1977_Raytheon_Digital_Low Power_Schottky 1977 Raytheon Digital Low Power Schottky

User Manual: 1977_Raytheon_Digital_Low-Power_Schottky

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TOTAL
WW·POWER SCHWiTKY
9LS/25LS/54LS/74LS

[RAYTHEON]
SEMICONDUCTOR DIVISION
350 Ellis Street, Mountain View, California 94042
(415) 968-9211, TWX: 910-379-6481

Raytheon cannot assume responsibility for use of any circuitry described other than circuitry entirety embodied in a Raytheon product. No other circuit patent licenses

are implied. Raytheon reserves the right to change said circuitry at any time, without notice. All AC spec~ications are based on the knowledge at the time of publication.
A~hough every effort has been made to insure the accuracy of the information contained in this catalog, Raytheon assumes no rasponsibility for inadvertent errors.

TABLE OF CONTENTS

PAGE
INTRODUCTION
General Description.
Circuit Characteristics.
Input Characteristics .
Output Characteristics.
Orderi ng Information .
Quality and Reliability
Definition of Letter Symbols and Terms.

ii
iii
iii
v
xvi

SECTION 1. SELECTION GUIDE TO DIGITAL PRODUCTS
9LS/54LS/74LS Low-Power Schottky . . .
Beam Lead Low-Power Schottky. . . . . .
25LS High-Performance Low-Power Schottky.
Standard TTL 2's Complement Multipliers.
54/74 SSI Series.
54/74 MSI Series.
8200 MSI Series.
930 DTL Series .
RA Y I and II Series TTL.
RAY III Series TTL. . .

1-2
1-4
1-5
1-5
1-6
1-7
1-8
1-9
1-10
1-15

SECTION 2. 9LS/54LS/74LS LOW·POWER SCHOTTKY
LSOO
LSOl
LS02
LS03
LS04
LS05
LS08
LS09
LS10
LS11
LS12
LS13
LS14
LS15
LS20
LS21
LS22
LS26
LS27
LS28
LS30
LS32
LS33
LS37
LS38
LS40
LS42
LS43
LS44
LS51
LS54
LS55

ii

Quad 2-input NAND gate. . . . . . .
Quad 2-input NAND gate, open collectors
Quad 2-input NOR gate, open collectors.
Quad 2-input NAND gate, open collectors
Hex inverter. . . . . . . . . . .
Hex inverter, open collectors . . . .
Quaq,?;,i[1p.M,t AN[) gate... . . .
Quad'.2:;f6pt.1~aNlD9'~te,6pe'ri collectors
Trip~3~\'fi3utfi\iAND,gatei:. . , . .
Trip~ll~jjatljA;Nl1igilte>:. ; . . . .
Trip!:lJi'a-iMputlNlPlND gate,i,open collectors
Duaf 4-it!PlJIl.'Sil!:lrflLtttrigger. . . . . .
Hex'Schn'\i:fr:Migge'r~'i: " . . . . . . .
Triple 3.inP14 A'¥P~gate. open collectors "
Dual4-input I\I:AN;Q gate, . . . . . . .
DuaJA-input,ANO'g.at!1.......;
Dual 4-inpufNANb' gate; 'open collectors.
Quad 2-input NAND, open collector 15V.
Triple 3-input NOR gate .
Quad 2-input NOR buffer.
8-input NAND gate . . .
Quad 2-input OR gate . .
Quad 2-input NOR buffer, open collectors
Quad 2-input NAND buffer. . . . . .
Quad 2-input NAND buffer, open collectors.
Dual 4-input NAND buffer .
1-of-10 decoder. . . . . . .
Excess 3 to decimal decoder. .
Excess gray to decimai decoder.
Dual AOI gate . . . .
2-3-3-2-input AOI gate.
2-wide, 4-input AOI gate

,.
",

..
~

"
\':

,,:.,

",

.~\

2-2
2-4
2-6
2-4
2-2
2-4
2-7
2-9
2-2
2-7
2-4
2-10
2-10
2-9
2-2
2-7
2-4
2-14
2-6
2-15
2-2
2-17
2-18
2-15
2-18
2-15
2-19
2-19
2-19
2-22
2-22
2-22

TABLE OF CONTENTS (Continued)

PAGE
SECTION 2. 9LS/54LS/74LS LOW-POWER SCHOTTKY (Continued)
LS73
LS74
LS75
LS76

LSn
LS78
LS83A
LS85
LS86
LS90
LS91
LS92
LS93
LS95B
LS107
LS109
LS112
LS113
LS114
LS122
LS123
LS125
LS126
LS132
LS136
LS138
LS139
LS151
LS152
LS153
LS155
LS156
LS157
LS158
LS160
LS161
LS162
LS163
LS164
LS170
LS174
LS175
LS181
LS190
LS191
LS192
LS193
LS194A
LS195A
LS196
LS197
LS221
LS251
LS253

~YTHE~

Dual J-K flip·flop. . .
Dual D flip-flop. . . .
Quad transparent latch.
Dual J-K flip·flop. . .
Quad transparent latch.
Dual J-K flip-flop. . .
4-bit full adder. . . .
4-bit magnitude comparator.
Quad exclusive OR gate
Decade cou nter . . .
8-bit shift register. .
Divide by 12 counter
4-bit binary counter.
4-bit shift register.
Dual J-K flip-flop. .
Dual J-K flip-flop. .
Dual J-K edge-triggered flip-flop
Dual J-K edge-triggered flip-flop
Dual J-K edge-triggered flip-flop
Retriggerable one-shot. . . .
Dual one~hot . . . . . . .
Quad 3-state buffer, low enable
Quad 3-state buffer, high enable
Quad 2-input Schmitt trigger 13-input NAND gate
Quad exclusive OR gate, open collectors
3-to-8 decoder/demultiplexer . .
Dual 2-to-4 decoder/demultiplexer
8-to-1 line multiplexer.
8-to-1 line multiplexer . . . . .
Dual 4-to-1 multiplexer. . . . .
Dual 2-to-4 decoder/demultiplexer
Dual 2-to-4 decoder/demultiplexer open collectors
Quad 2-to-1 line multiplexer
Quad 2-to-1 line multiplexer, inverting.
Decoder counter, asynchronous clear
Binary counter, asynchronous clear
Decade counter, synchronous clear
Binary counter, synchronous clear
8-bit shift register (SIPO). . . .
4 X 4 register file, open collectors.
Hex D-type flip-flop
Quad D-type flip-flop . . . . .
4-bit arithmetic logic unit
BCD decade counter, mode control
4-bit binary counter, mode control
BCD decade counter, up/down.
4-bit binary counter, up/down.
4-bit R shift register. . . . .
4-bit parallel shift register
4-bit presettable decade counter
4-bit presettable binary counter
Dual one-shot (very stable) . .
8-to-1 line multiplexer with tri-state-outputs
8-to-1 line multiplexer with tri-state-outputs

2-24
2-28
2-30
2-24
2-30
2-34
2-36
2-38
2·42
2-44
2-51
2-44
2-44
2-55
2-24
2-58
2-24
2-24
2-34
2-60
2-60
2-64
2·64
2-66
2-70
2·72
2·72
2-75
2-75
2-78
2·80
2-80
2-83
2-83
2-86
2-86
2-86
2-86
2-93
2-96
2-100
2-100
2-103
2-110
2-110
2-119
2-119
2-127
2-130
2-133
2-133
2-138
2-143
2-146

iii

TABLE OF CONTENTS (Continued)
PAGE
SECTION 2. 9LS/54LS/74LS LOW-POWER SCHOTTKY (Continued)
LS255
LS257
LS258
LS261
LS266
LS279
LS283
LS295A
LS298
LS365
LS366
LS367
LS368
LS386
LS395A
LS670

Dual 2·to-4 decoder/demultiplexer with tri·state outputs
Quad 2·to- 1 line multiplexer with tri-state outputs
Quad 2-to-l line multiplexer with tri-state outputs
2 X 4 binary multiplier. . . . . . . .
Quad exclusive NO R gate, open collectors
Quad set/reset latch. . . . . . . . .
4·bit full adder, fast carry (rotated LS83).
4·bit shift regjster with tri-state outputs
Quad 2-multiplexer with output register
Hex buffer, tri-state, common enable .
Hex inverter, tri·state, common enable.
Hex buffer, tri·state, 4-bit and 2-bit
Hex inverter, tri-state, 4-bit and 2-bit
Quad exclusive OR gate .
4-bit shift register, tri-state . . . .
4 X 4 register file, tri-state . . . .

2-148
2-150
2-150
2-154
2-70
2-157
2-36
2-159
2-161
2·163
2·163
2·163
2-163
2-42
2-165
2-168

SECTION 3. 25LS HIGH-PERFORMANCE LOW-POWER SCHOTTKY
25LS14
8-bit serial/parallel two's complement multiplier.
25LS15
Quad serial adder/subtractor. . . . . . . . .
25LS22
8-bit serial/parallel register with sign extender. .
25LS23
8-bit shift/storage register with synchronous clear
25LS122 Single retriggerable monostable multivibrator with clear
25LS123 Dual retriggerable monostable multivibrator with clear
25LS138 3-to-8 line decoder/demultiplexer. . .
25LS139 Dual 2-to-4Iine decoder/demultiplexer.
25LS151 8-to-l line multiplexer, compl. outputs.
25LS153 Dual 4-to-l line multiplexer. . . . .
25LS157 Quad 2-to-l line multiplexer . . . . .
25LS158 LS157, inverting . . . . . . . . .
25LS160 BCD decade counter, asynchronous clear.
25LS161 4-bit binary counter, asynchronous clear.
25LS162 BCD decade counter, synchronous clear
25LS163 4-bit binary counter, synchronous clear
25LS170 4 x 4 register file with open collectors.
25LS174 Hex D-type flip-flop with clear. . . .
25LS175 Quad D-type flip-flop with clear . . .
25LS181 4-bit arithmetic logic unit . . . . . .
25LS190 BCD decade up/down counter, synchronous.
25LS191 4-bit binary up/down counter, synchronous.
25LS192 BCD decade up/down counter, synchronous.
25LS193 4-bit binary up/down counter, synchronous.
25LS194A 4-bit bidirectional universal shift register. .
25LS195A 4-bit parallel access shift register . . . . .
25LS251 8-to-l line multiplexer with tri-state outputs
25LS253 Dual 4-to-l line data selectors/multiplexers with tri-state outputs
25LS257 Quad 2-to-l line multiplexer with tri-state outputs
25LS258 Quad 2-to-l line multiplexer with tri·state outputs
25 LS299 8-bit universal shift/storage register. .
25LS670 4 x 4 register file with tri-state outputs

3-2
3-6
3-10
3-15
3-18
3-18
3-21
3-21
3-24
3-26
3-28
3-28
3-30
3·30
3-30
3-30
3-38
3-42
3-42
3-44
3-50
3-50
3-58
3-58
3-66
3-66
3-73
3-75
3-79
3-79
3-83
3-86

SECTION 4. PACKAGING INFORMATION
Plastic Packages, DIP .
Metal Package, DIP. .
Ceramic Packages, DIP.
Ceramic Packages, Flat
Metal Packages, Flat. .
Beam Lead Mechanical Drawings.

4-2
4-2
4-3
4-4
4-5
4-6

iv

~YTHE@J

Introduction
GENERAL DESCRIPTION
The Raytheon Low-Power Schottky TTL family utilizes advanced process technology, Schottky-barrier clamping, shallow diffusions, higher sheet resistivity and small geometries
resulting in lower parasitic capacitance to achieve speeds
comparable to 5400/7400 at one-fifth the power and 54H
at one-tenth the power. The Raytheon TTL family is completely compatible with most of the popular TTL and
DTL logic families and is equivalent in performance to the
9LS series.

• High fan-out.
• Schottky-diode-clamped inputs minimize high-speed
termination effects.
• Low output impedance gives low noise susceptibility,
high capacitance drive capability.
• Power disSipation remains relatively low at operating
frequencies up to 30 MHz.
• Smaller, lower-cost power supplies and cooling equipment.
ABSOLUTE MAXIMUM RATINGS
.

7V

Raytheon Schottky Diodes are produced by depositing
platinum over the collector and base contact openings of
Schottky transistors. A protective layer of Titanium/
Tungsten alloy is deposited by a high-energy sputtering technique over the wafers. An alluminum layer is deposited and
the interconnect pattern is etched-out during the final
operation.

Supply Voltage, Vee (See Note 1)
Input Voltage (See Notes 1 and 2)
Interemitter Voltage (See Note 3)
Output Voltage (See Notes 1 and 4).
Operation Free-Air Temperature
Range:. . . . . . . .
Storage Temperature Range.

The tri-metal sandwich produced is one of the most rei iable
metalization systems available in the industry.

NOTES:
1. Voltage values, except interemitter voltage, are with respect to

Raytheon has extensive experience in tri-metal metalization.
For years similar techniques were used when producing trimetal systems for the fabrication of Beam Lead devices.
FEATURES

7V

5.5V
7V

_55°C to +125°C
_65°C to +150°C

network ground terminal.

2. Except 54LS74, 109, 181, 196, 197. For 54LS74, 109, 181,
196,197 rating is 5.5V.
3. This is the voltage between two emitters of a multiple-emitter
transistor.
4. This is the maximum voltage which should be applied to any
open-collector output when it is in the off state.

• High speed, Low-power
• 5 nsec typical gate' propagation delay time_
• 2 mW typical gate power dissipation at 50% duty cycle.
Table I compares Raytheon's Low-Power Schottky to the
other TTL technologies.

CIRCUIT CHARACTERISTICS
Dynamic Characteristic

Ease of System Design
• Switching times virtually insensitive to power supply,
temperature variations.
• Low noise generation.

The average propagation delay time is relatively insensitive
to variations of power supply voltage and temperature. Figure 1 shows typical propagation delay of a gate versus temperature with two different capacitive loads.

TABLE I
SPEED 'POWER COMPARISON FOR TTL TECHNOLOGIES
Series
Low-Power
Schottky

54LS (Ray)
54LS/74LS (T.I.)

Schottky

54S/74S

Standard

54/74

Other

~YTHE03J

154H/74H
54L/74L

Avg. Gate
Propagation Delay

Avg. Power
Per Gate

Speed-Power
Product

5 ns
10 ns

2mW
2mW

3'ns

20mW

60 PJ

10 ns

10mW

100 PJ

6 ns
33 ns

23mW
lmW

138 PJ
33 PJ

10 PJ
20 PJ

v

54 LSOO

CL= 50 pF

Vee = 5.0V

11

54S
10

r-- r--

50 pF

9

5400

8
Vee = 5.0V

7

o

RL = 2kSl

o

1=
+

54LS

6
N

15pF

r-- t=.

5
4

(20 nsec/division)

3

Figure 3. VCC Current Spiking Raytheon 54LS, 54S, 5400
Comparison

2
1
-55°e

0

-150 e

+25 e

+650 e

TEMPERATURE IN °c

+105"e

Figure 1. Propagation Delay Change With Temperature
The Raytheon LS family typically has 2 mW per gate
power dissipation at 50% duty cycle, nearly constant to fre·
quencies up to 5 MHz. PD increases to 8 mW per gate at
30 MHz. Figure 2 shows the dynamiC power dissipation at
various frequencies for three different loading configurations.
20

~

.5

A voltage higher than VOH min should be maintained on the
unused inputs of positive AND/NAND gates during dynamic
testing. This will eliminate the distributed capacitance associated with the floating inputs, band wire, and package lead,
and ensure that no degradation will occur in the propagation delay times. In addition to the circuits mentioned in
Note 2, all Raytheon LS devices employ a DTL input circuitry with Schottky diodes. The unused inputs may be
connected directly to Vee.

INPUT CHARACTERISTIC
Schottky barrier diode clamping minimizes the high sp.eed
termination effects previously associated with TTL devices.
Figure 4 shows input clamp diode voltage versus input current.

15

Voltage (V)

w

-10

I-

o

«
!2.
a:
w

s:0

l] l.,rx

-4

.

E

...

-8 t -

2,

5,

10,

20, 30, 40,

FREQ (MHz) UNUSED INPUT AT 5.0V

~

"

tl

J...

,

~H~ _~ ; :. .

t:

.1,.2, .5, 1,

1~I~uk~
,

o

~

r~ ~ k

~

0..

-12

Figure 2. Dynamic Power Dissipation

-16

With its advanced circuit technology, Raytheon LS devices
have inherently low power dissipation and current spiking
on the Vee line during transitions. Far less than in standard TTL or high-power Schottky circuits. This advantage
increases the "dynamic noise" margin of the overall system designed with 54LS. Figure 3 shows the Vee spikes
of Raytheon LS and standard 5400 and 54S circuits.

-20

vi

-05

j

'" r-•• to,· f- f-+«

H

I

III I

li~ I,
I'

lL

J

i
f

Figure 4. Clamp Diode Voltage Versus Input Current

t;YTHE~

OUTPUT CHARACTERISTIC
Figures 5 and 6 shol/¥ the typical sinking capability of Raytheon Low-Power Schottky devices and the V,N vs. VOUT
curves over the full military temperature range. As shown
in the curves, Raytheon LS devices can be guaranteed with
IOL ot ff.o mA at VOL of 0.45V max. and also high output
fan-out of 22 over the full military temperature range.

5



25

I +125"C +25°6

>

5

-

~

0

.1

1/

~r

5
?

+125"C
V~C

o

= 5.0 VOLTS

1.0

.5

0.5
1.0
1.5
2.0
2.5
Y,N -INPUT VOLTAGE_V

Figure 5. Typical Output vs. Input Voltage Characteristic

OUTPUT VOLTAGE VOL(V)

Figure 6

Ordering Information

Package Descriptions
BD

14-Pin Epoxy-B DIP

DB

14-Pin Epoxy-B DIP

L

16-Pin Metal Flatpak

BM

16-Pin Epoxy-B DIP

DC

14-Pin Ceramic DIP

16-Pin Epoxy-B DIP

CJ

14-Pin Ceramic Flatpak

DM

16-Pin Ceramic DIP

MB
MP

CK
CL

14-Pin Ceramic Flatpak
16-Pin Ceramic Flatpak

J
DP

14 or 16-Pin Ceramic DIP
14-Pin Epoxy-B DIP

R

24-Pin Ceramic DIP

N

CN

24-Pin Ceramic Flatpak
14-Pin Metal DIP

K

TO-3 Power Pack

W

24-Pin Glass/Metal Flatpak
14-Pin Ceramic Flatpak

D

~YTHEOEl

16-Pin Epoxy-B DIP

vii

Ordering Information
Low Power Schottky
54

930 DTL Series
LS153

/883B

25 Com'l 0 to +75°C
25 Mil -55 to +125°C
54
-55to+125°C
74
0 to +75°C

CJ

Function - - - - - - - - - - - - '
Package Type - - - - - - - - - - - - - - - - '

Function-----------.-...J
Package Type - - - - - - - - - - - - - '

CH

930

Temperature Range-----1T
RC
0 to +70 oC
RM -55 to +125°C

Temperature Range-----1T

W

RM

RAY I, II and III TTL Series

Ceramic DIP
Ceramic Flatpak
Gold-backed chip, visually inspected
to MIL-STD-883A, method 2012,
and packaged in waffle pack.

RFll

F,,,,,,

T

I
2

CJ

Temperature Range - - - - - - - - - - '
Optional Processing to MI L-STO-883A, Level 8 - - - - - - '
Notes:

1. 54LS orders will be branded 54LS
2. 9 LS orders will be branded 9 LS/54 LS or
9 LS/74 LS depending upon temperature range.
3. 25 LS orders will be branded 25 LS
4. For MIL-M·38510 device types, order by the
JAN part numbering system.

123

Package T y p e - - - - - - - - - - - - - - '

8200 MSI Series

54/7400 SSI and MSI Series
54

oor 1 -55 to +125°C
2 or 3 0 to +70 o C

/883B

RM

8200

OP

Temperature Range---...JT

Temperature Range----'T

54 -55 to +125°C
74 0 to +70 o C

RC
0 to +70 o C
RM -55 to +125°C

Function _ _ _ _ _ _ _ _--.-...J

Function-----------'

Package Type----_ _ _ _ _ _....J

Package T y p e - - - - - - - - - - - - - . . . J

W
CH

Ceramic DIP
Ceramic Flatpack
Gold-backed chip, visually inspected
to MI L·STD-883A, method 2012,
and packaged in waffle pack.

Optional Processing to MIL·STO·883A, Level B

viii

~YTHEO]J

Quality and Reliability
RAYACT-883A PROGRAM
The Rayth"on Acceptance Testing Program called Rayact-883A
IIlvolves In-process inspections which assure compliance with
MIL-STD-883A test methods and MIL-M-3851O Program Plan
Requirements.
Table 1 defines the Standard Process Flow for Raytheon
Semiconductor's Military Level Integrated Circuits. After
completion of the in-process inspections and 100% production
screens, each lot is subjected to a quality conformance inspection as defined in Table 2. The screening and acceptance

testlllg outlined in Tables 1 and 2 are provided at no extra cost.
In addition to the Standard Process Flow and acceptance testing, Qualification Tests in accordance with MI L-STD-883A,
Method 5005 are conducted every three months on each product line. Generic Summary Data of Groups A, B, and C
testing (Table 3) is available upon request.
The level of reliability you desire can be selected from Table 4.
These tests are conducted in accordance with Method 5004 of
MI L-STD-883A.

APPLICABLE DOCUMENTS:
Military: MI L-STD-883A
MIL-M38510
Raytheon Semiconductor:
Quality/Reliability Assurance Manual

Table 1-Standard Process Flow Summary for Integrated Circuits
MANUFACTURING OPERATION

MANUFACTURING INSPECTION

QUALITY /RELIABI L1TY
INSPECTION

Purchased Item Verification

Receiving Inspection To
Applicable M&SS and
Blueprint Number

Mask Making

Mask Inspection

Mask Inspection

Materials Preparation

Wafer Preparation and Epitaxial Growing

Photoengraving and Diffusion

Electrical Probe Check and 100%
Visual Inspection

a.c.
a.c.

Final Wafer Lot Acceptance

100% Visual Inspection

Q.C. Wafer Lot Acceptance

Electrical Test of Wafer

100% Electrical Test

Scribing and Dicing

Manufacturing Stores

Monitor
Monitor

100% Visual Inspection

a.c.
a.c.

Visual Die Sort
MIL.-STD-883A, Method 2010.2, Condition B

100% Die Sort Inspection

Dice Lot Acceptance

Die Attach

100% Visual Inspection

Lead Bond

100% Visual Inspection

Pre-Seal Inspection at 100X Magnification
MIL·STD-883A, Method 2010, Condition B

100% Visual Inspection at High-Power
Magnification

a.c.
a.c.
a.c.

Pre-Seal Inspection at 30X Magnification
MIL-STD-883A, Method 2010, Condition B

100% Visual Inspection at Low-Power
Magnification

t[AYTHE~

Monitor
Monitor

Monitor
Monitor
Lot Acceptance

Q.C. Lot Acceptance

ix

Quality and Reliability
Table 1-Standard Process Flow Summary for Integrated Circuits (Cont.)
MANUFACTURING INSPECTION

MANUFACTURING OPERATIONS

QUALITY IRE LIABILITY
INSPECTION

Final Seal

Visual and Hermeticity
100% Processing

a.c.
a.c.

Monitor

High·Temperature Bake
150 0 C ··24 Hours Minimum
IMI LSTD·883A, Method 1008, Condition C)
Temperature Cycling
-65 0 C to +150 0 C, 10 Cycles
IMI L·STD·883A, Method 1010, Condition C)

100% Processi ng

a.c.

Monitor

Centrifuge
30 KG Minimum Yl Axis
IMI L·STD·883A, Method 2001, Condition E)

100% Processing

a.c.

Monitor

Lead Form

100% Visual Inspection
100% Visual Inspection

a.c.
a.c.
a.c.

Monitor

Carrier Load

a.c.
a.c.

Monitor

Hermeticity
MILSTD·883A, Method 1014
External Visual

100% Inspection

Electrical Test and Sort

100% Inspection

Monitor

Monitor
Monitor

Monitor

Table 2-Quality Conformance Inspection (Each Lot)
INSPECTION

L TPD/MAX. ACC. NO.

External

7/2

Hermeticity

7/2

COMMENTS
M I L-STD-883A, Method 2009

Fine Leak

MI L-STD-883A, Method 1014, Condition A or B

Gross Leak

MI L-STD-883A, Mthod 1014, Condition C2

Electrical
Static Parameters

+25 0 C

5/1

+125 0 C

7/1

-55 0 C

7/1

+25 0 C

5/1

Dynamic Parameters +125 0 C
-55 0 C
Package and Ship

Per Applicable Electrical Test Specification

7/1
7/1
Quality Assurance Monitor

NOTE:
Generic Qualification Data in accordance with MI L-STD-883A, Method 5005, can be supplied if negotiated prior to procurement.

x

~YTHE@'J

Quality and Reliability
Table 3A-Group A Electrical Tests-MIL-STD-883A
CLASS A
LTPD

CLASS B
LTPD

CLASS C
LTPD

Subgroup 1
Static tests at 250C

5

5

5

Subgroup 2
Static tests at maximum rated operating temperature
Subgroup 3
Static tests at minimum rated operating temperature

5

7

10

5

7

10

Subgroup 4
Dynamic tests at 25 0 C
Subgroup 5
Dynamic tests at maximum rated operating temperature
Subgroup 6
Dynamic tests at minimum rated operating temperature

5

5

5

5

7

10

5

7

10

Subgroup 7
Functional tests at 25 0 C

3

5

5

Subgroup 8
Functional tests at maximum and minimum rated operating temperatures
Subgroup 9
Switching tests at 25 0 C

5

10

15

5

7

10

Subgroup 10
Switching tests at maximum rated operating temperature

5

10

15

Subgroup 11
Switching tests at minimum rated operating temperature

5

10

15

SUBGROUPS

NOTE:
The specific parameters to be included for tests in each subgroup shall be as specified in the applicable reliability specification. Where no
parameters have been identified in a particular subgroup or test within a subgroup. no group A testing shall be performed for that subgroup

or test to satisfy group A requirements.

Table 3B-Group B Tests, MIL-STD-883A, Method 5005
TEST

MI L-STD-883
METHOD

CONDITION

CLASS A

CLASS B

CLASS C

LTPD

LTPD

LTPD

Subgroup 1

Physical dimensions

2016

10

15

20

Subgroup 2

Resistance to solvents

2015

3 devices
(no failures)

3 devices
(no failures)

3 devices
(no failures)

Visual and mechanical

2014

Criteria from design and
1 device
construction requirements (no failures)
of applicable procurement
document

1 device
(no failures)

1 device
(no failures)

Bond strength

2011

Thermocompression
Ultrasonic or wedge
Subgroup 3
Subgroup 4

~YTHE~

Test condition C or 0
Test condition C or 0

5

15

20

10

15

15

10

15

15

Solderability

2003

Soldering temperature of
260 0 C ±100

Lead fatigue

2004

Test condition B2

Seal: Fine, Gross

1014

As appl icable

xi

1,

Quality and Reliability
Table 3C-Group C Tests, MIL-STO-883A, Method 5005
TEST

METHOD

MIL-STD-883A
CONDITION

CLASS A
LTPD

CLASS B
LTPD

CLASS C
LTPD

10

15

15

10

15

15

Subgroup 1 (Note 1)
Thermal shock
Temperature cycling
Moisture resistance
Seal
a. Fine
b. Gross (Note 7)
Visual examination (Note 2)
End point electrical parameters

1011
1010
1004
1014

Test condition B as a minimum.
Test condition C
As appl icable

As specified in the applicable
procurement document.

Subgroup 2 (Note 1)
Mechanical shock
Vibration, variable frequency
Constant acceleration
Seal
a. Fine
b. Gross (Note 7)
Visual examination (Note 3)
End point electrical parameters

2002
2007
2001
1014

Test condition B
Test condition A
Test condition E
As applicable

As specified in the applicable
procurement document.

Subgroup 3
Salt atmosphere (Note 4)
Visual examination (Note 5)

1009

Test condition A

10

15

15

1008

Test condition C
1000 hours.
As specified in the applicable
procurement document.

7

7

7

1005

Test condition to be specified
in the appl icable procurement
document (1000 hours).
As specified in the applicable
procurement document:

5

5

5

1005

Test condition A, 72 hours at
1500 C.
As specified in the applicable
procurement document_

7

-

-

Subgroup 4
High temperature storage (Note 6)
End point electrical parameters

Subgroup 5
Operating life test (Note 6)

End point electrical parameters

Subgroup 6
Steady state reverse bias
End point electrical parameters
NOTES:
1.

Devices used for environmental tests in subgroup 1 may be used for mechanical tests in subgroup 2.

2.
3.

Visual eXamination shall be in accordance with method 1010 or 1011 at a magnification of 5X to lOX.
Visual eXamination shall be performed at a magnification of 5X to lOX for evidence of defects of damage to case, leads,
or seals resulting from testing (not fixturing) such damage shall consitute a failure.
Electrical reject devices from the same inspection lot may be used for samples.
Visual examination shall be performed in accordance with 3.3.1 of method 1009.
See 40.4 of appendix B of MI L-M-38510.
When fluorocarbon gross leak testing is utilized, test condition C2 shall apply as minimum.

4.
S.
6.
7.

xii

~YTHE<3l

Quality and Reliability
Table 4-0ptional Screening-MIL-STD-883A, Method 5004
CLASS A
SCREEN

METHOD

CLASS B
REQUIREMENT

METHOD

REOliiR-C
MENT

r--------~-b.~~~
METHOD

REQUIREME NT

Internal visual (Precap)

2010
test condition A

100%

2010
test condition B

100%

2010
test condition B

100%

Stabilization bake

1008, 24 hrs.
test condition C,
1500 C

100%

1008, 24 hrs.
test condition C,
1500 C

100%

1008, 24 hrs.
test condition C,
1500 C

100%

Thermal shock

lOll,
test condition A,
00C-l000C
15 cycles

100%

Not required

Temperature cycling

1010
test condition C,
-65 0 C to +150 0 C
10 cycles

100%

1010,
test condition C,
-65 0 C to +150 0 C
10 cycles

Not required

100%

1010,
test condition C,
-65 0 C to +150 0 C
10 cycles

100%

Mechanical shock

2002**

100%

Not required

Constant Acceleration

2001,
test condition E
Y2 plane, then Yl
plane, 30,000 G's

100%

2001,
test condition E
Yl plane,
30,000 G's

100%

2001,
test condition E
Yl plane,
30,000 G's

100%

Seal
Fine,
Gross

1014,
Condition A
Condition C

100%

1014,
Condition A
Condition C

100%

1014,
Condition A
Condition C

100%

Hermetic devices
only

Not required

Hermetic devices
only

Hermetic devices
only
Not required

Critical electrical
parameters

*

100%

Go-No-Go

Burn-i n test

1015,240 hrs. @
TA = 1250C*

100%

1015,168 hrs. @
T A = 1250 C*

Critical electrical
parameters

*

100%

Not required

Not required

Reverse bias burn-in

1015,
test condition A
or C, 72 hrs. @
1500 C

100%

Not required

Not required

Final electrical test

*

100%

*

*

Static tests 25 0 C

100%

100%

Maximum and
minimum rated
operating temp.

100%

100%

100%

100%

100%

100%

Dynamic tests and
switching tests 25 0 C
Functional test 25 0 C
(subgroup 7, table 1,
5005)

Not requ ired

100%

100%

Group A Testing

Per Table 3A

Radiographic

2012

Qualification or
quality conformance
inspection
Groups Band C
optional, at extra cost

5005

.

5005

.

5005

.

External visual

2009

100%

2009

100%

2009

100%

Per Table 3A
100%

Not required

Per Table 3A
Not required

• Per applicable procurement document

~YTHEO]J

• *Test Condition F one shock pulse in Y 1 plane only or five shock pulses at Condition B in Y 1 plane only.

xiii

Quality and Reliability

Raytheon A + Program

Introduction
Raytheon's A+ program is designed to provide the Industrial and
Commercial marketplace with product reliability. - Reliability
consistent with application requirements. - Reliability that avoids
an overbuy situation where the user pays for screening beyond
the scope of his needs.

4. Pressure Cooker (epoxy packages only)
24 hours at +125°C in steam vapor, LTPD = 10. This RVT is performed on 25 samples from each EIA data code as to assure
package and device integrity.

5. 85/85 (epoxy packages only)
Raytheon offers three screening flows under the A+ program. Each
having a separate reliability factor and cost saving. When deciding
which A+ flow best suits your needs, you should consider the cost
savings realized through elimination of outside lab services and the
need to tighten incoming inspection. Users who do not presently
have their integrated circuits screened should consider the cost of
component replacement during system test and in the field. Substantial cost savings can now be realized by specifying Raytheon's
A+ program.
The designations A+l and A+2 are used for epoxy B packaged
devices only. A+3 is reserved for ceramic devices. The appropriate
screening level may be specified by simply adding the proper A+
suffix to the Raytheon part number, i.e., - - RC4136D B with A+2
screening would be designated RC4136DB2.

168 hours with bias at +8SoC and 85% relative humidity, STPD = 10.
This RVT is performed on 25 samples from each EIA date code
also as an indicator of package and device integrity.
6. Temperature Cycle (epoxy packages only)
100 cycles per method 1010.1, O°C to 100°C. This RVT is performed on 25 samples from each EIA date code to mechanically
stress the wire bond, die bond and package material.
7. Military Flow (ceramic packages and metal-cans)

Dnly dice lots which pass MI L-STD-883 condition B visual tests
are used in these packages and the 883 class B flow is used up
to point of electrical test. This provides military type product
reliability at commercial prices.

Customers who use the epoxy package may wish to obtain a copy
of the Epoxy Encapsulated Linear I.C. Quality Review, available
from your local Raytheon sales office.

Basic Reliability Measures
Raytheon has instituted an internal program to assure that products
bearing the Raytheon logo are unsurpassed in reliability when used
in the industrial environment. Several tests, including some normally
reserved for military products, are applied to our industrial products
on a continuing basis in support of this effort. A brief summary of
these tests is given below.

A+ Programs Increase Reliability
Raytheon's A+ programs were designed to provide an even greater
reliability assurance than standard process testing. Starting with
devices which are processed with the basic reliability measures,
various combinations of temperature cycle, burn-in, Hot Rail testing
and tightened AQL lot acceptance are available as shown in the flow
chart. The objectives of these 100% screens are:

1. Monitored Burn-In (all packages)

1. Temperature Cycle (epoxy packages only)

24 hours at +1 OOoC with zero failures allowed. This RVT (reliability
verification test), a Raytheon exclusive, is performed on 20 samples
from each manufacturing lot.

OoC to +1 OOoC per method 1011, condition A. This is the first
screening for the A+l and A+2 flows. (A+3 ceramic and metal-can
devices received temperature cycles as part of standard product flow.)
The purpose of this screening is to stress wire bonds and die bonds
mechanically to prove the integrity of the devices.

2. Standard Burn-In (all packages)

168 hours at +125°C, 1% PDA. This RVT is performed on 200
samples from each EIA data code.
3. Operating Life (all packages)
1000 hours at +125°C, LTPD = 5. This RVT is performed on all
new products and periodically on existing product types as an
indicator of long-term reliability.

xiv

2. Burn-In (all packages)

168 hours at +125°C. This screening is performed in A+2 and A+3
flows.
3. High Temperature Functional Test (Hot Rail)

(epoxy packages only)
+100 oC. This screening serves to further prove bond integrity.

t;VTHEO]J

A + Program Flow Chart

Quality and Reliability

I
I
I

DICE INVENTORY

I
DICE VISUAL INSPECTION

EPOXY B

I

I

I
DC"d

J

I

PRESEAL VISUAL INSPECTION

I

Mll·STD-Ba3A Method 2010.2 COrld"OOn a
100"10 by Mig ,lIld OA S,lmple

CERAMIC

ASS[MBlY

EPOXY B

I

I

I

J
J

I

I

Mll-STD-Ba3A Method 2010.2, Cond,"oll B
100% by Mig and QA Sample

CERAMIC

I

I
lOT ACg:PT ANCE

L
."

EPOXY B

TEMPCYClEO~'OO

I,

I

Mll-STD-Ba3A
Method lOla CondItIOn C
10 Cydes

TEMP CYCLE

I
DC,"d

;

FUNCTIONAL TESTS

J

I
I

I
J

UNBRANDED
INVENTORY

I

EPOXY B
C

B visual only)

I

sI

FUNCTIONAL TESTS

I

ICla~s

SEAL

I

I
QA
LOT ACCEPT ANCE

1

J
.,3

A+2

CERAMIC

TEMP CYCLE 0-1OO"C

I
BURN-IN 168 hrs@+125 C

I
DC TESTS@ +25 C

DC TESTS

(!!I

+25 C

BURN-IN 168hrs@+125C

MIL-STD-Ba3A
Method 1015
Conditione
168hrs

DC & FUNCTIONAL TESTS
@+25'C

I

HOT RAIL

FUNCTIONAL@+100"C

HOT RAIL
FUNCTIONAL@+100"C

LOT REJECTION POINT
l%PDA

LOT REJECTION POINT
1%PDA

BRAND

BRAND

I
I

QA LOT ACCEPTANCE
FUNCTIONAL@+25"C,0.15%AOL;
DC @ +25' C, 0.28% AOL;
DC@+75"C, 1.0% AOL;
AC@+25 C, 1.0% AOL

BRAND

I

QA

LOT ACCEPTANCE

FUNCTIONAL@+100°C,0.15% AOL;
DC@O°C, 1% AOL;
DC@+25°C, 0.28% AOL;
OC@+75°C, 1.0% AOl;
AC@+25°C, 1.0% AOl.

QA LOT ACCEPTANCE

FINE & GROSS LEAK, 0.4% AOL;
FUNCTIONAL @+25 C, 0.15% AOL
DC@OaC, 1.0% AOl;
DC @+25°C, 0.28% AOL;
DC@+75°C, 1.0% AOL;
AC@ +25~C, 1.0% AQL.

I
PACK

PACK

PACK

I
QA PLANT CLEARANCE VISUAL & MECHANICAL DOCUMENTATION, MIXING INSPECTION

t

SHIP
A<1
RELIABILITY FACTOR'" 1.5X
QUALITY GUARANTEE
ON FUNCTIONALITY", 0.15% AOL

•

t

SHIP

MajorDefect,@. 25% AOL
Minor Defects@ 1.0% AQL

SHIP

A+2

A+3

ax -

RELIABILITY FACTOR'"
lOX·
OUALITY GUARANTEE
ON FUNCTIONALITY"" 0.15% AQL

ReliABILITY FACTOR"" 15X
QUALITY GUARANTEE
ON FUNCTIONALITY"" 0.15% AOL

• Must be expressed as a range since a normally controlled environment (constant power and temperature) cannot be assured.

~YTHEO~

xv

DEFINITIONS OF SYMBOLS AND TERMS

These symbols, terms, and definitions are in accordance
with those currently agreed upon by the JEDEC Council
ofthe Electronic Industries Association (EIAI for use in the
USA and by the International Electrotechnical Commission (I ECI for international use_ The definitions are grouped
into sections applying to voltages, currents, switching characteristics, and classification of circuit complexity.

VO(ofl} Off-state output voltage
The voltage at an output terminal for a specified output
current with input conditions applied that according to
the product specification will cause the output switching
element to be in the off state.
Note: This characteristic is usually specified only for
puts not having internal pull-up elements.

out~

CURRENT
IIH

High~level

input current

The current flowing into* an input when a specified highlevel voltage is applied to that input.
IlL

VOLTAGES
V,H

VI l

High-level input voltage
An input voltage "level within the more positive (less
negative) of the two ranges of values used to represent
the binary variables. A minimum value is specified which
is the least-ppsitive (most-negative) value of high-level
input voltage for which operation of the logic element
withing specification limits is guaranteed.

Low·level input current

The current flowing into* an input when a specified low·
level voltage is applied to that input.
10H

High-level output current
The current flowing into* the output with a specified high·
level output voltage VOH applied.
Note: This parameter is usually specified for open-collector
outputs intended to drive other logic circuits.

low-level input voltage
An input voltage level within the less positive (more neg-

ative) of the two ranges of values used to represent the
binary variables. A maximum value is specified which is
the most-positive (least-negative) value of low-level input
voltage for which operation of the logic element within

specification limits is guaranteed.
VT+

10(011}
Off-state output current
The current flowing into* an output with a specified output voltage applied and input conditions applied that
according to the product specification will cause the out~
put switching element to be in the off state.

Positive-going threshold voltage
The voltage level at a transition·operated input that causes
operation of the logic element according to specification
as the input voltage rises from a level below the negative~
going threshold voltage, VT_.

Note: This parameter is usually specified for open-collec·
tor outputs intended to drive devices other than logic
circuits or for three-state outputs.
lOS

Short-circuit output current

Negative-going threshold voltage
The voltage level at a transition·operated input that causes
operation of the logic element according to specification
as the input voltage falls from a level above the positivegoing threshold voltage, VT+.

The current flowing 'Into"* an output when "that output
is short-circuited to ground (or other specified potential)
with input conditions applied to establish the output
logic level farthest from ground potential (or other specified potential).

VOH High-level output voltage
The voltage at an output terminal for a specified output
current 10H with input conditions applied that according to the product specification will establish a high level
at the output.

ICCH Supply current, output(s} high
The current flowing into* the Vce supply terminal of a
circuit when the reference outputls} is lare} at a highlevel voltage.

VT _

VOL

low-level output voltage
The voltage at an output terminal for a specified output
current IOL with input conditions applied that according
to the product specification will establish a low level at
the output.

VO(on} On-state output voltage
The voltage at an output terminal for a specified output
current with input conditions applied that according to
the product specification will cause the output switching
element to be in the on state.
Note: This characteristic is usually specified only for
puts not having internal pull~up elements.

xvi

ICCl Supply current, output Is} low
The current flowing into* the Vee supply terminal of a
circuit when the reference output(s) is (are) at a lowlevel voltage.

DYNAMIC CHARACTERISTICS
f max Maximum clock frequency

The highest rate at which the clock input of a bistable
circuit can be driven through its required sequence while
maintaining stable transitions of logic level at the output
with input conditions established that should cause a
change of output state with each clock pulse.

out~

*Current flowing out of a terminal is a negative value.

~YTHEO]J

DYNAMIC CHARACTERISTICS (continued)

Average pulse width
The time between 50-percent-amplitude points (or other
specified reference points) on the leading and trailing

tHZ

Output disable time (of a three-state output) from high
leV81
The time between the specified reference points on the

edges of a pulse_
thold Hold time

input and output voltage waveforms with the three~state

The time interval for which a signal or pulse is retained at
a specified input terminal after an active transition occurs
at another specified input terminal.

output changing from the defined high level to a highimpedance (off) state,
tLZ

Output disable time (of a three-state output) from low
level

The time between the specified reference points on the
input and output voltage waveforms with the three~state

output changing from the defined low level to a highimpedance (off) state,

trelease Release time
The time interval between the release from a specified
input terminal of data intended to be recognized and the
occurrence of an active transition at another specified
input terminal.
Note: When specified, the interval designated "release
time" falls within the setup interval and constitutes, in

tpLH Propagation delay time, low-to-high-Ievel output
The time between the specified reference points on the

effect, a negative hold time,

input and output voltage waveforms with the output

changing from the defined low level to the defined high
level.
tpHL Propagation delay time,

high~to-Iow-Ievel

tsetup

Setup time
The time interval for which a signal is applied and maintained at a specified input terminal before an active transition occurs at another specified input terminal.

tZH

Output enable time (of a three-state output) to high
level

output

The time between the specified reference points on the
input and output voltage waveforms with the output
changing from the defined high level to the defined low
level,

The time between the specified reference points on the
input and output voltage waveforms with the three-state

tTLH Transition time, low-to-high-Ievel output

output changing from a high-impedance (off) state to the
defined high level.

The time between a specified low-Ieve! voltage and a
specified high-level voltage on a waveform that is changing

from the defined low level to the defined high level,
tTHL Transisition time, high-to-Iow-Ievel output
The time between a specified high-level voltage and a
specified low-level voltage on a waveform that is changing
from the defined high-level to the defined low-level.

~YTHEO]J

tZL

Output enable time (of a three-state output) to low
level
The time between the specified reference points on the
input and output voltage waveforms with the three-state

output changing from a high-impedance (off) state to the
defined low level.

xvii

SECTION 1
Selection Guide To
Raytheon
Digital Products
CONTENTS

PAGE

9LS/54LSI74LS Low-Power Schottky.

1-2

Beam Lead Low-Power Schottky. . .

1-4

25LS High-Performance Low-Power Schottky.
Standard TTL 2's Complement Multipliers.

1-5

54174 SSI Series .

1-6

54/74 MSI Series.
8200 MSI Series .
930 DTL Series .
RAY I and" Series TTL.
RA Y "I Series TTL. . .

~YTHEO~

1-5
1-7

1-8
1-9
1-10
1-15

1-1

Digital Circuits
FEATURES
• High Speed, Low Power
• 5 ns typical gate propagation delay time
• 2 mW typical gate power dissipation at 50% duty cycle = speed-power product of 10pJ
• Ease of System Design
• Switching times virtually insensitive to power supply, temperature variations
• Low noise generation
• High fan-out
• Schottky-diode-clamped inputs minimize high-speed termination effects
• Low output impedance gives low noise susceptibility, high capacitance drive capability
• Power dissipation remains relatively low at operating frequencies up to 30 MHz
• Smaller, lower-cost power supplies and cooling equipment

9LS/S4LS/74LS Low Power Schottky
Type Number

Description

Prop Delayl
(ns) or Max.
Dp. Freq.
(MHz)2

Available Packages
Pwr
Diss.
(mW)

J

W

10
20
10
20
10

8
8
11
8
12

X
X
X
X
X

X
X
X
X
X

14 Pin

9 LS/54 LS/7 4 LSOO
9 LS/54 LSI7 4 LSO 1
9 LS/54 LS174 LS02
9 LS/54 LS174 LS03
9 LS/54 LSI7 4 LS04

Quad 2·input
Quad 2·input
Quad 2·input
Quad 2·input
Hex inverter

9 LS/54 LS174 LS05
9 LS/54 LS174 LS08
9 LS/54 LS174 LS09
9 LS/54 LS174 LS1 0
9 LS/54 LS174 LS11

Hex inverter, open collectors
Quad 2·input AND gate
Quad 2·input AND gate, open collectors
Triple 3·input NAND gate
Triple 3·input AN 0 gate

20
12
17.5
10
12

12
17
17
6
13

X
X
X
X
X

X
X
X
X
X

9 LS/54 LS174LS12
9 LS/54 LSI7 4 LS 13
9 LS/54LSI74LS14
9 LS/54 LS174 LS15
9 LS/54 LS174 LS20

Triple 3·input NAND gate, open collectors
Dual 4·input Schmitt trigger
Hex Schmitt trigger
Triple 3·input AN 0 gate, open collectors
Dual4·input NAND gate

20
20
20
17.5
10

6
60
60
13
4

X
X
X
X
X

X
X
X
X
X

9 LS/54 LS174 LS21
9 LS/54 LS174 LS22
9 LS/54 LS174 LS26
9 LS/54LS174LS27
9 LS/54 LS/74 LS28

Dual 4·input AND gate
Dual4·input NAND gate, open collectors
LS03, 15 volt outputs
Triple 3·input NO R gate
Quad 2·input NOR gate buffer

17.5
20
25
10
15

8.5
4
8
18
22

X
X
X
X
X

X
X
X
X
X

9 LS/54 LS/7 4 LS30
9 LS/54 LS/74 LS32
9 LS/54 LS/7 4 LS3 3
9 LS/54 LS/74 LS37
9 LS/54LS/74LS38

Single 8·input NAN 0 gate
Quad 2·inptu 0 R gate
LS28, open collectors
Quad 2·input NAND gate buffer
LS37, open collectors

13
11
30
15
30

2
20
22
17
17

X
X
X
X
X

X
X
X
X
X

9 LS/54LS174LS40
9 LS/54 LS/7 4 LS42
9 LS/54 LS/7 4 LS43
9 LS/54 LS/74 LS44
9 LS/54 LS/7 4 LS51

Dual4·input NAND gate buffer
1 of 10 decoder
Excess 3 to decimal decoder
Excess gray to decimal decoder
Dual 2·wide ADI

15
11 ns
11 ns
11 ns
13

9
35
35
35
5.5

X

X

1-2

NAND gate
NAND gate, open collectors
NO R gate
NOR gate, open collectors

1. Maximum at 25°C
2. Guaranteed minimum at 25°C

X

16 Pin

24 Pin

J

W

X
X
X

X
X
X

J

W

X

~YTHEO:EJ

Digital Circuits
9LS/S4LS/74LS Low Power Schottky (Cont.)

Type Number

Description

Available Packages

Prop Delay'
(ns) or Max.
Dp. Freq.
(MHz)2

Pwr
Diss.
(mW)

14 Pin
J

W

X
X
X
X

X
X
X
X

9 LS/54 LS/7 4 LS54
9 LS/li4 LS/74 LS55
9 LS/54 LS/74LS73
9 LS/54 LS/74LS74
9 LS/54 LS/74LS75

4·wide 2·3·3-2 input AD I
2-wide 4-input ADI
Dual J-K .flip-flop, negative edge trigger
Dual D·type flip-flop
Quad transparent latch

13
13
35 MHz
30 MHz
12

4.5
2.8
20
20
32

9 LS/54 LS/7 4 LS7 6
9 LS/54 LS/7 4 LS77
9 LS/54 LS/74 LS78
9 LS/54 LS/74 LS83A
9 LS/54 LS/7 4 LS8 5

Dual J-K flip-flop, preset and clear
Quad transparent latch
Dual J-K flip-flop, common clock and clear
4-bit binary full adder
4-bit magnitude comparator

35 MHz
10
35 MHz
18
20

20
33
20
96
52

9 LS/54 LS/74 LS8 6
9 LS/54 LS/74LS90
9 LS/54 LS/74 LS91
9 LS/54 LS/74 LS9 2
9 LS/54 LS/74 LS93

Quad 2-input exclusive DR gate
Decade Counter
8-bit shift register
Divide by 12 counter
4-bit binary counter

12
32
32
32
32

MHz
MHz
MHz
MHz

30
45
45
45
45

X
X
X
X
X

X
X
X
X
X

9 LS/54 LS/7 4 LS9 5B
9 LS/54 LS/7 4 LS 107
9 LS/54 LS/74 LSI 09
9 LS/54LS/74LSI12
9LS/54LS/74LS113

4-bit bidirectional shift register
Dual J-K flip-flop with clear
Dual J-K flip-flop, positive edge trigger
Dual J-K flip-flop, preset and clear
Dual J-K flip·flop with preset

30
35
30
35
35

MHz
MHz
MHz
MHz
MHz

65
20
20
20
20

X
X

X
X

X

X

9LS/54LS/74LS114
9 LS/54LS/74LSI22
9 LS/54 LS174 LS123
9 LS/54LS/74LS125
9 LS/54LS/74LSI26

Dual J-K flip-flop, common clock
Retriggerable one-shot
Dual one-shot multivibrator
Quad buffer with tri-state output
LS125. inverting

35 MHz
25
25
15
15

20
45
30
15
22

X
X
X
X
X

X
X
X
X
X

9 LS/54LS/74LSI32
9 LS/54LS/7.4LSI36
9LS/54LS/74LS138
9 LS/54 LS/7 4 LS 139
9 LS/54 LS/7 4 LS 151

Quad 2·input Schmitt trigger
LS86 with open collectors
3-to-8 line decoder/demultiplexer
Dual 2-to-4 line decoder/demultiplexer
8-to-l line multiplexer, compl. outputs

20
23
23
23
20

40
30
31
34
30

X
X

X
X

9 LS/54 LS/7 4 LS 15 2
9 LS/54 LS/7 4 LS 153
9LS/54LS/74LS155
9 LS/54 LS/74 LS156
9LS/54LS/74LS157

8-to·l line multiplexer
Dual 4-to-l line multiplexer
Dual 2-to-4 line decoder/demultiplexer
LS155, open collectors
Quad 2-to-l line mUltiplexer

20
15
40
40
15

34
31
30
31
49

X

9LS/54LS/74LS158
9LS/54LSmLSI60
9 LS/54 LS/7 4 LS 161
9LS/54LS/74LS162
9 LS/54 LS/7 4 LS 163

LS157, inverting
BCD decade counter, asynchronous clear
4-bit binary counter, asynchronous clear
BCD decade counter, synchronous clear
4-bit binary counter, synchronous clear

12
30
30
30
30

9 LS/54 LS/7 4 LS 164
9 LS/54LS/74LS170
9 LS/54 LS/7 4 LS 174
9 LS/54 LS/74 LS 17 5
9 LS/54 LS/7 4 LS 181

8-bit shift register
4 x 4 register file, open collectors
Hex D-type flip-flop
Quad D·type flip-flop
4-bit arithmetic logic unit

35 MHz
30
40 MHz
40 MHz
40

~YTHE€FJ

MHz
MHz
MHz
MHz

X
X

X

W

X

X

X

X

X
X

X
X

X
X

X
X

X
X
X

X
X
X

X
X
X
X

X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X

X
X
X

24 Pin
J

W

X

X

X
X

X

24
93
93.
93
93
80
25
80
55
102

16 Pin
J

X

1. Maximum at 25°C

2. Guaranteed minimum at 25°C

1-3

Digital Circuits
9LS/S4LS/74LS Low Power Schottky (Cont.)

Type Number

Description

Prop Delayl
(ns) or Max.
Op. Freq.
(MHz) 2

Available Packages
Pwr
Diss.
(mW)

9lS/54lS/74lS190
9lS/54lS/74lS191
9lS/54lS/7 4lS 192
9lS/54lS/74lS193
9lS/54lS174lS194A

BCD decade counter, mode control
4-bit binary counter, mode control
BCD decade counter, up/down
4·bit binary counter, up/down
4·bit bidirectional universal shift register

25 MHz
25 MHz
30 MHz
30 MHz
30 MHz

90
90
85
85
75

9lS/54lS/7 4lS 195A
9lS/54lS/7 4lS 196
9 lS/54lS/74lS197
9 lS/54lS/74lS221
9 lS/54lS/7 4lS251

4·bit parallel access shift register
4·bit presettable decade counter
4-bit presettable binary counter
Dual one-shot
lS151 with tri-state outputs

30 MHz
35 MHz
35 MHz
40
25

70
60
60
95*
35

9 lS/54lS/74lS253
9 lS/54lS174lS255
9lS/54lS/74lS257
9 lS/54lS/74lS258
9 lS/54lS174lS261

lS153 with tri-state
lS155 with tri·state
lS157 with tri-state
lS158 with tri-state
2 x 4 parallel binary

15
25
18
15
35

35
35
50
35
110

9 lS/54lS174lS266
9 lS/54lS/74lS279
9 lS/54lS174lS283
9 lS/54lS/74lS295A
9 lSI 54 lS/74lS298

Quad 2·input exclusive NOR open collectors
Quad latch
4·bit full adder, fast carry
lS95B with tri·state outputs
Quad 2 multiplexer with output register

20
27
18
30 MHz
16

40
12
96
70
65

9lS/54lS/74lS365
9lS/54lS/7 4lS366
9lS/54lS/74lS367
9 lS/54lS/74lS368
9lS/54lS/74lS375

Hex buffer (tri-state, common enable)
Hex inverter (tri·state, common enable)
Hex buffer (tri-state, 4 x 2 bit)
Hex inverter (tri·state, 4 x 2 bit)
Quad latch (rotated lS75)

15
15
15
15
12

68
60
68
60
32

9lS/54lS/74lS386
9 lS/54lS174lS395
9lS/54lS174lS670

Quad 2·input exclusive 0 R gate
4·bit shift register (tri·state)
4 x 4 register file (tri·state)

12
35 MHz
40

30
75
150

1. Maximum at 25°C

outputs
outputs
outputs
outputs
multiplexer

14 Pin

16 Pin

W

J

X
X

X

X

X

24 Pin

J

W

J

X
X
X
X
X

X
X
X
X
X

X

X

X
X

X
X

X
X
X
X
X

X
X
X
X
X

X
X

X
X

X

X

X
X
X
X
X

X
X
X
X
X

X
X

X
X

W

X
X

X

X

X

2. Guaranteed minimum at 25°C

Beam Lead Low Power Schottky Devices

'-4

layout

Die
Size
(Mils)

No. of
Beams

EIA

Mech.
Outline
Dwg.

Type

Description

54lS00Bl
54lS03Bl
54lS04Bl
54lS05Bl

Quad 2·input NAND gate
Quad 2·input NAND gate, open collector outputs
Hex inverter
Hex inverter, open collector outputs

45 x 45
45 x 45
45 x 45
45 x 45

16
16
16
16

X
X
X
X

9
9
9
9

54lS10Bl
54lS11 Bl
54lS15Bl
54lS153Bl
54lS253Bl

Triple 3·input NAND gate
Triple 3·input AN 0 gate
Triple 3-input AN 0 gate, open collector outputs
Dual 4·to-l line multiplexer
Dual4-to-lline mUltiplexer, tri·state output

45 x 45
45 x 45
45 x 45
55 x 55
55 x 55

16
16
16
20
20

X
X
X
X
X

9
9
9
12
12

Std.

~YJHEO]J

Digital Circuits
25LS High-Performance Low Power Schottky
Prop Delay I
(ns) or Max.
Dp. Freq.
(MHz)2

Type Number

Description

25LS14
25LS15
25LSn
25LS23
25LS138

8-bit serial/parallel mUltiplier
Quad serial adder/subtractor
8-bit serial/parallel register
8-bit shift/storage register
3-to-8Iine decoder/demultiplexer

40
40
70
50
12

25LS139
25LS151
25LS153
25LS157
25LS158

Dual 2-to-4Iine decoder/demultiplexer
8-to-l line multiplexer, compl. outputs
Dual 4-in-l line multiplexer
Quad 2-to-l line multiplexer
LS157, inverting

10
9
10
6
6

25LS160
25LS161
25LS162
25LS163
25LS170

BCD decade counter, async. clear
4-bit binary counter, async. clear
BCD decade counter, sync. clear
4-bit binary counter, sync. clear
4 x 4 register file, open collector

40
40
40
40
20

25 LS174
25LS175
25LS1B1 3
25LS190
25LS191

Hex D-type flip-flop
Quad D-type flip-flop
4-bit arithmetic logic unit
BCD decade counter, mode control
4-bit binary counter, mode control

50
50
12
35
35

25LS192
25LS193
25LS194A
25LS195A
25LS251

BCD decade counter, up/down
4-bit binary counter, up/down
4-bit bidirectional-universal shift register
4-bit parallel access shift register
LS151 with tri-state outputs

25LS253
25LS257
25LS258
25LS299
25LS670

LS153 with tri-state outputs
LS157 with tri-state outputs
LS158 with tri-state outputs
B-bit shift/storage register
LS170 with tri-state outputs

1. Maximum at 25°C
2. Guaranteed minimum at 25°C

Available Packages
Pwr.
Diss.
(mW)

14 Pin

W

455
240
200
190
31

X

X

X

X

34
30
31
40
24

X
X
X
X
X

X
X
X
X
X

MHz
MHz
MHz
MHz

93
93
93
93
125

X
X
X
X
X

X
X
X
X
X

MHz
MHz

80
55
102
90
90

X
X

X
X

X
X

X
X

35 MHz
35 MHz
40 MHz
40 MHz
9

B5
85
75
70
35

X
X
X
X
X

X
X
X
X
X

9
7
7
50 MHz
20

35
50
35
190
150

X
X
X

X
X
X

X

X

MHz
MHz
MHz
MHz

MHz
MHz

20 Pin

16 Pin

J

J

W

J

W

X
X
X

X
X
X

X

X

3. Available in 24-pin J or Wpackage.

Standard TTL 2's Complement Multipliers
Type Number
2505
2506

Description
4-bit by 2-bit 2's complement multiplier
4-bit arithmetic logic unit/function generator with output latch

Prop Delay!
(ns)

Pwr Diss.
(mW)

20
20

450
450

Available
Packages
N

R

X
X

X
X

1. Maximum at 25°C

~YTHE@J

'-5

Digital Circuits
54/74 SSI Series

1

Prop Delay
(ns) or Max.
Dp. Freq.
(MHz)

Type

Description

54/7400
54/7401
54/7403
54/7404
54/7405

Quadruple 2·input NAND gate
Quadruple 2·input NAN D gate, open collectors
Qupdruple 2·input NAND gate, open collectors
Hex inverter
Hex inverter, open collectors

10
22
22
10
22

54/7408
54/7409
54/7410
54/7411
54/7412

Quadruple 2·input AND gate
Quadruple 2·input AND gate, open collectors
Triple 3·input NAND gate
Triple 3·input AN 0 gate
Triple 3·input NAND gate, open collectors

54/7415
54/7420
54/7421
54/7422
54/7437

Triple 3·input AN D gate, open collectors
Dual 4·input NAN 0 gate
Dual 4·input AND gate
Dual 4·input NAND gate, open collectors
Quad 2·input NAND gate

54/7438
54/7474
54/7486
54/74136

Quad 2·input NAND gate, open collectors
Dual D·type flip·flop
Quad 2·input exclusive 0 R gate
54/7486 with open collectors

Pwrl
Diss.

Available Packages
14 Pin
DC

CJ

10
10
10
10
10

X
X
X
X
X

X
X
X
X
X

15
18.5
10
15
22

19
19.4
10
19
10

X
X
X
X
X

X
X
X
X
X

18.5
10
15
10

19.4
10
19
10
10

X
X
X
X
X

X
X
X
X
X

10
25 MHz
14
27

10
43
150
150

X
X
X
X

X
X
X
X

22

(mW)

Power dissipation is given for VCC = 5.0 volts. Propagation delays given are for the average path. Operating temperature range, 5400 Types:
-55°C to +125°C; 7400 Types: ooC to +70 oC.

1-6

~YTHE~

Digital Circuits
54/74 MSI Series
Prop Delay
(ns) or Max.
Dp. Freq.
(MHz)

Available Packages
Pwrl
Diss
(mW)

14 Pin

16 Pin

24 Pin

DC CJ

CL DO

N R

Type

Description

54/7442
54/7443
54/7444
54/7445
54/7483

BCD·to·Decimal Decoder
Excess 3·to·Decimal Decoder
Excess 3 Gray·to·Decimal Decoder
BCD·to·Decimal Decoder/Driver (30V Breakdown)
4·Bit Binary Full Adder

22
22
22
30
13

140
140
140
215
300

54/74123
54/74145
54/74150
54/74151
54/74152

Dual Retriggerable Monostable Multivibrator
BCD·to·Decimal recoder Driver (15V Breakdown)
16·to-l Line Data Selector/Multiplexer
8-to·l Line Data Selector/Multiplexer
8·to-l Line Data Selector/Multiplexer

21
30
11
11
11

230
215
200
145
130

54/74153
54/74154
54/74155

DuaI4-in-l Line Data Selector/Multiplexer
4-to-16 Line Decoder/Demultiplexer
Dual 2-to-4 Line Decoder/Demultiplexer

14
23
21

180
170
250

X X

54/74156
54/74157
54/74158
54/74159
54/74160

Dual 2-to-4 Line Decoder/Demultiplexer (Open CoiL)
Quad 2-to·l Line Data Selector/Multiplexer
Quad 2·to-l Line Data Selector/Multiplexer (lnv. Data)
4-to-16 Line Decoder/Demultiplexer (Open Call.)
BCD Decade Counter, Async. Clear

21
9
9
24
32 MHz

250
150
150
170
305

X X
X X
X X

54/74161
54/74162
54/74163
54/74164
54/74165

4·Bit Finary Counter, Async. Clear
BCD Decade Counter, Sync. Clear
4·Bit Binary Counter, Sync. Clear
8·Bit Parallel-Out Serial Shift Register (S.LP.O.)
Parallel-Load 8-Bit Shift Register (P.LS.O.)

32
32
32
36
26

MHz
MHz
MHz
MHz
MHz

305
305
305
167
210

X
X
X

54/74166
54/74170
54/74174
54/74175
54/74180

8-Bit Shift Register with Clear (P.I.S.O.)
4x4 Register File
Hex D·Type Flip-Flop
Quad D-Type Flip-Flop
9-Bit Odd/Even Parity Generator/Checker

35 MHz
20
35 MHz
35 MHz
32

360
625
225
150
170

54/74181
54/74182
54/74190
54/74191
54/74192

4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
BCD Decade Up/Down Counter
4-Bit Binary Up/Down Counter
BCD Decade Up/Down Counter (Dual Clock)

17
13
25 MHz
25 MHz
30 MHz

440
180
325
325
325

54/74193
54/74194
54/74195
54/74198
54/74199

4·Bit Binary Up/Down Counter (Dual Clock)
4-Bit Bidirectional Universal Shift Register
4-Bit Parallel Access Shift Register
8-Bit Right/Left Shift Register (P.LP.O.)
8-Bit Shift Register (P.LP.O.)

30
36
39
35
35

325
195
195
360
360

X X
X X
X X

54/74255
54/74283

54/7 4155 with 3·State Outputs
4·Bit Binary Full Adder with Fast Carry

21
13

250
300

X X
X X

MHz
MHs
MHz
MHz
MHz

X
X
X
X
X

X
X
X
X
X

X X
X X
X X
X X
X X
X X
X X

X X
X X

X

X
X
X

X
X X

X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X X

X X
X X

1. Power dissipation is given for VCC = 5.0 Volts. Propagation delays given are for the average path. Operating temperature range, 5400 Types:
-55°C to +125°C; 7400 Types: O°C to +70 oC.

~YTHE~

1-7

Digital Circuits
8200 MSI Series
Prop Delay
(ns) or Max.
Op. Freq.
(MHz)

Type

Description

RM/RC8TD9
RM/RC8T1D
RM/RC8T20
RM/RC82DO
RM/RC8201

Quad Bus Driver (Tri-State Outputs)
Quad D-Type Bus Flip-Flop (Tri-State Outputs)
Bidirectional One-Shot
Dual 5-Bit Buffer Register
Dual 5-Bit Buffer Register (Inv. Outputs)

16
50 MHz
30
35 MHz
35 MHz

235
250
250
400
400

RM/RC8202
RM/RC8203
RM/RC8230
RM/RC8231
RM/RC8232

10-Bit Buffer Register
10-Bit Buffer Register (Inv. Outputs)
8-lnput Multiplexer
8-lnput Multiplexer (Open Call. f Output)
8-lnput Multiplexer

35 MHz
35 MHz
11
13
11

400
400
184
184
172

RM/RC8233
RM/RC8234
RM/RC8235
RM/RC8241

2-lnput 4-Bit Multiplexer
2-lnput 4-Bit MUltiplexer (Open Call.)
Z-Input 4-Bit Multiplexer (Open Call.)
Quad Exclusive 0 R Gate

16
16
16
14

200
160
230
225

RM/RC8242
RM/RC8243
RM/RC8250
RM/RC8251
RM/RC8252

4-Bit Comparator (Open Call.)
8-Bit Positi on Scaler
Binary-to-Octal Decoder
BCD to Decimal Decoder
(9301) BCD to Decimal Decoder

14
25
20
20
20

170
315
125
135
135

RM/RC8260
RM/RC8261
RM/RC8262
RM/RC8263
RM/RC8264

Arithmetic Logic Element
Fast Carry Extender
9-Bit Parity Generator/Checker
3-lnput 4-Bit Multiplexer
3-lnput 4-Bit Multiplexer (Open Call.)

14
13
30
17
25

400
115
300
378
400

RM/RC8266
RM/RC82S7
RM/RC8270
RM/RC8271
RM/RC8273

2-lnput 4-Bit Multiplexer
2-lnput 4-Bit Multiplexer (Open Call.)
4-Bit Shift Register
4-Bit Shift Register
10-Bit Serial-In, Parallel-Out Shift Register

14
17
23 MHz
22 MHz
35 MHz

200
200
168
270
340

RM/RC8274
RM/RC8277
RM/RC8280
RM/RC8281
RM/RC8284

1O-Bit Parallel-In, Serial-Out Shift Register
Dual 8-Bit Shift Register
Decade Counter
4·8it Binary Counter
Binary Hex Synchronous Up/Down Counter

25 MHz
20 MHz
25 MHz
25 MHz
30 MHz

380
400
185
185
315

RM/RC8285
RM/RC8290
RM/RC8291

BCD Decade Synchronous Up/Down Counter
Presettable High Speed Decade Counter
Presettable High Speed Binary Counter

30 MHz
60 MHz
60 MHz

315
190
190

1

Available Packages

Pwrl
Diss
(mW)

14 rin

16 Pin

24 Pin

DP DC CJ DB Cl DO MB MP
X

N R

X
X
X

X
X

X

X
X X
X X
X X
X X

X
X
X

X
X
X

X
X
X

X

X

X

xl

X
X

X
X

X

X

X

X

X

X

X X
X
X

X

X
X X

X

X
X

X
X
X X
X X

X

X
X

X

X
X

X
X

X

X
X

X
X

X
X

X X
X X

X

X

X

X

X

X
X
X

X X
X X
X

X X
X X
X X

X
X X
X X

X

X

Power dissipation is given for VCC ~ 5.0 volts; propagation delays are given for the average path. Operating temperature range, RM Types:
_55°C to +125°C; RC Types: DoC to +70 oC.

1-8

~YTHEO]J

Digital Circuits
930 Senes DTL

TYPICAL CHARACTERISTICS
Available Packages

Description

Tpd (ns)
Avg. Pwr.
or
Toggle
Function
(mW)
Fanout Rate
Function (Min)
50% Duty

RM/RC930
RM/RC932
RM/RC933
RM/RC934
RM/RC935

Dual 4 NANDINOR gate with nodes 3
Oual.4 NANO/NOR buffer
Oual four expander
Hex Inverter 3
Hex Inverter 3

8
22
NA
8
8

30
40
NA
30
30

8.5/gate
28/gate
NA
8.5/gate
7/gate

0.5
0.5
NA
0.5
0.5

X
X
X
X
X

RM/RC936
RM/RC937
RM/RC940
RM/RC941

Hex
Hex
Hex
Hex

8
8
8
8

30
30
30
30

8:5/gate
8.5/gate
8.5/gate
8.5/gate

0:5
0.5
0.5
0.5

X
X
X
X

RM/RC944
RM/RC945
RM/RC946
RM/RC948
RM/RC949

Oual4 NANO/NOR power gate
Clocked Flip·Flop3
Quad two NAND/NOR gate 3
Clocked Flip·Flop4
Quad two NAND/NOR gate 4

25
9
8
9
7

27
52
30
50
25

22/gate
35
8.5/gate
40
8.5/gate

0.5
0.5
0.5
0.5
0.5

RM/RC950
RM/RC951
RM/RC957
RM/RC958
RM/RC961

8
9
22
25
7

30
50
40
27
25

22
35
28/gate
22/gate
8.5/gate

0.5

RM/RC962
RM/RC963
RM/RC988
RM/RC993
RM/RC994

Pulse triggered binary flip·flop
Monostable multivibrator
Quad 2 input buffers
Quad 2 NAND power gates
Dual 4 NAN D/N 0 R gate with nodes4
Triple three NANDINOR gate 3
Triple three NANDINOR gate 4
Monostable multivibrator
Dual RM945 3} separate clock, separate
Dual RM9484 direct set, no direct clear

8
7
10
9
9

30
25

8.5/gate
8.5/gate

-

-

52
50

RM/RC997
RM/RC999

Dual RM9484 } common clock, common
Dual RM945 3 direct clear, direct set

9
9

50
52

Type'
Number

Inverter 2
Inverter"
Inverter
Inverter

DC
Noise
Margin
(V)

14 Pin

.....
c.:>

CD

c.:> ....

cc cc
X
X

X
X
X

X
X
X
X
X

X
X
X X X

X

X

X
X
X
X

.....
X
X
X
X
X
X
X
X
X

X

X

X
X
X
X
X

X

X
X

0.5
0.5
0.5

X
X
X
X
X

X
X
X
X
X

X X X
X X X
X
X
X
X
X
X

70
80

0.5
0.5
1.0
0.5
0.5

X
X
X
X
X

X
X
X
X
X

X X X
X X X
X
X
X
X
X
X

80
70

0.5
0.5

X
X

X
X

X
X

-

X
X
X
X X X X X
X
X
X
X
X
X

X
X

NOTES
1.
2.
3.
4.

Operating temperature range; RM types: -55°C to +125°C; RC types: DoC to +75°C
Without collector pull-up resistor, Rc
6 Krl pull·up resistor
2Krlpull·up resistor

[§VTHEO]J

1-9

Digital Circuits
RAY I and II Series TTL
Type l
Number

Description

TYPICAL CHARACTERISTICS

Fanout
Function

Tpd (ns)
or
Toggle
Rate
(Min)

Avg. Pwr.
Function
(mW)
50% Duty

Available
Packages

DC
Noise
Margin

14 Pin

(V)

C3

... c ...c
:Ie:

RF30
RF31
RF32
RF33

Single phase SRT flip·flop
Single phase SRT flip·flop
J-K flip·flop (AND inputs)
J-K flip·flop (AN 0 inputs)

15
7
12
6

15 MHz
15 MHz
15 MHz
15 MHz

30
30
30
30

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF50
RF51
RF52
RF53

J-K flip·flop (AND inputs)
J-K flip·flop (AND inputs)
F-K flip·flop (AND inputs)
J-K flip·flop (AND inputs)

15
7
12
6

20
20
20
20

MHz
MHz
MHz
MHz

50
50
50
50

+1.1,-1.5
+1.1, -1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF60
RF61
RF62
RF63

J-K flip·flop
J-K flip·flop
J-K flip·flop
J-K flip·flop

15
7
12
6

20 MHz
20 MHz
20 MHz
20 MHz

55
55
55
55

+1.1,-1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF100
RF10l
RF102
RF103

Dual J-K flip·flop
Dual J-K flip·flop
Dual J-K flip·flop
Dual J-K flip·flop

(separate
(separate
(separate
(separate

clocks)
clocks)
clocks)
clocks)

11
6

35
35
35
35

MHz
MHz
MHz
MHz

55/flip·flop
55/flip·flop
55/flip·flop
55/flip·flop

+1.0, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RFll0
RFll1
RF112
RFl13

Dual
Dual
Dual
Dual

J-K flip·flop
J-K flip·flop
J-K flip·flop
J-K flip·flop

(common
(common
(common
(common

clock)
clock)
clock)
clock)

11
6

35
35
35
35

MHz
MHz
MHz
MHz

55/flip·flop
55/flip·flop
55/flip·flop
55/flip·flop

+1.0, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF120
RF121
RF122
RF123

Dual
Dual
Dual
Dual

J-K flip·flop
J-K flip·flop
J-K flip·flop
J-K flip·flop

(separate
(separate
(separate
(separate

clocks)
clocks)
clocks)
clocks)

11

50
50
50
50

MHz
MHz
MHz
MHz

55/flip·flop
55/flip·flop
55/flip·flop
55/flip-flop

+1.0, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF130
RF131
RF132
RF133

Dual
Dual
Dual
Dual

J-K flip-flop
J-K flip·flop
J-K flip·flop
J-K flip-flop

(common
(common
(common
(common

clock)
clock)
clock)
clock)

11
6

50
50
50
50

MHz
MHz
MHz
MHz

55/flip-flop
55/flip-flop
55/flip·flop
55/flip·flop

+1.0, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF200
RF201
RF202
RF203

J-K flip-flop
J-K flip-flop
J-K flip-flop
J-K flip·flop

(AND inputs)
(AN 0 inputs)
(AND inputs)
(AND inputs)

11
6

50 MHz
50 MHz
50 MHz
50 MHz

55
55
55
55

+1.0, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF210
RF211
RF212
RF213

J-K flip·flop
J-K flip·flop
J-K flip·flop
J-K flip-flop

(0 R inputs)
(0 R inputs)

11
6

(OR inputs)

9

(0 R inputs)

5

50
50
50
50

MHz
MHz
MHz
MHz

55
55
55
55

+1.0, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF250
RF251
RF252
RF253

J~K flip-flop (AND inputs)

J-K flip-flop (AN 0 inputs)
J-K flip-flop (AN 0 inputs)
J-K flip-flop (AND inputs)

30 MHz
30 MHz
30 MHz
30 MHz

50
50
50
50

+1.1, -1.5
+1.1, -1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RF260
RF261
RF262
RF263

J-K flip·flop
J-K flip-flop
J-K flip·flop
J-K flip·flop

30 MHz
30 MHz
30 MHz
30 MHz

55
55
55
55

+1.1,-1.5
+1.1,-1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

(0 R inputs)
(0 R inputs)

(DR inputs)
(DR inputs)

(OR inputs)
(0 R inputs)
(0 R inputs)
(0 R inputs)

9
5

9
5
6

9
5

9
5

9
5

11
6

9
5
11
6

9
5

1. Operating temperature range, final digits 0 or 1: -55°C to +125°C; final digits 2 or 3: OOC to +70°C.

1-10

t;YTHEO~

Digital Circuits
RAY I and II Series TTL (Cont.)
Type l
Number
RF9601
RF9602

Description
Retriggerable monostable multivibrator
(-55°C to +125°C)
Retriggerable monostable multivibrator
(O°C to +75°C)

Fanout
Function

Tpd (ns)
or
Toggle
Rate
(Min)

Avg. Pwr.
Function
(mW)
50% Duty

10 mA

25

100

+1.0, -1.5

12.8 mA

25

100

+1.0, -1.5

15
7
12
6

10
10
10
10

15/gate
15/gate
15/gate
15/gate

+1.1, -1.5
+1.1, -1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

15
7
12
6

12
12
12
12

30
30
30
30

+1.1,-1.5
+1.1,-1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

15
7
12
6

12
12
12
12

15
15
15
15

+1.1,-1.5
+1.1, -1.5
+1.1,-1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

15
7
12
6

12
12
12
12

20/gate
20/gate
20/gate
20/gate

+1.1,-1.5
+1.1,-1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

15
7
12
6

11
11
11
11

30/gate
30/gate
30/gate
30/gate

+1.1, -1.5
+1.1, -1.5
+1.1,-1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

15
7
12
6

11
11
11
11

35
35
35
35

+1.1,-1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

DC
Noise
Margin
(V)

14 Pin
... :.0:
(.)

(.)

(.)

c

c

X X X X

RG40
RG41
RG42
RG43

Dual 4 input
Dual 4 input
Dual 4 input
Dual4 input

RG50
RG51
RG52
RG53

Exp. 4-wide, 2-2-2-3
Exp. 4-wide, 2-2-2-3
Exp. 4-wide, 2-2-2-3
Exp. 4-wide, 2-2-2-3

RG60
RG61
RG62
RG63

Single 8 input
Single 8 input
Single 8 input
Single 8 input

RG70
RG71
RG72
RG73

Dual
Dual
Dual
Dual

2-wide, 2 input
2-wide, 2 input
2-wide, 2 input
2-wide, 2 input

RG80
RG81
RG82
RG83

Dual
Dual
Oual
Dual

pulse shaper/delay
pulse shaper/delay
pulse shaper/de!ay
pulse shaper/delay

RG90
RG91
RG92
RG93

Exclusive
Exclusive
Exclusive
Exclusive

RG100
RG10l
RG102
RG103

Exp. 3-wide, 3 input AOI gate
Exp. 3-wide, 3 input AOI gate
Exp. 3-wide, 3 input AO I gate
Exp. 3-wide, 3 input AOI gate

15
7
12
6

12
12
12
12

25
25
25
25

+1.1, -1.5
+1.1,-1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RGll0
. RGll1
RGl12
RGl13

Exp. 2-wide, 4 input AO I gate
Exp. 2-wide, 4 input AO I gate
Exp. 2-wide, 4 input AOI gate
Exp. 2-wide, 4 input AO I gate

15
7
12
6

12
12
12
12

20
20
20
20

+1.1, -1.5
+1.1,-1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG120
RG121
RG122
RG123

Expandable single
Expandable single
Expandable single
Expandable single

15
7
12
6

18
18
18
18

IS/gate
15/gate
151gate
IS/gate

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG130
RG131
RG132
RG133

Dual 4-input line
Oual 4 input line
Dual 4 input line
Dual 4 input line

30
30
24
12

15
15
15
15

30/gate
30/gate
30/gate
30/gate

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

tiAYTHE03J

NAND gate
NAND gate
NAND gate
NAN D gate

Available
Packages

TYPICAL CHARACTERISTICS

input AOI gate
input AO I gate
input AOI gate
input AOI gate

NANO gate
NAND gate
NAN D gate
NAND gate
AOI gate,
AOI gate,
AOI gate,
AO I gate,

one side expo
one side expo
one side expo
one side expo

AN D gate
AN D gate
AN D gate
AN D gate

0 R gate with complement
0 R gate with complement
0 R gate with complement
DR gate with complement

8 NAND gate
8 NAN D gate
8 NAN D gate
8 NAN D gate

driver
driver
driver
driver

1. Operating temperature range, final digits 0 or 1: -55°C to +125°C; final digits 2 or 3: O°C to +70o C.

,-"

Digital Circuits
RAY I and II Series TTL (Cont.)
Type l
Number

Descriptio
Description

RG140
RG141
RG142
RG143

Quad
Quad
Quad
Quad

2 input
2 input
2 input
2 input

RG150
RG151
RG152
RG153

4-wide,
4-wide,
4-wide,
4-wide.

RG160
RG161
RG162
RG163

Triple
Triple
Triple
Triple

RG170
RGl7l
RG172
RG173

2-wide,4 input
2-wide, 4 input
2-wide,4 input
2·wide,4 input

RG180
RG181
RG182
RG183

Dual4 input
Dual4 input
Dual 4 input
Dual4 input

RG200
RG201
RG202
RG203

Expandable single
Expandable single
Expandable single
Expandable single

RG210
RG211
RG212
RG213

Expandable
Expandable
Expandable
Expandable

RG220
RG221
RG222
RG223

Quad
Quad
Quad
Quad

NAN D gate
NAN D gate
NAN D gate
NAND gate

RG230
RG231
RG232
RGi33

4-wide,
4-wide,
4-wide,
4-wide,

RG240
RG241
RG242
RG243

Dual 4 input
Dual 4 input
Dual4 input
Dual 4 input

RG250
RG251
RG252
RG253

Expandable 4-wide,
Expandable 4-wide,
Expandable 4-wide,
Expandable 4-wide,

2-2-2-3
2-2-2-3
2-2-2-3
2-2-2-3

2 input
2 input
2 input
2 input

input
input
input
input

buss
buss
buss
buss

15
7
12

6

AD I expander
AD I expander
ADI expander
ADI expander

-

-

driver
driver
driver
driver

22
11
18

9

expander
expander
expander
expander

-

NAN D expander
NAND expander
NAN D expander
NAND expander

-

ADI
ADI
ADI
ADI

NAND
NAND
NAND
NAND

2-2-2-3
2-2-2-3
2-2-2-3
2-2-2-3

-

-

-

8 NAN D gate
8 NAN D gate
8 NAN D gate
8 NAN D gate

2-wide, 4 input
2-wide, 4 input
2-wide, 4 input
2·wide, 4 input

2 input
2 input
2 input
2 input

Fanout
Function

input
input
input
input

11

6
9
5

AD I gate
AD I gate
AD I gate
AD I gate

11
6

9
5

TYPICAL CHARACTERISTICS

Available
Packages

Tpd (ns)
or
Toggle
Rate
(Min)

Avg. Pwr.
Function
(mW)
50% Duty

10
10
10
10

15/gate
15/gate
15/gate
15/gate

+1.1,-1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

4
4
4
4

5/gate
5/gate
5/gate
5/gate

+1.1, -1.5
+1.1,-1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

15
15
15
15

15/gate
15/gate
15/gate
15/gate

+1.1,-1.5
+1.1,-1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

1
1
1
1

5/gate
5/gate
5/gate
5/gate

+1.1,-1.5
+1.1,-1.5
+1.1,-1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

1
1
1
1

1
1
1
1

+1.1,-1.5
+1.1, -1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

8
8
8
8

221gate

22/gate

+1.0, -1.5
+1.0, -1.:,5
+1.0, -1.5
+ 1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

7
7
7
7

30
30
30
30

+1.0,-1.5
+1.0, -1.5
+ 1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

8
6
6

22/gate
221gate
221gate

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

22/gate
221gate

DC
Noise
Margin
(V)

14 Pin

CJ~ c '-'
c

gate
gate
gate
gate

11
6

6

22/gate

+1.0,-1.5
+1.0,-1.5
+1.0, -1.5
+1.0, -1.5

AD I expander
AD I expander
ADI expander
ADI expander

-

2

-

2

-

2
2

7/gate
7/gate
7/gate
7/gate

+ 1.0, -1.5
+1.0,-1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

22/gate

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

9
5

-

NAND gate
NAN D gate
NAN D gate
NAN D gate
2-2-2-3
2-2-2-3
2-2-2-3
2-2-2-3

11
6

input
input
input
input

ADI
ADI
ADI
ADI

gate
gate
gate
gate

9

6
6
6

5

6

22/gate
22/gate

+1.0, -1.5
+1.0,-1.5
+1.0, -1.5
+1.0, -1.5

11
6

8
8
8
8

40
40
40
40

+1.0, -1.5
+1.0,-1.5
+1.0, -1.5
+1.0, -1.5

9
5

22/gate

1. Dperating temperature range, final digits 0 or 1: _55°C to +125°C; final digits 2 or 3: DoC to +70°C.

1-12

~YTHEO]J

Digital Circuits

.

RAY I an dliS enes TTL(C on t )

Type l
Number

Fanout
Function

Description

TYPICAL CHARACTERISTICS
Tpd (ns)
or
Toggle
Rate
(Min)

Avg. Pwr.
Function
lmW)
50% Duty

DC
Noise
Margin
(V)

Available
Packages
14 Pin

i3~Q

...
Q

11
6
9
5

8
8
8
8

22
22
22
22

+to, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

-

1
1
1
1

7/gate
7/gate
7/gate
7/gate

+1.0, -1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

11
11
11
11

38/gate
38/gate
38/gate
38/gate

+1.1, -1.5
+1.1, -1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

-

7
7
7
7

15/gate
15/gate
15/gate
15/gate

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

Expandable 3-wide, 3 input AO I gate
Expandable 3-wide, 3 input AO I gate
Expandable 3-wide, 3 input AO I gate
Expandable 3-wide, 3 input AO I gate

11
6
9
5

7
7
7
7

35
35
35
35

+1.0,-1.5
+1.0,-1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG310
RG311
RG312
RG313

Dual
Dual
Dual
Dual

11
6

7
7
7
7

30/gate
30/gate
30/gate
30/gate

+1.0, -1.5
+1.0, -1.5
+1.0,-1.5
+1.0,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG320
RG321
RG322
RG323

Triple 3 input
Triple 3 input
Triple 3 input
Triple 3 input

9
5

6
6
6
6

22/gate
22/gate
22/gate
22/gate

+1.0,-1.5
+1.0, -1.5
+1.0, -1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG370
RG371
RG372
RG373

Hex inverter
Hex ·inverter
Hex inverter
Hex inverter

15
7
12
6

10
10
10
10

15linverter
15/inverter
15/inverter
15/inverter

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG380
RG381
RG382
RG383

Hex
Hex
Hex
Hex

11
6

9
5

6
6
6
6

221inverter
22/inverter
22/inverter
22/inverter

+1.0, -1.5
+1.0, -1.5
+1.0,-1.5
+1.0, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG7510
RG7511
RG7512
RG7513

Quad 2 input line
Quad 2 input line
Quad 2 input line
Quad 2 input line

30
15
24
12

15
15
15
15

30/gate
30/gate
30/gate
30/gate

+1.1, -1.5
+1.1, -1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG7520
RG7521
RG7522
RG7523

Quad 2 input lamp driver
Quad 2 input lamp driver
Quad 2 input lamp driver
Quad 2 input lamp driver

15
15
15
15

30/gate
30/gate
30/gate
30/gate

+1.1,-1.5
+1.1,-1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RG260
RG261
RG262
RG263

Single 8 input
Single 8 input
Single 8 input
Single 8 input

RG270
RG271
RG272
RG273

2·wide, 4 input AOI
2·wide,4 input AOI
2·wide, 4 input AOI
2·wide,4 input AOI

RG280
RG281
RG282
RG283

Expandable dual4 input
Expandable dual 4 input
Expandable dual 4 input
Expandable dual 4 input

RG290
RG291
RG292
RG293

Dual
Dual
Dual
Dual

RG300
RG301
RG302
RG303

~YTHEO].J

NAND
NAND
NAND
NAND

gate
gate
gate
gate

expander
expander
expander
expander

-

-

AND gate
AN D gate
AN D gate
AN D gate

2 and 3 input AND/O R gate expo
2 and 3 input AND/OR gate expo
2 and 3 input AND/OR gate expo
2 and 3 input AND/O R gate expo

2-wide, 2 input
2-wide, 2 input
2-wide, 2 input
2-wide, 2 input
NAND
NAND
NAND
NAND

AO I gate,
AOI gate,
AOI gate,
AOI gate,
gate
gate
gate
gate

inverter
inverter
inverter
inverter
driver
driver
driver
driver

one side expo
one side expo
one side expo
one side expo

15
7
12
6
-

-

9
5

11
6

40 rnA
20mA
40 rnA
20 rnA

1. Operating temperature range, final digits 0 or 1: _55°C to +125°C; final digits 2 or 3: OOC to +70 oC

1-13

Digital Circuits

.

RAY I and II Series TTL (Cont )

Type I
Number

Description

Fanout
Function
10
10
10
10

adder
adder
adder
adder

TYPICAL CHARACTERISTICS

Available
Packages

Tpd (ns)
or
Toggle
Rate
(Min)

Avg. Pwr.
Function
(mW)
50% Duty

5 24 ns
S 12 ns
7 13 ns

90 mW
90 mW
90 mW
90 mW

+O.S, -1.4
+O.S, -1.4
+O.S, -1.3
+O.S, -1.3

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

5 25 ns
S 22 ns
7 13 ns

125 mW
125 mW
125 mW
125 mW

+O.S, -1.4
+O.S, -1.4
+O.S, -1.3
+O.S, -1.3

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

5 25 ns
S 22 ns
7 13 ns

125 mW
125 mW
125 mW
125 mW

+O.S, -1.4
+O.S, -1.4
+O.S, -1.3
+O.S, -1.3

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

r
r
r

DC
Noise
Margin
(V)

14 Pin
-.~

(.) (.)

c

(.)

c

RL10
RL11
RL12
RL13

Fast full
Fast full
Fast full
Fast full

RL20
RL21
RL22
RL23

Dependent carry fast adder
Dependent carry fast adder
Dependent carry fast adder
Dependent carry fast adder

10
10
10
10

RL30
RL31
RL32
RL33

Dependent carry fast adder
Dependent carry fast adder
Dependent carry fast adder
Dependent carry fast adder

10
10
10
10

RL40
RL41
RL42
RL43

Carry decoder
Carry decoder
Carry decoder
Carry decoder

10
10
10
10

RLSO
RLSl
RLS2
RLS3

4·bit storage register
4·bit storage register
4·bit storage register
4·bit storage register

11
11
11
11

25 ns
25 ns
25 ns
25 ns

175 mW
175mW
175 mW
17fi 1'1"'.'

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RL70
RL71
RL72
RL73

4·bit storage register
4·bit storage register
4·bit storage register
4·bit storage register

11
11
11
11

25 ns
25 ns
25 ns
25 ns

175mW
175mW
175 mW
175 MW

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

RL80
RL81
RL82
RL83

lS·bit scratch
lS·bit scratch
lS·bit scratch
lS·bit scratch

27
27
27
27

250
250
250
250

+1.1,-1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

pad
pad
pad
pad

memory
memory
memory
memory

S
S
6
S

},,'"'" 2

ns
ns
ns
ns

20
20
20
20

mW
mW
mW
mW

mW
mW
mW
mW

Expander
+0.7, -2.35
+0.7, -2.35
+0.7, -2.25
+0.7, -2.25

X X X X
X X X X
X X X X

1. Operating temperature range, final digits 0 or 1: -55°C to +125°C; final digits 2 or 3; O°C to +70°C.
2. Pin 5, A ~ 4.0 nS (add 1 All pfd)

'-14

~YTHE03J

Digital Circuits
RAY III Series TTL
Type l
Number

Description

Avg. Pwr.
Function
(mW)
50% Duty

11
10
11
10

75
75
75
75

MHz
MHz
MHz
MHz

55/FF
55/FF
55/FF
55/FF

+1.1, -1.5
+1.1,-1.5
+1.1,-1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

Fanout
Function

DC
Noise
Margin
(V)

Pins
14

RF3200
RF3202
RF3210
RF3212

AND input J-K flip-flop
AND input J-K flip-flop
DR input J-K flip-flop
OR input J-K flip-flop

11
10
11
10

75
75
75
75

MHz
MHz
MHz
MHz

55
55
55
55

+1.1, -1.5
+1.1,-1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RF3220
RF3222
RF3230
RF3232

Tr,iple latch flip-flop (sep. neg. edge clocks)
Triple latch flip-flop (sep. neg. edge clocks)
Dual D-type flip-flop
Dual D-type flip-flop

11
10
11
10

50
50
60
60

MHz
MHz
MHz
MHz

60/FF
60/FF
75/FF
75/FF

+1.1,-1.5
+1.1,-1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

RF3240
RF3242
RF3250
RF3252

Triple latch flip-flop (com. pas. edge clock)
Triple latch flip-flop (com. pas. edge clock)
5-channel selector flip-flop
5-channel selector flip-flop

11
10
11
10

50
50
50
50

MHz
MHz
MHz
MHz

70/FF
70/FF
150
150

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3180
RG3182
RG3200
RG3202

Dual4 input NAND gate expander
Dual4 input NAND gate expander
Expandable single 8 NAND gate
Expandable single 8 NAND gate

-

-

11
10

1
1
6.5
6.5

22
22

+1.1, -1.5
+1.1,-1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3210
RG3212
RG3220
RG3222

Expandable 2-wide, 4 input AO I gate
Expandable 2-wide, 4 input AO I gate
Quad 2 input NAND gate
Quad 2 input NAND gate

11
10
11
10

5.5
5.5
4.5
4.5

30
20
22/gate
22/gate

+1.1,-1.5
+1.1, -1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3230
RG3232
RG3240
RG3242

4-wide, 2-2-3-3 input AOI expander
4-wide, 2-2-3-3 input AOI expander
Dual 4 input NAN 0 gate
Dual 4 input NAND gate

-

11
10

2
2
4.5
4.5

7/gate
7/gate
22/gate
22/gate

+1.1,-1.5
+1.1, -1.5
+1.1,-1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3250
RG3252
RG3260
RG3262

Expandable 4-wide, 2-2-2-3 input AOI gate
Expandable 4-wide, 2-2-2-3 input AOI gate
Single 8 input NAND gate
Single 8 input NAND gate

11
10
11
10

6.0
6.0
5.5
5.5

40
40
22
22

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3270
RG3272
RG3300
RG3302

2-wide,4 input AOI expander
2-wide, 4-input AOI expander
Expandable 3-wide, 3 input AO I gate
Expandable 3-wide, 3 input AOI gate

-

11
10

1
1
6.0
6.0

7/gate
7/gate
35
35

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3310
RG3312
RG3320
RG3322

DuaI2-wide, 2 input AOI gate, one sideexp.
Dual 2-wide, 2 input AOI gate, one side expo
Triple 3 input NAND gate
Triple 3 input NAND gate

11
10
11
10

5.5
5.5
4.5
4.5

30/gate
30/gate
22/gate
22/gate

+1.1, -1.5
+1.1, -1.5
+1.1, -1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3380
RG3382
RG3390
RG3392

Hex inverter
Hex inverter
Dual 4 input AND gate, split outputs
Dual 4 input AND gate, split outputs

11
10
11
10

4.5
4.5
6.5
6.5

22/inverter
22/inverter
30/gate
20/gate

+1.1,-1.5
+1.1,-1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

-

-

-

-

24

.... :..:: co>:
'-'
,-,,-,c

Dual
Dual
Dual
Dual

_--_ I

(separate clocks)
(separate clocks)
(common clock)
(common clock)

Available
Packages

RF3120
RF3122
RF3130
RF3132

C'§YTHEO]J

J-K flip·flop
J-K flip-flop
J-K flip-flop
J-K flip-flop

TYPICAL CHARACTERISTICS
Tpd (ns)
or
Toggle
Rate
(Min)

Operating temperature range, final digit 0: -55°C to +125°C; final digit 2: O°C to +70°C.

1-15

Digital Circuits

.

RAY III Series TTL (Cont )

Type l
Number

I

Description

TYPICAL CHARACTERISTICS

Fanout
Function

Tpd (nsl
or
Toggle
Rata
(MinI

Avg. Pwr.
Function
(mWI
50% Duty

DC
Noise
Margin
(VI

Available
Packages
Pins
14

24
u

C3~CI CIa:

RG3400
RG3402
RG3410
RG3412

auad 2 input AND gate
auad 2 input AND gate
auad 2 input NOR gate
auad 2 input NO R gate

11
10
11
10

6.5
6.5
4.5
4.5

30/gate
30/gate
30/gate
30/gate

+1.1, -1.5
+1.1, -1.5
+1.1,-1.5
+1.1, -1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3420
RG3422
RG3430
RG3432

Dual 4 input NAND gate, split outputs
Dual 4 input NAND gate, split outputs
Single 8 input NAND gate, split outputs
Single 8 input NAND gate, split outputs

11
10
11
10

4.5
4.5
5.5
5.5

221gate
22/gate
22
22

+1.1, -1.5
+1.1,-1.5
+1.1, -1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RG3440
RG3442
RG3450
RG3452

Dual 2·wide, 2 input ADI gate, split outputs
Dual 2·wide, 2 input ADI gate, split outputs
4·wide, 2·2·3-4 input ADI gate
4·wide, 2·2·3-4 input ADI gate

11
10
11
10

5.5
5.5
5.5
5.5

30/gate
30/gate
40
40

+1.1, -1.5
+1.1, -1.5
+1.1,-1.5
+1.1,-1.5

X
X
X
X

X
X
X
X

X
X
X
X

RL3002
RL3100
RL3102

10·bit parity generator/checker
4·bit full adder
4·bit full adder

14
10
10

25 ns
15 ns
15 ns

325 mW
350
350

+1.1,-1.7
+1.4, -1.7
+1.4, -1.7

X
X
X

Operating temperature range, final digit 0: _55°C to +125°C; final digit 2: O°C to +70 oC.

1·16

~YTHEO~

SECTION 2
9 LS/54LS/74LS
Low-Power Schottky
CONTENTS

PAGE

CONTENTS

PAGE

LSOO
LS01
LS02
LS03
LS04
LS05
LS08
LS09
LS10
LS11
LS12
LS13
LS14
LS15
LS20
LS21
LS22
LS26
LS27
LS28
LS30
LS32
LS33
LS37
LS38
LS40
LS42
LS43
LS44
LS51
LS54
LS55
LS73
LS74
LS75
LS76
LS77
LS78
LS83A.
LS85
LS86
LS90
LS91
LS92
LS93
LS95B.
LS107.
LS109.
LS112.
LS113.
LSl14.

2-2
2-4
2-6
2-4
2-2
2-4
2-7
2-9
2-2
2-7
2-4
2-10
2-10
2-9
2-2
2-7
2-4
2-14
2-6
2-15
2-2
2-17
2-18
2-15
2-18
2-15
2-19
2-19
2-19
2-22
2-22
2-22
2-24
2-28
2-30
2-24
2-30
2-34
2-36
2-38
2-42
2-44
2-51
2-44
2-44
2-55
2-24
2-58
2-24
2-24
2-34

LS122 .
LS123.
LS125 .
LS126.
LS132 .

2-60
2-60
2-64
2-64
2-66

LS136 .
LS138 .
LS139 .
LS151 .
LS152 .
LS153.
LS155 .
LS156 .
LS157 .
LS158 .
LS160.
LS161 .
LS162.
LS163.
LS164.
LS170 .
LS174 .
LS175.
LS181 .
LS190.
LS191 .
LS192.
LS193.
LS194A
LS195A
LS196.
LS197 .
LS221 .
LS251 .
LS253 .
LS255 .
LS257 .
LS258 .
LS261 .
LS266 .
LS279 .
LS283 .
LS295A
LS298 .
LS365 .
LS366 .
LS367 .
LS368 .
LS386 .
LS395A
LS670 .

2-70
2-72
2-72
2-75
2-75
2-78
2-80
2-80
2-83
2-83
2-86
2-86
2-86
2-86
2-93
2-96
2-100
2-100
2-103
2-110
2-110
2-119
2-119
2-127
2-130
2-133
2-133
2-138
2-143
2-146
2-148
2-150
2-150
2-154
2-70
2-157
2-36
2-159
2-161
2-163
2-163
2-163
2-163
2-42
2-165
2-168

~YTHEO~

2-1

LSOOLS04
LS10 LS20 LS30

Positive-NAND Gates, Hex Inverters
PIN-OUT AND'LOGICDIAGRAMS

:LSOO
QUADRUPLE 2-INPUT NAN'D GATE

12

11

10

. . 11.,804
,
HEX INVERTER:

12

Vee 48 4A 4Y 38 3A 3Y

~tTtJ
3

4

2

ffi]~U~

£dJMMrn

lA IV 2A 2Y 3A 3Y GNO

3

Die Size .060 x .067

4

5

posHive logic: Y = A

Die Size .060 x .067

LS20,
DUAL 4-INPUT NAND GATE

1.S1II.
TRIPLE 3-INPUT NAND GATE

12 11

Vcc 6A 6Y SA 5Y 4A 4Y

9
8
7
6

lA 18 IV 2A 28 2Y GND
Positive logiC: Y = AB

5

10

13
14
1

W~

1
2

11

10

10

12

13
14
1

14
1

2

2
11\ 18 NC lC 10 IV GNO

3

4

posHive logiC: Y = ABC

5

Die Size .060 x .067

4

5

positive logic: Y = ABCD

Die Size .060 x .067

NC - No intemal connection
I-S30
II-INPUT NAND GATE

12 11

14
1
2

3

4

5

posHive logic: Y - ABCDEFGH

Die Size .060 x .067

2-2

~YTHEO:El

Positive-NAND Gates, Hex Inverters
Recommended Operating Conditions
9LS/54LS
Nom
Max

Min
4.5

Supply voltage, Vee

5

I High logic level

Normalized fan-out from each output, N

I Low logic level

-55

Operating free-air temperature, T A

5.5
20
10
125

Min

9LS/74LS
Max
Nom

4.75

5

0

5.25
20
20
70

Unit
V

°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions·

Parameter

9LS/54LS
Typ·· Max

Min

VIH

2

VIL
VI
VOH

Vee=MIN,

II
IIH
III
los

2

11--18mA

ov

leCH

9LS/74LS
Typ·· Mex

0.7
-1.5

Vee=MIN, Vll=VllmaX, loW-400!.lA, Vll =0.7V
Vee-MIN,
VIH-2V
llnl =4 mA
Jim =8 mA
VI=7.0V
Vee=MAX,
VI-2.7V
Vee-MAX,
VI=O.4V
Vee=MAX,
Vee-MAX,
Vee=MAX, All inputs at
I LSOO,04,10,20
{Per Gate}
I LS30
Vee=MAX,
All inputs at 4.5 {Per Gate}

Val

Min

2.5

3.4
0.25

15
0.2
0.35
0.6

0.8
1.5
2.7

0.4
0.1
20
-0.4
100
0.4
0.5

3.4
0.25
0.3

-15
0.2
0.35
0.6

0.4
0.45
0.1
20
-0.4
-100
0.4
0.5
1.1

Unit
V
V
V
V
V
V
mA
!.IA
mA
mA
mA

mA
1.1
leel
..
"For conditIons shown as MIN or MAX, use the approproate value specIfIed under recommendea operatIng conditIons for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.

Switching Characteristics, Vee
Parameter

Min

Test Conditions: CL = lSpF.

-5S0C
Typ
RL

= 5V Over Recommended Free-Air Temperature Range
Max

Min

+2S0C
Typ

Mex

Min

+12SoC
Typ
Max

Unit

= 2kO (See Fig. A, page 2-1741

tplH

LSOO,04,
10,20
LS30
tpHl LSOO,04,10,
LS20
LS30
Test Conditions: CL - SOpF.
tplH

tpHl

LSOO,04,
10,20
LS30
LSOO,04,10,
LS20
LS30

12
3.0
5.0
11
4.0
6
9
15
3.0
5.0
10
4.0
16
8.0
18
25
6.0
15
- 21(0 (See Fig. A, page 2-174)
6
7

RL

9
8
11
12
27

15
13
17
16
35

9
8
10
"12
21

10

7

11

9

10
12
20

15
13
16
16
28

ns

8
10
10

12
15
14
16
17

10
12
10
12
16

16
18
16
18
23

ns

ns

ns

Note: Ae specification shown under -S5°e and +125°e are for 9lS devices only. All 50pF specifications
a'e for 9lS devices only.

CEAYTHE<3l

2-3

LS01
LS05

LS03
LS12

Positive-NAND Gates, Hex Inverters
With Open-Collector Outputs

LS22

PIN·OUT AND LOGIC DIAGRAMS

1.S03
QUADRUPLE 2·INPUT NAND GATE

LS01
QUADRUPLE 2·INPUT NAND GATE

12

11

13

9

14

8
7
6
2 3

4

12

Vee 4Y 4B 4A 3Y 3B 3A

10

@~1Jj

11

10

vee 4B 4A 4Y 3B 3A 3Y

: @tTt]

13

14

;W~
IV IA IB 2Y 2A 2B GNO

5

2 3

4

IA IB IV 2A 2B 2Y GNO

5

positive logic: Y = AB

positive logic: Y = AB

Die Size .060 x .067

Die Size .060 x .067

LS05
HEX INVERTER

LS12
TRIPLE 3-INPUT NAND GATE

Vee 6A 6Y SA 5Y 4A 4Y

9
8
7
6

12

~UU~

4

5

10

13

9

14

8
7
6

~cb1~m

IA IV 2A 2Y 3A 3Y GNO

3

11

2 3

positive logic: Y = Ii.

4

5

positive logic Y = ABC

Die Size .060 x .067

Die Size .060 x .067

LS22
DUAL 4·INPUT NAND GATE

12

10

IA IB Ne Ie 10 IY GNO
positive logic: Y = ABCD

Die Size .060 x .067
NC - No internal connection

2·4

~YTHEO~

Positive-NAND Gates, Hex Inverters
With Open-Collector Outputs

LS01
LS12

LS05

LS03
LS22

Recommended Operating Conditions
Min
Supply voltage, Vee (See Note 1)
High·level output voltage, VOH
Low-level output current, IOL
Operating free-air temperature, T A
NOTE 1: Voltage values are wIth respect to network ground termonal.

9LS/54LS
Nom
Max

4.5

5.5
5.5
4
125

5

-55

Min

9LS/74LS
Nom
Max

4.75

5

5.25
5.5
8
70

Unit
V
V
rnA
°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions"

Parameter

Min

9LS/54LS
Typ"" Max

Vee-MIN,
Vee-MIN,

11--18mA
VOH-5.5V

VOL

Vee~MIN,

VIH~2V

VIL -0.7V
IOL -4mA
IOL ~8mA

9LS/74LS
Typ"" Max

2

2

VIH
VIL
VI
IOH

Min

0.25

0.7
-1.5
100
0.4

0.25
0.3

0.8
1.5
100
0.4
0.5

Unit
V
V
V
/lA
V

0.1
0.1
rnA
VI~7.0V
Vee~MAX,
II
20
20
Vee~MAX,
VI~2.7V
/lA
IIH
-0.4
-0.4
rnA
Vee-MAX,
VI-O.4V
IlL
0.2
0.4
0.2
0.4
rnA
Vee~MAX,
All inputs at OV (Per Gate)
leeH,
0.6
1.1
0.6
1.1
rnA
Vee~MAX,
All inputs at 4.5V (Per Gate)
leeL
..
·For condItIons shown as MIN or MAX, use the appropriate value specIfied under recommended operatong condItions for the applocable
device type.
·'AII typical values are at Vee = 5V, TA = 25°e.
t Not more than one output should be shorted at a time.

Switching Characteristlcs, Vcc = 5V Over Recommended Free-Air Temperature Range
Parametar
Test Conditions: CL

I
I

Min

I

-55OC
Typ

I
I Max I

= 1SpF, RL = 2kO

Min

I

+25°C
Typ

I
I Max I

tpLH
tpHL

I
I

I

12
6.0

=

I

I 18.0 I
I 12 I

I

Unit

28
18

I

ns
ns

35
25

I

ns
ns

+12S"C
Typ I Max

I

I

ISee Figure B, page 2-174)

17.0116 1 28 1 7.0 114122
tpLH
6.0
12
22
4.0
10
18
tpHL
Test Conditions: CL - SOpF, RL 2kO (See Figure B, page 2-174)

I

Min

I

35
25

I
I

I

12
6.0

I
I

I

20
12

I
I

30
20

J 7.0 1 15 I
I

I
I

4.0

I

10

I

12
6.0

I
I

21
12

I
I

I

I

Note: Ae specification shown under ,_55°e and +125°e are for 9LS devices onlv. All 50pF specifications
are for 9LS only.

~YTHEO"El

2-5

LS02 LS27
PIN-OUT AND LOGIC DIAGRAMS
LS02
QUADRUPLE 2-INPUT NOR GATE
12

Vee 4Y 4B 4A 3Y 38 3A

11, 10

"'i3~

9

13
14

8
7
6
2 3

4

LS27
TRIPLE 3-INPUT NOR GATE

9

13
14

8
7
6

IV lA 18 2Y 2A 28 GND

5

2

positive logic: Y = A+B

Die Size .OS3 x .053

3

4

5

positive logic: Y = A+B+C

Die Size .OS3 x .OS3

Recommended Operating Conditions
Min
Supply voltage, Vee

9LS/54LS
Nom
Max

4.5

5

LHigh

logic level
I Low logic level

Normal ized fan-out from each output, N
Operating free-air temperature, TA

-55

Min

5.5
20
10

4.75

125

0

9LS/74LS
Nom
Max
5

Unit

5.25
20
20

V

70

°C

Electricaf Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Condltions*

Parameter

Min

9LS/54LS
Typ** Max

2

VIH
VIL
VI
VOH

11=-18mA
10H- 400/lA

Vee=MIN,
Vee=MIN,
Vee=MIN,

VOL

Min

9LS/74LS
Typ*' Max

2
0.7
-1.5

2.5

VIL -0.7V
10L -4mA
10L-BmA

3.4
0.25

O.B
-1.5
2.7

0.4

3.4
0.25
0.35

0.1
20
-0.4
15
100
15
1.6
3.2
1.6
LS02
Vee=MAX, All inputs at OV
leeHt
4.0
2.0
2.0
LS27
2.8
2.B
5.4
LS02
Vee=MAX, All inputs at 5V
leeL
3.4
6.B
3.4
LS027
..
..
*For condItIons shown as MIN or MAX, use the appropnate value specIfIed under recommendea operating condItIons
device type.
·"AII typical values are at Vee = SV, TA = 2 Soe.
tNot more than one output should be shorted at a tim•.
Switching Characteristics, Vcc = 5V Over Recommended Free-Air Temperature Range
Vee-MAX,
Vee=MAX,
Vee=MAX,
Vee-MAX,

II
IIH
IlL
los

VI=7V
VI=2.7V
VI=O.4V

..

Parameter
Test Conditions: Cl
tpLH
tpHL
Test Conditions: Cl
tpLH
tpHL

2-6

I

I

Min

-55°C
Typ

I

1
+ 25°C
"I
I Max I Min I Typ, I Max I

Min

+125°c
Typ I Max

I
I

I

I

I

Unit
V
V
V
V

0.4
V
0.5
0.1
mA
20
/lA
-0.4
mA
-100 mA
3.2
rnA
4.0
5.4
mA
6.8
for the appilcable

Unit

= 15pF, Rl = 2kO (See Fig. A. page 2-174)

I

I
I

5
7

I
L

I
J

8
10

I

I

I

I

I
I

I

6.0
11
11
I 6.0 I 12
14 I
= SOpF, R, = 2kO (See Fig. A. page 2-174)

I

I

I
I

13
15

J

8
7

I
I

13
14

I
I
I
I

I

8
4

I
I

10
7

I
I
I

I

13
14
15
15

I
I

I

ns
ns
ns
ns

~YTHEC3J

Positive-AND Gates

LS08

LS11

LS21

PIN-OUT AND LOGIC DIAGRAMS

LS08
QUADRUPLE 2-INPUT AND GATES

LSll
TRIPLE 3-INPUT AND GATES

VCC 4B 4A 4V 3B 3A 3V

Vee lC IV 3C 3B 3A 3V

"" "UfJ

"~tJ

13
14

11
12

2

3

4

lA lB IV 2A 2B 2V GND

5

positive logic: Y = AB

positive logic: Y = ABe

Die Size .045 x .056

Die Size .052 x .054

LS21
DUAL 4-INPUT AND GATES
12 10

9

13

8

7
6
2

4

5

lA lB NC lC lD IV GND
positive logic: Y = ABeD

Die Size .042 x .044
Ne-No intemal connection

Recommended Operating Conditions
9LS/54LS

Supply voltage, Vee
Normalized fan-out from each output, N
Operating free-air temperature, T A

~VTHE03l

9LS/74LS

MIn

Nom

Max

Min

Nom

Max

4.5

5

5.5
20
11
125

4.75

5

5.25
20
20
70

I High logic level
I Low logic level
-55

0

Unit

V

°c

2-7

LS08

LS11

Positive-AND Gates

LS21

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

Min

9LS/S4LS
Typ"
Max

11=-18mA
IOH=-4OOILA

Vee-MIN,
Vee=MIN,

VOL

9LS/74LS
Typ"
Max

2

2

VIH
VIL
VI
VOH

Min

0.8
1.5

0.7
-1.5
2.5

VIH=2.0V
IOL-4mA
IOL-8mA

3.4
0.25

2.7
0.4

3.4
0.25
0.35

0.4
0.5
0.1
20
-0.4
-100
1.2
2.2

Unit
V
V
V
V
V

mA
VI=7.0V
0.1
Vee=MAX,
II
20
VI=2.7V
IlA
Vee-MAX,
IIH
mA
-0.4
Vee-MAX,
VI=O.4V
IlL
-100 -15
mA
-15
Vee-MAX
los
mA
0.6
1.2
0.6
All inputs at 4.5V (Per Gate)
Vee=MAX,
leeH
1.1
mA
1.1
2.2
Vee-MAX,
All inputs at OV (Per Gate)
leeL
"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"AII typical values are at Vee = SV, TA = 2soe.
tNot more than one output should be shorted at a time.

Switching Characteristics, Vee
Parameter

Min

Test Conditions: CL = 1SpF.
LS08,11
LS21
LS08,11
t PHL
LS21
Test Co.ndltlons: CL

tpHL

LSOB,11
LS21
LS08,11
LS21

RL

10
6
6
-

SOpF.

= 5V Over Recommended Free-Air Temperature Range
Max

Min

+2SOC
Typ

Max

Min

+12S0C
Typ
Max

Unit

= 2kO (See Fig. A, page 2-174)
9

tpLH

t PLH

-SS"C
Typ

RL -

11
12
10
14

4
8.5
15
9
11
6
11
6
2kO (See Fig. A, page 2-174)
17
22
15
22

10
12
B
12

13
14
10
10

10
8
8

14
15
12
12

15
20
12
20

11
12
11
12

16
23
16
23

9

ns
ns

ns
ns

Note: AC specification shown under -S5°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS only.

2-8

~YTHEO!J

Positive-AND Gates
With Open-Collector Outputs

LS09

LS15

PIN-OUT AND LOGIC DIAGRAMS
LS09
QUADRUPLE 2-INPUT AND GATES
12
L5

13
14

11

-.,---,

10

Vee 48 4A 4V 38 3A 3V

9

~

III "

--=~-.-.
~ ,~.
'-.'

• • ~!

I"

8

:;-,.-.,..-,.

~
.......
~

2 3
4
Die Size .045 x .056

LS15
TRIPLE 3-INPUT AND GATES

7

6

5

@~tJ

10

W~

11
12

1~. 18 1V JA 28. 2V GNU

positive logic: Y = AB

positive logic: Y = ABC

Die Size .052 x .054

Recommended Operating Conditions
Min

9LS/54LS
Nom
Max

4.5

Supply voltage, Vee (See Note 1)
High-level output voltage, VOH
Low-level output current, IOL

5

5.5
5.5
125

-55

Min

9LS/74LS
Nom
Max

4.75

5

0

5.25
5.5
70

Unit
V
V

°c

NOTE1: Voltage values are with respect to network ground terminal.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions·

Parameter

9LS/54LS
Typ·· Max

2

VIH
Vil
VI
VOH

Vee=MIN,
Vee=MIN,

IOH

Vec=MIN,
Vcc=MAX,
Vcc-MAX,
• Vcc-MAX,

II
IIH
IlL

Min

Min

9LS/74LS
Typ·· Max

11=-18mA
VOH=5.5V,

VIW2.0V
llOL =4mA
IIOL -8mA

VIL =VILMAX

0.8
-1.5

V
V
V

100

JlA

2
0.7
-1.5
0.25

100
0.4

0.25

004

U.;:!!)

U.b

0.1
20
-0.4

VI=7.0V
VI-2.7V
VI-OAV

Unit

0.1
20
-0.4

V
mA
JlA
mA

0_6
All inputs at 4.5V (Per Gate)
1.2
1.2
mA
0.6
Vcc=MAX,
1.1
1.1
2.2
mA
Vcc-MAX,
All inputs at OV (Per Gate)
2.2
..
..
'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
ICCH

ICCL

device type.
"AII typical values are at Vee = 5V, TA = 25°C.

Switching Characteristics, Vcc = 5V Over Recommended Free-Air Temperature Range
Parameter

I

I

Min

-55°C
Typ

I

I

I Max I

Min

I

+25°C
Typ

1 _ +125°C
I
I Max I Min I Typ I Max I

Unit

Test Conditione: CL = 15pF, RL = 2kO (See Fig. B. page 2-174)

I I I I I

I II I I I
I
I 9 I

tpLH
14
20
14
21
tpHL
I
I 10 I 15 I
I 8 I 12
Test Conditione: CL = SOpF. RL = 2kO (See Fig. B. page 2-174)
tpLH
I 30 I 38
L
I 30 I 38 I
tpHL
I 12 I 17
I
I 16 I 23 I

42
13

28

I
I

I
I

40
13

I
I

54
17

I
I

ns
ns
ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS devices only.

~VTHEO:?J

2-9

LS13

Schmitt-Trigger Positive-NAND Gates and
Inverters with Totem-Pole Outputs

LS14

PIN-OUT AND LOGIC DIAGRAMS

FEATURES
• Operation from Very Slow Transitions
• Temperature-Compensated Threshold Levels

LS13

• Temperature-Compensated Hysteresis, Typically O.8V
•

High Noise Immunity

DESCRIPTION
Each circuit functions as a NAND gate or inverter, but
because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. The
hysteresis or backlash, which is the difference between the
two threshold levels, is typically 800 millivolts.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean,
jitter-free output signals.

Vee

GND

14

7

b~m

IA 18 NC IC 10 IV GND
positive logic: V = ABCD

12.3456

Die Size .057 x .057

NC- No internal connection

SCHEMATIC (EACH GATE)
LS14

r--r--~---1---->r----~--VCC

loon

20 kn

NOM

NOM

13 12 11 10 9

8
VCC 6A 6V 5A 5V 4A 4V

If ~

[ill £¥][j~!,!f1 ~

Vee

B-i--r---c-~-~-,..-1

1

1

I

I

I

GND

14

0--1- +-1--.I

~~~

~~~~------~--

7
__~______~~-L_GNO

1t>J1t>J~

~~&m
IA IV 2A 2V 3A 3V GNO
positive logic: V = A

2

3

4

5

6

Die Size .057 x .057

Recommended Operating Conditions
Min
Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, T A

2-10

4.5

55

9LS/54LS
Nom
Max

5

5.5
-400
4
125

Min

4.75

0

9LS/74LS
Nom Max

5

5.25
-400
8
70

Unit
V
IJ.A
mA

°C

~YTHE03'l

Schmitt-Trigger Positive-NAND Gates and
Inverters with Totem-Pole Outputs

LS13

LS14

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

VOH

Vcc=5V
VllC=5V
Vee=5V
Vee- MIN,II--18mA
Vee-MIN, IOH--400jlA, VI-0.6V

VOL

Vee=MIN,

IT+
ITII

Vee=5V,
Vcc=5V,
Vee=MAX,
Vec=MAX,
Vec-MAX,
Vce=MAX

VT+
VTVT+- VTVI

IIH
III
los
leeH

leel

Min

1.9

1.4

.8
0.8

1.0

.5
0.4

1.6
.8
0.8

2.5

3.4

2.7

3.4

-1.5
0.25

Vce=MAX,

VI=4.5V

0.25
0.35
-0.14
-0.18

0.4

0.1
20
-0.4
LS13
LS14
LS13
LS14

2.9
8.6
4.1
12

-100
6
16
7
21

1.9
1.0
1.5

-0.14
-0.18

-15
VI=OV

9LS/74LS
Typ"
Max

1.6

VI=VT+
VI=VT_
VI=7V
VI-2.7V
VI-0.4V

Vee=MAX,

Min

1.4
.5
0.4

IOL=4mA
10l =8mA

VI=2V

9LS/54LS
Typ"
Max

-15
2.9
8.6
4.1
12

0.4
0.5

0.1
20
-0.4
-100
6
16
7
21

Unit
V
V
V
V
V
V
mA
mA
mA
jlA
mA
mA
mA
mA

"For conditions· shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
""All typical values are at Vee = 5V, T A = 25°e.
tNot more than ona output should be shorted at a time.

Switching Characteristics, Vee = 5V Over Recommended Free-Air Temperature Range
Parameter

Min

-55°C
Typ

Max

Min

+25°C
Typ

Max

Min

+125°C
Max
Typ

I

Unit

TMt Conditione: CL = 15pF, RL = 2kO (See Fig. A, page 2-174)
LS13
LS14
LS13
tpHl
LS14
Teet Conditione: CL =
tPLH

tplH
tpHl

LS13
LS14
LS13
LS14

16
16
22
17
SOpF,
20
20
25
21

22
28
15
15
22
28
18
27
38
22
15
32
RL = 2kO (See Fig. A, page 2-174)
38
38
42
38

20
20
25
20

27
27
33
27

16
20
16

30
30
38
30

ns
ns
ns
ns

20
21
25
21

38
38
42
38

ns
ns
ns
ns

16

Note: AC specification shown under _55°e and +125°C are for 9LS devices only. A" 50pF specifications
are for 9LS only.
PARAMETER MEASUREMENT INFORMATION

VOLTAGE WAVEFORMS
NOTES:

A. The input waveform is supplied by a generator with the following characteristics:
Zout = 50S. and PRR .;; 1 MHz, tr .;; 15 ns, tf .;; 6 ns.
B. el includes probe and jig capacitance.
C. All diodes are 1N916 or 1N3064.

~YTHE~

2·11

LS13

Schmitt-Trigger Positive-NAND Gates and
Inverters with Totem-Pole Outputs

LS14

TYPICAL CHARACTERISTICSt

POSITIVE·GOING THRESHOLD VOLTAGE
VS
FREE·AIR TEMPERATURE.

NEGATIVE·GOING THRESHOLD VOLTAGE
VS
FREE·AIR TEMPERATURE

>

>

~ 1.69 f- v~e =15V

t

I 1.70

>

1.68
1.67

"C

o

~

1.65
~ 1.64
'0
1.63
.., 1.62

0.88

~ 0.87
~ 0.86

J

.=

0.85

.~

*

~

.~

~ 1.61
I 1.60
·75 ·50 ·25 0 25 50 75 100 125
T A·Free·Air Temperature·oe

J
I

~

0.80
·75 ·50 ·25 0 25 50 75 100125
TA·Free.Air Temperature·oe

--

~

'ij 810

!>- 800

~

V~C=15V

-- -I'-...

:r: 790
I

... 780

~ 770
i!: 760

>

DISTRIBUTION OF UNITS
FOR HYSTERESIS

TA= 25°e

I 820

I-...

99% ARE
ABOVE
735mV

.u...r

750
·75 ·50 ·25 0 25 50 75 100125
T A Free·Air Temperature °c

2.0

~ 1.8

.~ 1.6

~

1.4

~ 1.2

c::
~ 1.0

f! 0.8

I
I l..J.-+-rT

I

"'
\

~

"""

VT+-VT:·Hysteresis·mV

OUTPUT VOLTAGE
VS
INPUT VOLTAGE

TA = 25"C

-I

I

I VT+

>

tlit
(i It~·-jge,

I
~
Posrtlve-IG·
olng T~ res.~

I

8.

0

I I

3~r-r-+-~+-+-1-~-r~

l3

Negative-Going Threshold Voltage,

~ 0.6
"C
0 0.4
.r:
f! 0.2
.r: 0
4.5

...

I

720 740 760 780800 820 8408ElO 880

THRESHOLD VOLTAGES AND HYSTERESIS
VS
SUPPLY VOLTAGE

>

....

0.81

Vee = 5V

~ 830

,. " .... i"""

~

0.84
0.83
0.82

HYSTERESIS
VS
FREE·AIR TEMPERATURE

850
840

v~e=15V

0.89

~

.

~ 1.66

0.90

I

8-

VT_

~
"

S-

2 ~+-t-+--+t++-+-tH-;

o"

Hysteresis. VT + - VT _

I

~
4.75

5

5.25

Vec·Supply Voltage·V

5.5

oU..LL~q±:±~
o

0.4

0.8
1.2
1.6
V rlnput Voltage-V

2

t Data for temperatures below O°C and above 70°C and supply voltages below 4.75V and above 5.25 are applicable for 9LS/54LS13. and
9LS/54LS14.

2-12

~YTHEO}J

Schmitt-Trigger Positive-NAND Gates and
Inverters with Totem-Pole Outputs

LS13

LS14

TYPICAL APPLICATION DATA
I

-~

i TTL SYSTEM

I----@}D---

CMOS

I

I
I

I

~------~

I

I

I

I
I

~INE.WAVE ~n
I

~--

OSCILLATOR

I

OUTPUT I

1----...

I

I

TTL SYSTEM INTERFACE
FOR SLOW INPUT WAVEFORMS

PULSE SHAPER

---- ----

0.1 Hz tol0MHz

330n

--VT+

INPUT

OUTPUT

THRESHOLD DETECTOR

MULTIVIBRATOR

Open-collector
output

r----'~A
TI

INPUT
- - - ,I

r-

:. .}.LI' .
I

I

I

,,'

I
I

1I

1-1

I

OUTPUT
--

I

i
I
I

L ___ --'

..

PULSE STRETCHER

~YTHE<3J

2·13

Quadruple 2-lnput High-Voltage
Positive-NAND Gate

LS26

PIN-OUT AND LOGIC DIAGRAM
(OPEN-COLLECTOR OUTPUTS)

Vee 48 4A 4Y 38 3A 3Y

~l[jti
1A 18 1Y 2A 28 2Y GND

positive logic: Y = AS
Die Size .047 x .048

Recommended Operating Conditions
Min

Supply voltage, Vee (See Note 1)
High-level output voltage, VOH
Low-level output current, IOL
Operating free-air temperature, T A

9LS/54LS
Nom
Max

4.5

5.5
15
4
125

5

55

Min

9LS/74LS
Max
Nom

Unit

5.25
15
8
70

V
V
mA
C

4.75

5

0

NOTE 1: Voltage values are with respect to network ground terminal.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Teat Conditlona·

Parameter

Min

9LS/54LS
Typ·· Max

VI

Vee=MIN,

11=-18mA

IOH

Vee=MIN,

VIL =VILmax

VOL

Vee=MIN,

VIW2V

II
IIH
IlL
leeH
leeL

VI=7V
Vee=MAX,
Vee=MAX, . VI=2.7V
Vec=MAX,
VI=O.4V
All inputs at OV
Vee=MAX,
All inputs at 4.5V
Vee-MAX,

VOH-12V
VOH=15V
IOL =4mA
IOL -8mA

9LS/74LS
Typ·· Max

0.25

0.7
-1.5
50
1
0.4

0.8
2.4

0.1
20
-0.4
1.6
4.4

Unit

V

2

2

VIH
VIL

Min

0.25
0.35

0.8
2.4

0.8
-1.5
50
1
0.4
0.5
0.1
20
-0.4
1.6
4.4

V
V
/lA
mA
V
mA
/lA
mA
mA
mA

"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
""All typical values are at Vee = SV, TA = 2soe.

Switching Characteristics, Vcc
Parameter

I
I

Min

-55°C
Typ

I

= 5V Over Recommended Free-Air Temperature Range

I
I Max I

Min

I

+25°C
Typ

I
I Max I

Min

+125°C
Typ
Max

I

I

J

I

Unit

I

ns
ns

I

ns
ns

Test Conditions: CL = 15pF, RL = 2kO (See Fig. B, page 2-174)

I 7.0 1 16 I

I

I

I

28
7.0
14
22
12 I 22 I 4.0
10 I 18
Test Conditions: CL = SOpF, RL = 2kO (See Fig. B, page 2-174)
tPLH
I 12 I 18 I 35 I 12 I 20 I 30
tpHL
I 6.0 I 12 I 25 I 6.0 I 12 I 20

tpLH
tpHL

I

6.0

I

1

I
I

I
I

7.0
4.0
12
6.0

I
I
I
I

15
10
21
12

I
I

I
I

28
18
35
25

I
I

Note: Ae specification shown under _55°e and +12Soe are for 9LS devices only. All SOpF specifications
are for 9LS only.

2-14

t§YTHEO~

NOR, NAND Buffers

LS28

LS37

LS40

PIN·OUT AND LOGIC DIAGRAMS
LS28
QUADRUPLE 2·INPUT NOR BUFFER
1

2

3

4

14

@lr:JtJ

Vee

Vee 4Y 48 4A 3Y 38 3A

13

R ~ffi_,'.1
Ili":'~=~.""i I
R,.
' •• ' • .1

:b~- =~d
......
..... .•
r11:', •• ,

LS37
QUADRUPLE 2·INPUT NAND BUFFER

'1"-

@~il

12
11

1

10

9

14

13

2

12

3

11

4

10

5

5 ......

678

positive logic: Y; A+S

Die Size .045 x .052

1

W~

9
6

1Y 1A 18 2Y 2A 28 GNO

7

48 4A 4Y 38 3A 3Y

8

lA 18 1Y 2A 28 2Y GNO

positive logic: Y ; AS

Die Size .045 x .052

14 13

2

12

4'

10

5

9
6

7

8

lA 18 NC 1C 10 1Y GNO

positive logic: Y ; ABeD

Die Size .045 x .052

Recommended Operating Conditions
9LS/54LS

Supply voltage, Vee
Normalized fan-out from each output, N
Operating free-air temperature, T A

r§VTHEO]J

9LS174LS

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
60
30
125

4.75

5

5.25
60
60
70

I High logic level
I Low logic level
-55

0

Unit
V

°c

2-15

LS28

LS37

NOR, NAND Buffers

-LS40

Electrical Characteristics Over Recommended Free·Alr Temperature Range (Unless Otherwise Noted
T..t CQndltlon.·

Parameter

Min

9LS/54LS
Typ·· Max

2

VIH
VIL
VI

IOH=-1.2mA

'VOL

Vcc=MIN,

VIH=2V

II
IIH
IlL
loS

Vcc=MAX,
VCC=MAX,
Vcc=MAX,
Vcc=MAX

VI-7V
VI=2.7V
VI=0.4V

9LS"4LS
Typ·· Max

2
0.7
-1.5

11=-18mA

Vcc=MIN,
Vcc=MIN,

VOH

Min

2.5

VIL =0.7V
10L =12mA
IOL=22mA

3.4
0.25

0.8
-1.5
2.7

0.4

3.4
0.25
0.35

0.1
20
-0.4
-100

-30
-30
0.45
0.9
0.45
Vcc"'MAX, All inputs at OV LS28
ICCH
0.23
0.5
0.23
LS37.40
(Per Gate)
1.7
3.45
LS28
1.7
VccMAX, All inputs at 5V
ICCL
1.5
3.0
(Per Gate)
LS37.40
1.5
~For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
device type.
'
""A" typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.

..

..

..

Unit
V
V
V
V

0.4
V
0.5
0.1,
mA
20
flA
-0.4
mA
-100 mA
0.9
mA
0.5
3.45
mA
3.0
.for the applicable

.

Switching CharacteristIcs , V'cc- 5V Over Recommended Free Air Temperature Range
Parameter

I.
-55OC
I
1 Min 1 Typ 1 Max I

Min

I

+25°C
Typ

I Max

I
I

Min

+125°C
Typ
Max

I

I

I

I

Unit

Teet Conditions: CL = 45pF,R!,. = 6670 (See Fig. A, page 2-174)

I

I

I

1

J

I

I

I

I

I

I

I

tpLH
11
6
10
5
tpHL
I 7 I 15
I
I 9 I 14 I
Teet ConcIHIOflll: CL = 12SpF, RL = 6670 (See Fig. A. page 2-174)
7
tpLH
8
16
15
tpHL
I 10 I 18
I
I 14 I 20 I

I

I

I

I

I

I 7

I 1514 I

I

I

I

6

8
10

I

I

ns

I ns

16
20,

I
I

ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only, All 50pF specifications are for 9LS devices only.

2-16

~YTHEO~

Quadruple 2-lnput Positive-OR Gate

LS32

PIN-OUT AND LOGIC DIAGRAM

lS32
QUADRUPLE 2-INPUT OR GATE

12

11

10

Vee 48 4A 4V 38 3A 3V

13

9

14

8

~tJtJ

WWm

7
6

2 .......
3 4 5

lA 18 tv 2A 28 2V GND

positive logic: Y = A+B

Die Size .053 x .053

Recommended Operating Conditions
Min

9LS/S4LS
Nom
Max
5

4.5

Supply voltage, Vee
I High logic level
Low logic level

Normalized fan-out from each output, N

I

-55

Operating free-air temperature, T A

5.5
20
10
125

Min

9LS/74LS
Max
Nom

4.75

5

0

5.25
20
20
70

Unit
V

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Test Conditions"

Min

9LS/S4LS
Typ"" Max

2

VIH
V'L
V,

9LS/74LS
Typ·· Max

2
0.7
-1.5

1,--18mA
low 400tlA, V'L -0.7V
Llol -4mA
V,w2V
IIOl -8m A
V,=7V
V,=2.7V
v,=O.4V

Vee-MIN,
Vee-MIN,

VOH

Min

2.5

3.4
0.25

0.8
-1.5
2.7

0.4

3.4
0.25
0.35

Unit
V
V
V
V

0.4
V
0.5
0.1
mA
I,
0.1
Vee=MAX,
20
20
Vee=MAX,
tl A
I'H
-0.4
-0.4 mA
Vee-MAX,
I'l
-100 mA
-100 -15
lost
Vee-MAX
-15
3.1
6.2
3.1
6.2
mA
All inputs at 5V
Vee-MAX,
leeH
4.9
9.8
4.9
9.8
mA
All inputs at OV
Vee=MAX,
leel
. . for the applicable
'For condItions shown as MIN or MAX, use the approproate value specIfIed under recommended operatong condItIons
device type .
•• All typical values are at Vee = 5V, T A = 25° e.
tNot more than one output should be shorted at a time.
Vee=MIN,

VOL

..

Switching Characteristics, Vee

I

Parameter

I

Test Conditions: CL

=

I

J
I

Min

+12SoC
Typ I Max

I

J

I

Unit

=

1 I

I

7
7

tplH
tpHl
I
I
Test Conditions: CL - SOpF, RL
tplH
tpHl

= 5V Over Recommended Free-Air Temperature Range

-SsoC
+2SoC
Min I Typ I Mu I Min I Typ I Max
1SpF, RL 2kO (See Fig. A, page 2·1741

I

-

I

I

9

I

I

11

I

I

11
7
12
13 I
I 7 I 12
2kO (See Fig. A, page 2-1741

I

I

I

I

I

I

9
9

I

13
14

10

I

15

I
I

I

I 14

I

I 8

I

13 I

I

I

I

I lu

I

Ibl

I 12 I 181

11

ns
ns
ns
ns

Note: Ae specification shown under _55°C and +12Soe are for 9lS devices only. All 50pF specifications
are for 9lS only.

t;VTHE031

2-17

,LS33

NOR, NAND Buffers With
Open-Collector Outputs

LS38

PIN-OUT AND LOGIC DIAGRAMS
LS33
QUADRUPLE 2-INPUT NOR BUFFER
vee 4V 4B 4A 3V 3B 3A

LS38
QUADRUPLE 2-1NPUT NAND BUFFER
Vee 4B 4A 4V 3B 3A 3V
14 13

~i3Q

12

3

11

4

10

5

9

6

tv IA IB 2V 2A 2B GND
positive logic: Y = A+B

Die Size .045 x .052

2

7

~rJrJ

8

IA IB IV 2A 28 2V GND
positive logic: Y = AB

Die Size .045 x .052

Recommended Operating Conditions
Min

9LS/54LS
Nom
Max

4_5

SupplV voltage, Vee (See Note 1)
High-level output voltage, VOH
Low-level output current, IOl
Operating free-air temperature, T A

5

-55

5.5
5.5
22
125

Min

9LS/74LS
Nom
Max

4.75

5

5.25
5.5
22

Unit
V
V
rnA

°C

NOTE I: Voltage values are with respect to network ground terminal.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted
Parameter

Test Conditions·

Min

9LS/54LS
Typ·· Max

2

VIH
VIL
VI

Vee-MIN,

11--18mA

IOH

Vec=MIN,

VIL =VILmax

Min

9LS/74LS
Typ·· Max

2
0.8
-1.5

0.7
-1.5

VOL

Vcc';'MIN,

VIH=2V

II
IIH
IlL

Vcc-MAX,
Vcc-MAX,
Vcc-MAX,

VI-7V
VI-2.7V
VI-004V

ICCH

Vec=MAX, All inputs at OV

ICCl

Vcc=MAX, All inputs at 4.5V

250

VOH=5.5V
IOl -12mA
IOl -24mA

004

0.25

0.25
0.35

0.1
20
-0.4

250
0.4
0.5
0.1
20
-0.4

LS33
LS38

1.8.
0.9

3.6

1.8
0.9

3.6

2.0

LS33
LS38

6.9
6.0

13.8
12.0

6.9
6.0

1.38
12.0

2.0

Unit
V
V
V
p.A
V
V
rnA
p.A
rnA
rnA
rnA

*For conditions shown as MIN or MAX, use the appropriate value spacified under recommended operating conditions for the applicable
device type.
**AII typical values are at Vee = 5V, TA = 25°C.

Switching Characteristics, Vee
Parameter

I

I

Min

-55°C
Typ

I

= 5V Over Recommended Free-Air Temperature Range
I

I Max I

Min

I

+25°C
Typ

1
I Max I

Min

.+125°C
Typ
Max

I

I

I
I

Unit

I

ns

Test Conditions: CL = 45pF, RL = 6670 (See Figure B, page 2-1741
tpLH

I

I

I

I

I
I

I
I

17

I

25

I

I

I

7.0

I

17

I

I

25

I

tpHl
13
22
4.0
9
16
Test Conditions: CL :.. 125pF, RL - 6670 (See Figure B, page 2-1741
tplH
tpHl

2-18

30
22

I
I

I
I

45

I

I

32

I

42

I

36

I

I

18

I

35

I

I

29

I

10

I

44

I

15

I

37

I

17

I

ns

I

56
35

J
1

ns
ns

1

Note: Ae specification shown
under _55°e and +1 25°C
are for 9LS devices only.
All 50pF specifications
are for 9 LS devices only.

~YTHEO!J

4-Line To 10-Line Decoders (1-of-10)

LS42

FEATURES

LS43

LS44

PIN-OUT DIAGRAM

• All Outputs Are High for Invalid Input Conditions
• Also for Application as
4-Line to 16-Line Decoders
3-Line to B-Line Decoders

LS42
BCD-TO-DECIMAL DECODER

DESCRIPTION
These monolithic decimal decoders consist of eight inverters
and ten four-input NAND gates. The inverters are connected
in pairs to make BCD input data available for decoding by
the NAND gates. Full decoding of valid input logic ensures
that all outputs remain off for all invalid input conditions.
The LS42 BCD-to-decimal decoders, the LS43 excess-3-todecimal decoders, and the LS44 excess-3-gray-to-decimal
decoders feature inputs and outputs that are compatible for
use with most TTL and other saturated low-level logic
circuits.

OUTPUTS

positive logic: see function table

Die Size .077 x .065

54LS circuits are characterized for operation over the full
military temperature range of -55 DC to 125DC; 74LS
circuits are characterized for operation from ODC to 70 DC.

LS43
EXCESS-3-TO-DECIMAL DECODER

13 12

NO.

L54'

L543

EXCESS

BCD INPUT

Excess a-INPUT

a·GRAY INPUT

B
lLLLl

BAD

LLLHlHLLLHHL
LLHLL

14
15
16

All. TYPES
DECIMAL OUTPUT

C
BAD
LHL

1
2
3
4
5
HHHHH

6

7

LHHHHH

HHHHHL

lLH

lHLHHHHLHHHHHH

LHLLLHHHLHlLHHHHLHHHHH
LHL

LLHHLlHHHH

H

L

LHH

IIHHlHHHHH

H

LHHHHLHLHHHHH
LLHlHHHH

H
H

H

H

H

L

H

H

H

H

H

L

H

H

HH

H

H

H

H

l
H

H
l

H

H

H

L

HHHHHH

H

H

cHlHHHHHlHL

LHHHHH

HHH

::iHHLLHHHHHL

LLHHHH

HHHH

H

~

L

H

H

~~~~~~~
H

H

H

H

L

L

H

L

l

H

H

H

HH
H

L.L.HHHHHHHHHH
LHHHHHHHHHHH
LHH

HHH

OUTPUTS

positive logic: see function table

Die Size .077 x .065

HH

H = high level, L = low level

LS44
EXCESS-3-GRAY-TO-DECIMAL DECODER

14
15
16

~~1~11

~~IC:J10

OUTPUTS

positive logic: see function table

Die Size .077 x .065

~YTHE03J

2-19

LS42

LS43

4-Line To·10-Line Decoders C1-of-10}

LS44

LOGIC DI.AGRAMS

i5

o

LS42
BCD·TO·DECIMAL DECODERS

LS43
EXCESS-3·TO-DECIMAL DECODERS

LS44
EXCESS-3·GRA Y •TO·DECIMAL·DECODERS

2-20

t;YTHE~

4-Line To 10-Line Decoders (1-of-10)

LS43

LS42

LS44

Recommended Operating Conditions
9LS/54LS

Supply voltage, Vee

Min

Nom

4.5

5

9LS/74LS
Max

Min

Nom

5.5

4.75

5

-400

High level output current, IOH
Low·level output current, IOL

4

Operating free·air temperature, T A

125

-55

0

Max

Unit

5.25

V

-400

tJ A

8

rnA

70

"c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted.
9LS/74LS

9LS/54LS

Test Conditions'

Parameter

Min

Typ"

Max

VOH
VOL

0.8

1.5

Vee-MIN,

11--18mA

Vee-MIN,
VIL =VILmax

VIW2V,
low- 4OOtJ A

Vee=MIN,

VIH-2V,

2.5

0.25

IloL -4mA

1.5

3.5

2.7
0.4

V
V
V

3.5

IIOL =8mA

VIL =VILmax

Unit
V

0.7

VIL
VI

Max

2

2

VIH

Typ"

Min

0.25

0.4

0.35

0.5

V

II

Vee=MAX,

VI=7V

0.1

0.1

rnA

IIH

Vee=MAX,

VI=2.7V

20

20

IlL

Vee-MAX,

VI-O.4V

0.4

0.4

tJ A
rnA

-100
rnA
-15
-100 -15
Vee-MAX
lost
13
rnA
13
7
7
Vee-MAX,
lee tt
.
'For condItIons shown as MIN or MAX, use the appropnate value specIfIed under recommendea operatong condItIons for the apphcable
device type.
"AII typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
ttlee is measured with all outputs open and inputs grounded.

.

..

Switching Characteristics, Vee
Parameter

From

Teat CondItIona: C L = 15pF.

= 5V Over Recommended Free-Air Temperature Range
_55°C

To

!Input)

(Output)
RL

..

Min.

= 2kfi (See Fig, A.

Typ.

+25°C
Max.

Min.

+125°C

Typ.

Max.

Min.

Units

Typ.

Max.

page 2-174)

A,B,C or D

Any output
2 gate delay

15

26

14

25

15

26

ns

tpHL

A,B,e or D

Any Output
3 gate delay

17

31

17

30

18

31

ns

tpLH

A,B,e or D

Any output
2 gate delay

11

27

10

25

11

26

ns

tpLH

A,B,e or D

Any output
3 gate delay

22

35

17

30

20

34

ns

tpHL

Teat Conditions: C L = 5OpF.

RL

= 2k!l (See FIg, A, page 2-174)

tpHL

A,B,eor D

Any Output
2 gate delay

18

32

18

31

19

33

ns

tpHL

A,B,e or D

21

35

22

35

23

36

ns

tpHL

A,B,e or D

Any Output
3 gate delay
Any Output
2 gate delay

21

33

20

32

21

33

ns

tpLH

A,B,e or D

Any Output
3 gate delay

29

36

25

38

28

40

ns

Note: Ae specification shown under _55°C and +125°e are for 9LS devices only. All 50pF specifications
are for 9LS only.

~YTHE@J

2-21

LS51

LS54

AND-OR-Invert Gates

LS55
PIN·OUT AND LOGIC DIAGRAMS

2

LS54 .
4-WIDE 2·3-3-2·INPUT AOI GATE

LS51
DUAL 2·WIDE AOI GATE
vce IC IB IF
1 14 13
[ill 13

2 1 14 13

3

3

4

4

5

5

o

6 7 8 9

6 7

Die Size .041 x .046

9
positive logiC:
Y = (AB) + (CDE) + (FGH)

Die Size .041 x .046

+ (IJ)

LS55
2·WIDE 4-INPUT AOI GATE

7 8
positive logic:
Y = (ABeD) + (EFGH)

Die Size .041 x .046

Recommended Operating Conditions
Min

4.5

Supply voltage, Vee
Normalized fan-out from each output, N
Operating free-air temperature, T A

2-22

I High logic level

I Low logic level

-55

9LS/54LS
Nom
Max

5

5.5
20
10
125

9LS/74LS
Min

Nom

Max

4.75

5

5.25
20
20
70

0

Unit
V

°c

ttAVTHEO]J

ANO-OR-Invert Gates

LS54

LS51

LS55

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

Min

9LS/54LS
Typ"
Max

VcC=MIN,
Vcc=MIN,

1,=-18mA

VOH
Val

Vcc=MIN,

V'H=2V

I,
I'H
I,l

Vcc-MAX,
Vcc-MAX,
Vcc=MAX,

V,-7V
V,-2.7V
V,=O.4V

los

Vcc=MAX

2.5

V,L =0.7V
10l -4mA
10l -8mA

3.4
0.25

See Note 1

ICCl

Vcc=MAX,

See Note 2

2.7
0.4
0.1
20
-0.4
-100

-15

Vcc=MAX,

0.8
-1.5

0.7
-1.5

IOH=-400/lA

ICCH

9LS/74LS
Typ"
Max

2

2

V,H
V,L
V,

Min

0.8
0.8
0.4
1.4
1.0
0.7

LS51
LS54
LS55
LS51
LS54
LS55

1.6
1.6
0.8
2.8
2.0
1.3

3.4
0.25
0.35

-15
0.8
0.8
0.4
1.4
1.0
0.7

0.4
0.5
0.1
20
-0.4
-100
1.6
1.6
0.8
2.8
2.0
1.3

Unit
V
V
V
V
V
mA
/lA
mA
mA
mA

mA

'For conditions shown as MIN or MAX, use the appropriate value specified under recommendea operating conditions for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
NOTES:
1. ICCH is measured with all inputs grounded, and the outputs open.
2. ICCl is measured with all inputs of one gate at 5V, the remaining inputs grounded, and the outputs open.

Switching Characteristics, Vee
Parameter

I
I

= 5V Over Recommended
I

-55*C
Min

I

Test Conditions: CL = 15pF,

Typ

RL

I

Max

I

+250C

I

Min

Typ

I Max

I I

I I I
I

I

Free-Air Temperature Range

Min

+ 125°C
Typ
Max

I

I

I
I

Unit

I

ns

= 2kO (Soe Fig. A, page 2·174)

I

8
itplH
8.0
13
13
tpHl
I 8.0 I 13
I 12 I 17 I
I
Test Conditions: CL - 50pF, RL - 2kO (See Fig. A, page 2·174)
tplH
tpHl

I
I

I

13

I

18

I

15

I

20

L
I

J

I

12
12

L
I

18
18

I

I

I
I

I

8

I

9

I

13
13

I

I
I

I

I

12
13
17
17

I ns
I ns

I

ns

Note: AC specification shown under _55°C and +125 C are for 9lS devices only. All 50pF specifications
0

are for 9LS devices only.

~YTHEO}J

2-23

LS73
LS107

LS76
LS113

LS112

Dual J-K Negative-Edge-Triggered
Flip-Flops
'

.Pln-for-Pln and functional equivalents to 5473, 5476, 54107, 54S112, 54S113
PIN-OUT DIAGRAMS

DESCRIPTION
These monolithic dual J-K flip-flops feature individual J, K,
clock, and asynchronous preset and clear inputs to each
flip-flop. The preset or clear inputs, when low, set or reset
the outputs regardless of the level.s at the other inputs. When
preset and clear inputs are inactive (high), a high level at the
clock input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed
to change when. the clock pulse is high and the bistable will
perform according to the function table as long as minimum
setup and hold times are observed. Input data is transferred
to the outputs on the negative-going edge of the clock pulse.

LS113
8

7

6

5

2J 2PR 20 2iI
8

9
4
10

3

11

2

lCK lK 1J lPR 10

12 13 14
Die Size .060 x .066

LS76

LS73

IK 10
1J Iii

14

13 12

2J

11

15

10

16

9

8
2

7
4

3

6

5

CLR

Die Size .060 x .066

Die Size .060 x .066

LS112

LSI 07

1

9

2

9

8

7

6

2

11

8

12

14 15 16
1J

Die Size .060 x .066

2-24

Iii 10 lK

lCK lK 1J lPR 10

Die Size .060 x .066

r§YTHEO}J

Dual J-K Negative-Edge-Triggered
Flip-Flops

LS73
LS112

LS107

LS76
LS113

LOGIC DIAGRAM ('h)

Q

+_ CLEAR"

PRESET"4-----~----~

L -_ _. . -_ _

K~====!

~=='--J
CLOCK
PRESET

LS73
LS76
LS107
LS112
LS113

CLEAR
X
X
X
X

X
X
X

LS113

LS73,LS107
FUNCTION TABLE
(EACH FLIP-FLOP)
OUTPUTS

INPUTS
CLEAR

CLOCK

FUNCTION TABLE
(EACH FLIP-FLOP)

J

K

0

L

X

X

X

L

H

H

I

L

L

Qo

00

H

H

l

H

L

H

L

H

L

H

H

H

H

TOGGLE

X

X

Qo

H

H

INPUTS
PRESET CLOCK
L
X
H
I
H
I
H
I
H
I
H
H

0

00

J

K

X
L

X
L
L
H
H
X

H

L
H
X

H high level Isteady-state)
L c low level Isteady-state)

H . high level Isteady-state)
L - low level Isteady-state)
X ~. don't care

X .- don't care
~ .-. transition from high to low level

00

t

OUTPUTS
0
0
H
L

00

ao

H

L
L
H
TOGGLE

Qo

Go

transition from high to low level
the level of
before the indicated steady-.state

a

input conditions were established.

00 :;. the level of Q before the indicated steady-state input conditions were
established.
TOGGLE: Each output changes to the complement of its previous level on
each! clock transition.

TOGGLE: Each output changes to the complement
of its previous level on each
transition.

t

clock

LS76,LS112
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
PRESET CLEAR CLOCK
X
H
L
H
L
X
L
L
X
H
H
I
H
H
I
H
H
I
H
H
I
H
H
H

H
L

0

OUTPUTS

J

K

0

0

X

X

X

X

X

X

H
L
W

L
H
W

00

Go

L
H
L
H

L
L
H

X

X

H

H
L
L
H
TOGGLE

qo Go

high level Isteady-state)
low level Isteady-state)

X .:: don't care
t ..; transition from high to low level
0 0 = the level of
before the indicated steady-state input conditions were

a

established.
TOGGLE: Each output changes to the complement of its previous level on
each ~ clock transition.
*This configuration is nonstable; that is, it will not persist when preset and
clear inputs return to their inactive (high) level.

~YTHEO:?J

2-25

LS73 LS76
LS107 LS113

Dual J-K Negative-Edge-Triggered
Flip-Flops

LS112

Recommended Operating Conditions
9LS/54LS

Supply voltage, Vcc

l High logic level

Normalized fan-out from each output, N

Nom

Max

Min

Nom

Max

4.5

5

5.5
20
10
35

4.75

5

5.25
20
20
35

125

0'

I Low logic level
0
15
15
15
15
0
-55

Clock frequency, fclock
Width of clock pulse, tw(clock) (High)
Width of preset pulse, tw(preset) (Low)
Width of clear pulse, twlclearl (Low)
Input setup time, t setup
Input hold time, thold
Operating free-air temperature, T A

9LS/74LS

Min

0
15
15
15
15
0
0

Unit

V

MHz
ns
ns
ns
ns
ns

°c

70

tsetup is the minimum time required for the correct logic level to be present at the J or K input prior to the falling edge of the clock in order
to be recognized and transferred to the outputs.
thold is the minimum time required for the logic level to be maintained at the J or K input after the falling edge of the clock in order to
insure recognition. These devices require no hold time.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

VIH
VIL
VI
VOH
VOL

Teat Conditions·

9LS/54LS
Typ·· Max

2

VCC=MIN,
VIH=2V,
VIL =VILmax

9LS/74LS
Typ·· Max

2

2.5
l.IOL =4mA
IOL -SmA

3.4

0.8
-1.5
2.7

0.25

0.4

4

0.1
0.4
0.3
20
SO
60
-0.4
-0.8
-0.8
-100
8

VI=2.7V

VI=OAV
-15

3.4
0.25
0.35

I

VI=7V

See Note 1

Min

0.7
-1.5

11=-18mA
VcC=MIN,
Vcc=MIN,
VIH-2V,
VIL =VILmax, IOH=-4OO!LA

Jor K
Clock
Vcc=MAX,
Preset or Clear
J or K
Clock
Vr.C=MAX,
IIH
Preset or Clear
J or K
Clock
Vcc-MAX,
IlL
Preset or Clear
VCC=MAX
lost
VCC=MAX,
Icc tt
II

Min

-15
4

Unit

V
V
V
V

0.4
0.50
0.1
0.4
0.3
20
SO
60
-0.4
-O.S
0.8
-100
S

V

mA

!LA

mA
mA
mA

*For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
'*AII typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
tt ICC is measured with outputs open, with clock, J, K, and clear grounded and preset at 4.5V; then with clock, J, K, and preset grounded
and clear at 4.5V.

2-26

~YTHEO!1

Dual· J-K Negative-Edge-Triggered
Flip-FI~ps

LS107

Switching Characteristics, Vee
Parameter

I

Typ

Test Condition.: C L = 1SpF, RL

I
Max

= 2kO

tpHL
tpLH
tpHL

Min

35
CLR.PR
CLR.PR
CK
CK

8
14
8
13

+2SDC
Typ

I
Max

Min

+12SDC
Typ

Max

12
19
12
18

50
8
11
8
11

MHz

12
12
16

11
13
10
11

15
18
14
16

15
22
14
20

13
18
14
15

17
23
18
20

17

1)iI.t Conditions.: CL -SOpF, RL - 2kO (See Fig. A. paga2·174)
f max
tpLH
tpHL
tpLH
tpHL

CLR.PR
CLR.PR
CK
CK

10
19
10
18

Unit

(See Fig. A. page 2·174)

f max
tpLH

LS76
LS113

= 5V Over Recommended Free-Air Temperature Range

-SSDC
Min

LS73
LS112

14
24
14
23

10
17
10
15

ns
ns
ns
ns

MHz
ns
ns
ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS only.

t;YTHEO})

2·27

Dual D-Type Positive-Edge-Tri9gered
Flip-Flop

LS74

PIN-OUT DIAGRAM

DESCRIPTION
This monolithic dual edge-triggered D-type flip-flop features
individual D, clock, preset, and clear inputs_
Preset and clear inputs are active-low and operate independently of the clock input. When preset and clear are inactive
(high), information at the D input is transferred to the Q
output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level of the clock pulse and is
not directly related to the transition time of the positivegoing pulse. When the clock input is at either the high or
low level, the D-input signal has no effect at the output.

...

"" '"a:ww
a..
u
u
0

~

5

3

4

20 211

2

6

7
8
13

9
10 11

a:
..: 10 u

12

""9 !;iw

~
u

LOGIC DIAGRAM ('h)

u

10

a:
a..

Die Size .055 x .056
PRESET'"••:...:."'0'......._ "

CLEAR

FUNCTION TABLE
(EACH FLIP-FLOP)

{I.'"'

INP TS
PRESET CLEAR CLOCK
L
H
X
H
L
H
H
H

~~=L.-J~r---L-'

CLOCK 13
:.:.• .;.;"1'

X
X
t
t

L
L
H
H
H

o TP TIl
D

Q

Q

X
X
X
H

H
L

L
H
H*
L
H

L
X

L

H*

H

~ 00

= high level (steady state)
L = low level (steady state)
H

o '2::.'':::2'==~..J

X = don't care

i = transition from low to high level
0 0 = the level of 0 before the indicated steady-state input conditionll were
estabUshed.
'This configuration is nonstable; that is, it will not persist when preset and
clear inputs return to their inactive (high) level.

Recommended Operating Conditions
Min

4.5

Supply voltage, Vee
Normalized fan-out from each output, N
Clock frequency, fclock
Width of clock pulse, tw(clock) (High)
Width of preset pulse, tw(preset) (Low)
Width of clear pulse, tw(clearl (Low)
Input setup time, !setup
Input hold time, thold
Operating free-air temperature, T A

I High logic level
I Low logic level

I High-level data
I Low-level

data

0
17
15
15
10
10
0
-55

9LS/54LS
Max
Nom

5

5.5
20
10
30

125

9LS174LS
Min

Nom

Max

4.75

5

5.25
20
20
30

0
17
15
15
10
10
0
0

Unit

V

MHz
ns
ns
ns
ns

70

ns
VC

tsetup is the minimum time required for the correct logic level to be present at the D input prior to the rising edge of the clock in order to
be recognized and transferred to the outputs.

thold is the minimum time required for the logic level to be maintained at the D input after the rising edge of the ciock in order to insure
recognition. This device requires no hold time.

2-28

t;YTHE03'l

Dual D-Type Positive-Edge-Triggered
Flip-Flop

LS74

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted.
Teet Conditione·

Paramater

Min

9LS/54LS
Typ··
Max

Min

2

VIH

2

VIL
VI
VOH
VOL

VCC=MIN,

11=-18mA

Vcc-MIN,

VIH=2V,

VIL=VILmax

IOW-400~A

Vcc=MIN,

VIH=2V,

VIL =VILmax

2.5

Vcc=MAX,

VI=5.5V

Clear
D input
Clockor prese

IIH

VCC=MAX,

VI-2.7V

Clear
D input
Clockor prese

IlL

Vcc=MAX,

VI=O.4V

Clear
-15

lost

Vcc=MAX

Icctt

Vcc-MAX,

V

-1.5

-1.5

V

2.7
0.4

..

3.4

V

0.25

0.4

0.35

0.50

0.1

0.1

0.2

0.2

0.3

0.3

20

20

40

40

60

60

-0.4

-0.4

-0.8

-0.8

-1.2

-1.2

-100
4

V
0.8

IIOL =8mA

D input
Clock or prese

II

Unit

0.7

3.4
0.25

IloL=4mA

9LS/74LS
Typ·· Mex

-15
4

8

V

mA

/lA

mA

-100

mA

8

rnA

'For condItions shown as MIN or MAX, use the approproate value spaclfled under recommended operatIng conditIons for the appiocable
device type.
"AII typical values
at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
tt ICC is measured with outputs open with D, clock, and preset grounded; then with D, clock, and clear grounded.

are

Switching Characteristics, Vee
Parameter

From
(Input)

= 5V Over Recommended Free-Air Temperature Range
_55°C

To
(Output)

Min.

Typ.

+25°C
Max.

Min.

Typ.

30

45

Units

+125°C
Max.

Min.

Typ.

Max.

Test Conditions: C L = 15pF, RL = 2kn (See Figure A. page 2-174)
f max
tpLH

maximum

clock
frequency

MHz

set or clear

QorO

12

18

10

15

16

23

I CK Low

set or clear

QorQ

22

29

18

24

21

28

tpHL I CKHigh

set or clear

QorQ

29

39

26

35

27

38

tpHL

clock

QorQ

13

20

12

18

13

20

ns

tpHL

clock

QerO:

17

27

14

22

15

24

ns

ns

Test Conditions: CL = 50pF, RL

ns
ns

=2kn (See Figure A, page 2-174)
16

22

13

19

I CK Low
tpHL

19

26

set or clear

QorQ

26

33

21

27

24

31

CK High

set or clear

QorQ

33

44

29

38

30

41

tpLH

clock

QorQ

17

24

15

22

16

25

ns

tpHL

clock

QorQ

22

31

18

26

19

28

ns

tpLH

I

ns

Note: AC specification shown under -5SoC and +12SoC are for 9LS devices only_ All 50pF specifications
are for 9LS only.

~YTHEo!)

2-29

4-Bit Bistable Latches

LS75 LS77
DESCRIPTION
These latches are ideally suited for use as temporary
storage for binary information between processing units
and' input/output or indicator units. Information present
at a data (D) input is transferred to the Q output when the
enable (G) is high and the Q output will follow the data
input as long as the enable remains high. When the enable
goes low, the information (that was present at the data input at the time the transition occurred) is retained at the
Q output until the enable is permitted to go high.

These circuits are completely compatible with all popular
TTL or DTL families. All inputs are diode-clamped to
minimize transmission-line effects and simplify system
design.
FUNCTION TABLE
(Each Latch)
OUTPUTS
INPUTS

The LS75 feature complementary Q and Q outputs from a
4-bit latch, and is available in various 16-pin packages. For
higher component density applications, the 'LS77 4-bit
latcl'l is available in 14-flin flat packages.

0

G

Q

Q

L

H

L

H

H

H

H

L

X

L

QO

QO

H = high level, L = low level, X = Irrelevent
of Q before the high-to-Iow transition of G

Co '= the level
LS75
10

3 2 1161514

4

20

2(1

3(1

30

40

13
12 GND

Vee 5

67891011

10
logic: see function table

Die Size .065 x .059

LS77

2 1

10

20

1-2

30

40

1413

3

12
11 GND

Vee 4

5 6 7 8 9 10

Ne

3D

10

Ne

40

logic: see function table

Die Size .065 x .059

FUNCTIONAL BLOCK DIAGRAMS leach latch)
'LS75

DATA~
TO
OTHER
LATCH
ENABLE

2-30

1

'LS77

iJ

DATA~

(1
O

'

O;~ER

0

LATCH
ENABLE

[[AYTHE@J

4-Bit Bistable Latches

LS75

LS77

Recommended Operating Conditions
9LS/54LS
MIN
Supply voltage, Vee

4.5

NOM
5

High·level output current, IOH

9LS/74LS

MAX

MIN

5.5

4.75

NOM

MAX

5

-400

Low-level output cu rrent, 10 L

4

Unit

5.25

V

-400

I'A

8

mA

Width of enabling pulse, tw

20

20

ns

Setup time" tsu
Hold time, th

20

20

ns

0

0

Operating free-air temperature, T A

-55

125

ns

0

70

°e

Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
(Unless Otherwise Noted)
PARAMETER
VIH

High·level input voltage

VIL

Low-level input voltage

VI"

Input clamp voltage

1i0H High-level output'voltage
VOL

Low-level output voltage
Input current at

II

maximum input voltage

High-level input current

IIH

Low-level input current

IlL

Short-circuit

lOS
lee

output currentp

Suppl y cu rrent

9LS/54LS

TEST eONDITIONSt

MIN

TYPt

9LS/74LS
MAX

2
Vee-MIN,

11~-8mA

Vee-MIN,

VIH-2 V,

VI L ~VI L max,IOH=-440 I'A
Vee~MIN,

VIL~VIL

VIW 2V,

Vee=MAX, VI=7 V

Vee=MAX,

VI~2.7

VI~O.4

V
V

See Note 1

V
V

-1.5

-1.5

V

3.5

2.7
0.4

3.5

V

0.25

0.4

0.35

0.5

D input

0.1

0.1

0.4

0.4

D input

20

20

G input

80

80

D input

-0.4

-0.4

G input

-1.6

-1.6

-100

-15

Unit

0.8

G input

Vee~MAX

Vee~MAX,

MAX

2

0.25

10L=4 mA

TYP:\:

0.7

10L ~8 mA

max

VecMAX,

2.5

MIN

'LS75

6.3

12

'LS77

6.9

13

-100

-15
6.3

12

t

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

:\:

All typical values are at Vee = 5 V, T A = 25°e.

p

Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

V
mA
I'A
mA
mA
mA

NOTE 1: lee is tested with all input grounded and all outputs open.

~YTHEO:El

2-31

4-Bit Bistable Latches

LS75 LS77

SwItChing Characteristics Vee = 5.0V Over Recommended F......Alr Temperature RaQge.
91.8/541.875

Parameter
TMt CondItIon: C L

From

To

(Input)

(Output)

tPLH
tPHL
tPLH
tpHL
tpLH
tpHL
tPLH
tPHL

Min.

Typ.

+25°C
Max.

Min.

Typ.

D

Q

D

Q

G

Q

G

Q

-

18
12
15
10
18
17
19
10

31
16
19
14
22
21
23
14

15
9
12
7
i5
14
16
7

Unit

+125°C
Max.

Min.

Typ.

Max.

,

= 15pF, R.. = 2.Ok (Sea fig. A, page 2-174 and fig. 1, page 2-32)

tPLH
tPLH
tpHL
tpHL
tPLH
tPHL
tPLH
tPHL
T..t Condition: C L

-55°C

27
17
20
15
27
25
30
15

18
12
15
10.
18
17
19
10

31
16
19
14
22
21
?3
14

22
16
19
14
22
21
23
14

37
22
25
20
28
27
29
20

ns

ns

ns

ns

= 5OpF; RL = 2.Ok (Sea fig. A, page 2-174. and fig. 1, page 2-32)

.

D

Q

D

Q

G

Q

G

Q

22
16
19
14
22
21
23
14

37
22
25
20
28
27
29
20

19
13
16
11
19
18
20
11

33
18
21
16
24,
23
25
16

ns
ns
ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS deOices only. All 50pF specifications are for 9LS devices only.

,SWitching Characteristics Vee = 5.0V Over Recommended Free-Air Temperature Range.
91-8/54L877

Parameter

From
. (Input)

TMt CondltlCJtla: C L
tpLH

(Output)

tpHL

TMt ConcIItI_: C L
tPLH

D

Q

G

Q

tpHI-

Typ.

Max.

Min.

Typ.

+125°C
Max.

Min.

Typ.

Unit

Max.

15
12
13
13

24
20
21
21

11
9
10
10

19
17
18
18

14
12
13
13

23
20
21
21

18
17
18
18

28
26
27
27

ns

ns

= 5OpF, RL = 2.Ok (Sea fig. A, page 2-174 and fig. 1, page 2-32)
D

Q

G

Q

17

16

tpHItpLH

Min.

+25°C

= 15pF, RL = 2.Ok (Sea Fig. A, page 2-174 and fig. 1 page 2-32)

tpHL
tpLH

-55°C

To

17

17

28
26
27
27

15
13
14
14

24
22
23
23

ns

ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications are for 9LS devices only.

2·32

~YTHEc31

4-Bit Bistable Latches

LS75 Lsn

PARAMETER MEASUREMENT INFORMATION

--- --OUTPUTS

INPUTS

o

G

Q

VCC

a

1

PULSE
GENERATOR
A
(See Note A)

RL:>

l~

...

a

PULSE
GENERATOR
B
(See Note A)

~

. .. ...

RL

(See Note C)

1; (See Note B)

.-G

~

:

... ~

Q

0

,....

... .. ...

I

f----

-'- CL
(See Note B)

J.

.....

TEST CIRCUIT

1 ~s

---j

I ' 90%
I I Vref

o INPUT

10%

I--I

---I

,

I

~< 10 ns

k - - tsetup

II

I

~I-I--.~'!!l'!s____

90%

90%

I

-------.I

I

' - - 500 ns ~ 500 ns = . j
~tPLH
I
':=:!tPHL

:

,

Vref

L : ~.,
I

~
,..

I

I

:--!I
I

tP\H

:I

\l~ref
,

OV

r___
-

- -- -

H
VVOOI

.

'--_ _ _ _ _ _ _-J

....

~

'--_ _ _ J _ -

,.t-----.,•

"HC

I-

.1

____'r-_ _ _ 3V

I

I
10%

+.
:T

ov

I

_~.!.h~d~

i

I

a

I

,

I

OUTPUT

I

1 , . - - - - - - 3V

I:
I
Vref
I
I
I 10%
tsetup --t.thold..,1 '--_ _ _ _ _ _ _ _ _ _J_I - - - - - - - - -

: - - tPHIL

OUTPUTQ

--I

I

1 ' - - < 10ns

90%

---+---,GINPUT
(See Note 0)

--1

11---< 10ns

.-IIt--tPHL

y v r r - e f - - - - - - - " ' " " " \ - - - VOH

.

~~

tPLH
VOLTAGE WAVEFORMS
FIGURE 1.

NOTES: A. The pulse generators have the following characteristics: Zout '" 50 SJ.; for pulse generator A, PRR<;500 kHz; for pulse
generator B, PRR~1 MHz. Positions of D and G input pulses are varied with respect to each other to verify setup times.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064.
O. When measuring propagation delay times from the 0 input, the corresponding G input must be held high.
E. Vref = 1.3 V.
t Complementary Q outputs are on the 'LS75 only.

t;YTHEO]J

2-33

Dual J-K Negative-Edge-Triggered
Flip-Flops

LS78

. DESCRIPTION·
These monolithic dual J-K edge-triggered flip-flops feature
individual J, K, and preset inputs plus common clock and
common clear inputs. The preset or clear inputs, when low,
set or reset the outputs regardless of the levels at the other
inputs. When preset and clear inputs are inactive (high), a
high level at the clock input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs
. may be allowed to change when the clock pulse is high and
the bistable will perform according to the function table as
long as minimum setup and hold times are observed. Input
data is transferred to the outputs on the negative-going edge
of the clock pulse.
LOGIC DIAGRAM f'h).

Q

PR.S.T·_+-__..-_---'

g

FUNCTION TABLE
(EACH FLIP-FLOP)
INPU

UTPUTS

PRESET CLEAR CLOCK
L
H
X
X
L.
H
X
L.
L.

i

H
H
H
H
H

•••

H
H
H
H
H

t

H

J

K

Q

X
X
X

X
X
X

H

L.

L.
W

H
H'

L.

L.
L

H
H

H
H

X

X

L.

Q

ao 50

H
L.
L
H
TOGGL.E

ao 50

H = high level (steady state)
L = low level (steady stete)

X = don't care
~ = transition from high to low level
O. = the level 01 0 before the indicated steady-state input conditions were
established.
TOGGLE: Each output changes to the complement 01 its previous level
on aach ~ ctock transition.
·This configuration is nonstable; that Is. it will not persist when preset
and clear Inputs retum to their Inactive (high) level.

L---t---l1>--CLEAR

TO OTHER
FLlP·FLOP

12 11 10

LS114

PIN-OUT DIAGRAMS

LS78

876

5

LS114

·13
14
1

3 4 5.
Die·Size .060 x .DEia!

Recommended Operating Conditions
Min

4.5

Supply voltage, Vee
Normalized fan-out from each output, N
Clock frequency, fclock
Width of clock pulse, tw(clock) (High)
Width of preset pulse, tw(presetl (Low)
Width of clear pulse, tw(cisari (Low)
Input setup time, tsetup
Input hold time, thnlrl
Operating free-air temperature, T A

I High logic level

I Low logic level

0
15
15
15
15
0
-55

9LS/54LS
Nom
Max

5

5.5
20
10
35

125

9LS174LS

Min

Nom

Max

4.75

5

5.25
20
20
35

0
15
15
15
15
0
0

Unit
V

MHz
ns
ns
ns
ns
ns

70

°c

tsetup is the minimum time required for the correct logiC level to be present at the J or K input prior to the falling edge of the clock in order
to be recognized and transferred to the outputs.
thold is the minimum time required for the logic level to be maintained at the J or K input after the falling edge of the clock in order to
insure recognition. These devices require no hold time.

2-34

~YTHEO:3l

Dual J-K Negative-Edge-Triggered

Flip-Flops.

LS78 LS114

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Val

III

9LS/54LS
Typ"" Max

Min

Jar K
Preset
Clear
Clock
Jar K
Preset
Clear
Clock
Jar K
Preset
Clear
Clock

lost
Icc tt

VCC=MAX,

9LS/74LS
Typ"" Max

2
0.7
-1.5

11=-18rnA
Vcc-MIN,
Vcc-MIN,
VIH-2V,
Vcc=Vllrnax,loH=-400tlA
VCc=MIN,
VIH=2V,
IIOL =4rnA
Vll=Vllrnax
Iiol =BrnA

VOH

IIH

Min
2

VIH
Vil
VI

II

Test Conditions"

2.5

0.8
-1.5

3.4

2.7

0.25

3.4

0.4

0.25
0.35

0.1
0.3
0.6
0.8

VI=7V

20
VCC=MAX,

VI=2.7V

Vcc=MAX,

VI=O.4V

60
120
160
-0.4
-0.8
-1.6
-1.6
-15

Vcc=MAX
Vcc-MAX,

-100
4

-15

B

4

Unit
V
V
V
V

0.4
0.5
0.1
0.3
0.6
0.8
20
60
120
160
-0.4
-O.B
-1.6
-.1.6
-100
8

V

rnA

tlA

rnA

rnA
rnA

"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"'AII typical values are at Vee = 5V, T A = 25°C.
tNot mar. than one output should be shorted at a time.
tt ICC is measured with outputs open, with clock, J, K, and clear grounded and preset at 4.5V; then with clock, J, K, and· preset grounded
and clear at 4.5V.

Switching Characteristics, Vee
Parameter

From

(Input)
Test Conditions: C l

= 15pF, Rl =2kf!
maximum clock

clear or

tpHL

preset

+25°C

Typ. Max.

Min.

+125°C

Typ. Max. Min.

Units

Typ. Max.

(See Figure A. page 2-174)
35

clock

OorO
OorO

tpHl
Test Conditions: C l

= 50pF. RL = 2kf!

tpLH

clear or

tpHl

preset

tpHI,.

Min.

MHz

50

frequency

tplH

tpLH

_55°C

To
(Output)

f max

tplH

= 5V Over Recommended Free-Air Temperature Range

clock

8

12

8

12

11

15

ns

15

19

13

17

13

17

ns

8

12

8

12

11

15

ns

14

19

13

18

13

18

ns

10

14

13

17

ns

(See Figure A. page 2-174)

oora

OorO

10

14

19

24

16

21

16

21

ns

9

14

10

14

13

18

ns

19

24

17

21

17

22

ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS only.

~YTHEO]J

2-35

4-Bit Binary Full Adders With Fast Carry

LS83A

LS283

PIN-OUT DIAGRAMS

DESCRIPTION
These improved full adders perform the addition of two
4-bit binary numbers. The sum (k) outputs are provided for
each bit,.and the resultant carry (C4) is obtained from the
fourth bit. These adders feature full internal look ahead
across all four bits generating the carry term in ten nanoseconds typically. This provides the system designer with
partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation.
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.
The LS83A and the LS283 are identical in performance;
only the pin out is different. They are designed to replace
the 5483A and the 54283 respectively. The LS283 is
recommended for new designs, Vee and ground on corner
pins simplify board layout.

12111098

LS83A

13
14

Ole Size .Ull"2")(l)68

15 16

1

2

Die Size .062 x .068

FUNCTION TABLE
LOGIC DIAGRAM

OUTPUT

%
%
1%i% %%%% %
CO = L

)-----C4

A 4 - -........,

:£4

%~
A3

:£3

83

L

A4

WHEN
C2= L

84

L

L

WHEN
C2=H

~

C4

H

L

L

L

L
H

L

H

L

L

H

H

H

L

L
L

L

A3---<-r

CO= H

INPUT

L

L

H

C4

L
H

L

H

L.
L

L

L

L

L
H

L
L

L
H

H

L

L

L

H

L
L

H

L

H

H

L

H

L

H

L

H

H

L

L

L

H
H

L

H

H

L

H

H

L

L

L

H

H

H

L

L

H

H

L

H

L

L

L

H

L

L
H

L

H

H

L

H

L

L

H

H

H

L

L

L

H

B1-fr{r-t==!::::;Ck_ _,

L

H

L

H

H

H

L

L

L

H

H

H

L

H

L

L

H

H

L

H

A 1 - -........r

L

L

H

H

L

L

H

H

L

H

CO---D----'

H

H

H

H

L

H

L

H

H

L

L
H

H

H

H

H

H

H

H

H

L

L
H

H

H

L
H
. -

H

H

H

H = high level. L = low level
NOTE:

Input conditons at Al, B1, A2, 82, and CO are used to determine outputs :El and I:2 and the value of the internal
carry C2. The values at C2, A2, 83, A4, and 84 are then
used to determine outputs :E3, I:4, and C4.

2-36

~YTHE?EJ

LS83A

4-Bit Binary Full Adders With Fast Carry

LS283

Recommended Operating Conditions
Min
4.5

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, T A

9LS/S4LS
Nom
Max
5

-55

5.5
. 400
4
125

Min

9LS/74LS
Nom
Max

4.75

5

0

5.25
400
8
70

Unit
V
/lA
mA

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Test Conditions·

Min

V IH
V IL

2

VO H
VOL

IIH
IlL

VIL=VILmax
Any A or B
co
Any A or B
co
Any A or B
co

Min
2

2.5

3.4

0.8
-1.5
2.7

0.25

0.4

VI=7V

Vee=MAX,

VI=2.7V

Vee=MAX,

V I =O.4V

3.4
0.25
0.35

Ilo L -8mA

Vee=MAX,

9LS/74LS
Typ·· Max

0.7
-1.5

II --18mA
Vee-MIN,
Vee MIN,
V IH -2V
V IL ~VILmax, IOH=-400/lA
V IH -2V,
Vee-MIN,
IIOL =4mA

VI

II

9LS/S4LS
Typ·· Max

0.2
0.1
40
20
-0.8
-0.4

Unit
V
V
V
V

0.4
0.5
0.2
0.1
40
20
-0.8
-0.4

V
mA
/lA
mA

-100
-15
-100
mA
-15
All inputs grounded
22
39
22
39
Vee=MAX,
All 8 low, other inputs at 4.5V
34
19
19
34
mA
Icc
Outputs open
19
34
19
34
All inputs at 4.5V
.
..
.. for the applicable
'For cond,tions shown as MIN or MAX, use the appropriate value specIfIed under recommendea operatong condItIons
device type .
• 'All typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
Vee=MAX

lost

.

-

Switching Characteristics , V'cc- 5V Over Recommended Free Air Temperature Range
Parameter
Test Conditions: CL
tpLH
tpHL
tpLH
tpHL
tPLH
tpHL
tpLH
tpHL
,est Conditions: CL

From
(input)

To
(output)

= 15pF, RL = 2k!l (See Fig.
CO
Ai or 8i
CO
Ai or Bi

-SsoC
Min

Typ

~

Min

+2SoC
Typ

A, page 2-174)

15
15
20
~i
19
9
C4
9
9
C4
10
= 2kO (See Fig. A, page 2-174)
16
Any ~
19
25
~i
24
11
C4
12
11
C4
13
Any

Max

Miix

Min

+12SoC
Typ
Max

..

20
21
30
29
14
14
15
14

14
16
18
15

7
9
8
9

-.

19
22
24
24
12
13
13
14

15
20
21
17
11
11
11
11

21
27
27
25
18
16
17
16

= SOpF, RL
;w
15
21
11
:.l:.l
tpLH
CO
19
25
25
25
30
tpHL
26
25
32
18
32
tpLH
Ai or Bi
18
26
25
31
30
tpHL
10
15
12
19
16
tpLH
CO
18
10
16
13
17
tpHL
10
15
13
19
17
tpLH
Ai or Bi
14
20
18
12
16
tpHL
0
0
NOTE: Ae specification shown under -55 e and +125 e are for 9LS devices only. All 50pF specifications are for 9LS only.

~YTHE~

Unit

ns
ns
ns
ns

ns
ns
ns
ns

2-37

4-Bit Magnitude Comparators

LS85

PIN-OUT AND LOGIC DIAGRAM

DESCRIPTION
These four-bit magnitude. comparators perform comparison
of straight binary and straight BCD (8-4-2-1) codes. Three
fully decoded decisions about two 4-bit words (A,B) are
made and are externally available at three outputs. These
devices are fully expandable to any number of bits without
external gates. Words of greater length may be compared by
connecting comparators in cascade_ The A > B, A < B, and
A = B outputs of a stage handling less-significant bits are
connected to the corresponding A > B, A < B, and A =B
inputs of the next stage handling more-significant bits. The
stage handling the least-significant bits must have a highlevel voltage applied to the A = B input. The cascading paths
of the '85, and 'LS85 are implemented with only a two-gatelevel delay to reduce overall comparison times for long
words. An alternate method of cascading which further
reduces the comparison time is shown in the typical
application data.

LS85
DATA INPUTS

r -_ _

~A'-

__

~

2

1
16
15
14

7m

DATA 'ABA>BA=BAB

.AB

AB3

X

X

X

X

X

X

H

L

L

A3B2

X

X

X

X

X

H

L

L

A3=B3

A2Bl

X

X

X

X

H

L

L

A3=B3

A2=B2

A1BO

X

X

X

H

L

L

A3=B3

A2= B2

A1 =Bl

AO8

Al

1131
1141

121
131
141

(12)
(11)

81

n~

I

1

.....
t-<
p--

:gp---

J

~--(6)A_8

I

1

-

AD

(10)

BO

19)

D-

~YTHEO~

2-39

4-Bit Magnitude Comparators

LS85
Recommended Operating Conditions

9LS/54LS

Supply voltage, Vee
High-level output current, IOH
Low-level output current, 1m
Operating free-air temperature, T A

9LS/74LS

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
-400
4
125

4.75

5

5.25
-400
8
70

-55

0

Unit

V
IlA
mA

°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
. Paramlttsr

VIH
VIL
VI
VOH
VOL

Test Conditions·

9LS/54LS
Typ··
Max

Vee=MIN,
Vee-MIN,
V,L =V,Lmax,
Vee-MIN,
V,L =V,Lmax

Vee=MAX
Vec=MAX,

11--18mA
VIH=2V,
IOH=-4OOIlA
[IOL =4mA
V'H=2V,
IloL=8mA

Min

2

2

I, AB inputs Vee=MAX,
all other inputs
AB inputs
I'H all other inputs Vee=MAX,
AB inputs
I,L
Vee=MAX,
all other inputs

lost

Min

9LS/74LS
Typ·· Max
'.

0.7
-1.5
2.5

3.4
0.25

V,=7V
V,=2.7V
V,=O.4V
-15

0,8
-1.5
2.7

0.4
0.1
0.3
20
60
-0.4
-1.2
-100
20

-15

V
V
V
V

3.4
0.25
0.35

Unit

0.4
0.5
0.1
0.3
20
60
-0.4
-1.2
-100

V
mA
IlA
mA

mA
10.4
20
mA
'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device tYpe.
"AII typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a til"(le.
ttlee is measured with outputs open, A = B grounded, and all other inputs at 4.5V.
I ectt

2-40

10.4

~YTHEO]]

4-Bit Magnitude Comparators
Switching Characteristics, Vee
Parameter

From
(Input)

Test Conditions: CL

tPLH

= 5V Over Recommended Free-Air Temperature Range

No. of
-55°C
Gate
Typ
Levels Min
~ 2kO (See Fig. A, page 2-174)

To
(output)

= 15pF, RL

Any A or B
data input

AB
A=B

tpHl
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

Any A or B
data input
AB or AA>B or A =

Test Conditions: CL

tpLH

AB
A=B
A>B
A>B
A-B
A-B
AB or A A>B or A -

B
B

B
B

1
2
3
4
1
2
3
4
1
1
2
2
1
1

Max

14
20
25

42

28
11
15
21
22
14
12
13
14
16
12

50

34
48
27
23
23
30
26
21

Min

+25°C
Typ

14
19
24
27
11
15
20
23
14
11
13
13
14
11

Max

36
45

30
45
22

17
20
26
22
17

Min

+125°C
Typ

14
19
24
26
12
16
20
22
14
11
12
14
15
11

Max

41
48

33
48
27
22
22
30
25
20

I

Unit

ns

ns

ns
ns
ns
ns
ns
ns

= 2kO (See Fig. A, page 2-174)

AB

1
2
3

A=B

~

LS85

AB

4
1
2
3

A=B
A>B
A>B
A-B
A-B
A

INPUT A .:..(1;.:.4:..;",,-14,;.:.1_ _-01>

INPUT B ~(1.:..1_ _t.11ct>

INPUT B .;.(1_1.;.(8_1_ _+.q:.

(81 0C
(91 0C

81 (101

(81 0D

(111(121

°c

°D

LOGIC DIAGRAMS

~YTHEO~

2-45

LS90

Decade, Divide-by-Twelve, and
Binary Counters

LS92 LS93

Recommended Operating Conditions
. Min
Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL

4.5

-",_Input
B input
A input
B input
Reset inputs

Count frequency, count (see Figure 1 on 2-46)
Pulse width, tw
Reset inactive-state setup time, t setup
Qperating free-air temperature, T A

9.LS/54LS
Nom
Max
5

Min

9LS/74LS
Nom
Max

5.5
-400
4

4.75

u

~;!

u

;S;!

0
15
30
15
25
-55

16

0
15
30
15
25
0

16

125

;;5

5.25
-400
8

Unit
V
/.J. A
rnA
MHz

ns

70

ns
C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Teat Con"ltIons·

9 LS/54 LS90/92
Typ·· Max
Min

2

2

VIH
VIL
VI
VOH
VOL
Any reset
A input
B input
Any reset
A input
Binput
Any reset
A input
B input

Vee~MIN,

11~-18mA

Vee-MIN,
V IL ~VILmax,
Vee-MIN,
VIL ~VILrnax,
Vee-MAX,

VIH~2V,

0.7
-1.5
2.5

IOH~-400/.J.A

VIH-2V,
VI-7V

9LS/74LS90/92
Max
Min Typ"

IloL -4mA~
IloL-8mA~

2.7

3.4
0.25

0.8
-1.5

0.4
0.1

3.4
0.25
0.35

Unit
V
V
V
V

0.4
0.5
0.1

V

rnA
0.2
0.2
0.4
0.4
20
20
40
VI~2.7V
40
/.J.A
Vee~MAX,
IIH
80
-0.4
-0.4
-2.4
-2.4
rnA
VI~O.4V
Vee~MAX,
IlL
-3.2
-3.2
rnA
-100 -15
-15
-100
Vee~MAX
lost
15
15
9
9
I LS90
rnA
Vee~MAX,
lee tt
15
15
9
I LS92
9
"For conditions shown as MIN or MAX, use the appropriate value specified under recommendea operating conditions for the applicable
device wpe .
. ,"AII !ypical velues are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
tt lee is measured with all outputs opel\ both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
~ Outputs are tested at specified IOL plus the limit value of II L for the B input. This permits driving the B input while maintaining full fan-out
capability.
II

2-46

Vcc~MAX,

VI~5.5V

aD

~YTHEO!1

Decade, Divide-by-Twelve, and
Binary Counters

LS90 LS92 LS93

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
. Parameter

Test Conditions·

9 LS/54 LS93
Min

Typ··

2

V,H
V,
VOH

Vee-MIN,

11;-18rnA

Vee;MIN,

VIW2V ,

Vee-MIN,

VOL

VIH-2V,

Ii0L -4rnA~1

Typ··

Max

V
0.8

V

-1.5

-1.5

V

3.4
0.25

2.7
0.4

3.4

V

0.25

0.4

0.35

0.5

Any reset

Vee-MAX,

VI=7V

0.1

0.1

A or B input

Vee-MAX,

VI;5.5V

0.2

0.2

Vee;MAX,

VI;2.7V

Vee;MAX,

VI;O.4V

Any reset
A or B input
Any reset
IlL

A input
B input

lost

Vee;MAX

-15

Unit

0.7

110L, -8rnA~

VIL ;VILrnax

IIH

2.5

VIL ;VILrnax, loW-400J.lA

Min
2

V,L

'I

9 LSI14 LS93

Max

20

20

40
-0.4

40

V
rnA
J.lA

-0.4

-2.4

-2.4

rnA

-1.6

-1.6
-100

rnA

-100

-15

Vee-MAX,
9
15
9
15
rnA
'ed t
'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"All typical values are at Vee = 5 V, T A = 25° e.
tNot more than one output should be shorted at a time.
tt lec is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
~Outputs are tested at specified 10L plus the limit value of IlL for the B input. This permits driving the B input while maintai.ning full fan-out
capability.

~YTHEO}J

2-47

LS90

LS92

Decade, Divide-by-Twelve, and
Binary Counters

LS93

.

Switching Characteristics, V'cc.- 5V Over Recommended Free Air Temperature Range
Par.meter
Teat Condition.: CL

From
(input)

= 15pF, RL =

To
(output)

A

B

LS90

A

OA

LS92

A

OA

LS93

A

OA

LS90

A

OD

LS92

A

OD

LS93

A

OD

LS90

B

08

LS92

B

08

LS93

B

08

LS90

B

Oc

~
tpHL

LS92

B

Oc

I tPLH

LS93

B

Oc

LS90

B

OD

LS92

B

OD

"tPHL

LS93

B

OD

tpHL
tpHL
tpHL
tpLH

LS90
LS92
LS93

Set·to-O
Set-to-O
Set-to-O
Set-.to-9

Any
Any
Any
OA,OD
08,OC

LS90

f max

LS92

f max

LS93

..!e1tL

tpHL
I tPLH
tpHL
tpLH
I tpHL
tPLH
I tpHL
I tpLH
tpHL
I tpLH
tpHL
tPLH
I tpHL
tpLH
I tpHL
I tplH

tpHL
tpLH
I tpHL

tpHL
tPLH

~
tpLH

~
tpLH

~
Note:

2-48

LS90

Min

Typ

+2SDC

I
Max

Min

Typ

';' +12SDC

I
Max

Min

Typ

Max

Unit

2kO (See Fig. A, P!1118 2·174 and Fig. 1, page 2-49)

OA
08
OA
OR
OA
08

f max

-SSDC

B

A
B

A

AC specification shown under -55
are for 9LS only.

o

32
16
32
16
32
16
13
15
13
15
13
15
35
37
35
37
49
49
13
17

13
17

13
17
24
27
13
17
24
27
24
27
24
27
38
38
30
30
30
;14
24
0

C and +125 C are

for

9LS

20
22
20
22
20
22
51
56
54
56
76
76
20
27
20
27
20
27
39
42
20
27
39
41
39
41
39
41
57
57
47
47
47
35
47

devices only.

MHz

42

MHz

42
10
12
10
12
10
12
32
34
32
34
46
46
10
14
10
14
10
14
21
23
10
14
21
23
21
23
21
23
34
34
26
26
26
20
26

All

'"

42

MHz

16
18
16
18
16
18
48
50
48
50
70
70
16
21
16
21
16
21
32
35
16
21
32
35
32
35
32
35
51
51
40·
40
40
30
24

13
15
13
15
13
15
35
37
35
37
49
49
13
17
13
17

13
17
24
27
13
17

24
27
24
27
24
27
38
38
30
30
30
24
24

20
22
20
22
20
22
51
56
54
56
76
76
20
27
20
27
20
27
39
42
20
27
39
41
39
41
39
41
57
57
47
47
47
35
47

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

50pF specifications

~YTHE03l

J~~ecade, Divide-by-Twelve,
_~i"-ary Coul1t~rs

and
LS90

,

LS92

LS93

Switching Characteristics , V'cc- 5V Over Recommended Free-Air Temperature Range
Parameter
,T..t Condition.: C,

...!fbtL
tPHL

~
tpHL
tpLH

tP"HL
I tpLH
tpHL
I tpLH
tpHL
I tPLH
tpHL
I tPLH
tpHL
'tPLH
I tpHL
tpLH
I tPHL

From
(Input)

To
(output)

A

OA

LS92

A

OA

LS93

A

OA

LS90

A

OD

LS92

A

OD

LS93

A

OD

LS92

B
B

Os
Os

LS93

B

Os

LS90

B

Oc

LS92

B

Oc

~

LS93

B

Oc

~
tpHL

LS90

B

OD

I tpLH
tPHL

LS92

B

OD

~
tPHL
tpLH

t;;HL
tpLH

~
tpHL

LS93

B

OD

tpHL
tpHL
tpHL
tpLH

LS90
LS92
LS93

Set-to-O
Set-to-O
Set-to-O
Set-to-9

Any
Any
Any

tPHL

LS90

Min

OA,OD
Os,Oc

Note: AC specification shown under _55°C and +125°C are for
are for 9LS only.

~YTHE~

Typ

Max

Min

+2SDC
Typ

Max

I

Min

+12SDC
Typ

Max

Unit

= SOpF. R, = 2kO (See fig. A, page 2-174 and fig. 1, page 2-49)

LS90

LS90

-SSDC

17
19
17
19
17
19
39
41
39
41
53
53
17

19
17

19
17
41
29
30
17

19
29
30
29
30
29
30
43
43
33
33
33
28
33
9LS

25
27
25
27
25
27
56
58
56
58
82
82
25
27
25
27
25
27
41
42
25
27
41
42
41
42
41
42
63
62
50
50
50
40
49

14
16
14
16
14
16
36
38
36
38
50
50
14
16
14
16
14
16
26
27
14
16
26
27
26
27
26
27
40
40
30
30
30
25
30

21
23
21
23
21
23
52
54
52
54
78
78
21
23
21

23
21
23
37
38
21
23
37
38

37
38
37
38

58
58
46
46
46
36
45

17
19
17
19
17
19
39
41
39
41
53
53
17
19
17
19
17

19
29
30
17
19
29
30
29
30
29
30
43
43
33
33
33
28
33

25
27
25
27
25
27
56
58
56
58
82
82
25
27

25
27
25
27
41
42
25
27
41
42
41
42
41
42
62
62
50
50
50
40
49

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

devices only. All 50pF specifications

2-49

LS90

LS92

LS93

---------------------------------w
V
r.,

RESET TO 9
INPUTS
(SEE NorE 8)
CLOCK &

Decade, Divide-by-Twelve, and
Binary Counters

'-----------------~~------------------~>,~-----------------OV
1

i-----".tup

---.L...------..J0~r.~

(SE~'::~;E B)

•

-

1

:

1

1--",luP..:..l

1

.

~-

-

>j

I-

-

-

-

•1

-

-

-

-

-

-,; -

Iw(clock)

-- -

-

-

- -

::

I

r--"l.v ~V'.f I \ . r-\.;.----3V
:
/
r:.:;~
~;~~ ~
~
R~~;~i~ ----I:-I.---.I--IP-l-H~:----.-I-I-PHl
~ ME~~~RE
~ ME~i~RE yr!
IplH

U

~

I

OUTPUT DA

I

!.r.~T

I\.,

TVre,
I,Vrel
I
I
OUTPUT DB ____~I--"'\ PHl !+--+j-lpHl
II
-!...",,\I

ClOC;~~NPUT---i,--..J

I

r---+-

\,V rel
I
r--+t-lpHl

IPHl
--~!-"'\X,
",,\1
:
,Vrel
:
~Vrel
I
I
IPlHi-----I
IpHl i+-+i
I
1

- ..

I'

OUTPUT 0 0

---..1fv

,-Vrel
.

i

\:rel

I

OUTPUT DC

ref

rei

\v

rei

11

In+l I :
.:
I
I
I
:
I
II
'

:

r'> ~I
_ _ _
VUH

AT In+2

\ . Vrel
I .
1-. ~
I,
:

/
IpHl
. MEASURE
AT In+2

Iv
)

(I
re'
IplH

~ ~~A~URE

I
I
I

Iv
I

n-4

re,
{f
~
IplH MEASURE ATln+8 \I~
lS90 & lS93 oral
In+6lS92A
/1 V
{ J '
rei

,'.,'

{j

:
I

I Vrel
I

V
Ol
I
IpHl . MEASURE AT In+4
"I--VO H
::
I
I
\ . : VOL
IpHl MEASURE AT In+8
,~ __ V
lS92 oral
:
'iVref OH In_S lS92
I
'\:.:.: VOL
~)-IPHl MEASURE ATl n+10
I•
I
lS9U I
~V VOH
In+12alS92 or al
re~Ol In+16lS93

r--.t

~Vrel

I.

1--:1)-

NOTES: A. Input pulses are supplied by a generator having the following characteristics:
t r ... 15ns, tf ... 5ns, PRR = 1 MHz, duty cycle = 50%, Zout = 50 ohms
B. Each reset input is tested separately with the other reset at 4.5V.
C. Reference waveforms are shown with dashed lines.
FIGURE 1. VOLTAGE WAVEFORMS

2·50

~YTHE~

8-Bit Shift Registers

LS91

FEATURES

PIN-OUT DIAGRAM

•

For Use In Digital Computer Systems

DUAL·IN-LiNE PACKAGE

•

For Use In Data-Handling Systems

•

For Use In Control Systems

CK

NC

IT]
CLOCK

DESCRIPTION

These monolithic serial-in, serial-out, 8-bit shift registers
utilize transistor-transistor logic (TTL) circuits and are composed of eight R-S master-slave flip-flops, input gating, and
a clock driver_ Single-rail data and input control are gated
through inputs A and B and an internal inverter to form the
complementary inputs to the first bit of the shift register.
Drive for the internal common clock line is provided by an
inverting clock driver. This clock pulse inverter/driver causes
these circuits to shift information one bit on the positive
edge of an input clock pulse.

~000000
NC

NC

NC

NC

VCC

NC

FLAT PACKAGE
CK

FUNCTION TABLE
Inputs
ATtn
A

B

H
L

H

X

X

L

NC

IT]

Outputs
ATt n+8
QH
H
L
L

NC

positive logic: see function table

QH
H
H
H

H = high, L = low,

x = irrelevant

tn = Reference bit time, clock low
tn+8 = Bit time after 8
low-to-high
clock transitions.

CLOCK

[2]000000
NC

NC

NC

Vcc

NC

NC

NC

positive logic: see function table

NC-No Internal Connection

SCHEMATICS OF INPUTS AND OUTPUTS
LS91
EQUIVALENT OF EACH INPUT

LS91
TYPICAL OF BOTH OUTPUTS
· _ - -.....-VCC

VCC - - - - . - - -

120H NOM
17 kH NOM
INPUT

--1H......- ......-

" - - - t - - OUTPUT

~YTHEO~

2-51

a-Bit Shift Registers

LS91

FUNCTIONAL BLOCK DIAGRAM

(DUAL·IN·LlNE) (FLAT PACKAGE)

s a

s a

s a

s a

s a

s a

s a

(13) (13)

CK
R

Q (14) (14)

Recommended Operating Conditions
9LS/54LS
Min.
4.5

Supply voltage, Vee

9LS174LS

Nom. Max.

High-level output current, 10H

5

Min.

5.5

Nom. Max.
5

4.75

;400

Low-level output c~rrent, 'OL

Unit

5.25

V

f-400

IlA

4

8

mA

Width of clock input pu Ise, tw

25

25

ns

Setup time, tsu (See Figure 1)

25

25

ns

0

0

Hold time, tn (See Figure 1)
Operating free-air temperature, T A

-55

ns

0

125

70

°e

Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
(UnlesS Otherwise Noted)
9LS/54LS

Test eonditionst

Parameter
V IH High-level input voltage

Typ.:j:

VO H High-Ievel"output voltage

Max.

2

Vee = Min, II = -18 mA
Vee = Min, V IH = 2V

2.5

Min.

Typ.:j:

Max.
V

2

VI L Low-level input voltage
V I K I nput clamp voltage

9 LS/74LS
Unit

Min.

0.7

0.8

V

-1.5

-1.5

V

3.5

2.7

3.5

V

VI L = VI L max, 10H = -4001lA
VOL Low-level output voltage

Vee = Min, V IH = 2V

IIOL =4mA

VIL=VILmax

Ii0L =8mA

0.25

004

0.25

004

0.35

0.5

V

Input cu rrent at

II

maximum input voltage

0.1

Vee = Max, VI = 7V

0.1

mA

IIH High-level input current

Vee = Max, VI = 2.7V

20

20

p.A

II L Low-level input current

Vee = Max, VI = OAV

-004

-004

mA

lOS Short-circuit currentt

Vee = Max

-100

mA

ICC Supply current

Vee = Max, See Note 1

20

mA

15

-100
12

15

20

12

tFor conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.

:j:AII typical values are at Vec = 5 V, TA = 25'C.

f Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 1. ICC is measured after the eighth clock pulse with the output open and A and B inputs grounded.

2-52

~YTHEO]J

8-Bit Shift Registers
Switching Characteristics Vee =
Parameter

From

(Input)

LS91

s.ov Over Recommended Free-Air Temperature Range.

To

9LS/54LS
_55°C

(Output)
Min.

Teat COnditions: CL

Typ.

Unit

+25°C

Max.

Min.

= 15pF, RL = 2.0kO (See Fig. A, page 2·174 and

f(max)

Typ.

+125'C

Min.

Max.

Typ.

Max.

Fig. 1, page 2-55)
10

MHz

18

TpLH

clock

QH

26

42

24

40

26

42

ns

TpHL

clock

QH

28

45

27

40

28

45

ns

Teat COnditions: CL

= 5OpF, RL = 2.OkO (See Fig. A, page 2·174 and Fig.

1, page 2-55)

TpLH

clock

QH

30

47

27

45

30

47

ns

TpHL

clock

QH

33

52

30

48

33

52

ns

PARAMETER MEASUREMENT INFORMATION

OUTPUT
Vcc=5V

r-- - - I
I
I
I

I
I

I
See Note C

I

I
Cl

:

- LOA DCIRCUlT 1l

VCc=5V

I

See

L~t~

I

I

I

I

..:. _ _ _ _ _ _ _ _":"~

TEST CIRCUIT

1
ClOCK·PUlSE
INPUT

INPUT A

OUTPUTQH

2 thru 7

8

9 thru 15 16 17 18 19 thru 23 24 25 26 27

flJ1_-.-J1J11T~~nrumrr~~JlflJUlJ1

JL _________ ~ ______
_____ -.lL____
____s - L
TYPICAL INPUT/OUTPUT WAVEFORMS

r§VTHEO]J

2-53

8-Bit Shift Registers

LS91

PARAMETER MEASUREMENT INFORMATION

CLOCK
INPUT

-trt-:
90%
:

10%

I"'- tw(clock)--j+- tw(clock)--t
3V

CLOCK
INPUT

Vref

:
Vref

I
-:----OV

,,-_ _I..;.O-"%J:, : I
t, --..; I i-tSU--i

I

INPUT

V rei

I

AORB

:
I
tPHL -j+-!

tPHL-+OUTPUT QH OR QH
Vrel

:---3V
10% OV

-..I

tl

I--

~
_:~r~ ______

- - - : - :,----VOH
OUTPUT QH OR QH

90% 90%
:

V,el

fre,

INPUT

-----'·----VOL

A OR B

3V

I

:..- tsu

OV

-t--th

~V:I -

-

-

- - -3V

-l

OV

--t--thold
PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS

SWITCHING TIMES VOLTAGE WAVEFORMS

FIGURE 1. SWITCHING TIMES
NOTES: A. The generator has the following characteristics: tw(clock) = 500 ns; PRR .. 1 MHz; Zout '" 50 r!; t, = 15 ns, and
t f =6ns.
B. C L includes probe and j:s capacitance
C. All diodes are 1 N3064 or 1 N916
D. Vref =I.3V

2-54

t;YTHE~

4-Bit Bi-Directional
Parallel-Access Shift Register

LS95B
PIN-OUT DIAGRAM

DESCRIPTION
This 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register
has three modes of operation:
Parallel (broadside) load
Shift right (the direction aAtoward aD)
Shift left (the direction aD toward aA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high~to-Iow transition of the clock-2 input. During loading, the entry of s,erial data is inhibited.
Shift right is accomplished on the high-to-Iow transition of
clock 1 when the mode control is low; shift left is accomplished on the high-to-Iow transition of clock 2 when the mode
control is high by connecting the output of each flip-flop to the
parallel input of the previous flip-flop (aD to input C, etc.) and
serial data is entered at input D. The clock input may be
applied commonly to clock 1 and clock 2 if both modes can
be clocked from the same source. Changes at the mode
control input should normally be made while both clock inputs
are low; however, conditions described in the last three lines
of the function table will also ensure that register contents are
protected.

1234560
SERIAL ~MODEGNO
INPUT
INPUTS CONTROL

13 12. 1110

9

14

8

7
2

.3

4

5

6

Die Size .067 x .082

LOGIC DIAGRAM
DATA INPUTS
A

MODECONTROL~l6t)~~~~~r=Ef==~~~±====;~1t~==~~
SERIAL!.!)
INPUT

~~----~~~v~----~----~
OUTPUTS

FUNciioN TABLE
INPUTS
MODE

CLOCKS

CONTROL 2 (L) 1 (R)
H

H

H
H

SERIAL

OUTPUTS
PARALLEL
A

B

C

D

X

X

X

X

b

c

X

X

I

X

X

a

I

X

X

L

L

H

X

°Bt
X

L

X

I

H

L

X

I

L

Oct DOt

d
d

X

X

X

X

X

X

X

X

X

X

X

CA

CB

CAO

CBO DCO 000
b
c
d

a

°Bn DCn
OAO °BO
H
DAn
L
DAn

Cc

DOn

CD

d

DCO DOO

t

L

L

X

X

X

X

X

CBn Cen
°Bn OCn
OAO DBO Deo DOO

I

L

L

X

X'

X

X

X

OAO DBa Dca 000

I

L

H

X

X

X

X

X

OAO DBa DCO 000

t
t

H

L

X

X

X

X

X

H

H

X

X

X

X

X

°AO °BO OCO °DO
DAO DBa OCO 000

31

[[AYTH E0

tShifting left requires external connection of a'S to A,
QC to B, and aD to C. Serial data is entered at input D.
H = high level (steady state), L = low level (steady state), X =
irrelevant (any input, including transitions)
..J, = transition from high to low level, t = transition from low to
high level
a, b, c, d == the level of steady-state input at input, A, B, C, or D,
respectively.
0AO. 0BO. 0CO. 0DO = the level of 0A. OS. 0C. or 0D. respec·
tively, before the indicated steady-state input conditions were
established.

QAn. 0Sn. 0Cn. QDn

= the level

of QA. 0B. QC. or 00. respec-

tively, before the most-recent .J.. transition of the clock.

2·55

4-Bit Bi-Directional,
Parallel-Access Shift Register

LS958
Recommended Operating Conditions

Min
Supply voltage, Vee
4.5
High·level output current, 101'1
Low·level output 6urrent, . IOL
Clock frequency, fclock
0
Width of clock pulse, tw(clock)(see Figure 2 page 2-57)
25
Setup time, high-level or low-level data, t setup (see Figure 1 page 2-57)
0
Hold time, high-!evel or low-level data, thold (see Figure 1 page 2-57)
20
Time to enable clock 1, tenable 1 (see Figure 2 page 2-57)
20
20
Time to enable clock 2, tenable 2 (see Figure 2 page 2-57)
Time to inhibit clock 1, tinhibit 1 (see Figure 2 page 2-57)
10
Time to inhibit clock 2, tinhibit 2 (see Figure i page 2-57)
10
Operating free-air temperature TA
-55

9LS/S4LS
Nom
Max
5

5.5
-400
4
20

125

Min

9LS/74LS
Max
Nom

4.75

5

0
25
0
20
20
20
10
10
0

5.25
-400
8
20

70

Unit
V
JlA
rnA
MHz
ns
ns
ns
ns
ns
ns
ns
°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Test Conditions'

Min

VIH

2

VIL
VI
VOH
VOL
Mode inputs
Other inputs
Mode inputs

II
IIH

Other inputs
Mode inputs
Other inputs

IlL

9LS/S4LS
Typ"
Max

lost
I eett

Min

9LS/74LS
Typ"
Max

2
0.7
-1.5

11=-18mA

Vee=MIN,
Vee-MIN,
VIL =VILmax,
Vee=MIN,
VIL =VILmax

VIH-2V,
IOH=-400JlA
IIOL =4mA
VIW2V,
II0l =8mA

Vee=MAX,

VI=7V

Vee=MAX,

VI=2.7V

Vee=MAX,

VI=O.4V

Vee=MAX,
Vee-MAX,

See Note 1

2.5

3.4

2.7

0.25

0.4

13

0.2
0.1
40
20
-0.8
-0.4
-100
21

-15

0.8
-1.5
3.4
0.25
0.35

-15
13

Unit
V
V
V
V

0.4
0.5
0.2
0.1
40
20
-0.8
-0.4
-100
21

V
rnA
JlA
mA
mA
rnA

'For conditions shown as MIN or MAX, use the appropriate value specified under recommendea operating conditions for the applicable
device type.
-'All typical values are at Vee = 5V, TA = 2Soe.
tNot more than one output should be shorted at a time.
tt ICC is measured with all outputs and ,erial inputs open; A B, e, and D inputs grounded; mode control at 4.5V; and a momentar.y 3V
then ground, ~pplied to both clock inputs.

Switching Characteristics, Vee
Parameter

= 5V Over Recommended Free-Air Temperature Range

-SSDC
Min

Typ

Max

Min

+2SDC
Typ

Max

I

Min

+t2SDC
Max
Typ

I

Unit

Test Conditions: C, = 15pF. R, = 2kO (See Fig.A. page 2-174 and Fig. 1 and 2. page 2-57)
f max
30
20
35
27
37
tpLH
28
40
30
tpHL
32
45
Test Conditions: C, = 15pF. R, = 2kO (See Fig. A. page 2-174 and Fig. 1 and
40
42
31
tplH
32
I
45
50
34
36
tpHL

28
32
2. page
32
36

37
45
2-57)
42
50

MHz
ns
ns
ns
ns

Note: Ae specification shown under _55°C and +125°e are for 9lS devices only. All 50pF specifications are for 9LS devices only.

2-56

r§VTHEO"EJ

4-Bit Bi·Directional
Parallel·Access Shift Register

LS958

PARAMETER MEASUREMENT INFORMATION

LOAO CIRCUIT

DATA
INPUT

CLOCK 1 OR 2
INPUT

g~T~~~~C.

I
I

OV

r---....

I -..

OR 00

__________J

iI \

/

t V,~

V,e'

I~--~I~~I

tPHL~

VOH
_ _ _ VOL

~tPLH

VOLTAGE WAVEFORMS
FIGURE 1 - SWITCHING TIMES

NOTES:
A. Input pulses are supplied by a generator having the following characteristics: tr .;; 10 ns, tf .;; 10 ns, and Zout '" 50n. For the data
pulse generator, PRR = 500kHz; for the clock pulse generator, PRR = 1MHz. When testing f max , vary PRR. tw(data) ;;;. 20 ns,
tw(clock) ;;;. 15 ns.
B. Vref = 1.3V.

J---..,..------- - - -- VIH

SERIAL
INPUT

' -_ _ _ _ _ _ _ VIL

,..---"
MODE

,._ _ _ _ _ VIH

1 -______

\\,,_ _..1

CONTROL
INPUT

CLOCK 1
INPUT

I

I

.

CLOCK 2

INPUT

_ _ _ _ _ _.V.'e..lf

°AOUTPUT

T

I

-----'

'---------VIL

~tenable2

tinhibit 2-4"'---I.~~

VIL

r-\.- --- - -

""',.v.'e.' ____-.J!'

'___I

VIH

Vil

C:::

VOLTAGE WAVEFORMS

NOTES:
A. Input A is at a low level.
B. Vref = 1.3V.

C§YTHEO:?J

FIGURE 2 - CLOCK ENABLE/INHIBIT TIMES

2-57

Dual J-K Positive-Edge-Triggered Flip-Flop

LS109
DESCRIPTION

LOGIC DIAGRAM (Yo)

This mono.!ithic dual J-K edge-triggered flip-flop features
individual J, K, clock, preset, and clear inputs. A low level at
preset or clear sets or resets the outputs regardless of the
levels of the other inputs. VlLhen preset and clear are inactive
(high), data at the J and K inputs meeting the setup time
requirements are transferred to the outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to
the transition time of the positive-gQjng pulse. Following the
hold time interval, data at the J and K inputs may be changed
without affecting the levels at the outputs.

PRESET

+--_+---l

CLOCK

+----+-----.

CLEAR

The J and K· data inputs simplify hardware design as a
Q-type flip-flop can be implemented by simply tying the J and
K inputs together.

--If:=========~

FUNCTION TABLE
(EACH FLIP-FLOP)

PIN-OUT DIAGRAM

6

5

4

I
ITIl
PRESET CLEAR CLOCK
L
H
X
H
L
X
L
L
X
H
H
t
H
H
t
H
H
t
H
H
t
H
H
L

2K 2CK 2PR 20 20

3

7

8

1 lJ lK lCK lPR 10
ClR
Die Size .O~~x .056

___J

positive logic: see function table

J

"R

X

X

X
X

X
X

L
H
L
H

L
L
H
H

X

X

Q

ii

H
L
H
L
H'
H*
L
H
TOGGLE

00
H

Qo

iio
L
iio

H = high level (steady state)
L = low level (steady state)
X = irrelevant
t = transition from low to high level
O. = the level of 0 before the indicated steady-state input conditions
were established
TOGGLE: each output changes to the complement of Hi; previous level
on each t clock transition.
"This configuration is nonstable; that is, it will not persist when preset
and clear inputs retum to their inactive (high) level.

Recommended Operating Conditions
Min

4.5

Supply voltage, Vee
Normalized fan-out from each output, N
Clock frequency, fclock
Width of clock pulse, twlclock) (High)
Width of preset pulse, tw(preset) (Low)
Width of clear pulse, !wlelear) (Low)
I nput setup time !setuP
Input hold time, thold
Operating free·air temperature,
..

.

.

TA

l High logic level
j

Low 101lie level

0
17
15
15
15
0
-55

9LS/54LS
Max
Nom

5

5.5
20
10
30

125

9LS/74LS
Min

Nom

Max

4.75

5

5.25
20
20
30

0
17
15
15
15
0
0

..

Unit

V

MHz
ns
ns
ns

70

ns
ns
°C

tsetup IS the mll'~lmum time required for the correct logiC level to be present at the J or K Input prior to the rising edge of the clock In order

to be recognized and transferred to the outputs.
thold is the miflimum time required for the logic level to be maintained at the J or K input after the clock transition in order to insure
recognition. This device requires no hold time.

2-58

~YTHE~

Dual J-K

Positive~Edge-Triggered

Flip-Flop

LS109

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted.)
Teat Condition.·

Parameter

Min

9LS/54LS
Typ··
Max

2

VIH
VIL
VI
VOH

Vee=MIN,

11=-lSrnA

Vee-MIN,

VIH-2V,

Vee=MIN,

VIH-2V,

VIL =VILrnax

2.5

3.4
0.25

IloL =4rnA
IIOL =8rnA

J or K
clock or preset

Vee=MAX,

VI=2.7V

0.25

0.4
0.5
0.1

0.4

0.2
0.4

20
40

20
40

80
-0.4

Clear
J or K
clock or preset

Vee=MAX,

VI=0.4V

Clear
-15

V
V
V

0.35
0.2

VI=5.5V

Clear

IlL

0.4

3.4

0.1
Vee=MAX,

clock or prese

IIH

O.S
-1.5
2.7

Unit
V

2

J or K
II

9LS/74LS
Typ·· Max

0.7
-1.5

VIL =VILrnax, IOH=-4OOIlA

VOL

Min

V

rnA

IlA

SO
-0.4

-0.8

-O.S

1.6
-100

-1.6

rnA

rnA
-100
rnA
4
8
'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
··AII typical values are at Vee = SV, TA = 2Soe.
tNot more than one output should be shorted at a time.
tt ICC is measured with outputs open, clock grounded, and J, K, preset, and clear at 4.SV.
lost

Vee-MAX
Vee-MAX,

Icctt

4

-15

8

Switching Characteristics , V·CC- SV Over Recommended Free-Air Temperature Range
Parameter
Te.t Condltlona: CL
tpLH
tpHL

I CK Low
I CK High

I
Min

-55°C
Typ

Max

Min

+25°C
Typ

Max I Min

=15pF, RL =2kO (See Figure A on page 2·1741
12

18

10

15

16

23

22
29

29

12

18

21

28

39

16

24

27

38

12

18

13

20

15

24

tpLH

13
20
14
22
tpHL
17
27
Test Conditions: CL - 50pF, RL - 2kO (See Figure A on page 2-1741
tpLH
tpHL

I CK Low
I CK High

tpLH
tpHL

+125°C
Typ I Max I Unit

16

22

13

19

19

26

26
33

33
44

21
29

27

31

38

24
30

17

24

15

22

16
19
..

41
25

ns
ns
ns
ns
ns
ns
ns
ns
ns

26
29
22
31
18
tsetup is the minimum time required for the correct logiC level to be present at the J or K input prior to the rising edge of the clock in
order to be recognized and transferred to the outputs.
thold is the minimum time required for the logic level to be maintained at the J or K input after the clock transition in order to insure
recognition. This device requires no hold time.
Note: Ae specification shown under -ssoe and +12Soe are for 9LS devices only. All SOpF specifications
are for 9LS only.

~YTHE<3l

2-59

LS122

Single and Dual Retriggerable
Monostable Multivibrators with Clear

LS123

FEATURES

LS122

• Functionally and Mechanically Identical to 54122 and
54123
• Retriggerable for Very Long Output Pulses, Up to 100%
Duty Cycle
• Overriding Clear Terminates Output Pulse
• Low Power Dissipation:
'LS122 ... 30 mW Typical
'LS123 •.. 60 mW Typical
• Compensated for VCC and Temperature Variations
• D-C Triggered from Active-High or Active-Low Gated
Logic Inputs
• 'LS122 Has Internal 10 kn Timing Resistor
• Diode-Clamped Inputs
• Compatible for Use with TTL or DTL

GND

8

7

A1

A2

e1

82

CLR

logic: see function table
NC-No internal connection.

14

1

vee
Die Size .085 x .071

LS123
DESCRIPTION

GND

The 'LS122 and 'LS123 multivibrators feature doc triggering
from gated low-level-active (A) and high~level-active (B) inputs, and also provide overriding direct clear inputs. Complementary outputs are provided. The retrigger capability
simplifies the generation of output pulses of extremely long
duration. By triggering the input before the output pulse is
terminated, the output pulse may be extended. The overriding clear capability permits any output pulse to be term inated at a predetermined time independently of the
timing components Rand C. Enough Schmitt hysteresis is
provided to ensure jitter-free triggering from the B inputs
with transition rates as slow as 1 volt per second. Figure 1
illustrates triggering the one-shot with the high-level-active
(B) inputs.

10

9

8

15

INPUTS

OUTPUTS
Q

Q

X
X

X
X.
X

L
L
L
L
L

H
H
H
H
H

L
X

1I

t

X

X
X
X
X

H

H

X
X

L
L
L

X
X
X
X
X

H

X
X
X

L
L
L

t

t
t

• ••
•
H

L

X

X

L

L
X

t
H
H
H
H
H
H
H
H

L
H
H

t
H
H

t
H
H
H
H
H

IL

..f1.
L

.n..

X

H
H

B

Q

Q

X
X

L
L
L

H
H
H

X
H
X
L

t

L

H
H

•

L

..n..

1S

..J1..

1S
l.I

.n..

LS
H

LS

.J1.

..f1.

1S
1S

..Il...

L.J"

.J1.
SL

1S
1S
"lJ"

SL

OUTPUTS

INPUTS
CLEAR A

B2

X

H

'LS123 FUNCTION TABLE
(SEE NOTE 1)

B1

L

H
H
H
H
H
H
H
H

2-60

A2·

161

Vee

Die Size .085 x .071

'LS122 FUNCTION TABLE
(SEE NOTE 1)

CLEAR A1

7

t;VTHEO]J

Single and Dual Retriggerable
Monostable Multivibrators with Clear

LS122

LS123

NOTES: 1. H = hlgh level (steady state), L = low level (steady state), t = transition from low to high level, • = transition from high to low
level, H = one high-level pulse, L = one 'Iow-Ievel pulse, X = irrelevant (any input, including transitions).
2. To use the internal timing resistor of 'LS122, connect Rint to Vcc.
3. An external timing capacitor may be connected between Cext and Rext/Cext (positive).
4. For accurate repeatable pulse widths, connect an external resisto.r, between Rext/Cext and Vee with Rint open ci rcuited.
5. To obtain variable pulse widths, connect external variable resistance between Rint or Rext/Cext and Vee.

TVPICAL OUTPUT PULSE WIDTH
w

EXTERNAL TIMING CAPACITANCE
100000

RETRIGGER PULSE
(See Note)

Rr"260kH

RT" 160kH

9 INPUT
10000

Io4---tw+tpLH~

OUTPUTQ

~

~

~- ______

I

L

~
I

------------,OUTPUT WITHOUT RETRIGGER

OUTPUT PULSE CONTROL USING RETRIGGER PULSE
B'NPUT

Il'--____________
0

CLEAR

OUTPurajl- --

.!!

1000

I

100

v

if

}

OUTPUT WITHOUT CLEAR

---1

10

OUTPUT PULSE CO'-N-T=R-O-L-U-S''-N-G-C-LE=A-R-C'N-CP-CU=T--

100

10

1000

Cexr-External Timing CapBcitance-pF

NOTE:

Retrigger pulse must not start before 0.22 Cext (in

tThese values of resistance exceed the maximum recommended for

use over the full temperature range of the 9LS/54LS' circuits.

picofarads) nanoseconds after previous trigger pulse.

FIGURE 2

FIGURE I-Typical Input/Output Pulses

These monostables are designed to provide the system designer with complete flexibility in controlling the pulse
width, either to lengthen the pulse by rerriggering, or to
s~orten by clearing. The 'LS12;;1 has an internal timing resistor vilhich allows the circuit to be operated with only an
external capacitor, if so desired.
The output pulse is primarily a function of the external

capacitor and resistor. For Cext
pulse width (tw) is defined as:

> 1000

pF, the output

tw = 0.4 • RT • Cext
where
RT is in kH (either internal or external timing resistor),
Cext is in pF,
tw is in ns.
For pulse widths when Cext';; 1000 pF, see Figure 2.

Recommended Operating. Conditions
9LS/74LS

9LS/54LS

Unit
Min.
Supply:voltage, VCC

4.5

High-level .output current, IOH

5

5.5

40

A or B inputs low

40

40

Clear low

40

40

External timing resistance, R ext

5

No restriction

~YTHE03l

temperature, T A

225

5

-55

5

5.25

V

-400

I'A

8

mA

125

ns

360

k!l

No restriction

50

Wiring capacitarice at Rext/Cext terminal

Nom. Max.-

40

External capacitance, Cext

free~air

4.75

4
A or B inputs high

Operating

Min.

400

Low-level output curreot, IOL

Pulse Width, tw

Nom. Max.

0

50

pF

70

°c

2-61

LS122

Single and Dual Retriggerable
Monostable Multivibrators with Clear

LS123

Electrical Characteristics OVer Recommended Operating Free-Air Temperature Range
(Unless Otherwise Noted)
9LS/54LS

VIH

High·level input voltage

VIL

Low·level input voltage

VI

Input clamp voltage

Unit
Typ.* Max.

Min.
2

VOH High·level output voltage

VOL

Vee = MIN.

11=-1BmA

Vee = MIN.

VIH = 2V,

VIL = VIL max,

IOH =-400I'A

Vee = MIN,

Low·level output voltage

2.5

0.25

VIH=2V, lIOL=4mA

Typ.* Max.

Min.
2

V

0.7

O.B

V

-1.5

-1.5

V

2.7

3.5

3.5

0.4

1 IOL = BmA

VIL=VILmax
Input current at

II

9LS/74LS

Test Conditions t

Parameter

Vee = MAX,

VI = 7V

V

0.25

0.4

0.35

0.5
0.1

0.1

V

mA

maximum input voltage

IIH

High·level input current

Vee = MAX,

VI = 2.7V

20

20

I'A

IlL

Low-level input current

Vee = MAX,

VI = O.4V

-0.4

-0.4

mA

lOS

Short-circuit outputcurrentr

Vee = MAX

150

mA

ICC

1 'LS122
See Note 21
'LS123

Vee = MAX,

(quiescent or triggered)

150

-30

Supply current

-30

6

11

6

11

12

20

12

20

mA

t.For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5V, TA = 25°C.

rNat more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is
applied to clock.

,Switching Characteristics Vee = S.OV Over Recommended Free-Air Temperature Range.
Parameter

From

To

(Input)

(Output)

Test Conditions: CL = 15pF, RL
A
tpLH

B
A

tpHL

B

tpHL

clear

tpLH
twQ(min)
*twQ

tpLH

B
clear

tpLH
A or B

twQ(min)

Q

Q
Q

A
tpHL

Q

Q

B

tpHL

Q

Aor B

A

Typ.

+25°C
Max.

Min.

Typ.

+125°C
Max.

= 2.01< C". = Opf, R"" = 5.0kO (See Fig. 3, page 2-61

Aor B

Teat Conditions: CL = 5OpF, RL

-55'C
Min.

= 2.0k, C'x!
Q

Q
Q

Q
Q

..

=

25
32
33
40
21
33
140

37
48
49
61
31
50
250

-

-

Opt, R",.

30
37
38
45
26
39
155

26
33
34
41
22
35
127

Typ.

Unit
Max.

snd Fig. A, page 2-174)

22 33
29 44
30 45
37 56
18 27
30 45
q6 200
4.0 4.!? 5.0

= 5.0kO (See Fig. 3, pag~ 2-61
43
54
55
67
37
55
270

Min.

-

25
32
33
40
21
33
140

37
48
49
61
31
50
250

-

-

ns
ns
ns
ns
ns
I'S

and Fig. A, page 2-174)

38
49
50
62
32
50
240
..

30
37
38
45
26
39
155

43
54
55
67
37
55
270

ns
ns
ns

ns
ns

Note: Ae specification shown under -S5°e and +12Soe are for 9LS deVices only. All SOpF specifications are for 9LS deVices only .

'For this test R ext = 10kU, eext = 1000pF.

2-62

~YTHEO~

Single and Dual Retriggerable
Monostable Multivibrators with Clear

LS122

LS123

TYPICAL APPLICATION DATA

The basic output pulse width is essentially determined by
the values of external capacitance and timing resistance.
For pulse widths when Cext < 1000 pF.
When Cext > 1000 pF, the output pulse width is defined as:

where
RT is in kS1 (internal or external timing resistance.)
Cext is in pF
tw is in nanoseconds
For best results, system ground should be applied to the
Cext terminal. The switching diode is not needed for electrolytic capacitance applications.

Vcc

RT

ri

coxt

To Coxt

To Rext/Cext

terminal

terminal

FIGURE 3

TIMING COMPONENT CONNECTIONS

~YTHE~

2·63

LS125

Quad 3-State Buffer, Low Enable

LS126

Quad 3-State Buffer, High Enable

QUAD 3-STATE BUFFERS WITH ACTIVE HIGH ENABLES
LS125
LS126
Vee

E

DOE

0

0

GWgJ

mm0
E

DOE

0

0

GND

Recommended Operating Conditions.
9LS174LS

9LS/54LS
Min.

Typ.

4.5

5 ..0

Supply Voltage

Max.

Min.

5.5

4.75

-1 ..0

High Level Output IOH

Max.

5 ..0

5.25

V

-1 ..0

-2.6

mA

24

mA

7.0

°c

12

12

Low Level Output 10L

+125

-55

Operating Free Air Temperature

Unit

Typ.

.0

Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
(Unless Otherwise NOted)
Parameter

9LS/54LS

Test Conditions
Min.

VIH
VIL
VCD

Guaranteed Input HIGH Voltage for
All Inputs

Input HIGH Voltage

Typ.

2.0

Min.

Typ.

Max.

2.0

Guaranteed Input LOW Voltage for

I nput LOW Voltage

9LS/74LS

Max.

Unit

V

0.7

0.8

-1.5

-1.5

V

All Inputs

Input Clamp Diode Voltage

VCC = MIN, liN = -18mA

VOH Output HIGH Voltage
VOL Output LOW Voltage

10H = -1.0mA

Vee = MIN, VIN = VIH or

10H = -2.6mA

VI L per Truth Table

10L = 12mA

Vee = MIN, VIN = VIH or

10L = 24mA

VI L per Truth Table

0.65
2.4

3.4
0.25

V
V

0.4

2.4

3.1

V

0.25

0.4

V

.0.35

.0.5

V

10ZH Output Off Current HIGH

Vce = MAX, VOUT = 2.4 V, VE = VI L

20

2.0

p.A

IOZL Output Off Current LOW

Vee = MAX, VOUT = .0.4 V, VE = VIL

IIH

Input HIGH Current

IlL

Input LOW Current

-20

-2.0

p.A

Vee = MAX, VIN = 2.7V

20

2.0

p.A

Vee = MAX, VIN = 10V

.0.1

.0.1

rnA

VCC = MAX, VIN = O.4V

-0.4

-.0.4

mA

-1.0.0

mA

Output Short Circ .... it

lOS

ICC

Vee = MAX' VOUT =.OV

Current (Note 3)

-15

100

-15

Power Supply Current,

LS125

Vee = MAX, I(IN = OV, VE = OV

16

16

mA

Outputs LOW

LS126

Vee = MAX, VIN = OV, VE = 4.5V

20

2.0

mA

Power Supply Current,

LS125

Vce = MAX, VIN = OV, VE = 4.5V

2.0

2.0

mA

LS126

Vee - MAX, VIN = DV, VE = OV

24

24

mA

ICC Outputs Off
NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the
applicable device type.
2. Typical lim·its are at Vec = 5.DV, T A = 25°C.
3. Not more than one output should be shorted at a time.

2-64

Q,;YTHEO]J

Quad 3-State Buffer, Low Enable

LS125

Quad 3-State Buffer, High Enable

LS126

Switching Characteristics Vee = S.OV Over Recommended Free-Air Temperature Range.
91.S/54LS

Parameters

From

*

-55'C

To

(Input)

(Output)

Min

Typ.

+125'C

+25'C
Max.

Min.

Typ.

Max.

Min.

Typ.

Units
Max.

Tnt Condnlons: C, = 45pF, R, = 6670 (See Fig. C, page 2-174)
tpLH

D

tpHL

D

tpZH

E or E
E or E

tpZL

0
0
0
0

10

15

6

10

10

14

ns

13

20

10

16

13

20

13

20

10

16

13

20

ns
ns

13

20

10

16

13

20

ns

Tnt Conditions: C, = 5pF, R, = 6670 (See Fig. C, page 2-174)
tpLZ

E or

tpHZ

E or E

E

0

13

19

10

15

13

20

ns

13

27

15

23

18

27

ns

Teet CondItIons: C, = 45pF, RL = 8670 (See fig. C, page 2-174)
tpLH

D

0

13

20

10

15

13

19

ns

tpHL

D

18

25

15

21

18

25

ns

tpZH

E or E
E or E

0
0
0

18

25

15

21

18

25

ns

18

25

15

21

18

25

ns

tpZL

Note: AC specification shown under -55'C and +125'C are for 9LS devices only. All 50pF specifications are for 9LS devices only.
",For LS125 use E and for LS126 use E.

TRUTH TABLES
9LS125

9LS126

INPUTS
OUTPUT

E'

0

L
L
H

L
H
X

~YTHE03l

L
H
(Z)

INPUTS
OUTPUT
E

0

H
H
L

L
H
X

L
H
(Z)

L = LOW Voltage Level
H = HI G H Voltage Level
X = Don't Care
(Z) = High Impedance (off)

2-65

Quad 2-lnput Schmitt-Trigger

LS132

13 12 11 10

9

~

7 GND

VCC. 14

Die Size .057 x .057

Vee

8

2

3

4

5

4A

4V

38

3A

3V

~J W

mm
1A

6

48

18

1Y

2A

28

I2J

2V

GND

Recommended Operating Conditions
9LS/54LS

Supply voltage, Vee

Min.

Typ.

4.5

5.0

High level output current, IOH

9LS174LS

Max.

Min.

Typ.

5.5

4.75

5.0

5.25

V

-400

p.A

4

8

mA

+125

70

°e

-400

low-level output current, IOl
Operating free-air temperature, T A

-55

Unit
Max.

Electrical Characterlstlca Over Recommended Operating Free-Air Temperature Range
(Unless Otherwise Noted)
9LS/54LS

Test Conditions t

Parameter

Min.

Typ.

9LS174LS

Max.

Min.

Typ.

Unit
Max.

VT+

Positive-going threshold voltage

Vec= 5V

1.4

1.6

1.9

1.4

1.6

(9

V

VT_

Negative-going threshold voltage

Vee = 5V

0.5

0.8

1.0

0.5

0.8

1.0

V

Hysteresis (VT+-VT_)

Vce = 5V

0.4

O.B

0.4

0.8

Input clamp voltage

Vee = MIN,

II =-18mA

Vee = MIN,

IOH = MAX,

VIK

VOH High-level output voltage

VOL

low-level output voltage
Input cu rrent at

IT+
IT_

II

positive-going threshold
Input cu rrent at
negative-going threshold
Input current at
maximum input voltage

-0.65
2.5

VI = VT_MIN
Vee = MIN,

3.4

0.25

VI = VT+MAX, IOl = MAX

-1.5

-0.65
2.7

0.40

V
-1.5

3.4

0.35

V
V

0.50

V

Vee = 5V,

VI = VT+

-0.14

-0.14

mA

Vee = 5V,

VI = VT_

-0.18

-0.18

mA

Vee = MAX

0.1

VI=7V

IIH

High-level input current

Vee = MAX

VI = 2.7V

III

Low-level input current

Vee = MAX'

Vil = O.4V

lOS

Short-circuit output current

Vec= MAX
Vee = MAX

VIN = OV

Icel Supply Current low

Vee = MAX

VIN =4.5V

mA

20

20

p.A

-0.4

-0.4

mA

-100

mA

B.6

16

8.6

16

mA

12

21

12

21

mA

-15

IceH Supply Current High

0.1

-100

-45

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

2-66

~YTHEt3l

Quad 2-lnput Schmitt-Trigger

LS132

s.ov Over Recommended Free-Air Temperature Range.

Switching Characteristics Vee =

9LS/S4LS
Parameter

To

(Input)

(Output)

Teat Conditions: CL = 15pF,
tpLH
tpHL

y

tpHL

RL

Min.

ITyp. IMax. I

I

+2S"C

Min·l Typ.l Max.

I

+12S"C

Min.

I Typ. IMax.

Units

= 2.0k (See Fig. A, page 2-174)

A or B

Test Conditions: C L = SOpF,
tpLH

RL

I

-SS"C

From

J 16J
I 16 I

24
24

I

I

I

I

13
13

I
I

I
I

17
17

I

I

I

20
20

I

I

I

I
I

25
25

I
I

I

I

24
24

ns
ns

I 20 I
I 20 I

29
29

ns

16
16

= 2.Ok (See Fig. A, page 2·174)

y

Aor B

I 20 I
I 20 I

29
29

ns

PARAMETER MEASUREMENT INFORMATION

INPUTS

A-.-----:i~H

B-C -

-

D -

-

OUTPUT
y

~-e-4~~---~--~----~--~GND

FIGURE 1

[[AYTHEO]]

2-67

Quad 2-lnput Schmitt-Trigger

LS132

TYPICAL CHARACTERISTICS

NEGATIVE-GOING THRESHOLD VOLTAGE

POSITIVE-GOING THRESHOLD VOLTAGE

vs

>

1_70

.---.--'-,--.--'r--',-'-'-I-"--,---,

.. 1_69

~

1
!
t:-l!'

Vcc • 5V

~

1.68

~

1.67
1.68

~l!'
&
•

1.65

8 1.64

!

1.63

~

1.62

..,..--,r-.....

VCC=5V

0.69
0.68
0.87

0.86
0.86
0.84
0.83

!

0.82

i= 1.61

>

1

FREE-AIR TEMPERATURE
0.90 .--....-'-T....;..;.,r'-'-....

0.81

1.60 '-....1..._-'--'-_-'--'-_-'--'----'
-75 -50 -25
0
25 50 75 100 125

0.80 '--'---''--'---''--'----'--'----'
25 50" 75 100 125
-75 -50 -26 0

T A-free-Air Temperature-°c

TA-free-Air Temperature-°C

HYSTERISIS
DISTRIBUTION OF UNITS
fOR HYSTERESIS

vs
FREE-AIR TEMPERATURE
850 , - - , - - - , - - , - - , - - . -. ......,---,

840

~

Vcc = 5V

VCC=5V
TA' 25·C

830
820

c

j
I

790

~ 780

770
760
760'-....1..._-'-....1..._'-....1..._'-....1...--.J
-75 -60 -25
0
25 60 75 100 125

720 740 760 780 800 820 840 860 880

lA-free-Air Temperature-'"C

VT+-VT _-Hysteresis-mV

THRESHOLD VOLTAGES AND HYSTERESIS

OUTPUT VOLTAGE
VI

2.0

>

1.8

'Se
!:..,

1.6

l:

i

I

1.4

0.8
0.6

Positive-Going Threshold Voltage, VT+.
Negative-Going Threshold VoI_. VT-

Hystel'8lil. VT +-VT_

1

0.4

t:-

I

I

I

I

I

I

!

t-

5.5

-

-

2

-

I

0
4.76
5.25
5
VCC-8upply VoI _ _ V

I

-

>

0.2
0
4.5

2-68

JCC ! 5VI

TA =25·C

1.2
1.0

INPUT VOLTAGE

4

o

I
0.4

1.6
0.8
VI-Input VoI _ _ V

2

~YTHEO~

Quad 2-lnput Schmitt-Trigger

LS132

TYPICAL APPLICATIONS DATA

TTL SYSTEM

INPUT

I

1----1&-0-

MOS.
CMOS.
etc.
'--_
_ _-'

I

SINE·WAVE
OSCILLATOR

I~~ h_
PULSE SHAPER

TTL SYSTEM INTERFACE I
FOR SLOW INPUT WAVEFORMS

330£1

0.1 Hz to 10 MHz

THRESHOLD DETECTOR

MULTIVIBRATOR

I

I
I

I

1

I

J

I

I

J

I

I

,

1

I

1

1

I

OU~
PULSE STRETCHER

r§YTHE031

2-69

LS136

Quadruple 2-lnput Exclusive-OR,
-NOR Gates With Open-COllector Outputs

LS266

PIN-OUT AND LOGIC DIAGRAMS
LS136
QUADRUPLE 2-INPUT EXCLUSIVE-OR WITH OPENCOLLECTOR OUTPUTS

LS2!!6
QUADRUPLE 2-INPUT EXCLUSIVE-NOR WITH OPEN
COLLECTOR OUTPUTS

Vee 48 4A 4Y 38 3A 3Y

13

8

14

7
6

2

3

4

Die Size .045 x .056

5

@~~

12

11

10

Vee 48 4A 4Y 3Y 38 3A

9

@~m
8

13

7

14

~~rn

IA 18 IY 2A 28 2Y GND

positive logic: Y

= A Et> B = AB + AS

6

2

3

4

Die Size .045 x .056

~~rn

IA 18 IY 2Y 2A 28 GND

5

positive logic: Y

= 'A Et> B = AB + AS

Recommended Operating Conditions
Min
Supply voltage, Vee
High-level output voltage, VOH
Low-level output current, IOl
Operating free-air temperature, TA

4.5

9LS/54LS
Nom
Max
5

-55

5.5
5.5
4
125

Min
4.75

9LS/74LS
Nom
Max
5

0

5.25
5.5
S
70

Unit
V
V
mA

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (I,Inless Otherwise Noted)
Parameter

Test Conditions'

Min

9LS/54LS
Typ"
Max

2

VIH
Vil
VI

Vee-MIN,
Vee-MIN,
VIL =Vllmax,
Vee-MIN,
Vil =Vllmax
Vee-MAX,
Vee-MAX,
Vee-MAX,

IOH

11=-1SmA
VIH-2V,
VOH=5.5V
VIH-2V

Min

9LS/74LS
Typ"
Max

2
D.7
-1.5
100
0.25

0.4

Unit

O.S
-1.5

V
V
V

100

J..lA

0.4
Llol -4mA
V
VOL
0.5
IIOl -SmA
VI-7V
0.2
0.2
mA
II
VI-2.7V
40
40
IIH
J..lA
-O.S
-O.S
VI-O.4V
mA
IlL
13
LS266
S
S
13
I eet I
Vee=MAX,
mA
LS136
6.1
10
6.1
10
..
.
'For condItIons shown as MIN or MAX, use the appropriate value specIfIed under recommendea operatong condItIons for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°e.
tlee is measured with one input of each gate at 4.5V, the other inputs grounded, and the outputs open.

I

2-70

.

0.25
0.35

..

t;YTHEO~

Quadruple 2-lnput Exclusive-OR,
-NOR Gates With Open-Collector Outputs

LS136

LS266

Switching Characteristics , V'cc- 5V Over Recommended Free-Air Temperature Range

Teat Conditione:

-55'C

+25'C
Typ

Max

18
16
16
16

13
9
13
18

(See figure B on page 2-174)
31
Other input
35
16
23
low
30
35
Other inp~t
high'
19
23

30
13
31
13

From
(Input)

Parameter

To
(output)

Min

Typ

Max

Min

+125'C
Typ

Max

17
14
17
13

20
10
8
7

26
16
12
12

35
19
36
19

36
14
35
13

42
21
41
19

Min

Unit

CL = 15pF. RL = 2kO (See figure B on page 2-174)

tpLH
tpHL
tpLH
tpHL
Teat Conditione: C~
tpLH
tpHL
tpLH
tpHL

A or B
Aor B

Other input
low
Other input
high

14
10
12
10

ns
ns

= 5OpF. RL = 2kO
Aor B
Aor B

ns
ns

Note: AC specification shown under -5SoC and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS only.

~YTHE03l

2-71

:LS~38

Decoders/Demultiplexers

LS139

FEATURE$_
•
LS138: 3-Line-to-8-Line Decoder
1-of-8 Demultiplexer
LS139: Dual 2-Line-to-4-Line Decoder
Dual 1-of-4 Demultiplexer
LS138 is expandable to 5-lines-to-32-lines decoder
using 4 LS138's and one inverter.

PIN·OUT DIAGRAMS

LS138

•

DATA OUll'UlS
r -____
______
-JA~

VI Y2 Y3 V4

•

DESCRIPTION
The LS138 decodes one-of-eight lines dependent on the
conditions at the three binary select inputs and the three
enable inputs. Two active-low and on!! active-high enable
inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without
external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for
demultiplexing applications.

~

Y6'

1234567[]J
~~Y7GND
SELECT

Die Size .063 x .069

The LS139 comprises two individual two-line-to-four-line
decoders in a single package. The active-low enable input
can be used as a data line in demultiplexing applications.

ENABLE OUll'UT

LS139

These circuits are designed to be used in high-performance
memory-decoding and data-routing applications requiring
very short delay times.

34567[]J
IG IA 18 lYO 1YllY2lY3 GND

ENABLE~~
Die Size .063 x .069

LSl38
FUNCTION TABLE
INPUTS
SELECT
'S
A
C

ENABLE
GI G2'

OUTPUTS

VO VI V2 V3 V4 V5 V6 V7

X

H

X

X

H

H

H

H

H

L
H
H
H

X

X

X

X

H

L
L
L

L
L
L

L
L
H

L
H
H

H
H

H
H
H

H
H
H
H

H
H

L
L

H

H
H
H
H
H

L

L
L

L
H

H

H

L
H
H

L
H
L
H

H
H

L
L

H

H
H

L
H

H

X

L
H
H
H

L
H
H

H

H
H

H
H

H
H

H

H

H

H

H
H

L
H

L
H
H
H

H
H

H
H

H
H

H
H
H

H
H
H
L
H
H

H

H
H
L
H

"G2 = G2A + G2B
H = high level, L = low level, X = don't care

2-72

H
H
H
H
H
H
H
H
H

L

LS139
FUNCTION TABLE (V:z)
.. INPUTS
SELECT
S
A
G
H
x
X
L
L
L

OUTPUTS

ENABLE

L

L

L
L

H

H

H
L
H

VO VI V2 V3
H

L
H
H
H

H
H
L
H
H

H
H
H

L
H

H
H
H
H

L

H = high level, L = low level, X = don't care

~YTHE03J

Decoders/Demultiplexers

LS138

LS139

LOGIC DIAGRAMS
LS138

LS139

IVO
(1)

ENABLE 1G

DATA
OUTPUTS

SELECT
INPUTS

{:1:::~:-t>~tt:~~~~J

SELECT
INPUTS

t

IV1
IV2

A (2)
(3)

IV3

1B

DATA
OUTPUTS

(15)

ENABLE 2G

C (3)

SELECT
INPUTS

t

A(14)

2J13)

Recommended Operating Conditions
Min
4.5

Supply voltage, Vee
High·level output current, IOH
Low·level output current, IOL
Operating free·air temperature, TA

9LS/54LS
Max
Nom
5

-55

5.5
-400
4
125

Min
4.75

9LS/74LS
Nom
Max
5

0

5.25
-400
8
70

Unit
V
jlA
rnA

"C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter
VIH
VIL
VI
VOH
VOL
II
IIH
IlL
lost
Icc

Test Conditions·

Min

9LS/54LS
Typ·· Mex

2
11--18mA
Vee=MIN,
Vee=MIN,
VIH=2V,
VIL =Vllmax, IOH=-400,uA
Vee=MIN,
VIH=2V,
1101.. =4mA
Vil =Vllmax
IIOl =8mA
VI-7V
Vee-MAX,
VI-2.7V
Vee-MAX,
VI=O.4V
Vee=MAX,
Vee-MAX
I LS138
Vee=MAX,
Outputs enabled and open
LS139

I

Min

9LS/74LS
Typ •• Max

V

2
0.7
1.5

2.5

3.4

2.7

0.25

0.4

6.3
6.8

0.1
20
-0.4
-100
10
11

15

Unit

O.I::!

V

-1.5

V

3.4
0.25
0.35

V
0.4
0.5
U.l

15
6.3
6.8

20
-0.4
-100
10
11

V
rnA
jlA
rnA
rnA
rnA

"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
*"AII typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.

~YTHEO:FJ

2·73

LS138

Decoders/Demultiplexers

LS139

LS138

-

Switching Characteristics , V'cc.- 5V Over Recommended Free Air Temperature Range
Levels
-55°C
From
To
of
Parameter
(Input)
(output)
Min
Typ
Delav·
. Test Conditione: C L = 15pF, R.. = 2kO (See fig. A, page 2-174)

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

2
3

Binary
Select

Any

Enable

Any

11
17
16
22
11
19
16
22

2
3

Test Conditions: CL

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

= SOpF, RL =

2
3

Binary
Select

Min

+25°C
Typ

I
Min

Max

+125°C
Typ

Max

16
24
22
30
16
26
22
30

10
17
16
21
10
18
16
20

15
24
21
28
15
25
22
28

13
21
21
24
13
23
21
24

18
27
28
32
18
30
27
31

19
31
24
35
16
30
24
34

12
22
17
25
12
24
18
24

17

29
23
32
18
33
23
32

14
26
23
28
15
26
24
28

20
33
29
36
20
34
30
37

I

Unit

ns

ens
ns
ns
ns
ns
ns
ns

2kO (See fig. A, page 2-174)

13
23

Any

17

26
11
23
18
26

2
Enable

Max

Any

3

ns
ns
ns
ns
ns
ns
ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications are for 9LS devices only.

LS139

-

Switching Characteristics, V'cc- 5V Over Recommended Free Air Temperature Range

,p.rameter'~~
.
Delav

.

Teid Conditione: CL

tpLH
tpH-.I.
tpLH
tPHL
tplH
tpHl

2
3
2

Test ConcIItIons: CL

tpLH
tpHL

2

tPlH
tpHL
tpLH
tPHI

3
2

From
(Input)

To
(output)

-55"C
Min

Typ

Max

Min

+25°C
Typ

I
Max

Min

+125°C
Typ

Max

I

Unit

= 15pF, RL = 2kO (See Fig. A, page 2-174)
Binary
Select

Any

Enable

Any

12
13
16
18
12
11

21
21
28
30
22
22

12
12
15
17
11
11

26
26
33
35
27
27

15
15
18
20
14
14

17
22
25
15
16

13
13
17
18
11
12

20
20
27
30
22
22.

ns
ns
ns
ns
ns
ns

21
21
26
29
19
20

16
16
20
21
14
15

25
25
32
35
27
27

ns
ns
ns
ns
ns
ns

17

= SOpF, RL = 2kO (See Fig. A, page 2-174)
Binary
Select

Any

Enable

Any

15
16
19
21
15
14

Note: AC specification shown under _55°C and +125°C are for 9LS device. only. All 50pF specifications
are for 9LS only.

2-74

~YTHEc3J

8-Line-To-1-Line Multiplexers

LS151

PIN-OUT DIAGRAMS

FEATURES
•
•
•

LS151

Select one of eight data sources
Perform parallel-to-serial conversion
LS151 has complementary outputs;
LS152 has inverting output only
LS1'51 has strobe input

•

6

8

These monolithic data selectors/multiplexers contain full
on-chip binary decoding to select one-of-eight data sources.
The LS151 has a strobe input which must be at a low logic
level to enable the device. A high level at the strobe forces
the W output high. and the Y output low.
The LS151 features complementary Wand Y outputs
whereas the LS152 has an inverted (W) output only.

INPUTS
OUTPUTS
SELECT
STROBE
V
W
C
B
A
S
)(

H

L

L

L

L

L

L

H

L

L

H

L

L

L
DO

9

6

10
11

12 13 14

Die Size .056 x .057

LS152

LS152
FUNCTION TABLE

LS151
FUNCTION TABLE

X

5 4 3

7

DESCRIPTION

x

LS152

DATA INPUTS DATASEllCT

6

SELECT
OUTPUT

INPUTS
C

B

H

L

iXi
51

L
L

L
L

DO

H

51
52
OJ
54

L

H

H

H

L

L

L
L

H

L

H

L

OS 05

H

H

L

H

H

L

L

H

H

L

Os
OJ

H

H

06
07

H

H

H

L

52
OJ
54

L

H

H

H
H

L
L

H

L

1ill13

W

A
L

01
02
03
04

~ ,.--A----..
VCC567ABC

54

05
Os
OJ

10 9

8

3
2

7

8

14

9

123456[2]

10111213

~WGND

DATA INPUTS

DU11'UT

Die Size ,056 x ,057

H = high level, L = low level, X = don't care
~O,

01 , . , 07 = the level of the 0 respective input

LOGIC DIAGRAMS
(LS!5! STROBE
(ENABLEI----.!I>------,

onlyl

OO------r=~====~~

02---------Ft~=E=t~1
DATA

03----Tt=J=1~~::J

OUTPUT W (LS151 only)

INPUTS

D4------"Hfl:$:I~Er:

OUTPUT Y

05----lii=;~~S:

SELECT
DATA
(BINARV)

~YTHE03'l

{A===j;==~~~~~:!J
B
C

2-75

LS151

8-Line-To-1-Line Multiplexers

LS152

Recommended Operating Conditions
9LS/54LS
Supply voltage, Vec
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA

9LS/74LS

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
-400
4
125

4.75

5

5.25
-400
B
70

-55

0

Unit

V

tJ. A
mA

°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted
Parameter

VIH
VIL
VI
VOH
VOL
II
IIH
IlL
lost
Icc

Test Conditions·
.

11--1BmA
Vee-MIN,
Vee=MIN,
VIH=2V,
VIL=VILmax IOH=-4OOtJ. A
Vee-MIN,
VIH=2V,
IIOL-4mA
VIL=VILmax
IloL-BmA
Vee=MAX, VI=7V
VI=2.7V
Vce=MAX,
VI=O.4V
Vce=MAX,
Vce-MAX
Outputs open I LS151
Vee-MAX,
I LS152:
All inputs at 4.5V

9LS/74LS

9LS/54LS
Min

Typ··

Max

Min

Typ··

2

2
0.7
-1.5
2.5

Max

3.4
0.3

O.B
-1.5
2.7

0.4
0.5

u.l

u.l

6.0

20
-0.4
-100
10

20
-0.4
-100
10

5~6

9

-15

-15
6.0
5.6

V
V
V
V

3.4
0.25
0.35

0.45

Unit

9

V
mA
tJ. A
mA
mA
mA

*For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
*·AII typical values are et Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.

2·76

~YTHEO~

8-Line-To-1-Line Multiplexers

LS151

-

LS152

Switching Characteristics , V'cc- 5V Over Recommended Free Air Temperature Range
From
(input)

Parameter
Test Conditions: CL

To
(output)

A,

B, or C

W

tpHL

(4

levels)

(54LS151 only)

tpLH

A,

B, or C

(3

y

tpHL

levels)

tpLH

W

Strobe

tpHL
tpLH

(54LS151 only)

y

Strobe

tpHL
tpLH

(54LS151 only)

W

Any 0

tpHL
tpLH

(54LS151 only)

Y

Any 0

tpHL
-

SOpF.

RL

A,

8, or C

W

tPHL
tpLH

(4

levels)

(54LS151 only)

A,

8,

tpHL

(3

levels)

or

Strobe

tpHL
tpLH

Strobe

tpHL
tpLH
tpHL
tpLH
tpHL

Typ

Max*

Min

+2SDC
Typ

Max*

Any 0
Any 0

15
19
24
21
12
13
18
18
8
6
11
14

22
26
32
30
17
20
26
27
13
12
18
22

15
18
24
20
11
13
18
16
9
5
11
14

22
25
31
28

+12SDC
I
Max. Unit
Typ

20

18
20
29
22
13
14
21
17
11
6
13
15

25
26
36
31
19
20
29
25
17
13
19
22

24
31
33
37
20
24
28
35
15
16
20
30

17
21
26
25
13
15
20
20
10
8
14
18

24
29
32
35
19
23
27
31
16
14
19
27

20
22
29
29
15
16
23
21
13
8
15
20

27
31
38
38
21
24
30
32
19
14
21
29

17

19.
26
24
14
12
17

C

y

W
(54LS151 only)

y
(54LS151 only)

W
(54LS151 only)

Y

17
22
26
27
14
16
20
24
9
9
14
19

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS only.

~YTHEO~

Min

ns
ns
ns
ns
ns
ns

= 2kO (See Fig. A. page 2-174)

tpLH

tpLH

Min

= 1SpF. RL = 2kO (See Fig. A. pege 2-174)

tpLH

Test Conditions: CL

-SSDC

ns
ns
ns
ns
ns
ns

*Tentative data, subject
to change without notice

2-77

Dual 4-Line-To-1-Line Multiplexer
SF

LS153

.n

PIN-OUT DIAGRAM

FEATURES
•
•
•

Permits multipl!,xing from N lines to 1 line
Performs parallel-to-serial conversion
Strobe (Enable) line provided for cascading (N lines
to n lines)
Non-inverting

•

DATA

DESCRIPTION
The LS153 is a high speed DuaI4-Line-to-1-Line Multiplexer
with common select inputs and separate strobe (enable)
inputs for each half. Each half can select one bit of four and
present it at the output in non-inverted form.

14

LOGIC DIAGRAM

9

15

B

16

1C1~(5~)~-------+~FF~J
DATA 1

2

1C2~(4~)______~~~~L-~

~~~.

7.

Die Size .057 x .061

1C3~(3~)______~-r~__L-~
FUNCTION TABLE
SELECT

DATA INPUTS

INPLrrS

DATA 2

!;:':::

C2· ~:!-.--t=i=:::j~---'"

C3~(1~3~)----~=F==~~
STROBE 2G
(ENABLE) (15)

2Y

STROBE OUTPLrr

B

A

co

Cl

C2

C3

G

X

X

X

X

X

X

H

L

L

L

L

X

X

X

L

L

L

L

H

X

X

X

L

H

L

H

X

L

X

X

L

L

L

H

X

H

X

X

L

H

y

H

L

X

)(

L

)(

L

L

H

L

)(

)(

H

)(

L

H

H

H

)(

)(

)(

L

L

L

H

H

X

X

)(

H

L

H

Select Inputs A and B are common to both sections.
H = high level, L = low level, X = don't care

2·78

~YTHE~

Dual 4-Line-To-1-Line Multiplexer

LS153

Recommended Operating Conditions
Min
4.5

Supply voltage, Vcc
H igh·level output current, IOH
Low-level output current, In.
Operating free-air temperature, T A

9LS/54LS
Nom
Max
5

-55

5.5
-400
4
125

Min

9LS/74LS
Nom
Max

4.75

5

0

5.5
-400
8
70

Unit
V
fJ.A
mA
°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter
V,H
V,L
V,
VOH
VOL
I,
I'H
I,L
lost
ICCL tt

Tesl Conditions'

Min

9LS/54LS
Typ"
Max

2
Vcc-MIN,
Vcc-MIN,
V,L =V,Lmax,
Vcc-MIN,
V,L =V,Lmax
Vce-MAX,
Vee-MAX,
Vee-MAX,
Vcc-MAX
Vcc=MAX

Min

9LS/74LS
Typ"
Max

2
0.7
-1.5

1,--18mA
V,W 2V,
IOH=-4OOfJ.A
V,w2V,
IIOL -4mA
IIOL -8mA
V,-7.0V
V,-2.7V
V,-O.4V

2.5

3.4

2.7

0.25

0.4

6.2

0.1
20
-0.4
-100
10

-15

0.8
-1.5
3.4
0.25
0.35

-15
6.2

Unit
V
V
V
V

0.4
0.5
0.1
20
-0.4
-100
10

V
mA
fJ.A
mA
mA
mA

"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttleCL is measured with the outputs open and all inputs grounded.

-

Switching Characteristics , V'!;C- 5V Over Recommended Free Air Temperature Range
Parameter
Teat Conditions: CL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
Test Conditions: CL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

From
(Inllul)

To
(output)

Min

-55°C
Typ

I
Max

Min

+25°C
Typ

Max

Min

+125°C
Typ

Max

Unit

= 15pF, RL = 2kO (See Fig. A, page 2-174)
Data
Data
Select
Select
Strobe
Strobe

Y
Y
Y
Y
Y
Y

8
13
15
17
14
17

13
18
21
23
20
23

8
14
17
16
16
16

13
18
22
21
21
21

11
17
22
21
21
20

16
22
28
26
26
25

ns
ns
ns
ns
ns
ns

15
23
24
27
23
27

10
17
19
19
18
20

15
22
24
25
23
24

15
22
25
24
23
23

22
27
30
30
28
28

ns
ns
ns
ns
ns
ns

= 5OpF, RL = 2kO (See Fig. A, page 2-174)
Data
Data
Select
Select
Strobe
Strobe

Y
Y
Y
Y
Y
Y

10
17
18
22
17
21

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS only.

~YTHE@l

2·79

LS155

Dual 2-Line-To-4-Line
Decoders/Demultiplexers

LS156

FEATURES
•
•

LOGIC DIAGRAM

LS156 has open-collector outputs
Applications:
Dual 2-Line-to-4-Line Decoder
Dual 1-Line-to-4-Line Demultiplexer
3-Line-to-8-Line Decoder
1-Line-to-8-Line Demultiplexer

STROBE...:.I;:::21,--_...,--,

DESCRIPTION
These circuits feature dual l-line-to-4-line demultiplexers
with individual strobes and common binary-address inputs
in a single 16-pin package. When both sections are enabled
by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit
activating or inhibiting each of the 4-bit sections as desired.
Data applied to input 1 C is inverted at its outputs and data
applied at2C is not inverted through its outputs. The
inverter following the 1C data input permits use as a 3-to-8line decoder or l-to-8-line demultiplexer without external
gating. Input clamping diodes are provided on all of these
circuits to minimize transmission-line effects and simplify
system design.

B

A

2Vl
111 OUTPUT
2V2

DATA -'. 11:. :5:.:.-1_ _...,
2C
STROBE ..;..11_4"'-.1_ _-,
2G

PIN-OUT DIAGRAM
14

13

12

11

4

5

6

15

16

2

3'

Die Size .063 x .069 (both

FUNCTION TABLE
3-LINE·TOoS·LlNE DECODER
OR l·LINE·TO·8-LlNE DEMULTIPLEXER

FUNCTION TABLES
2-LINE-TO-4·LlNE DECODER
OR l-LlNE-T004-LINE DEMULTIPLEXER
INPUTS
SELECT

,v,

lV2

'V3

H

x

H

H

H

H

L

L

H

L

H

H

H

H

L

H

H

L

H

H

H

H

L

H

H

H

H

H

H

H

x

X

L

L
H

L

L

H

H

L

X

x

X

•

OATA

,YO

,G

·0

-

I

I

.. L.:_

SELECT

lee
A

2G

x

x

H

I

~ l~ I
x

2-80

H

H

X

X

L

I

OR DATA

101

111

121

131

141

IS'

III

171

c'

B

x

x

H

H

H

H

H

H

H

H

H

L

L

L

L

L

H

H

H

H

H

H

H

H

L

L

H

L

H

L

H

H

H

H

H

H

L

L

H

l

L

H

H

l

H

H

H

H

H

H

l

H

H

l

H

H

H

l
H

H

H

H

H

l

H

OUTPUTS

STROB. IOATA

B

...

OUTPUTS
STROBE

SELECT

2C

2VO

2V,

2V2

2V3

x

H

H

H

H

L

L

H

H

H

L

H

L

H

H

L

H

H

L

H

L

H

H

H

L

H

H

H

H

H

A

GI

X

H

2YO 2Vl 2Y2 2Yl ,VO ,V, ,V2 'V3

L

L

l

H

H

H

H

H

H

l

H

l

H

H

H

H

H

l

H

H

H

H

l

l

H

H

H

H

H

H

l

H

H

H

H

L

H

H

H

H

H

H

H

l

H

--- --

0

INPUTS

_

..
INPUTS

,C

A

L....

, . - --- ...

OUTPUTS

STROBE

B

1234567[[j
Ie IG B JV31V2v1Y1lvqGND
DATASTR:E(ECT OUTPUTS
IIII'UT

types)

tC = inputs 1C and 2C connected together
tG = inputs 1G and 2G connected together
H = high levet, L = low level, X = don't care

~YTHE~

Dual 2-Line-To-4-Line
Decoders/Demultiplexers

LS155

LS156

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Min

4.5

Supply voltage, Vee
High-level output current, IOH
Output voltage, VOH (LS156 only)
Low-level output, IOL
Operating free-air temperature, T A

9LS/54LS
Typ·· Max

5

-55

5.5
-400
5.5
4
125

Min

4.75

9LS174LS
Typ·· Max

Unit

5.25
-400
5.5
8
70

/J. A
V
mA

5

0

V

C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted
TaBt Condition.·

Paramatar

VIH
VIL
VI
VOH
IOH
VOL
II
IIH
IlL
lost
leett

Min

9LS/54LS
Typ·· Max

2
Vee=MIN,
Vee-MIN,
VIL =VILmax,
Vee=MIN,
VIL =VILmax,
Vee=MIN,
VIL=VILmax
Vee=MAX,
Vee=MAX,
Vee-MAX,
Vee-MAX
Vee-MAX

11=-18mA
VIW2V,
IOH=-400/J.A
VIH-2V,
VOH=5.5V (LS156 only)
VIH-2V,
IIOL -4mA
IIOL -8m A
VI=7V
VI=2.7V
VI-0.4V

Min

9LS174LS
Typ·· Max

2
0_8
-1.5

0.7
-1.5
2.5

3.4

2.7

3.4

100
0.25

0.4

6.1

0.1
20
-0.4
-100
10

-15

0.25
0.35

-15
6.1

Unit

V
V
V
V

100
0.4
0.5
0.1
20
-0.4
-100
10

/J. A
V
mA
p.A
mA
mA
mA

'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttlee is measured with outputs open, A, B, and lC inputs at 4.5V, and 2e, 1G, and 2G inputs grounded.

~YTHEO]]

2-81

LS155

Dual 2-Line-To-4-Line
Decoders/Demultiplexers

LS156

LS155
Switching Characteristics , V'cc- 5V Over Recommended Free Air Temperature Range

-

Parameter

Levels

From
(Input)

of

Logic
Tnt Conditions: CL

To
(output)

Min

-55°C
Typ

Max

17
24
23
30
21
30

13
21
18
26
18
25

19
29
25
36
23
35

2
2
3
3
3
3

+25°C
Typ

Max

Min

+125°C
Typ
Max

Unit

= 15pF, RL = 2kO (See Fig. A, page 2-174)

y
2C, 1G, or 2G
tpLH
2
11
2C, 1G, or 2G
Y
2
15
tpHL
Y
A or B
16
3
tpLH
Y
tpHL
Aor B
20
3
1C
Y
15
tpLH
3
Y
1C
20
3
tpHL
Tnt Conditions: CL - SOpF, RL = 2kO (See Fig. A, page 2-174)
tpLH
tpHL
tpLH
tPHL
tpLH
tPHL

Min

2C,lG,or2G
2C,lG,or2G
Aor B
A or B
1C
1C

Y
y
Y
y
Y
Y

10
15
16
19
15
19
13
18
18
22
18
23

16
23
24
30
22
28

12
17
19
20
19
21

18
26
27
31
26
31

ns
ns
ns
ns
ns
ns

19
26
25
30
24
31

15
22
22
26
22
25

21
31
29
36
29
35

ns
ns
ns
ns
ns
ns

LS156
Switching Characteristics , V'cc- 5V Over Recommended Free -Air Temperature Range
Levels

-55°C
From
To
of
(input)
(output)
Min
Typ
Logic
Tnt Conditions: CL = 15pF, RL = 2kO (See Fig. B, page 2-174)

Max

y
2C, 1G, or 2G
2
24
tpLH
2C,lG,or2G
Y
tpHL
18
2
Y
A or B
tpLH
29
3
A or B
Y
tpHL
24
3
Y
1C
3
tpLH
27
y
1C
tPHL
25
3
Teat Conditions: CL - SOpF, RL - 2kO (See Fig. B, page 2-174)

Parameter

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

2
2
3
3
3
3

2C,lG,or2G
2C,lG,or2G
Aor B
Aor B
1C
1C

y
y
Y
Y
Y
Y

27
21
32
27
30
28

+25°C
Typ

Max

34
27
40
34
38
35

22
16
27
22
25
23

30
24
37
30
34
31

24
18
29
24
27
25

34
27
40
34
38
35

ns
ns
ns
ns
ns
ns

39
32
45
39
43
40

25
19
30
25
28
26

34
28
41
34
38
35

27
21
32
27
30
28

39
32
45
39
43
40

ns
ns
ns
ns
ns
ns

Min

Min

+125°C
Typ
Max

I

Unit

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for

2-82

9LS

only.

~YTHE~

Quadruple 2-Line-To-1 Line Multiplexers

LS157 LS158

DESCRIPTION
These data selectors/multiplexers select a 4·bit word from
one of two sources and present it at the four outputs:The
LS157 presents true data; the LS158 presents inverted data.
PIN-oUT DIAGRAMS

LS157

14 13 12 11 10

LS158

Vee

::I
~
In

4A'4i 4V '3A"3i

1ill15
15

12 11

9

2

3 4

5

~

14 13 12 11 10

3V

9

16

::I

INPUTS
INPUTS
OUTPUT
OUTPUT

Vee In
1ill15

15

8

8

7

7

2

1234567\]]

3 4

5 6

""'v-jjUTPUT'--v"'"'OUTPUT
IIII'UTS
IIII'UTS

3V

10 9

1234567\]]

SELECT 1A 18 1V 2A 28 2V GND

Die Size .047 x .066

13

9

16

6

INPUTS
INPUTS
OUTPUT
OUTPUT

4A'4i 4V '3A"3i

SELECT lA 18 1V 2A 28 2V GND

I""'v-jjNPUTS1I11'UT'--v"'"'01l11'UT
IIII'UTS

Die Size .047 x .066

LOGIC DIAGRAMS

LS157
lA (2)

1A

lB (3)

lB

2A (5)

2A

LS158

(2)
(3)

(5)
(6)

2B (6)

2B

3A (11)

3A

38 (10)

38

4A (14)

4A

4B (13)

4B

(11)
(10)
(14)
(13)

STROBE G (15)

STROBE G (15)

SELECT S 11

SELECT S

1)

FUNCTION TABLE
INPUTS
STROBE SELECT

OUTPUT Y
A

B

54LS157

54LSl68

H

X

X

X

L

H

L

L

L

X

L

H

L

L

H

X

H

L

L

H

X

L

L

H

L

H

X

H

H

L

H = high level, L = low level, X = don't care
Low level at S selects A inputs
High level at S selects B inputs
Strobe is active low

r:!VTHEO]']

2·83

LS157

Quadruple 2-Line-To-1-Line Multiplexers

LS158

Recommended Operating Conditions
9LS/54LS

Supply voltage, Vee
High·level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA

9LS/74LS

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
-400
4
125

4.75

5

5.25
-400
8
70

-55

0

Unit

V
p.A
mA

°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

VIH
VIL
VI
VOH
VOL

Test Condltlons*

Typ**

Max

2
Vee=MIN,
Vee-MIN,
VIL=MAX,
Vee-MIN,
VIL =MAX

S or G input
II
Vee=MAX,
A or 8 input
S or G input
Vee=MAX,
IIH
A or B input
S or G input
IlL
Vee=MAX~
A or B input
lost
Vee=MAX
lee tt

9LS/74LS

9LS/54LS

Min

Vee=MAX,

11=-18mA
VIW2V,
IOH=-400p.A
VIW2V,
l'OL-4mA
11m =8mA

Typ**.

2.5

Max

2
0.7
-1.5
3.4
0.25

VI=7V
VI=2.7V
VI=O.4V
-15

I LS157
I LS158

Min

9.7
4.8

0.8
-1.5
2.7

0.4
0.2
0.1
40
20
-0.8
-0.4
-100
16

8

3.4
0.25
0.35

-15
9.7
4.&

Unit

V
V
V
V

0.4
0.5
0.2
0.1
40
20
-0.8
-0.4
-100
16

.J!..

V
mA
p.A
mA
mA
mA

'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted et a time.
ttlee is measured with 4.5V applied to all inputs and all outpus open.

2-84

[[AYTHEO]J

Quadruple 2-Line-To-1 Line Multiplexers

LS157 LS158

-

Switching Characteristics , V'cc.- 5V Over Recommended Free Air Temperature Range
Parameter

From
(Input)

Test Conditions: CL = 15pF,

I tPLH
tPHL
. tPLH
. r-:::.:--=:..
tpHL
'1 tPLH
tpHL
tpLH
,I tpHL
I tpLH
tpHL
I tpLH
tpHL

RL

To
(output)

Data

y

LS158

Data

y

LS157

Strobe

y

LS158

Strobe

Y

LS157

Select

Y

LS158

Select

Y

RL

= 2kO

Data

Y

LS158

Data

Y

LS157

Strobe

Y

LS158

Strobe

y

.~ LS157

Select

y

Select

y

tPHL

.~

tpHL

LS158

Typ

+2SoC
Max

Min

+12SoC
Typ

Max

10

10
12
11
9
16
14
14
15
17
16
16
14

9
7
8
4
16
9
10
12
16
12
13
12

16
13
14
8
22
14
15
17
24
19
20
17

7
9
8
7
12
12
11
13
13
14
12
13

14
15
13
13
17
17
16
18
18
19
18
1a

10
10
10
7
18
13
12
15
16
14
15
15

17
16
16
12
25
18
17
21
21
20
22
21

Typ

Max

11
13
11
12
16
17
16
15
17
18
16
16

5
7
6
4
10
9
9
10
11
11
10

14
16
13
16

Min

Unit

6
8
6
7
10
12
10
10
11
13
10
10

ns
ns
ns
ns
ns
ns

(See fig. A,peas 2-174)

~ LS157

tPHL
I tPLH
tpHL
I tpLH
tpHL
I tpLH
. tpHL

Min

= 21<0 (See fig. A, page 2-174)

LS157

Test Condltlona: C L = 5OpF.

-SsoC

8
11
7
10
12
15
12
14
12
15
12
14

17

20
17

19
18
21
18
19

ns
ns
ns
ns
ns
ns

Note: AC specification shown under -55°C and +125°C are for 9LS devices only. All 50pF specifications are for 9LS only.

~YTHE03J

2-85

LS160

LS162

LS161

LS163

Synchronous BCD

Synchronous 4-Bit Binary Counters

FEATURES
•
4-bit synchronous counters
•
Synchronously programmable
•
Internal look-ahead counting
•
Carry output for n-bit cascading
•
Synchronous or asynchronous clear
•
Advanced low-power Schottky technology
•
100% reliability assurance testing in compliance with
MI L-STD-883
DESCRIPTION
The LS160, LS161, LS162 and LS163 synchronous, presettable counts have internal look-ahead carry and ripple
carry output for high-speed counting applications. The
LS160 and LS162 are decade counters and the LS161 and
LS163 are 4-bit binary counters. Counting or loading
occurs on the positive transition of the clock pulse. A LOW
level on the load input causes the data on the A, B, C and D
inputs to be shifted to the appropriate Q outputs on the
next positive clock transition.
The LS160 and LS161 feature an asynchronous clear. A
LOW level at the clear input sets the Q outputs LOW regardless of the other inputs. The LS162 and LS163 have a
synchronous clear. A LOW level at the clear input sets the
Q outputs LOW after the next positive clock transition
regardless of the enable inputs.
Both count·enable inputs P and T must be HIGH to count.
Count enable T is included in the ripple carry output gate
for cascading connection.

2-86

Decade~ounters

PIN-OUT DIAGRAM

7m

1 2 3 4 5 6
CLEAR CK ~ P GND
ENABLE
DATA INPUTS
14

13

12

11

10

9

15
16

8

7
2

3

4

Die Size .060 x .117:-' all 4 types

5

6

Synchronous BCD Decade Counters

LS160

LS162

Synchronous 4-Bit Binary Counters

LS161

LS163

LOGIC DIAGRAMS
LS160 Synchronous
Decade Counter
CLR
1
CLEAR o-:...-co-,

CK~--~-===~~~==t===~~~==~===4~====t===~~

CLOCK

LOAD~~~~

EN P
EN T

RIPPLE
CARRY

LS162 synchronous decade counters are similar; however,
the clear is synchronous as shown for the LS163 binary
counters.
LS163 SYNCHRONOUS
BINARY COUNTER

CL~~= o-~...,

fiA

°B

CLog~o-+-;>-t____~____+1_4____~____rl_3__~r-____+-12__--,

RIPPLE
CARRY

LS161 synchronous binary counters are similar; however,
the clear is asynchronous as shown for the LS160 decade
counters.

r§VTHEO]J

2·87

LS160

LS162_

Synchronous BCD Decade Counters

LS161

LS163

Synchronous 4-BitBin~ry Counters

Recommended Operating Conditions
9LS/54LS

Supply voltage, Vcc
High·level output current, IOH

Min

Nom

4.5

5

9LS/74LS
Max

Min

Nom

5.5

4.75

5.0

-400

Low-level output current, IOL

4

Clock frequency, f clock

25

0
25

Width of clock pulse, tw(clockl
Width of clear pulse, tw(clear)
Data inputs A, B, C, D
Enable P or T

20

Load

20

0
20
20

Clear<>
Data inputs A, B, C, D
Other inputs

Hold time, thold
Operating free-air temperature, TA

0

20

20

25~

25

10~

10

-55

125

Unit

5.25

V

-400
8

p.A
mA

25

MHz

25
20

20

Setup time, tsetup (see Figures 3 and 4)

0

Max

ns
ns

ns

ns

0

70

°c

OThis applies only for LS162 and LS163, which have synchronous clear inputs.
~ The minimum hold time is as specified or as long as the clock input takes to rise from 0.8 V to 2 V, whichever is longer.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

Min

9LS/54LS
Typ"
Max

2

VIH

Typ"

Vcc-MIN,

VOH
VOL

11- 18mA

VIW2V ,
VIL =VILmax, IOH=-400p.A

Vcc-MIN,

VIH-2V,

VIL =VILmax,

2.5

3.4
0.25

IIOL -4mA

VCC=MAX,

0.4

VI=7V

3.4
0.25
0.35

IIOL -8mA

Data or enable P
Load, clock, or
enable T

1.5
2.7

0.4
0.5

0.1

0.1

0.2

0.2

0.1

0.1

0.2

Data or enable P

20

0.2
20

40

40

20
40

20
40

0.4

0.4

-0.8
-0.4

-0.8
-0.4

VCC=MAX,

VI=2.7V

Data or enable P

V
V
V

Clear (LS160,161
Clear (LS162,163
Load, clock, or
IIH enable T
Clear(LS160,161
Clear(LS162,163)

Unit

V
0,8

1.5

Vcc-MIN,

Max

2
0.7

VIL
VI

II

9LS/74LS
Min

V

mA

p.A

Load, clock, or
IlL enable T
Clear(LS160, 161 )
Clear(LS162,163)

Vcc=MAX,

-0.8

lost

VCC=MAX

ICCH

Vcc=MAX,
Vcc=MAX,

ICCL

VI=O.4V

-15

-100

mA

-0.8
-15

-100

mA

See Note 1

18

31

18

31

mA

See Note 2

19

32

19

32

mA

*For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
**AII typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
NOTES:
1. ICCH is measured with the load input high, then again with the load input low. with all other inputs high and all outputs open.
2. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.

2-88

~YTHEO::J

Synchronous BCD Decade Counters

LS160

LS162

Synchronous 4-Bit Binary Counters

LS161

LS163

-

Switching Characteristics , V'cc- 5V Over Recommended Free Air Temperature Range
From
(Input)

Parameter
Test Conditions: CL

To
(output)

-SSDC
Min

Typ

Max

30

tpLH

Clock

tpHL
tpLH

Clock

tpHL

(load input high)

tpLH

Clock

tpHL

(load input low)

tpLH

Ripple carry
AnyQ
Any Q

Enable T

Ripple carry

Clear

Any Q

tpHL
tpHL

Test Conditions: CL

Clock

tpLH

Clock

tpHL

(toad input highl

tpLH

Clock

tPHL

Iload input low)

Ripple carry
Any Q
Any Q

Enable T

Ripple carry

Clear

Any Q

tpHL
tpHL

I
Max

Min

+12SDC
Typ
Max

Unit

28
23
13
18
13
18
18
13
17

39
39
22

24
22
24
25
18
32

40
25
20
10
15
10
14
15
9

14

MHz

35
35
18
20
18
20
20
14
28

28
23
13
18
13
18
18
13
17

39
39
22
24
22
24
25
18
32

31
26
16
21
16
21
21
16
20

44
44
27
29
27
29
30
23
37

ns
ns
ns
ns
ns

= SOpF. RL = 2kO (See Fig. 1 snd 2 and Notes 3 and 4 and Fig. A. page 2-174)

tpHL

tpLH

+2SDC
Typ

= 15pF, RL = 2k!l (See Fig. 1 and 2 and Notes 3 and 4 snd Fig. A, page 2-174)

f max

tpLH

Min

31
26
16
21
16
21
21
16
20

44
44
27
29
27
29
30
23
37

28
23
13
18
13
17
18
12
17

39
39
22
24
22
24
24
18
32

ns
ns
ns
ns
ns

NOTES:
3. Propagation delay for clearing is measured from the clear input for the LS160 and LS161 or from the clock input transition
for the LS162 and LS163.
4. AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications are for 9LS only.

~YTHEO]'J

2·89

LS160

LS162

Synchronous BCD Decade Counters

LS161

LS163

Synchronous 4-Bit Binary Counters
TYPICAL CLEAR, PRESET, COUNT, AND INHIBIT SEQUENCES

CLEAR - - - - - , r~__~--____~-----------------LS160·
(AYNSCHRONOUS)

rs

-U

CLEAR

LS162
LOAD

DATA
INPUTS

(SYNCHRONOUS)

U

r--------------------------------

{:~...Jr----+----.[ =
CD

FIGURE 1

1-_ _- . ,_ _11-

LS160,LS162

CLOCK _ _-+...,
LS160
CLOCK
LS162
1

Illustrated below is the following sequence:
1. Clear outputs to zero
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit

,

ENABLE P

----+!--i-I,

ENABLET

,:'I-t,-------~---_,
,
L -_ _

:,

OA===i '
{aB==::LH

Oc= =::LH======~~~~:___:_-----~­

OUTPUTS

Q D_
- -_

--LiJ--,
_

"--_ _ _-+-_______

"

I:

----

:
3:

RIPPLE CARRY _ _ _ _~I-~I-~!
IL.._~~~~,-------OUTPUT
:7 '8 9
0 1
2
I
t:---:-COUNT----II--INHIBIT--CLEAR PRESET

CLEAR
LS161

- - U (ASYNCHRONOUS)

1 ------------------CLEAR ----, 1 .
LS163
I...l.J (SYNCHRONOUS)

LOAD

LJ'----------------

I~:~~S :...J- ;.-:.-:.-:.~: :~ .~
{(

FIGURE 2

[=

D-.J

LS161, LS163

CLOCK ----;....,
LS161
CLOCK'
LS163
ENABLEP _ _ _~-,~
ENABLET

OUTPUTS{=

aD

,:r-I--------~-----,L_

___

Illustrated below is the following sequence:
1. Clear outputs to zero
2. Preset to binary twelve
3. Count to thirteen; fourteen fifteen, zero,
one, and two
4. Inhibit

~===;--'-~-+!--....J~'__
__

+_-------

::LJI-'-----"1.__--.;________
I

RIPPLE CARRY
OUTPUT

2·90

:
111<--::--::-+-------:12 13 14 15 0
24
I I
J---- COUNT--..,-INHIBITCLEAR PRESET

r§VTHEO]J

Synchronous BCD Decade Counters

LS160

LS162

Synchronous 4-Bit Binary Counters

LS161

LS163

FIGURE 1
PARAMETER MEASUREMENT INFORMATION
CLOCK INPUT
LS160
LS161

CLEAR
INPUT

LOAD
INPUT

VOH

VOH

3V
ENABLE POR
ENABLE T
OV
VOH

RIPPLE
CARRY
OUTPUT

VOL

VOH
QOUTPUTS
LS163
QA AND QD OUTPUTS

VOL

LS162

VOH

Qs AND Qc OUTPUTS
LS162

VOL

NOTES:
A. The input pulses are supplied by generators having the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%, Zout '" 50 fl.;
tr .; 15 ns, tf .; 6 ns.
S. Enable P and enable T setup times are measured at tn

~YTHEO~

= O.

2·91

LS160

LS1&2

Synchronous BCD Decade Counters

LS161

LS163

Synchronous 4.. Bit Binary Counters
FIGURE 4

PARAMETER MEASUREMENT INFORMATION
Io
._---II-'wl....kl

~~~:

d

b

1.3V
---1, .. ~y \:::...I:
..•.

.r,;;\
..
"-..L.r
- -- . 3V
ov

\~

-y

!--t- tpHL
1
! (me.UN at tn+2)

I.-...ojtpLH
:
I ImaMura at t~+1)
OUTPUT
QA

1/

III
~
I
I

1.3V

1.3V

I
I

I

j--oj- tpLH

I

I

(me_ure at t n+4)

--+------I~ I '
OUTPUT

\.1.3V

QB

~S

I

Dc

I (measure at tn+2)

1,.3V
.

VOH

- - - - - - - -

:..-...r..

'---"- 'PHL
I
: hneasure at t n+8)

OUTPUT

"-= :::

.

S

fo-...I.. tpHL

I IIr - - - " - ' - -

---;~-----:--....' { 1.3V
I
~S:
~I
lSee Note BI

00

1.3V

r--r tpLH
I

I

{measure at tn+S)

VOH

11

- - - - - - - -

I--t- tpHL
I

VOH

_ _ _ _ _ _ VOL

1.3V

S

I .

~.3~

l---+- tpLH

r---t- tpHL

__+-_____;.-!.., I '~~~).ttn+10
OUTPUT

VOL

tpLH
I (measure at tn+4)

VOL

(me_UN at t"+O or'tn+16)

RIPPLE ~:
~ -ISee Note BI - •• CARRY
1 3V
1.3V
OUTPUT
•
1-1_ _ _ _ _ _ _ _ _ __

VOH

VOL
VOLTAGE WAVEFORMS
NOTES:
A. The input pulses are supplied by a generator having the following characteristics: PRR '" 1 MHz, duty cycle", 50%, Zout '"

son: t r '" 15 ns,

tf '" 6 ns. Vary PRR to measure f max •
B. Outputs Qd and carry are tested at tn+1 0 LS160, LS162, and at tn+16 for LS161, LS163 where tn is the bit time when all outputs are low.

TYPICAL APPLICATION DATA

N-BIT SYNCHRONOUS COUNTERS
I hiS application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit counter. The
LS160 or LS162 will count in BCD and the LS163 will count in binary. Virtually any count mode (modulo-N, Nl-to N2,
Nl·to-maximum) can be used with this fast look-ahead circuit.

INPUTS

r---A-----o.

INPUTS·

,--J'I---..

INPUTS

INPUTS

r---A-----o.

~

LO A B C 0

LO A BCD

LO ABC 0

LO ABC 0

HzCOUNT
L=OISABLE

EN P

EN P

EN P

ENP

H-COUNT
L-OISABLE

RIPPLE
EN T CARRY
OUTPUT

RIPPLE
ENT CARRY
OUTPUT

RIPPLE
ENT CARRY
OUTPUT

RIPPLE
EN T CARRY
OUTPUT

'--v--'

'---v--'

'---v--'

'---v--'

OUTPUTS

OUTPUTS

OUTPUTS

TO MORE
SIGNIFICANT
STAGES

OUTPUTS

CLOCK-4_----------~----------~--------4_--------_+

2-92

t;YTHEO}J

8-Bit Parallel-Out Serial Shift Registers

LS164

PIN-OUT DIAGRAM

FEATURES
• Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Asynchronous Clear

LS164

...'"g
...

DESCRIPTION
These 8-bit shift registers feature gated serial inputs and an
asynchronous clear_ The gated serial inputs (A and B) permit
complete control over incoming data as a low at either (or
both) input(s) inhibits entry of the new data and resets the
first flip-flop to the low level at the next clock pulse. A
high-level input enables the other input which will then
determine the state of the first flip-flop. Data at the serial
inputs may be changed while the clock is high or low. but
only information meeting the setup requirements will be
entered. Clocking occurs on the low-to-high-Ievel transition
of the clock input. All inputs are diode-clamped to minimize
transmission-line effects.

m

3 4 5 6
A B fiA fiB fiCfiDGND
'--v-'~
f~:~ OUTPUTS

9LS/54LS devices are characterized for operation over the
full military temperature range of _55°C to 125°C; 9LS/
74LS devices are characterized for operation from O°C to
70°C.
FUNCTION TABLES
INPUTS

OUTPUTS

CLEAR

CLOCK

A

B

QA

L

X

X

X

L

QB···QH
L
L

H

L

X

X

QHO

t
t
t

H

H

QAO
H

QBO

H

QAn

QGn

L
X

X

L

QAn

QGn

L

L

QAn

QGn

H
H

H = high level (steady state). L = low level (steady state)
X = irrelevant (any input. including transitions)

t = transition from low to high level.
aAO. aBO. aHO

= the

level of aA. aB or aH. respectively. before the indicated

steady state input conditions were established.
QAn. QGn = the level of QA or QG before the most recent

t transition of the

clock; indicates a one-bit shift.

TYPICAL CLEAR, SHIFT, AND CLEAR SEQUENCES
CLEAR
SERIAL
INPUTS

~~--------------------~w~------

{A
B

CLOCK
Q

~~------~----_+-__-.Jr------------i----,

Q B :-:::,

Qc~~~l

OUTPUTS

QD~-::-l
Q E ~-::-::i

~"---_T_----~i....--+

_____

~'-+-----

r-Lrii....-____

Q

_ __
i:
F==: .l. __________---'!.....--.'.....+-_

Q

G ---1

QH:==l

CLEAR

~YTHEO]J

---Jr--L...r1'--___+-____

: ____
A ---.....

r---1!--'_ _ _ __

ri..' _____
CLEAR

2-93

8-Bit Parallel-Out Serial Shift Registers

LS164

(13)

OUTPUT

OUTPUT OUTPUT OUTPUT
Qs

QA

Recommended Operating Conditions

Qc

OUTPUT

QE

QG

Qo

Min
Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOl
Clock frequency, fclock
Width of clock or clear input pulse, tw
Data setup time, tsetup (see Figure 1)
Data hold time, thold (see Figure 1)
Operating free-air temperature, TA

OUTPUT

9LS/54LS
Nom
Max
5

4.5

0
20
15
5
-55

5.5
-400
4
25

125

Min

OUTPUT OUTPUT
Q

F

QH

9LSf74LS
Nom
Max

4.75

5

0
20
15
5
0

Unit
V

5.25
-400
8
25

/J. A
mA
MHz

70

ns
ns
°C

ns

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

Min

9LS/54LS
Typ" Max

Vee=MIN,
Vec=MIN,
VIL =VILmax,
Ver.-MIN,
VIL =VILmax
Vee-MAX,
Vee-MAX,

VOH
VOL
II
IIH

11=-18mA
VIH=2V,
IOH=-400/J.A
VIH-2V,

9LSf74LS
Typ"
Max

2

2

VIH
VIL
VI

Min

0.7
-1.5
2.5

3.5
0.25

IIOL -4mA
IIOL =8mA

0.8
-1.5
2.7

0.4

3_5
0.25
0.35

0.1
20
-0.4

VI-7V
V I -2.7V
VI-O.4V

Unit
V
V
V
V

0.4
0.5
0.1
20
-0.4

V
mA
/J. A
mA
mA
mA

Vee=MAX,
IlL
-15
-100 -15
-100
Vee-MAX
lost
16
16
27
27
Vee-MAX
lee tt
"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
""All typical values are at Vee = 5V, TA = 25'e.
tNot more than one output should be shorted at a time.
ttlee is measured with outputs open, serial inputs grounded, the clock input at 2.4V, and a momentary ground, then 4.5V applied to clear.

Switching Characteristics, Vee
Parameter
Teat Conditions: CL
f max
tpHL
tpLH
tpHL
Test Conditions: CL
tpHL
tpLH
tpHL

2-94

I

Min

-55'C
Typ

= 5V Over Recommended
Max

Min

+25'C
Typ

Max

= 15pF, RL = 2kn (See Fig_ 1, page 2-95 and
25
36
24
38
17
30
21
35
= 2kn (See Fig_ 1, page 2-95

26
20
24

= SOpF, RL

29
23
27

42
34
39

27
20
24

Free-Air Temperature Range

Min

+125'C
Typ
Max

Fig_ A, page 2-174)

36
26
38
27
20
30
32
24
35
and Fig. A, page 2-174)
40
31
36

Unit

29
23
27

42
34
39

MHz
ns
ns
ns
Note: AC specification shown

ns
ns
ns.

under _55°e and +125°e
are for 9LS devices only.
All 50pF specifications
are for 9LS only.

~YTHEO:FJ

a-Bit Parallel-Out Serial Shift Registers

LS164

FIGURE 1

PARAMETER MEASUREMENT INFORMATION

~I II

~ tw(elear) """1 ,.---------.....,l.rJ'I------------- 3V

CLEAR
PULSE

(;~~E:t~~~)

I

1.3V

1 3V

I "___

..J

_~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

OV

3V
CLOCK
PULSE
GENERATOR
(PRR ,,1 MHz)

I

I
-----:-----OV
_
k-- thold
!,etup ~

SERIAL INPUTS
A AND B PULSE
GENERATOR
(PRR,,1 MHz)

I

I

k-I

QA OUTPUT

(See Note A)

}V

I

I

'------t----tpHL

(See Note E)

I

I

tpLH

OV

~tpHLIE--

,.------~tf--------------~'\l-~3~ VO H

1.3V

\:VOl
VOLTAGE WAVEFORMS

NOTES: A.
B.

[§YTHEO]l

QA output is illustrated. Relationship of serial input A and B data to other Q outputs is illustrated in the typical shift sequence:
Outputs are set to the high level prior to the measurement of tPHL from the clear input.

2·95

4-By-4 Register Files with
Open-Collector Outputs

LS170

PIN·OUT DIAGRAM

FEATURES

LS170

• Separate Read/Write Addressing Permits Simultaneous
Reading and Writing
• Fast Access Times ... Typically 20 ns
• Organized as 4 Words of 4 Bits
• Expandable to 1024 Words of n·Bits
• For Use as:
Scratch· Pad Memory
Buffer Sto rage between Processors
Bit Storage in Fast Multiplication Designs
• Open·Collector Outputs with Low Maximum Off·State
Current: .... 20MA

9
8
7
6
5

DESCRIPTION

positive logic: see description

The 'LS170 MSI 16·bit TTL register file incorporates the
equivalent of 98 gates. The register file is organized as 4
words of 4 bits each and separate on·chip decoding is pro·
vided for addressing the four word locations to either write·
in or retrieve data. This permits simultaneous writing into
one location and reading from another word location.
Four data inputs are available which are used to supply the
4·bit word to be stored. Location of the word is determined
by the write·address inputs A and B in conjunction with a
write·enable signal. Data applied at the inputs should be in
its true form. That is, if a high·level signal is desired from
the output, a high level is applied at the data input for that
particular bit location. The latch inputs are arranged so that
new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the Din·
put is transferred to the latch output. When the write·enable
input, GW, is high, the data inputs are inhibited and their
:aVe:S cail cauSe no (;haflg~ in ih~ information stored in the
internal latches. When the read·enable input, G R, is high,
the data outputs are inhibited and remain high.

Die Size .090 x .068

The individual address lines permit direct acquisition of.
data stored. in any four of the latches. Four individual de·
coding gates are used to complete the address for reading a
word. When the read address is made in conjunction with
the read·enable signal, the word appears at the four outputs.
This arrangement-data·entry addressing separate from data·
read addressing and individual sense line-eliminates reo
covery times, permits simultaneous reading and writing, and
is limited in speed only by the write time (30 nanoseconds
tYPical) and the read time (25 nanoseconds typical). The
register file has a nondestructive readout in that data is
not lost when addressed.

LOGIC
WRITE FUNCTION TABLE (SEE NOTES A, B, AND C)
WRITE INPUTS
WB
L
L
H
H
X

WA
L
H
L
H
X

READ FUNCTION TABLE (SEE NOTES A AND D)
READ INPUTS

WORD
Gw

0

L
L
L
L
H

O=D

00

00

O=D

00
00
00

1

00
00
00

OUTPUTS

2

3

RB

RA

GR

01

02

03

04

00
00

00

O=D

00

L
L
H
H
X

L
H
L
H
X

L
L
L
L
H

WOBI
W1Bl
W2Bl
W3Bl
H

WOB2
W1B2
W2B2
W3B2
H

WOB3
W1B3
W2B3
W3B3
H

WOB4
W1B4
W2B4
W3B4
H

00

00

O=D

00

00

NOTES: A. H = high level, L = low level, X = irrelevant.
B. (0 = D) = The four selected internal flip·flop outputs will assume the states applied to the four external data inputs.
C. 00 = the level of before the indicated input conditions were established.
D. WOBI = The first bit of word 0, etc.

a

2·96

~YTHEO~

4-By-4 Register Files with
Open-Collector Outputs

LS170

FUNCTIONAL BLOCK DIAGRAM

'LS170

-t__~__-+==:;===4==~======'-lF=J~)

(11115~)bo____~__
D1-

(1)

D2

DATA
INPUTS

OUTPUTS

(2)

D3

GW
WA
.WB, WRITE INPUT

r§VTHEo"EJ

----

(4) Ill) IS)
RB
GR RA
READ INPUT

2-97

4-By-4 Register Files with
Open-Collector Outputs

LS170
Recommended Operating Conditions

9lS/74lS

9lS/54lS
Min.
Supply voltage, VCC

4.5

Nom. Max.
5

5.5

High·level output voltage, VOH
low·level output current, IOl
Width of write-enable or read-enable pulse, tw

Min.
4.75

Nom. Max. Unit
5

'V

5.25

5.5

5.5

4

8

V
mA

25

25

ns

10

10

ns

15

15

ns

15

15

5

5

Data input with respect to
Setup times, high· or low·level data

write enable, tsu(D)
Write select with respect to
write enable, tsu (W)
Data input with respect to

Hold times, high· or low·level data

write enable, th(D)

(see Note 1 and Figure 2)

Write select with respect to
write enable, th(W)

25

Latch time for new data, tlatch (see Note 2)

125

ns
ns
ns

25

-55

Operating free-air temperature range, T A

,

70

0

·C

NOTES: 1. Write·select setup time will protect the data written into the previous address. If protection of data in the previous address is
not required, tsu(W) can be ignored as any address selection sustained for the final 30 ns of the write·enable pulse and during
th(W) will result in data being written into that location. Depending on the duration of the input conditions, one or a number
of previous addresses may have been written into.

2. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is im·
portant only when attempting to read from a location immediately after that location has received new data.

Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Test Conditions t

Parameter
VIH High-level input voltage

9lS/54lS
Min.

vI

:iij:iut ..:.lClIIIIJ vUitClge

IOH High-level output current

VCC = MIN,

II =-18mA

VCC = MIN,

VOH = 5.5V,

VCC = MIN,
VIH = 2V,
VIL = VIL max
Input current at

Any 0, R, orW

maximum input voltage

GR orGW
Any 0, R, orW

IIH

High-level input current

IlL

Low-level input current

IOL=4mA

V

0.7

0.8

V

-1.5

-1.5

V

20

20

0.25

Any 0, R, orW

0.4

IOL=8mA

VCC= MAX,

VI =7V

VCC = MAX,

VI = 2.7V

VCC = MAX,

VI = 0.4V

Vcc = MAX,

See Note 3

GR orGw

ICC Supply current

Typ;F Max. Unit

mA

VIL = VIL max, VIH = 2V

VOL Low-level output voltage

II

Min.
2

2

VIL Low-level input voltage

...

9lS/74lS

Typ;F Max.

GRorGw
25

0.25

0.4

0.35

0.5

0.1

0.1

0.2

0.2

20

20

40

40

-0.4

-0.4

-0.8

-0.8

40

25

40

V

mA

mA

mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
"'All typical values are at VCC = 5V, TA = 25·C.
NOTE
3. ICC is measured under the following worst-case conditions: 4.5 V is applied to all data inputs and both enable inputs, all address inputs are grounded, and all outputs are open.

2-98

t[AYTHEOEJ

4-By-4 Register Files with
Open-Collector Outputs

LS170

Switching Characteristics Vee = 5.0V Over Recommended Free-Air Temperature Range.

Tut Conditions:

-Ssoc

From

To

(Input)

(Output)

Parameter
RL

=

2.0k, CL

Read

tPHL

enable

tPLH
tpHL

Read
select

Any Q

tPLH

Write
enable

Any Q

Data

Any Q

tpLH

22
22
26
27
33
29
32
25

Any Q

tpHL

Tut Condition:

RL

= 2.0k, CL = 5OpF,
Read

tpLH
tpHL

enable

tpLH
tpHL

Read
select

tpLH

Write

Data

tpHL

Min.

Typ.

+12SoC
Max.

Min.

Unit

Typ. Max.

20
20
25
24
30
25
30
22

34
34
44
44
49
44
49
39

30
30
40
40
45
40
45
35

23
23
28
27
33
28
33
25

34
34
44
44
49
44
49
39

35
35
45
45
50
45
50
40

27
27
32
31
37
32
37
29

39
39
49
49
54
49
54
44

ns

ns
n.
ns

(See Figs. 1 and 2 and Fig. B, psge 2-174)

27
27
32
31
37
32
37
29

Any Q
Any Q
Any Q

tpHL
tpLH

+2SoC

Typ. Max.

= 15pF, (See Figs. 1 snd 2 snd Fig. B, psge 2-174)

tpLH

tpHL

Min.

Any Q

39
39
49
49
54
49
54
44

24
24
29
28
34
29
34
26

ns

ns
ns
ns

PARAMETER MEASUREMENT INFORMATION
WRITE·SELECT
INPUT WA or Ws
(See Note Al
DATA INPUT
01,02,03 or 04
(See Note AI

WRITE· ENABLE
INPUT GW
READ·SELECT
INPUT RA or RS
(See Note B)

.r-----\----------------3V

g~,T6tQJor04iref

\ . ._________

1'---------oV
,~~~--------3V

WRITE· ENABLE
INPUT Gw

~~~~--------oV

DA T A INPUT
01,02,03 or 0 4 _ _

1'---J'-------------------3V

f

:":'::PL"":H:---

~

Vref

VOLTAGE WAVEFORM 1

/

1'-------3V

,,.-----oV

I'---~'+------

3V
VOH

OUTPUT
Q1, 02, 03 or Q4

--;--;-::'P"":L-HJ
DATA INPUT
01,02,03 or 04

VOLTAGE WAVEFORMS

FIGURE 1

V::t

\l.'' i-'v_"'-,--'

1,.---.--------oV

READ· ENABLE -------~I
INPUT GR

~

/
•

I---+l 'PLH

1'--+-J·~~~~--------3V

/

Vref
VOLTAGE WAVEFORM 2

FIGURE 2

NOTES: A. High·level input pulses at the select and data inputs are illustrated in Figure 1; however, times associated with low·level
pulses are measured from the same reference points.
B. When measuring delay times from a read-select input, the read-enable input is low. When measuring delay times from the

read-enable input, both read·select inputs have been established at steady states.
C. In Figure 2, each select address is tested. Prior to the start of each of the above tests, both write and read address inputs are
stabilized with WA ~ RA and Ws ~ RS. During the test GR is low.
D. Input waveforms are supplied by generators having the following characteristics: PRR .;;; 1 MHz, Zout '" 50 n, duty cycle
.;;; SO%, tr .;;; 15 ns and tf .;;; 6 ns.
E. Vret ~ 1.3 V.

~YTHEO"EJ

2·99

LS174

Hex D-Type Flip-Flops With Clear

LS175

Quadruple D-Type Flip-Flops With Clear
PIN-OUT DIAGRAMS

FEATURES
• Positive edge-triggered common clock
• Asynchronous common reset
• Clock-to-output delays of 14 ns
DESCRIF'TION.
The LS174 is a six-bit register with single-rail outputs and
the LS175 is a four-bit register with complementary outputs. Both consist of Ootype flip-flops with a buffered
common clock and an asynchronous, active-Low buffered
clear.

Information at the 0 inputs meeting the setup time reQuirements is transferred to the Q outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock
input is at either the high or low level, the 0 input signal
has no effect at the output.

INPUTS

Q

ot

x

L

H

H

H

L

H

t

L

L

H

H

L

X

Go

aD

12 11 10

9

8

7

OUTPUTS
D

14 13

16

3

Die Size .056 x .085 2

FUNCTION TABLE
(EACH FLIP-FLOP)
--_. _..CLEAR CLOCK
L
x
H
t

15

15 14

13

4

12 11 10

16

H = high level (steady state I
L = low level (steady state)
5
234
x = irrelevant
t = transition from low to high level
00 = the level of Q before the indicated steady state
Die Size .056 x .085
input conditions were established.
LOGIC DIAGRAMS
t = !"li! 75 only
LS174

6

LS175

CLOCK~9~1~J-----~--~------~--~------~~~~----~

2-100

~YTHEO]]

Hex D-Type Flip-Flops With Clear

LS174

.Quadruple D-Type Flip-Flops With Clear

LS175

Recommended Operating Conditions
Min
Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Clock frequency, f clock
Width of clock pulse, tw (Low)
Width of clear pulse, tON (Low)

4.5

I

Data input tsetuD
]Clear recovery, tree

Setup time
Data hold time, thold
Operating free-air temperature, TA

9LS/54LS
Nom
Max

5

0
15
20
10
12
5
-55

5.5
-400
4
35

125

9LSI14LS

Min

Nom

Max

4.75

5

5.25
-400
8
35

0
15
20
10
12
5
0

70

Unit
V
J1A
rnA
MHz
ns
ns
ns
ns
ns

°c

tsetup is the minimum time required for the correct logic level to be present at the data input prior to the rising edge of the clock in order to

be recognized and transferred to the output.
thold is the minimum time required for the logic level to be maintained at the data input after the rising edge of the clock in order to insure
recognition.

tree is the minimum time required between the end of the clear pulse and the rising edge of the clock in order to transfer High data to the Q

output.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions·

Parameter
VIH
VIL
VI

Min

9LS/54LS
Typ·· Max

Min

9LSI14LS
Typ·· Max

2

2
0.7
-1.5

11=-18mA

0.8
-1.5

II
IIH

Vee=MIN,
Vee=MIN,
VIL =VILmax,
Vee-MIN,
V IL =VILmax
Vee=MAX,
Vee-MAX,

VI=7V
VI=2.7V

0.1
20

0.40
0.5
0.1
20

IlL

Vee=MAX,

VI=O.4V

-0.4

-0.4

VOH
VOL

VIH=2V,
IOH=-400J-lA
VIH-2V,

2.5

3.5
0.25

IIOL =4mA
IIOL =8mA

2.7
0.4

3.5
0.25
0.35

Unit
V
V
V
V
V
rnA
J-IA
rnA

-15
-15
-100
-100
rnA
LS174
16
26
16
26
Vee=MAX
rnA
LS175
11
18
11
18
I
"For conditions shown as MIN or MAX, use the approproate value specIfIed under recommended operating condItions for the applicable
device type.
""All typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
ttWith all outputs open and 4.5V applied to all data and clear inputs, ICC is measured, after a momentary ground, then 4.5V is
applied to clock.
lost

lee tt

Vee=MAX

I

..

~YTHEC!aJ

2-101

LS174

Hex D-Type Flip-Flops With Clear

LS175

Quadruple D-Type Flip-Flops With Clear

Switching Characteristics, Vee = 5V Over Recommended Free-Air Temperature Range
Parameter

From

(Input)

_55°C

To
(Output)

Min.

Typ.

+25'C
Max.

Min.

Typ.

+125'C
Max. Min.

Typ.

Units

Max.

Test Conditions: C L = 15pF, RL = 2k!1 (See Figure A on page 2·174)
f max

tPLH

maximum clock
frequency
clear

35

45

MHz

Q

19

25

19

25

25

31

ns

Q

23

29

19

25

22

27

ns

'(LS175 only)

tpHL

clear
(LS175 only)

tpLH

clock

QorQ

14

20

13

17

14

19

ns

tpHL

clock

QorQ

16

23

13

18

13

18

ns

Test Conditions: C L = 50pF, RL = 2k!1 (See Figure A on page 2-174)
tpLH
tpHL

clear

Q

21

27

'22

27

28

35

ns

Q

25

33

23

28

25

30

ns

(LS175 only)
clear

(LS175 only)
tpLH

clock

QorQ

16

22

15

19

17

21

ns

tpHL

clock

QorQ

20

28

17

23

17

22

ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS only.

2·102

~YTHE~

4-Bit Arithmetic Logic Unit

LS181

Subtraction is accomplished by 1's complement addition
where the 1 's complement of the subtrahend is generated
internally. The resultant output is A-B-l which requires an
end-around or forced carry to provide A-B.

FEATURES
•
Provides 16 arithmetic operations
•
Provides 16 logic operations
•
Fulliook-ahead for high-speed arithmetic operation
on long words

The LS181 can also be utilized as a comparator. The
A = B output is internally decoded from the function outputs
(Fa, Fl, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high
level to indicate equality (A = B). The ALU should be in
the subtract mode with Cn = H when performing this comparison. The A = B output is 'open-collector so that it can
be wire-AND connected to give a comparison for more than
four bits. The carry output (C n +4) can also be used to
supply relative magnitude information. Again, the ALU
should be placed in the subtract mode by placing the
function select inputs, S3, S2, Sl, SO at L, H, H, L,
respectively.

DESCRIPTION
The LS181 is an arithmetic logic unit (ALU)/function
generator which has a complexity of 75 equival~nt gates on
a monolithic chip_ This circuit performs 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and
2. These operations are selected by the four function-select
lines (SO, Sl, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic
manipulations, the internal carries must be enabled by
applying ~ low-level voltage to the mode control input (M).
A full carry look-ahead scheme is made available in these
devices for fast, simultaneous carry generation by means of
two cascade-outputs (pins 15 and 17) for the four bits in
the package. Wh~n used in conjunction with the 182, full
carry ahead look-ahead circuits, high-speed arithmetic
operations can be performed.

INPUT

If high speed is not of importance, a ripple-carry input
are available.
However, the ripple-carry delay has also been minimized so
that arithmetic manipulations for small word lengths
can be performed without external circuitry.
\

~

The Lsi81 will accommodate active-high or active-low
data if the pin designations are interpreted as follows:

PIN NUMBER
2
Active-low data (Table 1) AO
Active-low data (Table 2) AO

OUTPUT

Cn +4

ACTIVE·HIGH DATA

ACTlVE·LOW DATA

(FIGURE 11

(FIGURE 21
A;>B

H

H

H

L

A"B
A>B

L

H

AB

L

L

A;>B

A"B

A

J

(21)

...--..

J

B1

!.ill

H>

~

if-

I
A1

.!!L

iHL
tpLH
tpHL
tpLH
tpHL

Load
Data A,B,C,D °A,OB,OC,OO
Clock

Ripple Clock

Clock

OA,OB,OC,OO

Clock

Max/Min

Down/Up

Ripple Clock

Down/Up

Max/Min

Enable

Ripple Clocl~

28
39
2u
41
19
22
22
30
34
43
36

42
59
31
61
29
33
33
45
51
61

~6

fi4

27
28
27
28

42
43
42
43

54

25
36
17
'38
16
19
19
27
31
40
33
33
24
25
2425

I

Unit

MHz

25
37
33
22
tpLH
25
Load
OA,OB,Oc,OO
36
54
33
50
tpHL
36
14
LL
tpLH
17
17
26
Data A,B,C,D °A,OB,Oc,OO
38
56
35
50
tpHL
38
16
24
13
20
tpLH
16
Ripple Clock
Clock
19
28
16
24
tpHl
19
19
28
16
24
tpLH
19
Clock
OA,OB,OC,OO
27
24
40
36
tpHL
27
31
28
42
46
tPLH
31
Max/Min
Clock
40
37
52
56
tpHL
40
30
45
33
49
tpLH
33
Down/Up
Ripple Clock
30
45
33
49
tpHL
33
33
21
24
tpLH
37
24
Down/Up
Max/Min
22
33
25
tpHL
38
25
21
33
24
tpLH
37
24
Enable
Ripple Clock
22
33
25
tpHL
38
25
Teat Condltlona: Cl = SOpF. Rl = 2kO (See FIg. 1 thru 7 on pages 2-115 and 2-116 and Fig. A on page 2-174),
tpLH
tpHL
IPLH
tpHL
tPLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH

Max

37
04

26
54

24
28
28
40
46
56
49
49
37
37

37
37

28
39
20
41
19
22
22
30
34

43
36
36
27
28
27
28

37
54

26
56
24
28
28
40
46
56
49
49
37
38
37
38
42
59
31
61
29
33
33
45
51
61
54
54

42
43
42
33

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only.
All 50pF specifications are for 9LS only.

2-112

~YTHE~

Synchronous BCD Decade Up/Down Counter

LS190

Synchronous 4-Bit Binary Up/Down Counter

LS191

LOGIC DIAGRAM
LS190

-.. -.. .

CLOCK~--------------------------------'
DOWN/UP (5)

-'~

I

»

r---i

..-----tv~rj:;;;:~~~~[)

rP-~
,,1>-_---'("-'13;;.:...) RIPPLE
CLOCK
(12) MAX/MIN

>-----+-~~------'-'=- OUTPUT

DATA~(1~5~)~+-1_______-+-~~~-~~-r~
INPUT A

JJJH~----+-+---'A
~-

r--.

ENABLE G

(,:::.4)~+-----H--+-+-+--+--+-I------+----...
.TI--r--.r--.
-

-

~RESa~t--.......(_3) OUTPUT OA

~ ~ CK
__ K
QA
CLEAR
'(

~

F
DATA ~(1~)_ _ _-4-+--+-~~--+-~_+_~~
INPUT B
J '-

-

r--r- :RES~~t----"(2=-) OUTPUT OB
~>CK

-

'-- K
QBr--.
CLEAR-

UlH!~~h~~~i-tf)~~J

DATA ~(1~O~)_ _ _-+-+-~-+--+-~-+~-+-~r-~
INPUT C
I }:J>-+---.----+---,,\

...-,~~-H_±~----t-

~RES~~

~~>+----. ~~CK
->---

U-l----t-~-l--t:+=~:::t.~

(6) 'OUTPUT

Oc

- r - ~LEA9f-

?
DATA ..:.19..:.)_ _ _-+-+--+-H_+~+_H_+--~~
INPUTD

-

1

I~
'-~--.-----+---,

'- ---i

r-- -

,

PRESET
(7)
J.
0Dt--...-:'-'- OUTPUTOD

--<:>CK
'-- K
QDr--.
CLEAR

(11)

LOAD

nJr---.. J.

>-__+-__-+--+-_____________---t__

~I

::-{
--

~YTHE03'l

2-113

LS190

Synchronous BCD Decade Up/Down Counter

LS191

Synchronous 4-Bit Binary Up/Down Counter
LOGIC DIAGRAM

LS191
CLOCK (14)
DOWN/UP

-

(5)

I

r--' pJ>-_-.--;1c.;.;13;.;..) RIPPLE
CLOCK

> - _ 4 4......_ _ _--..,....;1c.;.;12...;..) ,MAXIMIN
OUTPUT

D~TA .:.:11c;:.5:. . )H'-----iH+-+-HH+-.""
~_
I )>1~---++---'A

INPUT A

~ r--ENABLE G, -,-,14,,-)+-.----I-+-+-t--f-+_+_+-t--f-RESE1 t--......~13:....) ,OUTPUT QA
J
QA

~>--_+_---~ ~ ~ CK
'-f--

~LE~t

f--

Y
DATA (1)
~
INPUT B --'---·--~-++-+-1f--+-++-+-1~-I,--'

-----

r- -

J

1

~RES~~

(2)

OUTPUT QB

~~CK

'-_ K

QB

CLEAR' -

~++++~~~------~r-~J)
DATA
INPUTC

I

1~1~D)----H-+++-H-+~+-~-.I'~~__1I__-t~;;,~~
.I

- r - rRES~ ~-.:.::16,,-) ,OUTPUT Dc
~~CK
--

~LEA~~
V

DATA
INPUT D

(=9:....)----iH+-+-H-++-+-H--r~

...../'"»---......---+---,1

I

~ ---t

(11)

LOAD

2-114

>-__~~~______________~~~J

-f--

~RES~~r---+-(7)~ OUTPUT QD

L-c~CK

-

K..._.QDf-~AR

J

~YTHEO:?J

Synchronous BCD Decade Up/Down Counter

LS190

Synchronous 4-Bit Binary Up/Down Counter

LS191

LS190 TYPICAL LOAD, COUNT AND INHIBIT SEQUENCES

Illustrated below is the following sequence:
1.
2.
3.
4.

Load (preset) to BCD seven.
Count up to eight, nine (maximum). zero, one, and two.
Inhibit.
Count down to one, zero (minimum). nine, eight, and seven.

LOAD~
I
I

A..J

DATA
INPUTS

iL. _

B..J

IL..

-

C..J

IL..

_

D

r- -

_

-

CLOCK
DOWN/UP!
ENABLE!

,

----rl
I
Ii
----:nI~i---------------------~------~~~---------------~r
C ___ ~

Q B ___
Q

~

I~'

__________________

~

L

L..UI'

---,
QD ____

I I

MAX/MIN

:::J ::
I,

I,

RIPPLE ----I
I I
CLOCK ___ ..J
I I
: 7 118

I

U
9

I

0

1

2

II--COUNT UP--+INHIBIT.J

2 11

u

0

9

8

7

I--COUNT DOWN---I

~

LOAD

~YTHEO]J

2-115

Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter

LS190
LS191

LS191 TYPICAL LOAD, COUNT AND INHIBIT SEQUENCES

Illustrated below is the following sequence:
1.
2.
3.
4.

Load (preset) to binary thirteen.
Count up to fourteen, fifteen (maximum). zero, one, and two.
Inhibit.
Count down to one, zero (minimum), fifteen, fourteen, and thirteen.

LOAD-U
, ,

r-+---.:...,
-'L-_

A

~

,

:[=
, ,
C ~-­
-': :L-_
,
o-1:
r-:--7"1 - ;L-_
B

DATA
INPUTS

I

I
I

DOWN/UP-'~~~______________~

,,

"
ENABLE:-1I~~~
__________~

,'

'-+1~ ,i------.,

QB - -,
___

Qc
QD

MAX/MIN

::J
::J

I', .

L

'----~.

,,

,," ,,
,, ,'
, I

=-=J ::, , n

RIPPLE - --'I-L.:'' - - - - ,
CLOCK -- -: ::

,13, ,14

U

15

n '-------0

1

2

"U
0 15

2,2, 1

U~COUNT UP -4INHIBIT~

14

13

l--COUNT DOWN--I

LOAD

2·116

~YTHE03l

Synchronous BCD Decade Up/Down Counter

LS190

Synchronous 4-Bit Binary Up/Down Counter

LS191

PARAMETER MEASUREMENT INFORMATION
DATA

J

0_N-S---'::-910"'.%3""'--'V~' --,:'~-1-0~%"0-~S_ - - - - - 30VV

INPUT
•• • _ .,/'",'","=1
(SEE NOT~ 1~~
LOAD
INPUT
(SEE NOTE Al

I~

:'-'-';".tse
"~tu~pc-__

tsetup":"'-"':
1.3V'
10%

1.:W'" 90%
3V
10% __ ~ _______ OV
--! ,'-"10NS

~:::

OUTPUT

FIGURE l-DATA SETUP TIME VOLTAGE WAVEFORMS

"10NS-<.....
INPUT
(SEE NOTE Al
10%

See waveform sequences in Figures 4 through 7 for
propagation times from a specific input to a specific
output. For simplification, pulse rise times, reference
levels, etc., have not been shown in Figures 4 through 7.

--'

.r.=-:--::::=~'_

i.-"10NS

-: - - - - - -

-·3V

I
I

~1;.;0%;;;;..._ _ _

OV

,..-_ _ _",\;- - - - - - VOH
NON INVERTING
OUTPUT

1

,

,....tPHL..,

FIGURE 2- GENERAL VOLTAGE WAVEFORMS
FOR PROPAGATION TIMES

1

i

INVERTING
OUTPUT

VOL

1

,....tPLH.~i

\1.3V

VOH

1.3V/

,...tPHL.., ~.- - - - - ' - - - - - - VOL

NOTES:
A. The input pulses are supplied by generators having the following characteristics: Zout ~ 50n, duty cycle" 50%, PRR " 1 MHz.

LOAD

,,
,
~~------------------

ANY DATA INPUT _ _ _ _ _ _ _ _..J
CORRESPONDING ____-:_-

a OUTPUT

,,

_-_'LI___-'-~I
'

tPLH ~

,

:...

--'I

I

I

:-tPHL

NOTE 8: Conditions on other inputs are irrelevant.

FIGURE 3-LOAD TO OUTPUT ANP DATA TO OUTPUT
LOADU

L-

DOWN/UP

I

I

CLOCK
ENABLE G

I

1
I

--l I-

:

--l :- tpLH

tpHL
RIPPLE C L O C K - - - - - - - - - - - - " -........""!.I_ _ _..JI

tpHL

--l......

--l:- tpLH

: --___:!-'I
--1 ......
---==-rL

tPLH.......,.M A X / M I N - - - - - - - - - - - - - - - , I;NOTE

~YTHE~

c:

tpHL

All data inputs are low.
FIGURE 4-ENABLE TO RIPPLE CLOCK, CLOCK TO RIPPLE CLOCK, DOWN/UP TO MAX/MIN

2·117

Synchronous BCD Decade Up/Down Counter
r
Synchronous 4-Bit Binary Up/Down Counter

LS190
LS191

PARAMETER MEASUREMENT INFORMATION (Continued)

U

LOAD:---U

DATAINPUTS:- - - - - - - - - -....- - - - - - - - - - - - - - - ( S E E N O T E S G T O I l - - - - - - - - - - - - - - - - J1 - - - DOWN/UP

~

U

COUNT
I
I
OUTPUT(S) __ -,
- ; r~_t_P_L;.;H_ _ _ _ _ _ _ _ __i.I___l:- tpHL
UNDER TEST ___ ,-'_ _ _ _ _ _~.
IL._ _ _ _ _ _ __
ENABLE

= LOW

F. to test OA, OB, and Oc outputs of LS190: Data inputs A, B, and C are shown by the solid line. Data input 0 is shown by the dashed line.
G. To test OD output of LS190: Data inputs A and D are shown by the solid line. Data inputs Band C are held at the low logic level.
H. To test OA, 0B, 0C, and OD outputs of LS191: All four data inputs are shown by the solid line.
FIGURE 5-CLOCK TO OUTPUT

u

LOAD--U

DATA A
DAT~:fN~~~~----------------J1

_________ _

DOWN/UP
COUNT

l::!---JI:-

tpLH

ld
I

MAX/MIN_ _ _ _ _
ENABLE

= LOW

NOTE I:
Data inputs Band C are shown by the dashed line for the LS190 and the solid line for the LS191: Data input D is shown by the solid
line for both devices.

FIGURE 6-CLOCK TO MAX/MIN

2-118

~YTHEO]J

Synchronous BCD Decade Up/Down,Counter

LS192

Synchronous 4-Bit Bin~ry Up/Down Counter

LS193

FEATURES
•
•
•

PIN-OUT DIAGRAM

Separate clock inputs for count-up, count.down
Asynchronous parallel load and clear
Cascadable

DESCRIPTION
These monolithic circuits are synchronous reversible
(up/down) counters having a complexity of 55 equivalent
gates. The LS192 is a BCD counter and the LS193 is a
4-bit binary counter. Syn
v

COUNT

°At---<__ciA

INPUT C

1(1~)------~1Ol:~~~~~~§E~~U
[1--1".1.

~

r-(2)
~BI----1~- OUTPUT OB

-~O~) Ji~~;;;~~'------:~P.t~D=§EJ~J~

(1

~

__

DATA
INPUT D -

(6)

n
- '-----1-- OUTPUT Oc
~.---T

b~

((9~)~----~iWJ£~~~~~==][~~
'"

:-f- J

(14)

CLEAR

~=F~~~~

2-120

r'-

r1. . /

,,",++-+Hi::~::!:::::1~
.....
~

-

LOAD

~

OUTPUT OA

~~

~

DATA

OUTPUT

(11)

J'o>.
y

(7) OUTPUT OD
1»-_--

~
-

~YTHEO!)

Synchronous BCD Decade Up/Down Counter

LS192

Synchronous 4-Bit Binary Up/Down Counter

LS193

LOGIC DIAGRAM
LS193
(13) BORROW
OUTPUT
(12)

DATA
INPUT A

(15)

DOWN
COUNT

(4)

UP
COUNT

DATA
INPUT B

~

(""L../

"

X>

(5)

rL--"
I
I

(10)

~
..r-\.
Ir\. ../

CLEAR

LOAD

~YTHEO!J

(11) J'oo.

---v

OUTPUT QB

If
*

(6)

OUTPUT

Dc

T

n
(14)

(2)

T

C=¢o
(9)
DATA
iNPUT D

bQ
~

D
DATA
INPUTC

OUTPUTQA

T

b

(1)

(3)

CARRY
OUTPUT

bH

...f"""'.

=-k
I r1---'

~

~

(7)

OUTPUTQD

T

hJ]

2-121

LS192

Synchronous BCD Decade Up/Down Counter

LS193

Synchronous 4-Bit Binary Up/Down Counter

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Test Conditions·

Min

9LS/S4LS
Typ·· Max

Vee-MIN,
Vee=MIN,
V IL =VILrnax,
Vee=MIN,

VOH
VOL

11-- 18
VIH-2V,
IOH=-400pA
VIH=2V,

VIL =VILrnax
VI-7V
Vee-MAX,
VI-2.7V
Vee-MAX,
VI-O.4V
Vee-MAX,
Vee-MAX
Vec-MAX

II
IIH
IlL
lost
lee tt

9LS/74LS
Typ·· Max

2

2

VIH
VIL
VI

Min

0.7
-1.5
2.5

3.4
0.25

IIOL =4rnA

0.8
-1.5
2.7

0.40

3.4
0.25
0.35

IIOL =8rnA
0.1
20
-15
19

..

-0.4
-100
34

-15
19

Unit
V
V
V
V

0.40
0.5
0.1
20
-0.4
-100
34

V
rnA
pA
rnA
rnA
rnA

"For conditions shown as MIN or MAX, use the appropriate value specIfIed under recommended operating conditions for the applicable
device type .
• 'All typical values are at Vee = 5V, TA = 25 C.
tNot more than one output should be shortad at a time.
ttlec is measured with all inputs grounded and all outputs open.
Q

-

Switching Characteristics, V'cc -- 5V Over Recommended Free Air Temperature Range
From
(Input)

Parameter
Test Conditions: CL

-

15pF,

RL -

SsoC

To
(output)
2k!l

Min

+2SoC

Typ

Max

19
18
18
18
27
33
29
31
24

29
28
28
28
42

Min

Typ

25

32
17
16
16
16
25
31
27
29
22

+12SoC
Max

Min

Typ

Max

19
18

29
28
28
28
42
51
44
44

I Unit

(See Fig. 1 and 2)

f max
tpLH
Count·up
Carry
tpHL
tpLH
Count-down
Borrow
tpHL
tpLH
Q
Either Count
tpHL
tpLH
Q
Load
tpHL
-:'-'c
- -Q
Clear
tpHL
Te.st Conditions: C~'- SOpF, RL - 2k!l (S.8 Fig. 1and 2)

51
44
44
39

MHz
26
24
24
24
38
47
40
40
35

18
18
27
33
29
31
24

39

ns
ns
ns
ns
ns
MHz

tpLH
tPHL
tpLH
tpHL
tpLH
tpHL
tpLH
tPHL
tpHL

Count-up

Carry

Count-down

Borrow

Either Count

Q

Load

Q

Clear

Q

..

o

23
22
22
22
31

34
32
32
32
47

37
33
35
28

56
49
49
44

21
20
20
20
29
34
31
33
26

31
30
30
30
43
51
44
45
40

23
22
22

34

22
31

32
32
32
47

37
33
35
28

56
49
49
44

ns
ns
ns
ns
ns

0

Note: AC specification shown under -55 e and +125 e are for 9LS devices only.
All 50pF specifications are for 9LS only.

2-122

~YTHEOE)

Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter
PARAMETER

ME~~l,I~EMENT

LS192
LS193

INFORMATION

OUTPUTS

~
QD Dc DaQA

Vee

OATA
PULSE
GENERATOR

r-----------------,
I

IlI'£N

CARRY

fSMNotwtA)

I

OPEN

I
I
I

Rl

QA

CLEAR

PULSE
GENERATOR
1800 N... AI

I

(See Note C)

Da

I T-=-

Dc
00

LOAD
PULSE

-=-

I
I

1800 Note BI

I
-=- I
L _____ ..!-!!~~~~~'_ _____ J

LOAD

GENERATOR
ISoo N... AI

Cl

I
I

r-----:~;~~;~------~
L _____ ~=.!s~!:':~
J

':"

_____

1"'-------------------.
LOAD CIRCUIT 2

I

L _____'!'::.~~~c:.~I_____ :
r----------------~
LOAD CIRCUIT 4
I

L ____ ~'::.L!.ad.::i:u!.1!.. ____ ~

t,

CLEAR

-+! l-- -l I-

I
I I
iI Jf90%90%~t----------------------------1.3V

~

I

LOAD
INPUT

Q

I+- tf

1_0%...,.~"'\""!.;~~~%-----------9~10~.~!"'!i;V~~o:-

___

tpHL

I+-

I
____, I
OUTPUT

--.I

:
~~:UP---l~
---i-1----..9....0%"""!i.~
1.3~
90%

-+I

W

P

-+I ~ t,

---:io
l

3V

..
,_;,;l;,;;O,;,;%~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

I

DATA
INPUT

TEST CIRCUIT
tf

~10%

I

10%_

-..I

I4--tPLH

~ 1.3V

II4-

------------. ::

I.-- 's.tup
"

I'

~-!

lrio/~V

""=;-+--,-, - - ---

t,

-,

-,

;/I

·~9~O::::%-----

*-'PHL

14-

1.3V

I
.1. _____

~

3V
OV
VOH
VOL

VOLTAGE WAVEFORMS

NOTES:

A. The pulse generators have the following characteristics: Zout = 50n and for the data pulse generator PRR
50%; for the load pulse generator PRR is two times data PRR, duty cycle = 50%.
B. CL includes probe and jig capacitance.
C. Diodes ~re 1 N3064.
D. tr and tf " 7 ns.
FIGURE 1 -

~YTHE03l

< 500KHz, duty cycle =

CLEAR, SETUP, AND LOAD TIMES

2-123·

LS192

Synchronous BCD Decade Up/Down Counter

LS193

Synchronous 4-Bit Binary Up/Down Counter
PARAMETER MEASUREMENT INFORMATION (Continued)
OUTPIITS

,..----J'----..
Do "c "'0A

4V

CARR. _ROW

Ir--------------~
RL
I

01=.011
_ _ AI

I

_ROW
A

.,.

°A

11

D

"c

eU"R

Do

I

I
II TCL,... _ 0 1
I .".

CA"IIIY

I

,,,_CI

':"

I
•

I
IL _______________ ~I

I

!

LOAD CIRCUIT 1

..~-----::;:~;----,
____
____ l

LOAD

.:.s:.-.::."!~::~

r-----7o:O-c:;:,;]-----,
' - - - - - I.. ____ :=:.!;~:=,~ ___ .. J

,"'.

...------::.:co;;::;4------ 1
!.s.=; ~o: '!C:'~ ____ J

' - - - - - - IL _ ___

'--____-1r----------------,
LOAD C'RCUIT 5

•

L._.__ :=:!;.~~c:~

____ .J

lOAO CIRCUIT.
I
~----------------~

'--_ _ _ _ _; '

'-___ !.s.=:~;:='! __ __ J

TEST CIRCUIT

.I......I~I--.,
COUNT.
UP
"'
INPUT
(Soe Note 0)

1

J90%~Ll_lln~
~ ~~.;-., ~1.3V\.:!/
I
l' - - - -

'\.!../~~~ ~

8

9

'

I

I

I

r-- 'PLH

-+t

OUTPUT

I

--I

''!1

I+'PHL

I

f:!

k-'PLH

'PHL

COUNT
DOWN
INPUT
(Se. No.e D)
OUTPUT
QD
(See Not. E)

I

I

:! "E ~::

Qo
_ _ _ _ _ _ _ _ _ _ _..J
f1.3V
(S.e No.e E)

CARRY
OUTPUT

----------------------------------------------~~LFI
I
I

VOH
1.3V
- - - VOL

1.3V

'1

-+I ~ J.+.."

':'-2' - II ~~---3V
~
T - - - - ov
1

90%
10%

8

-

1.3V

9

15

1.3V

16

I

I

-1

I

r-'PHL

-----------~I
\

i

I

1.3V

I~

!--'PLH

,I

1.3V

71 1.3v

."""'-------~-~-r--

I

~

'PHL~
BORROW
OUTPUT

3V
OV

VOL TAGE WAVEFORMS

I

VOH
V
OL

r-'PLH
I

1.3V~

:::

NOTES:
A. The pulse generator has the following characteristics: PRR .. 1 MHz, Zout = 50n, duty cycle = 50%.
B. CL includes probe and jig capacitance.
C. Diodes are 1 N3064.
D. Count·up and count·down pulse shown is lor the LS193 binary counter. Count cycle for LS192 decade counter is 1 through 10.
E. Waveforms for outputs QA, QB, and QC are omitted to simplify the drawing.
F. tr and tl .. 7ns.

FIGURE 2-PROPAGATION DELAY TIMES

2·124

~YTHEO!1

Synchronous BCD Decade Up/Down Counter

LS192

Synchronous 4-Bit Binary Up/Down Counter

LS193

TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

LS192

Illustrated below is the following sequence:
1.
2.
3.
4.

Clear outputs to zero.
Load (preset) to BCD seven.
Count up to eight, nine, carry, zero, one, and two.
Count down to one, zero, borrow, nine, eight, and seven.

CLEAR

U

LOAD

r - - :I -I - - - . , , - - - - - - - - - - - - - - - - -

''-- _____ ----------I

r--:--..,.---,,- -

-

-

-

-

-- -

-

-

-- -

---

'-----------------I

~================
I

COUNT
UP
COUNT

_--,-__.,..'....IC
I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

======== ========

~l:: ==~r-:-'-.,-,~-----~
'--_____:---;-____
ac

I

I

I

QD= --,

I

I

I

I

I

I

"

I

I

CARRY

I

I

I

~

I
I

U

I

BORROW-~,~,-~,~,-~,--------~,-~,---,LJ

101

I

---'11

~

171

SEQUENCE
ILLUSTRATED ~ ~
CLEAR PRESET

9

~ COUNT0UP~2

I
I

9 8-?i

~ COUNT
0 DOWN

NOTES:
A. Clear overrides load, data, and count inputs.
B. When counting up, count·down input must be high; when counting
down, count·up input must be high.

~YTHE~

2-125

Syn8h~onous

BCD Decade Counter
Synchronous 4-Bit Binary Up/Down Counter

LS192
LS193

TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

LS193

Illustrated below is the following sequence:
1.
2.
3.
4.

Clear outputs to zero.
Load (preset) to binary thirteen.
Count up to fourteen, fifteen, carry, zero, one, and two.
Count down to one, zero, borrow, fifteen, fourteen, and
thirteen.

U

I 1
....--'-:----;,-----------------

I~ _ _ _ _ _ - - - - - - - - - - 1

~---------------­

--:--:--.:.....;'-----------------

c================
c================
1

1

1 1
I 1

I

OUTPUTS{::=

1

. . ;~- ;

- L• .

-'--'--'

Clc=~
1 1
1
QD

=

~r-c--'------:"'
1

1

1

1

CARRY
BORROW
SEQUENCE
ILLUSTRATED

1

101

Q

1

l13J

~<:T

---J

u

1 I
1 1
1

___-'---:-__

1

1

~4 COUNT
15 0
~2
UP

11

r-

u

"I

0
15 14
COUNT DOWN--,

NOTES:
A. Clear overrides load, data, and count inputs.
B. When counting up, count-down input must be high; when counting

down, count-up input must be high.

2-126

~YTHEO]J

4-Bit Universal Shift Register

LS194A
PIN-OUT DIAGRAM

DESCRIPTION
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register. The circuit contains 46 equivalent gates and
features parallel inputs, parallel outputs, right·shift and left·
shift inputs, operating·mode·control inputs, and a direct
over·riding clear line. The register has four distinct modes
of operation, namely:
Parallel (broadside) load
Shift right (in the direction C A toward CD)
Shift left (in the direction CD toward CA)
Inhibit clock (do nothing)

7[!J
CLR SHIFT ABC

0 SHIFT GNO

RIGHT~LEFT

SERIAL PARALLEL SERIAL
INPUT INPUTS
INPUT

Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs,
SO and S1, high. The data are loaded into the associated
f1ip·flops and appear at the outputs after the positive
transition of the clock input. During loading, serial data
flow is inhibited.

16
10

Shift right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and S1 is low.
Serial data for this mode is entered at the shift.right data
input. When SO is low and S1 is high, data shifts left
synchronously and new data is entered at the shift·left
serial input. Clocking of the flip·flop is inhibited when
both mode control inputs are low.

9

2

8

Die Size .067 x .082

FUNCTION TABLE

._-

INPUTS
CLEAR

~

CLOCK

SERIAL

OUTPUTS

PARALLEL

QB

Qc

Qo

X

L

-L

L

L

X

X

QAO

d

a

QBO
b

QCO QOO

e

X

X

X

H

QAn

QBn QCn

X

X

X

X

L

QAn

QBn

aCn

aDn

H

B

~

0

X

X

X

X

X

X

X

X

X

X

a

b

f

X

H

X

t

X

L

so

LEFT RIGHT

L

X

X

X

X

H

X

X

L

H

H

H

t

H

L

H

H

L

H

H = high level (steady state)

QA

A

Sl

e

H

H

L

f

H

X

X

X

X

X

aBn

aCn

H

H

L

f

L

X

X

X

X

X

aBn

aCn DOn

H

L

L

X

X

X

X

X

X

X

QAO

QBO

LOGIC DIAGRAM

QCO

d

L
QDO

L = low level (steady state)
X = irrelevant (any input, including transHions)
t = transition from low to high level
a, b, c. d = the level of steady'state input at inputs A, B, C,
or D. respectively.
eo, 2Q.. = the- level of A• B, e• or A.,
respectively, before the indicated steady-state input
conditions were established.
A" OBn. Oen. ODn = the level of OA' Oa. e• respectively.
before the most-recent t transition of the clock.

a.., a... a

a a a

a

a

PARALLE,L INPUTS

'A

131

B
141

C
151

D'

161

MODE {Sl 1101
CONTROL
_191
INPUTS
sO'={»-r---t--trn-,j-----1l-lhbn---t-it-tht----t-tht-,1
SHIFT

~~~~~ _1"'21'--_-,

Ilr-Ht--.p71 S~~~;L

SERIAL
INPUT

INPUT

CLOCKI~l~llC»----_+-r-+---~~~r---~_t~r_-~
CLEAR~lC»---_ _ _~~~--~~b..._--~~~._--~

\121
QD

,

PARALLEL OUTPUTS

[EAYTHEO]J

2·127

4-Bit Universal Shift Register

LS194A

TYPICAL TIMING SEQUENCES

CLOCK
C:~~~Lr~:~~'jl;J!:::::::::ij:======s;;;;;;;~
lS1::~ i
INPUTS

,.~~~~~i~______~~______~____~-+_
OATA ic~~!~------~~------~-------+,~:

INPUTS {:A::ti-Ln
OUTPUTS

.

aa:::L...LJ---Ls--,
Oc'.:~ , :
'----c-+----..I
ao::i;'
i i i--SHIFT RIGHT-i

CLEAR LOAO

,

r-+-----i

LEFT

i--SHIFT

Recommended Operating Conditions
Min
4.5

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Clock frequency, fclock
Width of clock or clear pulse, tw
Mode control
Serial and parallel data
Clear inactive-state

Setup time, t setup
Hold time at any input, thold
Operating free-air temperature, TA

9LS/54LS
Nom
Max
5

0
30
30
16
18
0
-55

5.5
-400
4
30

125

Min
4.75

9LS/74LS
Max
Nom
5

0
30
30
16
18
0
0

5.25
-400
8
30

70

Unit
V
JlA
mA
MHz
ns
ns
ns
ns
ns
°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter
VIH
VIL
VI
VOH
VOL
II
IIH
IlL
lost
lee tt

Min

9LS/54LS
Typ"

9LS/74LS
M@~

11--18mA
VIH-2V,
IOH=-400JlA
VIH=2V,

Typ**

0.7
-1.5
2.5
IloL=4mA
IIOL =8mA

!!e~

2

2
Vee=MIN,
Vee-MIN,
VIL =VILmax,
Vee=MIN,
VIL =VILmax
Vee=MAX,
Vee-MAX,
Vee-MAX,
Vee=MAX
Vee=MAX

Mh'!

3.5

0.8
-1.5
2.7

0.25

oAo

15

0.1
20
-0.4
-100
23

3.4
0.25
0.35

VI=7V
VI-2.7V
VI-O.4V
-15

-15
12

Unit
V
V
V
V

0.40
0.5
0.1
20
-0.4
-100
23

V
mA
JlA
mA
mA
mA

'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"All typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttWith all outputs open, inputs A through 0 grounded, and 4.5V applied to SO, 51, clear, and the serial inputs, lee is tested with a momentary
GND, then 4.5V, applied to clock.

2-128

r§YTHEO]J

4-Bit Universal Shift Register

LS194A

Switching CharacteristiCS, Vee =5V Over Recommended Free-Air Temperature Range
-sS"C

Parameter

Min

Test Conditions: C L

=

Typ

=

1SpF, RL

Max

I
I

30
27
14
18

tpLH

tpHL
_Test Conditions: CL - 50pF, RL

=

tpLH
tpHL

Min

Max

40
24
11
15

34
22
26

Unit

Typ

Mex

27
14
18

34
22
26

ns
ns
ns

31
18
22

39
27
31

ns
ns

MHz

30
18
22

2kll (~Fi_g. below) . _..

".

--

_.-

28
15
19

39
27
31

31
18
22

tpHL

I

Typ

2kO (See Fig. below)

f max
tpHL

+12SOC

+2S"C
Min

36
23
27

ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9 LS onlv.

PARAMETER MEASUREMENT INFORMATION
TEST TABLE FOR SYNCHRONOUS INPUTS

OUTPUT

DATA INPUT
FOR TEST

S1

SO

OUTPUT TESTED
(SEE NOTE EI

FROM

A

4.5V

4.5V

OUTPUT--~~t-e-~-I'-~,

B

4.5V

Os at tn+1

UNDER
TEST

C

4.5V
4.5 V

4.5V

Oc attn +1

LOAD FOR OUTPUT UNDER TEST

___""""\ I·
CLEAR

'I

0

4.5V

4.5V

L Serial Input

4.5V

OV

QA at tn+4

R Serial Input

OV

4.5V

00 at tn+4

at tn+1

3V

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV

:

~1setup

I

tn

I

tn+1

r-

tn+1

(See Note F)

tn

P

~.
I
---3V

CLOCK

1.3V
~

' - _ _ _ _J

OUTPUTQ

QO

tw(clear)

1.3VU~=-,,
1

DATA
INPUT
(SEE TEST
TABLE)

QA at tn+1

tttoid

tUPI-I

~
_~~
I

1.3V

I

1
1

OV
3V

_ _ _ OV

1

1
~
I

~tpHL

I

-----~~~_1._3V____________

_J

V·;'---

VOLTAGE WAVEFORMS
NOTES:
A. The clock pulse generator has the following characteristics: Zout '" 50n and PRR .. 1 MHz, tr .. 15 ns and tf .. 6 ns.
When testing f max , vary PRR.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064 or 1 N916.
D. A clear pulse is applied prior to each test.
E. Proplagation delay times (tPLH and tPH L) are measured at t n+l. Proper shifting of data is verified at tn+4 with a functional test.
F. tn = bit time bef~re clocking transition.
tn+1 = bit time after one clocking transition.
tn+4 = bit time ~fter four clocking transiti.o.ns.

~YTHE03'l

2-129

4-Bit Parallel-Access Shift RegIster

LS195A
DESCRIPTION

PIN-OUT DIAGRAM

This 4-bit register features parallel inputs, parallel outputs,
J-K serial inputs, shift/load control input, and a direct overriding clear_ All inputs,are buffered to lower the input drive
requirements. The register has two modes of operation:
Parallel (broadside) load
Shift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits
of data and taking the shift/load control input low. The
data is loaded into the associated flip-flop and appears at
the outputs after the positive transition of the clock input.
During loading, serial data flow is inhibited.

7[[]
CLEARJ

K ABC

DGND

'-v-'~

SERIAL INPUTS PARALLEL
INPUTS

Shifting is accomplished synchronously when the shift/load
contro.!. input is high, Serial data for this mode is entered at
the J-K irputs. These inputs permit the first stage to perform as J-K, D-, or T-type flip-flop as shown in the function
table,

15

14

13

12
11

16

10

FUNCTION TABLE
INPUTS
CLEAR

l

SHIFTI
LOAD

X

CLOCK
X

H

L

,

H

H

L

OUTPUTS

SERIAL

PARALLEL

J

K

A

a c

0

°A

Oa

DC

DO

aD

X

X

X

X

X

)(

L

L

L

L

H

d

X

X

,

b

c

X

X

X

X

X

,

L

H

X

X

X

L

L

X

X

X

H

,
,
,

d
d
b
c
X ElAO 0ao Qeo aDO aDO
X OAO CAD aS n Not more than one output should be shorted at a time and duration of·the short-circuit should not exceed one second.

2-140

~YTHE~

Dual Monostable Multivibrator with
Schmitt-Trigger Inputs

LS221

Switching Characteristics Vee = 5.0V Over Recommended Free-Air Temperature Range.
Parameter
Test Conditions:
TW(out)
Test Conditions:
TW(out)
Test Conditions:
TW(out)
Test Conditions:
TW(out)
Test Conditions:

From

To

(Input)

(Output)

-SS"C
Min.

Typ.

+2S"C
Max.

Min.

Typ.

+12S"C
Max.

Min.

Typ.

Unit
Max.

R, = 2.0k, C, = 15pF, Ce" = 8OpF, R", = 2.0kO (See Fig. 1 on 2-139)
QorQ

A Dr B

77

138

70

17S

77

138

175

ns

22

50

80

ns

620

750

870

ns

6.0

7.7

8.S

ms

150

120

R, = 2.0k, C, = 15pF, Ce" = 0, R", = 2.0kO (See Fig. 1 on page 2-139)
QorQ

Aor B

22

20

80

50

47

70

R, = 2.0k, C, = 15pF, C", = l00pF, R", = 10kO (See Fig. 1 on page 2-139)
QorQ

Aor B

600

725

600

870

670

750

R, = 2.0k, C, = 15pF, C", = lpF, R", = 10kO (See Fig. 1 on page 2-139)
A or B

QorQ

6.0

7.7

8.S

6.0

6.7

7.5

R, = 2.0k, C, = 15pF, C", = 80pF, R", = 2.0kO (See Fig. 1 on page 2-139)
A

Q

48

74

45

70

48

74

B

Q

38

59

35

55

38

S9

A

Q

53

84

50

80

53

84

B

Q

43

69

40

65

43

69

tpHL

Clear

Q

38

59

35

55

38

59

ns

tpLH

Clear

Q

47

69

44

65

47

69

ns

tpLH

tpHL

ns

ns

Note: AC specification shown under -55°C and +125°C are for 9LS devices only. All 50pF specifications are for 9LS devices only.

PARAMETER MEASUREMENT INFORMATION

~-----------------3V

- - - - - - - - - - - OV
- - - - - - - - - - - 3V
- - - - - - OV
~-----+--\+_-------- VOH

Q OUTPUT
~

_____

' - - - - - - - - - - - - VOL
tPLH
Ir----------- VOH
1.3V
_ _ _ _ _ _ _ _ VOL

J~

tPHL
B input is high
TRIGGER FROM A. THEN CLEAR

/r---------

3V

~.------~.•- - - - - - - - - - -

OV

A INPUT \

Q

OUTPUT

t=---

---~ ~ 1.3

a OUTPUT

t:1.3

_ _ _.j
tw(out)

VOH
VOL

tw(out)~~v

f1.3

OH
VOL

B and clear inputs are high

TRIGGER FROM A

~YTHE03J

2-141

.

Dual Monostable Multivibrator
with
'
Schmitt-Trigger Inputs

LS221

PARAMETER MEASUREMENT INFORMATION

BINPUT

--e

W(in)

--I
~~1_.3________________________

1GI

b

"60ns~

3V
OV
3V

~V

- - - - - - - - - - - - - - - - - - - OV
.tPHL_~LH
VOH

CLEAR

VOL
VOH
VOL
TRIGGER FROM B, THEN CLEAR-CONDITION 1
3V

j:1:3V

B INPUT

---J

I-.- ..60 ns :=:j

CLEAR - - - - - - - - - - -

,

\'-___________ OV

~===================

3V
OV
VOH

oJ/

\'--------

Q OUTPUT _ _ _
A input is low

VOL

TRIGGER FROM B, THEN CLEAR-CONDITION 2
3V

BINPUT~. "50nsB"u~rup~
CLEAR

OV

-------------------

1~

3V

1~

OV
TRIGGERED
----,

~OH

"NO""T"""T"'RIf>G"'G"'E"'~)"ED.,.-------------------f1

Q

OUTPUT

A

input~! low

VOL

CLEAR OVERRIDING B. THEN TRIGGER FROM B

11~'3 .. 50 m ~_1_.3___________

B INPUT

---..1-.. 50 ns:.j
~3

CLEAR

~_1_.3_____________________

3V
OV

3V
OV

Q

OUTPUT __________________- ' /

A input is low

TRIGGERING FROM POSITIVE TRANSITION OF CLEAR

"-

VOH
VOL

NOTES: A. Input pulses are supplied by generators havingthe following characteristics: PRR .. 1 MHz, Zout "' 50.11; tr .. 15 os, tf .. 6 ns.

2·142

~YTHEOEJ

8-Line-To-1-Line Multiplexer
With Three-State Outputs

LS251
PIN-OUT DIAGRAM

FEATURES
•
•
•

Selects one of eight data sources
Performs parallel-to-serial conversion
Complementary 3-state outputs

DATA INPUTS DATA SELECT
~

DESCRIPTION

VCC 4

2 1 16 15

This monolithic data selector/multiplexer contains full
on-chip binary decoding to select one-of-eight data sources
and features a strobe-controlled three-state output. The
strobe must be at a low logic level to enable this device.
The three-state outputs permit a number of outputs to be
connected to a common bus. When the strobe input is high,
both outputs are in a high-impedance state in which both
the upper and lower transistors of each totem-pole output
are off, and the output neither drives nor loads the bus
significantly. When the strobe is low, the outputs are
activated and operate as standard TTL totem-pole outputs.

6

,.----A--.,

ABC

7

[i]][i]][ill[illimilll[iQ]

! ....F-~~".51i

14

5

12

6

11

7 . . ._

5

13

.......
8 9 10

ITJ[}]QJ[I][]J[I][IJm

3 l l O Y W :::l GND
'--v----' '---v---' '"
DATA INPUTS OUTPUTS

Die Size .056 x .057

:=
'"

To minimize the possibility that two outputs will attempt
to take a common bus to opposite logic levels, the output
control circuitry is designed so that the average output
disable time is shorter than the average output enable time.

Recommended Operating Conditions
9LS/74LS

9LS/54LS

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
-1
8
125

4.75

5

5.25
-2.6
8
70

-55

0

Unit

V
mA
mA

°c

LOGIC DIAGRAM

~;~~:CE) -'(.:...7)'--_ _... ;~_ _ _ _ _~------._-~
00 (4)

01 (3)

FUNCTION TABLE
02 (2)
03 (1)
OAT A
INPUTS

04 (15)
05 (14)
06.(13)
07 (12)

~:::CT {:::::
(BINARY)

~YTHE031

OUTPUTS

INPUTS
STROBE

SELECT

H
X

BB

~

~

~O,

y

w

C
X

B

A

S

x

X

H

Z

Z

L

L

L

L

DO

Do

L

L

H

L

Dl

Dl

L

H

L

L

D2

52

L

H

H

L

D3

H

L

L

L

D4

OJ
54

-

-

H

L

H

L

D5

D5

H

H

L

L

D6

06

H

H

H

L

D7

07

high logic level, L ~ low logic level
irrelevant, Z ~ high impedance (off)
01. . 07 ~ the level of the respective 0 input

II

c~_ _ _C_~

2-143

8-Line-To-1-Line Multiplexer
.With 'Three-State Outputs

LS251

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)

VIH
VIL
VI
VOH
VOL
10 (off)
II
IIH
IlL
iost
lee tt

9LS/54LS

Te.t Conditions·

Parameter

Min

Typ··

9LS/74LS

Max

Vee=MAX

11=-lSmA
VIH-2V,
10H=MAX
VIH-2V,

Typ··

0.7
-1.5
2.4
IOL=4mA
10L -SmA
Vo=2.7V
Vo=O.4V

3.4
0.4

6.1
7.1

20
-20
0.1
20
-0.4
-100
10
12

-15
Condition B

O.S
-1.5
2.7

0.25

VI=7V
VI-2.7V
VI-O.4V

I Condition A

Max

2

2
Vee=MIN,
Vee-MIN,
VIL=MAX,
Vee=MIN,
VIL =MAX,
Vee=MAX,
VIH=2V
Vee=MAX,
Vee-MAX,
Vee=MAX,
Vee=MAX

Min

3.4
0.25
0.35

-15
6.1
7.1

Unit

V
V
V
V

0.4
0.5
20
-20
0.1
20
-0.4
-100
10
12

V
fJ.A
mA
fJ.A
mA
mA
mA

·For conditions shown as MIN or MAX, use the appropriate value specified under recommendea operating conditions for the applicable
device type.
--All typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttlee is measured with the outputs open and all data and select inputs at 4.5V under the following conditions:
A. Strobe grounded.
B. Strobe at 4.5V

2-144

~YTHEcaJ

8;.Line-To-1-Line Multiplexer
With Three-State Outputs

LS251

Switching Characteristics , V'cc- 5V Over Recommended Free-Air Temperature Range
Parameter
Test Condhlons: CL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tZH
tZL
tZH
tZL
Test Conditions: CL
tHZ
tLZ
tHZ
tLZ
Test Condhlons: CL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tZH
tZL
tZH
tZL

From
(Input)

= 15pF, RL

-55°C
Min
Typ
= 2kO (See Fig. A, page 2-174)
To
(output)

Max

Min

+25°C
Typ

Max

Min

+125°C
Typ

Max

23
21
16
16
11
12
9
5
8
12
11
12
page 2·174)

32
29
24
25
17
17
16
10
13
18
17
19

23
20
17
15
11
11
10
5
8
11
14
12

34
28
25
24
20
16
17
10
14
18
21
18

27
24
21
17
18
14
13
5
10
15
11
13

42
34
30
26
26
20
19
10
16
22
17
19

10
7
13
Strobe
W
7
= SOpF, RL = 2kO (See Fig. A, page 2-174)
A, B, or C
25
y
(4 levels)
27
A, B, or C
17
W
(3 levels)
19

15
11
18
11

8
6
11
6

13
11
16
10

7
8
10
7

12
13
15
14

34
35
25
27
20
23

26
25
18
18
14
16
11
6
11
17
17
16

37
32
26
27
22
21
18
12
17
23
23
22

33
28
22
20
20
19
14
6
13
20
15
17

44
37
31
29
28
25
21
12
19
27
21
23

A,
(4
A,
(3

B, or C
levels)
B, or C
levels)

y

W

Any D

y

Any 0

W

Strobe

y

Strobe

W

= 5pF,

RL

Strobe

= 2kO

(See

Fig. C on

y

Any D

y

Any D

W

Strobe

y

Strobe

W

13
18
10
7
11
18
13
14

17
13
16
24
19
21

Unit

ns
ns
ns
ns
ns
ns

ns
ns

ns
ns
ns
ns
ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only.
All 50pF specifications are for 9LS only.

tEVTHEO]J

2·145

Dual 4-Line-To-1-Line Multiplexer
With Thre.State Outputs

LS253
FEATURES
•
•
•
•

PIN-OUT DIAGRAM

Three-state version of LS153
Non-inverting
Permits multiplexing from N lines to 1 line
Performs parallel-to-serial conversion

DESCRIPTION
The LS253 is a high-speed dual 4-line-to-1-line multiplexer
with common select inputs and separate output control
inputs for each half. Each half can select one bit of four
and present it at the output in non-inverted form.
The three-state outputs can interface with and drive data
lines of bus-organized systems. With all but one of the
common outputs disabled (at a high-impedance state)
the low-impedance of the single enabled output will drive
the bus line to a high or low logic level.

'"13

OATA INPUTS

co

Cl

C2

X
X
X

X
X
X
X
X

X

X

X

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
X
X
X
X
X
X

L
H
X
X
X
X

11

10

14

FUNCTION TABLE
SELECT
INPUTS
e A

12

X
X
X

H
L
L

x

L

L
H

X
X
X

X
X

L
H

L
L
L
L
L

9

15

OUTPUT
CONTROl OUTPUT
C3
G
V

8
16

Z

L
H
L
H
L
H
L
H

Address inputs A and B are common to both sections.
H = high level. L = low level, X = irrelevant, Z = high impedance (off)

2
3

4

5

6

7

Die Size .057 x .061

LOGIC DIAGRAM
OUTPUT

I

CONTROL~__------~----,
lG

Gcol-'-16:..;..)-------JDlI
'C1 (5 )

---R::f:*:t1-J

DATA 1 { lC2'-'
(("4~)

lC3~(3!L)--.t$$~..J
B (2)

SELECT{A(14 )

DATA 2

~2;:.:,:.:. .o:. .:.: - - -+ -t:±: : r- -,
2C2:...:..::;'-------1==I==Et:f'l

2V

2C3':..::.'3.:..:)____-t:±=::±::r---,
OUTPUT 11-'5)~.:>_---_-----'
CONTROL

2G

2-146

tEYTHEO~

Dual 4-Line-To-1-Line Multiplexer
With Three-State Outputs

LS253

Recommended Operating Conditions
Min
Supply voltage, Vee
High·level output current, IOH
Low-level output current, IOL
Operating free·air temperature, TA

9LS/54LS
Nom
Max

4.5

5

Min

5.5
-1
4
125

-55

9LS/74LS
Nom
Max

4.75

5

0

5.25
-2.6
8
70

Unit
V
mA
mA
°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

Min

9LS/54LS
Typ"
Max

Min
2

2

VIH
VIL
VI

II
IIH
IlL
lost

Vee=MIN,
Vee-MIN,
VIL =VILmax,
Vee-MIN,
VIL =VILmax
Vee ~IVIAX,
VIH=2V
Vee-MAX,
Vee-MAX,
Vee=MAX,
Vee-MAX

lectt

Vce=MAX

VOH
VOL
IOloff)

0.7
-1.5

11=-18mA
VIH-2V,
IOH=MAX
VIW2V,

2.4

0.8
-1.5

3.4

2.4

0.25

IOL -4mA
IOL -8mA
Vo ~2.7V
Vo-OAV

0.25
0.35

20
-20
0.1
20
-0.4
-100
12
14

-15
Condition A
Condition B

..
use the appropriate value specified

7
8.5

-15
7
8.5

Unit
V
V
V
V

3.1

0.40

VI-7V
VI-2.7V
VI=0.4V

*For conditions shown as MIN or MAX,

9LS/74LS
Typ"
Max

0.40
0.50
20
-20
0.1
20
-0.4
-100
12
14

V
/lA
mA
/lA
mA
mA
mA

under recommended operating conditions for the applicable

device type.
"AII typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
ttlee is measured with the outputs open under the following conditions:
A. All inputs grounded.
B. Output control at 4.5V, all inputs grounded.

Switching Characteristics , V'cc -- 5V Over Recommended Free-Air Temperature Range
From
(input)

Parameter

Test Conditions: CL = 15pF,
tpLH
tpHL
tPLH

-

-55°C
Typ

Max

+25°C
Typ

Min

Min

Max

-

Output
9
tHZ
y
tLZ
13
I Control
Test Conditions: CL = 50pF, RL = :2kn (See Fig. A, page 2-174)

7
12
18
18
10
13

15
22
30
31
21
23

9
14
20
Y
20
12
y
15
2kO (See Fig. C on page 2·174)

Y

Select
Output
Control
5pF, RL

Min

+125°C
Typ

I

16
22

I

7
12

12
17
25
27
16
18

I

15
19

I

16
20
13
10
21
27
15
18
29
35
21
24
Select
Y
29
36
21
24
Output
20
26
16
13
Y
Control
21
28
16
19
Note: AC specification shown under _55°C and +1250 e are for 9LS devices only. All 50pF specifications are for
tPLH
tpHL
tpLH
tpHL
tZH
tZL

--

r§YTHE~

Data

Max

Unit

= 2kn (See Fig. A, page 2-174)

Data

~tZH
tZL
Test Conditions: CL

RL

To
(output)

y

9
14
20
20
12
15

15
22
30
31
21
23

ns

9
13

16
22

ns

13
18
24
24
16
19

20
27
35
36
26
28

ns
ns

ns
ns
ns

9LS only.

2,,147

Dual 2-Line-To-4-Line Decoder/Demultiplexer
With Three-State Outputs

LS255

PIN-OUT DIAGRAM

FEATURES
•
Three-state version of LS155
•
Applications:
Dual 2-Line-to-4-Line Decoder
Dual 1-Line-to-4-Line Demultiplexer
3-Line-to-8-Line Decoder
1-Line-to-8-Line Demultiplexer
DESCRIPTION
The LS255 features dual 1-line-to-4-line demultiplexers
with individual strobes and common binary-address inputs
in a single 16-pin package_ When both sections are enabled
by the output controls, the common binary-address inputs
sequentially select and route associated input data to the
appropriate output of each section. The individual controls
permit activating or inhibiting each of the 4-bit sections as
desired. Data applied to input 1C is inverted at its outputs
and data applied at 2C is not inverted through its outputs.
The inverter following the , C data input permits use as
a 3-to-B-line decoder or '-to-B-line demultiplexer without
external gating. Input clamping diodes are provided on all
of these circuits to minimize transmission-line effects and
simplify system design.

234567[]]
lC lG B ,V3 lY2}YllvqGND
DATA
SELECT OUTPUTS
IM'UT

I

OUlPUT
CONTROL

15
16

FUNCTION TABLE
3-LlNE-T0-8-LlNE DECODER
OR l-LiNE-TO-8-LINE DEMULTIPLEXER
OUTPUTS

INPUTS
SELECT CONTRO

•

A

10

X

2

DATA
1VO

1C

1V1

1V2

1V3

H

X

z

z

z

z

L

L

H

H

H

H

L

H

H

H

L
L

L
H

H

H
L

H

H

H

L

H

H

H

L

H

H

H

H

L

X

X

X

L

H

H

H

H

2VO

2V1

X
L
L

I

Die Size .063 x .069

OUTPUTS

INPUTS

SELECT ICONTRoll DATA

OUTPUT

•

A

20

2C

X

X

H

X

z

z

z

z

L

L

L

L

L

H

H

H

L

H

L

L

H

H

L

L

L
L

H

H

H

H

L

H

L
H

H

H

H

H

H

H

L
H

H

H

L

X

X

X

2V2

2V3

CONT~~L -"(2,,,1_ _- ,
DATA
1C

SELECT
B

FUNCTION TABLES
2-LlNE-T0-4-LINE DECODER
OR 1-LlNE-TO-4-LINE DEMULTIPLEXER
OUTPUTS

INPUTS

CONTROL 10)

SELECT

ct
X

•

OR DATA

A

G~

11)

X

X

H

L

L

L
L

L
H

H

L
L

H

H
L

H
L

L
L

H

L

H

L

H

L
L

H

H

H

H

H

L

H

H

H

H

L
L

H

H

H

121

131

141

151

16)

171

2YO 2V, 2V2 2V3 1YO lV, lV2 1V3
z
z
z
z
z
z
z
z

L

L

LOGIC DIAGRAM

L

H

A

H
H

H

H

H

H

H

H

H

H
H

H
H

L

H

H

H

H

H

L

H

H

H

~~~~~~L_(:..:.14-")_ __'

H
H

H

L
H

H

H

2G

H

L

H

H

H

H

H

L

H

H

L
H

H
L

H

H

H

H

~

H

H

H
H

H

DATA 1151

2C -'-""----,

2V3

tC = inputs 1C and 2C connacted 10gether
*G = inputs 1G and 2G connacted 10gether
H = high level, L = low level, X = irrelevant, Z = high impedance (off)

2-14B

~YTHEO!)

Dual 2-Line-To-4-Line Decoder/Demultiplexer
With Three-State Outputs

LS255

Recommended Operating Conditions
Min

9LS/54LS
Nom
Max

4.5

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA

5

-55

5.5
-1
4
125

Min
4.75

9LS174LS
Max
Nom
5

0

5.25
-2.6
8
70

Unit
V
mA
mA
°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions·

Parameter
VIH
VIL
VI
VOH

Min

9LS/54LS
Typ·· Max

9LS174LS
Typ·· Max

2

2
Vee-MIN,
Vee=MIN,
VIL ;VILmax,
Vee-MIN,
V IL =VILmax
Vee=MAX,
Vlw 2V
Vec-MAX,
Vcc-MAX,
Vcc=MAX,
Vcc-MAX

Min

0.7
-1.5

11--18mA
VIH-2V,
IOH=MAX
VIH-2V,

2.4

3.4
0.25

IOL -4mA
IOL -8mA

0.8
-1.5
2.7

0.4

3.4

Unit
V
V
V
V

0.4
V
0.5
Vo~2.7V
20
20
pA
IOloff)
-20
-20
Vo-O.4V
mA
0.1
0.1
VI-7V
II
20
20
pA
VI-2.7V
IIH
-0.4
-0.4
mA
VI=O.4V
IlL
-100
-15
-100
mA
-15
lost
Condition A
10
6
10
6
mA
tt
Icc
VeC MAX
Condition B
11
11
17
17
"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device tvpe.
"AII typical values are at Vee = 5V, T A = 25°C.
tNot more than one output should be shorted at a time.
ttlee is measured with the outputs open under the following conditions:
A. A, B, and 1C inputs at 4.5V, and 2C, 1G, and 2G inputs grounded.
B. Same as Condition A except inputs 1G and 2G at 4.5V.
VOL

0.25
0.35

Switching Characteristics , V'cc -- 5V Over Recommended Free-Air Temperature Range
Parameter

From
(input)

To
(output)

Min

-55°C
Typ

Max

+25°C
Typ

Min

Max

Min

+125°C
Typ

Max

Unit

Test Conditions: C, = 15pF, R, = 2kO (See Fig. A, page 2-174)
A,B,lC
15
y
or2C
18
18
A or B
y
(3 levels)
22
Output
12
y
Control
14
SpF, RL = 2kll ISe. Fig. C on page 2-174)
Output
11
tHZ
y
tLZ
17
I Control
Test Conditions: C, = 5OpF, R, = 2kO (See Fig. A, page 2-174)

21
24
24
29
18
20

tpLH
tpHL
tpLH
tpHL
tZH
tZL
Test Conditions: CL -

A, B,lC
tpLH
Y
or 2C
tpHL
Aor
B
tpLH
y
(3 levels)
tpHL
Output
tZH
y
Control
tZL
Note: AC specification shown under _55°C and +125 ° C are for
All 50pF specifications are for 9LS only.

~-R"'A-YT-H-EO"'~-

19
22
22
26
16
18

I

18
23

I

27
30
30
34
22
26

I

13
16
16
20
10
12

18
22
22
26
15
18

15
18
18
22
12
14

21
24
24
29
18
20

9
15

15
20

11
17

18
23

16
20
20
24
14
16

22
28
28
32
20
22

19
22
22
26
16
18

27
30
30
34
22
26

ns
ns
ns

ns

ns
ns
ns

9LS devices only.
2-149

LS257

Quadruple 2-Line-To-1-Line
Multiplexers With Three-State Outputs

LS258

DESCRIPTION
These data selectors/multiplexers select a 4·bit word from
one of two sources and present it at the four outputs.
The LS257 presents true data; the LS258 presents inverted
data. With Output Control HIGH, the outputs are forced
to a high impedance state.

--

FUNCTION TABLE
INPUTS
OUTPUT
CONTROL

H

= high'

SELECT

OUTPUT"
A

B

LS257

LS258

H

X

X

X

Z

Z

L

L

L

X

L

H

L

L

H

X

H

L

L

H

X

L

L

H

L

H

X

H

H

L

level, L :: low level, X

= irrelevant,

Z -= high impedance (offl

Low level at S selects A inputs.
High level at S selects B inputs.

PIN-OUT DIAGRAMS

LS257

LS258

5 ~ INPUTS

5!i;;

~... z~ INPUTSOUTPUTINPUTSOUTPUT

INPUTS
OUTPUT
OUTPUT

vcco8~ 4Y ~ 3Y

[ill

15 14 13 12 11 10

vcc68~4V~ 3V

[ill

9

7m

15 14 13 12 11

SELECT IA 18 IV 2A 28 2V GND
'--v-tiUTPU-r---v--'OUTPUT
INPUTS
INPUTS
14

13 12 11

10

g

16

8

9
16

8

7

7

Die Size .047 x .066

2·150

9

7m

SELECT IA 18 IV 2A 28 2Y GND
'--v-tiUTPU-r---v--'OUTPUT
INPUTS
INPUTS

15

10

Die Size .047 x .066

~YTHEO::J

Quadruple 2-Line-To-1-Line
Multiplexers With Three-State Outputs

LS257

LS258

LOGIC DIAGRAMS

LS258

LS257

1B

1B

2A

2A

2B

2B
3A

3A
3B

3Y

4A
4B

4B

SELECT

SELECT

Recommended Operating Conditions
Min

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA

~YTHEO]J

4.5

-55

9LS/54LS
Nom
Max

5

5.5
-1
4
125

9LS174LS

Min

Nom

Max

4.75

5

5.25
-2.6

0

Unit

8

V
mA
mA

70

°C

2-151

Quadruple 2-Line-To.. 1-Line
LS257

Multiplexers With Three-State Outputs

LS258

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted
Teat Conditions'

Parameter

Vee-MIN,
Vcc=MIN,
VII =V~Lmax,
Vee=MIN,
VIL =VILmax
Vee=MAX,
Vo=2.4V

VOH
VOL
IOZH

Vee=MAX,
Vo=O.4V

IOZL

IIH
IlL

S input
Any other
S input
Any other
S input
Any other

2.4

All outputs
high
All outputs
low
All outputs
off
All outputs
high
All outputs
low
All outputs
_u

3.4
0.25

IOL =4mA

0.8
-1.5
2.4

0.4

VIH=2V,

VI=7V

Vee=MAX,

VI=2.7V

Vee=MAX,

VI=O.4V
-15

LS257

3.1
0.25
0.35

Unit
V
V
V
V

0.4
0.5

V

20

20

p.A

-20

-20

p.A

0.2
0.1
40
20
-0.8
-0.4
-100

0.2
0.1
40
20
-0.8
-0.4
-100

IIOL -8mA
VIH-2V

Vee=MAX,

9LS/74LS
Typ"
Max

2

11--18mA
VIH-2V,
IOH=MAX
VIH=2V,

Min

0.7
-1.5

Vee=MAX

lost

,Iee tt

9LS/54LS
Typ"
Max

2

VIH
VIL
VI

II

Min

-15

5.9

10

5.9

10

9.2

16

9.2

16

10

17

10

17

4.1

7

4.1

7

6.2

11

6.2

11

7.0

12

7.0

12

Vee=MAX

rnA
p.A
rnA
rnA

rnA

LS258

'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttlec is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.

2-152

~YTHEO~

Quadruple 2-Line-To-1-Line
Multiplexers With Three-State Outputs

LS257

LS258

-

Switching Characteristics , V'cc- 5V Over Recommended Free Air Temperature Range
Parameter

From
(Input)

Test Conditions: CL = 15pF, RL

= 2k!1

Data

Any

~ LS258
tpHl

Data

Any

LS257

Select

Any

LS258

Select

Any

LS257
~
tZl

Output
Control
Output
Control

tpHL

~
tpHL
tZH

tzt-

LS258

Test Conditions: C L

~
tLZ

LS257

~ LS258
tLZ

= lSpF,

RL

Any

Any

LS258
~
tpHL

Data

Any

LS257

Select

Any

LS258
~
tpHL

Select

Any

~ LS257

Output
Control
Output
Control

LS258

Min

+125°C
Typ

Max

·12
12
14
12
18
18
18
18
18
16
18
18

8
9
10
7
14
14
14
12
12
12
12
13

15
15
17
15
21
21
21
21
21
19
21
21

10
10
.9
8

15
18
15
15

12
12
11
10

18
21
18
18

10
11
12
9
16
16
16
14
14
14
14
15

17
17
19
17
23
23
23
23
23
21
23
23

12
13
14
11
18
18
18
16
16
16
16
17

19
20
22
19
25
25
25
25
25
24
25
25

Typ

Max

15
15
17
15
21
21
21
21
21
19
:l1
21

6
7
8
5
12
12
12
10
10
10
10
11

18
21
18
18
19
20
22
19
25
25
25
25
25
24
25
25

Min

Unit

ns
ns
ns
ns
ns
ns

ns
ns

= 2k!1 (See Fig. A, page 2-174)

Any

~
tZL

12
12
11
10

Any

Data

tZL

+25°C
Max

= 2k!1 (See Fig. A, page 2~174)

LS257

~
tpHL

Typ

8
9
10
7
14
14
14
12
12
12
1:l
13

Any

Output
Control
Output
Control

Test Conditions: CL = 5OpF,

~
tpHl

RL

Min

(See Fig. C on page 2·174)

~ LS257
tPHL

~

-55°C

To
(output)

12
13
14
11
18
18
18
16
16
16
16
17

Any
Any
o

ns
ns
ns
ns
ns
ns

0

Note: AC specification shown under -55 C and +125 C are for 9LS devices only.
All 50pF specifications are for 9LS only.

~YTHEO],'l

2·153

LS261

2-Bit By4-Bit Parallel Binary Multipliers
PIN-OUT DIAGRAM

FEATURES
•
•
•
•
•
•

Fast Multiplication ••• 5-Bit Product in 26ns Typ
Power Dissipation ... 110mW Typical
Latch Outputs for Synchronous Operation
Expandable for m-Bit·by-n·Bit Applications
Fully Compatible with Most TTL and Other Saturated
Low·Level Logic Families
Diode·Clamped Inputs Simplify System Design

DESCRIPTION
These low-power Schottky circuits are designed to be
used in parallel multiplication applications. They perform
binary multiplication in two's-complement form, two bits
at a time.
TheM inputs are for the multiplier bits and the B inputs
are for the multiplicand. The Q outputs represent the
partial product as a recoded base-4 number. This recoding
effectively reduces the Wallace-tree hardware requirements
by a factor of two_
The outputs represent partial products in one's complement
form generated as a result of multiplication_ A simple
rounding scheme using two additional gates is needed for
each partial product to generate two's complement.
The leading (most-significant) bit of the product is inverted for ease in extending the sign to square (left justify)
the partial-product bits.
The 9LS/54L261 is characterized for operation over the
full military temperature range of -55°C to 125°C; the
9LS/74LS261 for operation from O°C to 70°C.

LS261

13

11

12

10

14

15
16
1

4567[!]
04 IIJ 02 GNO

M:z

4

'--v--'

LATCH
CONTROL G OUTPUTS

~l1:!U2

Die Size _086 x .071

FUNCTION TABLE
INPUTS
LATCH

OUTPUTS

MULTIPLIER

CONTROL

G

M2

M1

MO

Q4

a3

a2

a1

ao

L

X

X

X

L

L

L

a20
L

a10
L

aoo

L

a40
H

a3 0

H
H

L

L

H

84

B4

B3

B2

B1

L

H

L

H

L

84

B4

B3

B2

B1

H

L

H

H

84

B3

B2

B1

BO

H

H

L

L

B4

83

82

81

80

H

H

L

H

B4

84

ih

82

81

H

H

H

L

B4

84

83

82

81

H

H

H

H

H

L

L

L

L

H = high level, L = low level, X = irrelevant
U40 ... UOO
84 ... 80

2-154

=

= The

logic level of the same output before the high-tolow transition of G.
The logic level of the indicated multiplicand (8) input

t;YTHEO~

2-Bit By 4-Bit Parallel Binary Multipliers

LS261

LOGIC DIAGRAM

~YTHE@J

2-155

2-Bit By 4-Bit Parallel Binary Multipliers

LS261
Recommended Operating Conditions

Min

Supply voltage, Vee
High·level output current, IOH
Low-level output current, IOL
Width of enable pulse, tw

4.5

Any
Any
Any
Any

Setup time, t setup
Hold time, thold

Minput
B input
M input
B input

Operating free-air temperature, TA

9LS/S4LS
Nom
Max

5

25
17'/'
15./.
O./.
Ot
-55

5.5
-1
4

125

Min

4.75

9LS174LS
Nom
Max

5

25
lU
15./.
O./.
O./.
0

5.25
-1
8

Unit

V
mA
mA
ns
ns
ns

70

°C

./. The arrow Indicates that the failing edge of the enable pulse is used for reference.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions·

Paramater

Min

9LS/54LS
Typ·· Max

2

VIH
V IL
VI

Vee-MIN,
Vee-MIN,
VIL =VILmax,
Vee=MIN,
VIL =VILmax
Vee-MAX,
Vee=MAX,
Vee-MAX,
Vee-MAX
Vee-MAX,
Outputs open

VOH
VOL
II
IIH
IlL
lost
Icc

Min

9LS174LS
Typ" Max

2
0.7
-1.5

11--18mA
VIH-2V,
IOH=-lmA
VIH=2V

2.5

3.4
0.25

IIOL =4mA
IIOL 8mA

VI-7V
VI-2.7V
VI-0.4V

2.7
0.4
0.1
20
-0.4
-100

-15
All inputs at OV

22

0.2
-1.5
3.4
0.25
0.35

-15

38

22

Unit

V
V
V
V

0.4
0.5
0.1
20
-0.4
-100

mA
p.A
mA
mA

40

mA

V

'For conditions shown as MIN or MAX, use the appropriate value specified under recommendeCl operating conditions for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.

Switching Characteristics , V'cc -- 5V Over Recommended Free-Air Temperature Range
From
(input)

Parameter
Teat Conditions: C,

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
Tesl Conditions:

tpLH
tPHL
tpLH
tpHL
tpLH
tpHL

To
(output)

-SsoC
Min

Typ

+2SoC

Max

Max

39
34
44
39
46
41

22
20
25
22
27
24

35
30
40
35
42
37

25
23
28
25
30
27

39
34
44
39
46
41

44
39
49
44
51
46

26
24
29
26
31
28

40
35
45
40
47
42

30
28
33
30
35
32

44
39
49
44
51
46

Min

Min

+12SoC
Typ

Typ

Max

Unit

= lSpF, R, = 2k11 (See Fig. A, page 2-174)
Enable G

Any Q

Any M input

AnyQ

Any B input

Any Q

C, = 5OpF,

R,

25
23
28
25
30
27

ns
ns
ns

= 2k11 (See Fig. A, page 2-174)

Enable G

AnyQ

Any M input

Any Q

Any B input

AnyQ

30
28
33
30
35
32

ns
ns
ns

Note: Ae specification shown under _55°C and +125°e are for 9LS devices onlv,
All 50pF specifications are for 9LS only.

2-156

~YTHE031

Quadruple S-R Latches

LS279

FEATURES
•
•

Functionally and Mechanically Identical to 54279
Features Low Power Dissipation of 19 mW Typical
FUNCTION TABLE
(EACH LATCH)

H = high level
L = low level
Qo = the level of Q before the indicated input conditions were
established.
*This output level is pseudo stable: that is, it may not persist when
the 5 and R inputs return to their inactive (high) level.
tFor latches with double Sinputs:
H = both 5 inputs high
L = one or both 5 inputs low

INPUTS OUTPUT
st

R

Q

H

H

QO

L

H

H

H
L

L
L

L
H*

PIN-OUT DIAGRAM
Vee

45

4R

40

352

351

3R

30

~WLm

321161514

4

13

5

12

67891011

w~
1R

'-51

152

10

2R

25

2Q

GND

logic: see function table
Die Size .065 x .059

Recommended Operating Conditions
9LS/54LS
Min.

Supply voltage, Vee (See Note 1)

4.5

High-level output current, IOH

NOTE

5

5.5

Min.
4.75

-400

Low-level output current, IOL
Operating free-air temperature, T A

9LS/74LS

Nom. Max.

4
-55

125

0

Nom. Max.
5

Unit

5.25

V

-400

/LA

8

mA

70

°e

1. Voltage values are with respect to network ground terminal.

~YTHEO~

2-157

Quadrupule S-R Latches

LS279

Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
(Unless Otherwise Noted)

IIH

9LS/54LS

Test eonditions t

Parameter

Min.

High·level input voltage

Min.

2

Input clamp voltage

VOH High-level output voltage

VOL Low-level output voltage

Vee = MIN,

II =-18mA

Vee = MIN,

VIH = 2V,

VIL = VIL max,

10H =-400/LA

Vee = MIN,

VIH = 2V, llOL =4 mA

VIL=VILmax

2.5

Typ* Max.

Uni

2

VIL Low·level input voltage
VI

9LS/74LS

Typ* Max.

0.8

V

-1.5

-1.5

V

2.7

3.5
0.25

V

0.7

V

3.5

0.4

0.25

0.4

0.35

0.5

V

IIOL = 8 mA

Input current at

II

maximum input voltage

Vee = MAX,

VI =7V

0.1

0.1

mA

IIH

High-level input current

Vee = MAX,

VI = 2.7V

20

20

/LA

IlL

Low-level input current

Vee = MAX,

VI = O.4V

-0.4

-0.4

mA

130

mA

_ 7

mA

lOS Short-circuit output current1 Vee = MAX
Ice

Supply current

Vee = MAX,

-30
See Note 2

130
3.8

-30

7

3.8

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5V, TA = 25°e.
1Not more than one output should be shorted at a time.
NOTE
2. Ice is measured with all R inputs grounded, all S inputs at 4.5 V, and all outputs open.

Switching Characteristics Vee = S.OV Over Recommended Free-Air Temperature. Range.
Parameter
Test Coltditions:

From

To

(Input)

(Output)

CL = 15pF,

RL

_55°e
Min.

Typ.

+25°e
Max.

Min.

I

+125°e

Typ.

Max.

Min.

Typ.

Unit

Max.

= 2kO (See Fig. A, page 2-174)

tpLH

S

Q

15

26

12

22

15

26

ns

tPHL

S

Q

12

19

9

15

12

19

ns

Q

'0

~n

~!3

27

,n
'u

~n
~v

tr:::....

~

Test Conditions:
tPLH
tpHL
tpHL

CL = SOpF,

RL

...

= 2.Ok (See Fig. A, page 2-174)

S
S

Q

19

30

16

26

19

30

ns

Q

16

23

13

19

16

23

ns

R

Q

22

35

19

31

23

35

ns

..

Note: Ae speCification shown under _55°e and +125°e are for 9LS devices only. All 50pF specifications are for 9LS devices only .

2-158

~YTHEO]l

4-Bit Bi-Directional Shift Register
Witl\ Three-State
Outputs
--,,~.

"

...... -

LS295A

.

FEATURES

PINOUT DIAGRAM

..g

• Three-state version of LS95B parallel-access shift
register

d

OU11'UT
CQNTROL

9 8

DESCRIPTION
This 4-bit register features parallel inputs, parallel outputs,
and clock, serial, mode, and output control inputs. The
register has three modes of operation:
Parallel (broadside) load
Shift right (the direction QA toward Qo)
Shift left (the direction Qo toward QA)

1234560
SERIAL ABC D MiiDE GND
INPUT~CONTROL

Parallel loading is accomplished by'applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-lo.1(II transition of the clock input.
During parallel loading, the entry of serial data is inhibited.

13

12

11

10
9

8

Shift right is accomplished when the mode control is low;
shift left is accomplished when the mode control is high by
connecting the output of each flip-flop to the parallel input
, of the previous flip-flop (Q o to input C, etc.) and serial
data is entered at input D.

7

W~en

the output is high, the normal logic levels of the four
o~tPuts are available for driving the loads or bus lines. The
outputs are disabled independently from the level of the
clock by a low logic level at the output control input. The
outputs then present a high impedance and neither load nor
drive the bus bus line; however, sequential operation of the
register is not affected.

Die Size .067 x .082

LOGIC DIAGRAM
DATA INPUTS

~~

____~~~A~_ _~______~

MODE 161
CONTROL
SERIAL t11
INPUT
INPUTS

MODE

OUTPUTS
PARALLEL

CLOCK

SERIAL

H

X

X

H

X

H

X

a.,

CONTROL
H

H

A

x

X

H

X
X

x

C
x

aa

00

°A

It

aAO aBO aco aDO

d

aBn 0Cn Oon d
°AO aao Oeo aDO

CLOCK (91

d

b

act Qot
X
X
X
X
X
X

Dc

D

X
X

X

H

L

OUTPUT(SI
CONTROL

nAn aBn 0Cn
QAn as n OCn

When the output control is low, the outputs are dlubled to the high-impedance It8te;

however. sequentla' optlfation of the registers is not affected.
"

. -

tShifting left requires external connection of a. to A, acto
entered at input O.

e, and aD to C. Serial data is

H = high level (sl8a11y sIBte), L = low level (steady sIBle), X = irrelevant (any input,
including transitions)
= transition from high to low level.
a, b, c, d = the level of ateally-sIBte input at inputs A. e, C, or 0, respectively.
aM, a... aoo• aoo = the level of a., as, ac. or aD, respectively, before the indicated
stsady-state input conditions were esIBbHshed.
a... as.. ac., aon = the level of a., as, ac, or aD. resJl8Cliveiy, before the most-recent
trens~lon of the clock.

[EYTHEO?J

2-159

4-Bit Bi-Directional Shift Register
With Three-State Outputs

LS295A
Recommended Operating Conditions

Min
Supply voltage, V~e
High·level output current, IOH
Low·level output current, IOL
Clock frequency, fclock
Width of clock pulse, tw(clock)
Setup time, high·level or low·level data, tset\ll1_
Hold time, high-level or low-level data, thold
Operating free-air temperature, TA

'9LS/54LS
Nom
Max

4.5

5

5.5
-1
4
30

0
20
10
10
-55

125

Min

9LS/74LS
Max
Nom

4.75

5

0
20
10
10
0

Unit

5.25
-2.6
8
30

V
mA
mA
MHz
ns
ns
ns

70

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range {Unless Otherwise Noted
Parameter

Test Conditions·

Min

9LS/54LS
Typ·· Max

Vee=MIN,
Vee-MIN,
VIL =VILmax,
Vee=MIN,
VIL =VjLmaX
Vee-MAX,
Vo=2.7V
Vee-MAX,
Vo=O.4V
Vee=MAX,
Vee-MAX,
Vee-MAX,
Vee-MAX

VOH
VOL
IOZH
IOZL

9LS/74LS
Typ·· Max

2

2

VIH
VIL
VI

Min

0.7
-1.5

11=-18mA
VIH=2V,
IOH=MAX
VIH=2V,

2.4

3.4
0.25

IIOL -4mA
IIOL =8mA

VIL =VILmax,
VIH=2V,

0.8
-1.5
2.7

0.4

3.4

Unit
V
V
V
V

0.40
0.5

V

20

20

I1A

-20

-20

I1A

0.25
0.35

0.1
0.1
mA
20
20
I1A
-0.4
-0.4
mA
-15
-100
-15
-100
mA
I Condition A
14
23
14
23
mA
Vee=MAX
lee tt
I Condition B
15
25
15
25
"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
**AII tvoical vali:Jes are at Vee = ;V TA = 25°C"
tNot more than one output should be shorted at a time.
ttlee is measured with the outputs open, the serial input and mode control at 4.5V, and the data inputs grounded under the following conditions:
A. Output control at 4.5V and a momentary 3V, then ground, applied to clock input.
B. Output control and clock input grounded.
II
IIH
IlL
lost

VI=7V
VI-2.7V
VI-O.4V

i

Switching Characteristics, Vee = 5V Over Recommended Free-Air Temperature Range
Parameter

I

Min

Test Conditions: CL = 15pF,

-55°C
Typ
RL

Max

Min

+25°C
Typ

Max

, 2-160'

+125°C
Typ
Max

Unit

= 2kO (See Fig. A, page 2-174)

f max
40
30
27
35
tpLH
38
29
35
45
tpHL
48
37
10
18
tZH
21
12
10
18
tZL
21
12
Te"t Conditions: CL - 15pF, RL '" 2kO (See Fig. C on page 2-174)
19
28
tHZ
21
32 I
24
32
tLZ
36
26
Test Conditions: CL = 5OpF, RL = 2kO (See Fig, A, page 2-174) ,
tpLH
tpHL
tZH
tZL

Min

32
40
15
15

42
52
25
25

30
38
13
13

39
49
22
22

29
37
12
12
21
26
32
40
15
15

I

38
48
21
21

MHz
ns
ns
ns
ns

32
36

ns
ns

42
52
25
25

ns
ns
ns
ns

Note: Ae specification shown
under -5Soe and +12Soe
are for 9LS devices only.
All SOpF specifications
are'for 9LS devices only.

Quadruple 2-lnput Multiplexers with Storage

LS298

FEATURES
•
Selects One of Two 4-Bit Data Sources and Stores Data
Synchronously with System Clock.

•

PIN-OUT DIAGRAM

~9 DATA

Appl ications:
Dual Source for Operands and Constants in Arithmetic
Processor; Can Release Processor Register Files for
Acquiring New Data.

!;;IU::: INPUT
~'"

Cl

9

Implement Separate Registers Capable of Parallel
Exchange of Contents Yet Retain External load
Capability.
Universal Type Register for Implementing Various
Shift Patterns; Even Has Compound left-Right
Capabilities.
~---~vr----J

DESCRIPTION
These monolithic quadruple tWo-input multiplexers with
storage provide essentially the equivalent functional capabilities of two separate MSI functions (54157/74157 or
54LS157/74LS157 and 54175/74175 or 54LS175/74LS175)
in a single 16-pin package.
When the word-select input is low, word 1 (A 1, B1, C1,
D1) is applied to the flip-flops. A high input to word select
will cause the selection of word 2 (A2, B2, C2, D2). The
selected word is clocked to the output tern;)inals on the
negative-going edge of the clock pulse.

DATA INPUTS
FUNCTION TABLE
INPUTS
WORD
SELECT
L
H

X

•
•

H

QA

QB

Qc

QD

a1

b1

c1

d1

a2

b2

c2

d2

QAO

QBO

QCO

QDO

H = high level (steady state I
L = low level (steady state)

x = irrelevant (any
LOGIC DIAGRAM

OUTPUTS

CLOCK

input, including transitions)

• = transition from high to low level

a1. a2. etc. = the level of steady-state input at A1. A2. etc.
OAO. OBO etc. = the level of 0A. 0B. etc. entered on the
most recent J. transition of the clock input.

---- ____- J

. Dynamic input activated by a transition from a high level to a low level

~YTHEO"?J

2-161

Quadruple2-lnput Multiplexers with Storage

LS298

Recommended Operating Conditions
Min

9LS/54LS
Nom
Max

4.5

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOl
Width of clock pulse, high or low level, tw

Hold time, thold

5.5
-400
4

20
15
25
5
0
-55

Data
Word select
Data
Word select

Setup time, t setup

5

Operating free-air temperature, TA

Min

9LS/74LS
Nom
Max

4.75

125

5

20
15
25
5
0
0

5.25
-400
8

Unit
V

iJ. A
mA
ns
ns
ns

70

°C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

Min

9LS/54LS
Typ"
Max

VOH
VOL
II
IIH
III
lost
lee tt

9LS/74LS
Typ"
Max

2

2

VIH
Vil
VI

Min

0.7
-1.5

Vee=MIN,
Vee-MIN,

11=-18mA
VIH=2V

Vil =Vllmax,
Vee-MIN,
Vil =Vllmax
Vee-MAX,
Vee-MAX,
Vee-MAX,
Vee-MAX
Vee-MAX,

IOH=-400J.!A
VIH-2V,

2.5

3.4

tlOl -4mA
IIOL -8mA

0.8
-1.5
2.7

0.25

0.4

13

0.1
20
-0.4
-40
21

VI-7V
VI-2.7V
VI=O.4V
-6

3.4
0.25
0.35

-5
13

Unit
V
V
V
V

0.4
0.5
0.1'
20
-0.4
-42
21

V
mA
J.!A
mA
mA
mA

"For conditions shown as MIN or MAX, use the appropriate value specified under recommendea operating conditions for the applicable
device type.
-'All typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttWith all outputs open and all inputs except clock low, lee is measured after applying a momentary 4.5V, followed by ground, to
the clock input.

Switching Characteristics, Vee

= 5V Over Recommended Free-Air Temperature Range

I
I

J

1

I
L

I

I

I

I

I

1 23
26

I

1 36
40

1

J

I

I
+125°C
L Min I Typ I

I

I

-55°C
+25·C
Min
Typ
Max
Min I Typ
Max
Test Conditions: CL = 15pF. RL = 2kO (See Fig. A. page 2-174)
Parameter

18
27
tpi H
20
31
I 21
32
tpHL
23
35
Test Conditions: CL = SOpF;RL = 2kO (See Fig. A. page 2-174)

I

tPLH
tpHI

1

I

I
I

I

I
I

I

I

21
24

I
I

32
37

I

I
I

I

I

I

I

20
23
23
26

I
I
I

I

I
Maxi

31
35
36
40

Unit

I

ns

I

ns

I
I

Note: Ae specification shown under _55°e and +125°e are for 9LS devices only. All 50pF specifications
are for 9LS only.

2-162

~YTHEO]]

Hex Buffers, Tri-State, Common Enable

LS365

LS366

Hex Buffers, Tri-State, 4-Bit and 2-Bit

LS367

LS368

DESCRIPTION
The LS365/366/367/368 are high speed hex buffers with
3-state outputs. They are organized as single 6-bit or 2-bit/
4-bit, with inverting or non-inverting data (D) paths. The
outputs are designed to drive 15TTL Unit Loads on 60 Low
Power Schottky loads when the Enable (E) is LOW.
When Output Enable Input (E) is HIGH, the outputs are
forced to a high impedance "off" state. If the outputs of
the 3-state devices are tied together, all but one device must
be in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should ensure
that Output Enable signals to 3-state devices whose outputs
are tied together are designed so there is no overlap.

PIN-OUT DIAGRAMS
LS365
HEX 3-STATE BUFFER WITH
COMMON 2-INPUT NOR ENABLE

LS366
HEX 3-STATE INVERTER BUFFER
WITH COMMON 2-INPUT NOR ENABLE

TRUTH TABLE
INPUTS
E1
L

E2
L

L
H

L
X

X

H

0

TRUTH TABLE
INPUTS

OUTPUTS

OUTPUTS

E1
L

E2
L
L

(Z)

L
H

D
L
H

X

X

(Z)

(Z)

X

H

X

(Z)

L

L
H

H

X
X

H
L

LS368
HEX 3-STATE INVERTER BUFFER
SEPARATE 2-BIT AND 4-BIT SECTIONS

LS367
HEX 3-STATE BUFFER
SEPARATE 2-BIT AND 4-BIT SECTIONS

TRUTH TABLE
INPUTS
E
L
L
H

0
L

OUTPUTS

H

L
H

X

(Z)

~VTHE@'l

INPUTS

OUTPUTS

E
L

0
L

L
H

H

L

X

(Z)

H

2-163

LS365

LS366

Hex Buffers, Tri-State, Common Enable

LS367

LS368

Hex Buffers, Tri-State, 4-Bit and 2-Bit

Recommended Operating Conditions
Min
Supply Voltage, Vee
High·Level Output Current, 10H

9LS/54LS
Nom
Max

4.5

5

5.5
-1

Low·Level Output Current, 10l

9LS/74LS
Nom

Max

4.75

5

5.25
-2.6

V

24

mA

75

C

12

Operating Free·Air Temperature, T A

-55

125

Unit

Min

0

mA

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted
Test Conditions·

Parameter

Min

VIH

Guaranteed Input HIGH Voltage for All Inputs

Vil

Guaranteed Input lOW Voltage for All Inputs

VeD

Vee-MIN,

VOH

Vee-MIN, VIN-VIH or Vil
per Truth Table

IOH--l.0mA

Val

Vee=;MIN, VIN-VIH or Vil
per Truth Table

10l -12mA
I()L-24mA

9LS/54LS
Typ··
Max

2.0

2.4

IIH

Ve~=MAX,

III
lost

IOH=-2.6mA

Icc

Vee=MAX,

VIN=O.4V
V_OUT=OV
VIN=OV, VE =4.5V

V

2.0

V

.8
-1.5

-0.65
2.4

0.25

V~=7.0V

Vee-MAX,
Vee=MAX,

Unit

V

3.4

Vee=MAX, V out =2.4V, VE"=2.0V
Vee-MAX, V out =O.4V, VE-2.0V
Vee=MAX,
VIN=2.7V

10ZH
10Zl

9LS/74LS
Typ·· Max

2.0
.7
-1.5

-0.65

IIN--18mA

Min

-30

V

3.1

0.4

0.25. 0.40
0.35
0.5

20
-20

20
20

fJ.A

20
- .1
-0.4

20

fJ.A
mA

-100

- .1
-0.4
-30

-100

I LS365/367

13.5

24

13.5

24

J LS366/368

11.8 .

21

11.8

21

V

fJ.A

mA
mA
mA

"For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
·'AII typical values are at Vee = 5V, TA = 25 e.
tNot more than one output should be shorted at a time.
Q

Switching Characteristics, Vee
From

Parameter

Test Conditions:

iinput;

CL =

tplH ( lS365/367)
tpHl ( lS365/367)
tplH ( lS366/368)
tpHl ( LS366/368)
tZH
tZl

= 5V Over Recommended
To
iuutput;

_55°C
Nlln

tZH

Min

lYIax

+25°e
Iyp
Max

+125°e
Iyp
Max

Min

10

9

14

16
10

12
9
12

20
14

D'I
Di

9
12
9

14

°i
°i

12

20

7
10

E

12

20

10

16

12

20

°i

20

36

18

30

20

36

RL

=

Di

E

°i
a

19

7
10

20
14

6670 (See Fig. C, page 2-174)
12

tlZ
E
°i
tHZ
Test Conditions: CL = 125pF, (See Fig. A, page 2-174)
tplH (LS365/367)
Di
°i
tpHL (LS365/367)

tZl

Iyp

Unit

45pF (See Fig. A, page 2-174)

Test Conditions: CL = 5pF,

tplH ( LS366/368)
tpHL ( LS366/368)

Free-Air Temperature Range

10

20

I

27

I

17

16

I
I

15
23

I
I

I
I

12
19

ns
ns

20

I
I

20
27

12

20

10

15

12

20

15

26

15

21

15

26

12
15

20
26

10
15

15
21

12

20

15

20

16

26

20

16

24

42

13
21

35

24

26
40

ns

I

ns

ns
ns
ns

Note: Ae specification shown under _55°C and +125°e are for 9LS devices only. All 50pF specifications are for 9LS only.
2·164

~YTHE~

4-Bit Cascadable Shift Registers with
3-State Outputs

LS395A

FEATURES
•

PIN-OUT DIAGRAM

Three-State, 4-Bit, Cascadable, Parallel-I n,
Parallel-Out Registers

•

LS395A

Schottky-Diode-Clamped Transistors

•

Low Power Dissipation ... 75mW Typical (Enabled)

•

Applications: N-Bit Serial-To-Parallel Converter
N-Bit Parallel-To-Serial Converter
N-Bit.Storage Register

•

Pin for pin compatible with LS395

DESCRIPTION
4

These 4-bit registers feature parallel inputs, parallel outputs, and clock, serial, load/shift, output control and
direct overriding clear inputs.

5

6

7

m

~ c;!s ABC 0 ~t;: ~
.... ffi ~ '----v----' 9~ '"
U

en -

Shifting is accomplished when the load/shift control is
low. Parallel loading is accomplished by applying the four
bits of data and taking the load/shift control input high.
The data is loaded into the associated flip-flops and appears
at the outputs after the high-to-Iow transition of the clock
input. During parallel loading, the entry of serial data is
inhibited.

PARALLEL
INPUTS

When the output control is low, the normal logic levels of
the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the
level of the clock by a high logic level at the output control
input. The outputs then present a high impedance and
neither load nor drive the bus line; however, sequential
operation of the reigsters is not affected. During the highimpedance mode, the output at aD' is still available for
cascading.
The 9LS/54 LS395A is characterized for operation over
the full military temperature range of _55°C to 125°C;
the 9LS174LS395A is characterized for operation from.
O°C to 70°C.
FUNCTION TABLE
INPUTS
CLEAR

LOAD/SHIFT
CONTROL

3-8TATE OUTPUTS

CLOCK SERIAL

PARALLEL
ABC D

QA

QB

Qc

Qo

CASCADE
OUTPUT
Qo

L

X

X

X

X X X X

L

L

L

L

L

H

H

H

X

X X X X

QAO

QCO

H

H

.(

X

QBO
b

QOO
d

H

L

H

X

X X X X

H

L

.(

H

H

L

.(

L

c

QOO
d

QBO

QCO

QOO

QOO

X X X X

QAO
H

QAn

QBn

QCn

QCn

X XXX

L

QAn

QBn

QCn

QCn

•

b c d

•

When the output control is high, the 3-state outputs are disabled to the high-impedance state;
however, sequential operation of the registers and the output at QD are not affected.
H

= high

level (steadv state), L

= low level

(steadv state). X

.( = transition from high to low level.
QAO. QBO. QCO. QDO = the level of QA. QB.

QAn. QBn. QCn. QDn

~YTHE031

= irrelevant (anv input, including transitions)

Oc. or QO. respectively. before the indicated steady state input conditions were established.

= the level of QA. QB. QC. or

QO. respectively. before the most recent'" transition of the clock.

2-165

4-Bit Cascadable Shift Registers with
3-State Outputs

LS395A
Recommended Operating Conditions

Min

9LS/54LS
Nom
Max

4.5

Supply voltage, Vee

5

High-level output current, 10H
Low-level output current, 10L

0
25
20
10
-55

Clock frequency, fclock
Width of clock pulse, tw(clock)
Setup time, high-level or low-level data, t sewp
. Hold time, high-level or low-level data, thold
Operating free-air temperature,

TA

5.5
-1
4
25

125

9LS174LS
Max
Nom

Min

4.75

5

fl

5.25
-2.6
8
25

25
-20
10
0

Unit
V

rnA
rnA
MHz
ns
ns
ns

70

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
9LS/54LS

Test Conditions*

Parameter

Min

Typ"

2

VIH

VOH

VOL

10ZH
10ZL

Vee=MIN,

11=-lSmA

Vee-MIN,

VIW2V,

VI L=VILmax,

10H=MAX

2.4

Vee=MIN

QA,QB

IOL-12mA

VIL=VILmax,
VIW 2V

Oc,QO

loe-24mA

Vee-MAX,
Vee=MAX,

0.25

QA,QB

VIW2V,

Oc,QO
VIW2V,

QA,QB

VO=O.4V

Max

Unit

V
O.S

V

-1.5

-1.5

V

2.4
0.4
0.4

10L -SmA

VO=2.7V

Typ**

0.7

3.4
0.25

101--4mA

QO

Min
2

VIL
VI

9LS/74LS
Max

3.1

V

0.25

0.40

0.35

0.50

0.25

0.40

0.35

0.50

V
V

20

20

iJ. A

-20

-20

iJ. A

Oc,QO

II

Vee-MAX,

VI-7V

0.1

0.1

mA

IIH

Vee-MAX,

VI=2.7V

20

20

iJ. A

IlL

Vee=MAX,

VI=O.4V

lost

Vee-MAX

leett

Vee=MAX,

':':0.4
-15

L

-100

-15

-0.4

mA

-100

mA

COiiG:tkm A

,n

'u

~<>

18

29

Condition B

15

25

15

25

mA

*For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable

device type .
•• All typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
ttlee is measured with the outputs open, the serial input and mode control at 4.5V, and the data inputs grounded under the following
conditions:

A. Output control at 4.5V and a momentary 3V, then ground, applied to clock input.
B. Output control and clock input grounded.

2-166

4-Bit Ca!!~_ilct~ble Shift Registers with
3-State Outputs
Switching Characteristics, Vee

= 5V Over Recommended Free-Air Temperature Range

-55°e
Parameters

Typ

Min

Test Conditions: CL = 15pF, RL

+25°e
Max

Min

Typ

+125°C
Max

Typ

Min

Unit

Max

= 2kO (See Fig. C, psge 2-174)

f max

. 35

25
Clear to

LS395

MHz

27

40

23

35

27

40

ns

tPLH

27

40

23

35

27

40

ns

tPHL

24

35

20

30

24

35

ns

tpZH

17

25

13

20

17

25

ns

tpZL

28

41

24

36

41

ns

tpHZ

15

22

11

17

2~
15

22

ns

tPLZ

19

27

15

23

19

27

ns

tpHL

output

Test Conditions: CL - 5.OpF, RL - 2kO (See Fig. C, page 2-174)
tHZ

13

22

11

17

13

22

ns

tLZ

18

27

15

23

18

27

ns

Test Conditions: CL = SOpF, RL

= 2kO (See Fig. C, page 2-174)

tPHL ..

30

44

26

39

30

44

ns

tPLH

30

44

26

39

30

44

ns

tpHL

27

38

23

34

27

38

ns

tPZH

20

29

18

24

22

27

ns

tpZL

31

45

27

40

30

45

ns

tpHZ

18

26

14

20

19

26

ns

tpLZ

22

32

18

27

22

32

ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications
are for 9LS devices only.

LOGIC DIAGRAM

~

OATA INPUTS
___________
___________
JA~

~

A
(3)

CLOCK ;.:.(1.;.;0)_ _011

~~..-II-----+-.....+----+--..-ll-----+-.....,

CLEAR
OUTPUT (9)
CONTROL

(15)

,OA

(14)

DB

~-------~-~v
3·STATE OUTPUTS

~YTHE03J

(13)

DC

(12)

Do,

(11)

DO,
CASCADE
OUTPUT

2-167

4-By-4 Register Files with3~State
Outputs

LS670
FEATURES
• Separate Read!Write Addressing Permits Simultaneous
Reading and Writing
• Fast Access Times ... Typically 20 ns
• Organized as 4 Words of 4 Bits
• Expandable to 512 Words of n·Bits
• For Use as:
Scratch·Pad Memory
Buffer Storage Between Processors
Bit Storage in Fast Multiplication Designs
• 3-State Outputs
DESCRIPTION
The LS670 and MSI 16-bit TTL register files incorporate
the equivalent of 98 gates. The register file is organized as
4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either writein or retrieve data. This permits simultaneous writing into
one location and reading from another word location.
Four data inputs are available which are used to supply the
4-bit word to be stored. Location of the word is determined
by the write-address inputs A and B in conjunction with a
write-enable signal. Data applied at the inputs should be in

12

11

10

9

8

GND
7

6

5

its true form. That is, if a high-level signal is desired from
the output, a high-level is applied at the data input for that
particular bit location. The latch inputs are arranged so that
new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the D
input is transferred to the latch output. When the writeenable input, GW, is high, the data inputs are inhibited and
their levels can cause no change in the information stored
in the internal latches. When the read-enable input, GR, is
high, the data outputs are inhibited and go into the highimpedance state.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a
word. When the read address is made in conjunction with
the read-enable signal, the word appears at the four outputs.
This arrangement-data-entry addressing separate from dataread addressing and individual sense I ine-el im inates recovery times, permits simultaneous reading and writing,
and is limited in speed only by the write time (27 nanoseconds typical) and the read time (24 nanoseconds typical). The register file has a nondestructive readout in that
data is not lost when addressed.

VCC

WRITE SELECT ENABLE
DATA
D1

OUTPUTS
02

~

D2

~
D2

4

Q2
Q3

D3

RB

RA

04

03

--..- --..-

0

GND

DATA
READ SELECT OUTPUTS
Positive Logic: See Description

Die Size .090 x .068

2-168

~YTHEO]J

4-By-4 Register Files with 3-State
Outputs

LS670

LOGIC
WRITE FUNCTION TABLE (SEE NOTES A, B, AND CJ
WRITE INPUTS

WORD

READ FUNCTION TABLE (SEE NOTES A AND oj
READ INPUTS

OUTPUTS

WB

WA

Gw

0

1

2

3

RB

RA

GR

Q1

02

03

04

L

L

L

Q=D

Qo

Qo

Qo

L

L

L

W081

WOB2

WOB3

WOB4

L

H

L

Qo

Q=D

H

L

L

Qo

Qo

Qo
Q=D

H

H

L

Qo

Qo

X

X

H

Qo

Qo

NQTES:

Qo

L

H

L

W181

W182

W183

W184

H

L

L

W281

W282

W283

W284

Qo

Qo
Q=D

H

H

L

W381

W382

W383

W384

Qo

Qo

X

X

H

Z

Z

Z

Z

A. H = high level, L = low level, X = irrelevant, Z = high impedance (off)

B. (0 = D)

=

The four selected internal flip·flop outputs will assume the states applied to the four external data inputs.

C. QO = the level of Q before the indicated input conditions were established.
D. WOB1 = The first bit of word 0, etc.

FUNCTIONAL BLOCK DIAGRAM

DATA
INPUTS
OUTPUTS

--.-Ra

WRITE INPUT

~YTHEO!J

GR

RA

READ INPUT

2-169

4-By-4 Register Files with 3-State
Outputs

LS670
Recommended OperatIng Conditions
9lS/54lS
Min.
Supply voltage, Vee

4.5

High·level output current, IOH
low·level output current, IOl

(see Figure 2)

Min.

5.5

4.75

5

-1

Nom. Max.
5

Unit

5.25

V

-2.6

mA

8

mA

4

Width of write-enable or read·enable pulse, tw
Setup times, high· or low·level data

9lS174lS

Nom. Max.

25

25

ns

10

10

ns

15

15

ns

15

15

ns

5

5

ns

Data input with respect to

write enable, tsetup(D)
Write select with respect to
write enable, tsetup(W)
Data input with respect to

Hold times, high· or low·level data
(see Note 2 and Figure 2)

write enable, thold(D)
. Write select wi th respect to
write enable, thold(W)

latch time for new data, tlatch (see Note 3)
Operating free·air temparature range, T A
NOTES

25
-55

ns

25
125

0

70

'e

1. Voltage values are with respect to network ground terminal.
2. Write-select setup time will protect the data written into the previous address. If protection of data in the previous address is
not required, tsetup(W) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and
during thold(W) will result in data being written into that location. Depending on the duration of the input conditions, one or
a number of previous addresses:may have been written into.
3. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important only when attempting to read from a location immediately after that location has received new data.

2-170

~YTHE~

4-By-4 Register Files with 3-State
Outputs

LS670

Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Parameter

9LS/54LS

Test Conditions t
Min.

VIH

High-level input voltage

VIL

Low-level input voltage

VI

Input clamp voltage

VOH

High-level output voltage

2

Vee = MIN.

II = -ISmA

Vee - MIN.

VIH = 2V.

VIL = VILmax

VOL

Low-level output voltage

9LS174LS

Tvp* Max.

Vee = MIN.

10H - -lmA

2.4

VIH = 2V.

2

Unit

V
O.S

V

-1.5

-1.5

V

3.4
2.4

10L = 4mA

Tvpt Max.

0.7

10H =-2.6mA

VIL = VILmax

Min.

0.25

0.4

V
3.1
0.25

0.4

0.35

0.5

V

10L = SmA

Off-state output current.
10ZH

high-level voltage applied

Vee = MAX.

VIH = 2V.

Va = 2.7V

20

20

itA

Vee = MAX.

VIH = 2V.

Va = O.4V

-20

-20

/LA

Off-state output current,
10ZL

low-level voltage applied
Input current at

II

IIH

IlL

maximum input voltage

High-level input current

VI = 7V

0.1

0.1

0.2

0.2

GR

0.3

0.3

Anv D, R, orW

20

20

GW

40

40

GR

60

60
-0.4

Vee = MAX,
VI = 2.7V

Low-level input current

Anv.D.R,orW
GW

Vee=MAX,

Vee = MAX

lOS

Short-circuit output current 'i

Vee = MAX

ICC

Supply current

Vee =MAX,

Any D, R, orW

-0.4

GW

-O.S

-O.S

GR

-1.2

-1.2

-30
See Note 4

130
30

50

-30
30

mA

itA

mA

130

mA

50

mA

rFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5V, TA = 25°e.
iNot more than one output should be shorted at a time.
NOTE 4:
Maximum ICC is guaranteed for the following worst-case conditions: 4.5V is applied to all data inputs and both enable inputs,
all address inputs are grounded and all outputs are open.

~YTHEO:?J

2-171

.

LS670
SwHchlng Characteristics Vee
Parameter

Test Conditions: CL

_55°C

From

To.
(Output)

Min.

tpHL

Select

tpLH

Write

tpHL

enable
Data

Any Q
Any Q
Any Q

tpHL

tZL

Read

tHZ

enable

Any Q

tLZ

Min.

Typ.

+125°C
Max.

Min.

Typ.

Max.

Unit

A on page 2-174)

26

44

23

40

26

45

28

49

25

45

28

50

30

49

26

45

30

50

31

54

28

50

31

55

28

49

25

45

28

50

26

44

23

40

26

45

ns
ns
ns

18

39

15

35

18

40

25

44

22

40

25

45

33

54

30

50

33

55

19

39

16

35

19

40

ns

= SOpF, RL = 2.0kO (See Figs. 1, 2,3 on pages 2-172 and 2-173 and Fig. A on page 2-174)

tpLH

Read

tpHL

Select

tpLH

Write

tpHL

enable

tpLH

+25°C

Max.

= SpF, RL = 2.0kO (See Figs. 1, 2, 3 on pages 2-172 and 2-173 and Fig. C on page 2-174)

tZH

Test Conditions: CL

Typ.

= lSpF, RL = 2.0kO (See Figs. 1, 2, 3 on pages 2-172 and 2-173 and Fig.
Read

Test Conditions: CL

-

= S.OV Over Recommended Free-Air Temperature Range.

(Input)

tpLH

tpLH

4-By-4 Register Files with 3-State
Outputs

Data

Any Q
Any Q
Any Q

tpHL

30

49

27

44

31

50

32

54

29

49

33

55

34

54

30

49

35

55

35

59

32

54

36

60

32

5J

;19

49

JJ

5b

30

49

27

44

31

-50

ns
ns
ns

Note: AC specification shown under _55°C and +125°C are for 9LS devices only. All 50pF specifications are for 9LS devices only_

REAn
ENABLE

3V

~~----------

OV

j+--tHZ
WAVEFORM 1
(See Note A)

lclosed'

S2 open
~

1.5V
VOL

tLZ
WAVEFORM 2
Slopen,
(See Note A) ____~S=2~c=lo=se=d_'_______ OV

VOH
1.5V
S2 closed

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS

FIGURE 1

NOTES:

A. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the read-enable input. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the read·
enable input.

B. When measuring delay times from the read-enable input, both read-select inputs have been established at steady states.
C. Input waveforms are supplied by generators having the following characteristics: PRR .; 1 MHz, Zout '" 50
50%, tr .; 15 ns, tr .; 6 ns.

2-172

n, dutY cycle

.;

~YTHEO]J

4-By-4 Register Files with 3-State
Outputs

LS670

PARAMETER MEASUREMENT INFORMATION

-J

WRITE·SELECT

::U~o:AAiWB

1.3V

=l

t

3V

1.3_V__________
OV

l--.tsetup(W)

I
-----i-____

OATA INPUT
01,02,03, or D4
(See Note AI

1.3V

thold{W)

,----------

3V

1.3V

OV

3V

WRITE-ENABLE

INPUT GW
OV

3V

READ-SELECT
INPUT RA or RS
(See Note BJ

OV

VOH

OUTPUT
Q1. 02, 03, or 04

VOL

VOLTAGE WAVEFORMS (51 AND 52 ARE CLOSED)

FIGURE 2
NOTES: A. High·level input pulses at ,the select and data inputs ar~ illustrated; however. times associated with low-level pulses are
measured from the same reference points.
B. When measuring delay times from a read select input, the read-enable input is low.

C. Input waveforms are supplied by generators having the following characteristics: PRR .;; 2 MHz. Zout ,., 50
50%. tr';; 15 ns. tr';; 6 ns.

i \

n. dutY cycle .;;

,-------,.----------------------3V

DATA
01, 02,INPUT
03. or 04

1.3V

II

WRITE· ENABLE
INPUT Gw

-~--.--~

-I

tPLH

I-

'-----OV

~-~----w
tPHL

g~T~'"a3. '" 04 ____ J.3V

-i

VOl

'\.3V

VOLTAGE WAVEFORM 1 (S1 AND 82 ARE

ClOSED~'----

VOl

1r----

3V

~------.,-----------------------

ov

I~-----"---

3V

_ _~_~_J

OUTPUT
Q1, 02, 03, or 04

3V

~1.3V

~-------OV

,----3V
1.3V

------,-----------f------OV

VOLTAGE WAVEFORM 2 (51 AND 52 ARE CLOSED)

FIGURE 3
NOTES: A. Each select address is tested. Prior to the start of each of the above tests both write and read address inputs are stabilized with
WA ~ RA and WB ~ RB. During the test GR is low.
B. Input waveforms are supplied by generators having the following characteristics: PRR .;; 1 MHz. Zout ,., 50 n. dutY cycle .;;
50%. tr';; 15 ns. tr';; 6 ns.

~YTHE~

2-173

FIGURES A, Band C

SWITCHING TEST CONDITIONS

INPUT

--/f~~.;V
T"=--- ov
- - -3V

I.~V

~tPLH'1

:--tPH~ _ _ V

IN.PHASE~I
r
I
OUTPUT

I

':3V

I
I

1.

OH

1.3V

I

VOL

I

,...tPHL'"

:

:.~.

t-"tpLH--I

:VOH
1.3V
~

OUT·Of.PHASE·
OUTPUT

FIGURE A

FOR TOTEM-POLE PUTPUTS

VCC

rh
T

- - -VOL

VOLTAGE WAVEFORMS

LOAD CIRCUIT

fROM OUTPUT
UNOER TEST

1.3V

INPUT
TEST
POINT

--/f~-I.;V
T'==-- OV
-

I.~Y

\'tPLH

1.3V

I

,-tpHL""

:

:
I

VOL

t--tPLH--I

,:VOH

- -

-VOL

VOLTAGE WAVEfORMS

FIGURE B

J1

1.3V

I

1.3V·
1.3V
~

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

VCC

I

RL

I
'~"':''I Q

~UeA TEST

3V

r-tPHL~ _ _ V

1

OUT·Of·PHASE
OUTPUT

'OMour'ur

-

IN-PHAS~I
I
1
I
OH
OUTPUT:

(See Note Al
CL

TEST
POINT

-

.

OUTPUT
CONTROL" 1.3V

(low-level
enabling)

t

vvAVt:t-ORM 1
(See Note Cl

WAVEfORM 2
(See Note C)

_______ _
r----------

~.:.::.v

:

OV

itZL~----;:"4!;V

_ .... {SI

k ] (S•• Note BI

~3V

l\

!tLz1

81 ANO

i 51 CLoseo ~1
3 v i r :SZ CLOSED
: 52 OPEN"
i
~""1.5V
I
----'------'VOL
~tHZ---l
~tZH-jO.5V O.SV

== ,-:. ---

~

S10PEN,
52 CLOSED __

~.:!------ VOH
~.~~

~""15V

_ ",OV

51 ANO

.

S2 CLOSEO
S2

VOLTAGE WAVEfORMS

LOAD CIRCUIT

FIGURE C -

FOR THREE-STATE OUTPUTS

NOTES:
A. CL includes probe and jig capacitance.
B. All diodes ar.e 1 N3064.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the following characteristics: tr .. 15 ns, tf" 6 ns, PRR .; 1 MHz, Zout '" 50 n,
and tw = 100 ns.

2-174

~YTHEO}J

25LS
HIGH-PERFORMANCE
LOW-POWER SCHOTTKY
Page

25LS2~

8-bit serial/parallel two's complement multiplier
Quad serial adder/subtractor
8-bit serial/parallel register with sign extender_
8-bit shift/storage register with synchronous clear _

3-2
3-6
3-10
3-15

25LS122
25LS123
25LS138
25LS139
25LS151
25LS153

Single retriggeraple monostable multivibrator with clear
Dual retrig!jerable monostable multivibrator with clear
3-to-8Iine decoder/demultiplexer
Dual 2-to-4 line decoder/demultiplexer
8-to-l line multiplexer, compl_ outputs
Dual 4 to 1 line multiplexer

3-16
3-18
3-21
3-21
3-24
3-26

25LS157
25LS158
25LS160
25LS161

Quad 2-to-l line multiplexer
LS157, inverting
BCD decade counter, asynchronous clear
4-bit binary counter, asynchronous clear

3-28
3-28
3-30
3-30

25LS162
25LS163
25LS170
25LS174

BCD decade counter, synchronous clear _
4-bit binary counter, synchronous clear _
4 x 4 register file with open collectors_
Hex D-type flip-flop with clear

3-30
3-30
3-38
3-42

25LS175
25LS181
25LS190
25LS191

Quad D-type flip-flop with clear _
4-bit arithmetic logic unit
BCD decade up/down counter, synchronous
4-bit binary up/down counter, synchronous

3-42
3-44
3-50
3-50

25LS192
25LS193
25LSl94A
25LS195A

BCD decade up/down counter, synchronous_
4-bit binary up/down counter, synchronous _
4-bit universal shift register
4-bit parallel-access shift register

3-58
3-58
3-66
3-66

25LS251
25LS253
25LS257
25LS258

8-to-l line multiplexer with tri-state output _
Dual 4-to-l line data selectors/multiplexers with tri-state output _
Quad 2-to-1 line multiplexer with tri-state output_
Quad 2-to-1 line multiplexer with tri-state output_

3-73
3-75
3-79
3-79

25LS299
25LS670

8-bit universal shift/storage register
4 x 4 register files with tri-state outputs

3-83
3-86

25LS14
25LS15
25LS22

~YTHEO~

3-1

8-Bit Serial/Parallel Two's
Complement Multiplier

25LS14

FEATURES
•
•
•
•
•
•
•
•

Two's Complement Multiplication Without Correction
Magnitude Only Multiplication
Cascadable for any Number of Bits
8-Bit Parallel Multiplicand Data Input
Serial Multiplier Data Input
Serial Data Output for Multiplication Product
25 MHz Minimum clock Frequency
100% Reliability Assurance Testing in Compliance
With MIL-STD-883

Vcc

Y

X4

X5

X6

X7

K

§]

25lS14

[!]
CP

GND

FUNCTIONAL DESCRIPTION
The 25LS14 is an 8-bit by l-bit sequential logic element
that performs digital multiplication of two numbers represented in two's complement form to produce a two's
complement product without correction by using Booth's
algorithm internally. The device accepts an 8-bit multiplicand (X input) and stores this data in eight internal
latches. The X latches are controlled via the clear input.
When the clear input is LOW, all internal flip-flops are
cleared and the X latches are opened to accept new multiplicand data. When the clear input is HIGH, the latches are
closed and are insensitive to X input changes.
The multiplier word data is passed by the Y input in a
serial bit stream-least significant bit first. The product is
clocked out the S output least significant bit first.

The multiplication of an m-bit multiplicand by an n-bit
multiplier results in an m + n bit product. The 25LS14
must be clocked for m + n clock cycles to produce this
two's complement product. Likewi~e, the n-bit multiplier
(Y-input) sign bit data must be extended for the remaining
m-bits to complete the multiplication cycle.
The device also contains a K input so that devices can be
cascaded for longer length X words. The sum (S) output of
one device is connected to the K input of the succeeding
device when cascading. Likewise, a mode input (M) is used
to indicate which device contains the most significant bit.
The mode input is wired HIGH or LOW depending on the
position of the 8-bit slice in the total X word length.

LOGIC DIAGRAM

CLEAR
lelR)

L---+-......--1rlcLe:~
VO=Vl

CP

CLOCK
(CP)

M

Recommended Operating Conditions
Military
Min.
Supply Voltage, Vee

4.75

5

High-level Output Current, IOH

3-2

5.25

Min.
4.5

Nom. Max.
5

-1

Low-level Output Current, IOl
Operating Free-Air Temperature, T A

CommerciaJ

Nom Max.

8
-55

12
125

8
0

5.5

Units
V

-,.

mA

12

mA

70

·C

~YTHEr3l

8-Bit Serial/Parallel Two's
Complement Multiplier

25LS14

Electrical Characteristics Over Operating Temperature Range (Unless Otherwise Noted)
Military

Min.
VCC = MIN., IOH = 1.0mA

VOH Output HIGH Voltage

VCC= MIN.
VIN = VIH or VIL

VIL

I nput LOW Level

VI

Input ClamP Voltage

3.4

3.4

Units

V
0.40
0.45

2.0

Vce

0.8

VCC = MAX., VIN = O.4V

Input HIGH Current

Vce = MAX., VIN = 2.7V

Input HIGH Current

Vce = MAX., VIN = 5.5V

V
V

-1.2

-1.2

0.48

0.48
-1.2

K' CLR

-1.2

CP

-1.6

-1.6

Y

-3.2

-3.2

X,M

20

20

K,CLR

30

30

CP

40

40

-40

VCC= MAX.

mA

/,A

80

80

1.0

1.0

mA

-100

rnA

155

mA

-100
91

Vce= MAX.

Power Supply Current

0.8

X,M

MIN., liN = -18mA

V

V

2.0

Guaranteed input logical LOW

(Note 4)

ICC

2.7

Max.

0.4

voltage for all inputs

Output Short Circuit Current

ISC

Typ.

0.45

Y
II

Min.

IOL = 12rnA

voltage for all inputs

Input LOW Current

IIH

Max.

IOL = 8.0mA

Guaranteed input logical HIGH

Input HIGH Level

IlL

2.5

(2)

VIN = VIH or VIL

VOL Output LOW Voltage

VIH

Commercial

Typ.

Test Cond!tions (Note 1)

Parameters

155

-40
91

Switching Characteristics, Vee = 5V
Parameter

From

To

(Input)

(Output)

+25°C
Min.

Typ.

Max.

Units

Test Conditions: CL = 15pF, RL = 2kO (See Fig. A, page 2-174)
tpLH

Clock

y

13

20

ns

tpHL

Clock

y

13

20

ns

17

25

ns

tpHL

Clear

ts

Set up time

th

Hold time

ts

Set up time

th

Hold time

ts

Set up time

th

Hold time

tpw

X
Y to Clock
K to Clock
Xi to Clear

32

ns

0

ns

18

ns

0

ns

13

ns

0

ns

Clock Pulse

Clock Hi

15

ns

Width

Clock Low

15

ns
ns

tp_w

Clear Pulse Width

20

t,

Clear Recovery Time

18

f max

Max. Clock Frequency

25

t;YTHE03J

ns
40

MHz

3-3

8-Bit Serial/Parallel Two's
Complement Multiplier

25LS14

FUNCTION TABLE
Inputs
CLR

-

CP

K

M

Xi

Y

-

L

L

-

CS

H

-

-

-

OP

H

-

-

-

-

-

L

H.

t

H

t

H

t

H

t

,

Internal

Output

Y-1

S

-

-

-

L

L

Load New Multiplicand and Clear Internal Sum and Carry Registers

-

-

Device Enabled

Function

Most Significant Multiplier Device
Devices Cascaded in Multiplier String

-

-

L

L·

AR

-

-

L

H

AR

Add Multiplicand to Sum Register and Shift

-

-

H

L

AR

Subtract Multiplicand from Sum Register and Shift

H

H

AR

Shift Sum Register

Shift Sum Register

H = HIGH
L= LOW
t = LOW to HIGH transition
CS = Connected to S output of higher order device
OP =: Xi latches open for new data (i = o. 7)
AR = Output as required per Booth's algorithm

DEFINITION OF FUNCTIONAL TERMS

Xo. Xl. X2. X3. X4. X5. XS. X7 The eight data inputs for
the multiplicand (X) data.
V The serial input for the multiplier (V) data-least signifi·
cant bit first.
S The serial output for the product of X • V -least signifi·
cant bit first.
CP Clock. The buffered common clock input for the serial/
parallel multiplier. All functions occur on the LOW-toHIGH transition of the clock.

3-4

CLR Clear. The buffered common clear for all flip-flops
within the device. When the clear is LOW all flip-flops are
cleared. Also the buffered X-input latch enable. When the
clear input is LOW. the X latches will accept new X-input
data.
K The sum expansion input to the serial/parallel multiplier.
Allows for cascading devices.
M The mode control input for the most significant bit of
determine the most significant bit.

~YTHEO~

B-Bit Serial/Parallel Two's
Complement Multiplier

25LS14

APPLICATIONS

24·BIT

y ----------~~~~~+-+-+-+-+-------------.-+-~~~~~~-+------------,

--------1M

M

H

-----;K
CLR
CP

25lS14

H

I------\K

I----IK

25LS14

CLR
CP

CLR
CP

25lS14

CLEAR __--~------------------------~~~--------------------------~
CLOCK--~~----------------------------~----------------------------~

PRODUCT
SERIAL

OUTPUT

SERIAL/PARALLEL
CLOCK ENABLE

6
' - - - DA

SIGN EXTEND
CLOCK
OUTPUT CONTROL

RE

SER/PAR

H - DB
MUX
CLEAR
25LS22
SE
S-BIT SHIFT REGISTER

~~

CP
OE

aD

DY7DV SDYSDV 4DY 30Y 20Y lOY a

MULTIPLIER INPUT

CLOCK

CP
y
L-K
L-M

CLEAR

~YTHEO:?J

X7 X6 X5 X4X3 X2Xl Xo
25LS14
SERIAL/PARALLEL
MULTIPLIER

CLR

3-5

Quad Serial Adder/Subtractor

25LS15

FEATURES.
•
•
•
•
•

Four Independent Adder/Subtractors
Use with Two's Complement Arithmetic
Magnitude Only Addition/Subtraction
Advanced Low-Power Schottky Processing
100% Reliability Assurance Testing in Compliance With
MIL-STD-883

VCC

~

CLOCK

CLEAR

DESCRIPTION
The 25LS15 is a serial/parallel two's complement adder/
subtractor designed for use in association with the
25LS14 serial/parallel two's complement multiplier. This
device can also be used for magnitude only addition or
subtraction.
Four independent adder/subtractors are provided with
common clock and clear inputs. The add function is A plus
B and the subtract function is A minus B. The clear function sets the internal carry function to· logic one in subtract
mode. This least significant plus one is self propagating in
the subtract mode as long as zeroes are applied at the LSB's.

Note: Pin 1 is marked for orientation

The 25LS15 is particularly useful for recursive or nonrecursive digital filtering or butterfly networks in fast
fourier transforms.

LOGIC DIAGRAM
(One of Four Similar Functions)

I

---£>0
TO 3 OTHER
---£>0
c--J
ADDER/SUBTRACTIONS
A1 ---£>o-rr~[)o--+-----IID
ar-F1SUM

CLOCK

....- - - - - I C P
CLR

S1
ADD
SUBTRACT

CLEAR

3-6

~~~i~-------------------------~-----

} TO 3 OTHER
ADDER/SUBTRACTORS

Quad Serial Adder/Subtractor

25LS15

Recommended Operating Conditions
Military

Supply Voltage VCC
High·Level Output Current IOH
Low Level Output Current IOL
Operating Free Air Temperature

Commercial

Min.

TVp.

Max.

Min.

Typ.

Max.

4.5

5

5.5
-440

4.75

5.0

5.25
-440
8
+70

-55

8
+125

0

Units
V
j.lA
mA

°c

Electrical characteristics Over Operating Temperature Range (Unless Otherwise Noted)
Military

Commercial

Typ.
Parameters

Description

V OH

Output HIGH Voltage

VOL

Output LOW Voltage

V IH

Input HIGH Level

Test Conditions (Note 1)

Min.

(Note 21

Max.

2.5

Vee = MIN .• IOH = -440j.lA

Min.

Typ.

Max.

2.7

Units
Volts

VIN = V IH or V IL
Vee - MIN.
V IN = V IH or V IL

IIOL =4.0mA

0.4

0.4

IIOL -8.0mA

0.45

0.45

Guaranteed input logical HIGH
voltage for all inputs

2.0

Volts

2.0

Guaranteed input logical LOW

Volts

V IL

Input LOW Level

0.7

0.8

Volts

VI

Input Clamp Voltage

Vee - MIN., liN = -18mA

1.5

1.5

Volts

IlL
(Note 31

I "put LOW Current

Vee = MAX" VIN = O.4V

-0.36

-0.36

Volts

IIH
(Note 31

Input HIGH Current

Vee = MAX., VIN = 2.7V

20

20

Volts

Input HIGH CUrrent

Vee = MAX., VIN = 7.0V

0.1

mA

-85

mA

75

mA

II

Output Short Circuit

Ise

Current (Note 4)
Power Supply Current

lee

Notes: 1.
2:
3,
4.
5.

INote 51

voltage for atl inputs

Vee = MAX.
Vee = MAX.

0.1
-30

-85
48

-30

75

48

For conditions shown as Min. or Max., use the appropriate value specified under Electrical Characteristics for the applicable' device type.

Typical limits are at Vee = 5.0V. 25°C ambient and maximum loading.
Actual input currents = Input Load Current x Input Load Factor (See Loading Rultes),
Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
All inputs HIGH, measured after a LOW-to-HIGH clock transition.

~YTHEO~

3·7

Quad Serial Adder/Subtractor

25LS15

= 5.0V, TA = +25°C

Switch Characteristics Vcc
Parameters

From

To

(Input)

(Output)

Test Conditions: CL = 15pF,
tpLH

RL

+25"C
Min.

Max.

Units

= 2kO (See Fig, A, page 2-174)

Clock

F

tPHL
tpHL

Clear

ts

Set up time

th

Hold time

ts

Clear R'ecovery time

th

Clear Hold time

F

22

14

22

20

30

25

ns

ns

0

"I

ns

ns

0

17

CIOCk HIGH
LOW

l

Width

14

10

A,B,S

Clock Pulse
tpw

Typ.

ns

17

tpw

Clear Pulse Width

20

fMAX

Max. Clock Frequency

30

ns
40

MHz

DEFINITION OF FUNCTIONAL TERM8

FUNCTION TABLE
Internal
External Inputs
CP

CLR

S

A

Point
B

C

Output

F
L

X

L

L

X

X

L

C1
L

X

L

H

X

X

H

H

L

H

X

X

X

NC

NC

NC

H

H

X

X

X

NC

NC

NC

t
t
t
t

H

L

L

L

L

L

L

H

L

L

L

H

L

H

H

L

L

H

L

L

H

L

H

L

L

H

H

H

L

t
t
t
t
t
t
t
t

H

L

H

L

L

L

H

H

L

H

L

H

H

L

H

L

H

H

L

H

L

H

L

H

H

H

H

H

H

H

L

L

L

L

H
L

Function

Clear

CP Clock
Add

CLR Clear

H

H

L

L

H

H

H

H

L

H

L

L

L

H

H

L

H

H

L

H

t
t

H

H

H

L

L

H

L

H

H

H

L

H

H

H

t
t

H

H

H

H

L

L

H

H

H

H

H

H

H

L

= Data

In the Carry Flip-Flop Before the Clock Transition

C
C,
X
NC
H
L

t

Subtract

= Data In the Carry Flip-Flop After the Clock
= Don't.Care

= No Change
= HIGH
= LOW

= LOW-to-HIGH Transition

A1,A2.A3,A4
B1,B2,B3,B4
81,82,83,84

The" A" input into each adder/subtractor
The "B" input Into each adder/subtractor
The add subtract control for each adder/
subtractor. When S is LOW, the F function
is A+B. When S is HIGH, the F function
is A-B.
The four independent serial outputs of the
adder/subtractor.
The clock input for the device. All internal
flip-flops change state on the LOW-toHIGH transition.
When the clear input is LOW, the four
independent addllr/subtractors are asynchronously reset. The sum flip-flop is always set to logic "0". The carry flip-flop
is set to logic "O~' in the add mode and
logic "1" in the subtract mode.

Quad Serial Adder/Subtractor

25LS15

APPLICATIONS
The normal butterfly network associated with the CooleyTukey Fast Fourier Transform (FFT) algorithm is shown
below. Here we assume A, B, C, D and Ware all complex
numbers such that:
A

~

B

~

BR+jB,

W

~

WR+jW,

C

CR+jCI~IAR+BRWR-B,W,)+j(A,+BRW,+B,WR)

D

CR+jD,~(AR-BRWR+B,W,)+J(A,-BRW,-B,WR)

The four multiplications can be implemented using four
25LS14 serial-parallel multipliers (the appropriate number
of bits must, of course, be used). The additions and the
subtractions are implemented using the 25LS15 quad serial
adder/subtractors. This diagram depicts only the basic data
flow; binary weighting of the numbers, rounding, truncation,
etc. must be handled as required by the individual design
parameters.

AR+jA,

The outputs C and D are also complex numbers and are
eva Iuated as:

FAST FOURIER TRANSFORM (FFT) BUTTERFLY

~

'N

25LS22
II-B'T REG

00

y

25LS14

A

S

1/425LS15
(A-B)

F - "...~. B

1/425LS15
(A+ B)

B

X

F_

A

WR~
'N
-r---B

25LS22

B

00

X

~

IN

25 LS22

00

B,WR

.... y

25LS14

S

y

25LS14

S

~B

B,W,

~B

X

A
1/425LS15
(A-B)

1/425LS15
(A+B)
A

F~

F_'

WI~
A ,~ 'N
B

25LS22

B

00

-Y

X

25LS14

BRW'

S~A

B
1/425LS15
(A+B)

F

B

A
1/425LS15
(A-B)

F_

An F FT butterfly connection for complex arithmetic inputs and outputs.

~YTHEO]J

3-9

8-Bit Serial/Parallel Register with Sign Extend

25LS22

FEATURES
• Three-State Outputs
• Multiplexed Serial Data Input
ill Sign Extend Function
• Advanced Low-Power Schottky Processing
• 100% Reliability Assurance Testing in Compliance With
MI L-STD-883

Vcc

[§]

SE

DB DV6 DV4 DV2 OVo

CLOCK

.DESCRIPTION

25LS22

CP

Co

CLEAR

The 25LS22 is an 8-bit Serial/Parallel register with 3state outputs. Data may also be loaded in a serial manner
from inputs DA or DB under control of a multiplexer
select input A register enable function also provides parallel
load, shift and hold functions.
The 25LS22 has a sign extend function which is specifically designed for use with the 25LS14 eight by one
serial/parallel two's complement multiplier. Typical shift
frequency is 50MHz. The 25LS22 is packaged in a standard
20-pin package.

8GNO
Note: Pin 1 is marked for orientation.

LOGIC DIAGRAM

SERIAL~~~+-----~---4~--~--~--~--~--~--~---+--~---+--~---'--+----'

PARALLEL

2

EX;~~~~18~~~O-~~~

DB
MUX
SELECT

17_-'FFL.Fl
r

-19,'L./'~-I--<"""

u....=:,d.-+....

Co

CLEAR~~~-----t--1-~-+~~-+-+-t-+-+-+-+-+-+-+-+-+~-+-+-+~-+-+-+~~~-+~
CLDCK~.t~-----+--~---+-+-+---+-+-+---+-+-+---+-+~-----+~----~~----~~

~~:i~~--------~~)D-r-+-t---1-+-+---1-+-t---1-+-+---1r-~--~r-~--~r-~---.

CONTROL

~

OV6

3-10

14

16
OV3

OV3

13
OV1

~YTHEO:3J

8-Bit Serial/Parallel Register with Sign Extend

25LS22

Recommended Operating Conditions
Military

Supply Voltage V CC

Min.

Typ.

4.5

5.0

Min.

Typ.

5.5

4."7:5

5.0

-0.44

10 0

High Level Output Current 10H

Commercial

Max.

I DYi

Max.
5.25
-0.44

-1.0

Low Level Output Current 10L

4
-55

Operating Free Air Temperature

-2.6

8
+125

4
0

Unit

V
mA

8

mA

70

°c

Electrical Characteristics Over Operating Temp. Range (Unless Otherwise Noted)
Military

Commercial

Typ.

Description

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Level

VIL

Input LOW Level

VI

Input Clamp Voltage

IIH
(Note 3)

Input LOW Current

Input HIGH Current

Input HIGH Current
Off State (High Impedance)

10

VIN

= MIN.
= VIH or VIL

VCC

= MIN.

VCC

Output Current (DYi)

Min.

(2)

DYi, 10H

2.4

2.4

DYi,

2.4

= -1.0mA
10H = -2.6mA
10L = 4.0mA

VCC

= MAX., VIN

= 2.7V

(Except DYi)
VCC

= MAX., VIN = 5.5V

(Except DYi)
VCC

= MAX.

0.4

0.45

0.45

0.8

V
V

-1.5

-1.5

SE

1.08

-1.08

S

0.72

-0.72

Others

0.36

-0.36

SE

60

60

S

40

40

Others

20

20

SE

0.3

0.3

S

0.2

0.2

Others

0.1

0.1

= 2.4V

40

40

Vo - O.4V

-100

-100

Vo

V
V

0.7

= -18mA

= MAX., VIN = O.4V

V

2.0

Guaranteed input logical LOW

VCC

Max.

0.4

2.0

voltage for all inputs

liN

Typ.

2.4

10L - 8.0mA

Guaranteed input logical HIGH

= MIN.,

Min.
2.7

= -440J.LA

voltage for all inputs

VCC

Unit

Max.

2.5

00, 10H

VIN = VIH or VIL

IlL
(Note 3)

II

Test Conditions (Note 1)

mA

J.LA

mA

J.LA

Output Short Circuit
ISC
ICC

Current (Note 4)
Power Supply Current

VCC = MAX.
VCC

= MAX.

-30

-85
40

65

-30
40

-85

mA

65

mA

Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device
type.

2. Typical limits are at VCC = 5.0V, 25°C ambient and maximum loading.
3. Actual input currents = Unit Load Current x Input Load Factor (See Loading Rules).
4. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.

~YTHE03J

3-11

8-81t Serial/Parallel Register with Sign. Extend

25LS22

Switching Characteristics Vee = 5V, TA = +25°C
Parameters

To
(Output)

Test Conditions: CL = SOpF,
tPLH

RL

Clock

Clock

aO

Clear

24

18

26

23

30

16.5

24

18

26

23

30

DYi

tpHL
tPHL

Units

Max.

16.5

DYi

Clear

tPLH

Typ.

Min.

= 2kO (see Fig. C on page 2-174)

tpHL
tpHL

+2SoC

From
(Input)

aO

ns
ns
ns
ns

Test Conditions: CL = 15pF, RL = 2kO (see Fig. C on page 2-174)
tZH
tZL

OE

DYi

1HZ

13

21

18

26

13

21
26

tLZ

18

tZH

18

26

tZL

23

32

SER/PAR

DYi

tHZ
tLZ
Is

Set Up Time RE To Clock

20

ts

Set Up Time SE To Clock

10

ts

Set Up Time S To Clock

15

ts

Set Up Time DA/DB to Clock

15

ts

Set Up Time DY· To Clock

15

ts

Clear to Recovery To Clock

8.0

ts

Set Up Time SIP To Clock

15

th
th

Hold Time Any Input
Clear Hold Time

tpw

Clock Pulse Width

tpw
f max

Clear Pulse Width

20

Max. Clock Frequency

50

18

26

23

32

ns

ns

ns

ns

0

ns

0

I

HIGH

8.0

LOW

8.0

ns
ns
MHz

70

FUNCTiON TABLi:
INPUTS

Register
Clear Enable

Mode

L

Clear
Parallel Load

OUTPUTS

Seriall

Sign

Mux

Parallel

Extend

Select

DE"

X
X

X
X

L
H

X
X

X

X

t

D7

D6

D5

D4

D3

D2

01

·DO

DO

t

DA

Y7n

Y6n

Y5n

Y4n

Y3n

Y2n

YIn

YIn

L

X
X

H

L

L

X
X
X

H

L

H

H

L

Clock

DY7

DY6

DY5

OY4

OY3

OY2

OYI

OYO

L

L

L

L

L

L

L

L

L

Z

Z

Z

Z

Z

Z

Z

Z

L

QO

H

L

H

H

H

L
L

t

DS

Y7n

Y6n

Y~n

Y4n

Y3n

Y2n

YIn

YIn

Sign Extend

H

L

H

L

X

L

t

Y7n

Y7n

Y6n

Y5n

Y4n

Y3n

Y2n

YIn

YIn

Hold

H

H

X

X

X

L

t

NC

NC

NC

NC

NC

NC

NC

NC

NC

Shift Right

L

LOW

H =

HIGH

t

Clock LOW·to-HIGH Transition

NC=

No Change

Don't Care
Z = High·lmpedance Output State
X
*When the DE input is HIGH, all input/output terminals are at the high-impedance state; sequential operation or clearing of the register is not
affected.
D7. D6 ... DO = the level of the steady-state input at the respective DY n terminal is loaded into the flip-flop while the flip-flop outputs (except
aO) are isolated from the DY n terminal.

0A. DB = the level of the steady state inputs to the serial multiplexer input.
Y7n. Y6n ... YOn = the level of the respective an flip-flop prior to the last Clock LOW-to-HIGH transition.

3-12

~YTHE03J

8-Bit Serial/Parallel Register with Sign Extend

25LS22

DEFINITION OF FUNCTIONAL TERMS
DYi

The multiplexed parallel input/output port to the
device. Data may be parallel loaded into the
register or data can be read in parallel from the
register on these pins. These outputs can be forced
to the high-impedance state, i = 0 through 7.

aO

The continuous output from the aO fl ip-flop of
the register. This output is used for serial shifting.

RE

Register Enable. When RE is LOW, the register
functions are enabled. When RE is HIGH, the
register functions (parallel load, shift right and sign
extended) are inhibited.

SIP

SE

Serial/Parallel. When SIP is LOW, the register can
by synchronously parallel loaded. This input forces
the register output buffers to the high-impedance
state independent of the OE input. When SIP is
HIGH, the register contents are shifted right on
the clock LOW-to-HIGH transition.

CP

Clock. The clock pulse for the register. Register
operations occur on the LOW-to-HIGH transition
of the clock pulse.

OE

Output Control. When the OE input is HIGH, the
eight DYi outputs are in the high-impedance state.
When OE is LOW, data in the eight flip-flops will
be present at the register parallel outputs unless
SIP is LOW.
LOADING RULES (In Unit Loads)
Fan-Out

Inputl
Output

Pin No:s

Output
HIGH

Output
LOW
4mA
SmA

RE
SIP

2

DA

3

DY7

4

0.3

50/130

11

22

DY5

5

0.3

50/130

11

22

DY3

6

0.3

50/130

11

22

DYI

7

0.3

50/130

11

22

OE

8

Sign Extend. When the SE input is LOW, the
contents of the a7 flip-flop will be repeated in
the a7 fl ip-flop as the register is sh ifted right.
When SE is HIGH, the two-input multiplexer
(DA and OS) is enabled to enter data during the
serial shift right. The a7 flip-flop (DY7) is normally considered the MSS of the register for
arithmetic definitions.

CLR

9

GND

10

oA, DB
S

CLR

LOW
Input
Unit Load

CP

11

QO

12

22

11

22

DYO

13

0.3

50/130

11

22

The serial inputs to the device.

DY2

14

0.3

50/130

11

22

Multiplexer Select. When S is LOW, the DA serial
input is selected. When S is HIGH, the Os serial
input is selected.

DY4

15

0.3

50/130

11

22

DY6

16

0.3

50/130

11

22

DB
SE

17

1

18

3

S

19

2

VCC

20

Clear. The asynchronous clear to the register.
When the clear is LOW, the outputs. of the flipflops are set LOW independent of all other inputs.
When the clear is HIGH, the register will perform
the selected function.

~YTHEO:?J

Low-Power Schottky TTL unit load is defined as 20"A measured at
2.7V HIGH and -0.36mA measured at O.4V LOW.

3-13

8-Bit Serial/Parallel Register with Sign Extend

25LS22

APPLICATIONS

WN""{
INPUTS

b

I

b

,Ie

"

c-'

b

e,

r - DA

r-r-

cce

25LS22

'"
ce
Q'
DY7

DY6

DY5 DY4

DY3 OY2

DVl

~

Load upper byte and

e,

OVo

25LS22

ce
Q'
DY7

25LS22
LOWER BYTE

DY6

DY5 DY4 DY3

DY2 DYl

oVo

FUNCTION

SE

SIP

RE

OE

SE

SIP

RE

OE

Description

H

H

L

X

X

L

L

X

Load from Bus

L

H

L

H

X

X

H

H

X

L

L

X

X

X

X

X

extend lower byte sign

to upper byte

I

,Ie

DA

Qo

25LS22
UPPER BYTE

SYSTEM
OPERATION

Load lower byte and

~

"

c-'

extend upper byte sign

7 clock cycles to
extend sign

Load from Bus

8 clock cycles to extend

while shifting value to

upper byte sign and shift

lower byte position

H

H

L

H

H

H

L

H

Read 16-bit word to Bus

X

X

X

L

X

X

X

L

upper byte into lower byte

position

Two 25LS22 S-bit registers can be used to perform the sign
extend associated with two's complement S-bit bytes for
arithmetic operations in a 16-bit machine. If the upper byte
value is to be used, it is shifted to the lower bit positions
and its sign is extended. If the lower byte value is to be
used, it is held in place while the sign is extended downward from the MSB position of the upper byte.

Unload

_

SET-UP, HOLD, AND RELEASE TIMES

~N~~~_

I_ts_~~th_I
TIMING

+-_______

_______

1________

INPUT _ _ _ _- : - _.....

DAOA~ts~-~

'N'",~~~
Notes: 1.

3-14

Diagram shown for HIGH data only. Output
transition may be opposite sense.

2.

Cross-hatched area is don't care condition.

~YTHEO]J

8-Bit Shift/Storage Register with Synchronous Clear

25LS23

FEATURES
•
•
•
•
•

Synchronous Clear
Three-State Outputs
Common Input/Output Pins
Advanced Low-Power SchottkY Processing
100% Reliability Assurance Testing in Compliance With
MI L-STD-883

CONNECTION DIAGRAM

Top View

vcc

S,

Sl

QH1

H/QH F/QF

O/Qo B/QB

ClK

SR

~

DESCRIPTION

25lS23

The 25LS23 is an 8-bit universal shift/storage register
with 3-state outputs. The function is similar to the
25LS299 with the exception of a synchronous clear
function. Parallel load inputs and register outputs are
multiplexed to allow the use of a 20-pin package. Separate
continuous outputs are also provided for flip-flops A and H.
Note: Pin 1 is marked for orientation

Four modes of operation are possible-Hold (store), Shiftleft, Shift-right and Load Data. The 25LS23 has a
typical shift frequency of 50MHz. The 25LS23 is packaged in a standard 20-pin package.

LOGIC DIAGRAM

So

SHIFT
(181 LEFT
SERIAL
INPUT

SERIAL

INPUT
CLEAR

OUTPUT
CONTROLS

I

G,
G2 (3)

113)
BlaB

r§VTHE@J

161

(14)

151

(15)

C/Qe

DIDO

E/Qe

F/OF

141
G/Oo

3-15

8-Bit Shift/Storage Register with Synchronous Clear

25LS23

Recommended Operating Conditions
Commetcial

Military
Min.

Supply Voltage

Vee

4.5

L
I

High Level Output Current IOH

Typ. Max.

5.0

5.5

Typ.

Max.

4.75

5.0

5.25

-0.44

00,,-07
DYO-DY7

-0.44

-1.0

Low-Level OutPut Current In!-

4.0
-55

Operating Free Air Temperature T A

Min.

-2.6

8.0

+125

4.0

8.0

0°

70

Unit

V
mA
mA
°e

Electrical Characteristics Over Operating Temperature Range (Unless Otherwise Noted)

Military
Description

Test Conditions (Note 1)
Vee

Output HIGH Voltage

VOH

VOL

Output LOW Voltage

VIH

Input HIGH Level

0

MIN.

VIN "" VIH or .1 DYO-DY7
VOL j

(21

Input LOW Current

Vee: MAX .• VIN : O.4V

Input HIGH Current

V

4.0mA
IOl'" B.OmA

0.25

0.4

0.25

0.4

0.35

0.45

0.35

0.45

2.0

2.0
0.7

0.8

-1.5

-1.5

50. 51

-0.8

-D.8

All others

-0.4

-D.4

40

40

(Except DYi)

All others

20

20

Vee: MAX .• VIN - 5.5V

50. 51

0.2

0.2

All others

(Note 41
Power Supply Current

VO: 0.4V

0.1

0.1

-100

-100

40

VO: 2.4V
-30

Vee: MAX.

-85
38

Vec - MAX. (Note 51

57

V
V

50. 5 1

Vee: MAX.

Output Current
Output Short Circuit CUrrent

Typ. Max. Units

Vee: MAX .• VIN: 2.7V

(Except DYi!

Off-State (High Impedancel

Min.

2.4

voltage for all inputs

IIH
Input HIGH Current
iNote 3)

Commercial

Max.

2.7

Guaranteed input logical LOW

Vee: MIN .• liN: -18mA

lee

2.4

-2.6mA

voltage for all inputs

Input Clamp Voltage

Ise

-1.0mA

L10H -

I 10L -

Input LOW Level

10

IloH -

VIN "" VIH or VIL .
Guaranteed input logical HIGH

VI
(Note 3)

2.5

Vee - MIN.

VIL

IlL

-440~A

IIOH '"

1 0 0. 0 7

Min.

400
-30
38

V
V
mA
"A
mA
~A

-85

mA

57

mA

Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type.

= 5.0V. 25°C ambient and maximum loading.
= Unit Load Current x Input Load Factor (see Loading Rules!'

2. Typical limits are at VCC
3. Actual input currents

4. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
5. Icc-measured with clock input HIGH and output controls HIGH.

= +25°C

Vee

From

To

I

(lnputl

(Output)

Switching Characteristics (TA

Parameters

= 50Vl
+25°C
Min.

TYP.

I

Max.

Units

Teat Condllton.: C, = 15pF, R, = 2k!l (See FIg. A, page 2-174)
tPLH

Clock

OOor 07

Clock

DYi

tPHL
tPLH

19
23
18

tPHL

ts

Sj, So Setup Prior to Clock

20

ts

SR. SL Setup Prior to Clock

20

Clock Pulse Width

25

th

Hold Time

3.0

ts

Clear Setup Prior to Clock

tpw

tZH
tZL
tZH
tZL
f max

Sit So

DYi

Gl. G2

DYi

ns

21

ns

20

Maximum FrequencV

20
19
20

ns

18
50

mH.

Teat Condition.: C, = 5pF, R, = 2k!l (See Fig. C, page 2-174)
tLZ
tHZ
tLZ
tHZ

3-16

So

DYi

Gl. G2

DYi

51.

22
20

2D
16

ns

8-Bit ShiftlStorageRegister with Synchronous Clear

25LS23

TRUTH TABLE
OUTPUTS

INPUTS

Function

Clear
Output
Control
Hold

G2

00

0,

OVO

OV,

OV2

OV3

DV4

DV5

DVS

(Note'l

L

L

L

L

L

L

L

L

L

L

L

L

X

H

L

NC

NC

Z

Z

Z

Z

Z

Z

Z

Z

X
X

L

H

NC

NC

Z

Z

Z

Z

Z

Z

Z

Z

H

H

NC

NC

Z

Z

Z

Z

Z

Z

Z

Z

L

L

L

L

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

H

H

L

L

A

H

A

8

C

D

E

F

G

H

H

L

L

L

L

DY6

L

DYa

DV,

DV2

DY3

DV4

DY5

DY6
DY6

SL

CLEAR

CLOCK

X

X.

L

t

X
X
X

X

X

X

X
X

X
X

X
X

X
X
X

X
X

H

X

H
H

t
t
t
t
t

M

Load (Note 21

X
X

0

Shift Right

L

D

Shift Right

H

X
X

E

Shift Left

X

L

H

Shift Left

X

H

H

H

INPUTS/OUTPUTS

G,

SR

S,

So

OV,

H

L

L

L

H

DY6

H

DVa

DY,

DY2

DY3

DY4

DY5

L

H

L

L

DY,

L

QY,

DY2

DY3

DY4

DY5

DYS

DY,

L

L

H

L

L

DY,

H

DY,

DY2

DY3

DY4

DY5

DYS

DY7

H

L= LOW

Z = High Impedance

t

H= HIGH

X = Don't Care

NC = No Change

Notes: 1. Either LOW to observe outputs.

= Transition LOW-to-HIGH

2. In this mode DYj are inputs.

DEFINITION qF FUNCTIONAL TERMS
SR

Shift right data input to 07

SL

Shift left data input to 00

Active LOW input to control three-state outpui: in active LOW AND configuration.

Clear

Active LOW synchronous input forcing the
00 through 07 register to see LOW condi·
tions, visable only if outputs are enabled.

The only two direct outputs; used to cascade
sh ift operations

A LOW-to-HIGH transition will result in the
register changing state to next state as described by mode and input data condition.

Clock

Input/Output line dependent on mode and
output control. Input only with mode select
LOAD. Output in all other modes but subject to output select (<31, (32).

DYO-DY7

Mode selection control lines used to control
input (output during load) conditions

50. 5 ,

APPLICATION

INPUT/OUTPUT DATA

I I I I I I I I

Ilrrrr!"r

SHtf:T
RIGHT

OVo ov, DY2 OV3 DY4 DYs OY6 DY7

SHIFT
LEFT
INPUT

OVo DY, DY2 OVa DV4 OVs DYe DY7

Sl

SR

5l

5R

DO

elK

CLEAR

25LS23

r--So

r - 5,

Go
SERIAL
OUTPUT
LEFT

I

a'

I---

G,loG2 p-

I

elK

CLEAR

25L523

r--So

c--

5,

Go

°7

I

I

I---

G,loG2 pSERIAL
OUTPUT
RIGHT

CLEAR
CLOCK
OUTPUT
CO~tTROL.

rv'ODE{

CO~ITROL

16-Bit Cascaded Parallel Load/Unload Sbift Right/Left Register

~YTHE~

3-17

25LS122

Single and Dual Retriggerable
Monostable· Multivlbrators with Clear

25LS123

FEATURES
•
•
•

•
•
•
•
•
•
•
•

25LS122

Retriggerable for Very Long Output Pulses, Up to 100%
Duty Cycle
Overriding Clear Terminates Output Pulse
Low Power Dissipation:
25LS122 ... 30 mW Typical
25LS123 ... 60 mW Typical
Compensated for VCC and Temperature Variations
D·C Triggered from Active-High or Active-Low Gated
Logic Inputs
25LS122 Has Internal 10 kn Timing Resistor
Diode-Clamped Inputs
Compatible for Use with TTL or DTL
50mV improved VOL compared to 9LS/74LS
440ILA source current
100% reliability assurance testing in compliance with
MI L-STD-883

DESCRIPTION
The 25LS122 and 25LS123 multi vibrators feature doc triggering from gated low-level-active (A) and high-level-active
(B) inputs, and also provide overriding direct clear inputs.
Complementary outputs are provided. The retrigger capability simplifies the generation of output pulses of extremely
long duration. By triggering the input before the output
pulse is terminated, the output pulse may be extended.
The overriding clear capability permits any output pulse to
be terminated at a predetermined time independently of
the timing components Rand C. Enough Schmitt hysteresis
is provided to ensure jitter-free triggering from the B inputs
with transition rates as slow as 1 volt per second. Figure
1 illustrates triggering the one·shot with the high·level-active
(B) inputs.

GND
8

7

logic: see function table
NC-No internal connlilction.

14

Vee
Die Size .085 x .071

25LS123
GND
10

9

8

Die Size .085 x .071

OUTPUTS

A2

B1

B2

Q

Q

L

X

X

X
X
X
X

H

H

X
X

X
X
L
L
L

X
X
X
X
X

X
X
X

L
L
L
L
L

H
H
H
H
H

Jl.

lS
V

X
X
X

L
L
L

H

t
t

H
H
H
H
H
H
H
H

t
t
3-18

25LS123 FUNCTION TABLE
(SEE NOTE 1)

CLEAR A1

t
t

H

L

X

X

L

L

X
H

t
H
H

t
H
H
H
H
H
H

L
H
H

t

IL

H
H

..fl.

t
H
H
H
H
H

L

.n..
SL

..n.
.Il..

SL
SL

7

15

25LS122 FUNCTION TABLE
(SEE NOTE 1)

INPUTS

1

OUTPUTS

INPUTS
CLEAR A

B

Q

Q

L

X

X
X

H

X
X

X

L

L
L
L

H
H
H

H
H

L

t

Sl.

1I

t

t

L

H
H

SL
Sl.

V
lS

H

V
V
V

LS

V

1S
1S

t'EVTHEO!J

Single and Dual Retriggerable
Monostable Multivibrators with Clear

25LS122

25LS123

NOTES: 1. H ~ high level (steady state), l ~ low level (steady state), t ~ transition from low to high level,. ~ transition from high to low
level, H ~ one high-level pulse, l ~ one low-level pulse, X ~ irrelevant (any input, including transitionsl.
2. To use the internal timing resistor of 25lS122, connect R int to VCC'
3. An external timing capacitor may be connected between Cext and Rext/Cext (positive).
4. For accurate repeatable pulse widths, connect an external resistor between Rext/Cext and Vee with Rint open circuited.
5. To obtain variable pulse widths, connect external variable resistance between Rint or Rext/Cext and Vee.

TVPICAL OUTPUT PULSE WIDTH
EXTERNAL TIMING CAPACITANCE

RETRIGGER PULSE
(See Notel
9 INPUT
.....-tw+tPLH~

I

L
Jl______

OUTPUTQ

I

1---

L

~OUTPUT -WITHOUT RETRIGGER

OUTPUT PULSE CONTROL USING RETRIGGER PULSE
8 INPUT

CLEAR
OUTPUT

a..JI.-_-_-_-_-_-_'
. ' -:_______

OUTPUT PULSE CONTROL USING CLEAR INPUT

100

10

1000

Cext-External Timing Capaciunce-pf

NOTE:

Retrigger pulse must not start before 0.22 Cext (in
picofarads) nanoseconds after previous trigger pulse.

tThese values of resistance exceed the maximum recommended for
use over the full temperature range of the 9lS/54lS' circuits.
FIGURE 2

FIGURE 1- Typical Input/Output Pulses

These monostables are designed to provide the system designer with complete flexibility in controlling the pulse
width, either to lengthen the pulse by retriggering, or to
shorten by clearing. The 25LS122 has an internal timing resistor which allows the circuit to be operated with only an
external capacitor, if so desired.
The output pulse is primarily a function of the external

capacitor and resistor. For Cext
pulse width (tw) is defined as:
tw

=

> 1000

pF, the output

0.4 • RT • Cext

where
RT is in H1. (either internal or external timing resistor),
Cext is in pF,
tw is in ns.
For pulse widths when Cext';;; 1000 pF, see Figure 2_

Recommended Operating Conditions
Military
Min.

4.5

Supply voltage, Vec
High-level output current, IOH

Nom. Max_
5

5.5

4
A or 8 inputs high

8

4
40

A or.B inputs low

40

40

Clear low

40

40
225

5

External capacitance, Cext

No restriction

5

-55

125

Nom_ Max_'

5

Unit

5.25

V

-440

/LA

8

mA

ns

360

kn

No restriction

50

Wiring capacitance at Rext/Cext terminal

~YTHEOBJ

4.75

40

External timing resistance, R ext

Operating free-air temperature, T A

Min_

-440

low-level output curreot, IOL

Pulse width, tw

Commercial

0

50

pF

70

°c

3-19

25LS122

Single and Dual Retriggerable
Monostable Multivibrators with Clear

25LS123

Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
(Unless Otherwise Noted)·
Commercial

Military

Parameter
VIH

High.level input voltage

VIL

Low·level input voltage

VI

Input clamp voltage

VOH High·level output voltage

VOL

Unit

Test Conditions t

Low·level output voltage

Min.
2

TVp.* Max.

V

0.7

0.8

V

-1.5

-1.5

V

11=-18mA

Vee = MIN,

VIH = 2V,

VIL = VIL max,

10H = -440I'A

Vee = MIN,

VIH = 2V, llOL = 4 mA

0.25

0.4

0.25

0.4

IIOL = 8mA

0.35

0.45

0.35

0.45

2.5

Vee = MAX,

VI = 7V

2.7

3.5

Input current at
maximum input voltage

TVp.* Max.

Vee = MIN,

VIL=VILmax
II

Min.
2

V

3.5

0.1

0.1

V

mA

IIH

High-level input current

Vee = MAX,

VI = 2.7V

20

20

JjA

IlL

Low-level input current

Vee = MAX,

VI = O.4V

-0.4

-0.4

mA

lOS

Short-circuit outputcurrent1

Vee = MAX

-85

mAo

-15

Supply current
lee

(quiescent or triggered)

Vee = MAX,

-85

-15

I 25LS122

6

11

6

11

25LS123

12

20

12

20

See Note 2l

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5V, T A = 25'e.
iNot more than one output should be shorted at a time and duration of the short·circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, lee is measured after a momentary ground, then 4.5 V, is
applied to clock.

Switching Characteristics Vee
Parameters

= 5.0V Over Recommended Free-Air Temperature Range.

From

To

(Input)

(Output)

+25'e
Min.

Typ.

Max.

Unit

Tesi ConditionS: CL= 15pF, RL = 2.Ok C... = OpF, Rex. = 5.0 kO
(See Fig. 3, page 3-19, and fig. A, page 2-174)
A
tPLH

B
A

tpHL
tpHL

B
elear

tpLH

Q

Q

20

30

26

38

28

40

35

48

ns
ns

Q

16

22

ns

Q

25

40

.ns

116

200

ns

4.5

5.0

ns

twQ(min)

Aor 8

Q

*tw Q

Aor B

Q

4.0

"For this test R ext = 10 kn, eext = 1000 pF.

3-20

~YTHEO!)

Decoders/Demultiplexers

25LS138 25LS139
PIN-OUT DIAGRAMS

FEATURES
•

•
•
•

•
•
•

25LS138: 3-Line-to-8-Line Decoder
1-of-8 Demultiplexer
25LS139: Dual 2-Line-to-4-Line Decoder
Dual 1-of-4 Demultiplexer
Higher Speed compared to 9LS/54LS and 9LS/74LS
8mA sink current over full military temperature
range
50mV improved VOL compared to 9LS/74LS
440IlA source current
100% reliability assurance testing in compliance with
MI L-STD-883_

25LS138

DATA OUTPUTS

,..-_ _-'''1..._ _- - ,

VI V2

V6'

DESCRIPTION
The 25LS138 decodes one-of-eight iines dependent on. the
conditions at the three binary select inputs and the three
enable inputs. Two active-low and one active-high enable
inputs reduce the 'need for external gates or inverters when
expanding. A 24-line decoder can be implemented without
external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for
demultiplexing applications.

Die Size .063 x .069

25LS139

The 25LS139 comprises two individual two-line-to-four-line
decoders in a single package. The active-low enable input
can be used as a data line in demultiplexing applications.
These circuits are designed to be used in high-performance
memory-decoding and data-routing applications requiring
very short delay times.

1234567[]]
lG lA lB IVO IVIIV21V3 GND

ENABLE~~
Die Size .063 x .069

25LS138

FUNCTION TABLE
ENABLE

INPUTS
SELECT

OUTPUTS
YO Y1 Y2 V3 Y4 Y5 Y6 Y7

C

B

A

X

G2"
H

X

X

X

H

H

H

H

H

H

H

H

25LS139

L

X

X

X

X

H

H

H

H

H

H

H

H

L

L

L

L

L

H

H

H

H

H

H

H

FUNCTION TABLE (111)

H
H

G1

L

L

H

H

L

H

H

H

H

H

H

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

H

H

H

H

H

L

H

H

H

H

H

L

H

L

L

H

H

H

H

L

H

H

H

H

X

X

H

H

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

L

L

L

L

H

H

H

H

L

H

H

L

H

H

H

H

H

H

L

H

L

L

H

H

L

H

H

H

L

H

H

H

H

H

H

H

H

H

H

L

L

H

L

H

H

L

H

L

H

H

H

H

H

L

*G2 ~ G2A + G2B
H = high level, L = low level, X = don't care

[[AYTHEO]]

INPUTS
ENABLE SELECT
B
A
G

L

H

H

~

high level, L

OUTPUTS
YO V1 Y2 Y3

~

low level, X

~

don't care

3-21

Decoders/Demultiplexers

25LS138 25LS139
LOGIC DIAGRAMS

25LS138

25LS139
1YO
ENABLE lG

-'-''P-t1===::::::t:=:ln

lYl
lY2

DATA
OUTPUTS

1Y3

DATA
OUTPUTS

SELECT
INPUTS

Recommended Operating Conditions
Military

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOl
Operating free-air temperature, TA

Min

Nom

4.5

5

4
-55

Commercial
Max

Min

Nom

Max

5.5

4.75

5

-440
8
125

4
0

5.25
-440
8
70

Unit

V
J.lA
mA

"C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

VIH
Vil
VI
VOH
Val
II
ilH
IlL
lost
lee

Test Conditions'

Min

Military
Typ"
Max

2

2
11--18mA
Vee-MIN,
Vee-MIN,
VIW 2V,
VIL =Vllmax, loW -440J.lA
VIH=2V,
Vec=MIN,
Vil =VII_max
VI-7V
Vee-MAX,
VI-2.7V
Vee=IVIAX,
VI-O.4V
Vee=MAX,
Vee=MAX
Vee-MAX,
Outputs enabled and open

Commercial
Typ"
Max

Min

0.7
1.5
2.5

3.4
0.25
0.3

IIOl =4mA
IIOl =8mA

-15
125LS138
125LS139

6.3
6.8

u.8
1.5
2.7

0.4
0.45
0.1
20
0.36
-85
10
11

3.4
0.25
0.35

15
6.3
6.8

Unit

V
V
V
V

0.40
0.45

V

U.1

mA

20
0.36

J.lA
mA
mA

-85
10
11

mA

'For conditions shown as MIN or M,o.X, use the appropriate value specified under recommendea operating conditions for the applicable
device type.
-'All typical values are at Vce = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.

3-22

~YTHE~

25LS138 25LS139

Decoders/Demultiplexers
25LS138
Switching Characteristics, Vee

= 5V, TA =

+25°C

Levels

Parameter

of
Delay

Test Conditions: C L

tpLH
tpLH
tPLH
tpLH

+25 0 C
From

To
(output)

(input)

= 15pF, RL = 2kO
Binary

2

tpLH
tpLH

3

Any

Select

3

Enable

Any

25LS139
Switching Characteristics, Vee
Levels
of
Delay

Test Conditions: C L

tpLH
tpLH
tpLH
tpLH
t PLH
tpLH

~YTHEO]J

2
3
2

=

Typ

Max

Unit

10
14
15
18
10
15
12
18

15
20
23
27
15
23
18
27

ns

ns
ns

Typ

Max

Unit

10
12
13
14

15
18
20
21
12
16

ns
ns

(See Fig. A, page 2·174)

2

tpLH
tpLH

Parameters

Min

ns
ns
ns
ns
ns

= 5V, TA = +25°C
+250 C

From

To
(output)

(input)
15pF, RL

=

2kO

(See Fig. A, page 2·174)

Binary
Select

Min

Any

9
Enable

Any

11

ns
ns
ns
ns

3-23

8-Line-To-1-Line Multiplexers

25LS151

PIN-OUT DIAGRAMS

FEATURES
•
•
•
•
•
•
•
•
•

25LS151

Select one of eight data sources
Perform parallel-to-serial conversion
25LS151 has complementary outputs
25LS151 has strobe input
Higher Speed,compared to 9LS/54LS and 9LS/74LS
8mA sink current over full military temperature
range
50mV improved VOL compared to 9LS/74LS
440/lA source current
100% reliability assurance testing in compliance with
.MI L-STD-883

DESCRIPTION
These monolithic data selectors/multiplexers contain full
on-chip binary decoding to select one-of-eight data sources.
The 25LS151 has a strobe input which must be at a low
logic level to enable the device. A flfgh level at the strobe
forces the W output high, and the Y o~tPut low.

3

14

4

13

The 25LS151 features complementary Wand Y outputs.

LOGIC DIAGRAMS

5

12

6

11

7

STROBE
(ENPBLEI

Die Size: .056 x .057

DO
01

25LS151

02
03
OATA
INPUTS

D4
05

l:

FUNCTION TABLE
INPUTS

OUTPUT V
OUTPUTW

SELECT

OUTPUTS

STROBE

y

W

C

B

A

S

x

X

X

H

L

H

L

L

L

L

DO

01
02
03
04
05
06
07

Do
D1
52
03
54

L

L

H

L

L

H

L

L

L

H

H

L

H

L

L

L

H

L

H

L

H

H

L

L

H

H

H

L

-

05

Os
D7

H ~ high level. L ~ low level, X ~ don't care
DO, 01 ... 07 ~ Ihe level of the 0 respective inpul

3-24

~YTHEO~

8-Line-To-1-Line Multiplexers

25LS151

Recommended Operating Conditions
Military

Supply voltage, Vee
High-level output current, IOH
Low-level output current, 10L
Operating free-air temperature, TA

Commercial

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
-440
8
125

4.75

5

5.25
-440
8
70

4
-55

4
0

Unit

V
pA
mA

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions·

Parameter

Min

Military
Typ··
Max

VOL
II
IIH
IlL
los t
Icc

2.5

Max

0.8
-1.5

0.7
1.5

11- 18mA
Vee-MIN,
Vee-MIN,
VIH-2V,
VIL =VILmax low -440pA
Vee-MIN,
VIH-2V,
IIOL -4mA
VIL =VILmax
110L -8m A
VI-7V
Vee-MAX,
VI-2.7V
Vee-MAX,
VI-O.4V
Vee-MAX,
Vee-MAX
Outputs open
Vee=MAX,
All inputs at 4.5V

VOH

Typ··

2

2

VIH
VIL
VI

Commercial
Min

2.7

3.4
0.25
0.3

~15

6.0

0.40
0.45
0.1
20
-0.4
-85
10

-15
6.0

V
V
V
V

3.4

0.35

Unit

0.40
0.45
0.1
20
0.4
-85

mA
pA
mA
mA

10

mA

V

*For conditions shown as MIN or MAX, use the appropriate value specified under retommended operating conditions for the applicable

device type .
• 'All typical values are at Vee = 5V, TA = 25 e.
tNot more than one output should be shorted at a time.
Q

Switching Characteristics, Vee = 5V, TA = +25°C
From
(Inplill

To
(output)

tpLH
tpLH
tpLH

A, B or C
(4 levels)

y

tPLH
tPLH

(3 levels)

Parameter
Teat Conditions: CL

tpLH
tPLH
tPLH
tpLH
tpLH
t~H

tpLH

r:VTHEO]J

-

+ 25 C
Q

Min
Typ
15pF, RL - 2kO (See FIg_ A. page 2-174)

A, B, or C

W

Strobe

y

Strobe

W

Any 0

y

Any 0

W

Max

272

41

20
16
22
22
18
13
17
17
15
10
10

30
23
32
33
27
20
26
26
23
15
15

Unit

ns
ns
ns
ns
ns
ns

3-25

Dual 4-Line-To-1-Line Multiplexer

25LS153

FEATURES
•
Permits multiplexing from N lines to 1 line
Performs parallel-to-serial. conversion
•
•
Strobe (Enable) line provided for cascading (N lines
to "lines)
•
Non-inverting
•
Higher Speed compared to 9LS/54LS and 9LS174LS
8mA sink current over full military temperature
•
range
•
50mV improved VOL compared to 9LS174LS
440MA source current
•
•
100% reliability assurance testing in compliance with
MIL-STD-883

PIN-OUT DIAGRAM

DATA

2

3

4

ITlm[IJ[iJ

STROBE B '-----y----J 1Y GND
lG
DATA INPUTS OUTPUT
SELECT
13 12 11 10

DESCRIPTION
The 25LS153 is a high speed Dual 4-Line to 1-Line Multiplexer with common select inputs and separate strobe
(enable) inputs for each half. Each half can select one bit of
four and present it at the output in non-inverted form.

14

9

15

8

16

LOGIC DIAGRAM

STROBE lG (1)
(ENABLE)

Die Size .057 x .061

lCO (6)

lCl~(5~)--------~~1-L-/
DATA 1

lC2~(4~)______~~~1-~

IV

lC3 f(3~)---t=$$I~.-J

FUNCTION TABLE
SELECT
INPUTS

DATA 2 [ : '

'~:

C2~~--~==EE~

2C3~(1~3~)_ _~=E==Ef~
STROBE 2G
(ENABLE) (15)

3-26

2V

DATA INPUTS

I STROBEIOUTPUTi

Cl

C2

C3

G

x

co
x

x

x

X

H

L

L

L

X

X

X

L

L
H

B

A

x
L

v

L

L

H

X

X

X

L

L

H

X

L

X

X

L

L

L

H

X

H

X

X

L

H

H

L

X

X

L

X

L

L

H

L

X

X

H

X

L

H

H

H

X

X

X

L

L

L

H

H

X

X

X

H

L

H

Select I~puts A and B are common to both sections.

H

~

high level, L

~

low level, X

~

don't care

~YTHEO:;J

Dual 4-Line-To-1-Line Multiplexer

25LS153

Recommended Operating Conditions
Military

Supply voltage, Vcc
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA

Min

Nom

4.5

5

Commercial
Max

Min

Nom

5.5

4.75

5

4

8
125

5.5
-440

-440

-55

Max

4

8
70

0

Unit

V
p.A
mA

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)

VIH
VIL
VI
VOH
VOL
II
IIH
IlL
lost
leeL tt

Military

Test Conditions'

Parameter

Min

Typ"

Commercial
Max

2
Vee=MIN,
Vee=MIN,
VIL =VILmax,
Vee-MIN,
VIL =VILmax
Vec-MAX,
Vee-MAX,
Vee-MAX,
Vee=MAX
Vee=MAX

Min

Typ**

2
0.7
-1.5

11=-18mA
VIH=2V,
IOH=-440p.A
VIH-2V,
IIOL -4mA
IIOL -8m A
VI-7.0V
VI=2.7V
VI=O.4V

2.5

Max

3.4
0.25
0.3

-15
6.2

0.8
-1.5
2.7

0.40
0.45
0.1
20
-0.36
-85
10

3.4

0.35

-15
6.2

Unit

V
V
V
V

0.40
0.45
0.1
20
-0.36
-85
10

V
mA
p.A

-~
mA
mA

*For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable

device type.
""All typical values are at Vee = 5V, T A = 25°C.

tNot more than one output should be shorted at a time.

tt leCL is measured with the outputs open and all inputs grounded.

Switching Characteristics, Vee
Parameter

Test Conditions: CL = 1SpF,

tpLH
tpLH
tpLH
tpLH
tpLH
tpLH

~YTHE031

= 5V, TA = +25°C

From
(input)
RL

Data
Data
Select
Select
Strobe
Strobe

To
(output)
= 2kO.

+25°C
Min

Typ

Max

Unit

(See Fig. A, page 2-174)

y
y
y
y
y
y

7
10
16
20
13
15

13
16
24
25
n-,20
20

ns
ns
ns
ns
ns
ns

3-27

Quadruple 2-Line-To-1 Line Multiplexers

25LS157 25LS158
DESCRIPTION

FEATURES

These data selectors/multiplexers select a 4-bit word from
one of two sources and present it at the four outputs_ The
25LS157 presents true data; the 25LS158 presents inverted
data_

•
•
•
•
•

Higher Speed compared to 9LS/54LS and 9LS/74LS
SmA sink current over full military temperature
range
50mV improved VOL compared to 9LS/74LS
440llA source current
100% reliability assurance testing in compliance with
MI L-STD-883

PIN-OUT DIAGRAMS

25LS157

25LSI58
~ INPUTS
INPUTS
a:
OUTPUT
OUTPUT

14 13 12.11 10

Vee Ii;

@)

15

iA"4i 4V '3A'3i

15

13

9

9

16

2

3

4

5

14 1312 11 10

3V

15

9

16

8

8

7

7

6

2

7m

3

4

5 6

1234567m

SELECT lA 18 IV 2A 28 2V GNO

"--v-"QUTPUr--v--'OUTPUT
INPUTS
INPUTS

Die Size .047 x .066

SELECT 1A 18 tV 2A 28 2V GNU

~UTPUr--v--'OUTPUT
INPUTS
INPUTS

Die Size .047 x .066

LOGIC DIAGRAMS

25LS157

25LSI58

r-,

lA ..:.(2"')_ _ _ _ _ _ _ _ _-r""'""\

lA

lB (3)

lB

2A (5)

2A~(5~)_ _ _ _ _ _~~~r_,

2B..:.(6~)-------4-~_r~

28 - - -

~(2:!)_ _ _ _ _ _ _ _ _

(3)

(6)

3A (11)

3A

3B (10)

3B

4A (14)

4A

(11)
(10)

(14)

4B ....:(..:..:13~)_ _ _ _ _ __+_-I--i_....

4B (13)
STROBE G-':(1=:;5;.:.)_ _~p_cr"'""'\
SELECT S ~(.:.Jl....._ _+..q_J

STROBEG~(~15~)--~p-~~
..I.1.!..i)~--+--cjLJ

SELECT S

FUNCTION TABLE

3-28

STROBE

INPUTS
SELECT

A

B

hi

X

X

L

L

L

X
X
X

H

L

L

L

H

H

H

L

L

L

H

L

H

L

H

X
X

OUTPUT V
25LS157
25LS158

~

H

L

H

H = high level, L = low level, X
Low level at S selects A inputs
High level at S select~ B inputs

= don't care

Strobe is active low

CE 63.l
YTHE

Quadruple 2-Line-To-1-Line Multiplexers

25LS157 25LS158

Recommended Operating Conditions
Military

Supply voltage, Vee
H igh·level output current, IOH
Low·level output current, IOl
Operating free·air temperature, TA

COmmercial

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
-440
8
125

4.75

5

5.25
-440
8
70

4
-55

4
0

Unit

V
JlA
mA

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Test Conditions'

Parameter

Min

Military
Typ"
Max

2

VIH
Vil
VI

Vee=MIN,
Vee-MIN,
VIL =MAX,
Vee-MIN,
Vil =MAX

VOH

Min

Commercial
Typ"
Max

2
0.7
-1.5

11=-18mA
VIW2V,
low-440JlA
VIH-2V,
IIOl -4mA
IIOL -8mA

2.5

3.4

0.8
-1.5
2.7

3.4

Unit

V
V
V
V

0.40
0.25 0.40
V
0.45
0.35 0.45
S or G input
0.2
0.2
Vee=MAX,
VI=7V
II
mA
A or B input
0.1
0.1
S or G input
40
40
VI=2.7V
Vee=MAX,
IIH
JlA
A or B input
20
20
-0.8
S or G input
-0.8
VI=O.4V
Vee=MAX,
IlL
mA
A or B input
-0.4
-04
-15
-15
Vee=MAX
-85
lost
-85
mA
9.7
16
9.7
16
125LS157
Vee=MAX
mA
lee tt
I 25LS158
4.8
8
4.8
8
'For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
"AII typical values are at Vee = SV, TA = 2Soe.
tNot more than one output should be shorted at a time.
tt lee is measured with 4.SV applied to all inputs and all outputs OPen.
VOL

Switching Characteristics, Vee
Parameter
Test Conditions: CL

....!Eb.!i
tplH
tpLH

~
..!fill
tplH

From
(input)

= 5V, TA
To
(output)

0.25
0.3

= +25°C
+25°C
Min

Typ

Max

= 15pF, RL = 2kfi (See Fig. A, page 2-174)

25LS157

Data

Yi

5
7

10
12

25LS158

Data

Yi

25LS157

Strobe

Yi

7
5
13

12
10
20

8

16
12
17
20
20
lU
20

It PlH
25LS158
tpLH

Strobe

Yi

I tpLH
25LS157
tpLH

Select

Yi

It PlH 25LS158
t PlH

Select

Yi

~YTHEO]l

Unit

8
12
10
11

n
10

ns
ns
ns
ns
ns
ns

3-29

25LS160 25LS162
25LS161

25LS163

Synchronous BCD Decade Counters
Synchronous 4-Bit Binary Counters
PIN-OUT DIAGRAM

FEATURES
•
4-bit synchronous counters
• Synchronously programmable
•
Internal look-ahead counting
•
Carry output for n-bit cascading
•
Synchronous or asynchronous clear
•
Advanced low-power Schottky technology
•
100% reliability assurance testing in compliance with
MIL-STD-883
•
Higher speed compared to 9LS/54LS and 9LS/74LS
• 8mA sink current over full military temperature
range
•
50mV improved VOL compared to 9LS/74LS
440J.LA sou rce cu rrent
•

1 2 3 4 5 6 7 II]
CLEAR CK ~ P GND
ENABLE
DATA INPUTS
14

13

12

11

9

DESCRIPTION
The 25LS160, 25LS161, 25LS162 and 25LS163 synchronous, presettable counts have internal look-ahead carry and
ripple carry output for high-speed counting applications.
The 25LS160 and 25LS162 are decade counters and the
25LS161 and 25LS163 are 4-bit binary counters. Counting
or loading occurs on the positive transition of the clock
pulse. A LOW level on the load input causes the data on the
A, B, C and D inputs to be shifted to the appropriate Q
outputs on the next positive clock transition.
The 25LS160 and 25LS161 feature an asynchronous clear~
A LOW level at the clear input sets the Q outputs LOW regardless of the other inputs. The 25LS162 and 25LS163
have a synchronous clear. A LOW level at the clear input
sets the Q outputs LOW after the next positive clock transition regardless of the enable inputs.

3-30

10

15
16

8

7
2

3

Die Size .070 x .118 -

4

5

6

all 4 types

Both count-enable inputs P and T must be HIGH to count.
Count enable T is included in the ripple carry output gate
for cascading connection.

~YTHEO~

Synchronous BCD Decade Counters

25LS160

25LS162

Synchronous 4-Bit Binary Counters

25LS161

25LS163

LOGIC DIAGRAMS
25LS160
Synchronous Decade Counter
CLR
1
CL EAR 0--<9'''
CK 2
CLOCK

°A

DO

11

14

LOAO~~~~
EN P
EN T

RIPPLE
CARRY

25LS162 synchronous decade counters are similar; however, the clear is synchronous as shown for the 25LS163
binary counters.
25LS163 SYNCHRONOUS
BINARY COUNTER
CLR
CLEAR 0--.,-9-,

DA
14

DB
13

12

CLOg:~+-;>~-~---+--Jr--~--r---t---.

11

RIPPLE
CARRY

25LS161 synchronous binary counters are similar; however,
the clear is asynchronous as shown for the 25LS160 decade
counters.

~YTHE~

3-31

25LS160

25LS162

Synchronous BCD Decade Counters

25LS161

25LS163

Synchronous 4-Bit Binary Counters

Recommended Operating Conditions
Military
Min
4.5

Supply voltage, Vec
High-level output current, IOH

Nom
5

8
125

-5.5

,

Min

5.5
4.75
-440

4

low-level output current, IOL
Operating free-air temperature, TA

- Commercial
Max

Nom
5

Max
5.25

V

-440

f.l.A
mA

8
70

<:I

o~

Unit

Uc

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Test Conditions·

Min

Military
Typ··
Max

2

VIH

.

2

i!;:

0.7

VIL
VI
VOH
VOL

Vec-MIN,

11- 18mA

Vec-MIN,

VIH-2V,

~:5

VIL =VILmax, IOH= -440f.l.A
Vcc=MIN,
VIH=2V,
V IL =VILmax,

IIOL -4mA

0.25

IloL-8mA

0.35

Load, clock, or
enable T

Vec=MAX,

VI=7V

Clear (LS160,161
Clear (LS162,163
Data or enable P
Load, clock, or
IIH enable T
Clear(LS160,161

VCC=MAX,

VI=2.7V

Clear (LS1 62,163)
Data or enable P
Load, clopk, or
I!L enable T
Clear(LS160,161 )
Clear(LS1 62,163)

VCC=MAX

lost

VCC=MAX

ICCH

Vcc=MAX,
VcC=MAX,

JCCL

Vl=O_4V

-15
See Note 1
See Note 2

2.7

0.35

0.40
0.45

V

V

0.1
0.2

0.1
0.2
20

0.1

40

40

20
40
0.4

20
40
-0.4

-O.R

-0.8

-0.4
-0.8

-0.4

31
32

V

V

0.2

-85
18
19

3.4
0.25

0.40
0.45
0.1

Unit
V

0.8
-1.5

1.5
3.4

Data or enable P
Ii

Commercial
Typ~·
Min
Max

mA

0.2
20
f.l.A

rnA

-0.8
-15

-85
18
19

31
32

mA
mA
mA

'For conditions shown as MIN or MAX, use the appropriate value specified under recom~nded operating conditions for the applicable
device type.
.
. \ ,
-'All typical values are at Vee = 5V, TA = 25°C.
tNot more than one output should be shorted at a time.
NOTES:
1. IceH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open.
2. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outP~ts open.

3-32

~YTHEO!)

Synchronous 4-Bit Binary Counters

25LS160 25LS162

Synchronous BCD Decade Counters

25LS161

Switching Characteristics, Vee
Parameters

To

(Inputs)

(Outputs)

Teet Conditions: CL
tpLH

= 5V, T

From

A

+ 25°C

=

Clock
Clock (Load

tpHL

Input High)

tpLH

Clock (Load

tpHL

Input Low)

Carry

Enable T

Q

Q

Carry

tpHL
Clear

tpw

(Note 1)
Pulse Width

Set up time

ts

Q

Clock

25

Clear

20

Data A,B,C,D

20

ENABLE P

20

Load,
Enable T
Clear (Note 2)

th
f max

Typ

Max

I Unit

= 15pF, RL = 2kO (see Fig. A on page 2-174)

tpLH

tpHL

J

+25·C
Min

tpHL

tpLH

25LS163

Hold time

Any input

Maximum Frequency

25

35

20

35

10

18

15

20

10

18

14

20

15

20

9

14

14

28

ns
ns
ns
ns
ns
ns

ns

20
20

ns

3
30

40

MHz

NOTES:
1. Measured from clear input on 25LS160 and 25LS161. Measured from clock input on 25LS162
and 25LS163.
2. Applies to 25LS162 and 25LS163 only.

~YTHEO~

3·33

. Synchronous BCD Decade Counters

25LS160 25LS162
25LS161

Synchronous4-Bit Binary Counters

25LS163

TYPICAL CLEAR, PRESET, COUNT, AND INHIBIT SEQUENCES
CLEAR
25LS160

---"'lJ
,
LfI

(AYNSCHRONOUS)

CLEAR - - - - , ..~----------------------------------25LS162
(SYNCHRONOUS)

U ~----------------------

LOAD

DATA
INPUTS

{:~

~==

~r---r-----'[

CD

r-

---.,.--...;'0-

25LS160,25LS162

CLOCK
25LS160
CLOCK
25LS162

IIluslrated below is the following sequence:
1. Clear outputs to zero
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit

ENABLEP _____~~,~
ENABLET _ _ _~,-~:rl-+--------r----~----

OUTPUTS

{:~ ~ ~~==========~--'---------

QD===~----~~------:
i 1Il;:_-=---::--::+-:________
"

RIPPLE CARRY
OUTPUT

!7

I

:8

9

0

1

2

3:

~ COUNT---II--INHIBIT--

CLEAR PRESET

CLEAR
25LS161~~(~A~SY~NC=H~R=O=N~O~US=)------------CLEAR
I~~~~__________________

25LS163 ~

{

:

( A

DATA

:

,--

:

,--

!

B

INPUTS

(SYNCHRONOUS)

, Ur------------------

LOAD

'--

C-.J

D-.J

25LS161,25LS163

CLOCK
25LS161
CLOCK
25LS163
ENABLE P _ _---,;.-_+'

Illustrated below is the following sequence:
1. Clear outputs to zero
2. Preset to binaoy twelve
3. Count to thirteen; fourteen fifteen, zero,
one, and two
4. Inhibit

ENABLE T -----'c-_+'

QA= ==:
{ ==::L.j
--1.'_+__-'
:
......__-+'________
QD ==::ur,' --------"1..____-::____________
Q

OUTPUTS'

-

-

B-

-

~"f:--------

-,

Oc

RIPPLE CARRY
OUTPUT

:
:12 13 14

I I

...---

rlJ.--=--=-f-'________

15
0
2'
COUNT---Ilt---- INHIBIT-

CLEAR PRESET

3·34

~YTHEO:;J

Synchronous BCD Decade Counters

25LS160

25LS162

Synchronous 4-Bit Binary Counters

25LS161

25LS163

FIGURE 1
PARAMETER MEASUREMENT INFORMATION

I.

.I

tw(clock 1

I

3V

CLOCK
INPUT

I.....-...L- tPLH
I
I

OU~:UT

(measureatt n +11

~...Jl'3v

I

l.-.-t- tpHL
'
,

__

"'---..1- -

-

-

-

OV

I

I (measureatt n +2 1
I

~l

VOH

/
I--rI

VOL

)

I.---.+- tpHL
I

OU~:UT

I

(measure at tn+41

~S

I.....-....L
I
I

I

QC

I.
I
OUTPUT
QD

(measure at tn+81

~ tPLH

tpHL
I·
(measure at t n+10
ortn+16 1
I (See Note BI
1.3V
I

")
I
I
I ,..-_ _ _ _ _.., I

..-.J/

I 1 .3V
CARRY _ _ _ _
OUTPUT.

I

:.

\.

_

_

_

_

S

·1

-l:;~S

\

I'

VOH

______

VOL

tpLH
(measure at tn+8 1
VOH

1.3V

- - - - - - - -

tpHL
(measure at tn+O or tn+161
(Se Note BI

~_

__ VOL

(measure at t n +4 1

1~3V

"'

\S

VOH

r----t- tpLH

tPHL

~s

OUTPUT

RIPPLE

l ~3~

--....:..-------:....--, I '

,

tpLH
(measure at tn+21

)

- -- - -

_

_

_

_

VOL

_

VOH

VOL

VOL TAGE WAVEFORMS
NOTES:
A. The input pulses are supplied by a generator having the following characteristics: PRR '" MHz, duty cycle", 50%, Zout '" 50r!:
tr '" 15 ns, tf '" 6 ns. Vary PRR to measure f max .

B. Outputs Qd and carry are tested at tn+l 0 25LS162, and at t n +16 for 25LS 163 where tn is the bit time when all outputs are low.

~YTHEO~

3-35

Synchronous BCD Decade Counters

25LS160 25LS162
25LS161

Synchronous 4-Bit Binary Counters

25LS163

FIGURE 2
PARAMETER MEASUREMENT INFORMATION

t

CLOCK INPUT
25LS160
25LS161

CLEAR
INPUT

f

\1.3V

I

l

1.3V

I
..,- I·tw(clear)

Uy

- -

-

'-~~
i

- - _I I -l-- tsetup.-J

I ' - tsetup-:

DATA INPUT_S_ _
A,B,C, AND D

~_--:_ _ _ _ _ _.J~I' j

;r

\w.

I

--'tPHL.....

~?E~: OU»O)
25LS160

1.3V

i

-

-

-

-

-

-

-

-

-

-

- -

______ -__ -m

'11\
1

u_:
3V

- -

i\::1~~Y

LOAD
INPUT

___________

tw(clock) . ,

- 1:V- -

-

-

- -

-

- -

- -

- -

OV

:

-

-

1

3V
0v

-:tPLH-

: f"1-'~-V-_-_-_-_-_-_-_-_--_-_-_-

VOH

'----e.L- tPLH(measure at tn+2 or t n+4)

...., tPHL:--

~.

I'''' - - - - - - - - - - - -1.3V
_____:-___-:-...J't ____________
_

0B AND Oc OUTPUTS:
I
2 5 L S 1 6 0 \1.3V
~

:

3V
ENABLE P OR
ENABLE T
OV
VOH

RIPPLE
CARRY
OUTPUT
I
...

~~~~~~NPU~
25LS163
a OUTPUTS
25LS163
0A AND aD OUTPUTS
25LS162
OB AND Dc OUTPUTS
25LS162

f

1.3V

' \ 1.3V

--ltPHL......
I
I
I
:1

VOL

Ir ,._ _ _ _ _ _ _ _ _ _ _ _ __

tsetup~

\1

f

3V
1.3V

-1- -

-

--

~ ;L~i;e;;;.u;...;;t~2~r_;;,+_:;)-

--

!

-

-

-

-

-

-

-

-

-

-

-

~tPLH~,.------------

:.3V

•
-!tPHLl-

I
:

OV
VOH

1.3V

•

~1.3V
\

lr-------- ---

I

T

1.3V

_____________ _

VOL
VOLTAGE WAVEFORMS
NOTES:
A. The input pulses are supplied by generators having the following characteristics: PRR .; 1 MHz, duty cycle'; 50%, Zout '" 50 D.;
tr .; 15 ns, tf .; 6 ns.
B. Enable P and enable T setup times are measured at tn = O.

3-36

~YTHEO~

Synchronous BCD Decade Counters

25LS160 25LS162

Synchronous 4-Bit Binary Counters

25LS161

25LS163

TYPICAL APPLICATION DATA

N-BIT SYNCHRONOUS COUNTERS
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit count.r. The
25LS160 or 25LS162 will count in BCD and the 25LS163 will count in binary. Virtually any count mode (modulo-N, Nl-to
N2, N1-to-maximum) can be used with this fast look-ahead circuit.

INPUTS

INPUTS

INPUTS

INPUTS

~

,---A---...

~

~

LD A BCD

LD A BCD

LD A BCD

LD A BCD

H = COUNT
L= DISABLE

EN P

EN P

EN P

EN P

H = COUNT
L = DISABLE

RIPPLE
ENT CARRY
OUTPUT

RIPPLE
EN T CARRY
OUTPUT

RIPPLE
EN T CARRY
OUTPUT

RIPPLE
EN T CARRY
OUTPUT

~

'--v---'

'--v---'

'--.r---J

OUTPUTS

OUTPUTS

OUTPUTS

TO MORE
SIGNIFICANT
STAGES

CK

CLEAR

OUTPUTS

CLOCK

t;VTHEO]J

3-37

25LS170

FEATURES
• Separate Read/Write Addressing Permits Simultaneous
Reading and Writing
• Fast Access Times ... Typically 20 ns
• Organized as 4 Words of 4 Bits
• Expandable to 1024 Words of n·Bits
• For Use as:
Scratch-Pad Memory
Buffer Storage between Processors
Bit Stonlge in Fast Multiplication Designs
• Open-Collector Outputs with Low Maximum Off·State
Current: 20 JlA

4-By-4 Register Files with
Open-Collector Outputs
PIN·OUT DIAGRAM
25LS170

WRITE SELECT ENABLE
Vcc

~

OUTPUTS

DATA - - - - - - " - - - - D1
WA WB WRITE READ 01
02
15

13

12

11

D2

02

DESCRIPTION

---

[!]

The 25LS170 MSI 16-bit TTL register files incorporate the
equivalent of 98 gates. The register file is organized as 4
words of 4 bits each and separate on·chip decoding is provided for addressing the four word locations to either writein or retrieve data. This permits simultaneous writing into
one location and reading from another word location.

D3

D4

,

DATA

RB

RA

-..READ
SELECT

03

Q4

GND

OUTPUTS

Four data inputs are available which are used to supply the
4-bit word to be stored. Location of the word is determined
by the write-address inputs A and 8 in conjunction with a
write-enable signal. Data applied at the inputs should be in
its true form. That is, if a high-level signal is desired from
the output, a high level is applied at the data input for that
particular bit location. The latch inputs are arranged so that
new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the D
input is transferred to the latch output. When the writeenable input, GW, is high, the data inputs are inhibited and
their levels can cause no change in the information stored in
the l:ltcriial :atcheS~ \ftv'hBIl ih~ reau-enabie input, G R, is
high, the data outputs are inhibited and remain high.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a
word. When the read .address is made in conjunction with
the read-enable signal, the word appears at the four outputs.
This arrangement-data-entry addressing separate from dataread addressing and individual sense line-eliminates recovery times, permits simultaneous reading and writing,
and is limited in speed only by the write time (30 nanoseconds typical) and the read time (25 nanoseconds typical).
The register file has a nondestructive readout in that data is
not lost when addressed.
All inputs except the read enable and write enable of the
25LS170 are buffered to lower the drive requirements to one
Series 54LS/74LS standard load, respectively, input-c1amp-

3-38

13

14

15

16

2

3

4

Die Size: .090 x .068

ing diodes minimize switching transients to simplify system
design. High-speed, double-ended AND-OR-INVERT gates
are employed for the read-address function and drive highsink-current, open-collector outputs. Up to 256 of these
outputs may be wire-AN D connected for increasing the
capacity up to 1024 word7." Any number of these registers
may be paralleled to proviae n-bit word length.

~YTHEQ]J

4-By-R Register Files with
Open-Collector Outputs

25LS170

LOGIC
WRITE FUNCTION TABLE (SEE NOTES A, B, AND CI.
WRITE INPUTS

READ INPUTS

WORD

WB

WA

Gw

0

L
L
H
H
X

L
H
L
H

L
L
L
L
H

O=D

X

READ FUNCTION TABLE (SEE NOTES A AND OJ

Clo
Clo
Clo
Clo

1

Qo
Q=D
Qo

Clo
Qo

2

RS

RA

GR

01

02

03

04

Clo

L
L
H
H
X

L
H
L
H
X

L
L
L
L
H

WOB1
W1B1
W2B1
W3B1
H

WOB2
W1B2
W2B2
W3B2
H

WOB3
W1B3
W2B3
W3B3
H

WOB4
W1B4
W2B4
W3B4
H

Clo
Clo

Qo

Clo

Q=D
Qo

Q=D
Qo

OUTPUTS

3

Clo

NOTES: A. H = high level, L = low level, X = irrelevant.
B. (Q = Dj = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs.
C. Clo = the level of Q before the indicated input conditions were established.
D. WOB1 = The first bit of word 0, etc.

FUNCTIONAL BLOCK DIAGRAM

01 ('5~

('I

02

02

DATA
INPUTS

OUTPUTS

03 (21
03

04

(3)

(12)

Gw

~YTHEO:?J

3-39

4-By-R Register Files with
Open-Collector Outputs

25LS170

Recommended Operating Conditions
Commercial

Militarv
Min.
Supply voltage, Vee

4.5

Nom. Max.
5

High-level output voltage, VOH

5.5

Min.

Nom. Max.

4.75

5

5.25

5.5
4

Low-level output current, IOL
Width of write-enable or read-enable pulse, tw

8

5.5
4

8

Unit
·V
V
mA

25

25

ns

10

10

ns

15

15

ns

15

15

ns

5

5

ns

Data input with respect to
Setup times, high- or low-level data

write enable, tsu(D)

Write select with respect to
write enable, tsu(W)
Data input with respect to
Hold times, high- or low-level data

write enable, th(D)

(see Note 2 and Figure 2)

Write select with respect to
write enable, th(W)

Latch time for new data, tlatch (see Note 3)

25

25
-55

Operating free-air temperature range, T A

125

ns
70

0

°e

NOTES: 2. Write-select setup time will protect the data wri~ten into the previous address. If protection of data in the previous address is
not required, tsu(W) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during
th(W) will result in data being written into that location. Depending on the duration of the input conditions, one or a number
of previous addresses may have been written into.

3. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important only when attempting to read from a location immediately after that location has received new data.

Electrical Characteristics Over Recommended Operating Free-Air Temp. Range
(Unless Otherwise Noted)
Militarv
Test Conditions t

Parameter

Min.
VIH High-level input voltage

Commercial

Tvp~ Max.

VIL Low-level input voltage
VIK Input clamp voltage
IOH High-level output current

Vee = MIN,

11=-18mA

Vee = MIN,

VOH = 5.5V,

Min.

TVp;F Max.

Unit
V

2

2
07

Q.8

V

-1.5

-1.5

V

20

20

mA

VIL = VIL max, VIH = 2V
Vee = MIN,
IOL=4mA

VOL Low-level output voltage

0.25

0.4

VIH = 2V,
IOL =8 mA

0.25

0.4

0.35

0.5

V

VIL = VIL max
Input current at

II

maximum input voltage

Any D, R,orW
Vee = MAX,

VI =7V

High~level

IlL

Low-level input current

input current

Vee = MAX,

VI = 2.7V

Vee = MAX,

VI = O.4V

Vee = MAX,

See Note 6

0.2

20

20

40

40

-0.4

-0.4

-0.8

-0.8

mA

GR orGw
Any D, R, orW

mA

GR orGW
lee Supply current

0.1

0.2

mA

GR orGw
Any D, R, orW

IIH

0.1

25

40

25

40

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5V, TA = 25°e.
'
NOTE

3-40

4. lee is measured under the following worst-case conditions: 4.5 V is applied to all data inputs and both enable inputs, all address inputs are grounded r and all outputs are open.

~YTHE~

4-By-R Register Files with
Open-Collector Outputs
Switching Characteristics, Vee
Parameter

=

25LS170

5V Over Recommended Free-Air Temperature Range
+2SoC

From

To

(Input)

(Output)

Typ

Min

Max

Unit

Test Conditions: C,

= 15pF, R, = 2kO (See Fig. 1, page 3-41 and Fig. B, page 2-174)

tpLH

Read

tpHL

enable

tpLH

Read

tpHL

select

tpLH

Write

tpHL

enable

tpLH

20
20

Any Q

Any Q

25

40
24
30
26
30
22

Any Q
Any Q

Data

tpHL

30
30
40
45
40
45
35

ns

ns
ns
ns

PARAMETER MEASUREMENT INFORMATION

WRITE·SELECT
INPUT WA or WB
(See Note AI
DATA INPUT
01,02,03 or 04
(See Note AI
WRITE·ENABLE
INPUT GW
REAO·SELECT
INPUT RA or RB
(See Note BI

.r-------~----------------3V
~--------------IOV

.-r=;.:....------03'V
1'-~~~~~---------3V
~,~~~-----------OV

g~T~T03

or 0 4 i r M

\

W~IT~.ENABLE

~.-------------

//,.------.....
.

INPUT GW

---+1-.-."'l'I:':'P':"LHOA TA INPUT
01, 02, 03 or D4

1'----J,-------------------3V

}v

Vnof

~tp::L::H----

\l1\;Vnof

f

re

VOLTAGE WAVEFORM 1

I,-----"",-------OV

/

'--------3V
,,-----OV

REAO·ENABLE
INPUT GR

1~--~~+-------3V

VOH

OUTPUT

DATA INPUT
01,02,03 or 04

01.02,03 or 04

FIGURE 1

FIGURE 2

NOTES: A. High·level input pulses at the select and data inputs are illustrated in Figure 1; however, times associated with low-level pulses

are measured from the same reference points.
B. When measuring delay times from a read-select input, the read-enable input is low. When measuring delay times from the
read-enable input, both read-select inputs have been established at steady states.
C. In Figure 2, each select address is tested. Prior to the start of each of the above tests, both write and read address inputs are
stabilized with WA = RA and WB = RB. During the test GR is low,
D. Input waveforms are supplied by generators having the following characteristics: PRR ..;; 1 MHz, Zout '" 50 n, duty cycle ..;;
50% tr:S;;; 15 nsand tf ~ 6 ns for.
D. V re f=1.3V,

ri.AVTHEO:?J

3-41

25LS174

Hex 0-Type Flip-Flops With Clear

25LS175

Quadruple D-Type Flip-Flops With Clear
PIN-OUT .DIAGRAMS

FEATURES

•
•
•
•
•

Positive edge-triggered common clock
Asynchronous common reset
Clock-to-output delays of 14 ns
Higher speed compared to 9LS/54LS and 9LS/74LS
8mA sink current over full military temperature
range
50mV improved VOL compared to 9LS/74LS
440ILA source current
100% reliability assurance testing in compliance with
MI L-STD-883_

•
•
•

25LS174
50 50 40 40

CLR 10

DESCRIPTION

15

The 25LS174 is a six-bit register with single-rail outputs
and the 25LS175 is a four-bit register with complementary
outputs. Both consist of D-type flip-flops with a buffered
common clock and an asynchronous, active-Low buffered
clear.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at a·
particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock
input is at either the high or low level, the D input signal
has no effect at the output.

0

0

ot

x

X

L

H

H

H

H

L

H

t
t

L

L

H

H

L

X

00

00

12 11 10

9

8
7

3

Die Size .056 x .085 2

4

5

6

25LS175
15 14

13

3D 30 30 CK

12 11 10
9

16
8

tii:ilfa:cEl7

OUTPUTS

L

CLEAR CLOCK

13

16

FUNCTION TABLE (EACH FLIP-FLOP)
INPUTS

14

2

3

4

5

6

CLR 10 10

Die Size .056 x .085

20 20 20 GN[J

H = high level (steady state)
L = low level (steadv state)
X ::: irrelevant
t == transition from iaw to high level
00 = the level of Q before the indicateo steady state
input conditions were established.

t

=

LOGIC DIAGRAMS

25LS174

.25LS175 onlv

60
CLOCK 9~~~____~__~______~~~______.--+~

____~~~~____-t__~~____~

CLEAR ~l)()---------t~~~-----;~--~----~~--~------~~~------~~

10

50

40

30

60

25LS175
CLOCK

9

CLEAR

20

3-42

3d

4d

40

~YTHEO~

Hex 0-Type Flip-Flops With Clear

25LS174

Quadruple D-Type Flip-Flops With Clear

25LS175

Recommended Operating Conditions
Commercial

Military

Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Clock frequency, f clock
Width of clock pulse, tw (Low)
Width of clear pulse, tw (Low)

Nom

Max

Min

Nom

Max

4.5

5

5.5
-440
8

4.75

5

35

.0
15
20
10
12
5
0

5.25
-440
8
35

V
p.A
mA
MHz
ns
ns
ns
ns
ns

70

°c

4

I Data input t setuD

Setup time

t Clear recovery, tree

Data hold time, thold
Operating free-air temperature, TA

Unit

Min

0
15
20
10
12
5
-55

125

4

tsetup is the minimum time required for the correct logic level to be present at the data input prior to the rising edge of the clock in order to
be recognized and transferred to the output.
thold is the minimum time required for the logic level to be maintained at the data input after the rising edge of the clock in order to insure
recognition.
tree is the minimum time required between the end of the clear pulse and the rising edge of the clock in order to transfer High data to the Q
output.

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)

V IH
V IL
VI

Commercial

Military

Test Conditions'

Parameter

Min

Typ"

Max

II
IIH

11=-18mA
VIH=2V, VI=VIHor VIL
low-44Op.A
VIH-2V,
IIOL -4mA
VI=VIHor VIL I'OL =8mA
VI=7V
VI-2.7V

IlL

Vee=MAX,

VI=O.4V

lost

Vee=MAX

V OH
VOL

lee tt

Vee=MAX

I

Max

0.7
-1.5
2.5

0.25
0.35

16
11

25LS174
25LS175

0.8
-1.5
2.7

3.4

-15
I

Typ"

2

2
Vee=MIN,
Vec=MIN,
VIL =VILmax,
Vee-MIN,
V IL =VILmax
Vee-MAX,
Vee-MAX,

Min

0.40

-0.36
-85
26
18

0.40
0.45
0.1
20

-15
16
11

V
V
V
V

3.4

0.45
0.1
20

Unit

-0.36
-85
26
18

V
mA
p.A
mA
mA
mA

*For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable

device type.
'"AII typical values are at Vee = 5V, T A = 25'e.
tNot more than one output should be shorted at a time.
ttWith all outputs open and 4.5V applied to all data and clear inputs, lee is measured. after a momentary ground. then 4.5V is
applied to clock.

-

Switching Characteristics , V'cc -- 5V Over Recommended Free Air Temperature Range
From
(Input)

Parameter
Test Conditions:

CL =

f max
tpLH (LS175 onlv)
tpHL
tpLH
tpHL

~YTHE03'l

15pF,

RL

To
(output)

+ 25'C
Min

Max

= 2kO (See Fig. A, page 2-174)
35

Clear
Clear
Clock
Clock

Typ

Unit

Q
Q
Q
Q

45
19
20
14
13

25
35
23
20

MHz
ns
ns
ns
ns

3-43

4-Bit Arithmetic Logic Unit

25LS181

FEATURES
•
•
•
•
•
•
•
•

The 25LS181 will accommodate active-high or active-low
data if the pin designations are interpreted as follows:

Provides 16 arithmetic operations
Provides 16 logic operations
Full look-ahead for high-speed arithmetic operation
on long words
Higher speed compared to 9LS/54LS and 9LS/74LS
SmA sink current over full military temperature
range
50mV improved VOL compared to 9LS/74LS
440IlA source current
100% reliability assurance testing in compliance with
MIL-STD-883_

Subtraction is accomplished by l's complement addition
where the 1 's complement of the subtrahend is generated
internally. The resultant output is A-B-l which requires an
end-around or forced carry to provide A-B.
The 25LS181 can also be utilized as a comparator. The
A = B output is internally decoded from the function outputs
(FO, Fl, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high
level to indicate equality (A = B). The ALU should be in
the subtract mode with Cn = H when performing this comparison. The A = B output is open-collector so that it can
be wire-AND connected to give a comparison for more than
four bits. The carry output (C n+4) can also be used to
supply relative magnitude information. Again, the ALU
should be placed in the subtract mode by placing the
function select inputs, S3, S2, Sl, SO at L, H, H, L,
respectively.

DESCRIPTION
The 25LS181 is an arithmetic logic unit (ALU)/function
generator which has a complexity of 75 equivalent gates on
a monolithic chip. This circuit performs 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and
2. These operations are selected by the four function-select
lines (SO, Sl, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic
manipulations, the internal carries must be enabled by
applying a low-level voltage to the mode control input (M).
A full carry look-ahead scheme is made available in these
devices for fast, simultaneous carry generation by means of
two cascade-outputs (pins 15 and 17) for the four bits in
the package. When used in conjunction with the 182, full
carry ahead look-ahead circuits, high-speed arithmetic
operations can be performed.

INPUT

OUTPUT

Cn +4

ACTIVE-HIGH OATA

ACTIVE-LOW DATA

IFIGURE 11

IFIGURE 21

H

H

AB

H

L

L

H

A>B
A  B

L

L

A-,B

A",;;B

A$

II

(3) (4)

(1) (2)

y

(11) (13)

(1) (2)

(13)

(11)

(9)

(12)

FIGURE 1
(FOR TABLE 1)

M-H

en = H

FUNCTIONS

Inocarryl

L

L

L

F·II

L

L

H

F

L

L

L

H

L

H

H

L

H

L

"A+'B

ACTIVE·LOW DATA.

Cn = L
(nocarryl

SelECTION

LOGIC

53 52 S, So

FUNCTIONS

L

l

L

L

F . A

L

L

L

H

F

F " (A + II PLUS 1

L

L

F " ZERO

L

~

F =A

F

F = A'" 8

F " (A + Bl PLUS 1

A PLUS 1

AJj

A-.

F = AS

F = A + '§

H

L

F

F-O
F • All
F-II

L

H

H

F=l

F = A PLUS A'§

F = A PLUS AS PLUS 1

H

L

L

F

F " (A .;. BI PLUS AS

F " (A + 81 PLUS A'a" PLUS 1

H

L

H

F=B

F = A MINUS B

F

~

(10)1

TABLE 2
M=H

M = L; ARITHMETIC OPERATIONS

LOGIC

L

G

MINUS 1 12', COMPU

(9)

(11)

ACTIVE-HIGH OAT A

L

(7)

FIGURE 2
IFOR TABLE 2)

TABLE 1

So

P

Cn +x

(12)

53 52 S1

(5) (6)

(14) (15)

54182

en

Cn +x

SELECTION

(17) (15)

(16)

171

(10)

(14)

A=B

II

(3) (4)

54182

en

(10)

I

(5) (6)

(14) (15)

X
(13)

(7)
(14)

M

(9)

(19) (18)

(23) (22) (21) (20)

=A7B

A19"B

M'" L; ARITHMETIC OPERATIONS

Cn

Cn '" L
Iwithc.arry)
F

A. MINUS 1

F

~

H

A.

F " AS MINUS 1

F "AS

F = ABMINUS 1

F - A"§

F - MINUS 1 C?'s COMP}

'"

Iwithcarryl

F "ZERO

F - A. PLUS IA +!')

F = A PLUS (A. + 11) PLUS 1

F = AB PLUS (A. + H)

F " AS PLUS (A + H) PLUS 1

L

H

H

L

F =

F " A. MINUS B MINUS 1

F "A MINU5 B

L

H

H

H

F=A+!'

F=A+fi

F = tA + 9") PLUS 1

H

L

L

L

F = AS

F " A PLUS tA + BI

F = A PLUS (A. + BI PLUS 1

F " A PLUS B PLUS 1

H

L

L

H

F =A0B

F " A PLUS B

F" A'PLUS B PLUS 1

L

H

H

F=A(3B

F = A MINUS B MINUS 1

L

H

H

H

F "'AI

F" AIMINUS 1

F = AD"

H

L

L

L

F =

F "A PLUS AS

F

H

L

L

H

A'+ B
F'~

F = A PLUS B

~

A PLUS AS PLUS 1

L

H

L

F " (A ... 11 PLUS A8

F = (A + II PLUS AS PLUS 1

H

L

H

L

F "B

F " A!' PLUS IA + BI

F = All PLUS IA + 81 PLUS'

H

L

H

H

F" AS

F = AS MINUS 1

F = AS

H

L

H

H

F=A+B

F=A+8

F ... IA + BI PLUS 1

H

H

L

L

F' ,

F=APLUSA*

F=APLUSAPlUSl

H

H

L

L

F=0

F=APLUSA-

H' L

F=A ... II

F .. (A + 81 PLUS A

F " fA ... 81 PLUS A PLUS 1

H

H

L

H

F "AD"

F

H

H

f=A"'B

F = IA ... 1) PLUS A

F = IA ... !') PLUS A. PLUS 1

H

H

H

L

F" AS

F

H

H

F=A

F '" A MINUS 1

F=A

H

H

H

H

F-A

F=A

H

H

H

F =B

= A.S P'LUS A
= A"lPLUS A

F '" A PLUS A PLUS 1
F = AS PLU5 A PLUS 1
F " A.1i PLUS A. PLUS 1

F =·A PLUS 1

• Each bit is shifted to the next more significant position.

~YTHEOFJ

3-45

4-Bit Arithmetic Logic Unit

25LS181

LOGIC DIAGRAM
S3
S2
S1

(3)
(4
(5)

SO~

83 ~

A3

82

~

(19)

.!3.21.

H>

J

w-

~

(17)

~

1
j

...

" - - F:::::l

n

GOR Y

(16)

(15)

.r

\

POR X

(13)
F3

r.JL/

~
J

A2

(21 )

81

!El.

~

~

~

-

.1 J
A1

.!.!L

t-------'(""13,,-) RIPPLE

(5)

DOWN/UP

CLOCK

-

1

(12) MAX/MIN
> - - - + - +......----.....:...:.=:. OUTPUT

DATA~(1~5~)~+-I_ _ _ _~+-~~_~~-r~

~

INPUT A

~."

I-

ENABLE G ....:.(4.;..:.1-+-.--_--1f-+_+-t---1_

TI-I-I-

A
~-+- ~RESalt--........(3_1 OUTPUT QA
_+_-~- - - -.......---+-~·-'6
-

...-t-+_+_-t--+~-1~f---,'-'--""'\
,,-+--_..r - ~

.......:>CK
'--

IJ
LllJd~=E~~§---~~~--~J
DATA
INPUTC

PRESET
(21
J
QB~-=-OUTPUT QB

~LEA~B-

y

....:.(_10~)_ _ __+_+-~-+-+--~~~--1~r-,~~+-_......._ __+_-~

I

r

Ji
____ ~RES~~

~~>+--.. ~>CK
~W-+-I-~~=++=~L)

-- r--

(6) OUTPUT Qc

~LEAW: f-If

DATA
INPUT D

_(9~1----+-r;-~r+-r;-+4-+--~J~'P-_ _......._ _-r_--,
- ---t

(111
LOAD

~YTHEO]J

1

--..../

>-__+-~~______________~~~f

PRESET
(71
-f-- J
QDI-.......""""'OUTPUT QD
L....cI>CK

'---- K

QD-

CLEAR

I

3-53

25LS190

Synchronous BCD Decade Up/Down Counter

25LS191

Synchronous 4-Bit Binary Up/Down Counter
LOGIC DIAGRAM
25LS191

CLOCK

(14)
(5)

DOWN/UP

I~

DATA (151
INPUT A

ENABLE G

(4)

I

~+

TI-

-I

r-

rP

'-

r

(12)

MAX/MIN
OUTPUT

(31

PRESET
QA

I-- J

OUTPUT QA

~ ~CK

1-1-

L.-

I--

K
OA ~
CLEAR

Y

(11

I

'-

n

J

-

-

I--

K
OB
CLEAR

h
DATA (10)
INPUT C

-

1

OUTPUT QB

-

r-

'--

n

-

'1'

'-

I-f--I

(9)

(2)

PRESET
QB

I-- J

~ ~CK

r

DATA
INPUT D

RIPPLE
CLOCK

J..
~

-...../
DATA
INPUT B

(13)

-

A
PRESET
J
Qc

~

>CK

-

K
Oc
CLEAR-

y

~
f

I

(6)

OUTPUT Qc

-

1

....

---t

.-- I--

PRESET
QD
J

(7)

OUTPUTQD

L..c:: t>CK

LOAD

3-54

(~

n

' - - - I~l

QD~
EAR

'1'

t;VTHEO]J

Synchronous BCD Decade Up/Down Counter

25LS190

Synchronous 4-Bit Binary Up/Down Counter

25LS191

25LS190 TYPICAL LOAD, COUNT AND INHIBIT SEQUENCES
Illustrated below is the following sequence.
1.
2.
3.
4.

Load (preset) to BCD seven.
Count up to eight, nine (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum), nine, eight, and seven.

LO{A:X,-=
,
,

B
DATA
INPUTS

'
I
~L.._
, ,

CJ::L

=

o~=
CLOCK

ENA8lE'L+-.c..;..._ _ _ _~

;

aD==~~

I

IIL.._ _ __

"
MAX/MIN:::~

~~~~:=:::,~
u
:7:189012212110987
UI--COUNT

UP~NHIBIT..f

I--COUNT

OOWN~

LOAD

25LS191 TYPICAL LOAD, COUNT AND INHIBIT SEQUENCES
Illustrated below is the following sequence:
1.
Load (preset) to binary thirteen.
2.
Count up to fourteen, fifteen (maximum), zero, one, and two.
3.
Inhibit.
4.
Count down to one, zero (minimum), fifteen, fourteen, and thirteen.

j

lOAD~

Ast:'..:=

---+--+.r= =

OAT A

B

INPUTS

c~~=
D~~=

ENABLEIL,....-'c-_ _ _---!

.
,
Oc:::r~
MAX/MIN ::~

~~'6i: : =~13.:: 14

15

0

1

2

·2 :2: 1

UI--COUNT UP --kNHIBITJ

0

15

14

13

J---COUNT DOWN---I

LOAD

[[AYTHEOE]

3-55

25LS190

Synchronous BCD Decade Up/Down Counter

25LS191

Synchronous 4-Bit ~inary
Up/Down Counter
,
.

PARAMETER MEASUREMENT INFORMATION

DATA
INPUT

......
'

-<10 NS

'~~------",~

(SEENOT~~~

LOAD
foetup: 1.3V~
INPUT
10%
(SEE NOTE A)

"-"o.:..:......,......_----oV

,-;:,=--,

OUTPUT
NOTE:
A. The inputs pulses are supplied by generators having the foilowing characteristics: Z~~t = 50n, duty cycle

<; 50%, PRR

< 1 MHz.

FIGURE l-DATA SETUP TIME VOLTAGE WAVEFORMS

LOAD

,~'-------------------,,

ANY DATA INPUT _ _ _ _ _ _ _ _.....
CORRESPONDING ____-_-_- _-_'..
, ______-'-.....1
QOUTPUT

'

tpLH ~

:...

:

~I

I

I

--:

I

____-'--!I
I

: - tpHL

tpLH ~

:, 1------...,

I

~

-'

:-- tPHL

NOTE: Conditions on other inputs are irrelevant.

FIGURE 2-LOAD TO OUTPUT AND DATA TO OUTPUT

LOADU

,~

DOWN/UP
CLOCK
ENABLE G

I,

I,

: :
I

tPHL-:

I

I-

-: :- tpLH

I

I

tPHL-:

-

-'I

: - tPLH

,, r
tpLH-I r-tpHL
.....
M A X / M I N - - - - - - - - - - - - - - - - - - - - , I I;-- - = " ' - j

RIPPLE CLOCK

LI_ _ _ _

~I

:

I

L

NOTE: All data inputs are low.

FIGURE 3-ENABLE TO RIPPLE CLOCK, CLOCK TO RIPPLE CLOCK, DOWN/UP TO MAX/MIN

3-56

~YTHEii!J

Synchronous BCD Decade Up/Down Counter

25LS190

Synchronous 4-Bit Binary Up/Down Cpunter

25LS191

PARAMETER MEASUREMENT INFORMATION (Continued)

u

LOAD~

-_----'-I ___ _

DATA INPUTS__- __
-_
-_-_-_-___
- ____
(SEE NOTES G TO I)

I

DOWN/UP

U

W

COUNT
I
(S)
- : '-- tPLH
OUTPUT
- - ..,
,
UNDER TEST ___ 'i.-_ _ _ _ _ _-'

I

:
:-- tPHL
r------------'---i
l

1..._ _ _ _ _ _ _ __

ENABLE = LOW
NOTES:
F. To test QA, QB, and QC outputs of 25LS190: Data inputs A, B, and C are shown by the solid line. Data input 0 is shown
by the dashed line.
G. To test QD output of 25LS190: Data inputs A and 0 are shown by the solid line. Data inputs Band C are held at the low
logic level.
H. To test QA. QB. Qc, and QD outputs of 54LS191: All four data inputs are shown by the solid line.
FIGURE 4-CLOCK TO OUTPUT

u

LOAD--U
DATA A

--JI _________ _

DAT~:ECN~~~ J~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-DOWN/UP
COUNT

l::!--JI

:-tPLH

ld,

MAX/MIN_ _ _ _ _
ENABLE = LOW

NOTE I:
Data inputs Band C are shown by the dashed line for the 25LS190 and the solid line for the 25LS191: Data input 0 is shown
by the solid line for both devices.
FIGURE 5-CLOCK TO MAXIMIN

r§YTHEO]J

3-57

25LS192

Synchronous BCD Decade Up/Down Counter

25LS193

Synchronous 4-Bit Binary Up/Down Counter

FEATURES
•
Separate clock inputs for count-up, count-down
•
Asynchronous parallel load and clear
•
Cascadable
•
Higher speed compared to 9LS/54LS and 9LSn4LS
•
8mA sink current over full military temperature
range
•
50mV improved VOL compared to 9LSn4LS
•
440J,IA source current
•
100% reliability assurance testing in compliance with
MIL-STD-883.

PIN-OUT DIAGRAM
OUTl'U"TS
INPUTS ~ INPUlS
r--"--- CI > r-K-----,
DATA a: ~ ~ ~ DATA
Vee A ;:j 1il <3 ::: e 0
[ill 15 14

DESCRIPTION
These monolithic circuits are synchronous reversible (up/
down) counters having a complexity of 55 equivalent gates.
The 25LS192 is a BCD counter and the 25LS193 is a
4-bit binary counter. Synchronous operation is provided
by having all flip·flops clocked simultaneously so that the
outputs change coincidently with each other when so
instructed by the steering logic. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple-ciock) counters.
The outputs of the four master-slave flip-flops are triggered
by a low-to-high-Ievel transition of either count (clock)
input. The direction of counting is determined by which
count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each
output may be preset to either level by entering the desired
data at the data inputs while the load input is low. The
output will change to agree with the data iAputs independently of the count pulses. This feature allows the counters
to qe used as modulo-N dividers by simply modifying the
count length with the preset inputs.
A clear input has been provided which forces all outputs to
the low level when a high level is applied. The clear function
is independent of the count and load inputs. The clear,
count, and load inputs are b"uffered to lower the drive
requirements. This reduces the number of clock drivers,
etc., required for long words.
These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up- and down-counting
functions. The borrow output produces a pulse equal in
width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal
in width to the count-down input when an overflow condition exists. The counters can then be easily cascaded by
feeding the borrow and carry outputs to the count-down
and count-up inputs respectively of the succeeding counter.

3-58

Low input to load sets OA = A, O. = B,
Oc = C, and

aD = D

25LS192

16

9

8

2

7

5

4

3

6

25LS193

14

15

13

12

11

10

16

9

8

2

7

3

4

5

6

Die Size: .100 x .077 Iboth types)

~YTHEO~

Synchronous BCD Decade Up/Down Counter

25LS192

Synchronous 4-Bit Binary Up/Down Counter

25LS193

Recommended Operating Conditions
Min
Supply voltage, Vee
High-level output current, IOH
Low-level output current, IOL
Count frequency, fcount
Width of any input pulse, tw
Data setup time, t setup (see Figure 1)
Data hold time, thold
Operating free-air temperature range, TA

4.5

Military
Nom
Max
5

5.5
-440
8
25

4
0
20
20
0
-55

125

Commercial
Min
Nom
Max
4.75

5

4
0
20
20
0
0

5.25
-440
8
25

70

Unit
V
JJ.A
mA
MHz
ns
ns
ns

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter
V,H
V ,L
V,

Min

Military
Typ"
Max

Vee=MIN,
Vee-MIN,
V IL =V,Lmax,
Vee-MIN,
V IL =V,Lmax
Vee-MAX,
Vee-MAX,
Vee-MAX,
Vee-MAX
Vee-MAX

VOL
I,

Commercial
Typ"
Max

0.7
-1.5

1,=-18
V'H-2V,
IOH =- -440JJ.A
V'H~2V,

Min
2

2

VOH

I'H
I,L
lost
lee tt

Test Conditions'

2.5
l'oL -4mA

l' oL -8mA

0.25

0.40

0.30

0.45
0.1
20
-0.4

--15

..

..

19
.

2.7

3.4

V ,-7V
V,-2.7V
V I -D.4V

0.8
-1.5

-85
34

3.4
0.25
0.30

-15
19

..

Unit
V
V
V
V

0.40
0.45
0.1
20
-0.4
-85
34

V
mA
JJ.A
mA
mA
mA

*For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditIOns for the applicable

device type.
"All typical values are at Vee ~ 5V, 'r A

=

25°e.

t Not more than one output should be shorted at a time.
tt1cc is measured with all inputs grounded and all outputs

open.

Switching Characteristics, Vee = 5V Over Recommended Free-Air Temperature Range
+25°C
From
To
I
Unit
(input)
(output) I Min I Typ I Max I
Test Conditions: C, - 15pF, R, - 2kO
(See Fig. 1 & 2 on page 3-62 and 3-63 and Fig. A, page 2-174)
Parameters

f max
tPLH
tPHL
tpLH
tPHL
tpLH
tPHL
tPLH
tpHL
tpHL

[[AYTHEO]J

25

35
9
17
9

Count-up

Carry

Count-down

Borrow

Either Count

Q

Load

Q

19
20
22

Clear

Q

23

17

29

MHz
18
24
18
24
30
32
33
40
33

ns
ns
ns
ns
ns

3-59

25LS192

Synchronous BCD Decade Up/Down Counter

25LS193

Synchronous 4-Bit Binary Up/Down Counter
LOGIC DIAGRAM
25LS192

(3)
1

SORROW
OUTPUT

(12)

DATA

(15)

DOWN
COUNT
UP
COUNT

DATA

CARRY
OUTPUT

..--..

INPUT A

~

r'----'"
(4)

"

v
(5)

QA
T

P

"v

~

(1 )

"\.
f"\---/

INPUT S

Qs
T

'----

-1)..
DATA

h

rl./

OUTPUT Qs

]

---'

,....A-

~
.........
[>oJ

~

-

(6)

OUTPUT Qc

~

If-~
'\,

ii4;

Qc
T

D

(9)

INPUT D

CLEAR

(2)

(10)

INPUT C

DATA

OUTPUT QA

Jr
r-A-

~

(3)

l

(7)

OUTPUT QD

DO

LOAD

3-60

(11)

.Jo>.
-yo

t;YTHEc3l

Synchronous BCD Decade Up/Down Counter

25LS192

Synchronous 4-Bit Binary Up/Down Counter

25LS193

LOGIC DIAGRAM
25LS193
(13) BORROW
OUTPUT

f

(12)

DATA
INPUT A

(15)

DOWN
COUNT

(4)

UP
COUNT

DATA
INPUT B

.........
["1...J

1:

'"
(5)
,...
--v

CARRY
OUTPUT

(3)

OUTPUTOA

T

h

(1 )

rt--r

~

~
r-L
OB

(2)

OUTPUTOB

T

]
D

-'"

DATA
INPUT C

(10)

..r--"\.
../

{-

(6)

i f J}
D

OUTPUTOC

T

DATA
INPUT 0

(9)
(14)

CLEAR

LOAD

~YTHEO]l

(11)

.r-'\.

~

~b
~

1
00
T

(7)

OUTPUT 00

J;H
3-61

25LS192

Synchronous BCD Decade Up/Down Counter

25LS193

Synchronous 4-Bit Binary Up/Down Counter
PARAMETER MEASUREMENT INFORMATION

1

r--------- --------,
I
I
.. .. ... I
! l
~

T

-

DATA

PUlse

BORROW

OPEN

A

CARRY

OPEN

•

°A

C

0.

~ > DOWN

rL {

GENERATOR
(See Note AI
CLEAR
PULSE
GENERATOR
(See

>UP

I

Note AJ
LOAD
PULSE
GENERATOR
(See Note Al

I

I

0

Dc -r-<

CLEAR

00

I

ISe:-Nol;"CI

I

c

I
I
I

I J'~NO"B'

----<

I
-= I
L _____ ..!-~~~~~:.~ ____ _J

LOAD

-=-

I
I

RL

-:!-

r-----~~;;~~~-----

L __________________
(Same as lOild CIrCUli 1)

-,
I

_I
-.

r-----------------____
r-- -- ------------ .,

~

L _____

I

LOAD CIRCUIT 2

I

(!!r:!!.::'!';c.:t~l

_ I
I

LOAD CIRCUIT 4

L ____ ~:: :.l:,ad':J::\I:,l~ ____ ~

f--

t,-1
I

CLEAR

I

INPUT

I

INPUT

Q

OUTPUT

I

: Jf90%90%'k~--________________________________________________________
- - - - - - - - - - - --- - - - - - - --- - - - . .-.
I

'"

I

-+l f+- t,
I

-+I

I

I

10%

~~~:up;

;I

1.3V

-

-

-

-

-

-

-

-

-

-

-

~
~
I

1.N

G\i

},Ie.l!~9~0~%~---------

3V

10%£1-

--.

t.- tPHL

3V

I

~tsetup~

----""'i-I--------~90~"k;.:o;;!l1$..l
1.3~ ~O%
-+f tPHL I+~ 10% 10%'1
I
I
-...l 14- t,
I
14--- tpLH·
.. ,
,

~

I-- tf

}.Tt!!1~.;~O;:~'. -------------------~9~10~~~~UI
~ ~O: ---""'i-------.;.;;~~ 1 .
'l'c
:

3V

_,_~1Q~o/c~"

I

LOAD

f-tf

~1.3V

I

DATA

TEST CIRCUIT

~

't:.= t-;- -

1.3V

- - - -

.1 _____

~

OV

VOH
VOL

VOLTAGE WAVEFORMS

NOTES:
A. The pulse generators have the following characteristics: Zout = 50.11 and for the data pulse generator PRR
50%; for the load pulse generator PRR is two times data PRR, duty cycle = 50%.
B. CL includes probe and jig capacitance.
•
C, Diodes are 1 N3064.
D. tr and tf ..; 7 ns.
FIGURE 1 -

3-62

< 500KHz, dutY cycle =

CLEAR, SETUP, AND LOAD TIMES

~YTHEOEJ

Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter

25LS192
25LS193

PARAMETER MEASUREMENT INFORMATION (Continued)

r-------------.,
I
"L
I

'ULSf
GENERATOR

..,."OW~_+~~--~~~_1~~

CS-Nott""

__--~~__~~__,

CARRY H-+-+-+-~

51

I
I

Q.H-++~

a"

••

I

a.::

...
IL _______________
lOAO CIRCU'T t
!

00

elUR

I
I
I

'-------+--<1 lOAD

~----------------,

LOAD CIRCUIT!)
L ________________
- '•

(S. ..... lOllll C."tv,11)

•

~---~------------~
lOAOCIACUIT,
•

' -__________-.;.

L ____

If

COUNT
UP
INPUT
(See Note 0)
OUTPUT
QO
(See Note E)

"\.

1

-.I ~ !+- I,

J90~iLTlJd h.

.:..S.:;.!;~;:=t.!'

____ J

TEST CIRCUIT

~

8

9

,I, h.

15

~

16

" " ; . ; - - 3V
___ ov

~~~';,~., ~1.3V\.!./" \.:./1.3V~~

I

I
~

I

_____________oJf

I

I

,..-'PLH

I
'VOH

I
I!t
I~I

I

:

1.3V

--J

~

VOL

J+:tPHL
- -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
___,. .~I
I
VOH
tpHL
!.-tPLH
CARRY
OUTPUT

~OO~:

INPUT
(See Note D)
OUTPUT
QO
(See Note E)

1.3V

tf

,

1.3V
- - - VOL

r---

-.l4..t 14- t,

~:_~_~h.\.!.Jrl.3V~
_~
Ai\. .. ~ ..
~9~~~
~1.3V~~.3V
_

n

••

%

,.

I

-1 r-

tPHL

- - - - - - -__________________'\ I

\ ; 1.3V
•

I
I

Ii
I

I

T----

~tPLH

I

I ~ 1.3V

wr _ _

..-I

tPHL~1
BORROW
OUTPUT

r-

VOH
V

OL

tPLH

I

Jr-

VOH

1.3V~ __

VOL

\! I

VOLTAGE WAVEFORMS

~

3V
OV

NOTES:
A.
B.
C.
D.

The pulse generator has the following characteristics: PRR .;;; 1MHz, Zout = 50n, duty cycle = 50%.
CL includes probe and jig capacitance.
Diodes are 1N3064.
Count-up and count-down pulse shown is for the 25LS193 binary counter. Count cycle for 25LS192 decade counter is 1 through 10.
E. Waveforms for outputs 0A, OB, and Ot:: are omitted to simplify the drawing.
F. tr and tf';;; 7ns.

FIGURE Z-'ROPAGATION DELAY TI~ES

[EYTHEO]']

3-63

25LS192

Synchronous BCD Decade Up/Down Counter

25LS193

Synchronous 4-Bit Binary Up/Down Counter
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES
~5LS192

Illustrated below is the following sequence:
1.
2.
3.
4.

Clear outputs to zero.
Load (pres'et) to BCD seven.
Count up to eight, nine, carry, zero, one, and two.
Count down to one, zero, borrow, nine, eight, and seven.

CLEAR

~ _______________________________________

U

LOAD

11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

DATA{:D

-1_-.Jr-;:- ;:- - - '- -:;-~ -_- ~ ~ ~ ~ ~ ~; ~ ~ ~; ~ ~ ~ ~
-.J

I

L ===
________________ _

I

COUNT~
"
UP
LJ
COUNT
DOWN

OUTPUTS

{

I

,I

,

I!

-------------- - -. - - - - - - - - - - - "

LJ

"

LJ

"

LJ

,-------------------LJ

I

I

~
I

I

I

I

I

I

QA=~~~~
I

I

I

OB=~

I

I

I

I

I

I

I

I

I

I

,

I

I

,I

I

I

I'

Qc=~

I

I

I

~

I

I

r;-

I

I

I

I

I

I

I

I

QD=i

I

I

I

I

I

I

~

I

I

I

I

I

I

I

I

I

I

I

I

CARRY

I

u

BORROW--~,~,--~,~,--~,----------------~,--~----,LJ

lui

i7i

SEQUENCE
ILLUSTRATED ~ ~
CLEAR PRESET

'~ij-COUNT
"
iI
~",
UP

1$-1'

.~ COUNT
U
!I
DOWN

NOTES:

A. Clear overrides load, data, and count inputs.
B. When counting up, count·down input must be high; when counting
down, count-up input must be high.

3-64

~YTHEO~

Synchronous BCD Decade Counter

25LS192

Synchronous 4-Bit Binary Up/Down Counter

25LS193

TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES
25LS193

Illustrated below is the following sequence:
1.
2.
3.
4.

Clear outputs to zero.
Load (preset) to binary thirteen.
Count up to fourteen, fifteen, carry, zero, one, and two.
Count down to one, zero, borrow, fifteen, fourteen, and
thirteen.

CLEAR

~
, I

U
I I

LOAD

~

OA>{

,L - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

I
I

I

I

I

_

,

r- -

--;--;-----',
I

I

~
~

I

I

COUNT
UP

, ,

COUNT
DOWN

=h----f:-~
,
I, ,
{
OUTPUTS·
I, 'rc.'--.-:..'___---,
Qc=~"
'---______~
QA:

Qs-

I

I

I

I

QD=~'
CARRY

I

I

I

I

I

I

I

I

I

It:

I
I

I

U
I

I

SORROW----'-'--'-,-~,--'-,---'-,--------~,----'-,-----.u

101

1131

SEQUENCE
-A---'-ILLUSTRATED , - ~ , - ~
CLEAR PRESET

~4

15

0

COUNT UP

~2

~1

0

'

15

14~'

- COUNT DOWN

NOTES:
A. Clear overrides load, data, and count inputs.

B. When counting up, count-down input must be high; when counting
down, count-up input must be high.

~YTHEO]J

3-65

25LS194A

4-Bit Universal Shift Register

25LS195A

4-Bit Parallel-Access Shift Register

FEATURES
•
•
•
•
•

PIN-OUT DIAGRAM

Higher speed compared to 9LS/54LS and 9LSn4LS
8mA sink current over full military temperature
range
50mV improved VOL compared to 9LSn4LS
440tlA sou rce cu rrent
100% reliability assurance testing in compliance with

25LS194A

MIL-STD-883.

III

CLR SHIFT A B C 0 SHIFT GND
RIGHT'----v---' LEFT
SERIAL PARALLEL SERIAL
INPUT
INPUTS
INPUT

DESCRIPTION

The 25LS194A and 25LS195A are 4·bit registers that exhibit fully synchronous operation in all operating modes.
The 25LS195A can either parallel load all four register
bits via the parallel inputs (A, B, C, D) or shift each of the
four register bits right one place. The shifting or parallel
loading is under control of the shift/load input (S/L). When
the shift/load input is LOW, data is loaded from the paral·
lei data inputs; when the shift/load input is HIGH, data is
loaded from the register bits on the left. The first bit, QA,
is loaded via the J and K inputs in the shift mode.

11

16

10

9

2

8
3

Die Size .067 x .082

25LS195A
The 25LS194A operates in four modes under control of
the two select inputs, So and S1. The four modes are parallel load (data comes from the parallel inputs), shift right
(data comes from the flip·flop to the left, with the QA bit
input from R), shift left (data comes from the flip·flop to
the riQht. with the 0D inrlllt frnf11 L!, and ho!d or

d~

ncthing

(each flip·flop receives data from its own output).
3
CLEARJ

For both devices the outputs change state synchronously
following a LOW·to·HIGH transition on the clock input,
CP. Both devices have an active-LOW synchronous clear
(CLR) which forces all outputs to the LOW state (QD HIGH)
independent of any other inputs.

K

ABC

DGND

'-v-'~

SERIAL INPUTS PARALLEL
INPUTS

15

14

13

12
11

16

Because all the flip-flops are D·type they do not catch o's or
1's, and the only requirements on any inputs is that they
meet the short set-up and hold time intervals with respect
to the clock LOW·to-HIGH transition.

10

9
2

8

3

.4

.5

6

.7

Die Size .067 x .082

3-66

t;YTHE~

4-Bit Universal Shift Register

25LS194A

4-Bit Parallel-Access Shift Register

25LS195A

25LS194A
LOGIC DIAGRAM
LOGIC DIAGRAM

PARALLEL INPUTS

B
(41

'A
(31

•

C
(51

0'
(61

MODE {S1 1101
CONTROL
(91
INPUTS so~~~--+-1+~~----~~~~r----t~~~+----1--~~,1

SERIAL

INPUT

CLOCK(~1~1I~--------__~-r-+

______~-+~r-____~__r-t-____-"

CLEAR~1~------------~-+'~______-4~~.-______~f.7.~____~

PARALLEL OUTPUTS

25LS194A
FUNCTION TABLE

CLEAR

MODE
Sl
SO

CLOCK

INPUTS
SERIAL
LEFT

RIGHT

OUTPUTS
PARALLEL
A

B

C

D

°A

°B

Oc

°D

L

X

X

X

X

X

X

X

X

X

L

L

L

L

H

X

X

L

X

X

X

X

X

X

H

H

H

X

X

a

b

c

d

H

X

H

X

X

X

X

H

L

H

X

L

X

X

X

X

L

°An
°An

nco
c
Q Bn

QDO
d

L

H

H

L

H

X

X

X

X

X

°Bn

°Cn

H

H

L

t
t
t
t
t

°BO
b

H

°AO
a
H

L

X

X

X

X

X

°Bn

°Cn

H

L

L

X

X

"X

X

X

X

X

°AO

°BO

H

high level (steady state)

L

low level (steady state)

X

irrelevant (any input, including transitions)

t

transition from low to high level

°Bn
°Dn
Q Dn
QCO

°Cn
Cen
H
L

°DO

a, b, c, d = the level of steady-state input at inputs A, B, C. or D, respectively.
0AO' QBO' nCO, 2QDO = the level of 0A' 0B' 0C' or ° 0 , respectively, before the indicated
steady-state input conditions were established.
QAn' QBn' 0Cn' 00n = the level of QA' 0B' 0C' respectively, before the most-recent t
transition of the clock.

~YTHEO]J

3-67

25LS194A

4-Blt Universal Shift Register

25LS195A

4-BitParaliel-Access Shift Register
25LS195A

LOGIC DIAGRAM

SERIAL
INPUT

PARAllEL INPUTS

~

A~--------~B~--~A~--~C----------~d

K

J

(2) (3

(4)

(5)

m

(6)

lOAD
CONTROL

ClOCK...;.(1_0_)--t~

P+----~~------~~r-----~+-~------r+_.

ClEAR~(1~)~~~-----r~--~--~~~--~--~~--~---r+-~--,

(15)

QA

~~----------~----~vr------------------~

PARAllEL OUTPUTS
25LS195A
FUNCTION TABLE

-_ ...........

INPUTS
CLEAR

SHIFT/
LOAD

CLOCK

SERIAL

J

K

PARALLEL
A

B

C

0

aA

aB

a

C

aD

00

L

X

X

X

X

X

X

X

X

L

L

L

L

H

H

L

t

X

X

a

b

c

d

a

b

c

d

d

H

H

L

X

X

X

X

X

X

QAO

QBO

Q CO

H

H

L

H

X

X

X

X

QAO

QAO

QBn

QDO
QCn

Dcn

H

H

H

H

H

H

t
t
t
t

H

high.J~vel

L

low level (steady state)

L

L

X

X

X

X

L

QAn

QBn

QCn

H

H

X

X

X

X

H

QAn

QBn

QCn

H

L

X

X

X

X

QAn

QAn

QBn

QCn

QDO

Dcn
QCn
QCn

(steady state)

X

irrelevant (any input, including transitions)

t

transition from low to high level

a, b, c, d = the level of steady-state input at A, B, C, or D, respectively.
QAO' QBO' Dca, QDO = the level of QA' QB' QC' or QD' respectively, before the indicated
steady-state input conditions were established.
QAn' QBn' QCn = the level of QA' QB' or QC' respectively, before the most-recent
transition of the clock.

3-68

~YTHEO]J

4-Bit Universal Shift Register

25LS194A

4-Bit Parallel-Access Shift Register

25LS195A

Recommended Operating Conditions
Military
Min

Nom

Supply voltage, Vee
High-level output current, IOH

4.5

5

Low-level output current, IOL

4
0

Clock frequency, fclock
Width of clock or clear pulse, tw
Mode control
Serial and parallel data

Setup time, t setup

Min

Nom

5.5

4.75

5

-440
8

4
0

3~_

Max

16
18

5.25

V
/lA
mA

35

MHz

0
-55

ns
ns
ns

30
16
18

--

ns
ns

0
0

125

Unit

-440
8

20

20
30

Clear inactive-state
Hold time at any input, thold
Operating free-air temperature, TA

Commercial
Max

70

°c

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Min

VOH
VOL
II
IIH
III
lost
Icc tt

Typ··

Max

Min

2

VIH
VIL
VI

Commercial

Military

Test Conditions·

Parameter

Vee-MIN,
Vee-MIN,

11--18mA

VCC=MIN,

VIH=2V,

VIW2V ,
Vil =Vllmax, IOH=--44O/lA

Vcc-MAX,
Vec-MAX,

VI=7V

Vcc=MAX,

VI=O.4V

2.5

V
0_8

V

-1.5

-1.5

V

2.7

3.5

3.4
0.25

0.40

0.30

0.45
0.1

0.30

0.45
0.1

20
-0.4

Vcc=MAX

V

0.40

-15

Unit

0_7

0.25

VI=2.7V

Vec-MAX

Max

2

IloL=4mA
IIOl -8m A

V il =Vllmax

Typ··

I

25LS194A

15

-85
23

I

25LS195A

14

21

20
-0_36
-15
15

-85
23

14

21

V
mA
/lA
mA
rnA
rnA

"For conditions shown as MIN or MAX, use the appropriate value specified under recommendea operating conditions for the applicable
device type.
""All typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttWith all outputs open, inputs A through 0 grounded, and 4_5V applied to SO, 51, clear, and the serial inputs, Ice is tested with a momentary
GND, then 4.5V, applied to clock.

Switching Characteristics, Vee
Parameter

(Input)

Test Conditions: CL = 15pF,
IplH

RL

Ipw
Ipw
Is

Is
Is

25LS194A
Typ
Max,

Min

25LS195A
Typ
Max

Unit

= 2.0kO (See Fig. 1 .. 2 on page 3-71 and Flg_ A on page 2-174)

13

21

12

18

17

26

13
12

21
18

ns
ns

17

26

ns

°i

Clear

°i
Clock

17

16

ns

Clear

17

12

ns

Mode Control
Dala Input

25

25
15

Pulse Width
Set up time
. Clear recovery

Clock
Data

th

Hold time

IR

Shift/Release Time
(25LS195A only)

f MAX

Maximum clock frequency

~YTHEO]l

Min

Ciock

tpHl
IpHl

= 5V Over Recommended Free-Air Temperature Range

To
(Output)

From

16
20

20

ns
ns
ns

0

0

ns

35

55

10
35

55

ns
MHz

3-69

4-Bit Universal Shift Register
4-Bit Parallel-Access Shift Register

25LS194A
25LS195A

25LS194A
TYPICAL TIMING SEQUENCES

CLOCK
MODE {SOU' !
CONTROL
__ J ,

-i' I:

INPUTS
Sl::~L.-+-_ _ _ _ _ _
CLEAR~~:-+----------~'~'------~:---------~

i:
!:

SERIAL{R
OAT A
I NPUTS

-'--+-_____-'-,:~
,

n

1..-_ _ _ _

{~---l1Hl-iir-"H-r:
-~--------:--.,......

l

PARALLEL . B
L!
DATA
C~~_ _ _ _ ____:_~---__~----~-

1

INPUTS

~

rD __ L L
oA·-~

OUTPUTS

l----l

,'-------'--:--------'

h

~L--Ji

oB::'; :: ;'
:'

oc

~a

.-~

:

D._~

i i

L--J

f..SHIFT

CLEAR LOAD

RIGHT~

I--SHIFT
LEFT

-+-INHIBIT~

CLEAR

25LS195A
TYPICAL TIMING SEQUENCES

I

I

SERIAL{.:!
INPUTS
K

---;----'~

r-TI
I

SHIFT/LOAD
PARALLEL
{
DATA
INPUTS

I

I

,

A '
I"ifi'"I
B
L :
C
nHf-,~~
---;----~---------~,
D

~

Dc : : : ; ,
aD:::~

:

CLEAR

__________

L,

I

OUTPUTS{~;~~~~

3·70

,

L.!......J

I

~SERIALSHIFT

~r--,,--______

~_ _ _ __
I

.l

t--SERIALSHIFT--

LOAD

~YTHE~

4-Bit Universal Shift Register
4-Bit Parallel-Access Shift Register

25LS194A
25LS195A

25LS194A

I"
CLEAR

"'

tw(clearl

--1.-3V""'Ui=:,..1-=--.V-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-- : :

1
,
1

lsetup
t

I

tn+1
,---.;.

n

tn+1

(See Note F)

I

t

n

~
I
-

~---

-I

~ thold

'-----...1

OV

lsetUPI--I

DATA
INPUT
(SEE TEST
TABLE)

OUTPUTQ

3V

1.3V

CLOCK

I
~
_~3~
I

1.3V

,

3V

__ _

1

OV

1

1
~

f---!--tPHL

I

----..... '

t - - - -.....\~.~---

\.. 1.3V

VOLTAGE WAVEFORMS
NOTES:
A. The clock pulse generator has the following characteristics: Zout'" 50 nand PRR .. 1 MHz, t r .. 15ns
and tf .. 6 ns. When testing f max, va~v PR R.
B. A clear pulse is applied prior to each test.
C. Vref = 1.3V.
Proplagation delav times (tPLH and tpHL) are measured at t n+1. Proper shifting of data is verified
at tn+4 with a functional test.
t n = bit time before clocking transition.
tn+1 = bit time after one clocking transition.
tn+4 = bit time after four clocking transitions.

FIGURE 1
25LS195A
LOAD FOR OUTPUT UNDER TEST
:.

CLEAR

-;

tw{clear)

---....~~~---------------------o--lsetup........j

r- t n +1

t-- t n+ 1

CLOCK

::

tn~ ___ 3V

tn...,

~ 1.3V

1.3V

'--

tW(Clk~lsetUP ..:"-thold
r--lsetuP.l-!- thold
OV
I
,I
~'Ii 3V

DATA
(SEE NOTE G) _ _ _-;. _ _ _
r-lsetup---'!
:
r----itrelease

....,-J:

SHIFT/LOAD

I

~1.3V!

t--tPHL.-I

~:::r~~I:~ED ------~'' \ 1.3V
NOTES:

1.3V ,_~~____ OV
r--tsetup-----.j
_.
3V

2~

~

~~~~ _______ OV

r.-tPLH-.t

t.-tPHL ....,

~2
1.3V

f

~

VOLTAGE WAVEFORMS

A. The clock pulse generator has the following characteristics: Zout ~ 50
ns. When testing f max • vary the clock PRR.
B. CL includes probe and jig capacitance.

VOH
VOL

.n

and PAR ~ MHz, tr '" 15 ns, and tf '" 6

C. All diode. are 1N 3064.
D. A clear pulse Is applied prior to each test.
E. Propagation delay times (tpLH and tpHL) are measured at t"+1' Proper shiftIng of data is verified at tn+4 with a
functional test.
F. J and K are tested the same as data A, B, C, and I;) inputs except that shift/load input remains high.
G. tn = bit time before clocking transition.
tn+1 == bit time after one clocking transition.
tn+4 == bit time after four clocking transitions.

FIGURE 2

G!VTHE@J

3-71

25LS194A

4-Bit Universal Shift Register

25LS195A

4-Bit Par~lIel-Access Shift Register
APPLICATION

12-BIT SHIFT-LEFT. SHIFT-RIGHT. PARALLEL LOAD REGISTER

S,
CLOCK
SHIFT
RIGHT

AO A, A2 A3

-

So

R

' - - S,

B

A

L

as

Oc

" - So

-

25LS194A

eLR QA

LEFT

0

C

' - - - CP

CLEAR
SHIFT

A4 A5 A6 A7

AS Ag Al0A11

I I I I I

IN

DO

I "

R

S,

B

A

"

C

0

L

25LS194A

' - - - CP
eLA QA

08

Oc

Do

r

1
~

-

"-

So

'--

S,

I I I It

r--

R

L

A

B

C

0

LEFT
IN

25LS194A

CP
CL.R

QA

as Qc

Do

y
SHIFT

~

~ RIGHT
OUT

OUT
8S

3-72

SHIFT

B9

810 811

8-Line-To-1-Line Multiplexer
With Three-State Outputs

25LS251

FEATURES
•
•
•
•
•
•
•
•

Selects one of eight data sources
Performs parallel-to-serial conversion
Complementary 3-state outputs
Higher speed compared to 9LS/54LS and 9LS/74LS
8mA sink current over full military temperature
range
50mV improved VOL compared to 9LS/74LS
440J.LA source current
100% reliability assurance testing in compliance with
MIL-STD-883_

PIN-OUT DIAGRAM
DATA INPUTS DATA SElECT
~ ,....----J"---.

Vce 4

I

DESCRIPTION

J

6

7

ABC

IT][Il CD ITlIIl m[I]
lOY W

~

DATA INPUTS OUTPUTS

2

t;

'-----.t---' '--v-'

This monolithic data selector/multiplexer contains full
on-chip binary decoding to select one-of-eight data sources
and features a strobe-controlled three-state output. The
strobe must be at a low logic level to enable this device.
The three-state outputs permit a number of outputs to be
connected to a common bus. When the strobe input is high,
both outputs are in a high-impedance state in which both
the upper and lower transistors of each totem·pole output
are off, and the output neither drives nor loads the bus
significantly. When the strobe is low, the outputs are
activated and operate as standard TTL totem-polt outputs.
To minimize the possibility that two outputs will attempt
to take a common bus to opposite logic levels, the output
control cii cuitry is designed so that the average output
disable time is shorter than the average output enable time.

5

Iilllllillil@JllilfiP[jQ)

2

16

GND

0

15

14
13
5

12
11

6

7 . . . . . . . . .. .
8
9 10
Die Size: .056 x .057

LOGIC DIAGRAM

STROBE (7)
(ENABLE) -'-'-'-------:.!......---t---H

SELECT

SELECT

Recommended Operating Conditions
Military

Supply voltage, Vr.r.
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA

3-80

Commercial

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5
-1

4.75

5

5.25
-2.6
8
70

4

8

4

-55

125

0

Unll

V
mA
mA

°c

t;YTHEO}J

Quadruple 2-Line-To-1-Line
Multiplexers With Three-State Outpufs

25LS257 25LS258

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Test Conditions·

Min

VIH

Guaranteed input logical high voltage for all inputs

VIL

Guaranteed input logical low voltage for all inputs

VI

Vee-MIN,

VOH

Vee-MIN,
V I W 2V ,
V =V max, IOH =MAX
Vee=MIN,

VOL

Vee-MAX,

IIH
IlL

-1.0mA

IOH

-2.6mA

Vee=MAX,

S input
Any other

S input
Any 9ther

S input
Any other

VI=7V

Vee=MAX,

VI=2.7V

Vee=MAX,

VI=O.4V

0.25

0.40

0.30

0.45

0.30

All outputs
25 LS257

All outputs
off

All outputs
off

0.45

V
pA

-20

-20

pA

0.2

0.2

0.1

0.1

40

40

20

20

-0.8

-0.8
-0.4
-15

-15

-85

5.9

10.0

5.9

10.0

8.2

13.5

9.2

13.5

10

15.3

10

15.3

4.1

8.0

4.1

8.0

6.2

11.0

6.2

11.0

7.0

11.2

7.0

11.2

Vee=MAX

mA
I1A
mA
mA

mA

high
low

0.40

20

-85

-15

V

20

-0.4

high

All outputs

V

IOL 8mA

All outputs

All outputs

-1.5

IOL =4mA

Vee=MAX

low

V

-1.5
3.1
0.25

V IH =2V,

Vee=MAX,

V
0.8

2.4

V IH -2V

Unit

0.7

3.4

Vo=O.4V

lost

lee tt

2.4

Commercial
Typ·· Max
Min
2

Vo=2.4V

IOZL
II

V IH =2V,

IOH

Max

2

11--18mA

VIL =VILmax

IOZH

Military
Typ··

25LS258

"For conditions shown as MIN or MAX, use the appropriate value specified under recommendea operating conditions for the applicable
device type.
"AII typical values are at Vee = 5V, TA = 25°e.
tNot more than one output should be shorted at a time.
ttlee is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.

~YTHEO::;J

3·81

25LS258

Quadruple 2-Line-To-1-Line
Multiplexers With Three-State Outputs

25LS257

Switching Characteristics , V'cc -- 5\l•TA = 25°C
Parameter 1)

From
(input)

To
(output)

Min

+2S'C
Typ

Max

Unit

Test Conditions: CL = 15pF, RL = 2kO (See Fig. A, page 2-174)

~ 25LS257

Data

Any

....!llii

25LS258

Data

Any

25LS257

Select

Any

25LS258

Select

Any

tpHL

tpHL
tPLH

t"PHl
tpLH

""1PHL
tZH

TzttZH

Tzt-

25LS257
25LS258

Test Conditions: CL

~
tLZ

25LS257

..!!iL

25LS258

tLZ

Output
Control
Output
Control

= 15pF, RL ;,
Output
Control
Output
Control

Any
Any

6
7
8
5
12
12
12
10
10
10
10
11

12
12
12
12
18
18
18
18
18
16
18
18

ns
ns
ns
ns
ns
ns

2kO(see~Fig. A, page 2-174)

Any
Any

10
10
9

8

15
18
15
15

ns
ns

8-Bit Universal Shift/Storage Register

25LS299

FEATURES
•
•
•
•
•
•

PIN-OUT DIAGRAM

Four operational modes
Three-state outputs
Common input/output pins
Cascadable shifting
Advanced Low-Power Schottky processing
100% reliability assurance testing in compliance with
MI L-STD-883

Vcc

St

07 DY7 DYS DY3 DYt CP SR

SL

lill

DESCRIPTION

SA

So

The 25LS299 is an 8-bit universal shift/storage register with
3-state outputs. Four modes of operation are possibleHold (store), shift left, shift right and load data.

[!Q]
So

Parallel load inputs and register outputs are multiplexed to
reduce the number of package pins. Separate continuous
outputs are also provided for flip·flop 00 and 07. These
devices can be cascaded to N-Bit words.

Gt

G2 DYs DY 4 DY2 DYo 00 CLR GND

The 25LS299 has a typical shift frequency of 50 MHz; and
is packaged in the standard 20-pin DIP package.
A separate active-LOW asynchronous clear input forces all
flip-flops to the LOW state whenever this clear input is
LOW.

LOGIC DIAGRAM
S,
1191

So
111

IIBI

SHIFT

~~~,r
SERIAL
INPUT

s~I~I~II~1'!!.I':=:=~~h
INPUT

171

AIOA

~YTHEO~

1131

BlOB

161
CIOc

1141
D/OD

151
E/OE

1151
F/OF

141
G/OG

1161
H/QH

3-83

8-Bit Universal Shift/Storage Register

25LS299
Recommended Operating Conditions

Military
Min

Nom

Max

5

5.5
-1.0
8
125

4.5

Supply Voltage, Vee
High·Level Output Current, 10H

-0.44

4
-55

Low-Level Output Current, 10L
Operating Free-Air Temperature, T A

Commercial
Min
Nom Max

4.75

5
-0.44

4
0

Unit

5.25
-2.6
8
70

V
mA
mA
C

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless Otherwise Noted)
Parameter

Military

Test Conditions·

Min

V IH

Guaranteed input logical HIGH voltage for all inputs

V IL

Guaranteed input logical LOW voltage for all inputs

VI

Vee-MIN., IIN- -18mA

VOH

VIN=VIH or V IL

Commercial
Max

2

DY O,DY 7

Vec-MIN.

IOH--0.44mA

2.5

IOH=-1.0mA

2.4

II
IH

SO, 51
All others

IlL

SO, 51
All others

0.30

Vee - MAX., See Note 3

-1.5

I

0.25

0.45

0.30

0.40
0.45
0.2

0.1

0.1

40

40
20
-0.8

-0.4

-0.4

-100

-100

40
-85

40
-85

38

57

-30
38

V
mA
IlA

20
-0.8

V O- 2.7V
-30

V

V

0.40

V O- O.4V

Vee - MAX., See Note 4

V
V

0.2

Vee=MAX., V IN = 0.4V

lOS
lee

V
0.8

2.4

Vee=MAX., V IN = 2.7V

Vee = MAX.

Unit

2.7

Vec=MAX., V IN = 5.5V

10

Max

2

0.25

10L -4.0mA
10L 8.0mA

VIN=V IH or V IL
SO,S1
All others

Typ**

0.7

IOH--2.6mA
VOL

Min

-1.5
0 0 ,07

Vee-MIN.

TVp**

mA
Il A
mA
mA

57

Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable
device type.
2. Typic": :iiiiits arc ai: V{;C; - 5.v V, 26°C tlmbien ana maximum ioaaing.
T

3. Not more than one output should be shorted at a time. Duration of the short circuit !est should not exceed one second.
4. lee - measured with clock input HIGH and output controls HIGH.

3-84

~YTHEO]]

a-Bit Universal Shift/Storage Register

25LS299

Switching Characteristics , V·CC- 5V, TA = +25°C
From
(Input)

Parameter
Test Conditions: C L

To
(output)

Clock

°i

Clock

DY i

tpHL

Clear

DYo-DY7

tpHL

Clear

00 or 0 7

51,50

DYi

<3 1 ,<3 2

DYi

tpHL
tpLH
tpHL

tZH
tZL
tZH

+2SoC
Min

Typ

Unit

Max

= 15pF, RL = 2kO (See Fig. A, page 2-174)

tpLH

tZL

I

19
23
18
21
25
27
20
19
20
18

51, So Set-up Prior

ts

to Clock
SR, SL Set-up Prior

ts

to Clock
Pulse Width (Clock)

tpw

Hold Time

tn

ns
ns
ns
ns
ns
ns

20

ns

20

ns

25
3

ns
ns

50

f max
Test Conditions: C L
tLZ
tHz
tLZ
tHz

MHz

= SpF, RL = 2kO (See Fig. C, page 2-174)
51,50

DYi

<31.<3 2

DYi

22
20
20
16

ns
ns

TRUTH TABLE
INPUTS

OUTPUTS

FUNCTION
SR

SL

CLEAR

CLOCK

X

X

L

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

H

X

M Load (Note 2)

X

X

H

t

0 Shift Right

L

X

H

H

D Sh ift Right

H

X

H

E Shift Left

X

L

H

t
t
t

Shift Left

X

1'1

H

t

Clear
Output
Control
Hold

= LOW

Z

= High

H = HIGH

X

= Don't Care

L

~YTHE~

Impedence

G2

Q7

OVo

OV1

OV2

OV3

OV4

OV5

OVs

OV7

L L

L

L

L

L

L

L

L

L

L

L

X

H L

NC

NC

Z

Z

Z

Z

Z

Z

Z

Z

X

X

L H

NC

NC

Z

Z

Z

Z

Z

Z

Z

Z

X

X

H H

NC

NC

Z

Z

Z

Z

Z

Z

Z

Z

L

L

L

L

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

H

H

L

L

A

A

A

B

C

0

E

F

G

H

L

L

L

L

DYS

L

DVO

DY1

DY2

DY3

DY4

DYS

DYS
DYS

S1 G1

(Note 1)

H

L

L

L

H

DYS

H

DYO

DY1

DY2

DY3

DY4

DYS

L

H

L

L

DY1

L

DY1

DY2

DY3

DY4

DYS

DYS

DY7

L

L

H

L

L

DY1

H

DY1

DY2

DY3

DY4

DYS

DYS

DY7

H

t = Transition LOW-to-HIGH
NC

INPUTS/OUTPUTS

Qo

So

= N a Change

Notes: 1. Either LOW to observe outputs.
2. In this mode DYi are inputs.

3-85

4-8y-4 Register Files with 3-State Outputs

25LS670

FEATURES
• Separate Read/Write Addressing Permits Simultaneous
Reading and Writing
• Fast Access Times ... Typically 20 ns
• Organized as 4 Words of 4 Bits
• Expandable to 512 Words of n-Bits
.• For Use as:
Scratch-Pad Memory
Buffer Storage Between Processors
Bit Storage in Fast Multiplication Designs
• 3·State Outputs
• The 25LS170 is Similar But Has Open-Collector Outputs

VCC

~

WRITE SELECT ENABLE
OATA
01

OUTPUTS
Q2

15

02

02

-- -RA

[!]
GND

DATA·
READ SELECT OUTPUTS
Positive Logic: See Description

DESCRIPTION
The 25LS670 MSI 16-bit TTL register file incorporates
the equivalent of 98 gates. The register file is organized as
4 words of 4 bits each and separate on-chip decoding is
provided for addressing the four word locations to either
write-in or retrieve data. This permits simultaneous writing
into one location and reading from another word location.
Four data inputs are available which are used to supply the
4-bit word to be stored. Location of the word is determined
by the write-address inputs A and B in conjunction with a
write-enable signal. Data applied at the inputs should be in
its true form. That is, if a high·level signal is desired from
the output, a high-level is applied at the data input for that
particular bit location. The latch inputs are arranged so that
new data will be accepted only if both internal address gates
inputs are high. When this condition exists, data at the 0
input is transferred to the latch output. When the writeFmab1r:' input, GV'J, ls h~gh, the d:::tu ;ilPUt3 aie inhibited
and their levels can cause no change in the information
stored in the internal latches. When the read-enable input,
GR, is high, the data outputs are inhibited and go into the
high-impedance state.

The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a
word. When the read address is made in conjunction with
the read-enable signal, the word appears at the four outputs.
This arrangement-data-entry addressing separate from dataread addressing and individual sense line-eliminates recovery times, permits simultaneous reading and writing, and
is limited in speed only by the write time (27 nanoseconds
typical) and the read time (24 nanoseconds typical). The
register file has a nondestructive readout in that data is not
lost when addressed.
All inputs except read enable and write enable are buffered
to lower the drive requirements to one Series 25LS standard
load, and input-clamping diodes minimize switching transients to simplify system design. High-speed double-ended
AND-OR-iNVERT yates are empioyed for tne read-address
function and have high-sink-current three-state outputs. Up
to 120 of these outputs may be wire-AND connected for
increasing the capacity up to 512 words. Any number of
these registers may be paralleled to provide n-bit word length.

LOGIC
READ FUNCTION TABLE (SEE NOTES A AND D)
READ INPUTS
RB

RA

WRITE FUNCTION TABLE (SEE NOTES A, B, AND C)

OUTPUTS
GR

01

02

03

WRITE INPUTS
04

WORD

WB

WA

GW

0

1

2

3

L

L

L

O=D

00

00

L

L

L

WOBl

WOB·2

WOB3

WOB4

L

H

L

W1Bl

W1B2

W1B3

W1B4

L

H

L

00

00
O=D

H

L

L

W2Bl

W2B2

W2B3

W2B4

H

L

L

00

00

00
O=D

00
00

H

H

L

W3Bl

W3B2

W3B3

W3B4

H

H

O=D

H

Z

Z

Z

X

X

00
00

00

X

L
H

00

X

00

00

NOTES:

A.
B.
C.
D.

Z

00

H = high level, L = low level, X = irrelevant, Z = high impedance (off)
(Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs.
00 = the level of a before the indicated input conditions were established.
WOB 1 = The first bit of word 0, etc.

4-By-4 Register Files with 3-State Outputs

25LS670

FUNCTIONAL BLOCK DIAGRAM

D1

~----.---f-~_--+=:::;:==:r==~===Ii=:33""")

OAT A
INPUTS

OUTPUTS

03 (2)

04 (3)

-.-.GW

WB

WA

WRITE INPUT

r§YTHEO]J

-.-.RB

GR

RA

READ INPUT

3-87

4-By-4 Register Files witb a:State Outputs

2SLS670

Recommended Operating Conditions
Military
Min.
Supply voltage, Vee

4.5

High-level output current, IOH
Low-level output current, IOL

4

5.5

4.75

8

4

Nom. Max.

5

Unit

5.25

V

-2.6

mA

8

mA

25

2ei

ns

10

10

ns

15

15

ns

15

15

ns

5

5

ns

Data input with respect to

write enable, tsetup(D)

(see Figure 2)

5

Min.

-1

Width of write-enable or read-enable pulse, tw
Setup times, high. or low·level data

Com."ercial

Nom. Max.

Write select wi th respect to
write enable, lsetup(W)
Data input with respect to

Hold times, high· or low-level data
(see Note 2 and Figure 2)

write enable, thold(D)
. Write select with respect to

write enable, thold(W)
Latch time for new data, tlatch (see Note 3)
Operating free-air temparature range, T A

NOTES

ns

25

25
-55

125

0

70

°e

1. Voltage values are with respect to network ground terminal.
2. Write-select setup tim" will protect the data written into the previous address. If protection of data in the previous address is
not required, tsetup(W) can be ignored as any address selection sustained for the final 30 ns of the write·enable pulse and
during thold(W) will result in data being written into that location. Depending on the duration of the input conditions, one or
a number of previous addresses;may have been written into.

3. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important only when attempting to read from a location immediately after that location has received new data.

4-By-4 Register Files with 3-State Outputs

25LS670

Electrical Characteristics Over Recommended Free-Air Temperature Range (Unless otherwise Noted)
Military

Parameter

Unit
Min.

V,H

High·level input voltage

V,L

Low·level input voltage

V,

Input clamp voltage

VOH

High-level output voltage

Low-level output voltage

TVp' Max.

2

VCC=MIN,

" =-18mA

Vee = ~IN,

V,H = 2V.

V,L = V!LmaX
VOL

Commercial

Test Conditions t

Vee = ~IN,

10H = -1mA

2.4

V,H = 2V.

TVp' Max.

V

2
0.7

0.8

V

-1.5

-1.5

V

3.4

10H =-2.SmA

V,L = V,Lmax

Min.

2.4

V

3.1

10L =4mA

0.25

0.4

0.25

0.4

10L =8mA

0.35

0.45

0.35

0.45

V

Off'Olate ou.!put cllrrent.
10ZH

high-level voltage applied

Vee = MAX,

V,H = 2V.

Vo = 2.7V

20

20

IJ.A

Vee = MAX,

V,H = 2V.

Vo = O.4V

-20

-20

IJ.A

Off-state output current,
10ZL

low-level voltage applied
Input current at

"

maximum input voltage

"H

High-level input current

',L

V, = 7V

0.1

0.1

0.2

0.2

GR

0.3

0.3

Any D. R.orW

20

20

GW

40

40

GR

SO

60

Vce =MAX.
V, = 2.7V

Low-level input current

Any.D.R,orW
GW

Vee = MAX.

Vee = MAX

lOS

Short-circuit output current ~

Vee = MAX

lee

Supply current

Vee=MAX,

tFor conditions shown as MIN or MAX, use the

AnyD.R,orW

-0.4

-0.4

GW

-0.8

-0.8

GR

-1.2

-1.2

-15
See Note 4

-85
30

-15

50

30

mA

IJ.A

mA

-85

mA

50

mA

appropri~te value specified under recommended operating conditions.

*AII typical values are at Vee = 5V, TA = 250e.

r

!liNot more than one output should be shorted at a time.

NOTE 4:

~YTHEO~

Maximum lee is guaranteed for the following worst-case conditions: 4.5V is applied to all data inputs and both enable inputs,
all address inputs are grounded and all outputs ar~ open.

3-89

4-By-4 Register Files with 3-State Outputs

25LS670

Switching Characteristics, Vee = 5V, Over Recommended Free-Air Temperature Range.
Parameter

T88t CondlUona: CL = 1SpF,

RL

From

To

(Input)

(Output)

Read

tpHL

Select

tpLH

Write

tpHL

enable

Any Q
Any Q
Any Q

Data

tpHL

T88t Condltlona: CL = SpF,

RL

Typ.

Max.

Unit

= 2.0kO (See Fig. 1 .2 on page 3-90'. 3-91 and Fig. A on page 2-174)

tpLH

tpLH

+25°e
Min.

23

40

25

45

26

45

28

50

25

45

23

40

ns
ns
ns

= 2.0kO (See Fig. C,page 2-174)

tZH
tZL

Read

tHZ

enable

Any Q

tLZ

WRITE·SELECT
INPUT WA or WB
(See Note A)

35
40

30

50

16

35

1.3V

ns

3V

1.3V

_ _ _ _ _ _ _ _ _ _ _ __

~ tsetup(W)
~

I

DATA INPUT
01.02, 03, or 04
(See Note A)

ns

t

-J
-

15
22

1.3V

trh_OI_d_(W~)_ _ _ _ _ _ _ __

I

OV
3V

1,3V

OV
3V

WRITE·ENABLE
INPUTGW

OV

I:, ~!'-~'p_3:-H-f-;-3V- - =,

R EAD·SE L ECT
INPUT RA or RB
(See Note B)

OUTPUT
Q1, Q2, Q3, ofQ4

VOLTAGE WAVEFORMS (S1 AND S2 ARE CLOSED)

,

VOL

FIGURE 1

NOTES: A. High-level input pulses at .the select and data inputs are illustrated; however, times associated with low-level pulses are
measured from the same reference points.
B. When measuring delay times from a read select input, the read-enable input is low.

e,

3·90

Input waveforms are supplied by generators having the following characteristics: PRR .;;; 2 MHz, Zout " 50
50%, tr';;; 15 ns, tr';;; 6 ns.

n, duty cycle .;;;

4-By-4 Register Files with 3-State Outputs

i

DATA
INPUT
01,02,03,
or 04

'II \

25LS670

r-----------~-------------------------3V

1.3V

'-----oV

r----------.-------------------3V

WRITE· ENABLE
INPUT GW
___-;-____;--__

....j
OUTPUT
01,02,03, or Q4

tpLH

~.

I-

~

1~.3_V____________
tpHL

_ }.3V

OV

--I

\-;--1-.3-V----- VOH

VOLTAGE WAVEFORM 1 (Sl AND S2 ARE CLOSEO'-)----- VOL

1r-----3V
.

OV

1,---~---3V
---;.------'

' - - - - - - - - - - - - OV

r-----3V
OUTPUT
01,02,03, or 04

FIGURE2

NOTES:

A. Each select address is tested. Prior to the start of each of the above tests both write and read address inputs are stabilized with

WA = RA and WB = RB. During the test GR is low.
B. Input waveforms are supplied by generators having the following characteristics: PRR <; 1 MHz, Zout '" 50 n, dutY cycle <;
50%, tr <; 15 ns, Ir <; 6 ns.

~YTHE€3l

3-91

SECTION 4
Packaging Information

CONTENTS

PAGE

Plastic Packages, DIP
Metal Packages, DIP

4-2

Ceramic Packages, DIP

4-3

Ceramic Packages, Flat

4·4

Metal Packages, Flat

4-2

.

Beam Lead Mechanical Drawings.

~YTHEO]J

4·5
4·6

4-'

Packaging Information
Plastic Packages
14-PIN PLASTIC DIP

16-LEAD PLASTIC DIP

DB/BD

BM/MB

~ .760 ----1

.031 OIA X .010

~[ :~: :,~::~~r;~:~;J.
~--II-

:0a5~ ~ I- NOM
.025

--II- .025 NOM

.045

'~~~

SeatingJM~ff~6~fE\
-.
PI~

c.l.

J~L

II

.100

,020
11.016

~

.375

ml

~.009

NOM

TVP

Metal Package
14-LEAD METAL DIP

o
.718

~.688~
~ \ '\\ /\1

Is

.025R

lV .. ~...

7

11

,,,.nIUI

JQvvvv
.718

,

.
1 i:::
157

~ =.1.
'688

45"TVP

.1~X

-r-I I

.100 TYP--j

4-2

r

[1fT

-111~05OTYp

-11- .017TYP

~YTHE~

Packaging Information
Ceramic Packages
l6-LEAD
CERAMIC PACKAGE

14-LEAD CERAMIC DIP
DC/J

OM

I

.785

--:750~.098

J
~ r. __ .060

.150

ffi r- Il

MIN

.200
.125

I

.098

MAX

1'-

I··

-

-.L

Tr=-

-

JL

.020
.016

.015

i ;
:::::::

Oo~

.Q1L
.009

MAX

./ I..065

15'-ffrat:~
j ll NOM

.200 MAX

~J ~~~R

iEl: ,

1 T4 r-

-I~ .005 MIN

.045

ECU.'f(I·tffllt~JI-150
I-

/-_

.200

.060

MAX

.125
MIN

.100
, TYP

-

037 -ti'-MIN
-'----11-.020
.027
.016

I

.310
.290-

~
MAX

- :~ri~

.100 TYP

24-LEAD
CERAMIC PACKAGE
R/J

~YTHE~

4·3

Packaging Information

Flat Packages
,J

Ceramic

14-LEAD CERAMIC
FLAT PACKAGE
CJ/W

16-LEAD CERAMIC
FLAT PACKAGE
CL!W

.050

TYP .004MIN

.019

.015

==~~~~~§~
~
=
-_- ------rr
.260
.240

.-L

'~t
I
.006 MIN

-t
.!l06.

I. ..;I1L

_,.;I7IL

.004 1.250

.250

I

+t-~~a::::::~~~ --~

1-

I
.025

2611
.'-240

-I

.08
__ .0_

.~p

TYP

24-LEAD CERAMIC
FLAT PACKAGE
CN/W

14-LEAD CERAMIC
FLAT PACKAGE
CK

--H-- ~

~.004 MIN

.Oi9C::~==:':il,4
~:I_-+t.015
_.260
1

..L.-

.:

~.370_~

71

r

.025

TYP

'.170

~

T¥_ ~Il.

-t

]~

241

j
.11!!!!

.055

.L~'Uj

24-LEAD METAL
FLAT PACKAGE

PIN NO.

I'::

.370

---lIT

14-LEAD METAL
FLAT PACKAGE
J(TO-86)

;: \:

1

.400

10t::=:::::l

8

-r

11

,,= T.019
j
TyP
.014

c=:::::J7

.060J
TYP

~YTHEO]J

~~

=4

.070

.OOS

.040 J~~~~~!5E.:9~

L.039
01 1

1+1._ _ _ _.__

T

;- .004

~=----1

4-5

Packaging Information

Beam Lead
Mechanical Outline Drawings
I .

r
1!,055
0.053

BEAM LEAD

0.0075 TYP

! ~.~5
~

TYP

'"

:!!

1/ ~~~~I~~pLlP

-

0.0075 TYP
_

,,-0.0025 TYP

r

~g:g~

dTYP

I 0.0075
-.L ,..,:;:0::tt;;;;;;~;t::;it=~~1---.-n-,1)•.005
-.L~ . Q.91Q TYP_'_
-L
0,004

i

05

0.063 tll

0,005 TYP.::L.

QJ153

MECHANICAL OUTLINE 9

4-6

::2------BEAM LEAD
.. --NITRIDE LIP
0,001 TYP
0.0025 TYP

,

-10.0075 TYP
.

I

'

---'--~L~~~75
-

0.005 TYP

l··

':'c6

_U

"irT

1 0.001 TYP
hp1
- 0.0025 TYP

~:~:; .. -_.. --I ~SILlCON

=4

20 BEAM CHIP
EIA STANDARD
NOTE:

20 PLACES

....J..

'i.:

_ TYP

0,0005 TYP

1. METALIZATION DOWN
2, COUNTER CLOCKWISE BEAM ORDER

'....J:"" 0,003

L

10.01(~.

~SILICON

T6 16 BEAM CHIP-

11--0.004
I
0.004

'

~ ~~~5

16PLACES

0,001 TYP - 0,001 TYP
L T : L.§0,0075ITYP

------I

~~~75

!
0.065~

16 PLACES

I 0.0025

sse

q, 0.0025 TYP 0.005 20 PLACES

1-....·.. ~1

1'1

NOTE:

0.055

0.0075 TYP
T ~-'----,

0,0005 TYP

1. METALIZATION DOWN
2. COUNTER CLOCKWISE BEAM ORDER

MECHANICAL OUTLINE 12

t[AYTHEO]J



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