1978_Fairchild_TTL_Data_Book 1978 Fairchild TTL Data Book

User Manual: 1978_Fairchild_TTL_Data_Book

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F=AIRCHIL.C
01978 Fairchild Camera and Instrument Corporatlon/464 Ellis Street, Mountain View, California 94042/(415) 982-50~1/TWX 910-379-6435
Fairchild reserves the right to make changes In the circuitry or specifications in this book at any time without notice.
Manufactured under one of the following U.S. Patents: 2981877, 3015048, 3064167, 3108359, 3117260, other patents pending.

INTRODUCTION
This TTL DATA BOOK is a complete reference source for all Fairchild semiconductor SSI/MSI TTL products
(except Fairchild Advanced Schottky TTL, FAST, devices). It is organized into the following sections:
Section 1 - Product Indices and Selection Guides
The Product Indices are divided according to the numbering system used, i.e., 54/74 Family TTL, 9XXX Family
TTL, etc. Each index indicates which speed versions are available for the given product number and on which
page the data sheet can be found. Selection Guides within this section are divided according to the device
function. SSI functions are tabulated by speed family, MSI functions by their significant parameters.
Section 2 - TTL Characteristics
Section 2 defines the dc and ac parameter symbols used throughout this data book and discusses the general
scheme for naming the various types of logic inputs and outputs. Speed/power trade-offs and basic gate
schematics are compared for the different TTL circuit families. Input/output characteristics, thresholds and
noise margins are discussed. Wiring, line driving and decoupling recommendations, as well as specific
examples of interfacing TTL to other types of logic circuits, are included.
Section 3 - Loading, Specifications and Waveforms
This section contains dc specifications and ratings common to all devices in each family of circuits. Included is
a discussion of the unit load method of normalizing the input and output characteristics of a circuit, and how to
translate the numbers given in the Input Loading/Fan-Out table of a data sheet into the actual values of hH, ilL,
IOH and IOL currents. The various load configurations for ac testing, a table of RL and CL values for SSI gates and
waveforms that help to define the various ac parameters are also included.
Section 4 through 7 - Family Data Sheets
Individual data sheets are grouped by product family (Le., 54174, 9XXX TTL, etc.) and arranged in numerical
order within these families. The last two digits of the device number are repeated on the outside corner of each
page for the convenience of the reader.
Section 8 - Other Digital Products
Shortform information on older logic families (DTL, CTL, RTL) is given for reference.
Section 9 - Ordering Information and Package Outlines
The simplified purchasing code which identifies not only the device type, but also the package type and
temperature range, is explained. Detailed physical dimension drawings for each package are given.
Section 10 - Fairchild Field Sales Offices, Representatives and Distributors

iii

TABLE OF CONTENTS
SECTION 1 PRODUCT INDICES AND SELECTION GUIDES
Indices
54/74 Family TTL ............................................................................ 1-3
9XXX Family TTL ........................................................................... 1-10
93XX Family TTL ........................................................................... 1-10
96XX Family TTL ........................................................................... 1-12
Selection Guides
SSI Functions ..........................................................................••.. 1-12
Single and Dual Flip-Flops .................................................................. 1-15
Latches .................................................................................... 1-16
Multiple Flip-Flops ......................................................................... 1-17
Multiplexers ................................................................................ 1-17
Decoders/Demultiplexers ................................................................... 1-19
Registers .................................................................................. 1-20
Counters .................................................................................. 1-23
Monostables (One-Shots) ................................................................... 1-24
Line and Bus Drivers/Transceivers/Receivers ................................................ 1-25
Display Decoder/Drivers .................................................................... 1-26
Arithmetic Operators ....................................................................... 1-27
Random Access Memories .................................................................. 1-28
SECTION 2 TTL CHARACTERISTICS
Glossary ..................................................................................... 2-3
Logic Symbols and Terminology .............................................................. 2-6
TTL Circuit Families .......................................................................... 2-8
Input Characteristics ....................................................................... 2-12
Unused Inputs ............................................................................. 2-13
Output Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-13
Increasing Fan-Out ......................................................................... 2-15
3-State Outputs ............................................................................ 2-15
Open-Collector Outputs .................................................................... 2~16
Thresholds and Noise Margins .............................................................. 2-17
Crosstalk .................................................................................. 2-19
Transmission Lines ......................................................................... 2-20
Transmission Line Effects .................................................................. 2-21
Backplane Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-24
Decoupling ................................................................................ 2-24
Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-24
Supply Voltage and Temperature ............................................................ 2-25
Interfacing ................................................................................. 2-25
SECTION 3 LOADING. SPECIFICATIONS AND WAVEFORMS
Unit Loads (U.L.) ............................................................................. 3-3
Absolute Maximum Ratings ...................................................................3-4
Recommended Operating Conditions .......................................................... 3-4
DC Characteristics Tables .................................................................... 3-5
AC Loading and Waveforms ................................................................ 3-11

v

SECTION 4

54n4 FAMILY DATA SHEETS ........................................................ .4-3

SECTION 5

9XXX FAMILY DATA SHEETS ................. ........................................ 5-3

SECTION 6

93XX FAMILY DATA SHEETS ........................................................ . 6-3

SECTION 7

96XX FAMILY DATA SHEETS ..•....... ................................................ 7-3

SECTION 8 OTHER DIGITAL PRODUCTS
RTL Micrologic and CTL Counting Micrologic Elements ........................................ 8-3
DTL Micrologic ..............................................................................8-3
SECTION 9 ORDERING INFORMATION AND PACKAGE OUTLINES
Ordering Information .........................................................................9-3
Package Outlines .........•.................................................................. 9-4
SECTION 10 FAIRCHILD FIELD SALES OFFICES, REPRESENTATIVES AND DiSTRIBUTORS ...... 10-3

vi

SECTION 1

• Indices
54174 Family TTL
9XXx Family TTL
93XX Family TTL
96XX Family TTL
• Selection Guides
SSI Functions
Single and Dual Flip-Flops
Latches
Multiple Flip-Flops
Multiplexers
Decoders/Demultiplexers
Registers
Counters
Monostables (One-Shots)
Line and Bus Drivers/Transceivers/Receivers
Display Decoder/Drivers
Arithmetic Operators
Random Access Memories

Section 1

PRODUCT INDICES AND SELECTION GUIDES
INDICES
54174 FAMILY TTL
54/74
TTL

54H174H
H-TTL

54S174S
S-TTL

54LS174LS
LS-TTL

00

Quad 2-lnput NAND Gate

X

X

X

X

01

Quad 2-lnput NAND Gate

X

X

02

Quad 2-lnput NOR Gate

X

X

X

4-5

03

Quad 2-lnput NAND Gate

X

X

X

4-6

04

Hex Inverter

X

X

X

4-7

04A

Hex Inverter

DEVICE
NO.

DESCRIPTION

X

Hex Inverter

05A

Hex Inverter

06

Hex Inverter Buffer/Driver

X

07

Hex Buffer/Driver

X

X

X

4-3
4-4

4-7

X

05

PAGE
NO.

X

X

4-8
4-8

X

4-9
4-10

X

X

X

4-11

X

X

4-12

08

Quad 2-lnput AND Gate

X

09

Quad 2-lnput AND Gate

X

10

Triple 3-lnput NAND Gate

X

X

X

X

4-13

X

X

X

4-14

11

Triple 3-lnput AND Gate

X

12

Triple 3-lnput NAND Gate

X

13

Dual 4-lnput Schmitt Trigger

X

14

Hex Schmitt Trigger Inverter

X

15

Triple 3-lnput AND Gate

16

Hex I nverter Buffer/Driver

X

17

Hex Buffer/Driver

X

20

Dual 4-lnput NAND Gate

X

X

21

Dual 4-lnput Positive AND Gate

X

X

22

Dual 4-lnput NAND Gate

X

X

23

Expandable Dual 4-lnput NOR Gate

X

4-24

25

Dual 4-lnput NOR Gate

X

4-26

26

Quad 2-lnput NAND Buffer

X

X

4-27

27

Triple 3-lnput NOR Gate

X

X

4-28

28

Quad 2-lnput NOR Buffer

X

4-29

30

8-lnput NAND Gate

X

4-30

4-15

X

X

1-3

X

4-16

X

4-17

X

4-18
4-19
4-20

\

X

X

X

X

X

4-21

X

4-22

X

4-23

•

PRODUCT INDICES AND SELECTION GUIDES
54/74 FAMILY TTL (Cont'd)
DEVICE
NO.
32

DESCRIPTION

54n4
TTL

Quad 2-lnput OR Gate

54H174H
H-TTL

X

54S174S
S-TTL

54LS174LS
LS-TTL

PAGE
NO.

X

X

4-31

33

Quad 2-lnput NOR Buffer

X

4-32

37

Quad 2-lnput NAND Buffer

X

X

4-33

38

Quad 2-lnput NAND Buffer

X

X

4-34

39

Quad 2-lnput NAND Buffer

X

40

Dual 4-lnput NAND Buffer

X

4-36

41

1-of-10 Decoder/Driver (Nixie)

42

1-of-10 Decoder

42A

1-of-10 Decoder

X

4-37

43A

1-of-10 Decoder

X

4-37

44A

1-of-10 Decoder

X

4-37

X

4-41

X

4-44

X

4-35
X

X

6-48

9315
X

45

1-of-10 Decoder/Driver

46A

BCD to 7-Segment Decoder/Driver

47

BCD to 7-Segment Decoder/Driver

47A

BCD to 7-Segment Decoder/Driver

X

X

4-37

4-44
4-44

48

BCD to 7-Segment Decoder

X

X

4-48

49

BCD to 7-Segment Decoder

X

X

4-51

50

Expandable Dual 2-Wide,
2-lnput AND-OR-Invert Gate

X

X

51

Dual 2-Wide AND-OR-Invert Gate

X

X

52

Expandable 2-2-2-3-lnput
AND-OR Gate

53

Expandable AND-OR-Invert Gate

54

4-Wide, 2-lnput AND-OR-Invert Gate

55

AND-OR-Invert Gate

60

Dual 4-lnput Expander

61

4-54
X

X

4-56

X

4-57

X

X

4-59

X

X

X

4-61

X

X

4-63

X

4-64

Triple 3-lnput Expander

X

4-67

62

3-2-2-3-lnput AND-OR Expander

X

64

4-2-3-2-lnput AND-OR-Invert Gate

X

4-70

65

4-2-3-2-lnput AND-OR-Invert Gate

X

4-71

70

J K Edge-Trigger Flip-Flop

71

J K Master/Slave Flip-Flop

X

4-74

72

J K Master/Slave Flip-Flop

X

X

4-76

73

Dual J K Flip-Flop

X

X

X

4-68

4-72

X

1-4

X

4-78

PRODUCT INDICES AND SELECTION GUIDES
54174 FAMILY TTL (Cont'd)
DEVICE
NO.

DESCRIPTION

54/74
TTL

54H174H
H-TTL

54S174S
S-TTL

54LS174LS
LS-TTL

PAGE
NO.

X

X

X

4-81

X

4-86

74

Dual D-Type Positive
Edge-Triggered Flip-Flop

X

75

4-Bit Bistable Latch

X

76

Dual JK Flip-Flop

X

77

Quad D-Type Latch

X

78

Dual J K Flip-Flop

4-84

X

4-89

X

X

4-90

80

Gated Full Adder

X

4-93

82

2-Bit Full Adder

X

4-95

83A

4-Bit Binary Full Adder

X

X

4-98

85

4-Bit Magnitude Comparator

X

X

4-101

86

Quad 2-lnput Exclusive-OR Gate

X

X

4-105

87

4-Bit True/Complement,
Zero/One Element

89

64-Bit Random Access Memory

90

Decade Counter

X

4-106

X
X

X

4-108

X

4-111

90A

Decade Counter

X

4-111

91A

8-Bit Shift Register

X

4-114

92

Divide-by-Twelve Counter

92A

Divide-by-Twelve Cou nter

X

4-117

X

4-120

4-117

X

93

Divide-by-Sixteen Cou nter

93A

Divide-by-Sixteen Counter

X

4-120

94

4-Bit Shift Register

X

4-123

95A

4-Bit Right/Left Shift Register

X

958

4-Bit Right/Left Shift Register

96

5-Bit Shift Register

X

4-129

97

Synchronous Modulo-64
Bit Rate Multiplier

X

4-132

101

JK Edge-Triggered Flip-Flop

X

4-138

102

J K Edge-Triggered Flip-Flop

X

4-140

103

Dual JK Edge-Triggered Flip-Flop

X

4-142

106

Dual J K Edge-Triggered Flip-Flop

X

4-144

107

Dual JK Flip-Flop

108

Dual JK Edge-Triggered Flip-Flop

109

Dual JK Positive
Edge-Triggered Flip-Flop

4-126

X

X

X

4-146
4-149

X
X

1-5

4-126

X

4-151

•

PRODUCT INDICES AND SELECTION GUIDES
54174 FAMILY TTL (Cont'd)
DEVICE
NO.

DESCRIPTION

54174
TTL

54H174H
H-TTL

54S174S
S-TTL

54LS174LS
LS-TTL

PAGE
NO.

112

Dual JK Negative
Edge-Triggered Flip-Flop

X

X

4-153

113

Dual JK Edge-Triggered Flip-Flop

X

X

4-155

114

Dual Negative
Edge-Triggered Flip-Flop

X

X

4-157

116

Dual 4-Bit Latch

121

Monostable Multivi brator

X

4-159

122

Retriggerable Resettable Multivibrator

X

4-163

123

Dual Retriggerable
Resettable Multivibrator

X

4-166

125

Quad Bus Buffer Gate

X

125A

Quad Bus Buffer Gate

126

Quad Bus Buffer Gate

X

132

Quad 2-lnput Sch mitt
Trigger NAND Gate

X

133

13-lnput NAND Gate

6-24

9308

4-169

X

4-169

X

4-170

X

X

4-171

X

X

4-172

134

12-lnput NAND Gate

X

4-173

135

Quad Exclusive-OR/NOR Gate

X

4-174

136

Quad 2-lnput Exclusive-OR Gate

137

1-of-8 Decoder/Demultiplexer

X

138

1-of-8 Decoder/Demultiplexer

X

X

4-180

139

Dual 1-of-4 Decoder

X

X

4-183

140

Dual 4-lnput NAND Line Driver

X

X

4-175
4-176

4-186

141

1-of-10 Decoder/Driver (Nixie)

X

4-187

145

1-of-10 Decoder/Driver

X

4-189

150

16-lnput Multiplexer

X

4-192

151

8-lnput Multiplexer

151A

8-lnput Multiplexer

152

8-lnput Multiplexer

152A

8-lnput Multiplexer

X

153

Dual 4-lnput Multiplexer

X

154

1-of-16 Decoder/Demultiplexer

X

155

Dual 1-of-4 Decoder/Demultiplexer

X

X

4-205

156

Dual 1-of-4 Decoder/Demultiplexer

X

X

4-208

157

Quad 2-lnput Multiplexer

X

X

4-210

X

X

4-194

X
X

1-6

4-194

4-197
4-197

X

X

4-199
4-202

X

PRODUCT INDICES AND SELECTION GUIDES
54174 FAMILY TTL (Cont'd)

DEVICE
NO.

54174

DESCRIPTION

TTL

54H174H
H-TTL

54S174S
S-TTL

54LS/74LS
LS-TTL

PAGE
NO.

X

X

4-213

93S10

X

4-215/
6-30

158

Quad 2-lnput Multiplexer

160

Synchronous Presettable
BCD Decade Cou nter

X

161

Synchronous Presettable
Binary Counter

X

X

4-221

162

Synchronous Presettable
BCD Decade Counter

X

X

4-215

163

Synchronous Presettable
Binary Counter

X

X

4-221

164

Serial-In Parallel-Out Shift Register

X

X

4-224

165

8-Bit Parallel-to-Serial Converter

X

X

4-227

166

8-Bit Shift Register

X

167

Synchronous Decade Rate Multiplier

X

168

Synchronous Bidirectional
BCD Decade Counter

X

4-239

169

Synchronous Bidirectional
Modulo-16 Binary Counter

X

4-242

4-230
4-232

170

4 x 4 Register File

X

X

4-244

173

4-Bit D-Type Register

X

X

4-247

174

Hex D Flip-Flop

X

X

X

4-250

175

Quad D Flip-Flop

X

X

X

4-253

176

Presettable Decade Counter

X

4-256

177

Presettable Binary Counter

X

4-260

178

4-Bit Shift Register

X

4-262

179

4-Bit Shift Register

X

4-264

180

8-Bit Parity Generator/Checker

X

4-267

181

4-Bit Arithmetic Logic Unit

9341

93S41

182

Carry Lookahead Generator

9342

93S42

183

Dual High Speed Adder

189

64-Bit Random Access Memory

X

4-277

190

Up/Down Decade Counter

X

X

4-280

191

Up/Down Binary Counter

X

X

4-285

192

Up/Down Decade Counter

X

X

4-287

193

Up/Down Binary Counter

X

X

4-291

X

6-94
4-275

X
X

1-7

4-269/
6-87

PRODUCT INDICES AND SELECTION GUIDES
54174

FAMILY TTL (Cont'd)

DEVICE
NO.

54174

DESCRIPTION

194

4~Bit

194A

4-Bit Bidirectional
Universal Shift Register

195

Universal 4-Bit Shift Register

195A

Universal 4-Bit Shift Register

196

Presettable Decade Counter

TTL

Bidirectional
Universal Shift Register

54H/74H
H-TTL

X

54S/74S
S-TTL

54LS174LS
LS-TTL

4-293

X
X

X

93HOO

PAGE
NO.

4-293
4-296/
6-3

93S00
X

4-296

X

X

4-299

X

4-303

197

Presettable Binary Counter

X

198

8-Bit Right/Left Shift Register

X

4-305

199

8-Bit Parallel I/O Shift Register

X

4-308

240

Octal Buffer/Line Driver

X

X

4-311

241

Octal Buffer/Line Driver

X

X

4-311

242

Quad Bus Transceiver

X

4-314

243

Quad Bus Transceiver

X

4-314

244

Octal Buffer/Line Driver

X

4-311

245

Octal Bus Transceiver

X

4-316

247

BCD to 7-Segment Decoder/Driver

X

4-318

248

BCD to 7-Segment Decoder

X

4-319

249

BCD to 7-Segment Decoder

X

4-320

251

8-lnput Multiplexer

X

X

4-321

253

Dual 4-lnput Multiplexer

X

X

4-324

256

Dual 4-Bit Addressable Latch

X

4-327

257

Quad 2-lnput Multiplexer

X

4-330

257A

Quad 2-lnput Multiplexer

X

4-333

258

Quad 2-lnput Multiplexer

X

4-334

258A

Quad 2-lnput Multiplexer

X

4-337

259

8-Bit Addressable Latch

X

4-338

260

Dual 5-lnput NOR Gate

X

4-341

266

Quad 2-lnput Exclusive-NOR Gate

X

4-342

273

8-Bit Register

X

4-343

279

Quad Set-Reset Latch

X

4-345

280

9-Bit Parity Generator/Checker

283

4-Bit Binary Full Adder

X

4-348

289

64-Bit Random Access Memory

X

4-352

X

X

X

X

4-346

X
X
X

1-8

PRODUCT INDICES AND SELECTION GUIDES
54/74 FAMILY TTL (Cont'd)
DEVICE
NO.

54174

DESCRIPTION

TTL

54H/74H
H-TTL

54S1748

S-TTL

54LS/74LS
LS-TTL

PAGE
NO.

290

BCD Decade Counter

X

X

4-355

293

Modulo-16 Binary Counter

X

X

4-356

295A

4-Bit Shift Register

X

4-357

298

Quad 2-Port Register

X

4-360

299

8-lnput Universal
Shift/Storage Register

X

4-363

322

8-Bit Serial/Parallel Register

X

4-366

323

8-Bit Universal Shift/Storage Register

X

4-370

347

BCD to 7-Segment Decoder

X

4-373

X

352

Dual 4-lnput Multiplexer

X

4-374

353

Dual 4-lnput Multiplexer

X

4-377

365A

Hex 3-State Buffer

X

4-380

366A

Hex 3-State Inverter Buffer

X

4-381

367A

Hex 3-State Buffer

X

4-382

368A

Hex 3-State Inverter Buffer

X

4-383

373

Octal Transparent Latch

X

4-384

374

Octal D-Type Flip-Flop

X

4-387

375

4-Bit Latch

X

4-389

377

Octal D Flip-Flop

X

4-391

378

Parallel D Register

X

4-394

379

Quad Parallel Register

X

4-397

384

8-Bit Serial/Parallel
Twos Complement Multiplier

X

4-400

390

Dual Decade Counter

X

4-405

393

Dual Modulo-16 Counter

X

4-408

395

Shift Register

X

4-410

447

BCD to 7-Segment Decoder

X

4-413

490

Dual Decade Cou nter

X

4-414

502

8-Bit Successive
Approximation Register

X

4-416

503

8-Bit Successive
Approximation Register

X

4-420

504

12-Bit Successive
Approximation Register

X

4-423

533

Octal Transparent Latch

X

4-425

1-9

•

PRODUCT INDICES AND SELECTION GUIDES
54/74 FAMILY TTL (Cont'd)
DEVICE
NO.

54/74
TTL

DESCRIPTION

54H174H
H-TTL

54S174S
S-TTL

54LS174LS
LS-TTL

PAGE
NO.

534

Octal D-Type Flip-Flop

X

4-426

540

Octal Buffer/Line Driver

X

4-427

541

Octal Buffer/Line Driver

X

4-427

563

Octal D-Type Latch

X

4-429

564

Octal D-Type Latch

X

4-430

573

Octal D-Type Flip-Flop

X

4-431

574

Octal D-Type Flip-Flop

X

4-432

670

4 x 4 Register File

X

4-433

9XXX FAMILY TTL
DEVICE
NO.

DESCRIPTION

PAGE
NO.

DEVICE
NO.

PAGE
NO.

DESCRIPTION

9000

JK Flip-Flop

5-3

9009

NAND Buffer

5-17

9001

JK Flip-Flop

5-3

9012

NAND Gate

5-10

9002

NAND Gate

5-10

9014

Quad Exclusive-OR Gate

5-19

9003

NAND Gate

5-10

9015

Quad NOR Gate

5-22

9004

NAND Gate

5-10

9016

Hex Inverter

5-10

9005

Extendable AN D-OR-Invert Gate

5-13

9017

Hex Inverter

5-10

9006

Extender

5-13

9020

Dual JK Flip-Flop

5-3

9007

NAND Gate

5-10

9022

Dual JK Flip-Flop

5-3

9008

Entendable AND-OR-Invert Gate

5-13

9024

Dual JK (or D) Flip-Flop

5-24

93XX FAMILY TTL
DEVICE
NO.

DESCRIPTION

93XX
TTL

93H
H-TTL

93L
L-TTL

93S
S-TTL

X

X

X

00

4-Bit Universal Shift Register

X

PAGE
NO.
6-3

01

1-of-10 Decoder

X

02

1-of-10 Decoder

X

6-10

04

Dual Full Adder

X

6-13

05

Variable Modulus Counter

X

6-16

07

7-Segment Decoder

X

08

Dual 4-Bit Latch

X

X

6-24

09

Dual 4-lnput Multiplexer

X

X

6-27

1-10

X

6-7

6-20

PRODUCT INDICES AND SELECTION GUIDES
93XX FAMilY TTL (Cont'd)
DEVICE
NO.

DESCRIPTION

93XX
TTL

93H
H-TTL

93l
l-TTL

93S
S-TTl

PAGE
NO.

X

6-30

10

BCD Decade Counter

X

X

11

1-of-16 Decoder/Demultiplexer

X

X

12

8-lnput Multiplexer

X

X

13

8-lnput Multiplexer

X

14

Quad Latch

X

15

1-of-10 Decoder

X

16

4-Bit Binary Counter

X

17B

7-Segment Decoder/Driver

X

17C

7-Segment Decoder/Driver

X

6-51

18

8-lnput Priority Encoder

X

6-56

19

Decade Sequencer

X

6-59

20

Decade Sequencer

X

6-59

21

Dual 1-of-4 Decoder

X

X

6-64

22

Quad 2-lnput Multiplexer

X

X

6-66

24

5-Bit Comparator

X

X

6-69

28

Dual 8-Bit Shift Register

X

X

6-72

34

8-lnput Addressable Latch

X

X

6-75

38

8-Bit Multiple Port Register

X

X

6-78

40

4-Bit Arithmetic Logic Unit

X

41

4-Bit Arithmetic Logic Unit

X

42

Carry Lookahead Generator

X

43

4-Bit by 2-Bit Twos
Complement Multiplier

44

Binary (4-Bit by 2-Bitl Full Multiplier

46

High Speed 6-Bit Identity Comparator

47

High Speed 6-Bit Identity Comparator

48

12-lnput Parity Checker/Generator

62

9-lnput P.arity Checker/Generator

68

7-Segment Decoder/Driver/Latch

X

6-117

70

7-Segment Decoder/Driver/Latch

X

6-123

72

High Speed 4-Bit Shift Register

74

7-Segment Decoder/Driver/Latch

X

6-130

86

4-Bit Quad Exclusive-NOR

X

6-138

6-36
X

6-42
6-45

X

6-48
X

X

6-30
6-51

X

6-82
X

X

6-87

X

6-94

X

6-98
6-101

X
X

6-106

X

6-109
6-111

X
X

X

1-11

6-39

6-114

6-127

PRODUCT INDICES AND SELECTION GUIDES
96XX FAMILY TTL
DEVICE
NO.

96XX
TTL

DESCRIPTION

96L
L-TTL

96S
S-TTL

96LS
LS-TTL

PAGE
NO.

00

Retriggerable Resettable
Monostable Multivibrator

X

7-3

01

Retriggerable Monostable Multivibrator

X

7-8

02

Dual Retriggerable Resettable
Monostable Multivibrator

X

32

X

7-14/
7-20

Address Multiplexer/Refresh Counter

X

7-27

42

Address Multiplexer/Refresh Counter

X

7-30

101

Quad 2-lnput Positive NAND Buffer

X

7-33

103

Quad Bus Transceiver

X

7-34

106

Quad 2-lnput NOR Receiver

X

7-36

X

X

SELECTION GUIDES
SSI FUNCTIONS
FUNCTION
NAND Gates

I

9XXX

I

54/74

I

54H174H

I

54S/74S

I

54LS/74LS

Hex Inverters

9016

5417404

54H174H04

54S174S04
54S174S04A

54LS174LS04

Hex Inverters (DC')

9017

5417405

54H174H05

54S174S05
54S174S05A

54LS17 4LS05

Hex Inverter (15 V)

5417416

Hex Inverter (30 V)

5417406

Hex Schmitt Trigger

5417414

Quad 2-lnput

9002

5417400

Quad 2-lnput (DC')

9012

5417403

Quad 2-lnput (DC')

5417401

54LS174LS14
54H174HOO

54S174S00

54LS174LSOO

54S/74S03

54LS174LS03

54H174H01

Quad 2-lnput (12 V)

7426

54LS/74LS26

Quad 2-lnput (48 V)

5417437

54LS/74LS37

'oc = Op"n-collector; 3S = 3-State

1-12

.-

-

PRODUCT INDICES AND SELECTION GUIDES
SSI FUNCTIONS (Cont'd)
FUNCTION
NAND Gates (Cont'd)

I

9XXX

Quad 2-lnput (OC*/48 rnA)
Quad 2-lnput Line Driver

54174

I

54H174H

I

545174S

5417438
96101

9003

Triple 3-lnput (OC*)

I

54LS174LS

54LS174LS38

5417439
54174132

Quad 2-lnput Schmitt
Triple 3-lnput

I

5417410

54S/748132

54LS/7 4LS 132

54H/74H10

54S17481 0

54LS174LS10

54H174H20

54S/74820

54LS/74LS20

5417412

Dual4-lnput

9004

5417420

Dual 4-lnput Schmitt

5417413

Dual 4-lnput (OC*)

5417422

54H174H22

54S/74822

54LS174LS22

5417440

54H/74H40

54S/74840

54LS/74LS40

Dual 4-lnput Buffer

9009

54LS/74LS13

Dual 4-lnput Line Driver

54S/748140
9007

8-lnput

5417430

8-lnput

54H174H30

54S/74830

54LS174LS30

13-lnput

54S/748133

54LS174LS133

12-1 n put (3S*)

54S/748134

NOR Gates

54/7402

Quad 2-lnput

54S174802

54LS/74LS02

9015

Quad 2-lnput

5417427

Triple 3-lnput
Dual 4-lnput wiSt robe

5417425

Dual 4-lnput (Exp)

5417423

54LS/74LS27

Dual5-lnput

54S/748260

54LS174LS260

Quad 2-lnput

54LS174LS28

Quad 2-lnput (OC*)

54LS174LS33

AND Gates
Hex Buffer (OC*/15 V)

5417417

Hex Buffer (OC*/30 V)

54/7407

Quad 2-lnput

54/7408

Quad 2-lnput (OC*)

5417409

Triple 3-lnput

5417411

54H174H08

54H174H11

Triple 3-lnput (OC*)

5417421

Dual4-lnput
'0 C

= Open-Collector;

3S

54H174H21

= 3-State

1-13

54S/74808

54LS174LS08

54S174809

54LS174LS09

54S174811

54LS174LS11

54S174815

54LS174LS15
54LS/74LS21

PRODUCT INDICES AND SELECTION GUIDES
SSI FUNCTIONS (Cont'd)
FUNCTION

1

9XXX

54/74

1

54H174H

1

1

54S/74S

1

54LS174LS

OR Gates
Quad

2~lnput

15417432

1

I

1

Exclusive-OR Gates

5417486

Quad 2-lnput

548174832

1

54L8174L832

54L8174L886

548174886

Quad 2-lnput (OC*)

54L8174L8 136
9014

Quad 2-lnput ORINOR
Quad 2-lnput ORINOR

5481748135

Exclusive-NOR Gate
Quad 2-lnput (OC*)

19386 (8242)

1

AND-OR Gates
2-2-2-3 Input (Exp)
AND-OR-INVERT Gates
Dual 2-2 Input (Exp)

I

I
9005

Dual 2-2 Input
2-2-2-3 Input (Exp)

9008

2-2-2-3 Input

1

I

54H174H52

5417450

54H174H50

5417451

54H174H51

5417453

54H174H53

5417454

54H174H54

I
I

I
I
548174851

2-2-3-3 Input

54L8174L8266

54L8174L851

54L8174L854

2-2-3-4 Input

548174864

2-2-3-4 Input (OC*)

548174865

4-4 Input (Exp)

54H174H55

4-4 Input

54L8174L855

Gate Expanders
54H174H61

Triple 3-lnput
Dual 4-lnput

9006

5417460

54H174H60
54H174H62

2-2-3-3 AND-OR
Buffer Gates and Drivers
Quad Buffer (38*)

54174125

54L8174L8125A

Quad Buffer (38*)

54174126

54L8174L8126

Hex (38*)

54L8174L8365A

Hex Inverter (38*)

54L8174L8366A

Hex (38*)

54L8/74L8367A '

Hex Inverter (38*)

54L8/74L8368A

·oc = Open-Colleclor; 3S = 3-Slale

1-14

PRODUCT INDICES AND SELECTION GUIDES
SINGLE AND DUAL FLIP-FLOPS

FUNCTION

DEVICE NO.

INPUTS

9000

3J. 3K. JK

Single JK

9001

2J. 2K. J. K. JK

Single JK

54H174H71

(AO!)
(2 + 21J. (2 + 2lK

Single JK

54H174H101

Single JK

CLOCK
EDGE

...r
...r

DIRECT
SET

DIRECT
CLEAR

GUARANTEED
CLOCK FREQ.
MHz

X

X

20 (Typl

X

X

50 (Typl

\...

X

25

(AO!)
(2 + 21J. (2 + 2lK

'-

X

40

Single JK

5417472

3J.3K

'-

X

X

15

Single JK

54H174H72

3J.3K

\...

X

X

25

Single JK

54H/74H102

3J.3K

""\...

X

X

40

Single JK

5417470

2J. 2K. J. K

J

X

X

20

Dual D

5417474

D

...r

X

X

15

Dual D

54H174H74

D

J

X

X

35

Dual D

548174S74

D

.r
.r

X

X

75

D

X

X

30

X

50 (Typl

X

50 (Typl

X

15

X

15

X

25

Dual D

54LS/74LS74

Dual JK

9020

J.K. J. K. JK

...r

Dual JK

9022

J. K. JK

Dual JK

5417473

J. K

..r
\...

Dual JK

54174107

J.K

Dual JK

54H174H73

J.K

Dual JK

54H174H103

J. K

Dual JK

54S1748113

J. K

Dual JK

54LS/74L8113

J.K

X

\...
\...

''-

X

40

X

80

\..

X

30

Dual JK

5417476

J. K

\...

X

X

15

Dual JK

54H174H76

J. K

'-

X

X

25

Dual JK

54H/74H106

J. K

X

X

40

X

X

80

X

X

30

Dual JK

54S174S112

J. K

Dual JK

54LS/74LS112

J. K

\...
\...
\...

Dual JK

54H/74H78

J. K

\..

X

X

25

Dual JK

54H174H108

J. K

'-

X

X

40

Dual JK

54LS/74LS73

J. K

'-

X

30

Dual JK

54S/74S114

J. K

\..

X

X

80

Dual JK

54LS174LS114

J. K

'-

X

X

30

Dual JK

9024, 54174109

J. K

X

X

25

...r

1-15

•

PRODUCT INDICES AND SELECTION GUIDES
SINGLE AND DUAL FLIP-FLOPS (Cont'd)

DEVICE NO.

FUNCTION

INPUTS

CLOCK
EDGE

DIRECT
SET

DIRECT
CLEAR

GUARANTEED
CLOCK FREQ.
MHz

Dual JK

54S/74S109

J, K

J

X

X

75

Dual JK

54LS/74LS109

J, K

..r

X

X

30

Dual JK

54LS/74LS76

J, K

Dual JK

54LS174LS107

J, K

Dual JK

54LS/74LS78

J, K

\..
\..
"\.

X

X

X

30

X

30

X

30

LATCHES
ENABLE
INPUTS
(LEVEL)

MIN ENABLE
PULSE WIDTH
ns

MAX DELAY
ENABLE TO
OUTPUT-ns

L

1 (U

18

24

L

1 (U

30

45

L

1 (U

18

24

4XD

L

1 (U

30

45

8XD

2XL

2 X2 AND

18

30

8XD

2XL

2 X 2 AND

30

45

DATA
INPUTS

COMMON
CLEAR

9314

4 X (R1Sl)

4-Bit RS Latch

93L14

4 X (R1Sl)

4-Bit D Latch

9314

4XD

4-Bit D Latch

93L14

Dual 4-Bit D Latch

9308

FUNCTION

4-Bit RS Latch

DEVICE NO.

(54174116)

Dual 4-Bit D Latch

93L08

4-Bit RS Latch

54174279

4 X (RS)

4-Bit RS Latch

54LS174LS279

4 X (RS)

4-Bit D Latch

5417475

4XD

2 (H)

20

30

4-Bit D Latch

54/7477

4XD

2 (H)

20

30

4-Bit D Latch

54LS/74LS375

4XD

2 (H)

20

30

Dual4-Bit
Addr. Latch

54LS/74L S256

8XD

L

2(U

17

27

8-Bit Addr. Latch

9334

1XD

L

1 (U

17

24

8-Bit Addr. Latch

93L34

1XD

L

8-Bit D Latch

54LS/74LS373

8XD

8-Bit D Latch

54LS174LS573

1 (U

26

45

1 (H)

15

30

8XD

1 (U

15

30

8-Bit D Latch

54LS/74LS533

8XD

1 (H)

15

30

8-Bit D Latch

54LS174LS563

8XD

1 (H)

15

30

8-Bit Addr. Latch

54LS174LS259

1XD

1 (U

17

27

16-Bit D Latch

54174170

4XD

2

25

45

16-Bit D Latch

54LS174LS170

4XD

2

25

35

16-Bit D Latch

54LS174LS670

4XD

2

25

35

64-Bit Memory

5417489

4XD

2 (U

40

70

L

1-16

PRODUCT INDICES AND SELECTION GUIDES
LATCHES (Cont'd)

FUNCTION

DEVICE NO.

DATA
INPUTS

COMMON
CLEAR

ENABLE
INPUTS
(LEVEL)

MIN ENABLE
PULSE WIDTH
ns

MAX DELAY
ENABLE TO
OUTPUT-ns

25 (Typ)

30 (Typ)

54LSn4LS89

4XD

2 (U

64-Bit Memory

54S/74S189

4XD

2 (U

20

40

64-Bit Memory

54LSn4LS189

4XD

2 (U

25 (Typ)

30 (Typ)

64-Bit Memory

54S/74S289

4XD

2 (U

20

40

64-Bit Memory

54LS/74LS289

4XD

2 (U

25 (Typ)

30 (Typ)

64-Bit Memory

MULTIPLE FLIP-FLOPS

DEVICE NO.

FUNCTION

DATA
INPUTS

COMMON
CLEAR

CPINPUTS
(LEVEL)

GUARANTEED
CLOCK FREQ.
MHz

4-Bit D Flip-Flop

54174175

4XD

L

1 (f)

25

4-Bit D Flip-Flop

54Sn4S175

4XD

L

1 (f)

75

4-Bit D Flip-Flop

54LS/74LS175

4XD

L

1 (J)

30

4-Bit D Flip-Flop

54174298

2X4XD

1( "\... )

25

4-Bit D Flip-Flop

54LS174LS298

2X4XD

1 (\...)

25

6-Bit D Flip-Flop

54174174

6XD

L

1(J)

25

6-Bit D Flip-Flop

54S/74S174

6XD

L

1 (f)

75

L

1 (f)

30

6-Bit D Flip-Flop

54LS174LS174

6XD

8-Bit Multiple Port Register

9338

1XD

1 (U

27

8-Bit Multiple Port Register

93L38

1XD

1 (U

14

8-Bit D Flip-Flop

54LS/74LS374

8XD

1 (f)

35

8-Bit D Flip-Flop

54LS174LS534

8XD

1(f)

35

8-Bit D Flip-Flop

54LS/74LS564

8XD

1 (f)

35

,
MULTIPLEXERS
DEVICE NO.

FUNCTION

ENABLE
INPUTS

TRUE
OUTPUT

COMPLEMENT
OUTPUT

Quad 2-lnput

9322

1

X

Quad 2-lnput

93L22

1

X

Quad 2-lnput

54/74157

1

X

Quad 2-lnput

54S174S157

1

X

Quad 2-lnput

54LS/74LS157

1

X

Quad 2-lnput

54S/74S158

1

X

54LSn4LS158

1

X

Quad

2~lnput

1-17

PRODUCT INDICES AND SELECTION GUIDES
MUL TIPLEXERS (Cont'd)
ENABLE
INPUTS

TRUE
OUTPUT

54S/74S257

1

3S'

Quad 2-lnput

54LS/7 4L S257

1

3S'

Quad 2-lnput

54LS174LS257 A

1

3S'

Quad 2-lnput

54S174S258

1

3S'

Quad 2-lnput

54LS174LS258

1

3S'

Quad 2-lnput

54LS174LS258A

1

3S'

Quad 2-lnput

54174298

Clocked
(Edge-Trigger)

X (Latched)

Quad 2-lnput

54LS174LS298

Clocked
(Edge-Trigger)

X (Latched)

Dual4-lnput

9309

X

X

Dual4-lnput

93L09

X

X

Dual 4-lnput

54174153

2

Dual4-lnput

54S/74S153

2

X

Dual4-lnput

54LS/74LS153

2

X

Dual4-lnput

54S174S253

2

3S'

Dual 4-lnput

54LS174LS253

2

3S'

Dual 4-lnput

54LS/74LS352

2

X

Dual4-lnput

54LS174LS353

2

3S'

8-lnput

9312

1

X

X

8-lnput

93L12

1

X

X

8-lnput

93S12

1

X

X

8-lnput

93.13

1

X

ac'

8-lnput

54174151A

1

X

X

8-lnput

54S/74S151

1

X

X

8-lnput

54LS/74LS151

1

X

X

8-lnput

54S/74S251

1

3S'

3S'

8-lnput

54LS174LS251

1

3S'

3S'

8-lnput

54174152A

8-lnput

54LS/74LS152

12-lnput

96LS42

1

X

14-lnput

96LS32

1

X

16-lnput

54174150

1

X

DEVICE NO.

FUNCTION

Quad 2-lnput

'OC

= Open-Collector;

35

COMPLEMENT
OUTPUT

X

X
X

= 3-5tate

1-18

PRODUCT INDICES AND SELECTION GUIDES
DECODERS/DEMULTIPLEXERS

FUNCTION

DEVICE NO.

ADDRESS
INPUTS

ACTIVE LOW
ENABLE

ACTIVE LOW
OUTPUTS

OPEN-COLLECTOR
OUTPUT VOLTAGE
V

Dual 1-of-4

9321

2+2

1+ 1

4+4

Dual 1-of-4

93L21

2+2

1+ 1

4+4

Dual 1-of-4

54S/74S139

2+2

1+ 1

4+4

Dual 1-of-4

54LS/74LS139

2+2

1+ 1

4+4

Dual 1-of-4

54174155

2

2+1

4+4

Dual 1-of-4

54LS/73LS155

2

2+1

4+4

Dual 1-of-4

54174156

2

2+ 1

4+4

5.5

Dual 1-of-4

54LS/74LS156

2

2+ 1

4+4

5.5

1-of-8

9301

3

1

8

1-of-8

93L01

3

1

8

1-01-8

9302

3

1

8

1-of-8

9334

3

1

8

--.

•
5.5

1-of-8

93L34

3

1

8

1-01-8

54LS/74LS259

3

1

8H

1-of-8

5417445

3

1

8

1-of-8

5417442A

3

1

8

1-of-8

54LS/74LS42

3

1

8

1-of-8

54S/74S138

3

2

8

1-of-8

54LS174LS138

3

2

8

1-of-8

54/74145

3

1

8

1-of-8 w/lnput Latches

54S/74S137

3

2

8

1-of-10

9301

4 (BCD)

10

1-of-10

93L01

4 (BCD)

10

1-01-10

9302

4 (BCD)

10

5.5

1-01-10

5417445

4 (BCD)

10

30

10

1-01-10

5417442A

4 (BCD)

1-01-10

54LS174LS42

4 (BCD)

10

1-01-10

54/7443A

4 (Excess-3)

10

1-01-10

5417444A

4 (Excess-3
Gray)

10

1-01-10

54174145

4 (BCD)

10

1-01-16

9311

4

2

1-19

16

30

15

15

PRODUCT INDICES AND SELECTION GUIDES
DECODERS/DEMULTIPLEXERS (Cont'd)

FUNCTION

DEVICE NO.

ADDRESS
INPUTS

ACTIVE LOW
ENABLE

ACTIVE LOW
OUTPUTS

1-of-16

93L11

4

2

16

1-of-16

54/74154

4

2

16

1-of-10
Decade Sequencer

9319

Clock

10

1;-of-10
Decade Sequencer

9320

Clock

10

OPEN-COLLECTOR
OUTPUT VOLTAGE

V

3 K Pull-up

REGISTERS

NO. OF
FUNCTION

DEVICE NO.

BITS

SERIAL
EiIITRY

PARALLEL
ENTRY
NO. OF BITS1

CLOCK
EDGE

GUARANTEED
CLOCK FREQ.
MHz

Parallel-in/Parallel-out
Shift Right

9300

4

J,

K

4S

..r

30

Parallel-in/Parallel-out
Shift Right

93HOO

4

J,

R'

4S

..r

45

Parallel-in/Parallel-out
Shift Right

93LOO

4

J, K

4S

..r

10

Parallel-in/Parallel-out
Shift Right

93S00

4

J, K

4S

..r

70

Parallel-i n/Parallel-o ut
Shift Right

93H72

4

D

4S

..r

45

Serial/Parallel-in,
Parallel-out, Shift Right

54/7494

4

D

2 X 4A (MUX)

..r

10

Parallel-i n/Parallel-out
Shift Right

5417495A

4

D

4S

"-

25

Parallel-in/Parallel-out
Shift Right

54LS/74LS95B

4

D

4S

"-

30

Parallel-in/Parallel-out
Shift Right

54/74178

4

D

4S

\..

25

Parallel-in/Parallel-out
Shift Right

54/74179

4

D

4S

\..

25

Parallel-in/Parallel-out
Shift Right

54LS/74LS195A

4

J, K

4S

J

30

Parall el-i n/Paral1 el-out
Shift Right (3S2)

54LS/74LS295A

4

D

4S

\..

30

1. S = Synchronous; A = Asynchronous
2. OC = Open-Collector; 3S = 3-State

)
1-20

PRODUCT INDICES AND SELECTION GUIDES
REGISTERS (Cont'd

FUNCTION

DEVICE NO.

NO.OF
BITS

SERIAL
ENTRY

PARALLEL
ENTRY
NO. OF BITS1

CLOCK
EDGE

GUARANTEED
CLOCKFREQ.
MHz

Paraliel-in/Parallel-out
Shift Right (3S2)

54LS/74LS395

4

0

4S

""\..

30

Parall el-i n/Parallel-o ut
Bidirectional

54174194

4

OR,OL

4S

f

25

Parallel-i n/Paral1 el-o ut
Bidirectional

54S/74S194

4

DR, OL

4S

f

70

Parallel-in/Parallel-out
Bidirectional

54LS174LS194A

4

OR,OL

4S

..r

30

Quad 0 (3S2)

54174173

4

4S

..r

25

Quad 0 (3S2)

54LS/74LS173

4

4S

.r

30

Quad 0 Flip-Flop

54/74175

4

4S

Quad 0 Flip-Flop

54S/74S175

4

4S

Quad 0 Flip-Flop

54LS174LS175

4

4S

Quad 2-Port Register

54/74298

4

20 (MUX)

54LS/74LS298

4

20 (MUX)

"\...
\...

30

Quad 2-Port Register
Quad 0

54LS/74LS379

4

4S

.f

30

Parall el-i n/Paral1 el-o ut
Shift Right

5417496

5

5A

..r

10

Hex 0 Flip-Flop

54/74174

6

6S

..r

25

6S

f

75

..r
..r
..r

30

0

.f

..r
..r

25
75
30

30

Hex 0 Flip-Flop

54S174S174

6

Hex 0 Flip-Flop

54LS/74LS174

6

6S

Parallel 0 Register

54LS/74LS378

6

6S

Multiport Register

9338

8

0

Multiport Register

93L38

8

0

.r

20

Parallel-in/Parallel-out
Shift Right

54174199

8

J, K

8S

..r

25

Serial/Paraliel-i n,
Parallel/Serial-out
Shift Right (3S2)

54LS/74LS322

8

20

85

f

35

Serial-in/Parallel-out
Shift Right

54174164

8

20

f

25

Serial-in/Parallel-out
Shift Right

54LS/74LS164

8

20

f

25

1. s = Synchronous; A = Asynchronous
2. OC = Open-Collector; 3S = State

1-21

30
25

PRODUCT INDICES AND SELECTION GUIDES
REGISTERS (Cont'd)

FUNCTION

DEVICE NO.

NO.OF
BITS

SERIAL
ENTRY

PARALLEL
ENTRY
NO. OF BITS1

CLOCK
EDGE

GUARANTEED
CLOCK FREQ.
MHz

Parallel/Serial-in,
Serial-out, Shift Right

54/74165

8

D

8A

J

25

Parall el/Seri al-i n,
Serial-out, Shift Right

54Lsn4LS165

8

D

8A

J

30

Parallel/Serial-in,
Serial-out,Shift Right

54/74166

8

D

8S

J

25

Serial-i n/Serial-out
Shift Right

54/7491 A

8

2D

J

10

Successive Approx
Register

54LS/74LSS02

8

D

J

15

Successive Approx
Register

54LS/74LSS03

8

D

...r

15

Parallel-in/Parallel-out
Bidirectional

54/74198

8

DR, DL

8S

J

25

Parall el-i n/Parallel-out
Bidirectional (3S2)

54LS/74LS299

8

DR,DL

8S

J

35

Parallel-in/Parallel-out
Bidirectional (3S2)

54LS/74LS323

8

DR,DL

8S

J

35

Octal D Register

54LS/74LS273

8

8S

J

30

Octal D Flip-Flop (3S2)

54LS/74LS374

8

8S

J

35

Octal D Flip"Flop

54LS/74LS377

8

8S

J

30

Octal D Flip-Flop (3S2)

54LSn4LS574

8

8S

...r

35

Successive Approx
Register

54LSn4LSS04

12

D

J

15

Serial-in/Serial-out
Shift Right

9328

2X8

2X2D
(MUX)

J

20

Serial-in/Serial-out
Shift Right

93L28

2X8

2X2D
(MUX)

J

5.0

Register File (OC2)

54174170

4X4

4A

\....

Register File (OC2)

54LS/74LS170

4X4

4A

\....

Register File (3S2)

54LS/74LS670

4X4

4A

\....

1.
2.

s = Synchronous; A = Asynchronous
oc = Open-Collector; 3S = 3-State

1-22

PRODUCT INDICES AND SELECTION GUIDES
COUNTERS

FUNCTION

DEVICE NO.

MODULUS

PARALLEL
ENTRY*

CLOCK
EDGE

GUARANTEED
CLOCK FREQ.
MHz

Asynchronous

54174290

2X5

'-

32

Asynchronous

5417490A

2x5

'-

32

Asynchronous

54LS/74LS90

2X5

"'\...

32

Asynchronous

5417492A

2X6

54LS/74LS92

2X6

''-

32

Asynchronous
Asynchronous

54174293

2X8

"'\...

32

Asynchronous

5417493A

2X8

""\....

32

Asynchronous

54LS/74LS93

2X8

"'\...

32

Asynchronous

54/74176

2X5

35

Asynchronous

54174177

2X8

A

''-

Asynchronous

54174196

2X5

A

""'\...

50

Asynchronous

54LS/74LS196

2X5

A

""\....

45

Asynchronous

54/74197

2X8

A

Asynchronous

54LS/74LS197

A

""-

50

2X8

Asynchronous

54LS/74LS290

2X5

""'\...

32

Asynchronous

54LS/74LS293

2X8

'-

32

Asynchronous

54LS/74LS390

2X5

"'\....

40

Asynchronous

54LS/74LS393

2X8

'-

40

Asynchronous

54LS/74LS490

2X5

\...

40

Variable Modulo

9305

2 X 5, 6, 7, 8

J

23

Synchronous

9310

10 (Presettable)

S

93L10

10 (Presettable)

S

Synchronous

93S10

10 (Presettable)

S

Synchronous

9316

16 (Presettable)

S

Synchronous

93L16

16 (Presettable)

S

f
f
f
J
J

30

Synchronous

Synchronous

93S16

16 (Presettable)

S

..r

Synchronous

54/74160

10 (Presettable)

S

.r

25

Synchronous

54LS/74LS160

10 (Presettable)

S

f

25

Synchronous

54174161

16 (Presettable)

S

25

Synchronous

54LS/74LS161

16 (Presettable)

S

J
...r

25

Synchronous

54174162

10 (Presettable)

S

..r

25

Synchronous

54LS/74LS162

10 (Presettable)

S

.r

25

Synchronous

54174163

16 (Presettable)

S

J

25

·s = Synchronous;

A

A = Asynchronous

1-23

32

35

50

13
70
30
13
70

PRODUCT INDICES AND SELECTION GUIDES
COUNTERS (Cont'd)

MODULUS

PARALLEL
ENTRY·

Synchronous

54LS/74LS163

16 (Presettable)

S

Up/Down

54LS174LS168

10 (Presettable)

Up/Down

54LS/74LS169

DEVICE NO.

FUNCTION

GUARANTEED
CLOCK FREQ.
MHz

CLOCK
EDGE

S

..r
..r

25

16 (Presettable)

S

..r

25

A

..r

25

25

Up/Down

54174192

10

Up/Down

54LS/74LS192

10

A

..r

30

Up/Down

54174193

16

A

J

25

Up/Down

54LS/74LS193

16

A

..r

30

Up/Down

54174190

10

A

Up/Down

54LS/74LS190

10

A

Up/Down

54174191

16

A

Up/Down

54LS/74LS191

16

A

Rate Multiplier

54/7497

m.f.l64

Rate Multiplier

54174167

m.f.l10

J
J

20

..r
..r
...r
...r

20

20

20
25
25

MONOSTABLES (ONE-SHOTS)
PULSE WIDTH
VARIATION (%)
FUNCTION

DEVICE NO. vs. TEMP

Single Retriggerable

9600

±1.5

Single Retriggerable

9601

Dual Retriggerable

9602

Dual Retriggerable

96L02

MIN
OUTPUT

NO.OF
INPUTS

vs. Vee

POS

NEG

RESETTABLE

(tw) ns

±1.5

3

2

X

75

±2.7

±1.0

2

2

±1.5

±1.5

1

1

X

72

±1.6

±1.5

1

1

X

110

X

21

50

Dual Retriggerable

96S02

±1.0

±1.0

1

1

Single Non-Retriggerable

54/74121

±0.25

±0.15

1

2

Single Retriggerable

54174122

±2.7

±1.0

2

2

X

Dual Retriggerable

54174123

±2.7

±1.0

1

1

X

45

96LS02

±1.0

±O.B

1

X

35

Dual Retriggerable
·5

= Synchronous;

A

= Asynchronous

1-24

1

40
45

PRODUCT INDICES AND SELECTION GUIDES
LINE AND BUS DRIVERS/TRANSCEIVERS/RECEIVERS
FUNCTION

DEVICE NO.

COMPANION
RECEIVER

10L

los

mA

mA (MIN)

Quad 2 NAND Driver

5417437

Any TTL

48

-20

Quad 2 NAND Driver (OC*)

5417438

96106

48

OC*

Quad 2 NAND Driver (OC*)

96101

96106

80

OC*

Quad 2 NAND Driver

9009

Any TTL

52.8

-40

Dual 2 NAND Driver

5417440

Any TTL

48

-20

Dual 2 NAND Driver

54H174H40

Any TTL

60

-40

Dual 2 NAND Driver

54S174S40

Any TTL

60

-50

54S/74S140

Any TTL

60

-50

Octal Inverting Bus Driver (38*)

54LS/74LS240

Any TTL

64

-40

Octal Inverting Bus Driver (38*)

54S174S240

Any TTL

64

-50

Octal Non-Inverting Bus Driver (38*)

54LS174LS241

Any TTL

64

-40

Dual 2 NAND Driver (50

0)

Octal Non-Inverting Bus Driver (38*)

54S174S241

Any TTL

64

-50

Octal Bus Transceiver

54LS/74LS245

Any TTL

24

-40

Octal Inverting Bus Transceiver

54LS174LS540

Any TTL

64

-40

Octal Non-Inverting Bus Transceiver

54LS/74LSS41

Any TTL

64

-40

Quad Inverting Bus Transceiver

54LS/74LS242

Any TTL

24

-40

Quad Non-Inverting Bus Transceiver

54LS174LS243

Any TTL

24

-40

Quad Bus Transceiver

96103

96103

70

-18

Quad 2-NOR Receiver

96106

7.8

-18

·oc =

Open-Collector; 3$ = 3-$tate

1-25

•

PRODUCT INDICES AND SELECTION GUIDES
DISPLAY DECODER/DRIVERS

FUNCTION

1-of-10 Cold Cathode
(CC")

DEVICE NO.

OUTPUT
OUTPUT
CURRENT VOLTAGE
mA
V

BLANKING
RIPPLE
ABOVE BCD
BLANKING
9-INPUT

9315 (54/7441)

7.0

1-of-10 Cold Cathode

74141

7.0

55

L

X

1-of-10 Driver (CC")

9302

16

5.5

L

X

1-of-10 Driver (C.C")

54/7445

80

30

L

X

1-of-10 Driver (CC")

54174145

7-Seg Decoder

9307

7-Seg Decoder

54/7448

55

ACTIVE
HIGH/LOW

L

80

15

L

12.5

5.5

H

X

1.3

5.5

H

X

X

7-Seg Decoder (CC')

5417449

10

5.5

H

X

7-Seg Decoder/Driver

9317B

40

20

L

X

X

7-Seg Decoder/Driver

9317C

20

30

L

X

X

7-Seg Decoder/Driver
(CC')

54/7446A

40

30

L

X

7-Seg Decoder/Driver
(CC')

54/7447A

40

15

L

X

7-Seg Decoder/Driver
(CC')

54LS/74LS47

24

15

L

X

7-Seg Decoder/Driver

54LS/74LS48

1.3

5.5

H

X

7-Seg Decoder/Driver
(CC')

54LS/74LS49

8.0

5.5

H

X

7-Seg Decoder/Driver
(CC")

54LS/74LS247

24

15

L

X

7-Seg Decoder/Driver

54LS/74LS248

1.3

5.5

H

X

7-Seg Decoder/Driver
(CC')

54LS/74LS249

8.0

5.5

H

X

7-Seg Decoder/Driver
(CC")

54LS/74LS347

24

7.0

L

X

7-Seg Decoder/Driver
(CC")

54LS/74LS447

24

7.0

L

X

7-Seg LED Driver
Common Cathode

9368

20

1.7

H

X

7-Seg LED Driver
Common Anode (CC')

9370

25

5.5

L

X

7-Seg LED Driver
Common Anode (CC')

9374

15

10

L

X

·oc =

Open-Collector

1-26

PRODUCT INDICES AND SELECTION GUIDES
ARITHMETIC OPERATORS
DEVICE NO.

FUNCTION

DESCRIPTION

NO. OF BITS

Adder

54/7480

Gated 1-Bit with Carry

1

Adder

9304

Dual 1-Bit with Carry

2

Adder

54H174H183

Dual 1-Bit with Carry

2

Adder

5417482

Full 2-Bit with Carry

2

Adder

5417483A

Full Binary 4-Bit with Carry

4

Adder

54LS174LS83A

Full Binary 4-Bit with Carry

4

Adder

54/74283

Full Binary 4-Bit with Carry

4

Adder

54LS174LS283

Full Binary 4-Bit with Carry

4

Arithmetic Logic Unit

9340

ALU with Internal CLA*

4

Arithmetic Logic Unit

9341 (54/74181)

ALU with External CLA*

4

Arithmetic Logic Unit

93L41

ALU with External CLA*

4

Arithmetic Logic Unit

54LS/74LS181

ALU with External CLA*

4

Arithmetic Logic Unit

93S41

ALU with External CLA*

4

Carry Lookahead

9342 (54174182)

CLA generator for 9341

Carry Lookahead

93S42 (54S/74S182)

CLA generator for 93S41/9405

Comparator

9386 (8242)

4-Bit Indentity Exclusive-NOR (OC*)

4

Comparator

54/7485

4-Bit Magnitude with Expander

4

Comparator

54LS174LS85

4-Bit Magnitude with Expander

4

Comparator

9324

5-Bit Magnitude

5

Comparator

93L24

5-Bit Magnitude

5

Comparator

93S46

6-Bit Identity with Expander

6

Comparator

93S47

6-Bit Identity (OC*)

6

Encoder

9318

Priority 8-Bit with Expander

8

Encoder

93L18

Priority 8-Bit with Expander

Multiplier

9344

Binary 4 X 2-Bit

4X2

Multiplier

93S43

2s Complement

4X2

Multiplier

54LS/74LS384

Serial/Parallel 2s Complement

8

Parity

54174180

8-Bit Parity Generator/Checker

8

Parity

93S62

9-Bit Parity Generator/Checker

9

Parity

9348

12-Bit Parity Generator/Checker

12
9

8

Parity

54LS/74LS280

9-Bit Parity Generator/Checker

True/Complement

54H/74H87

4-Bit True/Complement
Zero/One Element

4

True/Complement

54S/74S135

Dual 2-Bit Exclusive OR/NOR

4

'CLA = Carry Lookahead; OC = Open-Collector

1-27

•

PRODUCT INDICES AND SELECTION GUIDES
RANDOM ACCESS MEMORIES

ORGANIZATION

DEVICE NO.

CHIP
SELECT
ACCESS
TIME-ns
(MAX)
MIUCOM

ADDRESS
ACCESS
TIME-ns
(MAX)
MIL/COM

DESCRIPTION

READ/WRITE
CYCLE TIME
MIL
COM
O°C to +70°C -55°C to +125°C
ns (MAX)
ns (MAX)

TTL
16 X 4

1 7489

1

oel

1

60/60

1

50/50

1

115

1

115

SCHOTTKY
16 X 4

54S/74S189

351

50135

32/22

55

70

16 X 4

54S/745289

oel

50135

25/17

55

70

LOW POWER SCHOTTK,(
16 X 4

54Lsn4LS89

oel

37/372

10/102

722

722

16 X 4

54LS/74LS189

351

37/372

10/102

722

722

16 X 4

54Lsn4LS289

oel

37/372

10/102

722

722

1. OC = Open-Collector; 3S = 3-State
2. Typical Value

1-28

SECTION 2
• Glossary
• Logic Symbols and Terminology

• TTL Circuit Families
• Input Characteristics
• Unused Inputs
• Output Characteristics
• Increasing Fan-Out
• 3-State Outputs
• Open-Collector Outputs
• Thresholds and Noise Margins
• Crosstalk
• Transmission Lines
• Transmission Line Effects
• Backplane Data Bus
• Decoupling
• Grounds
• Supply Voltage and Temperature
• Interfacing

TTL CHARACTERISTICS

Section 2
TTL CHARACTERISTICS
GLOSSARY
Currents - Positive current is defined as conventional current flow into a device. Negative current is defined as
conventional current flow out of a device. All current limits are specified as absolute values.

lee

Supply Current - The current flowing into the Vee supply terminal of a circuit with the specified
input conditions and the outputs open. When not specified, input conditions are chosen to guarantee worst case operation.

hH

Input HIGH Current-The current flowing into an input when a specified HIGH voltage is
applied.

hl

Input LOW Current - The current flowing out of an input when a specified LOW voltage isapplied.

10H

Output HIGH Current - The leakage current flowing into a turned off open-collector output with
a specified HIGH output voltage applied. For an output with an internal pull-up circuit, the 10H
is the current flowing out of the output when it is in the HIGH state.

10l

Output LOW Current - The current flowing into an output when it is in the LOW state.

los

Output Short Circuit Current - The current flowing out of a HIGH-state output when that output
is short circuited to ground (or other specified potential).

10ZH

Output OFF Current HIGH - The current flowing into a disabled 3-state output with a specified
HIGH output voltage applied.

10Zl

Output OFF Current LOW - The current flowing out of a disabled 3-state output with a specified
LOW output voltage applied.

Voltages-All voltages are referenced to the ground pin. Negative voltage limits are specified as absolute
values (i.e., -10 V is greater than -1.0 Vl.
Vee

Supply Voltage - The range of power supply voltage over which the device is guaranteed to
operate within the specified limits.

VeD(Max)

Input Clamp Diode Voltage - The most negative voltage at an input when a specified current
is forced out of that input terminal. This parameter guarantees the integrity of the input diode,
intended to clamp negative ringing at the input terminal.
Input HIGH Voltage - The range of input voltages that represents a logic HIGH in the system.

VIH(Min)

Minimum Input HIGH Voltage- The minimum allowed input HIGH in a logic system. This value
represents the guaranteed input HIGH threshold for the device.
Input LOW Voltage - The range of input voltages that represents a logic LOW in the system.

Vll(Max)

Maximum Input LOW Voltage - The maximum allowed input LOW in a system. This value represents the guaranteed input LOW threshold for the device.

2-3

•

TTL CHARACTERISTICS
GLOSSARY (Cont'd)
VOH(Min)
Output HIGH Voltage - The minimum voltage at an output terminal for the specified output current IOH and at the minimum value of Vee.
VOL(Max)

Output LOW Voltage - The maximum voltage at an output terminal sinking the maximum specified load current IQL.

VT+

Positive-Going Threshold Voltage - The input voltage of a variable threshold device (Le., Schmitt
Trigger) that is interpreted as a VIH as the input transition rises from below VT-(Min).

VT-

Negative-Going Threshold Voltage - The input voltage of a variable threshold device (Le., Schmitt
Trigger) that is interpreted as a VIL as the input transition falls from above VT+(Max).

AC Switching Parameters
fmax

Toggle Frequency/Operating Frequency - The maximum rate at which clock pulses may be applied to a sequential circuit. Above this frequency the device may cease to function.

tPLH

Propagation Delay Time - The time between the specified reference points, normally 1.5 V (1.3 V
for LS) on the input and output voltage waveforms, with the output changing from the defined LOW
level to the defined HIGH level.

tPHL

Propagation Delay Time - The time between the specified reference points, normally 1.5 V (1.3 V
for LS) on the input and output voltage waveforms, with the output changing from the defined
HIGH level to the defined LOW level.

tw

Pulse Width - The time between 1.5 V (1.3 V for LS) amplitude pOints on the leading and trailing
edges of a pulse.

th

Hold Time - The interval immediately following the active transition of the timing pulse (usually
the clock pulse) or following the transition of the control input to its latching level, during which
interval the data to be recognized must be maintained at the input to ensure its continued recognition. A negative hold time indicates that the correct logic level may be released prior tothe active
transition of the timing pulse and still be recognized.

ts

Setup Time - The interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or preceding the transition of the control input to its latching level, during
which interval the data to be recognized must be maintained at the input to ensure its recognition.
A negative setup time indicates that the correct logic level may be initiated sometime after the
active transition of the timing pulse and still be recognized.

tpHZ

Output Disable Time (of a 3-State Output) from HIGH Level- The time between the 1.5 V (1.3 V
for LS) level on the input and a voltage 0.5 V below the steady state output HIGH level with the
3-state output changing from the defined HIGH level to a high impedance (off) state.

tPLZ

Output Disable Time (of a 3-State Output) from LOW Level- The time between the 1.5 V (1.3 V
for LS) level on the input and a voltage 0.5 V above the steady state output LOW level with the 3state output changing from the defined LOW level to a high impedance (off) state.

tPZH

Output Enable Time (of a 3-StateOutput) to a HIGH Level- The time between the 1.5 V (1.3 V for
LS) levels of the input and output voltage waveforms with the 3-state output changing from a high
impedance (off) state to a HIGH level.

2-4

TTL CHARACTERISTICS
GLOSSARY (Cont'd)
tPZL
Output Enable Time (of a 3-State Output) to a LOW Level- The time between the 1.5 V (1.3 V for
LS) levels of the input and output voltage waveforms with the 3-state output changing from a high
impedance (off) state to a LOW level.
tree

Recovery Time - The time between the 1.5 V (1.3 V for LS) level on the trailing edge of an asynchronous input control pulse and the same level on a synchronous input (clock) pulse such that
the device will respond to the synchronous input.

Miscellaneous

C

Marking code letter indicating that the device is guaranteed to meet the specifications for the
Commercial temperature range.

D

Package code letter for ceramic Dual In-line Packages.

F

Package code letter for ceramic flatpaks.

M

Marking code letter indicating that the device is guaranteed to meet the specifications for the
Military temperature range.

P

Package code letter for plastic Dual In-line Packages.

OB

Marking code indicating in-house 3851"0, level B reliability screening (military grade only).

OM, OR

Marking code indicating Matrix VI commercial/industrial reliability screening.

XC, XM

Shorthand for the commercial or military temperature range specifications or devices: the letter X
stands for the code letter of any package in which the device is available.

2-5

TTL CHARACTERISTICS
LOGIC SYMBOLS AND TERMINOLOGY
The logic symbols used to represent the MSI devices follow Mil Std 8068 for logic symbols. MSI elements are
represented by rectangular blocks with appropriate external AND/OR gates when necessary. A small circle at
an external input means that the specific input is active LOW; i.e., it produces the desired function, in
conjunction with other inputs, if its voltage is the lower of the two logic levels in the system. A circleat the output
indicates that when the function designated is True, the output is LOW. Generally, inputs are at the top and left
and outputs appear at the bottom and right of the logic symbol. An exception is the asynchronous Master Reset
in some sequential circuits which is always at the left hand bottom corner.
Inputs and outputs are labeled with mnemonic letters as illustrated in Table 2-1. Note that an active LOW
function labeled outside of the logic symbol is given a bar over the label, 'while the same function inside the
symbol is labeled without the bar. When several inputs or outputs use the same letter, subscript numbers
starting with zero are used in an order natural for device operation.
This nomenclature is used throughout this book and may differ from nomenclafure used on other data books
(notably early 7400 MSJ), where outputs use alphabetic subscripts or use number sequences starting with one.

TABLE 2-1
LABEL

MEANING

EXAMPLE
10

Ix

General term for inputs to combinatorial circuits.

J, K
S, R
D

Inputs to JK, SR, and D flip-flops and latches.

Ax, Sx

Address or Select inputs, used to select an input,
output, data route, junction, or memory location.

11

So

12

s,

p

Parallel data inputs to shift registers and counters.

2-6

2

3

4

9312

9301

Enable, active LOW on all TTL/MSI. A latch can receive
new data when its Enable input is in the active state.

Parallel Enable, a control input used to synchronously
load information in parallel into an otherwise
autonomous circuit.

1

9324

10

5

6

7

9

TTL CHARACTERISTICS
LOGIC SYMBOLS AND TERMINOLOGY (Cont'd)
TABLE 2-1 (Cont'd)
LABEL

MEANING

EXAMPLE

lrLll

PL

Parallel Load; similar to Parallel Enable except that PL overrides
the clock and forces parallel loading asynchronously.

PL Po p, P2 P3
CPo
74196
CP,

8--<:
6--<:

MR 00 Q1 Q2 03

X!!!)2

1 iii i

MR

Master Reset, asynchronously resets ali outputs to zero, overriding ali other inputs.

PE Po p, Pz P3
7 - CEP

'0- CEl

2-

9310

r--'5

TC

CP
MR 00 Q, 02 03

T,~ ,l ,12 ,I,
,CL

Clear, resets outputs to zero but does not override all other inputs.

23-

X

Y
D

E
Ao
9334

A,

A2
CL 00 0, 02 03 04 05

as

Q7

! 1 ~ i ~ LID ,1, 12
CP

CE, CEP,
CET

Clock Pulse, generally a HIGH-to-LOW-to-HIGH transition. An
active HIGH clock (no circle) means outputs change on LOW-toHI GH clock transition.

1iii i

PE Po P, P2 P3
7 - CEP

'0-

2-

Count Enable inputs for counters.

9316

CET

TC

1--'5

CP
MR 00 0, Q2 03

r,~ ,13 ,12 ,I,
'I'i't iii i I
lOa ha 12a 13a lOb hb 12b 13h

1 3 - So

Zx, OX, Fx General terms for outputs of combinatorial circuits.

ax

TC

OE

General term for latch and flip-flop outputs. If they pass through
an enable gate before exiting the package, a or Q changes
to 0 or O.
Terminal Count output (1111 for up binary counters, 1001 for up
decimal counters, or 0000 for down countersl.

Output Enable, used to force 3-state outputs into the high impeddance state.

9309

3 - 5,
Z,

Z,

,~

,15

Zb

r !

l iii i

PE Po p, P2 P3
7 - CEP

'0- CET

2-

9310

TC

1--'5

CP
MR 00 Q1 02 03

1,~ ,~ ,~ ,I,

~l'jr'f
IE

Do 01 02 03

7 - CP

'b[)
2-02

74173
OE

MR 00

,~
2-7

Zb

0,

02

03

r 1l l

TTL CHARACTERISTICS
TTL CIRCUIT FAMILIES
Each family is designed around certain performance objectives, within the economic limitations of a particular
process. The key performance factors that distinguish the families are power consumption, speed and the
ability to drive wiring capacitance. For com paris on purposes the. power supply current and propagation delay
or switching rate for several popular circuit types in the various families are shown in Table 2-2 below. The
propagation delays are in ns, the supply currents in mA and the toggle frequencies in MHz. All values listed are
worst-case guaranteed, rather than typical figures.
TABLE 2-2
CIRCUIT TYPE
2-lnput NAND
7400

tPLH/tPHL
Icc

TTL

H-TTL

S-TTL

22115

2.0/5.5

10/10
4.2/10

4.5/5.0
4.0/9.0

10/10
0.4/1.1

LP-TTL

LS-TTL

D-Type Flip-Flop
7474

f max
Icc

15
7.0

35
38

75
25

30
4.0

JK Flip-flop

f max
Icc

25
7.0

40
38

80
25

30
4.0

tPLH/tPHL
Icc

14/14
23.5

7.5/6.5
39

22/30
6.6

14/14
8.0

f max
Icc

30
92

70
127

13
27.5

25
32

f max
Icc

30
63

70
120

10
23

30
21

9024/7411217 4H 108

4-lnput Multiplexer
9322174157

Synchronous Counter
9310174160

4-Bit Shift Register
9300174195

45
112

In three of the families - TTL, H-TTL and LP-TTL -the transistors are turned on by applying sufficient base
current for the lowest expected current gain. The average transistor, having greater current gain, receives far
more base current than necessary, which forward biases the collector-base junction and saturates the
transistor. In order to turn off such a saturated transistor, the excess base charge must first be removed,
resulting in considerable delay. Gold doping is commonly used to speed up the charge recombination, but this
decreases the current gain.
Schottky clamped transistors (Figure 2-1) overcome this Ii mitation. They use a surface barrier diode with very
low forward voltage drop (0.3 V) as a bypass between base and collector. When the transistor starts conducting
and is about to become saturated, the excess input current is not fed into the base, but routed through the
Schottky diode into the collector (Baker Clamp), As a result the transistor is never fully saturated and recovers
quickly when the base current is interrupted. Since gold doping is not required, the transistors also have higher
current gain, require less base current, and turn on faster.
As a result of the faster turn-on and recovery, S-TTL circuits achieve roughly twice the speed of H-TTL at about
the same level of power consumption, as indicated in the table. On the other hand, LS-TTL circuits (also
Schottky clamped) use much less power than H-TTL, yet operate at about the same speed. Compared to S-TTL,
LS-TTL processing produces shallower diffusions and smaller transistors with greater bandwidth. Thus, LSTTL circuits operate at about half the speed of S-TTL while using only about 20% as much power.

Fig. 2-1 Schottky Transistor

2-8

TTL CHARACTERISTICS
TTL CIRCUIT FAMILIES (Cont'd)
Schematics of the basic gates of the various families are shown in Figures 2-2 through 2-7. All are similar,
containing an input AND gate, a phase splitter 02 with emitter and collector load resistors, a pull-up mechanism
03/04 and a pull-down transistor 05. In all except the LS-TTL circuit, the AND function is formed by a multiemitter transistor in which the emitter-base junctions serve to isolate the input signal sources from each other
and steer the current from the 4 kO gate resistor. When an input is LOW, the gate current flows out through the
base-emitter junction and 01 is saturated, making the base voltage of 02 only Slightly more positive than the
LOW input voltage, and 02 does not conduct. Moreover, the low emitter-to-collector resistance of 01 in this
condition allows the input signal source to wlthdraw charge from the base of 02 and help toturn it off quickly.
With all inputs HIGH, the gate current flows through the base-collector junction of 01 and turns on 02. In this
situation, a small quantity of charge is injected into the base of 01. Part of this charge recombi nes in the base
region and part of it drifts over to be "collected" by the emitters. This inverse beta current is a significant part of
the input leakage current hH. This same phenomenon occurs when the gate current exits througha LOW input.
Current is injected into the base from the LOW emitter and part of it is collected by the HIGH emitters. An input
signal exceeding the +5.5 V rating applied to one input can cause breakdown between it and a LOW input, with
the possibility of damage or of being biased in a negative resistance region, depending on the source
impedance. Biasing in the negative resistance region can lead to oscillation that is difficult to diagnose.
The phase splitter 02 is so named because the collector and emitter voltages change in opposite directions
when 02 turns on or off. When 02 turns off, the emitter voltage falls and it stops providing base current to the
pull-down transistor 05; Simultaneously the 02 collector voltage rises and pulls up the base of 03. The 03/04
circuitry provides current gain and the low impedance necessary to pull the output up to the HIGH level while
charging wiring capacitance. The amount of current available to charge capacitance is limited by the small
resistor (s) connected from Vee to the collector(s) of 03/04. This charging current shows up as a current spike at
the Vee pin and it is normal practice to add rf bypass capacitors on logic boards to supply this sudden demand
for current and thus prevent negative-going spikes on Vee.
When 02 turns on, the collector voltage falls and pulls down the base of 03; simultaneously 02 emitter voltage
rises and supplies base current to 05. As 05 starts conducting, it begins to discharge load capacitance and pull
the output down to the LOW level. The discharge current shows up as a current spike atthe ground pin and is
one of the principal reasons for recommending that system designers allow generous amounts of ground metal
on circuit boards.

vee

Vee

Fig. 2-2 7410 Gate

Fig. 2-3 9003 Gate

2-9

TTL CHARACTERISTICS
TTL CIRCUIT FAMILIES (Cont'd)
Although Fairchild does not offer LP-TTL gates or flip-flops, the input and output circuitry of Figure 2-4 is
representative of 93L Series MSI. As shown, the resistor values are four times those of Figures 2-2 and2-3. This
decreases the input loading ilL; the output drive capabilityand the power consumption. The speed-power tradeoff is evident from the values listed inthe table for the LP-TTL multiplexer, counter and shift register, compared
to the TTL counterpart.s.
Another speed-power trade-off is evident in the H-TTL gate of Figure 2-5. Compared to Figure 2-2, several
resistor values are halved and the output pull-up changed to a Darlington configuration. As seen from the values
listed in the table, both speed and power consumption are approximately doubled.
The S-TTL gate of Figure 2-6 is quite similar to the H-TTL gate and consumes about the same amount of power,
yet operates at twice the speed. The base of the pull-down output transistor 05 is returned to ground throug h
06 and a pair of resistors instead of through a simple resistor. This arrangement is called a squaring network
since it squares up the transfer characteristics by preventing conduction in the phase splitter 02 until the input
voltage rises high enough to allow 02 to supply base current to 05. The squaring network also improves the
propagation delay by providing a low resistance path to discharge capacitance at the base of OSduring turn-off.
Vee

vee

16k

6k

600

n

320!l

Fig. 2-5 74H10 Gate

Fig. 2-4 LP-TTL Gate
Vee

110n
06

2.8 kn

76011

vee
55 n

A~r---K

01

OUTPUT

y

B--
I
w

+0.75 r----,-----,---.,.-----r-,

LL)

I

0.5 t---S400 GATE

-S5 ol

Cl

'..."

I-

0

0.4

>
~

...

0

125°C

0.3

I-

:;)
Q.

I-

:;)

./

0.2

0

I

-'
0

>

0.1 ~

.....

o
o

~~

S.O

10

~

>

cj ~ ~

~ +0.51---+---+---+::oool!!~9

~

rv,/

g +0.251---+~~;.q---+----I
...~

V"'25°C

~~ /

~

:;)

~

15

O~-~H---~---+-----;

I-

o

I

5

>
20

25

30

35

40

-1.0 '--_ _-'-_ _--1._ _ _- ' -_ _- '
-5.0
+10
+15

45

IOL-OUTPUT LOW CURRENT-rnA

IOL - OUTPUT LOW CURRENT - rnA

Fig. 2-12 TTL Gate Output LOW Characteristics

Fig. 2-13 LS-TTL Gate Output LOW Characteristics

2-13

•

TTL CHARACTERISTICS
OUTPUT CHARACTERISTICS (Cont'd)
In the HIGH state a totem-pole output presents a low impedance and is capable of sourcing considerable
current. Figure 2-14 shows the output HIGH characteristics of a 5400 gate at three temperatures. With no load
current the VOH is about 3.5 Vat 25 0 C. For 10H increasing to about 6.0 mA, the characteristic has the shape of a
fixed voltage minus the logarithmically increasing voltage drop across two pn junctions. For 10H greater than
6.0mA, the pull-up transistor 03 (Figure 2-2) saturates and the slope of the characteristic is just the 1300
current limiting resistor plus the saturation resistance of 03. The maximum 10H current, where the characteristic intersects the horizontal axis, correlates with the short-circuit output current parameter los and is often
regarded as a measure of the circuit's ability to charge line capacitance.
The output HIGH characteristics of the 54S140 Line Driver are shown in Figure 2-15, with the axes oriented
differently than in Figure 2-13. The 'S140 pull-up is a Darlington circuit with a 250 collector resistor to limit the
short-circuit output current. This low resistance allows the 'S140 to source very large values of 10H, as
suggested by the graph. The 'S140 is guaranteed to force a 2.0V signal across a 50 Oload to ground, making it
an attractive circuit for driving long interconnections that must be treated as transmission lines.
Figure 2-16 shows the 54LSOO output HIGH characteristic, which is quite similar to the 5400 gate of Figure 2-14.
Due to the 5.0 kO resistor from 03 to output (Figure 2-7) the LS circuits provide higher output voltage for low
values of IOH, as shown in Figure 2-17. This provides greater protection against negative-going noise on a
quiescent HIGH signal.
4.5

>
I

w

Cl

I

4.0

,r

3.5

~

«

.......
0

3.0
2.5

....
:::I
a.
....
:::I

2.0

I
a
>

w

-40 -Vee =5V
54S140

§

-60

a:

1.5

~

0.5

-80

!;

-100

/.~

I!:

t\.

12rC

5 -120

~

I
J:
E -140

~

-160

5.0
20
25
15
10
iOHr-OUTPUT HIGH CURRENT-mA

30

0

>

/ / l F 5 'c

4.0

"

'- ~

3.0

~

i:

:::I

-55'C2.0

a.
....
:::I
0

I

~~

!-....;::

125'C

'I'

1"-,25'C

o

1.0
2.0
3.0
VaH-OUTPUT HIGH VOLTAGE-V

a
>

o

o

w

4.0

~
g

4.5

4.0

~

J:
CJ

~

Z
!;
II.
!;
o

~t-..

~

1.0

J:

>
I

vle =15) _
54LSOO

'<, ......-25'C

J:
CJ

....

~

5.0

>

«
....
...

~ '--

Fig. 2-15 S-TTL Line Driver Output
HIGH Characteristics

5.0

I

~

); ~r-----55'C
'r
~

Fig. 2-14 TTL Output HIGH Characteristics

w
CJ

~
~

i:

"

1.0

5

'r/J '/

25'l::~ ~

()

-55'C

o
o

-20

I

!z

y--- 25'C

0
I

-5J,C_

~

~'"

Cl

i:

125~C

'.:::: ~

>
J:

r-

Vee = 5 V
5400 GATE-

~
~~

I

I

3.5

~

Vee = 5 V
54LSOO

I

+125'C'-

~
.........

+25'C
-55'C

3.0

~

~~
4.0
8.0
12
16
20
IOH-OUTPUT HIGH CURRENT-mA

2. 5 0

24

Fig. 2-16 LS-TTL Gate Output HIGH Characteristics

2-14

0.1
0.2
0.3
0.4
IOH-OUTPUT HIGH CURRENT-mA

0.5

Fig. 2-17 LS-TTL Gate Output HIGH
Characteristics at Low Loading

TTL CHARACTERISTICS
INCREASING FAN OUT
To increase fan-out, inputs and outputs of gates on the same package may be paralleled. It is advisable to limit
the gates being paralleled to those in a single package to avoid large transient supply currents due to different
switching times of the gates. This is not detrimental to the devices, but could cause logic problems if the gates
are being used as clock drivers.
3-STATE OUTPUTS
In the newer TTL families there are many circuits that have an auxilliary control input whereby both the output
pull-up and pull-down circuitry can be disabled. This condition is called the high impedance (high-Z) state and
allows the outputs of different circuits to be connected to a common line or data bus. A typical 3-state output,
shown in Figure 2-18, has pull-up and pull-down circuitry quite similar to Figure 2-7. The significant difference
is that the enable function is connected through a diode to the base of 03. A LOW signal on the enable turns off
both 02 and 03 and thus disables both the pull-up and pull-down circuitry. In this disabled condition the
outputs are tested for leakage at 2.4 V (loZH) and at 0.4 V or 0.5 V (lOZL) to ensurethat they do not cause excessive
loading on a data bus. When the circuit is in the bi-state mode, i.e., enabled, the output HIGH and LOW
characteristics are the same as those of other circuit types having the same drive capabilities.

~----~----------------~---vcc

*

'Not used in Buffers
"Used only in Buffers

Fig. 2-18 Typical 3-State Output Control

•

TTL CHARACTERISTICS
OPEN-COLLECTOR OUTPUTS
A number of available circuits have no pull-up circuit on the outputs. Some are special purpose, such as the
74141 high voltage display driver, the 7445 high current display driver, the 9370 LED driver or the 96101
terminated bus driver. For circuits of this type, no external pull-up is necessary other than the intended load.
Other open-collector circuits, less dedicated in nature, are used for interfacing orforwired-OR(actuallywiredAND) functions. The latter is achieved by connecting open-collector outputs together and adding an external
pull-up resistor.
The value of the pull-up resistor is determined by considering the fan-out of the OR tie and the number of
devices in the OR tie. The pull-up resistor value is chosen from a range between maximum value (established to
maintain the required VOH with all the OR-tied outputs HIGH) and a minimum value (established so that theOR
tie fan-out is not exceeded when only one output is LOW)'
MINIMUM AND MAXIMUM PULL-UP RESISTOR VALUES
. _(
VCC(Max) - VOL
)
RX(MIn) - IOL - N2(LOW) e 1.6 mA
where:

Rx
N1
N2
IOH = ICEX
IOL

VOL
VOH
Vcc

=
=
=
=
=
=
=
=

VCC(Min) - VOH
)
_ (
RX(Max)- N1 e loH+N2(HIGH)e40,uA

External Pull-Up Resistor
Number of Wired-OR Outputs
Number of Input Unit Loads Being Driven
Output HIGH Leakage Current
LOW Level Fan-Out Current of Driving Element
Output LOW Voltage Level (0.5 V)
Output HIGH Voltage Level (2.4 V)
Power Supply Voltage

Example: Four 74LS03 gate outputs driving four other LS gates or MSI inputs.
R
(5.25V-0.5V
4.75V) 7420
X(Min) = 8.0 mA -1.6 rnA = 6.4 mA =
2.35V \ 49 k"
4.75V -2.4 V
R
X(Max)= ( 4 e 100,uA+2 e 40,uA=0.48rnAj=' u
where:

N1
N2(HIGH)
N2(LOW)
IOH
IOL
VOL
VOH

=4
= 4 e 0.5 U.L. = 2 U.L.
= 4 e 0.25 U.L. = 1 U.L.
= 100 ,uA
= 8.0 rnA
= 0.5 V
= 2.4 V

Any value of pull-up resistor between 7420 and 4.90 can be used. The lower values yield the fastest speeds
while the higher values yield the lowest power dissipation.

2-16

TTL CHARACTERISTICS
THRESHOLDS AND NOISE MARGINS
The noise margins most often cited for TTL are obtained by subtracting the guaranteed maximum input HIGH
level VIH of a driven input from the guaranteed minimum output HIGH level VOH of the driving source, and
subtracting the guaranteed maximum output LOW level VOL of the driver from the guaranteed minimum input
LOW level VIL of a driven circuit. The guaranteed worst-case values of these parameters vary slightly among the
various circuit families and are summarized in Table 2-3. Note that although the 9000 Series VIH and VIL
specifications have different limits at different temperatures (see data sheets), they are grouped with the 54/74
family in the table as a matter of convenience. Note also that the VOL limit listed for 74LS is 0.5 V, whereas these
circuits are also specified at 0.4 V at a lower level of IOL. Noise margins obtained by the aforementioned
subtractions are listed in Tables 2-4 through 2-7, for all combinations of driving and driven circuit types in the
various circuit families. Noise margins calculated in this manner are quite conservative, since it is assumed that
both the driver output characteristics and the receiver input characteristics are worst-case and that Vee is on
the low side for the driver and on the high side for the receiver.
Table 2-3

Parameter Limits
Military
(-55 to +125°C)

Fairchild TTL Families
TTL
H-TTL
LP-TTL
S-TTL
LS-TTL

Standard TTL, 9000, 54/74
High Speed TTL, 54H/74H
Low Power TTL, 93L (MSI)
Schottky TTL, 54S/74S, 93S
Low Power Schottky TTL, 54LS/74LS

Commercial
(0 to +70°C)

VIL

VIH

VOL VOH

VIL

VIH

VOL VOH

0.8
0.8
0.7
0.8
0.7

2.0
2.0
2.0
2.0
2.0

0.4
0.4
0.3
0.5
0.4

0.8
0.8
0.8
0.8
0.8

2.0
2.0
2.0
2.0
2.0

0.4
0.4
0.3
0.5
0.5

2.4
2.4
2.4
2.5
2.5

2.4
2.4
2.4
2.7
2.7

Units
V
V
V
V
V

VOL and VOH are the voltges generated at the output. V,L and V,H are the voltage required at the input to generate the appropriate levels. The
numbers given above are guaranteed worst-case values.

Table 2-4

~

LOW Level Noise Margins (Military)

From

TTL

H-TTL

LP-TTL

S-TTL

LS-TTL

Units

TTL
H-TTL
LP-TTL
S-TTL
LS-TTL

400
400
500
300
400

400
400
500
300
400

300
300
400
200
300

400
400
500
300
400

300
300
400
200
300

mV
mV
mV
mV
mV

From "VOL" to "VIL"

Table 2-5

~

HIGH Level Noise Margins (Military)

From

TTL

H-TTL

LP-TTL

S-TTL

LS-TTL

Units

TTL
H-TTL
LP-TTL
S-TTL
LS-TTL

400
400
400
500
500

400
400
400
500
500

400
400
400
500
500

400
400
400
500
500

400
400
400
500
500

mV
mV
mV
mV
mV

From "VOH" to "VIH"

2-17

•

TTL CHARACTERISTICS

Table 2-6

~

LOW Level Noise Margins (Commercial)

From

TTL

H-TTL

LP-TTL

S-TTL

LS-TTL

Units

TTL
H-TTL
LP-TTL
S-TTL
LS-TTL

400
400
500
300
300

400
400
500
300
300

400
400
500
300
300

400
400
500
300
300

400
400
500
300
300

mV
mV
mV
mV
mV

From "VOL" to "VIL"

Table 2-7

~

HIGH Level Noise Margins (Commercial)

From

TTL

H-TTL

LP-TTL

S-TTL

LS-TTL

UNITS

TTL
H-TTL
LP-TTL
S-TTL
LS-TTL

400
400
400
700
700

400
400
400
700
700

400
400
400
700
700

400
400
400
700
700

400
400
400
700
700

mV
mV
mV
mV
mV

From "VOH" to "VIH"

THRESHOLDS AND NOISE MARGINS (Cont'd)
A more meaningful interpretation of noise margin can be gained by examining the relationship between input
and output voltage of a circuit. Figures 2-19,2-20 and 2-21 show the voltage transfer function of TTL, S-TTL and
LS-TTL inverting gates, respectively. The steepest part of a particular curve, where the output changes rapidly
for small changes in input, is called the threshold region. Input signals above or below this region cause little or
no change in output and thus are of no concern. Problems can occur when an input voltage, whether steadystate, transient or a combination of both, causes an output voltage to rise or fall into the threshold region of its
driven loads. Thus, noise of this magnitude can propagate, which is a useful criterion.
The transfer characteristics of Figures 2-19 through 2-21 are essentially steady-state and thus apply for noise
disturbances of long duration. For short pulses, however, the finite response time of a circuit has an effect on
noise sensitivity. Figure 2-22 illustrates pulse noise immunity of TTL gates of the various families. These data
are obtained by applying positive pulses to an otherwise LOW input and noting the combinations of pulse
amplitude and duration required to cause the output to fall to 2.0 V, which is the guaranteed input HIGH level for
TTL circuits. The curves show that S-TTL responds to the shortest pulses, as might be expected, and that pulse
durations greater than about 4.0 ns have essentailly the same effect as dc input voltge. The curves show that
plain TTL (7400) is the least sensitive to noise pulses, with H-TTL and LS-TTL responses intermediate between
those of 7400 and S-TTL. The flat portion of the various curves shows that LS-TTL is the most sensitive to long
duration pulses, while 7400 is least sensitive. This can also be deduced by comparing the transfer functions of
Figures 2-19 and 2-21; the LS-TTL threshold regions are nearer the left hand axis, indicating that a lowervalue
of input voltage is required to affect the output voltage than is the case with plain TTL.

2-18

TTL CHARACTERISTICS
4.0

-- ~

>
I 3.0
w

5.0

~

Cl

...=>
0

.'ss,b

o'er-- 25'C

f--

75'C-

Vee = 5 V

r---..

25'C

l

-55 C t---

Cl

...


>
I

~ee J5V

...:::l>
...:::l'"

2.0

I

1.0

0

V

\

\

"\

1.0

1\

\

=>

0

o

1.0
2.0
V,N -INPUT VOLTAGE - v

-1.0
0.5

3.0

Fig. 2-19 Voltage Transfer Function of a
9000 Series Gate

0.7

VOUT

-y.,

4.0

Cl

...«
....J

0

>

...:::l
...:::l'"

3.0

VIN-D-VOUT

2.0

0

>
I

2.4

I

w

C
:::l

...

-55'C

\~\

:::;

'"::Ii

0

!

Vee =5V
TA = +25'C

>-

>

VOH

+25'C

\\

1.7

-2.0V

3.0

5.0

w

J\..

Fig. 2-20 Voltage Transfer Function of an
S-TTL Gate

0.1'
-\Lo

>
I

\

0.9
1.1
1.3
1.5
V,N -INPUT VOLTAGE - V

V,N.J -

+125'C

"
\

>

o

I".

\

\

>-

>

~

o

15
20
10
5.0
INPUT PULSE WIDTH - ns

25

Fig. 2-22 Pulse Noise Immunity of TTL Gates

CROSSTALK
Crosstalk, the coupling of energy from one circuit to another via parasitic capacitance and inductance, causes
increased problems in digital systems as the rise and fall times of the circuit decrease. The subject is extremely
complicated, and no simple formula can give correct values in all cases forthe amplitude of noise coupled from
one circuit to another. In some circumstances where the input and output resistances of the circuits are high, a
lumped equivalent circuit model can be drawn and reasonable calculations made. However, when the
connections act as transmission lines, the situation is extremely complicated. TTL elements have a low output
impedance in both HIGH and LOW logic states, and it is very difficult to couple enough energy into a short
interconnection between devices to switch an adjacent circuit erroneously.
Noise introduced via capacitive coupling will have the same polarity as the disturbing signal and its amplitude
will be inversely proportional to the rise or fall time of the disturbing signal. Noise introduced via magnetic
coupling can be of either polarity. Open wire connections between TTL circuits should not be bundled, tied or
routed together.

2-19

TTL CHARACTERISTICS
CROSSTALK (Cont'd)
Long parallel signal wires should be separated by ground wires to minimize coupling, particularly if one leads
to the Clock (or asynchronous Set or Clear) input of a flip-flop, counter orregister.ln the case of ripple counters
such as the 'LS90/'92/'93/,2901'293/'390/'393 and '490, the output of one stage may be internally connected to
the Clock input of the next stage. Excessive coupling between outputs can therefore cause erratic counting.
This situation most often occurs when counter outputs are taken off-card to a display unit by means of flat
cable. In these cases it is best to use every other wire in the cable for ground in order to prevent erratic
operation. In the case of parallel signal wires that do not involve a Clock or Asynchronous Set/Reset input, and
close coupling of signal wires is unavoidable, it is advisable to wait until induced disturbances (following a
signal change on one or more wires) have died out before sampling the data on a line. A disturbance induced in
one wire by a signal change on another will have a time duration equal to twice the propagation delay of the
wires. If two wires are closely coupled over a distance of three feet, involving a propagation delay of perhaps
5.0 ns, for example, an induced disturbance will have a duration of 10 ns.
TRANSMISSION LINES
Practical transmission lines, cables and strip lines used for TTL interconnections have a characteristic
impedance between 500 and 1500. Thus none of the standard or low power TTL circuits can drive a
transmission line, and only the 'S40/'S140 is truly capable of driving a 500 line under worst case condirions.
These considerations, applicable only when the round trip delay of the line is longer than the rise orfall time of
the driving signal (2td > tr), do not affect most TTL interconnections. Short interconnections do not behave like
a resistive transmission line, but more like a capacitive load. Since the rise time of different TTL outputs is
known, the longest interconnection that can be tolerated without causing transmission line effects can easily
be calculated and is listed in Table 2-8 below.

Table 2-8

PC Board Interconnections

TTL FAMILY

RISE TIME

FALL TIME

MAX INTERCONNECTION
LENGTH

93L

14-18 ns

4-6 ns

18 in. (45 cm)

9XXX, 93XX,
54/74

6-9 ns

4-6 ns

18 in. (45 cm)

54H174H,
54LS/74LS

4-6 ns

2-3 ns

9 in. (22.5 cm)

1.8-2.8 ns

1.6-2.6 ns

7.5 in. (19 cm)

54S174S,93S

Assuming 1.7 ns/foot propagation speed, typical for epoxy fiberglass PC boards with Ir

= 4.7.

Slightly longer interconnections show minimal transmission line effects; the longer the interconnections, the
greater the chance that system performance may be degraded due to reflections and ringing. The discussion of
transmission line effects gives additional information on transmission line phenomena on longer lines. Good
system operation can generally be obtained by designing around 100 0 lines. AO.026 inch (0.65 mm) trace on an
epoxy-glass board (~r =4.7) with a ground plane on the otherside represents a 100 0 line. Wire of 28 to 30 gauge
(0.25 mm to 0.30 mm) twisted together forms a twisted pair line with a characteristic impedance of 100 n to
115 n. Wire over ground screen (3/4" squares) gives 150 n to 250 n impedance with a significant improvement in
propagation speed, since the dielectric constant approaches that of air.
Transmission lines are also discussed in the FAIRCHILD ECL DATABOOK, the FAIRCHILD INTERFACE
HANDBOOK and the FAIRCHILD TTL APPLICATIONS BOOK.

2-20

TTL CHARACTERISTICS
TRANSMISSION LINE EFFECTS
The fast rise and fall times ofTTL outputs (2.0 ns to 6.0 ns) produce transmission line effects even with relatively
short « 2 ft) interconnections. Consider one TTL device driving another, and the driver switching from the LOW
to the HIGH state. If the propagation delay of the interconnection is long compared to the rise time of the signal,
the arrangement behaves like a transmission line driven by a generator with a non-linear output impedance.
Simple transmission line theory shows that the initial voltage step at the output just after the driver has
switched is

where Zo is the characteristic impedance of the line, Ro is the output impedance of the driver, and VE is the
equivalent output voltage source in the driver, Vee minus the forward drop of the pull-up transistors.
Figure 2-23 shows how the initial voltge step can be determined graphically by superimposing lines of constant
impedance on the static input and output characteristics of TTL elements. The constant impedance lines are
drawn from the intersection of the VIN and VOL characteristics, which is the quiescent condition preceding a
LOW-to-HIGH transition. Afterthis transition the VOH characteristic applies, and the intersection of a particular
impedance line with the VOH characteristic determines the initial voltage step. The VOH characteristic shown in
Figure 2-23 has an Ro of about 80 nand VE of approximately 4.0 V, for calculation purposes.

ImA
30
20

VOL

10

6.0

-1.0

VOLTS

\
\zo=son

Fig. 2-23 Initial Output Voltage of TTL Driving Transmission Line

2-21

TTL CHARACTERISTICS
TRANSMISSION LINE EFFECTS (Cont'd)
This initial voltage step propagates down the line and reflects at the end, assuming the typical case where the
line is open-ended or terminated in an impedance greater than its characteristic impedance Zoo Arriving back at
the source, this reflected wave increases VOUT. If the total round-trip delay is larger than the rise time of the
driving signal, there is a staircase response at the driver output and anywhere along the line. If one of the loads
(gate inputs) is connected to the line close to the driver, the initial output voltage VOUT might not exceed VIH.
This input is then undetermined until after the round trip of the transmission line, thus slowing down the
response of the system. Figure 2-24 shows the driver output waveform for four different line impedances. For Zo
of 25 nand 50 n the initial voltage step is in the threshold region of a TTL input and the output voltage only rises
above the guaranteed 2.0 V VIH level after a reflection returns from the end of the line. If VOUT is increased to
> 2.0V by either increasing Zo or decreasing Ro, additional delay does not occur. Ro is a characteristic of the
driver output configuration, varying between the different TTL speed categories. Zo can be changed by varying
the width of the conductor and its distance from ground. Table 2-9 lists the lowest transmission line impedance
that can be driven by different TTL devices to insure an initial voltage step of 2.0 V. Note that the worst case
value, assuming a +30% tolerance on the current limiting resistor and a -10% tolerance on Vee, is 80% higher
than the value for nominal conditions.

Table

2~9

Transmission Line Drive Capability
Lowest Transmission Line Impedance n

TTL FAMILY OR
DEVICE

54/74

9XXX,93XX
54H174H

54S/74S
93L
9009

544017440
54H/74H40
54S174S40
54S140174S140
Supply.Voltage (Vee)

COLLECTOR
RESISTOR
Rn

WORST CASE
(R + 30%)

130
80
58
55
320
50
100
60
25

241.4
148.5
107.7
110.0
594.2
92.8
185.7
111.4
50.0
I
I

1

I
I
I
I
I

4.50

I

NOMINAL

204.8
126.0
91.3
92.2
504.2
78.7
157.5
94.5
41.9

136.8
84.2
61.0
61.1
336.8
52.6
105.2
63.1
27.7

84.6
52.0
37.7
37.5
208.3
32.5
65.1
39.0
17.0

4.75

5.00

5.25

1
I ..
I

1

75.8
46.6
33.8
33.4
186.6
29.1
58.3
35.0
15.2

I

.,

5.50

I

I

,..

BEST CASE
(R - 30%)

Commercial grade
range
Military grade
range

.-

A graphical method provides excellent insight into the effects of high speed digital circuits driving interconnections acting as transmission lines. The method is basically to draw a load line for each input and output
situation. Each load line starts at the previous quiescent point, determined where the previous load line cuts the
appropriate characteristic. The magnitude of the slope of the load lines is identical and equal to the
characteristic impedance of the line, but alternate load lines have opposite signs representing the change in
direction of current flow. The pOints where the load lines cut the input and output characteristics represent the
voltage and current value at the input or output, respectively, for that reflection. This method, illustrated in
Figure 2-25, is shown with and without the input diode, and illustrates how the input diode on TTL elements
assists in eliminating spurious switching due to reflection.

2-22

TTL CHARACTERISTICS
5.0
4.0

~--~--~-----~~-----~~ns

•

~--'---~-----~-----~--ns

__

--~---k-----~-----~--ns

~

__

~--~------k-----~

100

50

__ ns

150

Fig. 2-24 TTL Driving Transmission Line
ImA
80

OUTPUT A

70

VOLTS
4

60

- - THEORETICAL
--ACTUAL

3
2

WITH
INPUT
DIODE

4+-~~+-~~~~~~~0

-1

NANO'"
I
,
I
,
,
I
'
SECONDS 0 20 40 60 80100120140160180
Zo=140nSLOPE
INPUTB'

4

- - THEORETICAL
--ACTUAL

V
VOLTS

VOLTS
4

3
2

WITHOUT
INPUT

--tt---t---7r-fr-~::-::;"e;---1 0 DIODE
-1

-2
-30
NANO""
I
I
,
I
,
,
SECONDS 0 20 40 60 80100120140160180

Fig. 2-25 Ringing Caused by Reflections

2-23

-3

TTL CHARACTERISTICS
BACKPLANE DATA BUS
Unterminated lines can impose a limitation on .maximum data rate because of the waiting time required for
reflections and ringing to damp out. For higher data rates, wherein terminations are required to control
reflections, a common technique is to use open-collector drivers and terminate each end of a signal wire with a
resistive divider between Vee and ground as shown in Figure 2-26. To terminate a 120 n twisted pair, for
example, a 180 n resistor to Vee and a 390 n resistor to ground offers a Thevenin equivalent resistance of 123 n
and a no-load voltage of 3.4 V with a Vee of 5.0 V. Under nominal conditions and assuming a quiescent LOW
level of 0.5 V, a driver must be able to sink about 24 mA from each end of the line, or 48 mA total. The quiescent
LOW current flowing in the line furnishes the pull-up mechanism when a driver turns off. When the quiescent
current is interrupted, a voltage change is generated whose magnitude is the product ofthe line impedance and
the current. Thus the interruption of 24 mA flowing in a 120 n line causes a voltage rise of about 2.9 V, from the
quiescent 0.5 V to 3.4 V. With variations in Vee and resistor tolerances, the quiescent LOW current can be
considerably more than 48 mA, and a circuit such as the 96101 Quad Bus Driver, which is guaranteed to sink
80 mA, is recommended. The96106 Quad NOR has higher noise margin and lower input loading than other TTL
gates and is therefore well suited as a line receiver. The 96103 Quad Transceiver combines the input attributes
of the 96106 with an open-collector driver capable of sinking 70 mAo
For communications between subsystems that are located in separate enclosures, wherein attenuation and
noise are important factors, the general practice is to use specialized drivers and receivers. Drivers with
complementary outputs·, such as the 9614, 9634 or 9638, can drive terminated twisted pair lines. Line receivers
with differential inputs·, such as the 9615, 9620 or 9637 provide good common-mode noise rejection and
accommodate attenuated input signals.
DECOUPLING
Decoupling capacitors should be used on every pc card, at least one for every 5 to 10 standard TTL packages,
one for every five 74H and 745 packages and one for every one-shot (monostable), line driver and line receiver
package. They should be good quality rf capacitors of 0.01 /IF to 0.1 /IF with short leads. It is particularly
important to place good rf capacitors near sequential (bistable) devices. In addition, a larger capacitor
(preferably a tantalum capacitor) of 2.0 /IF to 20 /IF should be included on each card.
GROUNDS
A good ground system is essential for a pc card containing a large number of packages. The ground can either
be a good ground bus, or better yet, a ground plane which, incorporated with the Vee supply, forms a
transmission line power system. Power transmission systems, which can be attached to a pc card to give an
excellent power system without the cost of a multilayer pc card, are commercially available. Ground loops on or
off pc cards are to be avoided unless they approximate a ground plane.
--

96101 DRIVERS

+5.0 V

+5.0 V

180n

180n

390n

390 n

96108 RECEIVERS

Fig. 2-26 High Speed Backplane Data Bus Using
Twisted Pair or Flat Cable

"Refer to FAIRCHILD LINEAR INTEGRATED CIRCUIT DATA BOOK

2-24

TTL CHARACTERISTICS
SUPPLY VOLTAGE AND TEMPERATURE
The nominal supply voltage Vcc for all TTL circuits is +5.0 V. Commercial grade parts are guaranteed to
perform with ±5% supply tolerance (±250 mY) over an ambient temperature range of O°C to 75°C (some to
70°C). Mil grade parts are guaranteed to perform with a ±10% supply tolerance (±500 mY) over an ambient
temperature range of -55°C to 125°C.
The actual junction temperature can be calculated by multiplying the power dissipation of the device with the
thermal resistance of the package and adding it to the measured ambient temperature TA or package (case)
temperature Tc.
Table 2-1 lists some of the standard Dual In-line Packages (DIP) and Flatpaks used by Fairehild, including
typical junction-to-ambient thermal resistance 6JA and typical junction-to-case thermal resistance 6Jc.
Designers should bear in mind that localized temperatures can rise well above the general ambient in a system
enclosure. On a large pc board mounted in a horizontal plane, for example, the local temperature surrounding
an IC in the middle of the board can bequite high duetothe heating effect ofthe surrounding packages and the
very poor natural convection. Low velocity forced air cooling is usually sufficient to alleviate such stagnant
air conditions.

Table 2-10 Thermal Resistances
PACKAGE

6JA,oC/W

6JC,oC/W

14-Pin Flatpak
16-Pin Flatpak
24-Pin Flatpak

128
123
90

50
47
44

14-Pin CerDIP
16-Pin CerDIP
24-Pin CerDIP

115
100
60

35
30
25

14-Pin Plastic DIP
16-Pin Plastic DIP
24-Pin Plastic DIP

125
120
74

48
45
40

Example: A 9301 in CerDIP dissipates typically 145 mW. At +55°C ambient temperature the junction
temperature is:
TJ

= (0.145 X 100) + 55 = 70°C

INTERFACING
All circuits in the Fairchild TTL families, in fact all TTL devices presently manufactured, are compatible. Any
TTL output can drive a certain number of TTL inputs, as described in Section 3. There are only subtle
differences in the worst case noise immunity when low power, standard and Schottky TTL circuits are
intermixed. Open-collector outputs, however, require a pull-up resistor to drive TTL inputs reliably, as
discussed earlier.
While TTL is the dominating logic family, and many systems use TTL exclusively, there are cases where
different semiconductor technologies are used in one system, either to improve the performance or to lower the
cost, size and power dissipation. The following explains how TTL circuits can interface with DTL, ECL (CMU,
CTL, and discrete transistors.
Interfacing TTL and DTL - Both DTL and TTL are current sinking families, operating on a +5.0 V supply. They
interface perfectly. When TTL drives DTL, one DTL input represents 1 U.L. in the LOW state, much less than
1 U.L. in the HIGH state. When DTL drives TTL, a 2 kO output has a drive capability of 8 U.L., a 6 kO output has
a drive capability of 4 U.L.

2-25

TTL CHARACTERISTICS
INTERFACING (Cont'd)
Interfacing TTL and ECL - Mixing ECL and TTL logic families offers the design engineer a new level of
freedom and opens the entire vhf frequency spectrum to the advantages of digital measurement, control and
logiC operation.
The chief advantages of emitter coupled logic are high speed, flexibility, design versatility and transmission
line compatibility. But application and interfacing cost problems have traditionally discouraged the use of ECL
in many areas, particularly in low cost, less sophisticated systems. Using 95K or 10K compensated ECL with
new ECL/TTL interface devices and several new interfacing methods promises to extend the advantages of
ECL to many low cost systems.
The most practical interfacing method for smaller systems involves using a common supply of+5.0 V to +5.2 V.
Care must be exercised with both logiC families when using this technique to assure proper bypassing of the
power supply to prevent any coupling of noise between circl.lit families. If only a few 95K or 10K ECL packages
are designed into a predominantly TTL system the safest method is to use a 0.01 f.lF miniature ceramic
capacitor across each ECL device. This value capacitor has the highest Q, or bypassing efficiency. When larger
systems are operated on a common supply, separate power busses to each logic family help prevent problems.
Otherwise, good high frequency bypassing techniques are usually sufficient.
95K series ECL devices are fully compensated sq that input thresholds and output levels are immune to broad
variations in ambient temperature and supply voltage. This feature makes it easier to interface with TTL and to
operate with the TTL power supply. 95K and 10K devices have high input impedance with input pull-down
resistors (> 20 knl to the negative supply. In the TTL to ECL interface circuits in Figure 2-27 it is assumed that
the ECL devices have high input impedance.
9500 series ECL elements are temperature compensated and have internal 2 kn pull-down resistors at each
input and output. These resistors provide partial termination of interconnecting transmission lines, in many
cases eliminating the need for external terminations. For ECL inputs with 2·kH pull-down reSistors, the 750 n
resistors shown in the TTL to ECL circuits should be changed to 1.2 kH in orderto provide the proper ECL input
signal levels.
All circuits described operate with ±5% ECL and ±10% TTL supply variations, except those with ECL and TTL
on a common supply. In.those cases the supply can be ±10% with95K or 10K ECL, ±5% with 9500 series ECL.
All resistors are 1/4 W, ±5% composition type.
TTL to ECL conversion is easily accomplished with resistors, which simultaneously attenuate the TTL signal
swing, shift the signal levels, and provide low impedance for damping and immunity to stray noise pick-up. The
resistors should be located as near as possible to the ECL circuit for optimum effect. The circuits in Figure 2-27
assume an unloaded TTL gate as the standard TTL source. ECL input impedance is predominately capacitive
(= 3 pF); the net RC time constant of this capacitance with the indicated resistors assures a net propagation
delay governed primarily by the TTL signal.
+5V

470

n

750

n
-5.2 V

Fig. 2-27 TTL to ECL Conversion

2-26

TTL CHARACTERISTICS
INTERFACING (Cont'd)
When interfacing between high voltage-swing TTL logic and low voltage-swing ECl logic. the more difficult
conversion is from ECl to TTL. This requires a voltage amplifier to build up the 0.8 V logic swing to a minimum
of 2.5 V. The circuits shown in Figure 2-28 may be used to interface from ECl to TTL.
The higher speed converters usually have the lowest fan-out - only one or two TTL gates. This fan-out can be
increased simply by adding a TTL buffer gate to the output of the converter. Another option. if ultimate speed is
required. is to use additional logic converters.
Interfacing TTL and CTL - CTl (Complementary Transistor logic) is a family of high speed digital circuits
used mainly in computers. It uses AND gates and"wired-OR outputs for logic flexibility. but logiC levels are not
restored in each gate. level restoring buffers (956) are therefore required. and all interfacing should be done
with restored logic levels. The CTl input threshold is'" 1 V. similar to TTL. but 1.0 rnA to 2.0 rnA are required to
pull the CTl input reliably over the threshold. A normal TTL output can drive a CTl input. but noise immunity is
improved considerably by a 1 kn pull-up resistor (Figure 2-29). The CTl output emitter follower can source
>30 rnA but cannot sink current. A resistive termination is therefore required. When the resistor is returned to
ground. it may not exceed 250 n to guarantee a VOL of < 400 mV at a fan-out of 1 U.L. A better. less power
consuming way for a fan-out of 1 U.L. is to use the built-in pull-down resistor (1 kn to -2.0 Vl. For increased fanout. this resistor can be reduced by a parallel external resistor to 180 n (8 U.U. as indicated in Figure 2-30.

r---------------,
I

vcc= ..... v

CTL

I

••

I
I

.

I
I

,

I
I

220n

I

I

l--~-------B

COMMON POWER SUPPLY

VeE = -2 V
OR QROUND

TTL TO CTL

Fig. 2-29 TTL to CTL Conversion

r--------------,
I

CTL

I

I
I

••

24GB

••

I
I

·5.' V
SEPARATE POWER SUPPLIES

I
I

1 kU

I

Fig. 2-28 ECl to TTL Conversion

I
L ___-=-_______ _
CTL TO TTL

I

__ ...1
VEe =-2V

ADDITIONAL PULL-DOWN
RESISTOR FOR INCREASED

FAN OUT

Fig. 2-30 CTL to TTL Conversion

2-27

TTL CHARACTERISTICS
INTERFACING (Cont'd)
Interfacing TTL and CMOS - With a 5.0 V power supply, a B Series (buffered) CMOS output is guaranteed to
sink 0.4 mA at VOL = 0.4 V, which matches the input requirements of a standard LS-TTL input. If the CMOS
supply voltage Voo is greater than 5.0 V, the LS-TTL input must be one having an input diode, as opposed to an
emitter. This insures that the high VOH of CMOS (=- Voo) will not cause breakdown of the LS-TTL input. A CMOS
input threshold VIH may be as high as 70% of Voo, while its VIL will be no lower than 30% of Voo. Thus a TTL
output signal is satisfactory at the LOW level, but a pull-up resistor is required to ensure an adequate HIGH level
for the CMOS input. The resistor should connect to the CMOS Voo supply, and if this exceeds 5.5 V, the TTL
driver must have the capability of not conducting appreciably at this higher voltage. Most LS-TTL outputs can
withstand 10 V, as discussed in Section 3.
TTL Driving Transistors - Although high voltage, high current ICs, such as the 9644, are available, it is
sometimes necessary to control greater currents or voltages than integrated circuits are capable of handling.
When this condition arises, a discrete transistor with sufficient capacity can be driven from a TTL output.
Discrete transistors are also used to shift voltages from TTL levels to logic levels for which a standard interface
driver is not available.
The two circuits of Figure 2-31 show how TTL can drive npn transistors. The first circuit is the most efficient but
requires an open-collector TTL or DTL output. The other circuit limits the output current from the TTL totempole output through a series resistor.
Shifting a TTL Output to Negative Levels - The circuit of Figure 2-32 uses a pnp transistor to shift the TTL
output to a negative level. When the TTL output is HIGH, the transistor is cut off and the output voltage is -Vx.
When the TTL output is LOW, the transistor conducts and the output voltage is

if the transistor is not saturated, or slightly positive if the transistor is allowed to saturate.

----~~-------.------------------Vee

Vee

R2
R3 =R2

R3

+-------+-------VOUT

OPEN COLLECTOR
TTL OR DTL

R1

Ib > 10 mA.

-vx

Fig. 2-32 PNP Transistor Shifting TTL Output

Fig. 2-31 TTL Driving NPN Transistors

2-28

TTL CHARACTERISTICS
INTERFACING (Cont'd)
High Voltage Drivers - A TTL output can be used to drive high voltage, low current loads through the simple,
non-inverting circuits shown in Figure 2-33. This can be useful for driving gas discharge displays or small
relays, where the TTL output can handle the current but not the voltage. Load current should not exceed
(IOL-4)mA.
Transistors Driving TTL -It is sometimes difficult to drive the relatively low impedance and narrow voltage
range of TTL inputs directly from external sources, particularly in a rough, electrically noisy environment. The
circuits shown in Figure 2-34 can handle input signal swings in excess of ±100 V without harming the circuits.
The second circuit has an input RC filter that suppresses noise. Unambiguous TTL voltage levels are generated
by the positive feedback (Schmitt trigger) connection.

vee
VL
9301 1/10 DECODER

>

Vee Vee

1k
1 kO

TO OTHER DISPLAYS

Fig. 2-33 Non-Inverting High Voltage Drivers

Vee
10 kll

Vee

100 kll

10 kO

10 kO

5.6 kll

Fig. 2-34 Transistors Driving TTL

2-29

•

SECTION 3
• Unit Loads (U.L.l
• Absol~te Maximum Ratings
• Recommended Operating Conditions
• DC Characteristics Tables
54XX. 74XX & 93XX Family DC Characteristics
54H. 74H. & 93H Family DC Characteristics
54$. 74S & 93S Family DC Characteristics
54LS. 74LS & 96LS Family DC. Characteristics
9XXX Family DC Characteristics
93L Family DC Characteristics
• AC Loading and Waveforms
AC Loads for SSI Gates Waveforms

Section 3

LOADING, SPECIFICATIONS AND WAVEFORMS

This section contains dc specifications and ratings common to all devices in each family of circuits. These
specifications plus the distinctive characteristics given in the individual data sheet are necessary to fully define
a circuit for testing or procurement purposes. Included is a discussion of the Unit Load method of normalizing
the input and output characteristics of a circuit, and how to translate the numbers given in the Input
Loading/Fan-Out table of a data sheet into the actual values of IIH, ilL, IOH and IOL currents. The various load
configurations for ac testing, a table of RL and CL values for SSI gates and waveforms that help to define the
various ac parameters are also included.
UNIT LOADS (U.L.)
For convenience in system design the input loading and fan-out characteristics of each circuit are specified in
terms of unit loads. One unit load in the HIGH state is defined as 40J.lA; thus both the input HIGH leakage current
IIH and the output HIGH current sourcing capability IOH are normalized to 40 J.lA. Similarly, one unit load in the
LOW state is defined as 1.6 mA and both the input LOW current IlL and the output LOW current sinking
capability IOL are normalized to 1.6 mAo On the data sheets the input and output load factors are listed in the
Input Loading/Fan-Out table. The table from the 5417404 Hex Inverter is reproduced below.
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54/74 (U.L.)
HIGH/LOW

54174H (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
20/10

1.25/1.25
12.5/12.5

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

The input loading and fan-out factors are arranged in four columns, since this hex inverter is available in
standard TTL, H-TTL, S-TTL and LS-TTL. Under the 54174H heading, for example, the input HIGH/LOW load
factors are 1.25/1.25, with the first number representing IIH and the second representing ilL. For purposes of
testing or procurement these load factors can be easily translated to actual test limits by simply multiplying
them by 40 J.lA and 1.6 mA, respectively. The second set of numbers represents the rated output HIGH/LOW
load currents IOH and IOL, respectively. In the 54174S column the output HIGH/LOW drive factors of 25/12.5
translate to 1.0 mA and 20 mA by multiplying them by 40 J.lA and 1.6 mA, respectively.
For any input or output for which the Military and Commercial grade specifications differ, the Military grade
loading or fan-out factors are shown in parenthesis immediately below the Commercial grade factors. In the
case of the 54174LS04 in the sample table shown, the output LOW fan-out for the Commercial grade (74LS04) is
shown as 5.0 (equivalent to 8.0 mAl, while the rating for the Military grade (54LS04) is 2.5 (or 4.0 mAl. The output
HIGH fan-out rating for the Military grade is the same as for the Commercial grade and thus the rating of 10
loads (or 400 J.lA IOH) is not repeated in parenthesis.
For convenience in system design the input and output loading factors should not be translated into J.lA and mAo
It is only necessary to add up the input loading factors of all inputs connected to a particular logic function and
compare the total unit loadi ng with the fan-out capability of the source of that particular function. For example,
a function that connects to one input of each of the hex inverter types in the table above must drive the total
loading calculated below.
Input HIGH Loading = 1.0 + 1.25 + 1.25 + 0.5 = 4.0 Unit Loads
Input LOW Loading = 1.0 + 1.25 + 1.25 + 0.25 = 3.75 Unit Loads
3-3

•

LOADING. SPECIFICATIONS AND WAVEFORMS
UNIT LOADS (U.L.) (Cont'd)
To extend the example, this amount of loading can be driven by anyone of the hex inverters in the Commercial
grade, since all outputs have fan-out capabilities greater than 4.0/3.75. In the Military grade, however, the
54LS04 has a rated output LOW drive factor of only 2.5 and thus could not be guaranteed to drive 3.75 unit loads.
Thus a different type of driver would be selected for operation over the Military temperature range.
In the case of an open-collector output, which is not capable of supplying IOH current or of establishing a VOH
level, the output HIGH load factor does not apply and thus the abbreviation OC is substituted. It is assumed that
the system designer will specify a pull-up resistor value that will establish the desired VOH while supplying the
cumulative hH of the driven loads plus the.IOH leakage current of the output (or outputs, in the case of wiredcollector logic) as specified in either the pertinent Family DC Characteristics table or on the data sheet.

ABSOLUTE MAXIMUM RATINGS1 (beyond which useful life may be impaired)
Storage Temperature
Ambient Temperature Under Bias
Junction Temperature Under Bias
Vee Pin Potential to Ground Pin
Input Voltage2:
Emitter Inputs
LS-TTL3 Diode and pnp Inputs
Input Current2,4
Voltage Applied to Outputs in HIGH State:
Open Collector
Standard TTL, H-TTL, S-TTL, LP-TTL
Standard LS-TTLS (with recommended operating Vee)
3-State LS-TTL (with Vee = 0 V)
Current Applied to Outputs in LOW State (Max)

-65°C to +150°C
-55° C to +125° C
-55° C to +175° C
-O.S V to +7.0 V
-0.5 V to +5.5 V
-0.5 V to +15 V
-30 rnA to +5.0 rnA
-0.5 V to +7.0 V
-0.5 V to Vee Value
-0.5 V to +10 V
-0.5 V to +5.5 V
twice the rated IOL

RECOMMENDED OPERATING CONDITIONS1

Free Air Ambient Temperature
Military (XM)
Commercial (XC)
Supply Voltage
Military (XM)
Commercial (XC)

Min

Max

-55°C
O°C

+125°C
+70°C

+4.5 V
+4.75 V

+5.5 V
+5.25 V

NOTES:
1. Unless otherwise res.tricted or extended by detail specifications.
2. Either input voltage IImit.or input current limit is sUllicientto protect Inputs.
3. Refer to input breakdown test In 54LS17:4LS family DC Characteristics or individual data sheets for em iller type LS-TTL inputs.
4. Except 9315/7441 limited to -10 mA to +1.0 mAo Also, steady-state clamp diode currents greater than -2.0 mA in LS-TTL inputs can cause logic
malfunctions; see discussion in Section 2.
5. Except 'LSOO, 'LS02, 'LS04, 'LS10, 'LS11, 'LS20, 'LS32, 'LS74, 'LS86, 'LS109, 'LS112, 'LS113 and 'LS114 limited to -0.5 V to +Vcc Value.

3-4

LOADING, SPECIFICATIONS AND WAVEFORMS
DC CHARACTERISTICS TABLES
Most of the circuits described in this data book were designed within the general framework of one of the
distinctive families of TTL circuits, i.e., TTL, H-TTL, S-TTL, LP-TTL or LS-TTL. Many dc specifications are
common to almost all circuits of a particular family, e.g., VIH, Vll, VOH,Veo, etc. and toavoid needless repetition
these common parameters do not appear on the individual data sheets. On the following pages are tables of dc
characteristics containing the parameters, limits and conditions common tothevarious families of TTL circuits.
These are intended to augment the distinctive parameters, such as accharacteristics, input loading, fan-out and
power supply current listed on the individual data sheets. In some cases a particular circuit will depart from its
family characteristics in one or more parameters and in these cases the limits or conditions shown on the
individual data sheets take precedence over the values listed in the family characteristics table.

54XX, 74XX, 93XX & 96XX FAMILY DC CHARACTERISTICS1
SYMBOL2

LlMITS3

PARAMETER

Min
VIH

Input HIGH Voltage

Vil

Input LOW Voltage

Veo

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

Input HIGH Current
IIH

UNITS

Typ4

V

Recognized as a HIGH Signal
Over Recommended
Vee and T A Range

0.8

V

Recognized as a LOW Signal
Over Recommended
Vee and TA Range

-1.5

V

Min

= -12 mA
10H = 40 /-LA Multiplied

V

Min

Output HIGH U.L.
Shown on Data Sheet

0.4

V

Min

10l = 1.6 mA Multiplied by
Output LOW U.L.
Shown on Data Sheet

40
80
n(40)

/-LA

Max

hH = 40 /-LA Multiplied by
Input HIGH U.L. Shown on
Data Sheet; VIN = 2.4 V

1.0

mA

Max

VIN

-1.6
-3.2
nH.6)

mA

Max

III = 1.6 mA Multiplied by
Input LOW U.L. Shown on
Data Sheet; VIN = 0.4 V

250

/-LA

Min

VOH

2.0

2.4

3.4

0.2
1.0 U.L.
2.0 U.L.
n U.L.

Input HIGH Current,
Breakdown Test, All Inputs
1.0 U.L.
2.0 U.L.
n U.L.

CONDITIONS3

Vee 5

Max

liN

= 5.5

V

III

Input LOW Current

10H

Output HIGH Current,
Open-Collector

10ZH

3-State Output OFF
Current HIGH

40

/-LA

Max

VOUT

= 2.4

10Zl

3-State Output OFF
Current LOW

-40

/-LA

Max

VOUT

= 0.4 V

IOS6

Output Short
Circuit
Current

-57
-57
-70
-70
-70

mA

Max

VOUT

=0 V

Std

7 54XX
. 74XX'
54XX
Buffers 74XX

93XX

-20
-18
-20
-18
-20

Noles on following pages.

3-5

by

= 5.5

V
V

•

LOADIING, SPECIFICATIONS AND WAVEFORMS
54H, 74H, & 93H FAMILY DC CHARACTERISTICSI
SYMBOL2

LIMITS3

PARAMETER
Min

VIH

Typ4

UNITS

2.0

Input HIGH Voltage

Vee 5

CONDITIONS3

Max
Recognized as a HIGH Signal
Over Recommended

V

Vee and T A Range

VIL

0.8

Input LOW Voltage

Recognized as a LOW Signal
Over Recommended

V

Vee and T A Range
VeD

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

-1.5

V

Min

hN=-12mA

V

Min

0.4

V

Min

50
100
n(40)

p.A

Max

hH = 40 p.A Multiplied by
Input HIGH U.L. Shown on
Data Sheet; VIN = 2.4 V

1.0

mA

Max

VIN = 5.5 V

-2.0
-4.0
n(-1.6)

mA

Max

hL = 1.6 mA Multiplied by
Input LOW U.L. Shown on
Data Sheet; VIN = 0.4 V

250

p.A

Min

VOH = 5.5 V

-100

mA

Max

VOUT = 0 V

10H = 40 p.A Multiplied by
2.4

3.4

Output HIGH U.L.
Shown on Data Sheet
10L = 1.6 mA Multiplied by

1.25
2.5
n

0.2

U.L.
U.L.
U.L.

Input HIGH Current,
Breakdown Test, All Inputs

hL

10H
loS6

Input LOW Current

1.25
2.5
n

U.L.
U.L.
U.L.

Output HIGH Current,
Open-Collector
Output Short Circuit Current

-40

Output LOW U.L.
Shown on Data Sheet

1. Unless otherwise noted. conditions and limits apply throughout the temperature range for which the particular device type is rated. The ground

pin is the reference level for all applied and resultant voltages.
For definitions of symbols and terminology please see Section 2.
Unless otherwise stated on individual.data sheets.
Typical characteristics refer to TA = +25 0 e and Vee = +5.0 V.
Min and Max refer to the values listed in the table of recommended operating conditions.
For testing los. the use of high speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and
more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal
and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests. los tests should be performed last.
7. Standard refers to the totem-pole pull-up circuitry commonly used for the particular family. as distinguished from buffers. line drivers or 3-state
outputs.

2.
3.
4.
5.
S.

3-6

LOADING, SPECIFICATIONS AND WAVEFORMS
54S, 74S & 93S FAMILY DC CHARACTERISTICS1
SYMBOL2

LIMITS3

PARAMETER
Min

UNITS

Typ4

V

Recognized as a HIGH Signal
Over Recommended
Vee and TA Range

0.8

V

Recognized as a LOW Signal
Over Recommended
Vee and T A Range

-1.2

V

Min

hN

V

Min

by Output HIGH U.L.
Shown on Data Sheet

V

Min

IOl = 1.6 mA Multiplied
by Output LOW U.L.
Shown on Data Sheet

50
100
n(40)

p,A

Max

hH = 40 p,A Multiplied by
Input HIGH U.L. Shown on
Data Sheet; VIN = 2.7 V

1.0

mA

Max

VIN

-2.0
-4.0
n(-1.6)

mA

Max

hl = -1.6 mA Multiplied by
Input LOW U.L. Shown on
Data Sheet; VIN = 0.5 V

250

p,A

Min

VOH

2.0

VIH

Input HIGH Voltage

Vil

Input LOW Voltage

VeD

Input Clamp Diode Voltage

VOH

Output
HIGH Voltage

VOL

Output LOW Voltage

hH

1.25 U.L.
Input HIGH Current 2.5 U.L.
nU.L.

Std.7 Mil.
Std.7 Com.
3-State

2.5
2.7
2.4

3.4
3.4
3.2
0.35

0.5

Input HIGH Current,
Breakdown Test, All Inputs
1.25 U.L.
2.5 U.L.
n U.L.

CONDITIONS3

Vee 5

Max

= -18 mA
IOH = 40 p,A Multiplied

= 5.5 V

hl

Input LOW Current

IOH

Output HIGH Current,
Open-Collector

10ZH

3-State Output OFF
Current HIGH

50

p,A

Max

VOUT

= 2.4 V

IOZl

3-State Output OFF
Current LOW

-50

p,A

Max

VOUT

= 0.5 V

IOS6

Output Short
Circuit Current

mA

Max

VOUT

=0 V

1.
2.

3.
4.
5.

6.
7.

Standard7/
3-State
Buffers/
Line Dvrs

-40

-100

-50

-225

= 5.5 V

Unless otherwise noted, conditions and limits apply throughout the temperature range for which the particular device type is rated. The ground
pin is the reference level for all applied and resultant voltages.
For definitions of symbols and terminology please see Section 2.
Unless otherwise stated on individual data sheets.
Typical characteristics refer to TA = +25°C and Vee = +5.0 V.
Min and Max refer to the values listed in the table of recommended operating conditions.
For testing los, the use of high speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and
more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal
and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, los tests should be performed last.
Standard refers to the totem-pole pull-up circuitry commonly used for the particular family, as distinguished from buffers, line drivers or 3-state
outputs.

3-7

LOADING, SPECIFICATIONS AND WAVEFORMS
54LS, 74LS 8. 96LS FAMILY DC CHARACTERISTICS1
SYMBOL2

LlMITS3

PARAMETER
Min
Input HIGH Voltage

Vil

Input LOW Voltage

Veo

Input Clamp Diode Voltage

VOH

Std.? Mil.
Std.7 Com.
Output HIGH
3-State/Buffers
Voltage
Line Dvrs

hH

Output LOW
Voltage

UNITS

Mil.
Com.

2.5
2.7
2.4
2.0

Vee s

CONDITIONS3

Max
V

Recognized as a HIGH Signal
Over Recommended
Vee and T A Range

0.7
0.8

V

Recognized as a LOW Signal
Over Recommended
Vee and T A Range

-1.5

V

Min

hN = -18 mA

V

Min

10H = 40 J1.A Multiplied
by Output HIGH U.L.
Shown on Data Sheet

2.0

VIH

VOL

Typ4

3.4
3.4
3.3
2.9

10l = 1.6 mA Multiplied
by Output LOW U.L.
Shown on Data Sheet
10l - 1.6 mA Multiplied
by Output LOW U.L. Shown
in Parenthesis on Data Sheet

Com.

0.35

0.5

V

Min

Mil. & Com.

0.25

0.4

V

Min

20
40
n(40)

J1.A

Max

hH = 40 J1.A Multiplied by
Input HIGH U.L. Shown on
Data Sheet; VIN = 2.7 V

100

J1.A

Max

VIN=10V8

-0.4
-0.8
n(-1.6)

mA

Max

hl = -1.6 mA Multiplied by
Input LOW U.L. Shown on
Data Sheet; VIN = 0.4 V

100

J1.A

Min

VOH = 5.5V

0.5 U.L.
Input HIGH Current 1.0 UL
n U.L.
Input HIGH Current,
Breakdown Test, All Inputs
0.25 U.L.
0.5 U.L.
nUL

ill

Input LOW Current

10H

Output HIGH Current,
Open-Collector

10ZH

3-State Output OFF
Current HIGH

20

J1.A

Max

VOUT = 2.4 V

10Zl

3-State Output OFF
Current LOW

-20

J1.A

Max

VOUT =0.4 V

IOS6

Output Short
Circuit Current

mA

Max

VOUT = 0 V

Standard?
3-State/
Buffers
Line Dvrs

-20

-100

-30

-130

-40

-225

1. Unless otherwise noted, conditions and limits apply throughout the temperature range for which the particular device type is rated. The ground
pin is the reference level for all applied and resultant voltages.
For definitions of symbols and terminology please see Section 2.
Unless otherwise stated on individual data sheets.
Typical characteristics refer to TA = +2S'C and Vee = +S.O V.
Min and Max refer to the values listed in the table of recommended operating conditions.
For testing los, the use of high speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and
more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal
and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, los tests should be performed last.
7. Standard refers to the totem-pole pull-up circuitry commonly used for the particular family, as distinguished from buffers, line drivers or 3-state
outputs.
B. Except 5.5 V for 'LS03, 'LS05, 'LS22, 'LS74, 'LS109, 'LS112, 'LS113, 'LS114, 'LS136 (which have emitter inputsl and as shown on other data sheets.

2.
3.
4.
5.
6.

3-8

LOADING, SPECIFICATIONS AND WAVEFORMS
9XXX FAMILY DC CHARACTERISTICS1
SYMBOL2

LIMITS3

PARAMETER
Min

Typ4

UNITS

Vee 5

CONDITIONS3

Max

VIH

Input HIGH Voltage
(See Data Sheets)

V

Recognized as a HIGH Signal
Over Recommended
Vee and T A Range

VIL

Input LOW Voltage
(See Data Sheets)

V

Recognized as a LOW Signal
Over Recommended
Vee and T A Range

Veo

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage
(See Data Sheets)

hH

Input HIGH Current

IlL

Input LOW Current
(See Data Sheets)

10H

Output HIGH Current,
Open-Collector

IOS6

Output Short
Circuit Current

-1.5
2.4

Min

hN=-12mA

V

Min

10H = 40 JJ.A Multiplied
by Output HIGH U.L.
Shown on Data Sheet

40
80
n(40l

JJ.A

Max

IIH = 40 JJ.A Multiplied by
Input HIGH U.L. Shown on
Data Sheet; VIN = 4.5 V

250

JJ.A

Min

VOH = 5.5 V

-100
-120
-150
-100
-110

mA

Max

VOUT = 0 V

3.4

1.0 U.L.
2.0 U.L.
n U.L.

Std.7 Mil.
Std.7 Com.
9009
9024 Mil.
9024 Com.

V

-30
-30
-40
-40
-35

1. Unless otherwise noted, conditions and limits apply throughout the temperature range for which the particular device type is rated. The ground

pin is the reference level for all applied and resultant voltages.
2. For definitions of symbols and terminology please see Section 2.
3. Unless otherwise stated on individual data sheets.
4. Typical characteristics refer to TA = +25°e and Vee = +5.0 V.
5. Min and Max refer to the values listed in the table of recommended operating conditions.
6. For testing los, the useof high speed test apparatus and/or sample-and-holdtechniques are preferable in orderto minimize internal heating and
more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal
and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, los tests should be performed last.

7.

Standard refers to the totem-pole pull-up circuitry commonly used forthe particular family, as distinguished from buffers, line drivers or 3-state
outputs.

3-9

LOADING, SPECIFICATIONS AND WAVEFORMS
93L FAMILY DC CHARACTERISTICS1
SYMBOL2

LIMITS3

PARAMETER
Min
Input HIGH Voltage

VIL

Input LOW Voltage

VeD

Input Clamp Diode Voltage

Recognized as a HIGH Signal
Over Recommended
Vee and T A Range

0.7
O.B

V

Recognized as a LOW Signal
Over Recommended
Vee and TA Range

-1.5

V

Min

V

Min

0.3
0.4

V
V

Min
Min

0.5 U.L.
1.0 U.L.
n U.L.

20
40
n(40)

J.LA

Max

Input HIGH U.L. Shown on
Data Sheet; VIN = 2.4 V

1.0

rnA

Max

VIN

-0.4
-O.B
n(-1.6)

rnA

Max

hL = -1.6 rnA Multiplied by
Input LOW U.L. Shown on
Data Sheet; VIN = 0.3 V

-25

rnA

Max

VOUT

VOL

Input HIGH Current

3.6

Input HIGH Current,
Breakdown Test, All Inputs
0.25 U.L.
0.5 U.L.
n U.L.

ilL

Input LOW Current

IOS6

Output Short Circuit Current

1.

2.
3.

4.
5.
6.

= -10 rnA
10H = -400 J.LA
10L = 4.B rnA
10L = B.O rnA
hH = 40 J.LA Multiplied by
hN

Mil. & Com.
Com.

Output HIGH Voltage
Output LOW
Voltage

2.4

CONDITIONS3

Vee 5

V

Mil.
Com.

VOH

hH

UNITS
Max

2.0

VIH

I
I

Typ4

-2.5

= 5.5 V

=0 V

Unless otherwise noted. conditions and limits apply throughout the temperature range for which the particular device type is rated. The ground
pin is the reference level for all applied and resultant voltages.
For definitions of symbols and terminology please see Section 2.
Unless otherwise stated on individual data sheets.
Typical characteristics refer to TA = +25'e and Vce = +5.0 V.
Min and Max refer to the values listed in the table of recommended operating conditions.
For testing los. the use of high speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and
more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the· chip temperature well above normal

and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests. los tests should

3-10

be

performed last.

LOADING, SPECIFICATIONS AND WAVEFORMS
AC LOADING AND WAVEFORMS
Figure 3-1 shows the ac test load configuration used for circuits of the 54174, 54174H and 54/74S families having
totem-pole outputs. The diodes and resistor are not used for testing circuits of the 54174lS, 9XXX, 93XX, 93H,
93S, 93l, 96XX or 96lS families. Figure 3-2 shows the test load configuration for open-collector outputs. For S SI
gates, RL and CL values are listed in the table below. For flip-flops and MSI, RL and CL values are listed in the
column headings of the ac tables on the data sheets. Figure 3-3 shows the test circuit for measuring Enable and
Disable times of 3-state outputs; RL and CL values are given in the column headings of the ac table in the data
sheet, except in certain tests they are superceded by RL or CL values listed in the Test Conditions column of the
same table.
A pulse generator signal swing of 0 V to +3.0 V, terminated at the test socket, is recommended for ac testing. A
1.0 MHz square wave is recommended for most propagation delay tests, with rise and fall times of 2.5 ns for STTL, 10 ns for lP-TTl and 6.0 ns for circuits of other families. The generatorPRR must necessarily be increased
for testing f max and decreased for testing one-shot pulse widths. Two pulse generators are usually required for
testing such parameters as set-up time, hold time, recovery time, etc.

AC LOADS FOR SSI GATES
SSI DEVICES

54174

AC TEST

54H174H

54LS/74LS

CL

RL

CL

RL

CL

RL

CL

RL

4 kn
400 n

25 pF
25 pF

280 n
280 n

15 pF
15 pF

280 n
280 n

15 pF
15 pF

2 kn
2 kn

15 pF

280 n

15 pF

2 kO

15 pF

2 kn

50 pF

6670

50 pF

667 n

50 pF
5 pF

667 n
667 n

15 pF

-

'01, '03, '05
'12, '22

tPLH
tPHL

15 pF
15 pF

'09, '15, '65

tPLH/tPHL

15 pF

400 n

'06, '07, '16, '17

tPLH/tPHL

15 pF

110 n

'26

tPLH/tPHL

15 pF

1 kn

'28, '33, '37, '38

tPLH/tpHL

45 pF

133 n

'40, '140

tPLH/tPHL

15 pF

133 n

'125, '126, '365
'366, '367, '368

tPLH, HL, ZL, ZH
tPHZ, LZ

50 pF
5 pF

4000
400 n

'134

tPLH/tPHL
tpzH/tpZL
tpHz/tPLZ

All Standard
Gates with Totem tPLH/tpHL
Pole Outputs

54S/74S

15 pF

25 pF

400 n

25 pF

3-11

93 n

280 n

50 pF

930

15 pF
50 pF
50 pF

280 n
280 n
280 n

15 pF

280 n

•

LOADING, SPECIFICATIONS AND WAVEFORMS

I - Ve-;- - - - - "7l

I

I

I
I

I

I

I
I

I
I

-=- L ____ __--===---.J
Fig. 3-1

'Not Used for LS-TTL
"Includes Jig and Probe Capacitance

Test Load for Totem-Pole Outputs in Bi-State Mode
Vee

Rl
~
o
I

Fig. 3-2

Cl'

'Includes Jig and Probe Capacitance

Test Load for Open-Collector Outputs

PARAMETER

SW1

SW2

tPZH

Open
Closed
Closed
Closed

Closed
Open
Closed
Closed

TOD.U.T ...........-K

tPZL
tPLZ
1 kn
(5 kn for LS)

tPHZ

'Includes Jig and Probe Capacitance

Fig. 3-3

Vm

Fig. 3-4.

~

Enable and Disable Test Loads for 3-State Outputs

1.5 V (1.3 V for LS)

Vm

Fig. 3-5

Waveform for Inverting Functions

3-12

~

1.5 V (1.3 V for LS)

Waveform for Non-Inverting Functions

LOADING, SPECIFICATIONS AND WAVEFORMS

Fig. 3-6

Set-up and Hold Times, Rising-Edge Clock

Fig. 3-7

Set-up and Hold Times, Falling-Edge Clock

•

1

14...---------lmax--------4~~1

I. .I-----IW(L)-----I~~I

',.C'

jl~----------~~I
\-IW(H)

-

jl~Y-m-=-1-.5-Y-(1-.3-Y-lo-r-L-S)

'-----~

~IPHL_I

_

IPLH

1

F

- Y O U T- - - ,

-

r

I

VOUT

Fig. 3-8

IPHL
-

Propagation Delays from Rising-Edge Clock or Enable

3-13

LOADING, SPECIFICATIONS AND WAVEFORMS

I! or cy;

VOUT

'lOUT

Fig. 3-9

Propagation Delays from Failing-Edge Clock or Enable

_tw_
SET

CLEAR

----IttPLH

a_ _

-----:....----.

1

1-°"

\ \ . ._ _ _ _ _ _ _ _....

Flg.3-10

tPLH

Vm=1.5.V(1.3VlorLS)

Propagation Delays from Set and Clear (or Reset)

3-14

LOADING, SPECIFICATIONS AND WAVEFORMS
VE
VE
Your

Fig. 3-11

3-State Output LOW Enable and Disable Times

VE
VE

Fig. 3-12

E or Pi:

3~State

Vm

Output HIGH Enable and Disable Times

= 1.5 V (1.3

V for LS)

Flg.3-13

Setup and Hold Times to Active LOW Enable or Parallel Load

Fig.3-14

Setup and Hold Times to Active HIGH Enable or Parallel Load

3-15

LOADING, SPECIFICATIONS AND WAVEFORMS

IVretCH)

\.

~IVretCL)

1-

-IIPHL

'0",

\

_______

PARAMETER
Vref(H)
Vref(L)
Vm

Fig. 3-15

MS,MR,PL,Ci

MS,MR,PL,CL

CPorE

1-

F

-IIPLH

FAMILY
54/74

54LS/74LS

54S/74S

1.7 V
0.9 V
1.5 V

1.6 V
0.8 V
1.3 V

.1.8 V
1.2 V
1.5 V

Waveforms for Schmitt Trigger Devices

I-

Iw

~I

loom

~;:.~"

*
- r-

Vm

IPHL

VOUT

Vm

IPLH

\lOUT

,_

F

Flg.3-16 Asynchronous Set, Reset, Parallel Load or Clear, Active Rising Edge Clock or Active LOW Enable

3-16

LOADING, SPECIFICATIONS AND WAVEFORMS

---"'t

---9rV-m-=-1'5-V-

rll

MR,Pi,C[

MR,MS,PL,CL

~ ::~"

---....I

CP or E

VOUT
tPLH

Ir

VOUT __________-JI'~
Flg.3-17

-------------

Asynchronous Set, Reset, Parallel Load or Clear, Active Failing Edge Clock or Active HIGH Enable

~H' II'"(H'~

n,. . ,
~

C_p
_ _ _ _...

Flg.3-18

~HI

(U'

'0' '"

Setup and Hold Times, Active HIGH Clock

~ '

6A

[I

IT

31

=t:J c::= m
I!I

I!lGND

Vee[I

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

:!iJVee

[I

ORDERING CODE: See Section 9

PKGS

~

54/74 (U.L.)
HIGH/LOW

54/74H (U.L.)
HIGH/LOW

54/74S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
20/10

1.25/1.25
12.5/12.5

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

IT
IT

~c:; :!l

[2

f---t>

:§)

~

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

PARAMETER

54/74

54/74H

54/74S

54/74LS

UNITS

CONDITIONS

Min Max Min Max Min Max Min Max
ICCH

Power Supply

12

26

24

2.4

ICCl

Current

33

58

54

6.6

tPlH
tPHL

Propagation Delay

22
15

10
10

2.0
2.0

4.5
5.0

10
10

tPlH
tPHl

Propagation Delay
(54/74S04A only)

1.0
1.0

3.5
4.0

·DC

limits apply over operating temperature range;

AC

limits apply at TA = +25 0

4-7

C and

Vee = +5.0 V.

mA

VIN = Gnd

Vcc = Max

VIN = Open

ns

Fig. 3-1, 3-4

ns

Fig. 3-1, 3-4

•

05
CONNECTION DIAGRAMS
PINOUT A

54/7405
54H/74H05
54S/74S05
54S/74S05A
54LS/74LS05

0::
II
IT
II

HEX INVERTER

[I
[I

(With Open-Collector Output)

GNOIT

ORDERING CODE: See Section 9
PIN
PKGS

COMMERCIAL GRADE

MILITARY GRADE

VCC = +5.0 V ±5%.
T A = 0° C to + 70° C

VCC = +5.0 V. ±10%.
TA = -55°C to +125°C

OUT

A

7405PC.74H05PC
74S05PC.74S05APC
74LS05PC

Ceramic
DIP (D)

A

7405DC. 74H05DC
74S05DC.74S05ADC
74LS05DC

5405DM. 54H05DM
54S05DM. 54S05ADM
54LS05DM

A

74S05FC. 74S05AFC
74LS05FC

54S05FM. 54S05AFM
54LS05FM

B

7405FC.74H05FC

5405FM. 54H05FM

Inputs
Outputs

DC ~~
DC rm~
DC ~~

PKG
TYPE

9A

6A

"......

IT
II
IT

31

=c;:J

rm

[I ....
[I

54/74 (U.L.)
HIGH/LOW

54174H (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
OC""/10

1.25/1.25
OC""/12.5

1.25/1.25
OC""/12.5

0.5/0.25
OC""/5.0
(2.5)

IT

I:EJ

c:= ~~

VeelI

INPUT LOADING/FAN-OUT: See Section 3 for U.l. definitions
PINS

I:EJ Vee

PINOUT B

Plastic
DIP (P)

Flatpak
(F)

-

GNO

"IC4= ~~

H

;!J

DC AND AC CHARACTERISTICS: See Section 3"
SYMBOL

PARAMETER

54/74

54174H

54/74S

54/74LS

CONDITIONS

UNITS

Min Max Min Max Min Max Min Max
ICCH

Power Supply

12

26

19.8

2.4

ICCl

Current

33

58

54

6.6

tPlH
tPHl

Propagation Delay

55
15

18
15

2.0
2.0

7.5
7.0

22
18

tPlH
tPHl

Propagation Delay
(54S174S05A only)

2.0
1.5

5.5
5.0

·DC limits apply over operating temperature range; AC limits apply al TA = +25°C and Vee = +5.0 V.
··OC- Collector

4-8

mA

V,N
V,N

= Gnd VCC = Max
= Open

ns

Fig. 3-2. 3-4

ns

Fig. 3-2. 3-4

06
CONNECTION DIAGRAM
PINOUT A

54/7406
HEX INVERTER BUFFER/DRIVER
(With Open-Collector High-Voltage Output)
(1 ~

ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP(P)

OUT

~

COMMERCIAL GRADE
VCC = +5.0 V ±5%,
TA = O°C to +70°C

MILITARY GRADE
VCC = +5.0 V ±10%,
TA = -55°C to +125°C

II

PKG

11
11

TYPE

A

7406PC

Ceramic
DIPm)

A

7406DC

5406DM

6A

Flatpak
(F)

A

7406FC

5406FM

31

[!

9A

[!
GNOIT

~vee

~

LYe Pll~

Dc ~~
DC ~~

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54/74 (U.L.)
HIGH/LOW
1.0/1.0
OC"/10

DC AND AC CHARATERISTICS: See Section 3'
SYMBOL

54/74

PARAMETER
Min

VOL

IOH
ICCH

Output LOW Voltage

XC

0.7

XM

0.7

XC, XM

0.4

Output HIGH Current

0.25
48

Power Supply Current

V

15
23

Propagation Delay

'DC limits apply over operating temperature range; AC limits apply at TA
"OC-Open Collector

mA
mA

ns

= +25'C and Vee = +5.0

4-9

IOL

= 40

IOL

= 30 mA

mA

= Min
VIN = VIH

Vcc

= 16 mA
VOH = 30 V, Vcc = Min
IOl

51

ICCl
tPlH
tpHl

CONDITIONS

UNITS
Max

= Vil
VIN = Gnd
VIN = Open

VIN

Fig. 3-2, 3-4
V.

Vcc

= Max

•

07
CONNECTION DIAGRAM
PINOUT A

54/7407
HEX BUFFER/DRIVER
(With Open-Collector High-Voltage Output)

IT -

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
VCC = +5.0 V ±5%,
TA = O°C to +70°C

Plastic
DIP(P)

A

7407PC

Ceramic
DIP (0)

A

7407DC

Flatpak
(F)

A

7407FC

MILITARY GRADE
VCC = +5.0 V ±10%,
TA = -55°C to +125°C

II

PKG

r-

11..

TYPE

~

Y

,L

:El Vee
E.l
ill

[I ~C TIl

:m
=:J
II
C 1]]]

9A

II

5407DM

6A

GNO[I

5407FM

31

INPUT LOADING/FAN-OUT: See Section 3· for U.L. definitions
PINS
Inputs
Outputs

54/74 (U.L.)
HIGH/LOW
1.0/1.0
OC**/10

DC AND AC CHARACTERISTICS: See Section 3*
SYMBOL

54174

PARAMETER
Min
XC

VOL

IOH
ICCH

Output LOW Voltage

0.7

XM

0.7

XC, XM

0.4

Output HIGH Current

0.25
41

Power Supply Current

10
30

Propagation Delay

·DC limits apply over operating temperature range; AC limits apply at
··OC-Open Collector

TA

mA
mA

ns

= +25'C and Vee = +5.0 V.

4-10

= 40 mA
VCC = Min
IOL = 30 mA
VIN = VIL
IOL = 16 mA
VOH = 30 V, VCC = Min,
VIN = VIH
VIN = Open
Vcc = Max
VIN = Gnd
IOL

V

30

ICCL
tPLH
tPHL

CONDITIONS

UNITS
Max

Fig. 3-2, 3-5

08
CONNECTION DIAGRAMS
PINOUT A

54/7408
54H/74H08
54S/74S08
54LS/74LS08
QUAD 2-INPUT AND GATE

•

ORDERING CODE: See Section 9
PIN
PKGS

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

OUT

Plastic
DIP(P)

A

740BPC, 74HOBPC
74S0BPC, 74LSOBPC

Ceramic
DIP (D)

A

740BDC, 74HOBDC
74S0BDC, 74LSOBDC

540BDM, 54HOBDM
54S0BDM,54LSOBDM

A

740BFC, 74S0BFC
74LSOBFC

540BFM, 54S0BFM
54LSOBFM

B

74HOBFC

54HOBFM

Flatpak
(F)

PKG
TYPE
PINOUT B

9A
6A

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54/74 (U.L.)
HIGH/LOW

54/74H (U.L.)
HIGH/LOW

54/74S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
20/10

1.25/1.25
12.5/12.5

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3*
SYMBOL

PARAMETER

54174

54174H

54/74LS

54/74S

CONDITIONS

UNITS

Min Max Min Max Min Max Min Max
ICCH

Power Supply

21

40

32

4.B

ICCl

Current

33

64

57

B.B

tPlH
tPHL

Propagation Delay

27
19

12
12

7.0
7.5

13
11

'DC

limits apply over operating temperature range;

AC

limits apply at TA =

2.5
2.5

+25'C and

4-11

Vee =

+5.0 V.

mA

VIN = Open
VIN

ns

Vcc

= Gnd

Fig. 3-1, 3-5

= Max

09
CONNECTION DIAGRAM
PINOUT A

54/7409
54S/74S09
54LS/74LS09
QUAD 2-INPUT AND GATE
(With Open-Collector Output)

0::
11
IT
11
IT

ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP(P)

OUT
A

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5,0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

7409PC, 74S09PC
74LS09PC

9A

~
GNOI::z:

Ceramic
DIP (0)

A

7409DC, 74S09DC
74LS09DC

5409DM, 54S09DM
54LS09DM

6A

Flatpak
(F)

A

7409FC, 74S09FC
74LS09FC

5409FM,54S09FM
54LS09FM

31

~

~~

~~

~vcc

t131

~
ITI
10]
~

~

II

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54/74 (U.L.)
HIGH/LOW

54/74S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
OC**/10

1.25/1.25
OC**/12.5

0.5/0.25
OC**/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3*
SYMBOL

PARAMETER

54/74

54/74S

54/74LS

CONDITIONS

UNITS

Min Max Min Max Min Max
ICCH

Power Supply Current

21

ICCl

33

tPlH
tPHl

32
24

Propagation Delay

2.0
2.0

32

4.8

57

8.8

10
10

20
15

'OC limits apply over operating temperature range; AC limits apply at TA ; +25 0 C and Vee; +5.0 V.
"OC-Open Collector

4-12

mA

VIN
VIN

ns

= Open Vcc = Max
= Gnd

Fig. 3-2, 3-5

10
CONNECTION DIAGRAMS
PINOUT A

54/7410
54H/74H10
54S/74S10
54LS/74LS10

IT
II
IT

TRIPLE 3-INPUT NAND GATE

[I

II
~

GNOII

~

~t=

~~

~vec

~
~
~
~

~
~

ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP(P)
Ceramic
DIP (0)
Flatpak
(Fl

OUT

COMMERCIAL GRADE

MILITARY GRADE

VCC = +5.0 V ±5%,
TA = 0° C to +70° C

VCC = +5.0 V ±10%,
TA = -55°C to +125°C

A

7410PC, 74H10PC
74S10PC, 74LS10PC

A

7410DC, 74H10DC
74S10DC, 74LS10DC

5410DM,54H10DM
54S10DM, 54LS10DM

A

74S10FC, 74LS10FC

54S10FM,54LS10FM

B

7410FC, 74H10FC

5410FM,54H10FM

PINOUT B

PKG
TYPE
9A

IT
II
IT

6A
31

Vee [I

II
~

II

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54/74 (U.L.)
HIGH/LOW

54/74H (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
20/10

1.25/1.25
12.5/12.5

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

~
~

~

~

TIl
:ill
TIlGND
~

' - - :!]

]]

DC AND AC CHARATERISTICS: See Section 3'
SYMBOL

PARAMETER

54174

54174H

54174S

54174LS

CONDITIONS

UNITS

Min Max Min Max Min Max Min Max
ICCH

Power Supply

ICCl

Current

tPlH
"tPHl

Propagation Delay

'DC limits apply over operating temperature range;

6.0

12.6

16.5

30

22
15

10
10

2.0
2.0

12

1.2

27

3.3

4.5
5.0

15
15

AC limits apply at TA = +25°C and Vee = +5.0

4-13

V.

mA

VIN
VIN

ns

= Gnd Vcc = Max
= Open

Fig. 3-1, 3-4

•

11
CONNECTION DIAGRAMS
PINOUT A

54/7411
54H/74H11
548/74811
54L8/74LS11

IT
11
11

TRIPLE 3-INPUT AND GATE

[I

IT
[!
GNOIT

~vee

~

~~
~

.------

~~

~
~
~
~

ORDERING CODE: See Section 9
PIN
PKGS

COMMERCIAL GRADE

MILITARY GRADE

VCC = +5.0 V ±5%.
TA = O°C to +70°C

VCC = +5.0 V ±10%.
TA = -55°C to +125°C

OUT

Plastic
DIP (P)
Ceramic
DIP (D)
Flatpak
(F)

A

7411PC.74HllPC
74S11 PC. 74LSllPC

A

7411 DC. 74Hl1DC
74S11 DC. 74LS11DC

5411DM.54HllDM
54S11 OM. 54LSll OM

A

74S11FC.74LSllFC

54S11 FM. 54LSll FM

B

7411FC.74HllFC

5411FM.54HllFM

PINOUT B

PKG
TYPE
9A
6A
31

IT
IT
IT
Vee IT
[I

[I

IT

INPUT LOADING/FAN-OUT: See Section 3 for U.L definitions
PINS

54174 (U.L.)
HIGH/LOW

54/74H (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

Inputs
Outputs

1.0/1.0
20/10

1.25/1.25
12.5/12.5

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

~

~
;Q
'--

~
~
~

~GNO

~
~
~

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

PARAMETER

54/74

54/74H

54174S

54174LS

CONDITIONS

UNITS

Min Max Min Max Min Max Min Max
ICCH

Power Supply

15

30

24

3.6

ICCL

Current

24

48

42

6.6

tPLH
tPHL

Propagation Delay

27
19

12
12

7.0
7.5

13
11

'oc limits

apply ovt.r operating temperature range;

AC

limits apply at TA =

2.5
2.5

+25°C and Vee = +5.0

4-14

V.

mA

= Open
VIN = Gnd

ns

Figs. 3-1. 3-5

VIN

Vcc

= Max

12
CONNECTION DIAGRAM
PINOUT A

54/7412
TRIPLE 3-INPUT NAND GATE
(With Open-Collector Output)

IT
IT:
II
II
II

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

~

PKG
TYPE

Plastic
DIP(P)

A

7412PC

Ceramic
DIP 

A2~

:TIl'C

RBi

DESCRIPTION - The '46A, '47 A and 'LS47 accept four lines of BCD (8421)
input data, generate their complements internally and decode the data with
seven AND/OR gates having open-collector outputs to drive indicator segments directly. Each segment output is guaranteed to sink 40 mA (24 mA for
the 'LS47) in the ON (LOW) state and withstand 15 V (30 V for the '46A) in the
OFF (HIGH) state with a maximum leakage current of 250J.lA. Auxiliary inputs
provide blanking, lamp test and cascadable zero-suppression fuctions. Also
see the 'LS247 data sheet.

A3[I

~d

GNO!I

}F

LOGIC SYMBOL
•
•
•
•

OPEN-COLLECTOR OUTPUTS
DRIVE INDICATOR SEGMENTS DIRECTLY
CASCADABLE ZERO-SUPPRESSION CAPABILITY
LAMP TEST INPUT

PKGS

OUT

1

Ao

A1

J 1 111
1
LT

ORDERING CODE: See Section 9
PIN

7

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

7446APC, 7447APC
74LS47PC

Ceramic
DIP)D)

A

7446ADC, 7447ADC
74LS47DC

5446ADM,5447ADM
54LS47DM

7B

Flatpak
(F)

A

7446AFC, 7447AFC
74LS47FC

5446AFM, 5447 AFM
54LS47FM

4L

9B

a

A2

bed

RBI

A3

e

f

BII
9 RBO

XIX!!!!!
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

Ao-A3
RBI
LT
BIIRBO

-

-

a-g

54174 (U.L.)

DESCRIPTION

HIGH/LOW

BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)
Segment Outputs (Active LOW)

1.0/1.0
1.0/1.0
1.0/1.0
-/2.5
5.0/5.0
OC*/25

'OC-Open Collector

4-44

54174LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
-/0.75
1.25/2.0
(1.0)
OC*/15
(7.5)

46. 47
FUNCTIONAL DESCRIPTION - The '46A, '47A and 'LS47 decode the input data in the pattern indicated in the
Truth Table and the segment identification illustration. If the input data is decimal zero, a LOW signal applied to
the RBI blanks the display and causes a multidigit display. For example, by grounding the RBI of the highest
order decoder and connecting its BI/RBO to RBI of the next lowest order decoder, etc., leading zeros will be
suppressed. Similarly, by grounding RBI of the lowest order decoder and connecting its BI/RBO to RBI of the
next highest order decoder, etc., trailing zeros will be suppressed. Leading and traili ng zeros can be suppressed
simultaneously by using external gates, ie: by driving RBI of an intermediate decoder from an OR gate whose
inputs are BI/RBO of the next highest and lowest order decoders. BI/RBO also serves as an unconditional
blanking input. The internal NAND gate that generates the RBO signal has a resistive pull-up, as opposed to a
totem pole, and thus BI/RBO can be forced LOW by enternal means, using wired-collector logic. A LOW signal
thus applied to BI/RBO turns off all segment outputs. This blanking feature can be used to control display
intensity by varying the duty cycle of the blanking signal. A LOW signal applied to L T turns on all segment
outputs, provided that BI/RBO is not forced LOW.

LOGIC DIAGRAM
RIPPLE-BLANKING
INPUT

INPUT
r -________
________

BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT

LAMP-TEST
INPUT

A~

~

Ao

OUTPUT

NUMERICAL DESIGNATIONS -

I-I
I I

I

--I I-I I-I
II II- I
I_I 1- I
11-I
11-1 -I
I -I
I I-I

I

112

RESULTANT DISPLAYS

3

4

5

7

9

4-45

10

11

12

13

14

15

46 • 47

TRUTH TABLE

I

INPUTS
DECIMAL
OR
FUNCTION LT

BIIRBO a

-

b

-c

d

-e T -9

H
H
H
H

L
H
L
L

L
L
L
L

L
L
H
L

L
H
L
L

L
H
L
H

L
H
H
H

H
H
L
L

L
H
L
H
L

H
H
H
H
H

H
L
H
L
L

L
H
H
L
L

L
L
L
L
L

H
L
L
H
L

H
H
L
H
L

L
L
L
H
L

L
L
L
H
L

L
H
H
L
L

H
L
H
L
H

H
H
H
H
H

L
H
H
H
L

L
H
H
L
H

L
H
L
H
H

H
L
L
H
L

H
L
H
H
H

L
H
H
L
L

L
L
L
L
L

H
H
X
L
X

L
H
X
L
X

H
H
L
L
H

H
H
H
H
L

H
H
H
H
L

H
H
H
H
L

L
H
H
H
L

L
H
H
H
L

L
H
H
H
L

L
H
H
H
L

RBI

A3

A2

A1

Ao

H
H
H
H

H
X
X
X

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

8

H
H
H
H
H

X
X
X
X
X

L
L
L
L
H

H
H
H
H
L

L
L
H
H
L

9
10
11
12
13

H
H
H
H
H

X
X
X
X
X

H
H
H
H
H

L
L
L
H
H

14
15

H
H
X
H
L

X
X
X
L
X

H
H
X
L
X

H
H
X
L
X

0
1

2

3
4
5
6
7

BT
RBI
LT

OUTPUTS

NOTE
1
1

2
3
4

NOTES:
(ll lii7RiiO is wire-AND logic serving as blanking input (Si) and/or ripple-blanking outputtRBO). T~lanking outtBl) must be open or held
at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBIl must be open or at a HIGH level if
blanking or a decimal 0 is not desired. X = input may be HIGH or LOW.
(2) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state
of any other input condition.
(3) When ripple-blanking input(RBii and inputs Ao, A" A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs
go to a HIGH level and the ripple-blanking output (RBOi goes to a LOW level (response condition).
(4) When the blanking input/ripple-blanking output
input, all segment outputs go to a LOW level.

Isi7REiO)

is open or held at a HIGH level, and a LOW level is applied to lamp test

4-46

46 • 47
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min
10H

Output HIGH Current
OFF State ata-g

los

Output Short Circuit
Current at BI/RBO

Icc

Power Supply Current

-

Max

'46

250

'47

250
-4.0

~

54174LS
Min

Il A
250
-0.3

85
103

XC

UNITS

CONDITIONS

Max
VOH = 30 V

Vee = Max

VOH = 15 V

-2.0

mA

Vee = Max

13
13

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74
SYMBOL

PARAMETER

54174LS

CL = 15 pF CL = 15 pF
RL = 120 n RL = 665 n
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tpHL

Propagation Delay
An to "8-9

100
100

100
100

ns

Figs. 3-2, 3-20

tpLH
tpHL

Propag~tio!!

RBI to a-f

100
100

100
100

ns

Figs. 3-2, 3-4
LT= HIGH, Ao-A3=LOW

Delay

4-47

48
CONNECTION DIAGRAM
PINOUT A

54/7448

-

54LS/74LS48

AnI}

BCD TO 7-SEGMENT DECODER

A11}

~I

t:T[!
BI/RB08:

:illg
TIJa

RBi~

E]b

A2~

:TIle

DESCRIPTION - The '48 translates four lines of BCD (8421) input data into
the 7-segment numeral code and provides seven corresponding outputs
having pull-up resistors, as opposed to totem pole pull-ups. These outputs
can serve as logic signals, with a HIGH output corresponding to a lighted
lamp segment, or can provide a 1.3 rnA base current to npn lamp driver transistors. Auxiliary inputs provide lamp test, blanking and cascadable zerosuppression functions.

~vcc

A3[f

J21d

GNO[!

;IJe

LOGIC SYMBOL

The '48 decodes the input data in the pattern indicated in the Truth Table and
the segment identification illustration. For a detailed description of the blanking, lamp test and zero-suppression functions refer tothe '46A data sheet, but
note that the segment output states of the '48 are the logical inverse of those
of the '46A. Also see the 'LS248 data sheet.

7

1

2

5

3

6

I I I I! !

Ao A1 A2 A3

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

Ceramic
DIP (0)

A

7448DC, 74LS48DC

5448DM, 54LS48DM

7B

Flatpak
(F)

A

7448FC, 74LS48FC

5448FM, 54LS48FM

4L

7448PC, 74LS48PC

9B

a

b

e

d

e

LT

I

RBI

9

BII
RBO

IIIIIII I

13 12 11 10 9 15 14

4

VCC = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

Ao-AJ

54174 (U.L.)

DESCRIPTION

HIGH/LOW

RBI
LT
BI/RBO

BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)

a-g

Segment Outputs (Active HIGH)

1.011.0
1.0/1.0
1.0/1.0
-/2.5
5.0/5.0
10/4.0

4-48

54174LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
-/0.75
1.25/2.0
(1.0)
2.5/3.75
(1.25)

48
NUMERICAL DESIGNATIONS -

-

-

_I -I 1 1 I-I -I
I I
- I

I I
I- I

1

4

RESULTANT DISPLAYS

- -I - I I II
I I I I
-I
I-I
I I-I -I 1-

5

6

10

9

13

12

11

I
I-

14

15

TRUTH TABLE

I

INPUTS
DECIMAL
OR
FUNCTION LT

-

-RBI

H
H
H
H

H

H
H
H
H
H

a

b

c

d

e

f

9

NOTE

H
H
H
H

H
L
H
H

H
H
H
H

H
H
L
H

H
L
H
H

H
L
H
L

H
L
L
L

L
L
H
H

1
1

L
H
L
H
L

H
H
H
H
H

L
H
L
H
H

H
L
L
H
H

H
H
H
H
H

L
H
H
L
H

L
L
H
L
H

H
H
H
L
H

H
H
H
L
H

L
H
H
L
L

H
L
H
L
H

H
H
H
H
H

H
L
L
L
H

H
L
L
H
L

H
L
H
L
L

L
H
H
L
H

L
H
L
L
L

H
L
L
H
H

H
H
H
H
H

H
H

H
H

L
H

X

X

X

X

L

L

L

L

X

X

X

X

H
H
L
L
H

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

H
L
L
L
H

H
L
L
L
H

H
L
L
L
H

H
L
L
L
H

A3

A2

A1

Ao

X
X
X

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

X
X
X
X
X

L
L
L
L
H

H
H
H
H
L

L
L
H
H
L

10
11
12
13

H
X
H
X
H
X
H I X
H
X

H
H
H
H
H

L
L
L
H
H

14
15

H
H

X
X
X

H
H

L

X

0
1

2
3
4
5
6
7
8
9

-81

X

RBI
LT

H
L

-BI/RBO

OUTPUTS

2
3
4

NOTES:
BI/RBO is wired-AND logic serving as blanking input lSi> and/or ripple-blanking output IRBOI. The blanking out lSi) must be open or
held at a HIGH level when output functions 0 through 15 are desired. and ripple-blanking input IRBII must be open or at a HIGH level
if blanking of a decimal 0 is not desired. X = input may be HIGH or LOW.

(1)

(2) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level. regardless of the state
of any other input condition.
(3) When ripple-blanking input IRBII and inputs AD. A1. A2. and A3 are at LOW level. with the lamp test input at HIGH level. all segment
outputs go to a LOW level and the ripple-blanking output IRBO) goes to a LOW level Iresponse condition!.
(4) When the blanking inpuVripple-blanking output
input. all segment outputs go to a HIGH level.

iSi/RBO)

is open or held at a HIGH level, and a LOW level is applied to lamp test

4-49

•

48
LOGIC DIAGRAM
RIPPLE-BLANKING
INPUT

1

INPUT

I

J

OUTPUT

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min
10H

Output HIGH Current at a-g

los

Output Short Circuit
Current at BIIRBO

Ice

Power Supply Current

Max

-1.3

Min

-0.3

76

XM
XC

90

UNITS

CONDITIONS

Max

-1.3
-4.0

I
I

54174LS

mA

Vee = Min, VOUT = 0.85 V

-2.0

mA

Vee = Max, VOUT = 0 V

38
38

mA

Vee = Max
All Inputs = 4.5 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74

SYMBOL

PARAMETER

54174LS

CL = 15 pF CL = 15 pF
RL = 1 k.o.
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
An to a-g

100
100

100
100

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
RBI to a-f

100
100

100
100

ns

Figs. 3-1, 3-5
Cf=HIGH,Ao-A3=HIGH

4-50

49
CONNECTION DIAGRAM
PINOUT A

54/7449
54LS/74LS49

-

AlIT

~vcc

rm,

A2[I

BCD TO 7-SEGMENT DECODER

Birr

rmg

A3[I

rm

~b

el1

~c
~d

GNO[I

DESCRIPTION - The '49 translates four lines of BCD (8421) input data into
the 7-segment numeral code as shown in the Truth Table. It has open-collector outputs and is logically the 14-pin version of the '48, without the lamp
test and ripple blanking features. Also see the 'LS249 data sheet.

LOGIC SYMBOL

i i ii!

ORDERING CODE: See Section 9
PIN
PKGS

OUT

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to HO°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Plastic
DIP(P)

A

74LS49PC

Ceramic
DIP (0)

A

74LS49DC

A

7449FC, 74LS49FC

Flatpak
(F)

Al

Ao

COMMERCIAL GRADE

A2

A3

BI

PKG
TYPE

a

c

b

e

d

,

9

9A

), 1! ! ! ,131

54LS49DM

SA

Vcc = Pin 14
GND = Pin 7

5449FM, 54LS49FM

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
54174 (U.L.)

DESCRIPTION

PIN NAMES

BI
a-g

54174LS (U.L.)
HIGH/LOW

HIGH/LOW

BCD Inputs
Blanking Input (Active LOW)
Segment Outputs (Active HIGH)

AIJ-A3

1.0/1.0
1.0/1.0
OC*/S.25

0.5/0.25
0.5/0.25
OC*/5.0
OC*/(2.5)

• OC - Open Collector

NUMERICAL DESIGNATIONS-RESULTANT DISPLAYS

-

I I
I I
0

-

-

-

I I
I 1 1 I I
1-I
-I
I-I
I
- I ,
2

3

4

5

6

-

1 I-I I-I

I I-I -I 1- -I
8

7

4-51

9

'0

"

a

Ao[I

I I I- I

'2

'3

1'4

'5

49
TRUTH TABLE
INPUTS
DECIMAL
OR
FUNCTION A3

OUTPUTS

A2

Al

Ao

-BI

a

b

c

d

e

f

9

NOTE
1

0
1
2
3

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

H
L
H
H

H
H
H
H

H
H
L
H

H
L
H
H

H
L
H
L

H
L
L
L

L
L
H
H

4
5

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

L
H
L
H

H
L
L
H

H
H
H
H

L
H
H
L

L
L
H
L

H
H
H
L

H
H
H
L

10
11

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

H
H
L
L

H
H
L
L

H
H
L
H

H
L
H
H

H
L
H
L

H
H
L
L

H
H
H
H

12
13
14
15
BI

H
H
H
H
X

H
H
H
H
X

L
L
H
H
X

L
H
L
H
X

H
H
H
H
L

L
H
L
L
L

H
L
L
L
L

L
L
L
L
L

L
H
H
L
L

L
L
H
L
L

H
H
H
L
L

H
H
H
L
L

6
7

8
9

2

NOTES:
(1) The blanking input must be open or held at a HIGH level when output functions 0 through 15 are desired.
(2) When a LOW level is applied to the blanking input all segment outputs go to a LOW level regardless of the state
of any other input condition. X = input may be HIGH or LOW.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
81

A3

~~
9

( J{ J {

{ I J( J I

((
4-52

rJ (
((

(r

49
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGEJunless otherwise specified)
SYMBOL

54174

PARAMETER

Min
VIL

Input LOW Voltage

IOH

Output HIGH Current

lee

Power Supply Current

AC CHARACTERISTICS: Vee

~
XC

~

= +5.0 V,

XC

TA

Max

PARAMETER

Min

V

250

250

p.A

Vee

= Min,

VOH

47
56

15
15

mA

Vee

= Max,

Inputs

= 15 pF
= 665 0

Min

CONDITIONS

0.7
0.8

= +25°C (See Section
CL
RL

UNITS

Max

0.6
0.8

54/74
SYMBOL

54174LS

Max

= 5.5

= 4.5 V

3 for waveforms and load configurations)

54174LS
CL = 15 pF
RL = 3 kO
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Antoa-g

100
100

100
100

ns

Figs. 3-2, 3-20

tPLH
tPHL

Propagation Delay
Bltoa-g

100
100

100
100

ns

Figs. 3-2, 3-5
RL = 6 kO for 'LS49

4-53

V

•

50
CONNECTION DIAGRAMS
PINOUT A

54/7450

54H/74H50
EXPANDABLE DUAL 2-WIDE 2-INPUT
AND-DR-INVERT GATE

PINOUT B

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

VCC = +5.0 V ±5%,
TA = O°C to +70°C

VCC = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

7450PC, 74H50PC

Ceramic
DIP(Q)

A

7450DC, 74H50DC

5450DM, 54H50DM

6A

Flatpak
(F)

B

7450FC, 74H50FC

5450FM, 54H50FM

31

9A

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54/74 (U.L.)
HIGH/LOW

54174H (U.L.)
HIGH/LOW

1.0/1.0
20/10

1.25/1.25
12.5/12.5

DC CHARACTERISTICS OVER OPERATING T,EMPERATURE RANGE: Expander Pins Open
SYMBOL

PARAMETER

54174

54174H

UNITS

CONDITIONS

Min Max Min Max
ICCH
ICCl

Power Supply Current

8.0
14

4-54

12.8
24

mA

VIN = Gnd
VIN - Open

I
I

VCC = Max

50
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE: Using Expander Pins

54174

PARAMETER

SYMBOL

54174H

UNITS

CONDITIONS

Min Max Min Max

VOH

VOH

VOL

VOL

XM

2.4

XC

2.4

Output HIGH Voltage

XM

2.4

XC

2.4

Output HIGH Voltage

XM

0.4

XC

0.4

Output LOW Voltage

XM

0.4

XC

0.4

Output LOW Voltage

VBE(Q)

Base-Emitter Voltage of
Output Transistor

XM
XC
XM
XC

hNX

Expander-Node
Input Current

XM
XC

Ix

Expander Current

XM
XC

a

1.0
1.0
1.1
1.0
-5.85
-6.3
2.9
3.1

V

h
12
h
12

=
=
=

V

h=0.15mA
12 = -0.15 mA
h = 270 mA
12 = -270 mA

V

h = 470 /LA
Rl = 68 0
h - 600 /LA
Rl = 63 0

IOl = 20 mA

V

h = 0.3 mA
Rl = 1380
h = 0.43 mA
Rl = 1300

IOl = 16 mA

V

h
h
h
h

IOl = 20 mA
Rl =00
IOl-16 mA
Rl =00

=
=
-

320 /LA
-320 /LA
570 /LA
-570 /LA

IOH = -500 /LA

IOH = -400 mA

700 u.A
1.1 mA
0.41 mA
0.62 mA

mA

Vx = 1.4 V. Vee = Min
TA = Min

mA

Vl = 0.4 V. IOl = 16 mA
Vee = Min, TA = Min

AC CHARACTERISTICS: Vee = +5.0 V. TA = +25°C (See Section 3 for waveforms and load configurations)

54174

PARAMETER

SYMBOL

54/74H

UNITS

CONDITIONS

Min Max Min Max
tPlH
tPHl

Propagation Delay

tPlH
tPHl

Propagation Delay

22
15

11
11

ns

Expander Pins Open
Figs. 3-1. 3-4

11'
7.4'

ns

Q = 25 pF
Rl = 280 O. Cx = 15 pF

"Typical Value

ADDED PROPAGATION DELAY TIME VI EXPANDER-NODE CAPACITANCE
4.0

10
CL

=1•• pF

f- CL

3.51- AL "" 2800
TA = 25°C

RL

I-TA

J

25PF

= 2800

/

= HOC

/

3.0

2.S
2.0

/'

1.5

./"

1.0

Sv

o
o

10

/
/

V

V

. / .- I--

o.

V

V

15

/

54Hson4HSO
54H53174HS3-

i

V

HS5n4 j55

20

25

o
o

30

ex-EXPANDER-NODE CAPACITANCE-pF

54HSO/74HSO
S4HS3I74H53 54Hssn4H55

10

15

20

25

ex-EXPANDER-NODE CAPACITANCE-pF

4-55

30

•

51
CONNECTION DIAGRAMS
PINOUT A

II

54/7451
54H/74H51
54S/74S51
54LS/74LS51

II
II
II
II
II

I
i

I

DUAL 2-WIDE, 2-INPUT AOI GATE
I
DUAL 2-WIDE, 2-INPUT/3-INPUT AOI GATE (,LS51)

GNOIT

-

~Yee

~~

~

~NC
TIlNC

}ID

11
]]

L.......-

PINOUT B

II

ORDERING CODE: See Section 9
PIN
PKGS

Plastic
OIP(P)

Ceramic
DIP 
w
%

"x:

CL =125 pF
RL = 2801l
TA = 25'C'

....
w

10

..........

9

>
w

0

w 2.5

.

;::

;::

..

3.0

0

:I

>j
w

Q

2.0
1.5

0

;::

c
c

1.0

"...
0

0.5

.....

10

7

w

8

>j
w

5

3

"...c

2

.....
0

15

20

25

30

/

25'C

/

/

/

4

0

~

o ",.........
5

0

::::ri
=

Z

,.......,.

0

TA
8 --

:II

Q

,.......,.
,."t.'
l
~;;.-

Z

I.

-~~

/

V

/

j't'

54H52J74H52

1V
0
0

5

10

15

20

25

Cx - EXPANDER-NODE CAPACITANCE - pF

Cx - EXPANDER·NODE CAPACITANCE - pF

4-58

30

53
CONNECTION DIAGRAMS
PINOUT A

54/7453
54H/74H53
EXPANDABLE 4-WIDE, 2-INPUT AOI GATE. ('53)
EXPANDABLE 2-2-2-3-INPUT AOI GATE ('H53)

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = 0° C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Plastic
DIP(P)

A

7453PC

B

74H53PC

Ceramic
DIP (0)

A

7453DC

5453DM

B

74H53DC

54H53DM

Flatpak

C

7453FC

5453FM

0

74H53FC

54H53FM

(F)

PKG
PINOUT B

TYPE
9A

6A

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54174 (U.L.)
HIGH/LOW

54/74H (U.L.)
HIGH/LOW

1.0/1.0
20/10

1.25/1.25
12.5/12.5
PINOUT 0

PINOUT C

4-59

•

53
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE: Using Expander Pins
SYMBOL

54174

PARAMETER

54/74H

UNITS

CONDITIONS

Min Max Min Max
XM
VOH

Output HIGH Voltage

2.4

r---

V

XC
XM
VOH

Output HIGH Voltage

2.4

V
2.4

Output LOW Voltage

XC

VOL

Output LOW Voltage

~
~
XM

VBE(Q)

Base-Emitter Voltage of
Output Transistor Q

hNX

Expander-Node
Input Current

~
XC

Ix

Expander Current

----xc

ICCH
ICCL

Power Supply Current

rxc
XM

V

IOL = 20 mA

V

h = 0.3 mA
Rl = 1380
h = 0.43 mA
Rl = 1300

IOL = 16 mA

V

h
h
h
h

IOL = 20 mA
Rl =00
IOL = 16 mA
Rl =00

0.4
0.4

l-

XC

IOH = -400 p.A

h = 470 p.A
Rl = 68 0
h = 600 p.A
Rl =630

0.4

r---

XM

12 = -0.15 mA

h - 270 p.A
12 = -270 p.A

XM
VOL

IOH = -500 p.A

h =0.15 mA

2.4

r--XC

h = 320 p.A
12= -320 p.A
h - 570p.A
12 = -570 p.A

0.4
1.0
1.0
1.1
1.0
-5.85
-6.3
2.9
3.1
8.0
9.5

11
14

= 700 JJ.A
= 1.1 mA
= 0.41 mA
- 0.62 mA

mA

Vx=1.4V

mA

Vl = 0.4 V, IOL = 16 mA

mA

VIN = Gnd
VIN = Open

VCC = Max

AC CHARACTERISTICS: Vcc = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
SYMBOL

PARAMETER

54174

54174H

UNITS

CONDITIONS

Min Max Min Max
tPLH
tPHL

Propagation Delay

tPLH
tPHL

Propagation Delay

22
15

·Typical Value

4-60

11
11

ns

Expander Pins Open
Figs. 3-1, 3-4

11.4'
7.4'

ns

Cx = 15 pF

54
CONNECTION DIAGRAMS
PINOUT A

54/7454
54H/74H54
54LS/74LS54
4-WIDE, 2-INPUT AND-OR-INVERT GATE
ORDERING CODE: See Section 9
PIN
PKGS

Plastic
DIP(P)

Ceramic
DIP (0)

Flatpak
(F)

OUT

COMMERCIAL GRADE

= +5.0 V ±5%,
TA = O°C to +70°C
Vee

A

7454PC

B

74H54PC

C

74LS54PC

A

7454DC

MILITARY GRADE
Vee

TA

= +5.0 V ±10%,

= -55°C to +125°C

PKG
TYPE

9A

PINOUT B
5454DM

B

74H54DC

54H54DM

C

74LS54DC

54LS54DM

C

74LS54FC

54LS54FM

0

74H54FC

54H54FM

E

7454FC

5454FM

6A

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54174 (U.L.)
HIGH/LOW

54174H (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
20/10

1.25/1.25
12.5/12.5

0.5/0.25
10/5.0
(2.5)

PINOUT C

PINOUT 0

4-61

PINOUT E

•

54
DC AND AC CHARACTERISTICS: See Section 3·
PARAMETER

SYMBOL

54/74

54/74H

54n4LS

UNITS

CONDITIONS

Min Max Min max Min Max
ICCH
!cCL

Power Supply Current

tPLH
tPHL

Propagation Delay

°DC limits apply over

= Gnd Iv - Max
= Openl CC-

8.0
9.5

11
14

1.6
2.0

mA

VIN
VIN

22
15

11
11

15
15

ns

Figs. 3-1, 3-4

operating temperature range; AC limits apply at TA = +25°C and Vee = +5.0 V.

4-62

55
CONNECTION DIAGRAMS
PINOUT A

54H/74H55
54LS/74LS55
EXPANDABLE 4-INPUT AOI GATE (,H55)
2-WIDE, 4-INPUT AOI GATE ('LS55)

PINOUT B

ORDERING CODE: See Section 9
PIN
PKGS

Plastic
DIP(P)
Ceramic
DIP (D)
Flatpak
(F)

OUT

COMMERCIAL GRADE

= +5.0 V ±5%,
TA = O°C to +70°C
Vee

MILITARY GRADE
Vee

TA

= +5.0 V ±10%,

= -55°C to +125°C

PINOUT C

A

74H55PC

B

74LS55PC

A

74H55DC

54H55DM

B

74LS55DC

54LS55DM

B

74LS55FC

54LS55FM

C

74H55FC

54H55FM

9A

6A

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

Inputs
Outputs

PKG
TYPE

54174H (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.25/1.25
12.5/12.5

0.5/0.25
10/5.0
(2.5)

4-63

•

55
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE: Using Expander Pins
SYMBOL

54/74H

PARAMETER

54174LS

UNITS

CONDITIONS

Min Max Min Max

VOH

VOL

XM

2.4

XC

2.4

Output HIGH Voltage

XM

0.4

XC

0.4

Output LOW Voltage

VSE(Q)

Base-Emitter Voltage of
Input Transistor Q

XM
XC

1.0
1.0

hNX

Expander-Node
Input Current

XM
XC

-5.85
-6.3

ICCH
ICCl

Power Supply Current

6.4
12

0.8
1.3

V

11
12
11
12

=
=
=

320 iJ,A
-320 iJ,A
570 iJ,A
-570 iJ,A

V

11 = 470 iJ,A
R1 = 68 n
11 = 600 iJ,A
R1 = 63 n

IOL = 20 mA

V

11 = 700 iJ,A
11 = 1.1 mA

IOl = 20 mA
R1 = 0 n

mA

Vx=1.4V

mA

VIN = Gnd
VIN - Open

IOH = -500 iJ,A

Vcc = Max

AC CHARACTERISTICS: Vcc = +5.0 V, TA = +25 0 C (See Section 3 for waveforms and load configurations)
SYMBOL

PARAMETER

54174H

54/74LS

UNITS

CONDITIONS

Min Max Min Max
tPLH
tPHl

Propagation Delay

tPlH
tPHl

Propagation Delay

11
11
11.4 '
7.7'

'Typical Value

4-64

15
15

ns

Expander Pins Open
Figs. 3-1, 3-4

ns

CL = 25 pF (Gnd to X)
Cx = 15 pF

60
CONNECTION DIAGRAMS
PINOUT A

54/7460
54H/74H60

[! I - - -

DUAL 4-INPUT EXPANDER

11
11
IT
IT
IT

ORDERING CODE: See Section 9
PIN
PKGS

OUT

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

A

7460PC, 74H60PC

Ceramic
DIP -IT I - - -

EI
}!)

m
TIl GNO
1m

'---- ]]
L.....-

II

DC AND AC CHARACTERISTICS: See Section 33
SYMBOL

PARAMETER

54/74

54/74H

UNITS

CONDITIONS4

Min Max Min Max
VON

Output ON Voltage

0.4

V

Vcc = Min, VIN = 2.0 V
V1 = 1.0 V, R = 1.1 kO
TA = Min

V

TA = -55°C
ION = 5.85 mA
TA = O°C
ION = 6.3 mA

Vcc = Min.
VIN = 2.0 V
V1 = 1.0 V

V

TA = +125°C
ION = 7.85 mA
TA = +70°C
ION = 7.4 mA

Vcc = Max,
VIN = 2.0 V,
V1 = 0.6 V

0.4
VON

Output ON Voltage
0.4
0.4

VON

Output ON Voltage
0.4

1. A maximum 01 lour expanders may be connected to one expandable ANO-OR-Invert gate
2. Expander Outputs
3. DC limits IIPply over operating temperature range; AC limits apply at TA = +25'C and Vee = +5.0 V.
4. V, is applied to x output terminal during test.

4-65

60
DC AND AC CHARACTERISTICS: See Section 31 (Cont'd)
SYMBOL

PARAMETER

54174

54/74H

UNITS

CONDITIONS2

Min Max Min Max
150
IOFF

Output OFF Current

= -55°C

TA

= O°C

TA

= -55°C

TA

= O°C

JJ.A
270
320

IOFF

TA

Output OFF Current

p.A
570
-0.47
-0.6

-0.3
0.43

ION

Output ON Current

lee(OFF)
lee(ON)

Power Supply Current

4.0
2.5

tPLH
tPHL

Propagation Delay

30
20

4.5
3.5

Vee = Min,
VIN = 0.8 V,
V1 = 4.5 V,
R = 1.2 kO
Vee = Min,
VIN = 0.8 V,
V1 = 4.5 V,
R = 575 0

mA

TA = -55°C
TA - O°C

Vee = Min,
VIN = 2.0 V,
V1 = 1.0 V

mA

VIN = Open
VIN - Gnd

Vee = Max,
V1 = 0.85 V

ns

Figs. 3-1, 3-4

OUTPUT CAPACITANCE: Vee and Ground Terminals Open
SYMBOL

PARAMETER

54174

54174H

UNITS

CONDITIONS

Min Max Min Max
Cx

Effective Capacitance of
Output Transistor 01

1. DC limits apply over operating temperature range;
2. V, is applied to x output terminal during test.
3. Typical Value

1.33
Ae limits apply at TA =

4-66

pF

+25°C and Vee = +5.0 V.

f

= 1.0 MHz, TA = +25°C

61
CONNECTION DIAGRAMS
PINOUT A

54H/74H61

C!:
IT
IT

TRIPLE 3-INPUT EXPANDER

[4
~

ORDERING CODE: See Section 9
COMMERCIAL GRADE
PIN
PKGS

OUT

II
II

MILITARY .GRADE
PKG

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

GNO!I

TYPE

Plastic
DIP (P)

A

74H61 PC

Ceramic
DIP(D)

A

74H61DC

54H61DM

6A

Flatpak
(F)

B

74H61FC

54H61FM

31

~
~
~

~~
1lJ; t!J

~

PINOUT B

~

IT
IT
IT
Vee IT
IT
IT
II ( - - - -

54/74H (U.L.)
HIGH/LOW
1.25/1.25

Inputs
Outputs

rm

9A

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

~vcc

~

rm
~

~GNO

:!PJ
]]
'---

~

' I'

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174H

PARAMETER
Min

UNITS

CONDITIONS

Max
TA = -55°C
ION = 4.5 mA
TA - O°C
ION = 5.35 mA

1.0
VON

Output ON Voltage

V
1.0

Vee = Min,
VIH = 2.0 V

IOFF

Output OFF Current

50

p.A

Vee = Min, VIL = 0.8 V
TA = Max, VOFF = 2.2 V

lee(ON)
lee(OFF)

Power Supply Current

16
7.0

mA

VIN = Open
VIN - Gnd

Vee

OUTPUT CAPACITANCE: Vee and Ground Terminals Open
54174H

PARAMETER

SYMBOL

Min
Cx

CONDITIONS

UNITS

Max

Effective Capacitance of
Output Transistor Q1

1.3"

"Expander Outputs
""Typical Value

4-67

pF

f

= 1.0 MHz,

TA

= +25°C

= Max

•

62
CONNECTION DIAGRAMS
PINOUT A

54H/74H62

II

3-2-2-3-INPUT AND-OR EXPANDER

IT

ORDERING CODE: See Section 9
PIN
PKGS

COMMERCIAL GRADE
Vee = +5.0 V ±5%,
TA = O°C to +70°C

OUT

MILITARY GRADE
Vee = +5.0 V ±10%,
TA =-55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74H62PC

Ceramic
DIP (0)

A

74H62DC

54H62DM

6A

Flatpak
(F)

B

74H62FC

54H62FM

31

-

11

m

[!

ill

II

:Thl

[!:

II
II

GNO[f

9A

PINOUT B

~
L ~
~

II
[I

IT
Vee

INPUT LOADING/FAN-OUT: See Section 3 for U.l. definitions

54174H (U.L.)
HIGH/LOW

PINS

[!

t!TI GND

II

~

I ~

[!:

~

IT

1.25/1.25
Note 2

Inputs
Outputs 1

I!l Vee
1lI

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54174H

PARAMETER

SYMBOL

UNITS

V

T = -55°C
ION = 5.85 rnA
TA - O°C
ION = 6.3 rnA

Vee = Min,
VIN = 2.0 V,
V1 = 1.0 V

V

TA = +125°C
ION = 7.85 rnA
TA = +70°C
ION = 7.4 rnA

Vee = Max,
VIN = 2.0 V,
V1 = 0.6 V

0.4
VON

Output ON Voltage
0.4
0.4

VON

Output ON Voltage
0.4
320

IOFF

Output OFF Current

TA = -55°C
p.A

570

ION

Output ON Current

lee(ON)
lee(OFF)

Power Supply Current

-470
-600
7.0
9.0

1. A maximum of one expander may be connected to one expandable AND-OR-Invert gate

2. Expander Outputs
3. V1 is applied to x output

CONDITIONS3

Max

Min

terminal during test
4-68

TA = O°C

Vee = Min,
VIN = 0.8 V,
V1 = 4.5 V,
R = 575 (}

p.A

TA =-55°C
TA = O°C

Vee = Min,
VIN = 2.0 V,
V1=1.0V

rnA

VIN = Open
VIN - Gnd

Vee = Max,
V1 = 0.85 V

62
OUTPUT CAPACITANCE: Vee and Ground Terminals Open
SYMBOL

54174H

PARAMETER
Min

Cx

Effective Capacitance of
Output Transistor Q1

UNITS

CONDITIONS

Max
1.3-

pF

f

= 1.0 MHz,

TA

= +25°C

'Typical Value

•

4-69

64
CONNECTION DIAGRAM
PINOUT A

54S/74S64
4-2-3-2-INPUT AND-DR-INVERT GATE
ORDERING CODE: See Section 9
PIN
PKGS

OUT

~

0::

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

ElVee

PKG

II -

TIl

TYPE

[I

12

9A

11
IT
IT

Plastic
DIP (P)

A

74S64PC

Ceramic
DIP (0)

A

74S64DC

54S64DM

6A

Flatpak
(F)

A

74S64FC

54S64FM

31

~~
=hllree=
,

TIl
~

~
~~

GNOIT

INPUT LOADING/FAN-OUT: See Section 3 for U.L definitions
PINS
Inputs
Outputs

54/74S (U.L.)
HIGH/LOW
1.25/1.25
25/12.5

DC AND AC CHARACTERISTICS: See Section 3*
SYMBOL

54174S

PARAMETER
Min

ICCH

12.5

Power Supply Current

rnA

Propagation Delay

CONDITIONS

2.0
2.0

5.5
5.5

'DC

limits apply over operating temperature range; AC limits apply at TA = +25°C and Vee
*'*ICCl is measured with all inputs of one gate open and remaining inputs grounded.

4-70

VIN = Gnd
**

16

ICCL
tpLH
tpHL

UNITS

Max

ns

= +5.0 V.

Figs. 3-1, 3-4

Vcc = Max

65
CONNECTION DIAGRAM
PINOUT A

545/74565
4-2-3-2-INPUT AND-DR-INVERT GATE
(With Open-Collector Output)
ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP (P)

OUT
A

COMMERCIAL GRADE

MILITARY GRADE

VCC = +5.0 V ±5%,
TA = O°C to +70°C

VCC = +5.0 V ±10%,
TA = -55°C to +125°C

74S65PC

PKG
TYPE
9A

II
IT I - - 12:
IT
IT
[I

Ceramic
DIP (0)

A

74S65DC

54S65DM

6A

Flatpak
(F)

A

74S65FC

54S65FM

31

TI.l Vee
TIl

~

m~
tJhK

m
TIl
~

t;L.J- ~
~

GNOIT

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

54/74S (U.L.)
HIGH/LOW

Inputs
Outputs

1.25/1.25
OCI/12.5

DC AND AC CHARACTERISTICS: See Section 32
SYMBOL

54174S

PARAMETER
Min

ICCH

11

Power Supply Current

mA

16

ICCl
tplH
tpHl

Propagation Delay

CONDITIONS

UNITS

Max

2.0
2.0

Note 3

7.5
8.5

10C-Open Collector
2DC limits apply over operating temperature range; AC limits apply at TA = +25°C and
31eel is measured with all inputs of one gate open and remaining inputs grounded.

4-71

VIN = 0 V

Figs. 3-2, 3-4

ns

Vee

= +5.0

V.

VCC = Max

70
CONNECTION DIAGRAMS
PINOUT A

54/7470

I!il Vee

~

NCO::

JK EDGE-TRIGGERED FLIP-FLOP

eDIT

J1[1:
DESCRIPTION - The '70 is a gated input edge-triggered J K flip-flop offering
Direct Clear and Set inputs, and complementary a and a outputs. Information at the J and K inputs is tranferred to the outputs on the positive edge of
the clock pulse. Direct-coupled clock triggering occurs at a specified voltage
level of the clock pulse. When the clock input threshold voltage has been
passed, the gate inputs are locked out. These flip-flops are designed for medium to high speed applications and offer a significant saving in system power
dissipation and package count where input gating is required.

J2G:
J3[I
a[I
GNO[I

tm

~~~ till

SD

tg]cp

~G£

K2

~K1
~K3

~O

PINOUT B
TRUTH TABLE

Asynchronous Inputs:
LOW input to So sets a to HIGH level
LOW input to CD sets a to LOW level
Clear or Set function can only
occur when clock input is LOW
Simultaneous LOW on CD and 'So is
indeterminate

INPUTS OUTPUT
@ tn + 1

@tn

a

K

J

L
H
L
H

L
L
H
H

an
L
H
an

K1IT
cp[I
5DIT

vccG:
CD [I

J = J1 • J2 • J3
K = K1 • K2 • 1<3
tn = Bit time before clock pulse.
tn + 1 = B.!,! tim~ after clock pulse.
If inputs J3 or K3 are not used
they must be grounded.
H = HIGH Voltage Level
L = LOW Voltage Level

NC[I

3l K2

Ll~ :DJm

TIl K3

SD

0

0

H~

ORDERING CODE: See Section 9

PKGS

OUT

COMMERCIAL GRADE
Vee = +5.0 V ±5%,
TA = O°C to +70°C

MILITARY GRADE
Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

=P

TYPE

),

J SD Of-CP

..&-.

Plastic
DIP(P)

A

7470PC

Ceramic
DIP (D)

A

7470DC

Flatpak

B

(F)

7470FC

9A
5470DM

=i-

K

Co OP-

y

6A
vce = Pin 14 (4)
GND = Pin 7 (11)

5470FM

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

J1.
K1,

J2,

J~

K2, K:3

CP

CD

So
a,Q

}

DESCRIPTION

54174 (U.L.)
HIGH/LOW

Data Inputs

1.0/1.0

Clock Pulse Input (Active Rising Edge)
Direct Clear Input (Active LOW)
Direct Set Input (Active LOW)
Outputs

1.0/1.0
2.0/2.0
2.0/2.0
20/10

4-72

~Q

}]J3
}] J2

J1[I

LOGIC SYMBOL

PIN

o

GNO

70
LOGIC DIAGRAM

1-

1

~

J

Q

~

~

a

~co

So-

K1

K2

K3

L"

-=--I

.f

J
"'\.

-...J-

'----L...

f

t===--

J,

~

•

J2

J3

CP

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER
Min

lee

26

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

UNITS

TA

CONDITIONS

Max

= +25° C (See Section

mA

Vee

= Max,

Vep

=0

3 for waveforms and load configurations)

54174
SYMBOL

CL
RL

DESCRIPTION

= 15 pF
= 400 n

Min
fmax

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to Q or Q

tPLH
tpHL

Propagation Delay
SD or CD to Q or Q

AC OPERATING REQUIREMENTS: Vee
SYMBOL

TA

Fig. 3-1, 3-8

50
50

ns

Figs. 3-1, 3-8

50
50

ns

Figs. 3-1, 3-10

= +25°C

Min
ts (H)

CONDITIONS

MHz

54174

PARAMETER

UNITS

Max

20

= +5.0 V,

UNITS

CONDITIONS

Max

Setup Time HIGH, In or Kn to CP

20

ns

Fig. 3-6

th (H)

Hold Time HIGH, I n or Kn to CP

5.0

ns

Fig. 3-6

ts(U

Setup Time LOW, In or Kn to CP

20

ns

Fig. 3-6

th (U

Hold Time LOW, In or Kn to CP

5.0

ns

Fig. 3-6

tw (H)
tw (U

CP Pulse Width

20
30

ns

Fig. 3-8

tw (U

SD or CD Pulse Width LOW

25

ns

Fig. 3-10

4-73

V

71
CONNECTION DIAGRAMS
PINOUT A

54H/74H71
JK MASTER/SLAVE FLIP-FLOP
(With AND-OR Inputs)
DESCRIPTION.- The '71 is a high speed JK master/slave flip-flop with
AND-OR gate inputs. The AND-OR gate inputs for entry into the master section are controlled by the clock pulse. The clock pulse also regulates the circuitry which connects the master and slave sections. Thesequence of operation is as follows: 1) isolate slave from master; 2) enter information from ANDOR gate inputs to master; 3) disable AND-OR gate inputs; 4) transfer information from master to slave. The logic state of J and K inputs must not be allowed to change when the clock pulse is in a HIGH state.
TRUTH TABLE

PINOUT B

CLOCK WAVEFORM

INPUTS OUTPU
@ tn

HIGH

@ tn + 1

LOW

J

K

Q

L
L
H
H

L
H
L
H

Qn
L
H
an

Asynchronous Input:
LOW input to So sets Q to HIGH level
Set is independent of clock

=

J
(J'A • J,s) + (J2A • J2S)
K = (K'A • K,s) + (K2A • K2S)

H = HIGH Voltage Level
L = LOW Voltage Level

tn = Bit time before clock pulse.
tn + , = Bit time after clock pulse.

LOGIC SYMBOL

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74H71PC

Ceramic
DIP (D)

A

74H71DC

54H71DM

6A

B

74H71FC

54H71FM

31

Flatpak
(F)

9A
Vcc = Pin 14 (4)
GND = Pin 7 (11)

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES

54/74H (U.L.)
HIGH/LOW

J1A, J1B, J2A, J2B }
K1A, K1B, K2A, K2B

Data Inputs

1.25/1.25

CP

Clock Pulse Input (Active Falling Edge)
Direct Set Input (Active LOW)
Outputs

2.5/2.5
3.75/3.75
12.5/12.5

So
Q,Q

4-74

71
LOGIC DIAGRAM

r-

Q

-"'\

So

K1A
K1B

K2A
K28

~~
~H

-

a

~

'--J-

~

I

~~

J'A
J'B

J2A
J28

1
CP

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174H

PARAMETER
Min

lee

UNITS

CONDITIONS

Max

Power Supply Current

30

mA

Vee

= Max,

Vep

=0 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174H
SYMBOL

PARAMETER

CL =.25 pF
RL = 280 n
Min

fmax

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to Q or Q

tPLH
tPHL

Propagation Delay
So to Q or Q

UNITS

CONDITIONS

Max

25

MHz

Figs. 3-1, 3-9

21
27

ns

Figs. 3-1, 3-9

13
24

ns

Figs. 3-1, 3-10

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54174H

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH, In or Kn to CP

0

ns

Fig. 3-18

th (H)

Hold Time HIGH, In or Kn to CP

0

ns

Fig. 3-18

ts(U

Setup Time LOW, I n or Kn to CP

0

ns

Fig. 3-18

th (U

Hold Time LOW, In or Kn to CP

0

ns

Fig. 3-18

tw (H)
tw (U

CP Pulse Width

12
28

ns

Fig. 3-9

tw (U

So Pulse Width LOW

16

ns

Fig. 3-10

4-75

•

72
CONNECTION DIAGRAMS
PINOUT A

54/7472
54H/74H72

NCD:
CO

IT

JK MASTER/SLAVE FLIP-FLOP

Jd2:

(With AND Inputs)

Jd:I

e
~

TIl Vee
:ill So

rmCl'

CD Sot>-

~~K2

Jdl 1 -

DESCRIPTION - The '72 is a high speed JK master/slave flip-flop with AND
gate inputs. The AND gate inputs for entry into the master section are
controlled by the clock pulse. The clock pulse also regulates the circuitry
which connects the master and slave sections. The sequence of operation
is as follows: 1) isolate slave from master; 2) enter information from AND gate
inputs to master; 3) disable AND gate inputs; 4) transfer information from
master to slave. The logic state of J and K inputs must not be allowed to
change when the clock pulse is in a HIGH state.
TRUTH TABLE
CLOCK WAVEFORM
INPUTS OUTPUl
@tn

J

K

L
L
H
H

L
H
L
H

GNOIT

@ tn + 1

HIGH

K,D: t-

C"PIT

LOW

a

3

2

Vee

1

4

CD

an
L
H
an

tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.
H = HIGH Voltage Loevel
L = LOW Voltage Level

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

~K'
~o

IT
IT

ilb -pSo
K

~

~K3
~K2
L

or- fmo

!TIl GNO

CP

~a

~ fJrO~ ~J3
~J2

J, IT t-

LOGIC SYMBOL

ORDERING CODE: See Section 9
PIN

[1 cr

NC[I

Asynchronous Inputs:
LOW input to So sets a to HIGH level
LOW input to CD sets a to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So is
indeterminate

rut
PINOUT B

So

J = (J'A • J,sl + (J2A • J2s1
K = (K'A • K,sl + (K2A • K2S1

PKGS

alI

tTIlK3

PKG
TYPE

~'~

0-

CP

Kco°cr-

Plastic
DIP(P)

A

7472PC, 74H72PC

Ceramic
DIP (0)

A

7472DC, 74H72DC

5472DM, 54H72DM

6A

Flatpak
(F)

B

7472FC, 74H72FC

5472FM, 54H72FM

31

'(

9A

= Pin 14 (4)
GND = Pin 7 (11)
NC = Pin 1 (6)

Vee

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

54174 (U.L.)
HIGH/LOW

54174H (U.L.)
HIGH/LOW

Jl-J3. Kl-Ka
CP

Data Inputs
Clock Pulse Input (Active Falling Edge)
Direct Clear Input (Active LOW)
Direct Set Input (Active LOW)
Outputs

1.0/1.0
2.0/2.0
2.0/2.0
2.0/2.0
20/10

1.25/1.25
2.5/2.5
2.5/2.5
2.5/2.5
12.5/12.5

CD

So
a,a

4-76

72
LOGIC DIAGRAM

r-

Q

~

'-J-

~

SD

'-

}-

K1
K2

J

I

K3

0

........-L....I

CD

~ -<
L

b

~

J,

~J2

I

J3

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER

Min
lee

Max

= +5.0 V,

TA

PARAMETER

= 15 pF
= 400 n

CL
RL

Min

Max

15

f max

Maximum Clock Frequency

tPLH
tpHL

Propagation Delay
CP to Q or Q

25
40

tPLH
tPHL

So or CD to

Propagation Delay
Q or Q

25
40

AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0 V,

ts (H)
ts (U

Setup Time
In or Kn to CP

th (H)
th (U

In or Kn to CP

Hold Time

mA

Vee

= Max,

Vep

=0

54/74H

= 25 pF
= 280 n

CL
RL

Min

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-9

21
27

ns

Figs. 3-1, 3-9

13
24

ns

Figs. 3-1, 3-10

= +25°C

54/74
Min

CONDITIONS

Max

54/74H
Min

UNITS

CONDITIONS

Max

0

0

ns

Fig. 3-18

0

0

ns

Fig. 3-18

tw (H)
tw (U

CP Pulse Width

20
47

12
28

ns

Fig. 3-9

tw (U

SO or CD Pulse Width LOW

25

16

ns

Fig. 3-10

4-77

V

3 for waveforms and load configurations)

25

TA

UNITS

Max
25

= +25°C (See Section
54/74

SYMBOL

Min

20

Power Supply Current

AC CHARACTERISTICS: Vee

54/74H

73
CONNECTION DIAGRAM
PINOUT A

54/7473

54H/74H73
54LS/74LS73
DUAL JK FLIP-FLOP
(With Separate Clears and Clocks)
DESCRIPTION - The '73 and 'H73 dual JK master/slave flip-flops have a
separate clock for each flip-flop. Inputs to the master section are controlled
by the clock pulse. The clock pulse also regulates the state of the coupling
transistors which connect the master and slavesections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from
J and K inputs to master; 3) disable J and K inputll; 4) transfer information
from master to slave.
TRUTH TABLE

CLOCK WAVEFORM

INPUTS OUTPUT
@tn

HIGH

@ tn + 1

3

2

LOW

J

K

a

L
L
H
H

L
H
L
H

an
L
H
an

4

LOGIC SYMBOL

H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.

Asynchronous Input:
LOW input to CD sets a to LOW level
Clear is independent of clock

The 'LS73 offers individual J, K, clear, and clock inputs. These dual flip-flops
are designed so that when the clock goes HIGH, the inputs are enabled
and data will be accepted. The logic level of the J and K inputs may be
allowed to change when the clock pulse is HIGH and the bistable will
perform according to the Truth Table as long as minimum setup times are
observed. Input data is transferred to the outputs on the negative-going edge
of the clock pulse.

1400

ORDERING CODE: See Section 9
PIN
PKGS

OUT

1

CP

3

K

Co

0

12L~f-9
5~

13

1.!!.

CP
K

CD

2

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Vcc = Pin 4
GND = Pin 11

PKG
TYPE·

Plastic
DIP(P)

A

7473PC, 74H73PC
74LS73PC

Ceramic
DIP (D)

A

7473DC, 74H73DC
74LS73DC

5473DM,54H73DM
54LS73DM

6A

Flatpak
(F)

A

7473FC, 74H73FC
74LS73FC

5473FM, 54H73FM
54LS73FM

31

9A

4-78

6

I

I

0 P-B

73
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
J1, J2. K1.

K2

CP1. B"2
CD1.CD2
01.02. Ch. 02

Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Outputs

54/74 (U.L.)
HIGH/LOW

54174H (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0

1.25/1.25
1.25/1.25
2.5/2.5
12.5/12.5

0.5/0.25
2.0/0.5
1.5/0.5
10/5.0
(2.5)

2.012.0

2.0/2.0
20/10

LOGIC DIAGRAMS (one half shown)

'73, 'H73
Q--~--------------~

~------------------~~Q

.......-----.-+--CD

K

CP--+---------------------------------------~

'LS73
Q--~-----------~

~------------~--Q

......-----CD
K----------i

I--------J

CP------+---------------~~-----"

4-79

•

73
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min
lee

= +5.0 V,

TA

PARAMETER

Max

54174LS

Min

UNITS

8.0

50

CL
RL

= 15 pF
= 400 n

Min

Max

54174H

mA

Max

= Max,
=0 V

load configurations)

= 15 pF

Min

UNITS

CONDITIONS

Max

f max

Maximum Clock Frequency

MHz

Fig. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CPn to Q or Q

25
40

21
27

20
30

ns

Figs. 3-1, 3-9

tPLH
tPHL

!:ropagation pelay
CDn to Q or Q

25
40

13
24

20
30

ns

Figs. 3-1, 3-10

UNITS

CONDITIONS

AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

25

Vee
Vep

54174LS

CL = 25 pF CL
RL = 280 n
Min

CONDITIONS

Max

= +25°C (See Section 3 for waveforms and
54174

SYMBOL

54174H

Min

40

Power Supply Current

AC CHARACTERISTICS: Vee

Max

15

30

= +5.0 V TA = +25°C
54174
Min

Max

54/74H

Min

Max

54174LS

Min

Max

ts (H)

Setup Time .!:!!GH
In or Kn to CPn

0

0

20

ns

th (H)

Hold Time HIGH
I n or Kn to CPn

0

0

0

ns

ts(U

Setup Time~W
In or Kn to CPn

0

0

20

ns

th (U

Hold Time LOW
I n or Kn to CPn

0

0

0

ns

tw (H)
tw (U

CPn Pulse Width

20
47

12
16

13.5
20

ns

Fig. 3-9

tw (U

CDn Pulse Width LOW

25

16

25

ns

Figs. 3-1, 3-10

4-80

Fig. 3-18
('73, 'H73)
Fig. 3-7 ('I:.S73)

74
CONNECTION DIAGRAMS
PINOUT A

54/7474
54H/74H74
54S/74S74
54LS/7 4LS7 4

C01C!:
01[i
CP,

DUAL D-TYPE POSITIVE EDGETRIGGERED FLIP-FLOP

IT

5018:

'-"

~ CP1D,~
S01

g;;; fr
~

a,IT
Q1IT
GNO

DESCRIPTION - The '74 devices are dual D-type flip-flops with Direct Clear
and Set inputs and complementary (0,0) outputs. Information at the input is
transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related
to the transition time of the positive going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of
the Clock Pulse input.

~vee
r--- ~C02

cz:

P1J02

~CP2

l

02CP2W= ~S02
CO2
~a2
S02
[
,at ~
Lr-

~02

--

PINOUT B

CP, C!: ~01
01[i
C01

~501

1L-01 aJ-..s-

rm

a1

IT r----< C01 a 1f:>---- P1J 01
~

Vee 8:
C02 IT

TRUTH TABLE
(Each Half)
INPUT

@ tn

OUTPUTS

@ tn + 1

D

0

0

L
H

L
H

H
L

Asynchronous Inputs:
LOW input to So sets 0 to HIGH level
LOW input to CD sets 0 to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So
makes both 0 and Q HIGH

02 IT
CP2

rDJGNO

~

cz: r------c;;;

H = HIGH Voltage Level
L = LOW Voltage Level
tn

=

~Q2

02 a2

s02

~a2
P:!S02

LOGIC SYMBOL

Bit time before clock pulse.

tn , , = Bit time after clock pulse.

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

TYPE

A

7474PC, 74H74PC
74S74PC, 74LS74PC

Ceramic
DIP (D)

A

7474DC, 74H74DC
74S74DC, 74LS74DC

5474DM,54H74DM
54S74DM,54LS74DM

A

74S74FC, 74LS74FC

54S74FM,54LS74FM

B

7474FC, 74H74FC

5474FM,54H74FM

9A

4-81

6A
31

J.

So,

0, - 0, t -

- cp,
CD'

Plastic
DIP(P)

Flatpak
(F)

PKG

-

0, p-

S02

-

02

-

CP2
CO2

'J'
Vee = Pin 14 (4)
GND = Pin 7 (11)

a2t-

a2 p-

74
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

Dl, D2
CP1, CP2
COl, CO2
SOl, S02

01,

ch,

02,

54174 (U.L.)

DESCRIPTION

PIN NAMES

02

54174H (U.L.)
HIGH/LOW

54174S (U.L.)

HIGH/LOW

HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
2.0/2.0

1.25/1.25
2.5/2.5

1.25/1.25
2.5/2.5

0.5/0.25
1.0/0.5

3.0/2.0

3.75/2.5

3.75/3.75

1.5/0.75

2.0/1.0

2.5/1.25

2.5/2.5

1.0/0.5

20/10

12.5/12.5

25/12.5

10/5.0
(2.5)

Data Inputs
Clock Pulse Inputs
(Active Rising Edge)
Direct Clear Inputs
(Active LOW)
Direct Set Inputs
(Active LOW)
Outputs

LOGIC DIAGRAM (one half shown)

Q

CP -+-+-+-:--1

D~===L.J

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54174

Min
Icc

Power Supply ~
XC
Current

Max

54174H
Min

Max

54/74S
Min

42
50

30
30

Max

54174LS
Min

8.0
8.0

50
50

UNITS

CONDITIONS

Max
mA

Vcc
VCP

= Max,
=0 V

AC CHARACTERISTICS: Vcc = +5.0 V, TA = +25 0 C (See Section 3 for waveforms and load configurations)
54174

SYMBOL

PARAMETER

54174H

54174S

54174LS

CL = 15 pF CL = 25 pF CL = 15 pF CL = 15 pF
RL = 400 n RL = 280 n RL = 280 n
Min

Max

Min

Max

Min

Max

fmax

Maximum Clock
Frequency

tPLH
tPHL

Propagation Delay
CPn to On or On

25
40

15
20

9.0
11

tPLH
tPHL

Propagation Delay
COn orSOn toOn orOn

25
40

20
30

tPLH
tPHL

Propagation Delay
COn orSon toOn orOn

25
40

20
30

15

35

CONDITIONS

Max
MHz

Figs. 3-1, 3-8

25
35

ns

Figs. 3-1, 3-8

6.0
13.5

15
35

ns

Vcp 2': 2.0 V
Figs. 3-1, 3-10

6.0
8.0

15
24

ns

Vcp::; 0.8 V
Figs. 3-1, 3-10

75

4-82

Min

UNITS

30

74
AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0 V,

54174
Min

Max

TA

= +25°C

54174H
Min

Max

54174S
Min

Max

54/74LS
Min

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH
On to CPn

20

th (H)

Hold Time HIGH
On to CPn

5.0

0

0

5.0

ns

ts(U

Setup Time LOW
On to CPn

20

15

3.0

20

ns

th (U

Hold Time LOW
On to CPn

5.0

0

0

5.0

ns

tw (H)
tw (U

CPn Pulse Width

30
37

15
13.5

6.0
7.3

18
15.5

ns

Fig. 3-8

tw (U

CDn or SDn Pulse
Width LOW

30

25

7.0

15

ns

Fig. 3-10

10

3.0

10

ns
Fig. 3-6

Fig. 3-6

4-83

•

75
CONNECTION DIAGRAM
PINOUT A

54/7475
4-BIT BISTABLE LATCH

-

Q1[I
0,

:m01

[I

!§lO2

odI

~Q2

II
Vee II

P1l E12

E3.4

03

~GNO

~O3
~Q3
~O4

[I

IT
Q4 IT
04

DESCRIPTION - The '75 latch is used as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (0) input is transferred to the 0 output when the
Enable is HIGH and the 0 output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information (that was
present at the data input at the time the transition occurred) is retained at the
o output until the Enable is permitted to go HIGH.

LOGIC SYMBOL

The '75 features complementary 0 and Q output from a 4-bit latch and isavailable in 16-pin packages. For higher component de!!..Sity applications, the '77
4-bit latch is available in the 14-pin package with 0 outputs omitted.

6

7

I I I I
13-

ORDERING CODE: See Section 9

3

2

0,

D2

D3

D4

01

02

03

04

E1.2

4 - E3.4

PIN
PKGS

OUT

Plastic
DIP(P)

A

COMMERCIAL GRADE

= +5.0 V ±5%,
= O°C to +70°C

Vee
TA

MILITARY GRADE

= +5.0 V ±10%,
= -55°C to +125°C

Vee
TA

7475PC

PKG
TYPE

I I I I I 11I I I

16 1 15 14

10

9B
Vcc = Pin 5
GND

Ceramic
DIP (0)

A

7475DC

5475DM

6B

Flatpak
(F)

A

7475FC

5475FM

4L

= Pin

12

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
D1-D4
E1,2
E2,3
01-04

01-04

DESCRIPTION
Data Inputs
Enable Input, Latches 1, 2
Enable Input, Latches 3, 4
Latch Outputs
Complementary Latch Outputs·

54/74 (U.l.)
HIGH/LOW
2.0/2.0
4.0/4.0
4.0/4.0
10/10
10/10

4-84

9

8

75
LOGIC DIAGRAM

a

TRUTH TABLE
(Each Latch)
INPUT

~~~~"'"?

@ tn

a

LATCH

I-x-

ENABLE

OUTPUT

@ tn +

0

Q

H
L

H
L

1

NOTES:
tn = bit time before enable
negative-going transition.
tn t 1 = bit time after enable
negative-going transition.

DATA

H = HIGH Voltage Level
L = LOW Voltage Level

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54/74

PARAMETER

SYMBOL

UNITS

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

~

= +5.0 V,

46
53

XC

TA

CONDITIONS

Max

= +25°C (See Section

mA

Vee = Max,
All Inputs = Gnd

3 for waveforms and load configurations)

54/74
PARAMETER

SYMBOL

CL
RL

= 15

pF

UNITS

CONDITIONS

= 400 n
Max

Min
tpLH
tpHL

Propagation Delay
D to Q

30
25

ns

Figs. 3-1, 3-5

tPLH
tpHL

Propagation Delay
D to

40
15

ns

Figs. 3-1, 3-4

tPLH
tpHL

Propagation Delay
E to Q, Q

30
15

ns

Figs. 3-1, 3-8

a

AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V, TA = +25° C
54174

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH, D to E

20

ns

Fig. 3-14

th (H)

Hold Time HIGH, D to E

0

ns

Fig. 3-14

ts(U

Setup Time LOW, D to E

20

ns

Fig. 3-14

th (U

Hold Time LOW, D to E

0

ns

Fig. 3-14

tw (H)

E Pulse Width HIGH

20

ns

Fig. 3-8

4-85

•

76
CONNECTION DIAGRAM
PINOUT A

54/7476
54H/74H76
54LS/74LS76
DUAL JK FLIP-FLOP
(With Separate Sets, Clears and Clocks)
DESCRIPTION - The '76 and 'H76 are dual JK master/slave flip-flops with
separate Direct Set, Direct Clear and Clock Pulse inputs for each flip-flop.
Inputs to the master section are controlled by the clock pulse. The clock pulse
also regulates the state of the coupling transistors which connect the master
and slave sections. The sequence of operation is as follows: 1) isolate slave
from master; 2) enter information from J and K inputs to master; 3) disable J
and K inputs; 4) transfer information from master to slave.
CLOCK WAVEFORM

TRUTH TABLE
INPUTS OUTPUT
@tn

@ tn + 1

J

K'

a

L
L
H
H

L
H
L
H

On
L
H
an

HIGH
LOW

H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.

Asynchronous Inputs:
LOW input to So sets
to HIGH level
to LOW level
LOW input to CD sets
Clear and Set are independent of clock
Simultaneous LOW on CD and So
makes both
and Q HIGH

a
a

a

The 'LS76 is a dual JK, negative edge-triggered flip-flop also offering indivIdual Direct Set, Direct Clear and Clock Pulse inputs. When the Clock Pulse
input is HIGH, the JK inputs are enabled and data is accepted. This data will
be transferred to the outputs according to the Truth Table on the HIGH-toLOW clock transitions.

ORDERING CODE: See Section 9
PIN
PKGS

OUT

LOGIC SYMBOL

7

2
4

11

16

10
3

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

7476PC, 74H76PC
74LS76PC

Ceramic
DIP (0)

A

7476DC, 74H76DC
74LS76DC

5476DM, 54H76DM
54LS76DM

68

Flatpak
(F)

A

7476FC, 74H76FC
74LS76FC

5476FM, 54H76FM
54LS76FM

4L

98

4-86

8

Vcc = Pin 5
GND = Pin 13

76
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
Jl, J2, Kl, K2
CP1, CP2
~01, CO2
501,502
Ql, Ql, 02, 02

Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs

54174 (U.L.)
HIGH/LOW

54174H .(U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
2.012.0
2.0/2.0
2.0/2.0
20/10

1.25/1.25
2.5/2.5
2.5/2.5
2.5/2.5
12.5/12.5

0.5/0.25
2.0/0.5
1.5/0.5
1.5/0.5
10/5.0
(2.5)

L6GIC DIAGRAMS (one half shown)
'76, 'H76
Q-1--------------__

r---------------~-a

So - t........-----+

.....-----.-+- CD

F==--J

K

CP~~---------------__i
TO OTHER
FLIP-FLOP

'LS76
Q~~--------~

~--------~~a

.....- - - - 8 0

Co-----.

I-------K
cp-+---------~---~

4-87

•

76
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54/74

Min
lee

Max

54/74H

Min

40

Power Supply Current

Max

54/74LS
Min

50

UNITS

CONDITIONS

Max
8.0

mA

Vee = Max,
Vep = 0 V

AC CHARACTERISTICS: Vee = +5.0 V,TA = +25°C (See Section 3 for waveforms and load configurations)
54174

SYMBOL

PARAMETER

54174H

54/74LS

CL = 15 pF CL = 25 pF CL = 15 pF UNITS
RL=400n RL = 280 n
Min

Max

15

Min

Max

fmax

Maximum Clock Frequency

25

tPLH
tPHL

Propagation Delay
CPn to On or an

25
40

21
27

tPLH
tpHL

Propagation Delay
COn or SOn to On or an

25
40

13
24

Min

CONDITIONS

Max
MHz

Figs. 3-1, 3-9

20
30

ns

Figs. 3-1, 3-9

20
30

ns

Figs. 3-1, 3-10

UNITS

CONDITIONS

30

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54/74

Min

Max

54/74H

Min

Max

54/74LS
Min

Max

18 (H)

Setup Time HIGH
In or Kn to CPn

0

0

20

ns

th (H)

Hold Time HIGH
In or Kn to CPn

0

0

0

ns

Fig. 3-18
('76, 'H76)

18(Ll

Setup Time LOW
I n or Kn to CPn

0

0

20

ns

Fig. 3-7
('LS76)

th (Ll

Hold Time LOW
In or Kn to CPn

0

0

0

ns

tw (H)
tw (Ll

CPn Pulse Width

20
47

12
28

20
13.5

ns

Fig. 3-9

tw

COn or SOn Pulse Width LOW

25

16

25

ns

Fig. 3-10

(Ll

4-88

77
CONNECTION DIAGRAM
PINOUT A

54/7477
QUAD D-TYPE LATCH

-

D1IT
Dd]:

TI)02

E3.4!I

In1 E1.2

Vee

DESCRIPTION - The '77 contains four D-type latches used for temporary
storage. Each latch shares an Enable input with one other latch. When the
Enable input is HIGH, a latch is transparent, Le., the 0 output follows the D
input each time itchanges. When the Enable goes LOW, the information 

PKG

J

TYPE

CP

SO

a

J So Q

9A

4-90

6A
Vcc = Pin 14 (4)
GND = Pin 7 (11)
31

78
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

54174H (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

J1, J2, K1, K2
CP

Data Inputs
Clock Pulse Input (Active Falling Edge)
Direct Clear Input (Active LOW)
Direct Set Inputs (Active LOW)
Outputs

1.25/1.25
2.5/2.5
5.0/5.0
2.5/2.5
12.5/12.5

0.5/0.25
4.0/1.0
3.0/1.0
1.5/0.5
10/5.0
(2.5)

Co
S01, S02
01, ck 02,

ch

LOGIC DIAGRAM
(one half shown)
Q -

.....- - - - - - - - - - - - - . .

a

~----------......-

.....----....-ii--

Co

K----I

cp-~--------------------_t

TO OTHER

FLIP-FLOP

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174H

PARAMETER

Min
lee

Power Supply Current

AC CHARACTERISITICS: Vee

= +5.0

Max

Min

V, TA

PARAMETER

8.0

= +25°C (See Section

Max

25

CONDITIONS

rnA

Vee

= Max,

Vep

54/74LS

Min

UNITS

CONDITIONS

Max

fmax

Maximum Clock Frequency

MHz

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP to On or an

21
27

20
30

ns

Figs. 3-1, 3-9

tpLH

Propagation Delay

tPHL

CD or SOn to On or an

13
24

20
30

ns

Figs. 3-1, 3-10

30

4-91

=0 V

3 for waveforms and load configurations)

CL = 25 pF CL = 15 pF
RL = 280 n
Min

UNITS

Max

50

54174H
SYMBOL

54/74LS

78
AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0 V,

TA

= +25°C

54/74H
Min

Max

54/74LS
Min

UNITS

CONDITIONS

Max

Setup Time HIGH
In or Kn to CP

0

20

ns

th (H)

Hold Time HIGH
In or Kn to CP

0

0

ns

ts(U

Setup Time J::2W
I n or Kn to CP

0

20

ns

th (U

Hold Time LOW
In or Kn to CP

0

0

ns

tw (H)
tw (U

CP Pulse Width

12
28

20
13.5

ns

Fig. 3-9

tw (U

Co or SOn Pulse Width LOW

16

25

ns

Fig. 3-10

ts

(H)

4-92

Fig. 3-18 ('H78)
Fig. 3-7 ('LS78)

80
CONNECTION DIAGRAMS
PINOUT A

54/7480

a"

GATED FULL ADDER

-

0:

:EJvcc

acl1

nJ a2

cnl:!

ma,

Cn+l[i

TIJAC

lIT
~l!

!ill A·
]]A2

GNOU

]:lA'

PINOUT B

DESCRIPTION - The '80 is a single-bit, high speed, binary full adder with
gated complementary inputs, complementary sum (~ and~) outputs and inverted carry output. It is designed for medium and high speed, multiplebit, parallel-add/serial carry applications. The circuit utilizes DTL for the
gated inputs and high speed, high fan-out TTL for the sum and carry outputs.
The circuit is entirely compatible with both DTL and TTL logic families. The
implementation of a single-inversion, high speed, Darlingtion-connected
serial-carry circuit minimizes the necessity for extensive "Iookahead" and
carry-cascading circuits.

AcO:

:EJA"c

a,l1

nJ A2

a21:!

mA,

vcc[i

TIlGNO

IT

acl!

!illi
]]I

CnU

]:lcn+'

a"

LOGIC SYMBOL
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

i i 1j YY1j 1 i

PKG

A1 A2 A* Ac 81 82 8· Be

TYPE
3 - Cn

Plastic
DIPIP)

A

7480PC

Ceramic
DIP (0)

A

7480DC

5480DM

SA

Flatpak
(F)

B

7480FC

5480FM

31

9A

Cn+1

I

I

! ! !
vcc = Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L definitions
PIN NAMES
A" A2, B" B2
A", B"
Ae, Be
C

n
en
+'
~,T

A", B"

DESCRIPTION

54174 (U.L.)
HIGH/LOW

0.4/1.0
-/1.63
0.4/1.0
5.0/5.0
5.0/5.0
10/10
3.0/3.0

Operand Inputs
Inverted Operand Inputs
Control Inputs
Carry Input
Inverted Carry Output
Sum Outputs
When Used As Outputs

4-93

•

80
TRUTH TABLE
INPUTS
OUTPUTS

I

I

H
H
H
L

H
L
L
H

L
H
H
L

H
L
L
L

L
H
H
L

H
L
L
H

Cn

B

A

Cn

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

L
L
H
H

L
H
L
H

+ 1

LOGIC DIAGRAM
A,

T":""oo..

A2

I'

A'

~

,

:=:D I? p- w-O-'
::::r

Ac

Be

NOTES:
(11

A = A'. Ac, B = B' • Be
B' = B, • B2

where

A, • A2.

B' are used as inputs, A, and A2
or B, and B2 respectively must beconnected to
Gnd.

(21 When A' or

~
.........

Cn

~

A, and A2 or B, and B2 are used as inputs, A' or B' respectively must be open or
used to perform Dot-OR logic.

(31 When

-

- Cn+1

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unlsess otherwise specified)
SYMBOL

54174

PARAMETER

UNITS

Min

Max

CONDITIONS

los

Output ShO.!,t Ci rcuit
Current at Cn + 1

XM
XC

-20
-18

-70
-70

mA

Vee = Max

los

Output Short Circuit
Curren't at A', B'

XM
XC

-0.9
-0.9

-2.9
-2.9

mA

Vee = Max

lee

Power Supply Current

XM
XC

31
35

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25 0 C (See Section 3 for waveforms and load configurations)

54174
SYMBOL

PARAMETER

CL = 15 pF
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Cn to en + 1

17
12

ns

Figs. 3-1, 3-4
RL = 780 n

tPLH
tPHL

PropaQ!ltion Delay
Be to Cn + 1

25
55

ns

Figs. 3-1, 3-5
RL = 780 n

tPLH
tPHL

Propagation Delay
Ae to I

70

ns

Figs. 3-1, 3-4
RL=400n

tPLH
tPHL

Propagation Delay
Be to I

55
75

ns

Figs. 3-1, 3-5
RL = 400 n

tPLH
tPHL

Propagation Delay
Al to A' or Bl to B'

65
25

ns

Figs. 3-1, 3-4
RL not used

80

4-94

82
CONNECTION DIAGRAM
PINOUT A

54/7482
2-BIT FULL ADDER

DESCRIPTION - The '82 is a full adder which performs the addition of
two 2-bit binary numbers. The sum (~) outputs are provided for each bit
and the resultant carry (C2) is obtained from the second bit. Designed for
medium to high speed, multiple-bit, parallel-add/serial-carry applications,
the circuit utilizes high speed, high fan-out TTL. The implementation of
a single-inversion, high speed, Darlington-connected serial-carry circuit
withi n each bit mini mizes the necessity for extensive "Iookahead" an d carrycascading circuits.

ORDERING CODE: See Section 9
PIN
PKGS

2

3

14

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

I I I I

PKG
TYPE

Plastic
DIP(P)

A

7482PC

Ceramic
DIP (0)

A

7482DC

5482DM

6A

Flatpak
(F)

A

7482FC

5482FM

31

9A

Vcc = Pin 14
GND = Pin 11
NC = Pins 6,7,8,9

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
A1, B1
A2, B2
CIN

~1
~2

C2

DESCRIPTION
Bit
Bit
Bit
Bit
Bit
Bit

1
2
1
1
2
2

13

5 - C'N

COMMERCIAL GRADE

OUT

LOGIC SYMBOL

Operand Inputs
Operand Inputs
Carry Input
Sum Output
Sum Output
Carry Output

54174 (U.L.)
HIGH/LOW
4.0/4.0
1.0/1.0
4.0/4.0
10/10
10/10
5.0/5.0

4-95

82
TRUTH TABLE
OUTPUTS

INPUTS

C,N =0

C,N = 1

A1

81

A2

82 I1

I2

C2

I1

I2 C2

L
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

L
H
H
L

L
L
L
H

L
L
L
L

H
L
L
H

L
H
H
H

L
L
L
L

L
H
L
H

L
L
H
H

H
H
H
H

L
L
L
L

L
H
H
L

H
H
H
L

L
L
L
H

H
L
L
H

H
L
L
L

L
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

H
H
H
H

L
H
H
L

H
H
H
L

L
L
L
H

H
L
L
H

H
L
L
L

L
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

L
H
H
L

L
L
L
H

H
H
H
H

H
L
L
H

L
H
H
H

H
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

4-96

82
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

los

Output Short Circuit
Current at In

los

54174

PARAMETER

Output Short Circuit
Current at C2

Max

XM

-20

-55

XC

-18

-55

XM

-20

-70

XC

-18

-70

r--

r---XM

lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0

r---

50

XC

58

V, TA

= +25

0

CONDITIONS

UNITS

Min

mA

Vee

= Max

mA

Vee

= Max

mA

Vce = Max;
A1, A2, CIN = 4.5 V;
B1, B2 = Gnd

C (See Section 3 for waveforms an d load configurations)
54174

SYMBOL

PARAMETER

CL
RL

= 15 pF
= 400 n

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
CIN to l1

34
40

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
B2 to l2

40
35

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
CIN to l2

38
42

ns

Figs. 3-1, 3-20

'tPLH
tPHL

Propagation Delay
CIN to C2

19
27

ns

Figs. 3-1, 3-5
RL = 780 n

4-97

•

83A
CONNECTION DIAGRAM
PINOUT A

5417483A
54LS/74LS83A
4-BIT BINARY FULL ADDER
(With Fast Carry)

DESCRIPTION - The '83A high speed 4-bit binary full adders with internal
carry lookahead accept two 4-bit binary words(Ao --' A3, So - 63) and a Carry
input (Co)' They generate the binary Sum outputs (So - S3) and the Carry
output (C4) from the most significant bit. They operate with either HIGH or
active LOW operands (positive or negative logic). The '283 is recommended
for new designs since it features standard corner power pins.

ORDERING CODE: See Section 9
______
-.____ COMMERCIAL GRADE

~------------------._----------------,_--~13

PIN

PKGS

OUT

7 3' 4 1 16

Co

14

r----------------r--------------~ PKG
Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

TYPE
9

A

7483APC, 74LS83APC

Ceramic
DIP (D)

A

7483ADC, 74LS83ADC

5483ADM, 54LS83ADM

66

A

7483AFC, 74LS83AFC

5483AFM, 54LS83AFM

4L

(F)

10 11 8

MILITARY GRADE

Plastic
DIP(P)

Flatpak

LOGIC SYMBOL

6 2 15

96

Vce = Pin 5
GND = Pin 12

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
54/74 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

So-53

A Operand Inputs
6 Operand Inputs
Carry Input
Sum Outputs

1.0/1.0
1.0/1.0
1.0/1.0
20/10

C4

Carry Output

10/5.0

1.0/0.5
1.0/0.5
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

PIN NAMES
Ao-A3
60-63
Co

DESCRIPTION

4-98

83A
FU NCTIONAL DESCRIPTION - The '83A adds two 4-bit binary words (A and B) plus the incoming carry. The
binary sum appears on the sum outputs (So - S3) and outgoing carry (C4) outputs.
Co

+ (Ao + Bo) + 2 (AI + Bl) + 4 (A2 + B2) + 8 (A3 + B3)

=

So

+ 2S1 + 4S2 + 8S3 + 16C4

Where: (+) = plus
Due to the symmetry of the binary add function the '83A can be used with either all inputs and outputs active
HIGH (positive logic) or with all inputs and outputs active LOW (negative logic)' Note that with active HI GH
inputs, Carry In can not be left open, but must be held LOW when no carry in is intended.
Interchanging inputs of equal weight does not affect the operation, thus Co, Ao, Bo can be arbitrarily assigned to
pins 10, 11, 13, etc.

TRUTH TABLE
INPUTS

Co Ao

AI

A2

As

Bo

OUTPUTS
Bl

B2

B3

So

SI

S2

S3

C4

Logic Levels

L

L

H

L

H

H

L

L

H

H

H

L

L

H

Active HIGH
Active LOW

0
1

0
1

1
0

0
1

1
0

1
0

0
1

0
1

1
0

1
0

1
0

0
1

0
1

1
0

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM
Co

Ao

Bo

A3

4-99

B3

(10 + 9 = 19)
(carry + 5 + 6

= 12)

•

83A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

Min
los

Output Short Circuit
Current at Sn

los

Output Short Circuit
Current at C4

lee

Power Supply Current

AC CHARACTERISTICS: Vee

54174LS

54174

PARAMETER
XM
I--XC
XM
I--XC

Max

Min

Max

-20

-55

-20

-100

-18

-55

-20

-100

-20

-70

-20

-100

-18

-70

-20

-100

XM
I--XC

99

39

110

39

mA

Vee

= Max

mA

Vee

= Max

mA

Vee = Max,
Inputs = Gnd ('LS83A)
Inputs = 4.5 V ('83A)

= 5.0 V, TA = 25° C (See Section 3 for waveforms and load configurations)
54174

SYMBOL

CONDITIONS

UNITS

PARAMETER

CL
RL

54174LS

= 15 p'F CL = 15 pF
= 400 fl

Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tpHL

Propagation Delay
Co to Sn

21
21

24
24

ns

Fi gs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
An or Bn to Sn

24
24

24
24

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
Co to C4

14
16

17
17

ns

Figs. 3-1, 3-5
RL = 780 fl ('83A)

tPLH
tPHL

Propagation Delay
An or Bn to C4

14
16

17
17

ns

Figs. 3-1, 3-5
RL = 780 fl ('83A)

4-100

85
CONNECTION DIAGRAM
PINOUT A

54/7485
54LS/74LS85

~vcc

~

B31I

II
IA =s II

!TIl A3

IT
IT

~A2
~A1
~B1
~AO
~BO

IA s
OA >s

~B2

OFS[!
OA B, A < B, A = B OUTPUTS AVAILABLE

1f 1j YY i 1,1 1t

ORDERING CODE: See Section 9
PIN
PKGS

OUT

i

Ao A1 A2 A3 Bo B1 B2 B3

2 - IA s
OA>S

I

5

Plastic
DIP (P)

A

7485PC, 74LS85PC

Ceramic
DIP (0)

A

7485DC, 74LS85DC

5485DM, 54LS85DM

6B

Flatpak
(F)

A

7485FC, 74LS85FC

5485FM, 54LS85FM

4L

OA <8

I

7

OA =s

I

6

9B
vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

54174 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

3.0/3.0
3.0/3.0
3.0/3.0
1.0/1.0
10/10

1.5/0.75
1.5/0.75
1.5/0.75
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)
10/5.0
(2.5)

Ao-As
Bo-B3
IA = S
IA < S, IA > S
OA > S

Word A Inputs
Word B Inputs
A = B Expansion Input
A < B, A > B Expansion Inputs
A Greater Than B Output

OA < B

A Less Than B Output

10/10

OA = B

A Equal B Output

10/10

4-101

85
FUNCTIONAL DESCRIPTION-The '85 compares two 4-bit words (A, 8). Each word has four parallel inputs
(Ao-A3, 80-83) of which A3 and 83 are the most significant. Three expanderinputs (IA > B, IA < B, IA = B) allow

cascading without external gates. The three outputs (OA > B, OA < B, OA = B) have only two gate delays from the
expander inputs, thus reducing the delay time when units are cascaded for long words. The IA = B input to the
least significant position must be held HIGH for proper compare operation. For serial (ripple) expansion, the A >
8, A < 8 and A = 8 outputs are connected respectively to the IA > B, IA < B, and IA = B inputs of the next most
significant comparator.

LOGIC DIAGRAM
80

l

AD

A1

9"

.. .

T'

1

'f
!

Y

OA8 IA=8 IA<8

. ·,t

I

.

82

t~tI"

OA =8

4-102

83

. t- .

1

I"

"I

11

T9
1

Y
OA >8

-)

85
TRUTH TABLE
COMPARING INPUTS

CASCADING INPUTS

OUTPUTS

A1. B1

AfJ. Bo

IA > B

IA < B

IA = B

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

H
L
H
L

L
H
L
H

L
L
L
L

X
X
AfJ>Bo
AfJ B3
A3 < B3
A3 = B3
A3 = B3

X
X
A2 > B2
A2 < B2

A3 =
A3 =
A3 =
A3 =

B3
B3
B3
B3

A2
A2
A2
A2

=
=
=
=

B2
B2
B2
B2

A1
A1
A1
A1

>
<
=
=

B1
B1
B1
B1

A3 = B3
A3 = B3
As = B3
As = B3
As = B3

A2
A2
A2
A2
A2

=
=
=
=
=

B2
B2
B2
B2
B2

A1
A1
A1
A1
A1

=
=
=
=
=

OA>B

OAe

A,,"'-

OAe

#.

IAS
IA>e

,

.A

j'jA{j'BiBrTBI'

Ar AI' ArArBr·Bi'BrBr

.

An Al A2 A3 80 8, 82 83

Ao Al A2 A3 Bo 8, 82 83
IA>B

IAa
DAe

IAB

#3

ArArArAr BrBrBrBr

F1

r--

0DABS
... r-NC

IA-B

J

An Al A2 A3 80 8, 82 83

A'4- IA>e

DA>B

L-

1

OAB
IAB
OA>B
L - IAB

------------- IA=B

54LS174LS85

IAB r-A>8
OA B or OA < B

26
30

36
30

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
An or Bn to OA = B

35
30

45
45

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
An Ixx to OA > B or OA < B

11
17

22
17

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation. Delay
IA = B to OA = B

20
17

22
17

ns

Figs. 3-1, 3-5

4-104

86
CONNECTION DIAGRAM
PINOUT A

54/7486
54S/74S86
54LS/74LS86
QUAD 2-INPUT EXCLUSIVE-OR GATE

IT ----,

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

II
IT
IT

PKG

Plastic
DIP(P)

A

7486PC, 74S86PC
74LS86PC

Ceramic
DIP(D)

A

7486DC, 74S86DC
74LS86DC

5486DM, 54S86DM
54LS86DM

6A

Flatpak
(F)

A

7486FC, 74S86FC
74LS86FC

5486FM, 54S86FM
54LS86FM

31

~

II
~

TYPE

[I

9A

GNOIT

~vee

~

. -~
~
~
. -~

~

~

~~

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

54174 (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

Inputs
Outputs

1.011.0
20/10

1.25/1.25
25/12.5

1.0/0.375
10/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

54174

PARAMETER

54174S

54/74LS

UNITS

CONDITIONS

Min Max Min Max Min Max

I
I

XM
XC

43
50

lee

Power Supply Current

tPLH
tPHL

Propagation Delay

23
17

tPLH
tPHL

Propagation Delay

30
22

·DC limits apply over operating

temperature range;

AC limits apply at TA

=

75
75

10
10

mA

Vee

3.5
3.0

10.5
10

12
17

ns

Other Input LOW
Figs. 3-1, 3-5

3.5
3.0

10.5
10

13
12

ns

Other Input HIGH
Figs. 3-1, 3-4

+25"C and Vee

4-105

=

+5.0 V.

= Max,

VIN

= Gnd

•

87
CONNECTION DIAGRAM
PINOUT A

54H/74H87
4-BIT TRUE/COMPLEMENT,
ZERO/ONE ELEMENT

-

o,lI

~vcc
~14
~O4

NC!I

PlNC

sdJ:
h[I

DESCRIPTION - The '87 performs four operations at its outputs, depending
on the state of the Select inputs SI and S2. The outputs can be forced
HIGH or LOW, or can follow the Datainputs in eithertheTrueor Complement
form. The Select input coding and the output responses are shown in the
Truth Table.

12

~b

(I

od]:

~O3

GNOII

~s,

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Plastic
DIP (P)

A

74H87PC

Ceramic
DIP (D)

A

74H87DC

PKG
TYPE

LOGIC SYMBOL

i i rI

9A
54H87DM

6A

I,

18-

Flatpak
(F)

A

54H87FM

74H87FC

31

12 13

14

s,
52
0, 02 03 04

1! ! 1l

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
11-14
SI, S2
01-04

54174H (U.L.)
HIGH/LOW

DESCRIPTION
Data Inputs
Select Inputs
Outputs

1.25/1.25
1.25/1.25
25/12.5

TRUTH TABLE
SELECT
INPUTS

OUTPUTS

SI

S2

J01 D2

L
L
H
H

L
H
L
H

11

h
H
L

12
12
H
L

= HIGH Voltage Level
L = LOW Voltage Level

H

4-106

0:3

04

13

T4
14
H
L

i3
H
L

VCC ~ Pin 14
GND ~ Pin 7

87
LOGIC DIAGRAM

DATA INPUTS

01

CONTROL INPUTS

02

•

v

03

04

OUTPUTS

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174H

PARAMETER
Min

VOH

Output HIGH Voltage

Ice

Power Supply Current

CONDITIONS

UNITS
Max
V

2.4
XM

78

XC

89

mA

Vee = Min, IOH
VIH = 2.0 V, VIL
Vee

=

= -1.0 mA,
= 0.8 V

Max

AC CHARACTERISTICS: Vee = 5.0 V, TA = 25° C (See Section 3 for waveforms and load configurations)
54174H
SYMBOL

PARAMETER

CL = 25 pF
RL = 280 n
Min

UNITS

Max

tpLH
tPHL

Propagation Delay
In to On

20
19

ns

tPLH
tPHL

Propagation Delay
Sn to On

25
25

ns

4-107

CONDITIONS

Figs. 3-1, 3-20

89
CONNECTION DIAGRAM
PINOUT A

54/7489
54LS/74LS89

~

AOO::

64-BIT RANDOM ACCESS MEMORY
(With Open-Collector Outputs)

mVCC

cs[I

illA1

WE [I

:E]A2

[I

:m

A3

011}

rm

04

0,

~04
~03
~(h

02[!

DESCRIPTION - The '89 a high speed, low power 64-bit Random Access
Memory organized as a 16-word by 4-bit array. Address inputs are buffered
to minimize loading, and addresses are fully decoded on-chip. Outputs are
open-collector type and are in the off (HIGH) state when both the Chip Select
(CS) and Write Enable (WE) are HIGH. For all other combinations of CS and
WE the outputs are active, presenting the complement of either the stored
data (READ mode) or the information present on the D inputs.

•
•
•
•

02 [I
GNOII

LOGIC SYMBOL

OPEN-COLLECTOR OUTPUTS FOR WIRED-AND APPLICATIONS
BUFFERED INPUTS MINIMIZE LOADING
ADDRESS DECODING ON-CHIP
DIODE CLAMPED INPUTS MINIMIZE RINGING

1i i T 1
1j
cs 0, 02 03 04 WE

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
Vcc
TA

MILITARY GRADE

= +5.0 V ±5%,

Vcc

= O°C to +70°C

TA

PKG

= +5.0 V ±10%,

= -55°C to +125°C

TYPE

Plastic
DIP (P)

A

7489PC, 74LS89PC

Ceramic
DIP (0)

A

7489DC, 74LS89DC

5489DM, 54LS89DM

78

Flatpak
(F)

A

7489FC, 74LS89FC

5489FM, 54LS89FM

4L

98

1151413-

Ao
A1
A2
A3
0, 02 03 04

!!!X
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-A3
CS
WE
D1-D4
01-04
'oc -

54174 (U.L.)
HIGH/LOW

DESCRIPTION
Address Inputs
Chip Select Input (Active LOW)
Write Enable Input (Active LOW)
Data Inputs
I nverted Data Outputs

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0

OC'n.5

Open Collector

4-108

54174LS (U.L.)
HIGH/LOW
0.5/0.013
0.5/0.013
0.5/0.013
0.5/0.013
OC'/10
(5.0)

89
FUNCTION TABLE
INPUTS

OPERATION

CONDITION OF OUTPUTS

CS

WE

L
L

L
H

Write
Read

Complement of Data Inputs
Complement of Selected Word

H
H

L
H

Inhibit Entry
Hold

Undetermined
(Off) HIGH

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

r':>---.....-

WE

I\,.....JIO-......-+-- CS

Ao

DECODER
DRIVERS

16-WORD x 4-BIT
MEMORY CELL
ARRAY

ADDRESS
DECODER

4-109

89
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER

Min
IOH

VOL

Output HIGH Current

Output LOW Voltage

54/74LS

Max

Min

20

I

XM, XC

I

XC

Ice

Power Supply Current

Co

Off-State Output Capacitance

UNITS

CONDITIONS

/lA

Vee = Min, VOH = 5.5 V

Max
20

0.4
0.45

V

Vee = Min

0.4
0.5

V

40

mA

Vee = Min, CS = Gnd

pF

Vo = 2.4 V, f = 1 MHz

105
4.0*

IOL=12mA
IOL=16mA
IOL - 8.0 mA
IOL = 16 mA

4.0'

Vee = Min

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

54/74
SYMBOL

PARAMETER

54/74LS

CL = 30 pF CL = 15 pF
RL = 3000 RL = 2 kO
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
CS to On

50
50

10*
10*

ns

Figs. 3-2, 3-5
'89 has 600 0 to Gnd

tPLH
tpHL

Propagation Delay
An to On

60
60

37*
37*

ns

Figs. 3-2, 3-20
'89 has 600 0 to Gnd

trec

Recovery Time
WE to On

70

30*

ns

Figs. 3-2, 3-4, 3-5
'89 has 600 0 to Gnd

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54/74
Min

Max

54/74LS
Min

UNITS

CONDITIONS

Max

ts (H)
t8 (l)

Setup Time HIGH or LOW
On to WE

40
40

25*
25*

ns

Fig. 3-13

ts (H)
t8 (l)

Setup Time HIGH or LOW
An to WE

0
0

10*
10'

ns

Fig. 3-21

th (H)
th (l)

Hold Time HIGH or LOW
On or An to WE

5.0
5.0

0*

ns

Figs. 3-13, 3-21

tw

WE Pulse Width LOW

40

25*

ns

Fig. 3-21

(l)

O·

·Typical Value

4-110

90
CONNECTION DIAGRAM
PINOUT A

54/7490A

54LS/74LS90

CP,

~cpo

MR'[1:

~NC
~oo

IT
MRl IT

DECADE COUNTER

~

~03
~GND
~01
~02

NCG
Vee

II

MSli1:

DESCRIPTION - The '90 is a 4-stage ripple counter containing a high speed
flip-flop acting as a divide-by-two and three flip-flops connected as a divideby-five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50% duty cycle output. In the
BCD mode, HIGH signals on the Master Set (MS) inputs set the outputs to
BCD nine. HIGH signals on the Master Reset (MR) inputs force all outputs
LOW. For a similar counter with corner power pins, see the 'LS290; for dual
versions, see the 'LS390 and 'LS490.

ORDERING CODE: See Section 9
PIN
PKGS

OUT

MILITARY GRADE

= +5.0 V ±5%,

TA = O°C to +70°C

LOGIC SYMBOL
6 7

t9
MS

COMMERCIAL GRADE
Vee

MS2IT

Vee

TA

PKG

= +5.0 V ±10%,

= -55°C

to +125°C

TYPE

Plastic
DIP (P)

A

7490APC, 74LS90PC

Ceramic
DIP (D)

A

7490ADC, 74LS90DC

5490ADM, 54LS90DM

6A

Flatpak
(F)

A

7490AFC, 74LS90FC

5490AFM, 54LS90FM

31

9A

14--0 cPo
1--0 CP,
MR

00 0, 02 03

~

2 3 12 9 8 11
vCC = Pin 5
GND = Pin 10
NC = Pins 4, 13

INPUT LOADING/FAN-OUT: See Section 3 for U.L. defintions
PIN NAMES

00

+2 Section Clock Input
(Active Falling Edge)
+5 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Inputs
(Active HIGH)
Asynchronous Master Set
(Preset 9) Inputs (Active HIGH)
+2 Section Output'

01-03

+5 Section Outputs

CPo
CP1
MR1, MR2
MS1, MS2

'The 00 output is guaranteed to drive the full rated fan-oat plus the

HIGH/LOW

54174LS (U.L.)
HIGH/LOW

2.0/2.0

0.125/1.5

3.0/3.0

0.250/2.0

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

20/10

10/5.0
(2.5)
10/5.0
(2.5)

54174 (U.L.)

DESCRIPTION

20/10
ep,

input.

4-111

•

90
FU NCTIONAL DESCRIPTION - The '90 is a 4-bit ripple type decade counter. It consists of four master/slave
flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five section. Each
section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock
transition. State changes of the 0 outputs do not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals are subject to decoding spikes and should not beused for clocks or strobes.
The 00 output of each device is designed and specified to drive the rated fan-out plus the CP1 input. A gated
AND asynchronous Master Reset (MR1, M R2) is provided which overrides the clocks and resets (clears) all the
flip-flops. A gated AN D asy nchronous Master Set (MS1, MS2) is provided which overrides the clocks and the MR
inputs and sets the outputs to nine (HLLHl. Since the output from the divide-by-two section is not internally
connected to the succeeding stages, the devices may be operated in various counting modes.:
A. BCD Decade (8421) Counter - The CP1 input must be externally connected to the 00 output. The CPo
input receives the incoming count and a BCD count sequence is produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter - The 03 output must be externally connected to the
CPo input. The input count is then applied to the CP1 input and a divide-by-ten square wave is obtained at
output 00.
C. Divide-By-Two and Divide-By-Five Counter - No external interconnections are required. The first
flip-flop is used as a binary element for the divide-by-two function (CPo as the input and 00 as the outputl.
The CP1 input is used to obtain binary divide-by-five operation at the 03 output.
MODE SELECTION
RESET/SET INPUTS
MR1 MR2

BCD COUNT SEQUENCE

OUTPUTS

OUTPUTS

COUNT

MS1

MS2

00

01

03

03

H
H
X

H
H
X

L
X
H

X
L
H

L
L
H

L
L
L

L
L
L

L
L
H

L
X
L
X

X
L
X
L

L
X
X
L

X
L
L
X

00

01

02

03

1
2
3
4

L
H
L
H
L

L
L
H
H
L

L
L
L
L
H

L
L
L
L
L

5
6
7
8
9

H
L
H
L
H

L
H
H
L
L

H
H
H
L
L

L
L
L
H
H

0

Count
Count
Count
Count

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

NOTE: Output 00 is connected
to Input CP, for BCD count.

LOGIC DIAGRAM
MR,
MR2

=D
J

CPo

I

I

so

01-

So

co

Q

K

So

0--<

~cP

CP
K

-J

~CP
Q

so co

y

=D

K

r-r---OICP
Q

So co

t--I---fl-l-L..J

s co

Q

Y

CP,
MR,
MR2

at-

00

4-112

t-

90
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

54174

PARAMETER

Min
hH

Input HIGH Current, CPo

1.0

0.2

mA

hH

Input HIGH Current CP1

1.0

0.4

mA

lee

Power Supply Current

42

15

mA

AC CHARACTERISTICS: Vee

= +5.0

V, TA

= +25°C (See

PARAMETER

CL
RL

= 15 pF
= 4000

Min

= Max,
Vee = Max,
Vee = Max

Vee

VIN
VIN

Max

54174LS
CL

= 15

Min

pF

UNITS

CONDITIONS

Max

f max

Maximum Count Frequency, CPo

32

32

MHz

Figs. 3-1, 3-9

f max

Maximum Count Frequency, CP1

16

16

MHz

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CPo to 00

16
18

16
18

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CPo to 03

48
50

48
50

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 01

16
21

16
21

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 02

32
35

32
35

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 03

32
35

32
35

ns

Figs. 3-1, 3-9

tPLH

Propagation Delay
MS to 00 and 03

30

30

ns

Figs. 3-1, 3-17

tPHL

Propagation Delay
MS to 01 and 03

40

40

ns

Figs. 3-1, 3-17

tPHL

Propagation Delay
MR to On

40

40

ns

Figs. 3-1, 3-17

AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0

V, TA

= +25°C

54174
Min

= 5.5 V
= 5.5 V

Section 3 for waveforms and load configurations)

54/74
SYMBOL

CONDITIONS

UNITS

Max

Max

54/74LS
Min

UNITS

CONDITIONS

Max

tw (H)

CPo Pulse Width HIGH

15

15

ns

Fig. 3-9

tw (H)

CP1 Pulse Width HIGH

30

30

ns

Fig. 3-9

tw (H)

MS Pulse Width HIGH

15

15

ns

Fig. 3-17

tw (H)

MR Pulse Width HIGH

15

15

ns

Fig. 3-17

tree

Recovery Time, MS to CP

25

25

ns

Fig. 3-17

tree

Recovery Time, MR to CP

25

25

ns

Fig. 3-17

4-113

•

91
CONNECTION DIAGRAMS
PINOUT A

54/7491A

SO

~

NclI

8-BIT SHIFT REGISTER

NCrr

~Q
~A

Ncii

fillB

Ncii

Vee

~GND

II

NC[I

t!Jcp

NC[I

fIlNC

PINOUT B

Ima

NC II
Ncii

~Q

NCrr

~A
~GND

VecG:

NC[I

~B

NC[I

~cp
~NC

NC[I

DESCRIPTION - The '91 is a serial-in, serial-out, 8-bit shift register. It is
composed of eight RS master/slave flip-flops, input gating and a clock driver.
The register is capable of storing and transferring data at clock rates up to
18 MHz while maintaining a typical noise immunity level of 1.0 V.

LOGIC SYMBOL
(Pinout A only)
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

"~

11 B

0

9

Plastic
DIP(P)

A

7491APC

Ceramic
DIP (D)

A

7491ADC

7491ADM

6A

B

7491AFC

7491AFM

31

Flatpak
(F)

CP

,

07

13

07

14

9A
Vee = Pin 5
GND= Pin 10

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
A, B
CP
Q7

Eh

DESCRIPTION
Serial Data Inputs
Clock Pulse Input (Active Rising Edge)
Data Output
Complementary Data Output

4-114

54174 (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
10/10
10/10

91
FUNCTIONAL DESCRIPTION - Single-rail data and input control are gated through inputs A and B and an internal inverter to form the complementary inputs to the first bit of the shift register. Drive for the internal common clock line is provided by an inverting clock driver. Each ofthe inputs(A, B, and CP) appear as only one TTL
input load. The clock pulse i nverter/driver causes these circu its to shift information to the output on the positive
edge of an input clock pulse, thus enabling the shift register to be fully compatible with other edge-triggered
synchronous functions.

LOGIC DIAGRAM
INPUTS

o

::=::(Jor-1

CP----t>.~~------~----~~----~------+-----~------~----~

TRUTH TABLE
INPUTS OUTPUT
tn

tn

+ 8

A

B

07

L
L
H
H

L
H
L
H

L
L
L
H

NOTES:
tn = Bit time before clock pulse.
In + 8 = Bit time after eight clock pulses.

H = HIGH Voltage Level
L = LOW Voltage Level

TYPICAL INPUT/OUTPUT WAVEFORMS

rLJ1
L
1

2 !!I_~IUU17
8 9 !!I_R
!JUU1JlJ115
16 17 18 19 !!!_'!!!nnJlJlJL23
24 2S 28 27

CLOCK-PULSE
INPUT

INPUT A

OUTPUTQ

L_____

____ ---1n L _______ ---1.---.L

4-115

91
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER
Min

Icc

Power Supply Current

I
I

UNITS

CONDITIONS

Max

XM
XC

50
58

mA

Vee

= Max'

"Icc is measured after the eighth clock pulse with the output open and A and B inputs grounded

AC CHARACTERISTICS: Vee

= +5.0 V,

TA

= +25°C (See Section 3 for waveforms and

load configurations)

54174
SYMBOL

PARAMETER

CL
RL

= 15 pF
= 400 n

Min
fmax

Maximum Shift Frequency

tPLH
tPHL

Propagation Eelay
CP to 07 or 07

SYMBOL

CONDITIONS

Max

10
40
40

AC OPERATING REQUIREMENTS: Vee +5.0 V, TA

UNITS

MHz

Figs. 3-1, 3-8

ns

Figs. 3-1, 3-8

= +25°C
54174

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH, D to CP

25

ns

Fig. 3-6

th (H)

Hold Time HIGH, D to CP

0

ns

Fig. 3-6

ts(U

Setup Time LOW, D to CP

25

ns

Fig. 3-6

0

ns

Fig. 3-6

25

ns

Fig. 3-8

lh(U

Hold Time La"", D to CP

tw

CP Pulse Width HIGH

(H)

4-116

92
CONNECTION DIAGRAM
PINOUT A

54/7492A
54LS/74LS92

cp,[I

DIVIDE-8Y-TWELVE COUNTER

NCIT

DESCRIPTION - The '92 is a 4-stage ripple counter containing a high
speed flip-flop acting as a divide-by-two and three flip-flops connected as
a divide-by-six. HIGH signals on the Master Reset (MR) inputs override the
clocks and force all outputs to the LOW state.

~cpo

~

TIlNC

NC[I

TIl 00

NCG

]]0,

Vee!}

~GND

MRd1

]]02

MR2(I

f!l 03

•

LOGIC SYMBOL

14....,-0 cPo
ORDERING CODE: See Section 9
PIN
PKGS

OUT

1....,-0 CP,
MR

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

~II
6 7

Plastic
DIP(P)

A

7492APC, 74LS92PC

Ceramic
DIP (D)

A

7492ADC, 74LS92DC

5492ADM, 54LS92DM

6A

Flatpak
(F)

A

7492AFC, 74LS92FC

5492AFM, 54LS92FM

31

9A

00 0, 0203

12 11

9

8

Vcc = Pin 5
GND = Pin 10
NC = Pins 2, 3, 4, 13

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

00

+2 Section Clock Input
(Active Falling Edge)
+6 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Input
(Active HIGH)
+2 Section Output-

Q1-03

+6 Section Outputs

CPo
CP1
MR1. MR2

"The 00 output is guaranteed to drive the full rated fan-out plus the

54174 (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

2.0/2.0

0.125/1.5

3.0/3.0

0.250/2.0

1.0/1.0

0.5/0.25

20/10

10/5.0
(2.5)
10/5.0
(2.5)

20/10

cp,

input.

4-117

92
FUNCTIONAL DESCRIPTION - The '92 is a 4-bit ripple type divide-by-twelve counter. Each device consists of
four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divideby-six
section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-toLOW clock transition. State changes of the outputs do not occur simultaneously because of internal ripple
delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or
strobes. The 00 output of each device is designed and specified to drive the rated fan-out plus the CP1 input of
the device. A gated AND asynchronous Master Reset (MR1, MR2) is provided which overrides the clocks and
resets (clears) all the flip-flops. Since tl;le output from the divide-by-two section is not internally connected to the
succeeding stages, the devices may be operated in various counting modes:

a

A. Modulo 12, Divide-By-Twelve Counter- The CP1 input must be externally connected to the 00 output.
The CPo input receives the incoming count and OJ produces a symmetrical divide-by-twelve square
wave output.
B. Divide-By-Two and Divide-By-Six Counter - No external interconnections are required. The first flipflop is used as a binary element for the divide-by-two function. The CP, input is used to obtain
divide-by-three operation at the 01 and 02 outputs and divide-by-six operation at the 03 output.
TRUTH TABLE

MODE SELECTION TABLE
RESET
INPUTS
MR1 MR2
H
L
H
L

H
H
L
L

00

01

02

L

L
L
Count
Count
Count

OUTPUT

COUNT

OUTPUTS
03
L

H = HIGH Voltage Level
L = LOW Voltage Level

00

01

02

03

0
1
2
3

L
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

4
5
6
7

L
H
L
H

L
L
L
L

H
H
L
L

L
L
H
H

8
9
10
11

L
H
L
H

H
H
L
L

L
L
H
H

H
H
H
H

NOTE: Output 00 connected to Cp,

LOGIC DIAGRAM

J

Q~

CPo ~ CP
K

LJ
.......(l

CD

-

CP
K

Q

J

Q

Q

CD

Y

Y

~

K Co Q

Y

cp,

-

f-c1--_-+--4R
Co

CD

CP

CL

4-124

CD

CD

aD

94
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER
Min

lee

Power Supply Current

UNITS

CONDITIONS

Max

~

50
58

XC

mA

Vee = Max

AC CHARACTERISTICS: Vee = 5.0 V, TA = 25°C (See Section 3 for waveforms and load configurations)
54/74

SYMBOL

PARAMETER

CL = 15 pF
RL = 400 n
Min

UNITS

CONDITIONS

Max

f max

Maximum Shift Frequency

tPLH
tPHL

Propagation Delay
CP to aD

tPLH

Propagation Delay, PLn to

35

tPHL

Propagation Delay,

40

10
40
40

aD
CL to aD

MHz

Figs. 3-1, 3-8

ns

Figs. 3-1, 3-8

ns

Figs. 3-1, 3-17

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54/74

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH, Ds to CP

35

ns

th (H)

Hold Time HIGH, Ds to CP

0

ns

ts (U

Setup Time LOW, Ds to CP

25

ns

th (U

Hold Time LOW, Ds to CP

0

ns

tw (H)

CP Pulse Width HIGH

35

ns

Fig. 3-8

tw (H)

CL Pulse Width HIGH

30

ns

Fig. 3-16

tw (H)

PL n Pulse Width HIGH

30

ns

Fig. 3-16

4-125

Fig. 3-6

Fig. 3-6

•

95
CONNECTION DIAGRAM
PINOUT A

54/7495A
54LS/74LS95B

OS

4-BIT RIGHT/LEFT SHIFT REGISTER

IT

~vcc

~

Poll

~ao

p,[!

~a,

p,8:

~a,

P3[I

~a3

PE IT:

~CP'

GNOIT

~CP'

DESCRIPTION - The '95 is a 4-bit shift register with serial and parallel synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input.
The data is transferred from the serial or parallel D inputs to the 0 outputs
synchronous with the H IGH-to-LOW transition of the appropriate clock input.
LOGIC SYMBOL
•
•
•
•

SYNCHRONOUS, EXPANDABLE SHIFT RIGHT
SYNCHRONOUS SHIFT LEFT CAPABILITY
SYNCHRONOUS PARALLEL LOAD
SEPARATE SHIFT AND LOAD CLOCK INPUTS

i I i 1j

PE Po

PIN
PKGS

OUT

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

A

7495APC, 74LS95BPC

Ceramic
DIP (D)

A

7495ADC, 74LS95BDC

Flatpak
(F)

p,

P3

8-0 cp,

COMMERCIAL GRADE

Plastic
DIP(P)

p,

9-0 cp,

ORDERING CODE: See Section 9
PKG

1-

OS

ao

a,

a,

a3

)3

1t

111

)0

Vcc

= Pin 14
= Pin 7

TYPE
9A

5495ADM, 54LS95BDM

6A

GND

A

7495AFC, 74LS95BFC

5495AFM, 54LS95BFM

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CP1
CP2
Ds
PO-P3
PE
00-03

DESCRIPTION
Serial Clock Input (Active Falling Edge)
Parallel Clock Input (Active Falling Edge)
Serial Data Input
Parallel Data Inputs
Parallel Enable Input (Active HIGH)
Parallel Outputs

4-126

54174 (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
2.0/2.0

0.5/0.25
0.5/0.25

20/10

0.5/0.25
0.5/0.25
1.0/0.5
10/5.0
(2.5)

95
FUNCTIONAL DESCRIPTION - The '95 is a 4-bit shift register with serial and parallel synchronous operating
modes. It has a Serial (Os) and four Parallel (Po - P3) Data inputs and four Parallel Data outputs (00 - 03). The
serial or parallel mode of operation is controlled by a Parallel Enable input (PE) and two Clock inputs, CP1 and
CP2. The serial (right-shift) or parallel data transfers occur synchronous with the HIGH-to-LOWtransition ofthe
selected clock input.
When PE is HIGH, CP2 is enabled. A HIGH-to-LOW transition on enabled CP2 transfers parallel data from the
Po - Pa inputs tothe 00 - 03 outputs. When PE is LOW, CP1 is enabled. AHIGH-to-LOWtransition on enabled
CP1 transfers the data from Serial input (Os) to 00 and shifts the data in 00 to 01, 01 to 02, and 02 to 03
respectively (right-shift). A left-shift is accomplished by externally connecting 03 to P2, 02 to P1, and 01 to Po,
and operating the '95 in the parallel mode (PE = HIGH), For normal operation, PE should only change states
when both Clock inputs are LOW. However, changing PEfrom LOWto HIGH while CP2 is HIGH, orchanging PE
from HIGH to LOW while CP1 is HIGH and CP2 is LOW will not cause any changes on the register outputs.
MODE SELECT TABLE
OPERATING
MODE

INPUTS
PE

CP1

CP2

Ds

Pn

00

01

02

03

Shift

L
L

L-

1-

X
X

I
h

X
X

L
H

qo
qo

q1
q1

q2
q2

Parallel Load

H

X

1.

X

pn

pO

P1

P2

P3

1..

L
L
H
H

L
L
L
L

X
X
X
X

X
X
X
X

No Change
No Change
No Change
Undetermined

L
L
H
H

H
H
H
H

X
X
X
X

X
X
X
X

Undetermined
No Change
Undetermined
No Change

Mode Change

S
1.
S
1..

r

L

S

•

OUTPUTS

I = LOW Voltage Level one set-up time prior to the HIGH-to-LOW clock transition.
h = HIGH Voltage Level one set-up time prior to the HIGH-to-LOW clock transition.
pn = Lower case letters indicate the state of the referenced input (or outputl one set-up
time prior to the HIGH-la-LOW clock Iransilion.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
p,

Po

P3

PE

DS--~---r----------,

cp, --II------ILJ

CP,

--------L.J

03

00

4-127

95
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min
Icc

Max

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

TA

PARAMETER

= 15 pF
= 400 n

CL
RL

fmax

Maximum Shift Frequency

tPLH
tPHL

Propagation Delay
CP1 or CP2 to an

Max

25

21

CONDITIONS

mA

Vee

= +5.0 V,

= 15 pF

Min

Min

UNITS

CONDITONS

27
27

MHz

Figs. 3-1, 3-9

ns

Figs. 3-1, 3-9

= +25°C

54174

PARAMETER

load configurations)

Max

30

TA

= Max

54174LS
CL

27
32

AC OPERATING REQUIREMENTS: Vee

UNITS

Max

= +25°C (See Section 3 for waveforms and

Min

SYMBOL

Min

63

54174
SYMBOL

54174LS

Max

54174LS
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time !:!!.GH or LOW
Ds or Pn to CPn

15
15

20
20

ns

Fig. 3-7

th (H)
th'(U

Hold Time HIGH or LOW
Ds or Pn to CPn

0
0

10
10

ns

Fig. 3-7

tw (H)

CPn Pulse Width HIGH

20

20

ns

Fig. 3-9

ten (U

Enable Time LOW
PE to CP1

15

25

ns

Fig. a

tinh (H)

Inhibit Time HIGH
PE to CP1

5.0

20

ns

Fig. a

ten (H)

Enable Time HIGH
PE to Ci5:2

15

25

ns

Fig. a

tinh (U

Inhibit Time LOW
PE to CP2

5.0

20

ns

Fig. a

PE)

--

V
;rvm

1\
1--t.,(LI-

cp,

t
_...J

/

\

f+---t'"h(HI_V--

j4-tmh(LI_

cp,

;rvm

\
~t,"(HI.

t
/

\

Vm

\
Fig. a
4-128

=

1.5 V (1.3 V FOR LSI

96
CONNECTION DIAGRAM
PINOUT A

54/7496
5-BIT SHIFT REGISTER
DESCRIPTION - The '96 consists of five RS master/slave flip-flops connected to perform parallel-to-serial or serial-to-parallel conversion of binary
data. Since both inputs and outputs to all flip-flops are accessible, parallelin/parallel-out or serial-in/serial-out operation may be performed.
All flip-flops are simultaneously set to the LOW state by applying a low level
voltage to the clear input. This condition may be applied independent of the
state of the clock input.

•

The flip-flops may be independently set to the HIGH state by applying a high
level voltage to both the preset input of the specific flip-flop and the common
parallel load input. The parallel enable input is provided to allow setting eagh
flip-flop independently or setting two or more flip-flops simultaneously. Preset is independent of the state of the clock input or clear input.
Transfer of information to the output pins occurs when the clock input goes
from a LOW level to a HIGH level. Since the flip-flops are RS master/slave circuits, the proper information must appear at the RS inputs of each flip-flop
prior to the rising edge of the clock input voltage waveform. The serial input
provides this information to the first flip-flop, while the. outputs of the subsequent flip-flops provide information for the remaining RS inputs. The clear
input must be at a HIGH level and the parallel load input must be at a LOW
level for serial shifting.

LOGIC SYMBOL

8

2

3

4

6

7

PL Po p, P2 P3 P4

9

ORDERING CODE: See Section 9

PKGS

COMMERCIAL GRADE
MILITARY GRADE
PIN r----------------r----------------,PKG
Vee = +5.0 V ±10%,
Vee = +5.0 V ±5%,
OUT
TA = -55°C to +1250C TYPE
TA = O°C to +70°C

Plastic
DIP(P)

A

7496PC

Ceramic
DIP (D)

A

7496DC

Flatpak
(F)

A

7496FC

Os

cp

16 15 14 13 11 10

98
5496DM

78

5496FM

4L

Vcc = Pin 5
GNO'" Pin 12

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CP
CL

Os
Po-P4
PL
00-Q4

DESCRIPTION
Clock Pulse Input (Active Rising Edge)
Asynchronous Clear Input (Active LOW)
Serial Data Input
Parallel Data Inputs
Asynchronous Parallel Load Input (Active HIGH)
Parallel Outputs

4-129

54/74 (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
5.0/5.0
10/10

96
MODE SELECT TABLE

INPUTS
PL

Pn

CL Os

L
H
H
L

X
H**
L **
X

L
H
H
H

OPERATION'
CP

X
X
X
X
X
X
H,L J

an
L
H
L

an

Clear; all outputs forced LOW
Selectively Preset; each output
set to its P input
-1 Shift right; Os---..Oo; 00----..01, etc.

'Simultaneous Preset and Clear operations produce undefined states.
"To insure proper presetting. P inputs must remain stable while PL is LOW.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
Po

P3

00
PL ------------------~~--~----~~--~----~~--~----~~--_r--__,

os

-----I'~>_

_

_dl~

s

o

CP

CP

CP

CP

o

R

R

CD

CD

CD

CD

cp ____-I'~----~----------~----------~----------~----------~

4-130

R

CD

96
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54/74

PARAMETER

SYMBOL

Min
lee

Power Supply Current

UNITS

CONDITIONS

Max

~

68

79

XC

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C (See Section 3 for waveforms and load configurations)

54174
SYMBOL

PARAMETER

CL = 15 pF
RL=400n
Min

f max

Maximum Shift Frequency

tPLH
tpHL

Propagation Delay
CP to an

tPLH

Propagation Delay,
PL or Pn to an

tPHL

cL to an

UNITS

CONDITIONS

Max

10

Propagation Delay,

MHz

Figs. 3-1, 3-8

40
40

ns

Figs. 3-1, 3-8

35

ns

Figs. 3-1, 3-"16

55

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54/54

PARAMETER
Min

UNITS

CONDITIONS

Max

tw (U

CP Pulse Width LOW

35

ns

Fig. 3-8

tw (U

CL Pulse Width LOW

30

ns

Fig. 3-16

tw (H)

PL Pulse Width HIGH

30

ns

Fig. 3-16

ts (H)

Setup Time HIGH, Ds to CP

30

ns

Fig. 3-6

th (H)

Hold Time HIGH, Ds to CP

0

ns

Fig. 3-6

ts (U

Setup Time LOW, Ds to CP

30

ns

Fig. 3-6

th (U

Hold Time LOW, Ds to CP

0

ns

Fig. 3-6

4-131

•

97
CONNECTION DIAGRAM
PINOUT A

54/7497
SYNCHRONOUS MODULO-64
BIT RATE MULTIPLIER
DESCRIPTION - The '97 contains a synchronous 6-stage binary counter
and six decoding gates that serve to gate the clock through to the output at
a sub-multiple of the input frequency. The output pulse rate, relative to the
clock frequency, is determined by signals applied to the Select (So - 55) inputs. Both true and complement outputs are available, along with an enable
input for each. A Count Enable input and a Terminal Count output are provided for cascading two or more packages. An asynctlronous Master Reset
input prevents counting and resets the counter.

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5:0 V ±10%,
TA = -55°C to +125°C

s,o::

-

:ill S3

S5!I

TIJS2

solI

ElM!!

oz[I

:g]Ev

ove!:
TeE!

~CE
~EZ

GNO[!

~CP

PKG
TYPE

Plastic
DIP(P)

A

7497PC

Ceramic
DIP (0)

A

7497DC

5497DM

7B

Flatpak
(F)

A

7497FC

5497FM

4L

9B

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

SO-55

Ez

Ey
CE
CP
MR

Oz
Oy
TC

54/74 (U.L.)

DESCRIPTION

PIN NAMES

HIGH/LOW

Rate Select Inputs
5z Enable Input (Active LOW)
Oy Enable Input
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Gated Clock Output (Active LOW)
Complement Output (Active HIGH)
Terminal Count Output (Active LOW>

1.0/1.0
1.011.0
1.0/1.0
1.0/1.0
2.0/2.0
1.0/1.0
10/10
10/10
10/10

LOGIC SYMBOL

i 1YYi i
11 -----4-+---r--~+---~~-+---r--~+---t-~~-+-r--~

Ez

Oz

4-134

97
MODE AND RATE SELECT TABLE (Note 1)

OUTPUTS

INPUTS

Oy

OZ

TC

X
64
64

H
H
H

L
L

H
H

H

1

1

L
L
L
L

64
64
64
64

H
H
H
H

2
4

2
4

8

8

16

L
H
H
L

64
64
64
64

H
H
L
H

32
63

S3

S2

S1

So

X

X

X

X

X

X

L
L

L
L

L
L

L
L

L
L

L
H

L
L
L
L

L
L
L
L

L
L
L
H

L
L
H
L

L
H
L
L

H
L
L
L

L
L
L
L

H
H
H
H

L
H
H
L

L
H
H
H

L
H
H
L

L
H
H
L

S5

H
L
L

X
L
L

H
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

NOTES

Ey

54

MR CE Ez

CLOCK
PULSES

H

40

1
1

2
3
3

16

1
1
1
1

3
3
3
3

32
63
63
40

1
1
1
1

3
3
4
5

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
NOTES:
1. Numerals indicate number of pulses per cycle.
_
_
2. This is a simplified illustration of the clear function. CP and Ez also affect the logic level of Oy and Oz. A LOW
signal on Ev will cause Ov to remain HIGH.
3. Each rate illustrated assumes 80- S5 are constant throughout the cycle; however, these illustrations in no way
prohibit variable-rate operation.
4. Ey is used to inhibit output y.
5. fout = m • !in = (32 + 8) fin = 40 fin = 0.625 fin
64
64
64

PULSE PATTERN TABLE

m

1
2
3
4
5

OUTPUT PULSE PATTERN AT Oz

1111111111111111111111111111111011111111111111111111111111111111
1111111111111110111111111111111111111111111111101111111111111111
1111111111111110111111111111111011111111111111101111111111111111
1111111011111111111111101111111111111110111111111111111011111111
1111111011111111111111101111111011111110111111111111111011111111

6 1111111011111110111111101111111111111110111111101111111vl1111111
8 1110111111101111111011111110111111101111111011111110111111101111
10 1110111111101110111011111110111111101111111011101110111111101111
12 1110111011101111111011101110111111101110111011111110111011101111
14 1110111011101110111011101110111111101110111011101110111011101111
16
20
24
28
32

1011101110111011101110111011101110111011101110111011101110111011
1011101010111011101110101011101110111010101110111011101110111011
1010101110101011101010111010101110101011101010111010101110101011
1010101010101011101010101010101110101010101010111010101010101011
010101 ....
.... 0101

4-135

97
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54/74

PARAMETER

SYMBOL

los

Output Short Circuit Current

lee

Power Supply Current

UNITS

CONDITIONS

Min

Max

-18

-55

mA

Vcc = Max

120

mA

Vee = Max
All Inputs = 4.5 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

54/74
PARAMETER

SYMBOL

CL = 15 pF
RL=400n
Min

UNITS

CONDITIONS

Max

25

f max

Maximum Clock Frequency

MHz

Figs. 3-1, 3-8

tPLH
tPHL

Propagation Delay
Ez to Oz

18
23

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay

Ez to Oy

30
33

ns

tpLH
tPHL

Propagation Delay
Ey to Oy

14
10

ns

tPLH
tPHL

Propagation Delay
Sn to Oy

23
23

ns

tPLH
tPHL

Propagation Delay
Sn to Oz

14
14

ns

tPLH
tPHL

Propagation Delay
CP to Oy

39
30

ns

tPLH
tPHL

Propagation Delay
CP to Oz

18
26

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
CP to TC

30
33

ns

Figs. 3-1, 3-8

tPLH
tPHL

Propagation Delay
CE to TC

20
21

ns

Figs. 3-1, 3-5

tpLH

Propagation Delay
MR to Oy

36

ns

tPHL

Propagation Delay
MR to Oz

23

Figs. 3-1, 3-4

Figs. 3-1, 3-5

Figs. 3-1, 3-4

Figs. 3-1, 3-16

4-136

ns

97
AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

= +25°C

TA

54/74

PARAMETER

Min

UNITS

CONDITIONS

Max

ts(U

Setup Time LOW
~ to CP Rising

25

th (U

Hold Time LOW
~ to CP Rising

0

tw CP -10

ns

ts (U

Setup Time LOW
CE to CP Falling

0

tw CP -10

ns

th (U

Hold Time LOW
CE to CP Falling

20

tinh (H)

Inhibit Time HIGH
CE to CP Falling

10

ns

Fig. b

toN (H)

CP Pulse Width HIGH

20

ns

Fig. 3-8

tw (H)

MR Pulse Width HIGH

15

ns

Fig. 3-16

C!

ns
Fig. b

Fig.

,

_

T -10

ENABLED--....,

,

ns

~DISABLED----......

I
Vm

I

.. ,

, . - - DISABLED--...,...---- ENABLED

.....

~

....

I,(L) ....

I--

~

CP

..l..",,

J
i+-- IwCP -

LJ

!+-linn(H)

\

Vm

= I.SV

J

Fig. b

,

,.,,,) -l<-

I

f,,,

\

--1
~lwCP

T

Fig. c

4-137

C

,

Vm

= I.SV

~

101
CONNECTION DIAGRAMS
PINOUT A

54H/74H101
JK EDGE-TRIGGERED FLIP-FLOP
(with AND-OR Inputs)
DESCRIPTION - The '101 is a high speed JK negative edge-triggered flipflop. The AND-OR gate inputs are inhibited while the clock input is LOW.
When the clock goes HIGH, the inputs are enabled and data will be accepted.
The logic state of J and K inputs may be allowed to change when the clock
pulse is in a HIGH state and the bistable will perform according to the Truth
Table as long as minimum setup times are observed. Input data is transferred
to the outputs on the falling edge of the clock pulse.
TRUTH TABLE
INPUTS OUTPUT
@tn

Asynchronous Input:
LOW input-to So sets a to HIGH level
Set is independent of clock

@ tn + 1

J

K

a

L
L
H
H

L
H
L
H

an
L
H
On

PINOUT B

J = (J1A • J1B) + (J2A • J2B)
K = (K1A • K1B) + (K2A • K2B)
tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.
H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC SYMBOL
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +1250C

PKG
TYPE

Plastic
DIP(P)

A

74H101PC

Ceramic
DIP (0)

A

74H101DC

54H101DM

6A

B

74H101FC

54H101FM

31

Flatpak
(F)

9A

Vcc

= Pin 14

GND

= Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
J1A, J1B, J2A, J2B}
K1A, K1B, K2A, K2B
CP

So
a,Q

54174H (U.L.)
HIGH/LOW

Data Inputs

1.25/1.25

Clock Pulse Input (Active Falling Edge)
Direct Set Input (Active LOW>
Outputs

0*/3.0
2.5/1.25
12.5/12.5

'CP Sourcing Current, see DC Characteristics Table
4-138

101
LOGIC DIAGRAM

-

-•

.r

Q

\..

L

-I

SO

K1A~

K1Bo-I""

K2Bo--f'"""""""";

Q

......

-»--k: ~~~'.

=3-

K2A~

"-

_

-

iL-oJ1B

-E~J2A

~

~J2B

_

CP

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
54174H

PARAMETER

SYMBOL

hH

Input HIGH Current at CP

Icc

Power Supply Current

AC CHARACTERISTICS: Vcc

= +5.0 V.

TA

UNITS

Min

Max

0

-1.0

mA

38

mA

CONDITIONS

= Max. Vcp = 2.4 V
Vcc = Max. Vcp = 0 V

Vcc

= +25°C (See Section 3 for waveforms and load configurations)
54/74H

SYMBOL

CL = 25 pF
RL = 280 n

PARAMETER

Min

UNITS

CONDITIONS

Max

fmax

Maximum Clock Frequency

MHz

Figs. 3-1. 3-9

tPLH
tPHL

Propagation Delay
CP to
or Q

15
20

ns

Figs. 3-1. 3-9

tPLH
tPHL

Propagation Delay
So to
or Q

12
20

ns

Vcp;?: 2.0 V
Figs. 3-1. 3-10

tPLH
tPHL

Propagation Delay
So to
or Q

12
35

ns

Vcp:5 0.8 V
Figs. 3-1. 3-10

a

a
a

AC OPERATING REQUIREMENTS: Vcc
SYMBOL

40

= +5.0 V.

TA

= +25°C
54174H

PARAMETER

Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time
I n or Kn to CP

10
13

ns

th (H)
th (U

Hold Time
I n or Kn to CP

0
0

ns

CP Pulse Width

10
15

ns

Fig. 3-9

So Pulse Width LOW

16

ns

Fig. 3-10

tw (H)

tw(U
tw (U

4-139

Fig. 3-7

102
CONNECTION DIAGRAMS
PINOUT A

54H/74H102
JK EDGE-TRIGGERED FLIP-FLOP
(With AND Inputs)
DESCRIPTION - The '102 is a high speed JK negative edge-triggered flipflop. It features gated J K inputs and an asynchronous Clear input. The AND
gate inputs are inhibited while the clock input is LOW. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic state of J
and K inputs may be allowed to change when the clock pulse is in a HIGH
state and the bistable will perform according to the Truth Table as long as
minimum setup times are observed. Input data is transferred to the outputs on
the falling edge of the clock pulse.
Asynchronous Inputs:
LOW input to So sets to HIGH level
LOW input to CD sets to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So
makes both
and El HIGH
J '= (J1A • J1e) + (hA • he)

TRUTH TABLE

a
a

INPUTS OUTPUT
@tn

@ tn

J

K

a

L
L
H
H

L
H
L
H

On
L
H
an

PINOUT B

+1

a

K = (K1A • K1e) + (K2A • K2e)
tn = Bit time before clock pulse.
tn + 1 = Bit time alter clock pulse.
H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC SYMBOL
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL
GRADE
MILITARY GRADE
______________
-+______________

~

~

Vee = +5.0 V ±5%,

TA

= O°C to +70°C

Plastic
DIP(P)

A

74H102PC

Ceramic
DIP(D)

A

74H102DC

Flatpa~

(F)

B

Vee

74H102FC

TA

= +5.0 V ±10%

= -55°C to +1250C

PKG
TYPE
9A

54H102DM
54H102FM

Vee = Pin 14 (4)
GNO = Pin 7 (11)

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

J" J2, J3 }
Kl, K2, K3
CP

CD

So

o,a

DESCRIPTION
Data Inputs

54174H
HIGH/LOW
1.25/1.25

Clock Pulse Input (Active Falling Edge)
Direct Clear Input (Active LOW)
Dir.ect Set Input (Active LOW)
Outputs

.cp Sourcing Current, see DC Characteristics Table
4-140

0*/3.0
2.5/1~25

2.5/1.25
12.5/12.5

102
LOGIC DIAGRAM

§o

K1
K2
K3

... J"'
I-

Q

I

-'4

I

I ......
-

-

-

.r

.A

Q

1

Co

~

J1-

I

-14

;.--a #- -

~

~

.r

- , - - i-----a

.J

I~

'l

J2
J3

CP

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74H

PARAMETER

hH

Input HIGH Current at CP

lee

Power Supply Current

UNITS

CONDITIONS

-1.0

mA

Vce = Max, Vcp = 2.4 V

38

mA

Vce = Max, Vep= 0 V

Min

Max

0

AC CHARACTERISTICS: Vce = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74H

SYMBOL

PARAMETER

CL = 25 pF
RL=280n
Min

fmax

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to Q or Q

tPLH
tPHL
tPLH
tPHL

UNITS

CONDITIONS

Max

40

MHz

Figs. 3-1, 3-9

15
20

ns

Figs. 3-1, 3-9

Propagation Delay
Co or So to Q or Q

12
20

ns

Vcp;::: 2.0 V
Figs. 3-1, 3-10

Propagation Delay
CD or So to Q or Q

12
35

ns

Vcp :50.8 V
Figs. 3-1, 3-10

AC OPERATING REQUIREMENTS: Vcc = +5.0 V, TA = +25°C
SYMBOL

54/74H

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

In or Kn to CP

10
13

ns

tt'(H)
th(U

Hold Time
In or Kn to CP

0
0

ns

tw (H)
tw (U

CP Pulse Width

10
15

ns

Fig. 3-9

tw (U

CD or So Pulse Width LOW

16

ns

Fig. 3-10

Setup Time

4-141

Fig. 3-7

•

103
CONNECTION DIAGRAM
PINOUT A

54H/74H103
DUAL JK EDGE-TRIGGERED FLIP-FLOP
(With Separate Clears and Clocks)

~Pt

Cl'1IT
~011I

DESCRIPTION - The '103 is a high speed JK negative edge-triggered fHpflop. It features individual J, K, clock and asynchronous clear inputs to each
flip-flop. When the clock goes HIGH, the inputs are enabled and data will be
accepted. The logic state of J and K inputs may be allowed to change when
the clock pulse is in a HIGH state and the bistable will perform according to
the Truth Table as long as minimum setup times are observed. Input data is
transferred to the outputs on the falling edge of the clock pulse.

INPUTS OUTPUT
@tn

J

K

0

L
L
H
H

L
H
L
H

On
L
H
an

+

-

IT

-----.J

JdI

1

tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.
H = HIGH Voltage Level
L = LOW Voltage Level

L-

-

o~

J

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA =O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

L

J

~

1!!. K

PKG
TYPE

A

74H103PC

Ceramic
DIP (0)

A

74H103DC

54H103DM

6A

Flatpak
(F)

A

74H103FC

54H103FM

31

Or-9

~ CP

3- K Co 0

Plastic
DIP(P)

CD

I

2

9A
Vcc = Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
J1, .12, K1, K2
CP1, CP:!
Co1, CD2
01,02, Q1, Q2

~a2

LOGIC SYMBOL

1-0 CP

OUT

~GND

~~o- L~K2

CP2!I

ORDERING CODE: See Section 9

PKGS

~a1

e02!I rJcoa-1-- ~a2

14-

PIN

~a1

Asynchronous Input:
LOW input to CD sets 0 to LOW level
Clear is independent of clock

TRUTH TABLE

@tn

K1IT
Vee

~J1

Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW>
Outputs

'CP Sourcing Current. see DC Characteristics Table

4-142

54/74H (U.L.)
HIGH/LOW
1.25/1.25
0*/3.0
2.5/1.25
12.5/12.5

Op....8

103
LOGIC DIAGRAM (one half shown)

Ii

Q

-"-'~

K

-

r=:3

I

"'

......

1

-

~

I~
-

~

"'--

..J

[

1

~

CO

-.

r

.r

I

\..

I
I

,.. J

~
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174H

PARAMETER

hH

Input HIGH Current at CP

Icc

Power Supply Current

AC CHARACTERISTICS: Vcc

= +5.0 V,

TA

CONDITIONS

UNITS

Min

Max

0

-1.0

mA

Vcc

76

mA

Vcc

= +25°C (See Section 3 for waveforms and

= Max,
= Max,

Vcp
Vcp

= 2.4 V
=0 V

load configurations)

54174H
SYMBOL

PARAMETER

CL
RL

= 25 pF
= 280 n

Min
f max

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CPn to an or an

tPLH
tPHL
tPLH
tPHL

CONDITIONS

Max
MHz

Figs. 3-1, 3-9

15
20

ns

Figs. 3-1, 3-9

Propagation Delay
COn to an or an

12
20

ns

Vcp ~ 2.0 V
Figs. 3-1, 3-10

Propagation Delay
COn to an or an

12
35

ns

Vcp:5 0.8 V
Figs. 3-1, 3-10

AC OPERATING REQUIREMENTS: VCC
SYMBOL

UNITS

40

= +5.0 V,

= +25°C

TA

54174H

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time
In or Kn to CPn

10
13

ns

th (H)
th (U

Hold Time
In or Kn to CPn

0
0

ns

tw (H)
tw (U

CPn Pulse Width

10
15

ns

Fig. 3-9

tw (U

COn Pulse Width LOW

16

ns

Fig. 3-10

4-143

Fig. 3-7

106
CONNECTION DIAGRAM
PINOUT A

54H/74H106

cp,IT

DUAL JK EDGE-TRIGGERED FLIP-FLOP
(With Separate Sets, Clear and Clocks)
DESCRIPTION - The '106 is a high speed JK negative edge-triggered flipflop. It features individual J, K, clock and asynchronous set and clear inputs
to each flip-flop. When the clock goes HIGH, the inputs are enabled and data
will be accepted. The logic state of J and K inputs may be allowed to change
when the clock pulse is in a HIGH state and the bistable will perform according to the Truth Table as long as minimum setup times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.

INPUTS OUTPUl
@tn

@tn + 1

J

K

0

L
L
H
H

L
H
L

On
L
H
an

H

so,l!
Co, I!

CP
[.,K QoQP-- ~Q,

J'/1

~Q'

2lJGND

-----I

,.-----,

TIJ K2
CP21I hIL~Jt
TI]Q2
f-c CP
vcc[[

502 II -!fJ co Q
C02[!

~Q2

T.-- ~J2

Asynchronous Inp~ts:
LOW input to So sets 0 to HIGH level
LOW input to Co sets 0 to LOW level
Clear and Set are independent of clock
Simultaneous LOW on Co and SO
makes both 0 and a HIGH
In = Bit time before clock pulse.
tn + , = Bit time after clock pulse.
H = HIGH Voltage Level
L = LOW Voltage Level

TRUTH TABLE

-

~K'
-~~
;J COQr--_

LOGIC SYMBOL

7

2

4- J So Q t"-15 !.. J So Q t"-11

PIN
PKGS

OUT

COMMERCIAL GRADE

= +5.0 V ±5%,
= O°C to +70°C

Vee

TA

8-<1 CP

1-< CP

ORDERING CODE: See Section 9
MILITARY GRADE

= +5.0 V ±10%,
= -55°C to +125°C

Vee

TA

PKG
TYPE

Plastic
DIP(P)

A

74H106PC

Ceramic
DIP (D)

A

74H106DC

54H106DM

68

Flatpak
(F)

A

74H106FC

54H106FM

4L

18- K CD Q ~14 :!! K CD Q ~10

T

3

98
Vcc = Pin 5
GND = Pin 13

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
J1, J2, Kl, K2
CP1, CP2
COl, CO2
501,502
01,02, 01, Q2

DESCRIPTION
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs

.cp Sourcing Current, see OC Characteristics Table

4-144

54174H (U.L.)
HIGH/LOW
1.25/1.25
0*/3.0
2.5/1.25
2.5/1.25
12.5/12.5

106
LOGIC DIAGRAM (one half shown)
Q

Q

.r

,.

r=:3-

E:::-

-\.

-I

......

I

1
~~

~ ~

So

K

I

FI~I
-

~

- "
I
I

CD

1

.r

-

-\.

I
1

J

•

l
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
hH
Icc

54/74H

PARAMETER
Input HIGH Current at CPn

Max

0

-1.0

mA

Vcc

76

mA

Vcc

Power Supply Current

AC CHARACTERISTICS: Vcc

= +5.0 V,

TA

CONDITIONS

UNITS

Min

= +25°C (S~e Section

= Max,
= Max,

Vcp
Vcp

= 2.4 V
=0 V

3 for waveforms and load configurations)

54/74H
SYMBOL

CL = 25 pF
RL = 280 n

PARAMETER

Min
f max

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CPn to an or On

tPLH
tPHL
tPLH
tPHL

CONDITIONS

Max
MHz

Figs. 3-1, 3-9

15
20

n~

Figs. 3-1, 3-9

Propagation Delay
COn or SOn to an or an

12
20

ns

Vcp ~ 2.0V
Figs. 3-1, 3-10

~ropag~tion Delay
COn or SOn to an or an

12
35

ns

Vcp:5 0.8 V
Figs. 3-1, 3-10

·AC OPERATING REQUIREMENTS: Vcc

SYMBOL

UNITS

40

= +5.0 V,

TA

= +25°C
54174H

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts (U

Setup Time
In or Kn to CPn

10
13

ns

th (H)
th (U

Hold Time
In or Kn to CPn

0
0

ns

tw (H)
tw (U

CPn Pulse Width

10
15

ns

Fig. 3-9

tw (U

COn or SOn Pulse Width LOW

16

ns

Fig. 3-10

4-145

Fig. 3-7

107
CONNECTION DIAGRAM
PINOUT A

54/74107
54LS/74LS107
DUAL JK FLIP-FLOP
(With Separate Clears and Clocks)
DESCRIPTION - The '107 dual JK master/slave flip-flops have a separate
clock for each flip-flop. Inputs to the master section are controlled by the
clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from J and
K inputs to master; 3) disable J and K inputs; 4) transfer information from
master to slave.

TRUTH TABLE

CLOCK WAVEFORM

INPUTS OUTPUT
@tn

HIGH

@ tn + 1

J

K

0

L
L
H
H

L
H
L
H

On
L
H
an

LOW

LOGIC SYMBOL

H = HIGH Voltage Level
L = LOW Voltage Level
In = Billime before clock pulse.
In + 1 = Billime afler clock pulse.

Asynchronous Input:
LOW input to Co sets 0 to LOW level
Clear is independent of clock

The 'LS107 offers individual J, K, clear, and clock inputs. These dual flip-flops
are designed so that when the clock goes HIGH, the inputs are enabled and
data will be accepted. The logic level of the J and K inputs may be allowed to
change when the clock is HIGH and the bistable will perform according tothe
Truth Table as long as minimum setup times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

Q

J

3

8

J

Q

5

4

ORDERING CODE: See Section 9
PIN
PKGS

OUT

13

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +125°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74107PC, 74LS107PC

Ceramic
DIP -3

K

Ceramic
DIP(D)

A

74H108DC

54H108DM

SA

Flatpak
(F)

A

74H108FC

54H108FM

31

= Pin 14
= Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES

CD
S01, S02
01, 02, 01, 02

Data Inputs
Clock Pulse Input (Active Falling Edge)
Direct Clear Input (Active LOW)
Direct Set Inputs (Active LOW)
Outputs

'CP Sourcing Current. see DC Characteristics Table
4-149

CD

y

Y

Vec

54/74H (U.L.)
HIGH/LOW
1.25/1.25
O*/S.O
5.0/2.5
2.5/1.25
12.5/12.5

Q

-6

CP

!...

TYPE
9A

74H108PC

---0

1- K Co
PKG

1!J So

GND

J1, J2, K1,K2
CP

:N)S02

a

ORDERING CODE: See Section 9

PKGS

-

oCo K
cpp
Loso Jr-

LOGIC SYMBOL

4-

PIN

t

~~

a
a

INPUTS OUTPUT
@tn

1

odl

Asynchronous Inputs:
LOW input to So sets to HIGH level
LOW input to CD sets to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So
makes both
and Q HIGH

TRUTH TABLE

EJvcc

a,II --.... -£OSo Jr- LTIl SOl
cp
arC! ~OCoK
liI co
Jll1 -, ---v:rrI J2

Q 1>-5

•

108
LOGIC DIAGRAM (one half shown)
~----------------------~~-oQ

Qo-~------------------------,

TO OTHER

,FLIP-FLOP
SoO-4-~~~~--+---~---------+---+---------,
.---------___1~--~------___11_+--_+_--_<

1-+-+---0 CD

Ko---~

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE .(unless otherwise specified)
SYMBOL

54/74H

PARAMETER

IIH

Input HIGH Current at CP

Icc

Power Supply Current

AC CHARACTERISTICS: Vcc

= +5.0 V,

TA

UNITS

CONDITIONS

-1.0

mA

Vcc = Max, Vcp = 2.4 V

76

mA

Vcc = Max, Vcp = 0 V

Min

Max

0

= +25°C (See Section 3 for waveforms and

load configurations)

54174H
SYMBOL

CL = 25 pF
RL = 280 n

PARAMETER

Min

UNITS

CONDITIONS

Max

f max

Maximum Clock Frequency

MHz

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP to an or On

15
20

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
Co or Son to an or On

12
20

ns

Vcp = ~ 2.0 V
Figs. 3-1,3-10

tPLH
tPHL

Propagation Delay
CD or SOn to an or an

12
35

ns

Vcp =:5 0.8 V
Figs. 3-1, 3-10

AC OPERATING REQUIREMENTS: Vcc
SYMBOL

40

= +5.0 V, TA = +25°C
54/74H

PARAMETER
Min

ts (H)

UNITS

CONDITIONS

Max

ts(L)

Setup Time
I n or Kn to CP

10
13

ns

th (H)
th (L)

Hold Time
I n or Kn to CP

0
0

ns

tw (H)
tw (L)

CP Pulse Width

10
15

ns

Fig. 3-9

tw

Co or SOn Pulse Width LOW

16

ns

Fig. 3-10

(L)

4-150

Fig. 3-7

109
CONNECTION DIAGRAM
PINOUT A

548/748109
54L8/74L8109
CO,

DESCRIPTION - The '109 consists of two high speed, completely independent transition clocked J Kflip-flops. The clocki~g operation is independent
of rise and fall times ofthe clock waveform. The JK design allows operation as
a D flip-flop (refer to '74 data sheet! by connecting theJ and K inputs together.
The '109 is functionally equivalent to the 9024.

TRUTH TABLE
INPUTS

OUTPUTS

@ tn

@ tn + 1

J

K

L
L
H
H

H
L
H
L

0

0

No Change
L
H
H L
Toggles

~vcc

[I

~rJ, IT - J ,
coo- ~C02

DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP

Kp-

So, [] --< So,

CP r--

0,

[! -

J

GNOI!

1

r!

4- CP

PIN
PKGS

OUT

3-< K CD 0

COMMERCIAL GRADE

MILITARY GRADE

= +5.0 V ±5%,
TA = O°C to +70°C
Vee

Vee

TA

PKG

= +5.0 V ±10%,

= -55°C to +125°C

A

Ceramic
DI.pm)

A

74S109DC, 74LS109DC

54S109DM, 54LS109DM

SA

A

74S109FC, 74LS109FC

54S109FM,54LS109FM

31

Flatpak
(F)

74S109PC, 74LS109PC

~CP2
~02

L

PJ

9A

~

J

!!

CP

~

K

So 0

CD

1~

T,
Vcc

= Pin 16
= Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

Jl, J2, Kl, K2
CP1, CP2
COl, CO2
SOl, S02
01,02, ell. Q2

DESCRIPTION

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs

1.25/1.25
2.5/2.5
5.0/5.0
2.5/2.5
25/12.5

0.5/0.25
1.0/0.5
1.0/1.0
1.0/0.5
10/5.0
(2.5)

4-151

r- 1O

0 ~9

GND

PIN NAMES

Q2

~

!!

TYPE

Plastic
DIP(P)

K2

LOGIC SYMBOL

2- J So 0

ORDERING CODE: See Section 9

rm

So p- ~S02

0,

<:i,1! --<~

Asynchronous Inputs:
LOW input to So sets 0 to HIGH level
LOW input to Co sets 0 to LOW level
Clear and Set are independent of clock
Simultaneous LOW on Co and So
makes both 0 and Q HIGH
tn = Bit time before clock pulse.
tn + , = Bit time after clock pulse.
H = HIGH Voltage Level
L = LOW Voltage Level

r-- ~J2

Rd1: --< K,
cp,~ - cp,

109
LOGIC DIAGRAM (one half shown)
So----------+-~~

Co ----_-+----1
CP

------1-+....

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74S

PARAMETER

Min
Icc

Max

Power Supply Current

AC CHARACTERISTICS: Vec

= +5.0 V,

TA

PARAMETER

CL
RL

= 15 pF
= 280 0

Min

Max

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CPn to an or an

9.0
11

tPLH
tPHL

Propagation Delay
COn or SOn to an or an

tPLH
tPHL

Propagation Delay
COn or SOn to an or an

75

8.0

CONDITIONS

mA

Vcc

Vcp

=0 V

load configurations)

= 15 pF

CL

Min

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-8

25
35

ns

Figs. 3-1, 3-8

6.0
12

15
35

ns

Vcp ~ 2.0 V
Figs. 3-1, 3-10

6.0
12

15
24

ns

Vcp:5 0.8 V
Figs. 3-1, 3-10

= +25°C

54/74S
Min

= Max,

54174LS

30

AC OPERATING REQUIREMENTS: Vcc "" +5.0 V, TA
PARAMETER

UNITS

Max

= +25°C (See Section 3 for waveforms and

fmax

SYMBOL

Min

52

54/74S
SYMBOL

54174LS

Max

54/74LS
Min

UNITS

CONDITIONS

Max

ts (H)
ts (U

. Setup Time
In or Kn to CPn

6.0
6.0

18
18

ns

th (H)
th (U

Hold Time
In or Kn to CPn

0
0

0
0

ns

tw (H)
tw (U

CPn Pulse Width

7.0
6.5

20
13.5

ns

Fig. 3-8

tw (U

COn or SOn Pulse Width LOW

6.0

15

ns

Fig. 3-10

4-152

Fig.3-6

112
CONNECTION DIAGRAM
PINOUT A

545/745112
54L5/74L5112
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
DESCRIPTION - The '112 features individual J, K, Clock and asynchronous
Set and Clear inputs to each flipcflop. When the clock goes HIGH, the inputs
are enabled and data will be accepted. The logic level of the J and K inputs
may change when the clock is HIGH and the bistable will perform according
to the Truth Table as long as minimum setup and hold times are observed.
Input data is transferred to the outputs on the falling edge of the clock pulse.

TRUTH TABLE
INPUTS OUTPUT
@ tn

@ tn

J

K

a

L
L
H
H

L
H
L
H

an
L
H
an

+

1

•

Asynchronous Inputs:
LOW input to So sets a to HIGH level
LOW input to Co sets a to LOW level
Clear and Set are independent of clock
Simultaneous LOW on Co and So
makes both a and Q HIGH

LOGIC SYMBOL

tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.
H = HIGH Voltage Level
L = LOW Voltage Level

10

4

3

SD

5

Q

11 J

SD Q

9

ORDERING CODE: See Section 9
PIN
PKGS

OUT

Plastic
DIP(P)

A

2

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

7

PKG

74S112PC, 74LS112PC

TYPE
98

14

15

Vcc

=

Pin 16

GND = Pin 8

Ceramic
DIP (0)

A

74S112DC, 74LS112DC

54S112DM,54LS112DM

68

Flatpak
(F)

A

74S112FC, 74LS112FC

54S112FM,54LS112FM

4L

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

h J2, Kl, K2
CP1, CP2
COl, CO2
501,502
01, 02, 01, 02

DESCRIPTION

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs

1.25/1.0
2.5/2.5
2.5/4.375
2.5/4.375
25/12.5

0.5/0.25
2.0/0.5
1.5/0.5
1.5/0.5
10/5.0
(2.5)

4-153

112
LOGIC DIAGRAM (one half shown)

Q

0--+--0<

_----0 So

coo----~

1-------oK

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54174S
Min

Icc

Power Supply Current

Max

54174LS
Min

B.O

50

UNITS

CONDITIONS

Max
mA

Vee = Max, Vep = 0 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174S
SYMBOL

PARAMETER

54174LS

CL = 15 pF CL = 15 pF
RL = 2BO n
Min

Max

BO

f max

Maximum Clock Frequency

tPLH
tpHL

Propagation Delay
CPn to an or an

7.0
7.0

tPLH
tpHL

Propagation Delay
COn or SOn to an or an

7.0
7.0

Min

UNITS

CONDITIONS

Max

30

MHz

Figs. 3-1, 3-9

16
24

ns

Figs. 3-1, 3-9

16
24

ns

Figs. 3-1, 3-10

ACOPERATING REQUIREMENTS: Vee = +5.0 V, TA =+25°C
SYMBOL

PARAMETER

54/74S
Min

ts (H)

Max

54/74LS
Min

UNITS

CONDITIONS

Max

ts(U

Setup Time
In or Kn to CPn

7.0
7.0

20
15

ns

th (H)
th (U

Hold Time
I n or Kn to CPn

0
0

0
0

ns

tw (H)
tw (U

CPn Pulse Width

6.0
6.5

20
15

ns

Fig. 3-9

tw (U

COn or SOn Pulse Width LOW

B.O

15

ns

Fig. 3-10

4-154

Fig. 3-7

113
CONNECTION DIAGRAM
PINOUT A

548/748113
54L8/74L8113

cp,u

DUAL JK EDGE-TRIGGERED FLIP-FLOP

K,[l
J,[1

DESCRIPTION - The '113 offers individual J, K, Set and Clock inputs. When
the clock goes HIGH the inputs are enabled and data may be entered.
The logic level of the J and K inputs may be changed when the clock
pulse is HIGH and the bistable will perform according to the Truth Table
as long as minimum setup and hold times are observed. Input data is
transferred to the outputs on the falling edge of the clock pulse.
TRUTH TABLE
INPUTS OUTPUT
@tn

@ tn

J

K

a

L
L
H
H

L
H
L
H

an
L
H
On

+

1

Q'E!
GNOIT

PKGS

OUT

~K2

rm

tn = Bit time before clock pulse.
tn + , = Bit time after clock pulse.
H = HIGH Voltage Level
L = LOW Voltage Level

1tl ~

~

~Q2

~a2

LOGIC SYMBOL

'0'

10

4

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

1

CP

2

K

11,CP" Q H
13--

-....J==:;-

-

Q

'-~

P-

J

~Q

k=*

110
K

c'f;
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54174S
Min

lee

Power Supply Current

Max

54174LS
Min

8.0

50

UNITS

CONDITIONS

Max
mA

Vee = Max, Vep = 0 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

54174S
SYMBOL

PARAMETER

54174LS

CL =15ipF CL = 15 pF
RL = 280 n
Min

Max

f max

Maximum Clock Frequency

80

tPLH
tPHL

Propagation Delay
CPn to On or Cin

7.0
7.0

tPLH
tpHL

!:r0pagation ~Iay
SOn to On or On

7.0
7.0

Min

UNITS

CONDITIONS

Max

30

MHz

Figs. 3-1, 3-9

16
24

ns

Figs. 3-1, 3-9

16
24

ns

Figs. 3-1, 3-10

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54174S
Min

Max

54/74LS
Min

UNITS

CONDITIONS

Max

ts (H)
ta(U

Setup Time
In or Kn to CPn

7.0
7.0

20
15

ns

th (H)
th (U

Hold Time
I n or Kn to CPn

0
0

0
0

ns

tw (H)
tw (U

CPn Pulse Width

6.0
6.5

20
15

ns

Fig. 3-9

tw (U

SOn Pulse Width LOW

8.0

15

ns

Fig. 3-10

4-156

Fig. 3-7

114
CONNECTION DIAGRAM
PINOUT A

545/745114
54L5/74L5114
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP

coO:
K1U

(With Common Clocks and Clears)

J,[}

-S01l..!
~

DESCRIPTION - The '114 features individual J, K and set inputs and common clock and common clear inputs. When the clock goes HIGH the inputs
are enabled and data will be accepted. The logic level of the J and K inputs
may be allowed to change when the Clock Pulse is HIGH and the bistable will
perform according to the truth table a;; long as the minimum setup times
are observed. Input data is transferred to the outputs on the negative-going
edge of the clock pulse.
TRUTH TABLE

@ tn + 1

J

K

a

L
L
H
H

L
H
L
H

an
L
H
an

PKGS

OUT

Plastic
DIP(P)

A

f WJ"~IfrL
co

CD
02

t

3- J

MILITARY GRADE

= +5.0 V ±5%,
= O°C to +70°C

= +5.0 V ±10%,
= -55°C to +125°C

74S114PC, 74LS114PC

TYPE

So

}]02

'r 11 02

1b

1

9A

0f.-5

>----c cp

1.!J

So

a P-6 B.

K Co

?

?

Vcc = Pin 14
= Pin 7

GND

Ceramic
DIP (D)

A

74S114DC, 74LS114DC

54S114DM,54LS114DM

6A

Flatpak
(F)

A

74S114FC, 74LS114FC

54S114FM, 54LS114FM

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

h J2, K1, K2
CP

CD
S01, S02
01, 02, 01,02

DESCRIPTION
Data Inputs
Clock Pulse Input (Active Falling Edge)
Direct Clear Input (Active LOW)
Direct Set Inputs (Active LOW)
Outputs

4-157

0-9

L-c CP

2-K Co

PKG

Vee
TA

S02
02

b

13 -

Vee

:ill J2

LfC'~

IT

GNO[2

= HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.

TA

:illK2

01

UJ '=;. ~ ..,..,.,..!.QJ S02

H

COMMERCIAL GRADE

S01

~'

LOGIC SYMBOL

ORDERING CODE: See Section 9
PIN

0,

Asynchronous Inputs:
LOW input to So sets a to HIGH level
LOW input to CD sets a to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So
makes both a and 0 HIGH

INPUTS OUTPUT
@ tn

0,[[

~vcc
TIlCi>

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.25/1.0
5.0/5.0
5.0/8.75
2.5/4.375
25/12.5

0.5/0.25
2.0/0.5
1.5/0.5
1.5/0.5
10/5.0
(2.5)

a 0-8

•

114
LOGIC DIAGRAM (one half shown)

-

-

~

-

Q

r

'--X:-

~

~Q

.Co

TO
OTHER
FLlp·FLOP

I

~

k*

I I

J

So
K

Jp
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174S

PARAMETER

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

Max

54174LS

Min

8.0

50

= +5.0 V,

TA

CL
RL

PARAMETER

= 15 pF
= 280 n

Min

Max

fmax

Maximum Clock Frequency

tPLH
tPHL

Propagation_Delay
CP to a ora

7.0
7.0

tPLH
tpHL

Propagation Delay
Co or SOn to a or

7.0
7.0

SYMBOL

80

a

AC OPERATING REQUIREMENTS: Ve
PARAMETER

mA

Vee

= +25°C (See Section 3 for waveforms and
54174S

SYMBOL

CONDITIONS

UNITS

Max

= Max, Vep = 0 V

lOad configurations)

54174LS

CL

= 15 pF

Min

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-9

16
24

ns

Figs. 3-1, 3-9

16
24

ns

Figs. 3-1, 3-10

30

= +5.0 V, TA = +25°C
54174S

Min

Max

54/74LS

Min

UNITS

CONDITIONS

Max

ts (H)
ts (l)

Setup Time_
In or Kn to CP

7.0
7.0

20
15

ns

Fig. 3-7

th (H)
th (l)

Hold Time
I n or Kn to CP

0
0

0
0

ns

Fig. 3-7

tw (H)
tw (l)

CP Pulse Width

6.0
6.5

20
15

ns

Fig. 3-9

tw

Co or SOn Pulse Width

8.0

15

ns

Fig. 3-10

4-158

121
CONNECTION DIAGRAM
PINOUT A

54/74121
MONOSTABLE MULTIVIBRATOR

-

orr

DESCRIPTION - The '121 features positive and negative dc level triggering
inputs and complementary outputs. Input pin 5 directly activates a Schmitt
circuit which provides temperature compensated level detection, increases
immunity to positive-going noise and assures jitter-free response to slowly
rising triggers.

Elvcc

NC [I

TIlNC

AdI
AdI

~NC
~RXCX

BIT

~cx
~RINT

orr

~NC

GNO[2

When triggering occurs, internal feedback latches the circuit, prevents retriggering while the output pulse is in progress and increases immunity to
negative-going noise. Noise immunity is typically 1.2 V at the inputs and 1.5 V
on Vee.
LOGIC SYMBOL
Output pulse width stability is primarily a function of the external Rx and Cx
chosen for the application. A 2 kO internal resistor is provided for optional
use where output pulse width stability requirements are less stringent. Maximum duty cycle capability ranges from 67% with a 2 kO resistor to 90% with
a 40 kO resistor. Duty cycles beyond this range tend to reduce the output
pulse width. Otherwise, output pulse width follows the relationship:
tw = 0.69 RxCx

yr

9-

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
Vee = +5.0 V ±5%,
TA = O°C to +70°C

MILITARY GRADE
Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

Ceramic
DIP (D)

A

74121DC

54121DM

6A

Flatpak
(F)

A

74121FC

54121FM

31

74121PC

RxCx Cx
0-6
RINT

1~

4-

9A
Vec = Pin 14
GND = Pin 7
NC = Pins 2,8,12,13

INPUT LOADING/FAN-OUT: See Section 3 for U.L.definitions
PIN NAMES

A1, A2
B

a,a

o

5B

DESCRIPTION
Trigger Inputs (Active Falling Edge)
Schmitt Trigger Input (Active Rising Edge)
Outputs

4-159

54/74 (U.L.)
HIGH/LOW
1.0/1.0
2.0/2.0
20110

0--1

•

121
TRIGGERING TRUTH TABLE

A1

INPUTS
k B

H

RESPONSE

I

H
L

X

X

L

.r

L
""l.

L

X

X

1-

H

L
H

No Trigger
Trigger
Trigger

....r

L

L-

X

X

L-

H

'-

L
H

NOTE:
Triggering occurs only when the is
output is HIGH (not In timing cycle)
and one of the above triggering situations is satisfied.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

No Trigger
No Trigger
Trigger
No Trigger
No Trigger
Trigger

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
54174

PARAMETER

SYMBOL

Min
VT+

Positive-going Threshold
Voltage at An or B Inputs

VT-

Negative-going Threshold
Voltage at An or B Inputs

los

Output Short Circuit
Current

Icc

Power Supply
Current

CONDITIONS

V

Vee = Min

V

Vee = Min

-55
-55

rnA

Vee = Max

25
40

rnA

Vee = Max

2.0
0.8
XM
XC

-20
-18

I Quiescent State

I

UNITS
Max

Fired State

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174
PARAMETER

SYMBOL

UNITS

CL = 15 pF
Min

Max

15

55

ns

25

70

ns

20

65

ns

30

80

ns

CONDITIONS

tPLH

Propagation Delay
Bto Q

tPLH

An to Q

tPHL

Propagation Delay
B to 0

tPHL

An to Q

tw

Pulse Width Using
Internal Timing Resistor

70

150

ns

Cx = 80 pF

tw

Pulse Width with Zero
Timing Capacitance

20

50

ns

Cx = 0 pF

tw

Pulse Width Using External
Timing Resistor

600

800

ns

Cx = 100 pF

6.0

8.0

ms

Rx=10kO
Pin 9 = Open
Fig. 3-1, a
Cx = 1.0j.lF

tHOLD

Minimum Duration
of Trigger Pulse

50

ns

ex = 80 pF, Rx = Open

Propagation Delay

Propagation Delay

4-160

Cx = 80 pF
Fig. 3-1, Fig. a

Rx = Open
Fig. 3-1
Fig. a
Pin 9 = Vee

Pin 9 = Vee, Fig. a

121
AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA.= +25°C
SYBMOL

54/74

PARAMETER
Min

Vr-f

Input Pulse
Rise/Fall Slew Rate

Rx

External Timing Resistor

Cx

External Timing Capacitor

tw

Output Pulse Width

UNITS
1.0
1.0

VllJ,s
Vis

1.4
1.4

40
30

kO

0

1000

p.F

40

sec

67
90
90

%

@An
@8
XC
XM

XM,XC
XM
XC

Duty Cycle

_

\

_tHOlD_

A

-',...

\

/

B

/

\

Q

J

""'

~.5V

~L

~

-

~_tPlH

l

\~Vm

~

- \r

tw

~tPHl

a

CONDITIONS

Max

'---

C
I

1\
Fig. a

4-161

Fig. a
Rx=2kO
Rx-30kO
Rx = 40 kO

•

121
TYPICAL CHARACTERISTICS
+30%

::z: +1.0%

~ +1.0

Ii

Ii

~ +0.5

V

/
./

-

I

V-

-50

50

I

~

75

100

T A - AMBIENT TEMPERATURE _

0

TA =25'l
-1.0

4.5

125

c

I 1.8

~....c

g

'\"

1.7

,

e

g

1.8

:t

:=
..
~

1.5

"

~
:Ii

1.4
Vee = 5 Y

1.3

~
I

f".. r--.....
....... ........

1.2
-75

-1 -1.0%

-75

5.5

50

e

40

z

30

~

0:

I'--

20

i

10

~

70
CL~F

I

f-

c, • '00

C, .50

w 80

:Ii

PI'

1':--"

....

,....- ~

CL~

;:

-

c,~ ~

>- 50

:l

w

e

z
z
:>
....

1~

CL

40

""'-

~

.....

~

--

0

0:

30
1--74121.-

I 20

Vee

,

=5 V

"

Cr =80 pF
RT = i'NTE~NAL

o

rn

125

Fig. d Variation In
Output Pulse Width
Versus Ambient Temperature

1--'74121_

'i,

-50 -25
25
50
75 100
TA -AMBIENT TEMPERATURE _ °c

80

::J

n

~7412i-

~

70

;:
~

tw=420nl @TA=25'C

/

I

I

...-

/

..0.5%

~

I

NEGjTIVE ~G T~f~LO Vr74121

:t

:>

I!

~ 60

,-,SITIVE GOING THRESHOLO
VT.

ffi

"~

~

~

80

l(v,.! -JI-

LCKLSH

/

!

Fig. c Variation In
Output Pulse Width
Versus Supply Voltage

>

......

0%

S

5.25
4.75
5.0
Vee-SUPPLY VOLTAGE-V

Fig. b Variation In
Internal Timing Resistor Value
Versus Ambient Temperaure
w

I

tw =420 •• @Ycc""5V

CT""80pF

~

25

[

~ V
= -0.5 RT = 10 kn (EXTERNAL)

I-'"

-25

w
~ +0.5%

---I--

.... /

!

~(4121 ~
·10%
-75

Ii

1--74121_

=

T A - AMBIENT TEMPERATURE _ .. C

Flg_ e Schmitt
Trigger Threshold Voltage
Versus Ambient Temperature

Fig. f Propagation Delay
Time B Input to Q Output
Versus Ambient Temperature

Flg_ g Propagation Delay
Time B Input to Q Output
Versus Ambient Temperature

~

~

~

~

75

100

RT =IINTErNAL

TA - AMBIENT TEMPERATURE - "C

~

25

-25

50

125

o

25
50
75 100
-50 -25
TA-AMBIENT TEMPERATURE_OC

-50

25

Vee = 5 V
Cr=80pF

10

-75

10ms

l-

ji

.

,
10 ...

J..t

.......

10J'1

Z

I~\~

G<

Yee =5 V
TA

4

8 8 10

20

40

I

'""
lOOn"

/'

-6'."~'I>.

~~

10 ~I

j

/'/'

~9

= 25"C

I I

10na
1

~~ '+~
9~
..

§

C1?

.......

~ 100 ~I

...

~oII0f i-'"

100 ns

... ~~~

I-

No Trigger
Trigger
Trigger

:::I

10 3
8
6

..,0 y.\~
'l~

4

3

\\ y.\~

~

2

'O~

1-10 2
:::I
8
6

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

j:

iii

o...

.., y.{\

4

3
2

10
1

2

3 4 6810

2

3 4 6 8102

2

34

TIMING CAPACITANCE Cx - pF

Fig. 8.

4-167

6810 3

123
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER

los

Output Short
Circuit Current

lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0

V, TA

UNITS

CONDITIONS

Min

Max

-10

-40

mA

Vee

= Max

66

mA

Vee

= Max

= +25°C (See

Section 3 for waveforms and load configurations)

54/74

SYMBOL

CL = 15 pF
RL = 400 0

PARAMETER

Min

UNITS

CONDITIONS

Max

tPLH

Propagation Delay
B to Q

28

ns

tPLH

Propagation Delay
Ato Q

33

ns

tPHL

Propagation Delay
B to Q

36

ns

tPHL

Propagation Delay
A to Q

40

ns

tPLH

Propagation Delay
COn to Q

40

ns

tPHL

Propagation Delay
COn to Q

27

ns

tw(min)

Pulse Width with Zero
Timing Capacitor

65

ns

Cx = 0 pF, Rx = 5 kO
Fig. 3-1, Fig. a

tw

Pulse Width with External
Timing Components

3.37

Ils

Cx = 1000 pF, Rx
Fig. 3-1, Fig. a

2.76

AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

TA

54/74

Min

Rx

External Timing Resistor

Cx

External Timing Capacitor

~

= 10 kO

UNITS

CONDITIONS

Max

40

Trigger Pulse Width

Cx = 0 pF, Rx = 5 kO
Figs. 3-1, 3-10

= +25°C

PARAMETER

tw

Cx = 0 pF, Rx = 5 kO
Fig. 3-1, Fig. a

ns

5.0
5.0

50
25

kO

No Restrictions

pF

4-168

Over Operating
Temperature Range

125
CONNECTION DIAGRAM
PINOUT A

54/74125
54LS/74LS125A

-

E('1

o[!

QUAD BUS BUFFER GATE

ou

(With 3-State Outputs)

E[!

o[!

ORDERING CODE: See Section 9
PIN
PKGS

OUT

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Plastic
DIP(P)

A

74125PC, 74LS125APC

Ceramic
DIP (D)

A

74125DC, 74LS125ADC

Flatpak
(F)

MILITARY GRADE

COMMERCIAL GRADE

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

o[!

PKG

GNOII

Inputs
Outputs

3JCC

74125FC, 74LS125AFC

54125FM,54LS125AFM

54/74 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
130/10
(50l

0.5/0.25
65/15
(25)/(7.5)

TIl 0
~E

11 0
]]0

6A
INPUTS

A

ffio

TRUTH TABLE

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

~CC

EJvcc
'i31-,-,E

TYPE
9A

54125DM, 54LS125ADM

-

E

D

L
L
H

L
H
X

OUTPUT

L
H

Z

H = HIGH Voltage l.evel
L = LOW Voltage Level
x = Immaterial
Z = High Impedance

DC AND AC CHARACTERISTICS: See Seciton 3'
SYMBOL

54/74

PARAMETER

54174LS

UNITS

CONDITIONS

Min Max Min Max

VOH

Output HIGH Voltage

~
~
~
XC

2.4
2.4

los

Output Short
Circuit Current

~

XM

-30
-28

lee

2.4
2.4

V

10H
10H
10H
IOH

= -2.0 mA
= -5.2 mA
= -1.0 mA
= -2.6 mA
= Max

Vee = Min,
VIN = VIH or VIL

-70
-70

-30 -130
-30 -130

mA

Vee

Power Supply Current

54

20

mA

Outputs OFF, VIN = Gnd
VE = 4.5 V, Vee = Max

tPLH
tPHL

Propagation Delay
Data to Output

13
18

15
18

ns

Figs. 3-3, 3-5

tPZH
tPZL

Output Enable Time

17
25

16
25

ns

Figs. 3-3, 3-11, 3-12

tPLZ
tPHZ

Output Disable Time

8.0
12

25
25

ns

Figs. 3-3, 3-11, 3-12

"DC limits apply over operating temperature range; AC limits apply at TA = +25°C and Vee = +5.0 V.

4-169

126
CONNECTION DIAGRAM
PINOUT A

54/74126
54LS/74LS126

o[I

QUAD BUS BUFFER GATE

olI

(With 3-State Outputs)

E[I
o[I

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

A

74126PC, 74LS126PC

Ceramic
DIP (0)

A

74126DC, 74LS126DC

A

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Plastic
DIP (P)

Flatpak
(F)

MILITARY GRADE

o[!
PKG

GNOIT

74126FC, 74LS126FC

54126FM, 54LS126FM

Inputs
Outputs

54174 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
130/10
(50)

0.5/0.25
65/15
(25)/(7.5)

~o

5J~

o

rm E
~o
~o

TRUTH TABLE

6A

INPUTS

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

bJ4= rm

Vee

I1iIE

TYPE
9A

54126DM,54LS126DM

iEl

~

Err

E

0

H
H
L

L
H
X

OUTPUT
L
H

Z

H = HIGH Voltage Level
L = LOW Voltage Level
x = Immaterial
Z = High Impedance

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

54174LS

54174

PARAMETER

UNITS

CONDITIONS

Min Max Min Max
XM
VOH

Output HIGH Voltage

los

Output Short
Circuit Current

lee

Power Supply Current

XC
~

2.4
2.4

XC
XM

XC

V

2.4
2.4
-30
-28

-70
-70

-30 -130
-30 -130

mA

24
mA
62

20

IOH = -2.0
IOH = -5.2
10H = -1.0
10H - -2.6
Vee

mA
mA
Vee = Min,
mA VIN = VIH or VIL
mA

= Max

Outputs LOW,
VE = 4.5 V
Outputs OFF,
VE = 0 V

tPLH
tPHL

Propagation Delay
Data to Output

13
18

15
18

ns

Figs. 3-3, 3-5

tP.ZH
tPZL

Output Enable Time

18
25

20
30

ns

Figs. 3-3, 3-11, 3-12

tPLZ
tPHZ

Output Disable Time

16
18

30
30

ns

Figs. 3-3, 3-11, 3-12

'DC limits apply over operating temperature range; AC limits apply at TA = +25°C and Vee = +5.0 V.

4-170

Vec
VIN

= Max
= Gnd

132
CONNECTION DIAGRAM
PINOUT A

54/74132
548/748132
54L8/74L8132
QUAD 2-INPUT
SCHMITT TRIGGER NAND GATE
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

II
II

TYPE

[I

A

74132PC, 74S132PC
74LS132PC

Ceramic
DIP (0)

A

74132DC, 74S132DC
74LS132DC

54132DM,54S132DM
54LS132DM

6A

Flatpak
(F)

A

74132FC, 74S132FC
74LS132FC

54132FM,54S132FM
54LS132FM

31

Plastic
DIP (P)

~

11

ORDERING CODE: See Section 9

II

9A

II
GNOII

=Jrr=
=0~

~vee

~

~
~
~
~
~

INPUT LOADING/FAN-OUT: See Section 3 for U.L. defintions
PINS

54174 (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

Inputs
Outputs

1.0/0.75
20/10

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

PARAMETER

54/74S

54174

54174LS

CONDITIONS

UNITS

Min Max Min Max Min Max
VT+

Positive-going
Threshold Voltage

1.5 2.0

1.6

1.9

1.4 1.9

V

Vee

= +5.0 V

VT-

Negative-going
Threshold Voltage

0.6 1.1

1.1

1.4

0.5 1.0

V

Vee

= +5.0 V

VT+-VT-

Hysteresis Voltage

0.4

0.2

0.4

V

Vee

= +5.0 V

IT+

I n put Cu rrent at Positivegoing Threshold

-0.43 *,

-0.9 *'

-0.14**

rnA

Vee

= +5.0 V,

VIN

= VT+

IT-

Input Current at Negativegoing Threshold

-0.56 **

-1.1 **

-0.18*'

rnA

Vee

= +5.0 V,

VIN

= VT-

los

Output Short Circuit Current

rnA

Vee

= Max,

VOUT

=0 V

leeH
leel

Power Supply Current

24
40

44
68

11
14

rnA

VIN
VIN

tPlH
tPHl

Propagation Delay

22
22

10.5
13

20
20

ns

Figs. 3-1, 3-4

'~c

-18 -55

limits apply over operating temperature range; AC limits apply at TA = +25'C and Vee = +5.0 V. "Typical Value

4-171

= Gnd IVee = Max
= Openl

•

133
CONNECTION DIAGRAM
PINOUT A

548/748133
54L8/7 4L8 133
13-INPUT NAND GATE
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
VCC = +5.0 V ±5%,
TA = O°C to +70°C

MILITARY GRADE
VCC = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74S133PC, 74LS133PC

Ceramic
DIP (D)

A

74S133DC, 74LS133DC

54S133DM,54LS133DM

68

Flatpak
(F)

A

74S133FC, 74LS133FC

54S133FM, 54LS133FM

4L

98

~vcc

II iL-

~
~
,----IT
~
1.-!!
~
[!
~
II ~~ ~
GNO[!
~
[I
[!

"

INPUT LOADING/FAN-OUT: See Section 3 for U.L definitions
PINS
Inputs
Outputs

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

PARAMETER

54174S

54174LS

UNITS

CONDITIONS

Min Max Min Max
ICCH

Power Supply Current

ICCl
tPlH
tPHl

Propagation Delay

'DC limits apply

over operating temperature range;

5.0

0.5

10

1.1

6.0
7.0

15
38

mA

VIN
ns

AC limits apply at TA = +25'C and Vee = +5.0 V.

4-172

VIN

= Gnd
= Open

Figs. 3-1, 3-4

Vcc

= Max

134
CONNECTION DIAGRAM
PINOUT A

54S/74S134
12-INPUT NAND GATE

IT

(With 3-State Outputs)

II

-

~vcc
r--- ~E

~

[!

f4

rm

II
I!
II

~

-

ORDERING CODE: See Section 9

tJ1]

~- rm

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
T A = 0 0 C to +70 0 C

Vee = +5.0 V ±10%,
TA = -55 0 C to +125°C

y

TYPE

A

74S134PC

Ceramic
DIP(Dl

A

74S134DC

54S134DM

68

Flatpak
(Fl

A

74S134FC

54S134FM

4L

TRUTH TABLE

98
INPUTS

OUTPUTS

A ......... L

Enable

Y

H ......... H
Any In LOW
X ......... X

L
L
H

L
H
Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

Inputs
Outputs

~

PKG

Plastic
DIP (Pl

PINS

~

'l!o--

GNO[!

54174S (U.L.)
HIGH/LOW
1.25/1.25
50/12.5

DC AND AC CHARACTERISTICS: See Section 3"
SYMBOL

54174S

PARAMETER
Min

VOH

Output HIGH Voltage

lee

Power Supply
Current

tPLH
tPHL

Propagation Delay
Data to Output

tPZH
tPZL
tPHZ
tpLZ

I
I

XM
XC

UNITS

CONDITIONS

Max

2.4
2.4

V

IOH = -2.0 mA
IOH - -6.5 mA

I
I

Vee = Min
VIN = 0.8 V

13
16
25

mA

VIN = 0 V, VE' = 0 V
VIN - 5'.0 V, V'E - 0 V
VIN - 5.0 V, VE - 5.0 V

6.0
7.5

ns

Figs. 3-3, 3-4

Output Enable Time

19.5
21

ns

Figs. 3-3, 3-11,3-12

Output Disable Time

8.5
14

ns

Figs. 3-3, 3-11,3-12

Outputs HIGH
Outputs LOW
Outputs OFF
2.0
2.0

'oe limits apply over operating temperature range; Ae limits apply at TA = +25°e and Vce = +5.0 V.

4-173

Vee =
Max

135
CONNECTION DIAGRAM
PINOUT A

549/749135

AlI

QUAD EXCLUSIVE-OR/NOR GATE

alI
v[I
cIT

ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP(Pl

OUT

IT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

[!

PKG

II

TYPE

GNOI!

A

74S135PC

Ceramic
DIP(Dl

A

74S135DC

54S135DM

68

Flatpak
(Fl

A

74S135FC

54S135FM

4L

98

Inputs
Outputs

~~

:ill

~

:ill

TIl

:m

:II

54/74S (U.L.)
HIGH/LOW
1.25/1.25
25/12.5

OUTPUT

A

8

C

y

L
L
H
H

L
H
L
H

L
L
L
L

L
H
H
L

L
L
H
H

L
H
L
H

H
H
H
H

H
L
L
H

H = HIGH Voltage Level
L = LOW Voltage Level

DC AND AC CHARACTERISTICS: See Section 3*
SYMBOL

:ill

TRUTH TABLE
INPUTS

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

~-~

:ill Vee

54174S

PARAMETER
Min

UNITS

CONDITIONS

Max

= Max, VIN = Gnd
A or 8 = L, C = L

lee

Power Supply Current

99

rnA

tpLH
tPHL

Propagation Delay
from A or 8 to Y

13
10

ns

tPLH
tPHL

Propagation Delay
from A or 8 to Y

12
13.5

ns

A or 8 = H, C
Fig. 3-1, 3-4

=L

tPLH
tPHL

Propagation Delay
from A or 8 to Y

13
10

ns

A or 8 = L, C
Fig. 3-1, 3-4

=H

tPLH
tPHL

Propagation DeJay
from A or 8 to Y

12
13

ns

A or 8 = H, C
Fig. 3-1, 3-5

=H

tPLH
tPHL

Propagation Delay
from C to Y

12
12

ns

A

= 8,

tPLH
tPHL

Propagation Delay
from C to Y

11.5
12

ns

A

~

"CC limits apply over operating temperature range; AC limits apply at TA = +25·C and Vee = + 5.0 V.

4-174

Vee

Fig. 3-1, 3-5

Fig. 3-1, 3-5

8, Fig. 3-1, 3-4

136
CONNECTION DIAGRAM
PINOUT A

54LS/74LS136
QUAD 2-INPUT EXCLUSIVE-OR GATE

tEl

IT 1 - - - -

(With Open-Collector Outputs)

II
IT
IT f II
II

.---

till
!ill

.---

t!ID

Vee

~ tL:= ~

GNDl..!.

r1

t!J
~ tIl

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

TRUTH TABLE

PKG
TYPE

Plastic
DIP(P)

A

74LS136PC

Ceramic
DIP (D)

A

74LS136DC

54LS136DM

6A

A

B

Z

Flatpak
(F)

A

74LS136FC

54LS136FM

31

L
L
H
H

L
H
L
H

L
H
H
L

9A

Inputs
Outputs

OUTPUT

H = HIGH Voltage Level
L = LOW Voltage Level

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

INPUTS

54/74LS (U.L.)
HIGH/LOW
1.0/0.375
OC**/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3*
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

Power Supply Current

10

mA

Vee = Max

tpLH
tpHL

Propagation Delay

23
23

ns

Other Input LOW
Figs. 3-2, 3-5

tPLH
tpHL

Propagation Delay

23
23

ns

Other Input HIGH
Figs. 3-2, 3-4

lee

'DC limits apply over operating temperature range; AC limits apply at TA = +25'C and
"OC-Open Collector

4-175

Vee =

+5.0 V.

•

137
CONNECTION DIAGRAM
PINOUT A

548/748137
1-0F-8 DECODER/DEMUL TIPLEXER
Ao

(With Input Latches)
DESCRIPTION - The 'S137 is a very high speed 1-of-8 decoder/demultiplexer with latches on the three address inputs. This device essentially combines the function and speed of the 'S1381-of-8 decoder with a 3-bit storage
latch. When the latch is enabled (LE = LOW), the '8137 acts as a 1-of-8 active
LOW decoder. When the Latch Enable (LB goes from LOW to HIGH, the last
data present at the inputs before this transition is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output
enable gate (E1 • E2) controls the state of the outputs independent of the
Address inputs or latch operation. All outputs are HIGH unless E1 is LOWand
E2 is HIGH. The 'S137 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus
oriented systems. The 'S137 is fabricated with the Schottky barrier diode process for high speed.

-

0:

~vcc

Ad]:

1m 00

Adl

~O'

LEE!

~O2

Ed]:

rm03

Ed:!

rm

04

~O5
~06

o-II
GNO[!

LOGIC SYMBOL
• SCHOTTKY PROCESS FOR HIGH SPEED
• COMBINES 1-0F-8 DECODER WITH 3-BIT LATCH
• MULTIPLE INPUT ENABLE FOR EASY EXPANSION OR
INDEPENDENT CONTROLS
• ACTIVE LOW MUTUALLY EXCLUSIVE OUTPUTS

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74S137PC

Ceramic
DIP (D)

A

74S137DC

54S137DM

68

Flatpak·
(F)

A

74S137FC

54S137FM

4L

98

4

1

2

3

LE

Ao

A,

A2

8
E, E2

00 0, 02 03 04 05 06 07

!!!!X!!!
Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

AeJ-A2
LE

E1
E2

50-57

DESCRIPTION
Address Inputs
Latch Enable Input (Active LOW)
Enable Input (Active LOW)
Enable Input (Active HIGH)
Outputs (Active LOW)

54/74S (U.L.)
HIGH/LOW
1.25/1.25
1.2511.25
1.25/1.25
1.25/1.25
25/12.5

4-176

137
TRUTH TABLE
INPUTS

OUTPUTS

LE

E1

E2

Ao

A1

A2

00

01

5:!

03 04 05 06 07

H
X
X

L
H
X

H
X
L

X
X
X

X
X
X

X
X
X

H
H

H
H

H
H

STABLE
H H H
H H H

H
H

H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

L
H
H

H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
Ao

06

05

4-177

137
FUNCTIONAL DESCRIPTION - The 'S137. is a very high speed 1-of-8 decoder/demultiplexer fabricated with
the Schottky barrier diode process. The decoder accepts three binary weighted inputs (Ao, Al, A2,) and when
enabled provides ei ght mutually exclusive active LOW outputs (00 - Or)' The'S 137 also features a 3-bit latch on
the Address !!!puts. The device functions as a 1-of-8 decoder (same as 'S138) when the Latch Enable (LE) is
LOW. When LE is HIGH, the address present one setup time prior to the LOW-to-HIGH transition of LE will be
stored in the address latches and the outputs will not be affected by further address changes. The output enable
control is an AND gate comprised of one active LOW input (El) and one active HIGH input (E2)' All outputs are
HIGH unless the enable inputs (El • 1:2) are in their true (active) state.
A non-overlapping decoder with edge-triggered address inputs can be easily implemented by tying the Latch
Enable input [E to the active HIGH Enable input (E2)' When this input (LE. 1:2) is LOW, all outputs are forced
HIGH and a new address enters the latches. When the LE. 1:2 input goes HIGH, the address is stored in the
latches and the corresponding output gate is enabled (goes LOW)' In this configuration, the address must be
stable only one setup time prior to the LOW-to-HIGH transition of the LE • E2 input. The addressed output
remains active LOW as long as the (LE • 1:2) input remains HIGH, even if the address changes. Data or control
information can thus be strobed into the 'S137 from very noisy or bus oriented systems using a LOW pulse width
equal to the minimum latch enable pulse width tw(U.
The multiple enable inputs along with the address latches allows easy expansion to a 1-of-64 decoder with
nonoverlap ping outputs (see Figure a),

STROBE
DECODER ENABLE
Xo
X,

J

X2
LE

Ao Al A2

El E2

93S137
00 0, 02 03 04 05 06 07

INPUT
ADDRESS

? 'I' 'I' 'I' ?

TO OTHER FIVE
DECODERS

I

X3
X4
Xs

(]
LE

Ao Al A2

(]

El E2

LE

Ao Al A2

El E2

LE

Ao Al A2

0
El E2

93S137

93S137

93S137

00 0, 02 03 04 05 06 07

00 0, 02 03 04 05 06 07

000, 02 03 04 05 06 07

rr!X!11XX

!X!!JO!J2J3

r!r'r!!!!
Fig. a

High Speed 1-of-64 pecoder with Input Data Storage

4-178

137
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54/74S

PARAMETER

SYMBOL

Min
Icc

UNITS

CONDITIONS

Max
95

Power Supply Current

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C (See Section 3 for waveforms and load configurations)

54174S
PARAMETER

SYMBOL

CL = 15 pF
RL=280n
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propaaation Delay
An to On

12
20

ns

Figs. 3-1, 3-20

tPLH
tPHL

~ropaHation

Delay

E1 to On

10
12

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
E2 to On

12
12

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
LE to On

12
20

ns

Figs. 3-1, 3-9

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54/74S

PARAMETER
Min

UNITS

ts (H)

Setup Time HIGH An to LE

4.5

ns

th (H)

Hold Time HIGH An to LE

0

ns

ts(U

Setup Time LOW An to LE

6.5

ns

th (U

Hold Ti me LOW An to LE

0

ns

tw (U

LE Pulse Width LOW

7.0

ns

4-179

CONDITIONS

Max
Fig. 3-13

Fig. 3-13
Fig. 3-21

138
CONNECTION DIAGRAM
PINOUT A

548/748138
54L8/7 4L8 138

Ao

1-0F-8 DECODER/DEMUL TIPLEXER

-

IT

E1vcc

AlII

moo

I!

iE1 ts1

A2

Id1

Ellh

E3 [!

]]04

IT

;m05

GNOI!

~tse

~h

DESCRIPTION - The '138 is a high speed 1-of-8 decoder/demUltiplexer.
This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a
1-0f-24 decoder using just three '138 devices or to a 1-of-32 decoder using
four '138 devices and one inverter. The '138 is fabricated with the Schottky
barrier diode process for high speed.

SCHOTTKY PROCESS FOR HIGH SPEED
DEMUL TIPLEXING CAPABILITY
MULTIPLE INPUT ENABLE FOR EASY EXPANSION
ACTIVE LOW MUTUALLY EXCLUSIVE OUTPUTS

•
•
•
•

E102

E"d::!

LOGIC SYMBOL

1

2

3

458

ElijJ E3

I

E2

~

Ao Al A2

E

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74S138PC, 74LS138PC

Ceramic
DIP (0)

A

74S138DC, 74LS1.38DC

54S138DM,54LS138DM

68

A

74S138FC, 74LS138FC

54S138FM,54LS138FM

4L

Flatpak
(F)

00 01 02 03 04 05 Oe 07

XXXIX!!!

98
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

1vl-A2

E1, E2
Ea

50-07

DESCRIPTION
Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs (Active LOW)

4-180

54174S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.25/1.25
1.25/1.25
1.25/1.25
25/12.5

0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

138
FUNCTIONAL DESCRIPTION - The '138 is a high speed 1-of-8 decoder/demultiplexer fabricated with the low
power Schottky barrrier diode process. The decoder accepts three binary weighted inputs (Ao, A1, A2) and
when enabled provides eight mutually exclusive active LOW outputs (00 - 0,). The '138 features three Enable
inputs, two active LOW(E1,"E2) and one active HIGH(Eal. All outputs will beHIGH unless E1 andE2 are LOWand
Ea is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32(Slines to 32
lines) decoder with just four '138 devices and one inverter. (See Figure aJ The '138 can be used as an 8-output
demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as
strobes. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or
active LOW state.

TRUTH TABLE
INPUTS

OUTPUTS

E1

E2

Ea

Ao

A1

A2

00

01

02

03

04

05

Os 07

H
X
X

X
H
X

X
X
L

X
X
X

X
X
X

X
X
X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H·
H
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

4-181

138

,

,

Ao
A,
A2

J

9LS04

-t>-

A3

A4

III

Ao A, A2

I~

III?

Ao A, A2

E

00 0, 02 03 04 Os 06 07

III

Ao A, A2

E

00 0, 02 03 04 Os 06 07

*r3
E

00 0, 02 03 04 05 06 07

Ao A, A2

~
E

00 0, 02 03 04 05 06 07

l !.I.!.I.I.!.I........II.I.I.I.I.LI........I.I.I.I.II.I.I.........X.l.I.I.II.J !,
Fig. a

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54/74S

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

Max

Min

74

UNITS

CONDITIONS

Max
10

rnA

Vee

= Max

= +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74S

SYMBOL

54/74LS

PARAMETER

CL
RL

= 15 pF
= 280 n

Min

Max

54174LS

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
An to an

12
12

18
27

ns

Figs. 3-1, 3-4, 3-5

tPLH
tPHL

Propagation Delay
E1 or ~ to On

8.0
11

15
24

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
E3 to On

11
11

18
28

ns

Figs. 3·1, 3-4

4·182

139

139
CONNECTION DIAGRAM
PINOUT A

548/748139
54L8/74L8139
DUAL 1-0F-4 DECODER

•

DESCRIPTION - The '139 is a high speed dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs
and providing four mutually exclusive active LOW outputs. Each decoder
has an active LOW Enable input which can be used as a data input for
a 4-output demultiplexer. Each half of the '139 can be used as a function
generator providing all four minterms of two variables. The '139 is fabricated with the Schottky barrier diode process for high speed.

•
•
•
•

SCHOTTKY PROCESS FOR HIGH SPEED
MULTIFUNCTION CAPABILITY
TWO COMPLETELY INDEPENDENT 1-0F-4 DECODERS
ACTIVE LOW MUTUALLY EXCLUSIVE OUTPUTS

LOGIC SYMBOL

1i i
E

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
OIP(P)

A

74S139PC, 74LS139PC

Ceramic
DIP (0)

A

74S139DC, 74LS139DC

54S139DM,54LS139DM

68

Flatpak
(F)

A

74S139FC, 74LS139FC

54S139FM,54LS139FM

4L

98

Ao

Al

rT1j
E

Ao

Al

DECODER.

DECODER b

0001 0203

00 0, 02 03

r!!!

! X! !

Vce = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao, A1

E

50-03

DESCRIPTION
Address Inputs
Enable Input (Active LOW)
Outputs (Active LOW)

4-183

54/74S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.25/1.25
1.25/1.25
25/12.5

0.5/0.25
0.5/0.25
10/5.0
(2.5)

139
FUNCTIONAL DESCRIPTION - The '139 is a high speed dual 1-of-4 decoder/demultiplexer fabricated with
the Schottky barrier diode process. The device has two independent decoders, each of which accepts two
binary weighted inputs (Ao, A1) and provides four mutually exclusive active LOW outputs (()o - 03!. Each
decoder has an active LOW enable @. When Eis HIGH all outputs are forced HIGH. Theenablecan be used as
the data input for a 4-output demultiplexer application. Each half of the '139 generates all four minterms of two
variables. These four minterms are useful in some applications, replacing multiple gate functions as shown in
Figure a, and thereby reducing the number of packages required in a logic network.

TRUTH TABLE

INPUTS

OUTPUTS

E

Ao

A1

00

01

02

03

H
L
L
L
L

X
L
H
L
H

X
L
L
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Fig. a

LOGIC DIAGRAM

4-184

139
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwisespecified)
SYMBOL

54/74LS

PARAMETER

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

Max

PARAMETER

Min

11

TA

= +25

0

CL

UNITS

CONDITIONS

Max

90

mA

Vee = Max

C (See Section 3 for waveforms and load configurations)

54/74LS
SYMBOL

54/74S

= 15 pF

Min

Max

54/74S

CL
RL

= 15 pF
= 280 n

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Ao or A1 to On

18
27

12
12

ns

Figs. 3-1, 3-4, 3-5

tPLH
tPHL

Propagation Delay
Eto On

15
24

8.0
10

ns

Figs. 3-1, 3-5

4-185

140
CONNECTION DIAGRAM
PINOUT A

548/748140
DUAL 4-INPUT NAND LINE DRIVER·

IT r- -

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERC,IAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

Ceramic
DIP(Q)

A

74S140DC

54S140DM

6A

A

74S140FC

54S140FM

31

Flatpak
(F)

74S140PC

9A

......

II r---NCIl:

iBJvee

-

~

~

~ ..c

[I r----l

II

11
GNDII

~~

~
~

:!J

INPUT LOADING/FAN·OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54174S (U.L.)
HIGH/LOW
2.5/2.5
75/37.5

DC AND AC CHARACTERISTICS: See Section 3"
SYMBOL

54174S

PARAMETER
Min

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

los

Output Short Circuit Current

UNITS

CONDITIONS

Max

2.0
0.5
-50

-225

V

Vcc = Min, VIN = 0.5 V,
Ro = 50 n to Gnd

V

Vcc = Min, 10l
VIN = 2.0 V

mA

Vcc

= Max, VOUT = 0 V

ICCH
ICCl

Power Supply Current

18
44

mA

VIN = Gnd
VIN - Open

tPlH
tPHl

Propagation Delay

6.5
6.5

ns

Figs. 3-1, 3-4

·DC limits apply over operating temperature range; AC limits apply at TA = +25'C and Vee = +5.0 V.

4-186

= 60 mA

Vcc

= Max

141
CONNECTION DIAGRAM
PINOUT A

74141
1-0F-10 DECODER/DRIVER (NIXIE)
(With Open-Collector Outputs)

•
LOGIC SYMBOL
DESCRIPTION -The '141 is a BCD-to-decimal decoder driver that is designed to accept a 4-bit BCD code input and drive cold-cathode indicator
tubes. This decoder utilizes design improvements that minimize switching
transients in order to maintain a stable display. The segments and numeric
designations chosen to represent the decimal numbers are shown in the Truth
Table. For binary inputs 10 through 15, the outputs are OFF. These invalid
codes can be used in blanking leading ortrailing-edgezeroes in a display. The
ten high performance, npn output transistors have a maximum reverse current of 50 J.LA at 55 V. Typical power dissipation is 55 mW.

t

Ao

i I i

00 01 02 03 04

as

06 07

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

= +5.0 V ±5%,
= O°C to +70°C

Vee

TA

PKG
TYPE

Plastic
DIP(P)

A

74141 PC

9B

Ceramic
DIP (D)

A

74141DC

6B

Vcc

= Pin 5
GND = Pin 12

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
Ao
A1-A3

00-09

BCD Input
BCD Inputs
Outputs (Active LOW)

74XX (U.L.)
HIGH/LOW
1.0/1.0
2.0/2.0
OC*/7.0mA

'OC-- Open Collector

4-187

as

09

141
FUNCTIONAL DESCRIPTION - The 1-of-10 decoder/driver accepts BCD inputs from all TTL circuits and
produces the correct output selection to directly drive gas filled cold cathode indicator tubes. The outputs are
selected as shown in the Truth Table. It is capable of driving all known available cold cathode indicator tubes
having 7.0 mA or less cathode current.

LOGIC DIAGRAM

TRUTH TABLE
A3

Ao

INPUTS

OUTPUT

As

A2

A1

Ao

ONt

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

0
1
2
3

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

4
5
6
7

H
H
H

L
L
X

L
L
H

L
H
X

9
NONE

H

H

X

X

NONE

8

tAli other outputs are off
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

74XX

PARAMETER
Min

UNITS

CONDITIONS

Max
V

Vee = Min
10 = 7.0 mA

V

Vee = Max
10 = 0.5 mA

50

p.A

Vee = Max
Vo = 55 V

Output HIGH Current
(for Input Counts 10 thru 15)

5.0
15

p.A

Power Supply Current

25

mA

VOL

Output LOW Voltage

VOH

Output HIGH Voltage
(for Input Counts 0 thru 9)

10H

Output HIGH Current

IOH
lee

2.5
60

4-188

= 55°C Vee = Max
= 70°C
Vo = 30 V
Vee = Max
Ail Inputs = Gnd
TA
TA

145
CONNECTION DIAGRAM
PINOUT A

54/74145
1-0F-10 DECODER/DRIVER
(With Open-Collector Outputs)

DESCRIPTION - The '145 decoder/drivers are designed to accept BCD
inputs and provide appropriate outputs to drive 7-segment numerical displays. All outputs remain OFF for all invalid binary input conditions. These
devices are designed for use as indicator/relay drivers or as open-collector
logic circuit drivers. Each of the high breakdown (15 V) output transistors
will sink up to 80 mA of current.

colI

-

mAo

ChI:!

EJA1

chIT

}!]A2
j]]A3

0.[[

• OPEN-COLLECTOR OUTPUTS
• 80 mA CURRENT SINKING
• 15 V GUARANTEED BREAKDOWN

05[[

:mag

06 [I

~O8

GND!!

~Ci?

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74145PC

Ceramic
DIP (0)

A

74145DC

54145DM

7B

Flatpak
(F)

A

74145FC

54145FM

4L

9B

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

Ao-A3

00-09

54174 (U.L.)
HIGH/LOW

DESCRIPTION

PIN NAMES

1.011.0

BCD Inputs
Outputs (Active LOW)

OC*/12.5

'oe-Open Collector
LOGIC SYMBOL
15

1

2

13

14

3

4

5

6

4-189

7

12

9 10 11

mvcc

0, [!

•

145
TRUTH TABLE
OUTPUTS

INPUTS

D2 03 04 05 06 07 08 09

Ao

A1

A2

A3 00 01

L
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

4-190

145
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER
Min

CONDITIONS

UNITS
Max

= Min,

= 80 rnA
= 15 V

VOL

Output LOW Voltage

0.9

V

IOH

Output HIGH Current

250

p.A

Vee = Max, VOH

lee

Power Supply Current

rnA

Vee

XC

70

XM

62

Vce

IOL

= Max,

VIN

= Gnd

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174
SYMBOL

PARAMETER

CL = 15 pF
RL = 100 n
Min

tPLH
tPHL

Propagation Delay
An to On

CONDITIONS

Max
50
50

4-191

UNITS

ns

Figs. 3-2, 3-20

150
CONNECTION DIAGRAM
PINOUT A

54/74150
16-INPUT MULTIPLEXER

17[

-

16[[
DESCRIPTION -Signals applied to the Select (So-Sa) inputs determine
which of the data inputs (10 - I1s) is routed through to the output. Data from
the selected input appears at the output (2) in inverted form. When the active-LOW Enable input is HIGH, the output will be HIGH, regardless of
other input conditions.

15[!

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +70°C

~11O

14!!

~111

Is!!

I,[!:

t!!l 112

II

ml13

lo[!

14

11
ORDERING CODE: See Section 9

ml

PKG

E[[

ml15

TYPE

2fi]

:ill SO

s3ffi

ElS1

GNOIE

llls2

Plastic
DIP (P)

A

74150PC

Ceramic
DIP (0)

A

74150DC

54150DM

6N

Flatpak
IF)

A

74150FC

54150FM

4M

9N

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
io-l1s
So-Sa

E
Z

Data Inputs
Select Inputs
Enable Input (Active LOW)
I nverted Data Output
LOGIC SYMBOL

i r iii iii 2j YY2j 'j 'j YT
10 11 12 Is r. 15 16 17 Is 19 110 111 112 113 114 1,5
151413'1-

54/74 (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
20/10

9-0 E

So
S,
S2
S3
Z

!
Vcc = Pin 24
GND = Pin 12

4-192

~vCC

1m Is
iBl I9

150
LOGIC DIAGRAM
E'lo

h

j

I.

Is

III
III
'I-

I.

15

III
III

.

DATA INPUT
17
I.
I.

16

III

III

~

I

1111

h1

ho

h.

h3

Tiffl

rz,

' '!,U

DATA SELECT
(BINARY)

• ,-.,..-A--------.

h.

,. ,.
j

OUT~UTZ
TRUTH TABLE
INPUTS

OUTPUT

53

S2

S1

So

E

X
L
L
L

X
L
L
L

X
L
L
H

X
L
H
L

H
L
L
L

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

L
L
L
L

Z
H

10
11
12

. . . . . .

112
113
114
115

H = HIGH Voltage Level
L = LOW Voltage Level
Immaterial

X=

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
54174

PARAMETER

SYMBOL

los

Output Short Circuit
Current

lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0

~
XC

V, TA

UNITS

CONDITIONS

Min

Max

-20
-18

-55
-55

mA

Vee

=

Max

68

mA

Vee

=

Max, VIN

= +25°C

= 4.5V

(See Section 3 for waveforms and load configurations)

54174
SYMBOL

PARAMETER

CL
RL

= 15 pF
= 400 n

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Sn to Z, 3 Levels

35
33

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
In to Z

20
14

ns

Figs. 3-1, 3-4

tPLH
tpHL

E

Propagation Delay
to Z

24
30

ns

Figs. 3-1, 3-5

4-193

151
CONNECTION DIAGRAM
PINOUT A

54/74151A
54S/74S151
54LS/74LS151

-

hIT

:ill Vee
:lli 14

12 [I

h[I
10 IT

8-INPUT MULTIPLEXER

~15

E]la
Ell?

zIT
:ill

:ITl SO

EIT

~Sl

GNO[!

]]S2

LOGIC SYMBOL
DESCRIPTION - The '151 is a high speed 8-input digital multiplexer. It provides in one package, the ability to select one line of data from up to eight
sources. The '151 can be used as a universal function generator to generate
any logic function of four variables. 80th assertion and negation outputs are
provided.

r
11 i 111j 1I
11E

10

h

12

13

14

15

16

17

SO

ORDERING CODE: See Section 9
PIN
PKGS

OUT

l O - S,

9 - S2

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

z

z

TYPE

!

!

Plastic
DIP(P)

A

74151APC, 74S151PC
74LS151PC

Ceramic
DIP (0)

A

74151ADC, 74S151DC
74LS151DC

54151ADM,54S151DM
54LS151DM

68

Flatpak
(F)

A

74151AFC, 74S151FC
74LS151FC

54151AFM,54S151FM
54LS151FM

4L

98
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

10-17

DESCRIPTION

Z

Data Inputs
Select Inputs
Enable Input (Active LOW)
Data Output

Z

Inverted Data Output

So-S2

E

4-194

54174 (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
20/10

1.25/1.25
1.25/1.25
1.25/1.25
25/12.5

20/10

25/12.5

0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

151
FUNCTIONAL DESCRIPTION - The '151 is a logical implementation of a single pole, 8-position switch with
the switch position controlled by the state ofthree Select inputs, So, Sl, S2. Both assertion and negation outputs
are provided. The Enable input (E) is active LOW. When it is not activated, the negation output is HIGH and the
assertion output is LOW regardless of all other inputs. The logic function provided at the output is:
Z=

(10 • So • ~11 • 52 + h • So • Sl • 82 + 12 • So • Sl • S2 + 13 • So • Sl • 82
14 • So • 51 • S2 + Is • So • 51 • S2 + 16 • So • Sl • S2 + 17 • So • Sl • S2),

E•

+

The '151 provides the ability, il'1 one package, to select from eight sources of data or control information. By
proper manipulation of the inputs, the '151 can provide any logic function of four variables and its negation.

TRUTH TABLE
OUTPUTS

INPUTS

E

52

Sl

So

Z

Z

H
L
L
L

X
L
L
L

X
L
L
H

X
L
H
L

H
10
11

L
10

L
L
L
L
L

L
H
H
H
H

H
L
L
H
H

H
L
H
L
H

13
T4
Ts
i6
17

i2

h
12
13
14
Is
16
17

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

I,

10

.....
.....
.....
.....
So

.....
.....
A

.....

r

12

14

15

16

.....
.....
.....

T

y

T

y

.....

+

+

I I'

'rt

+ . +

ill
~~

7
~
z
z

4-195

-t .f . t
~

I"

I

151
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54174

PARAMETER

SYMBOL

los

Output Short Circuit
Current

lec

Power Supply Current

~
XC

54174S

54/74LS

UNITS

CONDITIONS

Min

Max

Min

Max

Min

Max

-20
-18

-55
-55

-40
-40

-100
-100

-20
-20

-100
-100

rnA

Vee = Max

10

rnA

Vee = Max

48

70

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

54174
PARAMETER

SYMBOL

54174S

54174LS

Q = 15 pF CL = 15 pF CL = 15 pF UNITS
RL=400n RL = 280 n
Min

Max

Min

Max

Min

CONDITIONS

Max

tpLH
tpHL

Propagation Delay
Sn to Z

26
30

15
13.5

23
34

ns

Fi gs. 3-1, 3-20

tpLH
tPHL

Propagation Delay
Sn to Z

38
38

18
18

48
30

ns

Fi gs. 3-1, 3-20

tpLH
tpHL

Propagation Delay

E toZ

21
23

13
12

24
30

ns

Figs. 3-1, 3-5

tPLH
tPHL

E to Z

33
33

16.5
18

42
32

ns

Figs. 3-1, 3-4

tPLH
tpHL

Propagation Delay
In to L

14
14

7.0
7.0

21
20

ns

Figs. 3-1, 3-4

tPLH
tpHL

Propagation Delay
In to Z

20
27

12
12

32
26

ns

Figs. 3-1, 3-5

Propagation Delay

4-196

152
CONNECTION DIAGRAM
PINOUT A

54/74152A
54LS/74LS152

14

-

IT

~vCC
~Is

II
12 IT

rm

1,[1

[!:TI 15

IT
z!1

~so
~Sl

13

a-INPUT MULTIPLEXER

10

PJ

GNOIT

DESCRIPTION - The '152 is a high speed 8-input digital multiplexer. It
provides, in one package, the ability to select one line of data from up to
eight sources. The '152 can be used as a universal function generator to
generate any logic function of four variables. It is supplied in Flatpak only;
for Dual In-line Package applications use the 'LS151.

5

Flatpak
(F)

OUT
A

4

3

1 13 12 11

2

I I I I I I I I
11

12

13 14 15 16 17

9 - 5,

ORDERING CODE: See Section 9

PKGS

S2

LOGIC SYMBOL

10
1 0 - SO

PIN

16

8 - 52

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = 0° C to + 70° C

Vee = +5.0 V ±10%,
TA = -55° C to +125° C

74152AFC,74LS152FC

z

PKG

!

TYPE

54152AFM,54LS152FM

vcc = Pin 14
GND = Pin 7

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

54/74 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
20/10

0.5/0.25
0.5/0.25
10/5.0
(2.5)

Data Inputs
Select Inputs
Inverted Data Output

10-17

So-S2

Z

LOGIC DIAGRAM
10
50
5,

52

.....
....

I

........

T

I>

T

14

13

12

11

15

16

17

.......
- ....

...

_

-....
_......

-

......

,

,

I

r

y

,

1 T ,u. r

r

~
z

4-197

r

t7

r
T

,U

152
FUNCTIONAL DESCRIPTION - The '152 is a logical implementation of a single pole, 8-position switch
with the switch position controlled by the state of three Select inputs, So, S1, S2. The logic function
provided at the output is:
Z

= (10 • So • S1
14 •

So •

• 82 + h • So • S1 • 82 + 12 • So • S1 • 82 + 13 • So • S1 • 82 +
81 • S2 + 15 • So • ~h • S2 + 16 • So • S1 • S2 + 17 • So • S1 • S2).

The '152 provides the ability, in one package, to select from eight sources of data or control information.

TRUTH TABLE
OUTPUT

INPUTS
S2

S1

So

Z

L
L
L
L

L
L
H
H

L
H
L
H

To
T1
T2

H
H
H
H

L
L
H
H

L
H
L
H

14
15
T6
17

i3

H = HIGH Voltage Level
L = LOW Voltage Level

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

los

Output Short
Circuit Current

Icc

Power Supply Current

54174LS

54174

PARAMETER

1¥cXC

UNITS

CONDITIONS

Min

Max

Min

Max

-20
-18

-55
-55

-20
-20

-100
-100

mA

Vee = Max

9.0

mA

Vee = Max

43

AC CHARACTERISTICS: Vee = +5.0V, TA = +125° C (See Section 3 for waveforms an d load configurations)
54174

SYMBOL

PARAMETER

54174LS

CL = 15 pF CL = 15 pF
RL = 400 n
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Sn to Z

26
30

23
32

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
In to Z

14
14

21
20

ns

Figs. 3-1, 3-4

4-198

153
CONNECTION DIAGRAM
PINOUT A

54/74153
54S/74S153
54LS/74LS153
DUAL 4-INPUT MULTIPLEXER
EaIJ:

DESCRIPTION - The '153 is a high speed dual4-input multiplexer with common select inputs and individual enable inputs for each section. It can select
two lines of data from four sources. The two buffered outputs present data in
the true (non-inverted) form. In addition to multiplexer operation, the '153 can
generate any two functions of three variables.

s,1I

mEb

:EJSa

I,a[[

~lab
~12b

11

~"b

12a[!

PIN
PKGS

OUT

Za[!

COMMERCIAL GRADE
Vee

TA

MILITARY GRADE

= +5.0 V ±5%,

Vee

= O°C to +70°C

TA

= +5.0

PKG

V ±10%,

= -55°C to +125°C

1!] vcc

13aII

lOa

ORDERING CODE: See Section 9

-

GNOII

~IOb
~Zb

TYPE

Plastic
DIP (P)

A

74153PC, 74S153PC
74LS153PC

Ceramic
DIP (0)

A

74153DC, 74S153DC
74LS153DC

54153DM,54S153DM
53LS153DM

6B

Flatpak
(F)

A

74153FC, 74S153FC
74LS153FC

54153FM,54S153FM
54LS153FM

4L

9B

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

Za

Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Enable Input (Active LOW>
Side B Enable Input (Active LOW>
Side A Output

Zb

Side B Output

IOa-13a
IOb-l3b
So, S1

fa
Eb

54174 (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
20/10

1.25/1.25
1.25/1.25
1.25/1.25
1.25/1.25
1.25/1.25
25/12.5

20/10

25/12.5

0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

LOGIC SYMBOL

1 iii

142-

i 1, Y !
1j 1j

Eo lOa I'a 12a 13a lOb I'b 12b 13b Eb
So

Vee = Pin 16
GND = Pin 8

s,
Za

Zb

I

!

7

.4-199

153
FU NCTIONAL DESCRIPTION - The '153 is a du al 4-input multiplexer. It can select two bits of data from up to
four sources under the control of the common Select inputs (So, S1). Thetwo 4-input multiplexer circuits have
individual active LOW Enables (~, Eb) which can be used to strobe the outputs independently. When the
Eb) are HIGH, the corresponding outputs (Za, Zb) are forced LOW. The '153 is the logic
Enables
implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels
supplied to the two Select inputs. The logic equations for the outputs are shown below.

(Ea,

Ea • (loa • S1 • So + h a • 51 • So + 12a • S1 • So + l3a • S1 • So)
= Eb • (lab • 51 • So + hb • 51 • So + 12b • S1 • So + 13b • S1 • So)

Za =
Zb

The '153 can be used to move data from a group of registers to a common output bus. The particular register
from which the data came would be determined by the state of the Select inputs. A less obvious application is a
function generator. The '153 can generate two functions of three variables. This is useful for implementing
highly irregular random logic.
TRUTH TABLE

SELECT
INPUTS

INPUTS (a or b)

OUTPUT

So

S1

E

10

h

12

13

Z

X
L
L
H

X
L
L
L

H
L
L
L

X
L
H
X

X
X
X
L

X
X
X
X

X
X
X
X

L
L
H
L

H
L
L
H
H

L
H
H
H
H

L
L
L
L
L

X
X
X
X
X

H
X
X
X
X

X
L
H
X
X

X
X
X
L
H

H
L
H
L
H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

4-200

153
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

los

Output Short Circuit
Current

XM
XC

lee

Power Supply Current

XM
XC

AC CHARACTERISTICS: Vee

= +5.0 V,

TA

PARAMETER

54174LS

UNITS

CONDITIONS

Max

Min

Max

Min

Max

-20
-18

-55
-57

-40
-40

-100
-100

-20
-20

-100
-100

mA

Vee

= Max

10
10

mA

Vee

= Max

70
70

52
60

= +25

0

C (See Section 3 for waveforms and load configuration)
54174

SYMBOL

54/74S

Min

54174S

54/74LS

CL = 30 pF CL = 15 pF CL
RL = 400 n RL = 280 n
Min

Max

Min

Max

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tpHL

Propagation Delay
Sn to Zn

34
34

18
18

29
29

ns

Figs. 3-1, 3-20

tPLH
tPHL

fropagation Delay
En to Zn

30
23

15
13.5

29
32

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
In to Zn

18
23

9.0
9.0

15
20

ns

Figs. 3-1, 3-5

4-201

•

154
CONNECTION DIAGRAM
PINOUT A

54/74154
1-0F-16 DECODER/DEMUL TIPLEXER

CiolI

DESCRIPTION - The '154 is a multipurpose decoder designed to accept four
inputs and provide 16 mutually exclusive outputs. By means of the Address
(Ao - Aa) inputs, data applied to one of the Enable inputs can be routed to any
one of the outputs in True (non-inverted) form.

PIN
PKGS

OUT

Plastic
DIP(P)

A

Vee

MILITARY GRADE

= +5.0 V ±5%,

Vee

TA = O°C to +70°C

= +5.0 V ±10%,

TA = -55°C to +125°C

74154PC

o,!!

BlAo

02 I!
ch[!

B1A'
]]A2

o.!!

~Aa

Os!!
061l

}!JEo

PKG

od!:

TYPE

Os

mo,s
1!Io,.

I!

Og~

9N

Ceramic
DIP(D)

A

74154DC

54154DM

6N

Flatpak
(F)

A

74154FC

54154FM

4M

nlO'3
B10'2
TIl 0"

010ffi
GNolB

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

Ao-Aa

Eo, E1
50-015

54174 (U.L.)
HIGH/LOW

DESCRIPTION
Address Inputs
Enable Inputs (Active LOW)
Outputs (Active LOW)

1.0/1.0
1.0/1.0
20/10
LOGIC SYMBOL

'e-)
Eo

23

22

21

20

Ao

A,

A2

A3

E,

E

00 0, 02 03

O.

05 06 07

Os Og

0100,,0,20,30,.0'5

rrrr!!Y!!!X!!11X
Vcc = Pin 24
GND = Pin 12

4-202

~vcc

]!IE,

ORDERING CODE: See Section 9
COMMERCIAL GRADE

-

154
TRUTH TABLE
INPUTS

OUTPUTS

00 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015

Eo

El

Ao Al

A2 A3

H
H
L
L

H
L
H
L

X
X
X
L

X
X
X
L

X
X
X
L

X
X
X
L

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
L
H
L
H

L
H
H
L
L

L
L
L
H
H

L
L
L
L
L

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

L
H
L
H
L

H
H
L
L
H

H
H
L
L
L

L
L
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
L
H
L
H

H
L
L
H
H

L
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

4-203

154
FUNCTIONAL DESCRIPTION - The '154 decoder accepts four inputs and provides 16 mutually exclusive
active LOW outputs, as shown by the logic symbol. The active LOW outputs facilitate addressing other MSI
units with active LOW enable.

The '154 can demultiplex data by routing it from one input to one of 16 possi"ble decoder oiJtputs. The desired
output is addressed and the data is applied to one of the enable inputs. Providing that the other enable is LOW,
the addressed output will follow the state of the applied data.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified>
SYMBOL

54/74

PARAMETER

los

Output Short Circuit
Current

XM
XC

lee

Power Supply Current

XM
XC

AC CHARACTERISTICS: Vee

= +5.0 V,

TA

UNITS

CONDITIONS

Min

Max

-20
-18

-55
-57

mA

Vee

= Max

49
56

mA

Vee

= Max

= +25°C (See

Section 3 for waveforms and load configurations)

54174

SYMBOL

PARAMETER

CL = 15 pF
RL = 400.n
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
An to On

31
28

ns

Figs. 3-1, 3-20

tPLH
tpHL

Propagation Delay
En to On

23
24

ns

Figs. 3-1, 3-5

4-204

155
CONNECTION DIAGRAM
PINOUT A

54/74155
54LS/74LS155
DUAL 1-0F-4 DECODER/DEMULTIPLEXER
EalI

DESCRIPTION - The '155 contains two decoders with common Address(Ao,
Al) inputs and separate enable gates. Decoder "a" has an enable gate with one
active HIGH and one active LOW input, while decoder "b" has two active LOW
inputs. If the enable functions are satisfied, one output of each decoder will
be LOW, as selected by the Address inputs.

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Ear!

-

~vcc
~Eb

(>salI

~Eb
~Ao

02a[[

~03b

01a[!

tTI1 02b

OoalI

~01b

GND[[

~OOb

A1[!

PKG
TYPE

Plastic
DIP (P)

A

74155PC, 74LS155PC

Ceramic
DIP (D)

A

74155DC, 74LS155DC

54155DM,54LS155DM

6B

Flatpak
(F)

A

74155FC, 74LS155FC

54155FM,54LS155FM

4L

9B

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao, Al

Ea, Eb

Ea

00-5.3

DESCRIPTION

54174 (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
1.011.0
1.0/1.0
20/10

0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs (Active LOW)

LOGIC DIAGRAM
133

M 8
E

E

AD
DECODER a
A1
000,0203

AD

-

DECODER b
A1
00 0, 02 03

!!! r

!!!!
4-205

Vcc = Pin 16
GND = Pin 8

•

155
FUNCTIONAL DESCRIPTION - The '155 and '156 are dual 1-of-4 decoder/demultiplexers with common
Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary
weighted Address inputs (Ao, All and provides four mutually exclusive active LOW outputs (00-53>. If the
Enable requirements of each decoder are not met, all outputs of that decoder are HIGH.
Each decoder section has a 2-input enable gate. The enable gate for decoder "a" requires one active HIGH input
and one active LOW input (Ea, Ea.>. In demultiplexing applications, decoder "a" can accept either true or
complemented data by using the Ea or Ea inputs respectively. The enable gate for decoder "b" requires two
active LOW inputs (Eb, Eb>' The devices can be used as a 1-of-8 decoder/demultiplexer by tying Ea to Eb and
relabeling the common connection as A2. The other Et, and Ea are connected together to form the common
enable.
The '155 and '156 can be used to generate all four minterms of two variables. These four minterms are useful in
some applications replacing multiple gate functions as shown in Figure B. The '156 has the further advantage of
being able to AND the minterm functions by tying outputs together. Any number ofterms can be wired-AND as
shown below.
f

= (E + Ao + All. (E + Ao + All • (E + Ao + All. (E + Ao + All
where = E = Ea + Ea.; E = Eb + Eb

Fig. a
LOGIC DIAGRAM
Ea

Ea

Ao

Al

4-206

155
TRUTH TABLE
ADDRESS

ENABLE a

ENABLE b

OUTPUT a

OUTPUT b

Ao

AI

Ea

Ea

00 01

02 03

Eb

Eb

00 01 02 03

X
X
L

X
X
L

L
X
H

X
H
L

H
H
L

H
H
H

H
H
H

H
H
H

H
X
L

X
H
L

H
H
L

H
H
H

H
H
H

H
H
H

H
L
H

L
H
H

H
H
H

L
L
L

H
H
H

L
H
H

H
L
H

H
H
L

L
L
L

L
L
L

H
H
H

L
H
H

H
L
H

H
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

los

Output Short Circuit
Current

~

Icc

Power Supply Current

~
XC

AC CHARACTERISTICS: Vee

XM

UNITS

Min

Max

Min

Max

-20
-18

-55
-57

-20
-20

-100
-100

ns

10
10

mA

35
40

CONDITIONS

Vee

= Max

Vee

= Max; Ea. Eb = Gnd
Ea = 4.5 V

Ao. AI.

= +5.0 V. TA = +25°C (See Section 3 for waveforms and
54/74

SYMBOL

54/74LS

PARAMETER

54/74LS

CL = 15 pF CL
RL = 400 n
Min

Max

load configurations)

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
An to On

32
32

18
27

ns

Figs. 3-1. 3-20

tPLH
tPHL

Propagation Delay

Ea or Eb to 'On

20
27

15
24

ns

Figs. 3-1. 3-5

tPLH
tpHL

Propagation Delay
Ea to On

24
30

25
25

ns

Figs. 3-1. 3-4

4-207

156
CONNECTION DIAGRAM
PINOUT A

54/74156
54LS/74LS156

-

EalI

DUAL 1-0F-4 DECODER/DEMUL TIPLEXER

~vcc
~'Eb
~'Eb

'Ea£I

(With Open-Collector Outputs)

A,[I

im

03aG:

DESCRIPTION - The '156 contains two decoders with common Address
(1vJ, A1) inputs and separate enable gates. Decoder "a" has an enable gate
with one active HIGH and one active LOW input, while decoder "b" has two
active LOW inputs. If the enable functions are satistied, one output of each
decoder will be LOW, as selected by the Address inputs. For functional
description, truth table and logic diagram, please refer to the '155 data sheet.

PIN
PKGS

OUT

COMMERCIAL GRADE

~(hb

OoalI

~O'b

GND[!

~OOb

LOGIC SYMBOL

133

,i.l)
DECODERs

MILITARY GRADE

= +5.0 V ±5%,
= O°C to +70°C

Vee

TA

O'a[[

A
E

E

ORDERING CODE: See Section 9

= +5.0 V ±10%,
= -55°C to +125°C

Vee

TA

Ao

PKG

A1
000,0203

TYPE

!!!!

Plastic
DIP(P)

A

74156PC, 74LS156PC

Ceramic
DIP ----------,rr--~r---~++--.tt----4~--~+---~HH--,

Z,

'S157 • 'LS157

4-211

Zb

10.

•

157
TRUTH TABLE

INPUTS

OUTPUT

E

S

10

h

Z

H
L
L
L
L

X
H
H
L
L

X
X
X
L
H

X
L
H
X
X

L
L
H
L
H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

los

Output Short Circuit
Current

lee

Power Supply Current

~
XC

54174S

54/74LS

UNITS

CONDITIONS

Min

Max

Min

Max

Min

Max

-20
-18

-55
-55

-40
-40

-100
-100

-20
-20

-100
-100

mA

Vee = Max

16

mA

Vee = Max
Alllnputs=4.5V

48

78

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

54174
PARAMETER

SYMBOL

54174S

54174LS

CL = 15 pF CL = 15 pF CL = 15 pF
RL = 400 n RL = 280 n
Min

Max

Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tpHL

Propagation Delay
S to Zn

23
27

15
15

26
24

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay

E to Zn

20
21

12.5
12

20
21

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
In to Zn

14
14

7.5
6.5

14
14

ns

Figs. 3-1, 3-5

4-212

158
CONNECTION DIAGRAM
PINOUT A

54S/74S158
54LS/7 4LS 158

11,[!

y,!!

DESCRIPTION - The '158 is a high speed quad 2-input multiplexer. It selects
four bits of data from two sources using the common Select and Enable
inputs. The four buffered outputs present the selected data in the inverted
form. The '158 can also generate any four of the 16 different functions of
two variables.

IOb[]:

ElI,

hb[!

:TIlIOd

Zb!I

IQ) hd

GNOI!

}lZd

LOGIC SYMBOL

ORDERING CODE: See Section 9

PKGS
Plastic
DIP(P)

OUT
A

Ceramic
DIP (D)

A

Flatpak
(F)

A

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

~vcc
~E
~Ioc
~bc

loall

QUAD 2-INPUT MULTIPLEXER

PIN

-

sO:

1 iii i YYY1,

PKG

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

TYPE

74S158PC, 74LS158PC

1-S

98

74S158DC, 74LS158DC

54S158DM,54LS158DM

68

74S158FC, 74LS158FC

54S158FM,54LS158FM

4L

E

lOa l1a lOb hb loc he IOd I1d

Z,

Zb

Y
Y
4
7

Z,

Zd

! !

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
10a-lod
ha-hd

E
S
"Za-Zd

DESCRIPTION
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input (Active LOW)
Select Input
Inverted Outputs

54/74S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.25/1.25
1.25/1.25
2.5/2.5
2.5/2.5
25/12.5

0.5/0.25
0.5/0.25
1.0/0.5
1.0/0.5
10/5.0
(2.5)

TRUTH TABLE
INPUTS

OUTPUTS

~

S

10

h

Z

H
L
L
L
L

X
L
L
H
H

X
L
H
X
X

X
X
X
L
H

H
H
L
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

4-213

•

158
FUNCTIONAL DESCRIPTION - The '158 is a quad 2-input multiplexer fabricated with the Schottky barrier
diode process for high speed. It selects four bits of data from two sources under the control of a common Select
input (S) and presents the data in inverted form at the four outputs. The Enable inpuHE) is active LOW. When Eis
HI GH, all of the outputs (Z) are forced HIGH regardless of all.other inputs. The '158 is the logic implementation
of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the
Select input.
A common use of the '158 isthe moving of data from two groups of registers to four common output busses. The

particular register from which the data comes is determined by the state of the Select input. A le~s obvious use is
asa function generator. The '158 can generate four functions of two variables with one variable common. This is
useful for implementing gating functions.
LOGIC DIAGRAM
1o.

lOb

ICd

10,

l'b

n

~--+---+-'---+---H--------+--~

(~I I~

~

(1 (

(

I

I

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74S

PARAMETER

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

Max

tpHL
tpLH
tpHL

UNITS

CONDITIONS

Max
8.0

mA

Vee = Max·

= +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

PARAMETER

CL
RL

= 15 pF
= 280 n

Min

tpLH

Min

61

54174S
SYMBOL

54174LS

Max

54174LS
CL

= 15 pF

Min

UNITS

CONDITIONS

Max

Propagation Delay, S to Z

12
12

20
24

ns

Figs. 3-1., 3-20

E to Z

11.5
12

16
16

ns

Figs. 3-1, 3-5

Propagation Delay, In to Z

6.0
6.0

13
11

ns

Figs. 3-1, 3-4

Propagation Delay,

"IcC measured with outputs open and 4.5 V applied to all inputs.

4-214

160 • 162
CONNECTION DIAGRAM
PINOUT A

54/74160
54/74162

• 54LS/74LS160
• 54LS/74LS162

SYNCHRONOUS PRESETTABLE
BCD DECADE COUNTERS
DESCRIPTION - The '160 and '162 are high speed synchronous decade
counters operating in the BCD (8421) sequence. They are synchronously
presettable for application in programmable dividers alid have two types of
Count Enable inputs plus a Terminal Count output for versatility in forming
synchronous multistage counters. The '160 has an asynchronous Mastef
Reset input that overrides all other inputs and forces the outputs LOW. The
'162 has a Synchronous Reset input that overrides counting and parallel
loading and allows all outputs to be simultaneously reset on the rising edge
of the clock. For the S-TTL and LP-TTL versions, please see the 9310 data
sheet.
•
•
•
•

SYNCHRONOUS COUNTING AND LOADING
HIGH SPEED SYNCHRONOUS EXPANSION
TYPICAL COUNT RATE OF 35 MHz
LS VERSIONS FULLY EDGE TRIGGERED

PKGS

OUT

:ill Vee

cpIT

:lliTC

Poll

:mao

P11!

El01

P21]

:ill 02

m

P31!

03

CEP[!

:m

GNOI!

]]PE

'MR for '160
'SR for '162

LOGIC SYMBOL

PE Po P, P2 P3

7 - CEP

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°

PKG

1 0 - CET

TC

~15

2 - CP

TYPE

Plastic
DIP(P)

A

74160PC, 74LS160PC
74162PC, 74LS162PC

Ceramic
DIP (0)

A

74160DC, 74LS160DC
74162DC, 74LS162DC

54160DM,54LS160DM
54162DM, 54LS162DM

7B

Flatpak
(F)

A

74160FC, 74LS160FC
74162FC, 74LS162FC

54160FM,54LS160FM
54162FM,54LS162FM

4L

9B

'R 00 01 02 03

r1~
Vee = Pin 16
GND = Pin 8

}3

1~

}1

'MR for '160
'SR for '162

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

00-03

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input
(Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-flop Outputs

TC

Terminal Count Output

CEP
CET
CP
MR ('160)
SR ('162)
Po- P:l
PE

CET

1iii i

ORDERING CODE: See Section 9
PIN

-

*liE

54/74 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
2.0/2.0
2.0/2.0
1.0/1.0

0.6/0.3
1.0/0.5
0.6/0.3
0.5/0.25

1.0/1.0
1.0/1.0
1.0/1.0
20/10

0.5/0.25
0.5/0.25
0.6/0.3
10/5.0
(2.5)
10/5.0
(2.5)

20/10

160 -162
LOGIC DIAGRAMS
'160
Po

CET
CEP

TC
CP~>-----+-~--+---~----+-~--+---~--~--~~--+-----------+-~

Qo

'162
Po

SR--~~~~+-+----+----~r-r---~--~r-+---~----------,

TC

Qo

4-216

160 • 162
LOGIC DIAGRAMS
'LS160
Po

PE

-'"

I '"
CEP
IT5~

P3

I

I

I

tJ

tJ

tJ

CET

CP

~~ ~f '\,
..
I
1
r+ i!Jt

~

if-

~

Lj
TC

~

-"

-----.J

I
aD

~

aDI

HCD

aD I

1CD

aD I

I

LJ

I

~

I

I

I

I

a3

'LS162
Po

P3

PE-----.,........[>---.,---,.-+-----rl--------?-+----------,

CEP

l:=rn1;:±~~~~p

cp------l>

~~~~~~~~~~~~~

a3

aD

4-217

TC

160 • 162
FUNCTIONAL DESCRIPTION - The '160 and '162 count modul0-10 in the BCD (8421) sequence. From state 9
(HLLH) they increment to state 0 (LLLU. The '161 and '163 count modul0-16 binary sequence. From state 15
(HHHH) they increment to state 0 (LLLU. The clock inputs of all flip-flops are driven in parallel through a clock
buffer. Thus all changes of the Q outputs (except due to Master; Reset of the '160 and '161) occur as a result of,
and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous reset ('160 and '161), synchronous reset ('162 and
'163), parallel load, count-up and hold. Five control inputs - Master Reset (MR, '160 and '161), Synchronous
Reset (SR, '162 and '163), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading
and allows all outputs to go LOW on the next rising edge of CPo A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CPo
With PE and MR ('160, '161) or SR ('162, '163) HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits counting.
The TTL versions ('160-'163, as opposed to the 'LS160-'LS163) contain master/slave flip-flops which are
"next-state catching" because of the J K feedback. This means that when CP is LOW, information that would
change the state of a flip-flop, whether from the counting logic or the parallel entry logic if either mode is
momentarily enabled, enters the master and is locked in. Thus to avoid inadvertently changing the state of a
master latch, and the subsequent transfer of the erroneous information to the slave when the clock rises, it is
necessary to insure that neither the counting mode, the synchronous reset mode, nor the parallel entry mode is
momentarily enabled while CP is LOW.
The LS-TTLversions ('LS160 - 'LS163) use D-type edge-triggered flip-flops and changi ng the SR, PE, CEP and
CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for
the decade counters, 15 for the binary counters). To implement synchronous multistage counters, the TC
outputs can be used with the CEP and CET inputs in two different ways. These two schemes are shown in the
9310 data sheet. The TC output is subject to decoding spikes dueto internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the LS-TTL
versions ('LS160, 'LS162) of the decade counters, the TC output is fully decoded and can only be HIGH in state 9.
In the TTL versions ('160, '162), however, the TC output can also be HIGH in the illegal states 11,13 and 15. If a
decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return tothe
normal sequence within two counts, as shown in the state diagrams.
LOGIC EQUATIONS: Count Enable = CEP • CET • PE
('160, '162) TC = Qo • Q3 • CET
('LS160, 'LS162) TC = Qo • 01 • Q2 • Q3 • CET
('161, 'LS161, '163, 'LS163) TC = Qo. Q1 • Q2 • Q3 • CET
MODE SELECT TABLE
'SR PE
L
H
H
H
H

X
L
H
H
H

CET

CEP

Action on the Rising
Clock Edge ( I )

X
X
H
L
X

X
X
H
X
L

RESET (Clear)
LOAD (P n -'Qn)
COUNT !increment)
NO CHANGE (Hold)
NO CHANGE (Hold)

'160, '162

>For the "62 and "63 only.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

4-218

STATE DIAGRAMS
'LS160, 'LS162

160 • 162
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER

Min

Max

54174LS
Min

UNITS

CONDITIONS

Max

lecH

Power Supply Current
Outputs HIGH

XM
XC

85
94

31
31

mA

Vee = Max, PE = Gnd
Other Inputs = 4.5 V
Cp=...r-

ICCL

Power Supply Current
Outputs LOW

XM
XC

91
101

32
32

mA

Vec = Max
All Inputs = Gnd
CP=...r-

AC CHARACTERISTICS: Vcc = +5.0 V, TA = +25 0 C (See Section 3 for waveforms and load configurations)
54174
SYMBOL

PARAMETER

54/74LS

CL = 15 pF CL = 15 pF
RL = 400 n
Min

Max

25

Min

UNITS

CONDITIONS

Max

25

MHz

Fi gs. 3-1, 3-8

25
21

ns

Figs. 3-1, 3-8

20
23

24
27

ns

Figs. 3-1, 3-8
PE = 4.5 V

Propagtion Delay
CP to On

25
29

24
27

ns

Figs. 3-1, 3-8
PE = Gnd

tPLH
tPHL

Propagation Delay
CET to TC

16
16

14
23

ns

Figs. 3-1, 3-5

tPHL

Propagation Delay
MR to On ('160 and '161)

38

28

ns

Figs. 3-1, 3-16

f max

Maximum Count Frequency

tPLH
tPHL

Propagation Delay
CP to TC

35
35

tPLH
tPHL

Propagtion Delay
CP to On

tPLH
tPHL

4-219

•

160 • 162
AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54174
Min

ts (H)
ts (U

Setup Time, HIGH or LOW
Pn toCP

th (H)
th (U

Max

54174LS
Min

UNITS

CONDITIONS

Max

20
20

20
20

ns

Hold Time, HIGH or LOW
Pn to CP

0
0

5.0
5.0

ns

ts (H)
ts(U

Setup Time, HIGH or LOW
PE to CP

25
25

25
25

ns

th (H)
th (U

Hold Time, HIGH or LOW
PE to CP

0
0

0
0

ns

ts (H)
ts (U

Setup Time, HIGH or LOW
CEP, CET or SA to CP

20
20

25
25

ns

th (H)
th (U

Hold Time, HIGH or LOW
CEP, CET or SR to CP

0
0

0
0

ns

tw (H)
tw (U

CP Pulse Width, HIGH or LOW

15
25

15
25

ns

Fig. 3-8

tw (U

MR Pulse Width LOW
('160 and '161)

20

15

ns

Fig. 3-16

tree

Recovery Time
MR to CP ('160 and '161)

20

ns

Fig. 3-16

4-220

Fig. 3-6

Fig. 3-6

Fig. 3-6

161 • 163
CONNECTION DIAGRAM
PINOUT A

54/74161 • 54LS/74LS161
54/74163 .54LS/74LS163
SYNCHRONOUS PRESETTABLE
BINARY COUNTERS
DESCRIPTION - The '161 and '163 are high speed synchronous modul0-16
binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage
counters. The '161 has an asynchronous Master Reset input that overrides all
other inputs and forces the outputs LOW. The '163 has a Synchronous Reset
input that overrides counting and parallel loading and allows the outputs to
be simultaneously reset on the rising edge of the clock. For functional
description and detail specifications please refer to the '160 data sheet. For
S-TTL and LP-TTL versions please see the 9316 data sheet.

'MR for '161
'SR for '163

LOGIC SYMBOL
9

3

4

5

6

PE Po p, P2 P3
CEP
10

eET

TC

15

CP

1 14 13 12 11

• SYNCHRONOUS COUNTING AND LOADING
• HIGH SPEED SYNCHRONOUS EXPANSION
• LS VERSIONS FULLY EDGE TRIGGERED

'MR for '161
'SR for '163

STATE DIAGRAM

ORDERING CODE: See Section 9
PIN
PKGS

OUT

Vee = Pin 16
Gnd = Pin 8

COMMERCIAL GRADE

MILITARY GRADE

Vce = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74161 PC, 74LS161PC
74163PC, 74LS163PC

Ceramic
DIP (0)

A

74161DC, 74LS161 DC
74163DC, 74LS163DC

54161DM, 54LS161 OM
54163DM,54LS163DM

78

Flatpak
(F)

A

74161FC,74LS161FC
74163FC, 74LS163FC

54161FM, 54LS161 FM
54163FM,54LS163FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

00-03

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input
(Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-flop Outputs

TC

Terminal Count Output

CEP
CET
CP
MR ('161)
SR ('163)
PO-P3

PE

54/74 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
2.0/2.0
2.0/2.0
1.0/1.0

0.6/0.3
1.0/0.5
0.6/0.3
0.5/0.25

1.011.0
1.0/1.0
1.0/1.0
20/10

0.5/0.25
0.5/0.25
0.6/0.3
10/5.0
(2.5)
10/5.0
(2.5)

20/10

4-221

•

161 • 163
LOGIC DIAGRAMS

'161

TC

'LS161
Po

P3

J

I

E

t

.~

CE

_~
.~

0

J

0

0

CE

, i1c ~~~ ~~r ~
w

CP

...

v

1C~

R

----<>:>

1

f-.r g-.r
D

I

DI
I

K

I LJ

I

DJ
I
I

r

~

D

--.-1

L

I

Q3

Qo

4-222

TC

161 • 163
LOGIC DIAGRAMS

'163
Po

~
~

CEP
CET

I

t

I

e

e
t

t

t

-

~

t

-

•

n
CP

TC

...v

l

I
K CP

~

I

f-

I

I

I

I I

I
t-

f-

00

r-----I

I

I

t-

'LS163
Po

....

I

_

~ I ..
CEP
CET

I

I

d

(j

0

~

r;~ ~

~~ ~
CP

SA

...
;:...

I

CP

LJ

D

I

t
I

~LJ

D

:

I

t
I
LJ

00

4-223

D

I
I

I

I

I

I
LJ

t
D

I
[

~
TC

I

164
CONNECTION DIAGRAM
PINOUT A

54/74164
54LS/74LS164
SERIAL-IN PARALLEL-OUT SHIFT REGISTER
DESCRIPTION - The '164 is a high speed 8-bit serial-in parallel-out shift
register. Serial data is entered through a 2-input AND gate synchronous with
the LOW-to-HI GH transition of the clock. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. It utilizes the Schottky diode clamped process to
achieve high speeds.
•
•
•
•

TYPICAL SHIFT FREQUENCY OF 35 MHz
ASYNCHRONOUS MASTER RESET
GATED SERIAL DATA INPUT
FULLY SYNCHRONOUS DATA TRANSFERS

PIN
OUT

~

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

~vcc

TIlo?

00

IT

~06

01

[I

~05

II
03 II

~04
~MR

GNO[I

~cp

02

ORDERING CODE: See Section 9

PKGS

AIT
alI

PKG
TYPE

Plastic
DIP (P)

A

74164PC, 74LS164PC

Ceramic
DIP (D)

A

74164DC, 74LS164DC

54164DM,54LS164DM

6A

Flatpak
(F)

A

74164FC, 74LS164FC

54164FM, 54LS164FM

31

9A

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
A, B
CP
MR

00-07

DESCRIPTION

54174 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
10/5.0

0.5/0.25

Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs

LOGIC SYMBOL

A

2
8

Vce = Pin 14
GND = Pin 7

y
9

3

4

5

6

4-224

10 11 12 13

0.5/0.25
0.5/0.25
10/5.0
(2.5)

164
FUNCTIONAL DESCRIPTION - The '164 is an edge-triggered 8-bit shift register with serial data entry and an
output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these
inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be
tied HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into 00 the
logical AND of the two data inputs (A • B) that existed before the rising clock edge. A LOW level on the Master
Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all 0 outputs LOW.

MODE SELECT TABLE
OPERATING
MODE

INPUTS
MR A

OUTPUTS

B

00

•

01-07

Reset (Clear)

L

X

X

L

L-L

Shift

H
H
H
H

I
I
h
h

I
h
I
h

L
L
L
H

qo-qs
qo-qs
qo-qs
qo-qs

L (I) = LOW Voltage Levels
H Ih) = HIGH Voltage Levels
X = Immaterial
qn

= Lower case

letters indicate the state of the referenced

input or output one setup time priortothe LOW-to-HIGH clock
transition.

LOGIC DIAGRAM

A

o

B

CP-{>.O+--4-~~--~~~-+--~~~--~--+--+~--~~~-+--~

MR~o---~~----~~---4--~--~--r---+--+----~~---+--4---~
00

a,

05

4-225

a

164
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMTER

~

los

Output Short
Circuit Current

lee

Power Supply Current

AC CHARACTERISTICS: Vee

XC

= +5.0 V,

54174LS
Min

Max

-10
-9.0

-27.5
-27.5

-20
-20

-100
-100

mA

Vee = Max

27

mA

A, B = Gnd, Vee = Max
CP = 2.4 V, MR = S--

= +25°C (See Section 3 for waveforms and
54174

SYMBOL

PARAMETER

Max

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to an

27
32

tPLH
tPHL

Propagation Delay
CP to an

30
37

tPHL

Propagation Delay
MR to an

36

tPHL

Propagation Delay
MR to an

42

SYMBOL

= +5.0 V,

25

TA

PARAMETER

Min

UNITS

CONDITIONS

Max

25

f max

load configurations)

54174LS

CL = 15 pF CL = 15 pF
RL = 800.n
Min

AC CHARACTERISTICS: Vee

CONDITIONS

Max

54

TA

UNITS

Min

27
32

36

MHz

Figs. 3-1, 3-8

ns

Figs. 3-1, 3-8

ns

Figs. 3-1, 3-8
CL = 50 pF

ns

Figs. 3-1,3-16

ns

Figs. 3-1, 3-16
CL = 50 pF

= +25°C
54/74
Min

Max

54/74LS
Min

UNITS

CONDITIONS

Max

ts (H)
ts (U

Setup Time HIGH or LOW
A or B to CP

15
15

15
15

ns

th (H)
th (U

Hold Time HIGH or LOW
A or B to CP

0
0

5.0
5.0

ns

tw (H)
tw (U

CP Pulse Width HIGH or LOW

20
20

20
20

ns

Fig. 3-8

tw (U

MR Pulse Width LOW

20

20

ns

Fig. 3-16

tree

Recovery Time
MR to CP

20

ns

Fig. 3-16

4-226

Fig. 3-6

165
CONN£CTION DIAGRAM
PINOUT A

54/74165
54LS/7 4LS 165
a-BIT PARALLEL-TO-SERIAL CONVERTER
DESCRIPTION - The '165 is an a-bit parallel load or serial-in register with
complementary outputs available from the last stage. Parallel inputing occurs
asynchronously when the Parallel Load (PU input is LOW. With PL HIGH,
serial shifting occurs on the rising edge of the clock; new data enters via the
Serial Data (Os) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable.

PL[!

PIN
PKGS

OUT

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

:EjP3

Ps~

TI]P2

P6~

E]p,

P7[!

:IT] Po

I!

~Ds

GND!:!

]]07

07

MILITARY GRADE

mvcc

lil CP2

P411

ORDERING CODE: See Section 9
COMMERCIAL GRADE

-

cp,[!

TYPE

Plastic
DIP(P)

A

74165PC, 74LS165PC

Ceramic
DIP (0)

A

74165DC, 74LS165DC

54165DM,54LS165DM

68

Flatpak
(F)

A

74165FC, 74LS165FC

54165FM,54LS165FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES

Q7

Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
Asynchronous Parallel Load Input
(Active LOW)
Parallel Data Inputs
Serial Output From Last Stage

Q7

Complementary Output

CP1, CP2
Os
PL
Po-F7

54/74 (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
2.0/2.0

0.5/0.25
0.5/0.25
1.5/0.75

1.0/1.0
20/10

0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

20/10

LOGIC SYMBOL
1 11 12 13 14 3 4

5

6

b I p,I I I I I I I

PL Po

P2 P3 P4 Ps P6 P7

10

Os

07 - 9

1:=D

CP

07

4-227

0-7

Vee = Pin 16
GND = Pin 8

165
FUNCTIONAL DESCRIPTION - The '165 contains eight clocked master/slave RS flip-flops connected as a
shift register with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when
the PLsignal is LOW. The parallel data can change while PL is LOW provided that the recommended setup and
hold times are observed.
For clocked operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock
inhibit by applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH
while the clock is HIGH. Otherwise, the rising inhibit signal will causethesame response as a rising clock edge.
The flip-flops are edge-triggered for serial operations. The serial input data can change at any ti me, provided
only that the recommended setup and hold times are observed, with respect to the riSing edge of the clock.

TRUTH TABLE
CONTENTS

CP
PL

1

2

L
H
H
H
H

X

X
J

Po

..r

00 01
Ds 00
00 01

L
H

...r

...r

L
H

00 01
P1

Ds 00

04

Os

RESPONSE

Os 07

02

03

P2

Ps Ps Pr
03 04 05 Os
03 04 Os Os 07
02 03 04 Os Os
03 04 Os Os 07

01
02
01
02

P3
02

P4

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

cp,
c",

PL-cD------+

4-228

Parallel Entry
Right Shift
No Change
Right Shift
No Change

165
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

I

los

Output Short
Circuit Current

Icc

Power Supply Current

AC CHARACTERISTICS: Vee

l

= +5.0 V,

XM
XC

Min

Max

-20
-18

-55
-55

PARAMETER

Min

TA

36

= +25°C (See Section
CL
RL

= 15 pF
= 400 n

Min

Max

UNITS

CONDITIONS

Max

63

54174

SYMBOL

54174LS

= Max

mA

Vee

mA

Vee = Max, PL =
Pn ="l.. CP1, CP2

= 15

Min

pF

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
PL to 07 or 07

31
40

30
30

ns

Figs. 3-1, 3-16

tPLH
tPHL

Propagation Delay
CP1 to 07 or 07

24
31

30
30

ns

Figs. 3-1, 3-8

tPLH
tPHL

Propagation Delay
P7 to 07

17
36

25
30

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
P7 to 07

27
27

30
25

ns

Figs. 3-1, 3-4

SYMBOL

PARAMETER

= +5.0 V,

30

TA

MHz

Figs. 3-1, 3-8

= +25°C

54/74
Min

Max

54174LS
Min

UNITS

CONDITIONS

Max

ts (H)
ts (Ll

Setup Time HIGH or LOW
Pn to PL

10
10

10
10

ns

th (H)
th (Ll

Hold Time HIGH or LOW
Pn to PL

0
0

5.0
5.0

ns

ts (H)
ts (Ll

Setup Time HIGH or LOW
Ds to CPn

20
20

10
10

ns

th (H)
th (Ll

Hold Time HIGH or LOW
Ds to CPn

0
0

5.0
5.0

ns

ts (H)

Setup Time HIGH
CP1 to CP2 or CP2 to CP1

30

30

ns

tw (H)

CPn Pulse Width HIGH

25

20

ns

tw (Ll

PL Pulse Width LOW

15

15

ns

tree

Recovery Ti me
PL to CPn

45

15

ns

Fig. 3-13

Fig. 3-6

Fig. 3-8
Fig. 3-16

4-229

V

54174LS
CL

Maximum Clock Frequency

AC OPERATING REQUIREMENTS: Vee

= 4.5

3 for waveforms and load configurations)

fmax

20

--u-

•

166
CONNECTION DIAGRAM
PINOUT A

54/74166
a-BIT SHIFT REGISTER
DESCRIPTION - The '166 is an a-bit, serial- or parallel-in, serial-out shift
register using edge triggered D-type flip-flops. Serial and parallel entry are
synchronous, with state changes initiated by the rising edge of the clock.
An asynchronous Master Reset overrides. other inputs and clears all flipflops. The circuit can be clocked from two sources or one CP input can
be used to trigger the other.

osIT

•
•
•
•

P3[I

35 MHz TYPICAL SHIFT FREQUENCY
ASYNCHRONOUS MASTER RESET
SYNCHRONOUS PARALLEL ENTRY
GATED CLOCK INPUT CIRCUITRY

PKGS

OUT

Po II
pdI
P21I

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

GNO[!

PJMA

PKG
TYPE

Plastic
DIP(P)

A

74166PC

Ceramic
DIP (D)

A

74166DC

54166DM

78

Flatpak
(F)

A

74166FC

54166FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

CP1, CP2
Ds
PE
PO-P7

QR
Q7

54/74 (U.L.)
HIGH/LOW

DESCRIPTION

PIN NAMES

Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
Parallel Enable Input (Active LOW)
Parallel Data Inputs
Asynchronous Master Reset Input (Active LOW)
Last Stage Output

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.011.0
20/10

LOGIC SYMBOL
15 2

1-

:::J;"
6

~

3

4 5 10 11 12 14

!IIIIIIII

PE Po p, P2 P3 P4 Ps Pa P7
Os

CP
MA

07

!

1l
4-230

Vee = Pin 16
GND = Pin 8

~vcc
~PE
~P7
~07
~Pa

rm p5
rm p4

CP2[I
cp,[!

ORDERING CODE: See Section 9
PIN

-

166
FUNCTIONAL DESCRIPTION - Operation is synchronous (except for Master Reset) and state changes are
initiated by the rising edge of either clock input if the other clock input is LOW. When one of the clock inputs is
used as an active HIGH clock inhibit. it should attain the HIGH state while the other clock is still in the HIGH
state following the previous operation. When the Parallel Enable (PE) input is LOW. data is loaded into the
register from the Parallel Data (Po - P7) inputs on the next rising edge of the clock. When PE is HIGH.
information is shifted from the Serial Data (Os) input to 00 and all data in the register is shifted one bit position
(i.e .• 00-+0,. 0,-+02. etc') on the rising edge of the clock.

MODE SELECT TABLE
INPUTS
MR PE

RESPONSE

CP,

CP2

L

X

X

X

Asynchronous Reset; On = LOW

H
H

X
X

H*
X

X
H*

Hold

H
H

L
L

L
J'

J

H
H

H
H

L
J'

f

I

Parallel Load; Pn-+On

L
Shift;

Ds~

00.00--0,. etc.

L

"The HIGH signal on one CP input must be established
while the other CP input is HIGH.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

4-231

•

166
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min
lee

UNITS

CONDITIONS

mA

Vee = Max, CPl = .....rOs = 4.5 V
CP2, MR, PE, Pn = Gnd

Max

Power Supply Current

127

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C (See Section 3 for waveforms and load configurations)

54174
SYMBOL

PARAMETER

CL = 15 pF
RL=400n
Min

UNITS

CONDITIONS

Max

25

f max

Maximum Clock Frequency

MHz

tPLH
tPHL

Propagation Delay
CPn to 07

26
30

ns

tPHL

Propagation Delay
MR to 07

35

ns

Figs. 3-1, 3-8

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA= +25°C
SYMBOL

54174

PARAMETER

Min

UNITS

CONDITIONS

Max

ts (H)
ts (U

Setup Time HIGH or LOW
Os or Pn to CPn

20
20

ns

th (H)
th (L)

Hold Time HIGH or LOW
Os or Pn to CPn

0
0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
PE to CPn

30
30

ns

th (H)
th (L)

Hold Time HIGH or LOW
PE to CPn

0
0

ns

tw (H)

CPn Pulse Width HIGH

20

ns

Fig. 3-8

tw (U

MR Pulse Width LOW

20

ns

Fig. 3-16

4-232

Fig. 3-6

167
CONNECTION DIAGRAM
PINOUT A

54/74167
~

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION - The '167 contains a synchronous decade counter and four
decoding gates that serve to gate the clock through to the output at a submultiple of the clock frequency. The output pulse rate, relative to the clock
frequency, is determined by signals applied to the Select (So - Sa) inputs.
Both true and complement outputs are available, along with an enable input
for each. A Count Enable input and a Terminal Count output are provided
for cascading two or more packages. Asynchronous Master Reset and Master
Set inputs prevent counting and clear the counter or set it to maximum,
respectively.

NCrr

~vcc

sdI

ms,

S3[!

:Elso

MS[1

E]MR

azl]:

TIlEy

OyE!

]]CE

TC[!:

~Ez

GND[!

}]cp

LOGIC SYMBOL

4

11--0

ORDERING CODE: See Section 9

9-

PIN
PKGS

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

OUT

Plastic
DIP(P)

A

74167PC

Ceramic
DIP (0)

A

74167DC

Flatpak
(F)

A

74167FC

PKG
TYPE

14 15 2

3

I I I I I

10~

12-

MS So S1 S2 S3
CE
CP
TC 0-7
Ez
Ey
MR
oz Oy

!!

9B

1l

54167DM

7B

Vee = Pin 16
GND = Pin 8

54167FM

4L

INPUT LOADING/FAN-OUT: See Sectiol'1 3 for U.L. definitions
DESCRIPTION

PIN NAMES
So-S3

E.z

Ey
CE
CP
MS
MR

Oz
Oy
TC

Rate Select Inputs
Enable Input (Active LOW)
Oy Enable Input
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Set Input (Active HIGH) (Set to 9)
Asynchronous Master Reset Input (Active HIGH)
Gated Clock Output (Active LOW)
Complement Output (Active HIGH)
Terminal Count Output (Active LOW)

Oz

4-233

54174 (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
2.0/2.0
1.0/1.0
1.0/1.0
10/10
10/10
10/10

167

o
..,

...u

tI)

a

...

U

lIO:

0

U

1

I~

...u

UI

::I!

4-234

a:

::I!

167
TRUTH TABLE
INPUTS

OUTPUTS
CLOCK
PULSES Ey

MR CE

EZ

S3

S2

Sl

So

H
L
L
L

X
L
L
L

H
L
L
L

X
L
L
L

X
L
L
L

X
L
L
H

X
L
H
L

10
10
10

H
H
H
H

L
L

H
H

1
2

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
H
H
H

H
L
L
H

H
L
H
L

10
10
10
10

H
H
H
H

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
H
H
H
H

H
L
L
L
L

H
L
L
H
H

H
L
H
L
H

10
10
10
10
10

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

H
H
H
H
H

H
H
H
H
L

L
L
H
H
L

L
H
L
H
H

10
10
10
10
10

X

Oy Oz TC

NOTES

1
2

1
1
1

1
2
2
2

3
4
5
6

3
4
5
6

1
1
1
1

2
2
2
2

H
H
H
H
H

7
8
9
8
9

7
8
9
8
9

1
1
1
1
1

2
2
2
2,3
2, 3

H
H
H
H
L

8
9
8
9
H

8
9
8
9
9

1
1
1
1
1

2,3
2,3
2,3
2,3

H

4

1. This is a simplified illustration of the clear function. CP and E.z also affectthe logic level of Oy and Oz.
A LOW signal on Ey will cause Oy to remain HIGH.
2. Each rate illustrated assumes So- S3 are constant throughtout the cycle; however, these illustrations in no way prohibit variable-rate operation.
3. These input condtions exceed the range of the decade rate Select inputs.
4. Ey can be used to inhibit output Oy.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

PULSE PATTERN TABLE
PULSE PATTERN

S3

S2

Sl

So

m

Oz

L
L
L
L

L
L
L
H

L
H
H
L

H
L
H
L

1

1 1 1 101 1 1 1
1 101 1 1 101
1 101 0 1 101
10101 101 0

1
1
1
1

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

10100
1 000 1
1 0 0 0 0
o 000 1
o0 0 0 0

1
1
1
1
1

2
3
4

5
6
7

8
9

H = HIGH Voltage Level
L = LOW Voltage Level

4-235

1
1
1
0
0

0 1 0
000
000
0 0 0
0 0 0

•

167
FUNCTIONAL DESCRIPTION - The '167 contains four JK flip-flops connected as a synchronous decade
counter with a count sequence of 0-1-2-3-4-8-9-10-11-12. A LOWsignal ontheCount Enable(CEl input permits
cou nting, with all state changes initiated si multaneously by the rising edge of the clock. When the count reaches
maximum (12) the Terminal Count (TC) output goes LOW if CE is LOW. A HIGH signal on Master Reset ~R)
clears the flip-flops and prevents counting, although output pulses can still occur if the clock is running, Ez is
LOW and Sa is HIGH. A HIGH signal on Master Set (MS) prevents counting and sets the counter to 12, the only
state in which no output pulses can occur.
The flip-flop outputs are decoded by a 4-wideAND-OR-INVERT gate. Each AND gate also contains the buffered
and inverted CP and Z-enable (Ez) functions, as well as one of the Select (So - Sa) inputs. The Z output Oz is
normally HIGH and goes LOW when CP and Ez are LOWand any of the AND gates has its other inputs HIGH.
The AND gates are enabled at different times and different rates relative to the clock. For example, the gate to
which 50 is connected is enabled only when the counter is in state five, assuming that So is HIGH. Thus, during
one complete cycle of the counter (10 clocks) the So gate can contribute only pulse to the output rate. The 51
gate is enabled twice per cycle, the S2 gate fourtimes per cycle(etcJ. The output pulse rate thus depends on the
clock 'rate and which of the So -S3 inputs are HIGH, as expressed in the following formula.

fout =m. fin

where m

= S3 •

10
23

+ 52 •

22

+ 51

• 21

+ So •

20

Thus by appropriate choice of signals applied to the So - Sa inputs, the output pulse rate can range from 1/10 to
9/10 of the clock rate. The select codes, m values and Oz pulse pattern are shown in the Pulse Pattern Table. In
the Oz pattern, each column represents a clock period, with the state-12 column on the right. A one indicates
that the Oz output will be HIGH during that entire clock period, while azeroindicatesthatOz will beLOWwhen
the clock is LOW during that period. Note that the output pulses are evenly spaced only when m is one or two,
assuming that the clock frequency is constant, and that no output pulses can occur in state 12 of the counter.
The V output Oy is the complement of Oz and is thus normally LOW. A LOW signal on the V-enable input Ey
disables Oy. To expand the multiplier to 2-digit rate select, two packages can be cascaded as shown in Figure a.
Both circuits operate from the basic clock, with the i'C output of the first acting to enable both counting and the
output pulses of the second package. Thus the second counter advances at only 1/10 the rate of the first and a
full cycle of-the two counters combined requires 100 clocks. Output pulses contributed by the second counter
occur only when the first counter is in state 12. All output pulses are opposite in phase to the clock.

MSB

ENABLE

tt Lt

LSB

So S, S2 S3

CE

r - CP

#1

TC

1I I I
So S, S2 S3

H

CE
; - - - CP

'-- --c Ez

lEY

Oz

#2

Ez

oy

I

I

L-----I~

CLOCK
fin

Fig. a

Cascading for 2-Dlglt Rate Select

4-236

lou,

167
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
los
Icc

54174

PARAMETER
Output Short Circuit Current

UNITS

Min

Max

-18

-55

Power Supply Current

99

CONDITIONS

mA

Vee = Max

mA

Vee = Max; MS = Gnd
Other Inputs = 4.5 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174

SYMBOL

PARAMETER

CL = 15 pF
RL = 400 n
Min

UNITS

Max

fmax

Maximum Clock Frequency

tpLH
tPHL

Propagation Delay
CP to TC

25
30
33

ns

tPLH
tPHL

Propagation Delay
Ez to Oy

30
33

ns

tPLH
tPHL

Propagation Delay
Ey to Ov

14
10

ns

tPLH
tPHL

Propagation Delay
Sn to Oz

14
10

ns

tPLH
tPHL

Propagation Delay
CP to Oy

39
30

ns

tPLH
tPHL

Propagation Delay
Ez to Oz

18
23

ns

tPLH
tPHL

Propagation Delay
Sn to Oy

23
23

ns

tpLH
tPHL

Propagation Delay
CP to Oz

18
26

ns

tPLH
tPHL

Propagation Delay
CE to TC

20
21

ns

tPHL

Propagation Delay
MS to TC

27

ns

tPLH

Propagation Delay
MR to Oy

36

ns

tPHL

Propag!!.!!.on Delay
MR TO Oz

23

ns

4-237

CONDITIONS

MHz

Figs. 3-1, 3-8

Figs. 3-1, 3-4

Figs. 3-1, 3-5

Figs. 3-1, 3-16

•

167
AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

= 25°C

TA

54/74

PARAMETER

UNITS

Min

CONDITIONS

Max

ts(U

Setup Time LOW
CE to CP Rising

25

th (H)

Hold Time HIGH
CE to CP Rising

0

tw CP-10

ns

ts(U

Setup Time LOW
CE to CP Falling

0

tw CP-10

ns

th (U

Hold Time LOW
CE to CP Falling

20

tinh (H)

Inhibit Time HIGH
CE to CP Falling

10

ns

Fig. b

tw (H)

CP Pulse Width HIGH

20

ns

Fig. 3-8

tw (H)

MR Pulse Width HIGH

15

ns

tw (H)

MS Pulse Width HIGH

15

ns

~

,

ns
Fig. b

Fig. c

~

T-10

,

.....
I+-

ts(L) .....

~

CP

Fig. 3-16

_ _ DISABLED----....,

ENABLED-----..,.

\

ns

'--'..

.("",

Vm

,

I*- tinn(H)

~

1\

J

I

Vm

= 1.5V

~twCP_

Fig. b

_ _ DISABLED---...,,---ENABLED

....

~,,} -~, f", ,

Ci

I

CP

---'

~
T

;4-twCP

Fig. c

4-238

Vm

= 1.5V

~

168
CONNECTION DIAGRAM
PINOUT A

54LS/74LS168
SYNCHRONOUS BI-DIRECTIONAL
BCD DECADE COUNTER

-

utilE

~vcc

CP[!

liJfC

Pol!

:moo

P1[!

}i]01

P21!

:rn02

P31!

03

m

CEP[!

:mCET

GNO[!

]]PE

DESCRIPTION - The '168 is a fully synchronous 4-stage up/down counter
featuring a preset capability for programmable operation, carry lookahead for
easy cascading and a U/O input to control the direction of counting. It counts
in the BCD (8421) sequence and all state changes, whether in counting
or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.

LOGIC SYMBOL

1iii i
PE Po P, P2 P3

1-

ORDERING CODE: See Section 9
PIN
PKGS

OUT

utO

7---.
1) Count Enable = CEP • CET • PE
Up: TC = 00 .03. (UiO) • CET
3) Down: TC = 00 • 01 • 02 • 03. (UfO) • CET

2)

STATE DIAGRAM
54LS/74LS168

'168 and '169 MODE SELECT TABLE
PE

CEP CET UfD

Action on Rising Clock Edge

L
H
H
H
H

X
L
L
H
X

Load (Pn---On)
Count Up (increment)
Count Down (decrement)
No Change (Hold)
No Change (Hold)

X
L
L
X
H

X
H
L
X
X

H = HIGH Vollage Level
L = LOW Vollage Level
X = Immaterial

---!.~

- - __

Count Up
Count Down

LOGIC DIAGRAM

IJJ
CEP
CET

P,

P,

CJ

CJ

!D

UIO

~

l6

IU

- b 1~
leI
rr
,u, l{
L
~
U L
~ 4f-

I~

r-

CP

..

~?

~r

~J, 1.1.

lR-RD,

D,

I

Of

RD,

4-240

tl
t;J Ii

L

;~
leE

..I.I~

D,

I'"""

~

168
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74LS

PARAMETER
Min

lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

UNITS
34

TA

CONDITIONS

Max

= +25°C (See Section

rnA

Vee

= Max

3 for waveforms and load configurations)

54174LS
SYMBOL

CL

PARAMETER

= 15

pF

Min
f max

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to an

tPLH
tPHL

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-8

20
20

ns

Figs. 3-1,3-8

Propagation Delay
CP to TC

30
30

ns

Figs. 3-1, 3-8

tPLH
tPHL

Propagation Delay
CET to TC

15
20

ns

Figs. 3-1,

tPLH
tPHL

Propagation Delay
UfO to TC

25
25

ns

Figs. 3-1, 3-20

AC OPERATING REQUIREMENTS: Vee
SYMBOL

25

= +5.0 V,

TA

3~5

= +25°C
54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time HIGH or LOW
Pn, CEP or CET to CP

15
15

ns

Fig. 3-6

th (H)
th (U

Hold Time HIGH or LOW
Pn, CEP or CET to CP

5.0
5.0

ns

Fig. 3-6

ts (H)
tg(U

Setup Time HIGH or LOW
PE to CP

20
20

ns

Fig. 3-6

th (H)
th (U

Hold Time HIGH or LOW
PE to CP

0
0

ns

Fig. 3-6

ts (H)
ts (U

Setup Time HIGH or LOW
UfO to CP

25
25

ns

Fig. 3-6

th (H)
th (U

Hold Time HIGH or LOW
UfO to CP

0
0

ns

Fig. 3-6

tw (H)
tw (U

CP Pulse Width HIGH or LOW

10
20

ns

Fig. 3-8

4-241

•

169
CONNECTION DIAGRAM
PINOUT A

54LS/74LS169
SYNCHRONOUS BI-DIRECTIONAL
MODULO-16 BINARY COUNTER

-

U/oIT

~vcc
~TC
~oo

cplI
Po

II

~o,

p, [!

~02
~03

P2[!
P31!
CEPIT

~CET

GNO[!

~PE

DESCRIPTION - The '169 is a fully synchronous 4-stage up/down counter
featuring a preset capability for programmable operation, carry lookahead for
easy cascading and a UfO input to control the direction of counting. All state
changes, whether in counting or parallel loading, are initiated by the LOW-toHIGH transition of the clock. For a functional description and detail specifications, please refer to the '168 data sheet.

LOGIC SYMBOL

1iii i
PE Po

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
Vee

TA

= +5.0 V ±5%,

= O°C to +70°C

MILITARY GRADE

= +5.0 V ±10%,
= -55°C to +125°C

Vee

TA

PKG
TYPE

Plastic
DIP(P)

A

74LS169PC

Ceramic
DIP (D)

A

74LS169DC

54LS169DM

68

Flatpak
(F)

A

74LS169FC

54LS169FM

4L

98

17-

I

LJ

I

11

,

~rf~

.I.

~

I

LJ'

LJ

Q,

h

Q,

Q,

STATE DIAGRAM

MODE SELECT TABLE
PE

CEP CET UfO

L
H
H
H
H

X
L
L
H
X

X
L
L
X
H

X
H
L
X
X

Action on Rising Clock Edge
Load (P n - a n )
Count Up (increment)
Count Oown (decrement)
No Change (Hold)
No Change (Hold)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

~

4-243

-

COUNT UP
COUNT DOWN

•

170
CONNECTION DIAGRAM
PINOUT A

54/74170
54lS/7 4LS 170
4

x4

REGISTER FILE

(With Open-Collector Outputs)

DESCRIPTION - The '170 contains 16 high speed, low power, transparent
D-type latches arranged as four words of four bits each, to function as a
4 X 4 register file. Separate read and write inputs, both address and enable,
allow simultaneous read and write operation. Open-collector outputs make
it possible to connect up to 128 outputs in a wired-AND configuration
to increase the word capacity up to 512 words. Any number of these devices
can be operated in parallel to generate an n-bit length. The '670 provides
a similar function to this device but it features 3-state outputs.
LOGIC SYMBOL
•
•
•
•

SIMULTANEOUS READ/WRITE OPERATION
EXPANDABLE TO 512 WORDS OF n-BITS
TYPICAL ACCESS TIME OF 20 ns
LOW LEAKAGE OPEN-COLLECTOR OUTPUTS FOR EXPANSION

12

14

ORDERING

CODE~

PIN
PKGS

OUT

See Section 9

13

15

1

WE 0,
WAo

02

2

WA,
RAo

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

4

RA1

TYPE

RE

9B

11

Plastic
DIP (P)

A

74170PC, 74LS170PC

Ceramic
DIP (0)

A

74170DC, 74LS170DC

54170DM,54LS170DM

7B

Flatpak
(F)

A

74170FC, 74LS170FC

54170FM,54LS170DM

4L

10

9

7

6

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
01-04
WAo, WA1
WE
RAo, RA1
RE
01-04

54174 (U.L.)

DESCRIPTION

HIGH/LOW

Data Inputs
Write Address Inputs
Write Enable Input (Active LOW)
Read Address Inputs
Read Enable Input (Active LOW)
Data Outputs

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
OC* 110

'OC-Open Colleclor

4-244

54174LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
1.010.5
0.5/0.25
1.010.5
OC*/5.0
(2.5)

170
LOGIC DIAGRAM

~
WAo

-

to.

I
~7

~~~----+-~----~--~-----+~

"""

o I~

(j IW~RD

IGaO

IGaO

IIL--_--I--.

I

~J

I

G

r~W~~RD--I--J
Q

0

RE--<

RAo

~--

------<~>l..........I_)-

READ FUNCTION TABLE

WRITE FUNCTION TABLE
WRITE INPUTS
WE

WA,

WAo

L
L
L
L
H

L
L
H
H

L
H
L
H
X

X
H

= HIGH

READ INPUTS

o INPUTS TO
Word 0
Word 1
Word 2
Word 3
None (hold)

Voltage Level

L

= LOW Voltage

4-245

RE

RA,

RAo

L
L
L
L
H

L
L
H
H
X

L
H
L
H
X

Level

OUTPUTS FROM
Word 0
Word 1
Word 2
Word 3
None (HIGH Z)

x = Immaterial

170
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min
IOH

Output HIGH Current
Power Supply Current

lee

XC
- XM

54174LS

Max

Min

UNITS

CONDITIONS

Max

30

20

150

40

140

40

J.LA
mA

Vcc = Min, VOH = 5.5 V
iVee = Max; On, WE,
JRE = 4.5 V; WAn, RAn =Gnd

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25 0 C (See Section 3 for waveforms and load configurations)

54/74
SYMBOL

PARAMETER

54174LS

CL=15pF CL = 15 pF
RL = 400 n
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay'
RAo or RA1 to On

35
40

35
35

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
RE to On

15
30

30
30

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
WE to On

40
45

35
35

ns

Figs. 3-1, 3-9

tpLH
tPHL

Propagation Delay
On to On

30
45

35
35

ns

Figs. 3-1, 3-5

'Measured at least 25 ns after entry of new data at selected location.
AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25 0 C
SYMBOL

PARAMETER

54174
Min

Max

54/74LS
Min

UNITS

Is

Setup Time HIGH or LOW
On to rising WE

10

10

ns

th

Hold Time HIGH or LOW
On to rising WE

15

5.0

ns

ts

Setup Time HIGH or LOW
WAn to falling WE

15

10

ns

th

Hold Time HIGH or LOW
WAn to rising WE

5.0

5.0

ns

tw (U

WE or RE Pulse Width LOW

25

25

ns

Fig. a
4-246

CONDITIONS

Max

Fig. a

173
CONNECTION DIAGRAM
PINOUT A

54/74173
54LS/74LS173

-

OE1IT

4-BIT 0-TYPE REGISTER
(With 3-State Outputs)

OE,

[I

00

IT

:ill Vee
:ill MR
~oo

1m

018:

DESCRIPTION - The '173 is a high speed 4-bit register featuring 3-state
outputs for use in bus-organized systems. The clock is fully edge-triggered
allowing either a load from the D inputs or a hold (retain register contents)
depending on the state of the Input Enable lines (1E1, iE2l. A HIGH on
either Output Enable line (OE1, OE2) brings the output to a high impedence
state without affecting the actual register contents. A HIGH on the Master
Reset (MR) input resets the register regardless of the state of the Clock
(CP), the Output Enable (OE1, OE2) or the Input Enable (1E1, IE2) lines.

01

0,

IT

03

[I

~O'
~03

cpIT

~iE'

GNO[!

~iE1

LOGIC SYMBOL

8

• FULLY EDGE-TRIGGERED
• 3-STATE OUTPUTS
• GATED INPUT AND OUTPUT ENABLES

"U""

1

ORDERING CODE: See Section 9
PIN
PKGS

OUT

2

Do 0, 0, 03

IE

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

7

CP

1~=m
--<> 2

OE

2

MR 00

Plastic
DIP(P!

A

74173PC, 74LS173PC

Ceramic
DIP (0)

A

74173DC, 74LS173DC

Flatpak
(F)

A

98

,15
54173DM,54LS173DM

78

01

0,

!!!!

Vee = Pin 16
GND = Pin 8
74173FC, 74LS173FC

54173FM, 54LS173FM

4L

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Do-.23
IE1,IE2
OE1, OE2
CP
MR
00-03

54174 (U.L.)

DESCRIPTION
Data Inputs
Input Enable Inputs (Active LOW)
3-State Output Enable Inputs
(Active LOW)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master'Reset Input
(Active HIGH)
3-State Outputs

4-247

03

HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25
0.5/0.25

1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25

130/10
(50)

65/5.0
(25)/(2.5)

•

173
TRUTH TABLE
INPUTS

OUTPUT

MR CP IE1

IE2

Dn

X
X
H

X
X
X

X
X
X

X
L
L

H
L
L

X
L
H

H
L
L

L
L
L

X
L

S
S
S

..r

an

L
an
an
an

L
H

When either 0E1 or 01:2 are HIGH, the output
is in the OFF statelhigh impedenacel; however
this does not affect the contents or sequential
operating of the register.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
Do

1E1----

ffi, --~L_~1I~---jIt------------IIr_----------_t1l------------tl

CP

Co
Q

Q

Co

Co

Co
Q

Q

Q

Q

Q

MR

OE1
OE,
00

0,

02

4-248

03

Q

173
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

los

Output Short Circuit Current

Icc

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0

Min

Max

-30

-70

-20

-100

mA

28

mA

72

V, TA

PARAMETER

UNITS

Max

= +25°C (See Section
54174

SYMBOL

54174LS

Min

CL
RL

= 50 pF
= 400 0

Min

Max

25

CONDITIONS

= Max
Vee = Max,
Vee

MR = L
CP, OE1 = 4.5 V
OE2, iE1, 1E2, Dn = Gnd

3 for waveforms and load configurations)

54174LS
CL

= 15 pF

Min

UNITS

CONDITIONS

Max

fmax

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to On

43
31

40
25

ns

tPHL

Propagation Delay, MR to On

27

25

ns

Figs. 3-1, 3-16

tpzH
tPZL

Output Enable Time

30
30

20
20

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kO ('LS173)

tPHZ
tPLz

Output Disable Time

14
20

16
16

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kO ('LS173)
CL = 5 pF

AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0 V,

30

TA

Figs. 3-1, 3-8

= +25°C

54/74
Min

MHz

Max

54/74LS
Min

UNITS

t5 (H)
t5 (U

Setup Time HIGH or LOW
Dn to CP

10
10

10
10

ns

th (H)
th (U

Hold Time HIGH or LOW
Dn to CP

10
10

10
10

ns

t5 (H)
t5 (U

Setup Time HIGH or LOW
iE to CP

17
17

17
17

ns

th (H)
th (U

Hold Time HIGH or LOW
IE to CP

2.0
2.0

2.0
2.0

ns

tw (U

CP Pulse Width LOW

20

17

ns

tw (H)

MR Pulse Width HIGH

20

17

ns

tree

Recovery Time, MR to CP

10

15

ns

4-249

CONDITIONS

Max

Fig. 3-6

Fig. 3-8
Fig. 3-16

•

174
CONNECTION DIAGRAM
PINOUT A

54/74174
54S/74S174

54LS/74LS174

Mlil}

HEX D FLIP-FLOP

aol1

-

:ill Vee

oo[l

ma
m0 5

01~

:ill 04

a, []:

D1la4

5

a2[!

~03
~a3

GNO!:!

~cp

02[!

DESCRIPTION - The '174 is a high speed hex 0 flip-flop. The device is
used primarily as a 6-bit edge-triggered storage register. The information
on the 0 inputs is transferred to storage during the LOW-to-HIGH clock
transition. The device has a Master Resetto simultaneously clear all flip-flops.

• EDGE-TRIGGERED D-TYPE INPUTS
• BUFFERED POSITIVE EDGE-TRIGGERED CLOCK
• ASYNCHRONOUS COMMON RESET

3

PKGS
Plastic
OIP(P)

OUT

6 11 13 14

4

I I III I
DO 0, 02 03 04 05
9 - cp

ORDERING CODE: See Section 9
PIN

LOGIC SYMBOL

1-(l MR

ao a, a2 a3 a4 a5

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

A

74174PC,
74S174PC, 74LS174PC

Ceramic
DIP (0)

A

741740C,
74S1740C, 74LS1740C

541740M,
54S1740M,54LS1740M

68

Flatpak
(F)

A

74174FC,
74S174FC, 74LS174FC

54174FM,
54S174FM,54LS174FM

4L

! ! ! lllllt

98
Vcc

= Pin 16
= Pin 8

GND

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
00-05
CP
~
00-05

DESCRIPTION
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Flip-Flop Outputs

4-250

54/74 (U.L.)
HIGH/LOW

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
20/10

1.25/1.25
1.25/1.25
1.25/1.25
25/12.5

0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

174
FUNCTIONAL DESCRIPTION - The '174 consists of six edge-triggered 0 flip-flops with individual 0 inputs
and a outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each- 0 input's state is
transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A LOW
input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The '174 is useful
for applications where the true output only is required and the Clock and Master Reset are common to all
storage elements.

TRUTH TABLE
OUTPUTS

INPUTS
@ tn, MR = H

@ tn

On

an

H
L

H
L

+ 1

•

In = Bit time before positive"going clock transition

tn

+1

= Bit time after positive-going clock transition

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

MR

CP

05

Do

03

o

o

0

o

o

0

o

o

CP

co

05

03

4-251

00

174
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54174
Min

lee

Power Supply Current

Max

54174S
Min

65

Max

54174LS
Min

144

UNITS

CONDITIONS

Max
26

mA

Vee = Max
On = MR = 4.5 V
CP=...r-

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C (See Section 3 for waveforms and load configurations)
54/74
SYMBOL

PARAMETER

54174S

54174LS

CL = 15 pF CL = 15 pF CL = 15 pF
RL = 400 n RL = 280 n
Min

Max

25

Min

Max

f max

Maximum Clock Frequency

75

tpLH
tPHL

Propagation Delay
CP to an

30
35

12
17

tPHL

Propagation Delay
MR to an

35

22

Min

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-8

25
22

ns

Figs. 3-1, 3-8

35

ns

Figs. 3-1, 3-16

UNITS

CONDITIONS

30

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54174
Min

Max

54/74S
Min

Max

54174LS
Min

Max

ts (H)
ts (U

Setup Time HIGH or LOW
On to CP

20
20

5.0
5.0

10
10

ns

th (H)
th (U

Hold Time HIGH or LOW
On to CP

5.0
5.0

3.0
3.0

5.0
5.0

ns

tw (H)

CP Pulse Width HIGH

20

7.0

18

ns

tw (U

MR Pulse Width LOW

20

7.0

18

ns

tree

Recovery Time MR to CP

25

5.0

12

ns

4-252

Fig. 3-6

Fig. 3-8
Fig. 3-16

175
CONNECTION DIAGRAM
PINOUT A

54/74175
54S/74S175

~vcc
~a3
~O3

~

MFiD:

54LS/74LS175

ao 11
oo[l

QUAD D FLIP-FLOP

tm 03

008

~D2

o,~

Q,[!
DESCRIPTION - The '175 is a high speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are commono The information on the D inputs is stored during the LOW-to-HIGH
clock transition. 80th true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, independent of the Clock
or D inputs, when LOW.

tTIJ02

a, IT

~a2

GNO[!

t2JCP

LOGIC SYMBOL
•
•
•
•

EDGE-TRIGGERED D-TYPE INPUTS
BUFFERED POSITIVE EDGE-TRIGGERED CLOCK
ASYNCHRONOUS COMMON RESET
TRUE AND COMPLEMENT OUTPUT

i i

9-

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

A

74175PC, 74S175PC
74LS175PC

Ceramic
DIP (D)

A

74175DC, 74S175DC
74LS175DC

54175DM,54S175DM
54LS175DM

68

A

74175FC, 74S175FC
74LS175FC

54175FM,54S175FM
54LS175FM

4L

Do

0,

1r

0,

03

1-<1 MR

ao ao a, a, a, a2 a3 a3

errrrrTfT
3

Plastic
DIP(P)

Flatpak
(F)

cp

112

2

6

7 11 10 14 15

98

Vce

= Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

Do-D3
CP
MR
00-03

Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
True Outputs

00-Q3

Complement Outputs

4-253

54/74 (U.L.)
HIGH/LOW

54174S (U.L.)

1.0/1.0
1.0/1.0
1.0/1.0
20/10

1.25/1.25
1.25/1.25
1.25/1.25
25/12.5

20/10

25/12.5

HIGH/LOW

54/74LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

•

175
FUNCTIONAL DESCRIPTION - The '175 consists of four edge-triggered 0 flip-flops with individual 0 inputs
and a and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their
individual 0 inputs on the LOW-to-HIGH clock (CPl transition, causing individual a and Q outputs to follow. A
LOW input on the Master Reset (MRl will force all a outputs LOWandQ outputs HIGH independent of Clock or
Data inputs. The '175 is useful for general logic applications where a common Master Reset and Clock are
acceptable.

TRUTH TABLE
INPUTS

OUTPUTS

@ tn, MR = H

tn
tn

= Bit
+ 1

@ tn

+ 1

On

an

an

L
H

L
H

H
L

time before clock posltlve-gomg transition
after clock positive-going transition

= Bit time

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

MR

CP

D3

Do

00 00

4-254

175
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54174
Min

lee

Power Supply Current

Max

54174S
Min

45

Max

54174LS
Min

96

UNITS

CONDITIONS

Max
18

mA

Vee = Max
Dn = MR = 4.5 V
CP =.r--

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174
SYMBOL

PARAMETER

54174S

54174LS

CL = 15 pF CL=15pF CL = 15 pF
RL = 400 n RL = 280 n
Min

Max

25

Min

Max

fmax

Maximum Clock Frequency

tPLH
tpHL

Propagation Delay
CP to On

30
35

12
17

tPHL

Propagation Delay
MR to On

35

tPLH

Propagation Delay
MR to an

25

75

Min

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-8

25
25

ns

Figs. 3-1, 3-8

22

33

ns

Figs. 3-1, 3-16

15

24

ns

Figs. 3-1, 3-16

54174S

54/74LS

UNITS

CONDITIONS

30

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54174
Min

Max

Min

Max

Min

Max

ts (H)
ts(U

Setup Time HIGH or LOW
Dn to CP

20
20

5.0
5.0

10
10

ns

th (H)
th (U

Hold Time HIGH or LOW
Dn to CP

5.0
5.0

3.0
3.0

5.0
5.0

ns

tw (H)

CP Pulse Width HIGH

20

7.0

15

ns

Fig. 3-8

tw (U

MR Pulse Width LOW

20

7.0

18

ns

Fig. 3-16

tree

Recovery Ti me
MR to CP

25

5.0

12

ns

Fig. 3-16

4-255

Fig. 3-6

•

176
CONNECTION DIAGRAM
PINOUT A

54/74176
PRESETTABLE DECADE COUNTER
pL

DESCRIPTION - The '176 is a presettable decade ripple cou nter partitioned
into divide-by-two and divide-by-five sections, with separate clock inputs for
the two sections. It can be connected to operate either in a BCD (8421)
sequence or in a bi-quinary sequence producing a 50% duty cycle output.
A LOW signal on the Master Reset (MR) input overrides all other inputs and
forces the 0 outputs LOW. A LOW signal on the Parallel Load (PU input
causes the 0 outputs to assume the state of their respective Parallel Data(Pn)
inputs, regardless of the clock. In the counting mode, state changes are initiated by the falling edge of the clock.

IT

TIl Vee

~

od:!

TIlMR

pd}

:ill 03

Pori

TIl P3

oorr

~P1

CP1[!

]]01

GNO[I

~cpo

LOGIC SYMBOL

1

4 10

3 11

~

IIII

PL Po P, P2 P3
8--<: cPo
ORDERING CODE: See Section 9
PIN
PKGS

OUT

6--<: CP,

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA=-55°Cto+125°C

PKG
TYPE

Plastic
DIP (P)

A

74176PC

Ceramic
DIP (D)

A

74176DC

54176DM

6A

Flatpak
(F)

A

74176FC

54176FM

31

MR

00 0, 0203

~

IIII

13 5

9

2 12

9A
Vee = Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CPo
CP1
MR
PO-P3
PL
00-03
·Qo

DESCRIPTION
+2 Section Clock Input (Active Falling Edge)
+5 Section Clock Input (Active Falling Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Flip-flop Outputs'

is guaranteed to drive

CP1

in addition to the full rated load.

4-256

54174 (U.L.)
HIGH/LOW
2.0/3.0
3.0/3.0
2.0/2.0
1.0/1.0
1.0/1.0
20/10

176
FUNCTIONAL DESCRIPTION - The '176 is an asynchronously presettable decade ripple cou nter partitioned
into divide-by-two and divide-by-five sections. In the counting modes, state changes are initiated by the HIGHto-LOW transition of the clock signals. State changes of the Q outputs, however, do not occur simultaneously
because of the internal ripple delays. When using external logic to decode the Q outputs, designers should bear
in mind that the unequal delays can lead to decoding spikes and thus a decoded signal should not be used as a
clock or strobe. The CPo input serves the Qo flip-flop while the CP1 input serves the divide-by-five section. The
Qo output is designed and specified to drive the rated fan-out plus the CP1 input.
The '176 can be connected up to operate in two different count sequences. With the input frequency co nnected
to CPo and with Qo driving CP1, the circuit counts in the BCD (8421) sequence. With the input frequency
connected to CP1 and Q3 driving CPo, 00 becomes the low frequency output and has a 50% duty cycle
waveform. Note that the maximum counting rate is reduced in the latter (bi-quinary) configuration because of
the interstage gating delay within the divide-by-five section.
The '176 has an asynchronous active LOW Master Reset input (Kim) which overrides all other inputs and forceS
all outputs LOW. The counters are also asynchronously presettable. A LOW on the Parallel Load input (PLl
overrides the clock inputs and loads the data from Parallel Data (Po - P3) inputs into flip-flops. While PL is LOW,
the counters act as transparent latches and any change in the Pn inputs will be reflected in the outputs. In order
for the intended parallel data to be entered and stored, the recommended setup and hold times with respect to
the rising edge of PL should be observed.

LOGIC DIAGRAM
Po

MR ---4~----~01~~~--------------~~----------~-----------.

CPa -------------+-<>1
K Co

CPl ----------------------+-~----------------r_--------+_--'
00

4-257

a 1-+-+--'

•

176
+ 5 STATE DIAGRAM

o

BCD STATE DIAGRAM

r
J

0--

~

--EJ

4

1

3

~~--EJ

3--EJ

211
10

'13
'

~

"

MODE SELECT TABLE
INPUTS

RESPONSE

MR

PL

CP

L

X

X

H

L

X

H

H

L

On forced LOW
Pn .... On
Count Up

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER
Min

lee

Power Supply Current

UNITS

48

4-258

CONDITIONS

Max
rnA

Vee = Max
All inputs = Gnd

176
AC CHARACTERISTICS: Vee

= +5.0 V,

TA

= +25° C (See

Section 3 for waveforms and load configurations)

54174
SYMBOL

PARAMETER

CL
RL

= 15 pF
= 400 n

Min

UNITS

CONDITIONS

Max

f max

Maximum Count Frequency
at CPo

35

MHz

Figs. 3-1, 3-9

f max

Maximum Count Frequency
at CP1

17.5

MHz

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CPo to 00

13
17

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 01

17
26

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 02

41
51

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 03 for '176

20
26

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 03 for '177

66
75

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
Pn to an

29
46

ns

Figs. 3-1, 3-5

tPLH
tpHL

Propagation Delay
PL to an

43
48

ns

Figs. 3-1, 3-16

tpHL

Propagation Delay
MR to an

48

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

TA

= +25°C
54174

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH
Pn to PL

15

ns

Fig. 3-13

th (H)

Hold Time HIGH
Pn to PL

0

ns

Fig. 3-13

ts(U

Setup Time LOW
Pn to PL

20

ns

Fig. 3-13

th (U

Hold Time LOW
Pn to PL

0

ns

Fig. 3-13

tw (H)

CPo Pulse Width HIGH

14

ns

Fig. 3-9

tw (H)

CP1 Pulse Width HIGH

28

ns

Fig. 3-9

tw (U

PL Pulse Width LOW

25

ns

Fig. 3-16

tw (U

MR Pulse Width LOW

20

ns

Fig. 3-16

tree

Recovery Ti me
MR or PL to CP n

25

ns

Fig. 3-16

4-259

•

177
CONNECTION DIAGRAM
PINOUT A

54/74177
PRESETTABLE BINARY COUNTER
pt

0::

02

[I

~

E]Vcc

TIl MR

pdI

m

PorI

:ill P3

[I

~P1

CP1[I

~01

00

03

:II CPo

GNO[I

DESCRIPTION - The'177 is a presettable modul0-16 ripple cou nter partitioned into divide-by-two and.divide-by-eight sections, with a separate clock
input for each section. In the counting mode, state changes are initiated by
the falling edge of the clock. A LOW signal on the Master Reset (MR) input
overrides all other inputs and forces the outputs LOW. A LOW signal on
the Parallel Load (PU input overrides the clocks and causes the Q outputs
to assume the state of their respective Parallel Data (P n) inputs. For detail
specifications, please refer to the '176 data sheet.
ORDERING CODE: See Section 9
PIN
PKGS

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70° C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

OUT

PKG
TYPE

Plastic
DIP (P)

A

74177PC

Ceramic
DIP (0)

A

74177DC

54177DM

6A

A

74177FC

54177FM

31

Flatpak
(F)

LOGIC SYMBOL

1

4

10 3 11

61 I I I

PL Po P, P2 P3

8-0

CPa

6-0

CP,
MR 00 0, 02 03

~

13

I I 2I 12I

5

9

9A
Vcc = Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CPo
CP1
MR
PO-P3
PL
QO-Q3

DESCRIPTION
+2 Section Clock Input (Active Falling Edge)
+8 Section Clock Input (Active Falling Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Flip-flop Outputs'
-

'00 is guaranteed to drive CP, in addition to the full rated load.

4-260

54174 (U.L.)

HIGH/LOW
2.0/3.0
2.0/2.0
2.0/2.0
1.0/1.0
1.0/1.0
20/10

177
FUNCTIONAL DESCRIPTION-The '177 is an asynchronously presettable binary ripple counter partitioned
into divide-by-two and divide-by-eight sections. In the counting modes, state changes are initiated by the
HIGH-to-LOW transition of the clock signals. State changes of the 0 outputs, however, do not occur
simultaneously because of the internal ripple delays. When using external logic to decode the On outputs,
designers should bear in mind that the unequal delays can lead to decoding spikes and thus a decoded signal
should not be used as a clock or strobe. The CPo input serves the 00 flip-flop while the CP1 input serves the
divide-by-eight section. The 00 output is designed and specified to drive the rated fan-out plus the CP1 input.
With the input frequency connected toCPo and with 00 drivingCP1, the '177 forms a straightforward modul0-16
counter, with 00 the least significant output and 03 the most significant output.

The '177 has an asynchronous active LOW Master Reset input (MRl which overrides all other inputs and forces
all outputs LOW. The counters are also asynchronously presettable. A LOW on the Parallel Load input (PU
overrides the clock inputs and loads the data from Parallel Data (Po - P3l inputs into the flip-flops. While PL is
LOW, the counters act as transparent latches and any change in the Pn inputs will be reflected in the outputs .

MODE SELECT TABLE

INPUTS
MR

PL

CP

L
H
H

X
L
H

X
X

L

•

STATE DIAGRAM

RESPONSE
On forced LOW
Pn ..... On
Count Up

H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial

LOGIC DIAGRAM
Po

MR

--~~------Ol.~~+-------------~+-----------~r-----------,

Pi.

------()£...-'

CPo

-----------_+-<11

CP, ----------------------r-----~----------_+--------_+~
00

03

4-261

178
CONNECTION DIAGRAM
PINOUT A

54/74178
4-BIT SHIFT REGISTER
....,

B]vcc

P1u

II

ll)P2

Ds[!

:g)P3

0011

I!lSE

c"IT

}ill 03

Po

011]:

]]PE

GNDIT

]]02

LOGIC SYMBOL
DESCRIPTION - The '178 features synchronous parallel or serial entry and
parallel outputs. The flip-flops are fully edge-triggered, with state changes
initiated by a HIGH-to-LOW transition of the clock. Parallel Enable and
Serial Enable inputs are used to select Load, Shift and Hold modes of operation. The '178 is the 14-pin version of the '179. For detail specifications, please
refer to the '179 data sheet.

ii

PE

Po

1 Yy
Pl

P2

P3

3 - Ds

5 --
Ds------------~

cp--o~--------~--~~------~--~--;_------~--~--_+------~--_,

Qo

Q3

4-263

179
CONNECTION DIAGRAM
PINOUT A

54/74179
4-BIT SHIFT REGISTER

DESCRIPTION - The '179 features synchronous parallel or serial entry,
asynchronous reset and parallel outputs, with the complement output of the
fourth stage also available. The flip-flops are fully edge-triggered, with state
changes initiated by a HIGH-to-LOW transition of the clock. Parallel Enable
and Serial Enable inputs are used to select Load, Shift and Hold modes of
operation. A LOW signal on the Master Reset input overrides all other inputs
and forces the Q outputs to the LOW state.

PKGS

OUT

10 3

.-

ORDERING CODE: See Section 9
PIN

LOGIC SYMBOL

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C·to +125°C

PKG

2 15 14

PE Po p, P2 P3

6

Ds
cp

13

SE

03

TYPE

Plastic
DIP(P)

A

74179PC

Ceramic
DIP (D)

A

74179DC

54179DM

68

Flatpak
(F)

A

74179FC

54179FM

4L

98

1

5

7

9 11

Vcc = Pin 16
GND

= Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
PE
Po-P3
Ds
SE
CP
MR
Qj-Q3

Ch

DESCRIPTION
Parallel Enable Input
Parallel Data Inputs
Serial Data Input
Shift Enable Input
Clock Pulse Input (Active Falling Edge)
Asynchronous Master Reset Input (Active LOW)
Flip-flop Outputs
Fourth Stage Complement Output

4-264

54174 (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
20/10
20/10

12

179
FUNCTIONAL DESCRIPTION - The '179 contains four D-type edge-triggered flip-flops and sufficient interstage logic to perform parallel load, shift right or hold operations. All state changes except reset are initiated by
a HIGH-to-LOW transition of the clock. A LOW signal on MR overrides all other inputs and forces the 0 outputs
LOWand cb HIGH. With MR HIGH, aHIGH signal on SE prevents parallel loading and permits a right shift each
time the clock makes a HIGH-to-LOW transition. When MR and SE are LOW, the signal applied to PE
determines whether the circuit is in a parallel load or a hold mode, as shown in the Mode Select Table. The SE,
PE, Ds and Pn inputs can change when the clock is in either state, provided only that the recommended setup
and hold times are observed.

MODE SELECT TABLE
INPUTS

RESPONSE

MR

SE

PE

CP

L
H
H
H

X
H
L
L

X
X
H
L

'"'-

X

1X

•

Asynchronous Reset; On--LOW; 03-HIGH
Right Shift. Ds--Qo; 00-01, etc.
Parallel load. Pn --On
Hold

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
Po

P3

PE--i~~~~:)O------~~--~~--------~----+---------~~--~---------,

SE--i;~~~~)o----~~HHr--Hr-----~--~+--++-------~-+~--~------,

os--------------~

CP

CP

0

co

CP
CD

0

CP
CD

0

0

0

0

00

0,

02

CP
CD

0

0

MR

4-265

03

03

179
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER
Min

lee

Power Supply Current

UNITS

CONDITIONS

mA

Vee = Max, Pn = Gnd
Os, PE, SE, MR = 4.5 V
CP = L.

Max

XM

70
75

--xc

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C (See Section 3 for waveforms and load configurations)
54/74

SYMBOL

PARAMETER

CL = 15 pF
RL=400n
Min

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-9

26
35

ns

Figs. 3-1, 3-9

Propagation Delay
MR to 03

23

ns

Propagation Delay
MR to an

36

fmax

Maximum Clock Frequency

tPLH
tpHL

Propagation Delay
CP to an

tPLH
tPHL

25

Figs. 3-1, 3-17
ns

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54174

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time HIGH or LOW
Os or Pn to CP

30
30

ns

th (H)
th (Ll

Hold Time HIGH or LOW
Os or Pn to CP

5.0
5.0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
PE or SE to CP

35
35

ns

th (H)
th (U

Hold Time HIGH or LOW
PE or SE to CP

5.0
5.0

ns

tw (H)

CP Pulse Width HIGH

20

ns

Fig. 3-9

tw (Ll

MR Pulse Width LOW

20

ns

Fig. 3-17

tree

Recovery Time
MR to CP

15

ns

Fig. 3-17

4-266

Fig. 3-7

180
CONNECTION DIAGRAM
PINOUT A

54/74180
a-BIT PARITY GENERATOR/CHECKER

DESCRIPTION - The '180 is a monolithic, 8-bit parity checker/generator
which features control inputs and even/odd outputs to enhance operation in
either odd or even parity applications. Cascading these circuits allows unlimited word length expansion. Typical application would be to generate and
check parity on data being transmitted from one register to another. Typical
power dissipation is 170 mW.

16

IT

17

~vcc

~

II

~IS

EI[I

~14

olII

~13

LE[I

~12

Lo!I

~11

~IO

GNO[I

LOGIC SYMBOL

i i 7111 1j T1i

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V, ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

10

11

12

13

Is

14

4 - 01

3 - EI

Plastic
DIP(P)

A

74180PC

Ceramic
DIP (D)

A

74180DC

Flatpak
(F)

A

74180FC

9A

LO

54180DM

6A

6

54180FM

31

LE

1
Vcc = Pin 14
GND= Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

10-17
01
EI

Io
IE

54174 (U.L.)

DESCRIPTION

PIN NAMES

HIGH/LOW

Data Inputs
Odd Input
Even Input
Odd Parity Output
Even Parity Output

1.0/1.0
2.0/2.0
2.0/2.0
20/10
20/10
TRUTH TABLE
OUTPUTS

INPUTS

I OF 1's AT
o THRU 7

EVEN

ODD

EVEN

ODD

EVEN
ODD
EVEN

H
H
L

L
L
H

H
L
L

L
H
H

ODD
X
X

L
H
L

H
H
L

H
L
H

L
L
H

I

I

4-267

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

I

5

16

17

180
LOGIC DIAGRAM

:::::)D}D-

..-----I

-i)soD-~E

:~=)D
DATA
INPUTS

:::::)D}

D

...po.-

~,o

>-- ""'-'

:~=)D
01

EI

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

los

Output Short
Circuit Current

~
XC

lee

Power Supply Current

~

UNITS

CONDITIONS

Min

Max

-20
-18

-55
-55

mA

Vee = Max

49
56

mA

Vee = Max, In = Open
01, EI = 4.5 V

XC

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174

SYMBOL

PARAMETER

CL = 15 pF
RL = 400 n
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
In to ~E

60
68

ns

Figs. 3-1, 3-5
01 = Gnd

tPLH
tPHL

Propagation Delay
In to ~o

48
38

ns

Figs. 3-1, 3-4
01 = Gnd

tPLH
tPHL

Propagation Delay
In to ~E

48
38

ns

Figs. 3-1, 3-5
EI = Gnd

tPLH
tPHL

Propagation Delay
In to ~o

60
68

ns

Figs. 3-1, 3-4
EI = Gnd

tPLH
tpHL

Propagation Delay
EI or 01 to ~E

20
10

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
EI or 01 to ~o

20
10

ns

Figs. 3-1, 3-4

4-268

181
CONNECTION DIAGRAM
PINOUT A

54LS/74LS181

-

BoIT
iol!

4-BIT ARITHMETIC LOGIC UNIT

lEI Vee

rm A1
~i'

S3[!

S1[!

~A2
~12

solI

[rnA3

col!

rm 1h

S2[i

DESCRIPTION - The '181 is a 4-bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic operations on two variables and a variety of
arithmetic operations. For improved TTL, S-TTL and LP-TTL versions, please
see the 9341 data sheet.

~G

M!!
I'D!!
• PROVIDES 16 ARITHMETIC OPERATIONS
ADD,SUBTRACT,COMPARE,DOUBLE,PLUS
TWELVE OTHER ARITHMETIC OPERATIONS
• PROVIDES ALL 16 LOGIC OPERATIONS OF TWO VARIABLES
EXCLUSIVE - OR, COMPARE, AND, NAND, OR, NOR,
PLUS TEN OTHER LOGIC OPERATIONS
• FULL LOOKAHEAD FOR HIGH SPEED ARITHMETIC
OPERATION ON LONG WORDS

PKGS

OUT

llIII!II

7-

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

AD 10 A1 ., A2 82 Aa 83

Co

Cn +4 1--11

1- M
1 - 80
5 - 8,

A=B 1-- 10

G11>-'7
p 11>-'5

. - I,

a - ..

A

74LS181PC

Ceramic
DIP (D)

A

74LS181DC

54LS181DM

6N

A

74LS181FC

54LS181FM

4M

(F)

~F3

LOGIC SYMBOL

Plastic
DIP (PI

Flatpak

~P
!mA'B

GND~

ORDERING CODE: See Section 9
PIN

~Cn+4

1',1i]
r2fij

9N

F,

F,

F3

! !

~

!

Fo

Vee = Pin 24
GND = Pin 12

INPUT· LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES

Ao-Aa

Fo-F3

Operand Inputs (Active LOW)
Operand Inputs (Active LOW)
Function Select Inputs
Mode Control Input
Carry Input
Function Outputs (Active LOW)

A=B

Comparator Output

G
P

Carry Generate Output (Active LOW>
Carry Propagate Output (Active LOW)
Carry Output

Bo-~

So-53
M
Cn

Cn

+4

'oc- Open Collector

4-269

54/74LS (U.L.)
HIGH/LOW
1.5/0.75
1.5/0.75
2.0/1.0
0.5/0.25
2.5/1.25
10/5.0
(2.5)
OC"/5.0
(2.5)
10/10
10/5.0
10/5.0
(2.5)

181
FUNCTIONAL DESCRIPTION - The 'LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU).
Controlled by the four Function Select inputs (So - Sa) and the Mode Control input (M), itcan perform all the 16
possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands. The
Function Table lists these operations.
When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic
operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the
device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry
lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead
between packages using the signals j5 (Carry Propagate) and G (Carry Generate). In the ADD mode, Pindicates
that F is 15 or more, while G indicates that Fis 16 or more. In the SU8TRACT mode, j5 indicates that Fis zero or
less, while G indicates that Fis less than zero. j5 and Gare not affected by carry in. When speed requirements are
not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (Cn + 4) signal to the
Carry input (Cn) of the next unit. For high speed operation the device is used in conjunction with the 9342 or
93S42 carry lookahead circuit. One carry lookahead package is required for each group of four 'LS181 devices.
Carry lookahead can be provided at various levels and offers high speed capability over extremely long word
lengths.
The A = 8 output from the device goes HIGH when all four Foutputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract mode. The A= 8 output is open-collector and can be
wired-AND with other A = 8 outputs to give a comparison for more than four bits. The A = 8 signal can also be
used with the Cn + 4 signal to indicate A > 8 and A < 8.
The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds
a one to each operation. Thus, select code LHHL generates A minus 8 minus 1 (2s complement notation)
without a carry in and generates A minus 8 when a carry is applied. 8ecause subtraction is actually performed
by complementary addition (1 s complement), a carry out means borrow; thus a carry is generated when there is
no underflow and no carry is generated when there is underflow. As indicated, this device can be used with
either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH
outputs. For either case the table lists the operations that are performed tothe operands labeled inside the logic
symbol.
FUNCTION TABLE
MODE SELECT
INPUTS

ACTIVE LOW OPERANDS
& Fn OUTPUTS

ACTIVE HIGH OPERANDS
& Fn OUTPUTS

Sa

S2

Sl

So

LOGIC
(M=H)

ARITHMETIC"
(M = U (Cn = U

LOGIC ARITHMETIC"
(M=H) (M = U (Cn = H)

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

A
A8
A+8
Logic'1

A minus 1
A8 minus 1
AS minus 1
minus 1

A
A+B
A8
LogicO

A
A+8
A+B
minus 1

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

A+B
S
A(±) 8
A+S

A plus (A + B)
AB plus (A + B)
A minus 8 minus 1
A+B

AB
S
A(f)8
AS

A plus AS
(A + B) plus AS
A minus 8 minus 1
AB minus 1

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

A8
A(f)B
8
A+B

A plus (A + 8)
A plus 8
AS plus (A + B)
A+8

A+8
A(f)8
B
AB

A plus AB
A plus B
(A + 8) plus AB
A8 minus 1

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

Logic 0
A8
A8
A

A plus A'
AB plus A
A8 minus A
A

Logic 1
A+B
A+B
A

A plus A'
(A + B) plus A
(A + S) plus A
A minus 1

'each bit is shifted to the next more significant position
**arithmetic operations expressed in 2s complement notation

4-270

181
LOGIC SYMBOLS

ACTIVE LOW OPERANDS

ACTIVE HIGH OPERANDS
1

2

7

Cn

8

M

6

So

5

S,

4

S2

3

S3

2322 21 20 19 18

2

Cn+4
54LS/74LS181
4-BIT ARITHMETIC
LOGIC UNIT

A=S
G

P

9

10

11

16
14
17
15

7

Cn

8

M

6

So

5

S1

4

S2

3

S3

13

1

23 22 21 20 19 18

en + 4

16

54LS174LS181
A=B
4-BIT ARITHMETIC
LOGIC UNIT
G

14
17

P

15

10

9

11

•

13

LOGIC DIAGRAM
en

M

Ao

BO

8,

i,

i3

.---~----,r----,r-+1---~------+----+--~----+-----~----~4-~--~----~SO

?
F3

4-271

ji

C n +4

181
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
54174LS

PARAMETER

SYMBOL

UNITS

CONDITIONS

100

,..A

Vee = Min, VOH = 5.5 V

~
XC

32
34

rnA

XM

35
37

rnA

Min
IOH

Icc

Max

Output HIGH Current, A = B

Power Supply Current

---xc

Vee = Max
Bn, Cn = Gnd
Sn, M, )l;n = 4.5 V
Vee - Max
An, Bn, Cn = Gnd
M, Sn = 4.5 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174LS
PARAMETER

SYMBOL

CL = 15 pF
Min

UNITS

CONDITIONS

Max

tpLH
tpHL

Propagation Delay
Cn to en + 4

27
20

ns

M = Gnd, Figs. 3-1, 3-5
Tables I & II

tpLH
tPHL

Propagation Delay
Cn to;:

26
20

ns

M = Gnd, Figs. 3-1, 3-5
Table I

tPLH
tPHL

Propagation Delay
A or 8 to G

29
23

ns

M, 81, 52 = Gnd; 81,
Sa = 4.5 V; Figs. 3-1, 3-5
Table I

tPLH
tpHL

Propagation Delay
A orato ~

32
26

ns

M, So, 53 = Gnd; Sl,
S2 = 4.5 V; Figs. 3-1,3-4,
3-5; Table II

tPLH
tPHL

Propagation Delay

A or eto j5"

30
30

ns

tPLH
tpHL

Propagation Delay
A or eto P-

30
33

ns

M, So, Sa = Gnd; 81,
82 = 4.5 V; Figs. 3-1, 3-4,
3-5; Table II

tpLH
tPHL

Propagation Delay
Ai or to Fi

32
25

ns

M, Sl, S2 = Gnd; So,
Sa = 4.5 V; Figs. 3-1, 3-5:
Table I

tPLH
tPHL

Propagation Delay
Ai or Bi to Fi

32
32

ns

M,So, Sa = Gnd; Sl,
S2 = 4.5 V; Figs. 3-1, 3-4,
3-5; Table II

tpLH
tPHL

A or

Propagation Delay
eto F

33
29

ns

M =4.5 V; Figs. 3-1, 3-5;
Table III

tpLH
tpHL

Propagation Delay
)I; orB to Cn + 4

38
38

ns

M, 81, 52 = Gnd; So,
Sa = 4.5 V; Figs. 3-1,3-4;
Table I

-a

4-272

M, Sl, S2 = Gnd; So,
Sa = 4.5 V; Figs. 3-1, 3-4;
Table I

181
AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (Cont'd)
54174LS
SYMBOL

PARAMETER

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

lPLH
tPHL

Propagation Delay
A or B to Cn + 4

41
41

ns

lPLH
lPHL

Propagation Delay
A or"Bto A = B

50
62

ns

M,

So, 53 = Gnd; 8"

82

= 4.5

V; Figs. 3-1, 3-4,
3-5; Table"
M,

FUNCTION INPUTS: So

SUM MODE TEST TABLE I

SYMBOL

INPUT
UNDER
TEST

OTHER INPUT

So, 83 = Gnd; 8"

V; RL = 2 kO to
5.0 V; Figs. 3-2, 3-4, 3-5;
Table"

82

= 4.5

= 83 = 4.5 V, 8, = 82 = M = 0 V

OTHER DATA INPUTS

SAME BIT
APPLY
4.5 V

APPLY
GND

APPLY
4.5 V.

APPLY
GND

OUTPUT
UNDER
TEST

tPLH
tPHL

Ai

Si

None

Remaining
A. and B'

en

Fi

tPLH
tPHL

Bi

Ai

None

Remaining
AandB

en

Fi

tPLH
tPHL

A

B

None

None

Remaining

A and S, en

p

tPLH
tPHL

S

A

None

None

A and S, en

tPLH
tPHL

A

None

B

Remaining

Remaining

S

A, en

tPLH
tPHL

B

None

A

Remaining

B

Remaining
A, Cn

tPLH
tPHL

A

None

B

Remaining

Remaining

B

A,en

tPLH
tPHL

8

None

A

Remaining

Remaining

S

A, en

tPLH
tPHL

en

None

None

All

All

A

8

4-273

Remaining

-P

G

G
en

+4

en

+4

Any F
or en + 4

•

181
FUNCTION INPUTS: 8, = 82 = 4.5 V, So = 83 = M = 0 V

DIFF MODE TEST TABLE II

SYMBOL

INPUT
UNDER
TEST

OTHER INPUT
SAME BIT

OTHER DATA INPUTS

APPLY
4.5 V

APPLY
GND

A

None

B

tPLH
tPHL

B

A

None

tPLH

A

None

B

None

A and S, Cn

B

A

None

None

A and B, Cn

A

B

None

None

A and S, Cn

B

None

A

None

A andS,

A

None

B

Remaining

-B

A

None

A

B

None

None

B

None

A

None

Cn

None

None

A andB

tPLH
tPHL

tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL

LOGIC MODE TEST TABLE III

SYMBOL

tPLH
tPHL
tPLH
tPHL

INPUT
UNDER
TEST

APPLY
4.5 V

APPLY
GND

Remaining

Remaining
S, Cn

Fi

Remaining
B,Cn

Fi

Remaining

p

A
Remaining

A

A
Remaining

A

SAME BIT

Remaining
Remaining

IT
IT

Remaining
B, Cn

A=B

Remaining
B,Cn

A=B

Remaining

A and S, Cn

Cn +

Remaining
Aand B, Cn

Cn + 4

None

= 82

Cn +

4

4

= M = 4.5 V, 80 = 83 = 0 V

OTHER DATA INPUTS

APPLY
4.5 V

APPLY
GND

APPLY
4.5 V

A

B

None

None

A andB,

B

A

None

None

A and S,

4-274

p

Remaining
Cn

All

FUNCTION INPUTS: 8,

OTHER INPUT

OUTPUT
UNDER
TEST

APPLY
GND

OUTPUT
UNDER
TEST

Remaining
Cn

AnyF

Remaining
Cn

AnyF

183
CONNECTION DIAGRAM
PINOUT A

-

54H/74H183

Aa[I

DUAL HIGH SPEED ADDER

NC@:

twAb

Ba 11:

tm Bb
tIn C;b

tEl

c;a8:

~COb

Coa~

m
t!J

Sa II

NC

GNOII

Sb

LOGIC SYMBOL

1i

i lr y y

Aa Ba Cia Ab Bb Cib

Sa Coa

Sb Cob

!! !

TRUTH TABLE
(Each Half)
INPUTS

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILIT ARY GRADE

Vee = +5.0 V ±5%.
TA = O°C to +70°C

Vee = +5.0 V ±10%.
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74H183PC

Ceramic
DIP (0)

A

74H183DC

54H183DM

6A

Flatpak
(F)

A

74H183FC

54H183FM

31

9A

,1o

VCC = Pin 14
GND = Pin 7

DESCRIPTION - The '183 contains two independent full adders. Each adder
has an individual carry output for use in multiple-input. carry-save techniques to produce the true sum and true carry outputs with no more than
two gate delays. Typical propagation delay is 12 ns.

OUTPUTS

A

B

Ci

S

Co

L
H
L
L

L
L
H
L

L
L
L
H

L
H
H
H

L
L
L
L

H
H
L
H

H
L
H
H

L
H
H
H

L
L
L
H

H
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Aa. Ba
Ab. Bb
Cia. Cib
Sa. Bb
Coa• Cob

DESCRIPTION
Side a Operand Inputs
Side b Operand Inputs
Carry Inputs
Sum Outputs
Carry Outputs

54/74H (U.L.)
HIGH/LOW
3.75/3.75
3.75/3.75
3.75/3.75
25/12.5
25/12.5

4-275

Vee

•

183
LOGIC DIAGRAM

C;--4>
B-L{>

A--4>

)(

lrh
U

)( )
~

~

CO

s

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174H

PARAMETER
Min

Icc

Power Supply Current

I
I

UNITS

CONDITIONS

Max

XM
XC

69
75

mA

Vee = Max
All Inputs = Gnd

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74H
SYMBOL

PARAMETER

CL = 25 pF
RL = 280 n
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Ax, Bx or Cix to Sx

15
18

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
Ax, Bx or Cix to Cox

15
18

ns

Figs. 3-1, 3-5

4-276

189
CONNECTION DIAGRAM
PINOUT A

54S/74S189
54LS/74LS189
64-BIT RANDOM ACCESS MEMORY

Cs[I

(With 3-State Outputs)

WE~

G:

~A3
@]04

02j!

}TI04

IT

TIl 03

GNO[!

}]Ch

02

DESCRIPTION - The '189 is a high speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are
fully decoded on-chip. The outputs are 3-state and are in the high impedance
state whenever the Chip Select (CS) input is HIGH. The outputs are active
only in the Read mode and the output data is the complement of the stored
data.

LOGIC SYMBOL

3-STATE OUTPUTS FOR DATA BUS APPLICATIOfllS'
BUFFERED INPUTS MINIMIZE LOADING
ADDRESS DECODING ON-CHIP
DIODE CLAMPED INPUTS MINIMIZE RING' .....~

1i i T 1
1j

cs
l15-

<~;;i·

ORDERING CODE: See Section 9
PIN
PKGS

OUT

~vcc
~A1
~A2

01~

0,

•
•
•
•

-

AoD:

0, 02 03 04 WE

Ao
A1

1 4 - A2

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74S189PC, 74LS189PC

Ceramic
DIP(D)

A

74S189DC, 74LS189DC

54S189DM,54LS189DM

68

Flatpak
(F)

A

74S189FC, 74LS189FC

54S189FM,54LS189FM

4L

1 3 - A3
01 02 03 04

r! r X

98
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-As
CS
WE
Dl-D4
01-04

DESCRIPTION
Address Inputs
Chip Select Input (Active LOW)
Write Enable Input (Active LOW)
Data Inputs
Inverted Data Outputs

4-277

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

0.63/0.16
0.63/0.16
0.63/0.16
0.63/0.16
162/10
(50)

0.5/0.013
0.5/0.013
0.5/0.013
0.5/0.013
10/10
(5.0)

•

189
FUNCTION TABLE
INPUTS
CS

WE

L
L
H

L
H
X

OPERATION

CONDITION OF OUTPUTS

Write
Read
Inhibit

High Impedance
Complement of Stored Data
High Impedance

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

,
.
r r I' -.
_.

LOGIC DIAGRAM

DATA BUFFERS

AoA,A2A3-

DECODER
DRIVERS

-

WE

I.

CS

I I I I
ADDRESS
DECODER

-

--\

16-WORD x 4-BIT
MEMORY CELL
ARRAY

-I

I I I I
11I I
0,

02

03

--

I""

OUTPUT BUFFERS

O.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74S

PARAMETER

Min

VOL

Output LOW Voltage

Max

54174LS
Min

--?- - -

190

D~~;;~~~--~-----------------4~--------------~~-----------UID

UIO

ENABLE - - - 0 CE

L-----OICE

CP

CP

RC C>- - -

ClOCK---+-----------------4----------------~~------------

Fig. b

Synchronous N-Stage Counter Using Ripple Carry/Borrow

•

DIRECTION

CONTROL
ENABLE

rcp "-~:
- - U/D

--1:>0--<>

c.-.:=po--orcp

' - U/D

' - U/D

CE

CE

TC-

TCI--

CLOCK

Fig. c

Synchronous N-Stage Counter with Parallel Gated Carry/Borrow

OlD
tPLH

TC

Vm

!PlH1_
-l- ~.'.5V

' - _ _ _ _ _J

Fig.ld

4-283

Vm

p.3V for LS)

190
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min
lee

Power Supply Current

I
I

Max

54174LS
Min

99

XM
XC

35
35

105

UNITS

CONDITIONS

Max
mA

Vee = Max
All Inputs = Gnd

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174
SYMBOL

PARAMETER

54174LS

CL = 15 pF CL = 15 pF
RL=400n
Min

Max

20

Min

UNITS

CONDITIONS

Max

f max

Maximum Count Frequency

20

MHz

tPLH
tPHL

Propagation Delay
CP to On

24
36

24
36

ns

tPLH
tPHL

Propagation Delay
CP to TC

42
52

42
52

ns

tPLH
tPHL

Propagation Delay
CP to RC

20
24

20
24

ns

tPLH
tPHL

Propagation Delay
Pn to On

22
50

22
50

ns

tPLH
tPHL

Propagation Delay
CE to RC

33
33

33
33

ns

tPLH
tPHL

Propagation Delay
PL to On

33
50

33
50

ns

tPLH
tPHL

Propagation Delay

U/D to RC

45
45

45
45

ns

tPLH
tPHL

Propagation Delay
U!D to TC

33
33

33
33

ns

Figs. 3-1,3-8

Figs. 3-1, 3-5

Figs. 3-1,3-16

Fig. 3-1, Fig. d

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54174
Min

Max

54174LS
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time HIGH or LOW
Pn to PL

20
20

20
20

ns

th (H)
th (U

Hold Time HIGH or LOW
Pn to PL

0
0

5.0
5.0

ns

ts(U

Setup Time LOW
CE to CP

20

20

ns

th (U

Hold Time LOW
CE to CP

0

0

ns

tw (U

Fig. 3-13

Fig. 3-6

CP Pulse Width LOW

25

20

ns

Fig. 3-8

tw (U

PL Pulse Width LOW

35

35

ns

Fig. 3-16

tree

Recovery Ti me
PL to CP

20

20

ns

Fig. 3-16

4-284

191
CONNECTION DIAGRAM
PINOUT A

54/74191
54LS/74LS191
UP/DOWN BINARY COUNTER
(With Preset and Ripple Clock)
DESCRIPTION - The '191 is a reversible modul0-16 binary counter featuring synchronous counting and asychronous presetting. The preset feature
allows the '191 to be used in programmable dividers. The Count Enable input,
the Terminal Count output and the Ripple Clock output make possible a
variety of methods of implementing mUlti-stage counters. In the counting
modes, state changes are initiated by the rising edge of the clock. For detail
specifications and functional description, please refer to the '190 data sheet.

•
•
•
•

HIGH SPEED - 30 MHz TYPICAL COUNT FREQUENCY
SYNCHRONOUS COUNTING
ASYNCHRONOUS PARALLEL LOAD
CASCADABLE

•

LOGIC SYMBOL

11 15 1

10 9

ORDERING CODE: See Section 9
PIN
PKGS

OUT

13

MILITARY GRADE

COMMERCIAL GRADE
Vee = +5.0 V ±5%,
TA = O°C to +70°C

PKG

Vee = +5.0 V ±10%
TA = -55°C to +125°C

TYPE

Plastic
DIP(P)

A

74191PC, 74LS191PC

Ceramic
DIP (D)

A

74191DC, 74LS191DC

54191DM,54LS191DM

78

Flatpak
(F)

A

74191FC, 74LS191FC

54191FM,54LS191FM

4L

CE

14

TC

CP

98
Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

54174 (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

3.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0

1.5/0.75
0.5/0.25
0.5/0.25
0.5/0.25

1.0/1.0
20/10

0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)
10/5.0
(2.5)

00-03

Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Asynchronous Parallel Load Input
(Active LOW)
Up/Down Count Control Input
Flip-flop Outputs

RC

Ripple Clock Output (Active LOW)

20/10

TC

Terminal Count Output (Active HIGH)

20/10

CE
CP
PO-P3
PL

UID

4-285

12

191
RC TRUTH TABLE

MODE SELECT TABLE
INPUTS
PL

H
H
L
H

L
L
X
H

INPUTS

MODE

CE UfO

CP

S

L
H
X
X

Count Up
Count Down
Preset (Asyn.l
No Change (Hold)

..r
X
X

OUTPUT

CE

TC'

CP

RC

L
H
X

H
X
L

V

'"'l.r
H
H

X
X

'TC is generated internally

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

STATE DIAGRAM

-COUNTUP

----+- COUNT DOWN

LOGIC DIAGRAM
CP U/D

CE

Po

~~
f--

~7

rQ ~

~7

f-

(,

t

r~
PRESET

CLEAR

a

a

~
6)

ll: eeL '~J
PRESET

CLEAR

a

0

~

I

RC TC

00

4-286

UJ

~~

~~
l '" ecL '~J
PRESET

CLEAR

a

0

~

Lf~.~

~

192
CONNECTION DIAGRAM
PINOUT A

54/74192
54LS/7 4LS 192

~vcc

a,[~

~Po

UP/DOWN DECADE COUNTER

aoIT

~MR

(With Separate Up/Down Clocks)

CPD[i

~TCD

CPu [1

~TCu

ad}

~PI

a3[!

~P2
~P3

DESCRIPTION - The '192 is an up/down BCD decade (8421) counter. Separate Count Up and Count Down Clocks are used and in either counting mode
the circuits operate synchronously. The outputs change state synchronous
with the LOW-to-HIGH transitions on the clock inputs.

GND []:

Separate Terminal Count Up and Terminal Count Down outputs are provided
which are used as the clocks for a subsequent stage without extra logic,
thus simplifying multistage counter. designs. Individual preset inputs allow
the circuits to be used as programmable counters. Both the Parallel Load
(PU and the Master Reset (MR) inputs asynchronously ,override the clocks.

PIN
OUT

r

~ l ri
PL Po P,

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Plastic
DIP (P)

A

74192PC, 74LS192PC

Ceramic
DIP (0)

A

74192DC, 74LS192DC

Flatpak
(F)

A

PKG

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

54192DM,54LS192DM

5-

cPu

4-

CPD

54192FM, 54LS192FM

1

P2 P3
TCu

TYPE

MR

TCD
ao a, a2 a3

98

1~

! !!!

68

0-12
0-13

Vcc = Pin 16
GND

74192FC, 74LS192FC

•

LOGIC SYMBOL

ORDERING CODE: See Section 9

PKGS

-

P,[!:

= Pin

8

4L

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CPu
CPD
MR
PL
PO-P3
00-03
TCD
TCu

DESCRIPTION
Count Up Clock Input
(Active Rising Edge)
Count Down Clock Input
(Active Rising Edge)
Asynchronous Master Reset Input
(Active HIGH)
Asynchronous Parallel Load Input
(Active LOW)
Parallel Data Inputs
Flip-flop Outputs
Terminal Count Down (Borrow)
Output (Active LOW)
Terminal Count Up (Carry)
Output (Active LOW)

54174 (U~L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

1.0/1.0
20/10

0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)
10/5.0
(2.5)

20/10
20/10

4-287

192
FUNCTIONAL DESCRIPTION - The '192 and '193 are asynchronously presettable decade and 4-bit binary
synchronous up/down (reversible) counters. The operating modes of the '192 decade counter and the '193
binary counter are identical, with the only difference being the count sequences as noted in the State Diagram.
Each circuit contains four master/slave flip-flops, with internal gating and steering logicto provide master reset,
individual preset, count up and count down operations.
Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input
causes the slave, and thus the output to change state. Synchronous switching, as opposed to ripple counting,
is achieved by driving the steering gates of all stages from a common Count Up line and acommon Count Down
line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count
Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by
one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count
by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either Clock
input is LOW.

a

The Terminal Count Up (TCu) and Terminal Count Down (TCrr) outputs are normally HIGH. When a circuit has
reached the maximum count state (9 for the '192,15 for the '193), the next HIGH-to-LOWtransition of the Count
Up Clock will cause TCu to go LOW. TCu will stay LOW until CPu goes HIGH again, thus effectively repeating
the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in
the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can
be used as the clock input signals to the next higher order circuit in a multistage counter.
TCu = 00 • 03 • CPu
01 • 02 • 03 • CPD

= 00 •

TCD

Each circuit has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel
Load (PU and the Master Reset (MR) inputs are LOW, information present on the Parallel Data inputs (Po - P3) is
loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH
signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each a
output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next
LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted.
LOGIC DIAGRAM
Po

Pi:
(LOA

P3

DL ...
TC u
ICARRY

CPu
I UP
COUNT)

OU TPUT)

r-~~
!:

U.

)

b~}o-b
0

b

~or-+-

0 1--_

T

OI- l--

T

of-

T

op-

iL ~~ iL~

f-~
-

6
]1

cPo

...

MR

....
00

Teo

03

192
STATE DIAGRAM

MODE SELECT TABLE
MR
H
L
L
L
L

PL CPu
X
L
H
H
H

X
X
H

S
H

MODE

CPo
X
X
H
H

S

Reset (AsynJ
Preset (AsynJ
No Change
Count Up
Count Down

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174

PARAMETER

Min

Max

-20
-18

-65
-65

-20
-20

-100
-100

mA

Vce

34
34

mA

Vee = Max; MR, PL = Gnd
Other Inputs = 4.5 V

XM
XC

lee

Power Supply Current

XM
XC

89
102

V, TA

= +25°C (See

PARAMETER

CL
RL

= 15 pF
= 400 n

Min

Max

25

54174LS
CL

= 15 pF

Min

Maximum Count Frequency

30

tPLH
tPHL

Propagation Delay
CPu or CPo to an

38
47

31
28

tPLH
tPHL

Propagation Delay
CPu to TCu

26
24

16
21

tPLH
tPHL

Propagation Delay
CPo to TCo

24
24

16
24

tPLH
tpHL

Propagation Delay
Pn to an

MHz

tPLH
tPHL

Propagation Delay
PL to an

tPHL

Propagation Delay, MR to

20
30
40
40

32
30

35

25

4-289

UNITS

CONDITIONS

Max

fmax

an

= Max

Section 3 for waveforms and load configurations)

54174
SYMBOL

CONDITIONS

Max

Output Short
Circuit Current

= +5.0

UNITS

Min
los

AC CHARACTERISTICS: Vee

54174LS

Figs. 3-1, 3-8

ns

ns

Figs. 3-1, 3-5

ns

Figs. 3-1, 3-5

ns

Figs. 3-1, 3-16

192
AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0 V,

TA

= +25°C

54174
Min

Max

54/74LS
Min

ts (H)
ts (U

Setup..I.!me HIGH or LOW
Pn to PL

20
20

20
10

th (H)
th (U

Hold Time HIGH or LOW
Pn to PL

0
3.0

3.0
3.0

tw (U

CP Pulse Width LOW

20

17

tw (U

PL Pulse Width LOW

20

20

tw (H)

MR Pulse Width HIGH

20

15

tree

Recovery Time, MR to CP

6.0

3.0

tree

Recovery Ti me, PL to CP

6.0

10

4-290

UNITS

CONDITIONS

Max

ns

Fig. 3-13
CPu

= CPo = LOW

ns

Fig. 3-8

ns

Fig. 3-16

193
CONNECTION DIAGRAM
PINOUT A

54/74193
54LS/74LS193

-

P'[l:

~vcc

1m Po

UP/DOWN BINARY COUNTER

a, II
00 [!

(With Separate Up/down Clocks)

cPo[!

TIl TCo

cPu IT

:illTcu

02!!

ITIPi:

03[!

~P2

GNOII

]]P3

DESCRIPTION - The '193 is an up/down modul0-16 binary counter. Separate Count Up and Count Down Clocks are used and in either counting
mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate
Terminal Count Up and Terminal Count Down outputs are provided which
are used as the clocks for subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits
tOI be used as programmable counters. Both the Parallel Load (PLl and the
Master Reset (MAl inputs asynchronously override the clocks. Forfunctional
description and detail specifications please refer to the '192 data sheet.

B]MR

LOGIC SYMBOL

1r i
l1j

ORDERING CODE: See Section 9
PIN
PKGS

OUT

PL Po p, P2 P3
5 - cPu
TCu 0-12

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
4-

CPo

TCo 0-13
02 03

TYPE

MR

00

9B

1~

!!!!

Plastic
DIP(P)

A

74193PC, 74LS193PC

Ceramic
DIP (D)

A

74193DC, 74LS193DC

54193DM, 54LS193DM

68

Flatpak
(f)

A

74193FC, 74LS193FC

54193FM,54LS193FM

4L

A,

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L definitions
PIN NAMES
CPu
CPo
MR
PL

Po-P3
00-Q3

TCo
TCu

DESCRIPTION
Count Up Clock Input
(Active Rising Edge)
Count Down Clock Input
(Active Rising Edge)
Asynchronous Master Reset Input
(Active HIGH)
Asynchronous Parallel Load Input
(Active LOW)
Parallel Data Inputs
Flip-flop Outputs
Terminal Count Down (Borrow) Output
(Active LOW)
Terminal Count Up (Carry) Output
(Active LOW)

4-291

54/74 (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

1.0/1.0
20/10

0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)
10/5.0
(2.5)

20/10
20/10

193
STATE DIAGRAM

MODE SELECT TABLE
MR
H
L
L
L
L

PL CPU
X
L
H
H
H

CPO

MODE

X
X
H
H

X
X
H

S

Reset (AsynJ
Preset (AsynJ
No Change
Count Up
Count Down

S

H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

-COUNTUP
----COUNT DOWN

LOGIC EQUATIONS
FOR TERMINAL COUNT
TCu = Qo • Q1 • Q2 • Q3 • CPu
TCo = 00 •

01 • 02

• 03 • CPO

LOGIC DIAGRAM

Po
(LO AD)_"

-....

"

C Pu'"
(UP
COU NT)

r-

--l

~I-t

}-b }~,0' b
t: 1 it rL t= T "[Or--

Or--

T

0-

T

T

C PD
(DO WN
COU NT)"

...

~
(CLEAR)

TCu
(CA RRY
OUT PUT)

00

4-292

~

0'--

T

~

TCD
(BOR ROW
OUT PUT)

194
CONNECTION DIAGRAM
PINOUT A

54/74194
548/748194
54L8/74L8194A

-

MFiIT
DSRII

TIl 00

II

:E]01

Po

4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
DESCRIPTION - The '194 is a high speed 4-bit bidirectional universal shift
register. As a high speed multifunctional sequential building block, it is
useful in a wide variety of applications. It may be used in serial-serial,
shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data
register transfers. The '194 is similar in operation to the '195 universal
shift register, with added features of shift left without external connections
and hold (do nothing) modes of operation.

~vcc

p,!:!:

:m02

P21I

:m03

P31I

TIlcp

DSL[I

~S1

GND[!

:II So

LOGIC SYMBOL
• GUARANTEED SHIFT FREQUENCY OF 30 MHz (,LS194A)
OR 70 MHz (,5194)
• ASYNCHRONOUS MASTER RESET
• HOLD (DO NOTHING) MODE
• FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS

iriiil

ORDERING CODE: See Section 9
9~

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74194PC
74S194PC, 74LS194APC

98

Ceramic
DIP (D)

A

54194DM
74194DC,
74S194DC, 74LS194ADC 54S194DM,54LS194ADM

68

Flatpak
(F)

A

54194FM
74194FC,
74S194FC, 74LS194AFC 54S194FM, 54LS194AFM

4L

DSR Po P, P2 P3 DSL
SO

1 0 - s,
1 1 - CP

MR 00 0, 02 03

! }s L }3

1l

Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
So, S1
PO-P3
DSR
DSL
CP
MR
00-03

DESCRIPTION
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data I nput (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input
(Active LOW)
Parallel Outputs

4-293

54174 (U.L.)
HIGH/LOW

541745 (U.L.)
HIGH/LOW

54/74L5 (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0

1.25/1.25
1.0/1.0
1.0/1.0
1.0/1.0
1.25/1.25
1.25/1.25

0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25

20/10

25/12.5

10/5.0
(2.5)

•

194
FU NCTIONAL DESCRIPTION - The '194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to
the Select (So, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the
Select, Parallel data (Po - P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state,
provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed.
Synchronous state changes occur within 8.0 ns (typical, '194) or 15 ns (typical, 'LS194A), making the devices
especially useful for implementing high speed memory or CPU buffer registers. A LOW signal on Master Reset
(MR) overrides all other inputs and forces the outputs LOW.
MODE SELECT TABLE
OUTPUTS

INPUTS

OPERATING
MODE
Reset

MR

S1

So

L

X

DSR

DSL

X

X

X

Pn

00

01

02

03

X

L

L

L

L

Hold

H

I

I

X

X

X

qo

q1

q2

q3

Shift Left

H
H

h
h

I
I

X
X

I
h

X
X

q1
q1

q2
q2

q3
q3

L
H

Shift Right

H
H

I
I

h
h

I
h

X
X

X
X

L
H

qo
qo

q1
q1

q2
q2

Parallel Load

H

h

h

X

X

pn

po

P1

P2

P3

I = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
po (qol = Lower case letters indicate the state of the referenced input (or outputl one setup time
prior to the LOW-to-HIGH clock transition.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
P,

Po

s,---{>O~----~--~----~------~--~----~------~--~----~------~---r----,
SO---{~~----+-~+-~-4rl-------~--H-~--N-------~--H-ot--~------,---tr1t-,

r-Itt----t-- Dsc

DSR - - - - - - - - - - - - ,

cP---C~--------------~--~--t---------4----r--t---------4----r--+---------~

MR--~~------------------~--t-------------~--t-------------~--+-------------~
0,

00

4-294

194
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54/74
Min

lee

Max

54/74S
Min

63

Power Supply Current

Max

54/74LS
Min

135

UNITS

CONDITIONS

Max

23

mA

Vee = Max
Sn. MR. DSR.
DSL = 4.5 V
Pn = Gnd
CP=...r-

AC CHARACTERISTICS: Vee = +5.0 V. TA = +25 0 C (See Section 3 for waveforms and load configuration)
54/74
SYMBOL

PARAMETER

54/74S

54/74LS

CL = 15 pF CL = 15 pI': CL = 15 pF
RL = 400 0. RL = 280 0.
Min

Max

25

Min

Max

70

Min

UNITS

CONDITIONS

Max

f max

Maximum Shift Frequency

tPLH
tPHL

Propagation Delay
CP to an

22
26

8.0
12

30
21
24

MHz
ns

tPHL

Propagation Delay
MR to an

30

23

26

ns

Figs. 3-1. 3-16

UNITS

CONDITIONS

Figs. 3-1. 3-8

AC OPERATING REQUIREMENTS: Vee = +5.0 V. TA = +25 0 C
SYMBOL

PARAMETER

54/74
Min

Max

54/74S
Min

Max

54/74LS
Min

Max

ts (H)
ts (U

Setup Time HIGH or LOW
Pn or DSR or DSL to CP

20
20

6.0
6.0

16
16

ns

th (H)
th (U

Hold Time HIGH or LOW
Pn or DSR or DSL to CP

0
0

0
0

0
0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
Sn to CP

30
30

9.0
9.0

25
25

ns

th (H)
th (U

Hold Time HIGH or LOW
Sn to CP

0
0

0
0

0
0

ns

Fig. 3-6

tw (H)

CP Pulse Width HIGH

20

7.0

17

ns

tw (U

MR Pulse Width LOW

20

12

12

ns

tree

Recovery Time
MR to CP

25

5.0

18

ns

4-295

Fig. 3-8
Fig. 3-16

•

195
CONNECTION DIAGRAM
PINOUT A

54/74195
54LS/74LS195A

MFio:~tmvcc
J [!
till Qo
~Q1
KIT

UNIVERSAL 4-BIT SHIFT REGISTER

II

E]Q2

P1~

;mQ3

P2[!

]:leb

P3[I

~cp

GNO[!

~PE

Po

DESCRIPTION - The '195 is a high speed 4-bit shift register offering typical
shift frequencies of 50 MHz. It is useful for a wide variety of register and
counting applications. The '195 is pin and functionally identical to the 9300,
93LOO and 93HOO.

• TYPICAL SHIFT RIGHT FREQUENCY OF 50 MHz ('lS195A)
• ASYNCHRONOUS MASTER RESET
• J, K INPUTS TO FIRST STAGE
• FUllY SYNCHRONOUS SERIAL OR PARAllEL DATA TRANSFERS

lOGIC SYMBOL

1iii i
PE Po P, P2 P3

ORDERING CODE: See Section 9
PIN
PKGS

OUT

2-J

COMMERCIAL GRADE
Vee = +5.0 V ±5%,
TA = O°C to +70°C

MiliTARY GRADE

PKG

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

TYPE

Plastic
DIP (P)

A

74195PC, 74LS195APC

Ceramic
DIP (0)

A

74195DC, 74LS195ADC

54195DM,54LS195ADM

68

Flatpak
(F)

A

74195FC, 74LS195AFC

54195FM,54LS195AFM

4L

98

1 0 - CP
3--(l K

Q3

P-11

MR Qo Q1 Q2 Q3

I 11 I r
1 15 14 13 12

Vce = Pin 16
Gnd = Pin 8

INPUT lOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
PE
PO-P3
J

K
CP
MR
00-03

ch

DESCRIPTION
Parallel Enable Input (Active LOW)
Parallel Data Inputs
First Stage J Input (Active HIGH)
First Stage K Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
AsynchronolJs Master Reset Input
(Active LOW)
Parallel Outputs
Complementary Last Stage Output
(Active LOW)

4-296

54/74 (U.l.)
HIGH/LOW

54/74lS (U.l.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25

20/10

10/5.0
(2.5)
10/5.0
(2.5)

20/10

195
FUNCTIONAL DESCRIPTION - The Logic Diagram and Truth Table indicate the functional characteristics of
the '195 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It
performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The '195 has two primary modes of operation, shift right(Oo ~ 01) and parallel load, which are controlled by the
state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the firstflip-flop 00 via the J
and K inputs and is shifted one bit in the direction 00~01 ~02-+03 following each LOW-to-HIGH clock
transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D
type input for general applications by tying the two pins together. When the PE input is LOW, the '195 appears as
four common clocked D flip-flops. The data on the parallel inputs Po, P1, P2, P3 is transferred to the respective
00, 01, 02, 03 outputs following the LOW-to-HIGH clock transition. Shift left operation (03 ~02) can be
achieved by tying the On outputs to the Pn - 1 inputs and holding the PE input LOW.
All serial and parallel data transfers are synchronous, occuring after each LOW-to-HI GH clock transition. Since
the '195 utilizes edge-triggering, there is no restriction on the activity of the J, K. Pn and PE inputs for logic
operation - except for the setup and release time requirements. A LOW on the asynchronous Master Reset
(MR) input sets all 0 outputs LOW, independent of any other input condition.

MODE SELECT TABLE
OUTPUTS

INPUTS

OPERATING MODES

MR PE J

K

Pn

00

01

02

03

03

Asynchronous Reset

L

X

X

X

X

L

L

L

L

H

Shift,
Shift,
Shift,
Shift,

H
H
H
H

h
h
h
h

h
I
h
I

h
I
I
h

X
X
X
X

H
L
qo
qo

qo
qo
qo
qo

ql
q1
q1
ql

q2
q2
q2
q2

q2
q2
q2
q2

H

I

X

X

Pn

po

PI

P2

P3

;53

Set First Stage
Reset First Stage
Toggle First Stage
Retain First Stage

Parallel Load

H ; HIGH Voltage Level L; LOW Voltage Level X; Immatenal
I ; LOW voltage level one setup time prior to the LOW to HIGH clock transition.
h ; HIGH voltage level one setup time prior to the LOW to HIGH clock transition.
Pn (qn); Lower case letters indicate the state of the referenced input (or output) one setup time prior to
the LOW to HIGH clock transition.

LOGIC DIAGRAM
PE

J

K

P,

Po

P3

00

4-297

MIl

CP

•

195
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

54/74

Min
lee

Power Supply Current

Max

54174LS

Min

63

UNITS

CONDITIONS

Max
21

mA

Vee = Max, PE = Gnd
J,
Pn, MR = 4.5 V
CP =-.r

K

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74
SYMBOL

PARAMETER

54/74LS

CL = 15 pF CL = 15 pF
RL = 400 n
Min

Max

30

Min

UNITS

CONDITIONS

Max

30

f max

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to an

22
26

21
24

ns

tPHL

Propagation Delay, MR to an

30

26

ns

MHz

Figs. 3-1, 3-8

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

54/74

Min

Max

54/74LS

Min

UNITS

ts (H)
ts (U

Setup Time HIGH or LOW
J, K or Pn to CP

20
20

15
15

ns

th (H)
th (U

Hold Time HIGH or LOW
J, K or Pn to CP

0
0

0
0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
PE to CP

25
25

25
25

ns

th (H)
th (U

Hold Time HIGH or LOW
PE to CP

-10
-10

0
0

ns

tw (H)

CP Pulse Width HIGH

16

16

ns

tw (U

MR Pulse Width LOW

12

12

ns

tree

Recovery Time, MR to CP

25

20

ns

4-298

CONDITIONS

Max

Fig. 3-6

Fig. 3-8
Fig. 3-16

196
CONNECTION DIAGRAM
PINOUT A

54/74196
54LS/7 4LS 196

DESCRIPTION - The '196 decade ripple counter is partitioned into divideby-two and divide-by-five sections which can be combined to count either in
BCD (8421) sequence or in a bi-quinary mode producing a 50% duty cycle
output. Both circuit types have a Master Reset (MR) input which overrides all
other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PU overrides clocked operations and asynchronously loads the data on
the Parallel Data inputs (P n ) into the flip-flops. This preset feature makes the
circuits usable as programmable counters. The circuits can also be used as
4-bit latches, loading data from the Parallel Data inputs when PL is LOW and
storing the data when PL is HIGH. In the counting modes, state changes are
initiated by the falling edge of the clock.

• HIGH COUNTING RATES-TYPICALLY 60 MHz
• CHOICE OF COUNTING MODES-BCD, BI-QUINARY, BINARY
• ASYNCHRONOUS PRESET AND MASTER RESET

PIN
OUT

;El Vee

od}:
pdI

EJMR

Po [I

TIl P3

EJ03

[I

JE] P,

CP1[I

}l01

00

GNolI

]JCPo

LOGIC SYMBOL

1

4

10 3 11

bll I I
PL Po P, P2 P3

ORDERING CODE: See Section 9

PKGS

-

PiC!:

PRESETTABLE DECADE COUNTERS

8--(l CPa

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74196PC, 74LS196PC

Ceramic
DIP (0)

A

74196DC, 74LS196DC

54196DM,54LS196DM

6A

Flatpak
(F)

A

74196FC, 74LS196FC

54196FM,54LS196FM

31

9A

6--(l CP,

MR 00 0, 0203

Y I I 2I 12I

13

5

Vce

=

9

Pin 14

GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CPo
CP1
MR
PO-P3

PI.
00- 03*

54174 (U.L.)
HIGH/LOW

DESCRIPTION
+2 Section Clock Input
(Active Falling Edge)
+5 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Input
(Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input
(Active LOW)
Flip-flop Outputs*

'00 is guaranteed to drive the full rated fan-out plus the CP1 input.

4-299

54174LS (U.L.)
HIGH/LOW

2.0/3.0

1.0/1.5

3.0/4.0

2.0/1.75

2.0/2.0

1.0/0.5

1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25

20/10

10/5.0
(2.5)

196
FUNCTIONAL DESCRIPTION - The '196 and '197 are asynchronous presettable decade and binary ripple
counters. The '196 decade counter is partitioned into divide-by-two and divide-by-five sections while the '197 is
partitioned into divide-by-two and divide-by-eight sections, with all sections having a separate Clock input. In
the counting modes, state changes are initiated by the HIGH-to-LOW transition of the clock signals. State
changes of the 0 outputs, however, do not occur simultaneously because of the internal ripple delays. When
using external logic to decode the 0 outputs, designers should bear in mind that the unequal delays can lead to
decodi ng spikes and thus a decoded signal should not be used as a clock or strobe. The CPo input serves the 00
flip-flop in both circuit types while the CP1 input serves the divide-by-five or divide-by-eight section. The 00
output is designed and specified to drive the rated fan-out plus the CP1 input. With the input frequency
connected to CPo and with 00 driving CP1, the '197 forms a straight forward modul0-16 counter, with 00 the
least significant output and 03 the most significant output.
The '196 decade counter can be connected up to operate in two different count sequences. With the input
frequency connected to CPo and with 00 driving CP1, the circuit counts in the BCD (8421) sequence. With the
input frequency connected to CP1 and 03 driving CPo, 00 becomes the low frequency output and has a 50%
duty cycle waveform. Note thatthe maximum counting rate is reduced in the latter (bi-quinary) configuration
because of the interstage gating delay within the divide-by-five section.
The '196 and '197 have an asynchronous active LOW Master Reset input (MR) which overrides all other inputs
and forces all outputs LOW. The counters are also asynchronously presettable. A LOW on the Parallel Load
input (PL.) overrides the clock inputs and loads the data from Parallel Data (Po - P3) inputs into the flip-flops.
While PL is LOW, the counters act as transparent latches and any change in the Pn inputs will be reflected in the
outputs. In order for the intended parallel data to be entered and stored, the recommended setup and hold times
with respect to the rising edge of PL should be observed.

LOGIC DIAGRAM

MR

--~--------ol)~~~------------~+-~--------~r-----------,

Pl ------<01..-'

J So

CPo

a

------------r~

KCOat-t--f---J
CPl ---------------------4_----~------------+_--------4_~
00

4-300

196
+5 STATE

DIAGR~M

BCD STATE DIAGRAM

211
3

10

4112
3

6

.

5

~
MODE SELECT TABLE
INPUTS

RESPONSE

MR

PL

CP

L
H
H

X

X
X

L
H

On forced LOW
Pn-On
Count Up

1..

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARMETER

Min

hH

Input HIGH Current

Ice

Power Supply Current

CPo
'196 CP
'197 CP1

Max

54174LS
Min

UNITS

CONDITIONS

Max

1.0
1.0
1.0

0.2
0.4
0.2

rnA

Vee = Max, VIN = 5.5 V

59

20

rnA

Vee = Max
All Inputs = Gnd

4-301

196
AC CHARACTERISTICS: Vee

= +5.0 V,

TA

= +25°C (See Section 3 for waveforms and
54174

SYMBOL

54174LS

CL = 15 pF CL
RL = 400 n

PARAMETER

Min

Max

load configurations)

= 15 pF

Min

UNITS

CONDITIONS

Max

f max

Maximum Count
Frequency at CPo

'196
'197

50
50

45
50

MHz

Figs. 3-1, 3-9

f max

Maximum Count
Frequency at CP1

'196
'197

25
25

22.5
25

MHz

Fig. 3-9

tPLH
tPHL

Propagation Delay
CPo to 00

12
15

12
12

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 01

18
21

14
14

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 02

'196

36
42

34
32

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 02

'197

36
42

36
34

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 03

'196

21
18

18
18

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
CP1 to 03

'197

54
63

50
55

ns

Figs. 3-1, 3-9

tPLH
tPHL

Propagation Delay
Pn to On

24
38

15
35

ns

Figs. 3-2, 3-5

tPLH
tPHL

Propagation Delay
PL to On

33
36

24
35

ns

Figs. 3-1, 3-17

tPHL

Propagation Delay
MR to On

37

37

ns

Figs. 3-1, 3-17

AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

TA

= +25°C

54174

PARAMETER

Min

Max

54174LS

Min

UNITS

CONDITIONS

Max

ts (H)
ts (U

Setup Time HIGH or LOW
Pn to PL

10
15

8.0
12

ns

Fig. 3-;13

th (H)
th (U

Hold Time HIGH or LOW·
Pn to PL

0
0

0
6.0

ns

Fig. 3-13

tw (H)

CPa Pulse Width HIGH

'196
'197

20
20

12
10

ns

Fig. 3-9

tw (H)

CP1 Pulse Width HIGH

'196
'197

30
30

24
20

ns

Fig. 3-9

tw (U

PL Pulse Width LOW

20

18

ns

Fig. 3-17

tw (U

MR Pulse Width LOW

15

12

ns

Fig. 3-17

tree

Recovery Ti me
PL to CPn

20

16

ns

Fig. 3-17

tree

Recovery Time
MR to CPn

20

18

ns

Fig. 3-17

4-302

197
CONNECTION DIAGRAM
PINOUT A

54/74197
54LS/74LS197

pLIT

PRESETTABLE BINARY COUNTERS

adI

PoE!

~vcc
~MR
~a3
~P3

ao[I

~P'

cp,[I

~a,

~

DESCRIPTION - The '197 ripple counter contains divide-by-two and divideby-eight sections which can be combined to form a modul0-16 binary
counter. State changes are initiated by the falling edge of the clock. The '197
has a Master Reset (M R) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PU overrides clocked
operations and asynchronously loads the data on the Parallel Data inputs (Pn)
into the flip-flops.This preset feature makes the circuit usable as a programmable counter. The circuit can also be used as a 4-bit latch, loading data from
the Parallel Data inputs when PL is LOW and storing the data when PL is
HIGH. For detail specifications and functional description, please refer tothe
'196 data sheet.

pdI

LOGIC SYMBOL

• HIGH COUNTING RATES-TYPICALLY 70 MHz
• ASYNCHRONOUS PRESET
• ASYNCHRONOUS MASTER RESET

1

PKGS

OUT

4 10

~.lJ

PL Po
8-0 CPo

ORDERING CODE: See Section 9
PIN

~CPo

GNOIT .

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74197PC, 74LS197PC

Ceramic
DIP (D)

A

74197DC, 74LS197DC

54197DM,54LS197DM

6A

Flatpak
(F)

A

74197FC, 74LS197FC

54197FM,54LS197FM

31

9A

6-0

p,

3 11

II

P2 P3

cp,
MR ao Q, Q2 a3

~

IIII

13 5

9

2 12

Vee = Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

54174 (U.L.)
HIGH/LOW

DESCRIPTION

00

+2 Section Clock Input
(Active Falling Edge)
+8 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Input
(Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input
(Active LOW)
+2 Section Output-

01-03

+8 Section Outputs

CPo
CP1
MR
PO-P3
PL

2.0/3.0

1.0/1.5

2.0/2.0

1.0/0.81

2.0/2.0

1.0/0.5

1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25

20/10

10/5.0
(2.5)
10/5.0
(2.5)

20/10

*00 output is guaranteed to drive the full rated fan-out plus the CP1 input.

4-303

54174LS (U.L.)
HIGH/LOW

•

197
+ 16 STATE DIAGRAM

MODE SELECTION TABLE
INPUTS
MR

PL

CP

L
H
H

X
L
H

X
X

'--

RESPONSE
an forced LOW
Pn ...·O n
Count Up

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
Po

P3

PL

CPo

--------------+-~I

00

4-304

198
CONNECTION DIAGRAM
PINOUT A

54/74198
8-BIT RIL SHIFT REGISTER
DESCRIPTION - The '198 features synchronous parallel load, hold, shift
right and shift left modes, as determined by the Select (So, Sl) inputs. State
changes are initiated by the rising edge of the clock. An asynchronous Master
Reset (MR) input overrides all other inputs and clears the register. The '198
is useful for serial-serial, serial-parallel, parallel-serial and parallel-parallel
register transfers.

•
•
•
•

PARALLEL IN/PARALLEL OUT
SYNCHRONOUS PARALLEL LOAD
SHIFT RIGHT AND SHIFT LEFT CAPABILITY
ASYNCHRONOUS OVERRIDING CLEAR

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

solI

-

Pol!

!Bl0SL

~P7

oo[!
P,[I

1m 07

a, II
pdI

!BP6

02 [I
P3l!:

illps
mas

03[2

E]P4

cP[jJ:

E]04

!!J06

IT)MR

GNO [j1

PKG
TYPE

Plastic
DIP(P)

A

74198PC

Ceramic
DIP (0)

A

74198DC

54198DM

6N

Flatpak
(F)

"A

74198FC

54198FM

4M

9N

INPUT LOADING/FAN-OUT: See Section 3 for U.l. definitions
PIN NAMES

So, Sl
Po-P7
DSR
DSL
CP
MR

00-07

54/74 (U.L.)
HIGH/LOW

DESCRIPTION
Mode Select Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Flip-flop Outputs

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
20/10

LOGIC SYMBOL

iii I i 'j Y'j 22j
1'

DSR Po p, P2 P3 P4 P5 P6 P7 OSL

,- So

23- S,
,,- CP
Mil 00 A, 02 03 04 AS 06 07

I 1 ! !,~ L,161 8L
1

4-305

~vcc

~s,

OSR[I

Vcc = Pin 24
GND = Pin 12

•

198
FUNCTIONAL DESCRIPTION - The '198 contains eight edge-triggered D-type flip-flops and the interstage
gating required to perform synchronous parallel load, shift right, and shift left operations. Serial data enters at
DSR for shift right and at DSl for shift left operations. Parallel data is applied to the Po - P7 inputs. State
changes are initiated by the rising edge of the clock. The DSR, DSl and Po - P7 inputs can change when the
clock is in either state, provided only that the recommended setup and hold times are observed.

The operating mode is determined by So and S" as shown in the Mode Select Table. Clocking of the flip-flops is
inhibited when both So and S, are LOW. To avoid inadvertently clocking the register, the Select inputs should
only be changed while CP is HIGH. A LOW signal on MR overrides all other inputs and forces the outputs LOW.

MODE SELECT TABLE

INPUTS

RESPONSE

So'

S,'

X

X

X

X

H
L
H
L

H
H
L
L

MR

CP

L
H
H
H
H

...r
...r
...r

Asynchronous Reset; Outputs = LOW
Parallel Load; Pn-On
Shift Right; DSR--OO, 00--0" etc .
Shift Left; DSl-07, 07--06, etc.
Hold

'Select inputs should be changed only while CP is HIGH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

DSR

P5

Po

Pe

P7 DSL

So~~-------+--~~-----+-r----~~------+4r-----~~-----r;-----~'~------r.

4-306

198
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER
Min

lee

Power Supply Current

I

I

UNITS

CONDITIONS

Max

XC
XM

116
104

rnA

Vee = Max; So, S, = 4.5 V
CP =.s ; MR, Pn = Gnd

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

54/74
SYMBOL

PARAMETER

CL = 15 pF
RL=400n
Min

f max

Maximum Shift Frequency

tPLH
tPHL

Propagation Delay
CP to Q n

tPHL

Propagation Delay
MR to Q n

UNITS

CONDITIONS

Max

25

MHz

Figs. 3-1, 3-8

26
30

ns

Figs. 3-1, 3-8

35

ns

Figs. 3-1,3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54/74

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time HIGH or LOW
Pn, DSL, DSR to CP

20
20

ns

th (H)
th (U

Hold Time HIGH or LOW
Pn, DSL, DSR to CP

0
0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
So or S, to CP

30
30

ns

th (H)
th (U

Hold Time HIGH or LOW

So or S, to CP

0
0

ns

tw (H)

CP Pulse Width HIGH

20

ns

Fig. 3-8

tw (U

MR Pulse Width LOW

20

ns

Fig. 3-16

4-307

Fig. 3-6

I

199
CONNECTION DIAGRAM
PINOUT A

54/74199
8-BIT PARALLEL liD SHIFT REGISTER
DESCRIPTION - The '199 is a parallel in, parallel out register featuring
synchronous parallel load, shift right and hold modes. State changes are
initiated by the rising edge of the clock. Serial entry into the first stage is via
J and K inputs for maximum flexibility. Two clock inputs are provided and it
is possible to use one as an inhibit. An asynchronous Master Reset(MR) input
overrides all other inputs and clears the register.
• PARALLEL IN/PARALLEL OUT
• SYNCHRONOUS PARALLEL LOAD
• ASYNCHRONOUS OVERRIDING CLEAR
• JK ENTRY TO FIRST STAGE
ORDERING CODE: See Section 9

PKGS

PIN
OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

r----------------+--------------~ PKG
TYPE

Plastic
DIP (P)

A

74199PC

Ceramic
DIP (0)

A

74199DC

54199DM

6N

Flatpak
(F)

A

74199FC

54199FM

4M

9N

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

K
J
Po-P7
CP1, CP2
MR
PE
00-Q7

54174 (U.L.)
HIGH/LOW

DESCRIPTION

PIN NAMES

Serial Data Input (Active LOW)
Serial Data Input (Active HIGH)
Parallel Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Enable Input (Active LOW)
Flip-flop Outputs

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
20/10

LOGIC SYMBOL
23

3

5

7

9

16 18 20 22

PE Po P1 P2 P3 P4 Ps P6 py

13
11

Vcc = Pin 24
GND = Pin 12
14

4

6

8

10 15 17 19 21

4-308

199
FUNCTIONAL DESCRIPTION - The '199 contains eight edge-triggered O-type flip-flops and the interstage
gating required to perform synchronous parallel load and shift right operations. Parallel input data is applied to
the Po - P7 inputs, while serial entry to 00 is via J and K. State changes are initiated by the rising edge of the
clock. The J, K Po - P7 and PE inputs can change while the clock is in either state, provided only that the
recommended setup and hold times are observed.
Either CP input can be used as the clock; if one is not used it must be tied LOW. One CP input can be used to
inhibit the other by applying a HIGH signal, but this should only be done while the other CPis in the HIGH state
or else false triggering may result. A LOW signal on MR overrides all other inputs and forces the outputs LOW.

MODE SELECT TABLE
INPUTS

RESPONSE

MR

PE

CP1* CP2*

L

X

X

X

Asynchronous Reset; Outputs = LOW

H
H

X
X

H
X

X
H

Hold

H
H

L
L

J

L

H
H

H
H

L
J

J
L

J

L

Parallel Load; Pn -

•

an

Shift Right, 00-01,01-02. etc.

*See discussion for precautions on CP changes

H ; HIGH Voltage Level
L; LOW Voltage Level
X ; Immaterial

SERIAL ENTRY TABLE
(MR = PE = I.IIGH)
INPUTS
J

K

L
L
H
H

L
H
L
H

*tn, tn

+ 1

00 at tn

+

1*

L
00 at tn (No Change)
00 at tn (Toggles)
H

= time

before, after rising CP edge

LOGIC DIAGRAM
Po

Ps

Ps

~==~~:t1---~L----1----~--~1----J----~--~

PE~~~--~++-tt--~---++-~r---H---~--++--~--~---r---+~~--~4---.

MR~~~----~--~---+--~--~~~----+-~----~--~---+--~--~--~

00

Os

4-309

Os

199
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER
Min
XC

Icc

XM

= +5.0 V,

TA

CONDITIONS

mA

Vee = Max; J, K, Pn = 4.5 V
CP1 =I
CP2, MR, PE = Gnd

116

Power Supply Current

AC CHARACTERISTICS: Vee

UNITS
Max

104

= +25°C (See Section 3 for waveforms and

load configurations)

54/74
SYMBOL

PARAMETER

CL
RL

= 15 pF
= 400 n

Min
fmax

Maximum Shift Frequency

tPLH
tPHL

Propagation Delay
CP1 or CP2 to On

tPHL

Propagation Delay
MR to On

UNITS

CONDITIONS

Max

25

MHz

Figs. 3-1, 3-8

26
30

ns

Figs. 3-1, 3-8

35

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54/74

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time HIGH or LOW
Pn, K, J to CP

20
20

ns

th (H)
th (U

Hold Time HIGH or LOW
Pn , K, J to CP

0
0

ns

ts (H)
ts(U

Setup Time HIGH or LOW
PE to CP

30
30

ns

th (H)
th (U

Hold Time HIGH or LOW
PE to CP

0
0

ns

tw (H)

CP Pulse Width HIGH

20

ns

Fig. 3-8

tw (U

MR Pulse Width LOW

20

ns

Fig. 3-16

4-310

Fig. 3-6

240 • 241 • 244
CONNECTION DIAGRAMS
PINOUT A

OE,II
£!

54S/74S240 • 54LS/74LS240
54S/74S241 • 54LS/74LS241
54LS/74LS244

II
E
!!
[!

OCTAL BUFFER/LINE DRIVER

IT

(With 3-State Outputs)

[!

[!
GNDffi

-

iID Vee

\~

~~
\~
~~

ti!I OE,
:l!l
~
~

~
~
~

fm

~

PINOUT B
DESCRIPTION - The '240, '241 and '244 are octal buffers and line drivers
designed to be employed as memory address drivers, clock drivers and bus
oriented transmitters/receivers ~hich provide improved PC board density.
• HYSTERESIS AT INPUTS TO IMPROVE NOISE MARGINS
• 3-STATE OUTPUTS DRIVE BUS LINES OR BUFFER
MEMORY ADDRESS REGISTERS
• OUTPUTS SINK 24 mA (74LS) OR 40 mA(74S)
• 15 mA SOURCE CURRENT
• INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS
• FULLY TTL AND CMOS COMPATIBLE
ORDERING CODE: See Section 9

OE'l.!.

£!
II
E
!!
[!

IT
II
II
GNDffi

PIN
PKGS

OUT

Plastic
DIP(P)

Ceramic
DIP (0)

Flatpak
(F)

A

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V, ±5%,
TA = O°C to +70°C

Vee = +5.0 V, ±10%,
TA = -55°C to +125°C

-

iID Vee

~~
~~
~ri
~~

:!!JOE,
1!l
TIl
1!l

m
El

1lI

:rn
'i1]

PKG

OEl[! f-ot>--

74S240PC, 74LS240PC

B

74S241 PC, 74LS241PC

C

74LS244PC

A

74S240DC, 74LS240DC

54S240DM,54LS240DM

B

74S241 DC, 74LS241DC

54S241 OM, 54LS241DM

C

74LS244DC

54LS244DM

A

74S240FC, 74LS240FC

54S240FM, 54LS240FM

B

74S241FC, 74LS241FC

54S241FM,54LS241FM

C

74LS244FC

54LS244FM

PINOUT C

TYPE

9Z

4E

11
II
E
!!
I!
IT

~vcc

t!~=:=

rLX+-

~~~ m

[i H>--__
L

~

GNDffi

El
'ij]

:rn

19
4F

:!!JOE,
1!l
TIl
1!l

~

111

INPUT LOADING/FAN-OUT: See Section 9
PIN NAMES
OE1,OE2
OE2

54174S (U.L.)

DESCRIPTION
3-State Output Enable (Active LOW)
3-State Output Enable (Active HIGH)
Inputs
Outputs

4-311

HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.25/1.25
1.25/1.25
1.25/0.25
75/40
(30)

0.5/0.25
0.5/0.25
0.5/0.125
75/15
(7.5)

240 • 241 • 244
TRUTH TABLES

'S240, 'LS240
INPUTS

INPUTS

OUTPUT

OE1,01:2

0

L
L

L
H
X

H

'S241, 'LS241

H
L

Z

H = HIGH Voltage Level

'LS244
INPUTS

OUTPUT

OEl 01:2

0

L
L
H

L
H
X

H
H
L

OE1,01:2
L
H

L
L
H

Z

L = LOW Voltage Level

X = Immaterial

Z

OUTPUT

0
L
H
X

L
H

Z

= High Impedance

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74S

DESCRIPTION

Min

VOH

Output HIGH Voltage

Max

54/74LS
Min

I XM
XC

2.0
2.0

2.0
2.0

V

I XM
XC

2.4
2.4

2.4
2.4

V

XC

2.7

2.7

V

~
VOL

0.4
0.4
0.5

~
XC

Output LOW Voltage

0.55
0.55

XM

rxc
los

Output Short Circuit Current

('240)
HIGH ('241)

('244)

lee

Power
Supply
Current

('240)
LOW ('241)

('244)
('240)
OFF ('241)

('244)

UNITS

XM
XC
XM
XC
XM
XC
XM
XC
XM
XC
XM
XC
XM
XC
XM
XC
XM
XC

-50

-225
123
135
147
160

145
150
170
180

145
150
170
180

4-312

V
V

-40

CONDITIONS

Max

-225
23
23
23
23
23
23
44
44
46
46
46
46
50·
50
54
54
54
54

VIH = 2.0 V
10H = -12 rnA
VIL = 0.5 V
10H = -15 rnA
Vee = Min
Vee = Min, VIH = 2.0 V
VIL = Max, 10H = -3.0 rnA
Vee - Min, VIH - 2.0 V
VIL = Max, 10H = -1.0 rnA
10L
IOL
10L
10L
IOL

= 12
= 12
=24
- 48
-64

rnA
rnA
rnA
rnA
rnA

rnA

Vee = Max

rnA

Vee = Max

rnA

Vee = Max

rnA

Vee = Max

Vee = Min
Vee = Min

240 • 241 • 244
AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74S
SYMBOL

PARAMETER

54/74LS

CL = 50 pF CL = 50 pF
RL=90n
Min

Max

Min

UNITS

Max

tPLH
tPHL

Propagation Delay
Data to Output ('240)

7.0
7.0

14
18

ns

tPLH
tPHL

Propagation Delay
Data to Output ('241)

9.0
9.0

18
18

ns

tPLH
tPHL

Propagation Delay
Data to Output ('244)

18
18

ns

tPZH
tPZL

Output Enable Time
('S240)

10
15

tPZH
tPZL

Output Enable Time
('LS240, 'LS241, 'S241)

12
15

tPLZ
tPHZ

Output Disable Time

15
9.0

4-313

CONDITIONS

Figs. 3-1, 3-4

Figs. 3-1, 3-5

ns

Figs. 3-3, 3-11, 3-12

23
30

ns

Figs. 3-3, 3-11, 3-12
RL = 667 n (,LS)

25
18

ns

Figs. 3-3, 3-11, 3-12
RL = 667 n, CL = 5 pF (,LS)

•

242 • 243
CONNECTION DIAGRAMS
PINOUT A

54LS/74LS242
54LS/74LS243
QUAD BUS TRANSCEIVER
(With 3-State Outputs)

'E{I r---ot>-NcII

IT
II
IT
II

EJvcc

-

r----~--~+----H~--+H----~---+~--~~--~
So

OE

z

4-322

Z

251
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

los

Output Short Circuit Current

lee

Power Supply
Current

54174S

54174LS

Min

Max

Min

Max

-40

-100

-20

-100
10

Outputs ON
Outputs OFF

85

UNITS

CONDITIONS

mA

Vee = Max

mA

Vee = Max; In, Sn = 4.5 V
OE = Gnd
Vee = Max; OE, In = 4.5 V

12

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174S
SYMBOL

PARAMETER

54/74LS

CL = 15 pF CL = 15 pF
RL = 280!1
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Sn to Z

15
13.5

23
33

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
Sn to Z

18
19.5

45
30

ns

Figs. 3-1, 3-20

tPLH
tpHL

Propagation Delay
In to Z

12
12

28
26

ns

Figs. 3-1, 3-5

tpLH
tPHL

Propagation Delay
In to Z

7.0
7.0

15
15

ns

Figs. 3-1, 3-4

tPZH
tPZL

Output Enable Time
OE to Z orZ

19.5
21

20
25

ns

Figs. 3-3, 3-11,3-12
RL = 2 k!1 ('LS251)

tPHZ
tPLZ

Output Disable Time
OE to Z orZ

8.5
14

25
20

ns

Figs. 3-3, 3-11, 3-12
RL = 2 k!1 ('LS251)
CL = 5 pF

4-323

•

253
CONNECTION DIAGRAM
PINOUT A

54S/74S253
54LS/74LS253
DUAL 4-INPUT MULTIPLEXER
(With 3-State Outputs)
DESCRIPTION - The '253 is a dual 4-input multiplexer with 3-state outputs.
It can select two bits of data from four sources using common select inputs.
The outputs may be individually switched to a high impedance state with a
HIGH on the respective Output Enable (OE) inputs, allowing the outputs to
interface directly with bus oriented systems. It is fabricated with the Schottky
barrier diode process for high speed and is completely compatible with all
Fairchild TTL families.
• SCHOTTKY PROCESS FOR HIGH SPEED
• MULTIFUNCTION CAPABILITY
• NON-INVERTING 3-STATE OUTPUTS

OEa

C!:

sdI
loa

IT

~

till Vee
~OEb
!ElSa

i1a

IT
IT

lOa

[I

~i1b

Za

IT

:I2] lab

GNO!I

]JZb

12a

TIl lob
J] 12b

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74S253PC, 74LS253PC

Ceramic
DIP (D)

A

74S253DC, 74LS253DC

54S253DM, 54LS253DM

68

Flatpak
(F)

A

74S253FC, 74LS253FC

54S253FM, 54LS253FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
lOa -l3a
lOb -13b
So, S1
OEa
OEb
la, Zb

DESCRIPTION

54/74S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

1.25/1.25
1.25/1.25
1.25/1.25
1.25/1.25
1.25/1.25
162/12.5
(50l

0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
65/5.0
(25)/(2.5)

Side A Data Inputs
Side 8 Data Inputs
Common Select Inputs
Side A Output Enable Input (Active LOW)
Side 8 Output Enable Input (Active LOW)
3-State Outputs

1 iii i T1f 1j Y~

LOGIC SYMBOL

OEa lOa l'a 12a loa lab i1b 12b lob OEb

14-

So

2 - S,
Za

Zb

!

!
4-324

VCC = Pin 16
GND = Pin 8

253
FUNCTIONAL DESCRITION - This device contains two identical 4-input multiplexers with 3-state outputs.
They select two bits from four sources selected by common select inputs(So, Sl). The4-input multiplexers have
individual Output Enable (OEs, OEb) inputs which when HIGH, force the outputs to a high impedance (high Z)
state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown
below:

Za = OEs • (lOa • 81 • So + ha • 51 • So + 12a • Sl • So + 13a • Sl • So)
Zb

= OEb

• (lab • 51 •

&> + hb • 81 • So + 12b

• Sl •

&> + 13b

• Sl • So)

If the outputs of 3-state devices are tied together, all but one device must be i n the high impedance state to avoid
high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to
3-state devices whose outputs are tied together are designed so that there is no overlap.

TRUTH TABLE
SELECT
INPUTS

DATA INPUTS

OUTPUT
OUTPUT
ENABLE

So

Sl

10

h

12

13

OE

Z

X
L
L
H

X
L
L
L

X
L
H
X

X
X
X
L

XX
X
X

X
X
X
X

H
L
L
L

(Z)
L
H
L

H
L
L
H
H

L
H
H
H
H

X
X
X
X
X

H
X
X
X
X

X
L
H
X
X

X
X
X
L
H

L
L
L
L
L

H
L
H
L
H

Address inputs So and 8, are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
(Z)= High Impedance

LOGIC DIAGRAM

4-325

253
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
los

lee

PARAMETER
Output Short Circuit Current

Power Supply
Current

54/74S

54/74LS

Min

Max

Min

Max

-40

-100

-20

-100

Outputs HIGH

70

Outputs LOW

80

12

Outputs OFF

100

14

UNITS

CONDITIONS

mA

Vee = Max

mA

Vee = Max, OEn = Gnd
In, Sn = 4.5 V
Vee = Max
In Sn OEn = Gnd
Vee = Max, OEn = 4.5 V
In, Sn = Gnd

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74S
SYMBOL

PARAMETER

54/74LS

CL = 15 pF CL = 15 pF
RL = 280 D
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Sn to Zn

18
18

29
24

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
In to Zn

9.0
9.0

20
15

ns

Figs. 3-1, 3-5

tPZH
tPZL

Output Enable Time

19.5
21

22
22

ns

Figs. 3-3, 3-11, 3-12
RL=2kD,CL=15pF
('LS253); CL =50 pF('S253)

tPHZ
tPLZ

Output Disable Time

8.5
14

32
22

ns

Figs. 3-3, 3-11,3-12
RL = 2 kD, ('LS253)
CL = 5 pF

4-326

256
CONNECTION DIAGRAM
PINOUT A

54LS/74LS256
DUAL 4-BIT ADDRESSABLE LATCH

-

Aou

DESCRIPTION - The '256 is a dual 4-bit addressable latch with common
control inputs; these include two Address inputs (Ao, A1), an active LOW Enable input (E) and an active LOW Clear input (Cll. Each latch has a Data input (D) and four outputs (00 - 031.

P1JCi

D,I1

~E

Q2a[!

~Db
~Q3b
~Q2b

Q3aU

~Qlb

GND[!

~QOb

OoaC!
Qla[!

When the Enable@ is HIGH and the Clear input (CLl is LOW, all outputs (00.03) are LOW. Dual 4-channel demultiplexing occurs when the CL and E are
both LOW. When CL is HIGH and Eis LOW, the selected output (00-03),
determined by the Address inputs, follows D. When the Egoes HIGH, the contents of the latch are stored. When operating in the addressable latch mode
(E = LOW, CL = HIGH), changing more than one bit of the Address (Ao, A1)
could impose a transient wrong address. Therefore, this should be done only
while in the memory mode (E = CL = HIGHI.
SERIAL-TO-PARALLEL CAPABILITY
OUTPUT FROM EACH STORAGE BIT AVAILABLE
RANDOM (ADDRESSABLE) DATA ENTRY
EASILY EXPANDABLE
ACTIVE LOW COMMON CLEAR

•
•
•
•
•

LOGIC SYMBOL

i

D,

2

6
E

Ao
A,

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = 0° C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

CL

PKG
TYPE

Plastic
DIP (P)

A

74LS256PC

Ceramic
DIP (D)

A

74LS256DC

54LS256DM

6B

Flatpak
(F)

A

74LS256FC

54LS256FM

4L

9B

~vcc

Al[!

115

1

Ir
E

A,
CL

OOa Q, a Q2a 03a

QObQlbQ2bQ3b

1! l

! 1~ )1 1~

!
Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

CL
00a-03a

Common Address Inputs
Data Inputs
Common Enable Input (Active LOW)
Conditional Clear Input (Active LOW)
Side A Latch Outputs

00b-03b

Side B Latch Outputs

Ao, A1
Da, Db

E

4-327

Db

Ao

54174LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
1.0/0.5
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

256
TRUTH TABLE
INPUTS

OUTPUTS

MODE

CL

E

Ao

A1

00

01

02

03

L

H

X

X

L

L

L

L

Clear

L
L
L
L

L
L
L
L

L
H
L
H

L
L
H
H

D
L
L
L

L
D
L
L

L
L
D
L

L
L
l
D

Demultiplex

H

H

X

X

01-1

01-1

01-1

01-1

Memory

H
H
H
H

L
L
L
L

L
H
L
H

L
L
H
H

D
01-1
01-1
01-1

01-1
01-1
01-1
D

Addressable
Latch

1-1

~

01-1
D
01-1
01-1

01-1
01-1
D
01-1

Bit time before address change or rising edge of E

H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial

MODE SELECTION
E

CL

L
H
L
H

H
H
L
L

MODE
Addressable Latch
Memory
Active HIGH 4-Channel Demultiplexers
Clear

LOGIC DIAGRAM

4-328

256
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

lee

UNITS

CONDITIONS

Max

Power Supply Current

25

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V. TA = +25 0 C (See Section 3 for waveforms an d load configurations)
54174LS
SYMBOL

PARAMETER

CL = 15 pF
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

E to

Propagation Delay
an

27
24

ns

Figs. 3-1. 3-9

tPLH
tPHL

Propagation Delay
Dn to an

30
20

ns

Figs. 3-1. 3-5

tPLH
tpHL

Propagation Delay
An to an

30
20

ns

Figs. 3-1. 3-20

tPHL

cL to an

18

ns

Figs. 3-1. 3-16

Propagation Delay

AC OPERATING REQUIREMENTS: Vee = +5.0 V. TA = +25 0 C
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH
Dn to E

20

ns

Fig. 3-13

th (H)

Hold Time HIGH
Dn to E

0

ns

Fig. 3-13

ts (U

Setup Time LOW
Dn lo E

15

ns

Fig. 3-13

th (U

Hold Time LOW
Dn to E

0

ns

Fig. 3-13

ts (H)
ts (U

Setup Time HIGH or LOW.
An to E

0

ns

Fig. 3-21

tw (U

E Pulse Width LOW

17

ns

Fig. 3-21

4-329

•

257
CONNECTION DIAGRAM
PINOUT A

54S/74S257
54LS/74LS257

sIT

QUAD 2-INPUT MULTIPLEXER

la·1I

:mOE

(With 3-State Outputs)

ha[!

TIl lac

z.1I

TIll"

DESCRIPTION - The '257 is a quad 2-input multiplexer with 3-state outputs.
Four bits of data from two sources can be selected using a Common Data
Select input. The four outputs present the selected data in true (non-inverted)
form. The outputs may be switc~ to a high impedance state with a HIGH
on the common Output Enable (OE) input, allowing the outputs to interface
directly with bus oriented systems. It is fabricated with the Schottky barrier
diode process for high speed.

-

:ill Vee

lObI:!

TIlZ,

hb[!

:TIlICd

Zb[!

~I'd

GND[!

~Zd

LOGIC SYMBOL
•
•
•
•

SCHOTTKY PROCESS FOR HIGH SPEED
MULTIPLEXER EXPANSION BY TYING OUTPUTS TOGETHER
NON-INVERTING 3-STATE OUTPUTS
INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINAT10N EFFECTS

! iii ri Y'f Y

OE lOa 11a lOb 11b IOc 11c IOd hd

'-$

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74S257PC, 74LS257PC

Ceramic
DIP (0)

A

74S257DC, 74LS257DC

54S257DM, 54LS257DM

68

A

74S257FC, 74LS257FC

54S257FM, 54LS257FM

4L

Flatpak
(F)

Za

Zb

Z,

Zd

! ! ,l !

98
Vee = Pin 16
Gnd = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
S
OE
lOa-lad
ha-hd

Za-Zd

DESCRIPTION
Common Data Select Input
3-State Output Enable Input
(Active LOW)
Data Inputs from Source 0
Data Inputs from Source 1
Multiplexer Outputs

4-330

54/74 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

2.5/2.5
1.25/1.25

1.0/0.5
0.5/0.25

1.25/1.25
1.25/1.25
162/12.5
(50l

0.5/0.25
0.5/0.25
65/5.0
(25)/(2.5)

257
FUNCTIONAL DESCRIPTION - This device is a quad 2-input mulitplexer with 3-state outputs. It selects four
bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the
lox inputs are selected and when Select is HIGH, the hx inputs are selected. The data on the selected inputs
appears at the outputs in true (non-inverted) form. The device is the logic implementation of a 4-pole, 2-position
switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic
equations for the outputs are shown below:

Za = OE • (ha • S
Ze =

OE •

(he •

S

+ loa. S)
+ 10e • S)

Zb = OE • (hb • S
Zd = OE • (hd • S

+ lOb. S)
+ 10d • S)

When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance OFF state. If the
outputs are tied together, all but one device must be in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so there is no overlap.

TRUTH TABLE
DATA
INPUTS

OUTPUT
ENABLE

SELECT
INPUT

OE

S

10

h

Z

H
L
L
L
L

X
H
H
L
L

X
X
X
L
H

X
L
H
X
X

(Z)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
(l)= High Impedance

LOGIC DIAGRAM

4-331

OUTPUTS

L
H
L
H

257
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RAP':'GE (unless otherwise specified)
SYMBOL

54/74S

PARAMETER

Min

Icc

Power Supply
Current

AC CHARACTERISTICS: Vee

Max

Min

68

10

Outputs LOW

93

16

Outputs OFF

99

19

= +5.0 V,

TA

PARAMETER

UNITS

CONDITIONS

Max

Outputs HIGH

mA

Vee = Max; S, hx = 4.5 V;
OE, lox = Gnd
Vee = Max; hx = 4.5 V;
OE lox, S = Gnd
Vee = Max; S, lox = Gnd
OE, hx = 4.5 V

= +25°C (See Section 3 for waveforms and load
54/74S

SYMBOL

54174LS

CL
RL

= 15 pF
= 2800

Min

Max

configurations)

54174LS

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
In to Zn

7.5
6.5

18
18

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
S to Zn

15
15

21
21

ns

Figs. 3-1, 3-20

tPZH
tPZL

Output Enable Time

19.5
21

30
30

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kO ('LS257)

tPHZ
tPLZ

Output Disable Time

8.5
14

30
25

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kO, CL = 5 pF
( 'LS257)

4-332

257A
CONNECTION DIAGRAM
PINOUT A

54LS/74LS257 A
QUAD 2-INPUT MULTIPLEXER

sIT

(With .3-State Outputs)

II
I" IT
Z,

[I

lOb

[I

:mild
]]Zd

Yiii i 'j Y'f 7
OE lOa ha lOb I1b loc he IOd hd

MI.L,.lI;.Aft.jiGRADE

,-s

PKG

Plastic
DIP (P)

A

Ceramic
DIP (0)

A

74LS257ADC

54LS257ADM

68

Flatpak
(F)

A

74LS257AFC

54LS257AFM

4L

OUT

LOGIC SYMBOL

;i,">'

\le2'";+5.0 V ±10%,
Vee = +5.0 V ±5%,
TA = 0° C to +70° C ,jY'i' ',r":'I';'iiii':55° C to +125° C
I";'
<:1;.',::":;;
74LS257APC

PKGS

]]z,
J2] IOd

GNO[!

DESCRIPTION - The '257 A is the same as the '257, except that the output
drive capability is increased as indicated in the tables below. The ac test limits
are the same as the '257 but with the test load changed to 667 nand 45 pF,
except for the Output Disable Time tests, whose load is 667 nand 5
For
all other information please refer to the '257 data sheet.

ORDERING CODE: See Section 9

loc

II
IT

Zb

COMMERCIAL GRADE

~vcc

tm oe
;EJ
mile

lOa

hb

PIN

-

TYPE

Z,

Zb

Z,

Zd

! ! ,t !

98

Vee = Pin 16
Gnd = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Zn

54174LS (U.L.)
HIGH/LOW

DESCRIPTION

65/15
(25)/(7.5)

3-State Outputs

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

II XM ' XC
XC

VOL

Output LOW Voltage

los

Output Short Circuit Current

UNITS
0.4
0.5

-30

4-333

CONDITIONS

Max

-130

V
mA

IOL=12mA
10L - 24 mA
Vee = Max

Iv
-M'
I ee -

In

258
CONNECTION DIAGRAM
PINOUT A

548/748258
54L8/74L8258

-

sIT

QUAD 2-INPUT MULTIPLEXER

IDa

(With 3-State Outputs)

11

l1alI

~Ioc

Za[!

EJl1c

IT

~lc

I1bl1

~IOd

lb[I

~11d

I]:

~ld

lOb

DESCRIPTION - The '258 is a quad 2-input multiplexer with 3-state outputs.
Four bits of data from two sources can be selected using a common data
select input. The four outputs present the selected data in the complement
(inverted) form. The outputs may be switched to a high impedance state with a
HIGH on the common Output Enable(OE) Input, allowing the outputs to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed.

:ill Vee
mOE

GNO

LOGIC SYMBOL

• SCHOTTKY PROCESS FOR HIGH SPEED
• MULTIPLEXER EXPANSION BY TYING OUTPUTS TOGETHER
• INVERTING 3-STATE OUTPUTS

Yiii i lj Y111 11
OE'IOa ha lOb hb IOc 11C IOd hd

1- s

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74S258PC, 74LS258PC

Ceramic
DIP(D)

A

74S258DC, 74LS258DC

54S258DM, 54LS258DM

68

Flatpak
(F)

A

74S258FC, 74LS258FC

54S258FM, 54LS258FM

4L

98

Z,

Zb

Z,

Zd

r r! !
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. defintions
PIN NAMES

-SOE
lOa -lad
l1a -11d
Za-Zd

DESCRIPTION
Common Data Select Input
3-State Output Enable Input (Active LOW)
Data Inputs from Source 0
Data Inputs from Source 1
Inverting Data Outputs

4-334

54174S (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

2.5/2.5
1.25/1.25
1.25/1.25
1.25/1.25
162/12.5
(50l

1.0/0.5
0.5/0.25
0.5/0.25
0.5/0.25
65/15
(25)/(7.5)

258
FUNCTIONAL DESCRIPTION - This device is a quad 2-input multiplexer with 3-state outputs. It selects four
bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the lox
inputs are selected and when Select is HIGH, the hx inputsareselected. The data on the selected inputs appears
at the outputs in inverted form. The '258 is the logic implementation of a 4-pole, 2-position switch where the
position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the
outputs are shown below:
Za
Ze

= OE •
= OE •

(ha • S + loa. 5)
(he. S + 10e • S)

Zb

= OE •

Zd

= OE •

(hb • S + lOb. S)
(hd • S + 10d • S)

When the Output Enable input(OE) is HIGH, the outputs are forced to a high impedance OFF state. Ifthe outputs
of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3state devices whose outputs are tied together are designed so there is no overlap.

TRUTH TABLE
OUTPUT
ENABLE

H=
L=
X=
Z=

SELECT
INPUT

DATA
INPUTS

OUTPUTS

OE

S

10

h

Z

H
L
L
L
L

X

X
X
X

X

L
H

X
X

Z
H
L
H
L

H
H
L
L

L
H

HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance

LOGIC DIAGRAM

4-335

258
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

los

lee

PARAMETER

Output Short Circuit Current

Power Supply
Current

54/74S

54/74LS

Min

Max

Min

Max

-40

-100

-20

-100

Outputs HIGH

56

7.0

Outputs LOW

81

14

Outputs OFF

87

19

UNITS

CONDITIONS

mA

Vee = Max

mA

Vee = Max; S, hx = 4.5 V
OE lox = Gnd
Vee - Max; hx - 4.5 V
OE, lox, S = Gnd
Vee = Max; S, lox = Gnd
OE = 11x = 4.5 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74S
SYMBOL

PARAMETER

54/74LS

CL = 15 pF CL= 15 pF
RL = 280 n
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
In to Zn

6.0
6.0

18
18

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
S toZn

12
12

21
21

ns

Figs. 3-1, 3-4

tPZH
tPZL

Output Enable Time

19.5
21

30
30

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kn ('LS258)

tPHZ
tPLZ

Output Disable Time

8.5
14

30
25

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kn, CL = 5 pF
('LS258)

4-336

258A
CONNECTION DIAGRAM
PINOUT A

54LS/74LS258A
(With 3-State Outputs)

PIN

mOE

haII

:EJ lac

Za[I

~hc

10b[[

rm

hb[[

tTIJ lOd

PKGS

OUT

MILly"Wti'GRADE
.... .... .'.'
,;.~ ~....

'~

."'ce:;~\+5.0 V ±10%,
,:"}:A,'"li,;:::55° C to +125° C

Vee = +5.0 V ±5%,
T A = 0° C to +70° C

":.!.'\;

zc

Zbe!:

~11d

GNO[!

PJZd

LOGIC SYMBOL

! iii i Tln1I,

,', "i.'::;:,":

COMMERCIAL GRADE

1!l Vee

lOa [I

DESCRIPTION - The '258A is the same as the '258, except that the output
drive capability is increased as indicated in the tables below. The ac test limits
are the same as the '258 but with the test load changed to 667 nand 45 pF,
except for the Output Disable Time tests, whose load is 667 nand 5 pF. For
all other information please refer to the '258 data sheet.

ORDERING CODE: See Section 9

-

sIT

QUAD 2-INPUT MULTIPLEXER

OE lOa ha lOb 11b loc be IOd I1d

PKG

1-5

TYPE

Za

Plastic
DIP (P)

A

74LS258APC

Ceramic
DIP (0)

A

74LS258ADC

54LS258ADM

68

Flatpak
(F)

A

74LS258AFC

54LS258AFM

4L

Zb

r r

,<":,;,,
98

Zc

Zd

X

!

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

Zn

54/74LS (U.L.)
HIGH/LOW

DESCRIPTION
Inverting 3-State Outputs

65/15
(25)/(7.5)

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

II XM ' XC
XC

VOL

Output LOW Voltage

los

Output Short Circuit Current

0.4
0.5
-30

4-337

CONDITIONS

UNITS

Max

-130

V
mA

= 12 mA I V
M'
= 24 mA I ee = In
Vee = Max
10L
IOL

259
CONNECTION DIAGRAM
PINOUT A

54LS/74LS259
a-BIT ADDRESSABLE LATCH
DESCRIPTION - The '259 is a high speed 8-bit addressable latch designed
for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable
latches, and also a 1-of-8 decoder and demultiplexer with active HIGH
outputs. The device also incorporates an active LOW common Clear for
resetting all latches, as well as, an active LOW Enable. It is functionally
identical to the 9334 and 93L34 8-bit addressable latch.
•
•
•
•
•
•
•

Ao[!

SERIAL-TO-PARALLEL CONVERSION
EIGHT BITS OF STORAGE WITH OUTPUT OF EACH BIT AVAILABLE
RANDOM (ADDRESSABLE) DATA ENTRY
ACTIVE HIGH DEMUL TIPLEXING OR DECODING CAPABILITY
EASILY EXPANDABLE
COMMON CLEAR
FULLY TTL AND CMOS COMPATIBLE

A1

OUT

rm o
~07
till

IT

02!!
03

PKGS

~E

Ad:!

01

06

till 05
:II 04

II

GNO[I

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74LS259PC

Ceramic
DIP (D)

A

74LS259DC

54LS259DM

68

Flatpak
(F)

A

74LS259FC

54LS259FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

Ao-A2

D

E

cL
00-07

54/74LS (U.L.)
HIGH/LOW

DESCRIPTION

PIN NAMES

Address Inputs
Data Input
Enable Input (Active LOW)
Conditional Clear Input (Active LOW)
Latch Outputs

0.5/0.25
0.5/0.25
1.0/0.5
0.5/0.25
10/5.0
(2.5)

LOGIC SYMBOL
14

13

AD

2

A1

3

A3
CL 00 Q1 02 03 04 05 06 07

15

4

5

6

7

9

4-338

10 11 12

Vcc = Pin 16
GND = Pin 8

~vcc

~Ci.

[I

001}

ORDERING CODE: See Section 9
PIN

-

259
FUNCTIONAL DESCRIPTION - The '259 has four modes of operation as shown in the Mode Selection Table.
In the addressable latch mode, data on the Data line (0) is written into the addressed latch. The addressed latch
will follow the data input with all non-addressed latches remaining in their previous states. in the memory mode,
all latches remain in their previous state and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state.of the D input
with all other outputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and
data inputs. When operating the '259 as an addressable latch, changing more than one bit of the address could
impose a transient wrong address. Therefore, this should only be done while in the memory mode. The Truth
Table below summarizes the operations of the '259.

MODE SELECT TABLE
E

CL

L
H
L
H

H
H
L
L

MODE
Addressable Latch
Memory
Active HIGH 8-Channel Demultiplexer
Clear

TRUTH TABLE
OUTPUTS

INPUTS
CL

E

D

Ao

A1

A2

00

01

02

03

04

05

Os

07

L
L
L
L
H

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L

L

L

L

L

H

MODE
Clear
Demultiplex

L
L
L
L
L

H
L
L
L
L

X
L
H
L
H

X
L
L
H
H

X
L
L
L
L

X
L
L
L
L

L
L
H
L
L

L

L

H

H

H

H

L

L

H

H

X

X

X

X

Ot-1

01-1

01-1

01-1

Ot-1

01-1

01-1

01-1

Memory

H
H
H
H

I
L
L
L

I
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

L
H
Ot-1
Ot-1

Ot-1
01-1
L
H

Ot-1
01-1
01-1
01-1

Ot-1
01-1
01-1
01-1

01-1
01-1
01-1
Ot-1

Ot-1
Ot-1
01-1
01-1

01-1
01-1
01-1
Ot-1

01-1
01-1
01-1
Ot-1

Addressable
Latch

H
H

L
L

L
H

H
H

H
H

H
H

01-1
Ot-1

01-1
Ot-1

Ot-1
01-1

Ot-1
Ot-1

Ot-1
01-1

01-1
01-1

01-1
01-1

L
H

Q'-1 = Previous Output State
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

4-339

259
LOGIC DIAGRAM
E

D

<~

A,

Ao

'7

~7

'7

-

-,

U

-CL

A2

r-

~7

7

'7

'f

~ ~ ~ ~ ~ ~J5~ ~

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74LS

PARAMETER
Min

Icc

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

UNITS
36

TA

CONDITIONS

Max
mA

Vee

= +25°C (See Section 3 for waveforms and

= Max

load configurations)

54174LS
SYMBOL

PARAMETER

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tpHL

Propagation Delay,

E to an

27
24

ns

Figs. 3-1, 3-9

tpLH
tpHL

Propagation Delay, D to an

30
20

ns

Figs. 3-1, 3-5

tpLH
tPHL

Propagation Delay, An to an

30
20

ns

Figs. 3-1,3-20

tpHL

Propagation Delay, CL to an

18

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

TA

= +25°C
54174LS

PARAMETER
Min

ts (H)

Setup Time HIGH, D to E

UNITS

20

ns

th (H)

Hold Time HIGH, D to E

0

ns

ts(U

Setup Time LOW, D to E

15

ns

th(U

Hold Time LOW, D to E

0

ns

ts

Setup Time HIGH or LOW, An to E

tw (U

E Pulse Width LOW

0
17

4-340

CONDITIONS

Max

ns

Fig. 3-13

Fig. 3-21

260

260
CONNECTION DIAGRAM
PINOUT A

54S/74S260
54LS/74LS260
DUAL 5-INPUT NOR GATE

PIN
PKGS

OUT

-

-

11

ORDERING CODE: See Section 9
COMMERCIAL GRADE
VCC = +5.0 V ±5%,
TA = O°C to +70°C

MILITARY GRADE
VCC = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74S2S0PC, 74LS2S0PC

Ceramic
DIP (D)

A

74S2S0DC, 74LS2S0DC

54S2S0DM, 54LS2S0DM

SA

Flatpak
(F)

A

74S2S0FC, 74LS2S0FC

54S2S0FM, 54LS2S0FM

31

9A

IT

II
II
II

~VDD

~
~
~
~
~
~
~

12

---FD-

U

GNOII

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

54174S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

1.25/1.25
25/12.5

0.5/0.25
10/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

54174S

PARAMETER

54/74LS

UNITS

CONDITIONS

Min Max Min Max
ICCH

Power Supply Current

ICCL
tPLH
tPHL
·DC limits apply

Propagation Delay
over operating temperature range;

AC

29

4.0

45

5.5

5.5
S.O

10
12

limits apply at TA

mA

VIN = Open
ns

= +25°C and Vee = +5.0 V.

4-341

VIN = Gnd

Figs. 3-1, 3-4

Vcc=Max

266
CONNECTION DIAGRAM
PINOUT A

54LS/74LS266
QUAD 2-INPUT EXCLUSIVE-NOR GATE

IT

(With Open-Collector Outputs)

[!
[l

11
IT

IT
GNOII

--

~vee

~~ till
~
~

=lli~

~

~
~

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

= +5.0 V ±5%,
= O°C to +70°C

Vee
TA

MILITARY GRADE

= +5.0 V ±10%,
= -55°C to +125°C

Vee
TA

TYPE

Plastic
DIP(P)

A

74LS266PC

Ceramic
DIP (0)

A

74LS266DC

54LS266DM

6A

Flatpak
(F)

A

74LS266FC

54LS266FM

31

9A
INPUTS

Inputs
Outputs

OUTPUT

A

B

Z

L
L
H
H

L
H
L
H

H
L
L
H

H = HIGH Voltage Level
L = LOW Voltage Level

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

TRUTH TABLE

PKG

54/74LS (U.L.)
HIGH/LOW
1.0/0.375
OC··/5.0
(2.5)

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

54/74LS

PARAMETER
Min

UNITS

CONDITIONS

Max

= Max

Power Supply Current

13

mA

Vee

IPLH
IPHL

Propagation Delay

23
23

ns

Other Input LOW
Figs. 3-2, 3-5

IPLH
IPHL

Propagation Delay

23
23

ns

Other Input HIGH
Figs. 3-2, 3-5

Icc

"DC limits apply over operating temperature range; AC limits apply at TA = +25°C and Vee
"OC- Open Collector

4-342

=

+5.0 V.

273
CONNECTION DIAGRAM
PINOUT A

54LS/74LS273
8-BIT REGISTER
(With Clear)
DESCRIPTION - The '273 is a high speed 8-bit register, consisting of eight
O-type flip-flops with a common Clock and an asynchronous active LOW
Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch
row spacing.

•
•
•
•

EDGE-TRIGGERED
8-BIT HIGH SPEED REGISTER
PARALLEl IN AND OUT
COMMON CLOCK AND MASTER RESET

•

LOGIC SYMBOL

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CP
00-07
MR

00-07

54174LS (U.L.)
HIGH/LOW

DESCRIPTION
Clock Pulse Input (Active Rising Edge)
Data Inputs
Asynchronous Master Reset Input (Active LOW)
Flip-flop Outputs

0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

LOGIC DIAGRAM
Do

0,

D,

Q,

Q,

Ds

D3

D.

D,

~~--~~-----'-r----~~----~+-----~r-----~----~~----~

Q3

4-343

Q4

Qs

Q,

273
FUNCTIONAL DESCRIPTION - The '273 is an 8-bit parallel register with a common Clock and common
Master Reset. When the MR input is LOW, the a outputs are LOW, independent of the other inputs. Information
meeting the setup and hold time requirements of the D inputs is transferred to the a outputs on the LOWto-HIGH transition of the clock input.

TRUTH TABLE
INPUTS

OUTPUTS

MR

CP Dn

an

L
H
H

X

L
H
L

J

...r

X
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specifed)
SYMBOL

54174LS

PARAMETER
Min

lee

UNITS

CONDITIONS

Max

Power Supply Current

27

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C (See Section 3 for waveforms and load configurations)
54174LS
SYMBOL

PARAMETER

CL = 15 pF
Min

fmax

Maximum Clock Frequency

tpLH
tPHL

Propagation Delay
CP to an

tPHL

Propagation Delay
MR to an

UNITS

CONDITIONS

Max

30

MHz

Figs. 3-1, 3-8

24
24

ns

Figs. 3-1, 3-8

27

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54174LS

PARAMETER
Min

ts (H)

UNITS

CONDITIONS

Max

ts (U

Setup Time HIGH or LOW
Dn to CP

15
15

ns

th (H)
th (W

Hold Time HIGH or LOW
Dn to CP

5.0
5.0

ns

tw (H)
tw (U

CP Pulse Width HIGH or LOW

20
20

ns

Fig. 3-8

tw (U

MR Pulse Width LOW

20

ns

Fig. 3-16

tree

Recovery Time
MR to CP

15

ns

Fig. 3-16

4-344

Fig. 3-6

279
CONNECTION DIAGRAM
PINOUT A

54/74279
54LS/74LS279

AD:

QUAD SET-RESET LATCH

S,1l
S2 [!

a[!
~

[!

IT
GND\!

~~
~~

~vcc

till
tEl
tm
tm
tm
S
~

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

TRUTH TABLE
INPUTS

Plastic
DIP (P)

A

Ceramic
DIP (D)

A

74279DC, 74LS279DC

54279DM, 54LS279DM

68

Flatpak
(F)

A

74279FC, 74LS279FC

54279FM, 54LS279FM

4L

98

74279PC, 74LS279PC

54174LS (U.L.)
HIGH/LOW

54174 (U.L.)
HIGH/LOW

0.5/0.25
10/5,0
(2.5)

1.0/1.0
20/10

Inputs
Outputs

S2

R

Q

L
L
X
H
H

L
X
L
H
H

L
H
H
L
H

h
H
H
L
No Change

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
h = The output is HIGH as long as s,
or S2 is LOW. If all inputs go HIGH
simultaneously, the output state is indeterminate; otherwise, it follows the
Truth Table.

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

OUTPUT

S1

DC AND AC CHARACTERISTICS: See Section 3'
PARAMETER

SYMBOL

54/74

54/74LS

UNITS

CONDITIONS

Min Max Min Max

R=

lee

Power Supply Current

30

7.0

mA

Vee = Max,

tPLH
tPHL

Propagation Delay
S"to Q

22
15

22
15

ns

Figs. 3-1,3-10

tpHL

R to Q

27

27

ns

Figs. 3-1, 3-10

Propagation Delay

'De limits apply over operating temperature range; Ae limits apply at TA = +25°e and Vee = +5.0 V.

4-345

Gnd

•

280
CONNECTION DIAGRAM
PINOUT A

54S/74S280
9-BIT PARITY GENERATOR/CHECKER

DESCRIPTION - The '280 is a high speed parity generator/checker that
accepts nine bits of input data and detects whether an even or an odd number
or these inputs are HIGH. If an even number of inputs are HIGH, the Sum
Even output is HIGH. If an odd number are HIGH, the Sum Even output is
LOW. The Sum Odd output is the complement of the Sum Even outRMl

LOGIC SYMBOL

8

9 10 11 12 13

1

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
Vee = +5.0 V ±5%,
TA = O°C to +70°C

Plastic
DIP (P)

A

74S280PC

Ceramic
DIP (0)

A

74S280DC

54S280DM

6A

Flatpak
(F)

A

74S280FC

54S280FM

31

9A

6

5

Vee = Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

10-18
~o
~E

54/74S (U.L.)
HIGH/LOW

DESCRIPTION

PIN NAMES
Data Inputs
Odd Parity Output
Even Parity Output

1.25.1.25
25/12.5
25/12.5

TRUTH TABLE
NUMBER OF INPUTS
10-18 THAT ARE HIGH

OUTPUTS
~

EVEN
H
L

0,2,4,6,8,
1,3,5,7,9
H = HIGH Voltage Level
L = LOW Voltage Level

4-346

~

ODD
L
H

2

4

280
LOGIC DIAGRAM
I,

I,

~,.

~7

~,.

Y . ,.

~

I,

I,

V

T

~

I,

I,

b

";7

V

";7

n

";7

~7

~7

~7

VI V

I.. ,.

~,.

~7

";,.

~ r
fir

T

~

r

Ll)

T

10

"

";,.

Y

T

~
fir

}

~o

"

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74S

PARAMETER
Min

lee

Power Supply Current

UNITS

CONDITIONS

Max

XM
XC

99
105

mA

XM

94

mA

Vee = Max,
All Inputs =
Vee - Max,
All Inputs =

TA = 25°C
Gnd
TA - 125°C
Gnd

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C (See Section 3 for waveforms and load configurations)
54/47S
SYMBOL

PARAMETER

CL = 15 pF
RL = 280 n
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
In to 2E

21
18

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
In to 20

21
18

ns

Figs. 3-1, 3-20

4-347

283
CONNECTION DIAGRAM
PINOUT A

54/74283
54LS/74LS283
4-BIT BINARY FULL ADDER
(With Fast Carry)
S1[1:

DESCRIPTION - The '283 high speed 4-bit binary full adders with internal
carry lookahead accept two 4-bit binary words (Ao - A3, 80 - 83) and a Carry
input (Co)' They generate the binary Sum outputs (So - S3) and the Carry
output (C4) from the most significant bit. They operate with either active HIGH
or active LOW operands (positive or negative logic).

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

-

:ill Vee

B1[I

:ill B2

A1[I

TIJ A2

IT

J1] 52

Ao[I

:ill A3

So

BalI

J2] B3

Co [I

J]] 53

GNO[I

}]C4

PKG
TYPE

Plastic
DIP (P)

A

74283PC, 74LS283PC

Ceramic
DIP (D)

A

74283DC, 74LS283DC

54283DM, 54LS283DM

68

Flatpak
(F)

A

74283FC, 74LS283FC

54283FM, 54LS283FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

54174 (U.L.)

DESCRIPTION

Ao-A3
80-83
Co
80-S3

A Operand Inputs
8 Operand Inputs
Carry Input
Sum Outputs

C4

Carry Output

HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0

20/10
10/5.0

LOGIC SYMBOL

iii i 1j 1j 1j 1f
Ao Bo A1 B1 A2 B2 A3 B3
C4 - 9

7 - Co

So

5,

! !

52

53

)3 )0

4-348

Vcc = Pin 16
GND = Pin 8

54174LS (U.L.)
HIGH/LOW
1.0/0.5

1.010.5
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

283
FUNCTIONAL DESCRIPTION - The '283 adds two 4-bit binary words (A plus 8) plus the incoming carry Co.
The binary sum appears on the 8um (80 - 83) and outgoing carry (C4) outputs. The binary weight of the various
inputs and outputs is indicated by the subscript numbers, representing powers of two.
2° (Ao

+ 80 + Co) + 21

(A1

+ 81) + 22 (A2 + 82) + 23 (A3 + 83) = 80 + 281 + 482 + 883 + 16C4
Where

(+) =

plus

Interchanging inputs of equal weight does not affect the operation. Thus Co, Ao, 80 can be arbitrarily assigned to
pins 5, 6 and 7. Due to the symmetry of the binary add function, the '283 can be used either with all inputs and
outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). Note that if Co is
not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic.
Example:
Co

Ao

A1

A2

A3

80

81

82

83

So

81

82

83

C4

Logic Levels

L

L

H

L

H

H

L

L

H

H

H

L

L

H

Active HIGH
Active LOW

0
1

0
1

1
0

0
1

1
0

1
0

0
1

0
1

1
0

1
0

1
0

0
1

0
1

1
0

Active HIGH: 0

+ 10 + 9 = 3 + 16

Active LOW: 1 + 5

+6 =

12

+0

Due to pin limitations, the intermediate carries of the '283 are not brought out for use as inputs or outputs.
However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate
stage. Figure a shows a way of making a 3-bit adder. Tying the operand inputs of the fourth adder (A3, 83) LOW
makes 83 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle,
Figure b shows a way of dividing the '283 into a 2-bit and a 1-bit adder. The third stage adder (A2, 82,82) is used
merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and 82) and bringing out the carry
from the second stage on 82. Note that as long as A2 and 82 are the same, whether HIGH or LOW, they do not
influence 82. 8imilarly, when A2 and 82 are the same the carry into the third stage does not influence the carry
out of the third stage. Figure c shows a method of implementing a 5-input encoder, where the inputs are equally
weighted. The outputs 80, 81 and 82 present a binary number equal to the number of inputs 11 -15 that are true.
Figure d shows one method of implementing a5-input majority gate. When three or more of the inputs 11 -15 are
true, the output Ms is true.

ClO

L

Co

Co

Fig. a

3-Blt Adder

Co

Fig. b 2-Blt and 1-Bit Adders

4-349

283
13

Co

Co

M5

Fig. c

5-lnput Encoder

Fig. d 5-lnput Majority Gate

LOGIC DIAGRAM

4-350

283
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER

54174LS

Min

Max

Min

Max

UNITS

CONDITIONS

los

Output Short Circuit
Current at Sn

XM
XC

-20
-18

-55
-55

-20
-20

-100
-100

rnA

Vee

= Max

los

Output Short Circuit
Current at C4

XM
XC

-20
-18

-70
-70

-20
-20

-100
-100

rnA

Vee

= Max

Power Supply Current

XM
XC

Icc

99
110

XM, XC

AC CHARACTERISTICS: Vee

= 5.0 V,

TA

= 25°C (See Section
54/74

SYMBOL

PARAMETER

Max

rnA

34

rnA

Vee = Max,
Inputs = Gnd (,LS283)
Inputs = 4.5 V ('283)
Vee - Max
Inputs = 4.5 V (,LS283)

3 for waveforms and load configurations)

54/74LS

CL = 15 pF CL
RL = 400 0
Min

39
39

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Co to Sn

21
21

24
24

ns

Figs. 3-1, 3-20

tPLH
tpHL

Propagation Delay
An or Bn to Sn

24
24

24
24

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
Co to C4

14
16

17
17

ns

Figs. 3-1, 3-5
RL = 780 0 ('283)

tPLH
tPHL

Propagation Delay
An or Bn to C4

14
16

17
17

ns

Figs. 3-1, 3-5
RL = 7800 ('283)

4-351

•

289
CONNECTION DIAGRAM
PINOUTA

54S/74S289

54LS/74LS289
64-BIT RANDOM ACCESS MEMORY
(With Open-Collector Outputs)

DESCRIPTION - The '289 is a high speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading, and
addresses are fully decoded on-chip. Outputs are open-collector type and
are in the off (HIGH) state whenever the Chip Select (CS) input is HIGH.The
outputs are active only in the Read mode; output data is the complem
of
the stored data.
LOGIC SYMBOL
•
•
•
•

OPEN-COLLECTOR OUTPUTS FOR WIRED-AND A
BUFFERED INPUTS MINIMIZE LOADING
ADDRESS DECODING ON-CHIP
DIODE CLAMPED INPUTS MINIMIZE RIN

2

ORDERING CODE: See Section 9
PIN
PKGS

OUT

15

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

14

TYPE

13

Plastic
DIP (P)

A

74S289PC, 74LS289PC

Ceramic
DIP(D)

A

74S289DC, 74LS289DC

54S289DM, 54LS289DM

68

Flatpak
(F)

A

74S289FC, 74LS289FC

54S289FM, 54LS289FM

4L

98

4

6 10 12 3

5

7

Ao
A,
A2
A3

9

11

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-A3
CS
WE
D1-D4

61-04

DESCRIPTION
Address Inputs
Chip Select Input (Active LOW)
Write Enable Input (Active LOW)
Data Inputs
Inverted Data Outputs

54/74S (U.L.)
HIGH/LOW

54/74LS (U.L.)
HIGH/LOW

0.63/0.16
0.63/0.16
0.63/0.16
0.63/0.16
OC'/10

0.5/0.013
0.5/0.013
0.5/0.013
0.5/0.013
OC'/10
(5.0)

·oc -

Open Collector

4-352

289
FUNCTION TABLE
INPUTS
CS

WE

L
L
H

L
H
X

OPERATION

CONDITION OF OUTPUTS

Write
Read
Inhibit

Off (HIGH)
Complement of Stored Data
Off (HIGH)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

•

LOGIC DIAGRAM

r'~-

__

-WE

"-...Jc_.....+-CS

Ao

DECODER
DRIVERS

16-WORD x 4-BIT
MEMORY CELL
ARRAY

ADDRESS
DECODER

A3

4-353

289
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
54174S

PARAMETER

SYMBOL

Min
XM
XC

Max

54174LS
Min

UNITS

CONDITIONS
Vee = Min
IOL = 16 mA ('S289)
IOL = 8.0 mA (54LS289)
IOL = 16 mA (74LS289)

Max

0.5
0.45

0.4
0.5

V

VOL

Output LOW Voltage

IOH

Output HIGH Current

40
100

20
100

p.A

VOH = 2.4 V
VOH = 5.5 V

lee

Power Supply Current

105

40

mA

Vee = Max

IV I ee -

M'
In

AC CHARACTERISTICS OVER RECOMMENDED Vee AND TA RANGE (unless otherwise specified)
54/74S

PARAMETER

SYMBOL

54174LS

CL = 30 pF CL = 15 pF
RL = *
RL = 2 kn
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Access Time, HIGH or
LOW, An to On

XM
XC

50
35

37**
37**

ns

tPHL

Access Time
CS to On

XM
XC

25
17

10**
10**

ns

tPLH

Disable Time
CS to On

XM
XC

20
17

tPHL

Recovery Ti me
WE to On

XM
XC

40
35

tPLH

Disable Time
WE to 'On

XM
XC

30
25

Figs. 3-2, 3-20

Figs. 3-2, 3-5
ns

30**
30**

ns
Figs. 3-2, 3-4
ns

AC OPERATING REQUIREMENTS OVER RECOMMENDED Vee AND TA RANGE (unless otherwise specified)
PARAMETER

SYMBOL

54/74S

Min

Max

54174LS
Min

UNITS

CONDITIONS

Max

ts (H)
ts (U

Setup Time, HIGH or LOW
An to WE

0
0

10**
10**

ns

th (H)
th (U

Hold Time, HIGH or LOW
An to WE

0
0

0**
0**

ns

ts (H)
ts (U

Setup Time, HIGH or LOW
Dn to WE

20
20

25**
25**

ns

th (H)
th (U

Hold Time HIGH or LOW
Dn to WE

0
0

0*
0*

ns

ts (U

Setup Time LOW
CS to WE

0

ns

Fig. 3-14

th (U

Hold Time LOW
CS to WE

0

ns

Fig. 3-13

tw (U

WE Pulse Width LOW

ns

Fig. 3-14

°RL = 300 0 to Vee
""Typical Value

and SOD

0 to

20

25**

Gnd.

4-354

Fig. 3-21

Fig. 3-13

290
CONNECTION DIAGRAM
PINOUT A

54/74290
54LS/74LS290
BCD DECADE COUNTER

DESCRIPTION - The '290 is a 4-stage ripple counter containing a high
speed flip-flop acting as a divide-by-two and three flip-flops connected as
a divide-by-five. HIGH signals on the Master Reset (MAl inputs override the
clocks and force all outputs to the LOW state. HIGH signals on the Master
Set (MS) inputs override the clocks and MR and force the outputs to the BCD
nine state. The '290 is the same circuit as the '90 except that it has corner
power pins and is therefore recommended for new designs. For detail specifications, truth tables and functional description, please refer to the '90 data
sheet.

PKGS
Plastic
DIP(P)

OUT
A

1] Vee

Ncii

TIl MR

MS[I

TI]MR

Qd:!

I!lCP1

Q11I

TIl CPo

NC[I

}JQo

GNOII

}]Q3

•

LOGIC SYMBOL

~
MS

ORDERING CODE: See Section 9
PIN

-

MSIT

10--0 cPo

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

74290PC, 74LS290PC

PKG
TYPE
9A

11--0 CP1
MR

~

12 13

Ceramic
DIP (D)

A

74290DC, 74LS290DC

54290DM, 54LS290DM

6A

Flatpak
(F)

A

74290FC, 74LS290FC

54290FM, 54LS290FM

31

Qo Q1 Q2 Q3

9

5

4

8

Vee = Pin 14
GND = Pin 7
NC = Pin 2,6

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

54/74 (U.L.)
HIGH/LOW

DESCRIPTION

00

+2 Section Clock Input
(Active Falling Edge)
+5 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset
Inputs (Active HIGH)
Asynchronous Master Set (Set to 9)
Inputs (Active HIGH)
+2 Flip-flop Output"

Q1-03

+5 Flip-flop Outputs

CPo
CP1
MR1, MA2
MS1, MS2

·The

Qo

2.0/2.0

1.0/1.5

3.0/3.0

2.0/2.0

1.0/1.0

0.5/0.25

1.0/1.0

0.5/0.25

20/10

10/5.0
(2.5)
10/5.0
(2.5)

20/10

output is guaranteed to drive the full rated fan-out plus the CP, input.

4-355

54174LS (U.L.)
HIGH/LOW

293
CONNECTION DIAGRAM
PINOUT A

54/74293
54LS/74LS293

3

~

NCO::

MODULO-16 BINARY COUNTER

DESCRIPTION - The '293 is a 4-stage ripple counter containing a high
speed flip-flop acting as a divide-by-two and three flip-flops acting as a
divide-by-eight. HIGH signals on the Master Reset (MAl inputs override the
clocks and force all outputs to the LOW state. The '293 is the same circuit
as the '93 except that it has corner power pins and is therefore recommended
for new designs. For detail specifications, truth tables and functional description, please refer to the '93 data sheet.

NclI

TIl MR2

NC[I

:g) MR1

odI
0, IT

TIlCP1

NCIT

}]Oo

GNo[2

]]03

~CPo

LOGIC SYMBOL

10 ---0 cPo
11 ---0 CP,
MR

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to -I-70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

74293PC, 74LS293PC

Ceramic
DIP (0)

A

74293DC, 74LS293DC

54293DM, 54LS293DM

6A

Flatpak
(F)

A

74293FC, 74LS293FC

54293FM, 54LS293FM

31

9A

~

00 0, 02 03

9

5

4

8

Vcc = Pin 14
GND = Pin 7
NC = Pins 1, 2, 3. 6

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

54174 (U.L.)
HIGH/LOW

DESCRIPTION

00

+2 Section Clock Input
(Active Falling Edge)
+8 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Inputs
(Active HIGH)
+2 Flip-flop Output'

01-03

+8 Flip-flop Outputs

CPo
CP1
MR1, MR2

'The

00 output

is guaranteed to drive the full rated fan-out plus the

CP1

input.

4-356

54174LS (U.L.)
HIGH/LOW

2.0/2.0

1.0/1.5

2.0/2.0

1.0/1.0

1.0/1.0

0.5/0.25

20/10

10/5.0
(2.5)
10/5.0
(2.5)

20/10

Vee

295A
CONNECTION DIAGRAM
PINOUT A

54LS/74LS295A
4-BIT SHIFT REGISTER
Os

(With 3-State Outputs)

0::

:ill Vee

~

PorI
P,[I

1iI0o
1iI0,
TIl 02

P21I
DESCRIPTION - The '295A is a 4-bit shift register with serial and parallel
synchronous operating modes, and independent 3-state output buffers. The
Parallel Enable input (PEl controls the shift-right or parallel load operation.
All data transfers and shifting occur synchronous with the HIGH-to-LOW
clock transition.

p,[I

:mo,

PEII

I1Cl'

GNOIT

IlOE

The 3-state output buffers are controlled by an active HIGH Output Enable
input (OEl. Disabling the output buffers does not affect the shifti ng or loadi ng
of input data, but it does inhibit serial expansion. The device is fabricated with
the Schottky barrier diode process for high speed.
LOGIC SYMBOL
•
•
•
•

FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS
NEGATIVE EDGE-TRIGGERED CLOCK INPUT
PARALLEL ENABLE MODE CONTROL INPUT
3-STATE BUSSABLE OUTPUT BUFFERS

1-

PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

A

74LS295APC

Ceramic
DIP (0)

A

74LS295ADC

54LS295ADM

6A

A

74LS295AFC

54LS295AFM

31

(F)

8 - OE

00

TYPE

Plastic
DIP(P)

Flatpak

p, P2 P3

Ds
9-------------------------~~----------~~---------+~--------~
03

00

4-3.58

295A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
los

Icc

54/74LS

PARAMETER
Output Short Circuit Curent

Power Supply
Current

UNITS

Min

Max

-20

-100

Outputs ON
Outputs OFF

23
25

CONDITIONS

mA

Vee = Max

mA

Vee = Max. Pn = Gnd
PE. Ds. OE = 4.5 V
CP=L
Vee = Max. PE. Ds - 4.5 V
Pn• OE. CP = Gnd

AC CHARACTERISTICS: Vee = +5.0 V. TA = +25° C (See Section 3 for waveforms and load configurations)
54/74LS

SYMBOL

PARAMETER

CL = 15 pF
Min

f max

Maximum Shift Frequency

tPLH
tPHL

Propagation Delay
CP to On

tPZH
tPZL
tPHZ
tPLz

UNITS

CONDITIONS

Max

30

MHz

Figs. 3-1. 3-9

30
26

ns

Figs. 3-1. 3-9

Output Enable Time

18
20

ns

Figs. 3-3. 3-11.3-12
RL = 2 kO.

Output Disable Time

24
20

ns

Figs. 3-3. 3-11.3-12
RL = 2 kO. CL = 5 pF

AC OPERATING REQUIREMENTS: Vee = +5.0 V. TA = +25°C
SYMBOL

54/74LS

PARAMETER
Min

UNITS

ts (H)
ts (U

Setup Time HIGH or LOW
Ds. Pn to CP

20
20

ns

th (H)
th (U

Hold Time HIGH or LOW
Ds. Pn to CP

10
10

ns

ts (H)
ts(U

Setup Time HIGH or LOW
PE to CP

20
20

ns

th (H)
th (U

Hold Time HIGH or LOW
PE to CP

0
0

ns

tw (U

CP Pulse Width LOW

20

ns

4-359

CONDITIONS

Max

Fig. 3-7

Fig. 3-7

Fig. 3-9

298
CONNECTION DIAGRAM
PINOUT A

54/74298
54LS/74LS298

-

hbIT

QUAD 2-PORT REGISTER

EJvcc

1iI a.

haii

(Multiplexer with Storage)

IDa [1

Elab

8:

lilac

hcIT

TIl ad

hd[!

TIlC"P

lOb

10d

IT

~s

GNO[!

DESCRIPTION - The '298 is a quad 2-port register. it is the logical equivalent
of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data
sources!. The selected data is transferred to the output register synchronous
with the HIGH-to-LOW transition of the Clock input.

LOGIC SYMBOL

• SELECT FROM TWO DATA SOURCES
• FULLY EDGE·TRIGGERED OPERATION
• TYPICAL POWER DISSIPATION OF 65 mW ('LS298)

iiiliifi

10. h. lOb hb loc hc 10d hd

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

s

11--0

cp

TYPE

A

74298PC, 74LS298PC

Ceramic
DIP (0)

A

74298DC, 74LS298DC

54298DM, 54LS298DM

68

A

74298FC, 74LS298FC

54298FM, 54LS298FM

4L

(F)

10-

PKG

Plastic
DIP(P)

Flatpak

}:lloc

ac

ad

a.

ab

)5

L )3 1~

98
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN·OUT: See Section 3 for U.L. definitions
PIN NAMES
S

CP
loa-Iod
ha-hd
Oa-Qd

DESCRIPTION

54174 (U.L.)
HIGH/LOW

54174LS (U.L.)
HIGH/LOW

Common Select Input
Clock Pulse Input (Active Falling Edge)
Source 0 Data Inputs
Source 1 Data Inputs
Flip-flop Outputs

1.0/1.0
1.0/1.0
1.0/1.0
1.011.0
20/10

0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

4-360

298
FUNCTIONAL DESCRIPTION - This device is a high speed quad 2-port register. It selects four bits of data
from two sources (ports) under the control of a Common Select input (Sl. The selected data is transferred tothe
4-bit output register synchronous with the HIGH-to-LOW transition of the Clock input (CPl. The 4-bit output
register is fully edge-triggered. The Data inputs (lnx) and Select input (S) need be stable only one setup time
prior to the HIGH-to-LOW transition of the clock for predicatable operation.

TRUTH TABLE
INPUTS

OUTPUT

S

lox

I1x

Ox

I
I
h
h

I
h
X
X

X
X
I
h

L
H
L
H

I = LOW Voltage Level one setup tIme prtor to the HIGH-to-LOW
clock transition.
h = HIGH Voltage Level one setup time priortothe HIGH-to-LOW
clock transition.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

4-361

298
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74

PARAMETER

Min

Icc

= +5.0 V,

PARAMETER

= 15 pF
= 400 n

CL
RL

Min
tPLH
tpHL

SYMBOL

Max

Propagation Delay
CP to an

AC OPERATING REQUIREMENTS: Vee

mA

IOn, I1n, S = Gnd
CP = """L, Vee = Max

= +5.0 V,

TA

= 15 pF

CL

Min

UNITS

CONDITIONS

Max
25
25

ns

Figs. 3-1, 3-9

= +25°C

54174

Min

load configurations)

54174LS

27
32

PARAMETER

CONDITIONS

= +25°C (See Section 3 for waveforms and
54/74

SYMBOL

21

65

TA

UNITS

Max

Power Supply Current

AC CHARACTERISTICS: Vee

54/74LS

Max

54/74LS
Min

UNITS

ts (H)
ts(U

Setup Time HIGH or LOW
S to CP

25
25

25
25

ns

th (H)
th (U

Hold Time HIGH or LOW
S to CP

0
0

0
0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
lox or 11x to CP

15
15

15
15

ns

lh (H)
th (U

Hold Time HIGH or LOW
lox or I1x to CP

5.0
5.0

5.0
5.0

ns

tw (H)
tw (U

CP Pulse Width HIGH or LOW

20
20

20
20

ns

4-362

CONDITIONS

Max

Fig. 3-7

Fig. 3-9

299
CONNECTION DIAGRAM
PINOUT A

54LS/74LS299
8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER
(With Common Parallel I/O Pins)
DESCRIPTION - The '299 is an 8-bit universal shift/storage register with 3state outputs. Four modes of operation are possible: hold (store), shift left,
shift right and load data. The parallel load inputs and flip-flop outputs are
multiplexed to reduce the total number of package pins. Separate outputs are
provided for flip-flops 00 and 07 to allow easy cascading. A separate active
LOW Master Reset is used to reset the register.

•

• COMMON I/O FOR REDUCED PIN COUNT
• FOUR OPERATION MODES: SHIFT LEFT,
SHIFT RIGHT, LOAD AND STORE
• SEPARATE SHIFT RIGHT SERIAL INPUT AND SHIFT LEFT SERI~L
INPUT FOR EASY C A S C A D I N G ' \ " ' } ,
• 3-STATE OUTPUTS FOR BUS ORIENTED APPLICATION

ORDERING CODE: See Section 9

PKGS

PIN

PKG

OUT

TYPE

Plastic
DIP(P)

A

74LS299PC

Ceramic
DIP (0)

A

74LS299DC

54LS299DM

4E

Flatpak
(F)

A

74LS299FC

54LS299FM

4F

9Z

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
CP
Dso
DS7

So, S1
MR
OE1, OE2

1/00-1/07

00,07

Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-State Output Enable Inputs (Active LOW>
Parallel Data Inputs or
3-State Parallel Outputs
Serial Outputs

4-363

54/74LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
1.0/0.50
0.5/0.25
0.5/0.25
0.5/0.25
65/15
(25)/(7.5)
10/5.0
(2.5)

299
LOGIC SYMBOL
18

11

19

17

12
2
3

Vcc = Pin 20
GND = Pin 10
7

9

U

6

~

5

~

4

a

FUNCTIONAL DESCRIPTION - The '299 contains eight edge-triggered O-type flip-flops and the interstage
logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of
operation is determined by the So and S1, as shown in the Mode Select Table. All flip-flop outputs are brought
out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. 00 and
07 are also brought out on other pins for expansion in serial shifting of longer words.

A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are
initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that
the recommended setup and hold times, relative to the rising edge of CP, are observed.
A HIGH signal on either OEl or 0El! disables the 3-state buffers and puts the I/O pins in the high impedance
state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also
disabled by HIGH signals on both So and Sl in preparation for a parallel load operation.
MODE SELECT TABLE

INPUTS
MR

Sl

So

L
H
H
H
H

X
H
L
H
L

X
H
H
L
L

RESPONSE
CP
X

..r

...r
...r
X

Asynchronous Reset; 00-07 = LOW
Parallel Load; I/On-+On
Shift Right; 050-+00, 00-+01, et<; .
Shift Left; 057-.a7, 07-.a6, etc .
Hold
LOGIC DIAGRAM

4-364

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

299
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

lee

UNITS

CONDITIONS

mA

Vee = Max, OE = 4.5 V

Max

Power Supply Current

65

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174LS
SYMBOL

PARAMETER

CL = 15 pF
MIN

UNITS

CONDITIONS

Max

f max

Maximum Input Frequency

tPLH
tPHL

Propagation Delay
CP to 00 or Q7

23
25

ns

tPLH
tPHL

Propagation Delay
CP to liOn

25
29

ns

tpHL

Propagation Delay
MR to Qo or Q7

30

ns

tpHL

Propagation Delay
MR to liOn

33

ns

tPZH
tpZL

Output Enable Time

18
23

ns

Figs. 3-3. 3-11. 3-12
RL=2kO

tPHZ
tPLZ

Output Disable Time

15
15

ns

Figs. 3-3. 3-11. 3-12
RL = 2 kO. CL = 5 pF

35

MHz

Figs. 3-1, 3-8

Figs. 3-1. 3-8

Figs. 3-1. 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V. TA = +25°C
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

Is (H)
ts (U

Setup Time HIGH or LOW
So or S1 to CP

24
24

ns

th (Hl
th (U

Hold Time HIGH or LOW

So or S1 to CP

0
0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
liOn. Dso. DS7 to CP

10
10

ns

th (H)
th (U

Hold Time HIGH or LOW
liOn. Dso. DS7 to CP

0
0

ns

tw (H)
tw (U

CP Pulse Width HIGH or LOW

15
15

ns

Fig. 3-8

tw (U

MR Pulse Width LOW

15

ns

Fig. 3-16

tree

Recovery Ti me
MR to CP

10

ns

Fig. 3-16

4-365

Fig. 3-6

322
CONNECTION DIAGRAM
PINOUT A

54LS/74LS322
8-BIT SERIAL/PARALLEL REGISTER
(With Sign Extend)
DESCRIPTION - The '322 is an 8-bit shift register with provision for either
serial or parallel loading and with 3-state parallel outputs plusa bi-state serial
output. Parallel data inputs and parallel outputs are multiplexed to minimize
pin count. State changes are initiated by the rising edge of the clock. Four
synchronous modes of operation are possible: hold (store), shift right with
serial entry, shift right with sign extend and parallel load. An asynchronous
Master Reset (MR) input overrides clocked operation and clears the register.
The '322 is specifically designed for operation with the '384 Multiplier and provides the sign extend function required for the '384.

ReO::

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GR~.D€:

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee • ~l§'i;.
TA = -55 0
25°C

Plastic
OIP(P)

A

74LS322PC

Ceramic
OIP(Q)

A

74LS3220C

Flatpak
(F)

A

74LS322FC

r;',""

it

",

PKG

t12Js

~SE

IT

:mOl

1/0,

I/os!!

~1/06

1/03!!

:m1/04

IT

~1/02

0El!

TIl 1/00

MR[!

Elao

GNO§

TI]cp

TYPE

··ii . }::"');"

9Z

S3220M

4E

54LS322FM

4F

i,

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
RE

sip
SE
S
00,01
CP
MR
OE

00
1/00-1/07

DESCRIPTION
Register Enable Input (Active LOW)
Serial (HIGH) or Parallel (LOW) Mode Control Input
Sign Extend Input (Active LOW)
Serial Data Select Input
Serial Data Inputs
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
3-State Output Enable Input (Active LOW)
Bi-State Serial Output
Multiplexed Parallel Inputs or
3-State Parallel Outputs

4-366

~vcc

Do 11:

1/0,

ORDERING CODE: See Section 9

-

SIP I}

54174LS (U.L.)
HIGH/LOW
0.5/0.23
0.5/0.23
1.5/0.68
1.0/0.45
0.5/0.23
0.5/0.23
0.5/0.23
0.5/0.23
11/5.0
(2.5)
0.5/0.23
65/5.0
(25)/(2.5)

322
FUNCTIONAL DESCRIPTION - The '322 contains eight O-type edge triggered flip-flops and the interstage
gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel
load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold
mode. A HIGH signal on SIP enables shift right, while a LOW signal disables the 3-state output buffers and
enables parallel loading. In the shift right mode a HIGH signal on SEenables serial entry from either Do or 01, as
determined by the S input. A LOW signal on SE enables shift right but 07 reloads its contents, thus performing
the sign extend function required forthe '384 Twos Complement Multiplier. A HIGH signal on OE disablesthe3state output buffers, regardless of the other control inputs. In this condition the shifting and loading operations
can still be performed.

LOGIC SYMBOL
19 3 17

S Do 0,

RE
2

sip

18

SE

11

cp

.....~..;.,~..,;.;....;,;..;....T'""""T'.;....~+~;.;...T-......
9

4

16

5

15

6

14

7

13

vcc = Pin 20
GND = Pin 10

12

LOGIC DIAGRAM
RE·~~~----------~------1-------~------~------~--------~------~------'
SIP

S'---r-1I+1"-

Do-----r-

MR~~----_+~-----+~----~+-~--+-~+---~_r~--~_+_r---+~_+--~--~--~

OE---------+~=t~-r_i----r-t-r---~~t---II_ri_--~_t_r--~~_t--~--ri--__,

1/07

1/0,

1/0,

1/0.

4-367

1/03

1/0,

1/00

322
MODE TABLE
INPUTS

MODE

OUTPUTS

MR

RE

sip

SE

S

OE"

CP

1/07

II0s

1/05

1/04

I/0a

1/02

1/01

1/00

Co

Clear

L
L

X
X

X
X

X
X

X
X

L
H

X
X

L
Z

L
Z

L
Z

L
Z

L
Z

L
Z

L
Z

L
Z

L
L

Parallel
Load

H

L

L

X

X

X

S

17

Is

15

14

la

,12

h

10

10

Shift
Right

H
H

L
L

H
H

H
H

L
H

L
L

S
S

Do
Dl

07
07

Os
Os

05
05

04
04

Oa
Oa

02
02

01
01

01
01

Sign
Extend

H

L

H

L

X

L

r

07

07

Os

05

04

Oa

02

01

01

Hold

H

H

X

X

X

L

S

NC

NC

NC

NC

NC

NC

NC

NC

NC

'When the OE input is HIGH. all lIOn terminals are at the high-impedance state; sequential operation or clearing of the register is not affected.
1. 17 -10 = The level of the steady-state input at the respective 1/0 terminal is loaded into the flip-flop while the flip-flop outputs (except 00) are
isolated from the 110 terminal.
2. Do. 0, = The level of the steady-state inputs to the serial multiplexer input.
3. 07-00 = The level of the respective On flip-flop prior to the last Clock LOW-to-HIGH transition.
H = HIGH Voltage Level
L = LOW Voltage Level
NC = No Change Z = High-Impedance Output State
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54/74LS

PARAMETER

SYMBOL

Min

Icc

UNITS

CONDITIONS

Max

Power Supply Current

60

mA

Vce = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174LS
PARAMETER

SYMBOL

CL = 15 pF
Min

fmax

Maximum Clock Frequency

UNITS

CONDITIONS

Max

35

MHz

Figs. 3-1,

3~,8

tPLH
tPHL

Propagation Delay
CP to liOn

23
25

tPLH
tPHL

Propagation Delay
CP to Co

29

tPHL

Propagation Delay
MR to liOn

33

ns

tPHL

Propagation Delay
MR to Co

30

ns

tPZH
tPZL

Output Enable Time
OE to liOn

18
23

ns

Figs. 3-3, 3-11, 3-12
RL=2kO

tpHZ
tPLZ

DE to

Output Disable Time
liOn

15
15

ns

Figs, 3-3, 3-11, 3-12
RL = 2 kO, CL = 5 pF

tpZH
tPZL

0l!!put Enable Time
SIP to liOn

25
30

ns

Figs. 3-3, 3-11, 3-12
RL=2kO

tPHZ
tPLZ

Output Disable Time
SIP to liOn

23
23

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kO, CL = 5 pF

25

4-368

ns
ns
Figs. 3-1, 3-16

322
AC OPERATING REQUIREMENTS: Vee

= +5.0 V,

= +25

TA

Min
ts (H)
ts(Ll

Setup Time HIGH or LOW
RE to CP

th (H)
th (Ll

C

54174LS

PARAMETER

SYMBOL

0

UNITS

24
24

ns

Hold Time HIGH or LOW
RE to CP

0
0

ns

ts (H)
ts(Ll

Setup Time HIGH or LOW
Do, 01 or liOn to CP

10
10

ns

th (H)
th (Ll

Hold Time HIGH or LOW
Do, 01 or liOn to CP

0
0

ns

ts (H)
ts (Ll

Setup Time HIGH or LOW
SE to CP

15
15

ns

th (H)
th(Ll

Hold Time HIGH or LOW
SE to CP

0
0

ns

ts (H)
ts (Ll

sip to

Setup Time HIGH or LOW
CP

24
24

ns

ts (Ll

Setup Time HIGH or LOW
S to CP

15
15

ns

th (H)
th (Ll

Hold Time HIGH or LOW
S or sip to CP

0
0

ns

tw (H)

CP Pulse Width HIGH

15

ns

tw (Ll

M R Pulse Width LOW

15

ns

tree

Recovery Time
MR to CP

15

ns

ts (H)

4-369

CONDITIONS

Max

Fig. 3-6

I

Fig. 3-8
Fig. 3-16

323
CONNECTION DIAGRAM
PINOUT A

54LS/74LS323
a-BIT UNIVERSAL SHIFT/STORAGE REGISTER
(With Synchronous Reset and Common I/O Pins)
DESCRIPTION - The '323 is an 8-bit universal shift/storage register with 3state outputs. Its function is similar to the '299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to
minimize pin count. Separate inputs and outputs are provided for flip-flops
Co and Q7 to allow easy cascading. Four operation modes are possible: hold
(store), shift left, shift right, and parallel load. All modes are activated on the
LOW-to-HIGH transition of the Clock.

• COMMON I/O FOR REDUCED PIN COUNT
• FOUR OPERATION MODES: SHIFT LEFT, SHIFT RIGHT,
PARALLEL LOAD AND STORE
..:
• SEPARATE CONTINUOUS INPUTS AND OUTPUTS FROM a.G~Nb Q7
ALLOW EASY CASCADING
....•.•...........
• FULLY SYNCHRONOUS RESET
..:
...
• 3-STATE OUTPUTS FOR BUS ORIENTED APPLI~A1:IONS

ORDERING CODE: See Section 9

PKGS

COMMERCIAL GIit'Aibt'··
MILITARY GRADE
PIN r-----------~~~--------------~ PKG
Vee = +5.0 V ±10%,
OUT
Vee = +5.0 V ±5%,
TYPE
TA = O°C to +70°C
TA = -55°C to +125°C

Plastic
DIP(P)

A

74LS323PC

Ceramic
DIP (D)

A

74LS323DC

54LS323DM

4E

Flapak
(F)

A

74LS323FC

54LS323FM

4F

9Z

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
CP
Dso
DS7

So, S,
SR
OE" OE2

1/00-1/07

Qo, Q7

Clock Pulse Input (Active RiSing Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input (Active LOW)
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or
3-State Parallel Outputs
Serial Outputs

4-370

54174LS (U.L.)
HIGHILOW

0.5/0.25
0.5/0.25
0.5/0.25
1.0/0.50
0.5/0.25
0.5/0.25
1.0/0.50
65/15
(25)/(7.5)
10/5.0
(2.5)

323

FUNCTIONAL DESCRIPTION - The '323 contains eight edge-triggered O-type flip-flops and the interstage
logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type
of operation is determined by So and Sl as shown in the Mode SelectTable. All flip-flop outputs are brought out
through 3-state buffers to separate 1/0 pins that also serve as data inputs in the parallel load mode. 00 and 07
are also brought out on other pins for expansion in serial shifting of longer words.
A LOWsignal on SR overrides the Select inputs and allows the flip-flops tobe reset by the next rising edge of CPo
All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock
is in either state provided only that the recommended setup and hold times, relative tothe rising edge of CP, are
observed.
A HIGH signal on either OEl or OE2 disables the 3-state buffers and puts the 1/0 pins in the high impedance
state. In this condition the shift, load, hold and reset operations can still occur. The 3-state buffers are also
disabled by HIGH signals on both So and Sl in preparation for a parallel load operation.
MODE SELECT TABLE
INPUTS
SR

Sl

So

L
H
H
H
H

X
H
L
H
H

X
H
H
L
H

RESPONSE
CP

..J
S
S
S
X

Synchronous Reset; 00 - 07 = LOW
Parallel Load; I/On - On
Shift Right; 050 -00, 00 - 01, etc.
Shift Left; 057-07, 07-Qs, etc.
Hold

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

So

OE1======?cr~====--~====r-~====r-~====r-~====t-~====t-~====~
OE2
1/00

1/02

1/03

4-371

1/05

1/06

~--~

1/07

I

323
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74LS

PARAMETER
Min

lee

UNITS

CONDITIONS

Max
60

Power Supply Current

rnA

Vee = Max,
Outputs Disabled

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54/74LS

-

;.

PARAMETER

Cl = 15 pF
Min

UNITS

CONDITIONS

Max

35

MHz

Figs. 3-1, 3-8

fmax

Maximum Input Frequency

tPLH
tPHL

Propagation Delay
CP to 00 or 07

23
25

ns

tPLH
tPHL

Propagation Delay
CP to liOn

25
29

ns

tPZH
tPZL

Output Enable Time

18
23

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kO

tPHZ
tPLZ

Output Disable Time

15
15

ns

Figs. 3-3, 3-11, 3-12
RL = 2 kO, CL = 5 pF

Figs. 3-1, 3-8

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54/74LS

PARAMETER
Min

UNITS

ts (H)
ts (U

Setup Time HIGH or LOW
So or S1 to CP

th (H)
th (U

Hold Time HIGH or LOW
So or S1 to CP

0

ts (H)
ts (U

Setup Time HIGFr'il6t LOW
liOn, Dso, DS7 to CP

10
10

ns

th (H)
th (U

Hold Time HIGH or LOW
liOn, Dso, DS7 to CP

0
0

ns

ts (H)
ts(U

Setup Time HIGH or LOW
SR to CP

15
15

ns

th (H)
th (U

Hold Time HIGH or LOW
SR to CP

0

tw (H)
tw(U

CP Pulse Width HIGH or LOW

24
24

0

0
15
15

:,
",I

...., ".

-.,

4-372

CONDITIONS

Max
ns
Fig. 3-6
ns

Fig. 3-6

Fig. 3-6
ns
ns

Fig. 3-8

347
CONNECTION DIAGRAM
PINOUT A

54LS/74LS347
BCD TO 7-SEGMENT DECODER/DRIVER

-

Ao[1

~vcc

A,[l

~,

Li[!

~li
~a
~ii
~c
~ii

BI/RBO!:!
RBi [}:

A2[!
A31I

~e

GND[!

LOGIC SYMBOL
DESCRIPTION - The '347 is the same as the '47 except that the Output OFF
Voltage, VOH, is specified as 7.0 V rather than 15 V, with the same IOH limit
of 250 p,A. For all other information please refer to the '47 data sheet.

7

1

2

6

11

I A,I A2I A3I

RBI

LT

Ao

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

a

bed

e

I

13 12 11 10 9 15 14 4

A

74LS347PC

Ceramic
DIP (0)

A

74LS347DC

54LS347DM

7B

A

74LS347FC

54LS347FM

4L

9B
Vee = Pin 16
GND = Pin 8
:,~;:,.'

(F)

BII
RBO

YYYYYYy y

TYPE

Plastic
DIP (P)

Flatpak

9

"

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao~A3

RBT
LT
BIIRBO

8-9

DESCRIPTION
BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)

54/74LS
HIGH/LOW
0.5/0.25

0.5/0.25
0.5/0.25

-10.75
1.25/2.0
(1.0)
OC*/15
(7.5)

Segment Outputs (Active LOW)

'OC-Open Collector

4-373

352
CONNECTION DIAGRAM
PINOUT A

54LS/74LS352
DUAL 4-INPUT MULTIPLEXER
DESCRIPTION - The '352 is a very high speed dual 4-input multiplexer with
Common Select inputs and individual Enable inputs for each section. It can
select two bits of data from four sources. The two buffered outputs present
data in the inverted (complementary) form. The '352 is the functional equivalent of the '153 except with inverted outputs.

-

12,[I

~vcc
~Eb
~so
~13b

I"II

t1lll2b

10, [I

~l1b

z,[I

~IOb

GNO[I

~Zb

E,Ci:
s,[I

13,II
•
•
•
•

INVERTED VERSION OF THE '153
SEPARATE ENABLES FOR EACH MULTIPLEXER
INPUT CLAMP DIODE LIMIT HIGH SPEED TERMINATION EFFECTS
FULLY TTL AND CMOS COMPATIBLE

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74LS352PC

Ceramic
DIP (0)

A

74LS352DC

54LS352DM

68

Flatpak
(F)

A

74LS352FC

54LS352FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
lOa -13a
lOb -l3b
So, Sl

Ea

Et,

la,

Zb

54174LS (U.L.)
HIGH/LOW

DESCRIPTION
Side A Data Inputs
Side 8 Data Inputs
Common Select Inputs
Side A Enable Input (Active LOW)
Side 8 Enable Input (Active LOW)
Multiplexer Outputs (inverted)

0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

1iii i r1f 11 T1

LOGIC SYMBOL

14-

So

2-

S,

Ea lOa ha 12a l3a lOb hb 12b I3b Eb

Za

Zb

I

I
9

7

4-374

Vee = Pin 16
GND = Pin 8

352
FUNCTIONAL DESCRIPTION - The '352 is a dual 4-input multiplexer. It selects two bits of data from up to
four sources under the control of the common Select inputs (So, S,). The two 4-input multiplexer circuits have
individual active LOW Enables (Ea, Eb) which can be used to strobe the outputs independently. When the
Enables (Ea, ~) are HIGH, the corresponding outputs (2a, 2b) are forced HIGH.
The logic equations for the outputs are shown below.

Za = fa

• (loa • S, • So + ha • S, • So + 12a • S, • So + 13a • S, • So)

Zb = Eb • (lOb • S, • So

+ hb •

S, •

So + 12b • S, • So + I3b • S, • SO)

The '352 can be used to move data from a group of registers to a common output bus. The particular register
from which the data came would be determined by the state of the Select inputs. A less obvious application isa
function generator. The '352 can generate two functions of three variables. This is useful for implementing
highly irregular random logic.

•
TRUTH TABLE
SELECT
INPUTS

INPUTS (a or b)

OUTPUT

So

S,

E

10

I,

12

13

Z

X
L
L
H

X
L
L
L

H
L
L
L

X
L
H
X

X
X
X
L

X
X
X
X

X
X
X
X

H
H
L
H

H
L
L
H
H

L
H
H
H
H

L
L
L
L
L

X
X
X
X
X

H
X
X
X
X

X
L
H
X
X

X
X
X
L
H

L
H
L
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

4-375

352
LOGIC DIAGRAM
Ea

l1a

lOa

12a

S,

ba

So

lab

I2b

I1b

bb Eb

b

~

-

~

1
I

II

r

I

ll)

(

'7

I

~

I

T

Zb

Za

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74LS

PARAMETER
Min

lee

UNITS

CONDITIONS

Max

Power Supply Current

10

rnA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C
54174LS
SYMBOL

PARAMETER

CL = 15 pF
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Sn to Zn

22
38

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
En to Zn

15
20

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
In to Zn

12
12

ns

Figs. 3-1, 3-4

4-376

353
CONNECTION DIAGRAM
PINOUT A

54LS/74LS353
DUAL 4-INPUT MULTIPLEXER
(With 3-State Outputs)
DESCRIPTION - The '353 is a dual 4-input multiplexer with 3-state outputs.
It can select two bits of data from four sources using common select inputs.
The outputs may be individually switched to a high impedance state with a
HIGH on the respective Output (OE) inputs, allowing the outputs to interface
directly with bus oriented systems. It is fabricated with the Schottky barrier
diode process for high speed and is completely compatible with all Fairchild
TTL families.

• INVERTED VERSION OF 'LS253
• SCHOTTKY PROCESS FOR HIGH SPEED
• MULTIFUNCTION CAPABILITY

~

CEa!!
\

l3a

II

i2a

:EJso

[I

TIl l3b

ha

[I
IDa [I

~12b

Za[I

1:!2110b

GNOII

~Zb

~hb

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74LS353PC

Ceramic
DIP(o)

A

74LS353DC

54LS353DM

68

Flatpak
(F)

A

74LS353FC

54LS353FM

4L

98

INPUT LOADIIIIG/FAN-OUT: See Section 3 for U.L. definitions

lOa -ba
lOb -13b
So, S1
OEa
OEb
la, Zb

54n4LS (U.L.)
HIGH/LOW

DESCRIPTION

PIN NAMES

0.5/0.25
0.5./0.25
0.5/0.25
0.5/0.25
0.5/0.25
65/15
(25)/(7.5)

Side A Data Inputs
Side 8 Data Inputs
Common Select Inputs
Side A Output Enable Input (Active LOW)
Side 8 Output Enable Input (Active LOW)
3-State Outputs (inverted)

1iii i Y T!

LOGIC SYMBOL

1f1j

OEa IDa ha 12a 13a lOb hb 12b lab OEb

14- So
2-

S1
Za

Zb

!

I
9

4-377

~vcc

:ill OEb

s,[t

VCC = Pin 16
GND = Pin 8
,,";

353
FUNCTIONAL DESCRIPTION - The '353 contains two identical 4-input multiplexers with 3-state outputs.
They select two bits from four sources selected by common Select inputs (So, S1), The 4-input multiplexers
have individual Output Enable (OEa, OEb) inputs which when HIGH, force the outputs to a high impedance
(high Z) state. The logic equations for the outputs are shown below:

Za =

OEa • (loa • S1 • So

Zb = OEb • (lab • S1 • So

+ l1a
+ I1b

• S1 • So
• S1 • So

+ 12a •
+ 12b •

S1 • So
S1 • So

+ l3a •
+ I3b •

S1 • So)
S1 • So)

Iftheoutputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to
3-state devices whose outputs are tied together are designed so that there is no overlap.
TRUTH TABLE
SELECT
DATA INPUTS
INPUTS

OUTPUT
OUTPUT
ENABLE

So

S1

10

11

12

13

OE

Z

X
L
L

X
L
L
L

X
L
H
X

X
X
X
L

X
X
X
X

X
X
X
X

H
L
L
L

(Z)

H

L

L
L
H

H

X
X
X
X
X

H
X
X
X
X

X
L
H
X
X

X
X
X
L
H

L
L
L
L
L

L
H
L

H

H

H
H
H

H
L
H

H
L

Address inputs So and S, are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
(Z) = High Impedance

LOGIC DIAGRAM

OEb

ha

ba

tab

Za
4-378

lOa

353
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74LS

PARAMETER
Min
Outputs HIGH

lee

Power Supply
Current

UNITS

CONDITIONS

Max
12
mA

Outputs OFF

Vee = Max
In. Sn. OEn = Gnd
Vee = Max. OEn = 4.5 V
In. Sn = Gnd

14

AC CHARACTERISTICS: Vee = +5.0 V. TA = +25 0 C (See Section 3 for waveforms and load configurations)
54/74LS
SYMBOL

PARAMETER

UNITS

CL =45 pF
Min

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Sn to In

24
32

ns

Figs. 3-1. 3-20

tPLH
tPHL

Propagation Delay
In to In

15
15

ns

Figs. 3-1. 3-4

tPZH
tPZL

Output Enable Time

18
18

ns

Figs. 3-3. 3-11. 3-12
RL = 667!l

tPHZ
tPLZ

Output Disable Time

18
18

ns

Figs. 3-3. 3-11. 3-12
RL = 667!l. CL = 5 pF

4-379

•

365A
CONNECTION DIAGRAM
PINOUT A

54LS/74LS365A

- ~vcc
~E2
::::J--1fL
II
~

Ed"1

HEX 3-STATE BUFFER

~

[I

(With Common 2-lnput NOR Enable)

J--4::: ~
rm
[f J--~ ~

II
11

4::: ~~

II
GNO[I

ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP(P)

OUT
A

Ceramic
DIP(D)

A

Flatpak
(F)

A

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

TYPE

74LS365APC
74LS365ADC
74LS365AFC

98
54LS365ADM

68

54LS365AFM

4L

Inputs
Outputs

INPUTS

OUTPUTS

E1

E2

D

L
L
H

L
L

L
H

L
H

X

X

H

X
X

Z
Z

H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial
Z ~ High Impedance

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

TRUTH TABLE

PKG

54/74LS (U.L.)
HIGH/LOW
0.5/0.25
25/15
(7.5)

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

lee

Power Supply Current

24

mA

tPLH
tPHL

Propagation Delay
Data to Output

16
22

ns

Figs. 3-1, 3-4
CL = 50 pF

tPZH
tPZL

Output Enable Time

24
30

ns

Figs. 3-3, 3-11, 3-12
RL = 667 n, CL = 50 pF

tPLZ
tPHZ

Output Disable Time

20
25

ns

Figs. 3-3,3-11,3-12
RL = 667 n, CL = 5 pF

·De limits apply over operating temperature range; Ae limits apply at TA

~

+25°e and Vee

4-380

~

+5.0 V.

Vee = Max, VIN =OV, VE"=4.5 V

366A
CONNECTION DIAGRAM
PINOUT A

54LS/74LS366A

- :ill
[!
~f5l- TIl.
IT

El[i"

HEX 3-STATE INVERTER BUFFER

Vee

TIjE2

(With Common 2-lnput NOR Enable)

~r--t::: :illTIl
:ill
~r-c
IT

[I

[I
[!

~

~ :II

GNO[I

ORDERING CODE: See Section 9
PIN
PKGS

OUT

Plastic
DIP(P)

A

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

TRUTH TABLE

PKG
TYPE

INPUTS

98

74LS366APC

Ceramic
DIP (D)

A

74LS366ADC

54LS366ADM

68

Flatpak
(F)

A

74LS366AFC

54LS366AFM

4L

OUTPUT

E1

E2

D

L
L
H

L
L

L
H

H
L

X

X

H

X
X

Z
Z

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
H = HIGH Voltage level
l = lOW Voltage level
X = Immaterial
Z = High Impedance

54174LS (U.L.)
HIGH/LOW

PINS

0.5/0.25
25/15
(7.5)

Inputs
Outputs

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

Power Supply Current

21

mA

Vee = Max, VIN =0 V, VE =4.5 V

tPLH
tPHL

Propagation Delay

12
22

ns

Figs. 3-1, 3-5
CL = 50 pF

tPZH
tPZL

Output Enable Time

24
30

ns

Figs. 3-3, 3-11, 3-12
RL = 667 n, CL = 50 pF

tPLZ
tPHZ

Output Disable Time

20
25

ns

Figs. 3-3, 3-11, 3-12
RL = 667 n, CL = 5 pF

lee

'De limits

apply over operating temperature range;

AC limits apply at TA = +25°C and

4-381

Vee

= +5.0 V.

367A
CONNECTION DIAGRAM
PINOUT A

54LS/74LS367 A
::ill Vee

Err -

HEX 3-STATE BUFFER

II y~;-- ~E
11:
:ill
[I
:ill

(With Separate 2-Bit and 4-Bit Sections)

[I

[!

yK= TIl

:::::y-LL TIl
-L TIl~

IT
GNO\I

ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP(P)

OUT
A

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%
TA = -55°C to +125°C

74LS367APC

TYPE
98

Ceramic
DIP (D)

A

74LS367ADC

54LS367ADM

68

Flatpak
(F)

A

74LS367AFC

54LS367AFM

4L

Inputs
Outputs

INPUTS
E

D

L
L
H

L
H
X

OUTPUT
L
H
Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

TRUTH TABLE

PKG

54174LS (U.L.)
HIGH/LOW
0.5/0.25
25/15
(7.5)

DC AND AC CHARACTERISTICS: See Section 3"
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

Power Supply Current

24

mA

Vee = Max, VIN =OV, Ve =4.5 V

tPLH
tPHL

Propagation Delay

16
22

ns

Figs. 3-1, 3-4
CL = 50 pF

tPZH
tPZL

Output Enable Time

24
30

ns

Figs. 3-3, 3-11, 3-12
RL = 667 n, CL = 50 pF

tPLZ
tPHZ

Output Disable Time

20
25

ns

Fi gs. 3-3, 3-11, 3-12
RL = 667 n, CL = 5 pF

lee

'De limits apply over operating temperature range; Ae limits apply at TA = +25'e and Vee = +5.0 V.

4-382

368A
CONNECTION DIAGRAM
PINOUT A

54LS/74LS368A

-

e['1
~vcc
II y~ ~r-- t1§Je

HEX 3-INPUT INVERTER BUFFER
(With Separate 2-Bit and 4-Bit Sections)

~

[I

yrL ElTIl
II
[I

[!

y'-L :TIl
-----L !ill~

II
GNOII

ORDERING CODE: See Section 9
PIN
PKGS
Plastic
DIP(P)
Ceramic
DIP(D)
Flatpak
(F)

OUT
A

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

74LS368APC

TYPE
98

A

74LS368ADC

54LS368ADM

68

A

74LS368AFC

54LS368AFM

4L

Inputs
Outputs

INPUTS
E

D

L
L
H

L
H
X

OUTPUT
H
L
Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

TRUTH TABLE

PKG

54/74LS (U.L.)
HIGH/LOW
0.5/0.25
25115
(7.5)

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

Power Supply Current

21

mA

Vee = Max, VIN =OV, VE=4.5 V

tPLH
tPHL

Propagation Delay

12
22

ns

Figs. 3-1, 3-5
CL = 50 pF

tPZH
tPZL

Output Enable Time

24
30

ns

Fi 9s. 3-3, 3-11, 3-12
RL = 667 n, CL = 50 pF

tPLZ
tPHZ

Output Disable Time

20
25

ns

Figs. 3-3,3-11,3-12
RL = 667 n, CL = 5 pF

lee

'oe limits apply over operating temperature range; AC limits apply at TA = +25°C and Vee = +5.0 V.

4-383

•

373
CONNECTION DIAGRAM
PINOUT A

54LS/74LS373
OCTAL TRANSPARENT LATCH

<>Ell
00

(With 3-State Outputs)

-

II

DolI

rm Oe

01E
01[[

~oe

Od!:

iEJOS

odI

~OS

03!!

!mO.

031!

!rn O'

GNO@
DESCRIPTION - The '373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent to the
data when Latch Enable (LEI is HIGH. When LE is .LOW, the data that meets
the setup times is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high impedance state.

OUT

LOGIC SYMBOL

DO 01 02 03 D. Os 06 07
LE

111-c OE

ORDERING CODE: See Section 9

PKGS

ITIJLE

i i r i 1j 1j Y1j

• EIGHT LATCHES IN A SINGLE PACKAGE
• 3-STATE OUTPUTS FOR BUS INTERFACING

PIN

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to+125°C

00 01 02 03 O. Os 06 07

PKG
TYPE

Plastic
DIP{P)

A

74LS373PC

Ceramic
DIPlD)

A

74LS373DC

54LS373DM

4E

Flatpak
(F)

A

74LS373FC

54LS373FM

4F

! ! ! ! 1l1~ 1~ 1~

9Z
Vcc = Pin 20.
GND = Pin 10.

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Do.-07
LE
OE

00-07

~vcc
~07
~07

DESCRIPTION
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Latch Outputs

4-384

54/74LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
65/15
(25)/(7.5)

373
FUNCTIONAL DESCRIPTION - The '373 contains eight O-type latches with 3-state output buffers. When the
Latch Enable (LE) input is HIGH, data on the On inputs enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time its 0 input changes. When LE is LOW the latches
store the information that was present on the 0 inputs a setup time preceding the HIGH-to-LOW transition of
LE. The 3-state buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with
entering new data into the latches.

LOGIC DIAGRAM

Do

05

06

LE--I~~~--;---~--~--~--+---L---t---.---t-~~--t-~~-1r-~

OE

00

03

4-385

05

06

•

373
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54/74LS

PARAMETER
Min

lee

UNITS

CONDITIONS

mA

Vee = Max, OE = 4.5 V
On, LE = Gnd

Max

Power Supply lOut uts OFF
p
Current

40

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25·C (See Section 3 for waveforms and load configurations)
54/74LS
SYMBOL

PARAMETER

CL = 50 pF
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
On to On

18
20

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
LE to On

30
30

ns

Figs. 3-1, 3-8

tPZH
tPZL

Output Enable Time

28
36

ns

Figs. 3-3, 3-11,3-12
RL = 6670

tpHZ
tPLZ

Output Disable Time

20
25

ns

Figs. 3-3, 3-11, 3-12
RL = 6670, CL = 5.0 pF

UNITS

CONDITIONS

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25·C
SYMBOL

54174LS

PARAMETER
Min

Max

ts (H)
ts(U

Setup Time HIGH or LOW
On to LE

0
0

ns

th (H)
th (U

Hold Time HIGH or LOW
On to LE

10
10

ns

LE Pulse Width HIGH or LOW

15
15

ns

tw (H)

tw(U

4-386

Fig. 3-14

Fig. 3-8

374
CONNECTION DIAGRAM
PINOUT A

54LS/7 4LS37 4
OCTAL D-TYPE FLIP-FLOP
(With 3-State Outputs)
DESCRIPTION - The '374 is a high speed, low power octal Ootype flip-flop
featuring separate Ootype inputs for each flip-flop and 3-state outputs for bus
oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The '374 is manufactured using advanced low power
Schottky technology and is compatible with all Fairchild TTL families.

• EDGE-TRIGGERED D-TYPE INPUTS
• BUFFERED POSITIVE EDGE-TRIGGERED CLOCK
• 3-STATE OUTPUTS FOR BUS ORIENTED APPLICATIONS
LOGIC SYMBOL
ORDERING CODE: See Section 9
COMMERCIAL GRADE

PIN
PKGS

= +5.0 V ±5%,
= O°C to +70°C

Vee

OUT

TA

Plastic
OIP(P)

A

74LS374PC

Ceramic
OIP(D)

A

74LS3740C

MILITARY GRADE

= +5.0 V ±10%,
= -55°C to +125°C

Vee
TA

3

TYPE

7

8 13 14 17 18

5

6

9 12 15 16 19

cp

11

OE

9Z
54LS3740M

4

PKG

4E

2

Vcc = Pin 20
Flatpak
(F)

A

74LS374FC

54LS374FM

GND = Pin 10

4F

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
54174LS (U.L.)
HIGH/LOW

DESCRIPTION

PIN NAMES

0.5/0.25
0.5/0.25
0.5/0.25
65/15
(25)/(7.5)

Oata Inputs
Clock Pulse Input (Active Rising Edge)
3-State Output Enable Input (Active LOW)
3-State Outputs

00-D7
CP
OE

00-07

LOGIC DIAGRAM
Do

05

06

cP-;I~~--4r-+-----4r-+-----4r-+-----4~+-----4r-r----~--+-----~-r-----.

00

0,

03

4-387

05

06

07

374
FUNCTIONAL DESCRIPTION - The '374 consists of eight edge-triggered flip-flops with individual D-type
inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet .the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of
the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedence
state. Operation of the OE input does not affect the state of the flip-flops.

TRUTH TABLE
INPUTS OUTPUTS
Dn

CP

H
L
X

J
J
X

OE

On

L
L
H

H
L
Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

Icc

UNITS

CONDITIONS

Max

Power Supply Current,
Outputs OFF

45

mA

Vee = Max, Dn = Gnd
OE = 4.5 V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174LS
SYMBOL

PARAMETER

CL = 45 pF
Min

UNITS

CONDITIONS

Max

f max

Maximum Clock Frequency

MHz

Figs. 3-1, 3-8

tpLH
tPHL

Propagation Delay
CP to On

28
28

ns

Figs. 3-1, 3-8

tPZH
tPZL

Output Enable Time

28
28

ns

Figs. 3-3, 3-11, 3-12
RL = 667 0.

tPHZ
tPLZ

Output Disable Time

20
25

ns

Figs. 3-3, 3-11, 3-12
RL = 667 0., CL.= 5 pF

35

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54174LS

PARAMETER
Min

UNITS

ts (H)
ts (U

Setup Time HIGH or LOW
Dn to CP

20
20

ns

th (H)
th (U

Hold Time HIGH or LOW
Dn to CP

0
0

ns

tw (H)
tw (U

CP Pulse Width HIGH or LOW

15
15

ns

4-388

CONDITIONS

Max

Fig. 3-6

Fig. 3-8

375
CONNECTION DIAGRAM
PINOUT A

54LS/74LS375
4-BIT LATCH

-

IT
Ch II
0, IT
0,

DESCRIPTION - The '375 is a 4-bit D-type latch for use as temporary storage for binary information between processing units and input/output or
indicator units. When its Enable (E) input is HIGH, a latch is transparent,
i.e., the 0 output will follow the D input each time it changes. When E is
LOW a latch stores the last valid data present on the D input preceding the
HIGH-to-LOW transition of E. The '375 is functionally identical to the '75
except for the corner power pins.

~vcc
~D4

~a4

E1,2

[I

~a4

02

IT

~E3,4

Q2

[!

~03

02

IT

~Q3

GNOI!

~03

LOGIC SYMBOL

1

7

15

9

I I I I
01

ORDERING CODE: See Section 9
PIN
PKGS

OUT

02

03

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

74LS375PC

Ceramic
DIP (D)

A

74LS375DC

54LS375DM

68

Flatpak
(F)

A

74LS375FC

54LS375FM

4L

98

1 2 - E3,4
0,

02

03

DESCRIPTION

01-04

Data Inputs
Latches 1, 2 Enable Input
Latches 3, 4 Enable Input
Latch Outputs

01-04

Complementary Latch Outputs

D1-D4
E1,2
E3,4

Vcc = Pin 16
GND = Pin 8

54174LS (U.L.)
HIGH/LOW
0.5/0.25
2.0/1.0
2.0/1.0
10/5.0
(2.5)
10/5.0
(2.5)

4-389

04

! 1! LLt I II

INPUT LOADING/FAN-OUT: See Section 3 for U.L.definitions
PIN NAMES

04

4 - E1,2

375
LOGIC DIAGRAM
(1/4 of diagram shown)

DATA

ENABLE

TRUTH TABLE
(Each Latch)

I ~:
f t>o

tn

tn + 1

D
H
L

0
H
L

tn = Bit time before Enable negative going
transition.

tn

+ 1

= Bit time after Enable negative gOing

transition.

H = HIGH Voltage Level
L = LOW Voltage Level

TO OTHER LATCH

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

lee

UNITS
12

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

TA

CONDITIONS

Max

= +25°C (See Section

mA

Vee

= Max

3 for waveforms and load configurations)

54/74LS

SYMBOL

PARAMETER

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tpHL

Propagation Delay
Dn to On

27
17

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
Dn to an

20
15

ns

Figs. 3-1, 3-4

tPLH
tpHL

Propagation Delay
En to On

27
25

ns

tPLH
tPHL

Propagation Delay
En to On

30
15

ns

AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

TA

Figs. 3-1, 3-8

= +25°C
54/74LS

PARAMETER
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time HIGH or LOW
Dn to En

20

th (H)
th (U

Hold Time HIGH or LOW
Dn to En

0

ns

tw (H)

En Pulse Width HIGH

20

ns

ns
Fig. 3-14

4-390

Fig. 3-8

377
CONNECTION DIAGRAM
PINOUT A

54LS/74LS377
OCTAL D FLIP-FLOP

E[I

(With Common Enable and Clock)

Oou

-

~vcc

}!IOl

00[[

:mOl

IT
0, II
ad:!

liIOe
:mo,

odI

:E]os

D3[!

:ll)O4

0,

mas

od]:

j]]04

GNOffi

TIlcp

DESCRIPTION - The '377 isan 8-bit register built using advanced low power
Schottky technology. This register consists of eight O-type flip-flops with a
buffered common clock and a buffered common input enable. The device is
packaged in the space-saving (0.3 inch row spacing) 20-pin package .

LOGIC SYMBOL

• a-BIT HIGH SPEED PARALLEL REGISTERS
• POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOPS
• FULLY BUFFERED COMMON CLOCK AND ENABLE INPUTS

1i i r i 7'j ri

E Do 01 02 03 04 05 06 07

"- cp

ORDERING CODE: See Section 9

00 Q1

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
OIP(P)

A

74LS377PC

Ceramic
OIP(D)

A

74LS3770C

54LS377DM

4E

Flatpak
(F)

A

74LS377FC

54LS377FM

4F

9Z

Q2

03

Q4

as

E
00-07
CP
00-07

DESCRIPTION
Enable Input (Active LOW)
Oata Inputs
Clock Pulse Input (Active Rising Edge)
Flip-flop Outputs

4-391

07

! ! ! ! }2 ,t ,t ,l
Vcc = Pin 20
GND = Pin 10

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

06

54174LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

•

377
FUNCTIONAL DESCRIPTION - The '377 consists of eight edge-triggered D flip-flops with individual D inputs
and 0 outputs. The Clock (CP) and Enable input (8 are common to all flip-flops.
When E is LOW, new data is entered into the register on the next LOW-to-HIGH transition of CPo When E is
HIGH, the register will retain the present data independent of the CPo

TRUTH TABLE

INPUTS

E
H
L
L

OUTPUT

CP Dn
X

X

H
J
-I L

On

No change
H
L

H ~ HIGH Voltage Level
L. ~ LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

4-392

377
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0

UNITS
28

V, TA

CONDITIONS

Max

= +25°C (See

mA

Vee

= Max

Section 3 for waveforms and load configurations)

54174LS
SYMBOL

PARAMETER

CL

= 15 pF

Min
f max

Maximum Clock Frequency

tpLH
tpHL

Propagation Delay
CP to an

AC OPERATING REQUIREMENTS: Vee
SYMBOL

25
25

V, TA

MHz

Figs. 3-1, 3-8

ns

Figs. 3-1, 3-8

= +25°C
54174LS

PARAMETER

CONDITIONS

Max

30

= +5.0

UNITS

Min

UNITS

ts (H)
ts (U

Setup Time HIGH or LOW
Dn to CP

10
10

ns

th (H)
th (U

Hold Time HIGH or LOW
Dn to CP

5.0
5.0

ns

ts (H)
ts (U

Setup Time HIGH or LOW
Eto CP

10
20

ns

th (H)
th (U

Hold Time HIGH or LOW
Eto CP

5.0
5.0

ns

tw (H)
tw (U

CP Pulse Width HIGH or LOW

20
20

ns

4-393

CONDITIONS

Max

Fig. 3-6

Fig. 3-8

378
CONNECTION DIAGRAM
PINOUT A

54LS/74LS378
PARALLEL 0 REGISTER

-

0011

~vcc
~Os

Dol!

iEJOS

01!:!

~04

ElI

(With Enable)

odI

~04
~03
~03

[!

~cp

all!
0211

GNO

DESCRIPTION - The '378 is a 6-bit register with a buffered common enable.
This device is similar to the '174, but with common Enable rather than common Master Reset.
LOGIC SYMBOL
•
•
•
•
•

6-BIT HIGH SPEED PARALLEL REGISTER
POSITIVE EDGE-TRIGGERED D-TYPE INPUTS
FULLY BUFFERED COMMON CLOCK AND ENABLE INPUTS
INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS
FULL TTL AND CMOS COMPATIBLE

liiiYYY

E Do 0 1 O2 0 3 0 4 05

9-

ORDERING CODE: See Section 9
PIN
PKGS

OUT

cp
0 0 0 1 O2 0 3 0 4 aS

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
OIP(P)

A

74LS378PC

Ceramic
DIP (0)

A

74LS3780C

54LS3780M

68

Flatpak
(F)

A

74LS378FC

54LS378FM

4L

1!!)o}2}S

98
Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L definitions
PIN NAMES
E
00-05
CP
00-05

DESCRIPTION
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-flop Outputs

4-394

54174LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)

378
FUNCTIONAL DESCRIPTION - The '378 consists of eight edge-triggered O-type flip-flops with individual 0
inputs and
outputs. The Clock (CP) and Enable (Ei inputs are common to all flip-flops.

a

When the E input is LOW, new data is entered into the register on the LOW-to-HIGH transition of the CP input.
When the E input is HIGH the register will retain the present data independent of the CP input.

TRUTH TABLE
OUTPUT

INPUTS
E

CP On

H ~
L ~
L --F

On
No change
H
L

X
H
L

•

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

O2

0,

cp

03

~
cp

0

r-E

cp

0

r-E
Q

cp

0

r-E
Q

cp

0

E
Q

4>
Q,

4-395

cp

0

r-E
Q

cp

0

r-E
Q

Q

378
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

lee

UNITS

Power Supply Current

AC CHARACTERISTICS: Vee

=

22

+5.0 V, TA

=

CONDITIONS

Max
mA

Vee = Max, Dn
CP = S

= E = Gnd

+25°C (See Section 3 for waveforms and load configurations)
54174LS

SYMBOL

Ct. = 15 pF

PARAMETER

Min
fmax

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay
CP to On

AC OPERATING REQUIREMENTS: Vee
SYMBOL

30
27
27

=

+5.0 V, TA

=

CONDITIONS

Min

MHz

Figs. 3-1, 3-8

ns

Figs. 3-1, 3-8

+25°C

54174LS

PARAMETER

UNITS

Max

UNITS

CONDITIONS

Max

ts (H)

Setup Time HIGH, Dn to CP

20

ns

Fig. 3-6

th (H)

Hold Time HIGH, Dn to CP

5.0

ns

Fig. 3-6

ts (U

Setup Time LOW, Dn to CP

20

ns

Fig. 3-6

th (U

Hold Time LOW, Dn to CP

5.0

ns

Fig. 3-6

ts (H)

Setup Time HIGH, E to CP

30

ns

Fig. 3-6

th (H)

Hold Time HIGH, E to CP

5.0

ns

Fig. 3-6

ts (U

Setup Time LOW, E to CP

30

ns

Fig. 3-6

th (U

Hold Time LOW, E to CP

5.0

ns

Fig. 3-6

tw (H)

CP Pulse Width HIGH

20

ns

Fig. 3-8

4-396

379
CONNECTION DIAGRAM
PINOUT A

54LS/74LS379
(With Enable)

tEJ03

008:

D'~

EJD2

Q,[!

TIle2

a, E?:

~02

GND!!

~cp

LOGIC SYMBOL

EDGE-TRIGGERED D-TYPE INPUTS
BUFFERED POSITIVE EDGE-TRIGGERED CLOCK
BUFFERED COMMON ENABLE INPUT
TRUE AND COMPLEMENT OUTPUTS

OUT

12

0,

Do

O2

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
OIP(P)

A

74LS379PC

Ceramic
DIP (0)

A

74LS3790C

54LS3790M

68

Flatpak
(Fl

A

74LS379FC

54LS379FM

4L

A,

00

02

3

2

6

7

11 10 14 15

98

DESCRIPTION

00-03
CP
00-03

Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-flop Outputs

00-03

Complement Outputs

4-397

03

YI YI YI YI

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

E

03

9 - cp

COMMERCIAL GRADE

PIN NAMES

13

.l I I I I

ORDERING CODE: See Section 9
PIN

5

4

1

E

PKGS

~vcc
~C3
~D3

DESCRIPTION - The '379 is a 4-bit register with buffered common Enable.
This device is similar to the '175 but features the common Enable rather
than common Master Reset.

•
•
•
•

--.

EO::
oolI
colI

QUAD PARALLEL REGISTER

54/74LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

•

379
FUNCTIONAL DESCRIPTION - The '379 consists of four edge-triggered D-type flip-flops with individual D
inputs and 0 and Q outputs. The Clock (CP) and Enable
00

0
1

2
3
4

5
6
7

8
9

+5 TRUTH TABLE
(Input on CP1)

OUTPUTS

COUNT
03

02

01

00

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

COUNT
0
1

2
3
4

OUTPUTS
03

02

01

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

H = HIGH Voltage Level
L = LOW Voltage Level

H = HIGH Voltage Level
L = LOW Voltage Level

STATE DIAGRAM

4-406

J

a

9

>--

BCD TRUTH TABLE
(Input on CPo; 00 to CP1)

CP

-0 CD

~

MR

J

;0 Co

390
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

54174LS

PARAMETER
Min

hH

Input HIGH Current, CPa, CP1

lee

Power Supply Current

I
I

UNITS

CONDITIONS

0.1

mA

Vee = Max, VIN = 5.5 V

30

mA

Vee = Max

Max

'390
'393

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
54174LS
SYMBOL

PARAMETER

CL = 15 pF
Min

UNITS

CONDITIONS

Max

f max

Maximum Count Frequency
CPo ('390) or CP ('393)

40

fmax

CP1 Maximum Count Frequency

20

tpLH
tPHL

Propagation Delay
CPa ('390) or CP ('393) to 00

15
15

ns

tPLH
tPHL

Propagation Delay
CP1 ('390) to 01

21
21

ns

tPLH
tPHL

Propagation Delay
CP1 ('390) to 02

30
30

ns

tPLH
tPHL

Propagation Delay
CP1 ('390) to 03

21
21

ns

tpLH
tPHL

Propagation Delay
CP ('393) to 01

30
30

ns

tPLH
tPHL

Propagation Delay
CP ('393) to 02

40
40

ns

tPLH
tPHL

Propagation Delay
CP ('393) to 03

54
54

ns

Figs. 3-1, 3-9

tPHL

Propagation Delay
MR to On

35

ns

Figs. 3-1, 3-17

MHz

Figs. 3-1, 3-9

MHz

Figs. 3-1, 3-9

Figs. 3-1, 3-9

Figs. 3-1, 3-9

Figs. 3-1, 3-9

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

54174LS

PARAMETER
Min

UNITS

CONDITIONS

Max

tw (U

CP or CPa Pulse Width LOW

12

ns

Fig. 3-9

tw (U

CP1 Pulse Width LOW

25

ns

Fig. 3-9

tw (H)

MR Pulse Width HIGH

20

ns

Fig. 3-17

tree

Recovery Ti me
MR to CP

15

ns

Fig. 3-17

4-407

•

393
CONNECTION DIAGRAM
PINOUT A

54LS/74LS393
DUAL MODULO-16 COUNTER

cpO::

~

MR[I
Qo[I
Q1[I

DESCRIPTION - The '393 contains a pair of high speed 4-stage ripple
counters. Each half of the '393 operates as a modul0-16 binary divider,
with the last three stages triggered in a ripple fashion. The flip-flops are
triggered by a HIGH-to-LOW transition of their CP inputs. Each half of
each circuit type has a Master Reset input which responds to a HIGH signal
by forcing all four outputs to the LOW state. For detail specifications,
please refer to the '390 data sheet.

QdI

~Q1

Q3[I

:2J Q2

GNOIT

}]Q3

LOGIC SYMBOL
(each half)

1,13 - and buffered common Output Enable (OEl inputs.

05

IT

mos

06

[!

lllo6

od:!
GNoffi

:m07
TIl LE

This device is functionally indentical to the 'LS573, but has inverted outputs.
For truth tables, discussion of operations and ac and dc specifications, please
refer to the 'LS373 data sheet, but note that the data to output delays
are 5.0 ns longer for the 'LS563 than for the 'LS373.
• INPUTS AND OUTPUTS ON OPPOSITE SIDES OF PACKAGE
ALLOWING EASY INTERFACE WITH MICROPROCESSORS
• USEFUL AS INPUT OR OUTPUT PORT FOR MICROPROCESSORS
• FUNCTIONALLY IDENTICAL TO 'LS573
• INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS
• FULLY TTL AND CMOS COMPATIBLE
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
Vee = +5.0 V ±5%,

TA

MILITARY GRADE
Vee

= O°C to +70°C

TA

= +5.0 V ±10%,

= -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

Ceramic
DIP (D)

A

74LS563DC

54LS563DM

4E

Flatpak
(F)

A

74LS563FC

54LS563FM

4F

74 LS563PC

LOGIC SYMBOL

111-<:

iiiii,ii

DO 0, 02 03 D. 05 06 07
LE
OE

00 0, 02 03 O. 05 06 07

1!!!!!!!!

9Z
Vcc = Pin 20
GND = Pin 10

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Do-07
LE
OE

00-07

DESCRIPTION
Data Inputs
Latch Enable Input (Active HIGH)
3-State Output Enable Input (Active LOW)
3-State Latch Outputs

54n4LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25

65/15
(25)/(7.5)

4-429

~vcc

Do

•

564
CONNECTION DIAGRAM
PINOUT A

54LS/74LS564
OCTAL O-TYPE FLIP-FLOP
(With 3-State Outputs)

-

OElI
Doll:

~O'

D,I:!

DESCRIPTION - The '564 is a high speed low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Output Enable (OEL
The information presented to the 0 inputs is stored in the flip-flops on the
LOW-to-HIGH Clock (CP) transition.
This device is functionally identical to the 'LS574, but has inverted outputs.
For complete discussions of operations, truth tables, ac and dc electrical
specifications, refer to the 'LS374 data sheet.

D2[i

~O2

D31]:

rm

D7[!
GNDffi

Iillcp

DslI
D6!!

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plasti.c
DIP (P)

A

74LS564PC

Ceramic
DIP (0)

A

74LS5640C

54LS5640M

4E

A

74LS564FC

54LS564FM

4F

Flatpak
(F)

LOGIC SYMBOL

iiiiifii
Do D, D2 D3 D4 Ds D6 D7

ORDERING CODE: See Section 9

PKGS

11-

cp

1-[I
alI

]]I K2
]]cp

1]0

GNOII

ORDERING CODE: See Section 9

PKGS

~

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

A

9000DC

9000DM

B

9001 DC

9001DM

C

9020DC

9020DM

D

9022DC

9022DM

A

9000FC

9000FM

B

9001FC

9001FM

•

PKG
TYPE

J=AoBoCoO
K=AoBoCoO

6A

6B

31

Flatpak
(F)

C

9020FC

9020FM

D

9022FC

9022FM

PINOUT B

JKIT
So [I

PINOUT C

-

CD IT

Cpj}

till CD

cPj}

1i]Co

lil J3

J[l

:E]JK

J[l

ElJK

TIl K3

Kd3:
Kl []:

TIlJ
EJK2

K[i

TIlJ

SO []:

EJVec

TIl CD

J'd}

]]Ii<2

a[!

]]cp

~a

GNOII

-

PINOUT D

~vee

~

Kd1
Jl\1

4L

CD IT

:ill Vee

a[!

:TIl Kl

a[!

lili<
:TIl SO

alI

]]10

alI

:§]a

GNO!!

J]a

GNO!!

J]a

J=Ao§oCoO
K=AoBoCoO

5-3

9XXX Series
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES

JK Input
Data Inputs
Clock Pulse Input
Direct Clear Input
Direct Set Input
Outputs

JK

I n. Kn, .Tn.

Rn

CP

CO

So

Q,c:i

9000 (U.L.)
HIGH/LOW

9001 (U.L.)
HIGH/LOW

9020 (U.L.)
HIGH/LOW

9022 (U.L.)
HIGH/LOW

3.0/2.0
1.5/1.0
1.5/1.0
4.0/2.7
4.0/2.7
30/8.8
(7.8)

3.0/2.0
1.5/1.0
1.5/1.0
4.0/2.7
4.0/2.7
30/8.8
(7.8)

6.0/4.0
1.5/1.0
3.0/2.0
4.0/2.7

6.0/4.0
1.5/1.0
3.0/2.0
4.0/2.7
4.0/2.7
30/8.8
(7.8)

30/8.8
(7.8)

LOGIC SYMBOLS
9020

9000
14 JK

2
4
5

6

12

10

3

9
1

3-~""""

8

10

5

9

4

11

13

2-+----~-~

Vee = Pin 14
GNO = Pin 7

Vee = Pin 16
GND = Pin 8

9001

9022
2

4
5

10

6

12--......--"

9-+--1
1
3
10
11

8

2--+---"""'---'

13

Vee = Pin 14
GND = Pin 7

Vee = Pin 16
GND = Pin 8

ASYNCHRONOUS OPERATION

Co

L
L
H

L
H
L

H

H

SYNCHRONOUS OPERATION

OUTPUTS

INPUTS
So

Q

9

4i1-"'L.;,e...J

BEFORE CLOCK
AFTER CLOCK
OUTPUTS
INPUTS
OUTPUTS

Q

H
H
H
L
H
L
SYNCHRONOUS
INPUTS CONTROL

H = HIGH Voltage Level
L = LOW Voltage Level

L'

Q

Q

J

K

Q

Q

L
L
H
H

H
H
L
L

L*
H*
X
X

X
X
L*
H*

L
H
H
L

H
L
L
H

= Input does not go HIGH at any time while the clock is

LOW.
H" = Input is HIGH at some time while the clock is LOW.
X = Immaterial

5-4

9XXX Series
FUNCTIONAL DESCRIPTION - The TTL 9000 series has four flip-flops to satisfy the storage req uirements of a
logic system. All are master/slave JK designs and have the same high speed and high noise immunity as the rest
of the 9000 series. As with the gates, all inputs have diode clamps to reduce ringing caused by long lines and
impedance mismatches.
The J K type flip~flop was chosen for all flip-flop elements in this family because of its inherent logic power. The
input function required to produce a given sequence of states for a JK flip-flop will, in general, contain more
"don't care" conditions than the corresponding function for an RS flip-flop. These additional "don't care"
conditions will, in most cases, reduce the amount of gating elements required to implement the input function.
The master/slave design offers the advantage of a dc threshold on the clock input initiating the transition of the
outputs, so that careful control of clock pulse rise and fall times is not required.
Data is accepted by the master while the clock is in the LOW state. Refer to the truth tables fordefinition of HIGH
and LOW data. Transfer from the master to the slave occurs on the LOW-to-HI GH transition of the clock. When
the clock is HIGH, the J and K inputs are inhibited.
A joint (J K) input is provided for all flip-flops in this family. The common input removes the necessity of gating
the clock signal with an external gate in many applications. This not only reduces package count, but also
reduces the possibility of clock skew problems, since with internal gating provided, all flip-flops may be driven
from a common clock line. Several TTL drivers may be used in parallel to drive this common clock line if the load
exceeds the fan-out capability of the 9009 buffer.
The asynchronous inputs provide ability to control the state of the flip-flop independent of static conditions of
the clock and synchronous inputs. Both asynchronous set and clear are provided on all flip-flops except the
9020, which because of a logic trade-off has only clear inputs. The set or clear pin being LOW absolutely
guarantees that one output will be HIGH, but if opposing data is present at the synchronous inputs and theflipflop is clocked, the LOW output may momentarily spike HIGH synchronous with a positive transition of the
clock. If the LOW output of the flip-flop is connected to other flip-flop inputs clocked from the same line, the
spike will be masked by the clock. If the clock is suspended during the time when the asynchronous inputs are
activated, no spike will occur. When the spikes can cause problems, a simple solution is to common thejointJ K
inputs with the synchronous set or reset signal.
Synchronous Operation - The truth table defines the next state of the flip-flop after a LOW-to-HIGH transition
of the clock pulse. The next state is a function of the present state and the J and K inputs as shown in the table.
The J and K inputs in the table refer tothe basic flip-flopJ and K inputs as indicated on the logic symbols. These
internal inputs are for every flip-flop the result of a logic operation on the external J and K inputs. This operation
is represented symbolically by AND gates in the logic symbol for each flip-flop. Logic symbols are in
accordance with MIL Standard 8068.
The L * symbol in the J and K input column is defined as meaning that Input does not go HIGH atany time while
the clock Is LOW.
The H* symbol in the J or K input column is defined as meaning that the Input is HIGH at some time while the
clock is LOW.
The X symbol indicates that the condition of that input has no effect on the next state of the flip-flop.
The Hand L symbols refer to steady state HIGH and LOW voltage levels, respectively.
Unused Inputs - The 9001. 9020 and 9022 all have active level LOW synchronous inputs. When not in use they
must be grounded. All other unused inputs, including asynchronous, should be tied HIGH for maximum
operating speed.

5-5

•

9XXX Series
DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee
SYMBOL

DOC

PARAMETER

Min

25°C

Max

Min

75°C

Max

Min

= +5.0

UNITS

V ±5%
CONDITIONS

Max
V

Guaranteed
Input HIGH
Threshold

0.85

V

Guaranteed
Input LOW
Threshold

0.45

0.45

V

Vee = 4.75 V,
IOL = 14.1 mA
Vee - 5.25 V,
IOL = 16 mA

-1.60

-1.60

-1.60

-3.20

-3.20

-3.20

-6.40
-4.32

-6.40
-4.32

-6.40
-4.32

-1.41

-1.41

-1.41

-2.82

-2.82

-2.82

-5.64
-3.78

-5.64
-3.78

-5.64
-3.78

28
33
30

28
33
30

28
33
30

1.9

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.85

0.85

VOL

Output LOW Voltage

0.45

ilL

Input LOW Current
All J, K Inputs
CP Inputs 9000, 9001
JK Inputs 9000, 9001
CP Inputs 9020, 9022
JK inputs 9020, 9022
So, Co (all Flip-flops)
Input LOW Current
All J, K Inputs
CP Inputs 9000, 9001
JK Inputs 9000, 9001
CP Inputs 9020, 9022
:;!.K I!!puts 9020, 9022
So, Co (all Flip-flops)

1.8

1.6

mA

Vee = 5.25 V
VIN = 0.45 V
5.25 V on
Other Inputs

Vee = 4.75 V
VIN = 0.45 V
5.25 V on
Other Inputs

mA

Power Supply Current
lee

9000
9001
9020, 9022 each Flip-flop

DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee
SYMBOL

PARAMETER

-55°C
Min

Max

2.0

25°C
Min

Max

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

0.9

VOL

Output LOW Voltage

0.4

0.4

1.7

5-6

= +5.0

125°C
Min

So at Gnd
So at Gnd
C01, C02 at Gnd

mA

V ±10%

UNITS

CONDITIONS

Max
V

Guaranteed
Input HIGH
Threshold

0.8

V

Guaranteed
Input LOW
Threshold

0.4

V

Vee = 4.5 V,
IOL = 12.4 mA
Vee - 5.5 V,
IOL = 16 mA

1.4

9XXX Series
DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: (Cont'd)
-55°C

PARAMETER

SYMBOL

Min

IlL

Icc

Input LOW Current
All J, K Inputs
CP Inputs 9000, 9001
JK Inputs 9000, 9001
CP Inputs 9020, 9022
JK Inputs 9020, 9022
So, CD (all Flip-flops)
Input LOW Current
All J, K Inputs
CP Inputs 9000, 9001
JK Inputs 9000, 9001
CP Inputs 9020, 9022
JK Inputs 9020, 9022
So, CD (all Flip-flops)
Power Supply Current
9000
9001
9020, 9022 each Flip-flop

25°C

Max

Min

Max

-1.60

-3.20

-3.20

-3.20

-6.40
-4.32

-6.40
-4.32

-6.40
-4.32

-1.24

-1.24

-1.24

-2.48

-2.48

-2.48

-4.96
-3.35

-4.96
-3.75

-4.96
-3.35

24
28
27

24
28
27

24
28
27

tPHL

tsetup

20
20
30
35

9000XM
9000XC
9001XM, 9020XM, 9022XM
9001XC, 9020XC, 9022XC

J or K Data Entry
J, K or JK
trelease

I

9000 only
19001,9020,9022

J or K Data Entry
9000 only
Pulse
Widths

Clock
So or Co
Toggle Frequency

9001,9020,
9022

Vee = 5.5 V
V,N = 4.5 V
5.5 V on
Other Inputs

rnA

Vee = 4.5 V
V,N = 0.4 V
5.5 V on
Other Inputs

rnA

So at Gnd
So at Gnd
COl, C02, at Gnd

rnA

UNITS

CONDITIONS

Max

Clock to Output
So or Co to Output
Clock to Output
So or Co to Output
J, K or JK

CONDITIONS

= 15 pF of all flip-flops unless otherwise noted)

LIMITS

PARAMETER

UNITS

Max

-1.60

Min
tPLH

Min

-1.60

SWITCHING CHARACTERISTICS (TA = 25°C, Vee = 5.0 V, CL = Cl
SYMBOL

125°C

30
35
10
15
17
10
1.0
4.0

ns
Figs. a, b, c
ns
ns

Figs. a, c

ns

Figs. a, b, c

ns

Figs. a, c

ns

Figs. a, b,

ns

Figs. a,

ns

Figs. a, b,

Positive
Negative
Positive
Negative
Negative

20·
25·
8.0·
10·
25·

9000 only
9001,9020,
9022

20·

MHz

Figs. a,

50·

MHz

Figs. a, b,

"Typical Value

5-7

C

C
C

C
C

•

9XXX Series
SWITCHING TEST NOTES
tPLH and \PHL
1. VJK should be kept at the HIGH level when performing tPLH/tPHL test.
2. Drive the clock pulse input with a suitable pulse source. tPLH and tpHL delays are as defined in the waveforms.
RECOMMENDED INPUT PULSE SOURCES

ADJUSTABLE
DELAY
NETWORK

PULSE
GENERATOR
FREQUENCY" 2 MHz
DUTY CYCLE"" 50%

-1

no I I
VJK

L

GND TO INHIBIT
FOR tPLH/tPHL

I

ADJUSTABLE
DELAY
NETWORK
TTL

I

Vep

I

DTL9932 gates with adjustable capacitors connected from extender inputs to ground make suitable delay elements.

tsetup
1. tsetup is defined as the minimum time required for a HIGH to be present at a synchronous logic input at any
time during the LOW state of the clock in order for the flip-flop to respond to the data.
2. The test for tsetup is performed by adjusting the timing relationship between the Vcp and VJK inputs to the
tsetup minimum value. A device that passes the test will have the output waveform shown. The output of a
device that does not pass the tsetup test will remain at a static logic level (no switching will occur).
trelease
1. trelease is defined as the maximum time allowed for a HIGH to be present at a synchronous logic input at any

time during the LOW state of the clock and not be recognized.
2. The test for trelease is performed by adjusting the timing relationship between Vcp and VJK to the trelease
maximum value. The outputs of devices that pass will remain at static logic levels. In order to check both J
and K sides of the flip-flop it is necessary to perform the test with the flip-flop in each of its two possible
states, i.e., set and clear. This can be accomplished by making use of the appropriate direct inputs to
establish the state before a test. The outputs of devices that do not pass the trelease test will exhibit pulses
instead of static levels.

5-8

9XXX Series
SWITCHING TEST CIRCUITS
9020/9022

9000/9001

Vee

Vee

VJK ---+---1

Vep-...----+------I

VJK_-~~===:t~--~+==J

Vep~r_----r----r-_,

'---+----+-------1r- VOUT

I-___

_.--t_

VOUT

CL
CL

Fig. a

•

Fig. b
Vee = Pin 5.0 V
R = 2.0 kfl
CI = CL = 15 pF including probe and jig capacitance

WAVEFORM
> 3.0 V

1.5 V
< 0.4 V
> 3.0 V

1.5 V
< 0.4 V

l"I_~

< 0.4 V

I

I

\

f,""

> 3.0 V

1.5 V

ISETUP OR IRELEASE

\

/0o'

{

Lt,

~L'PLH

Fig. c

5-9

9XXX Series
CONNECTION DIAGRAMS
PINOUT A

9002 • 9003 • 9004
9007 • 9012
9016 • 9017
NAND GATES/HEX INVERTERS
DESCRIPTION - The 9002, 9003, 9004, 9007, and 9012 are active LOW level
output AND gates commonly know as NAND gates. The 9016 and 9017 are
hex inverters with input and output characteristics identical to a NAND gate.
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

A

9002DC, 9012DC

9002DM,9012DM

Ceramic

B

9003DC

9003DM

DIP

C

9004DC

9004DM

D

9007DC

9007DM

E

9016DC, 9017DC

9016DM,9017DM

A

9002FC, 9012FC

9002FM,9012FM

B

9003FC

9003FM

(D)

Flatpak
(F)

PKG
TYPE
PINOUT B
6A

C

9004FC

9004FM

D

9007FC

9007FM

E

9016FC,9017FC

9016FM,9017FM

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
9XXX (U.L.)
HIGH/LOW

PINS
Inputs
Outputs

1.5/1.0
30*/8.8

'9012 and 9017 have open-collector outputs

PINOUT C

IT I II r-NCIT

IT

GNoE

r--

r--

rD

fL
L

-

PINOUT E

~vcc

IT

~
~

II IT -

:ill
:ill

IT -----,

3]

fill NC

~

IT f----,

IT

-

PINOUT D

~
~
~

NCIT
NC[I
GNO[I

~

5-10

~vcc

r

~

~NC

~

9XXX Series
DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee
SYMBOL

O°C

PARAMETER

25°C

75°C

= +5.0 V ±5%

UNITS

CONDITIONS

Min Max Min Max Min Max
1.9

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOH

Output HIGH Voltage
(except 9012, 9017)

1.8
0.85

2.4

0.85

2.4

0.45
VOL

Input HIGH Current

0.45

60

60

IOH

Output HIGH Current
9012,9017

lee

Power Supply
Current, each gate

tPLH

Propagation Delay
Input to Output
Propagation Delay
Input to Output

I

I

ON
OFF

6.1
1.7
3.0

9012,9017

9012, 9017

5-11

V

Guaranteed Input
LOW Threshold

V

Vee = 4.75 V,
IOH = -1.2 rnA,
Inputs at VIL

V

Vee = 5.25 V,
IOL = 16 rnA,
VIN = 5.25 V
Vee = 4.75 V,
IOL = 14.1 rnA,
Inputs at VIH

JJ.A

Vee = 5.25 V,
VIN = 4.5 V
Gnd on Other Inputs

rnA

Vee = 5.25 V
VIN = 0.45 V,
5.25 V on Other Inputs
Vee - 4.75 V
VIN = 0.45 V,
5.25 V on Other Inputs
Vee = 4.75 V,
VIN = VIL,
VOUT = 5.5 V

-1.41

-1.41

250

250

JJ.A

6.1
1.7

6.1
1.7

rnA

13

3.0

45

3.0

15

3.0

Guaranteed Input
HIGH Threshold

-1 ..6

Input LOW Current
-1.41

tPHL

0.45

-1.6

V

0.45

Output LOW Voltage

-1.6
IlL

0.85

2.4

0.45

0.45

hH

1.6

15

ns

ns

= Open
= Gnd
CL = 15 pF,
RL = 4.0 kn
CL = 15 pF,
VIN
VIN

Fig. 3-4
Fig. 3-4

CL = 15 pF, Fig. 3-4
RL - 400 n
CL = 15 pF, Fig. 3-4

•

9XXX Series
= +5.0 V ±10%

DC AND AC CHARACTERISITICS OVER MILITARY TEMPERATURE RANGE: Vee
-55°C

PARAMETER

SYMBOL

25°C

125°C

UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

. Input HIGH Voltage

VIL

Input LOW Voltage

VOH

Output HIGH Voltage
(except 9012, 9017)

2.0

1.7
0.8

2.4

0.9

2.4

0.4
VOL

ilL

2.4

0.4

0.4

60

60

-1.6

-1.6

-1.6

-1.24

-1.24

-1.24

250
5.5
1.6

Input HIGH Current

Icc

Power Supply
Current, each gate

tPLH

Propagation Delay
Input to Output

9012,9017

Propagation Delay
Input to Output

9012,9017

I
I

ON
OFF

5.5
1.6
3.0

WORST CASE TURN OFF DELAY
VERSUS
AMBIENT TEMPERATURE

3.0

45

3.0

12

3.0

15

0

0

-

......r--

V

Vee = 5.5 V,
IOL = 17.6 mA,
VIN = 5.5 V
Vee = 4.5 V,
IOL = 13.6 mA,
Inputs at VIH
Vee = 5.5 V,
VIN = 4.5 V
Gnd on Other Inputs

mA

Vee = 5.5 V
VIN = 0.4 V
5.5 V on Other Inputs
Vee = 4.5 V
VIN = 0.4 V
5.5 V on Other Inputs

250

J1.A

Vee = 4.5, VIN
Vour = 5.5 V

5.5
1.6

mA

."'-

30

I

1-'"

Vee = 4.5 V,
IOH = -1.32 mA,
Inputs at VIL

ns

36

..... .d"" I

V

ns

Vee =5.DV

5

Guaranteed Input
LOW Threshold

10

SEE FIG. 12

or- t--JAX AT CL '" 150~ ...

V

/

"

24

18

./

12

MAXATCL-15pF

I I
I I
J

""

yell

15

SEE FIG. 12

"1'--

I I
J

I'--.,.
t--,

VCC"s.OV

--

MAX AT 150 pF

~A~rpF- -

I I

$.0

_jlN

= Open
= Gnd
CL = 15 pF,
RL = 4.0 kO
CL = 15 pF,
CL = 15 pF,
RL = 400 0
CL = 15 pF,

MIN AT 15 pF

jF_ o

0
55

-55

25

25
T A - AMBIENT TEMPERATURE - QC

lA-AMBIENT TEMPERATURE_oC

5-12

= VIL

VIN
VIN

WORST CASE TURN ON DELAY
VERSUS
AMBIENT TEMPERATURE

0

5

Guaranteed Input
HIGH Threshold

J1.A

Input LOW Current

Output HIGH Current
9012, 9017

V

0.4

Output LOW Voltage

IOH

tPHL

0.8

0.4

0.4

hH

1.4

-

Fig. 3-4
Fig. 3-4
Fig. 3-4
Fig. 3-4

9XXX Series
CONNECTION DIAGRAMS
PINOUT A

9005 • 9008
9006
EXTENDABLE AND-OR-INVERT GATES
EXTENDER (9006)

"Four extenders (9006) may be tied tothese
terminals

Vee = Pin 14
GND = Pin 7

PINOUT B

DESCRIPTION: - The 9005 and 9008 are AN D-OR-INVERT gates which may
be OR extended with the use of the 9006.

ORDERING CODE: See Section 9
PIN
PKGS

Ceramic
DIP (0)

Flatpak
(F)

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

A

9005DC

9005DM

B

90·06DC

9006DM

C

9008DC

9008DM

A

9005FC

9005FM

B

9006FC

9006FM

C

9008FC

9008FM

PKG
TYPE

6A

Vee = Pin 14
GND = Pin 7

PINOUT C

31

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Non-extendable Gate Inputs
Extendable Gate Inputs
All Inputs
Outputs

9005 (U.L.)
HIGH/LOW

9006 (U.L.)
HIGH/LOW

9008 (U.L.)
HIGH/LOW

2.25/1.5

2.25/1.5
30/8.8
(33)/(8.5)

"Four extender (9006) may be tied to these
terminals

1.5/1.0
2.25/1.5
30/8.8
(33)/(8.5)

"Outputs on 9006 have open-emitter and collector

5-13

Vee = Pin 14
GND = Pin 7

9XXX Series
DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee = +5.0 V ±5%
SYMBOL

PARAMETER

O°C

25°C

75°C

UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOL

ilL

lee

~Iee

1.9

1.8

1.6

V

Guaranteed Input HIGH
Threshold Voltage
Guaranteed Input LOW
Threshold Voltage

0.85

0.85

0.85

V

0.45

0.45

0.45

V

0.45

0.45

0.45

V

-1.6
-1.41
-2.4
-2.12

-1.6
-1.41
-2.4
-2.12

-1.6
-1.41
-2.4
-2.12

7.7
13.6
17.7

7.7
13.6
17.7

7.7
13.6
17.7

rnA

All Inputs Open

3.4
5.1
10.2

3.4
5.1
10.2

3.4
5.1
10.2

rnA

All Inputs Except
Extender Inputs Gnd

Extra Current Drain
when one 9006 Extender is
attached to a 9005 Gate ON

2.05

2.05

2.05

rnA

All Inputs HIGH

Extra Current Drain
when one 9006 Extender is
attached to a 9005 gate OFF

2.54

2.54

2.54

rnA

All Inputs Gnd

Output LOW Voltage

Input LOW Current
9005 Non-Extendable Gate
Input LOW Current
Extendable Gates and Extender
Power Supply Current, ON
9005 Non-Extendable Gate
9005 Extendable Gate
9008
Power Supply Current, OFF
9005 Non-Extendable Gate
9005 Extendable Gate
9008

rnA
rnA

Vee = 5.25 V,
IOL = 16 rnA,
Vee - 4.75 V,
IOL = 14.1 rnA
Vee
Vee
Vee
Vee

=
=
=
=

Max VIN = .45 V
5.25 V on
Min
Other
Max
Inputs
Min

DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee = +5.0 V ±10%
SYMBOL

PARAMETER

-55°C

25°C

125°C

UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOL

IiL

2.0

1.7
0.8

1.4

V

Guaranteed Input HIGH
Threshold Voltage
Guaranteed Input LOW
Threshold Voltage

0.9

0.8

V

0.4

0.4

0.4

V

0.4

0.4

0.4

V

-1.6
-1.24
-2.4
-1.86

-1.6
-1.24
-2.4
-1.86

-1.6
-1.24
-2.4
-1.86

Output LOW Voltage

Input LOW Current
9005 Non-extendable Gate
Input LOW Current
Extendable Gate and Extender

rnA
rnA

Vee = 5.5 V,
IOL = 17.6 rnA
Vee - 4.5 V,
IOL = 13.6 rnA
Vee
Vee
Vee
Vee

=
=
-

NOTE:
Output characteristics above apply to a 9005 (both gates) or a 9008.
Input characteristics above apply to a 9005 (both gates) or a 9008 using either the internal gates or an external 9006 extender.

5-14

Max
Min
Max
Min

VIN =.4 V
5.5 V on
Other
Inputs

9XXX Series
DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee

-55°C

PARAMETER

SYMBOL

25°C

125°C

= +5.0

UNITS

V ±10% (Cont'd)

CONDITIONS

Min Max Min Max Min Max

Icc

t.1lee

Power Supply Current, ON
9005 Non-extendable Gate
9005 Extendable Gate
9008

6.5
11.3
12.5

6.5
11.3
12.5

6.5
11.3
12.5

mA

All Inputs Open

Power Supply Current, OFF
9005 Non-extendable Gate
9005 Extendable Gate
9008

3.1
4.7
9.4

3.1
4.7
9.4

3.1
4.7
9.4

mA

All Inputs Except
Extender Inputs Gnd

Extra Current Drain
from one 9006 Extender Gate ON

1.61

1.61

1.61

mA

All Inputs HIGH

Extra Current Drain
from one 9006 Extender Gate 0 FF

2.35

2.35

2.35

mA

All Inputs Gnd
9006 Attached to a 9005

NOTE:
Output characteristics apply to a 9005 (both gates} or a 9008.
Input characteristics apply to a 9005 (both gates} or a 9008 using either the internal gates or an external 9006 extender.

= 25°C)

SWITCHING CHARACTERISTICS (TA
LIMITS

SYMBOL

UNITS

TEST CONDITIONS

Min

Max

tPLH
tPHL

3.0
3.0

12
14

ns

Vee = 5.0 V, CL = 15 pF
9005 Non-extendable Gate Only, See Figure a

tPLH
tpHL

3.0
3.0

15
12

ns

Vee = 5.0 V, CL = 15 pF, CN = 5.0 pF
9005 Extendable Gate and 9008, See Figure b

~tPLH

-2.0

4.0

~tPHL

-2.0

4.0

9006 Only

ns

The 9006 is tested by measuring its propagation
time through the 9005. The delay readings shall
not exceed the 9005 readings by the specified
amount. See Figure c

SWITCHING CHARACTERISTICS
TEST CIRCUITS
VIN

Vec

«h

~

2.0 kn

-.

tJ--l:==J- ""

9009

JL ~
d)-1 - '
--

1~1.0MHz

AMP ~ 4.0 V
WIDTH ~ 200 ns
t,=tf~10ns

CL

= 15

PFi.l

~

9005

CL

-= -=

= 15

VOUT

PF:1r

-= -=

Note: Capacitance includes probe and jig capacitance

Fig. a 9005 Non-Extendable Gate

5-15

•

9XXX Series
SWITCHING CHARACTERISTICS (Cont'd)
TEST CIRCUITS

Vee

VIN

VOUl

SL

f -1.0 MHz
AMP - 4.0 V
INPUT
WIDTH - 200 no
Ir = If ~ 10 ns

CN

= 5.0

pF

CL

= 15 pF

Note: Capacitance includes probe and jig capacitance

Fig. b 9005 or 9008 Extendable Gate

Vee

2.0kll

9009

Note: Capacitance includes probe and jig capacitance

Fig. c

9006 Extender

NOTES:
With switch in postion (1) measure delay of 9005. With switch in position (2)
measure delay (9005) + ' Capacitances include probe and jig
capacitances.

Fig. d

Switching Waveform

5-16

9XXX Series
CONNECTION DIAGRAM
PINOUT A

9009
NAND BUFFER
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V, ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

IT r-----

TYPE

II

t---

A

9009DC

9009DM

6A

Flatpak
(F)

A

9009FC

9009FM

31

-

NC[I

Ceramic
DIP (D)

~vcc

IT r----1
IT

11
GNOIT

~~

~
~

iTIl NC
~
~
~

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

Inputs
Outputs

9XXX (U.L.)

Vcc = Pin 14
GND = Pin 7

HIGH/LOW
3.0/2.0
90/26
(99)/(25.5)

DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee
SYMBOL

O°C

PARAMETER

25°C

75°C

UNITS

= +5.0 V ±5%
CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

Vil

Input LOW Voltage

VOL

Output LOW Voltage

hH

Input HIGH Current

III

1.9

1.8
0.85

1.6
0.85

0.45

0.85

Power Supply
Current (each gate)

tPlH
tPHl

Propagation Delay

I

ON
IOFF

Guaranteed Input
HIGH Threshold

V

Guaranteed Input
LOW Threshold
Vee = 5.25 V,
IOl = 48 rnA,
VIN = 5.25 V
Vee = 4.75 V,
IOl = 42.3 rnA,
Inputs at VIH

0.45

0.45

V

120

120

IJ.A

Vee = 5.25 V, VIN = 4.5 V
Gnd on Other Inputs

-3.2

-3.2

-3.2
rnA

-2.82

-2.82

-2.82

Vee = 5.25 V, VIN = .45 V
5.25 V on Other Inputs
Vee - 4.75 V, VIN -.45 V
5.25 V on Other Inputs

14.6
3.4

14.6
3.4

14.6
3.4

rnA

VIN = Open
VIN - Gnd

ns

Figs. 3-1, 3-4
Cl = 15 pF

Input LOW Current

leeH
leel

V

3.0
2.0

5-17

17

13

9XXX Series
DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee = +5.0 V ±10%
SYMBOL

-55°C

PARAMETER

25°C'

125°C

UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

Vil

Input LOW Voltage

VOL

Output LOW Voltage

hH

Input HIGH Current

ill

Input LOW Current

1.7

2.0
0.8

0.9

0.4

-3.2

leeH
leel

Power Supply
Current (each gate)

tPlH
tPHl

Propagation Delay

I ON
I

OFF

1.4
0.8

V

Guaranteed Input
LOW Threshold
Vee = 5.5 V,
IOl = 52.8 rnA
VIN = 5.5 V
Vee - 4.5 V,
IOl = 40.8 rnA,
Inputs at VIH

0.4

V

120

120

/loA

Vee = 5.5 V, VIN = 4.5 V
Gnd on Other Inputs

-3.2

-3.2
rnA

Vee = 5.5 V VIN = 0.4 V
5.5 V on Other Inputs
Vee = 4.5 V VIN = 0.4 V
5.5 V on Other Inputs

rnA

VIN = Open
VIN - Gnd

ns

Figs. 3-1, 3-4
Cl = 15 pF

-2.48

-2.48

12.9
3.2

12.9
3.2

12.9
3.2

5-18

Guaranteed Input
HIGH Threshold

0.4

-2.48

4.0
3.0

V

15
10

9XXX Series
CONNECTION DIAGRAM
PINOUT A

9014
QUAD EXCLUSIVE-OR GATE

0:

DESCRIPTION - The 9014 consists of four Exclusive-OR gates, useful in a
large number of code conversion, parity generation/checking, and com parison applications. The Exclusive-OR gate produces an output when the inputs
are complementary. Two gates have an additional inverted output which provides directly a compare capability. The Boolean expressions for the gates
are: Z = AS + AB; Z = AB + AB.

PKGS

OUT

~-f( El

mvcc

:ill

rG(

TIJ
:ill

......

]]

A[I

elI JJD

z[!
zIT -«:JGNO[!

ORDERING CODE: See Section 9
PIN

II
II

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

A

9014DC

9014DM

6B

Flatpak
(F)

A

9014FC

9014FM

4L

~

vcc = Pin 16
GND = Pin 8

TYPE

Ceramic
DIP (0)

:TIl

TRUTH TABLE
INPUTS OUTPUTS

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
9XXX Series
HIGH/LOW

PINS
Inputs
Outputs
Pins 3, 7, 9, 13
Pins 6, 10

2.25/1.5

A

B

Z

Z

L
L
H
H

L
H
L
H

L
H
H
L

H
L
L
H

H = HIGH Voltage Level
L = LOW Voltage Level

30/8.8
(33)/(8.5)
28.5/7.9
(30)/(7.75)

DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee = +5.0 V ±5%
SYMBOL

PARAMETER

GOC

25°C

75°C

UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOL

Output LOW Voltage

1.9

1.8
0.85

0.45

5-19

1.6
0.85

0.45

0.85

0.45

V

Guaranteed Input
HIGH Threshold

V

Guaranteed Input
LOW Threshold

V

Vee = 5.25 V,
IOL = 16 mA
IOL = 14.4 mA
(Pins 6 & 10)
Inputs = 5.25 V or 0 V
per Truth Table

•

9XXX Series
DC AND AC CHARACTERISTICS OVER COMMERCiAL TEMPERATURE RANGE: Vee
SYMBOL

O°C

PARAMETER

25°C

75°C

= +5.0 V ±5%

UNITS

CONDITIONS

V

Vee = 4.75 V,
IOL = 14.1 rnA
IOL = 12.7 rnA
(Pins 6 & 10)
Inputs = 5.25 V or 0 V
per Truth Table

Min Max Min Max Min Max

VOL

ilL

Icc

Output LOW Voltage

tPHH 2
tpLL 2
tPLH 2
tPHL 2

0.45

0.45

-2.4

-2.4

-2.4

-2.1

-2.1

-2.1

Input LOW Current

Power Supply
Current, each gate
Power Supply Current
Per Inverter

tPLH 1
tpHL 1
tPHH 1
tPLL 1

0.45

rnA

ON
OFF
ON
OFF

4.5

4.5

4.5

8.7
7.6
6.1
1.7

8.7
7.6
6.1
1.7

8.7
7.6
6.1
1.7

rnA
rnA
rnA

One Input = 5.5 V,
One Input = Gnd
Inputs - Gnd
Inputs = 5.5 V
Input Node HIGH
Input Node LOW

Switching Tests

3.0
3.0
6.0
6.0

13
15
28
28

ns

CL = 15 pF, VINl
Fig. a, Fig. b

= 5.0 V

Switching Tests

7.0
7.0
10
10

17
19
32
32

ns

CL = 15 pF, VINl
Fig. a, Fig. c

=0 V

DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee
SYMBOL

Vee = 5.25 V, VIN = .45 V
Other Inputs = 5.25 V
Vee - 4.75 V, VIN -.45 V
Other Inputs = 5.25 V

PARAMETER

-55°C

25°C

125°C

= +5.0 V ±10%

UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

2.0

1.7
0.8

0.4

VOL

1.4
0.9

0.4

0.8

5-20

0.4

Guaranteed Input
HIGH Threshold

V

Guaranteed Input
LOW Threshold

V

Vee = 5.5 V,
IOL = 17.6 rnA
IOL = 16 rnA
(Pins 6 & 10)
Inputs = 5.5 V or 0 V
per Truth Table
Vee - 4.5 V,
IOL = 13.6 rnA
IOL = 12.4 rnA
(Pins 6 & 10)
Inputs = 5.5 V or 0 V
per Truth Table

0.4

Output LOW Voltage

0.4

V

0.4

9XXX Series
DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee
-55°C

PARAMETER

SYMBOL

25°C

125°C

= +5.0 V ±10%

UNITS

CONDITIONS

Min Max Min Max Min Max
-2.4

-2.4

IlL

rnA

-1.86

-1.86

-1.86

4.2

4.2

4.2

8.1
7.2
5.5
1.6

8.1
7.2
5.5
1.6

8.1
7.2
5.5
1.6

ON

Power Supply
Current, each gate

lee

Vee = 5.5 V, VIN = 0.4 V
Other Inputs = 5.5 V
Vee = 4.5 V, VIN = 0.4 V
Other Inputs = 5.5 V

-2.4

Input LOW Current

OFF

Power Supply Current
Per Inverter

ON
OFF

One Input = 5.5 V
One Input = Gnd
Inputs Gnd
Inputs = 5.5 V
Input Node HIGH
Input Node LOW

rnA
rnA
rnA

tPLH 1
tpHL 1
tPHH 1
tPLL 1

Switching Tests

3.0
3.0
6.0
6.0

10
12
22
22

ns

CL = 15 pF, VIN1
Fig. a, Fig. b

= 5.0 V

tPHH 2
tPLL 2
tPLH 2
tPHL 2

Switching Tests

7.0
7.0
10
10

14
16
26
26

ns

CL = 15 pF, VIN1
Fig. a, Fig. C

=0

SWITCHING TEST CIRCUIT
Vee
2k
YOUT!

~~2

O-~

YIN!

...c-<>

1/49002

SL a-::f"""--J'
'~1

AMP. ~4.0Y
PULSE WIDTH

---f\)'

.....

VIN2

I

lo:u:T.'
...... I
-- -- ---

MHz

t, =t, S 10 ns

1-----""1

±'' '

= 200 ± 20 ns

=

I

Cl *

Cl*I
"::'~

includes probe and jig
capacity

*CL

Fig. a
WAVEFORMS

, " =1-~_,=~--m}=-:,::'"

YIN' - . : : . i - - - - - - - - - - - \ - - - - - - 1 . 5 Y

~

-I

--------'o~'nn~J":":- nnnt"
YOUT!

-IPHl!

=~\.

-IPlH!

'""" ----- -----------1- ------...,

----1.5Y

'o~, mn\:"~'mnnF",~,

1.5Y

Fig. c

Fig. b

5-21

V

•

9XXX Series
CONNECTION DIAGRAM
PINOUT A

9015
QUAD NOR GATE
DESCRIPTION - The 9015 consists of three 2-input and one 4-input NOR
gates. The NOR gate produces a LOW output if any of the inputs are HIGH.

PKG

IT
II
II

TYPE

[I

II
II

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Ceramic
DIP (0)

A

9015DC

9015DM

68

Flatpak
(F)

A

9015FC

9015FM

4L

IT
GND

II

-

:!!I Vee

~Jt :m

m
:ill

~~

TIl
TIl
~

]]

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

9XXX (U.L.)
HIGH/LOW
1.5/1.0
30/8.8
(33)/(8.5)

DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee
SYMBOL

PARAMETER

O°C

25°C

75°C

UNITS

= +5.0 V ±5%
CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOH

Output HIGH Voltage

VOL

1.9

1.8
0.85

2.4

1.6
0.85

2.4

0.85

2.4

0.45

0.45

0.45

0.45

0.45

0.45

Output LOW Voltage

5-22

V

Guaranteed Input
HIGH Threshold

V

Guaranteed Input
LOW Threshold

V

Vee = 4.75 V,
IOH = -1.2 rnA,
Inputs = VIL

V

Vee = 5.25 V,
IOL = 16 rnA,
Inputs = 5.25 V
Vee - 4.75 V,
IOL = 14.1 rnA,
Inputs = VIH

9XXX Series
DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE (Cont'd)
SYBMOL

O°C

PARAMETER

25°C

75°C

UNITS

CONDITIONS

Min Max Min Max Min Max

hL

Power Supply
Current, each gate
OFF

tPLH
tPHL

-1.6

-1.6

rnA

-1.41

-1.41

-1.41

rnA

6.55

6.55

6.55

8.75

8.75

8.75

3.38

3.38

3.38

6.77

6.77

6.77

Input LOW Current

ON
Icc

-1.6

3.0
3.0

Propagation Delay

13
15

rnA

rnA

ns

Vee = 5.25 V, VIN =.45 V
5.25 V on Other Inputs
Vee - 4.75 V, VIN - .45 V
5.25 V on Other Inputs
Inputs HIGH
Inputs HIGH
(4-lnput Gate Only)
Inputs LOW
Inputs LOW
(4-lnput Gate Only)
CL = 15 pF
Fig. 3-4

DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee = +5.0 V ±10%
SYMBOL

-55°

PARAMETER

25°C

125°C

UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOH

Output HIGH Voltage

2.0

1.7
0.8

2.4

0.9

2.4

0.4
VOL

hL

2.4

0.4

V

Guaranteed Input
HIGH Threshold

V

Guaranteed Input
LOW Threshold

V

Vee = 4.5 V,
IOH = -1.32 rnA,
Inputs = VIL

V

Vee = 5.5 V,
Inputs = 5.5 V,
IOL = 17.6 rnA
Vee - 4.5 V,
VIN ;= VIH,
IOL = 13.6 rnA

0.4

0.4

0.4

0.4

-1.6

-1.6

-1.6

rnA

-1.24

-1.24

-1.24

rnA

6.07

6.07

6.07

Input LOW Current

Power Supply
Current, each gate
OFF

tPLH
tPHL

0.8

Output LOW Voltage

ON
Icc

1.4

8.14

8.14

8.14

3.2

3.2

3.2

6.4

6.4

6.4

3.0
3.0

Propagation Delay

5-23

10
12

rnA

rnA

ns

Vee = 5.5 V, VIN = 0.4 V
5.5 V on Other Inputs'
Vee - 4.5 V VIN - 0.4 V
5.5 V on Other Inputs
Inputs HIGH
Inputs HIGH
(4-lnput Gate Only)
Inputs LOW
Inputs LOW
(4-lnput Gate Only)
CL = 15 pF
Fig. 3-4

9XXX Series
CONNECTION DIAGRAM
PINOUT A

9024
DUAL JK (OR D) FLIP-FLOP

-

~OlIT

i1!l

illi~o

Kl[!

:EJ J
Eli

CP1[!

11

:fficp

Ql[!

TIl So

501

DESCRIPTION - The 9024 consists of two high speed, clocked JK flipflops. The Ciocking operation is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together.

I!

~Q

GNDI!

]]0

"01

ORDERING CODE: See Section 9
PIN
PKGS

OUT

LOGIC SYMBOL

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

5

PKG
TYPE

Ceramic
DIP (D)

A

9024DC

9024DM

68

Flatpak
(F)

A

9024FC

9024FM

4L

b
SOl

2 - Jl

Ql

Kl

COl

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions

SYNCHRONOUS ENTRY
J-K MODE OPERATION
INPUTS
@ tn

OUTPUTS
@ tn + 1

J

K

Q

L
L
H
H

H
L
H
L

No Change
L
H
H
L
Toggles

Q

Q r--10

1 2 - CP

1.5/1.0
3.0/2.0
6.0/3.0
30/8.8
(7.8)

Clock, So Inputs
Co Input
Outputs

b
So

14- J

9XXX (U.L.)
HIGH/LOW

~7

9

1
11

J, K Inputs

Ql r - - 6

4 - CPl
3~

PINS

Vee

Jl[!

13~K

Co

9

15

SYNCHRONOUS ENTRY
D MODE OPERATION
INPUTS
@ tn

OUTPUTS
@ tn + 1

D

Q

Q

L
H

L
H

H
L

H = HIGH Voltage Level
L = LOW Voltage Level
tn, tn+1 = time before and

after rising edge of CPo

5-24

QP-9

Vcc = Pin 16
GND = Pin 8

ASYNCHRONOUS ENTRY
INDEPENDENT OF CLOCK &
SYNCHRONOUS INPUTS
INPUTS

OUTPUTS

So CD
Q
Q
5(11) 1(15) 6(10) 7(9)
L
L
H
H

L
H
L
H

H
H
H
L
L
H
No Change

9XXX Series
DC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee
SYMBOL

PARAMETER

GOC

25°C

75°C

= +5.0 V ±5%
UNITS

CONDITIONS

Min Max Min Max Min Max
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOL

Output LOW Voltage

1.9

1.8
0.85

0.45

1.6
0.85

0.85

0.45

0.45

SO
120
240

SO
120
240

-1.6
-3.2
-4.8
-1.41
-2.82
-4.23

-1.6
-3.2
-4.8
-1.41
-2.82
-4.23

V

Guaranteed Input
HIGH Threshold

V

Guaranteed Input
LOW Threshold

V

Vee = 4.75 V,
10L = 14.1 rnA
Vee = 5.25 V,
10L = 1S rnA

Input HIGH Current
hH

J,

K

Clock Input,
CD

So

p.A

Vee = 5.25 V, VIN =4.5 V
Gnd on Other Inputs

rnA

Vee = 5.25 V, VIN =.45 V
4.5 V on Other Inputs

rnA

Vee = 4.75 V, VIN = .45 V
4.5 V on Other Inputs

rnA

Vee = 5.25 V,
VOUT = 0 V

rnA

Per Flip-Flop in
Worst Logic State

Input LOW Current

J,K
hL

Clock Input,
CD'

So

J, K
Clock Input,
CD'

So

los

Output Short Circuit Current

lee

Power Supply Current

-1.S
-3.2
-4.8
-1.41
-2.82
-4.23

-30 -100 -30 -100 -30 -100
14

'Denotes maximum current under normal operation. These currents may Increase up to 4 IlL if J.

5-25

K

= HIGH and So = LOW.

•

9XXX Series
DC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee
-55°C

PARAMETER

SYMBOL

25°C

= +5.0 ±10%

125°C

UNITS

CONDITIONS

Min Max Min Max Min Max
V

Guaranteed Input
HIGH Threshold

0.8

V

Guaranteed Input
LOW Threshold

0.4

0.4

V

Vee = 4.5 V,
10L = 12.4 mA
Vee - 5.5 V,
10L = 16 mA

60
120
240

120
240

-1.6
-3.2
-4.8
-1.24
-2.48
-3.72

-1.6
"3.2
-4.8
-1.24
-2.48
-3.72

1.7

2.0

1.4

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

0.9

Output LOW Voltage

0.4

VOL

Input HIGH Current
hH

J,K
Clock Input, So

CD

60

J.lA

Vee = 5.5 V, VIN = 4.5 V·
Gnd on Other Inputs

mA

Vee = 5.5 V, VIN = 0.4 V
4.5 V on Other Inputs

mA

Vee = 4.5 V, VIN = 0.4 V
4.5 V on Other Inputs

mA

Vee = 5.5 V,
VOUT = 0 V

mA

Per Flip-Flop in
Worst Logic State

Input LOW Current

J,K
ilL

-1.6
-3.2
-4.8
-1.24
-2.48
-3.72

Clock Input, So
CD (Note 4)
J, K
Clock Input, So
~o·

los

Output Short Circuit Current

Icc

Power Supply Current

-30

-100 -30

-100 -30
14

"Denotes maximum current under normal operation. These currents may increase up to

SWITCHING CHARACTERISTICS: TA
SYMBOL

-100

= 25°C,

Vee

9XXX
Min

Propagation Delay
CP to Q or Q

th (H)
th (U

J, Kto CP

ts (H)
ts(U

Setup Time HIGH or LOW
J, "Kto CP

tPLH

Hold Time HIGH or LOW

if J,

K=

HIGH and So =

LOW.

= +5.0 V, CL = 15 pF

PARAMETER

tPLH
tpHL

4 hL

UNITS

TEST CONDITIONS

Max
20
33

0

ns

Figs. 3-1, 3-8

ns
Figs. 3-1, 3-6

20

1.0

ns

Propagation Delay
SD to Q, CD to C

12

ns

tPHL

Propagation Delay
So to C, CD to Q

25

fmax

Maximum Toggle Frequency

Figs. 3-1, 3-16

25

ns
MHz

5-26

Figs. 3-1, 3-8

00
CONNECTION DIAGRAM
PINOUT A

9300
93HOO
93LOO
93500

-

MRII

~vcc

rm

J[I

PorI

4-BIT UNIVERSAL SHIFT REGISTER
DESCRIPTION - The '00 is a 4-bit universal shift register. As a high speed
multifunctional sequential logic block, it is useful in a wide variety of register
and counter applications. It may be used in serial-serial, shift left, shift right,
serial-parallel, parallel-serial, and parallel-parallel data register transfers.

oo

~01
~02

i[I
P1[I

1m 03

P2[!

~Q3

P3[I

rm cp
~PE

GNO[[

LOGIC SYMBOL
• ASYNCHRONOUS MASTER RESET
• J, K INPUTS TO FIRST STAGE

1iii r

ORDERING CODE: See Section 9

PE Po P1 P2 P3

2-

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

9300PC, 93HOOPC
93LOOPC, 93S00PC

Ceramic
DIP (0)

A

9300DC, 93HOODC
93LOODC, 93S00DC

9300DM, 93HOODM
93LOODM, 93S00DM

68

Flatpak
(F)

A

9300FC, 93HOOFC
93LOOFC, 93S00FC

9300FM, 93HOOFM
93LOOFM, 93S00FM

4L

98

J
cp .

103---(1 K

03

MR 0001

P--11

0203

! 1~ 1~ )3 )2
Vcc

= Pin 16
= Pin 8

GND

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
PE
PO-P3
J

K
CP

-MR
00-03

ci3

93XX (U.l.)
HIGH/LOW

93H (U.l.)
HIGH/LOW

93l (U.l.)
HIGH/LOW

93S (U.L.)
HIGH/LOW

Parallel Enable Input
(Active LOW)
Parallel Inputs
First Stage J Input
(Active HIGH)
First Stage K Input
(Active LOW)
Clock Pulse Input
(Active Rising Edge)
Master Reset Input
Parallel Outputs

2.3/2.3

1.0/1.0

1.15/0.575

1.25/1.25

1.0/1.0
1.0/1.0

1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25

1.011.0
1.0/1.0

1.0/1.0

1.0/1.0

0.5/0.25

1.0/1.0

2.0/2.0

2.0/2.0

1.0/0.5

2.5/2.5

1.0/1.0
12/6.0

1.0/1.0
16/8.0

1.25/1.25
25/12.5

Complementary Last
Stage Output

16/8.0

20/10

0.5/0.25
10/5.0
(3.0)
10/5.0
(3.0)

DESCRIPTION

6-3

25/12.5

I

00
LOGIC DIAGRAMS

'00, 'HOO, 'LOO

c.--~-C)o--~------~------~----~--------'-----+-----+-------~r---~~----~------~

03
K-I--I--r"_

MR-------------------+-----+----------------+---4---------------~~--+_---------------J
00

'500

PE

J

Po

.,

"

6-4

P3

c.

MR

00
FUNCTIONAL DESCRIPTION - The Logic Diagrams and Truth Table indicate the functional characteristics of
the '00 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It
performs serial, parallel, serial-to-parallel, or parallel-to-serial data transfers.
The '00 has two primary modes of operation, shift right (00..-01)and parallel load, which are controlled by the
state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop 00 via the J
and K inputs and is shifted one bit in the direction 00"-01"-02 "03 following each LOW-to-HIGH clock
transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple Dtype input for general applications by tying the two pins together. When the PE input is LOW, the '00 appears as
four common clocked D flip-flops. The data on the parallel inputs Po - P3 is transferred to the respective 0003 outputs following the LOW-to-HIGH clock transition. Shift left operation (03. .02) can be achieved bytying
the On outputs to the Pn-1 inputs and holding the PE input LOW.
All serial and parallel data transfers are synch ronous, occuring after each LOW-to-H I GH clock transition. Since
the '00 utilizes edge triggering, there is no restriction on the activity of the J,
Pn and PE inputs for logic
operation - except for the setup and release time requirements. A LOW on the asynchronous Master Reset
(MR) input sets all 0 outputs LOW, independent of any other input condition.

K.

•

TRUTH TABLE
OPERATING
MODE

INPUTS (MR

= H)

OUTPUTS @ tn + 1

PE J

K

Po

P1

P2

P3

00 01

H
H
H
H

L
L
H
H

L
H
L
H

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

L
00

PARALLEL
L
ENTRY MODE L

X
X

X
X

L
H

L
H

L
H

L
H

SHIFT MODE

..

·tn + 1 = Indicates state after next LOW-to-HIGH clOCk transition.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

6-5

02

00 01
00 01

03

03

H

Qo 01
Qo 01

02 02
02 02
02 ~
02 02

L
H

L
H

L
H

00

L
H

H
L

00
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

los

Output Short
Circuit Current

lee

Power SUPPIY~
Current
XM

93XX

93H

93l

Min

Max

Min

Max

-20

-80

-30

-100

Min

112
102

92
86

93S

Max

UNITS

CONDITIONS

Max

Min

23

120

mA

Vee = Max,
Vour = 0 V

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25° C )See Section 3 for waveforms and load configurations)
93XX
SYMBOL

PARAMETER

93H

93l

93S

CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF
Min

Max

Min

Max

Min

Max

f max

Maximum Shift
Frequency

tPLH
tPHL

Propagation Delay
CP to On

22
26

16
21

35
51

tPHL

Propagation Delay
MR to On

40

28

60

30

45

10

Min

UNITS

CONDITIONS

Max

70

MHz

Figs. 3-1, 3-8

8.5
12

ns

Figs. 3-1, 3-8

23

ns

Figs. 3-1, 3-17

UNITS

CONDITIONS

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

93XX
Min

Max

93H
Min

Max

93l
Min

Max

93S
Min

Max

Setup Time..tIlGH
or LOW, J, K and
Po- P3 to CP

20
20

th (H)
th (U

Hold Time HIGH
or LOW, J, K and
Po- P3 to CP

0
0

0
0

0
0

0
0

ns

ts (H)
ts (U

Setup Ti~HIGH
or LOW, PE to CP

39
39

15
15

68
68

8.0
8.0

ns

th (H)
th (U

Hold Time HIGH
or LOW, PE to CP

-10
-10

0
0

-20
-20

0
0

ns

tw (H)
tw (U

CP Pulse Width
HIGH or LOW

17
17

12
12

38
38

7.0
7.0

ns

tw (U

MR Pulse
Width LOW

25

19

53

12

ns

tree

Recovery Ti me
MR to CP

25

7.0

70

5.0

ns

ts (H)
ts (U

12
12

60
60

6.0
6.0

ns
Fig. 3-6

Fig. 3-6

Fig. 3-8

Fig. 3-16

6-6

01
CONNECTION DIAGRAM
PINOUT A

9301
93L01
1-0F-10 DECODER

-

Ad:!

~vcc
~AO

As@:
05

[!

Os

G:

rm

08 [!

till 0,
till 02

IT

~03

GNOI!

1]0.

Od:~

09

DESCRIPTION - The '01 multipurpose decoders are designed to accept four
inputs and provide ten mutually exclusive outputs.

•
•
•
•

MULTIFUNCTION CAPABILITY
MUTUALLY EXCLUSIVE OUTPUTS
DEMUL TIPLEXING CAPABILITY
TYPICAL POWER DISSIPATION OF 145 mW for '01, 45mW for'L01

A1

~OO

•

LOGIC SYMBOL

Y
Ao

y
A1

2

1
A2

I
A3

ORDERING CODE: See section 9
00 01 02 03 O. 05 Os 0; 08 o.

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9301 PC, 93L01 PC

Ceramic
DIP (0)

A

9301 DC, 93L01 DC

9301DM, 93L01 OM

68

Flatpak
(F)

A

9301 FC, 93L01 FC

9301 FM, 93L01 FM

4L

98

!X~!!r!!r1
Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

AcJ-A3

Bo-Os

DESCRIPTION
Address Inputs
Decoder Outputs (Active LOW)

6-7

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

1.0/1.0
20/10

0.5/0.25
10/5.0
(3.0>

01
FUNCTIONAL DESCRIPTION - The '01 decoder accepts four active HIGH BCD inputs and provides ten
mutually exclusive active LOW outputs, as shown by logic symbol or diagram. The active LOW outputs
facilitate addressing other MSI units with active LOW input.enables. The logic design of the '01 ensures
that all outputs are HIGH when binary codes greater than nine are applied to the inputs. The most significant
input A3 produces a useful inhibit function when the '01 is used as a 1-of-8 decoder.
TRUTH TABLE
INPUTS

OUTPUTS

Ao

A1

A2.

A3

00 01

02 03 04 Os Os 07 08

Qg

L
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H,
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

L
H
L
H

L
L
H
H

H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

Ao

t
y
I

I

lt9
00

01

6-8

01
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER

Min

Icc

SYMBOL

= +5.0 V,

TA

93XX

PARAMETER

= 15 pF

Min
Propagation Delay
An to On

UNITS

CONDITIONS

Max
13

rnA

Vee

= +25°C (See Section 3 for waveforms and
CL

tPLH
jpHL

Min

44

Power Supply Current

AC CHARACTERISTICS: Vee

Max

93l

Max
35
30

93l

UNITS

= Max

load configurations)
CONDITIONS

CL = 15 pF
Min

Max
36
36

ns

Figs. 3-1, 3-20

•

6-9

02
CONNECTION DIAGRAM
PINOUT A

9302
1-0F-10 DECODER
(With Open-Collector Outputs)

-

AdI

""II

lilAc

[1

:mAl

05

as I!
ad}

TIl 00

• OUTPUTS HAVE WIRED-OR CAPABILITY
• PROVIDES CAPABILITY TO GENERATE AND SUM
MINTERMS OF 3 OR 4 VARIABLES
• ACTIVE LOW OUTPUTS ARE USEFUL FOR DRIVING
LOW VOLTAGE LAMPS AND RELAYS
• MULTIFUNCTION CAPABILITY
• MUTUALLY EXCLUSIVE OUTPUTS
• DEMULTIPLEXING CAPABILITY
• TYPICAL POWER DISSIPATION OF 145 mW

ma,

IT

TIl 02

0912

~03

GNO!I

]]04

08

DESCRIPTION - The '02 is a multipurpose decoder designed to accept four
inputs and provide ten mutually exclusive outputs. The open-collector outputs provide wired-OR capability which can be used for numerous summing,
decoding and demultiplexing operations.

:ill Vee

LOGIC SYMBOL

15

14

I

I

AD

Al

i

1
A2

A3

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9302PC

Ceramic
DIP (0)

A

9302DC

9302DM

66

Flatpak
(F)

A

9302FC

9302FM

4L

96

00 0, 02 03 04 05

Os

0, 08 09

YYYYYYYy Yy

13 12 11 10 9

3

4

5

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-A3

Co-Os
'oe -

DESCRIPTION
Address Inputs
Decoder Outputs (Active LOW)

93XX (U.L.)
HIGH/LOW
1.0/1.0
OC*/10

Open Collector

6-10

6

7

02
FUNCTIONAL DESCRIPTION - The '02 decoder accepts four active HIGH BCD inputs and provides ten
mutually exclusive active LOW outputs, as shown by the logic symbol. The open-collector outputs provide easy
summing of input terms. The '02 provides the capability in one package to generate and sum any or all of the
minterms of three variables, or the first 10-or-16 minterms of four variables. The logic design of the '02 ensures
that all outputs are HI GH when binary codes greater than nine are applied to the inputs. The most significant
input (Al) produces a useful inhibit function when the '02 is used as a 1-of-8 decoder.
TRUTH TABLE
INPUTS

OUTPUTS

Ao

A1

A2

A3

00

01

02

03

04

05

06

07

08

09

L
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC DIAGRAM

6-11

02
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER
Min

leEx

Output HIGH Leakage Current

lee

Power Supply Current

UNITS

CONDITIONS

250

p.A

Vee = Min, VeEx = 5.5 V
VIN = VIH or VIL per
Truth Table

44

mA

Vee = Max

Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
93XX

SYMBOL

PARAMETER

CL = 15 pF
RL = 400 n
Min

tPLH
tPHL

Propagation Delay
An to On

CONDITIONS

Max
35
30

6-12

UNITS

ns

Figs. 3-2, 3-20

04
CONNECTION DIAGRAM
PINOUT A

9304

BrI

~Al

!:mBl

'ColI

~CI

iII

~co
~s

sIT

PKGS

OUT

Vee = +5.0 V ±5%,
TA = O°C to +70°C

MILITARY GRADE
Vee = +5.0 V ±10 %,
TA = -55°C to +125°C

~so

GNOII

LOGIC SYMBOL

i i1

ORDERING CODE: See Section 9
COMMERCIAL GRADE

~B2

cii

MULTIFUNCTION CAPABILITY
8.0 ns CARRY PROPAGATION DELAY
COMPLEMENTARY INPUTS AND OUTPUTS AVAILABLE
TYPICAL POWER DISSIPATION OF 150 mW

PIN

~vcc

AlI

DESCRIPTION - The '04 consists of two independent, binary full adders. The
adders are useful in a wide variety of applications including multiple bit parallei add/serial carry addition, parity generation and checking, code conversion
and majority gating.
•
•
•
•

-

A20::

DUAL FULL ADDER

C

B

A

I8~
2 1

2 1

B

A

C

PKG
FULL ADDER 1

TYPE

Plastic
DIP(P)

A

9304PC

Ceramic
DIP (D)

A

9304DC

9404DM

6B

Flatpak
(F)

A

9304FC

9304FM

4L

9B

s

s

!!

Co

r

FULL ADDER 2

S

}o

!L

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Full Adder 1
A, B
C,
S

S
Co
Full Adder 2
A1, B1

A2,B2
C,
S

S
Co

DESCRIPTION

93XX (U.L.)
HIGH/LOW

Operand Inputs
Carry Input
Sum Output
Complementary Sum Output
Carry Output (Active LOW)

4.0/4.0
4.0/4.0
20/10
20/10

OR Operand Inputs (Active HIGH)
OR Operand Inputs (Active LOW)
Carry Input (Active LOW)
Sum Output
Complementary Sum Output
Carry Output (Active HIGH)

1.0/1.0
4.0/4.0
4.0/4.0
20/10
20/10

1417.0

1417.0

..

6-13

Co

S

•

04
FUNCTIONAL DESCRIPTION - The '04 logic block consists of two separate high speed carry dependent sum
full adders. This design allows a minimum carry propagation time when the adders are used in ripple carry
applications. The adders are identical except that adder 2 has provision for either active HIGH or active LOW
inputs at the A and B terminals. The adders produce a LOW carry and both LOW and HIGH sum with active
HIGH inputs, a HIGH carry and both HIGH and LOW sum when active LOW inputs are used. This principle of
duality is shown in the diagram below, where the adders are drawn as functional blocks.

TRUTH TABLES
ADDER 1
INPUTS

ADDER 2

OUTPUTS

INPUTS

OUTPUTS

CI

B

A

Co S

S

CI

B1

A1

B2

A2

Co S

S

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
L

H
L
L
H

L
H
H
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
L

H
L
L
H

L
H
H
L

H
H
H
H

L
L
H
H

L
H
L
H

H
L
L
L

L
H
H
L

H
L
L
H

L
L
L
L

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

H
H
L
L

L
L
H
H

L
L
L
L

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

H
L
H
L

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

H
L
L
L

L
H
H
L

H
L
L
H

H
H
H
H

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

H
H
L
L

L
L
H
H

H
H
L
L

H
H
H
H

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

H
L
H
L

L
H
L
H

H
L
H
L

H
H
H
H

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

L
L
L
L

H
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level

ACTIVE LOW

ACTIVE HIGH

6-14

04
LOGIC DIAGRAM

ADDER 1

~

A
B
CI

o--s

-

5

CO

ADDER 2

A1

}-

to.

....

--

A2
B1-t>

82

0-5
'---'

H

CI

-

--

-

--i..-.

s

Co

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER

Ise

Output Short Circuit Current

lee

Power Supply Current

AC CHARACTERISTICS: Vee = +5.0 V,

TA

UNITS

CONDITIONS

Min

Max

-20

-70

mA

Vee = Max, VOUT = 0 V

55

mA

Vee =Max, Pins 13 & 14=0 V

= +25°C (See Section 3 for waveforms and load configurations)
93XX

SYMBOL

PARAMETER

CL = 15 pF
Min

UNITS

CONDITIONS

Max

tPLH
tpHL

Propagation Delay
An to S

36
35

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
CI to Co

13
13

ns

Figs. 3-1, 3-4

6-15

•

05
CONNECTION DIAGRAM
PINOUT A

9305
VARIABLE MODULUS COUNTER
DESCRIPTION - The 'OS is a monolithic, high speed, variable modulus
counter circuit. It is a semisynchronous counter which can be programmed
without extra logic to provide division or counting by either 2 and 4, S, 6, 7, 8
or 10, 12, 14, 16. A binary count sequence can be obtained for all of the preceding counter modulos as well as SO% duty cycle output for dividers of 8,10,
12, 14, 16. The device also features asynchronous overriding Master Reset
and Set inputs and the negation output of the final flip-flop output which allows the cascading of stages.
• VARIOUS BINARY COUNTING MODES
MODULO 2 AND MODULO 5, 6, 7, 8
MODULO 10 (8421 BCD) 12, 14, 16
• VARIOUS DIVISION MODES WITH 50% DUTY CYCLE OUTPUT
MODULO 8,10,12,14,16
• LOGIC SELECTION OF COUNTING MODE
• ASYNCHRONOUS MASTER RESET ANS SET INPUTS
• MULTISTAGE COUNTING OPERATION

PKGS

OUT

C3[I

TIJMR

IT

~oo

SlIT

:!!lOa

03 [I
0, [I

TIl CPa

So

:IjOl
}]CPl

GNOIT

LOGIC SYMBOL

1

3

4

b I S,I
MS
So

ORDERING CODE: See Section 9
PIN

:!il Vee

~

MSU

1 0 - CPo

COMMERCIAL GRADE

MILITARY GRADE

Vee = +S.O V ±S%,
TA = O°C to +70°C

Vee = +S.O V ±10%,
TA = -SsoC to +12SoC

03

PKG
TYPE

Plastic
DIP(P)

A

930SPC

Ceramic
DIP (D)

A

930SDC

930SDM

6A

Flatpak
(F)

A

930SFC

930SFM

38

8 - CP,

MR 00 00 Q1 Q2 Q3

! L'2 ! ! !

9A
vce = Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
So, Sl
CPo
CP1
MS
MR
00
00
01-03
03

DESCRIPTION
Select Inputs
First Stage Clock Pulse Input (Active Rising Edge)
Three Stage Clock Pulse Input (Active Rising Edge)
Master Set Input (Active LOW)
Master Reset Input (Active LOW)
First Stage Output
Complementary First Stage Output
Three Stage Counter Outputs
Complementary Last Stage Output

6-16

93XX (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
16/8.0
16/8.0
16/8.0
20/10

0--2

05
FUNCTIONAL DESCRIPTION - The '05 consists of four master/slave flip-flops which are separated into two
functional units - a single toggle stage and a three stage synchronous counter. All four fli p-fli ps change state
on the LOW-to-HIGH transition of the clock. The three stage counter can be programmed with external
connections to provide moduli of either 5, 6, 7 or 8. This basic configuration allows synchronous binary
counting by the last three stages and independent modulo 2 operation with the first single stage.
A four stage binary counter with a modulo of 10,12, 14 or 16 is obtained by applying the incoming clock to the
single toggle stage and feeding its negation output to the clock input of the three stage counter. A 4-stage
divider with 50% duty cycle outpu.!..is produced by feeding the incoming clock to the three stage counter and
clocking the single stage with the 03 output. In either the binary or 50%division mode the modulo(10, 12, 14, 16)
is determined by the external programming connections for the three stage counter. These 4-stage counters or
dividers are not fully synchronous (semisynchronous) but have only one flip-flop ripple delay in either
configuration. Counter moduli other than 10, 12, 14, 16 can be formed with a few extra gates.

Several '05 variable modulus counters programmed in any modulo can be connected together without extra
logic to form asynchronous (ripple) type multistage counters. This is done by connecting the 03 output of the
less significant counter to the clock input of the following counter.
The Master Set and Reset will asynchronously set or reset all four stages when activated. The active LOW Reset
input when LOW will clear the counter, overriding the clock and forcing the outputs 00 - 03 LOW and outputs
Qo, Q3 HIGH. The active LOW Set input when LOW will preset the counter, overriding the clock and forcing the
outputs 00 - 03 HIGH and outputs Qo, 03 LOW. The master set provides a synchronous clear, since the first
clock pulse following the asynchronous master set will reset all stages. This action is independent of the molulo
programmed.

LOGIC DIAGRAM

So-----.....

s,

~-~---~---~~--~-------r_--_,

SD

cPo
CD

0

OP+---0,

00 00

6-17

05
COUNTING MODE
The following are rules specifying the external connections required for various counter and divider modulos.

ASYNCHRONOUS MODE
INPUTS

OUTPUTS

MSMR Co Co

01

L H
H L
H H

H L
H
H L
L
COUNT'

02

03 03

H
L

H
L

L
H

-As determined by programming connections.
H = HIGH Voltage Level
L = LOW Voltage Level

PROGRAMMING CONNECTIONS
FOR LAST THREE STAGES

So Sl

MODULO

NCNC
01 NC
NCOl

5
6
6

02 NC
NC02
0102
0201

7
7

CONNECTIONS FOR MODULO
10,12,14,16 BINARY COUNTERS
AND 50% DUTY CYCLE DIVIDERS
For~inary

Counting

00 connected to CPl
Incoming clock to CPo
For 50% Duty Cycle Output
'03 connected to CPo
Incoming Clock to CPl

8
8

NC = Not Connected

ALTERNATE PROGRAMMING CONNECTIONS
FOR LAST THREE STAGES··
MODULO INPUTS OUTPUT

So Sl
5
6
7
8
8

Oa 03

Oa

01 01
02 02
01 02
02 01

01
02

02
01

AVAILABLE
OUTPUT
FAN-OUT
14/8.0
1417.0
1417.0
1517.0
1517.0

--The alternate programming connections program the counter
and conveniently terminate unused select inputs (NC). Since
these inputs form the inputs to a single NAND gate (See logic
diagram), their connection to the counter outputs for the various count modulos provides the indicated output drive.

6-18

05
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
93XX

PARAMETER

SYMBOL
Ise

Output Short Circuit Current

lee

Power Supply Current

AC CHARACTERISTICS: Vee = +5.0 V, TA

UNITS

CONDITIONS

Min

Max

-20

-70

mA

Vee = Max, VOUT = 0 V

66

mA

Vee

= +25°C (See

= Max

Section 3 for waveforms and load configurations)

93XX

PARAMETER

SYMBOL

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

f max

Maximum Count Frequency

tpLH
tPHL

Propagation Delay
CPo to Cb (Modulo 16 Connection)

38
48

ns

tPLH
tPHL

Propagation Delay
CPo to 00

21
30

ns

Modulo-16
Figs. 3-1, 3-8

tPLH
tPHL

Propagation Delay
CP1 to cb or 03

23
30

ns

Modulo-8
Figs. 3-1, 3-8

tPLH

Propagation Delay
MS to Q1

26

ns

Modulo-8
Figs. 3-1, 3-16

tPHL

Propagation Delay
MR to Q1

35

ns

Modulo-8
Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee

23

= +5.0 V,

Modulo 16 (So to Q1, S1 to
Q2,QotoCP1,lnputtoCPo)
Figs. 3-1, 3-8

TA = +25°C
93XX

PARAMETER

SYMBOL

MHz

Min

UNITS

CONDITIONS

Max

22

ns

Fig. 3-8

24

ns

Fig. 3-16

Recovery Time
MS to CP1

25

ns

Fig. 3-16

Recovery Time
MR to CP1

30

ns

Fig. 3-16

tw

CPo Pulse Width

tw

MR or

tree
tree

MS Pulse Width

6-19

07
CONNECTION DIAGRAM
PINOUT A

9307

-

A,[I

7-SEGMENT DECODER

llivcc

A~II

ll)f

J:TII

Elg

1fiO[!

m-

RBi~

E]b

Aaii

TIle

AolI

~d

GND!!

}]e

DESCRIPTION - The '07 7-segment decoder Is designed to accept four inputs in 8421 BCD code and provide the appropriate outputs to drive a 7-segment numerical display. The decoder can be used with 7-segment incandescent lamp, neon,electro-Iuminescent, or CRT numeric displays.
LOGIC SYMBOL
• AUTOMATIC RIPPLE BLANKING FOR SUPPRESSION
OF LEADING-EDGE ZEROES
• LAMP INTENSITY MODULATION CAPABILITY
• LAMP TEST FACILITY
• BLANKING INPUT
• ACTIVE HIGH OUTPUTS

7

1

6

2

3

5

I A,I A2I AaI ! !

Ao

LT RBI

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

a

PKG
TYPE

bed

A

9307PC

Ceramic
DIP (D)

A

9307DC

9307DM

6B

Flatpak
(F)

A

9307FC

9307FM

4L

9B

f 9

= Pin 16
= Pin 8

GND

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-Aa

RBT
IT
RBO
a-g

DESCRIPTION
BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Ripple Blanking Output (Active LOW)
Segment Outputs (Active HIGH)

6-20

RBO

IIIIIII Y

13 12 11 10 9 15 14

Vcc

Plastic
DIP(P)

e

93XX (U.L.)

HIGH/LOW
0.25/1.0
0.25/0.5
1.25/4.0
1.75/1.5
0/6.25

4

07
FUNCTIONAL DESCRIPTION - The '07 7-segment decoder accepts a 4-bit BCD 8421 code input and
produces the appropriate outputs for selection of segments in a 7-segment matrix display used for representing
the decimal numbers 0-9. The seven outputs (a, b, c, d, e, f, g) of the decoder select the corresponding segments
in the matrix shown in Figure a. The numeric designations chosen to represent the decimal numbers are shown
in Figure b, together with the resulting displays for input code configurations in excess of binary nine.
The decoder has active HIGH outputs so that a buffer transistor may be used directly to provide the high
currents required for incandescent displays. If additional base drive current is required external resistors may
be added from the supply voltage to the seven segment outputs of the decoders. If additional base drive current
is required external resistors may be added from the supply voltage to the seven segment outputs of the
decoders. The value of this resistor is constrained by the 10 mA current sinking capability of the output
transistors of the circuit.
The device has provision for automatic blanking of the leading and/or trailing-edge zeroes in a multi digit
decimal number, resulting in an easily readable decimal display conforming to normal writing practice. In an
eight digit mixed integer fraction decimal representation, using the automatic blanking capability, 0060.0300
would be displayed as 60.03. Leading-edge zero suppression is obtained by connecting the Ripple Blanking
Output (RBO) of a decoder to the Ripple Blanking Input (RBU of the next lower stage device. The most
significant decoder stage should have the RBI input grounded; and, since suppression of the least significant
integer zero in a number is not usually desired, the RBI inputof this decoder stage should be left open. Asimilar
procedure for the fractional part of a display will provide automatic suppression of trailing-edge zeroes .
The decoder has an active LOW input Lamp Test which overrides all other input combinations and enables a
check to be made on 'possible display malfunctions. The RBO terminal of the decoder can be OR-tied with a
modulating signal viaan isolating buffer to achieve pulse duration intensity modulation. Asuitablesignal can be
generated for this purpose by forming a variable frequency multivibrator with a cross coupled pair of TTL gates.
LOGIC DIAGRAM
[f

A3

1

I

RBO

I

I

I

Ll

c

d

6-21

9

•

07
TRUTH TABLE

INPUTS

OUTPUTS

LT

RBI

Ao

A1

A2

A3

a

b

c

d

e

f

9

RBO

L
H
H
H

X
L
H
X

X
L
L
H

X
L
L
L

X
L
L
L

X
L
L
L

H
L
H
L

H
L
H
H

H
L
H
H

H
L
H
L

H
L
H
L

H
L
H
L

H
L
L
L

H
L
H
H

0
0
1

H
H
H
H

X
X
X
X

L
H
L
H

H
H
L
L

L
L
H
H

L
L
L
L

H
H
L
H

H
H
H
L

L
H
H
H

H
H
L
H

H
L
L
L

L
L
L
H

H
H
H
H

H
H
H
H

2
3
4
5

H
H
H
H
H

X
X
X
X
X

L
H
L
H
L

H
H
L
L
H

H
H
L
L
L

L
L
H
H
H

H
H
H
H
L

L
H
H
H
L

H
H
H
H
L

H
L
H
H
H

H
L
H
L
H

H
L
H
H
L

H
L
H
H
H

H
H
H
H
H

10

H
H
H
H
H

L
L
H
L
L

L
H
L
L
L

L
H
H
L
L

H
L
H
H
L

L
L
L
H
L

L
H
H
H
L

H
H
H
H
L

H
H
H
H
H

11
12
13
14
15

H
H
H
H
H

X
X
X
X
X

H
L
H
L
H

H
L
L
H
H

L
H
H
H
H

6
7

8
9

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

a

fLJb
el

Ie

-d-

Fig. a Segment Designation

0

I-I
I- I

1

2

3

4

5

6

7

8

9

-,

10

I -I -I I I I- I- -I I-I I-I
, I-I I 1-I
-I I-I
I 1Fig. b

Numerical Designations

6-22

11

-

12

13

14

I I I- I
, -I 1
-

-

15

07
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER
Min

VOH

VOL

Output HIGH
Voltage

Output LOW
Voltage

at a-g
at ABO

XM

XC

at a-g

~
XC

at ABO

~
XC

at a-g

~
XC

at ABO

UNITS

4.3

V

3.0
2.7

V
0.4
0.45
0.4
0.45
0.4
0.45
0.4
0.45

XM

XC

V
V

= 10 mA

V

10L

= 2.4 mA

los

Output Short Circuit
Current at a - g

~
XC

-3.7
-4.0

mA

lee

Power Supply Current

~
XC

73
82

mA

TA

= Max

Vee

~
XC

= +5.0 V,

10L = 12.5 mA
10L = 11.5 mA
ee
10L - 3.1 mA
10L - 2.75 mA
10L

Available Output
Current at a - g

-1.0
-1.1

Vee = Min
10H = 0 mA
Vee = Min
10H = -70 p.A

V

IA

AC CHARACTERISTICS: Vee

CONDITIONS

Max

mA

= 0.85 V Vee = Min
= 0.75 V TA = Max
Vee = Max, TA = +25°C
VOUT = 0 V
VOUT
VOUT

Vee

= +25°C (See Section 3 for waveforms and

= Max

load configurations)

93XX

SYMBOL

PARAMETER

CL

= 30 pF

Min
tPLH
tpHL

Propagation Delay
Ao-A3 or ABI to a-g or

6-23

CONDITIONS

Max
750
750

ABO

UNITS

ns

= Min

Fig. 3-20

•

08
CONNECTION DIAGRAM
PINOUT A

9308
93108
DUAL 4-BIT LATCH
DESCRIPTION ~ The '08 is a dual 4-bit D-type latch designed for general
purpose storage applications in digital systems. Each latch contains both an
active LOW Master Reset input an active LOW Enable inputs. The 54174116
is a pin for pin equivalent of the 9308.

ORDERING CODE: See Section 9

PKGS

COMMERCIAL GRADE
MILITARY GRADE
PIN ~----------------~----------------~PKG
Vee = +5.0 V ±5%,
Vee = +5.0 V ±10%,
TYPE
OUT
TA = -55°C to +125°C
TA = O°C to +70°C

Plastic
DIP (P)

A

9308PC, 93L08PC

Ceramic
DIP(D)

A

9308DC, 93L08DC

9308DM, 93L08DM

6N

Flatpak
(F)

A

9308FC, 93L08FC

9308FM, 93L08FM

4M

9N

INPUT lOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

Doa- D3a}
Parallel Latch Inputs
DOb-D3b
Eoa, E1a, EOb, E1b AND Enable Inputs (Active LOW)
Master Reset Inputs (Active LOW)
MRa, MRb
QOa-Q3a}
Parallel Latch Outputs
QOb-Q3b

93XX (U.l.)
HIGH/LOW

93l (U.L.)
HIGH/LOW

1.5/1.5

0.75/0.375

1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25

20/10

10/5.0
(3.0)

lOGIC SYMBOL
2

3

Eo

4

6

8 10

14 15 16 18 20 22

E1

E

Do 0, 02 03

E

4-BIT LATCH 1

4-BIT LATCH 2

MR 00 0, 02 03

1

5

7

9

Do 0, 02 03

MR 00 0, 02 03

11

13 17 19 21 23

6-24

Vcc = Pin 24
GND = Pin 12

08
FUNCTIONAL DESCRIPTION - Data can be entered into the latch when both of the enable inputs are LOW.
As long as this logic condition exists, the output of the latch will follow the input. If either of the enable inputs
goes HIGH, the data present in the latch at that time is held in the latch and is no longer affected by data input.
The master reset overrides all other input conditions and forces the outputs of all the latches LOWwhen a LOW
signal is applied to the Master Reset input.

TRUTH TABLE
MR

Eo

E1

D

On

H
H
H

L
L
L

L
L
H

L
H
X

L
H
On-1

OPERATION
Data Entry
Data Entry
Hold

H
H
L

H
H
X

L
H
X

X
X
X

On-1
On-1
L

Hold
Hold
Reset

an ~ 1 = Previous Output State
= Present Output State
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Qn

LOGIC DIAGRAM

6-25

•

08
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93)(X

PARAMETER

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

Max

93l

Min

100

TA

29

PARAMETER

CONDITIONS

mA

Vee

= Max

= +25°C (See Section 3 for waveforms and load configurations)
93XX

SYMBOL

UNITS

Max

CL
RL

= 15 pF
= 400 n

Min

Max

93l

= 15 pF

CL

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
En to an

30
22

45
38

ns

Figs. 3-1, 3-8

tPLH
tPHL

Propagation Delay
Dn to an

15
18

27
29

ns

Figs. 3-1, 3-5

tPHL

Propagation Delay
MR to an

22

30

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0 V, TA = +25°C
93XX

Min

ts (H)

Setup Time HIGH, Dn to En

th (H)

Hold Time HIGH, Dn to En

Max

93l

Mil)

UNITS

CONDITIONS

Max

10

8.0

ns

-2.0

0

ns

Fig. 3-13

ts (Ll

Setup Time LOW, Dn to En

12

18

ns

th (Ll

Hold Time LOW, On to En

8.0

4.0

ns

tw (Ll

En Pulse Width LOW

18

30

ns

Fig. 3-21

tw (Ll

MR Pulse Width lOW

18

32

ns

Fig. 3-16

tree

Recovery Time, MR to En

8.0

10

ns

Fig. 3-16

6-26

Fig. 3-13

09
CONNECTION DIAGRAM
PINOUT A

9309
93L09

zblI

DUAL 4-INPUT MULTIPLEXER

Zbl!

DESCRIPTION - The '09 monolithic dual 4-input digital multiplexers consist
of two multiplexing circuits with common input select logic. Each circuit
contains four inputs and fully buffered complementary outputs. In addition
to multiplexer operation, the '09 can generate any two function of three variabies. Active pullups in the outputs ensure high drive and high speed performance. 8ecause or its high speed performance and on-chip select decoding,
the '09 may be cascaded to multiple levels so that any number of lines can be
multiplexed onto a single output bus.

-

5.[!

11!1 Vee
~Za
~z.

lObI:!

I1!J So

hb[!

~Ioa

12b[!

1lil11a

13bII

1m 12a

GND[!

~13a

LOGIC SYMBOL
• MULTIFUNCTION CAPABILITY
• ON-CHIP SELECT LOGIC DECODING
• FULLY BUFFERED COMPLEMENTARY OUTPUTS

YYTiiil1

ORDERING CODE: See Section 9

loa ha 128 ba

lOb hb 12b lab

1 3 - SO

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9309PC, 93L09PC

Ceramic
DIP (D)

A

9309DC, 93L09DC

9309DM, 93L09DM

68

Flatpak
(F)

A

9309FC, 93L09FC

9309FM, 93L09FM

4L

98

3-

5,
Za

Za

!

1~

Zb

r

Zb

!

vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
93XX (U.L)
HIGH/LOW

93L (U.L.)
HIGH/LOW

Za

Common Select Inputs
Multiplexer A Inputs
Multiplexer A Output

1.0/1.0
1.0/1.0
20/10

Za

Complementary Multiplexer A Output

18/9.0

IOb-13b

Zb

Multiplexer 8 Inputs
Multiplexer 8 Output

1.0/1.0
20/10

Zb

Complementary Multiplexer 8 Output

18/9.0

0.5/0.25
0.5/0.25
10/5.0
(3.0)
10/5.0
(3.0)
0.5/0.25
10/5.0
(3.0)
10/5.0
(3.0)

PIN NAMES

So, Sl
IOa-138

DESCRIPTION

6-27

09
FUNCTIONAL DESCRIPTION - The '09 dual4-input multiplexers are able to select two bits of either HIGH or
LOW data or control from up to four sources, in one package. The '09 is the logical implementation of two-pole,
four-position switch, with the position of the switch being set by the logic levels supplied to the two select
inputs. Both assertion and negation outputs are provided for both multiplexers. The logic equations for the
outputs are shown below:

Za = lOa •
Zb = lab •

81 • So + l1a • 81 .- So + 12a • Sl • So + l3a • Sl • So
81 • SO + 11 b • 81 • So + 12b • Sl • So + 13b • Sl • So

The '09 is frequently used to move data from a group of registers to a common output bus. The particular
register from which the data came would be determined by the state of the select inputs. A less obvious
application is as a function generator. The '09 can generate two functions of three variables. This is useful for
implementing random gating functions.

TRUTH TABLE
SELECT
INPUTS

INPUTS (a or b)

OUTPUTS
(a or b)

So

Sl

10

11

12

13

Z

Z

L
L
H
H

L
L
L
L

L
H
X
X

X
X
L
H

X
X
X
X

X
X
X
X

L
H
L
H

H
L
H
L

L
L
H
H

H
H
H
H

X
X
X
X

X
X
X
X

L
H
X
X

X
X
L
H

L
H
L
H

H
L
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

6-28

09
LOGIC DIAGRAM

IDa

So
S1

.....
.....

1

......

1

.....

......
-.....
......
-.....

12a

ha

13a

T

('

lOb

hb

12b

13b

I

1 1
TI
T

~lL J ~ 1 Ill) ~ Ill) I III )

T

~

~

Y

'T

Za Za

Zb Zb

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
PARAMETER

SYMBOL

93XX
Min

los

Output Short Circuit Current

lee

Power Supply Current

Max

93L
Min

UNITS

CONDITIONS

-40

mA

Vee = Max, VOUT = 0 V

11.5

mA

Vee = Max

Max

-10
44

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load definitions)

PARAMETER

SYMBOL

93XX

93L

CL = 15pF

CL = 15pF

Min

Min

Max

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
So to Za

29
27

70
60

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay

So to

21
21

55
50

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
lOa to Za

12
13

40
60

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
lOa to Za

20
21

70
65

ns

Figs. 3-1, 3-5

Za

6-29

10 • 16
CONNECTION DIAGRAM
PINOUT A

9310
93L10
93S10

• 9316
• 93L16
• 93S16

BCD DECADE COUNTER/
4-BIT BINARY COUNTER

SYNCHRONOUS COUNTING AND PARALLEL ENTRY
DECODED TERMINAL COUNT
BUILT-IN CARRY CIRCUITRY
EASY INTERFACING WITH DTL, LPDTL, AND TTL FAMILIES

PKGS

OUT

Plastic
DIP(P)
Ceramic
DIP (0)
Flatpak
(F)

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

A

9310PC, 9316PC
93l10PC, 93l16PC
93S10PC, 93S16PC

A

9310DC, 9316DC
93l10DC, 93l16DC
93S10DC, 93S16DC

9310DM, 9316DM
93l10DM, 93l16DM
93S10DM, 93S16DM

A

9310FC, 9316FC
93L10FC, 93l16FC
93S10FC, 93S16FC

9310FM, 9316FM
93l10FM,93l16FM
93S10FM, 93S16FM

Vee

IlliTC

Pol!

1EJ00

P1[i

tm

01

~02

tTIl 03

P31:!
CEPIT

~CET

GNO[!

t!l'PE

LOGIC SYMBOL

ORDERING CODE: See Section 9
PIN

tI!l

pdl

DESCRIPTION - The '10 is a high speed synchronous BCD decade counter
and the '16 is a high speed synchronous 4-bit binary counter. They are synchronously presetable, multifunctional MSI building blocks useful in a large
number of counting, digital integration and conversion applications. Several
states of synchronous operation are obtainable with no external gating packages required through an internal carry lookahead counting technique.
•
•
•
•

-

MR[I
CP 11:

PKG
TYPE

9B

1iii i
PE Po P, P2 P3
7 - CEP

1 0 - CET

TC - 1 5

2 - CP
MR 00 0, 02 03

YI I r T
1 14 13 12 11

6B
vce

= Pin 16
= Pin 8

GND

4l

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

93XX (U.L.)
HIGH/lOW

DESCRIPTION

00-03

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input
(Active lOW)
Parallel Data Inputs
Parallel Enable Input (Active lOW)
Flip-flop Outputs

TC

Terminal Count Output

CEP
CET
CP
MR

Po-Ps
PE

93L (U.L.)
HIGH/lOW

93S (U.L.)
HIGH/lOW

1.0/1.0
2.0/2.0
2.0/2.0
1.0/1.0

0.5/0.25
1.0/0.5
r.0/0.5
0.5/0.25

2.5/2.5
3.1/3.1
3.1/3.1
1.25/1.25

0.67/0.67
2.0/2.0
16/8.0

0.33/0.17
1.0/0.5
10/5.0
(3.0>
10/5.0
(3.0>

1.25/1.25
2.5/2.5
20/10

20/10

6-30

25/12.5

10 • 16
LOGIC DIAGRAMS
'10, 'L10

.,

'0

"

_to.
-

....

~~

~~
~:"

~~

~~

n

~:"

~D

L...

4

.....q:::

C~

C
A

So

FZf:"

l!

~

'
Co

CII-

,..r-

r

CE.

~

CET

C.

}-

.........

to.

-:::....
-

0,

TC

00

'16,'L16

~

.........

'0

"

"

C.

]

~]

So

CII-

So
C.

~:::

~t'

~~;

Lt

~~

~~

~~

"

~Rc:

c.r-

r

-

r

ca.

to.
....

CET
CP

to.

;:.
-....

00

0,

6-31

0,

~

0,

•

10 -16
LOGIC DIAGRAMS
'S16

_....
CEP

CET

Po

p,

p,

I

I

tJ

tJ

tJ

r

-'"
-.....

P,

~~

.....
I-

~,
...'"

CP

H'

CoCP

MR

LJ

...........

~~

l1c~ ~
1

o

1

I 1
~

-

1

0

I

I

I

----.J

TC

0

H
LJ
1,

J,

j,

do

o

4t-

'S10

-'"
.....
-

_...
CEP

CET

Po

p,

P,

I

I

I

tJ

tJ

~~

.....

~,
CP

tJ

....
....

l'

CoCP

-'"...

o

~

I

I

~~ ~
1

0

H
LJ

~
o

I
6-32

~
TC

~

I

r-

~

I

1
~

o

I

I

10 • 16
FUNCTIONAL DESCRIPTION - The '10 counts modul0-10 in the BCD (8421) sequence. From state9(HLLH) it
increments to state 0 (LLLU. The '16 counts modul0-16 in binary sequence. From state 15(HHHH) it increments
to state 0 (LLLU. The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes
of the Q outputs (except due to Master Reset) occur as a result of, and synchronous with, the LOW-to-HIGH
transition of the CP input signal. The circuits have four fundamental modes of operation, in order of
precedence: asynchronous reset, parallel load, count-up and hOld. Four control inputs - Master Reset (MR)
Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CEn -determine the mode of
operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel
Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CPo With PE and MR HIGH, CEP and
CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The TTL and LP-TTL versions ('10, '16, 'L 10 and 'L 16 as opposed to the 'S10 and 'S16) contain masterslave flipflops which are "next-state catching" because of the JK feedback. This means that when CP is· LOW,
information that would change the state of a flip-flop, whether from the counting logic orthe parallel entry logic
if either mode is momentarily enabled, enters the master and is locked in. Thus to avoid inadvertently changing
the state of a master latch, and the subsequent transfer of the erroneous information to the slave when the clock
rises, it is necessary to insure that neither the counting mode, nor the parallel entry mode is momentarily
enabled while CP is LOW. The S-TTL versions('S10and 'S16) use D-type edge-triggered flip-flops and changing
the PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the
recommended setup and hold times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET Is HIGH and the counter is in its maximlJm count state (9 for
the decade counters, 15 for the binary counters-fully decoded in both types). To implement synchronous
multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. These two
schemes are shown in Figures a and b. The TC output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a clock or asynchronous resetforflip-flops, counters or
registers. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will
return to the normal sequence within two counts, as shown in the state diagrams.
Multistage Counting - The '10/,16 counters may be cascaded to provide multistage synchronous counting.
Two methods commonly used to cascade these counters are shown in Figures a and b.

In multistage counting, all less significant stages must be at their terminal count before the next more significant
counter is enabled. The '10/,16 internally decodes the terminal count condition and "AN Os" it with the CET
input to generate the terminal count (TC) output. This arrangement allows one to perform series enabling by
connecting the TC output (enable signal) to the CET input of the following stage, Figure a. The setup requires
very few interconnections, but has the following drawback: since it takes time for the enable to ripple through
the counter stages, there is a reduction in maximum counting speed. To increase the counting rate, it is
necessary to decrease the propagation delay of the TC signal, which is done in the second method.
The scheme illustrated in Figure b permits multistage counting, limited by the fan-out oftheterminal count. The
CEP input of the '10/'16 is internally "ANDed" with the CET input and as a result, both must be HIGH for the
counter to be enabled. The CET inputs are connected as before except for the second stage. There the CET
input is left floating and is therefore HIGH. Also, all CEP inputs are connected to the terminal output of the first
stage. The advantage of this method is best seen by assuming all stages except the second and last are in their
terminal condition. As the second stage advances to its terminal count, an enable is allowed to trickle down to
the last counter stage, but has the full cycle time of the first counter to reach it. Then as the TC of the first stage
goes active (HIGH), all CEP inputs are activated, allowing all stages to count on the next clock.

6-33

I

10 • 16
MODE SELECT TABLE
INPUTS
MR

PE

L
H
H
H
H

X
L
H
H
H

RESPONSE

CEP CET CP

X
X
L

X
H

X

X
X
X

..r

L
H

..r

X
X

Clear; All Outputs LOW
Parallel Load; Pn - - an
Hold
Hold; TC = LOW
Count Up

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC EQUATIONS
Count Enable = MR • PE • CEP • CET
Terminal Count = CET • 00 • 01 • 02 • 03
Terminal Count = CET • 00 • 01 • 02 • 03

('16)
('10)

STATE DIAGRAMS

'S10

'16, 'S16, 'L 16

'10, 'L 10

NOTE: The '20 can be preset to any state, but will not count beyond 9. If presetto state 10,11,12,13,14 or 15, it will return
to its normal sequence within two clock pulses.

eET 9310. 9316 TC

eey 9310 • 9316 TC

eEY 9310 • 9316 TC

eET 9310 ·9316 TC

eEY 9310.9316 TC
TO MORE
SIGNIFICANT
STAGES

CLOCK--~--------------~------------~__-------------+--------------~----------------

Fig. a Synchronous Multistage Counting Scheme (Slow)

eET 9310 • 9316 TC

eey 9310 • 9316 TC

eET 9310 • 9316 TC

eET 9310 • 9316 TC

CLOCK--~--------------~------------~---------------+--------------~--------------

Fig. b

Synchronous Multistage Counting Scheme (Fast)

6-34

TO MORE
SIGNIFICANT
STAGES

eEY 9310 • 9316 TC

__

10 • 16
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER

los

Output Short Circuit Current

Icc

Power Supply Current

AC CHARACTERISTICS: Vcc

93l

UNITS

Max

Min

Max

Min

Max

-20

-80

-2.5

-25

-40

-100

rnA

127

rnA

92

27.5

= +5.0 V, TA = +25°C (See Section 3 for waveforms and
93XX

SYMBOL

93S

Min

PARAMETER

CL

= 15 pF

Min

Max

CL

= 15 pF

Min

Max

load configurations)

93S
CL

= 15 pF

Min

UNITS

CONDITIONS

Max

fmax
tPLH
tPHL

Propagation Delay
CPto Q

20
23

32
39

9.0
13

ns

tPLH
tPHL

Propagation Delay
CP to TC

35
22

66
30

18
12

ns

tPLH
tPHL

Propagation Delay
CET to TC

19
19

35
30

10
10

ns

Figs. 3-1,

tPHL

Propagation Delay
MR to Q

45

62

20

ns

Figs. 3-1, 3-16

UNITS

CONDITIONS

SYMBOL

PARAMETER

= +5.0 V,

13

= Max
VCC = Max,
MR = Gnd
VCC

Maximum Count Frequency

AC OPERATING REQUIREMENTS: Vcc

30

93l

CONDITIONS

MHz

93XX
Max

93l
Min

Max

93S
Min

Setup Time HIGH or lOW
Pn to CP

30
30

75
75

8.0
5.0

ns

til (H)
tIl(Ll

Hold Time HIGI'I or lOW
Pn to CP

0
0

10
10

0
0

ns

ts (H)
ts(Ll

Setup Time HIGH or lOW
PE to CP

Note 2
30

Note 2
53

10
5.0

ns

th (H)
th (Ll

Hold Time HiGH or lOW
PE to CP

-7.0
Note 2

7.0
Note 2

0
0

ns

ts (H)
ts(Ll

Setup Time HIGH or lOW
CEP or CET to CP

22
Note 1

1

9.0
7.5

ns

til (H)

Hold Time HIGH or lOW
CEP or CET to CP

Note 1
0

Note 1
10

0
0

ns

tw (H)
tw (Ll

3~5

Max

ts (H)
ts(Ll

tIl(Ll

Figs. 3-1,3-8

= +25°C

TA

Min

70

26
~Note

Fig. 3-6

Fig. 3-6

Fig. 3-6

CP Pulse Width

17
17

25
25

6.5
7.0

ns

Fig. 3-8

tw (Ll

MR Pulse Width lOW

30

65

14

ns

Fig. 3-16

trec

Recovery Ti me
MR to CP

15

55

5.5

ns

Fig. 3-16

NOTES:
The Setup Time "Is IL)"and Hold Time "It. IH)" between the Count EnablelCEP and CEn and the Clock ICPt indicate that the HIGH-to-LOWtransltlon of
the CEP and CET must occur only while the Clock is HIGH for conventional operation.
12) The Setup Time "Is IH)" and Hold Time "It. IU" between the Parallel Enable I~ and Clock ICP) Indicate that the LOW-te-HIGH transition of the PE must
occur only while the Clock Is HIGH for conventional operation.
11)

6-35

•

11
CONNECTION DIAGRAM
PINOUT A

9311
93L11
1-0F-16 DECODER/DEMUL TIPLEXER
00 II

liI Ao

odI
odI

B]A1

II
os!!:
06 IT
0, II
08 I!

im A3

I!!l 014

09~

~Eh3

PKG

010 IIi

TYPE

GND~

iEl 012

MUTUALLY EXCLUSIVE OUTPUTS
HIGH CAPACITIVE DRIVE CAPABILITY
DEMULTIPLEXING CAPABILITY
TYPICAL POWER DISSIPATION OF 175 mW FOR '11, 58 mW FOR 'L11
2-INPUT ENABLE GATE

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

~vcc

01 [I

DESCRIPTION - The '11 is a multipurpose decoder designed to accept
four inputs and provide 16 mutually exclusive outputs. The 9311 is a faster
replacement for the 74154.
•
•
•
•
•

'-

Plastic
DIP (P)

A

9311PC, 93L11PC

Ceramic
DIP (0)

A

9311 DC, 93L 11 DC

9311DM,93L11DM

6N

Flatpak
(F)

A

9311 FC, 93L11 FC

9311FM,93L11FM

4M

]1]A2

04

~E1

~EO
~01S

~011

9N

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-A3
Eo, E1
00-015

DESCRIPTION
Address Inputs
AND Enable Inputs (Active LOW)
Decoder Outputs (Active LOW)

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
20/10

0.5/0.25
0.5/0.25
10/5.0
(3.0)

LOGIC SYMBOL

-11-

23

22

21

20

E

Ao

A1

A2

A3

Eo

E1

{)

00 0, 0203 04

Os 06 0,08090100110,20,3 0'40,S

!!!!1!!!!!l1!!!!
6-36

Vee = Pin 24
GND = Pin 12

11
FUNCTIONAL DESCRIPTION - The '11 decoder accepts four inputs and provides 16 mutually exclusive active
LOW outputs, as shown by the logic symbol. The active LOW outputs facilitate addressing other MSI units with
active LOW enable. The '11 can demultiplex data by routing it from one input to one of 16 possible decoder
outputs. The desired output is addressed and the data is applied to one of the enable inputs. Providing that the
other enable is LOW, the addressed output will follow the state of the applied data.

TRUTH TABLE
INPUTS

OUTPUTS

Eo

E1

Ao

A1

A2

A3

00 01

H
H
L
L

H
L
H
L

X
X
X
L

X
X
X
L

X
X
X
L

X
X
X
L

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
L
H
L
H

L
H
H
L
L

L
L
L
H
H

L
L
L
L
L

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

L
H
L
H
L

H
H
L
L
H

H
H
L
L
L

L
L
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
L
H
L
H

H
L
L
H
H

L
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

02 03 04 05 06 07 08 09 010 011 012 013 014 015

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM

6-37

I

11
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER

los

Output Short
Circuit Current

Ice

Power Supply Current

AC CHARACTERISTICS: Vee

XM
XC

= +5.0 V,

93L

Max

Min

Max

-20
-20

-55
-57

-2.5
-2.5

-25
-25

XM

49

16.5

XC

56

16.5

TA

= +25°C (See Section
93XX

SYMBOL

PARAMETER

UNITS

Min

CL
RL

= 15 pF
= 400 n

Min

Max

CONDITIONS

mA

Vee

= Max,

mA

Vee

= Max

VOUT

3 for waveforms and load configurations)

93L
CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
An to On

31
28

75
85

ns

Figs. 3-1,3-20

tPLH
tPHL

Propagation Delay
En to On

23
24

60
65

ns

Figs. 3-1, 3-5

6-38

=0 V

12
CONNECTION DIAGRAM
PINOUT A

9312
93L12
93S12

10

-

IT

j!) Vee

12[2

llIz
lllz

b[!

ElS2

I,[I

a-INPUT MULTIPLEXER

DESCRIPTION - The '12 is a monolithic, high speed, a-input digital multiplexer circuit. It provides, in one package, the ability to select one bit of
data from up to eight sources. The '12 can be used as a universal function
generator to generate any logic function of four variables. 80th assertion and
negation outputs are provided.

• MULTIFUNCTION CAPABILITY
• ON-CHIP SELECT LOGIC DECODING
• FULLY BUFFERED COMPLEMENTARY OUTPUTS

14

II

ms,

15

II

:ill So

16rI

mE

GND[!

1]17

LOGIC SYMBOL

1ii iii iii

E 10 11 12 13 14 Is 16 17

1 1 - SO

ORDERING CODE: See Section 9
PIN
PKGS

OUT

1 2 - S,
1 3 - S,

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9312PC, 93L 12PC
93S12PC

Ceramic
DIP (0)

A

9312DC, 93L 12DC
93S12DC

9312DM,93L12DM
93S12DM

68

Flatpak
(F)

A

9312FC, 93L12FC
93S12FC

9312FM, 93L 12FM
93S12FM

4L

z

z

!

1~

98
vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

Z

Select Inputs
Enable Input (Active LOW)
Multiplexer Inputs
Multiplexer Output

Z

Complementary Multiplexer Output

So-S2

E
10-17

6-39

93XX (U.L.)
HIGH/LOW

93S (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
20/10

1.25/1.25
1.25/1.25
1.25/1.25
25/12.5

20/10

25/12.5

0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(3.0)
10/5.0
(3.0)

12
FUNCTIONAL DESCRIPTION - The '12 is a logical implementation of a single pole, eight position switch with
the switch position controlled by the state ofthree 5elect inputs, So, 51,52. Both assertion and negation outputs
are provided. The Enable input (E) is active LOW. When it is not activated the negation output is HIGH and the
assertion output is LOW, regardless of all other inputs. The logic function provided at the output is;
Z = E • (10 • 80 • 81 • 82

• 50 • 81 • 82 + 12 • So • 51 • 82 + 13 • So • 51 • 82
• 50 • 81 • 52 + 16. So • 51 • 52 + 17 • So • 51 • 52).

+h

+ 14

• 80 • 81 • 52

+ Is

The '12 provides the ability, in one package, to select from eight sources of data or control information. By
proper manipulation of the inputs, the '12 can provide any logic function of four variables and its negation. Thus
any number of random logic elements used to generate unusual truth tables can be replaced by one '12.

TRUTH TABLE
INPUT5

OUTPUT5
13

14

Is

16

17

Z

Z

L

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

H
H
L
H

L
L
H
L

H

X

X
X
X

L
H
X

X
X

X
X
X
X

X
X
X

X
X
X
X

X
X
X
X

L
H
L
H

H
L
H
L

H

X

X

L
H
X

X
X

X
X

X
X

X
L

X
X

X
X

L
H
L
H

H
L
H
L

H
X
X
X
X

X
L
H
X
X

X
X
X
L
H

L
H
L
H
L

H
L
H
L
H

E

52

51

So

10

h

12

H
L
L
L

X

X

X

X

L
L
L

L
L
L

L
L
H

L
H

X
X
X

X

L
L
L
L

L
L
L
L

L
H
H
H

H
L
L
H

X
X
X
X

L
L
L
L

L
H
H
H

H
L
L
L

H
L
L
H

X
X
X

X
X
X

X

X

X
X

L
L
L
L
L

H
H
H
H
H

L
H
H
H
H

H
L
L
H
H

X
X
X
X
X

X
X

X
X

X
X

X
X

X

X

X

X
X
X
X
X
X
X
X

X
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

6-40

X

X
X
X

X

X

12
lOGIC DIAGRAM

I,

10
S2

S1

So

E

.....
....
.....

....
....
---...
....

Is

12

I.

15

16

17

---...
L
I
I

......

.....
-yo"

---...

......
II

I

"j

I

~

I

'l Jf

~

z

~

I

j

y

•

z

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER

Min
lee

= +5.0 V,

Min

Max

TA

= +25°C (See

PA~AMETER

CL

Max

UNITS

CONDITIONS

Max
13.3

mA

Vee

= Max

Section 3 for waveforms and load configurations)

= 15 pF

Min

Min

62

93XX
SYMBOL

93l

Max

44

Power Supply Current

AC CHARACTERISTICS: Vee

93S

93S
CL

93l

= 15

Min

pF CL

Max

= 15

Min

pF

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
So to Z

34
34

17
18

60
75

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
So to Z

24
26

16
15

45
65

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
Eto Z

30
30

13
16

50
70

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
Eto Z

20
23

14
11

35
60

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
In to Z

24
24

12
12

60
55

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
In to Z

14
16

8.0
9.0

45
45

ns

Figs. 3-1, 3-4

6-41

13
CONNECTION DIAGRAM
PINOUT A

-

loD:

9313

!!I Vee

h(I

8-INPUT MULTIPLEXER
(With Open-Collector Output)

fillz

[I

J!]z

13[i

lil S,

12

mSl

14[[

DESCRIPTION - The '13 is an 8-input multiplexer with open-collector output. It has the same pinning and logic configuration as the '12, but with an
open-collector Z output which allows for easy expansion of input terms. The
device can select one bit of data from up to eight sources. The '13 has an active LOW enable and internal select decoding.

III So

15[
16 [I

mE:
}]17

GNOII

• PIN FOR PIN REPLACEMENT FOR THE SIGNETICS 8231
• SAME PINNING AND LOGIC CONFIGURATION AS THE 9312
BUT WITH OPEN-COLLECTOR OUTPUT
• OPEN-COLLECTOR OUTPUT Z FOR EASY EXPANSION
OF INPUT TERMS (WIRED-OR APPLICATIONS)
• MULTIFUNCTION CAPABILITY
• ON-CHIP SELECT LOGIC DECODING
• FULLY BUFFERED Z OUTPUT

LOGIC SYMBOL

11iiiiifi
E

10

11

12

b

14

15

1 1 - SO
12-S,

ORDERING CODE: See Section 9

13-

PIN
PKGS

OUT

COMMERCIAL GRADE
Vee

TA

= +5.0 V ±5%,

MILITARY GRADE
Vee

= O°C to +70°C

TA

= +5.0

= -55°C

V ±10%,

to +125°C

PKG
TYPE

Plastic
DIP (P)

A

9313PC

Ceramic
DIP (0)

A

9313DC

9313DM

68

Flatpak
(F)

A

9313FC

9313FM

4L

98

s,

z

z

! II
Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES
So-S2

E

10-17

Z

Z·

Select Inputs
Enable Input (Active LOW)
Multiplexer Inputs
Multiplexer Output
Complementary Multiplexer Output

'An external pull-up resistor is needed to provide
"OC-Open Collector

HIGH

93XX (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
20/10
OC"/10

level drive capability. This output will sink a maximum of 16 mA at VOUT = 0.4 V.

6-42

16

17

13
FUNCTIONAL DESCRIPTION - The '13 is a logical implementation of asingle pole, eight-position switch with
the switch position controlled by the state of three Select inputs, So, S1, S2. An open-collector output Z is
provided for easy expansion of input terms. Also a fully buffered Z output is available. The Enable Input @is
active LOW. When it is not activated the negation output is HI GH and the assertion output is LOW regardless of
all other inputs. The logic function provided at the output is:
Z = E • (10 • So • S1 • S2

+ 11

• So • 81 • 82 + 12 • So • S1 • 82 + 13 • So • S1 • 82
• So • 81 • S2 + 16 • So • S1 • S2 + 17 • So • S1 • S2)

+ 14

•

So • 81

• S2

+ Is

The '13 provides the ability, in one package, to select from eight source~ of data or control information. By
proper manipulation of the inputs, the '13 can provide any logic functio_ns of four variables and its negation.

TRUTH TABLE
INPUTS

OUTPUTS

E

S2

S1

So

Z

Z

H
L
L
L

X
L
L
L

X
L
L
H

X
L
H
L

H
10
11
12

L
10
11
12

L
L
L
L
L

L

H
L
L

H
L

13
14

H

15

H
H

L

16
17

13
14
Is
16
17

H
H
H
H

H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
14

10

15

16

17

S2~o-~~--a~~----+------4------~------~-----4~----~~----~~---4~

so---i.~~~--~~I;~----~r---~~~---HH-----+H~---4++-----H.t----+Hr---~~

z

6-43

13
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
93XX

PARAMETER

SYMBOL

Min
10H

Output HIGH Current, Z

los

Output Short Circuit Current, Z

lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0

V, TA

0

CONDITIONS

150

JJ.A

Vee = 4.5 V, Your = 4.5 V, VIN = 0.6 V
on Data Input, VIN (E & Sn Inputs) = VIL
or VIH per Truth Table

-70

mA

Vee

47

mA

Vee

-20

= +25

UNITS

Max

= Max, Your = 0 V
= Max, 10 -17 = Gnd

C (See Section 3 for waveforms and load configurations)
93XX

SYMBOL

PARAMETER

CL

= 15

Min

pF

UNITS

CONDITIONS

Max

34
34

ns

Figs. 3-1, 3-20

So to Z

29
28

ns

Figs. 3-2, 3-20
RL = 400 n

tPLH
tPHL

Propagation Delay
10 to Z

30
30

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
10 to Z

26
24

ns

Figs. 3-2, 3-4
RL = 400 n

tPLH
tPHL

Propagation Delay
E to Z

34
36

ns

Figs. 3-1, 3-4

tPLH
tpHL

Propagation Delay
Eto Z

27
29

ns

Figs. 3-2, 3-5
RL = 400 n

Propagation Delay

tPLH
tPHL

So to Z

tPLH
tPHL

Propagation Delay

6-44

14
CONNECTION DIAGRAM
PINOUT A

9314
93L14

-

EU

QUAD LATCH

~vcc

solI

fIDQO

DolI

~S1

0, [I

~Q1

~Q2

S2[I

till 83

I!
03 IT

02

~Q3

~Mii

GND[I

DESCRIPTION - The '14 is a multifunctional4-bit latch designed for general
purpose storage applications in high speed digital systems. All outputs have
active pull-up circuitry to provide high capacitance drive and to provide low
impedance in both logic states for good noise immunity.

• CAN BE USED AS SINGLE INPUT D LATCHES
OR SET/RESET LATCHES
• ACTIVE LOW ENABLE GATE INPUT
• OVERRIDING MASTER RESET

LOGIC SYMBOL

1

3

2

4 14 6

5

7 11

~I~I~I~I~
E Do So 0, S, 02 S2 03 S3

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Qo

Q1

Q2

Q3

PKG

MR

TYPE

I I I I I
9

Plastic
DIP(P)

A

9314PC, 93L 14PC

Ceramic
DIP (D)

A

9314DC, 93L14DC

9314DM, 93L 14DM

68

Flatpak
(F)

A

9314FC, 93L14FC

9314FM, 93L 14FM

4L

15

13

12

10

98
vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

E
Do-D3

SO-53
MR
00-03

DESCRIPTION
Enable Input (Active LOW)
Data Inputs
Set Inputs (Active LOW)
Master Reset Input (Active LOW)
Latch Outputs

6-45

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

1.0/1.0
1.5/1.5
1.0/1.0
1.0/1.0
20/10

0.5/0.25
0.75/0.375
0.5/0.25
0.5/0.25
10/5.0
(3.0)

14
FUNCTIONAL DESCRIPTION - The '14 consists of four latches with a common active LOW Enable input and
active LOW Master Reset input. When the Enable goes HIGH, data present in the latches is stored and the state
of the latch is no longer affected by the Sn and Dn inputs. The Master Reset when activated overrides all other
input conditions forcing all latch outputs LOW. Each of the four latches can be operated in one of two modes:
D-TYPE LATCH- For D-type operation the S input of a latch is held LOW. While the common Enable is active
the latch output follows the D input. Information present at the latch output is stored in the latch when the
Enable goes HIGH.
SET/RESET LATCH - During set/reset operation when the common Enable is LOW a latch is reset by a LOW
on the D, input, and can be set by a LOW on the S input if the D input is HI GH. It both Sand D inputs are LOW, the
D input will dominate and the latch will be reset. When the Enable goes HIGH, the latch remains in the last state
prior to disablement. The two modes of latch operation are shown in the Truth Table.
TRUTH TABLE
OPERATION

MR

E

D

S

On

H
H
H

L
L
H

L
H
X

L
L
X

D MODE
L
H
On-1

H
H
H
H
H

L
L
L
L
H

L
H
L
H
X

L
L
H
H
X

R/S MODE
L
H
L
On-1
On-1

L

X

X

X

L

RESET

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
On-1 = Previous Output State
an = Present Output State

LOGIC DIAGRAM

6-46

14
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

93XX
Min

lee

Power Supply Current

Max

93l
Min

55

UNITS

CONDITIONS

Max
16.5

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

93XX
PARAMETER

SYMBOL

93l

CL = 15 pF CL = 15 pF
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

E to

Propagation Delay
an

24
24

45
36

ns

Figs. 3-1, 3-9

tPLH
tpHL

Propagation Delay
On to an

12
24

30
30

ns

Figs. 3-1, 3-5

tPLH

Propagation Delay
MR to an

18

30

ns

Figs. 3-1, 3-16

tpHL

Propagation Delay
Sn to an

24

33

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

93XX
Min

Max

93l
Min

UNITS

ts (H)
ts (U

Setup Time HIGH or lOW
On to E

5.0
18

10
20

ns

th (H)
th (U

Hold Time HIGH or LOW
On to E

0
5.0

0
10

ns

ts

(H)

CONDITIONS

Max

Fig. 3-13

Setup Time HIGH, On to Sn

8.0

15

ns

th (U

Hold Time LOW, On to Sn

8.0

5.0

ns

tw (U

E Pulse Width LOW

18

30

ns

Fig. 3-9

tw (U

MR Pulse Width LOW

18

25

ns

Fig. 3-16

tree

Recovery Time, MR to E

0

5.0

ns

Fig. 3-16

6-47

Fig. 3-13

15
CONNECTION DIAGRAM
PINOUT A

9315
1-0F-10 DECODER
DESCRIPTION-The '15 accepts 1248 binary coded decimal inputs and
provides ten mutually exclusive outputs to directly control the ionizing
potentials of many gas filled cold cathode indicator tubes. The '15 is a
pin-for-pin equivalent to the 7441 and is similar in operation to the C/lL996D
but can be driven from any TTL or DTL product.

•
•
•
•
•

OB!:!

:ill 0,

Ao!2

:Ii] 05

A3~

TIl 04

Vee

II

~GND

A1[I

32106

A2[I

~()y

odI

~O3

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0. V ±5%,
TA = DOC to +7D o C

Vee = +5.0. V ±1D%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9315PC

Ceramic
DIP (D)

A

9315DC

9315DM

68

Flatpak
(F)

A

9315FC

9315FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-A3

00-09
·oc -

93XX (U.L.)
HIGH/LOW

DESCRIPTION
Address (Data) Inputs
Decoder Outputs (Active LOW)

0..13/0..94
OC*/7.0mA

Open Collector

LOGIC SYMBOL

I i

Ao

Ai

r

A2

1

A3

00 0, 02 03 04 05 06 07 08 09

!l!!X!~!!!
6-48

:i] 00

II

09

STABLE HIGH VOLTAGE OUTPUT CHARACTERISTICS
DIRECT DISPLAY DRIVE CAPABILITY
BCD ACTIVE HIGH INPUTS
BLANKING TEST MODE
-55°C to +125°C TEMPERATURE CAPABILITY

~

Vee = Pin 5
GND = Pin 12

15
FUNCTIONAL DESCRIPTION - The 1-of-10 decoder/driver accepts BCD inputs from all TTL circuits and
produces the correct output selection to directly drive gas filled cold cathode indicator tubes. The outputs are
selected as shown in the Truth Table. It is capable of driving all known available cold cathode indicator tubes
having 7.0 rnA or less cathode current. Unused input codes 12 and 13 cause all the outputs to remain HIGH; no
cathode will be selected. This results in the indicator tube being blanked. Using this feature for blanking may
cause a slight glow to appear in the tube.
TRUTH TABLE
INPUTS

OUTPUTS

Ao

A1

A2

As

50

01

02 03 04 Os 06 07 06 09

0
1
2
3

L
H
L
H

L
L
H

r-i

L
L
L
L

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

4
5
7

L
H
L
H

L
L
H
H

H
H
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

8
9
10
11

L
H
L
H

L
L
H
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
L
H

H
L
H
L

12
13
14
15

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

6

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
Ao

~

I~

Ii I
08

J

I
06

J

~
Os

6-49

(J ()

I

)
00

15
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER
Min

VOH

Output HIGH Voltage

UNITS

CONDITIONS

V

Vee = Max, Force 2.0 rnA
into HIGH Output

V

Vee = Min, IOL = 7.0 rnA
Inputs at Threshold
Voltages, (VIL or VIH) as
per Truth Table

V

Guaranteed Input HIGH
Threshold Voltage

V

Guaranteed Input LOW
Threshold Voltage

Max

70

VOL

Output LOW Voltage

XM
XC

VIH

Input HIGH Voltage

XM
XC

VIL

Input LOW Voltage

XM
XC

1.1
0.85

IOH

Output HIGH Current

XM
XC

20
40

p.A

Vee = Max, VOUT = 55 V
Inputs at Threshold
Voltages, (VIL = Gnd,
VIH = 4.5 V), as per
Truth Table

hH

Input HIGH Current

XM
XC

2.0
5.0

p.A

Vee = Max, VIN = 4.5 V
Other Inputs Open

hL

Input LOW Current

-1.5

rnA

Vee = Max, VIN = 0.4 V
Other Inputs Open

Icc

Power Supply Current

29
31

rnA

Vee = 5.0 V, No Connection
to Input or Output Pins

I

2.5
3.0
1.9
2.0

XM
XC

6-50

17
CONNECTION DIAGRAM
PINOUT A

93178
9317C

-

A'[I

t!!Jvcc

nlr
EJii
TIl·
:ffili

A2[!

7-SEGMENT DECODER/DRIVER

L'i'[I
RBci[i
RBf[[

DESCRIPTION - The '17 is a seven segment decoder/driver designed to
accept four inputs in 8421 BCD code and provide the appropriate outputs to
drive a 7-segment numerical display. The decoder can be used to directly
drive 7-segment incandescent lamp displays and light emitting diode indicators (or indirectly drive neon, electro-luminescent, numeric displays>. The
'17 is available in two output current and latch voltage versions, the '17B
and C.
• AUTOMATIC RIPPLE BLANKING FOR SUPPRESSION OF LEADING
AND/OR TRAILING-EDGE ZEROES
• LAMP INTENSITY MODULATION CAPABILITY
• LAMP TEST FACILITY/BLANKING INPUT
• CODES IN EXCESS OF BINARY 9 DISABLE OUTPUTS

PKGS

OUT

MILIT ARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

A

9317PC

Ceramic
DIP (D)

A

9317DC

Flatpak
(F)

A

9317FC

GNOII

~i

7

1

I I

Ao Al

COMMERCIAL GRADE

Plastic
DIP (P)

TIll!
:!!Iii

LOGIC SYMBOL

ORDERING CODE: See Section 9
PIN

Ao[f

A3[!

i i 11

A2

A3

LT RBI

PKG
TYPE

a

bed

e

f

9 RBO

9B

XXX!!!!!

9317DM

7B

Vee = Pin 16
GND = Pin 8

9317FM

4L

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

93XX (U.L.)
HIGH/LOW

Address Inputs
Lamp Test Input (Active LOW)
Ripple Blanking Input (Active LOW)
Ripple Blanking Output (Active LOW>
Outputs

1.0/1.0
5.0/4.0
1.0/0.5
1.5/1.5
See Options

PIN NAMES
Ao-A3
LT

RBi
RBO

a-g
OPTIONS
PARAMETER

Latch Voltage
Output Current (Pins 9 through 15)

6-51

9317B

9317C

20 V
40 mA

30 V
20 mA

•

17
LOGIC DIAGRAM
iIIi

[f

'(7

A,

Ao

A1

A2

t)

Ij

t)

r- ~

f

,

",7

f0-

f-

~

TRUTH TABLE
INPUTS

OUTPUTS

A2.

A3

a

E

C

d

e

T

9

RBO

DECIMAL
OR
FUNCTION

X
L
L
L

X
L
L
L

X
L
L
L

L
H
L
H

L
H
L
H

L
H
L
H

L
H
L
H

L
H
L
L

L
H
L
L

L
H
H
H

H
L
H
H

0
0
1

L
H
L
H

H
H
L
L

L
L
H
H

L
L
L
L

L
L
H
L

L
L
L
H

H
L
L
L

L
L
H
L

L
H
H
H

H
H
L
L

L
L
L
L

H
H
H
H

2
3
4
5

X
X
X
X
X

L
H
L
H
L

H
H
L
L
H

H
H
L
L
L

L
L
H
H
H

H
L
L
L
H

H
L
L
L
H

L
L
L
L
H

L
H
L
H
H

L
H
L
H
H

L
H
L
L
H

L
H
L
L
H

H
H
H
H
L

10

X
X
X
X
X

H
L
H
L
H

H
L
L
H
H

L
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

11
12
13
14
15

LT

RBI

L
H
H
H

X
L
H
X

X
L
L
H

H
H
H
H

X
X
X
X

H
H
H
H
H
H
H
H
H
H

Ao A1

H = HIGH Voltage Level

L = LOW Voltage Level

x = Immaterial

6-52

6
7

8
9

17
FUNCTIONAL DESCRIPTION - The '17 7-segment decoder/driver accepts a 4-bit BCD 8421 code input and
produces the appropriate outputs for selection of segments in a seven segment matrix display used for
representing the decimal numbers 0 - 9. The seven outputs (8 - Ql of the decoder select the corresponding
segments in the matrix shown in Figure B. The numeric designations chosen to represent the decimal numbers
are shown in Figure c. Code configurations in excess of binary nine disable the outputs.
The decoder has active LOW outputs so that it may be used directly to drive incandescent displays or light
emitting diode indicators. The device has provision for automatic blanking of the leading and/or trailing-edge
zeroes in a multidigit decimal number, resulting in an easily readable decimal display conforming to normal
writing practice. I n an eight digit mixed integer fraction decimal representation, using the automatic blanking
capability, 0060.0300 would be displayed as 60.03. Leading-edge zero suppression is obtained by connecting
the Ripple Blanking Output(RBO) of a decodertothe Ripple Blanking Input(RBi) ofthe next lower stage device.
The most significant decoder stage should have the RBT input grounded; and, since suppression of the least
. significant integer zero in a number is not usually desired, the RBI input of this decoder stage should be left
open. A similar precedure for the fractional part of a display will provide automatic suppression oftrailing-edge
zeroes.
The decoder has an active LOW input Lamp Test which overrides all other input combinations and allows
checking on possible display malfunctions. The RBO terminal of the decoder can be OR-tied with a modulating
signal via an isolating buffer to achieve pulse duration intensity modulation. A suitable signal can be generated
for this purpose by forming a variable frequency multivibrator with a cross coupled pair of TTL gates. Forcing
the RBO LOW will blank the display, regardless of the CT or An inputs.

X, X2 X4 Xa
I
I
I

I
I
I

I
I
I

I
I
I LAMP TEST

I I I I ! ! ~~:~~E

a

BLANKING

Ao A, A2 A3 LT RBI

RBO a b c

Fig. a Segment Designation

RIPPLE BLANJG
OUTPUT
.~~

DISPLAY SEGMENT" 7

del

9

111111

I I I I I I
I I I I I I
I I I I I I
TO REMAINING
DISPLAY SEGMENTS

v+
Fig. b Seven segment Decoder Driving
Incandescent Lamp Display

o

I-II
I_II

1

2

3

-I
1Fig. c

4

5

I I 1-

6

7

-I

-I -I

Numerical DeSignations

6-53

8

I

9

17
DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee = +5.0 V ±5%
SYMBOL

O°C

PARAMETER

Min

VOH

Output HIGH Voltage
on Rm50nly

25°C

Max

3.0

Min

3.0

0.45
VOL

VOL

Max

75°C
Min

3.0

0.45

0.45

0.45

0.45

93178

0.9

0.9

0.9

9317C

0.45

0.45

0.45

Output LOW Voltage

Output Latch Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

93178
9317C

CONDITIONS

V

Vee = 4.75 V
IOH = -70 p.A
Pin 5 = VIH
Pins 1,2,6,7=OV

V

Vee = 5.25 V
IOL = 2.75 rnA
Inputs at VIH
or VOL per
Truth Table
Vee - 4.75 V
IOL = 2.4 rnA
Inputs at VIH
or VIL per
Truth Table

V

Vee = 4.75
IOL =40 rnA
Pin 3 = 0 V
Vee = 4.75 V
IOL = 20 rnA
Pin 3 = 0 V

0.45

Output LOW Voltage
on ABO Only

VLATeH

UNITS

Max

20
30

20
30

20
30

V

IOL = 10 rnA
Inputs = Open

2.0

2.0

2.0

V

Guaranteed
Input HIGH
Threshold

V

Guaranteed
Input LOW
Threshold

0.85

0.85

IOH

Output HIGH Current

200

tPLH
tPHL

Propagation Delay

500
500

6-54

0.85

250

p.A

Vee = 5.25 V
VeEx = 30 V
('17C) 20 V ('178)
Inputs at VIH
or VIL per
Truth Table

ns

Fig. 3-20

17
DC AND AC CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE: Vee
SYMBOL

-55°C

PARAMETER

Min

VOH

Output HIGH Voltage
on RBO Only

Max

3.0

25°C
Min

3.0

0.4
VOL

VOL

Max

125°C
Min

0.4

0.4

0.4

9317B

0.8

0.8

0.8

9317C

0.4

0.4

0.4

Output LOW Voltage

Output Latch Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

9317B
9317C

CONDITIONS

V

Vee = 4.5 V
IOH = -70 p.A
Pin 5 = VIH
Pins 1,2,6,7 = 0 V

V

Vee = 5.5 V
IOL = 3.1 rnA
Inputs at VIH
or VIL per
Truth Table
Vee - 4.5 V
IOL = 2.4 rnA
Inputs at VIH
or VIL per
Truth Table

V

Vee = 4.5 V
IOL = 40 rnA
Pin 3 = 0 V
Vee - 4.5 V
IOL = 20 rnA
Pin 3 = 0 V

0.4

Output LOW Voltage
on RBO Only

VLATeH

UNITS

Max

3.0

0.4

= +5.0 V ±10%

20
30

20
30

20
30

V

lOUT = 10 rnA
Inputs = Open

2.1

1.9

1.7

V

Guaranteed
Input HIGH
Threshold

V

Guaranteed
Input LOW
Threshold

1.4

1.1

IOH

Output HIGH Current

200

tPLH
tPHL

Propagation Delay

500
500

6-55

0.8

250

p.A

Vee = 5.5 V
VeEx = 30 V
(,17C) 20 V (,17B)
Inputs at VIH
or VIL per
Truth Table

ns

Fig. 3-20

18
CONNECTION DIAGRAM
PINOUT A

9318
93L18

14

a-INPUT PRIORITY ENCODER

• MULTIFUNCTION CAPABILITY
CODE CONVERSIONS
MULTI-CHANNEL DI A CONVERTER
DECIMAL TO BCD CONVERTER
• CASCADING FOR PRIORITY ENCODING OF N BITS
• INPUT ENABLE CAPABILITY
• PRIORITY ENCODING-AUTOMATIC SELECTION
OF HIGHEST PRIORITY INPUT LINE
• OUTPUT ENABLE -ACTIVE LOW WHEN ALL INPUTS HIGH
• GROUP SIGNAL OUTPUT-ACTIVE WHEN ANY INPUT IS LOW

OUT

IlliEO

16 IT

~GS

178:

E]13 .

EIII

::m 12

A2[I

2].,

A1[I

:ill 10
}JAo

GNOII

LOGIC SYMBOL

~ XYIlllLl
10 ., 12 13 14 15 16 17 EI

ORDERING CODE: See Section 9

PKGS

~vcc

15 IT:

DESCRIPTION - The '18 multipurpose encoders are designed to accept
eight inputs and produce a binary weighted code of the highest order input.

PIN

-

IT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
OIP(P)

A

9318PC, 93L 18PC

Ceramic
OIP(o)

A

93180C, 93L180C

93180M, 93L 180M

68

Flatpak
(F)

A

9318FC, 93L18FC

9318FM, 93L 18FM

4L

98

Ao

A1

! !

I

EO

7

A2

r!

Vcc = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT:See Section 3 for U.L. definitions
PIN NAMES

To
T1- T7

DESCRIPTION

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

1.0/1.0
2.0/2.0
2.0/2.0
20/10

0.5/0.25
1.0/0.5
1.0/0.5
10/5.0
(3.0)
10/5.0
(3.0)
10/5.0
(3.0)

EO

Priority Input (Active LOW)
Priority Inputs (Active LOW)
Enable Input (Active LOW)
Enable Output (Active LOW)

GS

Group Select Output (Active LOW)

20/10

Ao-~

Address Outputs (Active LOW)

20/10

Ef

6-56

GS

18
FUNCTIONAL DESCRIPTION - The '18 8-input priority encoder accepts data from eight active LOW inputs
and provides a binary representation on the three active LOW outputs. A priority is assigned to each input so
that when two or more inputs are simultaneously active, the input with the highest priority is represented on the
output, with input line 7 having the highest priority. A HIGH on the Enable Input (Eh will force all outputs tothe
inactive (HIGH) state and allow new data to settle without producing erroneous information at the outputs. A
Group Signal output (GS) and Enable Output (EO) are provided with the three data outputs. The GS is active
LOW when any input is LOW; this indicates when any input is active. The EO is active LOW when all inputs are
HIGH. Using the output enable along with the input enable allows priorityencoding of N input signals. Both EO
and GS are in the inactive HIGH state when the input enable is HIGH.

LOGIC DIAGRAM

10

i,

i4

is

is

7

7

T

-- J

~'-!

J

T r

~
A2

y

\-;

~ r-~ I..T"'
A,

6-57

,,-I

,~

Ao

I....
c

GS

-EO

18
TRUTH TABLE

OUTPUTS

INPUTS
EI

To

11

T2

T3

14

Ts

T6

17

GS Ao

A1

A2

EO

H
L
L
L
L

X
H
X
X
X

X
H
X
X
X

X
H
X
X
X

X
H
X
X
X

X
H
X
X
X

X
H
X
X
L

X
H
X
L
H

X
H
L
H
H

H
H
L
L
L

H
H
L
H
L

H
H
L
L
H

H
H
L
L
L

H
L
H
H
H

L
L
L
L
L

X
X
X
X
L

X
X
X
L
H

X
X
L
H
H

X
L
H
H
H

L
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H

L
L
L
L
L

H
L
H
L
H

H
L
L
H
H

L
H
H
H
H

H
H
H
H
H

H
H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
93XX

PARAMETER

SYMBOL

Min
Input HIGH"Current

IiH

10-i7,Ei

los

Output Short Circuit Current

lee

"Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

-20

93l

Max

Min

mA

Vee = Max,
VIN = 5.5 V

-70

mA

Vee

mA

Vee

22

= +25°C (See Section 3 for waveforms and
93XX

PARAMETER

SYMBOL

CONDITIONS

1.0

77

TA

UNITS

Max

CL

= 15 pF

Min

Max

= Max,
= Max

VOUT

load configurations)

93l
CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Tn to EO

10
18

18
50

ns

Figs. 3-1, 3-4

tPLH
tPHL

Ef to

Propagation Delay
GS

14
16

20
28

ns

Figs. 3-1, 3-5

tPLH
tPHL

t!opagation Delay
EI to EO

14
22

20
36

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay

ET to An

17
17

33
26

ns

Figs. 3-1, 3-5

tPLH
tPHL

Tn

Propagation Delay
to GS

14
16

60
26

ns

Figs. 3-1, 3-5

tPLH
tPHL

Tn

Propagation Delay
to An

21
21

36
36

ns

Figs. 3-1, 3-20

6-58

=0 V

/

19 .20
CONNECTION DIAGRAM
PINOUT A

9319 • 9320
DECADE SEQUENCERS
DESCRIPTION - The '19 and '20 are high speed counters with ten decoded
active LOW outputs. The '19 has standard TTL totem pole outputs, and the
'20 has resistor pull-up outputs for wired-AND applications. The devices provide a 1-of-1 0 sequential output pattern by the application of ten pulses to the
Clock input. Shorter sequenc·es can be obtained by using external feedback,
either hard-wired or programmable via multiplexing.

•
•
•
•
•
•

cpIT

COMBINATION DECADE COUNTER AND 1-0F-10 DECODER
GLiTCHLESS, SEQUENTIAL 1-0F-10 OUTPUT PATTERN
IDEAL FOR MULTIPHASE CLOCK GENERATION
ANY SEQUENCE BETWEEN TWO AND TEN OBTAINABLE
HIGH SPEED CLOCK INPUTS-TYPICALLY 50 MHz
WIRED-AND CAPABILITY (9320 ONLY)

-

~vcc

CEil

fill

iRIT

~o,

MRIT
09[[

~02
~"O3

OB[!

~04
~O5
~"O6

07 [I
GNO[!

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (P)

A

9319PC, 9320PC

Ceramic
DIPm)

A

9319DC, 9320DC

9319DM,9320DM

68

Flatpak
(F)

A

9319FC, 9320FC

9319FM, 9320FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
CP
CE
SR
MR

Co-Os

DESCRIPTION

9319 (U.L.)
HIGH/LOW

9320 (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0

1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0

20/10

3.0/10

Clock Pulse Input (Active Rising Edge)
Clock Enable Input
Synchronous Reset Input (Active LOW)
Asynchronous Master Reset Input
(Active LOW)
Decoded Outputs (Active LOW)

1

1

LOGIC SYMBOL

SR

MR
1 - CP
2 - CE

00 0, 02 03

O. 05 06 07 OB 09

1XXXX!!lrr
6-59

Vcc = Pin 16
GND = Pin 8

00

•

19 .20
LOGIC DIAGRAM

iii-~II"""'----'

CP==DO-~~----------4-'---------~-'----------~~---------4-'
CE

iiii
i5

E

BB

A Ii

C

Eii:

BC

Ai

co

~~
0,

00

E E

o 0

DE

AE

Ii B

ic

CD

DE

O.

Os

06

0,

06

O.

~~~ ~~~

(]
i

02

C

C

03

TRUTH TABLE

OPERATING
MODE

INPUTS
MR

SR

Initialize,
Asynchronous Reset

L
L-H

X
X

Synchronous Reset

H

L

Hold

H

Sequence/Count

H
H
H

···
·

H
H
H
H

OUTPUTS

CE CP

00 01

02

X

(quiescent)

H
L

H
H

H
H

H

..r

L

H

H

X

L

X

H
H
H

H
H
H

..r
..r
..r

··
··

H
H
H
H

···
·

H
H
H
H

X

··
··
..r

..r
S
I

· · · ·

07

Os Os

H
H

H
H

H
H

H

H

H

(No Change)
L
H
H

··
··

H
H
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

6-60

H
L
H

··
··

H
H
H
H

H
H
L

··

··

H
H
H
H

·· ·· ·· ··
· · · ·· · ·
·· ·· ··
·· ·· ·· ·· · · ·
·· ·· ·· ··
H
H
H

H
H
H

H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

19 • 20
FUNCTIONAL DESCRIPTION - The '19 and '20 are decade shift counters with active LOW 1-of-10 decoded
outputs. The decoded shift counter technique provides ten mutually exclusive, glitchless outputs. The edgetriggered counter is advanced on each LOW-to-HIGH transition of the Clock input (CPl. When the Clock Enable
(CEl, Synchronous Reset (SR), Master Reset (MR) are HIGH, the device is sequenced via the Clock thru output
states 00 - '09, successively.
The active HIGH Count Enable (CEl input is gated with the Clock and can be interchanged with Clock for layout
convenience. A LOW on the CE input inhibits the Clock and stops the counter. By returning one of the outputs to
the CE input, the device will sequence upto that output state and stop until reset with the Master Reset. Because
the CE input is gated with the CP input, it oannot be changed from LOW to HIGH while the CP is HIGH.
The active LOW Synchronous Reset (SR) is used to reset the counter to zero (returni ng the output to the 00 state)
in response to the LOW-to-HIGH transitton of the Clock. Any sequence between "two" and "ten" can be
obtained by connecting the last desired 'output to the SR input. This method of truncating the sequence
produces a series of pulses of equal duration as long as the clock frequency remains constant.
A LOW on the Master Reset (MR) overrides all other input conditions and resets the counter to zero. As long as
the MR is LOW, all of the outputs are HIGH. When the MR goes from LOW to HIGH, the zero output (00) goes
LOW. This MR gating with the 00 output insures complete system resetting or initialization before the first
output In the sequencer is activated. For low frequency applications (below 1.0 MHz) the MR can be used in lieu
of the SR for truncating the count sequence. If the input CP rise time is very slow (over 100 ns), the MR input
should be used to reset the counter to avoid mis-triggering. This is accomplished by returning the next higher
output to the MR pin. After the desired sequence is completed, the next clock pulse will reset the counter and
enable the first output within 50 ns.
The outputs of the '19 are standard TTL totem pole type which can drive up to ten standard TTL unit loads. The
outputs of the '20 are DTL resistor pull-up type for applications requiring wired-AND connections. The on-chip
pull-up resistors, (about 3 kOl of the '20 eliminate the need for external resistors normally required by opencollector outputs. Up to eight '20 outputs can be tied together with enough sink current capability left to drive
one standard TTL input or five 93L or 54LS174LS inputs.
The '19 and '20 will normally require initialization after power is first applied. A LOW pulse on the Master Reset
(or a LOW on the Synchronous Reset in conjunction with a clock pulse) will reset the 5-bit register and activate
output 00. If initialization is not possible or not required, an error correction circuit is provided to detect some of
the 22 unused states and return the counter to the proper sequence within ten clock cycles.

6-61

19 • 20
ENABLE

ENABLE

(HIGH)

-

6

6

MR

SR

b

(HIGH)

b
SR

MR

-

CP

00 01 02 03 04 Os 06 07 Os 09

CP

yrl¥:n

00 01 02 03 04 Os 06 07 Os 09

Y y Y YY Y Y
_3

Y

2
1

1

LJ

2

LJ

LJ
LJ

Fig. a Three-Phase Generator Operating
at One-Third the Clock Frequency

Fig. b Three-Phase Generator Operating
at One-Sixth the Clock Frequency

ENABLE
(HIGH)
CLOCK

6

6
MR

SR

SR

'-- CP

-

CP
#1

#2

00 01 02 03 04 Os 06 07 06 09

00 01 02 03 04 Os 06 07 06 09

CE

t----I r j
po-~

o

1

2

3

4 5

6

7

I

8

9

-10 11 12 13 14 15 16 17 18

Fig. c Expansion for longer sequences. The first sequencer locks up after 09 goes LOW because of the
feedback to CEo Simultaneously, SR of the second sequencer Is released and It starts counting on the next
clock. When 09 of the second sequencer goes LOW, the feedback to MR causes (jg of the first sequencer to go
HIGH, which then makes SR of the second sequencer go HIGH. On the next clock the second sequencer goes to
the 00 state, releasing MR of the first sequencer, making Its 00 go LOW. On the next clock the first sequencer
starts Its counting sequence again.

6-62

19. 20
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

9319

PARAMETER

SYMBOL

Min
VOH

Output HIGH Voltage

los

Output Short Circuit Current

lee

Power Supply Current

Max

9320
Min

UNITS

2.4
-1.3

CONDITIONS

Max
V

10H = -120 p.A

-3.7

rnA

Vee = Max, VOUT = 0 V

60

rnA

Vee = Max

60

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

9319
PARAMETER

SYMBOL

9320

CL = 15 pF CL = 15 pF
RL=400n
Min

Max

fmax

Maximum Count Frequency

35

tPLH
tpHL

Propagation Delay
CP to On

40
30

tPLH
tPHL

PropaQ.!tion Delay
MR to On

50
33

Min

UNITS

CONDITIONS

Max
MHz

Figs. 3-1, 3-8

40
30

ns

Figs. 3-1, 3-8

50
33

ns

Figs. 3-1, 3-16

35

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
PARAMETER

SYMBOL

9319
Min

Max

9320
Min

UNITS

CONDITIONS

Max

ts (H)
ts(U

Setup Time HIGH or LOW
SR to CP

10
10

10
10

ns

th (H)
th (U

Hold Time HIGH or LOW
SR to CP

5.0
5.0

5.0
5.0

ns

Fig. 3-6

tw

CP Pulse Width

15

15

ns

Fig. 3-16

tw(U

MR or SR Pulse Width LOW

9.0

9.0

ns

Fig. 3-16

tree

Recovery Ti me
MR to CP

35

35

ns

Fig. 3-16

,

21
CONNECTION DIAGRAM
PINOUT A

9321
93L21

eaIT

DUAL 1-0F-4 DECODER

Ao.[!

-

~vcc

~eb
~Aob

A1a!!

o~. [!
01a

~A1b
~OOb
~01b
~02b
~03b

I!

02.[!
03. IT
GND!!

DESCRIPTION - The '21 consists of two independent mUltipurpose decoders, each designed to accept two inputs and provide four mutually exclusive outputs. In addition an active LOW enable input, which gives demultiplexing capability, is provided for each decoder.

•
•
•
•

MULTIFUNCTION CAPABILITY
MUTUALLY EXCLUSIVE OUTPUTS
DEMUL TIPLEXING CAPABILITY
ACTIVE LOW ENABLE FOR EACH DECODER

LOGIC SYMBOL

1i i

I T1i

DECDDER a

DECOOER b

00010203

00 01 02 03

E Ao Al

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9321 PC, 93L21PC

Ceramic
DIP (0)

A

9321 DC, 93L21DC

9321 OM, 93L21DM

68

Flatpak
(F)

A

9321 FC, 93L21 FC

9321 FM, 93L21 FM

4L

98

E Ao

Al

r! ! r XX!!
Vee = Pin 16
Gnd = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

Ea,

Enable Inputs (Active LOW)
Eb
Aoa, A1a, AOb, A1b Address Inputs
Ooa-03a}
Decoder Outputs (Active LOW)
OOb-03b

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0

0.5/0.25
0.5/0.25

20/10

6-64

10/5.0
(3.0)

21
FUNCTIONAL DESCRIPTION - The '21 consists of two separate decoders each designed to accept two binary
weighted inputs and provide four mutually exclusive active LOW outputs as shown in the logic symbol. Each
decoder can be used as a 4-output demultiplexer by using the enable as a data input.

TRUTH TABLE
(EACH DECODER)
INPUTS

OUTPUTS

E

Ao

A1

00

01

02

03

L
L
L
L
H

L
H
L
H
X

L
L
H
H
X

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

LOGIC DIAGRAM
000

00.

Ao.

01a

Ao.

Olb

A"

02a

A,.

02.

03a

C3b

E.

E.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

Max
50

TA

PARAMETER

UNITS

CONDITIONS

Max
13.2

rnA

Vee = Max

= +25°C (See Section 3 for waveforms and
93XX

SYMBOL

93L
Min

93L

CL = 15 pF CL = 15 pF
Min

Max

load configurations)

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propaa,ation Delay
An to On

20
21

50
65

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
E'to On

14
18

40
52

ns

Figs. 3-1, 3-5

6-65

22
CONNECTION DIAGRAM
PINOUT A

9322
93L22
QUAD 2-INPUT MULTIPLEXER
sIT
DESCRIPTION - The '22 quad 2-input digital multiplexers consist of four
multiplexing circuits with common select and enable logic; each circuit contains two inputs and one output.

• MULTIFUNCTION CAPABILITY
• ON-CHIP SELECT LOGIC DECODING
• FULLY BUFFERED OUTPUTS

-

1iI Vee

10·tI

illl E

h.11:

Imloe

Za[!

IEl he

lab

11

hb

I!

~Ze

rrn

~hd
~Zd

zblI
GND[!

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V, ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9322PC, 93L22PC

Ceramic
DIP .~~----~--+---~~-+----~--+---~r-I

E--~~----------~~~t+----~H---~~--~NHr-~rr----~H--,

6-67

lOa

22
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

los

Output Short Circuit Current

lee

Power Supply Current

AG CHARACTERISTICS: Vee

93XX

Min

Max

-20

-70

93l

Min

mA

47

13.2

CONDITIONS

mA

= Max,
Vee = Max

Vee

= +5.0 V, TA = +25°C (See Section 3 for waveforms and
93XX

SYMBOL

UNITS

Max

PARAMETER

Max

load configurations)

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
S to Zn

23
27

36
49

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
10 or i1 to Zn

14
14

22
30

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
Eto Zn

20
21

27
27

ns

Figs. 3-1, 3-4

6-6~

=0V

93l

CL = 15 pF CL
RL = 400 n
Min

VOUT

24
CONNECTION DIAGRAM
PINOUT A

9324
93L24
5-BIT COMPARATOR
DESCRIPTION - The '24 expandable .comparators provide comparison between two S-bit words and give three outputs - "less than", "greater than" and
"equal to". A HIGH on the active LOW Enable Input forces all three outputs
LOW.

• THREE SEPARATE OUTPUTS-A< B, A > B, A = B
• EASILY EXPANDABLE
• ACTIVE LOW ENABLE INPUT

EO:

SA >B

Bo[I

SA~B

B,[~

tmAo

B'[1

tmA1

B.er:

PIN
PKGS

OUT

GNO[!

COMMERCIAL GRADE

MILITARY GRADE

Vee = +S.O V ±S%,
TA = O°C to +70°C

Vee = +S.O V ±10%,
TA = -SsoC to +12SoC

~vcc

A8

A Greater than 8 Output (Active HIGH)

20/10

A=8

A Equal to 8 Output (Active HIGH)

20/10

Ao-A4

6-69

24
FUNCTIONAL DESCRIPTION - The '24 5-bit comparators use combinational circuitry to directly generate "A
greater than Bn and "A less than Bn outputs. As evident from the logic diagram, these outputs are generated in
only three gate delays. The "A equals Bn output is generated in one additional gate delay by decoding the "A
neither less than nor greater than Bn condition with a NOR gate. All three outputs are activated by the active
LOW Enable Input @.
Tying the A > B output from one device into an A input on another device and the A < B output into the
corresponding B input permits easy expansion.
The AI, and B4 inputs are the most significant inputs and Afj, So the least significant. Thus if A4 isHIGH and B4 is
LOW, the A > B output will be HIGH regardless of all other inputs except E.

LOGIC SYMBOL

1

--B

A=B

L
L
L
H

L
L
H
L

L
H
L
L

X
X
Word A = Word B
Word A > Word B
Word B > Word A

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

6-70

24
lOGIC DIAGRAM
A.

-

n

'7

JD
B.

~

r)
L-

~:n

-

r-

AD

E

'7

r"

A1

A2

A3

07

FD7

~D

A B

tPLH
tPHL

A2 to A < B

tPLH
tPHL

A2 to A = B

A=B

Propagation Delay
Propagation Delay
Propagation Delay

Max

mA

Vee

= Max

3 for waveforms and load configurations)

93l

93XX
SYMBOL

CONDITIONS

Max

81

V, TA

UNITS

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

14
14

32
35

ns

Figs. 3-1, 3-4

25
22

54
75

ns

Figs. 3-1, 3-5

26
21

70
77

ns

Figs. 3-1, 3-4

30
32

100
102

ns

Figs. 3-1, 3-20

6-71

•

28
CONNECTION DIAGRAM
PINOUT A

9328
93L28
DUAL 8-BIT SHIFT REGISTER
DESCRIPTION - The '28 is a high speed serial storage element providing
16 bits of storage in the form of two 8-bit registers. The multifunctional
capability of this device is provided by several features: 1) additional gating
is provided at the input to both shift registers so that the input is easily
multiplexed between two sources; 2) the clock of each register may be
provided separately or together; 3) both the true and complementary outputs
are provided from each 8-bit register, and both registers may be master
cleared from a common input.

MR[I

ad}:
07

II

N

• 2-INPUT MULTIPLEXER PROVIDED AT DATA INPUT
OF EACH REGISTER
• GATED CLOCK INPUT CIRCUITRY
• BOTH TRUE AND COMPLEMENTARY OUTPUTS PROVIDED FROM
lAST BIT OF EACH REGISTER
• ASYNCHRONOUS MASTER RESET COMMON TO BOTH REGISTERS

a:

...'"

In

srI

-

~vcc
~Q7
~07

m

c;

D,[I

'"a:

DolI

~DO

cPU:

~cP

GND[I

~~P
9 COM

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

9328PC, 93L28PC

Ceramic
DIP (0)

A

9328DC, 93L28DC

9328DM, 93L28DM

68

Flatpak
(F)

A

9328FC, 93L28FC

9328FM, 93L28FM

4L

98

INPUT lOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

Q7

Data Select Input
Data Inputs
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
Master Reset Input (Active LOW)
Last Stage Output

07

Complementary Output

S
00,01
CP

-MR

93XX (U.l.)
HIGH/LOW

DESCRIPTION

6-72

93l (U.l.)
HIGH/LOW

2.0/2.0
1.0/1.0

1.0/0.5
0.5/0.25

3.0/3.0
1.5/1.5
1.0/1.0
20/10

1.5/0.75
0.75/0.375
0.5/0.25
10/5.0
(3.0)
10/5.0
(3.0)

20/10

:»

~s iiiCl
....
~D' :»m
-

28
FUNCTIONAL DESCRIPTION - The two 8-bit shift registers have a common clock input (pin 9) and separate
clock inputs (pins 10 and 7l. The clocking of each register is controlled by the OR function of the separate and
the common clock input. Each register is composed of eight clocked RS master/slave flip-flops and a number
of gates. The clock OR gate drives the eight clock inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW, the slave latches are steady, but data can enter the
master latches via the Rand S input. During the first LOW-to-HIGH transition of either, or both simultaneously,
of the two clock inputs, the data inputs (R and S) are inhibited so that a later change in input data will not affect
the master; then the now trapped information in the master is transferred to the slave. When the transfer is
complete, both the master and the slave are steady as long as either or both clock inputs remain HIGH. During
the HIGH-to-LOW transition of the last remaining HIGH clock input, the transfer path from master to slave is
inhibited first, leaving the slave steady in its present state. The data inputs (R and S) are enabled sothat new data
can enter th~ master. Either of the clock inputs can be used as clock inhibit inputs by applying a logic HIGH
signal. Each 8-bit shift register has a 2-input multiplexer in front of the serial data input. The two data inputs Do
and Dl are controlled by the data select input (S) following the Boolean expression:
Serial data in: SD = SDo

+ SDl

An asynchronous master reset is provided which, when activated by a LOW logic level, will clear al116 stages
independently of any other input signal.
LOGIC SYMBOL
13

10-----\
9--HL~

11

12

Do

0,

cp

SHIFT SELECT TABLE
07

14

07

15

INPUTS

MR

4

6

5

3

07

2

Do

Dl

L
L
H
H

L
H
X
X

X
X
L
H

Q7 (t n + 8)

L
H
L
H

H ~ HIGH Vollage Level
L ~ LOW Vollage Level
X "'" Immaterial
n + 8 ~ Indicales slale after eighl clock pulse

0,

07

S

OUTPUT

MR

Vce

= Pin 16
= Pin 8

GND

LOGIC DIAGRAM

Do
S
MR-------~~--4-----4---~---~---4-----~--~~-----4--------J

6-73

28
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

93XX
Min

lee

Power Supply Current

Max

93l
Min

UNITS

25.3

77

CONDITIONS

Max
rnA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)

93XX
SYMBOL

PARAMETER

93l

CL = 15 pF CL = 15 pF
RL = 400 n
Min

Max

'f max

Maximum Shift Right Frequency

20

tpLH
tpHL

Propagation Delay
CP to 07 or elY

20
35

tpHL

Propagation Delay MR to 07

50

Min

UNITS

CONDITIONS

Max

5.0

MHz

Figs. 3-1, 3-8

45
80

ns

Figs. 3-1, 3-8

110

ns

Figs. 3-1, 3-16

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
SYMBOL

PARAMETER

93XX
Min

Max

93l
Min

UNITS

ts (H)
ts (U

Setup Time HIGH or LOW
Dn to CP

20
20

30
30

ns

th (H)
th (U

Hold Time HIGH or LOW
Dn to CP

0
0

0
0

ns

tw (H)
tw (U

Clock Pulse Width HIGH
or LOW

25
25

55
55

ns

tw (U

MR Pulse Width with CP HIGH

30

60

ns

tw (U

MR Pulse Width with CP LOW

40

70

ns

tree

Recovery Time MR to CP

33

Fig. 3-6

ns

6-74

CONDITIONS

Max

Fig. 3-8
Fig. 3-16
Fig. 3-16

34
CONNECTION DIAGRAMS
PINOUT A

9334
93L34

-

AoU

8-BIT ADDRESSABLE LATCH

~VC;(

~ct

All2

~E
~D
~O7

A2[I

ooG
0,1}

S06

02[!
DESCRIPTION - The '34 is an 8-bit addressable latch designed for general
purpose storage applications in digital systems. It is a multifunctional device
capable of storing single line data in eight addressable latches, and being
a one-of-eight decoder and demultiplexer with active level HIGH outputs.
The device also incorporates an active LOW common clear for resetting all
latches, as well as, an active LOW enable.

•
•
•
•
•
•

SERIAL TO PARALLEL CAPABILITY
EIGHT BITS OF STORAGE WITH OUTPUT OF EACH BIT AVAILABLE
RANDOM (ADDRESSABLE) DATA ENTRY
ACTIVE HIGH DEMUL TIPLEXING OR DECODING CAPABILITY
EASILY EXPANDABLE
COMMON CONDITIONAL CLEAR

03[!

~O5

GNOI:! .

~O4

LOGIC SYMBOL

I
r

1r
0

E

1 - AG

ORDERING CODE: See Section 9

2 - A,

PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Plastic
DIP(P)

A

9334PC, 93L34PC

Ceramic
DIP (0)

A

9334DC, 93L34DC

Flatpak
(F)

A

9334FC, 93L34FC

PKG
TYPE

3 - A2
CL 00 0, 02 03 04

as

06 07

Y I I I I IT TT

15 4

5

6

7

9 10 11 12

98
9334DM, 93L34DM
9334FM, 93L34FM

68
4L

Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-A3
D

E
CL

00-07

DESCRIPTION
Address Inputs
Data Input
Enable Input (Active LOW)
Clear Input (Active LOW)
Parallel Latch Outputs

6-75

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

1.0/1.0
1.0/1.0
1.5/1.5
1.0/1.0
18/6.0

0.5/0.25
0.5/0.25
0.75/0.38
0.5/0.25
10/5.0
(3.0)

34
FUNCTIONAL DESCRIPTION - The '34 has four modes of operation which are shown in the Mode Select
Table. I n the addressable latch mode, data on the data line( D) is written into the addressed latch. The addressed
latch will follow the Data input with all non-addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the data or address inputs. To eliminate
the possibility of entering erroneous data into the latches, the Enable should be held HIGH while the Address
lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output will foil ow the state of
the D input with all other outputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the
address and data inputs. When operating the '34 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should only be done while in the memory
mode.
MODE SELECT TABLE
E

CL

L
H
L
H

H
H
L
L

MODE
Addressable Latch
Memory
Active HIGH 8-Channel Demultiplexer
Clear

TRUTH TABLE
OUTPUTS

INPUTS

MODE

CL

E

Ao

A1

A2

00

01

02

03

04

Os

06

07

L
L
L
L

H
L
L
L

X
L
H
L

X
L
L
H

X
L
L
L

L
D
L
L

L
L
D
L

L
L
L
D

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L

L

H

H

H

L

L

L

L

L

L

L

D

H

H

X

X

X

Ot-1

Ot-1

Ot-1

Ot-1

Ot-l

Ot-l

Ot-l

Ot-1

Memory

H
H
H

L
L
L

L
H
L

L
L
H

L
L
L

D
Ot-l
Ot-l

Ot-1
Ot-l
Ot-l

Addressable
Latch

H

L

H

H

H

Clear
Demultiplex

·· ·· ·· ·· ·· ·· .. ·· ·· .. ·· ·· ··
Ot-l
D
Ot-l

Ot-l
Ot-l
D

Ot-l
Ot-l
Ot-l

Ot-1 Ot-l
= LOW Voltage Level

Ot-l

Ot-l
Ot-l
Ot-l

Ot-l
Ot-l
Ot-l

Ot-l
Ot-l
Ot-l

Ot-l Ot-l
= Immaterial

Ot-l

· · · · · ·· .. ·· ·· .. ·· · ·
· ·
· · · · · 01-1

H

= HIGH

Voltage Level

L

x

0,-1

D

= Previous

LOGIC DIAGRAM
E

0

Ci.

Ao

1

Qs

Qo

6-76

Q6

Output State

34
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
93XX

PARAMETER

SYMBOL

Min
lee

Power Supply Current

AC CHARACTERISTICS: Vee

I
I

= +5.0 V,

XM
XC

TA

Max

93l
Min

86
86

21
26

= +25°C (See Section
93XX

PARAMETER

SYMBOL

= 15 pF

CL

Min

CONDITIONS

rnA

Vee

= Max

3 for waveforms and load configurations)

93l
CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tpHL

E to On

23
24

45
42

ns

Figs. 3-1, 3-9

tPLH
tpHL

Propagation Delay
D to On

28
24

65
45

ns

Figs. 3-1, 3-5

tPLH
tpHL

Propagation Delay
An to On

35
35

66
66

ns

Figs. 3-1, 3-20

40

55

ns

Figs. 3-1, 3-10

tPHL

Propagation Delay

Max

UNITS

Max

Propagation Delay
CL to On

AC OPERATING REQUIREMENTS: Vee
SYMBOL

PARAMETER

= +5.0 V,

TA

93XX
Min

E
D to E

ts (H)

Setup Time HIGH, D to

th (H)

Hold Time HIGH,

ts (U

= +25°C
Max

93l
Min

UNITS

20

45

ns

0

-5.0

ns

Setup Time LOW, D to E

17

45

ns

th (U

Hold Time LOW, D to E

0

-7.0

ns

ts (H)
ts(U

Setup Time HIGH or LOW
An to E

5.0
5.0

10
10

ns

tw (U

E Pulse Width LOW

17

26

ns

tw (U

CL Pulse Width LOW

35

ns

6-77

CONDITIONS

Max

Fig. 3-13

Fig. 3-21
Fig. 3-17

38
CONNECTION DIAGRAM
PINOUT A

9338
93138
a-BIT MULTIPLE PORT REGISTER
DESCRIPTION - The '38 is an 8-bit multiple port register designed for high
speed random access memory applications where the ability to simultaneously read and write is desirable. A common use would be as a register
bank in a three address computer. Data can be written into anyone of the
eight bits and read from any two of the eight bits simultaneously. The circuit
uses TTL technology and is compatible with all TTL families.

• MASTER/SLAVE OPERATION PERMITTING SIMULTANEOUS
WRITE/READ WITHOUT RACE PROBLEMS
• SIMULTANEOUSLY READ TWO BITS AND WRITE ONE BIT IN ANY ONE
OF EIGHT BIT POSITIONS
• READILY EXPANDABLE TO ALLOW FOR LARGER WORD SIZES

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP (Pl

A

9338PC, 93L38PC

Ceramic
DIP (0)

A

9338DC, 93L38DC

9338DM, 93L38DM

78

Flatpak
(f)

A

9338FC, 93L38FC

9338FM, 93L38FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

/>(J-A2

DESCRIPTION

CP
SLE
ZB

Write Address Inputs
Data Input
8 Read Address Inputs
C Read Address Inputs
Clock Pulse Input (Active Rising Edge)
Slave Enable Input (Active LOW)
8 Output

Zc

C Output

DA

Bo-8:2

Q)-c:!

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

0.67/0.68
0.6710.68
0.67/0.68
0.6710.68
0.67/0.68
0.67/0.68
20/10

0.33/0.17
0.33/0.17
0.33/0.17
0.33/0.17
0.33/0.17
0.33/0.17
10/5.0
(3.0)
10/5.0
(3.0)

20/10

6-78

38
LOGIC SYMBOL

15 14 13 1

12

11

2

3

9

7

6

Ao A1 A2 Bo B1 B2 Co C, C2
CP
DA

10 --0 SLE

4

Vee = Pin 16
GND = Pin 8

LOGIC DIAGRAM

A2-{>~;=~~~iilliii~i~i~i~i1f=-=--=:?~'o-'1~----

Ao-{>·_------

-~J----SLE

Co~~~---~
C,

C2

-{>.<>-T--------I
---1i>c>--f--------l
Zc

ZB

6-79

•

38
FUNCTIONAL DESCRIPTION - The '38 8-bit multiple port register can be considered a 1-bit slice of eight high
speed working registers. Data can be written into anyone and read from any two of the eight locations
simultaneously. Master/slave operation eliminates all race problems associated with simultaneous read/write
activity from the same location. When the clock input (CP) is LOW data applied to the data input line(OA) enters
the selected master. This selection is accomplished by coding the three write input select lines (Ao - A2)
appropriately. Data is stored synchronously with the rising edge of the clock pulse.
The information for each of the two slaved (output) latches is selected by two sets of read address inputs (60 -82
and Co - C2). The information enters the slave while the clock is HIGH and is stored while the clock is LOW. If
Slave Enable is LOW (SLE), the slave latches are continuously enabled. The signals are available on the output
pins (ZB and Zc). The input bit selection and the two output bit selections can be accomplished independently or
simultaneously. The data flows into the device, is demultiplexed according to the state of the write address Ii nes
and is clocked into the selected latch. The eight latches function as masters and store the input data. The two
output latches are slaves and hold the data during the read operation. The state of each slave is determined by
the state of the master selected by its associated set of read address inputs.
The method of parallel expansion is shown in Figure a. One '38 is needed for each bit of the required word
length. The read and write input lines should be connected in common on all of the devices. This register
configuration provides two words of n-bits each at one time, where n devices are connected in parallel.

CLOCK

INPUT
{
A SELECT

b
'-- Ao

-

Da

'-- Ao

A

A1

-

9338
8-BIT
B1 MULTIPLE
PORT
B2 REGISTER

B

A1

9338
a-BIT
B1 MULTIPLE
PORT
B2 REGISTER

Bo

Bo

Co

Co

c,

, . - - C,

r - C2

CP SLE

Da

A2

A2

-

b

CP SLE

ZB

r - C2

Ze

ZB

Ze

B OUTPUT {
SELECT

C OUTPUT {
SELECT

I

I

Ca Cb
C WORD

B WORD

Fig. a

Parallel Expansion

6-80

• ••

38
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

los

Output Short Circuit Current

lee

Power Supply Current

93XX

93l

UNITS

CONDITIONS

Min

Max

Min

Max

-10

-70

-2.5

-25

mA

Vee = Max

33

mA

Vee = Max

135

AC CHARACTERISTICS: Vee = +5.0 V. TA = +25°C (See Section 3 for waveforms and load configurations)

93XX
SYMBOL

PARAMETER

93l

CL = 15 pF CL = 15 pF
Min

UNITS

CONDITIONS

Min

Max

tPLH
tPHL

Propagation Delay
Bn or Cn to Zn

13
18

40
35

Max
68
95

ns

Figs.3-1. 3-20

.tPLH
tPHL

Propagation Delay
DA to Zn

25
25

45
50

70
92

ns

Figs. 3-1.3-5

tPLH
tPHL

Propagation Delay
CP to Zn

18
13

35
30

65
57

ns

Figs. 3-1.3-8

AC OPERATING REQUIREMENTS: Vee = +5.0 V. TA = +25°C
SYMBOL

PARAMETER

93XX
Min

ts (H)
ts(U

Setup Time HIGH or lOW
DA to CP

th (H)
th (U

Hold Time HIGH or lOW
DA to CP

ts (H)
ts(U

Max

93l
Min

UNITS

20
12

30
22

ns

0
-8.0

0
-4.0

ns

Setup Time HIGH or lOW
An to CP

10
10

0
0

ns

th (H)
th (U

Hold Time HIGH or LOW
An to CP

0
0

0
0

ns

tw (H)
tw (U

CP Pulse Width HIGH or LOW

23
13

40
30

ns

6-81

CONDITIONS

Max

Fig. 3-6

Fig. 3-21

Fig. 3-8

•

40
CONNECTION DIAGRAM
PINOUT A

9340
4-BIT ARITHMETIC LOGIC UNIT
(With Carry Lookaheadl
DESCRIPTION - The '40 is a high speed arithmetic logic unit with full onchip carry lookahead circuitry. It can perform the arithmetic operations add
or subtractin parallel, or any of six logic functions on two 4-bit binary words.
The internal carry lookahead provides either a ripple carry output or carry
lookahead outputs. An internal carry input network accepts carry lookahead
outputs from up to three other packages producing a 16-bit full carry lookahead ALU without additional gates. Ripple carries can be used between additional blocks of 12 bits to further expand the word length.

• MULTIFUNCTION CAPABILITY
TWO ARITHMETIC OPERATIONS-ADD, SUBTRACT
SIX LOGIC FUNCTIONS - A EX OR B, A AND B, PLUS FOUR OTHERS
• ADD TWO 4-BIT WORDS IN 23 ns TYPICAL
• SUBTRACT TWO 4-BIT WORDS IN 28 ns
• LOOKAHEAD CARRY INPUT AND OUTPUT NETWORKS ON-CHIP
• EASILY EXPANDABLE TO LONGER WORD LENGTHS
• TYPICAL POWER DISSIPATION OF 425 mW

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE
Vee

= +5.0

MILITARY GRADE

PKG

Vee = +5.0 V ±10%,

V ±5%,

TA = O°C to +70°C

TYPE

TA = -55°C to +125°C

Plastic
DIP(P)

A

9340PC

Ceramic
DIP (D)

A

9340DC

9340DM

6N

Flatpak
(F)

A

9340FC

9340FM

4M

9N

LOGIC SYMBOL

II 11 11 11

AO Bo

A1 81

A2 82

A3 83

1
COE

14--0 CG,
13--0 CP,
CO/CG 0---22

16--0 CG2
15--0 CP2

CP p-23

17--0 CG3
2 - So
3-51
Fo

Y

18

F1

Y

19

F2

Y

20

6-82

F3

y

21

Vce

= Pin 24

GND

= Pin

12

40
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

AfJ-A3}

DESCRIPTION

93XX (U.L.)

HIGH/LOW

80-B3

Operand Inputs (Active LOW)

3.0/3.0

SO, Sl
CG1

Mode Select Inputs
Carry Generate Input from immediately
preceeding stage (Active LOW)
Carry Propagate Input from immediately
preceeding stage (Active LOW)
Carry Generate Input from second
preceeding stage (Active LOW>
Carry Propagate Input from second
preceeding stage (Active LOW)
Carry Generate Input. from third
preceeding stage (Active LOW)
Carry Out Enable Input
Function Outputs (Active LOW)
Carry Out/Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW>

1.0/1.0
3.0/3.0

CP1
CG2

1.0/1.0
2.0/2.0
1.0/1.0
1.0/1.0
1.5/1.5
20110

20/10
20/10

•

LOGIC DIAGRAM

CGl
CPl

CO/CG

CG,

CP2

CG3
Cii

So

Sl---{>

6-83

40
FUNCTIONAL DESCRIPTION - The '40 accepts two 4-bit words, AD, A" A2, As and 80, 8" 82, lb, and
produces a 4-bit output, Fe, F" F2, Fa. The output function is determined by the states on the control lines So
and S,. The inputs and outputs of the '40 may be considered to be active LOWor active HIGH. Logic equivalents
for four representations of the '40 are shown in Figure a, b, c, and d.
The add and subtract operations are performed on the entire word, with carries or borrows propagated
between bits of different weight. The arithmetic may be performed in 1's complement, 2's complement, or signmagnitude notation. In the logic modes, carries are inhibited and the device acts like four gates as shown.
To achieve high speed operation, the '40 is designed to be used in a carry lookahead system. Full carry
lookahead is used inside the device to propagate carries between bits. Carry lookahead fu nctions over the 4-bit
block are available as outputs. These outputs are labeled CO/CG (Carry Out/Carry Generate) and CP (Carry
Propagate) on the logic symbol. The carry in to the device is formed from a set of Carry Generate and Carry
Propagate inputs (equation 1) so that three '40's can be interconnected without any additional gates to form a
12-bit full carry lookahead ALU with a carry in. The pin labeled COE (Carry Out Enable) controls the CO/CG
output according to equation 2. When COE is HIGH, CO/CG becomes a Carry Out which can be used to ripple
carries between blocks of 12 bits. The CG, input can be used for a ripple carry input, since this signal is
sufficient to produce a carry in.
EQUATION:
(1) (CG,) + (CP,) (CG2) + (CP,) (CF':!) (CG3)
(2) CO/CG = (CG) + (CP) (Cin) (COE)

= Cin (internal)

FUNCTION TABLES FOR LOGIC EQUIVALENTS OF THE '40
Note that when the input operands are defined as active HIGH, the carry lookahead inputs and outputs are not
formally carry generate and carry propagate. Consequently, these pins have been relabled CX and CY in the
active HIGH cases. However, the signals are connected in the same manner as CG and CPo

ACTIVE LOW OPERANDS

l! 11 11 11

Au Bo
14~

CG,

13~

cp,

Al 8,

Ao B2

Ao B3

1

OPERATION

So

S,

L

L

A SUBTRACT B

H

L

AADDB

L

H

A EX OR B

H

H

AAND B

COE

CO/CG 0-22

16-0 CG2
15~

CONTROL
INPUTS

CP2
CP 0-23

17--C CG3
2 - So

3 - 5,
Fo

F,

F2

F3

! ! ! !
Vee = Pin 24
GND = Pin 12

EQUIVALENT LOGIC

~
~

6-84

ADD

~
~

1: o----t

1:

H = HIGH Voltage Level
L = LOW Voltage Level

Fig. a

SUB

ca

40
FUNCTION TABLES FOR LOGIC EQUIVALENTS OF THE '40 (Cont'ql
ACTIVE HIGH OPERANDS
7 11

6 10

5

9

4

CONTROL
INPUTS

8

OPERATION

So

S1

L

L

A SUBTRACT B

H

L

AADD B

L

H

A EQUIV B

H

H

AOR B

14
13

CY,

16

CX2

15

CY2

17

CX,

CX

22

CY

23

So

5,

18

19

20

21

Vee = Pin 24
GND = Pin 12

EQUIVALENT LOGIC

=t 8~ HSUB

ADD

I:
I:

)[)o

D

'I
'I

Fig. b
ACTIVE LOW OPERANDS
WITH INVERTED B
7 11

6 10

5

9

4

CONTROL
INPUTS

8

14--0 CG,

13
16

CG/CO

22

CP

23

S1

L

L

AADD B

H

L

A SUBTRACT B

L

H

A EQUIV B

H

H

AANDB

15
17

OPERATION

So

So
S,

Fo

F,

18

19

y

Y

21

20

Vee = Pin 24
GND = Pin 12

14

CX,

13

CY,

16

CX2

15

CY2

17

CX,

6 10

5

9

4

CONTROL
INPUTS

8

CX

22

CY

23

OPERATION

So

S1

L

L

AADD B

H

L

A SUBTRACT B

L

H

A EX OR B

H

H

AORB

So

18

19

20

Vee = Pin 24
GND = Pin 12

=t E+=t E+ADD

SUB

~I:

'10-1: 00--40)Do

Fig. c

ACTIVE HIGH OPERANDS
WITH INVERTED B
7 11

EQUIVALENT LOGIC

21

Fig. d

6-85

EQUIVALENT LOGIC

=t 8=t EtADD

SUB

~I:
~I:

lD

D

'I
'I

40
DC CHARCTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise speci.fied)
SYMBOL

93XX

PARAMETER

Min
lee

Power Supply Current

CONDITIONS

UNITS

Max

~

135
146

XC

rnA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
93XX
SYMBOL

PARAMETER

CL = 15 pF
Min

UNITS

CONDITIONS

Max

So, CG1, CP, 81, 8:!=4.5V

tpLH
tPHL

Propagation Delay
Add Mode, So to F3

30
30

ns

51, Ao -AJ, ih = Gnd
Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay for
Subtract Mode, So to F3

37
32

ns

CG1, CP1, 83 = 4.5 V; So,
51, Ao - As, 81,82 = Gnd
Figs. 3-1', 3-4

tPLH
tPHL

Propagation_Dela~
Add Mode, 80 to CO/CG

20
20

ns

So, CG1, CP1,
81 - 83 = 4.5 V; 51, COE,
Ao - A1 = Gnd
Figs. 3-1, 3-5

tPLH
tPHL

Propagation Del!y for_ _ _
Subtract Mode, 80 to CO/CG

25
22

ns

CG1, CP = 4.5 V; So, 51,
COE, Ao - As, 81 - 83 = Gnd
Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay fQ_r_ _
Either Mode, CG3 to CO/CG

19
19

ns

Ao - As = 4.5 V; 51,
Bo - I3a CP1, CP2 = Gnd

ns

So, CG1, CG2, 83,
As = 4.5 V; 51,
Bo - B2, CP1, CP2 = Gnd
Figs. 3-1, 3-5

So, CG1, CG2, COE,
Figs. 3-1, 3-5

tPLH
tPHL

31
29

Propagation Delay fo!..
Either Mode, CG3 to F3

6-86

Ao -

41
CONNECTION DIAGRAM
PINOUT A

9341
93L41
93S41
4-BIT ARITHMETIC LOGIC UNIT
DESCRIPTION-The '41 4-bit arithmetic logic units can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations; the Add and Subtract modes are the most important. The '41 is a pin
replacement for the 54174181 .
• PROVIDE 16 OPERATIONS
ADD,SUBTRACT,COMPARE,DOUBLE
TWELVE OTHER ARITHMETIC OPERATIONS
• PROVIDE ALL 16 LOGIC OPERATIONS OF TWO VARIABLES
EXCLUSIVE-OR, COMPARE, AND NAND, OR, NOR, PLUS
TEN OTHER LOGIC OPERATIONS

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
OIP(P)

A

9341 PC, 93L41PC
93S41PC

Ceramic
DIP (D)

A

9341 ~C, 93L41DC
93S41DC

9341DM, 93L41 OM
93S41OM

6N

Flatpak
(F)

A

9341 FC, 93L41 FC
93S41FC

9341 FM, 93L41 FM
93S41FM

4M

9N

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

93XX (U.L.)
HIGH/LOW

93L (U.L.)
HIGH/LOW

93S (U.L.)
HIGH/LOW

3.0/3.0
4.0/4.0
1.0/1.0
5.0/5.0
20/10

1.5/0.75
2.0/1.0
0.5/0.25
2.5/1.25
10/5.0
(3.m
OC*/5.0
(3.m
10/5.0
(3.m
10/5.0
(3.m
10/5.0
(3.m

3.75/3.75
5.0/5.0
1.25/1.25
7.517.5
25/12.5

Ao-Aa,80-B3
SO-S3
M
Cn
Fo-F3

Operand Inputs (Active LOW)
Function Select Inputs
Mode Control Input
Carry Input
Funct10n Outputs (Active LOW)

A=B

Comparator Output

G

Carry Generator Output (Active LOW)

20/10

p

Carry Propagate Output (Active LOW)

20/10

Carry Output

20/10

Cn

+4

OC*/10

'OC-Open Collector

6-87

OC*/12.5
25/12.5
25/12.5
25/12.5

41
FUNCTIONAL DESCRIPTION - The '41 Is a4-bit high speed parallel arithmetic logic unit (ALU>. Controlled by
the four Function Select inputs (So- S3) and the Mode Control input (M), it can perform all the 16 possible
operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function Table
below lists these operations.
When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic
operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the
device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry
lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead
betweeen packages using the signals P (Carry Propagate) and G(Carry Generate>. P and G are not affected by
carry in. When speed requirements are not stringent, the '41 can be used in a simple ripple carry mode by
connecting the Carry output (C n + 4) signal to the Carry input (C n) of the next unit. For super high speed
operation the Schottky '41 should be used in conjunction with the '42 carry lookahead circuit.
The A = B output from the '41 goes HIGH when all four Fn outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract mode. The A = B output is open-collector and can be
wired-AND with the other A= B outputs to give a comparison for more than four bits. TheA= B signal can also
be used with the Cn + 4 signal to indicate A > B and A < B.
The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry
adds a one to each operation. Thus select code LHHL generates A minus B minus 1 (2s complement notation)
without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed
by complementary addition (1 s complement), a carry out means borrow; thus a carry is generated when there is
no underflow and no carry is generated when there is underflow.
As indicated the '41 can be used with either active LOW inputs producing active LOW outputs or with active
HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to
the operands labled inside the logic symbol.
FUNCTION TABLE
MODE SELECT
INPUTS

ACTIVE LOW INPUTS
& OUTPUTS
LOGIC

ACTIVE HIGH INPUTS
& OUTPUTS

S3

S2

S1

So (M=H) (M = U (Cn = U

LOGIC
(M=H)

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

A
AB
A+S
Logic 1

A minus 1
AB minus 1
AS minus 1
minus 1

A
A
A+S
A+B
AB
A+S
Logic 0 minus 1

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

A+S
S
A€I)S
A+B

A plus (A +
AB plus (A + S)
A minus B minus 1
A+S

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

AB
A€I)B
B
A+B

A plus (A + B)
A plus B
AS plus (A + B)
A+B

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

Logic 0 A plus A"
AS
AB plus A
AB
AS minus A
A
A

ARITHMETIC""

s"l

"Each bit is shifted to the next more significant position
"Arithmetic operations expressed in 28 complement notation
H = HIGH Voltage Level
L = LOW Voltage Level

6-88

AB

ARITHMETIC""
(M = U (C n = H)

A€I)B
AS

A plus AS
(A + B) plus AS
A minus B minus 1
AS minus 1

A+B
A €I) B
B
AB

A plus AB
A plus B
(A + S) plus AB
AB minus 1

Logic 1
A+S
A+B
A

A plus A"
(A + B) plus A
(A + S) plus A
A minus 1

B

41
LOGIC SYMBOLS
ACTIVE LOW OPERANDS
2

7

Cn

8

M

6

So

5

S,

4

S2

3

S3

ACTIVE HIGH OPERANDS
2

1 23 22 21 20 19 18

Cn

+ 4

1

2322 21 20 19 18

7

16

16

8

M

A =8

14

6

So

G

17

5

SI

17

P

15

3

S3

15

14

Fl

9

10

11

9

13

10

11

13

LOGIC DIAGRAM
en

M

Ao

80

ii,

ii3

6-89

41
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER

Min

lee

Power 5upply Current

XM
XC

lee

Power 5upply Current

XM
XC

lee

Power 5upply Current

Max

93l

Min

93S

Max

Min

UNITS

CONDITIONS

Max

127
140

125
140

mA

Vee = Max
Cn,Bo-Ba=Gnd
All Other
Inputs = 4.5 V

135
150

135
150

mA

Vee = Max
M, So-53=4.5V
All Other
Inputs = Gnd

mA

Vee = Max

36

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (5ee 5ection 3 for waveforms and load configurations)
93XX
SYMBOL

PARAMETER

93l

93S

CL = 15 pF CL = 15 pF CL = 15 pF
RL=400n
RL = 280 n
Min

Max

Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Cn tOCn +4

16
17

51
22

12
12

ns

M= Gnd
Figs. 3-1, 3-4
Tables I & II

tPLH
tPHL

Propagation Delay
Cn to F

17
17

37
42

12
12

ns

M =Gnd
Figs. 3-1, 3-4
Table I

tPLH
tPHL

Propagation Delay
AnorentoG·

19
12

51
26

14
14

ns

M, 51, 52 = Gnd
50,53 = 4.5 V
Figs. 3-1, 3-5
Table I

tPLH
tPHL

Propagation Delay
An or en to G

22
17

50

43

15
15

ns

M, So, 53 = Gnd
51,52 = 4.5 V
Figs. 3-1,3-4, 3-5
Table II

tpLH
tPHL

Propagation Delay
AnOrBntoP

19
15

50
46

14
14

ns

M, 51, 52, = Gnd
So, 53, = 4.5 V
Figs. 3-1, 3-5
Table I

tPLH
tPHL

Propagation Delay
An or en to j5

21
21

38
63

15
15

ns

M, So, 53 = Gnd
51,52 = 4.5 V
Figs. 3-1,3-4,3-5
Table II

tPLH
tPHL

Propagation Delay
A or Bi to Fi

26
26

36

20
20

ns

M, 51, 53 = Gnd
So, 53 = 4.5 V
Figs. 3-1, 3-5
Table I

6-90

65

41
AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (Cont'd)
93XX
PARAMETER

SYMBOL

93l

93S

CL = 15 pF CL = 15 pF CL = 15 pF UNITS
RL=4000
RL = 280 0
Min

Max

Min

Max

Min

Max

ns

M, So, 83 = Gnd
81,82 = 4.5 V
Figs. 3-1,3-4,3-5
Table II

ns

M, 81, 82 = Gnd
80,83 = 4.5 V
Figs. 3-1, 3-5
Table I

25
25

ns

M, So, 83 = Gnd
81,82 = 4.5 V
Figs. 3-1,3-4,3-5
Table II

51
49

20
20

ns

M = 4.5 V
Figs. 3-1, 3-5
Table III

21
30

46
60

18.5
18.5

ns

M, 81, 82 = Gnd
80,83 = 4.5 V
Figs. 3-1, 3-4
Table I

25
30

60
58

23
23

ns

M, So, 83 = Gnd
81,82 = 4.5 V
Figs. 3-1,3-4,3-5
Table II

ns

M, So, 83 = Gnd
81,82 = 4.5 V
RL = 4000 to
5.0 V; Figs. 3-1,
3-4, 3-5; Table II

tPLH
tPHL

Propagation Delay
Ai or Bi to Fi

26
32

39
49

21
21

tPLH
tPHL

Propagation Delay
Ai or Bi to Fi + 1

29
25

56
62

24
24

tPLH
tpHL

Propagation Delay
Ai or Bi to Fi + 1

29
30

68
71

tPLH
tPHL

Propagation Delay
An or ~n to F

24
24

tPLH
tPHL

Propagation Delay
An or Bn to Cn + 1

tPLH
tPHL

Propagation Delay
An or Bn to Cn + 1

tPLH
tPHL

Propagation Delay
or Bn to A = B

An

CONDITIONS

40

68

42

72

6-91

23
23

•

41
FUNCTION INPUTS:

SUM MODE TEST TABLE I

SYMBOL

INPUT
UNDER
TEST

OTHER INPUT

So = 53 =

4.5 V. 51 = 52 = M = 0 V

OTHER DATA INPUTS

SAME BIT

OUTPUT
UNDER
TEST

APPLY
4.5 V

APPLY
GND

APPLY
4.5 V

APPLY
GND

Ai

Bi

None

Remaining
Aand B

en

Fi

Bi

Ai

None

en

Fi

Ai

Bi

None

en

Remaining
A and B

Fi

+ 1

tPLH
tPHL

Bi

Ai

None

en

Remaining
Aand B

Fi

+ 1

tPLH

A

B

None

None

Remaining
A and B. en

p

B

A

None

None

Remaining
A and B. en

p

A

None

B

Remaining
B

Remaining
A. en

G

B

None

A

Remaining

Remaining

B

A. en

G

tPLH
tPHL

A

None

B

Remaining

B

Remaining
A. en

en + 4

tPLH

B

None

A

Remaining
B

Remaining
A. en

en + 4

en

None

None

All

All

A

B

Any F
or en + 4

tPLH
tPHL
tpLH
tPHL
tPLH
tPHL

tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL

tPHL
tPLH
tPHL

6-92

R~maini!!g

A and B

41
DIFF MODE TEST TABLE II

SYMBOL

INPUT
UNDER
TEST

FUNCTION INPUTS: 81 = 52 = 4.5 V. 80 = 53 = M = 0 V

OTHER INPUT

OTHER DATA INPUTS

SAME BIT

OUTPUT
UNDER
TEST

APPLY
4.5 V

APPLY
GND

APPLY
4.5 V

APPLY
GND

A

None

B

Remaining

Remaining

A

B. Cn

B

A

None

Remaining

Remaining

A

B. Cn

Ai

None

Bi

Remaining

Remaining

B. Cn

A

BI

Ai

None

Remaining

Rem~ning

B. Cn

A

Fi + 1

A

None

B

None

Remaining

A and B. Cn

p

B

A

None

None

A- and B. Cn

A

B

None

None

A and B. Cn

B

None

A

None

tPLH
tPHL

A

None

B

Remaining

Remaining

A-

B.Cn

tPLH

B

A

None

Remaining

Remaining

A

B.Cn

A

B

None

None

A- and B. Cn

B

None

A

None

A and B. Cn

Cn + 4

Cn

None

None

None

Cn + 4

tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL

tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL

SYMBOL

tPLH
tPHL
tPLH
tPHL

Remaining
Remaining

A and B. Cn

Remaining
Remaining

B

I=i

FI+1

j5

G
G
A=B
A=B

Cn + 4

FUNCTION INPUTS: 81 = 82 = M = 4.5 V. 80 = 53 = 0 V

LOGIC MODE TEST TABLE III
INPUT
UNDER
TEST

All
Aand

Remaining

FI

OTHER INPUT

OTHER DATA INPUTS

SAME BIT
APPLY
4.5 V

APPLY
GND

APPLY
4.5 V

A

B

None

None

A and 9.

B

A

None

None

Aand B. Cn

6-93

APPLY
GND
Remaining
Cn
Remaining

OUTPUT
UNDER
TEST

AnyF
AnyF

42
CONNECTION DIAGRAM
PINOUT A

·9342

93942
CARRY LOOKAHEAD GENERATOR
DESCRIPTION - The '42 is a high speed lookahead carry generator. It is
generally used with the 9341 (54174181) 4-bit arithmetic logic unit to provide
high speed lookahead over word lengths of more than four bits. The lookahead carry generator is fully compatible with all members of the TTL family.
• PROVIDES LOOKAHEAD CARRIES ACROSS A GROUP OF FOUR ALU'S
• MULTI-LEVEL LOOKAHEAD FOR HIGH SPEED ARITHMETIC
OPERATION OVER LONG WORD LENGTHS

PKGS

OUT

COMMERCIAL GRADE
Vee

TA

= +5.0 V ±5%,

= O°C

Vee

to +70°C

TA

TIlG2

11

TIl C n

Po

G3[I

E]Cn.,

P3[I

!TI Cn.y

:m G
:II Cn.,

TYPE

= -55°C to +125°C

A

9342PC, 93S42PC

Ceramic
DIP (D)

A

9342DC, 93S42DC

9342DM, 93S42DM

78

A

9342FC, 93S42FC

9342FM, 93S42FM

4L

(F)

Go[!

PKG

= +5.0 V ±10%,

Plastic
DIP(P)

Flatpak

mP2

GNO[!

MILITARY GRADE

:ill Vee

1'1 II

pIT

ORDERING CODE: See Section 9
PIN

-

G1[I

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Cn

Go, G2
G1
G3
Po, P1
P2
P3
Cn+x-Cn + z

G

P

DESCRIPTION
Carry
Carry
Carry
Carry
Carry
Carry
Carry
Carry
Carry
Carry

93XX (U.L.)
HIGH/LOW

93S (U.L.)
HIGH/LOW

1.0/1.0
7.017.0
8.0/8.0
4.0/4.0
4.0/4.0
3.0/3.0
2.0/2.0
20/10
20/10
20/10

1.25/1.25
8.75/8.75
10/10
5.0/5.0
5.0/5.0
3.75/3.75
2.5/2.5
25/12.5
25/12.5
25/12.5

Input
Generate Inputs (Active LOW)
Generate Input (Active LOW>
Generate Input (Active LOW)
Propagate Inputs (Active LOW)
Propagate Input (Active LOW)
Propagate Input (Active LOW)
Outputs
Generate Output (Active LOW)
Propagate Output (Active LOW>
4

LOGIC SYMBOL

3

2

1

15 14

6

5

bbbbbbbb

Po Go

p, G,

P2 G2

P3 G3 G

0--10

13- Cn

PO-- 7
C n+ x
,12

C n +y

,11

6-94

C n+z

1

Vce

= Pin 16
= Pin 8

GND

42
FUNCTIONAL DESCRIPTION - The '42 lookahead carry generator accepts up to four pairs of active LOW
Carry Propagate (Po - P:3) and Carry Generate (Go - (3) signals and an active HIGH Carry input (Cn) and provides anticipated active HIGH carries (Cn + x, Cn + y, Cn +z) across four groups of binary adders. The '42also has
active LOW Carry Propagate (P) and Carry Generate (G) outputs which may be used for further levels of lookahead. The logic equations provided at the outputs are:
Cn +x = Go + PeCn
Cn+y=G1 + P1GO + P1POCn
Cn +z = G2 + P2G1 + P2P1 Go + P2P1 PoCn
G =G3 + P3G2 + P3P2G1 + P3P2P1GO
P
-P3P2P1PO
Also, the '42 can be used with binary ALU's in an active LOW or active HIGH input operand mode. The connections (Figure a) to and from the ALU to the lookahead carry generator are identical in both cases. Carries
are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several
possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is
formed by dropping the last 93S41.
TRUTH TABLE
OUTPUTS

INPUTS
~1

Cn

~o

Po

X
L
X
H

H
H
L
X

H
X
X
L

X
X
L
X
X
H

X
H
H
X
L
X

X
H
X
X
X
L

H
H
H
L
X
X

H
X
X
X
L
L

X
X
X
L
X
X
X
H

X
X
H
H
X
X
L
X

X
X
H
X
X
X
X
L

X
H
H
H
X
L
X
X

X
H
X
X
X
X
L
L

H
H
H
H
L
X
X
X

H
X
X
X
X
L
L
L

X
X
H
H
X
X
L
X

X
X
H
X
X
X
X
L

X
H
H
H
X
L
X
X

X
H
X
X
X
X
L
L

X
X
X
H
X
X
X
L

P1

G2 P2

~3

15"3

Cn+x Cn+y Cn+z G

P

•

L
L
H
H

H
X
X
X
L

X
H
X
X
L

L
L
L
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
X
X
X

H
X
X
X
X
L
L
L
X
X
X
H
L

X
X
H
X
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

6-95

H
H
H
H
L
L
L
L
H
H
H
H
L

42

CIN'~_ _ _ _ _ _ _ _ _--j

Fig. a

32-Blt ALU with Ripple Carry Between 16-Blt Lookahead ALUs

LOGIC DIAGRAM
Cn

Go Po

Cn+x

G, p,

C n+ y

Cn+z

6-96

p

42
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
93XX

PARAMETER

SYMBOL
los

Output Short Circuit Current

ICCH

Power Supply Current
(All Outputs HIGH)

ICCL

Power Supply Current
(All Outputs LOW)

93S

UNITS

Min

Max

Min

Max

-40

-100

-40

-100

~
XC

35
39

~
XC

65
72

CONDITIONS

= Max

mA

VCC

45

mA

Vcc = Max; Pa, G3 = 4.5 V
All Other Inputs = Gnd

80

mA

Vcc = Max
Go, Gl, G2 = 4.5 V
All Other Inputs = Gnd

AC CHARACTERISTICS: Vcc = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
93XX
PARAMETER

SYMBOL

93S

CL = 15 pF CL = 15 pF
RL=400n
Min

Max

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
Cn to Cn + x, Cn + y, Cn + z

16
19

10
11.5

ns

Figs. 3-1, 3-5
Po, Pl, P:1 = Gnd
GJ, Gl, <32 = 4.5 V

tPLH
tPHL

Propagation Delay
Po, p;, or P2 to
+ x, Cn + y, Cn + z

13
14

7.0
7.0

ns

Figs. 3-1, 3-4
Px = Gnd (if not under test)
Cn, Go, Gl, G2 = 4.5 V

tPLH
tPHL

Propagation Delay
Go, Gl, or G2 to
+ x, Cn + y, Cn + z

13
14

7.0
7.0

ns

Figs. 3-1, 3-4
Gx = 4.5 V (if not under test)
Cn, Po, Pl, 'P:! = Gnd

tPLH
tPHL

Propagation Delay
Pl, Pi or P3 to G

16
19

7.5
10.5

ns

Figs. 3-1, 3-5
Px = Gnd (if not under test)
Gn, Cn = 4.5 V

tpLH
tPHL

~ropa[ation

Delay

Gn to G

16
19

7.5
10.5

ns

3-1, 3-5
Gx = 4.5 V (if not under test)
'P1 , 'P:!, P3 = Gnd

tPLH
tpHL

Propagation Delay
Pn to P

16
19

6.5
10

ns

Figs. 3-1, 3-5
fix = Gnd (if not under test)

en
en

6-97

~gs.

43
CONNECTION DIAGRAM
PINOUT A

93S43

-

""II

4-BIT BY 2-BIT
TWOS COMPLEMENT MULTIPLIER

IEJvcc
l§]V-l

Col!

DESCRIPTION - The '43 is a high speed twos complement multiplier. The
device is a 4-bit by 2-bit building block that can be connected in an iterative
array to perform multiplication of two binary numbers of variable lengths. The
device can generate the twos complement product, without correction, of two
binary numbers presented in twos complement notation.

"'Ii
x. I!

~vo

x,[!
xo[!

~P

X-l[!

j!]Kl

Sol!

l!!]K2

S1l!
S,,!!

~Ka

~Yl
j!]Ko

~S5

rnS4

113ffi

m

GNDffi

• VERY HIGH SPEED MULTIPLICATION-TWO 12-BIT
NUMBERS IN 125 ns (TYP)
• PROVIDES TWOS COMPLEMENT PRODUCT WITHOUT CORRECTION
• EXPANDS TO ANY SIZE ARRAY WITHOUT
ADDITIONAL COMPONENTS
• ACCEPTS ACTIVE HIGH OR ACTIVE LOW OPERANDS
• EASILY CORRECTABLE FOR UNSIGNED, SIGN-MAGNITUDE OR
ONES COMPLEMENT MULTIPLICATION

C n+4

LOGIC SYMBOL

r

r iii i l'i 'i Y
1-, Xo

ORDERING CODE: See Section 9
PIN
PKGS

OUT

23-

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

22-

PKG
TYPE

Plastic
DIP (P)

A

93S43PC

Ceramic
DIP (0)

A

93S43DC

93S43DM

6N

Flatpak
(F)

A

93S43FC

93S43FM

4M

9N

2'2-

v_,
vo

x,

X2 X3 X4 Ito kl k2 k3

V,

Cn +4

CO

20-< P

So S,

5,

! ! ,t

5,

S.

,I, ,~ ,I.

Vcc = Pin 24
GND = Pin 12

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
X-1, )(3, X4
xo, Xl, X2
Yo
y-l, Yl
ko-k3
Cn
j5
So-S5
Cn + 4

DESCRIPTION
Multiplicand Inputs
Multiplicand Inputs
Multiplier Input
Multiplier Inputs
Constant Inputs
Carry Input
Polarity Control Input (Active LOW for HIGH Operands)
Product Outputs
Carry Output

6-98

5,

93S (U.L.)
HIGH/LOW
1.0/1.0
2.0/2.0
2.0/2.0
1.0/1.0
2.0/2.0
1.0/1.0
3.0/3.0
25/12.5
25/12.5

r---'3

43
FUNCTIONAL DESCRIPTION - The '43 is a super fast hardware multiplier employing 8chottky technology
and twos complement arithmetic. It multiplies a multiplicand of four bits by a multiplier of two bits and forms a
basic iterative logic cell. It can also multiply in active HIGH (positive logic) or active LOW (negative logic)
representations by reinterpreting the active levels of the inputs, outputs and the Polarity Control (Pl. The binary
number with 1 as the most significant bit is treated as a negative number represented in twos complement form.
These '43 iterative logic cells can be connected to implement multiplication of an X-bit number by a V-bit
number. This application requires X • V + 4 • 2 packages and the resulting product has X + V bits. At the
beginning of the array, a constant can be presented atthe K inputs that will be added tothe least significant part
of the product. The packages can be connected in parallel, triangular or split-array scheme depending on the
speed requirement. The '41 ALU can be used with these multipliers in the split-array scheme to obtain high
speed multiplication.
TABLE I SWITCHING TEST CONDITIONS
INPUT

INPUT8 AT 0 V (Remaining Inputs at 4.5 V)

OUTPUT8

Cn

Cn

ko
kl
k2
k3
k3

Cn + 4,80-83,84,85
Cn + 4,81 -83,84,85
Cn + 4, 82, 83, 84, 85
83
84,85

X-l
xo
Xl
X2
X3, X4
X3,X4
X3, X4

C n + 4,
Cn + 4,
Cn + 4,
Cn + 4,
83
84,85
84,85

y-l
yo
Yl

Cn
Cn
Cn

+

+
+
+

P, y-l, Yl, All x

4, So-83, 84, 85

P, y-l, Yl, All X

P, Y-l, Yl, All X

P. y-l,

Yl, All X

P, y-l, Yl, All X
J5; Y-l, Yl, All x, Cn

I

P, Yl, All k

So-83, 84, 85
So-83, 84, 85
81-83, 84, 85
82, 83, 84, 85

P. y-l, Yl, All
P. Y-l, Yl, All
J5; y-l, Yl,

k
k
All k
All k
All k, Cn
k, Cn

P. y-l, Yl,
P. y-l, Yl,
P. Y-l, All
P. Xl, X2, X3,
P. Xl, X2, X3,

X4, All k
X4, All k
xo, Xl, X2, X3, X4, All k

4, So-83, 84, 85
4,80-83,84,85
4, So-83, 84, 85

LOGIC DIAGRAM
y-,
x-'-------r-----,,=tl=~==~tf:==~+*====~~------_,.
Yo,--l>~-H

S3

So

6-99

C n +4

S5

43
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93S

PARAMETER
Min

Icc

149

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V, TA = +25

UNITS

0

CONDITIONS

Max
rnA

Vee

= Max

C (See Section 3 for waveforms and load configurations)
93S

SYMBOL

PARAMETER

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
C n toCn +4

9.0
9.0

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
Cn to SO-S3

13
11

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
C n to S4, S5

16
15

ns

Figs. 3-1, 3'4

tPLH
tPHL

Propagation Delay
kn to C n + 4

12
13

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
kn to SO-S3

14
12

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
kn to 84, S5

19

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
Xn to Cn + 4

15
24

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
Xn to 8o-S3

25
25

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
Xn to S4, S5

30
21

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
Yn to Cn + 4

25
27

ns

Figs. 3-1, 3-5

tPLH
tPHL

Propagation Delay
Yn to 8o-S3

28
27

ns

Figs. 3-1, 3-4

tPLH
tPHL

Propagation Delay
Yn to S4, S5

32
30

ns

Figs. 3-1, 3-4

17

6-100

44
CONNECTION DIAGRAM
PINOUT A

9344

-

NcE

BINARY (4-BIT BY 2-BIT)
FULL MULTIPLIER

~vcc

NC[!

:rnX3
:§IlG

ViI:!

Ex.

Yo I!
Ss[!
s.[f

!!IMi
!!IMii

NciI

~Xo

miG

53!!
52!!

~K2
frnKi

Si§
DESCRIPTION - The '44 is a 4-bit by 2-bit full multiplier building block.
It multiplies two binary numbers and Simultaneously adds two other binary
numbers to the product. '44 devices can be interconnected to form a high
speed multiplier array of any size. The device is constructed with TTL
compatible inputs and outputs. Inputs are buffered to reduce loading.

rm
im NC

soli]

Kii

GNO§

LOGIC SYMBOL

• PERFORMS DIRECT MULTIPLICATION
• EXPANDS TO ANY SIZE ARRAY WITHOUT ADDITIONAL
COMPONENTS
• MULTIPLIES AND ADDS SIMULTANEOUSLY

!!llr!XI

Ml Mo

v,

Yo X3 x, x, Xo

14--0 Ko

ORDERING CODE: See Section 9

15--0 KI

PIN
PKGS

OUT

COMMERCIAL GRADE

MILIT ARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

16--0 K,
17--0 K3

TYPE

Plastic
OIP(P)

A

9344PC

Ceramic
OIP(O)

A

93440C

93440M

6N

Flatpak
(F)

A

9344FC

9344FM

4M

9N

50

SI

5,

~ X!

53

DESCRIPTION

Vec = Pin 24
GND = Pin 12

Xo-Xs

Multiplicand Inputs (Active LOW)
Multiplier Inputs (Active LOW)

Yo,Yl
Ml

~o,

M.!!.

Kl-K3
SO-S5

}

Additive Carry Inputs (Active LOW)
Outputs

6-101

'\

55

! r!

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

5,

93XX (U.L.)
HIGH/LOW
0.66/0.66
0.66/0.66
1.0/1.0
4.0/4.0
2.0/2.0
20/10

44
FUNCTIONAL DESCRIPTION - The '44 is a binary full multiplier for 4-bit by 2-bit words. It is easily expandable
in an array to form a high speed parallel multiplier of any length. The functional equation is illustrated below:
S (6-bits) = X(4-bits) ti mes '1(2-bits) plus M(2-bits) plus K(4-bits)
Functionally the '44 multiplies a 4-bit word (Xo-)(3) by a two bit word ('10-'11), generating eight partial
products. Two other words, Ko - K3 and Mo - M1, are added to these partial products through a lookahead
carry adder, generating a 6-bit product/sum. The function can be described by the following equation (note that
"+" means arithmetic addition):

All inputs and outputs are active LOW; Xand Yinputs are buffered to present only one TTL unit load. The device
operates only on positive numbers. If two's complement multiplication is required, then the numbers must be
changed to sign magnitude before multiplication, or else the product must be corrected following multiplication
of the two's complement numbers. The correction algorithm depends on whether X or '1 or both are negative.
If X is negative:
Subtract V from most significant half of product.
If V is negative:
Subtract X from most significant half of product.
If both X and Vare negative:
Add X plus V to most significant half of product.
The result will be the correct two's complement product.

WEIGHTING FACTORS OF THE BASIC MULTIPLIER

MULTIPLICATION TIME

W W+1

NUMBER
OF
BITS

PACKAGES

TIME (ns)

8x8

8

150

W_ Ko

~

12 x 12

18

260

W+1- K1
W+2_ K2

16 x 16

32

350

W+3_ K3

24 x 24

72

550

l
ssr--W+5
S.,..-.W+4

Xn Ym

S3r-- W + 3
So

Sl

S2r--W+2

! wL
This block represents the basic 4-bit by 2-bit multiplier, and
indicates the weighting factors (power of two) attached to
each of the inputs and outputs.

6-102

44
TYPICAL MULTIPLICATION ARRAYS
The '44 can be assembled in an iterative structure to perform multi-bit multiplication. The blocks are
interconnected so that partial product sums generated in a particular '44 are applied, if necessary, to equal
weight carry inputs (Ko - K3 or Mo, M1) of succeeding stages.
In the active iteritive multiplication arrays shown, weighting factors of the carry and sums between '44's are
indicated (Le., 0 = 20 , 1 = 21 , 2 = 22 , etcJ. Labels inside the blocks identify bits multipled in that block. For
instance 0 -0 refers to multiplicand bits Bo.1 ,2,3 and multiplier bits Ao.1, while 4 - 2 would represent multiplicant bits 84,5,6,7 and multiplier bits A2,3.
a-BIT BY 5-BIT MULTIPLICATION ARRAY
INPUTS

.0

83

85

84

.7

86

r-------~~~~---------+~~----------~~~----------~----------------------Ao

10

12

1<,

5,

K,

9344

S.

9344

9344

9344

K,

0-1

8,

0-3

4-1

4-3

11

I

10

8,

Ko

Po

P,

P,

P7

P,

PRODUCT

a-BIT BY a-BIT MU(TIPLICATION ARRAY
MULTIPLIER
INPUT

MULTIPLICAND
INPUT

Ao.l.2.3.4.5.6.7

80.1.2.3.4.5.6.7

9344
0-0

9344
0-2

9344

9344

0-4

0-6

9344
4-4

p,
LSB

PRODUCT

6-103

9344

4-6

Po

PtO

P11

MS.

~
~

16-BIT BY 16-BIT MULTIPLICATION ARRAY
INPUTS

B

KEY
X = 4 BIT MULTIPLICAND, INPUT B
Y = 2 BIT MULTIPLIER, INPUT A
ALL INPUTS ACTIVE LOW

A

K2

54

9344

X=Y

j(,

53

Ko

~ULTIPLIER

INPUT
Ao-15

tl
l

>
"

I

I

---

>

80,1.2.3

---

80.1,2.3

0-12

MULl
I

0-14

r--

o.j>.

---

o

~

tfu
0-8

0-10

4-8

4-10

4-12

4-14

4-4

4-6

8-4

8-8

8-6

8-10

-

)

---

ii,

,)

~l
1

~

52

So

<

--

1Jtt
0-8

0-4

8-12

8-14

r--

1Ttt
0-0

Po

0-2

p,

P2

P3

4-2

4-0

P4

P5

Po

8-0

p,

P8

P9

12-2

8-2

12-0

P10 P"

P12 P13

P14

P15

12-4

P16

P17

12-6

P18

P19

12-8

P20

P21

12-10

P22

P23

12-12

P24

P25

12-14

P26

~

P27 P2Si'29P30P3,

PRODUCT

NOTE:
Each block represents one 9344. Labels inside the blocks identify bits multiplied in that block. The first number is the 4-bit B input, and the second number is the 2-bit
A input. For instance, 12-0 refers to multiplicand bits B12,13,14,15 and multiplier bits Ao,l.

44
LOGIC DIAGRAM

Ko Jlo

YO-{~----------~~--~--------~--4r--~---r~--------4r--'
Y1~>r~--~----~~--~~------~--~~-+~~-+--~

~~>r~--~----~~--~~------H---~~-+ff-~-+---n----~,

X1-{~~--+-----~~--+-4-------~--~~-+~~~-,
~~:~~--r------;~--r-~------~~
X3~)o--M-...,.,-------tHIt----h

•
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
93XX

PARAMETER

SYMBOL

Min
lee

CONDITIONS

UNITS

Max
150

Power Supply Current

rnA

Vee

= Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
93XX
PARAMETER

SYMBOL

= 15 pF
RL = 400 n.
CL

Min

Propagation Delay

22

Ko to 55

39

6-105

CONDITIONS

Max
51
52

Propagation Delay
to 83

Ml

UNITS

ns

Figs. 3-1, 3-4

ns

Figs. 3-1, 3-5

46
CONNECTION DIAGRAM
PINOUT A

93S46
HIGH SPEED 6-BIT IDENTITY COMPARATOR
DESCRIPTION - The '46 is a very high speed 6-bit identity comparator. The
device compares two words of up to six bits and indicates identity in less than
12 ns. It is easily expandable to any word length by using either serial or paralIel expansion techniques. When the Enable input (E> is LOW, it forces the
output LOW.

• COMPARES TWO 6-BIT WORDS IN 12 ns
• EASILY EXPANDABLE TO ANY WORD SIZE
• ACTIVE HIGH ENABLE FOR FAST RIPPLE EXPANSION

ORDERING CODE: See Section 9
PIN
PKGS

OUT

AoIT

-

mBs

All!

ElAs

B1E

liIB4

A21!

:rn A4

B2[!

TIlB3

Ell

:rn A3
]]A=B

GND[!

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

93S46PC

Ceramic
DIP(D)

A

93S46DC

93S46DM

68

Flatpak
(F)

A

93S46FC

93S46FM

4L

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
DESCRIPTION

PIN NAMES

Ao-As
80-85
E
A=8

LOGIC SYMBOL

1 iii

i i 1j Y1j YY1j

Ao Bo Al Bl A2 B2 A3 B3 A4 B4 As Bs
7-

93S (U.L.)
HIGH/LOW
1.25/1.25
1.25/1.25
1.25/1.25
25/12.5

Word A Inputs
Word 8 Inputs
Enable Input (Active HIGH)
A Equal to 8 Output

E
A=B

!
Vee = Pin 16
GND = Pin 8

6-106

I!!l Vee

BalI

46
FUNCTIONAL DESCRIPTION - The '46 is a very high speed 6-bit identity comparator. The A = B output is
HIGH when the Enable (E> is HIGH and the two 6-bit words are equal. Equality is determined by Exclusive-NOR
circuits which individually compare the equivalent bits from each word. When any two of the equivalent bits
from each word have different logic levels, the A = B output is LOW.

An active HI GH Enable (E) provides a means of fast ripple expansion. By connecting the A = B output of the first
stage of the comparator to the enable of the next stage, the comparator can be expanded in 6-bit increments at
an additional 4.5 ns per stage. An even faster expansion technique is achieved by connecting the A = B outputs
to a Schottky NAND gate. This method compares two words of up to 78 bits each in 15 ns (typical) using the '133
13-input Schottky NAND gate.
TRUTH TABLE
INPUTS
E

An, Bn

L
L
H
H

An
An
An
An

=
i'
i'
=

OUTPUT
A=B

Bn
Bn
Bn
Bn

L
L
L
H

•

H = HIGH Voltage Level
L = LOW Voltage Level

RIPPLE EXPANSION
AoBo •••••• ·.····AsBs

E

E

93S46

As Be • • • • • • • • • • • • Al1Bl1

93S46

E

A=B

A=B

A12 B12 • • • • • • • • • • • • A17 817

E

93S46

A=B
L - - _ ( A = Ble E

NOTE: This simple method of expansion adds 4.5 ns for each additional '46 used.
PARALLEL EXPANSION
AeBo •••••••••••• AsBs

As

B6

• • • • • • • • • • • • All Bl1

A12812 • • • • • • • • • • • • A17 B17

93846

93S46

93S46

A=B

A=B

A=B

SCHOTTKY
NAND GATE

NOTE: This method of expansion adds one gate delay ("'3 ns) to the '46, independent of the word length that is compared.

6-107

46
LOGIC DIAGRAM
Ao Bo

AI BI

A2 B2

A3 B3

A4 B4

As Bs

J..l J.1 J..L J.1 J..L il

I

E

~

I II

Y

M

A=B

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93S

PARAMETER

Min
Icc

UNITS

CONDITIONS

Max

Power Supply Current

70

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
93S
SYMBOL

PARAMETER

Propagation Delay

CL = 15 pF
Min

Max

UNITS

CONDITIONS

E = 4.5 V, Other Inputs
= 4.5 V, Test each input

tPLH
tPHL

An or Bn to A = B

3.0
3.0

17
17

ns

tPLH
tPHL

Propagation Delay
An or Bn to A = B

3.0
3.0

14
15

ns

tPLH
tpHL

Propagation Delay
E to A = B

2.0
2.0

10
10

ns

6-108

individually, Figs. 3-1,3-5
E = 4.5 V, Other Inputs
= Gnd, Test each input
individually, Figs. 3-1, 3-4

An = Bn
Figs. 3-1, 3-5

47
CONNECTION DIAGRAM
PINOUT A

93847
HIGH SPEED 6-BIT IDENTITY COMPARATOR
DESCRIPTION - The '47 is a very high speed 6-bit identity comparator. The
device features an open-collector output for wired-OR expansion and active
LOW Enable. The '47 is fabricated with the Schottky barrier diode process for
high speed, and is completely compatible with all TTL families. This device
is recommended for applications where wired-OR expansion is desired and
the speed of an active pull-up is not required. The '47 is a pin-for-pin replacement for the DM7160/8160.

• SCHOTTKY PROCESS FOR HIGH SPEED
• COMPARE TWO 6-BIT WORDS IN 15 ns
• OPEN-COLLECTOR OUTPUT FOR WIRED-OR EXPANSION

PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vcc = +5.0 V ±5%,
TA = O°C to +70°C

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

93S47PC

Ceramic
DIP (D)

A

93S47DC

93S47DM

68

A

93S47FC

93S47FM

4L

(F)

!mBs

A1[!

~AS

B,[~

~B4

A2[!

fmA4

B2[!

~B3

elI

~A3
f!1A=B

TYPE

A

98

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao-As
80-85

E
A=8

93S (U.L.)
HIGH/LOW

DESCRIPTION
Word A Inputs
Word 8 Inputs
Enable Input (Active LOW)
A Equal to 8 Output

1.25/1.25
1.25/1.25
1.25/1.25
OC*/12.5

'OC-Open Collector

LOGIC SYMBOL

1 iii

ii

YJTT

1j
1j
Ao Bo A1 B1 A2 B2 A3 B3 A4 B4 A5 B5
7-0 E

A=B

!
6-109

~vcc

BolI

PKG

Plastic
DIP (P)

Flatp~k

-'

GNO[!

ORDERING CODE: See Section 9
PIN

AolI

VCC = Pin 16
GND = Pin 8

47
FUNCTIONAL DESCRIPTION - The '47 is a very high speed 6-bit identity comparator. When enabled (E input
LOW), the A = B output is HIGH ifthetwo 6-bit words are equal. When disabled (j~ input HI GH), the A = B output
is forced HIGH. Equality is determined by Exclusive-NOR circuits which individually compare the equivalent
bits from each word. Since the A = B output state is determined by the equality of each pair of inputs, the
equivalent An and Bn pins can be interchanged to facilitate board layout or wiring. The active LOW Enable @
can be used as a high speed strobe. When the Enable is HIGH, the A = B output is forced HIGH. This allows
devices tied to a common wired-OR (actually wired-AND) node tobestrobed individually or in groups. Only the
enabled devices will determine the state of the output node.
(A = B) =

E+

(Ao ED Bo) • (Al ED Bl) • (A2 ED B2) • (A3 ED B3) • (A4 ED B4) • (As ED B5)

LOGIC DIAGRAM
Ao Bo

A1 B1

A2 B2

A3 B3

A4 B4

E

As Bs

~

JJ. JJ. J.1 il JJ. J.1

I

TRUTH TABLE
INPUTS

I II

~( )

E

An, Bn

L
L
H
H

An
An
An
An

=
"#
"#
=

OUTPUT
A=B
H
L
H
H

Bn
Bn
Bn
Bn

H = HIGH Voltage Level
L = LOW Voltage Level

A=B
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93S

PARAMETER
Min

lee

65

Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

CONDITIONS

UNITS
Max
rnA

Vee

= Max

TA = +25°C (See Section 3 for waveforms and load configurations)
93S

SYMBOL

PARAMETER

CL = 15 pF
RL = 280 n
Min

Max

UNITS

CONDITIONS

E = Gnd, Other Inputs
input
individually, Figs. 3-2, 3-5

tPLH
tPHL

Propagation Delay
An or Bn to A = B

5.0
5.0

17
17

ns

= 4.5 V, Test each

tPLH
tPHL

Propagation Delay
An or Bn to A = B

4.0
4.0

14
15

ns

E = Gnd, Other Inputs
= Gnd, Test each input

tPLH
tPHL

Propagation Delay
'EtoA=B

3.0
3.0

10
10

ns

6-110

individually, Figs. 3-2, 3-4
An"# Bn
Figs. 3-2, 3-5

48
CONNECTION DIAGRAM
PINOUT A

9348
12-INPUT PARITY CHECKER/GENERATOR

DESCRIPTION - The '48 is a 12-input parity checker/generator generating
odd and even parity outputs. It can be used in high speed error detection
applications.

15IT

Ie

•
•
•
•

BOTH ODD AND EVEN PARITY OUTPUTS PROVIDED
GENERATES A PARITY BIT FOR UP TO 12 BITS
CHECKS FOR PARITY ON UP TO 12 BITS
EASILY EXPANDABLE

PKGS

OUT

II

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG

IT

~13
~12

19

II

~11

110

II

111

IT

~IO
~PE

GND!:!

~po

TYPE

Plastic
DIP (P)

A

9348PC

Ceramic
DIP (D)

A

9348DC

9348DM

68

Flatpak
(F)

A

9348FC

9348FM

4L

98

INPUT LOADING/FAN-OUT

10-111
PO
PE

93XX (U.L)
HIGH/LOW

DESCRIPTION

PIN NAMES
Parity Inputs
Odd Parity Output
Even Parity Output

2.0/2.0
20/10
20/10
LOGIC SYMBOL

1f
10

YTYY1 iii
11

12

iii

Is 14 15 16 17 18 19 110 111

po

PE

!

}o

Vcc = Pin 16
GND = Pin 8

6-111

~vcc
~14

18

1,[1:

ORDERING CODE: See Section 9
PIN

-

•

48
FUNCTIONAL DESCRIPTION - The '48 is a 12-input parity generator. It provides odd and even parity for upto
12 data bits. The Even Parity output (PE) will be HIGH if an even number of logic ones are present on the inputs.
The Odd Parity output (PO) will be HIGH if an odd number of logic ones are present on the inputs. The logic
equations for the outputs are shown below.
PO

= 10 EEl

11 EEl 12 EEl 13 EEl 14 EEl 15 EEl 16 EEl 17 EB 18 EB 19 EEl 110 EB 111

PE = 10 EB 11 EB 12 EB 13 EEl 14 EEl 15 EB 16 EB 17 EEl 18 ffi 19 EEl 11 0 ffi 111
NOTE: Less through delay is encounted from the 10,11,12, and 13 inputs than 14 thru 111 inputs. Therefore, if some
signals are slower than others, the slower signals should be applied to these four inputs for maximum speed.
TRUTH TABLE

LOGIC DIAGRAM

INPUTS

OUTPUTS

10-111

PO

PE

All Twelve
Any One
Any Two
Any Three

Inputs LOW
Input HIGH
Inputs HIGH
Inputs HIGH

L
H
L
H

H
L
H
L

Any
Any
Any
Any

Four
Five
Six
Seven

Inputs
Inputs
Inputs
Inputs

HIGH
HIGH
HIGH
HIGH

L
H
L
H

H
L
H
L

Any
Any
Any
Any
Any

Eight
Nine
Ten
Eleven
Twelve

Inputs
Inputs
Inputs
Inputs
Inputs

HIGH
HIGH
HIGH
HIGH
HIGH

L
H
L
H
L

H
L
H
L
H

H = HIGH Voltage Level
L = LOW Voltage Level

6-112

48
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER
Min

Icc

UNITS

CONDITIONS

Max

Power Supply Current

82

mA

Vee = Max

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25 0 C (See Section 3 for waveforms and load configuration)
93XX

SYMBOL

PARAMETER

CL = 15 pF
RL = 400 0.
Min

UNITS

CONDITIONS

12, 13, 17, Is = Gnd; Other
Inputs (exc. 14) HIGH

Max

tPLH
tPHL

Propagation Delay
14 to PO

46
42

ns

tPLH
tPHL

Propagation Delay
14 to PE

51
48

ns

12, 13, 17, Is = Gnd; Other
Inputs (exc. 14) HIGH
Figs. 3-1, 3-5

tPLH

Propagation Delay
13 to PO

27

ns

17 = HIGH; Other Inputs
(exc. 13) = Gnd
Figs. 3-1, 3-4

tPHL

Propagation Delay
14 to PO

25

ns

All Inputs (exc. 14) = Gnd
Figs. 3-1, 3-5

6-113

Figs. 3-1, 3-4

•

62
CONNECTION DIAGRAM
PINOUT A

93862
9-INPUT PARITY CHECKER/GENERATOR

-

II
"II

10

EJvcc

:m

1211

Ell6

13[!

;ml'

IT

f!m I.

18

~PE

POl:!

DESCRIPTION - The '62 is a very high speed 9-input parity checker/generator for use in error detection and error correction applications. The '62
provides odd and even parity for up to nine data bits. The even parity
output (PEl is HIGH if an even number of inputs are HIGH and E is LOW.
The odd parity output (PO) will be HIGH if an odd number of inputs are
HIGH and ~ is LOW. A HIGH level on the Enable (8 input forces both
outputs LOW.

17

~E

GNO[!

LOGIC SYMBOL
•
•
•
•
•
•

INPUT-TO-OUTPUT DELAY 16 ns
OUTPUT ENABLE TERMINAL
BOTH ODD AND EVEN PARITY OUTPUTS PROVIDED
GENERATES A PARITY BIT FOR UP TO NINE BITS
CHECKS FOR PARITY ON UP TO NINE BITS
EASILY EXPANDABLE

1i i
10 "

ORDERING CODE: See Section 9

12

PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

93S62PC

Ceramic
DIP(O)

A

93S62DC

93S62DM

6A

Flatpak
(F)

A

93S62FC

93S62FM

31

13 14

I, 16

93862

8 --~
J

0--

1-0F-1S
DECODER

A3

--I>-

--I

LATCH

~

LATCH

f--L

LATCH

.A>
CD
CD
+ t
J1 BLANKING
RIPPLE
CIRCUIT

6-124

a

0-- jj

~

SEGMENT
ENCODER

~

OUTPUT
DEVICES

p- c
p- ii
p-

p- T
p- 9

70
TRUTH TABLE

OUTPUTS

INPUTS
BINARY
STATE LE

-

b

c

H
L
H

H
L
L

H
L
L

A2

A1

Ao

X

X

X

X

•

X

L
L
L

L
L
L

L
L
L

L
L
H

.

STABLE
H H
L
L
H H

..

RBO

DISPLAY

H
L
H

H
H
H

H
L
H
H

L
H
H
H

H
H
L
L

L
L
L
L

H
H
H
H

L
H
L
H
H

L
H
L
H
L

L
H
L
L
L

L
H
L
L
L

H
H
H
H
H

L
H
L
H
H

L
L
L
L
H

L
L
L
L
L

L
L
H
L
L

L
H
L
L
L

H
H
H
H
H

cI

H

H

H

H

H

L"

BLANK

H
L
L
L

2
3
4
5

L
L
L
L

X
X
X
X

L
L
L
L

L
L
H
H

H
H
L
L

L
H
L
H

L
L
H
L

L
L
L
H

H
L
L
L

L
L
H
L

6

9
10

L
L
L
L
L

X
X
X
X
X

L
L
H
H
H

H
H
L
L
L

H
H
L
L
H

L
H
L
H
L

L
L
L
L
L

H
L
L
L
L

L
L
L
L
L

11
12
13
14
15

L
L
L
L
L

X
X
X
X
X

H
H
H
H
H

L
H
H
H
H

H
L
L
H
H

H
L
H
L
H

H
L
H
L
L

H
H
L
H
H

X

X

X

X

X

X

X

H

H

L
H

-e T -9

d

0
0
1

7
8

'The

-a

RBI Aa

STABLE
BLANK
n
u
I
I

::l
L

3
Y

cJ

c

,u

I

8
0

I

0

"L
u

r

L

d

E

RBi

will blank the display only il binary zero is stored in the latches.
"i'iEiO used as an input overrides all other input conditions.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

NUMERICAL DESIGNATION

o

2

4

3

I-I

I

I I

11-

5

'-II_II
I

6

I

1_11_1

7

8

9

10

-I I , , I , I

11

12

13

1_ 1- _I I

15

14

I

11_11111_11_1_11_1

6-125

70
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYBMOL

93XX

PARAMETER

Min
VOH

Output HIGH Voltage

RBO

VOL

Output LOW Voltage

RBO
a-g

IOH

Output HIGH Current, 8"- g

lee

Power Supply Current

UNITS

2.4

V

Vee

0.4
0.4

V

IOL
IOL

250

/J. A

105
mA
94

AC CHARACTERISTICS: Vee

= +5.0 V,

TA

CONDITIONS

Max

= +25°C (See

= Min,

IOH -80/J.A

= 3.2 mA I
= 25 mA I

V - M·
ee In

= Max, Vour = 5.5 V
A1, A2, A3, LE = Gnd
Vee = Max, Outputs Open
Ao, A1, A2, IT= Gnd
Vee = Max, Outputs Open
Vee

Section 3 for waveforms and load configurations)

93XX
SYMBOL

CL = 15 pF
RL = 500 n

PARAMETER

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
An to 8"-9

75
50

ns

Figs. 3-1, 3-20

tPLH
tPHL

Propagation Delay
LE to 8"-9"

90
70

ns

Figs. 3-1, 3-9

AC OPERATING REQUIREMENTS: Vee
SYMBOL

= +5.0 V,

TA

= +25°C
93XX

PARAMETER

Min

UNITS

CONDITIONS

Max

ts (H)
ts (U

Setup Time HIGH or LOW
An to LE

30
20

ns

th (H)
th (U

Hold Time HIGH or LOW
An to LE

0
0

ns

tw (U

LE Pulse Width LOW

45

ns

Fig. 3-13

Fig. 3-9

\
I

6:-126

72
CONNECTION DIAGRAM
PINOUT A

93H72
HIGH SPEED 4-BIT SHIFT REGISTER

-

MIi[I

(With Enable)

~vcc
~QO

D[!

Ern:

~Q'
~Q'

PoI:!

~Q3
~Q3

P.[~

DESCRIPTION - The '72 high speed 4-bit shift register is a multifunctional
sequential logic block which is useful in a wide variety of register applications. It may be used in serial-serial, shift left, shift right, serial-parallel,
parallel-serial and parallel-parallel data transfers. The '72 has three synchronous modes of operation: shift, parallel load and hold (do nothing).
The hold capability permits information storage in the register independent
of the clock.

P21!
P31!

~cp

GND!!

PJPE

LOGIC SYMBOL

60 MHz TYPICAL SHIFT FREQUENCY
SYNCHRONOUS PARALLEL DATA ENTRY
DATA HOLD (DO NOTHING) INDEPENDENT OF CLOCK
FULLY SYNCHRONOUS, EDGE-TRIGGERED
ASYNCHRONOUS MASTER RESET

•
•
•
•
•

1iii I
E

Po

p,

9-- and Enable@ as shown in
Table 1. The active LOW Enable when HIGH, places the register in the hold mode with the register flip-flops
retaining their information. When the Enable is activated (LOW) the Parallel Enable(PE) determines whether the
register operates in a shift or parallel data entry mode.
When the Enable is LOW and the Parallel Enable input is LOWthe parallel inputs are selected and will determine
the next condition of the register synchronously with the clock as shown in Table II. In this mode the element
appears as four common clocked D flip-flops. With E LOW and the PE input HIGH the device acts as a 4-bit shift
register with serial data entry through the D input shown in Table III. In both cases the next state of the flip-flops
occurs after the LOW-to-HIGH transition of the clock input.
The asynchronous active LOW Master Reset overrides all inputs and clears the register forcing outputs 00 -03
LOW and 03 HIGH. To provide for left shift operation, P3 is used as the serial data input and 00 is theserial data
output. The other outputs are tied back tothe previous parallel inputs, with 03 tied to P2, 02 tiedto P1 and 01 tied
to Po.
LOGIC DIAGRAM
i

Pi

Po

P3

03

cp--------------~--~--1_--------~--~--+_---------+--~--+_--------~
MR------------------~--1_------------~--+_------------~--+_----------~

03

00

TABLE I. MODE SELECT TABLE
MODE

Synchronous

Parallel Load
Serial Shift
Hold
Hold

Asynchronous Reset

MR

E

PE

H
H
H
H

L
L
H
H

L
H
L
H

Parallel Data Entry
X
X
X
X
X
X
X
X
X
X
X
X

L

X

X

All Outputs Set LOW (03 = HIGH)

IPO

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

6-128

P1

P2

P3

D
X
Serial Data Entry
X
X

72
TABLE II.
PARALLEL DATA ENTRY

TABLE III.
SERIAL DATA ENTRY

PO-P3
INPUT @ tn

a
@ tn + 1

DINPUT
@ tn

@ tn + 1

L
H

L
H

L
H

L
H

00

tn = Present State
tn + 1 = State after next clock
H = HIGH Voltage Level
L = LOW Voltage Level

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
los
lee

93H

PARAMETER
Output Short Circuit Current
Power Supply Current

AC CHARACTERISTICS: Vee

= +5.0 V,

CONDITIONS

Max

-30

-100

rnA

Vee

= Max,

120
135

rnA

Vee

= Max

XM
XC

TA

UNITS

Min

= +25°C (See Section 3 for waveforms and

VOUT

=0 V

load configurations)

93H
SYMBOL

CL

PARAMETER

= 15 pF

Min
fmax

Maximum Shift Frequency

tPLH
tPHL

Propagation Delay
CP to an

tpHL

Propagation Delay
MR to an

AC OPERATING REQUIREMENTS: Vee
SYMBOL

CONDITIONS

Max
MHz

Figs. 3-1, 3-8

16
21

ns

Figs. 3-1, 3-8

26

ns

Figs. 3-1, 3-16

45

= +5.0 V,

UNITS

= +25°C

TA

93H

PARAMETER
Min

ts (H)
ts(U

Setup Time HIGH or LOW
D or Pn to CP

7.0

ts (H)

ts (U

Setup Time HIGH or LOW
E to CP

17

ts (H)
Is (U

Setup Time HIGH or LOW
PE to CP

19

th (H)
th (U

Hold Time HIGH or LOW
D, Pn, E or PE to CP

0

tw (U

MR Pulse Width LOW

trec

MR Recovery Time

19
7.0

6-129

UNITS

CONDITIONS

Max

ns

Fig. 3-6

ns

Fig. 3-6

ns

Fig. 3-16

I

74
CONNECTION DIAGRAM
PINOUT A

9374
7-SEGMENT DECODER/DRIVER/LATCH
(With Constant Current Sink Outputs)

DESCRIPTION - The '74 is a 7-segment decoder driver incorporating input
latches and output circuits to directly drive common anode LED displays.

• HIGH SPEED INPUT LATCHES FOR DATA STORAGE
• 15 rnA CONSTANT CURRENT SINK CAPABILITY TO DIRECTLY DRIVE
COMMON ANODE LED DISPLAYS
• INCREASES INCANDESCENT DISPLAY LIFE
• ACTIVE LOW LATCH ENABLE FOR EASY INTERFACE
WITH MSI CIRCUITS
• DATA INPUT LOADING ESSENTIALLY ZERO WHEN LATCH DISABLED
• AUTOMATIC RIPPLE BLANKING FOR SUPPRESSION OF LEADING
AND/OR TRAILING-EDGE ZEROES

ORDERING CODE: See Section 9

= +5.0 V ±5%.
TA = O°C to +70°C
Vee

OUT

7

1

2

PKG

6

3

5

I I I I bb
Ao

A,

A2

RBO a b c

COMMERCIAL GRADE

PIN
PKGS

LOGIC SYMBOL

A3

LE

RBI

del

11111111

TYPE

4 13 12 11 10 9 15 14

Vcc = Pin 16
GND= Pin 8

Plastic
DIP(P)

A

9374PC

9B

Ceramic
DIP(D)

A

9374DC

6B

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

8-g

DESCRIPTION
Address (Data) Inputs
Latch Enable Input (Active LOW)
Ripple Blanking Input (Active LOW)
Ripple Blanking as Output (Active LOW>
as Input (Active LOW>
Constant Current Outputs (Active LOW)

'OC-Open Collector
"Except Loading is 10 I'A @ 0.4 V when

i:E is HIGH.

6-130

9

93XX (U.L.)

HIGH/LOW
1.0/0.25**
0.5/0.25
0.5/0.25
1.0/0.5
-/0.75
OC*/15rnA

74
FUNCTIONAL DESCRIPTION-The '74 is a 7-segment deconder/driver with latches on the address inputs and
active LOW constant curr~nt outputs to drive LEOs directly. This device accepts a 4-bit binary code and
produces output drive to the appropriate segments of the 7-segment display. It has a decode format which
produces numeric codes "0" through "9" and .other codes.

Latches on the four data inputs are controlled by an active LOW Latch Enable, IT. When LEis LOW, the state of
the outputs is determined by the input data. When LE goes HIGH, the last data present at the inputs is stored in
the latches and the outputs remain stable. The LE pulse width necessary to accept and store data is typically 50
ns, which allows data to be strobed into the '74 at normal TTL speeds. This feature means that data can be routed
directly from high speed counters and frequency dividers into the display without slowing down the system
clock or providing intermediate data storage.
The latch/decoder combination is a Simple system which drives LED displays with multiplexed data inputs from
MaS time clocks, DVMs, calculator chips, etc. Data inputs are multiplexed while the displays are in static mode.
This lowers component and insertion costs, since several circuits- seven resistors per display, strobe drivers, a
separate display voltage source, and clock failure detect circuits-traditionally found in multiplexed display
systems are eliminated. It also allows low strobing rates to be used without display flicker.
Another '74 feature is the reduced loading on the data inputs when the Latch Enable is HIGH (only 10 p.A typ).
This allows many '74s to be driven from a MOSdevice in multiplex mode without the need for drivers on the data
lines. The '74 also provides automatic blanking of the leading and/or trailing-edge zeroes in a multidigit decimal
number, resulting in an easily readable decimal display conforming to normal writing practice. In an a-digit
mixed integer fraction decimal representation, using the automatic blanking capability 0060.0300 would be
displayed as 60.03. Leading-edge zero suppression is obtained by connecting the Ripple Blanking Output
(RBO) of a decoder to the Ripple Blanking Input (RBI> of the next lower stage device. The most significant
decOder stage should have the RBI input grounded; and since suppression ofthe least significant integer zero in
a number is not usually desired, the RBI input of this decoder stage should be left open. A similar precedure for
the fractional part of a display will provide automatic suppression of trailing-edge zeros. The RBO terminal of
the decoder can be OR-tied with a modulating Signal via an isolating buffer to achieve duration intenSity
modulation. A suitable signal can be generated for this purpose by forming a variable frequency multivibrator
with a cross coupled pair of TTL or DTL gates.

LOGIC DIAGRAM

I-----------------~

I

Ao

I
I
I
I

I
I
I

I

~

J

J

~~

I

.....

I

I
I
I
I

IL ________ _ _ _ _1_ _ _ _ _ _ _ _ JI

LE

.to...
-

LATCH

1-0F-16
DECODER

.-1

LATCH

t>

--I

LATCH

lD

hi

LATCH

P

......

~

~

1

J B~~:~~G L

I

-I

6-131

CIRCUIT

I

SEGMENT
ENCODER

~
.:y

CONSTANT
CURRENT
OUTPUT
DEVICE

ppppp-p-p--

I

74
TRUTH TABLE
OUTPUTS

INPUTS
BINARY
STATE LE

-

b

-c

H
L
H

H
L
L

H
L
L

RBI A3

A2

Al

Ao a

X

X

X

X

•

L
L
L

L
L
L

L
L
H

-e

T

STABLE
H
H
L
L
H
H

d

-9

RBO

H
L
H

H
H
H

H
L
H
H

.

DISPLAY

0
0
1

H
L
L
L

*
L
H

X

L
L
L

2
3
4
5

L
L
L

L

X
X
X
X

L
L
L
L

L
L
H
H

H
H
L
L

L
H
L
H

L
L
H
L

L
L
L
H

H
L
L
L

L
L
H
L

L
H
H
H

H
H
L
L

L
L
L
L

H
H
H
H

X
X
X
X
X

L
L
H
H
H

H
H
L
L
L

H
H
L
L
H

L
H
L
H
L

L
L
L
L
H

H
L
L
L
H

L
L
L
L
H

L
H
L
L
H

L
H
L
H
H

L
H
L
L
H

L
H
L
L
L

H
H
H
H
H

,5

10

L
L
L
L
L

11
12
13
14
15

L
L
L
L
L

X
X
X
X
X

H
H
H
H
H

L
H
H
H
H

H
L
L
H
H

H
L
H
L
H

L
H
H
L
H

H
L
H
L
H

H
L
H
H
H

L
H
L
H
H

L
L
L
L
H

L
L
L
L
H

L
L
H
L
H

H
H
H
H
H

E
H

BLANK

X

X

X

X

X

X

X

H

H

H

H

H

H

H

L**

BLANK

6
7

8
9

'The

STABLE
BLANK
n
u
I
I

2
:3
Lj

5
I

8

9
-

I

L

0

I

mii will blank the display only If a binary zero is stored in the latches.

"FmC> used as an

input overrrides all other input conditions.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

NUMERICAL DESIGNATIONS

o

I-I
1 1

2

3

4

5

6

7

8

_1-11_11
I
I
I
1 _11_1

9

10

11

1

1-

6-132

12

III

13

14

I-I

-11_1-

15

74
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
93XX

PARAMETER

SYMBOL

Min
OFF
ON

Your

Output Voltage,
Applied

IOL

Output LOW Current,

a- 9

IOH

Output HIGH Current

8"-g

Icc

Power Supply Current

UNITS

CONDITIONS

Max
10
(Fig. a)

Separate
LED Supply

V

18

mA

Vee = 5.0 V, VOL = 3.0 V
TA = 25°C

250

IJ.A

Vee = Max, Your = 5.5 V

50

mA

Vee = Max, VIN = Gnd
Your = 3.0 V

12

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
93XX

CL = 15 pF
RL=1kO

PARAMETER

SYMBOL

Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
An to 8-g

140
140

ns

Figs. 3-2, 3-20

tPLH
tPHL

Propagation Delay
LEto 8"-g

140
140

ns

Figs. 3-2, 3-9

AC OPERATING REQUIREMENTS: Vee = +5.0 V, TA = +25°C
93XX

PARAMETER

SYMBOL

Min

UNITS

ts (H)
ts (U

Setup Time HIGH or LOW
An to LE

75
30

ns

th (H)
th (U

Hold Time HIGH or LOW
An to LE

0
0

ns

85

ns

tw

(U

..

LE Pulse Width LOW

~

i

12

~

.

11

i

10

~

9

~

8

a:

I

.~

Ii
a:
!

I I I I

.

..~
~

7

>
I

0

~N

U

I
I

j:'

z
;

~

o~:~
"Q~

5

15

TAo ""H"C
21
2.
Vee

21

= 5.25 Y

t-- ryee ~ 5.~ ~ \

.-.. -'

Vee =4.75 V

1.

'

'15

12

~~f-

"I

1

..

Fig. 3-9

"~ .-

o(,~

3

2

I

Fig. 3-13

C 3D

I

PEAK OUTPUT "ON" VOLTAGE

~

~

I

PEAK OUTPUT "OFF" YOLTAGE

e" 8
"!!! •
tcw •
cl

I

CONDITIONS

Max

9

0

8

~

3

0
0

2535'155857585

TA-AMBIENT TEMPERATURE_oC

1

2
YOUT -

Fig. a Output Voltage Safe Operating Area

Fig. b

6-133

3

•

5

8

7

•

•

10

OUTPUT VOLTAGE - VOLTS

Typical Constant Segment Current
Versus Output Voltage

I

74
APPLICATIONS -It is possible with common anode 7-segment LED displays and constant current sink
decoder drivers to save substantial amounts of power by carefully choosing operating points on display supply
voltage. First, examine the power used in the normal display driving method where the display and decoder
driver are both operated from a +5.0 V regulated supply (Vee = Vs>'
vs

I

COMMON
ANODE
LED

0=0 FLr
0::0

vcc

CURRENT

111111

AoA,A2A3LTRBI

'--RBO. bed e I 9

h

IF

T

Fig. c

Y

II

Separate Supply for LED Displays

The power dissipated by the LED and the driver outputs is (Vee x Iseg x n Segments>. The total power dissipated
with a 15 mA LED displaying an eight (8) would be:
PTOT=5.0 V x 15 mA x 7
=525 mW
Of this 525 mW, the power actually required todrive the LED is dependent on the VF drop of each segment. Most
GaAsP LEOs exhibit either a 1.7 V or a 3.4 V forward voltage drop. Therefore, the required total power for seven
segments would be:
P(1.7)=1.7 V x 15 mA x 7
=178.5 mW
P(3.4) =3.4 V x 15 mA x 7
=357 mW
The remaining power is dissipated by the driver outputs which are maintaining the 15 mA constant current
required by the LEOs. Most of this power is wasted, since the driver can maintain approximately 15 mA with as
little as 0.5 V across the output device. By using a separate power source (Vs, Figure c) for the LEOs, which is set
to the LED VF plus the offset voltage of the driver, as much as 280 mW can be saved per digit. i.e.,
Vs=VF (Max) + Vollset
=2.0 V + 0.5 V
=2.5 V
PT = 2.5 V x 14 mA (from Figure b) x 7
=245 mW
These figures show that using a separate supply to drive the LEOs can offer significant display power savings. In
battery powered equipment, two rechargeable nickle-cadmium cells in series would be sufficient to drive the
display, while four such cells would be needed to operate the logic units.

6-134

74
APPLICATIONS (Cont'd) - Another method to save power is to apply intensity modulation to the displays
(Figure d). It is well known that LED displays are more efficient when operated in pulse mode. There are two
reasons: one, the quantum efficiency of the LED material is better; secondly the eye tends to peak detect.
Typically a 20% off duty cycle to displays (GaAsP) will produce the same brightness as operating under dc
conditions.
ALL INVERTERS ARE DTL 9936 OR OPEN COLLECTOR TTL 7405
LEAST SIGNIFICANT DECADE

MOST SIGNIFICANT DECADE
D1D2 D.DB

INVERTER CAN BE
IMPLEMENTED WITH
ONE TRANSISTOR AND
A RESISTOR FOR
EACH DECADE

I I I
I I I

I I I I I
I I I I I

I I

I I

I I

I I

I I

I I

I I

I I

,'---------------------~~---------------------------'~
TO 7-SEGMENT DISPLAYS

Fig. d

Intensity Control by RBO Pulse Duty Cycle

Low Power, Low cost Display Power Sources-In small line operated systems using TTL/MSI and LED or
incandescent displays, a significant portion of the total dc power is consumed to drive the displays. Since it is
irrelevant whether displays are driven from unfiltered dc or pulsed dc (at fast rates), a dual power system can be
used that makes better utilization of transformer rms ratings. The system utilizes a full wave rectified but
u nsmoothed dc voltage to provide the displays with 120 Hz pulsed power while the rest of the system is driven by
a conventional dc power circuit. The frequency of 120 Hz is high enough to avoid display flicker problems. The
main advantages of this system are:

• Reduced transformer rating
• Much smaller smoothing capacitor
• Increased LED light output due to pulsed operation
With the standard capacitor filter circuit, the rms current (full wave) loading of the tranformer is approximately
twice the dc output. Most commercial transformer manufacturers rate tranformers with capacitive input filters
as follows:
Full Wave Bridge Rectifier Circuit
Transformer rms current = 1.8 x dc current required
Full Wave Center Tapped Rectifier Circuit
Transformer rms current = 1.2 x dc current required
Therefore, the removal of a large portion of the filtered de current requirement (display power) substantially
reduces the transformer loading.

6-135

74
APPLICATIONS (Cont'd) - There are two basic approaches. First (Figure e) is the direct full wave rectified
unregulated supply to power the displays. The '74 decoder driver constant current feature maintains the
specified segment current after the LED diode drop and 0.5 V saturation voltage has been reached ("2.2 VI. Care
must be. exercised not to exceed the '74 power ratings and the maximum voltage that the decoder driver sees in
both the "on" and "off" modes.
The second approach (Figure f) usesa 3-terminal voltage regulator such as the 7805 to provide dc pulsed power
to the display with the peak dc voltage limited to +5.0 V. This approach allows easier system thermal
management by heat sinking the regulator rather than the display or display drivers. When this power source is
used with an intensity modulation scheme or with a multiplexed display system, the freq uencies must be chosen
such that they do not beat with the 120 Hz full wave rectified power frequency.

t
1~11
6:1

7.5 V

rma

LARGE
SMOOTHING
CAPACITOR

Fig. e

DATA

DATA

Direct Unregulated Display Supply

til

~

1~11
6:(

til

o
a:

1&1

J:

I-

o
oI-

Fig. f

Pulsed Regulated Display Supply

6-136

74
PARALLEL DATA SUPPLY SYSTEM WITH RIPPLE BLANKING

SYSTEM
CLOCK

4.,,"" I 4.,,"" I
DECADE OR
BINARY
COUNTER

II

4-BIT TTL
DECADE OR
BINARY
COUNTER

DECADE OR
BINARY
COUNTER

STROBE
INPUT

,r-

.rAo A1 A2 A3LERBl
9374

9374

RBO. b c d e l 9

W

'i'

VLED OR Vc c

RBO. b c d e I 9

I l""""'P

I

Ao A1 A2 A3LERBl

9374

Yo,"" f-----5'" ," ·,·
DIGITS

0::0

0::0

Oc==JO

Oc==JO

I

I

0::0
Oc==JO
MOST
SIGNIFICANT
DIGIT

LEAST
SIGNIFICANT
DIGIT

6-137

•

86
CONNECTION DIAGRAMS
PINOUT A

9386

-

AoO::

4-BIT QUAD EXCLUSIVE-NOR

BoII

lilA3

(With Open-Collector Outputs)

00 II

:mB3

01!:!

TIl 03

B1IT

~02

A11I

]]B2

GND[I

}]A2

DESCRIPTION - The '86 consists of four independent Exclusive-NOR gates
with open-collector outputs. Single 1-bit comparisons may be made with
each gate, or multiple bit comparisons may be made by connecting the
outputs of the four gates together. Typical power dissipation is 170 mW.
The 9386 is equivalent to the 8242.

PINOUT B

-

030:

TRUTH TABLE
INPUTS OUTPUT
An

Bn

On

L
H
L
H

L
L
H
H

H
L
L
H

PIN
OUT

:mB2

A3II

:mA2

H = HIGH Voltage Level
L = LOW Voltage Level

LOGIC SYMBOL
(DIP only)

Vcc = +5.0 V ±10%,
TA = -55°C to +125°C

Ceramic
DIP (0)

A

9386DC

Flatpak
(F)

~B1
~01

BoIT
00[2

Vcc = +5.0 V ±5%,
TA = O°C to +70°C
9386PC

~A1

AoIT

MILITARY GRADE

A

TIl GND

Vee!:!

COMMERCIAL GRADE

Plastic
DIP(P)

TIl 02

B31I

ORDERING CODE: See Section 9

PKGS

~Vee

PKG
TYPE
9A

9386DM

6A

iiiiilJJ

Ao Bo A1 B1 A2 B2 A3 B3

00

0,

02

! ! L
=
Vcc

B

9386FC

9386FM

31

Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
Ao,
A1,
A2,
A3,

Be
B1
B2
B3

00-03

DESCRIPTION
Gate
Gate
Gate
Gate
Gate

0 Inputs
1 Inputs
2 Inputs
3 Inputs
Outputs

93XX (U.L.)
HIGH/LOW
2.0/2.0
2.0/2.0
2.0/2.0
2.0/2.0
OC*/15

'oc- Open Collector

6-138

03

)1

86
LOGIC DIAGRAM
B,

Bo

Ao

B3

A3

00

03

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

93XX

PARAMETER
Min
A Input
B Input

UNITS

CONDITIONS

Max

5.5
5.5

liN (A) = 10 rnA, VIN (B) =OV
liN (B) = 10 rnA, VIN (A) =OV

BV;

Input Latch Voltage

IOH

Output HIGH Current

150

p.A

Vee = Min, VIN = VIH
VOUT = 4.5 V

lee

Power Supply Current

47.5

rnA

Vee = 5.25 V
VIN (A), VIN (B) = 0.4 V

V

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
93XX

SYMBOL

PARAMETER

CL = 30 pF
RL = 530 n
Min

Propagation Delay
An, Bn to 00-03

CONDITIONS

Max
25
25

6-139

UNITS

ns

Figs. 3-2, 3-20

I

9600
CONNECTION DIAGRAM
PINOUT A

9600
RETRIGGERABLE RESETTABLE
MONOSTABLE MULTIVIBRATOR
DESCRIPTION - The 9600 monostable, retriggerable, resettable multivibrator provides an output pulse whose duration and accuracy is a function of
external timing components. The 9600 has excellent immunityto noiseon the
Vee and ground lines. It uses TTL technology for high speed and high fan-out
capability and is compatible with all members of the Fairchild TTL family.
•
•
•
•

74 ns TO 00 OUTPUT PULSE WIDTH RANGE
RETRIGGERABLE 0% to 100% DUTY CYCLE
RESETTABLE
LEADING OR TRAILING-EDGE TRIGGERING

LOGIC SYMBOL
Vee

ORDERING CODE: See Section 9
PIN
PKGS

OUT

~

Cx

COMMERCIAL
GRADE
____________

~----

Vee = +5.0 V ±5%,
TA = O°C to +75°C

~

MILITARY GRADE
______________

~

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

Ceramic
DIP(Q)

A

9600DC

9600DM

6A

Flatpak
(F)

A

9600FC

9600FM

31

9600PC

--If-

11

Q

9A
Co

~

Vcc = 14
GND= 7

910

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

DESCRIPTION

96XX (U.L.)

HIGH/LOW

C01-C02
Q

Trigger Inputs (Active Falling Edge)
Trigger Inputs (Active Rising Edge)
Clear Inputs (Active LOW)
Pulse Output

1.5/1.0
1.5/1.0
1.5/1.0
2417.06

a

Complementary Pulse Output

(6.2)
2417.06
(6.2)

10,11
12-14

LOGIC DIAGRAM

1
2

3--':=---1

4-----+-'

5-----1

910

7-3

Rx

13

9600
FUNCTIONAL DESCRIPTION - The 9600 monostable multivibrator has five inputs, three active HIGH and two
active LOW. This allows leading-edge or trailing-edge triggering. The TTL inputs make triggering independent
of input transition times. When input conditions for triggering are met, a new cycle starts and the external
capacitor is rapidly discharged and then allowed to charge. An input cycle time shorter than the output cycle
time will retrigger the 9600 and result in a continuous true output (see Rule 8), Retriggering may be inhibited by
tying the negation (()) output to an active LOW input. The output pulse may be terminated at any time by
connecting either or both reset pins to a LOW logic level pin. Active pullups are provided on the outputs for good
drive capability into capacitive loads.
Operating Notes
1. An external resistor (Ax) and an external capacitor (Cx) are required as shown in the logic diagram. The value
of Rx may vary from 5.0 kO to 50 kO for 0° C to +75 0 C operation and from 5.0 kO to 25 kO for -55 0 C to+125° C
operation. Cx may vary from 0 to any necessary value available.
2. The following are recommended fixed values of Rx: Rx = 30 kO for 0° C to +75° C operation, Rx = 10 kO for
-55° C to +125° C operation.
3. The output pulse width (t) is defined as follows:
t = 0.32 RxCx [1 + 0.7/Rx[ Where Rx is in kO, Cx is in pF, t is in ns; for Cx < 103 pF. (see Figure a)
The value of Cx may vary from 0 to any value necessary and obtainable. If however, Cx has leakage currents
approaching 3.0 p,A or if stray capacitance from either pin 11 or pin 13 to ground exceeds 50 pF, the timing
equation may not represent the pulse width obtained.
4. If electrolytic type capacitors are to be used, the following three configurations are recommended.
A. Use with low leakage electrolytic capacitors (see Figure bl.
The normal RC configuration can be used predictably only if the forward capacitor leakage at5.0 V is less
than 3.0 p,A, and the inverse capacitor leakage at 1.0 V is less than 5.0 p,A overtheoperational temperature
range and Rule 3 above is satisfied.
B. Use with high inverse leakage current electrolytic capacitors. (Figure c; this configuration is not recommended with retriggerable operationJ
The diode in this configuration prevents high inverse leakage currents through the capacitor by preventing an inverse voltage across the capacitor.
t = 0.3 RCx
C. Use to obtain extended pulse widths. (Figure d; this configuration is not recommended with retriggerable operationJ
This configuration obtains extended pulse widths because of the larger timing resistor allowed by Beta
multiplication. Electrolytics with high inverse leakage currents can be used. 01 is an npn silicon transistor such as 2N5961 or 2N5962, with hFE, Rand Rx related as in the inequality below.
R < Rx (0.7) (hFE 01) or < 2.5 MO, whichever is less
Rx (Min) < Ry < Rx (Max) Ry' of 5.0 kO to 10 kO is recommended
t = 0.3 RCx
5. This circuit is recommended to obtain variable pulse width by remote trimming (Figure e).
6. Under any operating condition, Cx and Rx (min) must be kept as close to the circuit as possible to minimize
stray capacitance and reduce noise pickup.
7. Input Trigger Pulse Rules (see Triggering Truth Table Figures f and gl.
t1, t:3 = Min. positive input pulse width> 40 ns.
t2, 14 = Min. negative input pulse width> 40 ns.
8. The retrigger pulse width is equal to the pulse width t plus a delay time (see Figure hl. For pulse widths greater
than 500 ns, tw can be approximated as t.
tw = t + tPLH = 0.32 RxCx (1 + 0.7/Rx) + tPLH
9. Two overriding active LOW resets are provided (see Figure il. A LOW to either or both resets can terminate
any timing cycle and/or inhibit any new cycle until both reset inputs are restored to a HIGH. Trigger inputs
will not produce spikes in the output when either or both resets are held LOW.
10. Use of a 0.01 p,F to 0.1 p,F bypass capacitor located close to the 9600 is recommended.

7-4

9600
OUTPUT PULSE WIDTH VERSUS TIMING RESISTANCE
AND CAPACITANCE FOR Cx < 103 pF
For Cx 2 103 pF, t = 0.32 RxCx (1 + 0.7/Rx)

TRIGGERING TRUTH TABLE"
INPUT PINS

RESPONSE

1

2

3

4

5

9

10

X

X
L
X

X
X
L

X
X
X

X
X
X

L
X
X

X
X
X

No Trigger
No Trigger
No Trigger

H
H
X
X

H

H
X
L
H

H
X
X
H

H
X
X
H

H
X
X
H

Trigger
No Trigger
No Trigger
Trigger

10

\...
\...

,

10

\...
H
X
L

J
J

....r

l ;.
~~

II

~.
v-- ..

,

,0

~-I-/

10

f.)'l:) \'

Rx -= 20 kn

....''-

~">'

~

,

v

a
a

'Pins 1 &2 are logically interchangeable, as are pins 3, 4, 5, and
also 9 & 10.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

a
a

1

2

4 6 10

ex -

102

10'

TIMING CAPACITANCE - pF

Fig. a
Rx

VCC~PIN13
CX

+

e-PINll

Fig. b
R < 0,6 Rx (MAX)

Ry

vcc~

FD777

VCC~PIN13

Rx.> Rx (MIN)

PIN13~---b

0,

J..

'T

R

Cx

Cx

PIN 13

PIN 11

+ t::.-- PIN 11

Vee

It.. AS CLOSE AS

---1

R,< Rx (MAX) ·Rx

POSSIBLE
TO DEVICE
---

+ f::- PIN 11
Fig. d

Fig. c

Fig. f

Fig. g

Fig. e

Input on Pin 1 or 2

Input on Pin 3, 4 or 5

7-5

Remote Trimming

9600
INPUT

Q OUTPUT

INPUT

I-Iw--I

---.J

L

---------',

RESET

NOTE:
Retriggering will not occur if the retrigger pulse comes
within ~ 0.3 Cx ns after the initial trigger pulse
(i.e., during the discharge cycle time>.

Q

OUTPUT

Q OUTPUT

Fig. h

Fig. I

INPUT PULSE
I ~ 100 kHz
AMP ~ 3.0 V
WIDTH ~ 40 ns
tr = tf -:; 10 ns

Va

""r'-i.:
T

Va-NOTE:
Capacitance includes
Jig and Probe

1

\

V

••

Flg.j

NORMALIZED OUTPUT
PULSE WIDTH VERSUS
AMBIENT TEMPERATURE
1.1 0

1.05

I

NORMALIZED OUTPUT
PULSE WIDTH VERSUS
SUPPLY VOLTAGE
1.10

I

Vee = 5.0 V _
Rx "" 10 kU
ex'" 103 pF _

,

140

f-

T; = 251.e
Rx = 10kn
Cx=103 pF

f-

/'

1.05

./

........

"

1.00

t'---.

........

r-- "-- I--

1.00

75

T A - AMBIENT TEMPERATURE _oC

Fig. k

120 -

=
=
== 0

CL = 15 iF

V

r---

./

so

0.90

25

ex

100

V

0.9 5

-25

vc~
5.~ V
Rx 5 k!l

./V

0.95

0.90
-75

MINIMUM OUTPUT PULSE
WIDTH VERSUS
AMBIENT TEMPERATURE

125

4.0

4.5

5.0

5.5

Vee-SUPPLY VOLTAGE-V

Fig. I

7-6

6.0

60
-75

-

COMPLEMENTARY
OUTPUT-

.Y

"'-25

25

V
I'C'.

1/

./

V
TRUE._

°IUTPr
75

TA-AMBIENT TEMPERATURE-OC

Fig. m

/

125

9600
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
96XX

PARAMETER

SYMBOL

Min

CONDITIONS

UNITS
Max

VOL

Output LOW Voltage

~

0.4
0.45

V

IOL = 9.92 mA*1 V
- M·
10L - 11.3 mA
CC In

VOL

Output LOW Voltage

~

0.4
0.45

V

10L

VIH

Input HIGH Voltage

~

V

TA

= Max

VIL

Input LOW Voltage

~
XC

0.9
0.85

V

TA

= 25°C

ilL

Input LOW Current

~
XC

-1.6
-1.6

mA

VIN
VIN

= 0.4 V J
= 0.45 V I Vee = Max

los

Output Short
Circuit Current

Xc"

XM

-25
-35

mA

Vee = Max, VOUT
TA = 25°C

Ipo

Quiescent Power
Supply Drain

Xc"

XM

24
26

mA

Vee = 5.0 V,
Pins 1, 2 = Gnd

AC CHARACTERISTICS: Vee

XC

XC

XC

= +5.0 V,

TA

1.5
1.65

= +25° C (See

I

= 12.8 mA,

Vee = Max

= 1.0 V*

Section 3 for waveforms and load configurations)

96XX

PARAMETER

SYMBOL

CL

= 15 pF

Min

UNITS

CONDITIONS

Max

tPLH

Tn to Q

~
xc

45
56

ns

tPHL

Propagation Delay
T;, to Q

~
XC

40
47

ns

tw (Min)

Minimum Q Pulse Width

~

100
120

ns

Rx

tw (Min)

Minimum

9" Pulse Width

~

112
130

ns

Fig. 3-1, Fig. j

tw

Pulse Width

3.76
3.76

Ils

Rx = 10 kn, Cx
Fig. 3-1, Fig. j

Propagation Delay

XC

XC

AC OPERATING REQUIREMENTS: Vee
SYMBOL

~
XC

3.2
3.08

= +5.0 V,

TA

96XX

Min
Maximum Allowable Wiring
Capacitance (Pin 13)

Rx (Max)

M·
· t or
aXlmum T".
Imlng R
eSls

"Ground Pin 11 for VOL Pin 6 or VOH Pin 8 or

los

~
XC

=0

pF

= 5.0 n,

=0

pF

Cx

= 1000 pF

= +25°C

PARAMETER

CSTRAY

Rx = 5.0 n, Cx
Figs. 3-1, Fig. j

UNITS

CONDITIONS

Max

5.0
5.0

50

pF

Pin 13 to Gnd

25
50

kn

Over Operating
Temperature Range

Pin 8. open Pin 11 for VOL Pin 8 or VOH Pin 6 or

7-7

los

Pin 6.

9601
CONNECTION DIAGRAM
PINOUT A

9601
RETRIGGERABLE MONOSTABLE
MULTIVIBRATOR

10

-

0:

~vcc

I, []

. ImRX

., [1

IlliNC

.,11

ITIJcx
~NC
~NC
~Q

NCrr

DESCRIPTION - The 9601 is a retriggerable one-shot with versatile trigger
gating, rapid recovery, internally compensated reference levels, and high
speed capability. It is well suited for a broad variety of applications, including
pulse delay generators, square wave generators, long delay timers, pulse
absence detectors, and clock pulse generators.

a[!
GNOIT

• RETRIGGERABLE, 0% TO 100% DUTY CYCLE
• DC LEVEL TRIGGERING, INSENSITIVE TO TRANSITION TIMES
• COMPLEMENTARY INPUTS, FOR LEADING OR
TRAILING-EDGE TRIGGERING
• COMPLEMENTARY OUTPUTS, WITH ACTIVE PULL-UPS
FOR DRIVING LOAD CAPAC IT ANCE.
• PULSE WIDTH COMPENSATION FOR Vee
AND TEMPERATURE VARIATIONS
• 50 ns TO co OUTPUT PULSE WIDTH RANGE
• OPTIONAL RETRIGGER LOCK-OUT CAPABILITY

LOGIC SYMBOL

CX
lt

ORDERING CODE: See Section 9
PIN
PKGS

OUT

11

COMMERCIAL GRADE

MILIT ARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Rx
'f,3

~~
3.,
L.....J

1 _

A

9601 PC

Ceramic
DIP (0)

A

9601DC

9601DM

6A

Flatpak
(F)

A

9601FC

9601FM

31

9A
Vcc

= Pin 14
GND = Pin 7

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

To, T1

DESCRIPTION

Q

Trigger Input (Active Falling Edge)
Trigger Input (Active Rising Edge)
Positive Pulse Output

Q

Complementary Pulse Output

12, 13

96XX (U.L.)

HIGH/LOW
1.5/1.0
1.5/1.0
24/8.0
(18)/(6.25)
24/8.0
(18)/(6.25)

7-8

Q :"--8

2 •

4 .,

Plastic
DIP (P)

Vee
14

0--8

9601
FUNCTIONAL BLOCK DIAGRAM
Ct
Rt
.......t-JI,IVV- +5 V

r----Q

10----...
11-___~
12
b

DIFFERENTIATOR

.,L r-'\.U

=====::::t_J

L...y'

Io-.....~

. . . --_..1

SCHMITT
TRIGGER

TRIGGERING TRUTH TABLE
Pin 1 Pin 2 Pin 3 Pin 4
H
L
L

H
'X
X

\..

H
H
L

'\..

RESPONSE

..r

J
J

X
H
L

No Trigger
Triggers
No Trigger

H
L
X

H
X
X

Triggers
No Trigger
No Trigger

H = HIGH Vollage Level
L = LOW Voltage Level
X = Immaterial

OUTPUT tw vs Rx AND Cx

..
c

I
J:

l-

e

i

III

III
...J

:;)

'"
'"~

I-

:;)

o
I

~

10 4
8
6
Vee = 5.0 V
TA =+25°C

4

2

I

103
8
6
41--

I--

2
10 2
8

~'I-

II

/

II

~

V

. SO \<\\
V
1\'1- ""
0\<\\
3'1-""3",, '1-0 \l\\~\"\y

1--1--

V

V ~ VII

~"f.

","i
~"f.

~

V

-:?

V

6
4

2
0
1.0

4

68 10

2

4

6 8102

2

4

6 8103

NOTE:
Cx-TIMING CAPACITANCE-pF

Capacitance includes Jig and Probe

Fig. a

Fig. b

7-9

9601
FUNCTIONAL DESCRIPTION - The 9601 monostable multivibrator has four inputs, two active HIGH and two
active LOW. This allows a choice of leading-edge or trailing-edge triggering. The TTL inputs make triggering
independent of input transition times. When input conditions for triggering are met, a new cycle starts and the
external capacitor is rapidly discharged and then allowed to charge. An in put cycle ti me shorter than the output
cycle time will retrigger the 9601 and result in a continuous true output. Retriggering may be inhibited by tying
the negation (Q) output to an active LOW input. Active pullups are provided on the outputs for good drive
capability into capacitive loads.
Operation Notes
1. TRIGGERING - The 9601 has four dc coupled triggering inputs; pins 1 and 2 respond to falling edge signals, while pins 3 and 4 respond to rising edge Signals. Triggering occurs as the input signal passes through
the threshold region. Triggering logic is outlined in the Table. Input signals can be interchanged between
pins 1 and 2, since they are logically identical; the same relationship holds for pins 3 and 4.

2. RETRIGGERING -In a normal cycle, triggering initiates a rapid discharge of the external timing capacitor, followed by a ramp voltage run-up at pin 13. The delay will time out when the ramp voltage reaches
the upper trigger point of the Schmitt circuit, causing the outputs to revert to the quiescent state. If another
trigger occurs before the ramp voltage reaches the Schmitt threshold, the capacitor will be discharged and
the ramp will start again without having disturbed the outputs. The delay period can therefore be extended
for an arbitrary length of time by insuring that the interval between triggers is less than the delay time, as
determined by the external capacitor and resistor.
3. NON-RETRIGGERABLE OPERATION - Retriggering can be inhibited logically, by connecting pin 6 back
to pin 3 or 4, or by connecting pin 8 back to both pins 1 and 2.

4. OUTPUT PULSE WIDTH -An external resistor Rx and an external capacitor Cx are required, as shown in
the functional block diagram; to minimize stray capacitance and noise pickup, Rx and Cx should be located as close as possible to the circuit. In applications which require remote trimming of the pulse width, as
with a variable resistor, Rx should consist of a fixed resistor in series with the variable resistor; the fixed
resistor should be located as close as possible to the circuit. The output pulse width tw is defined as follows,
where Rx is in k!1, Cx is in pF and tw is in ns.
tw

= 0.32 RxCx (1

+ 0.7/Rx)

(for Cx > 103 pF; see also Figure aJ

The values of Rx may vary from 5.0 k!1 to 50 k!1 for 0° to +75°C operation, and 5.0 k!1 to 25 k!1 for -55° to
+125°C operation. Cx may vary from 0 to any value.
5. SETUP AND RELEASE TIMES

h, 14

=

Setup time> 40 ns

Input to Pin 1 (2)
Pins 2 (1),3 and 4 = 1

12.13 = Release time> 40 ns

Input to Pin 3 (4)
Pin 4 (3) = 1
Pins 1 or 2 = 0

6. CAPACITOR LEAKAGE-Recommendations on electrolytic capacitors and larger values of Rx are discussed in the 9600 data sheet.

7-10

9601
TYPICAL CHARACTERISTICS

Tn
~

~
....
e

...
...
CJ

l:
l-

e

«
I-

...

~

....

::l

Go

I::l
Go

40

I::l

~

--- - * -'(~

...
e

N

:::;
00(

IPHL COMPLEMENTARY-

20

1.0

0

\IE. 0\1

-25

o

25

.90

125

75

-75

TA - AMBIENT TEMPERATURE - 'C

OUTPUT tw VI Vee
TA = 25'C
Rx = 10 kll
Cx = 103 pF

...
~

........

Go

I::l 1.00

o

...e
N

./
0.95

i-"""

V

Vee = 5.0 V
Rx = 10 kll
Cx = 103 pF
TA=25'C

",.... f-"""

1.2

I-

~

-

l-

S

V'

1.0

...e
N

:::;
00(

~

o

0.8

Z

I
..!

0.90
4.0

4.5

5.0

6.0

5.5

0.6
20

Vee-SUPPLY VOLTAGE - V

40

.

I

l-

16

...
UJ
Go

/'

12

I::l
Go

I::l

0

I
..!

8.0

4.0
10

e

i

V
./

i

....

/
/'

V

70

R'IOI.l~~

...

tAEN"~
COtAP\.E~i"'"

UJ
....

I"

::l

I

Go

I::l

/

50

I

Go

I::l

o
z
i

TRUE OUTPUT
30

I

z
~
J

V
20

Vee = 5.0 V
Rx = 5.0 kll
Cx = 0

l:

e

::l

90

"I

Vee =5.0V
Cx=103 pF

"-

%

OUTPUT tw vs T A

OUTPUT tw VI Rx

..

100

80

60

OPERATING DUTY CYCLE -

20

l-

125

Go

z

l:

"

::l

......

o

I
..!

75
TA-AMBIENT TEMPERATURE - 'C

i

1.05

I::l

IX

'~

25

ie!=

Go

:I!

o

-25

1.4

::l

00(

r-.....

OUTPUT tw vs DUTY CYCLE

1.10

:::;

.......,

I
..!

o

-75

i
III....

"'"

z

I

~

Vee =5.0V
Rx = 10kll
Cx = 103 pF

.95

:I!
0

IX

O~TPUI

o

2;

1.05

UJ

...>
...zCJ

"

i

60

IX

CJ

,

1.1
Vee = 5.0 V
CL = 15 pF

...I
:I!
i=

OUTPUT tw VI T A

DELAY TIME VI TA

80

30

40

10

-75

50

-25

25

75

TA - AMBIENT TEMPERATURE _ 'C

Rx - EXTERNAL TIMING RESISTOR - kll

7-11

125

9601
DC AND AC CHARACTERISTICS OVER COMMERCIAL TEMPERATURE RANGE: Vee = +5.0 V except as noted.
O°C

PARAMETER

SYMBOL

Min

+25°C

Max

Min

Max

+75°C
Min

UNITS

CONDITIONSl

V

Vee = 4.75 V
10H = -0.96 mA

V

Vee = 4.75 V
10L = 12.8 mA

Max

VOH

Output HIGH Voltage 2

VOL

Output LOW Voltage 2

VIH

Input HIGH Voltage 3

VIL

Input LOW Voltage 3

0.85

0.85

0.85

V

hL

Input LOW Current

-1.6

-1.6

~1.6

mA

Vee = 5.25 V
VIN = 0.45 V

hH

Input HIGH Current

60

60

IlA

Vee = 5.25 V
VIN = 4.5 V

los

Output Short Circuit Current2

mA

VOUT

Icc

Power Supply Current

tPLH

Propagation Delay
Tn to

40

ns

Rx = 5.0 kO
CL = 15 pF
Cx = 0, Fig. b

tPHL

Propagation Delay
Tn to Q

40

ns

Rx = 5.0 kO
CL = 15 pF
Cx = 0, Fig. b

tw (min)

Minimum True Output
Pulse Width

65

ns

Rx = 5.0 kO
CL = 15 pF
Cx = 0, Fig. b

tw

Pulse Width

3.76

IlS

Rx=10kO
Cx = 1000 pF
Fig. b

CSTRAY

Maximum Allowable
Wiring Cap. (Pin 13)

50

pF

Pin 13 to Gnd

Rx

Timing Resistor

50

kO

2.4

2.4
0.45

1.9

0.45
1.8

-10
25

3.08

50
50

0.45
1.6

25

50
5.0

V

-40
25

a

5.0

2.4

50

5.0

(1) Unless otherwise noted. 10 kU resistor placed between Pin 13 and Vee. for all tests. !Axl
(21 Ground Pin 11 for VOL Pin 6 or VOH Pin 8 or los Pin 8. Open Pin 11 for VOL Pin 8 or VOH Pin 6 or los Pin 6.
(31 Pulse Test to determine VIH and VIL (Min tw 40 nsl.

7-12

mA

=0 V
Vee = 5.25 V
Gnd Pins 1, 2

9601
DC AND AC CHARACTERISITCS OVER MILITARY TEMPERATURE RANGE: Vee = +5.0 V except as noted
SYMBOL

PARAMETER

-55°C
Min

+25°C

Max

2.4

Min

Max

2.4

+125°C
Min

UNITS

CONDITIONSI

V

Vee = 4.5 V
10H = -0.72 mA

V

Vee = 4.5 V
10L = 10 mA

Max

2.4

VOH

Output HIGH Voltage 2

VOL

Output LOW Voltage 2

VIH

Input HIGH Voltage3

VIL

Input LOW Voltage 3

0.85

0.9

0.85

V

IlL

Input LOW Current

-1.6

-1.6

-1.6

mA

Vee = 5.5 V
VIN = 0.4 V

hH

Input HIGH Current

60

60

/1 A

Vee = 5.5 V
VIN ~ 4.5 V

los

Output Short Circuit Current

mA

VOUT = 0 V

Icc

Power Supply Current

mA

Vee = 5.5 V
Gnd Pins 1, 2

tPLH

Propagation Delay
Tn to Q

40

ns

Rx = 5.0 kO
CL = 15 pF
Cx = 0, Fig. b

tPHL

Propagation Delay
Tn to Q

40

ns

Rx = 5.0 kO
CL = 15 pF
Cx = 0, Fig. b.

tw (min)

Minimum True Output
Pulse Width

65

ns

Rx = 5.0 kO
CL = 15 pF
Cx = 0, Fig. b

tw

Pulse Width

3.76

/1s

Rx = 10 kO
Cx = 1000 pF
Fig. b

CSTRAY

Maximum Allowable
Wiring Cap. (Pin 13)

50

pF

Pin 13 to Gnd

Rx

Timing Resistor

25

kO

0.4
2.0

0.4
1.7

-10
25

50
25

1.5

25

50
5.0

V

-40
25

3.08

5.0

0.4

25

5.0

III Unless otherwise noted, 10 kll resistor placed between Pin 13 and Vee. for all tests. IRxl
121 Ground Pin 11 for VOL Pin 6 or VOH Pin 8 or los Pin 8. Open Pin 11 for VOL Pin 8 or VOH Pin 6 or los Pin 6 '
131 Pulse Test to determine V,H and V,L IMin tw 40 nsl,

7-13

9602 • L02
CONNECTION DIAGRAM
PINOUT A

9602
96L02

DESCRIPTION - The 9602 is a dual TTL monostable multivibrator with trigger mode selection, reset capability, rapid recovery, internally compensated
reference levels and high speed capability. Output pulse duration and accuracy depend on external timing components, and are therefore under user
control for each application. It is well suited for a broad variety of applications, including pulse delay generators, square wave generators, long delay
ti mers, pulse absence detectors, frequency detectors, clock pulse generators
and fixed-frequency dividers. Each input is provided with a clamp diode to
limit undershoot and minimize ringing induced by fast fall times acting on system wiring impedances.
•
•
•
•
•
•
•
•

-

CX1[I

DUAL RETRIGGERABLE RESETTABLE
MONOSTABLE MULTIVIBRATOR

RETRIGGERABLE, 0% TO 100% DUTY CYCLE
DC LEVEL TRIGGERING, INSENSITIVE TO TRANSITION TIMES
LEADING OR TRAILING-EDGE TRIGGERING
COMPLEMENTARY OUTPUTS WITH ACTIVE PULL-UPS
PULSE WIDTH COMPENSATION FOR ilVee AND ilTA
50 ns TO 00 OUTPUT PULSE WIDTH RANGE
OPTIONAL RETRIGGER LOCK-OUT CAPABILITY
RESETTABLE, FOR INTERRUPT OPERATIONS

~vcc

Rx,ll

~CX2

COl [!

hI!

IB1 RX2
I!!l CO2

To I!

Imll

a,l!

TIlTo

0, IT

~a2

GNO[!

r!l02

LOGIC SYMBOL

Cx

(15)

l~i T2

Rx

Vee
18

(14)
0-8(10)

ORDERING CODE: See Section 9
PIN
PKGS

OUT

(12)~=D

(11) 5

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +70°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

T

PKG

Q

C>--7(9)

cO

TYPE

(113

Plastic
DIP(P)

A

9602PC, 96L02PC

Ceramic
DIP (D)

A

9602DC, 96L02DC

9602DM, 96L02DM

68

Flatpak
(F)

A

9602FC, 96L02FC

9602FM, 96L02FM

4L

98

Vec

= Pin 16
GNO = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

To

DESCRIPTION

Q

Trigger Input (Active Falling Edge)
Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
Positive Pulse Output

Q

Complementary Pulse Output

h

Co

7-14

96XX (U.L.)
HIGH/LOW

96L (U.L.)
HIGH/LOW

1.5/1.0
1.5/1.0
1.5/1.0
2417.0
(6.2)
2417.0
(6.2)

0.5/0.25
0.5/0.25
0.5/0.25
9.0/3.0
9.0/3.0

9602 • L02
FUNCTIONAL BLOCK DIAGRAM

.......o--*--I>.::...Q 7 (')

r:jC>---i~)o-Lt>:Q!!...6 (10)

3(13)

GND 8

OPERATION NOTES
1. TRIGGERING-can be accomplished by a positive-going transition on pin 4 (121 or a negative-going
transition on pin 5 (11), Triggering begins as a signal crosses the input VIL:VIH threshold region; this activates
an internal latch whose unbalanced cross-coupling causes it to assume a preferred state. As the latch output
goes LOW it disables the gates leading to the Q output and, through an inverter, turns on the capacitor
discharge transistor. The inverted signal is also fed back to the latch input to change its state and effectively
end the triggering action; thus the latch and its associated feed-back perform the function of a differentiator.
The emitters of the latch transistors return to ground through an enabling transistor which must be turned
off between successive triggers in order for the latch to proceed through the proper sequence when triggering is desired. Pin 5 (11) must be HIGH in order to trigger at pin 4 (12); conversely, pin 4 (12) must be LOW
in order to trigger at pin 5 (11).
2. RETRIGGERING -In a normal cycle, triggering initiates a rapid discharge of the external timing capacitor,
followed by a ramp voltage run-up at pin 2 (14). The delay will time out when the ramp voltage reaches the
upper trigger point of a Schmitt circuit, causing the outputs to revert to the quiescent state. If another trigger
occurs before the ramp voltage reaches the Schmitt threshold, the capacitor will be discharged and the ramp
will start again without having disturbed the output. The delay period can therefore be extended for an arbitrary length of time by insuring that the interval between triggers is less than the delay time, as determined
by the external capacitor and resistor.
3. NON-RETRIGGERABLE OPERATION-Retriggering can be inhibited logically, by connecting pin 6 (10)
back to pin 4 (12) or byconnecting pin 7 (9) back to pin 5 (11), Either hook-up has the effect of keeping the
latch-enabling transistor turned on during the delay period, which prevents the input latch from cycling as
discussed above in the section on triggering.
4. OUTPUT PULSE WIDTH -An external resistor Rx and an external capacitor Cx are required, as shown in
the functional block diagram. To minimize stray capacitance and noise pickup, Rx and Cx should be located
as close as possible to the circuit. In applications which require remote trimming of the pulse width, as with
a variable resistor, Rx should consist of a fixed resistor in series with the variable resistor; the fixed resistor
should be located as close as possible to the circuit. The output pulse width tw is defined as follows, where Rx
is in k!l, Cx is in pF and tw is in ns.
tw = 0.31 RxCx (1 + 1/Rx) for Cx ~ 103 pF
5 k!l:::; Rx:::; 50 k!l for O°C to +75°C
5 k!l :::; Rx :::; 25 k!l for -55° C to +125° C
(96L02) tw = 0.33 RxCx (1 + 3/Rx) for Cx ~ 103 pF
16 k!l:::; Rx:::; 220 k!l for O°C to +75°C
20 k!l:::; Rx:::; 100 k!l for -55°C to +125°C
Cx may vary from 0 to any value. For pulse widths with Cx less than 103 pF see Figures a and b.

(9602)

7-15

9602 • L02
OPERATION NOTES (Cont'd)
5. SETUP AND RELEASE TIMES- The setup times listed below are necessary to allow the latch-enabling
transistor to turn off and the node voltages within the input latch to stabilize, thus insuring proper cycling
of the latch when the next trigger occurs. The indicated release times (equivalent to trigger duration) allow
time for the input latch to cycle and its signal to propagate.

Input to Pin 5 (11)
Pin 4 (12) = L
Pin 3 (13) = H

Input to Pin 4 (12)
Pins 5 (11) and 3 (13) = H

12. ta = RELEASE TIME> 40 ns ('02)

1,.14 = SETUP TIME> 40 ns ('02)

> 60 ns (,L02)

>60 ns (,L02)

Co, pin 3 (13), will terminate an output pulse, causing Q to go LOW
andQ to go HIGH. As long as CD is held LOW, a delay period cannot be initiated nor will attempted triggering cause spikes at the outputs. A reset pulse duration, in the LOW state, of 25 ns is sufficient to insure
resetting. If the reset input goes LOW at the same ti me that a trigger transition occurs, the reset will dominate and the outputs will not respond to the trigger. If the reset input goes HIGH coincident with a trigger
transition, the circuit will respond to the trigger.

6. RESET OPERATION- A LOWsignal on

7. CAPACITOR LEAKAGE- For recommendations on electrolytic capacitors and larger values of Rx, please
see the 9600 data sheet.
9602 PULSE WIDTH vs Rx AND Cx

96L02 PULSE WIDTH vs Rx AND Cx
102

10 4

8

8
6

•
'!

[

w

8 I--Rx

..

41-- Rx = 120 kn ' \

~

8

I

4

200 kn

:c
c

/

-

1.0

......

w

/

II)

'/ /

.

4

6810

2

/

6 8102 2

..

2

....
&~
r-<
,...-

4

~K

10 2

0

8
6

I

4
2

68103

Cx-TIMINGCAPACITANCE-pF

Fig.

~

8
6

4

.!

jX = jO i!i

4

/' l/:V

10 3

...l

...
...::I

Vl/

4
2

::I

Rx =80kn
['-- Rx = 39 kn

./~
I--"

2

iii

::I

,-V
O. 1

y

" ; ' /1-"

,
~ 1.0
o
.!

.
I

./ "/1/

iii 1~

!l

:!!

/

10
1.0

2

4

6810

2

4

/. v/

V
Rx = 50 kll
Rx=30kll
Rx=20kll
Rx = 10 kll
I Rx 15 kll

I

68102

2

4

Cx-TIMING CAPACITANCE-pF

a

Fig. b

7-16

68103

9602 • L02
TYPICAL CHARACTERISTICS

9602 tw VI Vee

96L02 tw VI Vee

1.10

"...
.,"'

1.05

...::>
...::>

1.00

j!;

Q

i

.
.
..J

r-

::>

0

L"

«

a::

0

z

V

1.1 r-

~

1.0

...
Q

~

T~ = 251,C

Rx
Cx

~

~

I---

0.9

:I

a::

o
z

I

0.90
4.0

4.5

5.0

5.5

8.0

O. 8
4.0

4.5

9602

TA

tw(min) VI

96L02

.

140

c

Q

i

.,"'
::>

....
....
..J

0

z

i

"...
Q

i

I
E

J

125

....
....

-

::>

/

./
COMPLEMENTAY
OUTPUT

-r

I"'---

TRUj OUlpUT
-25

--

V

0

z

:iii

f-'"""

.....
....
..J

75

E
50
-75

125

-25

::>

::>
::>
0

1.0

"'

I'....

...
N

::i

«

:I

a::

veJ = 5.01V
Rx = 39 k!!
Cx = 1000 pF

j!;
Q

i
...
!l

....

1.01

"

-- -

~

...::>

o

""-

1.00

~

.............

Q

I!;I

- "

..,-

~

:I 0.99

.95

a::

o
z
I

0

z

I
.J

125

96L02 tw VI T A

::>

Q

75

1.02

ve~ = 5.0 V

.......

25

TA - AMBIENT TEMPERATURE - 'C

Rx = 10k!! Cx = 103 pF

1.05

"-

J

1

b
i

-!!!.U.!.2!!te.!!r.

I

9602 tw VI TA
1.1
%

~

Vee = 5.0 V
-Rx =20kll
Cx =0

::>

75

25

::> 100

TA - AMBIENT TEMPERATURE - ' C

.,"'

TA

COMPLEMENTAR#-

II)

70
80
-75

tw(min) VS

150

"'..J

90
80

8.0

I

Vee ~ 5.0 V
120 ;-- Rx ~ 5 kll
Cx =0
CL = 15 pF
110

::> 100
::>

5.5

c

I 130

"...

5.0

Vee - SUPPLY VOLTAGE - V

vee-SUPPLY VOLTAGE-V

.

I

39 kll
1000 pF

---

~

~

N

I

.J

..J

o

V"

V

I-

.,...
::>
...::>

.
.

/'
/'

"'N

:I 0.95

i

./

Q

::i

1.2

Q

TAl ~ 25}C
Rx ~ 10 kll
Cx ~ 103 pF

.90
-75

.J

-25

0

25

75

125

0.98
·75 -50

-25

25

50

75

100

TA-AMBIENTTEMPERATURE-'C

TA-AMBIENT TEMPERATURE-'-'C

7-17

125

9602 • L02
DC AND AC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
96XX

PARAMETER

SYMBOL

Min
VOH

VOL

UNITS

12.4

Output HIGH Voltage

V

XM

0.4

V

XC

0.45

V

-

Output LOW Voltage

~
XC

CONDITIONS

Max

Vee = 4.5 VIOL = 9.92 mA
Vee = 5.5 V, 10L = 12.8 mA
Vee =4.75 V, 10L -11.3mA
Vee = 5.25 V, 10L = 12.8 mA

V

Guaranteed Input
HIGH Threshold

0.85

V

Guaranteed Input
LOW Threshold

-1.6

mA

Vee = Max, VIN = VOL

-1.24
-1.14

mA

Vee = Min, VIN = VOL

60

IlA

Vee = Max, VIN = 4.5 V

~
XC

-25
-35

mA

Vee = Max, VOUT = 1.0 V

Power Supply Current

~
XC

45
52

mA

Vee = 5.0 V

tPLH

£,ropagation Delay
10 to Q

~
XC

35
40

ns

Rx = 5 k!I, Cx = 0
CL = 15 pF, Fig. c

tPHL

Propagation Delay

To to Q

~
xc

43
48

ns

Rx = 5 k.o., Cx = 0
CL = 15 pF, Fig. c

~

tw (min)

Minimum Output
Pulse Width

90
100
100
110

ns

Rx = 5 k.o., Cx = 0
CL = 15 pF, Fig. c

3.76

IlS

Rx = 10 k.o.
Cx = 1000 pF, Fig. c

50

pF

25
50

k.o.

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

hL

Input LOW Current

hL

Input LOW Current

hH

Input HIGH Current

los

Output Short
Circuit Current

lee

2.0
1.9

Vee = Min, 10H = -9.6 mA

~
XC

at Q
at

XC

Q~
XC
3.08

tw

Output Pulse Width

CSTRAY

Maximum Stray Capacitance
from Pin 2 (14) to Gnd

Rx

Timing Resistor Range

~
XC

5.0
5.0

7-18

9602 • L02
DC AND AC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
96L

PARAMETER

SYMBOL

Min
VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

hH

Input HIGH Current

UNITS

2.4

V

Vee = Min, 10H = -0.36 mA

V

Vee = Min, 10L = 4.8 mA

V

Guaranteed Input
HIGH Threshold

0.7

V

Guaranteed Input
LOW Threshold

20
1.0

mA

VIN = 2.4 V
VIN = 5.5 V

-0.4

mA

Vee = Max, VIN = 0.3 V

-13

mA

Vee = Max, VOUT = 1.0 V

16

mA

Vee = Max

ns

Vee = 5.0 V, Rx = 20 kO
Cx = 0, CL = 15 pF
TA=2SoC

ns

Vee = 5.0 V, Rx = 20 kO
Cx = 0, CL = 15 pF
TA = 25°C

ns

Vee = 5.0 V, Rx = 20 kO
Cx = 0, CL = 15 pF
TA = 25°C

15.2

J1.S

Vee = 5.0 V, Rx = 39 kO
Cx = 1000 pF, TA = 25°C
Rx = 39 kO, Cx = 1000 pF

0.3
2.0

J1.A

hL

Input LOW Current

los

Output Short Circuit Current

Icc

Power Supply Current

tPLH

Propagation Delay
To to

XM

xc

75
80

tPHL

To

Propagation Delay
to Q

XM
XC

62
65

tw (min)

Minimum Output Pulse Width
at

tw

Output Pulse Width

At

Change in
Pulse Width
Over Temperature

XC

1.6

%

Rx

Timing Resistor Range

XM
XC

100
220

kO

a

-2.0

110'

a

a

CONDITIONS

Max

12.4

'Typical Value

r,100n'j
INPUT PULSE
1.SV

v"

Va

t~I
I

Vo

f '" 25 kHz
Amp'" 3.0 V
Width", 100 ns
tr '" tf ::; 10 ns

~
"-~

I.

{

F

~,-~
Fig. c
7-19

Vee = Max

96802 • 96L802
CONNECTION DIAGRAM
PINOUT A

96802
96L802
eXl

DUAL RETRIGGERABLE RESETTABLE
MONOSTABLE MULTIVIBRATOR
DESCRIPTION - The 96S02 and 96LS02 are dual retriggerable and resettable monostable multivibrators. These one-shots provide exceptionally wide
delay range, pulse width stability, predictable accuracy and immunity to
noise. The pulse width is set by an external resistor and capacitor. Resistor
values up to 1.0 MO for the 96LS02 and 2.0 MO for the 96S02 reduce required
capacitor values. Hysteresis is provided on both trigger inputs of the 96LS02
and on the positive trigger input of the 96S02 for increased noise immunity.

IT

~

j!Jvcc

Rx,!!

mCX2

CD,I:[

:mRX2

h[i

:meD2

10 IT

:mh

o,lI
th II

~IO
~O2

GNOI!

~Q2

• REQUIRED TIMING CAPACITANCE REDUCED BY FACTORS
OF 10 TO 100 OVER CONVENTIONAL DESIGNS
• BROAD TIMING RESISTOR RANGE-1.0 kO to 2.0 MO
• OUTPUT PULSE WIDTH IS VARIABLE OVER A 2000:1 RANGE
BY RESISTOR CONTROL
• PROPAGATION DELAY OF 35 ns 96LS02, 12 ns 96S02
• 0.3 V HYSTERESIS ON TRIGGER INPUTS
• OUTPUT PULSE WIDTH INDEPENDENT OF DUTY CYCLE
• 35 ns TO co OUTPUT PULSE WIDTH RANGE

LOGIC SYMBOL

Cx
(15) l r

Rx

T2 (14)

0-6(10)

ORDERING CODE: See Section 9
PIN
PKGS

OUT

(12)~=D

COMMERCIAL GRADE

MILITARY GRADE

Vee"" +5.0 V ±5%,
TA"" O°C to +70°C

Vee"" +5.0 V ±10%,
TA "" -55°C to +125°C

PKG

(11) 5

TYPE

Plastic
DIP (P)

A

96S02PC, 96LS02PC

Ceramic
DIP (D)

A

96S02DC, 96LS02DC

96S02DM, 96LS02DM

68

Flatpak
(F)

A

96S02FC, 96LS02FC

96S02FM, 96LS02FM

4L

98

T

o C>---7 (9)
CD

(lX3
Vee = Pin 16
GND = Pin 8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

96S (U.L.)
HIGH/LOW

DESCRIPTION

Q

Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Rising Edge)
Direct Clear Input .(Active LOW)
True Pulse Output

Q

Complementary Pulse Output

10
10

h

CD

Vee
16

0.5/0.625
0.5/0.625
0.5/0.625
25/12.5
25/12.5

7-20

96LS (U.L.)
HIGH/LOW
0.5/0.25
0.5/0.25
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

96S02 • 96LS02
LOGIC DIAGRAM
r-!a?..6 (10)

POSITIVE
TRIGGER

FUNCTIONAL DESCRIPTION - The 96802 and 96L802 dual retriggerable resettable monostable multivibrators have two dc coupled trigger inputs perfunction, one active LOW (To) and one active HIGH (Ill. The 11 input of
both circuit types and the To input of the 96L802 utilize an internal 8chmitt trigger with hysteresis of 0.3 V to
provide increased noise immunity. The use of active HIGH and LOW inputs allows either rising or falling edge
triggering and optional non-retriggerable operation. The inputs are dc coupled making triggering independent
of input transition times. When input conditions for triggering are met the Q output goes HIGH and the external
capacitor is rapidly discharged and then allowed to recharge. An input trigger which occurs during the timing
cycle will retrigger the circuit and result in Q remaining HIGH. The output pulse may be terminated (Q to the
LOW state) at any time by setting the Direct Clear input LOW. Retriggering may be inhibited by tying the'a
output to To or the Q output to 11. Differential sensing techniques are used to obtain excellent stability over
temperature and power supply variations and a feedback Darlington capacitor discharge circuit mini mizes
pulse width variation from unit to unit. 8chottky TTL output stages provide high switching speeds and output
compatibility with all TTL logic families.
Operation Notes
TIMING
1. An external resistor (Ax) and an external capacitor (Cx) are required as shown in the Logic Diagram. The
value of Rx may vary from 1.0 kn to 1.0 Mn (96L802) or 2.0 Mn (96802).
2. The value of Cx may vary from 0 to any necessary value available. If, however, the capacitor has significant
leakage relative to Vee/Rx the timing equations may not represent the pulse width obtained.
3. Polarized capacitors may be used directly. The (+) terminal of a polarized capacitor is connected to pin 1
(15), the (-) terminal to pin 2 (14) and Rx. Pin 1 (15) will remain positive with respect to pin 2 (14) during the
timing cycle. In the 96802, however, during quiescent (non-triggered) conditions, pin 1 (15) may go negative
with respect to pin 2 (14) depending on values of Rx and Vee. For values of Rx 210 kn the maximum amount
of capacitor reverse polarity, pin 1 (15) negative with respect to pin 2 (14) is 500 mV. Most tantalum electrolytic capacitors are rated for safe reverse bias operation up to 5% of their working forward voltage rating;
therefore, capacitors having a rating of 10 WVdc or higher should be used with the 96802 when Rx 210 kn.
4. The output pulse width tw for Rx 2 10 kn and Cx 2 1000 pF is determined as follows:
(96802)
tw = 0.55 RxCx
(96L802) tw = 0.43 RxCx
Where Rx is in kO, Cx is in pF, t is in ns or Rx is in kO, Cx is in IlF, t is in ms.
5. The output pulse width for Rx < 10 kO or Cx < 1000 pF should be determined from pulse width versus Cx or
Rx graphs.
6. To obtain variable pulse width by remote trimming, the following circuit is recommended:

1.0 kll

PIN2(14)~
PIN 1 (15)

o-J

___

-----b

' - - AS CLOSE AS POSSIBLE

Rx -1.5 kll

TO DEVICE

Vee 0 - - -

-

-

7-21

-

-

-

-

-

96802 • 96L802
Operation Notes (Cont'd)
7. Under any operating condition, Cx and Rx (Min) must be kept as close to the circuit as possible to minimize
stray capacitance and reduce noise pickup.
8. Vee and ground wiring should conform to good high frequency standards so that switching transients on
Vee and ground leads do not cause interaction between one shots. Use of a 0.01 f.LF to 0.1 f.LF bypasscapacitor between Vee and ground located near the circuit is recommended.
TRIGGERING
1. The minimum negative pulse width into To is 8.0 ns; the minimum positive pulse width into 11 is 12 ns.
2. Input signals to the 96502 exhibiting slow or noisy transitions should use the positive trigger input 11 which
contains a Schmitt trigger. Input signals to the 96LS02 exhibiting slow or noisy transitions can use either
trigger as both are Schmitt triggers.
3. When non-retriggerable operation is required, i.e., when input triggers are to be ignored during quasi-stable
state, input latching is used to inhibit retriggering.

Q ......-

.....-OUTPUT

Lr---V"

r"l..
INPUT

INPUT-~
Q

Q ......---OUTPUT

-

~

QP--

0--

Co

r"l..

CD

r

r

NEGATIVE EDGE TRIGGER

POSITIVE EDGE TRIGGER

4. An overriding active LOW level direct clear is provided on each multivibrator. By applying a LOW to the clear,
any timing cycle can be terminated or any new cycle inhibited until the LOW reset input is removed. Trigger
inputs will not produce spikes in the output when the reset is held LOW. A LOW-to-HIGH transition on Co
will not trigger the 96502 or 96LS02. If the Co input goes HIGH coincident with a trIgger transition, the circuit
will respond to the trigger.

TRIGGERING TRUTH TABLE
PIN NO'S.
5(11) 4(12) 3(13)
H-L L
H
L....H

H
H

X

L

X

OPERATION
Trigger
Trigger
Reset

H = HIGH Voltage Level'" VIH
L = LOW Voltage Level :5 VIL
X = Immaterial (either H or L)
H~L = HIGH to LOW Voltage Level transition
L~H = LOW to HIGH Voltage Level transition

7-22

96502 • 96L502
TYPICAL CHARACTERISTICS

96S02
h DELAY TIME vs TA

OUTPUT tw vs Rx and ex
17

.
c

.,I
I:::l

I-- ~ee_~ 5.0 V
C,-15 P

15

0
0

I.:;;;

>
c(

j

-~

COMPLEMENT OUTPUT ( 0 ) -

tPHL

a..

I:::l

J

.1

16

14

-

13

..J

w

e

12

I
0

~

1.~ .'::-0-!!--'--!'-'-!'S~.~1:-0-!:,--'--!-,.LS~.l~O""--:!-,...J....'!-'-!SUJ.LJ,!103

11

1ooL----'---2~5----'---5.L0----..L..--~75

Iw - OUTPUT PULSE WIDTH -~.

TA -AMBIENT TEMPERATURE _oC

To DELAY TIME vs TA

OUTPUT tw vs T A

15r---~----~--~----~---'----,

14

Vee
CL

~

5.0 V_-+_ _+-_~
15 pF

~

42,..---,----r---,----,---,----,

__-I

8.0 0~---'-----'2~5'----'----5~0,---..L..---7-!5

28~0----~--~2~5-----'---~5~0,----'---~75TA-AMBIENT TEMPERATURE-oC

TA - AMBIENT TEMPERATURE _ °C

NORMALIZED Mw vs TA
~ +1.0,..--..----y--;---,--,--,
z
o +0.8~-+--t---+~
ii +0.6 f---"'-.I---t---+-

~

I

l:
l-

e

+0.4 ~-+-"""k:::-­

iw

l-

e

~
:::l
a..

i

.,w
a.. -0.2

N

:;
c(

::E

II:

0

z

-0.4

4

-0.6

E

~I=

-0.8

a..

2

~

I -1.0

~

•,

,3
o~ 10,
.,> •
SF

:::l

0

+25

+50

0

1 1.0

+75

.k.lI·

103

I-

..J

ew

PULSE WIDTH vs RxCx

,
,S
,3

10

c(

;

V

IPLH TRUE OUTPUT (0)

..
2

3 4

"'"

6 810

2

3 4

6

8102

2

TIMING CAPACITOR Cx - pF

TA - AMBIENT TEMPERATURE _ °C

7-23

3 4

6 8103

•

96802 • 96L802
TYPICAL CHARACTERISTICS
96LS02

h DELAY TIME

OUTPUT tw VI Rx and Cx
103
8
6
4

~
I

2

!c

L~
i=

........ .....

r--

28
-55 -35 -15

:!

100 pF-

III

IPHL - COMPLEMENT OUTPUT (0)

z
o

~

~~c~~1~.~~ -

...~

30

!

85 105 125 145

OUTPUT tw VI T A

~

36

III
Q

65

I

,.s1

S r-....
.........

45

c

I-- I--

IPLH - TRUE OUTPUT (0)

25

10 0

%

1/

L,....-~

+5

(~) F--

TA-AMBIENT TEMPERATURE-·C

Iw-OUTPUT PULSE WIDTH (pi)

8

i,....-

"

~

S.

2

i'..

15 pF

~

44 I-- I-- IPLH - TRUE OUTPUT (0) f-- f--

5 I\,

...~ 10 kO Vee = 4.75 V
Rx > 1.0 ~O
to 5.25 V

2.0

0.5
0.5
-0.85
-0.5
-0.4

3.0
3.0
3.0

CONDITIONS

V

2.0

XM

UNITS

Max

0
0
0

20

20

IJ.A

0.1

0.1

rnA

-1.0

-0.4

rnA

-40 -100

-20 -100

rnA

75

36

rnA

= Min, VIN = VIH or VIL

= 2.7 V
=
= 5.5 V ('S02) Vee
Max
= 10 V (,LS02)
VIN = 0.4 V, Vee = Max
Vee = Max, VOUT = 0 V
VIN = Open, Vee = Max

VIN
VIN
VIN

r,'~.=j

INPUT PULSE

~.,
-''"~

l

I

f'" 100 kHz
Amp "'3.0 V
Width'" 100 ns
tr = tf:5 5 ns

~

~~---1

~\
.~~

Fig. a

7-25

F

I

96S02 • 96LS02
AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
96S
PARAMETER

SYMBOL

Min
Propagation Delay

tPLH

To to Q

tPHL

To to Q

96LS

CL = 15 pF CL = 15 pF

Propagation Delay

Max

Min

UNITS

CONDITIONS

Max

15

55

ns

19

50

ns

tPLH

Propagation Delay
11 to Q

19

60

ns

tPHL

Propagation Delay
11 to Q

20

55

ns

tPHL

Propagation Delay
Co to Q

20

30

ns

tPLH

Propagation Delay
CD to Q

14

35

ns

tw (U

To Pulse Width

LOW

8.0

15

tw (H)

11 Pulse Width HIGH

12

30

ns

tw (U

CD Pulse Width LOW

7.0

22

ns

tw (H)

Minimum Q Pulse Width HIGH

30

45

25

55

ns

Rx = 1.0 k!1, Cx = 10 pF
including jig and stray

tw

Q Pulse Width

5.2

5.8

4.1

4.5

}ls

Rx = 10 k!1, Cx = 1000 pF

Rx

Timing Resistor Range"

1.0

2000

1.0

1000

k!1

TA = -55°C to +125°C,
Vee = 4.5 V to 5.5 V

t

Change in Q Pulse Width
over Temperature

1.0

3.0
1.0

%

Rx = 10 k!1, Cx = 1000 pF

1.0

0.8
%

TA = 25°C, Vee = 4.75 V to
5.25 V, Rx = 10 k!1,
Cx = 1000 pF
TA = 25°C, Vee = 4.5 V to
5.5 V, Rx = 10 k!1,
Cx = 1000 pF

t

~
XC

ns

Change in Q Pulse Width
over Vee Range
1.5

•Applies only over commercial

Vee

and

TA

range for 96S02.

7-26

Fig. a

96LS32
CONNECTION DIAGRAM
PINOUT A

96LS32
ADDRESS MULTIPLEXER/REFRESH COUNTER
(For 4K Dynamic RAMs)
DESCRIPTION - The 96LS32 is an address multiplexer and refresh counter
for multiplexed address dynamic RAMs requiring refresh of up to six input
addresses (or 4K bits for 64 x 64 organization). It multiplexes 12 bits of system
applied address to six output address pins. The device also contains a 6-bit
refresh counter which is externally clocked so that either distributed or burst
refresh may be used. The high performance of the 96LS32 makes it especially
suitable for use with high speed n-channel RAMs like the M4027. The 96LS32
operates from a single +5.0 V power supply and is specified for operation over
a O°C to +75°C ambient temperature range.

•
•
•
•
•
•

SIMPLIFIES SYSTEM DESIGN
REDUCES PACKAGE COUNT
DRIVES HIGH CAPACITANCE LOADS
USE FOR DISTRIBUTED OR BURST REFRESH
STANDARD 24-PIN DUAL IN-LINE PACKAGE
LOW POWER SCHOTTKY DESIGN MINIMIZES"

~...
t

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL G

= +5.0 V ±5%,
TA = O°C to +70°C
Vee

PKG
Vee

TA

= +5.0 V ±10%,

= -55°C to +125°C

TYPE

Plastic
DIP(P)

A

96LS32PC

Ceramic
DIP (D)

A

96LS32DC

96LS32DM

6N

Flatpak
(F)

A

96LS32FC

96LS32FM

4M

9N

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

Ao-As
As-Al1
CP
RE
RS
ZD

00-05

DESCRIPTION
Row Address Inputs
Column Address Inputs
Clock Pulse Input (Active Falling Edge)
Refresh Enable Input (Active HIGH)
Row Select Input (Active HIGH)
Refresh Counter Zero Detect Output (Active LOW>
Address Outputs

7-27

96XX (U.L.)

HIGH/LOW
0.5/0.13
0.5/0.13
0.5/0.13
0.5/0.13
0.5/0.13
25/3.1
25/3.1

96LS32
LOGIC DIAGRAM

05

12 TOTAL

,I

,
,
,

6 TOTAL'

I

,

,

,
,

A81t=f====$~====r::)

00

6 TOTAL

RS

6 TOTAL

RE------------~~

~64

CP--------------------~

LOGIC SYMBOL

7

23

8

3

4

5

6 18 17 20 19 22 21

RS

RE

ZD

cp

9

11

10

16

Vce = Pin 24
GND = Pin 12

7-28

15

14

13

96LS32
FUNCTIONAL DESCRIPTION - The 96LS32 address multiplexer/refresh counter performs the following
functions:

1. Row, Column and Refresh Address multiplexing
2. Address counting for burst or distributed refresh
These functions are controlled by two signals, Refresh Enable and Row Select, both of which are active HIGH
TTL inputs. the Function Table shows the levels required to multiplex to the output:
1. Refresh address (from internal counter)
2. Row addresses (Ao through A5)
3. Column addresses (As through A11)
BURST REFRESH MODE-When refresh is requested the Refresh Enable input is HIGH. This input is
ANDed with the six outputs of the internal 6-bit counter. At each CP pulse the counter increments by one,
sequencing the outputs (Do - 05) through all 64 row addresses. When the counter sequences to all zeroes, the
Zero Detect output goes LOW signaling the end of the refresh sequence. Due to counter decoding spikes, the
Zero Detect output is valid only after tcz following the LOW going edge of CPo
DISTRIBUTED REFRESH MODE-In the distributed refresh mode, one row is selected for refresh each
(trefresh/n) ti me where n = number of rows in the device and refresh is the specified refresh rate for the device.
For the M4027, trefresh = 2.0 ms and n = 64, therefore one row is refreshed each 31 /-Is. Following the refresh
cycle at row n, the CP input is pulsed, advancing the refresh address by one row so that the next refresh cycle
will be performed on row n + 1. The CP input may be pulsed following each refresh cycle or within the refresh
cycle after the specified memory device address hold time.
ROW AND COLUMN ADDRESS-All twelve system address lines are applied to the inputs of the 96LS32.
When Refresh Enable is LOW and Row Select is HI GH, the input addresses Ao - A5 are gated to the outputs and
applied to the driven memories. Conversely, when Row Select is LOW (with Refresh Enable still LOW), input
addresses As-An are gated to the outputs and applied to the driven memories. When memory devices are
driven directly by the 96LS32, the address applied to the memory devices is the inverse of the address at the
inputs due to the inverted outputs of the 96LS32. This should be remembered when checking out the memory
system.

FUNCTION TABLE

Refresh
Enable

Row
Select

H
L
L

X
H
L

Outputs
Refresh Address (from internal counter)
Row Address (complement of Ao - A5)
Column Address (complement of As-A11)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

7-29

96LS42
CONNECTION DIAGRAM
PINOUT A

96LS42
ADDRESS MULTIPLEXER/REFRESH COUNTER
(For 16K Dynamic RAMs)
DESCRIPTION - The 96LS42 is an address multiplexer and refresh counter
for multiplexed address dynamic RAMs requiring refresh of 64 or 128 cycles.
It multiplexes 14 bits of system supplied address to seven output address
pins. The device also contains a 7-bit refresh counter which is externally
controlled so that either distributed or burst refresh may be used. The high
performance of the 96LS42 makes it especially suitable for use with high
speed n-channel RAMs like the F16K. The 96LS42 is manufactured using
Fairchild's advanced low power Schottky process.

•
•
•
•
•
•

SIMPLIFIES SYSTEM DESIGN
REDUCES PACKAGE COUNT
DRIVES HiGH CAPACITIVE LOADS
EITHER BURST OR DISTRIBUTED REFRESH
LOW POWER SCHOTTKY DESIGN
STANDARD 28-PIN PACKAGE

ORDERING CODE: See Section 9
PIN
PKGS

COMMERCIAL G

PKG
Vee = +5.0 V ±10%,
TA = -55°C to +125°C

OUT

Plastic
DIP(P)

A

96LS42PC

Ceramic
DIP (D)

A

96LS42DC

TYPE
9Y

96LS42DM

8E

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES

AIJ-At;
A7-A13
CP
RE
RS

Z5

Oo-Oe

DESCRIPTION
Row Address Inputs
Column Address Inputs
Clock Pulse Input (Active Falling Edge)
Refresh Enable Input
Row Select Input
Refresh Counter Zero Detect Output (Active LOW>
Multiplexer Outputs (Active LOW>

7-30

96XX (U.L.)

HIGH/LOW
0.5/0.13
0.5/0.13
0.5/0.13
0.5/0.13
0.5/0.13
25/3.1
25/3.1

96LS42
LOGIC SYMBOL

9

10

5

6

7

8 21 20 23 22 25 24 27 26

3

2

ZD

RE

15

CP

11

13

12

18

17

16

19

Vee = Pin 28
GND = Pin 14

LOGIC DIAGRAM

A13
A6

06

I
I
I

TO~ALI
I

Td:AL I
I

I

I

I
I

I

I

A7

I
/4()

00

RS

7 TOTAL

-----

7 TOTAL

ZD

RE

7-BIT COUNTER

CP--------------------~

7-31

96LS42
FUNCTIONAL DESCRIPTION - The 96LS42 address multiplexer/refresh counter performs the following
functions:
1. Row, Column and Refresh Address multiplexing
2. Address counting for burst or distributed refresh
These functions are controlled by two signals, Refresh Enable and Row Select, both of which are active HIGH
TTL inputs. The Function Table shows the levels required to multiplex to the output:
1. Refresh addresses (from internal counter)
2. Row addresses (Ao through As)
3. Column addresses (A7 through A13)
Burst Refresh Mode-When refresh is requested the Refresh Enable input is HIGH. This input is AND-ed with
the seven outputs of the internal 7-bit counter. At each CP pulse the counter increments by one, sequencing the
outputs ((50- (6) through all 128 row addresses. When the counter sequences to all zeroes, the Zero Detect
output goes LOW signaling the end of the refresh sequence. Due to counter decoding spikes, the Zero Detect
output is valid only after tcz following the LOW going edge of CPo
Distributed Refresh Mode -In the distributed refresh mode, one row is selected for refresh each (trefresh/n) time
where n = number of rows in the device and refresh is the specified refresh rate for the device. For the F16 k,
Refresh =2.0 ms and n = 128, therefore one row is refreshed each 62 j.lS. Following the refresh cycle at row n, the
CP input is pulsed, advancing the refresh address by one row so thatthe next refresh cycle will be performed on
row n + 1. The CP input may be pulsed following each refresh cycleor within the refresh cycle after the specified
memory device address hold time.
Rowand Column Address-All 14 system address lines are applied to the inputs of the 96LS42. When Refresh
Enable is LOW and Row Select is HIGH, the input Addresses Ao - As are gated to the outputs and applied tothe
driven memories. Conversely, when Row Select is LOW (with Refresh Enable still LOWl.lnputaddresses A7A13 are gated to the outputs and applied to the driven memories. When memory devices are driven directly by
the 96LS42, the address applied to the memory devices is the inverse of the address at the inputs due to the
inverted outputs of the 96LS42. This should be remembered when checking out the memory system.

FUNCTION TABLE
Refresh
Enable

Row
Select

H
L
L

X
H
L

Outputs
Refresh Address (from internal counter)
Row Address (complement of Ao - As)
Column Address (complement of A7 - A13)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

7-32

96101
CONNECTION DIAGRAM
PINOUT A

96101
QUAD 2-INPUT POSITIVE NAND BUFFER
(With Open-Collector Output)
DESCRIPTION - The 96101 is similar to the 5417439, except that the outputs
are specified at three levels of IOL; in the HIGH state the IOH current is specified at two levels of VOH. During switching transitions, output current change
rate is typically 4.0 mAins.
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

Plastic
DIP(P)

A

96101PC

Ceramic
DIP (0)

A

96101DC

PKG
TYPE

IT
II
IT
IT
IT
IT
GNOIT

:ill Vee

~-g[ ill:ill

~G:[

~
~
~
~

9A
96101DM

6A

•

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs

96XX (U.L.)
HIGH/LOW
1.0/1.0
OC"/30

DC AND AC CHARACTERISTICS: See Section 3'
SYMBOL

96XX

PARAMETER
Min

UNITS

CONDITIONS

Max

2.0

VIH

Input HIGH Voltage

V

VIL

Input LOW Voltage

0.8

V

VOL

Output LOW Voltage

0.4
0.5
0.6

V

IOL = 48 mA
IOL = 60 mA
IOL - 80 mA

Vee = Min
VIN = VIH

IOH

Output HIGH Current

25
50

p.A

VOH = 3.5 V
VOH = 5.5 V

Vee = Min
VIN = VIL

hH

Input HIGH Current

40
1.0

p.A
mA

VIN = 2.4 V
VIN = 5.5 V

Vee = Max

IlL

Input LOW Current

-1.6

mA

VIN = 0.4 V, Vee = Max

leeH
leel

Power Supply Current

8.5
54

mA

VIN = Gnd
VIN = Open

tPLH
tPHL

Propagation Delay
Input to Output

22
25

ns

CL = 45 pF, RL = 120
Figs. 3-2, 3-4

"DC limits apply over operating temperature range; AC limils apply al TA

= +25'C and

7-33

Vee

= +5.0 V.

"OC-Open Colleclor

Vee = Max

n

96103
CONNECTION DIAGRAM
PINOUT A

96103
QUAD BUS TRANSCEIVER
(With Common Enable)
DESCRIPTION - Each transceiver contains an open-collector buffer whose
output is common to an inverting gate input. When both Enable inputs(i~1 and
E2) are LOW, the buffer is enabled, with its output state determined by its Data
(0) input. When either Enable input is HIGH, the buffer is disabled (output
OFFJ and the bus signal is determined by other circuits connected to the bus.
The receiver gate has greater input noise immunity than standard TTL, while
its output signal levels are standard TTL. In the power-down condition, the B
terminal leakage is limited to 100 MA.

orr ~-+Q :lilB
:m o
BIT

0[1

BI}

orr
o[!

E1LZ.

ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%,
TA = O°C to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

mvcc

~.~

p-Y>-

GNOI1

PKG
TYPE

Plastic
DIP(P)

A

96103PC

Ceramic
DIP (0)

A

96103DC

96103DM

6B

Flatpak
(F)

A

96103FC

96103FM

4L

9B
Vce = Pin 16
GND

= Pin

8

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
D
E1,
B

E:1

0

DESCRIPTION
Data Input
Enable Inputs (Active LOW)
Bus Terminal, as Input
as Output
Receiver Output

96XX (U.L.)
HIGH/LOW
1.0/1.0
1.011.0
2.5/0.05
OC'/70mA
50/12.5

·OC - Open Collector

7-34

EJo

TIlB

TIl 0
~o

]]E2

96103
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

96XX

PARAMETER

Min
VOL

Output LOW Voltage at B

VIL

Input LOW Voltage
at D or E

VIHR

Receiver HIGH
Threshold Voltage

VILR

Receiver LOW
Threshold Voltage

XC

r-xM
~
XM

~
XM

UNITS

CONDITIONS

0.7

V

10L = 70 rnA, VIH = 2.0 V
Vee = Min

0.8
0.7

V

Max

1.53
1.49
1.7
1.84

~
XM

1.3
1.21
1.47
1.56

~
XM

V

Vee = Min

V

Vee = Max

V

Vee = Min

V

Vee = Max

10H

Bus Output HIGH Current

100

p.A

Vee = 0 V to Max
VOH = 4.0 V, Vo = VIL

ilL

Input LOW Current at B

-85

p.A

VOUT = 0 V, Vee = Max
Vo = VIL

los

Output Short Circuit
Current at 0

-55

rnA

Vee = Max, VOUT = 0 V

lee

Power Supply Current

90

rnA

D input = 4.5 V
Vee = Max

-18

AC CHARACTERISTICS: Vee = +5.0 V, TA = +25°C (See Section 3 for waveforms and load configurations)
96XX

SYMBOL

PARAMETER

CL = 15 pF
Min

UNITS

CONDITIONS

Max

tPLH
tPHL

Propagation Delay
E1 or E'2 to B

30
23

ns

tPLH
tPHL

Propagation Delay
D to B

25
15

ns

tPLH
tPHL

Propagation Delay
B to 0

10
10

30
30

ns

RL = 390 n to Vee
1.6 kn to Gnd, Fig. 3-4

tPLH
tPHL

Propagation Delay
B to 0

10
10

35
35

ns

RL= 390 n to Vee
1.6 kn to Gnd
CL = 50 pF, Fig. 3-4

7-35

RL = 91 n to Vee,
200 n to Gnd
Figs. 3-4, 3-5

96106
CONNECTION DIAGRAM
PINOUT A

96106
QUAD 2-INPUT NOR RECEIVER
DESCRIPTION - The 96106 inputs are designed to provide higher noise
immunity than standard TTL inputs and also present less loading to the signal
source. Also, in the power down condition, input leakage is 80 JJ.A or less,
making the 96106 well suited for data bus applications. Output signal levels
are standard TTL.
ORDERING CODE: See Section 9
PIN
PKGS

OUT

COMMERCIAL GRADE

MILITARY GRADE

Vee = +5.0 V ±5%;
TA = DOC to +75°C

Vee = +5.0 V ±10%,
TA = -55°C to +125°C

PKG
TYPE

Plastic
DIP(P)

A

96106PC

Ceramic
DIP (0)

A

96106DC

96106DM

6A

A

96106FC

96106FM

31

9A

GNOIT

,..--- EJco

Boll

TIl Do

AoIT
A,[I
A2[I
B,[I
Bdz

Flatpak
(F)

Inputs
Outputs

t1:9

321 C2

lI c,
~vcc

Vee = Pin 8
GND = Pin 1

INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS

~~

m02

:m o,

96XX (U.L.)
HIGH/LOW
2.0/0.006
50/12.5

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

96XX

PARAMETER
Min

VIH

Input HIGH Voltage

~
XM
XC

xM
Vil

Input LOW Voltage

1.53
1.49
1.70
1.84

Input HIGH Current

III

Input LOW Current

los
leeH
leel

Output Short Circuit Current

CONDITIONS

V

Vee

= Min

V

Vee

= Max

V

Vee

= Min

V

Vee

= Max

80

JJ.A

Vee

-10

JJ.A

-55

rnA

40
20

rnA

1.30
1.21
1.47
1.56

~
XM
--$XM

hH

UNITS
Max

-18

Power Supply Current

7-36

= 0 V to Max, VIN = 4.0 V
Vee = Max, VIN = 0 V
Vee = Max, VOUT = 0 V
VIN = 4.5 V
Vee = Max·
VIN = 0 V

96106
AC CHARACTERISTICS: Vee

= +5.0 V, TA = +25°C (See Section 3 for waveforms and

load configurations)

96XX
SYMBOL

PARAMETER

CL

= 15 pF

Min

Max

UNITS

CONDITIONS

tPLH
tPHL

Propagation Delay

10
10

30
30

ns

RL = 390 0 to Vee,
1.6 kO to Gnd, Fig. 3-4

tpLH
tPHL

Propagation Delay

10
10

35
35

ns

RL = 390 0 to Vee
1.6 kO to Gnd
CL = 50 pF, Fig. 3-4

7-37

I
,

.

Section 8

OTHER DIGITAL PRODUCTS
RTL MICROLOGIC AND CTL COUNTING MICROLOGIC ELEMENTS
DEVICE
NO.

DESCRIPTION

LOGIC/
CONN.
DIAGRAM

PKG
TYPE

DEVICE
NO.

DESCRIPTION

LOGIC/
CONN.
DIAGRAM

PKG
TYPE

900

8uffer

F8

3F,S8

913

o Flip-Flip

FS

3F,S8

901

Counter Adapter

F18

3F,S8

914

DuaI2-NOR

F13

3F, S8

902

Flip-Flop

F19

3F,S8

915

DuaI3-NOR

F14

3F,SF

903

3-lnput NOR

F9

3F,S8

921

Dual 2-Expander

F7

3F, S8

904

Half Adder

F10

3F,S8

923

JK Flip-Flop

F1S

S8

905

Half Shift

F11

3F,S8

926

JK Flip-Flop

F1S

3F,SF

906

Half Shift

F20

3F,S8

927

Quad Inverter

F17

3F,SF

907

4-lnput NOR

F12

3F,S8

958

Decade Counter

F21

S8, SA

908

Adder

F1

3F,S8

959

4-8it Latch

F22

S8

909

8uffer

F2

3F,S8

960

8CD Decoder/Dvr

F23

S8

910

DuaI2-NOR

F3

3F,S8

974

JK Flip-Flop

F1S

S8

911

4-lnput NOR

F4

3F,S8

989

8inary Counter

F21

S8,SA

912

Half Adder

FS

3F,S8

DTL MICROLOGIC

930

LOGIC/CONN.
DIAGRAM

DESCRIPTION

DEVICE NO.

Dual 4-lnput Extendable NAND Gate

G1

PKG TYPE
31, SF, 6A, 9A

932

Dual 4-lnput Extendable NAND 8uffer Gate

G1

31, SF; SA, 9A

933

Extender

G9

SF,9A

935

Extendable Hex Inverter

G12

31, SA, 9A

936

Hex Inverter

G12

31, SA, 9A

937

Hex Inverter

G12

31, SA, 9A

941

Monostable Multivibrator

G17

31, SA

944

Dual 4-lnput Extendable NAND
8uffer Gate (Open-Collector)

G1

31, SF, SA, 9A

945

RS Flip-Flop

G18

31, SF, SA, 9A

946

Quad 2-lnput NAND Gate

G10

31, SF, SA, 9A

948

RS Flip-Flop

G18

31, SF, SA, 9A

8-3

OTHER DIGITAL PRODUCTS
DTL MICROLOGIC (Cont'd)
LOGIC/CONN.
DIAGRAM

DESCRIPTION

DEVICE NO.

PKG TYPE

949

Quad 2-lnput NAND Gate

G10

31, 5F, 6A, 9A

950

A-C Coupled RS Flip-Flop

G19

31, 5F, 6A, 9A

951

Monostable Multivibrator

G17

31, 5F, 6A, 9A

961

Dual 4-lnput Extendable NAND Gate

G1

31, 5F, 6A, 9A

962

Triple 3-lnput NAND Gate

G11

31, 5F, 6A, 9A

963

Triple 3-lnput NAND Gate

G11

31, 5F, 6A, 9A

1800

Dual 5-lnput NAND Gate

G1

9A

1801

Dual 5-lnput NAND Gate

G1

9A

1802

Single 8-lnput NAND Gate

G2

9A

1803

Single 8-lnput NAND Gate

G2

9A

1804

Single 10-lnput NAND Gate

G3

9A

1805

Single 10-lnput NAND Gate

G3

9A

1806

Quad 2-lnput AND Gate

G4

9A

1807

Quad 2-lnput AND Gate

G4

9A

1808

Quad 2-lnput OR Gate

G5

9A

1809

Quad

G5

9A

1810

Quad 2-lnput NOR Gate

G6

9A

1811

Quad 2-lnput NOR Gate

G6

9A

1812

Quad 2-lnput Exclusive-OR Gate

G7

9A

1813

Quad Latch

G13

9B

1814

Quad Latch

G14

9A

9093

Dual JK Flip-Flop

G15

31, 6A, 9A

9094

Dual JK Flip-Flop

G15

31, 6A, 9A

9097

Dual J K Flip-Flop

G16

31, 6A, 9A

9099

Dual JK Flip-Flop

G16

31, 6A, 9A

9109

High Voltage Hex Inverter

G12

6A

9110

High Voltage Hex Inverter

G12

6A

9111

RS Flip-Flop

G20

31,6A

9112

High Voltage Hex Inverter

G12

6A

9135

Hex I nverter (Open-Collector)

G12

31, 6A, 9A

9157

Quad 2-lnput Buffered NAND Gate

G8

31, 6A, 9A

9158

Quad 2-lnput Power NAND Gate

G8

6A,9A

2~lnput

OR Gate

8-4

OTHER DIGITAL PRODUCTS
F2
909

F1
908

F4
911

F5
912

,,~,

'e·

'@'

'e·

:~.

F6
913

F7
921

F8
900

F9
903

F10
904

,~,

,~,

~

,;C\.

,~.

4 GND

~

4 GND

4 GND

3~S

F12
907

F13
914

4 GND

"~'
g
4 GND

4 GND

10 Vee

10 Vee

4 GND

F18
901

8

2

8

7

3

7

4

4 GND

~
4 GND

F14
915

4

4 GND

F17
927

6
SGND

~

F15
923,974

,6,
,~. :~:
~
~

@. ~
4

4 GND

4 GND

10 Vee

F16
926

2

4 GND

~

F11
905

3

F3
910

,@.
8 Vee

3

4 GND

F20
906

F19
902

6
SGND

F21
958,989

F22
959

Za
Z4

+Vee

Z,

RESET

Z,

COUNT

GND

8-5

S

6

S GND

F23
960

OTHER DIGITAL PRODUCTS
G1
930, 932
944, 961
1800, 1801

G2
1802, 1803

G3
1804, 1805

G4
1806, 1807

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

G5
1808, 1809

G6
1810,1811

G7
1812

G8
9157,9158

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

G9
933

G10
946,949

No connection required to
Vee (Pin 14).

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

8-6

Vee = Pin 14
GND = Pin 7

OTHER DIGITAL PRODUCTS
G11
962, 963

G12
9109,9110,9112
9135, 935, 936
937

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

Vee = Pin 16
GND = Pin 8

G15
9093,9094

G16
9097, 9099

G17
941,951

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

Vee = Pin 14
GND = Pin 7

G19
950

G20
9111

"These inputs are capacitively
coupled.
Vcc = Pin 14
GND = Pin 7

Vee = Pin 14
GND=Pin7

G13
1813

8-7

G14
1814

Vee = Pin 14
GND = Pin 7

G18
945,948

Vce = Pin 14
GND = Pin 7

Section 9

ORDERING INFORMATION AND PACKAGE OUTLINES

Specific ordering codes, as well as the temperature ranges and package types available, are listed on the first
page of each data sheet in Section 4 through Seetion 7. The product indices and selection guides given in
Section 1 list only the "basic" device numbers. This basic number is used toform part of asimplified purchasing
code where the package style and temperature range are defined as follows:

xxxx

D

C

I

1-.-_ _ _ _ _

Temperature
Range Code

L-________ Package
Code
Device
' - - - - - - - - - - - - Number (basic)

TEMPERATURE RANGE - Two basic temperature grades are in common use:
C = Commercial
0° C to +70° C/7So C

•

M = Military
-55°C to +12S oC

PACKAGE CODE - One letter represents the basic package style. Different package outlines exist withi n each
package style to accommodate varying die sizes and number of pins, as indicated below:
D - Ceramic/Hermetic Dual In-Ii ne
4E,6A,68,6N,78,8E
F - Flatpak
3F, 31, 4F, 4L, 4M
H-Metal Can
S8,SF
P- Plastic Dual In-line
9A, 98, 9N, 9Y, 9Z

PACKAGE OUTLINES - The package outlines indicated by the codes above are shown in the detailed outline
drawings in this section.

9-3

FAIRCHILD PACKAGE OUTLINES
JEDEC TO-91 OUTLINE

3F
.370 19.391
.250 16.351

·t

I
I
-1"'---'"
*-

.0061.152)
.0041.0921

foool.------>.-+I~ :~~~ :~:~~:

I

L.035 1.8891
TYP.

I

I

f

I

.26016.60)

NOTES:
Leads are tin plated 42 alloy
Hermetically sealed alumina package
Cavity size is .130 (3.30) diameter
Package weight is 0.26 grams

r--- .240 (6.10)----'

.08510.2161
.07510.1911

JEDEC TO-86 OUTLINE

•

1.-'
1

14

j

-

~

r-

.019 (0483)
.015 (0.3811
TYP.

7

. 010 (1270)
TYP.

8

,

h~

.370 (9398)
.250 (6350)

.006 (0.152)
.004 (0.102)

I
r

.260 (6. 6041
.240 (6 .096)

J

I

I

.370 (9.398)
.250 (6350)

31
NOTES:
Leads are tin-plated 42 alloy
Hermetically sealed alumina package
Lead 1 orientation may be either tab or dot
Cavity size is .130 (3.30)
Package weight is 0.26 gram

~t~~~:§§~~~:~~~t
I

.260 (6604)
I
r--.240 (6096) ----j

.025 (0.635)
TYP.

.065 (1651)
.050 (1270)

20-PIN CERDIP

r----.

975 124.771--1

4E

11\1\[·960124.381,1\1\(1 1

=1~1 ~:::::::~.r.~~~~~'
L
.06511.651
II
.04511141--

V

I-

•

-I

21915561
:17014:321

:~~~ :g~~:
.31017.871_r--------i
.29017.371

IIlTII

r~~
h ~ Ih~.t,:?,~~",' -An~\
I
I

.16514.191 I
.10012.541--1

MIN.
,
.11012.791 .03710.941 .04511.141
.090 12.291 :ll27i5:691 .015 10.381
TYP.
TYP.

----1

•. 37519.521.
NOM .

NOTES:
Pins are tin-plated kovar or nickel alloy 42
Pins are intended for insertion in hole rows
on .300" 17.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .03010.76) inch
diameter pins
Hermetically sealed alumina packagelblackl
Cavity size is .140 x .25013.56 x 6.351
'The .037-.027 di mension does not apply to
the corner pins
Package weight is 2.4 grams

All dimensions in inches (bold) and millimeters (parentheses)

9-4

FAIRCHILD PACKAGE OUTLINES
20-PIN CERPAK

j

•

.050 11.271
~

5

.01910.48)
.01610.381
TYP.

t
.04511.14)
.02510.641

.30017.621

~~1·___~.2~50~1~6.3~5~1 ~·[1I ================~~~~~~~::JI~
__

L-.400110.16)~

L.00610.151
.00410.101

.085f2.161
.06011.521

.37519.52)

SaUARE

4F
NOTES:
Leads are tin plated nickel alloy
Base is AL203
Cavity size 200 x 200
Package weight ~ 0.8 grams

16-PIN BeO CERPAK
1.

24-PIN CERPAK
.050 (1.270)
TYP

16

L_
T-

j

i-l
.050
(1.270)
TYP.

.409 (1 0 ..389)
.371 (9.423)

.019
.015 (0.483)
(0.381)

T~ h.

350

I

~O~

:~~~g:
.006 (0.152)
.004(0102)

8

9

I

(8.890)
(6. TY
350p)
.

I

!

.283 (7.188)
I
--.247 (6.274)1

8
9
10
11
12

.019 (.483)
.015 (.381)
TYP

.350

~~===9,-________~=====~

~

.L

~2~

TYP.

1 •
2
3
4
5
6
7

.00 7
6 5 (1.905)
. 0 (1.524)

~.350 (8.890)~
.250 6.350)

24
23
22
21
20
19
18
17
16
15
14
13

§l
=
=
=
=

.62 o
(15.748)
MA X

~.350
(889~(~
.250 6.350

.090 (2.286)
.065 (1.651)

t

I

'
.024
(0.610)
TYP.

.006 (.152)
.004 (.102)

I

.395 (10033)
1--.365 (9.271)

I

-----I

4L

4M

NOTES:
Pins are alloy 42
Package weight is 0.4 gram
Hermetically sealed beryllia package

NOTES:
Pins are tin plated nickel alloy
Base is AI203 or BeO
Cavity size is 200 x 200
Package weight is 0.8 grams

All dimensions in inches (bold) and millimeters (parentheses)

9-5

•

FAIRCHILD PACKAGE OUTLINES
JEDEC TO-l00 OUTLINE

JEDEC TO-99 OUTLINE

I-- .335D\~509)-!
.370 (9.398)

I
I

r

335 (8 509)

305D\~747)

-II
,

.040
(10161
MAX.

,185 (4.699)
165(4.191)

_-----r-

- -

80~~.~483) ~~ ~ ~~04~~X016)

.260 (6.60)
.240 (6.10)

1___

_--'Y--",_ _----.

-._

t

10 LEADS

-'1'----+_

SEATING:-:r~-PLANE
I

335 (8.509)

'305(7747)~ t

.335.(8.. 509) -

040(1016)Q'
MAX
I

t

F··4.

.370 (9.398)

I

rn~~~~ru~

.019 (0.482)
.016 (0.406)
DIA.

.500 (12.70)

.040 (1.016)
MAX.
____

.500 (12.70)
MIN.

--L

.230 (5.842) - t " - - - I
T.P.

MIN.

.016(0.406)-DIA.

SEATING
PLANE

-r-----I--

'.

.115 (2.921)
T.P.
GLASS

L..--------i .200 (5.080)
T.P.

I

_____ 1

1_

~

.100 (2.540)
T.P.

36°
T.P.

INSULATING
STANDOFF SHAPE MAY VARY
.045(1.143)
.029(0.737)

.034 (0.864)
.028 (0.711)

10

W~
\""
V

"-'
.034 (0864)~
.028 (0.711)

_

8

INSULATING STANDOFF SHAPE MAY VARY

.045(1.143)
- .029 (0737)

58

5F

NOTES:
Leads are gold-plated kovar
Seven leads thru leads No.4 connected
to case
15 mil kovar header
Package weight is 1.22 grams

NOTES:
Leads are gold-plated kovar
Nine leads through, lead 5 connected
to case
15 mil kovar header
Package weight is 1.32

14-PIN HERMETIC DUAL IN-LINE
(JEDEC TO-116 OUTLINE)

ill

r - - . 7 8 5 (19 9 3 9 ) - - - - 1

6A

I A A

NOTES:
Pins are intended for insertion in hole rows
on .300" (7.6201 centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" 10.508) diameter pin
Pi ns are alloy 42
Package weight is 2.0 grams

,-750(1905)

I

A A I

::EJ : : : : : : :
.065 (1 651)J
.045 (1 143)

t-~"~b~'"

L

rr~~

t

.200 (5.08) b==j::::::;==.=:r=;::::::r==;:::::::;=='=r=l~=.=tl
MAX.

SEATING
~ L
PLANE ---~6~
.10012540)
.110
.090
(2.794)
(2.286)
TYP.

I

,
I

I--

,037
.027
(.940)
(686)
STANDOFF
WIDTH

All dimensions in inches (bold) and millimeters (parentheses)

9-6

FAIRCHILD PACKAGE OUTLINES
16-PIN DUAL IN-LINE

r - - - - . 7 8 5 (19.939)-------/
755
! \ 11.
(19.177)!\ !\

I[\,
f

!"II

8

(6.883)
.271
(6.223)
.245

.025 (.635) R
NOM.

~~9~_r~~T<~rT._.rr

68
NOTES:
Pins are tin-plated 42 alloy
Pins are intended for insertion in hole rows
on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 (0.51) inch
diameter pin
Hermetically sealed alumina package
Cavity size is .110 x .140 (2.79 x 3.56)
Package weight is 2.0 grams
'The .037-.027 dimension does not apply to
the corner pins

.110 (2.794)
.090 (2.286)
TYP

24-PIN DUAL IN-LINE

r----

I

•

1.290 (32.7661----1

11\1\1\11.235 (31.369) ~I\I\I\

I

1211109 8 7 6"5 4 3 2 1
.03010.7621 R
.020 (0.508)

.570 (14.478)
.515113.081)

L~~~
6N
.19014.8261
.140 (3.556)

NOTES:
Pins are tin-plated 42 alloy
Package material is alumina
Pins are intended for insertion in hole rows
on .600 (15.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Cavity size is .230 x .230 (5.84 x 5.84)
Package weight is 6.5 grams

.063 (1.544)

i MmW'~"'"
1=
~J II
---t !~~~'~G
i i

.200 (5080)
.100 (2.5401--1 t-.11012.7941
.090 12.286)
TYP.

II

.037 10.9401
.02010.508)
.027 1O.686dl--.016 10.4061
STANDOFF
WIDTH

All dimensions in inches (bold) and millimeters (parentheses)

9-7

FAIRCHILD PACKAGE OUTLINES
16-PIN DUAL IN-LINE
r---.785119.939)~

lr-. (\

('.755 119177)1\ ( \

III

: ::~I: ::::::J':~~'"''

78

J
I I .06511.651)
--I 1+.04511.143)

NOTES:
Pins are tin-plated 42 alloy
Pins are intended for insertion in hole rows
on .300" 17.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 10.51) inch
diameter pin
Hermetically sealed alumina package
Cavity size is .130 x .230
'The .037-.027 10.94-0.69) dimension does
not apply to the corner pins
Package weight is 2.2 grams

.31017.874)
.290 17.366)

,,,,,r.;;~oo,,.,..,
MIN.

t

.17014.318)

.. 165 12.959)
.100 12.540)

I

'

I,
I

i,
I

,

,

JL

~ .11 a 12. 794)

.09012.286)
TYP.

,~SEATING

I t

PLANE
.011 10.279)
,.0
09
10.228)
.04511.143)
-.01510.381)
10.508) 1--.375 19.525)--1
.03710.939)'
.016 10.406)
NOM.
.027 10.685)
STANDOFF
WIDTH

~ ~.020

28-PIN DUAL IN-LINE SIDE-BRAZED

BE

r - - , . 4 7 0 137.34)----1

Ij~l\i\ 1\/\,1.450136.83) 1\ 1\ 1\ 1\ 1\ I

T14

1

NOTES:
Pins are tin-plated alloy 42
Package material is alumina
Pins are intended for insertion in hole rows
on .600 115.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Cavity size is .240 16.095) x .240 16.096)
Package weight is 7.5 grams

.03010.76)
.020 (0.51) RADIUS

.570 (14.48)

'51513.08)~~~~-n~~rT~~~~~~~~

~.600 (15.24)--1

.190 (4.83)

·~ ______________________________~.063(1.60)

r,

NOM

II

~r

.02510.64)
1:::i-=;::r=;::r=w""l'l....F>=;=;::r=;:r=;:;="\~>?"'I>?-I'i""\t:I~ SEATING

.200 (5.08)
:100 (2.54)

t

PLANE

I

.011 10.28)
.00910.23)
(9.05)
I
I~ .750MAX
--I

~ .110 (2.79)

.090 (2.27)

All dimensions in inches Ibold) and millimeters Iparentheses)

9-8

FAIRCHILD PACKAGE OUTLINES
14-PIN ·PLASTIC DUAL IN-LINE
(JEDEC TO-116 OUTLINE)

9A
.025 (0.641

'02010.51~

~
1--

-----~ :~!~ :~~~~:~

7

10

0

.260 16.601
.240 (6.101

L

~

30 0

.012 (0.301
.008 (0.201

R·045 (1.141**
.. 035 (0.891

.110 (2.801
.09012.291
.05011.271
.04011.021

.085 (2.161
.075 (1.901

h

.06511.65)
.04511141

.310 (7 871

Package weight

~ .290 17 371 ~

SEATING

l

t

PLANE

II

.15013811_~ I
.10012541
I
.110 (2801 -r---l
.090 12.29)

NOM.

~

~

I

II

-----"

r

-

I~ .020 (0 511

~

.016 (0 411

0.9 grams

010
(o25)

.011 (0281
.009 (0 231

~
.37519521
NOM.

STANDOFF .037 (0.941
WIDTH
.027 (0.69)

TYP.

IS

.020 (0 511

~T.:'~''''''"Pf~~~
=-f.
MAX.

NOTES:
Pins are tin plated kovar
'Package material varies depending on the
product line
Pins are intended for insertion in hole rows
on .300" 17.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 10.508) inch
diameter pi n
"Notch or ejector hole varies depending on
the product line

16-PIN PLASTIC· DUAL IN-LINE
.025 10.635)
.020 1 0 ' 5 0 8 ) m
.770 119.561
~
.
.740 118.801 - - - 1 ..--'l 1
30'
.012 10.3051

rr-'-

1

:~r~:I~: ~ ~ ::]:i~:::'~i~Oi;ii!:
.06511.6511 I
.045 (1.143)-1

I

I-

I

--1

I-

111.02510.635)

~rnnmw~

NOM.

~

.200 15 080)

(0381)
015

MAX

NOM.

~~:~~g

_,_

I

I

~III-

.150(1810)i
i 110
100 12 540)[090
12.794)
12.286)

-+-

*o;~ --1 r

027
10.940)
10.686)

II

'300 17 620)
.290(7366)

-=[
020(0508)
.016 10 406)

I

r-

.375 NOM.
(9525)

STANOOFF
WIDTH

98

NOTES:
Pins are tin-plated kovar or alloy 42 nickel
Pins are intended for insertion in hole rows
on .300" (7.62) centers
.020 (0.508)
.01010.254) They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .0210 (0.51) centers
diameter pin
.011
Package weight is 0.9 gram
.009
'Package material varies depending on the
product line
I 10.279)
(0.229) '''The .037-.027 (0.94-9.69) dimension does
not apply to the corner pins
'''Notch or ejector hole varies depending on
the product line

--I

All dimensions in inches Ibold) and millimeters Iparentheses)

9-9

FAIRCHILD PACKAGE OUTLINES
24-PIN PLASTIC DUAL IN-LINE

r_____

r-

I (

1-260 (32_004)~
1.240 (31 A96)

.045 (U43) R
.035 (889)

.560 (14_224)
.540(13-716)

1_ -~::rr==rr=n::::rr=n=r~~
.065 (1-651)
.045IU43)

-l

.090 (2_286)
.065 (1651)

.165 (4_191)

9N

145t""'~ O~:,OO"
~
SEATING

!'

I

+-- :

.135 (3A291
I
.115(2_921)--1

(27941 I:
!
.037(9401
~.090 -I r-.027 (686) "
(2_2861
STANDOFF
WIDTH

I .110 .J

NOTES:
Pins are tin-plated kovar
Package material is plastic
Pins are intended for insertion in hole rows
on .600 (15.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion

PLANE

.Ie. .020(508)
.016 (A06)

28-PIN PLASTIC DUAL IN-LINE

-I
~1~5~~~~~~~=;;=~~=r~~~~~28~---'l"·
L

9Y

14

NOTES:
Pins are tin-plated kovar, alloy 42 or copper
Package material is plastic
Pins are intended for insertion in hole rows
on .600 (15.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Assembled package weight is 4.8 grams

.555114_101

.075

11.911
TYP.

.011 10_281 ~
.00910_231

r---

.100

I

12541

TYP.

.625115_881

NOM.

All dimensions in inches (bold) and millimeters (parentheses)

9-10

I

--j

FAIRCHILD PACKAGE OUTLINES
20-PIN PLASTIC DUAL IN-LINE

.310 (787)l
.290 (7 37)
.185 (470)
NOM.

.015(038)
NOM.

r=~.-l
r= . ~ I t

.125 (3 18)
MIN.

•

-,
I
.110 (2.79) TYP.
.090 (2.29)

SEATING
PLANE

.02510.64)
MAX.

_

-----.l

ffS\~.0~1
-----='r

~

I

....065(165) TYP....

•

I

10.281
.009 10.231
.37019.401
NOM .

.03210.81)
TYP.

9Z
NOTES:
Pins are tin plated alloy 42 or copper
(olin 195)
Package material varies depending on the
product line
Pins are intended for insertion in hole rows
on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board drilling dimensions should equal your
practice for .020" (0.51) diameter pin
Package weight is a little over 1.0 gram

All dimensions in inches (bold) and millimeters (parentheses)

9-11

I

FAIRCHILD FIELD SALES OFFICES,
REPRESENTATIVES AND DISTRIBUTORS

FAIRCHILD SEMICONDUCTOR FRANCHISED DISTRIBUTORS
UNITED STATES AND CANADA
ALABAMA
HALLMARK ELECTRONICS
4739 Commercial Orive
Huntsville, Alabama 35805
Tel: 205-837-8700 TWX: 810-726-2187
HAMIL TON/AVNET ELECTRONICS
4692 Commercial Drive
Huntsville, Alabama 35805
Tel: 205-837-7210
Telex: None - use HAMAVLECB DAL 73-0511
(Regional Hq. in Dallas, Texas)

HAMIL TON/AVNET ELECTRONICS
5921 N. Broadway

Denver, Colorado 80216
Tel: 303-534-1212 TWX: 910-931-0510
CONNECTICUT
CRAMER ELECTRONICS
35 Dodge Avenue
Wharton Brook Industrial Center
North Haven, Connecticut 06473
Tel: 203·239-5641

ARIZONA
HAMIL TON/AVNET ELECTRONICS
2615 S. 21s1 Street
Phoenix, Arizona 85034
Tel: 602-275-7851 TWX: 910-951-1535

HAMIL TON/AVNET ELECTRONICS
643 Danbury Road
Georgetown, Connecticut 06829
Tel: 203-762-0361
TWX: None - use 710-897-1405
(Regional Hq. in Mt. Laurel, N.JJ

KIERULFF ELECTRONICS
4134 East Wood Street
Phoenix, Arizona 85040
Tel: 602-243-4101

HARVEY ELECTRONICS
112 Main Street
Norwalk, Connecticut 06851

LIBERTY ELECTRONICS
6155 North 24th Ave.
Phoenix, Arizona 85021
Tel: 602-249-2232 TWX: 910-951-4282

Tel: 203-853-1515
SCHWEBER ELECTRONICS
Finance Drive
Commerce Industrial Park
Danbury, Connecticut 06810
Tel: 203-792-3500

HAMILTON/AVNET ELECTRONICS
3901 N. 25th Avenue
Schiller Park, Hlinois 60176

Tel: 312-678-6310 TWX; 910-227-0060
KIERULFF ELECTRONICS
85 Gordon Street
Elk Grove village, Illinois S0007

Tel: 312-640-0200 TWX: 910-227-3166
SCHWEBEA ELECTRONICS, INC.
1275 Summel Avenue
Elk Grove Village, Illinois 60007
Tel: 312-593-2740 TWX: 910-222-3453
SEMICONDUCTOR SPECIALISTS, INC.
(mailing address)
O'Hare International Airport
P.O. Box 66125
Chicago, Illinois 60666
(shipping address)
195 Spangler Avenue
Elmhurst Industrial Park
Elmhurst, Illinois 60126
Tel: 312·279-1000 TWX: 910-254-0169

INDIANA
GRAHAM ELECTRONICS SUPPLY, INC.
133 S. Pennsylvania St.
Indianapolis, Indiana 46204
Tel: 317-634-8486 TWX: 810-341-3481

CALIFORNIA
AVNET ELECTRONICS
350 McCormick Avenue
Costa Mesa, California 92626
Tel: 714-754-6111 (Orange County)
213-558-2345 (Los Angeles)
TWX: 910-595·1928

FLORIDA
ARROW ELECTRONICS
1001 Northwest 62nd Street
Suite 402
Ft. Lauderdale, Florida 33309
Tel: 305-776·7790

BELL INDUSTRIES
Electronic Distributor Division
1161 N. Fair Oaks Avenue
Sunnyvale, California 94086
Tel: 408-734~8570 TWX: 910-339-9378

ARROW ELECTRONICS
115 Palm Bay Road N.W.
Suite 10 Bldg. #200
Palm Bay, Florida 32905
Tel: 305-725-1408

ELMAR ELECTRONICS
2288 Charleston Rd.
Mountain View, California 94042
Tel: 415-961-3611 TWX: 910-379-6437

CRAMER ELECTRONICS
345 North Graham Avenue
Orlando, Florida 32814
Tel: 305-894·1511

HAMILTON ELECTRO SALES
10912 W. Washington Blvd.
Culver City, California 90230
Tel: 213-558-2121 TWX: 910-340-6364

HALLMARK ELECTRONICS
1302 W. McNab Road
Ft. Lauderdale, Florida 33309
Tel: 305-971-9280 TWX: 510-956-3092

4613 Fairfield
Metairie. Louisiana 70002
Tel: 504-887-7610
Telex: STERLE LEC MRIE 58-328

HAMIL TON/AVNET ELECTRONICS
575 E. Middlefield Road
Mountain View, California 94040
Tel: 415-961-7000 TWX: 910-379-6486

HALLMARK ELECTRONICS
7233 Lake Ellenor Drive
Orlando, Florida 32809
Tel: 305-855-4020 -r:WX: 810-85G-0183

MARYLAND

HAMIL TON/AVNET ELECTRONICS
6917 Complex Drive
San Diego, California 92123
Tel: 714-279-2421
Telex: HAMAVELEC SDG 69-5415
INTERMARK ELECTRONICS INC.
4040 Sorrento Valley Blvd.
San Diego, California 92121
Tel: 714-279-5200
INTER MARK ELECTRONIC INC.
1802 East Carnegie Avenue
Santa Ana, California 92705
Tel: 714-540-1322
UBERTY ELECTRONICS
124 Maryland Street
EI Segundo, California 90245
Tel: 213-322-8100 TWX: 910-348-7111
LIBERTY ELECTRONICS/SAN DIEGO
8248 Mercury Court
San Diego, California 92111
Tel: 714-565-9171 TWX: 910-335-1590

HAMILTON/AVNET ELECTRONICS
6800 N.W. 20th Avenue
FI. Lauderdale, Florida 33309
Tel: 305-971-2900 TWX: 510-954-9808
HAMILTON/AVNET ELECTRONICS
3197 Tech Drive, North
SI. Petersburg, Florida 33702
SCHWEBER ELECTRONICS
2830 North 28th Terrace
Hollywood, Florida 33020
Tel: 305-927-0511 TWX: 510-954-0304

GEORGIA
ARROW ELECTRONICS
3406 Oak Cliff Road
Doraville, Georgia 30340
Tel: 404-455-4054
HAMIL TON/AVNET ELECTRONICS
6700 Interstate 85 Access Road, Suite IE
Norcross, Georgia 30071
Tel: 404-448-0800
Telex: None-use HAMAVL'ECB DAL 73-0511
(Regional Hq. in Dallas, Texas)

COLORADO
CENTURY ELECTRONICS
8155 West 48th Avenue
Wheat ridge, Colorado 80033
Tel: 303-424-1985 TWX: 910-938-0393

6447 Atlantic Blvd.
Norcross, Georgia 30071
Tel: 404·449-9400

CRAMER ELECTRONICS

ILLINOIS

5465 East EvallS Place at Hudson
Denver, Colorado 80222
Tel: 303-758-2100
ELMAR ELECTRONICS
6777. E. 50th Avenue
Commerce City, Colorado 80022
Tel: 303-287-9611 TWX: 910-936-0770

LYKES ELECTRONICS CORP.

HALLMARK ELECTRONICS INC.
180 Crossen Avenue
Elk Grove Village, Illinois 60007
Tel: :\,2-437-8800

10-3

KANSAS
HALLMARK ELECTRONICS, INC.
11870 W. 91 st Street
Shawnee Mission, Kansas 66214
Tel: 913-888-4746
HAMIL TON/AVNET ELECTRONICS
9219 Guivira Road
Overland Park, Kansas 66215
Tel: 9'3~888-8900
Telex: None-use HAMAVLECB OAL 73-0511
{Regional Hq. in Dallas, Texas)

LOUISIANA
STERLING ELECTRONICS CORP.

HALLMARK ELECTRONICS. INC.
6655 Amberton Drive
Baltimore, Maryland 21227
Tel: 301-796-9300
HAMIL TON/AVNET ELECTRONICS
(mailing addresS)
Friendship International Airport
P.O. Box 8647
Baltimore, Maryland 21240
(shipping address)
7235 Standard Drive
Hanover. Maryland 21076
Tel: 301-796-5000 TWX: 710-862-1861
Telex: HAMAVLECA HNVE 87-968

•

PIONEER WASHINGTON ELECTRONICS. INC.
9100 Gaither Road
Gaithersburg. Maryland 20760
Tel: 301-948-0710 TWX: 710-82a..9784

SCHWEBER ELECTRONICS
9218 Gaither Road
Gaithersburg, Maryland 20760
Tel: 301-840-5900 TWX: 710-828-0536

MASSACHUSETTS
CRAMER ELECTRONICS
85 Wells Avenue
Newton Centre. Massachusetts 02159
Tel: 617-964-4000

GERBER ELECTRONICS
852 Providence Highway
U.S. Route 1
Dedham. Massachusetts 02026
Tel: 617-329--2400

HAMILTON/AVNET ELECTRONICS
100 E. Commerce Way
Woburn. Massachusetts 01801
Tel: 617-933-8000 TWX: 710-332-1201

FAIRCHILD SEMICONDUCTOR FRANCHISED DISTRIBUTORS
UNITED STATES AND CANADA
HARVEY ELECTRONICS
44 Hartwell Avenue
Lexington, Massachusetts 02173
Tel: 617~861-9200 TWX; 710-326-6617
SCHWEBER ELECTqONICS'
213 Third Avenue
Waltham, Massachusetts 02154

Tel: 617-890-8484
MICHIGAN
HAMIL TON/AVNET ELECTRONICS
32487 Schoolcraft
Livonia. Michigan 48150
Tel: 313-522-4700 TWX: 810-242-8775
PIONEER/OETROIT
13485 Stamford
Livonia, Michigan 48150

Tel: 313-525-1800
R-M ELECTRONICS
4310 Roger B. Chaffee
Wyoming, Michigan 49508

Tel: 616-531-9300
SCHWEBER ELECTRONICS
33540 Schoolcraft
Livonia, MichIgan 48150
Tel: 313-525:'8100
SHERIOAN SALES CO.
24543 Indoplex Drive
Farmington, MIchigan 48024
Tel: 313-477-3800
MINNESOTA
HAMILTON/AVNET ELECTRONICS
7449 Cahill Road
Edina, Minnesota 55435
Tel: 612-941-3801
TWX: None - use 910-227-0060
(Regional Hq. in Chicago. 111.1
SCHWEBER ELECTRONICS
7402 Washington A.venue S.
Eden Prairie, Minnesota 55344
Tel: 612-941-5280
SEMICONDUCTOR SPECIALISTS. INC.
8030 Cedar Avenue S.
Minneapolis, Minnesota 55420
Tel: 612-884-8841 TWX: 910-576-2812

HAMILTON/AVNET ELECTRONICS
2450 Byalor Drive S.E.
Albuquerque, New Mexico 87119

Tel: 505-765-1500
TWX: None - use 910-379-6488
(Regional Hq. in Mt. View, Ca. I

NEW YORK
ARROW ELECTRONICS
900 Broadhollow Road
Farmingdale, New York 11735

Tel: 516-694-6800
CRAMER ELECTRONICS
129 Oser Avenue
Hauppauge, New York 11787

Tel: 516-231-5682
CRAMER ELECTRONICS
6716 Joy Road
e. Syracuse, New York 13057
Tel: 315-437-6671
COMPONENTS PLUS. INC.
40 Osar Avenue
Hauppauge, L.I.. New York 11787
Tel: 516-231-9200 TWX: 510-227-9869

PIONEER/DAYTON
1900 Troy Street
Dayton, Ohio 45404
Tel: 513-236-9900 TWX: 810-459-1622
SCHWEBER ELECTRONICS
23880 Commerce Park Road
Beachwood. Ohio 44122
Tel: 216-464-2970 TWX: 810-427-9441
SHERIDAN/CLEVELAND
Unit 28
Versaplex Bldg.
701 Beta Drive
Cleveland, Ohio 44143
Tel: 216-461·3300 TWX: 810-427-2957
SHERIDAN SALES CO.
(mailing address)
P.O. Box 37826
Cincinnati, Ohio 45222
(shipping address)
10 Knollcrest Drive
Reading, Ohio 45237
Tel: 513-761-5432 TWX: 810-461-2670

HAMILTON/AVNET ELECTRONICS
6500 Joy Road
E. Syracuse, New York 13057
Tel: 315-437-2642 TWX: 710-541-0959

SHERIDAN SALES COMPANY
2501 Neff Road
Dayton. Ohio 45414
Tel: 513-223-3332 TWX: 810-459-1732

HAMILTQN/AVNET ELECTRONICS
70 State Street
Westbury. LI., New York 11590
Tel: 518-333-5800 TWX: 510-222-8237
ROCHESTER RADIO SUPPLY CO .. INC.
140 W. Main Street
(P.O. Box 1971) Rochester. New York 14603
Tel: 716-454-7800
SCHWEBER ELECTRONICS
Jericho TurnpIke
Westbury, LI .. .New York 11590
Tel: 516-334-7474 TWX: 510-222-3680
JACO ELECTRONICS. INC.
145 Oser Avenue
Hauppauge. L.I.. New York 11787
Tel: 516-273-1234 TWX: 510-227-8232

HAMILTON/AVNET ELECTRONICS
396 Brookes Lane
Hazelwood, Missouri 63042
Tel: 314-731-1144 TWX: 910-762-0606

SUMMIT DISTRIBUTORS. INC.
916 Main Street
Buffalo, New York 14202
Tel: 716-884-3450 TWX: 710-522-1892

NEW JERSEY
HAMILTON/AVNET ELECTRONICS
218 Little Falls Road
Cedar Grove, New Jersey 07009
Tel: 201-239-0800 TWX: 710-994-5787

NORTH CAROLINA
CRAMER ELECTRONICS
938 Burke Street
Winston Salem. North Carolina 27102
Tel: 919-725-8711

HAMILTON/AVNET ELECTRONICS
113 Gaither Drive
East Gate Industrial Park
Mt. Laurel. N.J. 08057
Tel: 609-234-2133 TWX: 710-897-1405

HAMILTON/AVNET
2803 Industrial Drive
Raleigh, North Carolina 27609
Tel: 919-829-8030
HALLMARK ELECTRONICS
1208 Front Street. Bldg. K
Raleigh. North Carolina 27609
Tel: 919-823-4485 TWX: 510-928-1831

STERLING ELECTRONICS
774 Pfeiffer Blvd.
Perth Amboy, N.J. 08861
Tel: 201-442-8000 Telex: 138-679

RESCO
Highway 70 West
Rural Route 8, P.O. Box 11~B
Raleigh. North Carolina 27612
Tel: 919-781-5700

WILSHIRE ELECTRONICS
102 Gaither Drive
Mt. Laurel, N.J. 08057
Tel: 215-827~1920

PIONEER/CAROLINA ELECTRONICS
103 Indultrial Drive
Greensboro. North Carolina 27406
Tol: 919-273-4441

WILSHIRE ELECTRONICS
1111 Paulison Avenue
Clifton, N.J. 07011
Tel: 201-365-!tlOO TWX: 711l-!189-7052

OHIO.
,
HAMILTONlAVNET ELECTRONICS
761 Beta Drive, Suite E
Cleveland. Ohio 44143
Tel: 216-481-1400
TWX: None-use 910-227..()()60
(Regional Hq. In Chicago. IIl.l

NEW MEXICO
CENTURY ELECTRONICS
11728 Linn Avenue
Albuquerque, New Mexico 87123
Tel: 505-292-2700 TWX: 910-989-0625

PIONEER/CLEVELAND
4800 E. 131st Street
Cleveland, Ohio 44105
Tel: 216-587-3600

HAMILTON/AVNET ELECTRONICS
167 Clay Road
Rochester, New York 14623
Tel: 716-442-7820
TWX: None - use 710-332-1201
(Regional Hq. in Burlington. Ma.)

MISSOURI
HALLMARK ELECTRONICS. INC.
13789 Rider Trail
Earth City. Missouri 63045
Tel: 314-291-5350

SCHWEBER ELECTRONICS
43 Belmont Drive
Somerset. N.J. 08873
Tel: 201-469-6008 TWX: 710-480-4733

HAMILTON/AVNET ELECTRONICS
118 West park Road
Dayton, Ohio 45459
Tel: 513-433-0610 TWX: 810-450-2531

OKLAHOMA
HALLMARK ELECTRONICS
4846 S. 83rd East Avenue
Tulsa, Oklahoma 74145
Tel: 918-835-8458 TWX: 910-845-2290
RADIO INC. INOUSTRIAL ELECTRONICS
1000 S. Main
Tulsa, Oklahoma 74119
Tel: 918-587-9123
PENNSYLVANIA
HALLMARK ELECTRONICS. INC.
458 Pike Road
Huntingdon Valley, Pennsylvania 19006
Tel: 215-355-7300 TWX: 510-667-1727
PIONEER/DELEWARE VALLEY ELECTRONICS
141 Gibraltar Road
Horsham. Pennsylvania 19044
Tel: 215-674-4000 TWX: 510~665-6778
PIONEER ELECTRONICS. INC.
560 Alpha Drive
Pittsburgh. Pennsylvania 15238
Tel: 412-782-2300 TWX: 710-795'3122
SCHWEBER ELECTRONICS
101 Rock Road
Horsham, Pennsylvania 19044
Tel: 215-441-0600
SHERIDAN SALES COMPANY
4297 Greensburgh Pike
Suite 3114
Pittsburgh, Pennsylvania 15221
Tel: 412-351-4000
.
SOUTH CAROLINA
DIXIE ELECTRONICS. INC.
P.O. Box 408 {Zip Code 292021
1900 Barnwell Street
COlumbia, South Carolina 29201
Tel: 803-779-5332
TEXAS
ALLlEO ELECTRONICS
401 E. 8th Street
Fort Worth. Texas 78102
Tel: 817-336-5401
CRAMER ELECTRONICS
13740 Midway Road, Suite 700
Dallal. Texas 75240
Tel: 214,881-9300
HALLMARK ELECTRONICS CORP.
10109 McKaiia Place Suite F
AUltin. Texas 78758
Tel: 512-837-2814
HALLMARK ELECTRONICS

8333 Foreet Lane

10-4

DaDal. Texa 75231
Tel: 214-234-7300

FAIRCHILD SEMICONDUCTOR FRANCHISED DISTRIBUTORS
UNITED STATES AND CANADA
HALLMARK ELECTRONICS, INC.
8000 Westglen
Houston, Texas 77063
Tel: 713-781-6100

CAM GARO SUPPLY LTD.
Rookwood Avenue
Fredericton, New Brunswick, E3B 4Y9, Canada

HAMIL TON/AVNET ELECTRONICS
4445 Sigma Road
Dallas, Texas 75240
Tel: 214-661-8661
Telex: HAMAVLECB OAL 73-0511

CAM GARD SUPPLY LTD.
15 Mount Royal Blvd.
Moncton, New Brunswick, E1C BNS, Canada
Tel: 506-855-2200

HAMIL TON/AVNET ELECTRONICS
3939 Ann Arbor
Houston, Texas 77042
Tel: 713-780-1771
Telex: HAMAVLECB HOU 76-2589

SCHWEBER ELECTRONICS, INC.
14177 Proton Road
Dallas, Texas 75240
Tel: 214-661-5010 TWX: 910-860-5493
SCHWEBEA ELECTRONICS, INC.
7420 Harwin Drive
Houston, Texas 77036
Tel: 713-784-3600 TWX: 910-881-1109
STERLING ELECTRONICS
4201 Southwest Freeway
Houston, Texas 77027
Tel: 713-627-9800 TWX: 901-881-5042
Telex: STELECO HOUA 77-5299
UTAH
CENTURY ELECTRONICS
2258 S. 2700 West
Salt Lake City, Utah 84119
Tel: 801-972-6969 TWX: 910-925-5686
HAMILTON/AVNET ELECTRONICS
1585 W. 2100 South
Salt Lake City, Utah 84119
Tel: 801-972-2800
TWX: None - use 910-379-6486
(Regional Hq. in Mt. View. CaJ
WASHINGTON
HAMIL TON/AVNET ELECTRONICS
13407 Northrup Way
Bellevue, Washington 98005
Tel: 206-746-8750 TWX: 910-443-2449
LIBERTY ELECTRONICS
1750 132nd Avenue N.E.
Bellevue, Washington 98005
Tel: 206-453-8300 TWX: 910-444-1379
RADAR ELECTRONIC CO., INC.
168 Western Avenue W.
Seattle, Washington 98119
Tel: 206-282-2511 TWX: 910-444-2052
WISCONSIN
HAMILTON/AVNET ELECTRONICS
2975 Moorland Road
New Berlin, Wisconsin 5315.
Tel: 414-784-4510
MARSH ELECTRONICS, INC.
1563 S. 100 Street
Milwaukee. Wisconsin 53214
Tel: 414-475-6000
CANADA
CAM GARD SUPPLY LTD.
640 42nd Avenue S.E.
Calgary, Alberta. T2G 1Y6, Canada
Tel: 403-287-0520 Telex: 03-822811
CAM GARD SUPPLY LTD.
10505 ll1th Street
Edmonton, Alberta T5H 3E8, Canada
Tel: 403-426-1805 Telex: 03-72960
CAM GARo SUPPLY LTD.
4910 52nd Street
Red Deer. Alberta, T 4N 2C8, Canada
Tel: 403-346-2088

Tel: 506-455-8891

CAM GARD SUPPLY LTD.
3065 Robie Street
Halifax, Nova Scotia, B3K 4P6, Canada
Tel: 902-454-8581 Telex: 01-921528
CAM GARD SUPPLY LTD.
1303 Scarth Street
Regina, Saskatchewan, S4R 2E7, Canada
Tel: 306-525-1317 Telex: 07-12667'
CAM GARD SUPPLY LTD.
1501 Ontario Avenue
Saskatoon. Saskatchewan, S7K 1S7, Canada
Tel: 306-652-6424 Telex: 07-42825
ELECTRO SONIC INDUSTRIAL SALES
!TORONTO) LTD.
1100 Gordon Baker Rd.
Willowdale, Ontario, M2H 3B3, Canada
Tel: 416-494-1666
Telex: ESSCO TOR 06-22030
FUTURE ELECTRONICS CORPORATION
130 Albert Street
Ottawa, Ontario, K1 P 5G4, Canada
Tel: 613-232-7757
FUTURE ELECTRONICS CORPORATION
44 Fasket Drive, Unit 24
Rexdale, Ontario, M9W 1K5, Canada
Tel: 416-677-7820
FUTURE ELECTRONICS CORPORATION
5647 Ferrier Street
Montreal, Quebec, H4P 2K5, Canada
Tel: 514-735-5775
HAMILTON/AVNET INTERNATIONAL
(CANADA) LTD.
6291 Dorman Rd .• Unit 16
Mississauga, Ontario, L4V 1H2, Canada
Tel: 416-677-7432 TWX: 610-492-8867
HAMILTON/AVNET INTERNATIONAL
(CANADA) LTD.
1735 Courtwood Crescent
Ottawa, Ontario. K1Z 5L9, Canada
Tel: 613-226-1700
HAMILTON/AVNET INTERNATIONAL
(CANADA) LTD,
2670 Paulus Street
St. Laurent, Quebec, H4S 1G2, Canada
Tel: 514-331-6443 TWX: 610-421-3731
RAE. INDUSTRIAL ELECTRONICS, LTD.
1629 Main Street
Vancouver, British Columbia, V6A 2W5, Canada
Tel: 604-687-2621 TWX: 610-929-3065
Telex: RAE-VCR 04-54550
SEMAD ELECTRONICS LTD.
625 Marshall Ave., Suite 2
Dorval, Quebec, H9P 1E1, Canada
Tel: 514-636-4614 TWX: 610-422-3048
SEMAD ELECTRONICS LTD.
105 Brisbane Road
Downsview. Ontario M3J 2K6, Canada
Tel: 416-635-9880 TWX: 610-492-2510
SEMAD ELECTRONICS LTD.
1485 laperriere Avenue
Ottawa, Ontario, K1Z 758, Canada
Tel: 613-722-6571 TWX: 610-562-8966

CAM GARD SUPPLY lTD.
825 Notre Dame Drive
Kamloops, British Columbia, V2C 5N8. Canada
Tel: 604-372-3338
CAM GARo SUPPLY L TO,
1777 Ellice Avenue
Winnepeg. Manitoba. R3H OW5. Canada
Tel: 204-786-8401 Telex: 07-57622

10-5

•

FAIRCHILD SEMICONDUCTOR SALES REPRESENTATIVES
UNITED STATES AND CANADA
"'L"'."'M'"
CARTWRIGHT & BEAN. INC.
2400 Bob Wallace Ave., Suite 201
Huntsville, Alabama 35805

Tel: 205-533--3509
C ...LIFORNI ...
CEL TEC COMPANY
18009 Sky Park Circle Suite B
Irvine, Calilornla 92715
Tel: 7'4-557-502' TWX: 9'0-595-25'2
CEL TC COMPANY
7867 Convoy Court, Suite 312
San Diego, California 92111
Tel: 714-279-796' TWX: 9'0-335-'5'2
MAGNA SALES. INC.
3333 Bowers Avenue

Suite 295
Santa Clara, California 95051
Tel: 408-985-'750 TWX: 9'0-336-024'
COLOR ... DO
SIMPSON ASSOCIATES. INC.

2552 Ridge Road
littleton, Colorado 80120
Tel: 303-794-836' TWX: 9'0-935-0719

CONNI!CTICUT
PHOENIX SALES COMPANY
3.89 Main Street
Ridgefield, Connecticut 06877
Tol: 203-438-9844 TWX: 7'0-467-0662

MINNESOT...
PSI COMPANY
720 W. 94tt!. Street
Minneapolis, Minnesota 55420
Tel: 6'2-884-'777 TWX: 9'0-576-3483

CARTWRIGHT & BEAN. INC

MISSISSIPPI
CARTWRIGHT & BEAN. INC.

TEX...S
TECHNICAL MARKETING
3320 Wiley Post Road
eharrollton. Texas 75220
Tel: 214-387-3601 TWX: 910-860-5158

P.O. Box 16728
5150 Keele Street
JaCkson. Mississippi 39206
Tel: 60'-98'-'368
MISSOURI
B.C. ELECTRONIC SALES. INC.
300 Brookes Drive, Suite 206
Hazelwood. Missouri 63042
Tel: 3'4-731-1255 TWX: 9'0-762-0600
NEW JERSEY
LORAC SALES, INC.
580 Valley Road
Wayne, New Jersey 07470
Tel: 20'-698-8875 TWX: 7'0-966-5846
NEW YORK
LORAC SALES. INC.
550 Old Country Road, Room 410
Hicksville, New York 11801
Tel: 516-681-8746 TWX: 510-224-6480
TRI'TECH ELECTRONICS. INC.
3215 E. Main Street
Endwell, New York 13760
Tel: 607-754-'094 TWX: 5'0-252-089'

FLORIO...
LECTROMECH. INC.
303 Whooping loop
Altamonte Springs. Florida 32701
Tel: 305-831-1577 TWX: 810-853-0262

TRI-TECH ELECTRONICS. INC.
590 Perinton Hills Office Park
Fairport, New York 14450
Tel: 716-223-5720

LECTROMECH. INC.
1350 S. Powerline Road, Suite 104
Pompano Beach, Florida 33060
Tel: 305-974-6780 TWX: 5'0-954-9793

TRI-TECH ELECTRONICS. INC.
6836 E. Genesee Street
Fayetteville. New York 13066
Tel: 3'5-446-288' TWX: 7'0-541-0604

LECTROMECH. INC.
2260 U.S. Highway 19 North
Suite 119 Bldg. l
Clearwater. Florida 33515
Tel: 813-7~541

TRI-TECH ELECTRONICS. INC.
19 Davis Avenue
Poughkeepsie. New York 12603
Tel: 914-473-3880

GEORGI...
CARTWRIGHT & BEAN. INC.
P.O. Box 52846 (Zip Code 303551
90 W. Wleuca Square, Suite 155
Atlanta, Georgia 30342
Tel: 404-255-5262 TWX: 8'0-75'-3220
ILLINOIS
MICRO SALES. INC.
2258-8 landmelr Road
Elk Grove Village, illinois 60007
Tel: 3'2-956-'000 TWX: 9'0-222-'833
INOIAN...
LESLIE M. DEVOE COMPANY
4215 E. 82nd Street Suite 0
Indianapolis, Indiana 46250
Tel: 317-842-3245 TWX: 810-260-1435

K...N....S
B.C. ELECTRONIC SALES. INC.
P.O. Box '2485. Zip 882'2
8190 Nieman Road
Shawnee Mission, Kansas 66214
Tel: 9'3-888-6680 TWX: 9'0-749-64'4
B.C. ELECTRONIC SALES

NORTH CAR OLIN...
CARTWRIGHT & BEAN. INC.
1165 Commercial Ave.
Charlotte, North Carolina 28205
Tel: 704-377-5873
CARTWRIGHT & BEAN. INC.
P.O. Box 18465
3948 Browning Place
Raleigh, North Carolina 27609
Tel: 9'9-78'-6580
OHIO
THE LYONS CORPORATION
4812 Frederick Road, Suite 101
Dayton, Ohio 45414
Tel: 513-278-0714
THE LYONS CORPORATION
8151 Wilson Mills Road, Suite 101
Highland Heights, Ohio 44143
Tel: 216-461-8288
OKLAHOM...
TECHNICAL MARKETING
9717 E. 42nd Street, Suite 221
Tulsa, Oklahoma 74101
Tel: 9'6-622-5984

6406 E. Kellogg
Suite 14
Wichita, Kansas 87207
Tel: 3'8-884-005'
M ...RYL...ND
DELTA III ASSOCIATES
1000 Century Plaza Suite 225
Columbia, Maryland 21044
Tol: 30'-730-'5'0 TWX: 7'0-826-9654

MAS....CHUSITTS
SPECTRUM ASSOCIATES. INC.
888 Worcester Street
Wellesley. U_achusetls 02181
Tel: 8'7-237-2796 TWX: 7'0-346-0424
MICHIG...N
RATHSBURG ASSOCIATES
18821 E. Warren Avenue
Detroit, Michigan 48224
Tel: 313-882-'7'7 Telox: 23-5229

OREGON
aUADRA CORPORATION
'9'45 S.W. Murphy Ct.
Aloha, Oregon 97005
Tel: 503-225-0350 TWX: 9'0-449-2592
PENNSYLV... NI'"
BGR ASSOCIATES
2500 Office Center
2500 Maryland Road
Willow Grove, Pennsylvania 19090
Tel: 215-657-3301
TlNNEIIEI
CARTWRIGHT & BEAN. INC.
P.O. 80x 4760
580 S. Cooper Street
Memphis, Tennessee 38104
Tel: 90' -276-4442

10-6

8705 Unicorn Drive
Suite 8120
Knoxville, Tennessee 37919

Tel: 615-693-7450

TECHNICAL MARKETING
6430 Hillcroft. Suite 104
Houston, Texas 77036

Tel: 713-777-9228
UT... H
SIMPSON ASSOCIATES, INC.
P.O. Box 151430
Salt lake City, Utah 84115
Tel: 801-571-7877
W...SHINGTON
aUADRA CORPORATION
14825 N.E. 40th Street
Suite 340
Redmond, Washington 98052
Tel: 206-883-3550 TWX: 9'0-449-2592
WISCONSIN
LARSEN ASSOCIATES
10855 West Potter Road
Wauwatosa, Wisconsin 53226
Tel: 4'4-258-0529 TWX: 9'0-262-3'60
C ...NAO...
R.N. LONGMAN SALES. INC. IL.S.I.I
1715 Neyeralde Drive
SUite 1
Mississauga, Ontario, l5T 1C5 Canada
Tel: 4'6-625-6710 TWX: 6'0-492-9976
R.N. LONGMAN SALES, INC. IL.S.U
16891 Hymus Blvd.
Kirkland, Quebec
H9H 314 Canada
Tel: 514-694-3911
TWX: 6' 0-422-3028

FAIRCHILD SEMICONDUCTOR SALES OFFICES
UNITED STATES AND CANADA
ALABAMA
Huntsville Office
Executive Plaza
Suite 107
4717 University Orive, N,W.
Huntsville. Alabama 35805
Tel: 205-837-8906
ARIZONA
Phoenix Office
4414 N. 19th Avenue 85015
Suite G
Tel: 602-264-4948 TWX: 910-951-1544

CALIFORNIA
Los Angeles Office"
Crocker Bank Bldg.
15760 Ventura Blvd. Suite 1027
Encino 91436
Tel: 213-990-9800 TWX: 910-495-1776
Santa Ana Office"
2101 E. 4th Street 92705
Bldg. B. Suite 185
Tel: 714-558-1881 TWX: 910-595-1109
Santa Clara Office"
3333 Bowers Avenue
Suite 299
Santa Clara, 95051

INDIANA
Ft. Wayne Office
2118 Inwood Drive 46805
Suite 111
Tel: 219-483-6453 TWX: 810-332-1507

NEW MEXICO
Alburquerque Office
2403 San Mateo N.E. 87110
Plaza 13
Tel: 505-265-5601 TWX: 910-379-6435

India~apolis Office
Room 205
7202 N. Shadel and 46250
Tel: 317-849-5412 TWX: 810-260-1793

NEW YORK
Melville Office
275 Broadhollow Road 11746
Tel: 516-293-2900 TWX: 510-224-6480

KANSAS
Kansas City Office
Corporate Woods
10875 Grandview, Suite 2255
Overland Park 66210
Tel: 913-649-3974

Poughkeepsie Office
19 Davis Avenue 12803
Tel: 914-473-5730 TWX: 510-248-0030

MARYLAND
Columbia Office·
1000 Century Plaza
Suite 225
Columbia, Maryland 21044
Tel: 301-730-1510 TWX: 710-826-9654
MASSACHUSETTS
Boston Office888 Worcester Street
Wellesley Hills 02181
Tel: 617-237-3400 TWX: 710-348-0424

Tel: 408-987-9530 TWX: 910-338-0241
FLORIOA
Flo Lauderdale Office
Executive Plaza
Suite 300-8
1001 Northwest 62nd Street
Ft. Lauderdale, Florida 33309
Tel: 305-771-0320 TWX: 510-955-4098
Orlando Office·
Crane's Roost Office Park
303 Whooping Loop
Altamonte Springs 32701
Tel: 305-834-7000 TWX: 810-850-0152
ILLINOIS
Chicago Office
The Tower - Suite 610
ROlling Meadows 60008
Tel: 312-640-1000

MICHIGAN
Detroit OfficeJohnston Building, Suite 24
20793 Farmington Road
Farmington Hills 48024
Tel: 313-478-7400 TWX: 810-242-2973

Fairport Office
260 Perinton Hills Office Park
Fairport 14450
Tel: 716-223-7700
OHIO
Dayton Office
4812 Frederick Road 45414
Suite 105
Tel: 513-278-8278 TWX: 810-459-1803
PENNSYLVANIA
Philadelphia Office
2500 Office Center
2500 Maryland Road
Willow Grove, Pennsylvania 19090
Tel: 215-657-2711
TEXAS
Dallas Office
13771 N. Central Expressway 75231
Suite 809
Tel: 214-234-3391 TWX: 910-867-4757

MINNESOTA
Minneapolis Office·
7600 Parklawn Avenue
Room 251
Edina 55435
Tel: 612-835-3322 TWX: 910-576-2944

Houston Office
6430 Hillcroft 77081
Suite 102
Tel: 713-771-3547 TWX: 910-881-8278

NEW JERSEY
Wayne Office580 Valley Road 07490
Suite 1
Tel: 201-898-7070 TWX: 710-988-5846

CANADA
Toronto Regional Office
Fairchild Semiconductor
1590 Matheson Blvd., Unit 28
Mississauga, Ontario L4W 1J1, Canada
Tel: 416-625-7070 TWX: 610-492-4311

•

·Field Application Engineer

10-7

FAIRCHILD SEMICONDUCTOR
INTERNATIONAL SALES OFFICES
AUSTRALIA
Fairchild Australia Ply ltd.
72 Whiting Street
Artarmon 2064
New South Wales
Australia
Tel: Sydney (02)-436-2733
(mailing address)
P.O. Box 450
North Sydney 2060
New South Wales
Australia

AUSTRIA AND EASTERN EUROPE
Fairchild Electronics

A-l0l0 Wien
$chwedenplatz 2
Tel: 0222 635821 Telex: 75096

BRAZIL
Fairchild $emicondutores Uda
Caixa Postal 30407
Rue Alagoss, 663
01242 Sao Paulo, Brazil
Tel: 66-9092 Telex: 011-23831
Cable: FAIRLEC

FRANCE
Fairchild Camera & Instrument S.A.
121, Avenue d'italie
75013 Paris, France

Tel: 331-584-55 66
Telex: 0042 200614 or 260937
GERMANY
Fairchild Camera and Instrument !Deutschland)
Oaimlerstr 15
8046 Garching Hochbruck
Munich, Germany
Tel: (089) 320031 Telex: 524831 fair d
Fairchild Camera and Instrument 
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