1978_Harris_Memory_Vol1 1978 Harris Memory Vol1
User Manual: 1978_Harris_Memory_Vol1
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~RIS
SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION
Volume 1
Volume 1
$2.95
Harris
Bipolar & CMOS
Memory
Data Book
Harris Semiconductor Memory Products represent
state-of-the-art in density and high speed performance. Harris' expertise in design and processing offers
the user the most reliable product available in a wide
choice of formats, options, and package types. With
continuing research and development· and the introduction of new products, Harris will provide its customers with the most advanced technology.
This book describes Harris Semiconductor Products
Division's complete line of memory products and
includes a complete set of product specifications and
data sheets. Also included are sections on reliability,
programming, and packaging.
Please fill out the registration card at the back of this
book and return it to us so we may keep you informed
of our latest new product developments over the next
year.
If you need more information on these and other
Harris products, please contact the nearest Harris
sales office listed in the back of this data book.
Harris Semiconductor's products are sold by description only.
Harris reserves the right to make changes in circuit design, specifi:
cations and other information at any time without prior notice.
Accordingly, the reader is cautioned to verify that data sheets and
other information in this publication are current before placing
orders. Information contained in application notes is intended
solely for general guidance; use of the information for user's specific application is at user's risk. Reference to products of other
manufacturers are solely for convenience of comparison and do
not imply totai equjvalency of design, performance, or~therwise.
Copyright
© Harris Corporation 1978
(All rights reserved)
Printed In USA
Genera I I nformation
Alpha-Numeric Index of
Total Harris Product
Product Index by Families
Harris Memory Selection Guide
Cross Reference Guide
II
(1-1)
(1-5)
(1-6)
/
(1-7)
Bipolar M e m o r v B
CMOS Memory
II
CMOS Interface
II
Harris Reliability & Quality
II
Ordering & Packaging
Dice Information
Harris Sales Locations
iii
II
IJ
II
Total Harris Product Index
HA-909
HA-911
HA-2050
HA-2050A
HA-2055
HA-2055A
HA-2060
HA-2060A
HA-2065
HA-2065A
HA-2400
HA-2404
HA-2405
HA-2420
HA-2425
HA-2500
HA-2502
HA-251O
HA-2512
HA-2515
HA-2520
HA-2522
HA-2525
HA-2530
HA-2535
HA-2600
HA-2602
HA-2605
HA-2620
HA-2622
HA-2625
HA-2630
HA-2635
HA-2640
HA-2645
HA-2650
HA-2655
HA-2700
HA-2704
HA-2705
HA-2720
HA-2725
HA-2730
HA-2735
HA-2900
HA-2904
HA-2905
HA-4602
HA-4605
HA-4622
HA-4625
HA-4741
HA-4900
HA-4905
HC-55516
HC-55532
Low Noise Operational Amplifier
Low Noise Operational Amplifier
High Slew Rate F.E.T. Input Operational Amplifier
High Slew Rate F.E.T. Input Operational Amplifier
High Slew Rate F.E.T. Input Operational Amplifier
High Slew Rate F.E.T. Input Operational Amplifier
Wide Band F.E.T. Input Operational Amplifier
Wide Band F.E.T. Input Operational Amplifier
Wide Band F.E.T. Input Operational Amplifier
Wide Band F.E.T. Input Operational Amplifier
PRAM, Four Channel Operational Amplifier
PRAM, Four Channel Operational Amplifier
PRAM, Four Channel Operational Amplifier
Sample and Hold
Sample and Hold
Precision High Slew Rate Operational Amplifier
Precision High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
High Slew Rate, Uncompensated Operational Amplifier
High Slew Rate, Uncompensated Operational Amplifier
High Slew Rate, Uncompensated Operational Amplifier
Wide Band High Slew Inverting Amplifier
Wide Band High Slew Inverting Amplifier
High Performance Operational Amplifier
High Performance Operational Arpplifier
High Performance Operational Amplifier
Very Wide Band, Uncompensated Operational Amplifier
Very Wide Band, Uncompensated Operational Amplifier
Very Wide Band, Uncompensated Operational Amplifier
High Performance Current Booster
High Performance Current Booster
High Voltage Operational Amplifier
High Voltage Operational Amplifier
Dual High Performance Operational Amplifier
Dual High Performance Operational Amplifier
Low Power, High Performance Operational Amplifier
Low Power, High Performance Operational Amplifier
Low Power, High Performance Operational Amplifier
Low Power, Current Programmable Operational Amplifier
Low Power, Current Programmable Operational Amplifier
Dual Low Power, Current Programmable Operational Amplifier
Dual Low Power, Current Programmable Operational Amplifier
Chopper Stabilized Operational Amplifier
Chopper Stabilized Operational Amplifier
Chopper Stabilized Operational Amplifier
Quad High Performance Operational Amplifier
Quad High Performance Operational Amplifier
Wide Band, High Performance Quad Operational Amplifier
Wide Band, High Performance Quad Operational Amplifier
Quad Operational Amplifier
Quad Precision Comparator
Quad Precision Comparator
Delta Modulator (CVSD)
Delta Modulator (CVSD)
1-1
I
I
HD-106S
HD-24S
HD-246
HD-248
HD-249
HD-4702
HD-6101
HD-6102
HD-6103
HD-6402
HD-640S
HD-6431
HD-6432
HD-6433
HD-6440
HD-649S
HD":6600
HD-1S530
HD-1SS31
HI-200
HI-20l
HI-S06
HI-S06A
HI-S07
HI-S07A
HI-S08A
HI-S09A
HI-S62
HI-l080
HI-108S
HI-1800A
HI-18l8A
HI-1828A
HI-1840
HI-S040
HI-S041
HI-S042
HI-S043
HI-5044
HI-S046
HI-S046A
HI-S047
HI-S047A
HI-S048
HI-S049
HI-SOSO
HI-SOS1
HI-S610
HI-S612
HM-0104
HM-0110
HM-0168
HM-0186
HM-0198
HM-0410
HM-6100
HM-6312
HM-6388
HM-6389
HM-6S01
HM-6S03
Keyboard Encoder
Triple Line Transmitter
Triple Line Receiver
Triple Party Line Receiver
Triple Line Receiver
CMOS Bit Rate Generator
CMOS Parallel Interface Element
CMOS Memory Extension/DMA/lnterval Timer/Controller
CMOS Parallel Input-Output .Port
CMOS Universal Assynchronous Receiver-Transmitter
CMOS Bit Rate Generator
CMOS Three State Latching Bus Driver
CMOS Bi-Directional Bus Driver
CMOS Bus Separator Driver
CMOS 1 of 8 Latched Decoder Driver
CMOS Three State Buffer Driver
Quad PROM Power Strobe
CMOS Manchester Encoder/Decoder (24 Pin)
CMOS Manchester Encoder/Decoder (40 Pin)
Dual SPST Switch
Quad SPST Switch
16/Dual 8 Channel Multiplexer
Overvoltage Protected 16/Dual 8 Channel Multiplexer
16/Dual 8 Channel Multiplexer
Overvoltage Protected 16/Dual 8 Channel Multiplexer
Overvoltage Protected 8/Dual 4 Cl'\annel Multiplexer
Overvoltage Protected 8/Dual 4 Channel Multiplexer
12 Bit High Speed, Precision Digital to Analog Converter
8 Bit Precision Digital to Analog Converter
8 Bit Precision Digital to Analog Converter
Dual DPDT Low Leakage Switch
8/Dua14 Channel Multiplexer
8/Dual 4 Channel Multiplexer
Fail-Safe 16 Channel Multiplexer
Low Resistance SPST Switch
Low Resistance Dual SPST Switch
Low Resistance SPST Switch
Low Resistance Dual SPOT Switch
Low Resistance DPST Switch
Low Resistance DPPT Switch
Low Resistance DPDT Switch
Low Resistance 4 PST Switch
Low Resistance 4 PST Switch
Low.Resistance Dual SPST Switch
Low Resistance Dual DPST Switch
Low Resistance SPOT Switch
Low Resistance Dual SPOT Switch
10 Bit High Speed Precision 0 to A Converter
12 Bit Very High Speed Precision 0 to A Converter
10 x 4 Diode Matrix
4 x 10 Diode Ma.trix
6 x 8 Diode Matrix
8 x 6 Diode Matrix
9 x 8 Diode Matrix
4x 10 Diode Matrix
CMOS 12 Bit Microprocessor
1024 x 12 CMOS ROM
8192 x 8CMOSROM
8192 x 8 CMOS ROM
2S6 x 4 CMOS RAM
2048 x 1 CMOS RAM
1-2
HM-6504
HM-6508
HM-6511
HM-6512
HM-6513
HM-6514
HM-6518
HM-6533
HM-6543
HM-6551
HM-6561
HM-6562
HM-6611
HM-6661
HM-7602
HM-7603
HM-76LS03
HM-7608
HM-7610
HM-7610A
HM-7611
HM-7611A
HM-7616
HM-76160
HM-76161
HM-7620
HM-7620A
HM-7621
HM-7621A
HM-7625R
HM-7629
HM-7640
HM-7640A
HM-7640AR
HM-7641
HM-7641A
HM-7641AR
HM-7642
HM-7642A
HM-7642P
HM-7643
HM-7643A
HM-7643P
HM~7644
HM-7644A
HM-7645
HM-7645P
HM-7647R
HM-7648
HM-7649
HM-7680
HM-7680R
HM-7680P
HM-7680RP
HM-7681
HM-7681R
HM-7681P
HM-7681RP
HM-7683
HM-7684
4096 x 1 CMOS RAM
1024 x 1 CMOS RAM
64 x 12 CMOS RAM
64 x 12 CMOS RAM
512 x 4 CMOS RAM
1024 x 4 CMOS RAM
1024 x 1 CMOS RAM
1024 x 4 CMOS RAM
4096 x 1 CMOS RAM
256 x 4 CMOS RAM
256 x 4 CMOS RAM
256 x 4 CMOS RAM
256 x 4 CMOS PROM
256 x 4 CMOS PROM
32 x8 Bipolar PROM - Open Collector
32 x 8 Bipolar PROM - Three State
32 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - Open Collector
256 x 4 Bipolar PROM - Open Collector
256 x 4 Bipolar PROM - Open Collector
256 x 4 Bipolar PROM - Three State
256 x 4 Bipolar PROM - Three State
2048 x 8 Bipolar PROM - Three State
2048 x 8 Bipolar PROM - Open Collector
2048 x 8 Bipolar PROM - Three State
512 x 4 Bipolar PROM - Open Collector
512 x 4 Bipolar PROM - Open Collector
512 x 4 Bipolar PROM - Three State
512 x 4 Bipolar PROM - Three State
256 x 8 Bipolar PROM - Three State
256 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Open Collector
512 x 8 Bipolar PROM - Open Collector
512 x 8 Bipolar PROM - Open Collector
512 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Open Collector
1024 x 4 Bipolar PROM - Open Collector
1024 x 4 Bipolar PROM - Open Collector
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM
1024 x 4 Bipolar PROM
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Open Collector
512 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM
2048 x 4 Bipolar PROM - Open Collector
1-3
II
HM-7684P
HM-7685
HM-7685P
HM-7686
HM-7686R
HM-7686P
HM-7686RP
HM-7687
HM-7687R
HM-7687P
HM-7687RP
JAN-0512
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
2048 x 4 Bipolar PROM
JAN Qualified PROM
I
1-4
-
Open Collector
Three State
Three State
Open Collector
Open Collector
Open Collector
Open Collector
Three State
Three State
Three State
Three State
Devices by Families
BIPOLAR PROMS
(Section 2)
JAN 0512
HM-76XX
HM-7602/03
HM-7610/11
HM-7620/21
HM-7640/41
HM-7642/43/44
HM-76LS03
HM-760a
HM-7610Al11A
HM-7616
HM-76160/161
HM-7620A/21A
HM-7625R
HM-7629
HM-7640A/41A
HM-7640AR/41 AR
HM-7642A143A
HM-7642P/43P
HM-7644A
HM-7645
HM-7645P
HM-7647R
HM-7648/49
HM-7680/81
HM-7680R/81 R
HM-7680P/81 P
HM-7680RP/81 RP
HM-7683
HM-7684/85
HM-7684P/85P
HM-7686/87
HM-7686/R/87R
HM-7686P/87P
HM-7686RP/87RP
CMOS BUS DRIVERS
(Section 4)
HD-6431
HD-6432
HD-6433
HD-6440
HD-6440A
HD-6495
CMOS INTERFACE
(Section 4)
HD-4702
HD-6402
HD-6405
CMOS PROMS
(Section 3)
CMOS ROMS
(Section 3)
HM-6312
HM-6388
HM-6389
DIODE MATRICES
(Section 4)
HM-0104
HM-0168
HM-0186
HM-0198
HM-0410
II
HM-6611
HM-6611A
HM-6661
HM-6661A
CMOS RAMS
(SeCtion 3)
HM-6501
HM-6503
HM-6504
HM-6508
HM-6511
HM-6512
HM-6513
HM-6514
HM-6518
HM-6533
HM-6543
HM-6551
HM-6561
HM-6562
Data Sheet Classifications
CLASSIFICATION
Pre"iew
DATA
SHEET
Ad"anr:e
Information
PRODUCT STAGE
DISCLAIMERS
Formative or
Design
This document contains the design specifications
for product under development. Specifications
may be changed in any manner without notice.
Sampling or
Pre-Production
This is advanced information, and specifications
are subject to change without notice.
First Production
Supplementary data maybe published at a
later date.
DATA SHEET
Prelimina"
DATA SHEET
Harris reserves the right to make changes at anytime without notice, in order to improve design
and supply the best product possible.
1-5
Harris M'emory Selectic>n Guide
NUMBER
WORDS
....------,
32
II
1
2
4
BYTE SIZE
1-6
8
12
Bipolar PROM Cross Reference
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AMD
27LS08
27S08
29750
27S18
27LS09
27S09
29751
27S19"
27LS100
27S10
29760
27LS20
27LSll
27S11
29761
27LS21
27812
29770
27S13
29771
HARRIS
7602
7603
7610/10A
7611/11A
7620/20A
7621/21A
INTEL
3601
3621
3602/02A
3622/22A
3604/04A
3604L
3624/24A
3605
3625
3608
3628
HARRIS
7610/10A
7611/11A
7620/20A
7621/21A
7640/41 A
7641/41A
7642
7643
7680
7681
MOTOROLA
MCM5303A
MCM7640
MCM7641
MCM7642
MCM7643
MCM2708
HARRIS
JAN 38510/201
7640/40A
7641/41 A
7642
7643
7608
RAYTHEON
29660
29662
29661
29663
29611
29613
29620
29622
29624
29625
29621
29623
29625
29627
29630
29632
29631
29633
29634
29635
29636
29637
HARRIS
7610/10A
7611/11A
7620/20A
7648
7640/40A
7649
7641/41A
7680
7681
7608
FAIRCHILD
93417
93427
93436
93446
93438
93448
93452
93453
93450
93451
HARRIS
7610/10A
7611/11A
7620/20A
7620/21A
7640/40A
7641/41A
7642
7643
7680
7681
FUJITSU
MB7056
MB7051
MB7057
MB7052
MB7058
MB7053
MB7059
MB7054
MB7060
MB7055
HARRIS
7602
7603
7610/10A
7611/11A
7620/20A
7620/21 A
7642
7643
7680
7681
INTERSIL
5600
5610
5603
5623
5604
5624
5605
5625
56506
56526
HARRIS
7602
7603
7610/10A
7611/11A
7620/20A
7621/21A
7640/40A
7641/41A
7642
7643
NATIONAL
DM8577
DM74S188
DM8578
DM74S288
DM74S387
DM748287
DM748473
DM878295
DM74S472
DM87S296
DM74S572
DM74S573
DM878229
DM87S228
DM74S672
DM74S673
DM27LS08
HARRIS
7602
MMI
6330
6331
6300
6301
6305
6306
6348
6340
6349
6341
6352
6353
6380
6381
6385
63100
63101
6336
HARRIS
7602
7603
7610/10A
7611/11A
7620/20A
7621/21A
7648
7640/40A
7649
7641/41A
7642
7643
7680
7681
7608
7684
7685
7629
NEC
j.!PB403
PB405
PB425
PB406
PB426
PB408
PB428
j.!PB427
HARRIS
7610/10A
7640/40A
7641/41A
7642
7643
7680
7681
7608
7603/L803
7610/10A
7611 llA
7648
7640/40A
7649
7641/41A
7642
7643
7680
7681
7684
7685
7608
SIGNETICS
82S23
828123
82S27
82S126
82S129
82S131
82S146
82S140
828147
82S141
82S136
82S137
82S180
82S181
82S2708
82S184
82S185
82S114
82S190
82S191
HARRIS
7602
7603
7610/10A
7611/11A
7620/20A
7648
7640/40A
7649
7641/41A
7642
7643
7680
7681
7608
7684
7685
7625R
76160
76161
1-7
TEXAS INST.
74S188/188A
748288
74186
74S387
74S287
748473
748475
748472
748474
-94S477
748476
HARRIS
7602
7603
JAN 38510/201
7610/10A
7611/11A
7648
7640/40A
7649
7641/41 A
7642
7643
I
CMOS Memory Cross Reference
I
AMD
9111
9101
9102
91.12
9130
9140
HARRIS
6561
6501
6508
6562
6533
6543
AMI
2114
2147
4025
5101
6508
HARRIS
6514
EA
2101
2111
2112
HARRIS
6501
6561
6562
Al
Al
Al
FAIRCHILD
2101
HARRIS
6508
Cl
GI
RA3-4256
4801
4804
2114
HARRIS
EMM
2114
HARRIS
6501
6508
6514
6514
INTERSIL
6504
6508
6512
6518
6551
6561
7101
7111
7112
7114
7141
7552
HARRIS
6504
6508
6512
6518
6551
6561
INTEL
2101
2102
2111
2112
2113
2114
2147
5101
HARRIS
6501
6508
6561
6562
6513
6514
6501
B2
Al
Cl
Al
~
MOSTEK
4102
4103
4104
4404
4451
HARRIS
6508
Cl
6504
6514
6514
A2
C2
C2
A3
Al
Al
A3
Al
Al
A3
A3
A3
A3
A3
A3
Al
Cl
Al
Al
Al
Al
Al
MOTOROLA
HARRIS
2114
6514
7001
I
Al
I
I
NATIONAL
2101
2102
2111
2114
5257
5269
74C920
74C921
74C929
74C930
HARRIS
6501
6508
6561
6561
6504
NEC
2101
2102
2111
2112
4PD415
5101
6508
HARRIS
6501
6508
6561
6562
RCA
4101
4111
4112
5001
5040
5501
5540
5114
HARRIS
6501
6561
6562
6508
6501
6508
6501
6514
Al
Bl
Al
Al
AI.
Al
Al
Al
SIGNETICS
2101
2102
2111
2601
2606
2613
2614
HARRIS
6501
6508
6561
Al
Cl
Al
SYNERTEK
2101
2102
2111
2112
2114
5101
5102
5111
5112
HARRIS
6501
6508
6561
6562
6514
6501
6508
6551
6561
6508
6518
6501
6508
6562
6504
6514
1-8
Al
Cl
Al
Al
Al
A3
A3
A3
A3
TI
2101
2102
2112
2114
4033
4039
4042
4043
4044
4045
5101
6508
TOSHIBA
5504
5501
5508
5047
54104
HARRIS
6501
6508
6562
6514
6508
6501
6561
6562
6504
6514
6501
6508
Al
Cl
Al
. Al
. Cl
Al
Al
Al
Al
Al
Al
A3
HARRIS
6504
6501
6508.
6514
6504
A3
A3
A3
C3
C3
A1
Cl
Al
Al
Al
A3
C2
A2
A2
Al
Cl
Al
Al
Al
Al
Cl
A - Pin for Pin Replacement
B - Minor Pinout Differences
C - Not Pin Compatible
1 - Synchronous-Asynchronous Differences
2 - NMOS Rather Than CMOS but Similar
3 - Similar Electrical Characteristics
User's Guide to Static RAM's
•
»
-'
I
co
II
2-1
Harris Generic Programmable
Read Only Memories
In 1970, Harris offered the industry's first Bipolar programmable read only memory, and
has been a leader in the field of Bipolar PROMs from 1970 to date. Harris PROMs are
manufactured using the Bipolar Junction Isolation process with reliability proven nickel
chromium fusible links. Harris has had experience with nichrome since 1964 when it was
first used for high reliability military circuits because of its high stability characteristics.
Harris has been manufacturing nichrome fuse links since 1970 when the first PROM was
manufactured, and has become the industry's most extensive programmable read only
memory concept. This history has been a factor in giving Harris PROMs the industry's
highest programming yield and a proven level of quality and reliability.
We now employ a shallow diffused self-aligned emitter aperture process conbined with
two-:level aluminum interconnect. This state of the art process technology has been
deployed to produce large format devices with the high speed and versatility required
by the industry.
Today Harris offers a family of programmable read only memories which we call the
Generic PROMs or GPROMs. They have the following characteristics:
•
Coherent part numbering scheme, the 76xxx series.
•
Identical programming procedure for all GPROMs.
•
All parameters are guaranteed over full temperature and voltage.
•
The GPROM family comprises a complete range of formats.
JAN QUALIFIED PROMS
The Harris Semiconductor Bipolar manufacturing line has received certification for processing JAN product. The Harris JAN 0512 is a QPL I JAN qualified PROM. Four additional Harris PROMs have been granted QPL II listing pending QPL I approval and may be
shipped as JAN qualified product. Additional Harris PROMs are at various stages of
qualification and the status of each at press time is listed below. As the status of these
products will change rapidly, we suggest that you contact the nearest Harris Representative
or Harris Sales Office for current status.
HARRIS PART#
JAN 0512
HM1-7610
HM1-7611
HM1-7620
HM1-7621
HM1-7642
HM1-7643
HM1-7644
HM1-7602
HMl-7603
HM1-7640
HM1-7641
SLASH SHEET
MI L-M-38510/20101
MIL-M-38510/20301
MI L-M-3851 0/20302
Mi L-M-3851 0/20401
MIL-M-38510/20402
MI L-M-3851 0/20601
MIL-M-38510/20602
MI L-M-3851 0/20603
MI L-M-3851 0/207 .
MI L-M-3851 0/207
MI L-M-3851 0/208
MI L-M-3851 0/208
2-3
STATUS
BJB
BEB
BEB
BEB
BEB
BVB
BVB
BEB
QPLI
QPL II
QPL II
QPL II
QPL II
Pending
Pending
Pending
Pending
Pending
Pending
Pending
QPL II
QPL II
QPL II
Slash Sheets
Slash Sheets
Slash Sheets
Slash Sheets
I
mJ
HARRlS
SEMICONDUCTOR
PRODUCTS DIVISION
HD-6600
A DIVISION OF HARRIS CO.RPORATI.ON
QUAD POWER STROBE
FEBRUARY 197B
Features
•
HIGH DRIVECURRENT-;ZO.OmA
•
HIGH SI'EED 50ns TYI'ICAL
•
TTL COMI'ATIBLE INI'UTS
logic Diagram
1.
•
DIELECTRIC ISOLATION
•
QUAD MONOLITHIC CONSTRUCTION
•
I'OWE.R SUI'I'LY FLEXIBILITY
•
LOW POWER:
STANDBY-30mW/CIRCUIT
NC
VCC3
14
13
2
3~----'
'-----""1 '2
ACTIVE-95mW/CIRCUIT
VCCI
11
.----""1 '0
9
6
Description
GND
The HO-6600 Quad Power Strobe is constructed with Harris Dielectric
Isolation Bipolar _Monolithic Process. The design incorporates powersupply flexibility with TTL compatible inputs and high current outputs.
This circuit is intended for use'in power switched PROM arrays.
I'
Circuit Diagram
(ONE OF FOUR IDENTICAL STROBES)
.-----...-----0
VCC2
._---oVCC3
INPUT
0-";"'-""
~--~-~----~-----,---oOUTPUT
L------~~----------~~--<)GND
2-:4
NC
8
Specifications HD-6600
ABSOLUTE MAXIMUM RATINGS
+8 VDC
+18 VDC
+18 VDC
-0.5 VDC to +5.5 VDC
-65 0 C to +150 0 C
-200m A
1000mW
(Derate 9mW/OC Above 60 0 C)
Power Supply Voltage VCCl
VCC2
VCC3
Input Voltage VIN
Storage Temperature TSTG
Output Current IL
Power Dissipation at 25 0 C
RECOMMENDED OPERATING CONDITIONS
Power Supplies:
TA = -55 0 C to +125 0 C HDl-6600-2
TA = OOC to +75 0 C HDl-6600-5
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
IIR
MIN.
TYP.
I nput Current
IIF
VIH
Input Threshold
VIL
Voltage
MAX.
UNITS
60
-1.6
J1A
mA
0.8
V
4.75
VCC2 = 12.0 VDC
VCC3 = 5.0 VDC
TEST CONDITIONS
VIN
VIN
V
2.0
VOH
D.C.
5 VDC ± 10%
12VDC±15%
5 VDC± 20%
VCC1
VCC2
VCC3
V
VCCl
= 5.0 VDe
IL
~ ~150triA
1.0
V
VCCl
= 5.0 VDe
IL
= 500J1A
VCCl
= 5.5 VDe
VIN
VIN
ICCl
4
6.0
mA
ICC2
40
70
mA
= 0.4 VDC
V CCl = 5.5
Supply Current
(Note 2)
15
8
mA
VCCl
A.C.
PARAMETER
TYP.
MAX.
UNITS
Turn On Delay
50
75
ns
VCCl
Turn Off Delay
50
75
ns
VCC2
tR
Rise Time
40
65
ns
RL =33fl
tF
Fall Time
40
65
ns
CL = 620 pF
(2)
All strobes enabled.
Switching Time Definitions
, -_ _---,,..-_ _ _ 3 vae
'-----OVDC
0I!TPUT
VOL
'F
tR
2-5
IL
= -150mA
IL
=0
= 5.0 VDC
= 12 VDC
VCC3 = 5.0 VDC
tON
(1) One strobe enabled.
= 2.4 VDC
CONDITIONS TA
tOFF
NOTES
DC
DC
DC
= 5.5 VDe
VIN =2.4VDC
SYMBOL
I
VDC
VIN = 0.4 VDC
ICC2
= 5.5 VDC
= 4.5 VDe
4.85
(Note 1)
VCCl
VCCl
Output Voltage
VOL
= 2.4 VDC
= 0.4 VDC
= 25 0 C
Typica'· Characteristics
TYPICAL OUTPUT VOL TAGE vs.
TYPICAL OUTPUT VOLTAGE vs.
LOAD CURRENT AND NUMBER OF STROBES ENABLED
VCC3 SUPPLY VOLTAGE
6.0,-------,------,------.------,
TA = 250C
6,0
NUMBER OF STROBES
----+
VCC1" 5VOC
6.75
VCC2 - 12 VDC
VCC3= 5 VOC
5.5
TA - 250C
VCCI- 5VOC
VCC2-12VOC
ONE STROBE
5.25
::
~
>0
~
4.85
5 4.75
l:
0
>
5.01-----+
>
4.8
4.51-----j.,c.,~,c...-+----+---__I
4.75
40
60
80
100
120
160
140
180
200
4.25
4.5
4.75
IL inmA
TYPICAL OUTPUT VOL TAGE vs.
5.0
TA - 250<:
VCCI =5VOC
VCC2" 12VOC
Vcca- 5VOC
RL=33n
---
4.9
~
.E
4.8
100
0
&0
..,.,., ~
--- ----
"""
14, 7
20
+25
+40
+60
+75
VS.
'OFF
80
.E
40
-20
6.0
TA = 250C
VCCI -5VOC
VCC2 -12 VOC
Vcca= 5VDC
RL-33n
120
!
l:
-55.040
5.75
LOAD CAPACITANCE
::
~
5.5
TYPICAL DELAY tOFF AND tF
'AMBIENT TEMPERATURE
I
5,25
6.0
VeC3 in Volts
+100
o
200
+125
400
600
800
TA in DC
1000
-1200
tF
~
'400
1800
1800
CL in pF
TYPICAL DELAY vs.
TYPICAL DELAY tON AND tR vs.
AMBIENT TEMPERATURE
.LOAD CAPACITANCE
120
VCCI-5 VOC
VCC2- 12VDC
Vcca-5 VOC
RL=33n
CL -620pF
100
80
0
.E
0
20
100
,.,,~
~
.... ,
-- ---~
=-- --..:: ~
---
'OFF
TA-25oC
VCCI- 5VDC
VCC2-1i!VOC
Vcca=5VOC
RL=33n
120
!
80
;
,E
.... .. '
0
0
20
0
-55
tR
0
tF
-
--40
-20
+25
+40
+60
+76
+100
200
+125
400
800
800
1000
CL in pF
TA in DC
2-6
1200
1400
1800
1800
HARRIS
HM-76XX
SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION Of' HARRIS CORPORATION
GENERIC PROM FAMILY
JANUARY 1978
Features
Organizations
•
COMMON D.C. ELECTRICAL CHARACTERISTICS AND PROGRAMMING
PROCEDURE
•
SIMPLE, HIGH SPEED PROGRAMMING PROCEDURE, ONE PULSE/BIT
•
EXPANDABLE - "OPEN COLLECTOR" OR "THREE STATE" OUTPUTS
AND CHIP ENABLE INPUTS
•
•
•
PART
·OUTPUT
OC
HM-7610
HM-7611
OC
INPUTS AND OUTPUTS TTL COMPATIBLE
• LOW INPUT CURRENT - 250IJA LOGIC "0", 40/JA LOGIC "1"
• FULL OUTPUT DRIVE - 16 mA SINK, 2mA SOURCE
HM-7620
HM-7621
OC
HM-7640
HM-7641
OC
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING, OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES
HM-7642
HM-7643
HM-7644
OC
TS
TS
TS
TS
TS
BITS
256
32 x 8
1024
256)( 4
2048
512 x 4
4096
512 x 8
4096
1024 x 4
APU
• DC - Open Collector
• TS - ~Three State'"
• APU - Active Pull-Up
PIN COMPATIBLE WITH INDUSTRY STANDARD PROMs AND ROMs
Description
WORDS )(
BITS/WORD
TOTAL
NUMBER
HM-7602
HM-7603
The field programmable PROM can be custom programmed
to any pattern using a simple programming procedure.
Schottky Bipolar circuitry provides fast access time, and
features temperature and voltage compensation to minimize
access time variation.
The HM-76XX Generic PROMs comprise a completely
compatible family having common D.C. electrical characteristics and identical programming requirements. They
are fully decoded, high speed, field programmable ROMs
and are available in all commonly used organizations, with
both open-collector and "Three State" outputs. All bits are
manufactured storing a logical "1" (outputs high). and can
be selectively programmed for a logical "0" (outputs low).
All pinouts are compatible to industry standard PROMs and
ROMs.
In addition to the conventional storage array, extra test
rows and columns are included to assure high programmability, and guarantee parametric and A.C. performance.
Fuses in these test rows and columns are blown prior to
shipment.
The nichrome fuse technology is the same as is used in the
JAN approved MIL-STD-38510/201 PROM and in all
other Harris PROMs.
Block Diagrams
Pinouts
HM-7602/03
32x 8
.11111
A2UZI
- -
~
m
~
~
.,
00
PI
00
NI
~
~
~
~
~
TOP VIEW
0,
VCC
02
CS
03
A4
04
A3
05
A2
Os
A,
07
AO
GND
Os
HM-7610/11
256x4
"344,t,II".'
'4' 131 121 111 1111
2-7
TOP VIEW
AS
VCC
AS
A7
A4
CS2
A3
CS,
AO
0,
A,
02
A2
D3
GNO
04
E
HM-7620/21
512x4
_"""AlA-7M
II) III 1111'1)''''
MI
TOP VIEW
A6
VCC
A7
Ali
...,
A.4
Aa
A3
cs
AIm
AD
0,
l!illa
A,
02
A2
GNO
03
A,."
HM-7640/41
512.x 8
_""'" AI 11.7 AI
"M,m lit IU !aI
04
TOP VIEW
A7
A6
AS
·Vcc
AS
I.C.'
CS,
CS2
CS3
CS4
OS·
A4
A3
A2
A,
AO
0,·
02
03
GNO
"'111
AtIJl
... '"
5'f211
51'.
CQI'"
ca.1'"
.
""
I
lit'
or
,,-.
. . "...
..
II.'
,,~
,tn
·1....... ~ •......--... .... IIh ...........fc.
'"
01
HM-7642/43
1024 x4
.11.4 AlAI A 7 " ' ' '
111 m ''''tnt,l)ltel
°i
De
OS·
04
TOP VIEW
A6
VCC
A7
AS
.... '",
A,II'
Alf_'
01,111
82ft.
A4
AS
A3
A9
AD
0,
A,
02
A2
03
04
CS,
GNO
~
AI
AC"Al: AI
HM-7644
1024x4
At
CS2
TOP VIEW
131.111 lIIl'IfII1_ln:l1
As
A5
.....
..A,II''"
.....
2-8
Vcc
A7
A4
AS
A3
A9
.AO
0,
A,
02
A2
GNO
04
03
Specifications HM-76XX
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7 .OV
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
100mA
Storage Temperature
-65 0 C to +150 0 C
Operating Temperature (Ambient) -55 0 C to +1 250 C
Maximum Junction Temperature
+1750 C
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-76XX-5 (VCC = 5.0V ±5%, TA = ooC to +75 0 C)
HM-76XX-2, HM-76XX-8 (VCC = 5.0V ±10%, T A = -55 0 C to +125 0 C)
Typical Measurements are at T A = 25 0 C, VCC = +5V
SYMBOL
OPEN COLLECTOR THREE STATE
OUTPUT
OUTPUT
MIN
TYP MAX MIN TYP MAX
PARAMETER
IIH
ilL
Address/Enable
Input Current (1)
"1"
"0"
-
VIH
VIL
Input Threshold
Voltage
"1"
"0"
2.0
VOH
VOL
Output Voltage
"1"
"0"
N/A
10HE
10LE
Output Disabled
Current (2)
"1"
"0"
-
10H
Output Leakage (1) "1"
-
VCL
Input Clamp Voltage
-
Output Short Circuit
lOS
-
UNITS
-
0.8
V
V
3.4
0.35
0.45
V
V
-
100
-100
J.1.A
J.1.A
VOH, Vee - VCC Max.
VOL = +0.3V, VCC = VCC Max.
-
N/A
J.1.A
VOH, VCC
-
-1.2
V
-
-100
mA
-
90
90
105
130
mA
170
-
125
170
mA
140
-
100
140
mA
-
40
-50.0 -250
0.8
0.35
0.45
100
N/A
-
-
-
100
-1.2
-
N/A
-
N/A
-15
-
90
90
105
130
HM-764017641
-
125
HM-764217643/7644
-
100
2.4
J.1.A
J.1.A
-
2.0
-
ICC
NOTE: (11
(21
VIH
VIL
= VCC Max.
liN - -18mA
Current
Power Supply Current
HM-7602/7603
HM-7610/7611
HM-762017621
TEST CONDITIONS
= Vee Max.
= 0.45V
Vee = Vee Min.
Vee = Vee Max.
10H = -2.0mA, Vee - vee Min.
10L = +16mA, Vee = vee Min.
-
40
-50.0 -250
VOUT- O.OV
One Output On"ly for a Max. of 1 sec.
Vce = VCC Max.
All I nputs Grounded
Enable current measured using only one enable input to disable the device.
N/A for HM-7644, Active Pull-Up Output.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-76XX-2
HM-76XX-8
HM-76XX-5
SYMBOL
TAA
TEA
PARAMETER
VCC-5V±5%
TA - 00 to +75 0 C
TYPICAL
MAXIMUM
VCC - 5V± 10%
TA - -550 C to +1250 C
TYPICAL
MAXIMUM
UNITS
HM-7602/7603
30
20
40
30
30
20
50
40
ns
ns
TAA
TEA
HM-7610/7611
40
15
60
25
40
15
75
30
ns
ns
TAA
TEA
HM-7620/7621
45
15
70
25
45
15
85
30
ns
ns
TAA
TEA
HM-7640/7641
45
30
70
40
45
30
85
50
ns
ns
TAA
TEA
HM-7642/7643
HM-7644
45
15
60
25
45
15
85
30
ns
ns
T AA - Address to Output Access Time
TEA - Chip Enable Access Time (N/A HM-76441
A.C. Limits Guaranteed for Worst Case N2 Sequencing
2-9
I
CAPACITANCE: TA = 250 C
SYMBOL
MAXIMUM
UNITS
I nput Capacitance
12
pF
VCC
Output Capacitance
12
pF
VCC
PARAMETER
CINA, CINCS
COUT
TEST CONDITIONS
=5V, VIN = 2.0V, f = 1MHz
= 5V, VOUT = 2.0V, f = 1MHz
SWITCHING. TIME DEFINITIONS
,
,
~
ADDRESS ==¥..;,;,:.5..;V_ _ _,,-_:::
,
-4Ii___~VOH
~ilOL
OUTPUT _ _
-I
I
'
. ----r
i-';"'~--V'L
I
i
-I
I
:
I
I
t
I
lk
OUTPUTS
f---
TAA
,I V I . H
~
.... . 1.5V· ' . .,' 1.5V
,',
TEA
I
!
! >!-
i-
I
T.S.
~ TEA iI
I
'" tf < 5nI
A.C. TEST LOAD
Vee
PROM
OUTPUT
""-1-#;.=ro,"
":"
.
.. Incl,udn jig & probe
total capaCitance"
I
TYPICAL A.C. CHARACTERISTICS
ADDRESS TOOU1'PUT DELAY
VS. SUPPLY VOl. TAGE
ADDRESS TO OUTPUT DELAY
VS. TEMPERATURE
,I
70' Vee _ l5.ov
CL -3OpF
B.
I
D.c. Load· limA
HM-,.l..
HM-7842143
HM_7640141
HM·7620121
]60
C
;! ..
,
.HM-78101'c'··
3.
HM-76D2/03
oac
-66OC
,I
.SOC
...
,:moe
'D"C
4.76
•..
'.25
TtOCI
VcclVI
CHIP SELECT TO OUTPUT DELAY
VS. TEMPERATURE
CHIP SELECT TO OUTPUT DELAY
VS.SUPPLY VOLTAGE
B.'
"
HM-7B40/41
I,'
.HM-:7602I03
10.
o
HM-1620121
HM-76101n
HM-?642/43
Vee. S.OV
C,l:.3OpF
D.C. Load • 16mA
-"''-
,. f-----,--1-'--,,-'-:-:-+ ~=:~:~~1;4-_,_-~
TA - 250(:
,'0
D"C
2!iOC
7D"C
CL-3OpF ~
D.C. Load· 16mA
4.6
'","",
4.7$
. HM-7642/43
5.0
VCC(VI
TIOCI
2-10
6.25
5"
HARRIS
HM-76LS03
SEMICONDUCTOR
PRODUCTS DIVISION
32 X 8 PROM
"Three State" Outputs
A DIVISION OF HARRIS CORPORATION
MAY 1978
Preliminary
Pinout
Features
TOP VIEW-DIP
•
ULTRA LOW POWER - 60mW TYPICAL
•
SIMPLE I·IIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
TYPICAL, ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
•
01
Vcc
02
CE
03
A4
04
A3
05
A2
06
A1
07
AO
GND
Os
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
PIN COMPATIBLE WITH THE STANDARD 7603 PINOUT.
Description
The HM-76LS03 is an ultra low power version of the standard 7603 PROM,
designed to be MaS compatible with it's low ICC specification. The
HM-76LS03 is a fully decoded high speed Schottky TTL 256-Bit Field
Programmable ROM in a 32 word by 8 bit/word format with "Three State"
outputs. This PROM is' available in a 16 pin DIP (ceramic or epoxy).
logic Symbol
01
CE
All bits are manufactured storing a logical ''1'' (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrome fuse technology is used on this and all
PROMs.
03
other Harris Bipolar
The HM-·76LS03 contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametric
and A.C. performance. The fuses in these test rows and columns are blown
prior to shipment.
There is a Chip Enable on the HM-76LS03,
CE
02
AO
04
A1
05
A2
06
A3
07
A4
Os
PIN NAMES
Ao-A4
01-0S
low enables the device.
CE
Address Inputs
Data Outputs
Ch ip Enable Input
Functional Diagram
AO (101
At (111
A2 (121
A4 (t41 -
32x8
ADDRESS
BUFFERS
A3 (t31
MEMORY ARRAY
......_ _......
CE(t&1
(161 =VCC
(8) = GND
(91
08
(71
07
(6)
(6)
0&
05
(41
04
(3)
(21
(1)
03
02
01
E
Specifications HM-16lS03
ABSOLutE MAX~MVMRATINGS
Storage Temperature
-650 C to +1500 C
,Operating Temperature {Ambient)
OQG.to:+750 C
Maximum Junction Temperature
+1750 C
Output or Supply Voltage Ratings (Operating) -0.3 to +7 .OV
Address/Enable,! nput Voltage
+5.5V
Address/Enable Input Current
-20m A
Output Sink Current
100mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and functional operation of the device at these or at anI! other conditions above those Indicated in the operational sections of this
specification is not implied. (While programming, follow the programming specifications)
HM-76LS03-5 (VCC= 5.0V ± 5%, TA = ooC to +750 C)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
TYP
MAX
UNITS
-
-
+40
-50
uA
uA
VIH = VCC max
VIL = 0.45V
2.0
1.5
1.5
0.80
V,
V
VCC = Vccmin
VCC= VCCmax
3.4
0.34
0.45
MIN
IIH
IlL
Address/Enable
Input Current
"1"
"0"
-
VIH
VIL
Input Threshold
Voltage
"1"
"0"
-
VOH
VOL
Output
Voltage
"1"
"0"
Output Disable
Current
"1"
"0"
10HE
'IOLE
I
PARAMETER
VCL
Input Clamp Voltage
lOS
Output Short Circuit Current
ICC
Power Supply Current
2.4
-
-
-
-2
-
-
TEST CONDITIONS
V \ IOH=':0.20mA VCe ;. VCC min.
'V
10L=iil.OmA
VCC'" VCC min.
+100
-100
uA
uA
-1.2
V
-20
rnA
VOUT =' O.OV o"',e output only for a max
of one second .
25
mA
.vCC,= V~cmax all inputs grounded
1:?
VOH, VCC = VCC max
VOL =+0.3\1
VCC= VCC max
liN =-18m,A
Typical measurements are at TA = 25 0 C, VCC = +5V
NOTE: Positive current defined as into the device terminals.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM_76LS03-5
5V±5%
ODe to +75DC
SYMBOL
TAA
TEA
I
PARAMETER
I
MIN
I
-
,Addres~
Access Time
Ch ip Enable Access Time
-
'1-
TYP
1
MAX
UNITS
300
300
I
500
500
ns
ns
, A.C. liinits guaranteed for worst ca,se N,2 sequencing.
CAPACitANCE: TA = 250 C
~
"
;
1
SYMBOL
PARAMETER
MAX
I
CINA, CINCE
COUT
I nput' Capacitance
'OutputCapacitance;'i
12
12
·1
'I
UNIT
pF
pF
I
1
TEST CONDITIONS
vcc = 5V, VIN = 2.0, f,= lMHz
VCC = 5V, VOUT = 2.0, f = lMHz
SWITCHING TIME DEFINITIONS
I
I
ADDRESSES
*,.6V
I
I
I
CE
VIH
I
I
I
I
i
-,,
,,
I
I
I
I
I
I
VDH
*,.6V
OUTPUTS
VOL
I
I
I
I
TAA
I
-'
'-
I
I
I
TEA
!
1
I
I
I
1
1
I
I
1
k
i
I
I
VIH
*,.6V
*,.6V
VIL
I
OUTPUTS
I
1
I
I
0--
,
1
I
I
I
-I
,
I
I
TEA
I
A.C. TEST LOAD
Vee
6Kn
OXO---~------~-----O
TEST POINT
OUTPUT
PROM
'OKn
3OpF·
•
':' GND
2-13
V'L
1
Includes jig and proba
total capacitance
*.I
I
1
I
I
T.s.
m
HARRIS
SEMICONOUCTOR
PRODUCTS DIVISION
HM-7608
A DIVISION OF HARRIS CORPORATION
1K
APRIL 1978
X
8 PROM
Pinouts
Features
•
60ns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OUTPUTS WITH A CHIP ENABLE INPUT
•
SIMPLE, HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/
BIT. ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
AS
•
FAST ACCESS TIME - GUARANT.EED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
CE
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
•
PIN COMPATIBLE WITH THE 2708 WITH:
ONLY ONE 5 VOLT SUPPLY
TOP VIEW - DIP
Vce
N.I.C.*
N.I.C:
as
07
as
SUPERIOR ACCESS TIME
05
FASTER PROGRAMMING TIME
04
GND
Description
The HM-760B is a fully decoded high speed Schottky TTL B192-Bit
Field Programmable ROM in a 1 K word by B bit/word format and is
available in a 24 pin D.I.P. (ceramic or epoxy) and a 24 pin flat pack.
All bits are manufactured storing a logical "1" (Positive Logic) and can be
selectively programmed for a logical "0" in any bit position, the HM-760B
has "Three State" outputs.
Nichrome fuse technology is used on this and all other Harris Bipolar
PROM's.
The HM.:.760B contains test rows and columns which are in addition to the
storage array to assure high programmability and guarantee parametric
and A.C. performance. The fuses in these test rows and columns are
blown prior to shipment.
This PROM is a plug in replacement for the 270B where the VSS pin on
the 270B becomes GND on the HM-760B. The VBB, VDD, and program
pins on the 270B are all N.C. on the HM-760B.
TOP VIEW - FLATPACK
A7===:::;r r;====Vcc
A6
A5
AS
Ag
~
N.I.C:
N.I.C.*
0,
02
07
06
03
05
GND
04
Os
PIN NAMES
AO-Ag
01 -08
CE
There is a chip enable input on the HM-760B where CE low enables
the device.
Address Inputs
Data Outputs
Chip Enable Input
·No Internal Connect
Functional Diagram
logic Symbol
8192
MEMORY ARRA Y
NOTE: PHYSICAL BIT POSITIONS
FOR COLUMNS ARE AS fOLLOWS:
0,.03. as. 07_(0 __15)
02.04. 06. 08 --<15. 0 __14)
• • • • • • • • • • • • e.e.e ••
128 TRANSIMISSION GATES
(
)
(24)
(12)
(21)
(19)
(lS)
2-14
=:;
Pin Numbers
= VCC
= GND
=
N.1.C.
= N.I.C.
= N.1.C.
•
NJ~
CE
A3
A2
A,
AO
CE
AO
Al
A2
A3
A4
A5
A6
A7
AS
A9
°1
°2
03
°4
°5
06
°7
Os
Specifications HM-7608
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to +150o C
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
+175 0 C
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may CaUse permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
PARAMETER
HM-7608-5 (VCC = 5.0V ±5%, T A = ooC to +750 C)
HM-7608-2 (VCC = 5.0V ±10%, TA = -55 0 C to +125 0 C)
Typical measurements are at T A = 250 C, VCC = +5V
MIN
TYP
MAX
IiH
IiL
Address/enable
I nput Current
"1"
"0"
-
-50.0
+40
-100
JlA
JlA
VIH = VCC Max.
Vil = 0.45V
VIH
Vil
Input Threshold
Voltage
"I"
2.0
-
1.5
1.5
-
"0"
0.8
V
V
VCC = VCC Min.
VCC = VCC Max.
VOH
VOL
Output
Voltage
"I"
2.4
"0"
3.2
0.35
0.45
V
V
10H = -2.0mA, Vec = VCC Min.
10l = +16mA, VCC = Vec Min,
10HE
10lE
Output Disable
Current
-
-
+40
-40
JlA
JlA
-
-1.2
V
-15
-100
mA
VOUT= O.OV
One Output Only for a Max.
of 1 Second
-
130
170
mA
VCC = VCC Max, All Inputs
Grounded
"I"
"0"
Vel
Input Clamp Voltage
lOS
Output S.C. Current
ICC
Power Supply Current
UNITS
-
-
TEST CONDITIONS
VOH, VCC = VCC Max,
VOL = 0,3V, VCC = VCC Max.
liN - -18mA
NOTE: Positive current defined as into device terminals.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7608-5
5V±5%
OOC to + 750C
SYMBOL
PARAMETER
HM-7608-2
5V ±10%
-55 0 C to + 1250 C
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TAA
Address Access Time
-
45
60
-
-
80
ns
TEA
Chip Enable Access Time
-
30
40
-
-
50
ns
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
CINA,CINCE
COUT
PARAMETER
MAXIMUM
UNITS
I nput Capacitance
8
pF
VCC = 5V, VIN = 2.0V, f
Output Capacitance
10
pF
VCC
?-Hi
TEST CONDITIONS
= lMHz
= 5V, VOUT = 2.0V, f = lMHz
I
SWITCHING TIME DEFINITIONS
ADDRESSES
------'r--:::--:--------VIH
--:i~ 1.5V
-----'"
OUTPUTS
CEl-,-_----,.
CHIP ENABLE
F ",
------t---,
TAA
1.5V
/----VOH
15V
OUTPUTS----t--i<======t===:>
A.C. TEST LOAD
PROM
OUTPUT
Lr----VIH
+,-----"'+------- VIL
VIL
Ox 0 - - -.....- .....- 0 TEST POINT
3OpF*
*
Includes Jig
and Probe Total
Capacitance
T.S.
m
HM-7610A/11A
HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
256 x 4 PROM
A DIVISION OF HARRIS CORPORATION
HM-7610A - Open Collector Outputs
HM-7611A - "Three State" Outputs
DECEMBER 1977
Features
Pinouts
•
40ns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS
•
SIMPLE, HIGH SPEED PROGRAMMING PROCEDURE USING SINGLE
PULSES, ASSURES FAST PROGRAMMING AND SUPERIOR
RELIABILITY
•
INPUTS AND OUTPUTS TTL COMPATIBLE
•
FAST ACCESS TIME - GUARANTEED FOR WORST CAST N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
TOP VIEW-DIP
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
•
PIN COMPATIBLE WITH INDUSTRY STANDARD PROM's AND ROM's
Description
The HM-7610A/11A are fully decoded high speed Schottky TTL 1024Bit Field Programmable ROMs in a 256 word by 4 bit/word format with
open collector (HM-7610A) or "three state" (HM-7611A) outputs.
These PROMs are available in 16 pin D.I.P. (ceramic or epoxy) and a
16 pin flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
The HM-7610A/11A contain test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
This PROM is intended for use in state of the art ultra high speed logic
systems.
Nichrome fuse technology is used on these and all other Harris Bipolar
PROM's.
A5
12}
A&
(1}
A7
(l5}
vee- 11&}
GND- IS}
ONE OF 1&
ROW
16x64
MEMORY
DECODER
ARRAY
AD 151------------r---,-r--il-f-:-::-=l-Ir-::-:-:-1
A2(7}
fe,
';I;&}~===~
;A3141
(13)---1'.----..
CE2 (141
~==~------~~--VCC
A7
£§2
g;,
°2
----~------~---g!
PIN NAMES
AO - A 7 Address Inputs
0, - 04 Data Outputs
CE" CE2 Chip Enable Inputs
logic Symbol
Functional Diagram
A4
13}
TOP VIEW-FLAT PACK
+--..,
}---~_l'----<._I---......
19}
04
110}
03
111}
02
f12}
0,
2-17
IE
Specifications HM-1610AIIIA
ABSOLUTE MAXIMUM RATINGS
-65 0 C to +15DoC
Storage Temperature
Operating Temperature (Ambient) -55 0 C to +1250 C
+1750C
Maximum Junction Temperature
Output or Supply Voltage (Operating) -0.3 to+7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and .functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
~
"
,j
O.C. ELECtRICAL
c\. fARACiEAISiICS
(Operating) HM-7610A/11A-5 (VCC; 5.0V ±S%, TA; DOC to +750C)
HM-761DA/11A-2 (VCC; 5.0V ±10%, TA; -550C to+1250C)
Typical measurements are at T A; 25 0 C, VCC; +5V
SYMBOL
I
MIN
TYP
MAX
UNITS
IIH
IlL
Address/Enable
Input Current
PARAMETER
"1"
"0"
-
-
+40
-250
MA
MA
VIH = VCC Max.
VIL= 0.45V
VIH
VIL
Input Threshold
Voltage
"1"
"0"
2.0
-
V
V
VCC = VCC Min.
VCC = VCC Max.
VOH
VOL
Output
Voltage
"1"
"0"
2.4*
V
V
IOH = -2.0mA, VCC = VCC Min.
IOl = +16mA, VCC = VCC Min.·.
IOHE
IOLE
Output Disable
Current
"1"
"0"
-50.0
1.5
1.5
0.8
3.2*
0.35
0.45
-
-
TEST CONDITIONS
VCl
Input Clamp Voltage
-
-
-1.2
V
lOS
OutpUt S.C. Current *
-15*
-
-100*
mA
VOUT = O.OV
One Output Only for a Max.
of 1 Second
ICC
Power Supply Current
-
-
130
mA
VCC = VCC Max. All Inputs
Grounded
-
+40
-40*
-
VOH, VCC = VCC Max.
VOL = 0.3V, VC"': = VCC Max.
JlA
JlA
liN =-18mA
Not applicable to open collector.
NOTE: Positive current defined as into device terminals.
oJ!
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7610Al11A-5
5V±5%
ooc to + 750C
SYMBOL
PARAMETER
HM-761()A/11A-2
5V ±10%
-550C to + 1250C
MIN
TYP
MAX
MIN
-
40
25
TAA
Address Access Time
-
TEA
Chip Enable Access Time
-
TYP
MAX
UNITS
-
-
60
ns
-
-
40
ns
A.C, limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A; 250C
SYMBOL
CINA, CINCE
COUT
PARAMETER
Input Capacitance
Output Capacitance
MAXIMUM
UNITS
TEST CONDITIONS
B
pF
VCC = 5V, VIN = 2.0V, f = lMHz
10
pF
VCC = 5V,VOUT = 2.0V, f = lMHz
2-18
SWITCHING TIME DEFINITIONS
,
ADDRESS
_____J,
VIH
*1.5V
o
TAA
,
,
~
OUTPUT_ _ _ _ _ _-+-__--'*1.5V
,
"----VIH
1.5V
-------:-~-----../ :---------VIL
,
"
OUTPUT----lr-----~~-"",-o TEST POINT
3OpF*
-Includes Jig
and Probe Total
Capacitance
2-28
'f.s.
HM-7625R
HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
256 x 8 PROM
"Three State" Outputs
MAY 1978
Features
Pinout
TOP VIEW - DIP
•
60ns MAXIMUM ADDRESS ACCESS TIME.
•
"THREE STATE" OUTPUTS WITH TWO CHIP ENABLE INPUTS.
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE-ONE PULSE/BIT TYPICAL.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
FAST ACCESS'TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING
OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE
RANGES.
•
IN~USTRY'S
HIGHEST PROGRAMMING YIELD.
Description
PIN NAMES
Address Inputs
01 - Os Data Outputs
CE1', CE2 Chip Enable Inputs
STR Strobe Input
AO - A7
The HM-7625R is a fully decoded high speed Schottky TTL 2048-Bit
Field Programmable ROM in a 256 word by 8 bit/word format and is
available in a 24 pin DIP (ceramic or epoxy).
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
logic Symbol
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
I
The HM-7625R contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametric
and A.C. performance. The fuses in these test rows and columns are
blown prior to shipment.
There are two chip enables on the HM-7625R. CEl low and CE2 high
enables the chip.
Functional Diagram
(241 -
vcc
(121' GND
(3), (11), (12)- NC
32)(64
MEMORY
ARRAY
;g~~~~ 1 - - - - - -....
BUFFERS
Os
2-29
06
o.
Specifications HM-7625R
ABSOLUTE MAXIMUM RATINGS
Output brSupply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
Address/Enable Input Current
-20mA
Output Sink Current
100mA
Storage Temperature
-65 0 C to +150 0 C
Operating Temperature (Ambient) -55 0 e to +125 0 e
Maximum Junction Temperature
+175 0 C
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanentqamage to the device., This is a
stress, only rating and functional operation of the device at these or at any' other conditions above those indicated in the operational
sectionsof ~his specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
I
HM-7625R75 (Vec = 5.0V ± 5%, TA = ooC to +75 0 C)
HM-7625R-2 (Vec = 5.0V ± 10%, TA = -55 0 C to +125 0 C)
Typical measurements are at TA = 25 0 e, Vee = +5V
SYMBOL
PARAMETER
MIN
TYP
IIH
III
Address/Enable "1"
Inpl!t Current
"0"
-
-
-50.0
VIH
Vil
Input Threshold "1"
Voltage
"0"
2.0
-
1.5
1.5
VOH
VOL
Output
Voltage
"1"
"0"
2.7(2)
-
10HE
IOlE
Output Disable
"1"
"0"
Current
MAX
UNITS
TEST CONDITIONS
I1A
I1A
VIH = VCC Max.
Vil = 0.45V
0.85
V
V
VCC = VCC Min.
VCC = VCC Max.
3.3
0.35
0.50
V
V
IOH = -2.0mA, VCC = VCC Min.
IOl = +16mA, Vce =VCC Min.
-
+40
-40
I1A
I1A
-
+25
-100(1)
-
VOH, VCC = VCC Max.
VOl= 0.3V, VCC = VCC Max.
VCl
Input Clamp Voltage
-
-
-1.2
V
lOS
Output Short Circuit
Current
-20
-
-70
mA
VOUT = O.OV, One OUtput at a
Time for a Max. of 1 Second
ICC
Power Supply Current
-
135
185
mA
VCC= VCC Max., All Inputs
Grounded.
liN = "18mA
NOTE: Positive current defined as into device terminals.
NOTE(1): III = -150I1A for-2
NOTE(2): VOH = 2.4V for-2
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7625R-2
5V±10%
-55OC to + 1250C
HM-7625R-5
5V±5%
OOC to +750 C
SYMBOL
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TAA
TEA
Address Access Time
Chip Enable Access Time
-
40
30
60
40
50
40
80
50
ns
ns
latched or
Transparent
TADH
TCDH
TSW
TSl
TDl
TCDS
Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe latch Time
Strobe Delatch Time
Chip Enable Set-Up Time
0
10
30
60
-10
-
-10
-
-
-
-
ns
ns
ns
ns
ns
ns
latched Only
a
a
40
15
35
40
-
-
a
10
40
80
50
15
45
-
50
-
TEST CONDIT.
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE (1): TA = 250 C
SYMBOL
CINA,CINCE
COUT
PARAMETER
Input Capacitc,nce
Output Capacitance
MAXIMUM
UNITS
8
pF
VCC = 5V, VIN
10
pF
VCC = 5V, VOUT
2-30
TEST CONDITIONS
= 2.0V, f = 1MHz
= 2.0V, f = 1MHz
SWITCHING TIME DEFINITIONS {Transparent Model
ADDRESSES _ _ _ _J
OUTPUTS
TAA
CE1
VIH
"' ~1.5V
~V
VIL
CE2
VOH
OUTPUTS
;----VIH
'----VIL
T.S.
VOL
NOTE: Strobe input must remain high throughout read cycle while in the transparent mode.
SWITCHING TIME DEFINITIONS {Latched Model
ADDRESS
----*,.'"
CE1
CHIP ENAB;;2
I
II
r-- TC", - - 1..
1...._
Ir--
~ 1.5V
t
5-V
1-.
STROBE-----+----
I·
OUTPUT
T ADH
~'-1_.5_V
________
...-:-::::-:------- VIH
I
¥I !.5V
1 Ir-
~1.5V
1.5V
.1
TSL
>
A.C. TEST LOAD
VCC
-_--0
Ox 0 - - -.....
TEST POINT
30pF*
*Includes Jig
and Probe Total
Capacitance
2-31
VIH
~ VIL
TDL
~TAA==~1.5V
PROM
OUTPUT
VIL
TSW--'·.,,,,--- TCDH---..+·-TCD---j
;L
:II~
T.S.
E
HM-7629
HARRIS
SEMICONOUCTOR
PRODUCTS DIVISION
256 x 8 PROM
A DIVISION OF HARAIS CORPORATION
"Three State" Outputs
MAY 1978
Features
Pinout
TOP VIEW - DIP
•
70n5 MAXIMUM ADDRESS ACCESS TIME.
•
"THR EE STATE" OUTPUTS WITH FOUR CHIP ENAB LE INPUTS.
(1)
I.C. (2)
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
TYPICAL.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
eE,
Vcc
•
•
CE2
CE3
CE4
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
.
,
Os
07
06
05
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
PIN NAMES
Description
The HM-7629 is a fully decoded high speed Schottky TTL 2048-Bit
Field Programmable ROM in a 256 word by 8 bit/word format and is
available in a 24 pin DIP (ceramic or epoxy).
GND
'-----'
04
AO - A 7 Address Inputs
01 - Os Data Outputs
CE1, CE2, CE3, CE4 Chip Enable Inputs
(1) Pin 23 must be tied to VCC except
during programming
(2) Internal Connection
logic Symbol
All bits are manufactured storing a logical "1" (positive logic) and cim
be selectively programmed for a logical "0" in any bit position,
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
The HM-7629 contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown pripr to shipment.
There are four chip enables on the HM-7629. CEl low, CE210w, CE3
high, and CE4 high enables the chip.
Functional Diagram
(24) = VCC
(12) = GND
(22) = I.C. = Internal connection, recommended
to be left open circuited
(23) = Must be tied to VCC except during
A3 A4 A5 A6 A7 AS
(51 (41 (31 (21 (11 {231
programming
AO(SI-f------1_-.fL~~l_~~~~~~~l_fL~~1_--------------~~;;~fL~~1H~~~,,~~~
A,m
M(61
EE,
(211
CE2 (201
eE3 (191
CE4 (18)
(171
Os
1161
07
(151
06
(141
05
2-32
(131
(111
04
03
(101
02
(91
0,
Specifications HM-7629
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to +150 0 C
Operating Temperature (Ambient)
ooC to +75C
Maximum Junction Temperature
+1750C
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable I nput Voltage
5.5V
Address/Enable Input Current
-20m A
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7629-5 (Vce = 5.0V + 5%, T A = ooe to +75 0 e)
Typical measurements are at T A = 25 0 e, Vee = +5V
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
IlL
Address/Enable" "1"
"0"
I nput Current
-
-50.0
+40
-250
J.1A
J.1A
VIH
VIL
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
1.5
1.5
0.80
V
V
Vee
Vee
VOH
VOL
Output
Voltage
"1"
"0"
2.4
3.4
0.35
0.45
V
V
IOH
IOL
IOHE
IOLE
Output Disable
Current
"1"
"0"
-
+100
-100
J.1A
J.1A
-
-
-
TEST CONDITIONS
~
~
~
Vee Max.
0.45V
Vee Min.
Max.
= Vee
= -2.0mA,
~
Vee = vee Min.
+16mA, Vee = Vee Min.
VOH, Vee ~ vee Max.
VOL = 0.3V, Vee ~ Vee Max.
= -18mA
VeL
Input Clamp Voltage
-
-
-1.2
V
lOS
Output Short Circuit
Current
-15
-
-100
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
ICC
Power Supply Current
-
125
170
mA
vee = Vee Max., All Inputs
Grounded.
liN
NOTE: Positive current defined as into device terminals.
* Enable current measured using only one enable input at
a time to disable the device.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7629-5
SV±S%
OOC to +75 0 C
MIN
TYP
TAA
Address Access Time
PARAMETER
-
45
70
ns
TEA
Chip Enable Access Time
-
30
40
ns
SYMBOL
MAX
UNITS
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A
SYMBOL
elNA, elNeE
eOUT
~
25 0 C
MAXIMUM
UNITS
Input Capacitance
12
pF
Vee
= 5V,
VIN
Output Capacitance
12
pF
Vee
= 5V,
VOUT
PARAMETER
2-33
TEST CONDITIONS
~
2.0V, f
~
= 2.0V, f
1 MHz
~
1 MHz
E
SWITCHING TIME DEFINITIONS
ADDRESSES
OUTPUTS
,
CE, & CE2
,
-----'
V
=:Y.E'.5V
~IH
CE3 & CE4
: ----- :
I
VIL
I
i
I
I
~~'.:...5_V_ _ _ _ _ ~::
i ~VOH
---41---!
' :
,
I
TAA
r
--l
I--
,I
I
I
A.C. TEST LOAD
Vcc
PROM
OUTPUT
Ox 0-----4>---_-0 TEST POINT
GOOn
30pF*
* Includes Jig
and Probe Total
Capacitance
2-34
---+!--'-. .~
I
OUTPUTS----t!---tek
VOL
-I
,
TEA ' - '
'I
I
-i
I
I
I
TEA
f--
'I
I
T.S.
HM-7640A/41A
HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
512 x 8 PROM
A DIVISION OF HARRIS CORPORATION
HM-7640A - Open Collector Outputs
HM-7641A - "Three State" Outputs
APRIL 1978
Features
Pinouts
•
SOns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND FOUR CHIPS
ENABLE INPUTS.
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEOUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
•
LOW INPUT LOADING
TOP VIEW - DIP
A7
vcc
AS
AS
A4
A3
A2
A,
AS
NC
S
Ao
Descnption
The dM-7640A/41A are fully decoded high speed Schottky TTL 4096Bit Field Programmable ROMs in a 512 word by 8 bit/word format and
ar, ~vailable in a 24 pin DIP (ceramic or epoxy) and a 24 pin flatpack.
GND
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
TOP VIEW - FLATPACK
A7~~~~~ll[J~~~~VCC
NC
Nichrome fuse technology is used on this and all other Harris Bipolar
PROM's.
The HM-7640A/41A contain test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
AS
AS
AS
A4
A3
eEl
eE2
A2
A,
CE3
CE4
0,
AO
Os
03
C5
07
02~~~~~I1b;~~~~0604
There are four chip enable inputs on the HM-7640A/41 A where CE1,
and CE2 low and CE3 and CE4 high enables the chip.
GND
Functional Diagram
PIN NAMES
Ao - AS Address Inputs
01 - Os Data Outputs
CE1, CE2, CE3, CE4 Chip Enable Inputs
64,64
MEMORY
ARRAY
logic Symbol
eE,
eE2
CE, (21)
CE2 (20)
CE3(19)
CE3
CE41181
CE4
I)" PIN NUMBERS
AO
(24)" Vee
(12)- GND
(22)- NC
A2
A,
I.)
0,
(101
0,
(13)
(14)
(15)
(16)
04
05
06
0,
(111
08
A3
A4
A5
A7
A6
AS
2-35
,r----""1
I
Specifications HM-7640A141A
ABSOLUTE MAXIMUM RATINGS
OUtput or Supply Voltage (Operating)
Address/Enable Input Voltage
Address/Enable Input Current
Output Sink Current
~0.3
Storage Temperature
-65 0 C to +150 0 C
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
to +7.0V
5.5V
-20mA
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at an'y other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
I
HM-7640A/41A-5 (VCC = 5.0V± 5%,TA = OoC to +75 0 C)
HM-7640A/41A-2 (VCC = 5.0V ± 10%, T A = -550C to +125 0 C)
Typical measurements are at T A = 25 0 C, VCC = +5V
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
IlL
Address/Enable "1"
"0"
Input Current
-
-50.0
+40
-250
JlA
JlA
VIH = VCC Max.
VIL=0.45V
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
1.5
1.5
0.8
V
V
VCC = VCC Min.
VCC = VCC Max.
VOH
VOL.
Output
Voltage
2.4*
3.2*
0.35
0.45
V
V
10H = -2.0mA, VCC = Vec Min.
10L = +16mA, VCC = VCC Min.
10HE
10LE
Output Disable "1"
Current
"0"
+40
-40*
JlA
JlA
-
"1"
"0"
-
-
-
-
-
VCL
Input Clamp Voltage
-
lOS
Output Short Circuit
Current
-15*
ICC
POlNer Supply Current
-
.-
TEST CONDITIONS
VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
-1.2
V
-100*
mA
VOUT = O.OV, One Output at a
Time lor a Max. 01 1 Second
170
mA
VCC = VCC Max., All Inputs
Grounded.
125
liN = -18mA
NOTE: Positive current def.ined as into device terminals.
*"Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7640A/41A
5V±5%
ooc to+750C
PARAMETER
SYMBOL
HM-7640A/41A
5V ±10%
-550 C to + 1250 C
MIN
TYP
TAA
Address Access Time
-
35
MAX
50
TEA
Chip Enable Access Time
-
30
40
MIN
TYP
MAX
UNITS
-
-
70
ns
50
ns
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
CINA, CINCE
COUT
PARAMETER
Input Capacitance
Output Capacitance
MAXIMUM
UNITS
8
pF
VCC = 5V, VIN
10
pF
VCC = 5V, VQUT
2-36
TEST CONDITIONS
= 2.0V. I
~
= lMHz
2.0V, I = lMHz
SWITCHING TIME DEFINITIONS
~
VIH
ADDRESSES ~1.6V
, - - - - - - - VIL
,,
I
==*_1~.5_V_ _ _~~
i
I
I
I
---+,---,~
- I, TAA I-,,
,
OUTPUTS
~
CE, • CE2
CHIP ENABLES
CE3.CE4:
I
: ,
I
I
I
I
! k,.----I!f----i.-
OUTPUTS
--l
I
TEA
I
V
IH
VIL
T.S.
I- --i TEA lI
I
I
I
I
I
A.C. TEST LOAD
Vee
PROM
OUTPUT
Ox 0----<....-
soon
...- 0 TEST POINT
3OpF*
• Include. jig & probe
total capacitance
I
2~37
m
HARRIS
HM-7640AR/41AR
SEMICONDUCTOR
PRODUCTS DIVISION
512 x 8 PROM
A DIVISION OF HARRIS CORPORATION
APR/L 1978
HM-7640AR - Open Collector Outputs
HM-7641AR - "Three State" Outputs
Pinouts
Features
•
50ns MAXIMUM ADDRESS ACCESS TIME.
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS WITH THREE CHIP
ENABLE INPUTS.
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOL TAGE RANGES.
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
•
LATCHED OUTPUTS.
•
LOW INPUT LOADING.
Description
The HM-7640AR/41 AR are fully decoded high speed Schottky TTL 4096
Bit Field Programmable ROMs ina 512 word by 8 bit/word format and are
available in a 24-pin DIP (ceramic or epoxy) and a 24-pin flat pack.
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
TOP VIEW - DIP
A7
VCC
AS
A5
A4
A3
A2
AS
GE,
A,
STR
AO
0,
Os
NC
GE2
CE3
07
Os
02
03
05
04
GND
TOP VIEW - FLATPACK
Nichrome fuse technology is used on this and all other Harris. Bipolar
PROMs.
I
The HM-7640AR/41AR contain test rows and columns which are in addition to the storage array to assure high programmability and guarantee
parametrics and A.C. performance. The fuses in these test rows and
columns are blown prior to shipment.
There are three chip enable inputs on the HM-7640AR/41AR, CE1, CE2
low and CE3 high enables the chip.
HM-7640AR/41 AR are operated in the Transparent Read Mode by holding the strobe input high throughout the read operation. This is the normal read mode where the three chip enable inputs will control the outputs.
In Latched Read Mode, bringing the strobe input low will latch the outputs and chip enable inputs. If the device is disabled, when the strobe
input goes low the outputs will be latched in the high impedance state. If
the device is in the latched mode the strobe input must be brought high to
allow the outputs to respond to new address or chip enable conditions.
Functional Diagram
PIN NAMES
AO - AS
01 - Os
GEl, GE2, CE3
STR
Address Inputs
Data Outputs
Chip Enable Inputs
Latch Input
Logic Symbol
Specifications-7640ARl41AR
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-650C to +150 o e
Operating Temperature (Ambient) -55 0 e to +125 0 e
Maximum Junction Temperature
+175 0 e
Output or Supply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
-20m A
Address/Enable Input Current
100mA
Output Sink Current
CAUTION:
Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device.
These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7640AR/41AR-5 (Vee = 5.0V± 5%, TA = ooe to +750 e)
HM-7640AR/41AR-2 (Vee =5.0V± 10%, TA =-550 e to +1250 e)
Typical measurements are at T A = 250 e, Vee = +5V
SYMBOL
PARAMETER
MIN
TYP
MAX
IIH
IlL
Address/Enable "1"
Input Current
"0"
-
-50.0
+40
-250
!J.A
!J.A
VIH = VCC Max.
VIL=0.45V
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
-
1.5
1.5
0.8
V
V
VCC = VCC Min.
VCC = VCC Max.
VOH
VOL
Output
Voltage
2.4*
3.2*
0.35
0.45
V
V
IOH = -2.0mA, VCC = VCC Min.
IOL = +16mA, VCC = VCC Min.
10HE
10lE
Output Disable "1"
Current
"0"
+40
-40'
!J.A
!J.A
"1"
"0"
-
UNITS
-
TEST CONDITIONS
VCl
Input Clamp Voltage
-
-
-1.2
V
las
Output Short Ci rcuit
-15*
-
-100*
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
-
-
180
mA
V,CC = VCC Max., All Inputs
Grounded.
-
liN = -1amA
Current
ICC
Power Supply Current
VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
NOTE: Positive current defined as into device terminals.
*"Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7640AR/41AR-S
5V±S%
ooc to+7S OC
HM-7640AR/41AR-2
SV.±10%
-ssoc to +12So C
MIN
TYP
SYMBOL
PARAMETER
MIN
TAA
TEA
Address Access Time
Chip Enable Access Time
-
35
30
50
40
-
TADH
TCDH
TSW
TSL
TDL
TCDS
Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Time
Strobe Delatch Time
Chip Enable Set-Up Time
0
10
30
60
-10
0
15
35
-
-
-
40
TYP
MAX
40
-
MAX
UNITS
TEST CONDIT.
-
70
50
ns
ns
Latched or
Transparent
0
10
40
80
-10
0
1S
45
-
Latched Only
50
-
ns
ns
ns
ns
ns
ns
-
-
-
SO
-
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 e
SYMBOL
CINA, CINCE
COUT
MAXIMUM
UNITS
I nput Capacitance
a
pF
VCC = 5V, VIN = 2.0V, f = lMHz
Output Capacitance
10
pF
VCC = 5V, VOUT = 2.0V, f = 1MHz
PARAMETER
2-39
TEST CONDITIONS
I
SWITCHING TIME DEFINITIONS (Transparent Mode)
CE1.CE2
ADDRESSES
OUTPUTS
VIH
---_./
-i ~1.5V
CHIP ENABLES
VIL
-----------+------/
TAA
VOH
I~V
VIH
1.5V
VIL
CE3
OUTPUTS
T.S.
VOL
TEA
-
- , TEA
NOTE: Strobe input must remain high throughout read cycle while in transparent mode.
SWITCHING TIME DEFINITIONS (Latched Mode)
ADDRESSES
:J
j
\.1.5V
TADH-
f--TCDS
CE1.CE2
CHIP ENABLES
CE3
1.5V~~
..,~1.5V
TCD--
TCDH
r-TSW
STROBE
K1.5V
1.5V;o ~ ",,1.5V
1.5V
-
TSL
I
TDL
"
1.5V
OUTPUTS
r
TAA
A.C. TEST LOAD
VCC
I>ROIIII 0
TEST POINT
OUTPUT
X 0 - -.....----<_-0
3OpF*
600n
*
Includes Jig and probe
Total Capacitance
.......
1.5
T.S.
m
HM-7642A/43A
HARR1S
SEMICONDUCTOR
PRODUCTS DIVISION
1K
X
4 PROM
A alVISION OF HARRIS CORPORATION
HM-7642A - Open Collector Outputs
HM-7643A - "Three State" Outputs
MARCH 1918
Features
•
•
•
•
•
Pinout
50ns MAXIMUM ADDRESS ACCESS TIME.
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND TWO CHIP
ENABLE INPUTS
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
TOP VIEW-DIP
A6
Description
The HM-7642A/43A are fully decoded high speed Schottky TTL 4096Bit Field Programmable ROMs in a 1 K words by 4 Bit/word format with
open collector(HM-7642A) or "Three State" (HM-7643A) outputs. These
PROM's are available in an l8-pin DIP (ceramic or epoxy) and an '8-pin
flat pack.
VCC
A5
A7
A4
AS
Aa
Ag
Ao
01
Al
02
A2
03
CEl
04
GND
CE2
All bits are manufactured storing a logical "'" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
TOP VIEW-FLAT PACK
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
The HM-7642A/43A contains test rows and columns which are in addition to the storage array to assure high programmability and guarantee
parametries and A.C. performance. The fuses in these test rows and
columns are blown prior to shipment.
There are two chip enable inputs on the HM-7642A/43A. CE, and CE2
low enables the chip.
A6
vee
A5
A7
AS
Ag
A4
A3
AO
01
AI
02
A2
03
eel
04
GNO
CE2
Functional Diagram
PIN NAMES
AO-Ag
01 -04
GEl, CE2
Logic Symbol
4096 BIT
MEMORY ARRAY
NOTE: Physical bit
positions for columns
are as follows:
°
2 , 04 ~ (0 - 1 5 )
A3
84 TRANSMISSION GATES
01, 03
~
(15, 0 - 1 4 )
A2
() ~ PIN NUMBERS
(18) = Vee
(9) = GND
AI
AO
eel
eE2
(S)
(10)
ADDRESS INPUTS
DATA OUTPUTS
CHIP ENABLE INPUTS
CHIP
ENABLE
LOGIC
2-41
I
Specifications HM-7642A143A
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to +150 0 C
Operating Temperature (Ambient) -55 0 C to +125 0 C
+175 0 C
Maximum Junction Temperature
Output or Supply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
Address/Enable Input Current
-20m A
100mA
Output Sink C\Jrrent
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the dev/ce at these',or at· any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICALCHARACTERISTICS (Operating)
I
HM-7642A/43A-5 VCC =5.0V ±5%, TA = ooC to +75 0 C)
HM-7642A143A-2 VCC = 5.0V ±1 0%, T A = -55 0 C to +125 0 C)
Typical Measurements are at T A = 25 0 C, Vce = +5V
TEST CONDITIONS
:;YMBOL
PARAMETER
MIN
TYP
MAX
UNITS
liH
IlL
Address/Enable "1"
"0"
I nput Current
-
-50.0
+40
-250
J1A
J1A
VIH = VCC Max.
VIL = 0.45V
VIH
VIL
Input Threshold "1"
"0"
Voltage
2.0
1.5
1.5
0.8
V
V
VCC = VCC Min.
VCC = VCC Max.
VOH
VOL
Output
Voltage
3.2*
0.35
0.45
V
V
10H = -2.0mA, VCC = VCC Min.
10L = +16mA, VCC = VCC Min.
10HE
10LE
Current
-
"1"
"0"
2.4*
-
VCL
Input Clamp Voltage
-
-
-1.2
V
lOS
OutPUt Short Circuit
-15*
-
-100*
mA
VOUT =
One Output at a
Time for a Max. of 1 Second
-
100
140
mA
VCC = VCC Max., All Inputs
Grounded.
Output Disable "1"
"0"
-
+40
-40*
VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
J1A
J1A
liN = -18mA
o.av,
Current
ICC
Power Supply Current
NOTE: Positive current defined as into device terminals.
*"Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7642A143A
5V:!:5%
OOC to +75 0C
SYMBOL
PAF!AMETER
HM-7642A/43A
5V ±10%
-550C to +125 0 C
MIN
TYP
MIN
TYP
TAA
Address Access Time
-
35
MAX
50
-
-
MAX
70
UNITS
ns
TEA
Chip Enable Access Time
-
25
30
-
-
40
ns
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
CINA, CINCE
COUT
MAXIMUM
UNITS
Input Capacitance
PARAMETER
8
pF
VCC = 5V, VIN= 2.0V, f
Output Capacitance
10
pF
VCC = 5V, VOUT = 2.0V, f = 1 MHz
2-42
TEST CONDITIONS
= 1MHz
SWITCHING TIME DEFINITIONS
VIH.
I
ADDRESSES ~1.5V
r----VIH
: ' -_________
, -------VIL
,
I
I
-I
I
I
:
i
I
I
,
I
i >t-
, ,..---+!--"' '
OUTPUTS---~!t_-~K
I
I '-----+,-- I
I
TAA
i
I
,
VOL
I
:
I
I '
I
~VOH
OUTPUTS_ _-III-___~
J~
I--
--I TEA I -
I
I
I
I
I
I
--I
I
I
TEA
T.S.
I-I
I
A.C. TEST LOAD
Vee
PROM
OUTPUT Ox 0 - - -...-
600n
....._-0 TEST POINT
3OpF*
.. Includes jig & probe
total capacitance
E
2-43
mi
.
HM-7642P/43P
SEMICONDUCTOR
HARR1S
PRODUCTS DIVISION
1K x4 PROM
A mV'S'ON OF "ARR'S CORPORATOON
HM-7642P - Open CoUector Outputs
HM-7643P -"Three State" Outputs
MARCH 1978
Features
•
•
•
•
•
Pinout
50ns MAXIMUM ADDRESS ACCESS TIME,
"THREE STATE" OR OPEN COLLECTOR OUTPUTS, A POWER DOWN
INPUT, AND A CHIP ENABLE INPUT.
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
FAST ACCESS TIME FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD,
TOP VIEW - DIP
Description
The HM-7642P/43P are fully decoded high speed SchottkyTTL 4096-Bit
Field Programmable ROMs in a 1 K words by 4 bit/word format with open
collector (HM-7642P) or "Three State'" (HM-7643P) outputs. These
PROM s are available in an l8-pin DIP (ceramic or epoxy) and an l8-pin
flat pack.
A6
VCC
A5
A7
A4
AS
A3
Ag
AO
01
A1
02
A2
03
eE
04
GND
PD
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrome fuse technology is used on these and all other Harris Bipolar
PROMs.
The HM-7642P/43P contains test rows and columns which are in addition to the storage array to assure high programmability and guarantee
parametrics and A.C. performance. The fuses in these test rows and columns are blown prior to shipment.
I
There is a power down input on the HM-7642P/43P which is similar to a
chip enable. The chip can be enabled or disabled using the power down
input where a powered down chip dissipates 25% of nominal power and
the outputs go to a high impedance state. The chip is powered up
when PDl is low.
.
TOP VIEW - FLAT PACK
CE
GNO
PO
PIN NAMES
AO- Ag
01 -04
PD
CE
63,-------_-,
A7
AS
Ag
0,
02
03
04
There is also the conventional chip enable input on this device,CE low and
PD 1 low enables the device.
Functional Diagram
Vcc
A6
AS
A4
A3
AD
A,
A2
ADDRESS INPUTS
DATA OUTPUTS
POWER DOWN INPUT
CHIP ENABLE INPUT
A.
logic Symbol
409B BIT
MEMORY ARRAY
NOTE: Physical bit
................
A3
84 TRANSMISSION GATES
positions for columns
PO
are as follows:
CE
0" 03
02, 04
~
~
(,5, 0 - , 4 )
(0 - -,5)
A2
( ) = Pin Numbers
A,
(,8) ~ Vee
(9) ~ GND
AO
CE
2-44
AO
A,
A2
A3
A4
A5
A6
A7
AS
Ag
0,
02
03
04
Specifications HM-7642P143P
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 e to +150 0 e
Operating Temperature (Ambient) -55 0 e to +1250e
+1750e
Maximum Junction Temperature
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Si nk Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7642P/43P-5 (Vee = 5.0V 15%, TA = ooe to +75 0 e)
HM-7642P/43P-2 (Vee = 5.0V ±10%, TA = -55 0 e to +1250C)
Typical Measurements are at T A = 25 0 e, Vee = +5V
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
III
Address/Enable "1"
I nput Current
"0"
-
-
-50.0
+40
-250
J.lA
J.lA
VIH
Vil
Input Threshold "1"
Voltage
"0"
2.0
1.5
1.5
0.8
V
V
VOH
Val
Output
Voltage
2.4*
3.2'
0.35
0.45
V
V
10HE
10lE
Output Disable "1"
Current
"0"
-
"1"
"0"
-
VCl
Input Clamp Voltage
-
las
Output Short Circuit
-15'
-
-
100
-
+40
-40*
TEST CONDITIONS
= VCC Min.
= VCC Max.
10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCC Min.
VCC
VCC
VOH. VCC = VCC Max.
Val = 0.3V, VCC = VCC Max.
J.lA
J.lA
Power Supply Current
= -18mA
-1.2
V
-100'
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
140
mA
VCC = VCC Max., All Inputs
Grounded.
liN
Current
ICC
= VCC Max.
= 0.45V
VIH
Vil
NOTE: Positive current defined as into device terminals.
'''Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7642P/43P-5
5V.:!:.S%
DoC to +7S oC
SYMBOL
PARAMETER
MIN
TYP
MAX
-
35
50
TAA
Address Access Time
TOA
Chip Disable Access Time
-
25
30
TpU
Chip Power-Up A.ccess Time
-
80
100
HM-7642P/43P-2
SV.:!:.10%
-SsoC to +12S oC
MIN
TYP
-
-
MAX
UNITS
70
ns
40
ns
150
ns
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
CINA, CINCE
COUT
PARAMETER
TEST CONDITIONS
MAXIMUM
UNITS
Input Capacitance
8
pF
VCC
= SV,
VIN
Output Capacitance
10
pF
VCC
= 5V,
VOUT
2-45
= 2.0V, f = 1MHz
= 2.0V, f = 1MHz
E
SWITCHING TIME DEFINITIONS
,
CE& PO
CHIP ENABLES
ADDRESSES ~1.5V
VIH
, ~-------VIL
,
I
I
i
,
,,
,
,,
,
,
K
i
I
I
V",,---VOH
OUTPUTS_ _ _-4I_ _ _.J~1.5V
I
I
VOL
-I
TAA
I-I
-------
1.5V
I
,
OUTPUTS
I
1
I
I
--I TEAll--
,
,
I
I
TpU
:
A.C. TEST LOAD
VCC
PROM
OUTPUT Ox 0---+--_'--0 TEST POINT
30pF*
600n
* Includes Jig
and Probe Total
Capacitance
2-46
VIH
...., 1.5V
----VIL
,,,
,,
,
,
I
I
I,
--I
,
I
)j-T.S.
I
TPA
lI
I
m
HM-7644A
SEMICONDUCTOR
HARRIS
PRODUCTS DIVISION
1K
A DIVISION OF HARRIS CORPORATION
Features
Pinouts
•
50ns MAXIMUM ADDRESS ACCESS TIME
•
ACTIVE PULL-UP DUTPUTS
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES
•
4 PROM
Active Pull-up Outputs
MARCH 1978
•
X
TOP VIEW - DIP
INDUSTRY'S HIGHEST PROGRAMMING YIELD
AS
VCC
A5
A7
A4
AS
A3
Ag
AO
0,
LOW PIN COUNT FOR MAXIMUM DENSITY
Description
The HM-7644A is a fully decoded high speed Schottky TTL4096-Bit
Field Programmable ROM in a 1 K word by 4 bit/word format with active
pull-up outputs. This PROM is available in a 16 pin DIP (ceramic or
epoxy) and a 16 pin flatpack.
All bits are manufactured storing a logical '.,.' (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrome_ fuse technology .is used on this and all other Harris Bipolar
PROMs.
The HM-7644A contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are bloWn prior to shipment.
A,
°2
A2
03
GND
04
TOPVIEW - FLATPACK
AS --~----=--VCC
A5
A7
A4
AS
A3Ag
AO
0,
A,
02
A2
03
GND
04
PIN NAMES
Functional Diagram
AO-Ag
63,-_ _ _ _ _ _ _ _---.
Address Inputs
01-04 Outputs
logic Symbol
L-_~----'
1 OF 64
ROW
•
DECODE
•
4088 BIT
MEMORY
ARRAY
.-
............... .
84 TRANSMISSION GATES
A2
()
A,
(16)
(8)
NOTE: Physical bit
positions are as follows:
°1.°3 - (15, 0--14)
02,04- (0_15)
2-47
Pin
Numbers
Vce
GND
,I"'~
,-
Specifications HM-7644A
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0C to +1500C
Operating Temperature (Ambient) ··550C to +1250C
Maximum Junction Temperature
+1750e
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable I nput Voltage
5.5V
Address/Enable Input Current
-20m A
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in th~ operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
HM-7644A-5 (Vec: 5.0V ± 5%. TA: OOC to +75 0C)
HM-7644A-2 (Vee: 5.0V ± 10%, TA: -55 0C to +125 0 C)
Typical measurements are at T A: 25 0 C, Vee: +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
I
PARAMETER
rvp
MAX
UNITS
pA
-50.0
+40
-250
Il A
1.5
1.5
0.8
V
V
Vee
Vee
-
3.2
0.35
0.45
V
V
IOH = -2.0mA, Vee = Vee Min.
IOl = +16mA. Vee = Vee Min.
MIN
-
-
"1"
"0"
IiH
III
Address Input
Current
VIH
Vil
I nput Threshold "1"
"0"
Voltage
2.0
VOH
VOL
Output
Voltage
2.4
-
"1"
"0"
TEST CONDITIONS
VIH;VeeMax.
Vil = 0.45V
= Vee Min.
= Vee Max.
= -18mA
Vel
Input Clamp Voltage
-
-
-1.2
V
lOS
Ou'tput Short Circuit
Current
-15
-
-100
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
ICC
Poyver Supply Current
-
100
140
mA
vee = Vee Max .• All Inputs
Grounded.
liN
NOTE: Positive current defined as into device terminals.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7644A-5
5V±5%
OOC to +750 C
I SYMBOL I
l
TAA
PARAMETER
I Address Access Time
MIN
I
-
I
TYP
I
35
I
HM-7644A-2
5V± 10%
-550 C to +1250 C
MAX
50
MIN
I
TYP
I
-
J
-
I
MAX
UNITS
I
ns
I
60
A.C. Iimits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A: 25 0 C
MAXIMUM
UNITS
elNA
Input Capacitance
8
pF
Vee; 5V, VIN
eOUT
Output Capacitance
10
pF
vee: 5V. VOUT = 2.0V. f = 1 MHz
SYMBOL
PARAMETER
2·'-48
TEST CONDITIONS
=
2.0V, f = 1 MHz
SWITCHING TIME DEFINITIONS
ADDRESSES_-_-_-_-_-_-_~~~-..r-:i... I~-1.-5-V------------ VIH
VIL
----------~----~ ,-------VOH
OUTPUTS----------~-----/'-------VOL
1_1.5V
TAA
A.C. TEST LOAD
Vee
PROM
OUTPUT
Ox o------<.....--....- - Q TEST POINT
30pP
·'ncludes Jig
and Probe Total
Capacitance
2-49
m
HM-7645
HARR1S
SEMICONDUCTOR
PRODUCTS DIVISION
.
.
1K
A D'V"'ON OF HARR., CORPORAT.ON
MARCH 1978
Pinout
•
50ns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OUTPUTS AND FOUR CHIP ENABLE INPUTS
•
SIMPLE HIGH SPEI;D PROGRAMMING PROCEDURE ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
•
TOP VIEW-DIP
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N:a SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHESTPROGRAMMING YIELD.
A6
VCC
A5
A7
A4
AS
A3
AS
CE2
214:a PINOUT
Description
The HM-7645 is a fully decoded high speed Schottky TTL 4096 Bit
Field Programmable PROM in a lK word by 4 bit/word format with
"Three State" outputs. This PROM is available ina 20 pin DIP (ceramic
or epoxy) and a 20 pin flat pack ..
All bits are manufactured storing a logical "'" (positive logic) and can
be selectively programmed for a logical "0" in any bit position.
The HM-7645 contains test rows and columns which are in addition to
the storage array to assure high programr.1ability and guarantee parametrics and AG. performance. The fuses in these test rows and columns
ar{! blown prior to shipment.
There are four chip e!1able inputs on the HM-7645. GE,. GE3 low and
GE2. GE4 high enables the chip.
Functional Diagram
CE3
AD
01
Al
02
A2
03
CEl
04
GND
CE4
TOP VIEW-FLAT PACK
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
I
4 PROM
"Three State" Outputs
Preview
Features
•
X
A6
VCC
AS
A4
AS
A3
A9
CE2
CE3
A7
01
AO
A1
02
03
. A2
CE1
04
GND
CE4
63,.-----------'---,
PIN NAMES
AD-AS
01 -04
CE1.CE3
CE2. CE4
4096 BIT
MEMORY ARRAY
ADDRESS INPUTS
DATA OUTPUTS
CHIP ENABLE INPUTS
Logic Symbol
~1----r------,
Ag
94 TRANSMISSION GATES
~OTE:
Physical bit
CE2
~3
CE4
AO
A1
A2
A3
positions for"columns
A4
are as follows:
AS
A6
A7
°1.°3
°2.04
= (15.0-14)
= (0 -15)
As
Ag
( ) = Pin Numbers
(20) = Vee
(10) =GND
2-50
Specifications HM-7645
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0C to +150 0 C
Ope'rating Temperature (Ambient) -55 0C to +1250C
+175 0C
Maximum Junction Temperature
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20m A
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
HM-7645-5 (Vcc = 5.0V± SOlo, TA = ooC to +75 0 C)
HM-7645-2 (VCC = 5.0V ± 10%, TA = -55 0 C to +125 0 C)
Typical Measurements are at T A = 25 0 C, VCC = +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
TEST CONDITIONS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
ilL
Address/Enable "1"
"0"
I nput Current
-
-50.0
+40
-250
J.l.A
J.l.A
VIH
VIL
Input Threshold "1"
"0"
Voltage
2.0
-
1.5
1.5
0.8
V
V
VCC
VCC
= VCC
= VCC
VOH
VOL
Output
Voltage
"1"
"0"
2.4
-
3.2
0.35
0.50
V
V
10H
10L
= -2.0mA, VCC = VCC Min.
= +16mA, VCC = VCC Min.
10HE
10LE
Output Disable
Current
"1"
"0"
-
-
+40
-40
J.l.A
J.l.A
-
VIH = VCC Max.
VIL = 0.45V
Min.
Max.
VOH. VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
= -18mA
VCL
Input Clamp Voltage
-
-
-1.2
V
lOS
Output Short Circuit
Current
-15
-
-100
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
ICC
Power Supply Current
-
100
140
mA
VCC = VCC Max., All Inputs
Grounded.
liN
NOTE; Positive current defined as into device terminals.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7645-5
5V:!:5%
OOC to +75 0 C
~YMBOL
PARAMETER
TAA
Address Access Time
TEA
Chip Enable Access Time
MIN
TYP
-
35
25
HM-7645 C 2
5V:!:10%
-55 0 C to +125 0 C
MAX
MIN
TYP
MAX
UNITS
50
-
ns
-
-
70
30
40
ns
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0C
SYMBOL
CINA, CINCE
COUT
MAXIMUM
UNITS
Input Capacitance
FARAMETER
8
pF
VCC
= 5V, VIN = 2.0V, f = lMHz
Output Capacitance
10
pF
VCC
= 5V,
2-51
TEST CONDITIONS
VOUT
= 2.0V. f = lMHz
E
SWITCHING TIME DEFINITIONS
CE1. CE3
I
~1.5V
ADDRESSES
I
I
I
--------------~
"VIL
.,
.
CE2.CE4
I
----......I
OUTPUTS
-I
I
I
I
I
I
I
~VOH
I 1.5V
k
i
OUTPUTS
I
I
VOL
-l
I--
I
I
I
TEA
I
I
II
I
A.C. TEST LOAD
VCC
PROM
OUTPUT Ox o-----+----4t---() TEST POINT
soon
30pF*
* Includes Jig
and Probe Total
Capacitance
PI
.
! >t--:
i
I
I
,~-----
~VIH
1.5V
CHIPE~1.5V
VIH
,
I
I
I
I
I
I
I
I
I
--i
I
I
TEA
F
I
VIL
T.S.
m
HM-7645P
HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
1K
A DIVISION OF HARRIS COAPOAATION
MARCH
4 PROM
"Three State" Outputs
1975PrBViBW
Features
•
X
Pinouts
SOns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OUTPUTS AND FOUR POWER DOWN INPUTS
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY
•
FAST ACCESS TIME - FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOL TAGE RANGES
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
•
2142 PINOUT
TOP VIEW - DIP
AS
VCC
AS
A7
AS
Ag
A3
Description
The HM-7645P is a fully decoded high speed Schottky TTL 4096-Bit
Field Programmable ROM in a 1K by 4 bit/word format with "Three
State" outputs. This PROM is available in a 20 pin DIP (ceramic or
epoxy) and a 20 pin flatpack.
All bits are manufactured storing a logical "1" (positive ·Iogic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrome fuse technology is used on these and all other Harris Bipolar
PROM's.
The HM-7645P contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
P03
PD2
Ao
0,
A,
02
A2
03
PO,
04
GNO
PD4
TOP VIEW - FLATPACK
There are four power down inputs on the HM-7645Pwhich are similarto
chip enables. The chip is enabled or disabled using the power down inputs
where ,a disabled chip dissipates 30% of nominal power and the outputs go
to a high impedance state. The' chip is powered up (enabled) when PD1,
PD3 are low, and PD2, PD4 are high.
E
Functional Diagram
PIN NAMES
AO-Ag
01-04
P01. Po2,
Address Inputs
Data Outputs
Power Down Inputs
POa. PD4
40118 BIT
Logic Diagram
MEMORY
ARRAY
NOTE: Physical bit
• • • • • • • • • • • • • • eo • •
84 TRANSMISSION GATES
positions for columns
are as follows:
°1.°3 =,(15. 0-14)
°2.°4 = (0-15)
2-53
,0,
Specifications HM-7645P
ABSOLUTE MAXIMUM RATINGS
StQrage Temperature
,
-650C to +l50 6C
Operating Temperature (Ambient) ":S5 0Cto +1250C
+175 0C
Maximum JU,nction Temperature
Output prSupply Voltage (Operating) -0.3 to +7.0V
" 5.5V'
Address/Enable 'Input Voltage
-20m A
Address/Enable Input Current
Output Sink Current
100mA
CAUTION: St;e.ses above tho.e Ii.ted under the "Ablfoltite Maximum Ratings" ",ay calise permanent damage to the device; These
are stress only ratings and functional operation of the device at these or at any other condition. above those, indicated in the operational
sections of this specification is not implied. {While programming, fo(/owthe p;ogramming specifications.)
HM-7645P-5 (VCC = 5.0V ± 5%, TA = ooC to +750 C)·
HM-7645P~2 (VCC = 5.0V ± 10%, TA = -55 0C to+1250 C)
, Typical measurements are at t A = 250C, VCC,= +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
I
SYMBOL
PARAMETER
MIN
TYP
, MAX
UNITS
IIH
-
-
, +40
-250
'p.A
P.A,
VIH = Vee Max:
VIL =O.45V
-
V
V
Vee = Vee Min.
Vee = Vee Max.
II,L
Address/Enable "1"
"0"
I nput Current
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
VOH
VOL:
Output
Voltage
2.4
lQHE
IOLE
Output Disable "1"
Currerit
"0"
-
"1"
"0"
-
e50.0
1.5
1.5
O.S
3.2
0.35
V
,V
'-
0.50
-
TEST CONDITIONS
:
.,
'"
10H = -2.0mA;VeC= VCeMin.
10L = +16mA, VCC =VCC Min.
VOH, VCC = Vee'Max. "
VOL =.().3V,VCC = Vce Max.
p.A
p.A
-
+40
-40
-1.2
V
~100
mA
VOUT = O.OV, One Output at a,
Time lor a Max. 01 1 Second
140
mA
VCC = VCC Max., All Inputs
Grounded.
VCL
Input Clamp Vqltage
lOS
Outpu'tShort Circuit
Current
-15
-
ICC
Power Slipply Current
-
100
liN = -1SmA
NOTE; Positive current defined as into device terminals.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7645P-2
5V:!:.10%
-55OC to +1250 C
HM-7645P-5
5V±'5%
OOCto +750 C
SYMBOL
TAA
TpD
TpU
PA~AMETER
Address Access Time
Chip'Power-Down
AcciissTime
Chip Power-Up Access Time
MIN
TYP
MAX
MIN
TYP
-
35
50
-
-
25
30
-
-
-
SO
100
-
-
MAX
UNITS
70
"5)'.
40
ns
150
'"
s
A.C: limits guaranteed lor worst case N2 sequencing.
CAPACITANCE: T A =250C
~YMBOL
MAXIMUM
UNITS
CINA, CINCE
I nput Capacitance,
PARAMETER
S
pF
Vce = 5V;VIN = 2.0V, I = 1 MHz
COUT
Output Capacitance
10
pF
Vce = 5V, VOUT = 2.0V, 1= 1MHz
,
TEST CON'DITIONS
.;
SWITCHING TIME DEFINITIONS
PD,. PD3
ADDRESSES
/"""---VIH
VIL
-i ~1.5V
POWER DOWNS
----VIL
VOH
PD2.Po4
OUTPUTS
---------+-----/
TAA
~'
VOH
OUTPUTS
T.S.
VOL
A.C. TEST LOAD
Vee
PROM
OUTPUT
---.-o()
OxD---....
600n
TEST POINT
30pF*
.* Includes Jig
and Probe Total
Capacitance
I
2-55
m
HAR.RJS
SEMICONDUCTOR
PRODUCTS DIVISION
HM-7647R
A DIVISION OF HARRIS CORPORATION
512 x 8 PROM
DECEMBER 1977
Features
•
•
•
Pinout
SOns MAXIMUM ADDRESS ACCESS TIME
"THREE STATE" OUTPUTS WITH TWO CHIP ENABLE INPUTS
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING
OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE
RANGES.
•
•
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
PIN COMPATIBLE WITH THE 82S115
•
•
LATCHED OUTPUTS
INPUT LOADING IS - l00I.lA MAXIMUM
TOP VIEW - D.I,P.
A3
Description
The HM-7647R is a fully decoded high speed Schottlky TTL 4096-Bit
Field Programmable ROM in a 512 word by 8 bit/word format and is
available in a 24 pin D.I.P. (ceramic or epoxy) and a 24 pin flatpack.
VCC
A4
A2
A5
AS
Al
AO
A7
AS
01
CEl
CE2
STR
02
Os
03
04
NC
GND
07
Os
05
NC
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any position. The HM-7647R
has "Three State" outputs.
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
I
TOP VIEW - FLATPACK
===jj'rr===
vcc
The pinout is identical to the 825115 PROM.
A3
The HM-7647R colltainstest rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametric
and A.C. performance. The fuses in these test rows and columns are
blown prior to shipment.
A5
A,
AS
A7
AS
GE,
0,
STR
02
Os
A4
There are two chip enable inputs on the HM-7647R. CE, low and CE2
high enables the chip.
HM-7647 R is operated in the Transparent Read Mode by holding the
strobe input high throughout the read operation. This is the normal read
mode where the two chip enable inputs will control the outputs.
In Latched Read Mode, bringing the strobe input low will latch the outputs and chip enable inputs. If the device is disabled when the strobe
input goes low the outputs will be latched in the high impedance state. If
the device is in the latched mode the strobe input must be brought high to
allow the outputs to respond to new address or chip enable conditions.
A2
AO·
CE2
03
07
04
NC
GND
Os
05
NC
PIN NAMES
AO-AS
01-0S
CEl - CE2
STR
Functional Diagram
Address Inputs
Data Outputs
Chip Enable Inputs
Latch Input
logic Symbol
"r-________________________
Vee· t241
~GN~D_.(~12~)
_______,
CEl
CE2
STR
AO
Al
A2
A3
A4
A5
AS
A7
AS
0,
01
02
03
04
05
Os
07
Os
Specifications HM-7647R
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to ::f"1500 C
Operating Temperature (Ambient) -55 0 C to +1250C
Maximum Junction Temperature
+175 0 C
Output or Supply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
Address/Enable Input Current
-20mA
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
HM·7647R-5 (VCC = 5.0V.±5%, TA = ooC to +75 0C)
HM-7647R-2 (VCC = 5.0V .±lO"A., TA =-55 0 C to +125 0 C)
Typical measurements are at T A = 25 0 C, VCC = +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
PARAMETER
MIN
TYP
-
-
IIH
IlL
Address/Enable
I nput Current
"'1"'
"0"'
VIH
VIL
Input Threshold
Voltage "0"
"1"
"0"
2.0
VOH
VOL
Output "1"
Voltage "0"
"1"
"0"
2.7(2)
10HE
10LE
Output Disable
Current "0"
"1"
"0"
MAX
-50
P.A
P.A
VIH = VCC Max.
VIL = 0.45V
V
V
VCC = VCC Min.
VCC = VCC Max.
V
V
10H - -2.0mA, VCC = VCC Min.
10L = +16mA, VCC = VCC Min.
-
1.5
1.5
0.S5
3.3
0.35
0.50 "
-
TEST CONDITIONS
UNITS
+25
-100(1 )
-
VCL
Input Clamp Voltage
-
V
Output S.C. Current
·20
-
-1.2
lOS
-70
mA
VOUT=O.OV
One Output Only for a Max.
of 1 Second
ICC
Power Supply Current
-
135
lS5
mA
VCC = VCC Max. AU Inputs
Grounded
-
+40
-40
-
VOH, VCC = VCC Max.
VOL = a.3V, VCC = VCC Max.
P.A
P.A
liN - -1 SmA
..
'Posltlve current defoned as onto deVIce termonals .
NOTE(1):
NOTE(2):
IIL=-150p.Afor-2
VOH = 2.4V for -2
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7647R-5
5V.:!:S%
OOC to +7SOC
HM-7647R-2
SV.:!: 10%
-S5OC to +1250 C
SYMBOL
PARAMETER
MIN
TVP
MAX
MIN
TYP
MAX
UNITS
TAA
TEA
Address Access Time
Chip Enable" Access Time
-
40
30
60
40
-
50
40
SO
50
ns
ns
TADH
TCDH
TSW
TSL
TDL
TCDS
Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Tim"e "
Strobe Delatch Time
Chip Enable Set-Up Time
0
10
30
60
-10
0
15
35
-
0
10
40
SO
-10
0
15
45
-
ns
ns
ns
ns
ns
ns
-
40
-
40
-
-
-
50
50
-
TEST CONDIT.
Transparent
Latched
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 250C
SYMBOL
CINA,CINCE
COUT
PARAMETER
I nput Capacitance
Output Capacitance
MAXIMUM
U",ITS
TEST CONDITIONS
S
pF
VCC = 5V, VIN = 2.0V, f = lMHz
10
pF
VCC = 5V. VOUT = 2.0V, f = lMHz
2-57
I
SWITCHING TIME DEFINITIONSITRANSPARENT MODE)
ADDRESSES
---_../-j~1.5V
OUTPUTS
TEA
.
VIH
CE,
,---:--'-- V IH
VIL
CE2
'----vIL
OUTPUTS
T.S.
VOH
~
VOL
NOTE:Strobe input must remain high throughout read cycle while in transparent mode.
SWITCHING TIME DEFINITIONS (LATCHED MODE)
1·,...'-.5-V----------T-A-D-H-'""""""'1~'~·5~V~~~~~~~~~~~~~~~= ~:~
ADDRESS _ _ _ _
+-__ r-- TCDS
I
~ 1.5V
CE, _ _ _ _
CHIP ENABLE
--..I~
CE2-----,-+-I---'
STROBE
OUTPUT
,.-_______ VIH
.\'
I
I;: sw-+. . .
*-,'.5V
I. .____';::____~~I'-~-.5-V_-----'
~
VIL
11'-. TC0-1
I·----,--TCDH----..+
T
.. tDL
TAA ==r....;1;.:;.5;.;V-·_ _ _ _ _ _ _ _ _ _
I
A.C. TEST LOAD
PROM OUTPUT Ox o---.,.;~-.....--o TEST POINT
soon
30pF*
* Includes Jig
and Probe Total
Capacitance
2-58
L~:::
---J~~---T.S.
II
HARRIS
HM-7648/49
SEMICONDUCTOR
PRODUCTS DIVISION
512 x 8 PROM
A DIVISION OF HARRIS CORPORATION
HM-7648 - Open Collector Outputs
H M-7649 - "Three State" Outputs
APRIL 1978
Features
Pinouts
•
SOns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND A CHIP ENABLE
INPUT
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING
OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE
RANGES.
TOP VIEW - D.I.P.
Vee
A8
A7
AS
AS
INDUSTRY'S HIGHEST PROGRAMMING YIELD
CE
•
PIN COMPATIBLE WITH THE 74S472/73
08
•
LOW INPUT LOADING
07
•
Os
Description
Os
The HM-7648/49 is a fully decoded high speed Schottky TTL 4096-Bit
Field Programmable ROM in a 512 word by 8 bit/word format with open
collector (HM-7648) or "Three State" (HM-7649) outputs. These PROMs
are available in a 24 pin D.I.P. (ceramic or epoxy) and a 24 pin flat pack.
TOP VIEW - FLATPACK
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
I
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
The pinout is identical to the 74S472/73 PROM.
The HM-7648/49 contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametic
and A.C. performance. The fuses in these test rows and columns are
blown prior to shipment.
PIN NAMES
AO-A8
0,-08
CE
There is a chip enable input on the HM-7648/49 where CE low enables
the device.
Functional Diagram
Address Inputs
Data Outputs
Chip Enable Input
logic Symbol
64,64
MEMORY
CE
ARRAY
AO
01
AI
A2
02
03
A3
04
A4
AS
AS
05
Os
A7
A8
10)
0,
10)
03
19)
o.
1111
o.
(12)
(131
00
07
2-59
o.
(14)
°7
08
Specifications HM-7648/49
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-650 C to +1500 C
Operating Temperature (Ambient) -55bC to +1250 C
Maximum. Junction Temperature
+1750 C
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
.5.5V
-20mA
Address/Enable Input Current
Output Sink Current
l00mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any othercondi;ions above thdse indic#Jred.in the.operationBl
sections of this specification is not implied. (While programming, follow the programming specifications.)
HM-764S/49:"5 (VCC", 5.0V±5%, T A. = OOC to +750 C)
HM-764SJ49-2 (VCC'; 5.DV 110%: TA = -550 C to +1250 C)
Typical measurements are at T A = 250 C, VCC = +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
.
I
PARAMETER
Input·Cu~rent
"1"
"0"
-
VIH
Vil
Input Thre.shold
Voltage
"1"
"0"
2.0
VOH
VOL
OutPut
"1"
"0"
2.4'
Volt~ge
10HE
10LE
OutPut Disable
Current
"1"
"0"·
Input Clamp Voltage
OutPut S.C. Current
ICC
Power Supply Current
-50
+25.
-250
P.A
IJ.A
VIH = VCC Max.
Vll=0.45V
1.5
1.5
O.BO
V
V
VCC = VCC Min.
VCC = VCC Max.
3.2"
0.35
0.50
-
V
V
10H = -2.0mA, VCC = VCC Min.
10L·= +l6mA,Vc:C = Vce Mill.•. ·
-
+50
IJ.A
IJ.A
-
Address!Enable
.105
UNITS'
TYP
1114
III
VCl
MAX
MIN
-
-
-
-
-1.2
V
-
-100'
mA
120
170
mA
-20'
-50'
,TEST CONDITIONS'
VOH; VCC = Vee Max.
VOL.:~o-,3V, VCC = VeC Max.
IIN·=-lBmA
VOUT=O.OV
One Output Only for a Max.
1 Second
of
-
VCC = VCC Max. All Inputs
Grounded
• "Three State" only
·NOTE: Positive current defined as into davice terminals.
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7648/49-5
5V±5%
OOC to+ 7SOC
SYMBOL
PARAMETER
TAA
Address Access Time
TEA
Chip Enable Access Time
HM-764W49-2
5V±10%
-550 C to + 1250C
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-
55
60
-
50
BO
ns
20
40
30
50
AS
-
A.C. limits guaranteed for worst case N2: sequencing.
CAPACITANCE: T A = 250 C
,.
SYMBOL
PARAMETER
CINA,CINCE
COUT
..
MAXIMUII4
InpUt Capacitance
B
OutPut Capacitance
10
.,
2-6.0
.....
' UNITS
TEST CONDITIONS
pF
VeC = 5V, VIN = 2.0V, f = lMHz
pF
VCC= 5V, VOUT = 2.0V,f= lMHz
.
SWITCHING TIME DEFINITIONS
,
~'f1.5V,
,
:
CE
-------.' ,..--------VIH
ADDRESSES _ _ _ _
VIL
,
________i_____..., , ,..____ VOH
OUTPUTS _ _ _ _ _ _1~
-!
__
_'¥1.5V
TAA
VOL
r-
:
r. . . . . . . .
_---VIH
1.5V
VIL
--1(:(
OUTPUT - - - . ; . ,
:
------: TEA
rI
! >.•
1
T.S.
: :
~
TEA
-~,:
i
i
A.C. TEST LOAD
PROM
OUTPUT
Ox
o---t-----.-<) TEST POINT
30pF*
600n
* Includes Jig
and Probe Total
Capacitance
I
2-61
m
HM-7680/81
SEMICONDUCTOR
HARRIS
PRODUCTS DIVISION
,.
1K
A DIVISION OF HAR .... CORPORATION
DECEMBER 1977
8 PROM
HM-7680", Open Collector Outputs
HM-7681 -"ihree State" Outputs
Preliminary
Pinouts
Features
•
60ns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND FOUR CHIP
ENABLE INPUTS
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
•
X
INDUSTRY'S HIGHEST PROGRAMMING YIELD
TOP VIEW-DIP
A7
Ae
A5
A4
A3
A2
A,
Description
The HM-7680/81 is a fully decoded high speed Schottky TTL 8192/8it
Field Programmable ROM in a 1 K word by 8 bit/word format wi.th Open
collector (HM-7680) or "Three State" (HM-7681) outputs., These
PROM's are available in a 24 pin D.I.P. (ceramic or epoxy) and II ,24 pin
flat pack.
All bits are manufactured storing a logical "1" (Positive Logic) and can be
selectively programmed for a logical "0" in anyone bit position.
AO
0,
02
03
GND
VCC
AS
Ag
~,
~2
CE3
CE4
Os
07
Oe
05
04
TOP VIEW - FLATPACK
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
I
The HM-7680/B1 contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There are four chip enable inputs on the HM-7680/81. CE1. CE2 low,
and CE3, CE4 high enablesthe chip.
Functional Diagram
63.-------------,
10F84
ROW
DECODE
•
NOTE: PHVSICAL BIT POSITIONS
FOR COLUMNS ARE AS FOLLOWS:
O,.0&0s.07-0-1S)
Oz. 04. 0&. 08-n6,O-141
S192 BIT
MEMORY
ARRAY
CE 1, CE2,
PIN NAMES
AO - A9' Address Inputs
01 - Os Data Outputs
CE3. CE4 Ch ip Enable Inputs
Logic Symbol
.................. .
128 TRANSMISSION GATES
(
) a
(24)~
Pin Numbers
Vce
(12)· GND
Specifications HM-7680/81
ABSOLUTE MAXIMUM RATINGS
-650C to +1500 C
Storage Temperature
Operating Temperature (Ambient) -55 0 C to +l250 C
Maximum Junction Temperature
+1750 C
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
100mA
Output Sink Current
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
PARAMETER
MIN
HM-7680/81-5 (VCC = 5.0V ±5%, TA = ooC to +75 0 C)
HM-7680/81-2 (VCC = 5.0V ±10%, T A = -55 0 C to +1250 C)
Typical measurements are at T A = 250 C, VCC = +5V
TYP
-
MAX
UNITS
TEST CONDITIONS
IIH
IlL
Address/enable
Input Current
"1"
"0"
-
-50.0
+40
-250
JJ.A
JJ.A
VIH = VCC Max.
VIL = 0.45V
VIH
VIL
Input Threshold
Voltage
"1"
"0"
2.0
1.5
1.5
0.8
V
V
VCC = VCC Min.
VCC = VCC Max.
VOH
VOL
Output
Voltage
"1"
"0"
2.4 •
3.2'
0.35
0.50
V.
V
10H = -2.0mA, VCC = VCC Min.
10L = +16mA, VCC = VCC Min.
10HE
IDLE
Output Disable
Current
"1"
"0"
+40
-40'
JJ.A
JJ.A
-
VCL
I nput Clamp Voltage
-
lOS
Output S.C. Current
-15'
-
ICC
Power Supply Current
-
130
-
-
-1.2
-100'
mA
VOUT= O.OV
One Output Only for a Max.
of 1 Second
170
mA
VCC = VCC Max. All Inputs
Grounded
VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
V
liN = -18mA
NOTE: Positive current defined as into device terminals .
• "Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7680/81-5
5V±5%
ooc to + 750 C
SYMBOL
PARAMETER
MIN
TYP
HM-7680/81-2
5V ±10%
-550 C to + 1250 C
MAX
MIN
TYP
MAX
UNITS
-
80
ns
50
ns
TAA
Address Access Time
-
45
60
-
TEA
Chip Enable Access Time
-
30
40
-
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
PARAMETER
MAXIMUM
UNITS
TEST CONDITIONS
CINA, CINCE
I nput Capacitance
8
pF
VCC = 5V, VIN = 2.0V, f = lMHz
COUT
Output Capacitance
10
pF
VCC = 5V, VOUT = 2.0V, f = lMHz
2-63
I
SWITCHING TIME DEFINITIONS
--'----.J/~~-----VIH
ADDRESSES
OUTPUTS
1.6V
' -_ _ _ _ _ _.-VIL
Ce1. CE2 _ _......,.
CHIP ENABLES
CE3 III CE4--~
~-.,....--_ ~.,....---VIH
' -_ _ _
vL
~~--VOH
_----:...__
+~_J
VOL
OUTPUTS-------t---r'-_~~-~
A.C. TEST LOAD
PROM
OUTPUT
Ox o--~~-...-oTEST POINT
3OpF*
• Includes Jig
and Probe Total
Capacitance
I
2-64
T.S.
m
HARRIS
HM-7680R/81R
SEMICONDUCTOR
PRODUCTS DIVISION
1K x 8 PROM
A DIVISION OF HARRIS CORPORATION
DECEMBER 1977
HM-7680R - Open Collector Outputs
HM-7681R - "Three State" Outputs
Preliminary
Features
Pinouts
•
60ns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND THREE CHIP
ENABLE INPUTS
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURES AND VOLTAGE RANGES
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
•
LATCHED OUTPUTS
TOP VIEW-DIP
Description
The HM-7680R/81 R is a fully decoded high speed Schottky TTL 8192Bit Field Programmable ROM in a 1 K word by 8 bit/word format with
open collector (HM-7680R) or "Three State" (HM-7681 R) outputs.
These PROMs are available in a 24 pin D.I.P. (ceramic or epoxy) and a
24 pin flatpack.
TOP VIEW - FLATPACK
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrome fuse technology is used on these and all other Harris Bipolar
PROMs.
The HM-7680R/81 R contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
E
There are three chip enable inputs on the HM-7680R/81 R. CE1, CE2 low
and CE3 high enables the chip.
The HM-7680R/81 R is operated in the Transparent Read Mode by holding the strobe input high throughout the read operation. This is the normal read mode where the three chip enable inputs will control the outputs.
In Latched Read Mode, bringing the strobe input low will latch the outputs and chip enable inputs. If the device is disabled when the strobe
input goes low, the outputs will be latched in the high impedance state. If
the device is in the latched mode the strobe input must be brought high to
allow the outputs to respond to new address or ch ip enable conditions.
PIN NAMES
AO - A9
a' - as
eEl. CE2, CE3
STR
Address Inputs
Data Outputs
Chip Enable Inputs
Strobe
logic Symbol
Functional Diagram
NOTE: Physical bit position'
for columns are as follows:
0,.°3.°5_ 07-(0-15)
02_ 04. 06. 08-(15. 0_14)
819ZBlT
MEMORY
AIIRAY
(
) =:
Pin Numbers
(24) "" Vee
(12) '" GND
2-65
Specifications HM-7680R/81R
ABSOLUTE MAXIMUM RATINGS
-650 C to +150 0C
Storage Temperature
Operating Temperature (Ambient) -55 0C to +125 0C
Maximum Junction Temperature
+1750C
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
-20mA
Address/Enable Input Current
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditi(Jns above those indicated in the operational
sections of this specification is not implied. (While programming. folloW the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ilH
III
Address/Enable
Input Current
'1"
"0"
-
-50.0
+40
-250
JlA
JlA
VIH = Vee Max.
Vil = 0.45V
VIH
Vil
I nput Threshold
Voltage
"1"
"0"
2.0
1.5
1.5
O.S
V
V
Vee= Vee Min.
Vee = Vee Max.
VOH
VOL
Output
Voltage
"1"
"0"
2.4"
3.2*
0.35
0.50
V
V
10H = -2.0mA, Vee = vee Min.
10l'= +16mA, Vee = vee Min.
10HE
10lE
Output Disable
Current
"1"
"0"
+40
-40'
JlA
JlA
SYMBOL
I
HM-7680R/81 R-5 (VCC = 5.0V ±5%, TA = OoC to +750 C)
HM-7680R/81 R-2 (VCC =5.0V T10%, TA = -55 0C to +125 0C)
Typical measurements are at T A = 250 C, V CC = +5V
VCl
Input Clamp Voltage
lOS
Output S.C. Current
ICC
Power Supply Current
-
-
-
-
VOH, Vce - Vce Max.
VOL = 0.3V, VCC = Vee Max.
-
-1.2
V
-15*
-2.5
-100*
mA
VOUT= O.OV
One Output Only for a Max.
of 1 Second
-
130
170
mA
Vce = Vec Max. All Inputs
Grounded
liN =-lSmA
NOTE: Positive current defined as into device terminals.
*"Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7680R/81 R-6
5V±5%
OOC to +750 e
HM-7680R/81 R-2
5V±10%
-55OC to + 1250 e
SYMBOL
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TAA
TEA
Address Access Time
Chip Enable Access Time
-
45
30
60
40
-
-
SO
50
ns
ns
latched or
Transparent
TADH
TCDH
TSW
TSl
TDl
TCDS
Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe latch Time
Strobe Delatch Time
Chip Enable Set-Up Time
0
10
30
60
-10
0
10
40
-
n.
ns
ns
ns
ns
ns
latched Only
-
0
10
40
SO
-10
0
10
40
-
-
40
40
-
-
-
50
50
-
TEST CONDIT.
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: TA = 25 0 C
SYMBOL
PARAMETER
MAXIMUM
UNITS
TEST CONDITIONS
CINA,CINCE
I nput Capacitance
S
pF
VCC =5V, VIN = 2.0V, f = lMHz
COUT
Output Capacitance
10
pF
Vce =5V, VOUT = 2.0V, f = lMHz
2-66
SWITCHING TIME DEFINITIONS (Transparant Modal
-----~~----~----VIH
ADDRESSES _ _ _ _ _"...; ~1.5V
OUTPUTS
VIL
CE,. CE2-~----"I';-",,"---_"'" /-:-::::-:--_ VIH
CHIP ENABLES
VIL
CE3
~---VOH
-----+----' I~V
T.8.
VOL OUTPUTS'
I
TAA
NOTE: Strobe input must remain high throughout read cycle while in transparent mode.
SWITCHING TIME DEFINITIONS (Latched Mode)
ADDRESSES
--....
~
~
K1.5V
I--TCDS
CE,.CE2
CHIP ENAB LES
CE3
TADH-
1.5V~~
oj !\,.5V
f-Tsw
1.5V
STROBE
1.5V
-
TCD-
TCDH
~1.5V
1.5V
-
TSL
OUTPUTS
)K1.5V
TAA
A.C. TEST LOAD
PROM
OUTPUT
OXo---1~-""'-03
1'04
AO
A1
A2
A3
A4
AS
AS
A7
AS
A9
2,-68
SpBcificBtions 7680PI81P
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20m A
Output Sink Current
100mA
Storage Temperature
-650 C to +150 0 C
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
+175 0 C
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" mav cause permanent damage to the device. These
are stress onlv ratings and functional operation of the device at these or at anv other condition. above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
HM-7680P/81P-5 (VCC = 5.0V ± 5%, TA = ooC to +750 C)
HM-7680P/81P-2 (VCC = 5.0V ± 10%, TA = -55 0 C to +125 0 C)
Typical measurements are at T A = 25 0 C, VCC = +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
III
Address/Enable "1"
Input Current
"0"
-
-50.0
+40
-250
J..I.A
J..I.A
VIH = VCC Max.
Vil =0.45V
VIH
Vil
Input Threshold "1"
Voltage
"0"
2.0
1.5
1.5
0.8
V
V
VCC = VCC Min.
Vce = Vec Max.
VOH
Val
Output
Voltage
2.4-
3.2·
0.35
0.50
V
V
10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCC Min.
10HE
10lE
Current
-
"1"
"0"
-
Output Disable "1"
"0"
Volt~ge
VCl
Input Clamp
las
Output Short Circuit
Current
-15'
ICC
Power Supply Current
-
-
-
+40
VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
J..I.A
J..I.A
-40 •
130.
TEST CONDITIONS
-1.2
V
-100'
mA
VOUT = O.OV, One Output at a
Time for a Max. of i Second
170
mA
VCC = VCC Max., All Inputs
Grounded.
liN = -18mA
NOTE: Positive current defined as into device terminals.
'''Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7680P/81P-5
5V±5%
OOC to+750 C
SYMBOL
PARAMETER
MIN
TAA
Address Access Time
Chip Power-Down
Access Time
Chip Power-Up Access Time
-
TpD
TpU
HM-768OP/81P-2
5V.± 10%
-55OC to + 1250C
TYP
MAX
MIN
45
60
30
40
80
100
-
TYP
- ,
-
MAX
UNI.TS
80
ns
50
ns
150
ns
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: TA = 25 0 C
SYMBOL
CINA, CINCE
COUT
PARAMETER
MAXIMUM
UNITS
I nput Capacitance
8
pF
VCC = 5V, VIN = 2.0V, f = lMHz
Output Capacitance
10
pF
VCC = 5V, VOUT = 2.0V, f = lMHz
2-69
TEST CONDITIONS
I
SWl'rCHIN(; TIME DEFINITIONS
PD1. PD2
ADDRESSES _ _ _ _J
VIH
1.5V
VIH
POWER DOWNS
VIL
VIL
PD3.PD4
VOH
15V
OUTPUTS
-----------+---T-A-A-/~
VOL
OUTPUTS
A.C. TEST .LOAD
PROM
OUTPUT
Ox o---~~--"",-o TEST POINT
30pF*
* Includes Jig
and Probe Total
Capacitance
I
2-70
T.S.
m
HM-7680RP/81RP
HARR1S
SEMICONDUCTOR
PRODUCTS DIVISION
1K
X
8 PROM
A DIVISION OF "'ARRIS CORPORATION
APR/L 1978
Preview
HM-7680RP - Open Collector Outputs
HM-7681RP - "Three State" Outputs
Features
Pinouts
•
•
SOns MAXIMUM ADDRESS ACCESS TIME.'
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND TWO CHIP ENABLE
INPUTS.
TOP VIEW-DIP
•
SIMPLE HIGH SPEED PROGRAMMING PROC.EDURE~- ONE PULSE/BIT. ASSURES
FAST PROGRAMMING AND SUPERIOR RELIABILITY.
A7
VCC
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER
COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
AS
A5
A4
AS
Ag
LATCHED OUTPUTS.
A POWER DOWN INPUT ALLOWING 70% REDUCTION IN NOMINAL POWER DISSIPATION.
A3
A2
A,
•
•
•
Description
'CE,
CE2
PO
STR
AO
The HM-7680RP/81 RP are fully decoded high speed Schottky TTL 8192-Bit
Field Programmable ROMs in a 1 K words by 8 bit/word format with open collector
(HM-7680RP) or "Three State" (HM-7681RP) Outputs. These PROMs are available in a 24 pin DIP (ceramic or epoxy) and a 24 pin flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be selectively
programmed for a logical "0" in any bit position.
Os
07
0,
02
03
05
GND
04
Os
TOP VIEW-FLATPACK
Nichrome fuse technology is used on these and all other Harris Bipolar PROMs.
The HM-7680RP/81 RP contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametrics and
A.C. performance. The fuses in these test rows and columns are blown prior to
shipment.
E
There are two chip enable inputs on the HM-7680RP/81 RP. CEl and CE2 low
enables the device.
There is also a power down input on this device. A powered down device has 70%
reduction in nominal power dissipation if the outputs are not latched and 50% reduction in nominal power if the outputs are. latched.'
The HM-7680RP/81 RP is operated in the Transparent Read Mode by holding the
the strobe input high and the PD. input high throughout the read operation. This is
the normal read mode where the two chip enables and the power down inputs will
control the outputs.
In Latched Read Mode, bringing the strobe input low will latch the outputs and
the chip enable inputs. However, the power down input is independent of the latch
function and can be changed while in the latched mode. If the device is disabled
when the strobe input goes low, the outputs will be latched in the high impedance
state. If the device is in the latched mode, the strobe input mUst be.broughthigh to
allow the outputs to respond to new address or chip enable conditions.'
The following is a summary of the functional dependencies of the operating modes:
1.
Chip enabled, transparent, powered up - normal mode where the power down
input is effectively a chip enable with the ICC reduction function.
2.
Chip enabled, latched, power up - this is normal latched mode where the outputs remain latched regardless of address and chip enable switching.
3.
Chip enabled, latched, power down - this is' the powered down latched mode
where the output data remains latched while power is reduced to 50% of its
nominal value. Ifthe latch strobe changes state while in this mode, the outputs
will go to a high impedance state and power will reduce to 30% of nominal
power. This is because the PO input becomes an effective chip enable in the
Transparent Mode.
4.
Chip disabled, transparent, power down - this is the normal powered down
mode where the outputs are in a high impedance state and the power is reduced to 30% of the nominal power.
On the following page is a table to clarify the operational interdependencies.
2-71
PIN NAMES
AO-Ag Address Inputs
0,-08 Data Outputs
CE"
CE2
PO
Chip Enable Inputs
Power Down Input
STH Strobe Input
logic Symbol
TRUTH TABLE for HM-7680RP/81RP
PO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
STR
CE2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
cE,
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
POWER'
OUTPUTS
Latched Data
Latched "Three State"
Latched "Three State"
Latched "Three State'~',
Unlatched "Three state"
Unlatched "Three State"
Unlatched '''Three State"
Unlatched "Three State"
Latched Data'
Latched "Thrfl8 State"
Latched "Three State"
Latcha<;! "Th ree State"
Unlatched Data
Unlatched ''Three State"
Unlatched ''Three State"
Unlatched, "Three State"
50%
5'0%
50%
50%
30%
30%
30%
30%
'100%
100%
100%
100%
100%
100%
100%
100%
"
Assume that t,l\e sequence 'of transitions is: 1) Chip Enabl~s, 2) STR, 3) PO
and the initial stata isUnl,atched Data.
Functional Diagram
8192 BIT
MEMORY
ARRAY
NOTE: PhvIlCll Bit PoIItIom
for CoIUIIIIII .,. • FIIIIOWI:
0,.03, Os. 07- 0-1&
D2. 04,
oe.
08-,0-1&,0-14
• • • • • • • • • • • •
128 l:RANSMISSION GATES
OUTPUT BUFFERS
Specifications HM-7680RP181RP
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to +150o C
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
+175 0 C
Output ~r Supply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
Address/Enable Input Current
-20mA
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may caule permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming. follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7680RP/81 RP-5 (VCC = 5.0V ± 5%, TA = ooC to +75 0 C)
HM-7680RP/81 RP-2 (VCC = 5.0V± 10%, TA = -55 0 Cto +125 0 C)
Typical measurements are at T A = 25 0 C. Vce= +5V
~NITS
SYMBOL
PARAMETER
MIN
TYP
MAX
IIH
ilL
Address/Enable "1"
"0"
Input Current
-
-50.0
+40
-250
JlA
JlA
VIH - Vc';C Max.
VIL = 0.45V
VIH
Vil
I nput Threshold' "1 "
Voltage
"0"
2.0
1.5
1.5
O.S
V
V
VCC = VCC Min.
VCC = VCC Max.
VOH
Val
Output
Voltage
3.2"
0.35
0.50
V
V
10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCC Min.
10HE
10LE
Output Disable "1"
"0"
Current
-
"1"
"0"
2.4"
-
-
-
+40
-40'
JlA
JlA
TEST CONDITIONS
VOH, VCC = VCC Max.
Val = 0.3V, VCC = VCC Max.
VCl
Input Clamp Voltage
-
-
-1.2
V
las
Output Short Circuit
-15'
-2.S
-100'
mA
VOUT= O.OV, One Output at a
Time for a Max. of 1 Second
ICC
Power Supply Current
-
120
170
mA
VCC = VCC Max., All Inputs
Grounded.
liN = -ISmA
Current
NOTE: Positi,ve current defined as Into device terminals.
'''Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7680RP/81 RP-S
SV'± 5%
ooC to +7So C
HM-7680RP/81 RP-2
5V'± 10%
-S50C to + 12SoC
SYMBOL
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TAA
TDA
TEA
TpU
Address Access Time
Chip Disable Access Time
Chip Enable Access Time
Chip Power-Up Access Time
-
-
60
40
40
100
-
-
4S
30
30
80
-
-
SO
SO
SO
ISO
ns
ns
ns
ns
0
10
30
60
-10
0
10
40
-
0
10
40
80
-10
0
10
40
-
40
-
ns
ns
ns
ns
ns
ns
TADH
TCDH
TSW
TSL
TDL
TCDS
Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Time
Strobe Delatch Time
Chip Enable Set-Up Time
-
40
-
-
SO
-
-
SO
-
TESTCOND.
latched or
Transparent
latched Only
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
CINA, CINCE
COUT
PARAMETER
I nput Capacitance
Output Capacitance
MAXIMUM
UNITS
S
pF
VCC
= 5V,
VIN = 2.0V, f - lMHz
10
pF
VCC
= 5V,
VOUT = 2.0V, f = lMHz
2-73
TEST CONDITIONS
SWITCHING TIME DEFINITIONS (Transparent Model
_ _ _ _ _"' , _ _ _ _ _ _ _ _ VIH
ADDRESSES
1.5V
Vil
,----VOH
VOL OUTPUTS-----r--f'-____+-__~
-+___~~I~V
OUTPUTS _ _ _ _ _
~
TAA
TDA
NOTE: Strobe input must remain high throughout read cycle while in transparent mode.
SWITCHING TIME DEFINITIONS (Latched Model
ADDRESS ~
----
...,
1.5V
CHIP ENA BlES
---------
TADtI-
-TCDS
CE1,CE2, PO
1.5V
~~1.5V
j1;,.,1.5V
f--TSW
TCD--
TCDH
VIH
1.5V
Vil
.,----,.
1.5V
1.5V
STROBE
1.5V
-
TSl
1.5V
OUTPUTS
TAA
A.C. TEST LOAD
PROM
OUTPUT
OXO-----<~-....--O
TEST POINT
30pF*
* Includes Jig
and Probe Total
Capacitance
2-74
TDl
.......
r-T.S.
T.S.
m
HM-7683
SEMICONDUCTOR
HARRIS
PRODUCTS DIVISION
1K
A DIVISION OF HARRIS CORPORATION
MARCH 1978
8 PROM
Active Pull-up Outputs
Preliminary
Features
Pinouts
TOP VI EW - DIP
•
60ns MAXIMUM ADDRESS ACCESS TIME
•
SIMPLE, HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
X
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
•
LOW PIN COUNT FOR MAXIMUM DENSITY
Description
The HM-7683 is a fully decoded high speed Schottky TTL 8192-Bit
Field Programmable ROM in a 1 K word by 8 bit/word format and is
available in a 20 pin DIP (ceramic or epoxy) and a 20 pin flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can
be selectively programmed for a logical "0" in any bit position.
AO
VCC
A1
AS
A2
A7
A3
AS
A4
A5
0,
Ag
02
Os
03
07
04
Os
GND
05
TOPVIEW-FLATPACK.
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs.
The HM-7683 contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parameterics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
Functional Diagram
~r-----------------------,
PIN NAMES
AO - Ag
01 - Os
Address Outputs
Data Outputs
S192BIT
MEMORY
ARRAY
Logic Symbol
10F64
ROW
NOTE: Physical Bit Potition.
For Columns An AI Follows:
AS
Ag
01,03, Os, 07--(0--151
OZ, 04. 06, Os --116, 0--141
...................
128 TRANSMISSION GATES
A2
2-75
Specifications HM-7683
.4BSOLUTE MAXIMUM RATINGS
Output or· Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
100mA
Storage Temperature
-650C to +1500C
Operating Temperature (Ambient) -550C to +1250C
Maximum Junction Temperature
+1750 C
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" mllY caUse pe;manent damage to the device. These
are stress only ratings and functional operation of the device at these or .at any other conditions above those indicated in the operational
sections 0.' this specification is not implied. (While programming, fol/o,w the programming specifications.)
.
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
PARAMETER
MiN
TYP
MAX
UNITS
-
-50.0
+40
-250
IlA
IlA
VIH = VCC Max.
Vll=0.45V
1.5
1.5
0.8
V
V
Vec = VCC Min.
Vee·= Vee Max.
3.2
0.35
0.50
V
V
10H = -2.0mA, VCC = VCC Min.
IOl = +16mA, VCC = Vec Min.
-
-1.2
V
-15
-100
mA
VOUT = O.OV, One Output at a
Time for a Max. of. 1 Second
-
130
170
mA
vee = VCC Max., All Inputs
Grounded .
IIH
IlL
Address Input
Current
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
Outpu't
Voltage
2.4
VOH
.' VOL
"1"
"0"
-
"1"
"0"
Vel
Input Clamp Voltage
lOS'
Output Sh'ort Circuit
Current
ICC
Power Supply Current
HM-7683:"5 (VCC = 5.0V ± 5%, TA= 0 0 to +750 C)
HM-7683-2 (Vec = 5.0V ± 10%, TA '" -550 C to +1250 C)
Typical Measurements are at T A " 250 C, VCC = +5V
-
-
..
.
TEST CONPITIONS
liN = -lBmA
'
NOTE: POSitive current defined as Into deVice termmals .
. A.C. ELECTRICAL CHARACTERISTICS (Operating)
I SYMBOL I
I
TAA
PARAMETER
I Address Acce", Time
HM-7683~5
HM~7683-2
5V±5"
DoC to +75OC
5V ±lD%
-S5GC to + 1250 C
MIN
I
TYP
I
MAX
.MIN
I
TYP
I
MAX
UNITS
I
-
I
45
I
60
-
I
-
I
80
ns
I
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE:TA
SYMBOL
=
25 0 C
PARAMETER
'"
MAXIMUM
UNITS
CINA
Input Capacitanoe
8
pF
COUT
Output Capacitance
10
pF
2-76
TEST CONDITIONS
Vee = 5V, VIN = 2.0V, f = lMHz
.'
Vec
= 5V, VOUT = 2.0V, f
= lMHz
SWITCHING TIME DEFINITIONS
--------"'1,...------- VIH
ADDRESSES _ _ _ _ _ _J-: ~ 1.6V
-----+---,
OUTPUTS
------~---/
VIL
,---VOH
r:=1.6V
VOL
TAA
A.C. TEST LOAD
Vee
PROM
OUTPUT
Ox o--~~-....-o TEST POINT
30pF*
-Includes Jig
and Probe Total
Capacitance
2-77
m
HM-7684/85
I-lARRiS
2K
SEMICONDUCTOR
PRODUCTS DIVISION
,
A DIVISION OF HARRIS CORPORATION
4 PROM
HM-7684 - Open Collector Outputs
HM-7685- "Three State" Outputs
MARCH 1978
Pinouts
Features
•
60n5 MAXIMUM ADDRESS ACCESS. TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND A CHIP ENABLE
INPUT
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY
TOP VIEW - DIP
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOL TAGE RANGES
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
Description
The HM-76B4/85 are a fully decoded high speed Schottky TTL 8192Bit Field Programmable ROM in a 2K wordbya 4 bit/word format with
open collector (HM-7684) or "Three State" (HM-7685) outputs. These
PROMs are available in an 18 pin DIP (ceramic or epoxytand an 18 pin
flatpack.
All bits are manufactured storing a logical "1 "(positive logic) and can be
selectively programmed for a logical "0" in any bit position.
•
X
A6
VCC
AS
A7
A4
AS
A3
As
AO
°1
A1
°2
A2
03
A10
°4
GND
IT
TOP VIEW - FLATPACK
Nichrome fuse technology is used on this and all other Harris Bipolar
PROMs .
The HM-7684/85 contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There is a chip enable on the HM-7684/85.
CE low enables the chip.
PIN NAMES
Functional Diagram
AO - A10 Address Inputs
01 - 04 Data Outputs
CE Chip Enable Input
8192 BIT
MEMORY
logic Symbol
ARRAY
I ) '" Pin Numbers
1181' Vee
(91- GND
128 TRANSMISSION GATES
31
31
2-78
Specifications HM-7684/85
ABSOLUTE MAXIMUM RATINGS
..
Storage Temperature
-65 0 e to +150 oe
Operating Temperature (Ambient) -55 0 e to +125 0 e
+175 0 e
Maximum Junction Temperature
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
-20mA
Address/Enable Input Current
Output Si nk Current
100mA
CAUTION: Stresses above those lisred under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
PARAMETER
MIN
TYP
IIH
IlL
Address/Enable "1"
Input Current
"0"
-
-
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
VOH
VOL
Output
Voltage
2.4·
10HE
IOLE
Output Disable "1"
"0"
Current
VCL
Input Clamp Voltage
lOS
Output Short Circuit
Current
ICC
Power Supply Current
TEST CONDITIONS
MAX
UNITS
-50.0
+40
-250
fJ.A
fJ.A
VIH
VIL
= VCC Max.
= 0.45V
1.5
1.5
.0.8
V
V
VCC
VCC
= VCC Min.
= VCC Max.
3.2"
0.35
0.50
V
V
10H = -2.0mA, VCC = VCC Min.
IOL = +16mA, VCC = VCC Min.
+40
-40·
fJ.A
fJ.A
-
"1"
"0"
HM-7684/85-5 (Vee = 5.0V ± 5%, TA = ooe to +75 0 e)
HM-7684/85-2 (Vee = 5.0V ± 10%, TA = -55 0 e to +125 0 e)
Typical measurements are at T A = 250 e, Vee = +5V
-
-
-
-1.2
V
-15"
-
-100'
rnA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
-
120
170
rnA
VCC = VCC Max., All Inputs
Grounded.
VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
liN
= -18mA
NOTE: Positive current defined as into device terminals.
'''Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7684/85-5
5V:!:5%
(JOc to + 750C
PARAMETER
HM-7684/85-2
5V:!: 10%
-550C to +125OC
MIN
TYP
MAX
MIN
TYP
MAX
TAA
Address Access Time
-
45
60
-
-
80
ns
TEA
Chip Enable Access Time
-
30
40
-
-
50
ns
SYMBOL
UNITS
A.C. limits guaraineed for worst case N2 sequencing.
CAPACITANCE: TA = 25 0 e
SYMBOL
CINA, CINCE
COUT
PARAMETER
MAXIMUM
,
I nput Capacitance
8
Output Capacitance
10
2-79
UNITS
TEST CONDITIONS
pF
VCC
= 5V,
VIN
pF
VCC
= 5V,
VOUT
= 2.0V, f = 1MHz
= 2.0V, f = 1MHz
•
SWITCHING TIME DEFINITIONS
ADDRESSES
CE
VIH
--i ~1.5V
VIH
CHIP ENABLES
VIL
VOH
OUTPUTS
OUTPUTS
TAA
VOL
r='
A.C. TEST LOAD
VCC
PROM
OUTPUT
TEST POINT
Ox
60012
30pF*
* Includes Jig
and Probe Total
Capacitance
•
2-80
T.S.
m
HM-7684P/85P
HARR1S
SEMICONDUCTOR
PRODUCTS DIVISION
2K
X
4 PROM
A DIVISION OF HARRIS CORPORATION
MARCH 1978
HM-7684P - Open Collector Outputs
HM-7685P - "Three State" Outputs
w
. Features
Pinouts
•
60ns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND A POWER DOWN
INPUT
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY
TOP VIEW - DIP
A6
VCC
A5
A7
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVEB COMMERCIAL AND MILITARY TEMP. AND VOLT. RANGES
A4
AS
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
A3
Ag
AD
01
A1
02
A2
03
A.10
04
D(Jscliption
The HM-7684P/85P are fully decoded high speed Schottky TTL 8192Bit Field Programmable ROMs in a 2K words by 4 bit/word format with
open collector (HM-7684P) or "Three State" (HM-7685P) outputs. These
PROMs are available in an 18 pin DIP (ceramic or epoxy) and an 18 pin
flatpack.
PD
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrome fuse technology is used on these and all other Harris Bipolar
PROMs.
The HM-7684P/85P contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
a
There is a power down input on the HM-7684P/85P which is similar to
chip enable. The chip is enabled or disabled using the power down input
where a disabled chip dissipates 30% of nominal power and the outputs go
to a high impedance state. The chip is powered up (enabled) wh&n PDl
is low.
Functional Diagram
~r-------------------------,
TOP VIEW - FLATPACK
A6=7~""---:;~=::::I
A5
A4
A3
AD
A1
A2
A10
VCC
A7
AS
Ag
01
02
03
04
GNO
PO
PIN NAMES
AO - A 1 0
01 - 04
PO
Address Inputs
Data Outputs
Power Down Input
8192 BIT
MEMORY
ARRAY
logic Symbol
AS
( ) - Pin Numbert
(181- Vee
(9)
=
GND
128 TRANSMISSION GATES
31
31
2-81
I
Specifications 7684PI85P
ABSOLUTE MAXIMuM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable I nput Voltage
5.5V
-20mA
Address/Enable I nput Current
100mA
Output Sink Current
Storage Temperature
-65 0 e to +150 0 e
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
+175 oe
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
N
sections of this specification is not implied. (While programming, follow the programmingspecifications.)
HM-7684P/85P-5 (Vee = 5.0V ± 5%, TA = ooe to +75 0 e)
HM-7684P/85P-2 (VCC 5.0V ± 10%, T A = -55 0 C to +125 0 C)
Typical measurements are at TA = 25 0 C, VCC = +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
II
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
IlL
AddresslEnable "'"
"0"
I nput current
-
-50.0
+40
-250
P.A
P.A
VIH
VIL
VIH
VIL
Input Threshold "'"
Voltage
"0"
2.0
-
1.5
1.5
0.8
V
V
Vee
Vee
VOH
VOL
Output
Voltage
"1"
"0"
3.20.35
0.50
V
V
10HE
10LE
Output Disable
Current
"1"
"0"
2.4 •
-
-
TEST CONDITIONS
= Vee Max.
= 0.45V
= Vee Min.
= Vee Max.
10H = -2.0mA, Vee = vee Min.
10L = +16mA, Vee = vee Min.
Vel
Input Clamp Voltage
-
-
-1.2
V
lOS
Output Short Circuit
-15-
-
-100-
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
-
120
170
mA
vee = vee Max., All Inputs
Grounded.
+40
-40·
VOH,Vee = Vee Max./
VOL = 0.3V, Vee = Vee Max.
P.A
P.A
liN
Current
ICC
Power Supply Current
= -18mA
NOTE: Positive current defined as into device terminals.
-"Three State" only
A.C. EL.ECTRICAL CHARACTERISTICS (Operating)
HM-7684P/85P-5
5V±5%
ooC to +750 C
SYMBOL
PARAMETER
Address Access Time
Chip Power Down
Access Time
Chip Power-Up Access Time
TAA
TpD
TpU
MIN
-
HM-7684P/85P-2
5V'± 10%
-550 C to + 1250 C
TYP
MAX
MIN
TYP
45
60
30
40
80
100
-
-
MAX
UNITS
80
ns
50
ns
150
ns
A.C. ,limits guaranteed for worst case N2 sequencing.
CAPACITANCE: TA = 25 0 C
SYMBOL
CINA, CINCE
eOUT
MAXIMUM
UNITS
Input Capacitance
PARAMETER
8
pF
Vee ",5V, VIN
Output Capacitance
10
pF
Vce
2-82
TEST CONDITIONS
= 5V.
= 2.0V, f = lMHz
VOUT
= 2.0V. f = lMHz
SWITCHING TIME DEFINITIONS
PO
POWEROOWN
VIH
ADDRESSES
1.5V
VIL
OUTPUTS
-----+--_../
TAA
VIH
.1.5V
._---.------ V.lL
VOH
rV
VOL
OUTPUTS
T.S.
A.C. TEST LOAD
vee
PROM
OUTPUT
Ox D---t---.-OTEST POINT
soon
30pF*
* Includes Jig
and Probe Total
Capacitance
I
2-83
HM-7686/87
w~~~
2K
PRODUCTS DIVISION
X
4 PROM
A DIVISION OF HARRIS CORPORATION
HM-7686 - Open Collector Outputs
HM-7687- "Three State" Outputs
APR/L.T978
Features
Pinouts
•
60')5 MAXIMUM ADDRESS ACCESS TIME.
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND THREE CHIP
ENABLE INPUTS.
•
SIMPLE HIGH· SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
A4
Al0
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
A3
01
A2
02
AI
03
AO
04
TOP VIEW - DIP
A7
VCC
AS
AS
Ae
Description
The HM-7686/87 are fully decoded high speed Schottky TTL 8192-Bit
Field Programmable Roms in a 2K word by 4 bit/word format with open
collector (HM-7686) or "Three State" (HM-7687) outputs. These PROMs
are available in a 20 pin DIP (ceramic or epoxy) and a 20 pinflatpack.
CE2
All bits are manufactured storing a.logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
CE3.
Njchrome fuse technology is used on these and all other Harris Bipolar
PROMs.
TOP VIEW - FLATPACK
The HM-7686/87 contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in test rows and columns are
blown prior to shipment.
There are three chip enable inputs on the HM-7686/87; eEl. CE2. and
CE3 low enables the chip.
Functional Diagram
~r---------------------~
A7C:~~==~~==~~VCC
AS
AS~
A5
A4
Aa
A2
AI
AO
CEI
GND
Ae
~O
01
02
Oa
04
CE2
CEa
PIN NAMES
AO - A10 Address Inputs
01 - 04 Data Outputs
CE1. CE2. CE3 Chip Enable Inputs
8192 BIT
MEMORY
ARRAY
logic Symbol
A5
128 TRANSMISSION GATES
31
31
CE,">..!:o..r----.
CE2
CE3~.........:c:..:,-,-,
2-84
Specifications 7686/87
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to +1500C
Operating Temperature (Ambient) -55 0 C to +1250 C
+175 0 C
Maximum Junction Temperature
Output or Supply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
Address/Enable Input Current
-20mA
Output Sink Current
100mA
CAUTION: Suesses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
HM-7686/87-5 (VCC = 5.0V ± 5%. T A = DoC to +75 0 C)
HM-7686/87-2 (VCC = 5.0V ± 10%, TA = -550 C to +1250 C)
Typical measurements are at T A = 250 C, VCC :; +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
TEST CONDITIONS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
III
Address/Enable "1"
Input Current
"0"
-
-50.0
+40
-250
JJ.A
JJ.A
VIH
Vil
= VCC Max.
= 0.45V
VIH
Vil
Input Threshold "1"
Voltage
"0"
2.0
1.5
1.5
O.S
V
V
VCC
VCC
= VCC Min.
= VCC Max.
VOH
VOL
Output
Voltage
2.4"
3.2"
0.35
0.50
V
V
10H = -2.0mA, VCC = VCC Min.
10l = +16mA. VCC = VCC Min.
10HE
10lE
Output Disable "1"
Current
"0"
-
"1"
"0"
-
-
-
-
-
+40
-40
VOH. VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
JJ.A
JJ.A
*
VCl
Input Clamp Voltage
-
V
Output Short Circuit
Current
-15'
-
-1.2
lOS
-100'
rnA
VOUT = O.OV. One Output at a
Time for a Max. of 1 Second
ICC
Power Supply Current
-
120
170
mA
VCC = VCC Max .• All Inputs
Grounded.
liN
= -1SmA
NOTE: Positive current defined as into device terminals.
'''Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7686/87-2
5V'± 10%
-550C to + 1250 C
HM-7686/87-5
5V.± 5%
OOC to +750 C
MIN
TYP
MAX
TAA
Address Access Time
PARAMETER
-
45
60
~
TEA
Chip Enable Access Time
-
30
40
-
SYMBOL
MIN
TYP
MAX
UNITS
-
SO
ns
50
ns
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 250 C
SYMBOL
CINA. CINCE
COUT
MAXIMUM
UNITS
I nput Capacitance
S
pF
VCC
= 5V.
VIN
Output Capacitance
10
pF
VCC
= 5V.
VOUT
PARAMETER
2;..85
TEST CONDITIONS
= 2.0V. f = 1MHz
= 2.0V. f = 1 MHz
I
SWITCHING TIME DEFINITIONS
CE1. CE2 & CE3
-----""'\.I,..--------VlH
ADDRESSES _ _ _ _ _J-: ~1.5V
r
------+--~ ,..----VOH
0"""""
TAA
CHIP ENABLES
VIL
VOC
00.".""
T.S.
A.C. TEST LOAD
PROM
OUTPUT
Ox Q----<..--_-.() TEST POINT
30pF*
* Includes Jig
and Probe Total
Capacitance
I
2-86
1.5V
'-"-----.-.VIL
m
HM-7686R/87R
HARRIS
2K x 4 PROM
SEMICONDUCTOR
PRODUCTS DIVISION
... DIVISION 0' HARRIS CORPORATION
HM-7686R - Open Collector Outputs
HM-7687R - "Three State" Outputs
Preview
APR/L 1978
Features
Pinouts
•
60ns MAXIMUM ADDRESS ACCESS TIME
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND TWO CHIP
ENABLE INPUTS
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY
TOP VIEW-DIP
A7
VCC
AS
AS
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES
AS
Ag
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD
A4
AlO
•
LATCHED OUTPUTS
A3
01
A2
°2
•
Description
The HM-7686R/87R are fully decoded high speed Schottky TTL 8192ait Field Programmable ROMs in a 2K words by 4 bit/word format with
apen collector (HM-7686R) or "Three State" (HM-7687R) outputs.
These PROMs are available in a 20 pin DIP (ceramic or epoxy) and 20 pin
flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrome fuse technology is used on these and all other Harris Bipolar
f>ROMs.
Al
03
AO
04
CEI
CE2
GND
STR
TOP VIEW-FLAT PACK
The HM-7686R/87R contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There are two chip enable inputs on the HM-7686R/87R.
low enables the chip.
I
CE1, CE2
The HM-7686R/87R is operated in the Transparent Read Mode by holding the strobe input low throughout the read operation. This is the normal read mode where the two chip enable inputs will control the outputs.
In Latched Read Mode, bringing the strobe input high will latch the outputs and chip enable inputs. If the device is disabled when the strobe
input goes high, the outputs will be latched in the high impedance state.
If the device is in the latched mode, the strobe input must be brought low
to allow the outputs to respond to new address or chip enable conditions.
Ao-A,a
0,-04
CE1.
CE2
Address Inputs
Data Outputs
Chip Enabla Inputs
§'T'R Strobe Input
Functional Diagram
Logic Symbol
CEI
CE2
STR
AO
Al
A2
A3
A4
A5
A6
A7
AS
Ag
Al0
.
..
..
A,
A,
..
.
2-87
°1
02
03
04
Specifications HM-7686R/87R
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
100mA
Storage Temperature
-65 0 C to +1500 C
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
+175 0 C
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)
HM-7686R/87R-5 (VCC = 5.0V.;t 5%, TA = OOC to +75 0 C)
HM-7686R/87R-2 (VCC = 5.0V.;t 10%, T A = -550 C to +125 0 C)
Typical measurements are at T A = 25 0 C, VCC = +5V
D.C. ELECTRICAL CHARACTERISTICS (Operating)
I
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
IlL
AddresslEnable """
"a"'
Input Current
-
-50.0
+40
-250
J.1A
J.1A
VIH
VIL
Input Threshold "1"
Voltage
"0"'
2.0
-
1.5
1.5
O.B
V
V
VCC
VCC
VOH
Val
Output
Voltage
3.2'
0.35
-.
0.50
V
V
10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCCMin.
10HE
10lE
Output Disable "'1"
Current
"0"
2.4 •
"1"'
"0"'
-
-
+40
TEST CONDITIONS
VIH = VCC Max.
VIL=0.45V
VOH, VCC = VCC Max.
Val = 0.3V, VCC = VCC Max.
J.1A
J.1A
-40·
= VCC Min.
= VCC Max.
= -lBmA
VCl
Input Clamp Voltage
-
-
-1.2
V
las
Output Short Circuit
Current
-15'
-2.5
-lOa'
mA
VOUT = a.ov, One Output ota
Time for a Max. of 1 Second
ICC
Power.'SupplY Current
-
120
170
mA
VCC = VCC Max., All Inputs
Grounded.
liN
NOTE: Positive current defined as into device terminals.
*"Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7686R/87R-5
5V±5%
ooC to .+ 750 C
HM-7586R/87R-2
5V ± 10%
-550C to +125°C
SYMBOL
PARAMETER
MIN
TYP
MAX
MIN
TYP
TAA
TEA
Address Access Ti me
Chip Enable Access Time
-
45
30
60
40
-
-
-
BO
50
ns
ns
latched or
Transparent
TADH
TCDH
TSW
TSl
TOl
TCDS
Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Time
Strobe Oelatch Time
Chip Enable Set-Up Time
0
10
30
60
-10
0
10
40
0
10
40
80
-10
0
10
40
-
40
-
-
ns
ns
ns
ns
ns
ns
Latched Only
-
-
-
40
-
50
MAX
50
-
UNITS
TEST CONDIT.
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
CINA, CINCE
COUT
PARAMETER
MAXIMUM
UNITS
Input Capacit.ance
8
pF
VCC
= 5V,
Output Capacitance
10
pF
VCC
=
2-88
TEST CONDITIONS
VIN
= 2.0V, f = lMHz
5V, VOUT
=
2.0V, f = lMHz
SWITCHING TIME DEFINITIONS (Transparent Model
------~r----------VIH
..., '<-l.SV
ADDRESSES
OUTPUTS
. " . - - - - VIH
,_1~~~ _____ VIL
VIL
r----VOH
VOL OUTPUTS
T.S.
-----+-_./ ~SV
TEA NOTE: Strobe input must remain low throughout read cycle while in transparent mode.
SWITCHING TIME DEFINITIONS (Latched Model
ADDRESSES.~
..,
1s.1.SV
f--TCDS
eEl.CE2
CHIP ENABL ES
-;
---- ---_ ...... _-'
1.SV
----------
TADH-
Kt.5V--------- --------------;~V~
f-Tsw
1.SV~
{1.5V
-
I(1.SV
TAA
A.C. TEST LOAD
VCC
PROM
OUTPUT
TCD--
TCDH
TSL
OUTPUTS
,-----_ .... __ ... .; .... -
Ox o---..........--_-Q TEST POINT
30pF*
600n
* Includes Jig
and Probe Total
Capacitance
2-89
'"
VIH
1. SV
VIL
1.SV
TDL
"-
lT.S.
I
HARRIS
HM-7686P/87P
SEMICONDUCTOR
PRODUCTS DIVISION
2K.x 4 PROM
A DIVISION OF HARRtS CORPORATION
HM-7686P - Open Collector Outputs
HM-7687P - "Three State" Outputs
APRIL 1978
Features
Pinouts
•
60ns MAXIMUM ADDRESS ACCESS TIME.
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND THREE POWER
DOWN INPUTS.
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
•
TOP VIEW - DIP
FAST ACCESS TIME - FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
Description
The HM-7686P/87P are fully decoded high speed Schottky TTL 8192-Bit
Field Programmable ROMs in a 2K word by 4 bit/word format with open
collector (HM-7686P) or "Three State" (HM-7687P) outputs. These
PROMs are available in a 20 pin DIP (ceramic or epoxy) and a 20 pin
flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nichrorr>e fuse technology is used on these and all other Harris Bipolar
PROMs.
The HM-7686P/87P contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametrics.and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There are three power down inputs on the HM-7686P/87P which are similar to chip enables. The chip is enabled or disabled using the power down
inputs where a disabled chip dissipates 30% of nominal power and the outputs go to a high impedance state. The chip is powered up (enabled) when
PD1. PD2 and PD3 are low.
Functional Diagram
Vee
A7
AS
AS
AS
Ag
A4
A10
A3
0,
A2
°2
A,
03
Ao
°4
PO,
P02
GNO
P03
TOP VIEW - FLATPACK
A7:::;;:==~Lf==~;:~vee
A6
AS
AS
A4
A3
Ag
A,O
0,
A2
02
A,
03
04
P02
P03
AO
PO,
GNO
63,----________-,
PIN NAMES
AO - A10 Address Inputs
0, - 04 Data Outputs
PD,. PD2. PD3 Power Down Inputs
819281T
MEMORY
ARRAY
logic Symbol
A.
Ao
A.
........
128 TRANSMISSION GATES
3'
31
Aa
...
PO,
PD2
"".
2:..90
PO,
P02
P03
AO
A,
A2
0,
A3
A4
AS
A6
A7
AS
Ag
A10
°2
03
°4
Specifications HM-1686P/81P
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
-20m A
Address/Enable Input Current
Output Sink Current
100mA
-65 0 C to +150 0 C
Storage Temperature
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
+175 0 C
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
N
sections of this specification is not implied. (While programming, follow the programming specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7686P/87P-5 (VCC; 5.0V ± 5%, TA ; ooC to +75 0 C)
HM-7686P/87P-2 (VCC ; 5.0V ± 10%, T A; -55 0 C to +125 0 C)
Typical measurements are at T A; 25 0 C, VCC ; +5V
PARAMETER
MIN
TYP
MAX
UNITS
IIH
ilL
Address/Enahle "1"
-
"0"
-
-50.0
+40
-250
J1A
J1A
VIH = Vee Max.
VIL = 0.45V
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
-
1.5
1.5
0.8
V
V
Vee = Vee Min.
Vee = vee Max.
VOH
VOL
Output
Voltage
"1"
"0"
2.4 •
-
3.2*
0.35
0.50
V
V
10H = -2.0mA, Vee = Vee Min.
10L = +16mA, Vee = vee Min.
10HE
10LE
Output Disable
"1"
"0"
-
-
+40
-40 •
J1A
J1A
SYMBOL
Input Current
Current
TEST CONDITIONS
VOH, Vee = Vee Max.
VOL = 0.3V, Vee = Vee Max.
= -13mA
VeL
Input Clamp Voltage
-
-
-1.2
V
lOS
Output Short Circuit
Current
-15"
-
-100*
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
lee
Power Supply Current
-
120
170
mA
Vee = Vee Max., All Inputs
Gr0unded.
liN
NOTE: Positive current defined as into device terminals.
*"Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7686P/87P-2
5V ± 10%
-55 0 C to + 1250 C
HM-7686P/87P-5
5V±5%
OOC to +750 C
PARAMETER
SYMBOL
TAA
TpD
TpU
Address Access Time
Ch ip Power Down Access Time
Chip Power-Up Access Time
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-
45
60
40
-
-
80
ns
50
ns
150
ns
30
30
-
100
-
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A; 25 0 C
SYMBOL
eINA, CINeE
eOUT
PARAMETER
MAXIMUM
UNITS
Input Capacitance
8
pF
Vee
Output Capacitance
10
pF
Vec = 5V, VOUT = 2.0V, f
2-91
TEST CONDITIONS
~
5\1, IIIN = 2.0V, f
= 1 MHz
= 1 MHz
E
SWITCHING TIME DEFINITIONS
VIH
ADDRESSES
OUTPUTS
-----"
1.5V
-----+---"
TAA
VIL
F
1•5V
PD1. PD2. PD3
POWERDOWNS
-------,
VOH
VOL
T.S.
OUTPUTS
A.C. TEST LOAD
PROM
OUTPUT
OxO--~~-""-O TEST POINT
30pF*
* Includes Jig
and Probe Total
Capacitance
I
2-92
HARRIS
HM-7686RP/87RP
SEMICONDUCTOR
PRODUCTS DIVISION
2K
X
4 PROM
A DIVISION OF HARRIS CORPORATION
APR/L 1978
HM-7686RP - Open Collector Outputs
HM-7687RP - "Three State" Outputs
Features
•
Pinouts
SOns MAXIMUM ADDRESS ACCESS TIME.
•
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND A CHIP ENABLE INPUT.
•
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT. ASSURES
FAST PROGRAMMING AND SUPERIOR RELIABILITY.
•
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER
COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
•
INDUSTRY'S HIGHEST PROGRAMMING YIELD.
•
LATCHED OUTPUTS.
•
A POWER DOWN INPUT ALLOWING 70% REDUCTION IN NOMINAL POWER DISSIPATION.
TOP VIEW-DIP
Description
The HM-7686RP/87RP are fully decoded high speed Schottky TTL 8192-Bit
Field Programmable ROMs in a 2K words by 4 bit/word format with open collector
(HM-7686RP) or "Three State" (HM-7687RP) outputs. These PROMs are available in a 20 pin DIP (ceramic or epoxy) and a 20 pin flatpack.
A7
VCC
AS
AS
A5
Ag
A4
A10
A3
01
A2
02
A1
03
04
CE
PO
STR
GND
All bits are manufactured storing a logical "1" (positive logic) and can be selectively
programmed for a logical "0" in any bit position.
Nichrome fuse technology is used on these and all other Harris Bipolar PROMs.
The HM-7686RP/87RP contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametrics and
A.C. performance. The fuses in these test rows and columns are blown prior to
shipment.
There is a chip enable input on the HM-7686RP/87RP. CE low enables the device.
There is also a power down input on this device. A powered down device has 70%
reduction in nominal power dissipation if the outputs are not latched and 50% reduction in nominal power if the outputs are latched.
The HM-7686RP/87RP is operated in the Transparent Read Mode by holding the
the strobe input low and the PD input low throughout the read operation. This is
the normal read mode where the chip enable and the power down input will control
the outputs.
In Latched Read Mode, bringing the strobe input high will latch the outputs and
the chip enable input. However, the power down input is independent of the latch
function and can be changed while in the latched mode. If the device is disabled
when the strobe input goes high, the outputs will be latched in the high impedance
state. If the device is in the latched mode, the strobe input must be brought lowto
allow the outputs to respond to new address or chip enable conditions.
The following is a summary of the functional dependencies of the operating modes:
1.
Chip enabled, transparent, powered up - normal mode where the power down
input is effectively a chip enable with the ICC reduction function.
2.
Chip enabled, latched, power up - this is normal latched mode where the output remains latched regardless of address and chip enable switching.
3.
Chip enabled, latched, power down - this is the powered down latched mode
where the output data remains latched while power is reduced to 50% of its
nominal value. If the latch strobe changes state while in this mode, the outputs
will go to a high impedance state and power will reduce to 30% of nominal
power. This is because the PO input becomes an effective chip enable in the
Transparent Mode.
4.
Chip disabled, transparent, power down - this is the normal powered down
mode where the outputs are in a high impedance state and the power is reduced to 30% of the nominal power.
On the following page is a table to clarify the operational interdependencies.
2-93
TOP VIEW-FLATPACK
A7
AS
A5
A4
A3
A2
A1
AO
Vec
AS
Ag
A10
01
02
03
04
PO
STR
CE
GND
AO-A10
01-0 4
PO
STR
CE
PIN NAMES
Address I"puts
Data Ouputs
Power Down Input
Strobe Input
Chip Enable Input
logic Symbol
I
TRUTH TABLE for HM-7686RP/87RP
PD
STR
CE
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
POWER
OUTPUTS
Unlatched Data
Unlatched "Three State"
Latched Data
Latched "Three State"
Unlatched "Three State"
Latched Data
Latched "Three State"
100%
100%
100%
100%
30%
50%
50%
Assume that the sequence of transitions is: 1) Chip Enable, 2)
3) PO, and the initial state is Unlatched Data.
STR,
Functional Diagram
63
~:::J=~-l
I
1 OF 64
8192 BIT
MEMORY
ARRAY
ROW
DECODE
o
•
128 TRANSMISSION GATES
o
••
OUTPUT
BUFFE~
2-94
0
..
31
OUTPUT
BUFFER
0
31
o
31
••
••
OUTPUT
BUFFER
OUTPUT
BUFFER
Specifications HM-7686RP187RP
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to +150 o C
Operating Temperature (Ambient) -550C to +125 0 C
+175 0 C
Maximum Junction Temperature
Output or Supply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
-20mA
Address/Enable Input Current
Output Sink Current
100mA
CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the d.vice at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While progr.mming, follow the programming·specifications.)
D.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7686RP/87RP-5 (VCC = 5.0V + 5%, TA = DoC to +750C)
HM-7686RP/87RP-2 (Vce = 5.0V + 10%, T A = -55 0 C to +125 0 C)
Typical measurements are at T A = 25 0 C, VCC = +5V
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
IIH
IlL
Address/Enable "1"
Input Curfent
"0"
-
-50.0
+40
-250
J.lA
VIH
VIL
Input Threshold "1"
Voltage
"0"
2.0
1.5
1.5
O.B
VOH
VOL
Output
Voltage
3.2'
0.35
0.50
V
V
10HE
10LE
Output Disable "1"
"0"
Current
+40
-40'
J.lA
J.lA
-
2.4 •
-
"1"
"0"
-
-
= Vee Min.
= VCC Max.
10H = -2.0mA, VCC = VCC Min.
10L = +16mA, VCC = VCC Min.
V
V
-
-
VIH = Vce Max.
VIL = 0.45V
J.lA
-
TEST CONDITIONS
Vee
VCC
VOH, VCC = Vce Max.
VOL = 0.3V, VCC = VCC Max.
= -lBmA
VCL
Input Clamp Voltage
-
-
-1.2
V
lOS
Output Short Circuit
Current
-15*
-2.5
-100'
mA
VOUT = O.OV, One Output at a
Time for a Max. of 1 Second
ICC
Power Supply Current
-
120
170
mA
VCC= VCC Max., All Inputs
Grounded.
liN
NOTE: Positive current defined as into device terminals.
*"Three State" only
A.C. ELECTRICAL CHARACTERISTICS (Operating)
SYMBOL
TAA
TOA
TEA
TpU
TAOH
TCOH
TSW
TSL
TOL
TCOS
PARAMETER
Address Access Time
Chip Disable Access Time
Chip Enable Access Time
Chip Power-Up Access Time
Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Time
Strobe Oelatch Time
Chip Enable Set-Up Time
HM-7686RP/87RP-5
5V±5%
OoC to +75 0
MIN
e
HM-7686RP/B7RP-2
5V.± 10%
-550C to + 1250
TYP
MAX
MIN
TYP
MAX
UNITS
60
40
40
100
-
-
-
BO
50
50
150
ns
ns
ns
ns
Latched or
Transparent
-
45
30
30
BO
0
10
30
60
-10
0
10
40
-
-10
0
10
40
40
ns
ns
ns
ns
ns
ns
Latched Only
-
-
-
-
-
-
40
-
-
-
e
-
0
10
40
BO
50
-
-
-
50
-
TESTCOND.
A.C. limits guaranteed for worst case N2 sequencing.
CAPACITANCE: T A = 25 0 C
SYMBOL
CINA, CINCE
COUT
PARAMETER
MAXIMUM
UNITS
I nput Capacitance
B
pF
VCC
= 5V,
Output Capacitance
10
pF
VCC
= 5V, VOUT = 2.0V, f = lMHz
2-95
TEST CONDITIONS
VIN
= 2.0V, f = lMHz
I
SWITCHING TIME DEFINITIONS (Transparent Model.
ADDRESSES
CE,PD
VIH
--; 1I\:1.5V
---_0./
",,---VIH
1.5V
,--------- VIL
VIL
OUTPUTS _____-+ ___- - J
TAA
VOH
~V
OUTPUTs
T.8.
VOL
NOTE: Strobe input mUSt remain low· throughout read cycle while in transparant mode.
SWITCHING TIME DEFINITIONS (Latched Model
ADDRESS ~ s.1.5V
.
VIH
..,
1.5V
- - - - - - - - - - VIL
I---TCDS
TADH-
CE,PD
CHIP ENAB LES
-j
VIH
r--.1.jiV
(1.5V
--TSW
1.5V· /
I
TCO":"-
TCDH
~1.5V
STROBE
1{1.5V
.
TAA
A.C. TEST LOAD
PROM
O.UTPUT
1.5V
1.5V
TSL
OUTPU TS
VIL
-<> TEST POINT
Ox o-----1~-.....
30pF*
* tnct,udes Jig
and Probe Total
Capacitance
2-96·
TDl.
"-
I-T.S.
JAN-0512
HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
512 BIT, BIPOLAR PROM
MIL/M38510/20101
A DIVISION OF HARRIS CORPORATION
MARCH 1978
Features
Pinout
•
FIELD PROGRAMMABLE
•
64 WORDS!8 BITS PER WORD
•
FULLY DECODED
•
DTLiTTL COMPATIBLE
•
TOP VIEW - D.I.P.
SSn5 ACCESS TIME
N.C.
VCC
N.C.
G2'
AO
Description
The JAN-0512 is a field programmable 64 word by 8 bit PROM. In an
unprogrammed memory, all "Memory Elements" are short circuits so that
logical "zeros" appear at each output bit position for any address input.
"Electronic Programming" involves the alteration of specific "Memory
Elements" to create logical "ones" in selected bit positions. This alteration is irreversible and cannot be accomplished under normal operating
conditions.
BO
A1
B1
A2
B2
E1
B3
E2
B4
A3
BS
A4
B6
AS
B]
G1
IC'
N.C.
G2
"Must be left open circuit
E
Block Diagram
OUTPUT BUFFERS
r=-----------
80
A1
4
ADDRESS
A2
MEMORY
ELEMENTS
&
DECODING
MATRIX
ENABLE
·IC - Internal Connection mUlt be left open
IC'
2-97
JIIC
NOTE: For oper.tioRilI condition, return pin.
11,13, and 23 to systam ground.
Specifications JAIV-0512
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range
Input Voltage Range
Storage Temperature Range
Lead Temperature (Soldering 10 Seconds)
Thermal Resistance, Junction-to-Case
Output Supply Voltage
Output Sink Current
Maximum Power Oissipation, Po
Maximum Junction Temperature, T J
-0.5 VOC to 7.0 VOC
-1.5 Vocat -12mA to 5.5VOC
-650 C to + 1500 C
300 0 C
JC' Case J ; 30 0 C/w
-0.5VOC to 7.0VOC
+30mA
575mWdc
1750 C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Normalized Fanout (Each Output)
Ambient Operating Temperature Range
4.75 VOC Min. to 5.25VOC Maximum
2.0VOC
0. 8V OC
6 Maximum (10mA)
-55 0 C to +125 0 C
ELECTRICAL CHARACTERISTICS
The electrical characteristics areas specified in the table and apply.over the full recom_
mended ambient operating temperature.range, unless otherwise specified.
I
LIMITS
SYMBOL
VOH
MIN
TEST
High Level Output Voltage
i
MAX
2.4
UNITS
TEST CONDITIONS
Volts
VCC =4.75V
VIN = 0.8V
IOH = -500/1A
I
VOL
Low Level Output Voltage
0.45
Volts
VCC - 4.75V
VIN = 2.0V
IOL = 10mA
VIC
Input Clamp Voltage
-1.5
Volts
VCC = 4.75V
liN = -12mA
TA = 25 0 C
100
/1A
VCC = 5.25V
VOH = 2.8V
VIN = 0.8V
200
/.fA
VCC = 5.25V
VOH = 5.25V
VIN" 0.8V
60
/1 A
VCC - 5.25V
VIN = 2.4V;
100
/1 A
VCC = 5.25V
VIN = 5.25;(1)
-1.6
rnA
VCC = 5.25V
VIN=O.4V;@
100
mA
VCC = 5.25V
YIN =0
140
os
140
ns
ICEX1
Maximum Collector Cut-Off
Current
ICEX2
ItH1
High Level Input Current
IIH2
IlL
LevI.} Level Input Current
ICC
Supply Current
tPHL
tPLH
-0.2
Propagation Delay Time
. High-to-Low Level Logic
25
Propagation Delay Time
Low-to-High Level Logic
25
NOTES:
.
;
1. When testing one E input, apply 5.25V to the other.
2. When testing one E input, apply GND to the other.
2-98
VCC = 5.0V
CL = 30pF Min.
R1 =470.(1 ±5%
Switching Time Test Circuits
INPUT
+5.0V
5.0V
AU
I
PULSE
SEE
GENERATOR
NOTE 2
PRR
= lMHz = 20%
80
Al
81
A2
B2
A3
A4
Rl
VCC
OUTPUT
83
D.U.T.
84
AS
85
El
86
E2
87
G, G2' G2
CL
;;,1-___1_oO_"S_ _ _ _ _-.;.._ .C-=.:.O=- _ _ _ 3.0V ± O.1V
2.7V
INPUT
I
''-'''"'-"'--~--
OV
~-----VOH
1.5V
'-------+--'-- - - -VOL
r--------t---..- - - - - - VOH
OUTPUT
-1.5V
~-VOL
NOTES:
1. Pins 12 and 14 shall be left open.
2. The applicable test table should be selected from the altered item drawing.
3. C1 ~ O.5fJ.F ±10%; R1 ~ 50n ±5%; R2 ~ 4701:1 ±5%; R3 ~ 1kl:1 ±5%;
CL :::: 30pF including jig and probe capacitance.
2-99
E
Characteristic Curves
OUTPUT CHARACTERISTICS
OUTPUT CURRENT
40
VS.
TEMPERATURE
40
VCC-5V
VCC-5V
35
1
~
30
zw
25
'"
20
a:
:l
35
./
)/
~1
"C/
(J
~
...
:l
15
~
:l
0
ii# -fJ
./
V ./
:et:.
""
o
25
a:
a:
20
--
~
:l
15
:l
10
I!:
0
.
0.2
0.3
0.4
0.5
0.6
o
-65
0.7
OUTPUT VOLTAGE (VOL TSI
I
75
J
a:
a:
/
:l
...~
VCc-SV
IOL -10mA
<
>
125
70
25
50
\
VCC-5.0V
.....,
CL -3OpF
VCC=t25V
.§
..........
::>
'"wa:
.......
100
VA-VE-OV
(J
----
PROPAGATION DELAY vs. TEMPERATURE
100
~
.......
CASE TEMPERATURE (OCI
POWER SUPPLY CURRENT VS. TEMPERATURE
zw
r--
5
o
0.1
VOL-0.4V
........
(J
V., V/'"
5
30
~
:l
".,
~c.
/'
<
.§
zw
~~ ~;...-r
./
10
o
V
--
]
>
c(
-
75
....w
C
z
0
;:
VCC-4.75V
~ 1'-->- ~ ~
t-
50
c(
-
CI
~
0
...a:
25
o
-65
o
25
o
25
70
125
-55
o
25
TEMPERATURE (OCI
TEMPERATURE (OCI
2-100
70
125
JAN-0512 Programming Procedure
PROGRAMMING SPECIFICATIONS
PARAMETER
VALUE
Address Input Voltage
High Logic Level
Low Logic Level
Open Circuit
-S.OV
Power Supply Voltage
+S.OV +S%, -0%
G1 Voltage@
G2 Voltage
G2' Voltage
For Device Type 01 Circuit A
3-61
3-32
3-38
3-43
4096 x 1 CMOS RAM
3-68
HM-6551
HM-6561
256 x 4 CMOS RAM
256 x 4 CMOS RAM
3-80
HM-6562"
256>< 4 CMOS RAM
1024 Field Programmable
3-86
j-92
HM-6611
HM-6661
3~74
CMOS PROM
1024 Field Programmable
CMOS PROM
Data Entry Formats for Harris Custom Programming
3-2
3-99
3-100
Symbols and Abbreviations
This data sheet utilizes a new set of specification nomenclature. This new format is an IEEE and JEDEC supported standard
for semiconductor memories. It is intended to clarify the symbols, abbreviations and definitions, and to make all memory
data sheets consistent. We believe that, once acclimated, you will find this standardized format easy to read and use.
EXAMPLE:
ELECTRICAL PARAMETER ABBREVIATIONS
All abbreviations use upper case letters with no subscripts.
The initial symbol is one of these four characters:
V
I
P
C
(Voltage)
(Current)
(Power)
(Capacitance)
WRITE
ENABLE
The second letter specifies input (I) or output (0), and the
third letter indicates the high (H), low (L) or off (Z) st'lte
of the pin during measurements. Examples:
VI L - Input Low Voltage
10Z - Output Leakage Current
TIMING PARAMETER ABBREVIATIONS
All timing abbreviations use upper case characters with no
subscripts. The initial character is always T and is followed
by four descriptors. These characters specify two signal
points arranged in a "from-to" sequence that define a.
timing interval. The two descriptors for each signal point
specify the signal name and the signal transitions. Thus
the format is:
III
TXXXX
Signal name.from W.hiCh in.terval is defined.
Transition direction for first signal
Signal name to which interval is defined
Transition direction for second signal
~
Signal Definitions:
A = Address
D = Data.ln
Q=Data Out
W = Write Enable
E = Chip Enable
S = Chip Select
G = Output Enable
Transition Definitions:
H=
L=
V=
X=
Z=
Transition
Transition
Transition
Transition
Transition
to
to
to
to
to
CHIP
ENABLE
High
Low
Valid
Invalid or Don't Care
Off (High Impedance)
The example shows Write pulse setup time defined as
TWLEH-Time from Write enable Low to chip Enable High.
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limh for each parameter. Input requirements
are specified from the external system point of view.
Thus, address set-up time is shown as a minimum since
the system must supply at least that much time (even
though most devices do not require it). On the other hand,
responses from the memory are specified from the device
point of view. Thus, the access time is shown as a maximum since the device never provides data later than that
time.
WAVEFORMS
WAVEFORM
SYMBOL
INPUT
OUTPUT
MUST BE
VALID
WiLL BE
VALID
~
CHANGE
FROM H TO L
WILL CHANGE
FROM H TO L
~
CHANGE
FROM L TO H
WILL CHANGE
FROM L TO H
m
DON'T CARE:
ANY CHANGE
PERMITT!:D
CHANGING:
STATE UNKNOWN
=>--
HIGH
IMPEDANCE
w~~
HM-6312/6312A
PROO\)CT.S DIVISION
CMOS ROM
A DIVISION Of HAR~IS CORPORATION
1024 Word x 12 Bit
JUL Y 1978
Features
Pinout
•
HM-6100 COMPATIBLE
•
LOW POWER - TYPICAL<>-------'
L - ' -____--~------, AND DISABLES·
ROM OUTPUT
DXO,
{
OXQ,
Vee
OX1, DX1, Vee
OX2, OX2, Vee
OX3, OX3. Vee
F
'<.. PROGRAMMABLE
INVERTING (H)
NON INVERTING (L)
3-4
Specifications HM-6312A-2IHM-6312A-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Applied Input or Output Voltage
Storage Temperature Range
Operating Temperature Range
Industrial-9
Military-2
ELECTRICAL CHARACTERISTICS
D.C.
vee=
+12.0V
GND -O.3V to vee + O.3V
-650 e to +150 0 e
-400 e to +85 0 e
-550 e to +1250 e
lO±5%
SYMBOL
PARAMETER
MIN
VIH
VIL
ilL
VOH
VOL
10
Logical "1" Input Voltage
Logical "0" Input Voltage
Input Leakage
Logical "1" Output Voltage
Logical "0" Output Voltage
Output Leakage
Standby Supply Current
Operating Current
Input Capacitance'
1/0 Capacitance'
70% VCC
ICCSB
ICCOP
CI
CIO
MAX
TYP
UNITS
20% VCC
+1.0
-1.0
VCC-O.l
-1.0
OV5VIN5vcc
10UT= 0
.IOUT=O
}J.A
}J.A
mA
pF
500
Operating Current
Input Capacitance*
I/O Capacitance* @
V
V
}J.A
V
V
TEST CONDITIONS
OV5 V05VCC
VI = 0 or VCC
f = 1MHz, 10 = 0
VI = VCC or GND
*Guaranteed and sampled, but not 100% tested.
II
See Switching Waveforms page 3-9
INDUSTRIAL
A.C,
SYMBOL
PARAMETER
TELOV
TGHOV
Access Time From E
Output Enable Time
Output Disable Time
Strobe Pos. Pulse Width
Cycle Time
Address Set-Up Time
Address Hold Time
Propagation to F
TGLOZ
TEHEL
TELEL
TAVEL
TELAX
TELFV
NOTES:
..................... 220nsec MAX
A4
W
!
• DATA RETENTION VOLTAGE. ,,'; •••••••••••••• '2.0 VOLTS MIN.
• TTL COMPATIBLE INIOUT',
•
HIGH OUTPUT DRIVE-2TTL 'LOADS
•
•
HIGH NOISE III"MlIIIIITY
ON CHIP ADDRESS'REGI8.TERS
•
•
THREE STATE OU"(PU1"S
EASY MICROPROCESSOR INTERFACING
a
,5
Q3
03
02
02
• LATCHED OUTPUTS
• MILITARY AND INDUSTRIAL TEMPERATURE RANG,ES
",,"",--_;.;;.r
A -ADDRESS INPUT
E -CHI,P ENABLE
\iii~WRITE ENABLE
G -'OUTPUT ENABLE
DlIscription
The HM-6501 is a 256 by 4 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation. ,
CHIP SELECT
D- DATA INPUT
Q- DATA OUTPUT
logic Symbol
AO __r-M-~~~__ DO
On chip latches are provided for address and data outputs allowing efficient interfacing withlTlicroprocessor systems. The data output,buffers
can be forced to a high impedance state for use_ in expanded memory
arrays.
I
01
's -
A,Al
QO
01
01
A3
The HM-E?501 is a, fully static RAM and may be maintained in, any state
for an indefinite period of time. Data retention supply voltage and supply
current are gllarante~dover temperature.
A4
02
A5
A6
02
A7
03
03
Functional Diagiam
A7'~""""""..:.;;.:r---:,
';60---'''--'{
ASO:---......
32
A1o--"'--'.....,
32.32'
MATRIX
AO~--:-:--L...,.,.-.J
G'
,00
0 0 0 - - - 1 >-.,.:....'---'-~------;
GATED
COLUMN
DECODER
AND DATA
INPUTIOUTPUT
0
0
~~-+-;:>---oOI
D20----......
0
~~-----------------'r------_t~_T--_,--~~--~--pt~
02
030----1
>-+---------...
Q3
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
w'o------Q
THREE STATE BUFFERS:
A HIGH--DUTPUT ACTIVE
DATA LATCHES:
LHIGH_O-D
Q LATCHES ON FALLING EDGE OF L
Eo---~~~-~~-------r;---"
MA3A2
ADDRESS LATCHES:
LATCH ON RISING EDGE OF L
GATED OECODERS:
GATE ON RISING EDGE OF G
Go----~)~~-----~-~
3:"14
Specifications HM-6501B-2IHM-6501B-9
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-vee
Operating Supply Voltage
Military (-2)
Industrial (-9)
+8.0V
Applied Input or Output Voltage
Storage Temperature
GND -O.3V
+O.3V
vee
-650
-vee
4.5V to 5.5V
4.5V to 5.5V
Operating Temperature
Military (-2)
Industrial (-9)
e to +1500 e
-55 0 e to +125 0 C
-4oo e to +85 0 e
ELECTRICAL CHARACTERISTICS
TEMP. & VCC =
OPERATING
RANGE
SYMBOL
PARAMETER
ICCSB
Standby Supply Current
ICCOP
TYP MAX UNITS
TEST
CONDITIONS
0.1
1
JlA
10=0
VI = VCC or GND
Operating Supply Current @
4
1.5
2.5
mA
ICCDR
Data Retention Supply Current
10
0.01
1
JlA
f = lMHz, 10 = 0
VI = VCC or GND
VCC = 3.0, 10 = 0
VI = vec or GND
VCCDR
Data Retention Supply Voltage
10Z
2.0
1.4
Input Leakage Current
-1.0
2.0
+1.0
-O.S
0.0
+0.5
JlA
V
GND~ VI ~ VCC
Output Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
JlA
V
GND ~ VO ~ VCC
VIL
I nput Low Voltage
-0.3
0.8
-0.3
2.0
I.S
VIH
Input High Voltage
VCC -2.0
VCC +0.3
2.5
2.0
S.3
V
VOL
Output Low Voltage
0.2
0.35
V
10L = 3.2mA
VOH
Output High Voltage
V
10H = -O.4mA
3.0
2.4
6
I nput Capacitance
CO
TELQV
TAVQV
TSHQX
TGLQX
TSLQZ
TGHQZ
TELEH
TEHEL
TAVEL
TELAX
TDVWH
TWHDX
TWLSL
TWLEH
TSHWH
TELWH
TWLWH
TELEL
NOTES:
0.4
®
Output Capacitance ®
CI
A.C.
MIN
--00
A
ALL LINES ACTIVE HIGH - POSITIVE LOGIC
THREE STATE BUFfERS:
AIHIGH-OUTPI,.tT ACTIVE
CONTROL AND DATA LATCHES:
LLOW-Q*D
Q LATCHES ON RISING EDGE OF L
ADDRESS LATettES:
LATCH ON RISING EDGE OF L
GIATEO DECODERS:
GATE ON RISING EDGE OF G
A7 A6 A3 A2 AS
3-20
Iii
AD
A2
A3
The HM-6503 is a truly static RAM and maybe maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.
E
Specifications HM-6503-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage -
OPERATING RANGE
vee
+8.0V
Input or Output Voltage Applied
Storage Temperature
Operating Supply Voltage
Industrial (-9)
GND -O.3V
to vee +O.3V
4.5V to 5.5V
Operating Temperature
Industrial (-9)
-65 0 C to +1500 C
-400 e to +850 e
ELECTRICAL CHARACTERISTICS
TEMP.• VCCOPERATING
RANGE
PARAMETER
SYMBOL
ICCSB
Standby Supply Current
Iceop
Operating Supply Current <2>
leeDR
Dat8 Retention Supply Current
VeeDR
Data Retention Supply
Vol~ge
MAX
MIN
TYP MAX UNITS
50
0.1
10
flA
10-0
VI- VCCo. GND
7
5
6
mA
f - lMHz. 10 - 0
VI- veeo. GND
0.01
5
flA
10 = ovec - 3.0
VI' VCC o. GND
25
2.0
2.0
1.4
NOTES:
V
Input Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
I'A
GND~VI~VeC
Output Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
flA
GND~VO~VCC
Vll
Input Low Voltage
-0.3
vec
-2.0
0.8
vee
+0.3
0.4
-0.3
2.0
1.5
V
2.0
5.3
V
0.25
0.35
VIH
I.put High Voltage
VOL
Output low. Voltage
VOH
Output High Voltage
CI
Input Capacitance<2>
8.0
5.0
CO
Output Capacitance
10.0
2.4
2.5
3.5
V
10-2.OmA
V
10- -1.OmA
8.0
pF
f -lMHz
VI - VCC or GND
6.0
10.0
pF
f"MHz
VO-VCC",GND
••
••
@
@
@
••
@
••
••
••
@
4.0
TElOV
Chip Enable Access Time
300
170
250
TAVOV
Address Access Time
320
170
270
TElOX
Chip Enable Output Enable
Time
100
50
60
TEHOZ
Chip Enable Output Disable
Time
100
50
60
TElEH
Chip EnabJe Pulse Negative
300
250
170
Width
A.C.
TEST
CONDITIONS
10Z
II
D.C.
MIN
TEMP- 250C(J)
VCC-I.OV
..
TEHEL
Chip Enable Pulse PositivI
Width
120
100
70
TAVEL
Addr," Setup Time
20
20
0
TELAX
Address Hold Time
50
50
20
TWLWH
Write Enable Pulse Width
60
60
40
TWLEH
Write Enable Pulse Setup Time
200
150
130
TWLEL
early Write Pulse Setup Time
0
0
-10
TWHEL
Write Enable Read Mode
Setup Time
0
0
-10
••
TElWH
Early Write Pilise Hold Time
60
60
40
••
TDVWL
Data Setup Time
0
0
-10
TDVEL
Early Write Data Setup Time
0
0
-10
TWLDX
Data Hold Time
60
60
40
TELDX
Early Write Data Hold Time
60
60
40
TELWL
Early Write Output Hi-Z Time
' 0
0
-10
TOVWL
Data Valid to Write Time
0
0
0
TELEL
Read or Write Cycle Time
420
350
240
..
••
••
••
••
••
••
••
..••
••
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
1. All devices tested at worst case Iimits. Room temp., 5 volt data provided for information - not guaranteed.
2. Operating Supply Current (iCCOP) is proportiomil to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
3. Capacitance sampled and guaranteed - not 100% tested.
4. AC test conditions: Inputs - TRISE = TFALL = 20nsec; Output - 1 TTL load and 5OpF; All timing measurad at 14 VCC,
3-21
E
Specifications HM-6503-5
....
..
ABSOLUTE MAXIMUM RATINGS
Supply Voltage -
OPERATING RANGE
VCC
+8.0V
GND
Input or Output Voltage Applied
Operating Supply Voltage
Commercial
-O.3V
to VCC +O.3V
OOC to +75 0 C
Commercial
-65 0 C to +1500 C
Storage Temperature
4.75V to 5.25V
Operating Temperature
ELECTRICAL CHARACTERISTICS
TEMP. &VCCOPERATING
RANGE
SYMBOL
ICesB
Standby Supply Current
ICCOP
Operating Supply Current C%>
MIN
MAX
...
MIN
TYP
MAX UNITS
TEST
CONDITIONS
500
100
500
Il A
10 - 0
VI = vce or GND
7,
5
6
rnA
f = lMHz, 10" 0
VI = vce or GND
Input leakage Cu rrent
-10.0
+10.0
-7.0
jJ.A
GND :5 VI :5vec
Output Leakage Current
-10.0
+10.0
-7.0
to.5
to.5
+7.0
10Z
+7.0
jJ.A
GND:5vO:5VCC
VIL
Input Low~Voltage
-0.3
0.8
-0.3
2.0
1.5
V
VIH
Input High-Voltage
vec
-2.0
2.5
2.0
5.3
V
VOL
OutPl-lt Low Voltage
0.25
0.35
V
10 = 1.6mA
VOH
Output High Voltage
V
10= -0.4mA
II
D.C.
PARAMETER
TEMP - 25OC
10.0
6.0
10.0
pF
f = lMHz
VO=VCC or GND
TELOV
Chip_Enable Access,Time
350
200
300
ns
TAVOV
Address AccesS; Time
370
200
320
·ns
TELOX
Chip Enable Output Enable
100
50
80
ns
@
@
@
100
50
80
ns
@
@
Time
TEHOZ
Chip Enable Output Disable
Time
TELEH
Chip Enable Pulse Negative
350
300
200
ns
150
120
100
ns
@
@
@
@
@
@
@
Width
TEHEL
A.C.
NOTES:
1.
2.
3.
4.
Chip Enable Pulse Positive
Width
TAVEL
Address Setup Time
20
20
0
ns
TELAX
Address Hold 'time
50
50
20
ns
TWLWH
Write Enable Pulse Width
100
80
60
ns
TWLEH
Write Enable Pulse Setup Time
250
200
100
ns
TWLEL
Early Write Pulse Setup Time
0
0
-10
ns
TWHEL
Write Enable Read
Setup Time
0
0
-10
hs
TELWH
Early-Write Pulse Hold Time
100
80
60
n.
TDVWL
Data Setup Time
30
20
0
TDVEL
Early Write Data Setup Time
30
20
0
ns
Os
TWLDX
Data Hold Time
100
80
60
ns
TELDX
Earty Write Data Hold Time
100
80
80
ns
TE.LWL
Early Write Output Hi':'Z Time
0
0
-10
ns
TOVWL
Data Valid to Write Time
0
0
0
ns
TELEL
Read or Write Cycle Time
500
420
300
ns
@
@
@
@
@
@
@
@
All devices tested at worst case limits .. Room temp., 5 volt data provided for. information ~ not guaranteed.
Operating Supply Current (iCCOP) is proportional to Operating Frequency. Example: TypicaliCCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC test conditions: .Inputs - TRISE = TFALL = 20nsec; Output - 1 TTL load and 50pF; All timing measured at Yo VCC.
Read Cycl,
A
TELEL
TEHEL
TELEH
r
TEHQZ
Q
W
VALID DATA OUTPUT
HIGH
t
TIME
REFERENCE
t t
3
-1
4
TRUTH TABLE
TIME
REFERENCE
INPUTS
-1
1
2
MEMORY DISABLED
CYCLE BEGINS. ADDRESSES ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID
READ ACCOMPLISHED
PREPARE FOR NEXT CYCLE ISAME AS -11
CYCLE ENDS. NEXT CYCLE BEGINS ISAME AS 01
A
a
H
X
V
X
X
x
Z
Z
X
V
V
X
V
Z
Z
L
L
.r
3
4
5
FUNCTION
E Vi
'-
0
~UT1'UT
H
'-
X
H
H
H
H
X
H
becomes enabled but data is not valid until during time
(T = 2). iN must remain high until after time (T = 2).
After the output data has been read, E may return high
(T = 3). This will disable the output buffer and ready the
RAM forthe next memory cycle (T = 4).
The address information is latched in the on chip registers
on the falling edge of E (T = 0). Minimum address set up
and hold time requirements must be met. After the required hold time, the addresses may change state without
affecting device operation. During time (T = 1) the output
Early Write Cycle
A~~~~~~
TELEL
TELEH
w~~~~~-+
-!TOVEL
o3888888>K
Q__
~HI~G~H-~Z
__~~~~~~~~~~~~~~~~~~~~~~__+-__
TELOX~
OATAVALIO
. . . ___________
~
TOVEL
_~N-E-XT"":"OA-T-A-
________________________________________________________________
t
TIME
REFERENCE
2
-1
~HI~GH~-~Z_
I
3
TRUTH TABLE
TIME
REFERENCE
INPUTS
A
OUTPUT
r
Vi
0
a
-1
H
'-
X
L
X
X
0
v v
Z
Z
Z
Z
Z
Z
1
2
3
4
L
.r x
H
'-
X
L
X
X
X
X
V
X
x
X
V
FUNCTION
MEMORV DISABLED
CYCLE BEGINS; ADDRESSES ARE LATCHED
WRITE IN PROGRESS INTERNALL Y
WRITE COMPLETED
PREPARE FOR NEXT CYCLE ISAME AS -11
CYCLE ENDS. NEXT CYCLe BE.GINS (SAME AS 01
The early write cycle is the only cycle where the output is
guaranteed not to oecome active.' On the falling edge of
E (T = 0), the addresses, the write signal, and the data
input are latched in on chip registers. The logic value of IN
at the time E falls determines the state of the output buffer
for that cycle. Since W is low in the early write cycle the
output buffer is latched into the high impedance state and
3-23
will remain in that state until E returns high (T = 2). For
this cycle, the data input is latched by Egoing low; therefore data set up and hold times' should be·referenced to E.
When E (T := 2) returns to the high state the output buffer
disables and all signals are unlatched. The device is now
ready for the next cycle.
I
Read Modify Write Cycle
TIME
REFERENCE
t
-I
t
5.
'6
TRUTHTABLE
TIME
REFERENCE
E
W
INPUTS
A
0
Q
-1
0
I
H
'-L
X
H
X
V
X
X
Z
Z
X
X
X
X.
V
2
3
4
5
6
1
I
.
L
L
L
H'
H
:'X.
f
x
H
:'-
H
X
OUTPUT
x .. x
x
x x
' X
X·X
V X
FUNCTION
MEMORY'DISABLED'
CYCLE BEGINS. ADDRESS ARE LATCHED
OUTPUT. EN.AB,LED
OUTPUT VALID. READ AND MODIFY TIME
WRITE BEGfNS. DATA IS LATCHED
WRITE IN PRDGRESS'INTERNALLY
WRITE COMPlETED
PREPARE FOR NEXT CYCLE (SAME AS-lI
CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 0)
Y
V
V
V
Z
Z
The read modify write cycle begins as all other cycles on' calso 'l1tct)es itself on its low going edge. All input signals
the falling edge of E (T = 0). The W line should be high at . excluding E have been latched and have no further effect .
(T. = 0) in order to latch the output buffers in the active
on the RAM. The rising edge of E (T = 5) completes the
state. During (T;= 1 ) the output will be active Qutnot valid.
write portionof-ttie cycle .arid lJrilatches all inputs and the
until (T = 2). On thefillifrig edgeofthe WIT';' 3fthe dat~
output. The ()utput goes to a high impedance and the RAM
present at the output and input are latched. TheW signal' is·teady for the-nextcycle. .
-~-------------"-----'---'---NOTES:
in
In the abDve descriPtions the numbers·
parenthesis IT = Xl refet to the respective timing·diagrams.
The numbers are IDeated .on the time reference line bel.oweach diagram. The timing' diagrams sh.own
are Dnlyex~",pie$~n~ a~~ not.the .only valid ~ethDdDfQPeraii6n~
. .
Suggestions For.fl503 Memory Array Design
The HM-6503 is a device that can be used to good advantage in systems which are offered with choices of memory
array size. With one common memory board layout the
designer can easily offer two differeot arritY si~es" This is
accomplished by using the conveniently,similiar pinouts of
the HM-6503 (2K by 1) and the i-IM-:6504 (4K by 1). For
example, a 16K word by 8 bit array using HM-6503s and a
32K word by 8 bit array using HM-6504s can be easily implemented pn .the same printed circuit card. TI;lecircu)t
.diagram s\lggests on~ implementation requiring 'only. one
jumper wire for. 16K or 32K word ·selection. This single
jumper wire also allows the 16K array to utilize the HM6503H or the HM-6503L version.
3-2:4
+vCC
4-
6&03H
MPf6604.. __ ~.JUMPER
1
B503~
TO RAM
PIN 14
H0-8440
CMOS
ADDRESS ~:----E""'~H L~T~:O
BUS'I&
DECODER
.QRI)lER
.. CHIPENABLE
~IMING CONTR.OL
----+---.. . .I. .
8
WORD
ENABLE
UNE3
Battery Backup Applications
The HM-6503 is especially well suited for use in battery backup systems. Data retention supply voltage and supply
current are guaranteed over the full temperature range.
When designing the backup system, the following suggestions should be considered:
1.) As RAM VCC drops, the input logical one voltages should follow so as not to exceed VCC +0.3. It is
suggested to use CMOS drivers, operating at CMOS VCC, such as the HD-6495, HD-6432, and HD-6433.
Another approach is the use of open collector or open drain buffers pulled up to CMOS VCC.
2.)
E must
be held high at CMOS VCC.
VCC to minimize power dissipation.
W,
address and data inputs should be held at either GND or CMOS
3.) When exiting from the battery backup mode, VCC should ramp without ring or discontinuities.
4.)
The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 or 4.75
volts).
A very simple battery backup system is shown in Figure 1. When system power is available, diode D1 is forward
biased and supplies current to the CMOS devices. Upon loss of system power, diode D 1 is reverse biased and only
CMOS devices are consuming battery power. A disadvantage to this method is that CMOS VCC is one diode drop,
.7V, below TTL VCC. There is a possibility that a TTL output signal could rise higher than CMOS VCC and cause
possible latch problems. This possibility can be reduced by incorporating a system similar to that shown in Figure
2. Other alternatives include using a germanuin diode yielding a VF ~ .2V or adding diode D2 in the TTL supply
and raising VCC to account for the drop. A PNP transistor is substituted for the diode in Figure 2. T'le saturation
drop of the transistor, 0.2V, is less than the 0.7V drop of the diode giving more margin against latch-up. A power
fail output signal is available to disable the E circuitry. Open collector TTL with pullups to CMOS VCC or LS
type TTL should be used as memory drivers. This will insure that the CMOS inputs are not floating during the
backup period. When system power is restored, operation continues as normal and the NI-CAD battery pack is
trickle charged through RC.
(OPTIONAL)
r-ruH-------'
0
o
:
02
:
L __ - T - - _.J
SYSTEM
POWER
r--4~--------~---------------------+vcc
L---~----"+---------------"""--_CMOS
VCC
RC
i
-=- NO·CAD
2.4V
FIGURE 1
r---------~----------._--------~vce
r---r-~_1r_--_f------+--.ellos vee
Re
-=-
I
POWE R FAIL ...--------,--------------------~
FIGURE 2
3-25
NI-CAD
2.4V
HARRIS
HM-6504
SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HAARIS CORPORATION
4096 x 1 CMOS RAM
JULY 1978
Pinout
Features
<.< 1mW MAX.
TOP VIEW
•
LOW POWER STANDBY .••. ' • • . • • • • . • • • • . • . • . • •
•
LOW POWER OPERATION . • . • • • • . • • . . . . . • . • . 35mW/MHz MAX.
AO
vee
•
EXTREMELY LOW SPEED POWER PRODUCT
A1
AS
•
DATA RETENTION . . . . • • . . . . . . . . . . . . . . • . . . • • . @2.0VMIN.
A2
A7
•
TTL COMPATIBLE INPUT/OUTPUT
A3
AS
•
THREE-8TATE OUTPUT
A4
A9
•
STANDARD JEDEC PINOUT
AS
A10
Q
A11
•
•
FAST ACCESS TIME • . • • . • • • . . . • • • • • • • • • • . . .• 300nsec MAX.
MILITARY TEMPERATURE RANGE
•
INDUSTRIAL TEMPERATURE RANGE
•
18 PIN PACKAGE FOR HIGH DENSITY
•
ON CH,IP ADDRESS REGISTER
D
iN
GND
E
logic Symbol
Description
vee
The HM~6504 is a ,4096 x· 1 static CMOS RAM ,fabricated using self
aligned silicon gate technology. The device utilizl;ls synchronous circuitry
to achieve high performance and low power operation.
AO
AI
A2
D
A3
A4
AS
A6
A7
AS
A9
On chip latches are provided for addresses. data input and data output
'allowi ng efficient interfacing with microprocessor systems. The data
output can be forced to a high impedance for use in expanded memory
arrays.
Q
AIO
Al1
The HM~6504 is a truly static RAM and may be maintained in any state
for an indefinite period of time.
~
- Address Input
E - Chip Enable
GND
iN - Write Enable
Data retention supply voltage and supply current are guaranteed ,over.
temperature.
0- Data Input
Data Output
Q -
Functional Diagram
,A
Al1
84,84
MATRIX
AI
A4
>--OQ
o
A
ALL LINES ACTIVE HIGH - POSITIVE LOGIC
THREE STATE BUFFERS:
A HIGH -
OUTPUT ACTIVE
CONTROL AND DATA LATCHES:
LlOW-Q-D
Q
LATCHES ON RISING EDGE OF L
ADDRESS LATCHES:
LATCH ON RISING EDGE OF L
GATED DECODERS:
GATE ON RISING EDGE OF G
w
~ ~2~ A8A7AB
3-26
W
SpecificBtiona HM-6504-2IHM-6504-9
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
Supply Voltage - vee
+8.0V
Input or Output Voltage Applied
Operating Supply Voltage
Military (-2)
Industrial (-9)
GND -O.3V
to VCe+O.3V
Operating Temperature
Military (-2)
Industrial (-9)
-65 0e to +150 0e
Storage Temperature
4.5V to 5.5V
to 5.5V
4~5V
-550e to +1250e
-400e to +850e
ELECTRICAL CHARACTERISTICS
TEMP.&VCCOPERATING
RANGE
PARAMETER
SYMBOL
ICCSB
Standby Supply Current
ICCOP
Operating Supply Current <2>
ICCDR
DatI Retention Supply Current
VeCDR
Data Retention Supply Voltage
2.0
MAX
MIN
TVP
8.0
5.0
CO
Output Capacitance <3>
10.0
6.0
2.4
2.5
0.25'
VIH
VOL
3.6
10- -1.OmA
8.0
pF
,& lMHz
VI &VCCor GND
10.0
pf
'-IMHz
VO • vee or.GND
TELOV
Chip Enable Access Time
300
170
260
TAVOV
Address Access Time
320
170
270
TELOX
Chip Enable Output Enable
100
60
80
TEHOZ
Chip Enable Output Disable
100
60
80
TELEH
Chip Enable Pulse Negative
300
260
170
120
100
70
Width
TEHEL
Chip Enable Pulse Positive
Width
TAVEL
Address Setup Time
20
20
0
TELAX
Address Hold Time
60
60
20
TWLWH
Write Enable Pulse Width
80
60
40
TWLEH
Write Enable Pulse SetuP Time
200
150
130
TWLEL
Early Write Pulse Setup Time
0
0
-10
Write Enable Read Mode
0
0
-10
TWHEL
Sewpnme
1.
2.
3.
4.
TELWH
Early Write Pulse Hold Time
80
60
40
TDVWL
Data Setup Time
0
0
0
TDVEL
Early Write Data Setup Time
0
0
0
TWLDX
Data Hold Time
BO
60
40
TELDX
Early Write Data Hold Time
80
60
40
-10
TELWL
Early Write Output Hi-Z Time
0
0
TOVWL
Data Valid to Write Time
0
0
0
TELEL
Read or Write Cycle Time
420
360
240
10-2.0mA
V
4.0
Time
NOTES:
10 - o vee • 3.0
VI -Vec or GND
Output Leakage Current
Time
A.C.
TEST
CONDITIONS
10Z
II
D.C.
MIN
TEMP - 2&Oe
vee- s.ov
n.
n.
n.
n.
n.
n.
n.
n.
n.
no
n.
n.
n.
..n.
n.
n.
n.
n.
n.
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
All devices tested at worst case limits. Room temp .. 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: TypicallCCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC .test conditions: Inputs - TRISE =TFALL =20nsec; Output - 1 TTL load and 50pF; All timing measured at Yo VCC.
3-27
Specifications HM-6504-5
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
Supply Voltage - VCC
+8.0V
Input or Output Voltage Applied
Storage Temperature
Operating Supply Voltage
Commercial
GND -O.3V
to VCC +O.3V
4.75V to 5.25V
Operating Temperature
Commercial
-650 C to +1500 C
OoC to +75 0 C
ELECTRICAL CHARACTERISTICS
TEMP.&VCCOPERATING
RANGE
PARAMETER
SYMBOL
ICCSB
Standby Supply Current
lecop
Operating Supply Current <2>
MAX
MIN
TYP
006<
TElEL
~TEHn
TfHEL_
TELEH
~
--.J
HIGH
5r---?Q---,----:V.:.::=ALlDOUTPUT"----t.--~TELQV
lEMOZ
Q
TEHQZ
~TELQX
Ref'!':eENCf.'-----tf--+----+----II-----I-----!f--t!4,
-1
5
TRUTH TABLE
liME
REF RENCE
INPUTS
iN A
E
-1
0
1
H
~
L
L
2
3
4
5
J
H
~
X
H
H
H
H
X
H
OUTPUTS
0
X
V
X
X
X
X
X
X
X
X
V
X
X
X
FUNCTION
Q
MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID
READ ACCOMPLISHED
PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)
Z
Z
X
V
V
Z
Z
IT = 2). W must remain high for the read cycle. After the
output data has been read, E may return high (T = 3).
This will disable the chip and force the output buffer to
a high impedance state. After the required E high time
(TEHEL) the RAM is ready for the next memory cycle
In the HM-6508 Read Cycle, the address information is
latched into the on chip registers on the falling edge of
E (T= 0). Minimum address setup and hpldtime requirements must be met. After the required hold time, the
addresses may change state without affecting device operation. During time (T = 1) the data output becomes enabled; however, the data is not Valid until during time
(T = 4).
D----~~----~~------Write Cycle
TAVE~. "'TELA~--l
TAVEL--!
VAl.ID
::::...
NEXT
TELEL
TEHEL_
TELEH
t:==,.rEHEL
TWLEH
I
ij/////
TWLWH
TELWH
1
'--
'//////A""""'---,,""'-,
.1
.1
VALID DATA INPUT
"~TDVWH_ '~TWHDX
HIGH Z
,I
TIME
REfERENCE
-1
2
3
TRUTH TABLE
TIME
REFERENCE
-1
E
H
0
~
1
L
L
2
INPUTS
iN A
X
x
'-.
J
3
4
J
H
H
X
5
~
X
X
V
X
X
X
X
V
OUTPUTS
0
Q
X
Z
Z
Z
Z
Z
Z
Z
X
X
V
X
X
X
FUNCTION
MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
WRITE PERIOD BEGINS
DATA IS WRITTEN
WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)
3-36
The write cycle is initiated by the falling edge of E which
latches the address information into the on ch ip registers.
The write portion of the cycle is defined as both E and VIi
being low simultaneously. Vi may go low anytime during
the cycle provided that the writ~ enable pulse setup time
(TWLEH) is met. The write portion of the cycle is terminated by the first rising edge of either E or W. Data
setup and hold times must be referenced to the terminating
signal.
If a series of consecutive write cycles are to be performed,
the W line may remain low until all desired locations have
been written. When this method is used, data setup and
hold times must be referenced to the rising edge of E. By
positioning the VIi pulse at different times within the E
low time (TE LEH l. various types of write cycles may be
performed.
If the E low time (TELEH) is greater than the W pulse
(TWLWH) plus an output enable time (TELQX), a combination read write cycle is executed. Data may be modified
an indefinite number of times during any write cycle
(TELEH). The data input and data output pins may be tied
together for use with a common I/O data bus structure.
When using the RAM in this method allow a minimum of
one output disable time (TWLQZ) after TN goes low before
applying input data to the bus. This will insure that the
output buffers are not active.
Battery Backup Applications
The HM-6508 is especially well suited for use in battery backup systems. Data retention supply voltage and supply current are
guaranteed over the full temperature range.
When designing the backup system, the following suggestions should be considered:
1.)
As RAM VCC drops, the input logical one voltages should follow so as not to exceed VCC +0.3. It is suggested to use CMOS drivers, operating at CMOS VCC, such as the HD-6495, HD-6432, and HD-6433. Another approach is the use of open collector or open drain buffers pulled up to. CMOS VCC.
2.)
E
must be held high at CMOS VCC.
VCC to minimize power dissipation.
Vi,
address and data inputs should be held at either GND or CMOS
3.)
When exiting from the battery backup mode, VCC should ramp without ring or discontinuities.
4.)
The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 or 4.75V).
A very simple battery backup system is shown in Figure 1. When system power is available, diode D1 is forward biased and
supplies current to the CMOS devices. Upon loss of system power, diode D1 is reverse biased and only CMOS devices are
consuming battery power. A disadvantage to this method is that CMOS VCC is one diode drop, .7V, below TTLVCC. There
is a possibility that a TTL output signal could rise higher than CMOS VCC and cause possible latch problems. This possibility
can be reduced by incorporating a system similar to that shown in Figure 2. Other alternatives include using a germanuin diode
yielding a VF ~ .2V or adding diode D2 in the TTL supply and raising VCC to account for the drop. A PNP transistor is
substituted for the diode in Figure 2. The saturation drop of the transistor, 0.2V, is less than the 0.7V drop of the diode giving
more margin against latch-up. A power fail output signal is available to disable the E circuitry. Open collector TTL with
pullups to CMOS VCC or LS type TTL should be used as memory drivers. This will insure that the CMOS inputs are not
floating during the backup period. When system power is restored, operation continues as normal and the NI-CADbattery
pack is trickle charged through RC.
lOPTIONAL)
:*:
, - - - - t - - - - t - - - - vcc
~~S:EE: GK)>---r-_ _L_~_'-i~T_-__-_J_ _ _ _ _ _-+:
'-----:::i"~H-I---,-----l-t--
SYSTEM "';C;-~+--_
POWER
r-+-""T-+---t-_CMOSVCC
vee
RC
cMOS
vee
-
===
RC
r
-=-
NI"CAD
HV
FIGURE 1
POW€RfAIL
_------------1
FIGURE 2
NI-CAD
2.4V
1
I
HA.RRIS
SEMICONOUCTOR
PROOUCTS OIVISION
HM-6512
A DIVISION OF HARRIS CORPORATION
64
X
12 CMOS RAM
APRIL 1978
Features
•
Pinout
LOW POWER STANDBY
TOP VIEW
1mWMAX.
•
LOW POWER OPERATION, . . . . • . . . • . . . • . . . • • . 22mW/MHz MAX.
•
DATA RETENTION . • • • . . . • . . • • . • • • • • • . • . . . • . . @ 2.0V MIN.
•
TTL COMPATIBLE INPUT/OUTPUT
cs
vce
MSEL
OX11
THREE STATE OUTPUTS
ox,o
ox.
oxs
•
FAST ACCESS TIME • . . • . . • . . • • . . • . • . . . • . • • • . 250nsec MAX.
oX7
•
MILITARY AND INDUSTRIAL TEMPERATURE RANGE
•
18 PIN PACKAGE FOR HIGH DENSITY
•
ON CHIP ADDRESS REGISTER
•
•
TWO HM-6512's CAN BE USED WITH HM-6100 AND HM-6312 WITHOUT
ADDITIONAL COMPONENTS
,
"'1.:. _ _....I""
oxs
logic Symbol
STA
Description
vee'
MSEl
DXO
ox,
ox,
The HM-6512 is a high speed, low power, silicon gate CMOS 768 bit
static RAM organized 64 words by 12 bits. In all static .states .these
units exhibit the microwatt power requirements typical of CMOS. Inputs
and three state outputs are TTL compatible. The basic part operates at
4-7 volts with a typical 5 volt, 250 C access time of 150ns.
51
Signal polarities and functions .are specified for direct interfacing with
the HM--6100 microprocessor. The device is ideally suited for minimum
system all CMOS applications where low pLwer, minimum cost, or nonvolatility is required.
DX3
ox.
DXS
Dxa
ox,
ox.
ox.
DX10
OXt1
CS STR MSEL ADROX -
Chip Select
Chip Enable
Enable and RIW Decode
Address Decode
Address Input and
Data I/O
Functional Diagram
r------- -----'OF..
STR
ox.
ox.
ox,
ox.
DX10
DXt1
I
I
ADDRESS
I
REGISTER
DX5*
DXo-11
MSEL
ADR
DX5·
os
STR
3-38
~
I
Specifications HM-6512
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
8.0V
Input or Output Voltage Applied
GND -O.3V to
vee +O.3V
-650 e to +150o e
Storage Temperature Range
Operating Temperature Range
-40 oe to +85 0 e
Industrial HM-6512-9
-55 0 e to +125 0 e
Military HM-6512-2
ELECTRICAL CHARACTERISTICS
SYMBOL
D.C.
PARAMETER
VIH
Logical "1" Input Voltage
VIL
Logical "0" Input Voltage
IlL
Input Leakage
VOH
Logical "1" Output Voltage
VOL
Logical "0" Output Voltage
10
MINIMUM
TYPICAL
MAXIMUM
VCC -2.0
TEST CONOITIONS
V
-1.0
O.S
V
+1.0
jJ.A
2.4
Output Leakage
UNITS
V
-1.0
OV ~ VIN ~ VCC
10H = -0.2mA
0.45
V
+1.0
jJ.A
OV~ VO ~ VCC
IOL = 2.0mA
ICCSS
Supply Current Standby
1.0
100
jJ.A
STR = VCC = 5.5V
VIN = VCC or GNO
ICCOR
Supply Current Oata Retention
0.1
50
jJ.A
STR = VCC = 3.0V
VIN = VCC or GND
I nput Capacitance
5.0
7.0
pF
Input/Output Capacitance
6.0
10.0
pF
CI
CIO"
TAC
Access Time from STR
250
ns
TEN
Output Enable Time
200
ns
200
ns
TDIS
Output Disable Time
TSTR
STR Pulse Width (Positive)
200
ns
TSTR
STR Pulse Width (Negative)
250
ns
Cycle Time
450
ns
TWP
Write Pulse Width (Negative)
130
ns
TAS
Address Setup Time
30
ns
TC
A.C.
vee = 5.0V ±10%, TA = Industrial or Military
TAH
Address Hold Time
50
ns
TDS
Data Setup Time
130
ns
TDH
Data Hold Time
a
ns
TPS
MSEL Pulse Separation
150
ns
TMS
MSE L Setup Time
50
ns
TMH
MSEL Hold Time
50
ns
"Guaranteed but not 100% tested.
3-39
CL = 50pF
See Figures
1&2
Spllt:ificlItions" HM;.65t2C-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
7;OV
Input or Output Voltage Applied
GNP -O.3V to VCC +O.3V
-650C to +1500C
Storage Temperature Range
Operating Temperature Range
"'400 C to +850C
Industrial HM-6512C-9
ELECTRICAL CHARACTERISTICS vcc = 5.0V:ts%, TA = Industrial
SYMBOL
VIH
D.C.
Logical ;'0" Input Voltage
In'put L~akage
-5.0
VOH
Logical "1" Output Voltage
2.4
VOL
Logical "0" Output Voltage
Output Leakage
TYPICAL
MAXIMUM
VCC-l.5
ilL
UNITS
TEST CONDITIONS
V
0.8
V
+5.0
IJ.A
OV
V
-5.0
<: VCC
V
IJ.A
OV(:,VO
800
IJ.A
STR = VCC = 5.25V
VIN = VCC or GNO
CIN'
Input Capacitance
5.0
7.0
,pF,
CIO'
fnput/Output Capacitance
6.0
10.0
pF
TAC
Access Time from STR
400
ns
TEN'
Output Enable Time
300
"' 'ns
TDIS
' Output Diseb'le Time
300
ns
TSTR
STR Pulse Width '(Positive)
250
ns
T~
STR Pulse Width (Nagative)
400
ns
Cycle Time
650
ns
TWP
Write Pulse Width (Nagative)
200
ils
TAS
Address Setup Time
60
ns
TAH
AddresS Hold Time
100
ns
ns
TOS
Data Setup Time
200
TOH
Data Hljld Time
0
,
ns
TPS
MSE L Pulse Separation
150
,
ns
TMS
MSEL Setup Time
100
ns
TMH
MSEL Hold Time,
100
ns
10L= 1.6mA
<: VCC
CL = 50pF
See Figures
1111,2
"
..
,
'3:"40
VIN
+5.0
Suppl~ Current Standby
'Guaranteed but not 100% tested.
<:
10H =-O.2mA
0.45
ICCSS
TC
A.C.
Logical "1" Input Voltage
MINIMUM
VIL
10
•
PARAMETER
Functional Description
MSEL - The MSEL pin functions as a second chip enable
and a write enable pin. If MSEL is low during the address
strobe time the chip is placed in the write mode immediately. If MSEL is high during address strobe the chip performs a read operation during the first MSEL pulse and a
write operation during the second MSEL pulse. In the
event that a read only operation is desired the second
MSEL pulse would be omitted.
ADR - The ADR pin provides the user with a method for
using two HM-6512 chips in a HM-6100, HM-6312 ROM
based system without any further decoding. The data on
this pin is compared internally with address on DX5. If
the two match, the chip will respond to MSEL and CS,
otherwise the outputs remain high impedance and the
stored data is unchanged. Using the HM-6312 with RSEL
pin programmed for an active low for address 0-3778
and one or two HM-6512 RAMs provides for a 64 or
128 word scratch pad memory on page O.
Read Cycle
STR
CS
MEMSEl
ox
TIME
REFERENCE
-1
t t
0
2
1
3
4
TRUTH TABLE
TIME
REFERENCE
STR
-1
H
0
""\..
1
L
L
2
3
4
INPUTS
MSEL
X
X
FUNCTION
DX
Z
Memory Disabled
V·
Valid, Address Latched In
End of Address Time
Valid, Data on Output
End of Read Cycle
Begin New Cycle, Same as-1
""\..
X
..r
L
V
H
H
X
Z
Z
I
... Address valid during this time.
FIGURE 1
Read Modify Write Cycle
REF~I::N::::CE~+---1tr---it-+---+---+-t--t+-+t-+f--+-t---1
0
1
2
3
4
3-41
5
6
7
8
',L .T\ilUTH
.'
TIME
REFERENCE
-1
STR
H
0
'L
L
L
L
L
L
1
2
3
4
5
6
H
7
8
'-
TABLE
"
"
INPUTS
MSEL
ox
Z
X
H
V'
'L
Z
X
.I
V
'-
Z
FUNCTION
Me,mor,V Dis,abled
Cycle Begins, Address Latched In
End of Address Time
Segin Read Time'
E;nd of Read Time
Begin Write Time
.r
V
Data Written hi
H
X
H
Z
Z
End of Write Time
End of Cycle, Memory Disabled
Begin N.ew Cycle, New ,~ddress ~atch:ed In
V'
... Addres~ valid d,uring this tifT"!e.
FIGURE 2
Write Cycle
STR
MSEL~~~~~~~____________-Jlr-----------------------~________
RE;~~~~NC~E~-+----+----4------------~--------------------+!-+t----+1-------TRUTH TABLE
TIME
REFERENCE
I
STR
-1
H
0
'-
1
2
3
4
5
L
L
INPUTS
MSEL
X
X
L
f
J
H
H
X
X
""-
FUNCTION
OX
Z
Memory Disabled
V'
Cycle Begins, Addresses are Latchf3:c::i
Z
Write Period Begins
Data I n is Written
Write Completed
Prepare for Next Cycle
Cycle Ends, Next Cvcle Begins
V
Z
Z
V·
"''Address valid during.thistime.
FIGURE 3
Typical Microprocessor System
HM-6190
LXMAR~~~
__~~__--~t-~
____----------__
~
MSELri---------------L--------------~~k---------------~
XTC
3-42
m
HARRIS
HM-6513
SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION
512 x 4 CMOS RAM
JULY 1978
Features
•
Pinout
•
LOW POWER OPERATION . • • • • . • • • • • . • • . • • • • 36mW/MHz MAX.
•
DATA RETENTION • • • • • • • . . . • • . • • • • . • . . • • • . . . @2.0VMIN.
•
TTL COMPATIBILITY INPUT/OUTPUT
•
COMMON DATA IN/OUT
•
TOP VIEW
LOW POWER STANDBY . . • . • • . • • • • • • • . • . • • • • . . «lmW MAX.
THREE STATE OUTPUTS
•
FAST ACCESS TIME •••.••••••••.•••.•••••
•
INDUSTRIAL OR COMMERCIAL TEMPERATURE RANGE
•
18 PIN PACKAGE FOR HIGH DENSITY
•
ON CHIP ADDRESS REGISTER
•
PINOUT ALLOWS UPGRADE TO HM-6514
300nsec MAX.
VCC
A4
A6
A3
A7
A2
AS
AO
DOO
Al
DOl
y
D02
E
D03
W
GND
Description
logic Symbol
The HM-6513 is a 512 x 4 static CMOS RAM fabricated using self aligned
silicon gate technology. The device utilizes synchronous circuitry to
achieve high performance and low power operation.
E
On chip latches are provided for the addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high
impedance state for use in expanded memory systems.
A-Address Input
E -Chip Enable
VV-Write Enable
DQ -Data In/Out
Y - Hard Wired Input
Functional Diagram
A3
A4
GATED
A6
DECODER
..
ROW
64x32
MATRIX
A7
AS
DOO 0---+----:<
f--7-==r-.......-t---I
00lo---+---t7<
f-~-==r-
.......-t---I
GATED COLUMN
DECODER
AND DATA
INPUT/OUTPUT
DQ3o----.......~-f-~ f--~==T--+--~r_--I
ALL LINES ACTIVE HIGH - POSITIVE LOGIC
THREE STATE BUFFERS:
OUTPUT ACTIVE
ADDRESS REGISTERS:
LATCH ON RISING EDGE OF L
GATED DECODERS:
GATE ON RISING EDGE OF G
3-43
W
DOO
DOl
D02
D03
Y
The HM-6513 is supplied in two versions. the HM-6513H and the HM6513l. The H or L is used to designate the logic level to be connected
to the Y input. If a HM-6513H is procured the user must connect the
input to VCC in the system. If a HM-6513L is used the Y input must be
connected to system ground.
A6
VCC
AO
Al
A2
A3
A4
A5
A6
A7
AS
The HM-6513 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.
A HIGH -
A5
GND
I
Specifications HM-6513-9
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage - vee
Operating Supply Voltage
Industrial (-9)
+8.0V
Input or Output Voltage Applied
Storage Temperature
GND -O.3V
to vee +O.3V
4.5V to 5.5V
Operating Temperature
Industrial (-9)
-65 0 e to +150oe
-40 o e to +85 0 e
ELECTRICAL CHARACTERISTICS
TEMP.&VCCOPERATING
RANGE
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TEST
CONDITIONS
Standby Supply Current
50
0.1
10
I'A
10:0
VI : vec or GND
leeop
Oper.ting Supply Current@
7
5
6
rnA
I: lMH,. 10 : 0
VI : vee or GND
leCDR
Data Retention Supply Current
25
0.01
5
I'A
10 : 0 vee: 3.0
VI' vee or GND
VeeDR
Data Retention Supply Voltage
2.0
2.0
1.4
Input Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
I'A
GND ~ VI ~vee
Input/Output Leakage' Current
-1.0
+1.0
-0.5
0.0
+0.5
I'A
GND ~ VIO ~ vee
IIOZ
I
MAX
leess
II
D.C.
MIN
TEMP - 250CO)
VCc-s.OV
V
VIL
Input low Voltage
-0.3
O.B
-0.3
2.0
1.5
V
VIH
Input High Voltage
vee
-2.0
vee
+0.3
2.5
2.0
5.3
V
VOL
Output low Voltage
0.35
0.4
V
10: 2.0mA
VOH
Output High Voltage
V
10' -LOrnA
el
Input Capacitance @
B.O
B.O
pF
VI • vce or GND
I : lMHz
elo
Input/Output Capacitance@
10.0
10.0
pF
via: vee or GNO
I : lMHz
TELOV
Chip Enable Access Time
300
170
250
TAVOV
Address Access Time
320
170
270
TELOX
Chip Enable ,Output Enable
Time
100
50
80
ns
ns
ns
@
@
@
lWLOZ
Write El"!able Output Disable
100
50
80
ns
@
100
50
80
ns
@
@
0.45
2.4
3.5
4.0
5.0
6.0
Time
TEHOZ
Chip Enable Output Disable
Time
TELEH
300
250
170
ns
120
100
70
ns
@
20
0
n,
50
20
ns
240
150
ns
240
150
300
240
150
ns
ns
Data Setup Time
200
160
100
Data Hold Time
0
0
-10
@
@
@
@
@
@
@
@
@
@
@
@
@
Chip Enable Pulse Negative
Width
A.C.
NOTES:
1.
2.
3.
4.
TEHEL
Chip Enable Pulse Positive
Width
TAVEL
Address SetuP Time
20
TELAX
Address Hold Time
50
lWLWH
Write Enabte Pulse Width
300
lWLEH
Write Enable Pulse Setup Time
300
TELWH
Write Enable Pulse Hold Time
TOVWH
lWHOZ
ns
ns
ns
ns
lWHEL
Write Enable Read Setup Time
0
0
-10
TOVWL
Data Valid to Write Time
0
0
-10
lWLOV
Write Data Delay Time
100
80
50
TWLEL
Early Output High-Z Time
0
0
-10
ns
ns
TEHWH
Late Output High-Z Time
-10
ns
Read or Write Cycle Time
0
420
0
TELEL
350
240
ns
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: TypicaliCCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC test conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - 1 TTL load and 5OpF; All timing measured at Y,
3-44
vec.
Spllcificatio.ns HM-6513-5
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage - VCC
Input or Output Voltage Applied
Storage Temperature
Operating Supply Voltage
Commercial
+8.0V
GND -O.3V
to VCC +O.3V
-650 C to +150o C
4.75V to 5.25V
Operating Temperature
Commercial
OoC to +75 0 C
ELECTRICAL CHARACTERISTICS
TEMP. & vccOPERATING
RANGE
SYMBOL
ICCSS
Standby Supply Current
ICCOP
Ope~atiiig Supp'ly Current ®
MIN
MAX
MIN
TYP
MAX UNITS
TEST
CONDITIONS
500
100
500
IJA
VI - vce or GND
7
5
6
mA
'-IMHz.IO-O
VI - VCC or GND
IJA
GNDSVI ~VCC
Input Le,akage Current
-10.0
+10.0
-7.0
to.5
+7.0
IIOZ
Input/Output Leakage Current
-10.0
+10,0
-7.0
to.5
+7.0 ... IJA
VIL
Input l?W Voltage
-0.3
0.8
-0.3
2.0
1.5
V
YI.H
In!?ut High V:oltage
VCC
-2.0
VCC
+0.3
2.5
2.0
5.3
V
VOL
Output Low Voltage
0.35
0.4
V
VOH
Output High Voltage
CI
Input Capacitance C!>
8.0
5.0
CIO
Input/Output Capacitance C!>
10.0
II
D.C... ,
PARAMETER
TEMP - 250C G)
vee- s.ov
0.45
2.4
3.5
GND S VIO S VCC
10-1.6mA
V
10 - -0.4mA
8.0
pF
VI - vce or GND
'-lMHz
6.0
10.0
pF
VIO - VCC or GND
'-IMHz
4.0
TELOV
chip Enable Access Time
350
200
300
ns
TAVOV.
Address Access Time
370
200
320
ns
TELOX
Chip Enal;Jle Output Enable
Time
100
50
80
n.
@
@
@
lWLOZ
Write Enable Output" Disable
Time
'100
50·
80
n.
@
80
n.
@
'TEffaZ
Chip Enable Output Disable
TELEH
Chip Enable Pulse Negative
Width
350
300
200
n.
@
TEHEL
Chip Enable Pulse"Positive
Width
150
120
100
ns
@
TAVEL
Address Setup Time
20
20
0
n.
TELAX
Address Hold Time
50
50
20
ns
lWLWH
Write Enable Pulse Width
350
300
200
ns
TWLEH
Write Enable Pulse Setup Time
350
300
200
ns
TELWH
Write Enabtl Pulse Hold Time
350
300
200
ns
TDVWH
Oata Setup Time
250
220
150
n.
@
@
@
@
@
@
@
@
@
@
@
@
@
100
50
I
Time
A.C.
NOTES:
lWHDZ
Data Hold Time
0
0
"10
ns
TWHEL
Write Enable Read Setup·Time
0
0
-10
ns
TDVWL
Output Data Valid to Write Time
0
0
-10
ns
TWLDV
Write Oata Delay Time
100
80
50'
ns
TWLEL
Early.outPut High-Z Time
O'
0
-10
ns
TEHWH
Late Output High~Z Time
0
0
-10
n.
TELEL
Read or Write Cycle Time
500
420
320
n.
1. All d~vices.tested at worst case limits. Room temp .• 5 volt data provided for information - not guaranteed ..
2.•.. Qperating Suppl.v Current (lCCOP) is proportional to Operating F"iquency. Example: Typical.ICCOP = 5mA/MHz.
3. Capacitance sampled and g\laranteed - 1)0\ 100% tested.
4.
AC test conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - 1 TTL. load and 5OpF; All timing measured at Y,
vec.
Read Cycle
TAVEL
A
E
DO
iii
HIGH Z
HIGH
TIME
REFERENCE
t t
-1
TRUTH TABLE
TIME
E
REFERENCE
-1
H
0
'-
1
L
L
2
3
INPUTS
W
A
f
4
H
5
'-
X
H
H
H
H
X
H
DATA 1/0
DO
WNCTION
Z
Z
MEMORY DISABLED
CYCLE BEGINS. ADDRESSES ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID
READ ACCOMPLISHED
PREPARE FOR NEXT CYCLE (SAME AS-lI
CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS OJ
X
V
X
X
X
V
V
X
Z
Z
~
V
The address information is latched in the on chip registers
on the falling edge of E (T = 0). Minimum address setup
and hold time requirements must be met. After the required hold time the addresses may change state without
affecting device operation. During time (T = 1) the output
becomes enabled but data is not valid until time (T = 2).
W must remain high throughout the read cycle. After the
data has been read E may return high (T = 3). This will
force the output buffers into a high impedance mode
at time (T = 4). The memory is now ready for the next
cycle.
Write Cycle
I
TElEL
:;::~::::~J--------'TELEH'------1::::::~=:::1
=:----f----f----f--------it~-I--+
2
3
TIME
REFERENCE·l
Q
TRUTH TABLE
TIME
REFEAENCE
E
INPUTS
Vi
A DO
-1
H
0
'-
1
L
X
X
L
L
.r
2
3
f
H
4
H
5
'-
X
X
X
V
X
X
X
X
V
Z
Z
Z
V
Z
Z
Z
The write cycle is initiated on the fal!ing edge of E (T = 0),
which latches the address information in on ChiP, sgisters.
If a dedicated write cycle is to be performed and the outputs are not to become active TWLEL and TEHWH must be
met. Under these conditions TWLDV is unnecessary and
input data may be applied at any convenient time as long as
FUNCTION
MEMORY DISABLED
CYCLE BEGINS. ADDRESSES ARE LATCHED
WRITE PERIOD BEGINS
DATA IN IS WRITTEN
WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS-1)
CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS OJ
TDVWH is still met. If TWLEL is not met then the outputs
may become enabled momentarily near the beginning of
the cycle and a disable time (TWLOZ) must be met before
the input data is applied (TWLOZ = TWLDV). Similiarly,
if TEHWH is not met the outputs may enable briefly near
the end of the cycle.
3-46
The write operation
(T = 2) or E (T
high time (TEHEL)
of consecutive write
IN
is terminated by the first rising edge of
After the minimum required
the next cycle may begin. If a series
cycles are to be performed, the W line
E
= 3).
may be held low until all desired locations have been
written. In this case, data setup and hold times must be
referenced to the rising edge of f.
Read Modify Write Cycle
f
~~~R~EN~C~E--~-------+------~----~----------~--------~----~--i--------r-
TRUTH TABLE
TIME
REFERENCE
-,
,
0
2
3
E
'N!UTS
W
A
H
X
X
'-
H
H
V
L
L
L
H
L
J
X
X
X
V
Z
V
Z
Z
Z
J
H
X
X
H
X
X
7
'-
H
V
L
Z
Z
X
5
6
4
DATAI/O
DQ
If the pulse width of Vii is relatively short in relation to that
of E a combination read-write cycle may be performed. If.
Vii remains high for the first part of the cycle, the outputs
will become active during time (T = 1). Data out will be
valid during time (T = 2). After the data is read, Wcan go
low. After minumum TWLWH, iii may return high. The
FUNCTION
MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
READ MODE, CUTPUT ENABLED
READ MODE, OUTPUT VALID
WRITE MODE, OUTPUT HIGH Z
WRITE MODE. DATA IS WRITTEN
WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENDS. NEXT CYCLE BEGINS {SAME AS 01
information just written may now be read or E may return
high, disabling the output buffers and preparing the device
for the next cycle. Any number or sequence of readwrite operations may be performed while E is low providing
all timing requirements are met.
NOTES:
In the above descriptions the numbers in parenthesis (T = Xl refer to the respective timing diagrams.
The numbers are located on the time reference line below each diagram. The timing diagrams shown
are only examples and are not the only valid method of operation.
2113 Compatibility
13 ~.~================~'C~Y~============~jrl--;rm
21===1
_______________
A_DD_R_E_SS_V_A_Ll_D______________
ADO
I.
~
~
COMPATIBLE
TIMING
ADO
~~______________A_D_D_R_E~
__V_AL_'D____________~~
&S. E
3-47
2113 -
Requires the Address to Remain Valid
Throughout the Cycle.
6513 -
Requires Valid Address for Only a Small
Portion of the Cycle, but Requires E to
Fall to Initiate Each Cycle.
I
Battery ~a(;kup Application, "
The HM-6513 is especially well suited for use in battery backup systems. Dat~ r~teni:ion supply voltage arid supply
. ..
..'
.... ' . "current are guaranteed over the full temperature range. ._,.
When designing the backup system, the following suggestiOfls s!:lould be considered:
1.) As RAM VCe drops, the input logical one voltages should follow so as n()t..to exceed VCC +0.3. It is
suggested to, use CMOS drivers, operating iltUMOS VCC,suchas t!:le HO~6495, HO':"'S4321;and HD-6433.
AnotheJapprollch is theuM6f open coilectororopen drain buffers pulled upt'o CMOS vec.
2.)
be held higtiat CMOS vec.
VCC to minimize power dissipation.
E must
W,
address and data inputs should"be held-at,either GND or CMOS
3.) When exiti.ngfrom the ~attery backup modfl,: VCC sho.uld ramp without ring:or dis.continuJ.ties.
4.) The RAM can begin . operation one TEHEL after VCCreaches the minimumoperating voltage (4.5 or 4.75
volts).
.
A very simple battery' backup systeril'fii sh()wn in Fig~re .1. When system power is available,. diode D1 is forward
biased and supplies current to the CMOS devices. Upon iossof system power, d.iode D1 is reverse biased and only
CMOS devices are consuming battery power. A disadvantage to this method is that CMOS VCCis one diode drop,
.7, below TTL vec: Ther~ is a possibility that a'TTL output signal could rise 'higher than CMOS, vec and cause
possible latch problems. This possibility can be reduced by incorporating a system similar to that shown in Figure
2. Other alternatives include using a germanuin diod\! yejlding a VF ~ .2V or adding diode D2 in the TTL supply
and raising VCC to account for the drop. A PNP transistor is substituted for the diode in Figure 2. The saturation
drop of the transitor, O.2V, is less than the O.7V drop of the diode giving more ma(gin against·latch-up. A power
fail output signal is available to disable the chip enable circuitry. Open collector TTL with.pullups to CMOS VCC or
LS type TTL should be used as memory drivers. This will insure that the CMOS inputs are not floating during the
backup period. When system power is restored,operation continues as normal and the NI-CAD battery pack is
trickle charged through RC.
' .
.-___;-___.,-___+VCC
IOPTIONALI
r---~--l
I
02
~':::UDI-~t- - ·=-'=.~ :·;~'- -"~ ~ ~ - l-P- R-C~:
..
~_1_-...,.-_t--...,..-cuosvcc
:
_-_
:::SVCC
.,:...NI-CAD
t2AV
FIGURE.1
POWER FAIL
+-------------'
FIGURE 2
Suggestions For 6513 Memory Array Design
The HM-6513 is a device that can be used to. good
advantage in systems which are offered with choices
of memory array size. With one common memory
board layout the designer can easily offer two different .array sizes. This is accomplished' by using the .
conveniently similar pinouts of the HM-6513 (512 by
4) and the HM-6514 (1K by 4). For example,a4K'
by 8 bit array using HM-6513s and a 8K word by
8 bit array using HM-6514s can be easily impleme~ted 9n the .samewinted cirquitcard. The circuit aia'::- ,,gram suggests one impl.ementation requiring only
one jumper wire for 4K or 8K word selection. This
simple jumper wire also allows the 4K array to utili.ze
the HM-6513H or the HM-6513L version.
+VCC
6513H4, JUIIP£R
651. _~..._ _ _ _ ~~ ~AII
IISB
1
AOOR::-7'~'3-_~*-t
6S13!
HD-a..O
"CIIOS
1 OF8
LATCHED
DECODER
DRIVER
'·8 .'
WORO
ENABLE
LINES
,.
',,\~
HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
HM-6514
A DIVISION OF HARAIS CORPORATION
1024 x 4 CMOS RAM
JULY 1978
Features
Pinout
•
LOW POWER STANDBY
•
LOW POWER OPERATION • . • • • . • . • . • • • . . • . . • 35mW/MHz MAX.
•
DATA RETENTION . • . . • . . . . • . . • • . • . • • . . . . • . . @2.0VMIN.
TOP VIEW
... «1mWMAX.
vee
A6
A7
•
TTL COMPATIBLE INPUT/OUTPUT
AS
•
COMMON DATA IN/OUT
A9
•
THREE-STATE OUTPUTS
•
STANDARD JEDEC PINOUT
•
FAST ACCESS TIME • . • . . .
•
MILITARY TEMPERATURE RANGE
•
INDUSTRIAL TEMPERATURE RAN.GE
•
18 PIN PACKAGE FOR HIGH DENSITY
•
ON CHIP ADDRESS REGISTER
. • . . . . . . . . .. 300nsec MAX.
AD
DOD
Al
001
A2
002
E
D03
iN
Description
logic Symbol
vee
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self
aligned silicon gate technology. The device utilizes synchronous circuitry
to achieve high performance and low power operation.
w
AO
Al
On chip latches are provided for the addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to
a high impedance state for use in expanded memory systems.
A2
A3
DOD
A4
001
AS
The HM-6514 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.
A - Address Input
~ - Chip Enable
W- Write Enable
DQ - Data InlOut
Functional Diagram
A9
A8
A7
GATED
A8
DECODER
ROW
84.84
84
MATRIX
A.
A4
GATED COLUMN
DECODER
AND
DATA
INPUTIOUTPUT
ALL LINES ACTIVE HIGH - POSITIVE LOGIC
THREE STATE BUFFERS:
A HIGH OUTPUT ACTIVE
ADDRESS REGISTERS:
LATCH ON RISING EDGE OF L
GATED DECODERS;
GATE ON RISING EDGE OF G
3-49
002
A6
A7
A8
A9
D03
GND
I
Specifications HM-6514-2IHM-6514-9"
ABSOUj.TEMAXIMUM RATINGS,
OPERATING RANGE
Supply Voltagl1 - vee
+8.0V
Input or Output Voltage Applied
Storage Temperature,
Operating Supply Voltage
Military (-2)
Industrial (-9)
GND -O.3V
to Vee+O.3V
-650e to +1500C
4.5V to 5.5V
4 •.5V to 5.5V
Operating Temperature
Military (-2)
Industrial (-9)
-550e to +1250e
-40oe to +850 e '
ELECTRICAL CHARACTERISTICS
TEMP. 8t veeOPERATING
RANGE
SYMBOL
PARAMETER
MIN
MAX
TEMP - 250C
vee-a.ov
MIN
TYP
G>
MAX UNITS
ICCSB
Standby Supply Current
50
0.1
10
/J.A
,10-0
VI =VCC or GND
ICCOP
Operetlng SuPPlY Current <2>
7
5
6
mA
f= lM'Hz. io=o
VI = VCC or GND
26
0.01
5
/J.A
10· OVCC· 3.0
VI = VCC or GND
"
ICCDR
Data Retention SUpply Current
VCCDR
Data Retention Supply Voltage
2.0
2.0
1.4
Input Leakage Current
-1·1l
t1.0
-0.5
0.0
+0.5
1I0Z
Input/OutPut Leakage Current
-1.0
+1.0, ,
-0.5
0.0
+0:5
VIL
Input Low Voltage
-0.3
0.8
-'0.3
2.0
1.5
V
VIH
Input High Voltage
VCC
+0.3
2.5
2.0
5.3
V
0:35
4.0,
0.4'
V
IO-2.OmA
3.5
V
10--t.OmA
8.0
5;0,
8.0
pF
VI - vee or GND
f = lMHz
10.0
6.0
10.0
pF
VO=
or GND
f = lMHz'
IJ
D.C.
vee
-2.0
VOL
Output Low Voltage
VOH
O~tput
CI
I
o
TEST
CON.DITIONS
0:45
High Voltage
,Input Capecitance
2.4
®
CIO
Input/OutPut Capacitance
®
V
/J.A,
/J. A
GND~VI ~VCC
GND
5 VO~VCC
vee
TELaV
Chip Enable AccesS Time
300
170
250
nl
TAVaV
Address Access Time
320
170
270
n.
TELaX
Chip Enable OutPut Enable
100
50
80
n.
@
@
@
100
50
80
nl
@
100
50
8D
n.
@
170
n.
@
70
ns
@
@
@
@
@
@
@
@
Time
TWLaZ
Write Enable Output Disable
Time
/
"
TEHOZ
Chip Enable OutPut Disable
Time
TELEH
Chip Enable Pulse Nagatlv.
TEHEL
Chip Enable Pul.. POlltive
300
" 250
120
100
WI<\th
WI<\th
A.C.
NOTES:
1.
2.
3.
4.
TAVEL
Addres.1 ~p' Time
20
20
0
nl
TELAX
Add.... Hold Tim.
50
50
20
ns
ns
TWLWH
Write Enable Pulle Width
300
240
150
TWLEH
Write Enable Pul.. Setup Time
300
24D
150
n.
TELWH
Write Enable Pulse Hold Time
300
200
240
150
n.
160
100
ns
0
0
ns
0
0
n.
0
n.
TDVWH
Oa.. SetuP Tiine
TWHDZ
Data Hold Tilne
TWHEL
Write Enable Rnd Setup TIm.
0
0'
TQVWL
Data Valid to Write Time
6
0
TWLDV
Write DIte Otley Tim.
100
80
50
n.
TWLEL
Early OutPut High-Z Time
D
0
-10
n.
TEHWH
Late OutPUt High-Z TIm.
0
350
n.
Read .or Write Cycle Time
0
420
-10
TELEL
240
n.
@
@
@
@
@
@
All devlees tested at worst case limits. Room temp.,5yolt data provided for information - not guarantead.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = SmA/MHz.
Capacitance sampled and guarantead - not 100% tested.
AC test conditions: Inputs - TRISE = TFALL = 20nsee; Outputs'- 1 TTL load and SOj:jF; All timing mellstired'at,% VCC." .
3-50
Specifications HM-6514-5
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage - VCC
Input or Output Voltage Applied
Storage Temperature
+8.0V
GND -O.3V
to VCC +O.3V
-650C to +150oC
Operating Supply Voltage
.Commercial
I
4.75V to 5.25V
Operating Temperature
Commercial
OoC to +75 0 C
ELECTRICAL CHARACTERISTICS
TEMP. & VCCOPERATING
RANGE
SYMBOL
Iccsa
Standby Supply Current
leeop
Operating Supply Current (2)
MIN
MAX
MIN
TYP
MAX UNITS
TEST
CONDITIONS
500
100
500
IJA
VI - vee or GNO
7
5
6
mA
f - 1MHz. 10 - 0
VI - vee or GNO
Input Leakage Current"
-10.0
.10.0
-7.0
jJA
GNO:$ VI :$ vee
Input/o.utput Leakage Current
-10.0
.10.0
-7.0
±a.5
±a.5
+7.0
IIOZ
+7.0
jJA
GND Svo:$vee
VIL
Input Low Voltage
-0.3
0.8
-0.3
2.0
1.5
V
VIH
Input High Voltage
vee
-2.0
vee
+0.3
2.5
2.0
5.3
V
VOL
Output Low Voltage
0.35
0.4
V
VOH
Output High Voltage
II
D.C.
PARAMETER
TEMP - 250C (j)
VCC-5.0V
0.45
2.4
<_________A_O_O_RE_~_VA_l_IO________~
ti. E
3-53
Battery Backup Applications
The HM-6514 is especially well suited for use in battery backup systems. Dataretention supply voltage and supply
current are guaranteed over the full temperature range.
When designing the backup system, the following suggestions should be considered:
1.) As RAM vce drops, the input logical one voltages should follow so as not to exceed VCC +0.3. It is
suggested to use CMOS drivers, operating at CMOS VCC, such as the HD-6495, HD-6432, and HD-6433.
Another approach is the use of open collector or open drain buffers pulled up to CMOS VCC.
2.)
E must be held high at CMOS VCC. W, address and data inputs should beheld at either GND or CMOS
VCC to minimize power dissipation.
3.) When exiting from the battery backup mode, VCCshould ramp without ring or discontinuities.
4.) The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 or 4.75
volts).
A very simple battery backup system is shown in Figure 1. When system power is available, diode D1 is forward
biased and supplies current to the CMOS devices. Upon loss of system power, diode D 1 is reverse biased and only
CMOS devices are consuming battery power. A disadvantage to this method is that CMOS VCC is one diode drop,
.7V, below TTL VCC. There is a possibility that a TTL output signal could rise higher than CMOS VCC and cause
possible latch problems. This possibility can be reduced by incorporating a system similar to that shown in Figure
2. Other alternatives include using a germanuin diode yielding a VF ~ .2V or adding diode D2 in the TTL supply
and raising VCC to account for the drop. A PNP transistor is substituted for the diode in Figure 2. The saturation
drop of the transistor, O.2V, is less than the 0.7V drop of the diode giving more margin against latch-up. A power
fail output signal is available to disable the E circuitry. Open collector TTL with pullups to CMOS VCC or LS type
TTL should be used as memory drivers. This wiHinsure that the CMOS inputs are not floating during the backup
period. When system power is. restored, operation cdntinues as normai and the NI-CAD battery pack is trickle
charged through RC.
r-oM-
I
:
:
IOPTIONAL)
I
••
ooo --"'--'
02
L __ - T - - _.J
SYSTEM
}-~~
________
~
____________
~
____
~VCC
POWER
L....--------1. .-------------_----.CMOS vcc
RC
-=-
i
NI-CAD
2.4V
FIGURE 1
r---~---~~------~----------VCC
,...--1f----_t"----+----.....,-+CMOS vcc
ftC
-=-
NI-CAD
-
POWER FAIL
1
4_----------------_----------'
FIGURE 2
3-54
2.4V
HARRIS
HM-6518
SEMICONDUCTOR
PRODUCTS DIVISION
1024
A DIVISION OF HARRIS CORPORA nON
1 CMOS RAM
X
JULY 1978
Features
Pinout
TOP VIEW
• LOW STANDBY POWER . . • • . . . . • . • • . • • • . • • • . • • . . 551lW MAX
• LOW OPERATING POWER • . • • • • • • . • • . • • • . • • • • • 22mW/MHz MAX
• FAST ACCESS TIME . • • • • • . • • • • • • . . • • . • . • • • • . . l80nlee MAX
• DATA RETENTION VOLTAGE . • • . • • • . • . • . • • • • . • 2.0 VOLTS MIN
•
•
•
•
•
•
•
•
TTL COMPATIBLE IN/OUT
HIGH OUTPUT DRIVE - 2 TTL LOADS
HIGH NOISE IMMUNITY
ON CHIP ADDRESS REGISTER
TWO CHIP SELECTS FOR EASY ARRAY EXPANSION
THREE STATE OUTPUTS
MILITARY TEMPERATURE RANGE
INDUSTRIAL TEMPERATURE RANGE
51
vcc
AO
D
At
Vi
A2
A9
A3
AS
A4
A7
Q
A6
"",,-_ _- f " A5
A -ADDRESS INPUT
-CHIP ENABLE
-CHIP SELECT
Description
E
S
The HM-6518 is a 1024 by 1 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.
iN -WRITE
ENABLE
D - DATA INPUT
Q -DATA OUTPUT
logic Symbol
On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers
can be forced to a high impedance state for use in expanded memory
arrays.
AO
At
A2
A3
A4
A5
A6
D
Q
A7
The HM-6518 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.
AS
A9
GND
I
Functional Diagram
A5
A6
A7
A8
A9
D~----------~ ~--------~
>----<00
A
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
Vi
A
LATCHED
ADDRESS
REGISTER
THREE STATE BUFFERS:
A HIGH --- OUTPUT ACTIVE
DATA LATCH:
L HIGH --- Q= D
o LATCHES ON RISING EDGE OF L
ADDRESS REGISTERS AND DECODERS:
LATCH ON RISING EDGE OF L
GATE ON RISING EDGE OF G
AO At A2 A3 A4
3-55
Specifications HM-6518B-2IHM-6518B-9
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
....
Supply Voltage -:-vee
+8.0V
Input or Output Voltage Applied
Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
GND -O.3V
to vee +O.3V
Operating Temperature
Military (-2)
Industrial (-9)
-650 e to +150 0 e
Storage Temperature
4.5V to 5.5V
4.5Vt05.5V
-55 0 e to +1250 C
-4ooe to +85 0 e
ELECTRICAL CHARACTERISTICS
SYMBOL
ICCSB
Standby S'upply Current
ICCOP
Operating Supply Current
ICCDR
Data Retention Supply c,urrent
VCCDR
Data Retention Supply Voltage
I
MIN
MIN
MAX
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: TvpicaliCCOP = 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - 1 TTL load and 5OpF. All timing measurements
at 1/2 VCC.
3-58
Rlllld Cye/II
• ______-=HI=-~__~r_---------------------------------------
I': ~
I----TlLClY~
TlLAX
~"""'--~V~lW=DOU1ftIT='~,~.=;=D~~-=-L~-Z
.
......':-----1t----l!I--------J.---+-+---+-t
-1--1
-1
•
•
•
TRUTH TABLE
TIME
REFERENCE
-1
0
1
2
3
4
5
OUTPUT
INPUTS
A
0
Q
X
H
H
H
H
X
H
X
X
X
X
X
X
X
Z
Z
Ill" !CI>W
H H
"\..X
L L
L L
..rL
H H
'-X
X
V
X
X
X
X
V
FUNCTION
'.
MEMORY DISABLE'D
CYCLE BEGINS. ADDRESSES ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID
OUTPUT LATCHED
DEVICE DISABLED. PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 0)
X
V
V
Z
Z
G) Device selectad only If both 51 and !2 are low. and de••lected If either 51 or n are high.
NOTES:
must be, low, W must be high. When E goes high the output data is latched into an on chip register. Taking either
or both Sf or"S2 high forces ,the output buffer to a high'
impedance state. The output data' may be re-enabled
at any time by taking Sf and 52 low. On the falling edge
of E the data will be unlatched.
In the HM-6518 read ,cycle the ,address information is
latched into the on chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time require- '
ments must be met. ! Setup Time
Time
1.
2.
3.
4.
400
200
200
200
200
600
200
400
25
75
220
220
220
220
220
130',
,
,!'io, :'.'
.'~O
50
220
>
200
350
2\;
75
130
130
130
130
L 130
0100
:
50
100
50
"30
300 350
.HO 1.50
110 150
110 150
110 150
475 SeQ
175
300
10
60
110
110
110
110
ns
ns.
ns
ns
ns
n~
ns
ns
ns
ns
ns
I··' ns
n$
ns
HO
n~;
70
40
~O
40
ns
ns
ns
ns
JOO.
nl':
(4)
(4)
(41..
.
'.
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
..
"
All devices te~ted at worst casaUml'ts.
Room temperature,'5V -dlItaprovided for in,formation _ not guaranteed.
Operatlpg supply current (lCCOP) is proportional to:op8rating,trequency. Exampte: TypicallCCOP = SmA/MHz.
Capaci~a~ce~mpled and ~l!arartiee<;l·~ ·l;Iot 1QO% testtid. ;,
AC test conditions: Inputs - Trise = Tfall .; 20ns.
Outputs - 1 TTL I-ojid alld. 5QpF,.
Specifications HM-6533C-9
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage-Vee
Applied Input or Output Voltage
Storage Temperature Range
+8.0V
GND-O.3V
Vee+O.3V
Operating Supply
Voltage-Vee
-65 0 e to
4.5V to 5.5V
Operating Temperature Range
-400 e to +85 0 e
+150 oe
ELECTRICAL CHARACTERISTICS
vee & TEMP =
OPERATING
RANGE
SYMBOL
D.C.
ICCSB
Standby Supply Current
ICCOP
II
10Z
VIL
VIH
VOL
VOH
CI
Operating Current (2)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Capacitance (3)
CIO
Output Capacitance (3)
TELQV
TSLQX
TSHQZ
TGLQX
TGHQX
TELEL
TEHEL
TELEH
TAVEL
A.C.
PARAMETER
TELAX
TWLWH
TWLEH
TELWH
TWLSH
TSLWH
TDVWH
TWHDX
TDVSH
TSHDX
TSLSH
NOTES:
Chip Enable Access Time
Chip Select Output Enable Time
Chip Select Output Disable Time
Output Enable Time
Output Disable Time
Read or Write Cycle Time
Chip Enable Positive Pulse Width
Chip Enable Negative Pulse Width
Address Setup Time
Address Hold Time
Write Enable Pulse Width
Write Enable Pulse Setup Time
Chip Enable Write Pulse Hold Time
Chip Select Write Pulse Setup Time
Chip Select Write Pulse Hold Time
Data Setup Time
Data Hold Time
Data to Ch ip Select Setup Time
Data to Chip Select Hold Time
Chip Select Write Setup Time
1.
2.
3.
4.
MIN
MAX
MIN
TYP MAX
UNIT
10=0.
VI = VCC or GND
mA
F = 1MHz, 10 = 0
GND-+'-.,.,.,.-----'---------1-1
o
GATED
COLUMN
DECODER
AND DATA
INPUT/ounUT
DATA
ou'nUT
LATCHES
o
Ql
02
.3'0----i >+_________...J
03
SELECT LATCH:
L LOW·....'d-D·
Q LATCHES ON RiliNG EDGE OF L
; ADDFIESS L.ATCHES AND GATED DECODERS
:
LAT~HONfUSINGEOaEOFL
GATE ON R.lS1N,P EDGE OF G
3:-74
Specifications HM-6551B-2IHM-6551B-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
OPERATING RANGE
-vee
+8.0V
Applied Input or Output Voltage
Operating Supply Voltage
Military (-2)
Industrial (-9)
GND -O.3V
+O.3V
vee
Operating Temperature
Military (-2)
Industrial (-9)
-650 e to +1500 e
Storage Temperature
-vee
4.5V to 5.5V
4.5V to 5.5V
-550 e to +125 0 e
-40 0 e to +85 0 e
ELECTRICAL CHARACTERISTICS
SYMBOL
D.C.
PARAMETER
ICCSB
Standby Supply Current
ICCOP
Operating Supply Current@
ICCDR
Oata Retention Supply Current
VCCDR
Data Retention Supply Voltage
TEMP. = 25 0 C
VCC =5.0V
MIN
MIN
MAX
CD
TYP MAX UNITS
TEST
CONDITIONS
10
1 (+25 0 CI
0.1
1
!J.A
10 =0
VI = VCC or GND
4
1.5
25
mA
f = 1 MHz, 10 = 0
VI = VCC or GND
10
0.01
1
!J.A
VCC = 3.0, 10 = 0
VI = VCC or GND
2.0
1.4
Input Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
!J.A
GND~ VI ~
10Z
Output Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
!J.A
GND~ VO~ VCC
V
II
2.0
V
VIL
Input Low Voltage
-0.3
0.8
-0.3
2.0
1.5
VIH
Input High Voltage
VCC -2.0
VCC +0.3
2.5
2.0
5.3
V
VOL
Output Low Voltage
0.2
0.35
V
VOH
Output High Voltage
CI
Input Capacitance@
6
4
CO
Output Capacitance@
10
220
0.4
2.4
3.0
TELOV
TAVOV
Chip Enable Access Time
Address Access Tim"e
TS1LOX
TWLOZ
Chip Select 1 Output Enable Time
220
130
Write Enable Output Disable Time
130
TS1HOZ
Chip Select 1 Output Disable Time
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
TELEH
TEHEL
TAVEL
A.C.
TEMP. & VCC=
OPERATING
RANGE
Address Setup Time
Chip Select 2 Setup Time
TS2LEL
TELAX
TELS2X
Address Hold Time
TDVWH
TWHDX
Chip Select 2 Hold Time
Data Setup Time
Data Hold Time
TWLS1H
TWLEH
TSl LWH
TELWH
TWLWH
TELEL
NOTES:
130
220
100
170
70
0
0
0
40
0
40
40
100
40
80
0
100
vec
IOL = 3.2mA
V
IOH =-0.4mA
6
pF
VI = VCC or GND
f = 1 MHz
6
10
pF
VO= VCC or GND
f = lMHz
120
110
170
170
ns
50
90
50
90
ns
ns
50
120
50
-10
90
@)
@
@
@)
@
@
@)
@
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
4.5
ns
ns
ns
ns
ns
-10
ns
20
20
50
ns
ns
ns
ns
ns
Chip Select 1 Write Pulse Setup Time
Chip Enable Write Pulse Setup Time
0
120
120
100
60
60
Chip Select 1 Write Pulse Hold Time
120
100
60
ns
Chip Enable Write Pulse Hold Time
Write Enable Pulse Width
Read or Write Cycle Time
120
120
320
100
100
240
60
60
170
ns
ns
ns
0
ns
1.
2.
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 1.5mA/MHz.
3.
Capacitance sampled and guaranteed - not 100% tested.
4.
AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - 1 TTL load and 50pF. All timing measurements
at 1/2 VCC.
3-75
I
SpecilicationsHM-6551-2IHM-6551-9
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-vee
Operating Supply Voltage
Military (-2)
Industrial (-9)
+8.0V
Applied Input or Output Voltage
GND -O.3V
vee +O.3V
Operating Temperature
Military (-2)
Industrial (-9)
-65 0 e to +1500 e
Storage Temperature
-vee
4.5V to 5.5V
4.5V to 5.5V
-550 e to +125 0 e
-40 0 e to +85 0 e
ELECTRICAL CHARACTERISTICS
SYMBOL
D.C.
I
A.C.
PARAMETER
TEMP. & VCC=
OPERATING
RANGE
TEMP. = 25 0 C
vee = 5.0V
MIN
MIN
MAX
------r-----:-J
A'o----,i
A20----,i
.. 0--,.--1
..
32X 32
MATRIX
"'cr,.,---:-t........,-:--.J
--f-oC
LATCHES AND GATED DECODERS
LATCH-ON RISING EDOE OF L
GATE ON RIIINGLEDOE OF G
DQ3
Ii
Ii
12
0--""'-11-<
cOLUMN
DECODER
AND·
DATA.IN/OUT
Specifications HM-6561B-2IHM-6561B-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
OPERATING RANGE
-vee
Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
+8.0V
Input or Output Voltage Applied
GND -O.3V
to vee +O.3V
Operating Temperature
Military (-2)
Industrial (-9)
-65 0 e to +150o e
Storage Temperature
4.5V to 5.5V
4.5V to 5.5V
-55 0 e to +125 0 e
-40o e to +850 e
ELECTRICAL CHARACTERISTICS
SYMBOL
D.C.
ICCSB
Standby Supply Current
ICCOP
Operating Supply Current@
ICCDR
Data Retention Supply Current
VCCDR
1/
I/OZ
Data Retention Supply Voltage
TEMP. = 250 C
VCC= 5.0V
MIN
MIN
MAX
CD
TYP MAX UNITS
0.1
1
JlA
10=0
VI = VCC or GND
4
1.5
2.5
mA
f = 1MHz, 10 = 0
VI = VCC or GND
10
0.01
1
JlA
VCC = 3.0, 10 = 0
VI=VCCorGND
2.0
1.4
I nput Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
JlA
GND~ VI ~VCC
I nput/Output Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
GND ~VO~VCC
2.0
V
VIL
Input Low Voltage
-0.3
0.8
-0.3
2.0
1.S
VIH
Input High Voltage
VCC -2.0
VCC +0.3
2.5
2.0
5.3
V
VOL
Output Low Voltage
0.2
0.35
VOH
Output High Voltage
CI
Input Capacitance@
6
4
I "put/Output Capacitance @
10
220
220
120
120
120
TELQV
TAVQV
TSLQX
TWLQZ
TSHQZ
TELEH
TEHEL
TAVEL
TELAX
TDVWH
TWHDX
TWLDV
TWLSH
TWLEH
TSLWH
TELWH
TWLWH
TWLSL
TSHWH
TELEL
NOTES:
1.
2.
3.
4.
TEST
CONDITIONS
10
1 (+25 0 C)
JlA
V
CIO
A.C.
PARAMETER
TEMP.S, VCC =
OPERATING
RANGE
Chip Enable Access Time
Address Access Time
Chip Select Output Enable Time
Write Enable Output Disable Time
Chip Select Output Disable Time
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Write Data Delay Time
Chip Select Write Pulse Setup Time
Ch ip Enable Write Pulse Setup Time
Chip Select Write Pulse Hold Time
Chip Enable Write Pulse Hold Time
Write Enable Pulse Width
Early Output High Z Time
Late Output High Z Time
Read or Write Cycle Time
0.4
2.4
3.0
220
100
0
40
100
0
120
220
220
220
220
220
0
0
320
170
70
0
30
80
0
90
170
170
170
170
170
0
0
230
4.5
V
10L = 3.2mA
V
10H =-O.4mA
6
pF
VI = VCC or GND
f = lMHz
6
10
pF
VO = VCC or GND
f = lMHz
120
110
170
170
50
50
50
120
SO
-10
20
50
0
50
100
100
100
100
90
90
90
ns
ns
ns
ns
ns
ns
ns
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
100
-10
-10
170
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: InputS - TRISE = TFALL = 20nsec; Outputs - 1 TTL load and 50pF. All timing measurements
at 1/2 vce.
3-81
I
SpecificationsHM~6661-2/HM-6661-9
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
Supply Voltage -vee
+8.0V
Input or Output Voltage Applied
Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
GND -O.3V
to vee +O.3V
Operating Temperature
Military (-2)
Industrial (-9)
-650 e to +1500e
Storage Temperature
4.5V to 5.5V
4.5V to 5.5V
-550e to + 1250 e
-400 e to +850 e
ELECTRICAL CHARACTERISTICS
SYMBOL
I
MIN
MIN
MAX
cCD
TYP MAX UNITS
TEST
CONDITIONS
1.0
1
JlA
10=0
VI = VCC or GND
Operating Supply Current@
4
1.5
2.5
mA
f= lMHz, 10=0
VI = VCC or GND
Data Retention Supply Current
10
0.1
1
JlA
VCC = 3.0, 10 = 0
VI = VCC or GND
Standby Supply Current
ICCOP
ICCDR
2.0
1.4
Input Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
JlA
GND~VI ~ VCC
IIOZ
Input/Output Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
GND~VO~VCC
VIL
Input Low Voltage
-0.3
0.8
.0.3
2.0
1.5
JlA
V
VCC -2.0
VCC+0.3
2.5
II
Data Retention Supply Voltage
2.0
2.0
5.3
V
0.35
V
Input High Voltage
Output Low Voltage
VOH
Output High Voltage
CI
I nput Capacitance @
6
4
I nput/Output Capacitance@
10
300
300
150
150
150
CIO
TDVWH
TWHDX
TWLDV
TWLSH
TWLEH
TSLWH
TELWH
TWLWH
TWLSL
TSHWH
TELEL
NOTES: 1.
2.
3.
4.
0.4
Chip Enable Access Time
Address Access Time
Chip Select Output Enable Time
Write Enable Output Disable Time
Chip Select Output Disable T'ime
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Write Data Delay Time
Chip Select Write Pulse Setup Time
Chip Enable Write Pulse Setup Time
Chip Select Write Pulse Hold Time
Chip Enable Write Pulse Hold Time
Write Enable Pulse Width
Early Output High Z Time
Late OutpUt High Z Time
Read or Write Cycle Time
3.0
2.4
240
70
300
100
0
50
150
0
150
300
300
300
300
300
0
0
400
0
40
120
0
120
240
240
240
240
240
0
0
310
V
0.2
VIH
VOL
TELQV
TAVQV
TSLQX
TWLQZ
TSHQZ
TELEH
TEHEL
TAVEL
TELAX
A.C.
TEMP. = 25 0
VCC= 5.0V
10
1 (+25 0 C)
ICCSB
VCCDR
D.C.
PARAMETER
TEMP; & VCC =
OPERATING
RANGE
10L = 3.2mA
V
IOH =-0.4mA
6
pF
VI = VCC or GND
f = lMHz
6
10
pF
VO= VCC or GND
f = lMHz
160
150
240
240
120
120
120
ns
ns
ns
ns
ns
ns
@
@
@
@)
@
@
@)
@
@
@)
@
@
@
@
@
@)
@
@
@
@
4.5
60
60
60
160
50
-10
30
100
0
60
160
160
160
160
160
-10
-10
210
ns
ns'
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: ,TypicalICCOP = 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - 1 TTL load and 50pF. All timing measurements
at 1/2 VCC.
3-82
Specifications HM-6561-5
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
OPERATING RANGE
-vcc
+8.0V
Applied Input or Output Voltage
Storage Temperature
Operating Supply Voltage
Commercial
-vcc
4.75V to 5.25V
GND -O.3V
VCC+O.:W
Operating Temperature
Commercial
-65 0 C to +150 0 C
ooC to 75 0 C
ELECTRICAL CHARACTERISTICS
TEMP. & vee =
OPERATING
RANGE
SYMBOL
ICCSB
Standby Supply Current
ICCOP
Operating Supply Current@
VCCDR
D.C.
Data Retention Supply Voltage
MAX
MIN
MIN
TYP MAX UNITS
TEST
CONDITIONS
100
10
100
JlA
10= 0
VI = VCC or GND
4
1.5
2.5
mA
f = 1 MHz, 10 = 0
VI = VCC or GND
2.0
V
2.0
Input leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
JlA
GND ~VI ~VCC
IIOZ
Input/Output Leakage Current
-1.0
+1.0
-0.5
0.0
+0.5
JlA
GND ~VO~ VCC
VIL
I nput Low Voltage
-0.3
0.8
-0.3
2.0
1.5
V
VCC -2.0
VCC+0.3
2.5
2.0
5.3
V
0.2
0.35
V
II
VIH
I nput High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
CI
I nput Capacitance@
6
4
Input/Output Capacitance@
10
350
CIO
A.C.
PARAMETER
TEMP. = 250 e (j)
vee = 5.0V
TELQV
TAVQV
TSLQX
TWLQZ
TSHQZ
TELEH
TEHEL
TAVEL
TELAX
TDVWH
TWHDX
TWLDV
TWLSH
TWLEH
TSLWH
TELWH
TWLWH
TWLSL
TSHWH
TELEL
NOTES: 1.
2.
3.
4.
Chip Enable Access Time
Address Access Time
Chip Select Output Enable Time
Write Enable Output Disable Time
Chip Select Output Disable Time
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold'Time
Write Data Delay Time
Chip Select Write Pulse Setup Time
Chip Enable Write Pulse Setup Time
Chip Select Write Pulse Hold Time
Chip Enable Write Pulse Hold Time
Write Enable Pulse Width
Early Output High Z Time
Late Output High Z Time
Read or Write Cycle Time
0.4
2.4
3.0
360
180
180
180
350
150
10
70
170
0
200
350
350
350
350
350
0
0
500
300
130
10
50
140
0
170
300
300
300
300
300
0
0
430
IOL=1.6mA
V
10H = -0.2mA
6
pF
VI = VCC or GND
f = lMHz ,
6
10
pF
VO= VCC or GND
f = lMHz
200
200
80
80
80
200
90
0
40
120
0
60
200
200
200
200
200
-10
-10
290
300
310
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
4.5
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (iCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - 1 TTL load and 50pF. All timing measurements
at 1/2 VCC.
3-83
I
Readey,;l;
w~~~--------~--------------------------~-------~ PRfiylOUS DATA
__~
.' HIGH Z
VALID DATA LATCHED
-jTIHQZ .
il.•z_--'-l£..oI~£"£.£..:.~~~F>-~_ _ _ _ _ _ _ _ _-'-__
4¥Z£Z£Z£Z-/.6~~..::o~..:l).:...::...::$~"
AEF~::~------~~--+--4~-------4~--------t------tr-------tt--4fr'-3
••
TRUTHTABLE
TIME
REFERENCE
E
INPUTS
51 Vi A,
H' H
-1
""-
0
X
L
L
L' L
L
f
H
H
X
""-
l'
2
3
4
5
X
H
H
H
H
X
H
OUTPUT
DQ
FUNCTION
Z
Z
X
V
V
Z
Z
MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID
OUTP,UT LATCHED
DEVICE DISABLED, PREPARE FOR NEXT CYCLE, (SAME AS -1)
-CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)
X
V
X
X
X
X
V
NOTES: 1) Deyice selected only If,both
S1andS2 are low. and deselected
I
If,elther 51 or
52 are high.
The HM-6561 has output data latches that are controlled
by E. ' On the rising edge of ~ the present data is latched
and remains latched until E falls. Either or both 51 or 52
may be used to force,the output buffers into a highimpedance state.
The HM-6561 Read Cycle is initiated on the falling edge
of E. This signal latches the input address word into on
chip registers. Minimum address setup and hold, times
must be met. After the required hold time, the address
lines may change state without affecting device operation.
In order to read the output data E. 51 and 52 must'be low
and IN must be high. The output data wiH be valid at access,
time (TELaV).
Write Cycle
TAVEL
nlU
TEUH
TEMEL
f
TWLEH
TELWH
twLWH
W
lWHDX
DO
HIGft Z
HtGH Z
TWLSL
I'WLIH
ii,li
t•
t
TIME
.,
REFERENCE
t
t
2
t• t•
TRUTH TA,BLE
TIME
REFERENCE
-1
E
H
1
""L
2
3
f
4
H
5
""-
0
L
INPUTS
51 Vi A'DQ
H
X
L
L
X
H
X
X
X
L
X
V
X
FUNCTION
Z
MEMOflY DISABLED
CY,CLE BEGINS, ADD,Rt::SSES ARt:: LATCHED,
WRITE PER.lOD BEGINS
DATA IN IS WRITTEN
WRITE IS COMPLETED
PREPARE FOR' NEXT CYCLE (SAME AS -1)
CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)
Z'
Z
fX V
H
X
X
X
X
V
Z
Z
Z
NOTES: 1) Device selecte(l only If both
51
and '$'2 ,ar~ low, and deselected if either S1
3-:-84
or"S2 are high.
In the Write. Cycle the falling edge of E latches the addresses into on chip registers. The write portion of the
cycle is defined as E, IN, 81, and 52 being low simultaneously. IN may go low anytime during the cycle provided
that the write enable pulse setup times (TWLEH and
TWLSH) are met. The write portion ofthe cycle is terminated by the first rising edge of E, IN, 81 or 52. Data setup
and hold times must be referenced to the terminating
signal.
ination read-write cycle is executed.
Data may be modified an indefinite number of times during
any single write cycle (TELEH).
Data mUltiplexing is done internal to the chip and is controlled by IN. WhenIN goes low, the output buffers are
forced to a high impedance state. After one output disable
time (TWLOZ) input data may be applied to the bus.
If it is desired that the output buffers not become active
during the write cycle, IN should go low with or before
81, or 52 (TWLSLI. It should also change to a high state
after 81 or S2 goes high (TSHWH). Thus, TWLSL and
TSHWH may be ignored unless the system design requires
that the data outputs never become active during a write
cycle. If the specified TWLSL time is met, the TWLDV
time may be ignored. Data may then be applied to the
bus whenever convenient since the output is guaranteed not
to become active.
If a series of consecutive write cycles are to be performed,
the IN line may remain low until all desired locations
have been written. When this method is used, data setup
and hold times must be referenced to the first rising edge
of E, 81, or 52. By positioning the write pulse at different
times within the E low time (TELEH), various types of
write cycles may be performed.
If the E low time (TELEH) is greater than the W pulse
(TWLWH) plus an output enable time (TWHOX). a comb-
Battery Backup Applications
The HIIi1-6561 is especially well suited for use in battery backup systems. Data retention supply voltage and supply current are
guaranteed over the full temperature range.
When designing the backup system, the following suggestions should be considered:
1.)
As RAM VCC drops, the input logical one voltages should follow so as not to exceed VCC +0.3. It is suggested to use CMOS drivers, operating at CMOS VCC, such as the HD-6495, HD-6432, and HD-6433. Another approach is the use of open collector or open drain buffers pulled up to CMOS VCC.
2.)
E and
3.)
When exiting from the battery backup mode, VCC should ramp without ring or discontinuities.
4.)
The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 or 4.75V).
one of S1 or S2 must be held high at CMOS VCC.
GND or CMOS VCC to minimize power dissipation.
W,
address, data, and the other S should be held at
A very simple battery backup system is shown in Figure 1. When system power is available, diode D1 is forward biased and
supplies current to the CMOS devices. Upon loss of system power, diode D1 is reverse biased and only CMOS devices are
consuming battery power. A disadvantage to this method is that CMOS VCC is one diode drop, .7V, below TTL VCC. There
is a possibility that a TTL output signal could rise higher than CMOS VCC and cause possible latch problems. This possibility
can be reduced by in<;orporating a system similar to that shown in Figure 2. Other alternatives include using a germanuin diode
yielding a VF ~ .2V or adding diode D2 in the TTL supply and raising VCC to account for the drop. A PNP transistor is
substituted for the diode in Figure 2. The saturation drop of the transistor, 0.2V, is less than the 0.7V drop of the diode giving
more margin against latch-up. A power fail output signal is available to disable the E circuitry. Open collector TTL with
pullups to CMOS VCC or LS type TTL should be used as memory drivers. This will insure that the CMOS inputs are not
floating during the backup period. When system power is restored, operation continues as normal and the NI-CAD battery
pacK is trickle charged through RC.
- --,
IOPTlONALI
-- --
*l
SYSTEM ,-,=-'----'--~
POWER
~~~~~: C3D1--~_ _-_-_-;-"T_--_-_"_ _ _ _ _ _...: vee
~OII-----C--'---'-'I
-=-
i
r--+--r-+--~-
""."
-=-=-
NI-CAO
2.4V
POWER fAIL
+--------------.1
FIGURE 2
FIGURE 1
3-85
CMQSVCC
NI-CAO
2.4V
1
I
HARRIS
HM-6562
SEMICONOUCTOR
PROOUCTS DIVISION
A. DIVISION OF HARRIS CORPORATION
256 x 4 CMOS RAM
JULY 1978
Features
Pinout
•
•
•
•
•
•
•
•
•
•
•
•
TOP VIEW
LOW POWER STANDBY
. . . . . . . . . . . . . . . .. 55J.lW MAX
LOW POWER OPERATION. . . . • • . • • • . . • . • • • .• 22mW/MHz MAX
FAST ACCESS TIME . . . . . . . . . . . . . . . . . . . . . . .. 220nsec MAX
DATA RETENTION VOLTAGE • . • . • • . • . • • • • . . "
2.0 VOL TS MIN
TTL COMPATIBLE INIOUT
HIGH OUTPUT DRIVE - 2 TTL LOADS
HIGH NOISE IMMUNITY
ON CHIP ADDRESS REGISTER
16 PIN.PACKAGE FOR HIGH DENSITY
THREE-STATE OUTPUTS
MILITARY TEMPERATURE RANGE
INDUSTRIAL TEMPERATURE RANGE
vcc
A3
A4
IV
E
003
002
DOl
000
Description
The HM-6562 is a 256 by 4 static CMOS RAM fabricated using selfaligned .silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.
A - Address Input
Chip Enable
E-
iN -
Write Enable
DO - Data I nlOut
logic Symbol
On chip latches are provided for address allowing for efficient interfacing
with microprocessor systems. The data output buffers can be forced to a
high impedance state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus compatibility.
E vcc IV
AO
Al
A2
A3
A4
AS
A6
A7
The HM-6562 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.
The HM-6611, 256 x 4 CMOS PROM, is pin for pin replaceable with the
HM-6562. This allows a single memory board design with any organization of RAM and PROMs.
000
DOl
D02
D03
"::" GND
I~--------------------~----------~
Functional Diagram
AO
A20----1
32x32
"
.3
MATRIX
A4~--,-_.----,
000
o--~~-<
r-------+--+--l
ALL UNES POSITIVE LOGIC· ACTIVe HIGH
THREE STATE BUFFERS:
A HIGH _
OUTPUT ACTIVE
GATED
00.0-----<>--+-0("
COI,UMN
r-------+-....._+_-I
DECODER
AND
DATA INIOUT
ADDRESS LATCHES AND GATED DECODES
LATCH ON· RISING EDGE OF L
GATE'ON RISING EDGE OF G
DO'o---~+<
r-------+-....._+_-I
D03 o----<~_+_<
r-------+-....J
A5
3-86
A6
A7
Specifications HM-6562B-2IHM-6562B-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
OPERATING RANGE
-vee
+8.0V
Input or Output Voltage Applied
Operating Supply Voltage
Military (-2)
Industrial (-9)
GND -O.3V
to vee +O.3V
Operating Temperature
Military (-2)
Industrial (-9)
-65 0 e to +150 0 e
Storage Temperature
-vee
4.5V to 5.5V
4.5V to 5.5V
-55 0 e to +125 0 e
-40 0 e to +85 0 e
ELECTRICAL CHARACTERISTICS
SYMBOL
D.C.
ICCSB
Standby Supply Current
ICCOP
TEMP. = 25 0 e
vee = 5.0V
MIN
MIN
MAX
2.35 and < VCC +0.3
volts). *
14. Wait 1 microsecond.
15. Compare the output data with the desired data.
PROGRAMMING STEPS:
INITIALIZE:
VCC = +10.0V ± 10%
p=VCC
E = GND (not used during programming)
a.
If any bit fails to verify, reject the device as
defective.
b.
If all four bits verify, return to step 13 to verify
the next word.
1.
Setup the address of the word to be programmed.
After steps 13thru 15 are completed for each word in the
matrix, the device has been properly programmed.
2.
Wait 500 nanoseconds or more (TAVPL).
• Never allow any input to rise more than 0.3 volts above
PROGRAM CYCLE TIMING TABLE
SYMBOL
PARAMETER
MIN
MAX
UNITS
TAVPL
Address to Program Setup Time
500
ns
TPLQL
Program Enable to Data Time
100
TAVQV
Address to Output Valid
500
J.ls
ns
TQLQH
Data Low Pulse Width
3.0
TQHPH
Data High to Program Disable Time
100
TAXAX
AO I nverted Time
500
J.ls
ns
TPHQV
Program Disable to Read Time
500
ns
TPHAV
Program Disable to Address Invert (AO)
0
ns
3-97
5.0
ms
vee.
Il
PROGRAMMING CYCLE
vee = 10.0V± 10%
+1DV
AD
GND
VALlD'ADDRESS'
AO
NEXT ADDRESS
,TPHAV
+1oV
AN
GNI)
VAUD,ADDRESS
AN
TAVPL
+1DV------l
+1ci
GND -
"DAT~ OUTP~TPIN I'«)T
TO BE PRO RAMMED
LOW VOLTAGE VERIFY CYCLE
vee = 3.5V .± 0.5V
+3.5
,,'
A PREVIOUS ADD
VALID ADDRESS
GND--------J ~----~~--------~==~
,NE/ ..
* These outputs are three state
4-9
TRC
EPE
CLSI
CLS2
SBS
PI
CRL
TBRS
TBR7
TBR6
TBRS
TBR4
TBR3
TBR2
TBR1
TRO
TRE
TBRL
TBRE
MR
NC
GNO
RRO
RBR8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
FE
OE
SFO
RRC
ORR
DR
RRI
CHARACTER FORMAT
START DATA PARITY STopll
BITS
BIT
BITS
BIT
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8'
8
8
8
8
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Specifications HO-6402A
ABSOLUTE MAXIMUM RATING§.
+12:av .
Supply Voltage:
Input or Output Voltage Applied
Storage Temperature Range
Operating Temperature Range
Industrial HD-6402A-9
Military HD-6402A-2
GND -O.3V to Vee +O.3V
-650 C to 1500 e
'.;.-
-400 C to +85QC
-550 C to + 1~50C .
ELECTRICAL CHARACTERISTICS
VCC = 10.0V±O.5V, TA = Industrial or Military
SYMBOL
D.C.
.' PARAMETER
MINIMUM
VIH
VIL
ilL
Logical "1" Input Voltage
Logical "0" Input Voltage
Input .Leakage
70% VCC
VOH
VOL
VCC -0.01
ICC
Logical "1" Output Voltage"
Logical "0" Output Voltage"
Outpu't Leakage,
Supply Ci!rrent
CIN
Co
Input Capacitance"
Output Capacitance"
10
TYPICAL
MAXIMUM
UNITS
20%VCC
.1.0
V
CONDITIONS ..'
V
-1.0
5.0
7.0
6.0
"
IOUT=O,
IOUT=O.
V
, V.'
,JJA
GND +0.01
1.• 0
500
-1.0
OV.~ VIN;~ V,CC
p.A,
OV'~ Vo ~VCC
VCC,=.10·I5V•
VIN =VCc,orC?ND
JJA
pF
pF
8.0
10.0
"
"
*Guarante/ld but not 100% tested.
'.;'
VCC= l,O.OV
TA ··25OC
1··A.c.
,
SYMBOL
PARAMETER
MIN
fclock
tpw
tpw
tSET
tHOLD
tpd
Clock Frequencv'
Pul~e Widths CRL. ORR; TBRL
Pulse Width MR
Input Data Setup Time
Input Oats Hold Time
Output Propagation Deleys
D.C.
75
350
40
30
TYP
CD
VCC,- lOV±O.6V
T A' io' Industrial
or'Military
MAX
MIN
6.0
D.C.
100
400
40
30
50
TYP
"
MAX
UNITS.
4.0
MHz.
. ns
70
ns
ns
ns.
ns
CONDITIONS
CL = 50pF
See Switching Time
Waveforms 1, 2. 3
NOTE 1: All devices guaranteed 'at wors.t cS,se limits. Rooni' temperature. 10V data provided for information-not guaranteed.
Switching Waveforms.
CLS1, CLS2, SBS,
FIGURE 1
Oata Input Cycle
PI,~E_PE_ _ _ _- .
, FI~I:IRI: 2 ' ' (
Control Register LOad Cycle
4·40
SFO ORRRD
FIGURE3 '
Status Flag OutJ;iuHlelaYI
or Data Output Delay•..
Specifications HD-6402
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Input or Output Voltage Applied
Storage Temperature Range
Operating Temperature Range
Industrial HD-6402-9
Military HD-6402-2
+8.0V
GND -0.3V to VCC +0.3V
-650 C to +150 0 C
-40 0 C to +85 0 C
-550 C to +125 0 C
ELECTRICAL CHARACTERISTICS
Vce = 5.0V ±-1 0%. TA = Industrial or Military
SYMBOL
D.C.
MINIMUM
PARAMETER
VIH
Logical "1" Input Voltage
VIL
Logical "0" Input Voltage
IlL
Input Leakage
-1.0
VOH
Logical "1" Output Voltage
2.4
VOL
Logical "0" Output Voltage
10
OU,tput Leakage
ICC
Supply Current
TYPICAL
MAXIMUM
UNITS
CONDITIONS
V
70% VCC
20% VCC
V
1.0
/lA
0.45
V
1.0
/lA
OV
100
/lA
VIN = GND or VCC;
VCC,= 5.5V. Output
Open
-1.0
1.0
OV ~ VIN ~ VCC
10H =-0.2mA
V
10L = 2.0mA
CIN
Input Capacitance*
7.0
8.0
pF
Co
Output Capacitance'
8.0
10.0
pF
5
Vo ~ Vcc
'Guaranteed but not 100% tested
VCC=5.OV
TA =25OC
TYP
VCC - 5.DV+10%
TA = Indust.or Mil.
MAX
MIN
3.0
D.C.
TYP
MAX
UNITS
2.0
MHz
CONDITIONS
Clock F~equency
D.C.
tpw
Pulse WidthsCRL, ORR, TBRl
150
150
ns
CL = 50pF
tpw
Pulse Width MR
350
400
os
See Switching Time
tSET
Input Data Setup Time
50
50
ns
Waveforms 1 , 2, 3
tHOlD
I nput Data Hold Time
60
60
ns
fclock
A.C.
MIN
PARAMETER
SYMBOL
ilOspike on Vec, which if it becomes a diode drop less than any input, may cause the device'to latch up. It isrecommended that a 0.1 IJF ceramic disk decoupling capacitor be placed between VCC and GND.at each device to:filter
out this noise.
I
PROPAGATION DELAYS
1.8
1.1
1.4
1.2
tR.'F
.\.0
'R, 'F 13OOpF, 0.8
';
;,
.
~,: :
:
o &0 100
200
!lOll
400
&00
o &0 100
200
300
CLlpF.
CLlpF,
FIGURE 1
FIGURE 2
400
. '~ )
The abol/e exampl~ will illustrate the calculat,ion of a more usettJl prop~gation delay. The system in this ellample uses
a 5 volt ~J.. pply w~th a tolerance of ±10%, an:ambiet\t ten1perature of as: high as l:!50C"mda calculated load capacita"ce of 1.50pF. T,his aPPIication requires the HD-6431-2. The table of A.C. spees,shows thattPD at 4.5V .and 1250 C
is '75nsec; Use-th~'graph'irt'Figure '1'to get the: degradation multiple for f50pF ;''fhe 'number~hOwn!is 0.B4: The'adjust·
ed propagation delay, to the 10% or 90% point,is therefore 75 x 0.B4 or 63nsec. To obtain the rise and fall times
check the A.C. specs for the rise and fall times at 4.5\1 and 1250 C to obtain a worst case rise time of 90nsec. US!!
Figure 2 to find it's degradation multiple to be 0.65. The adjusted rise time is, therefore,~O x 0.65 or 5Bnsec. To
obtain the standard 50% to'SO'i/;'propaQ'atlbn dehiy';'addtii'l! ~l:litJ'Stelh)roi>agatidndelaVto hart' of the adjusted rise time
to get a propagation delay of 92nsec.':'fh~' rise'ti01ewasu~~d'liere b~ca~~~Wis always the worst case.
4;';18'
&00
HARRIS
HD-6432
SEMICONDUCTOR
PRODUCTS DIVISION
A OIVISION Of MAARIS CORPORATION
CMOS BI-DIRECTIONAL
BUS DRIVER
MAY 1978
Features
Pinout
•
SINGLE POWER.SUPPLY
•
HIGH NOISE IMMUNITY
•
INOUSTRIAL AND MILITARY GRADES
TOP VIEW
•
DRIVE CAPACITV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300pF
•
SOURCE CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA
•
SINK CURRENT.
•
PROPAGATION DELAY . . . . . . . . . . . . . . . . . . . . . . . . 45nsec@ 5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA
3B
EBA
Description
EBA
GND
The HD-6432 is a self-aligned silicon gate CMOS bi-directional bus driver.
This circuit consists of 12 drivers organized as 6 bi-directional pairs.
Four enable lines select drive direction or Three-State mode.
Functional Diagram
Truth Table
CONTROL
DATA PORT
INPUTS
STATUS
(17)
EAB
EAB
4-19
A
B
L
X
H
L
H
H
L
a
a
I
x
H
L
X
H
I
H
L
L
X
a
a
L
x
L
X
ISOLATED
I
I
X
H
X
H
ISOLATED
L
X
X
H
ISOLATED
X
H
L
X
ISOLATED
H
L
H
L
NOT
ALLOWED
'":-'--
I
EBA EBA
= Input, a
",Output, X" Don't Care
I
Specifications HD4i432A
ABSOLUTE MAXIMUM RATINGS
. Supply Voltage
+12.0V
GNE> -0.3V to vee +0.3V
-65 0 e to +150 0 e
Input or Output Voltage Applied
Storage Temperature Range
Operating Temperature Range
Industrial HD-6432A-9
Military HD-6432A-2
Operating Voltage Range
-400 e to +85 0 e
-55 0 e to +125 0 e
+4 to +llV
ELECTRICAL CHARACTERISTICS
Vee = 10V
±10%; TA = Industrial or Military
MAX
SYMBOL
PARAMETER
MIN
VIH
Logical "1" Input Voltage
70% Vee
VIL
Logical "0" Input Voltage
IlL
Input Leakage
Logical "1" Output Voltage
VOL
Logical "0" Output Voltage
D.C.
10
Output Leakage
ICC
Supply Current
TEST CONDITIONS
V
20% Vec
V
10
!J.A
-10
VOH
UNITS
-10
OV~VIN~VCe
V
10H = -8.0mA,
0.4
V
10L = 12mA
10
!J.A
100
!J.A
Vee -0.4
OV~Vo~Vec,
EAB = EBA = Low
VIN = Vec or GNO,
VCC = 11V
CIN
Input Capacitance'
5
pF
CliO
VIN = OV; T A = 25 0 C;
f= 1MHz
(except I/O)
20
I/O Capacitance'
pF
VIN = OV; TA = 25 0 C;
f = 1MHz
I
, Guaranteed and sampled, but not 100% tested.
eL
=300pF
; ~'.
PARAMETER
MIN
VIH
Logical "1" Input Voltage
70% Vcc
VU.
Logical "0" Input Voltage
IlL
"
'D.C."
I' '
Input Leakage
MAX
LQllical"1',! Output Voltage
.......OL
LQllical "0'" Output Voltage
UNITS
TEST CONDITIONS
V
20%VCC
10
-;10
VOH
I;
,
/
VCC-o·4
'0.4
V
jJ.A
V
V
,OV~VIN~VCC
10H= -B.OmA,
E1 =E2=Low
lei'.:. D 12mA
E,=E2=!.oW'
.... "
10
' 'Output Leakage
-10
10
p.A
OV~VO~Vc:C,
E1 =E2 = High
ICC
Supply Current
100
p.A
VIN = VCC or GND,
VCC=11V
VIN = OV; TA = 250 C;
f = 1MHz
,
CIN
Input Capaeital)ce*
5
pF
Co
Output Capacitance *
15
pF
:
I
~
,
Guaranteed and sam~led, but not 100% tested.
"
(j)
VCC·,0.0V
250 C
SYMBOL
,A.C.
PARAMETER
VIN = OV; TA - 250 C;
f = 1MHz
MIN
Vee "'O.OV±10%
1'A .. Indust. lir Mil.
MAX
MIN
MAX
UNITS
ns
tpo
Propagation Delay
30
40
tEN
Enable time
60
70
ns
tDiS
'tR
,
Disable Tirne
Output Fllse Time
70
ns
75
15
ns
ns
tF
_.,¥,
Output Fall Tim,e,
'\
60
65
65
(j):
'I
,
AU. devicei guarantaed a~ worst IlBse limits •. Floom temperature,
10V data provided for inform~tion-not guaranteed.
"
',NOTE
,
, 4-32
Specifications HD-6495
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Input or Output Voltage Applied
Storage Temperature Range
Operating Temperature Range
Industrial HD-6495-9
Military HD-6495-2
Operating Voltage Range
+8.0V
GND -0.3V to Vee +0.3V
-65 0 e to +150o e
-40 o e to +850e
-55 0 e to +1250e
+4 to +7V
ELECTRICAL CHARACTERISTICS
Vee = 5.0V
±10%; TA = Industrial or Military
SYMBOL
PARAMETER
MIN
VIH
Logical "1" Input Voltage
70% VCC
VIL
Logical "0" Input Voltage
IlL
Input Leakage
VOH
MAX
TEST CONDITIONS
V
20% Vee
V
1.0
J.lA
-1.0
Logical "1" Output Voltage
UNITS
V
VCC -0.4
OV~VIN~VCC
10H = -4.0mA,
El = E2 = Low
VOL
D.C.
Logical "0" Output Voltage
0.4
V
10L = 6.0mA
El=E2=Low
10
Output Leakage
-1.0
1.0
J.lA
OV~VO~VCC,
El = E2 = High
ICC
Supply Current
10
J.lA
VIN = Vec or GNO,
CIN
Input Capacitance*
5
pF
VIN = OV; TA = 250 C;
Co
Output Capacitance*
15
pF
VCC = 5.5V
f = lMHz
VIN = OV; TA = 25 0 C;
f = lMHz
I
• Guaranteed and sampled, but not 100% tested.
eL = 300pF
Vee =5.0V
66Ol1
.D~~
y
_________
10%
. Et- E2-LOW
.
#
"" r-'·
y
All inputs have tR, tF ~ 2Ons.
lKG
r.
T300pF
OUTPUT .TEST CIRCUIT
.FOR PROPA~ATION DE~AYS
OUTPUT TEST CIRCUIT
FOR THREE..:sTATEDELAV;S
DECOUPLING CAPACITORS
The i:ransient cu~rent required to charge the load capacitance is give,n by IT =C dv. Assurning.that all outpu~ may
.
~
change state at the same time and that dv is constant; IT = (ECl) (VCC)( 80%-) ego [tR= 85ns,Vcc '" Ii.ov, each
'.
'. .
dt
:.
.'
tR or t F .
,
Cl =300pF, IT.= (6)(300X 10- 12\ 5.0 x 0.8 = 84.7mA.] This current spike may cause a large negative voltage
. '
185 x 10-9
.
spike on Vee, which ifit becomes a diode drop less than any input, may cause the device to latch up. It is fI;com~
mended that a 0.1 /lFceramic disk decoupling capacitor be placed between VCC and GND at each device to'filter
out this noise.
t
.
. PROPAGATION OELAYS
1.8
1.2'1
1.1
1.1'
1.4
1.2
"IotF
1.0
tR. tF (3GOpFI 0..
1.08
..-.!!!.....- 1.00
tpI)
1300pFI 0.82
0.1
200
,300 400
CLlpFI
FIGURE I
100
o 10 100
200
300 400
CLIpFI
FIGURE 2
The above example will illustrate the calculation of;! more useful propagation delay. The system in this exampll; uses
a 5 volt supply with a tolerance of ±10%;' an ambient temperature otas high as 1250C, and a calculated load capacitance of 150pF. This application requires the HD-6495-2. The table of A.C. specs shows that tPD at4~5V and 1-250C
is 45nsec. Use the graph in Figure 1 to get the degradation multiple for 150pF. The number shown is 0.84. The adjusted propagation delay, to the 10% or 90% point, is therefore 45 x 0.84 or 38nsec. To obtain the rise and fall times
check the A.C. specs for the rise and fall times at 4.5V and 1250C to obtain a worst case rise time of 95nsec. Use
Figure 2 to. find·it's degradation mlJltipleto~,,0.65.~ The. adjustedris,lItime is, therefore, 95 x 0.65 or 62nsec. To
obtain the standard 50% to 50% propagation delay,. add· the adjusted pr~pagation delay to half ofthe adjusted rise time
to get a propagation delay of 69nsec. The rise time was used here because it is always the worst case.
4-34
100
HARRIS
MONOLITHIC DIODE
SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION Of HARRIS CORPORATION
MATRICES
JUNE 1978
Features
Description
•
FIELD PROGRAMMABLE
•
CMOS COMPATIBLE
•
ZERO POWER DISSIPATION
•
FAST SWITCHING
•
FIVE POPULAR ORGANIZATIONS
De~igned with the CMOS circuit engineer in mind, these
versatile diode matrices allow the application of logically
powerful programmable solutions to low power CMOS
system applications.
These devices incorporate an advanced dielectric isolation
process to eliminate the need for power supply pins and
allow parasitic free operation.
Programming is accomplished by cleanly vaporizing a fusible link by application of a brief high voltage pulse to
a selected array element. This operation open circuits
a row to column orring diode eliminating their former
interaction.
Monolithic Structure
ROW
CONNECTION --~tz:;>4!lIi
SILICON
DIOXIDE
DIELECTRIC
LAYER
"P" TYPE
SILICON
Fusible link System
METALIZED
INTERCONNECT
LINE
DISCONNECTED
DIODE
INTACT
LINK
FUSED
LINK
CONNECTED
DIODE
4-35
I
MoilolithicDiode Matrices
HM-0198
........
N.C.
HM-0168 6x8
DIODE MATRICES
HM-0186 8x6
DIOPE MATRICES
18
K 31-.......,rll-r.,rI
HM-0410 4 x 10 DIODE MATRICES
K
4f-.....+lHfo++lH
HM-0104 10 x 4 DIODE MATRICES
HM-0198 9x 8
PIODE MATRICES
K 7 f-.............L..fo&.l...
A8
10 A
A9
NOTE: Anodes are bold lines.
HM-0104
HM-0168
,-----114 A
9A
8A
I
HM-Q410
HM-0186
K1
A 11--
'-"
14 A
=--"
A 2
13 A
!< 2
A3
12 A
K3
"- 12
K
A 4
11 A
K 4
"- 11
K.
A 5
10 A'
~6
"-
A6
9'A.
'.
y
i-'--
K 7
13 A
10 K
' - - 9A
B A
CUSTOM PATTERNS
When ordering a matrix with a custom pattern: Send a paper tape, or cOPy,a matrix pattern and circle out those diodes
to be removed from the matrix. . Anotlll1r. method to s;learly iq!lntify l! pa1;tE!rnJs to call out respective anode and
cathode for each diode to be removed, by.packa!le pin n u m b e r . '
... '
4-36
Specifications Diode Matrices
ABSOLUTE MAXIMUM RATINGS
Forward Current
100mA
Surge Current (1001015 Max.)
200mA
Total Ckt. Dissipation (Still Air)
450mW
Storage Temperature (Ambient)
-650 C to +150o C
Maximum Ratings are limiting value. above which permanent damage may occur.
ELECTR ICAl CHARACTER ISTICS
I TA
SYMBOL·
VF
BVR
PARAMETER
HM-OXXX-6
HM-OXXX-2
HM-OXXX-8
ODC to +7&OC
-55OC to +1250 C
MIN
MAX
Forward Voltage
MIN
MAX
UNITS
1.5
.9
V
V
IF = 20mA
IF= lmA
V
IBV = 100lolA
50
ns
IF = 10m~ tolR = 10mA
Recovery.to 1mA .
8
pF
VR=5V; f=lMHz (1)
1.5
0.9
Reverse Breakdown Volt age
20
30
250 C
CONDITIONS
250C
.'
trr
Reverse Recovery Time
Cc
CrosspoInt Capacitance
100
-L-
(1) CCOCVBIAS
I
TYPICAL PERFORMANCE CURVES
VOLTAGEVf
~
10
WORSTfci
OIODE0250C
&
I
1//
3
V
" WORST
DIODE. --66OC
I
z
//
CURRENT-mA
1
l~
o.&
IJ
0.3
I I
o.2
I J
o. 1
2!iPC.L, /-'&&OC
0.2
OA
0.8
o.s
VOLTS
4-37
1.0
1.2
Programming
Use a simple supply capable of driving'a 27 ohm resistor (carbon) when Sl depressed with a clean transition from 0 to
24-30 volts in less than 100J.ls for min time of 10ms, The diode to be disconnected is selected by setting the row and
column switches S2 and S3 respectively as required, When switch Sl is depressed programming current is provided
to column contacts on the matrix, This current opens the fusible link in series with the selected diode. The peak
fusing current required to open a fusible link is approximately 750 milliamperes. As the temperature of the fuse is
raised, the aluminum begins to melt. This melting continues until the fuse link separates. The cohesive forces of the
melting aluminum retracts the remaining portions of the metal, thereby preventing formation of loose aluminum
residues. The melting temperature of aluminum at approximately 650 0 C will not affect the passivating layer of silicon
dioxide whose melting temperature is about 13500C. Test verification is obtained by an indicator lamp or LED placed
in series with the column and row switches through the verify contacts of Sl to give electrical indication of the condition of each diode in the matrix before and after fusing.
Caution: Programming is limited to one fuse at a time.
SIMPLE PROGRAMMER
PROGRAMMER TEST CONFIGURATION
+24 to 30 Vohs _ - - - - - - - - - - . . _ . . ,
1 Amp. Min.
27
I
Acceptable
8, SPOT MOMENTARY
S2 10 POS. 1 POi.~
S3 10 POS, 1 POL~
PROG.
INDICATOR LAMP, LEO
25
50
75
~lOms
100
MICROSECONDS
NOTE: The 27 ohm resistor is only used for oscilloscope
measurements of 'the Power Supply Characteristics
becaues it r~presents a typical unprogrammed
fuse/diode.
Relj~Qjljty
& QualjtyContents
PAGE
I ntroduction, Quality Control,Reliability
5-3,5-4
Section 1. CMOS Reliability/Quality Enhancement
5,..5
Section 2. Fusing Mechanism of Nichrome Thin Films
5-11
• Fusing Mechanism of Nichrome Thin Films
5-11
• Microscopic Observations of Fuses
5-23
Section 3. Reliability Screening Programs
5-28
• Reliability Screening Programs
5-28
Program
5'::'28
• Dash 8 Program
5-29
•
HI~Rel
5-39 .
Section 4. Burn-In Circuits
• Burn-In Circuit Index
5-39
• Burn-In Circuits
5-41
5-2
Harris Reliability & Quality
Int,oduction
The Product Assurance "Department at Harris Semicond\Jctor Products Division is responsible for assuring that the quality and reliability of memory products shipped to customers
meets their requirements. During all phases of product fabrication, there are many independent visual and electrical checks performed by Product Assurance personnel.
Prior to shipment, a final inspection is performed at Quality Ass~rance Plant Clearance to
insure that all requirements of the purch~se order and customer specifications are met.
The following military. documents provide the foundation for Harris Product Assurance
Program.
MIL-M-38510D
.. M I C,-O-9858A
MIL-STO-8838
I'~.\SA Publication 200-3
M I L-C-45662A
MI L-I-:4508A
"General Specification of Microcircuits"
"Quality Program Requirements"
"Test Methods and Procedures for Microelectronics"
"Inspection System Provisions"
"Calibration System Requirements"
"Inspection System Requirements"
The Harris Semiconductor Reliability and Quality Manual, which is available upon request,
describes the total function and policies of the organization to assure product reliability and
quality. All customers are encouraged to visit the Harris Semiconductor facilities and survey
the deployment of the Product Assurance function.
QUlllity Cont,ol
All critical processing steps for memory products are subject to rigid process control monitoring.
.
.
For example, to insLlrE,! process stability of CMOS fabrication,frequent qualification of diffusion furnaces, metallization and passivation equipment by C-V plotting techniques is performed. The C-V' plot method provides a very'sensltive monitor of the amount of ionic
contamination present in the processing equipment; and assures clean process with builtin reliability. Process controls of this kind are one reason Harris products have an excellent
reliability record.
Another example, in the case of bipolar memory circuits, 'is the nichrome fusible link process. Tl1is process is rigorously controlled by frequent measurements of parameters such as
resistivity and. dimensions. Consistent and controlled execution of this process hal! led to'
very reliable PROMs of high programmability.
.
The above are only a few of the many process controls instituted to ensure high quality and
reliable products. Some other examples are listed below:
"
•
•
•
•
•
•
In-line SEM inspection
Continuous environmental monitoring for particle count, temperature and humidity
Oxide and metallization thickness measurements
Doping concentration and profiles
Pre and post etch inspections
Prescribed interval calibration and preventative maintenance of processing equipment
Total documation of specifications and change control procedures·
The Product Assurance department also maintains a well equipped Analytical Services Department. This area is equipped with a complete electron microscopy laboratory, including
Scanning Electron microscopes with energy dispersive x-ray analysis capability, electron microprobe, a Scanning Auger. microscope with ESCAattachment, and all sample preparation
equipment. The Analytical Services Department also has a complete physical chemistry
laboratory utilized for analyzing the products and process materials for memory circuits.
Equipment in this section includes atomic absorbtion flame emission spectrometry, arc
emission spectrography, gas chromatography, a research grade talystep, an ultraviolet spec-
.5..:.3.
E
trophotometer and arl if)t"aredspe~troli!!:lotomelet. This $ection~al$o contains a complete
" '. ' ,
' .""
wet chemical analysis rabo"ratory."
Further, to ensure high quality metal deposition, critical die areas are monitored·viajo:""
process SEM.
Reliability
ThE! reliability approach 'Jf Hlirris \SemlcQnductoris, b~sedon designing in, reliability rat~~r
than testing forreliability'olilY. The latter' is appliedto'eheek andconfirm thatsolliid'design with quality and reliability ground rules are observed and correctly executed jn a new
"product design.
, . , . " ' ,
Rel,iability'engineering becomesinitolved as early as ,concept review'af·a new 'product arid
continues to remain involved through design and layout reviews. At these criti~1 development points ofa new de~;gn, basic relii'!,bi!ity layout guidelines are invokedtojn~ure an allaround reliable design., This concept is refleCted by the Harris relia,bility proe~dures which
encompass mandatory first run J)roducievalustion. This is done at notonty the circuit
level, but also at the process and package level. Reliability engineering approval is required
before new product designs are relflased to m1l:nuta9,turing.",
Both maximum rated, and accelerated,StresScQhditlons are performed.: AcCeleration is im ..
portant to determine how and at.what.stress leyel.a new design would'faH. From. this information, necessary design changes can' be,inlPtemented to insute a wIder and. safer margin
between the max'inium ratedstresscondi1:io~ 'ahd!the aEivice'sstreS$ limit~~on;" "", ',"
The notably lo~failure rates' f,or theB ipolar ~~d. CMOS Mell)ory prOdyctsare Ii; direct. nesult
of the application
this reliability con~ePt.,Fp,r:;th~iP-RciM cireu.its, the,hi~\1 ~a",d~~s
for reliability and quality have yielded the industry's highest programmability yields. Our
demonstrated expertise with NiCr fusing has resulted inobserved failure rate'swhic:n\arilessW;::;'
than equivalently c()!1JJ?lex TTl"L.~1 circu,its.,C;:onservatively deratJ"g to+2,5 0 C gives,!! ~a,il
ure rate of .020%/1kHi::s, for programmed 76XX Bipolar PROMs and a value of ,0'3%1
lkHrs. for the 65XX CMOS Memory prOd,4!=ts,
" .
-fha el«ceLien't. r~liabi'liiY~~erforma~ce.~;f~iher exemplified by QUr~l!stomer!!. AnalV$ of
p,arts' returneqto/:larris Indjcate!!.~, foilpwing res'uiis." F.or the. CMOS M~rt:!or,y'products,
the' retums.,constituteO.2% of :the,totalvO.lijme ipp~w.h il!!! for thel3ipola;: Memory. prod!.Jcts, this}igureis 1,5%'.'Thi$ nlim~~r,i'19Iudes all. progr,ammabjlity rejects for. tti!! P~QMs.
The accompanying charts illustrate the distribution of categories for why devioes .areretu r.n!!!d. Note that. 60-;-70%, 91 th!!!se r~lu rned Ilre devi.oes that, werenpt. defecti.ve. as ~t'lipped .
.These4~its' filUed due, to ,electrQ~a:tlc:aatnage(ESQ),eleetrical .ov:arstr~~s (!=OS), or
were gqod devicesvilh ichWereii)G.qrre<:tlyiCIentified as board or systeiTCI~velfail~res.
The latter category is defined' as 'invalid returns' a!1d.represents 30-40% ofthe i9(al. J)um.~E!r
of returned units.
. . .
.
' .
.
of
sh
,
..;"{
','
60
I
40
CUST.OMER INDUCED .I'ROBLEMS;73.5%
OF RETURNED UNITS
....'
,.
....'
1;
iNVALID RETURNS. '. : •••• : •• 44%
2.
ELECTROS.TATIC DAMAGE •• '. ". 28'J(,
, 3.
EOS. V~SI'I"ES ••. : •.• ',:' , 1,6%
30
I'EReENTAGE
OF RETURNS
OBSERVED FAILURE MODES 26,5%:"
4.
,ASSEI\IIBLY,. """,,"',,!.,. ':',,,' • ,,''', ,2;6%
6.I'RQCE$ljHll(i FL"~." •• ',' ,.•• 21%
.,,!.
TESTES9AI'ES,' ':' :;~"U';',' " ..•.3%
RETURNED
SHlPPEtJ.
UNiTS 'EQUAL ::i:tO.2% OF tOTAL !>ARTS
,", '. :
1"',
,.:;~-.,.;;
:,
SUMMARY BASED .ON :'RESOL TS OBTAINED DIJIt ..
,INO THE INTERVAL,Srn-" 3/'7.8
' :< ,,!
CMOS FAILURE CATEGORIES
CUSTOMER INDUCED PROBLEMS:
61%
OF RETURNED UNITS
1.
INVALID RETURNS •••• 27%
CUSTOMER PROGRAMMING
2.
PROBLEMS . . . . . . . . • . 26%
3.
BLOWN BOND WIRES (REVERSE INSERTION) . . .. 5%
4.
EOS, VCC SPIKES . . • . • . 3%
30
PERCENTAGE
OF RETURNS
20
OBSERVED
5.
6.
7.
10
FAILURE MODES:
PROCESSING FLAWS .•. 28%
ASSEMBLY. . • . . • . . .• 8%
TEST ESCAPES ••..• "
3%
RETURNED UNITS EQUAL ~ 1.5% OF
TOTAL PARTS SHIPPED
SUMMARY BASED ON RESULTS OBTAINED DURING THE INTERVAL 91'76 - 3/'78
BIPOLAR FAILURE CATEGORIES
Section 1. CMOS Reliability/Quality Enhancement
To ensure a totally reliable product and system, the design engineer needs to understand
the capabilities and limitations of the CMOS product. In addition, a clear understanding
of the techniques employed to improve reliability is essential for High Reliability system
goals, The following describes the necessary tools to enhance CMOS reliability.
DESIGNING OUT FAILURE MODES
Static Charge
Since the introduction of MaS, manufacturers have searched for effective and safe ways
of handling this sensitive device. High input impedance of CMOS, coupled with gate-oxide
breakdown characteristics, result in susceptibility to electrostatic charge damage.
Figure 1 shows a cross-section of silicon gate MaS structure. Note the very thin oxide layer
( ~ 1000A)* present under the gate material. Actual breakdown voltage for this insulating
layer ranges from 70 to 1OOV.
Handling equipment and personnel, by simply moving, can generate in excess of 10kV of
static potential in a low humidity environment. Thus, static voltages, in magnitudes sufficient to damage delicate MaS input gate structures, are generated in most handling environments.
A failure occurs when a voltage of sufficient magnitude is applied across the gate oxide
causing it to breakdown and destruct. Molten material then flows into the void creating a
short from the gate to the underlying silicon. Such shorts occur either at a discontinuity
in doping concentration, or at a defect site in the thin oxide. If no problems appear in. the
oxide, breakdown would most likely occur at gate/source, or gate/drain intersection coincidence due to the doping concentration gradient.
Noncatastrophic degradation may result due to overstressing a CMOS input. Sometimes
an input may be damaged, but not shorted. Most of these failures relate to damage of the
protection network, not the gate, and show up as increased input leakage.
*1'&' (Angstrom = 1Q-8cm i
5-5
, SOURCE METAL
.' ~;
DRAIN METAL
:
,:"
FIGURE 1 .,..' Silicon-gate ~FEJ struCture cross-section.' shows the
~qvily doped source ari~dr.ainrel!ion." Thlly:, lire sep~rated by a narrow
gap over which lias a thin-gate oxide and gate material.
Voltage Limiting Input Protection
During the evolution of monolithic MOS, manufacturers developed various protection
mechanisms that are an integral part of the circuit. However, several of these earlier techniques have been replaced by improved methods now in use. The object of most of these
schemes is to prevent damage to input-gate structures by limiting applied voltages.
Recent CMOS designs en:,ploy a dual:"diodJcon~ePt
Figure 2 illustrates such a protection circuit.
i~ their input p rotiK:ti on networks.
,One char,actedstic of jlmcti.o'n~isolatedCMOS protection Circuits, is the ~ .2qbn current
limiting resistor. Cross sectional area of the, metallization leading to the resistor, and the
area of iheresistor are, therefore, designed 'to absorb discharge energy without sustaining
permanent damage. This dual-diode protection has proved very effective and is tlie most
commonly used method in production today.
HARRIS INPUT GATE PROTECTION
'To protect input device gates against destructive overstress by static electricity aceumulating
, during handling and insertion of CMOS products, Harris provides a protection Circuit on all
inputs. The generaloonfigurationof this proteotioncircuitis shown inF·igure 2.
Both diodes to,the VOD and VSS lines have breakdown voltages averaging between 35 and
40 volts~Excessivestatic charge aocumulatedon the input pin is thus effectively discharged
through these diodes which limit the voltage applied from gate to drain and source. The
200 ohm resistor provides current limiting during discharge. OepencFng on the polarity of
the input static charge and on which of the supplypiris is grounded, the protective diodes
milyeither conductinth~ forward direction or breakdown in the reyerSe direction.
In order to test this concept, step stress tests have been performed at Harris using an approximate equivalent circuitto simulate the stati~ charge encountered in handling operations.
The equivalent circuit consists of a 100pF capacitor in series with a t5K ohm resistor
,and ,is considered the rough equivalent of a human body. Step stresSing takes the form of
charging the capacitor to a given voitageand then discharging it into an input pin of the
CMQS device under testaccording to the sequence given in MI, I..-STD-38510.
'
Stress Voltage
Cumulative Failures
500
700
1000
1500
1700
1800
o
o
o
1
3
4
5-6
These results indicate that the input protection used for Harris CMOS products provides
adequate protection against static electricity based on the limits specified in MI L-STD38510.
There are two trade-offs to consider when fabricating an input protection scheme. Effectiveness of the overvoltage protection, and performance of the overall circuit. It is obvious
that increasing series resistance and capacitance at an input limits current. This, in turn,
increases the input protection's ability to absorb the shock of a static discharge. However,
such an approach to protection can have a significant effect on circuit speed and input
leakage. The input protection selected must provide a useful performance level and adequate static-charge protection.
Commonly used MOS-input protection circuits all have basic characteristics that limit
their effectiveness. The zener diodes, or forward-biased pn-junctions, employed have
finite turn-on times too long to be effective for fast rise-time conditions. A static discharge of 1.5kV into a MOS input may bring the gate past its breakdown level before the
protection diodes or zener becomes conductive.
Actual turn-on times of zeners and pn-diodes are difficult to determine. It is estimated
that they are a few nanoseconds and a few tens of picoseconds, respectively. A low-impedance static source can easily produce rise times equal to or faster than these turn-on
times. Obviously the input time constant fequired to delay buildup of voltage at the gate
must be much higher for zener, or other schemes having longer turn-on times.
~200n
PO LYSI LICON
RESISTOR
Voo
NOTE: FOR CMOS, Voo IS MOST
POSITIVE; VSS IS MOST
NEGATIVE.
INPUTo-~~~
200
I
FIGURE 2 - Junction isolated dual-diode protection networks are most
commonly used in today's CMOS circuits.
Consider an example. Figure 3 shows a test circuit that simulates the discharge of a 1.5kV
static charge into a CMOS input. Body capacitance and resistance of the average worker
is represented by a 100pF capacitor through 1.5k!l, Switch A is initially closed, charging
100pF to 1.5kV with switch B open. Switch A is opened, then B is closed, starting the
discharge. With the 1.5Kn x 5pF time constant to limit the charge rate at the DUT input,
it would take approximately 350psec to charge to 70V above VDD. Diode turn-on time
is much shorter than 350psec, hence the gate node would be clamped before any damage
could be sustained.
There is no completely foolproof system of chip-input protection presently in production.
If static discharge is of high enough magnitude, or sufficiently short rise-time, some damage
or degradation may occur. It is evident, therefore, that proper handling procedures should
be adopted.
5-7
.,
_/~
1.5kV~A
.
.
,I
C.L:__ _
I
I
I
I
I
. . . """-+---,
o-o:.~
100pF
1
4pF
I
I
Vss
: .
Vss
I D.EVICE UNDER TE.ST
TEST S,ETUP
FIGURE 3 - Input protection network test setup illustrates how diode.
clamping prevents excessive voltages from damaging'the CMOS device.
HANDLING RULES
Elimination or reduction of static charge can be accomplished as follows:
• Us'~ conductive work stations. Metallic Or conductive plastic* tops on work benches
conl1ected togroiJnd help el.iminate static build-up.
'
• Ground all handling equipment.
• Gound all handling personnel with a conductive bracelet through 1 Mn
'
The lMn resistor will prevent injury.
to ground.
• Smocks, clothing, ilnd especially ,shoes of (:ertaininsulating materials (notably nylon)
should not be worn in areas where devices are handled. These materials, highly dielectric in nature, win hold o~ aid i':1the, g.eneration of iI static charge.
• Control relative humidity to as .higha levet 10 megohms and it will not break down, electrically or structurally to
voltages in excess of 100 volts.
5-12
e.
The white spots, dark spots and filaments are described by the fluid dynamics of a
disintegrating liquid sheet 12 • Briefly, that model describes how minute discontinuities in a liquid sheet, perterbate into larger holes and finally into droplets and
filaments because of surface tension effects. The structure looks similar to a "frozen
splash".
MASS TRANSPORT MODELS
In the previous section, it has been demonstrated that programmed nichrome fuses melt
and that mass transport takes place. But what is the mechanism, the driving force for mass
transport? Table 1 lists the possibilities.
Table 1
(1) Electromigration (Huntington & Grone 15): Mass flux occurs under the influence
of high current flow because electron collisions with atoms of the conducting
medium provide a net motion vector in the direction of electron flow.
(2) Thermal gradient (Soret 16): In the presence of a thermal differential, material
will diffuse from the high temperature to the cold temperature region.
(3) Concentration gradient (Fick 17): In an imbalanced distribution of concimtration,
mass will diffuse from regions of higher concentration to lower concentration.
(4) Field enhanced ionic mobility (Eyring and Jost 18): Molten metals will ionize,
lose electrons and become cations. In the presence of an electric field, they will
be driven towards the cathode.
Considering each possible mechanism in turn:
(1) Electromigration -
On the surface, this seemsa most logical explanation for programming. It is known that the current densities in a fuse neck at programming
are very high ( '" 5 x 107 amps/cm 2 ) and it could be postulated that.this electron
tlux sweeps the nickel arid chromium from the gap. But empirical data and theoretical considerations show this not to be the case.
a.
TEM of the fuse gap indicates the molten nichrome has moved ina direction
opposite to electron flow.
b. Theoretical calculations of the kinetic energy of conduction electrons in nichrome demonstrate .that because the mean free path is short and the lattice
binding energy is high (transition metals typically have high melting points),
the electrons have insufficient energy to impart the mobility to the nickel and
chromium atoms necessary for electromigration in the direction of electron
flow.
However, general treatments of electromigration theory 15. 24 identify two forces
acting on atoms of the conducting medium. One is the aforementioned electron
momentum ("electron wind") in the direction of electron flow. The other is the
electrostatic force from the applied electric field that causes ions of the conducting
material to move opposite to the direction of electron flow. See mechanism (4).
Obviously, the joule heating that leads to melting the fuse is coming from electron
interaction with the nichrome film. There is no incongruity with the fact that this
.is not leading to electromigration such as observed in aluminum. Because the mean
free path is short, the energy exchanged per collision is small. But because electron
scattering is a dominant factor in· resistive materials, the frequency of collisions is
high. Thus, thermal energy (lattice vibration) is added to the metal atoms. The
electron collisions increase the amplitude of the atomic vibration and increase the
temperature. This is why nichrome is an efficient material for converting electrical
energy into thermal energy (toaster effect).
Footnote: Arguments have also been advanced that oxidation is the mechanism of fusing 19. If this were so, the probe data,
which discerns elemental presence, would not show nickel and chromium depletion in the gap region, i. e., mass
transport, per se, would not have occured. Because the TEM data clearly indicates mass transport, attention is
focused here on identifying the driving force for that mass transport.
5-13
I
(2) Thermal Gradient -
Froman analysis of heat flow in a fuse, it has been shown
(see the Transient Heat Flow Analysis section), Figure 6, that the temperature
profile across a fuse neck is flat. The gradient occurs at the neck-to-fuse body
interface. But the programmed gap occurs in a region where there is no temperature
gradient. Further, this model would predict a symmetric distribution of mass,
post-programming which is not observed. Temperature gradient does not cause
the mass transport.
(3) Concentration Gradient - It has been shown in unprogrammed fuses that no concentration gradient exists. Laterally in the fuse film this is borne out by the TEM/
probe analysis. That is, no nickel or chromium concentration variations are observed across an unprogrammed fuse. Vertically (distribution of nickel, chromium
through a cross section of the resistor) it has been shown 20 , from sputter etching
Auger analysis that the nickel and chromium are distributed uniformly through
the film (no concentration layering effects).
Because there is no concentration gradient initially, this is ruled out as a starting
mechanism for fusing.
(4) Field Enhanced Ionic Mobility - Eyring and Jost 18 have observed that liquids have
a fixed ratio between their energy as a liquid and the energy required for vaporization, see Figure 7. Stated simply, the principal is, the more cohesive the liquid,
the more energy is required to transform it to the gaseous phase, and the ratio is
a constant. This rule held for all types of liquids (gases, solvents, organics, etc.)
except metals. But by accounting for ionization of molten metals and the subsequent reduction in atomic radii, see Table II, they found that metals obeyed the
liquid:gas constant energy ratio. In other words, molten metals are ionic.
It follows then that these positive ions (they have given up outer shell electrons)
will move in the presence of an electric field (from the programming pulse) toward
the negative terminal, opposite to the direction of electron flow. This is consistent
with the TEM observations and with some investigations of electromigration. For
example, Wever 25 observed in copper above 9500 C, that mass flux was toward
the cathode.
In summary, nichrome fuses program as follows: A programming pulse of sufficient
power is applied across the fuse. Power dissipation in the fuse neck heats this
region into the molten $tate and the nickel and chromium atoms become ionized.
They move toward the negative side of the fuse and the liquid film begins to disintegrate. The film becomes electrically discontinuous and rapidly returns to the
solid state, the final structure resembling a frozen splash described by fluid dynamics. The fuse gap consists of insulative oxides of silicon and chrome, with
resistance > 10 megohms.
TRANSIENT HEAT FLOW ANALYSIS
The previous discussions dealt with the fusing event postfacto, describing the microscopic
material structure created by programming. The dynamics of the fusing event can also
be characterized. By modeling the fuse structure and its environment in terms of classical
heat flow, the connection between electrical and material behavior of fuses can be established.
A computer thermal analysis program called ''THEROS''21 was used tocalculate the dynamic temperature effects in a PROM-fuse structure as a function of applied power density.
This computer program can thermally model a multicomponent structure and calculate
the temperature as a function of time for given power dissipation conditions. The program
takes into account temperature dependent thermal properties of the various materials and
5-14
models a 2-dimensional multimaterial, multigeometrical structure into a RC circuit network
that can be analyzed by sophisticated transient circuit analysis programs. This approach is
convenient because the differential equations that describe heat flow problems have the
same form as differential equations for RC circuit networks. For example, specific heat
is analogous to capacitance, thermal conductivity is analogous to the inverse of resistance,
temperature is analogous to voltage and heat flow is analogous to current. By way of the
"THEROS" heat flow to electrical analog program, the sophistication available with present
circuit analysis programs can be utilized to solve complex heat flow problems without
consuming hours of computer time and without the errors prevalent in more simplified
calculations. For the heat flow model to be truly representative of the actual device, the
immediate environment of the fuse must be completely accounted for. For example,
the passivating oxide layer on top of the fuse will affect the heat flow and the subsequent
structure of the programmed fuse. Programming a fuse without the passivating oxide 22
will result in a different structure than occurs in an actual PROM circuit.
The term "power density" is defined as the amount of power that is dissipated in the fuse
neck region divided by the area of the fuse neck (watts/miI 2), see Figure 8. The concept
of defining power density as power per unit surface area is applicable to thin film heat
flow problems where the heat is dissipated through a surface. (The concept is analogous to
defining current density as current per cross sectional area). Figure 9 shows a plot of the
computer results giving the temperature in the center of the nichrome fuse that would
be achieved if a constant power were applied for a time t. The curves show that the fuse
can easily reach the melt temperature of nichrome 23 within microseconds for power densities > 2.5 watts/mil 2.
Figure 10 is a plot of the intercept of the time to reach the melt temperature (14500 C) vs.
the power density. This theoretical prediction of the power density versus time to reach the
melt temperatures compares well with experimental data on time to fuse. The data in
Figure 10 was taken from test vehicle fuses, processed identically to circuit fuses, but
free of interfacing circuitry. This allowed precise characterization of fuse-pulse interactions. The data matches for long fusing time but deviates for short fusing time. This
difference can be accounted for by considering the definition of "time to fuse". The
experimental data points represent total time to fuse which includes rise time of the programming pulse, time for the fuse to heat to sufficient temperature, and time of the actual
fusing event. For example, Figure 11 shows a typical current trace for a fuse programmed
under constant voltage conditions. The trace shows a fixed rise time, tr (about 100 nanoseconds for this datal. a response time; tm, for the nichrome 'to reach the melt temperature,
and a time for the fuse neck to enter the melt phase and program, tf. Plotting the time
defined as tm shows excellent correlation with the theoretical prediction of the time to
reach melt temperature. The difference between the theoretical prediction to reach melt
and the actual time to fuse agrees with the measured values of tr + tf. Figure 10, therefore,
shows that fusing follows a heat flow dependence that requires the nichrome to achieve
melt. Proper PROM design necessitates taking into account thermal factors that affect the
heat flow conditions in the neighborhood of the fuse. Concentrating power by optimum
fuse geometry and ensuring sufficient power to the fuse will achieve fast, uniform programming.
For power density conditions below the programming threshold level, the fuse temperature
as a function of power density into a fuse for a sustained pulse (t __ ex> ) is shown in Figure
12. There is good agreement of the computer model with experimental data. The experimental data was derived from measuring the fuse resistance (at reduced current, avoiding
12R heating) of an externally heated fuse and comparing that to the power necessary to
generate the same resistance at an ambient temperature of 250C. The agreement between
model and experimental data is a further indication that the heat flow analysis is correctly
projecting the temperature in the fuse.
5-15
Ii
It is also relevant to note the low power density ona fuse in the read mode, 5% of the
threshold power density to melt the nichrome fuse. Test vehicle fuses. were stressed at
1 watt/mil~ which i.s 65% of the fusing threshold level and equivalent to a fuse temperature
of BOOOC. No failureoccured after 4000 hours of continuous operation. Thus, the designed power density for PROM operation in the. read mode avoids theoccurence of unprogrammed fuses becoming open.
In summary, the power density vs. time to program cUrVe,Figure to, agrees with the heat
flow model and implies a single mechanism, melting for both fast and slow fusing .. High
power fusing (fast blow) apprqaches adiabatic heating conditions and therefore gives a large
melted region and wide gap .. Restricted power programming (slovv blow) allows much of the
heat to diffuse away taking .iongerfor the fuse to reach melt.
MARGINALLY PROGRAMMED FUSE
By grossly violating recommended programming procedures for flJses, it is possible to
create a marginal fuse gap that may be subject to reverting state ("growback"). This anomaly was induced in a test vehicle fuse by restricting the power input to a value on the t
- ' " asymptote ( '" 1.5 watts / mil2 )of the power density vs. time to fuse curve (Ref.
previous section, Figure 10). Under these conditions, a fuse was induced to program,
become electrically discontinuous, after 5 minutes of sustained power. This effect, programming under an anomalously reduced power, was not found to be reproducible. Many
fuses at this power would not program after days.
This deliberately improperly programmed fuse was subsequently subjected to a slowly
applied DC voltage ramp under current limited conditions (10M resistorih series). At 12
volts, the fuse ..resistance dropped to '" 5000 ohms. The TEM photograph of this fuse is
shown in Figure 13. It is obvious from this photograph that the reduced· power condition
has resulted in a fuse that has marginally. programmed. That is, the gap created after programming is very narrow (approx.imately a few hundred angstroms) and subject to avoltage
breakdown effect.
Fuses programmed per the. recommended power levels will program rapidly with a wide
gap as illustrated in the Mass Transport Models section. These fuses can be subjected to
more that 100 volts and will undergo no change in electrical or physical condition.
As indicated in Figure 13, if a restricted amount of power is appli.ed to a fuse, it is possible
to create a· very narrow gap. Under the presence of high voltage and extreme current
limiting, it is then possible to force a voltage breakdown across the gap. It is postulated
that this voltage discharge results in the establishment of a low conductivity rei ink at one or
a few points of closest approach in the marginally blown gap. This specific structure could
not be confirmed with the TEM study because even the TEM did .not have resolution to
examine.microsturcture at < 300 angstroms.
This mechansim of marginal programming is precluded from occuring inan actual PROM
circuit because the programming specification, specifically the power and pulse Widths,
have been established to only generate well blown, wide gap fuses. That is, if the power
actually reaching a fuse is lower than that required to blow the fuse properly, the fuse
will not program in the time allotted for the programming pulse. The device, therefore,
becomes a programming reject (won't program) and is scrapped.
In summary, the observation that a nichrome fuse can be marginally programmed has no
connection with the reliability of th~ PROM circuit. Recall, to generate this anomaly, a
power density four times less than the designed value and a program time rv 10B times
longer than the. maximum specified programming time was required. Further, a voltage
'" 10 times higher than the maximum that would be seen in an actual PROM,(with current
limiting) was required to cause the rei ink.
5-16
Obviously, these observations and conclusions are based on nichrome fuses,PROM design,
and control procedures as deployed by this manufacturer. Contentions by others that a
specific fuse material, nichrome or something else, is more or less reliable must be interpreted in prespective of the manufacturer's technology and not necessarily be construed as
being generally representative.
LIFE TEST RESULTS
Life testing data of programmed PROM's has been accumulated for several years of production. The data in Table III summarizes those results. The total sample base represents
a multiplicity of designs and configurations (256, 512, 1024,2048, and 4096 bit PROM's).
These samples were selected from production runs that had passed the standard final test
program and were programmed to data sheet programming procedure. The burn-in conditions are representative of typical applications (except for elevated temperature). The
results indicate that the level of reliability of these PROM circuits is equivalent to circuits
of similar complexity that do not utilize fusible links.
SUMMARY
(1) Conduction electrons in nichrome have a short mean-free path. This maximizes 12R
heating and precludes electromigration in the direction of electron flow as a fusing
.
mechansim.
(2) Transmission electron microscopy is the only effective analytical tool to characterize
the programmed fuse gap structure.
(3) Nichrome fuses program by molten metal (nickel, chrome). ions moving in the presence
of an electric field. The final structure resembles a frozen splash and is described by
fluid dynamics.
(4) Thermal analysis coupled with empirical programmed fuse data indicate a threshold
power density for fusing. If this power density is exceeded, which can be assured if
the programming time utilized is as specified, the fuse gap will be wide and reliable.
If this power density threshold is only matched, it is possible to create a marginal
fuse.
(5) Life test results indicate programmed PROM reliability is equivalent to devices of the
same complexity that do not utilize fusible links.
REFERENCES
14. Kenny, G. B., Fusing Mechanism of Nichrome Resistors
in PROM devices, M. S. Thesis, MIT, June, 1975.
15. Huntington, H. B., and Grone, A. J., Phys. Chem. Solids,
20,76 (1961).
16. Soret, Ch., Arch. de (Geneve, 3, 48 (18791.
17. Fick, A., Pogg. Ann, 95, 59 (18851.
18. Jost, W., Diffusion in Solids, Liguids, Gases, p. 470,
Academic Press (19601.
19. Franklin, P. and Burgess, D., Reliability Aspects of
Nichrome Fusible Link PROM's, 12th Annual Proceedings
IEEE, Reliability Physics Symposium, pp. 82-86, 1974.
20. Davidson, J. L.,
PROM Reliability, Presentation at
NEPCON, Boston, Mass., October 1974.
21. Rossiter, T. J., THEROS, A Computer Program for
Heat Flow Analysis, RADC Technical Report - 74-113,
1974.
22. Advertisement, Fairchild Semiconductor, "ELECTRONICS", p. 39, July 24, 1975.
23. Bechtoldt, C. J. and Vacher, H. C" Trans AIME Vo.
221, p. 14, (19611.
24. D'Heurle, F. M., Proc. IEEE, 59, 10 (Oct. 19711.
25. Wever, H., Z. Elektrochem., 60, p. 1170 (19561.
1. Press Release, Harris Semiconductor, May 41970
2. MO,R. S. and Gilbert, D. J., J. Electrochem. Soc., 120,
7 Pp. 100-1003, (1973),
3. Jones, K. W., Plasma Etching as Applied to Failure
Analysis, 12 Annual Proceedings IEEE, Reliability Physics
Symposium, pp. 43-47,1975.
4. Ziman, J: M., Electron and Phonons - The Theory of
Transport Phenomena in Solids, Oxford Press, 1972.
5. Coles, B. R., Phys. Soc.; B, 65, 221.
6. Chopra, K. L., Thin Film Phenomena, McGraw-Hili,
1969.
7. Nagata, M·. et aI., Proc. Elec. Compo Conf" 1969.
8. L. Holland, "Thin Film Microelectronics", p. 17-19,
Chapman and Hall, Ltd., (19661.
9. Nat. Bur. of Standards Pub!. 296, Ed. by Wachtmon,
J. B., et al" P. 125, (19681.
10. Wells, A. F. "Structural Inorganic Chemistry", P. 379,
Oxford Press (1950),
11. Philofsky, E. et aI., Observations on the Reliability of
NiCr Res;stors, 8th Annual Proceedings IEEE, Reliability
Physics Symposium, pp. 191-199, 1970.
12 Jones, K. W., et aI., Fusing Mechansim of Nichrome
Resistor Links in PROM Devices, 14th Annual Proceedings IEEE, Reliability Physics Symposium, 1976.
13. Harris Integrated Circuits Data Book, pp. Me-28-55,
August, 1975.
5-17
I
OXIDATioN OF NICHROME
CONDUCTION PROPI:RTIES OF NICHROME
_NICKEL AND CH~ort1lUN! ~RE TRANSITION METALS.
• NH:r FORMs SELf L;'IMIl'ING SKIN OXIDE
• INNER SHELL ELECTRONS CONDUCT, OUTER SHELL SHIELDS. HIGHER RESISTANCE.
• SPiNEL THlCKNESS;;:oi
_ALLOV EFFECT ENHANCES SHIElDINGIRESISTiVlTv.
,
,50
DIFFUSION
COEFFICIENT
x
'2.
~.
.
~
,/
p' •
/
( pOem.
50
.1
II
.
\
O-REF.A
X-REf,C
30
40
_Ct .~~. NiC.raCJ.t _ ••
~
~i
:,\
o(cm2)
in NiCrzu. _
O.. N~
.I~EF.A'
')
t'\
·SEC.
w ..
O-REf.B
20
i :
• pROMOnS RESIsrOR stAelllTV
...
w ..
Tlo(:'
\
SPINEL GENERAL
FORM IREF. Sf
AlIA
(NICr:to.o)
.
60
WEIQHT%
, Ref. A - ;:~.IS ~!~n$pO't in'6xi~}' NBS Pu~. ~:(1981U:
. A'~ Handbook.of ChemiUry·lind Physics.
a -: Thin Film Tech."oIQ9Y, R. WA Berry. el. ai,
Japanese Metal Matefllil 'Handbook: V. Yamamoto', et.' iii.
Ref." -:- A. F. wells, "Slructu~81Inorganic:'CMWIist,y:\'Odord P,essI19SO).
t .:.
Figure 3
Figure 1
.
'" .'. ) " '.
• .
c'.
.'.~, ;,' ,
•
;i ,;~,::
,
SCANNING TRANSP.1ISS,ON. ELE.CTRON
MI'CROSCOPY ANALYSIS .oj:: FUSES
• SHORT MEAN FREE PAnt LENGTH OF ELECTRONS
• BULK"REStSTlVITV IN THIN fiLM.
• ooClO FILM REPRODUCIBILITY
PfPb .JlBUlI(
M RuJIVITY
RESrSTIVITY
"
i·
\
I
....
NiCt
\.'''f.A'
1
1.... 8'
1\
\"- -
"
IDE~~CTdR I
-- - .... ---- --- -- ---'0
20
50
lOG
200
500
,
'.1
1000
FILM THICKNESS Ii)·
FigUre 4
Figure 2
5-18
STEM PROGRAMMED FUSE
PROGRAMMING CONDITIONS:
POWER - 150 mW.
10
TIME TO FUSE· 2 joISEe.
• Liquified gases
o Other liquids
~ Alcohols
~
's
~
.;
5
'0
..,
u.
0
15
.lE of vaporization
Fig. 11-:!4. Empirkal relation between free energy ofadivation in liquids,
energy ufevaporation. ~H, Rosevaere, Powell and Eyring.
~F.
and
TAHLF II
C'orrected ratio of energy of vaporization and activation for viscous flow
)(etsl
POINT MICROPROBE ANAL VStS
A-NiCr
B - MEL TED Nie,
I---
c-
Si02. CHROMIUM OXIDE
0-Si02
GAflREGIO/II
Zn
--o... ~-o.'i
E - DENSIFIED Nie,
,,0---0---0-
:,
,,
F - FIELD OXIDE ISi021
~~E
,
II-R"''''
Na
K
Ag
--I
.:
Cd
Ga
Ph
Hg
Hg
I
~ ..
I
--o---o'
_0
Sn
Sn
U~ltNSITY L.-+-~t--+--+--+-+-----=--
NOTE: (AI "FROl,EN SPLASH" EFFECT
PROGRAMMING HAS MEL TEO
--o--..
Nie, IN GAP REGION.
o-~\
.
An"rage
temp.
ce.
500
480
1400
850
750
800
700
250
600
600
1000
~1l!.'NP
.JA·rirr
.1 Et'Gp kcal. .IEr·i...kcoJ. .11<:1'IIP
~
1.45
1.13
4.82
3.09
1.66
1.13
2.80
0.65
0.55
1.4"
1.70
23.'
19.0
60.7
26.6
22.5
3'.1
'2.6
13.6
12.3
16.3
1'.5
16.1
16.7
12.6
8.6
13.6
30.3
16.9
20.8
22,2
10.6
8.6
("jim
rlllo,"
r
2.52
3.'1
3,.79
2.10
3.96
2.63
4.97
2.37
3.M
•. 07
3.30
,""0"--0---0-
,,.
'0-_ ,--d
(B) MASS TRANSPORT IN GAP.
Ie) MASS ASYMMETRV rq NEGTlVE TERMINAL.
From "Diffusion in Solids, Liquids, Gases", W.•Iost.
~
-0
Figure 5
Figure 7
TEMPERATURE PROFILE IN FUSE NECK
FROM HEAT FLOW MODEL
\-1
('
FUSE
STRUCTURE
POST
PROGRAMMING
'!
~
r
~
~.
MOLTEN ZONE
_GAP_
0
POWER DENSITY IN FUSE NECK REGION
I
i""-L
I
POWER DENSITY =,2 ( PS/Jw)
!L·w)
1.
TEMPERATURE
PROFilE DURING
PROGRAMMING
,/"
I
\
TJ -TO)
Tmax - Ta
Psi/w =
0.7
p.
=
l.w=
0
L
Figure 6
RESISTANCE OF THE
FUSE NECK (OHMS)
1=
LENGTH OF FUSE
NECK
SHEET RESISTIVITY OF
NICHROME (OHMS/SQ)
w=
WIDTH OF FUSE NECK
, =
PROGRAMMING
CURRENT ( ,= VF/RF)
AREA OF FUSE NECK
(MIL.2)
Figure 8
5-19
DYNAMIC HEATING OF NiCr FUSE
VS.
POWER DENSITY
3500
3000
2500
~
.
2000
0:
::>
>-
'"
0:
~
~
1500
1000
500
10
1000
100
TIME (",SEC)
Figure 9
POWER DENSITY VS. TIME TO FUSE
(t, + tf)
TYPICAL CURRENT TRACE
OF PROGRAMMING PULSE
6 -tm
1f~5OOns
,.-- NiC, IN MELT PHASE
,
,,
tm-001 l !-«,,
I
I
;
tf
4
" . RISE TIME
tm • TIME FOR NiCr TO REACH
MELT
tf· TIME FOR Nie, TO PROGRAM
>
>-
in
~
c
I
3
..
COMPUTER PREDICTION OF TIME
FOR NiCr TO REACH MELT ttml
.... EXPERIME~TAL RESULTS OF TOTAL
TIME TO FUS.E, h, + tm + tpl h, Ii:;: 100nsi
a
EXPERIMENTAL R£SULTSOF TIME TO
MELT Itm)
100
1000
TIME (/lSI
Figure 10
5-20
10,000
100.000
10,00
PROGRAMMING PULSE CHARACTERI.STlCS
~
§
....z
w
a:
a:
:>
u
TIME (500ns/cml
"
•
RISE TIME OF PROGRAMMING PULSE
tm·
TIME FOR NiC, TO REACH MELT
t, .
TIME OF THE FUSING EVENT (IONIC MASS TRANSPORT)
Figure 11
MAXIMUM FUSE TEMPERATURE VS. POWER DENSITY
104
/
/
I
/
/
~w
103
@
I;ROGRAMMING I
MODE
a:
:::>
/
....
«
~
/x
1!i
....
OE
:::>
.,a:
///
::;
'5
S
/x
1()2
x
-MODEL
- X - EXPERIMENTAL DATA
@ NICHROME MELT TEMPERATURE
r-
READ MOOE--1
POWER DENSITY (WATTS/MIL2)
Figure 12
5-21
MARGINALLY PROGRAMMED TEST VEHICLE FUSE
PROGRAMMING CONDITIONS.:
POWER DENSI1'y z 1.5 WATTSIMIL:t
TIME TO FUSE" 300 SEC.
FORCED RELINK OF MARGINALLY PROGRAMMED TEST FUSE
SLOW RAMP
D.C.
AT 12 VOLTS.
RF·DROPPED TO:><5KU
PROGRAMMED
rEST VEHICLE
FUSE
Figure 13
OPERATING LIFE TEST RESULTS
#DEVICES
ALL PROM TYPES
3840
I
#
DEVICE-HAS
#FAILURES
ACTUAL
FAILURE RATE
FAILURE RATE
110% c.L.11I
3(3)
O.03%/K HRS(4)
O.046%/K HRS(4)
IMnF - 3.3 x 1011
HRS)
IMTTF - 2.16xlo11
HRS)
1.03OM
DERATED TO 250C
o
O.OO4%1K HRS
O.OO5%/K HRS
IMTTF - 2.5 x 107·
HRS)
IMTTF - 1.65 x 107
HRS)
BURN-IN SCHEMATIC
1M
(1)
C.L. lCONFIDENCE LEVEL)
(2)
FUSE MATRIX: 50% PROGRAMMED
RANDOM PATTERN AS PER PRESCRIBED
PROGRAMMING PROCEDURE.
(3)
NON-FUSE RELATED FAILURES
(4)
SAME OR BETTER THAN MSI FAILURE
RATES IREF.MDFR 1273 - ROME AIR
DEVELOPMENT CENTER)
CS
10
A2
I
TA"+I25OC
VCC"S.5V
lMHz· 1M = 210·411· 812" ••••
Table III
Microscopic Observations of Fuses
Steve Harris, Memory Applications Manager
Beauty is in the eye of the beholder. When the eye is attached to a microscope, beauty
can take strange forms. Nowhere is this more evident than when the realm of blown fuses
in PROMs is entered. This paper will "shed some light" on the misinformation which
has been generated regarding the nature of nichrome fuse gaps as viewed by different microscopic techniques.
WHAT YOU SEE OPTICALLY
Using a light microscope to examine fuse structures is a futile exercise because the wavelength of visible light is within an order of magnitude of the total fuse dimensions. The
microstructure of the fusing process reaction zone contains formations that are smaller
than a wavelength of light. In addition, the overlying passivation acts like an aberrant lens
and distorts the image which is visible. The most that can be reliably ascertained regarding
the nature of a fuse with optical microscopy is whether the fuse is physically present or
absent.
Photo 1 * illustrates this physical phenomenon. The photograph is of photoresist after exposure to ultraviolet light and normal d,eveloping solutions. The ridges in the vertical
portion of the photoresist are produced by the standing wave that is present due to reflection of the U. V. light from the oxidized silicon during resist exposure. As can be seen,
the ridge pattern has a wavelength A of the incident light ( A = 3650nm), the index of
refraction of the photoresist is n = 1.58; thus, for visible light on the order of A= 5000nm,
less than ten wavelengths are needed to span the fuse neck region.
WHAT THE SCANNING ELECTRON MICROSCOPE SHOWS
The SEM is a useful analytical tool for many applications. This is amply demonstrated by
Photo 1 that showed us the standing wave pattern in photoresist.
The SEM does have limitations in observing fuses, however. For one, it cannot "see"
through the passivation layer on top of the fuse. This necessitates the removal of the
glass and hence, physical and chemical alteration of the fuse gap microstructure. In addition, the results after depassivation are misleading. A SEM of a depassivated typical programmed NiCr fuse is shown in Photo 2. Photo 3 is a typical programmed polysilicon fuse
as deployed in the CMOS PROM.
Previous observers have never reached satisfactory explanations for the fusing phenomena
based on SEM photographic evidence. The important facts to consider here are that for
both fuses, an electrical discontinuity has been achieved through programming. In both
cases, the observer is hard pressed to determine how this was achieved, for his eyes tell
him that both fuses appear physically connected in various areas. Electrically, we know
this is not the case.
This brings us to the crucial observation that the SEM cannot distinguish between el.ectrical conductors and electrical insulators. This is readily confirmed by observing the lack
of differentiation afforded in the SEM view of the adjacent aluminum interconnect (an
excellent conductor) and the underlying silicon dioxide (an excellent insulator). Since both
of the above fuses are electrically discontinuous, some portion of their makeup is insulative,
but the Scanning Electron Microscope gives us no clues as to the integrity of the insulator.
'Photos Found on Pages 5-25 Thru 5-27.
5-23
Ii
TRANSMISSION ELECTRON MICROSCOPY ANALYSIS OF FUSES
A fresh approach in fuse analysis has been developed to view a fuse without disturbing
tbe conditions present at the time of programming. Basically, the technique uses a thinned
specimen PROM with the fuses sandwiched between the two normal glass sheets found on
the PROM (the passivation above and thermal oxide below) with the underlying silicon
substrate etched away as shown in Photo 4. Now standard high resolution bright and
dark field TEM (Transmission Electron Microscopy) analytical techniques are available.
Photo 4 is a TEM photograph of a typical programmed NiCr fuse. Now we can see which
regions of the blown fuse are conductive metal and which are not. The well-defined darkened regions are metallic while the overlying gray, which is all that was seen by SEM,
has proven by electron diffraction analysis to be a stable insulating oxide compound with
crystalline order that resembles a NiCr204 spinel. The surrounding region of high transmission are characteristic of the undisturbed passivation and underlying thermal Si02.
Therefore, Transmission Electron Microscopy has the. capability of determining the true
chemistry of programmed NiCr fuses.
5-24
PHOTO 1A
••
PHOTO 18
5-25
SEM Photographs of Programmed Fuses
PHOT03A
I
PHOT02a
PHOT03B
I
PHOTO 4
5-27
Section 3.
Reliability Screening Programs
Reliability Screening Programs
Facility Qualification
Harris is closely attuned to the requirements of military quality and reliability manufacturing programs. Our facilities and its quality plan is well accepted at all major companies.
In addition, we have JAN qualification in the Bipolar Memory area and have JAN qualifications in process on CMOS Memory and Linear products.
MIL-STD-883A Class B (Dash 8)
As a special service to users of high rei products Harris makes instantly available high reliability on many of bur product lines, Simply by adding its postscript -8 to appropriate
Harris part numbers "off the shelf" delivery can be obtained of products screened to MILSTD-883 Method 5004 Class. B.
Hi-ReI Program
To meet our commitment to CMOS growth, Harris has introduced the Hi-Rei Dash8program. This program is designed to meet the needs of the customer seeking enhanced quality
and reliability by additional screening steps.
.
This program is designed for:
• Customers using a current reliability add-on program.
• For the individual seeking atrade-off between additional costandill1proved reliability
and quality through screening - Harris gives a broad selection f;rorriGlass B flow to
burn-in only.
.
The Harris Hi-Rei Program is a comprehensive program aimed .atserving the various needs
of many customers. With the increasing need for 'improved IGsystems meantimeto failure
performance, the Hi-Rei program assures high quality and reUability.of CMOSctrcuits.
Harris CMOS devices have been produced for over 6 years inrnodernstateoftheartrnanufacturing facilities. Our irnplerne~ted second and thirdge~erati()lJrnask desi~ns with the
experience of well-controlled processes, results in standardprdducts with built-in reliability.
Coupling Harris CMOS with a. Hi-Rei. program will result in an enhanced combination
for quality and reliability.
.
User Benefits
• Eliminates user screening programs
• Provides uncomplicated incoming inspection
I
• Reduces infant mortality and board rework
• Reduces field failures and unnecessary maintenance costs
Quality
I n theory, parts tested 100 percent s~ould upon receipt at the user's site be 100 percent
good. Due to the mass production of CMOS there may exist a small percentage of parts
which escape 100 percent tests. The AQL or L TPD outgoing sampling plans at Harris have
been very successful in stopping the DOA's (Dead on Arrival). For the user with complex
systems using large quantities of products, a quality enhancement can be tailored into your
specific Hi-Rei program by choosing tightened sampling plans. The tightened quality test
plan ensures close maintenance of the improved quality level through careful product segregation and retesting.
5-28
Reliability
Experience and perfected process controls have built reliability into a standard Harris
CMOS product. Reliability cannot be tested into a part. Quality level may be improved
by retesting and tighter sampling plans. However, reliability is improved by proper design
and observance of sound ground rules, controlled processes and finally by stress testing
to confirm claimed reliability performance. The Hi-Rei program offers a varied mix of
stress tests to compress time and weed out devices subject to infant mortality. The equivalent early life failures are removed by the various screens· such as temperature cycling,
stapilization bake, burn-in and high temperature functional testing. Some or all of these
~tress tests will remove early failures and thus improve overall system reliability.
Dasb 8 Program -
MIL-STD-883; Off-the-Shelf Delivery; MIL-STD-883/MIL-M-38510,
MIL -Q-985.8A
INTRODUCTION
Statement of Scope
This section establishes the detail requirements for Harris' Circuits screened and tested
under the Product Assurance Program.
The Harris DASH 8 Devices pass the screening requirements of the latest issue of MI LSTD-883, Method 5004, Class B, and the requirements as specified in this document.
Included in this section are the quality standards and screening methods for commercial
parts which must perform reliably in the field.
Applicable Documents
The following Military documents form a part of this section to the extent referenced
herein and provide the foundation for Harris Products Assurance. Program,
MIL-M-38510
MIL-Q-9858A
"General Specification for Microcircuits"
"Quality Program Requirements"
M I L"':STD-883
"Test Methods and Procedures for Microelectronics"
NASA Publication 200-3
"I nspection System Provisions"
Harris maintains a Product Assurance Program (PAP) using MIL-M-38510 asa guide.
Harris Product Assurance Program assures compliance with the requirements and quality
standards of control drawings and the requirements of this specification.
The DASH 8 Program will also be found useful by those Harris customers who must generate their own' procurement specifications. Use of the enclosed Harris Standard Test
Tables, Test Parameters, and Burn-In Circuits will aid in reducing specification negotiation time.
.
NOTE: At the time of this printing, a new industry Standard Method for production of
Class Band C microcircuits was being defined by JEDEC. Harris intends to implement this
new standard procedure. The procedure embodies all relevant device screening sections of
Mil. Spec. 8838 and 385100 and is quite similar to our current Dash 8 program. Please
consult your Harris representative if you are interested in. procuring parts to this standard
specification.
PRODUCT ASSURANCE AT HARRIS
qur Product A.~~Wiilnce Department strives to assure that the quality and reliability of
p'r()ducts shipRed :to cuslomerSis of a high quality level and consistent with customer
requirements.· D'uring product' p'rocessing, there are several independent visual and electrical checks performed by Quality Assurance personnel.
Prior to shipment, a final inspection is performed at Quality Assurance Plant Clearance
to insure that all requirements of the purchase order and customer specifications are met.
The system and procedures used and implemented are in accordance with MIL-:M-38510,
MI L-Q-9~58A, MI L-STD-883A, MI L-C-A5662 and MI L-I-45208.
The Harris Semiconductor Reliability and Quality Manual which is available upon request,
describes the total function and pol icies of the organization to assure product reliability
and qual ity.
I
HARRIS SEMICONDUCTOR DASH 8 PRODUCT FLOW
MI L-M-38510/Mlt-STD-'883, METHOD 5004 CLASSB
100%SCREENINGPROCEDlJRE
MlbSTD-883 METHOD/COND.
2010 Condo B.
Stabilization Bake
1080Cond. C (24 hrs. minimum)
Temperature Cycling
1010 Condo C
2001 Condo E; Yl plane
seal:@Fine.
® Gross
1014 Cond.AorB
1014 Condo C2
Initial Electrical
Harris Specifications
Burn-In Test
1015,160 hrs. @ 1250C (or.equivalent) (Burn-In circuits enclosed)
Final Electrical
100%.go-no"'90
Tested at Worst Case Operati ng
Conditions
External Visual
2009 Sample Inspection
Lot Acceptance
Table I, GroupA Elect. Tests
Note:
I
Traceabil itV:
All devices· are assigned date code identification that provides traceability
back to the inspection lot.
Branding:
All devices are branded with the HX-XXXX-8 and EIA date code.
Aged Products:
Product that has been held for more than 24 months will. be reinspected
prior to shipment to group A inspection requirements ..
Additional
Requirements:
Attributes data will besi:Jpplied on Group A Lot Acceptarice upon request.
Generic data from Harris' Reliability Add-On Program is available upon· request. The objective
of Harris Reliability Add-On Program is to provide a continuous liJe and .environmental
monitor for all products families in manufacturing. This program provides life testperformance results to fullfil! reliability data requirements and to verify package integrity; The
Reliability Add-On Program is supplemental to customer. funded Lot Qualification.
For customers desiring Lot duaiification, Harris Semiconductor will perform GroupA, B, C
and D inspections to MIL-STD'-883, Method 5005 as definedherein for an additional charge.
STANDARD PRODUCTS SCREENING AND
INSPECTION PROCEDURE
PRODUCT CATEGORIES
MIL
1M)
COMM
IC)
EPOXY
IE)
Incoming Material
Silicon and Chemical Procurement.
X
X
X
Q.C. Incoming Inspection. Materials
are Inspected for Conformance to
Specified Requirements.
X
X
X
Manufacturing Wafer Fabrication
X
X
X
X
X
X
Manufacturing, Wafer Electrical
Probe (100%)
X
X
X
Manufacturing, Wafer Scribe,
Break (100%)
X
X
X
Manufacturing Dice Screen (100%)
X
X
X
QA Dice Inspection Control
X
X
X
Preform Procurement
Package Procurement
Leadframe Procu rement '
Epoxy Compound Procurement
X
X
X
N/A
N/A
Q.C: Preform Inspection
Q.C. Package Inspection
Q.C. Leadframe Inspection
X
X
X
X
N/A
N/A
X
Manufacturing Package Clean
X
X
N/A
Manufacturing Die Mounting
X
X
X
OPER. SEQ.
M
C
E
OPER. DESCRIPTION
QC
M
C
E
M
C
E
M
C
E
• PIH20 & Gas Monitor
• SEM Process Control
• Wafer Process Control
X
X
X
I
QA Die Mount Control
(continuous sampling)
• Visual Die Inspection
X
X
X
Bond Wire Procurement
X
X
X
Q.C. Wire Inspection (receiving)
X
X
X
X
X
AI
AI
X
Au
X
X
X
MS883
Method
2010
Condo
A or B
MS883
Method
2010
HS
Mod.
Condo
B
MS883
Method
2010
HS
Mod.
Condo
MS883
Method
2010
Condo
Aor B
MS883
Method
2010
HS
Mod.
Cond.
B
MS883
Method
2010
HS
Mod.
Condo
B
Preseal Bake Per MS-883,
Method 1008, Condo C
8 hr.
4 hr.
4 hr.
Package Lid Procurement
X
X
N/A
Package Lid Inspection
X
X
N/A
Package Lid Clean
X
X
N/A
Package Seal/Encapsulation
X
X
X
QA Package Seal/Encapsulated
Control (continuous sampling)
X
X
X
Manufacturing Wire Bonding
QA Bond Control (continuous
sampling)
• Visual Die & Bond Inspection
• Wire and Pull Test
M
C
E
Manufacturing Pre-Seal Screen
(100%)
QA Pre-Seal Inspection
Lot Acceptance
M
C
B
'"
I
M
C
E
5-32
M
C
E
Stabilization Bake
MS-883, Method 1008, Condo C.
M
Temperature Cycle, MS-883,
Method 1010. Condo C,
24 hr.
8 hr.
8 hr.
X
X
N/A
Centrifuge, MS-883, Method 1010,
(Yl) Plane 30 KG's min.
100%
X
N/A
M
C
Fine Leak, MS-883, Method 1014
100%
X
N/A
M
C
Gross Leak, MS-883, Method 1014
Condition C2
100%
X
N/A
M
C
E
Frame Removal & Loading Units
In Carriers/Sticks
X
X
X
Final OA Lot Inspection, MS-883
Method 1014
• Fine & Gross Leak
• Visual/Mechanical Inspection
X
X
X
X
X
X
X
N/A
N/A
Classes
A/B
Products
N/A
N/A
M
C
E
Group A Initial Tests 1.
M
Brand Device Type/Date Code
Serialize, If Applicable
M
Burn-In (100%), MS-883,
Method 1015
C
E
I
M
C
E
M
C
E
Group A Final Test (100%) 1.
X
N/A
N/A
OA Acceptance Elec. Testing
• Visual/Mechanical Method
2009 Lot Sampling
X
X
X
Brand Devices Type/Date Code
N/A
X
X
X
X
X
Controlled Inventory
5-33
M
C
Package for Sh ipment
X
X
X
Quality Conformance Inspection
Group a/c/o Testing, MS-883,
Method 5005, Periodically or by
Customer P.O. Request
X
X
X
QA Plant Clearance
• Final Visual of Marking and
Physical Quantity, Conformation
of Product by I nspection or
Sample Test
X
X
X
Ship to Customer
X
X
X
E
M
C
E
NOTE: 1. Group A, Subgroup I, 2, 3, & 9 for Bipolar - Table I, Subgroup 2 & 10 for CMOS.
HARRIS.COMMERCIAL GRADE PRODUCTS
This product is processed on the same wafer fabrication lines, to the same thorough
specification and rigid controls as HI-Rei parts. At wafer electrical probe the product may
be categorized for electrical performance, such as temperature range of operation or maximum output (see specific product data sheet for grading details) by utilizing multiple
colored inks. Defective die are inked with red ink, but, for example, die meeting the
commercial temperature range electrical specifications may be inked with green ink.
I
The die are then visually inspected and sorted after die separation to a modified Class B
visual criteria. They are then assembled in packages on a controlled assembly line. The ink
used to categorize product performance, such as the green ink, might not be removed from
the commercial grade die. This ink has'been chemically characterized as inert and reliability verification confirms there is no effect on performance or operating life of the
.
parts.
Harris invites any interested customer to review our assembly flow and facilities for information, quality survey, or certification.
5-34
TABLE I - GROUP A ELECTRICAL TESTS
1.
CLASSESS& B
LTPD
CLASSC
LTPD
5
5
Subgroup 2
Static Tests at Maximum Rated
Operating Temperature
7
10
Subgroup 3
Static Tests at Minimum Rated
Operating Temperature
7
10
5
5
10
15
7
10
Subgroup 10
Switching Tests at Maximum Rated
Operating Temperature
10
15
Subgroup 11
Switching Tests at Minimum Rated
Operating temperature
10
15
SUBGROUP2.
Subgroup 1
Static Tests at 250C
Subgroup 7
Functional Tests at 250 C
Subgroup 8
Functional Tests at Maximum and
Minimum' Rated Operating
Temperatures
Subgroup 9
Switching Tests at 25 0 C
1. The specific parameters to be included, for tests in each subgroup shall be as specified in the applicable
procurement document. Where no parameters ha,va been identified ,in a particular subgroup or test within
a subgroup, no group A testing is required for that subgroup or test to satisfy group A requirements.
2. A single sample may be used for all subgroup testing. Where the required size exceeds the lot size, 100%
inspection shall be allowed (see 30.2.5 of Appendix B of MIL-M-:-38510l.
5-35
I
TABLE II - GROUP B TESTS (LOT RELATED)
1
MIL-STD-883
TEST
METHOD
CONDITION
..
LTPD*
Subgroup 1
2016
2 Devices
(No Failures)
a. Resistance to Solvents
2015
3 Devices
(No Failures)
b. Internal Visual and
Mechanical
2014
Physical Dimensions
Subgroup
2.
c. Bond Strength 2.
(1 ) Thermocompression
(2) Ultrasonic or Wedge
(3) Beam Lead
2011
FailiJre Criteria from Design imd
Construction Requirements of Applicable
Procurement Document.
1 Device
(No Failures)
(1) Test Condition Cor D
(2) Test Condition C or D
(3) Test Condition H
15
Soldering Temperature of 260 ±1 OOC
15
Subgroup 3
Solderability 3.
2003
NOTES:
1.
Electrical reject devices from the same inspection lot may be used for all subgroups when end point measurements are not required.
I
2.
Test samples for bond strength may, at the manufacturer's option unless otherwise sPecified be randomly
selected immediately following internal visual (precap) inspection specified in method 5004, prior to sealing.
3.
All devices submitted for solderability test must have been through the temperature/time exposure specified
for burn-in. The LTPD for solderability test applies to the number of leads inspected except in no case shall
less than 3 devices be used to provide the number of leads required~
4.
Generic data from Harris Reliability Add-On Program in the form of Reliability Bulletins are available upon
request.
* Reference Note - Table 1*
TABLE III - GROUP C (DIE-RELATED TESTS)
MI L-STD-883
TEST
CONDITION
METHOD
LTPO*
Subgroup 1
Operating Life Test
1005
End Point Electrical
Parameters
Test Condition to be specified (1000 Hrs)
5
Table I - Subgroup 1
Subgroup 2
Temperature Cycling
1010
Test Condition C
Constant Acceleration
2001
Test Condition E
Yl Axis
Seal
(a) Fine
(b) Gross 2.
1014
As Applicable
Visual Examination
End Point Electrical
Parameters
1.
Table I - Subgroup 1
NOTES:
1.
Visual examination shall be in accordance with method 1010.
2.
When fluorocarbon gross leak testing is utilized, test condition C2 shall apply as minimum.
3.
Generic data from Harris Reliability Add-On Program in the form of Reliability Bulletins are available
upon request.
* Reference Note - Table 1 *
5...,37
15
TABLE IV - GROUP D (PACKAGE RELATED TESTS)
MI L-STD-883
METHOD
TEST
CONDITION
LTPD*
Subgroup 1
2016
PhySical Dimensions
15
Subgroup 2 4.
2004
1014
Test Condition 82 (Lead Fatigue)
As Applicable
15
Thermal Shock
1011
15
Temperature Cycling
Moisture Resistance
Seal
(a) Fine
(b) Gross 6.
Visual Examination
End Point Electrical
Parameters
1010
1004
1014
TestCondition 8 as a Minimum,
15 Cycles Minimum.
Test Condition C, 10 Cycles Minimum
Omit Initial/Conditioning and Vibration
As Applicable
Lead I ntegrity
Seal
(a) Fine
(b) Gross 6.
Subgroup 3 1.
2.
Table I - Subgroup 1
Subgroup 4 1.
Mechanical Shock
Vibration Variable Frequency
Constant Acceleration
Seal
(a) Fine
(b) Gross 6.
Visual Examination
EndPoint Electrical
Parameters
2002
2007
2001
1014
Test Condition 8
Test Condition A
TestCondition E (See 3)
As Applicable
15
..
3.
Table 1- Subgroup 1
Subgroup 54.
I
Salt Atmosphere
Visual Examination
1009
Test Condition A
5:
NOTES:
1.
Devices used in subgroup 3, "Thermal and Moisture Resistance" may be used in subgroup 4, "Mechanical".
2.
Visual examination shall be in accordance with method 1010 or 1011 at a magnification of 5X to lOX.
3.
Visual examination shall be performed in accordance with method 2007 for evidence of defects or damage
to case, leads, or seals resulting from testing Inot fixturingl. Such damages shall constitute a failure.
4.
Electrical reject devices from that same inspection lot may be used for samples.
5.
Visual examination shall be in accordance with paragraph 3.3.1 for method 1009.
6.
When fluorocarbon gross leak testing is utilized, test condition C2 shall apply as minimum.
7.
Generic data from Harris Reliability Add-On Program in the form of Reliability Bulletins are available
upon request.
* Reference Note -
Table 1
*
15
Section 4.
Burn-In Circuits
Burn-In Circpit Index
Drawing No.
HM-0104
HM-0168
HM-0186
HM-0198
HM-0410
HM-6312
HM-6388
HM-6389
HD-6431
HD-6432
HD-6433
HD-6440
HD-6495
HD-6600
HM-6501
HM-6503
HM-6504
HM ..6508
HM-6511
HM-6512
HM-6513
HM-6514
HM-6518
HM-6533
HM-6543
HM-6551
HM-6561
HM-6562
HM ..6611
HM-6661
HM-7602
HM-7603
HM~76LS03
HM-7608
HM-7610
HM-7610A
HM-7611
HM-7611A
HM-7616
HM-76160
HM-76161
HM-7620
HM-7620A
HM-7621
HM-7621A
HM-7625R
HM-7629
HM-7640
HM-7640A
HM-7640AR
10 x 4Diode Matrix
6 x 8 Diode Matrix
8 x 6 Diode Matrix
9 x 8 Diode Matrix
4 x 10 Diode Matrix
1024 x 12 CMOS ROM
8192 x 8 CMOS ROM
8192 x 8 CMOS ROM
Hex Latched Bus Driver
Hex Bi-Directional Bus Driver
Quad Bus Transceiver
1 of 8 Decoder-Driver
Hex Bus Driver
Quad Power Strobe
256 x 4 CMOS RAM
2048 x 1 CMOS RAM
4096 x 1 CMOS RAM
1024 x 1 CMOS RAM
64 x 12 CMOS RAM
64 x 12 CMOS RAM
512 x 4 CMOS RAM
1024 x 4CMOS RAM
1024 x 1 CMOS RAM
1024 x 4 CMOS RAM
4096 x 1 CMOS RAM
256 x 4 CMOS RAM
256 x 4 CMOS RAM
256 x 4 CMOS RAM
256 x 4 CMOS PROM
256 x 4 CMOS PROM
32 x 8 Bipolar PROM - Open Collector .
32 x 8 Bipolar PROM- Three State
32 x 8 Bipolar PROM - Three State .
1024 x 8 Bipolar PROM - Three State
256 x 4 Bipolar PROM - Open Collector
256 x 4 Bipolar PROM - Open Collector
256 x 4 Bipolar PROM - Three State
256 x 4 Bipolar PROM - Three State
2048 x 8 Bipolar PROM - Three State
2048 x 8 Bipolar PROM - Open Collector
2048 x 8 Bipolar PROM - Three State
512 x 4 Bipolar PROM - Open Collector
512 x 4 Bipolar PROM - Open Collector
512 x 4 Bipolar PROM - Three State
512 x 4 Bipolar PROM - Three State
256 x 8 Bipolar PROM - Three State
256 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Open Collector
512 x 8 Bipolar PROM - Open Collector
512 x 8 Bipolar PROM - Open Collector
1
2
3
4
5
6
Preview
Preview
7
8
9
10
24
11
12
13
13
14
15
16
17
17
18
19
20
12
21
22
23
Preview
25
25
Preview
Preliminary
26
26
26
26
Preview
Preview
Preview
26
26
26
26
31
32
27
27
Preview
I
HM-7641
HM-7641A
HM-7641AR
HM-71a42
HM-7642A
HM-7642P
HM-7643
HM-,.'Z643A
HM-71il43P
HM-7644
HM-7644A
HM-7645
HM-7645P
HM-71il47R
HM-71il48
HM-7649
HM-7680
HM-76BOR
HM-7€l80P
HM-7680RP
HM-7681
HM-7681R
HM-7681P
HM-7681RP
HM-7683
HM-7684
HM-7684P
HM-7685
HM-7685P
HM-7686
HM-7686R
HM-7686P
HM-7686RP
HM-7587
HM-7687R
HM-7587P
HM'-7587RP
JAN-0512
512 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Open Collector
1024 x 4 Bipolar PROM - Open Collector
1024 x 4 Bipolar PROM - Open Collector
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM
1024 x 4 Bipolar PROM
1024 x 4 Bipolar PROM - Three State
1024 x 4 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Three State
512 x 8 Bipolar PROM - Open Collector
512 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Open Collector
1024 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM - three State
1024 x 8 Bipolar PROM - Three State
1024 x 8 Bipolar PROM
2048 x 8 Bipolar PROM - Open Collector
2Q48 x 8 Bipolar PROM - Open. Collector
2048 x 4 Bipolar PROM - Three State
2048 x 4 Bipolar PROM - Three State
2048 x 4 Bipolar PROM - Open Collector
2048 x 4 Bipolar PROM ~ Open Collector
2048 x 4 Bipolar PROM - Open Collector
2048 x 4 Bipolar PROM - Open Collector
2048 x 4 Bipolar PROM - Three State
2048 x 4 Bipolar PROM - Three State
2048 x 4 Bipolar PROM - Three State
2048 x 4 Bipolar PROM - Three State
JAN Qualified PROM
I
5-40
27
27
Preview
28
28
Preliminary
28
28
Preliminary
26
26
Preview
Preview
29
30
30
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Pretiminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Prel iminary
33
Burn-In Circuits
a
HM-0104
II
NOTES,
HM-0168
NOTES,
= 500
R = 500
R
.±10%, %W
±.10%, "h.W
VIN = 6.3V RMS 60 CYCLE
VIN = 6.3V RMS 60 CYCLE
II
HM-0186
II
HM-0198
~~NC
R
2
'-- 3
_4
17
16
15
14
5
6
13
12
7
f:
NOTES,
R
R
= 500
.! 10%, %W
VIN = 6.3V RMS 60 CYCLE
VIN = 6.3V RMS 60 CYCLE
•
HM-0410
II
HM-6312
Vee
10
17
Vee
3
16
11
4
15
111
12
5
14
110
13
6
13
19
14
7
12
la
15
a
11
17
9
10
16
NOTES:
= 500
"::"
.±10%, %W
VIN
11
10
NOTES,
= 500
±10%, Y:tW
R
-
= 6.3V
RMS 60 CYCLE
5-41
112
I
II
HD-6431
Voo
Voo
Voo
•
HD-6432
Voo
10
A A A
12
f,.A
R
A A
R
A A
118
R R
A
NOTES:
R1 = 820,Q, %W,.± 10%
R2 =910n,14W,'± 10%
NOTES:
R ~ 820n
•
HD-6440
HD-6433
Voo
Voo
R2
Rl
* -ALL,OUTPUTS ARE
Rl
2.2Kn
• TERMINATED WITH
THIS LOAD
2.2KP.
Rl
Rl
• OUTPUTS
NOTES:
R1 = S20n, %W, ±.10%
R2 =910n, 14W,:!: 10%
1111
HD-6600
HM-6501,6551
14
+12V
+6V
(14)
NC
NC
12
(2~ c:::!,13)
R
(S.
13
It
R
(12)
16
(11) Vcel
'1
(5){;J C(i.'O)
C
GND
(6)
(9
(7)
(8)
18
AI
NC
A3
A2
AI
AD
As
As
47
7
GNo 8
Dii 9
00,
10
A2
Rl
01 2 11
R2
NOTES:
NOTES:
R=39nlW
c = .1 mfd 20wvdc
All Rl "" 2k 1,4W
AIIR2=lk)4W
5-42
II
HM-6503, 6504
II
HM-650a
Voo
2
17
3
16
10
4
15
12
5
14
13
S
13
14
12
8
11
9
10
IS
Rl
16
ce
AO
A,
A2
4
13
A3
12
A4
11
Ag
I"
As
A7
As
10
DO
110
19
la
R2
GNO
NOTES:
Voo
~
5.5V
a
9
AS
NOTES:
17
R1=1.Skrl%W
R2=lkH%W
-:-
Static burn In circuit
II
HM-6511
II
HM-6512
VOO
VOO
CS
CS
STR
2
17
RM
3
16
OXO
4
15
OX,
OX 2
5
6
14
OX3
7
12
OX4
a
11
oXs
9
10
OXs
13
OX"
OX,O
OXg
OXa
OX7
MSEL
17
STR
AOR
LOGIC LOW
16
OX"
OX,0
OXg
OXO
4
15
OX,
OX 2
5
14
6
13
OX3
7
12
OX4
8
11
OXe
'0
oXs
":"
OXe
OX7
":"
NOTES:
NOTES:
All resistors are 47k,Q.
All resistors are 47k!l.
%W,± 10%
~W,±'10%
iii
HM-6513,6514
II
HM-6S1a
Vee -S.5V
VOO
2
17
3
16
4
15
5
14
Is
6
13
16
7
12
a
9
13
I.
Rl
17
An
Al
10
-
As
12
NOTES:
Voo = 5.SV
R1=1.SkH%W
R2 = 1.0krl%W
5-43
10
As
NOTES:
Static burn in circuit
11
13
GND 9
11
10
112
As 111
A7
1,0
As 19
"
A3
11
01
WE
Ag
A2
DO
R2
16
15
la
II
HM-6533
19
II
HM-6543
19
VeeS.SV
In
112
113
114
Vee
lio
13
110
14
IS
111
3
112
4
21
13
20
19
15
14
S
16
5
18
16
6
17
6
17
17
11
9
10
11
17
16
IS
14
13
12
11
7
16
la
10
8
15
10
'15
'16
12
9
14
113
10
13
11
12
114
12
la
-=
-:
NOTES:
R
II
HM-6561
= 10K, %W
II
HM-65~2,
13
f3
12
f2
17
11
16
fO
15
f5
14
"1
10
I.
i.
'6
;7
R/W-
'a
csp
'ose
1/0 4
Rl
1/03
R2
1/02
R3
1/01
R4
01104
01/0~
13
A7
17
GNO
~
12
11
01/02
01/01
":"
NOTES:
AI, 2, 3, 4
NOTES:
= 10kn %W
I II
Rl, 2, 3, 4
HM-6611
= 10kn %W
II
HD-64.95
Voo
''s"
R
Voo
·R
R
'5
"0
'4
f,
f9
f,O
fl1
R
R
R
.R
GNO
R
.".
~
NOTES:
R ~ 820H. %W. ~ 10%
5-44
R
•
HD-7602/03,76LS03
II
HM-1024, 7610/11, 7620/21, 7644
HM-7610A/11A, 7620A/21A, 7644A
+S.6V
+.OV,
"
'S
02
IS
03
14
04
13
Os
NOTES:
A3
14
07
10
GND
TA
16
IS
14
t.l
+3°
_2°C
13
AI
Ao
R
= 300n %W
12
fO
=
11
50kHz
13
"
t2
" "
"
'7
cs
"
"R
As
,."
't
7
GND 8
5%
II
HM-7642/43
16
As
AS
IS
A4
14
A3
A2
13
10
As
AS
17
A4
16
A3
15
~
14
11
15
12
12
1,0
11
•
NOTES:
10
AS
A.
0,
'="
III
fg
R
02
R
03
R
04
R
Cs2
III
NOTES:
= 300n \TA curve). At this time many.chemical bonds are, broken and
re-formed as atomi!; rearrangements a,ccur and the glass assumes a morehi'!lhly~ordered
lattice network. Ttleseeyents, Vl(hich oc~ur just .atthEu:ritical time the h~rmeticsea.i is
being formed, free water molecules originally bound in the glass. These molecules evolve
and many oH:hem are then trapped within the pacKage cavity; Because of this process,
packages'sealed, withdeiiitrifying glass will alWays tend to have, die cavities with higher
.
•.,:,.
,
moisture'contents.
I
Still, another c~ntributing factor, tho~gh p~ssibiY()f second7'o~der importance, i~the
greater potential for water desorptlo,n frolT! dl!Vitrifying glass during the, operating lifetime
of the part,: In contrast, thealumino~ilic;ate component,of the vitreous glass in this study
imparts a' contiri"uing dryness property, which reduces the tendency, to evolve moisture
with time ... JhiseHect ,Is suggested bY the activatio~ enerQY for water'deso~ption from
borosilicate and aluminosilicate glasses, which has been reported as 21and 49 kcal/gram-;,
mole, respectively. 18
,R~liability
Qualification'ofVitreous"Glass-Sealed Cerdips'
. Package qualTfication ~peratrng life 't~ts werecohc:luctedfor~Weous Cerdil:1sinac;:c.ordance lIvithMethod 5005.3 of IVII L~STD-883. Low power diSSipation circl!ii types:sy;ch
as CMOS digital devices which operate with minimal chip temperature rise,'were assembled
in vitreous glass Cerdips. These were placed under 10-15V reverse bias at ~ 25 0 C. Low
ambient operating temperatures allow condensation of cavity moisture. and electrical
bias may then initiate corrosion of thin film met!lllization rendering the device nonfunctional. Table 2 shows that 1373 devices operated at 250C or OOC for a total of
4.531M device hours with zero failures. Delidding and visual examination ofthe packages
as they completed life test showed no corrosion eff~ts whatever on any of the devices.
Table 2.
Vitreous Sealing Glass
Applied Stren
A. Static Operating
Life@ Vdd =10
to 15V@250 C
Ambient
B.
Static Operating,
Life@Vdd =10
to 15V@OoC
No. of
Devices
DeviceHours
No.of
Failures
1313
4.447M
0
(See
Note 1)
6()
84.0K
0
(See
Note,1 )
Note 1 - Resulting Failure Rate: 0.02%/1000 Hours @ 60% Confidence
Identical device types were also assembled in a specific devitrifying glass package. known
to have considerable moisture in the cavity. and these were then life-tested under the
same conditions,. Table 3 shows that 451) of these devices operated 125.5K device hours
at 250C experienced 79 corrosion-related failures. The failures were verified by visual
examination. This package/gla~' structure was never qualified for use on deliverable
product.
' ,
Table 3.
Devitrifying Sealing Glass
Applied Stress
Static Operating Life
@ Vdd = 10-15 Volts
@ 250 C Ambient
(See Note 21
No. of.
Devices
DeviceHours
No. of
Failures
455
125.5K
79
(See
Notll11
Note 1 - Resulting Failure Rate: 65%/1000 Hours@ 60% Confidence
Note 2 - Low Ambient Temp. to Enhance Dawpoint Stimulat,ion
Teble 4 shows freeze-out test results conducted on 500-600mW Bipolar PROMs IIssembled
with vitreous gla$5. The devices were power~cycleq at low temperatures for a total of
385.1 K d~ice hours with no corrosion-related failures observed.
It must be emphasized that some devitrifying glasses. although possessingcBvity ambients
with more than 500ppmv moisture. do not necessarily induce corrosion failure. For
example. Tab'le 5 illustrates the results of freeze-out testing of PROM type circuits in a
devitrifying glass package. For this particular 74 package group zero failures occurred.
As the moisture distribution data of Figure 7 implies. a significant percentag!!! of these
packages are dry enough for corrosion to be avoided. Obviously. however. II drier package
is preferred for overall reliilbiliW considerations.
Extensive package environmental-related physical parameter testing of vitreous Cerdips
via MI L-STD-883 testing scheme resulted in zero failures for all tests applied as shown
in Table 6.
'
,
,
6-7
Table 4.
· Freeze-Out.Test Res~'lts of Bipoiar(600-BOOmW) PROMS
.'
. . , '.' .' ' '. Vitrepus Glass
'.' ' "
' "
'.
·
.
..
.
MolYr
Ambient
Temp.
4/76
6/76
11/76
3/77
3/7.7
6/77
6/77
7/77
9/77
10/77
10/77
"
11/77
-30C
-30C
-20C ..
-25C
-20C
-20C
-20C
-20C
-40C
-55e
-40C
-30C
·
i
Total
'.'
'
..
.:-
:1::
'"0 4
W
Vitreous Glass
(.)
:>'"
2
200
100
200
300
40
500
600 700
Temperature,oC (Chromel/Alumel)
400 600 800
Temperature,oC
FIGURE 2 - Differential Thermal Analysis
FIGURE 1 - Sealing Glass Viscosities
1----------------,
,-_..1
\,
I
',
500
\
\
I
'\ I
\', I
I
I
- - - Vitreous Glass
------- Devitrifying Glass
T
5
Minutes
10
FIGURE 3 - Nominal Seal Furnace Profiles'
r,::------:l
I
I
1 BellowsActivated I
~ I
Package I
~ I Opening
Device
L ___ _
~1
..+----.....----......
;I
all
I
(1)1
II
I
L_,",-
FIGURE 4 - Mass Spectrometer
6-10
15
0.8.LG=~~~~=;--1
0.7
0.6
~0.5
~ 0.4
~
0.3
~0.2
0.1
O~~~------~~
-20 -40
100
FIGURE 5 - Surface Conductivity Vehicle
60
+60
+50
+140
+40
+100
+30
+20
+10
-10
w
-20
:IE
:::l
...J
g
>
CD
ls'
,..:
z
:IE
. - ..
.. !S
~
it
zw
Z
a:
8w
a:
:::l
-30
-50.
Ii;
S
:IE
20
15
:::
ffi
+20
+10
-40
-10
-70
-80
.u.
0
50
Z
~
~
a:
~
w
40
w
a:
:::l
iii
w
1.5
...
a:
0
760
600
500
400
-110
~
300
~ 250
~
-120
200
150
-130
100
-140
75
-150
0.1
50
NOMOGRAPH FOR DEWPOINTS & PPM AS A FUNCTION OF P
FIGURE 6
6-11
if
....+
:!
«•
i!
30
-100
-100
(!>
100
90
80
70
60
e
-70
-90
200
10
J
-10
-20
300
%
-90
-60
400
+90
u.
~
w
-10
0
1000
900
900
700
600
500
30
+60
+50
+40
+30
-50
u.
40
+120
-30
-40
50·
20
14.7
10
9
8
7
8
«
if
W-
a:
:::l
iii
w
...a:
I
80
70
"C
N=42
Mean Oewpoint=-6oC
(I)
60
t:
(I)
~
'"
.1::
C
:;)
...
0
~
. A= <200
8=200-500
C=500-1,OOO
0= 1,000'-2,000
E=2,OOO-4,OOO
F=4,OOO-6,OOO
IU _·O.IJ'UU--C ,000
,000-10,000
1= >10,000
50
40
30
20
1 Unit
Moisture Content, ppmv
FIGURE 7 - Oevitrifying Sealing Glass
N=65
Mean Oewpoint=-37oC
A= <200
8=200-500
C=500-1,OOO
0=1,000-2,000
E=2,OOO-4,OOO
F=4,OOO-6,OOO
G=6,OOO-8;000
H=8,OOO-10,OOO
1=>10,000
o
~
1 Un
G H
Moisture Content, ppmv
FIGURE 8 - Vitreous Sealing Glass
N=21
Mean Oewpoint=-38oC
I
o
~
FIG U R E 9 - Metal-Seal Packages
6-12
Selection Guide
1*
PRODUCT
HM-Ol04
HM-0168
HM-0186
HM-0198
HM-0410
HM':'6312
HM-6388 (preliminary)
HM-6389 (Preliminary)
HD-6431
HD-6432
HD-64:33
HD-6440
HD-6495
HD-6600
HM-6501
HM~6503
HM-6504 t
HM-6508
HM-6512
HM:"6513
HM-6514 t
HM-6518 t
HM-6533
HM-6543
HM-6551
HM-6561 t
HM-6562
HM-6611
HM-6661
JAN-0512
HM-7602
HM-7603
HM-76LS03
HM-7608
HM-7610
HM-7610A
HM-7611
HM-7611A
HM-7616
HM-7620
HM-7620A
HM-7621
HM-7621A
HM-7625R
HM-7629
HM-7640
HM-7640A
HM-7640AR
*
CERDIP
3*
EPOXY
CERPACK
3D
9H
9H
9H
8C
9H
8C
3G
3D
3G
3D
3G
88
'8C
S8
·8C
88
3E
3D
3D
3G
3D
3D
3D
3D
3E
3E
3E
3D
3G
BE
8H
8H
88
8C
8C
8C
8C
8K
8K
8E
8C
88
88
8C
3G
3G
3G
3F
3G
3G
3G
3G
88
88
88
8F
88
88
88
88
8L
88
88
88
88
8F
8F
SF
8F
8F
4U
4U
4U
4U
4G
42
4N
42
4N
42
4D
4M
58
58
4P
4N
58
58
4N
4M
4M
4M
4N
4P
5C
4N
4K
42
42
42
4K
42
42
42
42
5A
42
42
42
42
4K
4K
4K
4K
4K
9*
3G
3G
3G
3G
3F
3F
3F
3F
3F
These package numbers to be used in product ordering. Other numbers shown in Selection Guide and drawings are
internal package numbers.
t Available in Leadless Carriers. See page 6-19.
6-13
Selection Guide
(Continued)
"RODUCT
HM-7641
HM-7641AR
HM-7642
HM-7642A
HM-7642P
HM-7643
HM-7643A
HM-7643P
HM-,7644
HM-7.644A
HM-7647R
HM-7648
HM-7649
HM-7.680
HM-}680R
HM-7680P
HM-7680RP
HM-7681
HM-7681R
HM-7681P
HM-7681RP
HM-7683
HM-7684
HM-7684P
HM-768S
HM-768SP
HM-7686
HM-7686R
HM-7686P
HM-7686RP
HM-7687
HM-7687R
HM-7687P
HM-7687RP
HM-76160
HM-76161
I
..
1"
3"
g"
CERDIP
EPOXY
CERPACK
4K
4K
4N
4N
4N
4N
4N
4N
4P
4P
4K
4L
4L
4K
4K
4K
4K
4K
4K
4K
4K
4L
SE
SE
SE
SE
4L
4L
4L
4L
4L
4L
4L
4L
SA
SA
3F
3F
3D
3D
3D
3D
3D
3D
3K
3K
3F
3N
3N
3F
3F
3F
3F
·3F
3F
3F
3F
8F
8F
8C
8C
8C
8C
8C
8C
8C
8C
8F
8D
8D
SF
8F
8F
8F
8F
8F
8F
8F
8J
8H
8t-!
8H
8H
8J
8J
8J
8J
8J
8J
8J
8J
8L
8L
...
t Available in Leadless Carriers. See page 6-19.
NOTE FOR PACKAGE DRAWINGS ON FOLLOWING PAGES:
1.
2.
3.
All dimensions in inches; millimeters are shown in parentheses.
All dimensions ± .010 (± 0.2Smm) unless otherwise shown.
Internal package codes ate shown in black squares.
..
Package Dimensions
18 LEAD EPOXY
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L. 0251D.641REF.
on± 002 I
~['05~
,;~;'
I
.025 (0.841 TYP::::J
",,~--I
MAX
Q
D
L
Leadless Carriers
Harris Semiconductor is offering four CMOS RAMs in 18 pin leadless carriers. Electrical specifications for
these parts are identical to the equivalent product in the standard DIP package. Mechanical specifications
for the 18 pin lead less carriers are shown below. For availability and additional information contact your
nearest Harris Representative or Harris Sales Office.
All electrical grades of the following product types are available as stock items:
HM4-5618
HM4-6561
HM4-6504
HM4-6514
1024 x 1
256 x 4
4096 x 1
1024 x 4
CMOS
CMOS
CMOS
CMOS
RAM
RAM
RAM
RAM
18 Pin
18 Pin
18 Pin
18 Pin
The Package Code for Leadless Carriers is 4.
r
.285±.010
(7.24.t.25)
r--
I
I
.350±.010
(8.89±.251
~~
SIDE VIEW
TOP VIEW
BOTTOM VIEW
6-19
.045±.Dl0
(1.14.t .25)
Dice Ordering Information
GENERAL INFORMATION
Harris Memory Products afe'aY~ilaPle in'chiPfO~tn~tk~n~hYbrid micro circuit designer.
The standard chips are DeelectricaUY;,,~@!!itl!d,at,-It~§9,Gto the data sheet limits for the
commercial device and are;1 00%"iStlllnyJnsp~tedtoMrL:"STD-883, Method 2010, Cond:ition B criteria. Packagingforshipment~<)nsis~~,gfwatfle;pack carriers plus an anti-static
cushioning strip for extra Pfotection;:,;'
.
Th,e hybrid industry hasra~idlyt>ec!Jm~ ;m~fe.diV~?ifiedand stringent in its ,requirements
for integrated circuits. To meet these,ciernandsH~rriS'~has several options additional to
standard chip processing availableuponreq!-!I!st~t.e)ctta cost. For more information consult
,".
the nearest Harris Sales Office.
CHIP ORDERING INFORMATION
Standard and special chip sales are direct factory order only. The minimum order on aU
sales is $250.00 per line item. Contact the local Harris Sales Office for pricing and delivery
on special chip requirements.
MECHANICAL INFORMATION
Dimensions:
All chip dimensions nominal with a tolerance of ±.003", Maximum chip
thickness is.012".
",',
Bonding Pads:
Minimum bonding pad size is .004" x .004:' unless, otherwise specified.
PRODUCT CODE EXAMPLE
6508
HMO
PREFlX,J
T
6
MODEL NUMBER
H (Harris)
FAMILV:---...J
M,: Memory
D= Digital
TEMPERATURE:
6 = 250 C Probe *
0= Chip Form
·Contact Harris for
availability of -2
(-550 C to +125 0 C)
dice.
I
NOTE: All Harris Digital Memory Products have biased ,substrates. Persons wishing to ,utilize product
in dice form should contact the Harris factory for specific product information regarding proper
connection of the substrate.
7-2
Dice Geometry Index
Product
HD-6431
HD:...6433
HP-6495
HD-6432
HD-6440
HD-6600.
HM:"0104,
.HM-0168'
HM-0186
HM-0198
HM:-0410
HM:...6312
"HM-6501
HM-6551
HM-6503
HM-6504
HM-6508
. HM-6512
HM"-6513
HM-6514
HM-6518
HM-6561
HM-6562
HM:-6611
HM-6661
HM-'7602
HM-7603
HM-'76LS03
HM:-7608..
. ...
. HM-7680/80R/80P/80RP
HM-7681/81 R/81P/81 RP
HM-7610
.
HM-7611
HM-7610A
HM-7611A
HM-7620
HM-7621
HM-7620A
HM-7621A
Product
Drawing No.
HM-7625R
HM-7647R
HM-7648
HM-7649
HM-7629
HM-7640
HM-7641'
HM-7642
HM-7643
HM-7644
HM-7640A
HM-7640AR
HM-7641A
HM-7641AR
HM-7642A'
HM-7642P
HM-7643A
HM-7643A
HM-7643P
HM-7616
HM-76160
HM-76161
1
1.
1
2
3
"5
6
7
8
9
10
11
11
12
12
13
14
15
15
16
17
Drawing No ..
27
27
'21
27
28
28
28
29
29
29
·.30
30
30
30
31
31
31
31
31
32
32
32
18
19
20
21
21
21
22
22
22
23
23
24
24
25
25
26
26
J
7-3
a
II
HO-6431, HO-6433, HO-6495
HO-6432
107
MILS
1 - - - - - - - 9 4 MILS - - - - - - I
•
1 - - - - - - - 9 4 MILS -----'-~-_l
II
HO-6440
HO-6600
PIN
PIN
TWO
I
r - - - 62 MILS - - - - - j
1------77 MILS - - - - I
7-4
•
T
HM-0168
HM-0104
ONE
PIN__
:IIUIIUIIIIUIIU:
•
•
HM-0186
,
53
=
r-- =T
41
•
MILS--1
HM-0198
, •• •.• T
•
HM-0410
III
HM-6501, HM-6551
.55555555"::11
PIN . WS5555555::' 41'
ONE"'-....4g:g99999-=-MILS
.-.&999999-;. I,
• • • • • '-L
I
III
I
72 MILS
HM-6312
PIN
•
~.
~' '.~.'
r j.~'.i,.]
iJ;.'~ ~~
U[~
r;'
• T'~II"'rT'~Jr";I~
'•• ,'k'~W~~j'''~
..... ' .,....
•'.cL. ".. .. 'r.j...4. .','I. "'
•.. .J.,...I. ."•..f. . •.. ' r1... . t..•.,." . . .,.1c!1'
......'Ii\'
...•.. . . .'. nii
.........
rn
.....
, '
~".~ j'1.~,-r. J;~i.I-.i,.~ '.! i.:~I- ;~.i',I.·, ). ~."'!"'. i!.'i."I'~., i."'-I',.' ,{~.,i: ', I: ~lf 'i!till,.~" '~.1;
•. '•. '•. ,I""
i.r,•. .
1::[1'
,",""
,I" ij,
;'
II
~
r or ',-
,
11111"'
:• . "'I":!'I:",!,I!"I
•.
. . I.• '. '11.1. •. II',
.'1:. :1:""1,,·1
'.'1 ' '1'1 i"I":'
•.,·'I·i•. i.'i;;:'['
•. I ,II
,.
,: "i",'
,,:11'1
'1:",,,:,,,
I!II ,II i!.'iill' i"i:I'!'lilil'll I,. ""llli!II!!
!',i"'II'"',I",
',I"', "I ,.".1·:! :,:,'
'!I, II"i'I""
rl; 1 '11,: I I, 'III
I,,"~
,I!
1
I ;'1 I'
';';:1 ":
: , ' 'I'
;
1 I '." ,.~
. '",,'
,,,
'II'i l·'.','I',".',II' .• II······
•. "
'.• '·.:'.'•I"I'I'Iii!)::!
.I'""'1'
i l•. :., "'," .• '.!,I'.i'.'III"
111.·.·.1 .,1,:1
'.1,:"'I'
. 1::." '. ".1 ., .'."e,:,.
I 'i:ii;: 11 .iii,'I'
,!1[IIiI'!"I.',
r"jlf I,I.~
1.•i,'ii,:i~:
";::;: :J;:
,I.iiil:'IIII.!IIIIII'!I'1
i.il:I.I'.·"I'i.".'II. ,. ,.111. 'i ··" I' III 0 ..
II I:,: i ,'Ii: ::::.1:1:1::::' 1;::'>11:; ::::1 iil'l :1 1ll,::1 i: [In j:W
I
'1'li.1 "1,.1!II11,.,:,.,.,,.,'
1::,.,.".1.'ii ,.1,: i,,>
'.','.' ,,,.,,,,
'I"'..' 'i'l:".':.'1l·1:. !II
"'" 1"I'li
,I "I.1.".::1
!.!." !.il:,
i:i:, :,I"l
'.'.:."'."."
'1"""'
"""," ,. '1'1"'"
iii'; •
~ 'I .. ,..''''''
:1 11 ,!" ""HI'I'I"'I
'1'1"'" -'" ""'1:
"I' :,. .,,',
II:' 'I""' II""
",-c .• J),t,
:: ':';YI!!:-:
~:_1;
'.'•. "I. ,:"":
' , ,1:-: 'i'i~'II"
"'I!1:;:I:
i "1."1i I:'i!':
il. I'!I!;:.".'••.;:'
','!'!::,
~C:-.:''..-"•
"I;-j.
.: I 'IIIIII':!I::
11'I1"""::'
I::.:,'
,:' ,,"1'1'
".: ' : ' . " ' : ' i "
" L:,!" 1:., I': ... '.'.;'; '. I ~'!~
"':""""':~"'I>'~
' ...•.
1,.:.,".,;.1.
~,
II.~~
I
. J~~.~
1111!I"~1
I
J
.,
'" " '"
I
'-~'-:-:'-j~I;~'-'-,--::"'{{i, ' , j :
,~c==c=c~:.O
8·1~li~1}:ii[J=-~'·""1"":""-·~·:~1. i"il' r¥
i4III,
""~\\.llr,.i(rr' '''~iLl.'liJr'' ""","jI~'''o-1l1''''
Lii·:·,:'I'!.'GT;',lm~J'::l..J
;',"';'lI"c'1-I';"f,JJj~,"1-I~
1-------132
7-5
MILS - - - - ;
HM-6503,HM...6504'·· .
1 - - - - - - 1 5 6 MILS
II
-~-,----;
HM-6512
•
I
1 - - - - - - 1 3 3 MILS -.-'---....,..;..--~
7-6
HM-6513, HM-6514
PIN ONE
II
III
HM;.6518
HM-6561
1---.,...---'--13.2 MI LS - - - - - - 1
III
II
HM-6562
HM-6611
I
7-7
II
HM-6661
I:iM-7608. HM-7680/80RI80P/80RP.
HM-7681/81 R/81P181 RP
I,
II
•
HM.,.7602. HM-7603. HM-76LS03
HM-7610. HM-7611
III
•
HM-7610A, HM-7611A
HM-7620, HM-7621
1----107 MILS - - - - I
II
HM;.7620A,HM-7621A.
HM-7625R, HM-7647R, HM-7648,
HM-7649
1------98 MILS - - - - - I
1 - - - - - - 1 3 5 MILS----I
7.;.9
III
HM-7629, HM ...7640, HM.:..7641
II
HM-7642,
HM~7643, HM-7644
PIN
HM-7640A,HM-7640AR, H!VI ...7641A,
HM-7641AR
III
7-10
HM-7642A, HM-7642P, HM-7643A,
HM-7643P
II
HM-7.1S, HM-76160, HM-76161
PIN
ONE
1-------207 MILS---------;
I
7-11
OEM Sales Offices.
EASTERN REGION
535 Broadhollow Road
Melville. L.I .• N.Y. 11746
(516)249-4500
Suite 301
177 Worcester Street
Wellesley Hills. Mass. 02181
(617) 237-54;30
Suite 325
650 E. Swedesford Road
Wayne. Penn. 19087
(215) 687-6680
FRANCE
Suite 300
625 Ell is Street
Mountain View. Calif. 94043
(415) 964-7443
HARRIS SEMICONDUCTOR
4 Ave. Charl.es.de Gaulle
F-78150 Le Chesnay
Tel: 955-45-20
TX 842 696 514 F
HOME OFFICE
GERMANY
P.O. Box 883
Melbourne. Flo 32901
(305) 724-7000
TVVX-51 0-959-6259
HARRIS GmbH
Harris SemiconduCtor Div.
Einsteinstrasse127.
D-BOOO Munchen BO.W. Germany
Suite 115
2020 West McNab Road
Ft. Lauderdale. Flo 33309
(305) 971-3200
EUROPEAN DISTRIBUTORS
AUSTRIA
CENTRAL REGION
Suite 100
4972 Northcutt Place
Dayton. Ohio 45414
(513) 226-0636
Suite 508
2355 S. Arlington Hts. Rd.
S Arlington Hts .• III. 60005
(312) 437-4712
Suite 7G
777 S. Central Expressway
Richardson. Texas 75080
(214) 231-9031
WESTERN REGION
2016 Quail Street
Newport Bch .• Calif. 92660
(714) 540-2176
International Sales
Europe
OEM SALES
BELGIUM
HARRIS SEMICONDUCTOR. INC.
53 Blvd. de Waterloo. Bte 5
B-l000 Brussels. Belgium
Tel: (02) 511 0824
TX 26382
ENGLAND
HARRIS SYSTEMS LTD.
Harris Semiconductor Div.
P.O. Box 27. 145 Farnham Rd.
Slough SL 1 4XD
Tel: (Slough) 34666
TX 848174 Harris G
8-1
KONTRON GmbH
Ameigasse 49
A-1140 Vienna
Tel: (222) 945646
TX 11699
BELGIUM
BETEAS.A.
15 Av. Geo Bernier
B-l050 Brussels
Tel: (02) 6499900
TX 23188
DENMARK
DITZ SCHWEITZER A. S.
Vallensbaekvej 41
DK-2600 Glostrup
Tel: (02) 453044
TX 33257
FAR EAST DISTRIBUTORS
EUROPEAN DISTRIBUTORS
(Continued)
NORWAY
FINLAND
@~e.~~~11l~75
FINN METRIC OY
Ahertajantie 60
SF-02101 Tapiola PI 6
Tel: 460844
TX 122018
FRANCE
Al.MEX
48Rull deL'Aubepine
F-92160 Antony
Tel:. 666-21~12
TX 250067
A2M
40 Rue des Tilleuls
F-92100 Boulogne
Tel: (1) 603 6640
TX 200491
SPETELEC
Tour Europa
Belle Epine,Cidex Alii
F-94532 Rungis
Tel: 6865665
TX 25.801
GERMANY
ALFRED NEYE-ENATECHNICK GmbH
Schillemrasse.l4
0-2085 Quickborn b. Hamburg
. TI!I: (04106) 612/1
TX 0213590
KONTRON ELEKTRONIK GmbH
Breslauer Str. 2
0,..8057 Echingnear Munich
Tel: (89) 31 88-1 .
TX 0522122
ITALY
ERIE ELETTRON.ICA SPA
Via Melchiorre Gioia 66
1-20125 Milano
Tel: (2)6884833/4/5
TX 36385
LASI ELETTRONICA SPA
V. Le Lombar~ia, 6
I - Cinisello Balsamo - Milano
Tel: (02) 9273.578
TX 37612
NETHERLANDS
TECHMATIONELECTRONICS B.V.
Gebouw 106, P.O. Box 7713
1117 ZL - Schiphol,..Oost
NL - Amsterdam· .
Tel: (020) 470141
TX 18612
EG·A,·A/s y
;,
··P.~•. f3()x 53iOek~rn
.N..,Oslo5
..tel: (02)~21900
. i:TX11265
AUSTRALIA
CEMA (DISTRIB.) PTY. LTD.
21 ChandosStreet
Crows Nest, N.S.W. 2065
Tel: 439~4655
TX A22846
SPAIN & PORTUGAL
, ········INSTRUr0ENTOS EU;CTRONICOS
DEPRECISION .
~.IcaldeSainz·deBaranda33
MliQrid9,.Spain
Tel:.2'74H)07
TX 22961
SWEDEN
AB ELEKTROFLEX
Box 7068
S-17207 Sundbyberg
Tel: (08) 289290
TX 17644
SWITZERLAND
STOLZA. G.
Bellikonerstr.218
CH-8968 Mutschellen
Tel: (057) 54655
TX 54070
UNITED .KINGDOM & IRELAND
APEX LTD.
396 Bath Road
Slough, Berks SL 1 6JE, England
Tel: (06286) 63741
TX 848519
CRELLON ELECTRONICS LTD.
380 Bath Road
Slough, Berks SL 1 6JE, England
Tel" Burnham (06286)4434
TX 847571
JAPAN
HAKUTO COMPANY,.L TO.
ForeignDivision
c.p.a. Box 25
Tokyo, 100-91
Tel: (03) 503-3711
TXJ22912
MITSUBISHI CORPORATION
6-3, Marunouchi .2-Chome.
Chiyoda-Ku
Tokyo, 100-91
Tel: (03) 210-3023
TX J 22222
India
AMERICAN COMPONENTS INC.
For Sujata Sales and Exports Ltd.
1601 Civic Center Drive
Santa Clara, Calif. 95050U.S.A.
Tel: (408) 249-42.12
TX ELCOMP
South America
ROW INC.
3421 Lariat Drive
Shingle Springs, CA 95682
Tel: (916) 677-2827
MEMEC LTD. ;.
Thame Park I nd. Estate
Thame, Oxon OX9 3RS, England
Tel: (084421) 3146
TX 837508
far East
OEM SALES
JAPAN.
HARRIS SEMICONDUCTOR. INC.
Far East Branch
Suzuya Bldg,; 2F
8-1 Shinsen-Cho
Shibuya-Ku, Tokyo 150
Tel: (03)476 - 5581
TX J 26525
8-2
,I
I.;
Harris Technology: Your competitive edge.
Innovative technology from Harris can be translated into technical advantages for your product
or a more competitive and cost effective means of solving your customer's needs. Over the
years Harris has pioneered in developing sophisticated processes such as dielectric isolation (0 II,
and is known for expertise in thin-film technology, dielectrically isolated high voltage CMOS,
and its unique self-aligned silicon gate CMOS process which yields ICs with superior speed/
power/density characteristics.
These state-of-the-art processes have spawned a wide family of analog and digital devices
which offer designers higher performance and raise the level of system reliability. Advanced
linear products include the first monolithic 12-bit D/A converter, high performance operational
amplifiers, and the- most complete family of CMOS and bipolar analog switches. Digital products include a complete range of bipolar PROMs from 256 to 8K bits, CMOS memories, and a
CMOS 12-bit microprocessor.
Let Harris technology go to work for you and supply that elusive competitive edge ... that extra
something to help you meet the challenge of competition and succeed.
Harris offers:
ANALOG
DIGITAL
Operational Amplifiers
auad Comparators
Switches
Multiplexers
Sample and Hold
D/A Converters
A/D Converters
Precision Voltage References
Delta Modulators (CVSD)
Keyboard Encoders
line Drivers/Receivers
Bipolar PROMs
CMOS RAMs, ROMs, PROMs
Microprocessors
CMOS LSI Logic
Digital Data Book Registration
Important:
Harris has a number of exciting new digital products in development.
Every Data Book holder should mail one of these cards immediately
to receive new product data as soon as available.
Registration Card
o
Add my name to mailing list for future Harris Digital Product Data Sheets and Application Notes.
My application/end product is:
I plan to use the following digital I.C.'s:
Types
0
Bipolar PROM
0
CMOS RAM
0
CMOS PROM, ROM
0
CMOS /J.P, Peripiferal
0
CMOS Communications Ckts (UART,
BRG, 1553 Ckt)
0
Diode Matrix
o
I need a new or improved digital I.C. with the following characteristics:
Qty!Yr.
Name _ _ _ _ _ _ _ _ _ _ _ _ _ _ Title _ _ _ _ _ _ _ _ _ _ _ __
Company_ _ _ _ _ _ _ _ _ _ _ _ _ Mail Station _ _ _ _ _ _ _ _ __
Address __________________________________________________
City______________ State _________ Zip _ _ _ __
FIRST CLASS
PERMIT NO. 10
SEC. 510 P.L. & R.
MElB.OURNE, FLA.
BUS
N
E S S
NO POSTAGE STAMP NECESSARY
REP
FIRST CLASS POSTAGE WILL BE PAID BY
m
L
Y
M A
I
L
IF MAILED IN THE UNITED STATES
HARRIS
SEMICONDUCTOR
PROeUCTS DIVISION
BOX 883
MELBOURNE, FLORIDA 32901
HA.RRIS
SEMICONDUCTOR
PROOUCTS DIVISION
A DIVISION OF HARRIS CORPORATION
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