1978_Intel_Component_Data_Catalog 1978 Intel Component Data Catalog
User Manual: 1978_Intel_Component_Data_Catalog
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\ote\®,.
component
Data
catalOg
1978
© lnlelC orporation 1976 , 1977. 1978
Price $3.00
Intel Corporation
3065 Bowers Avenue· Santa Clara, CA 95051
Telephone: (408) 987-8080
TWX: 910-338-0026· Telex: 34-6372
Numerical and
Functional Indexes
General Information
Random Access
Memory
Read Only Memory
Serial Memory
Memory Support
Telecom
Series 3000 Bipolar
Microprocessor
intel®
Component
Data
Catalog
1978
MCS-4/40™
Microprocessor
MCS-48™
Microcomputers
I·
™
I~
10
MCS-SO/S5
11
Microprocessors
Microcomputer
Support Systems
I
131
Military Products
141
Microprocessor
Peripherals
12
.
. .
I
FUNCTIONAL INDEX
GENERAL INFORMATION
Table of Contents
Ordering Information
Packaging Information
Standard Product Flow
Intel Technical Library
System Sales Offices
Component Sales Offices
PROGRAMMABLE READ ONLY MEMORIES/
READ ONLY MEMORIES
2-2
2-3
2-4
2-12
2-14
2-17
2-18
SELECTOR GUIDE
BIPOLAR CROSS REFERENCE
Custom Mask Programmable
1302
2048-Bit Static ROM
2K (256 x 8) UV Erasable PROM
1702A
2K (256 x 8) UV Erasable PROM
M1702A
(-55°C to +100°C)
2K UV Erasable Low Power PROM
1702AL
2K UV Erasable PROM
4702A
8K (IK x 8) ROM
2308/8308
2316A/4316A1
16K (2K x 8) ROM
8316A
16K (2K x 8) ROM
2316E
16K (2K x 8) ROM
M2316E
Low Power 16,384-Bit Mask
2316AL
Programmable ROM
32K (4K x 8) ROM
2332
64K (8K x 8) ROM
2364
8K Factory Programmable PROM
2608
16K Factory Programmable PROM
2616
2704
512 x 8 EPROM
2708/8708
8K and 4K UV Erasable PROM
8K UV Erasable PROM (-55°C to +100°C)
M2708
16K UV Erasable PROM
2716
16K UV Erasable PROM (-55°C to +100°C)
M2716
2732
32K UV Erasable PROM
8K Low Power Erasable PROM
2758
256 x 4 High Speed PROM
360113621
3602A 13622A
Family
2K High Speed PROM
3604A 13624A
4K High Speed PROM
Family
M3604AI
M3624A
4K High Speed PROM (-55°C to +125°C)
4K (IK x 4) PROM
3605/3625
8K Bipolar PROM
3608/3628
3621
See 3601.
3622A
See 3602A.
3624A
See 3604A.
M3624A
See M3604A.
3625
See 3605.
3628
See 3608.
4316A
See 2316A.
See 2308.
8308
8316A
See 2316A.
UV Erasable and Electrically
M8702A
Programmable 204B-Bit PROM
See 2708.
8708
UV Erasable and Electrically
M8708
Programmable 8096-Bit PROM
PROM AND ROM PROGRAMMING INSTRUCTIONS
RANDOM ACCESS MEMORIES
SELECTOR GUIDE
256 x I-Bit Static MOS RAM
1101A
1103
1024 x I-Bit Dynamic RAM
1103A
1024 x I-Bit Dynamic RAM
2101A18101A-4 256 x 4-Bit Static RAM
2102A/2102AL
8102A-4
lK x I-Bit Static RAM
M2102A-4
lK x I-Bit Static RAM
(-55°C to +125°C)
2104A
(S Version)
4096 x I-Bit Dynamic RAM
2104A Family
4096 x I-Bit Dynamic RAM
2104A
4096 x I-Bit Dynamic RAM
2107A
4096 x I-Bit Dynamic RAM
2107B
4096 x I-Bit Dynamic RAM
2107C Family
4096 x1-Bit Dynamic RAM
2108
8192 x I-Bit Dynamic RAM
2109 Family
8192 x I-Bit Dynamic RAM
2111A/8111A-4 256 x 4-Bit Static RAM
M2111A
256 x 4-Bit Fully Decoded Static
RAM (-55°C to +125°C)
2112A
256 x 4-Bit Static RAM
2114
1024 x 4-Bit Static RAM
M2114
1024 x 4-Bit Static RAM (-55°C to +125°C)
2115A12125A
Family
High Speed 1K x I-Bit Static RAM
M2115AI
High Speed lK x I-Bit Static RAM
M2125A Family (-55°C to +125°C)
2116 Family
16,384 x I-Bit Dynamic RAM
2117 Family
16,384 x I-Bit Dynamic RAM
2125A
See 2115A.
2141
4096 x I-Bit Static RAM
2142
1024 x 4-Bit Static RAM
M2142
1024 x 4-Bit Static RAM (-55°C to +125°C)
2147
4096 x I-Bit Static RAM
2185
1024 x 8-Bit Static RAM
3101/3101A
16 x 4-Bit High Speed RAM
3104
16-Bit Content Addressable Memory
5101 Family
256 x 4-Bit Static CMOS RAM
M5101
256 x 4-Bit Static CMOS RAM
(-55°C to +125°C)
81(ilA-4
See 2101A.
8102A-4
See 2102A.
M8102A-4
1024-Bit Fully Decoded Static RAM
8111A-4
Sea 2111A.
M8111A
256 x 4-Bit Fully Decoded Static RAM
3-2
3-4
3-12
3-26
3-30
3-34
3-36
3-44
3-52
3-60
3-65
3-73
3-85
3-89
3-94
3-98
3-99
3-104
3-109
3-117
3-99
3-129
3-133
3-137
3-138
3-144
3-145
3-149
3-153
3-157
3-26
3-30
4-2
4-4
4-5
4-9
4-11
4-14
4-18
4-22
4-25
4-28
4-29
4-30
4-31
4-34
4-38
4-41
4-44
4-49
4-50
4-51
4-55
4-58
4;-61
4-63
4-66
4-55
4-58
4-61
4-63
4-66
4-22
4-18
4-22
4-38
4-69
SERIAL MEMORY
SELECTOR GUIDE
Quad 256-Bit Dynamic Shift Register
1402A
3-85
"For specifications contact Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
1-3
5-2
114~
1404A
1405A
2401/2405
2416
2464
FUNCTIONAL INDEX
Dual 512-Bit Dynamic Shift Register
1024-Bit Dynamic Shift Register
Dynamic Recirculating Shift Register
2048/1024-Bit Dynamic Recirculating
Shift Reg isters
16K-Bit CCD Serial Memory
64K-Bit CCD Serial Memory
MCS-80/85™
8008 I 8008-1
8080A/8080A-l I
8080A-2
M8080A
5-3
5-7
8224
M8224
8801
8228/8238
MEMORY SUPPORT
SELECTOR GUIDE
3205/3404
Binary Decoder and 6-Bit Latch
3207A
Quad Bipolar-to-MOS Level
Shifter and Driver
3207A-l
Quad Bipolar-to-MOS Level
Shifter and Driver
3208A/3408A
Hex Sense Amplifier
3222
Refresh Controller
3232
Address Multiplexer and Refresh Counter
3242
Address Multiplexer and Refresh Counter
3245
Quad TTL-MOS Driver
3404
See 3205.
3408A
See 3208A.
5235
Quad TTL-MOS Driver
6-2
6-3
M8228
6-7
8085A
6-11
6-13
6-19
6-25
6-29
6-33
6-3
6-13
6-37
8085A-2
8155/8156
8185
8355
8755A
PCM CODEC u-Law
PCM CODEC A-Law
8041/8741
7-3
7-14
8205
8212/3212
M8212/M3212
821413214
M8214/M3214
821618226,
3216/3226
M8216/M3216
8251A
M8251A
8253/8253-5
8255A 18255A-5
M8255A
8257 I 8257-5
8259/8259-5
8271
8273
8275
8278
8279 I 8279-5
SERIES 3000 BIPOLAR MICROPROCESSORt
3001
3002
3003
3212
3214
3216
3226
Microprogram Control Unit
Central Processing Element
Look-Ahead Carry Generator
See 8212/3212.
See 8214/3214.
See 8216/3216.
Inverting Bidirectional Bus Driver
8-3
8-4
8-5
12-17
12-31
12-38
12-38
MCS-4/40TM MICROPROCESSORt
4040
4004
4003
4265
4269
4201A
4008/4009
4289
4002
4001
4308
Single Chip 4-Bit P-Channel
Microprocessor
Single-Chip 4-Bit P-Channel
Microprocessor
10-Bit Shift Register 10utput Expander
Programmable General Purpose
1/0 Device
Programmable Keyboard Display Device
Clock Generator
Standing Memory and 1/0 Interface Set
Standard Memory Interface
320-Bit RAM and 4-Bit Output Port
256 x 8 Mask Programmable ROM
1024 x 8 Mask Programmable ROM
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-14
8294
8741
Single Component 8-Bit Microcomputer
Single Component 8-Bit Microcomputer
Single Component 8-Bit Microcomputer
Single Component 8-Bit Microcomputer
MCS-48™ InputlOutput Expander
11-11
11-19
11-24
11-28
11-32
11-34
11-38
11-43
11-57
11-63
11-76
11-77
11-84
Universal Peripheral Interface 8-Bit
Microcomputer
High-Speed lOut of 8 Binary Decoder
8-Bit Input/Output Port
8-Bit Input/Output Port
Priority Interrupt Control Unit
Priority Interrupt Control Unit
4-Bit Parallel Bi-directional Bus Driver
4-Bit Parallel Bi-directional Bus Driver
Programmable Communication Interface
Programmable Communication Interface
Programmable Interface Timer
Programmable Peripheral Interface
Programmable Peripheral Interface
Programmable DMA Controller
Programmable Interrupt Controller
Programmable Floppy Disk Controller
Programmable Protocol Controller
Programmable CRT Controller
Programmable Keyboard Interface
Programmable Keyboard Display
Interface
Data Encryption Unit
See 8041/8741.
12-3
12-11
12-17
12-26
12-31
12-35
12-38
12-43
12-46
12-62
12-65
12-76
12-95
12-98
12-111
12-123
12-142
12-165
12-188
12-198
12-209
12-3
MICROCOMPUTER OEVELOPMENT SYSTEMS
INTELLEC® SERIES II
Model 210
Intellec® Series II Microcomputer
Development System
Model 220
Intellec® Series II Microcomputer
Development System
Model 230
Intellec® Series II Microcomputer
Development System
Expansion
Intellec® Series II Microcomputer
Chassis
Development System
MCS-48™
8021
8048/8748/8035
8748-4 I 8035-4
8049/8039
8243
11-5
PERIPHERALS
TElECOMM UNICA nONS
2910
2911
8-Bit Microprocessor
Single-Chip 8-Bit N-Channel
Microprocessor
Single-Chip 8-Bit N-Channel
Mi croprocesso r
Clock Generator and Driver for ~080A CPU
Clock Generator and Driver for 8080A CPU
Clock Generator Crystal for 8224/8080A
System Controller and Bus Driver for
8080A CPU
System Controller and Bus Driver for
M8080A CPU
Single-Chip 8-Bit N-Channel
Microprocessor
Single-Chip 8-Bit N-Channel
Microprocessor
2048-Bit Static MOS RAM with II 0
Ports and Timer
1024 x 8-Bit Static RAM for MCS-85148™
16,384-Bit ROM with 1/0 Ports
16,384-Bit EPROM with 1/0 Ports
10-4
10-10
10-18
10-23
10-28
'For specifications contact Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
tThese are partial specifications. For complete specifications contact Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
1-4
13-3
13-6
13-10
13-13
FUNCTIONAL INDEX
Enhancement Kit Intellec® Series II
Microcomputer Development System
Model 770
Printer Intellec® Series II
Microcomputer Development System
System
Intellec® Series II Microcomputer
Monitor
Development System
ROM Editor/
Intellec® Series II Microcomputer
Assembler
Development System
ISIS-II
Diskette Operating System
Microcomputer Development System
PUM-80
High Level Programming Language
Intellec® Resident Compiler
FORTRAN-80
8080/8085 ANS FORTRAN 77
Intellec® Resident Compiler
Diskette-Based Software Support
MCS-48'"
Package
Intellec® PROMPT-48'", MCS-48'" Microcomputer
Design Aid
Intellec® PROMPT-80/85'", 8080/8085
Microcomputer Design Aid
ICE-30'· 3001 MCU In-Circuit Emulator
ICE-41'" UPI-41'· In-Circuit Emulator
ICE-48'" MCS-48'· In-Circuit Emulator
MDS-EMI 8021 Emulator Board
ICE-80'· 8080 In-Circuit Emulator
ICE-85'" MCS-85'" In-Circuit Emulator
Insite'" User's Program Library
UPP-103 Universal PROM Programmer
Intellec® High-Speed Paper Tape Reader
SDK-85 MCS-85'" System Design Kit
MILITARY PRODUCTS MANUFACTURING FLOW
2K (256 x 8) UV Erasable PROM
M1702A
1024-Bit Fully Decoded Static RAM
M2102A-4
256 x 4-Bit Fully Decoded Static RAM
M2111A
1024 x 4-Bit Static RAM
M2114
M2115A/M2125A
High-Speed 1K x 1-Bit Static RAM
Family
1024 x 4-Bit Static RAM
M2142
M2316E
16K (2K x 8) ROM
8K (1K x 8) UV Erasable PROM
M2708
16K (2K x 8) UV Erasable PROM
M2716
M3001
Microprogram Control Unit
Central Processing Element
M3002
Look-Ahead Carry Unit
M3003
M3212
See M8212.
M3214
Interrupt Control Unit
M3216
Non-Inverting Bi-directional Bus Driver
Inverting Bi-directional Bus Driver
M3226
M3604A/
M3624A
4K (512 x 8) High-Speed PROM
M5101-4/
M5101L-4
256 x 4-Bit Static CMOS RAM
M8080A
Single Chip 8-Bit N-Channel
Microprocessor
M8102A-4
1024-Bit Fully Decoded Static RAM
M8111A
256 x 4-Bit Fully Decoded Static RAM
M8212
8-Bit Input/Output Port
M8214
Interrupt Control Unit
M8216
Non-Inverting Bi-directional Bus Driver
M8224
Clock Generator/Driver (for 8080A)
M8226
Inverting Bi-directional Bus Driver
M8228
System Controller
M8251A
Programmable Communications
Interface
Programmable Peripheral Interface
M8255A
UV Erasable and Electrically
M8702A
Programmable 2048-Bit PROM
M8708
UV Erasable and Electrically
Program mabie 8096-Bit PROM
Model 210
TEST AND INSTRUMENTATION SYSTEMS
u-Scope'" 820 Microprocessor System Console
u-Sco pe ,. Pro be 8080A
Microcomputer Training Programs
13-15
13-16
13-18
13-20
13-21
13-24
13-27
13-31
13-34
13-39
13-44
13-47
13-49
13-54
13-57
13-63
13-67
13-71
13-73
13-75
13-80
13-84
13-86
MILITARY PRODUCTS
PROGRAM DESCRIPTION
INTEL MILITARY PRODUCTS
14-2
14-2
"For specifications contact Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
1-5
14-3
4-9
3-34
3-98
3-104
3-137
4-28
4-41
4-49
12-26
12-35
12-43
4-61
3-157
11-19
12-26
12-35
12-43
11-28
12-62
12-95
I
I
I
NUMERICAL INDEX
1101A
1103
1103A
1302
256 x 1 Static MOS RAM
1024 x 1-Bit Dynamic RAM
1024 x 1-Bit Dynamic RAM
Custom Mask Programmable 2048-Bit
Static ROM
1402A
Quad 256-Bit Dynamic Shift Register
1403A
Dual 512-8it Dynamic Shift Register
1404A
1024-Bit Dynamic Shift Register
1405A
Dynamic Recirculating Shift Register
1702A
2K (256 x 8) UV Erasable PROM
M1702A
2K (256 x 8) UV Erasable PROM
1702AL
2K (256 x 8) UV Erasable PROM
2101A/8101A-4 256 x 4-Bit Static RAM
2102A/2102ALI
8102A-4
1K x 1-Bit Static RAM
M2102A-4
1K x 1-Bit Static RAM
2104A
(S Version)
4096 x 1-Bit Dynamic RAM
2104A Family
4096 x 1-Bit Dynam ic RAM
2104A
4096 x 1-Bit Dynamic RAM
2107A
4096 x 1-Bit Dynamic MOS RAM
2107B
4096 x 1-Bit Dynamic MOS RAM
2107C Family
4096-Bit Dynamic RAM
2108-2/2108-4 8192 x 1-Bit Dynamic RAM
2109 Family
8192 x 1-Bit Dynamic RAM
2111A/8111A-4 256 x 4-Bit Static RAM
2112A
256 x 4-Bit Static RAM
2114
1024 x 4-Bit Static RAM
M2114
1024 x 4-Bit Static RAM
2115A/2125A
Family
High-Speed 1K x 1-Bit Static RAM
M2115A/M2125A
Family
High-Speed 1K x 1-Bit Static RAM
2116 Family
16,384 x 1-Bit Dynamic RAM
2117 Family
16,384 x 1-Bit Dynamic RAM
2125A
See 2115A.
2141
4096 x 1-Bit Static RAM
2142
1024 x 4-Bit Static RAM
M2142
1024 x 4-Bit Static RAM
2147
4096 x 1-Bit Static RAM
2185
1024 x 8-Bit Static RAM
2308/8308
8K (1K x 8) ROM
2316A/4316A
8316A
16K (2K x 8) ROM
2316E
16K (2K x 8) ROM
M2316E
16K (2K x 8) ROM
2332
32K (4K x 8) ROM
2364
64K (4K x 8) Bit ROM
2401/2405
2048/1024-Bit Dynamic Recirculating
Shift Register
2416
CCD Serial Memory
2464
65,536-Bit CCD Serial Memory
2608
8K (1K x 8) Factory Programmable PROM
2616
16K (2K x 8) Factory Programmable PROM
2704
512 x 8 EPROM
2708/8708
8K and 4K UV Erasable PROM
M2708
8K (1 K x 8) UV Erasable PROM
2716
16K (2K x 8) UV Erasable PROM
M2716
2732
2758
2910
2911
3001
M3001
3002
M3002
3003
M3003
3101/3101A
3104
3205/3404
3-4
3-12
4-5
4-9
4-11
3-26
3-30
3-34
3207A
3208A 13408A
3-36
3-44
3-52
3-60
3-65
3-73
3-85
3-89
3-94
3-98
3212
M3212
3214
M3214
3216
M3216
3222
3226
M3226
3232
3-99
3242
3-104
3-109
3-117
3-99
3-129
3-133
3-137
3-138
3-144
4-18
3245
16K (2K x 8) UV Erasable PROM
32K (4K x 8) UV Erasable PROM
8K (1K x 8) UV Erasable Low Power PROM
PCM CODEC - uLaw
PCM CODEC - A Law
Microprogram Control Unit
Microprogram Control Unit
Central Processing Element
Central Processing Element
Look-Ahead Carry Generator
Look-Ahead Carry Generator
16 x 4-Bit High-Speed RAM
16-Bit Content Addressable Memory
3205 High-Speed 1-out-of-8 Binary
Decoder 3404 High-Speed 8-Bit Latch
Quad Bipolar-To-MOS Level Shifter
and Driver
Hex Bipolar Sense Amplifiers for
MOS Circuits
See 8212.
See M8212.
Interrupt Control Unit
Interrupt Control Unit
Parallel Bi-directional Bus Driver
Parallel Bi-directional Bus Driver
Refresh Controller for 4K Dynamic RAMs
Parallel Bi-directional Bus Driver
Parallel Bi-directional Bus Driver
Address Multiplexer and Refresh
Counter for 4K Dynamic RAMs
Address Multiplexer and Refresh
Counter for 16K Dynamic RAMs
Quad TTL-to-MOS Driver for 4K
N-Channel MaS RAMs
See 3205.
See 320BA.
256 x 4-Bit High-Speed PROM
3404
3408A
3601/3621
3602A 13622A
Family
2K (512 x 4) High-Speed PROM
3604A 13624A
Family
4K (512 x 8) High-Speed PROM
M3604A/M3624A 4K (512 x 8) High-Speed PROM
360513625
4K (1K x 4) PROM
3608/3628
8K (1 K x 8) Bipolar PROM
3621
See 3601.
3622A
See 3602A.
3624A
See 3604A.
3625
See 3605.
3628
See 3608.
4001
256 x 8 Mask Programmable ROM and
4-Bit 110 Port
4002
320-Bit RAM and 4-Bit Output Port
4003
10-Bit Shift RegisterlOutput Expander
4004
Single Chip 4-Bit P-Channel
Microprocessor
4008/4009
Standard Memory and 110 Interface Set
4040
Single Chip 4-Bit P-Channel
Microprocessor
4-22
4-25
4-28
4-29
4-30
5-3
5-7
4-31
4-34
4-38
4-41
4-44
"For specifications contact Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
1-7
4-49
4-50
4-51
7-3
7-14
8-3
8-4
8-5
3-145
3-149
6-3
6-7
6-13
12-17
12-26
12-31
12-35
12-38
12-43
6-19
12-38
6-25
6-29
6-33
6-3
6-13
4-55
4-58
4-61
4-63
4-66
4-55
4-58
4-63
4-66
9-12
9-11
9-5
9-4
9-9
9-3
NUMERICAL INDEX
Im1A
4265
4269
4289
4308
4316A
4702A
5101 Family
Clock Generator
Programmable General Purpose
1/0 Device
Programmable Keyboard Display Device
Standard Memory Interface
1024 x 8-Bit Mask Programmable ROM
and Four 4-Bit 1/0 Ports
See 2316A.
2K (256 x 8) UV Erasable PROM
256 x 4-Bit Static CMOS RAM
9-8
8275
8278
8279/8279-5
9-6
9-7
9-10
8294
8308
8316A
8355
8702A
9-14
4-22
4-14
3-153
M5101-41
8708
8741
3-157
256 x 4-Bit Static CMOS RAM
Quad TTL-ta-MOS Driver for 4K
5235/5235-1
6-37
N-Channel MOS RAMs
Quad CCD Driver
5244
11-5
8-Bit Microprocessor
8008/8008-1
10-4
Single Component 8-Bit Microcomputer
8021
10-10,18
See 8048. See also 8748.
8035
See 8049.
8039
10-23
Universal Peripheral Interface 8-Bit
8041/8741
12-3
Microcomputer
8048/8748/8035 Single Component 8-Bit Microcomputer 10-10
Single Component 8-Bit Microcomputer 10-23
8049/8039
8080A/8080A-ll Single Chip 8-Bit N-Channel
11-11
8080A-2
Mic raprocesso r
Single Chip 8-Bit N-Channel
MaOaOA
11-19
Microprocessor
Single Chip B-Bit N-Channel
8085A
11-43
Microprocessor
Single Chip 8-Bit N-Channel
8085A-2
11-57
Microprocessor
3-26
8101A-4
See 2101A.
8102A-4
See 2102A.
3-30
See 2111A.
3-85
8111A-4
2048 8-Bit Static MOS RAM with I/O
8155/8156
11-63
Ports and Timer
11-76
8185
1024 x 8-Bit Static RAM for MCS-85/48
12-11
High-Speed 1-aut-ol-8 Binary Decoder
8205
8-Bit Input/Output Port
12-17
8212/3212
12-26
M8212/M3212 8-Bit InputlOutput Port
12-31
8214/3214
Priority Interrupt Control Unit
12-35
M8214/M3214 Priority Interrupt Control Unit
M5101L-4
8748-4/8035-4
8755A
8801
Programmable CRT Controller
Programmable Keyboard Interface
Programmable Keyboard Display
Interface
Data Encryption Unit
See 2308.
See 2316A.
16,384-Bit ROM with 1/0 Ports
UV Erasable and Electrically
Programmable 2048-Bit PROM
See 2708.
See 8041/8741.
Single Component 8-Bit Microcomputer
16,384-Bit EPROM with 1/0 Ports
Clock Generator Crystal for 8224/8080A
Available Literature
Bipolar Cross Reference
Component Sales Offices
Development Systems
European Marketing Offices
Expansion Chassis Intellec® Series II
FORTRAN-80 Intellec® Resident Compiler
IC 38510 Military Products
ICE-30'M In-Circuit Emulator
ICE-41'M UPI-41'· In-Circuit Emulator
ICE-48'· In-Circuit Emulator
ICE-80'M In-Circuit Emulator
ICE-85'· In-Circuit Emulator
Insite Users' Library
Intel Technical Library
Intellec® Systems
Intellec® High-Speed Paper Tape Reader
Intellec® PROMPT-48'" Design Aid
Intellec® PROMPT-BO/85'" Design Aid
International Distributors
ISIS-II Diskette Operating System
Manufacturing Flow
MCS-48'M System Workshop
MCS-80/85'" System Workshop
MDS-EMI 8021 Emulator Board
Memory Cross Reference
Memory Support Circuits
Military Products
Military Products Manufacturing Flow
Model 210 Intellec® Series II
Model 210 Enhancement Kit Intellec® Series II
Model 220 Intellec® Series II
Model 230 Intellec® Series II
Model 770 Pri nter Intellec® Series II
Ordering Information
Packaging Information
Peripherals
PUM-80'M High-Level Programming Language
Intellec® Resident Compiler
Programming Selection
PROM/ROM Selector Guide
PROMPT-48'M Intellec® Design Aid
PROMPT-80/85'" Intellec® Design Aid
RAM Selector Guide
Recommended Products for MCS-80/85'·
RMX-80 Real-Time System Workshop
821618226,
3216/3226
12-38
4-Bit Parallel Bi-directional Bus Driver
4-Bit Parallel Bi-directional Bus Oriver
12-43
Clock Generator and Driver for 8080A CPU 11-24
Clock Generator and Driver for 8080A CPU 11-28
See 8216.
System Controller and Bus Driver for
S080A CPU
11-34
System Controller and Bus Driver for
M8228
M8080A CPU
11-38
MCS-48'" Input/Output Expander
10-28
8243
Programmable Communication Interface 12-46
8251A
M8251A
Programmable Communication Interface 12-62
12-65
8253/8253-5
Programmable Interface Timer
12-76
8255A 18255A-5 Programmable Peripheral Interface
Programmable Peripheral Interface
M8255A
12-95
12-98
8257/8257-5
Programmable DMA Controller
8259/8259-5
Programmable Interrupt Controller
12-111
8271
Programmable Floppy Disk Controller
12-123
8273
Programmable Protocol Controller
12-142
MB216/M3216
8224
M8224
8226
8228/8238
"For specifications contact Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
1-8
12-165
12-188
12-198
12-209
4-18
4-22
11-77
4-38
12-3
10-18
11-84
11-32
2-14
4-4
2-18
13-3
2-17,18
13-13
13-27
14-2
13-44
13-47
13-49
13-57
13-63
13-67
2-14
13-3
13-73
13-34
13-39
2-17,18
13-21
2-12
13-89
13-87
13-54
5-2
6-2
14-2
14-3
13-3
13-15
13-6
13-10
13-16
2-3
2-4
12-2
13-24
4-69
4-2
13-34
13-39
3-2
11-4
13-88
NUMERICAL INDEX
ROM Editor I Assembler Intellec® Series II
Sales Offices
SDK-85'· MCS-85'· System Design Kit
Serial Memories
Series 3000 Bipolar Microprocessor
Standard Product Flow
System Monitor Intellec® Series II
System Sales Offices
13-20
2-17,18
13-75
5-2
8-2
2-12
13-18
2-17
Technical Library
Telecommunications
Training Programs
u-Scope'· 820 Microprocessor System Console
u-Scope'· Probe 8080A
UPP-103 Universal PROM Programmer
User's Library
Workshops
1-9
2-14
7-1
13-86
13-80
13-84
13-71
13-67
13-86
I
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_ _ _ ii
2 General
Information
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GENERAL INFORMATION
TABLE OF CONTENTS
Ordering Information .......................................................................
Packaging Information ......................................................................
Standard Product Flow .....................................................................
Intel Technical Library ........................... ,...........................................
System Sales Offices ......................... ,..............................................
'Component Sales Offices ................................ ,...................................
2·2
2·3
2·4
2·12
2·14
2·17,
2·18
ORDERING INFORMATION
Semiconductor components are identified as follows:
Example:
M
C
o
5
L
L -_ _ _ _ _ _ _ _ _ _- , , -_ _ _ _ _ _ _ _ _ _~I
I
Four or f'Ive characters
per device type
~I
4
______. -______~
Up to three character
modifier for power,
speed, processing, etc.
Package Type
B - Hermetic Package, Type B
C - Hermetic Package, Type C
D - Hermetic Package, Type D
M - Metal Can Package
P - Plastic Package
X - Unpackaged Device
M - Indicates Military Operating
Temperature Range
Examples:
P5101 L
CMOS 256 X 4 RAM, low power selection, plastic package, commercial temperature range.
C8080A2
8080A Microprocessor with 1.5 fJ.s cycle time, hermetic package Type C, commercial
temperature range.
MD3604/C
512 X 8 PROM, hermetic package Type D, military temperature range, MI L-STD-883 Level
C processing. *
MC8080A/B
8080A Microprocessor, hermetic package Type C, military temperature range, MIL-STD-883
Level B processing. *
Kits, boards and systems may be ordered using the part number designations in this catalog.
The latest Intel OEM price book should be consulted for availability of various options. These may be
obtained from your local Intel representative or by writing directly to Intel Corporation, 3065 Bowers
Avenue, Santa Clara, California 95051.
'On military temperature devices, B suffix indicates MIL-STD-883 Level B processing. Suffix C indicates MIL-STD-883 Level
C processing. "5" number suffixes must be specified when entering any order for military temperature devices. All orders
requesting source inspection will be rejected by Intel.
2-3
I
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
PLASTIC DUAL IN-LINE PACKAGE TYPE P
I
c
r-- :8z5
l6-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
.S35 (21.2091 ~
(20.9551
l---- __ - 3 P I N 1 r
o .255 (6.4771
.245 (6.2231
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-.-l
.200(5.0801
MAfX:'::'-Ih=;:;:;:;::;::':-__
SEATING
'"2:"'('--3.-,7-5"",I-----'V
"iP
;0'
.325
I
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REF.
920 (20.820)~
880 (19812)
la-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
[1
PIN 1 MARK
~~PINl
-=- __
.300 (7.620)
.280 (7.i12)'
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.20015.0801
.00S 12.4131
IT~r~~~~oml:3=r
'i¥~1
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.125 (3.115)
L
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Jj
~.025MIN
(0.635)
M~ ;;;941-~,i~~~r ~
.090 (2.286)
PLANE
.125
___
~
=="___
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.050 TYP
MIN.
1
Ljl
¥MI ¥ f~.025 MIN
11.2701
.110 (2.794)
.032 TYP.
10.8131
r
PIN 1 MARK
.120 13.0481
.100 12.5401
.090 12.2861
J
1.060 126.924 1---+1
1
PIN 1
=~
J
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'L18.2551----1
.325
i
REF .
~PlN1MARK
!!O.1601
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.400
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.380 (9.652)
~~-
.20015.0801
MAX.
~
.10012.5401
~
PLANE
(0.254)
.022 10.5581
.015 10.3811
1.095 (27.813)
=
SEATING
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(0.635)
-
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22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
O'
;00
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LIB:i~51----l
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--:1
990 1251461
970 ~638f
.20015.0801
SEATING
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MAX.
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r------
20-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
.010 TYP.
(0.254)
:070
1,.77:1-1.,40
-="-~
---
.125 (3.175)
MIN.
.050 TYP.
11.2701
.032 TYP.
.110 (2.794)
.090 (2.286)
(0.8131 - .
2-8
MAX.
13.556)
~.025MIN.
I
I
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--I
(0.635)
.022 10.5581
.015 (0.381)
-R
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.D10TYP.
(0.254)
~
I
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.425
~
I
~(10.795)--..1
REF .
0°
W
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
CERAMIC DUAL IN-LINE PACKAGE TYPE C
Dl- cl
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
I
Tll
--~ (30.861)----'-1
1.185 130.099 1
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PIN 1 .600 ),5.2401
.570 (14.478)
-~-
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.200/S.0BO)
.095 (2.413J
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.070 11.7781
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MIN.
/1.270)
___ .022 (0.558)
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.015 10.381)
.110 (2.794)
.090 (2.286)
1.415 (35.941)
0[-~J-cl600
135.'791~1
1 -, .385
28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
PIN1MARK
t115.2401
.570 (14.478)
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.200 (5.080)
.095 (2.413)
MAX.
.070 11.7781
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.145 MAX
11T020MIN.
.010TVP
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10.5081
.022 10.5581
11.2701
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31
.625
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---.015 (0.381)
REF .
. 110 (2.794)
.090 (2.286)
40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
"
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2.020 151.3081---:1
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1.980 1 5 0 ' 2 9 I ] ; 2 1 PIN 1 MARK
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.570 (14.478)
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.095 12.4131
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=
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.145
MAX.
(3.683)
_
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i.020MIN.
.050 TVP
(1.270)
.110 (2.794)
.090 (2.286)
2-9
10.5081
.022 (0.558)
ms
(0.381)
I
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.010 TYP
1O.2541~,
~"
.625
(1~.~~~)
0
W
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
CERAMIC DUAL IN-LINE PACKAGE TYPE B
I
C
22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
1,095 (27.813) ~
1.060 (26.924)
B~-=a-~~
PIN'-':\,O,'601
=~~-
.200 (5.080)
MAX,
r-
,150 /3.810)
WW~~--;~~m'125
(3"3-1" .190 (4.826)
SEATING
"'P""LA:-:N"'E"----!--
'25J~N1751 ~ 12.7941j
~ .160
IIII-----J It
L~ ~
.090 (2.286)
C
t,O'5MIN,
~
,060 TV?
(1.524)
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
.370 ( 9.398)
~
JL020
.032 TYP.
(0.813)
, .285 (32.639)
1.235 (3l.3SS)
~~:::::
,425
MAX.
1
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(4.064)
,
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L J'
10,2541
*'
.475
.016 (O.406)
(12.065)
REF.
~~
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-
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--~-
.220(5.558)
MAX.
~
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.625
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.150 (3.810).
.125 (3.1~
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(15875)
S!~~~G. ±WWr~=r:I~=~=~~'10'5J;:~ :~:::::TYp19.~
.100 (2.540) _
MIN.
--
2'"
1~7941j
.090 (2.286)
L
.060 TVP.
(1.524)
r-
28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
(0.3811
~
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.032 TVP
(0.813)
1.485 (37.719)
1.435 (36.449)
L J
(0 254}
JI_.02010.5081
675
.016 (0.406)
(17.145)
REF.
---J
I~~~---:J~-3
-~N-'.Ir
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(3"b
~::-~-::~-::m.~ (~240)
__
.S70 (13.081)
--~~
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MAX.
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1*1
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.150 (3.810)
S)
.22O(5.S58)
,'9014,8261
"',~,"" ". L L~ ~, J ~ JL •• :::: ,.~" .~
SEATING
PLANE
-----
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(15.87S)
,155
t,01SMIN.
(3.937)
1
.010 TVP.
..J
~o
j
,090 12,2861
.060 TYP,
,032 TYP
(1.524)
(0.813)
,0'6 10.4061
L-I'7.'451-J
REF.
2.080 (52.832)
H
40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
C2.030
15'.5621~
-==:L[JPIN'-:]115,2401
__ ~
,570 ,'3.081)
--~-
.220(5.558)
~
.625
r-.MAX.~
.150 (3.810)
MAX.
.'2513'B=1
S~~~~~~G--4-~h~=~=~Jm---.-----r;:~ :~:~~:
-~
MIN.
,110 12,7941 j
.090 (2,286)
L
2-10
L
J
.060 TVP.
(1.524)
.032TVP
(0.813)
1.015 MIN.
~I
.020 10,5081
.ms (0.406)
R:I
L J
1.c:::"5.8751
.010 TYP.
~
I
......:
.
.675
07.145)REF.
0'
15"
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
METAL CAN PACKAGE TYPE M
8-LEAD METAL CAN
PACKAGE TYPE M
I'
I
·I~~DIA
.30S (7.747)
.
"85~~'0401"0161
=K
1-1
,--
.165 (4.191)
MAX.
5°~l~271 lliF~
~ ~ ~~I~~WR
.370 ~)
.335 (8.509) DIA.
8 LEADS
~ ~ DIA
.200 (5.08)
TYP,
2-11
.016 (0.406)
.
STANDARD PRODUCT FLOW
I
Optical inspection criteria based on
MIL-STD-SS3 Method 2010.38 to
insure that all devices are free
from internal defects which could
lead to failure in normal applications.
(Monitored by QA)
Hermeticity Testing to
eliminate devices which
show insufficient
hermeticity. (Monitored
byQA)
Fine leak C DIPs.CERDIPs.and
Metal cans (MIL-STD-883
Method 1014.28): Gross Leak
C DIPs and Cerdips only (Method
1014.2C. vacuum omitted and 1 hour pressurization).
Ole Attach
(Monitored by QA)
""'
~'twers AvenU8
Sanla Clara, Cal,fo.nla 95051
T81. (408) 987.8010"
TWX 910-338-002:6
TELEX 34-6372
U.S. AND CANADA SALES OFFICES
ALABAMA
Glen White Assoclalt's
7f144 Horseshoe Trsil
Huntsy,lie3S802
Tel (205) 883-9394
'"
4426 North Saddle Bag Trsil
Seollsdale65251
T81(602)994-
4979 Nortl> Milwaukee Avenue
Ch,cal,lo6063O
T&I(312)283-0300
INDIANA
OataEleclromcs
1150NShadeiandAva
SUileB-16-S
Indlanapol'546203
T~I (317) 359-5366
IOWA
Tachnlcal Repras8ntatlves, Inc
5t Andl'Elws BUlld,ng
1930 SI Andrews O.,ve NE
C&da. Rapids 52402
Tel (319j393-5510
KANSAS
Trchmcal Rapresentetlves, Inc
6245N'eman Road.Su,te=l00
Lenexa 66214
rei (913j eea-0212,'l,& 4
TWX 910_749-641~
~:~~~~DAssoclales
5fWestT,momumRoad
T,momum21093
Tel (301)252-7742
InteICe.p·
~~,~e;~J"monlum Road
Tlmcn'um~1093
Tel (301) ~52-7742
TWX 710-232-1807
Mesa Inc
11900ParklawnO"ve
Rockv,'le?06S2
Tel Wash (301j681-8430
Balto(301)792-0021
CONNECTICUT
IntalCcrp
PeoacockAlley
1 Padanaram Road,Su,lal46
Oanbury06610
Tel (203) 792-B366
TWX 710-456-1199
MASSACHUSElT8
Intel Corp'
167 Blllp"ca Road,Sulle 14A
Chelmsfo.d01824
Ta' (617)256-6&67
TWX 710-343-6333
Compute. Marketing AS90~,ates
257 C.escenl Street
Wallham02154
Tal (617)894-7000
MICHIGAN
Hwy.
Lowry&AsscCI~les,
Inc
135W NorlhStreat
5u,Ie4
BnCjhton48116
Tel· (313) 227-70e7
~!~~I:t~:mcs
SOOI E BloommglonFrwy
Su,Ia218
Bloomington 55420
Tel (61l') 661-9150
IntelCNp
8200 No,mandaleAvanue
5ulte422
Bloom,nglon55437
1al(612)635-6722
TWX ~10-5fG-26B7
MISSOURI
Techmcal Represemallvas, Inc
Trade Ca~ler Bldg
~~~~~:~~o'.:~II' SUlta
loa
NEWYORIC (conL)
T·Squared
4054New~ourtAveoue
Syracusa13206
Tel (315)463-8592
TWX 710_541_11554
T-Squared
640 Kraag RClBd
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rei (716)246-5005
TELEX 97-82R9
InlelCorp.
85 MatketStreat
Poughkeeps,a12f101
Tel (914)47'3.2303
TWX 510-248·11060
Measu.emanITachnology, Inc.
159 Northam Boulevard
GrealNackl1021
I'll (516) 462-35Q0
NORTH CAROLINA
Col-Ins-Cc
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Winston Salam 27106
Tel (800) 327-&600
Glen While Assoc,ates
3700 C'omputer oflve
Su,le330
Ralalgh27609
Tal (919)767-7016
OHIO
IntfllCcrp·
6312 NOl'lh MaonSlreel
Daylon45415
Tel (S13)B90-5350
TELEX2B6-004
IntalCo,p'
:ffl250 EuchdAv~
Tal (216) 289-01Cl
~~~Z8f R~~~~~~S
~d~~I~e~~~d
Tel (201}9B5-9100
TWX 110-480.f;238
NEW MEXICO
BFA Corporation
312We.:;t Parker Road
Las C.ucesB6001
Tal (50S} 523-0BOI
TWX 910-983-0(143
BFACorpo.ation
3705Waslerl,ald,NE
Albuquerque67111
~~45g~~~:i9~121'527
NEW YORK
Intel COl'll •
350 Vanderbilt MolorPk .... y
SUlle4C12
Hauppauge 11167
Tel (516) 231-3300
TWX :510-227-8236
InlelCorp
474 Thul'$lon Road
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Glen Wh,te Assoc'ales
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Tal (615j477-B850
Glen While Assoc,atn
2523 Howard Acad
Gefmantown38138
Tel (B01) 754·0463
GlenWh,teAssoc,ates
644BRldgeLakeRoad
HI~on 37343
Tel (615) 842-7799
TEXAS
Inial Corp
6776SW Freeway
Su,le550
Houslon77074
Tel (713)771-5761
MycrosystemsMarkellnglnc
13717 N Cant'IIIExpre~sW3v
SU,le405
Oalla8752<13
Tel (214)238-7157
TWX 910-667_4763
Mycrosystems Mlirkallng Inc
8810 HafW,n Avanua, 5ulte 1?5
Houslon77038
Tal (713)783-2900
,
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Tel (314)731-5200
TWX 910-76N1616
NEW JERSEY
InlelCorp
PENNSYLVAt,lIA(conl.)
Lowry&Assocletes,lnc
Th.eeParkwaycenter
5u,te201
Plttsburqh15220
Tel (412)922-5110
Inc
Su,ta100
Oayton45429
Tel (51J) 435-4795
Lcwry & Assoc,ates, Inc
Glen While Ass()C,ates
PO BOK 1104
Lynchburq24505
Tel (804)384-6920
~~~I~l~~aqnn
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Colonial Baach 22443
Tel (804) 2~4-4671
Blvd
Clav81and44122
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OREGON
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7100SW HamplonStreet
SUlta;21
Po.lland97223
, al (503~ 620-9616
P£NNSYLVANIA
1,leICorp'
5;>OPannsylvanlaAve
ForIWashln~lon'9034
T,,'(215)<;42-9444
TWX 510-661-0709
QEO ElectrOnics
300NYorlI20092
S·16120Bromma
Sweden
Tel/08}96SS90
TELEX 12281
ENGLAND
Intel C"rporallon (U Kj Ltd ,
BroarJf,eldHouse
4 Between Towns R08d
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i~~J~~~7~~4 31
Intel Corporallon (UK) Ltd
46-50 Baam S"aat
Nanlw,ch, Cheshire CW5 5LJ
Tel (0270)626560
TELEX 36620
GERMANY
InlelSam,C'onductorGmbh'
Seldlstra.sse27
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Tel (069)556141
TELEX 523177
InlelSam,conduclorGmbl'
Abraham Lmcoln Straasa 30
8200Wlesbadenl
Tel (06121)74655
TELEX 04186183
~.~!t~:r;;~cs~:,~~~r, ~mb~
o·7000SlUIt~rteO
ORIENT MARKETING OFFICES
JAPAN
Inl~IJapanCorpora~on'
Flowe.HJII-Shmmechl East Bid9
'-23-9, Shmmach',Selagaya-ku
TokyO 154
Ta! (03)426_9261
TELEX 761-26426
Tal (0711)1351506
TELEX 7255346
Inlel Semlconductort;mbH
Wlesanwag26
D-6272N,adartlausen
Tel (06127j2314
HONG KONG
Chona Electronics
Soa Bird House, 9th F100r
22-2S Wyndham Street
Hong Kong
KOREA
Ko.amDlg,tal
Sam Yung Blrlg :303
71·28ukchang-Do"gChyng-Ku
Seoul 100
DENMARK
Scandm8vlan5amloonductor
Supplyl>/S
Na~nasgede 16
OK-2200Copenhagen N
Tel (01)935090
TELEX 11'037
ISRAEL
Easl.onlcsLtd'
11 RozanisSt.eet
PO E\oK39300
lel-Av,v
Tel 475151
TELEX 33638
SWEDEN
Nord,skElecl,onlkAB
Fack
5-10380 Siockhclm 7
FINLAND
OyF,nt'o",cAB
LoennrotinkalU35D
ITALY
NETHERLANDS
CN RoodBV
Cortl/ender
Lmdenstr,;at,13
PO~tbU8 42
RIISWllk2H2100
TeI070·Q96360
TELEX 31238
Inel<.cNede.land
AFDElektromc
Joan Muyskenw.. g~2
NL-l006Amsterdam
Tel (020j934624
TELEX 14622
NEW ZEALAND
W K McLean Ltd
103-5 Feiton MalthewAvanua
Glenn tnnes, A~ckland
Tel 587-037
TE.LEXNZ2763
UNITED KINGDOM
Rap,d Re~all, Ltd
11-15 Betterton Street
Dru.yLano
LondonWC2H985
Tal (01) 319-67.011
TELEX 28752
NORWAY
Nord,skElektrorlk (Norga)A/S
~a;l~a~;mlconduClors Ltd
TAIWAN
Taiwan Autol'lallon Co'
2nd Floo., 224
Nanking EaslRoad
Section 3
Ts,"e.
Tel (02) 771094Q.3
TELEX 11942TAIAUTO
INTERNATIONAL DISTRIBUTORS
ARGENTINA
SIESA
Av Pie RcgueSaen2Pana 1142 P3
1035 Buenos Aires
T~I 35-6764
AUSTRALIA
A J Ferguson (Adela,da) PTY, Lid
44ProapectRd
Prospact5062
~~lut~6~~ls~~lta
17005
TELEX62S35
A J Fa.gu$onElactromc$
34 HarbartSirEoet
WeslRyda,NSW 2114
Tal AC6269·1244
TELEX 82635
Warburlon-Frankle(Sydnay)Ply Lid
199 Parramatta Road
Aubum,NSW 2114
Tal 64&-1711,648-1361
TELEX WAR FRAN AA 22265
Wa.burton-Flank,alndustnas
(Melboume)Pty Ltd,
220ParkSI.eat
SoulhMelbourna,Vlctona3205
AUSTRIA
Bacher Elektromsche Gemte GmbH
Me,dhngerHaupl~rass.a7B
A 1120Vlanna
Tal (0222)836396
TELEX (01)1532
BELGIUM
InelcoBelg,umSA
Avenue Vat Oucheese, 3
B-1160Bruss.als
Tel (02)6600012
TELEX 25441
~~I~n\~18
Tel (90)664451
TELEX 12426
FRANCE
TekelecA,rtfomc
C,ledesB.uyere5
RueCaliaVemet
92310 Sayres
Tel (1J027 7535
TELEX 250997
GERMANY
~~~~I?a~s~~:s;~~~cnnlk GmbH
0-2085 Qu,ckbor,-.-Hamburg
Tel (04106)6121
TELEX 02-13590
Elecl.omc 2000Verlnebs GmbH
Npu'llarklerSt.l.ISse 75
D-BooOMuenchen60
i~IL~~89J2~~~61
~~~~i~;fi~~
0·6277 Kamberg
Tal (06434)6005
TELEX 484426
~ledra3S5PA
•
V,aleElve21a,16
20154M,lan,
Tel (02)3493041
TELEX3B332
Eiadra3SSPA'
V'aPaOloGaldano,141 0
10137 To"no
TEL (011)3097097-3097114
Eledm3SSPA'
VI~GluseppaValmarana,63
00139Rome,It.tlf
Tel (06)8127290-eI27324
TELEX 63051
JAPAN
PMEledron
No 1 Hlgasll,kata-Macl>l
Mldo-,·Ku, ~okohama226
Tal (045)471-8811
TELEX 781-4773
Ryoyo ElootM Corp
KonwaBldg
1-12-22. Tsukljl,1-Chome
Ch"o-Ku, Tokyo 104
Tel (03)543-7711
N,ppon MicroComputer Co Lid
MUlsum, Bldg 4-5-21 KOjlfl"BChl
Ch,ycda-ku, Tokyo 102
Tel (03)2300041
INDIA
~~~~~~~I~~~~~~~nR~ad
"Nola New Telephona Number
~_~~~Vell
~~~~~:~~HA9 7PP
i~~J~1)992~:03
~ramUGAL
Jermyn Industries
VeslryEstala
Sevenoa~s, Ka.,1
ComponenleeEElactronicaLDA
Ay M,gup! Bombarda, 133
Llwoal
Tel 11945313
SOUTH AFRICA
t:lectronlcBu,ldmg Elam ..nts
PO BoK4B09
Pretofla
Tel 769221
TELEX 30161
i:~;b~Sn::1~~dro 22
2-17
~n~~~!:~O
GemSt!nstrasse2
Po~tcheck eo- 21190
CH-8021 Zunch
Tal (01) BO 2230
TELEX 56768
Tel (0-':)553893
TEI...E:.X16963
SPAIN
Interface
Secunderebad
Te,73720
TELEX 015-363
CABLE GUNTICO
i~IL~~8} 1~~a:740
+~~J~7~~I~~144
"SmlromElactromcs Ltd·
ArkwnghlRoad
Readlng,Berksh,reRG20LS
Teli0134)6S464
TELEX 847395
*FiBJd Application location
MICROCOMPUTER AND MEMORY COMPONENT
SALES AND MARKETING OFFICES
306560wersAvenue
Santa Clara, Callforma 95051
Tel: (408) 987-8080'·
TWX 910-338-0026
TELEX 34-6372
U.S. AND CANADIAN SALES OFFICES
ALABAMA
Glen White Associates
7844 Horseshoe Trail
HuntsVllte 35802
Tel (205)883-9394
ARIZONA
Intel Corp
S850N 35th Avenue
Phoenix 85021
Tel: (602) 242-7205
CALIFORNIA
intelCorp.
15335 Mornson
SUite 345
Sherman Oaks 91403
(213)986-9510
Intel Corp.·
990 E.ArquesAve
SUite 112
Sunnyvale 94086
Tel: (408) 738-3870
TWX. 910-339-9279
TWX. 910-338-D255
Mac-I
2578Shatiuck
SIllIe 48
Berkeley 94704
Tel (415)843-7625
Mac-I
PO. Box 1420
CupertlO095014
Tel (408)257-9880
EarleAssoclates,lnc
4805 MercuryStreat
Suite L
San Diego 92111
Tel (714) 278-5441
TWX' 910-335-1585
Mac-I
PO. Box 8763
Fountain Valley 92708
Tel (714)839-3341
Inlel Corp'
1651 Eaet4th Street
SUite 150
Santa Ane 92701
Tel. (714) 835-9642
TWX: 91D-595-1114
COLORADO
Intel Corp
6000 East Evans Ave
Bldg I, SUIte 260
DenverB0222
Tel (303) 758-8086
TWX 910-931-2289
CONNECTICUT
Intel Corp.
Peacock Alley
1 Padanaram Road, SUite 146
Danbury 06610
Tel. (203) 792-8365
TWX 710-456-1199
FLORIDA
Intel Corp.
1001 NW 62nd Street, SUlta 406
Ft.Lauderdale33309
Tel' (305) 771-0600
TWX 510-956-9401
Intel Corp.
5151 Adanson Straat, Suite 105
Orlando 32804
Tel' (305) 628-2393
TWX 81(}-853-9219
ILLINOIS
Intel Corp *
1000 Jone Boulevard
SUite 224
Oakbrook 60521
Tel. (312)325-9510
TWX 910-651-5881
IOWA
Technical Representatives, Inc.
SI Andrews Building
1930 St Andrews Drive N E.
Cedar Rapids 52402
Tel (319) 393-5510
KANSAS
Technical Represenlatlves, Inc
6245 Nieman Road, SUlle #100
Lenexa 66214
Tel (913)888-0212,3, &4
TWX 910-749-6412
MARYLAND
Glen While Associates
57 West Timonium Road
Timonium 21093
Tel (301)252-8380
InleICorp.*
57 West TimOnium Road
SUite 307
TimOnium 21093
Tel (301) 252-7742
TWX 710-232-1807
MASSACHUSETTS
Intel Corp *
187 Billerica Road, SUite 14A
Chelmsford 01824
Tel (617)256-6567
TWX 710-343-6333
MICHIGAN
InlelCorp.
26500 Northwestern Hwy
SUlle401
Southfield 48075
Tel. (313) 353-0820
TWX 910-420-1212
TELEX. 231143
MINNESOTA
Intel Corp.
8200 Normandala Avenue
SUite 422
Bloomington 55437
Tal (612)835-8722
TWX 910-578-2887
NEW YORK ICDnl.)
Intel Corp.
85 Market Street
Poughkeepsie, NawYork 12601
Tel (914)473-2303
TWX 510-248-0060
NORTH CAROLINA
Glen White Assoclatas
3700 Computer Dr.. SUIte 330
Raleigh 27609
TeJ. (919)787-7016
MISSOURI
Technical Representatlves,lnc,
Trade Center Bldg.
300 Brookes Drive, Suite 108
Hazelwood 63042
Tel (314) 731-5200
TWX 910-762-0618
OHIO
Intel Corp,"
8312 North Main Street
Daylon45415
Tel. (513)890-5350
TELEX 288'()04
Intel Corp."
26250 EUClid Ave.
SUite 531F
Euchd44132
Tel. (216)289-0101
NEW,JERSEY
Intet Corp
2 KUmar Road
Edison 08817
Tel (201) 985-9100
TWX 710-480-8238
OREGON
ES/Chase Company
7100 S W. Hampton Street
SUite 121
Portland 97223
Tel (503)620-9618
NEW YORK
Intel Corp"
350 Vanderbilt Motor Pkwy.
SUite 402
Hauppauge 11787
Tel (516) 231-3300
TWX 510-227-6236
Intel Corp.
474 Thuraton Road
Rochester, N.Y, 14619
Tel (716)328-7340
TWX 510-253-3841
T-Squared
4054 NewcourtAve.
Syracuse 13206
Tel. (315) 463-8592
TWX. 710 541-0554
T-Squared
640 Kreag Road
P.O. BoxW
Pittsford 14534
Tel (716) 248-5005
TELEX, 97-8289
PENNSYLVANIA
Intel Corp."
520 Pennsylvania Ave
Fort Washington 19034
Tel (215)542-9444
TWX 510-661-0709
TENNESSEE
Glen White Assoclales
At #12, Norwood SID
Jonesboro 37659
Tel (815)477-8850
Glen White AssQClates
2523 Howard Road
Germsntown38138
Tel. (901)754-0483
Glen White Associates
6446 Rloge Lake Road
Hixon 37343
Tel (615}842-7799
TEXAS
Intel Corp
6776SW. Freeway
SUite 550
Houston 77074
Tel. (713)771-5781
MycroaystemsMarketlnglnc.
13777N Central Expressway
SUite 405
Dallas 75243
Tel: (214) 238-7157
TWX. 910-S87-4763
MycrosystemsMarketln9lnc.
8810 Harwln Avenue, SUlie 125
Houston 77036
Tel' (713) 783-2900
Intel Corp·
2925L.B.J Freeway
SUltel0D
Dallas 75234
Tel. (214) 241-9521
TWX. 910-860-5487
VIROINIA
Glen White Associates
POBox 1104
Lynchburg 24505
Tel (804) 384-6920
Glen White AssoCiates
Rt.#I, Box 322
ColOnial Baach22443
Tel (804) 224-4871
WASHINGTON
ES/Chase Co,
PO Box 60903
Seattle 98108
Tel (2OS) 762-4824
Twx 910-444-2298
CANADA
Inlel Corp
70 Chamberlain Ave
Ottawa, Ontano KIS lV9
Tel (613) 232-8576
TELEX 053-4419
Mullltek, Inc.~
4 Barran Street
Ottawa, Ontario K2J lG2
Tel (613)825-4553
TELEX. 053-4585
EUROPEAN MARKETING OFRCES
BELGIUM
Intel International'
Rue du Mouhn aPapler
51-Bolle 1
B-1160 Brussels
Tel (02) 660 30 10
TELEX 24814
FRANCE
Inlel CorPOratIon, SA R L"
74, Rue D'Arcuel!
Slilc 223
94528 Rungls Cedex
Tel (01) 667 22 21
TELEX 270475
SCANDINAVIA
Intel ScandlnavlaA/S·
Lyngbyvel 322nd Floor
DK-2100 Copenhagen East
Denmark
Tel' (01) 18 20 00
TELEX. 19567
Intel Sweden AB"
Box 20092
S-16120Bromma
Sweden
Tel (08)985390
TELEX 12261
ENGLAND
Intel Corporalton (U.K.) Ltd"
Broadfteld House
4 Between Towns Road
Cowley, OXford OX4 3NB
Tel (0865) 7714 31
, TELEX 837203
Intel Corporabon (U.K.) Ltd
46-50 Beam Street
Nantwlch, Cheshire CW5 5W
Tel (0270) 62 65 60
TELEX. 36620
ORIENT MARKETING OFFICES
,JAPAN
Intel Japan Corporation·
Flower HIII-Shinmachl East Bldg.
1-23-9, ShlOmachl, Setagaya-ku
Tokyo 154
Tei (03)426-9261
TELEX' 781-28426
TAIWAN
Taiwan Automation Co *
2nd Floor, 224
Nanking East Road
Section 3
Taipei
Tel' (02) 7710940-3
TELEX: 11942 TAIAUTO
HONG KONG
China Electronics
Sea Bird House, 9th Floor
22_28WyndhamSlreet
Hong Kong
KOREA
KoramDlgltal
SamYung Bldg #303
71-2 Bukchang-DongCtlung-Ku
Seoul 100
INDIA
Electronics Inlernallona!
128 Mahatma Gandhi Road
Secunderabad
Tel 73720
TELEX 015-363
CABLE GUNTICO
,JAPAN (coni,)
Ryoyo ElectncCorp.
Konwe Bldg.
1-12-22. TsukljJ, l-Chome
Chuo-Ku, Tokyo 104
Tel (03)543-7711
NIppon Micro Computer Co. Ltd.
Mutsuml Bldg. 4-5-21 KOllmachi
Chlyoda-ku,TOkyo 102
Tel (03) 230-0041
GERMANY
Intel Semiconductor GmbH"
Seldlstrasse 27
BOOa Muenchen 2
Tel (089)558141
TELEX 523177
Intel Semiconductor GmbH
Abraham LIOcoinStrasse30
6200Wlesbaden 1
Tel' (06121) 74855
TELEX' 04186183
Intel SemIconductor GmbH
Ernsthaldanstrasse 17
0-7000 StuHgart80
Tel. (0711) 7351508
Tt:LEX' 7255346
Intal semiconductor GmbH
Wlesenweg28
0-6272 Nlederhsusen
Tel. (06127) 2314
INTERNATIONAL DISTRIBUTORS
ARGENTINA
SI ES,A
Av Pte Rogue Saenz Pena 1142 9B
1035 Buenos Aires
Tel 35-6784
AUSTRALIA
A. J Ferguson (Adelaide) PTY, Ltd.
44 Prospect Rd.
Prospect 5082
South Australia 17005
Tel 269-1244
TELEX 82635
A. J Ferguson Electronics
34 Herbert street
Wast Ryde, N S.W. 2114
Tel' AC8 269-1244
TELEX 82635
Warburton-Frankie (Sydney) Ply. Ltd
199 Parramatla Road
Auburn,NSW 2114
Tal 648-1711,648-1381
TELEX' WAAFRAN AA 22265
Warburton-Frankie Induslnas
(Melbourne) Pty.Ltd,
220 Park Street
South Melbourne, VIctoria 3205
AUSTRIA
Bacher Elektronlsche Gerate GmbH
MeldlingerHauptatrasse78
A 1120Vlenna
Tel' (0222) 83 63 96
TELEX (01) 1532
BELGIUM
Inelco Belgium SA
Avenue Val Duchesse, 3
B-1160 Brussels
Tel· (02) 86000 12
TELEX. 25441
"'Note New Telephone Number
DENMARK
ScandinaVian Semiconductor
SupplyA/S
Nannasgade 18
DK-2200Copenhagen N
Tel' (01) 93 50 90
TELEX 19037
FINLAND
Oy Flntronlc AB
Loennro\inkatu35D
SF 00180
Helsmkl18
Tel (90) 864 451
TELEX 12426
FRANCE
TekelecAlrtronlc
Cite des Bruyeres
RueCarleVernet
92310Sevres
Tel (1)0277535
TELEX 250997
GERMANY
Alfred Neye Enatachnlk GmbH
Schilierstrasse14
p..2085 QUlckbom-Hamburg
Tel: (04106) 6121
TELEX 02-13590
ElectroniC 2000 Vertrtebs GmbH
NeumarkterStrasse 75
0-8000 Muenchen BO
Tel: (089) 434061
TELEX 522561
JarmynGmbH
Postiach 1146
p..6277 Kamberg
Tel (06434) 6005
TELEX' 484428
ISRAEL
Ealilronlcs Ltd.·
11 Rozanls Street
PO. Box 39300
Tel-Aviv
Tel. 475151
TELEX 33638
ITALY
Eledra 3S S,P.A.·
Vlale Elvezla, 18
20154 Milan,
T91. (02) 3493041
TELEX 39332
Eledra 3S S.P A •
Via Paolo Galdano, 141 0
10137 Tonno
TEL {011)3097097-3097114
Eledra3SSPA.*
Via Giuseppe Valmarana, 63
00139Rome,lIaly
Tel (06)8127290-8127324
TELEX' 63051
JAPAN
Pan Electron
No 1 Higashlkata-Machl
Mldorl-Ku, Yokohama 226
Tel (045)471-8811
TELEX 781-4773
2-18
NETHERLANDS
InelcoNederland
AFDElektronlc
Joan Muysksnweg 22
NL-l006 Amsterdam
Tel. (020) 934824
TELEX 14622
NEW ZEALAND
W KMcLean Ltd
103-5 Felton Matthew Avenue
Glenn Innes, Auckland
Tel 587-037
TELEX NZ2783
NORWAY
Nordlsk EleklroOik (Norge)A/S
MustadsVel I
N-Oslo 2
Tel (02) 55 38 93
TELEX 16963
PORTUGAL
Ditram
Componentas E Electronlca LOA
Av Miguel Bombarda, 133
Llsboa1
Tal 11945313
SOUTH AFRICA
Electronic BUIlding Elements
P.O Box 4609
PretorIa
Tel: 789221
TELEX: 30181
SPAIN
Interface
Ronda San Pedro 22
Barcelona 10
Tel.3017851
SWEDEN
Nordlsk Electronlk AB
Fack
S-I0380 Stockholm 7
Tel. (OS) 248340
TELEX' 10547
SWITZERLAND
IndustradeAG
Gemsenstrasse2
Postcheck80-21190
CH-8021 Zurich
Tel (01) 60 22 30
TELEX 56788
UNITED KINGDOM
Rapid Recall, Ltd.
11-15 Betterton Street
Drury Lane
London WC2H 9BS
Tel (01)379-8741
TELEX'28752
G E.C SemIconductors Ltd
East Lane
Wembley HA9 7PP
Middlesex
Tel' (01) 904-9303
TELEX 923429
Jermyn Industries
Vestry Estate
Sevenoaks, Kent.
Tel. (0732) 50144
TELEX. 95142
*Fleld Application LocaUon
3 RandomiAccess
Memory
RANDOM ACCESS MEMORIES
Electrical Characteristics Over Temperature
Type
No.
01
Bits
Description
Dynamic,Fully Deco!!e!!
1024xl
18
300
580
400/64
+16, +19
1024
Dynamic Pull Decoded
1024xl
18
150
340
437176
+19, +22
1103A
1024
Dynamic·Fully Decoded
1024xl
18
200
580
400/64
+16, +19
loo3A·l
1024
Dynamic Fully De90ded
1024xl
18
145
340
627/10
+19, +22
1024
Dynamic Fully Decoded
1024xl
18
145
400
570/10
+.19, +22
4096
16·Pin Dynamic
4096xl
16
350
350
441125
+12, +5,-5
2104A·l
4096
16·Pin Dynamic
4096xl
16
150
320
462/26
+12, +5,-5
2104A·2
4096
16·Pin Dynamic
4096xl
16
200
320
422/26
+12, +5, -5
2104A·3
4096
16-Pin Dynamic
4096xl
16
250
375
396/26
+12, +5, -5
2104A·4
4096
16·Pin Dynamic
4096xl
16
300
425
396/26
+12, +5, -5
(S)2104A·l
4096
16·Pin Dynamic
4096xl
16
150
320
462/26
+12, +5,-5
2104A·2
4096
16·Pln Dynamic
4096xl
16
200
375
422/26
+12, +5,-5
2104A·3
4096
16·Pln Dynamic
4096xl
16
250
375
396/26
+12, +5,-5
2104A-4
4096
16·Pin Dynamic
4096xl
16
300
425
396/26
+12, +5,-5
4096
22·Pin Dynamic
4096xl
22
250
430
396/2.6
+12, +5, ~5
2107C·l
4096
22·Pin Dynamic
4096xl
22
150
360
462/2.6
+12, +5, 75
2107C·2
4096
22·1'1 n Dynamic
4096xl
22
200
400
436/2.6
+12, +5,-5
II03A·2
2101C
:!:
I-
«
(!j
Z
0
()
:::i
ii5
Supplies (VI
1024
2104A
W
Power
Dissipation
Max.!l)
Operating!
Standby (mW)
1103·1
1103
(J)
Cycle
Time
Min.
(ns)
Page
No.
DYNAMIC RAMS
'.
0
Organl.
zation
Access
No. Time
Max.
01
Pins (ns)
2107C·4
21()8.2
2108·4
2109-3
2109-4
2116·2
4096
22·Pin Dynamic
4096xl
22
300
470
396/2.6
+12, +5,-5
8192
16·Pin Dynamic
8192xl
16'
200
350
828124
+12, +5,-5
8192
16·Pln Dynamic
8192.1
16
300
425
780/24
+12, +5, -5
8192
16·Pin Dynamic
8192xl
16
200
375
462/20
+12, +5,-5
8192
16·Pin Dynamic.
8192xl
16
250
410
436/20
+12, +5,-5
16,384
16·Pln Dynamic
16,384xl
16
200
350
828124
+12, +5,-5
2116·3
16,384
16·Pin Dynamic
16,384xl
16
250
375
816/24
+12, +5,-5
2116-4
16,384
16·Pln Dynamic
16,384x1
16
300
425
760/24
+12, +5,-5
2111·2
16,384
16·Pln Dynamic
16,384xl
16
150
320
462120
+12, +5. -5
21·17·3
16,384
16·Pin Dynamic
16,384xl
16
200
375
462120
+12, +5,-5
2117·4
16,384
16-Pin Dynamic
16,364.1
16
250
410
436/20
+12, +5,-5
3-4
3·36
3·60
3-65
3-73
3·109
3·117
STATIC RAMS
2101A18101A·4
1024
Static, Separate I/O
256x4
22
350
350
300
+5
2101A·2
1024
Static, Separate I/O
256x4
22
250
250
350
+5
2101A·4
1024
Static, Separate I/O
256x4
22
450
450
300
+5
+5
21 02A18102A-4 1024
Static
1024xl
16
350
350
275
2102A·2
1024
Static
1024xl
16
250
250
325
+5
2102A·4
1024
Static
1024xl
16
450
450
275
+5
2102AL
1024
Low Standby Power Static
1024xl
16
350
350
165/35
+5
2102AL·2
1024
Low Standby Power Static
1024xl
16
250
250
325/42
+5
2102AL·4
1024
Low Standby Power Static
1024xl
16
450
450
165/35
+5
M2102A·4
1024
Stallc, TA = 55·C to +125·C
1024xl
16
450
450
350
+5
2111A18111A·4
1024
Static, Common I/O with
Output Deselect
256x4
18
350
350
300
+5
2111A·2
1024
Static, Common I/O
256x4
18
250
250
350
+5
2111A·4
1024
Static, Common I/O
256x4
18
450
450
300
+5
3·2
3·26
3·30
3·34
3-65
RANDOM ACCESS MEMORIES (Continued)
Electrical Characteristics Over Temperature
Type
No.
of
Bits
Organl·
zatlon
Description
No.
of
Pins
Access
Time
Max.
(ns)
Cycle
Time
Min.
(ns)
Power
Dissipation
Max.!11
Operatlngl
Standby (mW)
Supplies (V)
Page
No.
STATIC RAMS (Continued)
2112A
1024
Static, Common I/O without
Output Deselect
256x4
16
350
350
300
+5
2112A·2
1024
Static, Common 1/0 without
Output Deselect
256x4
16
250
250
350
+5
2112A·4
1024
Static, Common I/O without
Output Deselect
256x4
16
450
450
300
+5
4096
Static, Common 110
1024x4
18
450
450
525
+5
2114·2
4096
Static, Common 110
1024x4
18
200
200
525
+5
2114·3
4096
Static, Common 110
1024x4
18
300
300
525
+5
2114L
4096
Static, Common 110
1024x4
18
450
450
370
+5
2114L2
4096
Static, Common I/O
1024x4
18
200
200
370
+5
2114L3
4096
Static, Common 110
1024x4
18
300
300
370
+5
4096
Static, Common I/O TA
55'C to +125'C
1024x4
18
450
450
550
+5
2114
M2114
2115A,2125A
1024
Static, Open Connector
1024x1
16
45
45
370
+5
Static, Open Connector
1024x1
16
70
70
370
+5
2115AL,
2125AL
1024
Static, Open Connector
1024x1
16
45
45
240
+5
2115AL·2,
2125AL·2
1024
Static, Open Connector
1024x1
16
70
70
240
+5
M2115A,
M2125A
1024
Static, Three State
1024x1
16
55
55
690
+5
3·104
M2115AL,
M2125AL
1024
Static, Three State
1024x1
16
75
75
415
+5
3·104
+5
4096
Low Power Static
4096x1
18
120
120
3851110
4096
Low Power Static
4096x1
18
150
150
3851110
+5
2141·4
4096
Low Power Static
4096x1
18
200
200
305166
+5
2141·5
4096
Low Power Static
4096x1
18
250
250
305166
+5
2141L·3
4096
Low Power Static
4096x1
18
150
150
220128
+5
2141L·4
4096
Low Power Static
4096x1
18
200
200
220128
+5
2141L·5
4096
Low Power Static
4096x1
18
250
250
220128
+5
4096
StatiC, with Output Enable
1024x1
20
450
450
525
+5
2142·2
4096
Static, with Output Enable
1024x1
20
200
200
525
+5
2142·3
4096
StatiC, with Output Enable
1024x1
20
300
300
525
+5
2142L
4096
StatiC, with Output Enable
1024x1
20
450
450
375
+5
2142L·2
4096
Static, with Output Enable
1024x1
20
200
200
375
+5
2142L·3
4096
StatiC, with Output Enable
1024x1
20
300
300
375
+5
M2142
4096
Static, with Output Enable
1024x1
20
450
450
550
+5
2147
4096
High Speed Static
4096x1
18
70
70
8401105
+5
2147·3
4096
High Speed Static
4096x1
18
55
55
9451160
+5
2147L
4096
High Speed Static
4096x1
18
70
70
735153
+5
64
Fully Decoded
16x4
16
60
60
525
+5
64
High Speed Fully Decoded
16x4
16
35
35
525
+5
3104
16
Content Addressable
Memory
4x4
24
30
40
625
+5
5101
3101
:co.
0-
3·99
2141·3
~«
I-...J
00
3101A
(/)1Xl
/
1024
Static CMOS RAM
256x4
22
800
800
15012,5
+5
5101L
1024
Static CMOS RAM
256x4
22
650
650
135120~W
+5
O~
5101L·1
1024
Static CMOS RAM
256x4
22
450
450
135120~W
+5
~~
(/)«
5101L·3
1024
Static CMOS RAM
256x4
22
650
650
13511
+5
M5101·4
1024
Static CMOS RAM
(-55'C to 125'C)
256x4
22
800
800
16811
+5
1024
Static CMOS RAM
(-55'C to 125'C)
256x4
22
800
800
1681400~W
+5
(/)
zO
00
3·98
1024
2142
>-a,
3·94
2115A·2,
2125A·2
2141-2
~
~
3·89
<.!)
M5101L·4
3-3
3·129
3·133
3·137
3·138
3·145
3·149
3·153
3·157
inter
.1103
1024 x1 BIT DYNAMIC RAM
I
• Low Power Dissipation - Dissipates
Power Primarily on Selected Chips
• Simple Memory Expansion Chip Enable Input Lead
• Access Time - 300 nsec
• Cycle Time - 580 "sec
• Refresh Period ... 2 milliseconds
for 0 -70 0 C Ambient
• Fully Decoded - on Chip Address
Decode
• Inputs Protected - All Inputs Have
Protection Against Static Charge
• OR-Tie Capability
• Ceramic and Plastic Package -18 Pin Dual In-Line Configuration.
The Intel 1103 is designed primarily for main memory applications where high performance,
low cost, and large bit storage are important design objectives.
It is a 1024 word by 1. bit random access memory element using normally off P-channel
MOS devices integrated on a monolithic array. It is fully decoded, permitting the use of an
18 pin dual in-line package. It uses dynamic circuitry and primarily dissipates power only
during precharge.
Information stored in the memory is non-destructively read. Refreshing of all 1024 bits is
accomplished in 32 read cycles and is required every two milliseconds.
A separate cenable (chip enable) lead allows easy selection of an individual package when
outputs are OR-tied.
The Intel 1103 is fabricated with silicon gate technology. This low threshold technology allows the design and production of higher performance MOS circuits and provides a higher
functional density on a monolithic chip than conventional MOS technologies.
Intel's silicon gate technology also provides excellent protection against contamination.
This permits the use of low cost plastiC packaging.
.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
, OF 32
ROW
SELECTOR
PRC CE R/W
D'N
32
READI
WRITE
AMPLIFIERS
V B9
00---_
Vas
00---_
VDD 0-0--~
PRECHARGE 0-0- - _
CENABLE 0-0- - _
PIN NAMES
REAOiWRITE 0-0- - ' - - _
I D'N
I Ao-A9
DATA INPUT
PRC
PRECHARGE INPUT
LOGIC 0" HIGH VOLTAGE
ADDRESS INPUTS
CE
CHIP ENABLE
LOGIC 1 '" LOW VOLTAGE
IR/W
READIWRITE
DOUT
DATA OUTPUT
3·4
64
MEMORY MATRIX
1103
Maximum Guaranteed Ratings·
Temperature Under Bias
Storage Temperature
All Input or Output Voltages with
Respect to the Most Positive
Supply Voltage, VBB
Supply Voltages VDD and Vss
with Respect to VBB
Power Dissipation
OOC to 70°C
-65°C to +150 oC
'COMMENT:
Stresses above those listed under "Maximum Guaranteed
Rating" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex·
tended periods may affect device reliability.
-25V to 0.3V
-25V to 0.3V
1.0 W
D.C. and Operating Characteristics
T A = O°C to +70 o C, V~~)= 16V ± 5%, (VBB -vSS i 6
)=
SYMBOL
TEST
ILl
INPUT LOAD CURRENT (ALL INPUT PINS)
ILo
OUTPUT LEAKAGE CURRENT
lee
I DD1 (2)
Vee SUPPLY CURRENT
3V to 4V, V DD = OV unless otherwise specified
MIN.
TYP.
SUPPLY CURRENT OURING Tpc
IDD2(2) SUPPLY CURRENT DURING T ov
MAX.
UNIT
1
jJ.A
VIN = OV
VOUT = OV
CONDITIONS
1
iL A
100
iL A
37
56
mA
ALL ADDRESSES = OV
PRE CHARGE = OV
CENABLE = Vss; TA = 25°C
38
59
mA
ALL AODRESSES = OV
PRECHARGE = OV
CENABLE = OV; TA = 25°C
11
mA
PRECHARGE = Vss
CENABLE = OV; T A
I DD3 (2) SUPPLY CURRENT DURING Tpov
5.5
I DD4 (2) SUPPLY CURRENT DURING T CP
3
4
mA
PRECHARGE = VSS
CENABLE = Vss; T A = 25°C
17
25
rnA
CYCLE TIME = 580 ns; PRECHARGE
WIDTH = 190 ns; TA = 25°C
ID65J,.v
AVERAGE SUPPL Y CURRENT
VI L1171
INPUT LOW VOLTAGE
(ALL ADDRESS & DATA·IN LINES)
VsS-17
Vs s -14.2
V
TA = OOC
INPUT LOW VOLTAGE
(ALL ADDRESS & DATA·IN LINES)
Vss-17
VSS-14.5
V
TA = 70°C
VI LP,8) INPUT LOW VOLTAGE (PRECHARGE
CENABLE & READ/WRITE INPUTS)
VsS-17
Vss-14.7
V
TA = OOC
VIL417,8) INPUT LOW VOLTAGE (PRECHARGE
CENABLE& READ/WRITE INPUTS)
V ss -17
Vs S-15.0
V
TA = 70°C
VIH1 (7 )
INPUT HIGH VOLTAGE
(ALL INPUTS)
Vss-l
Vss +l
V
TA = OOC
VI H2 (7 )
INPUT HIGH 'JOLTAGE
(ALL INPUTS)
VsS-0.7
VSS+l
V
TA = 70°C
VIL2
(7)
IOH1
OUTPUT HIGH CURRENT
600
900
4000
iL A
TA = 25°C
IOH2
OUTPUT HIGH CURRENT
500
800
4000
iLA
TA = 70°C
IOL
OUTPUT LOW CURRENT
VO H1
OUTPUT HIGH VOLTAGE
60
90
400
mV
VOH2
OUTPUT HIGH VOLTAGE
50
80
400
mV
'. "o,r
VOL
OUTPUT LOW VOLTAGE
See Note 3
250C
(4)
RLO AD =1000
TA = 70°C,
See Note 3
Note 1:
Note 2:
The VSS current drain is equal to (IDO + IOH) or (lOD + lOLL
See Supply Current VS. Temperature (P. 3) for guaranteed current at the temperature extremes. These values are taken from a single pulse
Note 3:
The output current when reading a low output is the leakage current of the 1103 plus external noise co:upled into the output line from the
clocks. VOL equals IOL across the load resistor.
This value of load resistance is used for measurement purposes. I n applications the resistance may range from 100 Q to 1 kQ.
This parameter is periodically sampled and is not 100% tested.
(VBB - VSS) supply should be applied at or before VSS'
The maximum values for VIL and the minimum values for VIH are linearly related to temperature between aOc and 70 0 e. Thus any value
in between OOC and 70 0 C can be calculated by using a straight~line relationship.
The maximum values for VIL (for precharge, cenable & read/write) may be increased to VSS-14.2 @OoCandVSS-14.5@70oC (same
values as those specified for the address & data~in lines) with a 40ns degradation (worst case) in tACo tpc, tAC, twe, t AWC , tACC 1 and tACC2'
measurement.
Note
Note
Note
Note
4:
5:
6:
7:
Note 8:
3·5
I
1103
Supply Current vs Temperature
60
59
........
56
55
I
;;;:
.......
51
50
.s
62
Vss = 16.8V
60
59
V BB -Vss = 3V==
......... GUARANTEED
I I
~p
;;;:
.s
~!<
0
...........
35
30
I'......
25
i'-50
.... ....
1',
,
~~
~
~
40
TYPICAL
o
70
I'-....f'....
25
o
~o
Vss = 16.8V
VBB -VSS = 3 V -
" .....
.... I
I
6
1 1
4.1
4
GUARANTEED
~
GUARANTEED
3.9
~~
~
........
5
~ t.....
ITYPICAL
TPICAj-
4
o
25
50
o
70
U J
25
T(aC)
IDD(mA)
Typical Characteristics
:I:
IDD vs TIME
TA =25 0 C
-,-
VSS = 16.8V
VBB-V SS = 3V
I DD2 =59
IDDl =56
1.4
..2
50
70
T(ac)
AIDD
(SEE
NOTE 1)
1.6 r-,---,---r---''--'---'---::I
1.5 I-+--j--+--j--+--j--;;;,.£--j
1
TYPICAL
70
T (ac)
VBB-V SS =3V_
10
M
50
Vs~ 1=16.8VI
1
J
45
T(ac)
12
I
GUARANTEED
35
o
-
VBB -VSS = 3V==
55
54
N
~o
Vs~ ~ 16.8V'
- - I' ...
1.31-+---+
1.2 1-+---+
1.1
I---j---+
1.0 1--+---+
0.9
T PC TDV
0.8
T~~V
TCp
Tpw+ TW
0'---'---_....1..
14
15
16
Note 1. ,0,100 is due to charging of internal device node
17
capacitance at precharge
Vss (VOLTS)
Note 2. These values are taken from a single pulse measurement
1.2 ,..-,---,...,
22
1.0
16
~--r- - t OVl
VIL
ADDRESS
tCA
OVH - ' "
- - - t AC - - - - - - - . .
•
OA t RWC
IS DEFINED AS THE TRANSITIONS BETWEEN THESE TWO POINTS
tow IS REFERENCED TO POINTCDoF THE RISING EDGE OF CHIP ENABLE OR READ/WRITE WHICHEVER OCCURS FIRST
tOH IS REFERENCED TO PorNT® OF THE RISING EDGE OF CHIP ENABLE OR READ/WRITE WHICHEVER OCCURS FIRST
3-11
DATA CAN
CHANGE
I
inter
1103A
1024 x 1 BIT DYNAMIC RAM
I
*No Precharge Required -- Critical
• Address Registers
Incorporated on the Chip
Precharge Timing is Eliminated
• Electrically Equivalent to 1103-Pin-for.. Pin/Functionally
Compatible
• Simple Memory Expansion-Chip Enable Input Lead
• Inputs Protected -- All Inputs
Have Protection Against
Static Charge
• Fast Access Time -- 205ns max.
• Low Standby Power Dissipation -- 2 J,lWIBit typical
• Ceramic and Plastic
Package --18-Pin DIP
The 1103A is a 1024 word by 1 bit dynamic RAM. It is designed primarily for main memory applications
where high performance, low cost, and large bit storage are important design objectives. The 1103A is electrically equivalent to the 1103.
1103A systems may be simplified due to the elimination of the precharge clock, its associated circuitry, and
critical overlap timing. Only one external clock, CENABLE, is required.
Information stored in the'memory is non-destructively read. Refreshing of all 1024 bits is accomplished in 32
read cycles (addressing Ao to A4) and is required every two milliseconds. The memory may be used in a low
power standby mode by having cenable at Vss potential.
The 1103A is fabricated with silicon gate technology. This low threshold technology allows the design and
production of higher performance MOS circuits and provides a higher functional density on a monolithic chip
than conventional MOS technologies.
PIN CONFIGURATION
LOGIC SYMBOL
CE
BLOCK DIAGRAM
RM
"t_
AD
A,
N.C.
A,
A4
DATA OUT
D,N
A,
DATA IN
Voo
'-_-' v,.
VSBO----
Vsso-vDOo-CENABLEo--
PIN NAMES
READ/WRITEo--
DIN
DATA INPUT
NC
NO EXTERNAL CONNECTION
REQUIRED (INTERNALLY
NOT CONNECTED)
AO-A9
R/W
ADDRESS INPUTS
CE
CHIP ENABLE
READ/WRITE
DOUT
DATA OUTPUT
3-12
LOGIC 0 = HIGH VOLTAGE
LOGIC 1
=
lOW VOLTAGE
1103A
Absolute Maximum Ratings*
ooc to 10°C
Temperature Under Bias
...........................................................
Storage Temperature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150OC
All Input or Output Voltages with Respect to the most Positive Supply Voltage, VBB
. . . . . . . . . . . . . . . . . . . -25V to 0.3V
Supply Voltages Voo and Vss with Respect to VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V to 0.3V
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification isnot implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D. C. and Operating Characteristics
TA
= oOC to +70 0 C, VSS [1] = 16V ±
Symbol
5%, (VBB -VSS ) [2]
Test
III
Input Load Current (All Input
Pins)
ILO
Output Leakage Current
IBB
VBB Supply Current
1001
Supply Current During Cenable
On
IDD2
Supply Current During Cenable
Off
Typ.
Min.
= 3V to 4V, VDD = OV unless otherwise specified.
Max.
Unit
IlA
VIN = OV
VOUT
Il A
Il A
4
11
mA
Cenable
= OV; TA = 25°C
0.1
4
mA
Cenable
= VSS; TA = 25° C
Cycle Time
11
I DDAV
Average Supply Current
25
mA
Input Low Voltage
V DD - l
V DD +1
V
VIH
Input High Voltage
Vss - l
Vss +l
V
IOHl
Output High Current
Output High Current
600
IOL
Output Low Current
V OH1
Output High Voltage
60
VOH2
Output High Voltage
50
VOL
Output Low Voltage
f--
500
OV
1
100
V IL
IOH2
Conditions
1
1800
4000
Il A
1500
4000
Il A
TA
=
~2~C
TA = 100e
= 580ns; TA = 25°C
J
RLOAD (4]
See Note Three
180
400
mV
150
400
mV
= 100n
= 25°C
TA = 100e
TA
See Note Three
NOTES:
1. The VSS current drain isequal to (IDD + IOHI or (IDD + lOLl.
2. (VBB -VSSI supply should be applied at or before VSS.
3. The output current when reading a low output is the leakage current of the 1103 plus external noise coupled into the output line from the clocks.
VOL equals IOl across the load resistor.
4. This value of load resistance is used for measurement purposes. In applications the resistance may range from 100n to 1 kn.
3·13
1103A
]
Supply Current vs Temperature
2
1',
,~'~",)
,
1
1',
....
10
~
o
~
6
~o
4
o
"-
Vss : 16.8V
,'rc:r","
~,...
VBB --Vss : 3 V -
I
4 .1
<
-
®
VIL
200
250
300
350
400
I
I
I
I
I
I
V,H
500
550
I
I
--
X
600
I
_ t w ___
• l-
tAC
X
ADDRESS CAN CHANGE
tcc
l~tAH----"
ADDRESS
STABLE
..
/
.
.
tew
.....-twP-----.
~
II
-
450
I
twCyOR tRWC
'--;
f-o--I ...-
twc
VIL
150
I
1'\
CENABLE
READ!WRITE
100
I
ADDRESS STABLE
0)
tAC
50
~tDW(31~
V,H
DATA CAN CHANGE
DATA IN
VIL
X
.
tco
VOH
-
'\
DATA OUT
~~~~~ ~01~;;n ~ I\.
VOL
C LOAD '" l00pF
t Ace
---..
/
---
------""",
DATA OUT
NOT VALID
r---
~tDH(41
K
DATA CAN CHANGE
,,
DATA OUT VALID
READ CYCLE
o
I
50
100
150
200
250
300
350
400
450
I
I
I
I
I
I
I
I
I
500
550
600
I
I
I
·,1
f.o..o - - - - - - - - - - - t R c - - - - - - - - - -__
V,H
ADDRESS
V IL
®
(D
=><-
tAC
V,H
CENABLE
V IL
twc
V,H
--
ADDRESS STABLE
..-
K
ADDRESS CAN CHANGE
"
..-
VIL
'ee
.
.
tev
tco
VOH
.
~
"fiATACiDT
VREF =40mV./
R LOAD = 100n
C LOAO '" 100pF
VOL
tAce
.....
•
I\.
~-----------------
~,
"
~ DATA OUT VALID
NOTES:
}
....
~tWH--'"
\
.
~ ~~~~~:
ADDRESS
STABLE
/
J
READ/WR1TE
-.
tAC
.
......--- tAH-----'
X
tT is defined as the transition between these two points.
3. tow is referenced to point
of the rising edge of cenable or Read/Write, whichever occurs first.
4. tDH is referenced to point 2 of the rising edge of ReadlWrite.
3·16
inter
1103-1
1024 x 1 BIT DYNAMIC RAM
• High Speed 1103A - Access Time -145ns/Cycle Time-340ns
* No Precharge Required -- Critical
• Simple Memory Expansion-Chip Enable Input Lead
Precharge Timing is Eliminated
• Inputs Protected -- All Inputs
Have Protection Against
Static Charge
• Low Standby Power Dissipation -- O.2IJWIBit Typical
• Address Registers
Incorporated on the Chip
• Standard 18-Pin Dual
In-Line Packages
The Intel"'1103A-1 is a high speed 1024 bit dynamic random access memory and is the fastest version of the
standard 1103A. It is designed primarily for main memory applications where high performance, low cost, and
large bit storage are important design objectives.
1103A-1 systems may be simplified due to the elimination of the precharge clock, its associated circuitry, and
critical overlap timing. Only one external clock, CENABLE, is required.
Information stored in the memory is non-destructively read. Refreshing of all 1024 bits is accomplished in 32
read cycles (addressing AO to A4) and is required everyone millisecond. The memory may be used in a low
power standby mode by having cenable 'at \Iss potential.
The 1103A-1 is fabricated with silicon .gate technology. This low threshold technology allows the design and
production of higher performance MOS circuits and provides a higher functional density on a monolithic chip
than conventional MOS technologies.
PIN CONFIGURATION
.."
A,
2
As
3
U
BLOCK DIAGRAM
LOGIC SYMBOL
CE
1S R/W
R/W
D"
17 Vss
1103A·1
16 CENABLE
A,
15 A4
A, 4
N.C. 5
1103A-l
A,
... 6
13 ...
A, 7
12 DIN
As
8
11 Voo
A, 9
10 Vee
D,.
A,
14 DOUT
°OU1
A,
A,
A,
Vase---
A,
A,
VssO---
A.
vooO---
A,
CENABLE 0 - - -
PIN NAMES
REAOIWRITE 0 - - LOGIC 0 = HIGH VOLTAGE
0IN
DATA INPUT
NC
NO EXTERNAL CONNECTION
REQUIRED (INTERNALLY
NOT CONNECTED)
Ao-Ag
ADDRESS INPUTS
CE
CHIP ENABLE
R/W
READ/WRITE
DOUT
DATA OUTPUT
LOGIC 1
3-17
=
lOW VOLTAGE
1103A-1
Absolute Maximum Ratings*
Temperature Under Bias
Storage Temperature
...........................................................
ooc to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150OC
All Input or Output Voltages with Respect to the most Positive Supply Voltage, Vee
. . . . . . . . . . . . . . . . . . . -25V to 0.3V
Supply Voltages Voo and Vss with Respect to Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V to 0.3V
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a str~ss rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D. C. and Operating Characteristics
TA = O°C
Symbol
ILl
to + 55°C, \/ss[1J
= lev ± 5%,
Test
(VaB -VSS )121
= 3V to 4V, VDD = OV unless otherwise specified.
Typ.
Min.
Input Load Current (All Input
Pins)
Max.
Unit
10
/lA
VIN = OV
VOUT = OV
ILO
Output Leakage Current
10
/lA
100
/lA
Conditions
lee
Vee Supply Current
1001
Supply Current During Cenable
On
7
11
mA
Cenable = OV; TA = 25°C
1002
Supply Current During Cenable
Off
0.Q1
0.5
mA
Cenable = VSS; TA = 25°C
Cycle Time = 340 ns; T A = 25° C
100AV
Average Supply Current
33
mA
VIL
Input Low Voltage
V oo - l
V oo +l
y
VIH
Input High Voltage
Vss-l
Vss +l
V
IOHl
Output High Current
1150
1800
7000
/lA
TA _25 C}
IOH2
Output High Current
900
1600
7000
/lA
TA = 55°C
IOL
Output Low Current
V OH1
Output High Voltage
115
V OH2
Output High Voltage
90
VOL
Output Low Voltage
25
O
RLOAO [4]
See Note Three
180
700
mV
TA = 25°C
160
700
mV
TA= 55°C
= lOOn
See Note Three
NOTES:
1. Tho VSS current drain is equal to (100 + IOHI or (100 + lOLl.
2. (Vee -VSsl supply should be applied at or before VSS.
3. The output current when reading a low output is the leakage current of the 1103 plus external noise coupled into the output line from the clocks.
VOL equals IOL across the load resistor.
4. This value of load resistance is used for measurement purposes. In applications the resistance may range from 100.0 to 1 kn.
3-18
1103A-1
A.C. Characteristics
TA = aoc to
55°C,
Vss
=
19V
±5%,
(VBB -Vss ) =3.av to
4.av,
VDD
= av.
READ, WRITE, AND READ/WRITE CYCLE
Symbol
Test
tREF
Time Between Refresh
tAC
Address to Cenable Set Up
Time
Min.
Max.
Unit
1
ms
0
Conditions
ns
tAH
Address Hold Time
100
ns
tec
Cenable Off Time
120
ns
READ CYCLE
Symbol
Test
Min.
t RC
Read Cycle
300
tcv
Cenable on Time
140
tco
Max.
Unit
ns
500
ns
Cenable Output Delay
125
ns
tAce
ADDRESS TO OUTPUT
ACCESS
145
ns
\vH
ReadlWrite Hold Time
Conditions
t T = 20ns
C LOAO = 50pF
= lOOn
= 80mV
R LOAO
t ACC
= tAC MIN +
VREF
leo + tT
30
ns
-
WRITE OR READ/WRITE CYCLE
Symbol
Test
Min.
Max.
Unit
t wCY
Write Cycle
340
ns
t RWC
ReadlWrite Cycle
340
ns
tcw
Cenable to ReadlWrite Delay
140
twP
ReadlWrite Pulse Width
20
ns
500
Read/Write Set Up Time
20
ns
tow
Data Set Up Time
40
ns
tOH
Data Hold Time
10
tco
Output Delay
t T= 20ns
twc
Read/Write to Cenable
ns
~-
. -
125
ns
-
Test
}
ns
tw
Symbol
Conditions
0
{C LOAO = 50pF'; R LOAO
V REF = 80mV
ns
Typ. Plastic Pkg.
Plastic
Max.
Ceramic Pkg.
Unit
Max.
Conditions
CAD
Address Capacitance
5
7
12
pF
V IN = Vss
CCE
Cenable Capacitance
22
25
28
pF
CRW
ReadlWrite Capacitance
11
15
19.5
pF
CIN1
Data Input Capacitance
4
5
7.5
pF
= Vss
= Vss
Cenable = OV
VIN = Vss
C IN2
Data Input Capacitance
2
4
6.5
pF
Cenable - Vss
COUT
Data Output Capacitance
2
3
7.0
pF
VIN = Vss
VOUT = OV
NOTES:
= lOOn
VIN
f
VIN
= 1 MHz.
at A.C. ground.
-
1. These parameters are periodically sampled and are not 100% tested. They are measured at worst case operating conditions.
3-19
All
u nu sed pi ns are
1103A-1
WRITE CYCLE OR READ/WRITE CYCLE
.... . ~
twcvORtRWC
tAC
V,H
AODRESS
V,L
V ,H
®
=><
-
G)
tAC
CENABLE
VIL
twc
V,H
r-I
X
ADDRESS STABLE
I--;
~
.-
r---
.----: tw----.
tAH
VIL
tee
..
/
..
..
tew
.....-twP____.
~
,/
I--- tow (31-----.
V,H
DATA IN
ADDRESS
STABLE
-
/
READ/WRITE
X
ADDRESS CAN CHANGE
....
....-tOH i4J
X
DATA CAN CHANGE
VIL
X
DATA CAN CHANGE
teo
1-- 1-------DATA&iT
,
VOH
DJITAljl)'f
VREF=40mV,
R LOAD ,. 1000
VOL
C LOAD = 100pF
tAce
~~
-
NOT VALID
"
j4-- DATA"OUT VALID
READ CYCLE
o - - - - - - - - - - - - t R c - - - - - - - - - - -..
I
f-ol
..
V ,H
ADDRESS
VIL
=><...
®
X
ADDRESS STABLE
G)
tAC
1
.-
ADDRESS CAN CHANGE
'cc
....-.tAH~
X...
ADDRESS
STABLE
tAC
I-
V,H
'\
CENABLE
VIL
twc
/
f- .-
..
tev
_.WH-1
V,H
READ/WRITE
V"
~\
II
'eo
Votl
..
~
DATA OUT
~~~~~1':n/
VOL
CLOAD = 100pF
.....
~-----------------
-,
'- '"
~ 'DATA OUT VALID
'ACC
NOTES:
~ ~~~;~ } tr is defined as the transition between these two points.
3. tow is referenced to point
of the rising edge of cenable or Read/Write, whichever occur. first.
4. tOH is referenced to point 2 of the rising edge of Read/Write.
3·20
1103A-1
Supply Current vs Temperature
2
1', "OJ
,
:;j'
IIss = 20V
V••
'
~
OPERATING ____
23
RE'I'ON
1.2
17
18
19
\Iss
20
21
19
17
22
18
19
20
21
Vss (V)
(V)
AVERAGE IDD VS.
CYCLE TIME
I DD VS. CENABLE
0
30
,
20
15
~
0
1
'" '"
0.2
70
60
f'-
50
40
30
20
1\
'~~~
10
CYCLE TIME
(~s)
____~~::::~=-__~~~Jl_
TIME
3-21
inter
1103A-2
1024 x 1 BIT DYNAMIC RAM
• High Speed 1103A - Access Time -145nslCycle Time-400ns
*Precharge
No Precharge Required -- Critical
Timing is Eliminated
• Simple Memory Expansion-Chip Enable Input Lead
• Low Standby Power Dissipation -- O.2IJWIBit Typical
• Inputs Protected -- All Inputs
Have Protection Against
Static Charge
• Address Registers
Incorporated on the Chip
• Standard 18-Pin Dual
In-Line Packages
The I ntel®1130A-2 is a high speed 1024 bit dynamic random access memory and is the 400 ns cycle time version
of the standard 11 03A. It is designed primarily for main memory applications where high performance, low cost,
and large bit storage are important design objectives.
1103A-2 systems may be simplified due to the elimination of the precharge clock, its associated circuitry, and
critical overlap timing. Only one external clock, CENABLE, is required.
I nformation stored in the memory is non-destructively read. Refreshing of all 1024 bits is accomplished in 32
read cycles (addressing AO to A4) and is required everyone -millisecond. The memory may be used in a low
power standby mode by having cenable at Vss potential.
The 1103A-2 is fabricated with silicon gate technology. This low threshold technology allows the design and
production of higher performance MOS circuits and provides a higher functional density on a monolithic chip
than conventional MOS technologies.
PIN CONFIGURATION
",
A, 2
Ao
U
CE
18 R/W
RIW
0"
17 Vss
1103A-2
16 CENABLE
3
BLOCK DIAGRAM
LOGIC SYMBOL
A.
A, 4
N.C. 5
15 A4
1103A-2
A,
A,
14 DOUT
Ag 6
13 As
As
12 DIN
DOUT
A,
A,
A,
7
A5 B
11 V OD
A, 9
10 VgS
vssa-----
A,
A,
Vsse>-----
A,
vooe>-----
A,
CENABLE
PIN NAMES
0---
READ!WRITE 0 - - - -
LOGIC 0 '" HIGH VOLT AGE
DIN
DATA INPUT
NC
AO-Ag
ADDRESS INPUTS
CE
CHIP ENABLE
R/W
READ/WRITE
DOUT
DATA OUTPUT
LOGIC 1 '" LOW VOLTAGE
NO EXTERNAL CONNECTION
REQUIRED (INTERNALLY
NOT CONNECTED)
3-22
1103A-2
Absolute Maximum Ratings*
Temperature Under Bias
Storage Temperature
....•••.............•..................•......••.•.•..•...•
ooc to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150OC
All Input or Output Voltages with Respect to the most Positive Supply Voltage, VBB
. . . . . . . . . . . . . . . . . . . -25V to 0.3V
Supply Voltages Voo and Vss with Respect to VBB . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • . . . . . -25V to 0.3V
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . . . . . . . • . . . . 1.0W
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D. C. and Operating Characteristics
TA= O°C to
Symbol
+ 55°C, \lsS[1]
= 19V ± 5%, (VaB -VSS )[2] = 3V to"4V, VDD, = OV unless otherwise specified.
Test
Min.
Typ.
Max.
Unit
10
}1A
Conditions
VIN
VOUT =OV
= OV
III
Input Load Current (All Input
Pins)
I LO
Output Leakage Current
10
}1A
IBB
VBB Supply Current
100
}1A
1001
Supply Current During Cenable
On
7
11
rnA
Cenable = OV; TA = 25°C
1002
Supply Current During Cenable
Off
0.Q1
0.5
rnA
Cenable = VSS; TA = 25°C
Cycle Time' = 400 ns; T A = 25° C
22
100AV
Average Supply Current
30
rnA
ViL
Input Low Voltage
Voo-l
V oo +l
V
VIH
Input High Voltage
VSS-l
VSS +l
V
IOH1
Output High Current
1150
1800
7000
}1A
I~H2
Output High Current
900
1600
7000
}1A
IOL
Output Low Current
V OH1
Output High Voltage
115
V OH2
Output High Voltage
90
VOL
Output Low Voltage
TA
'2~C
TA =55°C
1
RLOAO [4]
See Note Three
180
700
mV
TA = 25°C
160
700
mV
TA = 55°C
= loon
See Note Three
NOTES:
1. The VSS current drain is equal to ODD + IOH) or ODD + lOLl.
2. (VBB -VSS) supply should be applied at or before VSS.
3. The output current when reading 8 low output is the leakage current of the 1103 plus external noise coupled into the output line from the clocks.
VOL equals IOL across the load resistor.
4. This value of load resistance is used for measurement purposes. In applications the resistance may range from 1000 to 1 kG.
3·23
1103A·2
A.C. Characteristics
TA = O°C to 55°C, Vss = 19V ±5%, (VBB -Vss )=3.0V to 4.0V, VDD = OV.
READ, WRITE, AND READ/WRITE CYCLE
Symbol
tREF
t AC
Test
Refer to page 2-23 for definitions.
Min.
Time Between Refresh
Address to Cenable Set Up
Time
Max.
Unit
1
ms
0
ns
tAH
Address Hold Time
100
ns
tcc
Cenable Off Time
180
ns
Conditions
READ CYCLE
Symbol
Test
Max.
Mill.
Urnt
t RC
Read Cycle
360
tcv
Cenable on Time
140
500
ns
tco
Cenable Output Delay
125
ns
t ACC
ADDRESS TO OUTPUT
ACCESS
145
ns
twH
ReadIWrite Hold Time
ns
Conditions
t T= 20ns
C LOAO = 5()pF
RLOAO =100.11
t ACC = t Ac MIN +
VREF = 80mV
\:0 + tT
30
ns
-
WRITE OR READ/WRITE CYCLE
Symbol
Test
Min.
Max.
Write Cycle
400
ns
t Rwc
ReadIWrite Cycle
400
ns
tew
Cenable to ReadIWrite Delay
140
twp
ReadIWrite Pulse Width
20
ns
500
ReadIWrite Set Up Time
20
ns
tow
Data Set Up Time
40
ns
tOH
Data Hold Time
10
tco
Output Delay
twc
ReadIWrite to Cenable
Test
}
tT= 20ns
ns
tw
Symbol
Conditions
.Unit
t wCY
ns
125
0
ns
ns
Typ. Plastic Pkg.
Max.
Plastic
Ceramic Pkg.
Unit
Max.
{C LOAO =50pF'; R LOAD = 100.11
VREF = BOmV
Conditions
CAD
Address Capacitance
5
7
12
pF
VIN= Vss
CCE
Genable Capacitance
22
25
28
pF
VIN = VSS
CRW
ReadIWrite Capacitance
11
15
19.5
pF
VIN = Vss
f =lMHz. All
C IN1
Data Input Capacitance
4
5
7.5
pF
Genable = OV
VIN = Vss
unused pins are
C IN2
Data Input Capacitance
2
4
/l.5
pF
Cenable - Vss
COUT
Data Output Capacitance
2
3
7.0
pF
VIN = Vss
VClUT = OV
at A.C. ground.
NOTES: 1. These parameters are periodically sampled and are not 100% tested. They are measured at worst case operating conditions.
3-24
1103A-2
Supply Current vs Temperature
2
1
2102A is a high speed 1024 word by one bit static random access memory element using N-channel MOS devices
integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to
operate. The data is read out nondestructively and has the same polarity as the input data.
The 21 02A is designed for memory applications where high performance, low cost,large bit storage, and simple interfacing are
important design objectives. A low standby power version (2102AL) is also available. It has all the same operating
characteristics of the 2102A with the added feature of 35m W maximum power dissipation in standby and 174m W in operations.
It is directly TTL compatible in all respects: inputs, output, and a single +5 volt supply. A separate chip enable (CE) lead allows
easy selection of an individual package when outputs are OR-tied.
The Intell!!> 2102A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance easy to use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.
PIN
CONFIGURATION
LOGIC SYMBOL
A.
Po.,
Ao
A5
As
A,
R/W
A.
A,
CE
A2
DATA OUT
A3
DATA IN
A.
Vee
GND
...,
A2
A3
A.
PIN NAMES
D'N
As
A.
A, DauT
As
~1w
BLOCK DIAGRAM
DATA INPUT
D'N
...,.A.
ADDRESS INPUTS
R/W
READ/WRITE INPUT
CE
CHIP-ENABLE--- -
~OYT
DATA OUTPUT
Vee
POWER (+5V)
A,
A,
CELL
ARRAV
""""
3:lCOLUMNS
CE
DATA
CU,
TRUTH TABLE
CE
RIW
D'N
DOUT
MODE
X
X
HIGH Z
NOT SELECTED
WRITE "0"
H
H
X
H
OnUT
WRITE"'"
0- "IN NUMBERS
READ
*AII8102A-4 specifications are Identical to the 2102A-4 specification••
3-30
2102A FAMILY
Absolute Maximum Ratings*
Ambient Temperature Under Bias
Storage Temperature
Voltage On Any Pin
With Respect To Ground
Power Dissipation
-10°C to 80°C
-65°C to +150 0 C
-O.5V to +7V
1 Watt
'COMMENT:
Stresses above those listed under" Absolute Maximum Rating"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
at any other condition above those indicated in the opera·
tional sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
D. C. and Operating Characteristics
TA = O°c to 70°C, Vcc = 5V ±5% unless otherwise specified.
Symbol
Parameter
2102A,2102A·4
2102AL,2102AL·4
Limits
Min. Typ.ll1 Max.
2102A·2,2102AL·2
Limits
Typ.t 11 Max.
Min.
Unit Test Conditions
IU
Input Load Current
1
10
1
10
pA
VIN = 0 to 5.25V
ILOH
Output Leakage Current
1
5
1
5
pA
CE = 2.0V,
VOlJT = VOH
ILOL
Output Leakage Current
-1
-10
-1
-10
pA
CE = 2.0V,
VOUT = O.4V
ICC
Power Supply Current
33
Note 2
45
65
mA
All Inputs = 5.25V,
Data 0 ut 0 pen,
TA = O°C
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
0.8
-0.5
0.8
V
Vcc
2.0
Vcc
V
0.4
V
IOL = 2.1mA
V
IOH = -100pA
0.4
2.4
2.4
Notes: 1. Typical values are for TA = 25°C and nominal supply voltage.
2. The maximum ICC value is 55mA for the 2102A and 2102A·4, and 33mA for the 2102AL and 2102AL·4.
Standby Characteristics
TA
2102AL, 2102AL·2, and 2102AL·4 (Available only in the Plastic Package)
= O°C to 70°C
Min.
Vcc in Standby
1.5
1.5
V
CE Bias in Standby
2.0
2.0
V
VPD
VPD
V
Symbol
VPD
VcEs [21
2102AL·2
Limits
Typ.t 11
2102AL,2102AL·4
Limits
Typ.tl1
Min.
Max.
Parameter
Max.
Unit
Test Co nditions
2.0V-
I
1.2
1.0
) =5L
o
10
20
rI
30
40
--
25
r~rI
~
~
30
50
--
60
20
/
<1
.§
15
10
/
/'
v
I-
TYPICAL
I
TA
= 25°C
Vee MIN.
70
VOL (VOLTS)
ACCESS TIME VS.
LOAD CAPACITANCE
ACCESS TIME VS.
AMBIENT TEMPERATURE
350
350
.I.
250
TYPI~
--
TA = 25 C
Vee MIN.
1 TTL LOAD
Vee MIN.
1 TTL LOAD
CL = l00pF
~
250
~I-
./'
~YPICAl
150
150
our
OUTPf REFrENCEILEVELj' VOH : 2.0V
VOL 10.8V
50
o
10
20
30
40
50
60
100
70
200
-
3·33
10-
-
T RTRENCEI LEVEL 1'.5V
300
CLI.F)
T.I"C)
Q
400
500
600
intel~
M2102A-4
1K x 1 BIT STATIC RAM
I
• Three State Output: OR .. Tie
Capability
• 16 'Pin Hermetic Dual.. ln .. Line
Package
• 10% Vee Supply Tolerance
• Directly TTL Compatible: All
Inputs and Output
• Low Power: 38SmW Max.
The Intel® M2102A is a high speed 1K x 1 RAM specified over the -55"C to +125°C temperature range. The RAM uses fully DC
stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is r\!lad out nondestructively and has
'
the same polarity as the input data.
The Intel® M2102A is fabricated with N·charinel silicon gate technology. This technology allows the design and production of
high performance easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.
PIN CONFIGURATION
LOGIC SYMBOL
A.
..,
A.
A,
R/W
Ag
A,
CE
A3
A.
As
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias .. _65°e to +135°e
Storage Temperature .......... -65° C to +150 0 C
Voltage On Any Pin
With Respect to Ground , .... ',. -O.6V to +7V
Power Dissipation , ...... , .......... ,. 1 Watt
Ao
A,
A2
A2
DATA OUT
A.
DATA IN
A.
Vec
II.,
GND
DIN
A.
A7
DOUT
'ceMMENT
As
Stresses above those listed under "Absolut,. Maximum Rating"
may CfSuse permanent damage to the device. This is a stnns rat~
~1w ce
TRUTH TABLE
CE
R/W
X
L
o,N
"oUT
HfGH Z
ing only and functional operation of the devies at these or at any
other condition above those indicated in the operational sltctions
of this specification is not implied. Exposure to absolute ma)(i~
mum rating conditions for I'!xtended periods may affect d,vice
reliability.
NOT SELECTED
WRITE ''0''
WRITE "1"
R~AD
D. C. and Operating Characteristics TA '" -SSOC·to +12S0C, Vec =SV ± 10% unless otherwise specified
Symbol
Parameter
Limits
Min.
Typ)lJ
Max.
Unit
Test Conditions
ILl
Input Load Current
10
p,A
VIN '" 0 to S.SV
ILOH
Output Leakage Current
10
p,A
CE =Min. VIH , VOUT
ILOL
Output Leakage Current
-so
p,A
CE", Min. VIH , VOUT '" 0.4SV
ICCl
Power Supply Current
60
mA
All Inputs'" S.SV,
Data Out Open, TA '" 2SoC
ICC2
Power Supply Current
70
mA
All Inputs '" S.SV,
Data Out Open, TA '" -SSoC
VIL
Input "Low" Voltage
-O.S
0.8
V
VIH
Input "High" Voltage
2.0
Vcc
V
VOL
Output "Low" Voltage
0.45
V
IOL'" 2.1 inA
VOH
Output "High" Voltage
V
IOH '" -100 p,A
30
2.2
NOTE 1. Typical values are for TA = 25°C and nominal supply voltage.
3·34
= VOH
M2102A-4
A.C. Characteristics TA ~ -55°C to +125°C. Vee ~ 5V ± 10% unless otherwise specified
Symbol
M2102A-4 Limits (ns)
Parameter
Min.
Max.
READ CYCLE
tRe
Read Cycle
tA
Access Time
450
teo
Chip Enable to Output Time
tOH1
Previous Read Data Valid with Respect to Address
tOH2
Previous Read Data Valid with Respect to Chip Enable
450
230
40
0
WRITE CYCLE
twe
Write Cycle
450
tAW
Address to Write Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Setup Time
20
300
0
300
tDH
Data Hold Time
tew
Chip Enable to Write Setup Time
0
300
Capacitance[2J TA
A.C. CONDITIONS OF TEST
SYMBOL
1ansee
Input Rise and Fall Times:
Reference Levels
Output Load:
LIMITS (pF)
TEST
0.8 Volt to 2.0 Volt
Input Pulse Levels:
Timing Measurement
~ 25°C. f ~ 1 MHz
Inputs:
Output:
C IN
INPUT CAPACITANCE
(ALL INPUT PINS) VIN = OV
C OUT
OUTPUT CAPACITANCE
1.5
Volts
0.8 and 2.0 Volts
1 TTL Gate and CL = 100 pF
VOUT = OV
TVpJ11
MAX.
3
5
7
10
Waveforms
READ CYCLE
WRITE CYCLE
~------------'wc-----------~
I-------'RC--------I
CHIP
ENABLE
CHIP
DATA
READ!
'cw
ENABLE
'wP
OUT
WAITE
CD
@
@
NOTES:
1.5 VOLTS
'ow
2.0 VOLTS
DATA
IN
0.8 VOL TS
1. Typical values are for TA =
25" e
and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3-35
DATA STABLE
inter
2104A FAMILY
4096
I
x 1 BIT DYNAMfC RAM
86047
56848
Max. Acce •• Time (n.)
150
200
259
300
Read, Write Cycle (n.)
320
375
375
425
3S
32
30
30
Max. IDD (mA)
• Highest Density 4K RAM Industry Standard 16 Pin Package
• Low Power 4K RAM: 462mW Operating
27mW Standby
• All Inputs Including Clocks TTL
Compatible
• :!;10% Tolerance on All Power Supplies
+12V, +5V, -5V
stOSO
$6049.
• Refresh Period: 2 ms
• On-Chip Latches for ACildresses, Chip
Select and Data In
• Simple Memory Expansion: Chip Seleet
• Output is Three-State, TTL Comp~t.ible;
Data is Latched and Vatid into Next Cycle
• RAS-Only Refresh Operation
The Intel@ 2104A is a 4096 word by 1 bit MOS RAM fabricated with N-channel silicon gate technology for high performance
and high functional density.
The efficient design of the 2104A allows it to be packaged in the industry standard 16 pin dual-in-line package. The 16 pin
package provides the highest system bit densities and is compatible with widely available automated handling equipment.
The use of the 16 pin package is made possible by multiplexing the 12 address bits (required to address 1 of 4096 bits) into
the 2104A on 6 address input pins, The two 6 bit address words are latched into the 2104A by the two TTL clocks, Row
Address Strobe (RAS) and Column Address Strobe (CAS). Non-critical clock timing requirements allow use of the
multiplexing technique while maintaining high performance.
A new unique dynamic storage cell provides high speed along with low power dissipation and wide voltage margins. The
memory cell requires refreshing for data retention. Refreshing is most easily accomplished by performing a FlAS-only
refresh cycle or read cycle at each of the 64 row addresses every 2 milliseconds.
The 2104A is designed for page mode operation, RAS-only refresh, and CAS-only deselect.
PIN CONFIGURATION
v aB
LOGIC DIAGRAM
v"
Ao
0,.
CAS
A,
WE
Dour
A,
RAS
es
A,
A.
A,
A,
A,
A.
A,
"-
VDD
BLOCK DIAGRAM
WE ---r}.E!~...J
0,.
0,.
A,
Dour
Vee
"out
PIN NAMES
Ao·Ao
CAS
ADDRESS INPUTS
COLUMN ADDRESS STROBE
WE
- V..
"096 BIT
WRITE ENABLE
POWER 1-5VJ
POWER ,+SVI
CS
o,N
CHIP SELECT
VBa
Vee
DATA IN
VoD
POWER (+12Vl
DoUT
DATA OUT
Vss
GROUND
RAS
ROW ADDAESS STROBE
STORAGE ARRAY
- VOD
-Vee
_GNO
CLOCK
GENERATOR NO.1
2104A FAMtLY
ABSOLUTE MAXIMUM RATINGS"
'COMMENT:
Ambient Temperature Under Bias ..... _10 0 C to +80°C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Voltage on any Pin Relative to VBB
(Vss - VBB ;;;. 4.5V) . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Data Out Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device_ This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to abselute maximum rating conditions for extended
periods may affect device reliability.
D.C. AND OPeRATING CHARACTI;RISTICS[1]
TA = 0 0 to 70°C, Voo = +12V ±10%, Vcc = +5V ±10%, VBB = -5V ±10%, Vss = OV, unless otherwise noted.
Limits
Symbol
Parameter
Min.
Typ.(21
Max.
Unit
Conditions
ILl
Input Load Current (any input)
10
J.i.A
VIN
IILOI
Output Leakage Current for
High Impedance State
10
J.i.A
Chip deselected: RAS and CAS at VIH
VOUT = 0 to 5.5V
1001 [3]
V 00 Standby Current
IBB1
VBB Standby Current
1002[3]
Operating V 00 Current
IBB2
Operating VaB Current
ICC1[4]
VCC Supply Current when
Deselected
1003
Operating Voo Current
(RAS-only cycle)
VIL
I nput Low Voltage (any input)
to VIH MAX
= 13.2V
= 12.6V
0.7
2
mA
Voo
0.7
1.5
mA
Voo
5
50
J.i.A
Voo = 13.2V
CAS and RAS at VIH.
Ch i p deselected prior
to measu rement.
See Note 5.
= tRC MIN
= tRC MIN
tRC = tRC MIN
= O°C
24
35
mA
S6047
22
32
mA
S6048
20
30
mA
S6049, S6050
130
325
J.i.A
Min cycle time. TA
10
J.i.A
25
mA
S6047,S6048
tRC = tRC MIN
S6049,S6050
tRC = tRC MIN
12
22
mA
-1.0
10
0.8
V
2.2
7.0
V
Input High Voltage
VIH
= Vss
tRC
tRC
(Ao-A5, DIN,CS)
VIHC
Input High Voltage
(RAS, CAS, WE)
2.4
7.0
VOL
Output Low Voltage
0.0
0.4
V
IOL = 3.2 mA
VOH
Output High Voltage
2.4
Vcc
V
IOH
Symbol
Test
Typ.
Max.
Unit
3
7
pF
Input Capacitance (RAS, WRITE)
3
7
pF
Co
Output Capacitance (DOUT)
4
7
pF
CI3
Input Capacitance (CAS)
6
7
pF
CI1
Input Capacitance (Ao-A5, DIN,
CI2
CS)
= -5 mA
Conditions
= Vss
= VSS
VOUT = OV
VIN = Vss
VIN
VIN
Notes: 1. All voltages referenced to VSS. The only requirement for the sequence of applying voltages to the device is that VOO, VCC, and
VSS should never be O.3V or more negative than VBS. After the application of supply voltages or after extended periods of operation without clocks, the device must perform a minimum of one initialization cycle (any valid memory cycles containing both RAS
and CAS) prior to normal operation.
2. Typical values are for TA "" 2SoC and nominal power supply voltages.
3. The 100 current flows
4. When chip is selected
to
VSS.
Vee
supply current is dependent on output
loading~C
is connected to output buffer on!y';
5. The chip is deselected; i.e., output is brought to high impedance state by CAS-only cycle or by a read cycle with CS at VIH.
6. Capacitance measured with Boonton Meter.
3-37
I
2104A FAMILY
A.C.CHARACTERISTICS[1,2]
TA:ooe to 70 oe, VDD: 12V ±10%, Vcc=5V ±10%, VBB=-5V ±10%, Vss=OV,unless otherwise noted.
READ, WRITE, AND READ MODIFY WRITE CYCLES
Parameter
Symbol
I
86047
Max.
Min.
S6048
Max.
Min.
86049
Min.
Max.
2
2
86050
Max.
Min.
2
2
tREF
Time Between Refresh
tRP
RAS Precharge Time
100
120
120
125
tcP
CAS Precharge Time
60
80
110
110
tRCD[3]
RAS to CA8 Delay Time
20
tCRP
CAS to RAS Precharge Time
tRSH
RAS Hold Time
tAR
RAS to Address or CS Hold Time
tASR
Row Address Set-Up Time
tASC
Column Address or CS Set-Up Time
tRAH
50
65
25
35
85
Unit
ms
ns
ns
80
135
ns
0
0
0
0
ns
100
135
165
165
ns
95
120
160
215
ns
0
0
0
0
ns
-10
-10
-10
-10
ns
Row Address Hold Time
20
25
35
80
ns
tCAH
Column Address or CS Hold Time
45
55
75
80
ns
tT
Rise or Fall Time
3
50
3
50
3
50
3
50
ns
tOFF
tCAcl 4 ,5]
Output Buffer Turn-Off Delay
0
50
0
60
0
60
0
80
ns
Access Time F rom CAS
100
135
165
165
ns
tRAC[4]
Access Time From RAS
150
200
250
300
ns
READ CYCLE
S6047
8ymbol
Parameter
Min.
Max.
86048
Min.
Max.
375
86049
Min.
86050
Max.
Min.
10000
300
Max.
tRC
Random Read or Write Cycle Time
320
tRAS
RAS Pulse Width
150
tCAS
CAS Pulse Width
100
135
165
165
ns
IRCS
Read Command Set-Up Time
0
0
0
0
ns
tRCH
tDOH
Read Command Hold Time
0
a
0
0
ns
10
10
10
10
, tRCD(MAX)
access time is tRCD + tCAC.
4. Load = 2 TTL loads and 100pF.
5. Assumes tRCD ;;, tRCD(MAX).
6, In a write cycle with twcs;;' tWCS(MIN) the cycle is an early write cycle and DOUT will be data written into the selected cell
(DOUT = DIN)- If tCWD;;' tCWD(MIN) and tRWD;;' tRWD(MIN) the cycle isa read-modify-write cycle and
DOUT will be data from the selected address read. If neither of the above conditions are satisfied, DOUT
is indeterminate.
3-38
ns
ns
2104A FAMILY
WAVEFORMS
'RC
f---
,"AS
READ CYCLE v,",
CD
,"SH
'RCD
cAs
t
AsRr
~
ADDRESSES
tRP -
lit -'cRP~L
l0
_,"AH-_1
ROW
,X
0J
\\\\ l0
I-
tAse
){
ADDRESS
III1
-
teAs
I
1---'cAH~~
----------tcP-
X
COLUMN
ADDRESS
'AR
0({
r
VIHC
1---~'cAH--
tAse
/
..,t
tRCS
v"
~---tRAC
t CAC
tOFF ___
t='aoHi
1-
vaH
..0
vaL
-¥@
DOUT
WRITE CYCLE
f
HIGH IMPEDANce
'"C
CD \\\\ 0
tASRr--
V,H
){CD0
v"
-~AH--i
'ASC
ROW
)(
ADDRESS
)(
V'H
\
OS
v"
-
lit
-tcRP
VI/
-'c!>
,
t RSH
tRCO
ADDRESSES
I·-'RP~-==:d
•
0
~~
VALID
DATA OUT
~
,"AS
CD
RCH
~
J¥
WE
(,
'cA.
~~
I---tcAH-
X
COLUMN
ADDRESS
'wCR
'AR
'ASC
-----.-tcAH-
f2\
/
t RWL
,\I--'wcs~
VIHC
.0
WE
v"
'CWL
-'wCH~
'wP
tOHR
®""t-
V,H
-'oH~
XCD0
O'N
v"
,
K
tRAC
'oFF
,
'CAC
"\.0
I.
-r®
'\.
HIGH IMPEDANCE
¥-0
"oUT
tQOH-j
VALID
DATA OUT
}-
RAS-ONL Y REFRESH CYCLE
1-------------'RC--------------1
vIHc _ _-",-,LII------------tRAs--------------I1
RAS
V
1L
CD
r-'RP~
l'f
0
,'-___
.x CD AD~~v:.SS J(
v"-L:f.,,,..-"'==---''P--------------------------o
ADDRESSES V
1H
(See next page for notes)
3-39
2104A FAMILY
A.C.CHARACTERISTICS [7,8]
TA = 0° to 70°C, Voo=12V ±10%, Vcc=5V ±10%, Vss=-5V ±10%, Vss=OV,unless otherwise noted.
READ-MODIFY-WRITE CYCLE
Symbol
I
Parameter
S6047
Min.
Max.
S6048
Min.
Max.
S6049
Min.
Max.
S6050
Min.
Max.
330
420
480
575
Unit
tRWC
Read Modify Write Cycle Time [2]
tCRW
RMW Cycle CAS Width
115
tRRW
RMW Cycle RAS Width
165
tRWL
RMW Cycle RAS Lead Time
50
70
85
130
ns
tCWL
Write Command to CAS Lead Time
50
70
85
130
ns
twp
Write Command Pulse Width
45
55
75
80
ns
tRCS
Read Command Set·Up Time
a
a
a
ns
tRWO[6]
RAS to WE Delay
110
145
175
250
ns
tcwo [6]
CAS to WE Delay
60
80
90
115
ns
tos
Data·ln Set-Up Time
tOH
Data-In Hold Time
155
10,000
-
a
265
10,000
ns
250
180
220
ns
10,000
385
10,000
ns
a
a
a
0
ns
55
65
75
80
ns
WAVEFORMS
READ-MODIFY-WRITE CYCLE
"'we
~r--tRP~
"'RW
8
0
-tcRp------..1
i--- tRCD
ADDRESSES
v,"
V"
tASR~
tCRW
8 ~\\ 0
VI}
f---l-t
r1'"A"
tAscr
)(eD AD~~~SS J( X ~g~~~~
f--t
0
-"'WL~
---t
CWL
CAH
__
------------ ' t c p -
)(
AR
v,"
Iv"
t~
80
t RWD
tResl~
~~,-y
tow~
VIHC
WE
00/
l
~:®ltO"®
I.-tos®
XeD
t RAC
tOFF~
t CAC --------------
®
HIGH
IMPEDANCE
0
0
®
DATA IN
VALID
:x
tDOH-----J
VALID
DATA OUT
Notes: 1,2. VIHMIN or VIHCMIN and VILMAX are reference levels for measuring timing of input signals.
3,4. VOHMIN and VOLMAX are reference levels for measuring timing of 00UT.
5.
Referenced to CAS or WE, wh ichever occurs last.
6.
In a write cycle with tWCS;;' tWCS(MIN) the cycle is an early write cycle and 00UT will be data written into the selected cell
(DOUT = DIN). If tCWD;;' tCWD(MIN) and tRWD;;' tRWD(MIN) the cycle is a read-modify-write cycle and DOUT will be
data from the selected address read. If neither of the above conditions are satisfied, DOUT is indeterminate.
7.
8.
All voltages referenced to VSS.
A.C. Characteristics assume tT
= 5n5.
340
2104A
FAMILY
TYPICAL CHARACTERISTICS
.
t.e
3D
-
I.
40
80 •
--
••
TA
tRCO
100ns
t.P
1S0ns_
3. f---f---f--tRCD
=
10005_ 600
.,
400
r---
5.
25
'" 2S"C
teAS '" 200 os
60.
200
~
-"
j
2.
f - - - - . . / - - - / - - - / - - - - - i 400
"-..
"'~2
I.
100
•
~ ~ 150 1-----+-
1l.!'
.... ___
75
260 , - - - - , . - - - - , , - - - - , - - - - - ,
Voo = lD.8V
Vea = -5.5V
Voo '" 12.0V
Vae = -5,OV
-
1002
r---r---r---,-----.~
12.0V
-5.0V
500 ns
Voo
V••
TYPICAL ACCESS TIME
VS. TEMPERATURE
TYPICAL IBB2 AND 1002
VS. CYCLE TIME
TYPICAL IBB2 AND 1002
VS. TEMPERATURE
_ _ 20.
100
F-----i/---/-----i-----i
' ••2
•~L=:t=:::::C::::::d •
200
400
TEMPERATURE (OCI
600
800
1000
25
5.
75
100
TEMPERATURE (OCI
TCVCLE (nl)
APPLICATIONS
ADDRESSING
Two externally applied negative going TTL clocks. Row
Address Strobe (RAS). and Column Address Strobe
(~). are used to strobe the two sets of 6 addresses into
internal address buffer registers. The first clock. RAS.
strobes in the six low order addresses (AD-As) which
selects one of 64 rows and begins the timing which
enables the column sense amplifiers. The second clock.
CAS. strobes in the six high order addresses (A6-AI tl to
select one of 64 column sense amplifiers and Chip Select
(CS) which enables the data out buffer.
system access time since the decode time for chip select
does not enter into the calculation for access time.
Both the RAS and CAS clocks are TTL compatible and do
not require level shifting and driving at high voltage MOS
levels. Buffers internal to the 2104A convert the TTL level
signals to MOS levels inside the device. Therefore. the
delay associated with external TTL-MOS level converters
is not added to the 2104A system access time.
An address map of the 2104A is shown below. Address "0'"
corresponds to all addresses at VIL. All addresses are
sequentially located on the chip.
READ CYCLE
A Read cycle is performed by maintaining Write Enable
(WE) high during CAS. The output pin of a selected device
will unconditionally go to a high impedance state
immediately following the leading edge of CAS and
remain in this state until valid data appears at the output at
access time. The selected output data is internally latched
and will remain valid for at least tOOH MAX. A subsequent
CAS must be given to the device either by a Read. Write.
Read-Modify-Write. CAS-only or RAS/CAS refresh cycle.
2104A Address Map
4032
0
a:
w
C
~
c
ARRAY
(DATA lNI
~
a:
4095
Device access time. tACC. is the longer of two calculated
intervals:
63
SENSE AMPLIFIER
COLUMN DECODER
1. tACC
= tRAC
OR 2. tACC
= tRCO + tCAC
Access time from RAS. tRAC. and access time from CAS.
tCAC. are device parameters. RAS to CAS delay time. tRCO.
is a system dependent timing parameter. For example.
substituting the device parameters to the S6050 yields:
DATA CYCLESITIMING
A memory cycle begins with addresses stable and a
negative transition of RAS. See the waveforms on page 4.
It is not necessary to know whether a Read or Write cycle
is to be performed until CAS becomes valid.
3. tACC = tRAC = 300ns for 80nsec :::; tRCO :::; 135nsec
OR
4. tACC = tRco + tCAC = tRCO + 165ns for tRCO > 135ns.
Note that Chip Select (CS) does not have to be valid until
the second clock. CAS. It is. therefore. possible to start a
memory cycle before it is known which device must be
selected. This can result in a significant improvement in
3·41
2104A FAMILY
I
Note that if 80nsec S tRCO S 135nsec, device access time is
determined by equation 3 and is equal to tRAC. If tRCD >
135ns, access time is determined by equation 4. This 55ns
interval (shown in the tRCD inequality in equation 3) in
which the falling edge of CAS can occur without affecting
access time is provided to allow for system timing skew in
the generation of CAS. This allowance for a tRCD skew is
designed in at the device level to allow minimum access
times to be achieved in practical system designs.
Write, or Read-Modify-Write cycle. A device is deselected
by 1) driving CS high during a Read, Write, or ReadModify-Write cycle or 2) performing a CAS Only cycle
independent of the state of CS.
REFRESH CYCLES
Each of the 64 rows internal to the 2104A must be
refreshed every 2 msec to maintain data. Any cycle (Read,
Write, Read-Modify-Write, RAS-only refresh) refreshes
the entire selected row (defined by the low order row
addresses). The refresh operation is independent of the
state of chip select. It is evident, of course, that if a Write or
Read-Modify-Write cycle is used to refresh a row, the device should be deselected (CS high) if it is desired not to
change the state of the selected cell.
WRITE CYCLE
A Write Cycle is generally performed by bringing Write
Enable (WE) low before CAS. Don will be the data written
into the cell addressed. If WE goes low after CAS but tCWD
< tCWD MIN and tRWD < tRWD MIN, Dour will be
indeterminate.
PlEAD-MODIFY-WRITE CYCLE
A Read-Modify-Write Cycle is performed by bringing
Write Enable (WE) low during a selected RAS/CAS cycle
with tRwD ::::tRWD MIN and tCWD ::::tCWD MIN. Data in must be
valid at or before the falling edge of WE. In a read-modifywrite cycle Dour is data read from the selected cell and
does not change during the modify-write portion of the
cycle.
CAS ONLY (DESELECT) CYCLE
In some applications, it is desirable to be able to deselect
all memory devices without running a regular memory
cycle. This may be accomplished with the 2104A by per·
forming a CAS·Only Cycle. Receipt of a CAS without
deselects the 2104A and forces the Data Output to the
high·impedance state. This places the 2104A in its lowest
power, standby condition. 100 will be about twice 1001 for
the first cycle of CAS'only deselection and 1001 for any
additional CAS'only cycles. The cyc.!!...!i":!.!.!!ll and CAS
timing should be just as if a normal RAS/CAS cycle was
being performed.
m
RAS/CAS TIMING
The device clocks, RAS and CAS, control operation of the
2104A. The timing of each clock and the timing
relationships of the two clocks must be understood by the
user in order to obtain maximum performance in a
memory system.
The RAS and CAS have minimum pulse widths as defined
by tRAS and tCAS respectively. These minimum pulse
widths must be maintained for proper device operation
and data integrity. A cycle, once begun by driving RAS
and/or CAS low must not be ended or aborted prior to
fulfilling tl1e minimum clock signal pulse width(s). A new
cycle must not begin until the minimum precharge time.
tRP. has been met.
PAGE MODE OPERATION
The 2104A is designed for page mode operation. Product
tested to page mode operating specifications are available
upon request.
POWER SUPPLY
CHIP SELECTION/DESELECTION
The 2104A is selected by driving
RAlICAS CVCL~
RAS
CAl
v,.
v"
v,.
v"
. ~~;-
-,
-
I
n..r-~
~
.
eoo
700 100 900 10001""
r\r-)J
l-
~
- ~ rv I~ J~
A 0.01 IlF ceramic capacitor is recommended between Vee
and Vss at every eighth device to prevent noise coupling to
the Vee line which may affect the TTL peripheral logic in
the system.
VI
"00
·eo
'60
'oD
(mAl
0
Typical power supply current waveforms versus time are
shown below for both a RAS/CAS cycle and a CAS only
cycle. 100 and lee current surges at RAS and CAS edges
make adequate decoupling of these supplies important. Due
to the high frequency noise component content of the cur·
rent waveforms, the decoupling capacitors should be low
inductance, ceramic units selected for their high frequency
performance.
It is recommended that a 0.1 IlF ceramic capacitor be con·
nected between Voo and Vss at every other device in the
memory array. A 0.1 IlF ceramic capacitor should also be
connected between Vee and V ss at every other device
(preferably the alternate devices to the VOO decoupling).
For each 16 devices, a 10 IlF tantalum or equivalent capaci·
tor should be connected between Voo and Vss near the
array. An equal or slightly smaller bulk capacitor is also
recommended between Vee and Vss for every 32 devices.
·co
"or
....,.
a Read.
I eAt ONL V CYCLE I
100 200 300.00 500
.,.
(mAl
CS low during
TYPICAL SUPPL V CURRENTS VS TIME
3-42
2104A FAMILY
gridded both horizontally and vertically at each device in
the array. This technique allows use of double-sided circuit
boards with noise performance equal to or better than
multi-layered circuit boards.
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distributio~
system on the array board should be minimized. It is
recommended that the Voo, VBB, and VSS supply lines be
,. 0"
•
B
2
-'
• °lt
• B
t
• 02
0
B
2
• °t
CAS
WE
~AS
~OB':
,-,
S
00
.
2'
!I
081t
~
..
• B ,.
!I
OOt
OECOUPLING CAPACITORS
°=
0.1 MF to Voo TO Vss
B
= 0.1 gF Vss TO Vss
C
= 0.01 MF VCC TO Vss
3-43
!!
,;-
4096
x
2104A FAMILY
1 BIT DYNAMIC RAM
2104A-4
2104A-3
2104A-1
2104A-2
Max. Acceaa Time (na)
150
200
250
300
R.ad, Write Cycle (na)
320
320
375
425
35
32
30
30
Max. IDD (mA)
Period: 2 ms
Highest Density 4K RAM Industry Stan• Refresh
• dard
16 Pin Package
On-Chip Latches for Addresses, Chip
•
Select and Data In
Low
Power
4K
RAM
• All Inputs Including Clocks TTL
Memory Expansion: Chip Select
• Simple
• Compatible
Output
is Three-State, TTL Compatible;
• Data is Latched
and Valid into Next Cycle
• Standard Power Supplies:
+12V, +5V, -5V
Compatible
with
Intel® 2116 16K RAM
•
The Intel@ 2104A is a 4096 word by 1 bit MQS RAM fabricated with N-channel silicon gate technology for high performance
and high functional density.
The efficient design ofthe 2104A allows it to be packaged in the industry standard 16 pin dual-in-line package. The 16pin
package provides the highest system bit densities and is compatible with widely available automated handling equipment.
The use of the 16 pin package is made possible by multiplexing the 12 address bits (required to address 1 of 4096 bits) into
the 2104A on 6 address input pins. The two 6 bit address words are latched into the 2104A by the two TTL clocks. Row
Address Strobe (RAS) and Column Address Strobe (CAS). Non-critical clock timing requirements allow use of the
multiplexing technique while maintaining high performance.
A new unique dynamic storage cell provides high speed along with low power dissipation and wide voltage margins. The
mem~ cell requires refreshing for data retention. Refreshing is easily accomplished by performing any RAS/CAS cycle
with CS at VIH for each of the 64 row addresses every 2 milliseconds.
The 2104A is designed for CAS-only deselect and is compatible with Intel@ 2116. 16K RAM.
PIN CONFIGURATION
LOGIC DIAGRAM
BLOCK DIAGRAM
O'N
"oUT
PIN NAMES
Ao· ...
CAS
0,.
DbuT
ADDRESS INPUTS
COLUMN ADDRESS STROBE
CHIP SELECT
DATA IN
DATA OUT
ROW ADDRESS STROBE
.ao96 BIT
+ - - V18
WE
WRITE ENABLE
V..
Vee
POWER I-SVI
-Vee
Voo
POWER 1+5VI
POWER 1+12VI
_GNO
Vss
GROUNO
STORAGE ARRAY
CLOCK
GENERATOR NO.1
3-44
- VOD
2104A FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT:
Ambient Temperature Under Bias . . . . . -10°Cto +BQoC
Storage Temperature . . . . . . . . . . . . . -65°C to +l50°C
Voltage on any Pin Relative to VBB
(Vss - VBB ;;;. 4.5V) . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation .... . . . . . . . . . . . . . . . . . .. 1.0W
Data Out Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device_ This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1]
TA
= 0° to 70°C, Voo = +12V ±10%, Vee = +5V ±10%, Vee = -5V ±10%, Vss = OV, unless otherwise noted.
Limits
Symbol
Parameter
Min.
Typ.(2)
Max.
Unit
Conditions
= VIL MIN to VIH MAX
ILl
Input Load Current (any input)
10
J.lA
VIN
IILol
Output Leakage Current for
High Impedance State
10
J.lA
Chip deselected: RAS and CAS at VIH
VOUT = 0 to 5.5V
1001 [31
Voo Standby Current
0.7
2
mA
Voo
0.7
1.5
mA
VOO
5
50
J.lA
= 13.2V
= 12.6V
Voo = 13.2V
24
35
mA
2104A-l
22
32
mA
2104A-2
IBBl
V BB Standby Current
1002[31
Operating Voo Current
leB2
Operating VeB Current
ICC1[41
VCC Supply Current when
Deselected
20
30
mA
130
325
J.lA
10
J.lA
V
VIL
Input Low Voltage (any input)
-1.0
0.8
VIH
Input High Voltage
2.4
7.0
V
VOL
Output Low Voltage
0.0
0.4
V
VOH
Output High Voltage
2.4
VCC
V
CAS and RAS at VIH.
Chip deselected prior
to measurement.
See Note 5.
= 320 ns
tRC = 320 ns
2104A-3,4
tRC = 375 ns
Min. cycle time. T A = O°C
tRC
= 3.2 mA
IOH = -5 rnA
IOL
CAPACITANCE [6] TA = 25°C
Symbol
Typ.
Max.
Unit
Cll
Input Capacitance (Ao-A5), DIN, CS
Test
3
7
pF
Conditions
VIN
CI2
Input Capacitance RAS, WR ITE
3
7
pF
VIN
Co
Output Capacitance (DOUT)
4
7
pF
CI3
Input Capacitance CAS
6
7
pF
= VSS
= VSS
VOUT =OV
VIN = Vss
Notes: 1. All voltages referenced to VSS. The only requirement for the sequence of applying voltages to the device is that VOO, VCC, and
VSS should never be O.3V or more negative than Vee. After the application of supply voltages or after extended periods of operation without clocks, the device must perform a minimum of one initialization cycle (any valid memory cycles containing both RAS
2.
3.
4.
5.
and CAS) prior to normal operation.
Typical values are for TA = 25"C and nominal power supply voltages.
The 100 current flows to VSS.
When chip is selected VCC supply current is dependent on output 10ading~C is connected to output buffer on!r;
The chip is deselected; i.e., output is brought to high impedance state by CAS-only cycle or by a read cycle with CS at VIH.
6. Capacitance measured with Boonton Meter.
3-45
2104A FAMILY
A.C.CHARACTERISTICS[1]
TA=O°C to 70°C,VDD=12V ±10%,Vcc=5V ±10%,VBB=-5V ±10%, Vss=OV,unless otherwise noted.
READ, WRITE, AND READ MODIFY WRITE CYCLES
Parameter
Symbol
2104A·l
Max.
Min.
2104A·2
Min.
Max.
2
2104A·3
Min.
Max.
2
2104A-4
Min.
Max.
2
2
tREF
Time Between Refresh
tRP
RAS Precharge Time
100
115
115
125
tcp
CAS Precharge Time
60
80
110
110
tRCL[2]
RAS to CAS Leading Edge Lead Time
20
tCRP
CAS to RAS Precharge Time
tRSH
50
25
70
35
110
80
Unit
ms
ns
ns
135
ns
a
a
0
a
ns
RAS Hold Time
100
130
140
165
ns
tCSH
CAS Hold Time
150
200
250
300
ns
tAR
RAS to Address or CS Hold Time
95
120
160
215
ns
tASR
Row Address Set-Up Time
a
0
0
ns
tASC
Column Address or CS Set-Up Time
-5
a
a
a
a
ns
tRAH
Row Address Hold Time
20
25
35
80
ns
tCAH
Column Address or C~ Hold Time
45
50
50
80
tT
Rise or Fall Time
3
50
3
50
3
50
3
50
ns
tOFF
tc,'l,Cl;JJ
tRAC l3 )
Output Buffer Turn-Off Delay
a
50
a
60
a
60
a
80
ns
ns
Access Time From CAS
100
130
140
165
ns
Access Time From RAS
150
200
250
300
ns
READ CYCLE
2104A-1
Symbol
Parameter
Min.
Max.
2104A-2
Min.
Max.
2104A-3
Min.
Max.
2104A-4
Min.
Max.
Unit
tRC
Random Read or Write Cycle TIme
320
tRAS
RAS Pulse Width
150
tCAS
CAS Pulse Width
100
130
140
165
ns
tRCS
Read Command Set-Up Time
0
Read Command Hold Time
Data Out Hold Time
a
a
a
a
a
ns
tRCH
tDOH
a
a
32
32
32
32
jJ.s
375
320
32000
200
32000
250
425
32000
300
ns
32000
ns
ns
WRITE CYCLE[4]
2104A-1
Parameter
Symbol
Min.
Max.
2104A-2
Min.
Max.
2104A-3
Min.
Max.
2104A-4
Min.
Max.
Unit
tRC
Random Read or Write Cycle Time
320
tRAS
RAS Pulse Width
150
tCAS
CAS Pulse Width
100
130
140
165
ns
twcs
Write Command Set-Up Time
a
a
0
0
ns
tWCH
Write Command Hold Time
55
75
75
80
ns
tWCR
105
145
185
215
ns
twp
Write Command Hold ,Time Referenced to RAS
Write Command Pulse Width
45
55
75
80
ns
tRWL
Write Command to RAS Lead Time
100
130
140
150
ns
tCWL
Write Command to CAS Lead Time
100
130
140
150
ns
tDS
Data-In Set-Up Time
a
0
0
0
ns
tDH
Data-I n Hold Time
55
75
75
80
ns
tDHR
Data-In Hold Time Referenced to RAS
105
145
185
215
ns
Notes:
32000
200
425
375
320
32000
250
32000
300
ns
32000
ns
1. All voltages referenced to VSS. Minimum timings do not allow for tT or skews.
2. CAS mus.!.!!'main at VIH a minimum of tRCL MIN after RAS switches to VIL. To achieve the minimum guaranteed access time
(tRAC), CAS must switch to VIL at or before tRCL of tRAC - tT - tCAC as described in the Applications Information section.
tRCL MAX is given for reference only as tRAC _ tCAC'
3. Load = 2 TTL and 100 pF. See Applications Information.
4. In a write cycle DOUT latch w.i!!...conta," data written into cell. In a read-modify-write cycle DOUT latch will contain data read
from cell. If WE goes low after CAS and prior to tCAC, DOUT is indeterminate.
3-46
2104A FAMILY
WAVEFORMS
READ CYCLE
t RC ---
---~--~
-
tRAS
V,"
(i)
RAS
V,L
~l®
.
I----'RCL-
CAS
V ,L
~H
ADDRESSES
V,L
(JJ
tASR~
~
tRSH
1\\\\ (2)
RDW
ADDRESS
.
teAP
... --tcp--
--~'cAH-~
tAse
K )(
Vt
t cAs - - - - - - - - - - - -
~
~
I--,"AH-
.,,-
-- -- 'RP--- - ---
.
II/v
tCSH-
V ,H
1-
K
COLUMN
ADDRESS
tAR
~
V 'H
es
V ,L
r--
V 'H
V
f-
t RCS
cf¥
WE
V,L
·---'cAH~
tAse
-
tACH
\
tRAC
:1-
t eAc
1-
t OFF -
VOH
~®
DOUT
HIGH IMPEDANCE
10
VOL
'OOH-
T
VALID
DATA OUT
l.
r---
WRITE CYCLE
- ---tRC
~H
RAS
~L
-
·I~'RP~
,"AS
CD ®
/'
CAS
tASR : - - -
~H
v,L
I. VI
CD 1\\\\~
.
~L
ADDRESSES
t RSH
I----'"CL-
~H
)(CD®
- - tRAH
ROW
--1
ADDRESS
tAse ~
X )(
-'cRP~"-----
.
'cSH
'cAS
.....--tcp-
!+--'cAH-
K
COLUMN
ADDRESS
IwCR
~
V'H
tAR
tAse
. . . - -tcAH------+-
V
\ I~
es
V,L
t RWL
tewL
~H
WE
~L
~'wCH~
'\ - I w c s 'wp
,@
tOHR
V'H
D'N
v,L
®tos--j-
/
-'oH~
XCD®
f(
tRAC
i 70ns.
3-49
2104A FAMILY
CHIP SELECTION/DESELECTION
Note that if 25 nsec S tRCL S 70 nsec, device access ti me is
determined by equation 3 and is equal to tRAC. If tRCL > 70
nsec, access time is determined by equation 4. This 45ns
interval (shown in the tRCL inequality in equation 3) in
which the failing edge of CAS can occur without affecting
access time is provided to allow for system timing skew in
the generation of CAS. This allowance for a tRCL skew is
designed in at the device level to allow minimum access
times to be achieved in practical designs.
WRITE CYCLE
A Write Cycle is generally performed by bringing Write
Enable (WE) low before CAS. DouT will be the data written
into the cell addressed. If WE goes low after CAS and prior
to tCAC, DO!'T will be indeterminate.
READ-MODIFY-WRITE CYCLE
The 2104A is selected by driving CS low during a Read,
Write, or Read-Modify-Write cycle. A device is deselected
by 1) driving CS high during a Read, Write, or ReadModify-Write cycle or 2) performing a CAS Only cycle
independent of the state of CS.
REFRESH CYCLES
Each of the 64 rows internal to the 2104A must be
refreshed every 2 msec to maintain data. Any data cycle
(Read, Write, Read-Modify-Write) refreshes the entire
selected row (defined by the low order row addresses).
The refresh operation is independent of the state of chip
select. It is evident, of course, that if a Write or ReadModify-Write cycle is used to refresh a row, the device
should be deselected (CS high) if it is desired not to
change the state of the selected cell.
A Read-Modify-Write Cycle is performed by bringing
Write Enable (WE) low after access time, tRAC, with RAS
and CAS low. Data in must be valid at or before the falling
edge of WE. In a read-modify-write cycle DouTis data read
and does not change during the modify-write portion of
the cycle.
RAS/CAS TIMING
The device clocks, RAS and CAS, control operation of the
2104A. The timing of each clock and the timing
relationships of-the two clocks must be understood by the
user in order to obtain maximum performance in a
memory system.
CAS ONLY (DESELECT) CYCLE
In some applications, it is desirable to be able to deselect
all memory devices without running a regular memory
cycle. This may be accomplished with the 2104A by performing a CAS-Only Cycle. Receipt of a CAS without RAS
deselects the 2104A and forces the Data Output to the
high-impedance state. This places the 2104A in its lowest
power, standby condition. 100 will be about twice 1001 for
the first cycle of CAS-only deselection and 1001 for any
additional CAS-only cycles. The cycle timing and CAS
timing should be just as if a normal RAS/CAS cycle was
be i ng performed.
RAS/CASCYClE
RM
CAs
'"
(rnA)
V," ---,
V"
v,"
V"
~[
+2:
-20
-40
-
I
CASONLYCYCLE
I
f-
\- ~
IL f-~
.A
VI
It is recommended that a 0.1 pF ceramic capacitor be connected between Voo and VSS at every other device in the
memory array. A 0.1 pF ceramic capacitor should also be
connected between V BB and Vss at every other device
(preferably the alternate devices to the Voo decoupling).
For each 16 devices, a 10 pF tantalum or equivalent capacitor should be connected between Voo and Vss near the
array. An equal or slightly smaller bulk capacitor is also
recommended between V BB and V ss for every 32 devices .
Itf-J'l
A 0.01 pF ceramic capacitor is recommended between V cc
and Vss at every eighth device to prevent noise coupling to
the VCC line which may affect the TTL peripheral logic in
the system.
+100
'80
..0
'DO
'4"[
+2: -"
- ~
'-J
f-
POWER SUPPLY
Typical power supply current waveforms versus time are
shown below for both a RAS/CAS cycle and a CAS onl'l
cycle. 100 and IBB current surges at RAS and CAS edges
make adequate decoupling of these supplies important. Due
to the high frequency noise component content of the current waveforms, the decoupling capacitors should be low
inductance, ceramic units selected for their high frequency
performance.
~
L...
.or
(mM
I
100 200 300400 500 600700 800 9001000(ns)
The RAS and CAS have minimum pulse widths as defined
by tRAs and teAS respectively. These minimum pulse
widths must be maintained for proper device operation
and data integrity. A cycle, once begun by driving RAS
and/or CAS low must not be ended or aborted prior to
fulfilling the minimum clock signal pulse width(s). A new
cycle must not begin until the minimum precharge time,
tRP, has been met.
TYPICAL SUPPLY CURRENTS VS. TIME
3-50
2104A FAMILY
Due to the high frequency characteristics of the current
waveforms. the inductance of the power supply distribution
system on the array board should be minimized. It is
recommended that the VD D• VSB. and Vss supply lines be
,B ,
DO'
gridded both horizontally and vertically at each device in
the array. This technique allows use of double·sided circuit
boards with noise performance equal to or better than
multi-layered circuit boards.
,
D ,
,
B ,
,
D,
~~~==·P~=i~·==P~~~·~p~~~·==p~~~·==.~~~.~~p~~.==~~~,..
i
i
,
'B ,
••
=
VBB
DIN
••
-,- 0
.0 's'
••
••
,
D,
'B
••
,0
••
'D'
" S"
••
••
~~~5§~VSS
vcc
DOUT
DECOUPLING CAPACITORS
D
~
B
= 0.1
C
= 0.Q1 MF VCC TO Vss
0.1 MF to VOD TO VSS
MF VBB TO Vss
3·51
inter
2104A
4096 x 1 BIT DYNAMIC RAM
2104A
Max. Access Time .(ns)
350
Read, Write Cycle (ns)
500
35
Max. 100 (mA)
Highest Density 4K RAM Industry Stan• dard
16 Pin Package
Low
Power
4K RAM
• All Inputs Including
Clocks TTL
• Compatible
Standard Power Supplies:
• +12V,
+5V, -5V
Period: 2 ms
• Refresh
On-Chip
for Addresses, Chip
• Select andLatches
Data In
Simple Memory Expansion: Chip Select
• Output
is Three-State, TTL Compatible;
• Data is Latched
and Valid into Next Cycle
Compatible
with
Intel® 2116 16K RAM
•
The Intel® 2104A is a 4096word by 1 bit MOS RAM fabricated with N-channel silicon gate technology for high performance
and high functional density.
The efficient design of the 21 04A allows it to be packaged in the industry standard 16 pin dual-in-line package. The 16 pin
package provides the highest system bit densities and is compatible with widely available automated handling equipment.
The use of the 16 pin package is made possible by multiplexing the 12 address bits (required to address 1 of 4096 bits) into
the 2104A on 6 address input pins. The two 6 bit address words are latched into the 2104A by the two TTL clocks, Row
Address Strobe (RAS) and Column Address Strobe (CAS). Non-critical clock timing requirements allow use of the
multiplexing technique while maintaining high performance.
A new unique dynamic storage cell provides high speed along with low power dissipation and wide voltage margins. The
memory cell requires refreshing for data retention. Refreshing is easily accomplished by performing any RAS/CAS cycle
with CS at VIH for each of the 64 row addresses every 2 milliseconds.
The 2104A is designed for CAS-only deselect and is compatible with Intel® 2116, 16K RAM.
PIN CONFIGURATION
LOGIC DIAGRAM
BLOCK DIAGRAM
~N
v••
Vss
Ao
D'N
CAS
A,
WE
DOUT
RAS
es
.."
A,
A,
A,
A,
As
A,
D'N
A,
A,
As
DOUT
Vee
PIN NAMES
Ao· As
CAS
cs
- VBB
409681T
ADDRESS INPUTS
WE
WAITE ENABLE
COLUMN ADDRESS STROBE
V••
POWER (-SV)
Vee
Voo
Vss
POWER (+5V)
CHIP SELECT
DATA IN
"'N
t\)UT
DATA OUT
lIAS
ROW ADDRESS STROBE
STORAGE ARRAY
- VOD
-Vee
_GND
POWER (+12V)
GROUND
CLOCK
GENERATOR NO.1
3·52
2104A
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec~
tions of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
Ambient Temperature Under Bias . . . . . -10°C to +80°C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Voltage on any Pin Relative to VBB
(Vss - VBB ~ 4.5V) . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation . . . . . . . . . . . . . • . . . . . . . . . 1.0W
Data Out Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
reliability.
D.C. AND OPERATING CHARACTERISTICS[1]
TA = o°c to 70°C, Voo = +12V ±5%, Vee = +5V ±10%, V BB = -5V ±10%, Vss = OV, unless otherwise noted.
Symbol
Parameter
Min.
Limits
Typ.[Z]
Max.
Unit
10
MA
VIN
10
MA
Chip Deselected: RAS and CAS at V IH
VOUT = 0 to 5.5V
Conditions
III
Input Load Current (Any Input)
IILOI
Output Leakage Current for
High Impedance State
1001 [3]
Voo Standby Current
0.7
2
mA
Voo = 12.6V, CAS and RAS at VIH.
IBB1
V BB Standby Current
5
50
MA
Chip Deselected Prior to Measurement. See Note 5.
100 2[3]
Operating Voo Current
25
35
mA
teye = 500 ns
IBB2
Operating V BB Current
130
400
MA
tRe
= 500ns,
lee1[4]
Vee Supply Current When
Deselected
10
MA
VIL
Input Low Voltage (Any Input)
-1.0
0.8
V
VIH
Input High Voltage
2.4
7.0
V
VOL
Output Low Voltage
0.0
0.4
V
IOL
= 2.0mA
VOH
Output High Voltage
2.4
Vee
V
IOH
=
CAPACITANCE [6]
TA
=
VIL MIN to V IH MAX
TA
-5 mA
= 25°C
Typ.
Max.
Unit
Conditions
CI1
Input Capacitance (Ao-A5), DIN, CS
3
7
pF
VIN = Vss
CI2
Input Capacitance RAS, WRITE
3
7
pF
V1N = Vss
Co
Output Capacitance (DOUT)
4
7
pF
VOUT = OV
CI3
Input Capacitance CAS
6
7
pF
VIN = Vss
Symbol
= OOG
Test
Notes: 1. All voltages referenced to VSS. The only requirement for the sequence of applying voltages to the device is that Voo, Vee, and
VSS should never be O.3V or more negative than VBB. After the application of supply voltages or after extended periods of operation without clocks, the device must perform a minimum of one initialization cycle (any valid memory cycles containing both RAS
and CAS) prior to normal operation.
2.
3.
4.
5.
Typical values are for T A = 25°C and nominal power supply voltages.
The 100 current flows to VSS.
When chip is selected Vee supply current is dependent on output loading. Vee is connected to output buffer only.
The chip is deselected; i.e., output is brought to high impedance state by CAS-only cycle or by a read cycle with CS at VIH.
6. Capacitance measured with Boonton Meter.
3·53
2104A
A.C.CHARACTERISTICS[1]
TA = O°C to 70°C, V DD = 12V ±5%, VCC = 5V ±10%,
VBB
= -5V ±10%, VSS = OV, unless otherwise noted.
READ, WRITE, AND READ MODIFY WRITE CYCLES
Symbol
2104A
Parameter
Min.
tREF
Time Between Refresh
tRP
RAS Precharge Time
150
tcp
CAS Precharge Time
150
tRCL [2J
RAS to CAS Leading Edge Lead Time
100
tCRP
CAS to RAS Precharge Time
Max.
2
Unit
ms
ns
ns
150
ns
0
ns
ns
tRSH
RAS Hold Time
200
tCSH
CAS Hold Time
350
ns
tAR
RAS to Address or CS Hold Time
250
ns
ns
tASR
Row Address Set·Up Time
0
tASC
Column Address or CS Set-Up Time
0
ns
tRAH
Row Address Hold Time
100
ns
100
tCAH
Column Address or CS Hold Time
tT
Rise or Fall Time
3
50
ns
tOFF
Output Buffer Turn-Off Delay
0
100
ns
tCAC[3J
Access Time From CAS
200
ns
tRAC[3J
Access Time from RAS
350
ns
ns
READ CYCLE
Symbol
2104A
Parameter
Min.
tRC
Random Read or Write Cycle Time
500
tRAS
RAS Pulse Width
350
200
Max.
Unit
ns
32000
ns
tCAS
CAS Pulse Width
tRCS
Read Command Set-Up Time
0
ns
tRCH
Read Command Time
0
ns
tDOH
Data Out Hold Time
32
I'S
ns
WRITE CYCLE [4]
Symbol
Notes:
2104A
Parameter
Min.
Max.
Unit
tRC
Random Read or Write Cycle Time
500
tRAS
RAS Pulse Width
350
tCAS
CAS Pulse Width
200
ns
twcs
Write Command Set-Up Time
0
ns
twCH
Write Command Hold Time
100
ns
twCR
Write Command Hold Time Referenced to RAS
250
ns
ns
32000
ns
twp
Write Command Pulse Width
100
ns
tRWL
Write Command to RAS Lead Time
200
ns
tCWL
Write Command to CAS Lead Time
200
ns
tDS
Data-In Set-Up Time
0
ns
tDH
Data-In Hold Time
100
ns
tDHR
Data-In Hold Time Referenced to RAS
250
ns
1. All voltages referenced to VSS. Minimum timings do not allow for tT or skews.
musl-!:!'main at VIH a minimum of tRCL MIN after RAS switches to VIL. To achiev~ the minimum guaranteed access time
(tRAC), CAS must switch to VIL at or before tRCL of tRAC - tT - tCAC as described in the Applications Information section.
tRCL MAX is given for reference only as tRAC _ tCAC.
3. Load = 2 TTL and 100 pF. See Applications Information.
2.
CAS
4. In a write cycle DOUT latch will contain data written into cell. In a read-modify-write cycle DOUT latch will contain data read
from cell. If WE goes low after CAS and prior to tCAC, DOUT is indeterminate.
3-54
2104A
WAVEFORMS
READ CYCLE
.
t RC -- -
145 ns.
3·57
100
2104A
Note that if 100 nsec ..; tRCL ..; 145 nsec, device access
time is determined by equation 3 and is equal to tRAC. If
tRCL> 145 nsec, access time is determined by equation 4.
This 45 ns interval (shown in the tRCL inequalitY in equation 3) in which the failing edge of ~ can occur without
affecting access time is provided to allow for system timing
skew in the generation of CAS. This allowance for a tRCL
skew is designed in at the device level to allow minimum
access times to be achieved in practical designs.
CHIP SELECTION/DESELECTION
The 2104A is selected by driving CS low during a Read,
Write, or Read-Modify-Write cycle. A device is deselected
by 1) driving CS high during a Read, Write, or ReadModify-Write cycle or 2) performing a CAS Only cycle
independent of the state of CS.
REFRESH CYCLES
Each of the 64 rows internal to the 2104A must be
refreshed every 2 msec to maintain data. Any data cycle
(Read, Write, Read-Modify-Write) refreshes the entire
selected row (defined by the low order row addresses).
The refresh operation Is independent of the state of chip
select. It is evident, of course, that if a Write or ReadModify-Write cycle is used to refresh a row, the device
should be deselected (CS high) if it is desired not to
change the state of the selected cell.
WRITE CYCLE
A Write ~cle is generally performed by bringing Write
Enable (WE) low before CAS. DouTwil1 be the data written
Into the cell addressed. If WE goes low after CAS and prior
to teAC, DouT will be indeterminate.
READ-MODIFY-WRITE CYCLE
A Read-Modify-Write Cycle is performed by bringing
Write Enable (WE) low after access time, tRAC, with RAS
and CAS low. Data in must be valid at or before the falling
edge of WE. In a read-modify-write cycle DouT is data read
and does not change during the modify-write portion of
the Cycle.
RAS/CAS TIMING
The deviee clocks, RAS and CAS, control operation ofthe
2104A. The timing of each clock and the timing
relationships of the two clocks must be understood by the
user in order to obtain maximum performance in a
memory system.
CAS ONLY (DESELECT) CYCLE
In some applications, it is desirable to be able to deselect
all memory devices without running a regular memory
cycle. This may be accomplished with the 2104A by performing a CAS-Only Cycle. Receipt of a CAS without
deselects the 2104A and forces the Data Output to the
high·impedance state. This places the 2104A in its lowest
power, standby oondition. 100 will be about twice 1001 for
the first cycle of CAS·only deselection and 1001 for any
additional CAS-onlY cycles. The cyc.!L!imJ!lg and CAS
timing should be just as if a normal RAS/CAS cycle was
being performed.
The RAS and CAS have minimum pulse widths as defined
by tRAS and teAS respectively. These minimum pulse
widths must be maintained for proper device operation
and data integrity. A cycle, once begun by driving RAS
andlor CAS low must not be ended or aborted prior to
fulfilling the minimum clock signal pulse width(s). A new
cycle must not begin until the minimum precharge time,
tRP, has been met.
m
I
'IlAS!CiU CYCLE
,
I
o;Q ONt V CYCLE
I
tJ 100 20b 300 400 600 60D 100 800 900 1000(ml
-.,
- -it f- u
VI
.,00
+i20r
l_ Jf-
t
I
+410
+60
'00
(mAl
+:
+40
POWER SUPPLY
Typical power supply current waveforms versus time are
Shown belOW for both a RAS/CAS cycle and a CAS only
cycle. 100 and IBB current surges at RAS and CAS edges
make adequate decoupling of these supplies important. Due
to the high frequency noise component content of the current waveforms, the decoupling capacitors should be low
inductance, ceramic units selected for their high frequenoy
performance.
It is recommended that a 0.1 p.F ceramic capacitor be corio
nected between Voo and Vss at every other device in the
mernory array. A 0.1 p.F ceramic capacitor should also be
connected between VaB and Vss at every other device
(preferably the alternate devices to the VoD decoupling).
For each 16 devices, a 10 p.F tantalum or equivalent capacitor should be connected between VOO and Vss near the
array. An equal or slightly smaller bulk capacitor is also
recommended between VBa and Vss for every 32 devices.
- I~ ~ I-J~
A 0.01 p.F ceramic capacitor Is recommended between Vce
and VSS at every eighth device to prevent noise coupling to
the Vce line which may affect the TIL peripheral logic in
the system.
"'"'
TYPICAL sOI'Pl Y CURRENtS Vs. TIME
3·58
2104A
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution
system on the array board should be minimized. It is
recommended that the Voo, VBB, and Vss supply lines be
gridded both horizontally and vertically at each device in
the array. This technique allows use of double-sided circuit
boards with noise performance equal to or better than
multi-layered circuit boards.
DECOUPLING CAPACITORS
D = 0.1 /IF to VDD TO Vss
B = 0.1 /IF VBB TO Vss
C = 0.01 /IF VCC TO Vss
3-59
inter
2107C FAMILY
4096·811 DYNAMIC RAM
Access Time (ns)
Read, Write Cycle (ns)
RMW Cycle (ns)
Max 100 AV (rnA)
2107C·1
150
380
450 35
2107C·2
200
400
500
33
2107C
250
430
550
30
2107C·4
300
470
590
30
•
Direct Replacement for Industry
Standard 2~·Pin 4K RAMs
•
:!: 10% Tolerance on all Power
Supplies
•
•
•
Low Operating Power
•
Output is Three·State and TTL
Compatible
•
TTL Compatible - All Address, Data,
Write Enable, Chip Select Inputs
•
Refresh Period 2 ms
•
Low Standby Power
Only One High Voltage Input SignalChip Enable
150 ns Access Time
The Intel® 2107C is a 4096-word by l-bit dynamic n-channel MOS RAM. It was designed for memory appHcations where
very low cost and large bit storage are important design objectives. A new unique dynamic storage cell provides high speed
and wide operating margins. The 21 07C uses dynamic circuitry which reduces the standby power dissipation.
Reading information from the memory is non-destructive. Refreshing is most easily accomplished by performing one read
cycle on each of the 64 row addresses. Each row address must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic one or a logic zero.
The 2107C is fabricated with n-channel silicon gate technology. This technology allows the design and production of high
performance, easy to use MOS circuits and provides a higher functional density on a monolithic. chip than other MOS technologies. The 21 07C is a replacement for the 2107 A, 21 07B and other industry standard 22-pin 4K RAMs.
PIN CONFIGURATION
2107C
VBB
LOGIC SYMBOL
2107C
A8
A,O
A7
A11
A6
AO
A,
A2
A3
DIN
DOUT
Ao
A5
A,
A4
A2
A3
VCC
WE
cs
DIN
DATA OUTPUT
NC
A3
Ao
DOUT
Aa
l50uT
CE
cs
A2
A4
Ag
AlO
A11
PIN NAMES
VBS
VCC
CHIP SELECT
Voo
DATA INPUT
Vss
Ao-A11
DIN
Ao
A6
A7
vec
A,
A4
Voo
CE
NC
Co
Voo
Ao
Vss
Ag
BLOCK DIAGRAM
ADDRESS INPUTS·
CHIP ENABLE
WI!
CE
CE WE
POWER (-5V)
POWER (+5V)
POWER (+12V)
GROUND
WRITE ENABLE
AS
NOT CONNECTED
*Refresh Address AO-AS.
3-60
A7
As Ag A10 An
2107C FAMILY
Absolute Maximum Ratings·
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _10°C to BO°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6SoC to +1S0oC
Voltage on any Pin Relative to Vss (Vss - Vss ;;;.4.S1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.00W
'COMMENT:
Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. and Operating Characteristics
TA =
aOc to 70°C,
Voo = +12V ±10%, VCC = +SV ±10%, Vss[l] = -SV ±10%, Vss = OV, unless otherwise noted.
Limits
Symbol
Parameter
Conditions
Unit
Min.
Typ,l2]
Max.
Input Load Current (all inputs except CEI
10
j.LA
VIN = OV to VIH MAX
CE = VILC or VIHC
ILC
Input Load Current, CE
2
j.LA
VIN = OV to VIHC MAX
IILOI
Output Leakage Current for high
impedance state
10
j.LA
CE = VILC or CS = VIH
Vo = OV to S.5V
1001[3]
VDD Supply Current - standby [3]
20
200
j.LA
CE = -1V to +0.6V
24
35
mA
2107C·1, tCYC = 3BO
22
33
mA
2107C·2, tCYC = 400
20
30
mA
2107C,
20
30
mA
2107C·4, tCYC = 470
10
j.LA
CE = VILC or CS = VIH
5
50
j.LA
CE = -1 V to +0.6V
100
400
j.LA
Min. cycle time, Min. tCE
-1.0
O.B
V
III
IDDAV
Average VDD Current - operating
ICCI [3,4]
V cc Supply Current - standby
ISSI
Vss Supply Current - standby
Iss AV
Average Vss Current - operating
VIL
Input Low Voltage
tCyc= 430
VIH
Input High Voltage
2.4
VCC+1
V
VILC
CE Input Low Voltage
-1.0
+1.0
V
VIHC
CE Input High Voltage
VDo-1
Voo+1
V
VOL
Output Low Voltage
0.0
0.40
V
IOL = 3.2 mA
VOH
Output High Voltage
2.4
Vcc
V
IOH = -2.0 mA
!
NOTES:
1. The only requirement for the sequence of applying voltage to the device is that VOO, VCC, and VSS should never be O.3V or more nega.
tlve than VSS.
2. Typical values are for TA = 25°C and nominal power supply voltages.
3. The IDO and ICC currents flow to VSS.
4. During CE on VCC supply current is dependent on output loading. VCC is connected to output buffer only.
3·61
2107C FAMILY
A.C. Characteristics [1]
T A = o°c to 70°C, VDD = 12V ±10%, VCC = 5V ±10%, VBB = -5V ±10%, Vss = OV, unless otherwise noted.
READ, WRITE, AND READ MODIFY!WRITE CYCLE
--2107C·l
Symbol
2107C·2
2107C
2107C·4
Units
Parameter
Min.
tREF
Time Between Refresh
tAC
Address to CE Set· Up Time
tAH
Address Hold Time
tcc
tT
CE Off Time
tCD
CE Off to Output Disable Time
Max
Min.
Max.
2
Min.
Max.
2
Min.
2
2
ms
0
0
0
0
ns
50
50
100
100
ns
130
CE Transition Time
130
130
40
30
30
2107C·l
2107C·2
40
40
30
2
ns
130
40
Note
Max.
30
ns
ns
3
Units
Note
ns
3
READ CYCLE
Symbol
2107C
2107C·4
Parameter
Min.
tCY
Cycle Time
380
tCE
CE On Time
210
Max.
Min.
Max.
400
4000
Min.
Max.
430
230
4000
260
Min.
Max.
470
4000
300
4000
ns
280
300
ns
ns
tco
CE Output Delay
130
tACC
tWL
Address to 0 utput Access
150
CE toWE
0
0
0
0
ns
twc
WEtoCE On
0
0
0
0
ns
180
200
230
250
4
5
WRITE CYCLE
2107C·l
Symbol
2107C·2
2107C
2107C·4
Parameter
Min.
Max.
Min.
Min.
Max.
Min.
4000
300
Note
ns
3
Cycle Time
380
tCE
CE On Time
210
tw
WE to CE Off
CEtoWE
125
125
125
175
ns
tcw
150
150
150
200
ns
tDW
DIN to WE Set·Up
0
0
0
0
ns
tDH
twp
DIN Hold Time
WE Pulse Width
0
0
0
0
ns
50
50
50
100
ns
tWD
WE to Output Disable Time
15
15
15
15
Test
4000
430
Units
Max.
tCY
Symbol
400
Max.
230
4000
Plastic and
Ceramic Package
Typ.
260
470
Unit
4000
ns
Conditions
Max.
CAD
Address Capacitance, CS, DIN
5
7
pF
VIN = VSS
CCE
CE Capacitance
10
15
pF
COUT
Data Output Capacitance
5
7
pF
VIN = Vss
VOUT=OV
8
pF
VIN = Vss
WE Capacitance
6
CWE
NOTES:
1. After the application of supply voltages or after extended
periods of operation without CE, the device must perform a
6. If WE is low before CE goes high then DIN must be valid
when CE goes high.
minimum of one initialization cycle (any valid memory cycle
7. Capacitance measured with Boonton Meter or effective capa-
or refresh cycle) prior to normal operation.
citance calculated from the equation:
2. tAC is measured from end of address transition.
3. IT
= 20 ns.
C = ~ with the current equal to a constant 20 mAo
4. CLOAD = 50 pF, Load = One TTL Gate, Ref = 2.0V.
5. tACC
= tAC + tco
+ 1IT·
6
t:.V
3·62
2107C FAMILY
Read and Refresh Cycle
.
V,H
ADDRESS
ANDeS
V,L
)
1
'CY
®
ADDRESS STABLE
®
I------'AH~
~
[1]
K
-I
ADDIRESS STAB LE
ADDRESS CAN CHANGE
-
'CE
-
'T-_
-'T
r--
®
CE
0
I
1\
II
-'CC~
---j
WE CAN
CHANGE
~I-'WC
I
--',
.
'co
®
I
HIGH
IMPEDANCE
VALID)
\:
I.
~
\
-f+
,,--k
-
Write Cycle
V,H
ADDRESS
ANDes
V,L
=x
~'WL
::Lf+
tACC
MeAN
CHANGE
HIGH
/
IMPEDANCE
\
"-'CD
~
'Cy
0
0
ADDRESS STABLE
K
ADbRESS STA BLE
ADDRESS CAN CHANGE
~tAH~
~
itT
tCE
tAC- ~
:---
tT-
r--
®
CE
1\
II
0
'w--~
I'
,cw-i=~
II
I----tcc-··-
twP~
~
WE CAN CHANGE
~
DIN CAN CHANGE
V
I---tow
~
I
I
--i-
Dour
VOL
NOTES: 1.
2.
3.
4.
5.
6.
HIGH
IMPEDANCE
/
\
fNOEFINED \
tOH
K
DIN STABLE
D,N
I
CAN CHiNGE
I
!---two-I
VOH
I
WE CAN CHANGE
HIGH
IMPEDANCE
200
N
PSB = Standby power dissipation = Voo x 1001 + IVBB I x IBB
Note that 1002 depends upon refresh as follows:
'DO
r--
50
1. For (RAS before CAS) use 1002 from Figures 1 and 2.
2. For (CAS before RAS) multiply 1002 determined in (1) by 0.96.
0
'DO
75
3. For (RAS only) multiply 1002 determined in (1) by 0.78.
TEMPERATURE (DC)
Figure 1.
Examples of typical calculations for VBB = -5.0V, Voo = 12.0V,
1002 VS. CYCLE TIME
60
50
"!c:
/
T = 25
\~\
40
V'\
.P
READ
CYCLE
30
.
0
~,
tREF = 2000
f.J.S:
'\
2. 64 cycle (CAS before RAS); POP = 12.0V x 43 (0.96) mA =
495 mW .
"'~RPW =550n.
t-,;it~ ~
0425
0.425
PREF=495 (64 2000) + (12x1.2+5xO.001) (1-64 2'000)=
~
~
'1 I ~
400
f.J.S.
PREF = 28.0 mW
WRITE
CYCLE
tRPW :: 300ns
20
tRAS = 0.3
0.425
0.425
PREF = 516 (128 2000) + (12x1.2+5xO.001) (1-128 2000)
Vee = -s.ov
CYCLE
f.J.S,
1. 128 cycle (RAS before CAS): POP = 12.0V x 43 mA = 516 mW
1=,2bv
V DD
WR1ITE
,
T A = 25°C, tCYC = 0.425
500
600
700
PREF = 20.9 mW
"
800
~-
3. 128 cycle (RAS only): POP = 12.0V x 43 (0.78) mA = 402 mW
900 1000
PREF = 25.0 mW
T CYCLE (ns)
Figure 2.
rL
RAS
CAS
I
l J
rL
r
I--
rl
'50
75
100
(rnA)
..
'
NOT
~
M
IV
~ II.
rL
rL
I--
i'--
~ 1M
~ \
J
n
A,
IN
""\
~
IJ
\ r
~ )~
I
rrL
-
1\
JV \
n
IV i~
r--
AM
AJ\
A~ .• I\
"I .A
IV lJ J \
+60
(rnA)
0
4~
"L"
,V
An
J\llM
.1\/\
V
A 11M
'II
v
600
(ns)
V
IV \
'V
! - - - - f------- f------- 1 - - ..
·60
400
600 (ns)
READ CYCLES
200
400
600 (nsl
200
400
CAS BEFORE RAS
(FOR 64 CYCLE REFRESH)
READ-MODIFY-WRITE
Note 1, Increase 10 current due to WE gomg low. Width of thiS
current pulse IS Independent of WE pulse Width.
Figure 3. Supply Current Waveforms.
3·67
400
RASONlV REFRESH
600
(ns)
2108-2 AND 2108-4
A.C. CHARACTERISTICS 11)
T A=O°C to 70°C, VOO=12V ±10%, VCC=5V ±10%, VBB=-5V ±10%, VSs=OV, unless otherwise noted.
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
Symbol
2108-2
Min.
Max.
Parameter
Min.
21084
Max.
tRP
~ Precharge Time
75
95
ns
tcp
CAS Precharge Time
100
125
ns
RAS to CAS Leading Edge Lead Time
tCRP[3]
CAS to RAS Precharge Time
tRSH
45
75
2
ms
tREF
tRCL[2]
2
Unit
Time Between Refresh
60
110
ns
0
0
ns
RAS Hold Time
160
220
ns
tCSH
CAS Hold Time
200
300
ns
tASR
Row Address Set·Up Time
0
0
ns
-10
-10
ns
45
60
tASC
Column Address Set·Up Time
tAH
Address Hold Time
tT
Transition Time (Rise and Fall)
tOFF
Output Buffer Turn Off Delay
50
0
60
0
ns
50
ns
80
ns
tCAC [4]
Access Time Fr.om CAS
125
190
ns
tRAC[4]
Access Time From RAS
200
300
ns
READ AND REFRESH CYCLES
Symbol
Parameter
2108-2
Min.
Max.
21084
Min.
Max.
425
Unit
tcVC[5]
Random Read Cycle Time
350
tRAS
RAS Pulse Width
275
32000
330
32000
ns
tCAS
CAS Pulse Width
125
3000
190
3000
ns
tCH
CAS Hold Time for RAS·Only Refresh
30
30
tCPR
CAS Precharge for 64 Cycle Refresh
30
30
ns
tRCH
Read Command Hold Time
20
20
ns
tRCS
Read Command Set·Up Time
tOOH
Data·Out Hold Time
ns
ns
0
0
ns
32
32
!1S
WRITE CYCLE
Symbol
Parameter
2108-2
Min.
Max.
Min.
425
2108-4
Max.
Unit
tcvC[5]
Random Write Cycle Time
350
tRAS
RAS Pulse Width
275
32000
330
32000
ns
tCAS
CAS" Pulse Width
125
10000
190
10000
ns
tWCH
Write Command Hold Time
75
100
ns
twp
Write Command Pulse Width
50
100
ns
tRwL
Write Command to RAS Lead Time
125
200
ns
tcwL
tDS[6]
Write Command to CAS Lead Time
100
160
ns
0
0
ns
tDH I6J
Data·]n Hold Time
100
125
ns
Data·ln Set·Up Time
ns
Notes: 1. All voltages referenced to VSS.
2. CAS must remain at VJH a minimum of tRCL MIN after RAS switches to VIL. To achieve the minimum guaranteed access time
(tRAC), CAS must switch to VI L at or before tRCL (MAX) = tRAC -tCAC. Device operation is not guaranteed for tRCL>2 ",5.
3. The tCRP specification is less restrictive than the tCRL range which was specified in the 2108 preliminary data sheet.
4. Load = 1 TTL and 50 pF.
5. The minimum cycle timing does not allow for tT or skews.
6. Referenced to CAS or WE, whichever occurs last.
3·68
2108-2 AND 2108-4
WAVEFORMS
REAO CYCLE
·1
I----- t RP ------1
tCYC
tRAS
0)
.
0)
tASA
ADDRESSES
V,L
I---
~
[-
I---t'H~
ROW
ADDRESS
K X
tASH
f\\\\
teAs
(J)
V
_t'H~
'ASC
~
COLUMN
ADDRESS
t:lt
[- t RCS
~
.
teRP ---+-
~'ep~1
tCSH
~tReL--~
IIH
r---
'I
~&
tRAC
'oFF -
1\
~
1-:--------- teAc
RCH
'DOH~
.. 0
0
J
CD
C
VALID
DATA OUT
WRITE CYCLE
.
V ,H
AAS
tCYC
l-tR~
~ f+- tc RP ---+-
tRAS
CD 1"10
V'L
tCSH
I------- t ACl -------------CAS
v,L
tASR
V,H
ADDRESSES
V'L
-r--
XD0
..---t AH - -
ROW
ADDRESS
fAse -
)
'ep
tRSH
eD ~\\
v,H
~~.------
'CAS
----
t---- t AH - - - - -
1-+
~
COLUMN
ADDRESS
·1
t RWl
V,H
WE
v,L
I, ~ t WeH'ewL
0
twp
®
,s~
_~tos
V,H
D'N
V'L
t--- V
:1
.y
I
tOH-j
j(
XeD0
tRAC
tOfF~
VOH
DoUT
Notes:
VOL
teAc
~0
.r-
1,2. VIH MIN and VIL MAX are reference levels for measuring timing of input signals.
3,4.
5.
6.
7.
VOH MIN and VOL MAX are reference levels for measuring timing of 00UT.
00UT follows 01 N when writing, with WE before CAS.
Referenced to CAS or WE, whichever occurs last.
tOFF is measured to lOUT'; IILOI.
3-69
®
J
2108·2 AND 2108·4
A.C. Characteristics
oOc to 70°C, Voo = 12V ±10%, Vcc = 5V ±10%, VBB = -5V ±10%, Vss = OV, unless otherwise noted.
TA =
READ-MODIFY-WRITE CYCLE
2108-2
Min.
Max.
2108-4
Min.
Max.
tRMW
Read·ModifyWrite Cycle Time
400
595
tCRW
RMW Cycle CAS Width
225
3000
tRRW
RMW Cycle RAS Width
325
32000
Symbol
Parameter
Unit
ns
350
3000
ns
500
32000
ns
tRWH
RMW Cycle RAS Hold Time
250
390
tCWH
RMW Cycle CAS Hold Time
300
460
ns
tRwL
Write Command to RAS Lead Time
125
200
ns
tCWL
Write Command to CAS Lead Time
100
160
ns
twp
Write Command Pulse Width
50
100
ns
tRCS
Read Command Set·Up Time
0
tMOO
Modify Time
0
tos
Data·ln Set·Up Time
tOHM
Data-In Hold Time (RMW Cycle)
ns
0
10
ns
0
10
/-LS
0
0
ns
50
125
ns
Waveforms
READ MODIFY WRITE CYCLE
.
.
tAMW
~=tR'
tRRW
RAS
V ,H
VIL
CD
.
- tAcL - - - - V ,H
CD
CAS V IL
tASA ~---------JI
~IH
XCD
IL
ADDRESS
K ){
~tcp
I'L-
1~-tAH
- tCWL - - - - - - - - .
j(
COLUMN
ADDRESS
(3)
tRcsl-1
WE ~lH
IL
_tw,v
®CDJ
.
tM00J:f~tDS @
[XCDDATA IN
tRAC
VALID
.
®
t eAc
tOFF--1
®
HIGH
IMPEDANCE
¥
Notes
_____
tCRW
t RWH
t---tRWL~
lASer
ROW
tCWH
~\\\ (3)
r-- tAH
AODRESSES
i
I-tCR'-~
®
01
0"
VALID
DATA OUT
1.2. VI HMI N and VI LMAX are reference levels for measuring timing of input signals.
3.4. VOHMIN"and VOLMAX are reference levels for measuring timing of 00UT.
5. tOFF is measured to lOUT" ILO .
6. Referenced to CAS or WE, whichever occurs last.
3-70
tOHM
X
2108-2 AND 2108-4
Refresh Cycle Waveforms
CAS BEFORE RAS CYCLES. (64 CYCLE REFRESH)
r------
----tRP
v'"------~
RAS
CAS
IASR
~~~:E:E_S X~·~:~
_
.....
..
___
X~:;....J'--______________...X'_~__
V_A_LI_D_ _ _ _
V_A_LlD
_ __
I
ALL OTHER INPUTS DON'T CARE
RAS ONLY CYCLES (128 CYCLE REFRESH)
~--I
!--I
------tCYC----------~
·1
-- tRAS
'
~IRP--_
V'" ------~0~
RAS
v"
'C"
v,"
CAS'
v"
'ASR
r--
X':0®,,:X
~.~:ESSES
v,"
VALID
x
VALID
. .-'-lo....------
V,, _ _ _L..~~----....;;_~lo....----------------
Notes: 1,2. VI HMI N and VI LMAX are reference levels for measuring timing of Input signals.
3.
CAS must be high or low as appropriate for the next cycle.
Applications Information
The 2108 may be refreshed in any of three modes: read
cycles with RAS before CAS timing as shown on page 5,
RAS only cycles (page 7), or CAS before RAS cycles (page
7). In all three modes A6 must be held high for the S1572
and S1627 or low for the S1573 and S1626. The row
addressed by Ao through As is refreshed. Therefore, 64
cycles are required to refresh the stored data.
The CAS-before-RAS mode is useful in the 2116 as a
technique for increasing memory availability and minimizing standby power dissipation by requiring only 64 refresh
cycles every 2 ms. Systems employing the 2108 in a CASbefore-RAS refresh mode can be easily upgraded to the
most efficient 16K RAM capability.
Since the 2108 input pin A6 supplies two system addresses
(A6 and A13) to the internal memory array, it is not possible
to simply tie this input high or low. The 2108 input A6
must be tied to the appropriate level only during row address
strobe (RAS) and then used to supply the high order sys·
tem address Al3 during column address strobe (CAS).
Control of A6 in a system may be implemented. as shown
at right. In this circuit the output A6 of multiplexer M
supplies the appropriate high or low level (determined by
S1572, S1627, S1573, or S1626) during RAS for both a
memory cycle and refresh cycle. During CAS, system
address Al3 is multiplexed on A6 as shown. See the 2116
section for additional applications information.
ROW
ENABLE
3242
t5V
FOR 51572 OR
FOR 81573 OR
I-------Ag
1-------'"
I-I-========:Ai ~~MORY
JI3
1------1\4
"f
i
REFRESH E N A B L E - - - * - - - - - - - '
3·71
r - - - - 5 --,
I
S1627~'»-+-_UII~--+f.-L..~
S1626~,
ARRAY
I
I
2108-2 AND 2108-4
POWER SUPPLY DECOUPLINGI
DISTRIBUTION
OUTPUT DATA LATCH
The 2108 contains an output data latch eliminating the need
for an external system data latch and the timing circuitry
required to strobe an external latch. The output latch
operates identically to the 16-pin 4K RAM (Intel 2104)
output latch enhancing the system compatibility of the 16K
and 4K devices.
Power supply current waveforms for the 2108.are shown in
Figure 3. The VDD supply provides virtually all of the
operating current for the 2108. The VDD supply current,
I DD, has two components: transient current peaks when the
clocks change state and a DC component while the clocks are
active (low). When selecting the decoupling capacitors for
the VDD supply, the characteristics of capacitors as well as
the current waveform must be considered. Suppression of
transient or pulse currents require capacitors with small
physical size and low inherent inductance. Monolithic and
other ceramic capacitors exhibit these desirable characteristics. When the current waveform indicates a DC component, bulk capacity must be located near the current load to
supply the load power. Inductive effects of PC board traces
and bus bars preclude supplying the DC component from
bulk capacitors at the periphery of a memory matrix without
voltage droop during the active portion of a memory cycle.
This means that some bulk capacity in the form of electrolytic or large ceramic capacitors should be distributed around
or within the memory matrix.
Operation of the output latch is controlled by CAS. The data
output will go to the high-impedance state immediately
following the CAS leading edge during each data cycle and
will either go to valid data at access time on selected devices
(devices receiving both RAS and CAS) or will remain in the
high impedance state on unselected devices (devices
receiving only CAS). During RAS-only refresh cycles, the
data output remains in the state it was prior to the RAS-only
cycle. This unique feature of latched output RAMs allows a
refresh cycle to be hidden among data cycles without
impacting data availability. For instance, a RAS-only
refresh cycle could follow each data cycle in a
microprocessor system but the accessed data would
remain at the device output and the microprocessor could
take the data at any time within the cycle. Non-latched
output devices do not provide this type of hidden refresh
capability since their data output would go to the high
impedance state at the end of the data cycle.
The VBB supply current, I BB, has high transient current
peaks, with essentially no DC component (less than 400
microamperes). The VBB capacitors should be selected for
transient suppression characteristics. The following capacitance values and locations are recommended for the
2108:
1. A 0.33 IlF ceramic capacitor between VDD and Vss
(ground) at every other device.
2. A 0.1 I'F ceramic capacitor between VBB and Vss at every
other device (preferably alternate devices to the Voo
decoupling above).
3. A 4.7 I'F electrolytic capacitor between Voo and Vss for
each eight devices and located adjacent to the devices.
The Vee supply is connected only to the 2108 output buffer
and is not used internally. The load current from the Vee
supply is dependent only upon the output loading and is
usually only the input high level current to a TTL gate and
the output leakage currents of any OR-tied 2108 (typically
100 I'A or less total). Intel recommends that a 0.1 or 0.01 I'F
ceramic capacitor be connected between Vee and Vss for
every eight devices to preclude coupled noise from
affecting the TTL devices in the system.
Intel recommends a power supply distribution system such
that each power supply is grided both horizontally and
vertically at each memory device. This technique minimizes
the power distribution system impedance and enhances the
effect of the decoupling capacitors.
3-72
inter
2109 FAMILY
8,192 x 1 BIT DYNAMIC RAM
2109-3
2109-4
86000,86001 86002,86003
200
250
375
410
Maximum Access Time (ns)
Read, Write Cycle (ns)
Read-Modify-Wrlte Cycle (ns)
375
_ 8K RAM, Industry Std. 16-Pin Package
_
_ ±10% Tolerance on All Power Supplies:
_
+12V, +SV, -SV
_ Low Power: 462mW Max. Operating,
_
20mW Max. Standby
_
- Low IDD Current Transients
_
_ All Inputs, Including Clocks, TTL Compatible
475
Non-Latched Output is Three-State,
TTL Compatible
RAS Only Refresh
64 Refresh Cycles Required Every 2ms
Page Mode Capability
CAS Controlled Output
Allows Hidden Refresh
The Intel® 2109 is a 8,192 word by 1-bit Dynamic MOS RAM which is pin compatible with the industry standard 16K
dynamic RAMs. The 2109 is manufactured with the same masks as the Intel® 2117 and is fabricated with Intel's standard
two layer polysilicon NMOS technology - a production proven protess for high reliability, high performance, and high
storage density. As is shown in the block diagram below, the device is organized as two 8K arrays separated by sense
amplifiers and column decoders. The selected 8K array is tested for all of the A.C. and D.C. characteristics necessary to
permit the 2109 to be considered a functionally compatible 8K version of the 16K device.
The 2109 uses a single transistor dynamic storage cell and advanced dynamic circuitry to achieve high speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients and ±10% tolerance on all power supplies contribute to the high noise immunity of the 2109 in a system
environment.
The 2109 is available as either an "upper" or "lower" half of the 2117. Row Address 6 (As) selects the operating half, and is
VIH for 86000, S6002, S6064 and S6066 specifications and As is VIL for S6001, S6003, S6065 and S6067 specifications.
The 2109 three-state output is controlled by Column Address Strobe (CAS) independent of Row Address Strobe (RASl.
After a valid read or read-modify-write cycle, data is latched on the output by holding CAS low. The data out pin is returned
to the high impedance state by returning CAS to a high state. The2109 hidden refresh feature allows CASto be held lowto
maintain latched data while RAS is used to execute RAS-Only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RASOnly refresh cycles, hidden refresh cycles, or normal read or write cycles on the 64 row address combinations of Ao
through As. A6 must be at its proper state (VIH or VIL depending on the device specification) for 64 cycle refresh. A write
cycle will refresh stored data on all bits of the selected row except the bit which is addressed.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
Ao
A,
A,
D,N
A,
A,
A5
A, Dour
RAS
CAS
Vss
CAS
A,
DOUT
WE
NOTE 1: 86000.86002: A6 AT VIH DURING ROW ADDRESS VALID
86001.86003, A. AT VIL DURING ROW ADDRESS VALID
PIN NAMES
Ao-As
ADDRESS INPUTS
WE
WRITE ENABLE
CAS
COLUMN ADDRESS STROBE
V"
POWER (-5VJ
D,N
DATA IN
Vee
POWER (+5V)
DOUT
DATA OUT
VDD
POWER (+12V}
RAS
ROW ADDRESS STROBE
Vss
GROUND
CAS-===:=J
~===============~----~
D,N
3-73
2109 FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT:
Ambient Temperature Under Bias ... -10° C to +80°C
Storage Temperature ............. -65° C to +150° C
Voltage on Any Pin Relative to VBB
(VSS-VBB24V) ..................... -0.3Vto+20V
Data Out Current ............................ 50mA
Power Dissipation ........................... 1.0W
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating onlv and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1.2j
TA
= ooe
Symbol
to
7o oe,
VDD
= 12V ±10%,
Vee
Parameter
= 5V
±10%, Vss
= -5V
±10%, VSS
= OV,
unless otherwise noted.
Limits
Min. Typ.l31 Max. Unit Test Conditions
IILlI
Input Load Current (any input)
0.1
10
!J.A VIN=VSS to 7.0V, VBB=-5.0V
IILOI
Output Leakage Current for
High Impedance State
0.1
10
Chip Deselected: CAS at VIH,
!J.A VOUT = 0 to 5.5V
_.
Notes
4
1001
VOD Supply Current, Standby
1.5
mA CAS and RAS at VIH
IBBI
VBB Supply Current, Standby
1.0
50
!J.A
ICCI
Vce Supply Current. Output
Deselected
0.1
10
35
!J.A CAS at VIH
mA 2109-3, tRe = 375ns, tRAS = 200ns
4
33
mA 2109-4, tRC = 410ns, tRAS = 250ns
4
1002
I Voo Supply Current, Operating
IBB2
VBB Supply Current, Operating,
RAS-Only Refresh, Page Mode
1003
Voo Supply Current, RAS-Only
Refresh
150
1.5
300
!J.A TA = O°C
27
mA 2109-3, tRe = 375ns, tRAS = 200ns
4
26
mA 2109-4, tRe = 410ns, tRAS = 250ns I
4
1005
Voo Supply Current, Standby,
Output Enabled
VIL
Input Low Voltage (all inputs)
-1.0
0.8
V
VIH
Input High Voltage (all inputs)
2.4
6.0
V
VOL
Output Low Voltage
VOH
Output High Voltage
3
0.4
2.4
5
mA CAS at VIL. RAS at VIH
V
IOL = 4.2mA
4
V
IOH = -5mA
4
NOTES:
1. All voltages referenced to Vss.
2. No power supply sequencing is required. However, VOD, Vee and Vss should never be more negative than -O.3V with respect to VBB as
required by the absolute maximum ratings.
3. Typical values are for TA = 25°C and nominal supply voltages.
4. See the Typical Characteristics Section for values of this parameter under alternate conditions.
5. lee is dependent on output loading when the device output is selected. Vee is connected tothe output buffer only. Vee may be reduced
to Vss without affecting refresh operation or maintenance of internal device data.
3-74
2109 FAMILY
TYPICAL SUPPLY CURRENT WAVEFORMS
~/=
LONG~/=
RASONLVREFRESH
: ~E l I i I I I 1 I ! I j I 1 I I PI I ! I I
125
II~
100
100
(mAl
75
50
25
J
/'I.
1\
V\
\"-~
1
I~
l
Jk
I
75
50
1\
25
I••
(rnA)
A
0
~
- 25
- 50
, "I
r
It
A
1J
V
II,
I"'
'I
"V
~
A
1.
,j
f
A
~\
"
."
I
I
-76
125
100
IsS
(mAl
1\
75
rt
50
III
25
o
o
J
J\
V
100
~
200
J ~
300
400
500
TIME(ns)
moo
I I
100
200
300
400
500
600
700
800
J
1111
I
J
100
900
....
I-200
V"
300
= 25°C,
Symbol
Voo
500
The effects of cycle time, Voo supply voltage and ambient
temperature on the 100 current are shown in graphs
included in the Typical Characteristics Section. Each
family of curves for IDOl, 1002, and 1003 is related by a
common point at Voo = 12.0V and TA =25°Cfortwo given
tRAS pulse widths. The typical 100 current for a given
condition of cycle time, Voo and TA can be determined by
combining the effects of the appropriate family of curves.
CAPACITANCE 11]
TA
400
TlME(ns)
TlME(ns)
Typical power supply current waveforms vs. time are
shown for the RAS/CAS timings of Read/Write, Read/
Write (Long RAS/CAS), and RAS-only refresh cycles. 100
and Iss current transients at the RAS and CAS edges
require adequate decoupling of these supplies. Decoupling recommendations are provided in the Applications
section.
V
= 12V±100f0, Vee = 5V±100f0, VBB = -5V±100f0, Vss = OV,
Parameter
unless otherwise specified.
Unit
Typ.
Max.
Cll
Address, Data In
3
5
pF
CI2
RAS Capacitance, WE Capacitance
4
7
pF
CI3
CAS Capacitance
6
10
pF
Co
Data Output Capacitance
4
7
pF
NOTES:
1. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation:
C ; I.lt with j,V equal to 3 volts and power supplies at nominal levels.
j,V
3-75
2109 FAMILY
A.C. CHARACTERISTICS[1,2,3]
TA
= ooe
to
7o oe,
Voo
= 12V ±10%,
Vcc
= 5V
±10%, VBB
= -5V
±10%, Vss
= OV,
unless otherwise noted.
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
5ymbol
2109·3
56000,56001
Min.
Max.
Parameter
2109-4
56002,56003
Max.
Min.
Access Time From RAS
200
250
tCAC
Access Time From CAS
tREF
Time Between Refresh
135
2
165
2
tRAC
tRP
RAS Precharge Time
tCPN
tCRP
CAS Precharge Time Inon-page cycles)
CAS to RAS Precharge Time
120
25
-20
25
135
65
tRCD
RAS to CAS Delay Time
tRSH
RAS Hold Time
tCSf-I
CAS Hold Time
tASR
Row Address Set-Up Time
200
0
tRAH
Row Address Hold Time
tASC
Column Address Set-Up Time
tCAH
Column Address Hold Time
tAR
Column Address Hold Time, to RAS
tT
Transition Time (Rise and Fall)
120
3
tOFF
Output Buffer Turn Off Delay
0
50
60
375
200
135
10000
10000
150
25
-20
35
Unit
Notes
ns
4,5
4,5,6
ms
ns
ns
ns
ns
85
ns
165
ns
250
ns
25
0
35
ns
-10
-10
ns
55
75
ns
160
3
7
ns
ns
0
50
70
410
250
10000
165
10000
ns
8
ns
READ AND REFRESH CYCLES
tRC
Random Read Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
tRCS
Read Command Set-Up Time
tRCf-I
Read Command Hold Time
0
0
ns
ns
ns
0
ns
0
ns
WRITE CYCLE
tRC
Random Write Cycle Time
375
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
200
135
twcs
Write Command Set-Up Time
tWCH
Write Command Hold Time
410
ns
10000
250
10000
ns
10000
165
10000
ns
ns
-20
55
120
-20
75
160
ns
75
ns
100
100
ns
0
75
160
ns
tWCR
Write Command Hold Time, to RAS
twp
Write Command Pulse Width
tRWL
Write Command to RAS Lead Time
tCWL
Write Command to CAS Lead Time
tDS
Data-In Set-Up Time
tDH
Data-In Hold Time
55
80
80
0
55
tDHR
Data-In Hold Time, to RAS
120
9
ns
ns
ns
ns
READ-MODIFY-WRITE CYCLE
tRWC
Read-Modify-Write Cycle Time
tRRw
RMW Cycle RAS Pulse Width
375
245
10000
tCRw
RMW Cycle CAS Pulse Width
180
10000
tRWD
RAS to WE Delay
160
230
200
95
125
tCWD
CAS to WE Delay
Notes: See following page for A.C. Characteristics Notes.
3-76
475
305
ns
10000
10000
ns
ns
ns
9
ns
9
2109 FAMILY
WAVEFORMS
- - - - - - - - - - - - tRC
READ CYCLE
,H
-
---------
1-------------..--- ------------ tRAS -~--.. ------
_ _ _ _ _-::~
V
r ___t_R'__",,-
~~
~----------------------------~·I
V il
® teR' ____I
_1••,~-----------tesH----
-- ------- --+--1
_....:::~~__~I_H::=====t!Re:!:O;;;;:::;::;::~·I--------
~::
--
--~I
_ _JJ
t ASH -- ------------.--..-1
CD\\\\~---teAs
r
i---------+tAR--+-----~1
tASR - - - -
-
tRAH -
I---teAH--
tAse
~H---~~:r-v-~~----vK~-Xr-r-+----+-------rX~--------+--------ROW
COLUMN
ADDRESSES
ADDRESS
ADDRESS
V,L _ _ _~~~_~_ _~~~_L~_+---_+-----_f~--------+_--------
l..-.t
V IH
...,
RCS
t RCH
0
---+---""""_,(0Il
,~--+-------H\--Ci'¥'
V'L
'\.'-_____
1------- - tCAC -_. - - - - - - -
i-------------tRAC-----------
i - - - tOFF - - - - - -
VOH ________=::'H~'G~H=,._---------------------0~3~1
VOL
0
IMPEDANCE
tRe
WRITE CY CLE
-
tRAS
eD\ 0
CDteR' ----j
t ASR
V,H
ADDRESSES
V'L
V,H
WE
V'L
-r----.
XeD0
eD r\\'\ I\@
--tRAH--.j
ROW
ADDRESS
tASC-
X )(
1:-- tRP-;=;j
~
t RSH
tRco
J
@
"'-O_A_T_A_O_U_T_ _ _ _-1
~ 1·---·te'N~1
tCSH
-~-
VALID
tCAS - - - - - - - -
f----
It
tAR
-
~tCAK-
K
COLUMN
ADDRESS
.
(f} .
-
t RWl
'eWL
--twcs-
_ t WCH twp
I
/
tweR
f--@tosV,H
D'N
V'L
- - - - - - t OH
@-
K
XeD0
,
tOHR
~~~---------~IM~:~E~~GA~:~C~E-----------------------------------------------------------NOTES:
1,2. V 1H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT ·
5. tOFF IS MEASURED TO lOUT';;;; IILO I.
~: ~~~HA~SDRt~~E~~~~i6~~E~HCEE~:ZCI~~°E~~,6i:H6~~~VRE~~S~~UH~~~:~~R
OCCURS FIRST.
S. tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (I.e., FOR SYSTEMS WHERE CAS HAS NOr BEEN DECODED WITH RAS).
A.C. CHARACTERISTICS NOTES (From Previous Page)
1. All voltages referenced to Vss.
2. Eight cycles are required after power-up or prolonged periods
(greater than 2ms! of RAS inactivity before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
3. A.C. Characteristics assume tT = 5ns.
4. Assume that tRCD oS tRCD (max). If tRCD is greater than tRCD
(max) then tRAC will increase by the amount that tRCD exceeds
tRCD (max).
5. Load = 2 TTL loads and 100pF.
6. Assumes tRCD ;0, tRCD (max).
7. tRCD (max.! is specified as a reference pOint only; if tRCD is less
than tRCD (max.! access time is tRAC, iftRCD is greater than tRCD
(max.! access time is tRCD + tCAC.
8. tT is measured between V'H Imin.! and V,L (max.!.
9. twcs, tCWD and tRwD are specified as reference points only. If
twcs;o, twcs (min.! the cycle is an early write cycle and the data
out pin will remain high impedance throughout the entire
cycle. If tCWD;o, tCWD (min.! and tRWD;o, tRWD Imin), the cycle is
a read-modify-write cycle and the data out will contain the data
read from the selected address. If neither of the above
conditions is satisfied, the condition of the data out is
indeterminate.
3-77
I
2109 FAMILY
WAVEFORMS
READ-MODIFY-WRITE CYCLE
.1
tRwe
I--',,-~I
tRRW
C1
I
~
~
'c,"
8 tcRP----1
®
tReD
-'
l ASR
ADDRESSES
~::
-
_tAR
!-
_tcPN_1
'RSH
'cR.
(0 ~\\ 0
H'RAH
tAS~t-
)( CD AD~~~SS]( X ;g~~~~
(3)
- tRWL ~tCWL---
tCAH
K
t Rwe
t Rcs
1-
I-""-JI
'CWO
1
0(iY
-I
~-I---'OH®
®'os-
){CD
-
-tcAC----i
_I
fRAe
°OUT
VOH
HIGH
Vo
IMPEDANCE
,
(j)
(4)
DATA IN
VALID
0
x:
~
_1-t
OFf
®
VALID
OATADUT
RAS-ONL Y REFRESH CYCLE
I-----------------'RC----------------~
r--,,,-I
- = L i - - - - - - - - - ' R A S - - - - - - - - . J1
CD 0
Jlr
v,H _ _
RAS
v"
ADDRESSES VIH
){:
CD AD~~~SS
1\'-___
X
V"-~~0~~~~-~~-----------------------------
DOUl :::-----------------~IM~~~~~:~NC~E~-----------------HIDDEN REFRESH CYCLE
V'H
ADDRESSES
V"
V'H
WE
V"
D
OUT
NOTES:
VOH _ _ _ _ _ _ _ _
Vo,
1,2.
3,4.
5.
6
7
S.
VALlO DATA
~~-----------
u
GRAPH 12
TYPICAL RAS ONLY
REFRESH CURRENT
1003 VS. AMBIENT TEMPERATURE
50r----,r-----r-----~--_,
TA ". 25°C
V aB = -s.OV
",I 25"C
r-- Y oo = 12.0V
voL 120V
r----- v ss '" -S OV -+-----.+-----__1
40~----~----~------4_----_4
40
30
30~----~----~------4_----_4
30~----+_-----+------+_----__1
20
20 ~----~----~---- tRAS
vas = -s.ov
z
~
i!:
::>
'- -...........
'"I
M
0
12
'0
200
400
200ns _
20~----+------+----~t~R~As~~20~0~n'--1
tRC '" 375n5
........
tRAS = 500ns
'Or---~~--~~~tR~A~C~50~0=n'-1
600
800
o
12
10
°0~----720:-----~40:-----760~-----:'80·
O,LO-------:,L,-----:"2:------:',3:-----':'4.
1000
TA - AMBIENT TEMPERATURE
tRC - CYCLE TIME (ns)
Voo - SUPPLY VOLTAGE (VOL TS)
GRAPH 13
TYPICAL PAGE MODE CURRENT
1004 VS. IpC
GRAPH 14
TYPICAL PAGE MODE CURRENT
1004 VS. VOO
50
Voo ~ 12.0V
TA =2S"C
;;
40
E
TA -2S'C
....
Voo = 12.0V
~
;;
E
....
40
30
a:
a:
::>
u
30
~
~
i!:
::>
20
'"I
~
12
i!:
I~ ~=_3~On5
'0
'""I
tCAS -'rn,
40
....
~
a:
a:
u
20
-f.-----' 1
1-""
tCAS
10
30
"
~
teAS = 135ns
tpc = 22Sn5
~
0
12
VSS = -S.OV
;;
E
~
Ves = -S.OY
a:
a:
::>
u
Ves '" -S.OV
re)
GRAPH 15
TYPICAL PAGE MODE CURRENT
1004 VS. AMBIENT TEMPERATURE
50
50
r---"""'==*==;I;:;:
1:;---1
tRAS '" 500n5
tRe = 750ns
tRC 1= 75On5
tRis = 200ns
o
=
t~375ns
teAS'" 135ns
tpc 225ns
20
iil
I
Q
350n5
10
12
tpc 1- 50000
tCAS = 3S0ns
t?C = 500n5
j
0
o
200
400
tpc -
600
800
1000
'2
"
'0
'3
'4
0
Voo - SUPPLY VOLTAGE (VOLTS)
CYCLE TIME (ns)
20
40
60
80
TA - AMBIENT TEMPERATURE ( C}
NOTES:
GRAPH 16
TYPICAL OUTPUT SOURCE CURRENT
IOH VS. OUTPUT VOLTAGE VOH
;;
E
....
~
80
60
£
40
Y oo
::>
::>
:=::>
0
I
~
E
TA "'25'C
20
'" 12.0V
Vss = -S.SV
Vcc =4.5V -
--- ------
I---
o
o
;;
E
....
TA
"u
"v;Z
....
":=
"
Vss '"' -S.SV
VCC '" 4.SV
60
40
/
0
I
.1001@VOO=13,2V,TA=0°C
=1 2S"C
~ Voo'" 12.0V
80
~
a:
a:
20
S"
o
/
•
1002 or 1003@tRAS= 200ns, tRC =
375ns, VOO = 12.0V, TA = 25°C
...
1002 or 1003 @ tRAS = 500ns, tRC =
750ns, VOO = 12.0V, T A = 25°C
o
1004 @ tCAS = 135ns, tpc = 225ns,
VOO = 12.0V, T A = 25°C
1:;. 1004 @ tCAS = 350ns, tpc = 500ns,
VOO = 12.0V, TA = 25°C
/
The typical 1DO current for a given com-
o
Y OH - OUTPUT VOLTAGE (VOLTS)
1. The cycle time, VOD supply voltage, and
ambient temperature dependence of I DOl,
1002,1003 and 1004 is shown in related
graphs. Common points of related curves
are indicated:
'00
'00
a:
a:
::>
u
w
u
a:
....
GRAPH 17
TYPICAL OUTPUT SINK CURRENT
IOL VS. OUTPUT VOLTAGE VOL
VOL - OUTPUT VOL TAGE (VOLTS)
3-80
bination of cycle time, VOO supply
voltage and ambient temperature may be
determined by combining the effects of
the appropriate family of curves.
2109 FAMILY
D.C. AND A.C. CHARACTERISTICS, PAGE MODE[7.8.11]
TA
= ooe
to 70 oe, VDD
= 12V±100f0,
Vee
= 5V±100f0,
VBB
= -5V±100f0,
Vss
= OV,
unless otherwise noted.
For Page Mode Operation order: 2109·3* S6064, S6065 or 2109·4* S6066, S6067.
5ymbol
tpc
Parameter
2109-3
56064,56065
2109-4
56066,56067
Min.
Min.
Max.
Max.
Unit
Page Mode Read or Write Cycle
225
275
ns
tpCM
Page Mode Read Modify Write
270
340
ns
tcp
CAS Precharge Time, Page Cycle
80
100
tRPM
RAS Pulse Width, Page Mode
200
10,000
250
10,000
tCAS
CAS Pulse Width
135
10.000
165
10,000
ns
IDD4
VDD Supply Current Page Mode,
Minimum tpc, Minimum tCAS
26
mA
30
Notes
ns
ns
9
·56064, 56066: A6 at VIH during Row Address Valid.
56065, 56067: A6 al VIL during Row Address Valid.
WAVEFORMS
PAGE MODE READ CYCLE
~----------------------------tRPM-------------------------------~1~
"t===::-;;.:t:===::j----------.. . I--~!1===::-;t;RS~H:===:~-tRP}__
_
V 1HC
CAS
-.J~~~;~:1~1
tePN
V 1L
ADDRESSES V1H
VIL_~~~~~~~~~----t_-'~~~~~--_HI~~~~~~-~----------
WE
V 1HC
vlL _ _ _t-_J
i-------tRAC
--------I
V OH
DOUT VOL------------~~
NOTES:
1,2 V 1H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MA.X ARE REFERENCE LEVELS FOR MEASURING TIMING OF D oUT 5. tOfF IS MEASURED TO lOUT
IllO I.
6. tRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST.
7. ALL VOL lAGES REFERENCED TO Vss.
8. AC CHARACTERISTIC ASSUME tT '" 5ns.
9 SEE THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNDER AL TERNATE CONDITIONS.
10 tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (t.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
11. ALL PREVIOUSLY SPECIFIED A.C. AND D.C. CHARACTERISTICS ARE APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE (i.e., 2109·3, S6064 OR 86065 WILL OPERATE AS A 2109·3).
3·81
2109 FAMILY
PAGE MODE WRITE CYCLE
_
V 1HC
RAS
V ,L
I
ADDRESSES V,H
VIL __~~~~~~~~~~____~~__~~~~~____~______4~__~~T-__~~____-+~
___________
ii'l£ V ,HC
VIL ____
~----_+~~--~----------~~----~--------~~--~~----~~----+_-----------
V,H
D,N
VIL ______
~-£~~~~~--~~-----'~--~~~--~~---------;~~------------~~----------------
PAGE MODE READ-MODIFY-WRITE CYCLE
ADDRESSES
VIH
VOL
VO"
DOUT VOL
NOTES,
1.2. V,H MIN AND VIL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3.4. VOH MIN AND VOL MAX ARE REFERENCE lEVELS FOR MEASURING TIMING OF DOUT5. tOFF IS MEASURED TO lOUT < IILO I.
6. tos AND tOH ARE REFERENCED TO CAS OR
WHICHEVER OCCURS LAST.
7. teRP REOUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A
ONLY CYCLE n .•.• FOR SYSTEMS WHERE CAl HAS NOT BEEN DECODED WITH
m.
mi.
3-82
CAS-
2109 FAMILY
APPLICATIONS
The 2109 is packaged in a standard 16-pin DIP by
multiplexing 14 address bits onto 7 input pins (Ao-As). The
7 bit address words are latched into the 2109 by two TTL
clocks, Row Address Strobe (RAS) and Column Address
Strobe (CASl. Since the 21 09 is an 8K memory device, only
13 of the 14 address bits are required and the 14th address
bit must be at VIH (for S6000, S6002, S6064 or S6066) or VIL
(for S6001, S6003, S6065 or S6067) during Row Address
Valid. This means it is'~ot possible to simply tie input pin
As high or low, since itJsupplies two system addresses to
the memory array. Input pin Ae must be at the appropriate
level (determined by the "S"-specification) during the row
address valid period and then changed to the proper high
order address during the column address valid period.
READ CYCLE
A Read cycle is performed by maintaining Write Enable
(WE) high during a RAS/CAS operation. The output pin of
a selected device will remain in a high impedance state
until valid data appears at the output at access time.
RAS/CAS TIMING
RAS and CAS have minimum pulse widths as defined by
tRAS and tCAS respectively. These minimum pulse widths
must be maintained for proper device operation and data
integrity. A cycle, once begun by driving RAS and/or CAS
low must not be ended or aborted prior to fulfilling the
minimum clock signal pulse width(s!. A new cycle can not
begin until the minimum precharge time, tRP, has been
met.
DATA OUTPUT OPERATION
The 2109 Data Output (DOUT), which has three-state
capability, is controlled by CAS. During CAS high state
(CAS at VIH) the output is in the high impedance state. The
following table summarizes the DOUT state for various
types of cycles.
Intel 2109 Data Output Operation
for Various Types of Cycles.
Device access time, tACC, is the longer of the two
calculated intervals:
1. tACC
= tRAC
OR 2. tACC
= tRCD + tCAC
Type of Cycle
DOUT State
Read Cycle
Data From Addressed
Memory Cell
HI-Z
HI-Z
HI-Z
Data From Addressed
Memory Cell
I ndeterm i nate
Fast Write Cycle
RAS-Only Refresh Cycle
CAS-Only Cycle
Read/Modify/Write Cycle
Access time from RAS, tRAC, and access time from CAS,
tCAC, are device parameters. Row to column address
strobe delay time, tRCD, are system dependent timing
parameters. For example, substituting the device parameters of the 2109-3 yields:
Delayed Write Cycle
HIDDEN REFRESH
3. tACC = tRAC = 200nsec for 25nsec :StRCL :S65 nsec
OR
4. tACC = tRCD + tCAC = tRCD + 135 for tRCD > 65nsec
A feature of the 2109 is that refresh cycles may be
performed while maintaining valid data at the output pin.
This feature is referred to as Hidden Refresh. Hidden
Refresh is performed by holding CAS at VIL and taking
RAS high and after a specified precharge period (tRP),
executing a "RAS-Only" refresh cycle, but with CAS held
low (see Figure below!.
Note that if 25nsec :StRCD :S65nsec device access time is
determined by equation 3 and is equal to tRAC. If tRCL
>65nsec, access time is determined by equation 4. This
40nsec interval (shown in thetRCD inequality in equation 3)
in which the falling edge of CAS can occur without
affecting access time is provided to allow for system
timing skew in the generation of CAS.
REFRESH CYCLES
Each of the 64 rows of the 2109 must be refreshed every 2
milliseconds to maintain data. Any memory cycle:
RAS
1. Read Cycle
2. Write Cycle (Early Write, Delayed Write or ReadModify-Write)
3. RAS-only Cycle
refreshes the selected row as defined by the low order
(RAS) addresses. As must be held at the proper level (VIH
or VIL depending on specification) to perform 64 cycle
refresh operation, but may be driven high and low for 128
cycle RAS-only refresh without affecting device data
retention. Any Write cycle, of course, may change the
state of the selected cell. Using a Read, Write, or ReadModify-Write cycle for refresh is not recommended for
systems which utilize "wire-OR" outputs since output bus
contention will occur.
-{
MEMORY
CYCLE
I
"""~.=:1
{'-------JCYi
\
CAS
HIGHZ
DOUT
(' - - - - - - - - 1
DATA
)-
This feature allows a refresh cycle to be "hidden" among
data cycles without affecting the data availability.
POWER ON
The 2109 requires no power on sequence providing
absolute maximum ratings are not exceeded. After the
application of supply voltages or after extended periods of
bias (greater than 2 milliseconds) without clocks, the
device must perform a minimum of eight initialization
cycles (any combination of cycles containing a RAS clock,
such as RAS-Only refresh) prior to normal operation.
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A RASonly refresh cycle maintains the DOUT in the high
impedance state with a typical power reduction of 20%
over a Read or Write cycle.
3-83
2109 FAMILY
I
POWER SUPPLY DECOUPLING/DISTRIBUTION
8K UPGRADE FOR 4K SYSTEMS
It is recommended that a 0.1",F ceramic capacitor be
The 2109 can be used to upgrade existing 4K (Intel 2104A)
memory systems with minimal redesign. The 2109
maintains many of the features of the 4K RAMs. For
example, the latched data output of the 4Ks can be
emulated by holding CAS low to maintain data out valid.
Hidden refresh capability for the 4Ks is also maintained
with the 2109. The 64 cycle refresh operation of the 2109
makes it compatible with 4K systems.
connected between Voo and Vss at every other device in
the memory array. A 0.1",F ceramic capacitor should also
be connected between VBB and Vss at every other device
(preferably the alternate devices to the Voo decoupling>.
For each 16 devices, a 10",F tantalum or equivalent
capacitor should be connected between Voo and Vss near
the array. An equal or slightly smaller bulk capacitor is
also recommended between VBB and Vss for every 32
devices.
To upgrade a 4K system to accept the 2109, an extra
memory address multiplexer must be implemented to
replace the Chip Select (CS) input of the 4Ks. The
replacement circuitry is shown in the figure below, and
involves some gating to control the output of the
multiplexer during row and column address valid periods
and also some control to handle the multiplexer during
refresh operation.
The Vcc supply is connected only to the 2109 output
buffer and is not used internally. The load current from the
Vcc supply is dependent only upon the output loading and
is associated with the input high level current to a TTL gate
and the output leakage currents of any OR-tied 2109's
(typically 100",A or less totaD.lntel recommends that a 0.1
or 0.01",F ceramic capacitor be connected between Vcc
and Vss for every eight memory devices.
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution system on the array board should be minimized. It is
recommended that the Voo, VBB, and Vss supply lines be
gridded both horizontally and vertically at each device in
the array. This technique allows use of double sided
circuit boards with noise performance equal to or better
than multi-layered circuit boards.
COLUMN
ENABLE
A6::; VIH
I E5
/:o---t----lL.....'
1\
As::; VIL
66001
56003
56066
56067
AOOR 12
OECOUPLING CAPACITORS
D = O.1IlF TO VDD TO Vss
B = O.1IlF VBB TO VSS
C = O.01IlF VCC TO Vss
SAMPLE P.C. BOARD LAYOUT EMPLOYING VERTICAL
AND HORIZONTAL GRIDDING ON ALL POWER SUPPLIES.
3·84
As (<:81
TOMEMORV
ARRAY
inter
2111A/8111A-4*
256 x 4 BIT STATIC RAM
2111A-2
2111A
2111A-4
250 ns Max.
350 ns Max.
450 ns Max.
Fully Decoded: On Chip Address
• Decode
Inputs Protected: All Inputs Have Pro• tection
Against Static Charge
Low
Cost
Packaging: 18 Pin Plastic Dual
• In-Line Configuration
Low Power: Typically 150 mW
• Three-State
Output: OR-Tie Capability
•
Data Input and Output
• Common
+5V Supply Voltage
• Single
Directly
• Output TTL Compatible: All Inputs and
MOS: No Clocks or Refreshing
• Static
Required
Memory Expansion: Chip Enable
• Simple
Input
The Intel® 2111A is a 256 word by 4-bit static random access memory element using N-channel MOS devices integrated on a
monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is
read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2111A is designed for memory applications in small systems where high performance, low cost, large bit storage, and
simple interfacing are important design objectives.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. Separate chip enable (CE) leads allow
easy selection of an individual package when outputs are OR-tied.
The Intel® 2111A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.
Intel's silicon gate technology also provides excellent protection against contamination. This permits the use of low cost
plastiC packaging.
PIN CONFIGURATION
LOGIC SYMBOL
_0.
CD __ I _ _r-=:B.:;L.,OCK
0
A,
DIAGRAM
@
AO
A,
Vee
Ao
A,
A,
A,
1/0 1
A2
A,
R/W
A,
1/° 2
A3
A4
®
---0
AD
CE,
A,
1/° 3
A5
1/04
A,
1/° 4
A,
1/03
A5
A7
1/0 2
A,
GND
liD,
A7
0
ROW
SelECT
CD
©
MEMORY ARRAY
32 ROWS
32 COLUMNS
@
1/01
00
@
1/02
@
INPUT
DATA
CONTROL
1/03
CE2
00
~vcc
1/0 4
PIN NAMES
I
I
L
Ao-A7
ADDRESS INPUTS
00
OUTPUT DISABLE
R/W
eE
~
! 1/0,-1/°4
eE,
2-
~~~D~:~:~ 11~:~
o '"
CHIP ENABLE 2
DATA INPUT/OUTPUT
----
• All 8111A-4 specifications are Identical to the 2111 A-4 specifications.
3-85
PIN NUMBERS
GNO
2111A FAMILY
'COMMENT:
ABSOLUTE MAXIMUM RATINGS*
Stresses above those listed under ''Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Under Bias ..... -10°Cto 80°C
Storage Temperature . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground. . . . . . . ..
-0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . .. 1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A = O°C to 70°C, Vcc = 5V ±5% , unless otherwise specified.
Typ.[ll
Max.
Unit
III
Input Load Current
1
10
pA
V IN = 0 to 5.25V
ILOH
I/O Leakage Current
1
10
pA
Output Disabled, VI/O = 4.0V
Output Disabled, VI/0=0.45V
V IN - 5.25V
Symbol
Parameter
Min.
ILOL
I/O Leakage Current
-1
-10
pA
ICC1
Power Supply
Current
2111A,2111A-4
2111A-2
35
45
55
65
mA
ICC2
Power Supply
2111A,2111A-4
60
2111A-2
70
Current
mA
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Output Low Voltage
Vcc
0.45
V
VOL
VIL
Output High
VOH
I\~
10L = 2.0mA
V
10H = -200pA
2111A-4
2.4
V
IOH--150pA
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
T~MPER1TURE
O°C
25°C
70°C
\\
\\
-10
'\
-5
o
.-
11/0=OmA, TA = O°C
2.4
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
AMBlkNT
11/0 = OmA, T A = 25°C
V IN = 5.25V
2111A,2111A-2
Voltage
-15
V
Test Conditions
1
Vee" 4.75V
!\..iUTPUj "H1Gr"
TYPjlCAL
~.
V OH (VOLTS)
NOTE: 1. Tvpical values are for TA
= 25'C and
VOL (VOLTS)
nominal supply voltage.
3-86
2111A FAMILY
A.C. CHARACTERISTICS FOR 2111A-2 (250 ns ACCESS TIME)
READ CYCLE T A
Symbol
= O°C to 70°C. Vcc = 5V ±5%. unless otherwise specified.
Parameter
Read Cycle
tRC
Min.
T yp.[1]
Max.
Unit
tA
Access Time
250
ns
tco
Chip Enable To Output
180
ns
too
tOF [3]
Output Disable To Output
130
ns
180
ns
tOH
Data Output to High Z State
0
Previous Read Data Valid
after change of Address
40
Test Conditfons
ns
250
ns
t r • tf = 20ns
Input Levels = 0.8V or 2.0V
Timing Reference = 1.5V
Load = 1 TTL Gate
and CL = 1OOpF.
WRITE CYCLE
Symbol
Parameter
Min.
Typ.[1]
Max.
Unit
twc
Write Cycle
tAW
Write Delay
tcw
Chip Enable To Write
tow
Data Setup
150
ns
tOH
twp
Data Hold
ns
Write Pulse
0
150
tWR
Write Recovery
0
ns
ns
tos
Output Disable Setup
20
ns
CAPACITANCE
Symbol
CIN
CI/O
[2]
TA
170
ns
20
ns
150
ns
Test Conditions
t r• tf = 20ns
Input Levels = 0.8V or 2.0V
Timing Reference = 1.5V
Load = 1 TTL Gate
and CL = 100pF.
= 25°C. f = 1 MHz
Test
Input Capacitance
(All Input Pins) VIN
= OV
I/O Capacitance VI/a = OV
Limits (pF)
TypJl] Max.
4
8
10
15
WAVEFORMS
READ CYCLE
WRITE CYCLE
I-------wc-------I
1-------tRc---~
ADDRESS
ADDRESS
CHIP
_--t_~I--~-tco
ENABLES
(ffi, CE2)
CHIP
ENABLES
(CE,.CE2 l
OUTPUT
OUTPUT
DISABLE
DISABLE
DATA I/O
DATA I/O
twP----twRREAD!
WRITE
NOTES: 1. Typical values are for TA = 25°C and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3. tOF is with respect to the trailing edge of CE1. CE2. or 00. whichever occurs first.
3-87
I
2111A FAMilY
2111A (350 ns ACCESS TIME)
A.C. CHARACTERISTICS
READ CYCLE TA ~ ODC to 70 DC. Vcc ~ 5V ±5%. unless otherwise specified
Symbol
I
Parameter
tRC
Read Cycle
tA
Access Time
Min.
Max.
350
Chip Enable To Output
too
tOF [2J
Output Disable To Output
Data Output to High Z State
Previous Read Data Valid
after change of Address
Test Conditions
- - I------
~
ns
t r • tf
ns
Input Levels
180
ns
Timing Reference = 1.5V
150
ns
Load
240
0
Unit
ns
350
tco
tOH
T yp.[1J
~
20ns
~
0.8V or 2.0V
1 TTL Gate
and CL
40
~
100pF.
ns
WRITE CYCLE
Symbol
Parameter
Min.
T yp.[1J
Max.
Unit
Test Conditions
twc
Write Cycle
220
ns
tAW
Write Delay
20
ns
t r • tf
tcw
Chip Enable To Write
200
ns
tow
Data Setup
200
ns
Input Levels ~ 0.8V or 2.0V
Timing Reference ~ 1.5V
tOH
twp
Data Hold
ns
Write Pulse
0
200
tWR
Write Recovery
0
ns
tos
Output Disable Setup
20
ns
---
ns
Load
~
~
--
20ns
1 TTL Gate
and CL
~
100pF.
2111A-4 (450 ns ACCESS TIME)
A.C. CHARACTERISTICS
READ CYCLE TA = ODC to 70 DC. VCC ~ 5V ±5%. unless otherwise specified
Symbol
Parameter
tRC
Read Cycle
tA
Access Time
Min.
T yp.[1]
Max.
Unit
450
ns
ns
t r • tf
Input Levels ~ 0.8V or 2.0V
Timing Reference ~ 1.5V
450
tco
Chip Enable To Output
310
ns
too
tOF [2J
Output Disable To Output
250
ns
200
ns
tOH
Data Output to High Z State
Previous Read Data Valid
after change of Address
0
Test Conditions
Load
~
~
20ns
1 TTL Gate
and CL = 100pF.
ns
40
WRITE CYCLE
Symbol
Parameter
Min.
Typ.[1J
Max.
Unit
Test Conditions
twc
Write Cycle
270
ns
tAW
Write Delay
20
ns
t r • tf
ns
Input Levels = O.8V or 2.0V
Timing Reference ~ 1.5V
tcw
Chip Enable To Write
250
tow
Data Setup
250
ns
tOH
twp
Data Hold
0
ns
Write Pulse
250
ns
tWR
Write Recovery
0
ns
tos
Output Disable Setup
20
ns
NOTES: 1. Typical values are for TA = 2SoC and nominal supply voltage.
2. tOF is with respect to the trailing edge of CE1. CE2. or 00. whichever occurs first.
3·88
Load
~
~
20ns
1 TTL Gate
and CL = 100pF.
inter
2112A
256 X 4 BIT STATIC RAM
2112A-2
2112A
2112A-4
250 ns Max.
350 ns Max.
450 ns Max.
• Single +5V Supply Voltage
• Directly TTL Compatible: All Inputs and
Outputs
• Static MOS: No Clocks or Refreshing
Required
• Simple Memory Expansion: Chip Enable
Input
• Fully Decoded: On Chip Address
Decode
• Inputs Protected: All Inputs Have Protection Against Static Charge
• Low Cost Packaging: 16 Pin Plastic Dual
In-Line Configuration
• Low Power: Typically 150 mW
• Three-State Output: OR-Tie Capability
The Intel® 2112A is a 256 word by 4-bit static random access memory element using N-channel MOS devices integrated on a
monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is
read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2112A is designed for memory applications in small systems where high performance, low cost, large bit storage, and
simple interfacing are important design objectives.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate chip enable (CE) lead allows
easy selection of an individual package when outputs are OR-tied.
The Intel® 2112A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
(0~'~a:=::f--I
@
AO~
A,
Vee
Ao
A,
A4
A,
A, 0)
:'"
--<> Vc
-
®
I'Q-
A,
WE
Ao
CE
liD,
A,
CD ..
SELECT
1/°2
A,
1/0 3
A4
1/°4
As
1/0 4
A,
1/0 3
A,
A,
1/0 2
A,
GND
110,
-----0
MEMORY ARRAY
32 ROWS
32 COLUMNS
ROW
-
As
WE
~
I
® ..
COLUMN I/O CIRCUITS
COLUMN SELECT
INPUT
DATA
CONTROL
CE
I/O,
r
...,-
PIN NAMES
An·A,
ADDRESS INPUTS
WE
CE
WRITE ENABLE
CE
@::::'3,--_~-or""'l
WE
o
r
@~"~~~~==L-r------------~
CHIP ENABLE INPUT
1/0,.1/0, DATA INPUT/OUTPUT
Vee
POWER (+5VI
3-89
r
= PIN NUMBERS
GND
2112A FAMILY
'COMMENT:
ABSOLUTE MAXIMUM RATINGS*
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the de·
vice at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Under Bias ..... _10°C to 80°C
Storage Temperature . . . . . . . . . . . -65°C to +150°C
I
Voltage On Any Pin
With Respect to Ground. . . . . . . ..
-0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A ~ O°C to 70°C, Vcc ~ 5V ±5% unless otherwise specified.
Symbol
Parameter
Typ.lll
Min.
Max.
Unit
III
Input Current
1
10
JlA
ILOH
I/O Leakage Current
1
10
JlA
ILOL
I/O Leakage Current
-1
-10
ICC1
Power Supply
Current
2112A, 2112A-4
2112A-2
35
45
JlA
mA
ICC2
Power Supply
Current
2112A, 2112A·4
2112A-2
VIL
V IH
Input "Low" Voltage
-0.5
Input "High" Voltage
2.0
VOL
Output "Low" Voltage
VOH
Output "High"
55
65
60
70
0.8
Test Conditions
VIN ~ 0 to 5.25V
Output Disabled, VII0~4.0V
Output Disabled, VI/0~0.45V
mA
VCC
+0.45
VIN ~ 5.25V, 1110
TA ~ 25°C
~
OmA
VIN ~ 5.25V, Ilia
TA ~ O°C
~
OmA
V
V
10L
~
2.0 mA
2112A,2112A-2
2.4
V
10H
~
-200JlA
2112A-4
2.4
V
10H
= -150JlA
Voltage
V
A.C. CHARACTERISTICS FOR 2112A-2
READ CYCLE
Symbol
T A = OoC to 70 c C, Vcc ~ 5V ±5% unless otherwise specified.
Parameter
tRC
Read Cycle
tA
Access Time
tco
Chip Enable To Output Time
tCD
Chip Enable To Output Disable Time
tOH
Previous Read Data Valid After
Change of Address
Typ. [1]
Min.
Max.
250
Unit
ns
0
Test Conditions
t r , tf
~
20ns
250
ns
180
ns
Timing Reference
120
ns
Load = 1 TTL Gate
40
ns
~
1.5V
and CL = 100pF.
READ CYCLE WAVEFORMS
CAPACITANCE
Symbol
CIN
CliO
[2J
TA = 25°C, f ~ 1 MHz
Limits (pF)
Typ.l1J Max.
Test
Input Capacitance
(All Input Pins) VIN
= OV
I/O Capacitance Vila ~ OV
4
8
10
15
NOTES:
1. Typical values are for TA ~ 25° C and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3·90
2112A FAMILY
A.C. CHARACTERISTICS FOR 2112A-2 (Continued)
WRITE CYCLE #1 TA = O°C to lO°C. Vcc = 5V ±5%
Symbol
Parameter
Write Cycle
tWCl
tAWl
tOWl
Typ)11
Min.
Max.
Unit
200
ns
Test Conditions
Address To Write Setup Time
20
ns
t r • tl = 20ns
Input Levels = 0.8V or 2.0V
Write Setup Time
180
ns
Timing Reference = 1.5V
tWPl
Write Pulse Width
180
ns
Load = 1 TTL Gate
tCSl
Chip Enable Setup Time
0
ns
tCHl
Chip Enable Hold Time
0
ns
tWRl
Write Recovery Time
Data Hold Time
0
0
ns
tOHl
tCWl
Chip Enable To Write Setup Time
180
ns
and CL = 100pF.
ns
WRITE CYCLE #2 TA = O°C to lO°C. Vcc = 5V ±5%
Symbol
Parameter
Typ.[1]
Min.
Max.
Unit
Test Conditions
tWC2
Write Cycle
320
ns
tAW2
tDw2
Address To Write Setup Time
Write Setup Time
20
180
ns
t r • tl = 20ns
Input Levels = 0.8V or 2.0V
ns
Timing Reference = 1.5V
tW02
Write To Output Disable Time
120
ns
Load = 1 TTL Gate
tCS2
Chip Ena,ble Setup Time
0
ns
tCH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
ns
tOH2
Data Hold Time
0
ns
WRITE CYCLE WAVEFORMS
WRITE CYCLE #1
WRITE CYCLE #2
1------"C1 - - - - - . -
INPUT/OUTPUT
NOTE: 1. Typical values are for TA
= 25° C and
nominal supply voltage.
3·91
and CL = 100pF.
2112A FAMILY
A.C. CHARACTERISTICS FOR 2112A
READ CYCLE
TA = OoC to 70°C, VCC = 5V ±5% unless otherwise specified.
Parameter
Symbol
tRC
Read Cycle
tA
Access Time
tco
Chip Enable To Output Time
Chip Enable To Output Disable Time
tco
tOH
Previous Read Data Valid After
Change of Address
WRITE CYCLE #1
Symbol
Typ.[ll
Max.
350
0
Unit
Test Conditions
ns
t r , tf - 20ns
350
240
ns
Input Levels = 0.8V or 2.0V
ns
Timing Reference = 1.5V
200
ns
Load = 1 TTL Gate
ns
40
and CL = 100pF.
TA = O°C to 70°C, VCC = 5V ±5%
Parameter
Min.
Typ.[ll
Max.
Unit
Test Conditions
tWC1
tAW1
tOW1
Write Cycle
270
ns
t r , tf = 20ns
Address To Write Setup Time
20
250
ns
Input Levels = 0.8V or 2.0V
Write Setup Time
ns
Timing Reference = 1.5V
tWP1
Write Pulse Width
250
ns
Load = 1 TTL Gate
tCS1
Chip Enable Setup Time
0
ns
tCH1
Chip Enable Hold Time
0
ns
tWR1
Write Recovery Time
0
ns
tOH1
Data Hold Time
0
ns
tCW1
Chip Enable to Write Setup Time
250
ns
WRITE CYCLE
Symbol
NOTE:
Min.
#2
and CL = 100pF.
TA = O°C to 70°C, Vcc = 5V ±5%
Parameter
Min.
Typ.!1J
Max.
Unit
Test Conditions
tWC2
tAw2
Write Cycle
470
ns
Address To Write Setup Time
ns
Input Levels = 0.8V or 2.0V
tOW2
Write Setup Time
20
250
ns
Timing Reference = 1.5V
tW02
Write To Output Disable Time
Load = 1 TTL Gate
Chip Enable Setup Time
200
0
ns
tCS2
tCH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
ns
tOH2
Data Hold Time
0
ns
1. Typical values are for TA = 25° C and nominal supply voltage.
3·92
ns
t r , tf = 20ns
and CL = 100pF.
2112A FAMILY
A.C. CHARACTERISTICS FOR 2112A-4
READ CYCLE
TA ~ O°C to 70°C. VCC ~ 5V ±5% unless otherwise specified.
Symbol
tRC
Min.
Parameter
Read Cycle
Typ.[ll
Max.
Unit
ns
450
Test Conditions
t r • tf = 20ns
tA
Access Time
450
ns
Input Levels = 0.8V or 2.0V
tco
Chip Enable To Output Time
310
ns
Timing Reference
tco
Chip Enable To Output Disable Time
260
ns
Load
tOH
Previous Read Data Valid After
Change of Address
WRITE CYCLE #1
Symbol
0
~
ns
40
~
1.5V
1 TTL Gate
and CL
~
100pF.
T A ~ O°C to 70°C. Vcc ~ 5V ±5%
Parameter
Min.
Typ.[1l
Max.
Unit
Test Cond itions
ns
t r • tf
Address To Write Setup Time
320
20
ns
Input Levels
Write Setup Time
300
ns
Timing Reference
tWP1
Write Pulse Width
Load
Chip Enable Setup Time
300
0
ns
tCS1
tCH1
Chip Enable Hold Time
0
ns
tWR1
Write Recovery Time
0
ns
tOH1
Data Hold Time
0
ns
tCW1
Chip Enable to Write Setup Time
300
ns
tWC1
Write Cycle
tAW 1
tOW1
ns
= 20ns
= 0.8V or 2.0V
= 1.5V
= 1 TTL Gate
and CL = 100pF.
WRITE CYCLE #2 TA = O°C to 70°C. Vcc = 5V ±5%
Symbol
NOTE:
Parameter
tWC2
tAW2
tOW2
Write Cycle
Min.
TypJ1l
Max.
Unit
Test Conditions
ns
t r • tf
Address To Write Setup Time
580
20
ns
I nput Levels
Write Setup Time
300
ns
Timing Reference
tW02
Write To Output Disable Time
Load
Chip Enable Setup Time
260
0
ns
tCS2
ns
tCH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
ns
tOH2
Data Hold Time
0
ns
1. Typical values are for TA
= 25'C and
nominal supply voltage.
3-93
= 20ns
= 0.8V or 2.0V
= 1.5V
= 1 TTL Gate
and CL = 100pF.
inter
2114
1024 X 4 BIT STATIC RAM
2114-2
I
I
2114-3
300
525
200
525
Max. Access Time (ns)
Max. Power Dissipation (mw)
2114
450
525
2114L2
2114L3
200
370
300
370
2114L
450
370
Directly TTL Compatible: All Inputs
• and
Outputs
Data Input and Output Using
• Common
Three-State Outputs
Compatible with 3605 and 3625
• Pin-Out
Bipolar PROMs
• High Density 18 Pin Package
• Identical Cycle and Access Times
+5V Supply
• Single
• No Clock or Timing Strobe Required
• Completely Static Memory
The Intel® 2114 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel Silicon-Gate
MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and therefore
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2114 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing are
important design objectives. The 2114 is placed in an 18-pin package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an individual package when outputs are or-tied.
The 2114 is fabricated with Intel's N-channel Silicon-Gate technology - a technology providing excellent protection against
contamination permitting the use of low cost plastic packaging.
PIN CONFIGURATION
As
Vee
As
A,
BLOCK DIAGRAM
LOGIC SYMBOL
0
A3
..
Ao
A,
1/° 1
As
A2
A.
As
A3
A,
As
I/0,
A,
I/O:,
A,
1/°3
A,
1/°4
A.
WE
A9
@
-+----=- Vee
~GND
A®
A.
A,
1/0:,
A,
A.
A,
As
(])
CD
ROW
SELECT
MEMORY ARRAY
64 ROWS
64 COLUMNS
@
@
1/°3
A.
I/O,@
I/O:,@
I/0.
I/o,,@
WE
CS
PIN NAMES
ADDRESS INPUTS
AO-Ag
WE
WRITE ENABLE
CS
CHIP SELECT
1/0,-1/°4 DATA INPUT/OUTPUT
o
Vee POWER_(+~~~-I
GND GROUND
i
I
I
3·94
0
PIN NUMBERS
2114 FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias . . . . . . . . . . . . -10°Cto 80°C
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . -0.5V to +7V
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . 1.0W
D.C. Output Current
. . . . . . . . . . . . . . . . . . . . . 5mA
D.C. AND OPERATING CHARACTERISTICS
TA = o°c to 70°C, Vcc
SYMBOL
= 5V ± 5%, unless otherwise noted.
PARAMETER
2114·2, 2114-3, 2114
Min. Typ.I 1 ] Max.
2114L2, 2114L3, 2114L
Min. Typ.]l] Max. UN]T
CONDITIONS
= 0 to
III
Input Load Current
(All Input Pins)
10
10
fJ.A
VIN
llLOI
I/O Leakage Current
10
10
fJ.A
CS = 2.4V,
VI/O = O.4V to Vcc
ICCl
Power Supply Current
95
65
mA
VIN = 5.25V, 11/0
TA = 25°C
= 0 mA,
ICC2
Power Supply Current
100
70
mA
VIN = 5.25V, 1110
TA = O°C
= 0 mA,
VIL
Input Low Voltage
-0.5
0.8
-0.5
0.8
V
VIH
Input High Voltage
2.0
6.0
2.0
6.0
V
10L
Output Low Current
2.1
6.0
2.1
6.0
mA
VOL
= O.4V
10H
Output High Current
-1.0
-1.4
-1.0
-1.4
mA
VOH
= 2.4V
IOS[2]
Output Short Circuit
Current
80
NOTE: 1. Typical values are for T A = 25° C and Vee
2. Duration not to exceed 30 seconds.
40
=
40
mA
5.0V.
CAPACITANCE
TA = 25°C, f = 1.0 MHz
SYMBOL
TEST
MAX
UNIT
CONDITIONS
CI/O
Input/Output Capacitance
5
pF
VI/a = OV
CIN
Input Capacitance
5
pF
VIN = OV
NOTE:
This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.8 Volt to 2.4 Volt
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 nsec
Input and Output Timing Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1;5 Volts
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF
3-95
5.25V
2114 FAMILY
A.C. CHARACTERISTICS
TA = o°c to 70°C, Vee = 5V ± 5%, unless otherwise noted.
READ CYCLE [1)
SYMBOL
2114-2, 2114L2 2114-3,2114L3
Max.
Max.
Min.
Min.
PARAMETER
tRe
Read Cycle Time
tA
Access Time
teo
Chip Selection to Output Valid
tex
Ch ip Selection to Output Active
tOTo
Output 3-state from Deselection
tOHA
Output Hold from Address Change
200
2114,2114L
Max.
Min.
300
450
UNIT
ns
200
300
450
ns
70
100
120
ns
20
20
20
80
60
50
ns
ns
100
ns
50
50
WRITE CYCLE [2)
2114,2114L
Max.
Min.
2114-2, 2114L2 2114-3, 2114L3
Min.
Max.
Max.
Min.
PARAMETER
SYMBOL
UNIT
twe
Write Cycle Time
200
300
450
ns
tw
Write Time
120
150
200
ns
tWR
Write Release Time
0
0
0
ns
tOTW
Output 3-state from Write
tow
Data to Write Time Overlap
120
150
200
ns
tOH
Data Hold From Write Time
0
0
0
ns
60
100
80
ns
NOTES:
1. A Read occurs during the overlap of a low CS and a high WE.
2. A Write occurs during the overlap of a low es and a low WE.
WAVEFORMS
READ CYCLE@
WRITE CYCLE
.
1-------tRc-------I
twc
I-----t.-----I
ADDRESS
ADDRESS
-..II\.----------+-IJ'----
-twR-
tj j j j j j j j j j j j j,
,\\ l\\\'
tw
®
~\\\
'--toTW..:j
NOTES:
DOUT
@) \iiiE is high for a Read Cycle.
@) If the CS low transition occurs simultaneously with the WE low
,tow
transition, the output buffers remain in a high impedance state.
D,N
® WE must be high during all address transitions.
3-96
"1
tOH
2114 FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
1.2
1.2
1. 1
1.0
~
filNO.9
.
:::;
ii!
0.8
1.0
~
fil
NO.9
..ii!
:::;
~
~
0.7
0.6
0.6
0.5
4.75
5.00
5.25
5.50
..
V"
~
J....--
1. 1
1.0
u
u
@ 0.9
N
:::;
~ 0.8
0.9
0.8
~
~
a;
o
z
0.7
0.6
O. 7
-
r--
0.6
0.5
100
200
JOO
400
500
20
600
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
30
30
~
o
o
60
TA ("C)
40
10
40
CL (pF)
40
20
80
1. 2
0
z
60
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
N
a;
40
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
:::;
:;;
20
TA (OC)
1.1
1.0
o
Vee (V)
1.2
w
0.8
0.7
0.5
4.50
~
0
----
1. 1
- --- -
r---.....
\
"
"-
10
/
V
/'
~
V
~
o
o
VOH (V)
VOL (V)
3-97
80
inter
M2114
1024 X 4 BIT STATIC RAM
M2114
Max. Access Time (ns)
450
Max. Power Dissipation (mW)
550
• High Density 18 Pin Package
• Identical Cycle and Access Times
• Single +5V Supply
• No Clock or Timing Strobe Required
• Completely Static Memory
Directly TTL Compatible: All Inputs
• and
Outputs
Common Data Input and Output Using
• Three-State
Outputs
Military
Temperature
• -55°C to +125°C Range
The I ntel® M2114 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel SiliconGate MOS technology. It uses fully DC stable (static) circuitry throughout - in both t.he array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The M2114 is designed for memory applications where high performance, large bit storage, and simple interfacing are
important design objectives. The M2114 is placed in an 18-pin package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead
allows easy selection of an individual package when outputs are OR-tied.
PIN CONFIGURATION
A"
Vee
LOGIC SYMBOL
A"
As
A,
A,
A.
IIa
A,
A,
Ag
A.
I/O,
A,
1/0,
A,
1/0,
1/0 1
A,
BLOCK DIAGRAM
0
• 0®
As
CD
A.
-4--=--
A
~GND
1/0,
A7
A.
As
As
@
A,
ROW
SELECT
Vee
MEMORY ARRAY
64 ROWS
64 COLUMNS
@
@
liD,
A,
I/O,@
A,
1/°4
As
WE
A,
1/°4
WE
es
I/O,@
1/0,@
PIN NAMES
AO-Ag
WE
ADDRESS INPUTS
Vee POWER (+5V)
WRITE ENABLE
GNDGROUND
CS
CHIP SELECT
o
1/0,-1/04 DATA INPUT/OUTPUT
3-98
0
PIN NUMBERS
inter
2115A, 2125A FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
2115AL
2125AL
2115A
2125A
2115AL-2
2125AL-2
2115A-2
2125A-2
45
45
70
70
75
125
75
125
I Max. T AA(ns)
l Max. Icc(mA)
• Pin Compatible To 93415A
(2115A) And 93425A (2125A)
• Fan-Out Of 10 TTL (2115A Family)
-- 16mA Output Sink Current
• TTL Inputs And Outputs
• Single +5V Supply
• Uncommitted Collector (2115A)
And Three-State (2125A) Output
• Standard 16-Pin Dual In-Line
• Low Operating Power Dissipation
--Max.0.39mW/Bit (2115AL, 2125AL) Package
The Intel® 2115A and 2125A families are high-speed, 1024 words by 1 bit random access memories. Both open collector
(2115A) and three-state output (2125A) are available. The 2115A and 2125A use fully DC stable (static) circuitry throughout - in both the array and the decoding and, therefore, require no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data.
The 2115AL/2125AL at 45 ns maximum access time and the 2115AL-212125AL-2 at 70 ns maximum access time are fully
compatible with the industry-produced 1 K bipolar RAMs, yet offer a 50% reduction in power of their bipolar equivalents.
The power dissipation of the 2115AL/2125AL and 2115AL-2/2125AL-2 is 394 mW maximum as compared to 814 mW
maximum of their bipolar equivalents. For systems already designed for 1 K bipolar RAMs, the 2115A/2125A and the
2115A-2/2125A-2 at 45 ns and 70 ns maximum access times, respectively, offer complete compatibility with a 20% reduction
in maximum power dissipation.
The devices are directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate select (CS) lead
allows easy selection of an individual package when outputs are OR-tied.
The 2115A and 2125A families are fabricated with Intel's N-channel MOS Silicon Gate Technology.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
cs
-
WORD
os
Vee
A,
DON
A,
WE
A,
A,
A3
As
DRIVER
A,
32 X 32
ARRAY
A,
1
A,
A3
A.
A,
DOUT
A,
GND
A,
SENSE AMPS
A,
A,
Vee
"
GNO '"
A,
11
12
A,
13
PIN 16
~
TABLE)
ADDRESS
ADDRESS
DECOOER
DECODER
DOUT
A1 A2 A3 A4
00000
PIN NAMES
W£
{SEE TRUTH
1
ttttt
I Ao TO Ag
lOGIC
WRITE
~
An
os
CONTROL
AND
DRIVERS
10
A,
PIN 8
J
~
A,
ttttt
-
AS A6 A7 As Ag
CS
@@@@@
CD @ @
WE
DIN
TRUTH TABLE
CHIP SELECT
INPUTS
ADDRESS INPUTS
WRITE ENABLE
CS WE DtN
H
X
X
~-~:~:~N~~kT
L
L
L
3-99
OUTPUT
OUTPUT
2115AFAMILY 2125AFAMILY
CIou,
L
L
L
H
H
H
HIGH Z
HIGH Z
HIGH Z
H
X
CloUT
CloUT
H
MODE
CloUT
NOT SELECTED
WRITE "0"
WRITE "'"
READ
2115A, 2125A FAMILY
ABSOLUTE MAXIMUM RATINGS*
I
Temperature Under Bias . . . . . . . . . . . . . _1O°C to +8SoC
Storage Temperature . . . . . . . . . . . . . .'-6SoC to +lS0°C
All Output or Supply Voltages . . . . . . . . . . -O.SV to +7V
All Input Voltages . . . . . . . . . . . . . . . . . -O.SV to +S.SV
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . 20 rnA
'COMMENT: Stresses above those listed under "Absolute Maxi·
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
at any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability .
D.C. CHARACTERISTlCSll,21
Vcc = SV ±S%, TA = o°c to 7SoC
Symbol
Test
Min.
Typ.
Max.
Unit
VOL1
211SA Family Output Low Voltage
0.45
V
IOL=16mA
Vob
2125A Family Output Low Voltage
0.45
V
IOL = 7 rnA
VIH
Input High Voltage
VIL
Input Low Voltage
IlL
Input Low Current
Conditions
V
2.1
0.8
V
-0.1
-40
/lA
Vcc = Max., VIN = O.4V
IIH
Input High Current
0.1
40
/lA
Vcc = Max., VIN = 4.5V
ICEX
2115A Family Output Leakage Current
0.1
100
/lA
Vce = Max., VOUT = 4.5V
ilOFFI
2125A Family Output Current (High Z)
0.1
50
/lA
Vec = Max., VOUT = 0.5V/2.4V
105[31
2125A Family Current Short Circuit
to Ground
-100
rnA
Vcc = Max.
VOH
Family Output High Voltage
ICC
Power Supply Current:
ICC1: 2115AL, 2115AL·2, 2125AL,
2125AL·2
2.4
ICC2: 2115A, 2115A·2, 2125A, 2125A·2
V
60
75
rnA
100
125
rnA
IOH = -3.2 rnA
All Inputs Grounded, Output
Open
NOTES:
1. The operating ambient temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and a two minute
warm~up. Typical thermal resistance values of the package at maximum temperature are:
6JA (@400fpM air flow) = 45°C/W
6JA (still air! = 60°C/W
6JC = 25°C/W
2. Typical limits are at VCC = 5V, TA = +25°C, and maximum loading.
3. Duration of short circuit current should not exceed 1 second.
3·100
2115A, 2125A FAMILY
2115A FAMILY A.C. CHARACTERISTICS[1,21 vee = 5V ±5%, TA = O°C to 75°C
READ CYCLE
Symbol
2115AL Limits
2115A Limits 2115AL·2 Limits 2115A-2 Limits
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
tACS
Chip Select Time
15
30
15
30
15
30
15
40
ns
tRCS
Chip Select Recovery Time
10
30
10
30
10
30
10
40
ns
tAA
Address Access Time
30
45
30
45
40
70
40
70
ns
tOH
Previous Read Data Valid After
Change of Address
5
5
10
5
10
5
10
10
ns
WRITE CYCLE
Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
tws
Write Enable Time
tWR
Write Recovery Time
tw
Write Pulse Width
tWSD
10
10
25
25
0
10
30
30
0
10
25
25
0
40
45
0
ns
30
20
30
10
30
15
50
15
Data Set-Up Time Prior to Write
0
-5
5
-5
0
-5
5
-5
ns
tWHD
Data Hold Time After Write
5
0
5
0
5
0
5
0
ns
ns
tWSA
Address Set-Up Time
5
0
5
0
5
0
15
0
ns
tWHA
Address Hold Time
5
0
5
0
5
0
5
0
ns
twses
Chip Select Set-Up Time
5
0
5
0
5
0
5
0
ns
tWHeS
Chip Select Hold Time
5
0
5
0
5
0
5
0
ns
A.C. TEST CONDITIONS
All INPUT PULSES
!
Vee
± /.
\
3.5Vp.p
300n
GND
2115A
-=-
90%
10%
10ns
10ns
DouT
30pF
600n
~.•
--r
-=- .,
(INCLUDING
SCOPE AND
JIG)
READ CYCLE
10%
90%
,. -10ns
GND
":'
I
IOn •
WRITE CYCLE
....
....J)K\,,___________
A".A. _ _
~
-';1-
f-
4-
--l(-
D,N
......__tw ___
DATA VALID
~"--.:J ' -
WE
PROPAGATION DELAY FROM CHIP SELECT
twso
--
_lt
_tWHA_1
...--twSA_
!+-twscs
DouT
--'-rJ
OATA
I:JNDEFINED
(ALL ABOVE MEASUREMENTS REFERENCED TO 1 5V)
3-101
WHO
tws
~~tWHCS~
'w.
~
2115A,2125A FAMILY
2125 FAMILY A.C. CHARACTERISTICS[l,21
READ CYCLE
Symbol
2125AL Limits
2125A Limits 2125AL·2 Limits 2125A·2 Limits
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
tACS
Chip Select Time
15
30
15
30
15
30
15
40
ns
tZRCS
Chip Select to HIGH Z
10
30
10
30
10
30
10
40
ns
tAA
Address Access Time
30
45
30
45
40
70
40
70
ns
tOH
Previous Read Data Valid After
Change of Address
5
5
10
5
10
10
5
10
ns
WRITE CYCLE
Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
tzws
Write Enable to HIGH Z
tWR
Write Recovery Time
10
tw
Write Pulse Width
tWSD
Data Set·Up Time Prior to Write
0
25
10
25
0
10
30
30
25
25
0
10
0
30
10
30
10
50
15
ns
0
-5
5
-5
0
-5
5
-5
ns
5
0
0
ns
15
5
0
ns
5
0
ns
5
0
ns
Data Hold Time After Write
5
0
5
0
5
tWSA
5
0
5
0
5
tWHA
Address Hold Time
5
0
5
0
5
twscs
Chip Select Set·Up Time
5
0
5
0
5
0
0
0
0
tWHCS
Chip Select Hold Time
5
0
5
0
5
0
A.C. TEST CONDITIONS
1/'",·----------·-----··------"""\\""-;. ;---;..;:;.;.:;.;..%--510n
GND
---,~--~
30pF
{INCLUDING
SCOPE AND
-=- _:
,---10ns
'
'
GNO -.:
READ CYCLE
~ ~
:_10ns
~~:------~
~~-----:! --::
,,
JIG I
AO·A g _ _ _
ns
ALL INPUT PULSES
Vee
300n
ns
20
Address Set·Up Time
DOUT
ns
45
30
tWHD
2125A
40
-----I
i--l0ns
WRITE CYCLE
J~..._ _ _ _ _ _ _ _ _ _ _ _ __
AO Ag
l~tAA--~1
DATA VALID
WE
PROPAGATION DELAY FROM CHIP SELECT
(ALL ABOVE MEASUREMENTS REFERENCED TO 1.5V)
3·102
~
,
1-----1Ons
2115A, 2125A FAMILY
2125A FAMILY WRITE ENABLE TO HIGH Z DELAY
5V
WE
WRITE ENABLE
750U
iF=
DoUT
2125A
DATA OUTPUT _ _..:"O~"~LE;.:V.:;EL:;""_ _
5pF
Dour _ _..:"I_"~LE;.:V~EL:;,..._-.I
,-__ !.I~!
DATA OUTPUT
LOAD 1
2125A FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z
cs
CHIP SELECT _ _---I
Dour
r - - ~I~-;
tZRCS
-Jf_} a.sv
DATA OUTPUT _ _ _
..O;......;;L;;;EV..;;E;;;L_ _
"'" LEVEL
DDUT
--..;...==--~--}
DATA OUTPUT
(ALL
0.5V
'- __
.!!!'!!! ~
tzxxx PARAMETERS ARE MEASURED AT A DELTA
OF O.SV FROM THE LOGIC LEVEL AND USING LOAD
1.1
2115A/2125A FAMILY CAPACITANCE* Vee= 5V, f = 1 MHz, TA = 25°C
2115A Family
LIMITS
TEST
SYMBOL
2125A Family
LIMITS
TEST CONDITIONS
UNITS
TYP.
MAX.
TYP.
CI
Input Capacitance
3
5
3
MAX.
5
pF
All
Co
Output Capacitance
5
8
5
8
pF
CS = 5V, All Other Inputs = OV,
Output Open
Inpu~s
= OV, Output Open
"This parameter is periodically sampled and is not 100% tested.
TYPICAL CHARACTERISTICS
Ice VS. TEMPERATURE
110
110
J115A.~
l - t-100
2l'5A.
2125A. 2125A·2 -
80
!l
70
50
50
V2115A.2115A.2
2125A,2125A·2
"!l
90
50
so
1 ~
~ ~
oS
l"- t--
2116AL.2116AL·2
r-- ~-
50
o
70
.,../
100
r-t--t-- r-
90
1
AeCESS TIME VS. TEMPtRATURE
lee VS. Vec
70
V
90
~115Al. 21'5AL·2
w
o
~
~
~
50
TEMPERATURE (OC)
50
M
90
f-
2~
15A], 21 JA.2
212SAL-2.2126A.2
......- p-
~
~V
-
---
V
I.--
I - I.-1--"'~115AL.
211SA
21rAL'i125A,
I--
2125AL.2126AL·2
50
o
~
TA=~5OC
o
10
Vee "SV
10
vcclVI
3-103
20
30
40
50
TEMPERATURE (GC)
60
70
80
inter
,,-
M2115A, M2125A, FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
,,"
"
M2115AL, M2125AL
M2115A, M2125A
Max. T AA (ns)
75
55
Max. ICC (mA)
75
125
• Low Operating Power Dissipation
4131mW (M2115AL, M2125AL)
• Fast Access Time Over -55°C
to 125°C --55ns Maximum
(M2115A, M2125A)
• Single 5V Supply With .:!:10%
Tolerance
• TTL Inputs and Output
• Uncommitted Collector
(M2115A, M2115AL) and Three
State (M2125A, M2125AL)
Output
• Non-Inverting Data Output
• Hermetic 16 Pin Dual In-Line
Package
The Intel® M2115A and M2125A families are fully static, random access memories (RAMs) organized as 1024 words by 1
bit, which operate over a _55°C to +125°C ambient temperature range. Both open collector (M2115A) and three-state
(M2125A) outputs are available. The M2115A and M2125A use fully DC stable (static) circuitry throughout in both the array
and the decoding, and, therefore, require no clocks or refreshing to operate. The data is read out nondestructively and has the
same polarity as the input data.
The M2125AL/M2125AL is ideal for high-performance systems where speed and power dissipation are significant design considerations. They have a maximum access time of 75 ns, while power dissipation is only 413 mW maximum. The M2115A/
M2125A at 55 ns maximum should be considered for applications in which speed is a primary design objective.
The devices are directly TTL compatible in all respects: inputs, outputs and a single +5V supply. A separate chip select lead
allows easy selection of an individual package when outputs are OR-tied.
PIN CONFIGURATION
LOGIC SYMBOL
CS
CS
Vee
"0
D,.
A,
A,
WE
A,
As
Ag
A,
As
"0
BLOCK DIAGRAM
DIN WE
I. I.
r--
WOAD
DRIVER
32 X32
ARRAY
1 I
A,
'"
DOUT
GND
A,
A,
A,
A,
A,
A,
As
Vee
a
GND =
SENSE AMPS
I.
DRIVERS
12
13
LOGIC
TABLEJ
1-
-
1
ADDRESS
DeCODER
ADDRESS
OECODER
DouT
t t 11 t
An
A, A2 A3 A4
000®®
PIN NAMES
I
t ttl t
Af:, As A7 As A9
CS
@@)@@@
CD @ @
WE
o.N
TRUTH TABLE
CHIP SELECT
ADDRESS INPUTS
INPUTS
WRITEENA~
DATA INPUT
CONTROL
ISEE TRUTH
11
A,
A,
PIN 16
PIN 8
!----------
AND
WRITE
d
DATA OUTPUT
3-104
OUTPUT
OUTPUT
211SA FAMILY 2125A FAMILY
CS WE DiN
DoUT
H
L
L
L
MOOE
DoUT
X
X
L
L
H
H
H
H
HIGH Z
HIGH Z
HIGH Z
NOT SELECTED
WRITE "0"
X
DoUT
DoUT
READ
L
H
WRITE"'"
M2115AL, M2115A, M2125AL, M2125A
ABSOLUTE MAXIMUM RATlNGS*
'COMMENT: Stresses above those listed under "Absolute Maxi·
mum Ratings" may cause permanent damage to the device. This is
Temperature Under Bias . . . . . . . . . . . _65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
All Output or Supply Voltages . . . . . . . . . . -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . -0.5V to +6V
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . 20 mA
a stress rating only and functional operation of the device at these
or at any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTICS[l,21
VCC = 5V ±10%, TA = _55°C to +125°C
Symbol
Test
Min.
Typ.
Max.
Unit
Conditions
VOLl
M2115A, M2115ALOutput Low
Voltage
0.45
V
IOL=10mA
VOL2
M2125A, M2125AL Output Low
Voltage
0.45
V
10L = 5 mA
VIH
Input High Voltage
VIL
Input Low Voltage
0.8
V
IlL
I n put Low Cu rrent
-0.1
-40
IlA
Vcc = Max., VIN = O.4V
IIH
Input High Current
0.1
40
IlA
Vcc = Max., VIN = 4.5V
ICEX
M2115A, M2115AL Output Leakage
Current
0.1
100
Il A
Vcc
= Max., VOUT = 4.5V
IIOFFI
M2125A, M2125AL Output Leakage
Current (High Z)
0.1
50
Il A
Vcc
= Max., VOUT = 0.5V/2.4V
IOS[31
M2125A, M2125AL Current Short
Circuit to Ground
-100
mA
Vcc
= Max.
VOH
M2115A, M2115AL Output High
Voltage
ICCl
M2115AL, M2125AL Power Supply
Current
ICC2
M2115A, M2125A Power Supply
Current
2.1
V
2.4
V
10H = -3.2 mA
60
75
mA
All Inputs Grounded, Output
Open
100
125
mA
All Inputs Grounded, Output
Open
NOTES:
1. The operating ambient temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and a 2·minute
warmup. Typical thermal resistance values of the package at maximum temperature are:
eJA (@ 400 fpM air flow) = 45°C/W
eJA (still air) = 60°C/W
eJC = 25°C/W
2. Typical limits are at V CC = 5V, T A = +25° C and maximum loading.
3. Duration of short circuit current should not exceed 1 second.
3·105
M2115AL, M2115A, M2125AL, M2125A
M2115AL, M2115A A.C. CHARACTERISTICS[1.2]
Vee = 5V ±10%. TA = _55°C to +125°C
IREADCYCLE
Symbol
t ACS
t RCS
tAA
tOH
M2115AL Limits
Typ.
Min.
Max.
Test
Chip Select Time
Chip Select Recovery Time
Address Access Time
Previous Read Data Valid After Change of
Address
5
M2115A Limits
Min.
Typ.
Max.
45
50
75
40
45
5
35
55
35
10
10
Units
ns
ns
ns
ns
WRITE CYCLE
Symbol
tws
tWR
tw
tWSD
tWHD
tWSA
tWHA
twses
tWHeS
Test
Min.
Write Enable Time
Write Recovery Time
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Typ.
Max.
45
50
0
55
5
5
15
5
5
5
10
-5
0
0
0
0
0
Min.
0
40
5
5
5
5
5
5
Typ.
Max.
Units
35
35
ns
ns
ns
ns
10
-5
0
ns
ns
ns
ns
ns
0
0
0
0
ALL INPUT PULSES
A.C. TEST CONDITIONS
'T"
4.5V
~ ~I,"--~--~--'"'~
-\:
--
~
90%
3.±5VP-P _/_: _____________ : _\",,-_"-~..;,;10%;.;;:..._ __
I
300n
,
I
GND
M2115A
I
-=- -.:
I
:--10ns
-......;
I
:-lOns
DoUT-----.---~
600n
~---~-------~--f,
::r= ~~LUDING
3.5~P.~ _ ~ \
SCOPE AND
--r ::
JIGI
GND"':"
READ CYCLE
AO-A9 _ _ _
J
-+j
_____________ / -
~
-10%
__ 90%
It
~
l--1Ons
:_1Ons
WRITE CYCLE
)K"""______________
CS
--lE--
AO·Ag
D,N
DATA VALID
-¥___+_-+_+-... I+-tw_ ~+--r---+-----'~~
WE
PROPAGATION DELAY FROM CHIP SELECT
tmo _ _
4-tW$A-"
- - twscs_
DouT
tALL ABOVE MEASUREMENTS REFERENCED TO 1.5VI
3-106
~I tWHO
~twHA-'
-I- 'ws b-.:.
HCS -
M2115AL, M2115A, M2125AL, M2125A
M2125AL, M2125A A.C. CHARACTERISTICSI1.21
Vcc = 5V ±10%, TA = _55°C to +125°C
READ CYCLE
Symbol
M2125AL Limits
Min.
Typ.
Max.
Test
Chip Select Time
Chip Select to HIGH Z
Address Access Time
Previous Read Data Valid After Change of
Address
tACS
tZRCS
tAA
tOH
M2125A Limits
Typ.
Min.
Max.
45
50
75
5
40
5
45
35
55
25
10
Units
ns
ns
ns
10
ns
WRITE CYCLE
Symbol
Test
Min.
Write Enable to HIGH Z
Write Recovery Time
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time
Address Hold Time
Chip Select Setup Time
tzws
tWR
tw
tWSD
tWHD
tWSA
tWHA
twscs
tWHCS
Chip Select Hold Time
Typ.
Min.
Max.
Units
35
35
10
-5
0
0
0
0
0
40
5
5
5
5
5
10
-5
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
0
5
0
ns
All INPUT PULSES
1---___ .. ______-\:---90%
:.\~__
~----
4.5V
3.s±vP'p. .
510n
"'tND
----...----4
300n
Max.
45
50
0
55
5
5
15
5
5
5
A.C. TEST CONDITIONS
M2125A
DOUl
Typ.
._,,,,,O%;,;,,,,_ _
, ,
, ,
-=- _:
,
-~
:--10n5
:_10n5
30pF
(INCLUDING
SCOPE AND
JIG)
READ CYCLE
Ao-A9 _ _
~~,"
WRITE CYCLE
v:-
It-
_ _ _ _ _ _ _ _ _ _ __
--el-
l-
~t--
,~
_tw ____
DATA VALID
WE
-~
PROPAGATION DELAY FROM CHIP SELECT
tWSD
l-
I---
tWSA
(ALL ABOVE MEASUREMENTS REFERENCED TO 1.5V)
3·107
,....
-lt
WHD
_tWHA_
-
!-+------ twses ------.-,
DouT
7
'w,,--=
~ tWHCS
-----.
M2115AL, M2115A, M2125AL, M2125A
M2125AL, M2125A WRITE ENABLE TO HIGH Z DELAY
5V
WRITE ENABLE
WE
750n
~
1.5V
tzws
M2125AL,
M2125A
Dour
DATA OUTPUT _ _'..;,'0'..,;'L;;.;E..;,V;;;EL:""_-Ji
5pF
r-----
HIGH Z
}0.5V
"1" LEVEL
-----''----''---C=} 05V
DOUT
'- __ ~I~!
DATA OUTPUT
LOAD 1
M2125AL, M2125A PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z
cs
CHIP SELECT
---.. . .{'t::
cs -
r - - HiGH Z
Dour
DATA OUTPUT _ _'_'O'_'L_E_V_EL_ _-'I
}
O.5V
"1" LEVEL
} 0.5V
Dour
'---~~:
DATA OUTPUT
(All tzxxx parameters are measured at a delta of O.5V from
the logic level and using Load 1.)
CAPACITANCE* VCC=5V f=1MHz TA=25°C
Symbol
M2115AL, M2115A
Limits
Typ.
Max.
Test
M2125AL, M2125A
Limits
Typ.
Max.
Test Conditions
Units
CI
Input Capacitance
3
5
3
5
pF
Co
Output Capacitance
5
8
5
8
pF
All Inputs = OV, Output Open
CS - 5V, All other inputs - OV,
Output Open
*This parameter is periodically sampled and is not 100% tested.
TYPICAL CHARACTERISTICS
ICC
vs. TEMPERATURE
110
120
r-
'00
80
r-
60
----
'00
M2~15A. L212SlA
I--
-
I
2 !-IS.
3. Load = 1 TTL and 50 pF.
4. The minimum ~e timing does not allow for tT or skews.
5. Referenced to CAS or WE, whichever occurs last.
3-112
2116 FAMILY
WAVEFORMS
READ CYCLE
'1
tCYC
I---tRP~
tRAS
V,H
RAS
(JJ
~
(j)
.
V,L
(JJ
V,L
tASR
'IH
I---
V,L
ROW
ADDRESS
K
tAse
)(
I - - - tAH -
K
ADDRESS
Ht
t RCS
'0,,-
_~
teAc
~®
CD
CD
-¥
VOL
RCH
~
.
tRAC
VOH
Dour
:;
dY
.
V,L
\\\\ l®
tCAS
COLUMN
I-
V,H
WE
tRSH
I+-
I+-t AH -
~
ADDRESSES
~,cp~1
tCSH
-tRCL~
V,H
CAS
~tCRP - - . .
'OOH-
}-
VALID
DATA OUT
WRITE CYCLE
~------------------------------tcvc------------------------------~
I~'~---------------------
V ,H
lIAS
tRAS
-----------------------1
1-
t Rp --------.
0\~0~------------------~~
V,L
!+-- 'CRP
-
'----
I
~------------------------tCSH----------------------+___..j
______-+-iI-----___....;.tR;;;;C;.L~
_ __::=::+_T'""T"""'!l~---------tRSH----------.j
o r\\ \\@-----
"oH
CAS
"oL
tASR~
V,H
\lQ)~
A -0
ADDRESSES
V,L
-------tAH-
ROW
ADDRESS
'ASC
-I+-
'CAS
'CP
-----r----I
- tAH COLUMN
ADDRESS
"oH
WE
"iL
V,H
D'N
V,L
t O O H - - lI
cAe
~-------------------tRAC1:=========~~~========~+_----I~.>-;--------- t
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~tO~F~F~-I~~~
DoUT
Notes:
~0
VOH
VOL
1,2.
3,4.
5.
6.
7.
VIH MIN and VIL MAX are reference levels for measuring timing of input signals.
VOH MIN and VOL MAX are reference levels for measuring timing of DOUT.
DOUT follows DIN when writing, with WE before CAS.
Referenced to CAS or WE, whichever occurs last.
tOFF is measured to lOUT'; IILOI.
3·113
®
2116 FAMILY
A.C. CHARACTERISTICS
T A = O°C to 70°C, VDD = 12V ±10%, VCC = 5V ±10%, VBB = -5V ±10%, VSS = OV, unless otherwise noted.
READ-MODIFY-WRITE CYCLE
Symbol
Parameter
2116-2
Min.
Max.
2116-3
Min.
Max.
2116-4
Min.
Max.
525
595
Unit
tRMW
Read-Modify-Write Cycle Time
400
tCRW
RMW Cycle CAS Width
225
10000
310
10000
350
10000
ns
tRRW
RMW Cycle RAS Width
325
32000
450
32000
500
32000
ns
tRWH
RMW Cycle RAS Hold Time
250
350
390
ns
tCWH
RMW Cycle CAS Hold Time
300
410
460
ns
tRWL
Write Command to RAS Lead Time
125
200
200
ns
tCWL
Write Command to CAS Lead Time
100
160
160
ns
twp
Write Command Pulse Width
50
100
100
ns
tRCS
Read Command Set-Up Time
0
tMOO
Modify Time
0
tos
Data-In Set-Up Time
tOHM
Data-In Hold Time (RMW Cycle)
0
10
0
ns
0
10
ns
10
0
ps
0
0
0
ns
50
100
125
ns
WAVEFORMS
READ MODIFY WRITE CYCLE
--'R-RW-tRMW=----f=-'RP~i
,
0
r--tCRP -
11
1
1
' - - - t RCL ----------'
-
Ci)
I
I
ADDA ESSES
~IH
IL
-i'AH
tASA~
XCi) AD~~~SS
0
!
lAse
-\\\\ '0
r
K ){
'CWH----------
1~~tAH
COLUMN
K
ADDRESS
tcp
--+
~
I---'RWL\-'wpV
L
I
'RCSI-I
tMOO"
tRAC
..-
)
.
tOFf-~1
..,.®
teAc
HIGH
IMPEDANCE
¥
Notes: 1,2.
---
_ t CWl -
0Ci)!
i'
"4---
tCRW - - , - - - - -
.----tAWH
tOHM
"-'os
(DOATA IN
... ®
(j)~
VALID
G)'I.-
DATA OUT
VI HMIN and VI LMAX are reference levels for measuring timing of input signals.
3,4. VOHMIN and VOLMAX are reference levefs for measuring timing of DOUT.
5. tOFF is measured to lOUT" IILol.
3-114
VALID
K
tDOH
"
I-
2116 FAMILY
REFRESH CYCLE WAVEFORMS
CAS BEFORE RAS CYCLES. (64 CYCLE REFRESH)
1-------------'CyC-------------I
i+-------,---'RAS - - - - - - - 1 1 - - - - 'RP - - - · 1
V,H
V,H
V,H
ADDRESSES
Ao'A5
~L
VALID
____
~~~~
________________
~~~
________________________________
~~~
VALID
_____________
All OTHER INPUTS: DON'T CARE
RAS ONLY CYCLES (128 CYCLE REFRESH)
1+-------------tCyC - - - - - - - - - - - - - 1
1+-------tRAS
--------1
I+----'R·----I
V,H
RAS
V,H
CAS
--t -----------------
~ ~:E: E_S ,:>it~ ~ :-AS-R- V-:- - l-'D- -'A-H- -~ fl~- - - ______
______________________________
-£~~~
___V_A_L_'D_______
Notes: 1,2. VIHMI N and VI LMAX are reference levels for measuring timing of input signals.
3.
CAS must be high or low as appropriate for the next cycle.
APPLICATIONS INFORMATION
REFRESH MODES
The 2116 may be refreshed in any of three modes.
Read/Refresh cycles and RAS-only cycles refresh the row
addressed by Ao through A6 and therefore require 128
cycles to refresh the stored data. Assuming a 500 nsec
system cycle time, the refresh operations require 64 ,"sec
out of each 2.0 msec refresh period or 3.2% of the available
memory time. The third 2116 refresh mode, CAS-beforeRAS, allows refresh of the stored data in only 64 cycles and
requires only 32 ,"sec or 1.6% of the available memory time
(equal to the 64-cycle refresh 4K RAMs). While some 2116
aplications would not be impacted by the 3.2% memory
lockout time using 128 cycle refresh, most large mainframe
memory applications would suffer throughput degradation
in that refresh mode. Intel designed the 2116 to allow either
128-cycle or 64-cycle refresh, allowing the system designer
to choose the refresh mode which fits his system needs. In
addition to allowing higher memory throughput, the CASbefore-RAS 64-cycle refresh mode dissipates approximately 14% less power than the 128-cycle RAS-only mode
and 23% less power than the 128-cycle Read/Refresh mode
(refer to the Standby Power Calculation section).
3·115
2116 FAMILY
OUTPUT DATA LATCH
POWER SUPPLY DECOUPLINGI
DISTRIBUTION
The 2116 contains .an output data latch eliminating the need
for an external system data latch and the timing circuitry
required to strobe an external latch. The 2116 output latch
operates identically to the output latch found on all industry
standard 16-pin, 4K RAMs and enhances the system com·
patibility of the 16K and 4K devices.
Power supply current waveforms for the 2116 are shown in
Figure 3. The Voo supply provides virtually all of the
operating current for the 2116. The Voo supply current,
100 , has two components: transient current peaks when the
clocks change state and a DC component while the clocks are
active (low). When selecting the decoupling capacitors for
the Voo supply, the characteristics of capacitors as well as
the current waveform must be considered. Suppression of
transient or pulse currents require capacitors with small
physical size and low inherent inductance. Monolithic and
other ceramic capacitors exhibit these desirable character·
istics. When the current waveform indicates a DC compo·
nent, bulk capacity must be located near the current load to
supply the load power. I nductive effects of PC board traces
and bus bars preclude supplying the DC component from
bulk capacitors at the periphery of a memory matrix without
voltage droop during the active portion of a memory cycle.
This means that some bulk capacity in the form of electrolytic or large ceramic capacitors should be distributed around
or within the memory matrix.
Operation of the output latch is controlled by CAS. The data
output will go to the high-impedance state immediately
following the CAS leading edge during each data cycle and
will either go to valid data at access time on selected devices
(devices receiving both RA§ and CAS) or will remain in the
high impedance state on unselected devices (devices
receiving only CAS). During RAS-only refresh cycles, the
data output remains in the state it was priortothe RAS-only
cycle. This unique feature of latched output RAMs allows a
refresh cycle to be hidden among data cycles without
impacting data availability. For instance, a RAS-only
refresh cycle could follow each data cycle in a
microprocessor system but the accessed data would
remain at the device output and the microprocessor could
take the data at any time within the cycle. Non-latched
output devices do not provide this type of hidden refresh
capability since their data output would go to the high
impedance state at the end of the data cycle.
The VBB supply current, I BB, has high transient current
peaks, with essentially no DC component (less than 400
microamperes). The VBB capacitors should be selected for
transient suppression characteristics. The following capacitance values and locations are recommended for the
2116:
1. A 0.33 IlF ceram ic capacitor between V 00 and V ss
(ground) at every other device.
2. A 0.1 ",F ceramic capacitor between VBB and Vss at every
other device (preferably alternate devices to the Von
decoupling above).
3. A 4.7 ",F electrolytic capacitor between Voo and Vss for
each eight devices and located adjacent to the devices.
The Vee supply is connected only to the 2116 output buffer
and is not used internally. The load current from the Vee
supply is dependent only upon the output loading and is
usually only the input high level current to a TTL gate and
the output leakage currents of any OR-tied 2116s (typically
100 ",A or less total). Intel recommends that a 0.1 or O.Ol",F
ceramic capacitor be connected between Vee and Vss for
every eight devices to preclude coupled nOise from
affecting the TTL devices in the system.
Intel recommends a power supply distribution system such
that each power supply is grided both horizontally and
vertically at each memory device. This technique minimizes
the power distribution system impedance and enhances the
effect of the decoupling capacitors.
3-116
2117 FAMILY
16,384 x 1 BIT DYNAMIC RAM
Maximum Access Time (ns)
Read, Write Cycle (ns)
Read-Modify-Write Cycle (ns)
• Industry Standard 16-Pin Configuration
• ±10% Tolerance on All Power Supplies:
+12V, +5V, -5V
• Low Power: 462mW Max. Operating,
20mW Max. Standby
• Low 100 Current Transients
• All Inputs, Including Clocks,
TTL Compatible
2117-2
150
320
330
2117-3
200
375
375
2117-4
250
410
475
• Non-Latched Output is Three-State,
TTL Compatible
• RAS Only Refresh
• 128 Refresh Cycles
Required Every 2ms
• Page Mode Capability
• CAS Controlled Output
Allows Hidden Refresh
The Intel® 2117 is a 16,384 word by 1-bit Dynamic MaS RAM fabricated with Intel's standard two layer polysilicon NMOS
technology - a production proven process for high performance, high reliability, and high storage density.
The 2117 uses a single transistor dynamic storage cell and advanced dynamic circuitry to achieve high speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients and ±10% tolerance on all power supplies contribute to the high noise immunity of the 2117 in a system
environment.
Multiplexing the 14 address bits into the 7 address input pins allows the 2117 to be packaged in the industry standard 16-pin
DIP. The two 7-bit address words are latched into the 2117 by the two TTL clocks, Row Address Strobe (RAS) and Column
Address Strobe (CAS), Non-critical timing requirements for RAS and CAS allow use of the address multiplexing technique
while maintaining high performance.
The 2117 three-state output is controlled by CAS, independent of RAS. After a valid read or read-modify-write cycle, data is
latched on the output by holding CAS low. The data out pin is returned to the high impedance state by returning CAS to
a high state. The 2117 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to
execute RAS-only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RASonly refresh cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of Ao through A6
during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is addressed.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
-vss
64x 128 CELL
MEMORY ARRAY
AO
A,
A,
A3
DOUT
A,
As
A6
DOUT
RAS
CAS
WE
PIN NAMES
AO-AS
ADDRESS INPUTS
WE
WRITE ENABLE
CAS
COLUMN ADDRESS STROBE
V"
Vee
POWER (-5V)~_
Voo
Vss
POWER (+12V)
D'N
DATA IN
DOUT
DATA OUT
RAS
ROW ADDRESS STROBE
-VOD
POWER (+5V)
GROUND
3·117
2117 FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT:
Ambient Temperature Under Bias '"
-10° C to +80°C
Storage Temperature . . . . . . . . . . . .. -65° C to +150° C
Voltage on Any Pin Relative to Vss
(Vss-Vss~4V)
..................... -0.3Vto+20V
Data Out Current ............................ 50mA
Power Dissipation ........ . . . . . . . . . . . . . . . . . .. 1.0W
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1,2]
TA
= ooe to 7o oe,
Symbol
-
VDD
= 12V ±10%,
VCC
Parameter
= 5V ±10%, VSB = -5V ±10%,
VSS
= OV,
unless otherwise noted.
Limits
Min. Typ.f31 Max. Unit Test Conditions
!Ill I
Input Load Current (any input)
0.1
10
p.A V1N=VSS to 7.0V, Vss=-5.0V
Illol
Output Leakage Current for
High Impedance State
0.1
10
Chip Deselected: CAS at VIH,
p.A VOUT = 0 to 5.5V
Notes
4
1001
Voo Supply Current, Standby
1.5
rnA CAS and RAS at VIH
ISS1
Vss Supply Current, Standby
1.0
50
p.A
ICC1
Vcc Supply Current, Output
Deselected
0.1
10
p.A CAS at VIH
1002
Voo Supply Current, Operating
35
rnA 2117-2, tRC = 375ns, tRAS = 150ns
4,6
35
mA 2117-3, tRC = 375ns, tRAS = 200ns
4
33
rnA 2117-4, tRC = 410ns, tRAS = 250ns
4
ISS2
Vss Supply Current, Operating,
RAS-Only Refresh, Page Mode
1003
Voo Supply Current, RAS-Only
Refresh
150
300
p.A TA = O°C
27
mA 2117-2, tRC = 375ns, tRAS = 150ns
4,6
27
rnA 2117-3, tRC = 375ns, tRAS = 200ns
4
rnA 2117-4, tRC = 410ns, tRAS = 250ns
4
26
1.5
5
1005
Voo Supply Current, Standby,
Output Enabled
Vil
Input Low Voltage (all inputs)
-1.0
0.8
VIH
Input High Voltage (all inputs)
2.4
6.0
V
VOL
Output Low Voltage
0.4
V
IOl = 4.2mA
4
VOH
Output High Voltage
V
10H = -5mA
4
2.4
3
rnA CAS at Vlk RAS at VIH
V
NOTES:
1. All voltages referenced to Vss.
2. No power supply sequencing is required. However, VDD, Vcc and Vss should never be more negative than -O.3V with respectto VBB as
required by the absolute maximum ratings.
3. Typical values are for TI.I = 25°C and nominal supply voltages.
4. See the Typical Characteristics Section for values of this parameter under alternate conditions.
5. Icc is dependent on output loading when the device output is selected. Vce is connected to the output buffer only. Vee may be reduced
to Vss without affecting refresh operation or maintenance of internal device data.
6. For the 2117-2 at tRe = 320ns, tRAS = 150ns, IDD2 max. is 45mA and IDD3 max. is 31mA.
3-118
2117 FAMILY
TYPICAL SUPPLY CURRENT WAVEFORMS
ii.A:S/~
LONG
RAs/ffl
RAS ONLY REFRESH
J 111/111 t i l l
Pi
J II
I f II
125
100
IDO
(rnA)
75
50
J
"
( ~
W\
25
\I--J
J
A
~
I...
I~
I
I\.
75
,'"
50
1\
25
IBB
(rnA)
II
0
~ (
-25
V
n
A
I~
.
A.
'V
lJ
II,
- 50
..
A 1\
."
l
A
~\
"
-75
125
100
Iss
(rnA)
1\
75
"
50
25
o
o
III1
/\
J V r-- I ~
100
200
300
400
500
TIME(ns)
IlriEl
100
200
300
400
500
600
100
800
"~
111/'
J
900
100
TlME( n5)
Typical power supply current waveforms vs. time are
shown for the RAS/CAS timings of Read/Write, Read/
Write (Long RAS/CAS), and RAS-only refresh cycles. 100
and IBB current transients at the RAS and CAS edges
require adequate decoupling of these supplies. Decoupling recommendations are provided in the Applications
section.
V
-
...
J "'400
r-..
300
200
TlME(ns)
The effects of cycle time, Voo supply voltage and ambient
temperature on the 100 current are shown in graphs
included in the Typical Characteristics Section. Each
family of curves for 1001, 1002, and 1003 is related by a
common point at Voo = 12.0V and TA =25°Cfortwo given
tRAS pulse widths. The typical 100 current for a given
condition of cycle time, Voo and TA can be determined by
combining the effects of the appropriate family of curves.
CAPACITANCE!1]
TA
= 25°C,
Symbol
VOD
= 12V±10%, VCC = 5V±10%,
VBB
500
= -5V±10%,
Parameter
VSS
= OV,
unless otherwise specified.
Typ.
Max.
Unit
CI1
Address, Data In
3
5
pF
CI2
RAS Capacitance, WE CapaCitance
4
7
pF
CI3
CAS CapaCitance
6
10
pF
Co
Data Output CapaCitance
4
7
pF
NOTES:
1. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation:
C = IAt with AV equal to 3 volts and power supplies at nominal levels.
AV
3-119
2117 FAMILY
A.C. CHARACTERISTICS[1,2,3]
TA
= O°C
to 70°C, VDD
= 12V ±10%,
VCC
= 5V
±10%, VBB
= -5V ±10%,
Vss
= OV,
unless otherwise noted.
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
2117-2
Symbol
Parameter
Min.
tCAC
Access Time From CAS
tREF
Time Between Refresh
tRP
tRAH
100
CAS Precharge Time(non-pagecycles) 25
CAS to RAS Precharge Time
-20
RAS to CAS Delay Time
20
RAS Hold Time
100
CAS Hold Time
150
Row Address Set-Up Time
0
Row Address Hold Time
20
tASC
Column Address Set-Up Time
tCAH
Column Address Hold Time
tRCO
tRSH
tCSH
tASR
2117-3
Min.
150
100
2
tRAC
Access Time From RAS
tCPN
tCRP
Max.
RAS Precharge Time
50
Max.
200
135
2
120
25
-20
25
135
200
0
25
65
-10
-10
50
50
55
120
3
0
50
60
10000
10000
375
200
135
10000
10000
tAR
Column Address Hold Time, to RAS
tT
Transition Time (Rise and Fall)
45
95
3
tOFF
Output Buffer Turn Off Delay
0
2117-4
Min.
150
25
-20
35
165
250
0
35
-10
75
160
3
0
Max.
Unit
Notes
250
165
2
ns
4,5
4,5,6
ns
ms
ns
ns
ns
85
ns
7
ns
ns
ns
ns
ns
ns
ns
50
70
ns
8
ns
READ AND REFRESH CYCLES
tRC
Random Read Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
tRCS
Read Command Set-Up Time
tRCH
Read Command Hold Time
320
150
100
0
0
0
0
410
250
165
0
0
ns
10000
10000
ns
ns
ns
ns
WRITE CYCLE
tRC
Random Write Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
twcs
Write Command Set-Up Time
tWCH
Write Command Hold Time
tWCR
Write Command Hold Time, to RAS
twp
Write Command Pulse Width
tRWL
Write Command to RAS Lead Time
tcwL
Write Command to CAS Lead Time
tos
Data-In Set-Up Time
tOH
Data-In Hold Time
tOHR
Data-In Hold Time, to RAS
320
150
100
10000
10000
-20
45
95
45
60
60
0
45
95
375
200
135
10000
10000
410
250
165
ns
10000
10000
ns
-20
75
160
75
100
100
0
75
160
-20
55
120
55
80
80
0
55
120
ns
ns
9
ns
ns
ns
ns
ns
ns
ns
ns
READ-MODIFY-WRITE CYCLE
tRWC
Read-Modify-Write Cycle Time
tRRW
RMW Cycle RAS Pulse Width
tCRW
RMW Cycle CAS Pulse Width
tRWO
RAS to WE Delay
tcwo
CAS to WE Delay
330
185
135
120
70
10000
10000
Notes: See following page for A.C. Characteristics Notes.
3·120
375
245
180
160
95
101)00
10000
475
305
230
200
125
ns
10000
10000
ns
ns
ns
9
ns
9
-
2117 FAMILY
WAVEFORMS
..
READ CY CLE
v ,H
RAS
VIL
~
'1H
ADDRESSES
V'L
K
ROW
ADDRESS
DOUT
tAR
tAse
)<
teAs
V
~tCAH~
K
COLUMN
ADDRESS
.1--- t
H
RCS
dJl
V'L
VOL
\\\\ ~
~
-tRAH ...........
V ,H
V OH
t RSH
CD
I---
tASR
~tcp~
tCSH
tRco
I
VIL
-0
f<---.~~tCAc
tRAC
HIGH
t RcH
0
\
.
I----tO FF -
r-V-A-L-,D-----"'\I@
--------~IM~P~E~D~A~NC~E~-------------------~8)~~-D-AT-A_O_U_T_ _ _ _-1
WRITE CY CLE
t RC
l~tR~
tRAS
CD ]\0
(VtCRP
---1
kf
t;-
tCSH
CD
---tRAH----j
)[CD® ROW;)(
tAsR-r-....
V,H
ADDRESSES
V'L
ADDRESS
1\\\1\0
tASC-
I-
)<
!--tCAH-
K
COLUMN
ADDRESS
t RWL
'eWL
- twcH -
---twcs ...........
@
~
V'L
~
'cAS
- - t-tAR
I
V,H
l--tcPN-1
t RSH
tRCD
I
WE
f--:-tRd
~
~~
®tcRP~1
WE
--
CD [\l®
V,H
CAS
tRC
tRAS
~I /
I
''I
twp
tWCR
1--0 o s CD0
t
V,H
D'N
V'L
- - tDH
@-
X
K
.
tOHR
~~~--------~IM~P~~~~~:N~C~E~-------------------------------NOTES:
1,2. V 1H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DoUT 5. tOFF IS MEASURED TO lOUT';;;; jlLO (.
~: !~~HA~sDRt~~E~~~~EE6~~\NHCEE~RT~~I~~°E~:'O~Hd;~~V:~A~~~~~g~:J;R OCCURS FIRST.
S. tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (i.e., FOR SYSTEMS WHER~ CAS HAS NOT BEEN DECODED WITH RAS).
A.C. CHARACTERISTICS NOTES (From Previous Page)
1. All voltages referenced to Vss.
2. Eight cycles are required after power-up or prolonged periods
(greater than 2ms) of RAS inactivity before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
3. A.C. Characteristics assume tT = 5ns.
4. Assume that tRCD ,,; tRCD (max.!. If tRCD is greater than tRCD
(max.! then tRAC will increase by the amount that tRCD exceeds
tRC'D (max.!.
5. Load = 2 TTL loads and 100pF.
6. Assumes tRCD ~ tRCD (max.!.
7. tRCD (max.! is specified as a reference pOint only; if tRCD is less
than tRCD (max.! access time is tRAC, iftRCD is greater than tRCD
(max.! access time is tRCD + ICAC.
8. IT is measured between VIH (min.! and VIL (max.!.
9. twcs, tcwD and IRWD are specified as reference points only. If
Iwcs ~ Iwcs (min.! the cycle is an early write cycle and the data
out pin will remain high impedance throughout the entire
cycle. If tCWD ~ tCWD (min.! and tRWD ~ tRWD (min.!, the cycle is
a read-modify-write cycle and the data out will contain the data
read from the selected address. If neither of the above
conditions is satisfied, the condition of the data out is
indeterminate.
3-121
2117 FAMILY
WAVEFORMS
READ·MODIFY·WRITE CYCLE
tRWC
. r- 'R,----j
tHRW
CD ®
®teRP-1
teS.
i-=----- ,"CD
'-./I
~tAR
H~".:-jXCD AD~~SS J( X ;g~~~~
tASRr--ADDRESSES
~::
~
®
tRCSt-!
r----- te" ------/
tRSH
teRW
CD~\\\~-
I-----'RWL~
.....
! - - tCWL -
K
tRWO
towD
r-----~Py
®CD/
'I _I--'D'j;;"""
®
®'DS
XeD
DATA IN
VALID
-teAC--------I ®
'RAC
01
VD.
!\JUT Vo
HIGH
L
IMPEDANCE:'
K
-
VALID
DATA OUT
0
'oFF
®
RAS·ONL Y REFRESH CYCLE
~-------------------------'RC------------------------------~
v,.
ilAS v"
__ ....",..,>'-I--------'RA·----------I1•
CD
-J
r-'RP----j
$
®
,'-___
-teRP®
) { CD AD~C:SS
](
V"--~~®~2--~~~--~-----------------------------------------------------------
ADDRESSES VIH
DOUT VOH
HIGH
VOL
IMPEDANCE
HIDDEN REFRESH CYCLE
RAS
v,.
ADDRESSES
V,, __~~~~~~+_~~------~~--~~----------~f_--~~----------_+-----------V,.------~~~~+---------------------------~I-----------------------+~~--------
WE
VO.
DOUT
-----------------<1
VALID DATA
~~----------------------~~----------------------~
NOTES:
VOL
1,2. V,H MIN AND V,L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT '
5. to" IS MEASURED TO 'OUT" IILO I.
~: :~~HA~DRt~~E~:~~EE6~~E:;:~:~~c::~:.;Hri~~~E:~~~~~~~~~R OCCURS FIRST.
8. 'cR. REQUIREMENT IS ONLY APPLICABLE FOR RASICAS CYCLES PRECEEDED BY A CASONLY CYCLE Ii .•. , FOR SYSTEMS WHERE CASHAS NOT BEEN DECODED WITH RASI •
. 3·122
2117 FAMILY
TYPICAL CHARACTERISTICS[lJ
GRAPH 1
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS. VOO
GRAPH 2
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS. VBB
1.2
1.2
~
1.1
....
~
"00
C
1.0
~
~
!O:
0
0
0.9
~
u
~t'-
~
1.1
?u
1.0
~u
1.0
:'0m:
0.9
!O:
0.9
;
0.8
'""
~
~
u
~
?u
TA =70"C
t--- Ves
0.8
1.1
"m
'" -5.5V
Voo'"
12.0V~
vec1·ov
;
0.7
10
12
11
13
-4.5
-4.0
14
-5.0
-5.5
Vas - SUPPLY VOL T AGE (VOLTS)
GRAPH 4
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS.
AMBI ENT TEMPERATURE
GRAPH 5
TYPICAL STANDBY CURRENT
L
1.0
,/'
./
:<
.s
1.2
TA '" DOC
Vas'" -4.5V
r5
1.0
::J
OJ
~
0.8
'"I
Von'" 10.BV
/'
.. /
::J
0 0.6
!!
.s....
:<
1.2
r5a:
a:
1.0
40
60
10
80
TA - AMBIENT TEMPERATURE (QCJ
~
12
"
1002 VS. tRC
13
~----~----_4----~~~:~~~:
:<
.s
~
r5
a:
30
a:
20
::J
'"I
'"I
2
:<
.s....
Q
10
!!
----
~375n'
Voo =12.0V
Vss =: -5.0V
30
200ns
tRG '" 375ns
tRAS
~
&:
::J
tRi
=
20
'"I
2
750n,
!!
tRAS
10
t Rc =
l
tRAS == 200ns
0
200
400
600
800
tRG - CYCLE TIME Ins)
1000
o
10
80
40
::J
OJ
--' - - : ± = 5 0 0 n ,
10
60
iE
a:
a:
tRAS '" 200n5
30
~
&:
20
40
50
-5.0V
40
::J
OJ
::J
!!
=:
f-
::J
OJ
&:
Vas
20
r--
GRAPH 9
TYPICAL OPERATING CURRENT
1002 VS. AMBIENT TEMPERATURE
1002 VS. VOO
f-
a:
o
--
TA - AMBIENT TEMPERATURE (OC)
TA = 25 l C
iE
a:
0.6
0.4
14
50
TA "" 25"C
.s
r-- r--
I
Q
!!
GRAPH 8
TYPICAL OPERATING CURRENT
50r-----,-----~------,_-----,
40
0.8
iil
Voo - SUPPLY VOL TAGE (VOLTS)
GRAPH 7
TYPICAL OPERATING CURRENT
:<
6.0
Voo =: 13.2V
Vss '" -4.5V
::J
OJ
~
0.4
20
5.5
1.4
f-
Vss"'-5.5VVee =t5V
o
5.0
/"
a:
a:
0.8
4.5
GRAPH 6
TYPICAL STANDBY CURRENT
1001 VS. AMBIENT TEMPERATURE
IDOl VS. VOO
/
0.9
Voo =: 12.0VVBB i-5.5V
Vee - SUPPLY VOL T AGE (VOLTS)
1.4
1. 1
T A =70°C
O.B
0.7
4.0
-6.0
Voo - SUPPL Y VOL T AGE (VOL TS)
1.2
0.7
u
TA=70°C
Vee 1= 4.5V
0.7
I
1.2
'?
C
;
GRAPH 3
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS. VCC
12
11
13
Voo - SUPPLY VOLTAGE (VOL IS)
NOTES: See following page for Typical Characteristics Notes.
3·123
14
o
o
20
40
=:
500ns
750n,
60
TA - AMBIENT TEMPERATURE (C)
80
2117 FAMILY
TYPICAL CHARACTERISTICS
[1]
GRAPH 11
TYPICAL RAS ONLY
REFRESH CURRENT
1003 VS• VDO
GRAPH 10
TYPICAL RAS ONLY
REFRESH CURRENT
1003 VS. tRC
I
50r-----,------,------,------,
50
f------- voo =
40
;;E
12.0V
vBS '" -s.ov
fii
~
30
=>
=>
u
it
~
iilit
"~
=>
20
'- r--........
'"I
8
E
10
vas:::: -s.ov
40~----+-----~-----+----~
....
fii
a:
a:
--
r--.....
30r------r----~------~-----i
M
~
200
400
600
I
'----~oo· 12.0V
Vas'" -5.0V
40
fii
'"'"=>
30
u
tRAS = 200ns
20~----~----~---'!;;,375ns
-
I
tRAS '" 500ns
;;E
....
~
it
=>
20
tRAS - 200ns
tRC '" 375ns
'"I
10~----~----~r----tR~A~C~·~5=0~On-'-i
~
I
M
~
10
tRAS '" 500ns
t Rc "" 700ns
l
tAC (" 750n5
tR/t '" 200ns
o
50
TA = 25°C
TA ",1 25oC
;;E
....
GRAPH 12
TYPICAL RAS ON L Y
REFRESH CURRENT
1003 VS. AMBIENT TEMPERATURE
OL-----L-----L-----L---~
1000
800
10
11
12
13
20
14
Voo - SUPPLY VOLTAGE (VOLTS)
GRAPH 13
TYPICAL PAGE MODE CURRENT
1004 VS. tpc
GRAPH 14
TYPICAL PAGE MODE CURRENT
1004 VS. VOO
50
TA l25'C
;;E
....
40
;;E
TA=25°C
a:
30
'"u=>
=>
"
~
20
I
~
Q
Q
10
it
I~ ~=~fOns
"
"~
30
~
iil
80
vaa '" -5.0V
;;E
....
z
40
fii
Vss '" -S.OV
a:
voo
Vea'" -S.OV
....
Voo'" 12.0V
fii
a:
60
GRAPH 15
TYPICAL PAGE MODE CURRENT
1004 VS. AMBIENT TEMPERATURE
50
50
40
TA - AMBIENT TEMPERATURE (DC)
tRC - CYCLE TIME (ns)
10
:to-'
.1
teAS
tpc
n,
30
it
tCAS'" 135ns
tee 225ns
20
=>
'"I
~
350ns
1- 500n,
10
tCAS - 350ns
tPC1 = 500ns
0
o
200
400
600
800
10
1000
12
11
13
0
14
tpc - CYCLE TIME (ns)
Voo - SUPPLY VOL TAGE (VOLTS)
GRAPH 16
TYPICAL OUTPUT SOURCE CURRENT
IOH VS. OUTPUT VOLTAGE VOH
GRAPH 17
TYPICAL OUTPUT SINK CURRENT
IOL VS. OUTPUT VOLTAGE VOL
20
40
60
80
TA - AMBIENT TEMPERATURE lOCI
NOTES:
....
fii
80
T A =2S C
VOO "" 12.0V
Vas = -S.SV
Q
a:
a:
=>
"w
"a:=>
1il
....
....~
=>
0
I
V cc =4.5V -
60
40
are indicated:
100
100
;;E
:---
20
~
E
o
o
--r-- ---
V OH -OUTPUTVOLTAGE (VOLTS)
;;E
....
T A ""!25 C
O
80
f-- voo' 12.0V
Vss '" -5.5V
Vce '" 4.5V
fii
''=>""
'Oiz"
u
....
40
I
20
IDOl @VDD= 13.2V, TA
•
IDD2 or I DD3 @ tRAS = 200ns, tRC =
375ns, VDD = 12.0V, T A = 25°C
750ns, VDD
/
a=>
.9
= O°C
•
A I DD2 or I DD3 @ tRAS = 500ns, tRC =
60
~
1. The cycle time, VDD supply voltage, and
ambient temperature dependence of I DD1,
IDD2, IDD3 and IDD4 is shown in related
graphs. Common points of related curves
V
.IV
o
o
VOL - OUTPUT VOL TAGE (VOLTS)
3-124
o
= 12.0V, TA = 25°C
I DD4 @ tCAS = 135ns, tpc = 225ns,
VDD = 12.0V, TA = 25°C
t:,. I DD4 @ tCAS = 350ns, tpc = SOOns,
VDD = 12.0V, TA = 25°C
The typical I DD current for a given combination of cycle time, V DD supply
voltage and ambient temperature may be
determined by combining the effects of
the appropriate family of curves,
2117 FAMILY
D.C. AND A.C. CHARACTERISTICS, PAGE MODE I7 ,8,11]
TA
= O°C
to 70°C, VDD
= 12V±100f0, Vee = 5V±100f0,
VBB
= -5V±100f0, Vss = OV,
unless otherwise noted.
For Page Mode Operation order 2117-2 S6053, 2117·3 S6054, or 2117-4 S6055.
2117-2
S6053
Symbol
Parameter
tpc
Min.
Max.
2117-4
S6055
2117-3
S6054
Min.
Max.
Min.
Max.
Unit
Page Mode Read or Write Cycle
170
225
275
ns
ns
tpCM
Page Mode Read Modify Write
205
270
340
tcp
CAS Precharge Time, Page Cycle
60
80
100
tRPM
RAS Pulse Width, Page Mode
150
10,000
200
10,000
250
10,000
tCAS
CAS Pulse Width
100
10,000
135
10,000
165
10,000
ns
1004
Voo Supply Current Page Mode,
Minimum tpc, Minimum tCAS
26
mA
38
30
Notes
ns
ns
9
WAVEFORMS
PAGE MODE READ CYCLE
~----------------------------tRPM------------------------------~b
_VIHC
RAS
l::::::::~~:::::::::j--------------------~(ff--j:::::::~:;:::::::
' •
tRSH
tRP
_ V 1HC
CAS V 1L
ADDRESSES
WE
~IH
"--~~~~~~~~~------~~~~~~------~~~tT~-i~----+------------------
V 1HC
+-__J
V,L _____
V OH
Dour
NOTES:
VOl----------------------~~
1,2. V 1H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT'
5. tOFF IS MEASURED TO lOUT';;; IlLO I.
6. tRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST.
7. ALL VOLTAGES REFERENCeD TO Vss.
8. AC CHARACTERISTIC ASSUME tr '" 5ns.
9. SEe THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNDER ALTERNATE CONDITIONS.
REOUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CAS10.
ONLY CYCLE (Le.• FOR SYSTEMS WHERE CAS HAS NOT SEEN DECODED WITH R,AS).
11. ALL PREVIOUSLY SPECIFIED A.C. AND D.C. CHA·~ACTERISTICS ARE APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE (Le., 2117·3, 86054 WILL OPERATE AS A 2117-3).
tCRP
3-125
2117 FAMILY
PAGE MODE WRiTE CYCLE
_
V 1HC
RAS
VIL
I
ADDRESSES VIH
VIL __
WE
~~~~~~~~~~
______-4____
~~~~~
______ ____
~
~.r-
__
~~~~~~
______ ____________
~
V 1HC
VIL------~----_H~~--~r_----------~~------~-----------i~--_tp_------_1r_----_r------------
PAGE MODE READ-MODiFY-WRiTE CYCLE
K
tRPM
Gi" ®
'1
.J
~tRCD
eD r\"
I---tAR
ASR_
ADDRESSES
V IH
V"
leSH
h'~
®
'c,w
'---"w,~
~tASC
~g~
ItRCSj
-- _
tCRW~
Jr----,
@
t-l:: ,,,'
eD)C ~g~X)
1\
tcP'"
K
-'owo~
®,JeD
~'w'}
h
tDs
~
®"'$:
I---tRAC
IMPEDANCE
NOTES:
@)lL-
11I
tOH®
1-
8M:DATAIN
2
VALID
HIGH
H'c,"
tASC-1
){
tRCS
I---- tcwo___Jo
~'w'-Y_ r--k----.
VALID
DATA our
1<®
'-'""I
.l
~'w}
h
'0'
.XDATAIN
'o,,~
VAllO
DATA OUT
1,2. V 1H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. VOH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF Dour5. tOFF IS MEASURED TO lOUT 0:;; IILol.
6. tos AND tDH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
7. tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES'PRECEEDED BY A CASONLY CYCLE (i.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RASl.
3-126
tRCS
r--'cwo~
'0'11<-
~DATAIN~
VALID
'o,,~
j
;g~x
tOH
'0'1 '-
K
'
'
"
---1K.
tI'c,"
~"w,--I
t---'cw,~
){ ;g~J(
t-tRWD_
®
tAsc1
".......... s----,
'-'cA',
VALID
K
tOFF ........
VALID
DATA OUT
2117 FAMILY
APPLICATIONS
READ CYCLE
DATA OUTPUT OPERATION
A Read cycle is performed by maintaining Write Enable
(WE) high during a RAS/CAS operation. The output pin of
a selected device will remain in a high impedance state
until valid data appears at the output at access time.
The 2117 Data Output (Dour), which has three-state
capability, is controlled by CAS. During CAS high state
(CAS at VIH) the output is in the high impedance state. The
following table summarizes the Dour state for various
types of cycles.
Device access time, tACC, is the longer of the two
calculated intervals:
1. tACC = tRAC OR 2. tACC = tRCD
Intel 2117 Data Output Operation
for Various Types of Cycles
+ tCAC
Access time from RAS, tRAC, and access time from CAS,
tCAC, are device parameters. Row to column address
strobe delay time, tRCD, are system dependent timing
parameters. For example, substituting the device parameters of the 2117-3 yields:
REFRESH CYCLES
Each of the 128 rows of the 2117 must be refreshed every 2
milliseconds to maintain data. Any memory cycle:
DouT State
Read Cycle
Data From Addressed
Memory Cell
HI-Z
HI-Z
HI-Z
Data From Addressed
Memory Cell
Indeterminate
Fast Write Cycle
RAS-Only RefrElsh Cycle
CAS-Only Cycle
Read/Modify/Write Cycle
3. tACC = tRAC = 200nsec for 25nsec :5tRCL :565 nsec
OR
4. tACC = tRCD + tCAC = tRCD + 135 for tRCD > 65nsec
Note that if 25nsec :5tRCD :565nsec device access ti me is
determined by equation 3 and is equal to tRAC. If tRCL
>65nsec, access time is determined by equation 4. This
40nsec interval (shown in thetRCD inequality in equation 3)
in which the falling edge of CAS can occur without
affecting access time is provided to allow for system
timing skew in the generation of CAS.
Type of Cycle
Delayed Write Cycle
HIDDEN REFRESH
A feature of the 2117 is that refresh cycles may be
performed while maintaining valid data at the output pin.
This feature is referred to as Hidden Refresh. Hidden
Refresh is performed by holding CAS at VIL and taking
RAS high and after a specified precharge period (tRP),
executing a "RAS-Only" refresh cycle, but with CAS held
low (see Figure below).
1. Read Cycle
2. Write Cycle (Early Write, Delayed Write or ReadMQ~ify-Write)
3. RAS-only Cycle
RAs
refre~hes
the setlected row as defined by the low order
(RAS) addresses. Any Write cycle, of course, may change
the state of the selected cell. USing a Read, Write, or ReadModify-Write cycle for refresh is not recommended for
systems which utilize "wire-OR" outputs since output bus
contention will occur.
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A RASonly refresh cycle maintains the Dour in the high
impedance state with a typical power reduction of 20%
over a Read or Write cycle.
W/CAS TIMING
RAS and CAS have minimum pulse widths as defined by
tRAS and tCAS respectively. These minimum pulse widths
must be maintained for proper device operation and data
integrity. A cycle, once begun by driving RAS and/or CAS
low must not be ended or aborted prior to fulfilling the
minimum clock signal pulse width(s). A new cycle can not
begin until the minimum precharge time, tRP, has been
met.
3-127
-{
"""~.=1
r---{\-__
CY..J!
\
/
MEMORY
CYCLE
CAS
HIGHZ
DOUT
(
DATA
}-
\ . - - _ " ' - - - _ _.....J
This feature allows a refresh cycle to be "hidden" among
data cycles without affecting the data availability.
POWER ON
The 2117 requires no power on sequence providing
absolute maximum ratings are not exceeded. After the
application of supply voltages or after extended periods of
bias (greater than 2 milliseconds) without clocks, the
device must perform a minimum of eight initialization
cycles (any combination of cycles containing a RAS clock,
such as RAS-Only refresh) prior to normal operation.
2117 FAMILY
POWER SUPPLY DECOUPLING/DISTRIBUTION
I
It is recommended that a 0.1!,F ceramic capacitor be
connected between Voo and Vss at every other device in
the memory array. A 0.1!,F ceramic capacitor should also
be connected between Vee and Vss at every other device
(preferably the alternate devices to the Voo decoupling).
For each 16 devices. a 10!,F tantalum or equivalent
capacitor should be connected between Voo and Vss near
the array. An equal or slightly smaller bulk capacitor is
also recommended between Vee and Vss for every 32
devices.
The Vee supply is connected only to the 2117 output
buffer and is not used internally. The load current from the
Vee supply is dependent only upon the output loading and
1
is associated with the input high level current to a TTL gate
and the output leakage currents of any OR-tied 2117's
(typically 100!,A or less totaD. Intel recommends that a 0.1
or 0.01!,F ceramic capacitor be connected between Vee
and Vss for every eight memory devices.
Due to the high frequency characteristics of the current
waveforms. the inductance of the power supply distribution system on the array board should be minimized. It is
recommended that the Voo. Vee. and Vss supply lines be
gridded both horizontally and vertically at each device in
the array. This technique allows use of double sided
circuit boards,with noise performance equal to or better
than multi-layered circuit boards.
.2.
.r.LO
. i'ro
..
:....
l
'tI~
~
RASO
RASC
WECO
'r~
WEAe
RASB
RASA
. ./
. "'!i"':;;.
:.
i
:
,'"
6:t;iii~~
....
•
OECOUPLING CAPACITORS
0= O.lI'F TO VOD TO VSS
B = O.lI'F Ves TO Vss
C = O.OlI'F VCC TO VSS
•
CASCO
ASCD
ASCD
A4CO
A3CO
A2CD
A1CD
AOCD
"-
..
11
CASAe
ASAB
ASAB
A4AB
A3AB
A2AB
A1AB
AOAB
• •
SAMPLE P.C. BOARD LAYOUT EMPLOYING VERTICAL
AND HORIZONTAL GRIDOING ON ALL POWER SUPPLIES.
BOARD ORGANIZATION: S4K WORDS BY a·BITS.
64K BYTE STORAGE ARRAY LAYOUT
3·128
inter
2141
4096 X 1 BIT STATIC RAM
2141-2
2141-3
2141-4
2141-5
2141L-3
2141L-4
2141L-5
Max. Access Time (ns)
120
150
200
250
150
200
250
Max. Active Current (mA)
70
70
55
55
40
40
40
Max. Standby Current (mA)
20
20
12
12
5
5
5
Technology
• Automatic Power-Down
• HMOS
Directly TTL Compatible - All Inputs
Industry Standard 2147 Pinout
•
• Completely
and Outputs
Static Memory - No Clock
• or Timing Strobe
Separate Data Input and Output
Required
•
Three-State
Output
Equal Access and Cycle Times
•
• Single
+5V Supply
•
• High Density 18-Pin Package
The Intel® 2141 is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using HMOS, a highperformance MOS technology. It uses a uniquely innovative design approach which provides the ease-ol-use features
associated with non-clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
es controls the
power-down feature. In less than a cycle time after es goes high - deselecting the 2141 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as es remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are deselected.
The 2141 is placed in an 18-pin package configured with the industry standard pinout, the same as the 2147. It is directly
TTL compatible in all respects: inputs, outputs, and a single +5V supply. The data is read out nondestructively and has the
same polarity as the input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
AO
Vee
A,
A6
LOGIC SYMBOL
AO
A,
A,
A3
As
A4
A9
A6
A5
A,o
Dour
A"
D,N
GND
@
A,
A,
A3
A4
A5
WE
BLOCK DIAGRAM
-Vee
~GND
DOUT
MEMORY ARRAY
64 ROWS
64 COLUMNS
A,
As
A9
A,o
A"
CS
DIN WE CS
D,N
PIN NAMES
Ao-A"
WE
CS
D,N
DOUT
ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT
DATA OUTPUT
Vee POWER (+5VI
GND GROUND
TRUTH TABLE
CS
WE
H
L
L
X
L
H
MODE
NOT SE LECTED
WRITE
READ
@
-=-----1
CS
OUTPUT
POWER
HIGH Z
HIGH Z
STANDBY
ACTIVE
ACTIVE
DOUT
WE
3-129
(j)
1-----==:::..:..:~==~--fIi1'"-
Dour
2141
:{' rr-".,s"
'COMMENT: Stresses above those I~
Maximum Ratings" may cause permanen¥'tJl!
device. This is a stress rating only and func(ibfraL.
tion of the device at these or any other condition;'iibp
those indicated in the operational sections of this speciff.
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
I
TemperatureUnderBias .•...........•• -to·CtoS5·C
Storage Temperature ............... -65·Cto+t50·C
Voltage on Any Pin With
Respeetto G rou nd ....•............... -0.5V to +7V
D.C. Output Current ....................•..... 20 mA
D.C. AND OPERATING CHARACTERISTICS
TA = o·c to 70·C, Vcc = +5V±10% unless otherwise noted.
Symbol
2141-2/-3
2141 L-3/L-4/L-5
2141-4/-5
Min. TypJ1J Max. Min. TypJ1J Max. Min. Typ.llJ Max.
Unit
Conditions
III
In p ut Load Cu rrent
(All Input Pins)
0.01
10
O.ot
10
0.01
10
I'A
Vee=Max., VIN=
GND to Vee
IILol
Output Leakage
Current
0.1
10
0.1
10
0.1
10
I'A
CS=VIH, Vee=Max.,
VouT=GND to 4.5V
lee
Operating Current
rnA
TA=25°C Vee-Max.
CS=VIL,
TA=O· C
Outputs Open
ISB
Parameter
45
40
30
I
I
70
55
40
rnA
Standby Current
20
12
5
rnA
Vee-Min. to Max.,
CS=VIH
Ipol2)
Peak Power-On
Current
40
30
18
rnA
Vee=GND to Vee Min.
CS=Lower of Vee or
VIH Min.
VIL
Input Low Voltage
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
VIH
)nput High Voltage
2.0
6.0
2.0
6.0
2.0
6.0
V
VOL
Output Low Voltage
0.4
V
10L =4.0mA
VOH
Output High Voltage
V
10H = -2001'A
0.4
2.4
0.4
2.4
2.4
Notes: 1. Typical limits are at Vee = 5V, TA = +25°C, and specified loading.
2. lee exceeds ISB maximum during power-on, as shown in Graph 1. A pull-up resistor to Vee on the
keep the device deselected; otherwise, power-on current approaches lee active.
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference
Levels
Output Load
GND to 3.5 Volts
10 nsec
CS input is required to
GRAPH 1
TYPICAL POWER-ON CURRENT
VS. POWER SUPPL Y VO_L TAGE
2.0,..---r-----.--.,.----r---,
IPO
1.5 Volts
1 TTL Load plus 100pF
1.6i---+---:lH-----'r--+---;
1.21-----¥---+----+-~od-----I
CAPACITANCE [31
ISB
TA = 25°C, f = 1.0MHz
Symbol
Parameter
CIN
Input Capacitance
CoUT
Output Capacitance
Max. Unit
Conditions
5
pF
VIN =OV
10
pF
VOUT = OV
.4~--4----+----+----r--~
TA - 25'C
1 KIl
1.0
Note 3. This parameter Is sampled and not 100% tested.
CS PULL-UP RESISTOR TO Vee
2.0
3.0
Vee IV)
3-130
4.0
5.0
2141
A.C. CHARACTERISTICS
TA = O°C to 70°C, Vee = +5V±5%, unless otherwise noted.
READ CYCLE
2141·2
Parameter
Symbol
Min.
2141·3/L·3
Max.
Min.
Max.
2141-4/L·4
Min.
2141-S/L-S
Min.
Max.
Max.
Unit
tRC
Read Cycle Time
tAA
Address Access Time
120
150
200
250
ns
tACS1[1]
Chip Select Access Time
120
150
200
250
ns
tACS2[2]
Chip Select Access Time
130
160
200
250
ns
tOH
Output Hold from Address Change
10
10
10
10
tLZ
Chip Selection to Output in Low Z
10
10
10
10
tHZ
Chip Deselection to Output in High Z
0
tpu
Chip Selection to Power Up Time
0
tpo
Chip Deselection to Power Down Time
120
150
60
0
200
60
0
60
ns
250
0
60
ns
ns
0
0
ns
60
0
80
ns
100
100
ns
WRITE CYCLE
2141-2
Symbol
Parameter
Min.
2141-3/L-3
Min.
Max.
Max.
2141-4/L-4
Min.
2141-S/L-5
Min.
Max.
Max.
Unit
twc
Write Cycle Time
120
150
200
250
ns
tcw
Chip Selection to End of Write
110
135
180
230
ns
tAW
Address Valid to End of Write
110
135
180
230
ns
tAS
Address Setup Time
0
0
0
0
ns
twp
Write Pulse Width
60
70
100
150
ns
tWR
Write Recovery Time
10
15
20
20
ns
tow
Data Valid to End of Write
50
60
90
130
ns
tOH
Data Hold Time
10
twz
Write Enabled to Output in High Z
0
tow
Output Active from End of Write
0
15
15
60
0
60
0
ns
15
0
60
0
0
ns
60
ns
0
WAVEFORMS
READ CYCLE NO.
ADDRESS
1[3,4J
-f=~_~,.~~~_~'
---1=-tOH--~--------1
DATA OUT
PREVIOUS DATA VALID
*XX
READ CYCLE NO.
f-
--------
WRITE CYCLE
._-------]
I
*---
ADDRess
·lb-,.:W--~l
*r----DA-T-A-VA..,-L'CC'D------
--',,-----I
2[3,5]
WE
-tRc----
DATA IN
~--~tlZ
tACS_~
_
DATA OUT -+~H~'G~H~'M~PE~DA~N~CE~tl~=*======~~~~~==j
DATA VALID
~3~PLY
t-
=f-------.~
DATA OUT
(d
II II
r~ twp-------r WR
'I<
r·
*
DATA UNDEFINED
~-tDW~
DATA IN VALID
- - twz
4
~
t OH
-1
*
-'ow---I
HIGH IMPEOANCE
~
"u
Icc
~~--------------
·_ - - - - - -
CURRENT IS8
Notes: 1. Chip deselected for greater than 55ns prior to selection.
2. Chip deselected for a finite time that is less than 55ns prior to selection. Ilf the deselect time is Ons. the chip is by definition
selected and access occurs according to Read Cycle No. 1.1
3. WE IS high for Read Cycles.
4. Device is continuously selected, CS = VIL.
5. Addresses valid prior to or coincident with CS transition low.
3·131
2141
DEVICE DESCRIPTION
The 2141 is produced with HMOS, a new highperformance MOS technology which incorporates onchip substrate bias generation to achieve high- performance. This process, combined with new design ideas,
gives the 2141 its unique features. Both low power and
ease-of-use have been obtained in a single part. The lowpower feature is controlled with the Chip Select input,
which is not a clock and does not have to be cycled.
Multiple read or write operations are possible during a
single select period. Access times are equal to cycle times,
resulting in data rates up to 8.3 MHz for the 2141-2. This is
considerably higher performance than for clocked static
designs.
Whenever the 2141 is deselected, it automatically reduces
its power requirements to a fraction of the active power, as
shown in Figure 1. This is achieved by switching off the
power to unnecessary portions of the internal peripheral
circuitry. This feature adds up to significant system power
savings. The average power per device declines as system
size grows because a continually higher portion of the
memory is deselected. Device power disSipation asymptotically approaches the standby power level, as shown in
Figure 2.
There is no functional constraint on thearT\o
2141 is deselected. However, there is a' 'r,s
between deselect time and Chip Select access t1.
no compensation, the automatic power switch woold",
cause an increase in Chip Select access time, since sonl"e;
time is lost in repowering the device upon selection. A
feature of the 2141 design is its ability to compensate for
this loss. The amount of compensation is a function of
deselect time, as shown in Figure 3. For short deselect
times, Chip Select access time becomes slower than
address access time, since full compensation typically
requires 60ns. For longer deselect times, Chip Select
access time actually becomes faster than address access
ti me because the compensation more than offsets the ti me
lost in powering up. The spec accounts for this
characteristic by specifying two Chip Select access times,
tACS1 and tACS2.
11:=8----t1[
o
60
80
DESELECT TIME (n5)
FIGURE 3. tACS VS. DESELECT TIME.
The power switching characteristic of the 2141 requires
more careful decoupling than would be required of a
constant power device. It is recommended that a 0.1/LF
ceramic capaCitor be used on every other device, with a
22/LF to 47/LF bulk electrolytic decoupler every 32 devices.
The actual values to be used will depend on board layout,
trace widths and duty cycle. Power supply gridding is
recommended for PC board layout. A very satisfactory
grid can be developed on a tWO-layer board with vertical
traces on one side and horizontal traces on the other, as
shown in Figure 4.
VCC--i~"'_...j
FIGURE 1. icc WAVEFORM.
ICC
0:
w
;:
2
w
(J
:;
w
Q
w
<.'l
-
'"
'"
>
ISB
4K 8K 16K
32K
64K
MEMORY SIZE IN WORDS
FIGURE 2. AVERAGE DEVICE DISSIPATION VS.
MEMORY SIZE.
3·132
2142
1024 X 4 BIT STATIC RAM
I
2142-2
200
525
Max. Access Time (ns)
I
Max. Power Dissipation (mw)
2142-3
300
525
High Density 20 Pin Package
•• Access
Time Selections From 200-450ns
Identical
Cycle and Access Times
• Low Operating
• .1mW/Blt TypicalPower Dissipation
• Single +5V Supply
2142
450
525
2142L3
300
370
2142L2
200
370
2142L
450
370
No Clock or Timing Strobe Required
• Completely
Memory
• Directly TTLStatic
Compatible:
All Inputs
• and Outputs
Common Data Input and Output Using
• Three-State
Outputs
The Intel@ 2142 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel SiliconGate MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The 2142 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing
are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
The 2142 is placed in a 2o-pin package. Two Chip Selects (CS1 and CS2) are provided for easy and flexible selection of
individual packages when outputs are OR-tied. An Output Disable is included for direct control of the output buffers.
The 2142 is fabricated with Intel's N-channel Silicon-Gate technology - a technology providing excellent protection
against contamination permitting the use of low cost plastic packaging.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
.
A3
As
.
As
Vee
Ao
A,
A,
.,
A,
.
AJ
As
es,
00
Ao
I/O,
As
A,
1/02
A,
A,
1/03
A,
cs,
110,
As
AJ
I/O,
A,
As
I/o,
A,
A,
@)
®
®
CD
®
®
ROW
SELECT
64 COLUMNS
1/03
1/04
1/02
INPUT
DATA
WE
GND
MEMORY ARRAY
64 ROWS
1/03
=----N-+-+--D~_I
CONTROL
PIN NAMES
AI) Ag
ADDRESS INPUTS
00
OUTPUT DISABLE
WE
WRITE ENABLE
Vee
POWER (+5V)
B1. CS2
CHIP SELECT
GND
GROUND
1/01-1/04
DATA INPUT/OUTPUT
o
00
3·133
=
PIN NUMBERS
~vcc
~GND
2142 FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliabifity.
Temperature Under Bias ............ -10°Cto aoOc
Storage Temperature ......•...•..._65°C to +150°C
Voltage on Any Pin
With Respect to Ground ........... -0.5V to +7V
Power Dissipation
. . . . . . . . . . . . . . . .. 1.0W
D.C. Output Current .•................... 10mA
D.C. AND OPERATING CHARACTERISTICS
TA = o°c to 70°C, Vcc = 5V ± 5%, unless otherwise noted.
SYMBOL
PARAMETER
2142-2, 2142-3, 2142
Min. Typ,l11 Max.
Input Load Current
(All Input Pins)
ILl
2142L2,2142L3,2142L
Min. Typ,l11 Max.
UNIT
CONDITIONS
10
10
JlA
VIN = 0 to 5.25V
10
10
JlA
CS= 2.4V,
VIIO = O.4V to Vcc
95
65
mA
VIN = 5.25V, 1110 = 0 mA,
TA=25°C
100
70
mA
VIN = 5.25V, 1110 = 0 mA,
TA =; O°C
0.8
V
,
IILol
I/O Leakage Current
ICCl
Power Supply Current
ICC2
Power Supply Current
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
10L
Output Low Current
2.1
6.0
2.1
6.0
mA
VOL = O.4V
10H
Output High Current
-1.0
-1.4
-1.0
-1.4
mA
VOH = 2.4V
108[21
Output Short Circuit
Current
mA
Vito = GND to VCC
80
0.8
-0.5
6.0
2.0
6.0
40
40
V
NOTE: 1. Typical valuesare for TA = 2SoCand Vee = S.OV.
2. Duration not to exceed 30 seconds.
CAPACITANCE
TA = 25°C, f = 1.0 MHz
SYMBOL
MAX
UNIT
CliO
Input/Output Capacitance
TEST
5
pF
CONDITIONS
Vila = OV
CIN
Input Capacitance
5
pF
VIN = OV
NOTE: This parameter is periodically sempled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels • . • . . • • . • . . . . . . • • • • • • • . . • . . • . . • . . . . .. 0.8 Volt to 2.4 Volt
Input Rise and Fall Times ....•••••...••.......•..••..•••••.••..•.. 10 nsec
Input and Output Timing Levels .•.••••.••.••••.• , .••••..••......... 1.5 Volts
Output Load •.•••••.•.•••.•.•••..••..•.••...... 1 TTL Gate and CL = 100 pF
3·134
2142 FAMILY
A.C. CHARACTERISTICS
READ CYCLE
TA = o°c to 70°C, Vee = 5V ± 5%, unless otherwise noted.
[1]
PARAMETER
SYMBOL
tRe
Read Cycle Time
tA
Access Time
tOD
Output Enable to Output Valid
tODX
Output Enable to Output Active
tco
Chip Selection to Output Valid
tcx
Chip Selection to Output Active
tOTD
Output 3-state from Disable
tOHA
Output Hold from Address Change
WRITE CYCLE
2142·2,2142L2
Min.
Max.
2142,2142L
Max.
Min.
2142-3,2142L3
Max.
Min.
200
450
300
ns
300
200
70
100
20
ns
20
100
50
ns
ns
80
50
120
120
20
60
ns
ns
100
70
450
20
20
20
UNIT
50
ns
ns
[2]
PARAMETER
SYMBOL
2142-2,2142L2 2142-3, 2142L3
Max.
Min.
Max.
Min.
twe
Write Cycle Time
200
tw
Write Time
120
tWR
Write Release Time
0
tOTD
Output 3-state from Disable
tDW
Data to Write Time Overlap
tDH
Data Hold From Write Time
UNIT
300
450
ns
150
200
ns
0
0
80
60
120
2142,2142L
Max.
Min.
ns
100
ns
150
200
ns
0
0
ns
0
NOTES:
1. A Read occurs during the overlap of a low CS and a high WE.
2. A Write occurs during the overlap of a low es and a low WE.
WAVEFORMS
READ CYCLE@
WRITE CYCLE
1--------tRc-----+I
tA--
ADDRESS
'wc
ADDRESS
--~~-----------------r-JI'~---00
---..
-
tWR-
~
,\\ \ \ \ \
U
~tOTO+
\\\ 1\\\\ ,\\
cs,
'/ / II II / /
1// 'i// 1//
,\\\"""''\~
tw
DOUT
----------------------l@;:==~
,\ \ \ ,\ \
DOUT
NOTES:
@
OIN----~t~__-__- -.!rJ~1" '" XMX ~X>
tDW~
WE is high for a Read Cycle.
® WE must be high during all address transitions.
3-135
~tDH
2142 FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
1.2
1.2
---
1.1
1.0
I'---
~
53NO.9
::;
~
0.8
Ii!
-
::;
"~
Ii!
0.6
0.6
0.5
5.00
1. 1
1.0
/
5.25
5.50
20
60
40
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
--
..-
1.2
1 .1
1.0
~
u
u
o.9
~
o. 8
::;
~
a:
N
0.9
N
~
0.7
0.6
0.8
~
-
~
0.7
0.6
O. 5
100
200
300
400
500
20
600
60
CL (pFI
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
1
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
40
40
30
30
20
10
80
T. i"CI
~
~
o
-
Vee (VI
1.2
::;
~
0.8
0.7
4.75
------
1.0
~
53NO.9
0.7
0.5
4.50
fa
1. 1
'"
o
o
1
-
\~
'\
20
10
"'-.
/
V
/'
~
V
o
o
VOH (VI
VOL
3·136
IVI
80
M2142
1024 X 4 BIT STATIC RAM
2142
I
I
Max. Access Time (ns)
450
Max. Power Dissipation (mw)
550
• No Clock or Timing Strobe Required
• Completely Static Memory
• Directly TTL Compatible: All Inputs
and Outputs
• High Density 20 Pin Package
• Access Time -450ns
• Identical Cycle and Access Times
• Low Operating Power Dissipation
.1 mWIBIt Typical
• Common Data Input and Output Using
Three-State Outputs
• Single +5V Supply
The Intell!> M2142 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel SiliconGate MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The M2142 is designed for memory applications where high performance, large bit storage, and simple interfacing are
important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
The M2142 is placed in a 20-pin package. Two Chip Selects (CS1 and CS2) are provided for easy and flexible selection of
individual packages when outputs are OR-tied. An Output Disable is included for direct control of the output buffers.
PIN CONFIGURATION
..
A,
A4
LOGIC SYMBOL
A3
Vee
..
A,
A,
A,
A:3
es,
00
A,
..
AO
I/O,
A,
J/02
A,
1/03
A,
1/04
A,
CS1
®
A4
lID,
A5
A.
0
@
AO
A3
GNO
BLOCK DIAGRAM
A,
---------0
0
ROW
SELECT
CD
MEMORY ARRAY
64 ROWS
64 COLUMNS
@i
1/02
A,
@i
A,
A5
1/03
I/O,
1/04
1102
INPUT
w-
DATA
CONTROL
1/03
1/04
PIN NAMES
Ao-Ag
00
OUTPUT DISABLE
WE
ADDRESS INPUTS
WRITE ENABLE
Vee
POWER (+5V)
1. CS2
I/O, 1/04
CHIP SELECT
DATA INPUT/OUTPUT
GNO
GROUND
o~
3·137
PIN NUMBERS
@
_______.--0
Vee
GNO
inter
2147
40.96 X 1 EJIT STATI.C, flAM
I
Max. Access Time (ns)
Max. Active Current (mA)
Max. Standby Current (mA)
• HMOS Technology
• Completely Static Memory - No Clock
or Timing Strobe Required
• Equal Access and Cycle Times
2147
70
160
20
2147-3
55
180
30
2147L
70
140
10
• Automatic Power-Down
• High Density 18-PlnPackage
• Directly TTL Compatible - All Inputs
and Outputs
• Separate Data Input and Output
• Single +5V Supply
• Three-State Output
The Intel@> 2147 is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using HMOS, a highperformance MOS technology. It uses a uniquely innovative design approach which provides the ease-of-use features
associated with non-clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, 'address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high - deselecting the 2147 - the part
a.utomatically reduces its power requirements and remains in this low power standby mode as long as CS remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are deselected.
The 2147 is placed in an 18-pin package configured with the industry standard pinout. It is directiy TTL compatible in all
respects: inputs, outputs, and a single +5V supply. The data is read out nondestructively and has the same polarity as the
input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
LOGIC SYMBOL
Vee
@
A,
A6
L-_---',-
BLOCK DIAGRAM
Ao
A7
A2
A3
A4
A.
As
As
Aa
A,.
A7
AS
A"
A.
~vcc
. - - - - GND
DOUT
ROW
=---,~..----,SELECT
D,N
A,.
Cs
D,N WE CS
A"
PIN NAMES
Ao-A" ADDRESS INPUTS
WRITE ENABLE
WE
CHIP SELECT
CS
DATA INPUT
D,N
DATA OUTPUT
!>oUT
Vee POWER I+5VI
llND GROUND
TRUTH TABLE
a
WE
H
L
L
X
L
H
MODE
NOT SELECTED
WRITE
READ
OUTPUT
HIGHZ
HIGHZ
!>oUT
POWER
STANDBY
ACTIVE
ACTIVE
3-138
MEMORY ARRAY
64 ROWS
64 COLUMNS
2147
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TemperatureUnderBias ............... -10°Ct085°C
Storage Temperature ............... -65°Cto+150°C
Voltage on Any Pin With
RespeettoGround .................... -0.5Vto+7V
D.C. Output Current .......................... 20 mA
D.C. AND OPERATING CHARACTERISTICS I1 ]
TA = O°C to 70°C, Vee = +5V ±5%, unless otherwise noted.
Symbol
Parameter
2147-3
2147
2147L
Min. Typ. 12] Max. Min. Typ.12] Max. Min. Typ. [2] Max.
Unit
Test Conditions
III
Input Load Current
(All I nput Pins)
0.01
10
0.01
10
0.01
10
/-I A
Vee=MAX, VIN=GND to Vee
IILOI
Output Leakage
Current
0.1
50
0.1
50
0.1
50
/-I A
CS=VIH. Vee=Max.,
VouFGND to 4.5V
Icc
Operating Current
120
170
100
150
100
135
mA
140
mA
180
160
I
I
TA=25°C Vee=Max., CS=VIL,
TA=O°C
Outputs Open
ISB
Standby Current
18
30
12
20
7
1.0
mA
Vee=Min. to Max.
CS=VIH
Ipo 13]
Peak Power-On
Current
35
70
25
50
15
30
mA
Vee=GND to Vee Min.,
CS=Lower of Vee or VIH Min.
VIL
Input Low Voltage
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
VIH
Input High Voltage
2.0
6.0
2.0
6.0
2.0
6.0
V
VOL
Output Low Voltage
0.4
V
10L = 8mA
VOH
Output High Voltage 2.4
V
10H = -4.0mA
0.4
0.4
2.4
2.4
Notes:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
2. Typical limits are at Vee = 5V, TA = +25° C, and specified loading.
3. Icc exceeds ISB maximum during power on, as shown in Graph 7. A pull-up resistor to Vee on theCS input is required to keep the device
deselected; otherwise, power-on current approaches Icc active.
A.C. TEST CONDITIONS
vee
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference
Levels
GND to 3.5 Volts
10 nsec
1.5 Volts
See Figure 1
Output Load
510"
---+
DouT - - -......
300"
30 pF
(INCLUDING
AND
SCOPE
JIG)
Figure 1. Output Load
CAPACITANCE
TA = 25°C, f = 1.0MHz [4]
Symbol
Parameter
Max. Unit
Conditions
GIN
Input Capacitance
5
pF
VIN =OV
GOUT
Output Capacitance
7
pF
VOUT = OV
Note 4. This parameter is sampled and not 100% tested.
3·139
2147
A.C. CHARACTERISTICS
TA
= O·C to 70·C, Vcc = +5V±5%, unless otherwise noted.
READ CYCLE
Symbol
Parameter
Min.
2147-3
Max.
2147, 2147L
Min.
Max.
Unit
Test
Conditions
tRC
Read Cycle Time
tAA
Address Access Time
55
70
ns
tACS1
Chip Select Access Time
55
70
ns
Note 1
tACS2
Chip Select Access Time
65
80
ns
Note 2
tOH
Output Hold from Address Change
5
tLZ
Chip Selection to Output in Low Z
10
tHZ
Chip Deselection to Output in High Z
0
tpu
Chip Selection to Power Up Time
0
tpD
Chip Deselection to Power Down Time
55
70
ns
ns
5
10
40
0
ns
40
30
ns
ns
0
30
ns
WAVEFORMS
READ CYCLE NO.1 [3.4)
----,..----*~~r:_____
-___~_A_~_~_~_~~~.I
~-------------------------'RC---------------------------l~
ADDRESS
_
DATA OUT
-'oH-----li X X .._ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
I'4-l.
lIS: __ __
PREVIOUS DATA VALID
DATA VAllO
READ CYCLE NO.2 [3,5)
'RC
~
tACS
-,"z-
tlZ
DATA OUT
HIGH IMPEDANCE
r---
VCC
SUPPLY
CURRENT
XX
f-
HIGH
DATA VALID
IMPEDANCE
::---n-jr-------=L
i--- tPD
tpu
Notes: 1. Chip deselected for greater than 55ns prior to selection.
2. Chip deselected for a finite time that is less than 55ns prior to selection. (If the deselect time is Ons, the chip is by definition
selected and access occurs according to Read Cycle No. 1.)
3. WE is high for Read Cycles.
4. Device is continuously selected. CS = VIL.
5. Addresses valid prior to or coincident with CS transition low.
3·140
2147
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol
Parameter
Min.
twe
Write Cycle Time
tew
Chip Selection to End of Write
tAW
Address Valid to End of Write
tAS
Address Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End of Write
tOH
Data Hold Time
twz
Write Enabled to Output in High Z
tow
Output Active from End of Write
2147-3
Max.
55
45
45
0
35
10
25
10
0
0
2147,2147L
Min.
Max.
70
55
55
0
40
15
30
10
30
Unit
Test
Conditions
ns
ns
ns
ns
ns
ns
ns
ns
35
0
0
ns
ns
WRITE CYCLE
.
ADDRESS
twe
~
Il
.-..J
.
tew
s\
II
.
tAW
E
I------ tWR
twp
tAS
--0
-,1-
.. ....- tOH-+--
VALID
DATA IN
.....-..-twz
DATA OUT
I I I I
\
f-- j - - - - - t o w
DATA IN
V
I----tow
=1r------
HIGH IMPEDANCE
-----------0(1\
______
--------------------;
DATA UNDEFINED
..
3·141
2147
TYPICAL D.C. AND A.C. CHARACTERISTICS
GRAPH 1
SUPPL Y CURRENT[1) VS.
SUPPLY VOLTAGE
IcC
100
100
75
-- -
r--
=25'C
-
4.50
5.00
Vee IV)
4.75
~
.9 40
TA
40
('C)
o
60
80
1==00....
o
1.0
GRAPH 5
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
t'l
/
1.0
~
'AA
j
_ 60
~<
TA
0
w
= 25'C -
N
~
":;;a:
i!!
0
z
.8
.7
4.50
5.00
Vee (V)
4.75
5.25
.8
80
2.0
-- - -
1.6
/
7\
r-j - -
--
/
Jl
1_2
Is.
.8
.4
/
V
TA = 25'C
1Kn CS PULL·UP
1.0
2.0
GRAPH 8
ACCESS TIME CHANGE VS.
INPUT VOLTAGE
/
o
~~e:1 ~~~2.0
1.0
4.0
3.0
GRAPH 9
ACCESS TIME CHANGE VS.
OUTPUT LOADING
20
20
'"
j
-~
«
1ii
I-
>'"
'"
ISB
4K BK 16K
32K
MEMORY SIZE IN WORDS
64K
FIGURE 2. AVERAGE DEVICE DISSIPATION VS.
MEMORY SIZE.
Terminations are recommended on input signal lines to
the 2147 devices. In high speed systems, fast drivers can
cause significant reflections when driving the high
impedance inputs of the 2147. Terminations may be
required to match the impedance of the line to the driver.
The type of termination used. depends on designer
preference and may be parallel resistive or resistivecapacitive. The latter reduces terminator power disSipation.
3-143
2185
1024 X 8 BIT STATIC RAM
Operating Power Dissipation
• Low
Low Standby Power Dissipation
• Single
5V Power Supply
•
High
Density
18 Pin Package
• Fully Static Operation
•
Multiplexed Address and Data
• Fully
Lines
Directly Compatible with the MCS-85
• and
MCS-48 Microprocessor
No
Clock
or Timing Strobe Required
•
The Inte~2185 is an 8192-bit static Random Access Memory organized as 1024 words by 8-bit using N-channel SiliconGate MOS technology. It uses a uniquely innovative design approach which provides the ease of use features associated
with non clocked static memories and the reduced standby power dissipation associated with clocked static memories. To
the user this means low standby power dissipation without the need for clocks, address setup and hold times.
The 2185 is housed in an 18 pin package featuring a fully multiplexed address and data bus. It is directly compatible with
TTL in all respects: inputs, outputs and a single 5V supply.
PIN CONFIGURATION
BLOCK DIAGRAM
AD.
Vee
AD,
DE
WE
es
AD,
ALE
AD.
es
ALE
CE
CE
DE
WE
CE
AD.
RiW
LOGIC
CE
AD,
Aa
AOO-AD7 AND Aa-9
DATA
BUS
BUFFER
PIN NAMES
A...
A[lo-AD,
cs
CE,CE
ALE
DE
WE
ADDRESS LINE
ADDRESS AND DATA LINES
CHIP SELECT
CHIP ENABLE
ADDRESS LATCH ENABLE
OUTPUT ENABLE
WRITE ENABLE
ALE
3-144
1Kx 8
MEMORY ARRAY
inter
3101, 3101A
16 x 4 BIT HIGH SPEED RAM
• Fast Access Time -- 35 nsec. max.
over 0-75° C Temperature Range.
• OR-Tie Capability-Open Collector Outputs.
(3101A)
• Fully Decoded -- on Chip Address
Decode and Buffer.
• Simple Memory Expansion through
Chip Select Input--17 nsec. max.
overO-75°C Temperature Range.
• Minimum Line Reflection -- Low
Voltage Diode Input Clamp.
(3101A)
• Ceramic and Plastic Package -16 Pin Dual In-Line Configuration.
• DTL and TTL Compatible -- Low
Input Load Current:0.25mA. max.
The Intel@3101 and 3101A are high speed fully decoded 64 bit random access memories, organized 16 words
by 4 bits. Their high speed makes them ideal in scratch pad applications. An unselected chip will not generate
noise at its output during writing of a selected chip. The output is held high on an unselected chip regardless
of the state of the read/write signal.
The use of Schottky barrier diode clamped transistors to obtain fast switching speeds results in higher performance than equivalent devices with gold diffusion processes.
The Intel 3101 and 3101A are packaged in either hermetically sealed 16 pin ceramic packages, or in low cost
silicone packages, and their performance is specified over a temperature range from O°C to 75°C.
The storage cells are addressed through an on chip 1 of 16 binary decoder using four input address leads.
A separate Chip Select lead allows easy selection of an individual package when outputs are OR-tied.
In addition to the address leads and the Chip Select lead, there is a write input which allows data presented at
the data leads to be entered at the addressed storage cells.
PIN CONFIGURATION
LOGIC SYMBOL
., .,
cs
ADDRESS INPUT AD
CHIP SELECT
Cs
A, ADDRESS INPUT
WRITE ENABLE
WE
A2 ADDRESS INPUT
DATA INPUT 0,
AJ ADDRESS INPUT
.,
A,
DATA OUTPUT
0,
DATA INPUT 02
DATA OUTPUT 0'2
04 DATA INPUT
0'4 DATA OUTPUT
A,
A,
., .,
.,
D,
03 DATA INPUT
'OJ
ImTA OUTPUT
A•
A,
.,
.,
t-- 125
_O°C
~
~-150
-175
0.5
-200
0.4
Js.ov
--- --
i:'i
/1/
0.2
-50
I
j: -75
7S 0 C-..
20
INPUT THRESHOLD VOLTAGE
VS. AMBIENT TEMPERATURE
INPUT CURRENT
VS. INPUT VOLTAGE
0.6
OUTPUT VOLTAGE IVI
0.&
1.0
2.0
INPUT VOLTAGE (VI
3-146
3.0
0
25
50
AMBIENT TEMPERATURE (GC)
75
3101, 3101A
Switching Characteristics
Conditions of Test:
15 mA T... Lood
Input Pulse amplitudes: 2.5V
Input Pulse rise and fall times of
5 nanoseconds between 1 volt
and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 15mA and 30 pF
READ CYCLE
Address to Output Delay
~:.,
..'W~'
WRITE CYCLE
T------X
-_.iiI'
~
- ~---.
:S;18ns
"r
CH IPSE LECT INPUT
L"-1
CHIP SELECT INPUT
--~----,
Data may
~tow~
change
Chip Select to Output Delay
J'----=------------~
WRITE INPUT
~Ons
tWR
'-~18ns
01' 02' 03, 04
CHIP SELECT INPUT
(Selected Ch ips)'"
______ J
/"
*Outputs of unselected chips remain high dunng write cycle.
NOTE 1:
tSR is associated with a read cycle following a write cycle and does not affect the access time.
A.C. Characteristics
TA
=
DoC to +75°C, VCC = 5.0V ±5%
READ CYCLE
SYMBOL
PARAMETER
WRITE CYCLE
3101A
3101
LIMITS (nsl
LIMITS (nsl
MIN. MAX.
MIN. MAX.
SYMBOL
TEST
3101A
3101
LIMITS (nsl
LIMITS (nsl
MIN. MAX.
MIN. MAX.
tS+·ts_
Chip Select to Output
Delay
5
17
5
42
tSR
Sense Amplifier
Recovery Time
tA_' t A +
Address to 0 utput
10
35
10
60
twp
Write Pulse Width
25
40
tow
Data-Write Overlap
Time
25
40
twR
Write Recovery Time
0
5
Delay
CAPACITANCE (21
TA =
25°C
INPUT CAPACITANCE
(All Plnsl
OUTPUT CAPACITANCE
50
35
10 PF
maximum
NOTE 2:
12 pF
maximum
3-147
This parameter is periodIcally sampled and Is not 100%
tested. Condition of measurement is f = 1 MHz, Vbias
= 2V, VCC = OV, and TA = 25°C.
3101, 3101A
Typical A.C. Characteristics
ADDRESS TO OUTPUT DELAY
VS.
AMBIENT TEMPERATURE
CHIP SELECT TO OUTPUT DELAY
VS.
AMBIENT TEMPERATURE
40
40r------------,------------,------------,
Vee"
l.ov ±5%
Vee .l.OV±5%
C L "'30pF
C L =30pF
30
c
c
>
~
--
"
f-
~
f-
"
""
I
i
I
l-
20
'A.
'A_
.-
~
"
f-
::1l"
20 1-----------+------------j-------------1
~
f-
~
~
a:
""
"
30r------------r------------t-----------~
>
I
10 I-
o
"'"
o
's-
~
50
25
101-----------+------------j-------------1
>------ - - - - f - - - - - 's.
°OL------------2~5------------M~----------~75
75
AMBIENT TEMPERATURE (OC)
AMBIENT TEMPERATURE (OC)
ADDRESS & CHIP SELECT TO OUTPUT DELAY
VS.
LOAD CAPACITANCE
WRITE PULSE WIDTH & SENSE
AMPLIFIER RECOVERY TIME
VS. AMBIENT TEMPERATURE
40
45,---------,--------,r--------,---------,
J
T."25"C
I ____"
35 r-----------t-
/
/
1////
Vee
J5.0V
CL=~OpF
.{.; ;A:.,,/+-______---4
30
'SR
/
20
'vip
15~------~-------
10
o
50L--------~50~-------,~0~0------r-,~5~0------~200
o
25
50
AMBIENT TEMPERATURE (OC)
LOAD CAPACITANCE (pF)
3-148
75
inter
3104
16 BIT CONTENT ADDRESSABLE MEMORY
• Organization - 4 Words x 4 Bits
• Max. Delay of 30 nsec Over 0° C
to 75° C Temperature
• Open Collector Outputs - OR Tie
Capability
• High Current Sinking Capability15 mA max.
• Low·lnput Load Current0.25mAmax.
• DTL & TTL Compatible
• Bit Enable Input - Bit Masking
• Standard 24 Pin Dual In-Line
The Intel 3104 is a high speed 16 bit Content Addressable Memory (CAM). It is a linear select 4 word
by 4 bit array which is designed to compare data on
its inputs with data already stored in its memory and
to indicate a match when these data are identical.
This equality search is performed on all bits in parallel. The 3104 can also be used as a read/write RAM
with linear selection addressing.
PIN CONFIGURATION
WRITE ENABLE
WE
"DATA INPUT
Ii,
E,
BIT ENABLE INPUT
DATA INPUT
Ii,
D,
E,
BIT ENABLE INPUT
E,
DATA INPUT
DATA INPUT
24
il"
LOGIC SYMBOL
5 4 3 2
Vee SUPP'LYVOLTAGE
BIT ENABLE INPUT
10
81T ENABLE INPUT
MATCH OUTPUT
ADDRESS INPUT
16
17
MATCH OUTPUT
M,
ADDRESS INPUT
MATCH OUTPUT
M,
ADDRESS INPUT
18
MATCH OUTPUT
ADDRESS INPUT
19
MATCH OUTPUT
DATA OUTPUT
"DATA OUTPUT
GROCJND GRD
2021 22 23
DATA OUTPUT
12
13
DATA OUTPUT
11
14
15
Vee'" PIN 24
GND = PIN 12
Eo
Do
°0
E,
0,
0,
E2
D2
°2
Ea
D3
WE
°3
3-149
3104
Absolute Maximum Ratings*
'COMMENT:
Temperature Under Bias
-65°C to +125° C
Storage Temperature
-65°C to +1600 C
All Output or Supply Voltages
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex·
tended periods may affect device reliability.
-0.5 to +7 Volts
All Input Voltages
-1.0 to +5.5 Volts
Output Currents
100mA
D. C. Characteristics
TA = aoe to +75°e, VCC = 5.av ±5%; unless otherwise specified.
LIMIT
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST
CONDITIONS
IFA
ADDRESS INPUT LOAD CURRENT
-0.25
mA
VCC = 5.25V V A = .45V
IFE
BIT ENABLE INPUT LOAD CURRENT
-0.25
mA
VCC = 5.25V V E = .45V
I FW
WRITE ENABLE INPUT LOAD CURRENT
-0.25
mA
VCC = 5.25V Vw = .45V
IFD
DATA INPUT LOAD CURRENT
-0.25
mA
VCC = 5.25V V D =.45V
IRA
ADDRESS INPUT LEAKAGE CURRENT
10
/1A
VCC = 5.25V V A - 5.25V
IRE
BIT ENABLE INPUT LEAKAGE CURRENT
10
/1A
VCC - 5.25V V E - 5.25V
I RW
WRITE ENABLE INPUT LEAKAGE CURRENT
10
/1A
VCC = 5.25V Vw = 5.25V
IRD
DATA INPUT LEAKAGE CURRENT
10
/1A
VCC = 5.25V V D = 5.25V
I CEX
OUTPUT LEAKAGE CURRENT
(ALL OUTPUTS)
50
/1A
VCC = 5.25V V CEX = 5.25V
VOL
OUTPUT "LOW" VOLTAGE
(ALL OUTPUTS)
0.45
V
0.85
V
VCC - 5V
V
VCC = 5V
V IL
INPUT "LOW" VOLTAGE (ALL INPUTS)
V IH
INPUT "HIGH" VOLTAGE (ALL INPUTS)
2.0
VCC = 4.75V 'OL = 15mA
ICC
POWEH SUPPLY CURRENT
mA
VCC - 5.25V OUTPUTS HIGH
CIN••
INPUT CAPACITANCE
5
pF
V ,N - +2.0V, VCC - O.OV
f = 1 MHz
COUT"
OUTPUT CAPACITANCE
8
pF
V OUT = +2.0V, VCC = O.OV
f = 1 MHz
125
**This parameter is periodically sampled and is not 100% tested.
Typical D.C. Characteristics
INPUT CURRENT VS.
INPUT VOLTAGE
~
-20
vqc
=
75°C
2.0
(f{
5.0V
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
INPUT THRESHOLD VOLTAGE
VS.TEMPERATURE
..... ~O'c
?
w
It: ~ "-25'C
'~"" 1.5
0
>
g
0
1.0
-- --
50.----r---,----,-~_.---,
Vee = 5.0V
I--
~a:
:J:
....
....
-80
.5
~
;::
-100
-1
1.0
2.0
INPUT VOLTAGE IV)
3.0
4.0
o
o
I
25
0 ' - _............_l........_....L.._ _'-_....J
50
AMBIENT TEMPERATURE (DC)
3·150
75
o
.4
.6
OUTPUT "LOW" VOLTAGE IV)
1.0
3104
Switching Characteristics
Conditions of Test:
15mA Test Load
Input Pulse amplitudes· . 2.5V
Input pulse rise and fa II ti mes of
5 nanoseconds between 1 volt
and 2 volts
Vce
300n
30pF
Speed measurements are made at 1.5 volt levels
600n
Output loading is 15 mA and 30 pF
BIT ENABLE
INPUT
MATCH
OUTPUT
MATCH
DATA
MODE
DATA
INPUT
MATCH
OUTPUT
}
ADDRESS
INPUT
DATA
OUTPUT
ADDRESS AND
BIT ENABLE
INPUT
WRITE
ENABLE
INPUT
DATA
INPUT
~It~ons
READ
DATA
MODE
t~onsr-~
-....,J- -~ -I" ......
-t-'WP-t
ts
WRITE
DATA
MODE
'R
...........'1 '----
DATA
OUTPUT
A.C. Characteristics
SYMBOL
TA = O°C to +75°C, Vee = 5.0V ±5%; unless otherwise specified.
PARAMETER
MIN.
LIMITS
TYP. (11
MAX.
UNIT
tEM
BIT ENABLE INPUT TO MATCH OUTPUT DELAY
15
30
ns
tDM
DATA INPUT TO MATCH OUTPUT DELAY
16
30
ns
tAO
ADDRESS INPUT TO OUTPUT DELAY
14
30
ns
twp
WRITE ENABLE PULSE WIDTH
two
WRITE ENABLE TO OUTPUT DELAY
-
40
ns
ts
SET·UP TIME ON DATA INPUT
-
40
ns
tR
RELEASE TIME ON DATA INPUT
Note 1.
40
0
Typical values are at nominal voltages and TA = 25°C.
3·151
25
-
ns
ns
3104
Typical A.C. Characteristics
DATA INPUT TO MATCH OUTPUT
DELAY VS. TEMPERATURE
BIT ENABLE INPUT TO MATCH OUTPUT
DELAY VS. TEMPERATURE
30
30r------------r----------~----------~
S.ov
Vee = 5.0V
C L =30pF
CL = 30 pF
Vee '"
!
!
~
>
~
Q
>-
i
!:;
o
Q
20~----------~----------_+----------~
>~
>:::>
:J:
t
~
:J:
U
~
":;
-
~
t.
0
:;
~~
20
>-
t ..
~
>~
10~----------~----------_+----------~
w
10
~
....
III
">"
"
~
>iii
Q
O~
__________
o
~
25
__________
~
________
~
0
75
50
0
25
wr-----------r----------,-----------,
CL
""
75
WRITE ENABLE PULSE WIDTH
VS. TEMPERATURE
ADDRESS INPUT TO DATA OUTPUT
DELAY VS. TEMPERATURE
Vee'"
50
AMBIENT TEMPERATURE tOC}
AMBIENT TEMPERATURE tOC}
wr-----------~----------~--------__,
Vee '" S.ov
S.ov
c L =30pF
30 pF
5
w
Q
~
~
~r_----------+-~--------~----------_4
w
~
>--
~
~
~~
20~----------~----------_+----------~
!il
§
~
w
....
~
z
w
~
10~----------+_----------~----------_4
10r-----------~----------_+----------~
ii:
~
~
a;
Q
~
oL-__________L-__________L-________
o
25
50
oL-__________
~
o
75
~
25
__________L-________
50
AMBIENT TEMPERATURE t"C}
AMBIENT TEMPERATURE t"C}
3-152
~
76
inter
x
256
PIN
5101 FAMILY
4 BIT STATIC CMOS RAM
Typ. Current @ 2V Typ. Current @ 5V
5101L
5101L-1
5101L-3
(IIA)
(IIA)
Max Access
(ns)
0.14
0.14
0.70
0.2
0.2
1.0
650
450
650
• Single +5V Power Supply
• Ideal for Battery
Operation (5101 L)
• Directly TTL Compatible:
All Inputs and Outputs
• Three-State Output
The Intel® 5101 is an ultra-low power 1024-bit (256 words X 4 bits) static RAM fabricated with an advanced ion-implanted
silicon gate CMOS technology_ The device has two chip enable inputs. Minimum standby current is drawn by this device when
CE2 is at a low level. When deselected the 5101 draws from the single 5-volt supply only 10 microamps. This device is ideally
suited for low power applications where battery operation or battery backup for non-volatility are required.
The 5101 uses fully DC stable (static) circuitry; it is not necessary to pulse chip select for each address transition_ The data is read
out non-destructively and has the same polarity as the input data. All inputs and outputs are directly TTL compatible. The 5101
has separate data input and data output terminals. An output disable function is provided so that the data inputs and outputs may
be wire OR-ed for use in common data I/O systems.
The 510 1L has the additional feature of guaranteed data retention at a power supply voltage as low as 2.0 volts_
A pin compatible N-channel static RAM, the Intel® 2101 A, is also available for low cost applications where a 256 X 4 organization is needed.
The Intel ion-implanted, silicon gate, Complementary MOS (CMOS) process allows the design and production of ultra-low power,
high performance memories.
PIN CONFIGURATION
LOGIC SYMBOL
A3
22
Vee
">
2'
A,
A,
20
R/W
As
As
As
'9
'8
CE'
A,
OD
As
11
CE2
A,
'6
DO,
DI,
DO
GND
'5
D',
D',
DO
D03
D',
D',
DO
BLOCK DIAGRAM
As
A,
A,
CELL ARRAY
32 ROWS
32 COLUMNS
A,
,.
D',
DO,
'0
D',
"
'3
0'3
'2
DO,
A,
A,
00
DO
r::~::::-':='""t-
__D~DO,
R/W
0,
'-HI >'"'<> DO,
0,
'---1i-C~<>D03
03
0,
TRUTH TABLE
CE1
CE, 00 R/W D.N
H
X
X
X
X
X
L
X
X
X
X
X
H
H
H
H
H
L
X
H
H
X
Output
Mode
HighZ Not Selected
High Z Not Selected
High Z Output Disabled
HighZ Write
X
D.N
Write
X
DOUT
Reed
o
3-153
= PIN NUMBERS
5101 FAMILY
Absolute Maximum Ratings *
*COMMENT:
Ambient Temperature Under Bias ..... _1O°C to BO°C
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage Temperature . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground .... -0.3V to Vcc +0.3V
Maximum Power Supply Voltage . . . . . . . . . +7.0V
Power Dissipation . . . . . . . . . . . . . . . . . .. 1 Watt
D. C. and Operating Characteristics
TA = o°c to 70°C, Vcc = 5V ±5% unless otherwise specified.
Symbol
Il 2 [2]
Parameter
5101L and 5101L-1
5101 L-3
Limits
Limits
Min. Typ.[l] Max. Min. Typ,ll] Max. Units
Input Current
5
IllOI[2] Output Leakage Current
1
nA
p.A
5
1
Test Conditions
CE1=2.2V, VOUT=
Oto VCC
ICCl
Operating Current
9
22
9
22
mA
VIN=VCC, Except
CEl .;;; 0.65V,
Outputs Open
ICC2
Operating Current
13
27
13
27
mA
VIN=2.2V, Except
CE1';;;0.65V,
Outputs Open
200
p.A
CE2';;;0.2V, TA=
70°C
ICCl[2] Standby Current
10
Vil
Input Low Voltage
-0.3
0.65 -0.3
0.65
V
VIH
Input High Voltage
2.2
VCC
2.2
VCC
V
VOL
Output Low Voltage
0.4
V
IOl=2.0 mA
VOH
Output High Voltage
V
IOH= -1.0 mA
0.4
2.4
2.4
Low Vcc Data Retention Characteristics (For 5101 L, 5101 L-1 and 5101 L-3) TA = COC to 70°C
Symbol
Parameter
Min.
Typ,ll]
Max.
Units
10
p.A
VOR
VCC for Data Retention
ICCORl
5101 L or 5101 L-1 Data Retention
Current
0.14
5101 L-3 Data Retention Current
0.70
ICCOR2
tCDR
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
V
2.0
CE2';;;0.2V
1.
200
p.A
0
ns
tRC[3]
ns
NOTES:
2.
3.
Test Conditions
Typical values are TA = 25°C and nominal supply voltage.
Current through all inputs and outputs included in ICCl measurement.
tRC = Read Cycle Time.
3-154
VOR=2.0V,
TA=7COC
VOR=2.0V,
TA=70°C
5101 FAMILY
Typical ICCDR Vs. Temperature
Low Vcc Data Retention Waveform
SUPPl Y
VOLTAGE (Vee)
CHIP ENABLE (CE21
@
OV- -
CD
4.75V
@
O.2V
o®
tR
VOR
V,H
-"""--------------------- - -
10
20
30
40
TEMPERATURE
A.C. Characteristics
50
60
70
ee)
TA = o°c to 70°C, Vee = 5V ±5%, unless otherwise specified.
READ CYCLE
Symbol
Parameter
5101 L·1
Limits (ns)
Min.
Max.
5101L and
5101 L·3
Limits (ns)
Min.
Max.
450
650
tRe
Read Cycle
tA
Access Time
450
650
teal
Chip Enable (CE 1) to Output
400
600
tC02
Chip Enable (CE 2) to Output
500
700
taD
Output Disable to Output
tDF
Data Output to High Z State
tOHl
Previous Read Data Valid with
Respect to Address Change
tOH2
Previous Read Data Valid with
Respect to Chip Enable
250
a
a
130
350
a
a
a
a
650
150
WRITE CYCLE
twe
Write Cycle
450
tAW
Write Delay
130
150
tewl
Chip Enable (CE 1) to Write
350
550
tew2
Chip Enable (CE 2) to Write
350
550
tDW
Data Setup
250
400
tDH
Data Hold
50
100
twp
Write Pulse
250
400
tWR
Write Recovery
50
50
tDS
Output Disable Setup
130
150
Capaci"ta nce[21T A
A. C. CONDITIONS OF TEST
Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Measurement Reference Level:
Output Load:
20nsec
1.5 Volt
Symbol
C'N
1 TTL Gate and CL ~ 100pF
GoUT
NOTES:
~
25°C, f ~ 1 MHz
+0.65 Volt to 2.2 Volt
1. Typical values are for T A = 25° C and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3·155
Limits (pF)
Test
I nput Capacitance
(All Input Pins) V,N
~
OV
Output Capacitance VOUT
~
OV
Typ.
Max.
4
8
8
12
5101 FAMILY
Waveforms
WRITE CYCLE
READ CYCLE
14-_______
ADDRESS
'wc------~
ADDRESS
m
EEl
CE2
CEZ
00
OD
tew2
(COMMON 1/0)[11
DATA
IN
DATA
OUT
DATA IN
STABLE
'w, - - - - - - 1 - t WR - RW
NOTES:
1. 00 may be tied low for separate 1/0 operation.
2. During the write cycle, 00 is "high" for common 1/0 and
"don't care" for separate 1/0 operation.
3·156
M5101-4, M5101L-4
256 x 4 BIT STATIC CMOS RAM
•
•
•
•
Military Temperature
Range:
-55°C to +125°C
•
Ultra Low Standby
Current: 200 nA/Bit
•
Fast Access Time-800ns
Single +5V Power Supply
CE2 Controls Unconditional
Standby Mode
Three-State Output
The Intel® M5101 is an ultra-low power 256 X 4 CMOS RAM specified over the -55°C to +125°C temperature range_ The RAM
uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate_ When deselected with CE2 low, the
M5101 draws from the single 5-volt supply only 200 microamps at 125°C_
The Intel® M5101 is fabricated with an ion-implanted, silicon gate, Complementary MOS (CMOS) process_ This technology allows
the design and production of ultra-low power, high performance memories_
PIN CONFIGURATION
LOGIC SYMBOL
5101
5101
A,
v"
A,
A.
Absolute Maximum Ratings
..
Ambient Temperature Under Bias ... _65°C to 13SoC
A,
.
A,
A,
A,
A,
Storage Temperature . . . . . . . . . . _65°C to +150°C
Voltage On Any Pin
With Respect to Ground .... -O.3V to Vee +O.3V
A,
A.
A.
A,
A,
DO.
A,
D<.
D<,
DO,
DO,
0',
0',
DO,
*
D<,
00,
m,
00,
0',
Maximum Power Supply Voltage
+7.0V
Power 0 issipation
1 Watt
'COMMENT:
00,
m.
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
DO,
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN NAMES
01, 01.
00,_00, DATA OUTPUT
-A,
.m
AEAOIWI'UTE INPUT
V
D. C. and Operating Characteristics for M5101-4, M5101L-4
TA = -55 D C to 125°C, VCC = 5V ±5% unless otherwise specified.
Symbol
Parameter
I U[2]
Input Current
IlOH[2]
Output High Leakage
IlO l [2]
Output Low Leakage
ICCl
Operating Current
ICC2
Operating Current
ICCl[2]
Standby Current
V il
Input "Low" Voltage
VIH
Input "High" Voltage
VOL
Output "Low" Voltage
VO H
Output "High" Voltage
NOTES:
1. Typical values are TA =
Typ.[ll
Min.
Max.
8
Unit
Test Conditions
nA
VIN = 0 to 5.25V
2
jJ.A
CEl =2.2V, VOUT=VCC
2
jJ.A
CE 1 =2.2V, VOUT=O.OV
11
25
mA
VIN =Vcc Except CEl ":O.OlV
Outputs Open
20
32
mA
VIN=2.2V Except CEl ":0.5V
Outputs Open
2
200
jJ.A
VIN =0 to Vcc, Except
CE2": 0.2V
-0.3
0.5
V
Vcc-2.0
Vcc
V
0.4
V
IOl = 2.0mA
V
IOH = 1.0mA
Vcc-2.0
2SoC and nominal supply voltage:
3-157
2. Current through all inputs and outputs included in
ICCl.
""'1/' ,
M5101-4, M5101L-4
Low VCC Data Retention Characteristics (For M5101L-4)
TA
'<"'I" ;,..,
= -55°C to 125°C
"
Symbol
Parameter
Typ.!l]
Min.
VOR
Vee for Data Retention
leeOR
Data Retention Current
teoR
Chip Deselect to Data Retention
Time
tR
Operation Recovery Time
Max.
Unit
",r:~:, "
Test Conditions
V
2.0
CE2 E;;0.2V
2
200
/lA
VOR=2.0V
ns
0
tRe!2]
ns
NOTES: 1. Typical values are TA = 25°C and nominal supply voltage.
2. tRe = Read Cycle Time.
A.C. Characteristics for M5101-4, M5101L-4
READ CYCLE
TA = -55°C to 125°C, Vee = 5V ±5%, unless otherwise specified.
Symbol
Parameter
Min.
Read Cycle
Typ.
Max.
Unit
Test Conditions
ns
tRe
tA
800
Access Time
800
ns
teal
Chip Enable (CE1) to Output
700
ns
te02
Chip Enable (CE2) to Output
850
ns
too
Output Disable To Output
Data Output to High Z State
0
350
150
ns
tOF
tOH1'
Previous Read Data Valid with
Respect to Address Change
0
ns
tOH2
Previous Read Data Valid with
Respect to Chip Enable
0
ns
(See below)
ns
WRITE CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Unit
twe
Write Cycle
tAW
Write Delay
150
ns
tewl
Chip Enable (CE1) To Write
550
ns
tcw2
Chip Enable (CE2) To Write
550
ns
tow
Data Setup
400
ns
tOH
Data Hold
100
ns
twp
Write Pulse
Write Recovery
400
50
ns
tWR
tos
Output Disable Setup
150
ns
800
ns
0.5 Volt to Vee-2.O Volt
Input Pulse Rise and Fall Times:
Timing Measurement Reference Level:
Output Load:
(See below)
Capaci°tanee[3jTA = 25°C, f = 1 MHz
A. C. CONDITIONS OF TEST
Input Pulse Levels:
Test Conditions
ns
20nsec
1.5 Volt
Symbol
Test
Limits (pF)
Typ.
Max.
CIN
Input Capacitance
(All Input Pins) VIN = OV
4
8
GoUT
Output Capacitance VOUT = OV
8
12
1 TTL Gate and CL = 100pF
NOTE: 3. This parameter is periodically sampled and is not 100% tested.
3-158
M5101-4, M5101L-4
Waveforms
WRITE CYCLE
1-------------
,wc------------~
ADDRESS
- tCW1 - - - - o j
eE2
j4--t------ tCW2 - - - - - - - - - o j
0 0 - - + - - -.....
00
(COMMON I/O) (1]
(COMMON I/O) (2]
'os
DATA
IN
DATA
OUT
DATA IN
STABLE
-
tAW
'twR-
--II-'\./-------'wp---..j,-;;;;..-+-R/W
NOTES: 1. 00 may be tied low for separate 110 operation.
2. During the write cycle, 00 is "high" for common 110 and
"don't care" for separate 110 operation.
Low Vcc Data Retention
SUPPLY VOLTAGE (Vee)
G)
.@
4.75V
@
O.2V
®
CHIP ENABLE (CE2)
w------------------
3-159
VOR
VIH
4 Read Only
Memory
MOS ROM AND PROMFA"MILY
No.
of
Bits
Type
(I)
0
Organization
of
Pins
Output[11
Maximum
Access
(ns)
Maximum
Power
Dissipation
(mW)
Operating
Temperature
Range
.(oC)
Power
Supply
5V ±5%
12V ± 5%
-5V ± 5%
4-18
5V±5%
4·22
8192
1024 x 8
24
T.S.
450
840
o to 70
2~16A
16384
2048 x 8
24
T.S.
.850
515
2316E
16384
2048 x 8
24
T.S.
450
630
o to 70
o to 70
2308
~a:
NO.
:::Ec(w:::E
i=a:iilo
w~c(a:
z°:::Ea.
Oa:
a.
16384
2048 x 8
24
T.S.
TBD
TBD
-55 to 125
5V ± 10% 4·28
2332
32768
4096 x 8
24
T.S.
TBD
TBD
5V ± 10% 4·29
2364
65536
8192 x 8
2,8
T.S.
T13,D
TBD
o to 70
oto 70
2608
8192
1024 x 8
24
T.S.
450
800
o to 70
2616
16384
2048 x 8
24
T.S.
450
525
1702A
2048
256 x 8
24
T.S.
lJ,1s
885
oto 70
o to 70
5V ± 10% 4·30
5V ±5%
12V ± 5%
-5V ± 5%'
5V ±5%
5V ±5%
-9V ± 5%
5V ±5%
-9V ± 5%
5V±5%
-9V± 5%
5V ±5%
-rOY ±5%
1702A·2
2048
256 x 8
24
T.S.
650
959
Oto 70
1702A·6
2048
256 x 8
24
T.S.
1.5#s
885
Oto 70
4702A
2048
256 x 8
24
T.S.
1.7J,1s
M1702A
2048
256x 8
24
T.S.
850
960
-55 to 100
1702AL
2048
256x 8
24
T.S.
1JlS
221
o to 70
5V±5%
-9V ± 5%
2048
256x 8
24
T.S.
650
221
o to 70
5V±5%
-9V ± 5%
2704
4096
512x 8
24
T.S.
450
800
Oto 70,
5V±5%
12V ± 5%
-5V,± 5%
2708
8192
1024 x 8
24
T.S.
450
800
Oto 70
5V ±5%
12V ± 5%
-5V ± 5%
2708L
8192
1024 x 8
24
T.S.
450
425
o to 70
5V ±5%
12V ± 5%
-5V ± 5%
2708-1
8192
1024 x 8
24
T.S.
350
800
o to 70
5V ±5%
12V ± 5%
-5V ± 5%
8192
1024 x 8
24
T.S.
450
750
-55 to 100
450
525/132[21
1702AL·2
o to 70
:E
M2708
Notes:
5V ± 10% 4-25
M2316E
w~
a.
w
~
Page
No.
;
:::E
~a:
(V)
2716
16384
2048 x 8
24
T.S.
M2716
16384
2048 x 8
24
T.S.
2732
32768
4096 x 8
24
T.S.
2758
8192
1024 x 8
24
T.S.
450
525/132[21
b to 70
4·31
4·34
4·5
4-14
!5V ±1b% 4·9
-9V ± 10%
4·11
4·38
4·38
5V ± 10%
12V ± 10% 4-41
-5V ± 10%
5V±5%
4-44
-55 to 125
5V ± 10% 4·49
o to 70
o to 70
5V ± 10% 4·50
5V ±5%
4·51
ROM and PROM Programming Instructions 14.69 1
1. TS is a three state output.
2. The 2716/2758 has a standby power down feature.
4·2
BIPOLAR PROM FAMILY
Type
Maximum
Power
Dissipation
(mW)
Operating
Temperature
Range
Output[11
Maximum
Access
(ns)
16
O.C.
70
735
16
O.C.
60
735
16
T.S.
70
735
512x4
16
T.S.
60
735
No.
of
Pins
512x4
512x4
2048
512x4
2048
No.
of
Bits
Organization
2048
2048
Power
Supply
(oe)
4096
512x8
24
O.C.
70
895
3604A-2
4096
512x8
24
O.C.
60
895
3604AL
4096
512x8
24
O.C.
90
685/135[21
4096
512x8
24
T.S.
70
895
4096
512x8
24
T.S.
60
895
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
4096
512x8
24
O.C.
90
1045
-55 to 125
5V ± 10%
-55 to 125
5V ± 10%
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
3602A
3602A-2
3622A
3622A-2
3604A
3624A
3624A-2
M3604A
M3624A
3605
3605-2
3625
3625-2
3608
3608-4
3628
3628-4
Notes:
4096
512x8
24
T.S.
90
1045
4096
1024x4
18
O.C.
70
735
4096
1024x4
18
O.C.
60
735
4096
1024x4
18
T.S.
70
735
4096
1024x4
18
T.S.
60
735
8192
1024x8
24
O.C.
80
998
8192
1024x8
24
O.C.
100
998
8192
1024x8
24
O.C.
80
998
8192
1024x8
24
O.C.
100
998
1. O.C. and T.S. are open collector and three-state
output respectively.
2. The 3604Al has a low power dissipation feature.
5V± 5%
5V± 5%
5V ± 5%
4·55
5V ± 5%
5V ±5%
5V± 5%
5V ± 5%
4-58
5V ± 5%
5V ± 5%
4-61
5V ± 5%
5V ± 5%
5V ± 5%
4-63
5V± 5%
5V± 5%
5V± 5%
5V± 5%
5V± 5%
ROM and PROM Programming Instructions
4-3
Page
No.
4-66
BIPOLAR PROM CROSS REFERENCE
I ntel Part Number
Part
Prefix and
Direct
Organization
Number Manufacturer
Replacement
5340-1
5341-1
MMI
MMI
512 x 8
512 x 8
M3624A
M3624A
5604C
5605C
5624C
5625C
IM-Intersil
1M-I ntersil
IM-Intersil
512
512
512
512
x
x
x
x
4
8
4
8
3602A
3604A
3622A
3624A
6305-1
6306-1
6340-1
6341-1
6352-1
6353-1
6380-1
6381-1
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
512
512
512
512
1024
1024
1024
1024
x
x
x
x
x
x
x
x
4
4
8
8
4
4
8
8
3602A-2
3622A-2
3604A
3624A
3605-2
3625-2
3608
3628
74S472
74S473
74S474
74S475
74S570
74S571
TI
TI
TI
TI
512
512
512
512
512
512
x
x
x
x
x
x
8
8
8
8
4
4
x
x
x
x
x
x
x
x
x
x
x
4
4
8
8
8
8
4
4
4
8
8
x
x
x
x
x
x
x
x
x
x
x
x
8
8
4
4
8
8
4
4
8
8
4
4
7620-5
7621-5
7640-2
7640-5
7641-2
7641-5
7642-5
7643-5
7644-5
7680-5
7681-5
IM-Intersil
National
National
HM-Harris
512
512
512
512
512
512
1024
1024
1024
1024
1024
82S115
82S115
82S130
82S131
82S140
82S141
82S136
82S137
82S180
82S181
82S184
82S185
N-Signetics
S-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
512
512
512
512
512
512
1024
1024
1024
1024
2048
2048
87S295
87S296
National
National
93436C
93438C
93438M
93446C
93448C
93448M
93452C
93453C
Fairchild
Fairchild
Fairchild
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
Fairchild
Fairchild
Fairchild
Fairchild
Fairchild
512 x 8
512 x 8
512
512
512
512
512
512
1024
1024
x
x
x
x
x
x
x
x
4
8
8
4
8
8
4
4
For New
Designsll )
3624A
3604A
3624A
3604A
3602A
3622A
3602A
3622A
M3604A
3604A
M3624A
3624A
3605
3625
3625
3608
3628
3624A
M3624A
3602A
3622A
3604A-2
3624A-2
3605-2
3625-2
3608
3628
3608
3628
3604A
3624A
3602A-2
3604A-2
M3604A
3622A-2
3624A-2
M3624A
3605-2
3625-2
NOTE: 1. The Intel® PROMs have the same pin configuration and differ
only in access time from the PROMs in the first column. The
exceptions are the 6350, 6351, 82S115, and 82S184/85 which
have different pin configurations.
4-4
inter
1702A
2K (256
x 8) UV ERASABLE PROM
1702A-2
1702A
1702A-6
0.65 us Max.
1.0 us Max.
1.5 us Max.
• Fast Access Time: Max. 650 ns
(1702A-2)
• Fast Programming: 2 Minutes
for all 2048 Bits
• All 2048 Bits Guaranteed*
Programmable: 100% Factory
Tested
• Static MOS: No Clocks Required
• Inputs and Outputs DTL and
TTL Compatible
• Three-State Output: OR-tie
Capability
The 1702A is a 256 word by 8-bit electrically programmable ROM ideally suited for uses where fast turnaround and pattern experimentation are important. The 1702A undergoes complete programming and functional testing prior to shipment, thus insuring 100% programmability.
Initially all 2048 bits of the 1702A are in the "0" state (output low). Information is introduced by selectively
programming "l"s (output high) in the proper bit location. The 1702A is packaged in a 24 pin dual in-line
package with a transparent lid. The transparent lid allows the user to expose the 1702A to ultraviolet light to
erase the bit pattern. A new pattern can then be written into the device.
The circuitry of the 1702A is completely static. No clocks are required. Access times from 650ns to 1.5~s are
available. A 1702AL family is available (see 1702AL data sheets for specifications) for those systems requiring
lower power dissipation than the 1702A.
The 1702A is fabricated with silicon gate technology. This low threshold technology allows the design and production of higher performance MaS circuits and provides a higher functional density on a monolithic chip than
conventional MaS technologies.
'Inte!"s liability shall be limited to replacing any unit which fails to program as desired.
PIN CONFIGURATION
A,
2
23
Vee
- Vee
3
22
"DATA OUT 1
4 (lSB)
21
A3
-DATA OUT 2
5
20
A4
'DATA OUT 3
6
AO
"DATADUT 4
7
18
Aij
'DATA Dur 5
8
17
A7
*DATA OUT 6
9
16
VGG
·OATA OUT 7
10
15
VBS
·DATA OUT 8
11 (MSB)
14
cs
12
13
PROGRAM
Vee
PIN NAMES
~~__l~dd~~~J)U~____
CS
Chip Select Input
BLOCK DIAGRAM
J
DATA OUT 1
DATA OUT 8
---~---
"THIS PIN IS THE DATA INPUT LEAD DURING PROGRAMMING
NOTE: In the read mode a logic 1 at the address inputs
and data outputs is a high and logic 0 is a low.
U.S. Patent No. 3660819
4·5
1.1
1702A
PIN CONNECTIONS
The external lead connections t6 the 1702A differ, depending on whether the device is being programmed or used in read mode
(see following table). In the programming mode, the data inputs 1·8 are pins 4-11 respectively. The programming voltages and timing are shown in the ROM and PROM Programming instructions section, page 4-84.
~
MODE
12
(Vee!
13
(Program)
14
(CS)
15
(VBB)
22
(Vee)
16
(VGG)
23
(Vee)
24
(Voo)
Read
Vee
Vee
GND
Vee
VGG
Vee
Vee
Voo
Programming
GND
Program Pulse
GND
VBB
Pulsed VGG
GND
GND
Pulsed Voo
Absolute Maximum Ratings*
Ambient Temperature Under Bias ....... -10 o e to +80 o e
Storage Temperature . . . . . . . . . _ ... -65°C to +125°C
Soldering Temperature of Leads (10 sec) . . . . . . . . +300 0 e
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 2 Watts
Read Operation: Input Voltages and Supply
Voltages with respect to Vee . . . . . . . . . . +0.5V to -20V
Program Operation: Input Voltages and Supply
Voltages with respect to Vee . . . . . . . . . . . . . . . . -48V
D.C. and Operating Characteristics
Test
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
TA = oOe to 70°C, Vee = +5V ±5%, Voo = -9V ±5%, VGG = -9V ±5%,
unless otherwise noted.
READ OPERATION
Symbol
'COMMENT
1702A, 1702A-6 Limits
Typ,[1]
Max.
Min.
Min.
1702A-2 Limits
Typ.[1]
Max.
Unit
Conditions
III
Address and Chip Select
Input Load Current
1
1
ILO
Output Leakage Current
1
1
/lA
VOUT = O.OV, CS = VIH2
1001 [1]
Power Supply Current
35
50
40
60
mA
CS = VIH2, 10 L = O.OmA,
TA = 25°C, Continuous
1002
Power Supply Current
32
46
37
55
mA
CS = O.OV, 10L = O.OmA,
TA = 25°C, Continuous
1003
Power Supply Current
38
60
43
65
mA
CS =VIH2, 10L = O.OmA,
TA = O°C, Continuous
leFl
Output Clamp Current
8
14
7
13
mA
VOUT = -1.0V,
TA = O°C, Continuous
leF2
Output Clamp Current
7
13
6
12
mA
VOUT=-1.0V,
TA = 25°C, Continuous
IGG
Gate Supply Current
1
/lA
VIL1
Input Low Voltage
for TT L Interface
-1
0.65
-1
0.65
V
VIL2
Input Low Voltage
for MOS Interface
Voo
Vee-6
Voo
Vee-6
V
VIHI
VIH2
Addr.lnput High Voltage
Chip SeLl nput High Volt.
Vee-2
Vee-2
Vee+0.3
Vee+0.3
V
10L
Output Sink Current
1.6
-2.0
10H
Output Source Current
VOL
Output Low Voltage
VOH
Output High Voltage
1
Vee+0.3
Vee+0.3
4
1.6
4
-2.0
-3
3.5
Vee-2
Vee-1.5
-3
0.45
4.5
3.5
Note 1: Typical values are at nominal voltages and TA = 25°C.
4-6
4.5
0.45
/lA
VIN = O.OV
V
mA
VOUT = 0.45V
mA
VOUT= O.OV
V
10L = 1.6mA
V
10H = -200/lA
1702A
A.C. Characteristics
TA = rJ' C to + 70°C, Vee = +5V ±5%, VDD = -9V ±5%, VGG = -9V ±5% unless otherwise noted
Symbol
1702A-2
Limits
Min.
Max.
1702A
Limits
Max.
Min.
Test
1702A-6
Limits
Min.
Max.
Unit
MHZ
Freq.
Repetition Rate
1
1.6
0.66
tOH
Previous Read Data Valid
0.1
0.1
0.1
J..I.s
tAee
Address to Output Delay
1
0.65
1.5
J..I.s
tes
Chip Select Delay
0.1
0.3
0.6
J..I.s
teo
Output Delay From CS
0.9
0.35
0.9
J..I.s
too
Output Deselect
0.3
0.3
0.3
J..I.s
Capacitance"
SYMBOL
TA = 25°C
TEST
TYPICAL
MAXIMUM
UNIT
C IN
Input Capacitance
8
15
pF
COUT
Output Capacitance
10
15
CONDITIONS
VON' V"
A"
}
r.S = Vee
pF
unused pins
VOUT = Vee
are at A.C.
VGG = Vee
ground
'This parameter is periodically sampled and is not 100% tested.
Switching Characteristics
Conditions of Test:
Input pulse amplitudes: a to 4V; t R • tF ::s 50 ns
Output load is 1 TTL gate; measurements made
at output of TTL gate (tpo~15 ns), CL = 15pF
A) READ OPERATION
_
- - CYCLE TIME'
B) DESELECTION OF DATA OUTPUT IN OR·TIE
OPERATION
l/FREO _
VIH
----i
'0%
I
I
90%
I
---i} ;'
~tco~!
V OH
~~~A
VOL
4-7
DATA OUT
INVA:-ID
:
I
~I ~ tooy~.
I
~
:
~~-~~~--4---------
1702A
Typical Characteristics
OUTPUT CURRENT VS.
Vee SUPPLY VOLTAGE
"
.E
OUTPUT CURRENT VS.
TEMPERATURE
i
vee = +5V
vGG = -9V
VOL =+.45~/
TA ·2S0C
~
ia
~
u;
2f--
~
.a
Z
u;
Operatmg RII~ge_
0
~
"
-I-
.9
-.
o .J.'
-7
-lI
-6
Vco SUPPl.Y VOLTAGE (V)
.E
I
--3-
Vee
VGG
VOH
TA
"w
Ii!
~ -3.'
~
"
...
"ili
.
a
.g -. r-
-'0
~
.. +5\1
a:
= -9\1
=
oov
= 2SOC
"
.........
.9
~
0
....
J
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
-4
20
'0
30
38
"ffi
!
-
-
-~
•.0
~
•. 0
36
f-- V DD
1
VGG = -9V
T
= 250C~
+/
o.ov/
~ 10.0
..,"
37
Vee = +5V
• -9V-
12.0
f--
u;
~
..
..,
ffi
"
CS"
0
/'
4.0
Q
Q
V
V
-4
-3
-2
~T
~
60
.0
f-- f--f.':oov
1
I
3'
1
1
\
I
Vee'" +5V
-
Voo= -9V
\
'\
33
,'\
32
-
VGG=-9V
34
INPUTS = Vee
OUTPUTS ARE OPEN
1"-
"- ~S=Vcc
1 1
1'\
31
"-
30
I"
"l
-
CS=O.OV
29
1
27
20
I
1
-1
+1
"'2
+3
+4
40
20
60
80
100
120
AMBIENT TEMPERATURE (oC)
ACCESS TIME VS.
LOAD CAPACITANCE
ACCESS TIME VS.
TEMPERATURE
900
900
800
800
1702A
700
~
Vee =+5V Voo =-9V
VGG =-9V TA = 25"C -
w
~ 500
...
~ 400
:;;
~
~
1702A·2
100
100
30 40
50
60 70
80
90 100
-
400
1702A·2
300
200
10 20
Vee =+5VVDD =-9V _
VGG = -9V
200
o
1 TTL LOAD - 20 pF
600
i= 500
300
~
1762A
700
1 TTL LOAD-
]600
o
70
VGG= -9V
OUTPUT VOLTAGE (VOL lSI
~
60
Voo= -9V
29
-~/
/
50
I
lee CURRENT VS. TEMPERATURE
I
I
40
r-
VOL" +.45V
I AMIBIENT TEMPERATURE (oC)
3.
1'40
voo= -9V
vGG= -9V
Vee'" +5V
!l
0
%
0
.E
I
Iv)..1
TT r---.r-
0
j,
"ffi
...,
'" '" !'t>
a:
. .Id
2
~
~
ilia:
o
10
20
30 40
50
60
-
70
AMBIENT TEMPERATURE I"CI
LOAD CAPACITANCE IpFI
4·8
i-
- i-
80
90
M1702A
2K (256 x 8) UV ERASABLE PROM
-55°C to +100°C OPERATION
• Fast Access Time: Max. 850 ns
• All 2048 Bits Factory Tested
Prior to Shipment
• Completely Static
• Three-State Output
• Inputs and Outputs DTL
and TTL Compatible
• 24 Pin Dip
The Intel® M1702A is a 256-word by 8-bit ultraviolet light erasable and electrically reprogrammable EPROM which is specified over the _55°C to +100°C temperature range_ The M1702A has a transparent lid which allows the user to expose the
M1702A to UV light to erase the bit pattern_ A new pattern can then be written into the device_
Absolute Maximum Ratings*
PIN CONFIGURATION
. -65°C to 11 aOc
Ambient Temperature Under Bias
Storage Temperature
~65°C to +125°C
Soldering Temperature of Leads (10 sec)
+300 oC
Power Dissipation
. . . . . . 2 Watts
Read Operation: Input Voltages and Supply
Voltages with respect to Vee
. +O.5V to -20\/
19
Program Operation:
A~
Input Voltages and Supply
. -48V
Voltages With respect to Vee
'COMMENT
'DATA OUT 7
'co
10
15
VB~
14
CS
Stresses above those listed under "Absolute Maximum RatIngs" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to Absolute Maxirnum Rating conditions for extended periods may affect deVice reliability.
c.:':..'_ _,,-,
D.C. and Operating Characteristics
TA = -55°C to 100°C, Vee = +5V ±10%, Voo = -9V ±10%,
READ OPERATION
vGG = -9V ±10%
Symbol
Test
Min.
Typ.llJ
unless otherwise noted.
Max.
Unit
Conditions
III
Address and Chip Select Input Load Current
10
/lA
ILO
Output Leakage Current
10
/lA
VOUT = O.OV, CS~ VIH2
1001 [1]
Power Supply Current
35
50
mA
CS=V IH2, IOL =O.OmA,
TA = 25°C, Continuous
1002
Power Supply Current
32
46
mA
CS=O.OV, IOL =O.OmA,
TA = 25°C, Continuous
1003
Power Supply Current
38
65
mA
CS=VIH2,loL = O.OmA,
TA = -55°C, Continuous
ICF
Output Clamp Current
8
11
mA
VOUT = -1.0V,
T A = -55°C, Continuous
I
IGG
Gate Supply Current
10
/lA
V IL1
Input Low Voltage for TTL Interface
-1
0.65
V
VIL2
I nput Low Voltage for MOS Interface
Voo
Vcc-6
V
VIHl
Address Input High Voltage
Vcc-2
Vcc+0.3
V
VIH2
Chip Select Input High Voltage
IOL
Output Sink Current
IOH
Output Source Current
VOL
VOH
Note 1.
I
Vcc- 1.5
1.6
-2.0
Output Low Voltage
-3
Output High Voltage
Typical values are at nominal voltages and TA
Vcc+0.3
4
3.5
=
25°C.
4-9
4.5
0.45
VIN = O.OV
V
mA
VOUT = 0.45V
mA
VOUT = O.OV
V
IOL = 1.6mA
V
IOH = -200}JA
M1702A
A.C. Characteristics
TA = -55°C to 100°C, Vee = +5V ±10%, Voo = -9V ±10%, VGG = -9V ±10% unless otherwise noted.
Limits
Symbol
CIN
Min.
Unit
Freq.
Repetition Rate
1.2
MHz
f>revious Read Data Valid
0.1
!.Is
tAee
Address to Output Delay
0.85
!.Is
tes
Chip Select Delay
0.5
!.Is
teo
Output Delay From CS
0.35
too
Output Deselect
0.3
!.IS
I
!.IS
. TA = 25°C
TEST
TYPICAL
MAXIMUM
UNIT
Input Capacitance
8
15
pF
CONDITIONS
V IN = Vee }AII
CS = Vee
unused pins
--------~--------------~--------+_--------_4---------
C OUT
Max.
toH
Capacitance
SYMBOL
Test
Output Capacitance
10
pF
15
V OUT =
Vee
are at A.C.
VGG = Vee
ground
'This parameter is sampled and is not 100% tested.
Switching Characteristics
Conditions of Test:
Input pulse amplitudes: 0 to 4V; t R , tF S50 ns
Output load is 1 TTL gate; measurements made
at output of TTL gate (tpoo(15 ns), CL = 15pF
A) READ OPERATION
B) DESELECTION OF DATA OUTPUT IN OR·TIE
OPERATION
VOH ---i!~'
DATA OUT
~~~A ~ALlD
VOL
ERASING AND PROGRAMMING PROCEDURE
The erasing and programming procedure of the M1702A is
the same as the O°C to 70°C 1702A. The procedure is
discussed in Section IV, page 4·83, of the data catalog.
4-10
~lCO""
I
~I ~ IOO/~
:1
--+_--'_L ---------:
I
~C-.- - + - 1_ _
I
inter
1702AL, 1702AL2
2K (256 x 8) UV ERASABLE LOW POWER PROM
MAXIMUM
Part No. ACCESS (1J5)
17.o2AL
1..0
17.o2AL-2
.0.65
•
• Clocked VGG Mode for Low
Power Dissipation
• Fast Programming: 2 Minutes
for all 2048 Bits
• All 2048 Bits Guaranteed*
Programmable: 100% Factory
Tested
•
tOVGG (1J5)
.0.4
.0.3
Inputs and Outputs DTL and TILl
Compatible
Three-State Output: OR-tie
Capability
The 1702AL is a 256 word by 8 bit electrically programmable ROM and is the same chip as the industry standard 1702A. The
programming and erasing specifications are identical to the 1702A. The 1702AL operates with the VGG clocked to reduce the
power dissipation.
Initially all 2048 bits of the 1702AL are in the "0" state (output low). Information is introduced by selectively programming
"1 "s (output high) in the proper bit location. The 1702AL is packaged in a 24 pin dual in-line package with a transparent lid. The
transparent lid allows the user to expose the 1702AL to ultraviolet light to erase the bit pattern. A new pattern can then be
written into the device.
The 1702AL is fabricated with silicon gate technology. This low threshold technology allows the design and production of high
performance MOS circuits and provides a higher functional density on a monolithic chip than conventional MOS technologies.
*Intel's liability shall be limited to replacing any unit which fails to program as desired.
PIN CONFIGURATION
PIN NAMES
BLOCK DIAGRAM
DATA OUT 1
AO
"DATA OUT 1
-DATA
our
3
22
Vcr
4 ILSB)
21
A3
2
5
'DATA OUT 3
6
DATA OUT 8
°DATA OUT 4
'DATAOUT 5
8
-DATA OUT 6
9
·OATA OUT 7
10
-DATA
our
8
v"
11 lMSB)
14
L'.::..'_ _ _
13.J
CS
AO A,
PROGRAM
A7
NOTE: In the read mode a logic 1 at the address inputs
"THIS PIN IS THE DATA INPUT LEAD DURING PROGRAMMING
and data outputs is a high and logic 0 is a low.
U.S. Patent No. 3660819
4-11
1702AL, 1702AL2
PIN CONNECTIONS
The external lead connections to the 1702AL differ, depending on whether the device is being programmed or used in read mode
(see following table). In the programming mode, the data inputs I·B are pins 4·11 respectively. The programming voltages and tim·
ing are shown in the Data Catalog ROM and PROM Programming Instructions section page 4-83
~
MODE
12
(Vee)
16
(VGG)
13
(Program)
14
(CS)
15
(Vgg)
Vee
Clocked VGG
VBB
Pulsed VGG
Read
Vee
Vee
GND
Programming
GND
Program Pulse
GND
22
(Vee)
23
(Vee)
24
(Voo)
Vee
Vee
Voo
GND
GND
Pulsed Voo
Absolute Maximum Ratings*
Ambient Temperature Under Bias ....... -10°Cto +BO°C
Storage Temperature . . . . . . . . . . . . . -65°C to +125 0 C
Soldering Temperature of Leads (10 sec) . . . . . . .. +300 0C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 2 Watts
Read Operation: Input Voltages and Supply
Voltages with respect to Vee .......... +0.5V to -20V
Program Operation: Input Voltages and Supply
Voltages with respect to Vee . . . . . . . . . . . . . . . . -4BV
D.C. and Operating Characteristics
READ OPERATION
Symbol
Test
III
Address and Chip Select
Input Load Current
ILO
Output leakage Current
Min.
'COMMENT
Stresses above those listed under "Absolute Maximum Rat·
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to Absolute Maximum Rating c·onditions for extended periods may affect device reliability.
TA=oOet0700e,Vee=+5V±5%,Voo=-9V±5%, VGG[I] =-9V±5%,
unless otherwise noted.
1702AL Limits
Typ.l2]
Max.
Min.
1702AL-2 Limits
Typ.l2]
Max.
1
1
Unit
pA
Conditions
VIN = O.OV
1
pA
VOUT = O.OV, CS = Vee-2
7
10
rnA
15
mA
TA=25°C CS=VIH, VGG=Vcc,
TA=O°C IOL=O.OmA
50
35
50
rnA
CS =Vee -2,IOL = O.OmA,
TA =25°C, Continuous
32
4S
32
4S
rnA
CS =O.OV,IOL = O.OmA,
TA = 25°C, Continuous
Power Supply Current
38
SO
38
SO
rnA
CS = Vee -2,IOL = O.OmA,
TA = O°C, Continuous
leFt
Output Clamp Current
8
14
5.5
8
rnA
VOUT = -1.0V,
TA = O°C, Continuous
leF2
Output Clamp Current
7
13
5
7
rnA
VOUT = -1.0V,
TA =25°C, Continuous
IGG
Gate Supply Current
1
10001[1] Power Supply Current
Power Supply Current
10002
7
10
1001[1]
Power Supply Current
35
1002
Power Supply Current
1003
15
1
pA
VILI
Input low Voltage
. for TT L Interface
-1
0.S5
-1
0.S5
V
VIL2
Input low Voltage
for MOS Interface
VOO
Vee-S
VOO
Vee-S
V
VIH
Address and Chip Select
Input High Voltage
Vee-2
Vee+0.3
Vee-2
Vee+0.3
V.
IOL
Output Sink Current
loS
-2.0
IOH
Output Source Current
VOL
Output Low Voltage
VOH
Output High Voltage
1
4
-2.0
-3
3.5
I.S
4
4.5
-3
0.45
3.5
4.5
0.45
rnA
VOUT= 0.45V
rnA
VOUT= O.OV
V
IOL = I.SmA
V
IOH = -200pA
NOTES: 1. The 1702AL is operated with the VGG clocked to obtain low power dissipation. The average 100 will vary between 1000 and 1001 (at
25°e) depending on the VGG duty cycle (see curve opposite). 2. Typical values are at nominal voltage and TA = 25°e.
4-12
1702AL, 1702AL2
TYPICAL CHARACTERISTICS
AVERAGE CURRENT VS. OUTY
CYCLE FOR CLOCKEO VGG
45
CIJJEJ JGJ JL
40
I
1
Voo = -9V
35
'001
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
ACCESS TIME VS.
TEMPERATURE
os
=V 1H
TA
=25°C
800
1--+-+-+-j-+-+-+-+--+-1
"
f."
15
1--- .
a
.-~
z
~
~
0
=
f."
'000
10
20
30
40
50
60
70
80
90
o
100
DUTY CYCLE (%)
A.C. CHARACTERISTICS
Symbol
10
20 ~ 40 ~ ~ ro
AMBIENT TEMPERATURE lOCI
~
j
V
00
-4
-3
-2
1702AL
Limits
Min.
Max.
1702AL-2
Limits
Min.
Max.
Repetition Rate
1
1.6
MHz
Address to output delay
1
0.65
fJ.s
tOVGG
Clocked VGG set up
tcs
Chip select delay
0.1
0.3
fJ.s
teo
Output delay from CS
0.9
0.35
fJ.s
tOD
Output deselect
0.3
0.3
fJ.s
tOHe
Data out hold in clocked VGG mode
5
5
fJ.s
CS
=
6.0
4.0
lL
./
o.ov
/'
V
20
.
-1
-1-1
-t2
-t3
+4
0.4
0.3
fJ.s
TA = 25°C
TEST
CIN
I nput Capacitance
COUT
Output Capacitance
C VGG
VGG Capacitance
(Note 1)
IS
80
Unit
Freq.
*This parameter
VGG = -9V
T
=2SoC-
~A
OUTPUT VOL TAGE (VOL lS)
tACC
SYMBOL
-
TA = o°c to +70o C, vcc = +5V ±5%, VOO = -9V ±5% unless otherwise noted
Test
CAPACITANCE
10.0
-y
/1
I
Vee = +5V
- V OD "' - 9 V -
;;;
LOAD~
10
°0
I
12.0
~
30
12
60~--~---4---+----i
Vee = 525V
ALL ADDRESSES TIED
TOVCC
v)cc=sy
10
o
10
20
50
60
60
40
20
70
TA (OC)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
-30
30
-25
25
20
1
15
~
:2
J
10
j
V
V
/
V
. . .v
I-- I-20
TYPICAL
"
..§ -15
:r
:2
-10
TA
=
25°C
f\
\
\
TYPICAL
1\\
I\.
TA = 25"C
VC
Vee MIN
-5
/
TMIN
~
VOH (VOLTS)
VOL (VOLTS)
4·23
80
2316A
A.C. Characteristics
T A = o°c to + 70°C, Vee = +5V ±5% unless otherwise specified
PARAMETER
SYMBOL
LIMITS
Typ.(1)
MIN.
UNIT
MAX.
400
nS
850
tA
Address to Output Delay Time
teo
Chip Select to Output Enable Delay Time
300
nS
Chip Deselect to Output Data Float Delay Time
300
nS
tDF
0
CAPACITANCE(2) TA
CONDITIONS OF TEST FOR
A.C. CHARACTERISTICS
= 25°C, f = 1 MHz
LIMITS
Output Load ... 1 TTL Gate, and CLOAD = 100 pF
Input Pulse Levels . . . . . . . . . . . . . . . 0.8 to 2.0V
Input Pulse Rise and Fall Times. (10% to 90%) 20 nS
Timing Measurement Reference Level
Input . . . . . . . . . . . . . . . . . . . . . . . . 1.5V
Output ... . . . . . . . . . . . . . 0.45V to 2.2V
SYMBOL
TEST
TYP.
MAX.
CIN
All Pins Except Pin Under
Test Tied to AC Ground
4 pF
10 pF
COUT
All Pins Except Pin Under
Test Tied to AC Ground
8 pF
15 pF
(2) This parameter is periodically sampled and is not 100% tested.
A.C. Waveforms
ADDRESS
1-----'<:0----1
PROGRAMMABLE
CHIP SELECTS
1-------tA-------1
---"lfrl.
I'---0UTP_UTVAL_ID
Typical A.C. Characteristics
ACCESS TIME VS. LOAD
CAPACITANCE
ACCESS TIME VS. AMBIENT
TEMPERATURE
900
BOO
600
~
:;<
400
200
-
~
V
y
1000
BOO
WORST CASE
--
40
kt:
600
~
~ ~ICAL
20
--
:!400
~ ~PICAL
200
60
80
100
TA (-C)
200
JOO
CLOAO (pfd)
4·24
400
500
inter
2316E
16K (2K x 8) ROM
• EPROM/ROM Pin Compatible for
Cost-Effective System
Development
• Fast Access Time- 450 ns Max.
• Single +5V.:!:. 10% Power Supply
• Completly Static Operation
• Intel MCS 80 and 85 Compatible
• Three Programmable Chip
Selects for Simple Memory
Expansion and System Interface
• Inputs and Outputs TTL
Compatible
• Three-State Output for Direct
Bus Interface
The Intel® 2316E is a 16,384-bit static, N-channel MaS read only memory (ROM) organized as 2048 words by 8 bits. Its
high bit density is ideal for large, non-volatile data storage applications such as program storage. The three-state outputs and
TTL input/output levels allow for direct interface with common system bus structures. The 2316E single +5V power supply
and 450 ns access time are both ideal for usage with high performance microcomputers such as the Intel MCSTM-80 and
MCSTM-85 devices.
A cost-effective system development program may be implemented by using the pin compatible Intel 2716 16K UV EPROM
for prototyping and the lower cost 2616 PROM and 2316E ROM for production. The 2716 is fully compatible to the 2316E
in all respects. The three 2316E programmable chip selects may be defined by the user and are fixed during the masking process. To simplify the conversion from 2716 prototyping to 2316E production, it is recommended that the 2316E programmable chip select logic levels be defined the same as that shown in the below data sheet pin configuration. This pin configuration and these chip select logic levels are the same as the 2716.
PIN CONFIGURATION
A,
Vee
A6
AS
AS
A9
BLOCK DIAGRAM
...---0 Vee
--<-----------------'lX'---------toH~1
CSIWE
\<--___-----J;t
- .-tco- --___
I
l.-tOF---'"
!
4·33
2616*
16K (2K x 8) FACTORY PROGRAMMABLE PROM
•
•
Single
+ 5V Power Supply
Low Power Dissipation
525 mW Max. Active Power
132 mW Max. Standby Power
•
Pin Compatible to Intel® 2716 EPROM
and 2316E ROM
•
•
•
Fast Access Time -
450 ns Max.
Inputs and Outputs TTL Compatible
Completely Static
The Intel'" 2616 is a 16,384-bit, one-time factory-programmable MOS PROM organized as 2048 words by 8 bits. The
2616 operates from a single + 5V power supply, has a static standby mode, and is TTL inputloutput compatible. It is
specified over the D·G to 70·G operating temperature with 5% power supply variation.
A cost-effective system development program may be implemented quickly into production by using the Intel'" 2716
EPROM for pattern experimentation, the 2616 for fast first incremental 2316E ROM delivery, and the 2316E for volume
production. The 2616 is fully compatible to the 2716 in all respects. The fast factory 2616 code pattern turnaround time
gives rapid transition from EPROM to ROM for production.
The 2616 has a static standby mode which reduces the power dissipation without increasing access time. The maximum active power dissipation is 525 mW, while the maximum standby power dissipation is only 132 mW - a 75%
saving.
MODE SELECTION
PIN CONFIGURATION*
~
CE
DE
(18)
(20)
Vpp
\211
OUTPUTS
(9.11,13.17)
Vce
(24)
MODE
--
Read
V,L
V,L
<5
+5
Standby
V,H
Don't Care
+5
+5
DOUT
I
BLOCK DIAGRAM
DATA OUTPUTS
Vcc~
00-0,
GND<>--
PIN NAMES
Y-GATING
Ao-Al0
ADDRESS
INPUTS
16,384 BIT
CELL MATRIX
*Pin 18 and pin 20 have been named to conform with the entire family of 16K, 32K, and 64K EPROMs and ROMs.
4-34
I
Hj~
2616
Absolute Maximum Ratings*
· . _10°C to +80°C
· -65°C to +125°C
Temperature Under Bias . . . . . . .
Storage Temperature . . . . . . . . .
All Input or Output Voltages with
Respect to Ground . . . . . . . .
*COMMENT: Stresses above those listed under "Absolute
Maxj~
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec~
· .. +6V to -0.3V
tions of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
I
READ OPERATION
D.C. and Operating Characteristics
TA = O°C to 70°C, Ve e [1,2J = +5V ±5%, Vpp[2] = Vee ±0.6V
Limits
Parameter
Symbol
Unit
Typ.[3J
Min.
Conditions
Max.
III
Input Load Current
10
fJ.A
VIN = 5.25V
ILO
Output Leakage Current
10
fJ.A
VOUT = 5.25V
IpPl [2J
Vpp Current
5
mA
Vpp = 5.85V
leel[2]
Vee Current (Standby)
10
25
mA
CE = VIH, OE= Vil
lee2[2]
Vee Current (Active)
57
100
mA
OE= CE = V il
Vil
I nput Low Voltage
-0.1
0.8
V
V IH
Input High Voltage
2.0
V e e+ 1
V
VOL
Output Low Voltage
0.45
V
IOl = 2.1 mA
VOH
Output High Voltage
V
IOH = -400 fJ.A
NOTES:
2.4
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee. The supply current would then be the sum of ICC and IpPl.
3. Typical values are for TA = 25°C and nominal supply voltages.
Typical Characteristics
ACCESS TIME
vs.
CAPACITANCE
ICC CURRENT
VS.
TEMPERATURE
70
60
r- r--
50
;;
E
r-- r--
ICC2 ACTIVE CURRENT
CE"'VIL
VCc o5V _ , -
40
700
600
600
500
500
Vee'" 5V
g
ICCl
10
a
w
m
_
•
STA~BY
CURRENT
CE=VIH
Vcc-5V
-
400
.- 300
20
a
700
L¥
u
!::} 30
ACCESS TIME
vs.
TEMPERATURE
400
l-- I---
f.-- +--
300
200
200
100
100
o
~
TEMPERATURE (OC)
M
ro
M
, 00
200
300
400
CL (pF)
4-35
500
600
700
800
~
o
l - I-- I--
w
m
_
•
~
TEMPERATURE eel
M
ro
00
2616
A.C. Characteristics
TA=0°Cto70°C, VCC[1] =+5V±5%, Vpp[2] =Vcc±0.6V
Limits
Symbol
Parameter
Min.
Typ.l4]
Max.
Unit
Test C:mditions
tACC
Address to Output Delay
250
450
ns
CE=OE=VIL
tCE
CE to Output Delay 'elay
280
450
ns
OE = VIL
tOE
Output Enable to Output Delay
120
ns
CE = VIL
tDF
Output Enable High to Output Float
0
100
ns
CE = VIL
tOH
Address to Output Hold
0
ns
CE = OE = V IL
Capacitance [4] T A = 25°C,
Symbol
A.C. Test Conditions:
f = 1 MHz
Parameter
Typ.
Max.
Unit Conditions
CIN
Input Capacitance
4
6
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT= OV
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: ';;;20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1V and 2V
Outputs 0.8V and 2V
A.C. Waveforms [5]
ADDRESSES
VALID
ADDRESSES
CE----------------+_~
--J/
-(450ifAx.)-
OE---------------i----------,
/
.J
[6]
..-
tOE
(120 MAX.)
----
[7]
tOF
(100 MAX.)
[6]
tACC
,
(450 MAX.)
HIGH Z
OUTPUT----------------------------------~i_i_t_<
NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously of after Vpp.
2. Vpp may be connected directly to Vee. The supply current would then be the sum of ICC and lpP1.
3. Typical values are for T A = 2SoC and'nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
5. All times shown in praentheses are minimum times and are nsac unless otherwise specified.
6.
DE may
De delayed up to 330n5 after the falling edge
7. tDF is specified from
ofCE
without impact on tACe.
BE or 'C"E: whichever occurs first.
4-36
VALID OUTPUT
HIGH Z
2616
DEVICE OPERATION
pins, independent of device selection. Assuming that
addresses are stable, address access time (tACC) is equal to
the delay from CE to output (tCE). Data is available at
the outputs 120 ns (tOE) after the falling edge of OE,
assuming that CE has been low and addresses have been
stable for at least tACC - tOE.
The modes of operation of the 2616 are listed in Table I.
It should be noted that all inputs are at TTL levels. Only a
single +5V power supply is required since Vp p may be connected to Vcc.
TABLE I. MODE SELECTION
~
STANDBY MODE
eE
OE
Vpp
Vee
(18)
(20)
(21)
(24)
OUTPUTS
(9-11,13-17)
The 2616 has a standby mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW. The
2616 is placed in the standby mode by applying a TTL high
signal to the CE input. When in standby mode, the outputs
are in a high impedence state, independent of the OE input.
MODE
Read
V,L
V,L
+5
+5
DOUT
Standby
V,H
Don't Care
+5
+5
High Z
OUTPUT DESELECTION
READ MODE
The outputs of two or more 2616s may be OR-tied toge·
ther on the same data bus. Only one 2616 should have its
output selected (DE low) to prevent data bus contention
between 2616s in this configuration. The outputs of the
other 2616s should be deselected by raising the OE input
to a TTL high level.
The 2616 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs.
Chip Enable (eE) is the power control and should be used
for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output
4-37
2708/8708*
8K AND 4K UV ERASABLE PROM
•
Max. Power
Max. Access
2708
800 mW
450 ns
1K x 8
2708L
425 mW
450 ns
1K x 8
2708·1
800mW
350 ns
1K x 8
2704
800 mW
450 ns
512 x 8
Low Power Dissipation Max. (2708L)
425 mW
•
Fast Access Time - 350 ns Max.
(2708·1)
•
Pin Compatible to Intel® 2308 ROM
Organization
•
Static -
No Clocks Required
•
Data Inputs and Outputs TTL
Compatible during both Read and
Program Modes
•
Three·State Outputs - OR·Tie
Capability
The Intel® 2708 is a 8192·bit ultraviolet light erasable and electrically reprogrammable EPROM, ideally suited where
fast turnaround and pattern experimentation are important requirements. All data inputs and outputs are TTL com·
patible during both the read and program modes. The outputs are three·state, allowing direct interface with common
system bus structures. A pin·for·pin mask programmed ROM, the Intel® 2308, is available for large volume production
runs of systems initially using the 2708.
The 2708L at 425 mW is available for systems requiring lower power dissipation than from the 2708. A power
dissipation savings of over 50%, without any sacrifice in speed, is obtained with the 2708L. The 2708L has high input
noise immunity and is specified at 10% power supply tolerance. A high·speed 2708·1 is also available at 350 ns for
microprocessors requiring fast access times. For smaller size systems there is the 4096·bit 2704 which is organized as
512 words by 8 bits. All these devices have the same programming and erasing specifications of the 2708. The 2704
electrical specifications are the same as the 2708.
The 2708 family is fabricated with the N·channel silicon gate FAMOS technology and is available in a 24'pin dual in·line
package.
PIN CONFIGURATION
BLOCK DIAGRAM
DATA OUTPUT
24
Va-0 7
Vee
I
A,
Ag[lJ
\loB
CHIP SELECT
CsIWE-
CS/WE
LOGIC
OUTPUT BUFFERS
"bo
2708/2704
18
A,
A_
O_
--
PROGRAM
16
y
A,-_
A3----r-____________
Y GATING
DECODER
07 (MSB)
~
06
15
ADORESS
INPUTS
A,
A,-_
A,-_
A,-A,--
X
64 X 128
DECODER
ROM ARRAY
1>.9----
13
NOTE 1: PIN 22 MUST BE CONNECTED
TO Vss FOR THE 2104.
PIN NAMES
PIN CONNECTION DURING READ OR PROGRAM
Ao-Ag
ADDRESS INPUTS
0,,08
DATA OUTPUTS/INPUTS
CS/WE
CHIPSELECT/WRITE ENABLE INPUT
PIN NUMBER
ADDRESS
I
INPUTS
9·11,
'·8,
V,S
PROGRAM
VOD
13-17
22,23
12
18
19
READ
DOUT
GND
+12
HIGH IMPEDANCE
A'N
DON'TeARE
GND
DESELECT
GND
GND
+12
PROGRAM
D,N
AIN
GND
PULSED
+12
VIHW
MODE
26V
·
I
DATA I/O
All 8708 speCIfications are Identical to the 2708 speclflcallons.
4-38
CS/WE . Vas
20
i 21
Vee
VIL
-5
+5
V,H
-5
+5
-5
+5
!
24
2708 FAMILY
PROGRAMMING
The programming specifications are described in the PROM/ROM Programming Instructions on page 4·83.
Absolute Maximum Ratings*
_25°C to +85°C
-65°C to +125°C
+20V to -0.3V
+15V to -0.3V
Temperature Under Bias .... .
Storage Temperature ......... .
VDD With Respect to VBB ...... .
Vcc and Vss With Respect to VBB .,
All Input or Output Voltages With Respect
to VBB During Read ....... .
CS/WE Input With Respect to VBB
During Programming ....... .
Program Input With Respect to VBB
Power Dissipation . . . . . . . . . . . .
'COMMENT
Stresses above those listed under "Absolute Maximum
RatIngs" may cause permanent damage to the device.
This is a stress rating only and functional operation
of the device at these·or any other conditions above
those indicated in the operational sections of this
+15V to -0.3V
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
+20V to -0.3V
+35V to -0 3V
1.5W
affect device reliability.
DC and AC Operating Conditions During Read
Temperature Range
2708
2708·'
2708L
O'C - 70'C
O'C - 70'C
O'C - 70'C
Vee Power Supply
5V ± 5%
5V ± 5%
5V ± 10%
VDD Power Supply
12V ± 5%
12V ± 5%
12V±
VBS Power Supply
-5V ± 5%
-5V ± 5%
-5V ± 10%
1()',{,
READ OPERATION
D.C. and Operating Characteristics
2708L Limits
2708, 2108-1 Limits
Symbol
Parameter
Test Conditions
Units
Min.
Tvp.(2)
Max.
Min.
TVP.(2)
Max.
10
10
.A
VIN
1
10
10
.A
VOUT = 5.5V. CS/WE = 5V
von Supply Current
50
65
21
VCC Supply Current
6
10
2
III
Address and Chip Select Input Sink Current
ILO
Output Leakage Current
100(3)
ICC[3)
30
45
28
=
S.2SV or VIN = VIL
mA
Worst Case Supply Currents[41
mA
All Inputs High,
CS/WE = SV; T A = o°c
I'
mA
0.65
VSS
0.65
V
VCC+1
2.2
VCC+1
V
OA
V
IBB[3[
Vea Supply Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH1
Output High Voltage
3.7
3.7
V
IOH = -100 /JA
VOH2
Output High Voltage
2A
2.4
V
PO
Power Dissipation
VSS
3.0
10
10L " 1.6mA (2708. 2708·11
0.45
800
10L = 2mA (2708LI
325
mW
IOH=-l rnA
T A -70oC
425
mW
TA =O°C
NOTES: 1. Ves must be applied pnor to VCC and VOO. Ves must also be the last power supply sWitched off
2. Typical values are for T A = 2SoC and nominal supply voltages.
3. The total power disiipation is not calculated by summing the various currents (lDO. ICC. and ISS) multiplied by their respective voltages 9ince current paths eXist between the various power supplies and VSS. The 'DO. ICC. and ISS currents should be used to determine power supply capacity only.
4. las for the 2708L IS specified In the programmed state and is 18 rnA maximum in the unprogrammed state.
2708L
2708 AND 2708·'
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE
ACCESS TIME VS. TEMPERATURE
~
~
i
ALL POSSIBLE OPERATING
CONDITIONS:
J
1 TTL LOAD + l00pF
Vee"' 5.25V
VDO "' 12.6V
400
VaB " -S.25V
1
~
300
15
!
a
'00
~ 10
....H
200
t
~
_18B
100
20
'"
TA
rei
eo
80
100
.~::t::=t~
o
20
40
80
TAloCI
4·39
80
100
o
·20
-
~
--
20
.,...,......
/
..
TA ('CI
eo
~
2708 FAMILY
A. C. Characteristics
Symbol
Parameter
Min.
tACC
Address to Output Delay
tco
Chip Select to Output Delay
tDF
Chip Deselect to Output Float
0
tOH
Address to Output Hold
0
2708·1 Limits
Typ.
Max.
2708,2708L,Limits
Typ.
Min.
Max.
Units
280
350
280
450
ns
120
ns
120
ns
60
60
0
ns
0
CAPACITANCE!1l TA = 25°C, f = 1 MHz
Symbol
120
120
A.C. TEST CONDITIONS:
Parameter
Typ.
Max.
Unit.
Conditions
CIN
Input Capacitance
4
6
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT =OV
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ';;;;20 ns
Timing Measurement Reference Levels: 0.8V and
2.8V for inputs; 0.8V and 2.4V for outputs.
Input Pulse Levels: 0.65V to 3.0V
Note: 1. This parameter is periodically sampled and is not 100% tested.
Waveforms
ADDRESS
----X=---------------X------\
Ai
I
l---toH--1
CSIWE
~~--tc-o----I---------~
I
l........
1___ --------tACC--~1
I
toF_1
I
DATA
OUT
ERASURE CHARACTERISTICS
form Intel which should be placed over the 2708 window
to prevent unintentional erasure.
The erasure characteristics of the 2708 family are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluores·
cent lamps have wavelengths in the 3000-4000A range.
Data show that constant exposure to room level fluores·
cent lighting could erase the typical device in approxi·
mately 3 years, while it would take approximately 1 week
to cause erasure when exposed to direct sunlight. If the
2708 is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels are available
The recommended erasure procedure (see page 4·83) for
the 2708 family is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The inte·
grated dose (i.e., UV intensity X exposure time) for erasure
should be a minimum of 15 W·sec/cm 2 . The erasure time
with this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 p.w/cm 2 power rating.
The device should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
4·40
inter
M2708
8K (1K x 8) UV ERASABLE PROM
• Static: No Clocks Required
• Inputs and Outputs TTL
Compatible During Both Read
and Program Modes
• Extended Temperature Range:
-55°C to 100°C
• Fast Programming:
Typ. 100 sec. For All 8K Bits
• Low Power During Programming
• Access Time: 450 ns Max.
• Standard Power Supplies:
+12V, +5V, -5V
• Three-State Output: OR-Tie
Capability
• Hermetic Package: 24 Pin DIP
The Intel M2708 is a high speed 8192 bit erasable and electrically reprogrammable ROM (EPROM) ideally suited where fast
turn around and pattern experimentation are important requirements.
The M2708 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows the user to expose the
chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the devices.
The M2708 is fabricated with the time proven N-channel silicon gate technology.
PIN CONFIGURATION
BLOCK DIAGRAM
DATA OUTPUT
A,
Vee
A6
A,
As
A. (MSB)
A,
\10.
A3
CSIWE
A2
M2708
A,
(LSB) Ao
CHIP SELECT
lOGIC
CSIWE-
OUTPUT BUFFERS
1100
PROGRAM
A_
A,
o_
--
07 (MSB)
A2 A,_
(LSB) 00
06
0,
05
0,
0,
\\;s
03
V
ADDRESS
INPUTS
Y GATING
DECODER
A,
A,_
A._
A,-A.-
X
64 X 128
DECODER
AOMARAAY
~-
PIN NAMES
PIN CONNECTION DURING READ OR PROGRAM
Ao-Ag
ADDRESS INPUTS
~!WE
CHIP SELECT/WRITE ENABLE INPUT
PIN NUMBER
ADDRESS
DATA I/O
9·".
13-17
MODE
READ
Dour
~~~~~~~
~H
D,N
IMPEDANCE
INPUTS
1-8,
Vss
PROGRAM
Voo
22,23
12
18
A'N
DON'TeARE
GND
GND
GND
GND
A'N
GND
PULSED
19
+12
+12
+12
VIHP
4-41
CSIWE
20
V"
V,H
VIHW
V,.
Vee
21
-5
-5
-5
2.
+5
+5
+5
M2708
Absolute Maximum Ratings II
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . '-65°C to 110°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . • . -65°C to +125°C
VDD With Respect to VBB . . . . . • . . . . . . . . . . . . . . . . . +20V to -0.3V
Vcc and Vss With Respect to VBB . . . . . . . . . . . . . . . . . +15V to -0.3V
All Input or Output V91tages With Respect
to VB B During Read. . . . . . . . . . . . . . . . . . . . . . . .. +15V to -0.3V
CS/WE Input With Respect to VBB
During ProgramT)1ing . . . . . . . . . . . . . . . . . • . . . . . . +20V to -0.3V
Program Input With' Respect to VBB •. . . . . . . . . . . . . .. +35V to -0 3V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.8W
'COMMENT
Stresses above those Iisted under" Absol ute Max imum
Ratings" may cause permanent damage to the deVice.
This is a stress rating only and functional operation'
of the device at these or any other conditions aboVe
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
READ OPERATION
D.C. and Operating Characteristics
TA
= -55°C to
100°C, Vcc
Symbol
= +5V ±10%,
VDD
= +12V ±10%,
Parameter
= -5V
V BB [1J
Typ.l2J
Min.
±10%,: VSS = OV, unless otherwise noted.
Max.
Unit
Conditions
= 5.5 V or
= VIL
III
Address and Chip Select Input Sink Current
1
10
!J.A
VIN
ILO
Output Leakage Current
1
10
!J.A
VOUT = 5.5 V, CS/WE= 5V
IDD[3J
VDD Supply Current
50
80
mA
Worst Case Supply Currents:
IcC[3J
VCC Supply Current
6
15
mA
All Inputs High
IBB[3J
VB B Supply Cu rrent
30
60
mA
CS/WE = 5V; TA = -55°C
V IL
Input Low Voltage
Vss
0.65
V
VIH
Input High Voltage
3.0
Vcc +1
V
VOL
Output Low Voltage
0.45
V
IOL
VO H1
Output High Voltage
3.7
V
IOH
= 1.6mA
= -100!J.A
VOH2
Output High Voltage
2.4
IOH
=
PD
Power Dissipation
V
750
mW
VIN
-lmA
TA = 100°C
NOTES: 1. VBB must be applied prior to VCC and VDD. VBB must also be the last power supply switched off.
2. Typical values are for T A = 25°C and nominal supply voltages.
3. The total power dissipation of the 2704/2708 is specified at 750mW. It is not calculated by summing the various currents ODD.
ICC, and IBB) multiplied by their respective voltages since current paths exist between the various power supplies and VSS. The
IDD, ICC, and IBB currents should be used to determine power supply capacitY only.
Typical D.C. Characteristics
IBe CURRENT VS. TEMPERATURE
80
1
100 CURRENT VS. TEMPERATURE
......
r--- r......
60
!;:
-
w
a:
a:
a
40
~
il:
OJ
U)
jI 20
ICC CURRENT VS. TEMPERATURE
80
....,
.........
"- .......
o-60
rr--- .......
-40 -20
~
0
~E=HIGH
.'
•. 1
J.
1 60~~--~~--~~--~~--~~
~SIWE=HIGH
r--. ~ r-
-
!;:
w
.......... 1'-,
a:
. . .....
-r--.
CSIWE=LOW-
a:
a
40~-r--~-r--~-r--~-r--~4
~
il:
iil
Jl
20~-r--~-r--~-r--~-r--~4
rCSiE=tW
20
TA
40
rc}
60
80
100 120
o
-60 -40
-20
0
20
40
TA!"C}
4-42
60
80
100 120
~60
-40 -20
0
20
40
60
80
100 120
)fl
M2708
1'"1,
'"",'
A.C. Characteristics
o
0
i"
,,""1,
,',
.....'\ .
TA = -55 C to 100 C, Vee = +5V ±10%, Voo = +12V ±10%, Vaa = -5V ±10%, Vss = OV, Unless Otherwise Noted •
. ·,(;'1
Symbol
Parameter
Min.
Typ.
Max.
2BO
450
ns
60
120
ns
120
ns
--f--
tAee
Address to Output Delay
teo
Chip Select to Output Delay
tOF
Chip De-Select to Output Float
0
tOH
Address to Output Hold
0
-
Unit
ns
A.C. TEST CONDITIONS:
Symbol
Parameter
Typ. Max. Unit Conditions
CIN
Input Capacitance
4
6
pF
VIN=OV
COUT
Output Capacitance
B
12
pF
VOUT=OV
Note 1.
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ";20 ns
Timing Measurement Reference Levels: O.BVand
2.BV for inputs; O.BV and 2.4 V for outputs
Input Pulse Levels: 0.65V to 3.0V
This parameter is sampled and not 100% tested.
Waveforms
ADDRESS
--X-------X----
Intel which should be placed over the M2708 window to
prevent unintentional erasure.
ERASURE CHARACTERISTICS
The erasure characteristics of the M270B are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range.
Data show that constant exposure to room level fluorescent
lighting could erase the typical M2708 in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the M270B is to
be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from
The recommended erasure procedure (see page 4·B3) for
the M2708 is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensity X exposure time) for erasure should
be a minimum of 15 W·sec/cm 2. The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 J.lW/cm 2 power rating. The M2708
should be placed within 1 inch of the lamp tubes during
erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
4-43
2716*
16K (2K x 8) UV ERASABLE PROM
Time
• Fast350Access
ns Max. 2716·1
• Pin Compatible to Intel® 5V ROMs
(2316E, 2332, and 2364) and 2732
EPROM
390 ns Max. 2716·2
450 ns Max. 2716
Programming Requirements
• Simple
Single Location Programming
• Single + 5V Power Supply
Dissipation
• Low525Power
mW Max. Active Power
-
Programs with One 50 ms Pulse
Inputs and Outputs TTL Compatible
• during
Read and Program
• Completely Static
132 mW Max. Standby Power
The I ntel® 2716 is a 16,384-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2716
operates from a single 5-volt power supply, has a static standby mode, and features fast single address location programming. It makes designing with EPROMs faster, easier and more economical. For production quantities, the 2716 user can
convert rapidly to Intel's pin-for-pin compatible 16K ROM (the 2316E) or the new 32K and 64K ROMs (the 2332 and 2364
respectively).
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with the newer high performance
+5V microprocessors such as Intel's 8085 and 8086. The 2716 is also the first EPROM with a static standby mode which
reduces the power dissipation without increasing access time. The maximum active power dissipation is 525 mW while the
maximum standby power dissipation is only 132 mW, a 75% savings.
The 2716 has the simplest and fastest method yet devised for programming EPROMs - single pulse TTL level programming.
No need for high voltage pulsing because all programming controls are handled by TTL signals. Now, it is possible to program
on-board, in the system, in the field. Program any location at any time - either individually, sequentially or at random, with
the 2716's single address location programming. Total programming time for all 16,384 bits is only 100 seconds.
PIN CONFIGURATION*
MODE SELECTION
2732 t
2716
Vee
A7
AS
A6
~
Ag
Ag
Vpp
A11
De
OE/Vpp
(20)
Vpp
(21)
Vee
OUTPUTS
(24)
(9·11,13·17)
Read
V,L
V,L
+5
+5
DOUT
V,H
Don't Care
+5
+5
High Z
+25
+5
Pulsed VIL to VIH
V,H
V,L
V,L
+25
+5
DOUT
V,H
+25
+5
High Z
Program Verify
....__....
OE
(lSI
Standby
Program
02
GND
CE/PGM
MODE
o.
o.
05
04
03
05
Program Inhibit
V,L
D,N
BLOCK DIAGRAM
t Refer to 2732
Veco----
data sheet for
speci fi cati ons
PIN NAMES
ADDRESSES
CHIP ENABLE/PROGRAM
DE
OUTPUT ENABLE
00 01
OUTPUTS
AO-A10
ADDRESS
INPUTS
'Pin 18 and pin 20 have been renamed to conform with the entire family of 16K, 32K, and 64K EPROMs and ROMs. The
die, fabrication process, and specifications remain the same and are totally uneffected by this change.
4-44
2716
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Insutrctions on Page 4-83.
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . . . . . _10°C to +80°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +125°C
All Input or Output Voltages with
Respect to Ground . . . . . . . .
. ... +6V to -0.3V
Vpp Supply Voltage with Respect
to Ground During Program . . . . . . . . +26.5V to -0.3V
*COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
DC and AC Operating Conditions During Read
Temperature Range
V cc Power Supply [1 ,2J
V pp Power Supply [2J
2716
2716-1
2716-2
O°C _ 70°C
O°C .- 70°C
O°C _ 70°C
5V ±5%
5V± 10%
5V ± 5%
V cc ± 0.6V [3J
Vcc ± 0.6V[3J
V cc ± 0.6V [3J
READ OPERATION
D.C. and Operating Characteristics
Symbol
Limits
Parameter
Unit
Typ.l4J
Min.
III
Input Load Current
10
ILO
Output Leakage Current
IpPl [2J
Vpp Current
ICCl [2J
V CC Current (Standby)
ICC2[2J
V cc Current (Active)
VIL
Input Low Voltage
-0.1
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
NOTES:
Conditions
Max.
f.1A
VIN = 5.25V
10
f.1A
VOUT = 5.25V
5
mA
Vpp = 5.85V
10
25
mA
CE = VIH, OE = VIL
57
100
mA
OE=IT=VIL
0.8
V
V c C+ 1
V
0.45
2.4
V
IOL = 2.1 mA
V
IOH = -400 f.1A
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of lee and IPP1.
3. The tolerance of 0.6V allows the use of a driver circuit for switching the Vpp supply pin from Vee in read to 25V for programming.
4. Typical values are for TA "" 25°C and nominal supply voltages.
5. This parameter is only sampled and is not 100% tested.
Typical Characteristics
ACCESS TIME
ICC CURRENT
VS.
VS.
CAPACITANCE
TEMPERATURE
70
60
700
b
r--
i
i
700
I
600
600
leC2 ACTIVE CURRENT
CE=VIL
500
500
VCCi5V - , . -
400
t±-
-t--.
50
:<
40
v
I
u
!:) 30
300
I
I
20
_I----,
i
r
lecl STANDBY CURRENT
CE;VIH
Vec-5V ---;--
10
o
ACCESS TIME
VS.
TEMI'ERATURE
-
I-
200
300
I
I
I
Vce
200
lOa
10
20
30
o
40
50
TEMPERATURE { CI
60
70
80
5V
--
--
laO
!
o
=
400
100
200
300
400
CL (pF)
4-45
500
600
700
800
o
10
m
m
~
m
TEMPERATURE (~C)
M
ro
w
2716
A.C. Characteristics
2716 Limits
Symbol
Parameter
Min
Typ[41
2716-1 Limits
Max Min Typ[41
Max
2716-2 Limits
Min Typ[41
Test
Unit
Conditions
Max
tACC
Address to Output Delay
450
350
390
ns
CE~OE~VIL
tCE
CE to Output Delay
450
350
390
ns
OE ~ VIL
tOE
Output Enable to Output Delay
tDF
Output Enable High to Output Float
0
tOH
Address to Output Hold
0
Capacitance [51
Symbol
TA
= 25°C,
f
Parameter
120
100
120
0
0
0
= 1 MHz
Typ.
100
120
ns
CE = VIL
100
ns
CE
ns
CE=OE~VIL
0
A.C. Test Conditions:
Max_
Unit
Conditions
GIN
Input Capacitance
4
6
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT= OV
'-----
Output Load: 1 TTL gate and CL
ADDRESSES
VALID
CE----------------+_~
=
100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1V and 2V
Outputs
0.8V and 2V
A. C. Waveforms (1)
ADDRESSES
= VIL
____
~x
--oJ/
teE
6E---------------i--------~
[6J
tACC
HIGH Z
OUTPUT----------------------------------+-t-~~
HIGHZ
VALID OUTPUT
NOTE: 1. Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of ICC and IpP1.
3.
The tolerance of O.6V allows the use of a driver circuit for switching the Vpp supply pin from
gramming.
4. Typical values are for T A = 25°C and nominal supply voltages.
5. This parameter is only sampled and is not 100% tested.
6. 5E may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC'
7. tDF is specified from OE or CE, whichever occurs firs!.
4-46
Vee
in read to 25V for prow
2716
TYPICAL 16K EPROM SYSTEM
AB·15
ADO·7
8212
ADDRESS
LATCH
ALE
*1
RD
BOB5
VCC
)-
LS"'_A"
AO-A7
2716
DO-7
1
........
As
~
...
OE
-
~~,.....
~~-
_~r-
CEO
,~
~
~
,~
~
,~
t-
II
512 X B
O.C.
PROM
3604A
M ...
~N
"'''' uu
"''''
101M
uu
I
IT
L--...i CE 1
-~-
""~~
CE2
CE3
=]111
CE4
]
CE5
CE6
CE7
~J-
• This scheme accomplished by using CE (PD) as the primary decode. OE (CS) is now controlled by previously unused
signal. RD now controls data on and off the bus by way of OE .
• A selected 2716 is available for systems which require CE access of less than 450 ns for decode network operation.
• The use of a PROM as a decoder allows for:
a) ALE is required for Edge Enabled devices (32K and 64K), and is optional for 2716.
b) Compatibility with upward (and downward) memory expansion.
c) Easy assignment of ROM memory modules, compatible with PUM modular software concepts.
8K, 16K, 32K, 64K 5V EPROM/ROM FAMILY
PRINTED CIRCUIT BOARD LAYOUT
II
II
0 1 1 '
GN~0:__.• .__. .a~·..a"""",,"'.D.C2."...:........__...
o
c,
REV 1
*
o
.
: COMPONENT SIDE:
000.0
00000
04 Os 06 07 CE2
3nB
4-47
•
2716
ERASURE CHARACTERISTICS
The erasure characteristics of the 2716 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2716 in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the 2716 is to
be exposed to these types of lighting conditions for ex·
tended periods of time, opaque labels are available from
Intel which should be placed over the 2716 window to
prevent unintentional erasure.
signal to the CE input. When in standby mode, the outputs
are in a high impedence state, independent of the OE input.
The recommended erasure procedure (see Data Catalog
page 4-83) for the 2716 is exposure to shortwave ultraviolet
light which has a wavelength of 2537 Angstroms (J\). The
integrated dose (i.e., UV intensity X exposure time) for
erasure should be a minimum of 15 W-sec/cm 2 . The erasure
time with this dosage is approximately 15 to 20 minutes
using an ultraviolet lamp with a 12000 /l-W/cm2 power
rating. The 2716 should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
PROGRAMMING
DEVICE OPERATION
The five modes of operation of the 2716 are listed in Table
I. It should be noted that all inputs for the five modes are at
TTL levels. The power supplies required are a +5V VCC and
a Vpp. The Vpp power supply must be at 25V during the
three programming modes, and must be at 5V in the other
two modes.
TABLE I. MODE SELECTION
~
CE/PGM
DE
Vpp
Vee
(18)
(20)
(21)
(24)
OUTPUTS
(9-11,13-17)
MODE
Read
V,L
V,L
+5
+5
DOUT
Standby
V,H
Don't Care
+5
+5
High Z
Program
Pulsed VIL to VIH
V,H
+25
+5
D,N
V,L
V,L
+25
+5
Dour
V,L
V,H
+25
+5
High Z
r-p~~m Verify
Program Inhibit
OUTPUT DESELECTION
The outputs of two or more 2716s may be OR-tied together on the same data bus. Only one 2716 should have its
output selected (OE low) to prevent data bus contention
between 2716s in this configuration. The outputs of the
other 2716s should be deselected by raising the OE input
to a TTL high level.
Initially, and after each erasure, all bits of the 2716 are in
the "1" state. Data is introduced by selectively programming "a's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "a's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
The 2716
supply is
grammed
pins. The
TTL.
is in the programming mode when the Vpp power
at 25V and OE is at VIH. The data to be prois applied 8 bits in parallel to the data output
levels required for the address and data inputs are
When the address and data are stable, a 50 msec, active
high, TTL program pulse is applied to the CE/PGM input.
A program pulse must be applied at each address location
to be programmed. You can program any location at any
time - either individually, sequentially, or at random.
The program pulse has a maximum width of 55 msec. The
2716 must not be programmed with a DC Signal appl ied to
the CE/PGM input.
Programming of mUltiple 2716s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the paralleled 2716s may be connected together when they are programmed with the same data. A high level TTL pulse
applied to the CE!PGM input programs the paralleled
2716s.
READ MODE
The 2716 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (GE) is the output
control and should be used to gate data to the output
pins, independent of device selection. Assuming that
addresses are stable, address access time (tACC) is equal to
the delay from CE to output (tCE). Data is available at
the outputs 120 ns (tOE) after the falling edge of OE,
assuming that CE has been low and addresses have been
stable for at least tACC - tOE.
PROGRAM INHIBIT
Programming of multiple 2716s in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel 2716s may be
common. A TTL level program pulse applied to a 2716's
CE/PGM input with Vpp at 25V will program that 2716.
A low level CE/PGM input inhibits the other 2716 from
being programmed.
PROGRAM VERIFY
STANDBY MODE
The 2716 has a standby mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW. The
2716 is placed in the standby mode by applying a TTL high
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify
may be performed wth Vpp at 25V. Except during programming and program verify, Vpp must be at 5V.
4-48
M2716
16K (2K x 8) UV ERASABLE PROM
,.
"v.... .•
','"
""'"
•
•
•
- 55°C to
+ 125°C Operation
+ 5V Power Supply
Single
Single Programming Requirements
Single Location Programming
Programs with One 50 ms Pulse
•
•
•
Static Power· Down Mode
•
Inputs and Outputs TTL Compatible
during Read and Program
,
It/
Pin Compatible to Intel® M2316E ROM
± 10% Power Supply Tolerance
The Intel'" M2716 is a 16,384-bit ultraviolet erasable and electrically programmable read only memory (EPROM)
specified over the -55°C to 125°C temperature range. The M2716 operates from a single +5V power supply, has a static
power-down mode, and features fast, single·address location programming. It makes designing with EPROMs faster,
easier and more economical. For production quantities, the M2716 user can convert rapidly to Intel's pin-for-pin compatible 16K ROM - the M2316E.
The M2716 has a static power-down mode which reduces the power dissipation without increasing access time. The
active power dissipation is reduced by over 60% in the standby power mode.
The M2716 has the simplest and fastest method devised yet for programming EPROMs - single pulse TTL level programming. No need for high voltage pulsing because all programming controls are handled by TTL signals. Now it is
possible to program on-board, in the system, in the field. Program any location at any time - either individually,
sequentially or at random, with the M2716's single-address location programming. Total programming time for all
16,384 bits is only 100 seconds.
MODE SELECTION
PIN CONFIGURATION
~
CE/PGM
OE
(18)
1201
Vpp
(211
Vee
(241
OUTPUTS
(9-11,13.17)
MODE
Read
V,L
V,L
+5
+5
DOUT
Standby
V,H
Don't Care
+5
+5
High Z
Program
Pulsed VIL to VIH
V,H
+2.
+.
D,N
Program Verify
V'L
V,L
+25
+5
OOUT
Program Inhibit
V'L
V'H
+25
+5
High Z
BLOCK DIAGRAM
Veco---
OE
CE/PGM
PIN NAMES
Ao-Ag
ADDRESSES
CE/PGM
CHIP ENABLE/PROGRAM
DE
OUTPUT ENABLE
OUTPUTS
o
-01
A.-A,.
ADDRESS
INPUTS
4-49
1
2732
32K (4K x 8) UV ERASABLE PROM
+ 5V
•
Single
•
Simple Programming Requirements
- Single Location Programming
- Programs with One 50 ms Pulse
•
Low Power Mode
::!:
10% Power Supply
•
Pin Compatible to Intel® 2332 ROM
•
Inputs and Outputs TTL Compatible
during Read and Program
•
MCS·80 and MCS·85 Compatible
The Intel@ 2732 is a 32,768-bit ultraviolet erasable and electrically programmable read only memory (EPROM). The 2732
operates from a single +5V power supply, has a low power mode, and features fast, single-address location programming. It makes designing with EPROMs faster, easier and more economical. For production quantities, the 2732
user can convert rapidly to Intel's pin-for-pin compatible 32K ROM - the 2332.
The 2732 has the simplest and fastest method devised for programming EPROMs - single pulse TTL level programming. No need for high voltage pulsing because all programming controls are handled by TTL signals. It is possible to
program on·board, in the system, in the field. Program any location at any time - either individually or sequentially or
at random, with the 2732's single-address location programming. Total programming time for all 32,768 bits is only 200
seconds.
BLOCK DIAGRAM
PIN CONFIGURATION
VCC<>-GND<>-Ag
A11
oe--r-~~~~-r-~~~~-'
A3
OE
CE
A2
A10
CE
Ao-A11
ADDRESS
INPUTS
07
00
06
01
05
02
04
03
PIN NAMES
Ao-A10
Cf
Of
00-07
ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
4-50
I
y·GATING
32,766·8IT
CELL MATRIX
2758*
8K (1 K x 8) UV ERASABLE LOW POWER PROM
•
•
•
•
Fast Access Time: 450 ns Max. in
Active and Standby Power Modes
Simple Programming Requirements
Single Location Programming
Programs with One 50 ms Pulse
•
Inputs and Outputs TTL Compatible
during Read and Program
Low Power Dissipation
525 mW Max. Active Power
132 mW Max. Standby Power
•
•
Completely Static
Single
+ 5V Power Supply
Three·State Outputs for OR·Ties
The Intel® 2758 is a 8192·bit ultraviolet erasable and electrically programmable read·only memory (EPROM). The 2758
operates from a single 5-volt power supply, has a static standby mode, and features fast single address location program·
mingo It makes designing with EPROMs faster, easier and more economical. The total programming time for all 8192 bits
is 50 seconds.
The 2758 has a static standby mode which reduces the power dissipation without increasing access time. The maximum
active power dissipation is 525 mW, while the maximum standby power dissipation is only 132 mW, a 75% savings. Power·
down is achieved by applying a TTL·high signal to the C1: input.
.
A 2758 system may be designed for total upwards compatibility with Intel's 16K 2716 EPROM (see Applications Note 30).
The 2758 maintains the simplest and fastest method yet devised for programming EPROMs - single pulse TTL·level pro'
gramming. There is no need for high voltage pulsing because all programming controls are handled by TTL signals. Now it is
possible to program on·board, in the system, in the field. Program any location at any time - either individually, sequentially,
or at random, with the single address location programming.
PIN CONFIGURATION*
MODE SELECTION
I~
CEIPGM
AR
DE
Vpp
Vee
OUTPUTS
(181
(191
(201
(211
(241
(9-11.13·111
MODE
Read
V,L
V,L
V,L
+5
+5
°OUT
Standby
V,H
V,L
Don't
Care
+5
+5
High Z
Program
Pulsed V tl to V IH
V,L
V,H
+25
+5
D,N
Program Verify
V,L
V,L
V,L
+25
+5
DOUT
Program Inhibit
V,L
V,L
V,H
+25
+5
High Z
BLOCK DIAGRAM
Veco---.
PIN NAMES
Ag-Ao
/PGM
OE
°0-07
AR
ADDRESSES
DE __ r-;====",--_,---'....L..L...L....L...L...L....L...,
CHIP ENABLE/PROGRAM
CE/PGM
OUTPUT ENABLE
OUTPUTS
SELECT REFERENCE
INPUT lEVEL
..,_A9!
ADDRESS
INPUTS
*Pin 18 and pin 20 have been renamed to conform with the entire family of 16K, 32K, and 64K EPROMs and ROMs. The
die, fabrication process, and specifications remain the same and are totally uneffected by this change.
4·51
2758
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions on page 4-83_
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . .
Storage Temperature . . . . . . . . .
All Input or Output Voltages with
Respect to Ground . . . . . . . .
V pp Supply Voltage with Respect
· . _10°C to +80°C
· -65°C to +125°C
*COMMENT: Stresses above those listed under "Absolute Maxi~
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
· .. +6V to -0.3V
maximum rating conditions for extended periods may affect device
reliability.
to Ground During Programming . . . . . +26.5V to -0.3V
READ OPERATION
D.C. and Operating Characteristics
TA=0°Ct070°C, VC C [1,2] =+5V±5%, Vpp[2] =Vc c ±0.6V[3]
Symbol
Limits
Parameter
III
Unit
Typ.[4J
Min.
Input Load Current
10
ILO
Output Leakage Current
IpPl [2J
Vpp Current
ICCl [2J
Vee Current (Standby)
f-lA
VIN = 5.25V
10
f-lA
VOUT = 5.25V
5
mA
Vpp = 5.85V
10
25
mA
CE = VIH, OE = VIL
57
100
rnA
OE=CE=VIL
leC2 [2]
Vec Current (Active)
AR [5]
Select Reference Input Level
-0.1
0.8
V
VIL
Input Low Voltage
-0.1
0.8
V
2.0
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
NOTES:
1.
2.
3.
4.
5.
Conditions
Max.
liN = 10f-lA
V
VCC + 1
0.45
2.4
V
IOL - 2.1 rnA
V
IOH = -400f-lA
Vee must be applied simultaneously Of before Vpp and removed simultaneously or after Vpp.
Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of lee and IpP1.
The tolerance of O.6V allows the use of a driver circuit for switching the Vpp supply pin from Vee in read to 25V for programming.
Typical values are for TA = 25°e and nominal supply voltages.
AR is a reference voltage level which requires an input current of only 10 J.lA. The 2758 81865 is also available which has a reference
voltage level of VIH instead of VIL.
Typical Characteristics
ACCESS TIME
ICC CURRENT
70
60
-
vs.
vs.
CAPACITANCE
TEMPERATURE
-
r-- r-- r-I-
50
~ 40
ICC2 ACTIVE CURRENT
GE=Vll
VCC = 5V
E
'~
!
700
700
600
600
soo
500
400
~
30
.-- 300
20
200
ICC1 STA DBY CURR NT
CE= vlH
Vce'" 5V
'0
o
o
w
ACCESS TIME
vs.
TEMPERATURE
w
•
~
50
TEMPERATURE ("e)
00
ro
-
.....-- ~
I--
-
Vee
5V
300
200
'00
f--r-
'00
o
~
=
400
100
200
300
400
Cl (pF)
4-52
500
600
700
800
o
10
20
30
40
50
TEMPERATURE
(~C)
60
70
80
2758
A.C. Characteristics
TA=0°Ct070°C, Vcc[1] =+5V±5%, Vpp[21 =Vc c ±0.6V[31
Limits
Symbol
tACC
Parameter
Test Conditions
Unit
Typ)41
Max.
Address to Output Delay
250
450
ns
CE=OE=VIL
280
450
ns
OE = VIL
120
ns
CE = VIL
100
ns
CE = VIL
ns
CE=OE=VIL
Min.
tCE
C E to 0 utput Del ay
tOE
Output Enable to Output Delay
tDF
Output Enable High to Output Float
0
tOH
Address to Output Hold
0
A.C. Test Conditions:
Symbol
Parameter
Typ.
Max.
Unit
Conditions
CIN
I nput Capacitance
4
6
pF
V IN = OV
COUT
Output Capacitance
8
12
pF
VOUT= OV
NOTE: Please refer to page 2 for notes.
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: ';;20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1V and 2V
Outputs 0.8V and 2V
A.C. Waveforms [61
ADDRESSES
VALID
ADDRESSES
CE----------------~~
1----(450\rAX.)---J
--I
~--------------~--------~
.J
v
[81
tOF
[71
(100 MAX.)
tACC
,
(450 MAX.)
HIGH Z
OUTPUT----------------------------------i-+-~~
NOTES:
VALID OUTPUT
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of ICC and IpP1.
3, The tolerance of O.SV allows the use of a driver circuit for switching the Vpp supply pin from
4. Typical values are for T A'" 2SoC and nominal supply voltages.
5. This parameter is only sampled and is not 100% tested.
6. All times shown in parentheses are minimum times and are nsec unless otherwise specified.
7. dE may be delayed up to 330ns after the falling edge of CE without impact on lACC.
8. tDF is specified from BE or CE, whichever occurs first.
4·53
Vee in
read to 25V for programming.
HIGH Z
2758
ERASURE CHARACTERISTICS
STANDBY MODE
The erasure characteristics of the 2758 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2758 in approximately 3
years, wh ile it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the 2758 is to
be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from
Intel which should be placed over the 2758 window to
prevent unintentional erasure.
The 2758 has a standby mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW, The
2758 is placed in the standby mode by applying a TTL high
signal to CE input. When in standby mode, the outputs
are in a high impedence state, independent of the OE input.
OUTPUT DESELECTION
The outputs of two or more 2758s may be OR-tied together on the same data bus, Only one 2758 should have its
output selected (OE low) to prevent data bus contention
between 2758s in this configuration. The outputs of the
other 2758s should be deselected by raising the OE input
to a TTL high level.
The recommended erasure procedure (see Data Catalog
page 4·83) for the 2758 is exposure to shortwave ultraviolet
light which has a wavelength of 2537 Angstroms (A). The
integrated does (i.e., UV intensity X exposure time) for
erasure should be a minimum of 15 W-sec/cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes
using an ultraviolet lamp with 12,000 f-IW/cm2 power
rating. The 2758 should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
PROGRAMMING
Initially, and after each erasure, all bits of the 2758 are in
the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations, Although only
"O's" will be programmed, both "1 's" and "O's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
The 2758 is in the programming mode when the Vpp
power supply is at 25V and OE is at V IH. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.
DEVICE OPERATION
The five modes of operation of the 2758 are listed in Table
1. It should be noted that all inputs for the five modes are
at TTL levels. The power supplied required are a +5V VCC
and a Vpp. The Vpp power supply must be at 25V during
the two programming modes, and must be at 5V in the
other three modes. In all operational modes, AR must be
at VIL (except for the 2758 S1865 which has AR at VIH).
When the address and data are stable, a 50 msec,
active high, TTL program pulse is applied to the CE/PGM
input. A program pulse must be applied at each address
location to be programmed. You can program any location
at any time - either individually, sequentially, or at random, The program pulse has a maximum width of 55 msec,
The 2758 must be programmed with a DC signal applied
to tne CE/PGM input_
TABLE I. MODE SELECTION
~
CE/PGM
AR
5E
Vpp
Vee
OUTPUTS
(18)
(19)
(20)
(21)
(24)
(9·11,13-17)
Programming of multiple 2758s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the parallelled 2758s may be connected together when they are
programmed with the same data. A high level TTL pulse
applied to the CE/PGM input programs the paralleled
2758s.
MODE
Read
V,L
V,L
V,L
+5
+5
DOUT
Standby
V,H
V,L
Don't
Care
+5
+5
High Z
Program
Pulsed V IL to V IH
V,L
V,H
+25
+5
D,N
Program Verify
V,L
V,L
V,L
+25
+5
DOUT
Program Inhibit
V,L
V,L
V,H
+25
+5
High Z
PROGRAM INHIBIT
READ MODE
The 2758 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs,
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output
control and should be used to gate data to the outpUt
pins, independent of device selection. Assuming that
addresses are stable, address access time hACC) is equal to
the delay from CE to output (tCE)' Data is available at
the outputs 120 ns (tOE) after the falling edge of OE,
assuming that CE has been low and addresses have been
stable for at least tACC - tOE,
4-54
Programming of multiple 2758s in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel 2758s may be
common. A TTL level program pulse applied to a 2751's
CE/PGM input with Vpp at 25V will program that 2758,
A low level CE/PGM input inhibits the other 2758 from
being programmed.
PROGRAM VERIFY
A verify shauld tK\. perrerrned on the programmed bits to
determine that they Willie cG{tec.tl,y Iilrogr~mmed.The verify
may be performed with VJ>p at <;25V. Except dl.lrln~ programming and program verify, Vpp mustoe at !lV,
3602A, 3622A FAMILY
2K (512 x 4) HIGH-SPEED PROM
3602A-2
3622A-2
3602A
3622A
Typ. TA(ns)
45
55
Max. TA(ns)
60
70
• Low Power Dissipation
--O.3mW fBit
I
• Replaces Two 256x4 PROMs
Without Increasing Board
Area
• Open Collector (3602A)
or Three State (3622A)
Outputs
• Polycrystalline Silicon Fuse
For Higher Reliability
• Sim pie Memory Expansion-Chip Select Input lead
• Hermetic 16-Pin DIP
The Intel® 3602A/3622A are 2048-bit bipolar PROMs organized as 512 words by 4 bits. The fast second generation 3602A/
3622A replaces its Intel predecessor, the 3602/3622. A higher speed version, the 3602A-2/3622A-2, is now available at 60 ns.
All 3602A/3622A specifications, except programming, are the same as the 3602/3622_ Once programmed, the 3602A/3622A
are interchangeable with the 3602/3622.
The PROMs are manufactured with all outputs initially logically high. Logic low levels can be electrically programmed in
selected bit locations. Both open collector and three-state outputs are available_ The power dissipation is typically 0.2 mW/bit.
The pin configuration of the PROMs is the same as the popular 1 K bit, 256 X 4 PROMs with the exception that CS2 (pin 14)
is address As. The bit density of existing 256 X 4 PROM systems can be easily doubled without an increase in area with the
3602A/3622A. These PROMs like the 256 X 4 PROMs, are in 16-pin dual in-line package.
PIN CONFIGURATION
LOGIC SYMBOL
CS
AC
16
Vee
Ac
15
A,
Ac
14
A,
A,
13
cs
A3
Ao
12
0, IlSBI
A,
A,
11
O2
A2
10
°1
A,
0, IMSBI
A,
Ao
0,
A,
A,
OJ
Ac
A"
GNO
0,
4-55
0,
3602A, 3622A FAMILY
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions on page 4-89.
Absolute Maximum Ratings*
'COMMENT
Temperature Under Bias . . . . . . . . . . . -65°C to +125°C
Storage Temperatu re . . . . . . . . . . . .. -65°C to +160° C
Output or Supply Voltages . . . . . . . .. -0.5V to 7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . -1.6V to 5.6V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . 100mA
I
D. C. Characteristics:
Symbol
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
All Limits Apply for Vee= +5.0V ±5%, T A =
Parameter
Min.
Limits
Typ.!1]
oDe
to + 75°C
Test Conditions
Max.
Unit
IFA
Address I nput Load Current
-0.05
-0.25
mA
Vee = 5.25V, VA = 0.45V
IFS
Chip Select Input Load Current
-0.05
-0.25
mA
Vee = 5.25V, Vs = 0.45V
IRA
Address Input Leakage Current
40
Vee = 5.25V, VA =.5.25V
IRS
Chip Select Input Leakage
Current
40
IJ.A
IJ.A
Vee = 5.25V, Vs = 5.25V
VeA
Address Input Clamp Voltage
-0.9
-1.5
V
Vee = 4.75V, IA = -10mA
Ves
Chip Select I nput Clamp
Voltage
-0.9
-1.5
V
Vee = 4.75V, Is = -10mA
VOL
Output Low Voltage
0.3
0.45
V
Vee = 4.75V, IOL = 15mA
leEX
Output Leakage Current
40
/lA
Vee = 5.25V, VeE = 5.25V
Icc
Power Supply Current
140
mA
Vee=5.25V, VAO-+VAS= OV
CS = OV
0.85
V
Vee = 5.0V
V
Vee = 5.0V
VIL
Input "Low" Voltage
V IH
Input "High" Voltage
110
2.0
3622A. 3622A-2 ON L Y
Symbol
1101
Parameter
Min.
Typ.[ll
Output Leakage for High
Max.
Unit
40
!J.A
! mpedance Stage
Ise [2]
Output Short Circu it Current
VOH
Output High Voltage
Test Conditions
VO=5.25V or 0.45V.
Vee=5.25V, CS=2.4V
-20
-25
-70
rnA
V
2.4
NOTES: 1. Typical values are at 250 e and at nominal voltage.
2. Unmeasured outputs are open during this test.
4-56
Vo= OV, Vee =4.75V
10H =-2.4mA, Vee = 4.75V
3602A, 3622A FAMILY
A. C. Characteristics
Vee = +5V ±5%. TA = o°c to +75°C
MAX. LIMIT
PARAMETER
SYMBOL
3602A-2
3622A-2
3602A
3622A
tA++. tA __
tA+_. tA_+
Address to Output Delay
60
70
ns
ts++
Chip Select to Output Delay
30
30
ns
ts __
Chip Select to Output Delay
30
30
ns
LIMITS
SYMBOL
PARAMETER
TYP.
MAX.
CONDITIONS
UNIT
CS = VIL to Select the
PROM
TEST CONDITIONS
UNIT
V IN = 2.5V
C INA
Address I nput Capacitance
4
10
pF
Vee ~ 5V
CINS
Chip-Select Input Capacitance
6
10
pF
Vee
= 5V
VIN
COUT
Output Capacitance
7
12
pF
Vee
= 5V
VOUT
NOTE 1: This parameter
IS
= 2.5V
= 2.5V
only periodically sampled and is not 100% tested.
Switching Characteristics
Conditions of Test:
Input pulse amplitudes· 2.5V
Input pu fse rise and fall times of
5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 15 mA and 30 pF
Frequency of test· 2.5 MHz
15 rnA TEST LOAO
~_ _ _ _J,oo"
~
~6001!
Waveforms
ADDRESS TO OUTPUT DELAY
ADDRESS
INPUT
/,
111.5V
CHIP SELECT TO OUTPUT DELAY
"1~
CHIP
SELECT
INPUT
,..-------+""\.
1.5~,-_______f·5V
I
I
OUTPUT
t A ++
OUTPUT
OUTPUT
4-57
3604A, 3624A FAM I LY
4K (512 x 8) H IG H·SPEED PROM
3604A-2
3624A-2
3604A
3624A
3604AL
Max. TA(ns)
60
70
90
Max. 'CC(mA)
170
170
130/25*
*Standby Current When The Chip is Deselected.
• Fast Access Time
--60ns Max (3604A-2, 3624A-2)
• Four Chip Select Inputs
For Easy Memory
Expansion
• Low Standby Power Dissipation
(3604AL) --32}LW/Bit Max
• J:»_olycrystalline Silicon Fuse
For Higher Reliability
• Open Collector (3604A)
or Three State (3624A)
Outputs
• Hermetic 24 Pin DIP
The Intell!> 3604A13624A are 4096-bit bipolar PROMs organized as 512 words by 8 bits. The fast second generation
3604A/3624A replaces Its Intel predecessor, the 360413624. Higher speed PROMs, the 3604A-2/3624A·2, are now avail·
able at 60 ns. All 3604A/3624A specifications, except programming, are the same as or better than the 3604/3624. Once
programmed, the 3604A13624A are interchangeable with the 3604/3624
The PROMs are manufactured with all outputs initially logically high. Logic low levels can be electrically programmed
in selected bit locations. Both open collector and three·state outputs are available. Low standby power dissipation can
be achieved with the 3604AL. The standby power dissipation is approximately 20% of the active power dissipation.
The 3604A/3624A are available in a hermetic 24-pln dual In-line package. These PROMs are manufactured with the
time-proven polycrystalline silicon fuse technology.
READ:
Pin 22
3604A, 3604A-2
3624A, 3624A·2
No Connect or 5V
5V
+5V
Must be Left Open
3604AL
PROGRAM:
STANDBY:
PIN NAMES
Mode/Pin Connection
Pin 24
3604A, 3604A·2
3624A. 3624A·2
Pulsed 12.5V
Pulsed 12.5V
3604AL
Pulsed 12.5V
Pulsed 12.5V
3604AL
PIN CONFIGURATION
deselected.
-
AOORESS INPUTS
CHIP SELECT INPUTS
01-0S
DATA OUTPUTS
[11
[1) To select the PROM CSI • CS2 = 0
Power dissipation IS automatically
reduced whenever the 3604Al
IS
AO-AS
CS1-CS2 }
CS3-CS4
and CS3 • CS4 = 1-
BLOCK DIAGRAM
LOGIC SYMBOL
-~
~~
:>
"
OUTPUT
BUFFER
I
4-63
I
03
I
0,
I
0,
3605, 3625 FAMILY
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions on page 4-89.
Absolute Maximum Ratings*
'COMMENT
Temperature Under Bias ........... -65°C to +125°C
Storage Temperature . . . . . . . . . . . . . -65°C to +160°C
Output or Supply Voltages . . . . . . . .. -O.5V to 7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . -lV to 5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . 100mA
D. C. Characteristics:
Symbol
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
All Limits Apply for Vee= +5.0V ±5%, T A=
Parameter
Min.
Limits
TypJl1
Max.
Unit
oDe
to +75 De
Test Conditions
Address Input Load Current
-0.05
-0.25
mA
IFS
Chip Select Input Load Current
-0.05
-0.25
mA
Vee=5.25V, Vs=0.45V
IRA
Address Input Leakage Current
40
p.A
Vee=5.25V, VA=5.25V
IRS
Chip Select Input Leakage
Current
40
p.A
Vee=5.25V, Vs=5.25V
IFA
Vee=5.25V, VA=0.45V
VeA
Address Input Clamp Voltage
-0.9
-1.5
V
Vee=4.75V,IA=-10mA
Ves
Chip Select Input Clamp
Voltage
-0.9
-1.5
V
Vee=4.75V,ls=-10mA
0.3
0.45
V
40
p.A
Vee=4.75V,IOL = 15mA
Ve e=5.25V, VeE =5.25V
140
rnA
0.85
V
V
VOL
Output Low Voltage
leEx
3605 Output Leakage Current
Icc
Power Supply Current
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
110
2.0
Vee=5.25V, VAO-->VA9=OV,
CS1=CS2=VIH
Vee=5.0V
Vee=5.0V
3625,3625-2 ON LY
Symbol
Parameter
1101
Output Leakage for High
Impedance Stage
Ise [21
Output Short Circuit Current
VO H
Output High Voltage
Min.
-15
Typ.[l]
-25
Max.
Unit
Test Conditions
40
p.A
VO=5.25V or 0.45V,
Vee:" 25V,CS1= CS2=2.4V
-60
rnA
Va =OV
V
2.4
NOTES: 1. Typical values are at 25° e and at nominal voltage.
2. Unmeasured outputs are open during this test.
4-64
10H =-2.4mA, Vee = 4.75V
3605, 3625 FAMILY
A. C. Characteristics
Vee
= +5V ±5%. TA = o°c to +75°C
Max.
Symbol
tA++. tA __
tA+- .tA_+
ts++
ts __
Parameter
3605
3625
Unit
60
70
ns
Address to Output Delay
Chip Select to Output Delay
Chip Select to Output Delay
PARAMETER
SYMBOL
Limits
3605·2
3625·2
30
30
3030
MAX.
CS"1 =CS2=VI L
to select the
ns
PROM.
ns
LIMITS
TYP.
Conditions
UNIT
TEST CONDITIONS
C INA
Address Input Capacitance
4
10
pF
Vee = 5V
V IN = 2.5V
C INS
Chip·Select Input Capacitance
6
10
pF
Vee = 5V
VIN = 2.5V
COUT
Output Capacitance
7
12
pF
Vee = 5V
VOUT = 2.5V
NOTE 1: This parameter is only periodically sampled and is not 100% tested.
Switching Characteristics
Conditions of Test:
15mA TEST
Input pulse amplitudes - 2.5V
Input pulse rise and fall times of
5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 15 mA and 30 pF
Frequency of test - 2.5 MHz
td
vee
LOAD
30pF
Waveforms
ADDRESS TO OUTPUT DELAY
CHIP SELECT TO OUTPUT DELAY
ADDRESS
INPUT
OUTPUT
OUTPUT
4·65
300n
600n
inter
3608, 3628
8K (1K X 8) BIPOLAR PROM
3608, 3628
80 ns Max.
3608-4, 3628-4
100 ns Max.
• Fast Access Time: 65 ns Typically
• Low Power Dissipation: O.09mW/Bit
Typically
• Four Chip Select Inputsfor Easy Memory
Expansion
• Open Collector (360S) and Three-State
(362S) Outputs
• Hermetic 24-Pin DIP
• Polycrystalline Silicon Fuses for Higher
Fuse Reliability
The Intel® 3608/3628 are fully decoded 8192·bit PROMs organized as 1024 words by 8 bits. The worst case access time of
80 ns is specified over the O°C to 75°C temperature range and 5% Vee power supply tolerances. There are four chip selects
provided to facilitate expanding 3608/36285 into larger PROM arrays. The PROMs use Schottky clamped TTL technology
with polycrystalline silicon fuses. All outputs are initially high and logic low levels can be electrically programmed in selected
bit locations.
Prior to the 8192 bit 3608/3628, the highest density bipolar PROM available was 4096 bits. The high density of the
3608/3628 now easily doubles the capacity without an increase in area on existing designs currently using 512 words by 8
bit PROMs. There is also little, if any, penalty in power since the 3608/3628 power/bit is approximately one-half that of 4K
PROMs. The 3608/3628 are packaged in a hermetic 24-pin dual in-line package.
PIN CONFIGURATION
BLOCK DIAGRAM
DATA OUT 1
vee
0,
0,
A,
Ag (MSBI
21
17
LOGIC SYMBOL
DATAOUT8
0,
0.
CS, *
CSZ
0"
CS,
0.
CS.
0,
0, (MSBI
0,
°7
0.
GND -1..._ _ _r
*PROGRAMMING PIN
PIN NAMES
Ao·A g
ADDRESS INPUTS
cs, - CS~}CHIP SELECT INPUTS[l]
CS 3 - CS 4
0,
-os
OAT A OUTPUTS
-
-
[1] To select the PROM CS, = CS 2 = V1L
and CS3 ;: CS 4 = V 1H
4-66
3608, 3628 FAMILY
PROGRAMMING
The programming specifications are described on page 4-89 of the 1978 Data Catalog_
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ........... -65°C to +125°C
Storage Temperature ... _ ......... -65°C to +160°C
Output or Supply Voltages . . . . . . . .. -O.5V to 7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . -1V to 5.5V
Output Currents ............. _ ......... 100mA
D.C. CHARACTERISTICS:
Symbol
'COMMENT
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device_ This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied_
All Limits Apply for Vcc= +5.0V ±5%, T A =
Parameter
Min_
.----
Limits
TypJl1
Max_
Unit
-0.05
-0.25
rnA
-0.05
oDe
to +75°C
Test Conditions
IFA
IFS
Address Input Load Current
-0.25
rnA
Vee =5.25V, VA=0,45V
Vee=5_25V, Vs=0,45V
IRA
Address Input Leakage Current
40
pA
Vee =5.25V, VA=5.25V
IRS
Chip Select Input Leakage
Current
40
pA
Vee =5.25V, Vs4.0V
----- r----
-
Chip Select Input Load Current
---
_.
-~
- -
f--
I
-
VeA
Address Input Clamp Voltage
-0.9
-1.5
V
VCS
Chip Select Input Clamp
Voltage
-0.9
-1.5
V
Vee=4.75V, IA =_-10mA
Veeo~4.75V, Is=-10mA
0.45
V
Vcc=4.75V, 10L = lOrnA
100
pA
Vee=5.25V, VCE=5.25V
190
mA
Vee =5.25V, VAO--"VA9=OV,
PROM deselected
0.85
V
V
Output Low Voltage
VOL
-Ie Ex---T36Q8 and 3608-4 Output
Leakage Current
0.3
Power Supply Current
Icc
I
I
I
VIL
VIH
-
1----
-----~ ~-
150
I
Input "Low" Voltage
Input "High" Voltage
2.0
Vee=5.0V
Vec=5.0V
3628,3628-4 ONLY
Symbol
Parameter
1101
Output Leakage for High
Impedance State
Ise [2]
Output Short Circuit Current
VOH
Output High Voltage
NOTES:
Min.
TypJl1
-20
-25
2,4
3,4
1. Typical values are at 25° C and at nominal voltage.
2. Unmeasured outputs are open during this test.
4-67
Max.
Unit
100
pA
-80
mA
V
Test Conditions
VO=5.25V or 0,45V,
Vee =5.25V,CS, =CS 2 =2,4V
Vo = OV
10H =-2,4rnA, Vee = 4.75V
--
3608, 3628 FAMILY
A.C. CHARACTERISTICS Vee = +5V ±5%.
= oOe to
TA
+75°e
MAX. LIMITS
3608
3628
3608-4
3628·4
tA
Address to Output Delay
80
ns
cs,
tEN
Output Enable Time
40
100
45
ns
and e~
tOIS
Output Disable Time
40
45
ns
to select the PROM.
SYMBOL
PARAMETER
UNIT
CONDITIONS
= CS:! = VIL
=CS4 = VIH
CAPACITANCE(1I TA = 2Soe. f= 1 MHz
SYMBOL
PARAMETER
TYP. LIMITS
TYP.
MAX.
UNIT
TEST CONDITIONS
C INA
Address Input Capacitance
4
10
pF
Vee = 5V
V IN = 2.5V
CINS
Chip·Select Input Capacitance
6
10
pF
Vee = 5V
VIN = 2.5V
COUT
Output Capacitance
7
15
pF
Vee = 5V
VO UT = 2.5V
NOTE 1: This parameter is only periodically sampled and is not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test:
Input pulse amplitudes· 2.5V
Input pulse rise and fall times of
5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 15 mA and 30 pF
Frequency of test· 2.5 MHz
15mA TEST
LOAD~vee
300n
30pF
600n
WAVEFORMS
ADDRESS TO OUTPUT DELAY
CHIP SELECT TO OUTPUT DELAY
<:S,.es, ---""""' , - - - - - - - ' "
ADDRESS
INPUT
r---
CS .CS. _ _ _- - ' ' - -_ _ _ _ _ _...1 ' -_ __
3
OUTPUT
OUTPUT
'A
'A
'A
'A
1.5V
'EN
OUTPUT
4·68
PROM AND ROM PROGRAMMING INSTRUCTIONS
TABLE OF CONTENTS
Page No.
I.
PROM AND ROM INPUT FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4·70
A.
Acceptable Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
B.
Paper Tape Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71
1.
2.
3.
C.
Computer Punched Card Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73
1.
2.
D.
III.
Intellec Hex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73
PN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
Custom PROM/ROM Order Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76
1.
2.
3.
4.
5.
6.
7.
II.
Intellec Hex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71
BPNF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72
Non-Intellec Hex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73
MaS EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-77
8741.8748.8755 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-77
2316E, 2616, 8316A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
8041,8048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
2608,8308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
8355 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81
Bipolar PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
MOS EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-83
A.
Erasure Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-83
B.
1.
UV Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-83
1702A/1702AL Family Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
C.
2708/2704 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
D.
2716 and 2758 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
BIPOLAR PROM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-89
4-69
I.
PROM AND ROM INPUT FORMATS
A.
Acceptible Formats
Intel can accept programming and masking information for PROMs, EPROMs, or ROMs in the form of floppy disk, punched
paper tape, a master device from which to copy, or computer punched cards. The allowable formats are given in Table 1. The
preferred formats for the paper tape and computer card input media are the Intel Intellec Hex and BPNF since these formats
are defined to allow detection of errors.
It is desirable that two, preferably different, input media for each customer code be sent so Intel can perform a code verification to detect any errors between the two inputs. This procedure, if followed, can avoid errors due to a mispunched tape/card
or sending a defective or improper master device.
All orders must be accompanied by a customer PROM/ROM order form. A copy of the form is contained in this section and
additional copies are available from Intel Literature Department, 3065 Bowers Ave., Santa Clara, California 95051.
Table I. Acceptable Formats
---Floppy Disk
• Intel Microcomputer
Development System
Single or Double
Density Disk
Paper Tape
Computer Card
• Intel lee Hex
• Intellec Hex
• BPNF
• PN
• Hex
Master Device
• Same Density and
Pin Compatible
to Device which
is to be Programmed.
A 1. Logic l.evels
All data field for Intel's EPROMs/PROMs/ROMs are positive logic. The only exceptions are the 4001 and 4308 ROMs which
use negative logic. For the 4001/4308, an "0" is a high output and a "1" is a low output. Consequently, because the BPNP
format specifies the voltage level at the output of the device, it is necessary to input an "0" and "1" in the 4001/4308 instruction code as a "P" and "N" respectively. However, for the Hex format, the 4001/4308 input should be specified according to the instruction code logic state, i.e., a "1" or "0." The below example shows the corresponding input for 4001 instruction codes. For comparison, the input for an 80S0A is also given as an example.
1. 4001 Instruction Code
4001
Instruction
Mnemonic
f---NOP
WRM
~~""
H.,
Or Non-Intellec
4001
Instruction
Code
Hex Input
0000 0000
00
BPPPPPPPPF
1110 0000
EO
BNNNPPPPPF
BPNF
Input
-2. SOSOA Instruction Code
,---
Instruction
Mnemonic
Instruction
Code
Intellec Hex
Or Non·lntellec
Hex Input
BPNF
Input
JMP
1100 0011
C3
BPPNNNNPPF
Push D
1101 0101
D5
BPPNPNPNPF
4-70
--
B.
Paper Tape Format
The paper tape which should be used is 1" wide paper using 7 or B-bit ASCII code (such as a Model 33 ASR Teletype produces). The three paper tape formats which should be sent are described in Sections Bl through B3.
B1. InteHee Hex Paper Tape Format
In the Intel Intellec Hex Format, a data field can contain either B or 4-bit data. Two ASCII hexadecimal characters must be
used to represent both Band 4-bit data. In the case of 4-bit data, only one of the characters is meaningful and must be
specified on the Intel PROM/ROM Order Form.
Preceding the first data field and following the last data field there must be a leader/trailer length of at least 25 null characters. Comments (except for a colon) may be placed on the tape leader.
The format described below is readily generated by the Intel Intellec Microcomputer Development System or by systems
programmed by the user.
1. RECORD MARK FIELD: Frame 0
The ASCII code for a colon (:) is used to signal the start of a record.
2. RECORD LENGTH FIELD: Frames 1 and 2
The number of data bytes in the record is representated by two ASCII hexadecimal digits in this field. The high-order
digit is in frame 1. The maximum number of data bytes in a record is 255 (FF in hexadecimal). An end-of-file record
contains two ASCII zeros in this field.
3. LOAD ADDRESS FIELD: Frames 3-6
The four ASCII hexadecimal digits in frames 3-6 give the address at which the data is loaded. The high-order digit is in
frame 3, the lower-order digit in frame 6. The first data byte is stored in the location indicated by the load address;
successive bytes are stored in successive memory locations. This field in an end-of·file record contains zeros or the starting address of the program.
4. RECORD TYPE FIELD: Frames 7 and 8
The two ASCII hexadecimal digits in this field specify the record type. The high-order digit is in frame 7. All data
records are type 0; end-of-file records are type 1. Other possible values for this field are reserved for future expansion.
5. DATA FIELD: Frames 9 to 9+2* (record length)-1
A data byte is represented by two frames containing the ASCII characters 0-9 or A-F, which represent a hexadecimal
value between 0 and FF (0 and 255 decimal). The high-order digit is in the first frame of each pair. If the data is 4-bit,
then either the high or low-order digit represents the data and the other digit o' the pair may be any ASCII hexadecimal
digit. There are no data bytes in an end-of-file record.
4-71
6. CHECKSUM FIELD: Frames 9+2*(record length) to 9+2*(record length)+l
The checksum field contains the ASCII hexadecimal representation of the two's complement of the 8-bit sum of the
8-bit bytes that result from converting each pair of ASCII hexadecimal digits to one byte of binary, from the record
length field to and including the last byte of the data field. Therefore, the sum of all the ASCII pairs in a record after
converting to binary, from the record length field to and including the checksum field, is zero.
Intellec Hex Example:
: 10310000311A320E03117E31CD40003A9231B7C2EE
: 1031100060310EOOl17031CD40003A9231B7C2607B
: 10312000312A7E31227A310E03117E31CD40003ABO
: 103130009231B7C260312A8C317CB5CA50310E044D
: 10314000118831CD40003A923187C26031C3273186
: 103150000EOll17A31CD40000E09119031CD4000A1
: 103160000EOCl19231CD40000E09119031CD40006E
:OA3170007E3196310100000092311B
: 10317C0092310100963180008C31923100009631F1
:04318E009231923187
: 02319400923176
: 00310001CE
B2. BPNF Paper Tape Format
The format requirements are as follows:
1. All data fields are to be punched in consecutive order, starting with data field 0 (all addresses low). There must be
exactly N data fields for a N x 8 or N x 4 device organizations.
2. Each data field must begin with the start character 8 and end with the stop character F. There must be exactly 8 or 4
data characters between the Band F for a N x 8 or N x 4 organization, respectively.
NO OTHER CHARACTERS, SUCH AS RUBOUTS, ARE ALLOWED ANYWHERE IN A DATA FIELD. If in preparing a tape an error is made, the entire data field, including the 8 and F must be rubbed out. Within the data field, a P
results in a high level output, and an N results in a low level output.
3. Preceding the first data field and following the last data field, there must be a leader/trailer length of at least 25 characters. This should consist of rubout punches (letter key for Telex tapes) or null characters.
4. Between data fields, comments not containing 8's or F's may be inserted. Carriage return and line feed characters
should be inserted (as a "comment") after each 72 characters. When these carriage returns, etc., are inserted, the tape
may be easily listed on the teletype for purposes of error checking. The customer may also find it helpful to insert the
word number (as a comment) at least every four word fields.
5. Included in the tape before the leader should be the customer's complete Telex or TWX number and if more than one
pattern is being transmitted, the device pattern number.
6. MSB and LSB are the most and least significant bit of the device outputs. Refer to the data sheet for the pin numbers.
Example of BPNF 2048 x 8 format (N
Start characterl
Leader: Null characters, B
Rubout Key for TWX, or I
Letter Key for Telex
(at least 25 frames)
=2048):
Stop characterl
Data Field
P P P N N N N N F BfN N N N N N P
II
I
Word Field 0
Laader: Rubout Key
for TWX and Letter
Key for Telex (at least
25 frames)
I
Word Field 1
BPNPN F
II
I
Word Field 2047
n
Stop crracter
I
LSB
ptF ••• B ~ P N P P P N t F
I
Example of 512 x 4 format (N = 512):
Start characterl
MSB
II
MlB
LiB
B N N N N F ••••••• B P P P P F
I
I
I
L......_..-_..J
Word Fiald 0
Comment
(saa text)
Word Fiald 1
4-72
Trailer: Null characters,
I Rubout Key for TWX, or
Letter Key for Telex
(at least 25 frames)
Word Field 511
Trailar: Rubout Key
for TWX and Letter
Key for Telex (at least
25 frames)
83. Non-Intellec Hex Paper Tape Format
For the non-Intellec Hex Format, a data field can contain either 8 or 4-bit data. Two ASCII hexadecimal characters must be
used to represent both 8 and 4·bit data. In the case of 4·bit data, only one of the characters is meaningful and must be
specified on the Intel PROM/ROM Order Form.
Parity is allowed; however, it is not checked. Preceding the first data field and following the last data field there must be a
leader/trailer length of at least 25 null characters or rubout punches.
The format requirements are as follows:
1. The start of the first data field is indicated by a colon. After the last data field, a semicolon must be punched to indicate the end. All data fields are to be punched in consecutive order, starting with data field OOH (all addresses low).
2. Two hex characters must be used to represent the data field of both N word x 8-bit and N word x 4-bit devices. For all
8-bit data field, the high order data is represented by the left justified character of the pair. Either character of the pair
may be used to represent the word field of a N word x 4-bit device, however, it must be consistent throughout the word
field. The other character may be any hex character.
A field of "don't care" data is allowed. Data after a field of "don't care" will be programmed starting at an address
location enclosed in parentheses. In the following example, data is entered in addresses OOH to 05H, followed with
"don't care" from addresses 06H to 25H, data being entered again starting at address location 26H, and followed with
"don't care" data to the last address location.
y:?OF2145100FFI~6)117B0890F1IliJ
~-------r===-~~I
I
IL-~=J--------I
I
Data Fields from
Address OOH to 05H
Start Character
Address Location
where Data is to be
Programmed
Data Fields from
Address 26H to 2AH
End Character
3. The x character may be used to rubout any erroneous character(s). The # character may be used to rubout an entire
line up to the previous carriage return.
4. Spaces are allowed only between separate word fields.
5. After each 72 characters, a carriage return followed by a line feed should be punched to allow a print-out of the tape.
6. Comments must be placed only between the tape leader and the start of the first data field.
C.
Computer Punched Card Format
The following general format is applicable to the programming information sent on computer punched cards:
1. An 80 column Hollerith card (interpreted) punched on an IBM 026 or 029 keypunch should be submitted.
2. A single deck must consist of a Title Card followed by the data cards. There will be N/8 or N/14 data cards for N words
x 8-bit and N words x 4-bit devices, respectively, in the PN format.
For the Intellec Hex format, there will be N/32 data cards for both N words x 8-bit and N words x 4-bit devices, and
one end of fi Ie card.
C1. Intellec Hex Computer Punched Card Format
Two hex characters must be used to represent data for both a N word x 8-bit and N word x 4-bit device. For the latter, only
one of the characters is meaningful and must be specified on the Intel PROM/ROM Order Form. The entire data field for all
bits must be punched even if it is "don't care".
I
~uS;:ER"il
DECIMAL NUMBER INDICATING
THE TRUTH TABLE NUMBER
NO. OF OUTPUTS
4 or 8
CUSTOMER'S
DIVISION OR
LOCATION
INTEL
PIN
-,,'i"
I'"
III
111111111
I
II
•~ ~ ~ ~!.! ~ ~,o~, ~!,~,~ ~,~ ~!J~~r.o'~'r~~'~~'~~~ ,~~,~ft~,~!~!~ .o,~,,~~~~,!.~~,o ~,,~~~!,'~!~,!~,~~,~~~~,!~,!~ rO,~,,~~,~,~,~,~!
Column
1
2-3
Customer Company Name
Blank
Customer's Company DIVIsion or location
Blank
Customer Part Number
64-72
Punch the Intel 4·dlglt ba51c part number and
In ( ) the number of output bits, e.g., 2708
{S}, 2316 {8}, or 3605 (4)
Blank
Chip number for ROMs with programmable
chip select Inputs, If not applicable, leave
blank
Blank
Punch a 2·digit deCimal number to Indicate
truth table number. The first truth table
Will be 00, second 01, third 02, etc.
111111111111111111111111111111111111111111111111111111111111/1111111111111111111
441, ••••• ,III •• 1.4.ljll.ljl.,.jl.'4IHjUUI4.411.44'1l ... 11l1UI111lI1411Ill.'1
73-74
75-76
\\\\\\\\\111\\\\11\\\\\\\\\\\\\\\\\\1\\\\\\\\\\\\\\\\\\\\\\\5\1\\\\\\\\1111\\\\\
,;,1"666.61.,'1,.,.6111.'1,6,16;."1,, ••• 1'1"6'01"61&'6611.61,16.6",'&'666,6
11111111111111111111111111111111111111111111111111111111111111111111111111111111
8181B818181B8111181118181811118111181188118811811!8181181188888.8888881111818118
!! ~! 9;~! 19~2::'~~ ~ 1~ ~,~;,9 :,~,U ~ ~.~!,~ 1. J, ~;,!~ !,9, ;,:,~.:,H,~..l :,:,1 ~;, ~,~,; 9, g! 9, 9, 9 ~ 9 91,1 .9, ~ 9,991111 q; 1 ,1
4-73
Blank
4-28
29-30
31-50
51-52
53-61
62-63
11111111111111111111111111111111111111111111111111111111111111111111111111111111
IlllllllllllnlllllllllllllllllllllllllllllllllllllllllJllJIIIllIIIIIIIlIJl)!)I)
Data
PunchaT
77-78
79-80
Bla'1k
a. N word x 8·bit device
Column
2-3
4-7
8-9
10-73
75-75
76-78
79-80
Data
Record mark: A colon is used to signal the
start of a record.
Record length: This is the count of the actual
data bytes in the record. Column 2 con·
tains the high order digit of the count,
Column 3 contains the low order digit. A
record length of zero indicates end of file.
All frames containing data will have a
maximum record length of 10HEX bytes
(16 decimal).
Load address: The four characters starting
addresses at which the following data will
be loaded. The high order digit of the load
address is in Column 4 and the low order
digit is in Column 7. The first data byte is
stored in the location indicated by the load
address. Successive data bytes are stored in
successive memory locations. ROMs con·
taining more than 16 bytes of data will use
two or more records or cards to transmit
the data. Although the load address for the
beginning record need not be 0000, each
subsequent load address should be "1 0H"
(16 decimals) greater than the last.
Record type: A 2-digit code in this field specifies the type of this record. The high order
digit of this code is located in Column 8.
Currently, all data records are type O. Endof-file records will be type 1; they are, distinguished by a zero RECORD LENGTH
field (see above). Other possible values for.
this field are reserved for future expansion.
Data
Checksum: Same as paper tape format.
Blank
Punch same 2-digit decimal number as in Title
Card.
b. N word x 4-bit device
This format is identical to the previously documented 8-bit hexadecimal format with the following exceptions:
Column
Data
10-73
Each memory location is represented by two
columns containing the characters 0-9,
A-F. Since this is 4-bit data, the user must
indicate which character of each pair is to
be used as valid data. A single deck must be
submitted without mixing first and second
characters of the pair.
4·74
C2. PN Computer Punched Card Format
A word field consists of only P's and N's. A punched P will result in an output high level and a punched N in an output low
level. The B imd F characters, unlike the paper tape format, are illegal characters. The entire data field for all bits must be
punched even if it is "don't care". The data field must begin in consecutive order, starting with address 0 (all addresses
logically low).
1
INT:~lrB
DECIMAL NUMBER INDICATING
THE TRUTH TABLE NUMBER
NO. OF OUTPUTS
TITLE CARD
DESIGNATION
1
PIN
CUSTOMER'S
DIVISION OR CUSTOMER'i
PIN
LOCATION
I
,-'L-,
CUSTOMER'S
COMPANY NAME
.
I
.... r~~r..,..iNjC) CORP
\',~
I II
II
I
I
III
":,.,:'IJ',l
III
GLAlh~
C!~Lrr
(~.
I.'
00
I
I I I I II II
I
lOG II 0111 0 0 0 I 01 0 0 0 0 01 0 00000000000 DDI 0 0111 a0 0 DOD 0 0 0 0 0 0 0 0 DOD 0 0 0 DOD 0 0 0 II D0 010 II 0 0 0 0 U0 II
I! I ' ' 1 / ' "011 1111'11\1111 "'II'!lII'JI.nIUIIIIIIIJI JlJlJlIUUIIIJUU'I/lI"'IIIUII 1!1II\15l1l1011iIilIIIlIIlUIIIIUHUUIUlllltllIlIl.IIIIUI.fI ..
Column
Data
1
2-3
4-28
29-30
31-50
51-52
53-61
62-63
64-72
Punch a T
Blank
Customer Company Name
Blank
Customer's Company Division or location
Blank
Customer Part Number
Blank
Punch the Intel 4·digit basic part number and
in ( ) the number of output bits; e.g., 2708
(8),2316 (8). or 3605 (4)
Blank
Chip number for ROMs with programmable
chip select inputs. If not applicable, leave
blank.
Blank
Punch a 2·digit decimal number to indicate
truth table number. The first truth table
will be cio; second 01, third 02, etc.
1111111111 I 1111111111111 L111111111111111111111111111111111111111 I 1111\11111' 1111
22222222222222222221222222222222221222222222 222222 22222 222 21222222222 22222222 221
Ill] 11131 31 31131331 JJll 3 Jl J J3 J J J3 333 313 31133 J 3131] J3UJJ 33]3133 33 3 311333 J 3 3 J 3] J 3
44UUU4UU4CUUUCUUCUUUC4HUUCUCCCUCUUCUCU4ICUCU4 CI'CC4U4U
73-74
75-76
5555 5 5 5 5 51515 5 S515 S5 5 5 5 5 S S5 5 5 5 5 5 5 5 5 515 5 5 5 5 5 5 5 55555555555 5 ~ 5 5 5 SIS 5 5 5 5 5 5 51515 55555
6 &is 6 66 6' 6' 6 &, 616 u' 6 616 &6' &, &6 6 6 6 &6' 6 6 6 6 6 &6 6 6& 6 6 616' 6 &6 6' 6 6 6 6 6 6& 6 6 6 6 &6' 6 6 6 6 &6 6 6
1111111111 t, 1 t 1111'11111111'" 11 J " '" 1111' " 111 J 111111' 11111' 11' " 1111111171111
77-78
79-80
88888 8IB 8 B8888 8B IB 8 88 81 8 II 81111 II HI 8 81 8 8 B88 8 UBiBB II 8188 8 8 8 B8B 8 8 8 8 8 88 8 81118 8 BU8 8
9999 H 919 9 9 9 9 919 9199 9 9919 9 9 9 9 9 99' 9 9 9S 9 9 9 9 9 919 9 3 9 919 9 9 9 9 9 9 9 9 9 9 9 ~ 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
, I I • , I • I I
'~.'~
'I • ~'I! 'I II 'III Itl' 1/ 111<111,11 IIllli II 1/ \II' II lUI II 1"'" 11"'''1'10'"" 'h' IHn. loll \1 .1'1'1,'1/"1<:1
tllll$.'I~
II 'IIJ" • 'I ,III 1,1
Title Card Format.
For a N words X 4·bit organization only, cards 2 and
those following should be punched as shown. Each card
specifies the 4·bit output of 14 words.
LSBDECIMAL WORD
ADDRESS BEGINNING
EACH CARD
,--L-,
/J)fJIJO f'ttf'h
h~hl'1
r.nSBi
14 DATA FIELDS
I
Column
1·5
DECIMAL NUMBER
INDICATING THE
TRUTH TABLE NUMBER
),
PPPP I"thhP PPhh f'ltiPP PPPI1 Pf'tPIi PPftli ltPPP PWtlt F'PPf' !trtPP PI1f'tP
00
1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
111110 GlOG DOD DOD 0 D' 0 0' DDDI 00 0 DGDI 00 0 DDOG I 0 I ODD 0 I DO~ DDGD~OD 0 I 0 0 I DOD 0 aDO 0 DDDDOl DII
I J J , II I I .lI" IIIJ1"I""I1I1Ml'IIiUltllIlIIItItWnJZDJtII.II • • • nll'l"III'''.''1I11111111111I1I1I111I"UIIIIIIIIIIIIIIIIIIIIII""I1I1I1II11
11111111111111111111111111111111111111111111111111111111111111111111111111111111
I I I I I I I I II 2I I I I I I I II I I I I I I II I I I ZZZZ I I I I I I I II I I I I II I I I I I I I II I I I I I I I I I I IZZ I I I I I I I t
33333333 31333 J 3H]33]!3]3] 3 33]] 33 3 3J 33 3 333 33 333 3113 J 3 J 33 J 33 11 1 3313 J1 J 31]3 3 33 1 J 3 3
H
~~~
t t tt t t t t. t t 4 t H 4. t 4 t 4 t t I l l ( ' ~ 4 4 4 4 4 4 4 U 4 4.44 •• 44. 4 t 4. t. 4.4 •• 4 t 4. t ~ 4 4 4'~"'"
5 5 55 5 55151511115 5 55 551115 5 5,II, 1115 51111111111 5 511S1S 511511115 5 55 5115 51511515 511'
fi'
6 6' 6 &, 6' 6' 6 G' 5' 6' &, & 6 6 6 &b' ~ 6 6 6 &6""""" 6 6' 6' 6' 6' &, 6 6 &6; 6 6 6 6" 6 6" 6 6 6" 6' S
1221111111' 111 21111111 2111111111/1111112 112111111/1111111111111111 2111111 211 22; 1
'6
I B811811818118' 8 IIUI"8 8 B81888 I Bel .. 1 88111 B8111 8 B8 II 8'" 8 lUll B.11 .. II BIIIII 8 8 B
9999 9
g, 9 919!9 9 9 9 99 U t 99 9 9 99 9 9 UI9 911t' 99' 99 9 9 9 99 9 9 S9 9 9! 9 9 9 9 99! 9 9 9 9 9 9 9 S9 9 9 9 999 9 9'
11 I I II
1IIIal~lIlllll\lInllltlOl\IIIJII~I"JIIIIIIII"IJIUI.III1I"'''1HIIUS.III1'llIllllilllllllolllllll6l1llm.u.iiIIiUllOl1lll1l1llllllllll11
6
7-10
11
12-15
16
17·20
21
22·25
26
27-30
31
32-35
36
37-40
41
42-45
46
47-50
51
52-55
56
57-60
61
62-65
66
67-70
71
72-75
76-7B
79-60
4-·75
Data
Punch the 5 digit decimal equivalent of the
binary coded location which begins each
card. The address is right justified, I.e.,
rllrIIflrMI,IIJ(Iff14, rMlrII2B, etc.
Blank
Data Field
Blank
Data Field
Blank
Data Field
'Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Punch same 2 digit decimal number as In
title card.
For a N words X 8-bit organization only, cards 2 and
those following should be punched as shown. Each card
specifies the 8-bit output of 8 words.
Column
1-5
MSB ~SBDECIMAL WORD
ADDRESS BEGINNING
EACH CARD
8 DATA FIELDS
DECIMAL NUMBER
INDICATING THE
TRUTH TABLE NUMBER
r'-t
rL,
11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111
111110000 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 a0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 0 0 DO 0 0 0 0 0 0 0 0 0 0 0 0 011
I I I ' \ I PI! "" 1:ll"'\liIJlIIII~l'nlllH\HHIU"Dl'l!»I"SlllIJlllIHI'/OlO"\"""'I\I\'\/ll\tI\Ii\I\llllGlllllliUIIHIIIII IIJI 1111 1111 II IIIIIUI
111111111111111111111111111111111111111111111111111111111111111111111111\11\1111
222 n 11122 1212 212! 222 22 111l2il 222 22 2 22 22 221 n 2 222 2i2 22 2/2 2 22 22 III n 2 Z2 22 2 Z2 21121
J J I 33 J 1 33 J J J 1 Jj J3 JJ 1 ) 11 J JJ 3 n 111111 )] J 1 3] J 1 3111 J I 3ll J 11 3 J 11 33 3131 3 3 ] J ] 3 3 J 3 ] ] J 11 3
4 4 , 4 44 4 44 4, 4444 4 444 4 44 4 44 44, 4 j
j I
~ S5 5 5 5 sis 111115 5 S 5 51115 55 51111"
~
l J
I
t
44 • 4 44 44 44 44 4f 444 44 4 44 44 44 4 444 4 4 44 44 44 4 , 4 44 4 4
~ 5 i liS 515 5 5 1115 5 5 5111115 5 5 5115 5 1115 5 5115 511S 5 5 5
t 6 ~ 6 6 6 G5 6 6 Ii S 6 6 6 6 Ii 6 Ii 6 6 6 ES [ Ii t b 6 5 6 t 6 6 6 Ii 6 6 6 6 Ii 6 6 6 6 6 6 6 ~ 6 6 6 6 &&6 6 6 ES S 6 GU6 Ii 6 6 6 5 6 6 6 Ii 6 6 6 6 6 &
"'" '1'1':'" :11111' 'I'll' " '11'111' 'II' 'II" 'III, 1/111111' I ,II, 1/1,111111 ,II;'
B8 a8 8 8 BB8 8 tt i B8 B88 B8 8 8 8 8 gg 8 8 B8 B8 6 as 8 B8 BB8 8 8 8 8 BBB68888 B8S 8 8 8 8 8 BB8 8 B8 8 BB8 B8 8 B888 B8
6
7-14
15
16-23
24
25-32
33
3441
42
43-50
51
52-59
60
61-68
69
70-77
78
79-80
Data
Punch the 5 digit decimal equivalent of the
binary coded location which begins each
card. The add,ess Is right iustified, I.e"
001100,1100118,1100 16, etc.
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Punch same 2 digit decimal number as in
title card.
D.
Custom PROM/ROM Order Forms
All orders for PROMs/ROMs which are to be electrically or mask programmed at Intel must be submitted with the order
forms shown on the following pages. Additional forms are available from Intel Literature Department, 3065 Bowers Ave.,
Santa Clara, California 95051.
The order forms for the individual PROMs/ROMs are listed in Table II below.
Table II
PROM/ROM
Part Number
Order Form
Number
MaS EPROMs
8741,8748,8755
2316E,8316A,8316AL,2616
2332,2364
8041,8048
2608,8308
8355
Bipolar PROMs
4-76
A
A
B
B
C
D
E
F
1702A/4702A/8702A Family
2708/8708/2704 Family
2716,2758,8741,8748,8755
CUSTOMER EPROM
ORDER FORM
A
For Intel Use Only
Company
Phone #
S#
Company Contact
Date
P.O. #
Intel Device PIN
STD
APP
Date
All custom MOS EPROM orders must be submitted on this form. Programming information
should be sent per the formats described in the Programming Instruction section of the Intel
Data Catalog. Additional forms are available from Intel.
o
1 0
MARKING
The marking will consist of the Intel Logo, the product and package type (B1702A), the
4·digit Intel pattern number (WWWW), an internal manufacturing traceability code (XXYY),
and the customer part number (Z .... Z). The customer part number is limited to a maximum
of 9 digits or spaces.
B1702A
XXyy
D
WWWW
Z.... Z
1702A MARKING
EXAMPLE
FLOPPY DISK
Programming information may be sent on Intel Microcomputer Development System Floppy Disk. When using this input
medium the floppy disk file name should be indicated in the Customer Part Number Section below. The type of floppy disk
sent should also be indicated by checking one of the appropriate boxes:
o Single Density
0 Double Density
CUSTOMER PART NUMBER
Customer PIN
(Please Fill-In)
1.
2.
3.
I
L I
I
I
I
I
I
I
I
Floppy Disk File Name
(Please Fill-In)
1.
I
3.
I
4.
I
5.
I
I
6.
I
I
7.
I
I
8.
I
I
I
I
I
I
I
I
I
I
1.
I
I
2.
I
I
I
3.
I
I
4.
I
I
I
I
5.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
5.
I
I
6.
I
I
I
I
I
I
I
7.
I
I
8.
I
I
I
I
6.
I
I
I
I
7.
I
I
I
I
11.
I
I
14.
I
I
I
I
I
17.
I
I
I
I
I
I
I
I
I
14.
I
I
I
I
15.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
I
I
I
I
I
I
I
I
18.
I
I
I
19.
I
!
I
I
I
I
10.
I
I
11.
I
I
I
I
I
I
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!
13.
I
I
14.
I
I
15.
I
I
I
I
I
16.
I
I
I
I
I
I
I
I
I
I
I
I
17.
I
I
I
I
4-77
I
12.
I
I
I
I
I
I
8.
I
I
16.
17.
I
I
I
I
I
I
I
18.
I
13.
I
I
I
12.
15.
16.
11.
I
I
I
I
I
I
13.
I
9.
10.
I
I
I
9.
10.
19.
I
4.
I
9.
12.
I
2.
I
Intel Pattern Number
(Please Do Not Use)
I
18.
I
I
19.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2316E
2616
2316A/8316A/8316AL
2332
CUSTOMER 16K, 32K, and 64K
ORDER FORM
B
2364
For I nttol Use Only
Company ________________________________ Phone#________________
S# ________________
Company Contact __~______________________ Date ________________
P.O.
# _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___ Intel PIN & Pkg _________~
STD ________________
APP __________________
Date ________________
A custom 16K/32K/64K ROM order must be submitted on this form. Programming information should be sent per the formats described in the Programming Instruction section of
the Intel Data Catalog. Additional forms are available from Intel.
MARKING
The marking will consist of the Intel Logo, the product and package type (P2316E), the
4-digit Intel pattern number (WWWW), a date code (XXYY), and the customer part number
(Z .... Z). The customer part number is limited to a maximum of 9 digits or spaces.
00
WWWW
2 .... 2
P2316E
XXVV
When authorized by the customer to ship 2616 PROMs against a 2316E order, the PROMs
are marked with the dual part number 2616/2316E.
P2316E MARKING EXAMPLE
IMPORTANT MASK OPTION SPECIFICATION
The 2316E, 8316A, and 8316AL chip select inputs are mask programmable and must be specified by the user. The chip
select logic levels must be specified with one of the below Chip Numbers. The Chip Number will be coded in terms of positive
logic where a logic "1" is a high level input. It should be noted that Chip Number 4 for the 2316E is compatible to Intel's
2716 EPROM and 2616 PROM.
Chip Number
CS3
CS2
CS1
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
2
3
4
5
6
7
1
1
1
1
FLOPPY DISK
Programming information may be sent on Intel Microcomputer Development System Floppy Disk. When using this input
medium the floppy disk file name should be indicated in the Customer Part Number Section below. The type of floppy disk
sent should also be indicated by checking one of the appropriate boxes:
o Single Density
0 Double Density
CUSTOMER PART NUMBER
16K ROM
Chip Number
(Please Fill-In)
Customer PIN
(Please Fill-In)
1.
I
I
I
2.
I
I
I
3.
I
I
I
I
I
I
I
5.
I
I
6.
!
I
7.
I
I
I
8.
I
I
I
4.
I
I
I
I
I
I
I
I
I
I
!
Intel Pattern Number
(Please Do Not Use)
Floppy Disk File Name
(Please Fill-In)
1. LJ
1.
2. LJ
2.
3. LJ
3.
I
I
I
I
I
I
I
I
I
I
I
1.
I
I
I
I
I
I
I
2.
I
I
I
I
3.
I
I
I
I
I
I
4.
I
I
I
I
5.
I
I
I
I
6.
I
I
I
I
I
I
4. LJ
4.
I
I
I
I
I
I
5. LJ
5.
I
I
I
I
6. LJ
6.
I
I
I
I
7. LJ
7.
I
I
I
I
8. LJ
8.
I
I
4-78
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
7.
I
I
I
I
8.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
8041,8048
CUSTOMER 8041, 8048 ROM
ORDER FORM
C
For Intel Use Only
Company _____________________________ Phone#_________________
Company Contact
Date ____________.____________
P.O. #
Package Type:
s# __________
STD _ _ _ _ _ _ ___
D Plastic
D Cerdip
APP _ _ _ _ _ _ __
Date
All custom 8041 and 8048 orders be submitted on this form. Programming information
should be sent per the formats described in the Programming Instruction section of the Intel
Data Catalog. Additional forms are available from Intel.
--------------------------------------------------------------~------------------~
MARKING
All devices will be marked as shown at the right figure. The marking will consist of the Intel
Logo, the product and package type (P8048). the 4-digit Intel pattern number (WWWW), a
date code (XXYY), and the customer part number (Z .... Z). The customer part number is
limited to a maximum of 9 digits or spaces.
wwww
DO P8048
Z.... Z
XXV V
P8048 MARKING EXAMPLE
FLOPPY DISK
Programming information may be sent on Intel Microcomputer Development System Floppy Disk. When using this input
medium the floppy disk file name should be indicated in the Customer Part Number Section below. The type of floppy disk
sent should also be indicated by checking one of the appropriate boxes:
o Single Density
o Double Density
CUSTOMER PART NUMBER
1.
Ll
1
I
I
I
2.
1 I
I
I
I
1 I
3.
1
1
I
1
I
I
1 I
4.
1 I
I
I
I
I
1 I
I
Intel Pattern Number
(Please Do Not Use)
Floppy Disk File Name
(Please Fill-In)
Customer PIN
(Please Fill-In)
~I~i~I~I_~_LI_LI_LI~I~
1.
I
I
I
I
I L-J
2.
I
I
I
I . 1. 1-LI-,--I-,--I-LI--'
2.
I
I
I
1 I
I
I
I
3.
LLI
I
I
1 I
I
I
I
3.
I
I
I
1 I
I
I
4.
I
I
I
I
I
I
I
4.
l
I
I
I
I
I
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I
I
1
1 I
I
I
I
I
I
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
1-1
I
I
1
7.
I
I
I
I
1
I
I
I
I
8.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
I
I
LL-LIIIIIII
I
I
6.
I
7.
1 I
1
I
I
1 I
I
7.
I
8.
1 I
I
1 I
I
I
8.
LLI
9.
I
I
9.
I
1 1 I
10.
I
1 I
11.
1 I
LJ
I
I
I
I
III
I
i
I
I
1 I
I
I
I
I
I
I
1 I
I
I
I
I
I
10.
I
I
I
I
I
I
1 I
!
I
!
I
11.
1 I
1 I
I
1 1 I
I
I
1 I
I
I
10.
1 I
I
1
11.
I
1 1
12.
II!
1 1
13.
1 I
I
I
I
12.
I
I
I
1 1 1 I
I
1 I
I
1
13.
I
I
I
I
I
I
1 I
I
I-.J
14.
LJ
I
I
1 1 I
I
I
I
I
I~-.-J
15.
I
I
1 I
1 I
I
I
I
16.
LL.-LI-,---,---,---,---,--1-,--I-'----'
16.
1 I
I
I
I
!
I
I
I
I
I
I
I
12.
I
13.
1 I
14.
I
I
15.
LL.L I
1 I
I
I
I
17.
I
I
I
I
I
I
I
l--l
17.
1 I
I
I
I
I
I
18.
1 I
I
I
I
I
1 1 I
I
18.
I
I
I
1
1
I
1
19.
I
I
I
I
I
I
1 I
I
I
I
1 1 I
I
20.
I
1 1
I
1 1 I
I
I
I
I
19.
20.
I
I
I
I
I
I
I
I
I
I
I
1
14.
I
I
I
I
15.
I
I
I
I
I
I
I
I
I
16.
I
1 I
I
I
I
I
I~---L-J
1
17.
1 I
I
1 1 I
I
I
I
I
18.
I
I
I
I
I
I
I
I
I
I
20.
I
I
I
I
I
I
I
I
I
1
1 I
L--'--'--I-'--I-'--I-'--I-'--I~I~I~I~
4-79
9.
I
I
I
I
5.
I
I
I
I
I
I
I
I
1 I
6.
1 1 I
I
1 I
I
I
5.
I
I
I
I
1 1 I
I
1 I
1 I
I
I
I
1 I
1 I
I
I
1 I
I
5.
6.
I
I
1.
2608
2308/8308
CUSTOMER 8K ROM
ORDER FORM
D
For Intel Use Only
Company ________________________
Company Contact __________________
P.O.
# _____________________
Phone#_________________
S# ________________
Date __________________
STD _____________
APP ______________
Intel PIN & Pkg _ _ _ _ _ _ _ __
Date ____________________
All custom 8K ROM orders must be submitted on this form. Programming information
should be sent per the formats designated on this order form. Additional forms are available
from Intel.
MARKING
The marking will consist of the Intel logo, the product type (C8308). the 4-digit Intel pattern number (WWWW). a date code (XXYY). and a maximum 9-digit number (Z .... Z) which
is' specified by the user. The 9-digit number may be a part number or the chip number.
When authorized by the customer to ship 2608 PROMs against a 2308/8308 order, the
o
C8308 WWWW
o
XXV V
ZZZZZZZZZ
1
C8308 MARKING EXAMPLE
PROMs are marked with the dual part number 2608/2308 or 2608/8308.
IMPORTANT MASK OPTION SPECIFICATION
The 2308/8308 CS 2 chip select input is mask programmable and must be specified by the user. The chip select logic level
must be specified with one of the below Chip Numbers. The Chip Number will be coded in terms of positive logic where a
"1" is a high level input. It should be noted that Chip Number 0 for the 2308/8308 is compatible to Intel's 2708 EPROM and
2608 PROM.
CS,
CS2
Chip Number
(non-programmable)
(programmable)
o
o
o
o
1
1
FLOPPY DISK
Programming information may be sent on Intel Microcomputer Development System Floppy Disk. When using this input
medium the floppy disk file name should be indicated in the Customer Part Number Section below. The type of floppy disk
sent should also be indicated by checking one of the appropriate boxes:
o Single Density
0 Double Density
CUSTOMER PART NUMBER
Customer PIN
(Please Fill-I n)
Chip Number
(Please Fill-In)
Floppy Disk File Name
(Please Fill-In)
1.
I
I
I
I
I
I
I
I
I
1. U
1.
I
I
I
2.
I
I
I
I
I
I
I
I
I
2. U
2.
I
I
I
3.
I
I
I
I
I
I
I
3. U
3.
4.
I
I
I
I
I
I
4. U
4.
5.
I
I
5. U
5.
I
6.
I
I
I
I
I
I
6.
I
I
I
I
7.
I
I
I
I
I
8.
I
I
I
I
I
I
9.
I
I
I
I
I
I
I
I
I
10.
I
I
11.
I
I
12.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
7. U
7.
I
I
8. U
8.
I
I
9. U
9.
10. U
10.
I
I
I
I
I
11. U
11.
I
I
I
I
I
12. L.J
12.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
4-80
I
1.
I I
I
I
I
I
I
I
I
I
2.
I
I
I
I
I
I
I
I
I
I
3.
I
I
I
I
I
I
I
I
I
4.
I
I
I
I
I
I
I
I
I
5.
I
I
I
I
I
I
I
I
6.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
7.
I
I
8.
I
I
9.
I
I
I
I
10.
I
I
I
I
I
11.
I
I
I
I
I
12.
I
I
I
I
I
I
I
6. U
I
I
I ntel Pattern Number
(Please Do Not Use)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CUSTOMER 8355 ROM
ORDER FORM
E
8355
For Intel Use Onlv
CompanY ____________________________ Phone#_______________________
Company Contact
Date _________________________
P.O. #
Package Type: 0 Plastic
o
Cerdip
s#_________________
STD _________________
APP _________________
Date ____________________
!I. II custom 8355 orders must be submitted on this form. Programming information should
)e sent per the formats described in the Programming Instruction section of the Intel Data
~atalog. Additional forms are available from Intel.
MARKING
All devices will be marked as shown at the right figure. The marking will consist of the Intel
Logo, the product and package type (P83551. the 4·digit Intel pattern number (WWWW), a
date code (XXYYl. and the customer part number (Z .... Z). The customer part number is
limited to a maximum of 9 digits or spaces.
o
wwww
OP8355
XXV V
Z .•.. Z
1
P8355 MARKING EXAMPLE
FLOPPY DISK
Programming information may be sent on Intel Microcomputer Development System Floppy Disk. When using this input
medium the floppy disk file name should be indicated in the Customer Part Number Section below. The type of floppy disk
sent should also be indicated by checking one of the appropriate boxes:
o Single Density
0 Double Density
CUSTOMER PART NUMBER
Intel Pattern Number
(Please Do Not Use)
Floppy Disk File Name
(Please Fill-In)
Customer PIN
(Please Fill-In)
1.
1.
1.
2.
2.
2.
3.
3.
3.
4.
4.
4.
5.
5.
5.
6.
6.
6.
7.
7.
7.
8.
8.
8.
9.
9.
9.
10.
10.
10.
11.
11.
11.
I
I
12.
I
13.
12.
I
I
I
I
14.
15.
15.
15.
16.
16.
16.
17.
17.
17.
18.
18.
19.
20.
I
I
I
I
I
I
I
13.
I
14.
I
I
12.
13.
14.
I
I
I
I
18.
19.
19.
20.
20.
4-81
I
I
I
I
I
I
I
CUSTOMER BIPOLAR PROM
ORDER FORM
F
36AAPROM
For Infel Use Only
Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Phone.#_ _ _ _ _ _ _ __
Company Contact
Date _ _ _ _ _ _ _ _ __
P.O. #
Intel Device PIN _ _ _ _ __
S#_ _ _ _ _ _ _ _ ___
STD _ _ _ _ _ _ _ __
APP _ _ _ _ _ _ _ __
Date _ _ _ _ _ _ _ _ __
All custom bipolar PROM orders must be submitted on this form. Programming information should be sent per the formats described in the Programming Instruction section of the
Intel Data Catalog. Additional forms are available from Intel.
IMPORTANT HEX AND INTELlEC HEX FORMAT INFORMATION
A word field must be 8 bits in the hex format. Consequently for N words by 4-bit devices such as the 3605, it is important that you
indicate by checking the box below whether the submitted tape or card deck for programming is right or left justified.
.
o
o
Right Justified
left Justified
MARKING
All devices will be marked as shown at the right figure. The marking will consist of the Intel
logo, the product and package type (D36AAl. the 4-digit Intel pattern number (WWWW), a
date code (XXYY), and the customer part number (Z"" Z). The customer part number is
limited to a maximum of 9 digits or spaces.
o D36AA
XXyy
OZZZZZZZZZWWWW
1
D36AA MARKING EXAMPLE
FLOPPY DISK
Programming information may be sent on Intel Microcomputer Development System Floppy Disk. When using this input
medium the floppy disk file name should be indicated in the Customer Part Number Section below. The type of floppy disk
sent should also be indicated by checking one of the appropriate boxes:
o
o Single Density
Double Density
CUSTOMER PART NUMBER
Intel Pattern Number
(Please Do Not Use)
Floppy Disk File Name
(Please Fill-In)
Customer PIN
(Please Fill-In)
1.
1
1.
~I~I~~~~~~I~I~~
2.
~I~I~~~~~~~~I---,I
2.
3.
3.
IL-LI-L-L--I-I--1-1--I---I---L-l..-'
3.
4.
4.
4.
5.
5.
5.
6.
6.
7.
7.
1.
2.
1
6.
1 1 1 1 1
7.
8.
1
9.
1
1
1
1
8.
9.
1
10.
1
10.
10.
11.
<--I~I~~~~~~~~---'
11.
IL-LI-L-L-L--I---LI--LI--L-l..-'
12.
LI-LI--I---I-I--I-I--L-l..-l..-l..-l..-'
12.
1
13.
1
I
1
1
1
I
14.
1
15.
I~~I~--'---'-~~-'-~~---'
1
1
13.
1
14.
1
13.
14.
15.
15.
4-82
~I~I~~~~~~I~I~---,
9.
1
1
11.
12.
8.
1
1
1
I
IL-LI--'---L--'---L--I--I---L--L-'
II.
MOS EPROMs
A. Erasure Procedure
As stated in the EPROM related data sheets, the recommended erasure procedure to use with EPROMs is to illuminate the
window with a UV lamp which has a wavelength of 2537 Angstroms (A). The data sheets specify a distance of 1 inch and
erase times of 10-45 minutes, depending on the type of device and UV lamp. Actually, the amount of time required to erase
a device can be concisely stated in terms of the amount of UV energy incident to the window, expressed in Watt·seconds per
square centimeter (W·sec/cm 2 ). Table III lists the required integrated dosgae (UV intensity X exposure time) for the EPROMs
currently in production by Intel.
Table III. Required Erase Energy for Device Types
Device Type
2537 A. Erase Energy
6 W·sec/cm 2
1702A/4702A
270818708
15 W·sec/cm 2
2758, 2716
15 W·sec/cm 2
8741,8748
15 W·sec/cm 2
8755
15 W·sec/cm 2
The erase energy expressed in Table III includes a guardband to ensure complete erasure of all bits. It is not sufficient to
monitor "first bit" erasure to determine erasure time, as some other bits in the array may not be erased.
A 1. UV Sources
There are several models of UV lamps that can be used to erase EPROMs (see Table IV). The model numbers in the table refer
to lamps manufactured by Ultra Violet Products of San Gabriel, California. In addition, there are several other manufacturers,
including Data 1/0 (Issaquah, Wash.), PROLOG (Monterey, Calif.). Prometrics (Chicago, 111.), and Turner Designs (Mt. View,
Calif.). The individual manufacturers should be consulted for detailed product descriptions. Also shown in the table are
typical erase times for various combinations of Intel PROMs and lamp intensities.
Table IV.
Minimum Erase Time for Indicated Dosage
Without a Filter Over the Bulb
Model
Power Rating
6 W-sec
1702A,
4702A
15 W-sec
2708,8708,8755
2758,2716,8748,
8741
R-52
13000pW/cm 2
7.7 min
19.2 min
S-52
12000 pW Icm 2
8.3 min
20.7 min
S-68
12000 pW/cm 2
8.3 min
20.7 min
UVS-54
5700 pW/cm 2
17.5 min
43.8 min
UVS·11
5500 pW/cm 2
18.2 min
45.6 min
According to the manufacturers, the output of the UV lamp bulbs decrease with age. The output of the lamp should be
verified periodically to ensure that adequate intensities are maintained. If this is not done, bits may be partially erased which
will interfere with later programming and/or operation at high temperature.
For lamps other than those listed, the erase time can be determined by using a UV intensity meter, such as the Ultra Violet
Products Model J·225. When a meter is used, the intensity should be measured at the same position (distance from the lamp)
as the EPROMs to be erased. This will require careful positioning to insure that the sensor will receive the same amount of
UV light that the window of the EPROM will receive.
The sensors used with most UV intensity meters show reduced output with constant exposure to UV light. Therefore, they
should not be permanently placed inside the erasure enclosure, they should only be used for periodic measurements.
4·83
B.
1702A/1702AL Family Programming
The 1702A/1702AL is erased by exposure to high intensity short wave ultraviolet light at a wavelength of 2537A. The recommended integrated dose (i.e., UV intensity X exposure time) is 6 W-sec/cm 2. An example of an ultraviolet source which can
erase the 1702A/1702AL in 10 to 20 minutes is the Model S52 short wave ultraviolet lamp. The lamp should be used without
short wave filters and the PROM should be placed within 1 inch away from the lamp tubes.
Initially, all 2048 bits of the PROM are in the "0" state (output low). Information is introduced by selectively programming
"1 "s (output high) in the proper bit locations.
I
Word address selection is done by the same decoding circuitry used in the READ mode. All 8 address bits must be in the
binary complement state when pulsed Vee and V GG move to their negative levels. The addresses must be held in their binary
complement state for a minimum of 25 f.!.sec after Voo and VGG have moved to their negative levels. The addresses must then
make the transition to their true state a minimum of 10 f.!.sec before the program pulse is applied. The addresses should be
programmed in the sequence 0 through 255 for a minimum of 32 times. The eight output terminals are used as data inputs to
determine the information pattern in the 8 bits of each word. A low data input level (-48V) will program a "1" and a high
data input level (ground) will leave a "0". All 8 bits of one word are programmed simultaneously by setting the desired bit
information patterns on the data input terminals.
During the programming, VGG, Voo and the Program Pulse are pulsed signals. See page 4·12 for required pin connections
during programming.
1702A, 1702AL
D.C. and Operating Characteristics for Programming Operation
TA ; 25°C, Vee; ov, VB B ; + 12V ±10%, CS; OV unless otherwise noted
Symbol
Test
Min.
Typ.
Max.
Unit
Conditions
ILl1P
Address and Data Input Load Current
10
mA
VIN ; -48V
ILl2P
Program .and VGG Load Current
10
mA
VIN; -48V
IBB[l]
VBS Supply Load Current
loop[2]
Peak 100 Supply Load Current
VIHP
Input High Voltage
10
mA
200
mA
0.3
V
VIL1P
Pulsed Data Input Low Voltage
-46
-48
V
VIL2P
Address Input Low Voltage
-40
-48
V
VIL3P
Pulsed Input Low Voo and
Program Vo Itage
-46
-48
V
VIL4P
Pulsed Input Low VGG Voltage
-35
-40
V
Voo ; VPROG ; -48V,
VGG ; -35V
Notes: 1. The VSS supply must be limited to 100mA max. current to prevent damage to the device.
2. lOOp flows only during VOO, VGG on time. lOOp should not be allowed to exceed 300mA for greater than 1 OOl'sec. Average
power supply current lOOp is typically 40mA at 20% duty cycle.
4·84
·ROM/PROM PROGRAMMING INSTRUCTIONS
1702A, 1702AL
A.C. Characteristics for Programming Operation
TAMBIENT
= 25°C. Vcc = OV. VBB = + 12V ±1 0%. CS = OV unless otherwise noted
Symbol
Min.
Test
Typ.
Duty Cycle (VDD. VGG)
tq,PW
Program Pulse Width
Max.
Unit
20
%
3
ms
2
Conditions
VGG
VDD
tDW
Data Set·Up Time
25
/.Is
tDH
Data Hold Time
10
/.IS
tvw
VDD. VGG Set-Up
100
tVD
VDD. VGG Hold
10
tACW
Address Complement Set-Up
25
/.Is
tACH
Address Complement Hold
25
/.Is
tATW
Address True Set-Up
10
/.Is
tATH
Address True Hold
10
/.Is
= -35V.
= VPROG = -48V
/.Is
100
/.Is
PROGRAM WAVEFORMS
Conditions of Test:
Input pulse rise and fall times
CS = OV
:s 11.1sec
----i tACH : - ~---tACW-----+i'i i i
I
o
ADDRESS
I
:
~--------------~'
BINARY COMPLEMENT
ADDRESS OF WORD
TO BE PROGRAMMED
BINARY ADDRESS
OF WORD TO BE
PROGRAMMED
-40 to -48
I
I
I'
I
O----------------------~
--:
-46 to-48
~tATW
~---+--
I
I
I
I
I
I
I
I
I
I
I
I
PULSED Voo
POWER SUPPLY
---rtvoi
I
I
I
I
I
I
if
0------------------------1\ !
row~~:~,,~
I{
I
I
-35to-40
I
I
r-tvw-l
O--------.~I
PROGRAMMING
PULSE
I
I
I
I
I
III
I
~
:tATH-----1
r-tow-i
}
I
I
I
I
-'--i tOH:-I
DATA STABLE
TIME
-46 to
4-85
i
I
I
r--t100ms.
The width of the program pulse is from 0.1 to 1 ms. The number of loops (N) is from a minimum of 100 (tpw = 1 ms) to
greater than 1000 (tpw = 0.1 ms). There must be N succ~ssive loops throuhg all 1024 addresses. It is not permitted to apply N
program pulses to an address and then change to the next address to be programmed. Caution should be observed regarding
the end of a program sequence. The CS/WE falling edge transition must occur before the first address transition when chang·
ing from a program to a read cycle. The program pin should also be pulled down to VILP with an active instead of a passive
device. This pin will source a small amount of current (I ILL! when CS/WE is at VIHW (12V) and the program pulse is at VILP.
Programming Examples (Using N x tpw ;;> 100 ms)
Example 1:
All 8096 bits are to be programmed with a 0.5 ms program pulse width.
The minimum number of program loops is 200. One program loop consists of words
Example 2:
a to 1023.
Words a to 100 and 500 to 600 are to be programmed. All other bits are "don't care". The program pulse
width is 0.75 ms.
The minimum number of program loops is 133. One program loop consists of words
entered into the "don't care" bits should be all 1'So
Example 3:
a to
1023. The data
Same requirements as example 2, but the PROM is now to be updated to include data for words 750 to 770.
The minimum number of program loops is 133. One program loop consists of words a to 1023. The data
entered into the "don't care" bits should be all 1 'so Addresses a to 100 and 500 to 600 must be re·programmed with their original data pattern.
2704, 2708 Family
PROGRAM CHARACTERISTICS
TA = 25°C, Vee = 5V ±5%, VDD = +12V ±5%, Vss = ~5V±5%, Vss = OV, Unless Otherwise Noted.
D.C. Programming Characteristics
Symbol
Parameter
III
Address and CS/WE Input Sink Current
IIPL
Program Pulse Source Current
IIPH
Program Pulse Sink Current
IDD
ICC
IBS
VIL
VIH
Min.
TVp.
Max.
Units
10
~A
3
rnA
Test Conditions
VIN
= 5.25V
20
rnA
2708.2704
50
65
rnA
2708L
21
28
rnA
Worst Case Supply
2708.2704
6
10
rnA
Currents(1) :
2708L
2
4
rnA
All Inputs High
2708.2704
30
45
rnA
CSIWE
2708L
10
14
rnA
VSS
0.65
V
2708.2704
3.0
VCC+ 1
V
2708L
2.2
VCC+ 1
V
VOD Supply Current
V CC Supply Current
Vee Supply Current
Input Low Level (except Program)
= 5V;TA = O·C
Input High Level For all Addresses
and Data
VIHW
CS/WE Input High Level
11.4
12.6
V
Referenced to V55
VIHP
Program Pulse High Level
25
27
V
Referenced to V SS
VILP
Program Pulse Low Level
VSS
1
V
VIHP- VILP25Vrnin.
Note 1. IBS for th·e 2708L is specified in the programmed state and is 18 mA maximum in the unprogrammed state.
4-86
A.C. Programming Characteristics
Min.
Typ.
Max.
Units
Symbol
Parameter
tAS
Address Setup Time
10
IlS
tcss
CSIWE S~tup Time
10
IlS
~os
Data Setup Time
10
IlS
tAH
Address Hold Time
1
IlS
tCH
CSIWE Hold Time
.5
IlS
tOH
Data Hold Time
1
tOF
Chip Deselect to Output Float Delay
0
tOPR
Progfam To Read Delay
tpw
Program Pulse Width
tpR
tpF
Ils
120
ns
10
Ils
.1
1.0
ms
Program Pulse Rise Time
.5
2.0
IlS
Program Pulse Fall Time
.5
2.0
IlS
NOTE: Intel. standard product warrantY applies onlv to devices programmed to specifications described herein.
2704, 2708 Family
Programming Waveforms
V'HW
1 + - - - - - - - - - - 1 OF N PROGRAM LOOPS--------~~j.-READ
(AFTER N
PROG •.LOOPS)
CSIWE
VIL
NOTE 1
V OH
ADDRESS
ADDRESS 0
VOL
\+--
VOH
DATA
OATA
our
INVALID
t Acc 460ns MAX
DATA OUT
VALID
VOL
t oH {11-
j . - - - - - f - . O P R (10 MAX)
(.1mSMIN)
tM
if.iimsMAX}---+
V'HP
PROGRAM
PULSE
VOL-----"'I
NOTE 1. THE CSlWE TRANSITION MUST OCCUR AFTER THE PROGRAM PULSE TRANSITION
AND BEFORE THE ADDRESS TRANSITION.
NOTE 2. NUMBERS IN ( ) INDICATE MINIMUM TIMING IN.S UNLESS OTHERWISE SPECIFIED.
4-87
D. 2716 And 2758 Programming
Initally, and after each erasure, all bits of the 2716/2758 are in the "1" state. Information is introduced by selectively programming "0" into the desired bit locations. A programmed "0" can only be changed to a "1" by UV erasure.
The 2716/2758 is programmed by applying a 50 ms, TTL programming pulse to the CE/PGM pin with the OE input high and
the Vpp supply at 25V ±lV. Any location may be programmed at any time - either individually, sequentially, or randomly.
The programming time for a single bit is only 50 ms and for all bits is approximately 100 and 50 seconds for the 2716 and
2758 respectively. The detailed programming specifications and timing waveforms are given in the following tables and
figures.
CAUTION:
The Vee and Vpp supplied must be sequenced on' and off such that Vee is applied simultaneously or before
Vpp and removed simultaneously or after Vpp to prevent damage to the 2716/2758. The maximum allowable
voltage during programming which may be applied to the Vpp with respect to ground is +26V. Care must be
taken when switching the Vpp supply to prevent overshoot exceeding the 26-volt maximum specification. For
convenience in programming, the 2716/2758 may be verified with the Vpp supply at 25V ±lV. During normal
read operation, however, Vpp must be at Vee.
2716 AND 2758 PROGRAM CHARACTERISTICS(1)
TA = 25°C ±5°C, Vee[21 = 5V ±5%, Vpp[2.3l = 25V ±lV
D.C. Programming Characteristics
Parameter
Symbol
III
Input Current (for Any Input)
IpP1
Vpp Supply Current
IpP2
V PP Supply Current During
Programming Pulse
lee
Vec Supply Current
VIL
Input Low Level
VIH
Input High Level
Min.
Typ.
Max.
Units
Test Conditions
10
IlA
VIN = 5.25V/0.45
5'
mA
CE/PGM = VIL
30
mA
CE/PGM = VIH
100
mA
-0.1
0.8
V
2.0
Vce+1
V
Max.
Units
A.C. Programming Characteristics
Symbol
Parameter
Min.
Typ.
tAS
Address Setup Time
2
Ils
tOES
OE Setup Time
2
Ils
tos
Data Setup TIme
2
Ils
tAH
Address Hold Time
2
Ils
Ils
tOEH
OE Hold Time
2
tOH
Data Hold Time
2
tOF
Output Enable to Output Float Delay
0
Ils
120
ns
CE/PGM =VIL
120
ns
CE/PGM = VIL
55
tns
tOE
Output Enable to Output Delay
tpw
Program Pulse Width
tPRT
Program Pulse Rise Time
5
ns
tpFT
Program Pulse Fall Time
5
ns
45
50
NOTES: 1. Intel's standard product warranty applies only to devices programmed to specifications described herein.
2. Vee must be applied simultaneously or before Vpp and removed simultaneously or after VPP. The 2716/2758 must not be
inserted into or removed from a board with Vpp at 25 ±1 V to prevent damage to the device.
3. The maximum allowable voltage which may be applied to the Vpp pin during programming is +26V. Care must be taken when
switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification.
4-88
A.C. Conditions of Test:
Input Pulse Levels . . . . . . . . . . . . . . . . . . . 0.8V to 2.2V
Input Timing Reference Level . . . . . . . . . . . . lV and 2V
Output Timing Reference Level. . . . . . . .. 0.8V and 2V
Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V ±lV
Input Rise and Fall Times (10% to 90%) ......... 20 ns
PROGRAMMING WAVEFORMS
Vpp = 25V ±1 V, Vee = 5V ±5%
PROGRAM
VERIFY
PROGRAM
.)\
ADDRESSES
-:~IS-
'OF
IO.12MAXI~
I
DATA IN
STABLE
ADO. N
HIGH Z
DATA OUT
VALID
ADD. N
I
-
'DE
(Q,12MAX)-
\
/
_'os
(45 ms)
\
/
r-
'K
DATA IN
STABLE
ADD. N+m
'OF
~
r-10.12 MAX)
/
-'f,~-
'PW
121
t----'~iIS _
ADDRESS NTm
'AH
121
~
DATA
'~
ADDRESS N
_'~iIH~
a/PGM
tpRT _
I-- -
-'PFT
NOTE. ALL TIMES SHOWN IN PARENTHESES ARE MINIMUM TIMES AND ARE /.I5fC UNLESS OTHERWISE NOTED
III. BIPOLAR PROM PROGRAMMING
All Intel bipolar PROMs are programmed with the algorithm described below. This algorithm was developed specifically to
program the 3602A/3622A, 3604A/3624A, 3605/3625, and 3608/3628. The algorithm described in this section must be
used on the aforementioned PROMs to insure properly and reliably programmed fuses.
Initially, all bits are in a logic 1 (high) state. To program a bit to a logic 0 (low) state, it is necessary to force 5 mA into the
output to be programmed. A series of program pulses must also be applied to the Vee power supply and to anyone of the
logically low true chip select (CS) inputs. The logic level of the other chip selects, in the case of PROMs with mUltiple chip
selects, should be such that the PROM is selected during verification.
Program pulses are applied to all outputs of a word in a cycle time. The program pulses are multiplexed during a cycle time to
each output of the word to be programmed. If desired, a N word by 8-bit PROM may have its words programmed in two
separate groups - the four lower order bits (01 to 04) and the four higher order bits (05 to aS). The operation in this manner is the same as for a N word by 4-bit PROM. For fastest programming time, it is preferred that all eight outputs be,programmed at the same time.
The programming specifications are given in Table V and the programming waveforms are shown in Figure 1. The program·
ming procedure (described with nominal specifications) is as follows:
4-89
I
1. A 5 mA current must be forced into the output to be programmed by a current source. The current source must be
clamped to Vee by a silicon diode. All the other outputs must be floating until it is their turn for programming. The
Vee power supply and the chip select (CS) input is pulsed as shown in Figures 1 and 2. The width of Vee is linearly
increased from 0.2 f.1s to 8 f.1s according to the ramp time shown in Figure 3. The total ramp time for a group of four
outputs is 180 ms and 360 ms for a group of eight outputs.
The Vee program pulses are multiplexed during a cycle time to the outputs of the word to be programmed. The cycle
time (teycl between the Vee program pulses to the same output will increase as the Vee program pulse width increases
from 0.2 f.1S to 8 f.1S. The time (to) between Vee pulses of two different outputs is constant at 1.8 f.1S.
2. All outputs must be continuously monitored for programming verification. This verification must occur after Vee has
been at 4.5V for 90% of to and prior to Vee rising to 12.5V. The program/verification cycles must still be applied
(with the pulse width still linearly increasing to a maximum of 8 f.1s) even though the output has been sensed as being
programmed. An additional 128 verifications (i.e., 128 program/verify cycles) on each output must be obtained to
insure a correctly programmed output. This additional 128 verification is a minimum number and must occur after all
the bits of the word are sensed as being programmed. Please refer to Figure 1 for the timing waveforms.
More than 128 program/verify cycles may be required to achieve the 128 verifications on each bit. The cycles should
still continue even if one bit fails, since the verifications are not required to be in consecutive sequence. After the 128
verifications have occurred for all bits, a final Vee and CS pulse at a width of 2.5 ms is simultaneously applied to all
outputs. Programming should cease if the 128 verifications are not achieved in 800 ms.
3. A 4 rTiA±50%-curre-riTmus'i:alsohefo;:ceelinto -CS3(pin 19) of the 3608/3628 family andinto-CS4-fpiniS)-ofthe·
3604A/3624A family during programming. If desired for commonality the 4 mA may also be forced into CS4 of the
3604/3624 family.
4. The 4 mA current into the chip select input may be easily accomplished by using a 1.2K resistor connected to a +15V
power supply. The voltage on the chip select input will be approximately 10V with the 1.2K resistor.
Table V. Programming Characteristics
TA = 25°C
Parameter
Symbol
Min.
Limits
Nom.
Max.
Units
VIH1
Vee Program Pulse Amplitude
12
12.5
13
V
VIH2
CS Program Pulse Amplitude
3
5
5.5
V
VIL1
Vee During Verify
4.25[1J
4.5
4.75
V
Conditions
VIH2
CS During Verify
0
0.2
0.4
V
tPW1
Vee Pulse Width at Beginning
of Pulse Train
160
200
240
ns
Measu red at 12V
tpW2
Vee Pulse Width at End of Pulse
Train
7.2
8
8.8
f.1S
Measured at 12V
Tess
Chip Select Setup Time
0
ns
Measured from 1.5V on rising edge
of CS to 5.0V on rising edge of Vee
TesH
Chip Select Hold Time
100
ns
Measured from 5.0V on falling edge
of Vee to 1.5V on falling edge of CS
J"I'l.
Vee Rise Time
300
400
500
ns
Measured from 5V to 12V on Vee
TF
Vee Fall Time
50
100
200
ns
Measured from 12V to 5V on Vee
Teye
Time Between Pulses to Same
Output
9
10
f.1S
Measured at 5V on Vee
Top
DC Program Time After Verifica·
tion Has Been Obtained
2.2
2.5
ms
Measured at 12V
To
Time Between Vee Pulses to
Successive Outputs
1.5
1.8
f.1S
Measured at 5V on Vee
TRAMP
Time During Which Vee
Pulse Width is Increased
Linearly from tpw1 to
tpW2
4 outputs
160
180
200
8 outputs
320
360
400
2
4
6
les
NOTE:
Current to CS3 of 3608/3628 or
to CS4 of 3604A/3624A
..
1. The minimum V I L1 for the 3604AL (low power)
IS
4.5V 4.90
2.8
ms
mA
CS3 or CS4 should be driven with a
1.2K resistor from a 15V power
supply
-tCYC
~..o - - - -(SEE
FIG. 2 FOR
~I.
DETAllS~
tD-j
L
128
tCyc:--->.-tI....c--top
I
r---(NOTE2)
~I
':::JULJLJLrLJLJLrLJL~
Vee
--..J
"'5V
nL,
r-1
"'lOV
OUTPUT 1
'--------l:~l-----
lZ
0.45V {MAXi
tPROGRAMMED
a (NOTE
1)
aUT:~::I~::~ -------~1t---------~~Z----------~~"'""'""~,~
aUTPUTN
)n
>~:~-~lJ1'--------llJl,
II
l~ ~~
O,45V{MAX)
L
LpROGRAMMED 0 (NOTE 1)
Figure 1. Programming Cycles.
NOTES
1. PROGRAM VERIFICATION MUST OCCUR AFTER Vee HAS BEEN AT 4.5V FOR 90% OF to AND PRIOR TO Vee RISING TO 12.5V.
THE PROGRAMMED OUTPUT IS «OA5V WHEN
'OV
/ \
OUTPUT 1
>5V - - - -
'"---------------{~__:,....----------..I
UNPROGRAMMED BIT
n
""lOV
OUTPUT 2
~5V
________________________
JI
\~------~2il~----------------------------------
J\
""lQV
OUTPUT N
>5V
----------------------------------------~2
Figure 2. Programming Cycle Details.
4-91
~--------------------------
(a) RAMP TIME IN PROGRAMMING 8 OUTPUTS
(b) RAMP TIME IN PROGRAMMING 4 OUTPUTS
tpw
J
J:
e-
O
!<
~
"
",.
;i'"
"~
z
u
u
>
0.2
0.2
100
200
300
400
500
600
700
800
100
PROGRAMMING ELAPSED TIME (ms)
Figure 3.
00
300
400
500
600
PROGR.AMMING ELAPSED TIME (ms)
Vee Pulse Width vs.
4·92
Programming Time.
700
800
5 Serial
Memory
SERIAL MEMORIES
Electrical Characteristics Over Temperature
NoT
Type
of
Bits
2401
2048
Dual 1024-Bit Dynamic
Recirculating
2405
1024
1024-Bit Dynamic
Recirculating
Description
2464 65,536 256 Recirculating Shift
Registers of 256 bits each
I
Input
Output
Levels
Min.
Max.
Power
Dissipation
Max.[l]
16
25kHz
1MHz
350mW
TTL
TTL
+5
5-3
16
25kHz· lMHz
350mW
TTL
TTL
+5
5-7
18
2.5MHz
TTL
TTL
-5,+12
5-7
No.
of
Pins
Data Rep. Rate
5-2
Clock
Levels Supplies[V]
Page
No.
inter
2401,2405
2048/1024·BIT DYNAMIC
RECIRCULATING SHIFT REGISTERS
• Single Supply Voltage -- +5 Volts
• Fully TTL Compatible --Inputs,
Outputs and Clock
• Single Phase Clock
• Low Clock Capacitance -- 7 pF
• Write/Recirculate and Chip
Select Logic Incorporated on Chip
• Standard Configurations-Dual 1024 Bit -- 2401
Single 1~4 Bit -- 2405
• Guaranteed 1 MHz Operation
with 100 pF Load, over
Temperature Range
• Low Power Dissipation-120 pw/bit typically at 1 MHz
The 2401/2405 are 2048/1024 bit dynamic recirculating shift registers. They are directly TTL compatible in all
respects: inputs, outputs, clock and a single +5 volt power supply.
Write/recirculate controls are provided to eliminate the need for external logic elements when recirculating data.
Two chip select inputs have been provided to allow easy selection of an individual package when outputs of several
devices have been "OR-tied". A separate internal "pullup" resistor (RLI is provided which can be externally connected to the output pin to achieve full signal swing.
This Intel shift register family is fabricated with N-channel silicon gate technology. This technology provides the
designer with high performance, easy to use MOS circuits. Only a single +5V power supply is needed and all devices
are directly TTL compatible, including clocks.
PIN CONFIGURATIONS
LOGIC DIAGRAM
Vee
INHRNALL
OUTl
Vee
OU1
Vee
Ru
IN,
R,
NC
IN,
OUl 2
IN
(OUT)
LOAD
RESISTOR
RL
~OUTPUT
WiR l
R"
WIR
NC
CS X
W/R 2
Cs x
IW/Rl
CSy
CLOCK
CSy
CLOCK
NC
NC
GND
N.C
Grm
NC
IN
W/R
NC
CSX
NOTE This represents one half of the 2401 The chip
select Inputs and clock InPLJt (Ire common,
CS y
• DASH LINES INDICATE NECESSARY EXTERNAL
PRINTED CIRCUIT BOARD CONNECTIONS FOR
PROPER QPERATlON OF THE 2405.
(SEE APPLICATION SECTION)
TRUTH TABLE
PIN SYMBOL
FUNCTION
PIN NAMES
IN
W/R
DATA INPUT
OUT
WRITEIRECIRCULATE
RL
CONTROL
CSx. CSy
CHIP SELECT INPUT
N.C.
CSx
WRITE MODE
H
L
L
RECIRCULATE
L
X
X
X
H
X
X
X
H
READ MODE
X
L
L
DATA OUTPUT
INTERNAL LOAD
RESISTOR
NO CONNECTION
H '" Logic High Level
L
;:0
Logic Low Level
x = Don't Care Condition
5-3
CSy
W/R
2401,2405
Absolute Maximum Ratings*
'COMMENT:
Ambient Temperature Under Bias: 0 0 C to 700 C
Stresses above those listed under" Absolute Maximum Rating" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
_65 0 C to + 1500 C
Storage Temperature:
Power Dissipation:
1W
Voltage on Any Pin with Respect
to Ground:
-0.5V to +7V
D. C. Characteristics
TA = OCto 70ce, Vee = +5V ±5%, unless otherwise specified.
LIMITS
TYP.l11
MAX.
UNITS
ILl
INPUT LEAKAGE
10
IJA
VIN = 5.25V
100
IJA
VO UT = 5.25V
70
80
mA
mA
TA = 250C} Vcc = 5.25V;
TA = O°C
80% DUTY
CYCLE
SYMBOL
PARAMETER
MIN.
TEST CONDITIONS
ILO
OUTPUT LEAKAGE
Icc
POWER SUPPLY CURRENT
VIH
INPUT HIGH LEVEL
VOLTAGE (ALL INPUTS)
2.2
5.25
V
VIL
INPUT LOW LEVEL
VOLTAGE (ALL INPUTS)
-0.3
0.65
V
VOH
OUTPUT HIGH LEVEL
VOLTAGE
2.4
Vcc
V
IOH =-lmA,
RL ~ 1.5K ± 5% ohms,
VOL
OUTPUT LOW LEVEL
VOLTAGE
0
0.45
V
IOL =5.0mA,
RL = 1.5K ± 5% ohms,
externall21
45
50
external
NOTES: 1. Typical values are at 2SoC and at nominal voltage.
2. The following was used to calculate 'Ol.
tOl
=
Vce (max.) - VOL (max,)
.
5.25 - 0.45
RL (min.)
+ ILl (TTLdevlcel = ~ +1.6
a
4.97mA.
Also note that the internal load resistor. R LI. has a value ranging from 500 ohms minimum to 2,200 ohms maximum. The internal
load resistor can be used when driving from ona 2401/2406 to another 2401/2406 or to other MOS inputs.
POWER SUPPLY CURRENT (ICC)
VS. DATA REP RATE
EFFECTIVE INPUT CHARACTERISTIC
60
_ _ DATAI.··o··
_ _ _ DATA'" "'"
50
CONSTA~T PULSE
--
WIDTH "'1Q,J:s
40
20
---
CONSTANT DUTY
..........CyCLE. 60%
/'
...........
~~ ~~ ~
1-"'''' '"
--- -
_
_
,.
./
.~
CONSTANT PULSE
WIDTH = 800 ns
10
0
1KHz
10KHz
100KHz
DATA REP RATE
lMHz
10MHz
200mv -
K
~
Vllll\llx DEVICE INPUT
SPEC
VOL ...."
WORST CASE
rrL OUTPUT
3
!--200mv
VIHmin
VOHmon
•
VIN (VOLTS)
2401,2405
A. C. Characteristics
TA
=ooc to 70°C, Vee =+sv ±S%,unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TYP.
MIN.
MAX. UNITS
FREQ. MAX.
MAX. DATA
REP. RATE
1
FREQ. MIN.
MIN. DATA
REP. RATE
tcppw
CLOCK PULSE
WIDTH
0.80
10
/.IS
tcpo
CLOCK PL!LSE
DELAY
0.20
0.20
1000
40
/.IS
SO
ns
tw
200
tH
HOLD TIME
1S0
tA
ACCESS TIME
FROM CLOCK
OR CHIP
SELECT
f
MHz
KHz
KHz
1
2S[1]
CLOCK RISE
AND FALL TIME
WRITE TIME
t, , t
TEST CONDITIONS
/.IS
TA
TA
= 2So C
= 70° C
TA
TA
= 2So C
= 70° C
ns
ns
2S0
ns
SOO
RL
= 1.SK ± S% ohm,
EXTERNAL
CL = 100pF
ONE TTL LOAD
NOTE: 1. 100 kHz in plastic (P) package.
Capacitance
T A = 25" C
LIMITS
SYMBOL
PARAMETER
C1N
DATA, W/R & CS INPUT
CAPACITANCE
CoUT
Ccp
MAX.
UNITS
4
7
pF
OUTPUT CAPACITANCE
10
14
pF
CLOCK CAPACITANCE
4
7
pF
Waveforms
BIT1
MIN.
TYP.
BITn+1
BIT 2
TEST CONDITIONS
ALL PINS AT AC
GROUND; 2S0mV
PEAK TO PEAK,
1 MHz
BIT n+2
t,
VIH
CLOCK
'.SV
VIL
DATA.
W/R.
CS
VIH
-----.~.~-----____
,.s_V~~______
VIL
A
OUTPUT IF CHIP {
CONTINUOUSLY
SELECTED
OUTPUT IF CS IS
PULSED (OUTPUT
IS HIGH WHEN
UNSELECTED)
~
1
","OUT
,.5V
'----"0-"O"'U"'T---'
CS
O,;,UT;.;.P,;,UT~_ _~
"0" OUT
5-5
2401,.2405
D. C. Characteristics
TEMPERATURE DEPENDENCE .oF
.oUTPUT L.oW LEVEL SINK CAPASILI1'y
,.
.~
r-.. t-- r-....
" r-.....
"
; "
•
1
.
I
~
-1~lo
J.
_
55
toPW = 800"5
Vee -6.2fiV
--r-- -r--.
.. . -
r-.
j
~
'-
'0
8
30
10
20
30
40
50
AMBIENT TEMPERATURE
60
(0
70
to--
36
-- r - I- jRSTCiL1M1,T- - --
•o
Vs. AMBIENT TEMPERATURE (OC)
f · 1 MHz
VOL "O.45V
~r-.. r-..
.. -'>So
'0
POWER SUPPLY CURRENT (Icc)
eo
80,
o
20
10
30
AMBIENT TEMPERATURE
C)
70
8'
'~CI
A. C. Characteristics
MliiliMUM DATA RATE AND MAXIMUM CLOCK DELAY
VS. AMBIENT TEMPERATURE FOR CERAMIC (e) PACKAGE
'....
100KHz
-- - - ----
.--
25 KHz
10KHz
P~
t3:~~
MINIMUM
DATA RATE
1 KHz
V
,,/
V
.,~,,/
100Hz
V
./'
'..
V
•
,.
20
.
30
r---~--~---~--~----'
40~,
aool-----1H----,-
100pl
~
t
§
aoo
,,/
, ms
V
MAXIMUM
,. ...
eo
50
I---~,---+------jl----I------l
~
!_
w
~
J ... 1----+---~~--_I__---+--__l2
iS
jCLOCK
DELAY I1. D'
V~
,,"/
10Hz
V
--
MINIMUM CL.oCK PULSE WIDTH AND
EFFECTIVE MAXIMUM DATA RATE AT 80%
DUTY CYCLE VS.
POWER SUPPLY V.oLTAGE (Vee)
7'
"
3 ~
200 1---+----1----1----+---14
lOOms
~
~
Vee (VOLTS)
AMBIENT TEMPERATURE !OCI
Typical Application Of TTL Compatible Shift Registers
ACCESS TIME VS. L.oAP CAPACITANCE
000
...
...
SPEcLT
.........V
.RL· 1.5K!l ± 5% ohms.
external
j....---"'"
-
! .,.,..,.
200
DTLITTL
'00
DTIftTL
••
..
200
'00
'50
LOAD CAPACITANCE (pFI
250
300
CHI'
SELECT
INPUTS
NOTE (1): The 2401/2405 is directly compatible device to device •
An external 1.5Kfi ± 5% load resistor is recommended for driving
one TTL load with the 2401/24.05 output.
5·6
2464
65,536 BIT CCO SERIAL MEMORY
Organization: 256 Recirculating Shift Registers of 256 Bits Each
10pF Inputs and Output
• TTL-Compatible,
Including Clocks
Average Latency
• 130jlsec
285
nsec
Access Time
• 2.5 MHz Data
Rate
•
Page Mode Operation
• Standard
+12V, -5V Power Supplies
• High Density
18-Pin Package • Standard 300-mil
Width
Three-State Output
•
The Intel® 2464 is a 65,536-bit CCD serial memory designed for low-cost bulk store, swapping store, and buffer memory
applications. The 2464 incorporates several features which allow it to be used in both large and small systems. These
features are: TTL-compatible 10pF inputs including clocks, wide dynamic operating range, high performance, operation
over the full commercial temperature range, standard 300-mil wide DIP packaging, and versatility.
The 2464 is organized as 256 short recirculating loops of 256 bits each. Anyone of the 256 loops can be accessed by
applying an appropriate 8-bit address along with CEo All 256 loops shift synchronously under the control of two shift
clocks: SE and SYNC. The maximum shift rate is 1MHz for an average latency time of 130llsec, providing very high
performance with easily-designed low-frequency clocks.
The short loop approach and subsequent square architecture of the device makes it feasible to usethe2464 as a serial or as
a paging device. One distinct advantage of page mode operation is that the data rate can be maximized (2.5 MHz) at the
same time the shift rate is minimized, providing high performance at low power disSipation. This is possible because the
shift clocks do not determine the data rate in this mode.
The 2464 generates and uses an internal reference voltage which requires at least 10,000 shift cycles to stabilize, with
power supplies at operating levels. After this start-up period, no special action is needed to keep the internal reference
voltage stable.
The 2464 is a surface-channel CCD fabricated using an advanced Intel N-channel, Silicon-gate MOS process. This process
is an evolution of an existing Intel process used to fabricate 16K dynamic RAMs.
LOGIC SYMBOL
PIN CONFIGURATION
BLOCK DIAGRAM
2464
GND
SYNC
V DD
SE
CE
CE
WE
D,N
WE
Ao
A,
SYNC
@
~VDD
®
0
. @
GND
@)
-----=--- V
DOUT
BB
256-81T RECIRCULATING REGISTER
Ao
As
A5
A,
A,
A,
V BB
~
"hl0
A3
PIN NAMES
0
A,
AO-A7
D,N
DOUT
WE
CE
ADDRESS INPUTS
DATA IN
DATA OUT
WRITE ENABLE
CHIP ENABLE
SENSE ENABLE
SE
SYNC SYNCHRONIZE
+12V
V DD
V BB
-5V
GND
GROUND
A5
TRUTH TABLE
CE
WE
H
L
L
L
X
NOT SELECTED
HIGH Z
L
L-H
DISABLE OUTPUT
HIGH Z
WRITE
READ
HtGHZ
H
OPERATION
§
As
254
A,
255
OUTPUT
D,N
Dour
5-7
Dour
o
= PIN NUMBER
2464
ABSOLUTE MAXIMUM RATINGS*
'COMMENT
TemperatureUnderBias ............ -10°Cto+85°C
Storage Temperature .. . . . . . . . . . .. -q5° C to +150° C
Voltage on Any Pin with
RespecttoGround .................. -0.3V to +16V
Supply Voltages Voo and GND
with Respect to Vss .. . . . . . . . . . . . . . .. -0.3V to +20V
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure ,to absolute maximum rating conditions for extended periods may affect device reliability,
D.C. CHARACTERISTICS
TA = O°C to 70°C, Voo = +12V ±5%, VBB = -5V ±5%, unless otherwise specified
2464
Symbol
Parameter
Min.
TypJ1]
Max.
Unit
ilL
Low Level I nput Current
-10
±1
10
JlA
Test Conditions
VIN::; VIL
IIH
High Level I nput Current
-10
±1
10
JlA
VIN 2: VIH
VOUT = GND to +5V
IILOI
Output Leakage Current
10
JlA
VIL
Input Low Voltage, All Inputs
-0.3
0.8
V
VIH
Input High Voltage, All Inputs Including
CE, SYNC and SE
2.2
5.5
V
VOL
Output Low Voltage
0.4
V
IOL = 2.0mA
VOH
Output High Voltage
V
IOH =-2.0mA
1
2.4
OPERATING POWER CHARACTERISTICS
TA = O°C to 70°C, Voo = +12V ±5%, VBB = -5V ±5%, unless otherwise specified
2464
Symbol
100
AVG
Typ.l1]
Parameter
Average Operating Voo Supply Current
Max.
Note 2
Unit
Test Conditions
mA
1001
100 Component One
11
18
mA
1002
100 Component Two
25
38
mAl
1003
100 Component Three
0.9
1.5
mA
1004
100 Component Four
2.8
4.5
mA
ISS1
Vss Standby Current
ISS2
Vss Average Active Current
MHz
5
50
JlA
200
400
JlA
Typ.l1]
Max.
Unit
5
10
pF
VIN = OV
5
10
pF
VOUT = OV
CAPACITANCE TA = 25°C, f = 1.0MHz
2464
Symbol
Parameter
CIN
Input Capacitance -
COUT
Output Capacitance
All Inputs
Test Conditions
Notes:
1. Typical limits are for Voo = +12V, VBB = -5V, TA = 25°C and specified loading.
2. 100 AVG depends on system operation and can be calculated with the equation below. Referto page8 for a complete power discussion.
TCE
N
TssY1
100 AVG = T
1001 +
1002 + - T - 1003 + 1004
T
Where: T = any arbitrary time period representative of device operation, specified in I'sec.
TCE = total cumulative tCE time during period T
N = number of SE positive edges during period T
TSSY1 = total cumulative ISSY1 time during period T
5-8
2464
A.C. CHARACTERISTICS
TA
= O°C
to 70°C, VDD
= +12V ±5%,
VBB
= -5V
±5%, unless otherwise specified
A.C. TEST CONDITIONS
2464
Condition
O.4V and 2.4V
Input Pulse Levels
Input Rise and Fall Times
10 nsec
Input and Output Timing Levels
O.BV and 2.2V
Output Load
1TTL Gate and CL = 100pF
SEARCH OR REFRESH MODE
Symbol
Unit
2464
Parameter
tSCY1[11
SE Cycle Time with no SYNC Pulse
750
105
tSCY2
SE Cycle Time with SYNC Pulse
1000
ns
tsp
SE Pulse Width
630
ns
tSC1[1]
SE Off Time with No SYNC Pulse
100
ns
tSC2
SE Off Time with SYNC Pulse
350
tSSYl
SE On to SYNC On Time
tSSY2
SE Off to SYNC On Time
0
tSYSl
SYNC On to SE On Time
340
tSYS2
SYNC Off to SE Off Time
50
tSYp
SYNC Pulse Width
150
tREF
Time Between Refresh (256 SE Cycles)
ns
ns
105
ns
ns
TBD
ns
ns
ns
TBD
ms
WAVEFORMS
-~f+----tSCY2----+I
SE
SYNC
_ _ _ _ _Je
Note: 1. For constant 1 MHz operation, use tSCYl
= tSCY2 = 1000ns and tSCl
5-9
= tSC2
= 350ns.
2464
PAGE OR SERIAL MODE
Symbol
2464
Parameter
750
1000
630
100
350
tSCY1
SE Cycle Time with No SYNC Pulse
tSCY2
SE Cycle Time with SYNC Pulse
tsp
SE Pulse Width
tSC1
SE Off Time with No SYNC Pulse
tSC2
SE Off Time with SYNC Pulse
tSSY1
SE On to SYNC On Time
tSSY2
SE Off to SYNC On Time
tSYS1
SYNC On to SE On Time
tSYS2
SYNC Off to SE Off Time
tSYp
SYNC Pulse Width
tSCE
SE On to CE On
tCESY
CE Off to SYNC On Time
0
tCES
CE Off to SE On Time
0
tREF
Time Between Refresh (256 SE Cycles)
0
340
50
150
355
Unit
105
ns
ns
ns
ns
ns
105
ns
TBD
ns
ns
ns
ns
ns
ns
ns
TBD
ms
PAGE MODE TIMING WAVEFORMS
SE
~NC--~------------------~I~------~
ce-----oL
SERIAL MODE TIMING WAVEFORMS
---tSCY2"
-----tSCVl
.---tSCY1-- Ool.
.,J • . tSC1-+
SE
SYNC
--+--------of
icES
Note: 1. tCYC
= Read. Write or RMW data cycle.
&10
tscv'--1---
-tSCY2-----i
2464
READ CYCLE
Symbol
2464
Parameter
tACC
Address to Output Access Time
tRCY
Read Cycle Time
tAS
Address Set Up Time
tAH
Address Hold Time
tCE
CE On Time
tcc
CE Off Time
tcx
CE to Output Active
tco
CE to Output Valid
tOHO
Output Hold from Deselect
toTO
Output Three-State from Deselect
Unit
285
ns
400
0
80
285
ns
95
10
ns
ns
ns
ns
ns
275
10
ns
ns
60
ns
WRITE CYCLE
Symbol
Parameter
twCY
Write Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
tCE
CE On Time
tcc
CE Off Time
tCWL
CE toWE Low
tCWH
CE to WE High
twc
Write to CE Off Time
tos
Data Setup Time
tOH
Data Hold Time
Unit
2464
400
0
80
285
95
ns
ns
ns
ns
ns
10
155
100
0
80
ns
ns
ns
ns
ns
WAVEFORMS
READ CYCLE
WRITE CYCLE
1+-----tACC----~
DATA OUT = HIGH IMPEDANCE
5-11
2464
READ-MODIFY-WRITE CYCLE
Symbol
2464
Parameter
tACC
Address to Output Access Time
tRWC
Read-Modify-Write Cycle Time
tAS
Unit
285
ns
600
ns
Address Setup Time
a
ns
tAH
Address Hold Time
80
ns
tCRW
CE Width During RMW
ns
tcc
CE Off Time
485
95
tcx
CE to Output Active
10
tco
CE to Output Valid
tOHW
Output Hold from Write
tOTW
Output Three-State from Write
twp
Write Pulse Width
twc
Write to CE Off Time
tDS
tDH
ns
ns
275
10
ns
ns
60
ns
100
100
ns
Data Setup Time
a
ns
Data Hold Time
80
ns
WAVEFORMS
READ-MODIFY-WRITE CYCLE
ADDRESSES
Dour----------+----------J
5-12
ns
2464
DEVICE DESCRIPTION
MODES OF OPERATION
The 2464 can be conceptualized as a drum organized into 256
tracks and 256 pages, as illustrated in Figure 1. Each page
consists of 256 bits, one bit from each track.
Access to any random bit is accomplished by first rotating the
drum (i.e., shifting the CCD array) to the page containing the
desired bit. The time required to do this is referred to as the
latency time, and is a function of the SYNC and SE clock rates.
The desired bit is then selected from this page through the use of
an 8-bit address and CE.
Additional bits may be accessed from this page simply by
changing the 8-bit address and cycling CEo This capability is the
result of a characteristic of CCDs that allows them to pause at a
page before resuming rotation. Short loop CCDs characteristically have large pages and are able to pause for relatively long
periods. Long loop CCDs have shorter pages and more stringent
pause time limitations.
a) PAGE MODE
FIGURE 2.
Figure 2a illustrates page mode operation. The 2464 uses an 8-bit
address to randomly select any bit in the selected page. CE and
WE are the signals used to control this operation. They function
like the control signals of a RAM. I n fact, each page can be treated
as a 256-bit RAM. Access to other pages requires rotation of the
drum.
rotated. Although system applications usually limit serial access
to a specific track, this is not a limitation of the device. Addresses
can be changed on the fly during rotation, selecting bits from
different tracks without interruption of the serial data stream. A
practical application of this capability is to create long loops by
moving from the end of one track to the beginning of the next
track.
Figure 2b illustrates serial mode operation, which is actually a
subset of page mode operation. Only one bit is removed from a
page before rotation to the next page and the next bit. In this
fashion, data is serially obtained from a track as the drum is
BIT 0
-
BIT 1 -
c=:
_TRACK 0
,-
_TRACK 1
b) SERIAL MODE
Search mode operation and refresh mode operation are both
similar to serial mode operation. The only difference is that CE is
left high during search and refresh to disable operation of the
RAM control circuitry. During this time WE, DIN and the address
lines are ignored by the device. Dour remains in a highimpedance state. The difference between search mode and
refresh mode operation is the rate at which SYNC and SE are
clocked. Search mode uses high clock rates to minimize latency
times while refresh mode uses low clock rates to minimize power.
SHIFT CONTROL CLOCKS
rCONTROLLED BY
ADDRESSES Ao-A7
The relationship between the two shift clocks, SYNC and SE, can
best be understood by studying the operation of a single 256-bit
loop. Figure 3 is a diagram of one loop that clearly shows the
necessary relationships, although it is not an exact circuit
schematic.
rr-
""'·_/1 111 L"" ~
Each 256-bit loop is actually broken up into four serial registers of
64 bits, with 63 of the 64 bits contained in the array and the 64th bit
contained in either the input or output holding register. These
four serial registers are internally multiplexed to form the
complete 256-bit loop.
_TRACK 255
-
COLUMN OF
READ/WRITE/REFRESH
BUFFERS
PAGE 0
PAGE 1
PAGE 2
A SYNC pulse simultaneously loads four bits from the input
holding register into the beginning of the loop (one bit into each
64-bit register) and unloads four new bits from the end of the loop
FIGURE 1. ORGANIZATION
SE
SYNC
SEL~====+=~
WE----+---
:..:
3232
4K Dynamic RAM Address
Multiplexer and Refresh Counter
24
20ns
750mW
+5
6-25
0
3242
16K Dynamic RAM Address
Multiplexer and Refresh Counter
28
20ns
825mW
+5
6-29
3245
Quad TTL to MOS Driver for
4K RAMs
16
32ns
388mW
+12, +5
6-33
3404
High Speed 6-Bit Latch
16
12ns
375mW
+5
6-3
340BA
Hex Sense Amp and Latch for
MOS Memories
18
25ns
625mW
+5
6-13
5235
Quad Low Power TTL to MOS
Driver for 4K RAMs
16
125ns
240mW
12
High Speed Quad Low Power TTL
to MOS Driver for 4K RAMs
16
95ns
240mW
12
«
-'
0..
lI-
J:
()
t/)
t/)
0
:;:
()
5235-1
6-37
Note 1. Power Dissipation calculated with maximum power supply current and nominal supply voltages.
6-2
inter
3205, 3404
3205 HIGH SPEED 1 OUT OF 8 BINARY DECODER
3404 HIGH SPEED 6-BIT LATCH
Max. Delay Over 0° C to 75° C
• 18ns
Temperature: 3205
• Low Input Load Current: .25mA Max.,
1/6 Standard TTL input Load
Max. Data to Output Delay
• 12ns
Over O°C to 75°C
Line Reflection: Low
• Minimum
Voltage Diode Input Clamp
Outputs Sink 10mA Min.
• 16-Pin
In-Line Package
• Simple Dual
Expansion: Enable Inputs
•
Temperature: 3404
Compatible With DTL and
• Directly
TTL Logic Circuits
• Totem-Pole Output
3205
The 3205 decoder can be used for expansion of systems which utilize memory components with active low
chip select input. When the 3205 is enabled, one of its eight outputs goes "low", thus a single row of a memory
system is selected. The 3 chip enable inputs on the 3205 allow easy memory expansion. For very large memory
systems, 3205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory expansions.
3404
The Intel 3404 contains six high speed latches organized as independent 4-bit and 2-bit latches. They are
designed for use as memory data registers, address registers, or other storage elements. The latches act as high
speed inverters when the "Write" input is "low".
The Intel 3404 is packaged in a standard 16-pin dual-in-line package; and its performance is specified over the
temperature range of oDe to +75 o e, ambient. The use of Schottky barrier diode clamped transistors to obtain
fast switching speeds results in higher performance than equivalent devices made with a gold diffusion process.
PIN CONFIGURATION
3205
3404
Vee
Ao
0,
A,
D,
EI
6,
E,
Vee
6,
AI
1/8 BINARY
06
DECODER
Do
0,
03
'3
0,
W,
GRO
GRD
6·3
0,
3205,3404
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias:
Ceramic
Plastic
'COMMENT
Stresses above those listed under "Absolute Maximum Rat·
ing" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at
any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
-65°C to +125°C
-65°C to +75°C
-65°C to +160o C
Storage Temperatu re
All Output or Supply Voltages
-0.5 to + 7 Volts
All Input Voltages
-1.0 to +5.5 Volts
125 mA
Output Currents
D.C. CHARACTERISTICS
TA ~ aoc to + 75°C, Vee ~ 5.aV ±5%
3205,3404
SYMBOL
PARAMETER
MIN.
INPUT LOAD CURRENT
IF
LIMIT
MAX.
-0.25
UNIT
TEST CONDITIONS
mA
Vee - 5.25V, V F - 0.45V
IR
INPUT LEAKAGE CURRENT
10
J.lA
Vee = 5.25V, V R = 5.25V
Ve
INPUT FORWARD CLAMP VOLTAGE
-1.0
V
Vee = 4.75V, Ie = -5.0 mA
VOL
OUTPUT "LOW" VOLTAGE
V
Vee = 4.75V, 10L = 10.0 mA
VOH
OUTPUT HIGH VOLTAGE
V
Vee = 4.75V, 10H = -1.5 mA
V,L
INPUT "LOW" VOLTAGE
V
Vee = 5.0V
V ,H
INPUT "HIGH" VOLTAGE
V
Vee = 5.0V
Ise
OUTPUT HIGH SHORT
CIRCUIT CURRENT
mA
Vee = 5.0V, VOUT = OV
Vox
OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT
V
Vee = 5.0V, lox = 40 mA
0.45
2.4
0.85
2.0
-40
-120
0.8
V CC ~ 5.25V, Outputs Open
POWER SUPPLY CURRENT
3404 ONLY
POWER SUPPLY CURRENT
75
mA
VCC ~ 5.25V, Outputs Open
WRITE ENABLE LOAD CURRENT
PIN 7
-1.00
mA
Vee =5.25V, Vw =0.45V
IFW2
WRITE ENABLE LOAD CURRENT
PIN 15
-0.50
mA
Vee =5.25V, Vw =0.45V
IRW
WRITE ENABLE LEAKAGE CURRENT
10
~A
VR -5.25V
lee
IFW1
TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
100
TA
TA
80
~
(/
TA '"
= 75"C~ fA;
/, ~
./# r-.
.2
.4
TA '" Doe-
-30
1,1
TA
ff:
V/f,
-20
)
40
-10
I
T A '" DOC
TA '" 25"C
-50
.8
OUTPUT "lOW" VOL TAGE (V)
1.0
ll'
/I
1.0
1 .1_
Vee'" 5.0V
f.;. = 25"C
I-- -
4.0
TA '" 75"C
TA - DoC
3.0
I
TA '" 25"C
2.0
T A '" 75°C_
J
If
A
-40
.6
DATA TRANSFER FUNCTION
5.0
r- ~cc ~ 50~
1
occ
#
60
20
.Y
=75°G_
= 25"C ~
Vee - 5.0V
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
1.0
1\ ~
H- rll\
1--, \
1\ 1\
\
\. ~ ~
2:.0
3.0
4.0
OUTPUT "HIGH" VOLTAGE (V)
6-4
5.0
o
.2
.4
.6
.8
1.0
1.2 1.4 1.6 1.8 2.0
INPUT VOL T AGE (V)
3205, 3404
3205 HIGH SPEED 1 OUT OF 8 BINARY DECODER
SWITCHING CHARACTERISTICS
CONDITIONS OF TEST:
TEST LOAD:
390fl
Input pulse amplitudes: 2.5V
Input rise and fall times: 5 nsec
between 1V and 2V
Measurements are made at 1.5V
2K
All Transistors 2N2369 or Equivalent. CL ::: 30 pF
TEST WAVEFORMS
jI,~_ ',,1-
ADDRESS OR ENABLE
INPUT PULSE
'\
_1,''-+.-,_-_-1--.---------
____-...1
-__-_-_-_-_-_-_-_-_-_-_-_-_~J~--------------------~~ _______________ _
OUTPUT
A.C. CHARACTERISTICS
TA =
ooe to +75°C, Vcc = 5.0V ±5% unless otherwise specified.
PARAMETER
SYMBOL
MAX. LIMIT
t++
ADDRESS OR ENABLE TO
OUTPUT DELAY
t_+
t+_
CIN
ns
18
ns
18
ns
18
t --
in
INPUT CAPACITANCE
1. This parameter
IS
periodically sampled and
IS
P3205
C3205
4(typ.1
5(typ.1
,
UNIT
18
TEST CONDITIONS
ns
pF
pF
f
1 MHz. Vee
~
~
OV
VBIAS ~ 2.0V. TA ~ 250 e
not lOOro tested.
TYPICAL CHARACTERISTICS
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE
20r----,-----,-----,----~
20.------,-------,1.-------,
Vee" 5.0V
TA =2S"C
Vee
cL
15 f-.--__l----___+\;;,\ ........",..
= 5.0V
"30 pF
15~----___+------~------~
'-'
'-.
101===t===t===:::j
10~--·__l-----+7,,-,--~--~--1
t ..
o~--~----~----~-----"
o
50
100
150
o~----~L-
o
200
25
____
______
50
~
AMBIENT TEMPERATURE (OC)
LOAD CAPACITANCE (pF)
6-5
~
75
3205,3404
3404 6-BIT LATCH
SWITCHING CHARACTERISTICS
VCC
TEST LOAD:
CONDITIONS OF TEST:
Input pulse amplitudes: 2.5V
Input rise and fall times: 5 nsec
between 1 V and 2V
390\1
7fF
Measurements are made at 1.5V
-=-
I·
All Transistors 2N2369 or Equivalent. C L =
TEST WAVEFORMS
MEASUREMENT FOR DATA DELAY
DATA
INPUT
-=-
,
---~I'-------------------'
,
,
DATA
INPUT
~------------------~
WRITE
ENABLE
_I--t+_.t_+
-:"
--------~~,r-~~;;~--------------------""",
NOTE 1: Output Data
IS
SYMBOL
OUT
NOTE 2
valid after t+ • t _ +
A.C. CHARACTERISTICS
TA
\J,,,----------------------------~~
1·MEASUREMENT FOR WRITE ENABLE DELAY
I - - · - t w p - - i t HOLD
WRITE
ENABLE
OUT
\
Output Data
MIN.
LIMITS
TYP.
j~------------------~~N_O_T_E
__
2 ______________
valid after
t __ , t _
DATA TO OUTPUT DELAY
12
WRITE ENABLE TO OUTPUT DELAY
17
tSET UP
TIME DATA MUST BE PRESENT BEFORE
RISING EDGE OF WRITE ENABLE
tHO LD
TIME DATA MUST REMAIN AFTER
RISING EDGE OF WRITE ENABLE
'WP
C IND (3)
WRITE ENABLE PULSE WIDTH
DATA INPUT CAPACITANCE
WRITE ENABLE CAPACITANCE
UNIT
MAX.
t+_.t_+
IS
.<;
1
+
= O°C to +75°C, VCC = 5.0V ±5%; unless otherwise specified.
PARAMETER
NOTE 3: This parameter
i _ l - t __ .t_+
__________
t __ .t_+
CINW (3)
-=-
30pF
TEST CONDITIONS
ns
ns
12
ns
8
ns
ns
15
P3404
4
pF
C3404
5
pF
VBIAS
P3404
7
pF
f - 1 MHz, VCC - OV
C3404
8
pF
VBIAS
penodlcdlly sampled and
IS
f - 1 MHz, VCC - OV
= 2.0V,T A
o
250C
= 2.0V,T A = 25°C
not 100% tested.
TYPICAL CHARACTERISTICS
DATA INPUT, WRITE ENABLE
TO OUTPUT DELA Y VS.
AMBIENT TEMPERATURE
DATA INPUT, WRITE ENABLE
TO OUTPUT DELAY VS.
LOAD CAPACITANCE
20r-----.-----.------.--~-,
15
f-----1--:,
20
WRITE ENABLE PULSE WIDTH
VS. LOAD CAPACITANCE
20
I
Vee
cL
T A =2S'C
'" ]30 pF
'5
'5
WRITE ENABLE 1 -
,O~----+-
10
DATA
'0
dR WRITE ENA~LE C.j.
DATA t+
o
'00
200
300
LOAD CAPACITANCE (pFl
400
o
25
50
AMBIENT TEMPERATURE ("C)
6-6
~ 5.0V
Vee = 5.0V
75
-
,--
'00
~
200
V
300
LOAD CAPACITANCE (pF)
400
inter
3207A
QUAD BIPOLAR-TO-MOS
LEVEL SHIFTER AND DRIVER
• Easy to Use - Operates from Standard
Bipolar and MOS Supplies
• High Speed, 45 nsec Max. - Delay
+ Transition Time Over Temperature
with 200 pF Load
• TTL and DTL Compatible Inputs
• 1103 and 1103A Memory Compatible
at Output
• Simplifies Design - Replaces
Discrete Components
• Minimum Line Reflection Output Clamp Diodes
Input and
• High Input Breakdown Voltage 19 Volts
• CerDIP Package -
16 Pin DIP
The 3207A is a Quad Bipolar-to-MOS level shifter and driver which accepts TTL and DTL input signals, and
provides high output current and voltage suitable for driving MOS circuits. It is particularly suitable for driving
the 1103 and 1103A memory chips. The circuit operates from a 5 volt TTL power supply, and Vss ,and Vss
power suppl ies from the 1103 and 11 03A.
The device features two common enable inputs per pair of devices which permits some logic to be done at their
inputs, such as cenable and precharge decoding for the 1103 and 11 03A.
For the TTL inputs a logic" 1" is VIH and a logic "0" is VI L. The 3207 A outputs correspond to a logic" 1" as
VOL and a logic "0" as VOH for driving MOS inputs.
The 3207A is packaged in a hermetically sealed 16 pin ceramic dual-in-line package. The device performance
is specified over the same temperature range as the 1103 and 11 03A, i.e. from OOC to +70°C.
PIN CONFIGURATION
LOGIC SYMBOL
Dl
OUTPUT
OATAINPUT
OUTPUT
ENABLE INPUT
ENABLE INPUT
ENABLE INPUT
DATA INPUT
OUTPUT
E2
DATA INPUT
ENABLE INPUT
01
El
D2
03
DATA INPUT
E3
E4
OUTPUT
D4
6-7
O2
03
°4
3207A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
......... OOC to +70 o C
'COMMENT
Storage Temperature. . . . . . . . . . . -65°C to +160 o C
All Input Voltages and VSS"
Stresses above those listed under"Absolute Maximum Ratings"may
cause permanent daniage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this
specification IS not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
........ -1.0 to +21V
Supply Voltage VCC . . . • . . . . . . . . . . . -1.0 to + 7V
All Outputs and Supply Voltage
V BB with respect to GND . . . . . . . .. -1.0 to +25V
Power Dissipation at 25°C ..•...•.•..• 2 Watts (11
(1) Refer to the graph of Junction Temperature versus Total Power Dissipation on page 5~10 for other temperatures.
D.C. CHARACTERISTICS
T A = ooe to 70o e, Vcc= 5V ± 5%, VSS = 16V
SYMBOL
TEST
IFD
DATA INPUT LOAD CURRENT
IFE
ENABLE INPUT LOAD CURRENT
IRD
LIMIT
± 5%, VBB-VSS= 3.0V to 4.0V·
UNIT
CONDITIONS
-0.25
mA
VD = .45V. Vee= 5.25V, All Other Inputs
at 5.25V, VSS= lSV, Vee= 19V
-0.50
mA
VE = .45V, Vee= 5.25V, All Other Inputs
at 5.25V, Vss= lSV, Vee= 19V
DATA INPUT LEAKAGE
CURRENT
20
p.A
V D = 19V, Vee= 5:0V, All Other Inputs
Grounded, VSS= lSV, Vee= 19V
IRE
ENABLE INPUT LEAKAGE
CURRENT
20
p.A
V E = 19V, Vee= 5.0V, All Other Inputs
Grounded, VSS = lSV, Vee= 19V
Val
OUTPUT "LOW" VOLTAGE
.8
.7
.S
VOH (MIN.)
OUTPUT "HIGH" VOLTAGE
MIN.
MAX.
Vss -.7
Vss -.S
Vss -·5
VOH(MAX.)
VSS + 1.0
V(O°CI
V(25OCI
V(70oCI
IOl = 500llA, Vee= 4.75V
Vss= 16V, Vee= 19V
All Inputs at 2.0V
v(O°CI
V(2s"CI
V(70oCI
IOH= -500p.A, Vee= 5.0V
Vss = 16V, Vee= 19V
All Inputs at 0.85V
V
IOH = 5mA, VCC = 5.0V
VSS = lSV, V BS = 19V
IOl
OUTPUT SINK CURRENT
100
mA
Va = 4V, Vee= 5.0V,V 55= lSV,
Vee = 19V, VEe VD= 2.0V
IOH
OUTPUT SOURCE CURRENT
-100
mA
Va = VSS -4V, Vee= 5.0V, VSS = lSV
Vee= 19V, VE = VD = 0.85V
Vil
INPUT "LOW" VOLTAGE
VIH
INPUT "HIGH" VOLTAGE
CIN
INPUT CAPACITANCE
1.0
2.0
8(Typicall
V
Vee= 5.0V, Vss = lSV, Vee= 19V
V
Vee= 5.0V, VSS= lSV, Vee= 19V
pF
V eIAS = 2.0V, Vee= OV
POWER SUPPLY CURRENT DRAIN:
All Outputs "Low"
Symbol
Parameter
Max.
Unit
ICC
Current from
Vee
83
mA
ISS
Current from VSS
250
Il A
21
mA
900
mW
Min.
Vas
ISB
Current from
PTOTAL
Total Power Dissipation
Conditions
VCC = 5.25V, VSS = 16.8V, VSS = 20.8V
All I nputs Open
All Outputs "High"
ICC
Current from
Vee
33
mA
ISS
Current from VSS
250
IlA
ISS
Current from V BS
3
mA
PTOTAL
Total Power Dissipation
250
mW
VCC = 5.25V, VSS = 16.8V, VSS = 20.8V
All Inputs Grounded
Standby Condition with V CC = OV, V SS = V BB
ICC
Current from
Vee
0
mA
ISS
Current from VSS
250
IlA
ISS
Current from V BS
250
IlA
PTOTAL
Total Power Dissipation
10
6·8
mW
VCC = OV, VSS =16.8V, VSS = 16.8V
3207A
SWITCHING CHARACTERISTICS
A.C. CHARACTERISTICS
T A = DoC to 70°C, Vee = 5V ±5%, Vss = 16V ±5%, VBB = Vss +3 to 4V, f = 2 MHz, 50% Duty Cycle
LIMITS (ns)
SYMBOL
TEST
CL = 100pF
MIN.
MAX.
(1)
5
15
5
25
OUTPUT RISE TIME
5
OUTPUT FALL TIME
5
10
t+_
INPUT TO OUTPUT DELAY
t_+
INPUT TO OUTPUT DELAY
tr
tf
to
DELAY + RISE OR FALL TIME
CL = 200 pF
MIN.
MAX.
DELAY DIFFERENTIALllI
C L = 200 pF
MAX.
5
15
5
5
25
10
20
5
30
10
20
10
30
10
35
20
45
10
This is defined as the maximum skew between any output in the same package, eg., all the input to output delays for the
t_+ parameter are within a maximum of 10 nsec of each other in the same package.
WAVEFORMS
OUT
IN
GNO
TYPICAL CHARACTERISTICS
SWITCHING TIME VS.
AMBIENT TEMPERATURE
SWITCHING TIME VS.
LOAD CAPACITANCE
40
40.-----,-----,-----,------,
I
Vee =50V
30
vss
=16V
I---- V BB
'" 19V
cL
=
VCC=50V
30
200 pF
I
-
20
t10
o
Vss = 16V
. VBS = 19V
TA
--
---+-----+------1
= 2SoC
-,-,t.
tf
-t,_
oL-____L -____
o
20
40
60
o
80
100
~
200
_____ L_ _ _ __"
300
LOAD CAPACITANCF; (pF)
AMBIENT TEMPERATURE JOC)
6-9
400
3207A
POWER AND SWITCHING CHARACTERISTICS
POWER CONSUMED IN CHARGING AND
DISCHARGING LOAD CAPACITANCE
OVER OV TO 16V INTERVAL
NO LOAD D.C. POWER DISSIPATION VS.
OPERATING DUTY CYCLE
.2 r-----------------~----~----~----~~
1.0
,-----------r---------,-----------,--------,
Vee = 5V
Vss = 16V± 5%
.1
VBB '" Vss + 3 to 4 V
"«
"
"J:z
.75
...J
!
z
~
";::«
'" «z
I-
'"i5
~
;;:
U
I-
j; Uw
0.
in
":;;w'" U«
::>
'"
Z
.50
a:
w
~
c.5
U
"a:
U
c:i
~
.25
"
0.
.2
.4
B
1
°0~--------~--------5~0--------~75---------10~0
B 10
SWITCHING DUTY CYCLE (%)
FREQUENCY OF SWITCHING (MHz)
POWER = CV 2 f
WORST CASELOAD CAPACITANCE
ON EACH OUTPUT VS.
FREQUENCY OF SWITCHING
JUNCTION TEMPERATURE VS. TOTAL
POWER DISSIPATION OF THE CIRCUIT
200r---------~--------,---------,_------~
400r---------~--_.----,_--------,---------,
OPERATING IN THIS REGION IS NOT
RECOMMENDED
~
w
~
~0r---------+-~------~--------~--------~
«
~u.
uu.
«.:!
::>
Uo.
"I-
«a:
g~
!::-
"wa:
~~
«OJ
I-
w
wu
~~
0.
ill
U
IZ
z
in"
a:
~
o
;::
U
Z
~
200 I--------+---------~
SAFE OPERATING
REGION
100r---------t---------+---------;------=~~
: Vee
= 5V,
! TA = 70 0 e
Vss
= 16V,
V BB
= 19V
MAX. JUNCTION TEMPERATURE = 150"C
OL-------~--------~------~--------~
o
TOTAL POWER DISSIPATION OF THE CIRCUIT (W)
TOTAL POWER = D.C. POWER + POWER CONSUMED IN
CHARGING AND DISCHARGING LOAD CAPACITANCE.
FREQUENCY DF SWITCHING (MHz)
6-10
inter
3207A-1
QUAD BIPOLAR-TO-MOS
LEVEL SHIFTER AND DRIVER
• Power Supply Voltage Compatible
with the High Voltage 1103-1
• 1103-1 Memory Compatible
at Output
The Intel 3207 A-1 is the high voltage version of the standard 3207 A, and is compatible with the 1103-1. The
3207A-1 has all the same features as the standard 3207A. The absolute maximum ratings and pin configuration
are repeated below for convenience, while the DC and AC characteristics appear below and on the next page.
PIN CONFIGURATION
OUTPUT
DATA INPUT
ENABLE INPUT
ENABLE INPUT
DATA INPUT
OUTPUT
ABSOLUTE MAXIMUM RATINGS*
LOGIC SYMBOL
Temperature Under Bias . . . . . . . . . . oOe to +55°e
Storage Temperature . . . . . . . . . . . -65° e to +1600 e
All Input Voltages . . . . . . . . . . . . -1.0to +21 Volts
Supply Voltage VCC . . . . . . . . . . . -1.0 to +7.0 Volts
All Outputs and Supply Voltages VBB and Vss
with respect to GND . . . . . . . . . . . -1.0 to +25 Volts
Power Dissipation at 25°e . . . . . . . . . . . . . . . 2 Watts
OUTPUT
DATA INPUT
ENABLE INPUT
ENABLE INPUT
DATA INPUT
COMMENT:
OUTPUT
Stresses above those listed under" Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTICS TA = oOC to 550 C, Vee = 5V
SYMBOL
IFD
TEST
LIMIT
MIN.
MAX.
DATA INPUT LOAD CURRENT
-0.25
± 5%, VSS
=19V ± 5%, VsB -VSS = 3.0V to 4.0V
UNIT
rnA
CONDITIONS
Vo
0=
.45V, Vee= 5.25V, All Other Inputs
at 5.25V, Vss " 19V, V ss " 23V
IFE
ENABLE INPUT LOAO CURRENT
-0.50
rnA
VE " .45V, Vee" 5.25V, All Other Inputs
at 5.25V, Vss " 19V, Vss " 23V
IRD
DATA INPUT LEAKAGE
CURRENT
20
/lA
V D " 19V, Vee" 5.0V. All Other Inputs
Grounded. Vss " 19V, Vss " 23V
IRE
ENABLE INPUT LEAKAGE
CURRENT
20
/lA
V E " 19V. Vee" 5.0V. All Other Inputs
Grounded.V ss " 19V, Vss " 23V
VOL
OUTPUT "LOW" VOLTAGE
O.B
VlOoCI
0.7
0.6
V(25OCI
VOH (MIN.!
OUTPUT "HIGH·' VOLTAGE
V(550CI
Vss -0.7
Vss -0.6
VlOoCI
Vss -0.5
V(550CI
VOH (MAX.!
V(25OCI
VSS + 1.0
V
IOL "500IlA. Vee - 4.75V
VSS " 19V, Vsa " 23V
All Inputs at 2.0V
IOH" - 500/lA. Vee" 5.0V
Vss " 19V, Vas" 23V
All Inputs at O.85V
IOH" 5rnA, VCC" 5.0V
VSS" 19V, V BB "23V
IOL
OUTPUT SINK CURRENT
100
rnA
Vo "4V, V ce" 5.0V.V ss " 19V,
Vaa " 23V, VE " VD " 2.0V
IOH
OUTPUT SOURCE CURRENT
-100
rnA
Vo " Vss -4V, Vee" 5.0V. Vss " 19V
Vaa" 23V, VE " VD " 0.S5V
V'L
INPUT ··LOW··VOLTAGE
V,H
INPUT "HIGH·· VOLTAGE
C'N
INPUT CAPACITANCE
1.0
2.0
S(Typicai)
6-11
V
Vee" 5.0V, Vss " 19V, v sa " 23V
V
Vee" 5.0V. Vss " 19V, Vaa " 23V
pF
V aIAS " 2.0V, Vee" OV
3207A-1
D.C. CHARACTERISTICS (Cant'd)
TA = oOC to +55°C, vee
= 5V ± 5%, Vss = 19V ± 5%,
VBB -Vss
= 3.0V to 4.0V
POWER SUPPLY CURRENT DRAIN:
All Outputs '"low" .
Symbol
Min.
Parameter
Max.
Unit
ICC
Current from
Vee
83
rnA
ISS
Current from VSS
250
I1A
25
rnA
1040
rnW
Current from
IBB
Vas
Total Power Dissipation
PTOTAL
Conditions
Vee
~
5.25V, Vss
20V. VBB
~
~
24V
All Inputs Open
All Outputs '"High'"
ICC
Current from
Vee
33
rnA
ISS
Current from VSS
250
I1A
5
rnA
297
rnW
Vas
IBB
Current from
PTOTAL
Total Power Dissipation
Standby Condition with Vee
~
Current from
Vee
0
rnA
ISS
Current from VSS
500
I1A
Vas
500
I1A
15
rnW
Current from
'BB
~
5.25V. Vss
~
20V"VBB~
24V
All Inputs Grounded
OV. VSS = V BB
Ice
Total Power Dissipation
PTOTAL
Vee
Vee
~
OV, Vss
~
20V, VBB
~
20V
A.C. CHARACTERISTICS
TA
= OOC to 550 C, Vee = 5V ±5%, Vss = 19V ±5%, VBB = Vss
+3 to 4V, f
= 2 MHz, 50% Duty Cycle
LIMITS (ns)
SYMBOL
DELAY DIFFERENTIAL (1 )
TEST
CL
MIN.
(1)
= 100 pF
MAX.
CL
MIN.
= 200 pF
MAX.
CL
= 200 pF
MAX.
t+_
INPUT TO OUTPUT DELAY
5
15
5
15
5
t_+
INPUT TO OUTPUT DELAY
5
25
5
25
10
10
tr
OUTPUT RISE TIME
5
20
5
30
t,
OUTPUT FALL TIME
5
25
10
35
10
tD
DELAY + RISE OR FALL TIME
10
35
20
45
10
This is defined as the maximum skew between any output in the same package, eg., all the input to output delays for the
t_+ parameter are within a maximum of 10 nsec of each other in the same package.
WAVEFORMS
OUT
IN
GND
6-12
infer
3208A, 3408A
HEX BIPOLAR SENSE AMPLIFIERS
FOR MOS CIRCUITS
3208A HEX SENSE AMPLIFIER
3408A HEX SENSE AMPLIFIER WITH LATCHES
• High Speed - 20nsec Max.
• Wire-OR Capability Open Collector Output: 3208A
Three-State Output: 3408A
• Single SV Power Supply
• Input Level Compatible with
1103 Output
• Two Enable Inputs
• Minimum Line Reflection: Low
Voltage Diode Input Clamp
• Plastic 18 Pin Dual In-Line Package
• Schottky TTL
The Intel 3208A is a high speed hex sense amplifier designed to sense the output signals of the 1103 memory.
The device features two separate enable inputs each controlling the output state of three sense amplifiers, and a
common voltage reference input. OR-tie capability is available with the 3208A open collector TTL compatible
output.
The 3408A is a hex sense amplifier with a latch circuit connected to each amplifier. The sensed data may be
stored in the latches through application of a write pulse. The 3408A has three-state TTL outputs, hence in the
non-enabled state the outputs float allowing wire-OR memory expansion. The latches may be bypassed by
grounding the write input pin. Under this condition, the 3408A functions as a hex sense amplifier.
The 3208A and 3408A operate from a single +5 volt power supply. Device performance is specified over the
complete ambient temperature range of ooe to 70 0 e and over a Vee supply voltage range of 5 volts ±5%. The.
3208A and 3408A are packaged in an 18 pin plastic dual in-line package.
PIN CONFIGURATIONS
NC
v"
BLOCK DIAGRAMS
E,
w
REF
E,
REF
S,
0,
s,
0,
s,
0,
s,
0,
s,
0,
s,
0,
s,
0,
s,
0,
Os
I,
s,
s,
Ss
Os
Ss
S,
0,
S,
GNO
E,
Os
S,
E,
s,
3208A
3408A
PIN NAMES
SI. S2. S3. S4. S5. S6
SENSE AMP INPUTS
El. E2
ENABLE INPUTS
REF
REFERENCE INPUT
01.02.03.04.05.06
OUTPUTS (Non-inverting)
WRITE INPUT 1340BA only)
VIi
o
6-13
~ PIN NUMBER
o
= PIN NUMBER
3208A, 3408A
ABSOLUTE MAXIMUM RATINGS·
*COMMENT:
Temperature Under Bias
-55°C to +125°C
Storage Temperature
-65°C to +160 o C
All Outputs or Supply Voltage -0.5 to +7 Volts
-1 to +5.5 Volts
All TTL Input Voltages
All Sense Input Voltages
-1 to +1 Volt
Output Currents Total
300mA
Input Current
125mA
Stresses al:5ove those listed under Absolute
Maximum Rating" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at this or at
any other condition above those indicated in the
operational sections of this specification is not
implied.
II
D.C. CHARACTERISTICS FOR 3208A TA = O°C to 70°C, VCC = 5V ±5%
SYMBOL
I·
-:
PARAMETER
LIMITS
TYP.
MIN.
MAX.
UNIT
TEST CONDITIONS
IFE
INPUT LOAD CURRENT ON
ENABLE INPUT
-0.25
mA
Vce = 5.25V
VF = 0.45V
IRE
INPUT LEAKAGE CURRENT
ON ENABLE INPUT
20
p.A
Vee =4.75V
VR = 5.25V
V1H
INPUT "H IGH" VOLTAGE
ON ENABLE INPUT
V
Vee = 5.0V
V1l
INPUT "LOW" VOLTAGE
ON ENABLE INPUT
0.85
V
Vee = 5.0V
VOL
OUTPUT "LOW" VOLTAGE
0.45
V
Vee = 4.75V
10l = 10mA
leEX
OUTPUT LEAKAGE CURRENT
100
p.A
Vee = 5.25V
VeEX = 5.25V
IREF
INPUT CURRENT ON
REFERENCE INPUT
-150
p.A
Vee = 5.25V
VREF = 100mV
Is
INPUT CURRENT ON
SENSE AMP INPUT
-25
p.A
Vee = 5.25V
Vs= 100mV
VSH
INPUT "HIGH" VOLTAGE FOR
SENSE AMP INPUT
mV
Vee = 4.75 to 5.25V
VREF = 100 to 200mV
VSl
INPUT "LOW" VOLTAGE FOR
SENSE AMP INPUT
VREF
-50
mV
Vee = 4.75 to 5.25V
V REF = 100 to 200mV
VREF
OPERATING RANGE OF
REFERENCE VOLTAGE
200
mV
Vee = 4.75 to 5.25V
Icc
POWER SUPPLY CURRENT
120
mA
Vee = 5.25V
Ve
INPUT CLAMP VOLTAGE
ON ALL INPUTS
-1.0
V
Vee = 4.75V
le= -5.0mA
VSD
SENSE INPUT CLAMP
DIODE VOLTAGE
1.0
V
Vee =5.0V
ID= 5.0mA
,
2.0
VREF
100
3208A TRUTH TABLE
INPUTS
Sense Amp
Enable
OUTPUT
VREF
L
H
X
H
H
6-14
x = Don't care
3208A, 3408A
D. C. Characteristics for 3408A
SYMBOL
PARAMETER
INPUT LOAD CURRENT
ON ENABLE INPUT
IRE
INPUT LEAKAGE CURRENT
ON ENABLE INPUT
IFW
INPUT LOAD CURRENT
ON WRITE INPUT
I RW
INPUT LEAKAGE CURRENT
ON WRITE INPUT
V1H
INPUT "HIGH" VOLTAGE
ON ENABLE AND WRITE INPUT
V1L
INPUT "LOW" VOLTAGE ON
ENABLE AND WRITE INPUT
VOL
OUTPUT "LOW" VOLTAGE
VOH
OUTPUT "HIGH" VOLTAGE
I
= ooc to +700 C,
MIN.
IFE
110
TA
LIMITS
TYP.
vcc = 5V ±5%
-0.25
mA
Vee = 5.25V
VF = 0.45V
20
pA
Vee = 4.75V
VR = 5.25V
-0.25
mA
Vee = 5.25V
VF = 0.45V
20
pA
Vee = 4.75V
VR = 5.25V
V
Vee = 5.0V
0.85
V
Vee = 5.0V
0.45
V
Vee = 4.75V
10L = 10mA
V
Vee = 4.75V
IOH=-1.5mA
100
pA
Vee = 5.25V
Vo = 0.45V /5.25V
-100
mA
Vee = 5.0V
Vo=OV
2.0
2.4
OUTPUT LEAKAGE CURRENT
FOR HIGH IMPEDANCE STATE
TEST CONDITIONS
UNIT
MAX.
Ise
OUTPUT SHORT CIRCUIT
CURRENT
IREF
INPUT CURRENT ON
REFERENCE INPUT
-150
pA
Vee = 5.25V
VREF = 100mV
Is
INPUT CURRENT ON
SENSE INPUT
-25
pA
Vee = 5.25V
Vs= 100mV
V SH
INPUT "HIGH" VOLTAGE
FOR SENSE AMP INPUT
mV
Vee = 4.75 to 5.25V
VREF = 100 to 200mV
VSL
INPUT "LOW"VOLTAGE
FOR SENSE AMP INPUT
V REF
-60
mV
Vee = 4.75 to 5.25V
VREF = 100 to 200mV
VREF
OPERATING RANGE OF
REFERENCE VOLTAGE
200
mV
Vee = 4.75 to 5.25V
lee
POWER SUPPLY CURRENT
125
mA
Vee = 5.25V
Ve
INPUT CLAMP VOLTAGE
ON ALL INPUTS
-1.0
V
Vee = 4.75V
le= -5.0V
Vso
SENSE INPUT CLAMP
DIODE VOLTAGE
1.0
V
Vee = 5.0V
10= 5.0mA
-40
VREF
100
3408A TRUTH TABLE
Sense Amp
V REF
X
INPUTS
Enable
Write
L
L
OUTPUT
L
L
L
H
L
H
Previous
Data Stored
X
H
X
6-15
High Z'
x
= Don't care
'The output of the 3408A is three-state.
hence when not enabled the output is a
high impedance.
3208A, 3408A
TYPICAL D.C. CHARACTERISTICS FOR 3208A/3408A
SENSE AND REFERENCE INPUT CURRENT
VS. AMBIENT TEMPERATURE
SENSE THRESHOLD VS.
REFERENCE INPUT VOLTAGE
300,-__________, -__________- ,__________--,
-60
Vee'" 5.0V
Vee"5.0V
u
I-
ir
~
;!;
-
REFERENCE INPUT
UJ
U
2
UJ
a::
UJ
"UJ
a::
.."2
-20
:>
E
--
200
"
":fl
..J
J:
a::
J:
IUJ
'"
'"
2
UJ
100
UJ
iii'"
'"
SENSE INPUT
o
O~----------~-----------L----------~
o
25
50
70
o
75
100
200
300
REFERENCE INPUT VOLTAGE ImV)
AMBIENT TEMPERATURE 1°C)
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
4o,--------,---------,---------r--~~~,
Vee" 5.0V
TA'" 25°C
T A = 70De
-10
30
TA" 70°C
TA " 25"C
u
-20
2
a::
a::
:::>
u
20
..
.
I-
I-
:::>
:::>
I-
-30
I-
:::>
0
:::>
0
10
-40
-50LO------~~L---~------~----~7-----~5.0
°0~---L~~---------2~0~0------~30~0--------~400
OUTPUT "HIGH" VOLTAGE IV)
OUTPUT "LOW" VOLTAGE 'mV)
6-16
3208A, 3408A
A.C. CHARACTERISTICS
T A = ooe to 7o oe, Vcc
=
5V ±5%
3208A
SYMBOL
PARAMETER
LIMITS
TYP.
MIN.
UNIT
MAX.
ts_
SENSE AMP INPUT TO OUTPUT
DELAY
20
tE_
t E+
ENABLE INPUT TO OUTPUT
DELAY
20
TEST CONDITIONS
D.C. LOAD
C L = 30pF
= 10mA
D.C. LOAD
C L = 30pF
= 10mA
ns
D.C. LOAD
CL = 30pF
= 10mA
ns
ns
25
3408A
twp
WRITE PULSE WIDTH
ts_
SENSE AMP INPUT TO OUTPUT
DELAY
25
ns
D.C. LOAD
C L = 30pF
= 10mA
t E-
ENABLE INPUT TO OUTPUT
DELAY. LATCH STORES "LOW"
20
ns
D.C. LOAD
C L = 30pF
~
tE+
ENABLE INPUT TO OUTPUT
DELAY, LATCH STORES "HIGH"
25
ns
D.C. LOAD
C L = 30 pF
= 10mA
CAPACITANCE
SYMBOL
III TA
30
SWITCHING CHARACTERISTICS
= 25°C, f = 1 MHz
LIMITS
TYP. MAX.
TEST
= OV, V SIAS = 2.0V
Co
Vee
CINE
ENABLE INPUT
Vee = OV, V SIAS
= 2.0V
C INS
SENSE INPUT
Vee = OV, V SIAS
= OV
10mA
B
12
6
10
6
10
(11 This parameter is periodically sampled and is
not 100% tested.
CONDITIONS OF TEST
•
Input Pulse amplitude: 2.5V for all TTL compatible
inputs and 2.5V through a resistor network as shown
below for sense input.
•
•
Input Pulse rise and fall times: 5 ns.
Speed measurements are made at 1.5V for all TTL
compatible inputs and outputs. and for sense input.
see network and waveforms below. VREF is set at
150mV.
10mA TEST LOAD
SENSE INPUT
:d
Vee
WAVEFORMS
450 !!
3208A/3408A
D.U.T.
OUTPUT
240~!
ENABLE
INPUT
1K
30pF
OUTPUT
3408A ONLY
PULSE
INPUT
SENSE
INPUT
OUTPUT
6-17
3208A, 3408A
TYPICAL A.C. CHARACTERISTICS
SENSE INPUT TO OUTPUT DELAY
VS. AMBIENT TEMPERATURE
ENABLE INPUT TO OUTPUT DELAY
VS. AMBIENT TEMPERATURE
30
30
Vee = 5.0V
D.C. LOAD
C l == 30pF
Vee == 5.0V
D.C. LOAD == lOrnA
CL = 30pF
VREF == 150mV
>-
>~
:5UJ
20
0
...
...
.
:::l
.
0
0
......
:::l
3408A ts
-
:::l
-
3208A ts
:::l
0
0
~
320S~
......
3408A tE+
~
:::l
w
z
w
20
...
...
0
.
lOrnA
]
]
2107C. The 3222 is well
suited for asynchronous dynamic memory systems.
The 3222 operates from a single +5 volt power supply and is specified for operation over a 0° C to 75° C ambient temperature
range. It is fabricated by means of Intel's highly reliable Schottky bipolar process.
BLOCK DIAGRAM
PIN CONFIGURATION
VCC
REFREQ
Rx/Cx
ACK
CYREQ
STARTey
ADDRESS
INPUTS
6
~:X
' .. ·A. J
REFON
BUSY
A3
As
OS
02
TIMER
CONTROL
0;
03
ADDRESS INPUTS
ACKNOWLEDGE
Aa
o TP T
BUSY
BUSY INPUT
CYREO CYCLE REOUEST
INPUT
00· Os
0
XI
il
681T
REFRESH
COUNTER
~
lCLOCK
,.J
,,
SELECT
,
PIN NAMES
Ao·A.
MULTIPLEXER
C
A.
GROUND . .'_'_ _ _....
2 INPUT
6 CHANNEL
ADDRESS
L.
CONTROL
ADDR ESS OUTPUTS
INTERNAL REFRESH
REOUEST LATCH OUTPUT
REFON
REFRESH ON OUTPUT
REFlfEll REFRESH REQUEST INPUT
RxCx
RC TIE POIN"!;
STARTCV START CYCLE OUTPUT
+5VSUPPLV
Vee
6·19
W
ADDRESS
OUTPUTS
(00 - (5 )
3222
ABSOLUTE MAXIMUM RATINGS·
*COMMENT
Stresses above those listed under '''Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Temperature Under Bias . . . . . . . . . . . . _65° to +125°C
Storage Temperature . . . . . . . . . . . . . . _65° to +160°C
All Input, Output or Supply Voltages . . . . -O.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . • . . . • . . . .. 100 mA
Power Dissipation • • . . . . . . . . . . . . . . . . . . . . . . 1 W
D.C. CHARACTERISTICS All Limits Apply for VCC = +5.DV ±5%, TA = DOC to +75°C.
Limits
Symbol
Min.
Typ)l]
Max.
Unit
Test Conditions
IFB
Input Load Current BUSY
0.40
1
mA
VIN = 0.45V
IFO
Input Load Current All Other Inputs
0.05
0.25
mA
VIN = 0.45V
IRB
Input Leakage Current BUSY
<1
50
J.lA
VIN = Vee
IRa
Input Leakage Current All Other Inputs
<1
20
J.lA
VIN = 5.25V
VeLAMP
Input Clamp Voltage
-0.76
-1
V
Ie = -5.0mA
0.8
V
Parameter
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
Icc
Power Supply Current
91
120
mA
Vee = 5.25V
Ise
Output High Short Circuit Current
-48
-70
mA
VOUT = OV
Vee = 5.25V
VOL
Output Low Voltage
0.32
0.45
V
IOL = 5mA
VOH
Output High Voltage (00.05)
2.6
3.1
V
IOH =-lmA
Vee = 4.75V
VOHl
Output High Voltage (All Other Outputs)
2.4
3.0
V
IOH = -lmA
Vee = 4.75V
Note 1:
2.0
V
Typical values are for TA = 25°C and nominal power supply voltages.
Symbol
Test
CIN (Address)
Input Capacitance
Limits (pF)
Typ.
Max.
5
10
Conditions
Vbias = 2.0V
CIN (CYREQ)
Input Capacitance
6
10
Vee = OV
CIN (BUSY)
I nput Capacitance
20
30
f = 1 MHz
Note 2:
This parameter is periodically sampled and is not 100% tested.
6·20
3222
A.C. Characteristics
All Limits Apply for Vee
= +5.0V ±5%, TA = o°C to
+75°C. Load
= 1 TTL, CL = 15pF.
Conditions of Test: Input pulse amplitude: 3V, Input rise and fall times: 5ns between 1 V and 2V. Measurements are made at 1.5V.
Symbol
Parameter
Typ.'
Max.
Unit
tAA
Address In to Address Out
7
12
ns
tBAM
BUSY In to Address Out
21
28
ns
tBAR
BUSY In to Counter Out
18
27
ns
tBK
BUSY In to ACK Out
14
20
ns
tBR
BUSY In to REFON Out
15
24
ns
tBS
BUSY In to STARTCY Out
4
7
14
ns
CYREO
tHOLD
BUSY Hold Time
50
ns
External Delay between STARTCY and
BUSY
tRH
CYREO or REFREO Hold Time
0
tRR
REFREO to REFON
tRRe
REFREO to REFON
tRS
CYREO or REFREO In to
----STARTCY Out
tSetup
BUSY Setup Time
Min.
Note 1: Typical values are for TA
=:
9
Conditions
BUSY
= VIH
REFREO
= VIH, CYREO = VIL
= VIL
ns
External Delay after BUSY
ns
CYR EO and BUSY = VIH, No priority
contention between REF R EO and
CYREO
45
ns
BUSY
21
ns
BUSY
= VIH
= VIH
ns
BUSY
= VIL
18
26
33
14
120
During Refresh
25°C and nominal power supply voltages.
A. SYSTEM MEMORY CYCLE
WITH MEMORY NOT BUSY
B. SYSTEM MEMORY CYCLE WITH MEMORY
BUSY (FOLLOWING REFRESH CYCLE)
(Numbers in parentheses are minimum values in ns unless otherwise specifiedJ
CYREO
V'H---+----++---------
V'H---+'-----t---+------AEFREO
AHREQ
(IN)
(IN)
STAR-fey
STAATCY
(OUT)
lOUT)
V,H-----;;;.;;.-".I
BUSY
(IN)
Vll--~'
V'H-------t--r--------I-f
FlEFON
(OUT)
ACK
(OUT)
V'H-------t-.....,....
REFON
(OUT)
-+-
V,H---++------.........,.I
ACK
V IL -
-
-
(OUT)
--
V'H----++--------------
V'H=t
V il
V'H
°0·°5
lOUT)
-'>.;:.,,------------tAA
'\
VIl---#-------------
1,2MAX) __________
~
ADDRESS
V'H----....... F.:::.;::::..-------(OUT) V1l-----'I"----------0 0 .0 5
ADDRESS
VIl _ _ _ _ _~\.,-----------
6-21
ADDRESS
3222
C. REFRESH MEMORY CYCLE WITH
MEMORY NOT BUSY
D. REFRESH MEMORY CYCLE WITH MEMORY
BUSY (FOLLOWING SYSTEM CYCLE)
(Numbers in parentheses are minimum values in ns unless otherwise specified.)
V,H
CYREO
liN)
V'l-
V,H - - - - - - - - - - - - - - - - - - - - -
-
--
-
CYREO
liN)
-
V'L-- - - - - -
V,H
REFREO
liN)
/
V,H- - - - - - , .
V 1L _
V,H--------..
V,H
STARTCY
lOUT)
V'L_
STARTCY
lOUT)
V,l -
i
__
V,H
BUSY
liN)
BUSY
liN)
V,l
V,l----...II
V,H
REFON
lOUT)
REFON
V1l _
lOUT)
V,l -
ACK
lOUT)
V,l
V,H
ACK
lOUT)
V,H
As-A.
liN)
V,H
As-As
liN)
V,l
V,l
tSAR
V,H
V,H
°0-°5
lOUT)
~
VOL
127 MAX)
AODRESS
lOUT)
V,l
NOTE 1: tRR (26m MAX) IF PRIORITY CONTENTION IS ELIMINATED; tARe
F. USE OF 3222 FOR REFRESH TIMING AND
CONTROL IN A 2104A SYSTEM
E. TYPICAL APPLICATION OF 3222 REFRESH
CONTROLLER IN A 2107C SYSTEM
2104A
MEMORY
DEVICES
P-
o -
L
_ _ _ _..... ~~g~ TIMING
ADDRESS
INPUTS
TO 21078
ARRAY
RAS ENABLE
LATCH
,......1.._-'-'--_---, ONLY ONE 3222 IS REQUIRED PER SYSTEM.
~
_ _ _ _ _---I
ADEQUATE BUFFEAING SHOULD BE PROVIDED
BETWEEN THE 3222 ADDRESSES lOo-Osl
OUTPUTS AND THE MEMORY INPUTS.
6-22
3222
PIN NAMES AND FUNCTIONS
Pin
No.
Pin
Name
Q
2
3
4
5-7
15-17
REFREQ
CYREQ
STARTCY
Ao-As
Function
Output of the internal Refresh Request latch. This pin may be connected to the Refresh Request input
(REFREQ) directly for asynchronous sequential mode refresh or
indirectly through control logic for
burst mode or synchronous mode
refresh (see text).
An externally generated signal
which the 3222 monitors to determine memory system status. If BUSY
is high the memory is not busy and a
system or refresh cycle may begin.
If BUSY is low the memory is being
accessed for a data 1/0 or refresh
cycle and no other cycle may begin.
19
REFON
The 3222 output which when low indicates the memory system is either
ready to begin or is in a refresh cycle
(Refresh On).
20
ACK
The 3222 output which when low indicates the memory system is
either ready to begin or is in a
system cycle (system cycle request
accepted and acknowledged).
22
Vee
+5 volt supply.
The block diagram shows the four main circuit categories of
the 3222. An explanation of the workings of each of these
categories is given in the Device Operation section from a
users point of view.
DEVICE OPERATION
Operation of the Intel® 3222 Refresh Controller is most
easily explained by considering five conditions presented
by the three input control lines Cycle Request (CYREQ),
Refresh Request (REFREQ), and System Busy (BUSY).
These conditions are:
Low order memory address outputs.
Du ring a system cycle these outputs
give the low order (Ao-As) address
of a memory access. During a
refresh cycle these outputs give the
refresh address (generated internal
to the 3222).
BUSY
Connection point for the RC network which determines the refresh
period for sequential refresh mode.
(See Refresh Control section).
Function
As shown in the pin configuration figure, the 3222 has as
inputs the six low order (Ao-A5) system addresses. These
addresses are internally multiplexed with six internally
generated refresh addresses. The output of these
multiplexers provide the six low order addresses to the
memory array.
Low order system address inputs.
These addresses are multiplexed to
the address output pins (60-05)
during a system cycle.
18
RX/CX
1. Providing a refresh timing oscillator.
2. Generating six bit refresh addresses.
3. Multiplexing refresh and system addresses to the six
low order address inputs (60"05)'
4. Providing control signals for both refresh and memory cycle accesses.
Output signal indicating to external
circuitry that a memory cycle
(system or refresh) is to begin. See
text for timing considerations for a
refresh cycle.
Ground.
21
FUNCTIONAL DESCRIPTION
System Memory Cycle Request input (active when low). The request
is honored only if the memory is not
presently executing a cycle (BUSY
high) and if a refresh request did not
occur first.
GROUND
Pin
Name
The Intel® 3222 performs the four basic functions of a
refresh controller by:
Refresh Request input (active when
low). The request is honored only if
the memory is not presently executing a cycle (BUSY high) and if a
system cycle request did not occur
first.
11
Pin
No.
1. System memory cycle request - memory not busy
(BUSV = High)
2. System memory cycle request - memory busy
(BUSY =Low)
3. Refresh cycle request - memory not busy
(BUSY = High)
4. Refresh cycle request - memory busy
(BUSY =Low)
5. Simultaneous system memory cycle and refresh cycle
requests.
Condition 5 is actually a subset of the four previous
conditions and is included for completeness.
As is implied in the five conditions, the response of the 3222
to both refresh and memory cycles is dependent on the
state of the BUSY input. The BUSY signal is generated
externally to the 3222 and, when low, defines the time when
the memory is performing a cycle (refresh or memory
access). It is important to assure that BUSY is low for the
entire memory cycle time. Interference may occur in
asynchronous memory systems if the BUSY input goes
high prematurely. (An asynchronous memory system is
one in which the refresh and memory cycle requests occur
independent of each other.)
6-23
3222
System Memory Cycle Request -
and tRRC (or tRR) time respectively. The low going edge of
STARTCY is used to set the external BUSY latch low. As in
the previous two cases, the BUSY input must remain low for
the entire cycle required by the memory. As in the previous
two cases, the low going BUSY drives the STARTCY output
high.
Memory Not Busy
This section details operation of the 3222when the memory
is not busy and a request for a system memory cycle is
made (See Figure A for timing sequences). The request for
a memory cycle is made by the CYREQ input going low. The
Start Cycle output STARTCY goes low at tRS after CYREQ.
STARTCY is used for two purposes:
Refresh Cycle - Memory Busy
For this condition, it is assumed that the previous cycle was
a system access cycle. Timing conditions forth is operation
are shown in Figure D. Here, the STARTCY input goes low
tBS after BUSY returns high from the previous cycle. As
before, REFON goes low tBR after BUSY goes high. After
tHOLD, relative to STARTCY, BUSY again goes low and
places the low order refresh addresses on the address
outputs (0 0-0 5) after tBAR time. Internal refresh timing is
performed in a manner identical to that described in
Refresh Cycle-Memory Not Busy section.
1. To set the external BUSY latch. (See Figure E.)
2. To initiate memory system timing (after appropriate
delay).
The required delay time depends on system configuration
and associated delay paths for both Chip Enable (2107B
input signal) and system addresses.
The low going BUSY input causes the internally generated
Start Cycle output to go high and the Acknowledge output
ACK to go low (after tBK time). The Acknowledge output
confirms that the requested system memory cycle has been
accepted by the 3222. Note that the cycle request input may
be returned to the high state when the BUSY input goes low.
However, at the designer's discretion, the cycle request line
may remain low until "just prior" to BUSYreturning high. (If
BUSY goes high before CYREQ goes high, another
memory access may inadvertently be started.)
Simultaneous Refresh and Memory System Cycle Request
The simultaneous request for a refresh and memory system
access is almost a certainty in asynchronous systems. It is,
therefore, necessary to have circuitry in any refresh
controller capable of resolving the attendent ambiguity with
minimum additional delay. The Intel® 3222 Refresh
Controller has just such a circuit. (All timing parameters
specified for asynchronous operation assume that a refresh
and memory system request can occur at the same time.) A
latch internal to the 3222 decides which signal (CYREQ or
REFREQ) it will accept if both occur simultaneously, and
conditions the other control circuits appropriately. If a
refresh cycle was accepted, REFON will go low at the
appropriate time. If a memory system access was accepted
then ACK will go low at the appropriate time.
When the memory is not busy and a cycle request has been
made, the low order system address delay through the 3222
is tAA nsec. When the 3222 is not busy, the low order system
addresses (Ao-A5) are gated through to the output (0 0-0 5)
independent of any other input.
System Memory Cycle Request -
Memory Busy
The major differences between a system memory cycle
request when the system is busy and when it is not busy (as
previously described) are:
Refresh Control
The 3222 controls both burst and distributed refresh modes.
The burst refresh mode requires that REFREQ be generated
externally to the 3222 since refresh is completed in 64
consecutive cycles every 2ms. A system requiring distributed refresh timing, however can be controlled either by the
3222 or by external circuitry. If refresh timing is to be
controlled by the 3222 the output IT is tied to the REFREQ
input. Timing is controlled by an oscillator internal to the
3222. The desired refresh timing interval is determined by:
1. The Start Cycle outputS
==TA~R=T"'C"""Y does not go low until
tBS after the rising edge of the BUSY input. (Even
though the CYREQ input is lOw.)
2. Output add resses 00-05 change at or before tAA ti me if
the previous cycle was a system cycle request and
change at or before tBAM if the previous cycle was a
Refresh Cycle request. (Note that the longer delay is
after a refresh cycle.) See Figure B for definition of
terms.
Note that for a system memory cycle following a refresh
cycle, the refresh on output REFON goes high at or before
tBR relative to BUSY going high. Since the Acknowledge
output ACK can not go low until after tHOLD there is no
ambiguity between REFON and ACK. The memory is
always defined as being in a refresh cycle, system cycle or
no cycle.
Refresh Cycle -
1. tREF = .63 RxCx
r
Where:
tREF = the total time between refreshes (e.g. 2msec) in
msec.
r =the number of rows to be refreshed on the memory
device (for the 2107C r = 64),
Rx = external timing resistance in KO (3K to 10K)
C, = external timing capacitance in /Lf. (O.OOS/Lf to
0.02/Lf)
The 3222's oscillator stability is guaranteed to be ±2% for a
given part and ±6% from part to part, both over the ranges
O°C";; TA";; 7SoC and Vee = S.OV ±S%.
Memory Not Busy
Operation of the 3222 for a refresh request with the memory
not busy (see Figure C) is similar to a system cycle request
under the same condition. A refresh cycle is initiated
by the Refresh Request input (REFREQ) going low.
This low going input causes both the Start Cycle output,
STARTCY, and Refresh On output, REFON, to go low att
Figure F shows how the 3222 may be used to control refresh
in a 2104A system.
6-24
inter
3232
ADDRESS MULTIPLEXER AND REFRESH
COUNTER FOR 4K DYNAMIC RAMs
Input to Output Delay:
• Address
9ns Maximum Driving 15pF,
• Ideal for 2104A
• Simplifies System Design
•
• Reduces Package Count
• Standard 24-Pin DIP
•
25ns Maximum Driving 250pF
Suitable for Either Distributed or
Burst Refresh
Single Power Supply: +5 Volts ±10%
The I ntel® 3232 contains an address multiplexer and refresh counter for multiplexed address dynamic RAMs requiring refresh
of up to 6 input addresses (or 4K bits for 64 x 640rganization). It multiplexes twelve bits of system supplied address to six output
address pins. The device also contains a 6 bit refresh counter which is externally controlled so that either distributed or burst
refresh may be used. The high performance of the 3232 makes it especially suitable for use with high speed N-channel RAMs
like the 2104A.
The 3232 operates from a single +5 volt power supply and is specified for operation over a 0 to +75°C ambient temperature
range.
lOGIC DIAGRAM
PIN CONFIGURATION
COUNT
2'
Vee
REFRESH ENABLE
23
ROW ENABLE
2,
A,
~' <>--t=;=::::t=====:(:J
All
I
A,
A,
3232
As
A,
A,
A.
°0
0,
0,
0.
0;
~
GND
I
AlO
Ao
'2
TOTAL I
I
I
ARE ROW ADDRESSES.
A6 THROUGH All ARE COLUMN ADDRESSES.
TRUTH TABLE AND DEFINITIONS:
REFRESH
ENABLE
ROW
REFRESH
ROW
ENABLE
ENABLE
H
X
L
H
L
L
COi:iNT -
ENABLE
OUTPUT
REFRESH ADDRESS
(FROM INTERNAL COUNTER)
ROW ADDRESS
(Ao THROUGH A5)
COLUMN ADDRESS
(Ae THROUGH All)
OOUNT<>------~
ADVANCES INTERNAL REFRESH COUNTER.
ZERO DETECT -INDICATESA ZERO IN THE REFRESH ADDRESS
(USEe IN BURST REFRESH MODE).
6-25
6
fTOTAl
ZERO DETECT
Ao THROUGH As
NOTE:
All < > - - - r = = = ; : = = = = = = t J
A,
A,
6 TOTAL
6 TOTAL
I
I
I
6
I
TOTAL I
,
I
-:-
3232
ABSOLUTE MAXIMUM RATINGS·
·COMMENT:
Temperature Under Bias .............. -65° to +125°C
Storage Temperature ................. -65° to +160"C
All Input, Output, or
Supply Voltages .................... -0.5V to +7 Volts
Output Currents .............................. 100mA
Power Dissipation ................................ 1W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
All Limits Apply for Vee = 5.0V ±10%, TA = O°C to
+ 75°C
LIMITS
TYP.(1)
MAX.
-0.04
-0.25
mA
V IN
0.45V
0
10
p,A
V IN
5.5V
0.8
V
V
0.40
V
10L
5mA
V
10H
1mA
V
10H
=-1mA
SYMBOL
PARAMETER
IF
Input Load Current
IR
Input Leakage Current
V IH
VIL
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage (0 0-05)
2.8
4.0
VOHI
Output High Voltage
(zero Detect)
2.4
3.3
lee
Power Supply Current
Note 1.
MIN.
2.0
Input Low Voltage
0.25
100
Typical values are for T A ~ 25°e and Vee ~ 5.0V.
6-26
150
UNIT
mA
TEST CONDITIONS
Vee
5.5V
3232
A.C. CHARACTERISTICS
All Limits Apply for Vee
= +5.0V ±10%, T A = O"C to 75°C,
Load
= 1 TTL,
PARAMETER
tAO
Address Input to Output Delay
t AOI
Address Input to Output Delay
too
Row Enable to Output Delay
tOOl
Row Enable to Output Delay
TYP!I)
= 250pF,
Unless Otherwise Specified.
MAX.
UNIT
6
9
ns
CONDITIONS
Refresh Enable
16
25
ns
Refresh Enable
7
12
Refresh Enable
28
27
41
ns
12
ns
Refresh Enable
27
45
ns
Note 1, 2
60
ns
ns
Refresh Enable
80
ns
Refresh Enable
MIN.
SYMBOL
CL
tEO
Refresh Enable to Output Delay
7
14
tEal
Refresh Enable to Output Delay
12
teo
Count to Output
15
30
40
teOI
Count to Output
20
55
fe
tepw
Counting Frequency
5
Count Pulse Width
35
tez
Count to Zero Detect
15
= Low(lll21
= Low
= LOWIIII21
= Low
= Highlll12)
= High
MHz
ns
70
ns
Note 2
Note 1: Vee = 5.0V, T A = 25°e
2: Cl = 15pF
A.C. TIMING WAVEFORMS (Typically used with 2104A)
NORMAL CYCLE
V,H
ROW ENABLE
1.5V
V,l
V ,H
.... ·Al1
V,l
'00
V OH
110 .11.
ROW ADDRESS
COLUMN ADOR ESS
VOL
REFRESH
~---------------------------
ENABLE
V,l - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
REFRESH CYCLE
V,H
f'·5V
REFRESH
ENABLE
V,l--..J
V,H
---+-------------.. .,
V IL - - - -
VOH - - - - - - . . )
2.4V
ADDRESS
VOl-----J
VoH
1\
'.5V -I.l.---'
________________
REFRESH ADDRESS
REFRESH ADDRESS
O.8V
,-------------------1h
1\ '.5V
VOl - - - - - - - - - - - - - - - - - - - - - - - __ .lo..._ _ _ _ _ _ _ _ _ __
6-27
3232
PIN NAMES AND FUNCTIONS
Pin.
Pin
No.
Name
Function
inputs. The truth table on page 1 shows the levels required
to multiplex to the output:
Count Input
Active low input increments
internal six bit counter by
one for each count pulse in.
2
Refresh Enable
Input
Active high input which
determines whether the
3232 is in refresh mode (H)
or address enable (L).
7,3,5,18,
20,22
Ao-A, Inputs
Row Address inputs.
8.4,6,17,
19,21
A,-A ll Inputs
Column address inputs.
9,11,10,
16,15,14
0 0-0,
Address outputs to memories. Inverted with respect
to address inputs.
Outputs
12
GND
Power supply ground.
13
Zero Detect
Output
Active low output which
senses that all six bits of
refresh address in the counter are zero. Can be used in
the burst mode to sense
refresh completion.
23
Row Enable
Input
High input selects row, low
input selects column addresses of the driven memories.
24
Vee
+5V power supply input.
1. Refresh addresses (from internal counter)
2. Row addresses (Ao through As)
3. Column addresses (A. through All)
Burst Refresh Mode
When refresh is requested, the refresh enable input is high.
This input is ANDed with the 6 outputs of the internal 6 bit
counter. At each Count pulse the counter increments by
one, sequencing the outputs (0 0 -0 5) through all 64 row
addresses. When the counter sequences to all zeros, the
Zero Detect output goes low signaling the end ofthe refresh
sequence. Due to counter decoding spikes, the Zero Detect
output is va'lid only after tez following the low going edge of
Count.
Distributed Refresh Mode
In the distributed refresh mode, one row is selected for
refresh each (tREFRESH/n) time where n ~ number of rows in
the device and tREFRESH is the specified refresh rate for the
device. For the 2104A tREFRESH ~ 2msec and n ~ 64, there,
fore one row is refreshed each 31 Jl,sec. Following the refresh
cycle at row n x , the Count' input is pulsed, advancing the
refresh address by one row so that the next refresh cycle will
be performed on row n x +1' The Count input may be pulsed
following each refresh cycle or within the refresh cycle after
the specified memory device address hold time.
Rowand Column Address
All twelve system address lines are applied to the inputs of
the 3232. When Refresh Enable is low and Row Enable is
high, input addresses Ao-A5 are gated to the outputs and
applied to the driven memories. Conversely, when Row
Enable is low (with Refresh Enable still low), input
addresses A.-All are gated to the outputs and applied to the
driven memories.
DEVICE OPERATION
The Intel@3232 Address Multiplexer/Refresh Counter
performs the following functions:
Figure 1 shows a typical connection between the 3232 and
the 2104A 4K dynamic RAM. When the memory devices are
driven directly by the 3232, the address applied to the
memory devices is the inverse of the address at the 3232
inputs due to the inverted outputs of the 3232. This should
be remembered when checking out the memory system.
1. Row, Column and Refresh Address multiplexing
2. Address counting for burst or distributed refresh.
These functions are controlled by two signals: Refresh
Enable and Row Enable, both of which are active high TTL
Al1
I
A,
REFRESH
Os
>---
I
I
I
3232
>---
A,
A,
I
0.
I
I
I
2104A
A,
_J_
r---r-=I
I
I
A,
r----
A,
2104A
r-----r---:
I
~
ZERO DETECT
ENABLE
ROW
ENABLE
Figure 1. Typical Connection of 3232 and 2104 Memories.
6-28
I
2104A
3242
ADDRESS MULTIPLEXER AND REFRESH
COUNTER FOR 16K DYNAMIC RAMs
• Ideal For 2116
• Simplifies System Design
• Reduces Package Count
• Standard 28-Pin DIP
• Suitable For Either Distributed
• Single Power Supply:
+5 Volts ±10%
• Address Input to Output Delay:
9ns Driving 15 pF,
25ns Driving 250pF
Or Burst Refresh
The Intel® 3242 is an address multiplexer and refresh counter for multiplexed address dynamic RAMs requIring refresh of 64 or
128 cycles. It multiplexes 14 bits of system supplied address to 7 output address pins. The device also contains a 7 bit refresh
counter which is externally controlled so that either distributed or burst refresh may be used. The high performance of the 3242
makes it especially suitable for use with high speed N-channel RAMs like the 2116.
The 3242 operates from a single +5 volt power supply and is specified for operation over a 0 to +75°C ambient temperature
range. It is fabricated by means of Intel's highly reliable Schottky bipolar process and is packaged in a hermetically sealed 28
pin Type D package.
PIN CONFIGURATION
COUNT
Vee
RefRESH ENABLE
A,
ROW ENABLE
LOGIC DIAGRAM
A"
N.C.
o.
As
I
I
A,
A12
As
A4
A,
A"
As
A3
Ao
A10
A,
0.
°0
0;
0,
0..
0;
0,
GND
I
,.
TOTAL
I
I
00
ZERO DETECT
NOTE: Ao THROUGH A6 ARE ROW ADDRESSES.
A7 THROUGH A13 ARE COLUMN ADDRESSES.
TRUTH TABLE AND DEFINITIONS:
REFRESH
ENABLE
7 TOTAL
6 TOTAL
REFRESH
ENABLE
1---
ROW
ENABLE
x
L
f-----
OUTPUT
7
I TOTAL
I
I
I
7
I
TOTAL I
ROW
ENABLE ~-'''''~~'1..0~
REFRESH ADD~-
-~~~~6~~~:~~ ~~!}.~!!!:!L
b~~~~~°-i.~~'"~'"R~,!l,~:'----I
fA7 THROUGH A 13 )
COUNTO-------~
C5i}'N"T - ADVANCES INTERNAL REFRESH COUNTER.
ZERO DETECT INDICATES ZERO IN THE FIRST 6
SIGNIFICANT REFRESH COUNTER
BITS (USED IN BURST REFRESH MODE)
6-29
3242
A.C. Characteristics
= +5.0V
All Limits Apply for Vee
±10%, TA
= O°C to
75°C, Load
= 1 TTL,
C,
= 250pF,
Unless Otherwise Specified.
SYMBOL
PARAMETER
Typ.(l)
MAX.
UNIT
tAO
Address Input to Output Delay
6
9
ns
Refresh Enable = Low(2)(3)
t.\OI
Address Input to Output Delay
16
25
ns
Refresh Enable
MIN.
CONDITIONS
= Low
too
Row Enable to Output Delay
7
12
27
ns
Refresh Enable = Low(2)(3)
tOOl
Row Enable to Output Delay
12
28
41
ns
Refresh Enable
Notes 2, 3
----
= Low
t(:()
Refresh Enable to Output Delay
7
14
27
ns
hOI
Refresh Enable to Output Delay
12
30
45
ns
teo
Count to Output
15
40
60
ns
Refresh Enable = High(2)(3)
teOI
Count to Output
20
55
80
ns
Refresh Enable
5
MHz
70
ns
Ie
Counting Frequency
tcP\\
Count Pulse Width
35
lez
Count to Zero Detect
15
Notes: 1. Typical values are for TA
=
25°e and Vee
=
= High
ns
Note 3
5.0V.
2. TA = 25°e, Vee = 5.0V.
3. eL = 15 pF.
A.C. TIMING WAVEFORMS (Typically used with 2116)
NORMAL CYCLE
ROW ENABLE
,H
V
V IL
"'----------"r
-----'1-i,.5V
~--------------
:::==t=~='t::~===:=to=o~====
VOH---------~--------------~~--------DON'T CARE
) 2.4V
)
ROW ADDRESS
O.BV
COLUMN ADDRESS
~l---------~~~-----------~----------
REFRESH
ENABLE
~--------------------------V,, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
REFRESH CYCLE
REFRESH
ENABLE
V,"
II
\'----
~1.5V
V 1L
'
:: -tn --
1-
I
n
-
-
m~'"~
tcpw
-IJ
~~---------
f--- t eo ---
f-- t Eo __
~H-----'~~~2~.4V~----------+---~~c-------'X~-ADDRESS
REFRESH ADDRESS
REFRESH ADDRESS
~l-----~~O~.BV~------------+_--L~------~~--
": :__ ______ __ ______ __mL: 1~1.5_V
6-30
______
3242
Absolute Maximum Ratings*
'COMMENT:
Temperature Under Bias ........... ....
-10° to +85°C
Storage Temperature ................. -65° to +150° C
All Input, Output, or
Supply Voltages .................... -0.5V to +7 Volts
Output Currents .............................. 100mA
Power Dissipation ................................ lW
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. and Operating Characteristics
All Limits Apply for Vee
= 5.0V ±10%, T = 0° C to + 75° C
A
SYMBOL
PARAMETER
MIN.
IF
Input Load Current
IR
Input Leakage Current
VIH
Input High Voltage
LIMITS
TYP.(1)
MAX.
-0.04
-0.25
mA
VIS - 0.45V, Note 2
0.01
10
f.1.A
VI'
5.5V
8mA
V
2.0
VII.
Input Low Voltage
VOL
Output Low Voltage
VOH
Output High Voltage (00-06)
3.0
4.0
VOHI
Output High Voltage
(Zero Detect)
2.4
3.3
Icc
Power Supply Current
0.25
-
TEST CONDITIONS
UNIT
105
0.8
V
0.40
V
IOL
V
IOH
V
10H = -lmA
165
mA
Vee
Notes: 1. Typical values are for TA = 25°e and Vee = 5.0V.
2. Inputs are high impedance, TTL compatible, and suitable for bus operation.
Packaging Information
28 LEAD HERMETIC DUAL IN-LINE PACKAGE
TYPE D
1.470 137.3381
1-'- - - 1 . 4 3 0 136.3221~
C
---~PIN11
.530 113.4621
.510 112.9541
~
---
.625
Lm?-:::_~--;----T.180
.230
SEATING MAX.15.8421
PLANE
.100tI2.5401
MIN.
1.!.Q 12.794).....j
.090 12.286)
i
U~
I--
____
---
~
L II
__
_
14.5721
.140 13.5561
t015MIN
.065 11.651)
(0.381)·
.040 11.016)032 TVP - . --.023 10.584)
. 10.831)
.014 10.356)
6-31
lmA
5.5V
3242
2. Row addresses (Ao through As).
3. Column addresses (A7 through-A13).
PIN NAMES AND FUNCTIONS
Pin
No.
Pin
Name
Function
Count
Input*
Active low input increments internal 7bit counter by one for each count pulse
in.
2
Refresh
Enable
Input*
Active high input which determines
whether the 3242 is in refresh mode (H)
or address enable (L).
9,5,7,21,
23,25,27
AO-A6
Inputs*
Row address inputs.
10,6,8,20, A7-A13 Column address inputs.
22,24,26 Inputs*
11,13,12, 00-06
18,17,16, Outputs
19
Address outputs to memories. Inverted
with respect to address inputs.
14
GND
Power supply ground.
15
Zero
Detect
Output
Active low output which senses that the
six low order bits of refresh address in
the counter are zero. Can be used in the
burst mode to sense refresh completion.
3
Row
Enable
Input*
High input selects row, low input selects
column addresses of the driven memo·
ries.
28
Vee
+5V power supply input.
Burst Refresh Mode
When refresh is requested, the refresh enable input is high.
This input is ANDed with the seven outputs of the internal
7-bit counter. At each Count pulse the counter increments by
one, sequencing the outputs (00-06) through 128 row addresses. When the first six significant bits of the counter
sequence to all zeros, the Zero Detect output goes low,
signaling the end of the refresh sequence. Due to counter decoding spikes, the Zero Detect output is valid only after tez
following the low-going edge of COi:irit. The Zero Detect output used in this manner signals the completion of 64 refresh
cycles. To use the 128-cycle burst refresh mode, an external
flip-flop must be driven by the Zero Detect.
Distributed Refresh Mode
"The inputs are high impedance, TTL compatible, and suitable for bus
In the distributed refresh mode, one row is selected for refresh
each (tREFRESH/n) time where n = number of refresh cycles
required for the device and tREFRESH is the specified refresh
rate for the device. For the 2116 tREFRESH = 2 msec and n =
128 or 64, therefore, one row is refreshed each 15.5 or 31
psec, respectively. Following the refresh cycle at row n x , the
Count input is pulsed, advancing the refresh address by one
row so that the next refresh cycle will be performed on row
n x+1' The CoUrit input may be pulsed following each refresh
cycle or within the refresh cycle after the specified memory
device ad(jress hold time.
operation.
Rowand Column Address
DEVICE OPERATION
The Intel® 3242 Address Multiplexer/Refresh Counter per·
forms the following functions:
1. Row, Column and Refresh Address multiplexing.
2. Address Counting for burst or distributed refresh.
These functions are controlled by two signals: Refresh Enable
and Row Enable, both of which are active high TTL inputs.
The truth table on page 1 shows' the levels required to multiplex to the output:
1. Refresh addresses (from internal counter).
An
a,
A,
00
Ao
All 14 system address lines are applied to the inputs of the
3242. When Refresh Enable is low and Row Enable is high,
input addresses' Ao-A6 are gated to the outputs and applied to
the driven memories. Conversely, when Row Enable is low
(with Refresh Enable still low), input addresses A7-A13 are
gated to the outputs and applied to the driven memories.
Figure 1 shows a typical connection between the 3242 and the
2116 16K dynamic RAM. When the memory devices are
driven directly by the 3242, the address applied to the memory devices is the inverse of the address at the 3242 inputs due
to the inverted outputs of the 3242. This should be remembered when checking out the memory system.
2116
2116
3242
A,
A,
Ao
Ao
REFRESH
ENABLE
ROW
ENABLE
ClWJ'IT
Figure 1. Typical Connection of 3242 and 2116 Memories.
6-32
2116
Ao
inter
3245
QUAD TTL-TO-MOS DRIVER
FOR 4K N-CHANNEL MOS RAMs
Compatible with 4K RAMs
• Fully
Without Requiring Extra Supply
•
•
Density - Four Drivers in
• High
One Package
• TTL and DTL Compatible Inputs
• CerDIP Package - 16 Pin DIP
+5 and +12 Volt Supplies
• Only
Required
or External Devices
High Speed, 32 nsec Max. Delay + Transition Time
Low Power - 75mW Typical
Per Channel
The Intel® 3245 is a Quad Bipolar-to-MOS driver which accepts TTL and DTL input signals. It provides
high output current and voltage suitable for driving the clock inputs of N·channel MOS memories such as
the 21 07B. The circuit operates from two power supplies which are 5 and 12 volts. Input and output clamp
diodes minimize line reflections.
The device features two common enable inputs, a refresh select input, and a clock control input for
simplified system designs. The internal gating structure of the 3245 eliminates gating delays and minimizes package count.
The 3245 is fabricated by means of Intel's highly reliable Schottky bipolar process and is specified for
operation over a to +75° C ambient temperature range.
a
LOGIC DIAGRAM
PIN CONFIGURATION
E-, - - - - - - - - ,
E;-----0,
R--
PIN NAMES
'1-'4
SELECT INPUTS
0,-°4
DRIVER OUTPUTS
E1
ENABLE INPUTS
Vee
+5V POWER SUPPLY
R
REFRESH SELECT INPUT
Voo
+12V POWER SUPPLY
C
CLOCK CONTROL INPUT
NC
NOT CONNECTED
,E 2
6·33
3245
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . _10°C to 85°C
Storage Temperature . . . . . . . . . . . . _65°C to +150°C
Supply Voltage, Vee . . . . . . . . . . . . . . -0.5 to +7V
Supply Voltage, V DD . . . . . . . . . . . . . . -0.5 to +14V
All Input Voltages . . . . . . . . . . . . . . . . -1.0toVDD
Outputs for Clock Driver ......... -1.0 to V DD +1 V
Power Dissipation at 25°C. . . . . . . . . . . . . . . .. 2W
*COMMENT: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS
TA = o°c to 75°C, Vee =5.0V ±5%, VDD = 12V ±5%
Symbol
Min.
Parameter
Max.
Unit
Test Conditions
IFD
Input Load Current, 1,,1 2,1 3,1 4
-0.25
mA
VF = 0.45V
IFE
I nput Load Current, R, C, E" E2
-1.0
mA
VF = 0.45V
IRD
Data Input Leakage Current
10
jJ.A
VR = 5.0V
IRE
Enable I nput Leakage Cu rrent
40
jJ.A
V R = 5.0V
VOL
Output Low Voltage
0.45
V
V
IOl = 5mA, VIH = 2V
IOl - -5mA
VOH
Output High Voltage
VDD+l.0
V
V
IOH = -lmA, Vil = 0.8V
IOH - 5mA
Vil
Input Low Voltage, All Inputs
0.8
V
VIH
Input High Voltage, All Inputs
-1.0
VDD -0.50
-
V
2
POWER SUPPLY CURRENT DRAIN AND POWER DISSIPATION
Symbol
Test Conditions - I nput states to
ensure the following output states:
Additional Test
Conditions
Parameter
Typ.
Max.
Unit
Icc
Current from Vee
23
30
mA
IDD
Current from V DD
19
26
mA
PD1
Power Dissipation
365
485
mW
Power Per Channel
91
121
mW
Vee = 5.25V
Icc
Current from Vee
29
39
mA
V DD = 12.6V
IDD
Current from VDD
12
15
mA
PD2
Power Dissipation
300
388
mW
Power Per Channel
75
97
mW
High
Low
6-34
3245
A.C. CHARACTERISTICS TA = 0 to 75°C, vcc = 5.0V ±5%, VDD = 12V ±5%
0
Parameter
Min.!1)
L+
Input to Output Delay
5
tDR
Delay Plus Rise Time
t+_
Input to Output Delay
tDF
Delay Plus Fall Time
tT
Output Transition Time
tDR
tDF
Symbol
TypJ2,4] MaxJ3]
Unit
Test Conditions
11
ns
20
ns
=0
RSERIES = 0
RSERIES = 0
RSERIES = 0
RSERIES = 20.11
RSERIES = 20.11
RSERIES = 20.11
32
7
3
ns
18
32
ns
17
25
ns
Delay Plus Rise Time
27
38
ns
Delay Plus Fall Time
25
38
ns
NOTES: 1. CL = 150pF }
2. CL = 200pF
3. CL = 250pF
10
These values represent a range of
total stray plus clock capacitance
for nine 4K RAMs.
RSERIES
A.C. CONDITIONS OF TEST
4. Typical values are measured at 25° C.
CAPACITANCE
* TA = 25°C
Test
Symbol
Typ. Max.
Input Pulse Amplitudes: 3.0V
Input Pulse Rise and Fall Times: 5 ns between
1 volt and 2 volts
Measurement Points: See Waveforms
Unit
CIN
Input Capacitance, 11,1 2 ,1 3 ,14
5
8
pF
CIN
Input Capacitance, R,C,E 1 ,E 2
8
12
pF
*This parameter is periodically sampled and is not 100% tested.
Condition of measurement is f = 1 MHz. Vbias = 2V, VCC=OV.
and TA = 25°C.
WAVEFORMS
VDD -
-
-
-
-
-
-
-
-
-1- - - - - - - - - - - - - - - - - - - --2.0V
I
INPUT _ _ _____
T
I··
1.5V
GND - -
-
1 5V
I
'
2.0V
_1- ~ -"-==-4-..!......-:-1_ _ _-'01'./0_ ~-, ____~ _L _ i___ t
+-----..!
~
I
I---'~R-I
T--I
- __ - - - --
TYPICAL CHARACTERISTICS
DELAY PLUS TRANSITION TIME
VSo LOAD CAPACITANCE
INPUT TO OUTPUT DELAY
VS. LOAD CAPACITANCE
40
40
30
30
---
20
10
o
o
100
200
300
I
~I
400
1
....
::::: ~
f----
'DF
-,;;
--
v
V
10
',.
500
20
100
600
200
300
400
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
6-35
500
3245
Typical System
Below is an example of a 64K x 18 bit memory system (each card is 16K x 18) employing the 3245 quad high voltage
driver for the chip enable inputs. A single 3245 package drives 16K x 9 bits. Ao through A" are 2107B addresses.
CARD 0
CARDe
CARD B
-
(9 21078'5)(ROW 4LI
CARD A
- ( 9 21078',)(ROW 4RI
CHIP ENABLE
CHIP ENABLE
(ROW 3LI
(ROW 3RI
CHIP ENABLE
CHIP ENABLE
(ROW 2LI
(ROW 2RI
CHIP ENABLE
CHIP ENABLE
(ROW'LI
(ROW'RI
CHIP ENABLE
n
CHIP ENABL..-u
SEETABlE1o---______________~E,~,
SEETABlE1o-------------------E~,
DRIVER,
Rs(fl
DRIVER 2 [RS[311
DRIVER,
RS(21
DR IVER 2 [RS(411
o---~r~[::::>---fff~-.JJ--"N'.,.---i
CHIP ENADLE
[ROW 2LI
O-~++.::.<:jf""......... ~__4:f=F~L.Jt--'V'VV---s CHIP ENABLE
~
(ROW' LI
TABLE 1.
CARD
A
B
C
D
.,
INPUTS
"
ENABLE M
ENABLE P
ENABLE M
ENABLE
ENABLE N
ENABLE P
ENABLE Q
ENABLE N
a
R
I--,\M~~
REFRESH
ENABLE
CHIP ENABLE
o-__.i--..!~Ljr--f===l-,/
o-______________
CHIP ENABLE
(ROW 2RI
DRIVER #2
OUTPUTS
CONNECTED IN
SIMILAR MANNER
R = 20n
.....::cCJ
7408
A14
A12
Au
GND
RS('I
RS(21
RS(31
ENABLE M
ENABLE N
A15
RS("I
REFRESH
ENABLE
ENABLE P
ENABLE
REFRESH
ENABLE
6·36
Q
inter
5235, 5235-1
QUAD TTL-TO-MOS DRIVER
FOR 4K N-CHANNEL MOS RAMs
Technology for Very Low
• CMOS
Power: Suitable for Battery Backup
Density: Four Drivers in
• High
One Package
Gating Structure
• Internal
Minimizes Package Count
• TTL and DTL Compatible Inputs
• CerDIP Package: 16 Pin DIP
One Power Supply Required,
• Only
+12V (±10%)
The Intel® 5235 and 5235-1 are Low Power Quad TTL-to-MOS drivers which accept TTL and DTL input levels. They provide
high output current and voltage suitable for driving the clock inputs of N-channel MaS memories such as the 21 07 A or 2107C.
The circuit operates from a single 12 volt power supply.
The device features two common enable inputs, a refresh select input, and a clock control input for simplified system design.
The 5235-1 is a selection of the 5235 and is guaranteed for 95ns maximum delay plus transition time while driving a 250pF load.
The Intel ion-implanted, silicon gate Complementary MaS (CMOS) proces$ allows the design and production of very low
power drivers.
6·37
5235, 5235-1
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Temperature Under Bias ........... -10°C to 80°C
Storage Temperature ........... -65°C to +150°C
Supply Voltage, Voo . . . . . . . . . . . .. -0.5 to +14V
All Input Voltages ......... " -0.5 to (Voo+0.5V)
Outputs for Clock Driver ...... -0.5 to (Voo+0.5V)
Power Dissipation at 25°C . . . . . . . . . . . . . . . . 1W
D.C. CHARACTERISTICS
TA = o°c to 70°C, Voo = 12V ±10%.
Min.
Typ.!l]
Input Load Current
VOL
Output Low Voltage
-1.0
VOH
Output High Voltage
VIL
Input Low Voltage, All Inputs
Symbol
Parameter
Ilul
Max.
Unit
0.1
10
/.LA
0.15
-0.15
0.4
V
V
IOL = 5mA
IOL - -5mA
V
V
IOH = -5mA
IOH - 5mA
Voo-O.4 Voo-0.15
Voo +O·15 Voo+O·5
0.8
V
Test Conditions
VIN = .;;c.4V or ;;;'2.4V
VIH
Input High Voltage, All Inputs
1000
Supply Current
1.0
2.0
mA
f = OMHz
10D1
Supply Current
12
20
mA
f = 1MHz
(See
Figure 1)
2.0
V
Voo=13.2V
VIN~.4Vor
VIN;;;'2.4V,
CL = Opf.
Notel: Typical values are at 25° C and nominal voltage.
TYPICAL CHARACTERISTICS
Figure 1.
POWER SUPPLY CURRENT VS. FREQUENCY
(ALL 4 CHANNELS SWITCHING)
40
Figure 2.
DELAY PLUS TRANSITION TIME
VS. LOAD CAPACITANCE
100
GUA~ANTE~i
./'"
90
32
cl
1
24
c
c
6
8
o
'" Opf.
/
/;
./
-;::::::::. ~
0.1
0.2
80
".,../
70
0
0.5
I
/TYPICAL
(25' C)
60
1.0
5.0
2.0
50
10.0
o
100
f(MHz)
~
.9
70
300
.00
Figure 4.
DELA Y PLUS TRANSITION TIME
VS. INPUT VOLTAGE
90
90
I
200
LOAD CAPACITANCE (pF)
Figure 3.
DELAY PLUS TRANSITION TIME
VS. INPUT VOLTAGE
80
~ORtDF_
--
~
0.2
/
0.'
80
r---
t---..,
I
.P
0.6
70
602':-.0----=2':-.2---:2"'
.•---:2,L.6---,J2.8
0.8
6·38
5235, 5235·1
A.C. CHARACTERISTICS
TA = 0° to 70°C, VOO = 12V ±10%.
5235-1
Symbol
Min.!11 Typ.!2.41
Parameter
L+
Input to Output Delay
tOR
Delay Plus Rise Time
t+_
Input to Output Delay
tOF
Delay Plus Fall Time
tT
Transition Time
5235
Max.!31
55
20
75
20
95
55
20
10
95
20
40
Test
8
I 14 I pF I
'This parameter is periodically sampled and is not 100% tested.
Condition of measurement is f = 1 MHz, Vbias = 2V, VCC = OV,
and TA = 25°C.
t -
,
Unit
125
ns
70
ns
70
ns
95
125
ns
25
40
ns
Input Pulse Amplitudes: 2.0V
Input Pulse Rise and Fall Times: 5ns between
0.9 volt and 1.9 volts
Measurement Points: See Waveforms
5235
WAVEFORMS
voo - - - - - - - - - -
10
Max.!31
A.C. CONDITIONS OF TEST
Typ.! Max. ! Unit !
Input Capacitance
Typ.!2.41
95
20
75
NOTES: 1. CL = 150PF } These values represent a range of
total stray plus clock capacitance
2. CL = 200pF
3. CL = 250pF
for nine 4K RAMs.
4. Typical values are measured at 25"C, and nominal voltage.
I Symbol
I CIN
Min.!11
-r------"\
2.0V
INPUT
2.4V
O.4V - - -'-~--=-:J=:~==,:t::::::::-:::t==:::-::=-=-:::!
GN°---l1.5V
_ t OF -
6-39
5235, 5235-1
Typical System
Below is an example of a 64K x 18 bit memory system (each card is 16K x 18) employing the 5235 quad high voltage
driver for the chip enable inputs. A single 5235 package drives 16K x 9 bits. Ao through A11 are 2107B addresses.
CARD D
CARD C
CARD 8
-
(9 21078'5)(ROW 411
CARD A
-
(9 21078'5)-------(ROW 4RI
CHIP ENABLE
CHIP ENABLE
(ROW 311
(ROW 3RI
CHIP ENABLE
CHIP ENABLE
(ROW 211
(ROW 2RI
CHIP ENABLE
CHIP ENABLE
(ROW III
(ROW lRI
CHIP ENABLE
CHIP ENABLE
SEETABLE1~--_______________E_-,~,
SEETABlEl~----------------~E,~
DRIVER 1
RS(1)
DRIVER 2 [RS(311
~----T-'------t===!t-t--""'I\r----{ f:6~ E2~~SlE
R "" 20n
-=c-'
CHIP E-N-A-Sl-E o-______________
DRIVER #2
OUTPUTS
CONNECTED IN
SIMILAR MANNER
7408
A'4
A12
A'3
GND
RS(lI
RS(21
RS(31
ENABLE M
ENABLE N
A,S
RS(41
REFRESH
ENABLE P
ENABLE Q
ENABLE
REFRESH
ENABLE
6-40
-
.,~,
TELECOMMUNICATIONS
INTRODUCTION
The 2910 and 2911 Codecs (Coder-Decoder), are the first members of a family of advanced Telecom:
munication components. High density LSI fabrication techniques are used allowing sample and hold,
digital to analog converter, and comparitors to be integrated on a single chip along with digital logic
necessary to interface a full duplex PCM (Pulse Code Modulation) link. The primary applications are
in telephone systems for the transmission, switching and concentration of voice communications in
PCM systems.
TABLE OF CONTENTS
2910 PCM CODEC - J.lLAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
2911PCMCODEC-ALAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .' . . . . . . . . . . . . . . . 7-14
7-2
2910
PCM CODEC· fLLAW
8 BIT COMPANDED AID AND DIA CONVERTER
• Per Channel, Single Chip Codec
• 't5% Power Supplies: +12V, +5V, -5V
• CCITT G711 & G733 Compatible.
A TT T1 and T1/C Compatible with
8th Bit Signaling
• On-Chip Voltage Reference
• Low Power Consumption 300 mW.
Standby Power 120 mW
• Microcomputer Interface with On-Chip
Time-Slot Computation
• All Digital Inputs and Outputs TTL
Compatible.
• 78db Dynamic Range, with Resolution
Equivalent to 12-Bit Linear Conversion
Around Zero
• Fabricated with Reliable N-Channel
MOS Process
The Intel® 2910 is a fully integrated PCM (Pulse Code Modulation) Codec (Coder-Decoder), fabricated with n-channel silicon
gate technology. The high density of integration allows the sample and hold circuits, the digital-to-analog converter, the
comparator and the successive approximation register to be integrated on the same chip, along with the logic necessary to
interface a full duplex PCM link and provide in-band signaling.
The primary applications are in telephone systems:
•
•
•
Transmission
Switching
Concentration
-
T1 Carrier (T1C compatible)
Digital PBX's and Central Office Switching Systems
Subscriber Carrier/Concentrators
The wide dynamic range of the 2910 (78 dB) and the minimal conversion time (30/.lsec minimum) make it an ideal product
for other applications, I ike:
•
•
Data Acquisition
Telemetry
•
•
Secure Communications Systems
Signal Processing Systems
BLOCK DIAGRAM
PIN CONFIGURATION
~
CAP1 x
CLKc
CAP2 x
Dc
VI\c
SIG x
GRDA
FS x
SIGR
Voo
DR
PDWN
V,,"
2910
VF~
@
AUTO
---11-----------""---,
~L---OL_L_~
CD CAP1x
@
VB.
AUTO
SIG~
®
CAP~x
@
0,
@
elK.
~
FS.
@
"
@
CLKx
..-:cc==-,---~
c==.,...----
FS R
CLKR
Vee
TS x
CAP1R
Dx
CAP2R
GRDD
@
SIGR_I--------------'
0,,,",""'"
7-3
GRCA GAOO vee
'-\:.c
\IoD
NC
@@@@0
®
CLKc
~
2.10
t-IN OESCRIPTION
Pin No.
Pin No_ Symbol
Symbol
Function
Hold
2
CAP1 x
CAP2 x
Connections for the transmit
holding capacitor. For an 8
kHz sampling system the capacitor should be 2000 pF,
20%, ceramic or polycarbonate.
3
VFx
Input
Analog input to be encoded
into a PCM word. The signal
on this lead is sampled at the
same rate as the transmit
frame synchronization pul.se
FSx, and the sample value is
held in the external capacitor
connected to the CAP1 X and
CAi'2x leads until the encoding process is completed.
13
14
Most significant bit of the encoded PCM word (+5V for
pOSitive, -5V for negative
value). Used as an internal
ground offset correction, by
integrating it through the input coupling capacitor. Refer
to the Codec interface section.
15
1
4
5
6
AUTO
GRDA
SIGR
OutPl)t
Ground
Output
Analog return common to the
transmit and receive analog
circuits. Not connected to
GRDD internally. The exter·
nal connection to GRDD
should have a very low impedance.
7
VDD
Power
+12V, ±5%, referenced to
GRDD or GRDA, depending
upon system grounding considerations.
8
DR
Input
Receive PCM highway (serial
bus) interface. The Codec
serially receives a PCM word
(8 bits) through this lead at
the proper time defined by
FSR, CLKR, DC, and CLKe.
9
PDWN
Output
Normally low, this signal goes
high while the Codec is in the
power down mode. TTL interface, open drain output.
VFR
Output
Analog output. The voltage
present on VF R is the decoded value of the PCM word received on lead DR' This value
is held constant between tWo
conversions. For the dynam ic
range description, refer to the
Codec operation section, decoding paragraph.
10
Connections·.fOt. ti;~'·
holding capacitOr, For.
kHz sampling system,
capacitor should be 6do
20%, ceramic or polycarbonate.
GRDD
Ground
Ground return common to
the DC power supplies, optionally VBB, Vee, and VDD·
Ox
Output
Output of the transm it side
onto the send PCM h'ighway
(serial bus). The 8-bit PCM
word is serially sent out on
this pin at the proper time
defined by FSx, CLKx, Dc,
and CLKe. TTL three-state
output.
Output
Normally high, this signal
goes low while the Codec is
transmitting an 8-bit PCM
word on the Ox lead. (Timeslot information used for
diagnostic purposes and also
to gate the data on the 0 x
lead.) TTL interface, open
drain output.
Power
+5V, ±5%,
GRDD.
17
Input
Master receive clock defining
the bit rate on the receive
PCM
highway.
Typically
1.544 Mbps for a T1 carrier
system. Maximum rate 3.2
Mbps. 50% duty cycle. TTL
compatible.
18
Input
Frame synchronization pulse
for the receive PCM highway.
Maximum repetition rate 24
kHz. Also uSed to differentiate between non-signaling
frames and signaling frames
for the receive side. For functional description, refer to
the Codec operation section,
Codec control and signaling
paragraph. TTL interface.
Input
Master transmit clock defining the bit rate on the transmit PCM highway. Typically
1.544 Mbps for a T1 carrier
system. Maximum rate 3.2
Mbps. 50% duty cycle. TTL
interface.
16
Signaling output. SIGR is updated with the 8th bit of the
receive PCM word on signaling frames, and is latched between two signaling frames.
TTL interface.
19
7-4
Function
Hold
11
12
Vee
CLKx
referenced
to
2910
Pin No. Symbol
20
21
FS x
SIGx
Function
Input
Input
Description
Pin No. Symbol
Frame synchronization pulse
for the transmit PCM high·
way. Maximum repetition
rate 24 kHz. Also used to
differentiate between nonsignaling frames and signaling
frames on the transmit side.
For functional description,
refer to the Codec operation
section, Codec control and
signaling paragraphs. TTL interface.
Function
Description .
22
VBB
Power
-5V, ±5%, referenced to
GRDD or GRDA, dependIng
upon system grounding considerations.
23
DC
Input
Data input to program the
Codec for the chosen mode
of operation. For functional
descri ption, see the Codec
operation section, Codec con·
trol paragraph. TTL interface.
24
CLKC
Input
Clock input to clock in the
data on the DC lead in order
to define the mode of operation of the Codec. Maximum
rate 1.6 Mbps. For functional
description, refer to the
Codec
operation
section,
Codec control
paragraph.
TTL interface.
Signaling input. This digital
input is transmitted as the
8th bit of the PCM word on
the Ox lead, on signaling
frames. TTL interface.
FUNCTIONAL DESCRIPTION
chronous (transmission) or synchronous (switching) with
each other.
The 2910 PCM Codec provides the analog-to-digital and the
digital-to-analog conversions necessary to interface a full
duplex (4 wires) voice telepbone circuit with the PCM highways of a time division multiplexed (TOM) system.
On a signaling frame, the Codec transmit side will encode
the incoming analog signal as previously described and
substitute the signal present on lead SIGx for the least
significant bit of the encoded PCM word. Similarly, on a
receive signaling frame, the Codec will decode the 7 most
significant bits according to the CCITT G733 recommendation and will output the least significant bit value on the
SIGR lead until the next signaling frame. Signaling frames
on the send and receive sides are independent of each other.
In a typical telephone system the Codec is used between
the PCM highways and the line filters.
The Codec provides two major functions:
•
Encoding and decoding of analog signals (voice and
call progress tones)
•
Encoding and decoding of the signaling and supervision information
The 2910 Codec is intended to be used on line and trunk
terminations. The call progress tones (dial tone, busy tone,
ring-back tone, re-order tone), and the pre-recorded announcements, can be sent through the voice-path, while
signaling (off hook and disconnect supervision, rotary dial
pulses, ring control) is sent through the signaling path.
On a non-signaling frame, the Codec encodes the incoming
analog signal at the frame rate (FS x ) into an 8-bit PCM
word which is sent out on the Ox lead at the proper time.
Similarly, on a non-signaling frame of the receive link, the
Codec fetches an 8-bit PCM word from the receive highway
(DR lead) and decodes an analog value which will remain
constant on lead VFR until the next receive frame. Transmit and receive frames are independent. They can be asyn-
r
Circuitry is provided' within the Codec to internally define
the transmit and receive time-slots in order to minimize the
common equipment. This feature can be bypassed and
discrete time-slots sent to each Codec within a system.
In the power-down mode, most functions of the Codec are
disabled to reduce power dissipation to a minimum.
PABX Ie 0
SWITCHING SYSTEM ID3 CHANNEL BANK
TELEPHONE seT
I
I
L __ _
TYPICAL
LINE
TERMINATION
7-5
2910
The last 6 bits of the contro('w~fd.-
assignment, from 000000 (time-slott},
64).
CODEC OPERATION
Codec Control
The operation of the 2910 is defined by serially loading an
8-bit word through the Dc lead (data) and the ClKC lead
(clock). The loading is asynGhronous with the other operations of the Codec, and takes place whenever transitions
occur on the ClKC lead. The Dc input is loaded in during
the trailing edge of the ClKc input.
Bit 3 is the most significant bit and bit 8 the-Illast ,si
cant and last into the Codec.
"
CLKC _ _ _..J
Mode
Bit 3 ......... 8
0
0
0
1
1
0
X&R
X
R
,
, ,,,,
1
,
Standby
000 000
o0 0 o0
:
1
Time Slot"
1
2
:
64
The clocking of a full control word (8 bits) has to take
place in less time than the frame duration (elapsed time
between two FS x or FS R pulses). The Codec will load its
transmit and/or receive time-slot control registers with the
occurrence of the second FS (X or R) pulse following a
transition on the ClKC lead. The ClKc should be deactivated during transmission time slots.
The control word contains two fields:
Bit 1 and bit 2 define whether the subsequent 6 bits apply
to both the transmit and receive side (00), the transmit side
only (01), the receive side only (10) or whether the Codec
should go into the standby, power-down mode (11). In the
latter case (11), the following 6 bits are irrelevant.
~<--
Bit 2
The Codec will retain the control word (or words) until a
new word is loaded in or until power is lost. This feature
allows to dynamically allocate the time·slots for switching
applications.
BITS
FSx __
Bit 1
_____--,n,-_____---,n,-_____---,rL
LOADING XMT
Cl~
________________~
LOAO\"~\
FS R
__
J1<--_____--'nL._____---'nL._____---'n'--__
Time-Slots
counts are reset by the FS (Xor R) pulse. Thus, there is
no need for external generation of the time-slot.
A time-slot is a group of eight adjacent clock pulses (X or
R) starting with a leading edge of the corresponding ClK
(X or R). Time·slot 1 begins with the next leading ClK (X
or R) edge following the leading edge of FS (X or R). The
time-slots are adjacent (i.e., there is no gap between two
consecutive time-slots).
2. Direct Control Mode
Each Codec is programmed for time-slot 1 (code
00000000 for the control word). A different FSx and
FSR pulse is sent to each Codec, staggered 8 clock
pulses apart. Each Codec will consider its time·slot to be
made of the 8 clock pulses beginning with the next leading ClK (X or R) edge following the leading edge of the
FS (X or R) pUlse. In the direct mode, there is a need to
externally generate a different FS x and a different FSR
pulse for each Codec. The ClKc lead is tied to ClKx
and the Dc lead is held low for normal operation, and
high for power-down mode.
There are two options to run the system timing:
1. Microcomputer Controlled Mode
The same FSx and FSR pulses are sent to all Codecs in
the system. Each Codec is programmed for a different
time-slot. Each Codeccomputes its own time-slot,
counting down the ClK (X or R) pulses until there is a
lTIatch with the last 6 bits of the control word. The
7-6
2910
DIRECT MOD!;
MICROCOMPUTER CONTROL MODE
I
2910
LINE3
1-:91:-~ r---<
~ =r---<
I
r-~
LINE 3
CLKC DC
1T
1'"
r
r
LINE 2
r
r
;:: r---<
LINE 2
~
TT
1'"
LINE 1
~
CLKc DC
1= r-
LINE 1
CLKC DC
=
r-
T"1"
V
I
Ox DR
CLKR
elKx
FSx
FS.
CLKR FSR1 FSR2 FS.
Ox DR
CLKX FSx1 FSx2 FSx3
CLKc1 CL
DC
CLKc2
fetch a PCM word from the receive PCM highway during
time-slot 3.
Example
The two words 01000001 and 10000010 have been loaded
into the Codec. The transmit side is now programmed for
time-slot 2 and the receive side for time-slot 3. The Codec
will output a PCM word on the transmit PCM highway
Ibus) during the time-slot 2 of the transmit frame, and will
XMT TIME SLOT 1
FSx
CL.Ke
,,
,,
,
,
~--01000001--.1
XMT TIME SLOT 2
,
,
~--10000010--~,
XMT TIME SLOT 3
IN
elK" IN
~OUT
TS. OUT
Rev TIME SLOT 1
Fs"
Rev TIME SLOT 3
IN
,
PCM WORD CLOCKED IN
Encoding
-1
with the transmit time-slot and the conversion takes place
during the following frame (worst case conversion time is
15 time-slots). The PCM word is then output on the Dx
lead at the proper time-slot occurrence of the following
frame as described earlier (see Codec control paragraph).
The AID converter saturates at 3.04 volts.
The VF signal to be encoded is input on the VFx lead. An
internal switch samples the signal and the hold function is
performed by the external capacitor connected to the
CAP1x and CAP2x leads. The sampling is synchronized
11---o----- 193 X CLK. -------0-11
N.~~______~(2_4_C_HA_N_N_E_L~~~S~TE~M~)~~~~--~n"------------_ _~~~~~~--~~---------------------TIME SLOT 20 ~ f.TIME SLOT 20---1
D. ----- ----- ----- -- ------ ---- -- - -- --- - -- -- -{]--.- - -- -. ---------------~-------------------------,
I J AL
---0------ ----- -----N
~----------~~~~========~=--=~----------~~
7-7
~.
2910
Conversion Law
:. ,"'"
• ~..i:'"
...
CODEC TRANSFER CHARACTliRISTIC
The conversion law is commonly referred to as the p. Law
or the p. = 255 Law. Its mathematical expression is:
(S BITS CODING)
In (1+p.X)
In(1+p.)
y
-~~-~-3.09V
where X and Yare the normalized input and output of the
encoder and decoder and p. = 255.
········T
~'
./
.r
The Codec approximates the p. Law through 15 segments.
Each segment is made of 16 steps. In adjacent .segments,the
step sizes are in a ratio of two to one. Within each segment,
the step size is constant with the exception of the first segment where the first step is half the size of the other steps
in the segment.
-3.D4V
3.04V
There are two transfer characteristics: the first one for 8-bit
coding (non-signaling frame), the second one for 7-bit
coding (signaling frame).
For 8-bit coding, the output levels are midway between the
corresponding decision levels. The output levels Yn are
related to the input levels Xn by the expression:
Xn
+ Xn+1
2
O--j-- ------ -- -S---'-""'-A.-"-O..I--"''-A.:=''...I'-''''-'A:c''-''--'''-=,''-
__-".I-_ _ _ _ _ _ _ __
1
I
------------ ------ -----\-SIGx ------------ --- --- -----\-VFx
.
"
S!
~
,
en_ 7
FS X
i
: : ::: :::::: ::: ::: : : ::: ::: : : ::: : : : : ::: =:= : : r:::::::::::::::----+----------'<-f---
-----=====--=------==-------~I=:::j:::====-=----==-' =====~===t""--=:::::::::::===
CAPx _______~
_ _ __=~_ _ _ _=;i~=======V=F=x=H=O=L=D=T='M==E======~r::::::::::t:====~================~;;;
__
On the decoding side, when the FS R pulse is widened, the
8th bit of the PCM word is detected and transmitted on the
SIGR lead. That output is latched until the next receiving
signaling frame.
I"
TS1,
---'1
I-
The remainIng 7 bits are decoded according to the value
given in the conversion law section (CCITT G 733 recommendation) .
TSn,
•
1
r
TS1,
I-
TSn,
-----------j
CLKR~,JLJLJ1SLf1Jl..Js.fl...R..JTU'l.JL.JlSULJUl..
REC. SIGNAL FRAME
193
F~ S I
DR
SIG R
s-----..r-Ls- - - - - - - - -___
~:~~~::::::::=:::=::::=:::~::::::::=::=::~:~~~~~:~=~~:~~~~~~~:~:~~::~~~
?o
-'--------------*-(i--============*X
---------------:
: :
7-10
2910
Standby Mode - Power Down
The power consumption in the standby mode is .less than
120mW.
To minimize power consumption and dissipation in large
systems, a standby mode is provided by loading a control
word (Dc) with a "1" in bits 1 and 2 locations. Most of the
Codec functions thereby become disabled, with the excep·
tion of the interface to the DC and CLKc leads, to allow
the Codec to be reactivated.
VOLTAGE REFERENCE FOR THE D/A
CONVERSION
The voltage reference is generated on·board the chip and is
cal ibrated during the manufacturing process. The dynamic
range of the digital·to·analog converter is ±3.09 volts.
APPLICATION - LINE INTERFACE
Auto Zero
Grounding
Digital grounding is connected to the GRDD lead. It is the
common return for the digital signals.
The auto zero output (most significant bit or sign bit of the
AID conversion) integrated over a long time constant will
compensate for the DC offset inside the Codec (voltage
difference between the bottom of the DAC and GRDA).
The above drawing shows a possible connection between
the VF x and Auto leads.
Filters Interface
Attached is the schematic of the equivalent circuits of the
input and output of the Codec. Note that the output pulse
stream is of the non-return to zero type.
~'f-~f_--'V",f-va:HZ
SOOn.
47K
330
Analog grounding is connected to the GRDA lead. The
GRDA and GRDD lead are no: connected inside the 2910.
An external connection is thus necessary outside the Codec
to tie all the analog ground lines to the common return of
the system GRDD. That external connection has to have a
minimal impedance to avoid a DC offset in the Codec.
~~--~~--------~
~-----Oll!1F
7-11
2910
1I.4.t"l ..
~'44tJf '{;,
.~, ,11/'
ABSOLUTE MAXIMUM RATlNGS*
>_.
+,,_
'/r<~t,
'COMMENT: Stresses above those listed under ':f'b,plu
mum Ratings" may cause permanent damage to the de)l)ce<
Temperature Under Bias ............. _40°C to +80°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Supply Voltage with Respect to Vss ..... -0.5V to +14V
All Input Voltages . . . . . . . . . . . . . -0.5V to (Voo + 1V)
Outputs . . . . . . . . . . . . . . . . . . . . . .-lV to (Voo + lV)
Power Dissipation, . . . . . . . . . . . . . . . . . . . . . . 1.35W
stress rating only and functional operation of the device'-:a.t'.t'
any other conditions above those indicated in the operatioh-qJ;Se.e~,>
tions of this specification is not implied. Exposure to absolute ni~,7"
mum rating conditions for extended periods may affect device'
reliability.
DC AND OPERATING CHARACTERISTICS
T A = O°C to +70°C, Voo = +12V, Vcc = 5V, VBB = -5V
DIGITAL INTERFACE
Symbol
Parameter
Min.
Limits
Typ.
Max.
Unit
Test Conditions
IlL
Low Level I nput Current
10
fJ.A
VIN
IIH
High Level Input Current
10
fJ.A
VIN
VIL
Input Low Voltage
+0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
< VIL
> VIH
V
+2.0
0.4
2.4
V
10L = 10 mA on D x , 2.0 mA on SIGR,
6.4 mA on TSx
V
10H = 0.6 mA on SIG R, 30 mA on Dx
ANALOG INTERFACE
AIL
Input Leakage when Sampling
AIZ
Input Impedance when Sampling
Aoz
Output Impedance
AOR
Dynamic Range
1
1.8
2.0
-3.09
fJ.A
-3.lV
< VIN < 3.lV
500
n
In series with CAP x to GRD
2.2
kn
User provided VF R pull-down to VBB
+3.09
V
POWER DISSIPATION
1000
Standby Current
TBD
mA
Icco
Standby Current
TBD
mA
Voo = +12, +10%
IBBO
Standby Current
TBD
mA
Vcc = 5.0, +10%
1001
Operating Current
14
mA
Clocking Frequency
Icci
Operating Current
18
mA
X & R = 1.544 Mbps
IBBI
Operating Current
5
mA
VBB = -5_0, -10%
7·12
2910
TIMING SPECIFICATION
TRANSMIT SECTION
~;
Symbol
Parameter
Min
tCY
Clock Period (2.048 MHz Systems)
485
t,. tf
Clock Rise and Fall Time
tClK
Clock Pulse Width
Max
Unit
'::
: . ,S
Comments
ns
30
ns
230
ns
NOMinal 50% duty cycle
Increase by 0.1 ms/pF below 500 pF
tos
New Data Setup
25
ns
tOHx
Data Hold Time
75
ns
tHZX
Data Float on TS Exit
75
205
ns
tSOFF
Time Slot X to Disable
70
185
ns
tozx
D 2911 is a fully integrated PCM (Pulse Code Modulation) Codec (Coder-Decoder). fabricated with N-channel
silicon gate technology. The high density of integration allows the sample and hold circuits. the digital-to-analog
converter. the comparator and the successive approximation register to be integrated on the same chip. along with the
logic necessary to interface a full duplex PCM link.
The primary applications are in telephone systems:
• Transmission
• Switching
• Concentration
- 30/32 Channel Systems at 2.048 Mbps
- Digital PBX's and Central Office Switching Systems
- Subscriber Carrier/Concentrators
The wide dynamic range of the2911 (66 dB) and the minimal conversion time (40 IJsec minimum) make it an ideal product
for other applications. like:
• Secure Communications Systems
• Signal Processing Systems
• Data Acquisition
• Telemetry
BLOCK DIAGRAM
PIN CONFIGURATION
TRANSMIT SECTION
MO
o@
CAP1X
22
ClKC
CAP2 X
21
De
VFX
20
VBB
AUTO
19
FSx
GADA
18
CLKX
17
FSR
ClKR
2911
VDD
DR
16
POWN
15
Vee
VFR
"
TSx
CAP1R
10
Ox
CAP2R
11
GROD
CD
®
VFx~~:::::j
AUTO . .
x
CAPl
CAP2x
Ti;@l
=+:==1
Ok
CLKx
GAOA GfIJD
vas ICc VDo
® @ ® @ ®
o
7-14
PIN NUMIllER
@l
@I
'-r-..---r--fI~Fs,""
2911
PIN DESCRIPTION
Pin No. Symbol
Function
Description
Pin No. Symbol
Function
DescrlpUon
1
2
CAP1x
CAP2x
Hold
Connections for the transmit holding capacitor. For
an 8 kHz sampling system
the capacitor should be
2000 pF. 20%.
10
11
CAP1 R
CAP2R
Hold
Connections for the re--'
ceive holding capacitor.
For an 8 kHz sampling system, the capacitor should
be 400 pF, 20%.
3
VFx
Input
Analog input to be encoded
into a PCM word. The signal on this lead is sampled
at the same rate as the
transmit frame synchronization pulse FSx. and the
sample value is held in the
external capacitor connected to the CAP1x and
CAP2x leads until the encoding process is completed.
12
GRDD
Ground
Ground return common to
the DC power supplies, optionally Vss, Vee, and VOD.
13
Ox
Output
Output of the transmit side
onto the send PCM highway (serial bus). The 8-bit
PCM word is serially sent
out on this pin at the proper
time defined by FSx, CLKx,
Dc, and CLKe. TTL threestate output.
14
TSx
Output
Normally high, this signal
goes low while the Codec is
transmitting an 8-bit PCM
word on the Ox lead. ITimeslot information used for
diagnostic purposes and
also to gate the data on the
Ox lead.) TTL interface,
open drain output.
15
Vee
Power
+5V, ±5%, referenced to
GRDD.
16
CLKR
Input
Master receive clock defining the bit rate on the receive PCM highway. Typically 2.048 Mbps for a carrier system. Maximum rate
2.1 Mbps. 50% duty cycle.
TTL compatible.
17
FSR
I nput
Frame synchronization pulse
for the receive PCM highway. Maximum repetition
rate 16 kHz. For functional
description, refer to the
Codec operation section,
Codec control paragraph.
TTL interface.
18
CLKx
Input
Master transmit clock defining the bit rate on the
transmit PCM highway. Typically 2.048 Mbps for a carrier system. Maximum rate
2.1 Mbps. 50% duty cycle.
TTL interface.
19
FSx
Input
Frame synchronization pulse
for the transmit PCM highway. Maximum repetition
rate 16 kHz. For functional
description, refer to the
Codec operation section,
Codec control paragraph.
TTL interface.
4
AUTO
Output
Most significant bit of the
encoded PCM word 1+5V
for positive, -5V for negative value) Used as an internal ground offset correction, by integrating it
through the input coupling
capacitor. Refer to the
Codec interface section.
5
GRDA
Ground
Analog return common to
the transmit and receive
analog circuits. Not connected to GRDD internally.
The external connection to
GRDD should have a very
low impedance.
6
Voo
Power
+12V, ±5%, referenced to
GRDD or GRDA. depending upon system grounding
considerations.
7
DR
Input
Receive PCM highway (serial bus) interface. The Codec serially receives a PCM
word (8-bits) through this
lead at the proper time
defined by FSR, CLKR, Dc,
and CLKe.
8
PDWN
Output
Normally low. this signal
goes high while the Codec
is in the power down mode.
TTL interface, open drain
output.
9
VFR
Output
Analog output. The voltage
present on VFR is the decoded value of the PCM
word received on lead DR.
This value is held constant
between two conversions.
For the dynamic range description. refer to the Codec
operation section, decoding paragraph.
7·15
2911
Pin No. Symbol
Function
Description
Pin No. Symbol
20
Vaa
Power
-5V, ±5%, referenced to
GRDD or GRDA, dependupon system grounding
considerations.
21
Dc
Input
Dati I<--
:.· . ·.=-1;::::0":::3-'--'-"-'-,.-'-.-"-.-"-'-"-.-'-.-=m
CAPx
=:::::::-..:--...............
2
~ __________
---==-=---=-=:::==============::====~~
~J~~~'~O~cO~"~c~'c~"~~=======~~=---~~==========~============~~~~
__
>tOLD TIME
7·18
2911
Conversion Law
CODEC TRANSFER CHARACTERiStIC
The conversion law is commonly referred to as the A Law.
The Codec provides a piecewise linear approximation of
the logrithmic law through 13 segments. Each segment is
made of 16 steps with the exception of the first segment
which has 32 steps. In adjacent segments the step sizes
are in a ratio of two to one. Within each segment, the step
size is constant.
The output levels are midway between the corresponding
decision levels. The output levels Yn are related to the
input levels Xn by the expression:
Yn =
Xn-1
+ Xn
2
0< n :S 128
CODER TRANSFER CHARACTERISTIC
DECODER TRANSFER CHARACTERISTIC
(D/A CONVERSION)
(AID CONVERSION)
ANALOG
DIGITAL
OUTPUT
OUTPUT
L
I
L
I
r
7-19
"i!'~~.
2911
,j'I~::
,
A LAW - POSITIVE INPUT VALUES
"
(For Negative Input Values, Invert Bit 1)
1
2
3
4
5
Segment
No.
No. of Steps
x Step Size
Value at
Segment
End Points
Decision
Value No.
n
Decision
Value Xn
4096(3)
(128)
127
(4096)
3968
113
112
2176
2048
7
·
16 x 128
2048
6
·
16 x 64
1024
5
·
81
16 x 32
512
4
3
2
16 x 16
·
·
··
··
··
·
··
1088
1024
544
512
6
7
PCM Word(4)
Normalized
Value at
. Decoder
Decoder
Output
Value No.
Bit Number
1 2 3 4 5 6 7
8 Output Y n (5)
r;-'11'-1-1-'
(2)
1 1 1 1 0 0 0 0
(2)
1 1 1 0 0 0 0 0
(2)
1 1 0 1 0 0 0 0
272
2?6
1 1 0 0 0 0 0 0
128
49
48
136
128
1 0 1 1 0 0 0 0
16 x 4
33
32
1
0
·
··
68
64
2
0
4032
:
:
(2)
(2)
1 0 1 0 0 0 0 0
(2)
1 0 0 0 0 0 0 0
f,.
128
·
·
·:
2112
113
1056
97
528
81
·:
··
·:
:
:
:
:
(2)
65
64
16 x 8
32 x 2
80
·
" ..• ,
8'
256
64
1
97
96
(1 )
·""'1
264
·
65
132
49
·
·
:
·
:
:
:
:
·
66
·
·:
33
1
1
·:
NOTES:
(3)
4096 norma lized value units correspond to VF X max = 3.14 dBmO or 3.15 volts.
The PCM word corresponding to positive input values between two successive decision values numbered nand n+1 (see column 4)
is (128+n) expressed as a binary number.
X128 is a virtual decision value.
(4)
The PCM word on the highways is the same as the one shown in column 6, with the even order bits inverted. The 2911 provides
(5)
The voltage output on the VFR lead is equal to the normalized value given in the table, augmented by an offset. The offset value
is approximately 15mV.
(1)
(2)
for the inversion of the even order bits on both the send and receive sections. The sign bit is inverted on the encoder side only.
Decoding
The PCM word fetched from the receive PCM highway is
decoded as described in the previous paragraph. The decoded value is held in the external capacitor connected to
the CAP1 Rand CAP2R leads. The output signal on lead
VFR has a dynamic range of ±3.1 0 volts; it is held constant
between two successive decode operations. The VFR
output is updated within the fifth time-slot following the
receive time-slot in which the channel is operating.
2911
Standby Mode -
Power Down
To minimize power consumption and dissipation in large
systems, a standby mode is provided by loading a control
word (Del with a "1" in bits 1 and 2 locations. Most of the
Godec functions thereby become disabled, with the
8xception of the interface to the Dc and GLKc leads, to
allow the Godec to be reactivated.
VOLTAGE REFERENCE FOR,. .
CONVERSION
, , .' "\ 'sf'. 4{Ji-'- -<~,
The voltage reference is generated on-board th~' C$iP
is calibrated during the manufacturing process>';rhEi''r $'i~),
tolerance is ±20mV. The dynamic range of the digitaMo,. W .:<,.F·
analog converter is ±3.10 volts.
ti'Eli:::
'~;
The power consumption in the standby mode is less than
90 mW.
APPLICATION -
LINE INTERFACE
Auto Zero
Grounding
Digital grounding is connected to the GRDD lead. It is the
common return for the digital signals.
'6
ANALOG CKTS.
~--I ~~
L
01
47OK
AUTO
~
470K
[1&
GRDA
.2K
U
r~
I
±V,GRDA
0.1 "I
v
L
VFR
111
~
T8D
2000pF
I DIGITAL
I CKTS
+12
,
+5
I
I
111
U,
TBD
1
While improving DG offset, the use of Auto Zero may raise
idle channel noise due to biasing near zero with resultant
encoder "hunting" of the least significant bit.
Filters Interface
80
t-
The auto zero output (most significant bit or sign bit of the
AID conversion) integrated over a long time constant will
compensate for the DG offset inside the Godec (voltage
difference between the bottom of the DAG and GRDAI.
The above drawing shows a possible connection between
the VFx and Auto leads.
GROD
I
!
Attached is the schematic of the equivalent ci rcuits of the
input and output of the Godec. Note that the output pulse
stream is of the non-return to zero type.
-5
FILTER
~'~I
8KHz
VI
"
soon.
470K
Analog grounding is connected to the GRDA lead. The
GRDA and GRDD lead are not connected inside the 2911.
An external connection is thus necessary outside the
Godec to tie all the analog ground lines to the common
return of the system GRDD. That external connection has
to have a minimal impedance to avoid a DG offset in the
Godec.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . . . _40°C to +80°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
Supply Voltage with Respect to Vss ..... -O.5V to +14V
All Input Voltages . . . . . . . . . . . . . -O.5V to (Voo + lV)
Outputs . . . . . . . . . . . . . . . . . . . . . -lV to (Voo + lV)
Power Dissipation . . . . . . . . . . . . . • . . . . . . . . . 1.35W
2.2K
FILTER
~
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
2911
DC AND OPERATING CHARACTERISTICS
T A; O°C to +70°C, VOO; +12V, VCC; 5V, VSB; -5V
POWER DISSIPATION
Limits
Symbol
Parameter
Min.
Typ.
Max.
Test Conditions
Unit
1000
Standby Current
TBD
mA
Icco
Standby Current
TBD
mA
Voo; +12, +10%
IBBO
Standby Current
TBD
mA
Vcc ; 5.0, +10%
1001
Operating Current
TBD
mA
Clocking Frequency
Icci
Operating Current
TBD
mA
X & R ; 2.048 Mbps
IBBI
Operating Current
TBD
mA
VBB ; -5.0, -10%
DIGITAL INTERFACE
Symbol
Parameter
Min.
Limits
Typ.
Max.
Unit
Test Conditions
III
Low Level I nput Current
10
)J.A
VIN < Vll
IIH
High Level I nput Current
10
)J.A
VIN
Vll
Input Low Voltage
+0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
> VIH
V
+2.0
0.4
2.4
V
IOl;10mAonDx
6.4 mA on TSx
V
10H; 30 mA on Dx
ANALOG INTERFACE
Limits
Symbol
All
Parameter
Min.
Typ.
Input Leakage when Sampling
AIZ
Input Impedance when Sampling
ADZ
Output Impedance
ADA
Dynamic Range (VFR)
Max.
1
1.8
2.0
)J.A
500
n
2.2
kn
+3.1
-3.1
Test Conditions
Unit·
V
-3.1V1"" '" '1' ....0""
Figure 1. Block'Diagram of a Typical System
W\'tW\O?:'(
8-4
\:>"'~ '" '1' ....0""
~t'l\~~~
intel
3003
LOOK-AHEAD CARRY GENERATOR
The INTEL® 3003 Look-Ahead Carry
Generator (LCG) is a high speed circuit
capable of anticipating a carry across a
full 16-bit 3002 Central Processing
Element (CPE) array. When used with a
larger 3002 CP array multiple 3003 carry
generators provide high speed carry lookahead capability for any word length.
The LCG accepts eight pairs of active
high cascade inputs (X,Y) and an active
low carry input and generates active
loVl! carries for up to eight groups of
bi nary adders.
High Performance - 10 ns typical
propagation delay
Compatible with INTEL 3001 MCU
and 3002 CPE
DTL and TTL compatible
PACKAGE CONFIGURATION
v,
x,
Vee
V6
EC n + 8
26
Full look·ahead across 8 adders
X2
Xs
23
X.
Low voltage diode input clamp
INTEl®
3003
V5
21
V.
V3
X,
Xo
11
18
Vo
17
Co
13
16
Cn + 3
15
en + 1
Cn + 4
Cn + 2
GND
V,
19
X3
28'pin DIP
V2
Cn + 6
Cn + 5
Expandable
X6
Cn + 7
Cn + R
,.
CONTROL TO
MI'cMORV I/O
~ ~~GM
~tMG~~
UClo..'
Diagram of a TYPical System
8-5
\:)f:>,.., p.,. ~~aW\
D~~\C~~
MCS-4140™MICROPROCESSOR
INTRODUCTION
The MCS"4/40™. microprocessor family has been in use for a wide va'riety of computer and con"
trol applications since 1971, The 4004 and 4040 are complete 4"bit parallel central processing
units. (CPUs). The 4040 has a complete instruction set of 60 instructions, including arithmetic,
interru,pt, logiqal opera~ions, I/O instructions, register instructions, ROM bank switching, register
bank switohing, interrupt disaQle, and enable. The 4004 has a total .of 46 instructions all of which
are part of the 4040 instruction set and. are mutually compatible.
TABLE OF CONTENTS*
Central ProcessingUni1
. 4040 Single Chip 4"BitP·Channel Microprocessor . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9"3
4004 Single Chip 4"Bit P"Channel Microprocllssor .............• , . . . . . . . • . . . . . . . . . . . . . . ,. 9A
Input/Output
4003 1O"Bit ?,hift Register/Output Expander . . . . . . . . . . . . . . . . , . . . . . . . . • . . . . . . . . . . . . . . . 9"5
4265 Programmable General Purpose I/O Device . . . . . . . . . . . . . . . . . . . . . . . . . . ' .... , ..... , . , 9"6
4269Progran:mable Keyboard Display Device ...... , ....... ' . . . . . . . . . . . . . . . . . . . . . . . . . . 9,7
Peripherals
4201A Cioe.k Gerierator ; . . . . . . . . . . . . . . . . . . . : ... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9"8
4008/4009 Standard Me'!'ory and I/O Interface Set .... '.' . . . . . . . . . . . . . . . . . . . . . . . . . '...... 9·9
4289 Standard Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ....... , ....... 9·10
RAMs
4002 320·BitRAM and 4·Bit Output Port ........ '. . . . . . . . . . . . , .. , . . . . . . . . . . . . . . . . . . .9·11
ROMs'
.
4Q01 256 x8 Mask Programmable ROM and 4·Bit I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9·12
43081024 x 8 Mask ~rogrammable RONi and Four 4·Bit I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .9·14
4316A/2316A 2048 x 8 RON! . . • . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . , .4·22
PROMs
1702A/4702A 2K (256 x 8) UV Erasable PROM . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . 4·5
4702A Reprogrammable 2K PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4"14
*Partial data sheets are shown here. For complete specifications, contact Intel Literature Department, Intel Corporation, 3065
Bowers Avenue, Santa Clara, California 95051.
9-2
inter
4040
SINGLE CHIP 4-BIT
P-CHANNEL MICROPROCESSOR
• 8K Byte Memory Addressing
Capability
• Functionally and Electrically
Upward Compatible to 4004 CPU
• 14 Additional Instructions
(60 total) Including Logical
Operations and Read Program
Memory
• 24 Index Registers
• Subroutine Nesting to 7 Levels
• Standard Operating
Temperature Range of
OOto 70°C
• Interrupt Capability
• Single Step Operation
• Also Available With -40°
to +85° C Operating Range
The Intel® 4040 is a complete 4-bit parallel central processing unit (CPU). The CPU can directly address 4K eight bit instruction
words or 8K with a bank switch. Seven levels of subroutine nesting, including interrupt, and 24 randomly accessable index
registers (24x4) are provided as convenient facilities for the designer. The index registers may be used for addressing or for
scratch pad memory for storing computation results. The interrupt feature permits a normal program sequence to be
interrupted, with normal program execution continuing after the interrupt service routine is completed. Provisions have also
been made to permit single-stepping the CPU using the STOP and ACKNOWLEDGE signals.
The 4040 is an enhanced version of the 4004 and as such retains all the functional capability of that device. It will execute all the
4004 instructions, and is also electrically compatible with all components used with a 4004 CPU.
BLOCK DIAGRAM
00'0:,
BI·DIRECTIONAL
DATA BUS
it
DATABUS
BUFFER
(4 BIT)
INTERNAL DATA BUS
IACCUMULAT~:)
II
1I
1
~~
UNIT
(ALU)
I
j t
D:g~~:TL
CARRY
ROM
OUT
CONTROL
AND
I==-
MACHINE
CYCLE
ENCODING
ct
CM ROM
CM RAM
0-1
0-3
~
u
~
1==1
AND
CONTROL
SYIC
TtIIL.L
ACK
t
TIMING
CONTROL
SINGLE
STEP
TEST
JJ Wl
--... ~
2
~
I...-
RAM
CONTROL
MPX
0(4)
(12)
DECODER
I
I
I
~
I
PROGRAM COUNTER
1
LEVEL NO.1
2
3
LEVEL NO.2
4
5
lEVEL NO.3
6
INSTRUCTION
I-
-10V
+5V
Jt
MUlS;;~~:XER
J
ARITHMETIC
lOGIC
_
--
INSTRUCTION I
REGISTER (8)
TEMP. REG'(4)
t I
~-
(4 BIT)
INTERNAL DATA BUS
H
FLIP·FLOPS
POWER
SUPPLIES
~
Tcr~
SYNC 91
INTERRUPT
INT ACK
9-3
92
RESET
r-
LEVEL NO.4
,
7
9
LEVEL NO.5
10
11
LEVEL NO.6
12
13
lEVEL NO.7
14
15
ADDRESS
STACK
o (4)
1
2
3
4
5
6
7
SCRATCH
PAD
inter
4004
SINGLE CHIP 4-81T
P-CHANNEL MICROPROCESSOR
• CPU Directly Compatible
With MCS-40 ROMs and
RAMs
• Easy Expansion - One CPU
can Directly Drive up to
32,768 Bits of ROM and up
to 5120 Bits of RAM
• Standard Operating
Temperature Range of
0° to 70°C
• Also Available With -40°
to +85° C Operating Range
• 4-Bit Parallel CPU With 46
Instructions
• Instruction Set Includes
Conditional Branching,
Jump to Subroutine and
Indirect Fetching
• Binary and Decimal
Arithmetic Modes
• 10.8 Microsecond
Instruction Cycle
The Intel® 4004 is a complete 4-bit parallel central processing unit (CPU). The 4004 easily interfaces with keyboards,
switches, displays, A-D converters, printers and other peripheral equipment.
The CPU can directly address 4K 8-bit instruction words of program memory and 5120 bits of data storage RAM. Sixteen
index registers are provided for temporary data storage_ Up to 16 4-bit input ports and 16 4-bit output ports may also be
directly addressed_
The 4004 is fabricated with P-channel silicon gate MOS technology.
BI·DIRECTIONAL
DATA BUS
U J
DATA BUS
BUFFER
(4 BIT)
INTERNAL DATA BUS
LACCUMULAT~~
II
TEMP. REG. )
141
1
I
INSTRUCTION
1
(4 BIT)
INTERNAL DATA BUS
II
I.
STACK
REGISTER (8)
I
II
~
~
FLAG
FLlp·FLOPS
t I
:!i>-
INSTRUCTION
DECODER
~ ~ARITHMETIC
lOGIC
UNIT
(ALUI
MULTIPLEXER
AND
MACHINE
CYCLE
=-
ENCODING
-
LEVEL NO.1
'"
LEVEL NO.2
'"
LEVEL NO.3
141-
I
I t
DECIMAL
ADJUST
su
_
_
-10V
+5V
I
I
ROM
CONTROL
eM
I
ROM
TIMING
AND
CONTROL
TEST
,Ill
! 1
~
TEST
SyrCTT
SYNC
CM RAM
0-3
9-4
¢1 rp2
l
RESET
MPX
141
1
141
2 (4)
3 (41
4 (4)
5 (4)
6 (4)
7 (4)
(12)
(12)
IW
ADDRESS
STACK
1
RAM
CONTROL
0
J
1-.....-I
POWER {
PPLIES
in
REGISTER
(12)
()
1I
I
PROGRAM COUNTER
z
2
I
t
8 (4)
9 (4)
10 (4 )
11 (4)
12 (4 )
13 (4 )
14(4)
15(4)
SCRATCH
PAD
4003
10-BIT SHIFT REGISTER/OUTPUT EXPANDER
• Easy Expansion of I/O Output
Capability
• 10 Bit Serial-In/Parallel Out
• Serial-Out Capability for
Additional I/O Expansion
• Enable Output Control
• Standard Operating Temperature
Range of 0° to 70° C
• 16 Pin Dual-In-Line Package
The 4003 is a 10 bit serial-in, parallel-out, serial-out shift register with enable logic. The 4003 is used to expand the number of
ROM and RAM I/O ports to communicate with peripheral devices such as keyboards, printers, displays, readers,
teletypewriters, etc.
The 4003 is a single phase static shift register; however, the clock pulse (CP) maximum width is limited to 10msec. Data-in and
CP can be simultaneous. To avoid race conditions, CP is internally delayed.
PIN CONFIGURATION
CLOCK}
PULSE INPUT CP
DATA IN
PARALLEL {OO
OUTPUTS
E
!!
ENABLE INPUT
SERIAL OUT
Voo
0,
09
Vss
08
r
BLOCK DIAGRAM
°7
PARALLEL °
OUTPUTS
3
06
0.
°s
PARALLEL
OUTPUTS
Ef>-
0----...
(ENABLE)
.
I
'I
9-5
I
I
I
10 BIT PARALLEL
OUTPUT BUFFER
I
I
inter
4265
PROGRAMMABLE GENERAL PURPOSE I/O DEVI.CE
Interface
• TTL
Up to Eight 4265s Per System
• Interface
to Standard RAMs
• 28 Pin Dual-In-Line
Package
•
to Standard RAMs
• Interface
28
Pin
Dual-In-Line
• Standard Operating Package
• Range of 0° to 70° CTemperature
Available with -40° to
• Also
+85°C Operating Range
14 Operating Modes
• Multi-Mode
16 Lines of I/O Capability
• Bit
Set/Reset
• MultiplexableOutputs
•
Eight Bit Transfer Mode
• Interfaces
to 8080 Peripherals
• Synchronous
• Interface and Asynchronous
• Strobed Buffer Inputs and Outputs
The 4265 is a general purpose liD device designed to interface with the MCS-40'· microcomputer family. This device provides
four software programmable 4-bit liD ports which can be configured to allow anyone of fourteen unique operating modes for
interfacing to data memory or a variety of user peripheral devices.
A single MCS-40 system can accomodate up to four 4265s (one per CM-RAM) without external logic or up to eight 4265s with
one external decoder.
The 4265 resides on the MCS-40 data bus and uses the same selection procedure as 4002 RAM device. A valid compare selects
the 4265 for MCS-40 liD commands. As in the case of the 4002 or any MCS-40 peripheral circuit, selecti:m occurs only when the
proper SRC code and the CM signal are present simultaneously.
The 4265 provides an extremely flexible, general purpose liD system capable of handling 4- or 8-bit input or output data. One of
fourteen basic operating modes can be'selected (software programmable) as described below.
Port Z is TTL compatible with any TTL device. Ports W, X, and Yare low-power TTL compatible.
PIN CONFIGURATION
Vss
Voo
Do
Wo'
D,
W,
D,
W,
D,
W,
RESET
Xo
eM· RAM
x,
SYNC
X,
'"
X,
(,'1 2
Vo
2,
V,
2,
V,
2,
V,
20
VOO1
9-6
inter
4269
PROGRAMMABLE KEYBOARD DISPLAY DEVICE
Keyboard Features:
Display Features:
•
Programmable to Interface to Encoded
Keyboard (8-bit code), 64-Key Scanned
Keyboard (expandable to 128 keys) or
Sensor Matrix (64 sensors)
•
Programmable to Interface to
Individually Scanned Displays or
Burrough's Self-Scan* Drive (16,,18, or
20 Characters)
•
8 Character FIFO Character Buffer (or
RAM in Sensor Mode)
•
•
2 Key Rollover and Key Debounce
•
External Interrupt Line to Indicate
When a Character Has Been Entered'in
Character Buffer
Two 16 x 4 Display Registers
Recirculated Synchronously with
Keyboard Scan Lines to Give Automatic
Display Refresh
•
Display Registers Loadable and
Readable Selectively or Sequentially
•
•
40 Pin Dual In-Line Package
Standard Operating Temperature
Range of 0° to 70°C
Also Available with -40° C to +85° C
Operating Range
•
The 4269 has two separate and distinct sections: the keyboard section and the display section. The keyboard section can
interface to a range of devices from a matrix of toggle or thumb switches such as found on an instrument panel up to a full
typewriter style keyboard. The display section can interface to a range of devices from an array of individual LED indicators up
to a gas discharge alphanumeric display.
The 4269 Programmable Keyboard Display (PKD) relieves the 4004 or 4040 CPU from continuously scanning a switch array or
refreshing a display under software control. This greatly expands the CPU throughput. The 4269 can scan up to an 8 x 8
keyboard or sensor matrix (or a 2 x 8 x 8 keyboard with the use of the shift or control key input). The display portion can
continuously refresh either asingle 16x 8 alphanumeric display; a single 8 x 8 alphanumeric display; a dual16x 4 digit display; a
single 32 x 4 digit display; a 16 x 6, 18 x 6 or 20 x 6 alphanumeric gas discharge display such asthe Burroughs Self-Scan'; oran
array of 128 indicators.
·Self-Scan is a registered trademark of the Burroughs Corporation
PIN CONFIGURATION
9·7
inter
4201A
CLOCK GENERATOR
• Complete Clock Requirements for
MCS-40TM Systems
• Provides MCS-40 Reset Function
Signal
• Crystal Controlled Oscillator
(XT AL External)
• Standard Operating Temperature Range
of 0° to 70°C
• MOS and TTL level Clock Outputs
• Also Available with -40° to +85° C
Operating Range
The 4201A is a CMOS integrated circuit designed to fill the clock requirements of the MCS-40 microcomputer family. The
4201A contains a crystal controlled oscillator (XTAL external), clock generation circuitry, and both MaS and TTL level
clock driver circuits.
The 4201A also performs the power on reset function required by MCS-40 components and provides the logic necessary to
implement the single-step function of the 4040 central processor unit.
PIN CONFIGURATION
4201A
GNo
\'2T
'i lT
Vee
(:)2
'/1
Voo
RESET
RESET IN
STOP
N. OPEN
ACK
N. CLOSED
BLOCK DIAGRAM
""
~
=
&' '"
1 - - - - 1
MODEo~------------------.l--------
"1 DR rVER
(,'2 DRIVER
0-----------
%~: g>-__~-_-_-_-_~"'ST§EP=:
,'---......
DRrVER
~}
L----...I~
DRIVER
RESET OUT
P-o}
~~MOS
TTL
!------....,
I-_________________________ STOP
~
SINGL£
STEP F!F
__--------------------------OACK
111
Vss
9-8
V OD GROUND
inter
4008/4009
STANDARD MEMORY AND 1/0 INTERFACE SET . '
• Direct Interface to Standard
Memories
• Allows Write Program Memory
• 24 Pin Dual In-Line Packages
• Standard Operating
Temperature Range of
0° to 70°C
The standard memory and 1/0 interface set (4008/4009) provides the complete control functions performed by the 4001 or 4308
in MCS-40'· systems. The 4008/4009 are completely compatible with other members of the MCS-40 family. All activity is still
under control of the CPU. One set of 4008/4009 and several TTL decoders is sufficient to interface to 4K words of program
memory, sixteen four-bit input ports and sixteen four-bit output ports.
PIN CONFIGURATIONS
4009 BLOCK DIAGRAM
4008 BLOCK DIAGRAM
...
A,
"
A,
..,
A.
0,
0',0
0,
A,
"0,
110,
.,"
1102
11°1
Co
C,
C,
C,
110· X ll
9·9
4289
STANDARD MEMORY 'INTERFACE
• Direct Interface to all Standard
Memories
• 40 Pin Dual In-Line, Package
• Standard Operating
Temperature Range of
0° to 70°C
• Allows Read and Write Program
Memory
• Single Package Equivalent of
4008/4009
• Also Available With
-40° to +85 0 C Operating
Range
• TTL Compatible Address, Chip
Select, Program Memory Data
Lines
The 4289 standard memory interface and I/O interface enables the CPU devices to utilize standard memory components as
program data memory, Notably, PROMs (4702A), RAMs (2102) and ROMs can be arranged in a memory array to facilitate
system development. Programs generated using the 4289 interface can be committed to MCS-40'· ROMs (4308 and 4001) with
no change to software.
The 4289 also contains a 4 bit bi-directionall/O port and necessary steering logicto multiplex a host of I/O sources to the CPU.
The Read and Write Program Memory instruction allows the user to storedata and modify program memory. The device directly
addresses 4K of program memory, The address is obtained sequentially during A1-A3 states of an instruction cycle. The eight
bit instruction is presented to the CPU during M1 and M2 states of the instruction cycle via the four bit data bus,
The 4289 stores the SRC instruction operand as an I/O address and responds to the ROM I/O instructions (WRR and RDR) by
reading or writing data to and from the processor and 4289 '110 bus.
BLOCK DIAGRAM
SRC
REG,
IUPPER)
SRC
REG,
ILOWER)
MEMORY
ADDRESS
MPX
ADDRESS
BUFFERS
I/O DATA
BUS
BUFFERS
..
....
1/00
liD,
!
1/0, 1/03
F/L
OUT
111
Vss
9·10
VOD VOD1
..
oj
00,
012
o SYNC
oeM
o ~ESET
inter
4002
320-BIT RAM AND 4-BIT OUTPUT PORT
• Four Registers of 20 4 Bit
•
•
• 16 Pin Dual In-Line Package
• Standard Operating
Characters
Direct Interface to MCS-40TM
4 Bit Bus
Output Port Low-Power TTL
Compatible
•
Temperature Range of
0° to 70°C
Also Available With -40°
to +85° C Operating Range
The 4002 performs two distinct functions. As a RAM it stores 320 bits arranged in 4 registers of twenty 4 bit characters each (16
main memory characters and 4 status characters). As a vehicle of communi.cation with peripheral devices, it is provided with 4
output lines and associated control logic to perform output operations. The 4002 is a PMOS device and is compatible with all
MCS-40'· components.
'
The 4002 is available in two options, the 4002-1 and 4002-2, Along with an external pin connected to eitherVoo orVss, a two bit
chip selection address is provided allowing a maximum of 1280 bits of 4002 RAM on a single MCS-40 CM-RAM line. Thus, the
four CM-RAM lines give a maximum of 5120 bits of 4002 RAM in an MCS-40 system,
PIN CONFIGURATION
BLOCK DIAGRAM
::~:-----------~:~IIr----:TI-M-'N-G-----'I~~~--~o SYNC
"'f
.US
110
++++++
0,
OUTPUT
OJ
"1
lis,
Voo
02
p~~~~~}~
ClOCK}tP2
PHASE 2
I~~~~} SYNC
02
LINES
Do
OJ
I_------~o eM
0,
eM
{MEMORY
CONTROL
INPUT
iHARD WIRED
'0 CHIPSHECT
O2
k---~--__<> RST
OJ
INPUT
RESET
MEMORY
"DATA
MUX
DATA
ADDRESS
REGISTER
AND
OUTPUT
PORT
OUT
DECODER
ADDRESS
4 X 16
REG 0
DATA /I--ST-A-TU-S---I REG 1
IN
9-11
4 X4
REG 2
REG 3
inter
4001
256 x 8 MASK PROGRAMMABLE ROM
AND 4-BIT I/O PORT
• Standard Operating
Temperature Range of
0° to 70°C
4
• Also Available With -40° to
+85° C Operating Range
• Direct Interface to MCS-40TM
4 BifData 'Bus
• I/O Port Low:-Power TTL
Compatible
• 16 Pin Dual In-Line Package
The 4001 performs two basic and distinct functions, As aROMit stores 256 x 8 words of program or data tables; as a vehicle of
communication with peripheral devices it is provided with 4 liD pins and associated control logic to perform input and output
operations, The 4001 is a PMOS device, compatible with all other MCS-40'· devices,
BLOCK DIAGRAM
PIN CONFIGURATION
:: ~>-----------;:~lrR-O-M-TI-MI-NGI.I-----:
DATA
r
0,
.us
1/0
02
0,
1/0 3
VDD
1
ClDCK}1I
PHASE 2
2
I~~~~ }S't'NC
nn~u.
INPUT!
OUTPUT
1/02 LINES
Vss
ClOCK}~
PHASE 1
liD,
")
OVss
.....f - - - - O VOD
fr - - - - - - - -OCM
°oO--OI-----l--r-:::::-l
{ MEMORY
eM CONTROL
1..--------<)
RST
D,0--0t--~
INPUT
Cl
SYNC
D20--0t--~
{CLEAR INPUT
FOR I/O LINES
D,o--ot----JL..,...---1
RESET
MEMORY
DATA
MUX
CLEAR
ADDRESS
I/O
INTERFACE
REGISTER
AND
DECODER
9-12
1-_ _ _.1'-,
ROM
256 X 8
inter
MCS®
4001
ROM
CUSTOM ROM
ORDER FORM
CUSTOMER
P.O. NUMBER
DATE
For Intel use only
s#
PPPP
STD
ZZ
DD
APP
DATE
All custom 4001 ROM orders must be submitted on this form. Programming information should be sent in the form of computer
punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel.
MARKING
INTEL PATTERN NUMBER
The marking as shown at the right must contain the I ntel logo, the
product type (P4001), the 4·digit Intel pattern number (PPPP), a date
code (XXXX), and the 2·digit chip number (DO). An optional customer
identification number may be substituted for the chip number (ZZ).
Optional Customer Number (maximum 6 characters or spaces).
•
I
CUSTOMER NUMBER _ _ _ _ _ _ _ _ _ _ _ _ _ __
P4001
PPPP
xxxx
zz
OATE COOE
CHIP NUMBER OR
CUSTOMER NUMBER
MASK OPTION SPECIFICATIONS
A. CHIP NUMBER _ _ _ _ __
(Must be specified-any number from
through 15-00).
o
6.
If Inputs and outputs are mixed on
the same port, the pins used as the
outputs must have the Internal resistor connected to either VOO or
B. I/O OPTION - Specify the connec·
tion numbers for each 1/0 pin (next
page). Examples of some of the possible I/O options are shown below:
EXAMPLES - DESIRED OPTION/CON·
NECTIONS REQUIRED
1. Non-inverting output -
1 and 3 are
connected.
2. Inverting output - 1 and 4 are connected.
3. Non-inverting inpu,t (no input resis-
tori - only 5 is connected.
VSS 18 and 9 or 8 and 10 must be
connected). This is necessary for testing purposes. For example, if there
are two inverting inputs (with no In·
put resistod and two non-Inverting
outputs, the connection would be
made as follows:
Inputs - 2 and 6 are connected
Outputs - 1, 3, 8, and 9 are connected or
1, 3, 8, and 19 are connected
If the pins on a port are all inputs or
all outputs, the internal resistors do
not have to be connected.
4, Inverting input I input resistor to VSS)
- 2, 6, 7, and 9 are connected.
5.
Non-inverting Input (Input resistor to
VOD) nected.
2, 7, 8, and 10 are con·
C. 4001 CUSTOM ROM PATTERN Programming information should be
sent in the form of computer punched
9-13
cards or punched paper tape. I neither
case, a printout of the truth table
must accompany the order. In the
BPNF format, the characters should
be written as a "P" for a high level
output ~ VSS (negative logic "0") or
an "N" for a low level output ~ V DD
(negative logic "1").
Hex input tapes for the 4001 and
4308 may also be generated by
I ntellec®
Development Systems.
These tapes are assumed to be negative
logic. This means that a NOP instruction operation code (00000000), for
example, would be coded as 00 in the
HEX format. This would automatically result in the V IH levels on the
MCS 4/40 data bus. When the BPN F
format is used, all logic representations must be inverted. Thus, a NOP
would be represented as BPPPPPPPPF.
inter
.:
"
4308
1024 x 8 MASK PROGRAMMABLE ROM
AND FOUR 4-BIT 1/0 PORTS
• Direct Interface to MCS-40TM
4-Bit Data Bus
• Equivalent to Four 4001 ROMs
• Four Independent 4-Bit I/O
Ports
• Input I/O Buffer Storage with
an Optional Strobe
• I/O Ports Low-Power TTL
Compatible
• 28 Pin Dual In-Line Package
• Standard Operating
Temperature Range of
OOto 70°C
• Also Available With -40°
to +85° C Operating Range
The 4308 is a 1024 x 8 bit word ROM memory with four I/O ports. It is designed for the MCS-40'· system and is operationally
compatible with all existing MCS-40 elements. The 4308 is functionally identical to four 4001 chips. The 4308 has 161/0 lines
arranged in four groups of four lines.
BLOCK DIAGRAM
SYNC
eM ROM
Do
0,
0
11
o-!-0--...2.-.-
o~
0, o~
RESET
CLR/LD
d
"
0,
"
22
TIMING
"I
10 0
23 0
28
-,--0
--0
ADDRESS
DATA BUS
ROM ARRAY
AND MUX
1024' 8
REGISTER
CONTROL
IN·OUT
BUFFER
,;;.
[I
~ ~ ~ ~ ~
..
AND
LOGIC
DECODER
I
III
,tv
I{OPORT
0
1"1-1+
•
+
--"~
I
Jl
II I
t+~
I/O PORT
1
HH
1/010
I/Oh
PIN CONFIGURATION
9-14
1 1
4BITS~
1
1
JJI
iiS2"
ilil
lIO PORT
2
I/O PORT
I" ·1. ·
1/020
1/023
3
H·Il
1/030
1/033
""
Voo
Vss
,
4308
MCS e
CUSTOM ROM
ORDER FORM
intel
ROM
CUSTOMER
P.O. NUMBER
DATE
For Inlel use only
S#
PPPP
STD
ZZ
DD
APP
DATE
All custom 4308 ROM orders must be submitted on thiS form. Programming information should be sent in the form of computer
punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel.
MARKING
INTEL PATTERN NUMBER
•
The marking as shown at the right must contain the Intel logo,
the product type (P4308)' the 4-digit Intel pattern number
(pPPP), a date code (XXXX), and the 2-digit chip number
(DO). An optional customer identification number may be
substituted for the chip number (ZZ). Optional Customer
Number (maximum 6 characters or spaces)_
CUSTOMER NUMBER _______________________
P4308
I
zz
XXXX
CHIP NUMBER OR
CUSTOMER NUMBER
DATE CODE
MASK OPTION SPECIFICATION
A. CHIP NUMBER _ _ _ _ _ _ _ _ (Must be specified).
Hex input tapes for the 4001' and 4308 may also be generated by I ntellec® Development Systems. These tapes.
are assumed to be negative logic. This means that a NOP
instruction operation code (00000000), for example, would'
be coded as 00 in the HEX format. This would automatically result in the V IH levels on the MCS 4/40 data bus.
When the BPNF format is used, all logic representations
must be inverted. Thus, a NOP would be represented as
BPPPPPPPPF.
B_ I/O OPTION - Specify the connection numbers for each
1/0 pin_ See table below.
C_ 4308 CUSTOM ROM PATTERN - Programming information should be sent in the form of computer punched cards
or punched paper tape. In either case, a printout of the truth
table must accompany the order. In the BPNF format, the
characters should be written as a "P" for a high level output
= VSS (negative logic "0") or an "N" for a low level output
= V DD (negative logic "1").
PIN
1/0 00
1/0 0,
liDO,
1/00 3
1/01 0
1/01,
110 I,
1/01 3
1/020
1/0 2,
1/022
1/02 3
1/030
1/03,
1/03 2
1/033
OPTION
27
26
25
24
5
4
3
2
17
16
15
14
21
20
19
18
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
3
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
EJ-
ROM
PATTERN
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
MUX
I
"11
"
11
"
sus
I
ON
~~~t
"
11
11
11
11
DATA
OUTPUT
LOGIC
L F
RESETQ
_
4
, ON
110
o---BJ--t>-1:
1"
5
~
11
11
11
11
11
11
I eLK
2
INPUT
j
"6
FF
-
1/0 PORT LINE OPTION
NOTE: Options 10 and 11 cannot both be specified.
9-15
81~VDO
71
Y
XVss
MCS-48™
Microcomputers
MCS-48™ MICROCOMPUTERS
TABLE OF CONTENTS
Single Component 8-Bit Microcomputers
8021 Single Component 8-Bit Microcomputer . . . . . . . . • . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . .
8048/8748/8035 Single Component .8-Bit Microcomputer ..... , . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8748-4/8035-4 Single Component 8-Bit Microcomputer
..................................
8049/8039 Single Component 8-Bit Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-4
10-10
10-18
10-23
Input(Output
8243 MCS-48 ™ Input/Output Expander . . . . . . . . . . . • . . . . . . • . . . . . . . • . . . . . . . . . . . • . . . . . 10-28
INTRODUCTION
Recent advances in NMOS technology have allowed Intel for the first time to place enough capability
on a single silicon die to create a true single chip microcomputer containing all the functions required
in a digital processing system. This microcomputer, its variations, and its optional peripherals are
collectively called the MCS-48 microcomputer family and are fully described in this manual.
The head of the family is the 8048 microcomputer which contains the following functions in a single
40-pin package:
8-Bit CPU
1K x 8 ROM program memory
64 x 8 RAM data memory
27 I/O lines
8-bit timer/event counter
A 2.5 or 5.0 microsecond cycle time and a repertoire of over 90 instructions each consisting of either
one or two cycles makes the single chip 8048 the equal in performance of most presently available
multi-chip NMOS microprocessors, yet the 8048 is a true "low-cost" microcomputer. A single 5V
supply requirement for all MCS-48 components assures that "low cost" also applies to the power
supply in your system.
Even with low component costs, however, a project may be jeopardized by high development and
rework costs resulting from an inflexible production design. Intel has solved this problem by creating
two pin-compatible versions of the 8048 microcomputer: the 8048 with mask programmable ROM
program memory for low cost production and the 8748 with user programmable and erasable EPROM
program memory for prototype development. The 8748 is essentially a single chip microcomputer
"breadboard" which can be modified over and over again during development and pre-production,
then simply replaced by the low cost 8048 ROM for volume production. The 8748 provides a very
easy transition from development to production and also provides an easy vehicle for temporary field
updates while new ROMs are being made.
1()'2
To allow the MCS-48 to solve a wide range of problems and to provide for future expansion, all 8048
functions have been made externally expandable using either special expanders or standard memories
and peripherals. An efficient low cost means of I/O expansion is provided by the 8243 Input/Output
Expander which provides 16 I/O lines in a 24-pin package. For systems with large I/O requ irements,
multiple 8243s can be used.
For such applications as keyboards, displays, serial communication lines, etc., standard MCS-80 ™
(8080) peripheral circuits may be added. Program and data memory may be expanded using
standard memories or the 8355 and 8155 memories that also include programmable I/O lines and
timing functions.
The 8035 is an 8048 without internal program memory that allows the user to match his program
memory requirements exactly by using a wide variety of external memories. The 8035 allows the
user to select a minimum cost system no matter what his program memory requirements.
The 8048 was designed to be an efficient control processor as well as an arithmetic processor with an
instruction set which allows the user to directly set and reset individual lines within its I/O ports as
well as test individual bits within the accumulator. A large variety of branch and table look-up
instructions make the 8048 very efficient in implementing standard logic functions. Special attention was also given to code efficiency with over 70% of the instructions being single byte and all
others being only two bytes. This means many functions requiring 1.5K to 2.0K bytes in other
processors may very well be compressed into the 1 K words resident in the 8048 .
...------"'--271/0 LINES
__-......",....--~-INTERVAL TIMER/EVENT COUNTER
OSCILLATOR AND CLOCK DRIVER
RESET CIRCUIT
INTERRUPT CIRCUIT
Figure 1. On Chip Features
SPECIAL FEATURES
•
SINGLE 5V SUPPLY
•
8-LEVEL STACK
•
40-PIN DIP
•
2 WORKING REGISTER BANKS
•
PIN COMPATIBLE ROM AND EPROM
•
•
2.5 AND 5.0 !1sec CYCLE VERSIONS
RC, XTAL, OR EXTERNAL
FREQUENCY SOURCE
•
CLOCK PER CYCLE AND OPTIONAL
CLOCK PER STATE OUTPUT
• ALL. INSTRUCTIONS 1 OR 2 CYCLES
•
SINGLE STEP
10-3
inter
8021
SINGLE COMPONENT 8·BIT MICROCOMPUTER
8·Bit CPU, ROM, RAM, I/O in Single
• 28·Pin
Package
1K x 8 ROM
• 64
x 8 RAM
21 I/O Lines
•
Cycle; All Instructions
• 110orJ.Lsec
2 Cycles
• Interval Timer/Event Counter
Generated With Single Resistor
• Clock
or Inductor
• Instructions -8748 Subset
• High Current Drive Capability-2 Pins
• Zero·Cross Detection Capability
• Easily Expandable I/O
Single SV Supply ( + 4.SV to 6.SV)
The Intel® 8021 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's N-channel
silicon gate MOS process. The features of the 8021 include a subset of the 8048 optimized for low cost, high volume applications, plus additional I/O flexibility and power.
The 8021 contains a 1 K X 8 program memory, a 64 X 8 data memory, 21 I/O lines, and an 8-bit timer/event counter, in addition to on-board oscillator and clock circuits. For systems that require extra I/O capability, the 8021 can be expanded using
the 8243 or discrete logic.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8021 has bit handling
capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results from an instruction set consisting mostly of single byte instructions and no instructions over two bytes in length.
To minimize development problems and maximize flexibility, an 8021 system can be easily designed using the 8021 emulation board, EMB-21. The EMB-21 contains a 40-pin socket which can accommodate either the 8748 shipped with the board
or an ICE-48 plug_ Also, the necessary discrete logic to reproduce the 8021 's additional I/O features is included.
PIN CONFIGURATION
P22
Vee
P23
P21
P20
P17
P16
P15
PROG
POO
P01
P02
POl
P04
P05
P06
P07
ALE
T1
Vss
P1'
P13
BLOCK DIAGRAM
LOGIC SYMBOL
XTAL{
PORT
#
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
0
:;:
:l
Q
2
2
2
2
2
2
$
"
~
0
u
";:;
"E
j::
u
c
~
In
2
1
2
2
2
2
10-8
Cycle
Jump on A Zero
Jump on A not Zero
Jump on Tl = 1
Jump on Tl = 0
Jump on timer flag
2
2
2
2
2
2
2
2
2
2
2
Jump to subroutine
2
2
2
1
1
2
addr
Jump on Carry
addr
addr
addr
addr
addr
addr
Jump on Carry =
CALL
RET
'=
1
a
Return
CLR
CPL
C
C
Clear Carry
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCHD
MOVP
A,R
A,@R
A,#data
R,A
@R,A
@R,#data
A,R
A,@R
A,@R
A,@A
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Exchange A and register
Exchange A and data memory
Exc'hange hibble of A and register
Move to' A from current page
MOV
MOV
STRT
STRT
STOP
A,T
T,A
T
CNT
TCNT
Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
NOP
II:
.<:
JC
JNC
JZ
JNZ
JTl
JNTl
JTF
Bytes
Description
Mnemonic
R,#data
2
2
2
Complement Carry
No Operati on
2
2
2
1
2
2
1
2
1
2
8021
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under" Absolute M>!xi--"
mum Rati ngs" may cause permanent damage to the device. THls a
is
Ambient Temperature Under Bias ......... oOe to 70°C
Storage Temperature ........... , .. -65°C to +150 oe
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . . -0.5V to + 7V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . .. 1 W
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operationa' -sec~
tions of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
D.C. AND OPERATING CHARACTERISTICS
TA=oOet070oe, Vee=5.5V±1V, Vss=OV
Limits
Symbol
Parameter
Max.
Unit
·0.5
0.8
V
Min.
Typ.
Test Conditions
VIL
Input Low Voltage (All except XTAL 1, XTAL2)
VIH
Input High Voltage (All except XTAL 1, XTAL2)
2.0
Vee
V
Vee = 5.0V ±10%
VIH1
Input High Voltage (All except XT AL 1, XTAL2)
3.0
Vee
V
Vee = 5.5V ±1V
VOL
Output Low Voltage
0.45
V
IOL = 1.6 mA
VOL1
Output Low Voltage (P10, P11)
2.5
V
IOL=7mA
VOH
Output High Voltage (All unless Open Drain)
V
IOH = 50/lA
IOL
Output Leakage Current (Open Drain Option Port 0)
lee
Vee Supply Current
2.4
-10
/lA
60
mA
Vee> VIN > Vss +0.45
A.C. CHARACTERISTICS
T A = o°c to 70°C, Vee = 5.5V ±1 V, Vss = OV
Symbol
Min.
Max.
Unit
tCY
Cycle Time
Parameter
10.0
50.0
/lsec
LlF
Oscillator Frequency Variation -Resistor Mode
-20
+20
%
A.C. TEST CONDITIONS
. Control Outputs: CL = 80 pF, RL = 2.2K/4.3K
10-9
Test Conditions
3 MHz XTAL = 10 /lsec
F = 2.5 MHz
,0"
inter
8048/8748/8035
SINGLE COMPONENT 8-BIT MICROCOMPUTER'},.
- 8048 Mask Programmable ROM
-8748 User Programmable/Erasable EPROM
-8035 External ROM or EPROM
• 8-Bit CPu, ROM, RAM, I/O in
Single Package
"','
• 1K X 8 ROM/EPROM
64 X 8 RAM
271/0 Lines
• Interchangeable ROM and EPROM
Versions
:",~1{'
• Interval Timer/Event Counter
:~"
• Easily Expandable Memory and I/O <'1';
• Compatible with 8000 Series '-eripherl'-'
• Single SV Supply
• 2.S ~sec and s.o ~sec Cycle Versions:
All Instructions 1 or 2 Cycles
• Over 90 Instructions: 70% Single Byte
• Single Level Interrupt
,;
,~~
The Intel@> 8048/8748/8035 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel),
N-channel silicon gate MOS process,
' :",
;~ 'f,
The 8048 contains a 1K x 8program memory, a 64x 8 RAM data memory,27 1/0 lines,and an 8-bit timer/count~i'irfiaditi'i;,~ ,
to onboard oscillator and clock circuits, For systems that require extra capability, the 8048 can be eXP}lhatia usl:nil
standard memories and MCS-80'· (8080A) peripherals, The 8035 is the' equivalent of an 8048 without program r:il~inorY' '
The 8035L has the RAM power down mode of the 8048 while the 8035 does not.
" ~;To reduce development problems to a minimum and provide maximum flexibility, three interchangeable pin-compatibl~'
versions of this single component microcomputer exist: the 8748with user-programmable and erasable EPROM p~()grllrji~,
memory for prototype and preproduction systems, the 8048 with factory-programmed mask ROM program mei1:1ory fO,("
low cost, high volume production, and the 8035 without program memory for use with external program merflprles: ::
This microprocessor is designed to be an efficient controller as well as an arithmetic processor, The 8048 has extertsive btl \
handling capability as well as facilities for both binary and BCD arithmetic, Efficient use of program memory'reslitts frc)rif.~;;
an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length';;:'- ;;;~ ,
,-i
0
:;;; MOVA, PSW
MOV PSW, A
~
C XCH A, R
XCHA,@R
XCHD A,@R
MOVXA,@R
MOVX@R,A
MOVPA,@A
MOVP3 A,@A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
And immediate to port
Or immediate to port
CALL
RET
RETR
CLR
CPL
CLR
.l2
LL CPL
CLR
CPL
Or data memory to A
1
2
Mnemonic
.'"
Or register to A
Or immediate to A
Exclusive or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Description
Jump to subroutine
Cycles
2
2
2
2
1
2
1
2
2
2
2
2
Return
Return and restore status
Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
Move external data memory to A
Move A to external data memory
Move to A from current page
Move to A from page 3
Read timer/counter
Load timer/cou nter
Start timer
Start cou nter
Stop timer/counter
Enable timer/counter interrupt
Disable timer/counter interrupt
EN I
DIS I
SEL RBO
SEL RBl
SEL MBO
SEL MBl
ENTO CLK
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output on TO
NOP
No operation
Enable external interrupt
Disable external interrupt
Mnemonics copyright Intel Corporation 1976
10-12
Bytes
1
2
2
2
2
8048/8748/8035
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ........... DoC to 70°C
Storage Temperature ................... -65°C to +150 oe
Voltage On Any Pin With Respect
to Ground ............................. -O.5V to +7V
Power Dissipation .............................. 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
Symbol
Parameter
'COMMENT'
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This IS a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
speCification is not implied
TA = o°c to 70°C, Vee = Voo = +5V ±10%*, Vss= ov
limits
Typ.
Min.
Unit
Max.
Test Conditions
V IL
Input Low Voltage
(All Except XTAL1, XTAL2)
-.5
.8
V
V IH
Input High Voltage
(All Except XTAL 1,XTAL2,RESET)
2.0
Vee
V
V IH1
Input High Voltage (R ESET,XTAL1)
3.0
Vee
V
VOL
Output Low Voltage
(BUS, RD, WR, PSEN, ALE)
.45
V
IOL = 2.0mA
Vall
Output Low Voltage
(All Other Outputs Except PROG)
.45
V
IOL = 1.6mA
VOL2
Output Low Voltage (PROG)
.45
V
IOL = 1.0mA
V OH
Output High Voltage
(BUS, RD, WR, PSEN, ALE)
2.4
V
IOH = 100J.IA
VOH1
Output High Voltage
(All Other Outputs)
2.4
V
IOH = 50J.IA
IlL
Input Leakage Current
(Tl, EA, I NT)
±10
/1A
VSSVSS +.45
100
V DO Supply Current
10
20
mA
Total Supply Current
65
135
mA
100
+ Icc
A.C. CHARACTERISTICS
Symbol
-
TA = o°c to 70°C, Vcc = Voo = +5V ±1 0% *, VSS = OV
Parameter
8048/8748
8035/8035L
Min. Max.
8748-8
8035-8
Min. Max.
Unit
tLL
ALE Pulse Width
400
600
ns
tAL
Address Setup to ALE
150
150
ns
Conditions (Note 1)
tLA
Address Hold from ALE
80
80
ns
tcc
Control Pulse Width (PSEN, RD, WR)
900
1500
ns
tow
Data Setup before WR
500
640
ns
two
Data Hold After WR
120
120
ns
CL = 20pF
tey
Cycle Time
2.5
4.17 15.0
/1S
6 MHz XTAL
(3.6MHz XTAL for -8)
tOR
Data Hold
tRO
PSEN, RD to Data In
tAW
Address Setup to WR
tAD
Address Setup to Data In
tAFC
Address Float to RD, PSEN
'Standard 8748 and 8035 ±5%, ±10% available.
15.0
0
200
0
500
230
ns
ns
ns
260
1450
950
0
Note1:
200
750
0
Control Outputs:
BUSOutputs:
1()'13
ns
ns
CL = 80 pF
CL = 150 pF, tCY
=
25).ts
8048/8748/8035
A.C. CHARACTERISTICS
TA
= O°C
to 70°C, Vee
Symbol
tcp
= 5V±10%
Parameter
Min.
Max.
Unit
Port Control Setup Before Falling
Edge of PROG
110
tpc
Port Control Hold After Falling
Edge of PROG
140
ns
tpR
PROG to Time P2 Input Must Be Valid
810
ns
ns
tDP
Output Data Setup Time
220
ns
tPD
Output Data Hold Time
65
ns
tPF
Input Data Hold Time
110
ns
tpp
PROG Pulse Width
tpL
tLP
1510
ns
Port 2 I/O Data Setup
400
ns
Port 2 I/O Data Hold
150
ns
WAVEFORMS
PORT 2 TIMING
ALE
..J
EXPANDER
PORT
OUTPUT
EXPANDER
PORT
INPUT
PROG
10·14
Test Conditions
8048/8748/8035
WAVEFORMS
PROGRAMMING, VERIFYING, AND
ERASING THE 8748 EPROM
Programming Verification
Instruction Fetch From External Program Memory
In brief, the programming process consists of: activating
the program mode, applying an address, latching the
address, applying data, and applying a programming pulse.
Each word is programmed completely before moving on to
the next and is followed by a verification step. The follow·
ing is a list of the pins used for programming and a description of their functions:
-'L-L-----1---'cV-----'1
1_-'
ALE
J
L-I_ _ _----Ji-I---'L
BUS
Read From External Data Memory
ALE
J
L
Pin
Function
XTAL1
Clock Input (1 to 6MHz)
Reset
Initialization and Address Latching
Test 0
EA
Selection of Program of Verify Mode
BUS
Address and Data Input Data Output
During Verify
P20-1
Address Input
VDD
Programming Power Supply
PROG
Program Pulse Input
ProgrammingNerification Sequence
r'cc-I~I---------------~I
RESET +5V
o ..=-;:::::='--,BUS
TEST
'AFc-1
BUS
Activation of Program/Verify Modes
I~OAT'NG-I t='OR
+5~ - ,
I
AND PROG CAN
BE DRIVEN ONL v - - - - - - - - . j
DURING THIS TIME
I
EA+:~~r----------------
~ --FL-O-A-T'-NG--1
- tAD -
I.'RO·I
P20·21
V
----<~A~O~OR~E~SS~As~-AsL)_--------
+25V
,------,
00 ~v---------~!
'L
_ _ _ _ __
PROG + 5 V _ , ._ _ _ _ _ _ _
+2_5V~..----
+ov
The ProgramNerify sequence is:
Write to External Data Memory
ALE
J
1.
L
V DD = Sv, Clock applied or internal oscillator operating,
RESET = OIl, TEST 0 = Sv, EA = Sv, BUS and PROG
floating.
2.
Insert 8748 in programming socket
3.
TEST 0
4.
EA = 2Sv (activate program mode)
S.
Address applied to BUS and P20-1
6.
RESET = 5v (latch address)
= 011 (select program mode)
BUS
7.
Data applied to BUS
8.
V DD = 2Sv (programming power)
9.
PROG = 011 followed by one SOms pulse to 2Sv
10.
V DD
11.
TEST 0
= Sv
= Sv (verify mode)
12.
Read and verify data on BUS
WARNING:
13.
TEST 0 = 011
An attempt to program a missocketed 8748 will result in severe
damage to the part. An indication of a properly socketed part is the
appearance of the ALE clock output. The lack of this clock may
be used to disable the prOgrammer.
14.
RESET = 011 and repeat from step S
lS.
Programmer should be at conditions of step 1 when 8748
is removed from socket.
10-15
8048/8748/8035
Data show that constant exposure to room level flourescent lighting could erase the typical 8748 in approxmately 3 years wh ile it would take approximately 1 week
to cause erasure when exposed to direct sunlight. If the
8748 is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels are available
from Intel which should be placed over the 8748 window
to prevent unintentional erasure.
Programming Options
The 8748 EPROM can be programmed by either of two
Intel products:
1. PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP-101 or UPP-102)
peripheral of the Intellec@ Development System with a
UPP-848 Personality Card.
The recommended erasure procedure for the 8748 is exposure to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity X exposure time) for erasure should be a minimum of 15W-sec/cm 2 • The erasure time with this dosage
is approximately 15 to 20 minutes using an ultraviolet lamp
with a 120001.lW/cm 2 power rating. The 8748 should be
placed within one inch from the lamp tubes during erasure.
Some lamps have a filter on their tubes and this filter
should be removed before erasure.
8748 Erasure Characteristics
The erasure characteristics of the 8748 are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A).
It should be noted that sunlight and certain types of flourescent lamps have wavelengths in the 300D-4000A range.
WAVEFORMS
Combination ProgramNerify Mode (EPROM's Only)
PROGRAM --------+>---vERFY-1 ••- - - - PROGRAM
'TW-TO
tww _ _
DBo-DS,
J--
DATA TO BE
PROGRAMMED VALID
-
- - { NEXT ADDR
VALID
C
NEXT
ADDRESS
LAST
ADDRESS
Verify Mode (ROM/EPROM)
TO,RESET
~
/
\'--.- - - - '
DBa- DB7
:=J--
ADDRESS
10-71 VALID
\'----_--1/
\'-----
X
---{
NEXT
...._ _A_D_D_R_ES_S_ _•
__________-J)(~_________
A_D_D_R_E_SS_I_8-_9_IV_A_L_ID________
.
NEXTDATA } OUTVALI~
_J)(~___________
N_E_X_T_A_D_DR_E_SS
__
VA_L_I_D_______________
3. THE FOLLOWING CONDITIONS MUST BE MET.
es=TIL'1'
NOTES.
1. PROG MUST FLOAT IF EA IS LOW Ii •••• " 25VI, OR IF TO = 5V FOR THE 8741.
FOR THE 8041 PROG MUST ALWAYS FLOAT.
2. VEAH FOR 8041-11.4V MIN .• 12.6V MAX.
AO= TTL '0'
THIS CAN BE DONE USING 10K RESISTORS TO Vee, Vss RESPECTIVELY.
4. X1 AND Xl DRIVEN BY 3 MHz CLOCK WILL GIVE 5 psec tcy. THIS IS GOOD
FOR -8 PARTS AS WELL AS NON -8 PARTS.
.
10-16
8048/8748/8035
;
..
AC TIMING SPECIFICATION FOR PROGRAMMING
TA = 25°C
± 5°C, Vee = 5V ± 5%, Voo = 25V ± 1V
Min.
Parameter
Symbol
tAW
Address Setup Time to RESET f
4tcy
tWA
Address Hold Time After RESET f
4tcy
tow
Data in Setup Time to PROG f
4tcy
two
Data in Hold Time After PROG I
4tcy
tPH
RESET Hold Time to Verify
4tcy
tvDow
VDo
4tcy
tv DOH
VDD Hold Time After PROG I
0
tpw
Program Pulse Width
50
tTw
Test 0 Setup Time for Program Mode
4tcy
tWT
. Test 0 Hold Time After Program Mode
4tcy
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
Max.
Unit
60
MS
Test
Col1d1t1oRt,t.':; i
4tcy
tr. tf
VDD and PROG Rise and Fall Times
0.5
tCY
CPU Operation Cycle Time
5.0
tRE
RESET Setup Time Before EA I
4tcy
2.0
j.lS
j.lS
Note: If Test 0 is high too can be triggered by RESEi' I.
DC SPECIFICATION FOR PROGRAMMING
TA
= 25°C ± 5°C,
Symbol
Vee
= 5V ± 5%,
Voo
= 25V ± lV
Min.
Max.
Unit
24.0
26.0
V
VDD Voltage Low Level
4.75
5.25
V
PROG Program Voltage High Level
21.5
24.5
V
0.2
V
Parameter
VDOH
VDD Program Voltage High Level
VDDL
VPH
VPL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
24.5
V
VEAL
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
mA
IPROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
10-17
21.5
Test Conditions
inter
8748-4 I 8035-4
SINGLE COMPONENT 8-BIT MICROCOMPUTER
• 8748-4 User Programmable/Erasable EPROM
• 8035-4 External ROM or EPROM
• 8-Bit CPU, ROM, RAM, I/O in Single
Package
• Interchangeable with 8048 ROM Version
• Single 5V Supply
• 2.5 J,Lsec Cycle. All Instructions 1 or 2
Cycles
• Over 90 Instructions: 70% Single Byte
• 1K x 8 EPROM (8748-4)
64 x 8 RAM
27 I/O Lines
• Interval Timer/Event Counter
• Easily Expandable Memory and I/O
• Compatible with MCS-80™/MCS-85TM
Peripherals
• Single Level Interrupt
The Intel® 8748-4/8035-4 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's
N-channel silicon gate MOS process. The 8748-4 and the 8035-4 are the equivalent of the 8748 and 8035 except in their
ability to interface to an 8243 I/O Expander device. The Standard 8748/8035 can input or output from the 8243. The 87488748-4/8035-4 can use the 8243 as an output expander only.
"
The 8748-4 contains a 1Kx8 program memory, a 64x8 RAM data memory, 27 I/O lines, and an 8-bit timer/counter in
addition to on-board oscillator and clock circuits. For systems that require extra capability, the 8748-4 can be expanded using
standard memories and MCS-80tm (8080A) peripherals. The 8035-4 is the equivalent of an 8748-4 without program memory.
To reduce development problems to a minimum and provide maximum flexibility, three interchangeable pin-compatible
versions of this single component microcomputer exist: the 8748-4 with user-programmable and eraseable EPROM program
memory for prototype and preproduction systems, the 8048 with factory-programmed mask ROM prog"ram memory for
low cost, high-volume production, and the 8035-4 without program memory for use with external program memories.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8048 has extensive bit
handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results from an
instruction set consisting mostly of single-byte instructions and no instructions over two bytes in length.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
8748-4
8035-4
10-18
8748-4/8035-4
PIN DESCRIPTION
Designation
Pin #
Function
Designation
Vss
20
Circuit GND potential
RO
Voo
26
Programming power supply; +25V
during program, +5V during operation for both ROM and PROM.
Pin #
8
Function
Output strobe activated during a
BUS read. Can be used to enable
data onto the BUS from an external
device.
Used as a Read Strobe to External
Data Memory. (Active low)
: Vee
PROG
40
Main power supply; +5V during
operation and programming.
25
Program pulse (+25V) input pin
during 8748 programming.
Output strobe for 8243 I/O
expander.
Pl0-P1.7
Port 1
P20-P27
Pprt 2
00-07
BUS
27-34
8-bit quasi-bidirectional port.
21-24
35-38
8-bit quasi-bidirectional port.
12-19
'T,{}
,"
~~~~,
39
-':'-
HilT
6
Input which is used to initialize the
processor. Also used during PROM
programming verification, and
power down. (Active low)
WR
10
Output strobe during a BUS write.
(Active 10w)(Non TTL VIH)
ALE
11
P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit I/O expander
bus for 8243.
Address Latch Enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Input pin testable using the conditional transfer instructions JTO
and JNTO. TO can be designated as
a clock output using ENTO ClK
instruction. TO is a Iso used during
programming.
.'-,;"--.
4
Used as write strobe to External
Data Memory.
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives
the addressed instruction under the
control of PSEN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
'oc
RESET
Input pin testable using the JT1
and JNT1 instructions. Can be designated the timer lcounter input using
the STRT CNT instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
10-19
PSEN
9
Program Store Enable. This output
occurs only during a fetch to external program memory. (Active low)
SS
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction. (Active low)
EA
7
External access input which forces
all program memory fetches to reference external memory. Useful
for emulation and debug, and
essential for testing and program
verification. (Active high)
XTALl
2
One side of crystal input for internal oscillator. Also input for external source. (Not TTL Compatible)
XTAl2
2
Other side of crystal input.
8748-4/8035-4
INSTRUCTION SET
Mnemonic
ADDA,R
ADDA,@R
ADD A, #data
ADDCA,R
ADDCA,@R
ADDC A, #data
ANLA, R
ANLA,@R
ANL A, #data
ORLA, R
ORLA,@R
.!l!
ORLA, #data
E XRLA, R
XRLA,@R
« XRLA, #data
INCA
DECA
CLR A
CPLA
DAA
SWAP A
RLA
RLCA
RR A
RRCA
a
"
""
"
S
l!-
eS"
...
.:
..
I
'r
II:
Description
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate iNith carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
Bytes
Cy.cle
1
2
2
1
1
2
2
..
,5 CALL
S RET
-§ RETR
e
.
~
.
Description
Bytes
Jump to subroutine
Return
Return and restore status
2
Cycl ••
2
2
2
UI
1
1
2
2
1
1
1
2
2
2
:i
CLR C
CPL C
at CLR FO
.!l!
u. CPL FO
CLR Fl
CPL Fl
.
1
~
~
~
C
INA, P
OUTL P,A
ANL P, #data
ORL P, #data
INSA, BUS
OUTL BUS,A
ANL BUS,#data
ORL BUS,#data
MOVDP,A
ANLD P, A
ORLD P,A
I nput port to A
Output A to port
And immediate to port
Or immediate to port
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
Output A to expander port
And A to expander port
Or A to expander port
INCR
INC@R
DECR
Increment register
Increment data memory
Decrement register
JMP addr
JMPP@A
DJNZ R,addr
JCaddr
JNC addr
J Z addr
JNZ addr
JTOaddr
JNTO addr
JTl addr
JNTl addr
JFO addr
JFl addr
JTF addr
JNI addr
JBb addr
Jump unconditional
2
Jump indirect
Decrement register and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zerQ
Jump on A not zero
Jump on TOa 1
Jump on TO = 0
Jump onT1 = 1
Jump on T1 = 0
Jump on FO= 1
Jump on Fl = 1
Jump on timer flag
Jump on INT = 0
Jump on accumulator bit
1
1
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
MOVA, T
Iii MOVT,A
STRTT
STRTCNT
STOP TCNT
,§ EN TCNTI
IDIS TCNTI
"
~
e1:
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MOVA,R
MOVA,@R
MOV A, #data
MOVR,A
MOV@R,A
MOV R, #data
MOV @R,#data
MOVA, PSW
MOV PSW, A
XCH A, R
XCHA,@R
XCHDA,@R
MOVXA,@R
MOVX@R,A
MOVPA,@A
MOVP3A,@A
1:
8
"""c
Mnemonic
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
Move reg ister to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
Move external data memory to A
Move A to externa I data memory
Move to A from current page
Move to A from page 3
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter interrupt
Disable timer/counter interrupt
EN I
DISI
SEL RBO
SEL RBl
SEL MBO
SEL MBl
ENTO CLK
Enable external interrupt
Disable external interrupt
Select register benk 0
Select register bank 1
Select memory be n k 0
Select memory benk 1
Enable clock output on TO
NOP
No operation
Mnemonics copyright Intel Corporation 1976,1977
10-20
1
1
2
2
1
1
1
2
2
2
2
1
2
2
2
2
8748-4/8035-4
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ........... ooe to 70°C
Storage Temperature ................... -65°C to +150 oe
Voltage On Any Pin With Respect
to Ground ............................. -0.5V to +7V
Power Dissipation .............................. 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
Symbol
Parameter
Min.
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied,
TA = o°c to 70°C, Vee = V OD = +5V ±10%*, Vss= ov
Limits
Typ.
Max.
Unit
V il
Input Low Voltage
(All Except XTAL1, XTAL2)
-.5
.8
V
V IH
Input High Voltage
(All Except XTAL1,XTAL2,RESET)
2.0
Vee
V
3.0
Test Cond itions
V IH1
Input High Voltage (R ESET,XTAL 1)
Vee
V
VOL
Output Low Voltage
(BUS, RD, WR, PSEN, ALE)
.45
V
IOl = 2.0mA
VOLl
Output Low Voltage
(All Other Outputs Except PROG)
.45
V
IOl = 1.6mA
V OH
Output High Voltage
(BUS, RD, WR, PSEN, ALE)
2.4
V
IOH = 100}JA
VOH1
Output High Voltage
(All Other Outputs)
2.4
V
IOH = 50}JA
III
Input Leakage Current
(T1, EA, INT)
±10
/1A
Vss';;V IN';;Vee
IOl
Output Leakage Current (Bus, TO)
(High Impedance State)
-10
/1A
Vee :>VIN>VSS +.45
100
Power Down Supply Current
10
20
mA
TA = 25°C
100 + lee
Total Supply Current
65
135
mA
TA = 25°C
A.C. CHARACTERISTICS
Symbol
TA = o°c to 70°C, Vee = voo = +5V ±5%*, vss= OV
Parameter
Min.
Max.
Unit
Conditions
tll
ALE Pulse Width
400
ns
tAL
Address Setup to ALE
150
ns
tlA
Address Hold from ALE
80
ns
tee
Control Pulse Width (PSEN, RD, WR)
900
ns
tow
Data Setup Before WR
500
ns
two
Data Hold After WR
120
ns
Cl = 20pF
tey
Cycle Time
2.5
15.0
Jl.S
6 MHz XTAL
tOR
Data Hold
a
200
ns
tRO
PSEN, RD to Data In
500
ns
tAw
Address Setup to WR
tAO
Address Setup to Data In
tAFe
Address Float to RD, PSEN
A.C. TEST CONDITIONS
Control Outputs:
BUS Outputs:
'Standard 8748 and 8035 ±5%, ±10% available.
ns
230
950
C l =80pF
C l = 150 pF
10·21
ns
ns
0
tey = 2.5/1s
I
8748-4/8035-4
WAVEFORMS
Instruction Fetch From External Program Memory
I--~t~--J-tcv--J·I
ALE
J I______:-1---L
BUS
Read From External Data Memory
ALE
J
L
j--tcc-J
----~I
BUS
I
----
~I
tAFC--j I~OATING1 t:=tDR
FLOATING ~ --FL-O-A-T-IN-G--~I
I..
tAD~
Write To External Data Memory
ALE
J
L
-!----f4--1- two
FLOATING
BUS
10-22
inter
8049/8039
SINGLE COMPONENT 8-BIT MICROCOMPUTER
.8049 Mask Programmable ROM
.8039 External ROM or EPROM
• 8-Bit CPU, ROM, RAM, I/O in
Single Package
• 2K x 8 ROM
128 x 8 RAM
27 I/O Lines
• Interval Timer/Event Counter
• Easily Expandable Memory and I/O
• Compatible with MCS-80/85™ Peripherals
• Single 5V ±10% Supply
• 2.5 J.!sec Cycle; All Instructions
1 or 2 Cycles
• Over 90 Instructions: 70% Single Byte
• Pin Compatible with 8048/8748
• Single Level Interrupt
The Intel@ 8049/8039 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's Nchannel silicon gate MOS process.
The 8049 contains a 2K x 8 program memory, a 128 x 8 RAM data memory, 27 I/O lines, and an 8-bit timer/counter in
addition to on board oscillator and clock circuits. For systems that require extra capability, the 8049 can be expanded using
standard memories and MCS-80'''/MCS-85™ peripherals. The 8039 is the equivalent to an 8049 without program memory.
To reduce development problems to a minimum and provide maximum flexibility, two interchangeable pin-compatible
versions of this single component microcomputer exist: the 8049 with factory-programmed mask ROM program memory
for low-cost high volume production, and the 8039 without program memory for use with external program memories in
prototype and preproduction systems.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8049 has extensive bit
handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results from
an instruction set consisting mostly of single byte instructions and no instructions over two bytes in length.
LOGIC SYMBOL
PIN CONFIGURATION
BLOCK DIAGRAM
XTAL~
L:
RESETSINGLE
STEP
8049
WRITE
PAOGRAM
STORE
ENABLE
ADDRESS
LATCH
ENABLE
PORT
EXPANDER
STROBE
10-23
8049/8039
PIN DESCRIPTION
#
Function
Designation
VSS
V DD
20
Circuit GND potential.
RD
26
+5V during operation. Low power
standby pin.
Vee
40
Main power supply; +5V during
operation.
Designation
PROG
P10-P17
Port 1
P20-P27
Port 2
00-07
BUS
Pin
25
8-bit quasi-bidirectional port.
21-24
35-38
8-bit quasi-bidirectional port.
12-19
P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit I/O expander
bus for 8243.
T1
INT
6
Function
Output strobe activated during a
BUS read. Can be used to enable
data onto the BUS from an external
device.
RESET
4
Input which is used to initialize the
processor. Also used during verification, and power down. (Active
low)
WR
10
Output strobe during a BUS write.
(Active 10w)(Non TTL V1H)
ALE
11
True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Input pin testable using the cond itiona I transfer instruct ions JTO
and JNTO. TO can be designated as
a clock output using ENTO CLK
instruction.
39
#
Used as write strobe to External
Data Memory.
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives
the addressed instruction under the
control of PSEN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
TO
8
Used as a Read Strobe to External
Data Memory. (Active low)
Output strobe for 8243 I/O
expander.
27-34
Pin
Input pin testable using the JTl,
and JNTl instructions. Can be designated the timer/counter input using
the STRT CNT instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is {jisabled after a reset. Also
testable with conditional jump
instruction. (Active low)
10-24
Address Latch Enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
PSEN
9
Program Store Enable. This output
occurs only during a fetch to external program memory. (Active low)
SS
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction. (Active low)
EA
7
External Access input which forces
all program memory fetches to reference external memory. Useful
for emulation and debug, and
essential for testing and program
verification. (Active high)
XTAL1
2
One side of crystal input for internal oscillator. Also input for external source. (Not TTL Compatible)
XTAL2
3
Other side of crysta I input.
8049/8039
INSTRUCTION SET
S
.!I
'u"
E
'"
u
c(
Mnemonic
Description
ADDA,R
ADDA,@R
ADD A, #data
ADDCA, R
ADDCA,@R
ADDC A, #data
ANl A, R
ANlA,@R
ANl A, #data
ORlA, R
ORlA,@R
ORlA, #data
XRlA, R
XRl A,@R
XRl A, #data
INCA
DECA
ClR A
CPlA
DAA
SWAP A
RlA
RlCA
RRA
RRCA
Add
Add
Add
Add
Add
Add
And
And
And
INA, P
OUTlP, A
ANl P, #data
'5 ORl P, #data
S- INSA, BUS
0 OUTl BUS,A
ANl BUS,#data
.E ORl BUS,#data
MOVDA, P
MOVD P,A
ANlD P,A
ORlD P,A
'"
;...
.
Ii INCR
!i
'"
II
I¥:
.s:
u
c
.
as
INC@R
DECR
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
J Z addr
JNZ addr
JTO addr
JNTO addr
JTl addr
JNTI addr
JFO addr
JFl addr
JTF addr
JNI addr
JBb addr
register to A
data memory to A
immediate to A
register with carry
data memory with carry
immediate with carry
register to A
data memory to A
immed iate to A
Bytes
1
2
Cycle
Exclusive or data memory to A
Exclusive or immediate to A
Jump to subroutine
Return
Return and restore status
ClR C
CPl C
ClR FO
.!I
u. CPl FO
ClR Fl
CPl Fl
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear Flag 1
Complement Flag 1
e
2
2
2
1
2
1
2
2
2
2
2
.'"
Decrement A
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
Input Expander port to A
Output A to Expander port
And A to Expander port
Or A to Expander port
.
;:
0
~
~
0
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MOV A, T
MOVT,A
STRTT
STRT CNT
Ii! STOP TCNT
E
j: EN TCNTI
DIS TCNTI
e'C
Decrement register
Decrement register and skip
Jump on Carry = 1
Jump on Carry = 0
Jump on A Zero
Jump on A not Zero
Jump 'on TO = 1
Jump on TO= 0
Jump on T1 = 1
Jump on Tl = 0
Jump on FO= I'
Jump on Fl = 1
Jump on timer flag
Jump on INT = 0
Jump on Accumulator Bit
0
U
2
1
2
2
2
2
2
2
2
2
:l
2
2
2
2
2
MOVA, R
MOVA,@R
MOV A, #data
MOV R,A
MOV@R,A
MOV R, #data
MOV @R,#data
MOVA, PSW
MOV PSW, A
XCH A, R
XCHA,@R
XCHD A,@R
MOVXA,@R
MOVX@R,A
MOVPA,@A
MOVP3A,@A
~
§'"
Increment register
Increment data memory
Jump unconditional
Jump indirect
Bytes
Cycles
2
2
2
2
2
2
1
2
2
1
2
2
CI)
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
Or immediate to port
Description
c CAll
RET
11 RETR
Increment A
Input port to A
Output A to port
And immediate to port
Mnemonic
i
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register to A
..
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
Move external data memory to A
Move A to external data memory
Move to A from current page
Move to A from Page 3
Read Timer/Counter
load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter Interrupt
Disable Timer/Counter Interrupt
EN I
DISI
SEl RBO
SEl RBI
SEl MBO
SEl MBI
ENTO ClK
Disable external interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable Clock output on TO
NOP
No Operation
Enable external interrupt
Mnemonics copyright Intel Corporation 1976, 1977
10-25
1
1
2
2
2
2
8049/8039
Storage Temperature ............... -65°Cto+150°C
Voltage on Any Pin With
RespecttoGround ..................... . -0.5Vto+7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 Watt
'COMMENT: Stresses above thoS9'lil$teq
Maximum Ratings" may cause perm'a~ril'da
device. This is a stress rating only 'B.p'd,,: u
operation of the device at these or any othlfr.cp'nd~
above those indicated in the operational sections
thi
specification is not implied. Exposure to absdJute.,
maximum rating conditions for extended perioc!s miw
affect device reliabilitY.
D.C. AND OPERATING CHARACTERISTICS
TA = O°Cto 70°C, Vee = Voo = +5V ±10%, Vss = OV
ABSOLUTE MAXIMUM RATINGS*
AmbientTemperatureUnderBias
Symbol
........ 0°Ct070°C
or
Limits
Parameter
Min.
Test Conditions
Max.
Vil
Input Low Voltage
(All Except XTAL1, XTAL2)
-0.5
0.8
V
VIH
Input High Voltage
(All Except XT A L1, XT A L2, RESET)
2.0
Vee
V
VIHl
Input High Voltage (R ESET, XTAL 1)
3.0
Vee
V
VOL
Output Low Voltage
(BUS, RD, WR, PSEN, ALE)
0.45
V
IOl = 2.0mA
VOL1
Output Low Voltage
(All Other Outputs Except PROG)
0.45
V
IOl = 1.6mA
VOH
Output High Voltage
(BUS, RD, WR, PSEN, ALE)
2.4
V
IOH = 100MA
VOHl
Output High Voltage
(All Other Outputs)
2.4
V
IOH = 50MA
III
Input Leakage Current
(T1, EA, INT)
±10
IOl
Output Leakage Current (Bus, TO)
(High Impedance State)
-10
MA
Vee;;'VIN;;'VSS + 0.45
100
Power Down Supply Current
20
50
mA
TA = 25°C
75
140
mA
TA = 25°C
loo+lee Total Supply Current
A.C. CHARACTERISTICS
I
Unit
Typ.
pA
VSS';;VIN';;Vee
TA = o°c to 70°C, Vee = Voo = +5V ±10%, Vss = ov
8049/8039
Symbol
Unit
Parameter
Min.
Conditions
Max.
tll
ALE Pulse Width
400
ns
tAL
Address Setup to ALE
150
ns
tLA
Address Hold from ALE
80
ns
tee
Control Pulse Width (PSEN, RD, WR)
900
ns
tow
Data Set·Up Before WR
500
ns
two
Data Hold After WR
120
ns
Cl = 20 pF
tey
Cycle Time
2.5
15.0
MS
6 MHz XTAL
tOR
Data Hold
0
200
ns
tRo
PSEN, RD to Data In
tAW
Address Setup to WR
tAO
Address Setup to Data In
tAFe
Address Float to RD, PSEN
A.C. TEST CONDITIONS
500
230
Control Outputs: Cl
950
0
=
80 pF
10-26
ns
ns
ns
ns
BUS Outputs: Cl = 150 pF
tey = 2.5Ms
8049/8039
WAVEFORMS
Instruction Fetch From External Program Memory
1_--"
- tLL
ALE
--j---tcv------I
----'L
J
1...0-1_ _ _---'r--I
- tAFCI-tcc--!r-------------
--------~~~~
BUS
ADDRESS
INSTRUCTION
Read From External Data Memory
ALE
J
L
r-- tee-----l
--------~I
BUS
~I--------
''''I I";,"An.,1 t=''"
FLOATING~
I
'II
tAD
--F-LO-A-T-I-N-G---
l.. tRD-1
.,
Write To External Data Memory
ALE
J
L
BUS
FLOATING
10-27
inter
8243
MCS-48™ INPUT/OUTPUT EXPANDER
24-Pin DIP
• Single
5V Supply
• High Output
Drive
• Direct Extension
of Resident 8048 1/0
low Cost
• Simple
Interface to MCS-48™ Micro• computers
Four 4-Bit 1/0 Ports
• AND
• and OR Directly to Ports
• Ports
The Intel® 8243 is an input/output expander designed specifically to provide a low cost means of I/O expansion for the
MCS-48'· family of single chip microcomputers. Fabricated in 5 volts NMOS, the 8243 combines low cost, single supply
voltage and high drive current capability.
The 8243 consists of four 4-bit bidirectional static I/O ports and one 4-bit port which serves as an interface to the MCS-48
microcomputers. The 4-bit interface requires that only 4 I/O lines of the 8048 be used for I/O expansion, and also allows
multiple 8243's to be added to the same bus.
The I/O ports of the 8243 serve as a direct extension of the resident I/O facilities of the MCS-48 microcomputers and are
accessed by their own MOV, ANL, and ORL instructions.
BLOCK DIAGRAM
PIN CONFIGURATION
PORT 4
P50
Vee
P40
P5l
P4l
P52
P42
P53
P43
P60
CS
P6l
PROG
P62
P23
P63
P22
P73
P2l
P72
P20
P7l
GND
P70
PORT 5
PORT 2
'"~B
PORT 6
PORT 7
10-28
8243
Normally, a port will be in an output (write mode) or input
(read mode). If modes are changed during operation, the
first read following a write should be ignored; all following
reads are valid. This is to allow the external driver on the
port to settle after the first read instruction removes the
low impedance drive from the 8243 output. A read of any
port will leave that port in a high impedance state.
FUNCTIONAL DESCRIPTION
General Operation
The 8243 contains four 4-bit I/O ports which serve as an
extension of the on-chip I/O and are addressed as ports 47. The following operations may be performed on these
ports:
•
•
•
•
Transfer Accumulator to Port.
Transfer Port to Accumulator.
AND Accumulator to Port.
OR Accumulator to Port.
Sink Capability
The 8243 can sink 5 mA @ .4V on each of its 16 I/O lines
simultaneously. If, however, all lines are not sinking simultaneously or all lines are not fully loaded, the drive capability of any individual line increases as is shown by the
accompanying curve.
All communication between the 8048 and the 8243 occurs
over Port 2 (P20-P23) with timing provided by an output
pulse on the PROG pin of the processor. Each transfer
consists of two 4-bit nibbles:
For example, if only 5 of the 16 lines are to sink current at
one time, the curve shows that each of those 5 lines is
capable of sinking 10 mA @ .4V lif any lines are to sink
10 mA the totalloL must not exceed 50 mA or five 10 mA
loads).
The first containing the "op code" and port address and
the second containing the actual 4-bits of data.
A high to low transition of the PROG line indicates that
address is present while a low to high transition indicates
the presence of data. Additional 8243's may be added to
the 4-bit bus and chip selected using additional output
lines from the 8048/8748/8035.
Example: How many pins can drive 5 TTL loads 11.6 mAl
assuming remaining pins are unloaded?
10L = 5 x 1.6 mA = 8 mA
,IOL = 70 mA from curve
# pins = 70 mA + 8 mA/pin
Power On Initialization
P21
P20
0
0
0
1
0
Address Code
Port
Port
Port
Port
4
5
6
7
Example: This example shows how the use of the 20 mA
sink capability of Port 7 affects the sinking
capability of the other I/O lines.
P23 P22 Instruction Code
0
0
0
0
= 8.75 = 8
In this case, 81ines can sink 8 mA for a total of 64
mA. This leaves 6 mA sink current capability
which can be divided in any way among the
remaining 8 I/O lines of the 8243.
Initial application of power to the device forces
input/output ports 4, 5, 6, and 7 to the tri-state and port 2 to
the input mode. The PROG pin may be either high or low
when power is applied. The first high to low transition of
PROG causes device to exit power on mode. The power on
sequence is initiated if Vee drops below 1V.
An 8243 will drive
simultaneously.
Read
Write
ORlO
ANlO
the
following
loads
2 loads - 20 mA @ 1V Iport 7 onlyl
8 loads - 5 mA @ .4V
6 loads - 3.2 mA @ .4V
Is this within the specified limits?
Write Modes
,IOl = (2 x 201 + 18 x 51 + 16 x 3.21 = 99.2 mA from
the curve: for 10l = 5 mA. ,IOl = 100 mA since
99.2 mA < 100 mA the loads are within specified
limits.
The device has three write modes. MOVO Pi, A directly
writes new data into the selected port and old data is lost.
ORlO Pi,A takes new data, OR's it with the old data and
then writes it to the port. ANlD Pi,A takes new data AND's
it with the old data and then writes it to the port. Operation
code and port address are latched from the input port 2 on
the high to low transition of the PROG pin. On the low to
hig h transition of PROG data on port 2 is transferred to the
logic block of the specified output port.
Although the 20 mA @ 1V loads are used in
calculating ,IOl, it is the largest current
required @ .4V which determines the maximum
allowable dOL.
125
:<
After the logic manipulation is performed, the data is
latched and outputed. The old data remains latched until
new valid outputs are entered.
.§
-:, 100
9
..
':
z
Read Mode
75
"'
0:
0:
:::>
The device has one read mode. The operation code and
port address are latched from the input port 2 on the high
to low transition of the PROG pin. As soon as the read
operation and port address are decoded, the appropriate
outputs are tri-stated, and the input buffers switched on.
The read operation is terminated by a low to high
transition of the PROG pin. The port (4, 5, 6 or 7) that was
selected is switched to the tri-stated mode while port 2 is
returned to the input mode.
"'z"
;;;
....«
....
50
GUARANTEED WORST CASE
CURRENT SINKING
CAPABILITIES OF ANY I/O
PORT PIN VS. TOTAL SINK
CURRENT OF ALL PINS
25
0
°0~~1~2~3~~4~5~6~~7~8~9~~10~1~1~1~2~13
MAXIMUM SINK CURRENT ON ANY PIN@,4(10Ll
MAXIMUM IOLWORST CASE PIN (mA)
Figure 1. Sink Capability
10·29
I
8243
PIN DESCRIPTION
-=os
I/O
P4
IV-~-V I/O
P5
1',,--"----,/ I/O
P6
IV-~--,/
I/O
P7
I'v--~--v
I/O
Symbol
Pin No.
Function
PROG
7
Clock Input. A high to low
transistion on PROG signifies
that address and control are
available on P20-P23. and a low
to high transition signifies that
data is available on P20-23.
6
Chip Select Input. A high on CS
inhibits any change of output or
internal status.
11-8
Four-bit bidirectional port contains the address and control
bits on a high to low transition
of PROG. During a low to high
transition contains the data for
a selected output port if a write
operation, or the data from a
selected port before the low to
high transition if a read operation.
PROG
TEST
INPUTS
8048
8243
DATA IN
P20-P23
P2
Figure 2. Expander Interface
PROG
P20-P23
~'--
P20-P23
_ _--JI
-<
X'--_--J)>--
ADDRESS (4-8IT8)
DATA (4-BIT5)
GND
BITS 3,2
BITS 1,0
0°1
01
10
P40-P43
P50-P53
P60-P63
P70-P73
PORT
ADDRESS
1'-.1
12
2-5
1,23-21
20-17
13-16
Figure 3. Output Expander Timing
Vee
24
OV supply.
Four-bit bidirectional 1/0 ports.
May be programmed to be input
(during read), low impedance
latched output (after write) or a
tri- state (after read!. Data on
pins P20-23 may be directly
written. ANDed or ORed with
previous data.
+5V supply.
I
PORT 1
8048
PORT2
PROG~--------------+----------------~----------------~----------------J
Figure 4. Using Multiple 8243's
10-30
8243
...
<>
y..
,l'""
,'\t.; ~ ,'.',:~;~
COMMENT: Stresses above those listed un¢er ~lAbsolute
Maximum Ratings" may cause permanent d~!ti~,Jo the
device. This is a stress rating only and functio,;i1t~(Ua
tion of the device at these or any other condjtfons-iB~ .
those indicated in the operational sections of thisspc;lf(!
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device'
reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... O°C to 70°C
Storage Temperature .............. _65°C to +150°C
Voltage on Any Pin
With Respect to Ground ............ -0.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. AND OPERATING CHARACTERISTICS
TA
= o°c to 70°C, Vee = 5V ±1 0%
Symbol
Parameter
Min.
Typ.
Max.
Units
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+0.5
V
VOLl
Output Low Voltage Ports 4-7
VOL2
Output Low Voltage Port 7
VOH1
Output High Voltage Ports 4-7
2.4
IILl
Input Leakage Ports 4-7
-10
IIL2
Input Leakage Port 2, CS, PROG
-10
VOL3
Output Low Voltage Port 2
ICC
Vee Supply Current
VOH2
Output VA Itage Port 2
IOL
Sum of all IOL from 16 Outputs
0.45
V
IOL = 5 mAo
1
V
IOL=20mA
20
/1 A
Vin = Vee to OV
Vin = Vee to OV
V
10
Test Conditions
10
/1A
.45
V
20
mA
100
mA
2.4
IOH= 240/1A
IOL = 0.6 mA
IOH= 100/1A
5 mA Each Pin
'See following graph for additional sink current capability.
A.C. CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Test Conditions
tA
Code Valid Before PROG
100
ns
ts
Code Valid After PROG
60
ns
20 pF Load
tc
Data Valid Before PROG
200
ns
80 pF Load
tD
Data Valid After PROG
20
ns
20 pF Load
tH
Floating After PROG
ns
20 pF Load
tK
PROG Negative Pulse Width
900
tcs
CS Valid Before/After PROG
50
tpo
Ports 4-7 Valid After PROG
tLP1
Ports 4-7 Valid Before/After PROG
tACC
Port 2 Valid After PROG
0
150
ns
ns
700
100
ns
100 pF Load
ns
750
10-31
80 pF Load
ns
80 pF Load
8243
WAVEFORMS
PROG
~----------------tK--------------~~
FLOAT
PORT 2
..
FLOAT
~'"
•
t ACC
OUTPUT
PORT 2
VALID
~tpo
PORTS 4·7
--+-
tiP
PORTS 4-7
OUTPUT
VALID
PR EVIOUS OUTPUT VALID
INPUT VALID
10·32
tiP
..._stlCS.: /. . . . . ,:SO. /
'\1
8S''''
tA\CroproceSSOrs
MCS·80/85™ MICROPROCESSORS
INTRODUCTION
The MCS-80 and MCS-85 have become the industry standard 8-blt microcomputer systems. Their wide us~ge i.s due to
many factors, among them total system support in terms of the largest family of state-of-the-art processors,
memories, and peripheral components. Many of these are described in the pages that follow. In addition, system
designers using the 8080A and 8085A have the benefit of the world's largest and most usable set of microcomputer
development tools (see section 13).
.
The MCS-85 components are of particular interest for new microcomputer deSigns. Systems designed around the
8085A and the new 8085A-2 offer the highest performance-to-cost ratios in the industry. Higher speed, Single power
supply requirement, and low component count while maintaining total MCS-80 software compatibility are key features
of the MCS-85 system.
.
8085A
CPU
•
PROVEN
PERFORMANCE
•
WEALTH OF
SOFTWARE
•
EXTENSIVE DEVELOP·
MENTTOOLS
•
NEW COMPONENTS
CONTINUALLY
BEING DEVELOPED
•
LOWCOST
Figure 1. MCS·ao™ - Foundation for MCS·SS™
Figure 2. MC8-8S™ - The New Industry Standard
11·2
TABLE OF CONTENTS
Recommended Products for MCS·80/85 Microcomputer Applications ...................................... 11·4
8·Bit Microprocessor ........................................................ 11·5
Single Chip 8·Bit N·Channel Microprocessor ................................... 11-11
M8080A
Single Chip 8·Bit N·Channel Microprocessor ................................... 11·19
8224
Clock Generator and Driver for 8080A CPU ..................................... 11·24
M8224
Clock Generator and Driver for 8080A CPU ..................................... 11·28
8801
Clock Generator Crystal for 8224/8080A . ...................................... 11·32
8228/8238
System Controller and Bus Driver for 8080A CPU ............................... 11·34
M8228
System Controller and Bus Driver for M8080A CPU .............................. 11·38
8085A
Single Chip 8·Bit N·Channel Microprocessor ................................... 11·43
8085A·2
Single Chip 8·Bit N·Channel Microprocessor ................................... 11·57
8155/8156
2048·Bit Static MOS RAM with I/O Ports and Timer .............................. 11·63
8202
Dynamic RAM Controller. .................................................. 11·76
8355
16,384·Bit ROM with I/O Ports ............................................... 11·77
8755A
16,384·Bit EPROM with I/O Ports ............................................. 11·84
8008/8008·1
8080A/8080A·1/8080A·2
11·3
RECOMMENDED PRODUCTS FOR
MCS·80/85 MICROCOMPUTER APPLICATIONS
Part
No.
Page
No.
Memory and 110 Expanders
for MCS-65
8155/8156
8355
8755A
8202
11-63
11-77
11-84
11-76
RAMs (Static)
8101A-4
8102A-4
8111A-4
5101
2114
2142
3-26
3-30
3-85
3-153
3-jt4
3-133
256x4
1Kx 1
256x4
258x4 CMOS
1Kx 4
1Kx 4
RAMs (Dynamic)
2104A-4
2107C
2117-4
3-36
3-60
3-117
4Kx1
4Kx 1
16Kx 1
RAM Support Circuits
3222
3232
3242
6-19
6-25
6-29
Refresh controller
Refresh counter/multiplexer
Refresh counter/multiplexer
ROMs
2308
8308
8316A
2316E
4-18
4-18
4-22
4-25
1Kx8
1Kx8
2Kx8
2Kx8
EPROMs
1702A-2
2704
8708
2708
2708L
2708-1
2716
4-5
4-38
Blank
4-38
4-38
4-38
4-44
256x8
512x8
1Kx8
1Kx8
1Kx8
1Kx
2Kx8
8205
8212
8214
8216
8224
8226
8228
8238
8251A
8253
8255A
8257
8259
8041/8741
8271
8273
8275
8278
8279
8294
12-11
12-17
12-31
12-38
12-24
12-38
11-34
11-34
12-46
12-65
12-76
12-98
12-111
12-3
12-123
12-142
12-165
12-188
12-198
12-209
1-8 decoder
8-bit latch
Priority unit
4-bit bus driver
Clock generator
4-bit bus driver
System controlier
System controlier
USART
Interval timer
PPI
DMA
Interrupt
Universal peripheral Interface
Floppy disk
SDLC
CRT
KYBD/display
KYBD/display
Data encryption
Function
Peripherals
I
Description
TACC
(n8)
8080A
8008
X
RAM-I/O-TIMER
ROM-I/O
EPROM-I/O
'. Dynamic RAM Controller
11-4
80&5
X
X
X
X
450
450
450
450
450
450
X
X
X
X
X
X
X
X
X
X
X
X
300
270
250
X
X
X
X
X
X
X
X
X
X
X
X
450
450
850
450
X
X
X
X
X
X
X
X
X
X
X
X
650
450
450
450
450
350
450
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8008/8008·1
8·BIT MICROPROCESSOR
• 48 Instructions, Data Oriented
• Instruction Cycle Time - 1.25 J..Is with
8008·1 or 20 J..Is with 8008
• Address Stack Contains 8 14·Bit
Registers (Including Program Counter)
Which Permit Nesting of Subroutines
Up to 7 Levels
• Directly Addresses 16K x 8 Bits of
Memory (RAM, ROM, or S.R.)
• Interrupt Capability
The Intel@ 8008 is a single chip MOS 8-bit parallel central processor unit (CPU) for the MCS-8 microcomputer system.
This CPU contains 6 8-bit data registers, an 8-bit accumulator, 2 8-bit temporary registers, 4 flag bits (carry, zero, sign,
parity), and an 8-bit parallel binary arithmetic unit which implements addition, subtraction, and logical operations. A
memory stack containing a 14-bit program counter and 7 14-bit words is used internally to store program and
subroutine addresses. The 14-bit address permits the direct addressing of 16K words of memory (any mix of RAM,
ROM, or S.R.).
The instruction set of the 8008 consists of 48 instructions including data manipulation, binary arithmetic, and jump to
subroutine.
The normal program flow of the 8008 may be interrupted through the use of the interrupt control line. This allows the
servicing of slow I/O peripheral devices while also executing the main program.
The ready command line synchronizes the 8008 to the memory cycle allowing any type or speed of semiconductor
memory to be used.
BLOCK DIAGRAM
0..0,
BIDIRECTIONAL
DATA BUS
11
DATA BUS
BUFFER
(8 BIT)
INTERNAL DATA BUS
I
1,1
(81
TEMP. REG.
a.
I
TEMP. REG.
b.
~
~
'NSTRUCTION I
REGISTER (8)
(8)
I
FLAG
FLlp·FLOPS
I
~
I- -
LEVEL NO.1
DECODER
AND
MACHINE
CYCLE
ENCODING
r==-
a:
I - ...Zw
~
"...~
-9V
+5V
I
J
STATUS
lll
SO S1 S2
INT
t
INT
READY
1
READY
'"
B
REG.
18'
(14)
C
REG.
181
(14)
D
REG.
18'
1
(14)
LEVEL NO.4
(14)
E
REG.
H
REG.
(14)
l
REG.
lEVEL NO.5
lEVEL NO.7
t
SYNC CLOCKS
l 1t
11-5
LEVEL NO.3
lEVEL NO.6
TIMING
AND
CONTROL
SYNC
LEVEL NO.2
¢1
62
II
ACCUMULATOR
181
(14)
INSTRUCTION
I
_
I
PROGRAM COUNTER
~
_
STACK
MULTIPLEXER
J
(8'i-
POWER {
][
1
,J
' - - ---",IARITHMETIC
LOGIC
UNIT
IALUI
su PPLIES
18 BITI
INTERNAL DATA BUS
ADDRESS
STACK
(14)
(14)
SCRATCH
PAD
181
(81
181
8008/8008·1
PIN DESCRIPTION
INTERRUPT
Vee
READY
(>1
'·'2
DATA
BUS
00 0 - - 9
10
Vee
Figure 1. Pin Configuration
00-0 7
BI-DIRECTIONAL DATA BUS. All address and
data communication between the processor and the
program memory. data memory. and I/O devices
occurs on these 8 lines. Cycle control information
is also available.
INT
INTERRUPT input. A logic "1" level at this input
causes the processor to enter the I NTE R RUPT
mode.
READY
READY input. This command line is used to synchronize the 8008 to the memory cycle allowing
any speed memory to be used.
SYNC
SYNC output. Synchronization signal generated by
the processor. It indicates the beginning of a machine cycle.
¢"¢2
Two phase clock inputs.
SO.S,.S2
MACHINE STATE OUTPUTS. The processor controls the use of the data bus and determines whether
it will be sending or receiving data. State signals
SO. S1. and S2. along with SYNC inform the peripheral circuitry of the state of the processor.
Vee +5V ±5%
Voo -9V ±5%
8008/8008·1
INSTRUCTION SET
Data and Instruction Formats
Data in the SOOS is stored in the form of S·bit binary integers. All data transfers to the system data bus will be
in the same format.
I
0 7 0 6 05 0 4 0 3 O2 0, DO
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored
in successive words in program memory. The .instruction formats then depend on the particular operation
executed.
TYPICAL INSTRUCTIONS
One BVII! InurucIlO"$
1° 7 °6 Os 04 03 02 0, 00 I
Regnier 10
OP CODE
lI~g,s'tr.
memory , .. I",,·"ce.
110 iI"lnmto'toc or logledl, rOtan! O.
return '"S!rUCIIO"!
Two evte I"struello",
OPCODE
1°7 °6 °5 04 03 02 0, DO I
OPERAND
Immtd,ale !"'lode instructIons
Three Bvte Instruction,
1°7 °6 Os 04 03 0,:1 01 00 I
001
I
I
1°
OP CODE
7 0 6 Os 04 03 02 0,
X
)(
05 04 03 02 01
00
lOW AOORESS
JUMP or CALL ,nsuucttOll"
HIGH ADDRESS'
'For thfO thIrd hvtt· 01 Ihls InSTructIon,
De
and D7 arl! "don', COIle" bIts
For the MCS·ST"a logic"," is defined as a high level and a logic "0" is defined as a low level.
Index Register Instructions
The load instructions do not affect the flag flip·flops. The increment and decrement instructions affect all flip·
flops except the carry
MNEMONIC
MINIMUM
STAT·ES
REOUIREO
(1)MOV'I.r2
lSI
I4!'JMOVr,M
181
MOV M,r
171
131 MVI,
181
INSTRUCTION CODE
05 04 03
~O, DO
~D6
,,
,
,, ,,
0 0
0 0
1
0 0
0
B
, ,
5 5
1
load mdex register r1 With the content of Index register r2.
,
Load memory register M With the content of index r'i!Qlster r.
0
0
S
1
S S S
1
0
B B B
0 0
B B
MVIM
191
0
0
,,, ,,
B
B
B B
B
B B B
INA r
lSI
lSI
0 0
0 0
0 0
0 0
0
0
0 0 0
0 0 1
OCR r
B
B
DESCRIPTION OF OPERATION
0
Load Index register I With the content of memory register M.
Load Index register r With data B ... B.
load memory register M With data B ..• B.
Increment the content of Index register r Ir ; AL
Decrement the content of Index register r (r
i AL
Accumulator Group Instructions
The rpsilit of the ALU instructions affect all of the flag flip.flops. The rotate instructions affect only the carry flip·flop.
,
,
ADDr
lSI
AOOM
AOI
181
181
0
ADe r
lSI
B B
1 0
AOC M
ACI
181
181
0
0 0
SUB,
lSI
SUB M
181
181
SUI
SBB,
lSI
SBB M
181
181
SBI
0
0
0
0 0 0
0 0 0
0 0 0
,,,
,
5 S S
0 0
Add the content of Index register r. memory register M, or data
B .. , B to the accum'ulator, An overflow (carrv) sets the carry
fllp·flop,
B B B
B B B
,
0 0
0 0
0 0
,
, ,,
, ,
5 5 5
Add the content of Ind'x register r, memory register M, or data
1
B . , . 8 from the accumulator With carry. An overflow lcarryl
,
B B
B B
6
B B B
0
0
0 O·
0
0
0
1 0
S S S
1
B B
B B B
B B B
,
0
0
0 0
0
0
0
S S S
1
0 0
B B
B B B
B B B
1
1
0 0
,
0
1 0
,, ,
0 0
,,
,, ,,,
, ,
sets the carry flip.flop.
Subtract the content of Index register r, memory register M, or
data 8 ... B from the accumulator. An underflOW (borrow)
sets the carry fllp.flop.
Subtract ,the contel')l·of Index register r, memory regls •• r M, or data
data B . , . B from I,he'accumulator With borrow. An underflOW
(borrow) sets the carry flip.flop,
11-7
8008/8008~1
MINIMUM
MNEMONIC
STATES
INSTRUCTION COOE
0706
Os 0 4 03
~D,~
1
1
0
8
1
1
0
8
1
1
0
8
1
1
0
B
1
1
1
8
1
1
1
8
1
1
1
B
1
1
1
8
0
8
1
1
1
8
0
0
0
8
1
1
1
8
S
1
1
8
S
1
1
B
S
1
1
B
S
1
1
8
S
1
0
8
S
1
,0
8
S
1
0
B
1
0
8
S
1
0
B
S
1
0
8
S
1
0
8
S
1
0
8
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
DESCRIPTION OF OPERATION
REQUIRED
ANAr
ANAM
ANI
IS)
(8)
(8)
XRAr
IS)
XRAM
(8)
(8)
XRI
ORA,
IS)
ORAM
ORI
(8)
(8)
CMP,
CMPM
CPI
(8)
(8)
RLC
RRC
RAL
RAR
lSI
IS)
IS)
IS)
IS)
0
0
0
0
0
0
0
8
0
0
0
8
0
0
0
B
0
0
0
B
0
0
0
0
0
0
0
8
0
0
0
8
1
1
1
B
1
1
1
8
0 0
0 0
0 1
0 1
0
a
5
Compute Ihl' IOgl(;dl AND of the content of index register r,
rTlf!mory register M, or datd B . , . B with the accumulator.
Compute the' EXCLUSIVE OR of the content of index register
r. ITIt!mory register M, or data B . .. B with the accumulator.
Compute the INCLUSIVE OR of the content of Index register
r. memory reglSier m, or data B ... B with the accumulator.
Compare the content of index register r, memory register M,
or data B ... 8 with the accumulator. The content of the
accumulator
Rotate
RotBte
Rotate
Rotate
the
the
the
the
IS
unchanged.
content
content
content
content
of
of
of
of
the
the
the
the
accumulator
accumulator
accumulator
accumulator
left.
right.
left through the carry.
right through the carry.
Program Counter and Steck Control Instructions
141JMP
IS) JNC, JNZ,
1111
0 1
82 82
X X
X X X
82 B2 82
B3 8 3 B3
1 0 0
UnconditionallY jump to memory address 93 .. , 9392 ... 82.
82 B2 B
83 B3 83
19 or 111
0 1
82 B2
X X
190r 111
0
0
82
83
1
82
83
X
0
82
83
0
C4 C3
0
1
1
Aeturn (down one level," the stack I .f the condition flip-flop is
false. Otherwise. execute the next Instruction in sequence.
0
82
83
0
0
8
8
0
82
83
0
82
B3
0
82
83
0
82
B3
1
Jump to memory address 83 ... 8382 ... 82 if the condition
flip-flop is false. Otherwise, execute the next in-!' \Jction in sequence.
lSI
0
0
C4 C3
82 82
8 3 83
C4 C3
iI2 82
B3 83
X X
82 82 82
83 83 83
0 C4 C3
82 82 82
83 83 83
1 C4 C 3
82 B2 82
83 8 3 8 3
X X X
ANC. ANZ,
AP, APQ
130,5)
0
0
0
AC,AZ
AM. APE
13 or 5)
0 0
1 C4 C3
0
1
1
Aeturn (down one level '" the stack) If the condition flip·flop is
true. OtherWise. execute. the next instruction In sequence.
0
0
,A A A
1 0
1
Call the subroutine at memory address AAAOOO lup one level in the stackl.
JP, JPO
JC. JZ
JM. JPE
1
iI2i12
X X
(11)
0
CNC, CNZ.
cp, CPO
19 or 111
0
ce,
190r 11)
CALL
1
iI2 82
X X
1
iI2 82
X X
CZ,
CM, CPE
0
1
iI2 82
X X
RET
RST
IS)
iI2 iI2
83
1
82
83
0
B3
1
82
83
1
iI2 82
83 83
0 1
82 82
83 83
1 1
Jump to memory address 83 ... 8382 •.. 82 If t~.e cof\dition
flip.flop is true. Otherwise, execute the next instructi<...n in sequence.
Unconditionally call the subroutine at memory address 83 ...
8382 ... 82. Save the current address lup one level in the stack).
Call the subroutine at memory address 83 ... 8382 ... 82 if the
condition flip-flop is false. and save the current address (up one
level In the stack.) OtherWise. ·execute the next instruction in sequence.
Call the subroutine at memory address 83 ... 8382 ... 82 If the
condition flip-flop is true. and save the current address (up one
level in the stack). Otherwise, execute tl:le next instrjJction in sequence.
Unconditionally return (down one level in the stack).
Input/Output Instructions
IN
(8)
0
1
0
M
,M M 1
OUT
(6)
0
1
R R M
M M 1
o
0
o
o
0
0
0
0
X
Read the content of the selected input port I MMM) into the
accumulator.
Write the content of the acciJmulator into the selected output
port (RRMMM, RR 1001.
Enter the STOPPED state and remain there until Interrupted.
1
NOTES:
(11
SSS :' Source lndex Register
} These registers. r;. are deSignated A(accumulator-Q(X».
DDD = Destination Index RegISter
B1001), C(010), 010111, Ell001. Hll0l1, LillO)'
(21
Memory registers are addre$sed by ,the contents of registers H & L.
.
(3)
Additional bvtes of instruction are designated by 88888888..
(4)
X = "Don't Car.".
. '
(51
f.lag flip~flops are defined by 04C3 carry (OO·overflow or underflowl, zero IOl·result IS zerol, sign (1 O·MSB of result
parity ("-parity is evenl.
11-8
IS
"1"1.
8008/8008·1
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias
Storage Temperature
'COMMENT
O°C to +70°C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
-the device. This is a stress rating only and func-
-55°C to +150°C
Input Voltages and Supply
Voltage With Respect
teVee
+0.5 to -20V
Power Dissipation
1.0 W @ 25°C
tional operation of the device at these or any other
condition above those indicated in the operational
sections of this specification is not implied.
D.C. AND OPERATING CHARACTERISTICS
TA = O°C to 70°C, Vee = +5V ±.5%, Voo = -9V ±.5% unless otherwise sperified. Logic "'" is defined
as the more positive level (V 1H , VOH ). Logic "0" is defined as the more negative level (V 1L , VOL ).
SYMBOL
PARAMETER
MIN.
LIMITS
TYP.
MAX.
30
60
mA
TA
10
"A
V,N = OV
UNIT
100
AVERAGE SUPPLY CURRENTOUTPUTS LOADED'
ILl
INPUT LEAKAGE CURRENT
V,L
INPUT LOW VOLTAGE
(INCLUDING CLOCKS)
Voo
Vcc -4.2
V
V,H
INPUT HIGH VOLTAGE
(INCLUDING CLOCKS)
Vec-1.5
Vee +0.3
V
VOL
OUTPUT LOW VOLTAGE
VOH
OUTPUT HIGH VOLTAGE
0.4
Vee -1.5
TEST
CONDITIONS
= 25°C
·Measurements are made while
V
IOL = 0.44mA
CL = 200 pF
V
IOH
the 800B is executing a typical
sequence of instructions. The
test load is selected such that
at VOL = O.4V, 10L= 0,44mA
on each output,
= 0.2mA
A.C. CHARACTERISTICS
TA = DoC to 70°C; VCC = +5V ±5%, V DO = -9V ±5%, All measurements are referenced to 1.5V levels.
8008
SYMBOL
8008·'
LIMITS
PARAMETER
MIN.
MAX.
LIMITS
MIN.
MAX.
UNIT
ley
CLOCK PERIOD
I R,I F
CLOCK RISE AND FALL TIMES
11
PULSE WIDTH OF ,
.70
.35
IJ,s
I2
PULSE WIDTH OF 2
.55
.35
!is
CLOCK DELAY FROM FALLING
EDGE OF ¢, TO FALLING EDGE
OF ¢2
.90
t02
CLOCK DELAY FROM ¢2 TO ¢,
.40
.20
10'
2
3
1.25
50
1.1
3
IJ,s
50
ns
1.1
.35
TEST CONDITIONS
IR,IF = 50ns
IJ,S
IJ,S
103
CLOCK DELAY FROM ¢, TO ¢2
100
DATA OUT DELAY
tOH
HOLD TIME FOR DATA BUS OUT
.10
IIH
HOLD TIME FOR DATA IN
111
ISO
SYNC OUT DELAY
.70
.70
IJ,s
C L = 100pF
IS,
STATE OUT DELAY (ALL STATES
EXCEPT T1 AND T11) 121
1.1
1.1
IJ,S
C L = 1QOpF
t S2
STATE OUT DELAY (STATES
T1 AND T11)
1,0
1.0
IJ,S
C L =100pF
tRw
PULSE WIDTH OF READY DURING
.20
1,0
IJ,S
1.0
.10
IJ,S
111
{JS
,35
.35
IJ,S
.20
.20
IJ,S
¢22 TO ENTER T3 STATE
IRO
READY DELAY TO ENTER WAIT
STATE
11ltlHMIN~tso
121 If the INTERRUPT is not used, all states have the same outnut delay, t S1 '
11·9
C L =100pF
IJ,S
8008/8008·'1
TIMING DIAGRAM'
________ tCy---.....l
---J
Q
.....
..... '0'
10, ... 1:\,1
f.-
~
--
I
SYNC
DATA
BUS
LINES
-'0'
~
'02
.R
I-
'02
R
~
"2'
"22
I-
,......,'2'
011
"12
d21
.°22
;""50-1
1
\
-'0' ........1-'00 ..1
--- --
I
\
I-""~I.
...
DATA IN
--:1. f-:.-O
------ ----------- -_. ____ .J ----- ... I'-------4..
----------- ...I---- ... - I
J.
_1,.----ADDRESS OUT
I
-----too ______1
_III
,.-~~.
,
---.... 'OHI---
1'"':'-
-
"'- _ _ _ DATA
___
_ ... _
DUT
i+--'oo~
So
5,
STATE
LINES
Notes:
~
r-
H'RW I-
- ----...,
I)
{,
"""
tCHI........
-+-- t S2 -----+
1---'0' ..........
52
-~---.
111
..
T,
\
I':::.
tRD
1
...
Tj
I
T,
~
T,
1. READY line must be at "0" prior to <1>22 of T2 to guarantee entry into the WAIT state.
2. INTERRUPT line must not change levels within 200ns (max.) of falling edge of
Parameter
Clock Capacitance
CIN
I nput Capacitance
CO UT
Output Capacitance
Typ.
Max.
Unit
17
25
pf
Test Condition
fc = 1 MHz
6
10
pf
Unmeasured Pins
10
20
pf
Retu rned to VSS
go
"u
1.0
~
~
iil
0.5
NOTES:
1. The RESET signal must be active for a minimum of 3 clock cycles.
2. When DBIN is high and VIN
> VIH an internal active pull
up will
0
+25
+75
+50
AMBIENT TEMPERATURE fOC)
Figure 2. Typical Supply Current vs.
Temperature, Normalized[J]
be switched onto the Data Bus.
3. ~I supply I ~ T A = -0.45%f c.
,·,-r---~
°0
Vee
V,N
FIgure 3. Data Bus Characteristic
During DBIN
11-13
8080Al8080A·1/8080A·2
A.C. CHARACTERISTICS (8080A)
TA = O°C to 70°C, VDD = +12V ± 5%, VCC = +5V ± 5%, VBB = -5V ± 5%, Vss = OV, Unless Otherwise Noted
Symbol
Parameter
·2
·2
Max.
·1
Min.
·1
Min.
Max.
Min.
Max.
Unit
0.48
2.0
0.32
2.0
0.38
2.0
~sec
50
0
25
0
50
ICy[3J
Clock Period
Ir,lf
Clock Rise and Fall Time
0
1"'1
"'I Pulse Widlh
60
50
60
220
145
175
nsec
0
0
0
nsec
nsec
nsec
nsec
t"'2
"'2 Pulse Width
tOI
Delay "'I to "'2
t02
Delay "'2 to "'I
70
60
70
t03
Delay "'I to "'2 Leading Edges
80
60
70
IOA[2J
Address Oulput Oelay From "'2
200
150
175
nsec
tDO[2J
Data OUlput Delay From "'2
220
180
200
nsec
tocl 2J
Signal Output Oelay From "'2 or "'2 (SYNC, WR, WAIT, HLOA)
tOF[2J
OBIN Delay From "'2
:.
120
tOI[IJ
~Iay
tOSI
Data Selup Time Ouring "'I and OBIN
for Inpul Bus to Enter Inpul Mode
WAVEFORMS
130
25
10F
25
10F
10
30
120
nsec
140
nsec
IOF
20
}
CL=loo pF
}
CL=50 pF
nsec
nsec
(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = B.OV
"0" = 1.0V; INPUTS "1" = 3.3V, "0" = O.BV; OUTPUTS "1" "" 2.0V, "0" = O.BV.)
_~tcv-h
-tol-
rt:
~
-r
:1
-I
.... t 03 ...
t02
\
r--
j~
-
-- t ---
-too-I
_.
-~
-
.A _____
1
SYNC
-- tD;I~
OBIN
-
1---
tOI
·t:-~
__
-itoe
/\
....-----..
r----.
f-i
--tOA ---"
-
--
~-
---- -- --tAW
toHI_
i---too-
-tDS1~ ~
~
~~ ....,,g~A I~
- ---
I--tow
~
DATA OUT
-
1----
- t082 -
1--I
-1
1
I-to~
READY
nsec
110
140
25
Test Condition
... toF--1
----------------------
'DC
,X@
- tR:h-- t
WAIT
H-
- I-
toc---"
HOLD
'H- I -
I--
-d!f~toe ~I
t RS
-
l
-
'H __ 1·l@ I
.-:..r;:; ~
HLDA
--XOf
INT
tl~f:-:
tH ----+ ...
INTE
11·14
8080A/8080A·1 18080A·2
A.C. CHARACTERISTICS (8080A)
oDe to loDe, VDD ~ +12V ± 5%, Vcc ~ +5V ± 5%,
TA ~
Parameter
Min.
Data Setup Time to "'2 During DBIN
150
[1]
Symbol
tDS2
V BB ~ -5V ± 5%, Vss ~ OV, Unless Otherwise Noted
Max.
·1
Min.
·1
·2
·2
Max.
Min.
Max.
130
120
tDH[l]
Data Holt time From "'2 During DBIN
tIE[2]
INTE Output Delay From "'2
tRS
READY Setup Time During "'2
120
90
tHS
HOLD Setup Time to "'2
140
120
[1]
200
[1]
nsec
120
120
nsec
100
100
nsec
tiS
INT Setup Time During "'2
tH
Hold Time From "'2 (READY, INT, HOLD)
tFO
Delay to Float During Hold (Address and Data Bus)
tAW[2]
Address Stable Prior to WR
[5]
[5]
[5]
nsec
tDW[2]
Output Data Stable Prior to WR
[6]
[6]
[6]
nsec
tWD[2]
Output Data Stable From WR
[7]
[7]
[7]
nsec
tWA[2]
Address Stable From WR
[7]
[7]
[7]
nsec
tHF[2]
HLDA to Float Delay
[8]
[8]
[8]
nsec
tWF[2]
WR to Float Delay
[9]
[9]
[9]
nsec
tAH[2]
Address Hold Time After DBIN During HLDA
-20
-20
-20
nsec
0
120
0
120
CL~50
nsec
90
0
Test Condition
nsec
200
200
Unit
nsec
pF
nsec
120
nsec
i-
CL ~ 100 pF: Address, Data
CL ~ 50 pF: WR,HLDA,DBIN
1-
NOTES: (Parenthesis gives ·1,·2 specifications, respectively)
1. Data input should be enabled with DBIN status. No bus conflict can then occur and data hold time IS assured.
tOH '" 50 ns or tOF, whichever IS less.
2.
Load CircuIt.
+5V
r
1
1--1---':1
,
:
D81N
!
!
,
tWA
:I
,
two
--~----iI
---.
-,--
3. tCY ~ tD3 + tr+2 + t+2 + tf+2 + tD2 + tr+1 ,,480 ns (- 1:320 ns, - 2:380 ns).
TYPICAL A OUTPUT DELAY VS. A CAPACITANCE
i
-I
~
/
I
t DC
__ tAH
~
-- ~.tWF-
r-
I
WAIT
HOLD
1
-t-f-,---t-I
I
:EAOY
~
-- +----j--
tFDt
+- __ j- 'I
l-
SYNC
8080A
OUTPUT
I
~
r------.
~
I
+100
.1 CAPAC IT ANCE (pf)
(CACTUAl - C SPEC )
tHF
-
4. The following are relevant when interfacing the 80BOA to devices having VIH
c) If CL
~
HlDA
toc
~
--Y'
=I=-
3.3V:
SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL
5, tAW ~ 2 tCY - tD3 - tr+2 -140 ns (- 1:110 ns, - 2:130 ns).
6. tow ~ tCY - tD3 - tr+2 - 170 ns (-1:150 ns, - 2:170 ns).
7. [f not HLOA, two = tWA
8. tHF
.NT
=:
a) Maximum output rise time from .8V to 3.3V '" 100ns@ CL"" SPEC.
b) Output delay when measured to 3.0V '" SPEC +60ns @ CL == SPEC.
~
= t03
< CSPEC.
+ tr
()
C",
Clock Capacitance
17
25
pf
fc = 1 MHz
CIN
I nput Capacitance
6
10
pf
Unmeasured Pins
COUT
Output Capacitance
10
20
pf
Returned to Vss
~
il:
0.5
iil
NOTES:
AMBIENT TEMPERATURE f'C)
1. The RESET signal must be active for a minimum of 3 clock cycles.
2. When OBIN is high and VIN > VIH an internal active pull up will
Figure 1. Typical Supply Current vs.
Temperature, Normalizedl 31
be switched onto the Data Bus.
3. 61 supply I 6 T A = -0.45%( c.
Figure 2. Data Bus Characteristic During
DBIN
11·21
M8080A
A.C. CHARACTERISTICS
TA = -55°C to +125°C, VDD = +12V ±10%, VCC = +5V ±10%, Vss = -5V ±10%, Vss = OV, Unless Otherwise NotEkl;
Symbol
tCy[3]
Parameter
Clock Period
Min.
Max.
Unit
0.48
2.0
11 sec
50
nsec
t,. tf
Clock Rise and Fall Time
0
tl
1>1 Pulse Width
60
t2
<1'2 Pulse Width
220
nsec
tDl
Delay 1>1 to 1>2
0
nsec
tD2
Delay 1>2 to 1>1
80
nsec
tD3
tDA [2]
Delay 1>1 to 1>2 Leading Edges
80
n sec
nsec
nsec
Address Output Delay From 1>2
200
tDD [2]
Data Output Delay From 1>2
220
nsec
tDC [2]
Signal Output Delay From 1>1. or 1>2 (SYNC. WR.WAIT. HLDAI
140
nsec
tDF [2]
DBIN Delay From 1>2
'50
nsec
tDI[ll
Delay for Input Bus to Enter Input Mode
tDF
nsec
tDSl
Data Setup Time During 1>1 and DBIN
WAVEFORMS[14]
.,
A15"AO
Test Condition
25
Icc 5~f
0
nsec
30
(Note: Timing measurements are made at the following reference voltages: CLOCK "'" = 7.0V.
"0" = 1.0V; INPUTS "'" = 3.0V, "0" = 0.8V; OUTPUTS "'" = 2.0V. "0" = 0.8V.)
----------~--~
---------+--1/'-
0,,0 0 ---------+-~';t.----SYNC _ _ _ _ _ _ _ _ _+.JI
- - t oe
---
I
READY
'
~:.:...__+_Jtr:____tD_c--t~f'-'- - 4 - i
WAIT _--_-_--_-_-_-_-_-_-_-_ _ _ _ _ _ _ _ _ _ _ _
HOLD
1-
-~-
II
HLDA
INT
'II '
- - - - - - - - - - - - - - - : : ~H~L-----+t--4i
I
t!'3
-----------------------------------------------------------------~I-=
tH_
INTE
11·22
-+-
M8080A
,, tI;,.-,
A.C. CHARACTERISTICS (Continued)
.
.
""'~.!,...
.
"
TA -- 55°Cto+125°C IJ,DO-+12V+10%
IJ,CC= +5V+10%
IJ,BB =- 5V+10%
V.55= OV Uness
I Oth erwi'se N0 t
Symbol
Min.
Parameter
tD52
Data Setup Time to f/J2 During DBIN
tDH[11
Data Hold Time From r/J2 During DBIN
Max.
Unit
130
nsec
[11
nsec
200
~;.~
nsec
t1E[21
INTE Output Delay From r/J2
tRS
READY Setup Time During f/J2
120
nsec
tH5
HOLD Setup Time to r/J2
140
nsec
tiS
INT Setup Time During r/J2
120
nsec
tH
Hold Time From r/J2 (READY, INT, HOLD)
tFD
Delay to Float During Hold (Address and Oata Bus)
tAW [21
Address Stable Prior to INR
[51
nsec
tDW[21
Output Data Stable Prior to WR
[61
nsec
tWD[21
Output Data Stable From WR
[71
nsec
tWA [21
Address Stable From WR
[71
nsec
0
Test Condition}'-.,."
CL = 50pf
nsec
130
nsec
tHF[21
HLDA to Float Delay
[8]
nsec
tWF[2]
WR to Float Delay
[91
nsec
tAH [21
Address Hold Time After DBIN During HLDA
-20
nsec
1-
_ C L =50pf
-
NOTES:
1. Data Input should be enabled with DBIN status. No bus conflict can then occur and data hold time is assured.
tOH '" 50 ns or tDF, whichever
IS
less.
2. Load Circuit.
+5V
2.1K
M8080A
OUTPUT
3. tey
= t03 + tr¢2 + t- +10
SYNC
~
"ir
f-
CBIN
f-
"..,
0
WR
-'0
-20
/
-'00
~EADV
/'
/
/
"-SPEC
+50
-50
..l
+100
CAPAC IT ANCE (pf)
(CACTUAL - C SPEC )
WAIT
HOLO
4. The following are relevant when interfacing the M8080A to devices having VIH
a) Maximum output rise time from .8V to 3.3V = 100ns@Cl = SPEC.
I-
__ toe_
J,,---+--
HLDA
INT
INTE
I-
= 3.3V:
b) Output delay when measured to 3.0V "" SPEC +60ns@ CL = SPEC.
c) If CL SPEC, add .6ns/pF if Cl> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC.
tAW::: 2 tCY -t03 -t np2 -140nsec.
.
tow = tCY -t03 -trrt>2 -170nsec.
If not HLOA. two =tWA = t03 + trrt>2 +10ns. If HLOA. two = tWA = tWF·
tHF = t03 + t nP2 -50ns.
tWF = t03 + tr4>2 -10ns
Data in must be stable for this period during OBIN ·T3. Both tOS1 and tOS2 must be satisfied.
Ready signal must be stable for this period dUring T2 or TW. (Must be externally synchronized.)
Hold signal must be stable for this period during T 2 or TW when entering hold mode. and during T 3. T 4. TS
and TWH when in hold mode. (External synchronization IS not required,)
13. Interrupt signal must be stable during this period of the last clock cycle of any instruction In order to be
recognized on the following instruction. (External synchronization IS not reQulted.l
14. This timing diagram shows timing relationships only; it does not represent any specifiC machine cycle.
'*
5.
6.
7.
8.
9.
10.
11.
12.
11·23
8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
• Single Chip Clock Generator/Driver for
8080A CPU
• Oscillator Output for External System
Timing
• Power-Up Reset for CPU
• Ready Synchronizing Flip-Flop
• Crystal Controlled for Stable System
Operation
• Advanced Status Strobe
• Reduces System Package Count
The IntelCl!> 8224 Is a single chip clock generator/driver for the 8080A
designer to meet a variety of system speed requirements.
cpu. It is controlled by a crystal, selected by the
Also Included are circuits to provide power·up reset, advance status strobe, and synchronization of ready.
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing for 8080A.
BLOCK DIAGRAM
PIN CONFIGURATION
RESET
Vee
RESIN
XTAL 1
RDYIN
XTAL2
READY
SYNC
XTALl
XTAl2
OSC
TANK
.,
.,
TANK
@>
!TI>
1!9
.,(TTlllD
osc
~,(TTll
~,
STSTB
~,
GND
ij9
§>
I§>
[D
SYNC
[D
RESIN
STSTB
IZ>
RESET
IT>
Voo
II>
RDVIN
PIN NAMES
RESiN
RESET
RESET INPUT
RESET OUTPUT
RDYIN
READY INPUT
READY
SYNC
SYNC INPUT
STSTB
READY OUTPUT
STATUSSTB
(ACTIVE lOWI
~ 18080
CLOCKS
XTALl
XTAl2
TANK
OSC
., (TTLI
Vee
Vuo
GND
~,
11·24
!
CONNECTIONS
FOR CRYSTAL
USEO WITH OVERTONE XTAL
OSCillATOR OUTPUT
.2 ClK (TTL lEVELI
+5V
+12V
OV
READY~
8224
ABSOLUTE MAXIMUM RATINGS·
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias ............... O°C to 70°C
Storage Temperature .............. _65°C to 150°C
Supply Voltage, Vee ................ -0.5V to +7V
Supply Voltage, Voo .............. -0.5V to +13.5V
Input Voltage ..................... -1.5V to +7V
Output Cu rrent. . ....................... 1OOmA
D.C. CHARACTERISTICS
TA = O°C to 70°C; Vee = +5.0V ±5%; Voo = +12V ±5%.
Symbol
Parameter
Min.
Limits
Typ.
Max.
Units
IF
Input Current Loading
-.25
mA
VF = .45V
IA
Input Leakage Current
10
/lA
VA = 5.25V
Ve
Input Forward Clamp Voltage
1.0
V
Ie = -5mA
VIL
Input "Low" Voltage
.8
V
Vee = 5.0V
V1H
Input "High" Voltage
2.6
2.0
V
Reset Input
All Other Inputs
VIWVIL
RESIN Input Hysteresis
.25
VOL
Output "Low" Voltage
VOH
Test Conditions
V
Vee = 5.0V
.45
V
(rf>1,rf>2), Ready, Reset, STSTB
.45
V
IOL =2.5mA
All Other Outputs
IOL = 15mA
V
V
V
IOH = -100/lA
IOH = -100/lA
IOH = -lmA
Output "High" Voltage
rf>1 , rf>2
READY, RESET
All Other Outputs
9.4
3.6
2.4
-60
mA
Power Supply Current
115
mA
Power Supply Current
12
mA
Ise l1 ]
Output Short Circuit Current
(All Low Voltage Outputs Only)
Icc
100
-10
Note: 1. Caution, 2
- - - - - - - - - - - - --
VOLTAGE MEASUREMENT POI NTS: DO-D7 (when outputs) Logic "0" ~ 0.8V, Logic "'" ~ 3.0V. All other signals measured
at '.5V.
'ADVANCED IOW/MEMW FOR 8238 ONLY.
A.C. CHARACTERISTICS
TA ~
o°c to 70°C; Vee = 5V ±5%.
Limits
Symbol
I.:
..
Parameter
Min.
Max.
Units
22
ns
Setup Time, Status Inputs Do-D7
8
ns
Hold Time, Status Inputs Do-D7
5
tpw
Width of Status Strobe
tss
tSH
tDe
Delay from STSTB to any Control Signal
tRR
Delay from DBIN to Control Outputs
tRE
Delay from DBIN to Enable/Disable 8080 Bus
tRD
Delay from System Bus to 8080 Bus during Read
30
20
tWR
Delay from WR to Control Outputs
tWE
Delay to Enable System Bus DBo-DB7 after STSTB
tWD
Delay from 8080 Bus Do-D7 to System Bus
DBa-DB7 during Write
5
5
ns
ns
CL = 100pF
30
ns
CL = 100pF
45
ns
C L = 25pF
ns
CL = 25pF
45
ns
CL = 100pF
30
ns
CL = 100pF
ns
CL = 100pF
CL=100pF
60
40
tE
Delay from System Bus Enable to System Bus DBa-DB7
30
ns
tHD
H LOA to Read Status Outputs
25
ns
tDs
Setup Time, System Bus Inputs to HLDA
10
ns
tDH
Hold Time, System Bus Inputs to HLDA
20
ns
11·36
Condition
CL = 100pF
822818238
CAPACITANCE
This parameter is periodically sampled and not 100% tested.
Limits
Typ,l11
Max.
Unit
CIN
I nput Capacitance
8
12
pF
CoUT
Output Capacitance
Control Signals
7
15
pF
I/O
I/O Capacitance
(D or DB)
8
Min.
Parameter
Symbol
+12V
1Kn t10%
pF
15
Test Conditions: NS: VBIAS =2.5V, Vcc =5.0V, TA =25°C, f
8228
=1MHz.
Note 2: For DO·D7: R1 = 4Kn, R2 = ~n,
CL = 25pF. For all other outputs:
R1 = 500n, R2= 1Kn, CL = 100pF.
23
INTA
b----------l
Figure 1. INTA Test Circuit (for RST
2
As
GND.
20
+5V
A,
11
-5V
As
28
+12V_
A,
A_
As
8080A
CPU
13
SYSTEMDMAREO.- HOLD
25
As
26
A,
27
A,
29
As
30
A_
31
As
32
A.
A.,
As
A.
A.
33
A7
34
1
A,o
40
14
SYSTEM INT. REO.
INT
16
INT. ENABLE
A"
37
A12
A12
38
A"
INTE
ADDRESS BUS
As
As
35
A,o
A"
n
A,_
A"
39
A,_
36
A,s 18
A,s
WR
DBIN
[jDf~rL
-
14
HDlA
15
13
11
22
~
.,(TTL) ~
10
15
TANK
OSC
RDVIN
RESIN
+12V
+5V
GND
3
2
-~
--
8224
CLOCK
GENERATOR
DRIVER
~
4
~
23
1
12
.,
WAIT
0,
REArlY
0,
5
19
8
r
15
9
17
8
12
JJ
DB
13
1.
11
8228/8238
7
10
3
6
4
19
5
21
20
•
8
7
BI·DIRECTIONAL
BUS DRIVER
9
5
18
Os
D.
SYNC
10
0,
D_
RESET
21
21
DO
6,
17
07
STATUS STROBE
28
+5V14
GND1
.
22
BUSEN
Figure 2. CPU Standard Interface
11-37
-----
23
24
..
...
...
DBO
DB,
os,
DB,
DB_
DATA BUS
Oils
DBa
D~
jj;ifj(}
MEMR
SYSTEM
CONTROL
26
MEM W
25
27
I/OR
I/OW
CONTROL BUS
inter
,~ ,:~::' ,
M8228
",¥-'
SYSTEM CONTROLLER AND BUS DRIVER
FOR M8080A CPU
• User Selected Single Level Interrupt
Vector (RST 7)
• Single Chip System Control for
MCS·80™ Systems
• 28·Pin Dualln·Line Package
• Built·ln Bidirectional Bus Driver for
Data Bus Isolation
• Reduces System Package Count
• Full Military Temperature Range
- 55°C to + 125°C
• Allows the Use of Multiple Byte
Instructions (e.g. CALL) for Interrupt
Acknowledge
• ± 10% Power Supply Tolerance
The Intel@ M8228 is a single chip system controller and bus driver for MCS-80. It generates all signals required to
directly interface MCS-80 family RAM, ROM, and 1/0 components.
A bidirectional bus driver is included to provide high system TTL fan-out. It also provides isolation of the 8080 data bus
from memory and 1/0. This allows for the optimization of control signals, enabling the systems designer to use slower
memory and 1/0. The isolation of the bus driver also provides for enhanced system noise immunity.
A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small system requirements. The M8228 also generates the correct control signals to allow the use of multiple byte instructions (e.g.,
CALL) in response to an interrupt acknowledge by the M8080A. This feature permits large, interrupt driven systems to
have an unlimited number of interrupt levels.
The M8228 is designed to support a wide variety of system bus structures and also reduce system package count for
cost effective, reliable, design of the MCS-80 systems.
PIN CONFIGURATION
STSTB
Vee
HLDA
"OW
WR
DBIN
DB4
DO
DB7
I
--
"
BLOCK DIAGRAM
07
DB3
MEMw
0,_
OO_
CPU
{
DATA
~DB1
-
-
°40,0,0,-
BUS
IIOR
Ol
DB
- 0 82
°2°3-
DB3
SYSTEM DATA BUS
--- DB4
--- DBs
--- DBa
- - - DB7
MEMR
INTA
BUSEN
06
DB6
05
085
Si'STB - - - - - - - - - - - '
01
__
-_
--_
-_
-_
--_
1
WR _
___
__-_
DBIN
~
OBI
HLDA
--------------L_J
0'
PIN NAMES
INTA
INTERRUPT ACKNOWLEDGE
07-00
OAT A BUS (BOBO SIDE)
DB7-DBO
DATA BUS (SYSTEM SIDE)
HLDA
HLDA (FROM 8080)
WR (FROM SOBO)
"OW
MEMR
110 READ
110 WRITE
WIi
BUSEN
BUS ENABLE INPUT
MEMORY READ
STSTB
STATUS STROBE (FROM 8224)
MEMW
MEMORY WRITE
OBIN (FROM B080)
Vee
GND
;sV
DBIN
IIOR
11-38
o VOLTS
M8228
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias . . . . . . . . . . . _55°C to 125°C
Storage Temperature . . . . . . . . . . . . . -65°C to 150°C
Supply Voltage, Vee . . . . . . . . . . . . "
-0.5V to +7V
Input Voltage . . . . . . . . . . . . . . . . . "
-1.0V to +7V
Output Current. . . . . . . . . . . . . . . . . . . . ..
D.C. CHARACTERISTICS
100mA
TA = -55°C to 125°C; Vee = 5V ±10%.
Limits
Symbol
Parameter
Min.
Max.
Unit
Vc
Input Clamp Voltage, All Inputs
-1.2
V
IF
I nput Load Current,
STSTB
500
pA
D 2 ,D6
750
pA
Do, D1, D4, D5, D7
250
pA
All Other Inputs
250
pA
Test Conditions
Ie = -5mA
VF=O.4V
Input Leakage Current
IR
DBo - D7
All Other Inputs
pA
pA
2.0
V
VR = 5.5V
VTH
Input Threshold Voltage, All Inputs
lee
Power Supply Current
210
mA
VOL
Output Low Voltage,
Do - D7
.5
V
10L = 2mA
All Other Outputs
.5
V
10L = 10mA
VO H
0.8
20
100
Vee = 5V
Output High Voltage,
Do - D7
3.3
V
10H = -10pA
All Other Outputs
2.4
V
10H =-lmA
los
Short Circuit Current, All Outputs
15
10 (Off)
Off State Output Current,
All Controls Outputs
liNT
Note1:
INTA Current
Typical values are for T A = 25 0 C and nominal supply voltages.
11·39
90
mA
Vee = 5V
100
-100
pA
pA
Va = 5.5V
Va - .45V
5
mA
(See Figure 1)
M8228
CAPACITANCE This parameter is periodically sampled and not 100% tested.
Limits
Symbol
Parameter
Min.
+12V
Typ,£lJ
Max.
Unit
CIN
I nput Capacitance
8
12
pF
COUT
Output Capacitance
Control Signals
7
15
pF
1/0
1/0 Capacitance
(0 or DB)
8
15
pF
1KD:±10%
M8228
TEST CONDITIONS: VSIAS = 2.5V, Vcc=5.0V, TA = 25°C, f = 1 MHz.
23
Note 2: For DO-D7: R1 = 4Kn, R2 = ~n,
CL = 25pF. For all other outputs:
R1 =500n,R2= 1Kn, CL = 100pF.
INTA
P--------'
Figure 1. INTA Test Circuit (for RST 7)
A.C. CHARACTERISTICS
TA = -55°C to 125°C; VCC = 5V ±10%.
Limits
Symbol
I
Parameter
Min.
Max.
Units
tpw
Width of Status Strobe
25
ns
tss
Setup Time, Status Inputs Do-D7
8
ns
tSH
Hold Time, Status Inputs 00-07
5
tDC
Delay from STSTB to any Control Signal
tRR
tRE
Condition
ns
75
ns
CL = 100pF
Delay from DBIN to Control Outputs
30
ns
CL = 100pF
Delay from DBIN to EnablelDisable 8080 Bus
45
ns
CL = 25pF
tRD
Delay from System Bus to 8080 Bus during Read
45
ns
CL = 25pF
tWR
Delay from WR to Control Outputs
60
ns
CL = 100pF
tWE
Delay to Enable System Bus DBo-DB7 after STSTB
30
ns
CL = 100pF
tWD
Delay from 8080 Bus 00-07 to System Bus
DBO-DB7 during Write
ns
CL = 100pF
20
5
5
40
tE
Delay from System Bus Enable to System Bus DBa-DB7
30
ns
CL - 100pF
tHO
H LOA to Read Status Outputs
25
ns
CL = l00pF
tos
Setup Time, System Bus Inputs to HLDA
10
ns
tOH
Hold Time, System Bus Inputs to HLDA
20
ns
11-40
M8228
_ '8
WRb--------------,
DBIN 1-".!-7~______---,
HDLAI2~'~--~~~~~~
M8080A
CPU
J
INTA R
MEM
MEM W
(FROM 8224) STATUS STROBE
CONTROL BUS
I/O R
I/ow
Figure 2. M8080A CPU Interface
TYPE OF MACHINE CYCLE
I
STATUS WORD
WO
1
1
STACK
a
a
o
INP
a
a
a
a
a
a
MEMR
1
1
HLTA
OUT
1
D6
a
a
a
0
0
a
a
1
a
1
100
a
a
a
a
a
a
a
a
a
1
1
a
a
a
1
a
a
1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
I
-IN-T-';'--
' - - - - - (NONE)
~--------
INTA
I/OW
I/O R
MEM W -
MEM R
---------------MEMW
MEM R
'-------------------MEMR
--
Figure 3. Status Word Chart
11·41
CONTROL
SIGNALS
M8228
WAVEFORMS
9,
- tpw
\....J
:k
)I(
8080 DATA BUS
tS:~-
DBIf'1
..- ts;;J
\
1
tRR
.
HlDA
INTA, lOR, MEMR
DURING HLDA
SYSTEM BUS DURING READ
8080 BUS DURING READ
r--
I~
t De ...
'\
---------------
__
tHD
. . 1--10s - -- tDHj
---ri
1
P
-
._-------
I~
A
t RE - -
l~
j
--------------
..
\
WR
tWR~ ,I~
IOWOR MEMW
8080 BUS DURING WRITE
------------------------tRE
'\
1
~11~tWR
1
---------j- j
SYSTEM BUS DURING WRITE -
-
-
-
-
-
-
-
<
-
-
-
tWE --
SYSTEM BUS ENABLE
SYSTEM BUS OUTPUTS -
}
-
-
-
-
-
-
-
-
-
-
-
-
{
_t~I_- >- - - - - - - - - - - - - - -
~
t--
VOLTAG EM EASUREMENT POI NTS: 00-07 (when outputs) Logic "0" = 0.8V, Logic "1" = 3.0V. All other signals measured
at 1.5V.
..~
I
11-42
inter
808SA
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
• Single
+ 5V Supply
• 4 Vectored Interrupts (One is NonMaskable)
• 100% Software Compatible with
8080A
• Serial In/Serial Out Port
• 1.3 P.s Instruction Cycle
• On·Chip Clock Generator (with
External Crystal or RC Network)
• Decimal, Binary, and Double Precision
Arithmetic
• On·Chip System Controller; Advanced
Cycle Status Information Available for
Large System Control
• Direct Addressing Capability to 64K
Bytes of Memory
The Intel®8085A is a new generation, complete 8 bit parallel central processing unit (CPU). Its instruction set is 100%
software compatible with the 8080A microprocessor, and it is designed to improve the present 8080's performance by
higher system speed. Its high level of system integration allows a minimum system of 3IC's: 8085A (CPU), 8156 (RAM),
and 8355/8755A (ROM/PROM).
The 8085A incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) provided for the
8080, thereby offering a high level of system integration.
The 8085A uses a multiplexed data bus. The address is split between the 8-bit address bus and the 8-bit data bus. The
on-chip address latches of 8155/8156/8355/8755A memory products allows a direct interface with the 8085A.
BLOCK DIAGRAM
'T
I
IACCUMULAT~~I I
11
TEMP. REG.
TRAP
RST6.5
INTA
1
RT
l
5
RT
5
sr
l
I
INTERRUPT CONTROL
t
StD
SERIAL 1/0 CONTROL
8·BIT INTERNAL DATA BUS
I
J
1
JII
INSTRUCTION
REGISTER (8)
lSi
l
I F~I~~~O~~ I
t t
~~H'
INSTRUCTION
DECODER
AND
MACHINE
CYCLE
ENCODING
lOGIC
UNIT
(ALU)
===--
181
e
lSi
B
REG,
'"
D
REG.
lSi
E
REG.
IBI
181
l
181
H
REG.
REG.
_~EGISTER
ARRAY
REG
(161
STACK POINTER
(161
PROGRAM COUNTER
POWER
SUPPLY
{~+5V
tNCREMENTERiOECREMENTER
_GND
ADDRESS LATCH
TIMING AND CONTROL
X,~
elK
X2~
GEN
eLK
CONTROL
STATUS
DMA
RESET
~
~OUT 1 ~~ Ate }os~ JIM 1 HtJ..READY
HOLD
RESJOUT
RESET IN
11-43
I
\161
1
ADDRESS BUFFER
~
15 8
ADDRESS BUS
181
1
U
DATA/ADDRESS BUFFER (8)1
~
AD 7 -AD 0
ADDRESS/DATA BUS
8085A
PIN DESCRIPTION
The following describes the function of each pin:
x,
vee
Aa-A15 (Output 3-State)
X2
HOLD
Address Bus; The most significant 8-bits of the memory
address or the B-bits of the liD address,3-stated during
Hold and Halt modes.
RESET OUT
ClK (OUT)
SID
RESET IN
TRAP
ADo_7 (Input/Output 3-state)
RST7.S
Multiplexed AddresslData Bus; Lower 8-bits of the
memory address (or liD address) appear on the bus
during the first clock cycle of a machine state. It then
becomes the data bus during the second and third clock
cycles.
HlDA
SOD
READY
101M
RST 6.S
5,
RSTS.S
RD
3-stated during Hold and Halt modes,
ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of
a machine state and enables the address to get latched into
the on-chip latch of peripherals. The falling edge of ALE is set
to guarantee setup and hold times for the address information.
ALE can also be used to strobe the status information. ALE
is never 3-stated.
INTR
WR
INTA
ALE
ADo
So
AD,
A,s
AD2
A'4
AD3
A13
AD4
A'2
ADs
A"
A,o
ADs
AD7
Ag
Vss
As
so, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:
S1
-
o
o
So
-
0
1
o
Figure 1. Pin Configuration
HALT
WRITE
READ
FETCH
S1 can be used as an advanced RIW status.
buses in the next clock cycle. HLDA goes low after the
Hold request is removed. The CPU takes the buses one
half clock cycle after HLDA goes low.
RD (Output 3-state)
INTR (Input)
READ; indicates the selected memory or liD device is to be
read and that the Data Bus is available for the data transfer.
3-stated during Hold and Halt.
WRITE; indicates the data on the Data Bus is to be written
into the selected memory or liD location. Data is set up at
the trailing edge of WR. 3-stated during Hold and Halt
modes.
INTERRUPT REQUEST; is used as a general purpose
interrupt. It is sampled only during the next to the last
clock cycle of the instruction. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an
INTA will be issued. During this cycle a RESTART or
CALL instruction can be inserted to jump to the interrupt
service routine. The INTR is enabled and disabled by
software. It is disabled by Reset and immediately after an
interrupt is accepted.
READY (Input)
INTA (Output)
If Ready is high during a read or write cycle, it indicates
that the memory or peripheral is ready to send or receive
data. If Ready is low, the CPU will wait for Ready to go high
before completing the read or write cycle.
INTERRUPT ACKNOWLEDGE; is used instead of (and
has the same timing as) RD during the Instruction cycle
after an I NTR is accepted. It can be used to activate the
8259 Interrupt chip or some other interrupt port.
WR (Output 3-state)
I.:
..
HOLD (input)
HOLD; indicates that another Master is requesting the use
of the Address and Data Buses. The CPU, upon receiving
the Hold request, will relinquish the use of buses as soon
as the completion of the current machine cycle. Internal
processing can continue. The processor can regain the
buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and 101M lines
are 3-stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU h'as
received the Hold request and that it will relinquish the
11·44
RSTS.S
RST 6.S
RST 7.S
}
(Inputs)
RESTART INTERRUPTS; These three inputs have the
same timing as INTR except they cause an intemal
RESTART to be automatically inserted.
RST 7.5 ~ Highest Priority
RST 6.5
RST 5.5 ..". Lowest Priority
The priority of these interrupts is ordered as shown above.
These interrupts have a higher priority than the INTR.
808SA
The 8085A provides RD, WR, and 10lMemory signals for
bus control. An Interrupt Acknowledge signal (INTA) is
also provided. Hold, Ready, and all Interrupts are
synchronized. The 808SA also provides serial input data
(SID) and serial output data (SOD) lines for simple serial
interface.
TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is
recognized at the same time as INTR. It is unaffected by
any mask or I nterrupt Enable. It has the highest priority of
any interrupt.
RESET IN (Input)
In addition to these features, the 8085A has three
maskable, restart interrupts and one nonmaskable trap
interrupt.
Reset sets the Program Counter to zero and resets the
Interrupt Enable and HlDA flip-flops. None of the other
flags or registers (except the instruction register) are
affected. The CPU is held in the reset condition as long as
Reset is applied.
8085A VS. 8080A
RESET OUT (Output)
The 8085A includes the following features on-Chip in
addition to all of the 8080A functions.
Indicates CPU is being reset. Can be used as a system
RESET. The signal is synchronized to the processor clock.
X1, X2 (Input)
Crystal or RIC network connections to set the internal
clock generator. Xl can also be an external clock input
instead of a crystal. The input frequency is divided by 2 to
give the internal operating frequency.
elK (Output)
Clock Output for use as a system clock when a crystal or
RIC network is used as an input to the CPU. The period of
ClK is twice the X1, X2 input period.
a.
b.
c.
d.
e.
f.
g.
h.
j.
Internal clock generator
Clock output
Fully synchronized Ready
Schmitt action on RESET IN
RESET OUT pin
RD, WR, and 101M Bus Control Signals
Encoded Status information
Multiplexed Address and Data
Direct Restarts and nonmaskable Interrupt
Serial Input/Output lines.
The internal clock generator requires an external crystal
or R-C network. It will oscillate at twice the basic CPU
operating frequency. A 50% duty cycle, two phase,
nonoverlapping clock is generated from this oscillator
internally and one phase of the clock (<1>2) is available as an
external clock. The 808SA directly provides the external
ROY synchronization previously provided by the 8224.
The RESET IN input is provided with a Schmitt action
input so that power-on reset only requires a resistor and
capaCitor. RESET OUT is provided for System RESET.
101M (Output)
101M indicates whether the ReadlWrite is to memory or
1/0. Tri-stated during Hold and Halt modes.
SID (Input)
Serial input data line. The data on this line is loaded into
accumulator bit 7 whenever a RIM instruction is executed.
SOD (output)
The 8085A provides RD, WR and 101M signals for Bus
control. An INTA which was previously provided by the
8228 in 8080 system is also included in 8085A.
Serial output data line. The output SOD is set or reset as
specified by the SIM instruction.
Vee
Status Information
Status information is directly available from the 8085A.
ALE serves as a status stobe. The status is partially
encoded, and provides the user with advanced timing of
the type of bus transfer being done. 101M cycle status
signal is provided directly also. Decoded So, S 1carries the
following status information:
+5 volt supply.
VSS
Ground Reference.
FUNCTIONAL DESCRIPTION
The 8085A is a complete 8-bit parallel central processor. It
is designed with N-channel depletion loads and requires a
single +5 volt supply. Its basic clock speed is 3 MHz thus
improving on the present 8080's performance with higher
system speed. Also it is designed to fit into a minimum
system of three IC's: The CPU, a RAMIIO, and a ROM or
PROMIIO chip.
-..!L
~
HALT
0
0
WRITE
0
READ
1
0
FETCH
The 8085A uses a multiplexed Data Bus. The address is
split between the higher 8-bit Address Bus and the lower
8-bit AddresslData Bus. During the first cycle the address
is sent out. The lower 8-bits are latched into the
peripherals by the Address latch Enable (ALE). During
the rest of the machine cycle the Data Bus is used for
memory or 1/0 data.
S1 can be interpreted as RiW in all bus transfers.
I n the 808SA the 8 lSB of address are multiplexed with the
data instead of status. The ALE line is used as a strobe to
enter the lower half of the address into the memory or
peripheral address latch. This also frees extra pins for
expanded interrupt capability.
11-45
808SA
Interrupt and Serial 1/0
The 8085A has 5 interrupt inputs: INTR, RST 5.5, RST 6.5,
RST 7.5, and TRAP. INTR is identical in function to the
8080 INT. Each of three RESTART inputs, 5.5,6.5,7.5, has
a programmable mask. TRAP is also a RESTART interrupt
except it is non-maskable.
The three RESTART interrupts cause the internal
execution of RST (saving the program counter in the
stack and branching to the RESTART address) if the
interrupts are enabled and if the interrupt mask is not set.
The nonmaskable TRAP causes the internal execution of
a RST independent of the state of the interrupt enable or
masks.
RESTART Address (Hex)
Name
TRAP
RST 5.5
RST 6.5
RST 7.5
24 16
2C 16
34 16
3C 16
There are two different types of inputs in the restart
interrupts. RST 5.5 and RST 6.5 are high level-sensitive
like INTR (and INT on the 8080) and are recognized with
the same timing as INTR. RST 7.5 is rising edge-sensitive.
For RST 7.5, only a pulse is required to set an internal flip
flop which generates the internal interrupt request. The
RST 7.5 request flip flop remains set until the request is
serviced. Then it is reset automatically. This flip flop may
also be reset by using the SIM instruction or by issuing a
RESET IN to the 8085A. The RST 7.5 internal flip flop will
be set by a pulse on the RST7.5 pin even when the RST7.5
interrupt is masked out.
The status of the three RST interrupt masks can only be
affected by the SIM instruction and RESET IN.
The interrupts are arranged in a fixed priority that
determines which interrupt is to be recognized if more
than one is pending as follows: TRAP - highest priority,
RST 7.5, RST 6.5, RST 5.5, INTR - lowest priority. This
priority scheme does not take into account the priority of a
routine that was started by a higher priority interrupt. RST
5.5 can interrupt a RST 7.5 routine if the interrupts were reenabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic errors such as
power failure or bus error. The TRAP input is recognized
just as any other interrupt but has the highest priority. It is
not affected by any flag or mask. The TRAP input is both
edge and level sensitive. The TRAP input must go high and
M,
M,
elK
As-A15
M3
T,
PC H (HIGH ORDER ADDRESS)
(PC
+ 1)H
ADO_7
ALE
I
RD
..
WR
101M
STATUS
10 (READ)
s, So (FETCH)
Figure 2. 8085A Basic System Timing
11·46
01 WRITE
11
808SA
remain high to be acknowledged, but will not be
recognized again until it goes low, then high again. This
avoids any false triggering due to noise or logic glitches.
The following diagram illustrates the TRAP interrupt
request circuitry within the 8085A.
EXTERNAL
TRAP
INTERRUPT
REOUEST
•
•
•
•
4 8-bit 1/0 Ports
1 6-bit 1/0 Port
4 Interrupt Levels
Serial I n/Serial Out Ports
This minimum system, using the standard 1/0 technique is
as shown in Figure 3.
INSIDE THE
80SSA
In addition to standard 1/0, the memory mapped 1/0 offers
an efficient 1/0 addressing technique. With this technique,
an area of memory address space is assigned for 1/0
address, thereby, using the memory address for 1/0
manipulation. Figure 4 shows the system configuration of
Memory Mapped 1/0 using 8085A.
TRAP
RESET
+5V
D elK
D
FIF
INTERNAL
TRAP
ACKNOWLEDGE
Figure 3. 8085A Trap Interrupt Request Circuitry
Note that the servicing of any interrupt (TRAP. RST 7.5,
RST 6.5, RST 5.5, INTR) disables all future interrupts
(except TRAPs) until an EI instruction is executed.
The 8085A CPU can also interface with the standard
memory that does not have the multiplexed addressldata
bus. It will require a simple 8212 (8-bit latch) as shown in
Figure 5.
_
TRAP
_
RST7.5
_
RST6,5
_
RST5,5
-
INTR
-
TNfA
ADDR
The TRAP interrupt is special in that it preserves the
previous interrupt enable status. Performing the first RIM
instruction following a TRAP interrupt allows you to
determine whether interrupts were enabled or disabled
prior to the TRAP. All subsequent RIM instructions
provide current interrupt enable status.
x,
X,
RESET IN HOLD
HlOA
I-
r--
soot--
B085A
SIOI-
R~~~T
ADDR/
DATA ALE AD WR 101M
18)
S,t-Sot--
RDYelK
VI' Vr
18)
I~-
.-+-+-+-+-.1:'
"--+-+++-+-1 REi
T"
ALE
V-.-.-.--....---.--.--,-v
PORT
8156
/,-L-.L--'--...L....L...J...--'-",,- OATAI
The serial I/O system is also controlled by the RIM and
SIM instructions. SID is read by RIM, and SIM sets the
SOD data.
POR~~~18)
AOOR
101M
..-+-+-",RESET
18)
B
PORT~
e
TIME~N
Fl
16)
OUTr--
Basic System Timing
The 8085A has a multiplexed Data Bus. ALE is used as a
strobe to sample the lower 8-bits of address on the Data
Bus. Fi@ure 2 shows an instruction fetch, memory read
and 1/0 write cycle (OUT). Note that during the I/O write
and read cycle that the 1/0 port address is copied on both
the upper and lower half of the address.
'-+-+-+-+-.1 lOW
+--+-+++-+-1 REi
"-+--+-+-+-+-+---1 ALE
I-+-+-+-+-+-t-lf--l CE
. ,O
~~:::::::::::~~::::~~"'JlA
V 835518755A
As in the 8080, the READY line is used to extend the read
and write pulse lengths so that the 8085A can be used with
slow memory. Hold causes the CPU to relinguish the bus
when it is through with it by floating the Address and Data
Buses.
/,-L-.L--'--...L....L...J...--'-.I'\ OAT AI
'r.-.-.-....-.---.--,-vrI AOOR
101M
PORT
..-+-+-",RESET'
B
System Interface
2K Bytes ROM
256 Bytes RAM
1 Timer/Counter
ROY
~
elK
,t J t 1
8085A family includes memory components, which are
directly compatible to the 8085A CPU. For example, a
system consisting of the three ch;ps, 8085A, 8156, and
8355 will have the following features:
•
•
•
~--
~
18)
Vss Vee Voo PAOG
Figure 4. 8085A Minimum System (Standard I/O
Technique)
11·47
SOSSA
BOSSA MINIMUM SYSTEM CONFIGURATION
AB-15
A
ADO-7
V
ALE
BOS5A
-
RD
-
WR
101M
elK
RESET OUT
I-I--
READY
Vee
TIMER
RESET
WARD
IN
ALE
7-
eE"
;~~"
101M
AD _ 10/
0-7 CE iii; ALE
ADfOW ClKRST ROY
T6~~R_
8355 [ROM
OR
8156
(RAM, I/O. CQUNTERtrIMER)
S BS
SS
Figure 5. MCS·85™ Minimum System (Memory Mapped 1/0)
Vss Vee
----
j j
X,
TRAP
X,
-
RESET IN
HOLD
RST 7.5
HLDA
RST 6.5
SOD
BOSSA
RST 5.5
S,
RESET
So
OUT
ADDR/
DATA ALE AD WR 101M
ROY elK
ADDR
(8)
f----f-----
SID
INTR
INTA
-
f----f-----
(8)
101M (CS)
WR
8212
+ lID]
8755A [PROM + I/O]
lID
t-
DATA
A
STANDARD
MEMORY
ADDR
res)
V
(16)
......
elK
RESET
101M (GS)
WR
AD
DATA
...h
L
STANDARD
I/O
~
ADDR
0011111
Figure 6. MCS·85™ System (Using Standard Memories)
11·48
Vee
I/O PORTS,
CONTROLS
808SA
Driving the X1 and X2 Inputs
The user may drivetheXl and X2 inputs ofthe 8085A with a
crystal, an external clock source or an RC network as
shown below. The driving frequency must be twice the
desired internal operating frequency (the 8085A would
require a 6MHz crystal for 3MHz internal operation).
+5V
470.0
TO
1K .0
10-----41---1 X1
...-----<_---1
x,
25 TO 50%
DUTY CYCLE
AT 6 MHz
*
PARAllEL RESONANT
CRYSTAL (30pf lOAOING)
...------<6----1
20pf
X2
1-6 MHz
INPUT FREQUENCY
I
*X2 LEFT FLOATING.
1-6 MHz
INPUT FREQUENCY
+5V
The 20pF capacitors are required to guarantee oscillation
at the proper frequency during system startup .
...----
H
FLIP-FLOPS
+t
LOGIC
{ALU)
'"
B
REG
INSTRUCTION
DECODER
AND
MACHINE
ARITHMETIC
UNIT
18)
==-
D
REG
H
REG
CYCLE
'"
Ie,
'"
C
REG
E
REG
l
REG
ENCODING
STACK POINTER
Ie,
'"
'81
_~EGISTER
ARRAY
116)
116)
POWER
SUPPLY
PROGRAM COUNTER
{_'5V
INCA EMENTE A/DEC R EM ENTER
--GND
ADDRESS LATCH
TIMING AND CONTROL
X, -
elK
X2 - - -
GEN
CL}OUT
RESET
CONTROL
!
READY
~~
STATUS
AtE
,------c----,
DMA
U,JIM I
HOLD
I
HLDA
~
RESJ OUT
RESET IN
11-57
I
1
ADDRESS BUFFER
JJ
A,5 As
ADDRESS BUS
1161
18)
d
DATA/ADDRESS BUFFER {Bli
B
AD7 ADo
ADDRESS/DATA BUS
8085A·2
t~~
C";1'
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ....
Storage Temperature, , , .. , .. , .. '.
Voltage on Any Pin
With Respect to Ground. , , , , .. ,
Power Dissipation' , . , . , , , ' , ' , .. ,
, .. , , O°C to 70°C ~.
' ,_65°C to +150°C ,
, , ., - 0.5to 7V
, , , , ... 1.5 Watt
'COMMENT: Stresses above those lis~
Maximum Ratings" may cause permane' -"
device. This is a stress rating only and funCti
tion of the device at these or any other condl
those indicated in the operational sections of th
.
cation is not implied. Exposure to absolute maxim
rating conditions for extended periods may affect dev1f1!t,
reliability.
~(~.
'<$
D.C. CHARACTERISTICS
(TA '" o°c to 70°C; Vee'" 5V ±5%;
Symbol
vss '" OV; unless otherwise specified)
Parameter
Min.
V IL
Input low Voltage
VIH
Input High Voltage
VOL
Output low Voltage
VOH
Output High Voltage
Max.
Units
-0.5
+0.8
V
2.0
Vee +0.5
V
0.45
V
IOL = 2mA
V
IOH '" -400pA
2.4
Test Conditions
Icc
Power Supply Current
170
mA
IlL
Input leakage
±10
pA
Vln '" Vee
ILO
Output leakage
±10
pA
0.45V ..;; V out ..;; Vee
VILR
Input Low level, RESET
-0.5
+0.8
V
VIHR
Input High level, RESET
2.4
Vee +0.5
V
VHY
Hysteresis, RESET
0.25
Xl
X2
RESET OUT
SOD
SID
TRAP
RST7.5
RST6.5
RST5.5
INTR
INTA
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
VSS
V
Vee
HOLD
HlDA
elK (OUT)
' RESET IN
READY
101M
Sl
RD
WR
ALE
So
A15
A14
A13
A12
All
A10
Ag
AS
Figure 1. 8085A·2 Pinout Diagram
11·58
8085A·2
A.C. CHARACTERISTICS
Symbol
(TA
= O°C to
70°C; VCC
~/~;'~~'t'
= 5V ±5%; Vss = PV)
Min
Max
Units
tCYC
ClK Cycle Period
Parameter
200
2000
ns
t1
ClK low Time
30
ns
t2
ClK High Time
t r, tf
ClK Rise and Fall Time
tAL
Address Valid Before Trailing Edge of ALE
50
ns
tLA
Address Hold Time After ALE
50
ns
tLL
ALE Width
SO
ns
tLCK
ALE low During ClK High
50
ns
tLC
Trailing Edge of ALE to leading Edge of Control
60
tAFR
Address Float After leading Edge of READ (lNTA)
tAD
Valid Address to Valid Data In
ns
50
30
"
Test Condit1e'"
See notes 1, 2, 3, 4:
ns
ns
0
ns
350
ns
150
ns
tRD
READ (or INTA) to Valid Data
tRDH
Data Hold Time After READ (lNTA)
0
ns
tRAE
Trailing Edge of READ to Re-Enabling of Address
SO
ns
tCYC = 200ns
tCA
Address (AS-A15) Valid After Control
60
ns
CL = 150pF
tDW
Data Valid to Trailing Edge of WRITE
230
ns
tWD
Data Valid After Trailing Edge of WR ITE
40
ns
tcc
Width of Control low (RD, WR, INTA)
230
ns
tCL
Trailing Edge of Control to leading Edge of ALE
tARY
READY Valid from Address Valid
tRYS
READY Setup Time to leading Edge of ClK
tRYH
READY Hold Time
tHACK
HlDA Valid to Trailing Edge of ClK
tHABF
Bus Float After HlDA
150
ns
tHABE
H lDA to Bus Enable
150
ns
tRY
Control Trailing Edge to leading Edge of Next Control
220
ns
tAC
Address Valid to leading Edge of Control
115
ns
tHDS
HOLD Setup Time to Trailing Edge of ClK
120
ns
tHDH
HOLD Hold Time
tiNS
INTR Setup Time to Falling Edge of ClK (Ml, Tl
only); also RST and TRAP
tlNH
INTR Hold Time
25
ns
100
ns
100
ns
0
ns
40
.,
ns
0
ns
150
ns
0
ns
NOTES: 1. A8-A15 Address Specs apply to 101M, SO, and Sl,
2, For all output timing where CL '" 150pF use the following correction factors:
25pF.;; CL < 150pF: -{).10ns/pF
150pF < CL';; 300pF: +0.30ns/pF
3. Output timings are measured with purely capacitive load.
4. All timings are measured at output voltage VL ~ O.BV, VH ~ 2:0V, and 1.5V with 20ns rise and fall time on inputs.
5. To calculate timing specifications at other values of tCYC use Table 2.
11-59
'>
5\
8085A·2
Figure 2. Clock Timing Waveform
Read Operation
~
~
I
I
\'--------J/~--}--1-~\'--------J/
ClK
f4- tLCK - + '
)
ADDRESS
)
ADDRESS
T3
I
\\-_....J/
\
TWAIT
T,
I
-'tcA--~----------~----_rr_---
'AD
ALE
J
r- -'LL- i+-'LA--- t AFR -+-
I-- tAL .....
'RO
J
RD/INTA
'CC
I--'LC-N.
I------- 'AC ___
_I
t ARy
t RYH
'RY.
J
'\
READY
Write Operation
I
T,
)
/
ClK\
r-
1
tLCK
)!
ADDRESS
)
ADDRESS
I
ALE
J
WR
l- f- 'LL -
I
Tz
TWAIT
\
/
I
\
T3
/
I
\
I
,~ 'LA
X
----I !
'ow
I
'ee
j.- t AL ___
N.
i+-'LC
:]'
t -------.
1--------~~+-tCL--..
Ac
t ARy
READY
j
\
'RY.
t RYH
1
Figure 3. 8085A·2 Bus Timing
11·60
T,
8085A·2
Hold Operation
T,
T,
\
\
elK
t
HOLD
/
/
HOS '"
f-GHDH r-
(ADDRESS, CONTROLS)
\
t HACK ' "
4--t
HLDA
T,
T HOLD
\
:~
"\
t
BUS
T HOLD
\
r=t
HA8F -
HABE -
~
I
Figure 4. 8085A·2 Hold Timing
1------
BUS FLOATING*
ALE
w--------------~----~------------------~
HOLD
HLDA
*IO/M IS ALSO FLOATING DURING THIS TIME.
NOTE: THE BOS5A DOES NOT FLOAT ALE.
Figure 5. 8085A·2 Interrupt and Hold Timing
11-61
8085A·2
MACHINE CYCLE
OPCODE FETCH
MEMORY READ
MEMORY WRITE
I/O READ
I/O WRITE
ACKNOWLEDGE OF INTR
BUS IDLE
(OF)
(MR)
(MW)
(lOR)
(lOW)
(INA)
(BI): DAD
ACK. OF RST,TRAP
HALT
STATUS
101M Sl
so
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
0
1
0
0
0
0
1
1
1
0
1
TS
CONTROL
RD WR INTA
0
0
1
0
1
1
1
1
1
1
0
1
0
1
1
1
TS
TS
Figure 6. 8085A·2 Machine Cycle Chart
Status & Buses
Control
Machine
State
Sl,SO 101M As-AI5 ADo-AD7 RD,WR INTA ALE
Tl
X
X
X
X
1
1
l'
T2
X
X
X
X
X
X
0
TWAIT
X
X
X
X
X
X
0
T3
X
X
X
X
X
X
0
T4
1
ot
X
TS
1
1
0
T5
1
Ot
X
TS
1
1
0
Ts
1
ot
X
TS
1
1
0
TRESET
X
TS
TS
TS
TS
1
0
THALT
0
TS
TS
TS
TS
1
0
THOLD
X
TS
TS
TS
TS
1
0
0= Logic "0"
1 = Logic "1"
TS
X
= High Impedance
= Unspecified
* ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
t 101M
=
1 duringT4-TSof INA machine cycle.
Figure 7. 8085A·2 Machine State Chart
11·62
1
1
1
1
1
0
1
1
1
8155/8156
2048·BIT STATIC MOS RAM WITH 110 PORTS
AND TIMER
*Directly Compatible with 8080A and 8048 CPU
• 1 Programmable 6·Bit 110 Port
• 256 Words x 8 Bits
• Single
• Programmable 14·Bit Binary Counterl
Timer
+ 5V Power Supply
• Multiplexed Address and Data Bus
• Completely Static Operation
• 40·Pin DIP
• Internal Address Latch
• Chip Enable Active High (8156) or Low
(8155)
• 2 Programmable 8·Bit 110 Ports
The Intel@ 8155 and 8156 are RAM and 1/0 chips to be used in the MCS-85™ and MCS-48™ microcomputer systems.
Th RAM portion is designed with 2K-bit static cells organized as 256 x 8. They have maximum access times of 400 ns
to permit use with no wait system in an 8085A system.
The 1/0 portion consists of 3 general purpose 1/0 ports. One of the 3 ports can be programmed to be status pins, thus
allowing the other 2 ports to operate in handshake mode.
A 14-bit programmable counterltimer is also included on chip to provide either a square wave or terminal count pulse
for the CPU system. It operates in binary countdown mode, and its timer modes are programmable.
PIN CONFIGURATION
PC3
vee
pc.
PC,
TIMER IN
PC,
RESET
PC.
PC.
PB,
TIMER OUT
PB.
101M
PBs
BLOCK DIAGRAM
IO/M----I
256 X8
STATIC
RAM
PB.
RD
PB 3
WR
PB,
ALE
PB,
AD.
PB.
AlE----I
RD----I
AD,
PA,
AD,
PAs
AD3
PAs
AD.
AD.
PA.
PA 3
TIMER ClK
AD.
PA,
TIMER OUT-----'
AD,
PA,
Vss
PAa
RESET---~
* :
TIMER
8155 = CE, 8156 = CE
11-63
Vee 1+5VI
'----VSS (OVI
8155/8156
PIN DESCRIPTION
The following describes the functions of all of the 8155/8156 pins.
Symbol
RESET
ADO-7
CE or CE
Symbol
Function
The Reset signal is a pulse provided
by the 8085 to initialize the system.
Input high on this line resets the chip
and initializes the three I/O ports to'
input mode. The width of RESET
pulse should typically be 600 nsec.
(Two 8085A clock cycle timesl.
These are 3-state' Address/Data lines
that interface with the CPU lower 8bit Address/Data Bus. The 8-bit
address is latched. into the address
latch on the falling edge of the ALE.
The address can be either for the
memory section or the I/O section
depending on the polarity of the 10/M
input signal. The 8-bit data is either
written into the chip or Read from the
chip depending on the status of
WRITE or READ input signal.
PAo_7(8)
Function
These 8 pins are general purpose I/O
pins. The in/out direction is selected
by programming the Command/
Status Register.
These 8 pins are general purpose I/O
pins. The in/out direction is selected
by programming the Command/
Status Register.
PCO-S(6)
These 6 pins can function as either
input port, output port, or as control
signals for PA and PB.Programming
is done through the CIS Register.
When PCo-s are used as control
signals, they will provide the following:
PCO - A INTR (Port A ~nterrupt)
PC1 - A BF (Port A Buffer full)
PC2 - A STB (Port A Strobe)
Chip Enable: On the 8155, this pin is
CE and is ACTIVE LOW. On the8156,
this pin is CE and is ACTIVE HIGH.
PC3 PC4 PCs -
B INTR (Port B Interrupt)
B BF (Port B Buffer Full)
B STB (Port B Strobe)
Input low on this line with the Chip
Enable active enables the ADo-7
buffers. If 10/M pin is low, the RAM
content will be read outtotheAD bus.
Otherwise the content of the selected
I/O port will be read to the AD bus.
TIMER IN
This is the input to the counter timer.
TIMER OUT
This pin is the timer output. This
output can be either a square wave or
a pulse depending on the timer mode.
Input low on this line with the Chip
Enable active causes the data on the
AD lines to be written to the RAM or
I/O ports depending on the polarity of
10/M.
Vee
+5 volt supply.
Vss
Ground Reference.
ALE
Address Latch Enable: This control
signal latches both the address on the
ADo-7 lines and the state of the Chip
Enable and 10/M into the chip at the
falling edge of ALE.
10/M
10/Memory Select: This line selects
the memory if low and selects the 10 if
high.
11-64
8155/8156
OPERATIONAL DESCRIPTION
The 8-bit address on the AD lines, the Chip Enable input,
and 101M are all latched on chip atthefalling edge of ALE.
A low on the 10/M must be provided to select the memory
section.
The 8155/8156 includes the following operational
features:
• 2K Bit Static RAM organized as 256 x 8
• Two 8-bit I/O ports (PA & PB) and one 6-bit I/O port
(PC)
• 14-bit down counter
The 1/0 portion contains four registers (Commandl
Status, PAO-7, PBO-7, PCO-5). The 101M (IO/Memory
Select) pin selects the 1/0 or the memory (RAM) portion.
Detailed descriptions of memory, 1/0 ports and timer
functions will follow.
cr (8155 I
\
V
'\
I
\
/
\
V
\
OR
CE (8156 I
101M
X
ADDRESS
I\.
V
/
\
X
DATA VALID
AL E
AD OR Wii
NOTE: FOR DETAILED TIMING DIAGRAM INFORMATION. SEE FIGURE 7 AND A.C. CHARACTERISTICS.
Figure 1. Memory Read/Write Cycle
11-65
8155/8156
PROGRAMMING OF THE COMMANDI
STATUS REGISTER
READING THE COMMANDISTATUS
REGISTER
The command register consists of eight latches one for
each bit. Four bits (0-3) define the mode of the ports, two
bits (4-5) enable or disable the interrupt from port C when
it acts as control port, and the last two bits (6-7) areforthe
timer.
The status register consists of seven latches one for each
bit; six (0-5) for the status of the ports and one (6) for the
status of the ti mer.
The CIS register contents can be altered at any time by
using the I/O address XXXXXOOO during a WRITE
operation. The meaning of each bit of the command byte
is defi ned as follows:
~
L=
DEFINES PA()'7 }
0'" INPUT
DEFINES PBO-7
1 '" OUTPUT
The status of the timer and the I/O section can be polled by
reading the CIS Register (Address XXXXXOOO). Status
word format is shown below:
IX.lTIMERI1N:EI
OO=ALTl
DEFINES PC0-5
11 =ALT2
01 '" AL T 3
{
~T~BRL~U~~RT
:F IIN;RI
IL
PORT A INTERRUPT REOUEST
PORT A BUFFER FULL/EMPTY
(lNPUT/OUTPUTI
PORT A INTERRUPT ENABLE
A
1 '" ENABLE
}
L -_ _ _ _ _ _ _ _
IIN~RIIN;EI
L---
10=ALT4
'-------_
BBF
~~::RL~U~~RT B
PORT B INTERRUPT REQUEST
0'" DlSABLE
PORT B BUFFER FULL/EMPTY
(lNPUT/OUTPUTI
00'" NOP - DO NOT AFFECT COUNTER
OPERATION
01
'------TIMER COMMAND
=
PORT B INTERRUPT ENABLED
STOP - NOP IF TIMER HAS NOT STARTED;
STOP COUNTING IF THE TIMER IS
RUNNING
TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED, AND IS RESET TO
LOW UPON READING OF THE
CIS REGISTER OR STARTING
NEW COUNT.)
10'" STOP AFTER Te - STOP IMMEDIATELY
AFTER PR ESENT Te IS REACHED (NOP
IF TIMER HAS NOT STARTED)
11
=
START - LOAD MODE AND CNT LEI'JGTH
AND START IMMEDIATELY AFTER
LOADING (IF TIMER IS NOT PRESENTLY
RUNNING), IF TIMER IS RUNNING, START
THE NEW MODE AND CNT LENGTH
IMMEDIATELY AFTER PRESENT Te
IS REACHED.
Figure 2. Command/Status Register Bit Assignments
Figure 3. Command/Status Register Status Word
Format
11-66
8155/8156
The following diagram shows how 1/0 ports A and Bare
structured within the 8155 and 8156:
INPUT/OUTPUT SECTION
The I/O section of the 8155/8156 consists of four registers
as described below.
•
815518156
ONE BIT OF PORT A OR PORT B
Command/Status Register (C/S) - This register is
assigned the address XXXXXOOo. The CIS address
serves the dual purpose.
When the CIS register is selected during WRITE
operation, a command is written into the command
register. The contents of this register are not
accessible through the pins.
When the CIS (XXXXXOOO) is selected during a READ
operation, the status information of the I/O ports and
the timer become available on the ADO-7 lines.
•
PA Register - This register can be programmed to be
either input or output ports depending on the
status of the contents of the CIS Register. Also
depending on the command, this port can operate in
either the basic mode or the strobed mode (See timing
diagram). The I/O pins assigned in relation to this
register are PAO-7. The address of this register is
XXXXX001.
•
PB Register - This register functions the same as PA
Register. The I/O pins assigned are PBO-7. The address
of this register is XXXXX010.
•
PC Register - This register has the address XXXXX011
and contains only 6-bits. The 6-bits can be programmed to be either input ports, output ports or as control
signals for PA and PB by properly programming the
AD2 and AD3 bits of the CIS register.
NOTES:
(I) OUTPUT MODE }
(2) SIMPLE INPUT
(3) STROBED INPUT
INPUT MODE
OUTPUT MODE
Low
Low
Input Control
Low
High
Input Control
STB
- 1 FOR OUTPUT MODE
- 0 FOR INPUT MODE
Note in the diagram that when the I/O ports are
programmed to be output ports, the contents of the output
ports can still be read by a READ operation when
appropriately addressed.
Note also that the output latch is cleared when the port
enters the input mode. The output latch cannot be loaded
by writing to the port if the port is in the input mode. The
result is that each time a port mode is changed from input
to output, the output pins will go low. When the 8155/56 is
RESET, the output latches are all cleared and all 3 ports
enter the input mode.
When in the AL T 1 or ALT 2 modes, the bits of PORT Care
structured like the diagram above in the simple input or
output mode, respectively.
Reading from an input port with nothing connected to the
pins will provide unpredictable results.
When the 'C' port is programmed to either AL T3 or AL T4,
the control signals for PA and PB are initialized as follows:
BF
INTR
(4)
READ PORT' (lO!liii-l). (Ril=O). (CE ACTIVE). (PORT ADDRESS SELECTED)
WRITE PORT - (lO!liii-l). (i'ilI-O). (CE ACTIVE). (PORT ADDRESS SELECTED)
When PCO-5 is used as a control port, 3-bits are
assigned for Port A and 3 for Port B. The first bit is an
interrupt that the 8155 sends out. The second is an
output signal indicating whether the buffer is full or
empty, and the third is an input pin to accept a strobe
for the strobed input mode. See Table 1.
CONTROL
MULTIPLEXER
CONTROL
Table 1. Table of Port Control Assignment
Pin
PCO
PCl
PC2
PC3
PC4
PCS
ALT 1
Input
Input
Input
Input
Input
Input
Port
Port
Port
Port
Port
Port
ALT2
Output
Output
Output
Output
Output
Output
Port
Port
Port
Port
Port
Port
ALT3
A INTR (Port A Interrupt)
A B.EJf.'ort A Buffer Full)
A STB (Port A Strobe)
Output Port
Output Port
Output Port
ALT4
A INTR (Port A Interrupt)
A B.EJf.'ort A Buffer Full)
A STB (Port A Strobe)
B INTR (Port B Interrupt)
B B.EJf.'ort B Buffer Full)
B STB (Port B Strobe)
The set and reset of INTR and BF with respectto STB, WR and RD timing is shown in Figure 8.
To summarize, the registers' assignments are:
Address
XXXXXOOO
XXXXXOOl
XXXXX010
XXXXXOll
Pinouts Functions
Internal
PAO-7
PBo-7
PCO-5
.11·67
CommandlStatus Register
General Purpose 1/0 Port
General Purpose 1/0 Port
General Purpose 1/0 Port or
Control Lines
No. of Bits
8
8
8
6
8155/8156
TIMER SECTION
The timer is a 14-bit down counter that counts the 'timer
input' pulses and provides either a square wave or pulse
when terminal count (TCl is reached.
I
I
M21 MI
TIll T121 TIl
'----rl-...JI
The timer has the I/O address XXXXX100 for the low order
byte of the register and the I/O address XXXXX101 for the
high order byte of the register.
TIMER MODE
To program the timer, the COUNT LENGTH REG is
loaded first, one byte at a time, by selecting the timer
add resses. Bits 0-13 will specify the length of the next
count and bits 14-15 will specify the timer output mode.
The value loaded into the count length register can have
any value from 2H through 3FFFH in Bits 0-13.
I I
TID
T91 Tal
-----r-------'
L.I
MSB OF CNT LENGTH
I
LSB OF CNT LENGTH
Figure 4. Timer Format
There are four modes to choose from:
O.
Puts out low during second half of count.
1. Square wave
2. Single pulse upon TC being reached
3. Repetitive single pulse everytime TC is readied and
automatic reload of counter upon TC being reached, until
instructed to stop by a new command loaded into CIS.
M2
Note: See the further description on Command/Status
Register.
o
NOP -
Do not affect counter operation.
STOP - NOP if timer has not started; stop
counting if the timer is running.
o
M2
Ml
o
o
Puts out low during second half of
count.
Square wave, I.e., the period of the
square wave equals the count
length programmed with automatic reload at terminal count.
o
Single pulse upon TC being
reached.
Automatic reload, I.e., single pulse
every time TC is reached.
o
Bits 6-7 of Command/Status Register Contents are used
to start and stop the counter. There are four commands to
choose from:
C/S7 C/Ss
---o 0
M1 defines the timer mode as follows:
Note: In case of an asymmetric count, i. e. 9, larger half of
the count will be high, the larger count will stay active as
shown in Figure 5.
STOP AFTER TC - Stop immediately after
present TC is reached (NOP iftimer has not
started)
START - Load mode and CNT length and
start immediately after loading (if timer is
not presently running). If timer is running,
start the new mode and CNT length
immediately after present TC is reached.
-
5
-
Note: 5 and 4 refer to the number of clock cycles in that
time period.
Figure 5. Asymmetric Count
The counter in the 8155 is not initialized to any particular
mode or count when hardware RESET occurs, but RESET
does stop the counting. Therefore, counting cannot begin
following RESET until a START command is issued via the
CIS register.
11·68
8155/8156
8085A MINIMUM SYSTEM
CONFIGURATION
Figure 6shows that a minimum system is possible using only
three chips:
• 256 Bytes RAM
• ··2K Bytes ROM
• 38 I/O Pins
• 1 Interval Timer
• 4 Interru pt Levels
A8-15
"
A
~
ADO-7
"ALE
8085A
/
~
liD
WR
V
:,.
-
101M
-
ClK
-
RESET OUT
READY
vee
TIMER
IN
RESET
ViR AD
ALE
CEV
10/M
V
ASAIO
AD
7
V0-
EE I~/
ALE
1iD~ ClKRS
t
T6~~R_
B
8156
--l
'--'--
CONTROL
lATCHES
I
+
I
256 x 8
RAM
'----
1
8355 [ROM + 1/01
OR
8755A [PROM + 1/01
8155
~~~~
BBB
Figure 6. 8085 Minimum System Configuration
11-69
BB
RDY
8155/8156
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of thisspecifi·
cation is not implied. Exposure to absoiLite maximum
rating conditions for extended periods may affect device
reliability.
TernperatureUnderBias ................ 0°Cto+70°C
Storage Temperature ............... -65°Cto+150°C
Voltage on Any Pin
With Respect to Ground .. . . . . . . . . . . . .. -0.3V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
(TA = O°C to 70 D C; Vee = 5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
Vil
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee +O·5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
III
Input Leakage
±10
ILO
Output Leakage Current
Icc
Vee Supply Current
Ill(CE)
Ch ip Enable Leakage
8155
8156
2.4
V
TEST CONDITIONS
IOl = 2rnA
IOH = -4001lA
pA
VIN = Vee to OV
±10
pA
0.45V -7
A port can be read out when the latched Chip Enables are
active and either RD goes low with 101M high, or lOR goes
low. Both input and output mode bits of a selected port will
appear on lines AD O_Y'
BOS5A
v
ALE
r-
RD
WR
CLK (02)
To clarify the function of the 1/0 ports and Data Direction Registers, Figure 1 shows the configuration of one
bit of PORT A and DDR A. The same logic applies to
PORT Band DDR 13.
READY
101M
Vee
t-t-t-t--
.1
r-
J
J'~'~
ADO_7
8355
iiiR
ONE BIT OF PORT A AND DDR A:
AS_10
RO elK
101M
ALE iiiW REAOY CE
8355
Figure 2_ 8355 in 8085A System (Memory Mapped 1/0)
-'
~
ffi
~
RESET
WRITE DDR A
DO
-----r
READ PA
WRITE PA = (iiiW=o). (CHIP ENABLES ACTIVE) • (PORT A ADDRESS SELECTED)
WRITE DDR A '" (iOW=D). (CHIP ENABLES ACTIVE) • (DOR A ADDRESS SELECTED)
READ PA = {[(I0/M=1). (RD=Ol] + (iOR=o)} • (CHIP ENABLES ACTIVE). (PORT A ADDRESSSELECTEO)
Figure 1_ 8355 Block Diagram Showing One Bit of Port
A and DDR A
11-79
"-
AS-15
Al1
A12
A13
A,.
A,.
,/
A
BOSSA
~
ALE
RD
ViR
elK (.p2)
........
00
o
READY
,--
,--
r-
,----
,----
rrrr-
rrr-
I--
I--
I--
-
rrrr-
i--
-
r-
-
I-I--
101M
vee
J
iOii
vee
AlDa_1
"
T
AII-IO
AD
ALE
eLK
iOW
101M
READY
;,
AID(l..7
CE
fiR
'--
-
" s_
A IO
vee
ALE
eLK
row
101M
READY
AlDO_1
CE
iOii
I--
-
As-10
RD
ALE
iOW
8355
8355
(2K BYTES)
(2K BYTES)
(2K BYTES)
101M
READY CE
eLK
vee
r
A/°0-7
fOR
"
AS_10
ALE
eLK
iOW
101M
READY
A/0O-J
CE
C1I
C1I
7
t
RD
lOR
8355
(2K BYTES)
Use CE for the first 8355 in the system, and CE for the other 8355's. Permits up to 5 ea. 8355's in a
system without CE decoder.
Figure 3. 8355 in 8085A System (Standard 10)
co
Co)
I--
vee
8355
Note:
I--
I-I--
J"'
AD
I--
AS-10
RD eLK
101M
ALE iOW READY
8355
(2KBVTES)
CE
8355
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias ................ O°C to +70°C
Storage Temperature ............... -65° C to +150° C
Voltage on Any Pin
With Respect to Ground ............... -0.3Vto +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
(TA
= o°c to
UNITS
-0.5
0.8
V
Vee = 5.0V
2.0
Vec+O· 5
V
Vee = 5.0V
0.45
V
IOL = 2mA
10
IlA
VIN = Vee to OV
±10
IlA
0.45V ~VOUT ~Vee
180
mA
PARAMETER
MIN.
VIL
Input low Voltage
VIH
Input High Voltage
VOL
Output low Voltage
VOH
Output High Voltage
IlL
Input leakage
ILO
Output leakage Current
lec
Vee Supply Current
SYMBOL
= 5V ± 5%)
MAX.
SYMBOL
A.C. CHARACTERISTICS
70°C; Vee
TEST CONDITIONS
V
2.4
IOH = -4001lA
(TA = o°c to 70°C; Vee = 5V ± 5%)
PARAMETER
MIN.
MAX.
UNITS
teye
Clock Cycle Time
320
ns
Tl
ClK Pulse Width
80
ns
T2
ClK Pulse Width
120
ns
tf,t r
ClK Rise and Fall Time
30
ns
tAL
Address to latch Set Up Time
50
Address Hold Time after latch
80
ns
tLC
Latch to R EAD/WR ITE Control
100
ns
tRO
Valid Data Out Delay from READ Control
tAD
Address Stable to Data Out Valid
tLL
Latch Enable Width
tROF
Data Bus Float after READ
170
400
ns
ns
ns
100
100
ns
teL
R EAD/WR ITE Control to latch Enable
20
ns
tee
R EAD/WR ITE Control Width
250
ns
tow
Data In to WR ITE Set Up Time
150
ns
two
Data In Hold Time After WR ITE
10
ns
twp
WR ITE to Port Output
tpR
Port Input Set Up Time
50
tRP
Port Input Hold Time
50
tRYH
READY HOLD TIME
0
tARY
ADDRESS (CE) to READY
tRv
Recovery Time between Controls
tROE
Data Out Delay from READ Control
400
11-81
CLOAO = 150 pF
ns
tLA
0
TEST CONDITIONS
ns
ns
ns
160
ns
160
ns
300
ns
10
ns
150 pF load
8355
WAVEFORMS
O.8V
Figure 4. Clock Specification for 8355
ClK
A8-10
101M
~
ADDRESS
tAD
~
ICE - 1)·
ICE-D)
~
)
ADDRESS
'll ~
r----- 'LA ~
DATA
r\
r/
ALE
I-- 'AL-
1+ 'ROF •
t--tROE~
t"----tRD~
I------ t LC ~
'OW~~-~
f - - - - t CC · -
I I------
rtRV
I--two~
----~----"
t"---tCL~
Figure 5. ROM Read and 110 Read and Write
11·82
8355
Figure 6. Wait Siale Timing (READY 5 0)
A. INPUT MODE
PORT
INPUT
DATA*- BUS
-- -
-
-y
-------
--------------------
B. OUTPUT MODE
GLITCH FREE
_ _ _ _ _ _ _ _ _ _ t::-_--j-ool-~/OUTPUT
PORT
OUTPUT
DATA* - BUS
____ _
'"
-I\._______
*DATA BUS TIMING IS SHOWN IN FIGURE 3.
Figure 7. I/O Pori Timing
11·83
X. . ____
..J
8755A
16,384-BIT EPROM WITH 1/0 PORTS
•
Directly Compatible with 808SA and 8048 CPU
• 2048 Words x 8 Bits
• Single
+ 5V Power Supply (Vee>
• 2 General Purpose 8·Bit 1/0 Ports
• Each 1/0 Port line Individually
Programmable as Input or Output
• U.V. Erasable and Electrically
Reprogrammable
• Multiplexed Address and Data Bus
• Internal Address Latch
• 40·Pin DIP
The Intel® 8755A is an er~sable and electrically reprogrammable ROM (EPROM) and I/O chip to be used in the
MCS·85™ and MCS·48™ microcomputer systems. The PROM portion is organized as 2048 words by 8 bits. It has a
maximum access time of 400 ns to permit use with no wait states in an 8085A CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and each I/O port line is individu·
ally programmable as input or output.
PIN CONFIGURATION
PROG AND
CE
BLOCK DIAGRAM
CLK-----,
1
ADo_7
A8~10
CE
lOW
2K x 8
EPROM
101M
ALE
Ri5
lOW
RESET
~
~
lOR
PROG/CE~
voo
11·84
~Vccl+5V)
Vss IOV)
8755A
PIN DESCRIPTION
Symbol
Function
ALE
When Address latch Enable is high.
ADO-7. 10/1ii!. AS-l0. CEo and CE enter
the address latches. The signals (AD.
101M. AS-l0. CE) are latched in at the
trailing edge of ALE.
ADO-7
Bi-directional AddresslData bus. The
lower 8-bits of the PROM or liD
address are applied to the bus lines
when ALE is high.
During an liD cycle. Port A or Bare
selected based on the latched value of
ADo. If RD or lOR is low when the
latched Chip Enables are active. the
output buffers present data on the
bus.
A8-l0
These are the high order bits of the
PROM address. They do not affect
liD operations.
CEIPROG
CHIP ENABLE INPUTS: CE is active
low and CE is active high. Both chip
;m;;,bles must be aCtiVe"' to permit
accessing the PROM.
is also used
as a programming pin (see section on
programming) ..
CE
Read operation is selected by either
lOR low and active Chip Enables and
ADo low. Q[ 10/Mhigh. RD low. active
Chip Enables. and ADo low.
PBO-7
This general purpose liD port is
identical to Port A except that it is
selected by a 1 latched from ADO.
RESET
In normal operation. an input high on
RESET causes all pins in Ports A and
B to assume input mode (clear DDR
register).
When the Chip Enables are active. a
low on lOR will output the selected
liD port onto the AD bus. lOR low
performs the same function as the
combination of 10Ig high and RD
low. When lOR is not used in a
system. lOR should be tied to Vee
("1").
+5 volt supply.
cr
'loiM
Ground Reference.
VDD is a programming voltage. and it
is normally tied to +5V.
If the latched 10Ig is high when RD is
low. the. output data comes from an
liD port. If it is low the output data
comes from th~ PROM.
For programming. a high voltage is
supplied with VD D• = 25V. typical.
If the latched Chip Enables are active
when RD goes low. the ADO-7 output
buffers are enabled and output either
the selected PROM location or liD
port. When both RD and lOR are high,
the ADO-7 output buffers are tristated.
FUNCTIONAL DESCRIPTION
PROM Section
The 8755A contains an 8-bit address latch which allows it
to interface directly to MCS-48 and MCS-85 Microcomputers without additional hardware.
If the latched Chip Enables are active.
a low on lOW causes the output port
pointed to by the latched value of ADo
to be written with the data on ADo-7.
The state of 10Ig is ignored.
ClK
The ClK is used to force the READY
into its high impedance state after it
has been forced low by CE low. G,E
high. and ALE high.
READY
READY is a 3-state output controlled
by CEo CE. ALE and ClK. READY is
forced low when the Chip Enables are
active during the time ALE is high.
and remains low until the rising edge
of the next ClK (see Figure 2.).
PAo-7
The PROM section of the chip is addressed by the 11-bit
address and CEo The address. CE and CE are latched into
the address latches on the falling edge of ALE. If the
latched Chip Enables are active and IDig is low when RD
goes low. the contents of the PROM location addressed by
the latched address are put out on the ADO-7 lines.
1/0 Section
The liD section of the chip is addressed by the latched
value of ADo-l. Two 8-bit Data Direction Registers
determine the input/output status of each pin in the
corresponding port. A 0 specifies an input mode. and a 1
specifies an output mode. The table summarizes port and
DDR designation. Contents of the DDR's cannot be read.
These are general purpose liD pins.
Their input/output direction is determined by the contents of Data
Direction Register (DDR). Port A is
selected for write operations when
the Chip Enables are active and lOW
is low and a 0 was previously latched
from ADO'
AD1
0
0
1
1
11-85
ADO Selection
0
1
0
1
Port
Port
Port
Port
A
B
A Data Direction Register (DDR A)
B Data Direction Register (DDR B)
8755A
Erasure Characteristics
When lOW goes low and the Chip Enables are active, the
data on the AD is written into I/O port selected by the
latched value of ADO-1. During this operation all I/O bits of
the selected port are affected, regardless of their I/O mode
and the state of 101M. The actual output level does not
change until lOW returns high. (glitch free output).
The erasure characteristics of the 8755A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(.ll..). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000.8.
range. Data show that constant exposure to room level
flourescent lighting could erase the typical 8755A in
approximately 3 years while it would take approximately 1
week to cause erasure when exposed to direct sunlight. If
the 8755A is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels are
available from I ntel which should be placed over the 8755
window to prevent unintentional erasure.
A port can be read out when the latched Chip Enables are
active and either RD goes low with 10/M high, or lOR goes
low. Both input and output mode bits of a selected port will
appear on lines ADO-7.
To clarify the function of the I/O Ports and Data Direction
Registers, the following diagram shows the configuration
of one bit of PORT A and DDR A. The same logic applies to
PORT Band DDR B.
The recommended erasure procedure (see page 3-55) for
the 8755A is exposure to s'1ortwave ultraviolet light which
has a wavelength of 2537 Angstroms (.ll..). The integrated
dose (i.e., UV intensity X exposure time) for erasure
should be a minimum of 15W-sec/cm 2. The erasure time
with this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000~W/cm2 power rating.The
8755A should be placed within one inch from the lamp
tubes during erasure. Some lamps have a filter on their
tubes and this filter should be removed before erasure.
8755A
ONE BIT OF PORT A AND DOR A:
DO
~
"zffi
~
Programming
RESET
Initially, and after each erasure, all bits of the EPROM
portions of the 8755A are in the "1" state. Information is
introduced by selectively programming "0" into the
desired bit locations. A programmed "0" can only be
changed to a "1" by UV erasure.
DO
~
READ PA
WRITE PA" (Ww=OJ. (CHIP ENABLES ACTIVE). (PORT A ADDRESS SElECTED)
WRITE DDR A "
(iifw=o). (CHIP ENABLES ACTIVE) •
(oDR A ADDRESS SElECTEm
The 8755A can be programmed on -the Intel® Universal
PROM Programmer (UPP), and the PROMPT" 80/85 and
PROMPT-48'· design aids. The appropriate programming
modules and adapters for use in programming both
8755A's and 8755's are shown in the table below.
READ PA = {[(IOIM"1). (RO=Ol] + (iQR"O)) • (CHIP ENABLES ACTIVE). (PORT A ADDRESS SelECTED)
Figure 1. 8755A: One Bit of Port A and DDR A
Note that hardware RESET or writing a zero to the DDR
latch will cause the output latch's output buffer to be
disabled, preventing the data in the Output Latch from
being passed through to the pin. This is equivalent to
putting the port in the input mode. Note also that the data
can be written to the Output Latch even though the Output
Buffer has been disabled. This enables a port to be
initialized with a value prior to enabling the output.
The program mode itself consists of programming a
single address at a time, giving a single 50 msec pulse
for every address. Generally, it is desirable to have a
verify cycle after a program cycle for the same address
as shown in the attached timing diagram. In the verify
cycle (i.e., normal memory read cycle) 'Voo' should be at
o volts for the 8755, but for 8755A it should be Vee
(+ 5V). Except for the Voo level during the read cycle,
the 8755 and 8755A are functionally identical.
The diagram also shows that the contents of PORT A and
PORT B can be read even when the ports are configured
as outputs.
Preliminary timing diagrams and parameter values pertaining to the 8755/8755A programming operation are
contained on pp. 11-91 and 11-92.
Table 1. 8755/8755A Programming Module Cross
Reference
MODULE NAME
UPP 855
UPP 955
UPP UP1'4I
UPP UP2'4'
PROMPT ™ 875
PROMPT 975
PROMPT 475
WILL PROGRAM
8755
UPP
8755A
UPP 955
8755
8755A
UPP 855
PROMPT 80/85'21
8755
8755A
PROMPT 80/85
PROMPT 48'3>
8755A
USE WITH
uppl1l
NOTES: 1. Intt 1'8 l:nlv9rsal PROM Programmer module, described on p. 13-71 of
the Intel 1977 Data Catalog.
2. De!"cribAd on p. 13·39 of 1978 Data catalog.
3. Derorib....d on p. 13·34 of 1978 Data Catalog.
4. SpecIal adaptor socket
11-86
8755A
SYSTEM APPLICATIONS
A
A
"-
K;~'S
K;~'s
?
~Do-7
8085A
K
/1
"-
ADO_7
V
'\I
8085A
ALE
ALE
-
RD
WR
ClK (¢21
READY
101M
V"
WR
ClK (¢21
READY
t
-
iiiii
A8-10
101M
V
I!
fvV
AIDO_7
t-t--
RD
-
~
t-t--
t
~
rV'-.7
_,
AlD o
RD ClK
101M
ALE iiiW READY CE
iiiii
8755A
A B_10
I
RD ClK
101M
ALE iiiW READY CE
8755A
'USE CE FOR FIRST 8755A IN SYSTEM. AND CE FOR OTHERS.
BY CONNECTING CE OF EACH 8755A CHIP TO EACH OF A11
THROUGH A,s. THE MINIMUM SYSTEM CAN USE 5-8755A',
('OK BYTESI WITHOUT REQUIRING CE DECODER.
Figure 2. 8755A in 8085A System (Standard 110)
Figure 3. 8755A in 8085A System (Memory Mapped 110)
System Interface with 8048
ALE
ALE
2K X 8
PSEN I------~~I AD
8048
WR
iOW
RD
lOA
ROMI
PROM
8US
.<'-.r-~~~~::8C====~>lA/Oo~7 v.;~bH
83551
-V--'6-V
I/O
8755A
P20·P23
TEST
I/O
INPUTS
Figure 4. Interface to MCS·48™ Microcomputers
11-87
The 8755A contains an 8-bit address latch which allows
it to interface directly to MCS-48™ microcomputers
without additional hardware (Figure 4). Program memory
is accessed by applying 11 bits of address to the A o-A 1o
inputs and a low level on the loiM and CE inputs, then
latching these inputs with ALE. The CE input serves to
select one of several possible 8755A's in a system and
the 101M signal indicates that a subsequent read operation will be from program memory. While ALE is high the
A o-A 10, 101M, and CE inputs are allowed into the 8755A
and when ALE is brought low, these inputs are latched.
If the latched conditions indicate that a program
memory fetch is to occur, a low level on RD will cause
the data to be outputted on the data bus.
8755A
'COMMENT: Stresses above thOse /'~,tI
Maximum Ratings" may cause permanilfi/tia
device. This is a stress rating only and fui-wil'oba
tion of the device at these or any other condi'tloh$
those indicated in the operational sections of thi~$pe(;i
cation is not implied. Exposure to absolute max;rnu/n
rating conditions for extended periods may affect dev/de
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias .............. -10·C to +70·C
Storage Temperature ............... -65·Cto +150·C
Voltage on Any Pin
WithRespecttoGround ............... -0.5Vto+7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS,
(TA = o·C to 70·C; Vcc = 5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
Vil
Input low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vcc+O· 5
V
Vol
Output low Voltage
0.45
V
VOH
Output High Voltage
III
Input leakage
ILO
Output leakage Current
Icc
Vcc Supply Current
A.C. CHARACTERISTICS
IOl = 2mA
V
2.4
10
(TA
TEST CONDITIONS
IOH = -400JlA
JlA
VIN = Vce to OV
±10
JLA
0.45V ';;;VOUT .;;;vcc
180
mA
=o·C to 70·C; Vcc = 5V ± 5%)
MAX.
UNITS
SYMBOL
PARAMETER
MIN.
tCYC
Clock Cycle Time
320
ns
Tl
ClK Pulse Width
80
ns
T2
ClK Pulse Width
120
ns
30
tf,t.
ClK Rise and Fall Time
tAL
Address to Latch Set Up Time
50
tLA
Address Hold Time after Latch
80
ns
tlC
Latch to READIWRITE Control
100
ns
CLOAD = 150 pF
(See Figure 3)
ns
ns
tRO
Valid Data Out Delay from READ Control
170
ns
tAD
Address Stable to Data Out Valid
450
ns
tll
Latch Enable Width
100
ns
tROF
Data Bus Float after READ
0
tCl
READIWR ITE Control to Latch Enable
20
ns
tcc
READIWRITE Control Width
250
ns
tow
Data In to WRITE Set Up Time
150
ns
two
Data In Hold Time After WR ITE
30
twp
WR ITE to Port Output
100
ns
tPR
Port Input Set Up Time
50
ns
tRP
Port Input Hold Time
50
ns
tRYH
READY HOLD TIME
0
tARY
ADDRESS (CE) to READY
tRY
Recovery Time between Controls
tROE
Data Out Delay from READ Control
ns
400
ns
160
ns
160
ns
300
ns
10
ns
11·88
TEST CONDITIONS
150 pF load
i.,
8755A
WAVEFORMS
Figure 5. Clock Specification for 8755A
""-'0
)
~
ADDRESS
ADDRESS
'AO
A00-7
)
t
ADDRESS
)
~--~
~----<
DATA
tLL ______
~tAL~
CE
>-
V
ALE
IPROG}/CE
ADDRESS
I----tLA~
\
\
-
\
I---'ROE
tRDF
~
I--
J
I+---tLe~
tow
I---- tRO
1"-
~ t-two
Q
1"-
tee
~teL
.
Figure 6. PROM Read, 1/0 Read and Write Timing
Please note that ffi must remain low for the entire cycle.
This is due to the fact that the programming enable
function common to this pin will disrupt internal data bus
levels if CE1 is taken high during the read.
11·89
______
tRV
8755A
Input Mode
A. INPUT MODE
RDOR
lOR
PORT
INPUT
DATA' BUS
-
-
-
-
-
-
)(
-------
Output Mode
------------------------------
B. OUTPUT MODE
twp -t----+j /
GLITCH FREE
OUTPUT·
PORT
OUTPUT
..A_______...JX'-____________
DATA' - '"
BUS
_____
"DATA BUS TIMING IS SHOWN IN FIGURE 6.
Figure 7. 1/0 Port Timing
eLK
eE·C{
I
ALE
Figure 8. Wait State Timing (READY = 0)
11·90
8755A
D.C. SPECIFICATION FOR PROGRAMMING
(TA ; o°c to 70°C; Vee; 5V ±5%; Vss ; OV)
SYMBOL
PARAMETER
Voo
Programming Voitage
(during write to EPROM)
100
Prog Supply Current
A.C.~SPECIFICATION
MIN.
TYP.
MAX.
UNIT
24
25
26
V
15
30
mA
TYP.
MAX.
UNIT
FOR PROGRAMMING
(TA ; o°c to 70°C; Vee; 5V ±5%; Vss ; OV)
SYMBOL
PARAMETER
MIN.
ns
tps
Data Setup Time
tpD
Data Hold Time
10
a
ns
ts
Prog Pulse Setup Time
2
!is
tH
Prog Pulse Hold Time
2
tpR
Prog Pulse Rise Time
0.01
tpF
Prog Pulse Fall Time
0.01
tpRG
Prog Pulse Width
45
11-91
!is
2
2
50
!is
!is
msec
8755A
WAVEFORMS
FUNCTION
PIN NO.
~"""------PROGRAMCYCLE-----
........-tl"'''f-----VERIFY CYCLE.----l.....II ..
ALE
A/DO_7
11
12-19
DATA TO BE
PROGRAMMED
tpD
A8-10
CE
21·23
2
PROG/CE
V DD
5
'Lf--
9
• VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE IWITH V DD = +5V FOR 8755A, V DD = OV FOR 8755.1
Figure 10. 875518755A Program Mode Timing Diagram
11·92
\'p~~GRA~
CYCl1~J
.
12 Microprocessor
Peripherals
MICROPROCESSOR PERIPHERALS
INTRODUCTION
Intel peripherals greatly enhance the 8080, the 8085, and many other microcomputers. These peripherals can slgnlfi·
cantly reduce development time, operating software, package count, board space, and parts costs while improving
performance and increasing throughput in microcomputer systems. This section contains the most up·to·date data
about Intel peripherals now available.
TABLE OF CONTENTS
Universal Peripheral Interface 8·Bit Microcomputer ................................. 12·3
8041/8741
High Speed 1 Out of 8 Binary Decoder ..........................•.........•...... 12·11
8205
B-Bit Input/Output Port ........................................................ 12:17
8212/3212
, 8·Bit Input/Output Port. ....................................................... 12·26
M82121M3212
Priority Interrupt Control Unit .................................................. 12·31
8214/3214
M8214/M3214
Priority Interrupt Control Unit. .......................... ',' ..................... 12·35
8216/8226,3216/3226 4·Bit Parallel Bidirectional Bus Driver ...................' ......................... 12·38
M8216/M3216
4·Bit Parallel Bidirectional Bus Driver ............................................ 12·43
Programmable Communication Interface ......................................... 12·46
8251A
M8251
Programmable Communication Interface ......................................... 12·62
8253/8253·5
Programmable Interval Timer ........................... : ..... ',' ................ 12·65
Programmable Peripheral Interface ............................................. 12·76
8255A/8255A·5
Programmable Peripheral Interface ............................................. 12·95
M8255A
8257/8257·5
Programmable DMA Controller. .............................................. , 12·98
Programmable Interrupt Controller. ......................... : .................. 12·111
8259/8259·5
8271
Programmable Floppy Disk Controller .......................................... 12·123
Programmable HDLC/SDLC Protocol Controller .................................. 12·142
8273
Programmable CRT Controller ................................................. 12·165
8275
Programmable Keyboard Interface ............................................. 12·188
8278
Programmable Keyboard Display Interface ...................................... 12·198
8279/8279·5
Data Encryption Unit. ........................................................ 12·209
8294
12·2
inter
8041/8741
UNIVERSAL PERIPHERAL INTERFACE
8·BIT MICROCOMPUTER
• Fully Compatible with MCS·80™ and
MCS·48™ Microprocessor Families
• Pin Compatible ROM and EPROM
Versions
• Single Level Interrupt
• 1K x 8 ROMIEPROM, 64 x 8 RAM, 18
Programmable 1/0 Pins
• 8·Bit CPU plus ROM, RAM, 1/0, Timer
and Clock in a Single Package
• Single 5V Supply
• Asynchronous Data Register for
Interface to Master Processor
• Alternative to Custom LSI
• Expandable 1/0
The Intel® 8041/8741 is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, I/O ports,
timer/counter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to function as
a peripheral controller in MCS-80'·, MCS-85'·, MCS-48'·, and other 8-bit systems.
The UPI-41'· has 1K words of program memory and 64 words of data memory on-Chip. To allow full user flexibility the
program memory is available as ROM in the 8041 version or as UV-erasable EPROM in the 8741 version. The 8741 and the
8041 are fully pin compatible for easy transition from prototype to production level designs.
The device has two 8-bit, TTL compatible I/O ports and two test inputs. Individual port lines can function as either inputs or
outputs under software control. I/O can be expanded with the 8243 device which is directly compatible and has 161/0 lines.
An 8-bit programmable timer/counter is included in the UPI device for generating timing sequences or counting external
inputs. Additional UPI features include: single 5V supply, low power standby mode (in the 8041), single-step mode for
debug(in the 8741),single level interrupt, and dual working register banks.
Because it's a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI interface
devices. It is designed to be an efficient controller as well as an arithmetic processor. Applications include keyboard
scanning, printer control, display multiplexing and similar functions which involve interfaCing peripheral devices to
microprocessor systems.
PIN CONFIGURATION
BLOCK DIAGRAM
r
DAlA
MEMORY
D,
P"
P"
p,.
P"
MASTER
SYSTEM
INTEFIFACE
""
l~
PERIPHERAL
INTERfACE
P"
P"
P"
P"
CAVSTAL,{"
LC,OR
CLOCK
POWER {
. ,.
t----==__ ---jRAMARRAV
WR
X2
VOO - -
PROMPROGRAM$UPPlY
Vee - _
+5SUI'PLY
Vu - - GROUND
12-3
8041/8741
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
AmbientTemperatureUnderBias ........ 0°Ct070°C
Storage Temperature : . . . . . . . . . . . . .. -65°C to +150°C
Voltage on Any Pin With
RespecttoGround ...................... 0.5Vto+7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
TA
= o·c to 70·C, Vcc = VOO = +5V ±5%, VSS = ov
Limits
Symbol
Parameter
Min.
Max.
Unit
VIL
Input Low Voltage(AIi
Except X1, X2)
-0.5
O.B
V
VIH
Input High Voltage (All
Except X1, X2 RESET)
2.0
Vcc
V
VIH2
Input High Voltage (X1,
RESET)
3.0
Vce
V
VOL
Output Low Voltage (00-07,
Sync)
0.45
V
IOL = 2.0 mA
VOL2
Output Low Voltage (All
Other Outputs Except Prog)
0.45
V
IOL = 1.6 mA
Typ.
Test Conditions
VOH
Output High Voltage (00-07)
2.4
V
IOH = -400 ttA
VOH1
Output High Voltage (All
Other Outputs)
2.4
V
IOH =-50~A
IlL
Input Leakage Current
(To. T1, RD. WR, CS. Ao. EA)
±10
JJ.A
Vss :S VIN :S Vce
IOL
Output Leakage Current
(00-07. High Z State)
±10
JJ.A
Vss + 0.45 :S VIN :S Vee
100
Voo Supply Current
10
25
mA
65
135
mA
Ice + 100 Total Supply Current
Output Low Voltage (Prog)
VOL3
0.45
V
ILI1
Low Input Source Current
P1Q-P17 P20-P27
0.4
mA
VIL = O.BV
IOL = 1.0 mA
ILI2
Low Input Source Current
RESET.SS
0.2
mA
VIL = O.BV
A.C. CHARACTERISTICS
TA
= o·c to 70·C, Vce = Voo = +5V
±5%, Vss
= OV
DBB Read:
Symbol
Parameter
~
tAR
CS, Ao Setup to RD
tRA
CS, Ao Hold After RD t
tRR
RD Pulse Width
tAD
CS, Ao to Data Out Delay
tRO
RD
~
8741
Min.
RD t to Data Float Delay
tRY
Recovery Time Between Reads
AndlOr Write
tCY
Cycle Time
Min.
Max.
Units
60
0
ns
30
0
ns
300
2)( tCY
200
10
,
ns
250
370
to Data Out Delay
tOF
8041
Max.
150
ns
150
ns
10
140
tCY
= 2.5 fJs
ns
100
ns
1
1
fJs
2.5
2.5
fJs
12-4
Test Conditions
6 MHz Crystal
8041187~1
.j
DBB Write:
Symbol
tAW
$741
Parameter
Min.
CS, Ao Setup to WR ~
tWA
CS, Ao Hold After WR t
tww
WR Pulse Width
tow
Data Setup to WR t
two
Data Hold After WR t
8041
Max.
Min.
300
250
30
"'IX.
0
60
30
Te,!lt CQ"dltjol'lS
.
ns
ns
ICY = 2.5 /AS
ns
0
ns
A.C. TEST CONDITIONS
DrDo Outputs
RL = 2.2k to Vss
4.3k to Vee
CL = 100pF
WAVEFORMS
Read Operation -
BOR Ao
Data Bus Buffer Register
~
K
-tAR-·
r--tRA-
Y
\
eI OR Ao
-WR
(READ CONTflOLI
Data Bus Buffer Register
4 +--~lr -'ww~----'I.~_,.----->NA~
r
1
DATA
(lNPUTI _ _ _ _M..;.A..;.V..:.CH..;.A..;.NG:.:E~_
(SYSTEM'S
ADDRESS aus)
_
'W.RITE
-------'o-w-----' DATA BUS
\
-'0'1
_ t Rp' _
_-_'AD
Write Operation -
(SYSTEM'S
ADDRESS BUS)
'RV
'RR
'wo
~ -DATAVALI~-I\I
_..J1'
.
DATA
____..,.M-A-Y-CH-A-NG-E...,..._--..,.
~
12·5
',~
.
ns·
0
250
150
2)( tCY
"'
Units
CO~TROLI
..
8041/8741
PIN DESCRIPTION
UPI INSTRUCTION SET
Signal
Description
Mnemonic
Do-D7
Three-state, bi-directional, DATA BUS
BUFFER lines used to interface the UPI-41
to an 8-bit master system data bus.
ACCUMULATOR
PlO-P17
ADD A,Rr
ADD A,@Rr
ADD A,#data
ADDC A.Rr
AD DC A,@Rr
ADDC A,#data
ANL A.Rr
ANL A,@Rr
ANL A,#data
ORl A,Rr
ORl A,@Rr
ORL A,#data
XRl A,Rr
XRl A.@Rr
XRl A,#data
INC A
DEC A
CLR A
CPL A
DA A
SWAP A
RL A
RlC A
RR A
RRC A
8-bit, PORT 1, quasi-bi-directional I/O
lines.
8-bit, PORT 2, quasi-bi-directional I/O
lines
The lower 4-bits (P20-Pn) interface directly
to the 8243 I/O expander device and contain address and data information during
PORT 4-7 access.
I/O write input which enables the master
CPU to write data and command words to
the UPI-41 DATA BUS BUFFER.
I/O read input which enables the master
CPU to read data and status words from the
DATA BUS BUFFER or status register.
Chip select input used to select one UPI-41
out of several connected to a common data
bus.
Ao
Address input used by the master processor to indicate whether byte transfer is data
or command.
To, Tl
Input pins which can be directly tested
using conditional branch instructions.
TO is used during PROM programming and
verification in the 8741.
Inputs for a crystal, LC or an external timing signal to determine the internal oscillator frequency.
EA
PROG
Output signal which occurs once per UPI41 instruction cycle. SYNC can be used as a
strobe for external circuitry; it is also used
to synchronize single step operation.
MO'V A,Rr
MOV A,@Rr
MOV A.#data
MOV Rr.A
MOV @Rr,A
MOV Rr.#data
MOV @Rr,#data
MOV A,PSW
MOV PSW.A
XCH A,Rr
XCH A,@Rr
XCHD A,@Rr
MOVP A,@A
MOVP3, A.@A
External access input which allows emulation, testing and PROM/ROM verification.
. Multifunction pin used as the program
pulse input during PROM programming.
Input used to reset status flip-flops and to
set the program counter to zero.
RESET is also used during PROM programming and verification.
Single step input used in the 8741 in
conjunction with the SYNC output to step
the program through each instruction.
Vss
Add reg ister to A
Add data memory to A
Add immediate to A
Add immed. to A with carry
Add immed. to A with carry
Add immed. to A with carry
AND register to A
AND data memory to A
AND immediate to A
OR register to A
OR data memory to A
OR immediate to A
Exclusive OR register to A
Exclusive OR data memory to A
Exclusive OR immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap digits of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Input port to A
Output A to port
AND immediate to port
OR immediate to port
Input DBB to A, clear IBF
Output A to DBB, set OBF
Input Expander port to A
Output A to Expander port
AND A to Expander port
OR A to Expander port
1
2
2
2
2
1
1
2
2
1
1
1
1
1
1
1
2
2
2
2
DATA MOVES
During I/O expander access the PROG pin
acts as an address/data strobe to the 8243.
Vee
Voo
Bytes Cycles
INPUT/OUTPUT
IN A.Pp
OUTL Pp.A
ANL Pp,#data
ORl Pp,#data
IN A,DBB
OUT DBB,A
MOVD A,Pp
MOVD Pp,A
ANlD Pp,A
ORlD Pp,A
T1 also functions as the event timer input
(under software control).
SYNC
Description
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange digit of A and register
Move to A from current page
Move to A from page 3
TIMER/COUNTER
MOV A,T
MOV T,A
STRT T
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
+5V power supply pin.
+5V during normal operation.Programming
supply pin during PROM programming. Low
power standby pin in ROM version.
Circuit ground potential.
12-6
Read Timer !Counter
Load Timer !Counter
Start Timer
Start Counter
Stop Timer !Counter
Enable Timer !Counter Interrupt
Disable Timer !Counter Interrupt
1
1
2
1
1
2
2
1
1
1
1
1
1
1
1
1
2
1
1
2
2
1
1
1
1
1
2
2
804118741
Mnemonic
Description
Bytes
Cycles
CONTROL
BRANCH
JMP addr
JMPP @A
DJNZ R,addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNIBF addr
JOBF addr
JBb addr
REGISTERS
INC Rr
INC @Rr
DEC Rr
Increment register
Increment data memory
Decrement register
SUBROUTINE
CALL addr
RET
RETR
2
2
2
Jump to subroutine
Return
Return and restore status
FLAGS
CLR
CPL
CLR
CPL
C
C
FO
FO
Clear F1 Flag
Complement F1 Flag
CLR F1
CPL F1
Enable IBF Interrupt
Disable IBF Interrupt
Select register bank 0
Select register bank 1
No Operation
EN I
DIS I
SEL RBO
SEL RB1
NOP
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Jump unconditional
2
Jump indirect
1
Decrement register and skip
2
2
Jump on Carry = 1
Jump on Carry = 0
2
Jump on A Zero
2
Jump on A not Zero
2
2
Jump on TO = 1
Jump on TO = 0
2
Jump on T1 = 1
2
Jump on T1 = 0
2
Jump on FO Flag = 1
2
Jump on F1 Flag = 1
2
Jump on Timer Flag = 1, Clear Flag 2
Jump on IBF Flag = 0
2
Jump on OBF Flag = 1
2
Jump on Accumulator Bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
APPLICATIONS
01 0_3
DBO_3
000_3
-",
[-
8216
r.e
PERIPHERAL
CONTROL
INTERFACE
T1
PROG
101M
A14
A15
(STROBE)
"THE 8041 ~OES NOT REQUIRE
8216 BUS DRIVERS
Figure 1. Recommended 8741 Interface to an 8085 System
I
8041/8741
DATA BUS
CONTROL. BUS
CONTROL BUS
Figure 3. 8041 Matrix Printer Interface
Figure 2. 8041-8243 Keyboard Scanner
12·7
8041/8741
The program/verify sequence is:
PROGRAMMING, VERIFYING, AND
ERASING THE 8748 EPROM
1_ Voo = 5V, clock applied or internal oscillator
operating, RESET = OV, TEST 0 = 5V, EA = 5V,
BUS and PROG floating_
2_ Insert 8748 in programming socket
ProgramminglVerification
3_ TEST 0
= OV (select program
mode)_
4_ EA = 25V (activate program mode)_
In brief, the programming process consists of: activating the program mode, applying an address, latching the
address, applying data, and applying a programming
pulse_ Each word is programmed completely before
moving on to the next and is followed by a verification
step_ The following is a list of the pins used for programming and a description of their functions:
5_ Address applied to BUS and P20-1.
6. RESET = 5V (latch address).
7. Data applied to BUS.
8. Vo = 25V (programming power).
9. PROG = OV followed by one 50 ms pulse to 25V.
10. Voo = 5V.
11. TEST 0 = 5V (verify mode).
12. Read and verify data on BUS.
Pin
XTAL 1
13. TEST 0 = OV.
Function
Clock input (1 to 6 MHz)
14. RESET = OV and repeat from step 5.
15. Programmer should be at conditions of step 1 when
8748 is removed from socket
RESET
Initialization and address latching
TEST 0
Selection of program or verify mode
EA
Activation of program/verify modes
Programming Options
BUS
Address and data input data output during
verify
The 8748 EPROM can be programmed by either of two
Intel products:
P20-1
Address input
1. PROMPT·48 Microcomputer Design Aid.
Voo
Programming power supply
PROG
Program pulse input
2. Universal PROM Programmer (UPP-101 or UPP-102)
Peripheral of the Intellec® Development System with
a UPP-848 Personality Card.
+5V
RESET
- - - BUS AND PROG CAN BE DRIVEN ONLY DURING THIS TIME
+5V--
-----
---I
TEST 0
+25V
EA
+5V------'
<
BUS
C
P20·21
I
ADOR ESS AO-A7
X
AOOR ESS AS-Ag
)
DATA
)
<
DATA OUT
+25V
VOO
+5V-------------------------
.JI
+25V
PAOG
+5V------;~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+OV
WARNING: An attempt to program a missocketed 8748 will result in severe damage to the part. An indication of a properly socketed part
is the appearance of the ALE clock output, The lack of this clock may be used to disable the programmer.
Figure 5_ Programming/Verification Sequence
12-8
8041/8741
8748 Erasure Characteristics
time, opaque labels are available from Intel which
should be placed over the 8748 window to prevent
unintentional erasure.
The erasure characteristics of the 8748 are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms (A)_ It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8748 in approximately 3 years while It would take approximately one week to cause erasure when exposed
to direct sunlight. If the 8748 is to be exposed to these
types of lighting conditions for extended periods of
The recommended erasure procedure for the 8748 is exposure to shortwave ultraviolet light which has a wavelength of 2537 A. The integrated dose (I.e., UV Intensity
x exposure time) for erasure should be a minimum of 15
W-sec/cm 2• The erasure time with this dosage is approxImately 15 to 20 minutes using an ultraviolet lamp with a
12,000 /AW/cm 2 power rating. The 8748 should be placed
within one inch of the lamp tubes during erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
A.C. TIMING SPECIFICATION FOR PROGRAMMING
TA = 25°C ±5°C, Vcc = 5V ±S%, Voo = 2SV ±1V
Symbol
Min.
Parameter
tAW
Address Setup Time to RESET t
4tcy
tWA
Address Hold Time After RESET t
4tcy
tow
Data in Setup Time to PROG ,
4tcy
two
Data in Hold Time After PROG I
4tcy
tpH
RESET Hold Time to Verify
4tcy
tvoow
Voo
4tcy
tVOOH
Voo Hold Time After PROG I
0
tpw
Program Pulse Width
SO
tTw
Test 0 Setup Time for Program Mode
4tcy
4tcy
tWT
Test 0 Hold Time After Program Mode
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
tr. tf
Voo and PROG Rise and Fall Times
0.5
tCY
CPU Operation Cycle Time
5.0
tRE
RESET Setup Time Before EA ,
4tcy
Note: If TEST 0 is high. too
can
Max.
Unit
60
MS
Test Conditions
4tcy
2.0
p's
p's
be triggered by RESET 1.
D.C. SPECIFICATION FOR PROGRAMMING
TA = 2SoC ±soC, Vcc = SV ±S%, Voo = 2SV ±1V
Symbol
Parameter
Min.
Max.
Unit
VOOH
Voo Program Voltage High Level
24.0
26.0
V
VOOL
Voo Voltage Low Level
4.75
5.25
V
VPH
PROG Program Voltage High Level
21.5
24.5
V
VPL
PROG Voltage Low Level
0.2
V
VEAH
EA Program or Verify Voltage High Level
24.5
V
VEAL
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
mA
IpROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
12-9
21.5
Test Conditions
8041/8741
WAVEFORMS
Combination ProgramlVerify Mode (EPROMs Only)
tTW _
1 - : : - - - - - - - - - - PROGRAM
,-______'\1'0--------
----------.-J---- VERIFV--·'
PROGRAM - - - - -
TO
08 0-08,
J--
---<
DATA TO BE
PROGRAMMED,VALID
NEXT ADDR
VALID
C
NEXT
ADDRESS
LAST
ADDRESS
,~::;~ ~ ~ __-_-" '\~ ~ ~ ~ ~-t_D-:_V-fl_D_D,-W~-~__
J ·-----r
-
--,,'-------
Verify Mode (ROM/EPROM)
VERIFY MODE IROM/EPRDM)
TO,RESET
~\,--,_ _- - J/
J-______
ADDRESS
10-7) VALID
\'----- - -<,"__A_~_~_~_:S_S_-JX,-~_~_~_Tv_~_~_i~-J>-
--J~'"_ _ _ _ _
A_D_D_R_E_SS_I_8-_9_)V_A_L_I_D_ _ _ _
12·10
__J~'"
-
-
-
-
-
-
______
N_EX_T_AD_D_R_E_S_S_V_A_Ll_D_ _ _ _ _ _ _
-
~
inter
8205
HIGH SPEED 1 OUT OF 8 BINARY DECODER
• Low Input Load Current - 0.25 rnA
Max, 116 Standard TTL Input Load
• 1/0 Port or Memory Selector
• Simple Expansion -
Enable Inputs
• High Speed Schottky Bipolar
Technology - 18 ns Max Delay
• Directly Compatible with TTL Logic
Circuits
• Minimum Line Reflection - Low
Voltage Diode Input Clamp
• Outputs Sink 10 rnA Min
• 16·Pin Dual In· Line Ceramic or Plastic
Package
The Intel@ 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory
components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low", thus a single
row of a memory system is selected. The 3-chip enable inputs on the 8205 allow easy system expansion. For very large
systems, 8205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory
expansions.
The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature
range of ooe to +75°e, ambient. The use of Schottky barrier diode clamped transistors to obtain fast switching speeds
results in higher performance than equivalent devices made with a gold diffussion process.
PIN CONFIGURATION
LOGIC SYMBOL
Ao
16
V-cc
Ao
A,
15
00
A,
14
0,
A2
13
°2
A2
3
E,
4
8205
8205
E2
5
12
03
E3
6
11
0.
E,
10
°5
E,
9
06
E,
°7
GRD
8
PIN NAMES
AO· A,
ADDRESS INPUTS
E,· E,
00· 0,
ENABLE INPUTS
DECODED OUTPUTS
12-11
ADDRESS
ENABLE
Ao
A,
A,
L
H
L
L
L
Ii
" " '3
H
H
L
L
L
L
L
H
L
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
L
H
H
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
0
,
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
,j
H
H
H
H
H
H
H
H
OUTPUTS
2
3
4
S
6
7
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
,j
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
8205
FUNCTIONAL DESCRIPTION
Decoder
The 8205 contains a one out of eight binary decoder. It accepts a three bit binary code and by gating this input, creates
an exclusive output that represents the value of the input
code.
Ao----I
0,
----·1
0,
A,----·I
0,
A,
0,
For example, if a binary code of 101 was present on the AO,
A 1 and A2 address input lines, and the device was enabled,
an active low signal wou Id appear on the 05 output line.
Note that all of the other output pins are sitting at a logic
high, thus the decoded output is said to be exclusive. The
decoders outputs will follow the truth table shown below in
the saine manner for all other input variations.
DECODER
0.
0,
0.
0,
Enable Gate
When using a decoder it is often necessary to gate the outputs with timing or enabling signals so that the exclusive
output of the decoded value is synchronous with the overall
system.
(E'i 'E2'E3)
Figure 1_ Enable Gate
The 8205 has a built-in function for such gating. The three
enable inputs (Ei, E2, E3) are ANDed together and create
a single enable signal for the decoder. The combination of
both active "high" and active "low" device enable inputs
provides the designer with a powerfully flexible gating function to help reduce package count in his system.
ADDRESS
12-12
ENABLE
OUTPUTS
Ao
A,
A2
E,
E2
E3
a
1
2
3
4
5
6
7
L
H
L
H
L
H
l
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
fI
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
8205
ray of 8205s can be used to create a simple interface to a
24K memory system.
APPLICATIONS OF THE 8205
The 8205 can be used in a wide variety of applications in
microcomputer systems. I/O ports can be decoded from the
address bus. chip select signals can be generated to select
memory devices and the type of machine state such as in
8008 systems can be derived from a simple decoding of the
state lines (SO. S1. S2) of the 8008 CPU.
1/0 Port Decoder
Shown in the figure below is a typical application of the
8205. Address input lines are decoded by a group of 8205s
(3). Each input has a binary weight. For example. AO is as·
signed a value of 1 and is the LSB; A4 is assigned a value of
16 and is the MSB. By connecting them to the decoders as
shown. an active low signal that is exclusive in nature and
represents the value of the input address lines. is available at
the outputs of the 8205s.
This circuit can be used to generate enable signals for I/O
ports or any other decoder related application.
Note that no external gating is required to decode up to 24
exclusive devices and that a simple addition of an inverter
or two will allow expansion to even larger decoder net·
works.
The memory devices used can be either ROM or RAM and
are 1Kin storage capacity. 8308s and 81 02s are the devices
typically used for this application. This type of memory device has ten (10) address inputs and an active "low" chip
select (CS). The lower order address bits AO·A9 which come
from the microprocessor are "bussed" to all memory elements and the chip select to enable a specific device or group
of devices comes from the array of 8205s. The output of
the 8205 is active low so it is directly compatible with the
memory components.
Basic operation is that the CPU issues an address to identify
a specific memory location in which it wishes to "write" or
"read" data. The most significant address bits A 1O·A 14 are
decoded by the array of 8205s and an exclusive. active low.
chip select is generated that enables a specific memory device. The least significant address bits AO-A9 identify a
specific location within the selected device. Thus. all ad'
dresses throughout the entire memory array are exclusive
in nature and are non-redundant.
This technique can be expanded almost indefinitely to support even larger systems with the addition of a few inverters
and an extra decoder (8205).
Chip Select Decoder
>
Using a very similar circuit to the I/O port decoder. an ar·
Ao
Ao
A,
A,
8205
E1
E,
E,
EN
E,
E,
' - - Ao
0 0 0--- '6
~A,
0,0--- fi
t--
A,
A,
8205
E,
EN
'-----
A,
E,
E,
E,
A,
A,
8205
E,
E,
E,
j--
A,
g
A,
8205
PORT
NUMBERS
E,
GNO
°op----;
o,p----'cs,
o;p----,cs,
o,p----'cs,
o.P---- CS,
o,p---- cs,
o,p---- cs,
o,p-- CS;
O;;P---o,p---- C:S
o,p--iCS"
I--Ao
E,
E,
'-- Ao
o;p-- CS 11
o,p--- CSi2
o;p-- CS"
o;p---- CS"
o,p-- cs"
0;;0---
0, 0---
'--A,
L--",
0'P--- iii
8205
N
Ao
Oof>--i
o,f>--'
o,f>--.
o,f>--'
0, p---o,p-o,p--o,p--oop---o,p--o,p--- io
o,p--- fi
o,p--- "
o,p--- i3
0, p---- i,
o,p--- f'
I-- Ao
~~MORIES
Ao-"\L_________
0,
0---
p---0, p---0; p----
0;
o,p--- ill
o,p-- 2c-
TA =
ooc
I
I
.8
(V~
1.0
=
1.0
TA ::: 75"C
I
!
1.0
4.0
OUTPUT "HIGH" VOLTAGE (V)
12-15
1
r\
TA ::: 25"C
2.0
3.0
Vc~ = 5 0V
t--- I---
TA - DOC
I
2.0
-
3.0
Ii
o
1-4.0
TA '" 75°C
I{
-50
.6
1;.---+-25"C
I
-40
TA =25"C
OUTPUT "lOW" VOLTAGE
""1
UJ.
,II
-30
"
.4
fI
150J
-10
-20
h ,.... r- TA=O°C
-
I-t
.Y
TA = 75"C _
-~5'C_ t-.. ~
80
DATA TRANSFER FUNCTION
5.0
5.0
~
H- -\1\
-I
\
\
\ \
\. \, ~
o
.2
.4
.6
.8
1.0
1.2 1.4 1.6
INPUT VOLTAGE
(vf
1.8 2.0
.205
SWitCHiNG OHA'RAcTEfUS'fICS
'=-;;'f'
eC>V1dlftGn$ Of TM
TeetLC)ad
'3900
Input pulse amplitudes: 2.5V
iii~ut rise 'and fall, Wnes: 5 nsec
between 1V and 2V
Measurements are made at 1.5V
2K
All TransistOls 2N2369 or Equivalent,
eL = 30 pF
Te't WaYef6nne
ADDRESS OR ENABLE
INPUT PULSE
},---
'.,;t';.>j'
.,.....
A.C. CHARACTRISTICS
'fA
= O'C to + 75',C, Vee = 5V ;t 5% unless otherwise specified.
~VMBOL
,
MAX. LiM~T
PARAMETER
t++
ADDRESS OR ENABLE TO
OUTPUT DELAY
C+
"
t+_
t __
ns
18
ns
18
ns
ns
18
<;N (1)'
INPUT CAPACITANCE
-1. ThIs parameter
1$
P8205
C8205
TEST CONDITIONS
UNIT
18
4(typ.)
5(typ.)
pF
pF
f
= 1 MHz, Vee = OV
= 2.0V, T A = 250 e
vBIAS
periodIcally sampled and IS not 100% tested.
TYPICAL,~""'ARACTER.STICS
ADDRESS OR ENABLE TO OUTPUT
ADDRESS ClR ENABLE TO OUTPUT
Ol:LAV VS. LOAD CAPACITANCE
DE LA Y VS. AMBI ENT TEMPERATURE
ro,'
20
Vee = 5.OV
T• • 2~"C
15
~
"
S
"'0
t._, t__
I
t_.+
I
------+-----10
t ..
~
l!:"
"
0
o~------~------~----~
o
LOAD CAPACITANCE (pFI
25
50
AMBIENT TEMPERATURE ("C)
12·16
75
inter
8212/3212*
8·BIT INPUT/OUTPUT PORT
• Fully Parallel 8·Bit Data Register and
Buffer
• 3.S5V Output High Voltage for Direct
Interface to 8080 CPU or 8008 CPU
• Service Request Flip·Flop for Interrupt
Generation
• Asynchronous Register Clear
• Low Input Load Current - 0.25 rnA Max
• Replaces Buffers, Latches, and Multi·
plexers in Microcomputer Systems
• 3·State Outputs
• Reduces System Package Count
• Outputs Sink 15 rnA
The Intel@ 8212 input/output port consists of an 8·bit latch with 3·state output buffers along with control and device
selection logic. Also included is a service request flip·flop for the generation and control of interrupts to the
microprocessor.
The device is multi mode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the
principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
·Note: The specifications for the 3212 are identical with those for the 8212.
LOGIC DIAGRAM
PIN CONFIGURATION
SERVICE REOUEST FF
os,
vcc
MD
INT
01,
01 8
DO,
0°8
01,
01,
DO,
DO,
01 3
01 6
0°3
0°6
01.
01 5
D0.
0°5
STB
CLR
GND
OS,
[DDs,
OJ> os,
V
MO
----+ S T 8 ~-"""'---i._'/
II> D', - - - - - - - - + - H
[[> 0', - - - - - - - = - - H
PIN NAMES
01,·0"
00,·00,
~'DS2
MD
STB
INT
CLR
DATA IN
DATA OUT
DEVICE SELECT
MODE
STROBE
INTERRUPT (ACTIVE lOW)
CLEAR (ACTIVE lOW)
§> 0'8 ----------L--H
[g> C L R - - - - - < t
12·17
OUTPUT
BUFFER
8212/3212
FUNCTIONAL DESCRIPTION
Data Latch
The 8 flip-flops that make up the data latch are of a
"0" type design. The output (a) of the flip-flop will
follow the data input (0) while the clock input (e) is
high. Latching will occur when the clock (e) returns
low.
The data latch is cleared by an asynchronous reset
input (CLR). (Note: Clock (C) Overides Reset (CLR).)
Output Buffer
The outputs of the data latch (a) are connected to
3-state, non-inverting output buffers. These buffers
have a common control line (EN); this control line
either enables the buffer to transmit the data from
the outputs of the data latch (a) or disables the
buffer, forcing the output into a high impedance
state. (3 -state)
Service Reqeust Flip·Flop
The (SR) flip-flop is used to generate and control
interrupts in microcomputer systems. It is asynchronously set by the CLR input (active low). When
the (SR) flip-flop is set it is in the non-interrupting
state.
The output of the (SR) flip-flop (a) is connected to
an inverting input of a "NOR" gate. The other input
to the "NOR" gate is non-inverting and is connected
to the device selection logic (081 • OS2). The output
of the "NOR" gate (INT) is active low (interrupting
state) for connection to active low input priority
generating circuits.
SERVICE REQUEST FF
This high-impedance state allows the designer to
connect the 8212 directly onto the microprocessor
bi-directional data bus.
IT> MD ----HH_,/
!D.> S TB ~--+--f
OUTPUT
BUFFER
Control Logic
The 8212 has control inputs 081, OS2, MO and
STB. These inputs are used to control device selection, data latching, output buffer state and service
request flip-flop.
D01~
[I> 0 " - - - - - - - + - t i
DATALATCH
DS1, DS2 (Device Select)
These 2 inputs are used for device selection. When
OS1 is low and OS2 is high (OS1 . OS2) the device is
selected. In the selected state the output buffer is
enabled and the service request flip-flop (SR) is
asynchronously set.
MD (Mode)
~ 0 '6 - - - - - - - - - - c - i - I
This input is used to control the state of the output
buffer and to determine the source of the clock input
(e) to the data latch.
When MO is high (output mode) the output buffers
are enabled and the source of clock (e) to the data
latch is from the device selection logic (081 ·OS2).
When MO is low (input mode) the output buffer state
is determined by the device selection logic (081 .
OS2) and the source of clock (e) to the data latch is
the STB (Strobe) input.
IE> 0 '7 - - - - - - - + - t i
007
[i}>
~
DOS
[i>
D18-------...L..ti
l8> C L R - - - - - < i
STB (Strobe)
This input is used as the clock (C) to the data latch
for the input mode MO = 0) and to synchronously
reset the service request flip-flop (SR).
STB
MD
(081' 052)
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
DATA OUT EQUALS
3 STATE
3-STATE
DATA LATCH
DATA LATCH
DATA LATCH
DATA IN
DATA IN
DATA IN
CLR
0
0
1
1
1
1
(05" 052)
0
1
1
1
0
1
SETS SR FLIP· FLOP
(NO EFFECT ON OUTPUT BUFFER)
Figure 1. Service Flip·Flop Function
12·18
'SR
INT
0
0
1
1
0
1
1
1
1
0
0
0
1
0
'-0
0
'-
-INTERNAL SR FLIP· FlOP
CLA - RESETS DATA LATCH
Note that the SR flip-flop is negative edge triggered.
STB
8212/3212
APPLICATIONS OF THE 8212 MICROCOMPUTER SYSTEMS
FOR
• Interrupt instruction port
• Output port
• Basic schematic symbols
• 8080A status latch
• Gated buffer
• 8085A address latch
• Bidirectional bus driver
• Interrupting input port
Basic Schematic Symbols
Two examples of ways to draw the 8212 on system
schematics--(1) the top being the detailed view
showing pin numbers, and (2) the bottom being the
symbolic view showing the system input or output
as a system bus (bus containing 8 parallel lines).
The output to the data bus is symbolic in referencing 8 parallel lines.
INPUT DEVICE
OUTPUT DEVICE
11
11
STB
STB
01
7
9
16
18
8212
10
10
15
17
(DETAILEDI
19
16
18
20
22
23
INPUT
STROBE
DO
01
DO
GND
8212
INT
CLR
MD
-
15
17
19
21
14
Vee
SYSTEM
INPUT
OUTPUT
FLAG
SYSTEM
OUTPUT
(SYMBOLICI
GND
DATA BUS
Figure 2. Basic Schematic Symbols
Gated Buffer (3·State)
The simplest use of the 8212 is that of a gated
buffer. By tying the mode signal low and the strobe
input high, the data latch is acting as a straight
through gate. The output buffers are then enabled
from the device selection logic OS1 and OS2.
When the device selection logic is false, the outputs
are 3-state.
~e--~--------------~
STB
INPUT
DATA
(250 "AI
8212
~--------~CLR
When the device selection logic is true, the input
GATING
{
CONTROL
data from the system is directly transferred to the
(OS1.0S21
-----_-----------'
output. The input data load is 250 micro amps. The
output data can sink 15 milli amps. The minimum
high output is 3.65 volts.
Figure 3. Gated Buffer (3·State)
12·19
OUTPUT
DATA
115mAI
IJ.65V MINI
8212/3212
Bidirectional Bus Driver
A pair of 8212's wired (back-to-back) can be used
as a symmetrical drive, bi-directional bus driver.
The devices are controlled by the data bus input
control which is connected to 051 on the first 8212
and to 052 on the second. One device is active, and
acting as a straight through buffer the other is in
3-state mode. This is a very useful circuit in small
system design.
.l
srB
DATA
BUS
I
0
'"
r-<
DATA BUS
CONTROL
10= L - RI
II = R - LI
-
.1
8212
-V
DATA
BUS
CLR
Y
G~D L STB
~
8212
L
CLR
----.J
t--Y
GND
Interrupting Input Port
This use of an 8212 is that of a system input port
that accepts a strobe from the system input source,
which in turn clears the service request flip-flop
and interrupts the processor. The processor then
goes through a service routine, identifies the port,
and causes the device selection logic to go true enabling the system input data onto the data bus.
Figure 4. Bidirectional Bus Driver
DATA
BUS
INPUT
STROBE
STB
SYSTEM
INPUT
SYSTEM
RESET
PORT
{
SELECTION
IDS1.DS21
_ _ _ _ _---1
+-___ i~C~~~~R~~0ICKT
OR
TO CPU
INTERRUPT INPUT
Interrupt Instruction Port
The 8212 can be used to gate the interrupt instruction, normally RESTART instructions, onto the data
bus. The device is enabled from the interrupt
acknowledge signal from the microprocessor and
from a port selection signal. This signal is normally
tied to ground. (051 could be used to multiplex a
variety of interrupt instruction ports onto a common bus).
Figure 5. Interrupting Input Port
DATA
BUS
STB
RESTART
INSTRUCTION
IRST 0 - RST 71
IDSI) PORT SELECTION
INTERRUPT ACKNOWLEDGE _ _-
Figure 6. Interrupt Instruction Port
12-20
_ _-J
8212/3212
Output Port (WIth Handshaking)
The 8212 can be used to transmit data from the data
bus to a system output. The output strobe could be
a hand-shaking signal such as "reception of data"
from the device that the system is outputting to. It
in turn, can interrupt the system signifying the reception of data. The selection of the port comes
from the device selection logic. (OS1· OS2)
DATA
BUS
, . - - - - - OUTPUT STROBE
STB
SYSTEM OUTPUT
SYSTEM RESET
}
SYSTEM
INTERRUPT
L - -_ _ _-
PORT SELECTION
(LATCH CONTROLI
(OSI.0S21
Figure 8. 8080 Status Latch
8080 Status Latch
Here the 8212 is used as the status latch for an 8080
microcomputer system. The input to the 8212 latch
is directly from the 8080 data bus. Timing shows
that when the SYNC signal is true, which is connected to the OS2 input and the phase 1 signal is
true, which is a TTL level coming from the clock
generator; then, the status data will be latched into
the 8212.
~
Note: The mode signal is tied high so that the output
on the latch is active and enabled all the time.
It is shown that the two areas of concern are the
bidirectional data bus of the microprocessor and the
controL.bus.
10
01 9
8
D.
7
03
3
d.
8080
SYNC
OBIN
01
12Vn
19
t1L-
02
22
ovJ \.......::
DATA BUS
4
05
5
06
6
07
STATUS
LATCH
15
~
~7
r-------CLOCK GEN.
& DRIVER
9
16
18
--
~TlI
01
Do
~
~
tl'o
r,trJ7
r,g
rt,-
8212
20
22
11 CLR
os. MO OS1
13 12
t-=-
Y1
INTA
we
STACK
HLTA
OUT
Ml
INP
MEMR
T1
01
BASIC
02
CONTROL
BUS
SYNC
DATA
OBIN
STATUS
Figure 7_ Output Port (WIth Handshaking)
12-21
T2
8212/3212
ABSOLUTE MAXIMUM RATINGS·
Temperature under bias plastic ........... O·C to 75·C
Storage temperature ................... O·C to 75·C
All output or supply voltages ........... - 0.5V to + 7V
All input voltages ................... - 1.0V to + 5.5V
Output currents ............................ 100 rnA
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at any
other condition above those indicated in the operational sections of
this specification is not implied.
D.C. CHARACTERISTICS
TA = O°Cto +75°C
Symbol
Vee = +5V ±5%
Limits
Parameter
Min.
Typ.
Unit
Test Conditions
Max.
IF
Input Load Current
ACK, OS" CR, 01,-01, Inputs
-.25
mA
VF = .45V
IF
Input Load Current
MO Input
-.75
mA
VF = .45V
IF
Input Load Current
OS, Input
-1.0
rnA
VF = .45V
I,
Input Leakage Current
ACK, OS, CR, 01,-01, Inputs
10
f-tA
V R ..; Vee
I,
Input Leakage Current
MO Input
30
f-tA
V R ";V ee
I,
Input Leakage Current
OS, Input
40
f-tA
V R ..; Vee
Ve
Input Forward Voltage Clamp
-1
V
Vil
Input "Low" Voltage
.85
V
V'H
Input "High" Voltage
2.0
VOL
Output "Low" Voltage
VOH
Output "High" Voltage
3.65
Isc
Short Circuit Output Current
-15
10
Icc
V
.45
4.0
Output Leakage Current
High Imped~nce State
Power Supply Current
le=-5mA
90
12·22
V
lo, = 15 rnA
V
10H = -1 mA
= OV, Vee =S.OV
-75
mA
Vo
20
f-tA
Va = .45V/S.25V
130
mA
821213212
TYPICAL CHARACTERISTICS
INPUT CURRENT VS. INPUT VOLTAGE
Vee
~ ls.ov
100
>-
V
TA '" 0' C
VTA
::>
u
>-
'"
f----
~25<,.
300
WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE
DATA TO OUTPUT DELAY
VS. TEMPERATURE
22
250
LOAD CAPACITANCE (pF)
25
50
75
1~2.';5-----::------:::--------;";-----;7:::-5----7..
, 00
100
TEMPERATURE (OC)
TEMPERATuRE reI
12-23
I
8212/3212
TIMING DIAGRAM
DATA
-
-
-
-
-
'5VY--- - - - -- - - - -Y,5V
1;==
"I' =.j ~ - -tpw
J,
STB or OS, • DS2
tH
5vl
,
\ .'. _5v________
I.--tWE---I
---"-1;---------
OUTPUT
____________
'_,5. JVI
....I\.',._SV__________
\,_,SV_____
OS,. DS2 _ _ _ _ _ _
~_t_E~ r
________
OUTPUT
_______ X
~E..!?~~W2_ _l.: ~~____"____
A"i-'"==--~~
_
rtpwi
'SV\
11.5V
I.
~I
te
_ _ _ _ _ _ _ _ _ _ _ _ _ _ J~~----
DO
,,5VX----------y1.5V
DATA
_____ J
STBorOS,.DS2
k
tm
t
..
,,~,-
1
I-- tPD-1
J~5:;-
tH
--~ ' - - - -
_ _ _ _ _ _ _ _ _ _ _ __
- - - -- - - - --
OUTPUT
____ ___
STB
____~~.',._5V____________________
I--- tpw
-------~
1
I
NOTE: ALTERNATIVE TEST LOAD
f.-
tR
--I
Vee
OUT
-U
CI.
'OK
1K
12-24
821213212
A.C. CHARACTERISTICS
TA
= DOC to
+75°C, Vcc
Symbol
= +5V
±5%
Limits
Parameter
Min.
Typ.
--
Unit
Test Conditions
Max.
tpw
Pulse Width
tpd
Data To Output Delay
30
ns
twe
Write Enable To Output Delay
40
ns
t,o'
Data Setup Time
15
ns
th
Data Hold Time
20
ns
Ie
Reset To Output Delay
40
ns
t,
Set To Output Delay
30
ns
te
Output Enable/Disable Time
45
ns
t,
Clear To Output Delay
55
ns
ns
25
CAPACITANCE*
F = 1 MHz, VSIAS
Symbol
= 2.5V, Vcc
= +5V, TA
= 25°C
LIMITS
Test
Typ.
Max.
C'N
OS, MO Input Capacitance
9 pF
12 pF
C'N
OS2, CK, ACK, 01,-01 8
Input Capacitance
5 pF
9 pF
C OUT
00,-00 8 Output Capacitance
8 pF
12 pF
"This parameter is sampled and not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test
Input Pulse Amplitude = 2.5 V
Input Rise and Fall Times 5 ns
Between 1V and 2V Measurements made at 1.5V
with 15 mA & 30 pF Test Load
Test Load
15mA & 3DpF
300
TO
D.U.T.
"30pF
I
600
" INCLUDING JIG & PROBE CAPACITANCE
12·25
M8212/M3212*
8·BIT INPUT/OUTPUT PORT
• Fully Parallel 8·Bit Data Register and
Buffer
• 3.4V Output High Voltage for Direct
Interface to M8080A CPU
• Service Request Flip·Flop for Interrupt
Generation
• Asynchronous Register Clear
• Low Input Load Current 0.25 mA Max
• Replaces Buffers, Latches, and Multi·
plexers in Microcomputer Systems
• 3·State Outputs
• Reduces System Package Count
• Full Military Temperature Range
- 55°C to + 125°C
• ± 10% Power Supply Tolerance
• 24·Pin Dual In· Line Package
The Intel® M8212/M3212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and
device selection logic. Also included is a service request flip-flop for the generation and control of interrupts to the
microprocessor.
The device is multimode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, ali of the
principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
"Note: The specifications for the M3212 are identical with those for the M8212.
LOGIC DIAGRAM
PIN CONFIGURATION
SERVICE REQUEST FF
DS,
vee
MD
INT
DI,
DIB
DD,
DOs
DI2
DI7
DD2
D0 7
01 3
DI6
00 3
D0 6
DI4
DI5
D0 4
DOs
STB
CLR
GND
DS 2
\
[[>
DS2
[I)
MD
----H-L....J
lIT> STS ---+-..--I
J
Q> D " ----------+-I-I
DATA LATCH
~ D '2
-------.:!'l-H
PIN NAMES
DATA IN
DATA OUT
DSs-DS2
I
DEVICE SELECT
M~D~~M~O~DE~___
____
I!Y DI 6 -------+-1-1
f-fiJ~- "~C~~~~;;;:"':U""PT;;-;'-;CAe~T~IV~ELC-;;O=WIc-i
GUr-
CLEAR (ACTIVE lOW)
@> DI 7-------+--H
~D18--------L-H
~CLR-----~:~-~~
(ACTIVE LOW)
12-26
M82121M3212
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses,above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for ex tended periods may affect device
reliability.
Temperature Under Bias ........ -55°C to +125°C
Storage Temperature
.......... -65°C to +160°C
All Output or Supply Voltages .... -0.5 to +7 Volts
All Input Voltages ... _........ -1.0 to 5.5 Volts
Output Currents ...................... 100 mA
D.C. CHARACTERISTICS
T A = -55°C to +125°C Vee = +5V
Symbol
±10%
Limits
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
IF
Input Load Current
ACK, OS" CR, 01,-01 8 Inputs
-.25
mA
VF = .45V
IF
Input Load Current
MO Input
-.75
mA
VF = .45V
IF
Input Load Current
OS, Input
-1.0
mA
VF = .45V
IR
Input Leakage Current
ACK, OS, CR, 01,-01 8 Inputs
10
/.LA
VR = Vee
IR
Input Leakage Current
MD Input
30
/.LA
VR = Vee
IR
Input Leakage Current
DS, Input
40
/.LA
VR = Vee
Ve
Input Forward Voltage Clamp
-1.2
V
VIL
Input "Low" Voltage
.80
V
VIH
Input "High" Voltage
VOL
Output "Low" Voltage
.45
V
VOH
Output "High" Voltage
3.4
los
Short Circuit Output Current
-15
-75
mA
Vec
1101
Output Leakage Current
High Impedance State
20
/.LA
Va = .45V to Vee
lee
Power Supply Current
145
mA
2.0
Ie = -5 mA
V
4.0
90
12·27
V
10L = 10mA
10H = -.5mA
=
5.0V
M8212/M3212
A.C. CHARACTERISTICS
TA
= -55°C to
+125°C
Symbol
Vee = +5V ±10%
Limits
Parameter
Unit
Min.
Test Conditions
Max.
tpw
Pulse Width
tPD
Data To Output Delay
30
ns
NOTE 1
tWE
Write Enable To Output Delay
50
ns
NOTE 1
tSET
Data Setup Time
20
ns
tH
Data Hold Time
30
ns
tR
Reset To Output Delay
55
ns
NOTE 1
ts
Set To Output Delay
35
ns
NOTE 1
tE
Output Enable/Disable Time
50
ns
NOTE 1 CL = 30 pF
tc
Clear To Output Delay
55
ns
NOTE 1
CAPACITANCE
ns
40
F
Symboi
= 1 MHz, VSIAS =2.5V, Vcc =
+5V,
TA
= 25°C
LIMITS
Test
Typ.
Max.
CIN
DS, MD Input Capacitance
9 pF
12 pF
CIN
DS"CLR, STBI, 01,-01 8
Input Capacitance
5 pF
9 pF
COUT
00,-00 8 Output Capacitance
8 pF
12 pF
SWITCHING CHARACTERISTICS
Conditions of Test
Input Pulse Amplitude = 2.5V
Input Rise and Fall Times: 5 ns between 1V and 2V
NOTE 1:
TEST
'PD. 'WE. 'R.
Is.
tc
CL
R1
R2
30pF
300"
600"
'E. ENABLEt
30pF
10K"
1K"
'E. ENABLEt
30pF
300"
600"
'E. D ISAB LEt
5pF
300"
600"
'E. DISABLEt
5pF
10K"
1K"
12·28
M8212/M3212
TIMING DIAGRAM
'.5V~-
Data
--------~
5T90,05,. 05
.
2
- - - - - - - ¥'5V
Ir=='pw----r-'H~~---
,.5v1
\ __.5V______
_ _ _ _ _ _ _L_'wE_____
~I/--------
OUTPUT
________________ J\~'5V________
'-J5Vj
\ '5_V____
DS1.OS2+_MO_ _ _ _ _ _ _ _ _
~-'E1r------- ~~~-----"-
OUTPUT
- - - - - - - - - - -*\Io.--:
V
_ _ _ _
~rf'=f====!:=
1--'PWi
yr--'.5V- -
---~'.5V\
I..
-I r - - - - -
.'c
00 _________________ ~\~'.5V____
DATA
,5VX---------'-i'5V
--------~P'5ET----'5V~r
'" ~'---5T90< 05,. 05
\
2
___________k---_'p_01, ___________ _
~*('-1.5_V____________
OUTPUT
____________
5T9
,.5Vr\,.5V
-------'
'----------~'pW-1
1.SV
1.5V
1.SV
---'R-I '--_______
---J
12·29
M82121M3212
TYPICAL CHARACTERISTICS
INPUT CURRENT VS. INPUT VOLTAGE
Vee
~
100r-----~------,_------r-----_,
~~
.15.ov
-50
1-100
OUTPUT CURRENT VS. OUTPUT "LOW" VOLTAGE
Vee'" +6.0V
80r-----~r-----~------~------_i
""
TA'O"C'
;;-
..
"."
oS
V TA - 25'"C
V
Vv TA -7S'"C
~ -150
""
~
~
~
60
..
40
a;
a;
~
-200
"
0
20
-250
-300
-3
-2
+1
-1
+2
+3
INPUT VOLTAGE (V)
OUTPUT "LOW" VOLTAGE (V)
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE
50
Vee
"~5.0V
TA '" 25 C
40
;;oS
.
~
"."
."
30
a;
20
~
0
10
... ~
-
300
35
>
18
~
~
16
"
.
..
".
Q
..):,J!.,
Q
...
......
",'"
t-.
14
30
-.......
.,....w
""~
..
""
~
12
-25
!::
25
50
75
ST~<
OS,
20
OS;
...... -- ......
f-::';-
,-'
.....
t+_
t __
<~
25
50
TEMPERATURE
12-30
...'"
-
15
10
-25
100
TEMPERATURE reI
... ...' "
...
25
w
Q
10
...
~
0
0
0
;!
250
200
Vee'" +Sl,ov
c
,,/
.:""
~
150
~
40
+~.OV
!
..
~
WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE
20
>
fo ......
LOAD CAPACITANCE (pFI
DATA TO OUTPUT DELAY
VS. TEMPERATURE
Vee'
......
-
f-- -r:-
100
50
OUTPUT "HIGH" VOLTAGE (V)
22
......
\~;. .....
rei
75
100
8214/3214*
PRIORITY INTERRUPT CONTROL UNIT
• 8 Priority Levels
• Fully Expandable
• Current Status Register
• High Performance (50 ns)
• Priority Comparator
• 24-Pin Dual In· Line Package
The Intell!> 8214 is an 8-level priority interrupt control unit (PICU) designed to simplify interrupt-driven microcomputer
systems.
The PICU can accept 8 requesting levels; determine the highest priority, compare this priority to a software controlled
current status register and issue an interrupt to the system along with vector information to identify the service
routine.
The 8214 is fully expandable by the use of open collector interrupt output vector information. Control signals are also
provided to simplify this function.
The PICU is designed to support a wide variety of vectored interrupt structures and reduce package count in interruptdriven microcomputer systems.
*Note: The specifications for the 3214 are identical with those for the 8214.
PIN CONFIGURATION
LOGIC DIAGRAM
IT'>
Bo
24
Vee
B,
23
ECS
B,
22
A,
SGS
21
A,
INT
20
A,
eLK
19
A,
INTE
18
A3
...
17
A,
A,
16
A,
ELA
IIt>ETLG~~
REOUEST ACTIVITY
8214
liD
[jI>
[iD
[jI>
liD
~
Au
R;
IT>
CD
As
A,
Ao
CD
S
ECS
GND
13
ETLG
12>
ID
}B
PRIORITY
COMPARATOR
INTE
CD<
INPUTS
Ao·R1
REQUEST lEVELS (Rl HIGHEST PRIORITY)
80.8 2
CURRENT STATUS
SGS
ECS
STATUS GROUP SELECT
ENABLE CURRENT STAl"US
INTE
INTERRUPT ENABLE
ill
CLOCK UNT F·F)
ETLG
ENABLE LEVEL AEAD
ENABLE THIS LEVEL GROUP
rn
OUTPUTS:
Ao-A2
REQUEST lEVELS
J-
OPEN
iNT
INTERRUPT (ACT. LOW)
ENLG
ENABLE NEXT LEVEL GROUP
l!D
-ENLG[E>
Bo
B,
S;
[D
A; [D
I.E> As
IE> R,
15
PIN NAMES
Ao
if,
R,
R;
ID
A,
(OPEN COLLECTOR)
COLLECTOR
12-31
8214/3214
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 75°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . __ 65°C to +160°C
All Output and Supply Voltages _ ..... _ . . . . . . . . . . . . . . _ . . . . . . . . . . . . _ ... _ . . . . . . . . . . . .. -0.5V to +7V
All Input Voltages __ ... _ . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents ... _ ..... _ . . . . . . . . . . . . . _ .. _ ... _ . . . . . . . . . . . . . . . . . . . . . _ ... _ ... _ .... , 100 mA
*COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA ~ o°c to +70°C, Vee ~ 5V ±5%_
Symbol
Parameter
Ve
Input Clamp Voltage (all inputs)
IF
Input Forward Current:
ETLG input
all other inputs
IR
Input Reverse Current:
Vil
Min.
Limits
Typ.£11
Max_
Unit
Conditions
-1.0
V
le~-5mA
-0.5
-0.25
mA
mA
VF~0.45V
ETLG input
all other inputs
80
40
J.lA
J.lA
VR~5.25V
Input LOW Voltage:
all inputs
0.8
V
Vee~5.0V
VIH
Input HIGH Voltage:
all inputs
V
Vee~5.0V
Icc
Power Supply Current
90
130
mA
See Note 2.
Val
Output LOW Voltage:
all outputs
_3
.45
V
10l ~15mA
V OH
Output HIGH Voltage:
ENLG output
V
10H~-lmA
-.15
-.08
2.0
~
Ci~cuit
los
Short
leEx
Output Leakage Current: I NT and Ao-A2
Output Current: EN LG output
2.4
3.0
-20
-35
NOTES:
1. Typical values are for T A ~ 25 e, Vee = 5.0V.
2. BO-B2, SGS, elK, RO-R4 grounded, all other inputs and all outputs open.
0
12-32
-55
mA
VOS~OV, Vee~5.0V
100
J.lA
VeEx~5.25V
8214/3214
A.C. CHARACTERISTICS
Symbol
TA
= o°c to +70°C, VCC = +5V ±5%
Parameter
Min.
Limits
TypJ11
Max.
Unit
tCY
ClK Cycle Time
80
50
ns
tpw
ClK, ECS, INT Pulse Width
25
15
ns
tlSS
INTE Setup Time to ClK
16
12
ns
tlSH
INTE Hold Time after ClK
20
10
ns
tETCS[21
ETlG Setup Time to ClK
25
12
ns
tETCH[2J
ETlG Hold Time After ClK
20
10
ns
tECCS[21
ECS Setup Time to ClK
80
25
ns
tECCH[3J
ECS Hold Time After ClK
0
tECRs[31
ECS Setup Time to ClK
tECRH[3J
ECS Hold Time After ClK
0
tECSS[21
ECS Setup Time to ClK
75
tECSH[2J
ECS Hold Time After ClK
tOCS[2J
SGS and Bo ·B 2 Setup Time to ClK
110
ns
70
ns
70
ns
0
70
ns
ns
50
ns
tOCH[2J
SGS and Bo ·B 2 Hold Time After ClK
0
tRCS[3J
RO·R 7 Setup Time to ClK
90
tRCH[3J
Ro ·R 7 Hold Time After ClK
0
tiCS
INT Setup Time to ClK
55
tCI
ClK to INT Propagation Delay
tRIS I4J
Ro·R 7 Setup Time to INT
10
0
ns
tRIH[4J
Ro ·R7 Hold Time After INT
35
20
ns
ns
55
ns
ns
35
15
25
ns
tRA
Ro ·R 7 to AO·A2 Propagation Delay
80
100
ns
tELA
ElR to Ao ·A2 Propagation Delay
40
55
ns
tECA
ECS to Ao ·A 2 Propagation Delay
100
120
ns
tETA
ETlG to Ao ·A2 Propagation Delay
35
70
ns
tOECS[41
SGS and Bo·B2 Setup Time to ECS
15
10
tOECH[41
SGS and BO·B2 Hold Time After ECS
15
10
tREN
Ro ·R 7 to ENlG Propagation Delay
45
70
ns
tETEN
ETlG to ENlG Propagation Delay
20
25
ns
tECRN
ECS to ENlG Propagation Delay
85
90
ns
tECSN
ECS to ENlG Propagation Delay
35
55
ns
ns
ns
CAPACITANCE[5]
Symbol
Min.
Parameter
Limits
TypJ11
Max
Unit
10
pF
12
pF
CIN
Input Capac itance
5
COUT
Output Capacitance
7
Test Conditions:
NOTE
5.
VBIAS
= 2.5V, Vcc = 5V, TA = 25°C, f = 1 MHz
This parameter is periodically sampled and not
100%
tested.
12·33
8214/3214
WAVEFORMS
x-------
)[-----------------'1.
.------~
ETlG
INTE
-------
tRIS
r---
--"\
_...IX
'1'---------IETes
:I
------- -- --------'1.
'I '-
r----
'1'------..1,'
tACH
tRCS
J~
tOECS .~CH
\..
_J
InCH
1
I
tlSH
----------:x=x
-------JF r---..1
tecss
toes
"
tew }
lOCH
I
r
~
'I
ECAS
IEees
tECAH
teeCH
j
~~
INT
ELR
tRA
tecsH
\.
tCY
j
'<:1
------- ,--- ------ ----------..1
- ---- --- ------
~
r-----,
tpw
j'"---
------1-- -----------
ETA
IECA
tELA
r-
---------- -"'1. . _______
------ --- ----~'(
----_____________________
----------"\ ____________________ _
tECSN
ENLG
---.:.-------
-x----- -----------
t,SS
"\
tRIH
tREN
tETEN
~x
NOTES:
(1) Typical values are for T A
= 2soe ,Vee = S.OV.
(2) Required for proper operation if ISE is enabled during next clock pulse.
(3) These times are not required for proper operation but for desired change in interrupt
flip~flop.
(4) Required for new request or status to be properly loaded.
Test Load Circuit
Test Conditions
Input pulse amplitude: 2.5 volts.
I nput rise and fall times: 5 ns between 1 and 2 volts.
300n
Output loading of 15 mA and 30 pf.
I
OUTo---~--------------~
Speed measurements taken at the 1.5V levels.
30pf
12-34
600n
inter
M8214/M3214*
PRIORITY INTERRUPT CONTROL UNIT
• 24·Pin Dual In· Line Package
• 8 Priority Levels
• Fully Expandable
• Full Military Temperature Range
- 55°C to + 125°C
• Current Status Register
• + 10% Power Supply Tolerance
• Priority Comparator
The Intel@ M8214 is an 8-level priority interrupt control unit (PICU) designed to simplify interrupt-driven microcomputer systems.
The PICU can accept 8 requesting levels; determine the highest priority, compare this priority to a software controlled
current status register and issue and interrupt to the system along with vector information to identify the service
routine.
The M8214 is fully expandable by the use of open collector interrupt output vector information. Control signals are
also provided to simplify this function.
The PICU is designed to support a wide variety of vectored interrupt structures and reduce package count in interruptdriven microcomputer systems.
"Note: The specifications for the M3214 are identical with those for the M8214.
LOGIC DIAGRAM
PIN CONFIGURATION
·0.,
2.
Vee
23
'CS
22
A7
SGS
21
A6
INT
20
R,
ClK
19
A,
INTE
18
A3
Ao
17
A,
A,
'6
A,
15
Ao
.,
M8214
A,
10
'"A
11
GND
12
13
---l
CC>
QC>
Bo-8 2
CURRENT STATUS
SGS
STATUS GROUP SELECT
ENABLE CURRENT STAl'US
INTE
INTERRUPT ENABLE
ill
CLOCK UNT F·F)
ITA
ENABLE LEVEL READ
ETLG
ENABLE THIS LEVEL GROUP
"0
B,
B,
SGS
ECS
ETLG
REQUEST LEVELS (R1 HIGHEST PRIORITY),
INPUTS
Ro-R7
[D
[Q>
ENlG
"
PIN NAMES
[G>
V
CD
-=
I
INTE------------------------~
I
'I
.
ClK--------------------------~
I
I
OUTPUTS:
REQUEST LEVELS
} - OPEN
INTERRUPT (ACT. LOW)
COLLECTOR
ENLG
l~J
j-------+---------",
ENABLE NEXT LEVEl GROUP
12-35
M8214/M3214
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating onlv and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . -65°C to +160°C
All Output and Supply Voltages ........ -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . .. 100 mA
D.C. AND OPERATING CHARACTERISTICS
Symbol
Parameter
Min.
Limits
TypJ11
Max.
Unit
Conditions
-1.2
V
le=-5mA
-0.5
-0.25
mA
mA
VF=0.45V
ETLG input
all other inputs
80
40
/lA
/lA
VR=5.5V
Input LOW Voltage:
all inputs
0.8
V
Vee=5.0V
VIH
Input HIGH Voltage:
all inputs
V
Vee=5.0V
Icc
Power Supply Current
VOL
Output LOW Voltage:
all outputs
VOH
Output HIGH Voltage:
ENLG output
los
Short Circuit Output Current: EN LG output
leEx
Output Leakage Current: INT, Ao, A1, A2
Ve
Input Clamp Voltage (all inputs)
IF
Input Forward Cu rrent:
ETLG input
all other inputs
IR
Input Reverse Current:
VIL
-.15
-.08
2.0
90
130
mA
.3
.45
V
IOL =10mA
V
10H=-lmA
-55
mA
Vee=5.0V
100
/lA
VCEX=5.5V
2.4
3.0
-15
-35
NOTES:
1. Typical values are for T A = 25" e, Vee = 5.0V.
2. BO-B2, SGS, eLK, RQ-R4 grounded, all other inputs and all outputs open.
12-36
See Note 2.
M82141M3214
A.C. CHARACTERISTICS
Symbol
Parameter
Min.
tCY
ClK Cycle Time
85
tpw
ClK, ECS, INT Pulse Width
25
limits
Typ.l1]
Max.
Unit
ns
15
ns
tlSS
INTE Setup Time to ClK
16
12
ns
tlSH
INTE Hold Time after ClK
20
10
ns
tETCS[2]
ETlG Setup Time to ClK
25
12
ns
tETCH[2]
ETlG Hold Time After ClK
20
10
ns
tECCS[2]
ECS Setup Time to ClK
85
25
ns
tECCH[3]
ECS Hold Time After ClK
0
tECRS[3]
ECS Setup Time to ClK
70
ns
tECRH[3]
ECS Hold Time After ClK
0
tECSS[2]
ECS Setup Time to ClK
85
70
ns
tECSH[2]
ECS Hold Time After ClK
toCS[2]
SGS and Bo-B2 Setup Time to ClK
tOCH[2]
SGS and Bo-B2 Hold Time After ClK
tRCS[3]
Ro-R7 Setup Time to ClK
tRCH[3]
RO-R7 Hold Time After ClK
a
tiCS
INT Setup Time to ClK
55
tCI
ClK to INT Propagation Delay
tRIS[4]
Ro-R7 Setup Time to INT
10
a
ns
tRIH[4]
Ro-R7 Hold Time After INT
35
20
ns
110
ns
0
90
ns
50
ns
0
100
ns
55
ns
35
ns
ns
15
30
ns
tRA
Ro-R7 to Ao-A2 Propagation Delay
80
100
ns
tELA
ElR to Ao-A2 Propagation Delay
40
55
ns
tECA
ECS to Ao-A2 Propagation Delay
100
130
ns
tETA
ETlG to Ao-A2 Propagation Delay
35
70
ns
tOECS[4]
SGS and Bo-B2 Setup Time to ECS
20
10
tOECH[4]
SGS and Bo-B2 Hold Time After ECS
20
10
ns
tREN
Ro-R7 to ENlG Propagation Delay
45
70
ns
tETEN
ETlG to EN lG Propagation Delay
20
30
ns
tECRN
ECS to EN lG Propagation Delay
85
110
ns
tECSN
ECS to ENlG Propagation Delay
35
55
ns
ns
CAPACITANCE
limits
Typ.[1]
Max
Unit
CIN
Input Capac itance
5
10
pF
COUT
Output Capacitance
7
12
pF
Symbol
Min.
Parameter
Test Conditions:
VSIAS ; 2_5V, VCC; 5V, TA; 25°C, f; 1 MHz
12-37
8216/8226, 3216/3226*
4·BIT PARALLEL BIDIRECTIONAL BUS DRIVER
• Data Bus Buffer Driver for 8080 CPU
• 3.65V Output High Voltage for Direct
Interface to 8080 CPU
• Low Input Load Current - 0.25 rnA
Maximum
• 3·State Outputs
• High Output Drive Capability for
Driving System Bus
• Reduces System Package Count
The 8215/8226 is a 4·bit bidirectional bus driver/receiver. All inputs are low power TTL compatible. For driving MOS, the
DO outputs provide a high 3.65V VOH , and for high capacitance terminated bus structures, the DB outputs provide a
high 50 mA 10L capability. A non·inverting (8216) and an inverting (8226) are available to meet a wide variety of applica·
tions for buffering in microcomputer systems.
"Note: The specifications for the 321613226 are identical with those for the 821618226.
PIN CONFIGURATION
cs
LOGIC DIAGRAM
LOGIC DIAGRAM
8216
8226
Vee
000
OlEN
DBo
DO,
010
DB,
DO,
01,
DB,
DO,
010
010
DBo
0°0
0°0
01,
DI, ,
DO,
01,
DB,
GND
01,
.----<: DB,
DB,
DO,
01,
01,
......---<: DB,
DB,
DO,
PIN NAMES
DO,
01,
01,
......---<: DB,
DB,
DBo·oB3
DATA BUS
BI-DIRECTIONAL
D~·OI,
DATA INPUT
000 .0°3
DATA OUTPUT
OlEN
DATA IN ENABLE
DIRECTION CONTROL
CS
CHIP SELECT
DO,o---t-------+.......,
DB,
00,0---+--<1--+-.....-1
The 8216/8226 is a four bit bi-directional bus driver specif·
ically designed to buffer microcomputer system components.
01, o-----l---I.>--+.......,
Bidirectional Driver
DO,o-----l---c:::~-+--'
DB,
Each buffered line of the four bit driver consists of two
separate buffers that are tri·state in nature to achieve direct
bus interface and bi·directional capability. On one side of
the driver the output of one buffer and the input of another
are tied together (DB), this side is used to interface to the
system side components such as memories, I/O, etc., because its interface is direct TTL compatible and it has high
drive (50mA). On the other side of the driver the inputs
and outputs are separated to provide maximum flexibility.
Of course, they can be tied together so that the driver can
be used to buffer a true bi-directional bus such as the 8080
Data Bus. The DO outputs on this side of the driver have a
special high voltage output drive capability (3.65V) so that
direct interface to the 8080 and 8008 CPUs is achieved with
an adequate amount of noise immunity (350mV worst case).
DI, o---+--i :::1_-+-.,
DB,
DO, o-----l---c:::~-+--'
L.....---+.....----ocs
DIEN
(a) 8216
01.
DBo
DO.
01,
Control Gating OlEN, CS
DB,
DO,
The CS input is actually a device select. When it is "high"
the output drivers are all forced to their high-impedance
state. When it is at "zero" the device is selected (enabled)
and the direction of the data flow is determined by the
OlEN input.
01,
DB,
DO,
The OlEN input controls the direction of data flow (see
Figure 1) for complete truth table. This direction control
is accomplished by forcing one of the pair of buffers into its
high impedance state and allowing the other to transmit its
data. A simple two gate circuit is used for this function.
The 8216/8226 is a device that will reduce component count
in microcomputer systems and at the same time enhance
noise immunity to assure reliable, high performance operation.
01,
DB,
DO,
L.....---+......----ocs
OlEN 0 - -.....- - - - - '
(b) 8226
OlEN
cs
~
1
0
0
~.- r-2-1
1
01
DB
=>
~
DB
DO
} HIGH IMPEDANCE
Figure 1. 821618226 Logic Diagrams
12-39
8216/8226, 3216/3226
APPLICATIONS OF THE 8216/8226
8080 Data Bus Buffer
The 8080 CPU Data Bus is capable of driving a single TTL
load and is more than adequate for small, single board systems. When expanding such a system to more than one board
to increase I/O or Memory size, it is necessary to provide a
'buffer. The 8216/8226 is a device that is exactly fitted to
th is application.
The 8216/8226 can be used in a wide variety of other buffering functions in microcomputer systems such as Address
Bus Drivers, Drivers to peripheral devices such as printers,
and as Drivers for long length cables to other peripherals or
systems.
Shown in Figure 2 are a pair of 8216/8226 connected directly to the 8080 Data Bus and associated control signals.
The buffer is bi-directional in nature and serves to isolate the
CPU data bus.
BUSEN
15
4 01 OlEN
On the system side, the DB lines interface with standard
semiconductor I/O and Memory components and are completely TTL compatible. The DB lines also provide a high
drive capability (SOmA) so that an extremely large system
can be dirven along with possible bus termination networks.
Do
DB
2 DO
DBo
7
0,
O2
DB,
5
8216
8226
10
11
12
0,
On the 8080 side the D I and DO lines are tied together and
are directly connected to the 8080 Data Bus for bi-directional
operation. The DO outputs of the 8216/8226 have a high
voltage output capability of 3.65 volts which allows direct
connection to the 8080 whose minimum input voltage is
3.3 volts. It also gives a very adequate noise margin of
350mV (worst case).
DB2
13
14
DB,
cs
SYSTEM
DATA
BUS
8080
15
01 OlEN
D.
DB
DO
DB,
os,
0,
8216
8226
The D IEN inputs to 8216/8226 is connected directly to the
8080. DIEN is tied to DBIN so that proper bus flow is
maintained, and CS is tied to BUSEN so that the system
side Data Bus will be 3-stated when a Hold request has been
acknowledged during a DMA activity.
Os
11
12
0,
10
DBs
13
14
DB,
CS
Memory and 1/0 Interface to a Bidirectional Bus
In large microcomputer systems it is often necessary to provide Memory and I/O with their own buffers and at the same
time maintain a direct, common interface to a bi-directional
Data Bus. The 8216/8226 has separated data in and data
out lines on one side and a common bi-directional set on the
other to accomodate such a function.
Figure 2. 8080 Data Bus Buffer
Shown in Figure 3 is an example of how the 8216/8226 is
used in this type of application.
I
MEMORY
The interface to Memory is simple and direct. The memories
used are typically Intel® 8102, 8102A, 8101 or 8107B-4 and
have separate data inputs and outputs. The D I and DO lines
of the 8216/8226 tie to them directly and under control of
the MEMR signal, which is connected to the DIEN input,
an interface to the bi-directional Data Bus is maintained.
The interface to I/O is similar to Memory. The I/O devices
used are typically Intel® 8255s, and can be used for both
input and output ports. The I/O R signal is connected directly to the D IEN input so that proper data flow from the
I/O device to the Data Bus is maintained.
Figure 3. Memo!}, and I/O Interface
to a Bidirectional Bus
12-40
I/O
8216/8226, 3216/3226
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . . . . O°C to 70°C
Storage Temperature .......... .. -65°C to +150°C
All Output and Supply Voltages. . . . . ..
-0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . .. 125 mA
D.C. AND OPERATING CHARACTERISTICS
Limits
Typ.
Max.
Unit
Input Load Current OlEN, CS
-0.15
-.5
mA
VF = 0.45
IF2
I nput Load Cu rrent All Other Inputs
-0.08
-.25
mA
VF =0.45
IRI
Input Leakage Current OlEN, CS
80
/lA
VR =5.25V
IR2
Input Leakage Current 01 Inputs
40
/lA
VR =5.25V
Ve
Input Forward Voltage Clamp
-1
V
le=-5mA
VIL
Input "Low" Voltage
.95
V
20
100
/lA
Symbol
IFI
Parameter
VIH
Input "High" Voltage
1101
Output Leakage Current
(3-State)
Icc
Power Supply Current
Min.
2.0
Conditions
V
DO
DB
Vo = 0.45V /5.25V
8216
95
130
mA
8226
85
120
mA
0.3
.45
V
8216
0.5
.6
V
DB Outputs IOL=55mA
8226
0.5
.6
V
DB Outputs 10L=50mA
DO Outputs IOL=15mA
DB Outputs 10L =25mA
VOL1
Output "Low" Voltage
VOL2
Output "Low" Voltage
VOHI
Output "High" Voltage
3.65
4.0
V
DO Outputs 10H = -1mA
VOH2
Output "High" Voltage
2.4
3.0
V
DB Outputs 10H = -10mA
los
Output Short Circuit Current
-15
-30
-35
-75
NOTE: Typical values are for TA = 25° e, Vee = 5.0V.
12-41
-65
-120
mA
mA
DO Outputs Voii!!!.OV,
DB Outputs Vee=5.0V
8216/8226, 3216/3226
WAVEFORMS
A.C. CHARACTERISTICS
TA = O°C to +70°C, Vcc = +,)1/ ±5%
Symbol
Limits
Typ.ll1
Max.
Unit
Tp01
Input to Output Delay DO Outputs
15
25
ns
CL=30pF,R,=300n
R2=600n
Tp02
Input to Output Delay DB Outputs
8216
Parameter
---
Min.
Conditions
19
30
ns
CL=300pF,R1=90n
8226
16
25
ns
R2 = 180n
8216
42
65
ns
(Note 2)
8226
36
54
ns
(Note 3)
16
35
ns
(Note 4)
Output Enable Time
TE
Output Disable Time
To
Test Load Circuit
Test Conditions:
Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
Output loading is 5 mA and 10 pF.
Speed measurements are made at 1.5 volt levels.
OUT
0---1--------1
CAPACITANCEIS)
Max.
Unit
Input Capacitance
4
8
pF
COUT1
Output Capacitance
6
10
pF
COUT2
Output Capacitance
13
18
pF
Parameter
Test Conditions
NOTES:
Min.
Limits
Typ.ll1
CIN
Symbol
1.
2.
3.
4.
5.
VBIAS = 2.5V, VCC = 5.0V, TA '" 25°C, f = 1 MHz_
Typical values are for TA = 25°C, VCC = 5_0V.
DO Outputs, CL = 30pF, Rl = 300/10 KG, R2 = 180/1 Kil; DB Outputs, CL = 300pF, Rl = 90/10 KG, R2 = 180/1 Kil.
DO Outputs, CL = 30pF, Rl = 300/10 Kil, R2 = 600/1 K; DB Outputs, CL =30OpF, Rl =90/10 Kil, R2 = 180/1 Kil.
DO Outputs, CL = 5pF. R1 = 300/10 Kil, R2 = 600/1 Kil; DB Outputs, CL = 5pF, R, = 90/10 Kil, R2 = 180/1 Kn.
This parameter is periodically sampled and not 100% tested.
12·42
inter
M8216/M3216*
4·BIT PARALLEL BIDIRECTIONAL BUS DRIVER
• 3.40V Output High Voltage for Direct
Interface to 8080 CPU
• Data Bus Buffer Driver for 8080 CPU
• Low Input Load Current: 0.25 rnA
Maximum
• 3·State Outputs
• High Output Drive Capability for
Driving System Data Bus
• Full Military Temperature Range
- 55°C to + 125°C
• 16·Pin Dual In·Line Package
• ± 10% Power Supply Tolerance
The M8216 is a 4-bit bidirectional bus driver/receiver. All inputs are low power TTL compatible. For driving MOS, the
DO outputs provide a high 3.40V VOH , and for high capaCitance terminated bus structures, the DB outputs provide a
high 50 mA IOL capability. The M8216 is used to meet a wide variety of applications for buffering in microcomputer
systems.
"Note: The specifications for the M3216 are identical with those for the M8216.
LOGIC DIAGRAM
PIN CONFIGURATION
8216
cs
Vee
0°0
DIEN
DBo
DO,
~----oDBO
010
DB,
DO,
01,
DB,
DO,
01,
DB,
3ND
01,
000
0---+--< ~-+_...J
01,
o---+--D........--+--~
DO,
0---+--< .......--+_...J
01,
o---+-.. . n ........-+--,
DO,
0---4--< .......~_.....J
~---o DB,
........- - - 0 DB,
PIN NAMES
01, o---4--f~_-+--,
........- - - 0 DB,
DO,
0---4---< ~-+_...J
L......---+.........- - - - o CS
~ __~_~C~HI~PS~E~lE~CT~___
01 EN
12-43
o - _........_ _ _ _---l
M8216/M3216
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............ -55°C to +125°C
Storage Temperatu re .. . . . . . . . . . .. - 65·C to + 160·C
All Output and Supply Voltages ......... -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . • . . . . . . . . . . . . .. 125 rnA
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress· rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
D.C. AND OPERATING CHARACTERISTICS
Symbol
Parameter
Min.
Limits
Typ.
Max.
Unit
IF1
Input Load Current DIEN, CS
-0.15
-.5
mA
VF ; 0.45
Conditions
IF2
Input Load Current All Other Inputs
-0.08
-.25
mA
VF ; 0.45
IR1
Input Leakage Current DIEN, CS
80
IlA
VR; 5.5V
IR2
Input Leakage Current DI Inputs
40
Il A
VR ; 5.5V
Ve
Input Forward Voltage Clamp
-1.2
V
Ie; -5mA
VIL
Input "Low" Voltage
.95
V
Vee; 5V
VIH
Input "High" Voltage
V
Vee; 5V
1101
Output Leakage Current
(3-Statel
2.0
DO
DB
20
100
IlA
Vo ; .45V to Vee
Power Supply Current
95
130
mA
VOL1
Output "Low" Voltage.
0.3
.45
V
VOL2
Output "Low" Voltage
0.5
.6
V
DB Outputs 10 L; 45 rnA
VOH1
Output "High" Voltage
3.4
3.8
V
DO Outputs 10H ; -.5mA
VO H2
Output "High" Voltage
2.4
3.0
V
DO Outputs IOH ; -2mA
DB Outputs 10H ; -5.0mA
los
Output Short Circuit Current
-15
-30
-35
-75
lee
NOTE: Typical values are for TA = 25°e, Vee =5.0V.
12-44
-65
-120
mA
mA
DO Outputs IOL;15mA
DB Outputs 10L ;25mA
DO Outputs Vee; 5.0V
DB Outputs Vee; 5.0V
M8216/M3216
WAVEFORMS
INPUTS
OUTPUT
ENABLE
~to-I
y
OH
V
t
15vJ\'---~~
OUTPUTS
VOL
.5V
A.C. CHARACTERISTICS
TA = -55°C to +125°C, vcc =+5V ±10%
Symbol
---
Parameter
Limits
Typ.ll]
Max.
Unit
TpDl
Input to Output Delay DO Outputs
15
25
ns
(NOTE 2)
TpD2
Input to Output Delay DB Outputs
19
33
ns
(NOTE 2)
TE
Output Enable Time
42
TD
Output Disable Time
16
Min.
I
I
I
I
Conditions
I
75
ns
(NOTE 2)
40
ns
(NOTE 2)
Test Load Circuit
Test Conditions
Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
OUT~------'-------'
CAPACITANCE
Symbol
Parameter
Min.
Input Capacitance
limits
Typ.ll]
Max.
Unit
4
6
pF
CIN
COUT1
Output Capacitance
DO Outputs
6
10
pF
CO UT2
Output Capacitance
DB Outputs
13
18
pF
Test Conditions:
NOTES:
VBIAS = 2.5V, vee = 5.0V, TA = 25°C, f = 1 MHz.
1. Typical values are for TA
2.
TEST
TpD1
TpD2
T E, (DO, ENABLEt)
TE, (DO, ENABLEt)
T E, (DB, ENABLEt)
TE, (DB, ENABLEti
To. (DO, DISABLEt)
To, (DO. DISABLEt)
To, (DB, DISABLEt)
To, (OB, DISABLEt)
= 25°e, Vee = 5.0V.
cL
R,
R2
30pF
300pF
30pF
30pF
300pF
300pF
300n
90n
10Kn
300n
10Kn
90n
600n
180n
1 Kn
600n
1 Kn
180n
5pF
5pF
5pF
5pF
300n
10Kn
90n
10Kn
600n
1 Kn
180n
1 Kn
12-45
inter
a~ij,~
• Synchronous and Asynchronous
Operation
• Error Detection Framing
Parity, Overrun
• Synchronous - 5·8 Bit Characters;
Internal or External Character Synchronization; Automatic Sync Insertion
• Fully Compatible with 8080/8085 CPU
• Asynchronous - 5-8 Bit Characters;
Clock Rate - 1, 16, or 64 Times Baud
Rate; Break Character Generation; 1,
1112, or 2-Stop Bits; False Start Bit
Detection; Automatic Break Detect
and Handling
• 28-Pin DIP Package
• Baud Rate -
• Single
• All Inputs and Outputs are TTL
Compatible
DC to 64K Baud
• Full Duplex, Double Buffered, Transmitter and Receiver
+ 5V Supply
• Single TTL Clock
The Intel® 8251A is the enhanced version of the industry standard, Intel® 8251 Universal Synchronous/Asynchronous
Receiver/Transmitter (USART), designed for data communications with Intel's new high performance family of
microprocessors such as the 8085. The 8251 A is used as a peripheral device and is programmed by the CPU to operate
using virtually any serial data transmission technique presently in use (including IBM "bi·sync"). The USART accepts
data characters from the CPU in parallel format and then converts them into a continuous serial data stream for
transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the
CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has
received a character for the CPU. The CPU can read the complete status of the USART at any time. These include data
transmission errors and control signals such as SYNDET, TxEMPTY. The chip is constructed using N·channel silicon
gate technology.
PIN CONFIGURATION
0,
BLOCK DIAGRAM
0,
D,
0"
RxD
Vcr
GND
Rxe
D,
DTR
D"
RTS
[\
DSR
A~
D; [)~N
'"
DATA
BUS
BUFFEH
elK
WR
hD
es
elK
CD_
RD
WR
CTS
-
-- READ/WRITE
CONTROL
LOGIC
TxRDY
R"RDY
,,--
T~()
~hRDY
THANSMIT
CONTROL
I
CS _ _
I
_
__ --
1"
SYNDE1/BD
RD
·_
(P ·51
I
RESET
TxEMPTY
C/o
I
.•~ ~T
TRANSMIT
BUFFER
I
R[Sl T
0,
f;C
h.ltJ
r~
T~E
T~C
I
I
I
0, Do
CIO
AD
WA
CS
eLK
Data Bus (8 nl\s)
OSR
Data Set Ready
DTR
Data Terminal Ready
SYND[T/BD
Sync Detect/
Break Detect
RESET
Reset
hl
R;c
Transmitter Clock
Transmitter Oiltd
Receiver Clock
RxD
Receiver D,lta
T)lO
DTR ____
Control or Dilta IS to be Written or Hedd
Read oill,l Cor;Hnand
Write Oatd or Control
ChiD Enable
Clock Pulse (TTL)
COtlUl1dlld
R-i-s
CTS
RxRDY
Recc,\'er Reddy (has Chdrilcter for 80801
TxRDY
Transmitter Ready (ready lor chdr /rom 808011
I
OSR_
PIN NAMES
CTS ____ ,
MODEM
CONTROL
HECf IVE
BUFF [H
is Po
·
HlU IVl
CONTHOL
·
RdJ
RTS
Request to Send Data
Clear to Send Data
T,E
Transmitter Empty
Vee
+5 Volt Supply
GND
Ground
_H~H(lY
fhC
._SYN()(T
I
© Intel CorpDration, 1978
12-46
8251 AFEATURES AND ENHANCEMENTS
• Tx Enable logic enhancement' prevents a
Tx Disable command from halting trans·
mission until all data previously written has
been transmitted. The logic also prevents
the transmitter from turning off in the middle
of a word.
8251 A is an advanced design of the industry stan·
dard USART, the Intel® 8251. The 8251A oper·
ates with an extended range of Intel micropro·
cessors that includes the new 8085 CPU and main·
tains compatibility with the 8251. Familiarization
time is minimal because of compatibility and
involves only knowing the additional features and
enhancements, and reviewing the AC and DC speci·
fications of the 8251A.
• When External Sync Detect is programmed,
Internal Sync Detect is disabled, and an Ex·
ternal Sync Detect status is provided via a
flip·flop which clears itself upon a status read.
• Possibility of false sync detect is minimized
by ensuring that if double character sync is
programmed, the characters be contiguously
detected and also by clearing the Rx register
to all ones whenever Enter Hunt command is
issued in Sync mode.
The 8251A incorporates all the key features of
the 8251 and has the following additional features
and enhancements:
• 8251A has double·buffered data paths with
separate I/O registers for control, status,
Data In, and Data Out, which considerably
simplifies control programming and mini·
mizes CPU overhead.
• As long as the 8251A is not selected, the
RD and WR do not affect the internal opera·
tion of the device.
• In asynchronous operations, the Receiver
detects and handles "break" automatically,
relieving the CPU of this task.
• The 8251A Status can be read at any time
but the status update will be inhibited during
status read.
• A refined Rx initialization prevents the
Receiver from starting when in "break"
state, preventing unwanted interrupts from
a disconnected USART.
• The 8251A is free from extraneous glitches
and has enhanced AC and DC characteristics,
providing higher speed and better operating
margins.
• At the conclusion of a transmission, TxD
line will always return to the marking state
unless SBRK is programmed.
• Baud rate from DC to 64K.
• Fully compatible with Intel's new industry
standard, the MCS·85.
12·47
8251A
8251A BASIC FUNCTIONAL DESCRIPTION
C/O (Control/Data)
This input, in conjunction with the WR and RD inputs,
informs the ,8251A that the word on the Data Bus is either
a data character, control word or status information.
1 = CONTROL/STATUS 0 = DATA
General
The 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitter designed specifically for the 80/85 Microcomputer Systems. like other I/O devices in a Microcomputer System, its functional configuration is programmed
by the system's software for maximum flexibility. The
8251A can support virtually any serial data technique currently in use (including IBM "bi-sync").
CS (Chip Select)
A "low" on this input selects the 8251 A. No reading or
writing will occur unless the device is selected. When CS is
high, the Data Bus in the float state and RD and WFi will
have no effect on the chip.
In a communication environment an interface device must
convert parallel format system data into serial format for
transmission and convert incoming serial format data into
parallel system data for reception. The interface device must
also delete or insert bits or characters that are functionally
unique to the communication technique. In essence, the
interface should appear "transparent" to the CPU, a simple
input or output of byte-oriented system data.
Data Bus Buffer
This 3-state, bidirectional, 8-bit buffer is used to interface
the 8251 A to the system Data Bus. Data is transmitted or
received by the buffer upon execution of INput or OUTput
instructions of the CPU. Cnntrol words, Command words
and Status information are also transferred through the
Data Bus Buffer. The command status and data in, and
data out are separate 8-bit registers to provide double
buffering.
This functional block accepts inputs from the system Control bus and generates control signals for overall device
operation. It contains the Control Word Register and Command Word Register that store the various control formats
for the device functional definition.
RESET (Reset)
A "high" on this input forces the 8251A into an "Idle"
mode. The device will remain at "Idle" until a new set of
control words is written into the 8251A to program its
functional definition. Minimum R E'SET pulse width is
6 tCY (clock must be running).
Figure 1_ 8251A Block Diagram Showing Data Bus
Buffer and Read/Write Logic Functions
CLK (Clock)
I
The CLK input is used to generate internal device timing
and is normally connected to the Phase 2 (TTL) output of
the 8224 Clock Generator. No external inputs or outputs
are referenced to CLK but the frequency of ClK must be
greater than 30 times the Receiver or Transmitter data
bit rates.
c/o
RD
WR
CS
0
0
0
1
0
1
0
0
0
0
0
0
0
X
X
X
X
=
8251A DATA
DATA BUS
DATA BUS = 8251A DATA
STATUS DATA BUS
DATA BUS= CONTROL
DATA BUS = 3-STATE
DATA BUS= 3-STATE
=
WR (Write)
A "low" on this input informs the 8251A that the CPU is
writing data or control words to the 8251A.
Modem Control
The 8251A has a set of control inputs and outputs that can
be used to simplify the interface to almost any Modem. The
Modem control signals are general purpose in nature and
can be used for functions other than Modem control, if
necessary.
RD (Read)
A "low" on this input informs the 8251A that the CPU is
reading data or status information from the 8251A.
12-48
8251A
DSR (Data Set Ready)
TxE (Transmitter Empty)
The DSR input signal is a general purpose, l-bit inverting
input port. Its condition can be tested by the CPU using a
Status Read operation. The DSR input is normally used to
test Modem conditions such as Data Set Ready.
When the 8251A has no characters to transmit, the TxEMPTY output will go "high". It resets automatically upon njceiving a character from the CPU. TxEMPTY can be used to
indicate the end of a transmission mode, so that the CPU
"knows" when to "turn the line around" in the half·
duplexed operational mode. TxEMPTY is independent of
the Tx Enable bit in the Command instruction.
DTR (Data Terminal Ready) I
The DTR output signal is a general purpose, l-bit inverting
output port. It can be set "low" by programming the appropriate bit in the Command Instruction word. The DTR
output signal is normally used for Modem control such as
Data Terminal Ready or Rate Select.
In SYNChronous mode, a "high" on this output indicates
that a character has not been loaded and the SYNC charac·
ter or characters are about to be or are being transmitted
automatically as "fillers". TxEMPTY does not go low
when the SYNC characters are being shifted out.
RTS (Request to Send)
The RTS output signal is a general purpose, l-bit inverting
output port. It can be set "low" by programming the appropriate bit in the Command Instruction word. The RfS
output signal is normally used for Modem control such as
Request to Send.
CTS (Clear to Send)
A "low" on this input enables the 8251A to transmit
serial data if the Tx Enable bit in the Command byte is
set to a "one." If either a Tx Enable off or CTS off condition occurs while the Tx is in operation, the Tx will
transmit all the data in the USART, written prior to Tx
Disable command before shutting down.
Transmitter Buffer
The Transmitter Buffer accepts parallel data from the Data
Bus Buffer, converts it to a serial bit stream, inserts the
appropriate characters or bits (based on the communication technique) and outputs a composite serial stream of
data on the TxD output pin on the falling edge of TxC.
The transmitter will begin transmission upon being enabled
if CTS ; O. The TxD line will be held in the marking
state immediately upon a master Reset or when Tx Enable/
CTS off or TxEMPTY.
Figure 2. 8251A Block Diagram Showing Modem and
Transmitter Buffer and Control Functions
Transmitter Control
The transmitter Control manages all activities associated
with the transmission of serial data. It accepts and issues
signals both externally and internally to accomplish this
function.
TxC (Transmitter Clock)
TxRDY (Transmitter Ready)
This output signals the CPU that the transmitter is ready to
accept a data character. The TxRDY output pin can be
used as an interrupt to the system, since it is masked by
Tx Disabled, or, for Polled operation, the CPU can check
TxRDY using a Status Read operation. TxRDY is automatically reset by the leading edge of WR when a data
character is loaded from the CPU.
Note that when using the Polled operation, the TxRDY
status bit is not masked by Tx Enabled, but will only
indicate the Empty/Full Status of the Tx Data Input
Register.
The Transmitter Clock controls the rate at which the char·
acter is to be transmitted. In the Synchronous transmission
mode, the Baud Rate (lx) is equal to the TxC frequency.
In Asynchronous transmission mode the baud rate is a
fraction of the actual TxC frequency. A portion of the
mode instruction selects th is factor; it can be 1, 1/16 or
1/64 the T xC.
For Example:
If Baud Rate equals 110 Baud,
TxC equals 110 Hz (lx)
TxC equals 1.76 kHz (16x)
TxC equals 7.04 kHz (64x).
The falling edge of TxC shifts the serial data out of the
8251A.
12·49
8251A
Receiver Buffer
quency. A portion of the mode instruction selects this
factor; 1, 1/16 or 1/64 the RxC.
The Receiver accepts serial data, converts this serial input
to parallel format, checks for bits or characters that are
unique to the communication technique and sends an
"assembled" character to the CPU. Serial data is input to
RxD pin, and is clocked in on the rising edge of RxC.
For Example:
Baud Rate equals 300 Baud, if
RxC equals 300 Hz (lx)
RxC equals 4800 Hz (16x)
RxC equals 19.2 kHz (64x).
Receiver Control
Baud Rate equals 2400 Baud, if
RxC equals 2400 Hz (1x)
RxC equals 38.4 kHz (16x)
RxC equals 153.6 kHz (64x).
This functional block manages all receiver-related activities
which consist of the following features:
The RxD initialization circuit prevents the 8251A from
mistaking an unused input line for an active low data
line in the "break condition". Before starting to receive
serial characters on the RxD line, a valid "1" must first
be detected after a chip master Reset. Once this has been
determined, a search for a valid low (Start bit) is enabled. This feature is only active in the asynchronous
mode, and is only done once for each master Reset.
The False Start bit detection circuit prevents false starts
due to a transient noise spike by first detecting the failing edge and then strobing the nominal center of the
Start bit (RxD = low).
The Parity Toggle F IF and Parity Error F IF circuits are
used for parity error detection and set the corresponding
status bit.
The Framing Error Flag FIF is set if the Stop bit is
absent at the end of the data byte (asynchronous mode),
and also sets the corresponding status bit.
RxRDY (Receiver Ready)
This output indicates that the 8251A contains a character
that is ready to be input to the CPU. Rx RDY can be connected to the interrupt structure of the CPU or, for Polled
operation, the CPU can check the condition of RxRDY
using a Status Read operation.
Data is sampled into the 8251A on the rising edge of RxC.
NOTE: In most communications systems, the 8251A will
be handling both the transmission and reception operations
of a single link. Consequently, the Receive and Transmit
Baud Rates will be the same. Both TxC and RXC will require identical frequencies for this operation and can be
tied together and connected to a single frequency source
(Baud Rate Generator) to simplify the interface.
SYNDET (SYNC Detect)/BRKDET (Break Detect»
This pin is used in SYNChronous Mode for SYNDET and
may be used as either input or output, programmable
through the Control Word. It is reset to output mode low
upon RESET. When used as an output (internal Sync mode),
the SYNDET pin will go "high" to indicate that the 8251A
has located the SYNC character in the Receive mode. If the
8251 A is programmed to use double Sync characters (bi·
sync), then SYNDET will go "high" in the middle of the
last bit of the second Sync character. SYNDET is automatically reset upon a Status Read operation.
Rx Enable off both masks and holds RxRDY in the Reset
Condition. For Asynchronous mode, to set RxRDY, the
Receiver must be Enabled to sense a Start Bit and a complete character must be assembled and transferred to the
Data Output Register. For Synchronous mode, to set
RxRDY, the Receiver must be enabled and a character
must finish assembly and be transferred to the Data Output
Register.
Failure to read the received character from the Rx Data
Output Register prior to the assembly of the next Rx Data
character will set overrun condition error and the previous
character will be written over and lost. If the Rx Data is
being read by the CPU when the internal transfer is occurring, overrun error will be set and the old character will be
lost.
RxC (Receiver Clock)
The Receiver Clock controls the rate at which the character
is to be received. In Synchronous Mode, the Baud Rate (lx)
is equal to the actual frequency of RxC. In Asynchronous
Mode, the Baud Rate is a fraction of the actual RxC fre-
Figure 3. 8251A Block Diagram Showing Receiver
Buffer and Control Functions
12·50
8251A
When used as an input (external SYNC detect model. a
positive going signal will cause the 8251A to start assembling data characters on the rising edge of the next RxC.
Once in SYNC, the "high" input signal can be removed.
the period of RxC. When External SYNC Detect is programmed, the Internal SYNC Detect is disabled.
The 8251A cannot begin transmission until the Tx Enable
(Transmitter Enable) bit is set in the Command Instruction
and it has received a Clear To Send (CTS) input. The TxD
output will be held in the marking state upon Reset.
Programming the 8251A
Prior to starting data transmission or reception, the 8251 A
must be loaded with a set of control words generated by
the CPU. These control signals define the complete functional definition of the 8251A and must immediately folIowa Reset operation (internal or external).
BREAK DETECT (Async Mode Only)
This output will go high whenever an all zero word of the
programmed length (including start bit, data bit, parity bit,
and one stop bit) is received. Break Detect may also be read
as a Status bit. It is reset only upon a master chip Reset or
Rx Data returning to a "one" state.
The control words are split into two formats:
1. Mode Instruction
2. Command Instruction
Mode Instruction
~L_____A_Orl__- .____A_D_D_RES_S_B_US_______________~
CONTROL BUS
I/O R
\
0,
110 W RESET
\
(TTL)
\
DATA BUS
7
CS
Command Instruction
This format defines a status word that is used to control the
actual operation of the 8251 A.
8
C/D
This format defines the general operational characteristics
of the 8251 A. It must follow a Reset operation (internal or
external). Once the Mode Instruction has been written into
the 8251 A by the CPU, SYNC characters or Command Instructions may be inserted.
°7-0 0
RD
WR
RESET
elK
8251A
Figure 4. 8251A Interface to 8080 Standard
System Bus
DETAILED OPERATION DESCRIPTION
General
The complete functional definition of the 8251 A is programmed by the system's software. A set of control words
must be sent out by the CPU to initialize the 8251A to
support the desired communications format. These control
words will program the: BAUD RATE, CHARACTER
LENGTH, NUMBER OF STOP BITS, SYNCHRONOUS or
ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc. In the Synchronous Mode, options are also provided to select either internal or external character synchronization.
Once programmed, the 8251A is ready to perform its communication functions. The TxRDY output is raised "high"
to signal the CPU that the 8251A is ready to receive a data
character from the CPU. This output (TxRDY) is reset
automatically when the CPU writes a character into the
8251A. On the other hand, the 8251A receives serial data
from the MODEM or I/O device. Upon receiving an entire
character, the RxRDY output is raised "high" to signal the
CPU that the 8251 A has a complete character ready for the
CPU to fetch. RxRDY is reset automatically upon the CPU
data read operation.
Both the Mode and Command Instructions must conform
to a specified sequence for proper device operation. The
Mode Instruction must be inserted immediately following a
Reset operation, prior to using the 8251A for data communication.
All control words written into the 8251A after the Mode Instruction will load the Command Instruction. Command
Instructions can be written into the 8251A at any time in
the data block during the operation of the 8251A. To return to the Mode Instruction format, the master Reset bit
in the Command Instruction word can be set to initiate an
internal Reset operation which automatically places the
8251A back into the Mode Instruction format. Command
Instructions must follow the Mode Instructions or Sync
characters.
C/O" 1
c/o
=
1
MODE INSTRUCTION
SYNC CHARACTER 1
~------
C/O" 1
SYNC CHARACTER 2
C/O" 1
COMMAND INSTRUCTION
}
.
SYNC MODE
ONLY·
DA
* The second SYNC character is skipped if MODE instruction
has programmed the 8251A to single character Internal SYNC
Mode. Both SYNC characters are skipped if MODE instruction
has programmed the 8251A to ASYNC mode.
Figure 5. Typical Data Block
12·51
8251A
Mode Instruction Definition
I
The 8251A can be used for either Asynchronous or Synchronous data communication. To understand how the
Mode Instruction defines the functional operation of the
8251 A, the designer can best view the device as two separate components sharing the same package, one Asynchronous the other Synchronous. The format definition can be
changed only after a master chip Reset. For explanation
purposes the two formats will be isolated.
s, \ s,
j I I
EP
PEN
L,\ L, \ . ' \ .,
I
~
BAUD RATE FACTOR
,
0
0
,
,
(64XI
0
0
,
SYNC
MODE
('XI
('6XI
CHARACTER LENGTH
NOTE: When parity is enabled it is not considered as one of
the data bits for the purpose of programming the word
length. The actual parity bit received on the Rx Data line
cannot be read on the Data Bus. In the case of a programmed character length of less than 8 bits, the least
significant Data Bus bits will hold the data; unused bits are
"don't care" when writing data to the 8251A, and will be
"zeros" when reading the data from the 8251A.
0
,
0
0
,
0
,
,
5
6
7
BITS
BITS
BITS
8
BITS
PARITY ENABLE
1 = ENABLE
0'" DISABLE
EVEN PARITY GENERATION/CHE CK
0-000
1 = E'~/EN
,
,
, ,
,
NUMBER OF STOP BITS
0
0
0
0
INVALID
,~
BIT
BITS
2
81TS
(ONLY EFFECTS Tx; Rx NEVER
REOUIRES MORE THAN ONE
STOP BIT!
Asynchronous Mode (Transmission)
Whenever a data character is sent by the CPU the 8251A
automatically adds a Start bit (fow level) followed by the
data bits (least significant bit first), and the programmed
number of Stop bits to each character. Also, an even or
odd Parity bit is inserted prior to the Stop bit(s), as defined by the Mode Instruction. The character is then transmitted as a serial data stream on the TxD output. The serial
data is shifted out on the falling edge of TxC at a rate equal
to 1, 1/16, or 1/64 that of the TxC, as defined by the Mode
Instruction. BREAK characters can be continuously sent to
the TxD if commanded to do so.
When no data characters have been loaded into the 8251A
the TxD output remains "high" (marking) unless a Break
(continuously low) has been programmed.
Figure 6. Mode Instruction Format, Asynchronous
Mode
GENERATED
DO 01---- Ox
BY 8251A
srtp]
srTs
DO 01----0x ON THE DATA BUS
RECEIVER INPUT
t
t
t
RxD
sr6.1
arTS
Asynchronous Mode (Receive)
PROGRAMMED
The RxD line is normally high. A falling edge on this line
triggers the beginning of a START bit. The validity of this
START bit is checked by again strobing this bit at its nominal center (16X or 64X mode only). If a low is detected
again, it is a valid START bit, and the bit counter will
start counting. The bit counter thus locates the center of
the data bits, the parity bit (if it exists) and the stop bits.
If parity error occurs, the parity error flag is set. Data and
parity bits are sampled on the RxD pin with the rising edge
of RxC. If a low level is detected as the STOP bit, the
Framing Error flag will be set. The STOP bit signals the end
of a character. Note that the receiver requires only one stop
bit, regardless of the number of stop bits programmed. This
character is then loaded into the parallel I/O buffer of the
8251A. The RxRDY pin is raised to signal the CPU that a
character is ready to be fetched. If a previous character has
not been fetched by the CPU, the present character replaces
it in the I/O buffer, and the OVERRUN Error flag is raised
(thus the previous character is lost). All of the error flags
can be reset by an Error Reset Instruction. The occurrence
of any of these errors will not affect the operation of the
8251A.
12-52
L
DOES NOT APPEAR
CHARACTER
LENGTH
TRANSMISSION FORMAT
CPU BYTE (5·8 BITS/CHAR)
IS
DATA CH~RACTER
ASSEMBLED SERIAL DATA OUTPUT (TxO)
STOt;'l
~",,----,,--_D_A_T_A-iCHA...R_A_C_TE_R_.....L""';;;";""""'_"i.ITW
RECEIVE FORMAT
SERIAL DATA INPUT (AxO)
DATA CHARACTER
STOO
BITS
1----'----'----1
CPU BYTE (5·8 BITS/CHAR)*
...-----I~
"'1- - - ,
DATA CHARACTER
L-._ _--II 1-1- - - - '
*NOTE: IF CHARACTER LENGTH IS DEFINED AS 5, 6 OR 7
BITS THE UNUSED BITS ARE SET TO "ZERO"
Figure 7. Asynchronous Mode
L
8251A
Synchronous Mode (Transmission)
the SYNDET F/F is reset at each Status Read, regardless of
whether internal or external SYNC has been programmed.
This does not cause the 8251A to return to the HUNT
mode. When in SYNC mode, but not in HUNT, Sync Detection is still functional, but only occurs at the "known"
word boundaries. Thus, if one Status Read indicates SYN·
DET and a second Status Read also indicates SYNDET,
then the programmed SYNDET characters have been received since the previous Status Read. (If double character
sync has been programmed, then both sync characters have
been contiguously received to gate a SYNDET indication.)
When external SYNDET mode is selected, internal Sync
Detect is disabled, and the SYNDET F/F may be set at
any bit boundary.
The TxD output is continuously high until the CPU sends
its first character to the 8251 A which usually is a'SYNC
character. When the CTS line goes low, the first character
is serially transmitted out. All characters are shifted out on
the falling edge of TxC. Data is shifted out at the same
rate as the TxC.
Once transmission has started, the data stream at the TxD
output must continue at the TxC rate. If the CPU does not
provide the 8251A with a data character before the 8251A
Transmitter Buffers become empty, the SYNC characters
(or character if in single SYNC character mode) will be
automatically inserted in the TxD data.stream. In this case,
the TxEMPTY pin is raised high to signal that the 8251 A is
empty and SYNC chara~ers are being sent out. TxEMPTY
does not go low when the SYNC is being shifted out (see
figure below). The TxE~PTY pin is internally reset by a
data character being written into the 8251 A.
I I I I I
scs
ESD
EP
PEN
L21 L,
AUTOMATICALLY INSERTED BY USART
TxD
T.EMPTY
I
DATA
I
I \
1DATA 1SYNC 1 1SYNC 21
./
-~"
DATA
1- - - - -
I I I
0
0
L_
CHARACTER LENGTH
0
1
0
0
,
1
0
5
BITS
6
7
BITS
BITS
8
BITS
,
" \ \ \ \ \ \ \ FALLS UPON CPU WRITING A
'-_ _ _ _ _ /CHARACTERTOTHEUSART
PARITY ENABLE
(' = ENABLE I
(0 = DISABLE)
NOMINAL CENTER OF LAST BIT
Synchronous Mode (Receive)
EVEN PARITY GENERATION/CHEe
, = EVEN
In this mode, character synchronization can be internally
or externally achieved. If the SYNC mode has been programmed, ENTER HUNT command should be included in
the first command instruction word written. Data on the
RxD pin is then sampled in on the rising edge of RxC. The
content of the Rx buffer is compared at every bit boundary
with the first SYNC character until a match occurs. If the
8251A has been programmed for two SYNC characters, the
subsequent received character is also compared; when both
SYNC characters have been detected, the ,USART ends the
HUNT mode and is in character synchronization. The
SYNDET pin is then set high, and is reset automatically by
a STATUS READ. If parity is programmed, SYNDET
will not be set until the middle of the parity bit instead of
the middle of the last data bit.
In the external SYNC mode, synchronization is achieved by
applying a high level on the SYNDET pin, thus forcing the
8251A out of the HUNT mode. The high level can be
removed after one RxC cycle. An ENTER HUNT command
has no effect in the asynchronous mode of operation.
0"000
EXTERNAL SYNC DETECT
1 = SYNDET IS AN INPUT
o= SYf\lOET IS AN OUTPUT
SINGLE CHARACTER SYNC
1 = SINGLE SYNC CHARACTER
0= DouaLE SYNC CHARACTER
NOTE: IN EXTERNAL SYNC MODE, PROGRAMMING DOUBLE CHARACTER
SYNC WILL AFFECT ONLY THE Tx.
Figure 8. Mode Instruction Format
CPU BYTES (5-8 BITS/CHAR)
DATA
C~~RACTERS
ASSEMBLEO SERIAL DATA OUTPUT (T)(O)
DATA
CHARI-~A-CT-E-RS--'
RECEIVE FORMAT
Parity error and overrun error are both checked in the same
way as in the Asynchronous Rx mode. Parity is checked
when not in Hunt, regardless of whether the Receiver is
enabled or not.
SERIAL DATA INPUT (AxD)
DATA
CHAR~
...C_T_ER_S_ _...
CPU BYTES (5·8 BITS/CHAR)
The CPU can command the receiver to enter the HUNT
mode if synchronization is lost. This will also set all the
used character bits in the buffer to a "one", thus preventing a possible false SYNDET caused by data that happens
to be in the Rx Buffer at ENTER HUNT time. Note that
, DATA
CH~~ACTERS
Figure 9. Data Format, Synchronous Mode
12-53
8251 A
COMMAND rNSTFlUCTION DEFINITION
STATUS READ DEFINITION
Once the functional definitiom of the 8251 A has be~n programmed by the Moc;le Instruction and the Sync Charact~rs
are loaded (if in Sync Mode) then the device is ready to be
used for data communication_ The Command Instruction
controls the actual operation of the selected format. Functions such as: Enable Transmit/Receive, Error Reset and
Modem Controls are provided by the Command Instruction.
In data commuflication systems it is often necessary to
examine, the "status", of the, active device to ascertain if
errors have occurred or other conditions that require the "
processor's attention. The 8251 A has facilities that allow
the programmer to "read" the status of the device at any
time during the functional operation. (The status update is
inhibited during status read).
Once the Mode Instruction has been written into the 8251A
and Sync characters inserted, if necessary, then all further
"control writes" (C/O = 1) will load a Command Instruction. A Reset Operation (internal or external) will return
the 8251 A to the Mode Instruction format.
A normal "read" command is issued by the CPU with
to accomplish this function.
cio = 1
Some of the bits in the Status Read Format have identical
meanings to external output pins so that the 8251 A can be
used in a completely Polled environment or in an interrupt
driven environment. TxRDY is an exception.
Note that status update can have a maximum delay of 28
clock periods from the actual event affecting the status.
0,
I I I I I I
DSR
TRANSMIT ENABLE
1 '" enable
OJ
05
SYNDET
FE
OE
PE
0,
TXEMPTyl RxRDY
1
I
0= dl5CIble
0,
I
TxRDY
1
~
SAME DEFINITIONS AS I/O PINS
DATA TERMINAL
READY
"high" Will force OTR
PARITY ERROR
The PE flag is set when a parity
output to zero
error is detected. It is reset by
the ER bit of the Command
Instruction, PE does not inhibit
operation of the 8251 A.
RECEIVE ENABLE
'----~-I 1 = enable
0= dIsable
SEND BREAK
L.._ _ _ _ _
~_I ~~~:~~sT~:D
"low"
o = normal operation
L--.-
ERROR REseT
L - - - o - - - - - - - . . J 1 = reset BtrOr flags
PE, DE, FE
'----'----------1
'----------------1
OVERRUN ERROR
The DE flag IS set when the CPU
does not read a character before
the next one becomes available.
It is reset by the ER bit of the
Command Instruction. OE does
not inhibit operation of the 8251 A
however, the prevIOusly overrun
character IS lost,
REOUEST TO SEND
"high" Will force RTS
FRAMING ERROR (Async only)
The FE ·flag IS set when a valid
output to zero
Stop bit is not detected at the
end of every character. It is reset
by the E R bit of the Command
Instruction. FE does not Irlhibit
the operation of the 8251 A.
INTERNAL RESET
"high" returns 8251A to
Mode Instruction Format
DATA SET READY: Indicates
that the OSR IS at a zero level.
ENTER HUNT MODE*
1 = enable search for Sync
Characters
* (HAS NO EFFECT
Note 1:
IN ASYNC MODE)
Nota: Error Reset must be performed whenever RxEnable and
Enter Hunt are programmed.
Figure 10. Command Instruction Format
TxRDY stat.us bit has different meanings from the
TxRDY output pirro The former is not conditioned
by CTS and TxEN; the latter is conditioned by both
CTS and TxEN.
i.e. TxRDY status bit = DB Buffer Empty
TxRDY pin out = DB Buffer Empty 'iCTS=O)' iTxEN=1)
Figure 11. Status Read'Format
12-54
8251A
APPLICATIONS OF THE 8251A
ADDRESS BUS
CONTROL BUS
PHONE
DATA BUS
LINE
INTER·
FACE
R,D
8251A
1------1
hDI----
TELEPHONE
LINE
TERMINAL
Figure 12. Asynchronous Serial Interface to CRT
Terminal, DC-9600 Baud
Figure 14. Asynchronous Interface to Telephone Lines
PHONE
LINE
INTER·
SYNC
MODEM
FACE
SYNCHRONOUS
TERMINAL
OR PERIPHERAL
DEVICE
TelEPHONE
LINE
SYNDET
1-----1
Figure 15. Synchronous Interface to Telephone L.ines
Figure 13. Synchronous Interface to Terminal or
Peripheral Device
12·55
8251A
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias . . . . . . . . . o°c to 70°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS
Symbol
Min.
Parameter
Max.
Unit
Test Conditions
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee
V
0.45
V
IOL = 2.2 rnA
V
IOH = -400 !.LA
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
IOFL
Output Float Leakage
±10
JlA
VOUT = Vee TO 0.45V
IlL
I n put Lea kage
±10
!.LA
VIN = Vee TO 0.45V
lee
Power Supply Current
100
mA
All Outputs = High
CAPACITANCE
TA = 25°C; Vee = GND =
Symbol
ov
Parameter
CIN
Input Capacitance
ClIO
I/O Capacitance
Min.
Test Conditions
Max.
Unit
10
pF
fc = lMHz
20
pF
Unmeasured pins returned to GND
'20
g
2V
/
+10
>-
~
"ii'
t-
/
t::>
1N914
..,
0
8251A
\----+---<> OUT
-10
--
6K
-20
-100
/
V
"SPEC.
if
-50
+50
~ CAPAC IT ANCE (pF)
Figure 17. Typical A Output Delay vs. A
Capacitance (pF)
Figure 16. Test Load Circuit
12-56
+100
8251A
A.C. CHARACTERISTICS
Bus Parameters (Note 1)
Read Cycle:
PARAMETER
SYMBOL
MIN.
tAR
Address Stable Before READ (CS, C/D)
tRA
Address Hold Time for READ (CS, C/D)
tRR
READ Pulse Width
tRO
Data Delay from READ
tOF
READ to Data Floating
MAX.
TEST CONDITIONS
UNIT
a
a
ns
Note 2
ns
Note 2
250
ns
10
200
ns
100
ns
MAX.
UNIT
3, CL = 150 pF
Write Cycle:
SYMBOL
PARAMETER
MIN.
a
a
ns
tww
WR ITE Pulse Width
250
ns
tow
Data Set Up Time for WR ITE
150
ns
two
Data Hold Time for WR ITE
a
ns
tRV
Recovery Time Between WRITES
6
tCY
tAW
Address Stable Before WR ITE
tWA
Address Hold Time for WR ITE
TEST CONDITIONS
ns
Note 4
NOTES: 1. AC timings measured VOH = 2.0. VOL = 0.8, and with load circuit of Figure 1.
2. Chip Select ICS) and Command/Data IC/D) are considered as Addresses.
3. Assumes that Address is valid before ROt.
4. This recovery time is for Mode Initialization only, Write Data is allowed only when TxRDY = 1.
Recovery rime between Writes for Asynchronous Mode is 8 tey and for Synchronous Mode is 16 tey.
Input Waveforms for AC Tests
2.4
0.45
----.,X
_ _ _ _....J
:::
TEST
POINTS
12-57
:::x'-____
8251A
Other Timings:
SYMBOL
tCY
1:
1:4)
tR, tF
tOTx
tS'Rx
tHRx
fTx
tTPW
tTPO
fRx
tRPW
tRPO
tTxROY
tTxR OY CLEAR
tRxROY
tRxROY CLEAR
tiS
PARAMETER
MIN.
Clock Period
Clock High Pulse Width
Clock Low Pulse Width
Clock Rise and Fall Time
TxD Delay from Falling Edge of TxC
Rx Data Set-Up Time to Sampling Pulse
Rx Data Hold Time to Sampling Pulse
Transmitter Input Clock Frequency
1x Baud Rate
16x Baud Rate
64x Baud Rate
Transmitter Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
Receiver Input Clock Frequency
1 x Baud Rate
16x Baud Rate
64x Baud Rate
Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
TxRDY Pin Delay from Center of last Bit
TxRDY .j, from Leading Edge of WR
RxRDY Pin Delay from Center of last Bit
RxRDY .j, from Leading Edge of RD
Internal SYNDET Delay from Rising
Edge of RxC
tES
External SYNDET Set-Up Time Before
Falling Edge of RxC
tTxEMPTY
twc
TxEMPTY Delay from Center of Data Bit
Control Delay from Rising Edge of
WRITE (TxEn,DTR, RTS)
Control to READ Set-Up Time (DSR, CTS)
tCR
320
120
90
5
MAX.
1.35
UNIT
TEST CONDITIONS
J.ls
Notes 5, 6
tCY-90
ns
ns
ns
20
1
2
2
DC
DC
DC
J.ls
J.ls
64
310
615
kHz
kHz
kHz
12
1
tCY
tCY
15
3
tCY
tCY
DC
DC
DC
64
310
615
kHz
kHz
kHz
12
1
tCY
tCY
15
3
tCY
tCY
tCY
ns
8
150
24
150
tCY
ns
Note
Note
Note
Note
24
tCY
Note 7
16
tCY
Note 7
20
tCY
tCY
Note 7
8
20
tCY
Note 7
5. The TxC and RxC frequencies have the following limitations with respect to ClK.
For 1x Baud Rate, fTx or fRx .. 1/(30 tCY)
For 16x and 64x Baud Rate, fTx or fRx" 1/(4.5 tCY)
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
12-58
J.ls
7
7
7
7
Note 7
8251A
WAVEFORMS
System Clock Input
CLOCK ¢
Transmitter Clock & Data
TxC (1x MODE)
TiC (16xMODE)
Tx DATA
Receiver Clock & Data
(Rx BAUD COUNTER STARTS HERE)
START BIT
Rx DATA
DATA SIT
Rxe (Tx MODE)
RxC (16 MODE)
INTSAMPLING
PULSE
Write Data Cycle (CPU
TxADY
DATA IN (O.B.)
-+
USART)
_ _ _--'I
_ ______~D~O~N~'T~CA~R~E~__t=~~~~~----~D~O~N2·T~C~A~RE~
c/o
Read Data Cycle (CPU
+-
USARn
---'1
RxRDY _______
~
'il'-l_ _ _ _ _ __
I~XRDYCLEARI
- - - -____________~~
tRR-----~r--------
-lI r--
r
tRD
tDF
DATA OUT (O.B.) _____---'?DA~T~A!.!F:!,LO~A~T~____+-t:§~~~~b-D~A~T"-"'-Ac.':F.':!LO?!A!!.T
c/o
----------------'--+------------t--L------
12-59
DATA SIT
8251A
Write Control or Output Port Cycle (CPU
DATA IN (O.B.)
-+
USART)
---------~=t==!j-------tWA
c/o _ _ _ _ _ _ _ _-J
Read Control or Input Port (CPU
DSR, ers
(NOTE #2)
USART)
+-
______~x~______~----------------I-_tCR----,:I~tRR-Ic----
___
~=-
Rd
~
lf
~
l-tRD
l - tDF
DATA OUT
10.•.1
-I tAR I--
-
tRA
CID _ _ _ _ _ _ _ _-Jli
-I
r-~
tAR
I--
-
tRA
I--
----------~~------------~y---NOTE
#1: Twc INCLUDES THE RESPONSE TIMING OF A CONTROL BYTE.
NOTE #2: TCR INCLUDES THE EFFECT OF
ers ON THE TxENBL CIRCUITRY.
Transmitter Control & Flag Timing (ASYNC Mode)
tTxEMPTY
Tx EMPTY
TxAEADY
(STATUS BIT)
TxREADY
IPiNI
c/o
WrSBRK
TxDATA
-e. ...
NM..,.1tI1O
~~DATACHAR4 !::
EXAMPLE FORMAT'" 7 BIT CHARACTER WITH PARITY & 2 STOP BITS.
12·60
>-«
~~
t;c
g"'"
8251A
Receiver Control & Flag Timing (ASYNC Mode)
,--<
BREAK DETECT
- r-:-
OVERRUN ERRQR
lSTATUSBIT)
L--
~
CHAR 2
LOST
tR~RDY
1,-------.
-
RdDATA
wrRX~
c/O
WrERR
-;rRxEr>i
WrRlIEnJ
R"
u-
V
,J
\1.JJJ.JJJJJ
\.l
WJJ..AJJJJ
DATA CHAR 2
UJJJ.JJJ.AJ
EXAMPLE FORMAT = 7 BIT CHARACTER WITH PARITY & 2 STOP BITS
>--
-
~
Transmitter Control & Flag Timing (SYNC Mode)
ffl~~_ _ _ _ _~'~
TL-------~~TL-----------~
"READY
\
.L....J
(STATUS BIT}
"READY
fr-~rL...Jr
c/o
f\
"'" -
'-----,.
1''-----4
t
II
''"---
WrDATA
Wi _ _ _ _ _~,CHrAR~
' _CTHA~~~
;
'9-1
,.......
1'--1--+-+------1---1#
WrCOMMAND
SBRK
WrDATA WrDATA
MARKINGSTATE
'---
J~~l't'----~r - ~
1,1
WrDATA
CHAR 3
t !f:l~ C~~~A2
."
\'1\";;;'i;;DAii'''ttI---1-1----
CHAR,~
~RKh
CH~~A3
C~~TRA~ M~~! s::;~1 M~~~
s Jc\'-----.I
. " , ',,:' ':'X',,:""
rIt----+-----
j
hT,,5
wrcoMMA'JrI
'"'
DATA
CHARS
SYNC
CHAR
••
EXAMPLE FORMAT" 5 BIT CHARACTER WITH PARITY, 2 SYNC CHARACTERS
Receiver Control & Flag Timing (SYNC Mode)
SVNDET
(PIN) NOTE.:1
r~OTE~
tlS--"
tES_ ~
I-
SVNOET(S,B)
tL--
OVERRUN
ERROR (S,B)
.'---
,--
~
,os,
--.l~rEH t
---v
CARE'
",
Rd DATA
CHARl
Rd DATA
CHAR 1
RxEnl
DON'T
I~
~Ls
Rx ROY (PIN)
C/O
I----<
SYNC
CHAR 1
x ~ x 0 1 2 3 • :
SYNC
CHAR2
DATA
CHAR 1
~
CHAR 2
DATA
CHAR 3
RdSTATUS
~CHARASSnE1,JsT
RdDATA
'\.1
L
CHAR 1
, •• ':'X·
EXIT HUNT MODE
SET SYN DET (STATUS B)T)
INTERNAL SYNC. 2 SYNC CHARACTERS, 5BITS, WITH PARITY
EXTERNAL SYNC, 5 BITS, WITH PARITY
12-61
Ir--
CHAR 2
«012
CHAR ASSY
/ ' BEGINS
J1Jl1 fir
EXIT HUNT MODE
SETSVNCDET
DATA \..
DATA
DON'T CARE
I I I I I
JlJU1JlJ
r--
\....
0 1 2 3 • «0123. «0123. «01234 cOl 23. «0123. «xxxxxxx
I I I I I I I I I I I I I
NOTE =1
NOTE =2
-- - - --<
RdWS;:~~S
Rd SYNC
CHAR 1
t~
CHAR 1
I-
lJUl
:'1'
ETC.
<
hrL
SET SYNDET (STATUS BIT)'
inter
M8251
PROGRAMMABLE COMMUNICATION INTERFACE
• Synchronous and Asynchronous
Operation
• Full Duplex, Double Buffered Trans·
mitter and Receiver
• Synchronous - 5 8·Bit Characters;
Internal or External Character Synchro·
nization; Automatic Sync Insertion
• Error Detection Framing
Parity, Overrun, and
• Asynchronous - 5 8·Bit Characters;
Clock Rate - 1, 16, or 64 Times Baud
Rate; Break Character Generation; 1,
1V2, or 2·Stop Bits; False Start Bit
Detection
• Fully Compatible with 8080 CPU
• Baud Rate - DC to 56K Baud (Sync
Mode), DC to 8.1 K Baud (Async Mode)
• Full Military Temperature Range
- 55°C to + 125°C
• All Inputs and Outputs TTL
Compatible
The Intel® M8251 is a universal synchronous/asynchronous receiver/transmitter (USART) chip designed for data com·
munications in microcomputer systems. The USART is used as a peripheral device and is programmed by the CPU to
operate using virtually any serial data transmissioin technique presently in use (including IBM ubi·sync"). The USART
accepts data characters from the CPU in parallel format and then converts them Into a continuous serial data stream
for transmission. Simultaneously it can receive serial data streams and convert them into parallel data characters for
the CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has
received a character for the CPU. The CPU can read the complete status of the USART at any time. These include data
transmission errors and control signals such as SYNDET, TxEMPT. The chip is constructed uSing N·channel silicon
gate technology.
PIN CONFIGURATION
D,
D,
D3
Do
BLOCK DIAGRAM
RxD
Vee
GND
R;C
TRANSMIT
BUFFER
D5
DTR
RTS
D,
DsR
D,
RESET
D4
TxC
ClK
WR
TxD
cs
C/O
AD
RxADY
IP-SI
TxRDY
TxEMPTY
CTS
SYNDET
CS _ _ _...J
TxRDY
Vee
Pm Function
Data Set Ready
Data Terminal Ready
Sync Detect
Request to Send Data
Clear to Send Data
Transmitter Empty
+5 Volt Supply
GND
Ground
Pm Name
Pm Function
Pin Name
07,00
C/D
Data Bus (8 bits)
DSR
DTR
RD
WR
CS
elK
RESET
Control or Data is to be Written or Read
Read Data Command
Write Data or Control Command
Chip Enable
Clock Pulse (TTL)
Reset
TxC
TxD
Rxe
RxD
Transmitter Clock
Transmitter Data
RxRDY
Receiver Ready (has character for 8080)
Transmitter Ready (ready for char. from 8080)
TxADY
SYNDET
RTS
CTS
TxE
/
INTERNAL
DATA BUS
Receiver Clock
Receiver Data
12·62
R)lRDY
R;c
_SYNDET
M8251
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ..... -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
Voltage On Any Pin
With Respect to GND . . . . . . . . . . . . . . -O.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS*
TA
= -55°C to +125°C; V cc = 5.0V ±10%; GND = ov
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VO H
Output High Voltage
IDL
Data Bus Leakage
III
Input Load Current
Icc
Power Supply Current
Mm.
Typ.
Max.
Unit
Typ.
Test Conditions
• Nole: Military specifications have not yet been established.
CAPACITANCE
TA
= 25°C; Vec = GND = OV
Max.
Unit
4N
Input Capacitance
10
pF
fc=lMHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to GND.
Symbol
Parameter
Min.
Test Conditions
+20
/
2V
+'0
S
>-
510S1
~
"...i2
...
:;)
D.U.T.
0
TEST~INTS <::x. ___
0.45 _ _ _J
-
12-74
8253/8253·5
Clock and Gate Timing:
8253-5
8253
SYMBOL
Not~
1:
PARAMETER
MIN_
MAX.
MIN.
MAX.
UNIT
dc
380
dc
ns
tCLK
Clock Period
380
tPWH
High Pulse Width
230
230
ns
tpWL
Low Pulse Width
150
150
ns
tGW
Gate Width High
150
150
ns
tGL
Gate Width Low
100
100
ns
tGS
Gate Set Up Time to CLKt
100
100
ns
tGH
Gate Hold Time After CLKt
50
50
ns
tOD
Output Delay From CLK,j,[1]
400
400
ns
tODG
Output Delay From Gate,),[1]
300
300
ns
Test Conditions: 8253: CL = 1 OOpF; 8253-5: CL = 150pF.
12-75
8255A/8255A·5
PROGRAMMABLE PERIPHERAL INTERFACE
• MCS·85™ Compatible 8255A·5
• Direct Bit Set/Reset Capability Easing
Control Application Interface
• 24 Programmable 1/0 Pins
• Completely TTL Compatible
• 40·Pin Dual In·Line Package
• Fully Compatible with Intel® Micro·
processor Families
• Reduces System Package Count
• Improved Timing Characteristics
• Improved DC Driving Capability
The Intel@ 8255A is a general purpose programmable 1/0 device designed for use with Intel@ microprocessors. It has
241/0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first
mode (MODE 0), each group of 12110 pins may be programmed in sets of 4 to be input or output. In MODE 1, the second
mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8
lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking.
PIN CONFIGURATION
8255A BLOCK DIAGRAM
1'0..... (1<
SUPPll!S
{ _.w
_(,,"II
lin
,,~~~~/
GA~lJP
°7- 0 0
DATA BUS (SI·DIRECTIONAl)
RESET
RESET INPUT
C!
AD
Wi!
CHIPSELECT
AO,A1
PA7·PAO
• P87·P80
PC7·PCO
Vee
GND
I/,--_~
IC=~
PIN NAMES
READ INPUT
WRITE INPUT
PORT ADDRESS
PORT A IBIT)
PORT BIBIT)
PORT C IBIT)
+5 VOLTS
'VOLTS
© Intel Corporation, 1978
12-76
pc,
I'C.
8255A18255A·5
8255A FUNCTIONAL DESCRIPTION
(RD)
Read. A "low" on this input pin enables the 8255A to
send the data or status information to the CPU on the
data bus. In essence, it allows the CPU to "read from"
the 8255A.
General
The 8255A Is a programmable peripheral Interface (PPI)
device designed for use In Intel~ microcomputer
systems. Its function is that of a general purpose I/O
component to interface peripheral equipment to the
microcomputer system bus. The functional configura·
tlon of the 8255A is programmed by the system software
so that normally no external logic is necessary to Inter·
face peripheral devices or structures.
(WR)
Write_ A "low" on this input pin enables the CPU to write
data or control words into the 8255A.
(Ao and Ad
Data Bus Buffer
This 3-state bldirectional8·bit buffer is used to interface
the 8255A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status infor·
mation are also transferred through the data bus buffer.
Port Select 0 and Port Select 1. These input signals, in
conjunction with the RD and WR inputs, control the
selection of one of the three ports or the control word
registers. They are normally connected to the least
significant bits of the address bus (AD and A l ).
8255A BASIC OPERATION
The function of this block is to manage all of the internal
and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the
Control Groups.
INPUT OPERATION (READt
AO
0
1
0
RD
WR
CS
0
0
1
0
0
0
1
1
1
0
0
0
PORTA-DATA BUS
PORT B - DATA BUS
PORT C- DATA BUS
OUTPUT OPERATION
(WRITE)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
DATA
DATA
DATA
DATA
X
1
X
1
X
0
X
1
1
0
DATA BUS- 3-STATE
I LLEGAL CONDITION
X
X
1
1
0
DATA BUS - 3-STATE
A,
ReadlWrlte and Control Logic
BUS BUSBUS BUS -
PORT A
PORT B
PORT C
CONTROL
DISABLE FUNCTION
(CS)
Chip Select A "low" on this input pin enables the communlction between the 8255A and the CPU.
Figure 1. 8255A Block Diagram Showing Data Bus Buffer and ReadlWrite Control Logic Functions
12·77
8255A18255A·5
(RESET)
Ports A. B. and C
Reset_ A "high on this Input clears the control register
and all ports (A, C, C) are set to the input mode.
The 8255A contains three 8-blt ports (A, B, and C). All
can be configured In a wide variety of functional characteristics by the system software but each has its own
special features or "personality" to further enhance the
power and flexibility of the 8255A.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255A. The control word contains Information such as "mode", "bit set", "bit reset",
etc., that initializes the functional configuration of the
8255.
Each of the Control blocks (Group A and Group B) accepts
"commands" from the ReadlWrite Contr~1 Logic, receives
"control words" from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7-C4)
Control Group B - Port B and Port Clower (C3-CO)
Port A_ One 8-blt data output latch/buffer and one 8-bit
data input latch.
Port B. One 8-bit data input/output latch/buffer and one
8-bit data Input buffer.
Port C. One 8-blt data output latch/buffer and one 8-blt
data Input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control.
Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signal inputs in
conjunction with ports A and B.
The Control Word Register can Only be written into. No
Read operation of the Control WOrd Register is allowed.
PIN CONFIGURATION
'".,.
«
!Vi"---<\I
PIN NAMES
"'00-----o 8257 is a 4-channel direct memory access (DMA) controller. It is specifically designed to simplify the
transfer of data at high speeds for the Intel microcomputer systems. Its primary function is to generate, upon a
peripheral request, a sequential memory address which will allow the peripheral to read or write data directly to or
from memory. Acquisition of the system bus in accomplished via the CPU's hold function. The 8257 has priority logic
that resolves the peripherals requests and issues a composite hold request to the CPU. It maintains the DMA cycle
count for each channel and outputs a control signal to notify the peripheral that the programmed number of DMA
cycles is complete. Other output control signals simplify sectored data transfers and expansion to other 8257 devices
for systems that require more than 4 channels of DMA controlled transfer. The 8257 represents a significant savings in
component count for DMA-based microcomputer systems and greatly simplifies the transfer of data at high speed between peripherals and memories.
PIN CONFIGURATION
BLOCK DIAGRAM
HRQ
CLK
RESET
DACK2
DACK3
DRQ3
ORQ2
ORO 1
PIN NAMES
ADDRESS ENABLE
07-0 0
DATA BUS
AEN
A7-AO
ADDRESS BUS
I/O·READ
ADSTB
ADDRESS STROBE
TC
TERMINAL COUNT
110 WIii'fE
MARK
MODULO 128 MARK
MEMORY READ
DRQa·DRDo
i70R
i7CIW
MEMFi
MEMW
MEMORY WRITE
CLK
CLOCK INPUT
RESET
RESET INPUT
READY READY
HRQ
HOLD REQUEST
(T080SOAI
HLDA
HOLD ACKNOWLEDGE
(FROM SOSOA)
DMA REQUEST
INPUT
DACK3-DACKo DMA ACKNOWLEDGE
OUT
CS
CHIP SELECT
\l:c
+5 VOLTS
GND
GROUND
© Intel Corporation, 1978
12-98
8257/8257·5
FUNCTIONAL DESCRIPTION
Block Diagram Description
General
The 8257 is a programmable, Direct Memory Access
(DMA) device which, when coupled with a single Intel®
8212 I/O port device, provides a complete four-channel
DMA controller for use in Intel® microcomputer systems.
After being initialized by software, the 8257 can transfer a
block of data, containing up to 16,384 bytes, between
memory and a peripheral device directly, without further
intervention required of the CPU. Upon receiving a DMA
transfer request from an enabled peripheral, the 8257:
• Acquires control of the system bus.
• Acknowledges that requesting peripheral which is
connected to the highest priority channel.
• Outputs the least significant eight bits of the memory
address onto system address lines Ao-A7, outputs
the most significant eight bits of the memory address
to the 8212 1/0 port via the data bus (the 8212
places these address bits on lines A s·A 15), and
1. DMA C h a n n e l s · .
channel~(I~1EI9,
The 8257 provides four separate DMA
CH-O to CH-3). Each channel includes two sixteen::ibjt·
registers: (1) a DMA address register, and (2) a terminal count register. Both registers must be initialized
before a channel is enabled. The DMA address register is
loaded with the address of the first memory location to be
accessed. The value loaded into the low-order 14-bits of
the terminal count register specifies the number of DMA
cycles minus one before the Terminal Count (TC) output
is activated. For instance, a terminal count of 0 would
cause the TC output to' be active in the first DMA cycle for
that channel. In general, if N = the number of desired DMA
cycles,load the value N-1 into the low-order 14-bits of the
terminal count register. The most significant two bits of the
terminal count register specify the type of DMA operation
for that channel:
• Generates the appropriate memory and I/O read/
write control signals that cause the peripheral to
receive or deposit a data byte directly from or to the
addressed location in memory.
The 8257 will retain control of the system bus and repeat
the transfer sequence, as long as a peripheral maintains its
DMA request. Thus, the 8257 can transfer a block of data
to/from a high speed peripheral (e.g., a sector of data on a
floppy disk) in a single "burst". When the specified
number of data bytes have been transferred, the 8257
activates its Terminal Count (TC) output, informing the
CPU that the operation is complete.
The 8257 offers three different modes of operation:
(1) DMA read, which causes data to be transferred from
memory to a peripheral; (2) DMA write, which causes
data to be transferred from a peripheral to memory;
and (3) DMA verify, which does not actually involve the
transfer of data. When an 8257 channel is in the DMA verify
mode, it will respond the same as described for transfer
operations, except that no memory or I/O read/write
control signals will be generated, thus preventing the
transfer of data. The 8257, however, will gain control of the
system bus and will acknowledge the peripheral's DMA
request for each DMA cycle. The peripheral can use these
acknowledge signals to enable an internal access of each
byte of a data block in order to execute some verification
procedure, such as the accumulation of a CRC (Cyclic
Redundancy Code) checkword. For example, a block of
DMA verify cycles might follow a block of DMA read cycles
(memory to peripheral) to allow the peripheral to verify its
newly acquired data.
Figure 1. 8257 Block Diagram Showing DMA
Channels
12·99
8257/8257·5
These two bits are not modified during a DMA cycle, but
can be changed between DMA blocks.
BIT 15
BIT 14
Each channel accepts a DMA Request (DRQn) input and
provides a DMA Acknowledge (DACKn) output:
o
o
o
(DRQ O-DRQ 3)
1
1
1
o
1
'fr
Verily DMA~r~
Write DMA cycli<,
Read DMA Cycle'·
(Illegal)
>"r">
>
DMA Request: These are individual asynchronous channel request inputs used by the peripherals to obtain a DMA
cycle. If not in the rotating priority mode then DRQ 0 has
the highest priority and DRQ 3 has the lowest. A request
can be generated by raising the request line and holding it
high until DMA acknowledge. For multiple DMA cycles
(Burst Mode) the request line is held high until the DMA
acknowledge of the last cycle arrives.
(DACK 0 - DACK 3)
DMA Acknowledge: An active low level on the acknowledge output informs the peripheral connected to that
channel that it has been selected for a DMA cycle.
2. Data Bus Buffer
This three-state, bi-directional, eight bit buffer interfaces
the 8257 to the system data bus:
(Do-D7)
Data Bus Lines: These are bi-directional three-state lines.
When the 8257 is being programmed by the CPU, eightbits of data for a DMA address register, a terminal count
register or the Mode Set register are received on the data
bus. When the CPU reads a DMA address register, a
terminal count register or the Status register, the data is
s.,,°nt to the CPU over the data bus. During DMA cycles
(when the 8257 is the bus master), the 8257 will output the
most significant eight-bits of the memory address (from
one of the DMA address registers) to the 8212 latch via the
data bus. These address bits will be transferred at the
beginning of the DMA cycle; the bus will then be released
to handle the memory data transfer during the balance of
the DMA cycle.
Figure 2. 8257 Block Diagram Showing Data Bus
Buffer
12·100
8257/8257·5
3. ReadlWrlte logic
(Ao-Aa)
'"
.
When the CPU is programming or reading one of the
8257's register (i.e., when the 8257 is a "slave" device on
the system bus), the Read/Write Logic accepts the I/O
Read (m5R) or I/O Write (I/OW) signal, decodes the least
significant four address bits, (Ao-A3), and either writes the
contents of the data bus into the addressed register (if
I/OW is true) or places the contents of the addressed
register onto the data bus (if I/OR is true),
Address Lines: These least significant f~;:'ag
are bi-directional. In the "slave" mode ti1~"J~
which select one of the registers to beA.lf.:Q A!. . ~ ,>
operations began with Channel 0 initially assigned1p'the' ,~
highest priority for the first DMA cycle.
., ,~ .
Extended Write Bit 5
If the EXTENDED WRITE bit is set, the duration of both the
MEMWand I/OW signals is extended by activating them
earlier in the DMA cycle. Data transfers within microcomputer systems proceed asynchronously to allow
use of various types of memory and I/O devices with
different access times. If a device cannot be accessed
within a specific amount of time it returns a "not ready"
indication to the 8257 that causes the 8257 to insert one or
more wait states in its internal sequencing. Some devices
are fast enough to be accessed without the use of wait
states, but if they generate their READY response with the
leading edge of the I/OW or MEMW signal (which
generally occurs late in the transfer sequence), they
would normally cause the 8257 to enter a wait state
because it does not receive READY in time, For systems
with these types of devices, the Extended Write option
provides alternative timing for the I/O and memory write
signals which allows the devices to return an early READY
and prevents the unnecessary occurrence of wait states in
the 8257, thus increasing system throughput.
TC Stop Bit 6
If the TC STOP bit is set, a channel is disabled (i.e., its
enable bit is reset) after the Terminal Count (TC) output
goes true, thus automatically preventing further DMA
operation on that channel. The enable bit for that channel
must be re-programmed to continue or begin another
DMA operation. If the TC STOP bit is not set, the
occurrence of the TC output has no effect on the channel
enable bits. In this case, it is generally the responsibility of
the peripheral to cease DMA requests in ordertoterminate
a DMA operation.
If the ROTATING PRIORITY bit is not set (set to a zero),
each DMA channel has a fixed priority. In the fixed priority
mode, Channel 0 has the highest priority and Channel 3
has the lowest priority. If the ROTATING PRIORITY bit is
set to a one, the priority of each channel changes after
each. DMA cycle (not each DMA request). Each channel
moves up to the next highest priority assignment, while
the channel which has just been serviced moves to the
lowest priority assignment:
CHANNEL'" CH-O CH-1 CH-2 CH-3
JUST SERVICED
Priority _
Anlgnments
Hlghelt
t
Lowest
CH-1
CH-2
CH-3
CH·O
CH-2
CH-3
CH-O
CH-1
CH-3
CH-O
CH-1
CH-2
CH-O
CH-1
CH-2
CH-3
Auto Load Bit 7
The Auto Load mode permits Channel 2 to be used for
repeat block or block chaining operations, without
immediate software intervention between blocks. Channel 2 registers are initialized as usual for the first data
block; Channel 3 registers, however, are used to store the
block re-initialization parameters (DMA starting address,
terminal count and DMA transfer mode). After the first
block of DMA cycles is executed by Channel 2 (i.e., after
the TC output goes true), the parameters stored in the
Channel 3 registers are transferred to Channel 2 during an
"update" cycle. Note that the TC STOP feature, described
above, has no effect on Channel 2 when the Auto Load bit
is set.
12·103
8257/8257·5
If the Auto Load bit is set, the initial parameters for
Channel 2 are automatically duplicated in the Channel 3
registers when Channel 2 is programmed. This permits
repeat block operations to be set up with the programming
of a single channel. Repeat block operations can be used
in applications such as CRT refreshing. Channels 2 and 3
can still be loaded with separate values if Channel 2 is
loaded before loading Channel 3. Note that in the Auto
Load mode, Channel 3 is still available to the user if the
Channel 3 enable bit is set, but use of this channel will
change the values to be auto loaded into Channel 2 at
update time. All that is necessary to use the Auto Load
feature for chaining operations is to reload Channel 3
registers at the conclusion of each update cycle with the
new parameters for the next data block transfer.
Te STATUS FOR
Te STATUS FOR
' - - - - - - T e ST.4.TUS FOR
' - - - - - - - T C STATUS FOR
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
The TC status bits are set when the Terminal Count (TC)
output is activated for that channel. These bits remain set
until the status register is read or the 8257 is reset. The
UPDATE FLAG, however, is not affected by a status
register read operation. The UPDATE FLAG can be
cleared by resetting the 8257, by changing to the non-auto
load mode (i.e., by resetting the AUTO LOAD bit in the
Mode Set register) or it can be left to clear itself at the
completion of the update cycle. The purpose of the
UPDATE FLAG is to prevent the CPU from inadvertently
Skipping a data block by overwriting a starting address or
terminal count in the Channel 3 registers before those
parameters are properly auto-loaded into Channel 2.
Each time that the 8257 enters an update cycle, the update
flag in the status register is set and parameters in Channel
3 are transferred to Channel 2, non-destructively for
Channel 3. The actual re-initialization of Channel 2 occurs
at the beginning of the next channel 2 DMA cycle after the
TC cycle. This will be the first DMA cycle of the new data
block for Channel 2. The update flag is cleared at the
conclusion of this DMA cycle. For chaining operations,
the update flag in the status register can be monitored by
the CPU to determine when the re-initialization process
has been completed so that the next block parameters can
be safely loaded into Channel 3.
RESET
\
¥
\
\:
----[1.fU1fL - - SLfL..Jt
>--
I
\
+--JlJ1J1J1Jf--f\-\-----om"""
- Ii"co,,~,,-
,.""',, , .-
-j:
_ _ _ _ _ _ _ _----'n
'I
nLI-;fi--!+1_ _
!JHRO
rL
_ _ _ _ _-----'rl/
III
!
HRO
o
~
HeM
HLDA
Figure 5. Autoload Timing
9
9
8257 Register Selection
0\,1'
A,
.
0,
0,
0,
0 ..
0.
.. ..." .. .... " .,
."
'"0· '"0.
"
co,
."
.."'""
en
MODE lET (PI'CIII"'" only)
STATU8 (A.1Id on11)
w,
,
c.
0"
A"
0,
C"
0,
0 ..
e,,,
~·TT'i
:r[l
1. HRO IS set If DRQI) is active .
2. HRQ is reset if DRQ7jI IS not active.
)":r,~l,,
'" """ '"
o'I'osl'owl up
TC3 TC2 Tel TCO
'A,rA" OM ... $larlong Address C,"C,. Tefmmal Count val"e (N·l) Rd and Wr OMA V""fy (00), W"le (Ot) or Read (10)
Al
A~loLoad.TCS
.
A,
cycle.elechc~
TCSTOP EW EXTENDEOWRITE,RP ROTATINGPRIORITV,EN:J.-ENO CHANNELENABLEMASK,UP UPDATE
flAG, Te3-TCO TERMINAL COUNT STATUS BITS
Figure 6. DMA Operation State Diagram
12·104
8257/8257·5
,. ~\';:.:"t
c,
Programming and Reading the 8257 Registers
DMA Operation
There are four pairs of "channel registers": each pair
consisting of a 16-bit DMA address register and a 16-bit
terminal count register (one pair for each channel). The
8257 also includes two "general registers": one 8-bit
Mode Set register and one 8-bit Status register. The
registers are loaded or read when the CPU executes a
write or read instruction that addresses the 8257 device
and the appropriate register within the 8257. The 8228
generates the appropriate read or write control signal
(generally liaR or IIOW while the CPU places a 16-bit
address on the system address bus, and either outputs the
data to be written onto the system data bus or accepts the
data being read from the data bus. All or some of the most
significant 12 address bits A4-Als (depending on the
systems memory, 1/0 configuration) are usually decoded
to produce the chip select (CS) input to the 8257. An 1/0
Write input (or Memory Write in memory mapped 1/0
configurations, described below) specifies that the
addressed register is to be programmed, while an 1/0
Read input (or Memory Read) specifies that the addressed
register is to be read. Address bit 3 specifies whether a
"channel register" (AJ = 0) or the Mode Set (program
only)/Status (read only) register (A3 = 1) is to be accessed.
Internal 8257 operations may proceed thl'ou9l\*,
different states. The duration of a state is defined
clock input. When the 8257 is not executing oMAc
it is in the idle state, SI . A DMA cycle begins when
more DMA Request (DROn) lines become active. Th~
8257 then enters state So, sends a Hold Request (HRO) to
the CPU and waits for as many So states as are necessary
for the CPU to return a Hold Acknowledge (HLDAl. For
each So state, the DMA Request lines are again sampled
and DMA priority is resolved (according to the fixed or
rotating priority scheme). When HLDA is received, the
DMA Acknowledge (DACKn) line for the highest priority
requesting channel is activated, thus selecting that
channel and its peripheral for the DMA cycle. The 8257
then proceeds to state SI. Note that the DMA Request
(DROn) input should remain high until either DACKn is
received for a single DMA cycle service, or until both the
DACKn and TC outputs are received when transferring an
entire data block in a "burst" mode. If the 8257 should lose
control of the system bus (i.e., if HLDA goes false), the
DMA Acknowledge will be removed after the current DMA
cycle is completed and no more DMA cycles will occur
until the 8257 again acquires control of the system bus.
The least significant three address bits, Ao-A2, indicate the
specific register to be accessed. When accessing the
Mode Set or Status register, Ao-A2 are all zero. When
accessing a channel register bit Ao differentiates between
the DMA address register (Ao = 0) and the terminal count
register (Ao = 1), while bits Al and A2 specify one of the
Each DMA cycle will consist of at least four internal
states: SI, S2, S3, and S4. If the access timeforthe memory
or 1/0 devices involved is not fast enough to return the
required READY response and complete a byte transfer
within the specified amount of time, one or more wait
states (SW) are inserted between states S3 and S4. Recall
that in certain cases the Extended Write option can
eliminate the need for a wait state. Note that a READY
response is not required during DMA verify cycles.
Specified minimumlmaximum values for READY setup
time (tRS), write data setup time (tow), read data access
time (tRO) and HLDA setup time (tQs) are listed under A.C.
CHARACTERISTICS and are illustrated in the accompanying timing diagrams.
cs
IIOW
1I0R
A3
Program Half 01 a
Channel Register
0
0
1
0
Read Half 01 a
Channel Register
0
1
0
0
Program Mode Set
Register
0
0
1
1
Read Status Register
0
1
0
1
CONTROL INPUT
\\,(\\\,
a
four channels. Because the "channel registers" are 16bits, two program instruction cycles are required to load
or read an entire register. The 8257 contains a first/last
(F/L) flip flop which toggles at the completion of each
channel program or read operation. The F/L flip flop
determines whether the upper or lower byte of the register
is to be accessed. The F/L flip flop is reset by the RESET
input and whenever the Mode Set register is loaded. To
maintain proper synchronization when accessing the
"channel registers" all channel command instruction
operations should occur in pairs, with the lower byte of a
register always being accessed first. Do not allow CS to
clock while either liaR or IIOW is active, as this will cause
an erroneous F/L flip flop state. In systems utilizing an
interrupt structure, interrupts should be disabled prior to
any paired programming operations to prevent an
interrupt from splitting them. The result of such a split
would leave the F/L F/F in the wrong state. This problem is
particularly obvious when other DMA channels are
programmed by an interrupt structure.
one
During DMA write cycles, the 1/0 Read (liaR) output is
generated at the beginning of state S2 and the Memory
Write (MEMW) output is generated at the beginning of S3.
During DMA read cycles, the Memory Read (MEMR)
output is generated at the beginning of state S2 and the 1/0
Write (IIOW) output goes true at the beginning of of state
S3. Recall that no read or write control signals are
generated during DMA verify cycles. Extended WR for
MEM and 1/0 will be generated in S2.
Memory Mapped 1/0 Configurations
The 8257 can be connected to the system bus as a memory
device instead of as an 1/0 device for memory mapped 1/0
configurations by connecting the system memory control
lines to the 8257's 1/0 control lines and the system 1/0
control lines to the 8257's memory control lines.
This configuration permits use of the 8080's considerably
larger repertoire of memory instructions when reading or
loading the 8257's registers. Note that with this
connection, the programming of the Read (bit 15) and
Write (bit 14) bits in the terminal count register will have a
different meaning:
12·105
8257/8257·5
MEMRD
IIORD
MEMWR
IIOWR
BIT 15
READ
BIT 14
WRITE
0
0
0
1
0
1
8257
IIORD
MEM RD
IIOWR
MEMWR
Figure 7. System Interface for Memory Mapped I/O
Figure 8. TC Register for Memory Mapped 1/0 Only
-----_._------,
--'/0,
~:':'''"OO,,"O'
;;;:w;wells
;0.;
__
o~ao
_ _ O.o.CK,
_ _ ORO,
_OACK,
D~a,
•_ _ OACK,
Figure 9. Detailed System Interface Schematic
SYSTEM APPLICATION EXAMPLES
Figure 10. Floppy Disk Controller (4 Drives)
Figure 11. High·Speed Communication Controller
12-106
8257/8257·5
~'
~'~,. ~'~i
0
0
IMR =<> DATA BUS
DATA BUS (Note 1)
OUTPUT OPERATION (WRITE)
0
0
0
0
0
X
0
0
0
DATA BUS=<>OCW2
0
0
DATA BUS=<>OCW3
X
0
0
DATA BUS=<> ICW1
X
0
0
DATA BUS =<>OCW1, ICW2, ICW3 (Note 2)
DISABLE FUNCTION
X
X
X
X
X
X
Note 1:
Note 2:
1
X
X
0
DATA BUS =<> 3-STATE
DATA BUS=<> 3-STATE
Selection of IRR, ISR or Interrupting Level is based on the content of OeW3 written before the READ operation.
On-chip sequencer logic queues these commands into proper sequence.
Figure 4. 8259 Basic Operation
12-113
8259/8259·5
FUNCTIONAL DESCRIPTION
General
The 8259 is a device specifically designed for use in real
time, interrupt driven, microcomputer systems. It manages eight levels or requests and has built-in features for
expandability to other 8259s (up to 64 levels). It is
programmed by the system's software as an 1/0
peripheral. A selection of priority modes is available to the
programmer so that the manner in which the requests are
processed by the 8259 can be configured to match his
system requirements. The priority modes can be changed
or reconfigured dynamically at any time during the main
program. This means thatthe complete interrupt structure
can be defined as required, based on the total system
environment.
Interrupt Request Register (IRR) and
In-Service Register (ISR)
,ice
The interrupts at the IR input lines are handled by two
registers in cascade, the Interrupt Request Register (IRR)
and the In-Service Register (ISR). The IRR is used to store
all the interrupt levels which are requesting service; and
the ISR is used to store all the interrupt levels which are
being serviced.
Priority Resolver
This logic block determines the priorities of the bits set in
the I RR. The highest priority is selected and strobed into
the corresponding bit of the ISR during INTA pulse.
Figure 5. 8259 Block Diagram Showing Basic: Interrupt
Functions
INT (Interrupt)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible
with the 8080 input level.
INTA (Interrupt Acknowledge)
Three INTA pulses will cause the 8259 to release a 3-byte
CALL instruction onto the Data Bus.
Interrupt Mask Register (IMR)
~,{-
The I MR stores the bits of the interrupt lines to be masked.
The IMR operates on the ISA. Masking of a higher priority
input will not affect the interrupt request lines of lower
priority.
LINES
cs
CAS 0
CAS 1
Ao
ViR
RJj
INT
INTA
8259
CAS2
SP
SLAVE
PROG.
I
rI
INTERRUPT
REQUESTS
Figure 6. 8259 Interface to Standard System Bus
12·114
8259/8259·5
3. The CPU acknowledges the INT and responds with an
INTA pulse.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259 will also release a CALL
instruction code (11001101) onto the B-bit Data Bus
through its 07-0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259 from the CPU group.
6. These two INTA pulses allow the 8259 to release its
preprogrammed subroutine address onto the Data Bus.
The lower 8-bit address is released at the first INTA
pulse and the higher 8-bit address is released at the
second INTA pulse.
7. This completes the 3-byte CALL instruction released
by the 8259. ISR bit is not reset until the end of the
subroutine when an EOI (End of interrupt) command is
issued to the 8259.
SP (Slave Program)
More than one 8259 can be used in the system to expand
the priority interrupt scheme up to 64 levels. In such case,
one 8259 acts as the master, and the others act as slaves. A
"high" on the SP pin designates the 8259 as the master, a
"low" designates it as a slave.
The Cascade/Buffer/Comparator
This function block stores and compares the IDs of all
8259 used in the system. The associated three I/O pins
(CASO-2) are outputs when the 8259 is used as a master
(SP = 1), and are inputs when the 8259 is used as a slave
(SP = 0). As a master, the 8259 sends the 10 of the
interrupting slave device onto the CASO-2Iines. The slave
thus selected will send its preprogrammed subroutine
addressed onto the Data Bus during next two consecutive
INTA pulses. (See section "Cascading the 8259".)
. :. . :.«< ' ,.', ,.. 1.~>~~~>,:.:+.... "
;!:: .. "
. ,'i.:'" ..
Programming The 8259
,:.,",
The 8259 accepts two types of command words generated
by the CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 8259 in the
system must be brought to a starting point - by a
sequence of 2 or 3 bytes timed by WR pulses. This
sequence is described in Figure 1.
2. Operation Command Words (OCWs):
These are the command words which command the
8259 to operate in various interrupt modes. These
modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259 at anytime after
initialization.
lew,
'.:'.-.:"
.. " ,
.. ~' :,':'
. .".,'
:~
.....
'n
•
',;::.::'
ICW2
Figure 7. 8259 Block Diagram Showing Cascading
Function
OPERATIONAL DESCRIPTION
General
The powerful features of the 8259 in a microcomputer
system are its programmability and its utilization of the
CALL instruction to jump into any address in the memory
map. The normal sequence of events that the 8259
interacts with the CPU is as follows:
ICW3
1. One or more of the INTERRUPT REQUEST lines (lR7Ol are raised high, setting the corresponding IRR bit(s).
2. The 8259 accepts these requests, resolves the
priorities, and sends an INT to the CPU.
Figure 8. Initialization Sequence
12-115
8259/8259·5
Example of Interrupt Acknowledge Sequence
Initialization Command Words 1 and 2 (ICW1 and
ICW2)
Assume the 8259 is programmed with F = 1 (CALL address
interval = 4), and IR5 is the interrupting level. The 3 byte
sequence released by the 8259 timed by the INTA pulses is
as follows:
Whenever a command is issued with AO = Oand D4 = 1, this
is interpreted as Initialization Command Word 1 (ICW1),
and initiates the initialization sequence. During this
sequence, the following occur automatically:
a. The edge sense circuit is reset, which means that
following initialization, an interrupt request (IR)
input must make a low to high transition to generate
an i nterru pt.
b. The interrupt Mask Register is cleared.
c. IR 7 input is assigned priority 7.
d. Special Mask Mode Flip-flop and status Read Flipflop are reset.
The 8 requesting devices have 8 addresses equally spaced
in memory. The addresses can be programmed at
intervals of 4 or 8 bytes; the 8 routines thus occupying a
page of 32 or 64 bytes respectively in memory.
,
06
1st INTA
2nd INTA
A7
A6
AS
3rd INTA
AIS
A14
A13
07
D.
D.
I
'--..,.--l- - -./\
A7
A.
A.
0_
03
O2
0,
Do
A_
A3
A2
A,
Ao
DEFINED BY 05-7 OF ICWI
03
02
DO
01
CALL
CODE
LOWER
ROUTINE
ADDRESS
0
A'2
Al1
Al0
HIGHER
ROUTINE
ADDRESS
A8
A9
Initialization Command Word 3 (lCW3)
a. If the 8259 is the master. a "1" is set for each slave in
the system. The master then will release byte 1 of the
CALL sequence and will enable the corresponding
slave to release bytes 2 and 3, through the cascade
lines.
b. If the 8259 is a slave, bits 2 - 0 identify the slave. The
slave compares its CASO-2 inputs (sent by the
master) with these bits. If they are equal, bytes 2 and
3 of the CALL sequence are released.
I
)
v
04
0
This will load the 8-bit slave register. The functions of this
register are as follows:
The address format is:
~
05
AUTOMATICALLY
INSERTED BY 8259
If bit S is set in ICW1, there is no need to program ICW3.
J
,~----------------~v
DEFINED BY ICW2
AO-4 are automatically inserted by the 8259, while A15-6
are programmed by ICW1 and ICW2. When interval =8, A5
is fixed by the 8259. If interval = 4, A5 is programmed in
ICW1. Thus, the interrupt service routines can be located
anywhere in the memory space. The 8 byte interval will
maintain compatibility with current 8080 RESTART
instruction software, while the 4 byte interval is best for
compact jump table.
1 "'SINGLE
0= NOT SINGLE
CALL ADDRESS INTERYAL
, = INTERVAL IS 4
o~
INTERVAL IS 8
A1-60F LOWER
ROUTINE ADDRESS
The address format inserted by the 8259 is described in
Table 1.
The bits F and S are defined by ICW1 as follows:
F: Call address interval. F =1, then interval =4;
then interval = 8.
F =0,
UPPER ROUTINE
ADDRESS
S: Single. S = 1 means that this is the only 8259 in the
system. It avoids the necesity of programming ICW3.
L-....L--'_.L--'-_L-...L...-L_-\
0":
1 '" IR INPUT HAS A SLAVE
~~:~~ DOES NOT HAVE
ICW3 (SLAVE DEVICE)
07
I.
I.
06
D.
03
,
, •
•
•• • ,
•
• •
7
A7
A6
AS
6
A7
A6
I• •
A7
A6
A'
AS
I.
0
A7
A6
AS
I.
I.
3
,
A7
.6
A7
I.
1
A7
A6
I• •
A7
A,
A6
,
04
1
1
A.
1
AS
·
A.
•
DO
07
D,
·•,, ·•• •••
A7
A.
A7
A6
,
02
0'
0
•
•, •
•
• •
0
•
•
•
•
Table 1. 8259 Address Format
AO
A6
A7
A7
A6
A6
.7
A6
A7
A6
0
, , •
, • •
, •
, •, ••
, • •
,
•
•
•
•
•
•
•
•
•
•
0
0
0
0
D'
1
,
,
,
•
•
DO
03
0'
0
0
0
0
0
0
01
0
00
0
SLAVE 10111
o
0
0
1 2 3 4 !i 6
010101
o
0
1
1 0
0
1
1
o
0
0
0
1
1
1
1
NOTE 1 SLAVE 10 IS eQUAL TO THE CORRESPONDING MASTER IR INPUT
Figure 9. Initialization Command Word Format
12-116
7
0'
8259/8259·5
Operation Command Words (OCWs)
AFTER ROTATE
After the Initialization Command Words (ICWs) are
programmed into the 8259, the chip is ready to accept
interrupt requests at its input lines. However, during the
8259 operation, a selection of algorithms can command
the 8259 to operate in various modes through the
Operation Command Words (OCWs). These various
modes and their associated OCWs are described below.
"IS" STATUS
IS7
IS6
ISS
0
1
0
I I
IS4
153
152
151
0
0
0
0
I I I
LOWEST PRIORITY
PRIORITY STATUS
I I
4
3
2
ISO
I
0
HIGHEST PRIORITY
I I
1
0
7
I I
6
5
I
I
Interrupt Masks
Each Interrupt Request input can be masked individually
by the Interrupt Masked Register (IMR) programmed
through OCW1.
The IMR operates on the In-Service Register. Note that if
an interrupt is already acknowledged by the 8259 Ian INTA
pulse has occurred), then the Interrupting level, although
masked, will inhibit the lower priorities. To enable these
lower priority interrupts, one can do one of two things: (1)
Write an End of Interrupt IEOI) command IOeW2) to reset
the ISR bit or (2) Set the special mask mode using OCW3
(as will be explained later in the special mask mode.)
Fully Nested Mode
The 8259 will operate in the fully nested mode after the
execution of the initialization sequence without any oew
being written. In this mode, the interrupt requests are
ordered in priorities from Othrough 7. When an interrupt is
acknowledged, the highest priority request is determined
and its address vector placed on the bus. In addition, a bit
of the Interrupt service register (IS 7-0) is set. This bit
remains set until the CPU issues an End of Interrupt IEOI)
command immediately before returning from the service
routine. While the IS bit is set, all further interrupts of lower
priority are inhibited, while higher levels will be able to
generate an interrupt (which will only be acknowledged if
the CPU has enabled its own interrupt input through
software),
After the Initialization sequence, IRO has the highest
priority and IR7 the lowest. Priorities can be changed, as
will be explained in the rotating priority mode.
Rotating Priority Commands
There are two variations of rotating priority: auto rotate
and specific rotate.
1. Auto Rotate -
Executing the Rotate-at-EOI IAuto)
command, resets the highest priority ISR bit and
assigns that input the lowest priority. Thus, a device
requesting an interrupt will have to wait, in the worst
case, until 7 other devices are serviced at most once
each, i.e., if the priority and "in-service" status is:
BEFORE ROTATE
"IS" STATUS
157
156
ISS
154
152
151
ISO
I I I I I I I I I
0
1
0
1
LOWEST PR lOR ITY
PRIORITY STATUS
153
I I I I
7
6
5
0
0
0
0
HIGHEST PRIORITY
4
In this example, the In-Service FF corresponding to
line 4 (the highest priority FF set) was reset and line 4
became the lowest priority, while all the other priorities
rotated correspondingly.
The Rotate command is issued in OeW2, where: R =
1, EOI = 1, SEOI = O.
2. Specific Rotate - The programmer can change
priorities by programming the bottom priority, and by
doing this, to fix the highest priority: i.e., if IR5 is
programmed as the bottom priority device, the IR6 will
have the highest one. This command can be used with
or without resetting the selected ISR bit.
The Rotate command is issued in OCW2 where: R = 1,
SEOI = 1. L2, L 1, LO are the BCD priority level codes of the
bottom priority device. If EOI = 1 also, the ISR bit selected
by L2-LO is reset.
Observe that this mode is independent of the End of
Interrupt Command and priority changes can be
executed during EOI command or independently from
the EOI command.
End of Interrupt (EOI) and Specific End of
Interrupt (SEOI)
An End of Interrupt command word must be issued to the
8259 before returning from a service routine, to reset the
appropriate IS bit.
There are two forms of EOI command: Specific and nonSpecific. When the 8259 is operated in modes which
preserve the fully nested structure, it can determine whiCh
IS bit to reset on EOI. When a non-Specific EOI command
is issued the 8259 will automatically reset the highest IS
bit of those that are set, since in the nested mode, the
highest IS level was necessarily the last level acknowledged and will necessarily be the next routine level
returned from.
However, when a mode is used which may disturb the fully
nested structure, such as in the rotating priority case, the
8259 may no longer be able to determine the last level
acknowledged. In this case, a specific EOI (SEOI) must be
issued which includes the IS level to be reset as part of the
command. The End of the Interrupt is issued whenever
EOI ="1" in OCW2. Forspecific EOI, SEOI ="1", and EOI =
1. L2, L 1, LO is then the BCD level to be reset. As explained
in the Rotate Mode earlier, this can also be the bottom
priority code. Note that although the Rotate command can
be issued during an EOI = 1, it is not necessarily tied to it.
12·117
8259/8259·5
Special Mask Mode (SMM)
This mode is useful when some bit(s) are set (masked) by
the Interrupt Mask Register (IMR) through OCW1. If, for
some reason, we are currently in an interrupt service
routine which is masked (this could happen when the
subroutine intentionally mask itself off), it is still possible
to enable the lower priority lines by setting the Special
Mask mode. In this mode the lower priority lines are
enabled until the SMM is reset. The high!!r priorities are
not affected.
1"1' 1""1"'1"1"1',1',1 ',1
HCD f,.EVEL TO BE RESET
OR
II L
pu'r INTO LOWESfPFUOAITV
012
,
The special mask mode FF is set by OCW3 where ESMM =
1, SMM = 1, and reset where: ESSM = 1 and SMM = O.
Polled Mode
SPECifiC END OF INTERRUPT
1
~: ~t ~~T~~:ns ARE
----------
In this mode, the CPU must disable its interrupt input.
Service to device is achieved by programmer initiative by a
Poll command.
USED
AOTATEPR,ORIlV
1 < HOTAh
0" NOT ROTATE
The poll command is issued by setting P = "1" in OCW3
during a WR pulse.
I' 1-
J.
I""I~MI
" 1' 1' 1""1 '" 1
I
L
~~:i
The 8259 treats the next RD pulse as an interrupt
acknowledge, sets the appropriate IS Flip-flop, if there is a
request, and reads the priority level.
flEADlNSEAVICfREGISTEA
L=~ir-:"-'I-:-'---'---:--r-:-l
I
For polling operation, an OCW3 must be written before
every read.
Ii"" ,Ii"' ' il
tARE£>
,SlUG
ON NEXT vNNO(T
RuPULSEIlO'ULSf
The word enabled onto the data bus during RD is:
07
I
I"'" I'" I
S~EC,AL
SPECIAL
MASt(
foIASI(
WO -
Figure 10. Operation Command Word Format
06
05
04
03
02
01
DO
W2
WI
WO
2: BCD code of the highest priority
requesting service.
I: Equal to a "1" if there is an interrupt.
level
This mode is useful if there is a routine common to
several levels - so that the INTA sequence is not
needed (and this saves ROM space). Another
application is to use the poll mode to expand the
number of priority levels to more than 64.
"04 ~OJl
.,.
1 R SeOI
:0 (}
LOI
0
0
'0
I:
, ,
,
0
,
;
;
i
l~MM
i
oeWJ I
(J
0
Snec,l,e ~r"l <>llnlefl"pl L2, L 1, L.O"II'" IJeD hNellobe
No Ac(,on
HOi.10Pr10",y.t fOI (AuwMo(lul
,.,e!.
;
1'I"'~1
S"OCI.' M.lk
s.., SI>"C'~' M".~
fHIS
0
!
.'010'
;
;
}
NoAct,on
k"~'IIR
RLN,,,,", :>1"''''
ReaaISfl"'i'''"'S,.,,,,
1~" Cr" :;,~~~:,~~,I,,',7,P;~::,:~~;: ~:r ~,',~~~~~:)~~','~'?" ••v.,"m
.'Aoy,"o""'""nor,."".'",,,,,,,"
Figure 11. Summary of Operation Word Programming
12-118
825918259·5
....dlng 8259 St.tus
C.sc.dlng
The input status of several internal registers can be read
to update the user information on the system. The
following registers can be read by Issuing a suitable
OCW3 and reading with RD.
Th. 8259 can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels.
A typical system is shown in Figure 2. The master controls,
through the 3 line cascade bus, which one ofthe slaves will
release the corresponding address.
Interrupt Requests Register IIRR): 8-bit register which
contains the levels requesting an Interrupt to be
acknowledged. The highest request level Is reset from the
IRR wh.n an interrupt is acknowledged. (Not affected by
IMR).
As shown in Figure 2, the slaves interrupt outputs are
connected to the master interrupt request inputs. When a
slave request line is activated and later acknowledged, the
master releases the 8080 CALL code during the fir$t INTA
pulse. From the trailing edge of this first iiiiTA pulse until
the trailing edge of the third pulse, the CAS lines will
contain the slave address code. Thus, the corresponding
slave is enabled to release the twa-byte service routine
address during the second and third INTA pulses.
In Service Register (ISR): 8-bit register which contains
the priority levels that are being serviced. The ISR is
updated when an End of Interrupt command is issued.
Interrupt Mask Register: 8-bit register which contains the
interrupt request lines which are masked.
The IRR can be read when prior to the RD pulse, an WR
pulse is issued with OCW3, and ERIS = 1, RIS = O.
Note that sincll the CAS lines default to 000, no slave
should be connected with IRO on the master unless all
other master request inputs UR1-IR7) are connected to
slaves. Otherwise, the slave on IRO will attempt to drive the
data bus in conflict with a non-slave interrupt request on
the master.
The ISR can be read in a similar mode, when ERIS = 1, RIS
= 1.
There is no need to write an OCW3 before every status
read operation as long as the status read corresponds with
the previous one, I.e. the 8259 "remembers" whether the
I RR or ISR has been previously selected by the OCW3.
It is obvious that each 8259 in the system must follow a
separate initialization sequence and can be programmed
to work in a different mode. An EOI command must be
issued twice: once for the master and once for the
corresponding slave. An address decoder is required to
activate the Chip Select (CS) input of each 8259. The slave
program pin (SP) must be at a "low" level for a slave ( and
then the cascade lines are inputs) and at a "high" level for a
master (and then the cascade lines are outputs).
For reading the IMR, a WR pulse is not necessary to
preceed the RD. The output data bus will contain the IMR
whenever RD is active and AO = 1.
Polling overrides status read when P = 1, EElS = 1 in
OCW3.
INST.
NO.
ICW, A
ICW1 B
ICW' C
ICW1D
ICW'
AO
07
06
0
0
0
0
1
.,
AS
A5
AS
A5
ICW3M
ICW3S
OCWl
OCW2E
10
0'
04
03
02
1
1
A7 A6 A5 1
0
A7 AS A5 1
0
0
A1S A,4 Al3 Al2 All AIO
57
58 55 54 53 52
0
52
0
0
0
0
M7 M6 M' M4 M3 M,
0
0
0
0
1
0
A7
01
00
OPERATION DESCRIPTION
Byte' 100tlahzatlon, format = 4,51ngle.
0
A9
0
0
0
0
A8
51
51
SO
SO
0
0
1
.,
0
0
0
1
0
0
L2
L1
LO
OCW2RE
0
1
0
1
0
0
0
0
0
0
0
L2
L1
LO
0
0
0
0
0
0
0
1
L2
L1
LO
0
0
0
1
1
0
0
0
0
1
0
0
1
0
12
OCW2RSE
0
1
OCW2RS
0
1
14
15
16
OCW3P
17
OCW3SM
18
OCW3 RSM
OCW3RIS
OCW3RR
-
1
1
0
0
0
1
l"them.ll1Irmode~pl"
0
0
1,,"slavemodeSP-D
24-I-dono,,,,,..
Figure 13. 8259 Instruction Set
12-119
0
0
0
No,.
Figure 12. Cascading the 8259
0
OCW2SE
13
I
MO
Byte 1 rnltlahzatlon,format=4,notslngle
Bvtellnltlahzatlon,format~ 8, single
Byt91'nltlahzatlon.format=8.notsrngle.
Byta 2 InitializatIOn (Address No. 2)
By te31n1tlahzatl 0 n-millster,
Byta3 Inltlshzatlon-slave.
Load mask reg. read mask reg.
Non SpeCifIC EQI.
SpeCifiC EOI. L2, L1. LO code of ISFF
wbeTeset.
Rotate at EOI (Auto Mode).
Rotatest EOI (SpeclfiI;: Model. L2, Ll. LO,
cocle of III.. to be reset ~nd selectedu
bottomprronty.
L2, Ll, LOcode of bottom prrorrty lloe.
Poll mode.
Read ISregrlter.
Read requests register.
Set sp8C1at mask mode.
Re&81spacr.lmaskmode.
8259/8259·5
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias . . . . . . .. O· C to 70· C
Storage Temperature ............. , -65· C to +150" C
Voltage On Any Pin
With Respectto Ground .............. -0.5 V to +7 V
Power Dissipation ........................... 1 Watt
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
condWons above those indicated in the operational sections of this
specification is not Implied.
D.C. CHARACTERISTICS
ITA = O°Cto 70°C; Vee = 5V ±5%1
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-.5
.8
V
VIH
Input High Voltage
2.0
Vee+·5V
V
VOL
Output Low Voltage
.45
V
VOH
Output High Voltage
VOH-INT
Interrupt Output High Voltage
IlL
IOL = 2 rnA
2.4
V
IOH ='-400 p.A
2.4
V
IOH = -400 p.A
3.5
V
Input Leakage Current
IILIIRO.7)
TEST CONDITIONS
for IRo.7
Input Leakage Current
for Other Inputs
IOH = -50 p.A
-300
p.A
VIN = OV
10
p.A
VIN = Vee
10
p.A
VIN = Vee to OV
VOUT = 0.45V to Vee
IOFL
Output Float Lea kage
±10
p.A
Icc
Vee Supply Current
100
rnA
CAPACITANCE
TA = 25°C; Vee = GND = ov
MIN.
TYP.
TEST CONDITIONS
SYMBOL
PARAMETER
MAX.
UNIT
CIN
Input Capacitance
10
pF
fc = 1 MHz
ClIO
I/O Capacitance
20
pF
Unmeasured pins returned to Vss
12-120
8259/8259·5
A.C. CHARACTERISTICS
(TA = oOe to 70°C; VCC = +5V ±5%. GND = OV)
Bus Parameters
Read:
8259-5
8259
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
MAX.
UNIT
tAR
eS/Ao Stable Before RD or INTA
50
50
ns
tRA
eS/Ao Stable After RD or INTA
5
30
ns
tAR
RD Pulse Width
420
300
tRD
Data Valid From RD/INTA[1]
tDF
Data Float After RD/INTA
ns
300
20
200
20
MAX.
MIN.
200
ns
100
ns
MAX.
UNIT
Write:
8259-5
8259
SYMBOL
PARAMETER
MIN.
tAW
Ao Stable Before WR
50
50
ns
tWA
Ao Stable After WR
20
30
ns
tww
WR Pulse Width
400
300
ns
tDW
Data Valid to WR (T.E.)
300
250
ns
tWD
Data Valid After WR
40
30
ns
Other Timings:
8259
SYMBOL
Note 1:
PARAMETER
MIN.
tlW
Width of Interrupt Request Pulse
tiNT
INT
tiC
Cascade Line Stable After INTA
t
After IR
t
t
8259-5
MAX.
MIN.
ns
400
350
ns
400
400
ns
Input Waveforms for A.C. Tests
•
_0
>
TEST POINTS
0.45 _ _ _J
12-121
UNIT
100
8259: CL = 1OOpF, 8259-5: CL = 150pF.
2.4---"",X 2,.28
MAX.
100
<::X__
8259/8259·5
WAVEFORMS
Read Timing
ADDRESS BUS__
Write Timing
-J·~
______
~
____
~I~
______
ADD~ESSBWS
--~1~------~~~'~----
DATA BUS
----------~1~r---+---~----
\\\\\S
Other Timing
IR
INT
¥
F..----------.
y-
\~
________
INTA
DB
Note: Interrupt Request must remain "HIGH" (at least) until leading edge of first INTA.
Read Status/Poll Mode
~~~______~I
\
WFi-------,
I
",. :wmd ~:~",,/~,
12·122
inter
8271
", -'d'
PROGRAMMABLE FLOPPY DISK CONTROLLER':,"
Read/Write Head
• Automatic
Positioning and Verification
• Internal CRC Generation and Checking
Programmable Step Rate, Settle-Time,
• Head
Load Time, Head Unload Index
• Supports Standard or Mini-Floppy
Drives
IBM 3740 Soft Sectored Format
• Compatible
• Programmable Record Lengths
• Multi-Sector Capability
Maintains Dual Drives with Minimum
• Software
Overhead Expandable to 4
Drives
Count
Fully MCS-80 and MCS-85 Compatible
•
• Single + 5V Supply
• 40-Pin Package
The Intel@ 8271 Programmable Floppy Disk Controller (FDC) is an LSI component designed to interface one to four
floppy disk drives to an 8-bit microcomputer system. Its powerful control functions minimize both hardware and software overhead normally associated with floppy disk controllers.
BLOCK DIAGRAM
PIN CONFIGURATION
FAULTRESET/OPO
Vee
lOW CURRENT
SELECT 0
4 MHz elK
LOAD HEAD
RESET
DIRECTION
READY 1
SEEK/STEP
SELECT 1
WR ENBLE
OACK
INDEX
iiii
WR"PRciTffi
REA5Vo
WR
TRKO
ORO
INT
C5DNlToPi
DBO
WR DATA
OBl
OB2
FAUi:T
UNsEP"5AfA
OB3
DATA WINDOW
PLO/S8
OBS
Cs
OBS
PlOC
A,
GNO
Ao
SELECT 1,0
.AULTI'I!SETIOf'O
RESET
.,....
....... ,0
..".
:1i~NC
l!r
OATA IUS IBI DIRECTIONAL)
CLOCK tNPUT (TTL)
'AU," T IIUETIOI'TIONAL OUTPUT
CHIP RESET
'LOISS
DATAWINbDW
UNIEPDATA
fAULi'"
- - - DATA WINDOW
ORO
DRIVE
INTERFACE
CONTROLLER
SELECT 0
SELECT 1
WR ENABLE
LOAD HEAD
SEEK/STEP
DIRECTION
LOW CURRENT
FAULT RESET/OPO
RESET
UNUPARATEODATA
Os - - - - - - '
READV1,O
OMA ACKIKIWLlEDOE
READ DATA INSYNC
Ctl.PULleT
IN-r:ERNAl
DATA BUS
SEEK/STE,
DIRECTION
PlO/SS
DACK - - - - - ,
DMAREQUEST
REQ.STERSELECT
L-tc:==_____
------,
INT
PIN NAMES
:!_OIlQ
INTERFACE
CONTROLLER
1:>----- RDOATA
OBO
DB7
\ - - - - - WROATA
SERIAL
WRITEENABl£
SEEt of
many of the control tasks associated with implementing a
floppy disk interface. The FDC supports a variety of high
level instructions which allow the user to store and retrieve
data on a floppy disk without dealing with the low level
details of disk operation.
In addition to the standard read/write commands, a scan
command is supported. The scan command allows the
user program to specify a data pattern and instructs the
FDC to search for that pattern on a track. Any application
that is required to search the disk for information (such as
point of sale price lookup, disk directory search, etc.), may
use the scan command to reduce the CPU overhead. Once
the scan operation is initiated, no CPU intervention is
required.
Pin
Name
0
Composite write data.
Unseparated (27)
Data
This input is the unseparated data
and clocks.
Data Window (26)
This is adata window established
by a single-shot or phase-locked
oscillator data separator.
INSYNC
The interrupt signal indicates that
the 8271 requires service
These two lines are CPU Interface Register select lines.
12·125
(23)
0
This line is high when 8271 has
attained input data synchronization, by detecting 2 bytes of
zeros followed by an expected
Address Mark. It will stay high
until the end of the ID or data
field
8271
CPU Interface Description
This interface minimizes CPU involvement by supporting
a set of high level commands and both OMA and non-OMA
type data transfers and by providing hierarchical status
information regarding the result of command execution.
The CPU utilizes the control interface (see the Block
diagram) to specify the FOC commands and to determine
the result of an executed command. This interface is
supported by five Registers which are addressed by the
CPU via the A" Ao, RO and WR signals. If an 8080 based
system is used, the RO and WR signals can be driven by
the 8228's I/OR and I/OW signals. The registers are
defined as follows:
Command Register
The CPU loads an appropriate command into the
Command Register which has the following format:
A,
Ao
07
06 05 04 OJ
I 0 I0 I
02 0,
Do
I I I
' - - - - - - - COMMAND OPCODE
SURFACE/DRIVE
(SELECT 0, 1)
Figure 2. 8271 Block Diagram Showing CPU Interface
Functions
Parameter Register
Accepts parameters of commands that require further
description; up to five parameters may be required,
example:
A,
Ao
01 06
05 04
03
02 0,
Status Register
Reflects the state of the FOC.
Do
I0 I' I
I I I I0 I0 I
I0 I0 I
~.---~---~
IIII
" - - - - - - - TRACK ADDRESS 0-255
.
Result Register
'-OO'.~M"",OO"
1" INTERRUPT REQUEST
1 '" RESULT REGISTER FULL
1 '" PARAMETER REGISTER FULL
The Result Register is used to supply the outcome of FOC
command execution (such as a good/bad completion) to
the CPU. The standard Result byte format is:
Al
Ao
I 0 I'
07
06
0
I0 I
ITi L
Os 04
03
02
I I
0,
~--------
1 = COMMAND REGISTER fULL
~----------1
'" COMMAND BUSY
Test Mode
Do
I0 I
Allows the 8271 to be reset by the program.
INT (Interrupt Line)
L::== ::::~::::: ~:::
,,,=,,
DELETED DATA FOUND
Another element of the control interface is the Interrupt
line (INT), This line is used to signal the CPU that an FOC
operation has been completed. It remains active until the
result register is read.
' - - - - - - - - - - - - N O T useD'" 00
12-126
8271
DMA Operation
Disk Drive Interface
The 8271 can transfer data in either DMA or non DMA
mode. The data transfer rate of a floppy disk drive is high
enough (one byte every 32 usec) to justify DMA transfer.
In DMA mode the elements of the DMA interface are:
The 8271 disk drive interface supports the high level
command structure described in the Command Description section. The 8271 maintains the location of bad tracks
and the current track location for two drives. However,
with minor software support, this interface can support
four drives by expanding the two drive select lines (select
0, select 1) with the addition of minimal support hardware.
ORO: DMA Request:
The DMA request signal is used to request a transfer of
data between the 8271 and memory.
DACK: DMA Acknowledge:
The DMA acknowledge signal notifies the 8271 that a DMA
cycle has been granted.
The FDC Disk Drive Interface has the following major
functions.
READ FUNCTIONS
RD, WR: Read, Write
The read and write signals are used to specify the
direction of the data transfer.
Utilize the user supplied data window to obtain the clock
and data patterns from the unseparated read data.
DMA transfers require the use of a DMA controller such as
the Intel®8257. The function of the DMA controller is to
provide sequential addresses and timing for the transfer
at a starting address determined by the CPU. Counting of
data block lengths is performed by the FDC.
Compute and verify the ID and data field CRCs.
To request a DMA transfer, the FDC raises ORO. DACK
and RD enable DMA data onto the bus (independently of
CHIP SELECT). DACK and WR transfer DMA data to the
FDC. If a data transfer request (read or write) is not
serviced within 31 p'sec, the command is cancelled, a late
DMA status is set, and an interrupt is generated. In DMA
mode, an interrupt is generated at the completion of the
data block transfer.
Establish byte synchronization.
WRITE FUNCTIONS
Encode composite write data.
Compute the ID and data field CRCs and append them to
their respective fields.
CONTROL FUNCTIONS
Generate the programmed step rate, head load time, head
settling time, head unload delay, and monitor drive
functions.
When configured to transfer data in non-OM A mode, the
CPU must pass data to the FDC in response to the nonDMA data requests indicated by the status word. The data
is passed to and from the chip by asserting the DACK and
the RD or WR signals.
DATA
SEPARATOR
J-
DATA WINDOW
.
:::....
:::...
UNSEPARATED DATA
WRITE DATA
WRITE ENABLE
SEEK/STEP
DIRECTION
COUNT/OPI
.......
8271
FDC
.
::.....
...
LOAD HEAD
INDEX
TRACK 0
DUAL
FLOPPY
DISK
DRIVE
SELECTO
SELECT 1
LOW CURRENT
WAITE PAOTECT
WRITE FAUCi'
....
...
WRITE FAULT RESET/OPO
READY 0
READY 1
NOTE:
Figure 3. 8271 Block Diagram Showing Disk Interface
Functions
INPUTS TO CHIP MAY REOUIRE RECEIVERS
(AT LEAST PUll UP/DOWN PAl AS).
Figure 4. 8271 Disk Drive Interface
12·127
I
8271
Data Separation
The 8271 needs only a data window to separate the data
from the composite read data, as well as detect missing
clocks in the Address Marks.
The window generation logic may be implemented using
either a single shot or a phase-locked oscillator.
Figure 9. PLO Data Window Timing
Single-Shot Separator
Dllk Drive Control Interrace
The single shot approach is the lowest cost solution.
The FDC samples the value of Data Window on the leading
edge of Unseparated Data and determines whether the
delay from the previous pulse was a half or full bit-cell
(high input = full bit-cell, low input = half bit-ceill.
PLO/SS should be tied to Ground.
The disk drive control interface performs the high level
and programmable flexible disk drive operations. It
customizes many varied drive performance parameters
such as the step rate, settle time, head load time, and head
unload index count. The following is the description of the
control intertace.
Write Enable
The Write Enable controls the read write functions of a
flexible disk drive. When Write Enable is a logical one, it
enables the drive write electronics to pass current through
the Read/Write head. When Write Enable is a logical zero
the drive Write circuitry is disabled and the Read/Write
head detects the magnetic flux transitions recorded on a
diskette. The write current turn-on is as follows.
UNSEPARATED
OATA
'FOR STANDARD DRIVE
Figure 6, Single,Shot Data Separator Block Diagram
WAITEDAT~_~ _ _ ~
--I I--'WE
WRITEE~
I-'WE-J
L-
UNSEPARATED
DATA
Figure 10. Write Enable Timing
Seek Control
Figure 7, Single·Shot Data Window Timing
Phale-Locked Olcillator Separator
The FOe samples the value of Data Window on the leading
edge of Unseparated Data and determines whether the
pulse represents a Clock or Data Pulse.
PLO/SS should be tied to Vee (+5VI.
Seek Control is accomplished by Seek/Step, Direction,
and Count pins and can be implemented two ways to
provide maximum flexibility in the subsystem design. One
instance can be when the programmed step rate is not
equal to zero; in this the 8271 uses the Seek/Step and
Direction pins (the Seek/Step pin becomes a Step pinl.
Programmable Step timing parameters are shown.
Another instance is when the programmable step rate is
equal to zero; in which case the8271 will hold the seek line
high until the appropriate number of user-supplied step
pulses have been counted on the count input pin.
I
'DIRECTION
1I--
--I
tos
SEEKIST~ ___
f- ts ---.j
~
'so
---I""L----j f-.- tps
tps""tOS=tSD "" 1 OILS
+5V
1msO;;;; tS';;;: 255ms
'WHEN DIRECTION PIN IS HIGH THE HEAD MOVES TOWARD THE SPINDLE.
Figure 8. PLO Data Separator Block Diagram
Figure 11. Seek Timing
12-128
8271
OIRECTIOS
1
SEEK/ST_E_P_ _...
--l
tpi ;;,
J--.SC
n
COUNT
n
0.5115
n
- - - - - . J L..-I L.- - - - - - - l
I..-tc~tPc
tL.--Figure 15. Index Timing
lAST COUNT
tDS:::tso"'tcS=10~s
tsC>l~s
Select 1, 0
tpc o~ 20~s
tc:"..lms
Only one drive may be selected at a time. The
Input/Output pins that must be externally qualified with
select 0 and select 1 are:
Figure 12. SeekiStep/Count Timing
Unseparated Data
Data Window
Write Enable
Seek/Step
Count/User Optional Input
Load Head
Track 0
Low Current
Write Protect
Write Fault
Fault Reset/User Optional Output
Index
Head Settle
The 8271 allows the head settle time to be programmed
from 0 to 255 ms, in increments of 1 ms.
seEK OR LAST STEP
WRITE/READ ENABLE
__. . .1 1_....
.tsw----..J
r-
------',---o "ttsw ,,;; 255ms
'THE RfW HEAD IS ASSUMED LOADED.
Figure 13. Head Settle Timing
Low Current
Load Head
This output pin is active whenever the physical track
location of the selected drive is greater than 43. Gener·
ally this signal may be used to enable compensation for
lower velocity while recording on the inner tracks by
adjusting the current in a Read/Write head.
The Load Head output pin must become active priorto any
read or write operation and remain active for a
programmable number (0-14) of disk revolutions after
termination of each operation. When frequent disk
accesses are made, the Head Load settling delay is
eliminated.
1
LOAD HEAD _ _ _ _ _ _ _ _ _ _...
EARLIEST WRITE ENABLE
OR INTERNAL READ DATA
tlW-! r___
---'r-----
Figure 14. Head Load to Read/Write Timing
Index
The Index input is used to determine "Sector not found"
status, to initiate format track/read 10 commands and
head unload Index and Count operations.
Track 0
This input pin indicates that the diskette is at track O.
During any seek operation, the stepping out of the
actuator will cease when the track 0 pin becomes active.
Write Protect
The 8271 will not write to a disk when this input pin is
active and will interrupt the CPU if a Write attempt is made.
Operations marked check Write Protect will be aborted if
Write Protect line is active.
This signal normally comes from a sensor which detects
the presence or absence of a Write Protect hole in a
diskette envelope.
Write Fault and Write Fault Relet
Write Fault input is normally latched by the drive and
indicates any condition which could endanger data
integrity if writing is attempted. The 8271 interrupts the
CPU anytime Write Fault is detected during an operation
and will immediately reset the Write Enable, Seek/Step,
Direction, and Low CU.rrent signals. The Write Fault is
reset through the user specified optional output pin.
Ready 1, 0
These two pins indicate the functional status of the
flexible disk drives. Whenever an operation is attempted
on a drive which is not ready, an interrupt is generated.
Whenever a drive becomes not ready, this condition is
latched by the 8271. The Not Ready condition is reset by
the execution of a Read Drive Status command.
12·129
8271
PRINCIPLES OF OPERATION
As an 8080 peripheral device, the 8271 accepts commands
from the CPU, executes them and provides a RESULT
back to the 8080 CPU at the end of the execution. The
communication with the CPU is established by the
activation of CS, RD, WR. The A1. Ao select the
appropriate registers on the chip:
RD
Al
Ao
CS
a
a
a
Status Reg
Result Reg
1
1
1
a
-
1
CS
WR
In the Result Phase, the CPU Reads the Status Register
which provides the following information:
COMMAND BUSY
COMMAND REG FUll
PARAMETER REG FUll
Bit 7: Command Busy
Command Reg
Parameter Reg
Test Mode
-
The command busy bit is set on writing to the command
port. Whenever the FDC is busy processing a command
the command busy bit is set to a one. This bit is set to zero
after the command is completed.
Bit 6: Command Full
The FDC chip operation is composed of the following
sequence of events.
8080 WA ITES THE COMMAND AND PARAMETERS INTO
THE 8271 COMMAND AND PARAMETER REGISTERS.
THE 8271 IS ON ITS OWN TO CARRY OUT THE COMMANDS.
THE 8271 SIGNALS THE CPU THAT THE EXECUTION HAS
FINISHED. THE CPU WILL PERFORM A READ OPERATION
OF ONE OR MORE OF THE REGISTERS.
The command full bit is set on writing to the command
buffer and cleared when the FDC begins processing the
command.
Bit 5: Parameter Full
This bit indicates the state of a parameter buffer. This
bit is set when a parameter is written to the FOC and
reset after the FOC has accepted the parameter.
The Command Phase
The software writes a command to the command register.
As a function of the command issued, from zero to five
parameters are written to the parameter register. Refer to
diagram showing a flow chart of the command phase.
Note that the flOw chart shows that a command may not be
issued if the FDC status register indicates that the device
is busy. Issuing a command while another command is in
progress is illegal. The flow chart also shows a parameter
buffer full check. The FDC status indicates the state of the
parameter buffer. If a parameter is issued while the
parameter buffer ,is full, the previous parameter will be
over written and lost.
YES
The Execution Phase
I
NO
During the execution phase the operation specified
during the command phase is performed, During. this
phase there is no CPU involvement if the system utilizes
DMA for the data transfers. The execution phase of each
command is discussed within the detailed command
descriptions. The following table summarizes many of the
basic execution phase characteristics.
END OF COMMAND PHASE
YES
The Result Phase
During the Result Phase, the FDC chip notified the CPU of
the outcome of the command execution. This phase may
be initiated by:
1. The successful completion of an operation.
2. An error detected during an operation.
Figure 5. Command Phase Sequence
12·130
8271
Bit 4: Result Full
(02-01)
This bit indicates the state of the result buffer. This bit is
set when the FDC has a result byte and reset after the
result byte is read by the CPU. The data in the result buffer
is valid only after the FDC has completed a command.
Reading the result buffer while a command is in progress
will yield no useful information.
Completion Code: The completion code field provides
more detailed information about the completion type.
Bit 3: Interrupt Request
This bit reflects the state of the FDC INT pin.
Bit 2: Non-DMA Data Request
When the FDC is utilized without a DMA controller, this bit
is used to indicate FDC data requests.
Bits 1 and 0
Not used.
After reading the Status Register, the CPU then Reads the
Result Register for more information.
The Result Register
The standard result byte format is:
T'
I 'Loo,"~,~,
::::~::::: ~~::
' - - - - - - - - - - - - - NOT USED = 00
(05)
Deleted Data Found: This bit is set when deleted data is
encountered during a transaction.
11
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Event
Good Completion
Scan Met Equal
Scan Met Not Equal
Clock Error
Late DMA
ID CRC Error
Data CRC Error
Drive not ready
Write Protect
Recalibrate Error
Write Fault
Record Not Found
The Completion Type/Completion Code interface supplies the greatest detail about each type of completion.
This interface is used when detailed information about the
transaction completion is required.
(04-03)
00
01
10
Completion
Code
It is important to note the hierarchical structure of the
result byte. In very simple systems where only a GO-NO
GO result is required the user may simply branch on a zero
result (a zero result is a good completion). The next level of
complexity is at the completion type interface. The
completion type supplies enough information so that the
software may distinguish between fatal and non-fatal
errors. If a completion type 01 occurs, ten retries should
be performed before the error is considered unrecoverable.
I0 I
' - - - - - - - - - - - DELETED DATA FOUND
Completion
Type
Completion
Type
Event
Good Completion - No Error
System Error - recoverable errors
Operator intervention probably required
for recovery
Command/Drive Error - either a program
error or drive hardware failure.
12·131
8271
EXECUTION PHASE BASIC CHARACTERISTICS
The following table summarizes the various commands
with corresponding execution phase characteristics.
2
COMMANDS
Deleted
Data
3
4
5
6
Head
Ready
Write!
Protect
Seek
Seek
Check
7
8
Resun
Completion
Interrupt
SCAN DATA
SKIP
LOAD
j
x
YES
YES
YES
YES
SCAN DATA AND
DEL DATA
WRITE DATA
XFER
LOAD
j
x
YES
YES
YES
YES
x
LOAD
j
j
YES
YES
YES
YES
WRITE DEL DATA
x
LOAD
j
j
YES
YES
YES
YES
READ DATA
SKIP
LOAD
j
x
YES
YES
READ DATA AND
DEL DATA
READID
XFER
LOAD
j
x
YES
YES
YES
YES
YES
YES
x
XFER
LOAD
j
x
YES
NO
YES
YES
LOAD
j
x
YES
YES
YES
YES
x
LOAD
j
j
YES
NO
YES
x
LOAD
Y
x
x
x
YES
NO
YES
YES
'YES
x
x
NO
NO
NO
NO
YES
NO
NO
x
x
NO
NO
NO
NO
x
x
NO
NO
NO
NO
VERIFY DATA AND
DEL DATA
FORMAT TRACK
SEEK
READ DRIVE STAT
SPECIFY
x
x
RESET
x
R/W SP REGISTERS
x
Note: 1. "x"
~
DON'T CARE
2. "j"
UNLOAD
~
check
3. "-"
~
No change
NO
4. "y" - Check at end of operation
Table 1. Execution Phase Basic Characteristics
Explanation of the execution phase characteristics table.
1. Deleted Data Processing
4. Write Protect
If deleted data is encountered during an operation that
is marked skip in the table, the deleted data record is
not transferred into memory, but the record is counted.
For example, if the command and parameters specify a
read of five records and one of the records was written
with a deleted data mark, four records are transferred
to memory. The deleted data flag is set in the result
byte. However, if the operation is marked transfer, all
data is transferred to memory regardless of the type of
data mark.
The operations that are marked check Write Protect are
immediately aborted if Write Protect line is active atthe
beginning of an operation.
5. Seek
Many of the 8271 commands cause a seek to the
desired track. A current track register is maintained for
each drive or surface.
6. Seek Check
2. Head
The Head column in the table specifies whether the
Read/Write head will be loaded or not. If the table
specifies load, the head is loaded after it is positioned
over the track. The head loaded by a command remains
loaded until the user specified number of index pulses
have occurred.
3. Ready
The Ready column indicates if the ready line (Ready
1, Ready 0) associated with the selected drive is
checked. A not ready state is latched by the 8271 until the user executes a read status command.
12-132
Operations that perform Seek Check verify that
selected data in the ID field is correct before the 8271
accesses the data field.
8271
DETAILED COMMAND DESCRIPTION
Parameter 2:
Bad track address number 2 (Physical Address),
Many of the interface characteristics of the FOC are
specified by the systems software. Prior to initiating any
drive operation command, the software must execute the
specify command. There are two types of specify
commands selectable by the parameter issued.
First Parameter
Specify Type
OOH
10H
.18H
Initial ization
Load bad Tracks Surface '0'
Load bad Tracks Surface '1'
Parameter 3:
Current track address (Physical Address),
Conditions:
1. Bad track number one must be numerically less than
bad track number two.
2. If no bad tracks are present, set the parameter to FFH.
Reset Command
Specify Command
The Specify command is used prior to performing any
diskette operation (including formatting of a diskette) to
define the drive's inherent operating characteristics and
also is used following a formatting operation or
installation of another diskette to define the locations of
bad tracks. Since the Specify command only loads
internal registers within the 8271 and does not involve an
actual diskette operation, command processing is limited
to only Command Phase. Note that once the operating
characteristics and bad tracks have been specified for
a given drive and diskette, redefining these values need
only be done if a diskette with unique bad tracks is to be
used or if the system is powered down.
I
I
I
I
I
I
0
0
o
PAR
0
1
o
PAR
0
1
STEP RATE""
PAR
0
1
HEAD SETTLING TIMP
PAR
0
1
0
o
1
0
1
o
I
I
o
1
I
I
1
1
I
I
o
o
I
I
o
I
1
I
1
PAR
0
1
o
I
o
I
o
I
1
PAR
0
1
BAD TRACK NO.1
PAR
0
1
BAD TRACK NO.2
PAR
0
1
CURRENT TRACK
I
I
o
1/0
I
I
1
o
I
I
1
0
1
0
1
0
1
0
l' 1
1. The drive control signals are forced low.
2. An in-progress command is aborted.
3. The FOC status register flags are cleared.
4. The FOC enters an idle state until the next command is
issued.
Special Drive Commands
The seek command moves the head to the specified track
without loading the head or verifying the track.
The seek operation uses the specified bad tracks to
compute the physical track address. This feature insures
that the seek operation positions the head over the correct
track.
When a seek to track zero is specified (bad track registers
are not used), the FOC steps the head until the track 00
signal is detected.
If the track 00 signal is not detected within (FF)H steps, a
track 0 not found error status is returned.
A seek to track zero is used to position the read/write head
when the current head position is unknown (such as after
a power up).
PAR'L-__
I
0
Function: The Reset command emulates the action of the
reset pin. It is issued by outputting a one followed by a
zero to the Test Mode Register.
Load Bad Tracks
o
1
Command Seek Function
Parameter 0 - OOH = Select Specify Initialization.
Parameter 1 - 07-00 = Step Rate (0-255ms in 1 ms steps)'
Parameter 2 - 07-00 = Head Settling Time (0-255ms in 1
ms steps)'
Parameter 3 - 07-04 ~ Index Count - Specifies the
number of Revolutions (0-141 which are to occur before
the FOC automatically unloads the R/W head. If 15 is
specified, the head remains loaded.
03-00 = Head Load Time (0-60ms in steps of 4ms),
0
0
1
'Note: Mini-floppy parameters are doubled.
0
1
1
HEAD UNLOAD"
CMD
0
DO
1 HEAD LOAD TIME"
INDEX CNT BEFORE
1
0
The special drive commands are used to explicitly
position the drive read/write head or to interrogate the
drive status.
Initialization:
CMD
::: l ' 1
o
I
1
o
I
0
L-~
____________________________
~
Seek operations are not verified. A subsequent read or
write operation must be performed to determine if the
correct track is located.
Read Drive Status Command
At
CMD
Ao
07
06
I I I S~L I S~L I
0
0
05
04
03
02
0,
1
0
I I
1
0
1
Do
I
0 ]
Parameter 0: 10H = Load Su~face zero bad tracks
18H = Load Surface one bad track
Parameter 1:
Bad track address number 1 (Physical Address),
IF A DRIVE NOT READY RESULT IS RETURNED, THE READ STATUS MUST
BE ISSUED TO CLEAR THE CONDITION.
12-133
,
I
. ...
8271
Read/Write Special Register
Data Processing Commands
This command is used to access special registers within
the 8271.
Command code:
3DH Read Special Register
3AH Write Special Register
For both commands, the first parameter is the register
address; for Write command a second parameter specifies
data to be written. Only the Read Special Register
command supplies the result.
128 byte single record format.
Ao
I S~L I COMMAND OPCODE
0
0
Si L
0
1
TRACK ADDR 0·255
0
1
SECTOR 0·255
Commands
Register Address
in Hex
Description
Opcode
See Scan Description
See Scan Description
See Scan Description
READ DATA
READ DATA AND DELETED DATA
WRITE DATA
WRITE DELETED DATA
VERIFY DATA AND DELETED DATA
17
See Description
Variable Length/Multi-Record
23
22
See Read Status
Scan Sector Number
Scan MSB of Count
Scan LSB of Count
06
Surface 0 Current Track
Surface 1 Current Track
12
1A
Mode Register
Drive Control Output Port
Drive Control Input Port
14
13
Comment
12
16
OA
OE
1E
See Description
Description
07
06
05
04
03
02
01
Do
1010101010101 ~
" 0 DMA MODE, '" 1 NON DMA
~
I S5 L I COMMAND OPCODE
0
0
si L
0
1
TRACK ADDR 0·255
0
1
SECTOR 0-255
0
1
LENGTH
Mode Register Write Parameter Format
0 DOUBLE, - 1 SINGLE ACTUATOR
I
NO. OF SECTORS
Blt87-2
D7-D5 of Parameter 2 determine the length of the disk
record.
Not used. Must be set to zero.
Bit 1
000
o0 1
010
o1 1
o0
o1
0
1 1
Double/Single Actuator: Selects single or double actuator
mode. If the single actuator mode is selected the FDC will
assume that the physical track location of both disks is
always the same. This mode facilitates control of a drive
which has a single actuator mechanism which moves two
heads.
Bit 0
Data Transfer Mode: This bit selects the data transfer
mode. If this bit is a zero the FDC operates in the DMA
mode (DMA RequesVACK). If this bit is a one the FDC
operates in non-DMA mode. When the FDC is operating in
DMA mode interrupts are generated at the completion of
commands. If the non-DMA mode is selected the FDC will
generate an interrupt for every data byte transferred.
Commands
READ DATA
READ DATA AND DELETED DATA
WRITE DATA
WRITE DELETED DATA
VERIFY DATA AND DELETED DATA
SCAN DATA
SCAN DATA AND DELETED DATA
Drive Control Output Port Format
I I I I I I I I I
I
L==
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
8192 Bytes
16,384 Bytes
Opcode
13
17
OB
OF
1F
00
04
Commands
WRITE ENABLE
Read Data, Read Data and Deleted Data.
SEEK/STEP
Function
DIRECTION
The read command transfers data from a specified disk
record or group of records to memory. The operation of
this command is outlined in execution phase table.
LOAD HEAD
LOW HEAD CURRENT
WRITE FAULT RESETI
OPTIONAL OUTPUT
Commands
SEL(CT G
Write Data, Write Deleted Data.
SELECT 1
Function
Each of these signals correspond to the chip pin of the
same name.
The write command transfers data from memory to a
specified disk record or group of records.
12-134
8271
Commands
Read Special Register
Verify Data and Deleted Data.
Parameter (Hex) Results
Function
The verify command is identical to the read data and
deleted data command except that the data is not
transferred to memory. This command is used to check
that a record or group of records have been written
correctly through verifying the CRC character.
06
Record number in which the scan condition was
met.
14
Count MSB - The MSB of the count is decremented every 128 characters.
13
Count LSB - The LSB of the count is set to 128
and decremented every time a character is
compared.
Scan
The Scan command is used to search fields within disk
records for a specified pattern. It compares a sector image
in memory with a sector or multiple sectors on disk.
A,
AD
D,
0
0
S;L
0
1
TRACK ADDR 0·255
0
1
SECTOR 0·255
0
1
LENGTH
0
1
SCAN TYPE
0
1
D,
I S~L I I
0
I
I
o
I
0
ISDAT~I
S.DELD
0
DO
I
Notes: 1. The character (from memory) (FF)H is not
compared.
2. The image in memory must be supplied to the
FDC multiple times during the scan operation.
Usually this will be performed through the use
of the 8257 DMA controller auto load mode.
0
Commands That Process Special Data
Read 10
NO. OF SECTORS
The Read I D command will transfer the specified number
of ID fields into memory (beginning with the first ID field
after Index>. The GRG character is cheeked but not
transferred.
STEP SIZE
FIELD LENGTH
D,
D2 = 0
D2 = 1
Command
°
°
°
°
Scan Data
Scan Data and Deleted Data
Parameters 0, 1, 2 are same as the Read Command
Parameter 3
07-D6:
OO-EQ
01-GE
10-LE
D5-DO:
I ndicate scan type
Scan for each character within the field length
equal to the corresponding character within
the disk sector.
Scan for each character within the disk sector
greater than or equal to the corresponding
character within the field length.
Scan for each character within the disk sector
less than or equal to corresponding character
within the field length.
Step Size: The Step Size field specifies the offset to the next record in a multi record scan. In
this case, the next record address is generated
by adding the Step Size to the current record
address.
Parameter 4, Field Length
The Field Length is the number of characters to be
included in each scan comparison group.
More detailed information about the completion of the
scan command may be obtained through the Read Special
Registers command discussed previously.
°,
,
,
S,EL
I
SgL
I°I I ' I
1
I'
0
I
0
1°1°
1
TRACK ADDR ESS
°1°1
0
1°1°1
NUMBER OF ID FIELDS
Format Track
A,
0
AD
D,
0
S~l
0
,
,
,
,
0
1
0
0
0
D,
I
SgL
I
1
I
o
I
0
I
o
I
'
Do
I
'
TRACK ADDRESS
GAP3SlZEMINUS6
LENGTH
I
NO. OF SECTORS/TRACK
GAP5SIZEMINUS6
GAP' SIZEMINUS6
The format command can be used to initialize a disk
track compatible with the IBM 3740 format. A Shugart
"IBM Type" mini-floppy format may also be generated.
When a format track command is issued, the user must
supply a list of the ID fields in memory. As the command is
processed, the ID fields (cylinder address, head address,
sector address, record length) are read from memory and
transferred to the disk. Parameter 2, D7-Ds specify record
length; bits coded the same as in Read Data Command.
12-135
8271
The following is the gap size and description summary:
Deleted Data Address Mark
Gap
Gap
Gap
Gap
Gap
The Deleted Data Address Mark byte is located at the
beginning of each deleted Data Field on the diskette.
1
2
3
4
5
Programmable
17 Bytes
Programmable
Variable
Programmable
Address Mark Summary
The last six bytes of gaps 1,2,3 and 5 are [00] H , all other
bytes in the gaps are [FF] H . The Gaps 1,3,5 counts
specified by the user are the counts of the number of bytes
of [FF]H . Gap 4 is written until the leading edge of the
index pulse. If a Gap 5 size of zero is specified, the Index
Mark is not written.
Clock
Pattern
Data
Pattern
D7
C7
C7
C7
C7
FC
FE
FB
F8
FE
Index Address Mark
ID Address Mark
Data Address Mark
Deleted Data Address Mark
Bad Track ID Address Mark
IBM Format Implementation Summary
10 Field
Track Format
MARK
The disk has 77 tracks, numbered physically from 00 to 76,
with track 00 being the outermost track. There are
logically 75 data tracks and two alternate tracks. Any two
tracks may be initialized as bad tracks. The data tracks are
numbered logically in sequence from 00 to 74, skipping
over bad tracks (alternate tracks replace bad tracks).
Note: In IBM Tormat track 00 cannot be a bad track.
C
H
R
N
CRC
CRC
C ~ Cylinder (Track) Address, 00-74
H ~ Head Address
R ~ Record (Sector) Address, 01-26
N~ Record (Sector) Length, 00-02
Note: Sector Length ~ 128 x (2 N _1)
CRC ~ 16 Bit CRC Character (See Below)
Sector Format
Eack track is divided into 26,15, or 8 sectors of 128, 256, or
512 bytes length respectively. The first sector is
numbered 01, and is physically the first sector after the
physical index mark. The logical sequence of the
remaining sectors may be nonsequential physically. The
location of these is determined at initialization by CPU
software.
Data Field
I
Each sector consists of an ID field and a data field. All
fields are separated by gaps. The beginning of each field
is indicated by 6 bytes of (OOlH followed by one byte mark.
MARK
I
DATA
CRe
eRe
Data is 128, 256, or 512 bytes long.
Note:
Address Marks
Address Marks are unique bit patterns one byte in length
which are used to identify the beginning of ID and Data
fields and to synchronize the deserializing circuitry with
the firstbyte of each field. Address Mark bytes are unique
from all other data bytes in that certain bit cells do not
contain a clock bit (all other data bytes have clock bits in
every bit cell.) There are four different types of Address
Marks used. Each of these is used to identify different
types of fields.
All marks, data, 10 characters and eRC
characters are recorded and read most
significant bit first.
eRC Character
The 16-bit CRC character is generated using the
generator polynomial X16 + X12 + X5 + 1, normally
initialized to tFFlH. It is generated including all characters
except the CRC in the ID or data field, including the data
(not the clocksl in the mark. It is recorded and read most
significant bit first.
"Index Address Mark
Bad Track Format
The Index Address Mark is located at the beginning of
each track and is a fixed number of bytes in front of the
first record.
The Bad Track Format is the same as the good track
format except that the bad track ID field is initialized as
follows:
10 Address Mark
C = H = R = N = (FFlH
The ID Address Mark byte is located at the beginning of
each I D field on the diskette.
Data Address Mark
The Data Address Mark byte is located at the beginning of
each non-deleted Data Field on the diskette.
12-136
8271
INDEX
DATA
FIELD
GAP 2
INDEX ADDRESS MARK
GAPS
GAP 1:
POST INDEX GAP
I'
'I
SYNC
GAP 2:
I
POST 10 FIELD GAP
I"
'I
-rL -_ _ _ _
WRITE GATE TURN·ON FOR UPDATE OF NEXT
DATA FIELD.
NOTE: THE WRITE GATE TURN-ON SHOULD BE TIMED
TO WITHIN ± '" 1 BIT BY COUNTING THE BYTES
IN THE GAP UNTIL 1 BYTE BEFORE THE
TURN..()N.
GAP 3:
POST DATA FIELD GAP
I"
L
WRITE GATE TURN.QFF FROM UPDATE OF PREVIOUS DATA FIELD.
NOTE: IBM FORMAT REQUIRES AT LEAST 2 BINARY "1" BITS AS A DATA FIELD POSTAMBLE.
2-81T8
GAP 4:
FINAL GAP
I"
GAP 5:
'I
INITIAL GAP
I"
'I
SYNC
Figure 6. Track Format
12·137
I
I,
..
8271
Mini-floppy Disk Format
Data Format
Data is written (general casel in the following manner:
Clock
Clock
Data "0"
TF
TH
Data "1"
The mini-floppy disk format display differs from the
standard disk format in the following ways:
Missing
Clock
Clock
1. Gap 5 and the Index Address mark have been
eliminated.
2. There are fewer sectors/track.
Data "'"
Data "'"
;; Full Bit Time'" Nominally 4~s
'" Half Bit Time;; Nominally 2p.s
References
"The IBM Diskette for Standard Data Interchange", IBM
Document GA21-9182-0. "System 32", Chapter 8, IBM
Document GA21-9176-0.
Gaps
Gap 1 = 16 bytes of FF Hex followed by 6 bytes of zeros.
Gap 2 = 11 bytes of FF Hex followed by 6 bytes of zeros.
Gap 3 size is a function of the record size. For 128 byte
records Gap 3 = 27 bytes of FF Hex followed by 6
bytes of zeros.
Gap 4 is a final gap and is whatever is left over.
Data Track Gap Lengths
Datil Field
Lenglh (Byle.) Gap 1 Gap 2"
128
256
512
32
32
32
Gap 3" Gap 4"" GapS
17
17
17
33
48
274
197
46
46
46
The I D field format marks, and CRC used are the same as
in the standard disk format.
'Nominal after data written.
"Nominal after initialization.
Notes:
1. L is the gap length in bytes.
2. SYNC consists of 6 bytes of (OOlH.
3. All other bytes in the gaps are (FFlH.
4. All gaps except Gap 4 are fixed at initialization. Gap 3
length is nominal after writing data.
I
\
I
MEMORIES
J
I
(
8080 SYSTEM BUS
/).
"
/"\.
DB0-7
A •• A,
MEMR
lOW
MEMW
lOR
CS
HRO
/ACK
DB0-7
RD
WR
CS
INT
"
7
DATAl
DATA
WINDOW
SEPARATOR
ORO
8257
DMA
CONTROLLER
UNSEPARATED DATA
DACK
Figure 7. 8271 System Diagram
8271
FDC
A
I
)
I
DRIVE
INTERFACE
"
LINE
7438
DRIVER
WRDATA
,...:
CONTROL OUT
I
)
CONTROL IN
v
(
8271
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
AmbientTemperatureUnderBias ........ O°Cto 50°C
Storage Temperature ............... -65° C to +150° C
Voltage on Any Pin With
Respect to G rou nd ..................... -0.5V to + 7V
Power Dissipation .......................... , 1 Watt
D.C. CHARACTERISTICS
TA = O°C to 50°C, Vee = +5.0V ±5%
Symbol
Min.
Max.
Unit
Input Low Voltage
-0.5
0.8
Volts
VIH
Input High Voftage
2.0
(Vee + 0.5)
Volts
VOL
Output Low Voltag.e
VOH
Output High Voltage
ilL
Input Load Current
±10
loz
Off-State Output Current
lee
Vee Supply Current
VIL
Parameter
0.45
Volts
Volts
2.4
Test Conditions
IOL=2.0mA
10H = -200",A
",A
VIN = Vee to OV
±10
",A
VOUT = Vee to OV
160
mA
CAPACITANCE
TA = 25°C; Vee
Symlilol
= GND = OV
Parameter
Min.
Max.
Unit
CIN
Input Capacitance
10
pF
te = 1MHz
CliO
I/O Capacitance
20
pF
Unmeasured Pins
Returned to GND
Typ.
12-139
Test Conditions
8271
A.C. CHARACTERISTICS
T A = 0° C to 50°C, VCC = +5.0V ±5%
Read Cycle
Symbol
Parameter
tAC
Select Setup to RQ
Min.
Max.
Unit
0
ns
0
ns
Test Conditions
tCA
Select Hold from RD
tAA
RD Pulse Width
tAD
Data Delay from Address
200
ns
tAD
Data Delay from RD
150
ns
Cl = 150pF
tDF
Output Float Delay
20
100
ns
Cl = 20pF for
Minimum; 150pF for
Maximum
Min.
Max.
Unit
ns
250
Write Cycle
Symbol
Parameter
tAC
Select Setup to WR
tCA
Select Hold from WR
tww
WR Pulse Width
tow
Data Setup to WR
150
ns
two
Data Hold from WR
-20
ns
0
ns
0
ns
250
ns
Test Conditions
DMA
Symbol
Parameter
Min.
Request Hold from WR or RD
(for Non-Burst Mode)
tco
Max.
Unit
150
ns
Max.
Unit
Test Conditions
Other Timing
Symbol
Parameter
t ASTW
Reset Pulse Width
Min.
10
Test Conditions
tCY
tr
Input Signal Rise Time
20
tf
Input Signal Fall Time
20
tASTS
Reset to First IOWR
2
ns
ns
tCY
tCY
Clock Period
250
See Note 3
tCl
Clock Low Period
Tas
See Note 2
tCH
Clock High Period
Tas
See Note 2
Notes:
1. All timing measurements are made at the following reference voltages unless specified otherwise:
Input "1" at 2.0V, "0" at O.BV
Output "1" at 2.0V, "0" at O.BV
2. To be specified
3. Standard Floppy: TCY= 250ns ± 0.4%
Mini-Floppy:
TCY= 500ns ± 0.4%
12·140
8271
WAVEFORMS
Read Waveforms
Write Waveforms
==x
DATA BUS
x~
____
---.JC~I--'=_~~,ow_'WW~-+-h-"~oJ==
DMA Waveforms
DRQ~
r "oJ
\~----r------------------------------
AD OR WR
---~
~---------------------------------
CHIP CLOCK
WRITE DATA
PW
PULSE WIDTH PW '" lev ± 30ns.
H(HALF BIT CELL) '" B tev
F(FULL BIT CELL) '" 16 tCY
tCY = 250ns + 0.4%
250ns ± 30ns
2.0 sec + 8ns
4.0 sec ± 16n5
tev '" 500ns t 0.4%
500ns ± 30ns
4.0[Jsec 116m
8.0[Jsec ± 32ns
Figure 18. Write Data
Figure 20. Single·Shot Data Separator
READ DATA
I
• tey
F(MINIMUM FULL BIT-CELL);;;' Btcv
H(MINIMUM HALF BIT -CELL) ;;. 4tcv
=
250n5
2.0,usec
1.0llsec
tCY = 500ns
4.0psec
2.0J-lsec
• Standard flexible disk drive timing .
•• Minifloppy timing.
Figure 19. Read Data
Figure 21. Data Separator
12·141
inter
8273
PROGRAMMABLE HOLC/SOLC PROTOCOL
CONTROLLER
• HDLC/SDLC Compatible
• Frame Level Commands
Full Duplex, Half Duplex, or Loop
• SDLC
Operation
• Programmable NRZI Encode/Decode
• N·Bit Reception Capability
Phase Locked Loop Clock
• Digital
Recovery
• Up to 64K Baud Transfers
Two User Programmable Modem
• Control
Ports
• Minimum CPU Overhead
• Fully Compatible with 8080/8085 CPUs
• Single + 5V Supply
FCS (CRC) Generation and
• Automatic
Checking
• 40·Pin Package
The Intel® 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the ISO/C·
CITT's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high performance
microcomputer systems such as the MCS·85™. A frame level command set is achieved by a unique microprogrammed
dual processor chip architecture. The processing capability supported by the 8273 relieves the system CPU of the low
level real·time tasks normally associated with controllers,
BLOCK OIAGRAM
PIN CONFIGURATION
REGISTERS
FLAG DET
Vee
Tx INT
PB;
PB;
elK
RESET
PB2
TxDACK
fiB,
TxDAQ
FITS
RxDACK
PA,
RxDRQ
PA 3
AD
PAz
WR
CD
Rx tNT
eTS
DBD
TxD
DBl
Txe
DB2
RiC
DB3
RxD
DB,
32xClK
DB5
TxlNT RESULT
TEST MODE
TxDRQ
es
DBS
DPLl
DB'
A,
GND
Ao
_ _ _ _,
TxDACK - - - - ,
RxDRQ
DPLL
32X elK
RTS
RxDACK
PBl~4
TxlNT
RxlNT
RD
ViR
I
A,
PIN NAMES
DBO-DB7 DATA BUS (8 BITS)
FLAG DET FLAG DETECT
TxlNT
TRANSMITTER INTERRUPT
elK
CLOCK INPUT
RESET
RESET
TRANSMITTER DMA ACKNOWLEDGE
Tx DACK
TxDRQ
TRANSMITTER DMA REQUEST
READ INPUT
AD
ViR
WRITE INPUT
Ax DACK
RECEIVER DMA ACKNOWLEDGE
Rx ORO
RECEIVER DMA REQUEST
Ax INT
RECEIVER INTERRUPT
AO-Al
COMMAND REGISTER SELECT ADDRESS
DPLL
DIGITAL PHASE LOCKED LOOP
CS
32xCLK
Rx 0
Rx c'
Tx C
Tx 0
ill
RESET
CHIP SELECT
32 TIMES CLOCK
RECEIVER DATA
RECEIVER CLOCK
TRANSMITTER CLOCK
TRANSMITTER DATA
CLEAR TO SEND
CARRIER DETECT
CD
PA2-PA4 GP INPUT PORTS
~-PB 4 ~~g~:;~i6~~~~
Vee
GND
+5 VOLT SUPPLY
GROUND
12·142
os
elK _ _ _---l
FLAGDET
INTERNAL DATA BUS CPU INTERFACE
MODEM INTERFACE
8273
types of frames; an Information Frame is used to transfer
data, a Supervisory Frame is used for controi purposes,
and a Non-sequenced Frame is used for initialization and
control of the secondary stations.
A BRIEF DESCRIPTION OF HOLC/SOLC
PROTOCOLS
General
Frame Characteristics
The High Level Oata Link Control (HOLC) is a standard
communication link protocol established by International
Standards Organization (ISO). HOLC is the discipline
used to implement ISO X.25 packet switching systems.
The Synchronous Oata Link Control (SOLC) is an IBM
communication link protocol used to implement the
System Network Architecture (SNA). Both the protocols,
are bit oriented, code independent, and ideal for full
duplex communication. Some common applications
include terminal to terminal, terminal to CPU, CPU to
CPU, satellite communication, packet switching and other
high speed data links. In systems which require expensive
cabling and interconnect hardware, any of the two
protocols could be used to simplify interfacing (by going
serial), thereby reducing interconnect hardware costs.
Since both the protocols are speed independent, reducing
interconnect hardware could become an important
application.
Network
In both the HOLC and SOLC line protocols, according to a
pre-assigned hierarchy, a PRIMARY (Control) STATION
controls the overall network (data link) and issues
commands to the SECONOARY (Slave) STATIONS. The
latter comply with instructions and respond by sending
appropriate RESPONSES. Whenever a transmitting
station must end transmission prematurely it sends an
ABORT character. Upon detecting an abort character, a
receiving station ignores the transmission block called a
FRAME. Time fill between frames can be accomplished by
transmitting either continuous frame preambles called
FLAGS or an abort character. A time fill within a frame is
not permitted. Whenever a station receives a string of
more that fifteen consecutive ones, the station goes into
an IOLE state.
An important characteristic of a frame is that Its contents are made code transparent by use of a zero bit
insertion and deletion technique. Thus, the user can adopt
any format or code suitable for his system - it may even
be a computer word length or a "memory dump". The
frame is bit oriented that is, bits, not characters in each
field, have specific meanings. The Frame Check
Sequence (FCS) is an error detection scheme similar to
the Cyclic Redundancy Checkword (CRC) widely used in
magnetic disk storage devices. The Command and
Response information frames contain sequence numbers
in the control fields identifying the sent and received
frames. The sequence numbers are used in Error
Recovery Procedures (ERP) and as implicit acknowledgement of frame communication, enhancing the true fullduplex nature of the HOLC/SOLC protocols.
In contrast, BISYNC is basically half-duplex (two way
alternate) because of necessity to transmit immediate
acknowledgement frames. HOLC/SOLC therefore saves
propagation delay times and have a potential of twice the
throughput rate of BISYNC.
It is possible to use HOLC or SOLC over half duplex lines
but there is a corresponding loss in throughput because
both are primarily designed for full-duplex communication. As in any synchronous system, the bit rate is
determined by the clock bits supplied by the modem,
protocols themselves are speed independent.
A byproduct of the use of zero-bit insertion-deletion
technique is the non-return-to-zero invert (NRZI) data
transmission/reception compatibility. The latter allows
HOLC/SOLC protocols to be used with asynchronous
data communication hardware in which the clocks are
derived from the NRZI encoded data.
References
Frames
A single communication element is called a FRAME which
can be used for both Link Control and data transfer
purposes. The elements of a frame are the beginning eight
bit FLAG (F) consisting of one zero, six ones, and a zero,
an eight bit AOORESS FIELO (A), an eight bit CONTROL
FIELO (C), a variable (N-bit) INFORMATION FIELO (Il, a
sixteen bit FRAME CHECK SEQUENCE (FCS), and an
eight bit end FLAG (F), having the same bit pattern as the
beginning flag. In HOLC the Address (A) and Control (C)
bytes are ext~ndable. The HOLC and the SOLC use three
OPENING
FLAG (F)
AOORESS
FIELO (A)
01111110
BBITS
CONTROL
FIELD (C)
BBITS
IBM Synchronous Data Link Control General Information, IBM. GA273093-1.
Standard Network Access Protocol Specification, DATAPAC, TransCanada Telephone System CCG111
Recommendation X.25, ISO/CCITT March 2, 1976.
IBM 3650 Retail Store System Loop Interface OEM Information, IBM, GA
27-3098-0
Guidebook to Data Communications, Training Manual, Hewlett-Packard
5955-1715
IBM Introduction to Teleprocessing, IBM, GC 20-8095-02
System Network Architecture, Technical OverView, IBM, GA 27-3102
System Network Architecture 'Format and Protocol, IBM GA 27-3112
INFORMATION
FIELD (II
FRAME CHECK
SEQUENCE (FCSI
CLOSING
FLAG (FI
VARIABLE LENGTH
(ONLY IN I FRAMESI
16 BITS
01111110
Figure 1. Frame Format
12·143
8273
FUNCTIONAL DESCRIPTION
TxDRQ (6)
o
Req uests a transfer of data between memory and the 8273 for a
transmit operation.
RxRDQ (8)
o
Requests a transfer of data between the 8273 and memory for a
receive operation.
General
The Intel@ 8273 HDlC/SDlC controller is a microcomputer peripheral device which supports the International
Standards Organization (ISO) High level Data Link
Control (HDlC). and IBM Synchronous Data Link Control
(SDlC) communications protocols. This controller
minimizes CPU software by supporting a comprehensive
frame-level instruction set and by hardware implementation of the low level tasks associated with frame
assem bly/disassem bly and data integrity. The 8273 can be
used in either synchronous or asynchronous applications.
In asynchronous applications the data can be programmed to be encoded/decoded in NRZI code. The clock is
derived from the NRZI data using a digital phase locked
loop. The data transparency is achieved by using a zerobit insertion/deletion technique. The frames are automatically checked for errors during reception by verifying the
Frame Check Sequence (FCS); the FCS Is automatically
generated and appended before the final flag in transmit.
The 8273 recognizes and can generate flags (01111110).
Abort. Idle. and GA (EOP) characters.
The 8273 can assume either a primary (control) or a
secondary (slave) role. It can therefore be readily
implemented in an SDlC loop configuration as typified by
the IBM 3650 Retail Store System by programming the
8273 into a one-bit delay mode. In such a configuration. a
two wire pair can be effectively used for data transfer
between controllers and loop stations. The digital phase
locked loop output pin can be used by the loop station
without the presence of an accurate Tx clock.
TxDACK (5)
The Transmitter DMA acknowledge signal notifies the 8273 that
the TxDMA cycle has been
granted.
RxDACK
The Receiver DMA acknowledge
signal notifies the 8273 that the
RxDMA cycle has been granted.
(7)
A1-Ao (22-21)
TxD (29)
These two lines are CPU Interface Register Select lines.
o
TXC (28)
The transmitter clock is used to
synchronize the transmit data.
RxD (26)
This line receives serial data from
the communication channel.
FiXC (27)
The Receiver Clock is used to
synchronize the receive data.
32X ClK (25)
The 32X clock is used to provide
clock recovery when an asynchronous modem is used. In loop
configuration the loop station
can ru n without an accu rate 1X
clock by using the 32X ClK in
conjunction with the DPll output. (This pin must be grounded
when not used).
Hardware Description
The 8273 is packaged in a 40 pin DIP. The following is a
functional description of each pin.
Pin Name (No.)
I/O Description
Vee (40)
GND (20)
RESET (4)
+5V Supply
Ground
A high signal on this pin will force
the 8273 to an idle state. The 8273
will remain idle until a command
is issued by the CPU. The modem
interface output signals are forced high. Reset must be true for a
minimum of 10 TCY.
The RD and WR inputs are enal:!led by the chip select input.
I/O The Data Bus lines are bidirectional three-state lines which interface with the system Data Bus.
The Write signal is used to control the transfer of either a command or data from CPU to the
Cs (24)
DB7-0Bo (19-12)
WR (10)
i5PII (23)
o
Digital Phase locked loop output can be tied to RxC and/or
TxC when 1X clock is not available. DPll is used with 32X ClK.
FLAG DET (1)
o
Flag Detect signals that a flag
(01111110) has been received by
an active receiver.
RTS(35)
o
TxlNT (2)
RxlNT (11)
o
o
The Read signal is used to control the transfer of either a data
byte or a status word from the
8273 to the CPU.
The Transmitter interrupt signal
indicates that the transmitter
logic requires service.
The Receiver interrupt signal indicates that the Receiver logic requires service.
Request to Send signals that the
8273 is ready to transmit data.
CTS(30)
Clear to Send signals that the
modem is ready to accept data
from the 8273.
CiS
Carrier Detect signals that the
line transmission has started and
the 8273 may begin to sample
data on RxD line.
(31)
8273.
RD(9)
This line transmits the serial data
to the communication channel.
General purpose input ports. The
logic levels on these lines can be
Read by the CPU through the
Data Bus Buffer.
PB1-4 (36-39)
ClK (3)
12·144
o
General purpose output ports.
The CPU can -write these output
lines through Data Bus Buffer.
A square wave TTL clock.
8273
CPU Interface
Register Description
The CPU interface is optimized for the MCS-80/85'" bus
with an 8257 DMA controller. However, the interface is
flexible, and allows either DMA or non-DMA data
transfers, interrupt or non-interrupt driven. It further
allows maximum line utilization by providing early
interrupt mechanism for buffered (only the information
field can be transferred to memory) Tx command overlapping. It also provides separate Rx and Tx interrupt
output channels for efficient operation. The 8273 keeps
the interrupt request active until all the associated
interrupt results have been read.
The CPU utilizes the CPU interface to specify commands
and transfer data. It consists of seven registers addressed
via CS, A1, Ao, RD and WR signals and two independent
data registers for receive data and transmit data. A1, Aoare
generally derived from two low order bits ofthe address
bus. If an 8080 based CPU is utilized, the RD and WR
signals may be driven by the 8228 I/OR and I/OW. The
table shows the seven register select decoding:
Address Inputs
A1
AD
0
0
1
1
0
1
0
1
Command
Operations are initiated by writing an appropriate
command in the Command Register.
Parameter
Parameters of commands that require additional information are written to this register.
Result
Contains an immediate result describing an outcome of an
executed command.
Transmit Interrupt Result
Contains the outcome of 8273 transmit operation
(good/bad completion).
Receive Interrupt Result
Contains the outcome of 8273 receive operation (good/
bad completion), followed by additional results which detail the reason for interrupt.
Control Logic Inputs
CSoRD
CSoWR
Status
Result
TxlNT Result
RxlNT Result
Status
The status register reflects the state of the 8273 CPU
Interface.
Command
Parameter
Test Mode
-
DMA Data Transfers
The 8273 CPU interface supports two independent data
interfaces: receive data and transmit data. At high data
transmission speeds the data transfer rate of the 8273 is
great enough to justify the use of direct memory access
lDMA) for the data transfers. When the 8273 is configured
in DMA mode, the elements of the DMA interfaces are:
TxDRQ: Transmit DMA Request
Requests a transfer of data between memory and the
8273 for a transmit operation.
TxDACK: Transmit DMA Acknowledge
The TxDACK signal notifies the 8273 that a transmit DMA
cycle has been granted.
RxDRQ: Receive DMA Request
Requests a transfer of data between the 8273 and memory for a receive operation.
Figure 2. 8273 Block Diagram Showing CPU Interface
Functions
12-145
8273
RxDACK: Receive DMA Acknowledge
The RxDACK signal notifies the 8273 that a receive DMA
cycle has been granted.
RD, WR: Read, Write
The RD and WR signals are used to specify the direction of
the data transfer.
DMA transfers require the use of a DMA controller such as
the Intel 8257. The function of the DMA controller is to
provide sequential addresses and timing for the transfer,
at a starting address determined by the CPU. Counting of
data block lengths is performed by the 8273.
To request a DMA transfer the 8273 raises the appropriate
DMA REQUEST. DMA ACKNOWLEDGE and READ enables DMA data onto the bus (independently of CHIP
SELECT). DMA ACKNOWLEDGE and WRITE transfers
DMA data to the 8273 (independent of CHIP SELECT).
It is also possible to configure the 8273 in the non-DMA
data transfer mode. In this mode the CPU module must
pass data to the 8273 in response to non-DMA data requests indicated by the status word.
Modem Interface
The 8273 Modem interface provides both dedicated and
user defined modem control functions. All the signals are'
active low so that EIA RS-232C inverting drivers (MC 1488)
and inverting receivers (MC 1489) may be used to interface
to standard modems. For asynchronous operation, this
interface supports programmable NRZI data encode/
decode, a ~igital phase locked loop for efficient clock
extraction from NRZI data, and modem control ports with
automatic CTS, CD monitoring and RTS generation. This
interface also allows the 8273 to operate in PRE-FRAME
SYNC mode in which the 8273 prefixes 16 transitions to a
frame to synchronize idle lines before transmission of the
'
first flag.
It should be noted that all the 8273 port operations deal
with logical values, for instance, bit DO of Port A will be a
one when CTS (Pin 30) is a physical zero (logical onel.
Port A - Input Port
During operation, the 8273 interrogates input pins CT§
(Clear to Send) and CD (Carrier Detect). CTS is used to
condition the start of a transmission. If during transmission CTS is lost the 8273 generates an interrupt. During
reception, if CD is lost, the 8273 generates an interrupt.
l
ICTS -
Figure 3. 8273 Block Diagram Showing Control Logic
Functions
Port B - Output Port
During normal operation, if the CPU sets RTS active, the
8273 will not change this pin; however, ilthe CPU setsRi'S
inactive, the 8273 w(1I activate it before each transmission
and deactivate it one byte time after transmission. While
the receiver is active the flag de~ect pin is pulsed each time
a flag sequence is detected in the receive data stream.
Following an 8273 reset, all pins of Port Bare set to a high,
inactive level.
I RTS
CLEAR TO SEND
- REQUEST TO SEND
USER DEFINED OUTPUT PB4. pa3. PB2, PBl
CD - CARRIER DETECT
USER DEFINED INPUT PA4. PA3, PA2
FLAG DETECT
The user defined input bits correspond to the 8273 PA4 ,
PA, and PA2 pins. The 8273 does not interrogate or manipulate these bits.
The user defined output bits correspond to the state of
PB4-PB1 pins. The 8273 does not interrogate or manipulate these bits.
12-146
8273
Serial Data Logic
The Serial data is synchronized by the user transmit (TxC)
and receive (RxC) clocks. The leading edge of TxC
generates new transmit data and the trailing edge of RxC
is used to capture receive data. The NRZI encoding/
decoding of the receive and transmit data is programmable.
The diagnostic features included in the Serial Data logic
are programmable loop back of data and selectable clock
for the receiver. In the loop-back mode, the data presented
to the TxD pin is internally routed to the receive data input
TxC
TxD
RxC
RxD
\
/
X
circuitry in place of the RxD pin, thus allowing a CPU to
send a message to itself to verify operation of the 8273.
In the selectable clock diagnostic feature, when the data is
looped back, the receiver may be presented incorrect
sample timing by the external circuitry. The user may
select to substitute the TxC pin for the RxC input on-chip
so that the clock used to generate the loop back data is
used to sample it. Since TxD is generated off the leading
edge of TxC and RxD is sampled on the trailing edge, the
selected clock allows bit synchronism.
/
X
\
/
)
\
)
I
X
r
\
\
)
\
X
r
X
X
Figure 4. Transmit/Receive Timing
Asynchronous Mode Interface
Although the 8273 is fully compatible with the HDLC/
SDLC communication line protocols, which are primarily
designed for synchronous communication, the 8273 can
also be used in asynchronous applications by using this
interface. The interface employs a digital phase locked
loop (DPLU for clock recovery from a receive data stream
and programmable NRZI encoding and decoding of data.
The use of NRZI coding with SDLC transmission
guarantees that within a frame, data transitions will occur
at least every five bit times -the longest sequence of ones
which may be transmitted without zero-bit insertion. The
DPLL should be used only when NRZI coding is used
since the NRZI coding will transmit zero sequence as line
transitions. The digital phase locked loop also facilitates
full-duplex and half-duplex asynchronous implementation with, or without modems.
12·147
8273
Digital Phase Locked Loop
In asynchronous applications, the clock is derived from
the receiver data stream by the use of the digital phase
locked loop (DPLU. The DPLl requires a clock input at32
times the required baud rate. The receive data (RxDl is.
sampled with this 32X ClK and the 8273 DPll supplies a
sample pulse nominally centered on the RxD bit cells. The
DPll has a built-in "stiffness" which reduces sensitivity to
line noise and bit distortion. This is accomplished by
making phase error adjustments in discrete increments.
Since the nominal pulse is made to occur at 32 counts of
the 32X ClK, these counts are subtracted or added to the
nominal, depending upon which quadrant of the four error
quadrants the data edge occurs in. For example if an RxD
edge is detected in quadrant A1, it is apparent that the
DPll sample "A" was placed too close to the trailing edge
of the data cell; sample "8" will then be placed at T =
(T nominal - 2 countsl, = 30 counts of the 32X ClK to move
the sample pulse "8" toward the nominal center of the next
bit cell. A data edge occuring in quadrant 81 would cause
a smaller adjustment of phase with T = 31 counts of the
32X ClK. Using this technique the DPll pulse will
co'nverge to nominal bit center within 12 data bit times,
worst case, with constant incoming RxD edges.
A method of attaining bit synchronism following a line idle
is to use PRE-FRAME SYNC mode of transmission.
RxD
_-.JX'--___--JX'--___--JX'--__
DPLL
SAMPLES
OOM",~
j j
t±=±±J
ADJUSTMENT
-2
-1
Figure 5. DPll Sample Timing
12-148
+1
+2
8273
Synchronous Modem -
8273
Duplex or Half Duplex Operation
RxC
RxD
TxC
TxD
32xCLK
r
GND
MODEM
;=xc
MODEM
32XC[j(
1
1
GND
TxC
~
~
RxD
MODEM
8273
r - - - I - - I RxD
DPLL
MODEM
~
~
-V
MODEM
-....--
r
I
Asynchronous -
I
No Modems -
TxC
TxD
I
8273
RxC
RxD
32xCLK
I
32x
CLOCK
1
N.C.
Half Duplex Operation
TxD
RxC
DPLL
Duplex Operation
MODEM
Asynchronous Modems -
8273
TxD
N.C.
8273
32xCLK
""/
~
DPLL
Asynchronous Modems -
8273
/
RxC
RxD
A
i
l
32x
CLOCK
--
DPLL
I
I
Duplex or Half Duplex
8273
8273
I
12·149
8273
SOLe Loop
The DPLL simplifies the SDLC loop station implementation. In this application, each secondary station on a loop
data link is a repeater set in one-bit delay mode. The
signals sent out on the loop by the loop controller (primary
station) are relayed from station to station then, back to
the controller. Any secondary station finding its address in
the A field captures the frame for action at that station. All
received frames are relayed to the next station on the loop.
Loop stations are required to derive bit timing from the
incoming NRZI data stream. The DPLL generates sample
Rx clock timing for reception and uses the same clock to
implement Tx clock timing.
8273
LOOP
CONTROLLER
RxD 1-------,
r------tTxD
TXC
RxD Rxe
8273
LOOP
TERMINAL
TxD
8273
LOOP
TERMINAL
TxD~--+------+-----~RxD
I
Figure 6. SOLe Loop Application
12-150
8273
PRINCIPLES OF OPERATION
The 8273 is an intelligent peripheral controller which
relieves the CPU of many of the rote tasks associated with
constructing and receiving frames. It is fully compatible
with the MCS-80/85'· system bus. As a peripheral device,
it accepts commands from a CPU, executes these
commands and provides an Interrupt and Result back to
the CPU at the end of the execution. The communication
with the CPU is done by activation of CS, RD, WR pins,
while the A1, Ao select the appropriate registers on the
chip as described in the Hardware Description Section.
YES
The 8273 operation is composed of the following
sequence of events:
CPU WRITES COMMAND AND PARAMETERS INTO THE
8273 COMMAND AND PARAMETER REGISTERS.
NO
THE 8273 IS ON ITS OWN TO CARRY OUT THE COMMAND.
THE 8273 SIGNALS THE CPU THAT THE EXECUTION
H"AS FINISHED. THE CPU MUST PERFORM A READ
OPERATION OF ONE OR MORE OF THE REGISTERS.
END OF COMMAND PHASE
The Command Phase
During the command phase, the software writes a command to the command register. The command bytes provide a general description of the type of operation requested. Many commands require more detailed information about the command. In such a case up to four
parameters are written into the parameter register. The
flowchart of the command phase indicates that a command may not be issued if the Status Register indicates
that the device is busy. Similarly if a parameter is issued
when the Parameter Buffer shows full, incorrect operation
will occur.
The 8273 is a duplex device and both transmitter and
receiver may each be executing a command or passing
results at any given time. For this reason separate
interrupt pins are provided. However, the command register must be used for one command sequence at a time.
Status Register
The status register contains the status of the 8273 activity.
The description is as follows.
o.,D6C\;D4D3o,~
YES
Figure 7. Command Phase Flowchart
Bit 6 CBF (Command Buffer Full)
Indicates that the command register is full, it is reset when
the 8273 accepts the command byte but does not imply
that execution has begun.
Bit 5 CPBF (Command Parameter Buffer Full)
CPBF is set when the parameter buffer is full, and is reset
by the 8273 when it accepts the parameter. The CPU may
poll CPBF to determine when additional parameters may
be written.
Do
! CBSV! CBF! CPBF! CRBF! RxINT! TXINT! RXIRA! TxlRA !
Bit 7 CBSY (Command Busy)
Indicates in-progress command, set for CPU poll when
Command Register is full, reset upon command phase
completion. It is improper to write a command when CBSY
is set; it results in incorrect operation.
Bit 4 CRBF (Command Result Buffer Full)
Indicates that an executed command immediate result is
present in the Result Register. It is set by 8273 and reset
when CPU reads the result.
12-151
8273
Bit 3 RxlNT (Receiver Interrupt)
The Execution Pha.e
RxlNT indicates that the receiver requires CPU attention.
It is identical to RxlNT (pin 11) and is set by the 8273 either
upon good/bad completion of a specified command or by
Non-DMA data transfer. It is reset only after the CPU has
read the result byte or has received a data byte from the
8273 in a Non-DMA data transfer.
Upon accepting the last parameter, the 8273 enters into
the Execution Phase. The execution phase may consist of
a DMA or other activity, and mayor may not require CPU
intervention. The CPU intervention is elliminated in this
phase if the system utilizes DMA for the data transfers,
otherwise, for non-DMA data transfers, the CPU is
interrupted by the 8273 via TxlNT and RxlNT pins, for
each data byte request.
Bit 2 TxlNT (Transmitter Interrupt)
The TxlNT indicates that the transmitter requires CPU
attention. It is identical to TxlNT (pin 2), It is set by 8273
either upon good/bad completion of a specified command
or by Non-DMA data transfer. It is reset only after the CPU
has read the result byte or has transferred transmit data
byte to the 8273 in a Non-DMA transfer.
The Result Phase
During the result phase, the 8273 notifies the CPU of the
execution outcome of a command. This phase is initiated
by:
Bit 1 RxlRA (Receiver Interrupt Result Available)
The RxlRA is set by the 8273 when an interrupt result byte
is placed in the RxlRA register. It is reset after the CPU has
read the RxlRA register.
1. The successful completion of an operation
2. An error detected during an operation.
Bit 0 TxlRA (Transmitter Interrupt Result Available)
To facilitate quick network software decisions, two types
of execution results are provided:
The TxlRA is set by the 8273 when an interrupt result byte
is placed in the TxlRA register. It is reset when the CPU
has read the TxlRA register.
07
05
06
I,
04
1. An Immediate Result
2. A Non-Immediate Result
O2
03
0,
DO
I
I
'\
04
03
02
01
Do
o
0
0
0
a
I
07
1
06
1
05
1
All 8-blts received
o
0
0
DO received
o
A 2 match
01-00 received
eRe enor
02-00 received
Abol t detected
03-00 received
04-00 received
EQP detected
At match 01 genel al receive
Idle detect
05-DO received
Frame less than 32·l1lls
06-00 received
DMA ovelrun dctectell
Memory huffl'r over flow
C,IrlI!!r detect failure
ReceiVE! IntClrllpt overrUll
Figure 8. Rx Interrupt Result Byte Format
06
0,
05
Do
o
I
04
03
02
o
1
1
o
01
I
Do
0
Edrly trdnSITIlt Interrupt
Frame transmit complete
OMA underrun
Cledr to Send leTS} error
Abort complete
Figure 9. Tx Interrupt Result Byte Format
12·152
8273
Immediate result is provided by the 8273 for commands
such as Read Port A and Read Port B which have
information (CTS. CO. RTS. etc'! that the network
software needs to make quick operational decisions.
A command which cannot provide an immediate result will
generate an interrupt to signal the beginning of the Result
phase. The immediate results are provided in the Result
Register; all non-immediate results are available upon
device interrupt. through Tx Interrupt Result Register
Txl/R or Rx Interrupt Result Register Rxl/A. The result
may consist of a one-byte interrupt code indicating the
condition for the interrupt and. if required. one or more
bytes which detail the condition.
Tx and Rx Interrupt Result Registers
The Result Registers have a result code. the three high
order bits 07-05 of which are set to zero for all but the
receive command. This command result contains a count
that indicates the numberof bits received in the last byte. If
a partial byte is received. the high order bits of the last data
byte are indeterminate.
SAVE STATUS
READ STATUS
REGISTER
NO
NON-DMA DATA
TRANSFER
MODE ONLY
WRITE TxDATA
USE TiillACR
AND WIi
READ TxI/R
INTERRUPT CODE
RESULT PHASE FLOWCHART - Tx INTERRUPT RESULTS
Figure 10. Tx Interrupt Service
12·153
8273
SAVE STATUS
READ STATUS
REGISTER
NO
NON·DMA DATA
TRANSFER
MODE ONLY
READ Rx DATA
READ Txl/R
USE RxDACK
INTERRUPT CODE
ANDRD
READ STATUS
RESULT BYTES
READ Rd/R
RESUL T
RESULT PHASE FLOWCHART -
INTERRUPT RESULTS
AFTER COMMAND PHASE COMPLETION (READ PORT A, PORT B)
READ STATUS
REGISTER
READ RESULT
REGISTER
RESULT PHASE FLOWCHART -
Figure 11. Rx Interrupt Service
12·154
IMMEDIATE RESULTS
8273
DETAILED COMMAND DESCRIPTION
Initialization Set/Reset Commands
General
The 8273 HDLC/SDLC controller supports a comprehensive set of high level commands which allows the 8273 to
be readily used in full-duplex, half-duplex, synchronous,
asynchronous and SDLC loop configuration, with or
without modems. These frame-level commands minimize
CPU and software overhead. The 8273 has address and
control byte buffers which allow the receive and transmit
commands to be used in buffered or non-buffered modes.
In buffered transmit mode, the 8273 transmits a flag
automatically, reads the Address and Control buffer
registers and transmits the fields, then via DMA, it fetches
the information field. The 8273, having transmitted the
information field, automatically appends the Frame Check
Sequence (FCS) and the end flag. Correspondingly, in
buffered read mode, the Address and Control fields are
stored in their respective buffer registers and only
Information Field is transferred to memory.
In non-buffered transmit mode, the 8273 transmits the
beginning flag automatically, then fetches and transmits
the Address, Control and Information fields from the
memory, appends the FCS character and an end flag. In
the non-buffered receive mode the enti re contents of a
frame are sent to memory with the exception of the flags
and FCS.
These commands are used to manipulate data within the
8273 registers. The Set commands have a single parameter which is a mask that corresponds to the bits to be set.
(They perform a logical-OR of the specified register with
the mask provided as a parameter). The Register
commands have a single parameter which is a mask that
has a zero in the bit positions that are to be reset. (They
perform a logical-AND of the specified register with the
mask).
Set One-Bit Delay (CMD Code A4)
When one bit delay is set, 8273 retransmits the received
data stream one bit delayed. This mode is entered at a
receiver character boundary, and should only be used by
Loop Stations.
Reset One-Bit Delay (CMD Code 64)
~
~
~
~
~
:::, 1 : 1 0 1 0 l' l' 1
~
0
~
~
10 1; 1
~
~1
~
0
1
HOLC Implementation
The 8273 stops the one bit delayeq retransmission mode.
HOLC Address and Control field are extendable. The
extension is selected by setti ng the low order bit of the
field to be extended to a one, a zero in the low order bit
indicates the last byte of the respective field.
Set Data Transfer Mode (CMD Code 97)
Since Address/Control field extension is normally done
with software to maximize extension flexibility, the 8273
does not create or operate upon contents of the extended
HOLC Address/Control fields. Extended fields are
transparently passed by the 8273 to user as either
interrupt results or data transfer requests. Software must
assemble the fields for transmission and interrogate them
upon reception.
However, the user can take advantage of the powerful
8273 commands to minimize CPU/Software overhead and
simplify buffer management in handling extended fields.
For instance buffered mode can be used to separate the
first two bytes, then interrogate the others from buffer.
Buffered mode is perfect for a two byte address field.
When the data transfer mode is set, the 8273 will interrupt
when data bytes are required for transmission or are
available from a receive. If a transmit interrupt occurs and
the status indicates that there is no Transmit Result
(TxIRA = 0), the interrupt is a transmit data request. If a
receive interrupt occurs and the status indicates that there
is no receive result (RxIRA = OJ, the interrupt is a receive
data request.
The 8273 when programmed, recognizes protocol
characters unique to HOLC such as Abort, which is a
string of seven or more ones (01111111). Since Abort
character is the same as the GA (EOP) character used in
SOLC Loop applications, Loop Transmit and Receive
commands are not recommended to be used in HOLC.
HDLC does not support Loop mode.
12-155
Reset Data Transfer Mode (CMD Code 57)
If the Data Transfer Mode is reset, the 8273 data transfers
are performed through the DMA requests without interrupt·
ing the CPU.
8273
Set Operating Mode (CMO Code 91)
(~O)
Flag Stream Mode
If this bit is set to a one, the following table outlines the
operation of the transmitter.
I 1, -
ACTION
TRANSMITTER STATE
Idle
Transmit or Transmit}
Transparent Active
,Loop Transmit Active
1 Bit Delay Active
FLAG STREAM MODE
1 • PREFRAME SYNC MODE
1 • BUFFERED MODE
1 • EARLY INTERRUPT MODE
Send Flags immediately.
Send F lags after the
transmission complete
Ignore command.
Ignore command.
1 • EOP INTERRUPT MODE
If this bit is reset to zero the following table outlines the
operation of the transmitter.,
1- HDLCMODE
Reset Operating Mode (CMO Code 51)
TRANSMITTER STATE
CMD:
IDLE
PAR:
Transmit or TransmitTransparent Active
Loop Transmit Active
1 Bit Delay Active
Any mode switches set in eMO code 91 can be reset using
this command by placing zeros in the appropriate
positions.
(05) HOLe Mode
In HOLe mode, a bit sequence of seven ones (01111111) is
interpreted as an abort character. Otherwise, eight ones
(011111111) signal an abort.
}
ACTION
Send Id les on next character
boundary.
Send Idles after the transmission
is complete.
Ignore command.
Ignore command.
Set Serial I/O Mode (CMO Code AO)
(04) EOP Interrupt Mode
1, • NRZI MODE
In EOP interrupt mode, an interrupt is generated
whenever an EOP character (01111111) is detected by an
active receiver. This mode is useful forthe implementation
of an SOLe loop controller in detecting the end of a
message stream after a loop poll.
1 = TxC ..... RxC
1 '" LOOP BACK TxD .... RxD
Reset Serial I/O Mode (CMD Code 60)
(03) Transmitter Early Interrupt Mode (Tx)
The early Interrupt mode is specified to indicate when the
8273 should generate an end of frame interrupt. When set,
an early interrupt is generated when the last data
character has been passed to the 8273. If the user software
responds with another transmit command before the final
flag is sent, the final flag interrupt will not be generated
and a new frame will immediately begin when the current
frame is complete. This permits frames to be separated by
a single flag. If no additional Tx commands are provided, a
final interrupt will follow.
This command allows bits set in eMO code AO to be reset
by plaCing zeros in the appropriate positiohS.
If this bit is zero, the interrupt will be generated only after
the final flag has been transmitted.
(02) Buffered Mode
If the buffered mode bit is set to a one, the first two bytes
(normally the address (A) and control (e) fields) of a frame
are buffered by the 8273. l1this bit is a zero the address and
control fields are passed to and from memory.
(01) Preframe Sync Mode
If this bit is set to a one the 8273 will transmit two characters before the first flag of a frama
To guarantee sixteen line transitions, the 8273 sends two
bytes of data (OO)H if NRZI is set or data (55)H if NRZI is not
set.
12·156
(02) Loop Back
If this bit is set to a one, the transmit data is internally routed
to the receive data circuitry.
(01) TxC ..... RxC
If this bit Is set to a one, the transmit clock is internally
routed to the receive clock circuitry. It is normally used
with the loop back bit (02),
(~O)
NRZI Mode
If this bit is set to a one, NRZI encoding and decoding of
transmit and receive data is provided. If this bit is a zero, the
transmit and receive data is treated as a normal positive logic
bit stream.
NRZI encoding specifies that a zero causes a change in the
polarity of the transmitted signal and a one causes no polarity
change. NRZI is used in all asynchronous operations.
Refer to IBM document GA27-3093 for details.
8273
Reset Device Command
~
~
~
~
Selective Receive (CMD Code Cl)
~
~
~
~
~
~
CMD :
PAR :
::: I' 1: 1 1 I: 1 1 1 I: 1: I
PAR :
'1'1°1°1°1°1°1'
° °, LEAST
SIGNIFICANT BYTE OF THE
°
RECEIVE BUFFER LENGTH (BOI
,
MOST SIGNIFICANT BYTE OF RECEIVE
°
,
RECEIVE FRAME ADDRESS MATCH
°
ONE IA'I
, FIELD
RECEIVE FRAME ADDRESS MATCH
°
FIELD TWO IA21
BUFFER LENGTH (B1)
PAR :
An 8273 reset command is executed by outputing a (Ol)H
followed by (OO)H to the test mode register (TMR)' See 8273
AC timing characteristics for Reset pulse specifications.
The reset command emulates the action of the reset pin.
1. The modem control signals are forced high (inactive
level).
2. The 8273 status register flags are cleared.
3. Any commands in progress are terminated immediately.
4. The 8273 enters an idle state until the next command is
issued.
PAR :
Selective receive is a receive mode in which frames are
ignored unless the address field matches anyone of two
address fields given to the 8273 as parameters.
When selective receive is used in HOLC the 8273 looks at
the first character, if extended, software must then decide
if the message is for this unit.
Selective Loop Receive (CMD Code C2)
5. The Serial 1/0 and Operating Mode registers are set
to zero and OMA data register transfer mode is
selected.
6. The device assumes a non-loop SOLC terminal role.
CMD :
PAR :
PAR :
Receive Commands
PAR :
PAR :
The 8273 supports three receive commands: General
Receive, Selective Receive, and Selective Loop Receive.
General Receive (CMD Code CO)
General receive is a receive mode in which frames are
received regardless of the contents of the address field.
CMD :
PAR :
PAR :
°
°
°
°
°
°
°
,
,
,
'1'lololoLol'lo
LEAST SIGNIFICANT BYTE OF THE
RECEIVE BUFFER LENGTH IBOI
MOST SIGNIFICANT BYTE OF RECflVE
BUFFER LENGTH (B1)
RECEIVE FRAME ADDRESS MATCH
FIELD ONE IA'I
RECEIVE FRAME ADDRESS MATCH
FIELD TWO IA21
Selective loop receive operates like selective receive except that the transmitter is placed in flag stream mode .,.
automatically after detecting an EOP (01111111) following
a valid received frame. The one bit delay mode is also
reset at the end of a selective loop receive.
Receive Disable (CMD Code C5)
° °, '1'1010\0101010
°
RECEIVE BUFFER LENGTH (BOI
, MOST
SIGNIFICANT BYTE OF RECEIVE
°
BUFFER LENGTH (B'I
Terminates an active receive command immediately.
LEAST SIGNIFICANT BYTE OF THE
~
NOTES:
1. If buffered mode is specified, the RO, R1 receive frame length
(result) is the number of data bytes received.
2. If non-buffered mode is specified, the RO, R1 receive frame
length (result) is the number of data bytes received plus two
(the count includes the address and control bytes).
3. The frame check sequence (FCS) is not transferred to
memory.
4. Frames with less than 32 bits between flags are ignored (no
interrupt generated) if the buffered mode is specified.
5. In the non-buffered mode an interrupt is generated when a
less than 32 bit frame is received, since data transfer requests
have occurred.
6. The 8273 receiver is always disabled when an Idle is received
after a valid frame. The CPU module must issue a receive
command to re-enable the receiver.
7. The intervening ABORT character between a final flag and an
IDLE does not generate an interrupt.
8. If an ABORT Character is not preceded by a flag and is followed by an IDLE, an interrupt will be generated for the ABORT
followed by an IDLE interrupt one character time later. The
reception of an ABORT will disable the receiver.
12-157
~
~
~
~
~
~
~
~
I ° I ° I ' I ' I ° I °I °I ' I ° I
CMD:
PAR: NONE
~
8273
Transmit Commands
Transmit Transparent (CMD Coded C9)
The 8273 supports three transmit commands: Transmit
Frame, Loop Transmit, Transmit Transparent.
CMD
PAR
Transmit Frame (CMD Code Ca)
,
,
PAR
CMO
,
0
PAR
,
0
PAR
PAR
PAR
,
,
,
0
0
,
,
0
,
'1'10101'101010
,
,
0
0
'1'loloL'i o
0
,
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L')
The 8273 will transmit a block of raw data without
protocol, i.e., no zero bit insertion, flags, or frame check
sequences.
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)
MOST SIGNIF ICANT BYTE OF
FRAME LENGTH (L')
ADDRESS FIELD OF TRANSMIT FRAME (A)
,
0
,
0
0
Abort Transmit Commands
CONTROL FIELD OF TRANSMIT FRAME (C)
Transmits one frame including: initial flag, frame check
sequence, and the final flag.
If the buffered mode is specified, the LO, L1, frame length
provided as a parameter is the length of the information
field and the address and control fields must be input.
In unbuffered mode the frame length provided must bethe
length of the information field plus two and the address
and control fields must be the first two bytes of data. Thus
only the frame length bytes are required as parameters.
Loop Transmit (CMD Code CAl
An abort command is supported for each type of transmit
command. The abort commands are ignored if a transmit
command is not in progress.
Abort Transmit Frame (CMD Code CC)
~
CMO,
PAR,
~
~
~
~
~
~
~
~
~
I 0 I 0 I , I ' I0 I 0 I, I , I 0 I 0
NONE
After an abort character (eight contiguous ones) is transmitted, the transmitter reverts to sending flags or idles as a
function of the flag stream mode specified.
Abort Loop Transmit (CMD Code CE)
,
0
PAR
,
0
,
PAR
,
0
,
0
,
CMD
PAR
PAR
,
0
0
,
,
1 ' 1 0 1 0 1
'I
0 1 '
~
1 0
LEAST SIGNifiCANT BYTE OF
CMD,
PAR,
FRAME LENGTH (LO)
~
~
~
~
~
~
~
~
~
I 0 I 0 I ' I ' I 0 I 0 I' I ' I ' I 0 I
NONE
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (Ll)
After a flag is transmitted the transmitter reverts to one bit
delay mode.
ADDRESS FIELD OF TRANSMIT FRAME (A)
CONTROL FIELD OF TRANSMIT FRAME IC)
Abort Transmit Transparent (CMD Code CD)
Transmits one frame in the same manner as the transmit
frame command except:
1. This command should be given only in one-bit delay
mode.
2. If the flag stream mode is not active transmission will
begin after a received EOP has been converted to a
flag.
3. If the flag stream mode is active transmission will
begin at the next flag boundary for buffered mode or at
the third flag boundary for non-buffered mode.
4. At the end of a loop transmit the one-bit delay mode is
entered and the flag stream mode is reset.
~
CMD,
PAR,
~
~
~
~
~
~
~
~
~
I 0 I 0 I ' I ' I0 I 0 I' I ' I 0 I '
NONE
The transmitter reverts to sending flags or idles as a function of the flag stream mode specified.
. 12-158
8273
Modem Control Commands
(05) Flag Detect
The modem control commands are used to manipulate the
modem control ports.
This bit can be used to set the flag detect pin. However, it
will be reset when the next flag is detected.
When read Port A or Port B commands are executed the
result of the command is returned in the result register.
The Bit Set Port B command requires a parameter that is a
mask that corresponds to the bits to be set. The Bit Reset
Port B command requires a mask that has a zero in the bit
positions that are to be reset.
These bits correspond to the state of the PB4-PB, output
pins.
Read Port A (CMO Code 22)
~
~
~
~
~
~
~
~
~
~
PAR:
NONE
A,
PAR:
I
0
07
AO
I
0
I
o
06
I
0
0,
Os
03
O2
0,
~:~,lollllllolol'll
l
DO
I, I I I I , I ,
0
0
This is a dedicated 8273 modem control signal, and
reflects the same logical state of RTS pin.
This command allows Port B user defined bits to be reset.
Read Port B (CMO Code 23)
CMD:
(Do) Request to Send
Reset Port B Bits (CMO Code 63)
I 0 I 0 I 0 I 0 I ' I 0 I0 I 0 I ' I 0
CMD
(04-01) User Defined Outputs
0
NONE
Set Port B Bits (CMO Code A3)
ATS - AEQUEST TO SEND
USER DEFINED
FLAG DETECT
This command allows user defined Port B pins to be set.
This command allows Port B (D4-D,) user defined bits to
be reset. These bits correspond to Output Port pins (PB4PB,).
~:~III~I:llloloITl
I RTS -
I
REQUEST TO SEND
USER DEFINED
FLAG DETECT
8273 Command Summary
Command Description
Command
(HEX)
Parameter
Results
Result
Port
Completion
Interrupt
Set One Bit Delay
A4
Set Mask
None
64
Reset Mask
None
-
No
Reset One Bit Delay
Set Data Transfer Mode
97
Set Mask
None
-
No
Reset Data Transfer Mode
57
Reset Mask
None
No
Set Operating Mode
91
Set Mask
None
-
Reset Operating Mode
51
Reset Mask
None
-
No
Set Serial 1/0 Mode
AO
Set Mask
None
-
No
Reset Serial 1/0 Mode
60
Reset Mask
None
-
No
General Receive
CO
BO,B1
IC,RO,R1,A,C
RXI/R
Yes
Selective Receive
C1
BO,B1,A1,A2
IC,RO,R1,A,C
RXI/R
Yes
Selective Loop Receive
C2
BO,B1,A1,A2
IC,RO,R1,A,C
RXI/R
Yes
No
No
Receive Disable
C5
None
None
-
No
Transmit Frame
C8
LO,L1,A.C
IC
TXI/R
Yes
Loop Transmit
CA
LO,L 1 ,A,C
IC
TXI/R
Yes
Transmit Transparent
C9
LO,L1
IC
TXI/R
Yes
Abort Transmit Frame
CC
None
IC
TXI/R
Yes
Abort Loop Transmit
CE
None
IC
TXI/R
Yes
Abort Transmit Transparent
CD
None
IC
TXI/R
Yes
Read Port A
22
None
Port Value
Result
No
Read Port B
23
None
Port Value
Result
No
Set Port B Bit
A3
Set Mask
None
Reset Port B Bit
63
Reset Mask
None
-
No
12·159
No
I
8273
8213 Command Summary Key
BO
-
Least significant byte of the receive buffer
length.
Bl
- Most significant byte of the receive buffer
length.
- Least significant byte of the Tx frame length.
LO
L1
- Most significant byte of the Tx frame length.
Al
- Receive frame address match field one.
- Receive frame address match field two.
A2
- Address field of received frame. If non-buffered
A
mode is specified, this result is not provided.
- Control Held of received frame. If non-buffered
C
mode is specified this result is not provided.
RXI/R -'Receive interrupt result register.
TXI/R - Transmit interrupt result register.
- Least significant byte of the length of the frame
RO
received.
- Most significant byte of the length of the frame
Rl
received.
- I nterrupt result code (see table).
IC
w,
"
TXINT
RXINT
"",
,.,
CONTROLLER
Figure 14. 8273 System Diagram
j '.'''"'.'
A[CllvE
Figure 12. Typical Frame Reception
j '''",."
FRAME
" I" I" I'", I'"
I"MI;~::I
m --lr------------------.L
I
m
---I'---------------,L
~EARlYhINTEARUPT
Figure 13. Typical Frame Transmission
12·160
8273
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ........ O°C to 70° C
Storage Temperature ............... -65°Cto +150°C
Voltage on Any Pin With
Respectto Ground ..................... -0.5V to +7V
Power Dissipation .......................... , 1 Watt
D.C. CHARACTERISTICS
TA
= O°C to 70°C,
Symbol
Vee
= +5.0V ±5%
Min.
Max.
VIL
Input Low Voltage
-0.5
0.8
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
IlL
Input Load Current
±10
I'A
VIN = Vee to OV
loz
Off-State Output Current
±10
I'A
VOUT = Vee to OV
Icc
Vee Supply Current
160
mA
Parameter
Vee
+ 0.5
0.45
2.4
Unit
Test Conditions
Volts
Volts
Volts
IOL=2.0mA
Volts
10H = -2OOI'A
CAPACITANCE
TA = 25°C; Vee = GND = ov
Symbol
Parameter
Min.
Typ.
Max.
Unit
CIN
Input Capacitance
10
pF
te = 1MHz
CliO
1/0 Capacitance
20
pF
Unmeasured Pins
Returned to GND
12·161
Test Conditions
8273
A.C. CHARACTERISTICS
TA
= 0° C to
70° C, Vee
= +5.0V ±5%
Read Cycle
Symbol
Parameter
Min.
Max.
Unit
0
ns
0
ns
Test Conditions
tAC
Select Setup to RQ
tCA
Select Hold from RD
tAA
RD Pulse Width
tAD
Data Delay from Address
200
ns
tAD
Data Delay from RD
150
ns
Cl = 150pF
tDF
Output Float Delay
20
100
ns
Cl = 20pF for
Minimum; 150pF for
Maximum
Min.
Max.
Unit
ns
250
Write Cycle
Symbol
Parameter
tAC
Select Setup to WR
0
ns
tCA
Select Hold from WR
tww
WR Pulse Width
0
ns
250
tow
Data Setup to WR
150
ns
ns
two
Data Hold from WR
-20
ns
Test Conditions
DMA
Symbol
tco
Parameter
Min.
Request Hold from WR or RD
(for Non-Burst Mode)
Max.
Unit
150
ns
Max.
Unit
Test Conditions
Other Timing
Symbol
Parameter
Min.
Reset Pulse Width
tr
Input Signal Rise Time
20
tf
Input Signal Fall Time
20
tASTS
Reset to First IOWR
tCY
Clock
250
Note 3
tel
Clock Low
Tss
Note 2
tCH
Clock High
Tss
Note 2
tOCl
Data Clock Low
tOCH
Data Clock High
toCY
Data Clock
tTO
Transmit Data Delay
tos
Data Setup Time
100
ns
tOH
Data Hold Time
0
ns
tOPll
DPLL Output Low
tFlO
FLAG DET Output Low
10
tCY
2
ns
ns
tCY
200
ns
15625
ns
100
ns
200
ns
8·tcy±50
ns
NOTES:
1.
Test Conditions
tASTW
All timing measurements are made at the reference voltages unless otherwise specified:
Input "1" at 2.0V, "0" at O.BV
Output "1" at 2.0V, "0" at O.BV
2. To be specified.
3. 64K baud maximum operating rate.
12·162
Note 3
8273
WAVEFORMS
Read Waveforms
Ao. At. CS. DACK
--...".------------------"1'''''-----
__-+___
-4I-----tRR-----r;=!::~
_ _ _ __
AD
DATA BUS
• -
-
-
-
-
-
-
-
-
tRD-----l~~
tDF~
--"""'-I ...._ _ _ _ _..,)- - - - - - - -
- __
-_-::-_-_-_-_
i-------tAD
--
Write Waveforms
AO' At. CS. DACK
M":
=::x
X'-____
r:=~tAC=':::;;:=~'=====;;=:=tww~r~~tWD x'----------J~~::::::::::::=-tD-W==========::+t+-:-===-~-~"-----
DMA Waveforms
ORO
..J!
___
tcoJ
r
\'-------~----------------------------------------
ADOR~ ----------~~
_______
CHIP CLOCK
12-163
~
_ _ _ _ _ _ _ __
8273
Transmit Data Waveforms
i
tOCL
.1
tOCH
toCY
)t
TxO
'-'TD-
Receive Data Waveforms
\~-'DC-L_:tt
~I+---------'DCY
'OC" \
~
RXo------,~,J L~l-DPLL Output Waveform
Flag Detect Output Waveform
12-164
8275
PROGRAMMABLE CRT CONTROLLER
Programmable Screen and Character
• Format
Fully MCS·SO™ and MCS·SS™
• Compatible
• 6 Independent Visual Field Attributes
• Dual Row Buffers
• 11 Visual Character Attributes
(Graphic Capability)
• Cursor Control (4 Types)
• Light Pen Detection and Registers
">
• Programmable DMA Burst Mode
• Single + SV Supply
• 40·Pin Package
The Intel@ 8275 Programmable CRT Controller is a single chip device to interface CRT raster scan displays with
Intel@ microcomputer systems, Its primary function is to refresh the display by buffering the information from main
memory and keeping track of the display position of the screen. The flexibility designed into the 8275 will allow simple
interface to almost any raster scan CRT display with a minimum of external hardware and software overhead.
BLOCK DIAGRAM
PIN CONFIGURATION
vcc
LAo
LAl
LTEN
RVV
VSP
GPAl
GPAo
HLGT
IRQ
CCLK
CCs
CC5
CC4
CC3
CC2
CCl
CCo
CS
AO
LC3
LC2
LCl
LCO
DRQ
DACK
HRTC
VRTC
Ri5
WR
LPEN
DBO
DBl
DB2
DB3
DB4
DB5
DBS
DB7
GND
CCLK
DATA
080_7
BUS
BUFFER
C"o_6
DRQ _ _ _ _-,
lC0-3
DACK
IRQ
LA0-1
HRTe
VRTe
HLGT
RVV
PIN NAMES
LTEN
VS.
GPAO_1
OBO-1
81 DIRECTIONAL DATA BUS
ORa
OMA REQUEST OUTPUT
LAO_1
LINE ATIRIBUTE OUTPUTS
OMA ACKNOWLEDGE INPUT
HRTe
HORIZONTAL RETRACE OUTPUT
IRa
INTERRUPT REQUEST OUTPUT
VRle
!Ill"
\Wi
READ STROBE INPUT
HLGT
VERTICAL RETRACE OUTPUT
HIGHLIGHT OUTPUT
""".
C,An
DCL'
DC• •
LC0-3
LINE COUNTER OUTPUTS
WRITE STROBE INPUT
RW
REVERSE VIDEO OUTPUT
REGISTER ADDRESS INPUT
CHIP SELECT INPUT
CHARACTER CLOCK INPUT
v,.
LTEN
LIGHT ENABLE OUTPUT
VIDEO SUPPRESS OUTPUT
GPAQ-1
GENERAL PURPOSE ATTRIBUTE OUTPUTS
CHARACTER CODE OUTPUTS
LPEN
LIGHT PEN INPUT
LPEN
12-165
8275
PIN DESCRIPTIONS
Pin # Pin Name 110
1
2
3
4
LC3
LC2
LCl
LCO
0
5
DRQ
0
6
DACK
7
8
9
HRTC
VRTC
Pin # Pin Name 110
Pin Description
Line count. Output from the line count·
er which is used to address the character
generator for the line positions on the
screen.
0
o
RD
VCC
+5V power supply
39
38
LAO
LAl
o
Line. attribute codes. These attribute
codes have to be decoded externally by
the dot/timing logic to generate the
horizontal and vertical line combinations
for the graphic displays specified by the
character attribute codes.
37
LTEN
o
Light enable. Output signal used to
enable the video signal to the CRT. This
output is active at the programmed
underline cursor position, and at positions specified by attribute codes.
36
RVV
o
Reverse video. Output signal used to
indicate the CRT circuitry to reverse the
video signal. This output is active at the
cursor position if a reverse video block
cursor is programmed or at the positions
specified by the field attribute codes.
35
VSP
o
Video suppression. Output signal used to
blank the video signal to the CRT. This
output is active:
during the horizontal and vertical retrace intervals.
DMA request. Output signal to the 8257
DMA controller requesting a DMA cycle.
DMA acknowledge. Input signal from
the 8257 DMA controller acknowledging
that the requested DMA cycle has been
granted.
Horizontal retrace. Output signal which
is active during the programmed horizontal retrace interval. During this peri~
ad the VSP output is high and the
L TEN output is low.
Vertical retrace. Output signal which is
active during the programmed vertical
retrace interval. During this period the
VSP output is high and the L TEN out·
put is low.
Read input. A control signal to read
registers.
10
WR
11
LPEN
12
13
14
15
16
17
18
19
DBa
DBl
DB2
DB3
DB4
DB5
DB6
DB7
20
Ground
W'rite input. A control signal to write
commahds into the control registers or
write data into the row buffers during a
DMA cycle.
at the top and bottom lines 01 rows il
underline is programmed to be number
8 or greater.
when an end of row or end of screen
code is detected.
When a DMA underrun occurs.
Light pen. Input signal from the CRT
system Signifying that a light pen signal
has been det.ected.
I/O
Bi~directional
Pin Description
40
at regular intervals (1/16 frame frequency for cursor, 1/32 frame frequency for character and field attributes) - to create blinking displays
as specified by cursor, character attribute, or field attribute programming.
three-state data bus lines.
The outputs are enabled during a read of
the C or P ports.
34
33
GPAl
GPAO
o
General purpose attribute codes. Out·
puts which are enabled by the general
purpose field attribute codes.
32
HLGT
o
Highlight. Output signal used to intensify the display at particular positions on
the screen as specified by the character
attribute codes or field attribute codes.
31
IRQ
o
30
CCLK
29
28
27
26
25
24
23
CC6
CC5
CC4
CC3
CC2
CCl
Ground
22
CCo
CS
21
AO
12-166
Interrupt request.
Character clock (from dot/timing logic).
o
Character codes. Output from the row
buffers used for character selection in
the character generator.
Chip select. The read and write are en·
abled by CS.
Port address. A high input on AO selects
the lie" port or command registers and a
low input selects the "P" port or paramo
eter registers.
,~
,'t
"
,
8275
'\
If ~
FU NCTlO)'lAL·'OESCRIPTION
. ','
O~ta~' ,BUtter
" This 3'-state, bidirectional, 8-bit buffer is used to interface
',~'the 8275 to the system Data Bus.
This functional block accepts inputs from the System Con, trol Bus and generates control signals for overall device
operation. It contains the Command, Parameter, and Status
Registers that store the various control formats for the
device functional definition.
AO
OPERATION
REGISTER
0
Read
PREG
0
Write
PREG
1
Read
SREG
1
Write
CREG
RO (Read)
A "low" on this input informs the 8275 that the CPU is
reading data or status information from the 8275.
WR (Write)
A "low" on this input informs the 8275 that the CPU is
writing data or control words to the 8275.
Figure 1. 8275 Block Diagram Showing Data Bus Buffer
and ReadlWrite Functions
CS (Chip Select)
A "low" on this input selects the 8275. No reading or writing will occur unless the device is selected. When CS is high,
the Data Bus in the float state and RD and WR will have no
effect on the chip.
Ao
0
0
RD
WR
CS
0
1
0
0
0
0
0
0
1
0
ORQ (OMA Request)
A "high" on this output informs the DMA Controller that
the 8275 desires a DMA transfer.
OACK (OMA Acknowledge)
A "low" on this input informs the 8275 that a DMA cycle
is in progress.
IRQ (Interrupt Request)
A "high" on this output informs the CPU that the 8275
desires interrupt service.
12-167
1
0
X
X
1
1
X
X
Write 8275 Parameter
Read 8275 Parameter
Write 8275 Command
Read 8275 Status
Three-State
Three-state
8275
Character- Counter
The c:;haracter Counter is a programmable counter that is
used tb determine the number of characters to be displayed
per row and the length of the horizontal retrace interval. It
, "} is driven by the CCLK (Character Clock) input, which
,\" "'1.. should be a derivative of the external dot clock.
Line Counter
The Line Counter is a programmable counter that is used to
determine the number of horizontal lines (Sweeps) per
character row. Its outputs are used to address the external
character generator ROM.
Row Counter
The Row Counter is a programmable counter that is used to
determine the number of character rows to be displayed per
frame and length of the vertical retrace interval.
" nRil, ...
",,~';.;.;.;...""';;;'..,
, ,:IiAl3ir'
"'~
"'m:;'
'Wli
Light Pen Registers
The Light Pen Registers are two registers that store the con·
tents of the character counter and the row counter whenever there is a rising edge on the LPEN (Light Pen) input.
Note: Software correction is required.
Raster Timing and Video Controls
The Raster Timing circuitry controls the timing of the
HRTC (Horizontal Retrace) and VRTC (Vertical Retrace)
outputs. The Video Control circuitry controls the genera·
tion of LAo-1 (Line Attribute), HGLT (Highlight). RVV
(Reverse Video). LTEN (Light Enable), VSP (Video Sup·
press). and GPAO_1 (General Purpose Attribute) outputs.
Figure 2. 8275 Block Diagram Showing Counter and
Register Functions
FIFOs
There are two 16 character FI FOs in the 8275. They are
used to provide extra row buffer length in the Transparent
Attribute Mode (see Detailed Operation section).
Buffer Input/Output Controllers
Row Buffers
The Row Buffers are two 80 character buffers. They are
filled from the microcomputer system memory with the
character codes to be displayed. While one row buffer is
displaying a row of characters, the other is being filled with
the next row of characters.
The Buffer Input/Output Controllers decode the characters
being placed in the row buffers. If the character is a character attribute, field attribute or special code, these controllers control the appropriate action. (Examples: An
"End of Screen-Stop DMA" special code will cause the
Buffer Input Controller to stop further DMA requests. A
"Highlight" field attribute will cause the Buffer Output
Controller to activate the HGL T output.)
8275
"'~"(A~t~
SYSTEM OPERATION
The 8275 is programmable to a large number of different
display formats. It provides raster timing, display row buffering, visual attribute decoding, cursor timing, and light
pen detection.
It is designed to interface with the 8257 DMA Controller
and standard character generator ROMs for dot matrix,
decoding. Dot level timing must be provided by external
circuitry.
MEMORIES
U
~
\
SYSTEM BUS
DBO_7
AO
DBO_7
WR
I'ifENfR
lOW
MEMW
lOR
AD
cs
cs
HRQ
HACK
IRQ
LCO_3
DRQ
8257
DMA
CONTROLLER
VIDEO SIGNAL
CHARACTER
GENERATOR
DACK
8275
CRT
CONTROLLER
HORIZONTAL SYNC
CCO-6
CCLK
DOT
TIMING
AND
INTERFACE
VERTICAL SYNC
INTENSITY
VIDEO CONTROLS
Figure 3. 8275 Systems Block Diagram Showing Systems Operation
12-169
8275
>4
General Systems Operational Description
The 8275 provides a "window" into the microcomputer
system memory.
Display characters are retrieved from memory and dis·
played on a row by row basis. The 8275 has two row buf·
fers. While one row buffer is being used for display, the
other is being filled with the next row of characters to be
displayed. The number of display characters per row and
the number of character rows per frame are software programmable, providing easy interface to most CRT displays.
(See Programming Section.)
The 8275 requests DMA to fill the row buffer that is not
being used for display. DMA burst length and spacing is
programmable. (See Programming Section.)
The 8275 displays character rows one line at a time.
The number of lines per character row,'ifte ,underline position, and blanking of top and bottom lin~ _~"\programmabie. (See Programming Section.)
- -'~'k:~'~'\"
The 8275 provides special Control Codes which ~~ be:used
to minimize DMA or software overhead. It also proviJ;les
Visual Attribute Codes to cause special action or symbols
on the screen without the use of the character generator"
(see Visual Attributes Section).
*;'\'
The 8275 also controls raster timing. This is done by generating Horizontal Retrace (H RTC) and Vertical Retrace
(VRTC) signals. The timing of these signals is programmable.
The 8275 can generate a cursor. Cursor location and format
are programmable. (See Programming Section.)
The 8275 has a light pen input and registers. The light pen
input is used to load the registers. Light pen registers can be
read on command. (See Programming Section.)
--------------------------1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
First Line of a Character Row
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000_00_0000000000000.000_00_000_00.000.0
Second Line of a Character Row
-------------1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
'0.0000.00 •• 000.0 O. 0 0 0 DO ~ODD 0 0 DO. 0 0 0.0 O. DO O. DO. DO O. 0
'O.OODO.DO.OOOO.D O. 0 0 0 0 0 DODO 0 0 DO. 0 DO _ 0 0_ DO 0_ DO_ DOD. 0
Third Line of a Character Row
-------------1 st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000.00.0000000000000.000.00.000.00.000.0
0.0000.00.0.00.00.0000000000000.000.00.000.00.000.0
0.0000.00.0000.00 • • • • 0000000000 • • • • 000.000.00.0.0.0
0.0000.00.00.0.00.0000000000000.0.0000.000.00.0.0.0
0.0000.00.000 • • 00.0000000000000.00.000.000.00.0.0.0
OO •••• OOC.ODOO.OO • • • • • OOOOOOOOO.OO.ODOO • • • OODO.O.OO
Seventh Line of a Character Row
Figure 4. Display of a Character Row
12·170
8275
'"
¢,
After all the lines of the character r~,-tI"e scanned. the
roles of the two row buffers are reVers~anq the same
procedure is followed for the next row.
'-
Display Row Buffering
Before the start of a frame. the 8275 requests DMA and
one row buffer is filled' with characters.
~'\~4' ~
eel.
CCO_6
080-7 .
ORQ
CCO_6
LCO_3
DACK
ORQ
IRQ
DACK
LCO_l
IRQ
Ri'i
WR
Ri'i
LAO_l
HRTe
VRle
WR
HLGT
RVV
LlEN
AD
lAo-,
HRTe
VRle
HLGT
RVV
VSP
C!
LTEN
GPAO_l
vsp
C!
'-r------,...-~
GPAD--l
LPEN
LPEN
Figure 5. First Row Buffer Filled
When the first horizontal sweep is started. character codes
are output to the character generator from the row buffer
just filled. Simultaneously. DMA begins filling the other
row buffer with the next row of characters.
Figure 7. First Buffer Filled with Third Row,
Second Row Displayed
This is repeated until all of the character rows are displayed.
eel.
CCO_6
ORQ _ _ _ _-,
DACK
IRQ
lAo-,
HRTe
VRle
HLGT
RVV
LTEN
vsp
GPAo-l
LPEN
Figure 6. Second Buffer Filled, First Row Displayed
12-171
8275
Display Format
Row Format
Screen Format
The 8275 is designed to hold the line ~'~urit',
outputting the appropriate character codes'.'-9l1rJIl
horizontal sweep. The line count is incremen~' -d~r ',A
horizontal retrace and the whole row of character c~s i/:e ~7 ~ __
output again during the next sweep. This is continued i;mtil',<
the whole character row is displayed.
.'
The 8275 can be programmed to generate from 1 to 80
characters per row, and from 1 to 64 rows per frame.
--
r
The number of lines (horizontal sweeps) per character row
is programmable from 1 to 16.
The output of the line counter can be programmed to be in
one of two modes.
In mode 0, the output of the line counter is the same as the
line number.
123456789 . . . . . . . . . . . . . . 80
2
3
4
5
6
In mode 1, the line counter is offset by one from the line
number.
Note: In mode 1, while the first line (line number 0) is being dis·
played, the last count is output by the line counter (see
examples).
7
8
9
Line
Number
64
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Figure 8. Screen Format
The 8275 can also be programmed to blank alternate rows.
In this mode, the first row is displayed, the second blanked,
the third displayed, etc. DMA is not requested for the
blanked rows.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
0
0
0
0
0
0
0
•
•
0
0
0
0
•
0
0
0
0
•
0
0
•
•
•
•••••••
•
•
•
•
•
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Q
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 0
Line
Counter
Model
0000
0001
0010
0011
0100
0101
01 10
0111
1000
1001
1010
1011
1100
1101
1110
1111
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1 100
1101
1110
Figure 10. Example of a 16·Line Format
Line
Number
123456789 . . . . . . . . . . . . . . . 80
2
0
1
2
3
4
5
6
7
8
9
3
4
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
• •
0
0
•
•
•
•
•••••
•
•
•
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 0
Line
Counter
Mode 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1001
0000
0001
0010
0011
0100
0101
0110
0111
1000
64
Figure 11. Example of a 10·Line Format
Figure 9. Blank Alternate Rows Mode
Mode a is useful for character generators that leave address
zero blank and start at address 1. Mode 1 is useful for char·
acter generators which start at address zero.
12·172
8275
Underline placement is also programmable (from line number 0 to 15). This is independent of the line counter mode.
If the line number of the underline is greater than 7 (line
number MSB = 1), then the top and bottom lines will be
blanked.
Line
Number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
•
•
0
2
•
0
•
0
0
4
5
6
7
B
9
10
11
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 1
0000
0001
0010
1011
0000
0001
0010
0011
0100
10 1
110
0111
1000
1001
1010
0
a all
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0100
1 01
01 10
0111
1000
100 1
1010
1011
•
•
•
•
•••••••
•
•
•
•
•
•
•••••••••
0
Line
Counter
Mode 0
0
0
0
a
Dot Format
Dot width and character width are
external timing and control circuitry.
Dot level timing circuitry should be designed to accept the
parallel output of the character generator and shift it out
serially at the rate required by the CRT display.
a
a
8275
cc
VIDEO
vs.
Top and Bottom
Lines are Blanked
SYNCHRONIZER
Figure 14. Typical Dot Level Block Diagram
Figure 12. Underline in Line Number 10
If the line number of the underline is less than or equal to 7
(line number MSB = 0), then the top and bottom lines will
not be blanked.
Dot width is a function of dot clock frequency.
Character width is a function of the character generator
width.
Horizontal character spacing is a function of the shift
register length.
Note: Video control and timing signals must be synchronized with
the video signal due to the character generator access delay.
Line
Number
a
0
0
0
0
2
3
0
•
4
0
1
5
6
7
0
0
•0
•
0
0
0
•
0
0
0
0
0
•
0
•
•
•••••
0
0
0
0
0
•
•
•
•
•••••••
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 0
Line
Counter
Mode 1
0000
0001
0010
11
0100
10 1
11
0111
0111
0000
0001
0010
0011
0100
1 1
11
aa
a
a
a
a a
a a
Top and Bottom
Lines are not Blanked
Figure 13. Underline in Line Number 7
If the line number of the underline is greater than the maximum number of lines, the underline will not appear.
Blanking is accomplished by the VSP (Video Suppression)
signal. Underline is accomplished by the LTEN (Light
Enable) signal.
12-173
8275
~
"i¥
The row counter is an internal counter,drt~'* the, line
counter. It controls the functions of the'row ~!lfs and
counts the number of character rows displaye~.,
<
Raster Timing
The character counter is driven by the character clock input
(CCLK). It counts out the characters being displayed
(programmable from 1 to 80). It then causes the line
counter to increment, and it 'starts counting out the hori·
zontal retrace interval (programmable from 2 to 32). This
is constantly repeated.
":,fti
.
ONE CHARACTER ROW
'"'."'"~
LC O_3
Jl
CCLK
INTERNAL
ROW COUNTER
•
PROGRAMMABLE 1 TO 16
LINE COUNTS
Figure 16. Row Timing
HATe
LC O·3
After the row counter counts all of the rows in a frame
(programmable from 1 to 64), it starts counting out the
vertical retrace interval (programmable from 1 to 4).
----------------~
Figure 15. Line Timing
.
xxx:x:x:x::x:Kx
ONE FRAME
ROW'~6~~~~~
The line counter is driven by the character counter. It is
used to generate the line address outputs (LC O_3 ) for the
character generator. After it counts all of the lines in a
character row (programmable from 1 to 16), it increments
the row counter, and starts over again. (See Character For·
mat Section for detailed description of Line Counter
functions.)
FIRST
DISPLAY
ROW
LAST
DISPLAY
ROW
FIRST
LAST
RETRACE RETRACE
ROW
ROW
T
f
PROGRAMMABLE
1 TO 64 ROW COUNTS
PROGRAMMABLE
1 TO 4 ROW COUNTS
Figure 17. Frame Timing
The Video Suppression Output (VSP) is active during
horizontal and vertical retrace intervals.
Dot level timing circuitry must synchronize these outputs
with the video signal to the CRT Display.
12-174
8275
DMATiming
Interrupt Timing
The 8275 can be programmed to request burst DMA transfers of 1 to 8 characters. The interval between bursts is also
programmable (from a to 55 character clock periods ±1).
This allows the user to tailor his DMA overhead to fit his
system needs.
The 8275 can be programmed to generate' an intMl\ipt
request at the end of each frame. This can be used" to
reinitialize the DMA controller. If the 8275 interrupt
enable flag is set, an interrupt request will occur at the
beginning of the last display row.
The first DMA request of the frame occurs one row time
before the end of vertical retrace. DMA requests continue
as programmed, until the row buffer is filled. If the row
buffer is filled in the middle of a burst, the 8275 terminates
the burst and resets the burst counter. No more DMA
requests will occur until the beginning of the next row.
At that time, DMA requests are activated as programmed
until the other buffer is filled.
INTERNAL~
ROW
COUNTER
VRTC
~\----.;r_...J
IRQ
If, for any reason, there is a DMA underrun, a flag in the
status word will be set.
Figure 19. Beginning of Interrupt Request
IRQ will go inactive after the status register is read.
INTERNAL
ROW
LAST RETRACE ROW
COUNTER
~
FIRST DISPLAY ROW
\
ORO
tR~/\Y\/\
~
~ffi
~
~
~~
~g~
i~ i~~
~;;;
NEXT
ROW BUFFER
FILLED
~o~
---
~~ ~ ~
Figure 20_ End of Interrupt Request
ONE
ROW BUFFER
FILLED
Figure 18_ DMA Timing
A reset command will also cause IRQ to go inactive, but
this is not recommended during normal service.
Another method of reinitializing the DMA controller is to
have the DMA controller itself interrupt on terminal count.
With this method, the 8275 interrupt enable flag should not
be set.
The DMA controller is typically initialized for the next
frame at the end of the current frame.
12-175
Note: Upon power-up, the 8275 Interrupt Enable Flag may be Set.
As a result, the user's cold start routine should write a reset
command to the 8275 before system interrupts are enabled.
"
8275
l'
VISUAL ATTRIBUTES AND SPECIAL
CODES
The characters processed by the 8275 are 8-bit quantities.
The character code outputs provide the character generator
with 7 bits of address. The Most Significant Bit is the extra
bit and it is used to determine if it is a normal display
character (MSB = Ol. or if it is a Visual Attribute or Special
Code (MSB = 1).
There are two types of Visual Attribute Codes. They are
Character Attributes and Field Attributes.
Character Attribute Codes
' " ,"~" ,~~~~, "
Character attribute codes are codes that can'be'uS;:~:g'ep
erate graphics symbols without the use of a 'tha}~t>
generator. This is accomplished by selectively actiVating it\e(~~if
Line Attribute outputs (LAo_1l. the Video Suppres~ion"
output (VSP). and the Light Enable output. The dot level'
timing circuitry can use these signals to generate the proper
-"
symbols.
Character attributes can be programmed to blink or be
highlighted individually. Blinking is accomplished with the
Video Suppression output (VSP). Blink frequency is equal
to the screen refresh frequency divided by 32. Highlighting
is accomplished by activating the Highlight output (HGLT).
Character Attributes
MSB
LSB
11CCCCBH
IL
I
L _____
DOT CLOCK
-
~~~~z. RIGHT ...........
:::
02
J--
-L
----L
>......
--
-
=
i:=[
-)...... .
~ GENERATOR'~
;~~ 03 _ _ _ _ ---I--)--t=f=F~{ ~
---I
-
----1)-
--
-L
--LVERT....... V
~
L'N'
R,SGH,'srFT'R
...J-
:::::
8275
I
.-....;>--
Oor--------i
CHARACTER
HIGHLIGHT
BLINK
CHARACTER ATTRIBUTE CODE
~)
-
~
lrl q~"OR'Z,LEFTHALF
r-----..._---++----++-ll-+-'
OUT
I~
v
I_St
1-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1.1
Figure 21. Typical Character Attribute Logic
12-176
_
-
~VIDEO
.'ZATION I I - - - - - - - - - _ H , G H L I G H T
8275
,~,
,,,,~:.;:,
":}~~:"
Character attributes were designed to produce the following graphics:
CHARACTER ATTRIBUTE
CODE "CCCC"
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Above Underline
Underline
Below Underline
Above Underlihe
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
LA,
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUTPUTS
VSP
LAo
0
0
1
0
1
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
,.
,
.'-""
,
,. "'"
LTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
DESCRIPTION
SYMBOL
"
'\'
',' ,
Top Left Corner
:;
Top Right Corner
Bottom Left Corner
Bottom Right Corner
. m;Y~,i.
Top Intersect
+1""
<~'::: :': ~': ./,'
Right Intersect
Left Intersect
>1;,".
"
~~.¥' ..
Bottom Intersect
; ; . -,., . • '.
Horizontal Line
Vertical Line
:.'<:'1'-.,::";.:.
,:r"·,·
. .:.
~
:.:'
'-:;""'''.'
'"
.
..
Crossed Lines
Not Recommended *
,':.'
Special Codes
Undefined
Illegal
1
I.
Illegal
Undefined
I
I
Undefined
Illegal
I
*Character Attribute Code 1011 is not recommended for
normal operation. Since none of the attribute outputs are
active, the character Generator will not be disabled, and
an indeterminate character will be generated,
Character Attribute Codes 1101, 1110, and 1111 are illegal.
Blinking is active when B = 1.
Highlight is active when H = 1.
12-177
.
';"':
8275
Special Codes
Field Attributes
Four special codes are available to help reduce memory,
software, or DMA overhead.
The field attributes are control codes which affect the
visual characteristics for a field of characters, starting at the
character following the code up to, and including, the
character which precedes the next field attribute code, or
up to the end of the frame. The field attributes are reset
du ri ng the vertical retrace interval.
Special Control Character
MSB
1 1
1
1
o
S S
0 0
0 1
1 0
LSB
0 S S
~SPECIAL CONTROL CODE
There are six field attributes:
FUNCTION
End
End
End
End
of Row
of Row·Stop DMA
of Screen
of Screen-Stop DMA
The End of Row Code (00) activates VSP and holds it to
the end of the line.
1.
Blink - Characters following the code are caused
to blink by activating the Video Suppression output (VSP). The blink frequency is equal to the
screen refresh frequency divided by 32.
2.
Highlight -
3.
Reverse Video - Characters following the code are
Characters following the code are
caused to be highlighted by activating the Highlight output (HGLT).
caused to appear with reverse video by activating
the Reverse Video output (RVV).
The End of Row-Stop DMA Code (01) causes the DMA
Control Logic to stop DMA for the rest of the row when it
is written into the Row Buffer. It affects the display in the
same way as the End of Row Code (00).
4.
Underline - Characters following the code are
caused to be underlined by activating the Light
The End of Screen Code (10) activates VSP and holds it to
the end of the frame.
5,6.
General Purpose - There are two additional 8275
The End of Screen-Stop DMA Code (11) causes the DMA
Control Logic to stop DMA for the rest of the frame when
it is written into the Row Buffer. It affects the display in
the same way as the End of Screen Code (10).
If the Stop DMA feature is not used, all characters after an
End of Row character are ignored, except for the End of
Screen character, which operates normally. All characters
after an End of Screen character are ignored.
Enable output (L TEN).
outputs which act as general purpose, independently programmable field attributes. GPA0-1 are
active high outputs.
Field Attribute Code
MSB
1 0
LSB
U RI GTG
i~
HIGHLIGHT
BLINK
GENERAL PURPOSE
- - - - - - R E V E R S E VIDEO
L--------UNDERLINE
1 - .- - -
1
1-.
Note: If a Stop DMA character is not the last character in a burst or
row, DMA is not stopped until after the next character is
read. In this situation, a dummy character must be placed in
memory after the Stop DMA character.
H = 1 FOR HIGHLIGHTING
B = 1 FOR BLINKING
R = 1 FOR REVERSE VIDEO
U = 1 FOR UNDERLINE
GG = GPA1, GPAo
12-178
8275
~>,
The 8275 can be programmed to provide visible or invisible
field attribute characters.
If the 8275 is programmed in the visible field attribute
mode, all field attributes will occupy a position on the
screen. They will appear as blanks caused by activation of
the Video Suppression output (VSP). The chosen visual
attributes are activated after this blanked character.
Each row buffer has a correspondin~~jZl~'O-"
are 16 characters by 7 bits in size.
When a field attri bute is placed in the row \b~i~et'
DMA, the buffer input controller recognizes it:~Atr
the next character in the proper FIFO.
•
When a field attribute is placed in the Buffer Output Cho':
troller during display, it causes the controller to immediately put a character from the FIFO on the Character Code
outputs (CCO-8). The chosen Visual Attributes are also
activated.
Since the FIFO is 16 characters long, no more than 16 field
attribute characters may be used per line in this mode.
If more are used, a bit in the status word is set and the first
characters in the FIFO are written over and lost.
ABC D E
F G H I J K L M
NOPQRSTUV
Note: Since the FIFO is 7 bits wide, the MSB of any characters put
1 234 5
in it are stripped off. Therefore, a Visual Attribute or Special
Code must not immediately follow a field attribute code. If
this situation does occur, the Visual Attribute or Special
Code will be treated as a normal display character.
6 7 8 9
Figure 22. Example of the Visible Field Attribute Mode
(Underline Attribute)
If the 8275 is programmed in the invisible field attribute
mode, the 8275 FIFO is activated.
ABC D E F G H I J
NOPQRSTUV
K L M
1 234 5 6 7 8 9
Figure 24. Example of the Invisible Field Attribute
Mode (Underline Attribute)
Field and Character Attribute Interaction
Figure 23. Block Diagram Showing FIFO Activation
Character Attribute Symbols are affected by the Reverse
Video (RRV) and General Purpose (GPAO-1) field attributes. They are not affected by Underline, Blink or Highlight field attributes; however, these characteristics can be
programmed individuallv for Character Attribute Symbols.
12-179
"
8275
Cursor Timing
Device Programming
The cursor location is determined by a cursor row register
and a character position register which are loaded by command to the controller. The cursor can be programmed to
appear on the display as:
The 8275 has two programming registerS:, the
and
Register (CREG) and the Parameter Register (PRE~~'*,t
also has a Status Register (SR EG). The CommandRegis,~"
can only be written into and the Status Registers can'on'I'~::::~$::+
be read from. They are addressed as follows:
,;~:":t,~,
,rt~ J~'~
1.
2.
3.
4.
a
a
a
a
blinking underline
blinking reverse video block
non-blinking underline
non-blinking reverse video block
AO
The cursor blinking frequency is equal to the screen refresh
frequency divided by 16.
If a non-blinking reverse video cursor appears in a nonblinking reverse video field, the cursor will appear as a
normal video block.
Light Pen Detection
A light pen consists of a micro switch and a tiny light
sensor. When the light pen is pressed against the CRT screen,
the micro switch enables the light sensor. When the raster
sweep reaches the light sensor, it triggers the light pen
output.
PREG
0
Write
PREG
1
Read
SREG
1
Write
CREG
Instruction Set
The 8275 instruction set consists of 8 commands.
COMMAND
Reset
Start Display
Stop Display
Read Light Pen
If the output of the light pen is presented to the 8275
LPEN input, the row and character position coordinates are
stored in a pair of registers. These registers can be read on
command. A bit in the status word is set, indicating that
the Iight pen signal was detected. The LPEN input must be
a 0 to 1 transition for proper operation.
This has to be corrected in software.
REGISTER
Read
The 8275 expects to receive a command and a sequence
of 0 to 4 parameters, depending on the command. If the
proper number of parameter bytes are not received before
another command is given, a status flag is set, indicating an
improper command.
If a non-blinking underline cursor appears in a non-blinking
underline field, the cursor will not be visible.
Note: Due to internal and external delays, the character position
coordinate will be off by at least three character positions.
OPERATION
0
NO. OF PARAMETER BYTES
4
o
o
2
Load Cursor
2
Enable Interrupt
o
o
o
Disable Interrupt
Preset Counters
In addition, the status of the 8275 (SREG) can be read by
the CPU at any time.
12-180
8275
1.
Parameter - UUUU
Reset Command:
DATA BUS
OPERATION AO
Command
Write
1
Write
0
DESCRIPTION
Reset Command
Screen Camp
Byte 1
Screen Camp
Byte 2
0
Write
Parameters
Write
Screen Camp
0
Write
Byte 3
Screen Camp
Byte 4
0
MSB
0
0
S H
0
0 0
0
LSB
U U U U
0
000 0
000
0
H H H H H H
V
V R
U
U
L
L
M
Fc c z z z
Z
U
R
U
R R
L
L
0
1
As parameters are written, the screen composition is
defined.
FUNCTIONS
o
Normal Rows
Spaced Rows
Parameter -
2
3
1
16
LLLL
Number of Lines per Character Row
L
L
L
L
0
0
0
0
0
0
0
0
0
1
0
2
3
NO. OF LINES/ROW
16
Parameter - M
M
Parameter - HHHHHHH
Horizontal Characters/Row
H H H H H H H
0
0
0
o
Spaced Rows
S
0
0
0
LINE NUMBER 01'
UNDERLINE
R R
Action - After the reset command is written, DMA requests stop, 8275 interrupts are disabled, and the VSP
output is used to blank the screen. H RTC and VRTC continue to run. HRTC and VRTC timing are random on
power-up.
Parameter - S
o
Underline Placement
0
0
0
0
0
0
0 0
0 0
0
o
Mode 0 (Non-Offset)
NO. OF CHARACTERS
PER ROW
0
Mode 1 (Offset by 1 Count)
1
2
3
0
Line Counter Mode
LINE COUNTER MODE
Parameter - F
Field Attribute Mode
F
FIELD ATTRIBUTE MODE
o
Transparent
Non-Transparent
0
0
0
1
1
80
0
Parameter - VV
V V
o
o
0
0
0
Undefined
1
1
Undefined
a
o
CURSOR FORMAT
0
Blinking reverse video block
1
Blinking underline
Nonblinking reverse video block
Nonblinking underling
o
Vertical Retrace Row Count
Cursor Format
NO. OF ROW COUNTS PER VRTC
0
1
2
o
3
4
Parameter - RRRRRR
0
0
0
0
0
0
0
0
0
Parameter - ZZZZ Horizontal Retrace Count
Vertical Rows/Frame
R R R R R R
0
0
0
Parameter - CC
C C
0 0
0
0
NO. OF ROWS/FRAME
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
NO. OF CHARACTER
COUNTS PER HRTC
2
4
0
6
1
2
3
32
1
1
1
1
Note: uuuu MSB determines blanking of top and bottom lines
(1 = blanked, 0 = not blanked).
64
12-181
8275
2.
Start Display Comma(ld:
5.
Load Cursor Position:
DATA BUS
10PERATION AO
Command
I
Write
1
DESCRIPTION
Start Display
MSB
0 0
LSB
1
S S S
B
B
No parameters
BURST SPACE CODE
a
a
Write
0
7
15
23
31
39
47
55
a
a a
a 1
a
Write
a
o
Char. Number
Row Number
Action - The 8275 is conditioned to place the next two
parameter bytes into the cursor position registers. Status
flags not affected.
NO. OF CHARACTER CLOCKS
BETWEEN DMA REQUESTS
0 0 0
0 0
Load Cursor
Write
Parameters
SSS
S S S
OPERATION AO
Command
6.
Enable Interrupt Command:
DATA BUS
Command
10PERATION AO
DESCRIPTION
MSB
I
Enable Interrupt
1
Write
1
0
LSB
1 0
0 0 0 0
No parameters
BB
B B
BURST COUNT CODE
Action - The interrupt enable status flag is set and interrupts are enabled.
NO. OF DMA CYCLES PER
BURST
a a
a 1
a
2
4
8
7.
Action - 8275 interrupts are enabled, DMA requests begin,
video is enabled, Interrupt Enable and Video Enable status
flags are set.
3.
Disable Interrupt Command:
DATA BUS
I
OPERATION AO
Command
Stop Display Command:
I
Write
1
DESCRIPTION
MSB
Disable Interrupt 1
1
LSB
0
0
0
0
0
0
No parameters
DATA BUS
iOPERATION AO
Command
I
Write
1
DESCRIPTION
Stop Display
MSB
LSB
1
0 0 0 0 0 0
0
Action - Interrupts are disabled and the interrupt enable
status flag is reset.
No parameters
Action - Disables video, interrupts remain enabled, HRTC
and VRTC continue to run, Video Enable status flag is
reset, and the "Start Display" command must be given to
re-enable the display.
8.
Preset Counters Command:
DATA BUS
4.
Read Light Pen Command
DATA BUS
OPERATION AO
DESCRIPTION
MSB
LSB
Command
Write
1
Read Light Pen
0
Parameters
Read
Read
0
Char. Number
0
Row Number
(Char. Position in Row)
(Row Numbed
1
1 0
0
0
0
DESCRIPTION
MSB
I
Preset Counters
1
Write
1
1
LSB
1
o
0 0 0 0
No parameters
0
Action - The 8275 is conditioned to supply the contents
of the light pen position registers in the next two read
cycles of the parameter register. Status flags are not affected.
Note: Software correction of light pen position is required.
Command
iOPERATION AO
Action - The internal timing counters are preset, corresponding to a screen display position at the top left corner.
Two character clocks are required for this operation. The
counters will remain in this state until any other command
is given.
This command is useful for system debug and synchronization of clustered CRT displays on a single CPU.
12-182
8275
Status Flags
DATA BUS
MSB
Command
IE
IC -
(Improper Command) This flag is set when a
command parameter string is too long or too
short. The flag is automatically reset after a
status read.
(Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
LSB
0 IE IR LP IC VE
OU
FO
-
(Interrupt Enable) Set or reset by command. It
enables vertical retrace interrupt. It is auto·
matically set by a "Start Display" command
and reset with the "Reset" command.
VE -
IR -
(Interrupt Request) This flag is set at the begin·
ning of display of the last row of the frame if
the interrupt enable flag is set. It is reset after
a status read operation.
DU -
LP
This flag is set when the light pen input (LPEN)
is activated and the light pen registers have been
loaded. This flag is automatically reset after a
status read.
(DMA Underrun) This flag is set whenever a
data underrun occurs during DMA transfers.
Upon detection of DU, the DMA operation is
stopped and the screen is blanked until after
the vertical retrace interval. This flag is reset
after a status read.
FO - (FIFO Overrun) This flag is set whenever the
FIFO is overrun. It is reset on a status read.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias. . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
Voltage On Any Pin
With Respect to Ground . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
'COMMENT: Stresses above those listed under "Absolute Maxi·
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec·
tions of this specification is not implied.
D.C. CHARACTERISTICS
T A: O°Cto 70°C; Vee = 5V ±5%
SYMBOL
MIN.
MAX.
UNITS
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+0.5V
V
VIL
PARAMETER
VOL
Output Low Voltage
VOH
Output High Voltage
IlL
Input Load Current
IOFL
Output Float Leakage
lee
Vee Supply Current
0.45
2.4
V
V
±10
TEST CONDITIONS
IOL = 2.2 mA
IOH = -400J.l.A
J.l.A
VIN = Vee to OV
±10
J.l.A
VOUT: Vee to OV
160
mA
CAPACITANCE
TA: 25°C; Vee: GND = OV
SYMBOL
PARAMETER
MAX.
UNITS
CIN
lriput Capacitance
MIN.
10
pF
fc: 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to Vss.
12·183
TEST CONDITIONS
8275
A.C. CHARACTERISTICS
TA = O°C to 70°C; VCC = 5.0V ±5%; GND = OV
Bus Parameters (Note 1)
Read Cycle:
MIN.
SYMBOL
tAR
PARAMETER
Address Stable Before READ
tRA
Address Hold Time for READ
tRR
READ Pulse Width
Data Delay from READ
250
READ to Data Floating
20
MAX.
UNITS
ns
o
o
ns
ns
200
100
ns
MAX.
UNITS
CL = 150 pF
ns
Write Cycle:
SYMBOL
PARAMETER
MIN.
Address Stable Before WR ITE
Address Hold Time for WR ITE
tAW
tWA
tww
WR ITE Pulse Width
Data Setup Time for WR ITE
tDW
tWD
0
ns
ns
ns
0
250
ns
150
0
Data Hold Time for WR ITE
TEST CONDITIONS
ns
Clock Timing:
SYMBOL
PARAMETER
MIN.
tCLK
tKH
Clock Period
Clock High
320
120
tKL
Clock Low
120
tKR
Clock Rise
Clock Fall
5
5
tKF
Note 1: AC timings measured at VOH
MAX.
UNITS
TEST CONDITIONS
ns
ns
ns
30
ns
ns
30
= 2.0, VOL = 0.8
Write Timing
Read Timing
INVALID
INVALID
Clock Timing
Input Waveforms (For A.C. Tests)
CClK
2.4
tKF
0.45
12·184
=x >
0
2.
0.8
TEST POINTS
< .
20X=
0.8
8275
Other Timing:
).·~ttt.
SYMBOL
tcc
tHR
tLC
tAT
tVR
tlR
tRI
tKO
two
tRO
tLR
tRL
tpR
tpH
PARAMETER
MIN.
Character Code Output Delay
Horizontal Retrace Output Delay
Line Count Output Delay
Control/Attribute Output Delay
Vertical Retrace Output Delay
IROt from CCLKt
I ROt from Rdt
DROt from CCLKt
DROt from WRt
DROt from WRt
DACKt to WRt
WRt to DACKt
MAX.
UNITS
150
150
ns
ns
250
250
250
250
250
250
250
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
LPEN Rise
LPEN Hold
50
100
TEST CONDITIONS"
Note: Timing measurements are made at the following reference voltages: Output "1"::: 2.0V, "0"
CL =
CL =
CL =
CL =
50
50
50
50
pF
pF
pF
pF
CL =
CL =
CL =
CL =
CL =
CL -
50
50
50
50
50
50
pF
pF
pF
pF
pF
pF
=
O.8V.
WAVEFORMS
EXT DOT elK
CCLK·lL_ _ _ _ _ _--I
CCO_6
FIRST CHARACTER CODE
CHARACTER ---------~
_ _ _ _ _ _ _ _ _-J
GENERATOR
OUTPUT
SECOND CHARACTER CODe
r-------------, r---------~
FIRST
_____
_CHARACTER
_ _ _ _ _ _ _J
~
CHARACTER
_ _SECOND
___
_ _ _ __
ATTRIBUTES
& CONTROLS
VIDEO
(FROM SHIFT
REGISTER)
ATTRIBUTES
& CONTROLS
(FROM
SYNCHRONIZER)
FIRST CHARACTER
SECOND CHARACTER
ATTRIBUTES & CONTROLS FOR FIRST CHAR.
ATTRIBUTES & CONTROLS
FOR 2ND CHAR.
*CCLK IS A MULTIPLE OF THE DOT CLOCK AND AN INPUT TO THE 8275.
Figure 25. Typical Dot Level Timing
12-185
VIDEO
CONTROLS
AND ATTRIBUTES *
*lAO_l, VSP, lTEN, HGl T, RVV, GPAO_l
Figure 26. Line Timing
CCLK
HRTC
lCO_3
i-----PROGRAMMABlE FROM 1 TO 16 LlNES--<-··INTERNAL - - - - " ' \
ROW
COUNTER _ _ _ _J
!.-------------\I------"'
PRESENT ROW
I'-------------\I------J
Figure 27. Row Timing
CClK
----\
l:---AST
~
INTERNAL
RETRACE
ROW
ROW
COUNTER
VRTC
Figure 28. Frame Timing
12·186
8275
,,
Ie
\
AO
CCLK
cc
c_"_A_RA_c_T_E_R____4IX
~____C_"_A_R_AC_T_E_R____
LAST RETRACE
O-S _____
LCO_3
FIRST RETRACE
FIRST LINE COUNT
----------4------------
HRTe
INTERNAL
IRa
----------------+----------------
COUN~~:------------LA-~-T-O-'S~P-LA-~-R-:-W--~t-,_R~~~~~~~~
Figure 29. Interrupt Timing
CClK
~tKat_
ORa
J
\\.______. .
LPEN--~lJ'---Figure 30. DMA Timing
12·187
t.
inter
8278
PROGRAMMABLE KEYBOARD INTERFACE
• Simultaneous Keyboard and Display
Operations
• N·Key Rollover with Programmable
Error Mode on Multiple New Closures
• Interface Signals for Contract and
Capacitive Coupled Keyboards
• 16· or 18·Character 7·Segment Display
Interface
• 128·Key Scanning Logic
• Right or Left Entry Display RAM
• 10.7 msec Matrix Scan Time for 128
Keys and 6 MHz Clock
• Depress/Release Mode Programmable
• 8·Character Keyboard FJFO
• Interrupt Output on Key Entry
The Intel@ 8278 is a general purpose programmable keyboard and display interface device designed for use with 8·bit
microprocessors such the MDS·80™ and MCS·85™. The keyboard portion can provide a scanned interface to
128-key contact or capacitive-coupled keyboards. The keys are fully debounced with N-key rollover and
programmable error generation on multiple new key closures. Keyboard entries are stored in an
8-character FIFO with overrun status indication when more than 8 characters are entered. Key entries set
an interrupt request output to the master CPU.
The display portion of the 8278 provides a scanned display interface for LED, incandescent, and other
popular display technologies. Both numeric displays and simple indicators may be used. The 8278 has a
16X4 display RAM which can be loaded or interrogated by the CPU. Both right entry calculator and left entry typewriter display formats are possible. Both read and write of the display RAM can be done with autoincrement of the display RAM address.
PIN CONFIGURATION
RL
Vee
07-0 0
CLR
cs
B3
B2
NC
B,
So
KCL
M.
M.
M,
M3
D.
PIN NAMES
Ali. Wft
A.
REm'
X,.Xz
SYNC
RL
CLR
KCL
Me-Mo
83-BO
ERROR
IRQ
1m
BP
BLOCK DIAGRAM
DATA BUS
READ. WRITE STROBES
CHIP SELECT
CONTROL/DATA SELECT
RESET INPUT
FREQ. REFERENCE INPUT
HIGH FREQUENCY OUTPUT
CLOCK
KEYBOARD RETURN LINE
CLEAR ERROR
KEY CLOCK
MATRIX SCAN LINES
DISPLAY OUTPUTS
ERROR SIGNAL
INTERRUPT REQUEST
HYSTERESIS
TONE ENABLE
SCAN
OUTPUTS
,-c,
M.
DATA
BUS
MO
M2
0,
M,
02
M.
03
Voo
0,
NC
D.
ERROR
D.
IRQ
07
HYS
x,
4
GND
X2
+6 PWR_
GND-
© Intel Corporation, 1978
12-188
INTERNAL
BUS
TO
DISPLAY
DIGITS
8278
PIN DESCRIPTION
The 8278 is packaged in a 40-pin DIP. The following is a
brief functional description of each pin.
12-19
Three-state, bi-directional data bus
lines used to transfer data and commands between the CPU and the
8278.
10
Write strobe which enables the master CPU to write data and commands between the CPU and the
8278.
8
Read strobe which enables the master CPU to read data and status from
the 8278 internal registers.
CS
6
Chip select input used to enable
reading and writing to the 8278.
Ao
9
Address input used by the CPU to
indicate control or data.
4
A low signal on this pin resets the
8278.
GNO
2,3
Inputs for crystal, L-C or external
timing signal to determine internal
oscillator frequency.
PRINCIPLES OF OPERATION
23
Interrupt Request Output to the
master CPU. In the keyboard mode
the IRQ line goes low with each
FIFO read and returns high if there
is still information in the FIFO or an
ERROR has occurred.
IRQ
Mo-M6
27-33
22
SYNC
ERROR
24
Error signal. This line is high whenever two new key closures are detected during a single scan or when
too many characters are entered
into the keyboard FIFO. It is reset by
a system RESET pulse or by a "1"
input on the CLR pin or by the
CLEAR ERROR command.
CLR
39
Input used to clear an ERROR condition in the 8278.
BP
21
Tone enable output. Thisline is high
for 10ms following a valid key
closure; it is set high and remains
high during an ERROR condition.
Vee, VDD
Matrix scan outputs. These outputs control a decoder wh ich scans
the key matrix columns and the 16
display digits. Also, the Matrix scan
outputs are used to multiplex the
return lines from the key matrix.
Input from the multiplexer which indicates whether the key currently
being scanned is closed.
RL
KCL
Signal
Description
Pin No.
00-07
WR
Description
Pin No.
Signal
34
11
35-38
Hysteresis output to the analog detector. (Capacitive keyboard configuration). A "0" means the key currently being scanned has already
been recorded.
Key cloCk output to the analog detector (capacitive keyboard configuration) used to reset the detector
befo re scan n i n g a key.
+5 volt power input: +5V ± 10%.
40,26
20,7
Signal ground.
The following is a description of the major elements of the
Programmable Keyboard/Display interface device. Refer
to the block diagram in Figure 1.
1/0 Control and Data Buffers
The I/O control section uses the CS, Ao, RO, and WR lines
to control data flow to and from the various internal
registers and buffers (see Table 1), All data flow to and
from the 8278 is enabled by CS. The 8-bits of information
being transferred by the CPU is identified by Ao. A logic
one means information is command or status. A logic zero
means the information is data. RO and WR determine the
direction of data flow through the Data Bus Buffer (OBB)'
The OBB register is a bi-directional 8-bit buffer register
which connects the internal 8278 bus buffer register to the
external bus. When the chip is not selected (CS = 1) the
OBB is in the high impedance state. The OBB acts as an
input when (RO, WR, CS) = (1, 0, 0) and an output when
(RO, WR, CS) = (0, 1, 0).
CS
Ao
o
o
o
o
o
WR
RD
1
o
o
Condition
Read OBB Data
Read STATUS
o
o
0
1
Write Command to OBB
X
X
X
Disable 8278 Bus is
High Impedance
Write Data to OBB
High frequency (400 KHz) output
signal used in the key scan to detect
a closed key (capacitive keyboard
configuration).
Scan Counter
These four lines contain binary
coded decimal display information
synchronized to the keyboard column scan. The outputs are for
multiplexed digital displays.
The scan counter provides the timing to scan the
keyboard and display. The four MSB's (M3-M6) scan the
display digits and provide column scan to the keyboard via
a 4 to 16 decoder. The three LSB's (Mo-M2) are used to
multiplex the row return lines into the 8278.
12-189
8278
TO TONE GENERATOR
ANALOG
DETECTOR
I
RlLHys5
KCL
BP
ERROR
M,
CLR
8278
<
8
I
ANALOG
MULTIPLEXER
Mo
IRa
---8---
Do-D7
80BO, B085 OR 8048
MASTER
Tal
PROCESSOR
r--
ViR
SYNC
Ali
M,
Ao
,
,,
4 TO 16
cs
h
,,
16
DECODE
RESET
M,
f-'-
B, .... 8 0
'--I
I
I
CAPACITIVE
III
KEYBOARD
MATRIX
~'TSCAN
8 OR 16 DIGIT DISPLAY
Figure 1. System Configuration for Capacitive·Coupled Keyboard
Keyboard Debounce and Control
The 8278 system configuration is shown in Figure 2. The
rows of the matrix are scanned and the outputs are
multiplexed by the 8278. When a key closure is detected,
the debounce logic waits about 12 msec to check if the key
remains closed. If it does,the address of the key in the
matrix is transferred into a FI FO buffer.
FIFO and FIFO Status
The 8278 contains an 8X8 FIFO character buffer. Each
new entry is written into a successive FIFO location and
each is then read out in the order of entry. A FIFO status
register keeps track of the number of characters in the
FIFO and whether it is full or empty. Too many reads or
key entries will be recognized as an error. The status can
be read by a RD with CS low and Ao high. The status logic
also provides a IRQ signal to the master processor
whenever the FIFO is not empty.
Display Address Registers and Display RAM
The Display Address registers hold the address of the
word currently being written or read by the CPU and the
two 4-bit nibbles being displayed. The read/write
addresses are programmed by CPU command. They also
can be set to auto increment after each read or write. The
display RAM can be directly read by the CPU after the
correct mode and address is set. Data entry to the display
can be set to either left or right entry.
TO TONE GENERATOR
j
BP
I
RL
ERROR
CLR
M,
IRQ
Mo
MUL TIPLEXEA
8278
<8080,8085 OR 8048
MASTER
Tal
PROCESSOR
-
8
I
DIGITAL
---8 ---
Do-D7
,---
ViR
RO
Ao
M,
4 TO 16
DECODE
CS
RESET
M,
B, . ... 80
III
I 1--
4 TO 16
DECODE
-16---1
8 OR 16 DIGIT DISPLAY
Figure 2. System Configuration for Contact Keyboard
12·190
,,
~
,
'~,
'--I
J
I
CONTACT
16 DIGIT SCAN
I
KEYBOARD
MATRIX
I
8278
8278 COM MAN OS
The 8278 operating mode is programmed by the master
CPU using the Ao, WR, and 00-07 inputs as shown below:
3 . . ___
AD. CS
AI=1
AI=O
AUTO increment
no AUTO increment
Write Display Command
V_A_L_ID___...JXI....._I_NV_A_L_ID_
/
\
Where AI indicates Auto Increment and A3-Ao is the
address of the next display character to be read out.
CODE
I, I
0
I 0 I AI I A3 IA21 A, IAo I
Where AI indicates Auto Increment and A3-Ao is the
address of the next display character to be written.
Clear/Blank Command
INVALID
X
VALID
X
CODE I, I 0 I, I UI) I 50 ICO ICF ICE 1
INVALID
Where the command bits are defined as follows:
The master CPU presents the proper command on the 0007 data lines with Ao=1 and then sends a WR pulse. The
command is latched by the 8278 on the rising edge of the
WR and is decoded internally to set the proper operating
mode.
CE = Clear ERROR
CF = Clear FIFO
CD = Clear Display to all High
BD = Blank Display to all High
UD = Un blank Display
The display is cleared and blanked following a Reset.
COMMAND SUMMARY
Keyboard/Display Mode Set
8278 Status Read
CODE
The status register in the 8278 can be read by the master
CPU using the Ao, RD, and 00-07 inputs as shown below:
1 0 1 0 1 0 1 N 1
EI I 1 0I K
1
where the mode set bits are defined as follows:
K-
o1-
o-
o1-
the keyboard mode select bit
normal key entry mode
special function mode: Entry on key closure and on
key release
the display entry mode select bit
left display entry
right display entry
AO'Cll~
\\.-------J/
Ro
the interrupt request (IRQ) output enable bit.
0 - enable IRQ output
1 - disable IRQ output
VALID
I-
E-
o1N-
o1-
DO-D7~ VALID _
the error mode select bit
error on multiple key depression
no error on multiple key depression
The 8278 places 8-bits of status information on the 00-07
lines following (Ao, CS, RD) = 1, 0 , 0 inputs from the
master.
the number of display digits select
16 display digits
8 display digits
NOTE: The default mode following a RESET input
is all bits zero:
Status Format
153 1521 5, I So I 5IKE I05FI15F 1
07 06 05 D. 03 02 0, Do
Read FIFO Command
Where the status bits are defined as follows:
IBF = Input Buffer Full Flag
OBF = Output Buffer Full Flag
KE = Keyboard Error Flag (multiple depression)
B = BUSY Flag
53-SO = FIFO Status
Read Display Command
CODE 10 I ' I, 1AI I A31 A21 A, lAO I
12-191
8278
Status Description
Data Read Sequence
The S3-S0 status bits indicate the numberofentries (Oto 8)
in the 8-level FI FO. A FIFO overrun will lock status at 1111.
The overrun condition will prevent further key entries until
cleared.
Before reading data, the master CPU must send a
command to select FIFO or Display data. Following the
command, the master must read STATUS and test the
BUSY flag and the OBF flag to verify that the 8278 has
responded to the previous command. A typical DATA
READ sequence is as follows:
A multiple key closure error will set the KE flag and
prevent further key entries until cleared.
The IBF and OBF flags signify the status of the 8278 data
buffer registers used to transfer information (data, status
or commands) to and from the master CPU.
BUSY
The IBF flag is set when the master CPU writes Data or
Commands to the 8278. The IBFfiag is cleared by the 8278
during its response to the Data or Command.
J
L
---II
OBF
L - I_ _
The OBF flag is set when the 8278 has output data ready
for the master CPU. This flag is cleared by a master CPU
Data READ.
READ D'SPLAY
OR F,FO COMMAND
FROM MASTER
The Busy flag in the status register is used as a LOCKOUT signal to the master processor during response to
any command or data write from the master.
r
r
FIRST
DATA BYTE
READY
r
MASTER
READS DATA
NEXT
BVTEREADY
8278
PROCESS'NG
NEXT BYTE
After the first read following a Read Display or Read FIFO
command, successive reads may occur as soon as OBF
rises.
The master must test the Busy flag before each read
(during a sequence) to be sure that the 8278 is ready with
valid DATA.
8278 Data Write
The ERRORand TONE outputs from the 8278 are set high
for either type of error. Both types of error are cleared by
the CLR input, by the CLEAR ERROR command, or by a
reset. The FIFO and Display buffers are cleared
independently of the Errors.
The master CPU can write DATA to the 8278 Display
buffers by using the Ao, WR and 00-07 inputs as follows:
AD.
3 _____
CS
FIFO status is used to indicate the number of characters in
the FIFO and to indicate whether an error has occurred.
Overrun occurs when the entry of another character into a
full FIFO is attempted. Underrun occurs when the CPU
tries to read an empty FIFO. The character read will bethe
last one entered. FIFO status will remain at 0000 and the
error condition will not be set.
VA_L_'D
_ _ _-.JX'--_'_NV_A_L_'O_
\'-------11
8278 Data Read
The master CPU can read DATA from the 8278 FIFO or
Display buffers by using the Ao, RD, and 00-07 inputs as
follows:
AD.~
AD
==x_____
--'C
VA_L_'D_ _ _ _
\\...-----J/
The master CPU presents the Data on the 00-07 lines with
Ao=O and then sends a WR pulse. The data is latched by
the 8278 on the rising edge of WR.
Data Write Sequence
Before writing data to the 8278, the master CPU must first
send a command to select the desired display entry mode
and to specify the address of the next data byte. Following
the commands, the master must read STATUS and testthe
BUSY flag (B) and IBF flag to verify that the 8278 has
responded. A typical sequence is shown below:
BUSY
J
L
'BF
r
The master sends a RD pulse with Ao=O and CS=O and the
8278 responds by outputing data on lines 00-07. The data
is strobed by the trailing edge of RD.
WR ITE D ISPLA y
COMMAND
12-192
8278
READY
FOR
COMMAND
DR DATA
MASTER
OAT A WR ITE
FIRST BYTE
r
8278
READY
I
MASTER WR ITES
NEXT BYTE
8278
READY
8278
INTERFACE CONSIDERATIONS
Scanned Keyboard Mode
With N-key rollover each key depression is treated
independently from all others. When a key is depressed
the debounce logic waits for a full scan of 128 keys and
then checks to see if the key is still down. If it is, the key is
entered into the FIFO.
COUNT
Mo
M,
M.
X
HVS{
KCL
RL SAMPLED
1
t
X
n
t
X
n
t
X
n
t
n
X
t
n
X
n
i
Figure 3. Keyboard Timing
If two key closures occur during the same scan the
ERROR output is set, the KE flag is set in the Status word,
the TONE output is activated and I RQ is set, and no further
inputs are accepted. This condition is cleared by a high
signal on the CLEAR input or by a system RESET input or
by the CLEAR ERROR command.
In the special function mode both the key closure and the
key release cause an entry to the FIFO. The release is
entered with the MSB=1.
Any key entry triggers the TONE output for 10ms.
The HYS and KCL outputs enable the analog multiplexer
and detector to be synchronized for interface to capacitive
coupled keyboards.
SCAN CYCLE
IRQ
BP
ERRDR
KEY 1
DEPRESSED
KEY 1
ENTERED
KEY 1
READ BY MASTER
Figure 4. Key Entry and Error Timing
12·193
KEV 2
DEPRESSED
KEV 3
DEPRESSED
8278
Data Format
Right Entry
In the scanned keyboard mode, the code entered into the
FIFO corresponds to the position or address of the switch
in the keyboard. The MSB is relevant only for special
function keys in which code "0" signifies closure and "1"
signifies release. The next four bits are the column count
which indicates which column the key was found in. The
last three bits are from the row counter.
Right entry is the method used by most electronic
calculators. The first entry is placed in the right-most
display character. The next entry is also placed in the
right-most character after the display is shifted left one
character. The left-most character is shifted off the end
and is lost.
KEY CODING
1ST ENTRY
BIT
2ND ENTRY
3RD ENTRY
Display
Display data is entered into a 16x4 display register and
may be entered from the left, from the right or into specific
locations in the display register. A new data character is
put out on Bo-B3 each time the M6-M3 lines change (I.e.,
once every O.75ms with a 6 MHz crystal). Data is blanked
during the time the column select lines change by raising
the display outputs. Output data is positive true.
14
I
I I
I
I
11
11
a
I I
17TH ENTRY
I I
1
14
15
114 1 15 1 16 1
14
2
3
I I
3
15
4
116
3
2
12 1 3
13
2
I I
a
4
I
DISPLAY
a-RAM
ADDRESS
11
I
a
15
16TH ENTRY
18TH ENTRY
15
1
15
a
15
1
16
1
17 1
0
1
17 1 18 1
Left Entry
The left entry mode is the simplest display format in that
each display position in the display corresponds to a byte
(or nibble) in the Display RAM. Address 0 in the RAM is the
left-most display character and address 15 is the rightmost display character. Entering characters from position
zero causes the display to fill from the left. The 17th
character is entered back in the left-most position and
filling again proceeds from there.
DISPLAY
CHARACTER
Note that now the display position and register address do
not correspond. Consequently, entering a character to an
arbitrary pOSition in the Auto Increment mode may have
unexpected results. Entry starting at Display RAM address
o with sequential entry is recommended. A Clear Display
command should be given before display data is entered if
the number of data characters is not equal to 16 (or 8) in
this mode.
o
I
B.-B,
',------,I ,___. . ", ,'---....", ',------,I '_---'I '_---'I ,___
Figure 5. Display Timing
12-194
8278
Auto Increment
In the Left Entry mode, Auto Incrementing causes the
address where the CPU will next write to be incremented
by one and the character appears in the next location.
With non-Auto Incrementing the entry is both to the same
RAM address and display position. Entry to an arbitrary
address in the Left Entry - Auto Increment mode has no
undesirable side effects and the result is predictable:
In the Right Entry mode, Auto Incrementing and non
Incrementing have the same effect as in the Left Entry
except that the address sequence is interrupted:
DISPLAY
~-r~-r--=-,.::.-r~-r::.....,~-r~O~~RAM
1ST ENTRY
.
.
L_L--'_....L._"--..L_...L_l_l~1
ADDRESS
2ND ENTRY LI_"--'_....L._l.--L_..L_l....L.I_2....J
DISPLAY
7-.- RAM
1ST ENTRY rl..:.l-r-=--r::.....,,.::.-r-=--r--=-,...::.-,~I ADDRESS
4
COMMAND
10010101
I !
ENTER NEXT AT LOCATION 5 AUTO INCREMENT
3456
2ND ENTRY LI_l-..LI_2-'_...L_"--,_ _IL......L.I---I
012
3RD ENTRY IL _"--'_...L_'---..L__..L_L.......J
COMMAND
10010101
3
4TH ENTRY
ENTER NEXT AT LOCATION 5 AUTO INCREMENT
0234567
3RDENTRYLI_l-..LI_2-'_....L._"--'_....L._"-~
4THENTRy I_
L l -..LI_2-'_....L._"--,_3....L.1_4....L.1---I
Starting at an arbitrary location operates as shown below:
DISPLAY
7....-- RAM
ADDRESS
4
COMMAND
rl-=--,.....::..,....::..-r--=-,.....:-r~.-::.....,r-'--=,I
10010101
L_L-....L_...L_L-....L._..L._L....J.
ENTER NEXT AT LOCATION 5 AUTO INCREMENT
1
4
1ST ENTRY
5
6
0
11
4
2ND ENTRY
I I
8TH ENTRY 14 1 5
9TH ENTRY
15
I6
11
I2
I 7
I8
11
1 2
I3
I 6 I7 I8 I9 I 2 I 3 I4 I
Entry appears to be from the initial entry point.
12-195
8278
'COMMENT: Stresses above thos~listi!du
Maximum Ratings" may cause perman~t'. It has an active
internal pullup to keep it high
until a switch closure puliS it
low.
OUT Ao-OUT A3 These two ports are the outputs
OUT Bo-OUT B3 for the 16 x 4 display refresh
registers. The data from these
outputs is synchronized to the
scan lines (Slo-Sl31 for multiplexed digit displays. The two 4
bit ports may be blanked independently. Thesetwo ports may
also be considered as one 8 bit
port.
BD
Blank Display. This output is
used to blank the display during
digit switching or by a display
blanking command.
PRINCIPLES OF OPERATION
The following is a description of the major elements of the
8279 Programmable Keyboard/Display interface device.
Refer to the block diagram in Figure 1.
110 Control and Data Buffers
The I/O control section uses the CS, Ao, RD and WR lines
to control data flow to and from the various internal
registers and buffers. All data flow to and from the 8279 is
enabled by CS. The character of the information, given or
desired by the CPU, is identified by Ao. A logic one
means the information is a command or status. A logic
zero means the information is data. RD and WR determine
the direction of data flow through the Data Buffers. The
Data Buffers are bi-directional buffers that connect the
internal bus to the external bus. When the chip is not
selected (CS = 1), the devices are in a high impedance
state. The drivers input during WR - CS and output during
RD -CS.
Control and Timing Registers and Timing Control
These registers store the keyboard and display modes and
other operating conditions programmed by the CPU. The
modes are programmed by presenting the proper
command on the data lines with Ao = 1 and then sen~
a WR. The command is latched on the rising edge of WR.
12·200
8279/8279·5
The command is then decoded and the appropriate
function is set. The timing control contains the basic
timing counter chain. The first counter is a .;. N prescaler
that can be programmed to match the CPU cycle time to
the internal timing. The prescaler is software programmed
to a value between 2 and 31. A value which yields an
internal frequency of 100 kHz gives a 5.1 ms keyboard
scan time and a 10.3 ms debounce time. The other
counters divide down the basic internal frequency to
provide the proper key scan, row scan, keyboard matrix
scan, and display scan times.
SOFTWARE OPERATION
8279 commands
The following commands program the 8279 operating
modes. The commands are sent on the Data Bus with CS
low and Ao high and are loaded to the 8279 on the rising
edge of WR.
Keyboard/Display Mode Set
MSB
Scan Counter
Code:
The scan counter has two modes. In the encoded mode,
the counter provides a binary count that must be
externally decoded to provide the scan lines for the
keyboard and display. In the decoded mode, the scan
counter decodes the least significant 2 bits and provides a
decoded 1 of 4 scan. Note than when the keyboard is in
decoded scan, so is the display. This means that only the
first 4 characters in the Display RAM are displayed.
In the encoded mode, the scan lines are active high
outputs. In the decoded mode, the scan lines are active
low outputs.
101010iDIDIKIKIKI
Where DD is the Display Mode and KKK is the Keyboard
Mode.
DD
o
o
8 8-bit character display -
0
16 8-bit character display -
o
8 8-blt character display -
16 8-blt character display -
Return Buffers and Keyboard Debounce
and Control
Left entry
Left entry'
Right entry
Right entry
For description of right and left entry, see Interface
Considerations. Note that when decoded scan is set in
keyboard mode, the display is reduced to 4 characters
independent of display mode set.
The 8 return lines are buffered and latched by the Return
Buffers. In the keyboard mode, these lines are scanned,
looking for key closures in that row. If the debounce
circuit detects a closed switch, it walts about 10 msec to
check if the switch remains closed. If it does. the address
of the switch in the matrix plus the status of SHIFT and
CONTROL are transferred to the FIFO. In the scanned
Sensor Matrix modes, the contents of the return lines is
directly transferred to the corresponding row of the
Sensor RAM (FIFO) each key scan time. In Strobed Input
mode, the contents of the return lines are transferred to
the FIFO on the rising edge of the CNTLlSTB line pulse.
KKK
0
0
0
0
0
0
0
0
0
Encoded Scan Keyboard -
2 Key Lockout
Decoded Scan Keyboard -
2-Key Lockout
Encoded Scan Keyboard -
N-Key Rollover
Decoded Scan Keyboard -
N-Key Rollover
0
Encoded Scan Sensor Matrix
0
Strobed Input, Encoded Display Scan
Decoded Scan Sensor Matrix
0
FIFO/Sensor RAM and Status
This block is a dual function 8 x 8 RAM. In Keyboard or
Strobed Input modes, it is a FIFO. Each new entry is
written into successive RAM positions and each is then
read in order of entry. FIFO status keeps track of the
number of characters in the FIFO and whether it IS full or
empty. Too many reads or writes will be recognized as an
error. The status can be read by an RD with CS low and
Ao high. The status logic also provides an IRQ signal
when the FIFO is not empty. In Scanned Sensor Matrix
mode, the memory is a Sensor RAM. Each row of the
Sensor RAM is loaded with the status of the corresponding row of sensor in the sensor matrix. In this mode, IRQ is
high if a change in a sensor is detected.
LSB
Strobed Input, Decoded Display Scan
Program Clock
Code:
Where PPPPP is the prescaler value 2 to 31. The
programmable prescaier divides the external clock by
PPPPP to get the basic internal frequency. Choosing a
divisor that yields 100 KHz will give the specified scan and
debounce times. Default after a reset pulse (but not a
program clear) is 31.
Display Address Registers and Display RAM
The Display Address Registers hold the address of the
word currently being written or read by the CPU and the
two 4-bit nibbles being displayed. The read/write
addresses are programmed by CPU command. They also
can be set to auto increment after each read or write. The
Display RAM can be directly read by the CPU after the
correct mode and address is set. The addresses for the A
and B nibbles are automatically updated by the 8279 to
match data entry by the CPU. The A and B nibbles can be
entered independently or as one word. according to the
mode that is set by the CPU. Data entry to the display can
be set to either left or right entry. See Interface
Considerations for details.
Read FIFO/Sensor RAM
Code:
I 0 I0 I I I I I I
11
AI
X
A
A
A
X = Don't Care
Where AI is the Auto-Increment flag for the Sensor RAM
and AAA is the row that is going to be read by the CPU. AI
and AAA are used only if the mode is set to Sensor Matrix.
This command is used to specify that the source of data
reads (CS • RD • Ao) by the CPU is the FIFO/Sensor
RAM. No additional commands are necessary as long as
12-201
"Default after reset.
8279/8279·5
clear all positions of the Display RAM to a programmable
code. All ones, all zeros and hexadecimal 20 are possible.
The 2 least significant bits of CD are also used to specify
the blanking code (see below).
data is desired from the FIFO/Sensor RAM. Another
command is necessary if reading is desired from a
different row than has been selected. If AI is a one, the row
select counter will be incremented after each read so the
next read will be from the next Sensor RAM row.
r
In the Auto Increment mode for reading data from the
FIFO/Sensor RAM, each read advances the address by
one so that the next read is from the next character. This
Auto Incrementing has no effect on the display.
c
:
Read Display RAM
Code:
10 11 11 1AI I A 1A 1A 1A
I
Write Display RAM
'-11"""1-0"r-IO--'I-A-IIr-A-rl-A"T"I-A"T"IA--'I
Where AI is the Auto-Increment flag for the Display RAM
and AAAA is the character that the CPU is going to write
next. The addressing and Auto-Increment are identical to
Read Display RAM. The difference is that Write Display
RAM does not affect the source of CPU reads. The CPU
will read from whichever RAM (Display or FIFO/Sensor)
was last specified. This command will, however, change
the location the next Display RAM read will be from if that
source was specified.
Display Write Inhibit/Blanking
Code:
BLI
B
A
Do,,,,",,)
AB = Hex 20 (0010 0000)
1
1
All Ones
Clearing the display takes approximately 160 MS. During
this time the CPU cannot write to the Display RAM. The
MSB of the F I Fa status word will be set during this time.
C F set the FIFO status to empty and resets the interrupt
output line. After execution of a clear command with C F
set, the Sensor Matrix mode RAM pOinter will be set to row
O.
CA has the combined effect of Co and CF. C A uses the CD
clearing code to determine how to clear the Display RAM.
CA also resets the internal timing chain to resynchronize
it.
End Interrupt/Error Mode Set
Code:
11 11 11 1E Ix Ix Ix Ix I
X = Don't care.
For the sensor matrix modes this command lowers the
IRQ line and enables further writing into RAM. (The IRQ
line would have been raised upon the detection of a
change in a sensor value. This would have also inhibited
further writing into the RAM until resetl.
For the N-key rollover mode - if the E bit is programmed
to "1" the chip will operate in the special Error mode. (For
further details, see Interface Considerations Section.)
1 0 11 1 X IIW IIW 1 BL 1
A
All Z,m"X "
0
Enable clear display when = 1 (or by CA = 1)
Where AI is the Auto-Increment flag for the Display RAM
and AAAA is the character that the CPU is going to read
next. Since the CPU uses the same counter for reading
and writing, this command also sets the next write location
and Auto-Increment mode. This command is used to
specify the display RAM as the data source for CPU data
reads. If AI is set, the character address will be
incremented after each read (or write) so that the next
read (or write) will be from (to) the next character.
Code:
,~,
1
B
Status Word
Where IW is Inhibit Writing (nibble A or B) and BL is
Blanking (nibble A or B). If the display is being used as a
dual4-bit display, then it is necessary to mask one ofthe 4bit halves so that entries to the Display from the CPU do
not affect the other half. The IW flags allow the
programmer to do this. It is also useful to be able to blank
either half when that half is not to be displayed. The BL
flags blank the display. The next command sets the output
code to be used as a "blank". Default after reset is all zeros.
Note that to blank a display formatted as a single S-bit
output, it is necessary to set both BL flags to entirely blank
the display. A "1" sets the flag. Reissuing the command
with a "0" resets the flag.
Clear
The status word contains the FIFO status, error, and
display unavailable signals. This word is read by the CPU
when Ao is high and CS and RD are low. See Interface
Considerations for more detail on status word.
Data Read
Data is read when Ao, CS and RD are all low. The source
of the data is specified by the Read FIFO or Read Display
commands. The trailing edge of RD will cause the address
of the RAM being read to be incremented if the AutoIncrement flag is set. FIFO reads always increment (if no
error occurs) independent of AI.
Data Write
Code:
Where Co is Clear Display, C F is Clear FIFO Status
(including interrupt), and CA is Clear All. CD is used to
Data that is written with Ao, CSand WR low is always
written to the Display RAM. The address is specified by the
latest Read Display or Write Display command. AutoIncrementing on the rising edge of WR occurs if AI set by
the latest display command.
12-202
8279/8279·5
INTERFACE CONSIDERATIONS
Scanned Keyboard Mode, 2·Key Lockout
There are three possible combinations of conditions
that can occur during debounce scanning. When a key is
depressed, the debounce logic is set. Other depressed
keys are looked for during the next two scans. If none
are encountered, it is a single key depression and the
key position is entered into the FIFO along with the
status of CNTL and SHIFT lines. If the FIFO was empty,
IRQ will be set to signal the CPU that there is an entry in
the FIFO. If the FIFO was full, the key will not be entered
and the error flag will be set. If another closed switch is
encountered, no entry to the FIFO can occur. If all other
keys are released before this one, then it will be entered
to the FIFO. If this key is released before any other, it
will be entirely ignored. A key is entered to the FIFO
only once per depression, no matter how many keys
were pressed along with it or in what order they were
released. If two keys are depressed within the debounce
cycle, it is a simultaneous depression. Neither key will
be recognized until one key remains depressed alone.
The last key will be treated as a single key depression.
Increment flag is set to zero, or by the End Interrupt
command if the Auto-Increment flag is set to one.
Note: Multiple changes in the matrix Addressed by (SLO-3
=OJ may cause multiple interrupts. (SLo =0 in the Decoded
Model. Reset may cause the 8279 to see multiple changes.
Data Format
In the Scanned Keyboard mode, the character entered
into the FIFO corresponds to the position of the switch
in the keyboard plus the status of the CNTL and SHIFT
lines (non-inverted). CNTL is the MSB of the ct'laracter
and SHIFT is the next most significant bit. The next
three bits are from the scan counter and indicate the
row the key was found in. The last three bits are from the
column counter and indicate to which return line the key
was connected.
LSB
MSB
I
CNTL ISH I FTI
SCANNED KEYBOARD DATA FORMAT
Scanned Keyboard Mode, N·Key Rollover
With N-key Rollover each key depression is treated
independently from all others. When a key is depressed,
the debounce circuit waits 2 keyboard scans and then
checks to see if the key is still down. If it is, the key is
entered into the FIFO. Any number of keys can be
depressed and another can be recognized and entered
into the FIFO. If a simultaneous depression occurs, the
keys are recognized and entered according to the order
the keyboard scan found them.
Scanned Keyboard -
In Sensor Matrix mode, the data on the return lines is
entered directly in the row of the Sensor RAM that
corresponds to the row in the matrix being scanned.
Therefore, each switch postion maps directly to a Sensor
RAM position. The SHIFT and CNTL inputs are ignored in
this mode. Note that switches are not necessarily the only
thing that can be connected to the return lines in this
mode. Any logic that can be triggered by the scan lines
can enter data to the return line inputs. Eight multiplexed
input ports could be tied to the return lines and scanned by
the 8279.
Special Error Modes
For N-key rollover mode the user can program a special
error mode. This is done by the "End InterruptiError Mode
Set" command. The debounce cycle and key-validity
check are as in normal N-key mode. If during a single
debounce cycle, two keys are found depressed, this is
considered a simultaneous multiple depression, and sets
an error flag. This flag will prevent any further writing into
the FIFO and will set interrupt (if not yet set). The error flag
could be read in this mode by reading the FIFO STATUS
word. (See "FIFO STATUS" for further details.) The error
flag is reset by sending the normal CLEAR command with
CF = 1.
MSB
RL71 RLal RLsl RL41 RL31 RL21 RL,
IRLo
In Strobed Input mode, the data is also entered tothe FIFO
from the return lines. The data is entered by the riSing
edge of a CNTLlSTB line pulse. Data can come from
another encoded keyboard or simple switch matrix. The
return lines can also be used as a general purpose strobed
input.
MSB
RL71 RLal RLsl RL41 RL31 RL21 RL,
Sensor Matrix Mode
In Sensor Matrix mode, the debounce logiC is inhibited.
The status of the sensor switch is inputted directly to the
Sensor RAM. In this way the Sensor RAM keeps an image
of the state of the switches in the sensor matrix. Although
debouncing is not provided, this mode has the advantage
that the CPU knows how long the sensor was closed and
when it was released. A keyboard mode can only indicate
a validated closure. To make the software easier, the
designer should functionally group the sensors by row
since this is the format in which the CPU will read them.
The IRQ line goes high if any sensor value change is
detected at the end of a sensor matrix scan. The IRQ line is
cleared by the first data read operation if the Auto-
LSB
LSB
IRLo
Display
Left Entry
Left Entry mode is the simplest display format in that each
display position directly corresponds to a byte (or nibble)
in the Display RAM. Address 0 in the RAM is the left-most
display character and address 15 (or address 7 in 8
character display) is the right most display character.
Entering characters from position zero causes the display
to fill from the left. The 17th (9th) character is entered back
in the left most position and filling again proceeds from
there.
12-203
8279/8279·5
o
1st entry
o
2nd entry
16th entry
17thentry
18thentry
1
1jTI- - L..:.L.l
1
~=
o
1
o
1
o
1
14 15_0isplay
-II]
2
RAM
1ST
Address
===IIJ
14 15
[2J2I ====:@E]
Command
10010101
14 15
3
1
4
2
3
2
3
4
1
1
11 121
1
5
7-Display
6
I II
1
11 121
0
5
1
5
1
I
1
6
1
~:d~ess
7
6
I
1
4
1
7
1
1
Enter next at Location 5 Auto Increment
~= ===~
1
0
14 15
3rd entry
~= ==~
4th entry
2
11 121
0
LEFT ENTRY MODE
(AUTO INCREMENT)
1
3
1
2
11 121
4
1
3
1
5
6
13 1
4
5
7
I
1
7
6
1 3 14 1 1
1
LEFT ENTRY MODE
(AUTO INCREMENT)
Righi Entry
Right entry is the method used by most electronic
calculators. The first entry is placed in the right most
display character. The next entry is also placed in the right
most character after the display is shifted left one
character. The left most character is shifted off the end
and is lost.
2
1st entry
1
0
2nd entry
14 15
=
I
entry
14 15
In the Right Entry mode, Auto Incrementing and non
Incrementing have the same effect as in the Left Entry
except if the address sequence is interrupted:
1st entry
I
O_Display
ITJ----I II I
3
2
1
1
4
1
5
1
6
1
0 __ Display
7
1 11 1
~:d~ess
23456701
RAM
IIIi
2nd entry
Address
11 121
23456701
Command
10010101
11 121
Enter next at Location 5 Auto Increment
o
16th entry
GIil ===]
1
17th entry
34567012
1
2
13 14 15
14115116
14 15
3rd entry
I
4
0
4th entry
[3E[ ===115i161171
2
18th entry
3
~=
15
0
I I I31
11 12
567
13141
0
1
I
2
3
I
11 121
1
RIGHT ENTRY MODE
(AUTO INCREMENT)
1
===1161171181
Starting at an arbitrary location operates as shown below:
o
RIGHT ENTRY MODE
(AUTO INCREMENT)
Command
10010101
Note that now the display position and register address do
not correspond. Consequently, entering a character to an
arbitrary position in the Auto Increment mode may have
unexpected results. Entry starting at Display RAM address
o with sequential entry is recommended.
1
1
1
2
1
3
1
4
1
5
1
6
1
7 _ Display
1
1
234
5
6
7
0
1st entry
23456701
Aulo Increment
In the Left Entry mode, Auto Incrementing causes the
address where the CPU will next write to be incremented
by one and the character appears in the next location.
With non-Auto Incrementing the entry is both to the same
RAM address and display position. Entry to an arbitrary
address in the Auto Increment mode has no undesirable
side effects and the result is predictable:
12-204
~:d~ess
Enter next at Location 5 Auto Increment
2nd entry
I 1
11
121
1 1
·&h entry
14151617181112131
9th entry
15161718191213141
RIGHT ENTRY MODE
(AUTO INCREMENT)
827918279·5
I n a Sensor Matrix mode, a bit i~"lfllr'.',
word to indicate that at least one sensd~'cJosl,l
is contained in the Sensor RAM.
"'';'\'.);!'
Entry appears to be from the initial entry pOint.
8/16 Character Display Formats
In Special Error Mode the S/E bit is showing tk~e(.(;Q
and serves as an indication to whether a sim~jt~~
multiple closure error has occurred.
v {'!c,.",
If the display mode is set to an 8 character display, the on
duty-cycle is double what it would be for a 16 character
display (e.g., 5.1 ms scan time for 8 characters vs. 10.3 ms
for 16 characters with 100 kHz internal frequency).
FIFO STATUS WORD
G. FIFO Status
FIFO status is used in the Keyboard and Strobed Input
modes to indicate the number of characters in the FIFO
and to indicate whether an error has occurred. There are
two types of errors possible: overrun and underrun.
Overrun occurs when the entry of another character into a
full FIFO is attempted. Underrun occurs when the CPU
tries to read an empty FIFO.
The FIFO status word also has a bit to indicate that the
Display RAM was unavailable because a Clear Display or
Clear All command had not completed its clearing
operation.
APPLICATIONS
KEYBOARD
MATRIX
SHIFT
CONTROL
8 COLUMNS
a/
RETURN
LINES
INT
SHIFT CNTL
INT
Ro- 7
VDD
DATA BUS
a·BIT
MICRO-
PROCESSOR
SYSTEM
DATA
BUS
aL
AD
CONTROLS {
AODRESS{
BUS
CLOCK
WR
RESET
CS
AO
ClK
VSS
°0_7
lOR
lOW
5 0 _3
8279
3
8 ROWS
Ha
3- 8 DECODER
~
~~
3 lSB·
4/
SCAN LINES
(14
RESET
cs
4-16 DECODER
AO
elK 8 0 _3
A O_ 3
BD
BLANK
Ilh'SPLAY
V'6
7-
~
ADDRESSES
(OECODEDI
4
/
DISPLAY
CHARACTERS
DATA
DISPLAY
·00 not drive the keyboard decoder with the MSB of the scan lines.
12-205
I
8279/8279·5
ABSOLUTE MAXIMUM RATINGS·
*COMMENT:
Maximum Ratings" may cause permanefttJi;yn
device. This is a stress rating only and f~rti::'tfcihil
tion of the device at these or any other cond(tlbiis.~b
Ambient Temperature . . . . . . . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . -65°C to 125°C
Voltage on any Pin with
Respect to Ground . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1 Watt
cation is not implied. Exposure to absolute maxirrwri1·:
rating conditions for extended periods may affect device
reliabilitv.
D.C. CHARACTERISTICS
TA =
ooe to 70°C, Vss =
OV, Note 1
Symbol
Parameter
Min.
Max.
Unit
V IL1
Input Low Voltage for
Return Lines
-0.5
1.4
V
VIL2
Input Low Voltage for All Others
-0.5
0.8
V
VIHl
Input High Voltage for
Return Lines
2.2
VIH2
Input High Voltage for All Others
2.0
VOL
Output Low Voltage
VO H
Output High Voltage on Interrupt
Line
IILl
Input Current on Shift, Control and
Return Li nes
+10
-100
pA
pA
IIL2
Input Leakage Current on All Others
±10
pA
VIN = Vee to OV
IOFL
Output Float Leakage
±10
pA
VOUT = Vee to OV
lee
Power Supply Current
120
mA
Test Cond itions
V
V
0.45
3.5
V
Note 2
V
Note 3
VIN = Vee
VIN = OV
Notes:
1. 8279, V ee
~ +5V ±5%; 8279·5, Vee ~ +5V ±10%.
2. 8279, IOL ~ 1.6mA; 8279'5, IOL ~ 2.2mA.
3. 8279, IOH ~ -100",A; 8279·5, IOH ~ -400",A.
CAPACITANCE
SYMBOL
TEST
TYP.
MAX.
UNIT
Cin
Input Capacitance
5
10
pF
Vin=Vee
Cout
Output Capacitance
10
20
pF
Vout=Vee
12-206
TEST CONDITIONS
8279/8279·5
A.C. CHARACTERISTICS
TA = O°C to 70°C, VSS = OV, (Note 1)
Bus Parameters
Read Cycle:
8279-5
8279
Symbol
Min.
Parameter
Max.
Min.
Unit
Max.
tAR
Address Stable Before READ
50
0
ns
tRA
Address Hold Time for READ
5
0
ns
ns
250
tRR
READ Pulse Width
tRO[2]
Data Delay from READ
420
300
150
ns
tAO[2]
Address to Data Valid
450
250
ns
tOF
READ to Data Floating
tReY
Read Cycle Time
10
10
100
ns
100
j1S
1
1
Write Cycle:
8279-5
8279
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tAW
Address Stable Before WR ITE
50
0
tWA
Address Hold Time for WR ITE
20
0
ns
tww
WR ITE Pulse Width
400
250
ns
tow
Data Set Up Time for WR ITE
300
150
ns
two
Data Hold Time for WR ITE
40
0
ns
ns
Notes:
1. 8279, Vee = +5V ±5%; 8279-5, Vec = +5V ±10%.
2. 8279, CL = 100pF; 8279·5, CL = 150pF.
Other Timings:
8279
8279·5
Symbol
Parameter
tq,w
Clock Pulse Width
230
120
nsec
tCY
Clock Period
500
320
nsec
Keyboard Scan Time:
Keyboard Debounce Time:
Key Scan Time:
Display Scan Time:
Min.
Max.
Min.
Digit·on Time:
Blanking Time:
Internal Clock Cycle:
5.1 msec
10.3 msec
80 j1sec
10.3 msec
Input Waveforms For A.C. Tests
'~=x ?
2.0
TEST POINTS
O.B
0.45
12·207
<
2.0
O.B
x=
Max.
Unit
480 j1sec
160 j1sec
10 j1sec
8279/8278·5
WAVEFORMS
Read Operation
Ao,CS
(SYSTEM'Ii, ' \ ,
1-____________________________________~~----------------------------ADDRE~M?~
....--tAR--I~·>-----------tRCV
---1----------1
1---~-tRR-----1
(R EAD CONTROLI
~tOF
1----tAo---~~1
Write Operation
(SYSTEM'S
ADDR ESS BUS)
~------------------>-----tww----~
(WRITE CONTROLl
- tOW - - - - . :
DATA BUS _ _ _ _ _ _ _ _ DATA
_ _ _ _ _ _ _ _- J\ )
(INPUT)
MAY CHANGE
f',
-
two
DATA
_DATAVALlD~V~____________________
_
'~~
Clock Input
12-208
MAY CHANGE
8294
DATA ENCRYPTION UNIT
• 80·Byte/Sec Data Conversion Rate
• Single 5V ± 10% Supply
• 64·Bit Data Encryption Using 56·Bit
Key
• Peripheral to MCS·58™, MCS·80™, and
MCS.48™ Processors
• DMA Interface
• 3 Interrupt Output to Aid in Loading
and Unloading Data
• Compatible with Algorithm Specified
in Federal Information Processing
Data Encryption Standard
• 7·Bit User Output Port
• Encode and Decode Modes Available
The Intel@ 8294 Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encode and decode
64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard.
The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit cipher words. The operation
is· reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the 8294; however, the 56-bit key is user-defined and may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294 in 8-bit bytes by way of the system data
bus. A DMA interface and 3 interrupt outputs are available to minimize software overhead associated with data
transfer. Also, by using the DMA interface, 2 or more DEUs may be operated in parallel to achieve effective system
baud rates which are virtually any multiple of 80 bytes/second. The 8294 also has 7-bit TTL compatible output port for
user-specified functions.
Because the 8294 is compatible with the NBS encryption standard it can be used in a variety of electronic funds
transfer applications as well as other electronic banking and data handling applications where data must be encrypted.
PIN
CONFIGURATION
RESET
Ne
Vee
Ne
DACK
DRO
SRO
DAV
Ne
P.
P5
BLOCK DIAGRAM
PIN NAMES
PIN NAME
FUNCTION
RD,WR
os
DATA BUS
READ, WRITE STROBES
CHIP SELECT
~
CONTROl/DATA SELECT
OJ-DO
RESEr
Xl, X2
SYNC
ORO, DACK
SRO, DAV, ceMP
Ps-Po
Vee, Voo, GND
DATA
BUS
RESET INPUT
FREQUENCY REFERENCE INPUT
HIGH FREQUENCY OUTPUT
DMA REQUEST, DMA ACKNOWLEDGE
INTERRUPT REQUEST OUTPUTS
OUTPUT PORT LINES
+5V POWER, GND
AO
SRO
DAV
ceMP
PO
PO-P6
VDD
Ne
RESET - - - - '
SYNC - - - . . . ,
ceMP
DRO
Ne
D7
GND
+5V - - . . POWER - - - .
GND - - . -
12-209
INTERNAL
BUS
8294
COMMAND SUMMARY
FUNCTIONAL DESCRIPTION
In non-DMA mode, the conversion sequence is as follows:
Enter New Key
1. A mode command is issued to enable the desired interrupt outputs.
OP CODE:
MSB
2. A new key command is issued followed by 8 data inputs
to initialize the key. Each byte must have odd parity.
LSB
This command is followed by' a data inputs which are
retained in the key buffer (RAM) to be used in encrypting
and decrypting data.
Encode Data
101 0 1111 1010 10 10 I
OP CODE:
MSB
3. The encrypt data or decrypt data command is issued to
set the DEU in the desired mode.
After thIs, data conversions are made by writing 8 data
bytes and then reading back a converted data bytes. Any of
the above commands may be issued between data conversions to change the basic operation of the DEU; e.g., a
decrypt data command could be issued to change the DEU
from encrypt mode to decrypt mode without changing
either the key or the interrupt outputs enabled.
LSB
COMMAND AND DATA TRANSFER
This command puts the 8294 into the encrypt mode.
Four internal registers are addressable by the master: 2 for
input, 2 for output. Access and function of these registers
are described below.
Decode Data
RD WR CS AO
1
OPCODE:
MSB
0
0
LSB
This command puts the 8294 into the decrypt mode.
X
OP CODE:
MSB
the
the
the
the
0
0
X
Data Output Buffer - Data read from this register will be
the output of the encrypter/decrypter function.
LSB
where:
is
is
is
is
1
0
X
0
0
0
0
Data Input Buffer - Data written to this register is interpreted as part of a key, as data to be encrypted/decrypted,
or as a DMA block count, depending on the command
sequence preceding the write.
Set .Mode
A
B
C
D
0
1
Register
Data input buffer
Data output buffer
Status output buffer
Command input buffer
Don't care
Status Output Buffer - DEU status is available in this register at all times.
OAV (Output Available) interrupt enable
SRO (Service Request) interrupt enable
DMA (Direct Memory Access) transfer enable
CCMP (Conversion Complete) interrupt enable
STATUS
7
BIT:
FUNCTION: XXX
This command determines which interrupt outputs will be
enabled. A "1" in bits A, B, or D will enable the OAV,
SRO, or CCMP interrupts respectively. A "1" in bit C will
allow DMA transfers. When bit C is set the OAV and SRO
interrupts should also be enabled (bits A,B = 1). Following
the command in which bit C, the DMA bit, is set the 8294
will expect one data byte to specify the number of a·byte
blocks to be converted using DMA.
Write to Output Port
OPCODE:
MSB
5
4
3
2
xxx
XXX
KPE
HS
DEC
o
IBF
OBF
OBF -
Output buffer full; OBF = 1 indicates that the
output buffer contains encrypter/decrypter output
data. It is set false when the data is read.
IBF -
Input buffer full; IBF is set true when a command
or data is written to the input buffer. The DEU
sets th is flag false when it has accepted the input
byte. No data should be written when IBF = 1.
DEC -
Decode; indicates whether the DEU is in encrypt
or decrypt mode. Decrypt: DEC = TRUE;
Encrypt: DEC = FALSE.
HS -
Handshake flag; this flag is used in the data transfer protocol.
KPE -
Key Parity Error; after a new key has been entered,
the DEU will use this flag in conjunction with the
HS flag to indicate correct or incorrect parity.
LSB
This command causes the 7 least significant bits of the
command byte to be latched as output data on the 8294
output port.
6
Command Input Buffer - Commands
written to this register.
12-210
to
the
DEU are
8294
MASTER/SLAVE INTERFACE
Figures 1 through 4 illustrate four interface configurations used in Master/Slave data transfers. In all cases SRQ will be true
(if enabled) and IBF will be false when the DEU is ready to accept data or commands.
iNT_---------------,
INTERFACE TO
8080, 80B5, 8048,
OR OTHER
a-BIT PROCESSOR
{D~-~
WR------..
RD
MASTER
PROCESSOR
B294
INTERFACE
+5V
8294
cs
AO
AO~
CCMP~~~-C
L-_ _.....
Figure 1. Polling Interface
Figure 2. Single Interrupt Interface
+5V
MASTER
PROCESSOR
INTERFACE
DO07
Ail
ViR -----01
CS--.....-OI
DAV I---<~-i:~.
AO----o~
Figure 3. Dual Interrupt Interface
DO07
DO-D7
(B)
RD
RD
ViR
CS
AO
MASTER
PROCESSOR
8294
INTERFACE
SRO
AOA7
ORO
DAV
ABA,S
DACKl)
DACK1
DACK
*DMARO IS FOR MEMORY TO DEU DATA TRANSFER
DMAR1 IS FOR DEU TO MEMORY DATA TRANSFER
Figure 4. DMA Interface
12·211
8294
INTERFACE TIMING
Figures 5 through 8 illustrate recommended protocol sequences and timing for transferring commands and data between the
master processor and the 8294.
SRO
IBF
Figure 5. Single Byte Command
ceMP
SRO
IBF
HS
LflSL __ J-1L....-_ _
SRO
--ILILJL ____ nL....--_
:J
L
IBF
KPE ______________
'N_V_AL_'_O__________--J~
AO'
r-----,
--------------------~I
_____
LlL_n_____
.JLJl_.JlL--_ __
OAV
_ _ _ _ _r
1 ILJr-1LJr IL
OBF
_ _ _ _ _1r-1LJr-lLJr IL
n--U --u ---- u -- ____ .Il...
I
LnJ-lf
CHECKLf
KPE
WR
I~
KEY
KEY--·lJ KEY
~
nATA
nATA
nATA
NEW
KEY
8 DATA WRITES
COMMAND
Figure 6. New Key Command
Figure 7. Encode/Decode data
CCMP ____________________________________~r_
HS
SRO
OAV
OMAR
OACK
Tl'---_ _ _ _--'r
Ln.nJ· .. lL......--_ __
nmrL
--I1J···UL...11--U-···UU···-ULf ···---'Ur--
RD·
SET
OMA
MODE
DMA
BLOCK
COUNT (n)
8 DMA READS
8DMAWRITES
~------~--------~
REPEATED n TIMES
Figure 8. DMA Sequence
12·212
8 DATA READS
MICROCOMPUTER SUPPORT SYSTEMS'
TABLE OF
CONTE~TS
MICROCOMPUTER DEVELOPMENT SYSTEMS -INTELLEC® SERIES II
Model 210 Intellec® Series II Microcomputer Development System, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Model 220 Intellec® Series II Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Model 230 Intellec® Series II Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Expansion Chassis Intellec® Series II Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Model 210 Enhancement Kit Intellec® Series II Microcomputer Development System . . . . . . . . . . . . . . . . . . . 13-15
Model 770 Printer Intellec@ Series II Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
System Monitor Intellec® Series II Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . . . . • . 13-18
ROM Editor/Assembler Intellec@ Series II Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . 13-20
ISIS-II Diskette Operating System Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
PL/M-80 High Level Programming Languagelntellec® Resident Compiler ........... , .............. 13-24
FORTRAN-80 8080/8085 ANS FORTRAN 77 Intellec® Resident Compiler. . . . . . . . . . . . . . . . . . . . . . .. 13-27
MCS-48™ Diskette-Based Software Support Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31
MICROCOMPUTER DEVELOPMENT SYSTEMS
Intellec® Prompt 48™ MCS-48™ Microcomputer Design Aid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-34
Intellec® Prompt 80/85™ 8080/8085 Microcomputer Design Aid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39
ICE-30™ 3001 MCU In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .. 13-44
ICE-41 TM UPI-41TM In-CircuitE'mulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-47
ICE48™ MCS-48™ In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-49
MDS-EM1 8021 Emulation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - ........ "
13-54
ICE-80™ 8080 In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-57
ICE-85™ MCS-85™ In-Circuit Emulator . . . . . . . . . . . . ',' . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . 13-63
Insite™ User's Program Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . .".. . . . . . . . . . . . . . . . . . . . . . . .. 13-67
UPP-103 Universal PROM Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-71
Intellec® High Speed Paper Tape Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-73
SDK-85 MCS-85™ System Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-75
TEST AND INSTRUMENTATION SYSTEMS
I.IScope TM 820 Microprocessor System Console. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-80
I.IScope TM Probe 8080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-84
MICROCOMPUTER TRAINING PROGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-86
13-2
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
MODEL 210
INTELLEC® SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
ROM-based Monitor, Assembler and Editor
Low-cost development system for MCS-80™,
MCS-85™ and MCS-48™microprocessor families
Self-Test Diagnostic capability
Compact 4-slot chassis
Standard MULTIBUS™ with multiprocessor and
DMA capabilities
Single LSI electronics board with CPU, 32K bytes
RAM memory and 4K bytes ROM memory
Easy upgrade to other Intellec Series II Systems
Built-In Interfaces for TTY, CRT, Printer, HighSpeed Paper Tape Reader/Punch and Universal
PROM Programmer
Compatible with standard Inteliec/iSBC Expansion Modules
Eight-level nested, maskable priority interrupt system
Software compatible with previous Intellec systems
The Intellec Series II Model 210 Microcomputer Development System Is a low-cost, fully-supported development system providing basic hardware and software support for development of products based around Intel's MCS-80 or
MCS-85 microprocessor families. Through optional software, this development capability can be extended to products
based on the MCS-48 family of microprocessors.
Using the user-supplied system console (TTY or equivalent), the product designer may enter and correct his program's
source code, then assemble and begin execution, all using the Model 210 ROM-resident Editor/Assembler. MCS·80
and MCS·85 debugging is accomplished through system monitor debug commands. Completed programs may be
punched to paper tape for loading into the user's system or programmed into PROM using the optional Intellec
Universal PROM Programmer.
13·3
MODEL 210
MODEL 210 HARDWARE DESCRIPTION
interrupt controller, operating in a polled mode, nested
to the primary 8259.
The Intellec Series II Model 210 is a compact, 4" tabletop chassis with 4-slot cardcage, power supply, and two
printed circuit cards. The CPU, interrupt, I/O and bus interface circuitry are all fashioned from Intel's high technology LSI components and located on one PC board.
Known as the integrated processor board (IPB), it occupies the first slot in the cardcage. A second PC board
(the parallel I/O board - Pia) containing additional I/O
interface logic is mounted on the rear panel. The remaining 3 slots in the cardcage are available for system expanSion.
The second part of the I/O subsystem consists of the interface logic provided on the Pia board itself. Utilizing
Intel's UPI-41 programmable peripheral controller, the
Pia board provides device interfaces for:
•
•
•
•
Printer
High-Speed Paper Tape Reader
High-Speed Paper Tape Punch
Universal PROM Programmer
Communication between the Pia and IPB is maintained
over a separate 8-bit bidirectional data bus. Connectors
for the 4 devices specified above, as well as the two
serial channels, are mounted directly on the Pia.
The heart of the IPB is an Intel NMOS 8-bit microprocessor, the 8080A-2, running at 2.6 MHz. 32K bytes of
RAM memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with
system bootstrap, "self-test" diagnostics and the Intellec Series II System Monitor. The 8-level vectored priority interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259 interrupt controller,
the interrupt system may be user-programmed to respond to individual needs.
User control is maintained through a front panel consisting of a power switch and indicator, reset/boot
switch, run/halt light, and 8 interrupt switches and indicators. The front-panel circuit board is attached directly
to the IPB, allowing the 8 interrupt switches to connect
to the primary 8259, as well as the Intellec Series II Bus.
All Intellec Series II models implement the industrystandard MULTIBUS. It enables several bus masters,
such as CPU and DMA devices, to share the bus and
memory by operating at different priority levels. Resolution of bus exchanges is synchronized by a bus clock
signal which is derived independently from processor
clocks. Read/write transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microprocessor family.
The I/O subsystem in the Model 210 consists of two
parts. Two serial channels are provided directly on the
IPB itself. Each channel is RS232 compatible and is
capable of running asynchronously from 110 to 9600
baud or synchronously from 150 to 56K baud. One channel contains current loop adapters for teletype compatibility. Both channels are implemented using Intel's 8251
USART. They can be programmatically selected to perform a variety of I/O functions.
All standard Model 210 software is ROM based to eliminate costly delays of loading paper tape. The capabilities of the System Monitor with its "self-test"
diagnostics, Text Editor and MCS-80/MCS-85 or MCS-48
ROM Assemblers are described on pages 13-19 to 13-22
of this catalog.
Baud rate selection is accomplished programmatically
through an Intel 8253 Interval Timer. The 8253 also
serves as the real-time clock for the entire system. I/O
activity is signaled to the system through a second 8259
SIMPLIFIED IPB BLOCK DIAGRAM
13-4
MODEL 210
SPECIFICATIONS
PHYSICAL
Dimensions:
Weight:
1/0 Interfaces:
2 Serial 1/0 Channels, RS232C, at 110-9600 baud
(asynchronous) or 150-56K baud (synchronous). Baud
rates and serial format fully programmable using Intel
8251 USARTs. Serial Channel 1 additionally provided
with 20 mA current loop.
Parallel 1/0 interfaces provided for paper tape punch,
paper tape reader, printer, and Universal PROM Programmer.
Interrupts:
8-level, maskable, nested priority interrupt network
initiated from front panel or user-selected devces.
Direct Memory Access (DMA):
Standard capability on MULTI BUS; implemented for
user-selected DMA devices through optional DMA
module - maximum transfer rate of 2 MHz.
Memory Access Time:
RAM: 585 ns
PROM: 450 ns
19.13" (48.59 cm) deep x 17.37" (44.12
cm) wide x 4.81" (12.22 cm) high
45 Ib (20.5 kg)
ELECTRICAL
DC Power Supply:
Volts
Supplied
+ 5 ±5%
+12 ±5%
-12 ±5%
-10 ±5%
Amps
Supplied
24
2.0
0.3
1.0
Typical
System Requirements
3.5
0.1
0.05
0.1
AC Requirements: 50-60 Hz, 115/230 VAC
ENVIRONMENTAL
Operating Temperature: 0° to 35°C (95°F)
EQUIPMENT SUPPLIED
Model 210 Chassis
Integrated Processor Board (IPB)
Parallel 1/0 Board (PIO)
ROM-Resident System Monitor
Auxiliary ROM Board with MCS-80/MCS-85 Assembler
and Text Editor
PROM Programming Software (Paper Tape)
Assembler Cross Reference Program (Paper Tape)
A Guide to Microcomputer Development Systems
(9800558)
Model 210 User's Guide (9800557)
Hardware Interface Manual (9800555)
8080/8085 Assembly Language Manual (9800301)
Monitor Source Listing (9800605)
Schematic Drawings (9800554)
HOST PROCESSOR (IPB)
8080A-2 based, operating at 2.600 MHz.
RAM:
32K, expandable to 64K with SBC-032 RAM
board (System Monitor occupies 62K through
64K).
ROM:
4K (2K in monitor, 2K in boot/diagnostic), expandable with addition of 20K auxiliary ROM
board containing Text Editor and Assembler.
Bus:
MULTIBUS, maximum transfer rate of 5 MHz.
Clocks: Host Processor, crystal controlled at 2.6 MHz.
Bus Clock, crystal controlled at 9.8304 MHz.
ORDERING INFORMATION
PRODUCT CODE
DESCRIPTION
MDS-210
Intellec Series II Model 210
Microcomputer Development
System
.
13-5
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
MODEL 220
INTELLEC® SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Complete Microcomputer Development System
in one package for MCS·aO™, MCS·85™ and
MCS·48™ microprocessor families
Elght·level nested, maskable priority interrupt sys·
tem
Powerful ISIS·II Diskette Operating System with
Relocating Macro Assembler, Linker and Locater
Integral CRT with detachable upper/lower case
"typewriter" style full ASCII keyboard
Self· Test Diagnostic capability
Integral 250K·byte floppy disk with total storage
capacity expandable to over 2M bytes
Standard MULTIBUSTM with multiprocessor and
DMA capability
Single LSI electronics board with CPU, 32K bytes
RAM memory and 4K bytes ROM memory
Compatible with standard Inteliec/iS8C Expan.
sion Modules
Bullt·in Interfaces for Hlgh·Speed Paper Tape
Reader/Punch, Printer and Universal PROM Pro·
grammer
Software compatible with previous Intellec Sys·
tems
The Intellec Series II Model 220 is a complete microcomputer development system integrated into one compact
package. It includes a CPU with 32K bytes of RAM memory, 4K bytes of ROM memory, a 2000-character CRT, detach·
able full ASCII keyboard with cursor controls and upperllower case capability, and a 250K-byte floppy diskette drive.
Powerful ISIS·II Diskette Operating System software allows the Model 220 to be used quickly and efficiently for as·
sembly and debugging of programs for Intel's MCS·80, MCS-85 or MCS-48 microprocessor families without the need
for handling paper tape. ISIS-II performs all file handling operations for the user, leaving him free to concentrate on the
details of his own application. When used in conjunction with an optional in-circuit emulator (ICE™) module, the
Model 220 provides all the hardware and software development tools necessary for the rapid development of a microcomputer based product.
13-6
MODEL 220
The CRT is a 12-inch raster scan-type monitor with a
50/60 Hz vertical scan rate and 15.5 kHz horizontal scan
rate. Controls are provided for brightness and contrast
adjustments. The interface to the CRT is provided
through an Intel 8275 single-chip, programmable CRT
controller. The master processor on the IPB transfers a
character for display to the 10C, wtiere it is stored in
RAM. The CRT controller reads a line at a time into its
line buffer through an Intel 8257 DMA Controller and
then feeds one character at a time to the character generator to produce the video signal. Timing for the CRT
control is provided by an Intel 8253 Interval Timer. The
screen display is formatted as 25 rows of 80 characters.
The full set of ASCII characters are displayed, including
lower-case alphas.
MODEL 220 HARDWARE DESCRIPTION
The Intellec Series II Model 220 is a packaged, highly
integrated microcomputer development system consisting of a CRT chassis with 6-slot cardcage, power
supply, fans, cables, single floppy diskette drive and
two printed circuit cards. A separate, full ASCII
keyboard is connected with a cable. The master CPU
card contains its own microprocessor, memory, I/O, interrupt and bus interface circuitry, fashioned from Intel's high-technology LSI components. Known as the integrated processor board (IPB), it occupies the first slot
in the cardcage. A second, slave CPU card, is responsible for all remaining I/O control, including the CRT and
keyboard interface and floppy disk control. This card,
mounted on the rear panel, also contains its own microprocessor, RAM and ROM memory and I/O interface,
thus in effect creating a dual processor environment.
Known as the I/O controller (IOC), the slave CPU card
communicates with the IPB over an 8-bit bidirectional
data bus, thus leaving the remaining 5 slots in the cardcage available for system expansion.
The keyboard interfaces directly to the 10C processor
via an 8-bit data bus. The keyboard contains an Intel
UPI-41 Universal Peripheral Interface which scans the
keyboard, encodes the characters and buffers the characters to provide N-key rollover. The keyboard itself is a
high quality typewriter-style keyboard containing the
full ASCII character set. An upperllower case switch
allows the system to be used for document preparation.
Cursor control keys are also provided.
The heart of the IPB is an Intel NMOS 8-bit microprocessor, the 8080A-2, running at 2.6 MHz. 32K bytes of RAM
memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with
system bootstrap, "self-test" diagnostics and the Intellec Series II System Monitor. The 8-level vectored priority interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259 interrupt controller,
the interrupt system may be user-programmed to respond to individual needs.
The floppy disk drive is controlled by an Intel 8271
single-chip, programmable floppy disk controller. It
transfers data via an Intel 8257 DMA Controller between
an 10C RAM buffer and the diskette. The 8271 handles
reading and writing of data, formatting diskettes and
reading status, all upon appropriate commands from the
10C microprocessor.
A UPI-41 Universal Peripheral Interface on the 10C board
performs similar functions to the UPI-41 on the PIO
board in the Model 210. It provides interface for other
standard Intellec peripherals, including:
The I/O subsystem in the Model 220 consists of two
parts: the 10C card and two serial Channels on the IPB
itself. Each serial channel is RS232 compatible and is
capable of running asynchronously from 110 to 9600
baud or synchronously from 150 to 56K baud. Both may
be connected to a user-defined data set or data terminal.
One channel contains current loop adapters. Both channels are implemented using Intel's 8251 USART. They
can be programmatically selected to perform a variety of
I/O functions. Baud rate selection is accomplished programmatically through an Intel 8253 Interval Timer. The
8253 also serves as a real-time clock for the entire
system. I/O activity through both serial channels is
signaled to the system through a second 8259 interrupt
controller, operating in a polled mode, nested to the
primary 8259.
•
•
•
•
Printer
High-Speed Paper Tape Reader
High-Speed Paper Tape Punch
Universal PROM Programmer
Communication between the IPB and 10C is maintained
over a separate, 8-bit bidirectional data bus. Connectors
for the devices named above, as well as the two serial
channels, are mounted directly on the 10C itself.
User control is maintained through a front panel consisting of a power switch and indicator, reset/boot
switch, run/halt light, and 8 interrupt switches and indicators. The front-panel circuit board is attached directly
to the IPB, allowing the 8 interrupt switches to connect
to the primary 8259, as well as the Intellec Series II Bus.
The remainder of system I/O activity takes place in the
10C. The 10C provides interfaces for the CRT, keyboard,
integral floppy disk and standard Intellec peripherals, including printer, high-speed paper tape reader/punch and
Universal PROM Programmer.The 10C contains its own
independent microprocessor, also an 8080A-2. This CPU
controls all I/O operations, as well as supervising communications with the IPB. 8K bytes of ROM contain all
I/O control firmware. 8K bytes of RAM are used for CRT
screen refresh storage and the floppy disk buffer. These
do not occupy any space in Intellec Series II main
memory since the 10C is a totally independent microcomputer subsystem.
All Intellec Series II models implement the industrystandard MULTIBUS. It enables several bus masters,
such as CPU and DMA devices, to share the bus and
memory by operating at different priority levels. Resolution of bus exchanges is synchronized by a bus clock
signal which is derived independently from processor
clocks. Read/write transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microcomputer family.
The Model 220 may be expanded to 64K of RAM and up
to 2% million bytes of on-line diskette storage.
13-7
MODEL 220
CABLE BUS TO IPB
I/O CONTROLLER (IOC)
ROM:
4K (2K in monitor, 2K in boot/diagnostic).
Bus:
MULTIBUS, maximum transfer rate of 5 MHz.
Clocks: Host Processor, crystal controlled at 2.6 MHz.
Bus Clock, crystal controlled at 9.8304 MHz.
I/O Interfaces:
2 Serial I/O Channels, RS232C, at 110-9600 baud
(asynchronous) or 150-56K baud (synchronous). Baud
rates and serial format fully programmable using Intel
8251 USARTs. Serial Channel 1 additionally provided
with 20 mA current loop.
Parallel I/O interfaces provided for paper tape punch,
paper tape reader, printer, and Universal PROM Programmer.
Interrupts:
8-levei, maskable, nested priority interrupt network
initiated from front panel or user-selected devces.
Direct Memory Access (DMA):
Standard capability on MULTIBUS; implemented for
user-selected DMA devices through optional DMA
module - maximum transfer rate of 2 MHz.
Memory Access Time:
RAM: 585 ns
PROM: 450 ns
Diskette System Capacity: 250K bytes (Formatted)
Diskette Performance:
Diskette System Transfer Rate: 160K bits/sec.
Diskette System Access Time:
Track-to-Track: 10 ms
Average Random Positioning: 260 ms
Rotational Speed: 360 rpm
Average Rotational Latency: 83 ms
Recording Mode: FM
SPECI.FICATIONS
PHYSICAL
Dimensions:
Weight:
Keyboard:
Weight:
19.13" (48.59 cm) deep x 17.37" (44.12
cm) wide x 15.81" (40.16 cm) high
86 Ib (39 kg)
9" (22 cm) deep x 17.37" (44.12 cm)
wide x 3.0" (7.62 cm) high
6 Ib (3 kg)
ElECTRICAL
DC Power Supply:
.
Volts
Supplied
+ 5 ±5%
+12 ±S%
-12 ±5%
-10 ±5%
+15 ±5%
+24 ±5%
Amps
Supplied
30
2.5
0.3
1.5
1.5
1.7
Typical
System Requirements
7.5
0.2
0.05
0.15
1.3·
1.2·
Not available on bus .
AC Requirements: 50-60 Hz, 115/230 VAC
ENVIRONMENTAL
Operating Temperature: 0° to 35°C (95°F)
HOST PROCESSOR (IPB)
8080A-2 based,operating at 2.600 MHz.
RAM:
32K, expandable to 64K with SBC-032 RAM
boards (System Monitor occupies 62K through
64K).
13-8
MODEL 220
EQUIPMENT SUPPLIED
Model 220 Chassis
Integrated Processor Board (IPB)
I/O Controller Board (IOC)
CRT and Keyboard
250K-byte Floppy Disk Drive
ROM Resident System Monitor
ISIS-II System Diskette with MCS-80/MCS-85
Macro Assembler
A Guide to Microcomputer Development Systems
(9800558)
Installation and Service Guide (9800559)
ISIS-II System User's Guide (9800306)
Hardware Reference Manual (9800556)
Hardware Interface Manual (9800555)
8080/8085 Assembly Language Programming
Manual (9800301)
ISIS-II 8080/8085 Assembler Operator's Manual
(9800692)
Monitor Source Listing (9800605)
Schematic Drawings (9800554)
ORDERING INFORMATION
PRODUCT CODE
DESCRIPTION
MDS-220
Intellec Series II Model 220
Microcomputer Development
System (110V/60 Hz)
Intellec Series II Model 220
Microcomputer Development
System (220V/50 Hz)
MDS-221
13-9
inter
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
MODEL 230
INTELLEC® SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Complete Microcomputer Development Center
for Intel MCS·SOTM, MCS·S5™ and MCS·4S™
microprocessor families
Integral CRT with detachable upper/lower case
"typewrlter·style " full ASCII keyboard
64K bytes RAM memory
1 million bytes (expandable to 2.5M bytes) of disk·
ette storage
LSI electronics board with CPU, RAM, ROM, 1/0
and interrupt circuitry
Built·in interfaces for High·Speed Paper Tape
Reader/Punch, Printer and Universal PROM Pro·
grammer
Powerful ISIS·II Diskette Operating System Soft·
ware with Relocating Macro Assembler, Linker
and Locater
"Self·Test" Diagnostic capability
Standard MULTIBUSTM with multiprocessor and
DMA capability
Elght·level nested, maskable priority Interrupt sys·
tem
Compatible with standard Inteliec/iSBC Expan·
slon Modules
Software compatible with previous Intellec Sys·
tems
Supports PUM and FORTRAN high level
languages
The Intellec Series II Model 230 Microcomputer Development System Is a complete center for the development of
microcomputer-based products_ It includes a CPU, 64K bytes of RAM, 4K bytes of ROM memory, a 2000-.character CRT,
detachable full ASCII keyboard and dual double-density diskette drives providing over 1 million bytes of on·line data
storage.
Powerful ISIS-II Diskette Operating System software allows the Model 230 to be used quickly and efficiently for
assembly and/or compilation and debugging of programs for Intel's MCS-80, MCS-85 or MCS·48 microprocessor
families without the need for handling paper tape. ISIS-II performs all file handling operations for the user, leaving him
free to concentrate on the details of his own application. When used in conjunction with an optional in·circult
emulator (ICE TM) module, the Model 230 provides all the hardware and software development tools necessary for the
rapid development of a microcomputer-based product.
13-10
MODEL 230
speed paper tape reader/punch and Universal PROM
Programmer. The 10C contains its own independent
microprocessor, .also an B080A-2. The CPU controls all
I/O operations as well as supervising communications
with the IPB. 8K bytes of ROM contain all I/O control
firmware. 8K bytes of RAM are used fOJ CRT screen
refresh storage. These do not occupy space in Intellec
Series II main memory since the 10C is a totally independent microcomputer subsystem.
MODEL 230 HARDWARE DESCRIPTION
The Intellec Series II Model 230 is a packaged, highly integrated microcomputer development system consisting of a CRT chassis with 6-slot cardcage, power supply,
fans, cables, and five printed circuit cards. A separate,
full ASCII keyboard is connected with a cable. A second
chassis contains two floppy disk drives capable of
double-density operation along with a separate power
supply, fans and cables for connection to the main
chassis.
The CRT is a 12·inch raster scan type monitor with a
50/60 Hz vertical scan rate and 15.5 kHz horizontal scan
rate. Controls are provided for brightness and contrast
adjustments. The interface to the CRT is provided
through an Intel 8275 Single Chip Programmable CRT
Controller. The master processor on the IPB transfers a
character for display to the 10C, where it is stored in
RAM. The CRT controller reads a line at a time into its
line buffer through an Intel 8257 DMA Controller and
then feeds one character at a ti me to the character
generator to produce the video signal. Timing for the
CRT control is provided by an Intel 8253 Interval Timer.
The screen display is formatted as 25 rows of 80 characters. The full set of ASCII characters are displayed, in·
cluding lower case alphas.
The master CPU card contains its own microprocessor,
memory, I/O, interrupt and bus interface circuitry fash·
ioned from Intel's high technology LSI components.
Known as the integrated processor board (IPB), it occu·
pies the first slot in the cardcage. A second slave CPU
card is responsible for all remaining I/O control includ·
ing the CRT and keyboard interface. This card, mounted
on the rear panel, also contains its own microprocessor,
RAM and ROM memory, and I/O interface logic, thus, in
effect, creating a dual processor environment. Known
as the I/O controller (IOC), the slave. CPU card com·
municates with the IPB over an 8·bit bidirectional data
bus. In addition, 32K bytes of RAM (bringing the total to
64K bytes) is located on a separate card in the main
cardcage. Fabricated from Intel's 16K RAMs, the board
also contains all necessary address decoding and
refresh logic. Two additional boards in the cardcage are
used to control the two double-density floppy disk
drives. Two remaining slots in the cardcage are
available for system expansion. Additional expansion of
4 slots can be achieved through the addition of an Intellec Series II Expansion Chassis.
The heart of the IPB is an Intel NMOS 8-bit microproces·
sor, the 8080A·2, running at 2.6 MHz. 32K bytes of RAM
memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with
system bootstrap, "self·test" diagnostics and the
Intellec Series II System Monitor. The 8·level vectored
priority interrupt system allows interrupts to be in·
dividually masked. Using Intel's versatile 8259 Interrupt
Controller, the interrupt system may be user programmed to respond to individual needs.
The I/O subsystem in the Model 230 consists of two
parts: the 10C card and two serial channels on the IPB
itself. Each serial channel is RS232 compatible and is
capable of running asynchronously from 110 to 9600
baud or synchronously from 150 to 56K baud. Both may
be connected to a user·defined data set or terminal. One
channel contains current loop adapters. Both channels
are implemented using Intel's 8251 USART. They can be
programmatically selected to perform a variety of I/O
functions. Baud rate selection is accomplished programmatically through an Intel 8253 Interval Timer. The
8253 also serves as a real-time clock for the entire sys·
tem. I/O activity through both serial channels is signaled
to the system through a second 8259 interrupt con·
troller, operating in a polled mode nested to the primary
8259.
The remainder of system I/O activity takes place in the
10C. The 10C provides interface for the CRT, keyboard,
and standard Intellec peripherals including printer, high-
The keyboard interfaces directly to the 10C processor
via an 8·bit data bus. The keyboard contains an Intel
UPI-41 Universal Peripheral Interface which scans the
keyboard, encodes the characters and buffers the
characters to provide N·key rollover. The keyboard itself
is a high quality typewriter style keyboard containing
the full ASCII character set. An upper/lower case switch
allows the system to be used for document preparation.
Cursor control keys are also provided.
A UPI·41 Universal Peripheral Interface on the 10C board
performs similar functions to the UPI·41 on the PIO
board in the Model 210. It provides interface for other
standard Intellec peripherals including:
•
•
•
•
Printer
High-Speed Paper Tape Reader
High·Speed Paper Tape Punch
Universal PROM Programmer
Communication between the IPB and 10C is maintained
over a separate B-bit bidirectional data bus. Connectors
for the 4 devices named above, as well as the two serial
channels, are mounted directly on the 10C itself.
User control is maintained through a front panel,
consisting of a power switch and indicator, reset/boot
switch, run/halt light and 8 interrupt switches and
indicators. The front panel circuit board is attached
directly to the IPB, allowing the 8 interrupt switches to
connect to the primary 8259, as well as the Intellec
Series II Bus.
The Intellec Series II double-density diskette system
provides direct access bulk storage, intelligent controller, and two diskette drives. Each drive provides 1/2
million bytes of storage with a data transfer rate of
500,000 bits/second. The controller is implemented with
Intel's powerful Series 3000 Bipolar Microcomputer Set.
The controller provides an interface to the Intellec
Series II system bus, as well as supporting up to four
diskette drives. The diskette system records all data in
soft sector format.
13·11
MODEL 230
The diskette controller consists of two boards, the
Channel Board and the Interface Board. These two PC
boards reside in the Intellec Series II system chassis
and constitute the diskette controller.
The diskette system is capable of performing seven
different operations: recalibrate, seek, format track,
write data, write deleted data, read data, and verify CRC.
In addition to supporting a second set of double-density
drives, the diskette controller may co-reside with the
Intel single density controller to allow up to 2.5 million
bytes of on·line storage.
The Channel Board receives, decodes and responds to
channel commands from the 8080A·2 CPU in the Model
230. The Interface Board provides the diskette con·
troller with a means of communication with the diskette
drives and with the Intellec system bus. The Interface
Board validates data during reads using a cyclic redun·
dancy check (CRC) polynomial and generates CRC data
during write operations. When the diskette controller
requires access to Intellec system memory, the Interface Board requests and maintains DMA master control
of the system bus, and generates the appropriate
memory command. The Interface Board also acknowledges 1/0 commands as required by the Intellec bus.
SPECI FICATIONS
PHYSICAL
Dimensions:
Weight:
Keyboard:
Weight:
Dual Drive
Chassis:
Weight:
19.13" (48.59 cm) deep x 17.37" (44.12
cm) wide x 15.81" (40.16 em) high
73 Ib (33 Kg)
9" (22.86 cm) deep x 17.37" (44.12 cm)
wide x 3.0" (7.62 cm) high
6 Ib (3 Kg)
19.0" (48.26 cm) deep x 16.88" (42.88
cm) wide x 12.08" (30.68 em) high
64 Ib (29 Kg)
ELECTRICAL
DC Power Supply:
Volts
Supplied
··
+5
+12
-12
-10
+15
-+:24
±5%
±5%
±5%
±5%
±5%
±5%
Amps
Supplied
Typical
System Requirements
30
2.5
0.3
1.5
1.5
1.7
14.25
0.2
0.05
15
1.3
• Not available on bus.
AC Requirements: 50/60 Hz, 115/230 VAC
ENVIRONMENTAL
Operating Temperature: 0° to 35°C (95°F)
HOST PROCESSOR (IPB)
RAM: 64K (System Monitor occupies 62K through 64K).
ROM: 4K (2K in monitor, 2K in boot/diagnostic).
Diskette System Capacity (Basic Two Drives):
Unformatted
Per Disk: 6.2 megabits
Per Track: 82.0 kilobits
Formatted
Per Disk: 4.1 megabits
Per Track: 53.2 kilobits
All Intellec Series II mOdels implement the industry
standard MULTI BUS. It enables several bus masters
such as CPU and DMA devices to share the bus and
memory by operating at different priority levels. Resolu·
tion of bus exchanges is synchronized by a bus clock
signal which is derived independently from processor
clocks. Readlwrite transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microcomputer family.
Diskette Performance:
Diskette System Transfer Rate: 500 kilobitslsec
Diskette System Access Time
Track-to·Track:
10 ms
Head Settling Time: 10 ms
Average Random POSitioning Time: 260 ms
Rotational Speed: 360 rpm
Average Rotational Latency: 83 ms
Recording Mode: M2FM
EQUIPMENT SUPPLIED
Model 230 Chassis
Integrated Processor Board (IPB)
I/O Controller Board (IOC)
32K RAM Board
CRT and Keyboard
Double-Density Floppy Disk Controller (2 boards)
Dual·Drive Floppy Disk Chassis and Cables
2 Floppy Disk Drives (512K byte capacity each)
ROM-Resident System Monitor
ISIS·II System Diskette with MCS·80/MCS·85 Macro
Assembler
A Guide to Microcomputer Development Systems
(9800558)
Installation and Service Guide (9800550)
ISIS·II System User's Guide (9800306)
Hardware Reference Manual (9800556)
Hardware Interface Manual (9800555)
8080/8085 Assembly Language Programming
Manual (9800301)
ISIS·II 8080/8085 Assembler Operator's
Manual (9800292)
Monitor Source Listing (9800605)
Schematic Drawings (9800554)
ORDERING INFORMATION
PRODUCT CODE
DESCRIPTION
MDS-230
Intellec Series II Model 230
Microcomputer Development
System (l10V/60 Hz)
Intellec Series II Model 230
Microcomputer Development
System (220V/50 Hz)
MDS-231
13·12
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
EXPANSION CHASSIS
INTELLEC® SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Four expansion slots for Intellec Series II Systems
Standard Intellec MULTIBUSTM with multiprocessor and DMA capability
Internal power supply
Fits snugly beneath all Intellec Series II Units
Compatible with standard Inteliec/iSBC Expansion Modules
Cable connectable to main Intellec bus
The Intellec Series II Expansion Chassis provides 4 expansion slots for use with Intellec Series II Microcomputer
Development Systems. With its own separate power supply, the expansion chassis may be fully loaded with any
boards needed to expand a user's Intellec Series II System. With the addition of the expansion chaSSiS, Intellec Series
II Models 220 and 230 contain a total of 10 slots, sufficient for any configuration Intellec Series II system.
13-13
EXPANSION CHASSIS
Series II System, connect directly to the system bus
through an opening in the top of the chassis and provide
additional slots for the system users.
The power supply is linked directly to the main chassis
power supply, allowing power to flow to both chassis
when the main system power is turned on.
EXPANSION CHASSIS HARDWARE
DESCRIPTION
The Intellec Series II Expansion Chassis is a compact
chassis with 4-slot cardcage, power supply, fans and
cable assemblies. It is designed to fit under any Intellec
SPECIFICATIONS
PHYSICAL
Dimensions:
Weight:
ENVIRONMENTAL
Operating Temperature: 0° to 35°C (95°F)
19.13" (48.59 cm) deep x 17.37" (44.12
cm) wide x 4.81" (17.22 cm) high
42 Ib (19 Kg)
ELECTRICAL
DC Power Supply:
Volts
Supplied
+5 ±5%
+12 ±5%
-12 ±5%
-10 ±5%
Amps
Supplied
24
2.0
0.3
1.0
System
Requirements
EQUIPMENT SUPPLIED
Expansion Chassis
Cables
Interconnect Diagram
Schematic Drawings (9800554)
Installation and Service Guide (9800550)
None
None
None
None
AC Requirements: 50-60 Hz, 115/230 VAC
ORDERING INFORMATION
PRODUCT CODE
DESCRIPTION
MDS-201
Intellec Series II Expansion Chassis
13-14
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
MODEL 210 ENHANCEMENT KIT
INTELLEC® SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Upgrades Model 210 System to Model 220 capabil·
ity
Converts Model 210 chassis to MDS·201 expan·
sion chassis
Includes full Model 220 capability including Inte·
gral CRT and floppy disk
Eliminates the need to purchase an entire new
system as development requirements increase
The Intellec system peripherals as files through pre·
assignment of unique file names to each device. In this
manner data can be copied from one device to another
(I.e., tape reader to tape punch) using the same
command required to copy one diskette data file to
another. 1515·11 provides automatic Implementation of
random access disk files. Each file is identified by a
user-chosen name unique on its diskette. Up to 200 files
may be stored on each diskette.
The ISIS-II Text Editor is a comprehensive tool for the
entry and correction of assembly language, PUM and
FORTRAN programs for Intel® microcomputers. Its
command set allows manipulation of either entire lines
of text or individual characters within a line.
Programs may be entered from the console keyboard or
may be loaded directiy. Text is stored internally in the
editor's workspace, and may be edited with the follow·
ing commands:
• string insertion or deletion
• string search
• string substitution
ISIS·II SYSTEM COMMANDS
ISIS-II system commands are designed to provide
user with a powerful, easy-to·use program and
manipulation capability. Several commands have
capability of operating on several files at once via
wildcard file·namlng convention. As an example,
command "DELETE
.OBJ" deletes all files in
diskette directory with the suffix" .OBJ".
*
the
file
the
the
the
the
To facilitate the use of these editing commands, utility
commands are used to change positions in the
workspace. These include:
• move pointer by line or by character
• move pOinter to start of workspace
• move pointer to end of workspace
The contents of the workspace are stored on diskette
and can be immediately accessed by ISIS·II commands
or other programs, such as the 1515·11 MCS-80/MCS·85
Macro Assembler.
IDISK
Initializes a diskette for use by the
system. Requires only one disk drive.
ATTRIB
Assigns specified attributes to a file,
such as write·protect.
COpy
Creates copies of existing diskette files
or transfers files from one device to
another.
ISIS·II MCS·80/MCS·85 RELOCATING
MACRO ASSEMBLER
DELETE
Removes a file from the diskette, thereby
freeing space for allocation of other files.
DIR
Lists name, size and attributes of files
from a specified diskette directory.
RENAME
Allows diskette files to be renamed.
FORMAT
Initializes a diskette for use by the
system. (Use with two or more drives.)
DEBUG
Loads a specified program from a
diskette into memory and then transfers
control to the Intellec monitor for execu·
tion and or debugging.
The ISIS·II MeS·BO/MCS·85 Macro Assembler translates
assembly language mnemonics into relocatable andlor
absolute object code modules. In addition to eliml·
nating the errors of hand translation, the ability to refer
to program addresses with symbolic names makes it
easy to modify programs by adding or deleting instruc·
tions. Extended macro capability eliminates the need to
rewrite similar sections of code repeatedly and simpli·
fies program documentation. Conditional assembly per·
mits the assembler to include or delete sections of code
which may vary from system to system, such as the
code required to handle optional external devices.
SUBMIT
Provides the capability to execute a
series of 1515·11 commands which have
been previously written to a diskette file.
ISIS·II SYSTEM CALL CAPABILITY
The DELETE, RENAME and ATTRIB system commands,
along with a set of file 1/0 routines, are callable from
user·written programs. This allows the user to open,
close, read and write diskette files, access standard
peripheral devices, write error messages and load other
programs via simple program call statements.
In addition, the user is allowed complete freedom in
aSSigning the location of code, data and stack seg·
ments.
The 1515·11 Assembler accepts diskette file input and
produces a relocatable object file with corresponding
symbol table and assembly listing file, including any
error messages. A cross reference listing is also option·
ally produced. The list file may then be examined from
the system console or copied to a specified list device.
The relocatable object file generated by the assembler
may be combined with other object programs residing
on the diskette to form a single relocatable object mod·
ule or it can be converted to an absolute form for subse·
quent loading and execution.
13·22
1515·/1 DISKETTE OPERATING SYSTEM
1515·11 LINKER
The ISIS-II LINKER provides the capability to combine
the outputs of several independently compiled or
assembled object modules (files) into a single relocatable object module. The LINKER automatically resolves
all external program and data references during the linking process.
Object modules produced from previous link operations
may be easily linked to a new module. ISIS-II also provides facilities to ease the generation of overlays.
An optional link map showing the contents and lengths
of each segment in the output module can be requested.
All unsatisfied external references are also listed.
If requested by the user, the ISIS-II LINKER can search a
specified set of program libraries for routines to be included in the output module.
1515·11 OBJECT LOCATOR
The ISIS-II LOCATE program takes output from either
the resident FORTRAN or PUM compilers, the macro
assembler or the LINKER and transforms that output
from a relocatable format to an absolute format which
may then be loaded via the standard ISIS-II loader, or
loaded into the appropriate In-Circuit Emulator (ICE)
module.
During the LOCATE process, code, data and stack segments can be separately relocated, allowing code to be
put in areas to be subsequently specified as ROM, while
data and the stack can be directed to RAM addresses.
A LOCATE map showing absolute addresses for each
code and data segment and a symbol table dump listing
symbols, attributes and absolute address can also be requested.
1515·11 LIBRARY MANAGER
The ISIS-II LIBRARY MANAGER program provides for
the creation and maintenance of a program library con·
taining Intel-provided and user-written programs and
subroutines. These library routines can be linked to a
program using the ISIS-II LINKER. Several libraries,
each containing its own set of routines, can be created.
PROGRAM DEVELOPMENT FLOW USING ISIS·II DISK OPERATING SYSTEM
13·23
in1er
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
PL/M·80
HIGH LEVEL PROGRAMMING LANGUAGE
INTELLEC® RESIDENT COMPILER
Cuts software development and maintenance
costs
Produces relocatable and linkable object code
Speeds project completion
Improves product reliability
Resident operation on Intellec® Microcomputer
Development System and Intellec® Series II
Microcomputer Development Systems
Eases enhancements as system capabilities expand
Sophisticated code optimization reduces application memory requirements
PUM-80 is an advanced, high-level programming language for Intel® 8080 and 8085 Microprocessors, iSBC-80 OEM
Computer Systems and Intellec® Microcomputer Development Systems. PUM has been substantially enhanced since
its introduction in 1973 and has become one of the most effective and powerful microprocessor systems implementation tools available. It is easy to learn, facilitates rapid program development and debugging, and significantly reduces
maintenance costs.
PUM is a powerful, high-level algorithmic language in which program statements can naturally express the algorithm
to be programmed. This frees programmers to concentrate on their system development without having to deal with
assembly language details (such as register allocation, meanings of assembler mnemonics, etc.).
The PUM compiler efficiently converts free-form PUM programs into equivalent 8080/8085 instructions. Substantially
fewer PUM statements are necessary for a given application than if it were programmed at the assembly language or
machine code level.
Since PUM programs are problem oriented and more compact, programming in PUM results in a high degree of productivity during development efforts. This translates into significant reductions in software development and maintenance costs for the user.
13-24
PLlM-80
FEATURES
BENEFITS
Major features of the Intel PUM-80 Compiler and programming language include:
PUM is designed to be an efficient, cost-effective solution to the special requirements of microcomputer software development as illustrated by the following
benefits of PUM use:
• Resident operation on the Intellec® Microcomputer
Development System eliminates the need for a large
in-house computer or costly timesharing system.
• Generation of relocatable and linkable object code
permits PUM programs to be developed and debugged in small modules. These modules can be easily
linked with other modules and/or library routines to
form a complete application.
• Extensive code optimization results in generation of
short, efficient CPU instruction sequences. Major optimizations include compile time arithmetic, constant subscript resolution, and common subexpression elimination.
• The PUM Compiler fully supports symbolic debugging with the ICE-80™ and ICE-85™ In-Circuit Emulators.
• Compile time options include general listing format
commands, symbol table listing, cross reference
listing, and "innerlist" of generated assembly language instructions.
• Block structure aids in utilization of structured programming techniques.
• High level PUM statements provide access to hardware resources (interrupt systems, absolute addresses, CPU input/output ports).
• Complex data structures may be defined at a high
level.
• Re-entrant procedures may be specified as a user option.
• Low Learning effort - PUM is very easy to learn even
for the novice programmer.
• Earlier Project Completion - Critical projects are
completed much earlier than otherwise possible
because PUM substantially increases programmer
productivity.
• Lower Development Cost - Increases in programmer productivity translate into lower software
development costs because less programming
resources are required for a given function.
• Increased Reliability - PUM is designed to assist in
the development of reliable software (PUM programs
are simple statements of the program algorithm).
This substantially reduces the risk of costly correction of errors in systems that have aleady reached full
production status because a simply stated program
is more likely to correctly perform its intended function.
• Easier Enhancements and Maintenance - Programs
written in PUM are easier to read and easier to
understand. This means it is easier to enhance and
maintain PUM programs as system capabilities expand and future products are developed.
• Simpler Project Development The Intellec®
Microcomputer Development System, with resident
PUM-80, is all that is needed for development and
debugging of software for 8080 and 8085 microcomputers. This reduces development time and cost
because expensive (and remote) timesharing or large
computers are not required.
The PUM Compiler is an efficient multiphase compiler that accepts source programs, translates them into object
code, and produces requested listings. After compilation, the object program may be linked to other modules, located
to a specific area of memory, then executed. The diagram shown above illustrates a program development cycle where
the program consists of three modules, one PUM, one Fortran, and the other assembly language.
13-25
PlIM-80
PL/M-80
COMPILER
FACTORIAL GENERATOR - PROCEDURE
$OBJECT(:F 1 :FACT.OB2)
$DEBUG
$XREF
$TITLE('FACTORIAL GENERATOR - PROCEDURE')
$PAGEWIDTH(80)
FACT:
DO;
DECLARE NUMCH BYTE PUBLIC;
2
3
4
5
6
1
2
2
2
7
9
10
11
12
13
14
15
2
2
3
3
4
4
4
4
16
17
3
3
lR
<1
20
21
22
4
4
4
FACTORIAL: PROCEDURE (NUM,PTR) PUBLIC;
DECLARE NUM BYTE, PTR ADDRESS;
DECLARE DIGITS BASED PTR (161) BYTE;
DECLARE (I,C,M) BYTE;
NUMCH=I; DIGITS(1)=I;
DOM= 1 TONUM;
C=O;
DO I = 1 TO NUMCH;
DIGITS(I) = DIGITS(I) * M + C;
C = DIGITS(I)/10;
DIGITS(I) = DIGITS(I) - 10 * C;
END;
IF C <>0 THEN
DO;
NUMCH = NUMCH+ 1; DIGITS (NUMCH) = C;
C = DIGITS(NUMCH)/lO;
DIGITS(NUMCH) = DIGITS(NUMCH) - 10 * C;
END
END;
24
2
25
END FACTORIAL;
END;
SPECIFICATIONS
Operating Environment:
Required hardware
Intellecl!> Microcomputer Development System
65K bytes of memory
Dual diskette drives
System console - teletype
Optional hardware
CRT as system console
Li ne pri nter
Documentation Package:
PUM Programming Manual
ISIS-II PUM-80 Compiler Operator's Manual
Shipping Media:
Diskette
ORDERING INFORMATION
PRODUCT CODE
DESCRIPTION
MDS-PLM
High-Level Language Compiler
Resident on Intellec System Translates a Source Program written
in PUM-80 into 8080/8085 Machine
Code
Required software
ISIS-II Diskette Operating System
13-26
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
FORTRAN-80
8080/8085 ANS FORTRAN 77
INTELLEC® RESIDENT COMPILER
Meets and exceeds ANS FORTRAN 77 Subset
Language Specification
Produces relocatable and linkable object code
compatible with resident PL/M·80 and 8080/8085
Macro Assembler
Supports Intel Floating Point Standard
Resident operation on Intellec@ Microcomputer
Development System and Intellec@ Series II
Microcomputer Development System
Full FORTRAN 77 language 1/0 support when used
with ISIS·II run·tlme library
Supports full symbolic debugging with ICE·
80™and ICE·85™
Sophisticated code optimization insures efficient
program implementation
FORTRAN·80 is a computer industry·standard, high·level programming language and compiler that translates FOR·
TRAN statements into relocatable object modules. When the object modules are linked together and located into abo
solute program modules, they are suitable for execution on Intel@ 8080/8085 Microprocessors, iSBC·80 OEM Computer
Systems, and Intellec'" Microcomputer Development Systems. FORTRAN·80 meets and exceeds the ANS FORTRAN
77 Language Subset SpeCification 1. The compiler operates on the Intellec Microcomputer Development System under
the ISIS·II Disk Operating Systems and produces efficient relocatable object modules that are compatible for linkage
with PUM·80 and 8080/8085 Macro Assembler modules.
The ANS FORTRAN 77 language specification offers many powerful extensions to the FORTRAN language that are
espeCially well suited to Intel@ 8080/8085 Microprocessor software development. Because FORTRAN·80 conforms to
the ANS FORTRAN 77 standard, the user is assured of compatibility with existing FORTRAN software that meets the
standard as well as a guarantee of upward compatibility to other computer systems supporting an ANS FORTRAN 77
Compiler.
1ANSI X3J3/90
13·27
FORTRAN·SO
• The INCLUDE control permits specified source
files to be combined into a compilation unit at
compile time.
FORTRAN·SO LANGUAGE FEATURES
Major ANS FORTRAN 77 features supported by the
Intel® FORTRAN-80 Programming Language include:
• Structured Programming is supported with the
IF ... THEN ... ELSE IF ... ELSE ... END IF constructs.
• CHARACTER data type permits alphanumeric data
to be handled as strings rather than characters
stored in array elements.
• Full 1/0 capabilities include:
Sequential and Direct Access files
Error handling facilities
Formatted, Free-formatted, and Unformatted
data representation
Internal (in-memory) file units provide capability to format and reformat data in internal memory buffers
List Directed Formatting
FORTRAN·SO BENEFITS
FORTRAN-80 provides a means of developing application software for Intel® MCS-80/85 products in a
familiar, widely accepted, and computer industrystandardized programming language. FORTRAN-80 will
greatly enhance the user's ability to provide costeffective solutions to software development for Intel
microprocessors as illustrated by the following:
• Completely Complementary to Existing Intel Software Design Tools - Object modules are linkable
with new or existing Assembly Language and
PUM Modules.
• Supports arrays of up to seven dimensions.
• Incremental Runtime Library Support - Runtime
overhead is limited only to facilities required by
the program .
• Supports logical operators
.EQV. - Logical equivalence
.NEQV. - Logical nonequivalence
• Low Learning Effort - FORTRAN-80, like PUM, is
easy to learn and use. Existing FORTRAN software can be ported to FORTRAN-80, and programs
developed in FORTRAN-80 can be run on any other
computer with ANS FORTRAN 77.
Major extensions to FORTRAN 77 in Intel FORTRAN-80
include:
• Direct 8080/8085 port 1/0 supported by intrinsic
subroutines.
•
• Earlier Project Completion - Critical projects are
completed earlier than otherwise possible because FORTRAN-80 will substantially increase
programmer productivity, and is complementary to
PUM Modules by providing comprehensive arithmetiC, 1/0 formatting, and data management support in the language.
Binary and Hexadecimal integer constants.
• User-defined INTEGER storage lengths of 1, 2 or 4
bytes.
• User-defined LOGICAL storage lengths of 1, 2 or 4
bytes.
• Lower Development Cost - Increases in programmer productivity translates into lower software
development costs because less programming
resources are required for a given function.
• REAL STORAGE lengths of 4 bytes.
Bitwise Boolean operations using logical operators on integer values.
• Hollerith data constants.
• Increased Reliability - The nature of high-level
languages, including FORTRAN-80, is that they
lend themselves to simple statements of the program algorithm. This substantially reduces the
risk of costly errors in systems that have already
reached production status.
• Implicit extension of the length of an integer or
logical expression to the length of the left-hand
side in an assignment statement.
• A format descriptor to suppress carriage return on
a terminal output device at the end of the record.
• Easier Enhancements and Maintenance - Like
PUM, program modules written in FORTRAN-80
are easier to read and understand than assembly
language. This means it is easier to enhance and
maintain FORTRAN-80 programs as system capabilities expand and future products are developed.
FORTRAN·SO COMPILER FEATURES
• Supports multiple compilation units in single
source file.
• Optional Assembly Language code listing.
• Comprehensive cross-reference, symbol attribute
and error listing.
• Comprehensive, Yet Simple Project Development
- The Intellec Microcomputer Development System, with the 8080/8085 Macro Assembler, PUM-80
and FORTRAN-80 is the most comprehensive software design facility available for the Intel
MCS-80/85 Microprocessor family. This reduces
development time and cost because expensive
(and remote) timesharing or large computers are
not required.
• Compiler controls and directives are compatible
with other Intel language translators.
• Optional Reentrancy.
• User-defined default storage lengths.
• Optional FORTRAN 66 Do Loop semantics.
• Source files may be prepared in free format.
13-28
FORTRAN·80
SAMPLE FORTRAN·SO SOURCE PROGRAM
LISTING
C
C
C
10
2
3
4
THIS PROGRAM IS AN EXAMPLE OF ISIS-II FORTRAN-Bo THAT
CONVERTS TEMPERATURE BETWEEN CELCIUS AND FARENHEIT
PROGRAM CONVRT
CHARACTER*l CHOICE,SCALE
PRINT 1
FORMAT (' TEMPERATURE CONVERSION PROGRAM' ,II,
*, TYPE C FOR FARENHEIT TO CELCIUS OR', I,
*' F FOR CELCIUS TO FARENHEIT' ,II)
PRINT 2
FORt-'lAT (I,' CONVERSION? ',$)
READ (5,3) SCALE
FORMAT (A1)
IF (SCALE.EQ.'C') THEN
PRINT 4
FORMAT (I,' ENTER DEGREES FARENHEIT? ',$)
READ (5,*) DEGF
DEGC=5./9.*DEGF-32.
5
11
6
7
wRITE (6,5) DEGF,DEGC
FORMAT (1,£0'7.2,' DEGREES FARENHEIT
PRINT 6
FORMAT (I,' AGAIN (y OR N)? ',$)
READ (5,3) CHOICE
IF (CHOICE.EQ.'Y') THEN
GOTO 10
ELSE IF (CHOICE. EQ. 'N') THEN
CALL EXIT
ELSE
GOTO 11
END IF
ELSE IF (SCALE.EQ.'F') THEN
PRHJT 7
FORMAT (I,' ENTER DEGREES CELCIUS?
READ (5,*) DEGC
=
',F7.2,' DEGREES CELCIUS',I)
',$)
DEGF=9./5.*DEGC+32.
wRITE(6,B) DEGC,DEGF
FORMAT (I,F7.2,' DEGREES CELCIUS
GOTO 11
8
= ',£0'7.2,'
DEGREES FARENhEIT' ,I)
ELSE
9
wRITE (6,9) SCALE
FORMAT (I, lH ,Al,'
GO TO 10
END IF
END
NOT A VALID CHOICE -
13-29
RETRY!',I)
FORTRAN·SO
The FORTRAN·80 Compiler is an efficient, multiphase compiler that accepts source programs, translates them into
relocatable object code, and produces requested listings. After compilation, the object program may be linked to other
modules, located to a specific area of memory, then executed. The diagram shown below illustrates a program
development cycle where the program consists of modules created by FORTRAN·80, PUM·80 and the 8080/8085 Macro
Assembler.
I
EJ-I'------'
SPECIFICATIONS
OPERATING ENVIRONMENT
Required Hardware:
Intellec® Microcomputer Development System
- MDS·800, MDS·888
- Series II Model 220, Model 230
64K bytes of RAM memory
Dual diskette drives
- Single or Double Density
System console
- CRT or hardcopy interactive device
DOCUMENTATION PACKAGE
FORTRAN·80 Programming Manual (9800481)
ISIS·II FORTRAN·80 Compiler Operator's Manual
(9800480)
FORTRAN·80 Programming Reference Card (9800547)
SHIPPING MEDIA
Flexible Diskettes
-
Optional Hardware:
Line Printer
ICE·80™,ICE·85TM
Required Software:
ISIS·II Diskette Operating System
- Single or Double Density
ORDERING INFORMATION
PRODUCT CODE
DESCRIPTION
MDS·301
FORTRAN·80 Compiler for Intellec
Microcomputer Development
Systems
13·30
Single and Double Density
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC SERIES II
MCS·48™
DISKETTE·BASED SOFTWARE
SUPPORT PACKAGE
Extends Intellec@ Microcomputer Development
System to support MCS.48™ development
MCS·48 Assembler provides conditional assem·
bly and macro capability
Takes advantage of powerful ISIS·II file handling
and storage capabilities
The MCS-48™ Diskette-based Software Support Package (MDS-D48) comes on an Intel'" ISIS-II System Diskette and
contains the MCS-48 Assembler (ASM48), and the diskette version of the Universal PROM Mapper.
The MCS-48 Assembler (ASM48) translates symbolic 8048 assembly language instructions into the appropriate
machine operation codes. In addition to eliminating the errors of hand translation, the ability to refer to program addresses with symbolic names makes it easier to modify programs when adding or deleting instructions. Conditional
assembly permits the programmer to specify portions of the master source document which should be included or
deleted in variations on a basic system design, such as the code required to handle optional external devices.
Macro capability allows the programmer to define a routine through the use of a single label. ASM48 will assemble the
code required by the reserved routine whenever the Macro label is inserted in the text.
Output from the ASM48 is in standard Intel'" Hex format. It may be loaded directly to an ICE-48 module for integrated
hardware/software debugging. It may also be loaded into the Intellec Development System for 8748 PROM programming using the Universal PROM Programmer.
13-31
MCS-48T
M
DISKETTE-BASED SOFTWARE SUPPORT PACKAGE
SAMPLE MCS-48T M DISKETTE-BASED ASSEMBLEY LISTING
ISIS-II 8048 MACRO ASSEMBLER, Vl.0
LOC
OBJ
SEQ
SOURCE STATEMENT
1 ; DECIMAL ADDITION ROUTINE. ADD BCD NUMBER
2 ; AT LOCATION 'BETA' TO BCD NUMBER AT 'ALPHA' WITH
3 ; RESULT IN 'ALPHA.' LENGTH OF NUMBER IS 'COUNT' DIGIT
4 ; PAIRS. (ASSUME BOTH BETA AND ALPHA ARE SAME LENGTH
5 ; AND HAVE EVEN NUMBER OF DIGITS OR MSD IS 0 IF
6 ;000)
MACRO
AUGND,ADDND,CNT
7 IN IT
8
MOV
RO, #AUGND
9 L 1:
MOV
Rl, #ADDND
10
MOV
R2, #CNT
11
ENDM
12
13 ALPHA
EQU
30
14 BETA
EQU
40
15 COUNT
EQU
5
16
ORG
100H
17
INIT
ALPHA,BETA,COUNT
18+
RO, #ALPHA
MOV
19+L 1:
MOV
Rl, #BETA
20+
MOV
R2, #COUNT
21
CLR
C
A,@RO
22 LP:
MOV
23
A,@Rl
ADDC
24
DA
A
@RO,A
25
MOV
26
INC
RO
INC
Rl
27
DJNZ
R2,LP
28
END
0001 E
0028
0032
0100
0100
0102
0104
0106
0107
0108
0109
010A
010B
OlOC
0100
PAGE 1
B81E
B928
BA32
97
FO
71
57
Al
18
19
EA07
USER SYMBOLS
ALPHA 001 E
BETA 0028
L1
0102
COUNT 0005
LP 0107
ASSEMBLY COMPLETE, NO ERRORS
ISIS-II ASSEMBLER SYMBOL CROSS REFERENCE, Vl.0
PAGE 1
SYMBOL CROSS REFERENCE
ALPHA
BETA
COUNT
INIT
Ll
LP
13#
14#
15#
7#
19#
17
17
17
17
22#
28
SPECIFICA TlONS
Optional Hardware
Universal PROM Programmer
MDS-D48
Operating Environment:
Required Hardware
I ntellec® Microcomputer Development System
System Console
Intellec Diskette Operating System
32K RAM (non-Macro Assembler)
48K RAM (Macro Assembler}
I
Documentation Package:
MCS-48™ Assembly Language Manual
Universal PROM Mapper Operator's Manual
ISIS-II System User's Guide
Shipping Media:
Diskette
ORDERING INFORMATION
PRODUCT CODE
MDS-D48
DESCRIPTION
Diskette-Based Assembler for
MCS-48 Family of Microprocessors
13-32
INTELLEC SERIES II
AVAILABLE OPTIONS AND DOCUMENTATION
OPTIONS
DOCUMENTATION
EXPANSION MODULES
16K RAM Module
SBC·016
32K RAM Module
SBC·032
6K PROM Module using 1702A PROMs
MDS·406
16K PROM Module using 2708 PROMs
MDS·416
DMA Channel Controller
MDS·501
General Purpose I/O Module
MDS·504
High Speed Mathematics Unit
SBC·310
IN·CIRCUIT EMULATORS
8080A In·Circuit Emulator
ICE·80
8085 In·Circuit Emulator with External
ICE·85
Trace Capability
8748/8048 In·Circuit Emulator
ICE·48
Series 3000 In·Circuit Emulator
ICE·30
8021 Emulation Board
MDS·EMl
PERIPHERALS
MDS·PTR
UPP·l03
MDS·PRN
MDS·770/771
MDS·701/702
MDS·710/711
MDS·720/721
MDS·730/731
High Speed Paper Tape Reader
Universal PROM Programmer
165 Character per Second Dot Matrix
Printer
60 Character per Second Dot Matrix
Printer
Add·On Disk Drive for Intellec Series II
Model 230
1/2 Million Byte Floppy Disk System
1 Million Byte Floppy Disk System
Add·On Drives to 720/721 with
Addition al 1 Million Bytes
SOFTWARE
MDS·PLM
MDS·301
MDS·R48
MDS·D48
INSITE
8080/8085 PUM Compiler
8080/8085 ANS 1977 FORTRAN Compiler
MCS·48 Family ROM Assembler/Editor'
MCS·48 Family Diskette·Based Assem·
bier
Intel Microprocessor User's Library
'For use with Model 210.
13·33
MANUAL
A Guide to Microcomputer Devel·
opment Systems
Intellec'" Series II Model 210 User's
Guide
ISIS·II User's Guide
Intellec'" Series II Installation and
Service Manual
Intellec'" Series II Hardware Inter·
face Manual
Intellec'" Series II Hardware Refer·
ence Manual
Intellec'" Series II Schematic
Drawings
ISIS·II 8080/8085 Assembler
Operator's Manual
8080/8085 Assembly Language
Programming Manual
MCS-48/UPI·41 Assembly Language
Programming Manual
PUM·80 Programming Manual
FORTRAN·80
Programming Manual
ISIS·II PUM Compiler Operator's
Manual
ISIS·II 8080/8085 ANSI FORTRAN
Compiler Operator's Manual
Universal PROM Mapper Operator's
Manual
ICE·80 Operator's Manual
ICE·85 Operator's Manual
ICE·48 Operator's Manual
Universal PROM Programmer Hard·
ware Reference Manual
Single Density Diskette Operating
System Hardware Reference Manual
Double Density Diskette Operating
System Hardware Reference Manual
Documentation may be ordered from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
DOC. #
PRICE
9800558
$ 2.00
9800557
15.00
9800306
9800559
15.00
15.00
9800555
25.00
9800556
25.00
9800554
25.00
9800292
10.00
9800301
5.00
9800255
5.00
9800268
9800481
5.00
5.00
9800300
15.00
9800480
15.00
9800236
15.00
9800185
9800463
9800464
9800133
15.00
15.00
15.00
25.00
9800212
25.00
9800422
25.00
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC® PROMPT 48™
MCS-48™ MICROCOMPUTER DESIGN AID
Low Cost
Complete Design Aid and EPROM Programmer
for revolutionary MCS-48™ Single Component
Computers including:
CPUs
Simplifies microcomputing - enter, run, debug,
and save machine language programs with
calculator-like ease
8-bit MCS-48™ : 8748, 8035
Program 1 K byte erasable, reprogram mabie onMemory chip (8748), expandable. 1K byte
RAM in PROMPT'M system.
Complete with two removable MCS-48™ CPUs:
8748
Register 64 bytes RAM on-chip, expandable
Memory
CPU with erasable, reprogrammable
program memory on-chip
8035
CPU
256 bytes RAM in PROMPT'M system,
Data
Memory expandable
Integral keyboard and displays (no teletypewriter or CRT terminal required)
I/O
27 TTL compatible I/O lines on-chip,
expandable
Extensive PROMPT 48™ monitor allows system
I/O, bus and memory expansion
Control
On-chip clock, internal timer/event
counter, two vectored interrupts,
eight level stack
Intellec® Microcomputer Development System
compatible
Power
Single +5 VDC system
program
memory is off-chip
Comprehensive Design Library
Intellec PROMPT 48 is a low cost, fully-assembled design aid for the revolutionary 8748 single component microcomputer.
PROMPT 48 simplifies the programming of MCS-48 systems - programs can be entered and debugged with calculator-like
ease on the large, informative display and keyboard panel. The comprehensive design library with tutorial manual is ideal for
newcomers to microcomputing.
PROMPT 48's panel connector allows easy access to I/O ports and system bus. Thus users can expand program memory
beyond the 1k bytes provided internally.'PROMPT 48 can serve as an economical 8748 Specialized PROM Programmer (SPP)
peripheral in !nte!!ec Microcomputer Development Systems.
I
13-34
INTELLEC'" PROMPT 48 ™
multi-chip microprocessors. The MCS-48 is an efficient
controller and arithmetic processor, with extensive bit
handling, binary, and BCD arithmetic instructions. These
are encoded for minimum program length: 70% are single
byte operation codes, and none is more than two bytes.
PROMPT 48™ SIMPLIFIES MICROCOMPUTING
Intellec PROMPT 48 simplifies the programming of MCS-48
systems. Like the 8748 it is radically new, highly integrated,
and expandable. Like the MCSA8 family, it is low cost, and
ideal for small applications and programs. It is a design aid,
not a development system with sophisticated software and
peripherals.
Three interchangeable, pin-compatible devices offer flexibility and low cost in development and production:
8748 with user-programmable and erasable EPROM
program memory for prototype and preproduction systems
8048 with factory-programmed mask ROM memory
for low-cost, high volume production
8035 without program memory, for use with
external program memories
"PROMPT" stands for PROgraMming Tool. It is a programmer for 8748 EPROMs, and a versatile aid for debugging
MCS-48 programs. Programs' can be entered via its integral
panel keyboard, programming socket, or serial channel.
Almost any terminal can be interfaced to the serial channel,
including a teletypewriter, CRT, or the Intellec Microcomputer Development System.
Programs, written' first in assembly language, are entered
in machine language and debugged with calculator-like ease
on the large, informative display and keyboard panel. Most
MCS-48 operations can be specified with only two keystrokes.
Each MCS-48 processor operates on a single +5 V supply,
with internal oscillator and clock driver, and circuitry for
interrupts and resets. Extra circuitry is in the 8048 ROM
processor to allow low power standby operation: the 64 x 8
RAM data memory can be independently powered.
Once entered, routines can be exercised one ,instruction
(single step) or many instructions at a time. The principal
MCSA8 register - the accumulator - is displayed while
single-stepping. Programs can be executed in real-time
(GO NO BREAK) or with as many as eight different
breakpoints (GO WITH BREAK).'
For systems reqUiring additional compatibility, the MCS-48
can be expanded with the new 82431/0 expander, 8155 I/O
and 256 byte RAM, 8755 I/O and 2K byte EPROM or
8355 I/O and 2K ROM devices. MCS-48 processors readily
interface to MCS-80/85 peripherals and standard memories.
PROMPT 48 is a complete, fully assembled and powered
microcomputer system including program memory, data
memory, I/O and system monitor beyond that available on
MCSA8 single component computers. 1 K bytes of PROMPT
system RAM serve as "writable program memory" - a
ROM simulator for the program memory on each MCS-48
computer. 256 bytes of PROMPT system RAM serve as
"external data memory," beyond the 64 register bytes on
each MCS-48 computer. Users may further expand program or data memory via the panel I/O PORTS and BUS
CONNECTOR.
The PROMPT.48 manual includes chapters for the reader
with little or no programming experience. Topics treated
range from number systems to microcomputer hardware
design. A novel, unifying set of tutorial diagrams MICROMAPs - simplify microcomputer concepts.
PROMPT 48 comes complete with two of these revolutionary MCS-48 processors - an 8748 and an 8035.
EXPANDING PROMPT 48™
PROMPT 48 may be expanded beyond the resources on the
MCS-48 single component computer and those in the
PROMPT system. External program and data memory may
be interfaced and input/output ports added with the 8243
I/O Expander.
The PROMPT panel I/O Ports and Bus Connector allow
easy access to all MCS-48 pins except those reserved for
control by the PROMPT system, namely EA external access,
SS single step, and Xl, X2 clock inputs.
PROMPT's handy, pocket-sized reference cardlet can be
affixed to the mainframe. Programming pads aid in the
organization and documentation of programs. These
features, plus a comprehensive design library of manuals,
articles and application notes, make the Intellec PROMPT
48 ideal for the newcomer to microcomputing.
THE REVOLUTIONARY MCS 48™ SINGLE
COMPONENT COMPUTER
Advances in n-channel MOS technology allow Intel, for the
first time, to integrate into one 40-pin component all
computer functions:
8-bit CPU
1 K x 8-bit EPROM/ROM Program Memory
64 x 8-bit RAM Data Memory
27 Input/Output Lines
8-bit Timer/Event Counter
More than 90 instructions - each one or two cycles - make
the single chip MCS-48 equal in performance to most
13-35
A Specialized PROM Programmer Kit, the PROMPT-SPP,
allows PROMPT 48 to serve as an economical 8748
Specialized PROM Programmer peripheral in Intellec
Microcomputer Development Systems. The PROMPT-SPP
cable plugs directly into the rear panel of the Intellec
Microcomputer Development System.
PROMPT 48 can be fully controlled either by the panel
keyboard and displays, or remotely by a serial channel.
Thus a teletypewriter or CRT can be used but neither is
required. Full remote control by a serial ohannel means
users can download and debug programs using the PROMPT
48 together with an Intellec Microcomputer Development
System.
INTELLEC@ PROMPT 48™
The 8748 is the first microcomputer fully integrated on
one component. All elements of a computing system are
provided, including CPU, RAM, I/O, timer, interrupts and
erasable, reprogrammable non-volatile program memory.
PROMPT's PROGRAMMING SOCKET programs this
revolutionary "smart PROM" - the 8748 - in a highly
reliable, convenient manner. A fail-safe interlock ensures
the device is properly inserted before applying programming
pulses. Each location may be individually programmed,
one byte at a time. A read-before·write programming
algorithm prevents device damage by inadvertently programming unerased memory.
The EXECUTION SOCKET accepts an 8035 or an 8748.
80th are supplied with each PROMPT 48, and either can
serve as heart of the PROMPT system. There are no processors within the PROMPT 48 mainframe, which instead
contains monitor ROM and RAM, user RAM, peripherals,
drivers, and sophisticated control circuitry.
Once a processor is seated in the execution socket and
power is applied the PROMPT system comes to life. One
can select various access modes such as program execution
from PROMPT system RAM, or from on-chip PROM. Thus
programs can first be executed from PROMPT RAM with
the 8035 processor. When debugging is complete, the 8035
(execution socket) processor can program the 8748 (programming socket) processor. Finally, a programmed 8748
processor can be exercised by itself from the execution
socket. The execution socket processor runs either monitor
or user programs.
SYSTEM RESET initializes th~ PROMPT system and enters
the monitor. MONITOR INTERRUPT exits a user program
gracefully, preserving system status and entering the
monitor. USER INTERRUPT causes an interrupt only if
the PROMPT system is running a user program.
A comprehensive system monitor resides in four 1K byte
read-only memories. It drives the PROMPT keyboard and
displays and responds to COMMANDS and FUNCTIONS.
The top 16 bytes of on-chip program memory must be used
by the PROMPT system to switch between monitor and
user programs. It requires one level of the MCSA8 eightlevel stack.
PROMPT 48's COMMANDS are grouped and color-coded
to simplify access to the 8748's separate program and data
memory. You can EXAMINE and MODIFY registers, data
memory or program memory.
Then either the NEXT or PREVIOUS register and memory
locations can be accessed with one keystroke.
Programs can be exercised in three modes. GO NO BREAK
runs in real time. GO WITH BREAK is not real time - after
each instruction the MCS-48 program counter is compared
against pending breakpoints. If no break is encountered,
execution resumes. GO SINGLE STEP exercises one
instruction at a time.
Commands are like sentences, with parameters separated by
NEXT. Each command ends with 0 EXECUTE/END.
o
In addition to the PROMPT basic COMMANDs, thirteen
functions simplify programming. Each is started merely
by pressing a HEX DATA/FUNCTIONs key and entering
parameters as required.
13-36
INTELLEC® PROMPT 48™
An optional cable, PROMPT·SER, directly connects the
PROMPT system to virtually any terminal via a rear access
slot. Another cable, PROMPT·SPP, allows programs and
data to be downloaded from the I ntellec Microcomputer
Development System to the PROMPT system for debugging.
You enjoy easy access to the pins of the executing processor via this I/O PORTS and BUS CONNECTOR. Only
the EA external access, SS single step and X 1, X2 clock
inputs are reserved for the PROMPT system.
Thus program or data memory may be expanded beyond
that provided on-chip or in the PROMPT system. I/O ports
can be expanded, as with the 8243, or peripheral controllers
can be memory-mapped. The I/O ports and Bus connector
allows the execution socket processor to be directly interfaced to your prototype system, yet be controlled from the
PROMPT panel.
The COMMAND/FUNCTION GROUP panel keyboard and
displays completely control PROMPT 48 - a teletypewriter
or CRT terminal is not needed.
A hyphen prompting character appears whenever a
command or function can be entered. Addresses and data
are shown whenever EXAM IN ing registers and memory.
Parameters for COMMANDs and FUNCTIONs are also
shown.
[£) Port 2 MAP allows you to specify the direction of each
pin on port 2. Port 2 is multiplexed to address external
program memory and expand I/O. Thus it must be
buffered; the P2 MAP command establishes the direction of buffering.
~ Program EPROM programs 8748 EPROMs.
I!l Byte Search with optional mask sweeps th rough
register, data or program memory searching for byte
matches. Starting and ending memory addresses are
specified.
lID
Compare will verify any portion of EPROM program
memory against PROMPT memory.
m:J
Move Memory allows blocks of register, data or program memory to be moved.
181
Access specifies one of six access modes for PROMPT
48. For example, EPROM, PROMPT RAM or external
program memory, and a variety of input/output
options may be selected.
lID
Breakpoint allows you to set and clear any or all of the
eight breakpoints.
~
Clears portions of register, data Or program memory.
[§] Word Search with optional mask sweeps through
register, data or program memory searching for word
matches. Starting and ending memory addresses are
specified.
!§] Hex Calculator
computes
hexadecimal
sums
[Q] Dumps register, data, or program memory to PROMPT's
serial channel, for example a teletypewriter paper tape
punch.
and
differences.
[]
[l] 8748 Program for Debug is similar to Program EPROM,
but ensures that the top of program memory contains
monitor reentry code for debugging.
Enter (reads) register, data or program memory from
PROMPT's serial channel.
[E] Fetches programs from EPROM to PROMPT RAM.
13-37
INTELLEC® PROMPT 48™
SPECI FICATIONS
SYSTEM DEVICES
TIMING
Both user programs and the PROMPT monitor enjoy access to
system devices: serial I/O, panel displays and keyboard. These are
memory-mapped to program memory addresses beyond 2K.
Basic Instruction
Cycle Time
Clock
2.5 "sec
tCY = 2.5 "sec
6 MHz ±0.1%
MEMORY BYTES
Register
Data
Program
Maximum
64
3328
4096
On Chip
64
In PROMPT 48
o
256
1024 RAM
1024 EPROM
o
The 8748 contains 64 bytes of register memory, no external data
memory, and 1024 bytes of EPROM program memory. The PROMPT
system provides 256 bytes of external data memory, and 1024 bytes
of RAM program memory. PROMPT RAM program memory can be
used in place of the On-Chip EPROM program memory; thus
programs less than 1024 bytes may be designed. For larger programs
additional memory can be directly interfaced to the MCSA8 bus via
the PROMPT panel I/O Ports and Bus Connector.
The SERIAL I/O port (data 820 16 , control 821 16 1 is defined by
software and jumpers for 110 ba..a, -20 mA current loop, but can
easily be jumpered for other baud rates and RS232C levels. Asynchronous or synchronous transmission, data format, control characters,
and parity can be programmed.
Software is used to debounce the PANEL KEYBOARD (data
810 16 1. The monitor's input routines (see SOFTWARE DRIVERSI
provide this debouncing and can be called from user programs.
Eight display ports (data 810-817 16 1 allow each of the PANEL
DISPLAYS to be written from user programs. Data written on a
display device will time out after a fixed interval. Displays must be
refreshed on a polled or interrupt-driven basis. User programs can
call SOFTWARE DRIVERS which provide this capability.
COMMANDS
0 Single Step
o GO 0 With Break
o No Break
0 Register
o Examine/Modify 0 Data
o Program
1
1
o Open Previous/Clear Entry
I/O PORTS
All MCS-48 I/O Ports are accessible on the PROMPT panel connector.
FUNCTIONS
BUS is a true bidirectional 8-bit port with associated strobes. If
I2l
the bidirectional feature is not needed, bus can serve as either
a statically latched output port or a non-latching input port. Input
and output lines cannot be mixed.
PORTS 1 AN 0 2 are each 8 bits wide. Data written to these ports is
latched and remains unchanged until written. As inputs these lines
are not latching. The lines of ports 1 and 2 are called quasibidirectional. A special output structure allows each line of port 1 and half
of port 2 to serve as an input, an output, or both. Any mix of input,
output, and both lines is allowed.
Three pins - TO, T1 and INT - can serve as inputs; TO can be
designated as a clock output. Input/Output can be expanded via the
PROMPT panel connector with a special I/O expander (82431 or
I3J
o Next
Port 2 Map
Program EPROM 187481
~ Search (R, D or P)* Memory for
1 byte, optional mask
[5] Search (R, D or PI Memory for
2 bytes, optional mask
1m Hexadecimal Calculator +,[LJ 8748 Program EPROM for Debug
I
Memory
G Execute/End
(8J Compare EPROM with memory
!m
Move Memory (R, 0 or PI
[81 Access
[SJ Breakpoint
[C] Clear Memory (R, D or PI
lCI
Dump Memory IR, D or PI
(E] Enter (Read) Memory (R, 0 or PI
lE] Fetch EPROM Program Memory
* R, 0 or P is Register, Data or Program.
SOFTWARE DRIVERS
Panel Keyboard In: K8IN, KDBIN
Panel Display Out: DGS6, DGOUT, HXOUT, BLK, REFS, ENREF
Serial Channel:
CI, CO, RI, PO, CSTS
standard peripherals.
CONNECTORS
RESET and INTERRUPTS
Serial I/O: 3M 3462-0001 Flat Crimp/AMP 88106-1 Flat Crimp/
TI H312113 Solder/AMP 1-583485-5 Solder.
RESET initializes the PROMPT system and enters the monitor.
MONITOR INTERRUPT exits a user program gracefully, preserving
!l;;y~tern statl)S and entering the mordtcr. USER !NTERRUPT c<::uscs
an interrupt only if the PROMPT system is running a user program.
The processor traps to location 3 16 , The MCS-48 timer/event counter
is not used by the PROMPT system and is available to the user.
Either timer flag or interrupt will signal when overflow has occurred.
The timer interrupt can be used only in the GO NO BREAK (real
timel mode.
EPROM PROGRAMMING
PROMPT 48 provides a programming socket to directly program
8748s. Programs are loaded into the PROMPT RAM program
memory via keyboard, EPROM, teletypewriter, or other serial
interface.
Panel I/O Ports and Bus Connector: 3M 3425 Flat Crimp. A
(,(lmplete cable set including \.IIJ!rewrap header for prototyping is
included with each PROMPT.
EQUIPMENT SUPPLIED
PROMPT 48 mainframe with two MCSA8 processors (8748,80351,
display/keyboard, EPROM Programmer, power supply, cabinet and
ROM-based monitor.
110 VAC power cable, 110 or 220 VAC, fuse, Panel I/O Ports and
Bus Connector cable set, PROMPT 48 User's Manual, PROMPT 48
Monitor Listing, Reference Cardlet, PROMPT 48 Programming Pads,
MCSA8 Microcomputer User's Manuals, MCSA8 Assembly Language
Manual, PROMPT 48 Schematics.
PHYSICAL CHARACTERISTICS
A fail-safe interlock ensures programming pulses are applied only if
the device is properly inserted. Inadvertent reprogramming is
prevented by a read-before-write programming algorithm. Each
location may be individually programmed, one byte at a time.
Maximum Height:
Width:
Maximum Depth:
Weight:
13.5cm (5.3
43.2 em (17
43.2cm (17
9.6 kg (21
in.1
in.1
in.1
Ib.1
PANEL I/O PORTS and BUS CONNECTORS
ELECTRICAL REQUIREMENTS
All MCS-48 pins, except five, are accessible on the I/O Ports and
Bus Connector. The five reserved for PROMPT system control are
EA external access, SS single step, Xl, X2 crystal inputs, and 5 V.
Either 115 or 230 V AC (± 10%1 may be switch-selected on the
mainframe. 1.8 amps max current (at 125 VAC!.
Due to internal buffering of the MCS48 bus, access times will be
negligibly degraded by the PROMPT system. Since MCS-48 processors do not communicate internal address gate status, bus data must
be driven out if neither PSEN nor R D is asserted.
ENVIRONMENTAL
ORDERING INFORMATION
PROMPT 48 or
PROMPTA8-220V
Intellec® PROMPT 48 MCSA8 Microcomputer
Design Aid. Complete with two MCSA8 processors (8748 and 8305), EPROM programmer,
integral keyboard, displays, and system monitor in ROM.
Frequency is 47·63 Hz.
'Operating Temperature:
Non-Operating Temperature:
PROMPT-SER
PROMPT-SPP
13-38
O°C to +40°C
_20° C to +65° C
Serial cable connects PROMPT to TTY, CRT
Specialized PROM Programmer Kit connects
PROMPT 48 to Intellec Microcomputer Development System for EPROM programming
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC® PROMPT SO/S5™
SOSO/SOS5 MICROCOMPUTER DESIGN AID
Simplifies microcomputing
Low Cost
Enter, run, debug and save machine language programs with calculator-like ease
PROM Programmer for UV Erasable, Electrically
Reprogrammable ROMs (EPROMs): 8708/2708/
2704 standard, 8755 with adaptor
Complete, fully-assembled microcomputer, including:
Standard 8080A on popular SBC
CPU
80/10 Single Board Computer
Memory 1 K byte RAM, 3K byte ROM, and
two spare 1 K byte 8708 EPROMs
24 programmable parallel I/O (TTL)
I/O
lines, including two:
8-bit
ports,
fully
implemented
switches, displays
Programmable serial I/O interfaces
directly with most terminals
Power
Integral keyboard and 16-digit display (no teletypewriter or CRT terminal required)
Extensive system monitor software in ROM:
Examine/Display /Modify
Registers and Memory
Enter, Run, Test, Single-Step programs
Hex Calculator
Move, Search Mp.mory Blocks
Self-programmable - user can add functions
Comprehensive design library
Only 11 0 or 230 V AC required
Intellec PROMPT 80/85 is a low-cost, fully assembled microcomputer design aid. PROMPT 80/85 simplifies the programming
of SBC 80 and System 80 microcomputers, as well as 8080/8085 processors, 8708/2708/2704/8755 EPROMs and 8255/8251
programmable I/O devices. 8680 programs can be entered and debugged with calculator-like ease on the large, informative
display and keyboard panel. The comprehensive design library with tutorial manual is ideal for newcomers to microcomputing.
PROMPT 80/85's SBC 80/10 can be expanded using the SBC modular cardcage. And PROMPT 80/85 can serve as an econom·
ical 8708/8755 Specialized PROM Programmer (SPP) peripheral in Intellec Microcomputer Development Systems.
13-39
INTELLEC® PROMPT 80/85 ™
PROM PROGRAMMER
8708 UV Erasable, Electrically Reprogrammable ROMs
(EPROMs) can be easily programmed, compared, and
transferred to RAM using the zero-insertion force socket
on the panel. A new technique allows 8708 to be partially
programmed in mUltiple blocks of 16 bytes. Thus, small,
modular routines can be entered, tested, and readily saved
using EPROM.
EPROMs can also be conveniently duplicated. The master
(original) device plugs into the SBC 80/10 inside PROMPT
80, and can be copied to the panel programming socket.
8755 EPROMs can also be programmed, compared and
transferred over any address range using the optional
adaptor PROMPT 875.
REGISTER/DISPLAY GROUP
All 8080 registers can be displayed, even while singlestepping programs. The registers are shown in three rows:
first row:
B
C
D
E
second row:
H
L
Flags
A
third row:
Program Counter
Stack Pointer
One register row is visible at a time. Three small LEDs to
the left of these rows indicate which row is displayed. The
SCROLL REGISTER DISPLAY command displays the
next row (first, second, third, etc.)
RESET, INTERRUPTS
SYS RST resets the system, initiz.lizes the PROMPT 80/85
registers and enters the monitor. MON INT interrupts a user
program and enters the monitor saving the user registers.
USR INT is a user interrupt which traps PROMPT 80/85 to
location 3C0216.
MONITOR
A comprehensive system monitor resides in three 1 K
ROMs. It drives PROMPT's keyboard, displays, and
responds to COMMANDS and FUNCTIONS. The moni·
tor is modular, organized so that the third ROM may be
removed if F FUNCTIONS are not required. This allows
sizable user routines - as much as 2K ROM/EPROM and
nearly 1 K RAM - to be exercised.
COMMANDS
PROMPT 80/85 commands are compatible with those used
by Intel's SDK, SBC, and Intellec monitors.
You can EXAMINE/MODIFY a REGISTER, or DISPLAY/MODIFY MEMORY. Then either the NEXT or
PREVIOUS register and memory locations can be opened
with one button.
The GO command executes programs, allowing multiple,
optional breakpoints. Or a program can be SI NG LE
STEPped, executed one instruction at a time.
The SCROLL REGISTER DISPLAY command displays
the next row of the REGISTER/DISPLAY GROUP.
13-40
INTELLEC$ PROMPT 80185™
INPUT/OUTPUT GROUP
The INPUT/OUTPUT (i/O) GROUP features two fully
implemented 8-bit ports, both with displays, and with
latch switches for the input port E9_ The port addresses
are clearly marked E8 and E9_ Those two ports and a
third, at EA, are easily accessible on the I/O PORTS
CONNECTOR_ Negative true logic is used throughout the
I/O GROUP and PORTS CONNECTOR to enhance noise
immunity and allow wire-ANDing.
PARALLEL I/O
The I/O PORTS CONNECTOR provides easy access to 24
parallel, TTL-compatible lines. These lines are addressed
as three ports (each 8 lines), port E8, E8, and EA.
These ports can be defined to be input or output by software. Defining control words, tabulated in "Specifications", are sent OUT to port EB, the control word register_
SERIAL I/O
PROMPT's programmable serial I/O readily interfaces
with most terminals. Jumpers select either 20 mA teletypewriter (TTY) current loop or RS-232C operation, and
the appropriate communications frequp.ncy. Asynchronous or synchronous transmission, data format, control
characters, parity, and transmission rate can be programmed_
A serial cable kit, PROMPT-SER, connects PROMPT to
either a teletypewriter or RS-232C standard (CRT) terminal through a rear chassis access slot. Teletypewriters may
require minor reader control modifications.
COMMAND/FUNCTION DISPLAYS
The COMMAND/FUNCTION displays show addresses and
data when DISPLAYing MEMORY, and parameters for
COMMANDS and FUNCTIONS are entered.
FUNCTIONS
Eight FUNCTIONS are provided by PROMPT. Others
may be added by the user. Pressing a HEX DATA/FUNCTIONS key (0-7) starts a function.
Commands are entered naturally, like phrases in a sentence: the NEXT parameters are separated bycommas GJ
and command sentences end with [J EXECUTE/END_
The commands do what makes sense_ For example:
[jj]
is
FO
Read Paper Tape
[]
is
F1
Write Paper Tape
I2l is
F2
Program 8708 EPROM, Compare
[aJ
is
F3
Compare 8708 EPROM
~
is
F4
Transfer 8708 EPROM to RAM
[§J
is
F5
Move Block Memory
(§]
is
F6
Hexadecimal Calculator, +, -
ill is
F7
Byte Search Memory, optional mask
IS]
is
F8 Word Search Memory, optional mask
With the optional PROMPT-875 adaptor,
GO D [] [ijJ [ijJ [J EXECUTE/END
starts the program at address 100_
GO D [j] [ijJ [ijJ GJ NEXT I2l [ijJ [ijJ [J EXECUTE/END
starts the program at 100, but stops if you get to 200,
a breakpoint_
GO D [J EXECUTE/END
starts the program where you last stopped_
13·41
lID is
I&J is
F9
Program 8755 EPROM, Compare
FA
Compare 8755 EPROM
IS]
FB
Transfer 8755 EPROM
is
INTELLEC® PROMPT 80185™
PROMPT SIMPLIFIES MICROCOMPUTING
A COMPLETE COMPUTER
Intellec PROMPT 80/85 simplifies the programming of
8080/8085 processors, SBC 80 and System 80 microcomputers, as well as 8708/8755 EPROMs and 8255/8251
programmable I/O devices.
The heart of PROMPT 80/85 is the popular SBC 80/10
Single Board Computer, a complete computer on a single
printed circuit board_ The SBC 80/10 includes an 8080A,
1K bytes of static RAM memory, and sockets for 4K bytes
of EPROM memory. Signals to the SBC 80/10 include 48
programmable, parallel I/O lines with sockets for interchangeable line drivers and terminators, a programmable
serial channel, a multi-source single level interrupt network, and bus drivers for memory and I/O expansion.
Read-only-memory may be added in 1K byte increments
using Intel 8708 EPROMs or 8308 ROMs.
PROMPT is a low-cost programming tool. It is a microcomputer design aid - not a development system with
sophisticated software and peripherals.
PROMPT encourages the preparation and verification of
small, modular routines which together may comprise
sizable programs. These are written in assembly language,
then entered in machine language and debugged with
calculator-like ease on the large, informative display and
keyboard panel.
The central processor for PROMPT's SBC 80/10 is Intel's
powerful B-bit n-channel MOS 8080A CPU. The 80BOA
contains six 8-bit general-purpose registers and an accumulator. The six general-purpose registers may be addressed
individually or in pairs, providing both single and double
precision operations.
Many 8080 operations can be specified with only two
key strokes. Once entered, programs can be exercised one
instruction (single step) or many instructions at a time.
And, any of the 8080 registers can be watched while
single-stepping.
The 80BOA has a 16-bit address bus which allows direct
addressing of up to 64K bytes of memory. An external
stack, located anywhere in read/write memory, may be
used as a last-in/first-out store_ The contents of the program counter, accumulator, flags, and all of the generalprupose registers are stacked using a 16-bit pointer. Subroutine nesting is bounded only by memory size.
Programs are readily saved and instantly reloaded via UV
Erasable, Electrically Reprogrammable ROMs (EPROMs).
PROMPT 80/85 can program the popular 8708 EPROMs in
small blocks, so routines can be debugged and saved incrementally. Several programs are pre-recorded as examples on
PROMPT's spare 8708 EPROMs
PROMPT 80/85 is a complete, fully assembled and powered
8080 microcomputer, including RAM, I/O, and system
monitor in ROM. Twenty-four lines of programmable,
TTL-compatible, parallel I/O are easily accessed on a
panel connector. Two 8-bit ports are fully implemented,
one with displays for output, the other with displays and
switches for input. PROMPT's programmable serial I/O
interfaces directly with most terminals. A teletypewriter
or
can be usec..l, uui neither is required because of
PROMPT's built-in keyboard and display.
EXPANDING PROMPT 80/85 TM
ern
The PROMPT 80/85 manual includes chapters for the reader with little or no programming experience. Topics treated
range from the number system to microcomputer hardware design. A novel, unifying set of tutorial diagrams MICROMAPSTM - simplify microcomputer concepts.
PERIPHERALS
& f\I1EMORY
0000
MEMORV
PROMPT 80/85's SBC 80/10 can be expanded via the SBC
604 Modular Cardcage. The cardcage houses the SBC
80/10 and up to three expansion boards. Memory and I/O
can be added in various combinations_ Additional power
may be required.
CENT~AL
PROCESSOR
:: B~L.I___. .I
FFFFB/
',.
A
OTHER
REGISTERS
'--------'
Programming pads aid in the organization and documentation of programs. These features, plus a comprehensive
design library of manuals, articles, and applications notes,
make Intellec PROMPT 80/85 ideal for the newcomer to
microcomputing.
13-42
A Specialized PROM Programmer kit, the PROMPT-SPP,
allows PROMPT 80/85 to serve as an economical 8708/
8755 Specialized PROM Programmer peripheral in Intellec
Microcomputer Development Systems. The PROMPT-SPP
cable plugs directly into the rear panel of the Intellec
Microcomputer Development System.
INTELLEC® PROMPT 80/8S™
SPECI FICATIONS
SYSTEM MONITOR
WORD SIZE
Instruction: 8, 16, or 24 bits
Data:
8 bits
Resides in three 8308 ROMs, 0 to 3FF16, 40016 to 7FF16 and
80016 to BFF16. The third ROM implements F FUNCTlbNS,
and can be removed. PROMPT has an unused ROM/EPROM
socket at address C0016 to FFF16.
COMMANDS
Examine/Modify Register
Go (with optional breakpoints)
Scroll Register Display
Next 0
TIMING
Basic Instruction: 1.95/lsec
tCY ~ 488 nsec
Cycle Time:
Clock:
2.058 MHz ± 0.1%
MEMORY BYTES
ROM/PROM
RAM
Addressing
On Board
Monitor Uses
0·OFFF16
3COO-3FFF 16
4096
1024
2048 or 3072
114
Up to 48K bytes may be added using optional RAM, ROM, or
PROM expansion boards and the SBC 604 Cardcage.
I/O ADDRESSING
Ports E4 to E7 are dedicated to PROMPT's display/keyboard
groups. Ports E8 to EB drive the panel I/O PORTS CONNECTOR and PROM SOCKET.
I/O Ports Connector
PROM Socket
Dedicated to
Display/Keyboard
PORT
A
B
ConC trol
E4
E5
E6
E7
A
B
E8
E9
Serial I/O
USART
CanC trol Data
EA
EB
EC
Control
ED
PARALLEL I/O
The panel I/O ports can be defined input or output by outputing
control words to port address EB.
lOUT this to EBI
Port E8
Bits 7-0
Bits 7-0
80
OUTPUT
81
OUTPUT
82
OUTPUT
HEX Control Word
Bits 7-4
Port EA
Bits 3-0
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
Port E9
83
OUTPUT
INPUT
OUTPUT
84 or 85
OUTPUT
STROBED
OUTPUT
OUTPUT
86 or 8
OUTPUT
STROBED
INPUT
OUTPUT
Bits 2, 1,
o are strobes
All input ports are TTL-compatible. Ports E8 and EA are one-load
fully TTL-compatible as output. Port E9 is ordinarily used as
input. When used as output, E9 can sin k at least one low-power
TTL load.
SERIAL I/O
The serial I/O port is defined by software and jumper. PROMPT
is configured at the factory for 20 mA current loop TTY interface,
but can easily be jumpered for RS-232C levels.
Asynchronous or synchronous transmission, data format, control
characters, parity and transmission rate can be programmed.
INTERRUPTS
PROMPT 80/85 provides a panel user interrupt to 3C0216. The
SBC 80/10 supports single level vectoring to location 3816.
Requests may originate from user-specified I/O (2), the parallel
ports (2), or serial port (2).
FUNCTIONS
IQ) Read Tape
III Write Tape
111 Program 8708, Compare
[>J Compare 8708
@] Transfer 8708 to RAM
Display/Modify Memory
Single Step
Open Previous/Clear Entry
o Execute/end
With 875 adaptor:
IT!] Program 8755, Compare
@] Compare 8755
[0] Transfer 8755
lID Move Block Memory
[ID Hexadecimal Calculator,
+, -
Byte Search Memory, optional mask
rID Word Search Memory. optional mask
(l]
SOFTWARE DRIVERS
Panel Keyboard Input
Console Terminal Input
TTY Reader Input
Panel Display Output
Console Terminal Output
TTY Punch Output
CONNECTORS
PROMPT Panel I/O Ports
SSC 80/10 Parallel I/O
SBC 80/10 Serial I/O
SBC 80/10 Bus
SBC 80/10 Auxiliary Bus
3M 3425 Flat
3M 3415 Flat
3M 3462 Flat
CDC VPS01 E43DOOA 1
TI H312130
EQUIPMENT SUPPLIED
PROMPT 80/85 mainframe with SBC 80/10, display/keyboard,
PROM Programmer, power supply, cabinet, and ROM·based system monitor
(2) 8708 EPROMs with pre-recorded example programs
110 V AC power cable, 110 or 220 V AC fuse
PROMPT 80/85 User's Manual, PROMPT 80/85 Monitor Listing
PROMPT 80/85 Programming Pads
8080 Systems User'S Guide, 8080 Assembly Language Manual
System 80/10 Hardware Reference Manual
Design Library of Application Notes, Article Reprints
PROMPT 80 Schematics
PHYSICAL CHARACTERISTICS
Maximum Height: 13.5cm (5.3 in.!
Width:
43.2 em (17 in.!
Maximum Depth: 43.2 em (17 in.)
Weight:
9.6 kg (21Ib)
ELECTRICAL REQUIREMENTS
Either 115 or 230 V AC (± 10%) may be switch-selected on the
mainframe. 1.8 amps max current (at 125 V ACI.
Frequency is 47-63 Hz.
VDltage
Internal PROMPT
80/85 Supply
PROMPT 80/85
Requires
+26.5
0.1A
0.03A
+12
1.2A
0.5A
+ 5
6.0A
5.0A
- 5
0.3A
0.1A
-12
0.3A
0.2A
EPROM PROGRAMMING
8708/2708/2704 EPROMs can be programmed in multiple blocks
of 16 bytes. Starting and ending memory address need only differ
by a multiple of 16, and starting EPROM address end XXO hexadecimal (X ~ don't care). Programming time is 115 sec for 1 K
byte,3 sec for 16 bytes.
8755 EPROMs can be programmed at any addresses using the
optional PROMPT 875 adaptor. Programming time is 52 sec for 1
1K byte.
Fixed over-voltage protect on 5V supply 6.2-6.7 volts.
EPROMs may be erased by exposure to high intensity short-wave
ultraviolet light at a wavelength of 2537 A. The recommended
integrated dose (UV intensity x exposure time) is 10W-sec/cm 2 .
ENVI RONMENTAL
Operating Temperature:
Non-Operating Temperature:
ORDERING INFORMATION, COMPATIBLE EQUIPMENT
PROMPT-80 or
Intellec PROMPT 80/85 MCS80/85 MicroPROMPT-80-220V Computer Design Aid. Complete with SSC
80/10 Single Board Computer (8080 CPU),
integral keyboard, displays and EPROM
programmer.
PROMPT-875
PROMPT-SER
PROMPT-SPP
13-43
10°C to 40°C
_20°C to 65°C
Optional 8755 programming adaptor.
Serial Cable connects PROMPT to TTY, CRT.
Specialized PROM Programmer Kit connects
PROMPT 80/85 to Intellec Microcomputer
Development Systems for 8708/8755 EPROM
programming.
in1:el®
MICROCOMPUTER DEVELOPMENT SYSTEMS
ICE-30™
3001 MCU IN-CIRCUIT EMULATOR
Extends the Intellec® diagnostic capabilities into
user configured systems, allowing in-circuit emulation of the user system's 3001 MCU
Direct Intellec® System connection to the user
configured system is achieved via an external cable
with 3001 compatible 40-pin connector
Provides for the display of all 3001 address, status,
and control lines for the current micro-instruction
executed.
Allows for
single-step microprogram execution
Presets the 9-bit 3001 Microprogram Address
Register and sets two independent breakpoints on
micro-instruction addresses generated by the 3001
Allows two independent breakpoints to be set on
the logical combination of any three TTL compatible signals in the user system via three logic probes
Allows the microprogram word contents to be displayed and modified when used with the optional
ROM-SIM modules
ICE-30 is an Intellec resident module that provides the user with direct in-circuit emulation of the 3001 Microprogram Control Unit (MCU) and complete control over the execution of user developed microprograms. Through in·circuit emulation,
the designer is able to set microprogram address breakpoints, single-step microprogram execution, and monitor all of the
address, status, and control I ines of the 3001.
13-44
ICE-30™ MODULE
HARDWARE
hardware. ICE30 recognizes a set of commands issued
by the user, translates the commands, and places the
encoded results into a control block for the hardware.
In this fashion, the user can establish a dialogue with the
3001 Microcomputer Control Unit (MCU) which is
connected to the system, thus providing the capability
to monitor, control or alter its operation.
ICE-30 consists of a single PC board that resides in the
Intellec System. An external cable from the board, termiminating in a 3001 compatible 40-pin connector, forms
the interface to the user system. Through the 3001 compatible connector, ICE-30 plugs directly into the user system's 3001 socket and allows the user to completely
monitor and control all the activities of the MCU.
ICE30 is capable of operating in conjunction with a
RAM-based microprogram in the optional ROM-SIM
modules (see ROM-SIM Data Sheet #98-211A). The commands provided by ICE30SD may therefore be divided
into three categories: (1) Those commands unique to the
optional ROM simulator, (2) Those which support
ICE30SD functions, and (3) Those commands which are
common to both ROM-SIM and ICE30SD.
The figure below shows the hardware supplied with the
ICE-30 package.
ICE30 FUNCTION COMMANDS
13001
SET
Assign values to the two hardware breakpoint registers, the 9-bit microprogram
address register, and the PR latch.
GO
Initiates real-time emulation which continues until an address encountered matches
one of the two breakpoint values.
STEP
Causes execution to proceed in·a non-realtime single-step micro-instruction mode.
CONTINUE
Resumes step mode execution following a
break condition.
ENAB LE
Activates or deactivates the two hardware
breakpoint registers prior to issuing the
'GO' command.
TRAP
Used to set or remove any of the five-step
mode software traps (software breakpoint
registers).
C:=J
lCE·30 BOARD
COMMON COMMANDS
(Common to ICE30 and Optional ROM-SIM)
DISPLAY
Displays the contents of a specified address
or address range in the simulated control
storage.
BASE
Establishes a mode of display of all output
data for the 'DISPLAY' command.
RESTART
Reinitializes all program variables, except
the ROM-51 M configuration values, and
starts execution at the point following the
ROM-SIM configuration sequence.
EXIT
Causes ICE30SD to terminate.
ICE-30 MODULE HARDWARE
By inserting the board into the Intellec Bus inside a basic
Intellec system, a 3001 MCU chip in the user's system
may be emulated. The ICE-30 board contains a 3001
MCU and peripheral logic required to monitor the 3001
operation and store trace information. The external cable
carries status and control lines to and from the 3001
compatible 40-pin connector and the three logic probe
lines. In addition, a MATCH line is brought out on the
external cable which allows ICE-30 to control the user
system's master clock and perform microprogram halt and
single-step functions.
ROM-SIM COMMANDS
ICE30SD provides commands necessary to drive the
optional Intellec microprogram control storage simulation module, ROM-SIM. For a description of ROMSIM capabilities, ask for the ROM-SIM Data Sheet #98211A.
SOFTWARE
The ICE-30 Software Driver, ICE30SD, is an Intellec
Microcomputer Development System RAM-resident program which provides a user interface with the ICE-30
ICE30SD is written in Intel's high-level programming
language PL/M and will execute in the minimum 16K
RAM Intellec configuration.
13-45
ICE-30™ MODULE
16
ADDRESS BITS
I
READ/WRITE
COMMANDS
I
I
MODULE-SELECT
AND
ADDRESS
DECODING
I
SYSTEM
9
LOGIC
I
BUS
I
I
8
DATA BITS
BIPOLAR
RAM
8,192 BITS
I
I
I
ROM-SIMULATOR
L __ ~O~~ _ _
12
I ADDRESS
BITS
I
I
I
I
I
I
I
I
I
-.J
BUFFER
BOARD
CABLE
ASSEMBLY
USER
_ROM
SOCKETS
80R 16
DATA BITS
[-------,
1
I
I
I
I
I
BREAKPOINTS
AND
TRACE LOGIC
I
I
I
I
MULTIPLEXER
I
I
I
I
I
I
I
3001 MCU
CHIP
1 1 1
BUFFER
BOARD
CABLE
ASSEMBLY
I I
MATCH/
I
I
I
I
I
TRACE MEMORY
BREAKPOINT
COMPARATOR
I
IL
3 LOGIC
PROBES
~
ICE-30
MODULE
_
__
___
I
I,
.........J
FUNCTIONAL BLOCK DIAGRAM OF ICE-30 MODULE,
OPERATING IN CONJUNCTION WITH
ROM-SIMULATOR MODULE
SPECIFICATIONS
PHYSICAL CHARACTERISTICS
EQUIPMENT SUPPLIED
(Printed Circuit Board)
Printed Circuit Board
Interface Cables and
Buffer Enclosure Assembly
Reference Manual
Software Paper Tape
Width: 12,00 in,
Height: 6,75 in_
Depth:
0,50 in,
ORDERING INFORMATION
Part Number
Description
MDS-30-ICE
3000 Series In-Circuit Emulator
13-46
USER'S
3001 MCU
CHIP
SOCKET
MICROCOMPUTER DEVELOPMENT SYSTEMS
ICE-41TM
UPI-41TM IN-CIRCUIT EMULATOR
Extends Intellec® Microcomputer Development
System debug power to user configured system via
an external cable and 40-pin plug, replacing the
user UPI-41 device
Eliminates the need for extraneous debugging tools
residing in the user system
Collects address, data and UPI-41 status information on machine cycles emulated
Emulates user system UPI-41 device in real time
Provides capability to examine and alter CPU registers, memory, flag values, and to examine pin and
Allows user configured system to use static RAM
memory for program debug
port values
Provides hardware comparators for user designated
break conditions
Integrates hardware and software efforts early to
save development time
The ICE_41TM Module is an Intellec® System resident module that interfaces to any user configured UPI-41 system_ With an
ICE-41 Module as a replacement for a prototype system UPI-41 device, the designer can emulate the system UPI-41 device in
real time, single-step the system's program, and use internal static RAM memory for user system debugging. Powerful debug
capability is extended into the UPI-41 system while ICE-41 debug hardware and software remain inside the Intellec System.
Symbolic reference capability allows the designer to use meaningful symbols rather than absolute values when examining and
modifying memory, registers, flags, and I/O ports in his system.
13-47
ICE-41TM
Attempting to mesh completed hardware and software in
the final product can be costly and frustrating. The ICE-41
Module allows the designer to use his hardware and software to help debug each other as they are developed.
Hardware comparators provide the capability for breaking
system emulation under specified conditions. An additional
synchronization line allows the ICE-41 Module to break
emulation on a condition outside the scope of the UPI-41
device, or, alternatively, allows the ICE-41 to signal an
external device when a condition is recognized by the hardware comparators.
Static RAM memory is provided for program development.
Programs can be easily altered during debug sessions without the need for program reassembly and the reprogramming of PROM memory. Internal UPI-41 registers and flags
are accessible to the designer for checking program logic.
A trace buffer stores information on code executed, address,
register, flag, and I/O operations during real time execution.
The designer can examine this information after emulation
is terminated to check the hardware/software interaction of
his system.
The ICE-41 Module is a microcomputer system utilizing
Intel's UPI-41 microprocessor as its nucleus. This system
communicates with the Intellec System 8080 processor via
direct memory access. Host processor commands and
ICE-41 status are interchanged through a DMA channel. A
parameter block resident in Intellec System main memory
contains detailed configuration and status information
transmitted in an emulation break.
ICE-41 hardware consists of two PC boards, which reside in
the Intellec System chassis, and a cable assembly which
interfaces to the user system. A 40-pin socket on the end of
the cable assembly plugs directly into the socket provided
for the user's UPI-41 device.
The ICE-41 software is an Intellec System program which
provides the user with flexible, easy-to-use commands for
defining breakpoints, initiating emulation, and interrogating
and altering user system status recorded during emulation.
A broad range of commands provides the user with maximum flexibility in describing the operation to be performed.
SPECIFICATIONS
ICE-41 OPERATING ENVIRONMENT
EOUIPMENT SUPPLIED
Required Hardware:
Intellec® Microcomputer Development System
System Console
Intellec Diskette Operating System
ICE-41 Module
Required Software:
System Monitor
IS!S-!!
ICE-41 Diskette-Based Software
Printed Circuit Boards
Interface Cables and Buffer Module
Operator's Manual
Schematic Diagram
ICE-41 Diskette-Based Software
ORDERING INFORMATION
Part Number
Description
MDS-41-ICE
UPI-41 In-Circuit Emulator,
Cable Assembly and
Interactive Diskette
Software included
13-48
inter
MICROCOMPUTER DEVELOPMENT SYSTEMS
ICE-48™
MCS-48™ IN-CIRCUIT EMULATOR
Extends Intellec Microcomputer Development
System debug power to user configured system via
an external cable and 40-pin plug. replacing the
system MCS-48 device
Eliminates the need for extraneous debugging tools
residing in the user system
Collects bus. register and MCS-48 status information on instructions emulated
Emulates user system MCS-48 device in real time
Shares static RAM memory with user system for
program debug
Provides capability to examine and alter MCS-48
registers. memory. flag values. and to examine pin
and port values
Provides hardware comparators for user designated break conditions
Integrates hardware and software efforts early to
save development time
The ICE-48 module is an Intellec-resident module that interfaces to any MCS-48 system. The MCS-48 family consists of the
8048,8748, and 8035 microcomputers. The ICE-48 module interfaces with an MCS-48 system through a cable terminating
in an MCS-48 pin-compatible plug which replaces the MCS-48 device in the system. With the ICE-48 plug in place, the
designer has the capability to execute the system in real time while collecting up to 255 instruction cycles of real time trace
data. In addition, he can single step the system program to monitor more closely the program logic during execution. Static
RAM memory is available through the ICE-48 module to emulate MCS-48 program and data memory. The designer can
display and alter the contents of data and replacement RAM control memory, internal MCS-48 registers and flags; and 1/0
ports. Powerful debug capability is extended into the MCS-48 system while ICE-48 debug hardware and software remain
inside the Intellec System. Symbolic reference capability allows the designer to use meaningful symbols rather than absolute
values when examing and modifying memory, registers, flags, and 110 ports in this system.
13-49
ICE-48™ MODULE
DEBUG CAPABILITY INSIDE USER SYSTEM
MEMORY MAPPING
The ICE-48 module provides the user with the ability to
debug a full prototype or production system without
introducing extraneous hardware or software test tools.
The 8748 and 8048 contain internal program and data
memory. Both program and data memory can be expanded
using external memory devices.
The ICE-48 module connects to the user system through
the socket provided for the MCS-48 device in the user
system. Intellec memory is used for the execution of the
ICE-48 software. The Intellec console and file handling
capabilities provide the designer with the ability to
communicate with the ICE-48 module and display
information on the operation of the prototype system.
When the MCS-48 microcomputer is replaced by the ICE48 socket in a system, the ICE-48 module supplies static
RAM memory as a replacement for the internal
microcomputer memory. The ICE-48 module has enough
RAM memory available to emulate uptothetotal4Kcontroi
memory capability of the system. The ICE-48 module also
provides for up to 320 bytes of data memory.
BATCH TESTING
In conjunction with the ISIS-II diskette operating system,
the ICE-48 module can run extensive system diagnostics
without operator intervention. The designer or test
engineer can define a complete diagnostic exercise which
is stored in a file on the diskette. When activated with an
ISIS-II SUBMIT command, this file can instruct the ICE-48
module to execute the diagnostic routine and store the
results in another file on the diskette. Results are available
to the designer at his convenience. In this way, routine
diagnostics and long term testing can be donewithouttying
up valuable manpower.
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
The user prototype need consist of no more than an MCS48 socket and timing logic to begin integration of software
and hardware development efforts. Through the ICE-48
module mapping capabilities,lnteliec system resources can
be accessed to replace prototype memory. Hardware
designs can be tested using the system software which will
drive the final product.
The system integration phase, which can be costly when
attempting to mesh completed hardware and software
products, becomes a convenient two-way debug tool when
begun early in the design cycle.
REAL TIME TRACE
The ICE-48 module captures trace information while the
designer is executing programs in real time. The
instructions executed, program counter, port values for Port
0, Port 1, and Port 2, and the values of selected MCS-48
status lines are stored for the last 255 instruction cycles
executed. When retrieved for display, code is disassembled
for user convenience. This provides data for determining
how the user system was reacti ng prior to emulation break.
It is available whether the break was user initiated or the
result of an error condition.
The ICE-48 module separates replacement control memory
into 16 256-byte blocks. Replacement external data
memory consists of one 256-byte block. Each block of
memory can be defined separately as supplied by the user
system or supplied by the ICE-48 module. The user may
assign ICE-4B equivalent memory to take the place of
external memory not yet supplied in his system.
During final debug stages when external or resident 8748
PROM is used for program execution, thedesignercan load
the program back to ICE-48 memory to test out program
changes before reassembly and reprogramming the PROM.
SYMBOLIC DEBUGGING
ICE-48 software provides symbolic definition of all MCS-48
registers, flags, and selected MCS-48 pins. Symbolically
defined pseudo registers provide access to the sense of
MCS-48 flipflops which enable time, counter, interrupt,
and Flag O/Flag 1 options.
In addition, the user may reference locations in program
and data memory, or their contents, symbolically. The user
symbol table which is generated along with the object file
during a program assembly may be loaded to Intellee
memory for access during emlliation. The user is
encouraged to add to this symbol table any additional
symbolic values for memory addresses, constants, or
variables th,at he mayfind useful during system debugging.
Symbols may be substituted for numeric values in any of
the ICE-48 commands.
Symbolic reference is a great advantage to the system
designer. He is no longer burdened with the need to recall
or look up addresses of key locations in his program which
can change with each assembly. Meaningful symbols from
his source program can be used instead. For example, the
command:
GO FROM. START TILL XDATA . RSLT WRITIEN
begins execution of the program at the address referenced
by the label START in the designers assembly program. A
breakpoint is set to occur the first time the microprocessor
writes to the external data memory location referenced by
RSLT. The designer does not have to be concerned with the
physicallocatlons of START and RSLT. The ICE-48 software
driver supplies them automatically from information stored
in the symbol table.
For detailed information on the actions of internal registers,
flegs, or other system operations, the user may operete in
single or multiple-step sequences tailored to system debug
needs.
13-50
ICE-48™ MODULE
ICE-48 MODULE BLOCK DIAGRAM
USER SOCKET
11
,I-
r
II
CABLE
BUFFER
II
~
TRACE
MEM
INSTR
: SIMULATOR
r--
,-
W
CONTROL PROCESSOR DATA
1.,)-
,---.I
I
11-
P1
HLATCHrADDR
8748 P2A
ADDR
W/INTERNAL
MONITOR PGM
PO
DATA
EASS
I
I I
I
BREAK
TIMING
256-BYTE
DATAMEM
I
P~~
MEM
1
I I
1
'-,-
INTERNAL
TIMER
CONTROL
PROGRAM
«
LL
a:
1 BREAK·
POINT ,I
COMPARE
11
w
u
w
I-
r--
Z
8080
f.- CI)
:J
CONTROL
I-- ttl
PROCESSOR
U
W
'"' lJ
CONTROL
PROCESSOR
INTERFACE
..J
..J
W
I-
Z
l:=
CONTROL
SCRATCH
PAD
DECODE
HARDWARE
Three 15-bit hardware breakpoint registers are available
which can be loaded by the user. While in emulation mode,
a hardware comparator is constantly monitoring address
and status lines for a match which will terminate an
emulation.
The ICE-48 module is a microcomputer system utilizing
Intel's 8748 microcomputer as its nucleus. The 8748
provides the MCS-48 emulation characteristics. The ICE48 module uses an Intel® 8080 to communicate with the
Intellec host procesor via a DMA port. The 8080 also
controls an internal ICE-48 bus for intra module communication.
The breakpoint registers provide a signal when a match is
detected. The user can disable the emulation break
capability and use the signal to synchronize other debug
tools.
ICE-48 hardware consists of two PC boards, the Controller
Board and the Emulator Board, which reside in the Intellec
chassis. A cable interfaces the ICE-48 boards to the MCS48 system. The cable terminates in a MCS-48 pin
compatible plug which replaces any MCS-48 device in the
user system.
The Controller Board returns real time trace data, MCS-48
register, flag, and pin values, and ICE-48 status
information, to a control block in the Intellec System when
emulation is terminated. This information is available to the
user through the ICE-48 interrogation commands. Error
conditions, when present, are automatically displayed on
the Intellec System console.
REAL TIME TRACE
The Controller Board also contains static RAM memory
which can be used to emulate MCS-48 program and data
memory in real time. 4K of memory is available in 16256byte pages to emulate MCS-48 PROM or ROM program
memory. A 256-byte page of data memory is available to
access in place of MCS-48 external data memory. The
Controller Board address map directs the ICE-48 module to
access either replacement ICE-48 memory or actual user
system external memory in 256 byte segments based on
information provided by the user.
While the ICE-48 module is executing the user program, it
is monitoring port, program counter, data and status lines.
Values for each instruction cycle executed are stored in a
255 x 44 real time RAM trace buffer. A resetable timer
resident on the Controller Board counts instruction cycles
and provides timing for the trace monitor.
CONTROLLER BOARD
The ICE-48 module talks to the Intellec System as a
peripheral device. The Controller Board receives commands from the Intellec System and responds through a
DMA port.
13-51
ICE-48™ MODULE
EMULATOR BOARD
SOFTWARE
The Emulator Board contains the 8748 and peripheral logic
required to emulate the MCS-48 device in the user system.
A software selectable 6 MHz or 3 MHz clock drives the
emulated MCS-48 device. This clock can be disabled and
replaced with a user supplied TTL clock in the user system.
The ICE-48 software driver is a RAM-based program which
provides the user with an easy-to-use command language
for defining breakpoints, initiating real time emulation or
single step operation, and interrogating and altering user
system status recorded during emulation. The ICE-48
command language contains a broad range of modifiers
which provide the user with maximum flexibility in defining
the operation to be performed.
CABLE CARD
The Cable Card is included for cable driving. It transmits
address and data bus information to the user system
through a 40-pin connector which plugs into the user
system in the socket designed for the MCS-48 device.
The ICE-48 software driver is available on diskette and
operates in 32K of Intellec RAM memory.
ICE-48 COMMANDS
EMULATION COMMANDS:
INTERROGATION COMMANDS:
ENABLE
Activates brea kpoint and display registers for
use with GO and STEP commands.
DISPLAY
GO
Initiates real-time emulation and allows user to
specify brea kpoints, and data retrieval.
Print contents of memory, MCS-48 device registers, 110 ports, flags, pins, real time trace
data, symbol table, or other diagnostic data on
list device.
STEP
Initiates emulation in single instruction increments. Each step is followed by a register
dump. The user may optionally tailor other diagnostic activity to his needs.
CHANGE
Alter contents of memory, register, output
port, or flag. Set or alter breakpoints and display registers.
MAP
Define memory status.
INTERRUPT
Emulates user system interrupt.
BASE
Establish mode of display for output data.
SUFFIX
Establish mode of display input data.
UTILITY COMMANDS:
LOAD
Fetch user symbol table and object code from
input device.
LIST
Define list device.
EXIT
Return program control to ISIS II.
SAVE
Send user symbol table and object code to output device.
EVALUATE
Convert expression to equivalent values in
binary, octal, decimal, and hex.
DEFINE
Enter symbol name and value to user symbol
table.
REMOVE
Delete symbols from symbol table.
RESET
Reinitialize ICE-48 program variables.
MOVE
Move block of memory data to another area of
memory.
13-52
ICE-48™ MODULE
SPECIFICATIONS
ICE-48 OPERATING ENVIRONMENT
PHYSICAL CHARACTERISTICS
Diskette-Based ICE-4B Software
Required Hardware:
IntelleC® Microcomputer Development System
System Console
Intellec Diskette Operating System
ICE-48 Module
Required Software:
System Monitor
ISIS-II
Width:
Height:
Depth:
Weight:
DC Power:
±5V. ±5%
Vee
lOA maximum; 7.0A typical
Icc
+12V. ±5%
VOO
79 mA maximum; 45 mA typical
100
-10V
VBB
20mA
IBB
EQUIPMENT SUPPLIED
ENVIRONMENTAL CHARACTERISTICS
SYSTEM CLOCK
Crystal controlled 6.0 MHz internal, 3.0 MHz internal or
user supplied TTL external: software selectable.
ORDERING INFORMATION
Description
MDS-48-ICE
8048 CPU In-Circuit Emulator, Cable Assembly and Interactive Diskette Software
included
in. (30.48 cm)
in. (17.15 em)
in. (1.27 cm)
lb. (3.64 kg)
ELECTRICAL CHARACTERISTICS
Printed Circuit Boards
Interface Cables and Buffer Module
Operator's Manual
Schematic Diagram
ICE-48 Software, diskette-based version
Part Number
12.00
6.75
0.50
B.OO
13-53
Operating Temperature:
Operating Humidity:
OOC to 40°C
Up to 95% relative humidity
without condensation
intel®
MICROCOMPUTER DEVELOPMENT SYSTEMS
MDS-EM1
8021 EMULATION BOARD
EPROM functional equivalent of 8021 component 8-bit microcomputer
single
Connects to prototype system through 8021 pin
compatible plug
Based on 8748 - user programmable/erasable
EPROM 8-bit computer
On-card 3.0 MHz or external TTL driven clock
Operates with ICE-48™ to provide full in-circuit
debugging of 8021 prototype system
Portable 4" X 7" microcomputer circuit assembly
The MOs.-EM1 emulator board is a ready-ta-use 4" X 7" microcomputer circuit assembly that emulates the Intel 8021 microcomputer. A 12-inch flat-cable assembly connects the board to the 8021 socket in a prototype system. The board is designed
so that it can be mounted either as a stand:alone unit, or within the prototype assembly.
The 8021 microcomputer has 1K X 8 mask-programmable ROM program memory and 64 by 8 RAM data memory. The
MOs.-EM1 is controlled by an Intel 8748, with 1K of EPROM program memory and a 64 byte data memory. The EPROM can
be programmed and erased repeatedly during hardware and software development. The MOS-EM1 has several ancillary circuits
that perform the following functions which are specific to the 8021:
Zero crossing detector
Crystal controlled clock/buffer
Port 0 simulator
For prototype debugging, the 8748 can be removed from its socket and replaced with a cable to an INTEL ICE-48. When
used with the MOS-EM1. ICE-48 emulates the 8021 in real-time, or single-steps the 8021 program at the user's command.
A full range of capabilities for examining and modifying 8021 memory and status are supplied through ICE-48.
13-54
MDS-EM1
ZERO CROSS DETECTION SIMULATOR
HARDWARE
The zero cross detection simulator enables the 8748's T1 input to
The MDS-EM1 emulation board uses the 8748 to perform the
emulation.
detect zero-crossings. The circuitry provides a high level signal on
a positive crossing and a low level signal on a negative crossing of
zero to the T1 input of the 8748.
P0 SIMULATOR
RESET BUFFER
Port 0 of the 8021 is a quasi*~bidirectional port. The P0 simulator
converts the data bus of the 8748 into a quasi~bidirectional port.
The 8021 resets on a logic HIGH level signal. However. the 8748
resets on a logic LOW level, thus an inverter is provided on the
CRYSTAL CONTROL CLOCK BUFFER
MDS-EM1 to make the two chips compatible.
The MDS-EM1 allows user to select an on-board oscillator or a TTL
clock driven from the 8021 user's prototype system via a Cambian
Suitcase jumper.
Jumper
Position
State
W1
A-B
C- D
On-Board
External
TTL Clock
OPTIONAL PULL-UPS
Resistors are provided to simulate the optional pull·up resistors on
T1 input and Port 0 of the 8021. A removable resistor pack is used
on Port 0. The T1 input pull up can be installed by soldering in a
50K resistor.
SOFTWARE
*A bidirectional port which serves as an input port, output port,
or both even though outputs are statically latched.
When emulating the 8021 with MDS·EM1, the user must observe the
8021 instruction set.
r---,
I OPTIONAL I
LPULL-UP
-
DB0
]sl:3~~:OR K
DB7
...J
P00 - P07
~
~
P10 - P17
P20 - P28
40
LINES
~
V
ALE
8748
8021
CABLE
PLUG
DR
40-PIN
PLUG
PROG
h--1
ICE-48
T1
RESET
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CRYSTAL
C~~~~~L
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XTAL 1
I DCE~~~~~O~ I
FLAT CAB LE
I
ISIMULATORS I
T1
I
RESET
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RESET BUFFER
ro'NClA'Ro""
I CLOCK I
L- ~TI~-.J
MDS-EM1 FUNCTION
DIAGRAM
13-55
~
28
LINES
I
28·PIN
SOCKET
MDS-EM1
SPECI FICATIONS
SYSTEM CLOCK
Crystal controlled 3.0 MHz on board or user supplied TTL external
OPERATING ENVIRONMENT
clock: hardware jumper selectable.
Stand-Alone
PHYSICAL CHARACTERISTICS
Required Hardware:
Width:
Height:
Depth:
Weight:
MDS-EM1 emulation board
In-Circuit Emulation
Required Hardware:
MDS-EM1 emulation board
InteUee
Microcomputer
Development
7.0 in. 117.78 cml
4.0 in. 110.16 cml
0.75 in. 11.91 cml
<1.0 Ibs. 10.45 kgl
ELECTRICAL CHARACTERISTICS
System
configurated
to support ICE-48
DC Power:
V CC 5V ± 5%
ICC 300 rnA Imax.1
EQUIPMENT SUPPLIED
MDS-EM1 printed circuit board
ENVIRONMENTAL CHARACTERISTICS
12" long flat cable terminating in 28-pin plug, pin compatible
with 8021
Operating Temperature: 0 - 55°C
MDS-EM1 Operator's Manual
sation
ORDERING INFORMATION
Part Number
Description
MDS-EM1
8021 Emulation Board
13-56
Operating Humidity: up to 95% relative humidity without conden-
MICROCOMPUTER DEVELOPMENT SYSTEMS
ICE-80™
8080 IN-CIRCUIT EMULATOR
Connects Intellec® System to user configured system via an external cable and 40-pin plug, replacing
the user 8080
Offers full symbolic debugging capabilities
Allows real-time (2 MHz) emulation of the user
system 8080
Provides address, data and 8080 status information
on last 44 machine cycles emulated
Allows user configured system to share Intellec
RAM, ROM and PROM memory and Intellec I/O
facilities
Provides capability to examine and alter CPU registers, main memory, pin and flag values
Checks for up to three hardware and four software
break conditions
Eliminates the need for extraneous debugging tools
residing in the user system
Integrates hardware and software development
efforts
Available in diskette or paper tape versions
The Intellec In-Circuit Emulator/80 (ICE-80) is an Intellec resident module that interfaces to any user configured 8080 system. With ICE·80 as a replacement for a prototype system 8080, the designer can emulate the system's 8080 in real time,
single·step the system's program, and substitute Intellec memory and I/O for user system equivalents. Powerful Intellec debug
functions are extended into the user system. For the first time the designer may examine and modify his system with symbolic references instead of absolute values.
13·57
MODULE
INTEGRATED HARDWARE/
MEMORY AND
I/O MAPPING
SOFTWARE DEVELOPMENT
Memory and I/O for the user system can be resident in the
user system or "borrowed" from the Intellec System
through ICE·80's mapping capability.
The user prototype need consist of no more than an 8080
CPU socket and a user bus to begin integration of soft·
ware and hardware development efforts. Through ICE·80
mapping capabilities, system resources can be accessed
tor missing prototype hardware. Hardware designs can be
tested using the system software which will drive the final
product.
ICE-80 separates user memory into 16 4K blocks. User
I/O is divided into 16 16·port blocks. Each block of memory or I/O can be defined independently. The user may
assign system equivalents to take the place of devices not
yet designed for the user system during prototyping. In
addition, memory or I/O can be accessed in place of
suspect user system devices during prototype or produc·
tion checkout.
The system integration phase, which can be so costly and
frustrating when attempting to mesh completed hardware
and software products, becomes a convenient two·way
debug tool when begun early in the design cycle.
The user can also designate a block of memory or I/O as
nonexistent. ICE·80 issues error messages when memory
or I/O designated as nonexisting is accessed by the user
program.
SYMBOLIC DEBUGGING
ICE·80 allows the user to make symbolic references to
memory addresses and data in his program. Symbols may
be substituted for numeric values in any of the ICE·80
commands. The user is relieved from looking up addresses
of variables or program ~ubroutines.
The user symbol table generated along with the object file
during a PLiM compilation or a MAC80 or resident
assembly, is loaded to memory along with the user pro·
gram which is to be emulated. The user may add to
this symbol table any additional symbolic values for
memory addresses, constants, or variables that are found
useful during system debugging. By referring to symbolic
memory addresses, the user can be assured of examining,
changing, or breaking at the intenrlerl loratiQ~.
ICE·80 provides symbolic definition of all 8080 registers,
flags, and selected pins. The following symbolic references
are also provided for user convenience: TIMER, a 16·bit
register containing the number of ¢2 clock pulses elapsed
during emulation; ADDRESS, the address of the last
instruction emulated; INTERRUPTENABLED, the user
8080 interrupt mechanism status; and UPPER LIMIT, the
highest RAM address that can be occupied by user memory.
ICE-SO INSTALLED IN USER SYSTEM
REAL TIME TRACE
DEBUG CAPABILITY
INSIDE USER SYSTEM
ICE·80 captures valuable trace information while the user
is executing programs in real time. The 8080 status, the
user memory or port addressed, and the data read or
written (snap data), is stored for the last 44 machine
cycles executed. This provides ample data for determining
how the user system was reacting prior to emulation
break. It is available whether the break was user initiated
or the result of an error condition.
ICE·80 provides the user with the ability to debug a full
prototype or production system without introducing
extraneous hardware or software test tools.
ICE·80 connects to the user system through the socket
provided for the user 8080 in the user system. Intellec
memory is used for the execution of the ICE-80 soft·
ware, while I/O provides the user with the ability to
communicate with ICE·80 and receive information on the
operation of the user system.
For. detailed information on the actions of CPU registers,
flags, or other system operations, the user may operate in
single or multiple·step sequences tailored to system debug
needs.
13·58
ICE-80™ MODULE
HARDWARE
MHz. The CPU can alternately be driven by a clock de·
rived from user system signal lines. The clock source is
selected by a jumper option on the board. A timer on the
Trace Board counts the ¢2 clock pulses during emulation
and can provide the user with the exact timing of the
emulation.
The heart of ICE-80 is a microcomptuer system utilizing
Intel's 8080 microprocessor as its nucleus. This system
communicates with the Intellec® host processor via I/O
commands. Host processor commands and ICE-80 status
are interchanged through registers on the ICE-80 Trace
Board. ICE-80 and the system also communicate through
a Control Block resident in the Intellec® main memory
which contains detailed configuration and status infor·
mation transmitted at an emulation break.
The Processor Board turns on an emulation when ICE-80
has received a RUN command from the system. It termi·
nates emulation when a break condition is detected on the
Trace Board, or the user's program attempts to access
memory or I/O ports designated as nonexistent in the user
system, or the user 8080 is inactive for a quarter of a
second.
ICE-80 hardware consists of two PC boards, the Processor
and Trace Boards, residing in the I ntellec® chassis, and a
6-foot cable which interfaces to the user system. The
Trace and Processor Boards communicate with the system
on the bus, and also with each other on a separate ICE-80
bus. ICE-80 connects to the user system through a cable
that plugs directly into the socket provided for the user's
8080.
The Address Map located on the Processor Board stores
the assigned location of each user memory or I/O block.
During emulation the Processor Board determines whether
to send/receive information on the I ntellec or User bus by
consulting the Address Map. The Processor Board allows
the ICE-80 CPU to gain access to the bus as a master to
"borrow" Intellec facilities. At an emulation break, the
Processor Board stores the status of specified 8080 input
and output signals, disables all interaction with the user
bus, and commands the Trace Board to send stored infor·
mation to a Control Block in Intellec memory for access
during interrogation mode.
TRACE BOARD
The Trace Board talks to the system as a peripheral
device. It receives commands to ICE-80 and returns
ICE-80 responses.
While ICE-80 is executing the user program, the Trace
Board collects data for each machine cycle emulated (snap
data). The information is continuously stored in high·
speed bipolar memory.
The Trace Board also contains two 24-bit hardware break·
point registers which can be loaded by the user. While in
emulation mode, a hardware comparitor is constantly
monitoring address and status lines for a match which will
terminate an emulation. A user probe is also available
which can be attached to any user signal. When this signal
goes true a break condition is recognized.
CABLE CARD
The Cable Card is included for cable driving. It transmits
address and data bus information to the user system
through a 40·pin connector which plugs into the user sys·
tem in the socket designed for the 8080 when enabled by
the Processor Module's user bus control logic.
The Trace Board signals the Processor Board when a com·
mand to ICE-80 or break condition has been detected.
The ICE-80 CPU then sends data stored on the Trace
Board to the Control Block in memory. Snap data, along
with information on 8080 registers and pin status, and
the reason for the emulation break are then available for
access during interrogation mode. Error conditions, if
present, are transmitted and automatically displayed for
the user.
SOFTWARE
The ICE-80 software driver (ICE80SD) is a RAM·based
program which provides the user with easy·to·use English
language commands for defining breakpoints, initiating
emulation, and interrogating and altering user system
status recorded during emulation. ICE-80 commands are
configured with a broad range of modifiers which provide
the user with maximum flexibility in describing the
operation to be performed.
ICE80SD is available in both paper tape and diskette·
based versions. The diskette·based version, which is sup·
plied on a System Diskette for operation with the
Intellec Diskette Operating System, provides expanded
capabilities for retrieving and storing user programs, as
well as the standard peripherals available in the paper
tape version.
PROCESSOR BOARD
An 8080 CPU resides on the Processor Board. During
emulation it executes instructions from the user's pro·
gram. At all other times it executes instructions from the
control program in the Trace Module's ROM.
The Processor Board contains an internal Clock Generator
that provides the clocks to the user emulation CPU at 2
13-59
ICE-80™ MODULE
CHANGE
EMULATION COMMANDS:
Initiates real-time emulation and allows
user to specify breakpoints, data retrieval,
and conditions under which emulation
should be reinitiated.
GO
Initiates emulation in single or multiple
instruction increments. User may specify
a register dump or tailor diagnostic activity to his needs following each step, and
define conditions under which stepping
should continue.
Delimits blocks of instructions for which
register dump or tailored diagnostics are
to occur.
STEP
RANGE
CONTINUE
Resume real-time emulation.
CALL
Emulate user system interrupt.
Alter contents of memory, register, output port, or 8080 flag.
XFORM
Define memory and I/O status.
SEARCH
Look through memory range for specified
value.
UTILITY COMMANDS:
INTERROGATION COMMANDS:
LOAD
Fetch user symbol table and object code
from input device.
SAVE
Send user symbol table and object code
to output device.
EQUATE
Enter symbol name and value to user
symbol table.
FILL
Fill memory range with specified value.
BASE
Establ ish mode of display for output
data.
MOVE
Move block of memory data to another
area of memory.
DISPLAY
Print contents of memory, 8080 registers,
input ports, 8080 flags, 8080 pins, snap
data, symbol table, or other diagnostic
data on list device. Can also be used for
base-to-base conversion, or addition or
subtraction in any base.
TIMEOUT
Enable/disable user CPU 1/4 second wait
state timeout.
LIST
Define list device (diskette-based version
only).
EXIT
Return program control to monitor.
16 ADDRESS
8DATAQUT
8 DATA IN
CONTROL
r-----------------l
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L_
_
__
___
_ _ _ _ _ _ ---J
ICE-BO
PROCESSOR
BOARD
ICE·SO TRACE BOARD
CONTROL}
8 DATA BITS
INTELLEC BUS
16 ADDRESS BITS
FUNCTIONAL BLOCK DIAGRAM OF ICE-SO MODULE
13-60
ICE-80™ MODULE
SAMPLE, ICE-SO DEBUG SESSION
PAGE 1
ISIS 8080 MACRO ASSEM8LER, V1.0
, USER PROGRAM TO OUTPUT A SERIES OF
; CHARACTERS TO SDK-80 CONSOLE DEVICE
1320
01 E3
CO
13200601
START
1322 3A3613
13254F
1326 CDE301
1329 79
132A 93
132B 323713
132E FE40
1330 C22513
1333 C32013
13365A
1337
LOOP'
ORG
EOU
1320H
1 E3H
MVI
LOA
MDV
B,l
OATl
C,A
CO
A,C
B
RSL T
40H
LOOP
START
CALL
MOV
SBB
STA
CPI
JNZ
JMP
OAT'
RSLT
0000
DB
OS
END
,SDK-80 CONSOLE OUT DRIVER
,SET UP B VALUE
,LOAD A WITH DAn VALUE
,SEND C VALUE TO CONSOLE
_ RESTORE A
; SUBTRACT B FROM A
,STORE RESULT IN RSLT
, LAST VALUE TO PRINT
,LOOP AGAIN IF A
40H
, ELSE RESTART WHOLE PROCFDURE
5AH
INITIAL ICE-SO SESSION
(Note: The SDK-SO Monitor has already been used to Initial lIe the SDK·SO Boardl
ISIS ICE-aO, Vl.0
XFORM MEMORY 0 TO 1 U
-XFORM 10 OFH U
(?) "LOAD PROG. HEX
ISIS, Vl.0
-ICE80
CD ""
ERR=067
Gl
®
©
STAT-llH TYPE-OSH CMND-07H ADDR-1320H GOOO 06H BAD-04H
"CHANGE MEMORY '321H~ FFH
ERR-067
STAT=11H TYPE=06H CMND-07H ADDR;-1321H GOOD=-FFH 8AO~FDH
"LOAD PROG_ HEX
"GO FROM START UNTIL RSLTWRITTEN
EMULATION BEGUN
ERR-OS7
STAT=11H TYPE=07H CMND,;,02H
"DISPLAY CYCLES 5
STAT~A2H ADDR-1326H DATA- CDH
STAT-82H ADDR--1327H OATA--E3H
®
C1J
STAT-82H ADDR-1328H DATA01H
STAT-04H ADDR-FFFFH DATA-13H
STAT-04H ADDR-FFFEH DATA-29H
"CHANGE DOUBLE REGISTER SP-13FFH
-BASE HEX
"EOUATE STOP-1333H
"GO FROM START UNTIL STOP EXECUTED THEN DUMP
EMULATION BEGUN
B=OlH C"'-41H D=QOH E~-'OOH H=QOH L",QOH F=56H A=4QH P-'=1320H *=1333H S=13FFH
®
EMULATION TERMINATED AT 1333H
"EXIT
'FFFF
1.
In block 1 (1000H-1FFFH) of user memory, and requires access to the
SDK-BO monitor (block 0) and 1/0 ports in block OFH. Both ports and memory are defined as available to the user system. All other
memory and 110 is initialized by ICE-BO as nonexistent (guarded).
2.
A load command generates an error. The type and command numbers indicate that a data mismatch occurred on a write to memory command. The data to be written to address 1320H should have been 06H. When ICE-SO read the data after wrtting It, a 04H was detected.
A change command to a different memory address hints that bit 1 does not go to 1 anywhere in this memory block. Examination indi·
cates that a pin was shorted on the R AM located at 1300H -13 F F H In the prototype system. The problem IS fixed and a subsequent
load succeeds.
3.
A real-time emulation IS begun. The program is executed FROM 'START' (1320H) and continues UNTIL 'RSLT' is written (In location
1328H, the contents of the accumulator is stored In (written Into) 'RSL T'l.
Set up user memory and 1/0. The program is set up to execute
4.
An error condition results: TYPE 07, CMND 02 indicate the program accessed a guarded area.
5.
The last 5 machine cycles executed are displayed. The last instruction executed was a call (CDH). The fourth and fifth cycles are a push
operation (designated by status 04H) to store the program counter before executing the call. The stack pOinter was not initialized in the
program and is accessing memory location FFFFH.
6.
After making a note to initialize the stack pointer in the next assembly, a temporary fix is effected by setting the stack pointer to the top
of user available memory.
7.
After setting the base for displays to hex and adding the symbol 'STOP' to the symbol table, emulation is started which will terminate
when the instruction at 1333H ('STOP') is executed. When emulation terminates, a DUMP of the contents of user 8080 registers is
requested. One can see that the value of the accumulator is set at 40H, the stack pointer is set at 13FFH, the last address executed (*) is
1333H. and the program counter has been set to 1320H.
8.
EXIT returns control to the MDS monitor.
13-61
I
ICE-80 ™ MODULE
ICE80SD OPERATING ENVIRONMENT
SYSTEM CLOCK
Crystal controlled 2.185 MHz ±0.01 %. May be replaced
by user clock through jumper selection.
Paper Tape-Based ICE80SD
Required Hardware:
I ntellec® System
System console
Reader device
Punch device
ICE-80
Required Software:
System monitor
PHYSICAL CHARACTERISTICS
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
0.50 in. (1.27 em)
Depth:
Weight: 8.00 Ib (3.64 kg)
ELECTRICAL CHARACTERISTICS
DC Power:
Diskette-Based ICE80SD
Required Hardware:
Intellec@ System
32K bytes RAM memory
System console
ISIS MOS Floppy Disk Drive
ICE-80
Required Software:
System monitor
ISIS Diskette Operating System
Vee
Icc
Voo
100
Vss
Iss
ENVIRONMENTAL CHARACTERISTICS
Operating Temperature: O°C to 40°C
Operating Humidity:
Up to 95% relative humidity
without condensation
EQUIPMENT SUPPLIED
CONNECTORS
Printed Circuit Modules (2)
Interface Cables and Buffer Board
Hardware Reference Manual
Operator's Manual
Schematic Diagram
ICE-80 Software Driver, paper tape version
(ICE-80 Software Driver, disketted-based version is
supplied with Diskette Operating System)
Edge C-:Jnnector: CDC VPB01 E32AOOA 1
ORDERING INFORMATION
Part Number
Description
MDS-80-ICE
8080 CPU In-Circuit Emulator, cable assemb!',' and [r.tcract:vc :;cftir'Vai6 included.
+5V,±5%
9.81 A maximum; 6.90A typical
+12V,±5%
79 mA maximum; 45 mA typical
-9V, ±5%
1 mA maximum; 1 I1A typical
I.~
,
13-62
MICROCOMPUTER DEVELOPMENT SYSTEMS
ICE-85™
MCS-85™ IN-CIRCUIT EMULATOR
Connects the Intellec® System Resources to the
user-configured system via a 40-pin adaptor plug
Displays trace data from the user's SOS5 in assembler mnemonics and allows personality groupings
of data sampled by the external 1S-channel trace
module
Executes user system software in real-time
Allows user-configured system to share Intellec®
memory and I/O facilities
Extends ICE capabilities to the rest of the prototype system peripheral circuitry by allowing the
user to execute his own peripheral chip analysis
routines
Provides 1023 states of SOS5 trace data plus 1S
additional logic signals via an External Trace Module
Offers full symbolic debugging capability for both
assembly language and Intel's high-level compiler
language, PL!M-SO
Provides ability to examine and alter MCS-S5™
registers, memory, flag values, interrupt bits and
I/O ports
The ICE-85 module resides in the Intellec® Microcomputer Development System and interfaces to the user system's 8085. In
addition, an external trace module provides access to user system peripheral circuitry via a user-configured DIP clip for peripheral ICs or may be attached to as many as 18 separate prototype signal nodes via individual probe clips. Using the ICE-85
module, the designer can execute prototype software in real-time or single-step mode and can substitute Intellec® system
memory and I/O for user system equivalent. ICE capability can be extended to the rest of the user system peripheral circuitry
by allowing the user to create and execute a library of user-defined peripheral chip analyzer routines. All user access to the
prototype system software may be done symbolically by assigning names to program locations and data, I/O ports and groups
of external trace signals. For the first time, in-circuit emulation extends beyond the user's prototype CPU to the entire user's
system, allowing In-System Emulation.
13·63
MCS-85™ IN-CIRCUIT EMULATOR
SYMBOLIC DEBUGGING CAPABILITY
ICE-85 allows the user to make symbolic references to I/O
ports, memory addresses and data in his program_ Symbols
and PL/M statement number may be substituted for numeric values in any of the ICE-85 commands. The user is relieved from looking up addresses of variables or program
subroutines.
The user symbol table generated along with the object file
during a PL/M-80 compilation or by the ISIS-II 8080/8085
Macro Assembler is loaded into the Intellec® System memory along with the user program which is to be emulated.
The user may add to this symbol table any additional
symbolic values for memory addresses, constants, or variables that are found useful during system debugging. By
referring to symbol memory addresses, the user can examine, change or break at the intended location.
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
The user prototype need consist of no more than an 8085
CPU socket and a user bus to begin integration of software
and hardware development efforts. Through ICE-85 mapping capabilities, Intellec® System equivalents can be
accessed for missing prototype hardware. Hardware designs
can be tested using the system software which will drive the
final product.
The system integration phase, which can be so costly when
attempting to mesh completed hardware and software
products, becomes a convenient two-way debug tool when
begun early in the design cycle.
ICE-85 provides symbolic definition of all 8085 registers,
interrupt bits and flags. The following symbolic references
are also provided for user convenience: TIMER, the loworder 16 bits of a register containing the number of 2 MHz
clock pulses elapsed during emulation; HTIMER, the highorder 16 bits of the timer counter; PPC, the address of the
last instruction emulated; BUFFERSIZE, the number of
frames of valid trace data (between 0 and 1022).
PERSONALITY GROUPED DISPLAYS
Trace data in the 1023 by 42-channel real-time trace memory buffer is displayed in easy to read format. The user has
the option to specify trace data displays in actual 8085
assembler instruction mnemonics. The data collected from
the External Trace Module can be grouped and symbolically named according to user specifications and displayed in
the appropriate number base designation. Simple ICE-85
commands allow the user to select any portion of the 42Kbit trace buffer for immediate display.
TYPICAL ICE INTERROGATION AND
UTILITY COMMANDS
MEMORY AND I/O MAPPING
Memory and I/O for the user system can be resident in the
user system or "borrowed" from the Intellec® System
through ICE-85's mapping capability.
I
ICE-85 separates user memory into 32 2K blocks. Each
block of memory can be defined independently. The user
may assign Intellec® System equivalents to take the place
of devices not yet designed for the user system during prototyping. In addition; Intellec® System memory or I/O can
be accessed in place of suspect user system devices during
prototyping or production checkout.
The user can also designate a block of memory or I/O as
nonexistent. ICE-85 issues error messages when memory
or I/O designated as nonexistent is accessed by the user
program.
DISPLAY/
CHANGE
Display/Changes the vaiues of symbols and
the contents of 8085 registers, pseudoregisters, status flags, interrupt bits, I/O ports
and me(Tlory.
EVALUATE
Displays the value of an expression in the
binary, octal, decimal or hexadecimal.
SEARCH
Searches user memory between locations in a
user program for specified contents.
CALL
Emulates a procedure starting at a specified
ICALL
Executes a user-supplied procedure starting at
memory address in user memory.
a specified memory address in the Intellec®
System memory.
EXECUTE
13-64
Saves emulated program registers and emulates a user-supplied subroutine to access
peripheral chips in the user's system.
MCS-85™ IN-CIRCUIT EMULATOR
REAL TIME TRACE
EXTERNAL TRACE MODULE
ICE-85 captures valuable trace information from the emulating CPU and the External Trace Module while the user is
executing programs in real time. The 8085 status, the user
memory or port addressed, the data read or written, the
serial data lines and data from 18 external signals, is stored
for the last 1023 machine states executed (511 machine
cycles). This provides ample data for determining how the
user system was reacting prior to emulation break. It is
available whether the break was user-initiated or the result
of an error condition.
TTL level signals from 18 points in the user system may be
synchronously sampled by the External Trace Module and
collected in ICE-85's trace buffer. The signals can be collected from a single peripheral chip via the supplied 40-pin
DIP clip or may be placed by the user on up to 18 separate
signal nodes using the supplied 18 individual probe clips.
These signals are included in the 42-channel breakpoint
comparisons and clock qualifiers. Also, data from these
18 channels may be displayed in each to read, user-defined
groupings.
For detailed information on the actions of CPU registers,
flags, or other system operations, the user may operate in
single or multi-step sequences tailored to system debug
needs.
SYNCHRONOUS OPERATION WITH OTHER DESIGN
AIDS
ICE-85 can be synchronized with other Intellec® design
aids by means of two external synchronization lines. These
lines are used to enable and disable ICE-85 trace data
collection and to cause break conditions based on an
external signal which may not be included in the ICE-85
breakpoint registers. In addition, ICE-85 can generate signals on these lines which may be used to control other
design aids.
BREAK REGISTERS/TRACE MEMORY
EMULATION CONTROLS AND COMMANDS
GROUP
Defines into a symbolically named group, a
channel or combination of channels from the
8085 Microcprocessor and/or the External
Trace Module.
GO
Initiates real-time emulation and controls
emulation break conditions.
STEP
Initiates emulation in single instruction steps.
User may specify the type and amount of
information displayed following each step,
and define conditions under which stepping
should continue.
PRINT
Prints the user-specified portion of the trace
memory to the selected Iist device.
ICE-85 has two breakpoint registers which are used to
break emulation, and two trace qualifier registers which are
used to control the collection of trace data during emulation. Each register is 42 entries wide, one entry. for each
channel and each entry can take anyone of the three values
0, 1 or "don't care".
The trace buffer, also 42 entries wide, collects data sampled
from 24 8085 processor channels and 18 external channels
sampled by the External Trace Module. The signals collected from the 8085 include address lines, data lines, status
lines and serial input and output lines. The 18 channels
extending from the External Trace Module synchronously
sample and collect into the trace buffer any user-specified
TTL compatible signal from the rest of the prototype
system. "Break" and "trace qualification" may therefore
occur as a result of a match of any combination of up to 42
channels of CPU and external circuitry signals.
13-65
MCS-85™ IN-CIRCUIT EMULATOR
SPECIFICATIONS
ICE·B5 OPERATING ENVIRONMENT
PHYSICAL CHARACTERISTICS
Diskette·Based ICE·85 Software
Printed Circuit Boards:
12.00 in.
Width:
Height:
6.75 in.
0.50 in.
Depth:
Packaged Weight:
6.001b
Required Hardware:
Intellec® Microcomputer Development System
System Console
Intellec®·Diskette Operating System
ICE·85 Module
Required Software:
System Monitor
ISIS·II
(30.48 cm)
(17.15cm)
(1.27 cm)
(2.73 kg)
ELECTRICAL CHARACTERISTICS
DC Power:
Vcc = +5V ±5%
Icc = 12A maximum; lOA typical
Voo = +12V ±5%
100
80 mA maximum; 60 mA typical
VBB
-10V ±5%
IBB
30 mA maximum; 10 JLA typical
EQUIPMENT SUPPLIED
18·Channel External Trace Module
Printed Circuit Boards (2)
Interface Cable and Emulation Buffer Module
Operator's Manual
ICE·85 Software, Diskette·Based Version
ENVIRONMENTAL CHARACTERISTICS
EMULATION CLOCK
Operating Temperature: 0° to 40°C
Operating Humidity:
Up to 95% relative humidity with·
out condensation.
User's system clock or ICE·85 adaptor socket
(6.144 MHz Crystal)
,--------------------------------.----"'''''---.
Ice.a& CONTROL BOARD
L _________ _
I
,-----
,---------I
SYNCD
I
'--_--,..-_--IDA!A
I
I
I
CHIP DATA I
I,
I
I
CONTROL
ADDRESS
TRACE DATA
J~1
TO USER.S
SOCKET
t
I
TIMe CLOCK
L _____________ - ___ _
I
I
FORCE TRACE
ICE-i5 TRACE BOARD
I
t=~~==~~=========1==~~~==~====~--_1oSYNCl
_
L ____________________
r----------,-Jt--------i
~
~
8085 CHIP CONTROll.ER
SIGNAL BUFFERS'
18 USER TRACE
I __________ -'~PROBES
L
18 EXTERNAL TRACE BUFFER
ICE·a5 BLOCK DIAGRAM
ORDERING INFORMATION
Part Number
Description
MDS·85·ICE
8085 CPU In·Circuit Emulator and
18·Channel External Trace Module
13·66
MICROCOMPUTER DEVELOPMENT SYSTEMS
INSITE™
USER'S PROGRAM LIBRARY
• Programs for 8008, 8080, 8085 and 8048 Processors
• Updates of new programs sent every other
month
• Diskette, Paper Tapes, and Listings available for
Library programs
• Hundreds of programs
• For each accepted program submittal, Insite will
provide either a one year free membership, five
free paper tapes or free program diskette_
• 4004/4040 Library also available
Insite ™ , Intel's Software Index and Technology Exchange, is a collection of programs, subroutines, procedures and macros
written by users of Intel's 8008, 8080, 8085, and 8048 microcomputers, SBe 80 OEM computer systems, and Intellec®
development systems. Thanks to customer contributions to Insite TM, Intel is able to make these programs available to all
users of Intel microcomputers. By taking advantage of the availability of these general-purpose routines, the microcomputer
design engineer and programmer can save many hours of programming and debugging time. The library df programs also serves
as a good learning tool for those unfamiliar with Intel assembly language or PL/M, Intel's high-level language for the 8008,
8080, and 8085 microcomputers.
LIBRARY PROGRAMS AVAILABLE ON PAPER TAPE AND DISKETTE
13-67
INSITE™ USER'S PROGRAM LIBRARY
INSITETM PROGRAM LIBRARY MANUAL
PROGRAM SUBMITTAL (Conti
Each member will be sent the Program Library Manual
which is a collection of source listings of library programs
three pages and under. Longer programs are represented by
an abstract which indicates the function of the routine,
required hardware and software, and memory requirements.
2. A source listing of the program must be included. This
must be the output listing of a compile or assembly.
All accepted programs should assemble or compile
correctly with no syntax errors. No consideration will
be given to partial programs or duplication of existing
programs.
User's Library members will be updated regularly with new
programs submitted to Insite TM during the subscription
period. Please refer to the Intel OEM Price List for yearly
subscription fee.
PROGRAM LIBRARY SERVICES
PAPER TAPES AND LISTINGS are available for programs
in InsiteTM. A handling fee will be charged for each paper
tape and listing. Ordering information can be found in the
Program Library Manual.
DISKETTE - Source of most User's Library programs are
available on system diskettes. A three program minimum is
required on all diskette orders, with the exception of Section 9.
4004/4040 PROGRAM LIBRARY MANUAL
4004/4040 User's Library members will be sent the 4004/
4040 program library manual. Updates will be issued as
new programs are contributed. Paper tapes and diskette are
not available for 4004/4040 programs. Please refer to the
Intel OEM Price List for yearly subscription fee.
Programs submitted for our review must follow the guide·
lines listed below:
C.
b. Program title: Name or brief description of program
function.
c. Function: Detailed description of operations performed by the program. Attach additional pages if
necessary.
e. Required software:
For
eXa('n~ie:
TTY Driver
Floating Point Package
Support software required for cross
products
g. Output results: Values to be e~pected in registers,
memory areas or on output ports.
1. Programs must be written in a stimdard I ntel Assembly
Language or PL/M. These languages are documented in
.
the following manuals:
h. Program details: (for resident products only)
(1)
(2)
(3)
(4)
#98·019B
Programming
a. Processor (check appropriate box).
f. Input parameters: Description of register values,
memory areas or values accepted from input ports.
PROGRAM SUBMITTAL
Language
Complete the Submittal Form as follows: (please type or
print)
For example: TTY or Port 0 and 1
Interrupt Circuitry
I/O Interface
Machine line and configuration for
cross products
Membership in Insite™ is available on an annu'al basis.
Users may become a member through program contribu·
tion or membership fee. New members should use the memo
bership form on the back of this data sheet.
b. 8080 Assembly
#98-004C
4. A source paper tape or diskette of the contributed program is required. This will be used.for the reproduction
of tapes for other members.
d. Required hardware:
MEMBERSHIP
a. 8008 Assembly' Programming Manual
3. A test program which assures the val idity of the contributed program must be included. This must show
the correct operation of the program.
Manual
4004/4040 Assembly Language Programming Manual
#98-025A
Register modified
RAM required (bytes)
ROM required (bytes)
Maximum subroutine nesting level
i. Assembler/Compiler used:
For example: PL/M
I ntellec MDS'Macro Assembler
IBM 370 Fortran IV
d. 8008/8080 PL/M Programming Manual #98-108A
e. PL!M·80 Programming Manual #98-268
f. MCS-48 Assembly Language Manual #98-255
j. Programmer company and address.
13-68
INSITE™ USER'S LIBRARY PARTIAL PROGRAM INDEX
3-Byte Positive Fractional Multiply
8-Bit Multiply and Divide
8-Bit Random Number Generator
12 x 12 Multiply
16-8it 2'5 Complement Signed Multiplication
16-Bit CRe for Polynomial X16+12+XS+l
16-8it Division - 16-Bit Result
16-8it Division - 16-Bit Result
16-Bit Multiply - 16-Bit Result
16-Bit Multiply - 16-bit Result
16-Bit Multiply - 32-8it Result
16-Bit Random Number Generator
16-Bit Square Root Routine
32-8it Binary to BCD Conversion, Leading
Zero Blanking
32-8it Divide Subroutine
4040 Cross Assembler for Intel lee S/MOD
SO and MDS·SOO
2708 PROM Programmer for Intellee 8/
MOD 80
8080 Cross Assembler for' ntel 8080/8085
Microprocessors
8008 Cross Inverse Assembler for HP 2100
8008 Disassembler
8008 MACRO Definition Set for Assembly
on PDP-11
8008 MACRO Assembler Version 2.0
8080 MACAO Assembler 4.1
8080 CPU Exercise Routine
8080 Cross Assembler for Tektronics 4051
8080 Double Precision ARC Tangent
8080 Disassembler
8080 Disassembler
8080 Floating Point Extended Math Package
8080 Floating Point Package with BCD Conversion Routine
8080 Idle Analyzer for Approximating CPU
Utilization
8080 I/O System Status Display
8080 Least Squares Quadratic Fitting Routine
8080 RAM Memory Test
8080 Symbol Table Dump
9600 Initialize CRT and Uart for Baud
ADCCP Remainder Routine
A/D Converter Routine
Adaptive Game Program
Algebraic Compare Subroutine
APL Graphic Display on a 5 X 7 Dot Matrix
Approximating Routine
Arctan 2 Subroutine
ASCII Display
Absorbance Calculation
ASCII to EBCDIC and EBCDIC to ASCII
Converters
Assembler Oriented Centronics 306 Une
Printer Handler and Error Only Assembler
Bandit Static Display
Banner Print and Punch
BASIC CPU State Vector Maintenance
Basic Digital Panel Meter Call
BASIC Interpreter
BASIC/M Translator and Interpreter
BCD to BIN Conversion Routine
BCD to/from Binary Conversion
BCD Input and Direct Conversion to Binary
Routine
BCD Multiplication
BCD Sum for 8008
BCD Up/Down Counter
BIN to BCD Conversion Routine
Binary to BCD Subroutine
Binary to HEX Routine
Binary Loader for MDS
Binary Multiplication - 24-Bit
Binary Search
Binary Search Routine
Binary Tape Program
BINDECBIN - Binary to/from BCD
BI N LB - 8080 System Loader
Blackjack
$BLPT
BOOT - Bootstrap Loading and Program
Patching
Calendar Subroutine
Character Interpreted Memory Dump
Clock Subroutine
Compare
Compare Object Code Tape with Memory
Control Data Output
Conversion of Scientific to Easily Readable
Notation
CRECH - Cyclic Redundancy Check
Cross Assembler ASM08
Cross Assembler for PDP-11
Cross Assembler for PDP-11
Cross Assembler for NOVA 1200
Cross Assembler for Nova 1220, IBM 360/
40 and CDC 3000
Cross Assembler for Varian Data Machine
Cross Reference for PAS80 PASCA L Programs - XREF80
CATBZ - GET
Cyclic Redundancy Character Generator
Cyclic Redundancy Check
Cycl ic Redundancy Check for Data String
of 2 16 Bytes
Data Array Move
Data General to Intellec MDS Diskette
Transport Package
Data I/O PROM Processor
Decrement Hand L Registers
Delete Comments
Diagnostic 1003 - Memory Validity Check
Digital to Analog Conversion for Eight Outputs
Disable Hold - Screen Mode
Disassembler
Disk Dump Routine for ICOM F 005-11/
MOD 80 Floppy DOS
Double Precision Integer Arithmetic Package
Double Precision Multiply
Driver for Tektronix 4010 Grafic Screen
Elementary F unction Package
Enable Hold - Screen Mode
EALIST
Examin
Factorial of a Decimal Number
Fast Floating Point Square Root Routine
Fixed and Floating Point Arithmetic Routines
Fixed Point CHEBYSHEV Sine and Cosine
for PL/M Users
Flag Processing Routine
Floating Point Decimal and HEX Format
Conversion
Floating Point Format Conversion Package
Floating Point Interpreter
Floating Point Math Package
Floating Point Package for Intel 8008 and
8080 Microprocessors
Floating Point Procedures
Floating Point Square Root
Fly Reader Driver
Format
Format Intel Data
Gambol
Game of Life
Generalized Stepper Motor Drive Program
GLANCE
Gray to Binary Conversion
Handler for Tally PTP
HEX Convert - Convert Intel HEX to Prolog HEX File Converter
HEX to Decimal Conversion
HEX Format Paper Tape Dump for SDK
HEX Tape Loader for SDK
High Speed Paper Tape Reader with Stepper
Motor Control
Histogram
IBM Selectric Output Program
I CE-80 Disassembler
I-Command Insert Data in HEX Form
from TTY into RAM
Input/Output Commands for MDS
Intellec 8/MOD 80 Monitor
Intellec 8/MOD 80 - Silent 700 Interface
Intellec MDS Diagnostic Confidence Test
Version 1.0
13·69
Intellec MDS Monitor Version 2.0
I ntellec 8 Text Editor
I nterfacing the MDS and HP 2644
Interrupt Driven Clock Routine
I nterrupt Handler (Re-Entrant)
I nterrupt Service Routine
INVERT Data in RAM
I/O Routine for TI Silent 700 Terminal
I/O Simulation MACROS
Julian Data Routine
K, Program Trap and Dump Routine
Kalah
Keyboard Scanner
Kill the Rotating Bit
Leer
Legible Paper Tape
Lewthwaite's Game
List
List SCA
List Device Program
List 1 - High Speed List Program for Intellee 8
List/Print/Type "List SRC" on Diskette
LOAD
Log Base 2
LSOAT
MACRO Assembler for DG NOVA
Main Routine DDUMP (Diskette DUMP
Routines)
Mastermind
Match
Match Game
Maze
Maze
MBCD N1 x N2 Bytes Decimal Multiply
Subroutine
Memory Compare
Memory Diagnostic Program
Memory Dump
Memory Test for the 8080
Memory Test Program
Model 101 Centronics Printer Handler
Mon256 - 256-Byte PROM Monitor
Morse Code Generator
M U L/D I V Multi-Precision Pack for 8080
Natural Logarithm
N-Byte Binary Multiplication and Leading
Zero Blanking
Nim
Nim
Non-Encoded Key Board Subroutine
Nova Cross Assembler - Intel 8080
Numbers
Octal Code Conversion for PDP-11
Octal Debugging Program (ODT) for the
MCS-80 Computer
Octal PROM Programming
OCTHEX
P2708 PROM Programming Routine
Page Break for Tektronix 4010 I/O Graphics
Terminal
Page Listing Program
Paper Tape Reformatter for SO K
Paper Tape Leader 1.0.
Pascali
Pass - Parameter Passing Routine
PDP~11 Bubart File to Intel HEX File Converter
PDP-11 Program Load to HEX, Dump, &
Verify
P LIM 80 Pass 3
PL/M Floating Point Interface
PL/M Histogram Procedure and Random
Number Generator
PROM Programmer for InteJlec 8
Proportional Power Control I mage Builder
Punch Binary Tape
Punch Test or TTY Reader/Punch Test
Quicksort Procedures
RAM Check
RAM Test Program
AANDOM$8ITS
Random Number Generator
-
RING E N
INSITe M USER'S LIBRARY PARTIAL PROGRAM INDEX (Continued)
Read and Interrupt Modifications for Intel-
lee 8/MOD 80
Reader Test
Terminet 300
Terminet 1200
Text Storage Program
Thermocouple Lineariz.ation (Type J)
Tic-Tae-Toe
Time Sharing Communications
TIMIT - Interrupt Driven Real Time Clock
Routine
T.I. Silent 700 Interface - Intetlec MDS
T,I, Silent 700':"" SSC aD Monitor Interface
TRACE Version 7.0
TRACE - Program Trace and Debugger
Trace Routine
TTY Binary Dump Routine
TTY Binary Load Routine
Type
Type K. T.C. Linearizer
Snap Dump 8080
Software Stack Routines for 8008
Source Paper Tape to Magnetic Cassette
ReadIWrite Routines for Interchange Tapes
Real Time Executive
Real Time Monitor
React
SQRTF - Calculates 8-Bit Root of 16-8it
Number
Stage 2
Statement Counter
Structured Assembler for 80aO
Subroutine DMULT (Decimal Multiplication)
Subroutine Log - Common Logarithms
Subroutine SQRT
Symbol Table Dump for Intellec a/MOD 80
Symbol Table List Routine
Relative Jump Routine
RMSTF - Integration Routine
Run 0
Save/Restore CPU State on an Interrupt
SSC 80/10 I nteractive Monitor
110 Exerciser
sse 80/10 Port
SCAN
SDK-BO Keyboard Monitor
SDK-SO Paper Tape Punch Routine
Sets Horizontal Tabs on Terminet
Shellsorting Routine
Sin X, Cos X Subroutine
Slot Machine
SMAL: Symbolic Microcontroller Assembly
Language
Tabs
Tally - User Tally 2200 Line Printer in Assembly Stage of Programming
Tally R2050 HSPTR Driver
Tape Duplicator
Tape Labeler for MDS
Teleprocessing Buffer Routine
Terminal Editor
Utility Macros for 8080
Video Driver
Wipe
Word Game, The
4004/4040 USER'S LIBRARY PARTIAL PROGRAM INDEX
4 X 8 Keyboard Scanner
4 Digit BCD to Binary Converter
4 Digit Multiply
4040 Cross Assembler for Intellec S/MOD
80 and MOS-800
Paper Tape Conversion, 5 Level TTY to 8
Level ASCII
Paper Tape Edit Routine
Parity Checker/Generator
Parity Generator, ASCI I Character
Peripheral I nterface Routine for a Thermal
Strip Printer
Pro Forma
PROM Utility Dump Program
Fast Binary Multiply: Selectable Bit Precision and Constant Execute Time
Fast Decimal Multiply Routine
Floating Point Arithmetic Subroutine Pack-
age
S-Bit Binary to BCD Conversion
General Purpose ROM
8 Digit Register Display
High Speed Printer Interface
ASCii to EBCDIC Code Conversion
Automatic Digital Integration
HEX8CO
Intel MCS-40 Cross Assembler and Text Edi-
Bit Manipulation Routine
BNPF Tape Generator for PDP-8
BNPF Tape Generator for PDP-8
Bowmar TP 3100 Printer Routine
Right Justified Hexadecimal
Random Number Generator
tor
I/O Test
IOMEC Series 3 Cartritape to Intel MCS-4
"SE L" Subroutine (Selector)
TOUCHTONE Keyboard Scanner
John Conway's Solitaire Game of Life
Chebyshev Approximation Functions
Complement Decimal
Cross Assembler for PQP-8
Cross Assembler for NOVA
Cross Assembler and rest program
TP 3100
MCS-4 Simulator for NOVA
MCS-4 Simulator for pop-a
MCS-4/40 Disassembler
Mobile Mean Program
Mod 40/Silent 700 Interface
Multiply/Divide 8 Decimal Numbers
Delay Subroutines
Data Compare Routine
Translate HEX
Universal Logic Subroutine
USER Ll8RARY MEMBERSHIP FORM
I am'interested in becoming a member of Imite ™
Enclosed is 0 check, 0 money order, 0 purchase order*, 0 ~rogram Submittal
NAME ______________________________________
COMPANY. ___________
SHIP TO _____________________________________
o PLEASE SEND THE 4004/4040 LIBRARY INSTEAD OF INSITE™
SEND TO NEAREST LOCATION
North America
Europe
Orient
Intel Corporation
User's Library
Microcomputer Systems
3065 Bowers Avenue
Santa Clara, Californ"la
95051
Intel International
User's Library
51 Rue du Moulin a Papler
Boite 1
B·1160 Brussels
Intel Japan K.K.
User's Library
Flowerhill·Shmmachl, East Bldg.
1·23·9 Shinmachi, Setagaya·ku
Tokyo 154, Japan
Ph. 03·426-9261 (PME & FSE)
03·426-9267 (CS & Fin.!
·Please refer to the OEM Price List for membership fee.
13-70
Data Shifter
MICROCOMPUTER DEVELOPMENT SYSTEMS
UPP-103*
UNIVERSAL PROM PROGRAMMER
for
Universal PROM Mapper software provides powerful data manipulation and programming commands
Personality cards available for programming all
Intel® PROM families
Flexible power source for system logic and programming pulse generation
Zero insertion force sockets for both 16-pin and
24-pin PROMs
Holds 2 personality cards to facilitate programming
operations using several PROM types
Intellec® Development System Peripheral
PROM programming and verification
The Universal PROM Programmer (UPP) is an Intellec® System peripheral capablo of programming and verifying the following Int!!1 Programmable ROMs (PROMs): 1702A, 2704,2708,2716,3001,3602, 3602A, 3621, 3622, 3622A, 3604, 3604A,
3604A L, 3604L-6, 3605, 3608, 3624, 3624A, 3625, 3628, 8702A, 8704, and 8708. In addition, the UPP programs the
PROM memory portions of the 8748 Microcomputer and the 8755 PROM and I/O chip. Programming and verification
operations are initiated from the Intellec Development System consol" and are controlled by the Universal PROM Mapper
(UPM) program.
- - - - - - - - - - - - - - - - - - - - _ . _ - - - - - -.._ - - - - - - - - - - -
'This UPI' 103 ,"pi lit'" II", upp 101, UPP 102.
13-71
UPP-103
FUNCTIONAL DESCRIPTION
The basic UPP consists of a controller module, two
personality card sockets, front panel, power supplies,
chassis and an Intellec Development System interconnection cable. An Intel 4040-based intelligent controller
monitors the commands from the Intellec System and
controls the data transfer interface between the selected
PROM personality card and the Intellec memory. A unique
personality card contains the appropriate pulse generation functions for each Intel PROM family. Programming
and verifying any Intel PROM may be accomplished by
selecting and plugging in the appropriate personality
card. The front panel contains a power-on switch and
indicator, reset switch, and two zero-force insertion
sockets (one 16-pin and one 24-pin or two 24-pin). A
central power supply provides power for system logic and
for PROM programming pulse generation.
Universal PROM Programmer. It uses Intellec System
memory for intermediate storage. The UPM transfers data
in 8-bit HEX, BNPF, or binary object format between paper
tape or diskette files and the Intellec System memory.
While the data is in Intellec System memory, it can be
displayed and changed. In addition, word length, bit
position, and data sense can be adjusted as required for
the PROM to be programmed. PROMs can also be
duplicated or altered by copying the PROM contents into
the Intelfec System memory. Easy-to-use PROGRAM and
COMPARE commands give the user complete control
over programming and verification operations. The UPM
eliminates the need for a variety of personalized PROM
programming routines because it contains the programming algorithms for all Intel PROM families.
The Universal PROM Mapper (UPM) is the software
program which controls transfers of data between paper
tape or diskette files and a PROM plugged into the
There are two versions of the UPM: one that runs under
Intellec System Monitor (paper tape system), and one that
runs under ISIS-II, the Intellec Diskette Operating System
(diskette-hased system). The paper tape version is
included with the Universal PROM Programmer. The
diskette-based version of the UPM is available on all ISISII system diskettes.
HARDWARE INTERFACE
OPTIONS
Data: Two 8-bit unidirectional buses
Commands: 3 Write Commands
2 Read Commands
Initiate Command
Personality Cards:
UPP-361 : 3601 Personal ity Card
UPP-81G: 2716 Personality Card
UPP-848: 8748 Personality Card with 40-pin adaptor
socket
UPP-85b: 8755 PNsonality Card with 40-pin adaptor
socket
UPP-86!>: 3602, 3622, 3602A, 3622A, 3621, 3604,
3624, :l604A, 3624A, 3604AL, 36046-6, 3605, 3625,
3608,3628
UPP-872: 8702A/1702A Personality Card
UPP-878: 8708/8704/2708/2704 Personality Card
PROM Programming Sockets:
UPP-501: 16-pin/24-pin socket pair
UPP-502: 24-pin/24-pin socket pair
UPP-562: Socket Adaptor for 3621, 3602, 3622,
3602A, 3622A
UPP-555: Socket Adaptor for 3604AL, 36046-6, 3608,
.3628
UPP-565: Socket Adaptor for 3605, 3625
The Universal PROM Programmer may be used as a table
top unit or mounted in a standard 19" RETMA cabinet.
PHYSICAL CHARACTERISTICS
Dimensions:
Weight:
6" x 7" x 17"
14.7 cm x 17.2 cm x 41.7 crn
18 Ib (8.2 kg)
ELECTRICAL CHARACTERISTICS
AC Power Requirements: 50-60 Hz; 115/230 VAC: 80 Watts
ENVIRONMENTAL CHARACTERISTICS
Operating Temperature: O°C to 55°C
EQUIPMENT SUPPLIED
Cabinet
Power Supplies
4040 Intelligent Cbntroller Module
Specified Zero Insertion Force Socket Pair
Intellec"" Development System Interface Cable
Hardware Reference Manual
Reference Schematics
Universal PROM Mapper Operator's Manual
Universal PROM. Mapper program (paper tape version disk-based version available on ISIS-II diskettes)
ORDERING INFORMATION
Universal PROM Programmer:
UPP-l03 with 16-pin/24-pin socket pair and 24-pin/
24-pin socket pair.
13-72
MICROCOMPUTER DEVELOPMENT SYSTEMS
INTELLEC®HIGH SPEED PAPER TAPE READER
Loads 16K Intellec® program memory in less than
3 minutes.
Data transfer at asynchronous rates in excess of
2000 characters per second
20 times faster than standard ASR-33 Teletype
reader.
Rack-mountable or stand-alone
The Intellec® High-Speed Paper Tape Reader is an Intellec peripheral that reads paper tape over twenty times faster than the
standard ASR-33 Teletype reader. This translates into a significantly faster development cycle due to a marked reduction in the
time required for repetitive program loading, assembly, and editing operations.
The monitor software provides two key capabilities which significantly enhance the system's performance of the high·speed
reader. A general-purpose paper tape reader driver is included in the Intellec Monitor which enables all system software or userwritten application programs to utilize the high-speed reader features. The monitor also provides dynamic I/O reconfiguration,
permitting reassignment of the high-speed reader to other logical input devices.
Reader data and command interface hardware is provided with the basic Intellec. A reader/lntellec system interface cable is
included with the unit. A fanfold tape guide is also included to provide fanfold punch capability to the ASR-33 Teletype.
The high-speed reader may be used as a table-top unit or mounted in a standard 19" R ETMA cabinet.
I
13-73
HIGH SPEED PAPER TAPE READER
SPECI FICATIONS
TAPE MOVEMENT
Tape Reader Speed:
o to 200 characters per second asynchronous
Tape Stopping:
Stops "On Character"
ENVIRONMENTAL CHARACTERISTICS
Temperature:
Operating:
0 to 55°C (free air)
Non·operating: -55°C to +85°C
Humidity:
Operating: Up to 90% relative humidity without condensation.
Storage: All conditions without condensation of water
or frost.
TAPE CHARACTERISTICS
Tape must be prepared to ANSI X 3.18 or EMCA 10
Standards for base materials and perforations.
Reads tape of any material with th ickness between 0.0027"
and 0.0045" with transmissivity less than or equal to 57%
(oiled buff paper tape).
EQUIPMENT SUPPLIED
Paper Tape Reader
Reader Cable
Fanfold Tape Guide
Fanfold Paper Tape
Hardware Manual
Installation and Operations Guide
Fanfold Guide Installation Instructions
Tape loading: in line
Tape width: 1 inch
PHYSICAL CHARACTERISTICS
Height: 7.75 in. 119.69 cm)
Width: 19.25 in. (48.90 cm)
Depth: 11.62 in. (29.52 cm)
Weight: 13 Ib (5.9 kg)
ELECTRICAL CHARACTERISTICS
AC Power Requirements:
3-wire input with center conductor (earth ground) tied
to chassis. 100, 115, or 127 VAC, single phase at 3.0
amps or 220 or 240 VAC and 1.5 amps; 47 to 63 Hz.
ORDERING INFORMATION
Part Number
Description
MDS-PTR
Paper Tape Reader
I
13-74
inter
SDK-8S
MCS-8S™ SYSTEM DESIGN KIT
Complete Single Board Microcomputer
System Including CPU, Memory and I/O
Easy to Assemble Kit-Form
High-Performance 3MHz 8085 CPU
(1.3 J,lS Instruction Cycle)
Popular 8080A Instruction Set
Interfaces Directly With TTY
Interactive LED Display and Keyboard
Large Wire-Wrap area for Custom
Interfaces
Extensive. System Monitor Software in
ROM
Comprehensive Design Library Included
Low Cost
The MeS-85 System Design Kit (SDK-85) is a complete, single board, microcomputer system in kit form. It contains all
necessary components, including LED Display, Keyboard, resistors, caps, crystal and miscellaneous hardware to
complete construction. Included is a preprogrammed ROM that contains the system monitor for general software utilities
and system diagnostics.
The SDK-85 includes 6 digit LED display and 24 key-keyboard for a direct insertion, examination and execution of a user's
program. In addition, it can be directly interfaced with a teletype terminal.
The SDK-85 is an inexpensive, high-performance prototype system that has designed-in flexibility for simple interface to
the user's application.
13-75
SDK-85
Keyboard Monitor Commands
General
• Reset - Starts the monitor
• GO - allows you to execute a user program
• Single Step - allows you to execute a user program one
instruction at a time ~ useful for debugging
• Substitute Memory - allows you to examine and
modify memory locations
• Examine Register - allows you to examine and modify
the 8085's register contents
• Vector Interrupt - a user interrupt button
The SDK-85 is a complete 8085 microcomputer system on
a single board, in kit form. It contains all .necessary
components to build a useful, functional system. Such
items as resistors, caps, and sockets are included.
Assembly time varies from 3 to 5 hours, depending on the
skill of the user.
A compact but powerful system monitor is supplied with
the SDK-85 to provide general software utilities and
system diagnostics. It comes in a pre-programmed ROM.
Teletype Monitor Commands
The SDK~85 communicates with the outside world
through either the on-board LED Display/Keyboard
combination or, the user's TTY terminal (Jumper
Selectable). Both memory and I/O can be easily expanded
by simply soldering in additional devices in locations
provided for this purpose. A large area ofthe board (45 sq.
in.) is laid out as general purpose wire-wrap for the user's
custom interfaces.
• Display Memory - displays multiple memory locations
• Substitute Memory - allows you to examine and
modify memory locations one at a time
• Insert Instructions - allows you to store multiple bytes
in memory
• Move Memory - allows you to move blocks of data
in memory
• Examine Register - allows you to examine and modify
the 8085's register contents
• GO - allows you to execute user programs
Only a few simple tools are required for assembly;
soldering iron, cutters, screwdriver, etc. The SDK-85
User's Manual contains step-by-step instructions that
make assembly easy, and eliminate mistakes. Once
construction is complete, the user connects his kit to a
power supply and the SDK-85 is ready to go. The monitor
starts immediately upon power-on or reset.
ROM/IO (8355)
EPROM/Ie (8755)
ADDRESS
OECODER
CPU
In addition to detailed information on using the monitors,
the SDK-8S User's Manual provides circuit diagrams, a
monitor listing, and a description of how the system
works.
KEYBOARD/DISPLAY
RAM/IO/COUNTER
FOR BUS EXPANSION
ADDRESS
DATA
FielD
FIELD
1
1
1
1
l~nE'n/-1
o. 1.0.0.
1
1
1
1
1
I
1
1
1
1
1
1
1
I
I
1
I
"~T~O I
I
I
INTERRUPT
INPUTS
808S
~
DATAl
..:
1
1
,:
I
;..
~
8205
ADOR ESS
I
1
1
ADDA ESS
I
I
r
.
111
-
!
I
1
,..
:.
8355
~N~Cri
SINGLE
STEP
GO
-V sUeST EXAM
MEM
REG
NEXT EXEC
C
o
• ;.,
--,
8155
I
II
8155
.1
I..; ;.
I
I
I~
I
0
1
8279
i>
I
2
F
B
7
1
1
1
P~L 1
I
1
I
~ -----'~
8216
_____
J
8
1
DATA
BUS
I
,----,
1
IL..
8216
I
_____ ..1
I
I
I
7
E
8 9
A
H
L
4
5 6
SPH SPL PCH
.
• 7
I.
r--:l~-'g
L ____
I
1
1
I
--,1
8755
~.J
1
I
BUS
""'"
RESET
I ,D:-' I -n'DIR
·· I
&
I
.1
1
)-
1
1
SDK·85 KEYBOARD LAYOUT
SERIAL
rD 1
88
1
1
I
1
I
I
..1
16
,..
----,
ADDRESS
BUS
8212
BUS
•
CDNTROL
1
71
I
I
I
BUS
~-
- ...
,
L. _ _
"- _ _ _ _ ..I
I
I
1
I
1
1
I
I
.
1
),
I
r
I
----'~
3 x 8216
15
CONTROL
L _ _ ' _ _ ..
I
I
I
I OPTIONAL. A PLACE HAS BEEN PROVIDED ON THE PC BOARD FOR THE DEVICE BUT THE
DEVICE IS NOT INCLUDED
~
SDK·a5 FUNCTIONAL BLOCK DIAGRAM
13·76
BUS
SDK-8S
The SDK-85 is designed around Intel's 8085 Microprocessor. The Intel® 8085 is a new generation, complete 8bit parallel central processing unit (CPu). Its instruction
set is 100% software upward compatible with the 8080A
microprocessor, and it is designed to improve the present
8080's performance by higher system speed. Its high level
of system integration allows a minimum system of three
IC's: 8085 (CPU), 8156 (RAM) and 8355/8755 (ROM/
PROM),
The 8085 incorporates all of the features that'the 8224
(clock generator) and 8228 (system controller) provided
for the 8080, thereby offering a high level of system
integration.
The 8085 uses a multiplexed Data Bus. The address is split
between the 8-bit address bus and the 8-bit data bus. The
on-chip address latches of 8155/8156/8355/8755 memory
products allows a direct interface with 8085.
INSIDE THE 8085:
181
181
REG
181
H
181
REG
STACK POINTER
ENCODING
181
181
REG
MACHINE
CYCLE
181
REG,
REG
PROGRAM COUNTER
POWER{_+5V
SUPPLY
_
GND
(16)
REGISTER
ARRAY
1161
INCREMENTER DECREMENTER
(16)
TIMING AND CONTROL
A'5- AS
ADDRESS BUS
•
•
SEVEN a·BIT REGISTERS. SIX OF THEM CAN BE LINKED
IN REGISTER PAIRS FOR CERTAIN OPERATIONS.
B-BIT ALU.
•
•
ADrADo
ADDRESS/DATA BUS
16·BIT STACK POINTER (STACK IS MAINTAINED
OFI'BOARD IN SYSTEM RAM MEMORY).
16·BIT PROGRAM COUNTER .
8085 INSTRUCTION SET Summary of Processor Instructions
Mnemonic
Oescriplion
Inslruclion Codell)
Clockl2)
07 06 05 04 03 02 01 DO Cycles
MVI M
LXI B
LXI 0
LXI H
STAX
STAX
LDAX
LDAX
STA
LOA
SHLD
LHLD
XCHG
B
0
B
0
Move regls1er to register
S S
Move register to memory
S
Move memory to register
Move Immediate register
Move Immediate memory
Load Immediate register
Pair B & C
Load Immediate register
Pall 0 & E
Load Immediate register
Pall H & L
Store A ,"dllect
Store A ,"dllect
Load A ,"dllect
Load A Indileci
Store A dllecl
Load A dllect
Store H & L dllect
Load H & L dllect
Exchange 0 & E H & L
Registers
Oescriplion
InSlruclion Codell)
Clock)2)
07 06 05 04 03 02 01 DO Cycles
STACK OPS
MOVE. LOAD. AND STORE
MOVI112
MOV M.r
MOV r.M
MVI r
Mnemonic
PUSH B
PUSH 0
0
0
10
10
PUSH H
PUSH PSW
10
POP B
10
POP 0
POP H
POP PSW
13
13
XTHL
16
16
SPHL
LXI SP
INX SP
DCX SP
13-77
Push register Pair B &
C on stack
Push register Pall 0 &
E on stack
Push leglster Pall H &
L on stack
Push A and Flags
on stack
Pop register Pall B &
C off slack
Pop register Pall 0 &
E off stack
Pop reg Isler Pall H &
L off stack
Pop A and Flags
off stack
Exchange top of
stack. H & L
H & L to slack pOlnler
Load Immedlale sieck
pOinter
Increment stack pOinter
Decrement stack
pOinter
12
12
12
12
10
10
10
10
16
10
I
SDK-8S
8085 INSTRUCTION SET
Mnemonic
Summary of Processor Instructions (Con!.)
Inslruclion Codelll
Clockl21
D) D6 D5 D4 D3 D2 DI Do Cycles Mnemonic
Description
Description
Instruction Codelll
Clockl21
D) D6 D5 D4 D3 D2 DI DO Cycles
JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
PCHL
Jump unconditional
Jump on carry
Jump
Jump
Jump
Jump
on
on
on
on
Jump on
Jump on
Jump on
H & L to
counter
10
7/10
7/10
7/10
no carry
zero
no zero
pOSItive
minus
panty even
pallty odd
program
CNZ
CP
CM
CPE
CPO
1 0
7/10
7/10
7/10
SUBTRACT
7/10
6
S88 r
18
9/18
9/18
9/18
9/18
9/18
9/18
9/18
9/18
Callan pallty even
Callan pallty odd
RETURN
Return
RC
RNC
AZ
RNZ
RP
Return
Return
Return
Return
Return
Return
Return
Return
RM
RPE
RPO
on
on
on
on
on
on
on
on
10
6/12
6/12
6/12
6/12
6/12
6/12
6/12
6/12
carry
no carry
zero
no zero
pOSItive
minus
panty even
pallty odd
RESTART
AST
Aestart
SU8 M
A A A
SUI
S81
ORA r
CMPr
ANA M
XRA M
ORA M
CMP M
ANI
XRI
ORI
CPI
12
ROTATE
INR r
OCR r
INR M
OCR M
INX 8
RLC
ARC
RAL
Increment register
Decrement register
Increment memory
Decrement memory
Increment 8 & C
registers
Increment 0 & E
registers
INX H
Increment H & L
registers
DCX 8
DCX 0
DCX H
Decrement 8 & C
Decrement 0 & E
ADD M
ADC M
ADI
ACI
RAR
8 & C to H& L
0 & E to H & L
H & L to H & L
stack pointer to
L
Subtract regISter
from A
Subtract regISter from
A with borrow
Subtract memory
from A
Subtract memory from
A with borrow
Subtract immediate
from A
Subtract Immediate
from A with borrow
10
10
10
10
S
And register with A
Exclusive Or register
with A
Or register with A
Compare register with A
And memory with A
ExcluSive Or memory
with A
Or memory with A
Compare memory with A
And Immediate with A
Exclusive Or Immediate
with A
Or Immediate with A
Compare Immediate
with A
Aotate
Rotate
Rotate
carry
Rotate
carry
A left
A light
A left through
A light through
SPECIALS
CMA
STC
CMC
DAA
Complement A
Set carry
Complement carry
Decimal adjust A
INPUT /OUTPUT
Decrement H & L
IN
OUT
Add register to A
Add register to A
with carry
Add memory to A
Add memory to A
with carry
Add Immediate to A
Add Immediate to A
with carry
CONTROL
ADO
ADD r
ADC r
10
10
Add
Add
Add
Add
H&
LOGICAL
ANA r
XRA r
INCREMENT AND DECREMENT
INX 0
I
SU8 I
S88 M
Call unconditIOnal
Callan carry
Callan no carry
Callan zero
Callan no zero
Callan positive
Callan minus
RET
8
0
H
SP
7/10
CALL
CALL
CC
CNC
CZ
DAD
DAD
DAD
DAD
EI
01
NOP
HLT
Input
Output
10
10
Enable Interrupts
DISable Interrupt
No-operation
Halt
NEW 8085 INSTRUCTIONS
RIM
SIM
Read Interrupt Mask
Set Interrupt Mask
NOTES: 1. DOD or SSS 8=000, C=OOl, 0 OtO. E 011, H 100. L·l0l, Memory=110, A=ll1.
2. Two possible cycle times, (6/12) Ind Icate instructIOn cycles 'dependent on condition flags.
13-78
"All mnemonics copyright
©Intel Corporation 1977
SDK-85
SDK-8S SPECIFICATIONS
Central Processor
DMA
CPU: 8085
Instruction Cycle: 1.3 microsecond
Tcy: 330 ns
Hold Request: Jumper selectable. TTL compatible input.
Software
Memory
ROM: 2K bytes (expandable to 4K bytes) 8355/8755
RAM: 256 bytes (expandable to 512 bytes) 8155
Addressing:
ROM 0000-07FF (expandable to OFFF with an additional
8355/8755)
RAM 2000-20FF (2800-28FF available with an additional
8155)
Note: The wire-wrap area of the SDK-85 PC board may be
used for additional cust9m memory expansion up to the
64K byte addressing limit of the 8085.
Input/Output
Parallel: 38 lines (expandable to 76 lines).
Serial: Through SID/SOD ports of 8085. Software
generated baud rate.
Baud Rate: 110
Interfaces
Bus: All signals TTL compatible.
Parallel I/O: All signals TTL compatible.
Serial I/O: 20 mA current loop TTY
Note: By populating the buffer area of the board, the user
has access to all bus signals which enable him to design
custom system expansions into the kit's wire-wrap area.
System Monitor: Pre-programmed 8755 or 8355 ROM
Addresses; 0000-07FF.
Monitor I/O: Keyboard/Display or TTY (serial I/O)
Literature
Design Library (Provided with kit):
•
•
•
•
•
•
•
SDK-85 User's Manual
MCS-85 User's Manual
8080/8085 Assembly Language Programming Manual
Intellec'") MDS Brochure
ICE-85 Data Sheet
PLlM-80 Data Sheet
8085/8080 Assembly Language Reference Card
Physical Characteristics
Width: 12.0 in.
Height: 10 in.
Depth: 0.50 in.
Weight: approx. 12 oz.
Electrical Characteristics (DC Power Required
- Power Supply Not Included in Kit)
Vee 5V ±5%
VTTY -10V
± 10%
Interrupts
Three Levels: (RST 7.5) - Keyboard Interrupt.
(RST 6.5) - TTL Input
(INTR) - TTL Input
1.3 Amps
0.3 Amps (VTTY required only if
teletype is connected)
Environmental
Operating Temperature: 0-55°C
13-79
inter
TEST & INSTRUMENTATION SYSTEM
fLSCOPETM 820
MICROPROCESSOR SYSTEM CONSOLE
Provides an interface to microcomputer systems
for troubleshooting system problems
Is a stand-alone, self-contained, rugged portable
unit
Monitors, displays, and alters register, memory
and I/O values for system under test
Human engineered with easy to read 9-segment
hexadecimal displays and extensive operator
prompting
Executes diagnostic routines from J,LScope 820 console overlay memory
Executes instrument resident software patch
routines even when microcomputer system is
ROM-based
Gives complete control over microprocessor
including single step, run with display, or run
real-time capability
Designed to
processors
Provides a 32-bit hardware breakpoint with bit
masking and a 256-word trace memory
support
many
different
micro-
Has built-in, self-test operation
The IlScope™ 820 Microprocessor System Console is a portable, self-contained instrument designed to provide the control,
monitoring, and interaction necessary to effectively and quickly evaluate and debug 8-bit microcomputer-based systems
in the lab, on the production line, or in the field. Connection to the user's system is through a personality probe that is
plugged into the microprocessor socket. Each personality probe is unique to each microprocessor type. The instrument
features many different operating and control modes which allow the operator to carry out a number of functional checks
on the microcomputer System Under Test (SUT).
The unit has been specificially designed to ease the task of microcomputer system check-out for the lab, production line,
and field technician. It also provides the more powerful analytical capabilities necessary to troubleshoot difficult problems
by the more experienced, sophisticated user. Preprogrammed test routines resident in front panel PROMs, dedicated high
level command keys, visual prompting, and simplified data entry sequences all ease the check-out of microcomputer hardware. For more rigorous diagnostic tasks, the unit provides a 32-bit maskable hardware breakpoint with optional course of
action after a breakpoint match, a 256 X 32-bit trace memory and a 128 X 8 overlay RAM that allows real-time entry of test
routines via the IlScope 820 Microprocessor System Console keyboard.
13-80
fLSCOPETM 820
CHARACTERISTICS
COMMANDS
MEMORY OVERLAY
Reset
Self Test
CPU Reset
Run Real Time
Run with Display
Halt
Single Step
Enable/Disable Breakpoint
Enable/Disable Overlay
Enable Trace All Cycles
Enable Trace at Breakpoint
Examine/Modify Value
Single Registers
Double Registers
CPU Statas
Breakpoint Pass
Count
™
Examine/Modify Memory
Examine/Modify I/O
Examine/Modify Overlay Memory
Examine/Modify Next Location
Examine/Modify Last Location
Examine/Modify BreakpOint
Condition
Examine/Modify Breakpoint
Mask
Examine/Modify Breakpoint
Action
Examine/Modify Overlay Origin
Display Trace Data
Clear Entry
Continue
End/Execute
Subroutine Select
The jLScope
820 Microprocessor System Console allows memory
read/writes of the user CPU in any assigned 1 K or 2K block to be
made to the instrument's overlay memory. For 1 K block assignments, the first 128 bytes reside in the instrument's RAM memory
while the remaining 896 bytes reside in the interchangeable front
panel ROM/EPROM (either Intel's 2716 EPROM or Intel's 2316E
ROM). For 2K block assignments, again the first 128 bytes are from
RAM and the remaining 1920 bytes are from the front panel 2716/2316E.
DATA DISPLAY
Eight hexadecimal 0.5 in. LEOs are provided for the simultaneous
display of 4 bytes of information. The displays are physically separated into two groups. The first group displays 2 bytes of address,
while the second group displays CPU data, status, single and double
byte register values, or single and double byte breakpoint values.
In addition, eight binary displays are used to provide quick recognitio~ of single byte binary data patterns.
CPU CONTROLS
SELF TEST
User-selectable commands permit one of four possible CPU operating modes:
The necessary hardware and software have been incorporated into
the instrument to facilitate the self-checking of the majority of its
operations. Included in thase self tests are:
1. Run Real Time - User's CPU runs at full speed set by user
clock. No wait states or cycle stealing are required.
User's CPU runs at full speed, except
that 10 times/sec the instrument halts user's CPU temporarily
to acquire display data. Worse case throughput is 95% of real
•
Bit tests of all breakpoint condition and mask latches.
•
Bit tests of all RAM.
time operation;
•
Verifies checksum on all operating system ROMs.
3. Halt - User CPU halted at next opcode fetch. DMA activity
is permitted during HALT.
•
Clears trace memory and performs bit test on trace RAM.
•
Checks miscellaneous I/O ports and peripheral components.
4. Single Step - User CPU executes one instruction then halts.
•
Lights all front panel displays for user verification.
2. Run with Display -
BREAKPOINT
CONNECTION
The breakpoint condition is set by a 32-bit word (l6-bit address,
8-bit data, 8-bit status). The breakpoint mask is also set by a 32-bit
word which is bit-selectable. There are three courses of action following a breekpoint match:
Four external ,connections to the jLScope 820 Microprocessor
System Console are provided:
•
1.2 m (4 ft), 50 conductor flat cable for connection to the
microprocessor probe.
1. Halt on first opcode fetch following breakpoint match.
•
2. Halt on first opcode fetch following Nth breakpoint match
1 .. N .. 256.
3. Execute subroutine beginning at first opcode fetch following
breakpoint match.
All breakpoint actions following a match are controlled by the
breakpoint enable/disable switch except for trace recording and the
Sync Trigger Output. The Sync Output is a negative true TTL
output ,that,occurs whenever a breakpoint match occurs.
180 nsec typ
Pulse Width
Output High
2.5V min, -1.2 mA
Output Low
0.5V max, 24.0mA
20-pin board edge connector for the probe personality
PROM.
•
24-pin zero force insertion sockets for overlay EPROM/ROM.
•
One recessed pin for breakpoint sync output.
PHYSICAL CHARACTERISTICS
Width:
Length:
Height (top closed):
Height (top removed):
Weight:
479mm
394mm
168mm
117 mm
9.1 kg
(18-7/8 in.)
(15-1/2 in.)
(6-5/8 in.)
(4-5/8 in.)
(20Ib)
ELECTRICAL REQUIREMENTS
TRACE
Voltage:
Frequency:
The trace memory is a 256-word memory with each word consisting
of 16 address bits, 8 data bits and 8 status bits. The memory is a
circular buffer which records the last 256 cycles (words) prior to a
user CPU halt or DISPLAY TRACE command. Trace data can be
recorded on all CPU cycles or only when breakpoint matches
occur (independent of breakpoint enable/disable status). In addition, the operator can initiate a panel freeze which temporarily
stops all trace data recording, and allows display of previously
recorded data without halting the user CPU.
100, 120, 220, 240 48-63 Hz
10% +5%, 11 OV A max
ENVI RONMENTAL CONDITIONS
Operating Temperature:
Storage Temperature:
Humidity:
O°C to 55°C (32°F to 130°F)
-40°C to 75°C (_40°F to 167°F)
95% RH, 15°C to 40°C (59° F to 104°F)
non condensing
DATA ENTRY
ACCESSORIES SUPPLIED
All single and double byte items can be entered via the front panel
hexadecimal keypad. In addition, all single byte items can be
optionally entered via eight binary input keys.
Two keys
One' Operator's Manual
One fuse for 220/240 V operation One Hardware Reference Manual
One 2.3 m (7.5 ft) power cord
ORDERING INFORMATION
Part Number
Description
USC-820
Microprocessor System Console
13-81
}L SCOPETM 820
CPU CONTROL
ADDRESS DISPLAY/SELECT
The Instrument provides complete control over the opera·
A dedicated, 4-digit hexadecimal address display allows the
following address information to be displayed:
tion of .the microprocessor in the System Under Test
(SUT). The user CPU can be forced to HALT, SINGLE
STEP, RESET, RUN REAL TIME, or RUN WITH DIS·
PLAY, All of the above CPU commands can be issued
Without Impacting other operational parameters or diag·
nostic sequences that have been set up.
• The address of any memory location.
• The 1/0 port number of any 1/0 port.
• The address of any overlay memory location.
• The address of the overlay memory Origin assignment.
• The address at which the breakpoint is to occur.
• The address portion of the breakpoint mask,
• The address of the given trace record element.
An additional feature of the address displaylselect logic is
that once the operator has initkited a given memory, trace,
or 1/0 examination, it IS possible to continue the examination in a sequential fashion either In an ascending or descending address value.
BREAKPOINT CONTROL
The hardware breakpoint of the Instrument allows the
operator to alter the normal program flow of the SUT.
Breakpoint logiC is implemented In hardware. thereby
eliminating any throughput degradation of the SUT. All
32 bits of the breakpoint condition word are maskable in
order to allow the breakpoint condition to be as specific
or as general as may be deSired.
The occurrence of a breakpoint match can cause an unconditional halt, Incrementing of the pass counter, catting of
a subroutine, or the recording of a single cycle of trace
data. All of these options are selectable via the EXAM
ACTION key pnor to enabling the breakpoint.
TRACE MEMORY
The console has a full 32-blt word trace memory that
records 256 cycles of SUT operation Without causing any
delays. The trace memory provides information about CPU
ope~at,on just pnor to a CPU halt or just prior to the
Initiation of a panel freele via the trace DISPLAY key.
The operator can alternatively elect to have data recorded
on all SUT microprocessor cycles or only when program
execution of the SUT microprocessor generates a breakpoint match. Once the data is recorded, sequential examtnation of the data can be accomplished simply by depressing
the EXAM NEXT or EXAM LAST keys.
The ,address, data, and control variable entry into the
instrument is accomplished via the conveniently located
hexadeCimal keypad.
OVERLAY MEMORY
A unique feature of the unit IS the ability to map Its
memory onto the SUT memory space. USing the overlay
memory allows the operator to Insert patch, exerCise, or
diagnostic subroutines at any location or pomt of execution
In the SUT program. The subroutine can either be entered
via the front panel hexadecimal keypad or via the front
panel's ROMIPROM socket.
By using the umt's overlay memory, the operator can
qUickly set Up the SUT to execute speCial maintenance
or troubleshooting programs that permit rapid evaluation
of system operation.
13·82
For sele,ction of the information to be displayed or modified the operator enters the. h~xadecimal value of the desired address, 1/0 port number or label assigned to each of
the registers. Once this entry is made, the operator can then
elect to either CONTINUE data entry if modification is
desired or press the ENDIEXECUTE key if examination
only is desired. For all data entry sequences that potentially
require multiple value entry, the ,uScope™ 820 Microprocessor System Console provides operator prompting to
indicate the specific information expected.
J.L SCOPEiM 820
VALUE DISPLAY/SELECT
PROM/ROM SOCKET
A front panel socket is provided for mounting 2K PROMs
The value displays provide clear and easy to use Information. Together with the address display, they provide simultaneOlJs readout of trace vectors, breakpoint conditions
and breakpoint mask values, memory contents and 110 port
contents. In addition, the display allows readout of all
single and double byte register values, the state of CPU PinS
and flags, Information regarding the course of action fol·
or ROMs that seTve as storage for pre programmed test
subroutines The actual useabl.e program space of the
PROM/ROM is 1920 bytes. The remainmg 128 bytes of
storage, shadowed by RAM, are used by the unit to Identify
up to 16 separate subroutmes in the PROM/ROM and to
define the specific Instrument states and conditions under
which the subroutine will be called. Each of the separate
subroutines rs uniquely enabled by the SUBR SELECT key
and the hex keypad.
lOWing the occurrence of a breakpoint. CIS weH as Informa-
tIOn regarding the breakpoint pass count.
The Information displayed by the 4-dlQlt hexadeCimal value
readouts is selected via the hexadecimal keypad In con·
junction with any of the instrument's 11 dedicated examine
keys. Further, the information is either displayed statically
or is continually updated 10 times/sec if the unit is In the
run with display mode.
POWE R SUPPL Y
The system console is complete With Its OVvn fully regulated
DC power supply that prOVides all the DC power required
by the unit Itself, as well as that which IS required by the
assOCiated microprocessor probe. The supply IS completely
self-contained, Including ItS own AC on/off switCh, line
fuse, line filter and power cord. An additional feature of
the power supply is that It has been deslgnl:!d to permit Illle
voltaqe selectIon in the field to faCIlitate operation With a
Wide range of AC line voltages and frequencies.
BREAKPOINT ACTION
FollOWing the occurrence of a breakpOint match. the
operator has the fleXibility to execute a number ot dlf·
ferent diagnostic operations. Th@ selection of these
alternate courses of action IS accomplished by pushing the
- - - -_ _ _ _ _ _ _ _ _ _ _ _ EXAM ACTION key and then entetlng the assigned value
of the specific actIon deSlTed via the hex keypad. Further
keypad entries specify the parametTic value of the action
selected such as the number of breakpOint pass counts or
the start address of a subroutine call followmg a break·
pOint
PROBE CONNECTION
The instrument IS mtended to work With many of the
microprocessors that are available today. ThiS IS accomplished by standardized Interface logiC which transmits and
receives various address, data, and control Signals between
the system console and the circuitry of the particular
probe. The interconnect circuitry between the instrument
and probe has been deSigned to drive a 4·foot cable that
permits convenient positionmg of the panel ami the SUT.
In addition, a board edge connector has been prOVided for
a personality ROM that prOVides front panel definition
and interpretation of speCifiC control Signals for different
types of mlcroproCE'ssors. ThiS personality ROM IS supplied with each probe kit.
FRONT PANEL
All 8·bit values can be displayed in binary format on the
instrument. The binary display operates in parallel with the
hexadecimal display and it is provided for those instances
where operator recognition IS enhanced by binary presentation. The selection procedure for the binary data display is
identical to that for the hexadecimal value display. Once
the selection has been made, the operator can alter the
value by means of further hex keypad entries or by
changing the binary state of any of the data bits via the
8 binary data swltche-;.
The front panel of the J-IScope ™ 820 Microprocessor System Console has been designed to be rugged and durable as
well as easy to use and understand. A plastiC overlay that
employs membrane switch contacts prOVides long lasting
durability as well as protection from aCCidental spills.
Audio and tactIle feedback for the membrane SWitches IS
prOVided for operator convemence.
13-83
I Ease of use of the front panel has been further enhanced
. by human engmeering With functional grouping of SWitches
as well as LEOs that prompt the operator during data entry
sequences. GraphiCS have also been added to reinforce the
functional switch groupmgs as well as data entry procedures.
TEST & INSTRUMENTATION SYSTEM
}LSCOPETM PROBE 8080A
Operates over a broad range of environmental
conditions
Provides interconnection for 8080A Microprocessor-based Systems to the /-!Scope™ 820 Microprocessor System Console
Comes complete with cable, buffer box, personality ROM, and /-!Scope 820 system console overlay
Provides complete control over the system under
test, yet causes minimal interference with system
under test operation
Has user system interconnect cable with integral
ground plane for low noise operation
Fits securely in the console carrying case during
transit
Connects via a 4 foot cable to the /-!Scope 820
Console
Provides complete protection for plug pins during
transit
The probe 8080A provides the pScope 820 console with the ability to interact with 8080A Microcomputer-based Systems.
The purpose of the probe is to interface the pScope 820 console to the CPU of the System Under Test (SUT). All of the
interface signals and the associated circuitry have been designed to be effectively transparent to the SUT. CPU data, address,
and clock lines are sensed by the probe 8080A, with only the CPU control lines being switched. In addition, all SUT loading
and timing degradations have been minimized by specially designed buffer circuitry.
The mechanical design of the probe is compact, rugged, and allows proper operation of the probe and the console over the
full ambient range specified. The buffer circuitry and the ground plane design of the interconnect cable provide low noise
electrical signals while allowing the SUT to be 4 feet from the system console.
13-84
~SCOPETM
PROBE 8080A
GENERAL
Inputs from user system:
J..ISCOPE 820 CONSOLE INTERCONNECT
The probe interconnection to the J..IScope 820 console is
accomplished via a 1.2 m (4 ft) flat cable. 50-pin mating
connectors plug into a board edge connector in the power
cord compartment of the instrument and into a flat cable
connector on the buffer box.
INT, READY,
RESET
40 J..IA max @ 2.7V; -0.72 mA max@
O.4V; 50 pF typical
HOLD
60 IlA max @ 2.7V; -1.08 mA max @
O.4V; 50 pF typical
CONNECTIONS
Three external connections to the probe are provided:
SYSTEM UNDER TEST (SUT) INTERCONNECT
• 50-pin flat cable connector on buffer box
I nterconnection from the buffer box to the SUT is accomplished with a 406 mm (16 in.) flat cable, complete with
an integral ground plane, which is terminate.d with a low
profile 40-pin DIP connector. The DIP connector is
inserted into the SUT 8080A socket and the 8080A itself is
plugged into the 40-pin socket provided on the probe
buffer box.
CHARACTERISTICS
IlSCOPE 820 CONSOLE CONFIGURATION
PHYSICAL CHARACTERISTICS
Several features of the console are directly determined by
the probe being used with it. The instrument features that
are determined by the 8080A interface probe are:
Probe Buffer Box:
• Single Registers: A, B, C, D, E, H, L
• Double Registers: BC, DE, HL, PC, SP
• 40-pin zero insertion socket for the 8080A
• 40-pin low profile replaceable IC DIP connector for
connection to SUT
Height:
Length:
Width:
19 mm
184 mm
95 mm
(3/4 in.)
(7-1/4 in.)
(3-3/4 in.)
User System Interconnect Cable:
• CPU States: Flags, CPU pins (SYNC, RESET, HLDA,
HOLD, READY, INT, INTE)
• Trace/Breakpoint Word Size: 32 bits with 16 bits of
address, 8 bits of data and 8 bits of CPU status.
ELECTRICAL SPECIFICATIONS
All DC specifications are in addition to user system parameters. All capacitance values include cables and connectors.
Width:
Length:
57 mm (2-1/4 in.)
406 mm (16 in.) flat cable
J..IScope 820 Console Personality ROM PC Card:
Height:
Width:
Length:
19 mm (3/4 in.)
57 mm (2-1/4 in.)
83 mm (3-1/4 in.)
POWER REQUIREMENTS
Power supplied by J..IScope™ 820 Microprocessor System
Console.
Non-Intercepted Signals
1/>1,1/>2
±10 J..IA max; 55 pF typical
A15-AO, D7-DO
-0.25 mA max @ 0.45V; 30 J..IA max
@ 5.25V; 49 pF typical
ENVIRONMENTAL CONDITIONS
+12V Supply
15J..1A max
Operating Temperature:
0° to 55°C (32° to 130°F)
WAIT
35 pF typical (capacitive loading only)
Storage Temperature:
-40°C to 75°C (_40° to 167°F)
Humidity:
95% RH, 15° to 40°C (59° to
104°F) noncondensing
I ntercepted Signals
Outputs to user system:
SYNC
20 mA min @ 0.5V; -1 mA min @
2.7V;40 pF typical
HOLDA,INTE, 4 mA min @ O.4V; -0.2 mA min @
DBIN, and WR 2.7V; 40 pF typical
ORDERING INFORMATION
Part Number
Descri ption
PRB-80
8080A Interface Probe
13-85
ACCESSOR I ES SUPPLIED
One J..IScope 820 System Console Overlay
One Personality ROM
One Hardware Reference Manual
MICROCOMPUTER TRAINING PROGRAMS
Courses presented at training centers and customer facilities.
System demonstrations.
Training Centers
Boston
Hands-on laboratory sessions reinforce lecture.
Chicago
Santa Clara
Training center classes limited to 14 attendees.
Scheduled on a continuing basis throughout the year.
On-site courses tuned to customer requirements.
Intellec® Microcomputer Development Systems with InCircuit Emulators in laboratory.
Microcomputers are being used in hundreds of applications from simple controllers to complex data processing systems. To
enable users to bring microcomputers into their applications, Intel offers a selection of workshops that are designed to provide you with the "tools" for making optimum use of Intel microcomputers in system development.
COURSE PREREQUISITES:
MCS-80/85™ System, MCS-48™.system, PUM-80 Language/Software Design, General Purpose Peripherals,
Dedicated Function Peripherals Workshops. The course prerequisites are a knowledge of binary and hexadecimal
number systems and basic logic functions. To attain maximum benefit from course presentation, some background in logic
design or computer programming is recommended.
RMX-80™ System Workshop. A working knowledge of the 8080 (or 8085) and the Inteliec Microcomputer Development
System, or attendance at the MCS-80/85 System Workshop is required. For those that are unfamiliar with the concepts and
implementation of modular program design, we recommend attendance at the PL/M-80 Language/Software Design Workshop.
REGISTRATION AND ADDITIONAL INFORMATION: Contact MCSD Training at Intel Corporation, Santa Clara,
California 95051, (408) 987-8003 or 987-8004 or your local Intel sales office.
13-86
MICROCOMPUTER TRAINING PROGRAMS
MCS-SO/S5 System Workshop
This workshop will prepare the student to design and develop a system using
the Intel® 8080/8085 microprocessors through the use of lecture,
demonstration, and laboratory "hands-on" experience with the Intellec®
Microcomputer Development System and In-Circuit Emulator.
COURSE OUTLINE:
Day 1
Introduction
a. Microprocessor System
1. Function
2. Organization
3. Programming
b. Central Processor Overview
1. Functional Sections
2. Programming Model
3. Execution Sequence
Assembly Language Instructions
a. Input/Output
b. RegisterlMemory Reference
c. ArithmetiC, Logical, Rotates
Programmed Input/Output
a. Status Request
b. Command
c. Data Transfer
Development System
a. Function
b. System Monitor
c. Disk Operating System
Debugging With the Syslem Monitor
a. Break Points
b. Examine Registers
Laboratory
a. Using the System Monitor
b. Program Instruction Sequences
c. Debugging and Break Points
Day 2
Disk Operating System Modules
a. Macro Assembler
b. Text Editor
c. File Utility Commands
System Timing
a. Instructions
b. State Transition
c. Signal Relationships
d. Specifications
Subroutines
a. Invocation
b. Stack Memory
c. Parameters
Interrupt System
a. Description
b. RST Instruction
c. Service Subroutines
Laboratory
a. Using the Disk Operating
System
b. Program Assembly and
Execution
Day 3
Branch Tables
a. Application
b. Construction
Direct LoadlStore Instructions
Special Purpose Instructions
Macros
a. Definition
b. Reference
c. Expansion
8080A CPU Set
a. 8228/8238 System Controller
b. 8224 Clock Generator
c. RAMIROMIPROM Address
Decoding
d. Memory Mapped 110
8085 CPU Set
a. 8085 Bus Structure
b. 8355/8755 ROMIEPROM
and 110
c. 8155 RAMITimer and 110
Laboratory
a. Monitor Subroutines
b. Program DEBUG Under Disk
Operating System
13-87
Day 4
Family Peripherals
a. Memory Design
1. 8708 PROM
2. 2114 RAM
b. 110 Design
1. 8255 Parallel Interlace
2. 8251 Serial Interface
In-Circuit Emulator
a. Prototype Development
b. Resource Sharing
c. Mapping Commands
d. Utility Commands
e. Debug Commands
f. Emulation Syntax
Laboratory
a. Use of the In-Circuit Emulator
for System Debugging
Day 5
Single Board Computers
a. Use as a System Component
b. Parallel 110 Options
c. Serial 1/0 Options
d. Interrupt System
e. Family Boards
Relocation and Linkage
a. ISIS-Ii LINK and LOCATE
Commands
b. Relocatable Libraries
c. Parameter Passing
d. System Design
MICROCOMPUTER TRAINING PROGRAMS
RMx-ao Real-time Multi-tasking Executive
System Workshop
This workshop will cover the concepts of multi-tasking, i.e., what a task is,
concurrency of tasks, asynchronous events, priorities and scheduling,
resource sharing, interrupts and inter-task communication. Also included will
be discussions on system design, writing tasks, system generation and
debugging.
COURSE OUTLINE:
Day 1
IntroductIon
a. Preview of Workshop
What I. RMXl80
a. Constiiuent Parts of the
RMX/SO Product
b. Overview of the RMX/SO
Development Process
Review 01 the Development Proeell
a. Intel S080/S085 Translators
1. Assembler
2. PL/M-SO Compiler
3. Translator DEBUG option
!In-Circuit Emulator)
b. ISI8-11 Commands
c. LINKing Task Modules with the
RMX/SO Nucleus and Intel
Provided Tasks
d. LOCATElng the Final Module in
an End Product Environment
ISingle Board Computer Modules)
e. Debugging the Task Environment
Real Time Asynchronous Event
Proees.'ng
a. Definition of Terminology
b. Recognition of Asynchronous
Events
1. Polling IStatus Loop)
2. Preemption !Interrupt)
c. The Single Unit Program
1. Status Environment
2. Interrupt Environment
d. Program Execution
1. Sequential Processing
2. Concurrent Processing
Day 2
RMX/SO Model
a. Task
1. Single Unit Program
b. Exchanges and Messages
1. SEND Function
2. WAIT Function
c. Context Switching and
Dispatching of Tasks
1. Task States
d. A Sequential Model
e. A Concurrent Model
f. The Interrupt Exchange/Message
1. Interrupt Levels
RMX/80 Terminal Handler
a. Message Formats
b. Service Request Exchanges
1. Terminal Input ILine Edited)
2. Terminal Output
c. Service Response Exchanges
Implementing an RMX Ta.kll'
Module
a. Translator INCLUDE option
b. Creating a Taskls) Module
c. RMX/SO System Creation
d. Configuration Module
e. System Generation
Laboratory
a. Implementation of Two Modules
Day 3
Laboratory
a. Implement Configuration Module
and System Generation
Use olin-Circuit Emulator
to Emulate Talk System
a. Hardware Considerations
Terminal Handler
a. Line Edit Input
b. Control Character Table
c. Alarm Exchange - Alarm
Message Type
d. DEBUGGER and Wakeup
Exchange
13-88
DEBUGGER Ta.k
a. Configuration
b. Invoking the DEBUGGER
c. DEBUGGER Commands
Oay4
RMX/80 Interrupt Procea.'ng
a. Interrupt Exchanges
b. Enabling and Disabling Interrupt
Levels
c. Software Priorities and Interrupt
Masking
d. SBC SO/10 User Required
Interrupt Services
1. Interrupt Poll Routines
2. Clock Control Routines
e. User Defined Interrupt Handling
Line Printer Driver Ta.k Example
a. Interrupt Handling
1. Usfng RMX/SO Model
2. User Defined Handler
Analog 110 Talk.
High Speed Math Unit T.....
Labor.tory
a. Interrupt Handling
Day 5
Disk File By.tem
a. Disk File System Services
1. File Access
3. File Seek
2. File ReadlWrite 4. Disk I/O
b. Add-on ISIS-II Services
1. File Attributes
2. Fi Ie Rename
3. File Delete
c. Configuration
1. Free Space Manager
2. Concurrent Operation
d. File System Structure
1. 01 rectory Format
2. File Data Format
L.boratory
a. Disk Flle.System
MICROCOMPUTER TRAINING PROGRAMS
MCS· 48™ System Workshop
This workshop will prepare the student to design and develop a system using
the Intel 8048 microprocessor through the use of lecture, demonstration and
laboratory "hands-on" experience with the Intellec® Development System,
PROMPT-48, and In-Circuit Emulator.
COURSE OUTLINE:
Day 1
Orientation
Introduction
a. Microprocessor System
1. Function
2. Organization
3. Programming
8048 Overview
1 Functional Sections
2. Programming Model
3. Execution Sequence
Assembly Language Instructions
a. 110 Instructions
b Data Move Instructions
c. Increment/Decrement Instructions
d. Branch Instructions
e. Worksession No.1
f. Accumulator Group Instructions
1. ADDIADDC
2. Logicals
PROMPT-48
a. Function
b. Operation
Laboratory Exercise
a. Program Entry and Execution
Using PROMPT -48
Day 2
Assembly Language Instructions
a. Accumulator Group Instructions
1. Flags
2. Rotates
b. Specials (XCH, DA, SWAP)
c. Worksession No.2
d. Subroutines
1. Invocation
2. Stack Operation
e. Interrupt System
1. Description
2. Service Subroutines
3. Multiple Source Systems
Development System
a. Function
b. Disk Operating System
Text Editor and Macro Assembler
a. Function
b. Operation
Laboratory Exercise
a. Bootstrap Procedures
b. Create, Edit, and Assemble
Source Program
c. Execute Program
Day 3
System Timing
a. Basic Timmg and Timer
b. Bus Timing for Peripheral Devices
Peripherals and Design
a Expanding Memory"
1 Program Memory (1, 2K ROMs)
2 Data Memory (RAMs)
Expanding Ports (8243)"
1 DeVice Characteristics
2. Software Control of Ports
c. Combination Chips*
1. 8155 RAM and 1/0 Chip
2. 8355, 8755 ROM and 1/0 Chip
d. Peripheral Interfacing (Parallel)"
1 8255 Parallel 1/0
2. 8279 Keyboard and Display
Interface
-Keyboard Scanning
Techniques
-Display Refresh
Laboratory Exercise
a. Edit and Assemble Using DOS
b. Execute Using PROMPT-48
Day 4
Peripherals and Design
a. Peripheral Interfacing (Serial)"
1. Transmission Formats
2. Asynchronous Operation
3. RS232C Interface
b. AID and DIA Interfacing"
1. SucceSSive
Approximation AID
2. AID, DIA Chips
3. AID Design
Laboratory Exercls.
a. Edit and Assemble Programs
b. Execute Programs
Day 5
8048 Family
a. 8041 Overview
1. 8041/8048 Difference
2. 8041 SlavelMaster Protocol
b. 8021 Overview
c. 8049 Overview
In-Circuit Emulator
•. Prototype Development
b. Resource Sharing
c. Commands
1. Mapping
2. Utility
3. Interrogation
4. Emulation
Laboratory
a. Use of the In-Circuit Emulator
for System Debugging
*Each section will consist of a design
example including schematic, bus
loading calculations, software, and
timing.
13-89
MICROCOMPUTER TRAINING PROGRAMS
PL/M-80 Language/Software Design Workshop
This workshop will prepare the student for designing, developing and
debugging modular PL/M-80 programs using lecture, demonstration, and
laboratory "hands-on" experience with the Intellec® Microcomputer
Development System and In-Circuit Emulator.
COURSE OUTLINE:
Day 1
Introduction
a. Preview of Course
b, Overview of PL/M, Linking and
Relocation
c, Why use a High Level Language
Definitions
Symbols, Identifiers, Reserved
Words, Comments, Data Elements,
Expressions, Statements,
Declarations
Data Elements
Variables, Subscripted Variables,
Data Type', Constants
Operators, Operations and Priorities
Arithmetic and Boolean
Evaluating Expressions
Statements
Redefine, Basic, Conditional
Assignment
a. Implement a Given Algorithm in
PL/M
Day 2
ISIS-II Disc Operating System
a, Components of System
ISIS-II File Structure
a, System Files
b, User Files
c. Device Files
d, Directory and File Attributes
ISIS-II Commands
a, CUSPS - Commonly Used
System Programs
b, Di rectory and Attribute
Commands
c. Rename and Delete Commands
d, Creating System and
User Discs
ISIS-II Editor
a, Definition of Terminology
b, Invoking the Editor
c. Editor Commands
d, Editing Existing Files
ISIS-II PL/M 80 Compiler
a Invoking PLIM
b, Compiler Options
ISIS-II Locate
a, Invoking Locate
Laboratory
a, IntrOduction to ISIS-II Disc
Operating System
b, Creating a PLiM Source File
c. Compiling a PL/M Program
d, Locating and Executing a PL/M
Program
Day 3
Review
Procedures
a DeclaratIOn
b. Invocation
c. Program Construction
Data Relerences
a, Based Variables
b, Variable Equivalencing
Statement Labels
Unconditional Tranal.ra
Blocks
a, Concept and Use
b, Scope 01 Declarations
c, Modular Compilation
d, Modular Program
ISI8-11 Link
a, Invoking Link
b, Link Options
c Assembly Object Modules
Laboratory
a, Compile Program Modules
b, Link and Locate Modules
c. Execute Program
13-90
Day 4
Review
ISIS-II Librarian
a, Creating a Library
b, Managing a Library
1, Adding Modules
2. Deleting Modules
ISIS-II System Interfaces
a, System Library
In-Circuit Emulator
a. Definition
b. System Overview
1, Memory and 1/0 Mapping
2, Breakpoint Capability
3. Dynamic Tracing
4, Control Block
In-Circuit Emulator Soltware Driver
a, Modes
b, Commands
System Debugging Examples
System Demonstration
Laboratory
a. Create a library
b, Link Object to a Library
c, Locate
d, Load and Emulate Using
In-Circuit Emulator
Day 5
Review
Interrupt Procedure.
Reentrant Procedures
Predeclared Procedures
a, TIME, MOVE, LENGTH, LAST and
SIZE Procedures
'
b, Type TranSfers
c, Shifts and Rotates
The Memory Array and STACKPTR
Variables
Discussion of Selected Programs
Laboratory
a, Execution and Debugging of
Selected Programs
INTEL MILITARY PRODUCTS
IC 38510 PROGRAM
In 1977, Intel qualified the first military microprocessor to JAN MI L-M-38510. The JAN version of
the 8080A, designated JM3851 0/420, is manufactured on Intel's DESC-certified production line.
Intel also offers other selected products for high reliability military applications. The in-house
IC38510 Program emulates the anticipated JAN processing and lot acceptance requirements and is
in full compliance with the testing and screening requ irements of M I L-M-3851 OD and M I L-STD-883B.
Intel Specifications are available which document general and detailed requirements for each of the
military products. Detail specifications are organized by generic family and provide all information
necessary for non-standard parts submissions in accordance with MIL-STD-749, Step I, Step II, and
Step 1.11. These documents are available from your local Intel Sales Office or authorized Intel
Distri butor.
Three levels of product assurance are offered: Level B, Level C, and Military Temperature Only.
The Military Temperature level products have guaranteed operating characteristics over the specified temperature range and have undergone Intel's rigid product assurance requirements.
Level B and Level C products are in conformance with M I L-STD-883, Method 5004 requirements,
and in addition, have a specified maximum rebond criteria (10%) and a specified burn-in PDA (10%),
all documented in the detail specifications, consistent with 38510 requirements. Lot conformance
tests are performed in accordance with M I L-STD-883, Method 5005.
INTEL MILITARY PRODUCTS
MCS-80™
3000 Series
PROMs
RAMs
M8080A
M8212
M8214
M8216
M8224
M8226
M8228
M8251
M8255A
M3001
M3002
M3003
M1702A
M2708
M2716*
M3604A
M3624A
M2111A
M2102A-4
M2114*
M2115A
M2115AL
M2125A
M2125AL
M2147*
M5101L-4
"New Product to be released by mid-year 1978. Contact Intel representative for details.
14-2
LEVEL BAND C
MILITARY PRODUCTS MANUFACTURING FLOW
/ } - - - - Incoming QC Raw Material Inspection
I } - - - - Incoming QC Silicon Wafer Inspection
Wafers
>----
Optical Inspections
Wafer Fabrication
Contamination Checks
Part iels Co u nts
/ } - - - - Optical Inspection
Critical 0 imensions
Wafer Sort
QA Wafer Inspection
and Die Count
Scr ibe and Brea k
} - - - - 01 Water Die Clean
V } - - - - Post Break Chip Inspection MIL-STD-883B. Method 2010/B
QA Post Break Chip
Inspection. MIL-STD883B. Method 2010/B
Lead Frame
and Base
Lead Fra me Attach
v:}----
Visual Inspection for Alignment
and Glass Flow
} - - - - Di. Attach: Jumper Chip Attach
Visual Inspection of
Die Attached Units.
Monitor of Die Attach
Machines.
r - - - - A luminum Ultrasonic Wire Bond
Die Attach and Bond Inspection
Bond Pull Acceptance to
Monitor Bond Strengths per
MIL-STD-883B. Method 2011
C/lf---- per MIL-STD-883B. Method 2010/B
QA Die Attach and Bond
I nspection per M I L-STD-883B.
Method 2010 Condition B
AQL = 1%
Cap
Cap Seal
QA S.al Monitor. Cap
Alignment and Glass Flow
!-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Stabilization Bake.
150° C. 24 Hours
}-_ _ _ Temperature Cycle. per MIL-STD-883B.
Method 1010 Condition C.
Centrifuge. per MIL-STD 883B. Method
r - - - - 2001. Condition E. Y, Axis
v:}---- Hermeticity Testing:
Fine Leak - Helium
or Kr 85 to 5x 10-8 cc/sec_
Gross Leak - Fluoroc..rbon,
Condition C2. 100% MIL-STD883B. Method 1014
} - - - - Tin Plate
QA Tin Thickness Monitor
Thickness Spec 20-700
Microinches
} - - - - Trim Tie Bar
Hermeticlty Lot Acceptance
AQL = 1%
14-3
LEVEL BAND C
MILITARY PRODUCTS MANUFACTURING FLOW (Cont'd)
Final Visual - Package, Seal Date Code,
Country of Origin, and
Lead Inspection
Final Visual Lot
Acceptance, AQL
I----------------------LJ
= 1%
Plant Outgoing Inspection*
Mark, Tube Load and Opens and Shorts
Testing
Ship to USA
Stabilization Bake - 150" C, 24 Hours
Incoming Inspection of
Foreign Assembly Plant
Shipments**. LTPD
Dependent Upon Test
v}----
25" C Interim Electrical Tests, Level
B Products Only per MIL-STD-883B
Burn-In (Level B Products Only) per
MIL-STD-883B, Method 1015, Condition
Cor F
100% Electrical Tests at 25°C
(AC, DC, Function)
V)-----
100% Electrical Test at _55°C
(AC, DC, Function) Level B Product Only
r/~___ 100% Electrical Tests at +125Q C
(AC, DC, Function) Level B Product Only
Final QA Visual and Electrical
Tests at 25°C, -SSoC, and 125Q C
Mark Customer Number
1 - - - - - - , - - - - - - - - - - - - - - - - i 1 L TPD = 5 (AC, DC and Function)
(-SSoC and +125°C Testing On
Levels Band C Product Only)
1------------------------10
Group B Tests Performed per
MIL-STD-883B, Method S005,
for Lot Conformance. (Levels
Band COnly)
1 - - - - - - - - - - - - - - - - - - - - - - - - 1O
Group C and 0 Tests Performed
per MIL-STD-883B, Method S005,
for Lot Conformance. (Levels B
and COnly)
Ship to Customer
o
525
*Outgoing Acceptance (Plant Clearance) Inspet.'1ions:
~
~
1. Hermeticity
5
2
2. Centrifuge
5
2
3. X-Ray
7
Test
4. Lead Fatigue
6_
6. QA MONITOR
MANUFACTURING OPERATION
MANUFACTURING INSPECTION OR TEST
20
o
QA LOT ACCEPTANCE
**Incoming Inspection Testing:
!!!!
7
2. External Visual
7
3.
0
LTPD
1. X-Ray, Die Attach and
Seal Quality
o pens and Shorts
7
7
4. Hermeticity
Acoustic (Loose Particles) AQL = .04%
14-4
5. Lead Fatigue
20
o
6. Internal Visual
10
o
7. Bond Pull
7
8. Acoustic (1000 Particles) AQL
= .04%
3065 Bowers Avenue
Santa Clara. California 95051
T.I: (408) 987-8080 "
TWX 910-338-002ti
TElEX 34-6372
u.s.
u.s.
AND CANADIAN DISTRIBUTORS
AND CANADIAN DISTRIBUTORS
ALABAMA
' " Hamilton/ Avnel Electronics
8050serDriveNW
HuntSVille 35805
Tel: (205) 533-1170
Pioneer
1207 Putman Drive NW
Huntsville 35805
Tel. (205) 837-9300
ARIZONA
f ' Hamilton/ Avnet Electronics
8155 North 21st Street
PhoeniX 85021
Tel: (602) 275-7851
Liberty/ Ar izona
3130 N. 27th Avenue
PhoeniX 85017
TeL (602) 257-1272
TELEX: 910-951-4282
CALIFORNIA
, "Avnet Electronics
350 McCormick Avenue
Costa Mesa 92626
Tel. (714) 754-6111
Tel. (213) 558-2345
t " Hamillon/ Avnet Electronics
575 E. Middlefield Road
Mounlalfl View 94040
Tel: (415) 961-8600
t ' Hamllton/ Avnet ElectroniCS
8917 Complex Drive
San Die9092 123
Tel 1714) 279-2421
t 'Hamllton Electro Sales
10912 W. Washington Boulevard
Culver City 90230
Tel. (213) 558-212 1
ICramer/San Francisco
720 Palomar Avenue
Sunnyvale 94086
Tel. (408) 739-3011
Cramer / Los Angeles
17201 Daimler Street
Irvlfle9271 4
Tel (71 4) 979-3000
I Liberty Electronics
124 Maryland Street
EI Segundo 90245
Tel: (213)322-8 100
Tel: (7 14)638·7601
TWX 910-348-7140
t L lberty San Diego
8284 Mercury Court
San Diego 92111
Tel: (71 4)565-9171
TELEX: 910-335-1590
,Elmar ElectronicS
2288 Charleston Road
Mounlain View 940 40
Tel: (415) 961·3611
TElEX. 910·379~437
COLORADO
t Elmar/Denver
6777 E. 50th Avenu e
Commerce City 80022
Tel (303) 287-9611
TWX; 910-936-0770
" Hamllton/ Avnet ElectroniCS
5921 No. Broadway
Denver 80216
Tel (3031 545-1212
CONNECTICUT
t Cramer Connecticut
35 Dodge Avenue
North Haven 06473
Tel (203) 239·5641
I " Hamllton/ Avnel ElectrOnics
643 Danbury Road
Georgetown 06829
Tel (203)762-0361
Harvey Electronics
112 Main Street
Norwalk 06851
Tel: (203J853-15 15
FLORID ....
Cramer/E.W. Hollywood
4035 No. 29th Avenue
Hollywood 33020
Tel (305) 921-7878
, 'Hamllton /Avne1 Electronics
6800 NOr!hwest 20th Ave.
Ft Lauderdale 33309
Tel: (305) 971-2900
Cramer/EW Orlando
345 No. Graham Ave.
Orlando 3281 4
Tel . (305)89 4·1511
Pioneer
6220 S. Orange Blossom Trail
SUite 412
Orlando 32809
Tel (305) 859-3600
GEORGIA
t Cramer
6456 Warren Drive
Norcross 30071
Tel (404) 448-9OSO
•• Note New Telephone Number
GEORGIA (cont.)
, 'Hamllton Avnet ElecironlCS
6700185. Access Road. i l l
Norcross 30071
rei (404) 448-0800
ILLINOIS
Cramer Chicago
1911 So. BusseRd
Mt. Prospect 60056
TeL (312)593-8230
I ' Hamilton/ Avnet Electronics
3901 No. 25th Ave.
Schiller Park 60176
Tel. (312) 678-6310
PIoneer / Chicago
1551 Carmen Drive
Elk Grove Village 60006
Tel. (312) 437-9680
INDIANA
,Pioneer/ IndIana
6408 Caslleplace Dri ve
Indianapolis 46250
Tel (317)849-7300
Sheridan Sales
8790 Purdue Road
Indianapohs46268
Tel: (317)297·3146
K.... NSAS
" Hamillon/ Avnel Electronics
37 Lenexa Industrial Center
9900 Pllumm Road ;37
Lenexa 66215
TeL (9t3) 888·8900
MARYL .... ND
t Hamlllon/ Avnet
Box 8647, BWI Airpori
Baltimore 21240
!Cramer/EW Washington
16021 Industrial Drive
Gaithersburg 20760
Tel (301)948-0110
- HamillonAvnet
7235 Standafd Drive
Hanover 21076
TeL (301) 796·5000
t P,oneer Washington
9100 Gaither Road
Gaithersburg 20760
Tel (301) 948-0710
TWX 710-828-0545
MASS ACHUSETTS
ICramer Eleclronlcs Inc.
85 Wells Avenue
Newton 02159
Tel (617) 969-7700
·Hamllton. AVllet Eillctronics
100 E. Commerce Way
Woburn 01801
Tel : (617)933·8000
MICHIG .... N
ISheridan Sales Co.
245431ndoplex Circle
Farmington Hills 48024
Tel (313) 477-3800
fPioneer/Michlgan
13485Stamlord
Livonia 48150
Tel. (3131525-1800
, " Hamllton/ Avnet Electronics
32487 Schoolcraft Road
Uvonla48150
Tel (313) 522-4700
TWX. 810·242·8775
MINNESOT....
flndus lflal Components
5280 West 74th Street
MIflneapolis55435
Tel (612) 831-2666
Cramer/ Bonn
7275 Bush lake Road
Edlfla 55435
Tel. (6t2) 835-7811
t 'Hamilton / Avnet Etectronics
7683 Washington Avenue So.
Edina 55 435
Tel. (612) 941·3801
MISSOURI
t " Hamllton/ Avnet Electronics
396 Brookes Lane
Hazelwooct63042
Tel. (314) 731-11 44
Sheridan Sales
110 S. Hwy. 67. Suite 10
Florissant 63031
Tel. (31 4) 837-5200
NEW JERSEY
Cramer/Pennsylvania. Inc.
12 Spflngda le Road
Cherry HIli Industrial Center
Cherry Hill 08034
Tel: (609)424-5993
TWX 710"896-0908
t " Hamllton/ Avnet ElectronicS
218 Lillie Falls Road
Cedar Grove 07009
Tel (201) 239-0800
TWX 710-994·5787
NEW J ERSEY (conI.)
Cramer/Now Jersey
1 Cardrnal Drive
UttieFalls07424
Tel (201) 785-4300
Harvey ElectroniCS
389 Passaic Avenue
Fairfield 07006
Tel: (20t) 227-1262
t "Hamlllon·Avnet Electronics
113 Gailnar Drive
East Gate Industrial Park
Mt.Laufe108051
Tel (609) 234·2133
TWX ' 710-897-1 405
NEW MEXICO
"Hamllton/ Avnet EleclrOfllcs
2524 Baylor Oflve. S.E.
Albuquerque 87119
Tel (505) 765-1500
NEW YORK
Cramer; Rochester
3000 Winton Road South
Rochester 14623
Tel (716) 275-0300
t • Hamilton, Avnet ElectroniCS
t67Clay Road
Rochester 14623
Tel. (716)442-7820
Cramer/ Syracuse
6716Joy Road
East Syracuse 13057
Tel. (315J437-667t
, " Hamillon/ Avnet Electronics
6500 Joy Road
E. Syracuse 13057
Tel (315) 437·2641
Cramer Long Island
129 Oser Avenue
H6uppauge. 1.I. 11787
Tel (516) 231-5600
TWX 510-227-9863
f ' Hamilton/ Avnet ElectronICs
70 Stale Street
W(.Stbury. U 11590
Tel. (516) 333-5800
TWX 510-222-8237
Harvey ElectroniCS
60 Crossways Park West
WOOdbury 11797
Tel (516) 921·8700
NORTH CAROllN ....
Cramer ElectrOnics
938 Burke Street
Winston-Salem 27102
Tel. (919)725-8711
Pioneer/ Carolina
2906 BaltiC Avenue
Greensboro 27406
Tel (919)273- 4441
TWX 510-925-1114
Hamilton/ Avnel Electronics. Inc.
2803 Industrial Dflve
Raleigh 27609
Tel' (9 19)829-8030
OHIO
t Shendan Sales Co.
2SO' Nell Road
Dayton 45414
Cramer / Cleveland
5835 Harper Road
Cleveland 44139
Tel (216) 248 -8400
t · Hamilton/ Avnet ElectroniCS
118 Westpark Road
Dayton 45459
Tel. (513) 433-0610
TWX 810-450-2531
fP,oneer/ Dayton
1900 Troy Street
Dayton 45404
Tel. (513) 236-9900
fShendan Sales Co.
10 Knollcrest Drive
Crnclnnal145222
Tel: (513) 761-5432
TWX 810-461-2670
I Pioneer/Cleveland
4800 E. 131s1 Streel
Cleveland 44105
Tel: (216) 587-3600
I ' Hamilton/ Avnet Electronics
761 Beta Drive. Suite E
Cleveland 441 43
Tel. (216)461-1400
I Sheridan Sales Co.
23224 Commerce Pafk Road
Beachwood 44122
Tel: (2 16)831-0130
DKLAHOM ....
, Components SpeCialties. Inc .
7920 E. 40th Street
Tulsa 74145
Tel. (918) 664-2820
OREGON
Almac/ Stroum Electronics
4475 S.W. Scholls Ferry Rd.
Portland 97225
Tel (S03) 292-3534
PENNSYLVANI ....
' Shendan Sales Co.
1717 Penn Avenue. SUite 5009
Pittsburgh 15221
Tel : (412) 244·1640
PENNSYLVANI .... (conI.)
Pioneer/ Pittsburgh
560 Alpha Drive
Plltsburgh 15238
Tel (412) 782-2300
Pioneer / Delaware
141 Gibraltar Road
Horsham t9044
Tel (215) 674-4000
TWX: 510-665-6778
TEXAS
Component SpecialtIes Inc.
8330 Burnell Road. SUite 101
Austin 78758
Tel ( 512) 459-3308
, Cramer Etectrofllcs
13740 Midway Road
Dallas 75240
Tel: (21 4) 661-9300
, ' Hamilton/ Avnet Electronics
4445 Sigma Road
Dallas 752 40
Tel. (214) 661-8661
I 'Hamtllon/ Avnet ElecHonics
3939 Ann Arbor
Houston 77063
Tel. (713) 780-177 1
fComponenl SpeCialties. Inc.
10907 Shady Trail, SUite 101
Dallas 75220
Tel:(214)357~511
IComponent Specialties. Inc.
8585 Commerce Park Dflve. Suite 590
Houston 77036
Tel: (7 13) 771·7237
UTAH
I 'Ham liton / Avne i Electronics
1585 West 2100 South
Salt Lake City, 84119
Tel. (801) 972-2800
WASHINGTON
l 'Hamlllon / Avnet ElectronIcs
13407 NorlhrupWay
Bellevue 98005
Tel (206) 746-87SO
fAlmac/Stro um Electronics
5811 SIxth Ave. South
Sea1tte98108
Tel (206) 763-2300
t Llberty Electrofllcs
1750 132nd Avenue NE
Bellevue 98005
Tel (206)163-8200
WISC ONSIN
'Hamllton / Av net
2975 Moorland Road
New Berlin 53151
Tel: (414) 784-4510
CANADA
ALBERTA
tl. A. Varah lid
4742 141h Street N.E.
Calgary T2E 6l T
Tel (403) 276-8818
Tele~ 138258977
BRiTISH COLUMBI ....
fLA Varah Ltd.
2077 Alberta Street
Vancouver V5Y lC4
Tel. (604)873-3211
TWX . 610-929-1068
Telex; 04 53167
ONTARIO
l.A Varah.lId
S05 Kenora Avenue
Hamilton L8E-3P2
Tel: (4 16) 561-9311
TELEX 061-8349
"Hamllton / Avnet Electronics
3688 Nashua Olive. Unit GH
MisSlssauga l4VIMS
Tel. (416) 677-7432
TWX 610·492·8867
• Hamilton/ Avnet Electronics
1735 Court wood Cresc
Ollawa K2C 3J2
Tel (613) 226-1700
TWX 610 562·1906
tZenlronics
14\ Catherme Street
Ottawa. Ontario K2P lC3
Tel: (6 13)238-6411
tlentronics
99 Norlinch Dt .
Downsview. OntariO M3N lW8
Tel (416) 635-2822
Telex : 02-021694
QUEBEC
"Hamllton/ Avnet Electronics
2670 Pau lus
St. LaurentH4S lG2
Tel (51 4 )33 1~443
TWX 610-421-3731
Zentronics
8146 Montvlew Road
Town 01 Mount Royal. Montreal
Ouebec H4P 2L7
Tel (51 4) 735-5361
Telex: 05-827535
! Microcompute r System Technical Demonstrator Cen ters
• Microcompuler System Spares Order Poin t
INTEL COR PORATION , 3065 Bowers Avenue, Santa Clara. CA 95051 (408) 987·8080
Printed in U.S.A./CI17 / 02 7B/95K CP
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