1978_Motorola_MECL 1978 Motorola MECL

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GENERAL
INFORMATION

•

SELECTOR
GUIDES

•

MECL 10,000
Series

•

MECl III
MC1600 Series

•

MI0800 PROCESSOR
FAMILY

•

PHASE-LOCKED
LOOP COMPONENTS

II

®

MOTOROLA

MECL INTEIGRATED CIRCUITS
Prepared by
Technical Information Center

This book presents technical data for a broad line of MECL integrated circuits.
Complete specifications for the individual circuits are provided in the form of data
sheets. In addition, selector guides are included to simplify the task of choosing the best
combination of circuits for optimum system architecture.
The information in this book has been carefully checked and is believed to be reliable;
however, no responsibility is assumed for inaccuracies. Furthermore, this information
does not convey to the purchaser of microelectronic devices any license under the patent
right of any manufacturer.

Printed in U.S.A.

Series 8
Third Printing
©MOTOROLA INC., 1978
Previous Edition © 1974
"All Rights Reserved"

MECL, MECL I, MECL II, MECL III, MECL 10,000, MTTL,
and

au I L are trademarks of Motorola

Inc.

CONTENTS
Page
DEVICE INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . .. ii

,.,

CHAPTER 1 - GENERAL INFORMATION
High·Speed Logics
'·2
MECL Products/General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . '·2
MECL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,-4
Basic Considerations for High·Speed Logic Design . . . . . . . . . . . . . . . . . . . . '·4
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·6
Definitions of Letter Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . '·6
Technical Data ........................ .................... . '·9
General Characteristics and Specifications
'·9
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·9
MECL Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·9·
DC Test Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ,."
Noise Margin . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·'2
AC/Switching Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·'3
Testing MECL '0,000 and MECL III . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·'5
Operational Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. '·'7
Power Su pply Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. '·'7
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' · ' 7
Loadi ng Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . .. '·'8
Unused MECL Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Design Considerations
'·20
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ·20
Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·2'
Thermal Effects on Noise Margin
'·22
Mounting and Heat Sink Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ·22
Interfacing MECL to Slower Logic Types . . . . . . . . . . . . . . , . . . . . . . . . . . '·23
Circuit Interconnections
'·23
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '·26
Logic Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . , ·26
Summary of Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. , ·27
Package Outline Dimensions . . . . . . . . . . . . . . . . . . . . ',' . . . . . . . . . . . . . . . . '·28
Supplementary Literature and Application Notes . . . . . . . . . . . . . . . . . . . . . . . . '·3'
/'

'·'9

CHAPTER 2 - SELECTOR GUIDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MECL '0,000 Series
..........................................
MI L·M·385'0 JAN Qualified MECL Devices
..........................
MECLIIIMC'600Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2·'

2·2
2-4
2·5

CHAPTER 3 - MECL 10,000 SERIES DATA SHEETS . . . . . . . . . . . . . . . . . . . . . . . . 3·'
CHAPTER 4 - MECL III MC1600 SERIES DATA SHEETS
CHAPTER 5 - MIOSOO PROCESSOR FAMILY

4·'

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5·'

CHAPTER 6 - PHASE·LOCKED LOOP COMPONENTS

.... , . . . . . . . . . . . . . . . . . 6·'

DEVICE INDEX

Device
Number

Function

Page

MC1648/MC1648M
MC1650/MC1651
MC1654
MC1658
MC1660

Voltage-Controlled Oscillator
Dual A/D Converter . . . . . .
Binary Counter . . . . . . . .
Voltage-Controlled Multivibrator
Dual 4-lnput Gate . . . .

MC1662
MC1664
MC1666
MC1668
MC1670

Quad 2-lnput NOR Gate
Quad 2-'lnput OR Gate ..
Dual Clocked R-S Flip-Flop
Dual Clocked Latch ..
Master-Slave Flip-Flop . . .

4-27
4-28
4-29
4-30
4-31

MC1672
MC1674
MC1678
MC1688
MC1690

Triple 2-lnput Exclusive-OR Gate ..
Triple 2-lnput Exclusive-NOR Gate
Bi-Quinary Counter . . . . . . . .
Dual 4-5-lnput OR/NOR Gate ..
UHF Prescaler Type D Flip-Flop

4-34
4-35
4-36
4-38
4-39

MC1692
MC1694
MC1697
MC1699

Quad Line Receiver . . . . . . . .
4-Bit Shift Register . . . . . . . .
1-GHz DiVide-by-Four Prescaler
Divide-by-Four Gigahertz Counter

4-41
4-43
4-44
4-47

MC10100/MC10500
MC1 01 01 /MC1 0501
MC1 01 02/MC1 0502
MC1 0103/MC1 0503
MC1 01 04/MC1 0504

Quad
Quad
Quad
Quad
Quad

MC10105/MC10505
MC1 01 06/MC1 0506
MC1 01 07 /MC1 0507
MC10109/MC10509
MC10110

Triple 2-3-2 input OR/NOR Gate ..
Triple 4-3-3 Input NOR Gate . . . .
Triple 2-lnput Exclusive OR/Exclusive NOR ..
Dual 4-5 Input OR/NOR Gate . . .
Dual 3-lnput 3-0utput OR Gate .

MC.10111
MC10113/MC10513
MC10114/MC10514
MC1 0115/MC1 0515
MC10116/MC10516

Dual 3-lnput 3-0utput NOR .Gate
Quad Exclusive OR Gate
Triple Line Receiver
Quad line Receiver ..
Triple Line Receiver ..

3-9
3-10
3-11
3-13
3-13

MC10117/MC10517
MC10118/MC10518
MC10119/MC10519
MC1 0121 /MC1 0521
MC10123

Dual 2-Wide 2-3-lnput OR-AND/OR-AND-INVERT Gate ..
Dual 2-Wide 3-lnput OR-AND Gate . . . . . . . . . . . . . .
4-WIDE 4-3-3-3-lnput OR-AND Gate. . .
. ...... .
4-Wide OR-AND/OR-AND-INVERT
Triple 4-3-3-lnput Bus Driver . . . .

3-14
3-15
3-16
3-17
3-18

MC1 0124/MC1 0524
MC10125/MC10525
MC10128
MC10129
MC1 0130/MC1 0530

Quad TTL-to-MECL Translator . . . . . . . . .
Quad MECL-to-TTL Translator . . . . . . . . .
Dual Bus Dr.iver (MECL 10,000 to TTL/IBM)
Quad Bus Receiver (TTL/I BM to MECL 10,000)
Dual Latch . . . . . . . . . . . . . . . . . . . . . .

3-19
3-21
3-24
3-30
3-34

MC10131/MC10531
MC1 0132/MC1 0532
MC 10133/MC 10533
MC10134/MC10534
MC10135/MC10535

Dual Type D Master-Slave Flip-Flop . . . . . . . .
Dual Multiplexer with Latch and Common Reset
Quad Latch . . . . . . . . . . . .
Dual Multiplexer with Latch ..
Dual J-K Master-Slave Flip-Flop

3-35
3-37
3-39
3-40
3-41

2-lnput NOR Gate with Strobe . . . . . . . . . .
OR/NOR Gate
............ .
2-lnput NOR Gate
..... .
2-lnput OR Gate ..
2-lnput AND Gate . . .

ii

.. 4·2
4·10
4-20
4-22
4-26

3-2
3-3
3-3
3-4
3-5
3-6
3-6
3-7
3-8
3-9

DEVICE INDEX (continued)
Device
Number
MC1 0136/MC1 0536
MC10137/MC10537
MC1 0138/MC1 0538
MCM10139i
MCM10539
MC10141/MC10541
MCM10143
MCM10144/
MCM10544
MCM10145/
MCM10545
MCM10146/
MCM10546
MCM10147/
MCM10547
MCM10148/
MCM10548
MCM10149/
MCM10549
MCM10152/
MCM10552
MC1 0153/MC1 0553
MC10158/MC)0558

Function

Page
3-42
3·47
3-51

Universal Hexadecimal Counter
Universal Decade Counter
Bi-Quinary Counter . . . . . . . .

3-133

32 x 8-Bit Programmable Read-Only Memory

. 3-53
3-137

4-Bit Universal Shift Register . . . . . . . . . .
8 x 2 Multiport Register File (RAM) . . . .
256 x 1-Bit Random Access Memory ..

3-142

16 x 4-Bit Register File (RAM)·

3-144

1024 x 1-Bit Random Access Memory

3·146

126 x 1-Bit Random Access Memory

3-148

..... .

3-150

256 x 4-Bit Programmable Read-Only Memory

3·152

256 x 1-Bit Random Access Memory . . . .
Quad Latch (Negative Clock) . . . . . . . .
Quad 2-lnput Multiplexer (Non-Inverting)

3-156
3-55
3-56 .

64 x 1-Bit Random Access Memory

MC10159/MC10559
MC10160/MC10560
MC10161/MC10561
MC1 0162/MC1 0562
MC1 0163/MC1 0563

Quad 2-1 nput Multiplexer (I nverting) ..
12-Bit Parity Generator/Checker . . . .
Binary to 1-8 Line Decoder (Low)
..... .
Binary to 1-8 Line Decoder (High)
..... .
Error Detection/Correction Circuit (IBM Pattern)

3-57
3-58
3-59
3-61
3-62

MC10164/MC10564
MC10165/MC10565
MC1 0166/MC1 0566
I\!IC10168/MC10568
MC1 0170/MC1 0570

8-Line Multiplexer . . . . . . . . .
8-1 nput Priority Encoder . . . . .
5-Bit Magnitude Comparator .. .
Quad Latch (Common Clock) . . . . . . . .
9 + 2-B it Parity Checker

3-68
3-70
3-73
3-75
3-76

MC1 0171/MC1 0571
MC1 0172/MC1 0572
MC10173
MC10174/MC10574
MC10175/MC10575

Dual 4-Line Decoder (Low)
........... .
Dual 4-Line Decoder (High)
........... .
Quad 2-lnput Multiplexer/Latch . . . . . .
Dual 4-to-1 Multiplexer . . . . . . . . . . . . .
Quint Latch . . . . . . . . . . . . . . . . .

MC10176/MC10576
MC10177
MC10178/MC10578
MC10179/MC10579
MC1 0180/MC 10580

Hex D Master-Slave Flip-Flop . . . . . . .
Triple MECL-to-MOS Translator (N-Channel)
Binary Counter . . . . . . . . . . . .
Look Ahead Carry Block . . . . . . . . . . . .
Dual 2-Bit Adder/Subtractor . . . . . . . . . .

MC1 0181/MC1 0581
MC1 0182/MC1 0582
MC10183
MC1 0186/MC1 0586
MC10188

4-Bit Arithmetic
2-Bit Arithmetic
4 x 2 Multiplier
Hex D Flip-Flop
Hex Buffer with

MC10189
MC1 0190/MC1 0590
MC1 0191/MC1 0591
MC1 0193/MC1 0593
MC1 0194/MC1 0594

Hex Inverter with Enable
Quad MST-to·MECL Translator
Hex MECL-to-MST Translator . . . . . . .
Error Detection/Correction Circuit (Motorola Pattern) . . . .
Dual Simultaneous Bus Transceiver

3'77
3-78
. ..3-79
3·80
3·81
3-82
3-83
3·86
3-88
3-90

Logic Unit and Function Generator . . . . . . . . . . .
Logic Unit and Function Generator . . . . . . . . . . . . .
................................... .
with Common Reset
................... .
Enable. .
. ..... .

iii

3-92
3-95
3-98
3-103
3·105

3·106
3-107
3-109
. 3-62
. . . . 3·111

DEVICE INDEX (continued)
Device
Number

Function

MC10195/MC10595
MC1 0197/MC1 0597
MC10198
MC10210/MC10610
MC1 0211/MC1 0611

Hex Inverter/Buffer . . . . . .
Hex AND Gate . . . . . . . . . . . .
Monostable Multivibrator . . . . . . . . . . . .
High-Speed Dual 3-lnput/3-0utput OR Gate
High-Speed Dual 3-lnput/3-0utput NOR Gate

MC10212/MC10612
MC10216/MC10616
MC10231/MC10631
MC10287/MC10687
MCM10139/
MCM10539

High-Speed
High-Speed
High-Speed
High-Speed

MCM10143
MCM10144/
MCM10544
MCM10145/
MCM10545
MCM10146/
MCM10546
MCM10147/
, MCM10547
MCM10148/
MCM10548
MCM10149/
MCM10549
MCM10152/
MCM10552

32

X

Dual 3-lnput/3-0utput OR/NOR Gate . . . . . .
Triple Line Receiver . . . . . . . . . . . . . . . .
Dual D Master-Slave Flip-Flop . . . . . . . . . . .
2-Bit Multiplier
.................. .

8-Bit Programmable Read-Only Memory

Page
3-115
3-116
3-117
3-123
3-123
3-124
3-125
3-126
3-127
3-133

8 x 2 Multiport Register File (RAM) ..

3-137

256 x 1-Bit Random Access Memory.

3-142

16

3-144

X

4-Bit Register File (RAM).. ' . . .

1024

X

1-Bit Random Access Memory

3-146

126 x 1-Bit Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148

..... .

3-150

4-Bit Programmable Read-Only Memory

3-152

256 x 1-Bit Random Access Memory . . . . . .

3-156

64

X

256

1-Bit Random Access Memory
X

iv

GENERAL
INFORMATION

•

•

GENERAL INFORMATION
SECTION I

~

HIGH-SPEED LOGICS

High speed logic is used whenever improved
system performance would increase a product's
market value. For a given system design, highspeed logic is the most direct way to improve
system performance and emitter-coupled logic
(ECL) is today's fastest form of digital logic.
Emitter-coupled logic offers both the logic speed
and logic features to meet the market demands for
higher performance systems.

An important feature of MECL 10,000 IS Its
compatibility with MECL III to facilitate using
both families in the same system. A second important feature is its sign ificant power economy MECL 10,000 gates use less than one-half the
power of MECL III. Finally, low gate power and
advanced circuit design techniques have permitted
a new level of complexity for MECL 10,000 circuits. For example, the complexity of the MC10803
Memory Interface Function compares favorably to
that of any bipolar integrated circuit on the market.
The basic MECL 10,000 Series has been expanded by a subset of devices with even greater
speed. This additional series provides a selection
of MECL 10,000 logic functions with flip-flop
repetition rates up to 200 MHz min. The MECL
10,200 Series is meant for use in critical timing
chains, and for clock distribution circuits. MECL
10,200 parts are otherwise identical to their
10,000 Series counterparts (subtract 100 from
the MECL, 10,200 part number to obtain the
equivalent standard MECL 10,000 part number).
Continuing technical adva,nces led more recently to the development of the M10800 LSI processor family. The M10800 family combines the
performance of ECL with the system advantages
of LSI density. Architectural features of the
M10800 family significantly reduce the component
count of a high-performance processor system. The
M10800 LSI family is fully compatible with the
MECL 10,000 and MECL III logic families for a
complete selection of system design components.

MECL PRODUCTS
Motorola introduced the original monolithic
emitter-coupled logic family with MECL I (1962)
and followed this with MECL II (1966). These two
families are now obsolete and have given way to
the MECL III (MC1600 series), MECL 10,000,
MECL 10800, and PLL (MC12000 series) families.
Chronologically the third family introduced,
MECL III (1968) is a higher power, higher speed
logic. Typical 1 ns edge speeds and propagation
delays along with greater than 500 MHz flip-flop
toggle rates, make MECL III useful for high-speed
test and communications equipment. Also, this
family is used in the high-speed sections and
critical timing delays of larger systems. For more
general purpose applications, however, trends in
large high-speed systems showed the need for an
easy-to-use logic family with propagation delays
on the order of 2 ns. To match this requirement,
the MECL 10,000 Series was introduced in 1971.

MECL FAMILY COMPARISONS
MECL 10,000
Feature
1.
2.
3.
4.
5.

Gate Propagation Delay
Output Edge Speed
Flip-Flop Toggle Speed
Gate Power
Speed Power Product

10,100 Series
10,500 Series

10,200 Series
10,600 Series

10,800 LSI*

MECL III

2 ns
3.5 ns
160 MHz
25mW
50 pJ

1.5 ns.
2.5 ns
250 MHz
25 mW
37 pJ

1-2.5ns
3.5 ns
N.A.
2.3 mW
4.6 pJ

1 ns
1 ns
300-500 MHz
60 mW
60 pJ

'Average for Equivalent LSI Gate.
FIGURE 1a - GENERAL CHARACTERISTICS

1-2

Ambient
Temperature Range

dO

to 75°C

-3DPC to

+85 0

C

_55°C to 125°C

MECL 10,000

Ml0800

MECL III

PLL

MCM 1 01 DO Series

-

MC1697P

MC12DDD Series

MC1D1DD Series
MC1D2DD Series

MC1D8DD Series

MC16DD Series

MC 12000 Series

MC 1 0500 Series
MC10600 Series
MCM 10500 Series

-

MC1648M

MC125DD Series

FIGURE lb - OPERATING TEMPERATURE RANGE

MECL 10,000

Ml0800

MECL III

PLL

MCl 01 DDP Series
MC102DOP Series

-

MC1658P

MC12000P Series

16-Pin Ceramic DIP

MC10l00L Series
MC10200L Series
MC10500L Series
MCl 06DOL Series
MCM 10100L Series
MCM10500LSeries

MC10804L
MC10807L

MC1600L Series

MC12DDOL Series
MC12500L Series

16-P in Flat Package

MC1D500F Series
MC1D60DF Series
MCM10500F Series

-

MC1600F Series

MC12513F

-

MC10805L

Package Style
16-Pin Plastic DIP

20-Pin Ceramic DIP
24-Pin Plastic Package

MC10181P

24-Pin Ceramic DIP

MC10181 L,
MC10581 L

-

MC1D802L

-

-

-

-

-

24-Pin Flat Package

MC10581 F

-

MC 1 OaOOL Series

-

-

48-Pin Ceramic Quil
14-Pin Plastic DIP

-

-

MC1648P

MC12DOOP
MC12D02P
MC1202DP
MC1204DP

14-Pin Ceramic DIP

-

-

MC1648L

MC1200DL
MC12D02L
MC12020L
MC12040L

14-Pin Flat Package

-

-

MC1648F

MC12540F

-

MC1697P

8-Pin Plastic DIP

-

-

-

For package information see page 1-28.
FIGURE lc - PACKAGE STYLES

MECL IN PERSPECTIVE
Complementary Outputs cause a function and
its complement to appear simultaneouslY at the
device outputs, without the use of external inverters. It reduces package count by eliminating
the need for associated invert functions and, at the
same time, cuts system power requirements and
reduces timing differential problems arising from
the time delays introduced by inverters.

In evaluating any logic line, speed and power
requirements are the obvious primary considerations. Figure 1 provides the basic parameters of the
MECL 10,000, Ml0800, and MECL III families.
But these provide only the start of any comparative analysis, as there are a number of other important features that make MECL highly desirable for
system implementation. Among these:

1-3

•

•

High Input Impedance and Low Output Impedance, permit large fan out and versatile drive characteristics.
Insignificant Power Supply Noise Generation,
due to differential amplifier design which eliminates
current spikes even during signal transition period.
Nearly Constant Power Supply Current Drain
simplifies power-supply design and reduces costs.
Low Cross-Talk due to low-current switching in
signal path and small, (typically 850 mV) voltage
swing, and to relatively long rise and fall times.
Wide Variety of Functions, including complex
functions facilitated by low power dissipation
(particularly in MECL 10,000 series). A basic
MECL 10,000 gate consumes less than 8 mW in
on-chip power in some complex functions.
Wide Performance Flexibility due to differential amplifier design which permits MECL circuits to be used as linear as well as digital circuits.
Transmission Line Drive Capability is afforded
by the open emitter outputs of MECL devices. No
"line Drivers" are listed in MECL families, because
every device is a line driver.
Wire-ORing reduces the number of logic devices
required in a design by producing additional OR '
gate functions with only an interconnection.
Twisted Pair Drive Capability permits MECL
circuits to drive twisted-pair transmission lines as
long as 1000 feet.
Wire-Wrap Capability is possible with MECL
10,000 and the M10800 LSI family because of the
slow rise and fall time characteristic of the circuits.
Open Emitter-Follower Outputs are used for
MECL outputs to simplify signal line drive. The
outputs match any line impedance and the absence of internal pulldown resistors saves power.
Input Pulldown Resistors of approximately
50kn permit unused inputs to remain unconnected for easier circuit board layout.

fered in the MC10500 and MC10600 Series, and
in the PLL family as the MC12500 Series.

BASIC CONSIDERATIONS FOR HIGH-SPEED
LOGIC DESIGN
High-speed operation involves only four considerations that differ significantly from operation
at low and medium speeds:
1. Time delays through interconnect wiring,
which may have been ignored in medium-speed
systems, become highly important at state-of-theart speeds.
2. The possibility of distorted waveforms due
to reflections on signal lines increases with edge
speed.
3. The possibility of "crosstalk" between
adjacent signal leads is proportionately increased
in high-speed systems.
4. Electrical noise generation and pick-up are
more detrimental at higher sp'eeds.
In g'eneral, these four characteristics are speedand frequency-dependent, and are virtually independent of the type of logic employed. The merit
of a particular logic family is measured by how
well it compensates for these deleterious effects in
system applications.
The interconnect-wiring time delays can be
reduced only by reducing the length of the interconnecting lines. At logic speeds of two nanoseconds, an equivalent "gate delay" is introduced
by every foot of interconnecting wiring. Obviously,
for functions interconnected within a Single monolithic chip, the time delays of signals travelling
from one function to another are insignificant. But
for a great many externally interconnected parts,
this ca,-, soon add up to an appreciable delay time.
Hence, the greater the number of functions per
chip, the higher the system speed. MECL circuits,

MECL APPLICATIONS
Motorola's MECL product lines are designed for
a wide range of systems needs. Within the computer market, MECL 10,000 is used in systems
ranging from special purpose peripheral controllers
to large mainframe computers. Big growth areas in
this market include disk and communication
channel controllers for larger systems and high
performance minicomputers.
The industrial market primarily uses MECL for
high performance test systems such as IC or PC
board testers. However, the high bandwidths of
MECL 10,000, MECL III, and MC12,OOO are
required for many frequency synthesizer systems
using high speed phase lock loop networks. MECL
will continue to grow in the industrial market
through complex medical electronic products and
high performance process control systems.
MECL 10,000 and MECL III have beEm accepted within the Federal market for numerous
signal processors and navigation systems. Full
military temperature range MECL 10,000 is of-

particularly those of the MECL 10,000 Series are
designed with a propensity toward complex functions to e(lhance overall system speed.

Waveform distortion due to line reflections also
becomes troublesome principally at state-of-the-art
speeds. At slow and medium speeds, reflections on
interconnecting lines are not usually a serious
problem. At higher speeds, however, line lengths
can approach the wavelength of the signal and improperly terminated lines can result in reflections
that will cause false triggering (see Figure 21. The
solution, as in R F technology, is to employ "transmission-line" practices and properly terminate each
sign,al line with its characteristic impedance at the
end of its run. The low-impedance, emitterfollower outputs of MECL circuits facilitate transmission-line practices without upsetting the voltage
levels of the system.

1-4

The increased affinity for crosstalk in highspeed circuits is the result of very steep leading and
trailing edges (fast rise and fall times) of the highspeed signal. These steep wavefronts are rich in
harmonics that couple readily to adjacent circuits.

the affinity for crosstalk without compromising
other important performance parameters.

From the above, it is evident that the MECL
logic line is not simply capable of operating at high
speed, but has been specifically designed to reduce
the problems that are normally associated with
high-speed operation.

In the design of MECL 10,000, rne rise and fall
times have been deliberately slowed. This reduces

-11=8"-11=8"A

VTT = -2 Vdc

~

~
I
I

I

I

Receiving Gate
Input A

I

I
,

I
I
I

I
,I

II

In

!f\

rJ

Low
.h

I I

:~

:

n"

HIgh

Hi!h-

IIVf..-"

~ ~ece;~ing~ate

V

I

\

,,

(

.

Input A
I

Low

I

V

~

FIGURE 2a - UNTERMINATED
TRANSMISSION LINE
(No Ground Plane Used)

FIGURE 2b - PROPERLY TERMINATED
TRANSMISSION LINE
(Ground Plane Added)

GATE

GATE CIRCUIT
MUltiple

Differential

Inputs

Amplifier

Network

~

~

~

Complementary

Bias

TRANS~ER

CURVES

-O.BOO

Outputs

~

VCC2 (Gnd)

~CCl

D
(Gnd)

o
2.

-1.200

&

----

~

OR

o

>
; -1.600

--1-+-----

.'!

NOR

<5

-1.800

Input Voltage (Volts)

A

B~A+B+C+D

C

o

VEE (-5.2 VI

A+B+D+C

GATE SYMBOL

FIGURE 3 - MECL GATE STRUCTURE AND SWITCHING BEHAVIOR

1-5

•

•

CIRCUIT DESCRIPTION

ward·biased 05 is conducting. Under these conditions, with the base of 05 held at -1.29 V by the
VBB network, its emitter will be one diode drop
(0.8 V) more negative than its base, or -2.09 V.
(The 0.8 V differential is a characteristic of th is
P-N junction.) The base-to-emitter differential
across 01 - 04 is then the difference between the
,common emitter 'voltage (-2.09 V) and the lOW
logic level (-1.75 V) or 0.34 V. This is less than the
threshold voltage of 01 through 04 so that these
transistors will remain cut off.
When anyone (or all) of the logic inputs are
shifted upward from the -1.75 V lOW state to the
-0.9 V HIGH state, the base voltage of that tran·
sistor increases beyond the threshold point and the
transistor turns on. When this happens, the voltage
at the common-emitter point rises from -2.09 V to
-1.7 (one diode drop below the -0.9 V base voltage
of the input transistor), and since the base voltage
of the fixed·bias transistor (05) is held at -1.29 V,
the base·emitter voltage 05 cannot sustain conduction. Hence, this transistor is cut off.
This action is reversible, so that when the input
signaJ(s) return to the lOW state, 01 - 04 are
again turned off and 05 again becomes forward
biased. The collector voltages resulting from the
switching action of 01 - 04 and 05 are transferred through the output emitter·follower to the
output terminal. Note that the differential action
of the switching transistors (one section being off
when the other is on) furnishes simultaneous
complementary signals at the output. This action
also maintains constant power' supply current
drain.

The typical MECl circuit, Figure 3, consists of
a differential-amplifier input circuit, a temperature
and voltage compensated bias network, and emitterfollower outputs to restore dc levels and provide
buffering for transmission line driving. High fanout operation is possible because of the high input
impedance of the differential amplifier input and
the low output impedance of the emitter follower
outputs. Power·supply noise is virtually eliminated
by the nearly constant current drain of the differ-·
ential amplifier, even during the transition period.
Basic gate design provides for simultaneous output
of both the OR function and its complement, the
NOR function.
Power·Supply Connections - Any of the power
supply levels, VTT, VCC, or VEE may be used as
ground; however, the use of the VCC node as
ground results in best noise immunity. In such a
case: VCC ~ 0, VTT ~ ·2.0 V, VEE ~ ·5.2 V.
System logic Specifications - The output
logic swing of 0.85 V, as shown by the typical
transfer characteristics curve, varies from a lOW
state of Val ~ .:.1.75 V to a HIGH state of VOH ~
..,0.9 V with respect to ground.
Positive logic is used when reference is made to
logical "O's" or' "l's." Then

"0"

~

-1.75 V

"1"

~

-0.9 V

~

lOW
typical

~

HIGH

Circuit Operation -- Beginning with all logic
inputs lOW (nominal -1.75 V), assume that 01
through 04 are cut off because their P-N baseemitter junctions are not conducting, and the for·

DEFINITIONS OF LETTER SYMBOLS AND ABBREVIATIONS
Current:
ICC

Total power supply current drawn from
the positive supply by a MECl unit under
test.

ICBO

leakage current from input transistor on
MECl devices without pulldown resistors
when test voltage is applied.

ICCH

Current drain from VCC power supply
with all inputs at logic HIGH level.

ICCl

Current drain from VCC power supply
with all inputs at logic lOW level.

IE

Total power supply current drawn from a
MECl test unit by the negative power
supply.

IF

Forward diode current drawn from an
input of a saturated 10gic·to·MECl trans·
lator when that 'input is at ground,
potential.
Current into the input of the test unit
when a maximum logic HIGH (VIH max)
is applied at that input.

Iin '

*IINH

HIGH level input current into a node
with a specified HIGH level (VIH max)
logic voltage applied to tha.t node. (Same
as Iin for positive logic.)

*IINl

lOW level input current, into a node
with a specified lOW level (Vll min)
logic voltage applied to that node.
load current that is drawn from a MECl
circuit output when measuring the output
HIGH level voltage.

1-6

*IOH

HIGH level output current: the current
flowing into the output, at a specified
HIGH level output voltage.

*IOl

lOW level output current: the current
flowing into the output, at a specified
lOW level output voltage.

lOS

Output short circuit current.

lout

Output current (from a device or circuit,
under such conditions mentioned in
context).

Current (cont.) :
IR

ISC

VILA

VI LA max Maximum input logic LOW level (thres·

Short·circuit current drawn from a trans·
lator saturating output when that output
is at ground potential.

*VIL min

hold) voltage for which performance is
specified.

Voltage:
VBB
VBE

VCB

Reference bias supply voltage.
Base·to-emitter voltage drop of a transistor at specified collector and base
currents.
Collector·to-base voltage drop of a
transistor at specified collector and base
currents.

VCC

General term for the most positive power
supply voltage to a MECL device (usually
ground, except for translator and interface circuits).

VCCl

Most positive power supply voltage (output devices). (Usually ground for MECL
devices.)

VCC2

VOHA

Most positive power supply voltage (current switches and bias driver). (Usually
ground for MECL devices.)

HIGH

threshold voltage

VOH max Maximum output HIGH or high-level
voltage for given inputs.

VOH min

Minimum output'HIGH or high-level voltage for given inputs.

*VOL

Output logic LOW voltage level: The
voltage level at the output terminal for a
specified output current, with the
specified conditions applied to establish a
LOW level at the output.

VOLA

Output logic LOW threshold voltage level.

Input logic HIGH voltage level (nominal
value).

VOLA max Maximum output LOW threshold voltage
level for which performance is specified.
VOL max

Maximum output LOW level voltage for
given inputs.

VOL min

Minimum output LOW level voltage for
given inputs.

VTT
VOLSl

Line load-resistor terminating voltage for
outputs from a MECL device.
Output logic LOW level on MECL 10,000
line receiver devices with all inputs at
VEE voltage level.

VOLS2

Output logic LOW level on MECL 10,000
line receiver devices with all inputs open.

Input logic HIGH threshold voltage level.

VIHA min Minimum input logic HIGH level (threshold) voltage for which performance is
specified.

VIL

Output logic
level.

VOHA min Minimum output HIGH threshold voltage
level for whicli performance is specified.

*VIH max Maximum HIGH level input voltage: The
most positive (least negative) value of
high-level input voltage, for which
operation of the logic element with in
specification limits is guaranteed.

*VIH min

Maximum (most positive) supply voltage,
'permitted under a specified set of
conditions.
Output logic HIGH voltage level: The
voltage level at an output terminal for a
specified output current, with the
specified conditions applied to establish a
HIGH level at the output,

Input voltage for measuring I F on TTL
interface circuits.

VIHA

Minimum LOW level input voltage: The
least positive (most negative) value of
LOW level input voltage for which operation of the logic element within specification limits is guaranteed.
Input voltage (to a circuit or device).

V max

Most negative power supply voltage for a
circuit (usually -5.2 V for M ECL devices).

VIH

Input logic LOW threshold voltage level.

Reverse current drawn from a transistor
input of a test unit when VEE is applied
at that input.

Minimum HIGH level input voltage: The
least positive (most negative) value of
HIGH level input voltage for which operation of the logic element within specifica·
tion limits is guaranteed.
Input logic LOW voltage level (nominal
value).

*VIL max Maximum LOW level, input voltage: The
most positive (least negative) value of
LOW level input voltage for which operation of the logic element within specification limits is guaranteed.

• JEDEC. EIA. NEr.JiA standard definitIon

'-7

•

Time Parameters:
t+

t-

Waveferm fall time (HIGH to. LOW), 90%
to. 10%, er 80% to. 20%, as specified.
Same as t+
Same as tPropagation Delay, see Figure

t-+

Propagatio.n Delay, see Figure 9_
Prepagatien delay, input to. eutput frem
the 50% peint ef the input waveferm at
pin x (falling edge neted by - er rising
edge neted by +) to. the 50% peint ef the
eutput waveferm at pin y (falling edge
neted by - er rising edge neted by +). (ef

tx±y±

9.

Figure 9.)
, tx+

t x-

Output waveferm rise time as measured
frem 10% to. 90% er 20% to. 80% peints
en waveform (whichever is specified) at
pin x with input cenditiens as specified.
Output waveferm fall time as measured
frem 90% to. 10% or 80% to. 20% peints
en waveferm (whichever is specified) at
pin x, with input cenditiens as specified.
Teggle frequency
ceunter device.

fshift

of

a

tWSCS

Chip select setup time prior to write

tWHCS

Chip select hold time after write

tws

Write disable time

tWR

Write recovery time

Temperature:

tf
t+-

tpd

Address hold time.after write

tWHA

Waveform rise time (LOW to HIGH), 10%
to. 90%, or 20% to. 80%, as specified_

flip-flep

Tstg

Maximum temperature at which device
may be stored without damage or performance degradation.

TJ

Junction (or die) temperature of an integrated circuit device.

TA

Ambient (environment) temperature existing
in the immediate vicinity of an integrated
circuit device package.

eJA

Thermal resistance of an IC package, junction '
to ambient.

eJC

Thermal resistance of an IC package, junction
to case.

Ifpm

Linear feet per minute. ,

eCA

Thermal resistance of an IC package, case
to ambient.

Miscellaneous:

er

Shift rate fer a shift register.

eg

Signal generator inputs to a test circuit.

TPin

Test point at input of unit under test.

TPout

Test point at output of u'nit under test.

D.U.T.

Device under test.

Cin

Input capacitance.

Chip Select Access Time

Cout

Output capacitance.

Chip Select Recovery Time

Zout

Output impedance.

'PD

The total de power applied to a device, net
including any power delivered from the'
device to a load.

Read Mode (Memories)

Address Access Time
Write Mode (Memories)

Load Resistance.

Write Pulse Width
tWSD

Data Setup Time Prior to Write

tWHD

Data Hold Time After Write

tWSA

Address setup time prior to write

Terminating (load) resistor.
An input pull-down resistor (Le., connected
to the most negative voltage).
P.U.T.

Pin under test .

• JEDEC, EIA, NEMA standard definition

1-8,

SECTION II - TECHNICAL DATA
GENERAL CHARACTERISTICS and
SPECIFICATIONS

LETTER SYMBOLS AND ABBREVIATIONS
Throughout this section, and in the subsequent
data sheets, letter symbols and abbreviations will
be used in discussing electrical characteristics and
specifications The symbols used in this book, and
their definitions, are listed on the preceding pages.

(See pages 1-6 through 1-8 for defin itions of symbols and abbreviations.)
In subsequent sections of this Data Book. the
important MECL parameters are identified and
characterized, and complete data provided for each
of the functions. To make this data as useful as
possible, and to avoid a great deal of repetition,
the data that is common to all functional blocks
in a line is not repeated on each individual sheet.
Rather, these common characteristics, as well as
the application information that applies to each
family, are discussed in this section.
In general, the common characteristics of major
importance are:
Maximum Ratings, including both dc and ac
characteristics and temperature limits;
Transfer Characteristics, which define logic
levels and switching thresholds;
DC Parameters, such as output levels, threshold
levels, and forcing functiol1s.
AC Parameters, such as propagation delays, rise
and fall times and other time dependent characteristics.

MAXIMUM RATINGS
The limit parameters beyond which the life
of the devices may be impaired. are given in Figure
4a. In addition, Table 4b provides certain limits
which, if exceeded, will not damage the devices,
but could degrade the performance below that of
the guaranteed specifications.
MECL TRANSFER CURVES
For MECL logic gates, the dual (complementary) outputs must be represented by two transfer
curves: one to describe the OR switching action
and one to describe the NOR switching action. A
typical transfer curve and associated data for all
MECL families is shown in Figure 5.
It is not necessary to measure transfer curves at
all points of the curves. To guarantee correct
operation it is sufficient merely to measure two
sets of minImax logic level parameters.

In addition, this section will discuss general layout and design guides that will help the designer in
building and testing systems with MECL circuits.

FIGURE 4a - LIMITS BEYOND WHICH DEVICE LIFE MAY BE IMPAIRED
Characteristic

Symbol

Unit

MECL 10,000

M10BOO LS'

MECL II.

Characteristic

VEE

Vdc

-8.0 to 0

-8.0 to 0

-8.0 to 0

Supply Voltage (VCC = 0)

VTT

Vdc

-

-4.0 to 0

-

o to VEE(-5.2V) OtoVEE(-5.2V) o to VEE

Input Voltage (VCC = 0)

Vin

Vdc

'nput Voltage Bus (VCC = 0)

Vin

Vdc

-

Oto -2.0m

-

Output Source Current
Continuous

'out

mAdc

50

50

40

Output Source Current Surge

'out
T stg

mAdc

100

100

-

-55 to +150

-55 to +150

-55 to +150

165

165

150

-

Junction Temperature
Ceramic Package@

TJ

°c
°c

Junction Temperature
Plastic Package

TJ

°c

Storage Temperature

(-5.2V)

165@150

NOTES: Q)'nput voltage limit is VCC to -2 volts when bus is used as an input and the output drivers
are disal;Jled.
.
®Maximum T J may be exceeded (<;; 250 0 C) for short periods of time (<;; 240 hours) without
significant reduction in device life.
@Except MC1666 - MC1670 which have maximum junction temperatures

1-9

=

145 0 C.

•

•

FIGURE4b - LIMITS BEYOND WHICH PERFORMANCE MAY BE DEGRADED
Characteristics

Symbol

Unit

MECL 10.000

Ml0800 LSI

MECL III

TA

°c

MC: -30 to +85

-30 to +85

-30 to +85

TA

°c

-55 to +125

-

-55 to +125

VEE

Vdc

MC: -4.68 to -5.72

-4.68 to -5.72

-4.68 to -5.72

Supply Voltage (VCC = 0)

VTT

Vdc

-

Output Drive Commercial

-

n
n

n to -2.0 Vdc
100 n to -2.0 Vdc

t r • tf

ns

-

Operating Temperature
Range Coriimercial



LL r./ VEE

~

>

"

5.2 V
6.0 V

0
0

Load

~ -0.6
w

"
I.J

n

50

0

M10BOO LSI

'and subsets: 10,200; 10,500; 10,600.
FIGURE 7C - TYPICAL LEVEL CHANGE RATES

---------------~~
-1.475

-1.105

/:lV = High .Noise {

I

------+"."....,..,-h:,.,j----- -0.980

~oise

Margin

VOLA max

VIHA min

High

/:lV = Low

Gate
Output

VOHA min

j State

OR
VOHA min

Margin

------+-'-Jf+""'--l---- -1.630

{

VILAmax
VOLA max

1 Low

j State

Noise Margin Computations

Gate
Input

Vas

(switching threshold)

Family

Guaranteed
Worst-Case dc
Noise Margin

Typical dc
Noise Margin

All MECL 10,000

0.125

0.210

MECL III

0.115

0.200

Specification Points for Determining Noise Margin

~.
~.~

FIGURE B - MECL Noise Margin Data
NOISE MARGIN

Guaranteed noise margin (NM) is defined as
follows:

a

"Noise margin" is a measure of logic circuit's
resistance to undesired switching. MECL noise
margin is defined in terms of the specification
points surrounding the switching threshold. The
critical parameters of interest here are those designated with the "A" subscript (VOHA min, VOLA
max, VIHA min,VILAmax) in the transfer characteristic curves.
'

NMHIGH LEVEL = VOHA min - VIHA min
NMLOW LEVEL = VILA max - VOLA max
To see how' noise margin is computed, assume a
MECL ga'te drives a similar -MECL gate, Figure B.
At a gate input (point B) equal to VILA max,
MECL gate #2 can begin to enter the shaded transition region.

1-12

This is a "worst case" condition, since the
VOLA max specification point guarantees that
no device can enter the transition region before an
input equal to VILA max is reached. Clearly then,
V I LA max is one critical point for noise margin
computation, since it is the edge of the transition
region.
To find the other critical voltage, consider the
output from MECL gate #1 (point A!. What is the
most positive value possible for this voltage (con-,
sidering worst case specifications)? From Figure 8
it can be observed that the VOLA max specification insures that the LOW state OR output from
gate #1 can be no greater than VOLA max.
Note that VOLA max is more negative than
VILA max- Thus, with VOLA max at the input
to gate #2, the transition region is not yet
reached. (The input voltage to gate #2 is still to
the left of VI LA max on the transfer curve.)
In order to ever run the chance of switching
gate #2, we would need an additional voltage,
to move the input from Vo LA max to V I LA
max' This constitutes the "safety factor" known
as noise margin_ It can be calculated as the magnitude of the difference between the two specification voltages, or for the MECL 10,000 levels
shown:
NMLOW

Noise margin is a dc specification that can be
calculated, since it is defined by specification
points tabulated on MECL data sheets. However, by itself, this specification does not give a
complete picture regarding the noise immunity of a
system built with a particular set of circuits. Overall system noise immunity involves not only noisemargin specifications, but also other circuit-related
factors that determine how difficult it is to apply a
noise signal of sufficient magnitude and duration
to cause the circuit to propagate a false logic state.
In general, then, noise immunity involves line impedances, circuit output impedances, and propagation delay in addition to noise-margin specifications. This subject is discussed in greater detail in
Application Note AN-592.
AC OR SWITCHING PARAMETERS
Time-dependent specifications are those that
define the effects of the circuit on a specified input sig'nal, as it travels through the circuit. They
include the time delay involved in changi ng the
output level from one logic state to another.
In addition, they include the time required for the
output of a circuit to re.spond to the input signal,
designated as propagation delay, or access time, in
the case of memories. Since this terminology has
varied over the years, and because the "conditions"
associated with a particular parameter may differ
among logic families, the common MECL waveform and propagation delay terminologies are
depicted in Figure 9. Specific rise, fall, and propagation delay 'times are given on the data sheet
for each specific function'al block, but like the
transfer characteristics, ac parameters are temperature and voltage dependent_ Typical variations for
MECL 10,000 are given in the curves of Figure 10.

VILA max - VOLA max
-1.475 V - (-1.630 V)
= 155 mV.
Similarly, for the HIGH state:
NMHIGH = VOHA min - VIHA min
= -0.980 V - (-1.105 V)
= 125 mV
=

=

Analogous results are obtained when considering the "NOR" transfer data.
Note that these noise margins are absolute
worst case conditions. The lesser of the two noise
margins is that for the HIGH state, 125 mV_ This
then, constitutes the guaranteed margin against
signal undershoot, and power or thermal disturbances.
As shown in the table, typical noise margins
are usually better than guaranteed - by about 75
mV.

Overshoot

t __~,---\--

r~-......- - - - -

l~~~~~~===~E~~~
VIHA
VILA

Undershoot
50%

Undershoot

SETUP AND HOLD TIMES
Setup and hold times are two ac parameters
which can easily be confused unless clearly defined.
For MECL logic devices, tsetup is the minimum
time (50% - 50%) before the positive transition of
the clock pulse (C) that information must be pres-

High Level

VSS

l=~=;z.:s.__- - L o w

Level

V out OR

*

-+

MECL WAVEFORM TERMINOLOGY

v out

O%

V out

~

NOR

t+-*

~
50%

10%

t--I

--

* Also designated tpd

t+

t-= tf

t-

MECL III Rise and Fall Times

= tf

t+ = tr

MECL 10,000 Rise and Fall Times

MECL Propagation Delay

FIGURE 9a - TYPICAL LOGIC WAVEFORMS

1-13

•

•

FIGURE 9b - MEMORY CHIP SELECT ACCESS TIME WAVEFORM

Chip Select

Cii
Dout

FIGURE 9c - MEMORY ADDRESS ACCESS TIME WAVEFORM

Address

Dout

2.6

]

2.5

>

r--- I-sol n

LJad to l -2.0

~

I

OR



-

7.0 V

1-r--

5

620b-~~~=--+~~d-~--~--~--4+~

6.0 V

I

OL-~L-~~~

o

-5.2 V

10
V OUT (VOL TS)

-4',4 V

3.6V_

5

__-L~-U__~~~~~~

r(LOAD LINES FOR TERMINATION TO Vee (-5 2 Vdc) 2SoC

-3.0

v

50

~'HA

I
-55

,-25

0

-+25

+75

I

+125

.J.

40

T A. AMBIENT TEMPERATURE (oC)

VQH min

VQH

m!1C I

r---!:-± I I

FIGURE 14 - NORMALIZED POWER
DISSIPATION versus TEMPERATURE
AND SUPPLY VOLTAGE

r7!

F==:-270 Ohms

Joe Oh~$

10

La-JA
I
I

I

I
I

I
I

I

I

I

VO~I
max

JOL/
moo

7

-f--

/

lK Ohms

a

~2KOhms

o

05

10

15

2.0

FIGURE 15 - OUTPUT VOLTAGE LEVELS
versus DC LOADING

LOADING CHARACTERISTICS
The differential input to MECL circuits' offers
several advantages. Its common-made-rejection
feature offers .immunity against power·supply
noise injection, and its relatively high input
impedance makes it possible for any circuit to
drive a relatively large number of inputs without
deterioration of the guaranteed noise margin.
Hence, dc fanout with MECL circuits does not
normally present a design problem.
Graphs showing typical output voltage levels
as a function of load current for MECL III and
10,000 are shown in Figure 15. These graphs can
be used to determine the actual output voltages for
loads exceeding normal operation.
While dc laading causes a change in output
voltage leve!s, thereby tending to affect noise
margins, ac loading increases the capacitances
assaciated with the circuit and, therefore, affects
circuit speed, primarily rise and fall times.
MECL 10,000 and MECL III circuits typically
have a 7 ahm autput impedan'ce and are relatively
unaffected by capacitive laading on a pasitivegaing output signal. Hawever, the negative-going
-edge is dependent o.nthe output pulldown ar
terminatian resistar. Laading close to a M ECL
autput pin will cause an additional propagatian
delay of 0.1 ns per fanaut laad with a 50 ohm
resistar to -2.0 Vdc or 270 ohms to. -5.2 Vdc.
A 100 ohm resistar to. -2.0 Vdc or 510 ohms
to -5.2 Vdc results in an additional 0.2 ns propagation delay per fanout laad.

Terminated transmission line signal interconnections are used for best MECL 10,000 or
M ECL III system performance. The propagation
delay and rise time of a driving gate are affected
very little by capacitance laading alang a matched
parallel-terminated transmission line. Hawever, the
delay and characteristic impedance af the transmission line itself are affected by the distributed
capacitance. Signal propagation down the line will
be increased by a factor,
1+Cd/Co' Here Co is
the normal intrinsic line capacitance, and Cd is the
distributed capacitance due to laading and stubs
aff the line.
.'
MaximlJm allowable stub lengths for loading off.
of a MECL 10,000 transmissian line vary with the
line impedance. For example, with Zo ~ 50 ohms,
maximum stub length would be 4.5 inches (1.8 in.
far MECL III). But when Zo ~ 100 ohms, the
maximum allowable stub length is decreased to
2.8 inches (1.0 in. for MECL III).
.
The input loading capacitance of a MECL 10,000
gate is about 2.9 pF and 3.3 pF for MECL III. To.
allaw for the IC cannector or salder connection
and a short stub length, 5 to 7 pF is cammonlyused in loading calculati(;>ns.

v'

1-18

UNUSED MECL INPUTS
The input impedance of a differential ampl ifier,
as used in the typical MECL input circuit, is very
high when the applied signal level is low. Under
low-signal conditions, therefore, any leakage to the
input capacitance of the gate could cause a gradual
buildup of voltage on the input lead. thereby
adversely affecting the switch ing characteristics
at low repetition rates.
All single-ended input M EC L logic circuits
contain input pulldown resistors between the input
transistor bases and VEE. As a result, unused
inputs may be left unconnected (the resistor provides a sink for ICBO leakage currents, and inputs
are held sufficiently negative that circuits will not
trigger due to noise coupled into such inputs).

Input pulldown resistor values are typically 50
k.!1 and are not to be used as pulldown resistors
for preceding open-emitter outputs.
Several MECL devices do not have input
pulldowns. Examples are the differential line
receivers. If a single differential receiver within a
package is unused, cine input of that receiver must
be tied to the VBB pin provided, and the other
input goes to VEE. Also, several MECL memories
do not have input pulldowns on all inputs.
Several MECL circuits do not operate properly
when inputs are connected to VCC for a HIGH
logic level. Proper design practice is to set a HIGH
level as about -0.9 volts below V CC with a resistor
divider, a diode drop, or an unused gate output.

1-19

•

•

SECTION IV - SYSTEM DESIGN- CONSIDERATIONS
THERMAL MANAGEMENT

eJC = average thermal resistance, junction
to case
eCA = average thermal resistance, case to
ambient
eJA = average thermal resistance, junction
to ambient

Circuit performance and long-term circu it
reliability are affected by die temperature. Nor-'
mally. both are improved by keeping the IC
junction temperatures low.
Electrical power dissipated in any integrated
circuit isa source of heat. This heat source increases
the temperature of the die relative to some reference point, normally the ambient temperature of
25 0 C in still air. The temperature increase, then,
depends on the amount of power dissipated
in the circuit and on the net thermal resistahce
between the heat source and the reference point.
The temperature at the junction is a function
of the packaging and mounting system's ability
to remove heat generated in the circuit-from the
junction region to the ambient environment.
The basic formula (a) for converting power dissipation to estimated junction temperature is:
TJ = TA

+ PD (OJC + eCA)

This Motorola recommended formula has been
approved by RADC and DESC for calculating
a "practical" maximum operating junction temperature for MIL-M-38510 (JAN) MECL 10,000
devices.
Only two terms on the right side of equation (1)
can be varied by the user-the ambient temperature,
and the device case-to-ambient thermal resistance,
eCA. (To some extent the device power dissipation
can be also controlled, but under recommended
use the VEE supply and loading dictate a fixed
power dissipation.) Both system air flow and the
package mounting technique affect the eCA
thermal resistance term. eJC is essentially independent of air flow and external mounting method,
but is sensitive to package material, die bonding
method, and die area.
For applications where the case is held at
essen'tially a fixed temperature by mounting on
a large or temperature-controlled heat sink, the
estimated junction temperature is calculated by:

'(1)

or
(2)
where
T J = maximum junction temperature
T A = maximum ambient temperature
PD = calculated maximum power dissipation
including effects of external loads (see
Power Dissipation in section III).

(3)

FIGURE 16 - THERMAL RESISTANCE VALUES FOR STANDARD MECL IC CERAMIC PACKAGES
THERMAL RESISTANCE IN STILL AIR
Package Type
(All Using Standard" Mounting)
(All Gold Eutectic Die Bond)

8JA
(OCIWatt)

8JC
(OCIWatt)

Average

Maximum

Average

Maximum

100

130

25

40

165

205

40

60

100

130

25 .

40

88

115

13

20

73

95

16

25

45

55

10

15

40

52

6

10

40

52

8

12

14 Lead Dual-in-Line

1/4" X·3/4" Alumina
Die Area

=

4096 Sq. Mils

14 Lead Flat Pack
1/4" X 1/4" Alumina
Die Area! 4096 Sq. Mils
16 Lead Dual-in-Line

1/4" X 3/4" Alumina
Die Area: 4096 Sq. Mils
16 Lead Flat Pack
1/4" X 3/8" Beryllia
Die Area = 4096 Sq. Mils
20 Lead Dual-in-Line
1/4" X '" Alumina
Die Area = 11,349 Sq. Mils
24 Lead Dual-I n-Line
1/2" X 1-1/4" Alumina
Die Area = 8192 Sq. Mils

24 Lead Flat Pack
3/8" X 5/8" Beryllia
Die Area = 8192 Sq. Mils
48 Lead Quad-in-Line (QUIL)
1/2" X 1-1/4" Alumina
Ole Area:::: 16,384 Sq. Mils

Standard Mounting Methods.
Dual-ln·Line: In socket or on PC Board with no contact between bottom of package and socket or
PC Board.
Flat Pack: Bottom of Package in direct contact with non-metallized area of PC Board.

'-20

per minute. From Figure 18, eJA is 50 0 C/W. With
T A (air flow temperature at the device) equal to
25 0 C, the following maximum junction temperatu re resu Its:

where TC = maximum case temperature and the
other parameters are as previously defined.
The maximum and average thermal resistance
values for standard M ECL IC packages are given
in Figure 16. In Figure 17, this basic data is converted into graphs showing the maximum power
dissipation allowable at various ambient temperatures (still air) for circuits mounted in the different
packages, taking into account the maximum permissible operating junction temperature for long
term life (;;. 100,000 hours).

TJ = PD(OJAI +TA
TJ

\

3500

3000 ~

ill

2500

i'A'" (fran"t- t--

l-'·~

o\.

""

AtuminaCeramlcfor _
All Packages

I'..

~20Lead I~

r-- 1--"""""" r--..,
14 and 16 Lead

l

,

50

,

-

o

,

"'"

"-.....

........... r--,.

~ad(Aluml"a

o

~

r-.:: ~ ~

75

.(~~,~~""

.......

~48lead

24Lea~

0

Airflow DirectIOn

r- t--

l"- t---

-...:::::::t:::- r-

, 125~
, 150~
,
100

175

,

200

,

*X-Axis (Longitudinal) Airflow will
lower OJA by approximately 5%

225'

0

400

200

0
0

i5

'"w
~

0

0

O~fYllia~
o--+--' .............. .........."""

150

100 0

~

50

'"~
'"

"~"d (Beryllia)

0

~

0
25

,

11 Lead (Allmona)
50

,

75

,

--""

100'

Airflo~ olrecLn- t--

0"
0

ZOO 0

~
;(

0

~
.

'"r-

-

............. t--

150'

0

I

i'--f-

-

I--

....--:

-

Z-Axis (Transverse)

I

14 lead (Alumma)

I

I

16 Lead (Servilla)

0 _ 24 lead (Beryilla)

:::::::::; ~

125'

1000

800

FIGURE 18a - AIRFLOW versus THERMAL
RESISTANCE (CERAMIC DUAL-IN-LiNE PKG)

350

~ 250 0

600

AIRFLOW (lIpm)

400 0

0""
300 0

-

241 Lead (Alumina)

0

FIGURE 17a - AMBIENT TEMPERATURE DERATING
CURVES (CERAMIC DUAL-IN-LINE PKG)

z
o
~

~~ead+mina) t - -

48 lead (Alumina)

TA. AMBIENT TEMPERATURE - STILL AIR ('C)

-_;E

= 34.8 0 C

10 0

~
~

i5

(50 0 C/W + 25 0 C

Under the above operating conditions, the
MECL 10,000 quad gate has its junction elevated
above ambient temperature by only 9.8 0 C.

]> 4000

i

= (0.195 WI

\

*X·Axis (Longitudinal Alrflowapproximately same effect as Z·Axis Flow
175'

200'

225'

0

200

400

600

800

1000

AIRFLOW (llpm)

TA. AMBIENT TEMPERATURE - STILL AIR ('C)

FIGURE 17b - AMBIENT TEMPERATURE DERATING
CURVES (CERAMIC FLAT PKG)

FIGURE 18b - AIRFLOW versus THERMAL
RESISTANCE (CERAMIC FLAT PKG)

AIR FLOW
Even though different device types mounted
on a printed circuit board may each have different
power dissipations, all will have the same input and
output levels provided that each is subject to
identical air flow and the same ambient air
temperature. This eases design, since the only
change in levels between devices is due to the
increase in ambient temperatures as the air passes
over the devices, or differences in ambient temperature between two devices.
The majority of MECL 10,000, 10800, and
MECL III users employ some form of air-flow
cooling. As air passes over each device on a printed
circuit board, it absorbs heat from each package.
This heat gradient from the first package to the last

The effect of air flow over the packages on eJA
(due to a decrease in eCA) is illustrated in the
graphs of Figure 18. This air flow reduces the
thermal resistance of the package, therefore
permitting a corresponding increase in power dissipation without exceeding the maximum permissible
operating junction temperature.
As an example of the use of the information
above, the maximum junction temperature for
a 16 lead ceramic dual-in-line packaged MECL
10,000 quad OR/NOR gate (MC10l0l L) loaded
with four 50 ohm loads can be calculated. Maximum total power dissipation (including 4 output
loads) for this quad gate is 195 mW. Assume for
this thermal study that air flow is 500 linear feet

1-21

•

•

package is a function of the air, flow rate and
individual package dissipations. Figure 19 provides
gradient data at power levels of 200 mW. 250 mW,
300 mW, and 400 mW with an air flow rate of
500 Ifpm. These figures show the proportionate
increase in the junction temperature of each dual
in-line package as the air passes over each device.
For higher rates of air flow the change in junction
temperature from package to package down the
airstream will be lower due to greater cooling.

Power Dissipation
(mW)

The following sections on package mounting and
heat sinking are intended to provide the designer
with sufficent information to insure good noise
margins and high reliability in MECl system use.

MOUNTING AND HEAT SINK SU'GGESTIONS
With large high-speed logic systems, the use
of multilayer printed circuit boards is recommended to provide both a better ground plane and
a good thermal path for heat dissipation. Also, a
multilayer board allows the use of microstrip line
techniques to provide transmission lin,e interconnections.
Two-sided printed circuit boards may be used
where board dimensions and package count are
small. If possible, the VCC ground plane should
face the bottom of the package to form the
thermal conduction plane. If signal lines must be
placed on both sides of the board, the VEE plane
may be used as the thermal plane, and at the same
time may be used as a pseudo ground plane. The
pseudo ground plane becomes the ac ground
reference under the Signal I ines placed on the same
side as the VCC ground plane (now on the opposite
side of the board from the packages), thus maintaining a microstrip signal line environment.
Two-ounce copper PIC board is recommended
for thermal conduction and mechanical strength.
Also, mounting holes for low power devices may
be countersunk to allow the package bottom ~o
contact the heat plane. This technique used along
with thermal paste will provide good thermal
conduction.
Printed channeling is a useful technique for
conduction of heat away from the packages when
the devices are soldered into a printed circuit
board. As illustrated in Figure 20, this heat dissipation method could also serve as VEE voltage
distribution or as a ground bus. The channels
should terminate into channel strips at eac!], side
or the rear of a plug-in type printed circuit board.
The heat can then be removed from the circuit
board, or board slide rack, by means of wipers
that come into thermal contact with the edge
channels.

Junction-Temperature Gradient
(OC/Package)

200
250
300

0.4
0.5
0.63
400
0.88
Devices mounted on 0.062" PC board with Z axis spacing of
0.5". Air flow is 500 Ifpm along the Z axis.

F.IGURE 19 - THERMAL GRADIENT OF
JUNCTION TEMPERATURE
(16-Pin MECL Dual In-Line Package)

THERMAL EFFECTS ON NOISE MARGIN
The data sheet dc specifications for standard
MECL 10,000,10800, and MECL III devices are
given for an operating temperature range from
-30 0 C to +85 0 C (00 to +75 0 C for memories) in
Figure 6b and 6c of Section II, TECH N ICAl
DATA. These values are based on having an airflow
of 500 Ifpm over socket or PIC board mounted
packages with no special heat sinking (i.e., dual-inline package mounted on lead seating plane with
no contact between bottom of package and socket
or PIC board and flat package mounted with
bottom in direct contact with non-metall ized area
of PIC board). Under these conditions, adequate
cooling is'provided to keep the maximum operating
junction temperatures below 145 0 C for MECl III
device types 1666-1670 and below 1650 C for all
other MECl device types.
The designer may want to use MECl devices
under conditions other than those given above. The
majority of the low-power device types may be
used without air and with higher 0JA' However,
the designer must bear in mind that junction
temperatures will be higher for higher OJA, even
though the ambient temperature is the same.
Higher junction temperatures will cause logic
levels to shift.
As an example, a 300 mW 16 lead dual-in-I ine
ceramic device operated at OJA : 100 0 C/W (in
still air! shows a HIGH logic level shift of about
21 mV above the HIGH logic level when operated
with 500 Ifpm air flow and a eJA : 50 0 C/W,
(level shift : ~ T J X 1.4 mV /oC).
If logic levels of individual devices shift by
different amounts (depending on PD and eJAL '
noise margins are somewhat reduced. Therefore,
the system designer must layout his system
bearing in mind that the mounting procedures to
be used should minimize thermal effects on
noise margin.

FIGURE 20 - CHANNEL/WIPER
HEAT SINKING ON DOUBLE LAYER BOARD

1-22

MECL also interfaces readily with MOS. With
CMOS operating at +5 V, any of the MECL to
TTL translators works very well. On the other
hand, CMOS will drive MECt directly, when using
a common -5.2 V supply.
Specific circuitry for use in interfacing MECL
famil ies to other logic types is given in detail in the
MECL System Design Handbook. '
Complex MECL 10,000 functions are presently
available to interface MECL 10,000 with MOS
logic, MOS memories, TTL three-state circuits,
and IBM bus logic levels. See Application Note
AN-720 for additional interfacing information.

For operating some of the higher power device
types* in 16 lead dual-in-line packages in still air,
requiring 7JJA < 100 0 CIW, a suitable heat sink is
the IERC LlC-214A2WCB shown in Figure 21.
This sink reduces the still air 7JJA to around
55 0 C/W. By mounting this heat sink directly on a
copper ground plane (using silicone paste) and
passing 500 Ifpm air over the packages, eJA is
reduced to approximately 35 0 C/W, permitting use
at higher ambient temperatures than +85 0 C
(+75 0 C for memories) or in lowering TJ for improved rei iability.

CIRCUIT INTERCONNECTIONS
Though not necessarily essential, the use of
multilayer printed circuit boards offers a number
of advantages in the development of high-speed
logic cards. Not only do multilayer boards achieve
a much higher package density, interconnecting
,leads are kept shorter, thus minimizing propagation delay between packages. This is particularly
beneficial with MECL III which has relatively fast
(1 ns) rise and fall times. Moreover, the unbroken
ground planes made possible with multilayer
boards permit much more precise control of transmission I ine impedances when these are used for
interconnecting purposes. Thus multilayer boards
are recommended for MECL III layouts and are
justified when operating MECL 10,000 at top
circuit speed, when high-density packaging is a
requirement, or when transmision line interconnects are used.
Point-to-point
back-plane
wiring ,! without
matched I ine terminations may be employed for
MECL interconnections if line runs are kept short.
At MECL 10,000 speeds, this applies to line runs
up to 6 inches, and for MECL III up to 1 inch
(maximum open wire lengths for less than 100 mV
undershoot). But, because of 'the open-emitter
outputs of MECL 10,000 and MECL III circuits,
pull-down resistors are always required. Several
ways of connecting such pull-down resistors are
shown in Figure 22.
Resistor values for the connection in Figure 22a
may range from 270 ohms to 2 krl. depending on
power and load requirements. (See MECL System
Design Handbook.) Power may be saved by connecting pull-down resistors in the range of 50 ohms
(100 ohm minimum for MC10,500 and MC10,600
Series parts) to 150 ohms, to -2.0 Vdc, as shown
in Figure 22b. Use of- a series damping resistor,
Figure 22c, will extend permissible lengths of
unmatched-impedance interconnections, with some
loss of edge speed.
With proper choice of the series damping
resistor, line lengths can be extended to any
length, ** while limiting overshoot and undershoot
to a predetermined amount. Damping resistors
usually range in value from 10 ohins to 100 ohms,
depending on the line length, fanout, and 'line
impedance. The open emitter-follower outputs of
MECL III and MECL 10,000 give the system
designer all possible line driving options.

Heat Dissipator

IERC-LIC-214A2WCB

Multi-Layer
PC Board

FIGURE 21 - MECL HIGH-POWER
DUAL-IN-LiNE
PACKAGE MOUNTING METHOD
It should be noted that the use· of a heat sink
on the top surface of the dual-in-line package is not
very effective in lowering the eJA' This is due to
the location of the die near the bottom surface of
the package.
Also, very little « 10%) of the internal heat is
withdrawn through the package leads due to the
isolation from the ceramic by the solder glass
seals and the limited heat conduction from the die
through 1.0 to 1.5 mil aluminum bonding wires.
INTERFACING MECL TO
SLOWER LOGIC TYPES
MECL circuits are interfaceable with most
other logic forms. For MECL/TTL/DTL interfaces, when M EC L is operated at the recommended
-5.2 volts and TTL/DTL at +5 V supply, currently
available translator circuits, such as the MC10124
and MC1 0125, may be used.
For systems where a dual supply (-5.2 V and
+5 V) is not practical, the MC12000 includes a
single supply MECL to TTL and TTL to MECL
translator, or a discrete component translator can
be designed. For details, see MECL System Design
Handbook. Such circuits can easily be made fast
enough for any available TTL.

Limited only by line attenuation and band-

MC1654, 1676, 1694, 10128, 10129, 10136, 10137,
10177, 10182, and ;0804. Max Po
800 mW.

>

width characteri'stics.

1-23

•

•

~
-5.2 V

Rl

(0)

~

(b)

~

(c)

-2.0 V (VTTI

Rp

-5.2 V

FIGURE 23b - PARAllEL TERMINATION
-THEVENIN EQUIVALENT

.

-5.2 V

Another popular approach is the seriesterminated transmission line (see Figure 24). This
differs from parallel termination in that only
one-half the lOgic swing is propagated through the
I ines. The logic swing doubles at the end of the
transmission line due to reflection on an open line,
again establishing a full logic swing.

FIGURE 22 - PUll-DOWN
RESISTOR TECHNIQUES

One major advantage of M ECl over saturated
logic is its capability for driving matched-impedance
transmission lines. Use of transmission lines retains
signal integrity over long distances. The MECl III
and M ECl 10,000 emitter-follower output transistors will drive a 50-ohm transmission lihe (100
ohms or greater for MECl 10,500 and MC10,600
Series) terminated to -2.0 Vdc. This is the equivalent current load of 22 rnA in the H IG H logic
state and 6 rnA in the lOW state.
Parallel terminatio·n of transmission lines can be
done in two ways. One, as shown in Figure 23a,
uses a single resistor whose value is equal to the
impedance (Zo) of the line. A terminating voltage
(VTT) of -2.0 Vdc must be supplied to the
term inating resistor.
Another method of parallel termination uses
a pair of resistors, Rl and R2. Figure 23b illustrates
this method. The following two equations are used
to calculate the values of R 1 and R2:

A

tPdl
B

c

~~

______~~__________~50%

FIGURE 24 - SERIES TERMINATED LINE

To maintain clean wave fronts, the input
impedance of the driven gate must be much greater
than the characteristic impedance of the transmission line. This condition is satisfied by MECl
circuits which have high impedance inputs. Using
the appropriate terminating resistor (RS) at point
A (Figure 24), the reflections in the transmission
line will be terminated.
The advantages of series termination include
ease of driving multiple series-terminated lines, low
power consumption, and low cross talk between
adjacent lines. The disadvantage of this system
is that loads may not be distributed along the
transm ission I ine due to the one-half logic swing
present at inte~mediate points.
F,or board-to-board interconnections, coaxial
cable may be used for signal conductors. The
termination techniques just discussed also apply
when using coax. Coaxial cable has the advantages
of good noise immunity and low attenuation at
high frequencies. No significant performance
degradation occurs for lengths up to 20 feet for
MECl III, and up to 50 feet for MECl 10,000.

Rl = 1.6 Zo
R2 = 2.6 Zo

~-----tpd------__

B

VTT (-2.0 V)

FIGURE 23a - PARAllEL TERMINATED LINE

'-24

Twisted pair lines are one of the most popular
methods of interconnecting cards or panels. The
complementary outputs of any MECL III or
MECL 10,000 function are connected to one end
of the twisted pair line, and any MECL differential
line receiver to the other as shown in the example,
Figure 25. RT is used to terminate the twisted
pair line. The 1 to 1.5 V common·mode noise
rejection of the line receiver ignores common-mode
cross talk, permitting multiple twisted pair lines
to be tied into cables. MECL signals may be sent
very long distances (> 1000 feet) on twisted pair,
although line attenuation will limit bandwidth,
degrading edge speeds when long line runs
are made.

Series damping resistors may be used with wirewrapped lines to extend permissible backplane
wiring lengths. Twisted pair lines may be used
for even longer distances across large wire-wrapped
cards. The twisted pair gives a more defined
characteristic impedance (than a single wire), and
can be connected either single-ended, or differentially using a line receiver.
The recommended wire-wrapped circuit cards
have a ground plane on one side and a voltage
plane on the other, to insure a good ground and
a stable voltage source for the circuits. In addition,
the ground plane near the wire-wrapped lines
lowers the impedance of those lines and facilitates
terminating the line. Finally, the ground plane
serves to minimize cross talk between parallel paths
in the signal lines. Point-to-point wire routing is
recommended because cross talk will be minimized
and line lengths will be shortest. Commercial
wire-wrap boards designed for MECL 10,000
are available from several vendors.
Microstrip and Stripline
Microstrip and stripline techniques are used
with printed circuit boards to form transmission
lines. Microstrip consists of a constant-width
conductor on one side of a circuit board, with
a ground plane on the other side (shown in Figure
27). The characteristic impedance is determined
by the width and thickness of the conductor, the
thickness of the circuit board, and the dielectric
constant of the circuit board material.
Stripline is used with multilayer circuit boards
as shown in Figure 27. Stripline consists of a
constant-width conductor between two ground
planes.
Refer to MECL System Design Handbook for
a full discussion of the properties and use of these
lines.

FIGURE 25 - TWISTED PAIR LINE
DRIVER/RECEIVER

If timing is critical, parallel signal paths (shown
in Figure 2'6) should be used when fanout to
several cards is required. This will eliminate
distortion caused by long stub lengths off a
signal path.
Wire-wrapped connections can be used with
MECL 10,000. For MECL III, the fast edge speeds
(1 ns) create a mismatch at the wire-wrap connections which can cause reflections, thus reducing
noise immunity. The mismatch occurs also with
MECL 10,000, but the distance between the
wire-wra'p connection and the end of the line is
generally short enough so the reflections cause
no problem.
~-------- Card A

:::

--D l"~
VEE

--e=:;;::~:r----r- Card A
Zo

~-e=~=:r--r-+- Card B
Zo

---{I=~=)--lr-t-t-- Card C
Zo

FIGURE 27 - PC INTERCONNECTION
LINES FOR USE WITH MECL
'Multiple output gate eg MC10110

VTT

FIGURE 26 - PARALLEL FANOUT TECHNIQUES

1-25

•

•

4. To minimize clock skewing problems on
synchronous sections of the system, line delays
should be, matched to within 1 ns.
5. Parallel drive ,gates should be used when
clocking repetition rates are high, or when high
capacitance loads occur. The bandwidth of a
MECL III gate may be extended by paralleling
both halves of a dual gate. Approximately 40 or
50 MHz bandwidth can be gained by paralleling
two or three clock driver gates.
6. Fanout limits should be applied to clock
distribution drivers. Four to six loads should be
the maximum load per driver for best high speed
performance. Avoid large lumped loads at the end
of lines greater than 3 inches. A lumped load, if
used, should be four or fewer loads.
7. For wire-OR (emitter dotting), two-way
lines (busses) are recommended. To produce such
lines both ends of a transmission line are termin;ted with laO-ohms impedance. This method
should he used when wire-OR connections exceed
1 inch apart on a drive line.
'

CLOCK DISTRIBUTION
Clock distribution can be a system problem. At
MECl 10,000 speeds, either coaxial cable or
twisted pair line (using the MC10l0l and
MC10115) can be used to distribute clock signals
throughout a system. Clock Iine lengths should be
controlled and matched when timing could be
critical. Once the clocking signals arrive on card,
a tree distribution should be used for large-fanouts
at high frequency. An example of the application
of this technique is shown in Figure 28.

Off
Card

B. Off-Card Clock Distribution
1. The OR/NOR outputs of an MC1660 may
be used to drive into twisted pair lines or into flat,
fixed-impedance ribbon cable. At the far end of
the twisted, pair an MC1692 differential line
receiver is used. The line should be terminated as
shown in Figure 25. This method not only provides
high speed, board-to-board- clock distribution, but
also provides system noise margin advantages.
Since the I ine receiver operates independently of
the V BB reference voltage (differential inputs) the
noise margin from board to board is also independent of temperature differentials.
LOGIC SHORTCUTS
M ECl circuitry offers several logic design
,conveniences. Among these are:
1. Wire-OR (can be produced by wiring MECL
output emitters together outside paokages).
2. Complementary Logic Outputs (both OR
and NOR are brought out to package pins in most
cases) .
An example of the use of these two features to
reduce gate and package count is shown in Figure
29.
'

FIGURE 28 - 64 FANOUT CLOCK DISTRIBUTION
Because of the very high clock rates encountered
in MECl III systems, rules for clocking are more
rigorous than in slower systems.
The following guidelines should be followed for
best results:
A. On-card Syncrhonous Clock Distribution
via Transmission Line
1: Use the NOR output in developing clock
chains or trees. Do not mix OR and NOR outputs
in the chain.
'2. Use balanced fanouts on the clock drivers.
3. Overshoot can be reduced by using two
parallel drive lines in place of one drive line with
twice the lumped load.

AS + CD

A
B

Rp

C
D

C+D+E+F+G
Rp

E
F
G

A+B+E+F+G
MC10l05

Rp

FIGURE 29 - USE OF WIRE-OR AND
COMPLEMENTARY OUTPUTS

1-26

The connection shown saves several gate
circuits over performing the same functions with
non-ECL type logic. Also, the logic functions in
Figure 29 are all accomplished with one gate
propagation delay time for best system speed.
Wire-DRing permits direct connections of MECL
circuits to busses. (MECL System Design Handbook and Application Note AN-7261.

a proper LOW logic level. The MC10123 is an
exception to this rule because it has a special
VOL level that allows very high fanout on a bus
or wire-OR line. The use of a single output pulldown resistor is recommended per wire-OR, to
economize on power dissipation. However, two
pull-down resistors per wired-OR can improve fall
times and be used for double termination of busses.
Wire-OR should be done between gates in a
package or nearby packages to avoid spikes due to
line propagation delay. This does not apply to bus
lines which activate only one driver at a time.

Propagation delay is increased approximately
50 ps per wire-OR connection. In general, wire-OR
should be limited to 6 MECL outputs to maintain

SYSTEM CONSIDERATIONS - A SUMMARY OF RECOMMENDATIONS
MECL 10,000

MECL III

Power Supply Regulation

10% or better *

10% or better*

On-Card Temperature Gradient

Less Than 25 0 C

Less Than 25 0 C

8"

1"

Leave Open* *

Leave Open**

Standard 2-Sided or
Multilayer

Multilayer

Maximum Non-Transmission Line
Length (No Damping Resistor)
Unused Inputs
PC Board
Special Cooling Requirements
Bus Connection Capability
MSI/LSI Parts
Maximum Twisted Pair Length
(Differential Drive)
The Ground Plane to Occupy
Percent Area of Card
Wire Wrap may be used
Compatible with.MECL 10,000

No

No

-Yes (Wire-OR)

Yes (Wire-OR)

Yes

Yes (MSI)

Limited by Cable Response
Only, Usually> 100C),

Limited by Cable Response
Only, Usually> 1000'

> 50%

> 75%

Yes

Not Recommended

-

Yes

* At the devices.
**Except special functions without input pull-down resistors.

'-27

•

•

PACKAGE OUTLINE DIMENSIONS
A letter suffix to the MECL logic function part number is used to specify the package style
(see drawings below). See appropriate selector guide for specific packaging available for a given device type.

F SUFFIX

L SUFFIX

CERAMIC PACKAGE
CASE 607·04

CERAMIC PACKAGE

L

I"

[R

-r- R
,

L

1to

:

,01:,!J

[04

"

fr
I
! IL K-I-A
C

D
F

G
H

J

K
L
N
R
S

MILLIMETERS
MIN
MAX
6.10
6.99
0.76
2.03
0.25 0.48
0.08 0.15
1.27 sse
0.13 0.89
0.38
6.35
18.80
0.25
0.38
7.62 8.38

~
A-I

-

0.300

0.015
0.330

NOTE.
1. LEADS WITHIN 0.13 mm (0.0051
TOTAL OF TRUE POSITION
RELATIVE TO "A" AT MAXIMUM
MATERIAL CONDITION.

INCHES
MIN
MAX

31.24 32.26
12.70 13.72
5.59
4.06
0.41
0.51
1.52
1.27
2.54 SSC
G
0.30
J
0.20
2.29
4.06
K
15.24 BSe
L
M
15°
0°
1.27
N 0.51

1.230 1.270
0.500 0.540
0.160 0.220
0.016 0.020
0.050 0.060
0.100 sse
0.008 0.012
0.090 0.160
0.600 sse
15°
0°
0.020 0.050

A
B
C
D
F

PLANE,

MIN
0.750
0.245

MAX
0780
0275

NOTES

0160

'O200

0015

0.020
0065

INCHES

0
F

D.3S

0.51

G

H
J

1.40
165
2.54 ase
1.14

0.51
0.20
3.18
737

M

0.51

030
4.06

787
IS'
1.02

0055

1 LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION AT SEATING PLANE
2 AT MAXIMUM MATERIAL CONDITION'
PKG.INDEX NOTCH IN LEAD
NOTCH IN CERAMIC DR INK DOT'

0.100 Bse

0020
0.008
0.125
0290

0045

3 DIM "l" TO CENTER OF LEADS

0012
0.160
0.310

WHEN FORMED PARALLEL'

0.020

IS'
0.040

-

Dl

P SUFFIX
PLASTIC PACKAGE
CASE 626-04

. ~

P

NOTE4fFA

~

~~~B
L"''-o ,:J~ b, ~'-

I

MILLIMETERS
MIN
MAX

DIM

4.06

N

~

1981

C

M

N

MAX
698
508

L

.

SEATING -1M

F

G

K

~0~,J\
jG L
J
-ll-o

:!!:t.;-L-II--D

MILLIMETERS

[::::::::]J
.,. B. ·. "·'
A

-l.r{'l

•

Jq;~8

DIM MIN
A 19.05
8
6.22

L SUFFIX

-

. J.

SEAnNG P l : : 7 t F

CERAMIC PACKAGE
CASE 623-03

~-

.I

j

To

--il--J

INCHES
MIN
MAX
0.240 0.215
0.030 0.080
O.OlD 0.019
0.003 0.006
0.0508SC
0.005 0.035
0.015
0.250
0.740

O.OlD

I

1

'

s

:

.

0

1
'lG
J

02 :

:

I :
DIM

'I
-7-'i1

: Q3

CASE 620-02

NOTES

1. LEADSWITHINO.13mm
;0005) RAOIUSOFTRUE

J-II-

POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION

NOTES:
1. DIM "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEL.
2. LEADS WITHIN 0.13 mm
(0.005) RADTUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
(WHEN FORMED PARALLELI

MILLIMETERS

DIM
A
8
C

0
F
G
H

J
K

L
M
N

1-28

IN
940
6.10
3.94
0.38

2. OIM "l"TO CENTER OF
LEADS WHEN FORMED
PARALLEl.
3 PACKAGE CONTOUR

OPTIONALIROUNO OR
SQUARE CORNEAS)
INCHES

MAX

MIN

10.16

0370

660
445

0.240
0155
0.015
0.040

0.51
1.02
1.52
2.54 BSC

0.76
127
0.20
0.30
3.43
2.92
7628SC
10'
051
0.76

MAX
0.400
0.260
0175

0.020
0.060

0.100 BSC

0.030
0.008

0.050
0.012
0.135
0.3008SC
10'
0.020 0.030
0.115

•

PACKAGE OUTLINE DIMENSIONS (continued)

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 632-02

PLASTIC PACKAGE
CASE 646-04

~~

"j; ::::::rn
l

B P

7~

,

-II-oj

F

r-- A~~

rmmw=-1

J

-'IM
N

.

O:Bl
150
0.76
B.25

-

P

J
H

0.785
0.280
0.200
0.023
8se
0.015

_
0.020

BSC
15°
0.030
0.325

NOTE. DIMENSION "L" TO CENTER OF
LEADS WHEN FORMED PARALLEL.

--iJ~ JL

f-- --i f-G

DIM
A
B
C
D
F
G
H
J
K
L
M
N
R

!II

~
_
0.51

~

J--\\--

INCHES
MIN
MAX

19.9
0.660
7.11
0.220
5.08
0.381 0.584 0.015
0.17
1.17

H,

rf-

t

16.8
5.59

B
C
D
F

,

'

SEATING "KiM
PLANE

MILLIMETERS
DIM MIN
MAX

A

~ r,::'~
~ l--~-q-

[LJ

C

\~

HI----iGf-

~A

p

M

0 PLANE

MILLIMETERS
MIN
MAX
18.03 19.56
6.10
6.60
5.0B
0.3B
0.53
1.02
l.lB
2.54 BSe
2.41
1.32
0.3B
0.20
2.92
7.62 BSe
00
150
0.51
B.26

-

-

NOTES:
1. LEAOSWITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. DIMENSION "B" DOES NOT
INCLUDE MOLD FLASH.
4. DIMENSION "R" TO BE
MEASURED AT THE TOP OF
THE LEADS (NOT AT THE
TIPS).

INCHES
MIN
MAX
0.710 0.170
0.240 0.260
0.200
0.015 0.021
0.040 0.070
0.100 BSC
0.052 0.095
O.OOB 0.015
0.115
0.300 BSe
00
150
0.020
0.325

P SUFFIX

P SUFFIX

~;::::::n ~"

JC

P]I,;, "'''''''''~" "f'unlqi~
a~

B

,,~

1,0

-lHf--

Y'" "' ... '" '"

v

v

P

DIM
A
B
C
D
F
G
H

J

K
L
M
N
P
Q

I----

MILLIMETERS
MIN
MAX
31.50 32.13
13.21 13.72
4.70 5.21
0.3B 0.51
1.02
1.52
2.548se
1.65 2.16
0.20 0.30
2.92
3.43
14.99 15.49
100
0.51
1.02
0.13
0.38
0.51
0.76

'-I FI-'

I
I

A

'u'

SEATING

-It...I J

.M

\----

r;=L=J

J~FJ
JLo
H

~ --I

G

I----

SEATING

PLANE

PLANE

INCHES
MIN
MAX
1.240 1.265
0.520 0.540
0.185 0.205
0.015 0.020
0.040 0.060
0.1008SC
0.065 0.085
0.008 0.012
0.115 0.135
0.590 0.610
100
0.020 0.040
0.005 0.015
0.020 0.030

CO,"

CONFIG. (1,8,9, & 16)

\I

R J\
~
~--+
......jG

.
"
"~'"'"

PLASTIC PACKAGE

PLASTIC PACKAGE
CASE 649-03

DIM
A
B
C
D
F
G
H

NOTES.
I. LEADS WITHIN 0.13 mm (0.005)
RADIUS OF TRUE POSITION AT
SEATING PLANEAT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO CENTER OF
LEADS WHEN FORMED PARALLEL.

J

K
L
M
N
R

1-29

MILLIMETERS
MAX
MIN
22.10
6.60
6.10
5.08
0.38
0.53
1.18
2.54 BSC
0.38
2.41
0.20
0.38
.92
7.62 Bse
150
0
0.51
B.26

-

-

INCHES
MIN
MAX
0.870
0.240 0.260
0.200
0.015 0.021
0.070
0.100Bse
0.015 0.095
0.008 0.015
0.115
0.300 BSC
00
150
0.020
0.325

-

KJ

-fLJ

M

I-

NOTES:
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. DIMENSION "8" ODES NOT
INeLUOE MOLD FLASH.
4. "F" DIMENSION IS FOR FULL
LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAD POSITIONS
1,8,9,end 16).
5. DIMENSION "R" TO 8E
MEASURED AT THE TOP OF THE
LEADS (NOT AT THE TIPS),

•

PACKAGE OUTLINE DIMENSIONS (continued)

F SUFFIX
CERAMIC PACKAGE
CASE 650-03

CASE 650-02

A

a

C
0
F

G
H
K
L
N
R

I
I
, I.

-1

L

r.:
' 9

!

~ \

I

I

INCHES
MIN
MAX

9.40 10.16
6.22
6.60
1.52
2.03
0.48
0.38
0.08
0.15
1.27 BSC
0.64
0.89
6.35
9.40
18.92
0.51
0.38

I 0.400

-

I 0.260
I 0.080
I 0.019

.

J

2. LEADS WITHIN 0.13 mm (0.005)
TOTAL OF TRUE POSITION AT
MAXIMUM MATERIAL CONDITION.

0.370

N
R

!J.U,UJJ,U,U.! !

LSUFFIX
CERAMIC PACKAGE

•

.~

CASE 725-01

Tl'lTJL'JL~

_~~::f nf I! ~.
J"-" -+0 J"-, I t'=-.~L.
MILLIMETERS
DIM MIN
MAX
A 31.24 32.26
a 12.70 13.72
4.57
5.59
C
0.38
0.53
D
1.14
F
1.40
G
1.27 asc
1.02
1.52
H
J
0.20
0.30
2.54
3.30
15.24 BSC
L
M
7"
1.52
N
0.51
p
20.32 BSC

K

-

G
H
K
L

-

0.020
0.015

,

A
8
C
D
F

I
I

' I.

-1

-i t

I

I

_-.1

I

J iN

J--R
L

rBiKI~
I
I

J-

He

NOTES:
1. LEAD NO. 1 IDENTIFIED BY TAB
ON LEAD OR DOT ON COVER.

~

I

~I

~

DIM

~

0.250
0.745

I

iN

iBiK-l·

!

_~A

I

,

L

r

B I

,

A

G

.

i---R

MILLIMETERS
MIN MAX

-

_~

I
I
I

~, Itc
DIM

B ,

,
,

L

r

--.

,r.:9

\

-

F SUFFIX
CERAMIC PACKAGE

MILLIMETERS
MIN
MAX

INCHES
MIN
MAX

9.40 10.16
7.24
6.22
1.52
2.03
0.41
0.48
0.08
0.15
1.27 BSC
0.64
O.BS
6.35
9.40
18.92
0.51
0.3B

0.370 0.400
0245 0.2B5
0.060 O.OBO
0.016 0.019
0.003 0.006
0.050 BSC
0.025 0.035
0.250 0.370
0.745
0.020
- 0015

NOTES:
1. LEAD NO. IIOENTIFIED BY TAB
ON LEAD OR DOT ON COVER.
2. LEADS WITHIN 0.13 mm 10.005)
TOTAL OF TRUE POSITION AT
MAXIMUM MATERIAL CONDITION.

-

e:-----:

L SUFFIX

~=.r~:"~ ;:'C:'AG'

~-~~
.

B

e

t LJ

JfN! j!~~fr1
.....,Ft---

I

f--~~D

INCHES
MIN
MAX
1.230 1.270
0.500 0.540
0.180 0.220
0.D15 0.021
0.045 0.055
0.050 BSC
0.040 0.060
0.008 0.012
0.100 0.130
0.600 BSC
7"
0.020 0.060
O.BOO BSC

!

MILLIMETERS
DIM MIN
MAX
A 24.38 25.15
7.49
6.B6
8
4.32
5.08
C
0.38
0.56
D
1.40
1.65
F
2.54 asc
G
0.89
1.40
H
0.20
0.30
J
3.18
4.06
K
7.62 BSC
L
50
150
M
0.76
N
0.51

1-30

i

-IGf-- K

INCHES
MIN
MAX
0.960 0.990
0.270 0.295
0.170 0.200
0.015 0.022

Ii
0.020

8SC
0.055
0.012
0.160
8SC
15°
0.030

MV

NOTES:
1. LEADS WITHIN 0.25 mm (0.010)
OIA , TRUE POSITION AT
SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIM L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIM A AND 8 INCLUDES
MENISCUS.

SUPPLEMENTARY LITERATURE

1. "Improve Fast-logic Designs," by Bill Blood,
Electronic Design, May 10, 1973.
2. "Interface TTL Systems with ECl Circuits," by
George Adams, EDN, September 5,1973.

8. "A CAD Program for High Speed logic Element
Interconnections," by Thomas Balph, William
Blood, and Jerry Prioste, Computer Design,
May 1975.

3. "Increasing Minicomputer Speed with EmitterCoupled logic," by Jon De laune, Computer
Design, February 1974.

9. "Build a Clock Bias Circuit for ECl Flip·
Flops," by T. Balph and H. Gnauden, EDN,
May 5, 1975.

4. "An Engineering Comparison Study MECl
10,000 and Schottky TTL," Motorola Inc.,
1974.

10. "Ml0800 Microprogrammed Demonstrator" by
T. Balph, Electro 77, Session 31.
11. "Get the Best Processor Performance by Build·
ing It From ECl Bit Slices," by Tom Balph
and Bill Blood, Electronic Design, June 7,
1977.

5. "ECl Circuits Drive Light-Emitting Diodes,"
by Bill Blood, EDN, January 20, 1974.
6. "Four-Digit BCD Programmability Featured in
Variable Modulus 60 MHz Counter," by Tom
Balph and Bill Blood, Electronic Design,
March 15,1974.

12. "M10800, A MECl Microprogrammable OnLine Demonstrator," by Tom Balph, Motorola
Inc,1977.
13. "MECl System Design Handbook," by Bill
Blood, Motorola Inc.

7. "Build a low Cost ECl logic Probe," by Tom
Balph, Electronic Design, August 16, 1974.

APPLICATION NOTES
Copies of these Application Notes and Engineering Bulletins can be obtained from your Motorola
representative or authorized distributor, or from Technical I nformation Center, Motorola Semiconductor
Products I nc., P.O. Box 20912, Phoenix, Arizona 85036.

AN-270

Nanosecond Pulse Handling Techniques

AN-701

Understanding MECl 10,000 DC and
AC Data Sheet Specifications

AN·709

M ECl 10,000 Arithmetic Elements,
MC10179, MC10180, MC10181

AN-720

Interfacing with MECL 10,000 Integrated
Circuits

AN-726

Bussing with MECL 10,000 Integrated
Circuits

AN-417B IC Crystal Controlled Oscillators
AN-504

The MC1600 Series MECl 111 Gates

AN-532A MTTl and MECl Avionics Digital Frequency Synthesizer
AN-556

Interconnection Techniques for Motorola's MECl 10,000 Series Emitter
Coupled logic

AN-565

Using Shift Registers as Pulse Delay
Networks

AN-730

A High-Speed FIFO Memory Using the
MECL MCM10143 Register File

AN-567

MECl Positive and Negative logic

AN·742

AN-579

Testing MECl 10,000 Integrated logic
Circuits

A 200 MHz Autroranging MECL-McMOS
Frequency Counter

AN-744

AN-581

An MSI 500 MHz Freuqency Counter
Using MECl and MTTl

A Phase-Locked Loop Tuning System
for Television

AN-746

AN-583

A MECl 10,000 Main Frame Memory
Employing Dynamic MOS RAMs

A 3-1/2 Digit DVM Using an Integrated
Circuit Dual Ramp System

AN-774

Programmable Counters Using the
MC10136 and MC10137 MECl 10,000
Universal Counters

A Simple High Speed Bipolar Microprocessor Illustrates System Design and
Microprogram Techniques

AN·776

The M1 0800 MECl lSI Processor Family

EB-47

Event Counter and Storage latches
for High Frequency, High Resolution
Counters

EB-48

A Time Base and Control logic Subsystem for High Frequency, High Reso·
lution Counters

AN-584

AN-586

Measure Frequency and Propagation
Delay with High Speed MECl Circuits

AN-592

AC Noise Immunity of MECl 10,000
I ntegrated Circuits

AN-700

Simulate MECl System Interconnections
with a Computer Program

1-31

•

SELECTOR
GUIDES

•

•

MECL 10,000
MC10,100110,200 Series (-30 to +850 C)
MC10,500/10,600 Series (-55 to +1250 C)

INTEGRATED CIRCUITS

-

...

';

~.'"

.

.

LSUFFIX
CERAMIC PACKAGE
CASE 620

16 1

'_,owm
,

PLASTIC PACKAGE
CASE 648

CERAMIC PACKAGE
CASE 650

~"u,~
~Y1::'~AMIC
,
.

.

PACKAGE

CERAMIC PACKAGE
CASE 662

. CASE 623

DoviceType

Fun¢tion

C

NOR GATES
Ouad 2-lnput With Strobe

MC10l00
MC10l02
MC10l06
MC10lll
MC102ll

Quad 2·lnput
T"ple 4·3·3·lnput
Dual 3-lnput 3-Qutput

(High Speed)

MC10500
MC10502
MC10506

MC106ll

620, 648, 650
620,648,650
620,648,650
620,648
620,648,650

OR GATES
' MC10l03
MC10ll0
MC102l0

MC106l0

620, 648, 650
620,648
620,648,650

MC10l04
MC10197

MC10504
MC10597

620, 648, 650
620,648,650

Dual 2·Wide 2·3·lnput OR·AND/OR·AND·lnvert
Dual 2·Wide 3·lnput OR·AND
4·Wide 4·3·3·3 Input OR·AND Gate
OR·AND/OR·AND·INVERT Gate
H'ex Buffer with Enable
Hex Inverter with Enable
Hex Inverter/Buffer
High·Speed Dual 3·lnput 3·0utput OR/NOR

MC10l01
MC10l05
MC10l07
MC10l09
MC101l3
MC10117
MC101l8
MC101l9
MC10121
MC10188
MC10189
MC10195
MC10212

MC1050l
MC10505
MC10507
MC10509
MC105l3
MC10517
MC10518
MC105l9
MC1052l

620,648,650
620,648,650
620,648,650
620,648,650
620,648,650
620,648,650
620,648,650
620,648,650
620,648,650
620,648
620,648
620,648,650
620,648,650

TRANSLATORS
Quad MTTL to MECL
Quad MECL to MTTL
Triple MECL to NMOS

MC10124
MC10125
MC10177

MC10524
MC10525

620,648,650
620,648,650
620

MC10114
MC10115
MC10116
MC10216
MC10129

MC105l4
MC10515
MC10516
MC10616

620,648,650
620,648,650
620,648,650
620,648,650
620

Quad 2-lnput
Dual 3-lnput 3·Qutput

(High Speed)
AND GATES
Quad 2·lnput
Hex

MC10503

COMPLEX GATES
Quad OR/NOR
Triple 2·3·2 Input OR/NOR
Triple 2-lnput Exclusive OR/Exclusive NOR
DuaI4·5·lnput'OR/NOR
Quad Exclusive OR

-

MC10595
MC10612

RECEIVERS

Triple line
Quad Line

Triple Line
(High Speed)
Quad Bus

2-2

-

MECL 10,000 INTEGRATED CIRCUITS (continued)
Device T
Function

Case

FLIP-FLOPS
Dual Type 0 Master-Slave
(High Speed)

MC10131
MC10231
MC10135
MC10176

Dual J-K Master-Slave

Hex 0 Master-Slave

MC10531
MC10631
MC10535
MC10576

620,648,650
620, 648, 650
620,648,650
620,648,650

ORIVERS
Triple 4-3-3 Input Bus Driver

MC10123
MC10128

Bus Driver

620,648
620

PARITY CHECKER
MC10160

MC10560

620,648,650

a-Input Encoder

MC10165

MCI0565

620,648,650

DECODERS
Binary to 1-8 (low)
Binary to 1-8 (high)
Dual Binary to 1-4 (low)
Dual Binary to 1-4 (high)

MC10161
MC10162
MC10171
MC10172

MC10561
MC10562
MC10571
MC10572

620,648,650
620,648,650
620,648,650
620,648,650

MCI0132
MC10134
MC10158
MC10159
MC10164
MC10173
MC10174

MC10532
MC10534
MC10558
MC10559
MC10564
MC10574

620, 648, 650
620, 648, 650
620, 648, 650
620, 648, 650
620,648,650
620,648
620,648,650

MC10130
MC10133
MC10153
MC10168
MC10175

MC10530
MC10533
MC10553
MC10568
MC10575

620,648,650
620,648,650
620, 648, 650
620,648,650
620,648,650

12·Blt Panty Generator-Checker

ENCODER

DATA SELECTORS/MUL TlPLEXERS
Dual Multiplexer with Latch and Common Reset

Dual Multiplexer with Latch
Quad 2-lnput Multiplexer (non-inverting)
Quad 2-lnput Multiplexer (Inverting)

8-Llne Multiplexer
Quad 2-lnpul Multiplexer/Latch
Dual 4 to 1 Multiplexer

-

LATCHES
Quad (common clock)
Quad (negative tranSition)
Quad (positive transition)

Quad
QUint

MULTIVIBRATORS
Monostable Multivibrator

620,648

MC10198

SHIFT REGISTERS
Four-Bit Universal

MC10141

MC10541

620, 648, 650

ERROR DETECTION-CORRECTION
IBM Code
Motorola Code

MC10163
MC10193

MC10563
MC10593

620,648,650
620, 648, 650

MC10136
MC10137
MC10138
MC10178

MC10536
MC10537
MC10538
MC10578

620,648,650
620,648,650

MC10170
MC10186
MC10190
MC10191

MC10570
MC10586
MC10590
MC10591

620,648,650
620, 648, 650
620, 648, 650
620,648,650

MC10194

MC10594

620, 648, 650

MC10179
MC10180
MC10181
MC10182
MC10183
MC10287

MC10579
MC10580
MC10581
MC10582

620,648,650
620,648,650
623,649,652
620,648,650
623
620, 648, 650

COUNTERS
Universal Hexadecimal
Universal Decade
Bi-Quinary
Binary

620, 648, 650
620, 648, 650

GENERATOR CHECKER

9 + 2-Bit Parity
Hex "0" Master-Slave/with Reset

Quad MST-to-MECL 10,000
Hex M EC L 10,OOO-to-MST
BUS TRANSCEIVER
Dual Simultaneous

ARITHMETIC FUNCTIONS
Look-Ahead Carry Block
Dual High Speed Adder/Subtractor
4-Bit Logic Unit/Function Generator
2-Bit Logic Unit/Function Generator

4 x 2 Multiplier

2 x 1-Bit Array Multiplier
(High Speed)

2-3

MC10687

II

MECL 10,000 INTEGRATED CIRCUITS (continued)

COMPARATOR
5·BIt Magnitude

MC10166

MC10566

620,648650

MCM10143
MCM10148
MCM10145
MCM10147
MCM10144
MCM10152
MCM10146
MCM10139
MCM10149

MCM10548
MCM10545
MCM10547
MCM10544
MCM10552
MCM10546
MCM10539
MCM10549

623
620,650
620,650
620,650
620,650
620,650
620,650
620,650
620,650

MEMORIES

•

16-Bit Multiport Register F de (RAM) (8 x 2)
64-Bit Random Access (64 xl)
64-Blt Register File (RAM) (16 x 4)
128-Bit Random Access (128 x 1)
256-Bit Random Access (256 x 1)
256-Bit Random Access (256 x 1)
1024-Bit Random Access (1024 x 1)
256-Bit Programmable Read Only (32 x 8)
1024-Bit Programmable Read Only (256 x 4)

MIL-M-38S10

JAN QUALIFIED MECLDEVICES
MIL-M-38510 Device
JM38510/06001BEB, BFB
JM38510106002BEB, BFB
JM38510106003BEB, BFB
JM38510106004BEB, BFB
JM3-=
:[>-=

:[1:

:e>-

2 (6)
Po

~

tpd
3 (7)

~

25 mW typ/gate (No Load)
2.0 ns typ

t+, t- ~ 2.0 ns typ (20% -80%)

15 (3)
VCC1~ Pin 1 (5)

9 (13)

VCC2 ~ Pin 16 (4)
VEE ~ Pin 8 (12)

14 (2)

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE

CERAMIC PACKAGE

CERAMIC PACKAGE

CASE 648
MCl 01 03 only

CASE 620

CASE 650
MC10503 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Current
I nput Current
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

Symbol

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max Unit

IE

-

29

-

29

-

26

-

29

linH

-

415

-

390

-

245

-

245

-

tpd

1.0 3.7
1.1 4.0

1.0
1.1

3.1
3.6

1.0 2.9
1.1 3.3

1.0

3.3
3.7

1.0

29 mAde
245 !lAde
ns

t+,t-

_55°C and +125 0 C test values apply to MC105xx devices only.

3-4

1.1

1.1

3.7
4.0

ns

MC1 01 04/MC1 0504
QUAD 2-INPUT AND GATE

;:;:~2(6)
(10)6~

_

(14)10~

_

Po = 35 mW typ/gate (No load)
tpd

= 2.7

ns typ

t+, t- = 2.0 ns typ (20%-80%)

(11)7~3(7)
(15)11~14(2)

(16)12O--~9(13)

VCC1 = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

(1)13~15(3)

II

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC10104 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10504 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-30°C

-55°C
Characteristic
Power Supply Drain Current
Input Curren~
Pins 4, 7,10,13
Pins 5, 6, 11, 12
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

Symbol
IE

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min

Max

Unit

-

39

-

39

-

35

-

39

-

39

mAdc

-

450
375

-

425
350

-

265
220

-

265
220

-

265
220

/LAde

linH
-

-

ns
tpd
t+, t-

1.0 4.3
1.3 3.8

1.0 4.3
1.5 3.7

·55 0 C and +125 0 C test values apply to MC105xx devices only.

3·5

1.0 4.0
1.5 3.5

1.0 4.2 1.0
1.5 3.6 1.2

4.7
4.1

ns

•

MC1 01 05/MC1 0505
TRIPLE 2-3-2 INPUT
ORINOR GATE

MC1 01 06/MC1 0506
TRIPLE 4-3 ... 3 INPUT
NOR GATE

MC10105/MC10505

MC10106/MC10506

;~,

(8)
(8)

4~3

(9)

5

(13)
(14)
(15)
(1)
(16)

2

(7)
(6)

Po ~ 30 mW typ/gate
(No Load)
tpd

~

(9)

(10)

2.0 ns typ

(11)
(10) t'+, t- ~ 2.0 ns typ (20% to 80%) (13)
(11)
(14)
11
VCCl ~ Pin 1 (5)
(2)
(15) 11
13~14
VCC2 ~ Pin 16 (4)
(16)
12
15 (3)
VEE ~ Pin8 (12)
(1 )
13

~O~~

(7)

1~~2

(6)

12~ 15

(2)

-

P SUFFIX

PLASTIC PACKAGE
CASE 648
MC10l05 and
MC10106 only

(3)

14

-

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10505 and
MC10506 only

L SUFFIX

CERAMIC PACKAGE
CASE 620

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Current
Input Current

Symbol

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

-

24

-

23

-

21

_.

23

-

24

mAdc

linH

-

450

-

425

-

265

-

265

-

265

}lAde

Switching Times
Propagation Delay
Rise Time, Fall Time

Unit

IE

ns
tpd

1.0

3.7

1.0

3.1

1.0

2.9

1.0

3.3

1.0

3.7

t+, t-

1.0

4.0

1.1

3.6

1.1

3.3

1.1

3.7

1.0

4.0

(20% to 80%)
-55°C and +125 0 C test values apply to MC105xx devices only.

3-6

ns

MC10107/MC10507
TRIPLE 2-INPUT EXCLUSIVE
OR/EXCLUSIVE NOR

(8)
(9)
. (13)
(11)

4~2

(6)

5

(7)

3

9~11

(15)

7

10

(14)

(2)

14~12

(16)

(3)

15

(1 )

13

Po ~ 40 mW typ/gate (No Load)
tpd

~

2.8 ns typ

t+, t- ~ 2.5 ns typ (20% to 80%)

VCC1 ~ Pin 1 (5)
VCC2 ~ Pin 16 (4)
VEE~Pin8 (12)

•
P SUFFIX

L SUFFIX

F SUFFIX

CERAMIC PACKAGE
CASE 648

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10507 only

MCl 01 07 only
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-30°C

-55°C
Characteristic
Power Supply Drain Current
Input Current
Pins 4, 9,14
Pins 5, 7,15
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

Symbol
IE

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min

Max

Unit

-

31

-

31

-

28

-

31

-

31

mAdc

-

450
375

-

-

265
220

-

265
220

-

-

425
350

-

265
220

1.1
1.1

3.8
3.5

1.1
1.1

3.7
3.5

1.1
1.1

4.0
3.8

1.0
1.0

/-lAde

linH

ns
tpd
t+, t

1.0 4.5
1.0 4.3

-55°C and +125 0 C test values apply to MC105xx devices only.

3-7

4.5
4.J

ns

•

MC1 01 09/MC1 0509
DUAL 4-5 INPUT
ORINOR GATE

(8)
(9)
(10)
(11 )
(13)

:3=t=''''
6

-

2 (6)

7

(16)

'~

(1)

13

(14)
(15)

10

11
12

.

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10109 only

14 (2)
-15 (3)

tpd = 2.0 ns typ
Po = 30 mW typ/gate (No Load)
t+, t- = 2.0 ns typ (20% to 80%)

L SUFFIX
CERAMIC PACKAGE
CASE 620

~

VCC1 = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10509 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Current
Input Current

Symbol

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

Unit

IE

-

16

-

15

-

14

-

15

-

16

mAde

linH

-

450

-

425

-

265

-

265

-

265

/LAde

Switching Times

ns

Propagation Delay

tpd

1.0

3.7

1.0

3.1

1.0

2.9

1.0

3.3

1.0

3.7

Rise Time, Fall Time

t+, t-

1.0

4.0

1.1

3.6

1.1

3.3

1.1

3.7

1.0

4.0

(20% to 80%)
-55 0 C and +125 0 C test values apply to MC105xx devices only.

3-8

ns

MC10110
DUAL 3-INPUT 3-0UTPUT
OR GATE

MC10111
DUAL 3-INPUT 3-0UTPUT
NOR GATE

MC10110

MC10111

~~2
7

3

4

Po

~

80 mW typ/gate (No Load)

tpd = 2.4 ns typ (All Outputs Loaded)

t+, t- = 2.2 ns typ (20% to 80%) (All Outputs Loaded)

1~~12
11

;·6 ~

VCC1 = 1,15
VCC2 ~ 16

13

14

VEE = 8

•

12

13

14

11

Th ree V CC pins are provided
and each one should be used.

P SUFFIX
PLASTIC PACKAGE
CASE 648

L SUFFIX
CERAMIC PACKAGE
CASE 620

Numbers at ends of terminals denote pin numbers for Land P packages.

+25 0 C

-30°C
Characteristic
Power Supply Drain Current
Input Cu rrent
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

Symbol

Min

Max

IE

-

42

linH

-

680

tpd

1.4
1.0

3.5
3.5

+85 0 C

Max

Min

Max

Unit

-

38

-

42

mAdc

-

425

-

425

!lAde

3.5
3.5

1.5
1.2

3.8
3.8

Min

ns

t+, t-

3-9

1.4
1.1

ns

MC10113/MC10513
QUAD EXCLUSIVE
OR GATE

TRUTH TABLE
9 (13)
(8) 4

2 (6)

(9) 5

(10) 6

3 (7)

(11) 7

•

A B E
L L
L H
H L
H H

'" '"

L
L
L
L
H

'" = Don't

OUTPUT
L
H
H
L
L

Care

VCCl = Pin 1 (5)
VCC2
VEE

(14) 10

=
=

Pin 16 (4)
Pin 8 (12)

14 (2)
(15) 11

".

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10113 only

-

L SUFFIX
CERAMIC PACKAGE
CASE 620

PD = 175 mW typ/pkg (No Load)
tpd = 2.5 ns typ

(16) 12
15 (3)

t+, t-

(1) 13

=

F SUFFIX

2.0 ns :typ (20%-80%)

CERAMIC PACKAGE
CASE 650
MC10513 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55 0 e
Characteristic

Symbol

'Power Supply Drain Current
Input .current
Pins4,7,10,13
Pins 5, 6, 11, 12
Pin 9
Switching Times
Propagatio'n Delay,
Independent Inputs
Enable Input
Rise Time, Fall Time
(20% to 80%)

IE

-30 0 e

+85 0 C

+12Soe

-

46

-

46

-

42

-

46

-

46

-

450
375
925

-

425
350
870

-

265
220
545

-

265
220
545

-

265
220
545

Unit
mAde
!lAde

linH

,

+25 0 e

Min Max Min Max Min Max Min Max Min Max

-

-

ns
tpd

t+,t-

1.1 4.9
1.3 5.2
1.1 4.3

.,55 0 C and +125 0 C test values apply to MC105xx devices only.

3-10

1.1 4.7
1.3 5.2
1.1 4.2

1.3 4.5
1.5 5.0
1.1 3.9

1.3 5.0
1.5 5.5
1.1 4.4

1.3
1.5
1.1

5.3
5.8
4.6

ns

MC10114/MC10514
TRIPLE LINE RECEIVER

The

(8)4~2(6)

(9)5~3(7)
(13)

9~6 (10)

(14)10~7

(11)

(H~) 12~14(2)

VCCl = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

(1)13~15(3)
1'----11 (15)

tpd

=

MC1 0114/MCl 0514

is

designed

for

use in sensing differential signals over long lines.
An active current source and translated emitter
follower inputs provide the line receiver with
a common mode noise rejection limit of one
volt in either the positive or the negative direction. This allows a large amount of common
mode noise immunity for extra long lines.
Another feature is that the NOR outputs
go to a logic lo~ level whenever the inputs are
left floating.
This device is useful in high speed central
processors, minicomputers, peripheral controllers, digital communication systems, testing and
instrumentation systems_ It can also be used for
MOS to MECL interfacing and is ideal as a
sense amplifier for MOS RAMs.
A VSS reference is provided which is
useful in making a Schmitt trigger, allowing
single-ended driving of the inputs, or other
applications where a stable reference voltage
is necessary.

2.4 ns typ (Single-Ended Input)

tpd = 2.0 ns typ (Differential Input)
PD = 145 mW typ/pkg

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MCl 0114 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10514 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package_

3-11

•

II
ELECTRICAL CHARACTERISTICS

TEST VOLTAGE VALUES
@Test
Temperature

VEE

V,Hmax
MC10114

-30 0 C

-0.890

-1.890

-1.205

+25 0 C

-0.810

-1.850

+85 0 C

-0.700

-1.825

-1.890

-5.2

-1.810

-2.850

-5.2

-1.700

-2.825

-5.2

-1.500

From

+0.110

-0.890

-1.890

-1.105

-1.475

Pin

+0.190

-0.850

-1.035

-1.440

11

+0.300

-0.825

MC10514
-55 0 C

-0.880

-1.920

-1.255

-1.510

From

+0.120

-0.920

-1.880

-2.920

-5.2

+25 0 C

-0.780

-1.850

-1.105

-1.475

Pin 11

+0.220

-0.850

-1.780

-2.850

-5.2

+125 0 C

-0.630

-1.820

-1.000

-1.400

(151

+0.370

-0.820

-1.630

-2:820

-5.2

-55°C
Characteristic

Power Supply Drain Current
Input Current

Symbol

-30°C

+85 0 C

+25 0 C

+125 0 C

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

IE

Min
-

39

-

39

-

35

-

39

-

39

mAdc

Vin =VIH max (Pins4,9, 121, VIL min
(Pins 5, 10, 131

linH

-

80

-

70

-

45

-

45

-

45

!lAdc

Test one input at a time. Vin

Conditions

=:

VIH max to

P.U.T. and VIL min to the other input of
that gate.

Cf

'"

ICBO
Reference Voltage

Common Mode Rejection Test*
MC10114
MC10514
MC10114
MC10514
Switching Times
Propagation Delay
Rise Time, Fall Time

VBB

-

1.5

-

1.5

-

1.0

VIHL
VILL

=:

=:
=:

1.0

-

1.0

VOH

-1.060 -0.890 -0.960 -0.810 -0.890 -0.700
-1.080 -0.880
-0.930 -0.780
-0.825 -0.630
-

VOL

-1.890 -1.675 -1.850 -1.650 -1.825 -1.615
-1.920 -1.655
-1.850 -1.620
-1.820 -1.545

tpd

1.0

4.3

1.0

4.4

1.0

4.0

0.9

4.3

1.0

4.7

t+, t-

1.3

3.8

1.5

3.8

1.5

3.5

1.5

3.7

1.2

4.1

-VIHH = Input logic "1" level shifted positive one volt for common mode rejection tests.
V I LH

-

-1.440 -1.320 -1.420 -1.280 -1.350 -1.230 -1.295 -1.150 -1.240 -1.120

Input logic "0" level shifted positive one volt for common mode rejection tests.
Input logic "1"'evel shifted negative one volt for common mode rejection tests.
Input logic "0" level shifted negative one volt for common mode rejection tests.

-550C and +125 0 C test values apply to MC105xx devices only.

s
....
o
....
....

("')

!lAdc

Test one input at a time. Vin - VEE

Vdc

One input from each gate tied to VSS (Pin 111.

Vdc

Vin = VIHH or VIHL to one input of each
gate under test and VILH or VILL, respec·
tively, to the other input of each gate.

Vdc
ns

For single·ended input testing, one input from

ns

20% to 80%

each gate must be tied to VSS (Pin 111.

~

S

("')
....
o
C1
....
~

MC10115/MC10515
QUAD LINE RECEIVER

MC10116/MC10516
TRIPLE LINE RECEIVER

MC10115/MC10515
(8)

45

~--

(9)~

(11)7~
(10)

2

3

(6)

(7)

6

(14)10~

14 (2)

(1)13~15(3)
L-v

bias supply (VBS) is made available to make
the device useful as a Schmitt trigger, or in
other appl ications where a stable reference
voltage is necessary,

(8)4~2(6)

(9)5~3(7)
(13)9~6(10)

Active current sources provide these receivers (14)

(15) 11

(16) 12

MC10116/MC10516

These receivers are designed for use in
sensing differential signals over long lines. The

9

(13)

10~7(11)

with excellent common mode noise rejection. If (16) 12~14 (2)
any ampl ifier in a package is not used, one
(1)13~15(3)
input of that ampl ifier must be connected to
11 (15)
V BB to prevent upsetting the current source
BB
bias network.

~v

BS

VCCl = Pin 1 (5)

tpd = 2.0 ns typ
PD = 110 mW typ/pkg (No Load)

tpd = 2.0 ns typ
PD = 85 mW typ/pkg (No Load)

VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC10115and
MC10116 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10515 and
MC10516 only

Numbers at ends of terminals denote pin numbers for Land P package
Numbers in parenthesis denote pin numbers for F package
.

One input from each gate must be tied to VBB during testing.
-55°C
Characteristic
Power Supply Drain Current

Symbol

+25 0 C

-30°C
Min

Max

Min

Max

+125 0 C

+85 0 C
Min

Max

Min

Max

linH

VBB

29
24

-

29
23

-

-

26
21

-

29
23

-

-

29
24

95
150
95
95
1.0
1.0
1.0
1.5
1.5
-1.440 -1.320 -1.420 -1.280 -1.350 -1.230 -1.295 -1.150 -1.240 -1.120
-

165

-

/lAde
/lAde
Vde
ns

SWitching Times
Propagation Delay
Rise Time, Fall Time

Unit

mAde

ICBO

Reference Voltage

Max

IE

MC10115/10515
MC10116/10516
Input Current

Min

tpd
t+,t-

1.0
1.0

3.5
3.9

1.0
1.1

3.1
3.6

(20% to 80%)
·55 0 C and +125 0 C test values apply to MC105xx devices only.

3-13

1.0
1.1

2.9
3.3

1.0
1.1

3.3
3.7

1.0
1.0

4.0
4.4

ns

•

MC10117/MC10517
DUAL 2-WIDE 2-3-INPUT
OR-AND/OR-AND-INVERT GATE

(S) 4
(9) 5

..
-

3 (7)
2 (6) ,
(10) 6
'(11) 7
VCC1 = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE=PinS(12)

(13) 9

•

(14) 10
(15) 11
14 (2)
15 (3)
(16) 12
(1) 13

2.3 ns tYP

=

t+, t-

L SUFFIX
CERAMIC PACKAGE
CASE 620

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10517 only

Po = 100 mW tYP/pkg (No Load)
tpd

P SUFFIX
PLASTIC PACKAGE
CASE 64S
MC10117 only

= 2.2 ns typ (20% to SO%)

Numbers at ends of terminals denote pin numbers for Land P package

Numbers in parenthesis denote pin numbers for F package

-55°C
Characteristic
Power Supply, Drain Current
Input Current

Symbol
IE

Rise Time, Fall Time
(20% to 80%)

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min

Max

Unit

-

29

-

29

-

26

-

29

-

29

mAde

-

390
425

245

-

245

-

245

-

560

-

-

265
350

-

595

265
350

-

-

-

-

-

415
450

265
350

1.4
0.9

3.9
4.1

1.4

3.4
4.0

1.4
1.1

!lAde

linH

Pins4, 5,12,13
Pins 6, 7,10,11
Pin 9
Switching Times
Propagation Delay

-30°C

-

ns
tpd
t+, t-

1.1 3.5
1.0 4.1

-55°C and +125 0 C test values apply to MC105xx devices only.

3-14

1.1

3.8

1.2

4.6

0.9

3.5
4.1

ns

MC1 0118/MC1 0518
DUAL 2-WIDE 3.,.INPUT
OR-AND GATE

(7)

3

(8)

4

(9)

5

(10)

6

( 11)

7

(13)

9

= 100 mW tYP/pkg (No Load)
= 2.3 ns tYP
t+, t- = 2.5 ns tYP (20% to 80%)
PD

tpd

2 (6)

(14) 10
( 15) 11
(1 )

13

(2)

14

= Pin 1 (5)
= Pin 16 (4)
VEE = Pin 8 (12)

VCCl
VCC2

15 (3)

(16) 12

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10118 only

L SUFFIX
CERAMIC PACKAGE
CASE 620

•

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10518 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic

Symbol

Power Supply Drain Current

IE

-30°C

+25 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Ma,t

-.

-

29

--

29

Pins 3, 4,5,12,13,14

-

415

-

390

-

Pins 6,7,10, 11
.pin 9

-

450

-

425

-

-

595

-

560

-

tpd

1.1

3.5

1.4

3.9

1.4

t+,t

1.3

4.1

0.8

4.1

1.5

I nput Current

+85 0 C

26

-

29

-

29

245

-

245

-

245

265

-

265

350

-

350

-

350

3.4

1.4

3.8

1.2

3.5

4.0

1.5

4.6

1.2

4.0

MAde

linH
.

265

Switching Times
Propagation Delay
Rise Time, Fall Time

Unit
mAde

ns

(20% to 80%)
-55°C and +125 0 C test values apply to MC105xx devices only.

3-15

MC10119/MC10519
4-WIDE 4-3-3-3-INPUT
OR-AND GATE

(7) 3

(8)

4---'~

(9) 5---'-1

(10) 6

(11) 7----,L......_
(13) 9----'-..

V CC1
VCC2

(14) 10

•

2 (6)

=
=

1 (5)
16 (4)

VEE = 8 (12)

(15) 11 - - - t

PD

(16) 12 _ _-..Ie--

tpd = 2.3 ns typ

= 100

mW tYP/pkg (No Load)

t+, t- = 2.5 ns tYP (20% to 80%)

(1) 13

(2) 1 4 - - - t
(3) 15

P SUFFIX

l SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648

CERAMIC PACKAGE
CASE 620

,CERAMIC PACKAGE
CASE 650
MC10519 only

MC101190nly
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic

Symbol

Power Supply Drain Current

IE

I nput Current
Pins 3, 4, 5, 6, 7,9, 11, 12,
13,14,15
Pin 10

+2S oC

+8S oC

+12S oC

Min Max Min Max Min Max Min Max Min Max
-

29

-

29

-

26

-

29

-

29

Unit
mAdc
MAdc

linH

Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

-30°C

-

415
525

-

-

245
310

-

245
310

-

245
310

1.1

3.5

1.4 3.9

1.4

3.4

1.4

3.8

1.2

3.5

1.3

4.1

0.8 4.1

1.5

4.0

1.5

4.6

1.2

4.3

390
495

ns
I

tpd
t+,t

-55°C and + 125°C test values apply to MC105xx devices only.

3-16

ns

MC10121/MC10521
4-WIDE OR-AND/OR-AND-INVERT

(8) 4

(9) 5 - - - 1
(10)

6----'~-

(11) 7--.....,1...-_
(13)9 _ _-1

VCCl
VCC2

2 (6)

(14) 10

= Pin
= Pin

1 (5)
16 (4)

VEE = Pin8 (12)

3 (7)

•

Po = 100 mW typ/pkg (No Load)

(15) 1 1 - - - 1

tpd = 2.3 ns tYP

(16) 1 2 - - - - , - -

t+, t-

=

2.5 ns tYP (20% to 80%)

(1) 13

(2) 1 4 - - - 1
(3) 15 _----'o-r-

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC10121 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10521 only

Numbers at ends of terminals denote pin number for Land P package
Numbers in parenthesis denote pin numbers for F package

-55°C
Characteristic

Symbol

Power Supply Drain Currerit

IE

Input Current
Pins3, 4,5,6,7,9,11,12,
13,14,15
Pin 10
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

.c30oC

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max
-

29

-

29

-

26

-

29

-

29

Unit
mAde
MAde

linH

-

415
525

-

-

245
310

-

245
310

1.2

3.6

1.4 3.9

1.4

3.4

1.4

3.8 1.1

3.5

1.0

4.5

0.9

4.1

1.1

4.0

1.1

4.6

0.9

4.4

390
495

-

245
310
ns

tpd
t+,r-

-55°C and +125 0 C test values apply to MC 105xx devices only.

3-17

ns

MC10123
TRIPLE 4-3-3 INPUT
BUS DRIVER

1~~2

11~
'12~
13

15

14
VCC1 = Pin 1
VCC2 = Pin 16

,VEE -PinS

•

PD ~ 310 mW typ/pkg
(No Load)
tpd

~

3.0 ns typ

The MC10123 consists of three NOR gates
designed for bus driving applications on card or
between cards. Output low logic levels are
specified with VOL';; -2.0 Vdc so that the bus
may be terminated to' -2.0 Vdc. The gate output,
when low, appears as a high impedance to the
bus, because the output emitter-followers of the
MC10123 are "turned-off". This eliminates
discontinuities in the characteristic impedance
of the bus.
The VOH level is specified when driving a
25-ohm load terminated to -2.0 Vdc, the equivahint of a 50-ohm bus terminated at both ends.
Although 2,5 ohms is the lowest characteristic
impedance that can be driven by the MC10123,
higher impeqance values may be used with this
part. A typical 50-ohm bus is shown in Figure 1.

P SUFFIX
PLASTIC PACKAGE
CASE 648

L SUFFIX
CERAMIC PACKAGE
CASE 620

t+, t- ~ 2.5 ns typ (20%

to 80%)

FIGURE 1 - 50-OHM BUS DRIVER
1/3 MC10123

1/3 MC10123

1/3 MC10123

20 - 50 n

~---1----~------1-----~-----1----~----~
50n

50n

-2.0 Vdc

-2.0 Vdc

RECEI)lERS (MECL Gatesl

Outputs are terminated through a 25-ohm resistor to -2.1 volts:
-30 oC

,

Characteristic

Power Supply Drain Current

Min

Max

Min

Max

Min

Max

Unit

IE

-

82

-

75

-

82

mAde

Input Current

linH

Logic "0" Output Voltage

VOL

Logic "0" Threshold Voltage
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

+~l5oC

+2S o C

Symbol

- ,
350
220
220
-2.100 -2.030 -2.100 -2.030 -2.100 -2.030

/LAdc
Vdc

VOLA

-

-2.010

-

-2.010

-

-2.010

tpd
t-, t+

'1.2
1.0

4.6
3.7

1.2
1.0

4.4
3.5

1.2
1.0

. 4.8
3.9

Vde
ns
ns

MC1 0124/MC1 0524
QUAD TTL-TO-MECL
TRANSLATOR

(9) 5

4

(8)

(10) 6

2

(6)

(11) 7

3

(7)

1

(5)

(14) 10

(15) 11

= Pin

16 (4)

VCC (+5.0 Vdc)

15 (3)

VEE (-5.2 Vdc)

= Pin
= Pin

9 (13)
8 (12)

13 (1)
14 (2)

= 380

PD

Gnd

12(16)

VCCmax

= 7.0

Vdc

mW typ/pkg (No Load)

tpd = 3.5 ns typ (+ 1.5 Vdc in to 50% out)
t+, t- = 2.5 ns typ (20% to 80%)

P SUFFIX
CERAMIC PACKAGE
CASE 648
MC10124 only

The M C1 0124/M C1 0524 is a quad translator
for interfacing data and control signals between
a saturated logic section and the M EC L section
of digital systems. The device has TTL compatible inputs, and M EC L complementary
open-emitter outputs that allow use as an
inverti ng/non-i nverting
translator
or
as
a
differential line driver. When the common
strobe input is at the low logic level, it forces
all true outputs to a M ECL low logic state and
all inverting outputs to a MECL high logic state.
Power supply requirements are ground, + 5.0
Volts, and -5.2 Volts. The dc levels are standard or Schottky TTL in, MECL 10,000 out.
An advantage of this device is that TTL level
information can be transmitted differentially,
via balanced twisted pair lines, to the MECL
equipment, where the signal can be received
by any of the M ECL line receivers or the
MC10125 MECL to TTL translator or the
MC10177 MECL to MaS translator.

L SUFFIX

F SUFFIX

CERAMIC PACKAGE

CERAMIC PACKAGE

CASE 620

CASE 650
MC10524 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
V out
NAND

V out

AND

Coax

Coax

Coax

Input

Unused outputs
connected to a
50-ohm resistor
to ground (1 OO-ohm
for MC105XX)

Pulse Generator

PROPAGATION DELAY
Input Pulse
t+ = t- = 5.5 ±O.5 ns
(10 to 90%)

O.1I'F
50-ohm terminatIon to ground lo-

cated

In

each scope chan nel mput

All input and output cantes to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to mput
pin and TP out to output pin.

1

16

---Ii""
l~~vdc

+2.0 Vdc

Vee

V out AND

VoutNAND

'50 ohm, MC105XX only.
NOTE: All power supply and logic levels are shown shifted 2 volts positive.

3-19

•

I
s:

ELECTRICAL CHARACTERISTICS

.n
....
o....

TEST VOL TAGE/CURRENT VALUES
Test
Temperature

I

Volts

@l

VIHmin

I Vilmax I

VRH

1

1

VF

1

VR

Vcc

I

I

VEE

mA
111

I

112

N

~

MC10124

s:

-30°C

+2.0

+1.1

+4.0

+0.4

+2:4

+5.0

-5.2

-10

-20

+25 0 C

+1.8

+1.1

+4.0

+0.4

+2.4

+5.0

-5.2

-10

-20

+1.8

+0.8

+4.0

+0.4

+2.4

+5.0

-5.2

-10

-20 .

+ 1.1

+4.0

+0.4

+2.4

+5.0

• -5.2

-10

-20

+85 0 C

-55°C

w

i\J

o

.j::o

-55°C

+2.0

+25 0 C

+1.8

+1.1

+4.0

+0.4

+2.4

+5.0

-5.2

-10

-20

+125 0 C

+1.8

+0.8

+4.0

+0.4"

+2.4

+5.0

-5.2

-10

-20

+85 0 C

+25 0 C

-30°C

+125 0 C

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Negative Power
Supply Drain
Current

IE

-

72

-

72

-

66

-

72

-

72

mAde

All inputs and outputs open.

Positive Power
Supply Drain
Current

ICCH

-

16

-

16

mAde

Vin = VRH all inputs.

25

25

-

18

25

-

18

-

-

16

25

25

mAde

Vin (strobe) - VF

/-lAde
200

-

200

200

-

200

Vin = VR (strobe),
VF (single.inputs)

50

-

50

Reverse Current
Strobe Input

ICCl
IR

-

Single Inputs
Forward Current
Strobe Input

50

-

IF

Single Inputs
Input 8reakdown
Voltage

50

8Vin

-

-12.8

-12.8

-3.2

-

5.5

-

5.5

-12.8

-3.2

-

-

5.5

-

200
50

-

-12.8

-3.2

-

-3.2

-

5.5

-

-12.8

-3.2

-

-

5.5

Switching Times
Propagation Delay
Rise Time,
Fall Time

VI

-

-1.5

-

-1.5

-

tpd

1.0

8.0

1.0

6.8

1.0

t+, t-

1.0

4.5

1.0

4.2

1.1

Conditions

Vin = VR (strobe), VF (P.U.T.)
Vde

At lin - +1.0 mAde.
Vin (strobe) = VF while testing
single inputs .

-1.5

-

-1.5

6.0

1.0

6.8

; .0

8.0

+ 1.5 Vde in to 50% out

3.9

1.1

4.3

1.0

4.5

20% to 80%

Vde

Test one input at a time.
111 (single inputs), 112 (strobe).

ns

-55°C and + 125°C test values apply to MC1 05XX devices only.

I

Vin = VF (strobe), VR (single
inputs)

-

-1.5,

i

Vin = VF (strobe), VR (P.U.T.l
mAde

..
Clamp Input
Voltage

en
N

MC10524

Characteristic

·n
....
o

I

MC1 0125/MC1 0525
QUAD MECL-TO-TTL
TRANSLATOR
The M C1 0125/MC1 0525 is a quad translator
(6)
(7)

(10)

Gnd = Pin 16 (4)

(11)

VCC (+5.0 Vdc) = Pin 9 (13)

(14)10~~

(15)11~12(16)
(2)

(3)

VEE (-5.2 Vdc) = Pin 8 (12)

14~~
15~13(1)

~1(5)
VBB

Po = 380 mW typ/pkg (No Load)
tpd = 4.5 ns typ (50% to + 1.5 Vdc out)

t+, t- = 2.5 ns typ (1 V to 2 V)
VCCmax = + 7.0 Vdc

-

for interfacing data and control signals between
the M EC L section and saturated logic sections
of digital systems. The MC10125 incorporates
differential inputs and Schottky TTL "totem
pole" outputs. Differential inputs allow for use
as an inverting/non-inverting. translator or as
a differential line receiver. The VSS reference
voltage is availabe on pin 1 for use in singleended input biasing. The outputs go to a low
logic level whenever the inputs are left floating.
Power supply requirements are ground,
+5.0 Volts and -5.2 Volts. The MC10125 has a
fanout of 10 TT L loads. The dc levels are
MECL 10,000 in and Schottky TTL or standard
TTL out. This device has an input common
mode noise rejection of ± 1.0 Volt.
An advantage of this device is that MECL
level information can be received, via balanced
twisted pair lines, in the TTL equipment. This
isolates the MECL logic from the noisy TTL
environment.

L SUFFIX
P SUFFIX

CERAM)C PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648
MC10125 only

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10525 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vcc

25°C

VCC

V out

5"~

@

+5.0 Vdc

Coax

IO. 1 1'F

r--

Input

--,

280
450

I
Pulse Generator
All Diodes

Input Pulse

t+

= t- = 2.0 ±O.2

lC L

ns

MMD7000
or Equiv.

(20 to 80%)
-1.69 Vdc

I

0--+....-1'-'''''<:'''

I

I
I

50-ohm termination to ground lo-

cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.

PROPAGATION DELAY

L~-'-l1J
1~

8

lO.I1'F
V out

CL :::: 25 pF. including t8St fixture

-5.2 Vdc

VEE

3-21

•

II
...so

ELECTRICAL CHARACTERISTICS

(")

...

TEST VOLAGE AND CURRENT VALUES
@ Test
Temperature

I

Volts
VIHmax

I VILmin IVIHAmin IVILAmax I VIHH* I

VILH*

I

VIHL *

I

I

VILL'

VBB

I

VCC

I

I

VEE

-...
N
tTl

rnA
IOH

I

S

IOL

(")

MC10125
-30°C

-0.890

-1.890

-1.205

-1.500

+0.110

-0.890

-1.890

'-2.890

From

+5.0

-5.2

-2.0

+20

+25 0 C

-0.810

-1.850

-1.105

-1.475

+0.190

-0.850

-1.810

-2.850

Pin

+5.0

-5.2

-2.0

+20

+85 0 C

-0.700

-1.825

-1.035

-1.440

+0.300

-0.825

-1.700

-2.825

1

+5.0

-5.2

-2.0

+20

o

CJ1
N

CJ1

MC10525
-55°C

-0.880

-1.920

-1.255

-1.510

+0.120

-0.920

-1.880

-2.920

From

+5.0

-5.2

-2.0

+12

+25 0 C

-0.780

-1.850

-1.105

-1.475

+0.220

-0.850

-1.780

-2.850

Pin

+5.0

-5.2

-2.0

+12

+125 0 C

-0.630

-1.820

-1.000

-1.400

+0.370

-0.820

-1.630

-2.820

1

+5.0

-5.2

-2.0

+12

-30°C

-55°C

w
N

I'.l

+25 0 C

+125 0 C

+85 0 C

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit_

Negative Power
Supply Drain
Current

IE

-

44

-

44

-

40

-

44

-

44

mAdc

Positive Power
Supply Drain
Current

ICCH

-

52

-

52

-

52

-

52

-

52

mAdc

Characteristic

Conditions
Vin = VBB (Pins 3, 7, 11, 15),
VEE (Pins 2,6,10,14)
Vin

= VBS

(Pins 3, 7, 11, 15),

-VIH max (Pins 2, 6,10,14)
ICCl

-

39

-

39

-

39

-

39

-

39

mAdc

Vin - VBB (Pins 3, 7, 11, 15),
VEE (Pins 2, 6,10,14)

Input Current

linH

-

195

-

180

-

115

-

115

-

115

/lAde

One input from each gate tied to
VSS while the other inp.uts are
tested one at a time, Vin = VIH
max.

Input Leakage
Current

ICBO

-

1.5

-

1.5

-

1.0

-

1.0

-

1.0

/lAdc

One input from eaeh gate tied to
VaB while the other inputs are
tested one at a time, Vin = VEE.

lOS

40

100

40

100

40

40

100

40

100

mA

Vin'" VBB (Pins 3, 7,11,15),
VIL min (Pins 2, 6, la, 14).
Connect outputs to ground, one
at a time.

Short-Circuit
Current

-

L._.

. 100

i

----

-550C and + 125°C test values apply to MC1 05XX devices only.

(continued on next page)

s(")

ELECTRICAL CHARACTERISTICS (continued)

->

o....

-55°C
Characteristic
High Output
Voltage

~

Min

Max

VOH

2.5

-

Min
·2.5

+25 0 C

+85 0 C

Min

Max

Min

Max

Min

Max

Unit

Conditions

-

2.5

-

2.5

-

2.5

-

Vdc

Vin = VIL min (Pins 2,6,10,14),
VIH max (Pins 3, 7,11,15).

-

0.5

-

0.5

-

0.5

-

0.5

-

0.5

Vdc

Vin = VIL min (Pins 3, 7, 11,15),
VIH max (Pins 2, 6,10,14).

High Threshold
Voltage

VOHA

' 2.5

-

2.5

-

2.5

-

2.5

-

2.5

-

Vdc

Vin - VSB (Pins 3, 7,11,15),
VILA max (Pins 2, 6,10,14, one
at a time).

Low Threshold
Voltage

VOLA

-

0.5

-

0.5

-

0.5

-

0.5

-

0.5

Vdc

Vin = VSS (Pins 3, 7, 11,15),
VIHA max (Pins 2,6,10,14, one
at a time).

Indeterminate Input
Protection Tests

VOLS1

-

0.5

-

0.5

-

0.5

-

0.5

-

0.5

Vdc

Vin = VEE to both inputs of each
gate, one gate at a time.

-

0.5

-

0.5

-

0.5

--

0.5

-

0.5

Vdc

All inputs open.

Vdc

One input from each gate tied
to VBS (Pin 1).
Vin = VIHH or VIHL to one input
of each gate under test and VILH'or
VILL, respectively, to the other
input of each gate.

VOLS2
Reference Voltage

VSS

-1.440 -1.320 -1.420 -1.280 -1.350 -1.230 -1.295 -1.150 -1.240 -1.120

Common Mode
Rejection Tests'

VOH

2.5

-

2.5

~

2.5

-

2.5

-

2.5

-

Vdc

VOL

-

0.5

-

0.5

-

0.5

-

0.5

-

0.5

Vdc

tpd

1.0

6.5

1.0

6.0

1.0

6.0

1.0

6.0

1.0

7.0

t+, t-

-

4.5

-

3.3

-

3.3

-

3.3

-

5.3

w

Switching Times
Propagation
Delay

Rise Time,
Fall Time

U1

+125 0 C

Max

VOL

Low Output
Voltage

w

-30°C

Symbol

I'J

ns

'VIHH = Input logic "1" level shifted positive one volt for common mode rejection tests.
VILH = Input logic "0" level shifted positive one volt for common mode rejection tests.
VIHL = Input logic "1" level shifted negative one volt for common mode rejection tests.
VI LL = Input logic "0" level shifted negative one volt for common mode rejection tests.

-55°C arid + 125°C test values apply to MC1 05XX devices only.

II

50% in to + 1.5 Vdc out. For
single'ended input testing, one
input from each gate must be tied
to VBB (Pin 1).
ns

+1.0 Vdc to +2.0 Vdc

S

....

(")

o

U1

I'J

U1

MC10128
DUAL BUS DRIVER
(MECL 10,000 TO TTL/IBM)

The MC10128 is designed to provide outputs which are compatible with I BM-type bus
levels; or, if desired, it will drive TTL type loads
and/or provide TTL. three-state outputs. The
inputs accept MECL 10,000 levels. The

circuit is used in the TTL mode. When in the
high state the disable input causes the output to
exhibit a high impedance state when it would
normally be a positive logic" 1" state. When the
strobe is in the high state it inhibits the output
data to the I ow state.
Latches are provided on each data input for
temporary storage. When the clock input is in
the low logic state, information present at the
data inputs D 1 and D2 will be fed directly to
the latch output. When the clock goes high, the
input data is latched. The outputs are gated to
allow full. bus driving and strobing capability.
The MC10128 is useful in interfacing and
bus applications in central processors, minicomputers, and peripheral equipment.

MC1 0128 output levels can be accepted by the
MC10129 Bus Receiver.
The operating mode (IBM or TTL) is

II

selected by tying the external control" pins to
ground or leaving them open. Leaving a control
pin open selects the TT L mode, and tying a
control pin to ground selects the IBM mode.
The TTL mode will drive a 25·ohm load,
terminated to +1.5 Vdc or a 50-ohm load,
terminated to ground. The device has totempole type outputs, but it also has a disable
input for three-state logic operation when the

VCC = Pin 14
Gnd 1 = Pin 16
Gnd 2 = Pin 1

L SUFFIX
CERAMIC PACKAGE

PD = 700 mW pkg/typ (No Load)
tpd = 12 ns ty p

Gnd 3 = Pin 9

CASE 620

VEE = Pin 8

VCC Max.= +7.0 Vdc

CONTROL 1
13

11

D1O----~"-ID

10

CLOCKo--~~~~

7

RESETo---4~'--~

12
DISAB LE 1 6 - - - 1 r - t - - - - - t -J
DISABLE

5

2o---4~+-----+-~

6

D2o----!--!t-""i

R

___3
STROBEo--------~

4
CONTROL2

3·24

TTL MODE

S

TEST VOLTAGE/CURRENT VALUES
TEST VOLTAGE VALUES

mAde

!lAde

mAde

n
....

IOHl

IOH2

IOL

00

-50

-100

+56

-50
-50

-100
-100

+56
+56

Volts

@Test
Temperature

VIHmax

-30 0 C

VILmin VIHAmin VILAmax VEE

-0.890

VCC

-1.890

-1.205

-1.500

-1.105
-1.035

-1.475

·5.2 +5.00.
-5.2 +5.00

·1.440

·5.2 +5.00

+25 0 C

-0.810

·1.850

+85 0 C

-0.700

-1.825

ELECTRICAL CHARACTERISTICS
-30 0 C
Characteristic
Negative Power Supply

Symbol

Min

Max

IE

-

-

Positive Power Supply
Drain Current

ICC

-

Input Leakage Current
Pin 3
Pin 7
Pins 6, la, 11
Pins 5,12

linH

-

Logic "1" Output Voltage

VOH

+25 0 C
Min

+1j5 0 C
Min

Max

Unit

-

Max
91

-

-

mAdc

-

-

50

-

-

mAdc

-

-

620
350
265
485

-

-

2.5
2.7

-

-

-

-

-

-

0.5

-

-

-

2.5

-

-

-

Vdc

Conditions

VI Hmax to Data Inputs (Pins 6 and 11)

Drain Current

w

~

(.TI

!lAdc

-

-

-

Vdc

Logic "1" Threshold Voltage

VOHA

-

Logic "a" Threshold Voltage

VOLA

-

-

-

0.5

-

-

Vdc

Output Short Circuit Current

ISC

-

-

-

260

-

-

mAdc

Logic "a" Output Voltage

Switching Times
Propagation Delay
Data, Strobe
Clock, Reset
Setup Time
Hold Time
Rise Time, Fall Time

VOL

Vdc

ns
tpd

VIHmax to Data Inputs, lout
VIHmax to Data Inputs, lout

-

1.0
1.0

18
20

-

-

tset

--

-

-

-

-

-

-

-

-

-

thold
t+,t-

-

-

ns
ns

-

-

-

8.0

-

-

ns

-

VILA~

~100 nsec min

II

=
=

IOHl
IOH2

VIHmax to Strobe Input, lout = IOL
VIHmax to Data Inputs;apply pulse CD,
or VIHAmin to Data Inputs (one at a time.)
VI LAmax to Data Inputs (one at a time), or
VIHmax to Data Inputs and VIHAmin to
Strobe.
VIHmax to Data Inputs, connect outputs
to ground (one at a time!.
50% in to +1.5 V out. See switching
circuit and waveforms.

-

~

Test one input at a time. VIHmax to P.U.T.

+1.0 Vdc to +2.0Vdc.

o
....
I'J

•

IBM MODE

3:

TEST VOLTAGE/CURRENT VALUES
mAdc
TEST VOLTAGE VALUES
Volts

@ Test
Temperature

VIHmax VILmin VIHAmin VILAmax
-0.890
-1.890
-1.205
-1.500
-1.850 . -1.105
-1.475
-0.810
-1.035
-1.440
~~.700 ~5

-30°C
+25 0 C
+85 0 C

VEE VCC
-5.2 +6.00
-5.2 +6.00
-5.2 +6.00

IOH1
-59.3
-59.3
-59.3

n
....

I'Adc

o

....

IOH2
-30
-30

IOL
-240
-240

-30

-240

N

00

ELECTRICAL CHARACTERISTIC
. -30°C
Characteristic
Negative Power Supply'
Drain Current
Positive Power Supply
Drain Current

w

i\J
C!l

Input Leakage Current
Pin 3
Pin 7
Pins 6, 10, 11
Pins 5,12
Logic" 1" Output Voltage

+250 C

+85 0 C

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

97

-

-

mAde

VI Hmax to Data Inputs (Pins 6 and 11l.

ICC

-

-

-

73

-

-

mAdc

VI Hmax to Strobe 'I nput (Pin 3l.

I'Adc

Test one input at a time. VIHmax to P.U.T.

-

-

-

620
350
265
485

-

3.11

-

Vdc

-

-

-

-

VIHmax to Data Inputs, lout = IOHl
VIHmax to Data Inputs, lout = IOH2
VIHmax to Strobe Input, lout = IOl
VI Hmax to Data I nputs, apply pulse CD,
or VIHAmin to Data Inputs (one at a timel.

linH

VOH

-

-

-

-

-

-0.5

-

-

Vdc

logic "1" Threshold Voltage

VOL
VOHA

5.85
0.15

-

-

2.9

-

-

Vdc

logic "0" Threshold Voltage

VOLA

-

-

-0.5

0.15

-

-

Vdc

Output Short Circuit Current

ISC

-

-

-

320

-

-

mAdc

Logic "0" Output Voltage

Switching Times
Propagatio!' Delay
Data, Strobe
Clock, Reset

ns
tpd

Setup Time

tset

Hold Time

thold
t+,t-

Rise Time, Fall Time

CD A pulse is applied to pin 10.

VIH - - - ,

Conditions

VI lAmax to Data Inputs (one at a time), or
VIHmax to Data Inputs and VIHAmin to
Strobe.
VI Hmax to Data Inputs, connect outputs
to ground (one at a time).
50% in to +1.5 V out. See switching
circuit and waveforms.

-

-

1.0
1.0

-

-

-

-

r-

23
23
-

8.0

VIH

VILA~L-Jf4--IOO

",eo m----'-ID

14

ao

D



L


H

C

STROBE RESET



H
L
H
L

L



°n+1



H

H
H



L
L
L

L

an

H



H

~ "" bon't Care
D113

15 al

R

Po = 750 mW typ/pkg
(No Load)
tpd = 10 ns typ
Vcc Max = +7.0 Vdc

D2

D3

Hysteresis
Control

6

>-+-+--I--i D

4

3

02

2

03

VCC= Pin 9
Gnd = Pins 1 and 16
VEE = Pin 8

5 o-----~

Clock 1 1 0 - - - - - - - . J

L SUFFIX

Resetl00--------~-~

CERAMIC PACKAGE
CASE 620

Strobe 1 2 0 - - - - - - - - - - - - - - '

3-30

MC10129

TEST VOLTAGE VALUES
(Volts I

"MTTL I~(¥T
LEVELS 1

MECL 10,000 INPUT LEVELS

HYSTERESIS MOOE
INPUT LEVELS ::2)

"IBM IN~(,)
LEVELS 1

@Test
Temperature

VIHmax

VI Lmin VIHAmin VILAmax VIH

-30 o e

-0.890
-0.810
-0.700

-1.890
-1.850
-1.825

+250

C

+850 C

1.205
-1.105
-1.035

-1.500
-1.475
-1.440

VIL VIHA' VILA'
3.000 0.400 2.000 0.800
3.000 0.400 2.000 0.800
3.000 0.400 2.000 0.800

VIH
3.11
3.11
3.11

VIL VIHA' VILA'
0.150
0.150 1.700 1.10
0.150

-

-

VIHA"
2.900
2.600
2.300

VILA" VIH~" VILA'" VCC@ VEE
+5.0
-5.2
2.000 2.200 1.300
+5.0
-5.2
1.700
1.900 1.000
+5.0
-5.2
1.400
1.600 0.700

ELECTRICAL CHARACTERISTICS
-30 0 e
Characteristic

Negative Power Supply
Drain Current

Min

Max

Unit

167

152

-

167

mAde

Pin 5 grounded, VI H to Clock, Reset
open, VI L to all other inputs.

-

189

-

172

-

189

mAde

Pin 5 to VEE, VIH to Clock, Reset
open, V I L to all other Inputs.

-

8.0

-

8.0

-

8.0

Max

IE

-

ICC

Input Current
Data

linH

-

-

-

Conditions

mAde

Pin 5 to VEE. VI L to Data inputs.

/lAde

Pin 5 to VEE, VIH to P.U.T.,

one input at a time.

-

150
720
390

-

95
450
245

-

95
450
245

ICBO

-

1.5

-

1.0

-

1.0

/lAde

Pin 5 to VEE, VI L to Data inputs,

linL

0.5

-

0.5

-

0.3

-

/lAde

Pin 5 to VEE, VI L to P.U.T., VI H to all
. other inputs.

6.0
3.7

20
15

6.6
3.7

20
15

6.6
3.7

30
40

-

Reset
Clock, Strobe
Data

Max

Min

Positive Power Supply Drain Current

+BSoe

"';2S0e

Min
-

Symbol

one at a time.
Reset, Clock, Strobe

Switching Times
(See Figures 1 thru 5)
Propagation Delay
Data
t++
t--

ns

tpd

Clock

2.7

11

2.7

9.0

2.7

11

Strobe

1.6

8.0

1.6

7.0

1.6

8.0

Reset

2.0

8.0

2.0

6.5

2.0

8.0

1.5 Vdc in to 50% out.

50% to 50%

Rise Time, Fall Time

t+,t-

1.5

5.0

1.5

4.3

1.5

5.0

ns

20% to 80%

Setup Time

tset

27

-

20

-

27

-

ns

50% to 50%

Hold Time

thold

0

-

-2.0

-

-2.0

-

ns

6.6
3.7

30

6.7
3.7

25
15

6.6
3.7

30
40

Hysteresis Mode
Propagation Delay
Data
t++
t--

ns

tpd

17

1.5 Vde in to 50% out.

Setup Time

tsot

30

-

25

-

30

-

ns

Hold Time

thold

0

-

-2.0

-

-2.0

-

ns

50% to 50%

CD

When testing choose either MTTL or IBM Input Levels.

@

VIHA", VILA", VIHA"', and VILA''', are logic "1" and logic "0" threshold voltages in the hysteresIs mode as shown in'diagram,

® Operation and limits shown also apply for Vce

= +6.0 V.

Hvsteresls Mode
Threshold Voltage

LogiC "1"
LogiC "0"

3-31

•

MC10129
SWITCHING TIME TEST CIRCUIT

Vcc
Coax

I __
I

Input

{Ot-__- - - - - - o o 0 7
Pulse Generator

•

= t-

""

:

I
I

0

114
000-----'

I
I
I

Input Pulse

t+

~~tli~: ___ ,

Coax

5.5 ± 0.5 ns

(10 to 90%)

13

I

01

Unused 0 inputs
must be- tied to
V CC or pin 16.

Unused outputs
connected to a
50-ohm resistor
to ground.

50-ohm term lOation to ground lo-

cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin

R

and TP out to output pin.

">+-+-+--lo
Hysteresis
Control.

I
I

I

50-''------'

Clock

11 o-!~------'

Reset

10 o-!~----_---'-'~-..J

Strobe

12

I
I

O-:-L-f[-----__-_-_-_---'___~J
1 16

8

JO.1 Il F

25 1l FJ

-3.2 Vdc
+2.0 Vdc

*Hysterisis Control tied to VEE for fixed input

reference, tied to pin 16 for input hvsterisis

mode.
Note: All power supply and logic levels are
shown shifted 2 volts positive.

3-32

MC10129
SWITCHING WAVEFORMS@ 2SoC

FIGURE 1 - DATA to OUTPUT
(Clock and Reset are low, Strobe is high)

FIGURE 2 - STROBE to OUTPUT
(Data is high, Clock and Reset are low)

~---+5.0V

Data _ _ _ _ _...J

, - - - , - - - - - - + 1.11 V
Strobe

' - - - - - ' , - - - - - +2.4 V

+0.31 V

- - - - - - - - - +1.11 V
Q

Q------t'

t++

' - - - - - - - +0.31 V

' - - - - - - - - - +0.31 V

t--

FIGURE 4 - CLOCK to OUTPUT
(Reset is low, Strobe is high)

C+

FIGURE 3 - RESET to OUTPUT
(Data and Strobe are high)

5 0V
.

+2.4 V
~----

Clock----,

t1.11 V

+1.11 V

'-_J ______ +0.31 V

Q-----+-

Reset _ _ _ _ _ _ _..J

, - - - - - - - +1.11 V

' - - - - - +0.31 V
- - - - - - - +0.31 V

Clock

; - - - - - - - - - - - +1.11 V

+0.31 V

FIGURE 5 - TSET UpAND THOLD WAVEFORMS
+1.11 V

, - - - -__ - - - - - - +5.00 V

o
Q

+0.31 V

O%
}50%
~
tsetup

F

..,...----+2.400 V

thold

------+1.11 V

50%
C - - - - - - - ' , - - - - - - - ' - +0.31 V

Note: All power supply and logic levels are
shown shifted 2 volts positive.

3-33

•

MC10130/MC10530
D!JAL LATCH

S1

19\5-------,

TRUTH TABLE
01(1117---~

2161

eel {1016----.--'
3(1)

R1

E
R2

1814-11-----'
{,31 9

f1J

(15111--L-./

02 t14)10---~

•

C

CE

L

L

L

L

H

L

L

H

~

L

H

~

H

L

H

H

an
an
an

~

11113-11-----,

14121

·Eib

0

15\31

=

Qn+I

Don't Car.

VCC = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8(12)

S2116112------'

Po

=

155 mW tYP/pkg (No Load)

The MC10130/MC10530 is a clocked dual 0
tYpe latch. Each latch may be clocked separately
by holding the common clock in the low state,
and using the clock enable inputs for t,he
clocking function. If the common clock is to be
used to clock the latch, the clock enable (CE)
inputs must be in the low state. In this mode,'
the enable inputs perform the function of
controlling the common clock (C).
Any chang!, at th,e 0 input will be reflected
at th~ output while the clock is low. The outputs are latched on the positive transition of
the clock. While the clock is in the high state,
a change in the information present at the data
inputs will not affect the output information .
The set and reset inputs do not override
the clock and 0 inputs. They are effective only
when either

C or

CE or both are high.

tpd = 2.5 ns typ

-'''~-'~)P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC10130 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10530 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
'Characteristic
Power Supply Drain Current
Input Current
Pins 6,11
Pin 9
Pins4,5,7,10,12,13
Switching Times
Propagation Delay
. Data
Set, Reset
Clock
Rise Time, Fall Time
(20% to 80%)

-30°C

+25 0 C

+85 0 C

+125 0 C

Symbol Min Max Min Max Min Max Min Max Min Max
IE

-

39

-

38

-

35

-

38

-

39

-

375
450
485

-

350
425
455

-

220
265
285

-

220
265
285

-

220
265
285

Unit
mAde
!lAde

linH

-

-

-

ns
tpd

,
t+,t-

Setup Time

tset

Hold Time

thold

1.0 3.9 1.0 3.6 1.0
1.0 3.9 1.0 3.6 1.0
1.0 4.3 1.0 4.3 1.0
LO 3.9 1.0 3.6 1.1
2.5
1.5

3.5
3.5
4.0
3.5

1.0
1.0
1.0
1.1

3.8 LO
3.9 1.0
4.1 LO
3.8 1.0

4.1
4.1
4.7
4.1

ns

-

2.5

-

2.5

-

2.5

-

2.5

-

ns

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

-55 0 C and +125 0 C test values apply to MC105xx devices only.

3·34

MC10131/MC10531
DUAL TYPE D MASTER-SLAVE
FLIP-FLOP

Sl

(9)

5

01 (11)

7

CEI

(10)

Rl

(6)

3

(7)

6

(8)

4

Cc (13)

9

R2

2

(1) 13

14 (2)
CE2 .(15) l l - - - L - _

02 (14)

10----------~

The MC10131/MC10531 is a dual masterslave type 0 flip-flop. Asynchronous Set (S)
and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip-flop may be
clocked separately by holding the common
clock in the low state and using the enable
inputs for the clocking function. If the common clock is to be used to clock the flip-flop,
the Clock Enable inputs must be in the low
state. In this case, the enable inputs perform
the function of controlling the common clock.
The output states of the flip-flop change on
the positive transition of the clock. A change in
the information present at the data (0) input
will not affect the output information at any
other time due to master slave construction.

15 (3)

S 2 (16) 12 ----------------'

RoS TRUTH TABLE
R

S

L
L

L
H

°n+1
an
H

H

L

L

H

N.D.

H
N.D.

= Not

Defined

CLOCKED TRUTH TABLE

rJ>

c

0

L
H

rJ>
L

H

H

On+1
an
L
H

= Don't Care
= CE + Ce·

C
A clock H is a clock transition
from a low to a high state.

Po = 235 mW typ/pkg (No Load)
f T09 = 160 MHz typ
tpd = 3.0 ns typ
t+, t- = 2.5 ns typ (20%-80%)
VCC1 = Pin 1 (5)
VCC2 = Pin 16(4)
VEE = Pin 8 (12)

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC10131 only

CERAMIC PACKAGE

CERAMIC PACKAGE
CASE 650
MC10531 only

CASE 620

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-35

•

MC10131/MC1053Y·

. ELECTRICAL CHARACTERISTICS

-3aoc

-55°C
Characteristic
Power Supply D~ain' Current'
I nput Current
PinsA, 5,12,13
Pins6,ll
Pins 7,10
Pin 9

•

Switching Times
Propagation. Delay
Clock
Set, Reset
Rise Time, Fall Time
(20% to 80%)

Symbol
IE

+25 0 C

+85 0 C

+ 125°C

Min Max Min Max Min Max Min Max Min Max

-

62

-

62

-

56

-

62

-

62

-

565
375
415
450

-

525
350
390
425

-

330
220
245265

-

330
220
245
265

-

330
220
245
265

(
Unit
mAde
~Adc

linH

-

-

-

ns
tpd

t+, t-

1.7 4.6
1.7 4.5

1.7 4.6
1.7 4.4

1.8 4.5. 1.8 5.0
1.8 4.3 1.8 4.8

1.8
1.8

1.0 4.6

1.0 4.6

1.1

4.5

1.1

4.9

1.1

5.0
4.9
"4.9

tset

2.5

-

2.5

-

2.5

-

2.5

-

2.5

-

Hold"Time

thold

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

Toggle Frequency

fTog

115

-

125

-

125

-

125

-

125

-

.MHz

Setup Time.

-55°C and +125 0 C test values apply to MC105xx devices only"

3-36

ns

MC10132/MC10532
DUAL MULTIPLEXER WITH
LATCH AND COMMON Rt:SET

A(15)11

012(9)5------~--~~~

CEO (14) 10---~-~-......
CC.
(11)6
R (10)

7_::::tt++::~~~=;~=:!::~

C E 1 (13) 9

----+-++---"L.....-

021 (1)13---+-++---~~

14 (2) 0.2 clock is low. The outputs are latched on the
positive transition of the clock. While the clock is
in the high state, a change in the information
present at the data inputs will not affect the
output information. The reset input. is enabled
when the clock is in the high state, and disabled
when the clock is low.

022 (16) 12--+----......L..._

D=(AeD11)+(AeD12)

TRUTH TABLE
R

0

Cc

'L"

L
L
L
L

L
L
H
H

'L"

H
H
H
H

L
L
H
H

'"

'"

L
L

L
L
H

'" = Don't Care

CE
L
H
L
H

°n+1
L

Po = 225 mW typ/pkg (No Load)

an
an
an

L

H

H

an
an
an
L

L
H
H

The MC10132/MC10532 is a dual multiplexer
with clocked 0 type latches, It incorporates
common data select and reset inputs. Each latch
2 (6) 01
maybe clocked separately by holding the common
clock in the low state, and using the clock enable
inputs for a clocking function. If the common
clock is to be used to clock the latch, the clock
enable (CE) inputs must be in the low state. In this
3 (7) 0.1
mode, the enable inputs perform the function of.
controlling the common clock (CC).
The data select (A) input determines which
15 (3) 02
data input is enabled. A high (H) level enables data
inputs 012 and 022 and a low (L) level enables
data inputs 011 and 021. Any change on the data
input will be reflected at the outputs while the

tpd = 3.0 ns typ

VCC1 = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

P.SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC10132 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10532 Qnly

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-37

II

MC10132/MC10532

+125 0 C
-30°C
+25 0 C
+85 0 C
Symbol Min Max Min Max' Min Max Min Max Min Max
-55°C

Characteristic
Power Supply Drain Current
Input Current
Pins 4, 5, 7,12,13
Pin 6
Pins9,10,ll

..

Switching Times
Propagation Delay
Data
Reset
Clock
Select
Rise Time, Fall Time
,
(20% to 80%)

IE

-

60

-

55

-

60

-

61

-

495
660
450

-

460
620
425

-

290
390
265

-

290
390
265

-

290
390
265

Unit
mAdc
/-lAdc

-

ns
tpd
1.0
1.0
1.0
1.0
t+,ttset

Hold Time
Data
Select

thold

-55°C and

61

linH

Setup Time
Data
Select

+125 0

-

3.7
4.1
6.2
5.0

1.0
1.0
1.0
1.0

3.6
4.0
6.0
4.8

1.0
1.0
1.0
1.0

3.3
3.8
5.7
4.6

1.0
1.0
1.0
1.0

3.7
4.2
6.3
5.0

1.0
1.0
1.0
1.0

3.9
4.8
6.7
5.8

1.5 3.8 1.5 3.7 1.5 3.5 1.5 3.8 1.5

4.1

ns
ns

-

-

2.5
3.5

-

1.5
1.0

-

2.5
3.5

-

1.5
1.0

-

2.5
3.5
1.5
1.0

-

2.5
3.5

-

2.5
3.5

-

-

1.5
1.0

-

1.5
1.0

-

ns

C test values apply to MC105xx devices only.

3-38

-

MC10133/MC10533
QUAD LATCH

DO

GO

(7)

(9)

3----------'~

D1 (11)

7------j---J~
4

CE

6

(10) 01

9 -------II--'~

The MC1 0133/MC1 0533 is a high speed,
low power, quad latch consisting of four
bistable latch circuits with 0 type inputs and
gated Q outputs, allowing direct wiring to
a bus. When the clock is high, outputs will
follow 0 inputs. Information is latched on the
negative going transition of the c1cok.
The outputs are gated when the output
enable (G) is low. All four latches may be

11 (15) 02

(14) 10 - - - - - - - I I - - - - - -....a.t..____

15 (3)
D3

00

(16) 1 2 - - , - - _

02 (13)

G1

(6)

5 - - - - - - 1 - - - - - -.....-.;---....,

CE

(8)

2

clocked at one time with the common clock
(CC), or each half may be clocked separately
with its clock enable (CE).

03

(2)14----------'-t

TRUTH TABLE
C· 0

G
H

r/J r/J

L

L r/J
H L
H H

L
L

an
L

Po ~ 310 mW typ/pkg (No Load)

H

tpd

~

4.0 ns typ

t+, t-

~

2.0 ns typ
(20% to 80%)

r/J- Don t Care
C

=

II

V CC1 ~ Pin 1(5)
VCC2 ~ Pin 16(4)
VEE ~ Pin 8 (12)

°n+1
L

Cc + CE

P SUFFIX

F SUFFIX

PLASTIC PACKAGE

CERAMIC PACKAGE

L SUFFIX

CASE 648
MC1 0133 only

CASE 650
MC10533 only

CERAMIC PACKAGE
CASE 620

Numbers at ends of te.rminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic

Symbol

Power Supply Drain Current
I nput Current
Pins 3.7.9,14
Pins 4,12
Pins 5,10,13
Switching Times
Propagation Delay

Rise Time, Fall Time
(20% to 80%)

IE

-30°C

+25 0 C

+85 0 C

+125 OC

Min Max Min Max Min Max Min Max Min Max

Unit

-

83

-

82

-

75

-

82

-

83

-

-

390
425
560

-

245
265
350

-

245
265
350

-

-

415
450
595

-

245
265
350

1.0
1.0
1.0

5.8
5.8
3.3

1.0 5.6
1.0 5.4
1.0 3.2

1.0 5.4 1.1
1.0 5.4 1.2
1.0 3.1 1.0

5.9
6.0
3.4

1.0
1.0
1.0

6.3
6.3
3.6

1.0 3.9

1.0 3.6

1.1

3.5

1.1

3.8

1.0

4.1

ns

mAde
}.lAde

linH

-

ns
Data
Clock
Gate

tpd

t+,t-

Setup Time

tset

2.5

-

2.5

-

2.5

-

2.5

-

2.5

-

ns

Hold Time

thold

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

-55°C and +125 0 C test values apply to MC105xx deVIces only..

3-39

MC1 0134/MC1 0534
DUAL MULTIPLEXER
WITH LATCH

The MC10134/MC10534 is a dual multiplexer with clocked D tYpe latches. Each latch
may be clocked separately by holding the
common clock in the low state, and using the
clock enable inputs for the clocking function. If
the common clock is to be used to clock the
latch, the clock enable (CE) inputs ':"'ust be in
the low state. In this mode, the enable inputs
perform the function of cantrall ing the common
clock (CCl.
The data select inputs determine which data
input is enabled. A high (H) level on the AO
input enables data input D 12 and a low (L)

.0.0 (10) 6
PD = 225 mW typ/pkg (No Load)
tpd = 3.0 ns tYPo

Al (15)11

2 (6) Q1

D12(9)5------++--~__/

CEO (14) 10----++--0-1
CC(11)7----__++--~~/

CE 1 (13) 9

~______~

-----++--"L_

15 (3) Q2

level on the AO input enables data input D 11.
A high (H) level on the Al input enables data
input D22 and a low (L) level on the A 1 input
e'nables data input D21 .

14 (2) 0.2

reflected at the outputs while the clock is low.
The outputs are latched on the positive transition of the clock. Wh ile the clock is in' the
high state, a change in the information present
at the data inputs will not affect the output

D21 (1) 13-----++---~

•

Any
D22 (16) 12--------~L_~ ~______~

TRUTH TABLE

t/>

C

AO

D11

012

Q n +l

L
L
L
L

L
L

L
H

t/>
t/>

L

H
H

L

L

H

H

H

t/>

t/>
t/>
t/>

t/>

an

= Don't Care

C=

CE + Cc

. .
-, ~

change

on

the

VCCl = Pin 1 (5)
VCC2 = Pin 16(4)
VEE = Pin 8(12)

input

will

be

information.

~.~-~

H

PSUFFIX
PLASTIC PACKAGE
CASE 648
MC10134 only

data

_ -

~

L SUFFIX
CERAMIC PACKAGE
CASE 620

F SUFFI?<
CERAMIC PACKAGE
CASE 650
MC10534 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.
-55°C
Characteristic
Power Supply Drain Current
I nput Current
Pins
Pins

Symbol
IE

-30 0 C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min

Max

Unit

-

61

-

60

-

55

-

60

-

61

mAdc

-

495
450

-

460
425

-

290
265

-

290
265

-

290
265

~Adc

linH

4,5,7,12,13
6,9,10,11

'-

-

Switching Times
Propagation Delay

ns
tpd

Data
Clock
Select
Rise Time, Fall Time

t+,t-

1.0 3.6 1.0 3.5
1.0 6.2 1.0 6.0
1.0 5.0 1.0 4.8
1.5 3.8 1.5 3.7

1.0 3.3 1.0 3.6 1.0
1.0 5.7 1.0 6.3 1.0
1.0 4.6 1.0 5.0 1.0
1.5 3.5 1.5 3.8 1.5

3.9
6.7
5.6
4.1

ns

(20% to 80%)
Setup Time
Select
Hold Time
Data
Select

ns

, tset

Data

3.5

-

2.5
3.5

-

2.5
3.5

-

1.5
1.0

-

1.5
1.0

-

1.5
1.0

-

2.5
3.5

-

2.5
3.5

-

2.5

1.5
1.0

-

1.5
1.0

-

ns

thold

-

-550 C and +125 0 C test values apply to MC105xx devices only.

3-40

MC10135/MC10535
DUAL J-K MASTER-SLAVE
FLIP-FLOP

CLOCK J·K TRUTH TABLE'
51 (9) 5

J1

J

(11) 7

2 (6)

Kl (10) 6

3(7)

K

On+1

an

L

L

H

L

L

L

H

H

H

H

an

·Output states change on

Rl (8) 4
(13) .9
52 (16) 12

POSI

tlve transition of clock for j
j( Input condition present

c

The MC10135/MC10535 is a dual master·
slave de coupled J·K flip·flop. Asynchronous
set (5) and reset (R) are provided. The set and
reset inputs override the clock.
A common clock is provided with separate
j.j( inputs. When the clock is static, the j.j(
inputs do not effect the output.
The output states of the flip·flop change
on the positive transition of the clock.

R·S TRUTH TABLE
12(14)10

15 (3)

K2

14 (2)

(15)11

Rl (1)13

R

S

°"+1

L

L

an

L

H

H

H

L
H

L
N.D.

H

_

LSUFFIX

N.D. = Not Defined
PD = 280 mW typ/pkg (No Load)
fTog = 140 MHz typ
tpd

= 3.0 ns typ

•

.

CERAMIC PACKAGE
CASE 620

VCC1 = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

t+, t- = 2.5 ns typ (20% to 80%)
P SUFFIX
PLASTIC PACKAGE
CASE 648
MCl 0135 only

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10535 only

Numbers at ends of terminals denote pin numbers for Land P packages.

Numbers in parenthesis denote pin numbers for F

p~ckage.

-55 0 C
Characteristic

-30°C

+25 0 C

+85 0 C

+ 125°C
Max

Unit

-

75

-

75

-

68

-

75

-

75

mAdc

Pins 6,7,9,10,11

-

450

425

-

265

660

-

265

-

-

265

Pins 4,5,12,13

-

Power Supply Drain Current
Input Current

Symbol
IE

Min Max Min Max Min Max Min Max Min

!lAde

linH
620

390

390

390

Switching Times'
Propagation Delay

ns
tpd

Clock

1.7

4.8

1.8

5.0

1.8

4.5 1.8

4.6

1.8

5.3

Set, Reset

1.7

5.4

1.8

5.6

1.8

5.0

1.8

5.2

1.8

5.9

t+,t-

1.0

4.8

1.1

4.8

1.1

4.5

1.1

4.7

1.0

5.3

ns

Setup Time

tset

2.5

-

2.5

-

2.5

-

2.5

-

2.5

-

ns

Hold Time

thold

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

Toggle Frequency

fTog

125

-

125

-

125

-

125

-

115

-

MHz

Rise Time, Fall Time
(20% to 80%)

-55°C and +125 0 C test values apply to MC105xx devices only.

3-41

MC1 0136/MC1 0536
UNIVERSAL HEXADECIMAL
COUNTER
SEQUENTIAL TRUTH TABLE" •

The MC10136/MC10536 is a high speed
synchronous counter that can count up, count
down, preset, or stop count at frequencies exCarry Clock
Carry
ceeding 100 M Hz_ The flex ibility of this device
QO Ql Q2 Q3
Qui
SI S2 DO Dl D2 D3
iii'
allows the designer to use one basic counter for
L
L
H
L
L
H
H
H
H
L
L
L
C/J
most applications, and the synchronous count
L
H
,H
L
H
H
L
H
H
C/J
C/J

 = Don't care .
03) will be entered into the counter. Carry Out
• Truth table shows logic states assuming inputs vary in sequence
goes low on the terminal count, or when the
shown from top to bottom.
counter is being preset.
'" '" A clock H is defined as a clock input transition from a low to a
This device is not designed for use with gated
high logic level.
clocks. Control isviaS1 andS2.
VCCl = Pin 1 (5)
Po = 625 mW typ/pkg (No Load)
FUNCTION SELECT TABLE
fcount=150MHztyp
"
VCC2 = Pin 16 (4)
SI
52
Operating Mode
tpd = 3,3 ns typ (C - 0)
VEE = Pin 8 (12)
L
L
Preset (Program)
INPUTS

•

OUTPUTS

= 7.0 ns typ (C - Gout)
= 5.0 ns typ (Gin - Caut)

L

H

Increl;Tlent (Count Up)

H

L

Decrement (Count Down)

H

H

Hold (Stop Count)

SI(13)9

S2 (11) 7' O-"-+1_----t----,
Carry Tri'
(14) 10 o++----,

T
T03

Clock o---~~~~~-------+~~~--------~~-+-+--------~
(1) 13

12(16)

DO

14(2)
00

11 (15)
01

15(3)
01

6(10)
02

2(6)
02

Numbers at ends of terminals denote pin numbers for Land P packages'.
Numbers in parenthesis denote pin numbers for F package_

3-42

5(9)
03

3(7)
03

4(8)
Carry Out

MC10136/MC10536

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650

CASE 648
MC10136 Only

MCl 0536 Only

ELECTRICAL CHARACTERISTICS
-55°C
Characteristic
Power Supply Drain Current
I nput Current
Pins 5, 6,11,12
Pins 9,10
Pin 7
Pin 13
Switching Times
Propagatidn
Clock to
Clock to
Carry I n

Symbol
IE

-30°C

+25 0 C

+85 O C

+125 0 C

Min Max Min Max Min Max Min Max Min Max Unit
-

165

-

165

-

150

-

165

-

165 mAdc

-

375
415
450
495

-

350
390
425
460

-

220
245
265
290

-

220
245
265
290

-

220
245
265
290

/lAdc

linH
-

-

-

-

-

-

-

-

ns
Delay

tpd
0.8 4.6 0.8 4.8 1.0 4.5 1.4 5.0 1.4 5.2
2.0 11.0 2.0 10.9 2.5 10.5 2.4 11.5 2.4 12.6
1.6 7.1 1.6 7.4 1.6 6.9 1.9 7.5 1.9 7.6

Q

Carry Out
to Carry Out

Rise Time, Fall Time (20% to 80%)

t+, t-

Setup Time
Data (DO to C)
Select (S to C)
Carry In (Cin to C)
(C to Cin)

tset

Hold Time.
Data (C to DO)
Select (C to S)
Carry In (C to Cin)
(Cin to C)

thold

Counting Frequency

0.9

fcountup

3.3 1.1

3.3 1.1

3.5 1.2

3.7

3.5
7.5
3.7
-1.0

-

-

-

0
-2.5
-1.6
3.1

-

ns
ns

3.5
7.5
4.5
-1.0

fcountdown

3.3 0.9
-

-

3.5
7.5
4.5
-1.0

-

-

-

-

3.5
7.5
4.5
1.0

-

-

3.5
7.5
4.5
-1.0

-

ns
0
-2.5
-1.6
4.0

-

115
115

-

-

-

-55°C and +125 0 C test values apply to MC105xx devices only.

3-43

0
-2.5
-1.6
4.0

-

125
125

-

-

-

125
125

-

0
-2.5
-1.6
4.0
125
125

-

-

0
-2.5
-).6
4.0

-

115
115

-

-

-

MHz

•

MC10136/MC10536

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25 0 C
NOTE.

tsetup IS the rTllmmum tIme before the posItIve
tranSition of the clock pulse Ie) that Information must
be present at the ,nput 0 or S.
thold IS the minimum tIme after the positive tran-

vee1 = VCC2 = +2 0 Vdc

sition of the clock pulse (e) that information
remain unchanged at the Input 0 or S

.: *

Input Pulse
t+ := t- := 2.0 ns ± 0.2 n5
(20 to 80%)
Clock Input

@---....----o

\

\

TP out

Clock

·50 ohm, MC105xx only.

•

~ 01"F

Q Output

VEE = -32 Vdc

, - - - - - - - - - - -__-----+111V

c
+031 V

50-ohm termination to ground located in each scope channel input.

o

orS

All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TP in to input
pin and TP out,to output pin. V out
is 2:1 attenuated.
Unused outputs are connected to
a 50 ohm resistor to ground
(100-oh~ for MC105xx)'

<

NOTE: All power supply and logic levels are shown shifted 2 volts positive.

SET UP AND HOLD TIMES

50%

lal

1$

the minimum time to

Willt

after the

counter has been enabled to clock It.
Ibl 1$ the minimum time before the
counter has been disabled lhat It may
be clocked

Clock

(e) 1$ the minimum time before the
counter is enabled that II clock pulse

may be applied With no effect on the
state of tt1e counter.

(d) IS the minimum time to walt after
counter IS dIsabled that a clock
pulse may be eppllad WIth no effect In
the state of the counter.
the

50%

Ibl and Ic) may be neDBtive numbers

,3-44

MC10136/MC10536
APPLICATIONS INFORMATION

To provide more than four bits of counting
capability several MC10136/MC10536 counters
may be cascaded. The Carry I n input overrides
the clock when the counter is either in the increment mode or the decrement mode of operation.
This input allows several devices to be cascaded
in a fully synchronous multistage counter as illustrated in Figure 1. The carry is advanced between
stages as shown with no external gating. The
Carry I n of the first device may be left open. The
system clock is common to all devices.
The various operational modes of the counter
make it useful for a wide variety of applications.
If used with MECL III devices, prescalers with
input toggle frequencies in excess of 300 MHz are
possible. Figure 2 shows such a prescaler using
the MCl 0136 and MC1670. Use of the MCl 0231
in place of the MC1670 permits 200 MHz opera-

The MCl 0136 may also be used as a programmable cou nter. The configu ration of Figure 3
requires no additional gates, although maximum
frequency is limited to about 50 MHz. The
divider modulus is equal to the program input
plus one (M = N + 1), therefore, the counter will
divide by a modulus varying from 1 to 16.
A second programmable configu ration is also
illustrated in Figure 4. A pulse swallowing technique is used to speed the counter operation up
to 110 MHz typically. The divider modulus for
this figure is equal to the program input (M = N).
The minimum modulus is 2 because of the pulse
swallowing technique, and the modulus may vary
from 2 to 15. This programmable configuration
requires an additional gate, such as Y,MCl 01 09
and a flip-flop such as Y,MC10131.

tion.

FIGURE 1 - 12 BIT SYNCHRONOUS COUNTER

LSB

MSB

~i~!~m------~----------------~--------~------------------------~
Note: 5' and S2 are set either for increment or decrement operation.

FIGURE 2 - 300 MHz PRESCALER

Logic High

MC10136

S1
S2

o

aj--r-------1~c

________~~~
I "put Frequency

32

a
MC1670

3-45

•

MC10136/MC10536

FIGURE 3 - 50 MHz PROGRAMMABLE COUNTER

Program Input

I I I I

•

1 fout =
2 f max

Progcam Input + 1

e:!

50 MHz Typ.

is from

3 Divide Ratio

1 to 16.

FIGURE 4 - 100 MHz PROGRAMMABLE COUNTER

Program Input

I I I I
C

-

DO 01 0203

52

MC10136

51

0002 03

L
~

:--~

YoMC10109

0

YoMC10131.
C

f out =

Program Input

2

f max ~ 110 MHz Typ.

3

Divide Ratio is from 2 to 15.

3-46

0-1

eli]

MC1 0137/MC1 0537
UNIVERSAL DECADE COUNTER

SEQUENTIAL TRUTH TABLE'
INPUTS

OUTPUTS

Carry
S1

S2

L
L
L
L

L
H
H
H

L
L
L
H
L

H
H
H
H
L

H
H
H

L
L
L

02

03

Tn

H

H

H

L

r:>

<'

r:>


 = Don't care.
• Truth table shows logic states assuming Inputs vary In sequence
shown from top to bottom.
•• A clock H is defmed as a clock Input tranSition from a low to
a high logiC level.

FUNCTION SELECT TABLE

Operating Mode

S1

S2

L

L

Preset (Program)

I ncrement (Count Up)

L

H

H

L

Decrement (Count Down)

H

H

Hold (Stop Count)

PD

= 625 mW typ/pkg
= 150 MHz typ

The MC10137/MC10537 is a high speed
synchronous counter that can count UP. down,

preset, or stop count at frequencies exceeding
100 MHz. The flexibility of this device allows·

the designer to use one basic counter for most
applications. The snychronous count feature
makes the MC10137 suitable for either computers or instrumentation.
Three control lines (S 1, S2, and Carry In)
determine the operation mode of the counter.
Lines S1 and S2 determine one of four operations; preset (program), increment (count up),
decrement (count down), or hold (stop count).
Note that in the preset mode a clock pulse is
necessary to load the counter, and the information present on the data inputs (DO, Dl, D2,
and D3) will be entered into the counter. Carry
Out goes Iowan the terminal count. The Carry
Out on the MC1 0137 is partially decoded from
Q1 and Q2 directly, so in the preset mode the
condition of the Carry Out after the Clock's
positive excursion will depend on the condition
of Q1 and/or Q2. The counter changes state
only on the positive going edge of the clock.
Any other input may change at any time except
during the positive transition of the clock"The

sequence for counting out of improper states is

(No Load)

as shown in the State Diagrams.

fcount

tpd = 3.3 ns typ (C-9)
= 7.0 ns typ (C-C out )
= 5.0 ns typ (Cin -Cout)

(
P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650

MC1 0137 only

MC1 0537 only

3-47

•

MC10137/MC10537

ELECTRICAL CHARACTERISTICS

-55°C

•

Characteristic

Symbol

Power Supply Drain Current

IE

Input Current
Pins 5, 6, 11, 12
Pins 9,10
Pin 7
Pin 13
Switching Times
Propagation Delay
Clock to Q
Clock to Carry Out
Carry I n to Carry Out

+25 0 C

+85 0 C

+125 0 C

-

165

-

165

-

150

-

165

-

165

-

375
415
450
495

-

350
390
425
460

-

220
245
265
290

-

220
245
265
290

-

220
245
265
290

Unit
mAdc
MAdc

linH

-

-

-

-

-

-

ns
tpd

Rise Time, Fall Time
(20% to 80%)

t+,c

Setup Time
Data (DO to C)
Select (S to C)
Carry In (Cin to C)
(C to Cin)

tset

Hold Time
Data (C to DO)
Select (C to S)
Carry In (C to Cin)
(Cj;:; to C)

thold

Counting Frequency

-30°C

Min Max Min Max Min Max Min Max Min Max

fcountup
fcountdn

0.8
2.0
1.6

4.6
11
7.1

0.8 4.8 1.0 4.5
2.0 10.9 2.5 10.5
1.6 7.4 1.6 6.9

1.4 5.0 1.4 5.2
2.4 11.5 2.4 12.6
1.9 7.5 1.9 7.6

0.9

3.3

0.9

3.3

1.1

1.1

3.5

1.2

-

3.5
7.5
3.7
-1.0

-

3.5
7.5
4.5
-1.0

-

3.5
7.5
4.5
-1.0

0
-2.5
-1.6
3.1

-

0
-2.5
-1.6
4.0

-

0
-2.5
-1.6
4.0

-

125
125

-

115
115

-

3.3

3.7

ns
ns

3.5
7.5
4.5
-1.0

-

-

3.5
7.5
4.5
-1.0

0
-2.5
-1.6
4.0

-

0
-2.5
-1.6
4.0

-

115
115

-

125
125

-

-

-

-

-

-

-

-

ns

-

-55°C and +125 0 C test values apply to MC105xx devices only.

3·48

-

125 125 -

-

-

-

-

-

MHz

MC10137/MC10537

S1
(13) 9

S2
(11) 7

(14) 100---+-+....,

•
(1) 13
Clock

(16)12ElO

(2)1400

(15)1101

(3)1501

(10)602

(6)202

(9)503

VCC1 = P n 1 (5)
VCC2 = P n 16 (4)
VEE=Pn8(12)

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-49

(7)303(8)4ca;:ryo;;t

MC10137/MC10537
STATE DIAGRAMS
COUNT UP

COUNT DOWN

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2SoC

•

la} is the minimum time to wait after the counter
has been enabled to clock it.

(bl tS the minimum time before the counter hasbeen
disabled that it may be clocked.

Ie} is the minimum time before the counter is en·
abled that a clock pulse may be applied with no effect on the state of the counter.
(d) is the minimum time to wait after the counter
is disabled that a clock pulse may be applied with no
effect in the state of the counter.

(bl and (el may be negative numbers.
Vin

V

ee1 = V CC2

"" +2.0 Vdc

V out

NOTE:
tsetup is the minimum time be'fore the positive

Coax

Coax

transition of the clock pulse te) that information
must be present at the input 0 or S.

.:".

t hold is the minimum time after the positive
transition of the clock pulse te) that information
'must remain unchanged at the input 0 or S.
Clock Input @}--+---o
Input Pulse
t+ = t- = 2.0 ± 0.2 ns
(20 to 80%)

\TP

\
TP in
~50

out

ohm,

MC105XX only.

c

VEE = -3.2 Vdc

+0.31 V

o

50·ohm termination to ground located in each scope
channel input.
orS
All input and output cables to the scope are equal
lengths of 50·ohm 'coaxial cable. Wire length should
be
1/4 inch from TPin to input pin and TP out to
output pin. V out is 2:1 attenuated.

<

Unused outputs are connected to a 50-ohm resistor
to ground (100-ohm for Mel05XX).
NOTE: All power supply and logic levels are sho,:",," shifted 2 volts positive.

3-50

MC1 0138/MC1 0538
BI-QUINARY COUNTER

COUNTER TRUTH TABLES

The MC10138/MC10538 is a four bit
cou nter capable of divide by two, five, or ten
functions. It is composed of four set-reset
master-slave flip-flops_ Clock inputs trigger on
the positive going edge of the clock pulse.

BI-QUINARY
(Clock connected to C2
and Q3 connected to C1)
COUNT

0

1
2
3
4

5
6
7

8
9

01

'02

03

00

L
H
L
H
L
L
H
L
H
L

L
L

L
L
L
L
H
L
L
L
L
H

L
L
L
L
L
H
H
H
H
H

H
H
L
L
L

H
H
L

Set or reset inputs override the clock, allowing asynchronous "set" or "clear". Individual
set and common reset inputs are provided, as
well as complementary outputs for the first and
fourth bits. True outputs are available at all bits.

= 370

PD

•

mW typ/pkg (No Load)

fTog = 150 MHz typ
tpd = 3.5 ns typ
t+, t- = 2.5 ns typ (20% to 80%)

BCD
(Clock connected to' C1
and QO connected to C2)
116112

COUNT

00

01

0
1
2

L
H
L
H
L
H
L
H
L
H

L
L
H
H
L
L
H
H
L
L

3

4

5

6

7

8
9

?

03

L
L.
L
L
H
H
H
H
L
L

L
L
L
L
L
L
L
L
H
H

QO

50
(15) 11

02

5

Q'
(161
Clock

~ Cl

1111

7

Cl

QO

15131

R

Ql

13111

C2

Q2

4

181

2

161

115111

50

OJ

114110

51

00

14 121

(101

6

52

03

3

(91

5

53

-

-

0-

51

(10) 6

Q'

-

r--

-

a

C2

R

-

R

a

C2
R

Q3
(6) 2

S

Q'-

Cl

1 (5)
16(4)
8 (12)

53
(9) 5

Q-

L51

= Pin
= Pin
= Pin

(7J

5
Q-

52

VCC1
VCC2
VEE

Q2
4 (81

52

(1) 13

5
L

Q-

L51

~

9

Ql

51
(14110

(3) 15

1131

Q-

51

r--

-

Q'

02

-

o-

r - C2
R

(13) 9
Reset
(2) 14

(7) 3 (

71111
00

C2

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-51

MC101.38/MC10538

COUNTER STATE DIAGRAM - POSITIVE LOGIC

ao connected

Clock connected to C2

to C2

•
P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC1 0138 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10538 only

-55°C
Characteristic
Power Supply Drain Current
Input Current
Pin 12
Pins 5,6,10,11
Pin 7
Pin 9
Switching Times
Propagation Delay
Clock to QO, 00
Clock to Ql, Q2, Q3, 03
Set
Reset

Symbol
IE

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

-

97

-

97

-

88

-

97

-

97

-

375
415
495
700

-

350
390
460
650

-

220
245
290
410

-

220
245
290
410

-

220
245
290
410

Unit
mAdc
}.lAde

linH

-

-

-

ns
tpd
1.4
1.4
1.4
1.4

5.5
6.2
5.2
5.5

1.4
1.4
1.4
1.4

5.0
5.2
5.2
5.2

1.5
1.5
1.5
1.5

4.8
5.0
5.0
5.0

1.5
1.5
1.5
1.5

5.3
5.5
5.5
5.5

1.5
1.5
1.5
1.5

5.5
6.2
6.2
6.2

Rise Time, Fall Time
(20% to 80%)

t+,t-

1.1

4.7

1.1

4.7

1.1

4.5

1.1

5.0

1.1

5.0

ns

Counting Frequency

fcount

125

-

125

-

125

-

125

-

125

-

MHz

-55°C and +125 0 C test values apply to MC105xx devices only.

3·52"

MC10141/MC10541
FOUR-BIT UNIVERSAL
SHIFT REGISTER

The
MC10141/MC10541
is a four-bit
universal shift register which performs shift
left, or shift right, serial/parallel in, and serial/
parallel out operations with no external gating.
Inputs S1 and S2 control the four possible
operations of the register without external
gating of the clock. The flip·flops shift informa·
tion on the positive edge of the clock. The four
operations are stop shift, shift left, shift right,
and parallel entry of data. The other six inputs
are all data type inputs, four for parallel entry
data, and one for sh ifting in from the left
(0 L) and one for sh ifting in from the right
(DR).

III 13
OL

181

4

C

116112

DO

115111

01

1131 9

02

1101 6

D3

(14110

51

11ll 7

52

00

14121

01

15131

02

2

161

03

3

171

DR
191

5
TRUTH TABLE

SELECT

S1

S2

OUTPlIfS

ao nt ,

Parallel Entry

DO

01

02

03

Po

Shift Right"

aln

a2n

a3 n

DR

fShift = 200 MHz typ

H

(Putse

01 nt 1 Q2n+1

Q3 n

Shih Left"

aL

aOn

DIn

Q2 n

SlOp Shift

aOn

aln

02n

03 n

• OutPuts as e).

VEE - -3.2 Vdc

·50 ohm, MC105xx only,
NOTE: All power supply and logic levels are shown shifted 2 volts positive.

3-54

MC1 0153/MC1 0553
QUAD LATCH

DO(7)3----------~~

2(6) QO

GO(9)5--________~----~~,

6 (10) Ql

D 1 (11) 7 ---------+---t
CE(8) 4

VCC1 = Pin 1 (5)
CC(1)13

VCC2'" Pin 16(4)
VEE = Pin 8(12)

D2(13)9--------~~~

G1

(14) 10--------+-------.......81{____

D3(2)14----------~~

The MC10153/MC10553 is a high speed,
low power, quad latch consisting of four
bistable latch circuits with D tYpe inputs and
gated Q outputs, allowing direct wiring to
a bus. When the clock is low, outputs will
follow D inputs. Information is latched on the
positive going transition of the clock. The
MC10153/MC10553 provides the same logic
function as the MC10133/MC10533 except
for inversion of the clock.

11(15)Q2

TRUTH TABLE
G C 0
Q n+1

15 (3) Q3

L
L
L

L
L

t/J --

Don t Care

H

t/J t/J
t/J

L

H

L

an
L

H

H

. F SUFFIX

C=CC+'CE

P D = 310 mW tVP/pkg (No Load)

CERAMIC PACKAGE
CASE 650
MC10553 only

tpd = 4.0 ns typ
t+, t- = 2.0 ns tVl? (20% to 80%)

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648
MC10153 only
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55 0 C
Characteristic
Power Supply Drain Current
Input Current
Pins 3.4.7,9,12,14
Pin 13
Pins 5,10
Switching Times
Propagation Delay
Data
Clock
-Gate
Rise Time, Fall Time
(20% to 80%)
Setup Time
Hold Time

Symbol
IE

-30 0 C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

-

83

-

83

-

75

-

83

-

83

-

415
495
595

-

390
460
560

-

245
290
350

-

245
290
350

-

245
290
350

Unit
mAde
}.lAde

linH
-

-

ns
tpd

t+,t-

1.0 5.8
1.0 6.1
1.0 3.4

1.0 5.6 1.0 5.4
1.0 5.6 -1.0 5.6
1.0 3.2 1.0 3.1

1.0 3.9

1.0 3.6

1.1

5.9
1.2 6.2
1.0 3.4

1.0
1.0
1.0

6.3
6.6
3.6

1.1

3.5

1.1

3.8

1.0

4.1

ns

tset

2.5

-

2.5

-

2.5

-

2.5

-

2.5

-

ns

thold

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

-55 0 C and +125 0 C test values apply to MC105xx devices only.

3-55

•

•

MC1 0158/MC1 0558
. QUAD 2-INPUT MULTIPLEXER
(Non-Inverting)

The MC10158/MC10558 is a quad two
channel multiplexer. A common select input
determines which data inputs are enabled.
A high (H) level enables data inputs DO 0, Dl 0,

Select (13) 9

D2 0, and D3 0 and a low (L) level enables data
inputs DO 1, Dl 1, D2 1, and D3 1.
DO 1 (9) 5 ---+-I-'-L_~
1 (5)

TRUTH TABLE

ao

Select
DO 0 (10) 6 ---+-t'--L_~

01

L

H

H

H

'"
'"

L

H

H

'"
'"

H

L

D 1 1 (7) 3 ----t--+"~
2(6)al









00 01 02 03 04 05 06 07
H
L
L
L
L
L
L
L
L
L

L
L
H
L
L
L
L
L
L
L

L
H
L
L
L
L
L
L
L
L

L
L
L
H
L
L
L
L
L
L

L
L
L
L
H
L
L
L
L
L

L
L
L
L
L
H
L
L
L
L

L
L
L
L
L
L
H
L
L
L

L
L
L
L
L
L
L
H
L
L

.po

vcc1

= 315 ns typ/pkg (No Load)

tpd

= 4.0

= Pin 1 (5)

VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

ns typ

L SUFFIX
CERAMIC PACKAGE
CASE 620

= Don't Care

P SUFFIX

F SUFFIX

PLASTIC PACKAGE

CERAMIC PACKAGE

CASE 648
MC10162 only

CASE 650
MC10562 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic

Symbol

-30°C

+25 0 C

+85 0 C

+125 0 C·

Min Max Min Max Min Max Min Max Min Max

IE

-

Input Current

'inH

-

375

-

350

-

220

-

Switching Times
Propagation Delay

tpd

1.2

6:5

1.5

6.2

1.5

6.0

1.5 6.4

1.3 7.0

t+,t-

1.0

3.6

1.0

3.3

1.1

3.3

1.1

1.0 3.9

Power Supply Drain Current

Rise Time, Fall Time
(20% to 80%)

Unit

84

-

84

-

76

-

84

-

84

mAde

220

-

220

tlAdc
ns

-55 0 C and +125 0 C test values apply to MC105xx devices only.

3-61

3.5

ns

•

MC10163/MC10563
MC10193/MC10593
ERROR DETECTION CORRECTION CIRCUITS

•

The MC10163/MC10563 and the MC10193/
MC10593 are. error detection and correction
circuits. They are building blocks designed for
use with memory systems. They offer economy
in the design of error detection/correction
subsystems for main-frame and add·on memory
systems. For example, using eight MC10163's
together with eight 12·bit parity checkers
(MC1 0160), single·bit error detection/correction

and double·bit error detection can be done on
a word of 64·bit length. Only eight check bits
(80-87) need be added to the word. A useful
feature of this building block is that the
MC10193/MC10593
option
generates
the
parity of all inputs to the block. Thus, if the
MC10193 is applied in a byte sequence,
individual byte parity is automatically available.

MC10163/MC10563 LOGIC DIAGRAM

81(11)7

MC10193/MC10593 LOGIC DIAGRAM

81(11)7
82(10)6
15(3)POA
84(16)12
87(15)11

84(16)12
87(15)11
3(7)P3
85(8)4

85(8)4
86(9)5

86(9)5

2(6)P5

2(6)P0 8
80(13)9
83(14)10

80(13\9
83(14)10

14(2)P1

13(1)P2

IBM CODE
PO A = B1, B2, B4, B7
POB = BO, B3, 85, B6
P1 = B1, B3, B5, B7
P2 = 82, B3, B6, B7

MOTOROLA CODE
P1 = B1, B3, 85, 87

VCC1 = Pin 1(5)
VCC2 = Pin 16(4)
VEE = Pin 8(12)

P3 = B4, B5, B6, B7
Po = 520 mW typ/pkg (No Load)

'Pd =

P2 = B2, B3, B6, B7
P3 = B4, B5, B6, B7
P4= B1, B2, 84, B7
P5 = Byt. (BO, 1,2,3,4,5,6,7)
tpd = 7.5 ns typ (to P5)

5.0 ns typ

= 5.0 ns typ (to P1-P4)

Numbers at ends of terminals denote pin numbers for Land P packages.

Numbers in parenthesis denote pin numbers for F package.

3-62

MC 10 163/MC 10563, MC 10 193/MC 10593
SWITCHING TIME WAVEFORMS@ 25°C

'"'","'"
~}
(MC10~

Output 2(6)
POB

-

B5 Biased at V,H
Even Parity on inputs
(See logic diagram)

Output 2(6)

P5Byte(MC~

'"'"''''''~}

Output 2(6)

~

POB(MC101~

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10163 and
MC10193 only

~
L SUFFIX

CERAMIC PACKAGE
·CASE 620

Odd Parity on Inputs
(See logic diagram)

Output 2(6)
P5 Byte (MC10193)

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10563 and
MC10593 only

-55°C
Characteristic

Symbol

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

-

137

-

137

-

125

-

137

-

137

Pins 4,6,10

-

375

350

-

220

450

425

-

265

-

220

-

-

220

Pins 5,7,9,11,12

-

Power Supply Drain Current
Input Current

IE

Unit
mAde
pAdc

linH
265

265
ns

Switching Times
Propagation Delay

tpd
7.0

1.3

6.8

1.3

7.1

1.3

6.8

1.5

6.5

1.5

1.8

9.1

1.8

8.9

2.0

8.5

2.0

1.3

MC10163/MC10563
MC10193/MC10593 B to Pl-P4
B to P5
Rise Time, Fall Time

1.5

6.5

1.5

1.5

7.5

7.1

1.5

11

9.2

2.0

10

7.1

ns

t+,t-

(20% to 80%)
MC10163/MC10563

1.1

4.4

1.1

4.2

1.1

3.9

1.1

4.4

1.1

4.5

MCl 0193/MCl 0593

1.1

4.3

1.1

4.2

1.1

3.9

1.1

4.4

1.1

4.6

-550C and +125 0 C test values apply to MC105xx devices only.
MC10163/MC10563 APPLICATIONS INFORMATION
PO B of the "zero" byte, POA of the "one"
byte, ---, POB of the "th ree byte and data
bit 32.)
During the memory read operation, the
fetched check bits previously generated (as
described)
are exclusive-ORed with newly
generated CO-C32 to generate syndrome bits
SO-S32. Syndrome ST is a special case where
ST is the even parity of all eight fetched check
bits and all 64 fetched data bits. For determining the type and location of an error:
1. If all syndromes (SO-S32 and ST) are
false, there is no error:
2. If ST is true and SO-S32 are false, the
CT is in error.
3. If ST is false and one or more of SO-S32
is true, an uncorrectable error has occurred.
4. If ST is true and one or more of SO-S32
is true, simply add the Sl-S32 bits to get the
binary location of the error (Sl has weight 1,
S2 weight 2, S4 weight 4, etc.)
Data bits BO and B32 are special cases of
this location technique: BO is in error if ST, SO,
and S32 are true; B32 is in error if ST, SO, S 1,
and S32 are tru e.

The MC10163/MC10563 is a building block
for generating the modified Hamming singleerror-co rrecti on, dou b I e~e rro r-detecti on
(SEC-OED) code used in the IBM370/145
memory. While the MC10163 can also be used
for generating other patterns, it is optimized
for generating ·the pattern shown in the H
matrix of Figure 1.
When writing into a memory, the MC10163
is used to generate· the eight check bits
(CO-C32, CT) which are stored with the 64
data bits (BO- B63). These check bits are
generated by taking the parity of all data bits
marked with an X in the appropriate row of the
H matrix. (CO, C1, C32, CT, are even parity;
C2, C4, C8, C17, are odd parity.) To generate
these check bits with the building blocks, eight
MC10163's and eight MC10160 parity checkers
are used. One MC10163 is connected to each
byte of data and the outputs of these building
blocks are connected to the eight MC10160
parity checkers, one for each check bit. Figure
2 shows which connections are required (i.e.,
CO is the eV'ln parity of output POA of the
MC10163 on the "zero" byte of data, output

.

3-63

•

•

S

FIGURE 1 - 370/145 PATTERN

n
......
o......

C)

W

S

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

n
......
o

BYTE 7

~~~~~~~~
0 1 2 3 4 5 6 7 8 910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626381T

x x x x x x x x x x

co

x x x x

x Cl
C2

x C4

x x

xxxxxxxxCS
x

x x x x

x x x x x

x x x

x x x x x x x x x x x

x x

x x x C16
x C32
x CT

U"I

C)

,eN

S

n
......
o
......

to
W

S
n
......
o

U"I

<.0

w

W

OJ

"""
FIGURE 2 - 370/145 PATTERN GENERATION

co =

POBI

POA2

POB3

B(32)

Pll

P12

P13

P14

POB2
P15

POA3

Cl = Pl0

P16

P17

8(32)

C2 = P20

P21

P22

P23

P24

P25

P26

P27
P37

POAO

POBO

·POAI

C4 = P30

P31

P32

P33

P34

P35

P36

C8= POAI

POBI

POA3

POB3

POA5

POB5

POA7

POB7

C16 = POA2

POA2

POA3

POB3

POA6

POB6

POA7

POB7

C32 = POA4

POB4

POA5

POB5

POA6

POB6

POA7

POB7

B(O)

CT= POAO

POBI

POB2

POA3

POA4

P085

POB6

POA7

B(O)

Where for PNM: N = MC10163 Output
M = Byte Number

MC10163/MC10563, MC10193/MC10593

The MC10193/MC10593 is a building block
for generating modified Hamming SEC-OED
codes. It can be used for any length data word
and for a variety of codes. The MC10193 is
optim ized for codes organ ized on a byte
repetitive basis and has the advantage of auto~
matically supplying whole byte parity (P5
output). While it is possible to use a number of
criteria for choosing a pattern, the pattern of
Figure 3 was chosen on the basis of speed and
ease of error location decode. As can be seen in
the H matrix of Figure 3, the pattern is repetitive by byte with the various rows generated by
only five combinations of bit parities with in the
bytes. For the 64 bit data word in the example
of Figure 3, the eight check bits (864 to 871)
are generated by the odd parity of all data bits
indicated by an X in the appropriate row. The
syndromes Sl to S8 are generated by including
the fetched check bits in the same generator
that orjginally generated the check bits.
The pattern of Figure 3 is easily generated
by using eight MC10193 devices, one for each
data byte and eight MC10160 parity checkers,
one for each syndrome/check bit. The connections of building blocks and parity checkers are
shown in tabular form in Figure 4 and in
schematic form' in Figure 6.
Once the syndrome bits (Sl to S8) have
been formed from fetched data (80 to 863)
and fetched check bits (864 to 871), the
determination of type and location of error is
simply done:
1. If all syndromes are false, there is no
error.
2. If one syndrome is true, the corresponding check bit is in error.
3. If more than one syndrome is true, and
the parity of all syndromes is even, a multiple
(uncorrectable) error has occu rred.
4. If more than one syndrome is true, and
the parity of all syndromes is odd, a single
error has occurred and is easily located by the
circuit of Figure 5.
Figure 5 gives the error location circuit for
the example pattern. The outputs E80 to E86
are a one-of-eight-h igh code giving the byte in
error. Outputs ECO to EC3 give the binary
location of the bit in error within the located

;;;:;;tn~~f8~~
~

g
ill

.
ill
~

~

:g
~

:;:
lil
U>

g
ill
ill
~

U>

ill
U>

'"~

(;l

&l

w
oJ

D.

~

«
x

w
2:

rr.
w

II-

«
D.
«
oJ
0

rr.

0

I-

'"

)(

)(

)(

·

.'"
~

.:s
:I
.
U>

:1
N

;;
51

'"'"
'"'"
'"
'"
'"
'"
;J;
U>

'"
'"NM

I

'"g
III
ill
~

X')II;

...

)(

·

N

::J

:e

II..

;t

~

)(

11'"

~

w
rr.

)C

0

0

M

·

x

'"
N

fl
N
N

'"
1;l
~

·

2!

::
~

:!!
:!
::?

)()()()(

II()(

~

::
2
~

byte.
)()(

II()()(

Since this location process can occur

simultaneously with the determination of error
type described, the entire error correction
sequence (using a toggling fetched data latch)
takes less than 20 ns. Th is is because an error 'occu rrence detector is a simple 0 Ring of S 1
to S8. The error locator has simultaneously
located the error wh ich is then corrected as
through the error was a single (and therefore
correctable) error. The parity of syndromes
then determines if the error was indeed single,
and interrupts the CPU if the error was an
uncorrectable (multiple) error. Since uncorrec-

I()(

3-65

II

MC10163/MC10563, MC10193/MC10593
table data is unusable without special handl ing,
the CPU would be interrupted anyway; therefore this automatic correction of any error
as if it were single does not create any problems_
This fast' error correction technique allows

single erorr correction on a non-interrupt basis
with only a 20 ns memory system access time
penalty.
These
techniques
can,
of course,
be
extended to large or smalier data words_

FIGURE 4 - M2 PATTERN BUILDING BLOCK

SI =

Pl0

Pl1

P12

P13

P54

P55

P56

B(~)

S2=

P20

P21

P22

P23

P54

P55

P57

B(65)

S3 =

P30

P31

P32

P33

P54

P56

P57

B(66)

S4 =

P40

P41

P42

P43

P55

P56

P57

B(67)

S5=

P14

P15

P16

P17

P50

P51

P52

B(68)

S6=

P24

P25

P26

P27

P50

P51

P53

B(69)

S7 =

P34

P35

P36

P37

P50

P52

P53

B(70)

S8=

P44

P45

P46

P47

P51

P52

P53

B(71)

Where for PNM: N = MC10193 Oulput
M = Byte Number

•

FIGURE 5 - M2 PATTERN CORRECTION MATRIX

55

sa _

57 58 D - - - E B O

55-

56 57

sa

D---EBI

55

56 57
-

sa

D - - - EB2

sa 57
- sa

D - - - EB3

55

51---ECO
52 - - - ECt
53---EC2
55 - - - E C O

Sf 52 53 54 D - - - E B4
-Sf5253

54

56 - - - ECI
57---EC2

D---

. EB5

Sf 52 53 54
- D - - - EB6
51 52 53 54 D - - - EB7

3-66

I .
j

Byte. 0-3

I

I

Byt.s4·7
.

MC10163/MC10563, MC10193/MC10593
FIGURE 6 - SYNDROME AND CHECK BIT GENERATOR, M2 PATTERN

Bit

p

1
2
3

10
20
30

".,{ 'IJ
~
6
7

"1" for Check Bi ts

MC10160

21
31
41
51

20
22
54
57

3

MC10193

~~

MC10160

30
32
54
57

MC10193.

.[I]

31
33
56

53

MC10160
B6~6

40
42
55
57

41
43
56

54

MC10160

867

14
24
34
44
54

39

52

865

13
23
33

31

21
23
55

MC10193

MC10193

51

864

12
22.
32
42
52

23

11
13
55

MC10193

{

15

10
12
54
56

40
50

IJ"
,{ "IJ
f"IJ
.{ "IJ
,

"0" for Syndromes

14
16
50
52

15
17
51
MC10160

868

15
25
35
45
55

55

24
26
50
53

25
27
51

56

MC10160
869

'[IJ
,{ ::IJ

16
26
36
46
56

34
36
50
53

35
37
52

57

MC10160
870
17
27
37
47
57

44
46
51
53

45
47
52

58

MC10160

B7f

3-67

•

MC10164/MC10564
8-LlNE MULTIPLEXER

A (11) 7

The
MC10164/MC10564
can
be used
wherever data multiplexing or parallel to serial
VCC1 = Pin 1 (5)
conversion is desirable. Full parallel gating
8 (13) 9
VCC2 = Pin 16 (4)
perm its equal delays through any data path.
VEE = Pin 8 (12)
The output of the MC10164 incorporates a
C (14)10
buffer gate with eight data inputs and an
Z
Enable(6)2------~+4r+~+_--------~
15 (3) enable. A high level on' the enable forces the
output low. The MC10164 can be connected
directly to a data bus, due to its open emitter
output and output enable.
Figure '1 illustrates how a 1-of-64 line
X1 (9)' 5
multiplexer can be built with eight MC10164's
wire ORed at their outputs and one MC10161
X2 (8) '4
to drive the enables on each multiplexer,
without speed
degradation over a single
MC10164 being experienced.

----lkttt=!~L;
----t=t:t:t=I:::t==L.---

II

X4

(15)11----~bt~~~c=~~

Po = 310 mW tVP/pkg (No Load)
tpd = 3.0 nstyp (Data to output)

X6 (1) 13--,----t:=I==t=L./

X7 (2)

P SUFFIX

14-----=======L./

PLASTIC PACKAGE
CASE 648
MC10164 only

TRUTH TABLE

-------H---------------,

D2(1)13

)
~L_~------~~-----"

~3(7)QO

D3( 13) 1 0

--I"')
l-/r---rlH--!---------1

D4(15)11

D5(16)12

t)

D6(13)9

--LJ=

D7(10)6

-D-

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-71

•

MC10165/MC10565

select the one of 64 different system conditions, as represented at the encoder inputs,
which has priority in determining the next
system operation to be performed. The binary
code showing the address of the highest priority
input present will appear at the encoder outputs
to control other system logic functions.

A typical application of the MC10165/
MC10565 is the decoding of system status on
a priority basis. A 64 line priority encoder is
shown in the figure below. System status lines
are connected to th is encoder such that, when
a given condition exists, the respective input
will be at a logic high level. This scheme will

54-LINE PRIORITY ENCODER

LSB

Iz
MC10164
XO. ... .. X7ABC

112 MC10l0l

•

System
Clock

Highest
Priority
Input

~~

"TI

DO ~ 01

.,1.

:; 03
D7

i

J

i
J
iI
ol-

i

J
i

J
i
J
Lowest
Priority
Input

iI
oL-

0

u

C
DO

.,"'
;;

/11

II

Iz

H

MC10164
XO ..... X7ABC

II I

00

C
DO

"'.,

r-==:
-;::::

00
01
U 02
:; 03
D7

---;

C
DO

"'.,

-

0

00
01
02
U
:; 03
D7
0

.,"'

00
01
U 02
:;
03
D7
0

D7
C
DO

.,"'

;;
U
:;

00
-<>
01--<>
02,....->-<> MSB

D7

-

-

00
01
U 02
:; 03
D7

number of
highest priority
channel present
at input

II I

~l
~O

-

.,"'
;;

Six bit output
word yielding

" X7 ABC

.--

C
DO

C
DO

"

02

01
u,02
D7 :; 03

C
DO

XO.

I

Iz
MC10164'

00
01
02
03

"'.,

00
01
U 02
:; 03
D7
0

3-72

r-

MC10166/MC10566
5-BIT MAGNITUDE COMPARATOR

The MC10166/MC10566 is a high speed
expandable 5-bit comparator for comparing
the magnitude of two binary words. Two

:::~~: :~--------~

>

outputs are provided: A < B and A
B. A = B
can be obtained by NOR ing the two outputs
with an additional gate. A high level on the
enable function forces both outputs low.
Multiple MC10166s may be used for larger
word comparisons.

" "6' " r--;:L>

2 (6) A >8

83(15) l l I D

PD = 440 mW typ/pkg (No Load)
tpd = Data to output 6.0 ns typ
E to ou tput 2.5 ns typ

3(7)AB

H

x

I

X

L

L

L

L

L SUFFIX

CERAMIC PACKAGE

B

L

H

CERAMIC PACKAGE

Word B

H

L

CASE 620

CASE 650
MC10566 only

L

Word A '" Word

L

Word A

> Word

L

Word A

<

e

F SUFFIX

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-73

•

•

MC10166/MC10566
-55°C
Characteristic
Power Supply Drain Current
Input Current
Switching Times
Propagation Delay
Data
Enable
Rise Time, Fall Time
(20% to 80%)

Symbol

+25 0 C

-30°C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

Unit

IE

-

117

-

117

-

106

-

117

-

117

mAde

linH

-

375

-

350

-

220

-

220

-

220

IJ.Ade
ns

tpd

t+,t-

LO 8.2
1.0 3.9

1.0 8.0
1.0 3.8

1.0 7.6
1.0 3.6

1.0 8.4
1.0 4.0

1.1

1.0 3.6

1.1

1.1

3.8

3.5

3.8

1.0 8.9
1.0 4.2
1.1

4;1

ns

·55 0 C and +125 0 C test values apply to MC109XX devices only.

B24
A24
B23
A23
B22
A22
B21
A21
B20
A20

B4
A4
B3
A3 AB
Al
BO
AO

B19
A19
BIB
AlB
B17
A17
BIS
AIS
BIS
AIS

54

B14
A14
B13
A13
B12
A12
Bl1
~11

Bl0
Al0
B9
A9
A8
A7

BB
B7
BS,

AS
BS
A5
B4
A4
B3
... 3
B2
A2
Bl
A1
BO
AO

FIGURE 1 - 9·BIT MAGNITUDE COMPARATOR

AOBOA1B1A2B2A3B3A4B4

ASBSASBSA787A8B8

Bl
A4
B3
A3 AB
A1
BO
AO

MC101SS

MC101S,S
A>B

AB

AB ABI--4---A>B
Bl A>B
.....----1 Al
Al
The
MC10166/MC10566
compares the
BO
BO
magnitude of two 5·bit words. Two outputs are
AO
AO

>

provided which give a high level for A
B
and A
B, The A ~ B function can be obtained
by wireORing these outputs (a low level indio

<

B4
A4
B3
A3 AB
Al
BO
AO

cates A ~ B) or by NO Ring the outputs (a
high level indicates A ~ B),
For longer word lengths, the MC10166 can
be serially expanded or cascaded. Figure 1
shows two devices in a serial expansion for
a 9·bit word length. The A > B and A
B
outputs are fed to the AO and BO inputs res·

<

pectively of the next device. The connection
for an A ~ B output is also shown. The worst

B4
A4
B3
A3AB
Al
BO
AO

case del ay time of serial expansion is equal to
the number of comparators times the data·tooutput delay.
For shorter delay times than possible with
serial expansion, devices can' be cascaded.
Figure 2 shows 'a 25-bit cascaded ,comparator
whose worst case delay is two data-to-output
delays. The cascaded scheme can be extended
to longer word lengths.

FIGURE 2 - 25·BIT MAGNITUDE COMPARATOR

3-74

MC1 0168/MC1 0568
QUAD LATCH

The MC10168/MC10568 isa quad latch with

00(7)3---~

GO(9)5~~==~~==~~~

G1

(8)4~------~

common clocking to all four latches. Separate
output enabling gates are provided for each
latch, allowing direct wiring to a bus. When the
clock is high, outputs will follow the 0 inputs.
Information is latched on the negative·going
transition of the clock.

2 (6) QO

6 (10) Q1

TRUTH TABLE

01 (11) 7 ~----'-I

Cc

G

C

0

H

0

0

L

L

L

0

Qn

L

H

L

L

L

H

H

H

(1) 13

02 (13) 9 -+----'-1

G2 (16) 12 -t--------t.~/

G3(14) 10-t-==~~===-~

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10168 only

11 (15) Q2

Qn+ 1

•

0= don't care

15(3)Q3

03 (2) 14----"'-1

Po = 310 mW typ/pkg (No Load)
tpd:

G

to Q = 2 ns tyP
o to Q = 3 ns typ
C to Q = 4 ns typ

VCC1 = Pin 1 (5)
VCC2

=

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10568 only

L SUFFIX
CERAMIC PACKAGE
CASE 620

Pin 16 (4)

VEE = Pin 8 (12)

Numbers at ends of terminals denote pin numbers for Land P package
Numbers in parenthesis denote pin numbers for F package
'

-55 0 e
Characteristic
Power Supply Drain Current
Input Current

Symbol

IE

+85 0 e

+125 0 e

-

83

-

82

-

75

-

82

-

83

-

415
450
495

-

390
425
460

-

245
265
290

-

245
265
290

-

245
265
290

Propagation Delay

-

ns

"

tpd

Data
Gate
Clock
Rise Time, Fall Time

Unit
mAdc
MAdc

-

Switching Times

to

+25 0 e

linH

3,7,9,14
Pins 4,5,10,12
Pin 13
Pins

(20%

-30 o e

Min Max Min Max Min Max Min Max Min Max

t+,t-

1.0 5.8 1.0 5.6 1.0 5.4 1.1
1.0 3.4 1.0 3.2 1.0 3.1 1.0
1.0 6.1 1.0 5.8 1.0 5.6 1.2
1.0 3.9 1.0 3.6 1.1 3.5 1.1

5.9
3.4
6.2
3.8

1.0 6.3
1.0 3.6
1.0 6.6
1.0 4.0

ns

80%)

Setup Time

tset

2.5

-

2.5

Hold Time

thold

1.0

-

1.0

-550C and + 125 0 C test values apply to MC1 05xx devices only.

3-75

/

2.5

-

2.5

-

2.5

-

ns

1.0

-

1.0

-

1.0

-

ns

MC1 0170/MC1 0570
9 + 2-BITPARITY

GENERATOR-CHECKER

The MC10170/MC10570 is an ll-bit parity
circuit, which is segmented into 9 data bits
and 2 control bits.
Output A generates odd parity on 9 bits;
that is, Output A goes high for an odd number
of high logic levels on the bit inputs in only
2 gate del a·ys.
The Control I nputs can be used to expand
parity to larger numbers of bits with minimal
delay or can be used to generate even parity.
To expand parity to larger words, the MC10170
can be used with the MC10160 or other
MC10170's.

'--------+'r-...

Control (1) 13 High
Inputs (2) 14 Low _ _ _ _ _ _ _--+!

15 (3) B
Even

Parity

00 (7) 3
01 (8) 4
02(9)S
D3(10)6
D4 (11) 7
DS (13) 9

~-----2

(6) A

Odd
Parity

D6(14)10
D7(lS)11
08(16)12

-

OUTPUTS

INPUTS
Sums of
D Inputs
at High Level

Odd ParitY

Even ParitY

Output A

Output B

Even

Low

High

Odd

High

Low

P SUFFIX'
PLASTIC PACKAGE
CASE 648
MC10170 only

VCC1~Pin

l(S)
VCC2 = Pin 16 (4)
VEE=Pin 8(12)

PD = 300
tpd = 2.S
4.0
6.0

mW typ/pkg (No Load)
ns typ (Control to B)
ns typ (Data to A)
ns typ (Data to B)

L SUFFIX

F SUFFIX

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 6S0
MC10S70 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-5SoC
Characteristic
Power Supply Drain Current
I nput Current
Switching Times
Propagation Delay
Control
Data to A
Data to B
Rise Time, Fall Time
(20% to BO%)

Symbol

-30°C

+2SoC

+8SoC

+12SoC

Min Max Min Max Min Max Min Max Min Max

Unit

IE

-

78

-

78

-

71

-

78

-

78

mAdc

linH

-

375

-

350

-

220

-

220

-

220

MAdc
ns

tpd'
1.5 4.6 1.5 4.2 1.5 4.0 1.5 4.4 1.5 4.8
2.0 7.S 2.0 6.6 2.0 6.0 2.0 6.6 2.0 8.0
4.0 10 4.0 9.5 4.0 8.B 4.0 9.5 4.0 10.5
t+,t-

1.5 4.5

1.5 4.3

-SSoC and +12S o C test values apply to MC10Sxx devices only.

3-76

1.5 3.9

1.5 4.3

1.5

4.B

ns

MC10171/MC10571
DUAL BINARY TO 1-4 DECODER
(LOW)

EO 12114

The MC10171/MC10571 is a binary-coded
2 line to dual 4 line decoder
with selected
outputs low. With either EO or E 1 high, the
corresponding selected 4 outputs are high. The
common enable E, when high, forces all
outputs high.

101141 ao 3

111151 ao 2

121161 ao 1

P SUFFIX

13111 ao 0

PLASTIC PACKAGE
CASE 648
MC10171 only

3171 a1 3

•

4181 a1 2

VCCl = Pin 1 (5)
"'CC2

5 191 a1 1

=

Pin 16 (4)

VEE = Pin 8'(12)

i; 1101 a1 0

PD

=

L SUFFIX

325 mW typ/pkg
(No Load)

CERAMIC PACKAGE
CASE 620

tpd = 4.0 ns typ

TRUTH TABLE
ENABLE INPUTS

INPUTS

OUTPUTS

E

EO

El

A

B

010

011

012

013

000

001

002

003

L
L
L
L
L
L
H

L
L
L
L
L
H

L
L
L
L
H
L

L
L
H
H
L
L

L
H
L
H
L
L

1>

1>

1>

1>

L
H
H
H
H
L
H

H
L
H
H
H
H
H

H
H
L
H
H
H
H

H
H
H
L
H
H
H

L
H
H
H
L
H
H

H
L
H
H
H
H
H

H
H
L
H
H
H
H

H
H
H
L
H
H
H

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10571 only

cP = Don't Care
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55 0 C
Charaeteristi"
Power Supply Drain Current
I nput Current
Switching Times
Propagation Delay
Rise Time, Fall Time

-30°C

+25 O C

+85 0 C

+125 0 C

Symbol Min Max Min Max Min Max Min Max Min Max

Unit

IE

-

85

-

85

-

77

-

85

-

85

mAde

linH

-

375

-

350

-

220

-

220

-

220

/-LAde

tpd
t+,t-

1.3 6.5

1.5 6.2

1.5 6.0

1.5 6.4

1.2 7.0

1.0 3.6

1.0 3.3

1.1

1.1

1.0 3.9

ns

·55 0 C and +125 0 C test values apply to Mel 05xx devices only.

3-77

3.3

3.4

ns

MC1 0172/M C1 0572
DUAL BINARY TO 1-4 DECODER
(HIGH)

EO (2) 14

The MC10172/MC10572 is a binary-coded
2 I ine to dual 4' I ine decoder with selected
outputs high. With either EO or E 1 low, the
corresponding selected 4 outputs are low. The
common enable E, when high, forces all
outputs low.

10 (14) 003

11 (15) 002

12 (16)

ao

1

P SUFFIX

A (13) 9

PLASTIC PACKAGE

13 (1) 000

CASE 648

•

MC10172 only
3 (7) 013
B (11) 7
4(8) 012
VCC1

E (3)

15

VCC2

5 (9) 011

VEE
6 (10) 01

E1 (6) 2

°

= Pin
= Pin
= Pin

1 (5)

16 (4)
8 (12)

L SUFFIX
PD = 325 mW typ/pkg
(No Load)

CERAMIC PACKAGE
CASE 620

tpd = 4.0 ns typ

TRUTH TABLE
E

E1

EO

A

B

O~

L

H

L

L

L

H

H
H

L

L

H

H

L

H

011

012

013

000

001

002

003

H

L

L

L

H

L

L

L

H

L

H

L

L

L

H

L

L

H

L

L

H

L

L.

L

H

L

H

H

H

L

L
L,

L

H

L

L

L

H

0

L

L

H

L

L

L

L

L

L

H

L

L

L

F SUFFIX

L

H

L

L

L

H

L

L

L

L

L

L

L

H

0

0

0

0

L

L

L

L

L

L

L

L

CERAMIC PACKAGE
CASE 650
MC10572 only

o = Don't Care
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Current
Input Current
Switching Times
Propagation Delay
Rise Time, Fall Time

-30°C

+25 0 C

+85 0 C

+125 0 C

Symbol Min Max Min Max Min Max Min Max Min Max

Unit

IE

-

85

-

85

-

77

-

85

-

85

mAde

linH

-

375

-

350

-

220

-

220

-

220

!lAde
ns

tpd
t+,t-

1.3 6.5

1.5 6.2

1.5 6.0

1.5 6.4

1.2 7.0

1.0 3.6

1.0 3.3

1.1

1.1

1.0 3.9

-55°C and +125 0 C test values apply to MC105xx devices only.

3-78.

3.3

3.4

ns

MC10173
QUAD 2-INPUT
MULTIPLEXER/LATCH

The MC10173 is a quad two channel multiplexer with latch. It incorporates common
clock and common data select inputs. The
select input determ ines wh ich data input is
enabled. A high (H) level enables data inputs
DOO, D 1 0, D20, and D30 and a low (L) level
enables data inputs DOl, Dll, D21, D31.
Any change on the data input will be reflected
at the outputs while the clock is low. The
outputs are latched on the positive transition
of the clock. While the clock is in the high

Select 9

1 00
000 6

001 5

2 01
010 4

state, a change in the information present at
the

data

inputs

will

not affect the output

information.

011 3

TRUTH TABLE
1502

SELECT CLOCK

020 13

021

12

OOn+l

H

L

000

L'

L

001

¢

H

OOn

VCC = Pin 16
VEE

= Pin

8

r:P = Don't Care

1403
030 11

031

10

Clock 7 - - - - - - '

PD = 275 mW typ/pkg (No Load)
tpd = 2.5 ns typ

P SUFFIX

L SUFFIX

PLASTIC PACKAGE
CASE 648

CERAMIC PACKAGE
CASE 620

-30°C
Characteristic
Power Supply Drain Current
Input Current
Pins 3,4,5,6,10,11,12,13
Pins 7,9
Switching Times
Propagation Delay
Data
Clock
Select
Rise Time, Fall Time
(20% to 80%)

Symbol
IE

+25 0 C

+85 0 C

Min Max Min Max Min Max

-

73

-

66

-

73

-

470
400

-

295
250

-

295
250

Unit
mAdc
J..LAdc

linH

ns
tpd

t+,t-

Setup Time
Data
Select

tset

Hold Time
Data
Select

thold

3-79

0.8 3.7
1.6 7.2
-1.1 6.2

1.0 3.5
1.6 6.8
1.3 5.7

1.1 5.3
1.4 6.8
1.2 6.7

1.2 4.0

1.5 3.5

1.4 4.0

ns
ns

2.0
3.0

-

2.0
3.0

-

2.0
3.0

-

2.5
1.5

-

2.5
1.5

-

2.5
1.5

-

ns
-

•

•

MC10174/MC10574
DUAL 4-TO-1

XO

Xl

X2

(7)

(9)

(8)

X3 (10)

MU~TIPLEXER

3 0----------,,-....

TRUTH TABLE

5 o-------+-+--.

4

ADDRESS INPUTS
A
B

ENABLE

E
2 (6) Z

O------;:::j:t:~:f-....

6 O------I-+-H--.

OUTPUTS
Z

W

H

4>

4>

L

L

L

L

L
L
L

L
H
H

L
H

XO
Xl
X2
X3

YO
Yl
Y2
Y3

L
H

cJ>::::: Don't Care
A (11)

7

8 (13)

9

Enable (2)

YO

(1)

14,0-----++-Hf------~

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10174 only

13 o - - - - - - I - + - H - - !

Yl (15) 11 0 - - - - - - I - 1 - f . J - !
15 (3) W
Y2 (16) 12

Y3(14)

o-------t==t~

100-----~==~

P D = 305 mW typ/pkg (No Load)
tpd = 3.5 ns typ (Data to output)

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10574 only

L SUFFIX
CERAMIC PACKAGE
CASE 620

VCC1 = Pin 1 (5)
V CC2 = Pin 16 (4)
VEE = Pin 8 (12)

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55 0 e
Characteristic
Power Supply Drain Current
InpLit Current
Pins 3,4,5,6,7,9,10,11,12,13
Pin 14
Switching Times
Propagation Delay
Data
Select (A,B)
--Enable
Rise Time, Fall Time
(20% to 80%)

Symbol
IE

-30 o e

+25 0 C

+85 0 e

+125 0 e

Min Max Min Max Min Max Min Max Min Max

-

,80

-

80

-

73

-

80

-

80

-

375
565

-

350
525

-

220
330

-

220
330

-

220
330

Unit
mAdc
!JAdc

linH

-

-

ns
tpd

t+,t-

1.3 4.6
1.8 6.1
O.~ 3.0

1.4 4.8 1.5 4.5
1.9 6.4 2.0 6.0
1.0 3.1 1.0 2.9

0.9

1.0 3.4

3.3

-55°C and +125 0 C test values apply to MC105xx devices only.

3-80

1.1

3.3

1.4 4.8 1.2 4.5
2.1 6.4 1.9 6.0
0.9 3.2 0.9 2.9
1.1

3.6 0.9

3.4

ns

MC10175/MC10575
QUINT LATCH

00(14)10-------1

14(2)00

01 ( 16) 12 -----t-t---i

15(3)01

02( 1) 1 3 - - - - - H I - !

2(6)02

03 ( 13) 9 - - - - - I - I - - l

3(7)03

04(9) 5-----+-+-1

The MC10175/MC10575 is a high speed,
low power quint latch. It features five 0 type
latches with common reset and a common
two-input clock. Data is transferred on the
negative edge of the clock and latched on the
positive edge. The two clock inputs are
"OR"ed together.
Any change on the data input will be
reflected at the outputs while the clock is low.
The outputs are latched on the positive transition of the clock. While the clock is in the
high state, a change in the information present
at the data inputs will not affect the output
information. The reset input is enabled only
when the clock is in the high state .
TRUTH TABLE

-

4(8)04

PLASTIC PACKAGE
CASE 648
MC10175

Cl(ll)7
Reset(15)11------~-~

CO

C1

Reset

L
H

L

L
L




H


L
L
L
L
L
L
L
L
L
L
L
L
L
L·
L
L

L
L
L
L
L
L
L
L
L
L
L
L

r.P

=:

The
MC10178/MC10578
is a four-bit
counter capable of divide-by-two, divide·byfour, divide-by·eight or a divide-by·sixteen
function.
Clock inputs trigger on the positive going
edge of the clock pulse. Set and Reset inputs
override the clock, allowing asynchronous "set"
or "clear". Individual Set and common Reset
inputs are provided, as well as complementary
outputs for the first and fourth bits. True
outputs are available at all bits.

OUTPUTS

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

C2 00101

....
....
......




H

L
H

....
....
..

H

L
H

J HL

No Count
No Count

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

....
....

02103

IL J
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
.H
H

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

Don t Care

••

JVIH

Clock transition from VIL to VIH
may be appl ied to C 1 or C2 or both
for same effect.

V IL

Po

-

= 370 mW typ/pkg (No Load)

ftoggle = 150 MHz (typ)
tpd = 3.5 ns typ (C to 00)
= 11 ns typ (C to 03)

P SUFFIX

-

PLASTIC PACKAGE
CASE 648
MCl 0178 only

L SUFFIX

F SUFFIX

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10578 only

VCCl = Pin 1 (5)
V CC2 = Pin 16 (4)
,VEE = Pin 8(12)

so

00
(3)15'

(15) 11

(16) 1 2 -

01

~

Cl

s

Sl
(11 )7

S

0.'1---

0'

' - - - 01

Cl

01
(1) 13

Cl'C'

02
(8)4

S2
(10)6

' - - - 01

s

Cl

0' I - - 0'

S3
(9)5

~

01

s

Cl

03
(6)2

C'Q

Clock

(14)1 0
Cloc

'~ C2

Q

R

01---

Q

Q

R

R

R

Or--

(13) 9
Rese t
(7)3

(2)14

Numbers at ends of terminals denote pin numbers for Land P package.
Numbers in parenthesis denote pin numbers for F package.

3-86

MC10178/MC10578

ELECTRICAL CHARACTERISTICS

Characteristic
Power Supply Drain Current
Input Current
Pins 10,12
Pins 5,6,7,11
Pin 9
Switching Times
Propagation Delay
Clock to 00
Clock to 01
Clock to 02
Clock to 03

-30°C
+85 0 C +125 0 C
-55°C
+25 0 C
Symbol Min Max Min Max Min Max Min Max Min Max
97
88 97 97 97 IE

Unit
mAdc
}JAdc

linH
-

-

415
375
700

-

-

390
350
650

-

-

245
220
410

-

245
220
410

-

245
220
410
ns

tpd
1.4 5.0 1.4 5.0 1.5 4.8
1.9 9.9 1.9 9.4 2.0 9.2
2.9 13 2.9 12.3 3.0 12
3.9 16 3.9 14.9 4.0 14.5
1.4 5.6 1.4 5.2 1.5 5.0

Set, Reset
Rise Time, Fall Time
(20% to 80%)

t+,t-

Counting Frequency

fcount

1.1

4.9 1.1

4.7 1.1

1.5
2.0
3.0
4.0
1.5

4.5 1.1

5.3
9.8
12.8
15.5

1.5 5.6
2.0 10.8
3.0 14
4.0 17
5.5 1.5 6.1
5.0 1.1

5.3

ns

-

MHz

I

125

-

125

-55 0 C and + 125°C test values apply to MC 105xx devices only.

3-87

-

125

-

125

-

125

•

MC10179/MC10579
LOOK-AHEAD CARRY BLOCK

G395----------'"'!

P3111'3 _--._ _ _ _- " ' "......
G211319--+------i

)o------::::'t:::E=I

P2116I'2~_t=?====:::::r-):>--+_H
2161GG

'--t:fFft~[=:>----~-----'513IPG
G1(11)7

---H-+-+-"----t

---H++---"',-"'"

P1l'Ol'O
GolalO ----+-W+----'..L.~~---~;=l

6(10)C n+2

-=:;L:::==::=L./P------'

PO(2) 14 _ _ _

PD = 300 mW typ/pkg (No Load)
tpd = 3.0 ns typ (Carry, Propagate)
= '4.0 ns typ (Generate)
PG
GG
C n +2
C n +4

VCCl = Pin 1 (5)
VCC2 = Pin 16(4)
VEE = Pin 8 (12)

The MC10179/MC10579 is a high speed,
low power, standard MECL complex function
that is designed to perform the look-ahead
carry function. Th is device' can be used with
the MC1018l/MC1058l 4-unit ALU directly,
or with the MCl 0180/MC10580 dual arithmetic
unit in any computer, instrumentation or digital
communication application requiring high speed
arithmetic operation on long word~.
When used with the MC1018l/MC10581,
the MC10179/MC10579 performs a second
order or higher . look-ahead. Figure 2 shows
a 16-bit look-ahead carry arithmetic unit.
Second order carry is valuable for longer binary
words. As an example, addition of two 32-bit
words is. improved from 30 nanoseconds with
ripple-carry tech niques, to 18 nanoseconds with
carry look-ahead techniques. A block diagram
of a 32-bit ALU is shown in Figure 1. The
MC10179/MC10579 may also be used in many
other applications. It can, for example, reduce
system package count when used to generate
functions of several variables.

+ P1 + P2 + P3
+ P1 + P2 + P311G1 + P2 + P3) IG2 + P31 G3
= ICn + PO + P111GO + P1) G1
= ICn + PO + P1 + P2 + P3) (GO + P1 + P2 +P3) (G1 + P2 + P31 (G2 + P31 G3
= PO

= IGO

F SUFFIX
CERAMIC PACKAGE

_

PSUFFIX
PLASTIC PACKAGE
CASE 648
MC1 0179 only

CASE 650
MC10579 only

_LSUFFIX
CERAMIC PACKAGE
CASE 620

Numbers at ends of termin"als denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Gurrent
Input Current
Pins 5,9
Pins 4,7,11
Pin 14
Pin 12
Pins 10,13
Switching Times
Propagation Delay
G or C n to Carry; G or P to GG
P to PG
Rise Time, Fall Time
(20% to 80%)

-30°C

+25 0 C

+85 0 C

+125 0 C

Symbol" Min Max Min Max Min Max Min Max Min Max
IE

-

79

-

79

-

72

-

79

-

79

-

380
460
600
670
750

-

360
430
565
630
700

-

225
270
355
395
440

-

225
270
355
395
440

-

225
270
355
395
440

Unit
mAdc
/-lAdc

linH

-

-

-

ns
tpd

t+,t-

1.0 5.9
1.0 3.9

1.0 5.8
1.0 3.7

1.0 5.5
1.0 3.5

1.0 6.1
1.0 3.9

1.0 6.4
1.0 4.1

1.0 3.9

1.1

1.1

1.1

1(0 4.1

-550 C and +,25 0 C test values apply to MC105xx devices only.

3-88

3.7

3.5

3.9

ns

...os:

FIGURE 1 - 32-BIT ALU WITH CARRY LOOK-AHEAD

(")

...
-...I

cg

C out

81
A6
AI

A'

in

8'

Con

tv

Co

-

en

+ 4

en

r--M
SO

MC10181/MC10581

G

M
SO

r--

4 BIT ARITHMETIC

S1

LOGIC UNIT

,..: 5'

P

53
FO

Fl

F2

F3

85

r-

,---

, - - S1

813
81'
A13

Bl0

?

t'y
en.

9'

8f

,8

4 BIT ARITHMETIC

-

-

en

t

I

,---

-

LOGIC UNIT

4 BIT ARITHMETIC

G

r-

-

SO

, - - S1

LOGIC UNIT

pC-

r - 52

P
Fl

F2

F3

F.

F5

F6

F7

MC10181/MC10581
4 BIT ARITHMETIC

F2

F3

FO

Fl

F2

F3

F14

FIS

M

SO

52
53

Fl

F2

F3

PO

F8

GO

PI

G1

I I I

P2

G2

MC10179/MC1Q579
Cn

P3

F.

Gf-----o
P

en

Fl1

G3

CARRY LDQKAHEAO

C n + :2

FlO

f---o

+ 4

bC1S

FIGURE 2 - 16-BIT FULL LOOK-AHEAD CARRY ARITHMETIC LOGIC UNIT

•

f--o
f---

Pf-

53
Fl

FO

51

FO

4

G

LOGIC UNIT

_52

53
FO

en.

,--- M
MC10181/MC10581

S1

53

I

en

4

M

SO

Bt5

AD BO AlB 1 A2 82 A3 B3

A!80AI81A'B,J3BI,

en

A15

AfT

All

L

4 -{)

MC10181/MC10581 .G

,--52

r-

AI'

"" Al0

B6

AD BO A 1 81 A2 82 A3 83

Cn

r--

co

fr

r"i

AoeD Al B1A2B2AJ 83

A.

F12

F13

MC1 0180/MC1 0580
DUAL 2~BIT ADDERISUBTRACTOR

"1 Sa'A
+---"1 Se'e

so

( 1 1 1 7 - -............

(131 9 -

The MC10180/MC10580 is a high speed,
low power general-purpose adder/subtracter.
Inputs for each adder are Carry-in, operand
A, and operand B; outputs are Sum, Sum, and
Carry-out; The common Select inputs serve
as a control line to invert A for subtract, and
a control I ine to invert B.

15 (3)

......

2

(S)

3

'(7)

(91 5 -+-+-~ AO

(101 6 -+-+-~ 80
(8)' -+-+-~

C out

Con

--

14 (21
1

151

(1511'---~
(14)10---~

(16) 12

II,

-----I

A'

13 (11

= A ® SelA = A 0
® Sels = S (;:)

S' = S

SelA
Sels

P SUFFIX

L SUFFIX

PLASTIC PACKAGE
CASE 648
MC10180 only

CERAMIC PACKAGE
CASE 620

S ~ Gin lA'S' + A'S') + Cin lA'S' + A'S')
Cout = Cin A' + Cin S' + A'S'

VCC = Pin 16(4)
VEE = Pin 8(12)

F SUFFIX
,Po

= 360

CERAMIC PACKAGE
CASE 650
MC10580 only

mW typ/pkg (No Load)

tpd = 2,2 ns typ (Cin to C out )

= 4,5, ns

typ (AO to So or C out )

TRUTH TABLE
INPUTS

FUNCTION

POSTIVE LOGIC DIAGRAM - 1/2 Of Circuit Shown
ADO

SUBTRACT

C," o - - - - - j - j - - - - - + - - i

REVERSE
SUBTRACT

FUNCTION SELECT TABLE
SelA
H

SelB
L

S '" A plus B
S = A minus B

H

S'" B minus A

L

S = 0 minus A minus B

H

Se'8

AD

BO

Con

SO

SO

H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H

L
L
L
L

L
L

L

L

H

H

H
H

L

H
H

L
L

L
L
L

H

L

H

H

H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

Function

Numbers at ends of terminals denote pin numbers for Land P packages,
Numbers in parenthesis denote pin numbers for F package,

3-90

OUTPUTS

SetA

C out

H
H
H
H

L
L

L

H

L

L

H

H
H

L

L
L

H
H

H

H

L

H
H
H

L
L
L
L
L
L
L
L

L
L
L
L

L
L

L

H

L

L

H

'L

H
H

L

L

H
H

H

H

L

H
H
H
H

H

L
L
L
L
H
H
H
H

H
H

L
H
L
H

L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

'L
H
L
H
L
H
L
H

H
H
H

H
H
H
H

H

L
L

L

L

L

H

L

H

H

L

H
H

L
L

H

H

L

H

L
L

L

H

L

L

H

H
H

L
L
H
L
H
H
L

H
H

H
H

H

L
H
L
L

H
L
L
L
H

L
L

L

L
H
H
L
H

L
L
H

H
H

L
L
H

L
H
H
L

H
H

L
H

H
H
L
H
L
H
L
L

MC10180/MC10580

ELECTRICAL CHARACTERISTICS
-55°C
Characteristic
Power Supply Drain Current
Input Current
Pins 5,6,10,11
Pins. 7,9
Pins 4,12
Switching Times
Propagation Delay
Operand, Select
Carry-in
Rise Time, Fall Time
(20% to 80%)

Symbol
IE

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

-

95

-

95

-

86

-

95

-

95

-

375
495
630

-

350
460
590

-

220
290
370

-

220
290
370

-

220
290
370

Unit
mAdc
.uAdc

linH

-

-

-

-

-

ns
tpd

t+,t-

1.0 5.8
1.0 3.6

1.3 5.8
1.0 3.4

1.3 5.4 1.1
1.0 3.3 0.9

5.8
3.6

1.0 6.3
1.0 3.9

1.0 4.0

1.0 3.8

1.1

3.9

1.0 4.3

-55°C and +125 0 C test values apply to MC105xx devices only.

3-91

3.7

1.1

ns

MC10181/MC10581
4-BIT ARITHMETIC LOGIC UNIT
and FUNCTION GENERATOR

POSITIVE LOGIC

52

51

50

L

L

L

L

F

L

L

H

F:

F=Aplus(A.

L

L

H

F

F

L

H

L

H

II

M is High C = D.C.

S3

H

F

F

='

L

L

H

L

H

L

H

H

L

L

H

H

H

=:Ii"

A +B
=A + 8

Logical " ' "

F=

A-8

F=B
F= A

F

=
=

A plus 0

81

A plus (A • B)

F'" A tnnes 2
= (A + B) plus 0
F:::::. tA + B) plus (A •
F

F

H

L

L

@) B
F=AiB
F=A"es

H

L

H

F=AGlB

F

=

Bl

A plus B

f=-A plus (A + Bl
F:::: (A

=- A

H

L

H

L

F= B

F

==

H

L

H

H

F=A+8

F

== A

H

H

L

L

F;:; Logical "0"

F

=

H

H

L

H

F= A

H

H

H

L

F=Aes

H

H

H

H

F=A

e8'

The MC10181/MC10581 is a high-speed
arithmetic logic unit capable of performing
16 logic operations and 16 arithmetic operations
on two four-bit words. Full internal carry is
incorporated for· ripple th rough operation.
Arithmetic logic operations are selected by
applying the appropriate binary word to the
select inputs (Sl through S3) as indicated in
the table of arithmetic/logic functions. GrOllp
carry propagate (PG) and carry generate (GG)
are provided to allow fast operations on very
long words using a seco.nd order look ahead.
The internal carry is enabled by applying a low
level voltage to the mode control input (M).
When used with the MC10179, full-carry
look-ahead, as a second order look ahead block,
the MC10181 provi-<

H=>t

p

II

C>-<

{Jt

"---fL./

~

AO(3)21

81(1)19

--;L>

~

,~

~ 2(8)FO

~

3(9)F1

L
A1(24)18

82(17)11 0-

H=>t

P

,r--

II

gp--

A2(22)16

H=>t

~

7(13)F2

~

.r--"

'--

83(15)9 C>-<

"

6(12)F3
I

~~

""'"

./

A3(16) 10

5(11)C n +4
./

M(5)23

VCC1 = Pin 1 (7)
VCC2 = Pin 24(6)
VEE = Pin 12(18)
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-94

MC1 0182/MC1 0582
2-BIT ARITHMETIC LOGIC UNIT
and FUNCTION GENERATOR

POSITIVE LOGIC
Function Select

51

SO

L

L

L

H

H

L

H

H

Logic Function

Arithmetic Operation

M is High

M is Low

F
F' A
F, A

0B

F::: A plus B plus Carry

(1) B

F,

F"" A • B
F=A+B

If.

plus B plus Carry

F, AplusBplusCarry
F == A times2

Po = 575 mW typ/pkg (No Load)
tpd= 7.5 ns typ (A or B to F or C n +2)
= 2.7 ns typ (C n to C n+2 or F)
~

~YU U

- ,., 0' '" (A ,0 'G o.GG'

-

L SUFFIX
CERAMIC PACKAGE
CASE 620

The MC10182/MC10582 is a high-speed
arithmetic logic unit capable of performing
4 logic operations and 4 arithmetic operations
on two 2-bit words. Full internal carry is
incprporated for arithmetic operation.
Arithmetic logic operations are selected by
applying the appropriate binary word to the
select inputs (SO and S1) as indicated in the
tables of arithmetic/logic functions. Group
carry propagate (PG) and carry generate (GG)
are provided for a second order look ahead
carry using the MC10179. The internal carry
is enabled by applying a low level voltage to
the mode control input (M-).
The MC10182 provides an alternate to the
MC1018l four-bit ALU for applications not
requiring the extended functions of the
MC1018l or for applications requiring a 16-pin
package_ The MC10182 also differs from the
MC10181 in that Word A and Word Bare
treated equally for addition' and subtraction
(A plus B, A minus B, B minus Al.

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10182 only

FSUFFIX
CERAMIC PACKAGE
CASE 650
MC10582 only

-55°C
Characteristic

Symbol

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

-

152

-

152

-

138

-

152

-

152

Pins 7,9,10

-

375

350

660

-

495

Pin 13

-

595

-

220

-

-

220

Pins 6,11

-

220

Pins 5,12

-

Power Supply Drain Current
Input Current

IE

/JAdc

linH
620
460
560

390
290
350

390
290
350

390
290
350
ns

Switching Times
Propagation Delay

-

tpd
1.5

5.6

1.6

6.2

1.6

M or S to F; A or B to PG or GG
AOorBOtoF;Al orBl toFl
AO, BO, or A 1 to C n +2

2.3 10.8 2.3 10.5 2.3

10

2.4

11

2.4 11.7

2.3 10.8 2.3 10.5 2.3

10

2.4

11

2.4 11.7

2.3 10.8 2.3 10.5 2.3

10

2.4

11

2.4 11.7

Bl

2.8

13

2.8 12.6 2.8

12

2.9 13.2 2.9

14

1.5

4.9

1.5

4.5

1.6

5.3

C n to C n +2 or F

Unit
mAdc

1.5

to C n +2

Rise Time, Fall Time

t+,t-

6.1

(20% to 80%)
-550 C and +125 0 C test values,apply to MC105xx devices only.

3-95

1.5

5.9

4.7

1.5

5.0

1.6

6.6

ns

•

MCl 0182/MCl 0582

Cn
13(1)
10(14)
50

9(13)
51

M

7(11 )

4(8)

FO
AO

5(9)

80

6(10)

•
12(16)
A1o-----~--~~~--~

81

~--~+---~

11( 15)

__~----~

3(7)

Vce1 = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

3-96'

s:

...o
...

(")

TRUTH TABLE

Input

A1 B1 AO
L
L
L

Ct.)

L

51
50

eo c"

L
L

L
L

L
L
L
L

L
L
L
L
L

L
L
H
H

L

L

L
L

H
H
H

L
L

L

H
H
H
H

L
H
H
H

L

H

H

H

L
H

H
H

L

L

L

L

L

H

L

L
L

L H
H'L

H

L
H
H

H

H

L

H

L
L
L
L

L
H H

H

L

H

H
H

L

cO
......

M

L
L
L

H
H

L

L
H

L
L

L
H

L
H

L
L
H
H

L
H

L
H
H
H

L

L
H

L

H
H
L

H
H
H
L
H

H
H
H
H

L
H
L
L
H

H
H
H
H

L
H

H
H

H

L

L
H
L

L
L
L
H
H

L
H

H
H

H

L

L
H

L L
H H
L L

L

L

L

H

H

H 'L
H L

L

L

L

H

H

L

H

H
H

H L
H H
H'H

H
H
H

L
L
L

L
H
H

L
H

H
H

L
H

L
H
L
H

L

L

L

H

H

H

H

L

L

H

H

L

L

H

H

L

H

L

H

L

H

L

H

H
H
H

L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H

L
L
L
L
L
L
L
L
L
L

H

H,L

L
L
L
H

L

L
L H
H.H
L

H

H
H

H
H

H

L

L

L
L

L
H

H
L

H
H

L
H

H
H

L
H

L
H
H
H

L
L
L
H

L
H

L
L

L
H
H

H
H
H

H
L

H
H
H

H

H

L
L
H
L
H

H
H
H
H
L
L
H
H
H
H
H
H
H
H

H

H

L

H

L
H
H
H
H

L
L
H

L
L
H

H
L

H
H

H

L
H

L
L
H
L
H
H

H

H
L
L

L
H
H
L
L

L
H

H
H

L
H

L
H
.H

H
H
H

L
H
L

H
H

H

H
H

H

H

L
H

H
H

L
H

H

H

L
H

L

L

L

L

L

L

L

L

L
L

L
L

H
H

L
H

H
H

L
L

H

L

L

L

H
H

L
L
H

L

H
H

L

H
H

H
H

H

H
H
H
H
H

H H

H

H
H
H

H
H
H

H
H
H
H

H

L
L

H
H

H
H
H
H

L
L

H

H

H

L
L

L

H

H

H

L

L

H

L

H

L
L

L

H

H
H
H

L

H

H
H
H

L

L

H
H

L

H

L

H

L

H
H

L

H

L

H

H

H
H

H

L
H

L

L
L

L

L
L

L

H
H

H
H

L

L

H
H

L
L
L

H

L
H
H

L
H

H
H

L

H

L
L

L
L
L
L

L
L
L

L

L

L
H
H

L
L

L
L
L
L
L

L
L
L

H

H

':i

L
L

H
H

H
H
H
H
H
H

L
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I..

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I..

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L L
L L
H H
H H
H H
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I.. I..

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H L
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L
L

H H

L

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H
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H

H
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L

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H
L

H H
H H

L
H

H
H

H
H
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H

H
H

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H
H

H

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H
H

H

H

H
H

H

L

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H

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H
H

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H

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H

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H

H

H

H

H

H

L

H
L

L

H
H

L

H
H
H

H

H

H

H

L

L
L

H

L

H
H
H

L
H

H

H
H
H

H

H

L

H

L

L

L

H

L
H

H
H

These outputs are not normally used during logic operation.

II

L

L
L
L
L
L

L

L

L

H
H

L

L
H

H

L

L

H
H

L

H

o

H
H
H
H

L
H
H
H

H
H
H

H
H
H
H

H
H
H

L
L

H H
H

H
H

H
H
H

H
H

U"I
00
N

L
L

H

H
H

H

H
H

L

L
L

L
L

H
H
H

H

L

L
H

L

L
L
H
H

L
H

H

(")

L
L
L
L
L
L

L
L
L
H
H
H

L
L
H

-...s:
00
N

F1 FO PG GG Cn+2 F1 FO PG GG Cn+2 F1 FO PG GG Cn+2 F1 FO PG GG Cn+2 F1 FO PG GG Cn+2 F1 FO PG GG C n +2 F1 FO PG GG Cn+2 F1 FO PG GG Cn+2

L
L
H
H

L
H

-

L

H
H
H
H
-H

H
H
H

H
H

H
H
H

H
H

H

H

H

,

MC10183
4 X 2 MULTIPLIER

TRUTH TABLE
The MC10183 is a 4 X 2 bit multiplier that

I-Y:-~_l+_::-0--ti---o:_l--t--::-;-+--:-~_t-:-~_I-~:--I-~"":"~:""'-:~:-~_~o_"t-c_o_m",,,o':-p:_~e_:_:_"_to_"
H

L

L

H

H

L

L

Add 1X

L

H

L

H

H

L

L

Add 1X

O;'ec'

H

H

L

H

L

H

L

Add 2X

O;,ec'

L

L

H

H

L

~

~

.~

~

:

H

H

H

H

L

can mu I tip I Y 2' s complem ent nu mbers p roducing a 2's complement product without
correction. The device can be used as a 4 X 2
bit multiplier cell to build larger iterative arrays.
The part performs the function defined as

Ootec'

H

H

Sub 2X

Invert

~

~

~~~ ~~

:~~:~~

L

H

Sub Ze,o

Invert

H

L

L

L

H

L

H

Sub 1X

Inve"

L

H

L

I:

H

L

H

Sub 1X

Invert

H

H

L

L

L

H

H

Sub 2X

Inve"

F = XV + K, where K is an input field used
to add partial products in an array or to add
a constant to the least significant part of the
array product. The algorithm used is a modified
Booth's algorithm or multiplier coding technique. The device consists of a shift network

~

~

~

~

:

~

~ ~::;~

~:::::

:~d2 a~~~:e:si~b~r:~~;r a:d::hi:~ ~~b!r:~7ee; ~~

H

H

H

L

L

L

H

Inve,'

input constant K. The Y inputs control multi-

.

I-:-L-t-L:--+""'L-+""L-+--:-L-t-:-L-I-:-L+S=-u""'b-=Z-er-o+--o=-;:-re-c-,---t

•

Add Ze,o

L-_-'-_ _'-_....l-_-'_ _-'--_-'-_-'-_ _ _-'-_ _ _ _ _..... plication as shown in the Truth Table.

X-l, XO, Xl, X2, X3
Y-l, YO, Yl
KO, K 1, K2, K3

Cn

p-

M
SO,Sl,S2,S3, S4,S5

C n +4

The most significant digit in a word carries
a negative weight allowing 2's complement
numbers of various lengths to be multiplied.
An M-bit by N-bit multiplication produces
an M + N bit product.
The P pol arity input allows multiplication
in either positive logic (P = high) or negative
logic (P =Iow) representation. Also, mode
control M inverts Cn when high and passes Cn
directly when left low.

Multiplicand Inputs
Mu Itipl ier Inputs
COnstant Inputs
Carry Input I
Polarity Control
Mode Control
Product Output
Carry Output

L SUFFIX

PD = 760 mW typ/pkg (No Load)
tpd = 50 ns typ (8 X 8 bit product)

CERAMIC PACKAGE
CASE 623

t +, t- = 3.5 ns typ (20% - 80%)

-30°C
Characteristic
Power Supply Drain Current
Input Current

Symbol

IE

+25 0 C

+85 0 C

Min Max Min Max Min Max

-

201

-

183

-

201

-

350

-

220

220

200

-

245

-

linH

Pins 8,9,11,14,15,16,20
Pins 17,18,19
Pins 5,6,7,10,13

!lAde
320
390

220
245

Switehing'Times
Pro~agati~n Delay

ns
tpd
1.0

5.3

1.0

1.8

8.4

1.8

C n to C n +4
C n to S; X to_C n +4
K or X to S; C n to S4,S5

2.5

11

K to C n +4

1.6

7.3

1.0

6.3

5.0

1.0

5.5

8.0 1.8 8.8
2.5 10.5 2.5 11.5

1.6 7.0 1.6 7.7
3.2 14.1 3_2 13-5 3_2 14.8

Y to S or'C n +4
Rise Time, Fall Time

Unit
mAde

t+,t-

(20% to 80%)

3-98

1_0

6_0

LO 6_6

os

MC10183
POSITIVE LOGIC DIAGRAM
r - - - - - - - - - - - - - - - - - - i : : ! r O 4 55

3 54

.---~~rt----------------_t~~----------o2

Cn +4

X3 6 0-_+-1-1

1 S3
K3 5

0--+++--------------+-------,-'

X2 7

/

23 52
K2 14
X1 13

22 51

K1 11
XO 10

X-1

8

21 SO

KO 9

'V-1

160------1

VO 15 0-------1

Vee

= Pin 24
VEE=Pin12

V1 17

o-+-H--------i

P 18

o-~r.------j

3-99

en

20 0---\-\

M

19 Q---H

MC10183
MC10183 APPLICATIONS INFORMATION

The MC10183 is a 4 X 2 bit multiplier that
uses a modified Booth's algorithm or multiplier
coding technique. The device generates the
function: S.= X • Y + K

The two most significant bits of the product
are used for sign detection and overflow for
a two's complement multiply. These outputs
are used only as the two most significant bits
of the accumulated product at each addition
level within a multiplier array.
Overflow can occur either as the result of
2 times the multiplicand, and/or.of an addition
or subtraction. To show all possible conditions
(including overflow). the most significant bit
(S5) must carry a negative binary weight.
To show this for a 4 X 2' bit multiply plus
constant, consider the following addition:

where
X = 4·bit multiplicand
Y = 2-bit multiplier
K = 4-bit constant
The addition of the constant allows the device
to be used in an iterative array of parts for
larger words. The algorithm for multiplication is:
Yi-1

Yi

Yi+1

0

0
0

0
0
0
0

0

•

0

0
0

0

Operation

X

add zero
add multiplicand
add multiplicand
add 2 times multiplicand
sub 2 times multiplicand
sub multiplicand
sub multiplicand
sub zero

S5

The device consists of three main sections;
a decoder, a shifter, and a high speed lookahead carry adder/subtractor.

sum

S4 '" S5, and overflow can be detected by
EXCLUSIVE-ORing S4 and S5.

USAGE RULES
The M C1 0183 can be used in larger arrays
to produce a two's complement product of
2 two's complement numbers. The following
rules apply:

YO (1 times multiplicand)

B = Y-1 Y OY 1 + Y-1YOY1
(2 times multiplicand)

C=

S4' S3 S2 S1 SO

shifter outputs
constant

If no overflow occurs S4 = S5, and S4 can
be used as a sign bit. Under overflow conditions

1. The decoder uses the Y inputs to generate the control signals for the shifter and
the adder/subtractor. Also, the polarity control
P is used to allow operation in either positive
or negative logic. Referring to the logic diagram,
the control signals are:

e

Xi Xo

The shift network produces 5 product bits
(maximum value of 2 times multiplicand) and
a 4-bit constant is added to the least signficant
end of the product. The K3 bit is repeated to
hold the proper binary weight. Because S5 has a
negative weight all possible combinations are
represented properly.

DEVICE OPERATION

A = Y -1

4 - X3 Xi

+ K3 • K3 K2 K 1 KO

1. For an M-bit by' N-bit multiplier, an
(M+N)-bit product is formed. The number of
MC10183's equals (M' N)/8. As an example, an
8 X 8 bit (Figure 1) array requires (8X8)/8 =
8 packages.

PY1 + Y-1 Y OY 1 + PY1(Y-1 + yO)
(add/subtract)

The P input is tied to a high logic level or
ground for positive logic operation.

2. The MC10183 can be used directly for
both positive logic and negative logic representations. The P input can be tied to ground or to
a high logic level for positive logic operation, or
left at a low logic level for negative logic
operation.

2. The shift network is a multiplexer that
ripples through number X (1 times multiplicand), shifts number X by one bit (2 times
multiplicand), or sets the output to zero. The
network is controlled by decoder functions A
and B wh ich are generated in accordance with
the multiply algorithm.
3. The adder/subtractor follows the shift
network which performs the actual multiplication. The adder/subtractor produces the sum
or difference of the newly formed partial
product and the accumulated partial product
(constant K). Subtr.action is accomplished
by inverting the sh if ted' product and doing a
two's complement addition. The carry in of the
least sign ificant bit must be a logic one du ring
subtraction.

3. The M mode control input is used to
invert Cn when placed at a high logic level or
ground, or passes Cn directly when left as a low
logic level. When Cn is driven from Cn +'4
of a preceding device, M control is left in
a low logic state. When en is the least significant
input carry bit for a level of addition with in an
array, en is tied to Y 1 of the same device, and
the M input is placed at a high logic level. Y 1
controls when subtraction occurs, and carry in
must be equal to a logic one during subtraction.

3-100

MC10183

Multiplicand
X4 X5 X6 X7 M5B

xo X, X2 X3

III

I

-

.--,....--

YO
Y,

~

Cn

·f~

YO

-

II I II

X_, Xo X,X2 X3KO K,K2 K3
Y_,
Yo

MC101B3

-

Cn +4

50 5, 52 53 54 5S

I I

Y'

I

II

x", Xo x, X2 X3 KO K,K2 K3
Y-,

I

Y,

Cn

£~

MC101B3

505, 52 S3 54 5S

LLL

L

l....-

L..-

I

-

,--

-

X-,
Y-,
YO

I--

MC101B3

Cn

f~

r

I

X_, Xo x, X2X3 KOK, K2 K3
Y-1

OX, X2 X3KO K, K2 K3

Y,

Yo
Y,

Cn +4

,....--

I I

Y2

I

MC101B3

LLL

I

-

'---

I

-

I

I

_ .!'-'
y-, Xo XfX2
. X3 KO K,K2 K3
-YO
- , - Y,

-

Cn

MC10183

xc, Xo X'X2 X3 KO K,K2 K3
Y-1

Y4
Y5

Yo
Y,

..... -

Cn +4

Cn

MC101B3

Cn +4

_M

_M

r

II

505, S2 53 54 5s

p

~

50 5, 52 53 54 5S

I....-

Multipli er

Cn +4

Cn

I£~

50 5 , 525354 5S

Y3

Cn +4 ~

I I

P

-

So 5, 525354 5S

LL

L..-

'-'---

-

I
X_, XOX'X2X3 KOK, K2 K3
Y-,

t--

L-

MC10183

Cn

~ Y,

(;0+4

-

-M

r

Y6
Y7
zo Z, Z2 Z3 Z425

P

X-, XOX, X2X3 KO K,K2 K3

I - - Y-,

r- I-- Yo

YO
Y,

1-1--

IJ

50 5 ,52 53 54 55

I I
I I

Cn
P

I

2L~~819

Product

FIGURE 1 - 8-BIT X 8-BIT 2', COMPLEMENT MULTIPLIER

3-101

MC10183

Cn +4

M
50 5, 52 S3 54 5s

,t JJ
Zl1

2,3

215

~

..

MC10183
8

x

The S4 and S5 outputs are used only at the
most significant part of the array. These two
sum outputs only have meaning as the two
most significant bits of a two's complement
number.

4 BIT EXAMPLE

Figure 2 shows 4 MC10,183's in an 8 X 4 bit
array. A 12-bit two's complement product is
produced from a 4-bit multiplier and an 8-bit
multiplicand. The array is used for positive
logic represe~tation, and all P inputs are tied
to ground. At the first level of multiplication,
the X_l and Y -1 inputs are left open (logic
"0") because the initial condition is treated as
an add operation. The K inputs are used to add
the accumulated partial product at each level
of the array. If the initial partial product is
zero, the least significant K inputs are left at
a zero logic state (CONSTANT inputs in the
figure). However, these inputs can also be used
to add a constant to the least sign ificant end
of the product.

•

OTHER ARRAYS
The normal parallelogram structure consists
of several stages, each multiplying two bits of
multiplier times the multiplicand and adds the
partial product. In larger arrays, faster configurations can be made by moving some
multiplier blocks while maintaining the relative
weight of each partial product. The typical
times possible for various N-bit X N-bit arrays
are:

When the MC10183 is expanded to longer
numbers, the carry out (Cn +4) of a device
must be rippled to the carry in (Cn ) of the next
most significant device at the same level of
mUltiplication. The least significant device must
have the carry input equal to zero for an add
and equal to one for a subtraction. In observing

S5 S4 S3

S2

S, So

Cn

11

n

Cn+4

f

Y,

S5 S4 S3 S2 S,

So

I
K3 K2 K, Ko

I

S5 S4 S3 S2 S, So

-I 1 1 1 1 I

Multiplier

X3 X2 X, Xo X_I

Y.,

Y,

Cn

I

I

K3 K2 K, KO X3 X2 X, Xo X_I

1-0

YO

MC10183

...--Ir-J

Yo

18
32

.1.:1
Y-,

1-0

..-J~~J

MC10183

---8

K3 K2 Kl KO X3 X2 Xl XOX-l

YO
Yl

43
67
90

Package
Count

-Xs x6 x5 X4 x3 X2 Xl Xo

I

MC10183

8
12
16

=0

K3 K2 Kl KO X3 X2 Xl Xo X-l

Y-l

Total
Multiply
Time (ns)

The times do not include wiring delays.
Because of the versatility of the MC10183,
many other types of arrays can also be built.
Faster arrays using additional adders, pipeline
techniques, one's complement and magnitude
multipliers, and truncated product multipliers
can all be built.
Multiplicand

the multiplication algorithm Yi+l is always'
equal to 1 for a subtraction, and the carry input
can be tied to Y l ' However, the M mode input
must be tied to ground for this device to invert
the carry input (C n ) because the input requires
a complemented signal.
CONSTANT INPUTS

Number
of
Bits

Y-l

r-r--

Cn

~'n+4

S5

Product

YO

MC10183

Y,
S4 S3 S2 S,

I

I

I

So

I

Cn

Z, Zo

\

FIGURE 2 - 8-BIT BY 4-BIT 2'5 COMPLEMENT MULTIPLIER

3-102

MC10186/MC10586
HEX 0 MASTER-SLAVE
FLIP-FLOP WITH RESET

-----'"I

2(6)00

01 (10)6 -/-t--""""

3(7)01

02(11)7---1H--"""

4(8)02

00(9)5

The
MC10186/MC10586
contains
six
high-speed, master slave type "0" flip-flops.
Clocking is common to all six flip·flops. Data is
entered into the master when the clock is low.
Master to slave data transfer takes place on the
positive-going Clock transition. Thus, outputs
may change only on a positive·going Clock
transition. A change in the information present
at the data (D) input will not affect the output
information any other time due to' the master·
slave construction of this device. A common
Reset is included in this circuit. Reset only
functions when clock is low.

CLOCKED TRUTH TABLE

R

C

L

L

L
L
03(14)10---1-+---1

13(1)03

H

H •
H •
L

 ' Don't Care

0

'"

On+1

VCC; Pin 16(4)

On

VEE; Pin 8 (12)

L

L

H

H

'"

L

Po ; 460 mW typ/pkg
(No Load)
tpd = 3.5 ns typ
fTog

=

150 MHz typ

• A clock H is a clock transition
from a low to a high state.
04(15)11-+-+-111

14(2)04

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10186 only

L SUFFIX
05(16)12 ---1H--"""

15(3)05

CERAMIC PACKAGE
CASE 620

Clock( 13)9

F SUFFIX
-..:;"""''''''''''''' CERAMIC PACKAGE'
CASE 650
MC10586 only

Reset(5)1----.....- - - - - '

Number. at end. of terminal. danote pin number. for Land P package •.
Number. in parenthesis denote pin number. for F package.

3-103

•

MC10186/MC10586

ELECTRICAL CHARACTE RISTICS
-55°C
Characteristic
Power Supply Drain Current
Input Current
Pins 5, 6, 7, 10, 11, 12
Pin 9
Pin 1
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

•

Setup Time
Hold Time
Toggle Frequency

-30°C

+25 O C

+85 0 C

+125 0 C

Symbol Min Max Min Max Min Max Min Max Min Max
IE
linH

-

121

-

121

-

110

-

121

-

121

-

375
525
975

-

350
495
920

-

220
310
575

-

220
310
575

-

220
310
575

Unit
mAde
MAde

-

-

-

ns
tpd

1.6 4.9

1.6 4.6

1.6 4.5

1.6 5.0

1.6 5.3

t+, t-

1.0 4.3

1.0 4.1

'1.1

4.0

1.1

4.4

1.0 4.7

ns

tset

2.5

-

2.5

-

2.5

-

2.5

-

2.5

-

thold

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

fTog

125

-

125

-

125

-

125

-

125

-

MHz

, -55°C and + 125°C test values apply to MC105xx devices only.

3-104

ns

MC10188
HEX BUFFER WITH ENABLE

ADVANCE INFORMATION

The MC1 0188 provides a high speed Hex Buffer
with a common Enable input. When Enable is
in the high state, all outputs are in the low state.
When Enable is in the low state, the outputs
take the same state as the inputs.

o

9

3

~

+-__

6 ___

~

5 -_ _+-__""L---",....----2

,....._ _ _ _ 4

TRUTH TABLE

7 ---~----L_~

Inputs

,....--_ _ 13

10

-----t----""L----'

Output

VCC1 = Pin 1

A

B

0

VCC2 = Pin 16

L

L

L

VEE=Pin8

L

H

H

H
H

L
H

L
L

14 .

11

1"""""_ _ _ _

--

15

12 - - - - - - - - - " " 1
Po = 180 mW typ/pkg (No Load)
tpd = 2.0 ns typ (B-O)

.L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

= 2.5 ns typ (A-O)

+2S o C

-30 oC
Characteristic
Power Supply Drain Current
Input Current
Pins 5, 6;7,10,11,12
Pin 9
Switching Times
Propagation Delay
Data (B)
Enable (A)
Rise Time, Fall Time
(20% to 80%)

+8S o C

Symbol

Min

Max

Min

Typ

Max

Min

Max

Unit

IE

-

46

-

34

42

-

46

mAdc

-

425
460

-

-

265
290

-

265
290

/-LAdc

linH
-

ns
tpd

t+,t-

-

-

-

-

-

-

2.0
2.5

-

-

-

-

-

2.0

-

-

-

This is advance information and specifications are subject to change without notiCe.

3-105

ns

•

MC10189
HEX INVERTER WITH ENABLE

9

A

5

B

)oO_ _---.:O~ 2

x,-.~---

6----+--~

•

7

The MC10189 provides a high-speed Hex
Inverter with.a common Enable input. The hex
inverting function is provided when Enable is in
the low state. When Enable is in the high state
all outputs are low. Each input is connected
to VEE through a 50 kD resistor which
eliminates the need to tie unused inputs low.
Typical propagation times from inputs to
outputs are 2.0 ns and from Enable to outputs
are 2.5 ns.

----4----~~-'

3

-:0-----4

-

P SUFFIX
PLASTIC PACKAGE
CASE 648
11

L SUFFIX
CERAMIC PA'CKAGE
CASE 620

----I----"'-L~ - : 0 - - - - - 14

TRUTH TABLE
Inputs

VCC1 = Pin 1

Output

A

B

Q

L

L

H

L

H

L

Po = 200 mW typ/pkg (No Load)

H

L

L

tpd = 2.0 ns typ (B-O)

H

H

L

VCC2 = Pin 16
VEE=Pin8

12 _ _ _ _ _ _ _~./ X~--- 15

= 2.5 ns typ (A-O)

-30°C

+25 0 C

+85 0 C

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

Power Supply Drain Current

IE

-

44

-

40

-

44

mAdc

Pins 5, 6, 7,10,11,12

-

425

-

265

-

265

Pin 9

-

890

-

555

-

555

I nput Current

linH

Switching Times

ns

Propagation Delay

tpd

Data (81

1.0

3.3

1.0

2.9

1.0

3.3

Enable (AI

1.1

3.9

1.1

3.5

1.1

3.9

1.1

3.7

1.1

3.3

1.1

3.7

Rise Time, Fall Time

t+,t-

(20% to 80%1

3-106

ns

MC1 0190/MC1 0590
QUAD MST -TO-MECL 10,000
TRANSLATOR

The MC1 0190/MC1 0590 is a quad translator
for interfacing from IBM MST·type logic signals
to standard M EC L 10,000 logic levels. This
circuit features differential inputs for high noise
environments or may be used with single

(8)4~ .....

(9)5~2(6)

VCC1 = Pin 1 (5)
VCC2

(11) 7 = : t > - (10) 6'

3(7)

16 (4)

VSS= Pin 9 (13) Translator ended linesbytieingoneof the inputs to ground

(14)10~ __

(15)

= Pin

VEE = Pin 8 (12)
VCC = Pin 9 (13) Receiver

11~14

(2)

(1)13~ .....
(16) 12~15 (3)
Po

=

245 mW typ/pkg (No Load)

tpd = 2.5 ns typ
t+, t-

= 2.0

ns typ (20% to 80%)

(translator), or V BB ~ 1.29 V (receiver). Since
the device is designed to accept signals centered
arou nd grou nd, it is a usefu I interface element
for many communication systems. When pin 9
is connected to VCC (Gnd) the circuit becomes
a line receiver for MECL signals. The outputs
go to a low level whenever the inputs are left
floating.

.SUFFIX d

V1()(If ~L~S~;FIX

PLASTIC PACKAGE
CASE 648
MC10190 only

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10590 only

CERAMIC PACKAGE
CASE 620

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2SoC
VCCl

= VCC2 =

+2.0 Vdc

V out

PROPAGATION DELAY

,,,. ±1t,·"
-

VIH

1.16
--1

r--

V IL

I

+2.0 V (Translator)

Ves = +0.71 V (Receiver)

VSS"'" +3.25 V (Translator

Vee =

+2.0 V (Receiver)

5()'ohm resistor

e--.j........."l/

h

L 9o---J

50-ohm termination to ground 10
cated In each scope channel Input

All mput and output cables to the

~~~~~a~r:a~~~al ~~~:tl~~~:h5~~~~
be < 114 inch from TP m to Input
pin and TP out to output pin.

V out

I

-S - '

I-=

O 1

V (T.ranslator)

= + 1.6

V (Translator).

VIL = +0.31 V (Receiver)

Unused outputs

Vee::

= +2.4

, - - - - - - - - , . ' - - ' - - - - V I H = +1.11 V (Receiver)

V out

~F

----{

-3.2 Vdc

VEE
"50 ohm. MC10Sxx only

NOTE: All power supply and logic levels are shown shifted 2 volts positive.

3-107

•

I

ELECTRICAL CHARACTERISTICS

s:

n
....

TEST VOL TAGE VALUES
@Test
Temperature

(Volts)
VIHmax I VILmin I VIHAmin IVILAmax I VIHM*

I VILM*

I VIHH*

I VILH*

I

VIHL*

I VILL*

I

VSS*

I

VEE

MC10190
-30°C

-5.2

+25 0 C

-5.2

+85 0 C

-5.2
MC10590

-55°C

-0.880

-1.920

-1.255

-1.510

+0.344

-0.538

+0.186

-0.850

-1.486

-2.53

+1.25

-5.2

-0.780

-1.850

-1.105

-1.475

+0.440

-0.490

+0.186

-0.850

-1.486

-2.53

+1.25

-5.2

+125 0 C

-0.630

-1.820

-1.000

-1.400

+0.620

-0.430

+0.186

-0.850

-1.486

-2.53

+1.25

-52.

_30°C

-55°C

Cfl
a
~

00

+85 0 C

+25 O C

+125 0 C

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Conditions

Power Supply Drain

IE

-

57

-

57

-

52

-

57

-

57

mAde

ICC

-

27

-

27

-

27

-

27

27

mAde

linH

-

80

-

70

-

45

-

45

-

Vin ~ VIH max (Pins 4, 6,10,12),
VIL min (Pins5, 7,11,13).

45

!LAde

Current

Vin ~ VIH max to P.U.T., VIL min
to the other input of that gate.

Test one input at a time.
Reverse Lea kage

ICBO

-

1.5

-

1.5

-

1.0

-

1.0

-

1.0

!LAde

Current

Vin = VEE to P.U.T., one input

at a time.

Output Logic Levels
(Translator)

Common Mode

Translator (Pin 9

Vdel: Vin
Vde

VOH

-

-

-1.080 -0.880
VOL

-

-

-1.920 -1.655

-1.060 -0.890 -0.960 -0.810 -0.890 -0.700
-0.930 -0.780
-0.825 -0.630
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615
-.1.850 -1.620
-1.820 -1.545

Switching Times
Propagation

the gate under test and V I HM to

tpd

1.0

4.0

1.0

3.9

1.0

3.7

1.0

4.1

1.0

4.3

t+, t-

1.1

4.6

1.1

4.5

1.5

4.3

1.1

4.7

1.1

5.0

Vde

Receiver (Pin 9 = -'J
= Ground):
Vin=VIHH or VIHL to one input
of each gate under test and V I LH
or VILL, respectively, to the other

input of that gate.
ns

See switching times test circuit
and waveforms.

ns

20% to 80%

Delay
Rise Time,
Fall Time

VSS +1.25
VILM to one input of

cc

(Receiver)

MC10190
MC10590

~

the other input of that gate.

Rejection Test
MClO190
MCl0590

-....s:
o

("')

o

U'1

+25 0 C

Input Current

o
....
<0

-

*Vss:= IBM SupplyVoltage. Unless otherwise specified, Pin 9 == VSS == +1.25 Vdc.
VIHM =: Input logic "1" for IBM levels.
VILM"" Input logic "0" for IBM levels.
VIHH == Input logic "1" level shifted positive for common mode rejection tests.
VILH == Input logic "0" level shifted positive for common mode rejection tests.
VIHL == Input logic "1" level shifted negative for common node rejection tests.
YILL = Input logic "0" level shifted negative for common mode rejection tests.

_550C and +125 0 C test values apply to MC105xx devices only.

<0

o

MC10191/MC10591
HEX MEeL 10,000 TO
MST TRANSLATOR

The MC10191/MC10591 is a hex MECL
10,000 to IBM MST type logic translator. A
common enable (active low) is provided for
gating. Open em itter outputs are provided to
permit direct transmission line driving.
The MC10191/MC10591 is useful for interfacing to both III!ST-il and MST-IV systems.

(11 )7
2(6)
E(13)9
(10)6
3(7)

(9)5

4(8)
V CCl = Pin 1(5) = + 1.25 Vdc

(14)10
15(3)
Data
L
L
H
H

(15) 11
14(2)
(16)12

V CC2
VEE

Enable Output
L
H
L
H

L
L
H
L

=

Pin 16 (4)
8(12)

= Pin

=

Gnd

= -5.2

Vdc

PD = 170 mW typ/pkg (No Load)
tpd = 2.2 ns typ (Data to Output)

= 3.3

13(1 )

ns typ (Enable to Output)

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MCl 01 91 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10591 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Current

Max

Min

Max

Min

Max

Min

Max

IE

-

39
23

-

39
23

-

35
23

-

39
23

-

415
450

-

390
425
-

-

245
265

Pin9
linL
{..ogic "1" Output Voltage

VOH

Logic "0" Output Voltage

VOL

Logic "1" Threshold Voltage

VOHA

Logic "0" Threshold Voltage

VOLA

Rise Time, Fall Time

-

+ 125°C
Min

-.

Max

Unit
mAde

-

39
23

-

245
265

mAde
!lAde

'inH

Pins 5,6,7,10,11,12

Switching Times
Propagation Delay
Data
Enable

+850 e

Min

ICC
Input Current

+25 0 e

-30°C

Symbol

-

245
265
-

0.5
0.5
0.5
0.3
0.3
+0.111 +0.344 +0.156 +0.374 +0.255 +0.440 +0.327 +0.548 +0.375 +0.620
-0.538 -0.338 -0.523 -0.323 -0.490 -0.290 -0.454 -0.254 -0.430 -0.230
+0.091
+0.136
+0.235
+0.307
+0.355
-0.318
-0.303
-0.270
-0.234
-0.210
~

!lAde
Vde
Vde
Vde
Vde

ns
tpd

t+,t-

1.0
1.0
1.1

3.7
4.9
4.6

1.0
1.0
1.1

3.6
4.7
4.5

(20% to 80%1

-550 C and + 125 0 C test values apply to MC105xx devices only.

3-109

1.0
1.0
1.1

3.4
4.5
4.3

1.0
1.0
1.1

3.7
5.0
4.7

1.0
1.0
1.1

4.0
5.3
5.0

ns

•

MC10191/MC10591

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2SoC

VCC1 ~ +1.25 Vdc

""!D'' '
,...------,

Coax

All input and output cables to the

V out

scope are equal lengths of 50-ohm
coax is! cable, Wire length should
be < 1/4 inch from TPin to input
pin and TPout to output pin.

Coax

PROPAQATION OELAY

,------.,.t--t---- VI H ~ -0.890 V
41

Input

•

V IL

Pulse Generator

845
Input Pulse

t+ "" "t-

= 2.0 ± 0.2 ns

(20to 80%)

-5.2 Vdc

V out

V out

VEE

~

-5.2 Vdc

50-ohm termination to ground lo-

cated in each scope channel input.

3-110

~

-1.690 V

MC1 0194/MC1 0594
DUAL SIMULTANEOUS
BUS TRANSCEIVER

Po

~

The MC10194/MC10594 is a dual line
driver/receiver which is capable of transmitting
and receiving full duplex digital signals on a
high speed bus line. Because of the current

405 mW typ/pkg (No Load)

tpd- 2.5

"I typ

VCCI - Pin 1
VCC2 - Pin 16
VEE -Pln8

source line driver, two independent messages
Din lA

3 - - - - \ : -.......

Din 2A

4

may be transmitted on one line at the same
~~----7

----L_"

2

15

0in2B

14----\-.......

Din lB

13----{_./

~~----11

BusA

D out A

CoutS

Bus8

time.
The MC10194/MC10594 is designed to
work with a wide range of line impedances by
connecting a resistor equal to one half the line
impedance between the RE1 and RE2 inputs
and VEE. Each driver in the circuit will drive
lines down to 75 ohms or the two drivers may
be operated in parallel for lines down to 37
oh ms. The data in puts and data outputs are
standard MECL 10,000 logic levels.

DC TEST CONFIGURATION
-5.2

TRUTH TABLE

Inputs
Djn 1 Djn 2

Outputs

Bus

Dout

L

L

VSuso

H

H

L

VSusH

H

L

H

V SusH

H

H

H

VSusH

H

L

L

VSusH

L

H

L

VBusL

L

L

H

VSusL

L

H

H

vSusL

L

Gnd

37.5

-

37.5

RE

ICS

2

>-<>-.....- - - - 0 Dout
50
Note:

ICS is used to repr~sent a second
driver on the Bus line.

-2.0

DC LOGIC LEVEL DESCRIPTION
The bus terminal (pin 7 or 11) can be at any
one of three possible levels VBusO, VBusH, or
VBusL depending upon the combination of
inputs applied. The MECL inputs (pins 3 and 4
or 13 and 14) cause the bus terminal to switch

VBu~O
VSusOA

OV
-0.030 V

between two levels, VBusO and VBusH when
the external current source (ICS) is off, and
VBusH and VBusL when the external current
source is on. The bus output threshold voltage
levels caused by applying an input thrE!shold
voltage VILA or VIHA at a data input are also
translated depending upon the state of ICS'
These threshold levels are VBusOA and
VBusHA+ respectively when ICS is off, and
VBusHA- and VBusLA respectively when ICS
is on. These relative voltage levels are shown in
the figure on the right.

3-111

VSusHA+

-0.750 V

VSusH

-0.870 V

VSusHA-

-0.990 V

VSusLA

-1.598 V

VSusL

-1.718 V

•

MC10194/MC10594

F SUFFIX
CERAMIC ~ACKAGE
CASE 650
MC10594 Only

P SUFFIX

L SUFFIX

PLASTIC PACKAGE
CASE 648
MC10194 Only

CERAMIC PACKAGE
CASE 620

TEST VOLTAGE/CURRENT VALUES
(mAde)

'@1"est

Temperature

MC10194

ICSl
-21.1
-22.6
-24.2
-21.1
-22.6
-24.2

-30·C
+25 DC
+85 0 C

MC1D594

-55
±25
+125

ICSOA
6.35
6.80
7.27
6.35
6.80
7.27

(Volts)

ICS1A
14.50
15.27
16.35
14.50
15.27
16.35

VCl
-1.508
-1.618
-1.738
-1.458
-1.618
-1.818

VCH
0
0
0
0
0
0

ELECTRICAL CHARACTERISTICS
-5SoC

•

Characteristic

Symbol

Power Supply Drain Current

IE

Min

Max
107

_30 D e

Min

Max
107

+25 o C
Min

Max
97

-+8SoC

Min

Max
107

+12SoC
Min

Max
107

Unit
mAde

Conditions

Inpulsopen. See DC Test
Configuration and Logic
Level Description

Input Current
Data Inputs

J.tAdc

linH

Bus Terminals

Input Leakage Current

565
45

525
40

330
25

330
25

330
25

35

32

20

20

20

VIHMAX to Data Inputs.
VCH to Bus termInals,
Data Inputs open.

IlAdc

linL

Bus Terminals

Vel to Bus terminals,
Data inputs open.

Bus Driver Zero

Vauso

-10

+10

-10

+10

-10

+10

-10

+10

-10

+10

mVdc

Voltage Level

Bus Drive~ High
Voltage Level

VausH

-0.890 -0.690 -0.915 -0.715 -0.970 -0.770 -1.030 -0.830 -1.070 -0.870

Bus Driver Low
VOltage Level

VBusL

-1.658 -1.458 -1.708 -1.508 -1.818 -1.618 -1.938 -1.738 -2.018 -1.818

Bus Driver Zero Threshold
Voltage LENel
Bus Driver High Threshold
Voltage Level

But Driver Low Threshold
Voltage Level
Switching Times
Propagation Delay
Data to Bus
Bus to Data Out
Rise Time, Fall Time
Data Outputs

Bus Outputs

-30

-30

-30

-30

-30

Vdc

ICS off, VIHMAX to
Data Inputs. Or ICS on,
Data mputs open or VIL,

Vdc

ICS on, VIHMAX to
Data Inputs,

mVdc

ICS off, VILAMAX to
Data mputs (one at a
time).

V8u,HA.,l1 -0.910 -0.670 -0.935 -0.695 -0.990 -0.750 -1.050 -0.810 -1.090 -0.850

Vdc

ICS off, VIHAMIN to
Data inputs (one at a
time),

vBusHA.fi: -0.910 -0.670 -0.935 -0.695 -0.990 -0.750 -1.050 -0.810 -1.090 -0.850

Vdc

ICS on, VILAMAX to
Data inputs (one at a
time).

Vdc

ICS on, VIHA MIN to
Data inputs (one at a
time).

VSusOA

-1.488

-1.438

VSutLA

-1.598

-1.718

-1.798

tpd

1.0
1.0

3.2
4.6

1.0
1.0

3.1
4.5

1.0
1.0

2.9
4.3

1.0
1.0

3.2
4.7

1.0
1.0

3.4
5.0

1.0

4.5

1.1

4.4

1.1

4.2

1.1

4.6

1.0

4.9

1.0

.3.6

1.1

3.5

1.1

3.3

1.1

3.6

1.0

3.9

t+, t-

50% 'to 50%. See
Switch ing Time Test
Circuit and Waveforms.
20% to 80%

CD VSusHA+ denotes ~he upper output threshold level with'VIHAmin applied and the external current source, ICS off.
(]) VSusHA- denotes the lower output threshold level with VILAmax applIed and the external current source, ICS on.

Definitions
Vel ='
VCH ='
ICS1 =
ICS1A'"
ICSOA'"

ICS off, Data inputs
openorVIL"

Low bias voltage for testmg bus driver mput loading
High bias voltage for testmg busdrNer input loading
External current source input to the bus driver
Upper threshold level of external current source input to the bus driver
Lower threshold level of external current source mput to the bus driver

3-112 .

MC10194/MC10594

SWITCHING TIME TEST CI RCUIT AND WAVEfORMS

@

25°C

VCCI = vCC2 - +2.0
Scope

GenA

Coax

Din 1A

3

Din 2A

4

":'~ _t~~': ~~"

G.-B

Coax

50

VEE = -3.2 Vdc
12.5
7

+4.0 V

BUIA

>';---"=-ic=::r-o Scope

•

15 D out B

Don 2B

14 - - - - ' - - . . . "

Din 1 B

1 3 --~,----.L....-'"

Lm

f-<.....- - - t - l l

-r~-,--.'---1.I-,-"'3"'7~"'5-----0

Bus B

VEE

= -3.2 Vdc

50-ohm termination to ground located in each scope channel input.

All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input

VEE - -3.2 Vdl..

pin and TP out to output pin.

+2.00 V

Bus Input

+1.13 V ---t-''---~--...t

°aut
MECL Output

Data to Bus

Bus to Data

NOTE: All ppwer supply and logic levels are shown shifted 2 volts positive.

3-113

MC10194/MC10594

APPLICATION INFORMATION

The MC10194/MC10594 Dual Simultaneous
Bus Driver/Receiver is designed for high speed
data transfer over multi-port bus lines. Full
duplex data transmission can improve system
performance by increasing message density and
overcoming the requirement to wait two line
propagation delay times between messages.
, Figure 1 illustrates two types of system
operation. One mode of o~ration is with two
drivers on the bus line at 'locations X and Z.
Any input to Din X is seen at D out Z one line
propagation delay later. Similarly, any input to
Din Z is transmitted to D out X. Each driver
inhibits the data being sent on the bus from
appearing at its receiver output, so full duplex
signal transmission is possible. In addition, current source drivers allow two messages to pass
on the same line so there are no timing restrictions between sending messages.
A second type of system operation is with a
multi-terminal bus as illustrated in Figure 1 by
pOints X, Y, and 2. In this mode, anyone
terminal can transmit data and all other points
will receive the message. Alternately, any two
terminals can simultaneously exchange data,
but the other receivers will not see valid data.
The MC10194 uses current source line driving and is designed to operate with a load to
VCC (normally ground). This load is usually the
line termination resistors at each end of the line
as shown in Figure 2. In addition, to match the
driver to a given impedance line, an external
resistor equal to one-half the line termination
resistor value is connected between the RE out-

put and VEE. When the circuit is used with a
multi-terminal' bus, each driver must have the
resistor between RE and VEE, but the termination resistors are required only at each end of
the bus line.
Each MC10194 driver in a package is capable of driving 75-ohm lines. Higher impedance
lines may be used with no loss of performance
if the line is properly matched with RE. If it is
desirable to drive 50-ohm lines, both drivers in
a package should be operated in' parallel with
each having 50-ohm resistors at RE and the
driver outputs both connected to the 50-ohm
bus line.
To allow very high data rates, the rise and
fall times on the bus line are quite fast (typically 1.0 ns). With full duplex operation, it is
possible to get a crosstal k pu Ise of several
hundred mV at a receiver output A 10-20 pF
capacitor connected between each driver output and VEE will slow down the rise and fall
times, greatly reduce any crosswalk pulse, and
still give good system performance.
The adjustable current source drive feature
of the MC10194 makes this circuit a useful output driver for many appl ications. F or example,
it is possible to drive the 50-ohm to ground
load required by many interface systems. This
driver will sink the 14 to 18 mA required to
meet the AEC Committee specification for
Nuclear Instrument Modules. The MC10114
MECL Line Receiver makes a good interface
receiver for the MC10194 driver in these
applications.

FIGURE 1 - MC10194/MC10594 SYSTEM OPERATION

x

2

Y

D out

D out

,

D'"~

, D out

Data Bus Line

FIGURE: 2 - BUS LINE INTERFACE

1/220

1/220

Out

In

20

T

VCC VEE

In

1/220

Out

T
VEE

3-114

Bus LJne
Impedance

In

= 20

Out

T

Zo

VEE VCC

M C1 0195/MC1 0595
HEX INVERTER/BUFFER

TRUTH TABLE
Inputs

(13)9_A_ _~~

(9) 5

-=8-+_---'~--"

(10)6--+--"'-""L/

(11 )7.--+--~L/

(14) 1 O'--+--~L/

The MC10195/MC10595 has an enable
input which when placed low or left open
allows use as inverters. With the enable at a high
logic level the MC10195/MC10595 is a hex
buffer, useful for high fanout clock driving and
reducing stub lengths on long bus lines.

Output

A

B

Q

L
L
H
H

L
H
L
H

H
L
L
H

3(7)

11

4(8)

P SUFFIX
PLASTIC PACKAGE
CASE 648

13(1 )

L SUFFIX
CERAMIC PACKAGE
CASE 620

MC10195 Only

(15) 11 --+----+,L/

(16) 12 - - - - o . j - I

14(2)
VCC1 = Pin 1 (5)
VCC2= Pin 16(4)
VEE = Pin 8(12)
15(3)
F SUFFIX
CERAMIC PACKAGE
CASE 650

P D = 200 mW typ/pkg (No Load)
tpd = 2.8 ns typ (8-Q)
= 3.8 ns typ (A-Q)

MC10595 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Current
Input Current

Symbol
IE

-30°C

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

-

54

-

54

-

49

-

54

-

54

-

450

-

425

-

265

265

-

290

-

265

460

-

/-lAde

linH

Pins 5,6,7,10,11,12
Pin 9

495

290

290

Switching Times
Propagation Delay

ns
.tpd

Data (B)

1.0

4.3

1.1

4.2

1.1

4.0

1.1

4.4

1.0

4.7

Enable (A)

1.0

5.4

1.1

5.2

1.1

5.0

1.1

5.4

1.0

5.9

1.0

4.9

1.1

4.7

1.1

4.5

1.1

5.0

1.0

5.3

Rise Time, Fall Time

Unit
mAde

t+,t-

(20% to 80%)
·-55 0 C and +125 0 C test values apply to MC105xx devices only.

3-115

ns

•

MC1 0197IMC1 0597
HEX AND GATE

TRUTH TABLE

(13)9
(9)5

A
B

I

-

'I.
./

(11 )7

(14)10

2(6)

Inputs

P D = 200 mW typ/pkg (No Load)

~

(10)6

0

VCC1 = Pin 1 (5)
VCC2 = Pin 16(4)
VEE = Pin 8(12)

J

B

a

L
L
H
H

L
H
L
H

L
L
L
H

tpd = 2.8 ns typ (8 -0)

3(7)

= 3.8 ns typ (A-O)

I~

4(8)

~
J

13(1 )

J

Output

A

-P SUFFIX_

L SUFFIX

PLASTIC PACKAGE
CASE 648

~

CERAMIC PACKAGE
CASE 620

MC10197 only
-~

(15) 11

J

J

-~

(16)12

14(2)

~

.~

15(3)

F SUFFIX
- CERAMIC PACKAGE
CASE 650
MC10597 only
Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-55°C
Characteristic
Power Supply Drain Current
Input Current
Pins 5,6.7,10,11,12
Pin 9
Switching Times
Propagation Delay
Data (8)
Enable (A)
Rise Time, Fall Time
(20% to 80%) -

-30°C

+25 0 C

+85 0 C

+125 0 C

Symbol Min Max Min Max Min Max Min Max Min Max

IE
linH

-

54

-

54

-

49

-

54

--

450
495

-

425
460

-

265
290

-

265
290

-

54

Unit
mAdc
MAdc

-

-

-

-,.

-

265
290
ns

tpd

-t+,t-

1.0 4.3
1.0 5.4

1.1
1.1

4.2
5.3

1.1
1.1

4.0
5.0

1.1
1.1

4.4
5.5

1.0 4.7
1.0 5.9

1.0 4.9

1.1

4.7

1-.1

4.5

1.1

5.0

1.0 5.3

-55°C and + 125 0 C test values apply to MCl 05xx devices only.

3-116

ns

MC10198
MONOSTABLE MULTIVIBRATOR

VEE

69
RExt
5 - E Pos

7-

Q

r--3

External Pulse
Width Control

1 0 - ENeg
1 3 - Trigger
Input

6-2

1 5 - Hi-Speed
Input

VCC1 = Pin 1
VCC2 = Pin 16
VEE=Pin8

The MC10198 is a retriggerable monostable
multivibrator.
Two
enable
inputs permit
triggering on any com bination of positive or
negative edges as shown in the accompanying
table. The trigger input is buffered by Schm itt
triggers making it insensitive to input rise and
fall times.
The pulse width is controlled by an external
capacitor and resistor. The resistor sets a current
which is the linear discharge rate of the capacitor. Also, the pulse width can be controlled
by an external current source or voltage (see
applications information).
For high-speed response with minimum
delay, a hi-speed input is also provided. This
input bypasses the internal Schmitt triggers and
the' output responds with in 2 nanoseconds
typically.
Output logic and threshold levels are standard MECL 10,000.
Test conditions are per
Table 2. Each "Precondition" referred to in
Table 2 is per the sequence of Table 1.

TRUTH TABLE
INPUT

L
L
H
H

L
H
L
H

OUTPUT

Triggers on both positive & negative input slopes
Triggers on positive input slope
Triggers on negative input slope
Trigger is disabled

PD = 415 mW typ/pkg (No Load)
tpd = 4.0 ns typ Trigger I nput to Q
. 2.0 ns typ Hi-Speed Input to Q

L SUFFIX
CERAMIC PACKAGE
CASE 620

P SUFFIX
PLASTIC PACkAGE
CASE 648

Min Timing Pulse
Width
Max Timing Pulse
Width
Min Trigger
Pulse Width
Min Hi-Speed
Trigger Pulse Width
Enable Setup Time
Enable Hold Time

PWQmin

10 ns ty~

PWQmax

>10 ns tY1@

PWT

2.0 ns typ

PWHS

3.0 ns typ

tset
thold

1.0 ns typ
1.0 ns typ

10ns- !--;;;>10ns_
O(Gnd)

"
"C

2.

-1.0

2:'" -2.0

3.

E
"0

...>

I
I

-3.0

I

c:

c::

-4.0

-5.0

I
I

_Pinl_~

I

o

10

°r

n

II
20

30

t (ns)

3-118

Apply VIHmax to Pin 5 and
10.
b.) Apply V I Lmin to Pin 15.
c.) Ground Pin 4.
Att~10ns ,a.) OpenPin1.
b.) Apply -3.0 Vdc to Pin 4.
Hold these conditions for
~ 10 ns.
Return Pin 4 to Ground and perform test as
indicated in Table 2.

MC10198
TABLE 2 - CONDITIONS FOR TESTING OUTPUT LEVELS
(See Table 1 for Precondition Sequence)

~VILAmax
VILmin

Pl

P2

Pins 1, 16 =
Pins 6, B

Vee = Ground

= VEE = -5.2 Vdc

Outputs loaded 50

Test

P.U.T.

n

to -2.0 Vdc

Pin Conditions
13
10

5

15

Precondition

VOH
VOH

2
3

VIL'min

3
2

VILmin

Pl

Precondition

VOL
VOL

Pl

Precondition

VOHA
VOHA

2
3

VILA max
VIHA min

Precondition

VOHA
VOHA

2
3

VILmin

2
3

P2
P3

P3

Precondition

VOHA
VOHA
Precondition

VOHA

2

VIHmax

VOHA

3

VIHmax

VOHA,

2

VIHmax

VOHA

3

VIH max

VOHA

2

VIHAmin

VOHA

3

VI LA max

P2
P3

Precondition

Pl
Pl

Precondition

Pl
Pl

Precondition

VOLA
VOLA

3
2

VILA max
VIHAmin

Precondition

VOLA
VOLA

2
3

VILmin

3
2

P2
P3

VILmin

Precondition

VOLA
VOLA
Precondition

VOLA
VOLA

3
2

VIH max
VIH max

P2
P3

Preconditic..,

VOLA
VOLA

3
2

VIHAmir VIH max
VILAma

VIH max

Pl
Pl

Precondition

VOLA
VOLA

3
2

VIH max VIHAmin
VIH max VILA max

3-119

Pl
Pl

•

MC10198
. SWITCHING TIME WAVEFORMS

Trigger Input

Q

High-Speed
Trigger Input

•

Q

1-----pwQ----""
CIRCUIT OPERATION
includes RI nt). Any low leakage capacitor can
be used and RExt can vary from 0 to 16 k ohms.
Note that for capacitance less than 20 to 30 pF,
actual pulse width tends to be longer than values
calculated by the timing equation.

1. PULSE WIDTH TIMING-The pulse width
is determ ined by the external resistor and
capacitor. The MC10198 also has an internal
resistor (nominally 284 ohms) that can be used
in series with RExt. Pin 7, the external pulse
,width control, is a constant voltage node
(-3.60 V nominally). A resistance connected
in series from this node to VEE sets a constant
timing current IT' This current determines the
discharge rate of the capacitor:

2. TRIGGERING-The Epos and ENeg inputs
control the trigger input. The MC10198 can be
programmed to trigger on the, positive edge,
negative edge, or both. Also, the trigger input
can be totally disabled. The truth table is
shown on the first page of the data sheet.
The device is totally retriggerable. However,
as duty cycle approaches 100%, pulse width
jitter can occur d~e to the recovery time of
the circuit. Recovery time is basically dependent
on capacitance CExt. Figure 3 shows typical
recovery time versus capacitance at IT = 5 mAo

b.V
IT = CExt b.T
where
b.T = pulse width
b. V = 1.9 V change in capacitor voltage
Then:
b.T = CExt 1,9 V
IT

FIGURE 1-

If RExt + R Int are in seri~s to VEE:

94

IT = [(-3.60 V) - (-5.2 V)] .;. [RExt + 284 fl.]

±CExt

IT = 1.6 V/(RExt + 284)
MC10198

The timing equation becomes:

7

C,T =. [(CExt)(1.9V)] .;- [1.6 V/(RExt + 284)]
Rlnt

b.T = CExt(RExt + 284) 1. Hi

2840

where b. T = Sec
6

RExt= Ohms
CExt = Farads

REX"t

Figure

2. shows

typical curves for pulse

VEE = -5.2 V

width versus CExt and RExt (total resistance

3-120

-3.60 V External
Pulse Width Control

MC10198
FIGURE 3 - RECOVERY TIME
versus CExt @ IT = 5 rnA

FIGURE 2 - TIMING PULSE WIDTH
versus CExt and RExt

10
IOkU
3kn

lOOns

soon
IOns

D1

RExt=O

NOTE: TOTAL RESISTANCE
;RExI+Rlnl

001'
10pF

IODpF

lOOOpf
CEKI- TIMING CAPACITANCE

,,,
IOpF

o.OlpF

IOOpF

3. HI-SPEED INPUT - This input is used for
stretching very narrow pulses with minimum
delay between the output pulse and the trigger
pUlse. The trigger input should be disabled
when using the high-speed input. The MC1 0198
triggers on the rising edge using this input, and
input pulse width should be narrow, typically
less than 10 nanoseconds.

3. For optimum pulse width stabilitY versus
temperature and power supply variation, a nom:
inal timing current of approximately 0.5 mA is
used. Figures 4 and 5 show typical voltage change
at Pin 7 for power supply and temperature variation. Figure 6 shows typical pulse width versus
temperature and power supply variation.

II

versus

SUPPLY VOLTAGE VEE @
IT = 0.5 rnA, TEMPERATURE = 25 0 C
-3.3

~~
,,~

2. The E inputs should not be tied to ground
to establish a high logic level. A resistor divider
or diode can be used to establ ish a -0.7 to
-0.9 voltage level.

O.II1F

FIGURE 4 - TYPICAL VOLTAGE AT PIN 7
(EXTERNAL PULSE WIDTH CONTROLI

USAGE RULES
1. Capacitor lead lengths should be kept very
short to minimize ringing due to fast recovery
rise times.

DD1~F

1000pF

CEX1- TIMING CAPACITANCE

~C

~~

/'

-3.5

/'"

<~

~~
w~

!;(-i
w

C

~~
"><,,
<",

-3.7

/

wc

V

>;:

'"

-4.1
-5.7

V

/'

/'

1-1-

~" -3.9
c_

4. Pulse' Width modulation can be attained
with the EXTERNAL P'ULSE WIDTH CONTROL. The timing current can be altered to
vary the pulse width. Two schemes are:

V

-5.5

-5. I
-5.3
VEE. SUPPLY VOLTAGE (VOLTS)

-4.7

-4.9

FIGURE 5 - TYPICAL VOLTAGE AT PIN 7
(EXTERNAL PULSE WIDTH CONTROLI

(a) The internal resistor is not used. A dependent current source is used to set the timing
current as shown in Figure 7. A graph of pulse
width versus timing current (CExt = 13 pF) is
shown in Figure 8.
-

versus

TEMPERATURE @
IT = 0.5 rnA, VEE = -5.20 VOLTS
-3. 5

(b) A control voltage can also be used to
vary the pulse width using an additional resistor
(Figure 9). The current (IT + IC) is set by the
voltage drop across R I nt + R Ext. The control
current IC modifies IT and alters the pulse
width.
Current IC should never force IT to
zero. RC tYPically 1 kO,

6

7

5. The MC1 0198 can be made non-retriggerable.
The Q output is fed back to disable the trigger
input during the triggered state (Figure 10). The
example shows a positive triggered configuration, a similar configuration can be made for
negative triggering.

B

-3.9
-30

-10

10

30

50

TEMPERATURE (C)

3-121

70

90

MC10198
FIGURE 7

FIGURE 6 - PULSE WIDTH versus
TEMPERATURE AND SUPPLY VOLTAGE
64
3

4

I.--' ~

2

r-r--

1
0

t::MC10198

177}

VEE = -4.68 V-'
-5.20 V-'
-5.72 V-'

9

f1

L-- ~

/

RT = 3.0 k!.1
CT= 13 pF IT, = 0.5, mA

8
7

56
-30

-10

10

30

50

70

90

TEMPERATURE (CI

FIGURE 8 - PULSE WIDTH

..

versus IT@ CExt = 13 pF
100 0

1":

'"
(\.,

0

l'\

I'"
10
001 rnA

01 rnA

"

lOrnA

'T -T1MING CURRENT

FIGURE 10

FIGURE 9

4

f

VEE

CExt

RExt

-=

, IT

6 ~

IC
7_
,A

-3.6
V

284

RC

E

Control
Voltage

-

Pas

Vcc

1
T4

CExt

Q/---

External Pulse
Width Control

-0.9 V_ ENeg

6
IT + IC ~

Trigger

~

Input

RExt

-

-5.2 V

3-122

Hi-Speed
Input

O/-- I--

MC10210/MC10610
HIGH-SPEED DUAL 3-INPUT
3-0UTPUT OR GATE

MC10211/MC10611
HIGH-SPEED DUAL 3-INPUT
3-0UTPUT NOR GATE

MC10210/MC10610

The

(9)5~ 2(6)

(10)6

(11) 7

MC1 021 0/MC1 061 0

MC10611

are

MC10110/MC10111.

3 (7)

speed

and

MC10211/

versions

of the

They are,pin·for·pin reo

placements for those devices. Three V CC pins
are provided and each one should be used.

4(8)

(13)9~ 12(16)

(14)10
(15)11

higher

VCC1 = 1 (5),15 (3)
VCC2 = 16 (4)
VEE = 8 (12)

13(1)

•

14(2)
Po

MC10211/MC10611

(9)5
(10)6
(11) 7

(13)9
(14) 10
(15) 11

~
~

=

160 mW tYP/pkg (No Load)

tpd = 1.5 ns typ (All Outputs Loaded)
t+, t- = 1.5 ns typ(20% to 80%)

2(6)

(All Outputs Loaded)

3(7)
4(8)
12(16)

L SUFFIX

13(1)

CERAMIC PACKAGE

14(2)

CASE 620

P SUFFIX

F SUFFIX

PLASTIC PACKAGE

CERAMIC PACKAGE

CASE 648

CASE 650

MC10210/MC10211

MC1 0610/MC1 0611
only

only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-30°C

-55°C
Characteristic
Power Supply Drain Current
Input Current
Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

Symbol

+25 0 C

+85 0 C

+125 0 C

Min Max Min Max Min Max Min Max Min Max

Unit

IE

-

42

-

42

-

38

-

42

-

42

mAde

linH

-

700

-

650

-

410

-

410

-

410

/LAde
ns

tpd
t+,t-

1.0 2.9

1.0 2.6

1.0 2.5

1.0

2.8

1.0 3.0

2.9

1.0 2.6

1.0 2.5

1.0 2.8

1.0 3.0

1.0

-55 0 C and +125 0 C test values apply to MC 1 06xx devices only.

3-123

ns

MC10212/MC10612
HIGH-SPEED DUAL 3-INPUT

3~OUTPUT ORINOR GATE

(9)5=ri=3

P D = 160 mW typ/pkg (No Load)
tpd = 1.5 ns typ (All Outputs Loaded)

4(8)

(10)6
(11) 7

.

m

t+, t- = 1.5 ns typ (20% to 80%)
(All Outputs Loaded)

2(6)

Three VCC pins are provided and each one
should be used.

.

•

'=ri=12(16)
(13)9
13(1)
(14)10
14(2)
(15) 11

VCC1 = 1 (5),15(3)
VCC2 = 16 (4)
VEE=8(12)

.-

-

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10212 only

~
'~~

~

L SUFFIX
CERAMIC PACKAGE
CASE 620

F SUFFIX
CERAMIC PACKAGE
CASE 650
MC10612 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-SSoC
Characterist ic
Power Supply Drain Current
Input Current

Symbol

_30°C

+2SoC

+8SoC

+12SoC

Min Max Min Max Min Max Min Max Min Max

-

IE

-

42

linH

-

700' -

-

38

-

42

-

42

mAde

650

-

410

-

410

-

410

/lAde
ns

Switching Times
Propagation Delay
Rise Time, Fall Time
(20% to 80%)

Unit

42

tpd
t+,t-

1.0 2.9 1.0 2.6 1.0 2.5
1.0 2.9 1.0 2.6 1.0 2.5

-55°C and +125 0 C test values apply to MC106xx devices only.

3-124

1.0 2.8 1.0 3.0
1.0 2.8 1.0 3.0

ns

MC10216/MC10616
HIGH-SPEED TRIPLE
LINE RECEIVER

The MC10216/MC10616 is a high speed
triple differential amplifier designed for use in
sensing differential signals over long lines. The
bias supply (V SS ) is made available at pin 11
'to make the device useful as a Schmitt trigger,
or in other appl ications where a stable reference
voltage is necessary.
Active
current
sources
provide
the
MC10216 with excellent common mode noise
rejection. If any amplifier in a package is not
used, one input of that amplilier must be can·
nected to VSS (pin 11) to prevent upsetting
the current source bias network.

(8)4~2(6)

(9)5~3(7)
(13) 9~6 (10)

(14)10~7

(11)

(16)12~14(2)

(1)13~15(3)
~11(15)
VSS

•

PD = 100 mW typ/pkg (No Load)
tpd = 1.8 ns typ (Single ended)
= 1.5 ns typ (Differential)

VCC1 = Pin 1 (5)
V CC2 = Pin 16 (4)
VEE = Pin 8(12)

•

F SUFFIX

P SUFFIX

L SUFFIX

PLASTIC PACKAGE
CASE 648
MC10216 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC1 0616 only

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

One input from each gate must be tied to VBB during testing.
-55 0 C
Characteristic
Power Supply

Drain Current

I nput Current

+250 C

+85 0 C

+125 0 C

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

IE

-

28

-

'27

25

28

mAdc

-

180

115

-

115

!LAdc

1.5

-

1.5

-

27

195

-

1.0

-

1.0

!LAdc

linH
ICBO

Reference Voltage

-30 o C

Symbol

V8B

115
1.0

-1.440 1.320 1.420 -1.280 -1.35C -1.23C -1.295 -1.15C -1.240 -1.120

Switching Times
Propagation Delay
Rise Time, Fall Time

Vdc
ns

tpd
t+,t

1.0

2.7

1.0

2.6

1.0

2.5

1.0

2.8

1.0

2.9

1.0

2.7

1.0

2.6

1.0

2.5

1.0

2.8

1.0

2.9

(20% to 80%)
-55 0 C and +12SoC test values apply to MC106xx devices only.

3-125

ns

MC10231/MC10631
HIGH:'SPEED DUAL TYPE D
MASTER-SLAVE FLIP-FLOP

51

01

(9) 5--------------,

(11) 7

---------I

The MC10231/MC10631 is a dual masterslave type 0 flip-flop. Asynchronous Set (S)
and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip-flop may be
clocked separately by holding the common
clock in the low state and using the enable
inputs for the clocking function. If the common clock is to be used to clock the flip-flop,
the Clock Enable inputs must be in the low
state. In this case, the enable inputs perform
the function of controlling the common clock.
The output states of the flip-flop change on
the positive transition of the clock. A change in
the information present at the data (0) input
will not affect the output information at any
other time due to master slave construction .

2 (6)

eEl ·(10) 6
3 (7)

Rl

(8) 4 - + - - - - - - - - - - - J

Cc (13) 9

R2

(1) 13 -+------------,

14(2)
eE2 (15) 11 - - - ' - - -___

•

15 (3)

02 (1411 0 --------~

R-S TRUTH TABLE

52 ( 1 6 ) 1 2 - - - - - - - - - '

P SUFFIX
PLASTIC PACKAGE
CASE 648
MC10231 only

~UC~RAMIC
"f{l0nfV

R

S

L
L

L
H

H

L

H

H

CLOCKED TRUTH TABLE

On+l
an
H
L
N.D.

rp

N.D. = Not Defined

C

D

L



°n+l
an

H*
H*

L
H

H

L

= Don't Care

C

= CE

+ Ceo

*A

clock H is a clock transition
from a low to a high state.

Po

=

270 mW typ/pkg (No Load)

fTog = 225 MHz typ

LSUFFIX

VCCI = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

CERAMIC PACKAGE,
CASE 650
MC10631 only

PACKAGE

CASE 620

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

-30°C

-55°C
Characteristic
Power Supply Drain Current
Input Current
Pins 6,1,10,11
Pin 9
Pins 4,5,12,13

Setup Time
Toggle Frequency

+1250C

72

-

72

-

65

-

72

-

72

-

375
495
700

-

350
460
650

-

220
290
410

-

220
290
410

-

220
290
410

Unit
mAdc
~Adc

-

'Hold Time·

+85 0 C

-

-

Rise Time, Fall Time
(20% to 80%)

+ 125 0 C

IE

+25 0 C

Min Max Min Max Min Max Min Max Min Max

linH

Switching Times
Propagation Delay
Clock
Set, Reset

-55 0 C and

Symbol

-

-

ns
tpd
1.3 3.7
1.0 3.7
t+,t-

1.5 3.4
1.1 3.4

1.0 3.4 0.9 3.3

tset

1.5

-

1.5

-

thDld

0.9

-

0.9

fTog

200

-

200

-

test values apply to MC 1 06xx devices only.

3-126

1.5 3.3 1.6 3.7
1.1 3.3 1.2 3.7

1.2 3.9
1.0 3.9

1.0 3.1

1.0 3.6

1.0 3.6

ns

-

1.5

-

1.5

-

0.75 -

0.9

-

0.9

-

ns

200

200

-

200

-

MHz

1.0

~

ns

MC1 0287/MC1 0687
HIGH-SPEED -

2 x 1 BIT ARRAY MULTIPLIER
BLOCK

The MC10287/MC10687 is a dual high speed iterative
multiplier, It is designed for use as an array multiplier
block, Each device is a modified full adder/subtractor that
forms a single-bit binary product at each operand input of
the adder, Internal carry lookahead is employed for high
speed operation,

An addition or subtraction is selected by mode controls
(MO, Ml), The mode controls are buffered such that they

can be grounded or taken to a standard high logic level to
accomplish subtraction, When left open or taken to a low
logic level, MO and M 1 cause addition,

POSITIVE LOGIC

co

9----1

aO

6

aO'

7

bO

4

bO'

5

MO

3----1

NEGATIVE LOGIC

co

50
Cl

81 11

aO

9
6

aO'

7

bO

4

bO'
MO

al

51

----I
50

Cl

5

3----1

11--'

-,
51

al'10-,"",-_"

al' 10
bl 13
15

bl'12
MI14-----1

MO(7)

3

C2

Po = 400 mW typ/pkg (No Load)

bl

13

V CC = Pin 16(4)

bl' 12

VEE = Pin 8(12)

Ml

15

14----1

MO

aO(10)

AO (!) BO (!) MO

so = AO (!) 60 (!) CO

aO'(II)
bOIS)
bO'(9)
CO(13)

9

NEGATIVE LOGIC

14

Cl = CO lAO (!) BO (!) MO) + AO IBO (!) MOl

Ml

M1(2)

a1( 15)

al'(14)...,-"'"1..._-'
b1(1)

Al (!)Bl(!)Ml

51 = Al (!) Bl (!) Cl

AliBI (!) Ml)

bl'(16)v-"",-_,/

C2

Numbers at ends of terminals denote pin numbers for Land P packages,
Numbers in parenthesis denote pin numbers for F package,

3-127

C2

•

•

MCl 0287/MCl 0687
FUNCTIONAL TRUTH TABLE
Ml~

Ml MO bl b" a1 al' bO bO' aD .0 CO 5051 C2

bl b" 81 81' bObO'aD .0 CO SO 51 C2

14 3 131211 10 4

5

6

7' 9

2

1 15

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H

H
H
L
L
H

H
H
L
L
H

H
L
H

H

H

L

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
L
L

H
H
H

L
L
L
H
H

L
L
L
H
H

H
L
L
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
H

H
H

L
L
L

L
L
L

L
L
H
H

H
H
H
H
H

H'
H
H·
H
H

H
L
L
L
L

H
L
L
L
L

L
H
H
H
H

L
H
H
H
H

L
H
H
H
H

L
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
H
H
H
L

H
H
H
H
L

L
L
L
L
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

L
L
L

L
L
L

L
L

L
L

H
H
H
H
H

H
H
L
L
L

L
L
H
H
H

L
L
H
H
H

H
H
H
H
H

L
L
L
L
L

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

H
H
H
H
H

L
L
L
L
L

13 12 11 10 4

5

6

7

9

2

1 15

L
L
L
L
L

H

L
L
L
L
H

L
L
L
L
H

H
H
L
L
H

H
H
L

H
L
H

L
H
H

H
H
H

L
H

0
1
2
3
4

H

L
L
H
L

H
L ,L
L L
L L
H H

L
H

L
H

L
H

L
L

H
L
L
H
H

L
H
L
H
L

H
H
L
H
L

H H
H H
L L
L L
H 'L

5
6
7
8
9

L
L
L
L
L

H
H

H
L
L
H
H

L·
H
L
H
L

L
L
H
L
H

H

H
L
H
L
H

L
H

L

L
L
H
H
L

L
H
H

H
H
L
L
L

L
L
L
L
L

10
11
12
13
14

L
L
L
L
L

L
H
H
L
L

L
H
H
L
L

L
H
L
H
L

L
H
L
L
H

H
L
H
H
H

L
H
H
H
H

15
16
17
18
19

L
L
L
L
H

H
H
L
L
H

H
H
L
L
H

H
L
H

L
H
H

H
H

I;i

L
H

L
H

L
L
L
H
H

H
H
H

H
H
H
L
L

H
L
L
H
H

L
H
L
H
L

L
L
H

L
L

H
L
L
H
H

L
L
H
H
H

L L
L 'L
H H
H H
H H

L
L
H
H
H

L
L
H
H

L
L
H
H

H
L
H

L

L

H
L
H
L
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H

H
L
L
L
L

L
H
H
L
L

L
H
H
L
L

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
H
H
H

H
H

H
H

L

H
H
H
H
L

L
L
H

H
H
H
L
L

H
H
H
L
L

L
L
L
H
H

L
L
L
H
H

L
L
L
H
H

L
L
L
H
H

H
H
H
H
H

H
H
H
H
H

H
H

L
L

L
L

14 3
H
H
H
H

H
H
H
H

H
H
H
H
H

H
H
H
H

H
H
H
H

L

L

H
H

H ,H

L
L
L
L
L

H
H
H

Word

H

68
69
70
71
72

H
H
L
L

L
L
L
H
H

73
74
75
76
77

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L
L

L

H
L
L
H
H

H
H
H
H

H
H
L
L
L

H
H
L
L
L

L
L
H
H
H

L
L
H
H
H

L
L
H
H
H

L
L
H
H
H

L
L
H
H
L

L
L
H
H
L

H
L
H
L
H

L
H
L
L

L
H
L
H
H

H
L
H
L
L

78
79
80
81
82

L
L
L
L
L

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

H
H
H
H
H

H
H
H
H
H

H
L
L
L
L

H
L
L
L
L

L
H
H
L
L

L
H
H
L
L

L
H
L
H
L

H

H

L
H
H
L

L
L
L
H

L
H
H
H
L

83
84
85
86
87

L
L
L
L
L

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

H
H
H
H
L

H
H
H
H
L

H
H

H

H
H
L
L
H

H
L
H
L
H

H

H
H

20
21
22
23
24

H L
L.L
L L
L L
H L

88
89
90
91
92

L
L
L
H
H

L
L
L
H
H

25
26
27
28
29

L
L
L
L
L

H
H

L
L
L
H
H

L L
L - L
L L
H H
H H

L
L
L
H
H

L
L
L
H
H

L
L
L
H
H

H
L
L
H
H

H
L
L
H
H

L
H

H
H
L
H

H
H
L
H
H

L
L
L
H
H

93
94
95
96
97

H
L
H
H
H

H
L
H
H
H

30
31
32
33
34

L
L
L
L
L

L
L
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H

H
H
L
L
L

H
H
L
L

L
L
H
H
L

H

L
L

H
H
H
H
H

L
H

35
36
37
38
39

L
L
L
L
L

L
L
L
L
L

H
H
H
H
H

H
H
H
H
H

H
L
L
L
L

H
L
L
L
L

L
H
H
H
H

L
H
H
H
H

H

H
H

'!

H

L
L

H

L
L

H
'L

.-

L
L

L
H

H

L
L
H
L

L

L

L
L
H
H
L

H

L
H
L
H
H

L
H
L
L

H
H
H
H
H

98
99
100
101
102

L
H
H
L
L

L
H
H
L
L

L
H

L
H
L
L
H

L
L
L
L
H

H
H
H
H
L

103
104
105
106
107

H
H

L
H
H
L
H

L
H
H
H

108
109
110
111
112

L
H
L
H

L
H
L

H
L
H
H
L

L

L
H
L
L
L

H
L
L
H
L

L
L.
L
H
L

L
L
L
L
L

40
41
42
43
44

L
L
L
L
L

L
L
L
L
L

H
H
H
H
L

H
H
H
H
L

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

H
H

L
L
H

H
L
H
L
H

L L
L ' L
H H

L
H
L
H

L

H
L
L
L
H

H
L
L
H
H

H
L
L
H
H

L
H
L
H
L

H H
H H
L H
H ,L
L L

L
L
L
H
H

45
46
47
48
49

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

H
H
H
H
H

H
H
H
H
H

H
H
H
L
L

H
H
H
L
L

H H
L L
L L
H H
H.H

L
H
L
H
L

L
L
H
L
H

L
tc
H
L
H

H
H
L
H
L

113
114
115
116
117

L
L
H
H
L

L
L
H
H
L

H

L

H

L
H
L
H

H
L
H
H

50
51
52
53
54

L
L
L
L
L

L
L
L
L
L

L
L

L
L
L

H
H
L
L
L

L
L
L
L
L

H
H
L
L
L

H
H
L
L
L

L
L
H

L
L
H
H
H

L
L
H
H
L

L
L
H
H
L

H
L
H
L
H

H
L
H
L
L

H
H
H
H
H

L
L
L
L
L

118
119
120
121
122

H
L
L
L
L

L
H
H
H
H

L
H
H
H
H

L
H
H
L
L

L
H
H
L
L

L
H
L
H
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L
L

L
L
L
L

H

L
H
H
L
L

L
H
H
L
L

L
H

L
H
L
L
L

L
L
L
L
L

123
124
125
126
127

H
H

H
H

L
L
H

L
L
H

H
L
H

L
L
L
L

H

H L
L H
L L

L
L
L
L

H

L

L

L

H
H
H
H

L
L
L
L

L
L
L
L

L
L
L
L

H
H
H
H
H

L
L
L
L
L

L
L
L
L
L

L
L
L
L

to

H
L
L
L
L

H
H
H
H
L

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

L
L
L
L
H

L
L
L

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

L
L

L
H

L
H

Word

L
H

L
L

L
H
L
H
H

H
H
H
H

L
H
L
L
H

H
H
H
H

H
H
H
H

L

L

55
56
57
58
59

L
H
H
L
H

H
L
L
L
H

H
L
L
L
H

60
61
62
63
64

L
L
L
L
L

L
L
L
L
L

L

L

H

L
H

L
L

H
H

65
66
67

L
L
L

L
L
L

3-128

~

L
L

H

H

L
H
L
H

l.

L
L
L
L

L

L

L

H
L
L
L
L

L

H
L
H
H
L

H
L
L
L
L

L
H
L
L
L

L
L
H
L
L

L
L
L
H
L

L
L
L
L
H

L L
L L
L L
L 'L
L L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
H

H
H
H
H
L

L

128
129
130
131
132

L
L
L

L
L
L

L
L
L

L
L
L

L
L
L

H

L
L
H

L
L
L

H
H
H

L

L
L
L

133
134
135

l.
L
L
L

L
L

L
H
L

L
H

L
L

MC1 0287/MC1 0687

P SUFFIX

L SUFFIX

F SUFFIX

PLASTIC PACKAGE
CASE 648
MC10287 only

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650
MC10687 only

•

Numbers at ends of terminals denote pin numbers for Land P packages.
Numbers in parenthesis denote pin numbers for F package.

ELECTRICAL CHARACTERISTICS

Characteristic
Power Supply Drain Current
Input Current
Pins 3,14
Pins 4,5,12,13
Pins 6,7,10,11
Pin 9
Switching Times
Propagation Delay
CO to SO,C2
CO to S1
aO,aO',bO,bO~ to
aO,aO',bO,bO' to
al,al',b1,b1' to
MO to S1; M1 to
MO to C2

-30°C
+25 0 C
+85 0 C +1250 C
-55 0 C
Symbol Min Max Min Max Min Max Min Max Min Max
- 106 - 106 - 96 - 106 - 106
IE
linH

Unit
mAdc
~Adc

-

-

340
375
450
700

-

320
350
425
650

-

-

200
220
265
410

-

-

200
220
265
410

-

-

200
220
265
410
ns

tpd

SO,C2
Sl
Sl,C2
C2

Rise Time, Fall Time
(20% to 80%)

t+,t-

1.1
1.1
1.1
2.0
1.1
3.0
2.5

4.0 1.1
4.9 1.1
5.0 1.1
6.2 1.4
4.7 1.1
14 3.0
14 2.5

3.6
4.7
4.9
6.1
4.7
13
13

1.1

3.4 1.1

3.3 1.1

-55 0 C and +125'oC test values apply to MC106xx devices only.

3-129

1.1
1.1
1.1
1.4
1.1
3.0
3.0

3.4
4.5
4.7
5.8
4.5
12.5
12.5

1.1
1.1
1.1
1.4
1.1
3.0
2.5

3.7
4.7
5.2
6.4
4.8
13.5
13.5

1.1
1.1
1.1
2.0
1.5
3.0
2.5

4.2
4.9
7.0
6.6
5.2
14.5
14.5

3.1

1.1

3.4 1.1

3.6

ns

MC 10287/MCl 0687

APPLICATION INFORMATION

•

The MCl 0287/687 is a stand alone fully iterative dual
.multiplier cell. It is intended for use in parallel multiplier
arrays where maximum speed is desired. Each cell is a
modified gated adderlsu'btractor individually controlled
by a mode select line. Internal carry lookahead (also
called anticipated carry) is used to minimize sum and
carry out delay times.
The mode controls are specifically buffered such that
they can be grounded. Normally, MECL 10,000 device
inputs should not be placed at ground to establish a high
logic level. However, MO and Ml can be used at ground
potential for ease of layout in large arrays.
An array multiplier is defined a~ a multi-input, multioutput combinational logic circuit that forms the product
of two binary numbers. Binary multiplication can be
treated in two categories, that is, simple magnitude multiplication and 4-quadrant multiplication (requiring both
positive and negative numbers) .

MAGNITUDE BINARY MULTIPLICATION
Magnitude multiplication consists of the product of
two binary numbers in which all digits are number bits
(no sign bit). Magnitude representation then includes only'
positive numbers.
Thus, for a 4-bit number X the representation is:

X = X3 x2 xl xO
A 4-bit by 4-bit product becomes:

Z = X. '; = (X3 x2 xl XO) • (Y3 Y2 Yl YO)
The product consists of the sum of the single-bit products formed by this' expression. The standard "parallelo-

TABLE 1 - TYPICAL MUL TIPLY TIME FOR AN n-BIT BY
n-BIT BINARY MAGNITUDE ARRAY MULTIPLIER

Number of Bits
4
B
12
16

gram" matrix of the single-bit products (or summands)
can be written:
x3YO x2YO xlYO xOYO
x3Yl x2Yl xlYl xOYl
x3Y2 x2Y2 x 1Y2 xOY2
x3Y3 x2Y3 xlY3 xOY3
z7

z6

z5

z4

z3

z2

'2:1

zO

The MCl 0287 is used in an array summing the singlebit products to form the final result. It is observed that
the arithmetic product of binary digits Xi and Yi is also the·
logical product (xi times Yi = Xi AND Vi. The AND
function on the operand inputs of the MCl 0287 forms the
single-bit products of the matrix directly and sums them
internally. For magnitude binary multiplication, the
MC10287 functions as a dual full adder (MO, Ml are
both low).
The partial product array can be summed using a
number of different techniques. The fastest technique is
some form of matrix reduction scheme that prevents
carry propagation until the final level of summation.
Several of these schemes are discussed in detail in
Reference l_
As an example, if the matrix is rearranged and written
in a d)fferent form:
XOY3
xlY3 x3YO x2YO xlYO xOYO
x2Y3 x3Yl x'2Yl xlVl xOYl
x3Y3 x3Y2 x2Y2 xlY2 xOY2
z7

Z6

z5

z4

z3

z2

zl

zO

FIGURE 1 - 4-BIT BY 4-BIT MAGNITUDE ARRAY MULTIPLIER

Total MultiplV Time
(ns)

14
25

o

39
44

'I

3-130

'0

MC10287/MC10687

The summation of the partial products for this configuration is shown in Figure 1_ The number of MCl 0287's
for an n-bit by n-bit array is n(n-l)/2_ Note also that the
least significant product bit (zO = xOYO) is formed by an
individual AND gate (negative logic)_
Table 1 gives package count and typical mUltiplication
times for n-bit by n-bit magnitude multiplier arrays_ The
multiply times do not include wiring delays, and the
package count does not include the gate for the least
significant product bit.

in which all inputs are positive quantities. If one input is
negative (such as B), the outputs COllt and S must be
coded such that they can represent the 4 possible output
conditions. If B can be a negative one or zero, the net
output can then be:

!

-~

net output =

+1
+2

FOUR-QUADRANT MULTIPLICATION

If Cout, whose weight is twice that of S, is assigned a
positive value and S is a negative value, the above values
can be represented:

Sign-magnitude and 2's complement representations
are commonly used for 4-quadrant multiplication. For
sign-magnitude representation, the binary word consists of
a sign bit and magnitude bits which indicate the absolute
value of the number. For a 4-bit example:

where:

net output = 2 • Cout - S

-1 = 0-1
0=0-0

+1 = 2-1

)( = Xs x2 xl xo

+2 = 2 - 0

For X 0 Y = Z
Z = X • Y = (xs x2 Xl xO) • (Ys Y2 Yl YO)

If the truth table is written and logic equations generated, the result is a subtractor. That is, a subtractor used
in place of a full adder produces the proper outputs. The
symbol for the subtractor is:

An array multiplier for this representation consists of
an (n-l I-bit by (n-l I-bit magnitude multiplier that produces the product of the magnitude bits of X and Y and
of logic that produces the proper product sign bit
(zs =.Xs 0 ys)·
2's complement representation also includes a sign
bit which is a negative bit. That is:

A

~

X = -X3 x2 xl xO

co~

where x3 is the sign bit. The product of two 4-bit 2's
'complement numbers becomes:
Z = X • Y = (-X3 x2 Xl XO) • (-Y3 Y2 Yl YO)

z6

Z3

~

zO

/8

E)-Cin

The product is the' sum of this array of single-bit
products. However, notice that several summands are nega·
tive quantities, Therefore, they can not be simply added
as is the magnitude binary multiplier. The subtraction
capability of the MC10287 is utilized when considering
these negative quantities.
A standard full adder is symbolized as:

c:: ~

A

~

-A

A

zl

!

Also, if the input variables are mUltiplied by -1, the
outputs also are multiplied by -1. Thus, the following
devices are equivalent:

-x3YO x2YO xlYO xOYO
x2Yl xlYl xOY1

-x3Y2 x2Y2 x1Y2 xOY2
x3Y3 -x2Y3 -x 1Y3 -xOY3
-Z7

8- Cin
-5

The matrix for this expression is:

-x3Yl

/-8

5

-5

A

-A

~

/8

E)_C in

/-8

G~Cin

c:=: ~

c:U:

s

3-131

~

/6

G--Cin

~

-L~

-5

5

•

MC10287/MC10687

IMPROVED SWITCHING DELAYS

A basic adder/subtractor.can then handle all the varying
situations that appear in the multiplication matrix.
If the 2's complement matrix is rearranged:

The specified ac switchinp delays are given for output
loading of 50 n to -2 volts. With lower output current,
propagation delays will be improved and decreased multiply times can result. For output loading of 1 kn to VEE,
the following delays are typical.

-xOY3
-x1Y3 -x3YO x2YO xlYO xOyo
-x2Y3 -x3Yl
x2Yl X1Yl xOYl
x3Y3 -x3Y2 x2Y2 xlY2 xOY2
-Z7 z6

•

Z5

Z4

z3

z2

Zl

zo

4

14

B

25
39

6
28
66
120

12
16

44

C2
C2

1.7
2.8

2.7
3.1
3.9
4.4

SO
SO
S1
S1
S1

8.5

The techniques for implementing the MC10287 in
multiplier arrays resulted from work done originally at
M.I.T. Lincoln Laboratories. Also, applications information
presented here developed in part from personal corres·
pondence with P. Blankenship of Lincoln Labs. The
following references are useful in developing multipliers
using the MC10287:

Total Multiply Time
Package Count

CO

Delay (ns)

REFERENCE AND ACKNOWLEDGEMENT

TABLE 2 - TYPICAL MULTIPLY TIME FOR AN n-BIT BY
n-BIT 2'5 COMPLEMENT ARRAY MULTIPLIER

(ns)

Output

aO
aO
bO
. aO
bO
MO

The adder/subtractor array for this configuration is
shown in Figure 2. Care must be taken to insure that the
proper mode of operation (add or subtract) appears at
each summing node as a function of the positive and
negative weighted inputs.
The summand matrix can be altered different ways to
speed up the multiplier array. Reference 2 discusses the
algorithm used with the MC10287 in detail. Also, the
techniqaes of Reference 1 also apply to 2'·s complement
arrays using the MCl 0287.
Table'2 gives typical mUltiply times for 2's compleme.nt
arrays for n-bit by n-bit multipliers.

Number of Bits

Input

1. A. Habibi and P.A. Wintz, "Fast Multipliers," IEEE
Trans. Computers (Short Notes!. Vol. C-19, Feb.
1970, pp. 153-157.
2. S.D. Pezaris, "A 40-ns 17· Bit' by 17· Bit Array
Multiplier", IEEE Trans. Computers, Vol. C-20,
Number 4, April, 1971, pp. 442-447.

FIGURE 2 - 4-BIT BY 4-BIT 2'sCOMPLEMENT ARRAY MULTIPLIER

xovo

'0

3-132

MCM10139/MCM10539
32 x 8-BIT PROGRAMMABLE
READ-ONLY MEMORY

-

16

L SUFFIX

F SUFFIX

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650

2

15

3

14

4

13

5

12

6

11

8

9

10

o Typical Address Access Time = 15 ns
o Typical Chip Select Access Time = 10 ns

The MCM10139/10539 is a 256-bit field
programmable read only memory (PROM).
Prior to programming, all stored bits are at
logic 0 (low) levels. The logic state of each bit
can then be changed by on-chip programming
circuitry. The memory has a single negative
logic ch ip enable. When the ch ip is disabled
(CS = high). all outputs are forced to a logic 0
(low).

50 kn Input Pulldown Resistors on all inputs
Power Dissipation (520 mW typ @ 25 0 C)
Decreases with I ncreasing Temperature

•
•

BLOCK DIAGRAM

AD 10

A111

A212

32 x 8
Array and
AssocIated DrIvers

Input

Decoder

A3 13

A414

cs

15

------------------------.-+_--.-+_--.-+_--~+_--~+_~~~~~~~

9
07

6

06

05

3-133

04

4

3

03

02

01

DO

•

MCM 10139/M9M 10539

ELECTRICAL CHARACTERISTICS
-DOC

-SSoC

•

+7SoC

+2SoC

+ 12SoC

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Power Supply Drain Current

lEE

-

160

-

150

-

145

140

mAde

-

265

-

160

265

-

265

!lAde

Input Current High

linH

Logic "0" Output Voltage
MCM10139
MCM10539

VOL

450

265

Vde

-

-2.010 -1.665 -1.990 -1.650 -1.970 -1.625
-2.060 -1.655
-1.990 -1.620
-1.960 -1.545
-

-

SWITCHING CHARACTERISTICS (Note 1)
MCM10139

MCM10539
(VEE = -5.2 Vdc ± 5 %;
T A = -55°C to + 125°C)

*
*
*
*
*
*

Charactaristic

Symbol

(VEE = -5.2 Vdc ±5%;
TA DoC to +75 0 C)

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

tACS
tRCS
-tAA

15 ns Max
15 ns Max
20 ns Max

Rise and Fall Time

t r• tf

3.0 ns Typ

Input Capacitance
Output Capacitance

Cin
Cout

5.0 pF Max
B.O pF Max

NOTES:

1.

Test circuit characteristics: RT

=

= 50

.n. MCM 10139; 100 n., MCM 10539.

Conditions
Measured from 50% of Input to 50%

of output. See Note 2

Measured between 20% and BO% points.
Measured with a pulse technique.
CL ~ 5.0 pF including jig and stray capacitance.

For Capacitance Loading ~50 pF, delay should be derated by 30 ps/pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.

*To be determined; contact your Motorola representative for up-to-date information.

3-134

MCM10139/MCM10539

RECOMMENDED PROGRAMMING PROCEDURE*
The MCM10139 is shipped with all bits at logical "0" (Iowl. To write logical "15", proceed as follows.
MANUAL (See Figure 11

AUTOMATIC (See Figure 21

Step 1

Step 1

Connect VEE (Pin 81 to -5.2 volts and VCC (Pin 161
to 0.0 volts. Apply the proper address data and raise Vee
(Pin 161 to +6.8 volts.

Connect VEE (Pin 81 to -5.2 V and VCC (Pin 161 to
0.0 V. Address the word to be programmed by applying
-1.2 to -0.6 volts for a logiC "1" and -5.2 to -4.2 volts for a logic
"0" to the appropriate address inputs.

Step 2
Step 2

Raise VCC (Pin 161 to +6.8 volts.

Step 3

After

Vee

After a minimum delay of 100 J.1S and a maximum delay
of 1.0 ms, apply a 2.5 rnA current pulse to the first bit to
be programmed (0.1 .:;;: PW .:;;: 1 ms).

has stabilized at +6.8 volts (including any

ringing which may be present on the Vee line), apply
a current pulse of 2.5 rnA to the output pin corresponding to the

bit to be programmed

Step 4

to

Repeat Step 2 for each bit of the selected word specified
as a logic "1". (Program only one bit at a time. The delay
between output programming pulses should be equal to or less than
1.0 ms.1

Step 3

a logiC "1 ",

Return VCC to 0.0 Volts.

CAUTION
To prevent excessive chip temperature rise,

Step 4

Vee should

After all the desired bits of the selected word have been
programmed,
change
address
data
and
repeat
Steps 2 and 3.

not

be allowed to remain at +6.8 volts for more than 1 second.

NOTE: If all the maximum times listed above are mamtained, the
entire memory will program in less than 1 second. Therefore, it
would be permi'5sible for Vee to remain at +6.8 volts during the
entire programming time.

Verify that the selected bit has programmed by connecting a 460 n resistor to -5.2 volts and measuring
the voltage at the output pin. If a logic "1" is not detected at the
output, the procedure should be repeated once. During verification
VIH should be -1.0 to -0.6 volts.

Step 5

Step 6

After stepPing through all address words, return Vee to
0.0 volts and verify that each bit has programmed. If one
or more bits have not programmed, repeat the entire procedure
once. During verification VIH should be -1.0 to -0.6 volts.

Step 5

If verification is positive, proceed to the next bit to
be progr3mmed.

*NOTE: For deVices that program mcorrectly-retu rn. serialized units with individual truth tables. Noncornpl iance voids .warranty.

PROGRAMMING SPECIFICATIONS
Limits
Characteristic
Power Supply Voltage
To Program
To Verify
Programming Supply Current
Address Voltage
Logical "1"
Logical "0"

Symbol

Min

Typ

Max

Units

VEE
VCCP
VCCV

-5.46
+6.04

-5.2
+6.8

-4.94
+7.56

a

a

a

Vdc
Vdc
Vdc

ICCp

-

200

600

mA

VIH Program
VIH Verify
VIL

-1.2
-1.0
-5.2

-0.6
-0.6
-4.2

Vdc
Vdc
Vdc

-

-

-

-

1.0

sec

Output Programming Current

lOp

2.0

2.5

3.0

mAde

Output Program Pulse Width

to

0.5

-

1.0

ms

Output Pulse Rise Time

-

-

-

10

ilS

td
td 1

0.1
0.01

-

1.0
1.0

ms
ms

Maximum Time at Vee - Veep

Programming Pulse Delay (1)
Following Vce charlge
Between Output Pulses

NOTE 1. Maximum is specified to minimize the amount of time VCC is at +6.8 volts.

3-135

Conditions

VCC

=

+6.8 Vdc

II

MCM 10139/MCM 10539

FIGURE 1 - MANUAL PROGRAMMING CIRCUIT

+6.BV O.OV

Program

1

+15 V

3k
Verify

-O.B V
(Momentary)

"0"

16

Address

"1"

-C>-......-O

....---0--

460

Test
Point

n

Outputs

VEE

•

-5.2 V

CE
Open

B

VEE

VEE

-5.2 V

-5.2 V

7.5 k
(All Outputs)

~

VEE
-5.2 V

FIGURE 2 - AUTOMATIC PROGRAMMING CIRCUIT

Address

---1r

I

U

U

I

I

n

L'

I

I~------------------------------~I~t----~L

VCC

---1

f 4 - - - - - - - - - - - - - < 1 Second

3·136

-------------~

MCM10143
8 X 2 MULTIPORT REGISTER
FILE (RAM)

8 x 2 MULTIPORT REGISTER FILE
(RAM)
The MCM10143 is an 8 word by 2 bit multipart register file
(RAM) capable of reading two locations and writing one location simultaneously. Two sets of eight latches are used for data
storage in this LSI circuit.
WRITE
The word to be written is selected by addresses AO-A2. Each bit
of the word has a separate write enable to allow more flexibility in
system design. A write occurs on the positive transition of the clock.
Data is enabled by having the write enables at a low level when the
clock makes the transition. To inhibit a bit from being written, the
bit enable must be at a high level when the clock goes low and not
change until the clock goes high. Operation of the clock and the bit
enables can be reversed. While the clock is Iowa positive transition of
the bit enable will write that bit into the address selected by AO-A2.
READ
When the clock is high any two words may be read out simulta·
neously, as selected by addresses BO-B2 and CO-C2, including the
word written during the preceding half clock cycle. When the clock
goes low the addressed data is stored in the slaves. Level changes on
the read address lines have no effect on the output until the clock
again goes high. Read out is accomplished at any time by enabling
output gates (BO-81), (CO-Cl).

PIN ASSIGNMENT

VCC

24

2

OB,

VCC,

23

3

aBO

OC,

22

4

REB

oCo

2'

5

62

REc

20

Vcco

tpd:
Clock to Data out = 5 ns (typ)
(Read Selected)
Address to Data out = IOns (typ)
(Clock High)
Read Enable to Data out = 2.8 ns (typ)
(Clock high, Addresses present)
PD

=

BO

Clock

'9

B,

C2

,B

8

WE,

CO

'7

9

WEO

C,

'6

Do

A,

15

D,

AO

'4

VEE

A2

,3

6

610 mW/pkg (typ no load)

10
TRUTH TABLE
'MODE

INPUT
* ·Clock

Write

Read

L ""'H
H

wto
L

,>

WE,

REC

OBO

OB,

OCo

OC,

H
L

H
L

L
H

L

H

L
H

L
H

L

H

H

H

H

L

H
L

H
L
H

H
L
L

H
L
H

H

H

<:>
¢
Q
L

Q
Q

L

0
H

L
H

"

Q

L

H~L

Read

L-+H-L

Q
H

L~H

L

L

H

¢

¢

•• Note

REB

L

Read

H

"

OUTPUT

0,

<:>
<:>

Write

Read

.00

H
L

L

Clock occurs sequentlallv through Truth Table

• Note AO·A2, BO·82. and CO C2 are all set to same address location
throughout Table
(/) -- Don't Care

3-137

•

L SUFFIX
CERAMIC PACKAGE
CASE 623

,2

•

MCM10143

BLOCK DIAGRAM

4
U"

6

v
v
v

7
5

......

--

Read
Decoder
B

I

-,~

9
10

~
......

v

Cloc k~
14
A0
A 1 IJ 15
A 2v 13

WE

1

o1

v

8
11

---.....
~

v

Write
Amplifier
Bit 0

r-

~
......
~

Write
Amplifier
Bit 1

I~

.--

ro ;::-

C1
C2

v

17
16
18

v

......

--

Read
Decoder I----<
C

~

~

EC

Multiplexer
B-bit 0

l"-

~

Slave
B-bit 1

~

t- f.-

Output
Gate
B-bit 1

r---o

Output
Gate
B-bit 0

f---o a BO

2

a

,..

I--

Slave
B-bit 0

L.,

1----+

3

8 x1
Master Latches
Bit 0

Write
Decoder
A

t..
C

--1

t~

v

Multiplexer
B-bit 1

. 8 x 1
Master Latches
Bit 1

Multiplexer
C-bit 1

Multiplexer
C-bit 0

~

t- rt...

1----+

20

3-138

1

Slave
C-bit 1

Slave
C-bit 0

I-r-

Output
Gate
C-bit 1

~

- -..

Output
Gate
C-bit 0

~ aco

~

aC1

MCM10143

ELECTRICAL CHARACTERISTICS
oOC
Characteristics
Power Supply Drain Current
Input Current
Pins 10, 11, 19
All other pins
Switching Times Q)
Read Mode
Add ress Input
Read Enable
Data
Setup
Address
Hold
Address
Write Mode
Setup
Write Enable
Address
Data
Hold
Write Enable
Address
Data
Write Pulse Width
Rise Time, Fall Time
(20% to 80%)

+75 0 C

+25 0 C

Symbol

Min

Max

Min

Typ

Max

Min

Max

Unit

IE

-

150

-

118

150

-

150

mAdc

-

245
200

-

-

245
200

-

245
200

).IAdc

linH

ns
ts ±. 08 ±

4.0
1.1
1.7

tRE-QB+
tClock+QB-

15.3

4.5

10

14.5

4.5

15.5

5.3
7.3

1.2
2.0

3.5
5.0

5.0
7.0

1.2
2.0

5.5
7.6

tsetup(B-Clock-)

-

-

8.5

5.5

-

-

thold(Clock-B+)

-

-

-1.5

-4.5

-

-

tsetup(WE'-Clock +)
tsetup(WE +Clock-)
tsetup(A-Clock+)
tsetuolD-Clock+1

-

-

4.0
-2.0
5.0
2.0

-

-

-

-

-

7.0
1.0
8.0
5.0

thold(Clock-WE+)
thold (Clock +WE-)
thold (Clock + A +)
thold(Clock+D+)

-

-

5.5
1.0
1.0
1.0

2.5
-2.0
-3.0
-2.0

PWWE

-

-

8.0

t r , tf

1.1

4.2

1.1

G)AC timing figures do not show all the necessary presetting conditions.

3-139

,

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

5.0

-

-

-

2.5

4.0

1.1

4.5

..

MCM10143

READ TIMING DIAGRAMS

FIGURE 1

•

Enable

RE

FIGURE 2

Q

Data

,..,=,.,-,

Clock

,

••,,"'

nn ___
---------1 =t
nm£-___

~n-{,~~~:,-n--

0 _______

""':",:

n

n

m

i=

tsetu p

3-140

-

~~

- - -

~

---m

FIGURE 4

_____

t_h_O_ld_-_=i-t-___-'-__

__

FIGURE 3

MCM10143

WRITE TIMING DIAGRAM

Enable Setup
WE

l'-.'~

Clock

FIGURE 5

/

Enable Hold
WE

Clock

Disable
WE
Clock

Pulse Width

t·,,~
t~'·'l F'"""-t=
\

FIGURE 7

FIGURE B

Clock

'»'hOld

WE

Address

FIGURE 6

A ___

~~

________________

~

_ _ __

-- - -, :::==t.~;==:+==~:;;-=-~ \- -- - 0 - - - - - - - _ I '-------,f---...I

Clock _ _ _ _ _ _ _ _ _ _ _...1

3-141

FIGURE 9

II

•

MCM10144/MCM10544
256 X 1-BIT RANDOM
ACCESS MEMORY

A3
A4

..

'; :D

AI
A2

.

~

AO

,,:::
c ,

ID"C

3
4

:: 3

WE

«ID

!!.:

-1;0

"COl

';: «I

;;:.

«~
"C~

9

14

The MCM10i44/10544 is a 256 word
X 1-bit RAM. Bit selection is achieved by
means of an 8-bit address AO th rough A 7.
The active-low chip select allows memory
expansion up to 2048 words. The fast chip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS inputs
lo~) is controlled by the WE input. With WE
low the chip is in the write mode-the output
is low and the data present at Din is stored
at the selected address. With WE high the chip
is in the read mode-the data state at the
selected memory location is presented noninverted at D out .

0

5
;;:

A5

A6

13

Din

A7

•

Typical Address Access Time = 17 ns

•

Typical Chip Select Access Time = 4.0 ns

•

50.kS1 Input Pu Iidown Resistors on Ch ip
Select

•

Power Dissipation (470 mW typ @ 25 0 C)
Decreases with Increasing Temperature

. ' Pin-for-'Pin Replacement for F10410
TRUTH TABLE
MODE

INPUT

OUTPUT

es'

WE

Dm

Dout

Write "0"

L

L

L

L

Write "1"

L

L

H

L

Read

L

H

Disabled

H

'"

Q

'"

'"q,

PIN ASSIGNMENT

16
15

L
c

14

Don't Care.

13

4

~
"f{{fIf~CUE:AMIC

12
11

F SUFFIX

LSUFFIX
PACKAGE

CERAMIC PACKAGE
CASE 650

CASE 620

3-142

8

eS3

A5

10

VEE

A4

9

MCM10144/MCM10544

ELECTRICAL CHARACTERISTICS
OOC

-55°C
Characteristic
Power Supply Drain Current
Input Current High

+25 0 C

+75 0 C

+125 0 C

Symbol Min Max Min Max Min Max Min Max Min Max

Unit

lEE

-

140

-

135

-

130

-

125

-

125

mAdc

linH

-

375

-

220

-

220

-

220

-

220

!LAdc

-55°C and +125 0 C test values apply to MC105xx devices only_

SWITCHING CHARACTERISTICS (Note 1)
MCM10144 MCM10544

Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Rise and Fall Time

TA = 0 to TA = -55 to
+75 0 C,
+125 0 C,
VEE =
VEE=
-5.2 Vdc
-5.2 Vdc
± 5%
± 5%
Symbol Min Max Min Max Unit
tACS
tRCS
tAA

25
tw
2.0
tWSD
tWHD 2.0
tWSA 8.0
twHA .2.0
tWSCS 2.0
tWHCS
tws
tWR
t r , tf

Address to Output
CS or WE to Output
Capacitance
Input Capacitance
Output Capacitance

2.0
2.0
7.0

Cin
Cout

2.0
2.5
2.5

10
10
26

2.0
2.0
7.0

10
10
26

-

25
2.0
2.0
8.0
2.0
2.0

-

-

-

10
10

2.0
2.5
2.5

Measured from 50% of
input to 50% of output.
See Note 2.

ns

tWSA = 8.0 ns
Measured at 50% of
input to 50% of output.
tw = 25 ns.

ns

Measured between 20%
and 80% points..

pF

Measured with a pulse
technique.

-

10
10

1.5
1.5

7.0
5.0

1.5
1.5

7.0
5.0

-

5.0
8.0

-

5.0

-

I,W

-

Conditions

ns

..

NOTES: 1. Test circuit characteristics: RT = 50 .11, MCM10144; 100 fl, MCM10544. CL';; 5.0 pF (including Jig
and stray capacitance). Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MEC!. System Design
Handbook.

3-143

•

•

MCM10145/MCM10545
16 X 4-BIT REGISTER FILE
(RAM)

00

01

02

03

The MCM10145/10545 is a 16 word X 4-bit
RAM. Bit selection is achieved by means of
a 4-bit address AO through A3.
The active-low chip select allows memory
expansion up to 32 words. The fast ch ip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS in'put
low) is controlled by the WE input. With WE
low the chip is in the write mode-the output
is low and the data present at Dn is stored at
the selected address. With WE high the chip
is in the read mode-the data state at the
selected memory location is presented noninverted at On.

A1

Typical Address Access Time = 1~ ns

•
A2

•
.•

A3

•

Typical Chip Select Access Time = 4.5 ns
50 kn Pulldown Resistors on All Inputs
Power Dissipation (470 mOW typ @ 25 0 C)
Decreases with Increasing Temperature

PIN ASSIGNMENT
DO

01

02

03

,6

3

,5
,4

4

'3

5

,2

6

"'0

8

9

TRUTH TABLE
MODE

LSUFFIX

INPUT

OUTPUT

CS

WE

On

an

Write"O"

L

L

L

L

Write "1"

L

L

H

L

R.ed

L

H



a

Ol •• bled

H





L

~ - Don't Care.

CERAMIC PACKAGE
CASE 620

FIGURE 1 - CHIP ENABLE STROBE MODE

A---.....II
tC$O

Din

F SUFFIX
CERAMIC PACKAGE
CASE 650

-----+-"

cs -------,,1

3-144

tcs

MCM1 0145/MCM1 0545
ELECTRICAL CHARACTERISTICS
OOC

-55°C
Characteristic
Power Supply Drain Current
Input Current High
-55°C and

+125 0

+25 0 C

+75 0 C

+ 125°C

Symbol Min Max Min Max Min Max Min Max Min Max
125 120 - 120
135 - 130 lEE
linH

-

375

-

220

-

220

-

220

-

220

Unit
mAdc
,uAdc

C test values apply to MC105xx devices only.

SWITCHING CHARACTERISTICS (Note

1)

MCM10145 MCM10545
TA=Oto
+75 0 C,
VEE=
-5.2 Vdc
± 5%
Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Chip Enable Strobe Mode
Data Setup Prior to Chip Select
Write E'nable Setup Prior to
Chip Select
Address Setup Prior to Chip Select
Data Hold Time After Chip Select
Write Enable Hold Time After
Chip Select
Address Hold Time After Chip
Select
Chip Select Minimum Pulse Width
Rise and Fall Time
Address to Output
CS to Output
Capacitance
Input 'Capacitance
Output Capacitance

Symbol Min

Max

TA=-55to
+125 0 C,
VEE =
-5.2 Vdc
± 5%
Min

Max

tACS
tRCS
tAA

2.0
2.0
4.0

8.0
8.0
15

2.0
2.0
4.0

10
10
18

tw
tWSD
tWHD
tWSA'
tWHA
tWSCS

8.0
0
3.0
5.0
1.0
0

-

-

-

8.0
0
4.0
5.0
3.0
5.0

-

tWHCS
tws
tWR

0
2.0
2.0

8.0
8.0

0
2.0
2.0

10
10

tCSD
tcsw

0
0

-

-

-

tCSA
tCHD
tCHW

0
2.0
0

-

-

-

-

-

-

-

tCHA

4.0

-

-

-

tcs

18

-

-

-

1.5
1.5

7.0
5.0

1.5
1.5

7.0
5.0

-

6.0
8.0

-

6.0
8.0

-

-

-

Conditions

ns

Measured from 50% of
input to 50% of output.
See Note 2.

ns

tWSA = 5 ns
Measured at 50% of
input to 50% of output.
tw = 8 ns.

ns

Guaranteed but not
tested on standard
product. See Figure 1.

ns

Measured between 20%
and 80% points.

pF

Measured with a pulse
technique.

-

t r • tf

Cin
Cout

Unit

NOTES: 1. Test circuit characteristics: RT = 50 n. MCM10145; 100 n. MCM10545. CL';; 5.0 pF (including jig
and Stray Capacitance). Delay should be derated 30 ps/pF for capacitive loads up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.

3-145

•

MCM10146/MCM10546
1024 X1-BIT RANDOM
ACCESS MEMORY

The MCM10146/10546 is a 1024 X 1-bit
RAM_ Bit selection is achieved by means of'
a 10-bit address, AO to A9.
The active-low chip select is provided for
memory expansion up to 2048 words.
The operating mode of the RAM (CS input
low) is controlled by the WE input. With WE
low, the chiP: is in the write mode, the output,
Dout, is low and the data state present at
Din is stored at the selected address. With WE
high, the ch ip is in the read mode and the data
stored at the' selected memory location will be
presented non· inverted at D out . (See Truth
Table.)

°out

AO
A1
13

A2
A3
15

A4

A5

A6

A7

AS

A9

•

Pin-far-Pin Compatible with the 10415

•

Power Dissipation'(520 mW typ@ 25 0 C)
Decreases with I ncreasing Temperature

•

Typical Address Access of 24 ns

•

Typical Chip Select Access o'f 4,0 ns

•

50

kn

Pulldown Resistor on Cl')ip Select
Input

PIN ASSIGNMENT
TRUTH TABLE
MODE

INPUT

CS

.'

O,n

D out

L

L

L
L

Write "0"

t-

Write "1"

L

L

H

Read

L

H

DIsabled

H

'"
'"

lP '"

'"

Don't Care.

16

OUTPUT

WE

15
3

'4

4

13

6

11

'2

a
L

10
9

_LSUFFIX

CERAMIC PACKAGE

CERAMIC PACKAGE
CASE 620

CASE 650-03

3-146

MCM10146/MCM10546

ELECTRICAL CHARACTERISTICS
OOC

-55°C

+25 0 C

+125 0 C

+75 0 C

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Power Supply Drain Current

lEE

-

155

-

150

-

145

-

125

-

125

mAde

-

375

-

220

-

220

-

220

-

220

",Adc

Input Current High

linH

Logic "0" Output Voltage

VOL

-1.970 -1.655 -1.920 -1.665 -1.900 -1.650 -1.880 -1.625 -1.870 -1.545

Vdc

NOTE: -55°C and +125 0 C test values apply to MCM105XX only.

SWITCHING CHARACTERISTICS (Note 1)
MCM10146

a

TA to
+75 0 C,
VEE = -5.2 Vdc

MCM10546
TA - -55 to
+125 0 C,
VEE

± 5%

Characteristics

Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Wr.ite Mode
Write Pulse Width
(To guarantee writing)
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time

Write Recovery Time
Rise and Fall Time

CS

Symbol
tACS
tRCS
tAA

Min

Max

Unit

2.0
2.0
8.0

7.0
7.0
29

2.0
2.0
8.0

8.0
8.0
40

tw

25

-

25

Conditions
Measured at 50% of input
to 50% of output.

See Note 2.
ns

-

tWSA = 8.0 ns.
Measured at 50% of input
to 50% of output.

tWSD
tWHD
tWSA
tWHA
tWSC'S

5.0
5.0
8.0
2.0
5.0

-

5.0
5.0
10
8.0
5.0

tWHCS
tws
tWR

5.0
2.8
2.8

7.0
7.0

5.0
2.8
2.8

12
12

-

1.5

4.0

1.5

4.0

1.5

8.0

1.5

8.0

-

5.0
8.0

-

5.0
8.0

Cin
Cout

-

-

tw = 25 ns

-

tr,tf

Address to Output

NOTES:

± 5%

Max

ns

or WE to Output

Capacitance
I nput Capacitance
Output Capacitance

Min

= -:5.2 Vdc

ns

Measured between 20% and
80% P?ints.

pF

Measured with a pulse
technique.

1. Test circuit characteristics: RT = 50 n, MCM10146; 100 n, MCM10546. CL';; 5.0 pf including jig and stray capacitance.
For Capacitance Loading';; 50 pF, delay should be derated by 30 ps/pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.

3-147

•

MCM10147/MCM10547
128 X 1-BIT
RANDOM ACCESS MEMORY

II

The MCM1047/10547 is a fast 128-word
X 1-bit RAM. Bit 'selection is achieved by
means of a 7-bit address, AO through A6.
The active-low ch ip selects and fast ch ip
select access time allow easy memory expansion
up to 512 words without affecting system
performance.
The operating mode (CS inputs low) is
controlled by the WE input. With WE low the
chip is in the write mode-the output is low and
the data present at Din is stored at the selected
address. With WE high the chip is in the read
mode-the data state at the selected memory
location is presented non-inverted a~ D out .

2

AO

3

AI

12
4

A2

,5

A3

11

•

Typical Address Access Time of 10 ns'

. ' Typical Chip Select Access Time of 4.0 ns

A4

A5

kn

•

50

•

Power Dissipation (420 mW typ @ 25 0 C)
Decreases with I ncreasing Temperature

•

SimiiartoF10405

A6

Input Pulldown Resistors
on All Inputs

PIN ASSIGNMENT
TRUTH TABLE

16

MODE

15
14

13

4

12
6

11

INPUT

OUTPUT

Dout

es·

we

Din

Write "0"

L

L

L

L

Write "1"

L

L

H

L

Read

L

H

H

'"

Q

Oisabled

'"

¢

L

f/J = Con't Care .
B

vee

N.C.

.. _ _ LSUFFIX
CERAMIC PACKAGE
CASE 620

3-148

CERAMIC PACKAGE
CASE 650

MCM10147/MCM10547

ELECTRICAL CHARACTERISTICS
Characteristic

Power Supply Drain Current
Input Current High

DOC
-SSoC
+7S oC +12S oC
+2S oC
Symbol Min Max Min Max Min Max Min Max Min Max
95
9S
11S - lOS - 100 lEE
- 375 - 220 - 220 - 220 - 220
linH

-

-

Unit
mAdc
"Adc

·S5 0 C and +12S o C test values apply to MC10Sxx devices only.

SWITCHING CHARACTERISTICS (Note 1)

Characteristics

Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time

Write Mode
Write Pulse Width
Data Setup Time Prior to Write

Data Hold Time After Write
Address Setup Time Prior to Write

Address Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time

Rise and Fall Time
Capacitance
I nput Capacitance

Symbol

MCM10S47
MCM10147
TA - -55 to +12S oC.
TA=Oto+7S oC.
VEE = -S.2 Vdc ±S% VEE = -5.2 Vdc ±S%
Min
Max
Min
Max

tACS
tRCS
tAA

2.0
2.0
5.0

8.0
8.0
15

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
tws
tWR

8.0
1.0
3.0
4.0
3.0
1.0
1.0
2.0
2.0

-

8.0
8.0

t r• tf

1.5

5.0

-

-

··
·
··
··
··
···
·

5.0
Output Capacitance
8.0
Cout
NOTES: 1. Test CirCUIt charactemtrcs: RT = 50 n. MCM10147; 100 n. MCM10547.
CL'; 5.0 pF (including jig and stray capacitance).
Cin

-

··
·

Unit
ns

Conditions
Measured from SO% of
input to SO% of output.
See Note 2.

ns

tWSA = 4.0 ns
Measured at 50% of input
to 50% of output.
tw = 8.0 ns.

ns

Measured between 20% and
80% points.

-

-

··
·
··

pF

Measured with a pulse

technique.

Delay should be derated 30 ps/pF for capacitive load up to 50 pF.

2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
*To be determined; contact your Motorola representative for up-to-date information.

3-149

•

MCM10148/MCM10548
64 X 1-BIT
RANDOM ACCESS MEMORY

AO
3

AI

II

12

WE

6

A2

13

A4

A3

Din

AS

The MCM1 014811 0548 is a fast 64-word X
1-blt RAM. Bit selection is achieved by means
of a 6-bit address. AO through A5.
The active-low chip selects and fast chip
select access time allow easy memory expansion
up to 256 words without affecting system.
performance.
The operating mode (CS inputs low) is
controlled by the WE input. With WE low· the
chip is in the write mode-the output is low
and the data present at Din is stored at the
selected address. With WE high the chip is
, in the read mode-the data state at the selected
memory location is presented non-inverted
at D out .
•

Typical Address Access Time of 10 ns

•

Typical Chip Select Access Time of 4.0 ns

•

50

•

Power Dissipation (420 mW typ @ 25 0 C)
Decreases with Increasing Temperature

kn

Input Pu IIdown Resistors
on All Inputs

PIN ASSIGNMENT
TRUTH TABLE

16

MODE

15
3

14

4

13
12
11
10

8

9

-

LSUFFIX

INPUT

OUTPUT

cs·

WE

Din

Write "0"

L

L

L

L

Write:""

L

L

.H

L

Read

L

H

-----j

Decoder

1----+-----'

cs '3
F SUFFIX
CERAMIC PACKAGE
CASE 650

3-152

11

12

14

,15

03

02

Dl

00

MCM10149/MCM10549
ELECTRICAL CHARACTERISTICS
Characteristic
Power Supply Drain Current

DOC
+2SoC
+7SoC +12SoC
-ssoC
Symbol Min Max Min Max Min Max Min Max Min Max
125
130
125
140
135
lEE

I nput Current High

linH

450

265

265

265

Unit
mAdc
/lAdc

1:.165

-5S0C and +12SoC test values apply to MC10Sxx devices only.

SWITCHING CHARACTERISTICS (Note 1)

Characteristics

Read Mode
Chip Select Access Time
Chip Select Recovery Time

Address Access Time
Rise and Fall Time

Symbol

MCM10149

MCM10549

TA - 0 to +75 0 C,
VEE = -5.2 Vdc ± 5%

TA - -55 to +125 0 C,
VEE = -5.2 Vdc ±5%

Min

Max

tACS
tRCS
tAA

2.0
2.0
7.0

10
10
25

tr,tl

1.5

7.0

Cin

-

5.0
B.O

Min

Max

Unit

··
·
·

···
·

ns

-

5.0
B.O

Capacitance
I nput Capacitance

Conditions
Measured Irom 50% 01
input to 50% of output.

See Note 1.
ns

Measured between 20%
and BO% points.

pF

Measured with a pulse
technique,

Output Capacitance
Cout
NOTES. 1. Test CIrCUit characterIStiCS. RT - 50 n, MCM10149, 100 n, MCM10549.
CL" 5.0 pF !including jig and stray capacitance)
Delay should be derated 30 ps/pF lor capacitive load up to 50 pF
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.

4. Vcp

= VCC = Gnd lor

normal operation.

*To be determined; contact your Motorola representative for up-to-date information.

PROGRAMMING THE MCM10149
During programming of the MCM10149, input
pins 7, 9, and 10 are addressed 'with standard
M ECL 10K logic levels. However, during programming input pins 2, 3, 4, 5, and 6 are addressed
with 0 V .;;; VIH .;;; + 0.25 V and VEE';;; VIL';;;
-3.0 V. It should be stressed that this deviation
from standard input levels is required only during
the programming mode. During normal operation,
standard M ECL 10,000 .input levels must be used.
With these requirements met, and with V CP =
VCC = 0 V and VEE = - 5.2 V ± 5%, the address
is set up. After a minimum of 100 ns delay, VCP
(pin 1) is ramped up to +12 V ± 0.5 V (total

Coincident with, or at some delay after the
V CP pulse has reached its 100% .Ievel, the desired
bit to be fused can be selected. This is done by
taking the corresonding output pin to a voltage
of + 2.85 V ± 5%. I t is to be noted that only one bit
is to be fused at a time. The other three unselected
outputs should remain terminated through their
50 ohm load resistor (100 ohm for MCM10549)
to -2.0 V. Current into the selected output is
5 mA maximum.
After the bit select· pulse has been applied to
the appropriate output, the fusing current is
sourced out of the chip select pin 13. The 0% to
100% rise time of this current pulse should be
250 ns max. Its pulse width should be greater than
100/ls. Pulse magnitude is 50 mA ±5.0 mAo The
voltage clamp on this current source is to
be -6.0 V.

voltage VCP to VEE is now 17.2 V, + 12 V [-5.2 V]). The rise time of this VCP voltage
pulse should be in the 1 -10 /ls range, while its
pulse width (tw 1) should be greater than 100 /ls
but less than 1 ms. The V CP supply current at + 12
V will be approximately 525 mA while current
drain from V CC will be approximately 175 mAo A
current limit should therefore be set on both of
these supplies. The current limit on the VCP
supply should be set at 700 mA while the V CC supply should be limited to 250 mAo It should be
noted that the VEE supply must be capable of
sinking the combined current of the V CC and
V CP supplies while maintaining a voltage of
-5.2 V ± 5%.

t

NOTE:

t

After the fusing current source has returned
mA, the bit select pulse is returned to it initial
level, i.e., the output is returned through i.ts load
to -2.0 V. Thereafter, VCP is returned to 0 V.
Strobing of the outputs to determine success in
programming
should
occur no sooner than
100 ns after V CP has returned to 0 V. The reo
maining bits are programmed in a similar fashion.

o

F or devices that program incorrectly, return serialized u nits with Individual truth tables.

Non compliance voids warranty.

3-153

•

MCM10149/MCM10549

PROGRAMMING SPECIFICATIONS
The following timing diagrams and fusing
information represent programming specifications
for the MCM10149.
Vee =- Pin 16 >=. 0 V
VEE =: Pin 8 = -5.2 V ±5%

+12 V
!

Definitions and values of timing symbols are
as follows.
Symbol

0.5 V

t;"1

Pulse Width,
Programmin"g Voltage

t01

Delay Time,
Programming Voltage
Pulse to Bit
Select Pu Ise

;;'0

tw2

,Selected Output Open
Pin (11, 12,14or 15)

SOmA
:!:5mA

;;. 100 /-Is

< 1 ms

Pulse Width, Bit Select

;;. 100 /-Is

Delay Time, Bit Select
Pulse to Programming
Voltage Pu Ise

;;'0

t03

Delay Time, Bit Select
Pulse to Programming
Current Pulse

;;. 1 /-IS

tr3

Rise Time, Programming
Current Pulse

tw3

Pulse Width,
Programming
Current Pulse

t04

Delay Time,
Programming Current
Pulse to Bit
Select Pu Ise

a

3-154

;;. 1 /-Is

, t02

Chip Select Pin 13 0 m A - - - + - '

The timing diagram is shown for programming
one bit. Note that only one bit is blown at a time.
All addressing must be done 100 ns prior to the
beginning of the VCP pulse, i.e., VCP =
V.
Likewise, strobing of the outputs to determine
success in programming should occur no sooner
than 100 ns after V CP retu rns to a V.
Note that the fusing current is defined as
a positive current out of the chip select, pin 13.
A programming duty cycle of .. 15% is to be
observed.

Value

Rise Time,
Programming Voltage

OV

II

Definition

tr1

250 ns max
;;. 100 /-IS

;;. 1 /-Is

MCM10149/MCM10549

\,

MANUAL PROGRAMMING CIRCUIT

'!

+5 V

+5 V

~05/lF

12k

a2k

0.005/lF

J201-

+5 V

/ls
Delay

1

Verify

I/S MC740S

.-'--"""
Q

1/2
MC8S02

S80"""'--...r
1/2
MCBS02

Cp

Enable
Current

Pulse

Q

..-r--l.-

Q

>100/ls

Program
Enable

+5 V

+5 V

~
lN914
-5.2 V
(-S V Clamp)
Current Sr-0:..u:..r...:c..:,e...._--"""""_...._ _ _--,
510
510
lN914
or Equiv.

100

-5.2 V

-12 V

+5 V

+12.5 V
.-------1_--0+5 V

.---->----, Limit

1/4
MC7438

180

51n,1/2W
+5 V

150

1.0

n,

240

1/4 MC7438

180

1/2W

lN914

......... - - -...---.~---.

o-~_

:];._ O.I/lF
13

510
7

"<>--.....----().---l A 7
1.0 k

11

5

"o--~>------<>---l

A6

D3r--<~--~.----~

1.0 k
6
A5

1.0 k

12
10

02

A4
1.0 k
9
A3

C

MCM101491
10549

1.0 k

Rotary SW
14
01

3

680
-5.2 V

A2

2

15

~-~----~~Al

DOr-~>-----.----o

1.0 k

680
-5.2 V

4
'Qo-~_--~>---1

1.0 k
-5.2 V

AO
VEE

VCC

3-155

11

MCM10152/MCM10552
256 X 1-BIT
RANDOM ACCESS MEMORY

•

.

~

AO

"5:D

A1

",'0
• 0

A2
A3

•

'0:::

c ,

;:.

u

3

~o

4

":t!

9

WE

BE

'0",

'i:

'O.~

A4

14

..:"'

5

selected

«I

C

The MCM 10152/10552 is a 256-word X 1-bit
RAM. Bit selection is achieved by means of
an 8-bit address AO through A 7.
The active-low chip select allows memory
. expansion up to 2048 words. The fast chip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS inputs
low) is controlled by the WE input. With WE
low the chip is in 'the write mode-the output
is low and the data present at Din is stored
at the selected address. With WE high the chip
is in the read mode-the data state at the

13

Din

•

;:

A5

A6

loca~ion

is presented non-

Typical Address Access Time = 11 ns

•

Typical Chip Select Access Time = 4.0 ns

•

50 k.!1 Input Pulldown Resistors
on All Inputs

•

Power Dissipation (570 mW typ @ 25 0 C)
Decreases with Increasing Temperature

•

Pin-for-Pin Compatible with F10410/10414

A7

PIN ASSIGNMENT

memory

inverted at D out .

TRUTH TABLE
16

MODE

15
14

4

13
12

6

8

11

~o~

~~!_U

LSUFFIX

CERAMIC PACKAGE
CASE 620

3.-156

OUTPUT

INPUT

cs·

WE

Din

Dout

Write "0"

L

L

L

L

Write "1'"

L

L

H

L

. Read

L

H

Disabled

H

'"
'"

Q

'" 4J

= Don't Care.

L

MCM 10152/MCM 10552

ELECTRICAL CHARACTERISTICS
Characteristic
Power Supply Drain Current
Input Current High

_55°C
OOC
+25 0 C
+75 0 C +125 0 C
Symbol Min Max Min Max Min Max Min Max Min Max
- 140 - 135 - 130 - 125 - 125
lEE
375
220 - 220 - 220 - 220
linH

Unit

mAdc
/lAdc

_55°C and +125 0 C test values apply to MC10Sxx devices onlv_

SWITCHING CHARACTERISTICS (Note 1)
MCM10152

Characteristics

Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time

Symbol
tACS
tRCS
tAA

2.0
2.0
7.0

7.5
7.5
15

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
tws
tWR

10
2.0
2.0
5.0
3.0
2.0
2.0
2.5
2.5

-

7.5
7.5

tr.tf

1.5

5.0

Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write

Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to Write

Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time

Rise and Fall Time

MCM10552

TA=-55to+1250C.
TA = 0 to +75 0 C.
VEE = -5_2 Vdc 15% VEE = -S_2 Vdc 15%
Max
Min
Max
Min

-

-

··
·
··
··
·

···
·
·

Capacitance

5.0
8.0
Cout
NOTES: 1. Test circuit charactenstlcs: RT = 50 n. MCM10152; 100 n. MCM10552.
CL';; 5.0 pF (including jig and stray capacitance I.
Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
Jnput

Capacitance
Output Capacitance

Cin

-

··
·

Unit

Conditions
Measured from 50% of
input to 50% of output.

See Note 2.
ns

-

tWSA = 5.0 ns
Measured at 50% of input
to 50% of output.

tw

-

-

···

··

ns

Measured between 20% and
80% points.

pF

Measured with a pulse
technique.

2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
*To be determined; contact your Motorola representative for up-ta-date information.

3-157

= 10 ns.

-

II

..

3-158

MECL III
MC1600 Series

•

MC1648/MC1648M
VOLTAGE-CONTROLLED
OSCILLATOR

The MC1648 requires an external parallel
tank circuit consisting of the inductor (L)
and capacitor (C).
A varactor diode may be incorporated into
the tank circuit to provide a voltage variable
input for the oscillator (VCO). The MC1648
was designed for use in the Motorola PhaseLocked Loop shown in Figure 9. This device
may also be used in many other applications
requiring a fixed or variable frequency clock
source of high spectral purity. (See Figure 2.)
The MC1648 may be operated from a +5.0
Vdc supply or a -5.2 Vdc supply, depending
upon system requirements.

.-------,
I
I
Bias Point 10
Tank
12

I

I

I
I

L _______

J

Output

5

AGe
Input Capacitance = 6 pF typ
Maximum Series Resistance for L (External
Inductance) = 50 n typ ,
Power Dissipation = 150 mW typ/pkg
(+ 5.0 Vdc Supply)
Maximum Output Frequency = 225 MHz typ

II

Supply Voltage

Gnd Pins

Supply Pins

+5.0 Vdc

7,8

1,14

-5.2 Vdc

1, 14

7,8

L SUFFIX

PSUFFIX

F SUFFIX

CERAMIC PACKAGE
CASE 632

PLASTIC PACKAGECASE 646

CERAMIC PACKAGE
CASE 607

FIGURE 1 - CIRCUIT SCHEMATIC
VCC2
(14)

02

(71
(101
(121
(81
(51
Vee,
Bias Pt.
Tank
Vee 2 AGe
Numbers in parenthesis denote pin number for F packegelCase 607), L package tCas. 6321. and P package (Ca. 646).

4-2

s:
(")

....

~

-....s:
CO

FIGURE 2 - SPECTRAL PURITY OF SIGNAL AT OUTPUT

!1 1·

(")

L: Micro Metal torroid #T20-22, 8 turns
#30 Enamled Copper wire.

c

~

~

3.0 - 35 pF

10

14

I

1

_

0.1
I'F

,---------,-

_

3
Signal
Under

I

--'

Center Frequency"" 1 00 MHz

:r:

Scan Width = 50 kHz/div

t

VIHmax
MC1648

(Volts)

mAde

VILmin

IL

-30 0 C

+2.00

+1.50

5.0

-5.0

+25 0 C

+1.85

+1.35

5.0

-5.0

+1.70

+1.20

5.0

-5.0

+85 0 C

Test

12

Vertical Scale'" 10 dBidlv

I'

1200'

I

B.W.;; 10 kHz

@Test
Temperature

F

-

:~:

I
I

I

TEST VOLTAGE/CURRENT VALUES
+50 Vdc

10

~

CO

s:

MC1648M
0.1 I'F

·The 1200 ohm resistor and the scope termination impedance constitute a 25:1 attenuatar
probe. Coax shall be CT -070-50 or equivalent.

-55°C

+2.07

+1.57

5.0

-5.0

+25 0 C

+1.85

+1.35

5.0

-5.0

+125 0 C

+1.60

+1.10

5.0

-5.0

ELECTRICAL CHARACTERISTICS
Supply Voltage = +5.0 Volts
-55°C
Characteristic

Symbol

Min

Power Supply Drain Current

IE

-

-30°C

MaX"·

+25 0 C

+85 0 C

+ 125°C

Min

Max

Min

Max

Min

Max

Min

Max

Unit

-

-

-

-

41

-

-

-

-

mAdc

Conditions
Inputs and outputs open.

Logic "1" Output Voltage

VOH

3.92

4.13

3.955

4.185

4.04

4.25

4.11

4.36

4.16

4.40

Vdc

Logic "0" Output Voltage

VOL

3.13

3.38

3.16

3.40

3.20

3.43

3.22

3.475

3.23

3.51

Vdc

VIHmax to Pin 12, IL@Pin 3.

VBias'

1.67

1.97

1.60

1.90

1.45

1.75

1.30

1.60

1.20

1.50

Vdc

VILmintoPin12.

Bias Voltage

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Peak-to-Peak Tank Voltage

Vp_p

Min·
-

-

-

-

-

-

-

400

-

-

-

-

-

-

-

Output Duty Cycle

VDC

-

-

-

-

-

-

-

50

-

-

-

-

-

-

-

fmax «

-

-

225

-

200

2~5

_-

-

225

-

-

-.2~

-

~scillation Fr"que_nc y

22~~

UA Temperature.

-

-

mV

-

-

MHz

225

%

See Figure 3.

MC1648/MC1648M

FIGUR E 3 - TEST CIRCUIT AND WAVEFORMS

.. Use high Impedance probe (

> 1.0

Megohm must

be used).

... The 1200 -ohm resistor and the scope termination

Impedance constitute a 25.1 attenuatar probe.
Coax shall be CT -070·50 or equivalent .
.... Bypass only that supply opposite ground.

OPERATING CHARACTERISTICS
Figure 1 illustrates the circuit schematic for the
MC164S. The oscillator incorporates positive feed·
back by coupling the base of transistor 07 to the
collector qf 08. An automatic gain control (AGe)
is incorporated to limit the current through the
emittElr·coupled pair of transistors (07 and OS) and
allow optimum frequency response of the oscillator.

FIGURE 4 - THE MC1648 OPERATING IN THE VOLTAGE
CONTROLLED MODE

Output

In order to maintain the high 0 of the oscillator,
and provide high spectral purity at the output,
transistor 04 is used to translate the oscillator sig·
nal to the output differential pair 02 and 03.
02 and 03, in conjunction with output transistor
01, provides a highly buffered output which pro·
duces a square wave. Transistors 09 and all provide the bias drive for the oscillator and output
buffer. Figure 2 indicates the high spectral puritY
of the oscillator output (pin 3).

12

5

the cathode of the varactor diode (D) should be
biased at least 2 VSE above VEE (~1.4 V for positive supply operation).
When the MC1648 is used with a constant de voltage
to the varactor diode, the output frequency will vary
slightly because of internal noise. This variation is plotted
versus operating frequency in Figure 5.

When operating the oscillator in the voltage
controlled mode (Figure 4), it should be noted that

FIGURE 5 - NOISE DEVIATION TEST CIRCUIT AND WAVEFORM
N

I

100

rJl

VCC

:;
II:

Z

o

l-

I-

5.0 Vdc

Oscillator Tank Components
ICircuit of Figure 41

...-


w

o

10

V

>-

f
MHz

D

I'H

1.0·10

MV2115

100

10·60

MV2115

2.3

60·100

MV2106

0.15

L

u

z

w

:J

ow

II:
u.

0

z

w
:l

a:

36

..

32

I:l
I:l

0

,

~

0

'/

44
40

w

Vin

52
48 .

0

II.

L: Micro Metal Toroidal Core #T44-10,
4 turns of No. 22 copper wire:

60
·56

10

V

./

Il F

;/

28
24
20

11.0

4.0

5.0

7.0

6.0

8.0

9.0

I

:

I

I

12

f out

:

I.

']

MV14Ql

5 1l F J
3.0

I

L

. ,roo

/'
2.0

l

II~

./

16
12
8.0 .
0

~"OO'

:01.b ;

1 k

.

3

I

'-------

.

-~

5

:;;J; O.I.IlF

= +5 Vdc
= Gnd

VCCI " VCC2
VEE 1 " VEE2

-The 120,0 ohm re~istor and the scope termination impedance constitute a 25: 1 attenuator
probe. Coax.shall be CT-070-50 or equivalent.

10

Vin. INP'UT VOLTAGE (VOLTS)

FIGURE 7
18

~
>0
Z

•

L: Micro Metal Toroidal Core #T44-10.
4 turns of No. 22 copper wire.

17

I

Vin

16

14

w

13

0

a:

/

..

I:l

12

I:l

11

0

10

~o

9.0
8.0

/

/

C

51l F

i/
1.0

2.0

pF

1200'

1 k

/

o

= 500

10

/

II.

,

. . --1-

15

w
:l

3.0

4.0

5.0

6.0

7.0

8.0

9.0

I-=

MV1401
VCCI
YEE 1

12

5

'T'-= O.IIlF

= VCC2 = +5 Vdc
= VEE2 = Gnd

..L

*The 1200 ohm resistor and the scope termina-

'10

tion impedance constitute a 25:1 attenuatar
probe. Coax shall be CT -070-50 or equivalent.

Vin,. INPUT VOLTAGE (VOLTS)

FIGURE B
190
N

I

~
>-

150

w
:l

140

0

UJ

a:
II.

..
0

80

I:l

,-

~o

100
90

,

..

"O;f'

>

,

./

60
1.0

---

2.0.

3.0

V

4.0

10

g

+5 Vdc

I

~"'"
I
I

L

:;']

/

./

-=

'=

= VEE2 = Gnd

VEEI

i'g

/

. .1

70
50
.0

5 P F f 51 k

1/

1/

Veel "" VCC2

0.1.J:::""
I'FI

./

130
120
110

I:l

5 turns of No. 20 copper wire.
Von

./

..160

0

z

L: Micro Metal Torodial Core #T30-22,

180
170

12

I.
I

I

I

I
I
L

I
_ _ _ _ _._ _ ....I

0
3'

fo~,t

5

~.O._IIlF
5.0

.6.0

7.0

8.0

9.0

Vin. INPUT VOLTAGE (VOLTS)

4-6

10

·The 1200 ohm resistor and the scope termina·
tion impedance constitute a 25: 1 -attenuator
probe. Coax shall be CT-070·50 or equival,m.

MC1648/MC1648M

Typical transfer characteristics for the
oscillator in the voltage controlled mode are
shown in Figures 6, 7, and 8. Figures 6 and 8
show transfer characteristics employing only
the capacitance of the varactor diode (plus the
input capacitance of the oscillator, 6 pF typical). Figure 7 illustrates the oscillator operating
in a voltage controlled mode with the output
frequency range limited. This is achieved by
adding a capacitor in parallel with the tank
circuit as shown. The 1 kU resistor in Figures 6
and 7 is used to protect the varactor diode
during testing. It is not necessary as long
as the dc input voltage does not cause the diode
to become forward biased. The larger-valued
resistor (51 kU) in Figure 8 is required to
provide isolation for the high-impedance
junctions of the two varactor diodes.
The tuning range of the oscillator in the
voltage controlled mode may be calculated as:

Capacitors (C1 and C2 of Figure 4) should
be used to bypass the AGC point and the VCO
input (varactor diode), guaranteeing only
dc levels at these points.
For output frequency operation between
1 MHz and 50 MHz a 0.1 }.IF capacitor is sufficient for C1 and C2. At higher frequencies,
smaller values of capacitance should be used;
at lower frequencies, larger values of capacitance. At high frequencies the value of bypass
capacitors depends directly upon the physical
layout of the system. All bypassing should be
as close to the package pins as possible to
minimize unwanted lead inductance.
The peak-to-peak swing of the tank circuit
is set internally by the AGC circuitry. Since
voltage swing of the tank circuit provides the
drive for the output buffer, the AGC potential
directly affects the output waveform. If it is
desired to have a sine wave at the output of
the MC1648, a series resistor is tied from the
AGC point to the most negative power potential (ground if + 5.0 volt supply is used, -5.2
volts if a negative supply is used) as shown in
Figure 10.
At frequencies above 100 MHz typ, it may
be desirable to increase the tank circuit peakto-peak voltage in order to shape the signal
at the output of the MC1648. This is accomplished by tying a series resistor (1 kU minimum) from the AGC to the most positive
power potential (+ 5.0 volts if a + 5.0 volt supply is used, ground if a -5.2 volt supply is
used). Figure 11 illustrates this principle.

f max = .JCO(max) + Cs
fmin
where fmin

=

.JCo(rr,in) + Cs
1

21T.JU Co (max) + CS)
Cs = shunt capacitance (input plus external
capacitance) .
Co = varactor capacitance as a function
of bias voltage.
Good RF and low-frequency bypassing is
necessary on the power supply pins. (See
Figure 2.)

APPLICATIONS INFORMATION

(preferable over RF switching with a multiple
crystal system), and a broad range of tuning (up
to 150 M Hz, the range being set by the varactor
diode).
The output frequency of the synthesizer
loop is determined by the reference frequency
and the number programmed at the programmable counter; f out = Nfref. The channel
spacing is equal to frequency (fref).
For additional information on applications
and designs for phase locked-loops and digital
frequency synthesizers. see Motorola Application Notes AN-532A, AN-535, AN-553, AN564 or AN594.

The phase locked loop shown in Figure 9
illustrates the use of the MC1648 as a voltage
controlled oscillator. The figure illustrates
a frequency synthesizer useful in tuners for
FM broadcast, general aviation, maritime and
landmobile communications, amateur and
CB receivers. The system operates from a single
+5.0 Vdc supply, and requires no internal translations, since all components are compatible.
Frequency generation of this type offers
the advantages of single crystal operation,
simple channel selection, and elimination of
special circuitry to prevent harmonic lockup.
Additional features include dc digital switching

4-7

•

MC1648/MC1648M

FIGURE 9 - TYPICAL FREQUENCY SYNTHESIZER APPLICATION

VoltageControlled
Oscillator
MC1648

Phase

Detector
MC4044

1--'--"-'

f out

f out '" Nfref

where
N '" Np. P + A

N = Np. P + A

II

Figure 10 shows the MC1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To obtain a sine
wave at the output, a resistor is added from the AGC
circuit (pin 5) to VEE.
.
Figure 11 shows the MC1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To extend the
useful range of the device (maintain a square wave output
above 175 MHz), a resistor is added to the AGC circuit at
pin 5 (1 k-ohm minimum).

Figure 12 shows the MC1648 operating from +5.0 Vdc
and +9.0 Vdc.power supplies. This permits. a higher voltage
swing and higher output power than is possible from the
MECL output (pin 3). Plots of output power versus total
collector load resistance' at pin 1 are given in Figures 13
and 14 for 100 MHz and 10 MHz operation. The total
collector load includes R in parallel with Rp of L1 and
Cl at resonance. The optimum value for R at 100 MHz is
approximately 850 ohms.

FIGUR E 10 - METHOD OF OBTAINING ASINE-WAVE OUTPUT

FIGURE 11 - METHOD OF EXTENDING THE USEFUL RANGE
OF THE MC1648 ISQUARE WAVE OUTPUT)

+5.0 Vdc

+5.0 Vdc

1--+--

:: 3

=>

o
0: 2

w
~

\

_12

(I)

:;

0: 10
~

\

E

V

=>

11.

l-

r\

\

V '"

8

l-

1\

\

6

'\

=>

0

0:

4

w

~

o

0

11.

11.

2
0

100

1000

10,000

10

TOTAL COLLECTOR LOAD (ohms)

100

1000

TOTAL COLLECTOR LOAD (ohms)

4-9

10, 000

II

MC1650/MC1651
DUAL AID CONVERTER

The MC1650 and the MC1651 are very
high speed comparators utilizing differential
amplifier inputs ·to sense analog signals above
or below a reference level. An output latch
provides a unique sample-hold feature. The
MC1650 provides high impedance Darlington
inputs, while the MC1651 is a lower impedance
option, with higher input slew rate and higher
speed capabil ity.
The clock inputs (Ca and Cb) operate from
MECL III or MECL 10,000 digital levels. When
Ca is at a logic high level, QO will be at a logic
high level provided that V 1
V 2 (V 1 is more
positive than V2)' 00 is the logic complement
of QO. When the clock input goes to a low logic
level, the outputs are latched in their present

Vl. (10) 6
2 (6) aD

V2. (9) 5

C. (8) 4

3 (7) 00

Vlb (16) 12

14 (2) al

V2b (15) 11

Cb (1) 13

15 (3) 01

>

VCC = +S.O v = Pin 7,10· (11), (14)
VEE - -S.2 V - Pin 8 (12)
Gnd = Pin 1,16 (4) (S)
•

Po

= 330

,.

tpd

= 3.5 nstyp (MC1650)
= 3.0 nstyp (MC16S1)

•

Input Slew Rate = 350 Vllls (MC1650)
= 500 V/ILs (MC1651)

•

Differential Input Voltage:
5.0 V (_30°C to +85 0 C)

•

Common Mode Range:
-3.0 V to +2.5 V (_30°C to +S50C) (MC1651)
-2.5 V to +3.0 V (_30°C to +S50C) (MC1650)
Resolution: :e:;;;20 mV (-30o C to +8SoC)

•

mW typ/pkg (No Load)

state.
Assessment of the performance differences
between the MC1650 and the MC1651 may be
based upon the relative behaviors shown in
Figures 4 and 7.

TRUTH TABLE

n

•
DrivBs 60
lines
Number at end of terminal de~otes pin number for L package (Case 620).
Numbsr in parenthesis denotes pin number for F package (Case 650).

rp =

II

I MC1650 Inputsl

~~~=----..--

----

C

Vl, V2

00n+1

H

vl>V2

H

L

H

vl 

aO n

aOn



Don't Care

CIRCUIT SCHEMATIC,
1/2 of Device Shown

(Both Device.)

A

~--+------ B
~-+-----+--------C
B--Vl (10)6

C----+--+-~~-_+

V2(9) 5~~~------_+----------~
\ - - - - - - - --0

,--_-=;-~----E

I'---'-'--;=:::::!..........---'--MC1651 Inputsl
- -- A
~------I!
~-----+----------C

D---------~--~--~--~----~~

Vl (10) 6

}-------D

4

CloCk

---E

4-10

(S)

QOn+1

~
I-~~-~'.
"~I~.~~!lr~·

~

..

(Volts)

@Test
Temperatur,

F SUFFIX

L SUFFIX
CERAMIC PACKAGE
CASE 620

s("')
....

TEST VOLTAGE VALUES

CERAMIC PACKAGE

CASE 650

VIHmax
-30 o e -0.875

VILmin VIHAmin VILAmax
-1.890
-1.180
-1.515

VAl
+0.020

VA2
-0.020

+25 0 C -0.810

-1.850

-1.095

-1.485

+0.020

-0.020

+85 0 C -0.700

-1.830

-1.025

-1.440

+0.020

-0.020

VIHmax

VILmin

VIHAmin

VA31 VA41 VAS

I VA6

@

See Note

VCC® VEE ®
+5.0

-5.2

+5.0

-5.2

+5.0

-5.2

ELECTRICAL CHARACTERISTICS
-30 D e
Symbol

Characteristic

Min

+2SoC

Min

Max

+8SoC

Min

Max

POSitive

-

ICC
IE

Negative
I nput Current

-

-

I nput Leakage Current
MC1650
MC1651

-

-

-

-

-

-

-

-

-

-

-

Clock Input Current

linH

Logic "1" Output Voltage

VOH

-1.045

I

-

I

I VOL

IVOHA

IVOLA

LogiC "0" Threshold

Voltage@

NOTES-

CD

All data

IS

10
40

-

-

-

-

7.0
10

-

-

-

-

I

-1.890

350

-

-0.875

I

for 1/2

I

-0.960

I

-

-0.810

I

-

-0.890

I

-0.700

I

VA6

I

Gnd

4,13

-

-

-

-

-

-

-

-

6,12
6,12

-

-

-

-

-

-

-

1,5,11,16
1,5,11,16

4

13

-

-

12

-

6

-

-

-

1,5,11,16

4

13

-

-

12

-

-

-

6

-

1,5,11,16

,uAdc

4

13

-

-

6,12

-

-

-

-

-

1,5,11,16

Vdc

4,13

-

-

-

6,12

-

-

-

-

-

1,5,11,16
1,6,12,16
1,16
1,16
1,5,11,16
1,6,12,16
1,16
1,16

I

I -1.650 I -1.850 I -1.620 I -1.830 I -1.575 I

-1. 065 1

-

I

-

0 980
1- .

I -1.630 I

Me 1650 or MC1651,

(2) These tests done In order Indicated.

o

VA5

-

I
Vdc

I

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

I

-

-

4,13

-

I

I -0.910 I

-

1-1.600

I

-

-

1-1.555

I
I

Vdc

Vdc

except data marke-d C") which refers to the entire package.

See Figure 5.

MaXimum Power Supply Voltages (beyond which deVice life may be Impaired):

IVEEI + Ivccl;;;'12 Vdc.

II

I

I!

I

-

I
0)

6,12

5,11

-

-

-

-

-

-

5,11

-

-

-

-

-

-

-

-

-

-

-

-

-

-

4

-

6,12

-

6,12

-

-

-

-

-

-

-

-

-

-

-

5,11

-

-

6,12

-

-

-

5,11

-

-

-

-

-

-

6,12

-

-

6.12

-

5,11

-

5.11

5,11

-

6,12
-

6,12

-

6,12

-

5,11

5,11

6,12

1,5,11,16
1,6,12,16
1,16
1,16
1,5,11,16
1,6,12,16
1,16
1,16

-

-

1,5,16

-

-

-

-

-

-

6,12

5,11

-

-

-

-

-

5,11
-

-

-

-

4

6

-

-

13

4

-

6

-

-

-

!

-

4

-

-

-

-

-

-

6
6

-

4

-

-

-

4

6

-

~

-

-

-

-

-

-

-

13

-

5,11

-

-

Voltage@

VA4

/-lAde

-

Logic" 1" Threshold

VA3

.u Ade
-

IR

LogiC "0" Output Voltage

VA2

4,13

-

25'
55"

lin

MC1650
MC1651

~

VAl

mAde

Power Supply Dram Current

.j>.

VILAmax

-

6

-

-

4

-

4

-

-

6
6

-

-

-

-

-

o
S

("')
....
....
(j)
(jI

TEST VOL TAGE APPLIED TO PINS LISTED BELOW

Unit

Max

(j)
(jI

!

1,5,16

~

•

MC1650/MC1651
SWITCHING TEST VOLTAGE VALUES
(Vohsl

@Test
Temperature

VRl
-30°C 1+2 .000
+250 C 1+2 .000
+850 C +2.000

-30°C
Characteristic

Svmbol

Switching Times
Propagation Delay
150%10 50%1
V-Input

Clock Aperture@

2.:1
2.0

Min

5.0
4.7

2.0
2.0

Ma.

5.0
4.7

2.0
2.0

5.7
5.2

+2.00

+7.00

-3.20

VRl to V2. Vx to Clock. Pl to v,. or,
VA2 to V2. Vx to Clock. P2 to V,.
or, VA3 to V2. Vx to Clock, P3 to V,.
VRl to V2. P, to V, and P4 to Clock,
or, VR' to V,. P, to V2 and P4 to Clock.,

-

-

2.5

-

-

-

ns

-

-

-

-

-

1.0
1.0

3.5
3.0

1.5
1.0
1.0

3.5
3.0

1.0

3.8

1.0

3.3

ns
ns
ns

t-

VCCG) VEECD
+7.00
-3.20
+7.00
-3.20

(See Figures 1-3)

Unit

tap

Fall Time 110% to 90%1

VXX
+2.00
+2.00

Conditions

+850 C

Ma.

tsetup

t+

0

+250 C
Min

ns

Rise Time 110% to 90%1

NOTES:

Ma.

VR3

tpd

Clack@
Clock Enable@

Min

Vx
+1.040
See Note@ +1.110
+1.190
VR2

VRl to V2, Pl to Vl, P4 to Clock
VRl to V2, Vx to Clock, Pl to Vl·

Maximum Power Supply Voltages (beyond which device life rna·" be impaired:

IVccl+ IVEEI~12Vdc.

.

(3) Unused clock inputs may be tied to ground.

® See Flgure3.

FIGURE 1 - SWITCHING TIME TEST CIRCUIT@ 25 0 C

V out to
Vin to Channel A

Channel B

r-

PI

I

CC Gnd - - - ,

~+-~~~I~
I

I__..J

Q~-+

~; \
01'---+----'

-i----""'Ic

?=i-_.J

I

I

L__

1 lo.1

jLF

VeE =
-3.2 Vdc

Note: All power supply and logic levels are
shown shifted 2 volts positive,

50-ohm termination to ground located in each
scope channel input.
All input and output cables to the scope are
equal lengths of 50-ohm coaxial cable.

4-12

MC1650/MC1651

FIGURE 2 - SWITCHING AND PROPAGATION WAVEFORMS@ 2SoC

The pulse levels shown are used to check ae parameters
over the full common-mode range.

v-

I nput to Output

Test pulses:

t+. C

= 1.5 ±O.2 ns (10% to 90%)

f"" 5.0 MHz
50% Duty Cycle

TEST PULSE LEVELS

PI

:

P2

P3

MC1650

MC1651

MC1650

MC1651

MC1650

MC1651

+2.100 V

+2.100V

+5.000 V

+4.S00V

-0.300 V

-0.800 V

VIH
VA

+2.000 V

+2.000 V

+4.900 V

+4.400 V .

-0.400 V

-0.900 V

VIL

+1.900 V

+1.900 V

+4.800 V

+4.300 V

-0.500 V

-1.000V

Clock to Output
~---VIH

P1

+2.100 V

VR +2.000 V

'------.J'+----VIL + 1.900 V

~"'-t------

+1.110 V

P4

C

'------+0.310 V

Q _ _ _..J

P4: t+. C == 1.5

± 0.2 ns.

4-13

•

MC1650/MC1651

FIGURE 3 - CLOCK ENABLE AND APERTURE TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

Vee

Vin to Channel A

= +7.0

VXX

= +2.0

V out to Channel B

o.:~c JjdC o.1

IlFI
10

r-

-=

IIlF

7

1 1aF"

Vee

Vino--~'---~_+-i+

G-;\d---,
.

VA

D

I
"""-+----'
I
_~-TI---.
0
I

0

I

o---~------+_--~c

I

!~- i
DO

I
I 50
leo:
I
I
I
L ___VEE _ _ --l
r-1 1 ]il
0 VEE - -3.2 Vdc

-=

0.11lF

50-ohm termination to ground located
in each scope channel inpu.t.
.

All input and output cables to the scope
are equal lengths of 50-ohm coaxial cable.

•

An~log

Signal Positive and Negative Slew Case

VR+ 100 mV ""+2.100V

VinNegative - - - - . . " ,

,
Vin Positive - - - - '

.
VA - 2.000 V
\ _ _ _ _ _ _ _ _ _ _ _ _ _ V R - 100 mV = +1.900 V
Clock Enable

Time

'

VIH -+1.110V

" - - - - - - - - V I L - +0.310 V

,-----··1"

50%

Q

+ ____

Positive _ _ _ _

o Negative

V

~

_ F ..... '"

-~--V~---

--+-r.-.--50""""'%%y_r--~----

"0"

"1"

!--t d--1\'-----"o"
p

Clock enable time = mini mum time between analog and clock
signal such that output switches, and tpd (analog to Q) is not
degraded by more than 200 ps.
- - - - - - Clock aperture time = time difference between clock enable time
and time that output does not switch and V is less than_ 150 mV.
Note: All power supply and logic levels are
shown shifted 2 volts positive.

4-14

MC1650/MC1651

FIGURE 4 - PROPAGATION DELAY Itpdl versus
INPUT PULSE AMPLITUDE AND CONSTANT OVERDRIVE

Test Circuit

,-------1
Vino--1~---;~t>T
+
V ref

o----4--.....---4~~

I
i

I

Q .....--'-I---4~-

~

I-

:::>

o
d

F~=i==I!!!=I==''''''*,,==-f'''=~~+----l------j Logic "0"
-2~-~-~~-~--r--~-~-~~~.

-20

-15

-10

-5

5

10

Vref
Vin. DIFFERENTIAL INPUT VOLTAGE (m VOLTS)

4-17

15

20

..

MC1650/MC1651

FIGURE 7 - OUTPUT VOLTAGE SWING versus FREQUENCY

{AI Test Circuit

r-------,
rv

V1
V2

.J,.

I

~

-'

I

I

Q

I

I
I
I

Y:t Device

I

V1H

D

C-

O

I

L ______

Q

t

50

50
2.0 Vdc

~

{SI Typical Output Logic Swing versus Frequency

0,850

MC1651

'-

'~
0

2: 0,650

...
~
=>
0

,I"-

0

!"I\..'\:

~

\.

~

\ \.
\ \ '\1\..
\
\ \ \\

"

0,450

""
~

...

~

r'-.

0.250

""
~

75\

50

100\

200

pear-

\ Input Voltage

0,050

mV

10

20

30

70

50

leak to

100

200

~~o
~

300

FREQUENCY (MHz)

0,850

-

MC1650

~

~
~ 0,650

...~
...i5

.........

-..... ......,
.......

",

..;;;~

:--....

r-.....

"-

......

"-

r.......

0.450

i'..

"~
~ 0,250

"'-"''\."" "'''\.'\.\
'\. "-

50

'"~

75' 100'
200\ \~o
InputVollagek·~

mV Peak to Peak

0,050
10

\1\..

'\. I\. \

"-

20

30

50

70

FREQUENCY (MHz)

4-18

100

200

300

MC1650/MC1651

.

.'

,

FIGURE 8 - INPUT CURRENT versus INPUT VOLTAGE'

TEST CIRCUIT

-2.0 Vdc

..

-,5.2 Vdc

Typical MC1650 (Complementary Input Grounded'

I
5


I

-30De

I-

Typical MC1651 (Complementary Input Grounded'
30r--'--~---r--'---~--'--'--~---r--,

l

-~

I-

~ 15~~---+--~--1---~r_'-r--~~~~~t~~~

-

0

I-

-'"~

1"""'-

~

-r.:'"

~

~

~

j

-2

!

,(

-I-"
-"",

---

101-~---+--+--1---~~r-~~~--+--~

~~
5~-r--+--+--1--~i--~-r--+-~~~

o~~_~~~~'~~~~~

-5
-2.5

201--I---+--+--+--+---t-'\~~~···~··f.-~··--t-~
••••••••
+25 0 C

-1

+1

+2

+2.5

-5 """, ...

-2.5

-2

-1

Vi., INPUT VOLTAGE (VOLTS'

Vi.,INPUT VOLTAGE (VOLTSI

4-19

2

2.5

MC1654
BINARY COUNTER

The MC1654 is a four-bit counter capable of
divide-by-two, divide-by-four, divide-by-eight.
or divide-by-16 functions. When used independently, the divide-by-16 section will toggle
at 325 MHz typically. Clock inputs trigger on
the positive-going edge of the Clock pulse.
Set and Reset inputs override the Clock,
allowing asynchronous "set" or "clear." Individual Set and common Reset inputs are provided, as well as complementary outputs for the
first and fourth bits. True outputs are available
at all bits.

TRUTH TABLE
INPUTS
SO

SI

S2

S3

Cl

C2

OO~

1

a

a

a

a




OUTPUTS

R

1

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

= Don t

1

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

1

1

a
a
a·
a
a
a
a
a
a
a

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

,0

a
a
a
a
a
a
a

1



w_
e N
>-!

.~

>-

~

z::;
~a:

-

a:
u.

1.0

1000

0",

10

w
:J

aw

VCC = +5.2 Vdc
VEE - 0;.0 Vdc

0

==

IU~lx _I)dv

a:

':,i

DC CONTROL INPUT
1.0

10

1000

10,000

FIGURE 5 - FREQUENCY·CAPACITANCE PRODUCT ver.u.
CONTROL VOLTAGE (Vcx)

II

li0.

N

r

:2

....

U

e

1500

o

1400

a:

1300

w
U
Z

1100

0.

«
....

o«
0.

«
~

o>z

w

•

Desired

V

vex_

~

/

/

900

./

BOO

/

700

-

600
500

'x
u

at

/

1000

400

u.

Frequency-Capacitance Product

Desired Frequency (MHz)

1200

w
a:

a

cx(pF}=

,/

:J

lOa

f, OPERATING FREQUENCY (MHz)

'\.

lOa

:J

= 4.0 Vdt"i

llLllUlL._LLU

10
0.1

'\.

11II111
10

.-

u.

/~,

de

V,C11,,~i~ Vd,C
O. 1
1.0

lOa

aw

Vex - 0 Vdc

./

V

300

-2.0

/"

-1.B

-1.6

-1..4

-1.2

-1.0

-O.B

-0.6

~o

Vcx, INPUT VOLTAGE (Vde)

4-25

-0.4

-0.2

a

MC1660
DUAL 4-INPUT GATE

VCCl = Pin 1 (5)
(8)

4B§ = t i = A
x,

(9)

5

(10)

6

(11)

7

c

y

VCC2 = Pin 16 (4)
3

(7)

2

(6)

0

VEE = Pin 8 (12)
tpd = 0.9 ns typ (510-ohm load)
= 1.1 nstyp (50-ohm load)

(14)10~
(15) 1 1 ,

14 (2)

(16) 12

15 (3)

(1) 13

PD':' 120 mW tVP/pkg (No load)
Full Load Current, I L = -25 mAdc max,

'

X=A+B+C+D
Y=A+B+C+D

•

L SUFFIX

F SUFFIX

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 650

Numbers at ends of terminals denote pin numbers for L package
Numbers in parenthesis denote pin numbers for F package

+25 0 C

-30°C

+85 0 C

Characteristic

Symbol

Min

Max

Min

Max

Min

Power Supply Drain Current

IE

-

-

-

28

-

-

mAde

linH

-

-

-

350

-

-

~Adc

0.6
0.6

1.7
1.5

0.6
0.6

1.9
1.7

0.6

2.1

0.6

2.3

Input Cu rrent

Max

Switching Times

Unit

ns'

Propagation Delay

t+t-+

0.6
0.6

1.8
1.6

Rise Time, Fall Time
(10% to 90%)

t+,t-

0.6

2.2

-

4-26

ns

MC1662
QUAD 2-INPUT NOR GATE

::::~2

(61

VCC1 = Pin 1 (5)

67~ 3
(111~(7)

(101

(14110~

VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

14 (21

(151 11

(16112~
(11 13

tpd = 0.9 ns tYP (51 O·ohm loadi
= 1.1 nstyp (50·ohm load)
15 (31

PD = 240 mW tYP/pkg (No load)
Full Load Current, I L = -25 mAdc max

X=A+B

L SUFFIX
CERAMIC PACKAGE
CASE 620

•

F SUFFIX
CERAMIC PACKAGE
CASE 650

Number at end of terminals denotes pin number of L package.
Number in parenthesis denotes pin number for F package.

+2SoC

-30°C

+8SoC

Characteristic

Symbol

Min

Max

Max

Max

Min

Max

Unit

Power Supply Drain Current

IE

-

-

-

56

-

-

mAdc

linH

-

-

-

350

-

-

MAde

Propagation Delay

t+:t-+

0.6

1.6

0.6

1.5

0.6

0.6

1.8

0.6

1.7

0.6

1.9

Rise Time, Fall Time
(10% to 90%)

t+,r

0.6

2.2

0.6

2.1

0.6

2.3

Input Cu rrent

ns

Switching Times

4-27

.

1.7
ns

MC1664
QUAD 2-INPUT OR GATE

(8)
(9)

(10)
(11 )

4~
b
2

(6)

76~ 3

(7)

VCC1 = Pin 1 (5)
VCC2 = pin 16 (4)
VEE = Pin 8 (12)

(14) 1 O = : [ > - (2)
(15) 11
14

tpd = 0.9 ns typ (510-ohm load)
= 1.1 ns typ (50-ohm load)
Po = 240 mW typ/pkg (No load)

(16) 1 2 = : [ > - (3)
,(1) 13
15

Full Load Current, I L = -25 mAdc max

X=A+8

•

L SUFFIX
CERAMIC PACKAGE
CASE 620

F SUFFIX
CERAMIC PACKAGE
CASE 650

Number at end of terminals denotes pin number of L package.
Number in parenthesis denotes pin number for F package.

+25 0 C

-30°C

+85 0 C

Characteristic

Symbol

Min

Max

Min

Max

Min

Power Supply Drain Current

IE

-

-

-

56

-

-

mAde

linH

-

-

-

350

-

-

/.lAde

t++
t--

0.6
0.6

1.6
1.8

0.6
0.6

1.5
1.7

0.6
0.6

1.9

t+,c

0.6

2.2

0.6

2.1

0.6

2.3

I nput Current

Max

Switching Times
Propagation Delay
Rise Time, Fall Time
(10% to 90%)

Unit

ns

4:28

1.7
ns

MC1666
DUAL CLOCKED R-S FLIP-FLOP

(9)

(11)
(8)

sua
7

C

4

R

a

2

(6)

3

(7)

(16) 1 2 u a15(3)
(14) 9
C
(1)13

S

0
1

R

a

TRUTH TABLE
R
C


0

a

0
1
1
1






a
a
a
a

an

1

1
1

1

a
1



1
1
I/>


a

• ·Output state not defined

VCC2 = Pin 16 (4)
VEE = Pin 8 (12)

1

..aa

tpd = 1.6 ns typ (510-ohm load)
= 1.8 ns typ (50-ohm load)

1

Po = 220 mW typ/pkg (No load)

¢ = Don't Care

Number at end of terminal denotes pin number for L package
Number in parenth~sis denotes pin number for F package

+25 0 C

-30°C
Characteristic
Power Supply Drain Current
Input Current
Data, Set, Reset
Clock
Switching Times
Propagation Delay
Clock
Set, Reset

+85 0 C

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

55

-

-

mAde

-

-

-

370
225

-

-

/LAde

linH

ns

,

tpd

"-

1.0
1.0

1.1

2.7
2.5

1.0
1.0

2.5
2.3

1.1

2.8
2.7

Rise Time (10% to 90%)

t+

0.8

2.8

0.9

2.5

0.9

2.9

ns

Fall Time (10% to 90%)

t-

0.5

2.4

0.5

2.2

0.5

2.6

ns

4-30

MC1670
MASTER-SLAVE
FLIP-FLOP

(9)

5

S

Master
slave
construction
renders the
MC1670 relatively insensitive to the shape of
the clock waveform, since only the voltage

~

( 11l

7C:n
(14) 9 C2

f"'o--Q

(15) 11 0

~Q3(7)

(8)

4

levels at the clock inputs control the transfer of
information from data input (D) to output.
When both clock inputs (e1 and C2) are
in the low state, the data input affects only the

2 (6)

"Master" portion of the flip·flop. The data
present in the "Master" is transferred to the
"Slave" when clock inputs (C1 "OR" C2)
are taken from a low to a high level. I n other

~

R

words, the output state of the flip·flop changes
on the positive transition of the clock pulse.
While either C1 "OR" C2 is in the high
state, the "Master" (and data input) is disabled.
Asynchronous Set (S) and Reset (R) over·
ride Clock (C) and Data (D) inputs.

TRUTH TABLE

R

S

0

C

'"

'"
'"
'"

L

H

H

'L

H

H

L

L

'L"

L

L

L

L

L

L

'"

L

L

H

L

L

H

L

L

H

Q n +l

H

L

VCC1 = Pin 1(5)
VCC2 = Pin 16(4)
VEE = Pin 8(12)

Power Dissipation = 220 mW typical (No Load)
f T09 = 350 MHz typ

N.O.

L

on

H

On

L

On

H

On

J

L

J

H

f/J '"

Don't Care
NO"" Not Defined

C=Cl +C2

L SUFFIX

F SUFFIX

CERAMIC PACKAGE

CERAMIC PACKAGE

CASE 620

CASE 650

Number at end of terminal denotes pin number .for L package
Number in parenthesis denotes pin number for F package

+25 0 C

-30°C
Characteristic
Power Supply Drain Current
Input Current

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

48

-

-

mAde

-

-

550
250
270

-

-

-

-

-

1.0

2.7

1.1

2.5

1.1

2.9

!LAdc

linH

Set, Reset
Clock
Data
Switching Times
Propagation Delay

+85 0 C

Symbol

-

ns
tpd

Rise Time (10% to 90%)

t+

0.9

2.7

1.0

2.5

1.0

2.9

ns

Fall Time (10% to 90%)

t-

0.5

2.1

0.6

1.9

0.6

2.3

ns

tS"1"
ts"o"

-

-

-

-

-

ns

-

0.4
'0.5

-

-

tH"1"
tH"O"

-

-

0.3
0.5

-

-

-

ns

-

fTog

270

-

300

-

270

-

MHz

Setup Time
Hold Time
Toggle Frequency

4-31

•

•

MC1670

FIGURE 1 - TOGGLE FREQUENCY WAVEFORMS

Clock Input
R
"

300
MHz-max

114

I III I

~.

I I

I II

--- +0.71 VBias

I I

-+0.31 V

I

lil~
Qcra
Output

I
II (4

~

p;j~

~

I

I

600 mV min

OR

2. The device ceases to toggle (divide by two).

~

RIll

~

-r

The maximum toggle frequency of the MC1670
has been exceeded when either:
1. The output peak·to-peak voltage swing falls below
600 millivol ts,

FIGURE 2 - MAXIMUM TOGGLE FREQUENCY (TYPICAL) .

U
0



+0.450
+0.400
+0.350
+0.300
+0.250
175

= 25 0 e
= +2.0 Vdc
= -3.2 Vdc

r--....

Figure 2 illustrates the variation in toggle
frequency with the dc offset voltage (VBias)
of the input clock signal.
'Figures 4 and 5 illustrate minimum clock
pulse width recommended for reliable operation
of the MC1670.

\
./
-I"'""

=+0.500

iii

TA
Vee
VEE

225

275

325

375

425

fTog (MHz)

FIGURE 3 - TYPICAL MAXIMUM TOGGLE FREQUENCY
versus TEMPERATURE
W

...J

,,"

400

ON

1-:1:

:;;~ 350

~~

~a
j(w

--

-

i--'"

x~

300

~[[

Ell.

'"a
.t'

250
-30

o

25

50

85

T A • AMBIENT TEMPERATURE (aC)

Note: All power supply and logic levels are
shown shifted 2 volts positive.

4-32

MC1670

FIGURE 4 - MINIMUM "DOWN TIME" TO CLOCK
OUTPUT LOAD = 50n

>

r-

CJCK

\"

V. r-. r---/
V

\

/

wEi

,,>
uE
...J-

Vl~

Q or

a

1

\) t'--

-

II

1.0 ns/OIV.

FIGURE 5 - MINIMUM "UP TIME" TO CLOCK
OUTPUT LOAD = 50n

I_

V\=
II"

.I

W
...J

g

Q or Q

1 7
I V
1 .J \
1.0 ns/DIV.

4-33

C~K

-

•

MC1672
TRIPLE 2-INPUT
EXCLUSIVE-OR GATE

(8)

(9)

3~X

5~2(6)

(16)13~·
(10)

6~14(2)

(14)11~
(11)

7

15 (3)

B

L SUFFIX
CERAMIC PACKAGE
CASE 620

VCC1 = Pin 1 (5)
V CC2 = Pin 16 (4)
VEE = Pin 8(12)

•

tpd = 1.1 ns typ (510-ohm load)
= 1.3 ns typ (50-ohm load)
P D = 220 mW typ/pkg
Full Load Current, I L = - 25 mAdc max

F SUFFIX
CERAMIC PACKAGE
CASE 650

Number at end of terminal denotes pin number for L package_
Number in parenthesis denotes pin number for F package.

-30 D e·
Characteristic

+85 0 e

+25 D e

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

55

-

-

mAde

-

-

350

linH

-

-

-

t++, t-+
t+-,t-t++,t-+
t+-,t--

-

2.0
2.1

-

1.8

-

2.3
2.4

2.5
2.5

2.3
2_3

-

Rise Time (10% to 90%)

t+

-

2.7

-

2.5

-

2.9

ns

Fall Time (10% to 90%)

t-

-

2.4

-

2.2

-

'2.6

ns

Power Supply Drain Current
Input Current

MAde
A Inputs
B Inputs

Switching Times
Propagation Delay

linH

270

ns
A Inputs {
B Inputs {

4-34

1.9

-

2.8
2.8

MC1674
TRIPLE 2-INPUT
EXCLUSIVE-NOR GATE

(8)

(9)

3~X 2

5

(6)

B

(16)13~
(10)

6~14(2)

(14) 11

(11)

==0[>-----

7

15 (3)

B

L SUFFIX
CERAMIC PACKAGE
CASE 620

VCC1 ~ Pin 1 (5)
VCC2 ~ Pin 16(4)
VEE ~ Pin 8(12)

tpd

~
~

1.1 ns typ (510-ohm load)
1.3 ns typ (50-ohm load)

Po ~ 220 mW typ/pkg
Full Load Current, IL ~ -25 mAde max

•

F SUFFIX
CERAMIC PACKAGE
CASE 650

Number at end of terminal denotes pin number for L package.
Number in parenthesis denotes pin number for F package.

-30°C
Characteristic

+85 0 C

+25 0 C

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

55

-

-

mAde

linH

-

-

-

350

-

-

linH

-

-

-

270

-

-

t++, t-+
t+-,t-t++, t-+
H-, t--

-

-

-

1.8
1.9
2.3
2.3

-

-

2.0
2.1
2.5
2.5

-

2.3
2.4
2.8
2.8

Rise Time (10% to 90%)

t+

-

2.7

-

2.5

-

2.9

ns

Fall Time (10% to 90%)

t-

-

2.4

-

2.2

-

2.6

ns

Power Supply Drain Current
Input Current

}.lAde
A Inputs
B Inputs

Switching Times
Propagation Delay

ns
A Inputs{
B Inputs {

4-35

-

•

MC1678
BI-QUINARY COUNTER

The MC1678 is a four-bit counter capable of

provided, as well as complementary outputs
for the first and fourth bits.
True outputs
are available at all bits.
R ~ 2.40
DC I nput Loading Factor
Cl ~ 0·.77
C2 ~ 1.23
5 ~ 1.00

divide-by-two, divide-by-five, or divide-by-10
functions. When used independently, the divideby-two section will toggle at 350 M Hz typically,
while the divide-by-five section will toggle at
325 MHz typically. Clock inputs trigger on the
positive going edge of the clock pulse.
Set and Reset inputs override the clock,
allowing as y n c h ron 0 u s "set" or "clear",
Individual Set and common Reset inputs are

50 14

DC Output Loading Factor
Power Dissipation

f Tog

51

00 13

10

01

11

I

5
L51

L51

0
O·

~

5

L51

0-

Clock

Reset

O-

15 0 - - Cl

9

R

1

1

r

C2

I

00 12

2

,----- 51

0'1-

,-- 52

5

00'RT'-

"~tJr

Cl

Or---

r- C2

R

Or-

RTf-'

RT

03 .6

I

~

RTr-

RT

53 7

I

0'-

52

350 MHz typ

I

I

70

::=

750 m'W typ

02 4

52 3

I

r

~

=

R

aI-

t-- C2
R

I

J

C2

03 5

COUNTER TRUTH TABLES
BCD

BI-QUINARY

(Clock connected to C1

(Clock connected to C2

and 0.0 connected to C2)

R-S

and 03 connected to C 1)

COUNT

00

01

02

03

COUNT

01

02

03

00

C

R

5

0,,+1

0

L
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

0

L
H
L
H

L
L
H
H

L
L
L
L

L
L
L
L

L
L
H
H

H
H
H
H

L
L
L
L

L
L
L
H

H
L
L
L

L
H
H
H

L'
L
H
H

6
7

L
L
H
L

L
H
L
H

Qn

L
H
L
H

¢
¢
¢
¢

L
H

L

\-

L
L

H
H

8
9

H
L

H
L

L
H

H
H

1

2
3
'4

5
6
7
8

9

1

2
3
4
5

¢::= Don't Care
NO = Not Defined

COUNTER STATE DIAGRAM - POSITIVE LOGIC
Clock connected to C2

00 connected to C2

o

4-36

L
H
ND

MC1678
ELECTR ICAL CHARACTER ISTICS
+25 0 C

-30°C
Characteristic

+85 0 C

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

200

-

-

mAdc

-

-

-

1.00
0.70
0.45

-

-

Power Supply Drain Current
Input Current
Reset
C2
Set, Clock

mAdc

linH

-

Switching Times
Propagation Delay
Clock to 00, 00
C2 to 01, 02, 03,03
Set, Reset ,

-

-

-

ns
tpd
1.0
1.0
2.0

2.9
3.2
3.9

1.0
1.0
2.0

2.7
3.0
3.7

1.0
1.0
2.0

3.1
3.4
4.1

Rise Time (10% to 90%)

t+

1.0

2.9

1.0

2.7

1.0

3.1

ns

Fall Time (10% to 90%)

t-

1.0

2.8

1.0

2.6

1.0

3.0

ns

260
250

-

300
275

-

260
250

-

Toggle Frequency
00
03

MHz

fTog

-

APPLICATIONS INFORMATION
With the addition of a single gate, package,
the MC1678 will count in a fully synchronous
mode, as shown below.

50 14

1/2 MC1662

51

aD 13

10

alII

52 3

a2 4

•
53 7

03 6

Clock

15

']>----o---;c 1
R

Reset

9

o----L--LJ:=!==::!~==f===~-~
00

12

2

C2

03 5

4-37

•

MC1688
DUAL 4-5;;.INPUT

OR/NOR GATE,

(8i4"§:t .
(9)5

' . .... .

(10)6

(7)3

(6)2

(11 )7

(13)9~

(14)10

(2)14

(15)11
(16)12

(3)15

L SUFFIX

(1) 13

CERAMIC PACKAGE
CASE 620

VCC1 = Pin 1(5)
V CC2 = Pin 16(4)
VEE = Pin 8(12)
tpd = 0.8 ns typ
Po = 125 mW typ/pkg (No Load)
Output Rise and Fall Times
(10% to 90%) 1.1 ns

F SUFFIX
CERAMIC PACKAGE
CASE 650

Number at end' 01 term inal de[lotes pin n~mber for L packag~
Number in parenthesis denotes pin number for F package

+25 0 C

-30°C
Characteristic
Power Supply Drain Current
I nput Current
Switching Times
Propagation Delay
Rise Time, Fall Time
(10% to 90%)

+85 0 C

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

30

-

-

mAde

linH

-

-

-

350

-

-

'}lAde
ns

",

tpd

0.5

1.5

0.5

1.3

0.5

1.5

t+,t-

0:5

1.6

0.5

1.4

0.5

1.6

4·38

ns

MC1690
UHF PRESCALER
TYPE 0 FLIP-FLOP

(11)

7 C1

(14)

9 C2

(15)

1101

(16)

1202

-

2 (6)

L SUFFIX
CERAMIC PACKAGE
CASE 620

3 (7)

TRUTH TABLE

c

0

°n+l

L
H



On

....r....r-



L
H

On
L

C = Cl + C2

VCCI = Pin 1 (5)
VCC2 = Pin 16(4)
VEE = Pin 8(12)

F SUFFIX
CERAMIC PACKAGE
CASE 650

H

q:, ""

Don't Care

0= 01 + 02

PD = 200 mW tvp/pkg (No Load)
fTog = 500 MHz min

•

Number at end of term inal denotes pin number for L package
Number in parenthesis denotes pin number for F package

-30 o e
eha racteristic
Power Supply Drain Current
I nput Current

+2Soe

+8Soe

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

59

-

-

mAde

-

-

-

250
270

-

-

).LAde

linH

Pins 7,9
Pins 11,12

-

Switching Times

Typ

Max

tpd

-

-

-

1.5

-

-

-

t+,t-

-

-

-

1.3

-

-

-

ns

Setup Time

tsetup

-

-

-

0.3

-

-

-

ns

Hold Time

thold

-

-

-

0.3

-

-

-

fTog

500

-

500

540

-

500

-

Propagation Delay
Rise Time, Fall Time

Min

ns

(10% to 90%)

Toggle Frequency

4·39

MHz

MC1690

FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT

VCCI = VCC2
+2.0 Vdc

=

V out

Coax

.------....,-i ,

TP out

a 1""--1-------' I
V Bias =:+0.71 Vdc ()-_ _ _......

(Use High Impedance

L __ _
de Supply

All input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.

co..· --

Probe to Adjust VSias)

I

----'

0--------+
50

IO.l,."F

VEE

II

.. Non-inductive type.

-3.2 Vdc

50-ohm termination to ground located in each scope channel Input,

FIGURE 2 - TOGGLE FREQUENCY WAVEFORMS

TA = 25°C
Clock Input
500 MHz

-

+1.11 V

--- +0.71 VSias

-+0.31 V

The maximum toggle frequency of the MC1690 has been
exceeded when either:

1. The output peak-ta-peak voltage swing falls below
600 millivolts,

aorO
Output

~

600 mV min

OR
2. The device ceases to toggle (divide bV twol.

~

Note: All power supply and logic levels are shown shifted 2 volts positive.

4-40

MC1692
QUAD LINE RECEIVER

(S)

: . = : t > - - 2 (6)

(9)
(11 )

: . = : t > - - 3 (7)

(10)
(14)
(15)
(1 )
(16)

L SUFFIX

1 0 . = : t > - - 14 (2)
11

13~ 15

12

V BB

L

CERAMIC PACKAGE
CASE 620

(3)
VCCl = Pin 1 (5)
VCC2 = Pin 16 (4)

9 (13)

VEE = Pin 8 (12)·

tpd = 0.9 ns typ (51 O-ohm load)
= 1.1 ns typ (50-ohm load)

II

F SUFFIX

PD = 220 mW typ!pkg (No Load)
Full Load Current, I L = -25 mAdc max

CERAMIC PACKAGE
CASE 650

Numbers at ends of terminals denote pin numbers for L package
Numbers in parenthesis denote pin numbers for F package

-30°C

.. +85 0 C

+250 C

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

Power Supply Drain Current

IE

-

-

-

50

-

-

mAdc

Input Cu rrent

lin

-

-

-

250

-

-

MAdc

I nput Leakage Current

IR

-1.275

-

100

~

-

MAdc

VBB

- 1.375

-1.35

-1.25

-1.30

-1.20

Vdc

t-+
t+-

0.6
0.6

1.6
1.8

0.6
0.6

1.5
1.7

0.6
0.6

1.7
1.9

t+,t-

0.6

2.2

0.6

2.1

0.6

2.3

Reference Voltage
Switching Times
Propagation Delay
Rise Time, Fall Time

ns

(10% to 90%)

4-41

ns

MC1692
APPLICATION INFORMATION
The MC1692 quad line receiver IS used primarily to receive
data from balanced twisted pair lines, as indicated In Figure 1.
The line

IS

waveform picture of Figure 3 shows a 5 nanosecond pulse being
propagated down the 18 foot line. The delay time for the line
is 1.68 nslfoot.

dnven with a MC1660 ORINOR gate. The MC1660

is terminated with 50 ohm resistors to -2.0 volts. At the end of
the twisted pair a 100 ohm termination resistor is placed across

The MC1692.may also be applied as a high frequency schmitt

the differential line receiver inputs of the MC1692. Illustrated in
Figure 2 is the sending and receiving waveforms at a data rate of
400 megabits per second over an 18 foot twisted pair cable, The

tngger as Illustrated In Figure 4. This circuit has been used In excess of 200 MHz. The MC1692 when loaded Into 50 ohms will
produce an output rising edge of about 1.5 nanoseconds.

FIGURE 1 - LINE DRIVERIRECEIVER

FIGURE 3 - PULSE PROPAGATION WAVEFORMS

FIGURE 2 - 400 MBS WAVEFORMS

Sending
End

•

•1::'I

~
.

,I!!II
i, I
. II

•

.',.

11
II':!

-

2 ns/cm

Receiving
End

II

I

Sending
End

::=I

r.I

II

5 ns/cm

I

ReceiVing
End

VEE" -5.2 V

y.

MC1692

-1.3V~

FIGURE 4 - 200 MHz SCHMITT TRIGGER

9

0.01

0.01

50

500
100
VTT = -2 V

4-42

MC1694
4-BIT SHIFT REGISTER

FLlp·FLOP TRUTH TABLE
Inputs
D C R S
0 0 0 0
0 0 0 1
1 0
0 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

The MC1694 is a 4·Bit register capable of
shift rates up to 325 MHz (typical) in the
shift·right mode, accepting serial data at either
data input 01 or 02. A master reset and
individual set inputs override the clock allowing
asynchronous entry of information.

Output
Qn

a n ·1
1

0
0

1

DC Input Loading Factors
Reset = 2.5 Set = 1.0
Clock = 1.6 Data = 0.9

0

·
a

n ·1

1

DC Output Loading Factor = 70

VCC1 = 1
VCC2 = 16

0

·
1
1

=

VEE

Total Power Dissipation = 750 mW typ/pkg
Shift Frequ'ency = 325 MHz typ

8

0

·Output State

·

Undefined

01

14

02

15

50

ao

2

13

51

a1

52

12

a2

53

10

a3

3

4

6

5

L SUFFIX
CERAMIC PACKAGE
CASE 620

Clock

Reset

9 o-----+-----+------+-----~

+25 0 C

-30°C
Characteristic
Power Supply Drain Current
Input Current
Pin 9
Pin 7
Pins 2,3,6,10
Pins 14,15
Switching Times
Propagation Delay
Clock
Set, Reset

+85 0 C

Symbol

Min

Max

Min

Max

Min

Max

Unit

IE

-

-

-

200

-

-

mAde

-

-

-

-

-

-

-

1.0
0.75
0.6
0.5

mAde

linH

-

-

-

-

-

-

ns

tpd
1.0
2.0

3.2
3.9

1.0
2.0

3.0
3.7

1.0
2.0

3.4
4.1
ns

Rise Time (10% to 90%)

t+

1.0

2.9

1.0

2.7

1.0

3.1

Fall Time (10% to 90%)

t-

1.0

2.8

1.0

2.6

1.0

3.0

ns

240

-

275

-

250

-

MHz

Shift Rate

4-43

•

MC1697
1-GHz DIVIDE-BY-FOUR

PRES CALER

second stage. The complementary outputs are capable of
driving 50·ohm lines.
Pin 6 is available for connection of a decoupling capaci·
tor to ground. This capacitor stabilizes the reference point
which is internally coupled to the clock input.

The MC1697 is a divide·by·four gigahertz presealer in
an 8 pin plastic package. The clock input requires an ae
coupled driving signal of 800 mV amplitude (typical). The
clock toggles two divide·by·two stages, and the comple·
mentary outputs (50% duty cycle) are taken from the

vee1:: Pin 1
VCC2"" Pin 8
VEe::- Pin 5

Power Dissipation

=:

320 mW Typ/Pkg
(No L.oad - 7.0 V Supply)

·-----10

Clock 4

I

--_--1

Bias Point 6 --_-~

)---..-----1 c

01---1------ 2

C 01----<0-------3

Bias
Voltage
Generator

PIN ASSIGNMENT
VCC

PSUFFIX
PLASTIC PACKAGE
CASE 626

4-44

VCC

8

N.C.

7

2

Q

3

Q

Bias
Point

6

4

Clock VEE

5

Me 1697
ELECTRICAL CHARACTERISTICS
MC1697P Test Limits
+25 0 C
+75 o C

OOC
Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

-

57

-

-

mAdc

-

1.0

-

GHz

100

-

-

MHz

IE

-

Toggle Frequency
(high frequency operation)

trog

1.0

-

1.0 '

Toggle Frequency
(low frequency sine wave input)

trog

-

-

-

Power Supply Drain Current

COUNT FREQUENCY TEST CIRCUIT
VCCI' vCC2
+2.0 Vdc

Coax

0.01 "F

0/------'

, v 6 BP
Input

Pulse Generator
800 mV peak to peak typ

4

C

0.1 "F
Chip

3
af-----

Capacitor

5

O.' IlFJ

All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input

Unused outputs connected to a
50-ohm resIstor to ground.

VEE

pin and TP out to output pin.

-5.0 Vdc

Note: All power supply and logic levels' are shown shifted 2 volts positive.
TIMING DIAGRAM

1600

~
c.

1400

>

1200

".

1000

5
c.

.::

.

800

>

~
0

iii

600
400
200

100

200

300

400

500

600

700

800

Frequency (MHz)

'4-45

900 1000 1100 1200 1300 140015001600

II

MC1697

APPLICATION INFORMATION
The MC1697 is a very high speed divide·by·four prescaler
designed to operate on a nominal supply voltage of -7.0
volt. In some applications it may be necessary to interface
the output of the MC1697 with other MECL circuits
requiring a supply voltage of -S.2 volts. One method of
interfacing the circuits is shown below. This configuration
is adequate for frequencies up to 1 GHz over the tempera·
ture range of 0 0 to +7S o C. For best performance it is
recommended that separate regulated supplies be used.

METHOD OF INTERFACING MC1697 WITH STANDARD MECL CIRCUITS

II
,

,~

Q

MC1697

1----------1
Standard
MECL
Circuit

,

-7.0 V

Set to -5.2 V
Select Transistor based on
current requirement of

MECL circuits.

-7.0 V

4-46

MC1699
DIVIDE-BY-FOUR
GIGAHERTZ COUNTER

L SUFFIX
CERAMIC PACKAGE
CASE 620

F SUFFIX
CERAMIC PACKAGE
CASE 650

VCC1 =
V C C2 =
VEE =
Bias Point=
Clock (11) 7
Enable (9) 4

Reset (3)

Pin
Pin
Pin
Pin

16 (4)
1 (5)
8 (12)
11 (13)

D

The MC1699 is a divide-by-four gigahertz
counter. The clock input requires an ac coupled
driving signal of 800 mV amplitude (typical).
The, clock toggles two divide-by-two stages, and
the complementary outputs (50% duty cycle)
are taken from the second stage.
The MC1699 includes clock enable and
reset. The reset is compatible with MECL III
voltage levels; The enable input requires a VI L
of -2.0 V max. Reset operates only when either
the clock or the enable is high.
Pin 11 (13) is available for connection of a
decoupling capacitor to ground. This capacitor
stabilizes the reference point which is internally
coupled to the clock input.

QI-------ID

Q I - - - + - - - - - 2 (6)

---~,___

>-------IC R

14-------------~--------J

II

Number at end of terminal denotes pin number for L package (Case 620).
Number in parenthesis denotes pin number for F package (Case 650).

TIMING DIAGRAM
I

Enable-:l~_________________________________
Reset
,

I
I

Clock

I
I
Q

'----t-----t--'ri

(6),-'---+-'

I
I

Ll

Q (7)--1---+-'1

I
I

4-47

II
s(")

.....

en
c.o

c.o

ELECTRICAL CHARACTERISTICS
+25 0 C

-30°C
Characteristic
Power Supply Drain Current
I nput Current

.t..

00

Symbol

Min

Max

Min

Max

IE

-

-

-

57

-

-

-

-

-

500
265

-

-

-

Logic "1" Output Voltage

VOH

Logic "0" Output Voltage

VOL

-

Toggle Frequency
(high frequency operation)

fTog

1.0

-

1.0

fTog

-

-

-

Toggle Frequency
(low frequency sine wave
input)


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