1978_National_Data_Acquisition_Handbook 1978 National Data Acquisition Handbook
User Manual: 1978_National_Data_Acquisition_Handbook
Open the PDF directly: View PDF 
.
Page Count: 642
| Download | |
| Open PDF In Browser | View PDF |
DATA ACQUISITION
HANDBOOK
Selection Guides
Analog-to-Digital Converters
Digital-to-Analog Converters
Data Acquisition Systems
Digital Voltmeters
Voltage References
Analog Switches/Multiplexers
Sample and Hold
Amplifiers
Resistor Arrays
Active Filters .
Successive Approximation
Registers
Functional Blocks
Application Notes
Physical Dimensions
National Semiconductor Corporation 2900 Semiconductor Drive,
Santa. Clara, California 95051 Tel: (408) 737-5000 TWX: (910) 339-9240
National does not assume any responsibility for use of any circuitry described. no Circuit palent licenses are Implied, and National reserves the right. at any lime without nohce. to change said circuitry
Introduction
It's a rapidly changing world - and a moment's reflection reminds us. that, principally, it is electronics
that is causing the changes in our world. Electronic systems are changing too, from all-analog and alldigital types, to a world where analog and digital disciplines co-exist to make inexpensive but powerful
systems arid products that impact even our' daily lives. This Handbook is dedicated to the engineers who
design the data' acquisition and control systems that will playa major role in shaping and improving the
future_
Data Acquisition System Block Diagram
REF
Sales and Technical Assistance - All National
devices are available through our extensive network of local distributors. Technical assistance
in selecting and applying devices may be obtained
by contacting the nearest National representative
or sales office or by contacting the factory.
Converter Products Part Numbering System
National Semiconductor brings to the marketplace
a unique combination of qualifications to supply
the sophisticated components required by Data
Acquisition and Control systems - high technology devices, mass produced by one of the
world's largest semiconductor companies. We
have committed to design and source all the
building blocks required from transducer to
processor - this handbook is evidence of our
total systems approach. The products detailed
in this book include those devices in the direct
analog signal path before (and after) the digital
processor; devices are fabricated using many
technologies including BI-FETTM, linear bipolar,
CMOS, CMOS with trimmed thin film, 12 1., laser
trimmed thick and thin film hybrid and other
state-of-the-art processes. Microprocessor: Linear,
Discrete, and other functions are covered by their
respective databooks and are not duplicated herein.
AD
C
08
DO
ttL." . . . . , "'
TEMPERATURE RANGE
c: COMMERCIAL
I: INDUSTRIAL
M. DR NO DIGIT: MILITARY
TECHNOLOGY
P: PMOS
C. CMOS
H: HYBRID
B BIPOLAR
N. NMOS
L: LINEAR
"Ill
' - - - - - - - USED FOR MORE THAN ONE IN THIS FAMILY
' - - -_ _ _ _ _ RESOLUTION
DB: 8 BITS
10: 10 BITS
12.12 BITS
25'21/2 DIGIT
35. J 1/2 DIGIT
37:311401GIT
45:41/2 DIGIT
'---------FO~.~aMPLETE
Reliability - National manufactures components
to exacting quality and reliability standards. Most
of the devices included offer extended temperature
range performance versions and are built to conform with the requirements of MIL-M-38510
and can be ordered with extra reliability screening
including MIL-STD-883 Level A and B processing.
National's A+ and B+ industrial reliability programs can be specified for standard and industrial
temperature range devices. Consult your representative for processing details and availability
of these cost-effective programs.
B: BUILDING BLOCK
o DIGITAL PANEl METER CHIP
M:MODULE
s: CARD SYSTEMS
'----------FUNCTlDN
AD: ANAUJG·TD·DIGITAL
'j
DA: DIGI1AL·TD·ANALOG
Future Products - This handbook contains only
devices in production as of July, 1978. As this
book goes to press, development continues on
many advanced Data Acquisition/Conversion products - contact your distributor or representative
for information concerning new product introductions.
For information on National's part numbering system for non-converter devices, please consult the latest OEM price list.
3
(
,
Table of Contents
Edge I ndex by Product Family .................................. " . . . . . . . . . . . . . . .
Introduction ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Acquisition System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .
Converter Products Part Numbering System .............................. ',' . . . . . . . .
Alpha·Numerical Index ............................................. : . . . . . . . . . .
1
3
3
3
8
Section 1-Selection Guides
D/A Converter Selection Guide ........................... ,.........' .. :'...........
A/D Converter/DVM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Switches/Multiplexers Selection Guide. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BI-FETTM/BI-FET IITM Op Amp Selection Guide ................................. ,.
Pressure Transducer Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1·2
1·3
1-5
1-6
1-10
1-12
Section 2-Analog-to-Digital Converters t
ADB 1200 (MM5863) 12-Bit Binary A/D Building Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0800 (MM4357B/MM5357B) 8·Bit A/D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0808, ADC0809 Single Chip Data Acquisition System. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0816, ADC0817 Single Chip Data Acquisition System ...... , .. , .. , . .. . .. . .. . .. .. .
ADC1210, ADC1211 12-Bit CMOS A/D Converters ....... , .... . .. . .. . .. . .. . . . . ... ... .
ADC3511 3 1/2-Digit Microprocessor Compatible A/D Converter ...................... ,
ADC3711 3 3/4-Digit Microprocessor Compatible A/D Converter. . . . . . . . . . . . . . . . . . . . . . .
LF13300 Integrating A/D Analog Building Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM131A/LM131, LM231A/LM231, LM331A/LM331 Precision
Voltage-to-Frequency Converters ......... , .................................. -. .
TP3000 CODEC System (TP3001 /.I-Law, TP3002 A-Law) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2·8
2·19
2-29
2-39
f-49
2-49
2-57
2,78
2-89
t For additional information, see National Semiconductor's Linear Databo~k.
Section 3-Digital-to-Analog Converters t
AD7520 10-Bit Binary Multiplying D/A Converter. .. . . .. .. . ... ... . . . . ... . . . . ... . . .. .
AD7521 12-Bit Binary Multiplying D/A Converter ... , ... '" ........... ,. . . . .. ... . ...
DAC0800 (LMDAC08) 8-Bit Digital-to-Analog Converter. . . . . . . . . . .. . . . . . . . . . . . . . . . . . .
DAC0808, DAC0807, DAC0806 8-Bit D/A Converters ... ',' . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1020 10-Bit Binary Multiplying D/A Converter .................. ; ......... '... , .,
DAC1220 12-Bit Binary Multiplying D/A Converter .... : ....... , ...... '......... , . .. ..
DAC1200/DAC1201 12-Bit (Binary) Digital-to-Analog Converters. . . . . . . . . . . . . . . . . . . . . ..
DAC1202/DAC1203 3-Digit (BCD) Digital-to-Analog Converters. . . . ... . . . . . . . . . . . .. . ...
DAC1280, DAC1285'12-Bit (Binary) Digital-to-Analog Converters ..................... ,
DAC1286, DAC1287 3-Digit (BCD) Digital-to-Analog Converters. ......................
LM1508/LM1408 8-Bit D/A Converter ............ , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-1
3-1
3-3
3-11
3-18
3-18
3-28
,3-28
3-35
3-35
3-43
,t For additional information, see National Semiconductor's Linear Databook.
Section 4-Data Acquisition Systems
ADS1216HC 16-Channel, 12-Bit Data Acquisition System with Memory ................. '.
5
4-1
Table of Contents
(Continued)
Section 5-Digital Voltmeters
ADB4511 4 1/2-Digit Digital Panel Meter Controller ................................
ADD3501 3 1/2-Digit DVM with Multiplexed 7-Segment Output. . . . . . . . . . . . . . . . . . . . . . .
ADD3701 3 3/4-Digit DVM with Multiplexed 7-Segment Output ... , .. -. '" .. , ..........
LF13300 Integrating A/D Analog Building Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
"
5-1
. . 5-7
" 5-16
.. 2-57
Section 6-Voltage References t
LH0070 Series Precision BCD Buffered Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH0071 Series Precision Binary Buffered Reference ........................._. . . . . . . . . .
LM 103 Reference Diode ................................................ '...... "
LMl13/LM313 Reference Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
LM 129, LM329 Precision Reference ........ , .......................... .' . . . . . . . . . ..
LM134/LM234/LM334 3-Terminal Adjustable Current Sources. . . . . . . . . . . . . . . . . . . . . . . . ..
LM 136/LM236/LM336 2.5V Reference Diode ..................................... "
LM 199/LM299/LM399 Precision Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM199A/LM299A/LM399A Precision Reference .....................................
LM3999 Precision Reference ...................................... ; ............. ~
6-1
6-1
6-5
6-8
6-11
6-16
6-24
6-30
6-366-39
t For additional information, see- National Semiconductor's Linear Databaok.
Section 7 -Analog Switches/Multiplexers t
AH0014/AH0014C DPDT TTL/DTL Compatible MOS Analog Switches .......... , . '" . . . .
AH0015/AH0015C Quad SPST TTL/DTL Compatible MOS Analog Switches ............. "
AH0019/ AH0019C Dual DPST TTL/DTL Compatible MOS Analog Switches. . . . . . . . . . . . . . .
AH0120/AH0130/AH0140/AH0150/AH0160 Series Analog Switches. . . . . . . . . . . . . . . . . . . . .
AH2114/AH2114C DPST Analog Switch ...........................................
AM181/AM281, AM182/AM282 Dual Driver with SPST Switches ........................
AM184/AM284, AM185/AM285 Dual Driver with DPST Switches .. , ... '" ...............
AM187/AM287, AM188/AM288 Single Driver with SPDT Switches.......................
AM 190/AM290, AM191/AM291 Dual Driver with SPDT Switches...................... "
AM2009/AM2009C, MM4504/MM5504 6-Channel MOS Multiplex Switches. . . . . . . . . . . . . . ..
AM3705/AM3705C 8-Channel MOS Analog Multiplexer. '............................ "
AM9709, AM97C09, AH5009 Series Monolithic Analog Current Switches ................ "
CD4016M/CD4016C Quad Bilateral Switch ................. ',' ................. ; .. "
CD4051 BM/CD4051 BC Single 8-Channel Analog Multiplexer/Demultiplexer, ............. "
CD4052BM/CD4052BC Dual4-Channel Analog Multiplexer/Demultiplexer..... " ...... " ..
CD4053BM/CD4053BC Triple 2-Channel Analog Multiplexer/Demultiplexer. . . . . . . . . . . . . . ..
CD4066BM/CD4066BC Quad Bilateral Switch ...................................... '.
-CD4529BM/CD4529BC Dual 4-Channel or Single 8-Channel Analog Data Selector. . . . . . . . . ..
LF11331/LF12331/LF13331 4 Normally Open Switches with Disable ....................
LFl1332/LF12332/LF133324 Normally Closed Switches with Disable. . . . . . . . . . . . . . . . . ..
LFl1333/LF12333/LF13333 2 Normally Closed Switches and 2 Normally
Open Switches with Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LFl1201/LF12201/LF13201 4 Normally Closed Switches .............. , ............. "
LFl1202/LF12202/LF13202 4 Normally Qpen Switches ... '" ..................... , '"
LFl1508/LF12508/LF13508 8-Channel Analog Multiplexer ............................
LFl1509/LF12509/LF135094-Channel Differential Analog Multiplexer ........ ,' ..........
t For additional information, see National Semiconductor's Special Functions Databook and FET Databook.
7-1
7-1
7-1
7-4
7-11
'7-13
7-13
7-13
7-13
7-22
7:24
7-27
7-37
7-41
7-41
7-41
7-49
7-55
7-61
7-61
7-61
7-61
7-61
7-71
7-71
Section a-Sample and Hold t
LF198/LF298/LF398 Monolithic Sample and Hold Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
LH0023/LH0023C, LH0043/LH0043C Sample and Hold Circuits. . . . . . . . . . . . . . . . . . . . . . . . 8-9
LH0053/LH0053C High Speed Sample and Hold Amplifier ..... ~ ...... -. . . . . . . . . . . . . . . .. 8-17
t For additibnal information, see National Semiconductor's Special Functions Databook.
6
Table of Contents
(Continued)
Section 9-Amplifiers t
LF152/LF252/LF352 FET Input Instrumentation Amplifier ........................... ,
9·1
LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifier ... : . . . . . . . . . . .9-11
LF347 Wide Bandwidth Quad JFET Input Operational Amplifier ............. .'. . . . . . . .. 9-24
LF351 Wide Bandwidth JFET Input Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·32
LF353, LF354 Wide Bandwidth Dual JFET Input Operational Amplifier.. . . .. . .. . ... . . . . . 9-39
I:FT155/LFT156, LFT355/LFT356 Low Offset Monolithic JFET Input .
Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . ..
9-48
LH0036/LH0036C Instrumentation Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59
LH0037/LH0037C Low Cost Instrumentation Amplifier ........... '.' . . . . . . . . . . . . . . . . . 9-66
LH0044 Series Precision Low Noise Operational Amplifiers ................... : . . . . . . . . 9·69
LM146/LM246/LM346 Programmable Quad Operational Amplifiers. . . . . . . . . . . . . . . . . . . . . 9-75
t For additional information, see National Semiconductor's Special Functions Databook.
Section 10-Resistor Arrays
RA201 Precision Instrumentation Amplifier Resistor Network ............ '. . . . . . . . . . . . . .
10-1
Section 11-Active Filters
AF100 Universal Active Filter.............. '" .. .. . . . . . . . .. . . . . . ... . . . . .. .. . . . .. '11-1
AF 150 Universal Wideband Acitve Filter ........................................ ". 11-21
AF151 Dual Universal Active Filter .............................................. 11-41
Section 12-Successive Approximation Registers
DM2502, DM2503, DM2504 Successive Approximation Registers .. , ...... , .... :.. .. . . . . .
MM54C905/MM74C905 12-Bit Successive Approximation Register. . . . . . .. . . . . . .. . . . . . . . .
12-1
12-6
Section 13-Functional Blocks
LH0091 True rms to DC Converter ............................................ ; . .
13-1 .
LH0094 Multifunction Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-6
MM74C925, MM74C926, MM74C927, MM74C928 4-Digit Counter
with Multiplexed 7-Segment Output Driver...... , ..... , . '.' ...... . . .. . .. . . .. . . ... . .. 13-15
NSB53883 1/2-Digit 0.5 Inch LED Display ................................... '" . ... 13-19
NSB5918 3 3/4-Digit 0.5 Inch LED Display .... : ........ ; . .. . . . . . . . . . . ... . . . . . . . . . .. 13-23
Section 14-Application Notes
AN-156 Specifying A/D and D/A Converters. . . .. . . . . . ... .. . .... ... . ... .. .. .. . .. . . . .
AN-159 Data Acquisition System Interface to Computers ..... :~ .............. , .. . . .. .
AN-161 IC Voltage Reference has lppm per Degree Drift ............... : .............
AN-173 IC Zener Eases Reference Design .... : .................................... ,
AN 179 Analog-to-Digital Converter Testing ................. _................. .'. . ..
AN 184 References for A/D Converters ......................................... :. ..
AN-200 CMOS A/D Converter Chips Easily Interface to 8080A Microprocessor Systems. . . ....
AN-202 A Digital Multimeter Using ADD3501 .....................................
14-1
14-7
14-25
14-31
14-34
14-40
14-44
14-54
Section 15-Physical Dimensions
Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . .
7
15-1
Alpha-Numerical Index
AD7520 10-Bit Binary Multiplying D/A Converter .................................. .
3-1
AD7521 12-Bit Binary Multiplying D/A Converter ........ , .. , ...................... .
3-1
ADB1200 (MM5863) 12-Bit Binary AID Building Block .. ; ...... ',' ......... , ......... .
2-1
ADB4511 4 1/2-Digit Digital Panel Meter Controller ...... ~ .... '..................... . 5-41
ADC0800 (MM4357B/MM5357B) 8-Bit D/A Converter .............................. .
2-8
ADC0808 Single Chip Data Acquisition System .................................... . 2-19
ADC0809 Single Chip Data Acquisition System ................................ ',' .. .
2-19
ADC0816 Single Chip Data Acquisition System ........... ; ........................ .
2-29
ADC0817 Single Chip Data Acquisition System ............' ........................ .
2-29
ADC1210 12-Bit CMOS AID Converter .................... , ........... , ......... . 2-39
ADC1211' 12-Bit CMOS AID Converter .... , ..................................... . 2-39
ADC3511 3 1/2-Digit Microprocessor Compatible AID Converter. , ........ -. ........... . 2-49
ADC3711 3 3/4-Digit Microprocessor Compatible AID Converter ...................... . 2-49
ADD3501 3 1/2-Digit DVM with MlJltiplexed 7:Segment Output ...................... '..
5-1
ADD3701 3 3/4-Digit DVM with Multiplexed 7-Segment Output ....................... . 5-10
4-1
ADS1216HC 16-Channel, 12-Bit Data Acquisition System with Memory ................. .
11-1
AF100 Universal Active Filter .... ',' .......... ; .................................. .
AF150 Universal Wideband Active Filter ............... , ......................... . ,11-21
AF151 Dual Universal Acti~e Filter ............................................. . 11-41
7-1
AH0014 DPDT TTL/DTL Compatible MOS Analog Switch ............ , .............. .
7-1
AH001'4C DPDT TTL/DTL C~mpatible MOS Analog Switch .......................... .
7-1
AH0015 Quad SPST TTL/DTL Compatible MOS Analog Switch ....................... .
7-1
AH0015C Quad SPST TTL/DTLCompatible MOS Analog Switch .... , ................. .
7-1
AH0019 Dual DPST TTL/DTL Compatible MOS Analog Switch ....................... .
7-1
AH0019C Dual SPST TTL/DTL Compatible MOS Amilog Switch .......... : ........... .
7-4
AH0120 Series Analog Switches ................................................ '.
7-4
AH0130 S~ries Analog Switches ................" ................................ .
7-4
AH0140 Series Analog Switches ................................................ .
7-4
AH0150 Series Analog Switches .....................................•...........
7-4
AH0160 Series Analog Switches ...... '.......................................... .
7-11
AH2114 DPST Analog Switch .................................................. .
7-11
AH2114C DPST Analog Switch . ~" .................. ; .......................... .
AH5009 Series Monolithic' Analog Current Switches.................................. ' 7-27
7-13
AM 181 Dual Driver with SPST Switches .. '....................................... : .
AM182 Dual Driver with SPST Switches ........................... , ... : .......... . ,7-13
7-13
AM 184 Dual Driver with DPST Switches ......................................... .
AM185 Duill Driver with DPST Switches ......................................... . 7-13
7-13
AM 187 Single Driver with SPDT Switches .... : ................................... .
7-13
AM 188 Single Driver with SPDT Switches ........................................ .
7-13
'AM 190 Dual Driver with SPDT Swi~ches ......................................... .
7-13
AM191 Dual Driver with SPDT Switches: . , ................ -. ..................... .
AM281 Dual, Driver Vl(ith SPST Switches ........................................ '.. . 7-13
AM282 Dual Driver with SPST Switches ...................................... " ... . 7-13
7-13
AM284 Dual Drivl;!r with DPST Switches ..................... , ................... .
7-13
AM285 Dual, Driver with DPST Switches ...................... ,................... .
7-13
AM287 Single Driver with SPDT Switches ......................................... .
7-13
AM288 Single Driver with SPD1 Switches ........................................ .
AM290 Dual Driver with SPDT Swithes .................... , ..................... . 7-13
7-13
AM291 Dual Driver with SPDT Switches ........ '........... , ..................... .
AM2009 6-Channel MOS Mu Itiplex Switch ......................................... . 7-22
7-22
AM2009C 6-Channel MOS Multiplex Switch .............. : ........................ .
7-24
AM3705 8-Channel MOS Analog Multiplexer ................ ; ..................... .
7-24 ,
AM3705C 8-Channel MOS Analog Multiplexer .................. ',' ................. .
7-27
, AM9709 Series Monolithic Analog Current Switches ................... , ............ .
7-27
AM97C09 Se~ies Monolhhic Analog Current Switches ............................... .
B
Alpha-Numerical Index
(Continued)
"
AN-156 Specifying A/D and D/ A Converters ..... , ............ ; , .............. , . '. . ..
14-1
AN-159 Data Acquisition System Interface to Computers ... , ....... ,..... ............
14-7
AN-161 IC Voltage Reference has 1 ppm per Degree Drift .......•.............. '....... 14-25
AN -173 I C Zener Eases Reference ,Design ................... : ......... ; ..•.......... 14-31
AN-179 Analog-to-Digital Converter Testing ....... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-34
AN-184 References for A/D Converters ...... , ....... '. '..... , ...................... 14-40
AN-200 CMOS A/D Converter Chips Easily I nterface to 8080A Microprocessor Systems. . . . .. 14-44
AN-202 A Digital Multimeter Using ADD3501 .................... ~,; , . , . ,'. . . . . . . . . .. 14-54
CD4016C Quad Bilateral Switch ........ ,........... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7-37
CD4016M Quad Bilateral Switch .. , ............................ , . . . . . . . . . . . . .. . . . . . 7-37
CD4051 BC Single 8-Channel Analog Multiplexer/Demultiplexer ......... '. . . . . . . . . . . . . . . 7-41
CD4051 BM Single 8-Channel Analog Multiplexer/Demultiplexer . . . ... . . .. . . . . . . . . . . . . . ..
7-41
CD4052BC Dual 4-Channel Analog Multiplexer/Demultiplexer .. , ............ , . . .. . . . ..
7-41
CD4052BM Dual 4-Channel Analog Multiplexer/Demultiplexer ............ : .......... ,. '7-41
CD4053BC Triple 2-Channel Analog Multiplexer/Demultiplexer. . . . . . . . . . . .. . . . . ... . . . . . 7-41
CD4053BM Triple 2-Channel Analog Multiplexer/Demultiplexer ...... ; ..... '........... '.. ' 7-41
CD4066BC Quad Bilateral Switch ................ : ... ' ............ .......
'
.-., . . . . . . 7-49
CD4066BM Quad Bilateral Switch ..............' ............................. : ....' .' 7-49
7-55
CD4529BC Dual 4-Channel or Single 8-Channel Analog Data Selector ............ ; . .' . . . ..
CD4529BM Dual 4-Channel or Single 8-ChannelAnalog Data Selector. . . . . . . . . . . . . . . . . . ..
7-55
DAC0800 (LMDAC08) 8·Bit Digital-to-Analog Converter............... " ............. '.
3-3
DAC0806 8'Bit D/A Converter, ................. ' .... '.......... " ................ '. . 3-11
DAC0807 8-Bit D/ A Converter ....... " ................................ , ... ,.... '. . . 3-11
DAC0808 8-Bit D/A (;onverter ................ " ....... " ., .... " ... ; ... '" .. .. . 3-11
DAC1020 10-Bit Binary Multiplying D/A Converter ............ : ........'.: ..... : .. '...
3-18
DAC1200 12-Bit (Binary) Digital-to-Analog Converter ........ , . . . . . . . . . . . . . . . . . .. . . . .. 3-28
DAC1201 12-Bit (Binary) Digital-to-Analog Converter .............' ... , .... ~ . . . . . . . . .. '3-28
DAC1202 3-Digit (BCD) Digital-to-Analog Converter .................. , . . . . .. . ... . ... .3-28
DAC1203 3-Digit (BCD) Digital-to-Analog Converter ................... :' ... ; . . . . . . . . ... 3-28
DAC1220 12-Bit Binary MUltiplying D/A Converter.' ...... , .: ....... ; .. ,......... . i....
3-18
DAC1280 12-Bit (Binary) Digital-to-Analog Converter .................... :_ '... ; . . .. . . 3-35
DAC1285 12-Bit (Binary) Digital-to-Analog Converter ........ '.' ..... , ........ , ...... : . 3-35
DAC1286 3-Digit (BCD) Digital-to-Analog Converter ........... : .. ; .. ,: . . . . . . . . . . . . ... 3-35
DAC1287 3-Digit (B~D) Digital-to-Analog Converter ........ ; ................ , .. . .... ,3-35
DM2502 Successive Approximation Register '........................ '............. " '.12-1
DM2503 Successive Approximation Register ........................... .- .... '. . . . . ..
12-1
DM2504 Successive Approximation Register .................. ' ........ ;.: ._ .. _........ '. ", 12-1
LF152 FET Input Instrumentation Amplifier. .........................' ...... .- ..... -. . 9-1
LF155 Series Monolithic JFET Input Operational Amplifier ........ , .... ; .... '. . . . • . . .. 9-11
LF 156 Series Monolithic JF ET I nput Operational Amplifier ., ............... ; ....... '.'~ - 9-11
LF157 Series Monolithic JFET Input Operational Amplifier .. , ... , .... ;... : ........... : 9-11
LF198 Monolithic Sample and Hold Circuits ........................... ; .......... '. . .
8-1
'LF252 FET Input Instrumentation Amplifier. ... , ...... , ............. : ... . . . .... .. ..
9-1
LF298 Monolithic Sample and Hold Circuits .......... " ........ .- .. ,: .... I • • • • • • • • . • :
8-1
LF347 Wide Bandwidth Quad JFET Input Operational Amplifier ........ .- ... ; . . . . . . . . . . 9-24
LF351 Wide Bandwidth JFET Input Operational Amplifier .............. ; _'. . . . ... . . . .. ..
9-32
LF352 FET Input Instrumentation Amplifier .... , .......... '................. .......
9-1
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier ........... " ..... ' ..•...:. ;,' 9-39
9-39
LF354 Wide Bandwidth Dual J F ET I nput Operational Amplifier ............. .- .... .- ... '"
LF398 Monolithic Sample and Hold Circuits ........ , ... " .............. .- . _. . . . . .. .
8-1
LF11201 4 Normally Closed Switches ............................. : .... ;" ..... '. . . . 7-61
LFl12024 Normally Open Switches ................... , .. , ............. .- ... : .. ,.
7-61
LF 11331 4 Normally Open Switches with Disable ............................. , .. ~'.. ,7-61
LF113324 Normally Closed Switches with Disable ...................... '...... '.. '" . 7-61
LF 11333 2 Normally Closed Switches and 2 Normally Open Switches with Disable. ; . .- . . . . . . 7-61
9
Alpha-Numerical Index-
(Continued)
LFl1508 8-Channel Analog Multiplexer. _....... : ................................. '
LF 11509 4-Channel Differential Analog MUltiplexer ................................ ;
LF12201 4 Normally Closed Switches .' .... " ............... , ....... :, ............. .
LF 122024 Normally Open Switches ........................................... ; .
LF1.2331 4 Normally Open Switches with Disable ........... : .... : ................. .
LF123324 Normally Closed Switches with Disable ................................. .
LF12333 2 Normally Closed Switches and 2 Normally Open Switches with Disable......... .
LF 12508 8-Channel Analog Multiplexer ....................................."..... .
LF 12509 4-Channel Differential Analog Multiplexer ................................ .
LF13201 4 Normally Closed Switches ........................................... .
LF13202 4 Normally Open Switches ....................................... ; .... .
LF13300 Integrating AID Analog Building Block ...........................' ........ .
LF13331 4 Normally Open Switches with Disable ................. '................. .
LF133324 Normally Closed Switches with Disable ................................. .
LF 13333 2 Normally Closed Switches and 2 Normally Open Switches with Disable ......... .
LF13508 8-Channel Analog MUltiplexer. ... .'.......... '............................ .
LF13509 4-Channel Differential Analog Multiplexer ........ : ..... " ......... ; ....... .
LFT155 Low Offset Monolithic JFET Input Operational Amplifier ..................... .
LFT156 Low Offset Monolithic JFET Input Operational Amplifier; .' .................. ' ..
LFT355 Low Offset Monolithic JFET Input Operational Amplifier ........... '.......... .
LFT356 Low Offset Monolithic JFET Input Operational Amplifier ...... ,' ......... ; .... .
LH0023 Sample and Hold Circuit ............ ; .................... '....... : .' ...... .
LH0023C Sample and Hold Circuit ...... ' ........................•................
LH0036 Instrumentation ~mplifier ............................................. .
LH0036C I nstrumentation Amplifier ............. , ..... ,.......•......... ; ....... .
LH0037 Low Cost Instrumentation Amplifier ~ ...................... '........ ' ..' ..... .
LH0037C Low Cost I nstrumentation Amplifier. < " • • • • • • .' • • • • • • • • , • ; • • • • • • • • • • • • • • •
LH0043 Sample and Hold Circuit ............. , ..... :' ........................... .
LH0043C Sample and Hold Circuit .............................. '................ .
LH0044 Series Precision Low Noise Operational Amplifiers. , : ........................ .
LH0053 High Speed Sample and Hold Amplifier ... : .........•..... : ........... " ... '.
LH0053C High Speed Sample and Hold Amplifier ....... '.................... ',' ..... .
LH0070 Series Precision BCD Buffered ,Reference .................. : ............... .
LH0071 Series Precision Binary Buffered Reference .............. ; ......... , ; ....... .
LH0091 True rms to DC Converter .................................... '.......... .
LH0094 Multifunction Converter. 0' • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • , • • • • • • • • • • • • • •
LM103 Reference Diode .....................................................' ..
LMl13 Reference Diode ...................................................... .
LM129 Precision Reference ... ',' ...........•.....•.....................•........
LM131 Precision Voltage-to-Frequency Converter ................................... .
LM131A Precision Voltage-to-Frequency Converter ....................... "..........,.
LM134 3-Terminal Adjustable Current Source ..•...................' ............... .
LM136 2.5V Reference Diode....•..............................................
LM 146 Programmable Quad Operational Amplifier ................................. .
LM 199 Precision Reference...............•....................... ; .........•...
LM 199A Precision Reference ................................................... .
LM231 Precision Voltage-to-Frequency Converter .................................. '..
LM231A Precision Voltage-to-Frequency Converter .... _ ............................ .
LM234 3-Terminal Adjustable Current Source ........................ , .......... '.. .
LM236 2.5V Reference Diode...............•........•....... ,' ..•. ", .' .......... .
LM246 Programmable Quad Operational Amplifier ............. ; .•........ ; ........ .
LM299 Precision Reference.... '.............................................. '... .
LM299A Precision Reference ..........................................' ........ .
LM313 Reference Diode ....................................... : ............. ; ..
LM329 Precision Reference.. ; ...... ; .............. " .. '........................ .
10
7-71
7-71
7-61
7-61
7-61
7-61
7-61
7-71
7-71
7-61
7-61
2-57
7-61
7-61
7-61
7-71
, 7-71
9-48
9-48
9-48
9-48
8-9
8-9
9-59
9-59
9-66
9-66
8-9
,8-9
9-69
8-17
8-17
6-1
6-1
13-1
13-6
6-5
6-8
6-11 '
2-78
2-78
6-16
6-24
9;75
6-30
6-36
2-78
2-78
6-16
6-24
9-75
6-30
6-36
6-8
6-11
Alpha-Numerical Index
(Continued)
LM331 Precision Voltage-to-Frequency Converter .... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM331A Precision Voltage-to-Frequency Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM334 3-Terminal Adjustable Current Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM336 2.5V Reference Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM346 Programmable Quad Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM399 Precision Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . ..
LM399A Precision Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1408 8-Bit D/A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 1508 8-B it D/A Converter .......................................... : . . . . . . . .
LM3999 Precision Reference ....... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4504 6-Channel MOS Multiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5504 6-Channel MOS Multiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C905 12-Bit Successive Approximation Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM74C905 12-Bit Successive Approximation Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
MM74C925 4-Digit Counter with MUltiplexed 7-Segment Output Driver... .. .. .. .. .. .. ...
MM74C926 4-Digit Counter with MUltiplexed 7-Segment Output Driver. . . . . . . . . . . . . . . . ..
MM74C927 4-Digit Counter with Multiplexed 7-Segment Output Driver. . . . . . . . . . . . . . . . ..
MM74C928 4-Digit Counter with MUltiplexed 7-Segment Output Driver. . . . . . . . . . . . . . . . ..
NSB53883 1/2-Digit 0.5 Inch LED Display. . ..... . . . . . .. .. . . . . . .. .. .. .. . . .... . . . ..
NSB59183 3/4-Digit 0.5 Inch LED Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RA201 Precision I nstrumentation Amplifier Resistor Network. . . . . . . . . . . . . . . . . . . . . . . . . .
TP3000 CODEC System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . ... . . . .
TP3001 J.l-Law CODEC System .......................................... : . . . . . . .
TP3002 A-Law CODEC System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2-78
2-78
6-16
6-24
9-75
6-30
6-36
3-43
3-43
6-39
7-22
7-22
12-6
12-6
13-15
13-15
13-15
13-15
13-19
13-23
10-1
2;89
2-89
2-89
Section 1
Selection Guides
I
,
RESOLUTION
(BITS)
D/A CONVERTER
S
.:...
NATIONAL
PART NUMBER
ALTERNATE SOURCE
PART NUMBER
LINEARITY
@25°C
(MAX) (%)
INTERNAL
REFERENCE
OUTPUT
OPAMP
SUPPLIES
(V)
TEMPERATURE RANGES
AVAILABLE
(C)
S
DACOS06
MC140S·6
0.78
±5to±15
S
DACOS07
MC140S·7
0.39
±5to±15
S
DACOS08
MC150S·S/MC1408·S
0.19
±5to±15
10
DAC1020
AD7520LlAD7530L
0.05
5 to 15
10
DAC1021
AD7520K/AD7530K
0.1
5 to 15
10
DAC1022
AD7520J/AD7530J
0.2
5 to 15
12
DAC1220
AD7521 LlAD7531 L
0.05
5 to 15
12
DAC1221
AD7521K/AD7531K
0.1
5 to 15
12
DAC1222
AD7521J/AD7531J
0.2
5 to 15
o to +70, -55 to +125
o to +70, -55 to +125
o to +70
o to +70
o to +70
o to +70, -55 to +125
o to +70, -55 to +125
o to +70, -55 to +125
o to +70, -55 to +125
o to +70, -55 to +125
o to +70, -55 to +125
o to +70, -55 to +125
12
DAC1200
0.012
±15,5
-25 to +85, -55 to +125
12
DAC1201
0.049
12
DAC12S5
DACS5 (Binary)
DACSO (Binary)"
DACOS02
DAC·OSA, DAC·OSH
0.1
±5to±15
S
"DACOSOO
DAC·OS, DAC·OSE
0.19
±5 to ±15
S
DACOSOI
DAC·OSC
0.39
±5to±15
0.012
12
DAC1280
3·Digits
DAC1202
0.01
3·Digits
DAC1203
0.05
3·Digits
DAC1286
DACS5 (BCD)
0.05
3·Digits
DAC1287
DAC80 (BCD)'
0.1
"Note. Minor specification differences
0.024
•
•
•
•
•
•
•
•
•
•
•
•
COMMENTS
High Speed Multiplying
High Speed Multiplying
High Speed Multiplying
Multiplying
Multiplying
Multiplying
4·0uadrant Multiplying
4·0uadrant Multiplying
4·0uadrant Multiplying
4·0uadrant MUltiplying
4·0uadrant Multiplying
4·0uadrant Multiplying
Complete DAC
±15,5
-25 to +85, -55 to +125
Complete DAC
±15,5
-25 to +85, -55 to +125
Complete DAC
±15,5
-25 to +85
Complete DAC
±15,5
-25 to +S5, -55 to +125
Complete BCD DAC
±15,5
-25 to +S5, -55 to +125
Complete BCD DAC
•
±15,5
-25 to +85, -55 to +125
Complete BCD DAC
•
±15,5
-25 to +85
Complete BCD DAC
•
•
A/D Converter/
DVM
RESOLUTION
(BITS)
LINEARITY
@25°C
(MAX) (%)
BASIC TYPE
AID CONVERTER
8
CONVERSION
TIME
(TYP)
OUTPUT
LOGIC
LEVELS
SUPPLIES
(V)
TEMPERATURE RANGES
AVAILABLE
(OC)
COMMENTS
ADC0800
(MM5357B)
0.8
·100p5
TTL
TRI-STATE®
+5,-12
o to +70, -55 to +125
8
ADC0808
0.2
100 p5
TTL
TRI~STATE
+5
-40 to +85, -55 to +125
Includes 8-Channel MUX
8
ADC0809
0.4
100 p5
TTL
+5
-40 to +85, -55 to +125
Includes 8-Channel MUX
TRI-STATE
ADCOS16
0.2
lOOps,
TTL
TRI'STATE
+5
-40 to +S5, -55 to +125
16-Channel MUX, Sand H Port
ADCOS17
0.4
lOOps
TTL
TRI-STATE
+5
-40 to +S5, --55 to +125
16-Channel MUX, Sand H Port
st
TP3000
t-
TTL
±12
12
ADC1210
0.012
lOOps
CMOS
+5 to ±15
-25 to +S5, -55 to +125
12 (10)
ADC1211
0.049
lOOps
CMOS
+5to±15
-25 to +85, -55 to +125
8
8
,
r:.,
,
12
3 1/2-Digit5
.'.
. t
'Oto+70
tCompanding Coder-Decoder
1O-Blt Conversion in 30 p5
{LF13300 .
0.01
N/A
N/A
±15
N/A
36 m5
TTL
TRI-STATE
+5, -15
o to +70
o to +70
Dual Slope ADC
ADB1200
0.05
200 m5
TTL
TFiI-STATE
+5
o to +70
Integrating pP ADC
TTL
. TRI-STATE
+5
o to ",70
Integrating pP ADC
ADC3511
.
-
12-Bit Logic for LF13300
33/4-Digit5
ADC3711
0.05
400 ms
V-F
LM131
6.01
N/A
N/A
+5 to +40
o to +70, -25 to +S5, -55 to + 125
Vol tage- to- Frequency
Converter, 100 kHz Max
DIGITAL VOLTMETER
ADD3501
3 1/2-Digit5
0.05
200 m5
7-Segment
LED Drive
+5
o to +70
3 1/2-Digit LED DPM
ADD3701
0.05
AOOm5
7-Segment
LED Drive
+5
o to +70
3 3/4-Digit LED DPM
o to +70
o to +70
33/4-Digit5
4 1/2-Digit5
{LF13300
ADB4511
0.005
N/A
N/A
±15
N/A
500 m5
7-Segment
LED Drive
+5
-----------_ .. _-----
----
Dual Slope ADC
4 1/2-Digit DPM Logic
for LF13300
REVERSE BREAKDOWN
VOLTAGE
VR,at IR'
1.22
1.22
1.22
5.0
6.90
6.90
6.90
6.90
6.90
6.90
6_95
LM113
LM313
LM113-1
LM113-2
LM136
LM136A'
LM236
LM236A
LM336
LM3368
LMI36-5.0
LM136A-5.0
LM236-5.0
LM236A-5.0
LM336-5.0
LM3368-5.0
LM129A
LM129B
LM129C
LM3298
LM329C
LM329D
LM199A
6.95
LM199A
6.95
6.95
6.95
6.95
6.95
6.95
6.95
10.00
,
10.00
10.00
10.24
10.24
10.24
LM199
LM199
LM299A
LM299
LM399A
LM3Jl9
LM3999
LH0070-0
LH0070-1
LH0070-2
LHOil71-0
LH0071-1
LH0071-2
1.22
2.49
2.49
2.49
2.49
2.49
2.49
5.0
5.0
5.0
5.0
5.0
w
DEVICE
VOLTAGE
TOLERANCE
MAX, T A = 2SoC
±5%
±S%
±1%
±2%
±2%
-
±1%
±2%
±1%
±4%
±2%
±2%
±1%
±2%
±1%
±4%
±2%
+3%, -2%
+3%, -2%
+3%, -2%
±5%
±5%
±5%
+1%,-2%
+1%, -2%
+1%,-2%
+1%, -2%
+1%, -2%
+1%, -2%
±5%
±5%
±5%
0.1%
0.1%
0.05%
0.1%
0.1%
0.05%
"
VOLTAGE TEMPERATURE
DRI FT - pprnfC MAX
or rnV MAX CHANGE OVER
TEMPERATURE RANGE
DRIFT
(MAX)
100 (typl
100 (typi
50 (typi
50 (typl
18mV
18rnV
9rnV
9mV
6rnV
6rnV
36mV
36mV
18mV
18rnV
12rnV
12mV
10
20
50
20
50
100
0.5
10
1
15
0.5
1
1
2
5
20mV
10rnV
.4rnV
20mV
10mV
4rnV
.-
CURRENT RANGE, IR
DYNAMIC
IMPEDANCE
TEMPERATURE
RANGE
-S5°C to +125'C
DoC to +70°C
-5SoC to +125°C
-5S'C to +125°C
-55°C to +125°C
-55°C to +125°C
-25°C to +85°C
-25°C to +85°C
O°C to +70°C
O°C to +70'C
-55°C to +125'C
-55'C to +125°C
-25'C to +85'C
-25'C to +85'C
o°c' to +70°C
O°C to +70°C
-55°C to +125°C
-55°C to +12SoC
-55°C to +125°C
O°C to +70°C
DoC to +70°C
O°C to +70°C
-55°C to +85°C
85'C to +125°C
500 IlA to 20 mA
500 IlA to 20 mA
500 IlA to 20 mA
500llA to 20 rnA
400 IlA to 10 rnA
400llA to 10 mA
400llA to 10 rnA
400llA to 10 rnA
400 IlA to 10 rnA
400llA to 10 rnA
400llA to 10 rnA
400llA to 10 rnA
- 400llA to 10 rnA
400llA to 10 rnA
400llAto 10 rnA
400llA to 10 rnA
0.6 rnA to15 rnA
0.6 rnA to 15 rnA
0.6 rnA to 15 rnA
0.6 rnA to 15 rnA
0.6 rnA to 15 rnA
0.6 rnA to 15 rnA
0.5 rnA to 10 rnA
0.5 rnA to 10'rnA
0.3n
0.3n
0.3n
0.3n
-55°C to +85°C
85°Cto+125°C
-25°C to +85°C
-25°C to +85'C
o°c to +70°C
O°C to +70°C
O°C to +70°C
-25°C to +85°C'
-25°C to +85°C'
-25°C to +85°C'
-25° C to +850 C·
-25°C to '+85°C'
-25° C to +85° C·
0.5 rnA to 10 rnA
0.5 rnA to 10 mA
0.5n
0.5n
0.5 mA to 10 mA
0.5 rnA to 10 mA
0.5 rnA to'lO rnA
0.5 rnA to 10 mA
0.6 rnA to 10 rnA
o mAto 20 mA
o rnA to 20 rnA
o rnA to 20 rnA
OrnAt020mA
o rnA to 20 rnA
o rnA to 20 rnA
0.5n
0.5n
0.5n
0.5n
0.6n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0.2n
0_2n
0.6n
0.6n
0.6n
0.8n
0.8n
0.8n
0.5n
0.5n
*Devices are specified for operation over entire -55°C to +125°C range.
----
-- ----------
aouaJala~
a61!11 0 A
Voltage
Reference
REVERSE BREAKDOWN
VOLTAGE
VR at IR
DEVICE
VOLTAGE
TOLERANCE
MAX, T A = 2SOC
VOLTAGE TEMPERATURE
DRIFT - ppmtC MAX
or mV MAX CHANGE OVER
TEMPERATURE RANGE
DRIFT
(MAX)
CURRENT RANGE, IR
DYNAMIC
IMPEDANCE
TEMPERATURE
RANGE
LOW CURRENT ZENER DIODES
1.8
2.0
2.2
2.4
2.7
3.0
3.3
3.6
3.9
.;,.
LM103
LM103
LM103.
LM103
±10%
-S mVtC (typ)
±10%
-S mVtC (typ)
-S mVtC (typ)
-S mvtC (typ)
LM103
LM103
LM103
±10%
LM103
LM103
4.3
4.7
LM103
LM103
S.l
LM103
LM103
S.6
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
-S mvtC (typ)
-S mVfC (typ)
~S mVfC (typ)
-S mVfC
-S mVfC
-S mVfC
.:.S mVfC
(typ)
(typ)
(typ)
(typ)
-S mVfC (typ)
-S mVfC (typ)
-SSoC to
-SSoC to
-SSoC to
-SSoC to
+ 12SoC
10/lA to
10/lAto
10/lA to
10/lAto
10 mA
lOmA
10 mA
10mA
lSr2
lSr2
lSr2
lSI1
"'SSoC to + 12SoC
-S'SoC to + 12SOC
10/lAto 10mA
10/lAto 10mA
-SSoC to +12So.C
-SSoC to + 12SOC
10/lAt" 10mA
lO/lA to 10 mA
10/lAto 10mA
lSI1
lSI1
lSI1
+dsoc
+ 12SOC
+ 12SoC
-SSoC to +12SoC
-SSoC to +12SoC
"':SSoC to +12SoC
10/lAto 10mA
10/lAto 10mA
10/lAto 10mA
lSI1
lSr2
lSr2
lSI1
lSI1
-SSoC to +12SoC
10/lAto 10mA
lSI1
-SSoC to +12SoC
,
-
RON
1m
Dual SPST
10
30
80
15
50
'30
'75
VAil
IVI
±TO
±TO
flO
±7.5
±7.5
±7.5
±TO
PART
NUMBER
lOGIC
AH0141/DG141
AH0133/DG133
AH0134/DG134
AH0151/DG151
AH0152/DG152
AM181/DG181
AM182/DG182
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Vs
IVI
TYP
INPUT
tON/tOFF
TYP
RON
1m
SPOT
10
30
80
15
50
100
O.8/1.1,us
-18.12
-18,12
-18,12
±TS
±TS
±TS,5
±TS,5
O.5/0.9,us
O.S/O.9.us
O.B/l.1ps
D.S/O.9ps
180/150 ns
300/150 ns
AH5015
,AH50J6
15V TTL
TTL
Dual SPDT
"30
"75
150/300 ns
150/300 ns
Ouad SPST
'"
200~600
"200
'200
'200
"200
"200
'"250
'250
'250
"250
'250
280
850
~ 100
'100
*150
·,50
"30
'75
±10
±10
ilO
±1O
ilO
±10
±10
±lO
±10
±10
±10
±7.5
±7.S
15mA
lOrnA
5mA
3mA
±7.5
±10
AHOO15
lFl1201
LF11202
lF11331
LF11332
lF11333
LF13201
lF13202
LF13331
LF13332
LF13333
CD4066
CD4016
AHSOl 1/AM971 1
AM97Cll
AH5012/AM9712
AM97C12
AM193
AM194
-20, 10,5
TTL
±15
TTL
±15
TTL
±15
TTL
TTL
±15
TTL
±lS
±1S
TTL
TTL
±15
TTL
±15
TTL
±lS
TTL
±15
CMOS ±7.5
CMOS ±7.5
15V TTL
CMOS
TTL
CMOS
±1S,5
TTL
±lS,5
TTL
PART
Vs
IVI
TYP
NUMBER
lOGIC
INPUT
AH0146/DG146
AH0144/DG144
AH0143/0G143
AH0161!DG161
AHQ162/DG162
AH2114 (Sw. 1l
TTL
TTL
TTL
TTL
TTL
15VTTL
±7.5
±7.5
±9
±7.S
±1O
Dual DPST
10
30
80
15
50
200~600
"30
"75
Dual DPDT
10
30
80
15
50
200-600
150/300 ns
150/300 ns
150/300 ns
150/300 ns
180/150 ns
- 300/150 ns
RON
Inl
-18,12
-18,12
-18,12
iTS
VAil
(VI
PART
NUMBER
Vs
IVI
TYP
LOGIC
INPUT
tON/tOFF
TYP
±15
±TS
AM187iDG187
AM188/DG188
iTS,5
TTL
TTL
±TS,5
0.8/1.1ps
3-Channel
0.5/0.9I1 S
0.8/1.1ps
""'00
·150
a.S/O,9ps
35/600 os
1.2ps/50 ns
180/150 os
300/150 ns
"100
"100
0.5/0.9/15
±7.5
±10
AM190/DG190
AM191/DG191
TTL
TTL
±T5,5
i15,5
CMOS
±7.5
1501150 ns
±lO
±10
±10
±7.S
±7.5
±10
±7.5
±lO
AH0140iDG140
AH0129/DG129
AH0126/DG126
AH0153/DG153
AH0154/DG154
AHOO19
AM1S4/DG1S4
AM185iDG185
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-18,12
-18,12
-18,12
i15
itS
-20,10,5
±15.5
±15.5
0.8/1.1,us
i10
±1O
-±10
±7.S
n.5
±10
AH0145/DG145
TTL
TTL
TTL
TTL
TTL
TTL
-lB,12·
-lB,12
-18,12
±t5
0.8/1.1j1s
0.5/0.9,us
0.5/0.9,us
0.8/1.1,us
O.S/O.9,us
350/400 ns
.t15
-20,10,5
AH5013
AH5014
lSmA
lOrnA
5mA
3mA
AH5009/AM9709
AM97C09
AH501O/AM971O
AM97C10
TTL
CMOS
CD4052
LF11509
CD4529B
CMOS
TTL
CMOS
±7.5
±1S
±7.S
15mA
15V TTL
TTL
-
150/300 os
150/300 os
15V TTL
CMOS
150/300 os
150/300 ns
150/300 ns
150/300 ns
180/150 ns
300/150 ns
CD4053
AH0139/DG139
AH0142/DG142
AH0163/OG163
AH0164/DG164
AHOO14
5mA
4-Channel
'150
"150
Triple SPDT
280
±7.5
100/400 ns
90/500 ns
90/500 ns
90/500 ns
90/500 ns
90/500 ns
90/500 ns
90/500 ns
90/500 ns
90/500 ns
90/500 ns
tONftOFF
TYP
MULTIPLEXERS
±lO
±lO
±1O
(Sw.2)
'30
'75
Triple SPST
"100
15rnA
"150
5mA
VAil
(VI
0.S/0.9,us
0.5JO.9j.ls
4-Channel Differential
280
±7.5
'"350
12,-15
±7.5
270
6-Channel
250·1500
50 rnA
AM2009/MM4504!
MM5504
TTL
-15,5
a-Channel
250-400
"350
270
280
±5
12,-15
!75
±7.5
AM370S
LF11S0B
CD45298
CD4051
TTL
TTL
CMOS
CMOS
-15,5
±15
±7.5
±7.5
O.8/1.1,us
0.5/0.9,us
100/400 ns
180/150 ns
300/150 ns
150/150 ns
1/0.2,us
SO/50 ns
300/600 ns
1/0.2,us
SO/50 ns
150/150 ns
Notes:
RON max @ T A = 25" C
V A/I"" maximum voltage or current to be safely switched
Part number = basic number/alternate number {i.e.,
*Preferred devices
AM181/DG181L May be ordered by either number.
,
-
-----
SJaXaldmnw
/Sa40J!MS 601eU\f
Voltage Regulator
/
3-TERMINAL POSITIVE VOLTAGE REGULATORS
Available
VOUT
(VI
Output
Device
Currant
(A)
5
LM138, LM238
LM338
1.2 to 32 (Adjustable)
1.2 to 32 (Adjustable)
3
LM150, LM250
LM350
1.5
0,
0.5
Regulation
VOUT
Tol_
(±%)
VIN
(V)
Max
Load (Note 2)
%VOUT
Line (Note 1)
%VOUTIVIN
Ripple
Rejection
(dB)
N/A
N/A
0.005
0.005
0.1
0.·1
35
35
86
86
1.2 to 32 (Adjustable)
1.2 to 32 (Adjustablel
N/A
N/A
0.005
0.005
0.1
0.1
35 •
35
86
86
LM123K, LM223K
'LM323'K
5
5
6
4
0.01
0.01
0.5
0.5
20
20
75
75
LM117, LM217
LM317
1 .2 to 37 (Adjustable)
1.2 to 37 (Adjustable)
N/A
N/A
0.01
0.01
0.1
0.1
40
40
80
80
LM117HV, LM217HV
LM317HV
1.2to 57 (Adjustable)
1.2 to 57 (Adjustable)
N/A
N/A
0.01
0.01
0.1
0.1
60
60
80
80
LM109K, LM209K
LM309K
5
5
6
4
0.004
0.004
1.0
1.0
35
35
80
80
LM140K
5,6,8,10,12,15,18,24
4
0.02
0.5
35,40 (24V)
66-80
LM140AK
5,6,8,10,12, IS, 18,24
2
0.002
0.1
35,40 (24V)
66-80
LM340
5,6,8,10,12, IS, 18, 24
4
0.02
0.5
35,40 (24V)
66-80
LM340A
5,6,8,10,12, 15,1B, 24
2
0.002
0.1
35,40 (24V)
66-80
LM78XXC
5,6,8,10,12,15,18,24
4
0.03
0.5
35,40 (24V)
66-80
LM117H, LM217H
LM317H
1.2 to 37 (Adjustable)
1.2 to 37 (Adjustable) _
N/A
N/A
om
om
0.1
0.1
40
40
80
80
LM117HVH, LM217HVH
LM317HVH
1.2 to 37 (Adjustable)
1.2 to 37 (Adjusta!?le)
N/A
N/A
0.01
0.01
0.1
0.1
40
40
80
80
80
-
LM317M
1.2 to 37 (Adjust.ble)
N/A
om
0.1
40
LM341
5,6,8,10,12,15,18,24
4
0.02
0.5
35,40 (24V)
5,6,8,10,12,15,18,24
4
0.03
0.5
35,40 (24V)
0.25
LM342
5,6,8,10,12,15,18,24
4
0.03
0.5 .
35,40 (24V)
53-64
0.20
LM109H, LM209H
LM309H
5
5'
6
4
0.004
0.004
0.4
0.4
35
35
80
80
LM140L, LM240L
lM340L
5,6,8,10,12,15,18,24
5,6,8,10,.12,15,18,24.
2
2
0.02
'0.02
0.25
0.25
35,40 !24V)
35,40 (24V)'
48-62
' 48-62
LM78LXXA
5,6,8,10,12,15,18,24
4
0.03
0.25
35,40 (24V)
45-60
LM78MXX
0.10
-
-
Note 1: Line regulation is the change in output voltage for a change in input v~ltage.
Note 2: Load regulation is the change in output voltage due to a change in load current from no load to full load.
,
,
i
.-
I
5.0
3.0
1.5
{
I
[
f::0
I-
1:i
1.0
:::>
y
...
I-
t?
LM123/LM223/LM323K STEEL
LMl&8/LM25t/1.M358lC mEL
1.2"
LM117/LM217/LM317K SHEL
1.2V
LM111HVJLM217H"/LM311HVK STEEL
LM317T
C>
t§J - AUIJUST~81E
33"
62 -AO~UST~BLE
37V.
.
f§l.
(J(Jt;fr~~~(»"
1.2V
I
I
~ 0.5
LM117H/LM217H/LM317H
1.2V
I
tJ:.
I'
0.25
0.2
{
{
I
I
PACKAGE
TYPE
0
K
KC
K STEEL
TO·3*
HERMETIC
tJ
T
TO·220
PLASTIC
~
P
57V
-TO·202
PLASTIC
37V
~
H
TO·5, TO-39
HERMETIC
£)
Z
TO·99
PLASTIC
I
-A01JUSTlBLE
I
I
,"
37V
~-ADJUSTABlE
.
I
I
~-AOJUSTABLE
I
I
I
,b
LMI89H/LM289HllM309H
LM240LAZ/LM340LAZ
LM78LXXCZ
LM78LXXACZ
I
~((~(j>(!(!;j>~
LM342P
LMI40L,AH/LM240LAH/LM340LAH
LM78LXXCH
LM78LXXACH
0.1
PACKAGE
DESIGNATOR
tttttttttttttttt
LM341P
LM78MXXCP
E
37V
lM34DT
1.2V
I
i
{§J
I
LM317MP
.,.:::>
!
51"
190067670067
LM117H"H/LM217tJVH/LM317H"H
ct
I
LMI40AK/LM340AK, LMI40K/LM340K
LM78XXCK (AL)
IZ
I
ADJUSfABLE
I
I
~- ADJUSTABLE
:::>
...
I
I
I-
~Iffi
3lV
!
1.2"
1.2V
LM78XXCT
:::>
{)
1.2"
LMl_/LM289K1LM389K mEL, LM389K (AL)
5
a:
a:
, LM138/LM238IUI33aK mEL
I
• All devices with TO.J package desig'
nators (K or K STEEL ) are supplied
in steel TO..J packages unless otherwise
designated as (AU aluminum TO-3
package. All' KC designated devices
are supplied in aluminum TO-3.
~~.#.#.#.#.#.#
I I I I I L'I I
ffffffff
5
6
8
10
12
15, 18
24
Vo - NOMINAL REGULATED OUTPUT VOLTAGE (V)
Jo~el n 6al::l a6e~IO 1\
Voltage Regulator
3·TERMINAL NEGATIVE VOLTAGE REGULATORS
Output
Available
Device
Current
YOU,.
(V)
-5.0,-5.2
-5.0, -5.2
(A)
VOUT
Tol.
(±%)
Regulation
V'N
(V)
Ripp'.
Lin. (Note 1)
%VOUTN,N
Load (Note 2)
%VOUT
2
4
0.008
0.008
0.6
0.6
20
20
68
68
77
77
Max
Rejection
(dB)
3
LM145K, LM245K
LM345K
1.5
LM137, LM237
LM337 •
LM137HV, LM237HV
LM337HV
LM120K, LM220K
-1.2 to -37 (Adjustable)
-1.2 to -37 (Adjustabl.)
-1.2 to -47 (Adjustabl.)
-1.2 to -47 (Adjustabl.)
':"5, -5.2, -6, -8, -9
-12, -15, -18, -24
N/A
N/A
N/A
N/A
2'
0.006
0.007
0.006
0.007
0.02
0.3
0.3
0.3
0.3
0.3
40
40
50
50
25
35 (9V,UV)
40 115V, '8V).
42 (24V)
LM320K
-5, -5.2, -6, -8, -9,
-12, -15, -18, -24
4
0.02
0.3
-5, -5.2, -6, -8, -9
-12, -15, -18, -24
4.
25
35
40
42
25
35
40
LM79XXC
-5, -5.2, -6, -8, -9
-12, -15, -18, -24
4
0.03
0.4
35,40 (24VI
64
80
75
70
64
75-80
70
66-70
LM137H,LM237H
LM337H
LM137HVH, LM237HVH
LM337HVH
LM337M
LMI20H, LM220H
LM320H
-1.2 to -37
-1.2 to -37
-1.2 to -47
-1.2 to -47
-1.2 to -37
0.006
0.007
0.006
0.007
0.007
0.02
0.02
0.02
0.3
0.3
0.3
0.3
0.3
0.6
0.6
0.6
40
40 .
77
77
77
77
77
-5.0, -5.2, -6, -8
-5.0, -5.2, -6,'-8
-5; -5.2, -6, -8
-9,-12,-15,-18,-24
N/A
N/A
N/A
N/A
N/A
2
4
4
4
,
LM320T
00
0.5
(Adjustable)
(Adjustable)
(Adjustable)
(Adjustable)
(Adjustable)
0.02
0.3
(9V, 12V)
(15V, 18V)
(24V)
(9V, 12V, 15V, 18V)
(24V)
77
77
64
80
75
70
LM.79MXX
-5,-6,-8,-12,-15,-24
4
0.03
0.7
50
50
40
25
25
25
35, (9V, 12V, 15V, 18V)
40 (24V)
35,40 (24V)
0.25
LM320ML
-5, -6, -8, -10,
-12, -15, -18, -24 .
4
0.01 .
0.5
35,40 (24V)
50-60
0.20
LMI20H~
-9,-12
-15, -18, -24
2
4
0.02
0.02.
0.1
0.1
35 (9V,12V)
40 (15V, 18V)
42 (24V)
70-80
-5, -6, -8, -9
-12, -15, -18, -24
-~, -12, -15, -18, -24
4
0.01
0.5
35,40 (24V)
60-65
4
0.02
0.6
35,40 (24V)
50-55
LM320M
LM220H
LM320H
0.10
LM320L
LM79LXXA
-
64
64
60-64
70-80
58-60
I
3.0
1.5
en
CL
~
1.0
I;2:
w
a::
a::
:::>
c.:>
I:::>
CL
I:::>
{
(
I
Q
Q
cDl
~
0.5
00
LM145K/LM245K/LM345K
lM1371lM2311lM331K STEEL
LM137HV!LM237HV/LM337HVK STEEL
-'SIV
,-47V
LM337T
-31V
0-
;2:
c:(
a::
00000
(J(;>(frtJ i(~i!~(j
LM320T
LM19XXCT
LM137HVH!LM237HVH/LM337HVH
-47V
.# _IADJU~TAB~E
LM137H/LM237H/LM337H
-31V
~ -: ADJUSTABLE
LM337MP
-37V
LM320MP
LM79MXXCP
""I
1
0.25
0.2
0.1
{
{
f;91/J(P(P
, ,
,
(
LM320LZ
lM19LXl(CZ
lM791XXACZ
0
K
KC
K STEEL
TO-3*
HERMETIC
tJ
T
TO-220
PLASTIC
C
P
TO-202
PLASTIC
I
~
H
TO·5, TO-39
HERMETIC
I
~
Z
TO·99
PLASTIC
-1.2V
I
-1.2V
-1.2V
I
I
'I
I
I
I
I
I
I/J(P(PP~
;,;, ;,
I
(?1f?(}>(1~
II
LM120H/LM220H
LM320H
PACKAGE
TYPE
I I
####
I
LM320MLP
I
PACKAGE
DESIGNATOR
~I
,
,
- ADJUSTABLE
"
E
-1.2V
00,00
LM120K/LM220K/LM320K, LM320KC, LM79XXCK(AL)
c:(
:::>
-1.2V
~'I
LM120H
LM220H
LM320H
I-
-1.2V
ADJUSTABLE
'{)I
I
I
,_ - ADJUSTABLE
;
j
I
I
ADJUrTAB\E
'I
.~~~~
#
~~.//.
~~~.~
I' 'I
'I I 'II
.~
-24 -18
-15
-12
-10
-9
-8 '-6
-5.2
if.
All devices with TO-3 package designators (K or K STEEL ) are supplied
in steel TO-3 packages unless otherwise
designated as {AU aluminum TO-3
package. All KC designated devices
are supplied in aluminum TO-3.
f
-5
Vo - NOMINAL REGULATEO OUTPUT VOLTAGE (V)
JOleln6al::l a6eliOA
BI-FETTiBI-FET IITM
Op Amp
AC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
en-EQUIV.
INPUT NOISE
VOLTAGE (nV/y'Hz)
(Note 2)
IB-MAX BIAS
CURRENT (pA)
(TJ = 25°C)
AVOL LARGE
SIGNAL VOLTAGE
GAIN (V/mV)
MIN (TA = 25°C)
5
5 (max)
5·
5 (max)
5
5 (max)
5 (max)
5 (max)
100
50
100
50
100
50
50
50
50
50
50
50
50
50
50
50
5
5
12
12
50 .
50
5
12
20
20
12
12
12
1.2
20
12
5
5
5
100
100
100
50
50
50
5
12
50
20
12
12
,10
LF351
10
LF351A
2
10
5.
LF351B
10
LF355
10
5
5 (max)
LF355A
2
10
5
LF356
5 (max)
LF356A
2
5.
LF357
10
5 (max)
LF357A
2
5 (max)
LFT355
0.5
5 (max)
LFT356
0.5
10
LF13741
15
BI-FET II DUAL OP AMPS (Characteristics for Each Amplifier) (Note 3)
.200
100
200
200
50
200
50
200
50
50
50
200
25
25
25
25
25
25
25
25
25
50
50
25
13
13
13
5
5
12
12
50
50
5
12
0.5
16
16
16
25
25
15
15
15
15
20
12
37
10
10
LF353
LF353A
2
10
LF353B
10
5
BI-FET II QUAD OP AMPS (Characteristics for Each Amplifier) (Note 3)
200
100
200
25
25
25
13
13
13
16
16
16
200
100
200
25
25
25
13
13
13
16
16
16
VOS - MAX OFFSET
VOLTAGE (mV)
(TA = 25°C)
PART NUMBER
eNOS/I:l.T - T.C. OF
VOS (p.vfC)
TYP
SR -SLI:W
RATE (V/p.s)
MILITARY BI-FET OP AMP (Note 1)
LF155
LF155A
LF156
LF156A
LF157
LF157A
LFT155
LFT156
5
2
5
2
5
2
0.5
0.5
INDUSTRIAL BI-FET OPAMP (Note 1)
.:..
o
5
LF255
LF256
5
LF257
5
COMMERCIAL BI-FET AND BI-FET II OP AMP (Note 3)
LF347
LF347A
LF347B
I'
10
2
5
'I
10
10
10
1
I
1
I
ADDITIONAL NS PRODUCTS USING
BI-FET TECHNOLOGY
SELECTION BY DESIGN PARAMETER
Max Input Offset
Voltage
(TA = 25°C)
Max Input Bias
Current
(TJ = 25°C)
.:...
0.5 mV
LFT155/LFT156
LFT355/LFT356
50pA
LF155A/LF156A/LF157A
LFT155/LFT156
LF355A/LF356A/LF357A
Typ Equivalent
Input Noise Voltage
per
f = 1000 Hz.
RS = lOOn
12 nV or Less
LF 156/LF 156A
LF157/LF157A
LFT156
LF256/LF257
Typ Slew Rate
0.5 YIlls
LF13741
VRZ.
2mV
LF 155A/LF355A
LF 156A/LF356A
LF357A
LF351A
LF353A
LF347A
LF356
LF356A
LF357
LF357A
5mV
LF351B
LF347B
LF3538
LF155/LF156/LF157
LF255/LF256/LF257
100 pA
LF155/LF156/LF157
LF255/LF256/LF257
LF351A
LF353A
LF347A
15 nV To 20 nV
LF351
LF155
LF351A
LF155A
LF351B
LFT155
LF347
LF255
LF347A
LF347B
LF353
LF353A
LF353B
5 VIlls
LF 155/LF 155A
LFT155
LF255
LF355/LF355A
LFT355
12 VIlls
LF156
LF156A
LFT156
LF256
LF356
LF356A
LFT356
13 VIlls
LF351
LF351A
LF351B
LF353
LF353A
LF353B
LF347
LF347A
LF347B
10 mV
LF355/LF356/LF357
LF351
LF353
LF347
200 pA
LF355/LF356/LF357
LF351 ILF351 B
LF347/LF347B
LF353/LF353B
LF13741
15 mV
LF13741
LF 111 Comparator
•
•
LF 198 Sample and Hold
•
LF 11201 Series of Analog Switches
•
LF 11331 Series of Analog Switches
•
LF 11508 Series of Analog Multiplexers
•
LF 152 Instrumentation Amplifier
•
LF13300 Integrating AID Building Block
25 nV To 37 nV
LF355
LF13741
LF355A
50 VIIl'
LF157
LF157A
LF357
LF357A
-
----------
------
dwV dO
~J 1.L3::1-18~.L.L3::1-18
Pressure Transducer
Selection Guide
TRANSDUCER ORDERING INFORMATION
LX1
-,...-
7
-,...-
03
A
- r - -,...-
FN
T,___
-
STANDARD OPTIONS
B
D
F
N
S
OF
FN
FS
- Backward Gage Version (PX6B, PX7B)
- High Common-Mode Differential Version (PX7DD)
- Fluid-FilledVersion (PX6F or PX4F)
-Nylon Package (PX7N)
- Stainless Steel Package (PX4S)
- Combine "0" and "F" Options (PX7DDF)
- Combine "F" and "N" Options (PX7FN)
- Combine "F" and "S" Options (PX4FS)
' - - - - - - - PRESSURE TYPE
A - Absolute
o - Differential
G - Gage
L -_ _ _ _ _ _ _ _
PRESSURE RANGE (See Selection Guide)
L-----------PACKAGETYPE
4 - Rugged Cylindrical Plumbed Fitting (PX4 Series)
6 - Hybrid IC for PCB Mounting (PX6 Series)
7 - Rugged Zinc or Nylon Housing with Optional
Plumbing (PX7 Series)
L----------~---DEVICETYPE
LX1 - Linear Transducer, Pressure
TRANSDUCER SELECTION GUIDE
MAXIMUM RATINGS
TYPICAL CHARACTERISTICS
Excitation Voltage
30V
Output Current
20 mA
Source
Sink
10 mA
20 mA
Transducer Bias Current
O°C to +85°C
Operating Temperature Range
Storage Temperature Range
-40°C to +105°C
Lead Soldering Temperature (10 seconds)
260°C
Output Voltage Sensitivity to Excitation Voltage
0.5%
Output Impedance
<50n
Electrical Noise Equivalent (O:s; f :s; 1 kHz) 0.04% Span
Natural Frequency of Sensor Diaphragm
> 50 kHz
Transducer Bias Current
7-10 mA
LX14XXA
LX16XXA,D,G
11-15~A
1·12
TRANSDUCER SELECTION GUIDE (Continued)
GUARANTEED SPECIFICATIONS
OPERATING MAXIMUM
PRESSURE
OVER
PRESSURE
RANGE
DEVICE
TYPE
OPERATING TEMPERATURE RANGE = O°C to 85"C
REFERENCE PRESSURE = 0 psi t
REFERENCE TEMPERATURE = 25°C
VE= 15VDC
SPAN CHARACTERISTICS
OFFSET CHARACTERISTICS
TEMP.
OFFSET
REPEATABILITY
CALIBRATION COEFFICIENT
±psi
V
±psitC
STABILITY
±psi
SENSITIVITY
CALIBRATION
mV/psi
TEMP.
COEFFICIENT
±psitC
LINEARITY
HYSTERESIS
REPEATABILITY
STABILITY
±psi
±psi
ABSOLUTE PRESSURE DEVICES
LX1601A(F). LX1701A(F)(N)
10 to 20 psia
40 pisa
2.5 ±0.5 t
0.0054
0.05
0.3
1.000 ±20
0.0054
0.05
0.05
LX1602A(Fl. LX1702A(F)(N)
o to 15 psia
40 psia
2.5 ±0.3
O.Q072
0.06
0.3
670 ±13
0.0072
0.07
0.06
LX1603A(F), LX1703A(F)(N)
o to 30 psia
o to 60 psia
o to 100 psia
o to 100 psi a
o to 300 psia
o to 300 psia
o to 1000 psia
o to 2000 psia
o to 3000 psia
o to 5000 psia
60psia
2.5 ±0.25
0.009
0.1
0.3
333 ±6
0.009
0.16
0.10
100 psia
2.5 ±0.25
0.018
0.2
0.6
167 ±3.3
0.018
0,36
0.24
150 psia
2.5 ±0.25
0.030
0.4
1.0
100 ±2
0.03
0.60
0.40
150psia
2.5 ±0.2
0.0216
0.4
1.0
100 ±2
0.0216
0.60
0.40
450 psia
2.5 ±0.25
0.090
1.0
2.0
33.3 ±0.67
0.09
2.0
1.0
450 psia
2.5 ±0.2
0.063
1.0
2.0
33.3 ±0.67
0.063
2.0
1.0
1500 psia
2.5 ±0.25
0.3
3.5
7.0
10 tD.2
0.3
6.0
3.0
3000 psia
2.5 ±0.25
0.6
7.0
14
5 ±0.1
0.6
20.0
7.0
4500 psia
2.5 ±0.25
0.9
10.0
20.0
3.33 ±0.067
0.9
30.0
10.0
5000 psia
2.5 ±0.25
1.5
17.0
35.0
2 ±0.04
1.5
75.0
17.0
LX1601G(Bl.LX1701G(B)(N)* -5 to +5 psig
40 psig
7.5 ±O.S
0.0054
0.05
0.3
1,000 ±20
0.0054
0.05
0.05
LX1611G(Bl.LX1711G(B)(N)* -5 to +5 psig
100 psig
7.5 ±0.5
0.0054
0.05
0.3
1,000 ±20
0.0054
0.05
0.05
40 psig
2.5 ±0.3
0.0072
0.06
0.3
0.0072
0.07
0.06
60 psig
2.5 ±0.25
0.009
0.1
0.3
670 ±13
. 333 ±6
0.009
0.16
40 psig
7.5 ±0.25
0.009
0.1
0.3
333:':6
0.009
0.16
~O
.0
100 psig
2.5 ±0.25
0.018
0.2
0.6
167 ±3.3
0.D18
0.36
0.24
LX1610A(Fl. LX1710A(F)(N)
LX1420A(F)(S)
LX1620A(F), LXl720A(F)(N)
LX1430A(F)(S)
LX1730A(F)(N) .
LX1440A(F)(S)
LX1450A(F)(S)
.:.
w
LX 1460A( F)(S)
LX1470A(F)(S)
GAGE PRESSURE DEVICES
LX1602G(B),LX1702G!B)(N)'
LX1603G( B),LX 1703G(B)(N) *
o to 15 psig
o to 30 psig
LX1604G(B), LX1704G(B)(N)' -15 to +15 psig
LX161 OG(B),LX 171 OG(B)(N)'
LX 1620G(B) .LXl720G(B)(N)'
LX1730G(B)(N)'
o to 60 psig
o to 100 psig
o to 300 psig
150 psig
2.5 ±0.2
0.0216
0.4
1.0
100 ±2
0.0216
0.60
0.40
450 psig
2.5 ±0.2
9·063
1.0
2.0
33.3 ±0.67
0 ..063
2.0
1.0
DIFFERENTIAL PRESSURE DEVICES
LX1601D(FI, LX170lDD(FI
-5 to +5 psid
40 psid
7.5 ±0.5
0.0054
0.05
0.3
1,000 ±20
0.0054
0.05
0.05
LX161lD(FI, LX171lDD(FI
-5 to +5 psid
100 psid
7.5 ±0.5
0.0054
0.05
0.3
1,000 ±20
0.0054
0.05
0.05
LX1602D(FI, LX1702DD(FI
40 psid
2.5 ±0.35
0.0072
0.06
0.3
670 ±13
0.0072
0.07
0.06
LX1603D(F), LX1703DD(F)
o to 15 psid
o to 30 psid
60 psid
2.5 ±0.3
0.009
0.1
0.3
333 ±6
0.009
0.16
0.10
LX1604D(Fl. LX1704DD(FI
-15 to +15 psid
40 psid
7.5 ±0.3
0.009
0.1
0.3
333 ±6
0.009
0.16
0.10
LX1610D(FI, LX1710DD(F)
o to 60 psid
o to 100 psid
o to 300 psid
100 psid
2.5 ±0.25
0.018
0.2
0.6
167 ±3.3
0.018
0.36
0.24
150 psid
2.5 ±0.2
0.0216
0.4
1.0
100 ±2
0.0216
0.60
0.40
450 psid
2.5 ±0.2
0.063
1.0
2.0
33.3 ±0.67
0.063
2.0
1.0
LX1620D(FI, LXl720DD(FI
LX1730DD(FI
~
tReterenee pressure tor LX1601A and LX1701A is 10 psia.
'Available as LX17XXGB or LX17XXGN
------
Ja:>npsueJ~
aJnSSaJd
...
(I)
PRESSURE TRANSDUCER FEATURE CHART
(1)(,)
... :::J
:::J"C
en en
enS:::::
(I) co
......
c.1-
~
,
Brass
Housing
Stainless
Steel
Housing
Nylon .Housing
Ceramic
Package
Zinc
Housing
High
CommonMode
Differential
Housing
FluidFilled
Isolator
Backward
Gage
Isolator
Product '
LX14XX
Absolute
LX14XXAF
LX14XXAFS
LX14XXA LX14XXAS
LX16XX
Absolute
LX16XXA
LX16XX
Gage
LX16XXG
LX16XXAF
LX16XXGB
,
LX16XX
Differential
LX16XXD
LX16XXDF
.-
LX17XX
Absolute
LX17XXAN LX17XXA
LX17XX
Gage
LX17XXGN
LX17XXAF
LX17XXAFN
LX17XXG
LX17XX
Differential
LX17XXGB
(Zinc)
LX17XXDD
LX17XXDDF
(Brass)
Package Key
TYPE
PACKAGE
LX14XXA(S)
PX4(S)
LX14XXAF(S)
PX4F(S)
LX16XXA
PX6
LX16XXG
PX6
,LX16XXGB
PX6B
LX16XXD(F)
, PX6D(F)
LX17XXA(F)(i\J)
PX7(F)(N)
LX17XXG(N)
PX7(N)
LX17XXGB
PX7B
LX17XXDD(F)
PX7DD(F)
1-14
r
-4"0
r
""' ""'
Q)(1)
CAUTION: DO NOT APPLY WRENCH
TORQUE HERE
::JUJ
UJUJ
c.C
:::I~L~~S STEEL
r---,,",
C""'
(')(1)
(1)
AVAILABLE
RED
VE
- i--------1
1~
""'
Vp 2~f::::::::::~r_------~f-------;
L --L=
GNo 3 LL---....j
_ _---:! ~----_1
10
(254) MIN
114-18
NPTS
0'25- 1
(6.35)~
2.5 MAX
(63.5)
--------------i
PX4(S)
1/4" NPT Pressure Transducer Package
Wt: 100 G
1l
4.300
10.0
(109'22)T(254'0)
1.430
(36.322)1'
.
J-T"""--;
.
0.250
(6.350)
~~~~~~
LEADS
~~~~E RED
GREEN
.t-.t--;
~BLACK
. -----------18 AWG WIRE
EPOXY PonlNG
1" HEAT SHRINK TUBING
TRANSDUCER GAGE PROTECTOR
PX4F(S)
1/4" NPT Pressure Transducer Package, Fluid Filled
Wt: 700G
-------l
0.330 I
r-
~(8.382)1-
0.260
(6604)
0.020
(0.508)
_
yp
•
! L·------1T
T
I r - - - - - - ,-
.j
0.820
D
0.420
(10.668)
TYP
-I- ~ I--------.----+--------t0.800
I~...:.
--L
0.400
0.100
(10.160) (2.540)
0.200
(5.080)
0.200
I I
0.750
I
0.200
'·1'~i[-(19'050)- ~
0.010
,
0.565
(1~;~1)
(0.254)
-I
---~
~ (::~~:I
OIA
PX6
0.2" Port, Hybrid Pressure Transducer Package
Wt: 5G
1-15
0.420
(10.668)
-------lI{B.3B2)--·
0.330 I
0.020
0.260
TT-T
I
G~~ ~
I
0.820
(ZO.82B)
I--
0420
(lO.6IiB)
(0.508)
Nt* J
NC* 4
~
j
VE 5
0400
(to. HiD)
0.100
(2540)
TVP
PX6B
0.2" Port. Hybrid Pressure Transducer Package
Wt: 5G
0.330
- .J
-l (8.382)
I~~
1
<
0.260
I
0.020
(D.50B)
(j~ T
0.420
_._- - - -~
0""" I~ un; T
-I
!
j __ __L_____ ~~: ~
082~J
0.200
VP-
GND 2
O.BOO
(20.320)
(20828)
~
VE 5
_
__~ _ _ _ _ _ _
0.420
(10.668)
-
-
--
'--'==----0
I
I
""., '; :' "~'i~-' 0""- 'i.
0.400
0.100
I
0200
0.7511
0.20D
~
(1~~~1)
0.010
(0.254)
.
-----.-L_
~ f-{::::)OIA
PX6D
0.2" Port, Hybrid Pressure Transducer Package
Wt: 5G
OUTPUT
BROWN
REO
-L-+-1~~1'--D-.5-31-1 ::~;i~
~2':5 ~
at
-1
~
~?
I
1.240
1032
'T~===::::I
I'T
(13.487)
1-~~~--t3~~.2) MIN~~--~-
~~-{315:D857} ~-~~-
-1'-
f--+--t----+--I
MOlDEO~
0. 672
(17.018)
j
1
0.974
_(24.140)
-~ 1,.314
~_~iJ4.~OO}
CONNECTOR
I
I
I
I
I~~--I
(17.526)
!_,____J
L
1{8.27 NPT TO 1/2 HEX
PX7
1/8" NPT Zinc Cast Pressure Transducer Package
Wt: 100 G (Zincl, 50 G (Nylon - With Identical
Mechanical Performance)
1,16
-t"O
......
Q)C'D
::::Jtn
tntn
I
@E)
Q,C
-;s
OUTPUT
BROWN
GROUND
RED
00 NOT {
CONNECT
EXCITATION
C'"
nC'D
...
1240
(JI.496)
ORANGE
CD
YELLOW
GREEN
~
-.~J
--1~--~ (J'~ D857)
(13481)
13
-(3302) MIN
--_.
I I
0. 612
MOlDED_~/
CONNECTOR
1
I
(17.018)1
,
J {24.~40}
D.914:
,'---'-,.-,-t-ror--L--..J
:
11.374
,I
",
I
0.690"
1--- (17.526)----
! ~:~_-~~'~r
'-118.21 NPl TO 1/2 HEX
PX7B
lIS" NPT Zinc Cast Pressure Transducer Package
Wt: 100 G (Zincl
BROWN
REO
ORANGE
OUTPUT
GROUND
i21.43B1
j
t
00 NOT {
CONNECT
YelLOW
EXCITATION
0.100
(2.540)
GREEN
D.S]! ]
1-(13.487)
.
TV'
f-------(J~~.2) MIN-----_f----(J'~~0851)----f
==e:=J==:1/
MOLDED/'
CONNECTOR
0.625
(15.875)
0.612
!i7.ii18i
~.....--"'--~~
0.375
0.690
I---117.526)
PX7DD
1/4" NPT Brass Pressure Transducer Package
Wt: 270 G
1-17
1.412
(35.865)
Section 2
Analog-to-Digitai
Converters
~National
Analog-to-Dig ital Converters
~ Semiconductor
»
!!l
c
N
ADB1200(MM5863) 12-Bit Binary AID Building Block
-8
i:
i:
(J1
(X)
general description
features
The ADB 1200 is the digital controller forthe LF13300D*
analog building block. Together they form an integrating
12·bit AID converter. The ADB1200 provides all the
necessary control functions, plus features like auto
zeroing, polarity and overrange indication, as well as
continuous conversion. The 12-bit plus sign parallel and
serial outputs are TR I-STA TE® TTL level compatible.
Th,e device also includes output latches to simplify
data bus interfacing.
•
•
•
•
•
•
•
•
•
•
*See LF 133000 data sheet for more information
en
-
w
12-bit binary output
Parallel or serial output
TRI·STATE output
Polarity indication
Overrange indication
Continuous conversion capability
100% overrange capability
5V, -15V power requirements
TTL compatible
Clock frequency to 1 MHz
circuit diagram/typical applications
12·8il AID Converter
15V
5V
POWER
GNO
":"
-15V
v16
VR
VR
v+
4
PG
17
Vx
ANALOG
GNO
":"
16
1M
Vx
RU-
AG
PO/RU+
15
14
22
21
20
DC
LF13300
Vss
VGG 25
26
COMP
2
COMP OUT
19
RR
24
RU-
PO/RU+
DC
RR
AOB12oo
12·6IT
BINARY
o.ol.F .
POLYPROPYLENE {
CAPACITOR
16
OG
GNO
2B
END OF
CONVERION
DIGITAL
GNO
250kHz
CLOCK.
INPUT
2·1
START
CONVERSION •
TRI·STATE'"
DATA OUTPUT
M
co
co
it)
:E
:E
o
-o
absolute maximum ratings.
",,,.
Supply Voltage (VSS)
Supply Voltage (VGG)
Voltage at Any Input
Operating Temperature
Storage Temperature
lead Temperature (Soldering, 10 seconds)
5.25V
-16.5V
5.25V
O°C to +70°C
-40°C to +150°C
3'00°C
N
iii
c
t,.,,,~
>-C
DATA FROM PREVIOUS CONVERSION·
Negative Inpllt
DC
256 X III
256 X Iff
256 X III
PD/RU+
RU-
4096 X III
RR
I
I : ; BI~2l<1ff I
COMP
EOC (liE)
r5tiL
r5ii1
FIGURE 3. COntinuo,us Conversion Mode
SCNO.i~!-I----'"
iiE~!-I-----------IL_______
EOCNO.i
....I
r:::-::::\j).---
TRI-STATE'"
DATA BUS-----....;.;.;;...;;.;.;.;.;.;;......-----<~
FIGUR&-4. ith AID ,Convertor Data Retrieval Sequence
2-6
typical applications
~
c
!!l
N
o
o
(Continued)
3C
3C
Multi AID Converter System on Common Bus
U1
(X)
CJ)
-
w
DATA BUS
~--~~----,
r----~~-----,
VXm
jth AID Converter
.
TRI·inATE" OUTPUTS TO DATA BUS
SC 2
EoC 23
AoBI200
ClK
VGG
25
27
VSS liE
24 3
PG~I;...._-+_.
V_~4;...._...
lF13300
VXj
15V -15V GNo
CONTROL AND POWER BUS
*May be common or separate. Care should be taken to avoid ground currents
**Oirect or multiplexed access to the processor
Note. This application is related to Figure 4 of timing diagrams
2·7
5V
DE
250 kHz EoC* * SC**
CLOCK NO. j NO. j
~
m
r-------------------------------------------------------------------------------------,
Analog-to-Digital Converters
:Ii
M
~National
::i
::i
ADC0800(MM43,57B/MM5357B) a-Bit AID Converter
lI')
-
'om
.....
Oll')
COM
o~
U::i
Q::i
20k
If the overall converter system requires lowpass filtering
of the analog input sign'ai, use a 20· kn or. less series
resistor for a passive RC s,ection or add an op am'p RC
active lowpass filter (with its inherent low output
resistance) to insure accurate conversions.
CLOCK COUPLING
The clock lead should be kept away from the analog
input line to reduce coupling.
LOGIC INPUTS
T-/le logical "1" input voltage swing for the Clock, Start
. Conversion and Output Enable should be (VSS - 1.0V).
'.
2·10
.
Application Hints
-»
3:0
(Continued)
CMOS will Satisfy this requirement but a pull-4P resistor
should be used for TTL logic inputs.
CONTINUOUS CONVERSIONS AND LOGIC CONTROL
RE-START AND DATA VALID AFTER EOC
Simply tying the EOC output to the Start Conversion
input will allow continuous conversions. but· an oscillation on lhis Iilie will exist during the first 4 clock periods
after EOC goes high. Adding a 0 flip-flop between EOC
(D' in'put) to Start Conversion '(0 output) will prevent
the oscillation and will allow a stoplcontinuous control
via the "clear" inpu't:
The EOC line (pin 9) will be in the low state for a maximum of 40 clock periods to indicate "busy". A START
pulse which occurs while the AID is BUSY will reset the
SAR and start a new conversion with the EOC signal
remaining in the low state until. the end of this new
conversion. When the conversion is complete. the EOC
line will go to the high voltage state. An additional 4
clock periods must be allowed to elapse after EOC goes
high. before a new conversion cycle is requested. Start
Conversion pulses which occur during 'this last 4 clock
period interval may be ignored (see Figures 1 and 2 for
high speed operation). This is only a problem for high
conversion rates and keeping the number of conversions per second less than (1/44) x fCLOCK automati·
,cally guarantees proper operation. For example. for an
800 kHz clock •. 18.000 conversions per second are
allowed. The transfer of the new digital data to the
output is initiated when EOC goes to the high voltage
state.
A second control logic application circuit is shown in
Figure 2_. This allows an asynchronous start pulse of
arbitrary length less than TC. continuously converts for
a fixed high level and provides a single clock period
start pulse to the AID. The binary counter is loaded with
a count of 11 when the start pulse to the AID appears.
Counting is inhibited uritil the EOC signal from the AID
goes high. A carry pulse is then generated 4 clock
periods after EOC goes high and is used to reset the
input RS latch. This carry pulse can be used to indicate
that the conversion is complete. the data has transferred
to the output buffers and the system is ready for a new
conversion cycle.
Standard supplies are VSS = 5V. VGG = -12V and
VDD = OV. Device accuracy is dependent on stability
of the reference 'voltage and has slight sensitivity to
VSS -' VGG. VDD has no effect on accuracy. Noise
spikes on the VSS and VGG supplies can cause improper
conversion; therefore. filtering 'each supply with a
4.7 J.lF tantalum capacitor is recommended.
(FROM
MM14C115
t~~~------i
START CONVERSION
(lOA/D)
C
CLEAR
JL A~~~Bg: ~.......>--+-t-<~---.....----,
CONVES:S~~~ -
....... - -....
FIGURE 1. Delaying an Asynchronous Start Pulse
JL
START
CONVERSION
-::[>~>------I""")o-"'::!....!:~:!.. START CONVERSION
(lOA/D)
READY fOR
NEXT CONVERSION
GND
Vee
1
<
Vee
I
(110
...... 0
OJ
3:
3:
(II
W
(II
To prevent missing a start pulse which may occur after
EOC goes high and prior' to the required' 4 clock
period time interval. the circuit of. Figure 1 can be used.
The RS latch can be set at any' time and the 4-stage
shift register delays the application of the start pulse
to the AID by 4 clock periods. The RS latch is reset
1 clock period after the AID EOC signal goes to the low
voltage state. This circuit also provic;!es a Start Conversion pulse to the AID which is 1 clock period wide.
POWER SUPPLIES
IL._ _- - - Ir
3:0
~O
We»
GND
D
Vee
1
FIGURE 2. AID Control Logic
2·11
.......
OJ
,,~-----------------------------------------------------------------------------,
m
,...
Application Hints (Continued)
It)
M
ZERO AND FULL-SCALE ADJUSTMENT
:i
:i
Zero Adjustment: This is the offset voltage required at
the bottom of the R-network (pin -5) to make the
"",,,, to 11111110 transition when the i"!put
voltage is 1/2 lSB (20 mV for a 10.24V scale). In most
cases, this, can be accomplished by having a 1 knpot on
pin 5. A resisto,r of 475n can be used lis, a non;adjustable
best approximation from pin 5 to ground.
It)
-
om
0""
co ,It)
OM
Full-SCale Adjustment: ,This is the offset voltage required
at the top of the R-network (pin 15) to make the
00000001 to 00000000 transition when the input
voltage is 1 1/2 lSB from full-scale (60 mV less than
full-scale,for a 10.24V scale)_ This voltage is guaranteed
to be within 2 lSB for the ADC0800. In most cases,
this can be accomplished by having a 1 kn pot on pin
15.
u~
Q:i
<~
Typical Applications
Ratiometric Input Signal with Tracking' Raference
General Connection
..v'....- - - - .
DV
-12V CLOCK
...
OUTPUT ENABL£
sc
EDt
10
POTtNTIDMtTRIC
TRAMSDUC.R
VIN
12
~---t-:=f
AD.....
Hi-Voltage CMOS Output Levels
+10V
AOtalaa
-tIV.
OV to 10V VIN range
OV to 10V output levels
Level Shifted Zero and Full-Scale for Transducers
.IV
A'
'"
Level Shifted Input Signal Range
,.
FULLSCAU
11
lI.nY
10
ADCDIDD
VREF
R2
'00
'"
YIII'' '
-12.
2-12
Rl and R2 cha"ge the effective input renge
by lV110 kfl
Typical Applications
(Continued)
VREF = 10 VOC With TTL Logic,Levels
1SVnc
1.4k
1%
2.7k
EDC
5Voc
4.99.
1%
*See application hints
A 1 and A2 = LM35BN dual op amp
VREF = 10 VOC With 10V CMOS Logic Levels
2.7k
15
6.9V OC
voco-"'V'VV....- - ,
15V
Tk
LM329DZ
S.9k
1%
EDC
ENABLE
OUTPUT
- lY oc
*See application hints
Input Level Shifting
15"
'-_~~
-5V TO SV INPUT
TO ADcaaoo
•
-lZV
6.8k
LMl36
lM3lB
I4r-H)4.....p-I
15" O-.....M,..........
Permits TTL compatible outputs with
OV to 10V input range (OV to -1 OV
input range achieved by reversing
polarity of zener diodes and returning
the S.Bk resistor to V-I.
, 10k
ADJUST FOR -5V
OUT WITH OV INPUT
MICROPROCESSOR INTERFACE
The sample program, as shown, will start the converter,
load the converter's output data into the accumulator,
keep track of the number of data bytes entered, complement the data and store this data into sequential
memory locations. After 256 bytes have been entered,
the control jumps to the user's program where proces-
Figure 3 and the following sample program are included
to illustrate both hardware and software requirements to
allow output data from the AOC0800 to be loaded into
the memory of a microprocessor system. For this example, National's INS8060, SC/MP II, microprocessor has
been used_
2-13
~
m
1'0
.."
('I)
.."
:t
:t
'"-
om
or-co""
0('1)
o~
Timing Diagram
C
(')
o
(X)
o
(X)
CLOCK
~
STAR T
50%
l>
C
~511'"
(')
o
(X)
o
(0
-OWS
AL
•
\50%
50%
----J
~
c--twAlE--:l
STABLE ADDRESS
'"
ADDRE SS SD%
~
's I- I -
'H
-:-?A'--_ _ _ __
STABlE-··
INPU T
-:...1J2lSB
I-:-
_:______X~__________
'.SD%f
TRISTATE
CONTRO L
••
50%
I
C
---tEOC
j
OUTPUTS ________________
. !.R! .T~E____--_-_-_-_-_-_--,-_-_-_-_-_-_-'-H~-~-\i~-------'-.,~::__
'c
FIGURE 5
Typical Performance Characteristics
1.5
;;t
..3
2
r---,----,----r--~
a
.:.
0.5
2:
~
.....
ct
Q
ex:
.....
0
ct
c.o
ii:
c.o
ii:
>
-0.5
I-
>
I-
-1
o
-1.5
0
1.25
2.5
3.75
5
o
1.25
2.5
3.75
VIN (V)
VIN (V)
FIGURE 6. Comparator liN vs VIN
(Vee = VREF = 5V)
FIGURE 7. Multiplexer RON vs VIN
(Vee = VREF = 5V)
2-23
5
0)
oeX)
Functional Description
u
Multiplexer: The device contains an 8-channel singleended analog signal multiplexer_ A particular input
channel is selected by using the address decoder_ Table
I shows the input states for the address linesto select
any channel. The address is latched into the decoder
on the low-to-high transition of the address latch enable
signal.
o
C
C
(Continued)
repeatability of the device. A chopper-stabilized comparator provides the most effective meth~d of satisfying
all the converter requirements.
The AID converter's successive approximation register
(SAR) is reset on the positive edge' of the start conversion (SC) pulse. The conversion is begun on the falling
edge of the start conversion pulse. A conversion in
process' will be interrupted by receipt of a new start
conversion pulse. Continuous conversion may be accomplished by tying the end-of-conversion (EOC) output to
the SC input. If used in this mode, an external start
conversion pulse should be applied after power up.
End-of-conversion will go low between 1 and 8 clock
PLJlses after the rising edge of start conver~ion.
The chopper·stabilized comparator converts the DC'
input signal into an AC signal. This signal is then fed
through a ~igh gain AC amplifier and has the DC level
restored. This technique limits the drift component of
the amplifier since the drift is a DC component which is
not passed by the AC amplifier. This makes the entire
AID converter extremely insensitive to temperature;
long term drift and input offset errors.
The most important section of the AID converter is the
comparator. It is this section which is responsible for the
ultimate accuracy of the entire converter. It is also the.
comparator drift which has the greatest influence on the
Figure 4 shows a'typical error curve for the ADC0808 as
measured using the procedures outlined in AN-179.
The characteristic is generated with the analog input
signal applied to the comparator inpu.t.
INFINITE RESOLUTION
PERFECT CONVERTER
. 111
:-FULL-8CAlE
-" ERRQR -1/2LSB
110
111
,
110
101
_J
101
100
L
-llSB
ABSOLUTE
ACCURACY
100
011
011
010
I -1/Z LSB
IQUANTIZATION
ERROR
010
001
000 .......- - - - - - - - - - V , N
0
Z 3 4
5 6 7
LSB
FIGURE 2. 3-Bit AID Transfer Curve
/
FIGURE 3. 3-Bit AID Absolute Accuracy Curve
U~~~~N~~:,~~ENT'LREFERENCE L I N E '
.
QUAN~~Z~~~{IIIIIIIIIIIIIIIIII_IIIIIIIIIIIIIIIIIII_IIIII11111111111111111111111111111111111111111111111111111III
ov
.
.
INPUT
VOLTAGE
FIGURE 4. Typicai'E;rror Curve
Connection Diagrams
DUAL-IN-LiNE PACKAGE
28
IN3
27
IN4
26
IN5
25
IN6
24
IN7
23
START
22
EOC
ADC080B.
AOCOB09
2-5
OUTPUT
ENABLE
CLOCK
VCC
REF(+)
GND
9
IN2
INI
INO
AOOA
ADO B
ADO C
ALE
21 2-1MSB
20 2-Z
I.
19
11
18
12
17
13
2-3
z-4
2-8LSB
16 REF(-)
2-7 14
15 2-6
TOPVIEW
2-25
n
o
Q)
oQ)
l>
C
n
oQ)
o
U)
0)
o
ex)
o
(J
C
~,"""""'----"REf(+1
DIGITAL OUTPUT
REFERENCED TO
GROUND
AJ
REFH
QOUT='~
VREF
4.75V S; Vee = VREF S; 5.25V
FIGURE 10. Ground Referenced Conversion System with
Reference Generating V CC Supply
FIGURE 11. Typical Reference and Supply Circuit
'V
DIGITAL OUTPUT
PROPORTIONAL TO
ANALOG INPUT
115V _ VIN _ J.15V
lN914
Z5V
REFERENCE
RA =Rs
*Ratiometric transducers
FIGURE 12. Symmetrically Centered Reference
2-27
01
o
CO
o
Typical Application
()
C
C
Timing Diagram
oo
(X)
.....
[-lIf--j
0)
CLOCK
~
STAR T
''''
l>
C
r-\.SD%
oo
I
[-'W'
(X)
LE
.....
.....
500/,
50'
--:--I ---IWALE
f-:: =
ADORE
"''''
STABLE ADDRESS
I
,
50'
lsI--
-
rlH
, INPU T
~
::
STABLE
1--~1I2LSB
-
X
:
10-
,
'®
TRI·STATE
CONTRD l
EDe
tEoe
50
J
SD'~
Ie
FIGURE 5
Typical Performance Characteristics
2
1.5
:i
.3
~
-'
-0.5
>
I-
I-
-1
o
-1.5
0
1.25
2.5
3.75
5
o
1.25
2.5
3.75
VIN (VI
VIN (VI
FIGURE'G. Comparator liN vs VIN
(Vee = VREF = 5V)
FIGURE 7. Multiplexer RON vs VIN
(Vee = VREF= 5V)
2·33
5
I"'I""
co
o
o
C
C
(Continued)
The AID converter's successive approximation register
(SAR) is reset on the positive edge of the start conver·
sion (SC) pulse. The conversion is begun on the falling
edge of the start conversion pulse. A conversion in
process will be interrupted by receipt of a new start
conversion pulse. Continuous conversion may be accom·
plished by tying the end·of·conversion (EOC) output to
the SC input. If used in this mode, an external start
conversion pulse should be applied after power up.
End·of·conversion will go low between 1 and 8 clock
pulses af~er the rising edge of start conversion.
repeatability of the device. A chopper·stabilized com·
parator provides the most effective method of satisfying
all the converter requirements.
The most important section of the AID converter is
comparator. It is .this section which is responsible for
ultimate accu(acy of the entire converter. It is also
comparator drift which has the greatest influence on
Figure 4 shows a typical error curve for the ADC0816 as
The chopper·stabilized comparator converts the DC
input' signal into an AC signal. This signal is then fed
through a high gain AC amplifier and has the DC level
restored. This technique limits the drift component of
the amplifier since the drift is a DC component which' is
not passed 'by the AC amplifier. This makes the entire
AID converter extremely insensitive to temperature,
long term drift and input offset errors.
the
the
the
the
measured using the procedures outlined in AN-179.
The characteristic is generated with the analog input
signal applied to the comparator input.
INFINITE RESOLUTION
i--FULl-SCALE
-..
ERRQR"1/2lSB
PERFECT CONVERTER
111
110
101
101
10'
.,,
L
-'LSB
ABSOLUTE
ACCURACY
IDO
011
OIl
I~ IlUANTlZATION
-112 LSB
DlO
ODI
UL.,-.,-...,,------VIN
ERAOR
DO'I<.1..--------VIN
o 1 2 3 4 5 6 7
lSB.
FIGURE 2. 3-Bit AID Transfer Curve
FIGURE 3. 3-Bit AID Absolute Accuracy Curve
~~~~~~N:~:I~~ENTIAL
/REFERENCELINE
QUAN;~z~~g(IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII.11111111111111111111111111111111111111111111111111111111111111111111
ov
INPUT
VOLTAGE
FIGURE 4. Typical Error Curve
Connection Diagram
Dual·ln·Line Package
40
•
INJ
IN4
39
INS
IN6
INZ
INI
EXPANSION CONTROL
IN7
INB
AOUA
ADD B
IN9
ADD C
INID
INII
ADDD
ALE
AOCOSI6.
AUCOB1l
INIZ
INI4
Z-I MSB
z-Z
Z-3
EOC
Z-4
INIS
Z-5
2-6
Z-7
INll
COMMON
START
VCC
Z-B LSB
REF!-I
• COMPARATOR IN
REF!+I
GNU
0)
.....
0)
~
111
110
no
CLOCK
ZO
TRI·STATE® CONTROL
TOP VIEW
2-35
l>
C
n
o
0)
.....
......
,...
,....
ex)
o
u
c
<
~
CO
,....
ex)
o
u
c
<
Applications Information
OPERATION
Ratiometric Conversion
The ADC0816, ADC0817 is designed as a complete
Data Acquisition System (DAS) for ratiometric conversion systems. In ratiometric systems, the physical
variable being measured is expressed as a percentage of
full-scale which is not necessarily related to' an absolute'
standard. The voltage input to the ADC0816 is expressed
by the equation '
Ox
These limitations are automatically satisfied in' ratiometric systems and can be easily met in ground referenced systems.
Figure 9 shows a ground referenced system with a
separate supply and reference. In this system, the supply
must be trimmed to match the reference voltage. For
instance, if a 5.12V reference is used, the supply should
be adjusted to the same voltage within 0.1 V.'
(1)
VIN';' Input voltage into the 'ADC0816
Vfs = Full-scale voltage,
Vz = Zero voltage
Ox = Data point being measured
DMAX = Maximum data limit
DMIN. '" Minimum data limit
A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the
wiper is directly proportional to the output voltage
which is a ratio of the full-scale voltage across it. Since
the data is represented as a proportion of full-scale,
. reference requirements are greatly reduced, eliminating
a large source of p.rror and cost for many applications.
A major advantage of the ADC0816, ADCOS17 fs that
the input voltage range is equal to the supply range so
the transducers can be connected directly across the
supply and their outputs connected directly into the,
multiplexer inputs, (Figure 8).
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc."are
suitable for measuring proportional relationships; however, many types of measurements must be referred to
an absolute standard such as voltage or current. This
means a system reference must be used which relates
the full-scale voltage to the standard volt. For example,
if Vee = VREF = 5.12V, then the full-scale range is
divided into 256 standard steps. The smallest standard
step is 1 LSS which is then 20 mV.
The ADeOS16 needs less ,than 'a milliamp of supply
current so de~eloping the supply from the reference is
readily accomplished. In Figure 10 a ground referenced
system' is shown which "generates the 'supply from the'
reference. The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current
and the desired bus drive, or if a capacitive bus is driven
by the outputs a large capacitor will supply the transient
supply current as seen in Figure 11. The LM301 is
overcompensated to insure stability when loaded by the
10 IlF output capacitor.
The top and bottom ladder voltages cannot exceed
Vee and ground, respectively, but they can be symmetrically less than Vee and greater than ground. The
center of the ladder voltage should always be near the
center of the supply. The sensitivity of the converter
can be increased, (i.e., size of the LSB steps decreased)
by using a symmetrical reference system. In Figure 12,
a 2.5V reference is symmetrically centered about Vec/2
since the same current flows in identical resistors. This
system with a 2.5V reference allows the LSB bit to be
half the size of a 5V,reference system.
Converter Equations
The ,transition between adjacent ,codes Nand N + 1
is given by:
VIN =
,
~REF(+)
[..!::..
,256
+ _1_] ±VTUE
512
(2)
The center of an output code N is given by:
Resistor Ladder Limitations
VIN = VREF(+)
,
The voltages from the resistor I,adder are comp'ared to
the selected input S times in a conversion. These voltages
are coupled to the comparator via an analog switch, tree
which' is referenced'to the supply. The voltages at the
top, center and bottom of the ladder must be controlled
to maintain proper operation.
[~]
256
±VTUE
(3)
The output code N for 'an arbitrary input are the integers
within the ran'ge:
VIN
N = - - - x 256 ±Absolute Accuracy
VREF(+)
The top of the ladder, Ref(+), should not be more positive than the supply, and the 9~ttom of the ladder
Ref(-) should not be more negative than ground. The
center of the ladder voltage must also be near the
center of the supply because the analog switch_ tree
changes from N-channel switches to P-channel swit¢hes.
(4)
where: VIN = Voltage at comparator input
VREF(+) = Voltage at Ref(+)
VREFH =GND
VTUE = Total unadjusted error volta~e(typicall.y
VREF{+)/512)
2-36
Applications Information
»
c
(')
(Continued)
o(X)
..10
~
r - - - - - - i v"
r---'iREHt)
DIGITAL
OUTPUT
DIGITAL
OUTPUT
REFERENCED
TO
GROUND
PROPDRTlO~Al
TO ANALOG
INPUT
QOUT=
~=
VREF
QOUT=~
VIN
Vee
VREF
4.75V S; Vee =,vReF S; 5.25V
4.75V S; Vee = VREF S; 5.25V
*Ratiometric transducers
FIGURE 8. Ratiometric Conversion System
FIGURE 9. Ground Referenced
Conversion System Using Trimmed Supply
lD- 15V OI:
1k
AI
LMJ2911
~A1:-2- - ;
IDT
DIGITAL OUTPUT
REfERENCED TO
10DllpF
Vc£
>--::t
14
'!J...
12
2-1
"blOb'b'b'b'b'b'!'b' ,
2-12
Note: 3 bits shown for clarity
Pawer Dissipation vs
Supply Current vs
Temperature
Supply Voltage
2.5
100 HZ~fCIK :::::;2jO kHz
2.25
~
2
z
co
1.5
~
1.25
\
~
co
A~ LOGl'C ';.g;:.
~
·V+.pIN23~Glc"I·· --- f.v+. piN 23
I\.
\
~
I\.
a: 0.15
~
l1!
TA=25'C
'\. iJA '4h'cNi -
V
f.-
"\
0.5
0.25
o
25
50
75
100
125
150
o
10
15
'SUPPLY VOLTAGE (±VI
TEMPERATURE ('CI
applications information
THEORY OF OPERATION
will remain unchanged (high). This process will continue
until the LSB (00) is found. When the_ conversion
process is completed, it is indicated by CONVERSION
'COMPLETE (CC) (pin 14) going low. The logic levels at
the data output pins (pins 1-12) are the complementedbinary representation of the converted analog signal with
all being the MSB and 00 being the LSB. The register
will remain in the above state until the SC is again taken
low.
The ADC1210, ADC1211 are successive approximation
analog-to- VCC. Example: V+ = 10.24V, System VCC = 5V
VCC"15V
15VJUl
~
OV
SYSTEM
CLOCK 0-
H>-
--'.!L
Q11 12
9
,
0' •
O.
MM74C9Dl
.JMSB
1..._
~~
09 10
o.
Cp
ZRAIZ1:1OK.
1
14
DID 11
.........!!.
..,
r
V'fV
MM74C90&
OR
15Vn
OV
START 0-
MM14C902
.=lJ
ADC1Z10.
ADelll!
~ -1!.!f
,
1/2
-=
~14
r-
1--
-..,
I...
--
_...J
R:~:NI
05~
DIGITAL
OUTPUTS
I
o.r!-14
cc
OJ
f!.-
Q2~
MM74C906
o'fl00 f-l--
----
Lsa
o:!:-
Vee
. :J;DNVERSlO
COMPLETE
'11
1/6MM74C9D6
FIGURE 4. InterfaCing an ADC1210, ADC1211. Running on ':1+
10k
< VCC.
Example: V+ = 5V, VCC =15V
puts must be stable .logic "0"). Offset Null is accom·
plished by then applying an analog input voltage equal
to 1/2 LSB at" pins 18 and 19. R2 is adjusted until the
LSB output flickers equally between logic "1" and
logic "0" (all other bits are stable), In the circuit of
Figure 6, the ADC1210, ADC1211 is configured for
Complementary Binary logic and the values shown are
for V+ = 10.240V, VFS = 10.2375V, LSB = 2.5 mV.
OFFSET AND FULL SCALE ADJUST
A variety of techniques may be employed to adjust
Offset and Full Scale on the ADC1210, ADC1211. A
straight·forward Full' Scale Adjust is to incrementally
vary V+ (VREF) to match the analog input voltage.
A recommended technique is shown in Figure 6. An
LM199 and low drift op amp (e.g., tne LHOb44) are
used to provide the precision refer~nce. The ADC1210,
ADC1211 is put in the continuous convert mode by
shorting pins 13 and 14. An analog voltage equal to
VREF minus 1 1/2 LSB (10.23625V) is applied to pins
18 and 19, and- R1 is adjusted until the LSB flickers
equally between logic "1" and logic "0" (all other out·
An alternate technique is shown in Figure 7. ,In this
instance, an LH0071 is used to provide the reference
voltage. An analog input voltage equal to VREF minus
1 112 LSB (10.23625V) is applied to pins 18 and 19.
2-45
........
N
applications information
(j
(Continued)
v+(VAEF)
Q
~c;,~--' ~r-- - - - - ----:-----1
o
I
C
..
~
0.1%
....N
9
l>
C
o
....
........N
CLOCK
IS.
-15V
-I5V
FIGURE 6. Offset and Full Scale Adjustment for Complementary, ~inary
R1 is adjusted until the LSB output flickers equally
between logic "1" and logic "0" (all other outputs must
be a stable logic "0"). For Offset Null, an analog voltage
equal to 1/2 LSB (1.25 mV) is then ,applied to pins 18
and 19, and R2, is adjusted until the LSB output flickers
equally between logic "1" and "0".
FU~L SC~LE r-
RANGE=1 LSB
111
lID
Q
I
~
Q
INPUT VOLTAGE
(OVTO lD.Z315V)
101
IDO
011
1-
010
-RANGE
001
ZERO SCALE
DOO
15.
o
1
2
J
4
5
6
7
8
ANALOG INPUTV9LTAGE
FIGURE 8. Quantization Uncertainty
of a Perfect 3-Bit AID
-15V
CLOCK
offset the converter 1/2 LSB in order to reduce the
Uncertainty to ±1/2 LSB as shown in Figure 9. Rather
than +1, -0 bit shown in Figure 8. Quantization Uncer·
tainty can only be reduced by increasing Resolution.
It is expressed as ±1/2 LSB or as an error percentage of
full scale (±0.0122% FS for the ADC1210).
iULL~CA~T J
I
-15V
11
FIGURE 7. Offset and Full-Scale Adjustment
Technique Using LH0071
w
B
5
In both techniques shown, adjusting the Full·Scale first
and then Offset minimizes adjustment interaction. At
least one iteration is recommended as a self-check.
I 01
~
I DO
~
011
~
Q
DEFINITION OF TERMS
1ID
I
Ill\, RANj' MllDPOlrT
10
~ I- 1/"" OFFSET I
DO
Resolution: The Resolution of an A/D is an expression
of the smallest change in input which will increment
(or decrement) the output from one code to the next
adjacent code. It is defined in number of bits, or 1
part in 2n. The ADC1210 and ADC1211 hav,e a resolu·
tion of 12 bits or 1 part in 4,096 (0.0244%).
a
1
2
3· 4
5
I
a
7
8
ANALOG INPUT VOL lAGE
FIGURE 9. Transfer Characteristic Offset
1/2 LSB to Minimize Quantizing Uncertainty
Linearity Error: Linearity Error is the maximum devia·
,tion from a straight line passing through the end points
of the A/D transfer characteristic. It is measured after
calibrating Zero and Full Scale Error. The Linearity
Error of the ADC1210 is guaran~eed to be less than
±1/2 LSB or ±0.0122% of FS and ±0.048B% of FS for
the AD1211. Linearity is a performance characteristic
intrinsic to the device and cannot be externally adjusted.
Quantization Uncertainty: Quantization Uncertainty is
a direct consequence of the resolution of the converter.
All analog voltages within a given range are represented
by a single digital output cod~. There is, therefore, an
inherent conversion error even for a perfect A/D. As an
example, the transfer characteristic of a perfect 3·bit
A/D is shown in Figure 8.
Zero Scale Error (or Offset): Zero Scale Error is a
measure of the difference between the output of an
ideal and the actual AID for zero input voltage. As
shown in Figure 10, the effect of Zero Scale Error is
to shift the transfer characteristic to the right or left
along the abscissa. Any voltage more negative than the
LSB transition gives an output code of 000. In practice,
therefore, the voltage at which the 000 to 001 transition
As can be seen, all input voltages between OV and 1V
are represented by an output code of 000. All input
voltages between lV and 2V are represented by an
output code of 001, etc. If the midpoint ofthe range is
assumed to be the nominal value (e.g., 0.5Vl, there is an
Uncertainty of ±1/2 LSB. It is common practice to
2-47
,..
,..
N
(3
C
«
o
,....
,....
N
(J
C
«
applications information
(Continued)
takes place is ascertained, this input voltage's departure
from the ideal value is defined as the Zero Scale Error
(Offset) and is expressed as a percentage of FS. In the
example of Figure 10, the offset is 2 LSB's or 0.2B6%
of FS.
.
output impedance and input resistors R25, R26, R27,
and R28. The gain error may be adjusted to zero as
outlined in the Applications section.
Monotonicity and Missing Codes: Monotonicity is a
property of a D/A which requires an increasing or
constant output voltage for an increasing digital input
code. Monotonicity of a D/A converter does not, in
itself, guarantee that an A/D built with that D/A will
not have missing codes. However, the ADC1210 and
ADC1211 are guaranteed to have no missing codes.
The Zero Scale Error of the ADC1210, ADC1211 is
caused primarily by offset voltage in the comparator.
Because it is common practice to offset the A/D 1/2 LSB
to minimize Quantization Error, the offsetting techniques
described in the Applications Section may be used to
null Zero Scale Error and accompl ish the 1/2 LSB
offset at the same time.
Conversion Time: The ADC1210. ADC1211 are succes·
sive approximation A/D converters requiring 13 clock
intervals for a conversio~ to specified accuracy for the
ADC1210 and 11 clocks for the ADC1211. There is
a trade· off between accuracy and clock frequency due
to settling time of the ladder and propagation delay
through the comparator. By modifying the hysteresis
network around the comparator, conversions with 10·
bit accuracy can be made in 30 f.1s. Replace RA, RB
and CA in Figure 5 with a 10 MQ resistor between
pin 23 (Comparator Output) and pin·17 (+ IN), and
increase the clock rate to 366 kHz.
Full Scale Error (or Gain Error): Full Scale Error is a
measure of the difference between the output of an
ideal A/D converter and the actual AID for an input
voltage equal to full scale. ·As shown in Figure 11, the
Full Scale Error effect is to. rotate the transfer charac·
teristic angularly about the origin. Any voltage more
positive than the Full Scale transition gives an output
code of 111. In practice, therefore, the voltage at which
the transition from 111 to 110 occurs is ascertained.
The input voltage's departure from the ideal value is
defined as Full Scale Error and is expressed as a per·
centage of FS. In the example of Figure 11, Full Scale
Error is 11/2 LSB's, or 0.214% of FS.
In order to prevent errors during conversion, the analog
input voltage' should not be allowed to change by more
than ±1/2 LS8. This places a maximum slew rate of
12.5 f.1V /f.1S on the analog input voltage. The usual solu·
tion to this restriction is to place a Sample and Hold in
front of the A/D. See AN·154 for additional information.
Full Scale Error of the ADC1210, ADC1211 is due
primarily to mismatch in the' R·2R ladder equivalent
Q
Q
Q
111
8
~
~ 110
101
~
~
~
RESPONSE
WITH OFFSET
100
"
~
IDEAL
RESPONSE
011
"
110
~E~S~~C:HL;~~ROIR
001
~2
-1
0
1
2
3 4
5 6
7
110
101
100
011
010
8
~
001
ODD
0'0
GAi. ,lRO~"""',::;:
J
111
o
1
'DEIAL ~ESPrNSf-
x:
2
J
4
5
6
18
..
ANALOG INPUT VOLTAGE
ANALOG INPUT VOLTAGE
FIGURE 10. AID Tra"sfer Characteristic with Offset
FIGURE 11; Full Scale (Gain Error)
ordering information
PART NUMBER
ADC1210HD, ADC1210HN
ADC1210HCD, ADC1210HCN
ADC1211HD, ADC1211HN
ADC1211HCD, ADC1211HCN
OPERATING TEMPERATURE
RANGE
-55°C to +125°C
-25°C to +85°C
-55°C to +125°C
-25°C to +85°C
See NS Package D24A or N24A
2-'48
25°C
LINEARITY
0.01%
0.01%
0.05%
0.05%
l>
~""atjonal
~ '\,ierniconductor
Analog-to-Digital Converters
n
w
(J1
;,
ADC3511' 3%-Digit
M~cw'prc'~ ~ssor Compatible AID Converter
ADC _,711' 3 3/4-Digit
Microprocessor Compatible AID Converter
.'
C
\
Genet"( De!?,cription
...I.
...I.
l>
C
n
w
......
...I.
...I.
The ADC3~,! 1 and ADC3711 (MM74C937-1, MM74C9381) monolith;c AID converter ci rcuits are manufactured
using standard complementary MOS (CMOS) technology.
A pulse modulation analog-to-digital conversion technique is used and requires no external precision
components. In addition, this technique allows the use
of a reference voltage that is the same polarity as the
input voltage.
conversion input and a conversion complete output are
included on both the ADC3511 and the ADC3711.
Features
•
•
•
•
•
'"
Operates from single 5V supply
ADC3511 converts 0 to ±1999 ,counts
ADC3711 converts 0 to ±3999 counts
Addressed BCD outputs
No external precision components necessary
Easily interfaced to microprocessors or other digital
systems
.. Medium speed-200 mslconversion
One 5V (TTL) power supply is required. Operating
with an isolated supply allows the conversion of positive
as well as negative voltages. The sign of the input voltage
is automatically determined and indicated on the sign
, pin_ If the power supply is not isolated, only one polarity
of voltage may be converted.
• TTL compatible
• Internal clock set with RC network or driven externally
.. Overflow indicated by hex "EEEE" output reading as
well as an overflow output
The conversion rate is set by an internal oscillator.
The frequency of the oscillator can be set by an external
RC network or the oscillator can be driven from an
external frequency source. When using the external RC
network, a square wave output is available.
Applications,
The ADC3511 and ADC3711 have bee." designed to
provide addressed BCD data and are intended for use
with microprocessors and other digital systems. BCD
digits are selected on demand via '2 Digit Select (DO, 01)
inputs. Digit Select inputs are latched by a low-to·high
transition on the Digit Latch Enable (OLE) input and
will remain latched as long as OLE remains high. A start
•
•
Low cost analog-to·digital converter
Eliminate analog multiplexing by using remote AID
converters
., Convert analog transducers (temperature, pressure,
displacement, etc.) to digital transducers
Dual-In-Line Package
Connection Diagram
Vee
....!
ANALOG Vee
.2
u
!!. 2'
.!!. 2°
.£. vss
22.2
....!
!!.. 01
OVERFLOW...!!
.!!!.. DO
23
CONVERSION COMPLETE
-.!
.!!. OLE
START CONVERSION
..!..
.!!. fOUT
SIGN
-.!
.!!.. fiN
VFlLTER
....!!
.!!. V;'EF
.!!. SWI
VINI_'...!.!!
~SW2
VINI;'..!.!
VFB
Order Number ADC3511CCN
,
or ADC3711CCN
See NS Package N24A
.!1.. ANALOG GNO
,.g
TOP VIEW
2-49
,....
,....
.....
M
U
C
C
4.75V ~ VCC ~ 5.25V; -40°C ~ TA ~ +85°C,
n
= 5 conv./sec (ADC3511CC); 2.5 conv./sec (ADC3711CC); unless otherwise specified.
CONDITIONS
PARAMETER
Norl-Linearity
VIN
= 0-2V Full Scale
= 0-200 mV Full Scale
VIN
= OV
VIN
Offset Error
........
MIN
TVP
(Note 2) .
MAX
UNITS
--0.05
±0.025
+0.05
% of Full·Scale
(Note 3)
-1
-Quantization Error
W
U1
+0
-0.5
+1.0
Counts
+3.0
mV
(Note 4)
Rollover Error
-0
Analog Input Current
VIN+, VIN-
-5
TA = 25°C
±1
+0
Counts
+5
nA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditionsfor
actual device operation.
Note 2: All typicals are given for TA = 25'C.
Note 3: For the ADC3511CC: full .. cale = 1999 counts; therefore 0.025% of full-scale = 1/2 count and 0.05% of full-scale = 1 count. For the
ADC3711CC: full-scale = 3999 counts; therefore 0.025% of full-scale = 1 count and 0.05% of full-scale = 2 count . .
Note 4: For full .. cale = 2.000V: 1 mV = 1 count for the ADC3511 CC; 1 mV = 2 counts for the ADC3711 CC.
Block Diagram
ADC3511 3 1/2·Digit AID (*ADC3711 3 3/4-Digit A/D)
JII2f3J/4j·DIGIT
LATCH
A.
81
C1
p.
A2
82
C2
STAAT CONY
D2
16:4
AJ
MUX
53
C3
OJ
.
A•
DIGITAL TIMING
AND CONTROL
FRED-IN
co
.0 •
•02
fREQOlJ.,r
10J
10.
COMPARATOR
TIMING
,--.......
+
DIGITAL Vee
OVERFLOW
ROM
L-----------------_DVERFlOW
~_-+--+-----+
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CONVCOMPLETE
L....-------------------_foSl.N
100
--+--+-----+
ANALOG Vee .....
VFILTER
---t--+--,
SW2
....- - - - - - - - - - - - - - - - - - - - - - - - -..............
-VIN ..........+-EH~-_++--
v" .....-------...1
2·51
-VREF
l>
C
n
W
..........
....
,...
,...
I'
Applications, Information
U
THEORY OF OPERATION
Ct)
o
C
n
w
.....
.....
.....
Truth Table
DIGIT SELECT INPUTS
OLE
DO
01
L
L
L
L
H
L
L
L
H
H
X
SELECTED DIGIT
Digit 0 (LSD)
L
H
L
H
Digit 1
Digit 2
Digit 3 (MSD)
X
Unch;mged
= Low logic level
H ~ High logic level
. X ~ Irrelevant logic level
The value of the Selected Digit is presented at the 23 , 22, 21
and 2 0 outputs in BCD format.
Note 1: If the value of a digit changes while it is selected,
that change will be reflected at the outputs.
Note 2: An overflow condition will be indicated by a high
level on the OVERFLOW output (pin 5) and E16 in all digits.
Note 3: The sign of the input voltage, when these devices are
operated in the bipolar mode, is indicated by the SIGN output (pin 8). A high level indicates a positive voltage, a low
level a negative',
Timing Diagrams
Vee
OLE
GNO
vee
DO,OI
GNO
VOH
23,22,2 1,2 0
GND
Typical Applications
Figure 4 shows the ADC3511 and ADC3711 connected
to convert 0 to +2.000 volts full scale operating froin a
non-isolated power supply. (Note that the ADC3511
converts 0 to +1999 counts full scale, while the ADC3711
converts 0 to +3999 counts full scale.) In this configuration the SIGN output (pin 8) should be ignored. Higher
voltages can, of course, be converted by placing fixed
dividers in the inputs, while lower voltages can be con-'
verted by placing fixed dividers in the feedback loop,
as shown in Figure 6.
Figures 5 and 6 show systems operating with isolated
supplies that will convert both polarities of inputs. 60 Hz
common-mode noise can become a problem' in these
2-54
configurat,ions, so shielded transformers have been shown
in the figures. The necessity for, and the type of shielding
needed depends on the performance requirements, and
the actual applications.
The filter capacitors connected to VFB (pin 12) and.
VFIL'fER (pin 11) should' be of a low leakage variety.
In the examples shown every 1.0 nA of leaka~ will
cause approximately 0.1 mV error (1.0 x 10 A x
100 kO = 0.1 mV). If the currents in both capacitors are
exactly equal 'however, little error will result since the
source impedances driving both capacitors are approximately matched.
Typical Applications
»
c
(Continued)
n
~
(J1
........
23 22 21 20 01 DOOLE
tj
»
c
5V
If''
+
IDVal:
ZVREFERENCE
Vee
,I
r---
ANALOG Vee
,'f--
I
I
I
I
I
'---22
,3
ADC3511CC
(ADel111CC)
Vss
'Ir----
OVERFLOW
0'
CONVERSION
COMPLETE
START
CONVERSION
OLE
7.",
fOUT
I.~
'"
: m,\%
D47";~
VINI_}
SWIr---
VINI+)
swz
NDTEl _ _
r--
2D
VREF
VFILTER
ANALOG
G.DUND
v"
lOOk
T~
~~
Jj ~
II
1
NOTE 3
Il'OOOtl%
.3
......
....
....
I
lOOk
V'N
~
I ,
I
I
I
I r
I I
lOki
I
I
IN9I. ~ r I
lN914
I'N ~,l"F
SIGN
n
--,
L_
r
omEi"l
ADJUST
lM316
}.I
J.G ~ r+.:
- .I
~
lOOk
SDk
I
I
_.1
L
22M
I
I
Note 1: All resistors 1/4 watt, and
.±S%, unl ess otherwise specified .
Note 2: All capacitors ±10%.
Note 3: Low leakage capacitor.
Note 4:
R1R2
R3 = R1 + R2 ±25n.
\\
~
GND
SIGNAL
GND
FIGURE 4. 3 1/2-Digit AID; +1999 Counts, +2.000 Volts Full Scale
(3 3/4-Digit AID; +3999 Counts, +2.000 Volts Full Scale)
23 22 2' 20 01 DO OLE
Vee
ANALOG Vee
",3
ADC1511CC
(ADel111CC)
OVERFLOW
2V REFERENCE
,I
r---
"
I
I
I
I
I
Vss
DI
DO
OLE
--,
'"
r
}RI
m
VIN(_)
m
VINt+)
}R2
I
I
I
lN914
I
lOki
I
I I
I
.I
L
OmEV
ADJU~T
lOOk
SDk
I
I
I
I
_.1
Note 1: All resistors 1/4 watt, and
22M
±5%, unless otherWise specified.
Note 2: All capaCitors.!: 10%.
Note 3:
Note 'I:
FIGURE 5.3 1/2-Digit AID; ±1999 Counts, ±2.000 Volts Full Scale
(3 3/4-Digit AID; ±3999 Counts, ±2.000 Volts Full Scale)
2-55
Low leakage capacitor.
R1 R2
R3 = R1 + R2 '25H.
,....
;:::
Typical Applications
(Continued)
('I)
(;)
C
lALOG
'"
{AGI
ANAlDIi
UNKNOWN
INPUT
IVxl
OFFSETCQRRECTION
CAPACITORS
REfERENCE
INPUTIVRJ
BUFFU
OPAMP
UP AMP
,U>
INPUT
DOT
'oe2
COCI
COCl
Dual-In-~ine
POWER
Package
1
IS ANALOG
,NO
SUPVlYGIllO
v'
11 ANALOG
2
INPUT
COMPARATOR J
'"'
NEG RAM"
UNKNOWN
POLOEY/POS
16VREFIN
.•
15 BUFFER
ou>
14 QPAMP
IN
13 (]PAMP
OU>
RAMPUNKIIIOWN •
OFFSET 1
CORRECT
12
'01:2
RAMP 8
lleOCI
REFERENCE
1D
DIGITAL 9
,,0
COC3
TOPVIEW
PQWERSUPPLY
GNOIPSG)
v'
OPEN COllECTOR
COMPARATDRDUT
[I:OMPI
~
w
NEGATIVE RAMP POLARITY
UNKNDWNIRU-l OET/POS
IIAMPUNKNOWIII
(PO/RU+j
OfFSET
CORRECT
RAMP
REFERENCE
(01:)
(RR)
2·57
BIGITAL
GIIID[DGj
Order Number LF133000
See NS Package 018A
8
C"')
C"')
,.-
LL
..J
Absolute Maximum Ratings
±18V
570mW
110°C
--65°C to +150°C
O°C to +70°C
300°C
Supply Voltage
Power Dissipation, (Note 1)
Junction Temperature
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 seconds)
Electrical Characteristics
(VS = ±15V, T A = 25°C, unless otherwise noted)
PARAMETER
Analog Input Current, liN
CONDITIONS
LF13300
TEST
CIRCUIT
MIN
1,2
Vx = 0
TYP
80
TMINSTASTMAX
Vx = ±IIV
Analog Input Voltage Range
Analog Input Resistance
Reference Input Currents, I R
:
1,2
0.1
VR'" 10V
TMINSTASTMAX
VR = llV
3
VR = 10V
3
Reference Input Voltage ~ange
Reference Input Resistance
3
0
-12
Offset Correction
5
20
Input Current, IOC
5
TMINSTASTMAX
nA
nA
±11
V
Mn
100
nA
10
10
'ILA
ILA
11
4
. pA
10
1000
Offset Correction Voltage, -VB
Op Amp Slew Rate
500
UNITS
5
10,000
1,2
VX=O
MAX
V
Mn
V
2000
20
pA
nA
6
10
Op Amp Bandwidth
7
3
MHz
Buffer Slew Rate
9
25
V/ILS
11
2.5
11
0.25
Comparator Response Time
Comllarator Output S~turation
Voltage·
Logic ".1" Input Voltage
200ILV InllutStoP, 100ILV
Overdrive
VCC =
!lv,
RL = 2k,
V/lLs
ILS
0.4
V
2.0
5.0
V
-2.0
0.8
V
50
ILA
±18
V
TMINSTASTMAX
All Switching Input Pins 5, 6,
7,8, TMIN S TA S TMAX·
Logic "0" Input Voltage
All Switching Input Pins 5, 6,
7,8, TMIN STA STMAX
Logic I nput Current
. All Switching I nput Pins 5, 6,
15
7,8,OSVLS5V, TMINS
. TASTMAX
Power Supply Voltage Range ±VS
VR S V+ - 3V, VIN = OV
Power Supply Current
±4.75
3.0
mA
-5.5
mA
±11
TMIN STA STMAX
mA
Note 1: For operating at elevated temperatures, the LF13300 in the dual·in·line package must be derated based on the thermal resistance of
100'CIW junction to ambient.
2·58
r-
::2
Typical Performance Characteristics
Integrator Capacitance,
Integration Time Constant
C iiSfCLK for Different
IRC) YS fCLK fo, Different
Reference Voltages, VR
Integrator Resistances, R
Analog Input Bias Current, liN,
Vx = OV, vs Temperature
~
S
~
0.1
~
i=
15
i= 0.01
~
I
~
10
0.001
10
1M
100
1M
100
25
Offset Correction Bias Current,
Logic Input Current vs
IOL~
Temperature
vs Temperature
50
75
100
125
TA - AMBIENTTEMPERATURE ("CI
fClK (kHz)
Reference Input Bias Current,
I Rr vs Temperature
2B
1
...
i:i
~...
=>
24
20
16
10
12
~
"0;
:l
0.001 L..l.-'-..J....J.....J'-'---'-..J.....L....l--'-..J..-'-'
-50 -25
25
50 15 100 125
-50 -25
TA - AMBIENT TEMPERATURE ("CI
~
1.8
~>
1.6
:l
~
~
=
...
i
1.4
1.2
15
100
125
Logic Input Threshold Voltage
Comparator Saturation Voltage
vs Temperature
H-+++-H-++H-+++-I
H-++-H-++-I-+++-II-+--j
H--'I'*+-H-++H-+++-I
t=4=++:jst=l=++j=j=+:t~
H-+++-H-++H-+-f''k:-I
"
O.B
~
0.6 L-J--'---'--'-l...:..L-'-..J.....L...J'-'---'--'-'
0;
50
vs Terrwperature
:;; 430
..s
~
25
-50 -25
25
50
15
100 125
TA - AMBIENT TEMPERATURE ("CI
25
~
co
"
J90
.~
.
>
J50
i=
310
"...g;
;;!i
...g;
::"'"
~
H-++H-+++ VCC· 5V
H-++H-+++ Rl· 2k
50
75
100 125
TA - AMBIENTTEMPERATURE I"CI
TA -' AMBIENT TEMPERATURE ("CI
Power SupplV Current vs
Temperature
14
<:
12
i:i
10
..s...
H-++-H-+++-f-vs" 15V
'"~
i'"
270
230
IS
+IS
~
190
f
150
-50 -25
25
50
75
100 125
TA - AMBIENT TEMPERATURE'('CI
Functional Description
0
-50 -25
25
50
15
100 125
TA - AMBIENTTEMPERATURE rCI
The offset voltages are assigned as follows: V051 .:.. the
input offset voltage of the buffer; V052 - the input
offset voltage of A 1; V053 - the input offset voltage of
A2; V054 - the input offset voltage of the ·comparator.
The LF13300 goes through the following 5 states
during normal cycle: 1) Offset Correction; 2) Polarity
Determination; 3) Initialization; 4) Ramp Unknown;
5) Ramp Reference
.55 grounds the input of the buffer so that its output'
voltage is simply V051. 56 bypasses R to keep the
integration time constant, RC, from affecting the
circuit operation. 54 makes the total equivalent input
voltage to Al be -V051 - V052. 57 puts the op amp
in a unity gain configuration with respect to the input
of A2. 58 keeps the output voltage of the op amp at
-VB + V054 = -VB' (the Offset Correction potential)
since the comparator is placed inside the loop. C3
samples the output of the -VB generator. The voltage
at the non·inverting input of A2 is -VB - V051 -
Offset Correction Description (Figure 1)
The Offset Correction scheme will drive the input of
the comparator to its switching threshold when the
analog input is zero and. the timing components, RC,
are bypassed.
The Offset Correction input (OC) is driven high, closing
switches 54-59.
2·59
(,.)
(,.)
o
o
o
o
M
M
u:
...J
Functional Description
(Continued)
+ input of the integrator. If Vx < 0, the device is
connected as in Figure 3 with S2 and S4 closed. Vx is
now applied through the buffer to the - input of the
'integrator. In either Ramp Unknown case, the op amp
"outpu,t ramps in the positive direction and Vx i's applied
to a high impedance JFET input.
VOS2 - VOS3 + VOS4 = V1. Thus, the sum of the
offsets is stored on C1, and the differential voltage
acrbss the comparator is zero .
Polarity Determination (Figure 2)
The simplified diagram of the LF 13300 in the Polarity
Determination state is shown in Figure 2. S5 and S3 are
closed during this period. S5 grounds the buffer input
and Vx (the unknown voltage) is applied through S3 to
the non·inverting input of A1. The equation that des·
cribes the op amp output voltage is given in Figure 2.
When Vx is applied to A1 at q, the output of the op
amp slews to Vx and is integrated until t2, when S3
opens and S4 closes .. At t2, VOUT slews 'down by -VX
leaving
Ramp Reference (Figure 4)
In this stat~, the LF13300 is configured with switches
Sl and S4 closed. The reference voltage, VR, a positive
voltage, is applied to the buffer input and the op amp
output ramps down until VOUT = -VB' where the
comparator will trip. '
- 1 Jt2 VXdt - VB' at,the op amp output.
RC
t2
'
If Vx and VR are assumed to be constant over theIr
respective integration periods, the integrals of Figure 4
are reduced to,
Just before t2, the comparator senses the op amp output
with respect to -VB; the comparator output goes high
if Vx > 0 and remains low if Vx :=:; 0,
Initialization (Figure 1)
RC
Vx
In the Ramp Unknown state, if Vx ~ 0, S3 and S5 are
as shown in Figure 2, and Vx is applied to the
close~,
BUF OUT
15
R
t5 -t4
Since .14-t3 = 4096 clock periods and t5-t4 can be
measured in clock periods, VXNR = X/2 12 , where X is
a digital' binary output representing an analog input
Vx with respect to VR.
Ramp Unknown (Figures 2 and 3)
1
VR (t5 - t4)
RC
or
During initialization, the configuration is the, same way
as it is in the Offset Correction state and the op amp
outpUt is brought back to the Offset Correction poten·
tial-VB'·
r-----
Vx (t4 - t3)
OP AMP IN
COMPDUT
OPAMP OUT
-VB' = -VB + VOS4
14
13
I,
+
1
1
1
'I
I
1
I
I
I
I
I
V2 = -;VB + VOS4
I
S8
1
I
I
I
VI = -VB - VOSI - VOS2':: VOS3 + VOS4
-VB
L-r6~f
VR
lot-ti.V'tt~'r'- "
AG
'vx
Vs
. .__~~__. .____~
-VS
,
RU-
~~~ER
FIGURE 1. Offset Correction Circuit
2·60
PD/RU+
DC
RR
,
DIGITAL
GND
Functional Description
r-
(Continued)
1
RC
-VB' + Vx + -
1
-VB'+VX+ RC
8UF OUT
R
OPAMP IN
Vx dt: Ramp Unknown for Vx
t3
2': 0
Vx dt: Polarity Determination
tl
OPAMP OUT
COMP OUT
VOUT
r-----
I
jt4
jt2
+
I
I
V2
I
I
I
I
I
I
L i>;116
AG
17
18
11
12
COC2
OIGITAL
GNO
FIGURE 2. Polarity Determination Circuit or Ramp Unknown Circuit for
VOUT = -VB' + -
.
aUF OUT
R OP AMP IN
jt4
Vx dt: Ramp Unknown for Vx
t3
OP AMP OUT
COMPOUT
13
r---:---
I
1
RC
Vx ;:::. 0
----~--
+
I
I
I
I
I
I
I
I
L '?;_
AG
116
VR
11
Vx
18
12
COC2
OIGITAL
GNO
FIGURE 3. Ramp Unknown for·VX
2·61
<0
<0
".....
W
W
o
o
o
o
~
Functional Description
u:
1
(Continued)
VOUT* = -VB' + RC
OP AMP OUT
r-----
..oJ
CDMPOUT
13
vo~------
1
1
1
I
.1
1
I
1
1
L
S1~~
AS
11-12
Cocz
ANALDGGND ....-
*Moreaccurately
-~--'
rot-ri4I'~t1;-":~~~'"
.....
.
1
(ft5+a
VOUT=-VB'+RC
DS
{t4
VRdt+
t4
g~~TAL
-=
)
VXdt
+6
t3
Where 6 is the incremental. voltage overdrive needed to fully switch the comparator
and A is the sum of the additional time required to develop
lj
and the compar~tor
propagation delay.
FIGURE 4. Ramp Reference Circuit
12-Bit AID Converter Electrical Characteristics
12·bitplussign. (LF13300 with ADB1200 (MM5863)). (VR = 10.000V, FC = 250 kHz, O°C-::;T A -::; +70°C unless otherwise noted.)
PARAMETER
Resolution (Note 3)
CONDITIONS
MIN
VR = 5.000V, -10V ~ Vx ~ +10V-
13
TVP
MAX
UNITS
Bits
FC = 125 kHz,TA = 25°C
14
Bits
LS~
±1/8
±1/2
Ratiometric Gain Error (Def.)
Vx = ±10.000V, TA = 25°C, (Note 2)
±1/2
±2
Gain ErrorDrift
Vx = 10.000V
±1
ppm/"C
Zero Reading Drift
VX=OV
±0.5
ppm/"C
Non· Li nearity
±11
Analog Input Voltage Range
Analog Input Leakage Current
Vx = OV"T A = 25°C
Analog Input Resistance
Vx = O~, T A = 25°C
100
Reference Input Voltage Range
VR Varied, TA ~ 25°~
4
±12
80
Reference Input Leakage Current
VR = 10.000V, T A = 25°C
Reference Input Resistance
VR = 10.000V, TA = 25°C
100
Start Conversion Pulse Width
VSC = 2.4V
2.4
Conversion Time
VIN = 10.000V
V
500
pA
Mn
1000
12
0.1
',LSa
100
V
nA
Mn
1000
J.Is
36
ms
11
mA
27
45
mA
23
39
mA
tc = 8960/FC
15V Supply Currents
-15V Supply Currents
LF13300, V+ Current
LF13300, V- Current, ADB1200
(MM58631. VGG Current
5V Supply Currents
VIN = OV, AD81200 (MM5863),
VSS Current
Note 2: The AID converter system must have been operational for a minimum of 30 seconds before this measurement is made. This is to relax the
dielectric absorption effects of the integration capacitor, C.
Note 3: Polarity and Overrange outputs are considered as additional output bits.
2-62
r-
12-Bit AID Converter Circuit and Timing Diagrams
::2
15Vo--------,
'V
(,J
(,J
0-------------4-----------------------------,
r--------i---,
o
POWER GND
...
-15V o-------~~V' 2
16
V,
+
REFERENCE INPUT
VOLTAGE
"
ANALOG INPUT
VOLTAGE
•
PO
COMP
OUT
POLARITVISERIAl DATA OUTPUT
3
QVERRANGE
AG
RU-
V.
POIRUt
211 MSB
17
ANALOG OND
POL VPRDPYL:' {
CAPACITOR
"~I
CAPACITORS
BUFFER OUT
DC
OAtN
RR
LF13300
12-BIT BINARY
OUTPUTS
DGI-'--...."""""1
DADUT
DIGITAL
COC2
GND
2
COCt
COC3
~ ::LK
ZULSB
CLK
L....",.,,,.......,~=-'T;J
START
CONVERSION
SERIAL
Fe
CDRR~~~~~~-
I-
DETER~~~:;:~~
STAND BY -
...::::~
'-""-'."
ENOOf .
CONVERSION
PARALLEU
CLK
INITIALIZATION-
o
f,__:':V-...._:_---~~
SERIAL
SELECT
~
~~~~~~~ATlON
-
I ~-
I--INITIALlZATION
STAND BY -
~ ___-~~-'.~
~~
I--
=
DP
~~~-VB
cg~~ t
DC
PDIRU'
RU-
~ -:-I"'~
n
It.n~:
I
lW
~~
~
r.rlJ-
t III
t
I H-I
---+--tt--
~r++_------------------r_--~~~~H
RR
sc
t
~
tl~+----------___---------r-----~~L~+--------------------~---tr_
LI
EDC
L
I~~~~------------------~
4-~+-----~----------~
lSTAI'I AI"I
END D( CONVERSION
ItJI iTA,T
I I liD
_
~,~~+---------------r_---~,
*Note. All TTL signal level.
FIGURE 5.
2·63
1
END Of CONTVERSION
\
I,
!l.
r--
Application Hints
Increasing the Input Impedance of t~e LF.13300"
MM5863 12-Bit AID Converter
The input impedance 'of the LF13300. ADB120Q
(MM5863) AID converter can be increased.l to 2 orders
of magnitude over the fypical '1000 Mn cited in the
12-bit AID specifications by insuring that the signals
that switch the LF13300 do not overlap. A circuit that
eliminates switching overlap by introducing a Delay
(td) "" 3.3k x 100 pF "': 300 ns to the rising edge of the
signals from the ADB 1200 (MM5863) is shown in
Figure 6. Figure 7 shows the operation of this circuit.
The total delay time tr~ of the output will be equal to
the inherent gate rise, ~ime, t r• plus the. RC delay. td.
The fall time, tf will'·be the basic gate delay_
Eliminating Errors Due to P!lwer Supply Noise
For many applications, power supply noise (f ~ 10Hz)
causes errors which reduces the accwacy of the system.
In most applications, noise can be adequately eliminated
by putting a series resistodl00n} in the power supply
line with a 10 /IF tantalum capacitor connected at the
power supply pihS (Figure 9). The 10 /IF capacitor is,
! in addition to the normal 0.1 /IF ceramic disc capacitors,
used as supply bypass capacitors:
•
Errors caused by noise on the negative supply, -VS,
can be further re'duced by replacing, COC3 with a
10/lF low leakage tantaium capacitor. Since -VB is
3V above -VS, any noise appearing at -VS appears at
-V8; the 10 /IF capac,itor eliminates this noise.
Nulling the Residual Offset
Continuous Convers,ion Mode
The residual offset is < 200 /lV which is negligible for
most applications_ This 'can be reduced to < 40 /lV by
lowering the clock frequency from 250 kHz to about
75 kHz. If a lower residual offset is required, we'may
shown in Figure 8.,' This
trim out the remainder
circuit applies a negative.si:ep to the offset correci:ion
capacitor, COC2, by means of a variallie capacitor which
is adjusted until charge injection imbalance of the offset
correction switches are cancelled_
For using the MM5863 in the continuous conversion
mode, connect the end cif conversion output, EOC
(pin 23), to the output enable input, OE (pin 3), and
connect the start conversion input, SC (pin 2) to 5V.
as
Miscellaneous
Since none of the output pins employ short-circuit
protection, extreme care should be taken when breadboarding or troubleshooting with the power ON.
rMMmoBl
D-t-RR"
RR ..
VI Ii
t::;;c;.:
I
I
ftU •
D-t-ftU-'
FROM
I
I
ADB12DD
(MM58631
D-t-PDfRU
PDIRUt
V,
_-e_t/RC_~
TO LF133DO
-
VB
t:
ld --:
- -t, ~t'
I
I
D-t-OC'
DC •
".I
1/
- 'f~
FIGURE 7. Rise Time Delay Circuit,
L_..J
:FIGURE 6_ Overlap Elimination Circuit
1B
"
v,
17
,,'
-=
-v,
14
10tlf
100
"
to
vlFI3300
14
13
13
OFFSET
CORRECTION
'"
v'
+
~1O.'
"
lF1J3DD
100
cae2
."~
12
SIGNAL
"
12
"
10
10
COCI -::
1.'
LOW lEAKAGE
TANTALUM
FIGURE 9. Power Supply Noise Reduction Circuit
Cv 2 pf-20 pF VARIABLE CAPACITOR
FIGURE 8. Residual Offset Nulling Circuit
2-64
r
".....
Typical Applications
CN
CN
15Yo------------......,
o
o
5Yo-----------------------~----------------------~
PO~~~r--------------------,
...--.. .
-15Y o-----------~
_+----_+----------':':"'"...,
y+ 2
Y- 4
16 j-I~-....jp...
G;.......;........;.,
o---------.. . .
o---------.. . .
~ YR
YR -10.000Y
C~~~I-------+t COMP
17
Vx
2 VSS 24
PIS
SC*
17
POL/SOD t-----+SERIAL OUT
22
~ Vx
RU-I+------~ RU
21
PO/RU+
20 DC
19
18
POLYPROPYLENE {
CAPACITOR
AOB1200
(MM586J)
RR
GNO
DIGITAL
GND
LOW LEAKAGE {
MYLAR
CAPACITORS
250 kHz
CLOCK
SERIAL
CLOCK
*sc at logic "1" for continuous conversion mode
COMPARATOR
OUTPUT
END OF
CONVERSION
SERIAL CLOCK
INpUT
5Y~1
OV
:~~
U
~
~
n
L-
5vt
OV
SERIAL OUT
5Vt
OV
(t ot
POL
t t ~lB t f
21B
MSB
6tB
JSB
5SB
7SB
8tB
f· IlB f JB
9SB
llSB
FIGURE 10. Continuous Conversion 12·8it Plus Sign Sarial Output- AID Using the LF13300 and the MM5863
2·65
o
o
M
M
~
LL.
....I
Typical Applications
(Continued)
15V
5V
POWER
GNO
-=
-15V
v+
2
VSS
16
VR
VR
COMP OUT
POLARITY
COMP
OVERRANGE
17
Vx
Vx
RU-
AG
PD/RU+
22
RU-
MS8
2S8
18
ANALOG
GND
-=
21
R
3.9M 15
20
DC
PO/RU+
DC
TAl-STATE")
DATA OUTPUT
14
lF1330,O
19
RR
AD812DO
IMM5863)
RR
C
D.OO5>JF
13
POL YPROPYLENE {
CAPACITOR
OP AMP
OUT
18
OG
12·8IT
BINARY
GNO
0.1 pF
28
COC2
O.l.u F
MVLARS {
CO" "'''"'
COCI
CAPACITORS
-=
DIGITAL
GND
COC3
ENDOF
CONVERION
250 kHz.
CLOCK
~ MINIMUM OF 4864 CLOCK PERIODS
INITIATE
SelECT AID
l
CO~VERSION
START CONVERSION
IS C)
OV
END OF
CONVERSION
IEOCI
DATA
~
iDATAREAD
OUT
5V~
I
OUT
----j
~5CLOCKLI
I '
'"'"~
OV
OUTPUT
n
5V---
TRI·STATE OUT
t
•
t
I
PERIODS
'
•
iDATAREAO
OUT
~
TRI·STATE OUT
OUT
* Note.
Prior to the first conversion cycle, the data outputs will all be in a "1" state when the
outputs are enabled (DE in "0" state).
FIGURE 11. 12·Bit Plus Sign AID in Command Conversion Mode
4-Channel Differential Multiplexer with Autozeroed
Instrumentation Amplifier and 12-Bit AID Convert~r .
Figure 12 shows a low speed, high accuracy, data acqui·
sition unit where the analog input signal is acquired
differentially and preconditioned through an LF352
monolithic instrumentation amplifier. To eliminate
amplifier offset errors, autozeroing circuitry is added
around the LF352 and is timed through the ADS 1200
and flip-flop C. Flip-flops A and B form a 2-bit up
counter for channel select.
during autozero the multiplexer is disabled. Wh'en the
system does poiarity detection a~d AID conversion, the LF352 is active and the multiplexer is enabled.
The zeroing cycle for the LF 13300 and the LF352
lasts' for 256 clock periods, so the' maximum clock
frequency will depend upon the required accuracy and
the minimum zeroing time of the· instrumentation
amplifier. Notice· here that the system accuracy will be
lEiss than 12 bits since it will be' affect~d by the gain
linearity of the instrumentation amplifier.
For more details concerning data acquisition, see AN-156
and LF 1150S/LFl1509 data sheet. For details on the
instrumentation amplifier, see the LF352 data sheet.
The instrumentation amplifier is zeroed at power-up and
after each conversion as shown in the timing. diagram;
2·66
Typical Applications
15V
r"T1
......
(Continued) .
W
W
o
-15V
~
DIGITAL
""'=ANALOG
GND
GND
o
10M
S2
S3
I.
S4
S; O-:.::+--C.....""rl......
S2
I
I -15V
S3
~-1-1
I
1
S4
I'
.
LF135D9
16
14
EN
AD
AI
'--+-o-15V
10
1
1
1
1
1
I
L_
I
11
L ____ _
5Vo-~------------------~
Al
2Dk
1
L __ _
13
14
21
OVERRANGE
MSD
.DI-"--.....--''''I
LF133DD
5V
DC t-:-~p-t-~
DIGITAL
OUT
RR
f!.1H-f.""":::..j
5DDPF
LSD
T
lDk
*Low leakage mylar
**Polypropylene
fCLOCK MAX = 200 kHz
FIGURE 12. 4,Channel Differential Multiplexer with Auto,eroed Instrumentation Amplifier imd 12·Bit AID Converter
DC
PDtRU+
~.
4096 CP
RR
~.
4096 CP
~
n
n
P~~~~ ...,
4096 CP
FL
r
r
AD
Al
ENABLE
--.I
AV IS1-S,1
~~3~I-lu
U
Va
AV ISZ-S21
U
Va
FIGURE 13. Timing Diagram for Figure 12
2·67
Av IS3-S31
L
\
o
o
M
M
Typical Applications
u::
10V
OUTI
liN
LH0070·2
I
-I
(Continued)
I
615V
GNO
lOOk
.01% •
-15V
0.1 pF
25
lOT
~rl:
~lP~
25k >-
NSB5415
41/2·01GIT DISPLAY
Jr
2
171611311
.01%
~
16 V
17 REF
Vx
ANA LOG
GRO UNO
Rl
lB Vx
A6
15 BUFFER
OUT
.>-
62k~
LF13300
RR
14 OPAMP
INPUT
Cl--'-
RU-
T
13 OPAMP
10 OUTPUT
OC3
H
H
:C4
12
~
COMP
OC2
:C2
OC
OCI
POWER
GNO
C5-1t
___ 1
7-25 pF
7
ru
OS8870
8
1
5
4
3
5
7
2
2k
6
11
:C3
4
15V
4
-15V
a
Jrl,5rT4 3
21 19 20 22 23 24 25 18 17 16 15 12 13
g OP 01 02 03 04 05
b c d
I
RR
EOC
RU-
SAD
RCLK
~
20k~
3
~
PO/RU+
GNO
VCC
~-rf
>lk
.A
AOB4511
b
OC
GNO
9
500P"F"r
•
COMP IN
""'II
PF
11
.A
28
33
:AA·
"",,-
CCLK
OPI OP2
26 ~27
11
10
620 pF- '-7.5k~
~
~
'T
1
~
DIGITAL
GROUND
Cl = C2 = C3 = 0.33 I'F polypropylene loil
C4 = 4.7 I'F tantalum
)
()
5V
OPI
OP2
FIGURE 14.4 1/2 Digit DPM
4%-Digit DPM Electrical Characteristics
4 1/2·digit + sign (±19,999 counts) DPM system circuitas shown in Figure 14, Vs = ±15V, VREF = 2V, TA = 25°C unless
otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
-2V~ Vx~ 2V
Non·Linearity
Vx = ±1.9999V
±1/2
±1
Ratiometric Gain Error
Vx= VREF
±1/2
±1
Gain Error Drift
Vx = VREF, O~C ~ TA ~ +70°C
·±1/2
Zero Reading Drift
Vx = 0, O°C ~ T A ~ +70°C
±1/4
20,000
Reference Input Voltage Range
Reference Varied
Vx = 0
Reference Input Leakage Current
Vx = 2V
Analog Input Resistance
Vx = 0
Conversion Time
Vx = VREF, fCLK = 95 kHz
500
100
V
V
pA
.nA
Mn
1000
2·68
Counts
ppm/DC
12
0
Counts
ppm/DC
±2
Analog Input Voltage Range
Analog Input Leakage Current
UNITS
Counts
Resolution
0.505
Sec
Typical Applications
r-
"T1
.....
W
W
(Continued)
o
4 1/2-Digit DPM (20,000 Count System, > 14 Bits)
Decimal Point Programming
The circuit in Figure 14 shows a complete 4 1/2-digit
DPM using the LF13300 and ADB4511. The ADB4511
provides the. control logic to run the LF13300. It also
provides the interface and drive to. a 4 1/2-digit multiplexed LED display.
The decimal point is programmed in the following
manner:
o
Display
Features include extremely high input impedance,
1000 Mn and auto·zeroing of all offset voltages in
the LF 13300's integrator, comparator and buffer
amplifiers.
>
1.9.9.9.9
ttt t
Decimal Points
2 3
Decimal Point
DPi:Pinl1
DP2, Pin 10
The timing waveforms for this system are. the same as
those shown in Figure 5.
(O~
Gnd,l
~
4
234
010
100
5V)
The time for each phase of integration is listed below;
PHASE
OC
PDIRU+
RURR
Calculating the Integration Components
NO. OF CLOCK
PULSES
2,000
Ri,Ci
2,010
20,000
Proper selection of the integration components, Ri,
Ci, is mandatory. Ri. m~st be small enough to minimize
a slight error due to the integrators bias current, but at
the same time Ri x Ci must be large enough to keep the
integrator within its output swing range. The (Ri XCi)
min, (fastest integration). can be calculated as follows:
'$20,000
Construction and Calibration Hints
Extreme care must be taken in the following areas:
- - - --vOIMAX)
Grounds: No digital currents should flow in the analog
ground; that is, the analog and digital grounds must be
single point connected right at the power supply ground
terminal.
} VIN
I
I
I
Reference: The reference must be accurate and stable
to within 100 !lV. It must also be' well bypassed for
noise. Notice that with a 2V reference the resolution is
100 !lV.
-Va
I
I
} VIN
I
RU+
1
1-20,000-1
COUNTS
Clock: The RCLK and CCLK pins of the ADB4510 are
very high impedance nodes, so the 'clock components
must be mounted as close as possible to these pins.
Calibration Procedure
Calibration in this system is a 2 step procedure: refer-.
ence, and full-scale adjust.
•
VO(MAX) is ~ 3 VBE + 1 VSAT below VS+ ~ (VS+-2.6Vl
•
-VB is typicallv 3V above VS-' Assume 3.5V to be maximum
•
:.min Vo swing = I (VS+-2.6V) + (VS- + 3.5V)]
•
VO(RU+) SWING = VIN + RC
1
st
1
0 VINdt t = fCLK • 20,000
VIN =.2V max
Step 1: Adjust the reference voltage for exactly 2.0000V.
This voltage adjustment must be accurate to within
±50!lV.
•
Equating min Vo (SWING) and VO(RU+) SWING RiCi min
can be solved for:
1826
(Ri x Ci1 min = - - ; Vs = ±15V
fCLK
.
Step 2: With Vx (input voltage) equal to near full-scale,
"" ±1.9990V, adjust C5 to obtain correct reading.
2-69
8
CW)
CW)
Typical Applications
(Continued)
lL
~
FiGURE 15. PC Board for 4 1/2·0igit OPM (Foil Side)
NSB5415
FIGURE 16. Stuffing Diagram for 4 1/2·0igit OPM (Component Side)
2·70
r-
Typical Applications
"
(Continued)
"""'"
W
CN
o
.-------_~---+ 15V
11
14
lM325N
"'-----------4---.
-15V
o-_________~------------------~~~~~TAl
~~---~~---------.5V
FIGURE 17. Power Supply for 4 1/2·Digit DPM
'"~.
z"'
~
il;
"'0
I
"''''
~
....
'"
~~
0",
Tl
IOOpF
~-."tI+11r--;..-'---
. . . -..
-·-·. jrFI~ ·- .:,. .
>.[]
LM341P·5.0
e r .......
+'IN40:~' ' .
J,
=
----~I
jumper
FIGURE 18. PC Board for 4 1/2·Digit Power Supply Stuffing Diagram (Component Side Shown)
2·71
o
0
0
('I)
('I)
u::
...I
Typical Applications
(Continued)
6,1
IN10D4
,3
32VCT
210mA
ISY
T1 (NOTE 4)
lNl0Q4
ISYo-+-.----.
T
'OJIF
26
ISY
7.5.
LM329
22
"
21
"
'-::-
20
lf1330D
ADBI2ao
IMM5a&JI
"
,,01<
25
23
ANALOG
'NPUT
Z7
'00
17
SV
.:£.
Vj( ";"
POLARITY
.V
-::SY
.v
SY
.
Il
""
12
"
b
17
•
NSBlISI DISPLAY
MSD
SSD
TSD
LSD
1-11-11-11-1
1=1.1=1.1=1.1=1.
I
I
'DO
DP
1/80SI871
DIGITS
1/805"71
*Low leakage mylar
**Polypropylene
Z D.P. POSITIONING fOR
r
IDOmV
":'"
IS
Note 1: All diodes, 1 N914.
Note 2: All resistors 1/4W, 5% tolerance.
Note 3: Circuit drawn for 8V full scale operation input scaling not shown.
Note 4: Inductive components U4X003 or Microtran PC6714.
'
FIGURE 19.3314 Plus (±8191 Countsl and 3 1I2·0igit OPM Schematic Diagram
2·72
RANGES
BODY
BV
auv
Typical Applications
(Continued)
3 3/4 Plus Digit (±8191 Counts)/3 1/2-Digit (±1999
Counts) DPM
The DPM is able to operate from a single 15V power
supply with the aid of a dc-dc converter. The LM555
generates the negative voltages required in the circuit
and also doubles as the clock. The combination of
Ql, R2, R3 and R4 forms 'a level shift to convert the
output swing of ' the LM555 to a OV-5V swing that is
compatible with the logic. The LM340-5 drops the
incoming 15V to 5,V for use by the logic circuits and
the LED display.
In this circuit of Figure 19, the LF13300 and ADB1200
interact as previously described. The CMOS counter
(MM74C926, MM74C928) is connected to count clock
pulses during. the ramp reference cycle. The counts are
latched into the, display when. the .comparator output
trips, (goes low), as shown in the timing diagram'
Figure 20.
This circuit can be a 3 3/4 plus digit DPM if the
MM74C926 is used or a 3 1/2-digit DPM if the
MM74C928 is used. These 'counters are pin compatible
and physically interchangeable.
The RC network· consisting of R,1 imd C1 is a low pass
filter that prohibits the fast transients that occur on the
comparator output during Offset Correction from
loading any erroneous counts into the counter.
R,AMP UNKNOW~ FOR VIN
>0
-
RAMP UNKNOWN FOR VIN'< 0
OP AMP OUTPUT
PIN 13 ILFIJJOO)
COMP OUTPUT
PIN 3 ILFIJ300)
-:"n':'j
>X
kUA
:-:
.----,
RR
PIN 8
ILF13300)
lifE) EOC
PINS 3. 23 IMM5863)
RESET
PINI3
IMM14C9Z6)
I'
n
"
"
n
"
n
1
y
~
V
CLOCK
PIN IZ
IMM14C9Z6)
UlJlIlJIf
UUUUlJU
MM5B63 CLOCK
LATCH ENABLE - - - - - - - - - - "
'OISPLAYS NO. OF CLOCK PULSES
PIN 5IMI~14C926)
L..--..I COUNTED WHEN CLOCK WAS
ENABLED
LJ'
FIGURE 20. Timing Diagram for 3 3/4-Digil DVM
3%-Oigit OPM Electrical Characteristics
33/4 plus digits plus sign (±8191 counts) DPM system characteristics.
(Circuit as in Figure 18. Vs = ±15V, VR = 4.096V, T A = 25°C"unless otherwise noted).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Counts
16,382
Resolution
-8.2V:::: Vx :::: +8.2V
Nonl inearity
VIN
±1/2
Counts
VIN
= 4.000V
= 4_000V
±l/S
Ratiometric Gain Error
±1/2
±2
Counts
Gain Error Drift
VIN
= 4.000V, O°C:::: T A:::: +70°C
±1
ppmfC
= OV
±1 -
ppmtC
Zero Reading Drift
VIN
Analog Input Voltage Range
Reference Input Volta'ge Range
Reference Varied
Analog Input Leakage Current
VIN
0
= OV
Reference Input Leakage Current
Analog Input Resistance
VIN
Conversion Time'
VIN
= OV
= 4.000V, fC =
±11
V,
+12
V
80
500
pA
0.1
100
nA
Mn
1000
125 kHz
2-73
74
ms
oo
C")
C")
u::
Typical Applications
(Continued)
Component Side Foil
...I
FIGURE 21. PC Bo~rd for 3314 Plus (±8191 Counts) and 31/2·Digit DPM
FIGURE 12. Stuffing Diagram for 3 3/4 Plus (±8191 Counts) and 3 1/2·Digit DPM
2·74
r:]
AC Test Circuits
Test Circuit 1
Analog Input Characteristics Test with RU - High
18
CA)
CA)
Test Circuit 2
Analog Input Characteristics Test with PD/RU+ High
"N
e
e
"N
S2
"N
Vs
Vx
"N
Vs
NC
Vx
NC
-VS
NC
NC
-VS
5V
5V
11
11
lF13300
lF13300
10
10
-12V.
-12V
-=
-=
Test Circuit 4
Test Circuit 3
Reference Input Characteristic Test with RR High
SI
-VB Voltage Measurement Test
18
Vs
Vs
16
~VR
NC
15
-Vs
LF13300
I'
NC
NC
LF13300
-Vs
15
NC
NC
NC
IIC
NC
13
12
NC
5V
11
11
5V
10
10
-12V
-=
-VB
-=
Test Circuit 6
Op Amp Slew Rate Test
Test Circuit 5
Offset Correction Input Current, IOC Test
18
18
-=
17
Vs
lF13300
15
11
Vs
16
NC
-VS
NC
NC
-=
5V::rL
-5V
INPUT
NC
NC
-VS
NC,
-=
I'
lOOk
5V
VOUT
~
10
IOCl
IDe
10
-12V
-=
-=
2·75
20pF
-12V
AC Test Circuits
(Continued)
Test Circuit 7
Frequency Response Test
'.
lOOk
5Vo--iI-'"I
L......-O.lioUT.
LF13300
20pF
*"
1-1;,;;0"'_-0 -12V
.
Test Circuit 8
Open loop Gain Test
18
S4
10
vso--f-"""I
1M
INPUT
NC'-......J<\N.........
· 0 VIN
NCo--ir--''i
15
NC
L
1PF
14
5Vo-"'-;I-'"I
*
AVOL"
VC,UTX 105
13
1M
12
VIN
VOUT
LF13300
lOOk
11
-=
10
-12V
Test Circuit 9
Buffer Slew Rate Test
VsD--iI-'"I
10V-n
-10V-J L-
NCD--il-'"I
-VsD--iI-'"I
13
LF13300
NC
":'"
12
11
5vD--I-'"I
..1;.,;;0...._ - 0 -12V
2-76
AC Test Circuits
(Continued)
Test Circuit 10
Buffer Voltage Gain Test
Test Circuit 11
Comparator Response Time Test
LFIJJOO
Vso---i""";,
COMPA RA ~~~ Qo-....-II-""ti'
2k
5Vo-_.....+~
j..:..:--~.....-o-12V
10
=-J.=E
-12+IOO"V
-12V
--12-100"V
lk
VIN
r=
100mV,_
-100mV=a::J-
2-77
~National
Analog-to-Digital Converters
~ Semiconductor
LM131A/LM131, LM231A/LM231, LM331A/LM331
Precision Voltage-to-Frequency: Converte~s
General Description
)
The LM131/LM231/LM331 family -of voltage-tofrequency converters are ideally suited for use in'simple
low-cost circuits for· analog-to-digital conversion,
precision frequency-to-voltage conversion, long-term.
. integration, linear frequency ;modulation or demodu,
lation, and many other'functions_ The output when used
as a voltage-to-frequency converter is a pulse .train at a
frequency precisely proportional to the applied input
voltage. Thus, it provides all the inherent advantages of
the voltage-to-frequency conversion techniques, and is
easy to apply in all standard voltage-to-frequency
converter applications. Further, the LM131A/LM231A/
LM331A attains a new high level of accuracy versus
temperature which could only be attained with
expensive voltage-to-frequency modules. Additionally
the LM 131 is ideally suited for use in digital systems at
low power 'supply voltages and can provige low-cost
analog-to-digital conversion in microprocessor-controlled
systems. And, the frequency from a battery powered
voltage-to-frequency converter can be easily channeled
through a simple photoisolator to provide isolation
against high common mode levels.
the quick response necessary for 100 kHz voltage-tofrequency conversion_ And the output is capable of
driving 3 TTL loads, or. a high voltage output up to
40V, yet'is short-circuit'-proof against Vee .
Features
•
Guarant~ed
•
Improved performance in existing voltage-to-frequency
conversion applications
linearity 0.01% max
• Split or single supply operation
• Operates on single 5 V supply
• Pulse output compatible with all logic forms
• Excellent temperature stability, ±50 ppmfe max
• ··Low power dissipation, 15 mW typical at 5 V
• Wide dynamic range, 100dS min at 10kHz full scale
frequency
The LM131/LM231/LM331 utilizes a new temperaturecompensated band-gap reference circuit, to provide
excellent accuracy over the full operating temperature
range, at power supplies as low as 4.0V. The precision
timer circuit has low bias currents without degrading
• Wide range of full scale frequency, 1 Hz to 100 kHz
•
Low cost·'
Typical Applications
: '.
C,
0,01 JJF*
,E----.
J
1----1....-----i
LM131
LM231
-=1-
10k'10%
1
r-"'I-V'v-.
:LM331 ..
3
;
VLOGIC
fOUT
10 kHz
FULL·SCALE
12k !1%*
47.1"10%
RL
lOOk :±-1%*
j
/.
~k'
GAIN
ADJUST
VIN RS
1
fOUT"--'-'2,09V RL R,C,
*Use stable components with low temperature coefficients. See applications notes.
FIGURE 1. Simple Stand-Alone Voltage-to-Frequency Converter
with ±0.03% Typical Linearity (f = 10 Hz to 11 kHzl
2-78
Absolute Maximum Ratings
LM131A/LM131
LM231A/LM231
LM331A/LM331
Supply. Voltage
40V
40V
40V
Output Short Circuit to Ground
Continuous
Continuous
Continuous
Output Short Circuit to VCC
Continuous
Continuous
Continuous
Input Voltage
-O.2V to +VS
-O.2V to +VS
-O.2V to +VS
Operating Ambient Temperature Range
-55°C to +125°C
_25°C to +85°C
O°C to +70°C
Power Dissipation (PD at 25°C)
and Thermal Resistance (6jA)
(H Package) PD
OjA
(N Package) PD
OjA
670mW
150°CIW
570mW
150°C/W
570mW
150°CIW
500mW
155°CIW
TMIN
TMAX
TMIN
TMAX
TMIN
500mW
155°C/W
,
TMAX
,
Electrical Characteristics
T A = 25°C unless otherwise specified.
PARAMETER
VFC Non·Linearity (Note 21
CONOITIONS
(Note 1)
TYP
MAX
4.5V <:; Vs <:; 20V
MIN
±0.003
±0.01
TMIN <:;TA <:;TMAX
±0.006
±0.02
VS= 15V.f= 10Hzto II kHz
±0.024
±0.14
UNITS
% Full·
Scale
In Circuit of Figure 1
% Full·
Scale
% FullScale
Conversion Accuracy Scale Factor
VIN = -IOV. RS = 14 kl1
(Gainl
LM131. LMI3IA. LM231. LM231A
0.95
1.00
1.05
kHzIV
LM331. LM331A
0.90
1.00
1.10
kHzIV
Temperature Stability of Gain
TMIN <:; T A <:; TMAX. 4.5V <:; Vs <:; 20V
LMI311LM231/LM331
±30
±150
LMI31A/LM231A/LM331A
±20
±50
ppmtC
ppmtC
Change of Gain with Vs
4.5V <:; Vs <:; 10V
0.01
0.1
%!V
10V <:; Vs <:; 40V
0.006
0.06
%/V
Rated Full·Scale Frequency
VIN =
Overrange (Beyond Full·Scalel
VIN = -IIV
~IOV
10.0
kHz
10
%.
Frequency
INPUT COMPARATOR
Offset Voltage
LMI31/LM231/LM331
TMIN:::;TA<:;TMAX
LM131A/LM231A/LM331A
TMIN<:;TA<:;TMAX
±3
±IO
mV
±4
±14
mV
±3
±IO
mV
Bias Current
-80
-300
nA
Offset Current
±B
±100
nA
VCC-2.O
V
Common-Mode Range
-0.2
'TMIN'
+0.01 1-tI#IIIII-+H.tHi~tttl~-ttiltHffltIIII
~
...>
0.015
::i
"'
IIS,P~CI ~I~I,~" ,
"::::iz 0.010
::i
~ -O.Dl
.....- V
!il
0.005
"-0.02 H-11tt1111-ffl1ltlll-tttllIIIII-tttlffiH-ttlltHtttIIII
r--
-0.04 I---t---t--+l--if---+--l
10
-0.03 UJ_J.UJJLl.Wllll....LWIIUJJIIIW1.J.UJ1IIII
10
100
0.0001 0.001 0.01 0.1
12
FREDUENCY, kHz
5
FREUUE'NCY. kHz
Frequency vs Temperature.
LM131A
10.06
0.000
VREF
V5
Temperature,
~ 10.02 1-+-+'.:01',-"",,,,,
~
9.98 1---l--I...oClJ';
>
,.....
1.922
~ 1.920
g
1.918
"~
-
~
......
...~
t- "..
'"
~
1.914
9.96
+25
+15
3D
+2.0
1.916
-55 -25
25
35
40
VSUPPLV
1.928
1.926
1.924
t-t:t:::F:ilrtIIIH
20
1.930
10.04
~
~ 10.00
15
Output Frequency vs
LM131A
.-..,......,...--r-.-...............,.....,--,
10
PDWER,SUPPL V VDLTAGE. Vs
1.912
1.910
-15
+125
+25
-25
+75
.(,,,~;~
+1.0
+0.5
I~ I,UJiiIII
:AI ~
-0.5
"
-1.0
100kHz Nonlinearity Error,
LM131 Family (Figure 4)
"""t JOY
TYPICAL
;"'11'1, !iInl,
1"1IInI
-1.5
-2.0
m..
'1IIIiI!:It
5
+125+150
10 15 20 25 30 35 40
VSUPPLV. V
TEMPERATURE. "C
TEMPERATURE. "C
",,1iiII""
~
+1.5
Input Current (Pins 6, 7) vs
Nonlinearity Error, LM131
(Figure 1)
Temperature
200
+0.04 1---1--+-+-+-+---1
~ +0.03 1 - - + - + - + - + - - + - : - 1
g +0.02 1---1--+-+-+-+-"-+
ffi
::
"'~
+0.01 1 - - + - + - + - + - - + + - 1
~ -0.01
"
!il
-0.02
I--+~-+-+--+--+---I
+0.04
~
+0.03
~
+0.02
'"ffi
...>
+0.01
"'"
~ -0.01
~ -0.03
I---!--+---/-+-+--I
-0.04
20
40
60
80
100
........
"
V
----
...
100
~
50
~
~
120
10
-15
12
Output Saturation Voltage vs
_55
lc,
~ fd!'
3.2
.cOl
~
~ J!11! ~
>
~
~
>
'+125"C
1.6
1.2
20
25
VSUPPLV, V
30
35
40
J J
I
" /
jV
2.0
0.8
10 15
-55"C'
2.4
0.4
5
i
2.8
,---
,,-
+25
+75
+125 +150
+0.04
/+25°C
~ +0.03
g +0.02
ffi
+0.01
"'~
-0.02
...>
{>Q-__
/,
\
TO COMPUTER
OR
COUNTER
b~
TO F·TO·V
CONVERTER
USING LMI31
lOUT
OPTOISOLATOR
4NZ8 OR
SIMILAR
2-86
Typical Applications
(Continued)
Voltage-to-Frequency Converter with Isolators
+Vs
, - ..... -r---+---~
-=-
COMPARATOR
WITH
HYSTERESIS
Voltage-to-Frequency Converter with Isolators
+VS
+VLOGIC
fOUT
TELEMETRY
USING
RF LINK
Voltage-to-Frequency Converter with Isolators
+VS
+VLOGIC
lk
VFC
USING
LMJJl
L
..... _
_
TO COMPUTER
OR
~~ COUNTER
TO F·TO·V
CONVERTER
USING LMIJl
Connection- Diagrams
Metal Can Package
Dual-In-Line Package
CURRENT
OUTPUT
Vs
REFERENCE
CURRENT
COMPARATOR
INPUT
FREOUENCY
OUTPUT
THRESHOLD
GNO
RIC
GNO
TOPVIEW
TOP VIEW
Order Number LM231AN. LM231N. LM331AN.
or LM331N
See NS Package N08A
Order Number LM131AH. LM131H. LM231AH.
LM231H. LM331AH or LM331H
See NS Package H08B
2-87
LM131 A/131,
231A/231, 331A/331
y, a
l
'~
01
•
JDk
-1,
.-1,
~ kl~ ~
~" ~
,,~
.-L 05
1D,F-,-
t~
-'-Cl'
~1~
~
06
07
.~
... ~
D.
~.
CD
-,;3
III
rt
o~
J
o~
J
+
017
1
R2
.Ok
':'
-,-"F
en
n
c
iii'
...III
010
-
-
-
.~
1
r1z0
CURRENT
OUTPUT
REFERENCE 2
CURRENT
'~CAI'
~62V
l"
':'
9
FREQUENCY
~m.
OJ!-
~
O~
A'
2k
m
00
,3
"Aj
t*
019
'"cio
t
~:t
,
."
,~
042
041
R:
15
,
~
THRESHOLD
n~
GNO
~
.r
':'
'14
2k
052
•
057
~.
kt
03.
A'
Sk
~..
~'G
J
C3
20pF
n~
Rll
lk
I'
,'"
II
048
A17
34k
OSO
A18
450
L-,
~ ~\l
0*
'15
R12
Zk
059
7l
~'
O*-
Or A19'~
2k
,
::).'
~71 ~
••
20k
~6J
~ QT ~.
,Q61'
aSB
A'
A
kf7-0
'IC
$':
.....
AI1
.10
"
027
~rSc·
Q4;-t .
,
3k
O"A
4k
f--
A.
18k
':'
OUTPUT
COMPARATOR
INPUT
CD
-
A16
6k
067
Q~
~'
~
?
~o
'20
10k
'21
IOOkI.
~
AZ2
1k
,,~ CR2
~'"
','V
~National
Analog-to-Digital Converters
~ Semiconductor
TP3000 CODEC System
General Description
The TP3001 system also includes 4 pins for the insertion
and extraction of the signaling bits required for D3
channel bank operation.
Features
• TP3001 uses the standard J.!·255 code
• TP3002 uses the standard A·law code
• Each 2-chip system includes:
• Non·linear D/A converter
• Voltage reference with excellent long term stability
• Comparator
• Successive approximation logic
• Input digital buffer
• Output digital buffer
• Input sample and hold
• Output sample and hold
• Auto·zero circuit
• Control logic
• TP3001 system meets or exceeds all relevant D3
channel bank specifications
• Both systems meet or exceed all relevant CCITT
specifications
• Analog input range of ±5V
• Analog output range of ±5V
• Input and output PCM words can be clocked at
64 to 2100 kilobits per second
• Incoming PCM word may be asynchronous
• Provision for the insertion and extraction of signaling
bits in the TP3001 system
• Opendrain PCM out for TRI-STATE® capability
These IC's contain all the necessary elements required
for a complete CODEC system-both the input and output sample and hold, comparator, stable voltage refer·
ence, non-lin'ear OIA converter, successive approximation
logic, control logic and digital input and output PCM
'buffers. The user must provide an input,aliasing filter
(300 Hz ::; f ::; 3.4 kHz) such as the AF 133 or similar
filter. The AFl34, or similar filter, is available for use as
the output filter (300 Hz::; f ::; 3.4 kHz) which is needed
to reject sidebands around a kHz and provide correction
for the sinxlx frequency distortion introduced by the
output sample and hold.
Applications
• Use with digital switching systems" in telephone
central office or private branch exchange
• Replace 24 or 32·channel shared CODEC in telephone channel bank
• Use to digitize voice and similar analog signals for low
noise transmission and reception
A special auto-zero circuit insures an extremely low idle
channel noise and low crosstalk enhancement. During
the decode cycle, the non-linear OIA converter is shifted
112 LSa, thereby achieving a typical signal to total
distortion performance of at least 3 dB better than the
03 channel bank specifications.
Simplified Block Diagram
LF37DD
MM581DD OR MM5815D
r-------'r----------.
ANALOG IN
e>--JL.......i
?;;;:;.-_.......,~__~I...:..I_---!
ANALOGOUTo-~~(
~~~~__----------_+_+----~
2·89
~
o
O·
o
(TP3001 J.!-Law, TP3002 A-Law)
The TP3001 and TP3002 are Pulse Code Modulation
(PCM) systems for the digital coding and decoding of
analog signals in the voice frequency band. The TP3001
system utilizes J.!·law coding of the analog signals while
the TP3002 is an A·law system. Each system consists of
2 IC packages. The TP3001 system uses linear part
LF3700 and CMOS part MM58100. The TP3002 system
uses the same linear part and a different CMOS part
(MM58150). Each system samples a filtered (300 Hz ::;
f ::; 3.4 kHz) analog signal at an a kHz rate, converts
this sampled voltage to an a·bit companded digital code
(J.!-Iaw or A·law) and loads this code into a high speed
serial output buffer. This output buffer will operate at
any speed between 64 and 2100 kilobits per second.
Either system will also accept an incoming a·bit. PCM
word (again, at any speed between 64 and 2100 kilobits
per second) and will automatically ,interrupt the encode
cycle to decode the PCM word and update the COD EC
output sample and hold. After decoding, the systems
will automatically return to the encoding cycle. This
interrupt capability allows either CODEC system to send
and receive PCM data asynchronously. These systems
were specifically designed for low cost "per line" or per
channel COOEC applications.
-t
."
PCM OUT
PCMIN
o
o
o
Absolute Maximum Ratings
M
V+ to Gnd
V- to Gnd
Voltage at Any Pin Except Digital.
Inputs or Digital Outputs
Voltage at Any Digital Input or Output
Operating Temperature Range
Storage Temperature,
Lead Temperature (Soldering, 10 seconds)
...
Il.
15V
-15V
,.. r
V+ to V-0_3 to +5_5V
O~C to +70°C
-65°C to +150°C
300°C
Electrical Characteristics
V+; 12V, V-; -12V, VEE; -12V (Note 4) over operating temperature range, unless otherwise specified_
PARAMETER
TP3001 or TP3002
MIN
CONOITIONS
TYP
MAX
UNITS
Method 1:
Signal-to-Distortion
~ither
Encoding or
Decoding
A Suitable Noise Signal Applied to the
2
dB Above the CCITT
. Coder Input Between -55 dBmO and
Lir'!lits Shown 'in
~3 dBmO (Refer to CCITT Rec_ G712, .
Figure 1.
Paragraph 9, Method 11, (Figure 4)
,Met~od
2:
.- Measured with C Message Weighting
. Fijter, 1020 Hz Input Signal
o dBmO to --30 dBmO
36
dB
-40 dBmO
30
dB
... 25
dB
-45dBmO '
(Figure 5)
Method
Gain Tracking Error
TP3001 or TP3002 Either
Encodi~g
or
Decoding
i:
, Deviation From Gain at -10 dBmO
A Suitable N'oise Signal Applied
t~
Within Limits
the Coder Input Betvyeen -60dBmO and.
Shown in Figure 2
-10 dBmO (Refer to CClTT Rec. G712,
(Note that Figure
'Paragraph 11, Method 1, (Figure 4)
2 is 1/2 of the
Limits Set By.
CClTT.)
Method 2:
Deviation From Gain at 0 dBmO
1020 Hz Input Signal
3 dBmO to -37 dBmO
-0.25
+0.25
dB
-37 dBmO to -50 dBmO
-0.50
+0.50
dB
(Figure 6)
Idle Channel Noise
TP3001
Input Terminated with 600n
(Figure 7)
12
"
Single Frequency Distortion
Reference Voltage
1020 Hz Input Signal at 0 dBmO, (Figure 8)
dBmOp
-40
."(Note .11·
5.25
(Note 11
2.58
Temperature Coefficient of Reference Voltage
Decoder 0 dBmO Output Level
dBrncO
d
-72
TP3002
dBmO
-5.50 . . 5.75
V,
±1.5
mvfC
,
2.70
2.82
Vrms
Intrachannel Crosstalk'
Go-to-Return Crosstalk
'Level at Decoder OutputDue to a 0 dBmO
-62
dBmO
-70
dBmO'
Signal Being Encoded (Figure 9)
.
,
Return-to-Go Ciosstaik
Level at Encoder Output (Measured Via
, Independent Decoder)
D~e
"
to a 0 dBmO
Signal Being Decoded (Figure 10) ..
0-
2-90
Electrical Characteristics
-t
."
W
(Continued)
V+ = 12V, V- = -12V, VEE = -12V (Note 4) over operating temperature range, unle~s otherwise specified.
PARAMETER
CONDITIONS
Interchannel Crosstalk (TP3001 Only)
MIN
TVP
Level at Decoder Output When a -80 dBmO
UNITS
MAX
-83
dBmO
±0.05
dB Deviation
Signal is Applied to Encoder Input
(Figure II)
Analog Output Frequency Response
300::;
f::; 3.4 kHz
F rom Theoretical
sinxlx Response
(Figure 3)
Logical "1" Input Voltage
Logical
~:1"
(Note 51
Input Current
4.0.
V
Digital VIN = 5V
1
Digital VIN = OV
-1
Logical "0" Input Voltage
0.8
Logical."O" Input Current
Master Clock Frequency, Fe
For Proper Operation:
pA
V
pA
kHz
128
Duty Cycle = 50% ± 10%
Input and Output PCM Buffer Clocks
Fa and Fi = 8 kHz
64
2100
kHz
Fbo, Fbi Duty CyCle = 40-60%
(Fboand Fbi)
Propagation Delay Fbo to Valid PCM Out
50
150
PCM Out Pin Capacitance
250
PCM Out Fall Time
1 kn Resistor to VDD
ns
pF
4
50
150
ns
100 pF Capacitor to VSS
System Power Dissipation
Fbo, Fbi'= 1.544 MHz
250
300
mW
Shutdown Mode (LF3701 Onlyl
Pin 3 at Logic High
10
20
mW
Note 1: -The relationship between the digital coding and the relative audio signal level is fixed as follows: a sine wave of 1 kHz and a nominal
level of 0 dBmO should be present at the audio output of the decoder when the appropriate character sequence shown below is applied to the
decoder input.
TP3001 SYSTEM
MSB
2
3
o
o
o
o
0
o
o
o
o
o
o
o
o
0
0
0
o
o
o
o
TP3002 SYSTEM
II-LAW
45, 6
7
LSB
MSB
2
1
1
0
0
010
1
1
o
o
1
1
1
0
o
o
o
o
1
1
1
1
1
1
o
o
o
o
o
1
1
1
o
1
0
0
3
A-LAW
4
5
1
0
o
o
6
1
0
o
o
0
0
1
0
1
o
o
o
o
1
o
o
o
o
1
o
o
1
o
o
1
7
LSB
o
o
o
o
o
o
o
o
0
1
1
0
o
1
1
o
The resulting theoretical load capacity (TMAXI is 3.17 dBmO for the TP3001 system (/i-Iawl and 3.14 d8mO for the TP3002 system (A·lawl.
Note 2: The PCM transmit filter must be AC coupled to the
ground. CODEC input impedance will then appear as 24
kn.
cooec
and a resistor of 24
kn or lower must be tied between analog in and analog
Nota 3: PCM OUT and Si are open drain outputs and will require external pull·up resistors to +6V maximum. 1 kS'l for PCM OUT and 10 kH for
Si are recommended when Fbo = Fbi = 2.1 M H z . '
.
Nota 4: Special care must be taken to assure that the substrate to ground pn junction is never forward biased. In cases where the negative power
must be open circuited, it is recommended that a high current dio~e (1 amp Schottky) be placed between V- and ground. It is further recommended that the power supply turn·on sequence be as follows: V or ground first, followed by V . Power supply turn-off should reverse the
procedure.
.
Nota 5: For TTL or LS compatibility, external pull·up resistors are required between the digital inputs and the TTL or LS logic power supply.
2-91
0
0
0
o
o
o
M
a.
System Description
(Refer to block
dia~rams)
The incoming PCM word is read in serially (MSB first)
on the PCM IN line by the Input Clock (Fbi) and the
Input Sync (Fi). When the input word has been read in
a.nd Fi goes low, the system will immediately switch,
over to the decode mode. The current status of the'
successive approximation is .temporarily stored while
the decode word is delivered to the NON-LINEAR D/A
CONVERTER. During decode, 'the ladder is shifted the
required 1/2 LSB to minimize distortion. The CON·
TROL LOGIC will then raise the Output S/H Control
line so that the Output Sample and Hold will acquire
this new output. voltage. After 4 clock cycles the circuit
will return to the encode mode. The analog oUtput of
the system will therefore be a staircase type output with
the associated sinx/x frequency distortion,IFigure 3).
The master clock for the system is Fc and must be run at
128 kHz which divides the 1251ls (1/8 kHz) time·frame
into 16 time slots. The rising edge of the Output Sync'
(F 0) initiates the encoding cycle. The Input Sample
and Hold Control (IN S/H CNTL) will go high for 1911s
thereby causing the input sample and hold to acquire a
new input analog voltage. This acquired analog voltage is
presented to a UNITY GAIN BUFFER located on the
CMOS chip and then forwarded to the positive com·
parator input on the linear chip. The successive approximation will then begin. The SUCCESSIVE APPROXIMATION REGISTER will first load a zero code into the
NON·L1NEAR D/A CONVERTER. The output of the
DIA converter goes to a second unity gain buffer and
then to the negative input of the comparator on the
linear chip. The comparator will then decide if the
sampled analog voltage is positive or negative. If the
analog input voltage is positive, the CONTROL LOG IC
will pull the polarity control line high, which in turn '
will cause the voltage reference on the linear chip to
deliver a positive reference voltage to the NON-LINEAR
D/A CONVERTER. Conversely, if the analog input
voltage is negative, a negative reference voltage will be
applied to the NON·L1NEAR D/A. The successive
approximation will turn ON the second bit to the
NON·L1NEAR D/A CONVERTER and a decision is
made to either leave that bit ON, or turn it OFF. The
logic will then turn ON the third bit and make a decision
to leave that bit ON or turn it OFF. In this way, the
analog input voltage can be converted into the standard
8·bit 1l·law or A-law code in 8 clock cycles.
....
The system incorporates an AUTO·ZERO circuit to
ensure a low DC offset for the encoding process, and
very low idle channel noise. The encoded MSB (the sign
bit) is latched on the MSB OUT pin. This signal then is
fed to a simple external low pass RC filter (with a time
constant of about 100 ms to 1 sec) and then to the
AUTO·ZERO pin on the LF3700, The DC voltage on
,this pin will adjust the offset of the input sample and
hold to correct for any offset voltage in the encoding
path. This will also correct for up to ±20 mV DC offset
voltage present in the analog input signal. This scheme
simply forces equal numbers of positive and negative
voltages over the long term.
There are 4 pins available in the TP3001 system for the
inser'tion and extraction of signaling bits. The operation
of these pins is covered in the timing diagrams.
At the end of the encode cycle the 8·bit code is loaded
into the OUTPUT PCM BUFFER. The word is read out
serially (MSB first) on PCM OUT by the Output Clock
(Fbo) and the Output Sync (Fo).
System Block Diagrams
TP3001 System
V-
-IZV
V·
I·
f,
"~~
f"
2 fhl
f"
3 Fl.
,
PC
.r."
4 "
,'.
f.
J
f,
,
Flo
a CDMPOUT
11 peMOUT
II
f,.
~;......,
mOUTPU'1
PC.
DGNO
BUFFER
I~ Fba
.!!NC
f.
"
"~
"
V"
GAIN
VDO
BUFfERS
O/:iTER'r-+-~""":A>--D:::;",+,,"~'-+-+
6 COMPOUT
,. "
r1!--
lF17DO
'" "
INPUT
OUTPUT
PCM
"GND
BUffER
~I.' f
1M
L=================~----~~----~I~
Note. Pin 3 of the LF3700 should be connected to analog ground. Pin 3 of the LF3701 is a power down control; logic high (5V) is the power
down standby mode for the TP3000 systems.
Ordering Information
SYSTEM
ORDER LINEAR PART:
TP3001 (Il-Iaw)
LF37000 (D20A)
MM58100D (D28D)
TP3002 (A-law)
LF3700D (D20A)
MM58150D (0228)
AND CMOS PART:
Description of Pin Functions
CMOS PIN FUNCTIONS:
, MM58100 MM58150
PIN
PIN
NO..
NO.
CMOS PIN FUNCTIONS: (Continued)
Fj'
(INPUT
SYNC)
MM58100 MM58150
PIN
PIN
NO.
NO.
FUNCTION
NAME
5
When this line goes high, the data
on the PCM IN line is shifted into
the INPUT PCM BUFFER by Fbi
(INPUT CLOCK). This line must be
high for B clock pulses of Fbi.
4
6
When Fj goes low, the incoming
PCM word is loaded into the NON·
LINEAR OIA CONVERTER and
the OUTPUT SAMPLE AND HOLD
is placed in the acquire mode. Dur-
ing decode, the D/A converter is
shifted 1/2 lSB. After the decode
8
is complete, the successive approxi·
2
Fbi
(INPUT
PCM
CLOCK)
mation will resume,
The leading edges of this clock will
seriallv shift the data on the PCM
IN line into the INPUT PCM BU"·
FER when the Fi (INPUT SYNC)
Fsi
line is high.
When this line is hLgh, the falling
(MM58100
INPUT SIG·
NALING
ENABLE)
edge of Fi (INPUT SYNC) will
transfer the LSB on the incoming
PCM word to Si (INPUT SIGNAL·
ING BIT). The PCM word is then
6
10
decoded as a 7·bit code.
Si
(MM58100
INPUT SIG·
NALING
BIT)
When Fsi (INPUT SIGNALING
ENABLE) is high, the lSB of the
incoming PCM word is transferred
to this line and latched by the failing edge of Fi (INPUT SYNC). An
11
12
external pull-up resistor of 10k to
the digital
required.
positive
supply
is
2·93
9
NAME
FUNCTION
The incoming PCM word is received
on this line.
When the Fso (OUTPUT SIGNAL·
So
ING ENABLE) line is high the lSB
(MM58100
of the PCM word in the OUTPUT
OUTPUT
SIGNALING BUFFER is replaced by the logiC
BIT)
state on this tine.
When this line is high and Fa (OUT·
Fso
(MM58100
PUT SYNC) is low. the logic level
OUTPUT
on So (OUTPUT SIGNALING BIT)
SIGNALING is transferred to the LSB of the
ENABLE)
OUTPUT PCM BUFFER.
This is the principal clock of the
Fc
(MASTER
CODEC system. All CODEC func·
tions with the exc!!ption of Fi
CLOCK)
(INPUT SYNC) and Fbi (INPUT
CLOCK) are synchronized to Fe.
This clock frequency should be
128 kHz.
COMPOUT This is the output of the analog
comparator which is used in the
successive approximation conver·
sion.
The encoded MSB appears on this
MSB OUT
line for use in the AUTO ZERO
function.
PCMOUT
The result of the digital encoding is
available on this line. A lk external
resistor to the digital positive sup·
ply is required.
All digital signals should be refero GND
(DIGITAL
enced to this line.
(GND)
PCM IN
o
o
o
Description of Pin Functions
(Continued)
CMOS PIN FUNCTIONS: (Continued)
LINEAR PIN FUNCTIONS:
MM58100 MM58150
PIN
PIN
NO.
NO.
LF3700
PIN
NO.
13
14
15
10
'11
NAME
FUNCTION
The falling edges of this clock will
serially shift the PCM word in the
PCM OUTPUT BUFFER to the
PCM OUT line.
No Connection
Fa
When this line goes high, the output
(OUTPUT
PCM word can be shifted out by
SYNC)
Fbo (OUTPUT CLOCK). This line
must be high for 8 clock pulses of '
Fba- When Fa goes high, the following sequence is initiated: the IN·
PUT SAMPLE AND HOLD first ac·
quires the ANALOG IN voltage and
Fbo (OUT·
PUT PCM
CLOCK)
3
4
a successive approximation conversion is made on that voltage using
the NON·L1NEAR D/A CON·
VERTER and the COMPARATOR ..
The resulting S·bit PCM word is
then loaded into the OUTPUT
PCM BUFFER.
All analog signals should be refer-
16
12
17
13
18
14
AGND
(ANALOG
GROUND)
AGND
(ANALOG
GROUND)
VREF
15
No Connection
POL CNTL
This is the digital command for
19
20
21
16
enced to this line.
All analog signals should be refer·
enced to this line.
'
This is the +VREF or the -VREF
for the NON·L1NEAR D/A CON·
VERTER.
(POLARITY
CONTROL)
+VREF or -VREF.
,
OUT S/H
This is the digital command for the
9
10
'
11
CNTL (OUT· OUTPUT SAMPLE AND HOLD to
PUT SAMPLE acquire a new voltage.
22
23
17
18
24
19
25
20
AND HOLD
CONTROL)
+COMP IN
(NON·IN·
VERTING
COMPAR·
ATOR
INPUT)
IN S/H OUT
12
ThiS is the output of the buffer
amplifier for the input sample and
hold. This is connected to the
+COMP IN pin on the linear chip.
14
This is the input of the buffer
(OUTPUT OF amplifier for the input sample and
THE INPUT hold. This is connected to the out-
15
SAMPLE
put of the input sample and hold
AND HOLD) on the linear chip.
16
D/A OUT
27
21
This is the output voltage of the
NON·L1NEAR D/A CONVERTER.
VOO
This is the positive voltage supply
for the digital chip which is provided by the analog chip.
No Connection
VEE
This is ,the negative supply voltage
28
22
IN 5tH CNTL This is the digital command for the
26
13
17
18
for the digital chip (-12V).
(INPUT SAM· INPUT SAMPLE AND HOLD to
PLE AND
acquire a new voltage.
19
HOLD CON·
TROL)
NAME
+COMP IN
(NON·INVERT·
ING COMPAR·
ATOR INPUT)
-COMP IN
(INVERTING
COMPARATOR
INPUT)
POWER DOWN
FUNCTION
This is tied to the +COMP IN pin on the
CMO~ chip.
This is tied to the D/A OUT pm on the
CMOS chip and the OUTPUT SAMPLE
AND HOLD INPUT pin on the linear
chip,
Connect to Analog Gnd: - LF3700
(LF3701 see note System Block Diagram).
This is tied to the IN S/H CNTL pin on
the CMOS chip.
IN S/H CNTL
(INPUT SAM·
PLE AND HOLD
CONTROL)
COMPOUT
This is tied to the COMP OUT pin on the
(COMPARATOR
CMOS chip.
OUTPUT)
This is tied to the POL CNTL pin on the
POL CNTL
(POLARITY
CMOS chip.
CONTROL)
This is tied to VREF on the CMOS chip.
VREF
This is the analog input to the OUTPUT
OUT S/H
SAMPLE AND HOLD. This should be
INPUT (INPUT
. connected to the O/A OUT pin on the
TO OUTPUT
CMOS chip and the'lnvertlng comparator
SAMPLE AND
HOLD)
input pin on the linear chip.
All analog signals should be referenced to
AGND
this line.
"
.
(ANALOG
GROUND)
OUT S/H CAP
A .Iow leakage, 200 pF capacitor should
be connected from this line to ANALOG
(OUTPUT SAM·
PLE AND HOLD
GROUND.
CAPACITOR)
A 'OUT
This is the output of the OUTPUT
(ANALOG
SAMPLE AND HOLD.
OUT)
This is· tied to the OUT S/H CNTL pin
OUTS/H
on the CMOS chip.
CNTL (OUTPUT
SAMPLE AND
HOLD CONTROL)
All digital signals should be referenced to
GND
(DIGITAL
this line.
GROUND)
AUTOZ
This IS connected to the MSB OUT line
. (AUTO ZERO)
of the CMOS chip after an external low
o
AIN
(ANALOG IN)
V+
IN S/H OUT·
PUT (OUTPUT
OF INPUT
SAMPLE AND
HOLD)
IN S/H CAP
(INPUT SAM·
PLE AND fiOLD
CAPACITOR)
VDD
pass filter.
This is the appropriately filtered analog
input.
This is the positive supply voltage for the
analog chip.
This is the analog output voltage of the
INPUT SAMPLE AND HOLD. This is
tied to the IN S/H OUT pin on the CMOS
chip.
A low leakage. 200 pF capacitor should
be connected fro~m this line to analog
ground.
This is the positive supply voltage for
the CMOS chip. This IS tied to VOO on
the CMOS chip.
20
2·94
This is the negative supplV for the linear
chip.
-I
"'0
W
Typical Performance Characteristics
iii
~
40
o
~
=
TP3000S/~
30
'1l2.233.9./133.9~
27.6
20
o
o
T~~~r~A{CtL LI~
I I I I I
0.5
tCITt'UMlr
26.3
~ 0.25
IV
z
~ -0.25
1
-.....
z
;;
'/1..12 6
10
-:- TELEPHONE BANDWIOTH-,
~
~
E
-0.5
-2
SINX/X WHERE
-4
-
..,....
x o:'ni/8kHl ~
-6
o
-60
-50
-40
-30. -20 ·-10-30
-60
INPUT LEVel (dBmOI
-40
-20
00.3
FIGURE 2. Maximum Gain
Tracking Error (toGain) as
a Function of Input Level
with a White Noise Source
FIGURE 1. Typical Signall
Total Distortion Ratio as a
Function of Input Level with
a White Noise Source
3 3.4
FREOUENCY (kHz)
INPUT LEVel (dBmO)
FIGURE 3. Output sinxlx
Frequency Response
Test .Set-Up Diagrams*
AF1JJ
MARCONI
TF2807A
PCM MULTIPLEX
TESTER
MEASUREMENT
PORT
rlOlSE
SOURCE
The Marconi TF2807A's noise
600
output has a probability distribution of amplitude approxi-
mating a Gaussian
distribu-
tion which is band limited to
conform with the latest CCITT
recommendations.
Switch position A - Perfect encode; decode TP3000
Switch position B - Encode TP3000; perfect decode
FIGURE 4. Test Set-Up for Signal·to·Distortion and Gain Tracking Using a·Noise Source
HP204D
OSCILLATOR
AF1J3
HPJJ4A
DISTORTION
ANALYZER
Switch pOSition A - Perfect encode; decode TP3000
Switch position B - Encode TP3000; perfect decode
FIGURE 5. Test Set-Up for Signal-to-Distortion Using a 1020 Hz Signal
*Perfect encode or decode is /l·law ·when testing TP3001 and
A.la~ when
testing TP3002
2-95
o
o
o
('I)
o
Test Set-Up Diagrams·
(Continued)
....0.
r - TP3000 - ,
I
I
MARCONI
TF2807A
PCM MU l TIPlEX
TESTER
MEASUREMENT
PORT
1020 Hz
SOURCE
Switch position A '- Perfect encode; decode TP3000
Switch position B - Encode TP3000; perfect decode
FIGURE 6. Test Set·Up for Gain Tracking Usin'g 1020 Hz Signal
r -,- TP3000 - ,
I
600
HP3555B
TRANSMISSION
AND NOISE
MEASURI~G SET
A
Determine the 0 dBmO level on the HP3555B and then measure the idle channel
noise with the HP3555B in the C·MSG·mode. The noise in dBrncO is 90 dBmO·A.
where A is the idle channel noise measurement down from the 0 level (in dB).
FIGURE 7. Test Set·Up for Idle Channel Noise
*Perfect encode or decode is ,u·law when testing TP3001 and A~law whan testing TP3002
2·96
I
-I
Test Set-Up Diagrams*
."
W
(Continued)
o
o
o
ANALOG IN
HPZ04D
OSCILLATOR
10Z0 Hz
o dBmO
600
HPJOZA
WAVE
ANALYZER
The output at any frequency (except 1020 Hz) should be at least 40 dB down.
The two frequencies of interest are the second and third harmonics (2040 Hz
and 3060 Hz!.
Switch position A -- Perfect encode; decode TP3000
Switch position B - Encode TP3000; perfect decode
FIGURE 8. Test Set· Up for Single Frequency Distortion
r
HPZ040
OSCILLATOR
I
L
10Z0 Hz
OdBmO
rl
TRANSMIT
FILTER
RECEIVE
FILTER
illDiiiiornJODt . ,
:1
AF1JJ
1
LANALOG IN . t
I
ENCODE
I
I
I ANALOG OUT I
I
AF134
IL
DECODE
-.l PCM OUT
I
~MIN
I
_ _ _ '_.J
AF133
.,....
K
TRANSMIT
. FILTER
L
I
I
I
PERFECT
ENCODE
~
600
HP3DZA
WAVE ANALYZER
-==
TUNE FOR
10Z0 Hz
FIGURE 9. Test Set·Up for Go·to·Return Crosstalk
*Perfect encode or decode is p.-Iaw when testing TP3001 and A-law when testing TP3002
2·97
DO NOT CONNECT PCM OUT TO A
DECODER IN THIS TEST CONFIGURATION.
LEAVE PCM OUT PIN OPEN
THE PCM OUTPUT CODES FROM THE
PERFECT ENCODE MUST BE EITHER
01111111 OR 11111111 FOR THE
TPJDOl SYSTEM AND 11010101 OR
01010101 FOR THE TPJOOZ SYSTEM
o
8
Test Set-Up Diagrams·
(Continued)
('I)
Q.
IAF133
rl
600'~
TRANSMIT
FILTER
L ANALOG IN
I
.
ENCODE
IL
HPZD40
OSCILLATOR
DECODE
I
HP30ZA
WAVE ANALYZER
TRANSMIT
FILTER
I
I
I
I
I
. PERFECT
ENCODE
r-
AF134
I
TUNED TO
1020 Hz
I
RECEIVE
FI1.TER
I
I
I
I
PERFECT
DECODE
FIGURE 10. Test Set·Up for Return·ta-Go Crosstalk
HPZD40
OSCILL!\TOR
600
HP302A
WAVE ANALYZER
+MIN
_ _ _ _ ...J
AFI33
I
10ZO Hz
odBmO
I
I
I
-==
,
IPCM OUT
I
-
T~:2~ ~~ 1------------1
Switch position A - Perfect encode; decode TP3000
SWitch position B - Encode TP3000; perfect decode
FIGURE 11. Test Set~Up for Interchannel Crosstalk
*Perfect encode or decode is It·law when testing TP3001 and A·law when testing TP3002
2·98
I
-I
~
Timing Diagrams
W
o
SYSTEM TIMING
o
o
Fo. Fbo and PCM OUT Relationships
Fo (8kHz)
-.J
II-
I
I!---
~
MIN lOOns
TO DETECT HI TD LOW TRANSITION
rMIN lOOns
MULTI-CHANNEL
OPERATION
OPEN
DRAIN
PCM DUT
Fo (8kHz)
OPEN
DRAIN
--U-
U
-II-MIN100ns
-
SINGLE CHANNEL
OPERATION
(Fbo = 64 kHz)
II
Fo IN LOGIC "0" SHOULD OVERLAP
- - Fba IN LOGIC "1" FOR A MIN DF 500ns
X X X X X X X X X X X
PCM OUT
LSB
MSB
2
PRE~g~~_I.
4
6
7
LSB
MSB
.1.
CURRENTWDRD
NEXT WORD
Fi. Fbi and PCM IN Relationships
Fj(8kHz)
J.
I
IL
I·
MIN lOOns
TO OETECT LDW TO HI TRANSITION
MULTI-CHANNEL
OPERATION
Fj (8kHz)
--U
uI--
~
- - 1 r MIN 100 ns
SINGLE CHANNEL
OPERATION
(Fbi = 64 kHz)
2-99
MIN 500 ns
o
o
(W')
c.
o
Timing Diagrams
(Continued)
. SIGNALING
(TP3001 Only)
~
Fso• so. Fo Timing Relationships
Fso SHOULO OVERLAP EACH SlOE OF
THE POSITIVE EOG E OF Fo 500 ns MIN
Fso
" :
So
L
PCM OUT
OPEN
ORAIN
Fsi. Si. Fi Timing Relationships
Fsi
Fsi SHOULO OVERLAP EACH SlOE OF
THE NEGATIVE EqCE OF Fi 500 ns MIN
--l 1-:-:1
·1--1 ' 1-- 500 ns
500 ns
X
Si
L
Fj
2-100
'-I
."
Timing Generator
(".)
o
o
o
14
716
OM74LS93
"
14
716
OM74LS93
VCC
Ik
'----I-l-lt---.,.. ~1C28 kHz)
Ik
VCC
Q
OM74LS74
CLK ...
---....-..f CLK
11.024 MHz)
ii
Fa & Fj
L..-_---I
~--------~CLK
IT
Timing Generator Outputs
Q
Fa.Fj~
PCM
OUT
\
L
MSB
X
X
X
X
2-101
X
X
X
LSB
I
Section 3
Digital-to-Analog
Converters
~National
Digital-to-Analog Converters
~ Semiconductor
I\)
o
l>
C
.....
General Description
CJ1
The AD7520 and the AD7521 are, respectively, 10 and
12-bit binary multiplying digital-to-~nalog converters.
A deposited thin film R-2R resistor ladder divides
the reference current and provides the circuit with excellent temperature tracking characteristics (typically
0.0002%tC linearity error temperature coefficient). The
circuit uses CMOS current switches and drive circuitry
to achieve low power consumption (30mW max) and
low leakages (200 nA ·max). The digital inputs are compatible with DTLlTTL logic levels as well as full CMOS
logic level swings. This part, combined with an external
amplifier and voltage reference, can be used as a standard
D/A converter; however, it is also very attractive for
multiplying applications (such as digitally controlled
gain blocks) since its linearity error is essentially independent of the voltage reference.
the 10-bit resolution AD7520 and AD7530 family. The
AD7521 K, AD7521J and AD7521 L 'are direct replacements for the 12-bit resolution AD7521 and AD7531
family. For more information, see DAC1020 data sheet.
Features
"
Integrated thin film on CMOS structure
"
1O·bit or 12-bit resolution
"
Low power dissipation 10 mW@ 15V typ
" Accepts variable or fixed reference -25V -:; VREF -:;
+25V
" 4-quadrant multiplying capability
This part is available with 10-bit (0.05%); 9-bit (0.10%),
and 8-bit (0.20%) non·linearity. The AD7520L,
AD7520K, and AD7520J are direct replacements for
"
Interfaces directly with DTL, TTL and CMOS
"
Fast settling time,-600 ns typ
"
Low feedthrough error-l /2 LSB
Equivalent Circuit
r
@
100 kHz typ
::1~D-::fO:U::
I
--,
I
2nk
GND
lour2
lOUT'
6
Al
I
I
I
I
I
I
I
6
6
6
A1
6
AJ
I
I
I
A4
I
6
A5
AS
I
I
6
6
A7
AS
(MSB!
6
A'
I
I
I
I
I
I
6
I 6
6
AID
LA::'" _
(lSB!
.: __
-.J
IDk
RFEEDBACK
Switches shown in digital high state
Connection Diagrams
Ordering Information
AD7520
Dual-In-Line Package
lOUT'
15
lour2
14
GND
13
AI (MSB)
A1
AJ
A4
A5
RFHDBACK
lourl
VREF'N
lour2
v.
Al0(LSB)
RFEEDBACK
-55~C::;TA~+125°C
0.05%
010%
AD7520UD
AD7520TD
AD752QSD
0.20%
OND
15
AI (MSBI
'See NS
A1
AJ
12
A7
A4
A6
A5
A6
AD7520LD
AD7520KD
AD7520JD
Package D16C
12·Bit D/A Converter
All
IJ
O°C::;TA::;+70°C
AI2 (lSB)
14
11 AB
,
OPERATING TEMPERATURE RANGE
ACCURACY
1B
12 A9
10
10·8i1 D/A Converter
AD7521
Dual-In-Line Package
16
.....
CJ1
AD7S20 10-Bit Binary Multiplying Df A Converter
AD7S2112-Bit Binary Multiplying DfA Converter
I
l>
C
AIG
ACCURACY
OPERATING TEMPERATURE RANGE
55°C < T A < +125°C
O°C'(£TA<+70°C
A'
005%
AD7521UD
AD7521 LD
IlA8
0.10%
AD7521TD
AD7521KD
'"
0.20%
A07521$D
AD7521JD
A7
*See NS Package D18A
TOY VIEW
TDPVI[W
3-1
I\)
...&.
,...
N
,...
II)
C
c:(
o
N
,...
II)
C
,
n
o(X)
o
o
DAC0800(LMDAC08) a-Bit Digital-to-Analog Converter
-s:
r
C
l>
general description
The DAC08 is a monolithic 8·bit high·speed current·
output digital·to·analog converter (DAC) featuring
wpical settling times of 100 ns. When used as a
.. multiplying DAC, monotonic performance over a 40 to
1 reference current range is possible. The DAC08 also
features high compliance complementary current. outputs
to allow differential output voltages of 20 Vp·p with
simple resistor loads as shown in Figure 1. The reference·
to·full·scale current matching of better than ±1 LS8
eliminates the need for full scale trims in most applica·
tions while the nonlinearities of better than ±0.1% over.
temperature minimizes system error accumulations.
The DAC0800L, DAC0802L, DAC0800LC, DAC0801 LC
and DAC0802LC are a direct replacement for the
DAC08, DAC08A, DAC08C, DAC08E and DAC08H,
respectively.
features
100 ns
• Fast settling output current
±1 LSB
• Full scale error
±0.1%
• Nonlinearity over temperature
±10 ppmfC
• Full scale current drift
-10V to +18V
• High output compliance
• Complementary current outputs
II Interface directly with TTL, CMOS, PMOS and
others
.. 2 quadrant wide range multiplying capability
• Wide power supply range
±4.5V to ±18V
33 mW at±5V
• Low power consumption
The noise immune inputs of 'the DAC08 will accept
TTL levels with the logic threshold pin, VLC, pin 1
grounded. Simple adjustments of the VLC potential
allow direct interface to all logic families .. The perfor·
mance and characteristics of the device are essentially
unchanged over the full ±4.5V to ±18V power supply
range; power dissipation is only 33 mW with' ±5V'
supplies and is independent of the logic input states.
•
Low cost
connection diagram
typical· appliC?ations
Dual·ln·Line Package
10V
I
DIGITAL INPUTS
'MSB
¥Y¥yYY¥Y
Sk
10V o-JVV'v-l145
6
7
a
CO~~:~~~e~~..1.. U
~
lSB '
IOUT
IOk
10k
9 10 11 lZ 4 ) - OAcoa
1
.
VOUTTOZOVp·p
Sk
r-'V'IN--I15
~
~3~~~16~~13~__~I~ZY:,"",,~~.~~~-O
~ILL'~
-
- .
T~c
V- 0.01 pF
tJ"[:
r-
v+
OUT
-
~COMPENSATION
.2.
~VREFI-l
V~...!.
fl!.VnEFI+)
lOUT
lOUT..!
~v+
Msa al...!.
~aa
az"!
~B7
a3.2.
~a6
a4..!
r!-as
FIGURE 1. ±20 Vp'P Output Digital·to·Analog Converter
LSB
TOP VIEW
ordering information
NON LINEARITY
±O.l% FS
TEMPERATURE
. RANGE
55'C:S;TA:S;+125'C
D PACKAGE (D16C)
D!\COB02LD
LMDACOBAD
ORDER NUMBERS'
J PACKAGE (J16A)
DACOBOOLAJ LMDACOSJ
DACOB02LCJ
LMDACOBHJ
DACOBOOLD
DACOBOOU
LMDACOSJ
±O.l% FS
C),C:S;TA:S;+ 70'C
±O.19% FS
-55'C:S;TA:S;+ 125'C
±0.19% FS
Q'C:S;TA;';+70'C
DACOBOOLCJ
±O.39% FS ..
O'C < TA
DACOBOl LCJ
LMDACOBD
< +70'C
*Note. Devices may be ordered by ~sing either order nUlT!ber.
3·3
N PACKAGE (N16A)
DACOB02LCN
LMDACOBHN
LMDACOBEJ
DACOBOOLCN
LMDACOBEN
LMDACOBCJ
DACOB011.CN
LMDACOBCN
n
o
(X)
-
co
o
()
<
c
:!
-8
..J
absolute maximum ratings
operating conditions
Supply Voltage
±18V or 36V
Power Djssipation (Note 1)
500mW
V-to V+
Aeference Input Differential Voltage (V14 to V15)
V-to V+
Aeference Input Common·Mode Aange (V14, V15)
Reference Input Current
5mA
Logic Inputs
V- to V- plus 36V
Analog Current Outputs
Figure 24_
Storage Temperature
-£5°C to +150"C
Lead Temperature (Soldering, 10 seconds)
300°C
Temperature (T A)
DAC0802LA, LMDAC08A
DAC0800L, LMDACOB .
DAC0800LC, LMDAC08E,
DACOB01 LC, LMDACoaC,
DAC0802LC, LMDAC08H
MIN
MAX
UNITS
-55
-55
+125
+125
+70
+70
+70.
°c.
°c
0
0
0
°c
°c
°c
co
8<
c
electrical characteristics
(Vs = ±15V, IREF = 2 rnA, TMIN:::; TA:::; TMAX unless otherwise specified.
Output characteristics refer to both lOUT and lOUT.)
PARAMETER
CONDITIONS
Resolution
MIN
8
Monotonicity
8
OAC0802LI
DAC0802LC
TVP
MAX
8
8
8
DAC0800LI
DAC0800LC
TVP
MAX
8
8
8
8
±0.1
Nonlinearity
ts
8
MIN
8
Settling Time
To ±1/2 LSB, All Bits Switched
100
8
DAC0801LC
MIN
8
TVP
8
8
8
±0.19
13S
100
UNITS
MAX
8
8
Bits
Bits
to.39
%FS
160
ns
"ON" or "OFF", TA' 25"C
DAC0800L
DAC0800LC
tPLH, tPHL
Propagation Delay
Each Bit
100
100
135
160
35
35
60
60
tl0
t50
ns
ns
TA' 25"C
All Bits Switched
TCIFS
FuJI Scale TempeD
VOC
Output Voltage Compliance
Full Scale Current Change
< 1/2 LSB, ROUT> 20 MU Typ
IFS4
Full Scale Current
VREF ·10.000V, R14· 5.000 kU
R15· 5.000 kn, TA' 2S"C
IFSS
Full Scale Symmetry
IFS4 -IFS2
IZS
Zero Scale Current
IFSR
Output Current Range
V-· -5V
V-· -7V to -18V
35
35
60
60
±10
t60
-10
1.984
0
0
18
1.992
2.000
to.5
±4.0
0.1
1.0
2.0\
2.0
2.1
4.2
-10
1.94
tl
0
0
2.04
1.94
2.0
2.0
2.0
2.1
4.2
ns
n.
±10
±80
ppmtC
18
V
1.99
t2
t8.0
0.2
60
60
-10
18
1.99
35
35
0
0
2.04
±16
mA
~A
0.2
4.0
IlA
2.0
2.0
. 2.1
4.2
mA
mA
0.8
V
V
-10
10
IlA
IlA
V
Logic Input Levels
VIL
VIH
Logic "0"
VLC" OV
Logic "1"
Logic Input Current
IlL
IIH
O.B
2.0
Logic "0"
Logic "1"
VLC' OV
-10V:S; VIN:S; +0.8V
2V:S; VIN:S; +18V
VIS
Logic Input Swing
V'"
VTHR
Logic Threshold Range
VS·tlSV
-15V
115
Reference Bias Current
0.8
2.0
-2.0
-10
0.002
10
2.0
-2.0
6.002
-10
10
-2.0
0.002
-10
lB
-10
lB
-10
18
-10'
13.5
-10
13.5
-10
13.5
-1.0
dl/dt.
Reference Input Slew Rate
(Figure 24)
8.0
PSSIFS+
PSSIFS-
Power Supply Sensitivity
4.5V:S; V+:s; 18V
-4.5V:S; V-:s; lBV
IREF"lmA
0.0001
0.0001
Power Supply Current
VS' ±5V, IREF' 1 rnA
1+
1-
-3.0
-1.0
-3.0
8.0
0.01
0.01
0.0001
0.0001
-1.0
-3.0
8.0
0.01
0.01
0.0001
0.0001
V
JJA
mAIl"
0.01
0.01
%/%
%/%
2.3
-4.3
3.8
-5.8
2.3
-4.3
3.8
-5.8
2.3
-4.3
3.8
-5.8
mA
mA
2.4
-a.4
3.8
-7.8
2.4
-a.4
3.8
-7.8
2.4
-a.4
3.8
-7.8
mA
rnA
2.5.
-a.S
3.8
-7.8
2.5
-a.5
3.B
-7.8
2.5
-a.5
3.8
-7.8
rnA
mA
33
108
135
48
136
174
33
108
135
48
136
174
33
108
135
48
136
174
mW
mW
mW
VS' SV. -15V, IREF =2 mA
I-+1-
VS· ±15V, IREF' 2 mA
1+
\
1-
PD
Power Dissipation
±5V, IREF" 1 rnA
5V, -lSV, IREF' 2 rnA
±15V, IREF =2 mA
Note 1: The maximum junction temperature of the DAC0800, DAC0801 and DAC0802 is 100°C. For operetingat elevated temperature., devices
in the dual·in·line J or 0 package must be derated based on a thermal resistance of 100°C/W, junction to ambient, 175°C/W for the molded dUBI·
in·line N package.
3·4
C
l>
block diagram
()
v'
MSB
VLC
B1
0
OJ
0
0
--.
LSB
B2
"
B4
B5
B1
"
"
r
s:
C
l>
()
0
OJ
DACOB
16
COMP
v-
equivalent circuit
v'
13
MSIl
LSB
B2
B1
5
6
"
,
B4
B5
"
10
B7
11
"
12
,-'OUT
COMP o!"I---l-+--f
FIGURE 2
3-5
-oco
typical performance characteristics
(J
Full Scale Curr~nt
..
.
::..'"
IL
o
400
.e
..
C
R14= R15 = lk
RL ';500
ALL BITS "ON"
VR15 - OV
I-
=
~
.=
1 LSB-78nA
200
~
;::
150
~
100
0:
50
o '--I-l-U.1.IJW-..L..I.J.,
1/
12
10
8
:!!
300
z
250
;::
./
(J
]
~
"'-;r- ./
co
Refarance Input
Frequency Respo,!S8
LSB Propagation Delay vs I FS
0.01 0.2, 0.05 0.1 0.02 0.5 1
2
5 10
"'\
FIGURE 3
2
}- ~
1\
0.1
0.2
IFS - OUTPUT FULL SCALE CURRENT (rnA)
IREF - REFERENCE CURRENT (rnA)
-
-2
-4
-6
-8
-10
-12
-14
0.5
10
FREQUENCY (MH.)
Curve 1: Cc = 15 pF, VIN = 2 VP1>
centered at 1V.
Curve 2: Cc = 15 pF, VIN = 50 mVp·p
centered at 200 mV.
'
Curve3: CC=OpF,VIN=100mVp-p
at OV and applied through 50 n connected to pin 14. 2V applied to R 14.
FIGURE 4
FIGURE 5
Logic Input Current
Reference Amp
Common-Mode Range
3.6
".s
I-
.~
.=~,
3.2
2.4
B
E
VTH - VLC vs Temparature
2.6
2.4
2.2
TA = TMIN TO TMAX
AL~ 81TS "ON" I
2
I I
2.8
I-
vs Input Voltage
I
1.8
1.6
~
> 1.4
I
1.2
1
> 0.8
0.6
, 0.4
0.2
.0
~
I I
I
1.6
I
0.8
IRE~ = 012 mA_
0.4
0
-14 -10 -6
-2
2
6
10
14
18
Note. Positive common-mode range is
100
150
TA - TEMPERATURE ('C)
V; - LOGIC INPUT VOLTAGE IV)
FIGURE 7
always (V+) -1.5V.
.....
50
-50
-12-10-B-6-4-202 4 6 81012141618
VIS - REFERENCE COMMON-MOOE VOLTAGE (V)
r-..
...'"
Il
IRE~'I)mA I -
1.2
.....
"
-V--15V -V=-5V
+y = 15V
IREF=2mA
FIGURE 8
FIGURE 6
Output Current vs Output
Voltage (Output Voltage
Compliance)
2.8
":li
2.4
~
1.6
.s.
0:
.=
~
I
YS
16
I I
II
Bit Transfer Characteristics
Temperature
20 r-r-~~~~~~~-'
TA=TMINTOTMAX
~V = ~5V
1.4
":li
,.s
1.2
J .I
Bll
a:
a:
0.8
!;
0:6
15
0.4
B
IREF"'1 mA
~
I
-14 -10 -i -2
2
6
10
14
Vo - OUTPUT VOLTAGE (V)
FIGURE9
1: 0.2
18
-50
50
100
TA - TEMPERATURE ('C)
FIGURE 10
150
Bk
-Y= -15V
I
IREFI= 0.21rnA
0.4
IREF = 2 rnA
I-
IREF"2mA
1.2
'0.8
I
E
~
-V -IJV
I-
!;
ALL)BlTrON;'
Output Voltage Complianca
H-A--V=-5V
B3
B4
f.-'~
11-
-12-10-8-6-4-20 24681012141618
VL - LOGIC INPUT VOLTAGE (V)
Note.81-88 have identical transfer
characteristics. Bits are fullv switched
with less than 112 LSB error, at less than
±1DD mV from actual threshold. These
switching points are guaranteed to lie
between 0.8 and 2V over the operating
temperature range (V LC = OVl.
FIGURE 11
3·6
typical performance characteristics
c
»
(Continued)
ALL BITS MAY BE HIGH DR LOW
ALL BITS HIGH DR LOW
"
r-- _'1_ ~IT~ IR~F • krnA - -
I-
f--
2
4
6
ALL BITS HIGH DR LOW
IREF"2rnA I I
i
f--
ffi
'-r- I-~V!'5~
.!.
I I I
I I I
i
r-- I~ WI~H I~EFI. o.~ rnA
1+
~
I
£
-50
50
1-,-
1+-
100
V - NEGATIVE POWER SUPPLY (V)
TA - TEMPERATURE ("C)
FIGURE 12
FIGURE 13
FIGURE 14
(Continued)
DIGITAL INPUTS
255
x 256
'MSB
LSB
Bl BZ &3 84 85 B6 B7 88
iQ
10 +
= IFS for all
logiC states
RREF
fRI41
RI5
-YREF
For fixed reference. TTL operation,
typical values are:
VREF ~10.000V
RREF = 5.000k
R15'" RREF
CC= 0.01 /JF
VLC = OV (Ground)
O.I/-1F
~
.v
-v
FIGURE 15. Basic Positiva Raferance Operation
-
+IREF""2mA
r-------":\.,;::!:::=:..n'D
,,.
-'v
PDT
":'
,•
14
14
LOWTC
4.511
DACOS
DACOII
R15
-VREF o-oO-"iIII'v-iL
15 -_ _ _ _...:r
15
APPROX
":'
"
I
FS '"
FIGURE 16. Recommended Full Scale Adjustment Circuit
-VREF x 255
RREF
256
Note. RREF setslFS; R15 is
for bias current cancellation
FIGURE 17. Basic Negative Reference Operation
DIGITAL INPUTS
Msa
81
'Lsa'
8213 B4 US B6 B1 88
ED
IREf" ZmA
Full Scale
Full Scale-LSB
Half Scale+LSB
Half Scale
Half Scale-LSB
Zero Scale+LSB
Zero Scale
Bl
1
1
1
1
B2
1
1
B3
1
1
B4
1
1
B5
1
1
B6
1
1
B7
1
1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1.
1
1
1
1
1
a
a
a
a
a
a
a
a
a
a
O'
a
B8
1
a
1
a
1
1
a
lornA
1.992
1.984
1.008
1.000
0.992
0.008
0.000
FIGURE 18. Basic Unipolar Negative Operation
3·7
lornA
0.000
0.008
0.984
0.992
1.000
1.984
1.992
.EO
-9.960
-.g.920
-5.040
-5.000
-4.960
-().040
0.000
EO
0.000
-{).040
-4.920
-4.960
--5.000
-g.920
-g.960
»
oo
Q)
Vcc - POSITIVE POWER SUPPLY IV)
typical applications
-s::c
r
rJvLL
I I I
I I I
o -2 -4 -6 -B -10 -12-14-16-1B-20
B 10 12 14 16 18 20
Q)
o
o
10
.!!
-LlITJIR~F.I, J- -
Ii
B
Power Supply Current
vs Temperature
Powar Supply Current vs -'V
Power Supply Current vs +V
150
-co
o
typical a.pplications
(Continued)
U
(Continued)
if
VTH=VLC+I.4V
15V CMOS. "TL. HNIL
V1H = 1.6'1
12VfTD: ~
TTL,OTL
VTHt 1.4V
8
To
6.2V
ZENER
I
. ,,,
6Zk
. -=
' :"
T":"
0
0
0
(X)
'::"
i
15V
Vle
n
PMOS
V1H=OV
'ILe
D.lt1f
Vee
I
?
L..r
RR~F
~(OPTIONAL
RESISTOR
• ' ~ FOR OFFSET INPUTS
AIN
r.,::'.-------4\..,J,...J\N....,
10k
I
I
-5V10-10V
-5v~-+-;~-T--~~---:
V1H=2.8V
I
"1H"5V
I
I
VTH~-1.29V
I
I
I
I
I
lN4148
Rp
'::"
NO CAP
n
Typical values: RIN 7 5k, +VIN = IOV
3.9k
1k
-S>V
Note. Do not exceed negative logic input range of DAC.
FIGURE 23. Interlacing with Various Logic Families
FIGURE 24. Pulsed Reference Operation
R'N
DACOS
R15
0--""""--115
'-_______
DACOS
VIN~
(OPTIONAL)
~~~~ri::~!--
(a) IREF 2: peak negative swing of liN
..J
fOR TURN "ON", VL '" 2.7V
FOR TURN "OFF", VL "'0.7V
- , - O.• V
Y,N
15k
RREF
5
"
6
7
DAtOS
ID.U.T.)
-15V
TO D.U.T,
~O.I!'F
~o.t!'F
15V
RREF .... RI5
(b) +VREF must be above peak positive swing of V 1N \
FIGURE 25. Accomodating Bipolar References
"OUT
I XPROBE
-t5V
FIGURE 26. Settling Time Measurement
3-9·
C
l>
(')
0
(X)
DACOS
1.Jk
I
lN4148
---
REQ,,"ZOD
DVn
-s:
r
+VREF
'-ov
OV
£-D.• V
-o
(X)
U
-t-===~
CDMPEN
DACOBDB
SERIES
12 AS LSB
A'
11 A7
AJ
TO AS
A4
9 A5
TOPVIEW
typical application
VCC"5V
I
5.0DOk
t-:=;:>--"",,..,...--O 10 ODOV '" VREF
MSB Al
A'
AJ
DIGITAL
INPUTS
5.DDDk
A4
AS
A6
A7
VD
LSB AD
OUTPUT
VEE"-15V
FIGURE 1. ±10V Output Digital to Analog Converter
ordering information
ACCURACY
8·bit
OPERATING TEMPERATURE
RANGE
-55°C:O:TA~+125°C
, 0 PACKAGE (D16C)
DACO.808LD
LM1508D·8
ORDER NUMBERS'
J PACKAGE (J16A)
DAC0808LJ
LM1508J·8
N PACKAGE (N16A)
8·bit
O°C:O:TA~+75°C
DAC0808LCJ
LM1408J·8
DAC0808LCN
LM1408N·8
7·bit
6·bit
O°C ~ T A ~ +75°C
DAC0807LCJ
DAC0806LCJ
LM1408J·7
LM1408J·6
DAC0807LCN
LM1408N·7
DAC0806LCN
LM1408N·6
O°C~TA~+75°C
*Note. Devices may be ordered by using either order number.
3-11
00
00
0)0)
00
C»,S»
C
Relative
accuracy:
±0.19% error
maximum
(DAC0808)
Full scale cur.rent match: ±1 LSB typ
7 and 6-bit accuracy available (DACOB07, DACOB06)
Fast settling time: 150 ns typ
Noninverting digital inputs are TTL and CMOS
compatible
High speed multiplying input slew rate: B mA!j.ls
Power supply voltage range: ±4.5V to ±1BV
Low power consumption: 33 mW @±5V
The DAC0808 will interface directly with popular TTL,
DTL or CMOS logic levels, and is a direct replacement
for the MC1508!MC1408. For higher speed applications,
see DAC0800 data sheet.
MSB
AI
CC
l>l>
l>
oo
0)
o
~
I'
0
CO
0
U
~
il
Al THROUGH A8
III
~2
0.6
V ~ -15V
0.4
rl-Ir
I
E
III
i
0.8
5
~
0=
0.2
-12-10-8-6-4-2024681012141618
O)~
]
1.4
AS
A3
A4
-V- 5V
ft
18 ' - t - t- .
1.6
r- r-...
1.4
1.2
c
oo»
............
r--- ......
(X)
0.8
u
0-
0.6
§
0.4
o
.....
o
-55 -31-19 -1 11 35 53 11 89 101125
-12-10-8-6-4-20 24 6 8 1012141618
TA - TEMPERATURE rC)
VL - LOGIC INPUT VOLTAGe IV)
VL - LOGIC INPUT VOLTAGE IV)
(X) (X)
00·
Output Current vs Output
Output Voltage Compliance
vs Temperature
Voltage (Output Voltage
Compliance)
2.8
"
2.4
~
1.6
=>
1.2
ALL BITS "ON"
.§.
~
0-
VEE::; -15V
VEE
~
-5V
II
. I
I I
I I
,2
114::: 2 rnA
~
'"
~
It~llmA
>
~
50=
0-
15
08
I
E
0.4
12
1!4JnA
-4
-8
-12
-14 -10 -6 -2
6
10
14
18
-50
8.0
"
7.0
Typical Power Supply
Typical Power Supply
Current vs Temperature
CUrrent vs VEE
ALL 81TS HIGH OR LOW
ALL BITS HIGH OR LOW
-f--I--I'EE IWIT~
114 "'",2 rnA
,
.§.
0-
~
6.0
~
'
150
1.J- f--
11~ '" 2 rnA
Typical Power Supply
Current vs VCC
ALL BITS HIGH OR LOW
'14:: 2 rnA
'Ee
-f--
i
I
4.0
-f--
3.0
2.0
100
lEE
~. 5.0
i'"
. 50
TEMPERATURE I'C)
Vo - OUTPUT VOLTAGE IV)
-i--
1.0
'E~ WI~H 1~4 ~ 0.2 rnA
ICC
T
ICC
o
-50
lelE WiTH!) l1A -f--
50
100
150
'fC
I I
o -2'-4
-6 -8 -10-12-14-16-18-20
VEe - NEGATIVE POWER SUPPLY IV)
TEMPERATURE ("C)
2
4
Reference Input j
Frequency Response
~
5
~
0=
~
>
;::
~
-
r....
-2
-4
"\.
'\
'\
-6
-8
-10
-12
-14
-16
0.1
Unless otherwise specified: R 14 =
R15 = 1 kn,C = 15 pF,pin 16 to VEE;
RL = 50n, pin 4 to ground.
Curve A: Large Signal Bandwidth
Method of Figure 7, VREF = 2 Vp-p
offset 1 V above ground
Curve B: Small Signal Bandwidth
Method of Figure 7, R L = 250n.
VREF = 50 mVp-p offset 200 mV
above ground.
Curve· C: Large and Small Signal
Bandwidth Method of Figure 9 (no
op amp, RL = 50!!), RS = 50n,
VREF = 2V. Vs = 100 mVp-p centered at OV.
I
B
A
C
0.3
10
f - FREQUeNCY IMHz)
3-13
6
8 10 12 14 16 18 20
VCC - POSITIVE POWER SUPPL Y IV)
DAC0808, DAC0807,
DAC0806
Vee
o13
lsa
MSB
GNO
Al
A2
A3
A4
A5
AD
10
A1
11
AB
12
~
·VRHo·_1 ,
~
.."
VEE
FIGURE 2. Equivalent Circuit of the DAC0808 Series
co
»»
test circuits
nn
00
I~i
DIGITAL
INPUTS
The resistor tied to pin 15 is to temperature compensate the
bias current and may not be n~ces~ary for all applications.
AS
10 = K
(
r-o---~-o ~BTPUT
AS
A)
Al
A2. A4
2
+
where K '"
4
+ 16 +
A5
A6
32 + 64
A7
+
128
AS)
+ 256
VREF
R14
i,_ '-_,..,........J
AS
1
0)0)
VI and 11 apply to inputs Al-AS.
and AN = "'" if AN is at high level
AN = "0" if AN is at low level
iEEt
VEE
FIGURE 3. Notation Definitions Test Circuit
Msa
A'
A1
AJ
A4
OAC1200
12-81T
O·TO A
CONVERTER
A'
1~O.O2%
A.
EARORMAX)
---0;;
~
Lsa
f-<>-
rrrr
5k
50k
L~
O.1iJ~-b
VR'~j1Ei
Ion
,
Msa
-
6
-
rV
U
14
oro IOV OUTPUT
ERROR
(lV-l%)
13
,
)
H·BIT
COUNTER
9
DACOBOB
SERIES
~
10
"
11
~1
IkE
-=
VEE
FIGURE 4. Relative Accuracy Test Circuit
24V---r------~
'iN
2Voc
1k
~O.1iJF
Ik
SETTWIGTIME
eo {FIGURE 5)
-4:FOR SETTUrm TIME
1-'-0---...- ....-0 eO ~~I~~UH~~MCO~~ i~l~I~I~ls
'IN
Teas·",,·
TRANSIENT
RESPONSE
lN44S4 (LOW CAPACITANCE.
FAST RECOVERY DIODE)
FIGURE 5. Transient Response and Settling Time
3·15
1.4V
00
0')0)
c
»
n
o
0)
o.......
.....
oa)
test circuits
(Continued)
vee
o
Vee
o
--<:HH
FIGURE 8. Negative V REF
E-o
Vo
FIGURE 9. Programmable Gain Amplifier or Digital Attenuator Circuit
'applicatIon hintsREFERENCE AMPLIFIER DRIVE AND COMPENSATION
114. For bipolar ,reference signals, as in the multiplying
mode, R 15 can be tilid to.a 'negative voltage corresponding to the minimum input level. It' is possible to
eliminate R15 with only a small sacrifice in accuracy
and temperature drift.,
'
The reference amplifier provides 'a voltage at pin 14 for
converting'" the' reference volta'geto a current, and a
turn-around circuit or current mirror for feeding the
ladder. The reference amplifier input current, 114, must
always flow into pin 14, regardless of the set-up method
or refere'nce'voltage polarity.
The compensation capacitor value must be increased
with increases in R14, to maintain proper phase margin;
for R14 values of I, ,2.5 and 5 kn, minimum capa'citor
values, are 15, 37 and ni pF: The capacitor may be tied
to either VEE or ground; but using VEE, increases
negative supply rejection.
Connections for a positive voltage are shown in Figure 7.
The reference voltage source supplies the full current
3-l6
application hints
,(Continued)
of the monolithic resistor ladder. The reference current
may drift with temperature, causing a change in the
absolute accuracy of output current. However, the
DAC0808 has a very low full-scale 'current drift with
temperature.
A negative reference voltage may be used if R 14 is
grounded and the reference voltage is applied to R15 as
shown in Figure 8. A high input impedance is the main
advantage of this method. Compensation involves a
capacitor to VEE on pin 16, using the values of the
previous paragraph. The negative reference voltage must
be at least 4V above the VEE supply. Bipolar input
signals may be handled by connecting R14 to a positive
reference voltage equal to the peak positive input level
at pin 15.
The DAC0808 series is guaranteed accurate to within
±112 LSB at a full-scale output current of 1.992 mA.
This corresponds to a reference amplifier output current
drive to the la'dder network of 2 mA, with the loss of
,1 LSB (8 jlA) which is the ladder remainder shunted to
ground. The input current to pin' 14 has a guaranteed
value of between 1.9 and 2.1 mA, allowing some mismatch in the NPN current source pair. The accuracy test
circuit is shown in' Figure 4. The 12-bit converter is
calibrated for a full·scale output current of 1.992 mAo
This is im optional step since the DAC0808 accuracy is
essentially the same between 1.5 and 2.5 mAo Then the
DAC080B circuits' full-scale current is trimmed to the
same value with R14 so that a zero value appears at the
error amplifier output. The counter is activated and the
error band may be displayed on an oscilloscope, detected
by comparators, or stored in a peak detector:
When a DC reference voltage is used, capacitive bypass
to ground is recommended. The 5V logic supply is not
recommended as a reference voltage. If a well regulated
5V supply which drives logic is to be used as the refer·
ence, R14 should be decoup'led by connecting it to
5V through another resistor and bypassing the junction
of the 2 resistors with 0.1 jlF to ground. For reference
voltages greater than 5V, a clamp diode is recommended
between pin 14 and ground.
If pin 14 is driven by a high impedance such as a
transistor current source, none of 'the above compensa·
tion methods apply and'the amplifier must be heavily
compensated, decreasing'the overall bandwidth.
Two 8-bit D-to-A converters may not be used to
construct a 16-bit accuracy D·to-A converter. 16-bit
accuracy, implies a total error of ± 1/2 of one part in
65,536, or ±0.00076%, which is much more accurate
than the ±0.019% specification provided by the
DAC0808.
OUTPUT VOLTAGE RANGE
The voltage on pin 4 is restricted to a range of -0.6 to
0.5V when VEE ; -5V due to the current switching
methods employed in the DAC0808.
MULTIPLYING ACCURACY
The negative output voltage complia'nce of the DAC0808
is extended to -5V where the negative supply voltage is
more negative than -10V. Using a full·scale current of
1.992 mA and load resistor of 2.5 kn between pin 4
and ground will yield a voltage output of 256 levels
between 0 and -4.980V. Floating pin 1 does.not affect
the converter speed or pow~r dissipation. However, the
value of the load resistor determines the switching time
due to increased voltage swing. Values' of R L up to
500n do not significantly affect performance, but a
2.5 kn load increases worst·case settling time to
1.2 jlS (when all bits are switched ON). Refer to the
subsequent text section on Settling Time for more
details on output loading.
The DAC0808 may be used in the multiplying mode
with 8-bit accuracy when the reference current is varied
over a range of 256: 1. If the reference current in the
multiplying mode ranges from 16 jlA to 4 mA, the
additional error contributions are less than 1.6jlA. This
is well within 8-bit accuracy when referred to full-scale.
A monotonic converter is one which supplies an increase
in current for each increment in the binary word.
Typically, the DAC0808 is monotonic for all values of
reference current above 0.5 mAo The recommended
range for operation with a DC reference current is 0.5 to
4mA.
OUTPUT CURRENT RANGE
, SETTLING TIME
The output current 'maximum. rati,ng of 4.2 mA may be
used only for. negative supply voltages more negative
than -7V, due to the increased voltage drop across the
resistors in the reference current amplifier.
The worst-case switching condition occurs when all
bits are switched ON, which corresponds to a low·to-high
transition for all bits. This time is typically 150 ns
for settling to within '±112 LSB, for 8·bit accuracy,
and 100 ns to 1/2 LSB for 7 and 6·bit accuracy. The
turn OFF is typically under 100 ns. These times apply
when RL S 500n and Co S 25 pF.
ACCURACY
Absolute accuracy is the measure of each output current
level with respect to its intended v'alue, and is dependent
upon relative accuracy and full·scale current drift.
Relative accuracy is t[1e measure of each output current
level as a fraction of the full-scale current. The relative
accuracy of the DAC0808 is essentially constant with
temperature due to the exc~lIent temperature tracking
Extra care must be taken in board layout since this is
usually the dominant factor in satisfactoy test results
when measuring settling time. Short leads, 100 jlF
supply' bypassing for low frequenCies, and minimum
scope lead length are all mandatory.
3·17
CC
J>J>
00
00
0000
00
moo
c
J>
oo
(X)
o.......
o
C'i
C'i
(3
MIN
Digital
Inpu~
17V
±25V
V+ to Gnd
-100 mV to V+
Voltage Range
DC Voltage at Pin .1 or Pin 2 (Note 31
DAC1020LD, DAC1021 LD,
DAC1022LD, DAC1220LD,
DAC1221 LD, DAC1222LD
~5°C,to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
-55"C
UNITS
+125
"C
+70
"C
n
oI\)
...A.
5'
DAC1020LCD, DAC1021 LCD,
DAC1022LCD, DACl220LCD,
DAC1221LCD, DACl222LCD
300"C
MAX
0
c
n
l>
...A.
I\)
I\)
o
Electrical Characteristics
(v+ ~ 15V, VREF ~ 10.000V, TA ~ 25°C unless otherwise specified)
PARAMETER
CONDITIONS
DAC1020, DAC1021,
DAC1022
MIN
TYP
MAX
Resolution
linearity Error
10
DAC1220, DAC1221,
DAC1222
MIN
TYP
MAX
UNITS
Bits
12
TMIN < T A < TMAX,
-10V < VREF < +10V,
(Note 2)
1O·B it Parts
DAC1020, DAC1220
0.05
0.05
9-Bit Parts
DAC1021, DAC1221
0.10
0.10
% FS
B-Bit Parts
DAC1022, DAC1222
0.20
0.20
% FS
-10V -::; VREF -::; +10V,
0.0002
0.0002 % FS/oC
Linearity Error Tempco
% FS
(Note 1)
Full-Scale Error
-10V -::; VREF -::; +10V,
0.3
0.3
% FS
(Notes 1 and 2)
Full-Scale Error Tempco
TMIN < TA < TMAX,
(Note 2)
Output Leakage Current
lOUT 1
TMIN-::;TA-::;TMAX
All Digital Inputs Low
200
200
nA
lOUT 2
All Digital Inputs High
200
200
nA
Power Supply Sensitivity
0.001
All Digital Inputs High,
0.001
0.005
0.005
% FStC
% FSIV
14V -::; V+ -::; 16V, (Note 2),
(Figures 7 and 2)
V REF I nput Resistance
5
Full-Scale Current Settling
RL = 100n from 0 to 99.95%
Time
FS
All Digital Inputs Switched
10
20
5
500
10
20
500
kn
ns
Simultaneously
VREF Feedthrough
All Digital Inputs Low,
10
10
mVp-p
VREF = 20 Vp-p @ 100 kHz
Output Capacitance
lOUT 1
lOUT 2
Digital Input
All Digital Inputs Low
37
37
All Digital Inputs High
120
120
pF
All Digital Inputs Low
120
120
pF
All Digital Inputs High
37
37
pF
pF
(Figure 7)
Low Threshold
TMIN
0
t-
l""-
I
:::>
~
<
e;
l-
0.5
.........
<
'"
Ci
,
........
a:
0
a:
a:
'"2-0.05
....
,
'\
-0.10
0
'0
20
4~
60
80
5.0
TA - TEMPERATURE (OC)
10.0
15.0
V+ (VOLTS)
FIGURE 1. Digital Input Threshold vs
Al11bient Temperature
FIGURE 2. Gain Error Variation vs V+
;
.,,'
,
,
"
-
3·20
c
Typical Applications
The following applications are also valid for 12·bit
systems using the DAC1220 and 2 additional digital.
inputs.
-10k if more than 4 digital inputs are high; ROUT is
-30k if a single digital input is high, and ROUT
approaches infinity if all inputs are low.
Operational Amplifier Bias Current (Figure 3)
o
Ope~ational Amplifier VOS Adjust (Figure 3)
The op amp bias current, Ib, flows through the' 10k .
internal feedback resistor. BI·FET op amps have low
Ib and, therefore, the 10k i< Ib error they introduce is
negligible; they are strongly recommended for· the
DAC1020 applications. The 'b' of the LM741 type
bipolar op amps is of the order of 200 /1A and if a
VREF;::; 10V is used, bias curren.t cancellation schemes
are recommended.
Connect all digital inputs, A 1-A 10, to ground and
adjust the potentiometer to bring the op amp VOUT
pin to within ±1 mV from ground potential. If VREF is
less' than 10V, a finerVos adjustment is required. It is
helpful to increase the resolution of the VOS adjust
procedure by connecting a 1 kn resistor between the
inverting input of the op amp to ground. After Vas has
been adjusted, remove the 1 kn.
VOS Considerations
Full·Scilie Adjust (Figure 4)
Switch high all the digital inputs, A 1-A 10, and measure
the op amp output voltage. Use a 500n potentiometer,
. as show~, to bring II",oUTII to a voltage equal to VREF x
1023/1024.
.. .
The output impedance, ROUT, of the DAC is modu·
lated by the digital input code which causes a modulation
of the operational amplifier output offset. It is therefore
recommended to adjust the op amp Vas. ROUT is
SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER
OP AMP FAMI LY
CF
Ri
P
Vw
CIRCUIT SETTLING
TIME, ts
CIRCUIT SMALL
SIGNAL BW
LM357
10 pF
2.4k
25k
V+
1.5/15
1M
LM356
22 pF
00
25k
3/1s
0.5M
LF351
24 pF .
0
00
10k
V+
V-
10k
V-
4/1s
40/15
0.5M
00
LM741
MSD
LSD
AI A2 A3 A4 AS A6 A7 AS A9 'AID
AI
VOUT=-VREF ( .
.2
A2
4
A3
8
Al0)
1024
+ - +-+ ... - -
.
-10V $. VREF $. 10V .
..
1023
o $. VOUT $. - 1024 VREF
where
AN = 1 if the AN digital'input i. high
AN = 0 if the AN digital. input i.low
FIGURE 3. Basic Connection: Unipolar elr 2·0uadrant Multiplying
Configuration (Digital Attenuator)
3·21
200 kHz
»
O.
...
o
I\)
p
C
::t=O
...
I\)
I\)
o
o
C'oI
,..
o
C'I
Typical Applications
(Continued)
MSB
LSB
Al 'A2 A3 A4' A5 AS A1 AB A9 AID
(Continued)
COMPLEMENTARY OFFSET BiiJARY
.(BIPOLAR) OPERATION
MSB
.
LSI
AI A2 A3 A4 AS AS Al AH A9AIO
DIGITAL INPUT
a a 9
a a 0
Your
0
1
1
1
I
1
0
0
I
0
0
I
0
a a a
a 0 a a
1
1
1
1
VOUT
a a a a a
0
I
0
0
1
0
0
0
I
1
1
1
1
a
a
0
0
1
0
a
0
1
1
1
1
+VREF
VREF x 1022/1024
VREF x 2/1024
0
-VREF x 2/1024
-VREF (1022/1024)
•
•
AI
A2
AIO
I)
VOUT= -VREF ( + - - + ... + - - - - 2
4
1024
1024
where: AN = +1 if AN input is high
AN = -I if AN input is low
X(1023 )
VREF
RLADDER
1024
By doubling the output range we get half the resolution
The 10M resistor, adds a I LSB "thump", to allow full
offset binary operation where the output reaches zero
for the half·scale code. If symmetrical output excursions
are required, omit the 10M resistor.
lOUT I + lOUT 2 =
FIGURE 7. Bipolar 4·Quadrant Multiplying Configuration
Operational Amplifiers VOS Adjust (Figure 7)
Gain Adjust (Full·Scale Adjust)
a)
Assuming that the external 10k resistors are matched to
better than 0.1%, the gain adjust of the circuit is the
same with the one previously discussed.
b)
Switch all the digital inputs high; adjust the Vas
potentiometer of op amp B to bring its output to a
value equal to -(VREF/1024) (V).
Switch the MSB high and ·the remaining digital
inputs low. Adjust the Vas potentiometer of op
amp A, to bring its output value to within a 1 mV
from ground potential. For VREF < 10V, a finer
adjust is necessary, as already mentioned in the
previous application.
Msa
LSI
AI A2 Al M A$ AS AJ AI All AID
USB.
LSB
AI A2 AJ A4 AS AS A1 Ai AI AID
TRUE OFFSET BINARY OPERATION
DIGITAL INPUT
1
1
0
1
0
a
1
1
0
0
a a a
a 0 0
1
1
VOUT
I
1
0
o·
0
0
1
0
0
1
0
0
VREF x 1022/1024
0
-VREF
ts = 1.8 I'S
use LM336 for a voltage reference
FIGURE 8. Bipolar Configuration with a Single Op Amp
~=~
•
R4=(2Av--I)R
•
R3 + RIIIR2 = R; Av - = VOUT(PEAK) , R ~ 20k
VREF
Example: VREF = 2V, VOUT (swing) ~ ±IOV: AV- = 5V
Then R4 = 9R, RI = 0.8 R2. If RI = 0.2R then R2 = O.2SR,
R3 = 0.64R
'RI
AV--I
. FIGURE 9. Bipolar Configuration with Increased Output Swing
3·23
o
I\)
5'
c
l>
(")
...a.
I\)
I\)
o
Note that:
•
(")
...a.
oN
N
,....
Typical Applications
(Continued)
" MSB
o
LSB
Al A2 A3 A4 A5 A6 A7 AB A9 AID
(Continued)
o
~
o
N
P
c
l>
1!iV
I I"
'.' ='=
r.:'VC~C"--,h
-,
~
MM74C04
c
T,.T,,?
81 4
16
82 5
15
·A.!L.,
QAll.
BJ
ZOA6
r---~-44-1~ AS ~
:.':
y~
r-- ~
LO
OWN
l'"
,..!!
CRY
•~
GNO
UP
,--f-t-t-l-j?O-'I;>O-"I A4
r -+++--C"'>O--=i' AJ
'RW
~
,
.,1.
"0
h
.=~ ", n
A
"A
':'
~
Vee
LO
UP
J'
GNO
OWN
•
"r--"""iI-'lM,..
!?..
~SO
'----"l."
R.
LSO
VREF.
~O
A2.!...- L..JjL;C_LK_..:GTNO=-_".Jh
:m
<:
I
,nMM14C14
.
~
I
I.!!
A<'IA=B
' -_ _ _ _....;'::.1' SO
. AD ~
L.._ _ _ _ _ _~~ 81 A> 8
:~ a
7
1!ZMM14C74
~~CL~
A1j.:--1......
":"
OSTOP~
16
B
'
15V
JrlLJ
. ~~:~J4l ~
6
+
lIZLFlll33
II :
I
-.,
T,--
\9~k
.-+-:+--1
"
~VEE:iL,.,
.....
J
.
10k
-15V
'"
VA
Vcc
1
~:'2
10k
ISV
LF347
11
-15V·
-L-
*O.'~F
15V
MM14COO
(fREQUENCY
CONTROL)
~
•
Output frequency
•
Output voltage range ~ OV -1 OV peak
•
THO< 0.2%
feLK ; fMAX '" 2 kHz
512
•
Excellent amplitude and frequency stability with temperature
•
Low pass filter shown has a 1 kHz corner (for output frequencies below 10 Hz. filter corner should be reduced)
•
Any periodic function can be implemented by modifying the contents of the look up table ROM
No start up problems
.•
. FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look·Up ROM
3·25
--
4.19k
Cl:
Sit
-
NOr!-~+ l..'::-o
(A~ffi~~DE
'-o!f-o
'V
PS VCC
pt.;~ ~'''r
£:1,
SD.UARE
-.::15~-d'~o().:::NC~"..
.,g_'
:-:-::!:" 13; . +--------1
,-~:::::::::::::::,,~:~ ~
'\.J
+
~k-
i
A
*i
14 ......aSINEWAVEOUT
r-______~-_-_-_-_-~--.-o-=!J A'
13
CLR
!jj
':'
RAOB-4.7IIN
I
..I!~;a
Me "SSCE
~
~
'OV
r:J...
DC":-4~-----~""""i><>--e>O'::.jB AB.
D~h
~A7
eLR
o
JL
4k
, -.....-o15V
-l'
CONTROL)
o
N
,N
Typical Applications
(Continued)
"t-
U
«
C
o
N
o
"t-
U
«
C
TO DAC1020
DIGITAL INPUTS
CLOCK
15V
START!
MM74COO - NAND gates
MM74C32 - OR gates
MM74C74 - D flip-flop
MM74C193 - Binary upl
down counters
•
•
Binary up/down counter digitally "ramps" the DAC output
Can stop counting at any desired 1G·bit input code
•
Senses up or down count overflow and automatically reverses direction of count
FIGURE 13_ A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits
3-26
o
l>
Definition Of Terms.
Resolution: Reso!u'tion is defined as the reciprocal of
the num ber of discrete steps in the 0/A output. It is
directly related to the number of switches or bits within
the O/A. For example, the OAC1020 has 2 10 or 1024
steps while the OAC1220 has 212 or 4096 steps. There·
fore, the OAC1020 has 10·bit resolution, while the
OAC12:10 has 12-bit resolution.
Power Supply, Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the
O/A full·scale output:
Settling Time: Full·scale settling time requires a zero to
full·scale or full·scale to zero output change. Settling
time is the time required from a code transition until
the O/A output reaches within ±1/2 LSB of final output
value.
Linearity Error: Linearity error is the maximum devia·
tion from a straight line passing through the endpoints
of the O/A transfer characteristic. It is measured after
calibrating for zero (see Vas adjust in'typical applications) and full·scale. Linearity error is a design parameter
intrinsic to the device and cannot be externally adjusted.
Full-Scale Error: FUll-scale error is a measure of the
output error between an ideal 0/ A and the actual device
output. Ideally, for the OAC1020 full-scale is VREF 1 LSB. For VREF ~ 10V and unipolar operation,
VFULL-SCALE ~ 10.0000V - 9.8 mV ~ 9.9902V.
Full-scale error is adjustable to zero as shown in Figure 5.
OAe FAILS END POINT TEST
LINEARITY ERROR 2: 1 LSD
DIGITAL INPUT
IN
IN
a
bl
b2,
(a) End point test after zero and full·scale adiust,
The DAC has 1 LSB linearity error
(bl By shifting the full-scale calibration on of the DAC
of Figure (b 7) we could pass the "best straight
line" (b21 test and meet the ±1/2 LSB linearity
error specification
Note. (ai, (b1) and (b21 above illustrate the difference between "end point" National's linearity test (al and "best straight line" test.
Note that both devices in (a) and (b2) meet the ±1/2 LSB linearity error specification but the end point test is a more "real life" way
of characterizing the DAC.
'
3·27
.
o
~
o
I\)
p
o
l>
~
I\)
I\)
o
"':M
00
NN
~~
UU
'6 FEEDBACK
80k
18 CURRENT
U..J:!~~"""--"'-'''--''-'''''--'''--'''-''''''--'''-''''
+-,,"'---0 MODE
OUTPUT
19 ~g~lAGE
OUTPUT
Dual-ln·Lino Package
LSB
2-12
_~=:::::::;:-:r::==l~2~4
23 ANALOG AND DIGITAL GND
2. 11
22 -15V
~O
2-g
"W
2-B
VREF OUTPUT
+5\1
2-1
2-6
CURRENT MODE OUTPUT
VOLTAGE MODE OUTPUT
OFFSET
R24
15 FEEDBACK
JSk
14 REF COMP
13 VAEF INPUT
20
.........0 +5V
..!!.i:::==::!==:f=-FUll SCALE ADJ
MSB
TOP VIEW
13
21
FULL SCALE VREF
ADJUST
OUT
*R21 =R22 = 16k for DAC1202/1203 (BCD)
3-28
Absolute Maximum Ratings
Supply Voltage (V+ & V-I
±18V
Logic Supply"Voltage (VCC)
+10V
Logic Input Voltage
'-0.7V to +18V
Reference Input Voltage
-OV, +18V
Power Dissipation
(see graphs)
Short Circuit Duration (pins 18, 19 & 21)
Continuous
Operatin~ Temperature Range
DAC1200HD, DAC1201HD, DAC1202HD, DAC1203HD
DAC1200HCD, DAC1201HCD, DAC1202HCD, DAC1203HCD
_55°C to +125°C
_25°C to +85°C
Storage Tempera'ture Range
-65°C to +150°C
300°C
Lead Temperature (soldering, 10 sec.)
DC Electrical Characteristics DAC1200/1201 Binary D/A
(Notes 1, 2)
DAC1200/1200C
PARAMETER
TYP
MIN
MAX
TA = 25"C
Offset Voltage
TA = 25°C
MIN
TYP
MAX
12
12
Resolution
Ltnearity Error (Note 3)
DAC1201/1201C
UNITS
CONDITIONS
Bits
±0.0122
to.0244
±0.0488
±0.0976
5
10
10
15
% FS
% FS
rnV
rnV
Voltage Mode Full·Scale Error (Note 3) VREF = 10.240V
0.01
0.1
I 0.02
0.2
% FS
Voltage Mode Full·Scale Error
0.1
0.6
0.1
0.7
% FS
Pin 21 connected to Pin 14, TA = 25°C
Monotonlclty (Notes 3. 4)
Guaranteed over the temperature range
.1V+ = i2V
.1V- = ±2V
Voltage Mode Power Supply
Sensitivity
.1VCC = ±1 V
Output Voltage Range
TA= 25°C
VREF = 10.240V
1
±10.5
RL = 5k
Voltage Mode Output Short Circuit "
TA = 25"C
Current limit
Current Mode Voltage Compliance
OrnA< IREFO(2rnA, TA=25"C
VIN = 2.5V
Logic "0" Input Current"{BIt ON)
VIN = OV
V+= 15.0V
V·- = -'lS.0V
VCC = 5.0V
TA=25"C
3·29
0.02
0.02
0.02
±12
20
10.190 10.240
50
% FS/V
rnA
V
kll
15
10.290 10.190
% FS/V
% FS/V
V
±2.5
2.0
Logic. "1" Input Current (Bit OFF)"
ICC
50
15
10.240 10.290
V
V
2.0
Logic "0" Input Voltage (Bit ON)
Power Supply Current
0.002
0.002
0.002·
±10.5
±2.5
(Note 6)
Logic "1" Input Voltage {Bit OFFI
1+
1-
0.02
0.02
0.02
±12
20
Current Mode Output Impedance
Reference Voltage
0 002
0,002
.
0.002
0.8
0.8
V
10
10
pA
"10
-100
-10
-100
pA
10
25
20
15
30
25
10
25
20
15
·30
25
rnA
mA
rnA
";('1)
DC Electrical Characteristics DAC1202/1203 3-Digit BCD D/A
00
NN
,....
,....
0(')
««
CC
"-"-
ON
00
NN
,..
,..
00
««
CC
PARAMETER
-
MIN
TYP
MAX
3
Resolution
Linearity Error (Note 5)
TA = 25°C
Offset Voltage
TA = 25°C
DAC1203/1203C
DAC1202/1202C
CONDITIONS
(Notes 1,2)
MIN
TYP
UNITS
MAX
Digits,
3
0.01
0.02
0.05
0.;
% FS
% FS
1
5
10
1
10
15
Voltage Mode Full·Scale Error (Note 5) VREF = 10.000V
0,01
0.1
0.02
0.2
% FS
Voltage Mode Full·Scale Error
0.5
0.6
0.7
%'FS
Pin 21 connected to Pin 14, T A = 25°C,
Monotonicity (Notes 4. 5)
Guaranteed over the temperature'range
j,V+ = ±2.V
,:,.V·· = -t2V
j,VCC = ±1 V
Voltage Mode Power Supply
Sensitivity
Voltage Mode Output Voltage
Range
RL =
Voltage Mode Output Short Circuit
Limit
TA = 25°C
Current Mode Compliance
(Note 6)
0.002
0.002
0.002
TA = 25°C
VREF = 10.000V
5~
±10.5
±10.5
50
±2.5
A.,; IREF"; 2mA. TA = 25°C
9.950
Logic "1" Input Voltage (Bit OFF)
±12
V
50
V
kU
10.000 10.050 9.950
VIN = 2.5V
Vlf',I =OV
1+
I-
V+ = 15.0V
V- = -15.0V
VCC;' 5.0V
ICC
V
0.8
V
J1A
1
10
1
10
-10
-100
-10
-100
J1A
15
30
25
10
25
20
15
30
25
rnA
rnA
rnA
10
25
20'
TA=25°C
V,
10.000 10.050
2.0
0.8
Logic "0" Input Current (Bit ON)
mA
10
2.0
Logic "1" Input Current (Bit OFF)
%FSN
%FSN
'%FSN
i2.5
"a" Input Voltage (Bit ONt' .
Supply Current
0.02
0.02
0.02
20
10
Reference Voltage
P~,,:er
0.002
0.002
0.002
0.02
0.02
0.02
±12
20
Current Mode Output Impedance
Logic
mV
mY'
AC Electrical Characteristics DAC1200/1201/t202/1203'
\
PARAMETER
CONDITIONS (T A
= 25°C)
TVP
MAX
Voltage Mode
±1 LSB Settling Time (Note 6)
DAC1200/1202; Ve';;;; 1.25 mV
DAC1201/1203, Ve ';;;;5.0 mV
1.5
1
3.0
3.0
Voltage Mode Full·Scale
Change Settling Time (Note 6)
DAC1200/1202, Ve';;;; 1.25 mV
DAc1201/1203, V e ';;;;5.0mV
2.5
2.0
5.0
5.0
Current Mode
Full·Scale Settling Ti me
RL 1 kn, CL';;;; 20pF
0';;;; e.IOUT';;;; 2mA
1.5
Voltage Mode Slew Rate
-10V';;;; e.VOUT';;;; +10V
15
=
MIN
UNITS
\
(J.S
(J.S
(J.S
fJ.S
'.
fJ.S
V/(J.s
Note 1: Unless' otherwise noted, these specifications apply for V+ = 15.0V. V- = -15.0V, and Vee = 5.0V over the temperature range -55°C to
+125°C for the DAC1200HD/1201/1202/1203 and -2SoC to +8SoC for the DAC1200HCD/1201/1202/1203.
.
Nota 2: All typical values are for T A = 25°C.
Note 3: Unless otherwise noted, this specification applies for VREF = 10.24V. and over the temperature range _25°C to +85°C. Testing
conditions include adjustment of offset to a V and full ..cale to 10.2375 V.
.
,
Note 4: The DAC1200, DAC1202 and DAC1203 are tested for monotonicity by stimulating all bits; the DAC1201 is tested for monotoniclty by
stimulating only tha 10 MSBs and holding the 2 LSBs at 2.0V (i.e., 2 LSBs are OFF).
Note 5: Unless otherwise noted, this specification applies for VREF = 10.000V, and over the temperature range _25°C to +85°C. Testing
conditions include adiustmenfof offset to OV and full·scale to 9.990V.
Note 6: Not tested - guaranteed by deSign.
Nota 7:
(AVOUT=10V)
3·30
CC.
»»
Typical Performance Characteristics
00
..........
Maximum Power Dissipation
2.5
I
2.25
1'\"\,: JA • 4~oCJW I--
~
"c
~
1.5
C
~I
10
I
t-
+15VI
25
.s
-
~
r--
10
15
tOO
TEMPERATURE
(~CI
125
150
.
1 lSB Transition
1011 ... 1->1100 ... 0
VO=O,10V
CF = 30pF
TA = 25~C
-55 -25
25
50
r--
00
..........
t15V
NN
00
J
W~
ALL INPUTS LOGIC HIGH
15100
o
-55 -25
125
25
50
75
100
125
TEMPERATURE ( C!
TEMPERATURE eel
10V Full Scale Settling Time
lOV Full Scale Pulse Response
Applications Information
CURRENT MODE
DA
A2
1. Introduction
The DAC1200 series D/A converters are designed to
minimize adjustments and user·supplied external com·
ponents. For exa'mple, included in' the package are a
buffered reference, offset nulled output amplifier, and
application resistors as well as the basic 12·bit current
mode D/A.
VOUT
.
.
~1·Rn
'VOUT = (IZERa to IFULLSCALEIIR21+"""ff221
= (OmA to 2.0475mA)(5kll)
= OV to +10.2375V
However, the DAC1200 series is a sophisticated building
block. Its principles of operation and the following
applications information should be read before applying
power to the device.
'Values shown are for VREF = 10.240V.
1 LSB Voltage Step = 1046~~V = 2.SmV.
The user is referred to National Semiconductor Applica·
tion Notes AN·156 and AN·157 for additional informa·
tion.
1 LSB Current Step
=
~~ = 0.5~A
FIGURE lA. DAC1200/DAC1201 Unipolar Operation
2. Power Supply Sel"ection & Decoupling
Selection of power supplies is important in applications
requiring 0.01% ·accuracy. The ±15V supplies should be
well regulated '(±15V ± 0.1%) with less than 0.5mVrms
of output noise and hum.
r-'CNoUo.RRrr,rnNT""mDorn,riDTO
1 2481!ih,A
+--w-.-(
D/A
A2
To realize the full speed capability of the device, all three
power supply leads should be bypassed with 1 pF
tantalum electrolytic capacitors in shunt with 0.01 pF
ceramic disc capacitors no farther than Y, inch from the
device package.
Vour
,
'VOUT
= (IZERa. to
IFULLSCALE)(B£I...:....Bll.)
R21 + R22
= (0 to 1.24875mA)(8kS/)
= OV to 9.990V
3: Unipolar and Bipolar Operation
The DAC1200 series D/A's may be configured for eithe~
unipolar or bipolar operation using resistors provided
with the device. Figures 1 A 'and 1 B illustrate the proper
connection ..for binary. and BCD unipolar operation.
'Values shown are for "REF = 10.000V.
1 LSD Voltage Step = l~O~~O = 10mV
1 LSQ Current Step = l~~V =- 1.2SI'A
Bipolar operation is accomp.lished by offsetting the
output amplifier. A3 as shown in figures 2A and 2B.
FIGURE lB. DAC1202/DAC1203 Unipolar. Operation
3·31
NN
00
NO
................
CO
»»
.J
~
ALL INPUTS ldGIC lOW
50
-
I
20
Z
o
25
1_15J
-(iii).----J--oVOlJT
................
5. Current Mode Operation
OC\l
00
C\IC\I
..........
ou
««
CO
'VOUT = 10 to 2.0475mAIR22 -
V~i; R21
= 10 to 2.0475mAIR22 - VREF. R21 :;
~22
. =.-10.240 to + 10.235V
'Values shown are for VREF = IO.240V
I LSB = SmV.
FIGURE :lA. DAC1200/DAC1201 Bipolar Operation
Access to the summing, junction of A3 affords current
mode operation either with a resistive load or to drive a
fast-settli,ng external operational amplifier. The loop
around A3 should not be closed in current mode operation. There is a ±2.5V maximum,compliance voltage at
A2's output (pin 18) which restricts the maximum size
'of the load resistor; i.e., RL x IFULLSCALE .;;; 2.5V.
Note: IFULLSCALE "" 2 mA for DAC1200/DAC1201
and'" 1.25 mA for DAC1202/DAC1203.
6. Se~i:ling Time & Glitch Mini.rtization .
i)......-......-oVOUT
'VolJ'r = IOmA.to 1.24875niAIIR221
~ ~~~ VREF
= -10.000V to +9.80V
'Yalues shown are for VREF = 10.OOOV.
I LSD Voltage Step = 20mV.
The settling time of the DAC1200 series ana the glitch
which occurs between major, input code changes may be
improved by placing a 10 to 30pF. capacitor between
,pins 18 (current-mode output) and 19 (voltage mode
''outputl. The capacitor is used to cancel output capacitance of the current mode D/A and stray capacitance at
pin 18.
FIGURE 2B. DAC1202/DAC1203 Bipolar Operation
7. Current Output Boosting
The DAC1200 series may be operated as a "power D/A"
by including a current buffer such as the LH0002 or
LH0063 in the loop' with, A3 as shown in figure,' 5.'
External resistors may be used to achieve alternate zero
and full-scale voltages. It is advantageous to utilize R21
and R22 even in these applications since they are ciosely
matched in TCR and temperature to the internal array.
Figure 3 illustrates the recommended circuit for zero to
5V operation'. REXTshould be of metal film or wirewound construction with a TCR of less than 10ppmtC.
VOUT
FIGURE 5 .. Current Boosted Output
>-- S kG, Pin IS
Output Short·Circuit Current
Pin IS
Output Impedance
Pin 15, Closed Loop.
,
Current ~ode Output Range
±0.1
±30.
±10
±12
±10
±20
O.OS
Impedance
Bipolar
Reference Voltage
-2 rnA:<; iREF :<;'2 mA
Logic ".," Input Voltage
VIN
VIN
= 2.5V
= OV
±12
V
±20
mA
G
±2.S
6.3
4.4
6.6
6.0
6.3
6.6
V
IS
kG
4.4
kG
6.3
V
2.0
.,2.0
V
0.8
O.S
Logic "0" Input Current
ppmfC
mA
15
4.4
6.0
Logic "0" Input Voltage
(BitON)
Logic "'" Input Cl;Jrrent
% of FSR
±10
0.05
±2.S
15
2.0
(Bit OFF)
to.l
V
±10
O.OS
±2.S
Unipolar
FSRfc
Oto'-2 mA
±1.0
Bipolar, Pin 20
Current Mode Compliance
±12
±20
Unipolar, Pin 20
Current Mode Output
ppm of
±10
±t5
LSB
ppm of
±2.S, ±S.O, ±10, 0 to +5,0 to +10
Resistors
Output Voltage Swing
±3
±20
Using I nternally Supplied
Output Voltage Range
±10
LSB
LSB
,.
Bipolar, TMIN:<;TA:<;TMAX
UNITS
Bits
±1/2
. ±1/2
±1 .
Unipolar, TMIN:<; T A :<; TMAX
Zero·Scale Drift (Olfset
Drift)
DAC1280HCD
MAX
12
±1/2
±1/2 '
Differential N0ll-Linearity
Zero-Scale Error (Offset) .
TVP
MIN
12
TA = 2SoC
Linearity Error
Power Supply Sensitivity
,
DAC1285H, DAC1285HC, DAC1280HC 8inary D/A (Notes 1 and 2)
Resolution
Power Supply Current
.
'
0.8
V
t
10
I
to
I
10
IlA
-10
-100
-10
-tOO
-10
-100
IlA
1+
to
10
10
mA
1-
25
ICC
20
2S
20
25
20
mA
0.002
0.002
0.002
3-36
mA
%01
FSR/%V
DC Electrical Characteristics
PARAMETER
DAC1286H, DAC1286HC, DAC1287HC BCD D/A (Notes 1 and 2)
CONDITIONS
MIN
Resolution
DAC1286HD
TVP
MAX
3
3
TA = 25°C
TMIN::; TA ::; TMAX. (Note 3)
Linearity Error
DAC12B6HCD
MAX
MIN
TVP
DAC1287HCD
TVP
MIN
MAX
3
±1/2
±1/2
Digits
±1
±1
±1/2
tl/2
Differential Non-Linearity
±112
±1/2
±1/2
Zero·Scale Error (Offset Error) (Notes 4 and 5)
±0.05
±0.05
iO.05
Zero-Scale Drift (Offset Drift)
Unipolar. TMIN::; T AS: TMAX
±1
±1
±1
(Note 5)
±0.1
Full~Scale
Error (Gain Error)
Full·Scale Drift (Gain Drift!
Output Voltage Range
Using Internally Supplied
Resistors
Output Voltage Swing
RL::::: 5 kn
I
±0.1
±20
TMIN::; T AS: TMAX
±30
±10
i12
±10
±20
Output Impedance
Pin 15, Closed Loop
Unipolar. Pin 20
±12
6.0
-2 rnA::; IREF::; 2 mA
Logic."l" Input Voltage
(Bit OFF)
6.3
6.6
6.0
6.3
i12
V
±20
rnA
n
= 2.5V
=OV
ICC
Power Supply Sensitivity
6.6
V
15
kn
6.3
V
2.0
V
O.B
0.8
Power Supply Current
ppmfC
±2.5
2.0
Logic "0" Input Voltage
(BitON)
1+
1-
% of FSR
rnA
15
2.0
VIN
±0.1
±lO
0.05
±2.5
15
VIN
±10
0.05
±2.5
Logic "0" Input Current
ppm of
FSRfc
a to -1.25
Current Mode Compi,iance
Logic "1" Input Current
LSB
% FSR
V
±20
0.05
Current Made Output
Impedance
Reference Voltage
LSB
LSB
Oto+l0
Output Short-Circuit Current
Current Mode Output Range
UNITS
0.8
V
j.- -21
16
6.3V
R23 ..
6.3k
I
1
I
1
I
1
1
I
A3
12·81T CURRENT MODE OIA
20
-=
....
OTO
1.9995 rnA
-
-~t-"-i
&'&-$-
R20
5k
R2;v
5k
A4
+
,I
-=
I DAC1280, DAC1285
VOUT
I
I
15 NC
I
1
I
~------------------------~
FIGURE 6. ±10V Bipolar Operation with External Operational Amplifier
3·41
Functional Description
(Continued)
DlGIT~L
.
INPUTS
D~C1285,
D~C1286
15V
15V
24
"'''''MK RI (FULL SCALE)
R2 (OFFSET) :>It-----....IVV'\r-------.I
10k-lOOk, lOT
3.9M
0.01 pF
-15V
'1'
IBM
10k-lOOk, lOT
-15V
FIGURE 6. Full·Scale and Adjustnient Circuits
Ordering InformatiQn
,
PART NUMBER
BINARY
BCD
25°C
LINEARITY
PACKAGE
TEMPERATURE
RANGE
DAC1285HD
DAC1286HD
0.Q1%
DIP
-55°C to +125°C
DAC1285HCD
DAC1286HCD
0,01%
DIP
-25°C to +85°C
DAC1280HCD
DAC1287HCD
0.025%
DIP
-25°C to +85°C
*See NS Package HY24A
3-42
.
~ Semiconductor
~National
Oigital-to-Analog Converters
LM150SJLM140S S-Bit OJ A Converter
general description
The LM150B/LM140B is an B-bit monolithic digital-toanalog converter (DAC) featuring a full scale output
current settling time of 150 ns while dissipating only
33 mW with ±5V supplies. No reference current (I REF)
trimming is required for most applications since the full
scale output current is typically ±1 LSB of 255 I REFI
256. Relative accuracies of better than ±O.19% assure
B-bit monotonicity and linearity while zero level output
current of less than 4 JlA provides B-bit zero accuracy
for I REF ~ 2 mAo The power supply currents of the
LM150B/LM140B are independent of bit codes, and
exhibits essentially constant device characteristics over
the entire supply voltage range.
applications, see DACOBOO data sheet. For more information, see DACOBOB data sheet.
features
•
~
AI
AJ
A4
AS
AS
Al
maximum
Full scale current match: ±1 LSB typ
7 and 6-bit accuracy.available
Fast settling time: 150 ns typ
Noninverting digital inputs are TTL and CMOS
compatible
• High speed multiplying input slew rate: B mAIJls
• Power supply voltage range: ±4.5V to ±lBV
• low power consumption: 33 mW @ ±5V
Dual-In-Line Package
,
~
A2
error
•
•
•
•
The LM150B/LM140B will interface directly with popular TTL, DTL or CMOS logic levels, and is a direct
replacement for the MC150B/MC140B. For higher speed
block and connection diagrams
Relative
accuracy:
±O.19%
LM 150B-B and LM 140B-B
AS
16 COMPENSATION
NC(NOTE 3)
RANG,E
CONTROL
GND
15 VREFI-I"
VEE
14 VREfl+J
'.-
GND
MSB AI
VREFI+)o-f=';:::==:::;---t==;-'--,
VREFI_lo-.l-::::t.>-+-===::-.;
COMPEN
lM15D8·8
lM1408
SERIES
13 Vee
12 AS l5B
A'
11 A1
A3
10 AS
A.
'
A.
TOP VIEW
typical application
Vee= SV
!
DIGITAL
INPUTS
.....- - o
~:>--"""
lM" .,
AI
A3
ID.ODDV = VREF
5.0DOk
A4
AS
A6
AI
V.
LSB AS
OUTPUT
VEE=-ISV
FIGURE I .• IOV Output Digital to Analog Converter
ordering .information
ACCURACY
OPERATING TEMPERATURE
RANGE
ORDER NUMBERS'
HERMETIC
HERMETIC
PACKAGE (DI6C)
PACKAGE (JI6A)
LM1S08D-8
LMIS08J-8
PLASTIC
PACKAGE (NI6A)
8-8it
-5Soc::; TA::; +12SoC
8-Bit
O°C s;, TA::; +75"C
LM1408J-8
7-Bit
O°C:5. TA s;, +7SoC
LM1408J-7
LMI40BN-7
6-Bit
O°Cs;,TA::;+7SoC
LM1408J-6
LM1408N-S
*Note. Devices may be ordered by using either order number.
3-43
LMI40BN-8
co
o
v
.,...
:E
..J
........
CO
oit)
absolute maxi.mum ratings'
(TA = 25°C u~less otherwise noted)
Power Dissipation (Package Limitation)
Cavity Package
Derate above t A = 25· C
Operating Temperature Range
LM1508-B
LM1408-8 Series
Power Supplv Voltage
Vee
VEE
Digital Input Voltage, V5-V12
Applied Output Voltage, Vo
Reference Current, '14
Reference A":,plifier Inputs, V14, V15
, 5.5VDC
-16.5 VDe
-10 VDe to +18 VDC
-11 VDC to +18 VDC
5mA
VCe,VEE
Storage Temperature Rang~ .
l000mW
6.7mwfc
-55°C ~ TA ~ +125°C,
O~ TA ~ +75·C
-55·C to +150·C
~
:E
..J
electrical characteristics
(Vee = 5V, VEE =-1.5 Voe, VREF/R14 = 2 rnA, LM1508·8: TA = _55°C to +125°e; LM1408·8, LM1408·7, LM1408·6,
TA = oOe to +75°e, and all digital inputs at high logic level unless otherwise noted.)
PARAMETER
Er
CONDITIONS
MIN
TVP
'l"AX
UNITS
%
Rel,ative Accuracy (Error Relative
to Full Scale 10)
LM1508·8
LM1408·8
LM1408·7, (Note 1)
. LM1408·6, (Note 1)
Settling Time to Within 1/2 LSB
: T A = 25°C (Note 2)
±0.19
%
±0.39
±0.7B
%
%
150
ns
(Includes tPLH)
Propagation Delay Time
30
TA = 25°C
±20
Output Full Scale Current Drift
MSB
VIH
VIL
MSB
Digital Input
100
ns
ppmte
L~gic Levels
2
High Level, Logic "1"
Voe
0.8
Low Level. Logio "0"
Voe
Digital Input Current
VIH = 5V
VIL = 0.8V
High level
Low Level
Reference Input Bias Current
0
-0.003
0.040
-O.B
rnA
rnA
-1.
-5
/lA
Output Current Range
10
Output Current
VEE = -5V
VEE = -15V, TA = 25°C
0
0
'2.0
2.0
VREF = 2.000V,
R14 = 100011
1.9
' 1.99
0
Output Current, All Bits Low
Output Voltage Compliance
2.1
rnA
4
/lA
-{J.55, +0.4
~5.0, +0.4
VEE Below -10V
8
Reference Current Slew Rate
Output Curre~t Power Supply
rnA
rnA
Er::; 0.19%, TA = 25°C
Pin 1 Grounded,
SRIREF
2.1
4.2
-5V,"; VEE"; -16.5V
0.05
VDe
Voe
mAil"
2.7
/lAN
2.3
-4,3
22
-13
rnA
rnA
5.0
-15
5,5
~1i;.5
Voe
Voe
Sensitivity
Power Supply Current (All Bits
Low)
ICC
lEE
Power Supply Voltage Range
TA = 25°C
4.5
-4.5
Vee
VEE'
P~wer' Dissipation
All Bits Low
Vee = 5V, VEE = -51(
Vee
~
5V, VEE = -15V
Vee =.15V, VEE = -5V
Vee = 15V, VEE = -15V
All Bits High
Note 1 i All current switches are tested to guarantee at least 50% of rated current.
Nota 2: All bits .wItched.
Nota 3: Range control 'not required.
is
3-44
33
170
106
305
90
160
rnW
rnW
rnW
rnW
Section 4
Data Acquisition
Systems
/'
~National
Data Acquisition Systems
~ Semiconductor
ADS1216HC 16-Channel, 12-Bit Data Acquisition
System. with Memory
General Description
Features
The ADS1216HC is a complete 16·channel (differential
a·channel) data acquisition system with 12·bit linearity
and resolution. It features on·card memory and micro
or mini·computerTTL bus driving capability. The system
contains a 16·channel or differential a·channel multi·
plexer; programmable gain ampl ifier with program
memory loaded by software; sample·and·hold amplifier;
12·bit analog·to·digital converter, TRI·STATE@ TTL
bus drivers; and all timing, control, and interface circuits
necessary for interfacing any micro or mini·computer.
The system operates in a continuous, asynchronous,
sequential scanning mode, updating the self·contained
RAM upon completion of each data conversion. In this
way, latest data for all channels is always resident in
RAM. The system is memory·mapped so it appears to
the computer exactly like main memory. The interface
presents selected channel data to the data bus within
220 ns after data is requested; therefore data is acces·
sible at main memory access speed. The system will
operate with any of the popular computer systems by
. selection of appropriate off·card strap connections.
• 16 single'ended, 16 quasi·differential, or a differential
channels'
• 12·bit resolution and linearity
• 220 ns data access time
• 16 channels of on·card memory
• Memory·mapped interface
• On·card precision gain·set network for gains of 1, 2,
2 1/2, 5, 10,20,50, 100
• Full·scale ranges 0-100 mV to ±10V including 1-5V
• Gain program memory provides any of 4· selected
gains at any of 16 channels
• Internal precision reference divider for calibration at
0.1,1,5,10V
• Internal 10.24V reference
• Drives fully loaded TTL data bus
• Continuous sequential channel scanning
• Supplied with mating card· edge connectors
• Operates with all TTL compatible a·bit or 16·bit
processors.
Functional Block Diagram
ADDRESS
BUS
CONTROL
BUS
DATA
BUS
4·'
ol:
<0
.....
N
.....
U)
C
60 dB '@f= 0-'1
Sel~ct
Memory Read Strobe
kHz,
Gain = 1':"'100
Memory Write Strobe
ACCURACY
Resolution
Quantizing Error
Linearity Error
12 bits
±1/2 LSB
~ ±112 LSB 2SoC
~ ±1 LSB -2SoC to +BSoC
Full Scale Error'
~±112 LSB 2SOC
< ±1 LSB -2SoC to +BSoC
Zero Scale Error'
~±1/2 LSB 2SOC
~ ±1 LSB -2SoC to +BSOC
Power Supply Sensitivity' ~ ±1/2 LSB, Vs = 14-16V,
-2SoC to +BSoC
3 Sigma Noise Peak-Peak' ~ ±1/2 LSB, 0-3 kHz
No Missing Codes'
Amplifier Gain
1, 2, 2.S, S ±O.OS%; 10,
20, SO ±O.l%, 100 ±o..2S%
Memory Ready Signal
NINIT
Referenc~
Divider Ratio
±lSV
SV
2SmA
600mA
PHYSICAL
Dimensions,
Eurocard Version
ADS1216HCE
L Version
, ADS1216HCL
Bus Connector
Eurocard Version
ADS1216HCE
L Version
ADS1216HCL
lo..240±o..01SV @ 2SOC
Hi.24o. ±o..02o.V -2SoC to
+B5°C
10..24:10.00, S.o.O, 1.00
±O.o.S%; 0.100±o..l%
DATA OUTPUT
Staridard TT L Levels
TRI-STATE Bus Drivers
10 Standard,TIL Loads
,'Bus Structure
3 standard TTL loads
1 low power Schottky TTL
load
l'low power Schottky TTL
load
'
1 low-power Schottky TTL
load
Will drive 10 standard TTL
loads
2 standard TTL loads
POWER REQUIREMENTS
REFERENCE
Voltage
,BAO, 2 low power TTL loads
,BA l-BA4, 1 low power TTL
load
, BAs-BA 16, high impedance
with 0.6SV hysteresis
4-bit channel select" 12-bit
card select, or 4-bit channel
select, l·bit byte select, ll-bit
card select
CONTROL SUS
SIGNAL DYNAMICS
Throughput Rate
Natural' binary
Offset bi nary
2's complement binary
220 ns after address and read
signals
Analog Connector
B-bit double byte right-just;fied
or 16-bit single byte right or
left·justified data.
* Amplifier gain = 1
4-2
100 mm W x 160,mm Lx
11.2 mm loaded thickness
_ 4.37S'~ W x 6.70" Lx S/16"
loaded thickness
96 pin, 0.100" ctrs mating
Elco No. B2S7-096-64B-123
Card-edge 72 pin, 0.100"
ctrs, mating Elco No. 6307072-472-0.01
Card-edge 72 pin, 0.100"
ctrs, mating Elco No. 60.420.72-0.00-002 or Continental
No.600-121-72XA
Block Diagram
n
n ~
:;~~~££ _ ! c;
n
~
n
~ ~ ~
~ ~
%
l! ::
:
~
00
=
o
z
~ ;i ~ ~
Co::; c;
<
~
::
<
:;; c;
,.
=
,.
=
~ ~
~
z
o
~
,,1..
m
OUTPUT CODE
GAIN CONTROL
SElECT
16-CHANNEL
ADDRESS
COUNTER
ADDRESS
CLEAR
PRESET
OUT
SELECT
~
w
12·BIT ADDRESS
COMPARATOR
~
~
'---.----"
---~.
ADDRESS SELECT
FROM
ADDRESS
BUS
Timing Diagrams
J
aa
160
~
z
~ ~
~ ==
240
J2D
80
TO DATA BUS
iii
fROM ADDRESS BUS
160
''---
200
400
600
aDo
1000
200
400
~
&00
ADDRESSJ
INPUT
~L -
I
~J~J
'~
.
ADDRESS
INPUT
READ
'U......_--
I I
DUTPUT~
READY
111.7
DATA
OUTPUT
HI·Z
1--- -·1
HI·Z
VALID DATA
Read Cvcle
TI
"'.7
~
WRITE
READY
OUTPUT
DATA
INPUT
~~L FLATA
REQ'O
,
Write Gain Program
Important Note. Always load gain program after power-up and before beginning data acquisition operation.
:lH9 ~~ ~S·a"
Connection Tables
DIGITAl/BUS CONNECTIONS
Pin listing for Eurocard Version. Mating connector for Eurocard Version is Elco No. 8257-096·648·123.
ROWB
5V
5V
5V
17
BA16
LO
T16
2
BIN'
CODE
COMP
18
BA15
LO
T15
LO
T14
ROW A
ROWe
ROWB
POSITION
Rowe
ROWA
1
POSITION
3
VL
VL
READY
19
BA14
4
B08
VL
BOO
20
BA13
5
B09
VL
BOl
21
LO
T13
BA12
LO
T12
I
6
BOlO
VL
B02
22
BAll
LO
Tll
7
BOll
VL
B03
23
BA2
LO
BA3
8
B012
VL
B04
24
BAl
LO
BA4
9
B013
VL
B05
25
BA10
LO
TlO
10
B014
VL
B06
'26
BA9
LO
T9
11
B015
VL
B07
27
BA8
LO
T8
12
READ
VL
TREAD
28
BA7
LO
T7
13
BAO
VL
TO
29
BA6
AORS
T6
14 '
WRITE
VL
TWRITE
30
BA5
NINIT
T5
15
MEMSEL
012
TMEM
31
MUX SEL
8·CH
16·CH
16
NRY
SEL RY
RY
32
GNO
GNO
GNO
.
DIGITAl/BUS CONNECTIONS
Pin listing for L Version. Mating connector for L Version is Elco No. 6307·072-472·001.
POSITION
POSITlO~
POSITION
POSITION
1
5V
19
B013
37
BA16
55
8A9
2
5V
20
B05
38
T16
56
T9
3
CaMP
21
B014
39
BA15
57
BA8
4
5V
22
B06
40
T15
58
T8
5
BIN
23
B015
41
BA14
59
BA7
6
CODE
24
B07
42
T14
60
T7
7
VL
25
READ
43
BA13
61
8A6
8
READY
26
TREAD
44
T13
62
T6
9
B08
27
BAO
45
BA12
63
BA5
10
BOO
28
TO
46
T12
64
T5
AORS
11
B09
29
WRITE
47
BAll
65
12
BOl
30
TWRITE
48
Tll
66
INIT
13
BOlO
31
MEMSEL
49
BA2
67
8·CH
14
BD2
32
TMEM
50
8A3
68
16·CH
15
BOll
33
SEL RY
51
BAl
69
MUX SEL
16
B03
34
012
52
BA4
70
GNO
17
B012'
35
NRY
53
BA10
71
GNO
18
B04
36
RY
54
Tl0
72
GND
ANALOG CONNECTIONS
Mating connector for either format is the Elco No. 6042·072·000·002 or Continental 600·121· 72XA.
POSITION
POSITION
POSITION
POSITION
1
+15V
19
G5
37
MUX 9-16
55
CH 11
2
+15V
20
Vl0
38
AMP HI
56
COM 11
3
-15V
21
G21/2'
39
ANA COM
57
COM 6
4
-15V
22
TP3
40
MUX 1-8
58
CH 6
5
PS COM
23
G2
41
COM 8
59
CH 14
6
PSCOM
24
TP2
42
CH 8
60
COM 14
7
REF. IN
25
G.1
43
CH 16
61
COM 5
8
AOCIN
26
TPl
44
COM 16
62
CH 5
9
REF OUT
27
TPO
45
COM4
63
CH 13
10
OFFSET
28
AMP OUT
,46
CH 4
64
COM 13
11
GlOe
29
ANA GNO
47
CH 12
65
COM 2
12
S&H OUT
30
S&'H IN
48
COM 12
66
CH 2
13
G50
31
A3
49
COM 7
67
CH 10
14
VO.l
32
A4
50
CH 7
68
COM 10
15
G20
33
Al
51
CH 15
69
COM 1
16
Vl
34
A2
52
COM 15
70
CH 1
17
Gl0
35
AMP La
53
COM 3
71
CH 9·
18
V5
36
REF 1
54
CH 3
72
COM 9
4·4
l>
C
Applications Information
CJ)
ANALOG INPUTS
Sixteen pairs of input terminals are provided. Those
marked CH 1 to CH S are multiplexed by an S·channel' ,
multiplexer to MUX l-S. Those marked CH 9 to CH 16
are multiplexed gy another S·channel multiplexer to
MUX 9-16. Sixteen additional terminals, marked
COM 1 to COM 16 are not multiplexed, but are can·
nected to ANA COM. These are normally connected to
the transducer or signal common lines except when
multiplexing differential signals. The card connections
are flexible enough to permit 16·channel single·ended,
16·channel quasi·differential or S·channel differential
connections.
8·Channel Differential Connection
An alternate connection will provide more precise
gain accuracy when a unity gain, single·ended amplifier
is required. The connection ,shown in Figure 5b bypasses
the programmable gain amplifier, but retains a precise,
unity gain, FET input, buffer amplifier. With this can·
nection, it may be necessary to readjust the ADC zero.
Do not change the AMP zero control.
An on·card memory must be loaded with the gain
program for each channel from software control in the
computer program. Gain A 1 is selected by writing
XXX316 into each desired channel at the,selected chan·
nel addresses. Gain A2-A4 are selected by writing
XXX2, XXX1 and XXXO, respectively.
Offset
Connect channel 1 signal high and low inputs to CH 1
and CH 9, respectively. Repeat with channels 2-S high
and low to CH 2-CH Sand CH 10-CH 16, respectively.
Connect MUX l-S to AMP HI and MUX 9-16 to
AMP LO; also connect REF 1 to AMP LO as shown in
Figure
The data out will represent the difference in
signal levels as seen by MUX 1-8 and MUX 9-16;
that is, Vo = CH l-CH 9 and so forth to CH S-CH 16.
Input signals must be somewhere referenced to ANA
GND to insure that the input signals are within the
±10V common·mode voltage range of the system. To set
the multiplexer logic to the differential mode, it is
necessary to strap MUX SEL to S·CH.
When analog input signals range from zero upward or
± from zero, the amplifier should not be offset. Can·
necting REF 1, AMP LO, ANA COM, and ANA GND
provides no, offset. However, when analog input signals
have a fixed minimum value and it is desired to utilize
the entire scale range (e.g., VIN = 1-5V). AMP LO can
be offset by connecting to any of the reference voltages
available from the on·card reference divider. These
voltages are 0.1, 1, 5 and 1OV; they are available at
terminals VO.l, Vl, V5 and Vl0. AMP La can be offset
to one value for gains A2-A4, and REF 1 can be offset
to another value for gain A 1. Perhaps, most common
usage would be with only gain Al' offset, say to lV,
for full scale range of 1-,5V on A1 and zero referenced
signals on the other gain settings. To effect this schedule,
connect AMP La to' ANA GND and connect REF 1
to Vl as shown in Figur~s 4, 6 and 7. The AMP LO
terminal is common for gains selected by A2-A4,
while REF 1 is the equivalent AMP LO termina'l' for
gain A1.
1:
16-Channel Single·Ended Connection
Connect channell signal high through channel Hi signal
high to CH l-CH lS, respectively. Connect channell
signal low through channel 11:/ signal low to COM 1COM 16 as in Figure 2. Interconnect ANA GND, ANA
COM, AMP LO, and REF 1; interconnect MUX l-S,
MUX 9-16 and AMP HI. Also strap MUX SEL to
16-CH.
'
16-Channel Quasi·Differential. Connection
SAMPLE AND HOLD'
Connect all 16 pairs of signal lines as for 16'channel
single-ended connection. Strap ANA COM, AMP LO,
and REF 4 as in Figure 3, interconnect MUX l-S,
MUX 9-16 and AMP HI: Do not connect signals to
ANA GND, however, signals must somewhere be referenced to ANA GND. Also strap MUX SEL to 16·CH.
The sample and hold circuit may be bypassed by can·
necting the AMP OUT and ADC IN terminals directly,
as jn Figure 8. If the'sample and hold circuit is to be
used, strap AMP OUT to S&H IN and strap S&H OUT
to ADO IN, as in Figure 7. 'Since the S&H amplifier
exhibits some offset and a slight ga'in error, both controls
on the ADC for offset and full·scale may need readjustment if the S&H is bypassed. These 2 controls are
factory adjusted for use with the S&H amplifier in the
circuit.
,
AMPLIFIER
Gain,
The amplifier gain may be set ,to any of the following
values on a per:channel. I;lasis; 1, 2, 2 1/2, 5, 10, 20,
50, 100. Up to 4 different gains may be selected for
use with any of the '16 data clJannels., Gain is selected
by strapping the gain select terminals A l-A4, to the
gain set terminals G l-G 100. For example, gain 4
is set to 100 in Figure 4 by strapping A4 to Gl00,
gain 2 is set to unity by strapping A2 to G 1, gain 3
is set to 2 by strapping A3 to G2, and gain 1 is set to
2.5 by strapping Alto G2 1/2. If all channels have
a range of 0-10.2375V, the amplifier need not be used
at all unless desired. In this case, strap AMP, La, AMP
HI and REF 1 to ANA GND; and strap JllJUX1-S,
MUX 9-16, and 5&H IN, thus bypassing the amplifier
as in Figure 5a.
ANALOG·TO·DIGITAL CONVERTER CONNECTIONS
The ADC may be used for either positive unipolar or for
bipolar signals. When bipolar· signals are to be coded,
strap OFFSET to REF IN, strap CODE to COMP and
strap D12 to BDll, as In Figure 8. This offsets the ADC
range so that -10.240V is zero.scale or FS0016 and
10.2375V is full·scale or 07FF16 in a 2's complement
binary code with extended sign bit. If desired to use an
offset binary code on bipolar signals, strap OFFSET to
REF IN, CODE to BIN and D12 to LO, as in Figure 1,.
The result will be 000016 for -10.240V input and'
OFFF16 for 10.2375V input. To obtain extended sign,
strap D12 to BD 11 instead of LO.
4-5
.....
I\)
.....
en
::I:
o
o
:::I:
Applications Information
(Continued)
<0
N
,...
Channel Selection Logic
~
BA4
0
....
C
(Continued)
~
FOR 16-BIT
DATA
BUS
FOR
a·BIT
DATA
BUS
STRAP
FOR 8·BIT
DATA
BUS
BOO to' BOB'
TO
LO
BAO
La
BAl
AORO
AORl
BA2
AORl
AOR2
B03 to BOll
BA3
ADR2
AOR3·
B04 to B012
BA4
AOR3
ADR4
B05 to B013
BA5
AOR4
AOR5
B06 to B014
BA6
AOR5
AOR6
B07 to B015
BA7
AOR6
AOR7
BAB
BAg
AOR7
AORB
AORB
AOR9
VL
AORO
. BOl to BOg
B02 to BOlO
BA10
ADR9
AOR10
Note. See
BAll
ADR10
AORll
Figures 13-16
for examples
BA12
AORll
AOR12
BA13
ADR12
AOR13
BA14
AOR13
AOR14
BA15
AOR14
AOR15
BA16
AOR15
LO
T16
LO or VL
La
T5-T15
La or VL
La or VL
MEMSEL
This input must be true to select the data card; it is
normally connected to a memory select Iine or a mein·
ory/IO line. For positive true select, strap TMEM to
LO. For zero true select, strap TMEM to VL. If there
is no processor line of similar function, MEMSEL is
strapped to READ and TMEM is strapped to WRITE.
This insures that the on·card clock will be interrupted
for the minimum possible period corresponding to
the actual READ time.
an interface latch must be provided to hold the ,address
data during the data transmission period. Using this
card with a PACE system requires OI;ly a single 4·bit
latch to hold address bits applied at BA l-BA4.
.
READY
This input must be true to write a gain program into
the card; it is normally connected to a memory write
control line. For positive true write, strap TWRITE
to LO. For zero true write,strap TWRITE to VL.
The ready output signal jndicates to the processor
that the data card is ready, to accept data in the write
mode or that valid data 'will be on the .bus in the read
mode; it is normally connected to the processor ready or
wait control line. In the read mode, the READY output
will be available by 120 ns after a .. read command is
received by the card; data will be on the bus by 220 ns
after the read command. In the write mode, READY
will be available by 850 ns after the write signal is
received. The processor will not have to enter a wait
.cycle in the read mode; however, a wait cycle is neces·
sary in the write mode due to internal timing require·
ments on the data card. To obtain a positive true
READY signal, strap SEL RY to RY. To obtain a zero
true READY signal, strap SEL RY to NRY.
READ/WRITE
DATA LINES
READ
This input must be true to read data from the card;
it is normally connected to a memory read control
.line. For positive true read, strap TREAD to VL. For
zero true read, strap TR EAD to LO.
WRITE
For use with processors having a single READIWRITE
control line, strap the READ and WRITE lines together
and connect to the processor read/write line. For READ/
WRITE operation, strap both TREAD and TWRITE to
VL. For'READIWRITE operation, strap both TREAD
and TWRITE to YO.
The data card may be used with either 8 or l6·bit data
busses. For 16·bit busses, all 16 data lines ar,e available.
For 8·bit busses, the lower 8 bits must be paralleled with
the .upper 8 bits. Connect BOO to BD8, BDl to BOg,
and'so forth through BD7 to BD15. See under heading
Analog·to·Digital Converter Connections for consid·
eration of bits 12-15. The 12·bit data appears right
justified on a 16·bit data field. For 2's complement
bipolar dat~, the sign bit is extended to the 4 most
significant bits. For binary data, the 4 most significant
bits are zeros. All data. is positive true. By reconnecting
or reassigning data bus terminals, it is possible to- con·
nect for left·'justified data on a 16·bit data bus. Th is
is not possible for an 8·bit data bus. In this case, connect
. the CODE terminal to LO to set the 4 unused 'bits to
zero, per Figure 10.
ADRS
The ADRS line may be used to latch address data
presented to inputs BA5-BA 16. Data is latched on a
rising (trailing) edge and is unlatched on the next falling
edge. There is no latching capability at any other input.
In most applications, the ADRS line is strapped to LO;
and no latching takes place. However, there are some
processors such as the PACE which utilize a single set
of lines for both address and data. In these ~ystems,
4·7
(J)
N
0)
::J:
n
Applications Information
(Continued)
~~-------------l CH 1
@[D
~ICH1
mEI::)-
mr::::>- I
CH 2
I:§I:)-
[§C)
CH 2
CH 1
mr::::>- }
EH 2
I:§I:)-
lE::)-}CH3
I:§I:).
m:r:::::rJ
I:§I:)-
l E : : ) - } CH 4
I:§I:)-
lE::)-JCH4
l E : : ) - } CH 5
lE::)-JCH5
CH J
IT§I:)
~J
'I:§I:)-
CH 3
CH4
mE:)
I:§I:)-
CH 5
mE:)
I:§I:)-
CH 6
lE::)-lcH6
ffi!D
r-
~
I CH 7
@[D
r--r-
lE::)-JCH8
mr:=rI:§I:)-
CH 10
'[§1C)-}
>--
~
~
CH 11
~
~
I1EO
J-
@:2D-}
[§JD--
@ED
~J
CH 12
~
[@!O
I:§I:)-J
mED--
CH 13
~,
~J
CH 14
EEID-
@§:)
CH 10
eH 11
CH 12
eH 13
eH 14
~l
CH 15
~C~115
~
~} CH 16
CH 16
~
~
~
'AMPLO
§]E)
~
I
CH 7
JCH8
~JCH9
I:§I:)-'
~} CH 10
~
~,} eH 11
[F~
~-J Cfl12
~
~l
'
~
CH 13
~J'
@K)-
@JI:)-}
~,'
~J
~
ANA COM
ANA COM
AMP LO
AMP LO
CH 14
CH 15
CH 16
~
ANA GND
REF 1
~
fl.i!I::)-
~
~JCH9
CHa
~ICH6
lE::)-JCH7
I CH 8
@EC)
~
REF 1
REF 1
MUX 1-8
MUX 9-16
AMP HI
8 CH
MUX SEL
*Signals must be
somewhere referenced
MUX SEL
to analog ground.
*Signals must be
somewhere referenced
to analog ground
16 CH
FIGURE 1. 8-Channel Differential Connection
FIGURE 2. 16·Channel
Single-Ended Connection
4,8
FIGURE 3. 16,Channel
Quasi-Differential Connection
Applications Information
A4
l>
C
(Continued)
(/)
~
A2
A3
l-
AI
~
c:::=>
GIOO
.....
.....
N
ffiI:::)- }C~ 1
r
-
0)
l:
n'
ffiI:::)- ] CH 2
-
~
ffiI:::)- }CH 3
~
r
~
ffiI:::)-} CH4
mE::)-'
me:)
@C:)
IE:::)
ffiI:::)- JCH 5:
~
G2112
J--
G2
>--
ffiI:::)- }CH 6
m:E:)-
Gl
lEC>-}CH7
~
ffiI:::)-] CH 8
m:E:)-
IEC:>-]CH9
@EC)-
IE:)-]
mE)[EIC}-}
.
A4
A2
A3
A1
Gain
Gain
Gain
Gain
= 100
= 1
Range = 0-102.375 mV
Range = 0-1 0.2375V
=2
Range = 0-5.11875V
= 2 1/2 Range = 1-5.095V
'1
1
1
1
.~
LSB=25I'V
LSB =.2.5 mV
LSB = 1.25 mV
LSB.= 1 mV
mEIC>-
[EIC}-}
mEIC>IE:)-}
mEIC>-
MUX HI
MUX 1-8
MUX9-16
AMPHI
AMP HI
AMPlO
AMP LD
REF 1
REF j
~
s&HIN
I1ill::::)- }
mE)-
IE:)-}
~
~
~
ANAGND
ANA GND
ADC IN
ADCIN
~H
15
.
.
CH16
ANA GND
REF 1
MUX 1-6
MUXD-16
AMP HI
OFFSET
VI
REF IN
MUXSEl
REF OUT
16CH
FIGURE 5a. Amplifier
Completely Bypassed
CH 14
AMPlO
~.
SIlo H OUT
CH 13
ANA COM
me:::>-,
SIIoHOUT
CH 11
I1ill::::)- } CH12
FIGURE 4. Gain and Offset Connections, An. Example
(See Page 5)
MUX9-16
CH 10
FIGURE 5b. Amplifier Bypassed
Except for Single-Ended,Precise
Unity-Gain FET Buffer
4-9
FIGURE 6. 16-Channel Single Ended Con·
nection, One or More Channels Offset 1V as
with VIN =1-5V
U
::I:
,...
Applications Information
(Continued)
to
N
.,...
REF 1
en
VD.l
-
mc::::>
mc:>.
rE::::>
,,',
. ,!
REF IN
REF OUT
m::=:>
G21/2
G2
FIGURE 8. Sample and Hold Bypassed
r-r---
FIGURE 9. Normal MUX, AMP, S & Hand
ADC Interconnections
LGI
S & H OUT
I ANA COM)
lANA GND )
CH 13
ADCIN
CH 14
OFFSET
CH 15
REF IN
CH 16
REF OUT
c::::J
I:!iL:)
MUX 1-8
MUX9-16
~
.j
COMP.
AMP HI
.
.C:::)
AMP OUT
i
~,
t,":
UHIN
1
UHDUT
ADC IN
OFFSET
~
~
(+)
, .H
EXT.l0.240V
: R~F
Ch 13 = OV REF
Ch 14 = 5V REF
Ch 15 = 1V REF
Ch16=100mVREF
A4
A2
A3
Al
Gain =.100 ~ange = 0-102.375 mV
Gain = 1
Range = 0-10.2375V
Gain = 2 .:.. Range = 0-5.11B75V
Gain-=2'1!2 Range=1-5.095V
FIGURE 10. ADC, CODE and Logic Connections for Bipolar Inputs with Internal REF;
2's Complement Binary Output Code Data is '
Right-Justified, Extended.Sign_ For LeftJustified Data, Connect 0.12 to LO Rather
than to BD11, and Reassign Bits 12-15 as
Bits 0-3. ThiS is applicable Only to 16-Bit
Data Bus Op~rations_ ..
1
1
1
1
LSB
LSB
LSB
LSB
= 251lV
= 2.5 mV
= 1.25 mV .
= 1 mV
FIGURE'7;,Example of'Arialog'Conllection:with Multiplexed Reference
Voltages for'CalibrationJ;!urposes (Consider'Accuracy of Internal REF'
If Used)
'
•. : .
4-10
Applications Information
»
c
(Continued)
en
.....
I\)
.....
E:::J-,
0')
~AOffO
(')
~
H}
REf IN
J:
~ADRl
EXTERNAL
1U.240V
REf
~ADf\2
~ADR3
1+)
.IE::)-- ADA 4
FIGURE 11. ADC, CODE and Logic Connections for Bipolar Inputs with External
REF; Offset Binary Output Code Data is
Right-Justified, Bits 12-15 are.Zeros. For
Left-Justified Data on a 16-Bit Data Bus,
Reassign Data Bits 12-15 as Bits 0-3.
~
~
~ADR5
c=EJ
~A1fR7
XACK~
~ADR8
DATO~
~ADR9
~ADR6
'-c:Jill
~ADRA,
OATI~
~ADRB
~ADR'c
'-c:Jill
DAT2~
~ADAD
~
~ADRE
DAT3~
~ADRF,
~
DAT4~
~
S & H OUT
IANA COM)
~
DAT5~
~
DAT6~
~
DAT7~
~
VL
TREAD
TMEM
TWRITE
TD
T16
~}
I
I
I '
E!:::)-
TOLODRVLAS
APPROPRIATE TO
SElECT MEMORY
PAGE lOCATlOrJ
.
c::::)
~
~
MEMWAITE
~1Nff
~
FIGURE 13. Bus and LagicConnections far
80/10 System
FIGURE 12. ADC, CODE and Logic Connections for Unipolar Inputs with Internal REF;
Binary Output Code Data is Right-Justified,
Bits 12-15 are Zeros. .
4-11
o::I:
CO
Applications Information
(Continued)
C'
.....i
U)
C
] .
I,'
I
1
LATCHED OR
NoN·LATCHEo
ADDRESS BITS
~BAI3
DID - - c : : J E ]
lTMEM
LATCHED
ADDRESS
BITS
IEL::)-OA6
-c:::::!§]
DO
}
IEL::)-BA5
I:E::)-BA7
~A12
oAT4~
*
IEL::)-BA4
EXTEND~
oAT2~'
oAT3~
NBAoS
mc:::>-AI
c:::EEJ
l...C::EI
I
BAO
mc::>-Ao
TO LoORVLAS
APPROPRIATE TO
SELECT MEMORY
PAGE LOCATION
~
~VMA
READ
RIW
WRITE
~NINIT
*To LO when all address bits are latched on the CPU card
FIGURE 14. Bus and Logic Connections for
FIGURE 15. Bus and Logic Connections for PACE
6800 System
4-12
Applications Information
(Continued)
~
ImC)-I
~BAO
~
lE:::)-BAI
rCJEm
Lc:::m
lE:::)-BAZ
lE:::)-BA3
MEMRDY~'
lE:::)-BA4
BDO~
~BA5
LCEJ
lE:::)-BA6
BDI~
lE:::)-BA7
LCEJ
lE:::)-BA8
BD2~
lE:::)-BA9
~
ffiIC:)-- BAlD
ffiIC:)-- BAIl
ffiIC:)-- BAI2
ffiIC:)-- BAI3
ffiE::)-- 8AI4
BD3~'
Lc:::!2ill
BD4~
Lc:::!2ill
~DAI5
BD5~
Lc:::!2ill
DAI6
BD6~
ILO
Lc:::!2ill
VL
BD7~
1-~
}-!-
TMEM
Lc:::!2ill
ITREAD
TWRITE
l----4
~
ITO
~
Tl6
GND]
~
GL:>}
RAMSEL
I
I
I
TO LO DR VL AS
APPROPRIATE TO
SELECT MEMORY
PAGE LOCATION
G::::>-
.
MEMSEL
I READ
WRITE
DWDS
~,INIT
FIGURE 16. Bus and Logic Connections for SC/MP CPU with External RAM
4·13
o
::t
Physical Dimensions
inches (millimeters)
.(0
N
,....
en
c
100'0.38mm~
.
J
C
Note. See LF13300 data sheet for additional information.
4 t/2-Digit Panel Meter Controller
;;
CLOCK
CAPACITOR
~
Z
Q
...l§
i
Z
Q
~
I~
i
Q
~
~
~
::;
6
START AID
CONVERSION (SAD)
1
FEED'ACK
2000 OffSET CORRECTION 11)
1600 UNDERRANGE
~g~NTS
5
FUNCTIONS
COMPARATOR
,INPUT/en
Z010 POLARITY DETERMINATION
PROGRAM
~-----;::-O RESISTOR
RVec
BINARY TO 1-8EGMENT
DECODER
DP
MPI
DECIMAL POINT
DECODER
10-
DPI
5-1
OP2
!2B
Vee
.!14
GND
,..
,..
it)
~
m
c
. liN = ·-12 rnA
V
OUTPUTS - (EXCEPT SEGMENTS & DIGITS)
VOH
Logic .",. Output Voltage
Vee= Min, lOUT = -400/lA
IOH
Logic" 1" Output Current
Vec= Min
lOS
Output Short-Circuit' Current
Vce = Ma~, VOUT = OV
,V
2.4
-18
-400
/lA
-55
mA
(Not. 51
VOL
Logic "0': Output Voltage
Vec ;Min. 10tJT = 4 mA
0.4
V
ICC
Supply Current
Veel = M~x. Pin 28
90
rnA
ICC2·0N
Supply Current
VeC2 = Max. All Segments ON.'
Pin 26
600
mA
leC2.0.FF
Supply Curren.t
Vee = Ma~. All Segm,nts OFF.
Pin 26 (@ Pin 27 = 6vI
1
;
,
mA
SEGMENT OUTPUTS
IOL3
Low Level Outp;ut Current
Vee = Max. VOUT = 1.0V
IOH3·
High Level Output Current
Vee = Max. RpROG ~ 7.2k,
(Note 6)
-50 ..
VOH3
High-'Leve!'Output Voltage
Vee = Max. lOUT = -75 mA
2.7
RVee
Supply Pin
Vee = Min, IceR = 600 rnA.
'-100
/lA
-:-75
rnA
V
V
3.2
VOL!T= 2.7V
DIGIT OUTPUTS
VOl4
Low Level Output Voltage
Vee = Min, IOl = 0 /lA
IOH4
High Level Output Current
Vec = Min, VOUT = IV
V
0.2 ..
mA
,
CLOCK
fc
Clock Frequency
R = 80k to 200k. C = 50 pF to 200 pF
30
fMUX
Multiplex Frequency
1I320th of Clock Frequency
94
300
940
kHz
:
Hz
Note 1: HAbsolute Maximum Ratings" are those values beyond which the safetY of the device can'not be.. guaranteed. Except for" "Operating
Temperature Range" they are not meant to imply that the" devices should be operated at these limits. The table of "Electrical Characteristics"
~.~
provides conditions for actual device operation.
Note 2: .VeC2 supply ts conn~cted to RVec pin on'package through a protection reiistor, which dissipates power external to the package, accord·
.
. ,
ing to the graph (Figure 31.
Note 3: Unless otherwise specified, minImax (imits apply across the oOe to +70o e range fo~ the device. All typica(s are given for Vee = SV and
TA=25°e.
. . .
.
Note 4: All currents into device pins shown as positive, out of device as negative, all voltages 'referenced 'to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 5: Only one output at a time should be shorted.
Note, 6: The cu rrent/segment specified is peak current for a 5-digit multiplexed system, which works out to be 15 rnA/segment average DC current.
5-2
Functional Description
o.PERATION
value was determ ined during Phase I. The output re'gister,
will hold the data until a new conversion is completed
and new data is loaded into th~ register. "EEEE" will be
displayed in case of overrange.
The AD134511 is designed for use with the LF13300
dual slope DVM analog front end. Four control signals
are supplied to the LF13300 and one control signal is
required from the LF13300. The conversion cycle is
composed of 5 distinct phases (Figure 4):
Phase V Phase
Phase
Phase
Phase
Phase
I - Polarity Determination
II - Initialization
III - Ramp Unknown
IV - Ramp Reference
V ....: Offset C,?rrection a'nd Standby
Offset Correction (2000 Clock Periods)
The LF13300 requires this phase to correct any intrinsic
offset voltage errors prior to the polarity detect phase.
The end of conversion (EOC) goes to logic "1" after
this cycle and the system goes into the Standby mode.
Phase I - Polarity Determination (2,010 Clock Periods)
Offset Correction (OC) output remains at logic "1"
after OEC, thus the system is continuously corrected
during the Standby mode.
This phase is initiated by taking the start AID conversion
(SAD) input to a logic "1" momentarily (;? 1 CP). It is
used to determine polarity of the analog input. At the
2000th clock period, CaMP from the LF13300 is
examined for polarity. If CaMP = logic "1", then the
input voltage is positive. If CaMP = logic "0", then the
input is negative. The polarity determination ~ignal
(PD/RU+) will.be at a logic "1" during this entire phase.
The above operation is also necessary to determine
which integrator input (positive or negative) of the
LF 13300 should be used for proper AID conversion (see
LF13300 data. sheet).
Clock Generator: The ADB4511 has an 'on-chi~ clock
generator whose frequency 'is adjustable by external
ROSC and Case components. An external clock could
be used with COSC as the clock input.
Counters: The ADB4511 has four -':10 counters and one
72 counter for a cou,rlt of 20,000 clock pulses. The
counters advance at the negative-going clock edge.
Phase II :- Initialization (4000 Clock Periods)
Decimal Point: The decimal point output is a constant
current source. Decimal point inputs 1 and 2 are decoded
to ,drive either of the 4 positions MSD, SSD, ThSQ, FSD
(most, second, third and fourth significant digits). The
decimal point inputs are CMOS and TTL compatible.
This phase is identical to Phase V and is used by the
LF13300 to eliminate any offsets induced as a result of
the Polarity Detect Phase. Offset Correction (OC) will
be ata logic "1". , - ,
,
Digit Drivers: The digit drive buffers are multiplexed
emitter follower outputs. _The, modulo 5, multiplex
counter is triggered by the positive-going clock edge,
making.the multiplex rate 1/320 of the cl,ock frequency.
One-eighth of each digit ON interval is blanked, to
avoid ghosting.
Phase 11'1 ....: Ramp Unknown (20,000 Clock Periods)
The unknown input voltage is integrated for a fixed
time, 20,000 clock periods, during this phase. The result
of, the Phase I Polarity Detect Cycle determines whether
PD/RU+ or RU- will be at logic "1". If Phase I indicates
a positive input, the PD/RU+ signal will be a logic "1".
If Phase I indicates a negative output, Ramp Negative
(RU-) will be a I,ogic "1 ". These 2 signals will never be
at, logic "1" simultaneously.
Phase IV - Ramp Reference
Segment Outputs: The 7-segment outputs are multi,plexed in a similar fashion to the digit outputs. These
clutputs are constant current sources, and are programmable with one external resistor, Rp. (Figure 2). The
most significant digit (+1) is also decoded to be displayed
with the same 7-segment outputs.
This phase is a variable length phase depending on the
magnitude of the ana'iog input voltage. 'During this time,
Ramp Reference (RR) will be in the logic "1" state.
When CaMP goes to a logic "0" state, or when the
internal counter reaches 100% of full-scale (20,000
periods), the Ramp Reference (RR) signal goes to the
logic "0" state and the counter output is loaded into the
output register. The Polarity Bit will reflect whatever
Power Supply: Only one supply is required' for the
system. Two supply pins are provided on the chip in
order to make the interface between the digital and
analog chip noise-free and to lower the power dissipation'
on-chip. RVCC is connected to the output segment
source drivers through an external resistor. REX, to
reduce on-chip power dissipation (Figure 3).
5-3
;:
it)
~
Typical Performance Characteristics
to
C
I
·f ...
REF V
,7
I~
"'-/ I VREF
21
24
119 120 122 123
3
COMPOUT
PD/RU+
2M~
RUOP AMP OUTPUT
DC
tt
1
"~
2 NSB5415
4
L...!!I
RR
117
Dl
D2
D3
3
4
D4
D5
0>
END DF CONY
Il--
START AID CDNV
~
§:
AOS4511
RCLK
OFFSET CORRECTION
2
1
,..,.*
Rp
0C2
10pF
P10C3
DIGITAL
GND
p-
~
5V
r
o·~
Rp
27
DP 1
11
o
3
o·~
,.:J:.
1£
8
RAMP REFERENCE
RVCC
J.!..-..,
R*
,
CCLKr-DP2
10
'"
r
"w
w
o
o
c.
3.0k
O'lPF
o·
;;l'
RAMP NEGATIVE UNKNOWN
VCC
"2!.
'C
"2-
POLARITY DETERMINATIONI
RAMP POSITIVE UNKNOWN
GND
o·~
rll
15 112 114 13
16 12 15 13
8
COMPIN
W
r t;:r
8
H~OCl
[
,13
5
~
5
0:D'ir;4'
pF
OP AMP INPUT
0.1 pF
LOW LEAKAGE
TANTALUM
CAPACITOR
I 25 118
OP
BUFFER OUTPUT
~ r1
t tt
0>
15
r<>"'i
'::J
C.
LF13300
..t::i
16
DS8870
I ~ r1
j~m..."
3P4T
SWITCH
c:;'
a
c)'
T I~ I~/./~/./~. '/~
-,-
1
'"
"0
"0
I I l-I'l-I l-I l-I
171 Vx
0.9M,
U1
!.
DIGITS
-15 V
1
POWER
GND
c:;'
1~ 15'1.
~
C,*....I.-·
-,-
'"'"
'"
;.
:T
>
• 10k
*See Figures 1, 2 and 3 for values
~~Sl7Ba"
,...
,...
It)
~
Connection and .schematic Diagrams.
-,
m
c
«
.
.
Dual-In-Line Package
SEGMENT OUTPUTS
DIGIT OUTPUTS
,...---~-----
Decimal Point Addressing
,
DP 1
DP2
0
1
0
1
0
"
0
1
. - ,.1
15
DIGIT
POSITION
D4,FSO
03, ThSO'
ADB45t1
02, ssb
01,MSO
11
RR
DC
POJ
RU-
CI,
.sAD~
EDe CClK ReLK
2
1
",~
RUt
TOP VI,EW
3
5
14
GND
'--v--'
• Dp:
lNPuTS
DIGIT
OUTPUTS
Order Number ADB4511N
See NS Package N28A
SeglT!ent Outputs
"
,
. Inputs
Decimal Point (DP)
Start A/D.(SAD) .) .. '"
Comparator (Ci)
, - - - - - -.....--0
Vee; .
Digit Outputs
Veet
. Control Outputs
Segment Identification.
End of Conversion (EOC)
Ramp Unknown (RU)
Ramp Reference (RR)
Polarity Determination (PO)
. Offset Correction (OC)
5-6
DIGIT OUT
Digital Voltmeters
~National
~ Semiconductor
>
C
C
CtJ
en
o
ADD3501 31/2 Digit DVM with Multiplexed 7·Segmerit
Output
general description
features
The ADD3501 (MM74C935-1) monolithic DVM circuit
is manufactured using standard complementary MOS
(CMOS) technology_ A pulse modulation analog-todigital conversion 'technique is used and requires no
external precision components. In addition, this technique allows the use of a reference voltage that is the
same polarity as, the input voltage_
• Operates from single 5 V supply
• Converts O\( to ±1.999V
• Multiplexed 7-segment
•
Drives segments directly
• No external precision component necessary
• Accuracy specified over temperature
One 5 V (TTL) power supply is required. Operating with
an isolated supply allows the conversion of positive' as
well as negative voltages. The, sign of the input voltage
is automatically determined and output on the sign pin.
If the power supply is not isolated, only one polarity of
voltage may be converted.
• Medium speed - 200ms/conversion
The conversion rate is'set by an internal oscillator. The
frequency of the oscillator can be set by an external RG
network or the oscillator can be driven from an external
frequency source. When using the external RC network,
a square wave output is available. It is important to note
that great care has been taken to synchronize digit
multiplexing with the AID conversion timing to eliminate noise due to power supply transients.
•
• I nternal clocl~ set with
externally
.
• Overrange indicated by +OF L or -OF L display reading
and 0 F LO output
The ADD3501 has been designed to drive 7-segment
multiplexed LED displays directly with the aid of
external digit buffers and segment resistors_ Under
condition of overrange, the overflow output will go high
and the display will read +OF L or -OF L, depending on
whether the input voltage is positive or negative_ In
addition to this, the most 'significant digit is blanked
when zero.
Analog inputs in applications
±200 Volts
show~
can withstand
applications
•
Low cost digital power supply readouts
•
Low cost digital multimeters
•
Low cost digital panel meters
•
Eliminate analog multiplexing by using remote AID
converters
• Convert analog transducers (temperature, pressure,
displacement, etc.) to digital transducers
A, start conversion input and a conversion complete
output are included on all 4 versions of this product.
connection diagram
RC network or driven
(Top View)
Duai-in-Line Package
VCC- 1
2Br- S,
ANALOG VCC- 2·
Sd- 3
27r- St
r- S,
24 r- OI,GIT 1 IMSOI
26
S,- 4
25 r - GND
Sb- 5
S,- 6
23 r - OIGIT 2
OHO -
7
CONVERSION COMPLETE -
B
21 r - DIGIT 4 {LSDI
START CONVERSION _
SIGN _
9
20 f-'tOUT
10
19f- t 'N
lB r - vREF
ADD3501
VFlLTER 11
vINH_ 12
VINI+I_ 13
22 r - DIGIT 3
17f-SWI
16f-SW2
VFB- 14
15 f - ANALOG GND
Order Number ADD3501CCN
See NS Package N2BA
5-7
..I.
o
,~
o
o
«
absolute maximum rating
(Note 1)
Voltage at Any Pin
-0.3V to Vee + 0.3V
-40·C to +85°C
800mW
Operating Temperature Range (TA)
Package Dissipation at T A = 25~C
derate at () JAIMAXl = 125°C/Watt above T A = 25~.C
Operating Vee Rang~'.
Absolute Maximum Vee
Lead Temperature (Soldering, 10 secqnds)
Storage Temperature Range
electrical characteristics
4.5V to 6.0V
6.5V
300·C
_65°C to +150·C
4.75V';; Vee ';;·5.25V, -40°C';; T A
';;
+85°C, unless otherwise specified ..
ADD3501
PARAMETER
CONDITIONS
V IN(1 )
Logical "1" Input Voltage
VINIO)
Logical "0" I nput Voltage
VOUTIO)
Logical "0" Output Voltage
(All Digital Outputs except
Digit Outputs)
10 .=1.1 mA.
VOUTIO)
Logical "0" Output Voltage
(Digit Outputs)
10
VOUTI11
Logical "1" Output Voltage
(All Segment Outputs)
10 =50 mA @ T J = 25°C Vcc= 5V ' V ee :-l.6
10=30mA@Tj=100°C
V ee -l.6
VOUTI1)
Logical "1" Output Voltage
(All Digital Outputs except
Segment Outputs)
10 = 500pA (Digit Ou~puts)
10 = 360pA (Conv. Complete,
+1-, Oflo Outputs)
Vee -0.4
V OUT = 1.0V
2.0
IsouReE Output. Source Current
(Digit Outputs)
= 0.7 mA
IINIOl
Logical "0" I nput Current
(Start Conversion)
VIN = OV
Supply Current
Segments and Digits Open
fe
Conversion Rate
V
0.4
V
V
V
Vee - 1.3
Vce - 1.3
V
"
1.0
-1.0
10
640
f 1N /64,512
f MUX
Digit Mux Rate
tBLANK
Inter Digit Blanking Time
tsepw
Start Conversion Pulse Width
mA
kHz
convjsec
Hz
f 1N /256
i/(32fMux )
200
pA
kHz
0.6/RC
100
mA
pA
:
,
0.5
Oscillator Frequency
Clock Frequency
V
0.4
'.
VIN = 1.5V
fiN
V
1.5
"
Logical "l"lnput Current
(Start Conversion)
"
UNITS
,MAX
Vee -1.5 ..
IINI1)
Icc
.TVP (2)'
MIN
sec
DC
ns
Note 1: "Absolute Maximum Ratings" are th~se values beyond which the safety of the device cannot be guaranteed. Except far "Operating
Range" they are not meant to imply that the devices ~hould be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Nota 2: All typicals given for T A
= 2SoC.
5·8
electrical characteristics
ADD3501
1:c = 5 conversions/second, O°C .;;; T A .;;; 70°C, unless otherwise specified.
Non·Linearity
V ,N = 0- 2V Full Scale
V IN = 0 - 200mV Full Scale
-0.05
Qu.antization Error
-1
Offset Error, V,N = 0\1
-0.5
Rollover Error
-0
Analog I nput Current
(V ,N +, V ,N -)
TA = 25°C
+0.05
±0.025
% of
, full scale
+0'
-5
+1.5
±0.5
counts
+3
mV
+0
counts
+5
nA
block diagram
314·DlGIT
LATCH
,..--
~
Al_
• , -'+
ClQl.2.2-
-
START CONY
.3-
FRED OUT
16:4
MUX
I----
SEGMENT
DECODER
DJ-
A4_ I---'B4C4_
DIGITAL TIMING
AND CONTROL
.'
-
o
----
'-Ld :::
.....
~
~.
::
'OJ
COMPARATOR
TIMING
-
H>oH>o-
.:.-.-f-t>o-
~
102
+
...
~
->---
..--'--,
OVERflOW
ROM
~7
GNO ~vss
DIGIT 1 (MSDI
0lGIT2
DIGITJ
DIGIT 4 (LSD)
I--
SIGN
-
ANALOG Vee
C
r --~
1
~
I ::: I
-VIN
S,
OVERflOW
CONY COMPLETE
100
+VIN
S,
rr---
DIGITAL Vee
VFllTER
Sd
H>~ S,
MSD
101
104
DIGIT BLANK
S•
S,
~
......
RDM
7
B3CJ-
-
H>o-t>o-
I----
C2D2-
\
FREQIN
LSD
~
+
ttl:
0
........
,..-S:(0
-
~
0
L_":.J
ADD3501 3l!i·Digit DVM Block Diagram
5·9
VREF
SWI
SW2
ANALOG GND
»
c
cCN
U'I
9
oan
C")
C
c
«
theorY of operation'
A schematic for the analog loop. is shown in figure 1.
. The output of SW1 is eitHer at V REF or 'zero volts,
depending on the state of the D flip-flop. If a is at a
high level VOUT = V REF and if a is at a low level VOUT
= OV. This voltage is then applied to. the low pass filter
comprised of R1'an'd Cl. The ou~put of this filter, V FB ,
is connected to the negative input of the comparator,
where it is compared to the analog input voltage, V IN'
The output of the comparator is connected to the D
input of the D flip-flop. Information is then transferred
from the D input fo the a and a outputs on the positive
edge of clock. This loop forms an oscillator whose duty
cycle is precisely related to the analog input voltage. V IN'
The lowpass filter will pass the DC value and thel'):
V FB
!'
V REF (duty cycle)
Since the closed loop system will always force V FB to
eq4al V IN , we can then say that:
V REF (dutx cycle)
or
An example will demonstrate this relationship. Assume
the input voltage is equal to 0.500 V. If the a output of
the D flip-flop is high ·then V OUT will equal V REF
(2.000V) and V FB will charge toward 2V with a time
constant equal to RIC:'. At some time ,V FB will exceed
0.500V and the comparator output will switch to OV.
At the next clock rising edge the a output of the D flipflop will switch to ground, causing VOUT to switch to
OV. At this time "FB will start discharging tollllard OV
with a time constant RIC~, When VF:B is less than 0.5V
the comparator output will switch high. On the rising
edge of the next clock the a output of the D flip-flop
will switch high and the process will repeat. There exists
at the output of'SWl a 'square wave pulse train' with
positive amplitude' V REF ' and negative amplitude OV.
The duty cycle is logically ANDed with the input
frequency fiN' The resultant frequency f. equals: .'
f = (duty cycle) x (clock)
Frequency f is accumulated by counter no. 1 for a time
'determined by counter no. 2. The count contained in
counter no. 1 is then:
(count) =
(clock)/N
(duty cycle) x (clock)
(clock)/N
The DC value of this pulse train is:.
VOUT
.
TON
- - )' = VREF(dutycycle)
TON + TOFF ..
= V REF (
For the ADD3501, N = 2000.
schematic diagram
VjN
RESET
VIN
I
=
VFB
=
VREF x (duty cycle)
= (duty cycle) x liN
Count in Counter No.1 = _1_ = (duty cycle) x liN = ~ x N
liNIN
liNIN
VREF
Figura 1. Analog Loop Schematic
Pulse Modulation AID Converter
5·10
~
general information
The timing diagram, shown in figure 2, gives operation
for the free running mode. Free running operation is
obtained by connecting the Start Conversion input to
logic "I" (Veel. In this mode the analog input is con·
tinuously converted and the display is updated at a rate
equal to 64,512 x l/f lN .
Internally the ADD3501 is always continuously converting the analog voltage present at its inputs. The Start
Conversion input is used to control the transfer of information from the internal counter to the display latCh.,
The rising edge of the Conversion Complete output
indicates that new information has been transferred
from the internal counter to the displ~y latch. This
information will remain in the display latch until the
next low-to-high transition of the Conversion Complete
output. A logic "I" will be maintained on the Conversion
Complete output for a time equal to 64 x l/f lN .
An RS latch on the Start Conversion input allows a
broad range of .input pulse widths to be used on this
signal. As shown in figure 3, the Conversion Complete
output goes to a logic "0" on the rising edge of the
Start Conversion pulse and goes to a logic "I" some time
later when the new conversion is transferred from the
internal counter to the display latch. Since the Start
Conversion pulse can occur at any time during the
conversion cycle, ,the amount ot'time from Start Conversion to Conversion Complete will vary. The maximum
time is 64,512 x llflN and the minimum time is
256 x llf lN .
Figure 3 gives the operation using the Start Conversion
input. It is important to note that the Start Conversion
input and Conversion Complete output do not influence
the actual analog-to-digital conversion in any way.
timing waveforms
fiN
.nIl>----------
CONVERSION CYCLE
(INTERNAL SIGNAL)
r:
1-1.-.....,.--------
1.---------
64,512 x l/flN
64,000 x 1/fIN
I
~
----,.---.~
i
r-L....-I .
64,256
x l/flN -------;-~I-t I
,
r-- 64/flN
+-'n____
I
CONVERSION _'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
COMPLETE
r
. NEW
CONVERSION
CONVERSION
ENOS
I
STArTS
Figure 2. Conversion Cycle Timing Diagram for Free Running Operation
5-11
C
C
w
..
CJ1
o
,...
oIt)
(W)
c
C
IV
i
rr r9
1
2V RE'ERENCE
RI
10k
.1"'
1
R2
lO I ~'IN91'
Tvvoe
l -f- .
I
POWER GNO
L-.
~_
~
\~~
1
±1%1I
1
1k
I
IL ____
22MU
1
1
1
1
!.
A
..!~
~
200nf,~3
J,s
16
0"
-
zz
g~
~
25~t~
I
1.Sk
17
!l
19
" i
<
~
21
20
~
'"c;
:::;
Vss
I. ~
1.
L
'"c;
:::;
23
'":::;c;
25
24
'"
c;
:::;
A
t6
=
0
z
'"
- .
21
12.
lOOk
__ .J
ADD35D1
OFFSET
ADJUST 151
SIGNAL
;
GNO
=~.41
Tr'131
/
'---
r
r -;::--:k- ~
I
~
r
I
---'
~
w
I
'.T.
1
0575492
.,%1
i f~~'M33 ~9-j+
f
I
I
I ~R'20u: I
0.1"'
T/_7.
I -! 1/_7/_7
I
Ir'.------------,.
Lff3~0-5!
3DDmA
43
..----
114
-=
2
:£
113
<
2
I
112
<
!:j
~
c;
z
-+
11
10
,,!!l
0>,.
z'"
e ...
9
~0.41"F
"'",.
5~
me
,.
1:;
/!
'"
'"
11
.
6
g
~
5
n
~
4
P
g g
2
JI
(31
lOOk
+ IOIlF
10VDt
VIN
OVTO
+1.999 V
NOTES:
1. All RESISTORS %WATT:t 5% UNLESS OTHERWISE
SPECIFIED.
4 . ...!!!.!!.L
Rl + RZ -- R3:t 25n
2. ALL CAPACITORS ±10%.
3. lOW LEAKAGE CAPACITOR REQUIRED.
Figure 4. 3%·Digit DPM, +1.999 Volts Full Scale
~os£aa"
ADD3501
'!'
-"
. ADD3501
GUARD
11k
U
51k
v(.}
NOTES,
OV TO! 1.999V
V(-~
1: All RESISTORS'!. WATT ~ 5% UNLESS OTHER\~ISE
SPECIFIED.
4. J!!!!L
2. All CAPACITORS '111%
Al+R2
J. LOW LEAKAGE CAPACITOR REQUIRED
Figure 5. 3%-Oigit DPM. ± 1.999 Volts Full Scale
:0
R ± 25~1
3
'f'
c
B.
DIGITAL TIMING
f---
C. f---
AND CONTROL
s,
s.
... "
0 - - - . Sd
~~.
A4 _
FREQIN~
,.
.ho.
......
B3-
...
..... _ _ Sf
I-~",,>.
MSO
f'-r.....I""T...
""=1--1~.>o-"'" s,
I
10·1-----t--=-......
ti-tI-IHI-r)~b
.....--..
1031-----t--11rt"ttTtri:::.'1~·~t>c-I
1021----..,...---H...-+-+-H-++f'i:::.'-''''-::::
IO,I-----+---H-+-+-+-H-++f'~-~,. ....-:. . .
r---,-_
FREoour _____
O,.,T tlMSO}
DIGI12
O,.,T
3
OIGIT4(LSO}
DIGIT BLANK.
COMPARATOR
TIN!ING
~
GNO...-VSS
r--
y-
OVERFLOW
ROM
OVERflOW
CONY COMPLETE
. DIGITAL VCC - - - - ( 1 - - + - - - - - +
SIGN
!DO
-+
ANALOG VCC_---(I--+_ _ _ _
VFlLTER
---1--+---,
J --1
1
~r---------------------~
~
~-i."':-n-l~
f ~ ~I-------------------(I~
+VIN
--+
-VIN
-~-+-I_l:+rl_-....
L __ ...J
+--....-----------------------............- . .
VFB _ - - -_ _ _ _...1
ADD3701 3%-Digit DVM Block Diagram
S-18
VREF
SW,
SW2
ANALOG GND
Theory of Operation
A schematic 'for the analog loop is shown in figure 1.
The output of SW1 is either at V REF or zero volts,
depending on the state of the D flip·flop. If Q is at a
high level, VOUT = V REF and if Q is at a low level VOUT
= 0 V. This voltage is then applied to the low pass filter
comprised of R 1 and C1. The output of this filter, V FS,
is connected to the negative input of the comparator,
where it is compared to the analog input voltage, V ,N .
The output of the comparator is connected to the D
input of the D flip·flop. Information is then transferred
from the D input to the Q and Q outputs on the positive
edge of clock. This loop forms an oscillator whose duty
cycle is precisely related to the analog input voltage, V IN'
The lowpass. filter will pass the DC value and then:
V FS = V REF (duty.cycle)
.
Since the closed loop system will always force V FS to
equal V ,N , we can then say that:
V ,N = VFS = V REF (duty cycle)
or,
V ,N
..
- - = (duty cycle)
V REF
An example will demonstrate this relationship. Assume
the input voltage is equal to 0.500 V. If the Q output of
the D flip·flop is high then V OUT will equal V REF
(2.000 V) and V FS will charge toward 2 V with a time
constant equal to R,C,. At some time V FS will exceed
0.500 V and the comparator output will switch to 0 V.
At the next clock rising edge the Q output of the D flip·
flop will switch to ground, causing V OUT to switch to
0,\1. At this time V FS will start discharging toward 0 V
wi'th a time constant R, C,. When V FS is less than 0.5 V
the comparator output will switch high. On the rising
edge of the next clock the Q output of the D flip·flop
will switch high and the process will repeat. There exists
at the output of SW1 a square wave pulse train with
positive amplitude V REF and negative amplitude 0 V.
The duty cycle is logically ANDed with the input
frequency fiN' The resultant'frequency f equals: .
f = (duty cycle) x (clock)
Frequency f is accumulated by counter no. 1 for a time
determined by counter no. 2. The count contained in
counter no. 1 is then:
(count)
=__f_ _ = (duty cycle) x (clock)
(clock)/N
The DC value of this pulse train is:
VOUT
= VREF
tON
tON + tOFF
= VREF
(duty cycle)
For the ADD3701 N = 4000.
Schematic Diagram
COUNTER NO.1 (+ N)
RESET
L------ICOUNTER NO. 2(+2N)
V,N = VFB = V REF x (duty cycle)
i = (duty cycle) x liN
Count in Counter No.1
= _1_'
liNIN
,
(duty cycle) x liN
liNIN
=~ x N
VREF
Figure 1. Analog Loop Schematic Pulse !VI0dulation AID Converter
5·19
(clock)/N'
l>
C
C
w
......
o
~
o,...
('I)
c
c
«
General Information
The timing diagram, shown in figure 2, gives operation
for the free running mode. Free running operation is
obtained bV connecting the Start Conversion input to
logic "1" (Vee). In this mode the analog input is continuously converted and the display is updated at a rate
equal to 129,024 x l/f/ N •
Internally the ADD3701 is always continuously converting the analog voltage present at its .inputs. The Start
Conversion input is used to control the transfer of
information from the internal counter to the display
latch..
.
The rising edge of the Conversion Complete' output
indicates that new information has been transferred
from the internal counter to the display latch .. This
information will remain in the di.splay latch until the
next low-to·high transition of the Conversion Complete
output. A logic "1" will be maintained on the Conversion
C,:,mplete output for a time equal to 128 x l/f lN .
An RS ·Iatch on the Start Conversion input allows a
broad range of input pulse widths to be used on this
signal. As shown in figure 3, the Conversion Complete
output 'goes to a logic "O"on the rising edge of the
Start Conversion pulse and goes to a logic ~~1" some time
later when the new conversion is transferred from the
internal counter to the display latch. Since the Start
Conversion pulse can occur at any time during the
conversion cycle, the amount of time from Start Con·
version to Conversion Complete will vary. The maximum
time' is 129,024 X llflN and the minimum time is
512x 1/fIN'
Figure 3 gives the operation using the Start Conversion
input. It is important to note that the Start Conversion
input and Conversion Complete output do not influence
the actual analog-to-digital conversion in any way.
Timina Waveforms
fiN
.rut
r:
--:------~-129.024
x l/flN
1-0.-_--------128.000 x l / f I N - - - - - - - . ,
CONVERSION CYCLE
(INTERNAL SIGNAL)
--------------------'1L.....Jr---
r·---------
128.512 x l I f I N - - - - - - - + A / - t
CONVERSION
COMPLETE
t
I
~128/f1N
~
t
I
CONVERSION
NEW
CONVERSION
STARTS
ENDS
Figure 2. Conversion Cycle Timing Diagram for Free Running Operation
5·20
»
c
c
.....
CAl
o
~
r---------.....,U
CONVERSION CYCLE
(INTERNAL SIGNAill
r-,
n
START CONVERSION:.,.·__....._--'
CONVERSION ':
COMPLETE - - - - - - -
u
.-.
L _ _ _...
1.....i1_ _...:.,-_ _ _ _ _ _ _ _ _ _ _ _ __
r------,~
"
Figure 3. Conversion Cycle Timing Diagram Operating with Start Conversion Input
Applications
SYSTEM DESIGN CONSIDERATIONS
The Il)ost important characteristic of transients on the
Vee line is the duration of the transient and not its
amplitude,
Perhaps the most important thing to consider when
designing a system using' the ADD3701 is power suPpJy
noise on the Vcc and ground lines. Because a single
power supply is used and currents in the 300 mA range
are being switched, good circuit layout techniques
cannot be overemphasized. Great care has been exercised
in the design' of the ADD3701 to minimize these prob·
lems but poor printed 'circuit layout cal) negate these
features.
.
Figure 4 shows a DPM system which converts 0 to +3.999
counts operating from a non·isolated power supply.
In th,is configuration the sign output could be + (logic
"I") or - (logic "0") and it should be ignored. Higher
voltages could be converted by placing a fixed divider
on the input; lower voltages could be converted by
placing a fixed divider on the feedback, as shown in
figure 5.
Figures 4, 5, and 6 show schematics of DVM systems.
An attempt has been made to show, on these schematics,
the proper di'stribution for ground and Vcc. To help
isolate digital. and analog portions of the circuit, the
analog Vee and ground have been separated from the
digital Vee and gr~und. Care must be taken to eliminate
high current from flowing in the analog Vee and ground
wires. The most effective method of accomplishing this
is to use a single ground point and a single Vee point
where all wires are brought together. In addition to this
the conductors must be of sufficient size to prevent
significant voltage drops.
Figures 5 and 6, show systems operating with an isolated
supply that will convert positive and negative inputs.
60 Hz common mode input becomes a problem in this
configuratioJ1 and a transformer with an electrostatic
shield between primary and secondary windings is shown.
The necessity for using a shielded transformer depends
on'the performance requirements and the actual application.
The filter capacitors connected to V FB (pin 14) and
V FLT (pin 11) should be low leakage. In the application
examples shown every 1.0nA of leakage current will
cause 0,1 mV error (1.0xl0- 9 A x 100kn = 0.1 mV).
If the leakage current in both capacitors is exactly the
same no error will result since the source impedances
driving them are matched.
To prevent switching noise from causing jitter problems,
a voltage regulator with good high frequency response
is necessary. The LM309 and the LM340·5 voltage
regulators all function well and are shown in figures 4,
5, and 6. Adding more filtering than is shown will in
general increase the jitter rather than decrease it.
5-21
ADD3701
43
NSB5918
lMJ09
>IV
lDDmA
I ~R
. i - i-
"1 .Tocl ~~IN914
.'j~ II
,
.
..
I
~-
POWER GNU
I
BB01r]
Rl
R2
;on l
[ 1kII
±1%1
r rl
'1
\~~
---"
r -'~;--:k- ~
I
I
c".
zz
"'1!!
g
1
I
22MH
16
~
I
25tt;...-.,
1.5k
11
~
19
18
~
~
20
<;
c
...
21
!!
L
:::
2J
:~ion .
"
"
The LF 13300 is the anal.og secti.on .of a precision inte·
grating anal.og·t.o·digital (AID)! system. 'JF ET and. bip.olar
transist.ors (BI·FET) are cgmllioed .on the same 'chip t.o
pr.ovide' a high input impedance unity gain buffer;
cdmparat.or and integrat.or, al.ong with 9 JFET anal.og
switches. Th'e LF1,3300 has sufficient res.oluti.on t.o
c.onstruct up t.o a 4 1/2·digit Digital Panel Meter (DPM)
.or a 12·bit (plus sign) Data Acquisiti.on System and is
specifically designed .{.o'r use 'with either the AD
DPM digital building bl.ock .or the ADB 1200
12·bit binary building:bl.o,ck.
physically and electrically
digital circuits, '
.of ±llV with ±15V supplies
directly with ·micr.opr~~ess.ors '
~an be used as, a i 2·bit plus sign binary
1/2·digft,3 314·digit and 3 1/2.digit Digital
Panel Meter (DPM)
*See ADB1200 (MM58631 data sheet
Dual·ln·Line Pa~kage
PDwtR
.. UPPLVIlNO
y.
18 ANALOG
GOD
I'
lJANAlOG
INPUT
l
COMPARATOR J
. OUT
16VREFIN
158UFl:tR
Nf..GRAf,'IP
OUT
140PAM'
5
UNK~OWN
n
POLOET/pas 6
RAMPUNKNDwrt
OFfSH J
'"our
OPAMP
12
COC1
CORRECT
RAMP 8
RUERENCE
DIGITAL!
GNU
lIeOC1
"
COCJ
TOPVIEW
DIGUAL
GNOIOGI
5·26
Order Number LF13300D
See NS Package D18A
Section 6
Voltage References
Voltage References
~National
r-
::J:
~ Semiconductor.
8.....
LH0070 Series Precision BCD Buffered Reference
LH0071 Series Precision Binary Buffered Reference'
r-
o
::J:
General Description
The LH0070 and LH0071 are precision, three terminal,
voltage references consisting of a temperature compensated zener diode driven by a current regulator and a
buffer amplifier_ The devices provide an accurate reference th.at is virtually independent qf input voltage, load
current, . temperature and time_ The LH0070 has a
10_0DOV nominal output to provide equal step sizes in
BCD applications_ The LH0071 has a 10_240V nominal
output to provide equal step sizes in binary applications_
making them ideal choices as reference voltages in
precision D to A and A to D systems_
...
Feat~Jres
The LH0070 and LH0071 series combine excellent
long term stability, ease of application, and low cost,
• . Accurate output voltage
10V ±0.01%
LH0070
10.24V ±0.01%
LH0071
12.5V to 40V
• Single supply operation
.o.m
• Low output impedance
0.1 mV/V
• Excellent line regulation
• Low zener noise
1 DO pVp-p
• 3-lead TO-5 (pin compatible with the LM109)
• Short circuit proof
3mA
• Low standby cu rrent
Equivalent Schematic
Connection- Diagram
The output voltage is established by trimming ultrastable, low temperature drift, thin film resistors under
actual operating circuit conditions_ The devices are shortcircuit proof in both the' current sourcing and sinking
.
directions_
r--------....-----oV,N
TO-5 Metal Can Package
.
OUTPUT
-u~
">....--oVOUT
CI
-'.J'
R2
3
.;
"'15V
Typical Applications
+1 SV
'BDTTDMVIEW
Order Number LH0070-QH. LH0071-QH, LH0070-1H,
LH0071-1H. LH007D-2H or LH0071-2H
See' NS Package H03S' .
GNO
ICASEI
I-"-------:..,.-OVOUT
0-"'---"'----""'_------,
100
*Ndte: The output of the LH0070 and LH0071
may be adiusted to a precise voltage by using
100
L-_ _ _ _ _ _ _ _ _ _-'Io.I"OO".......+--o'O.OOV
T
+
OPTIONAL
OUTPUT
. the above cjr~uit since t~e supply, c,urrent of
the devices is relatively small and constant
with temperature and input voltage. For the
circuit shown. supply sensitivities are degraded
slightly to O.Ol%IV 'change in'''VbUT for
changes in VIN andV-.
.
An additional temperature drift of 0.0001%/
·C is added due to the variation of supply
current with temperature of the LH0070 and
LH0071. Sensitivity to the value of R 1, R2
and R3 is 10.. than 0.001 %1%.
·Output Voltage Fine Adjustment
Statistical Voltage Standard
6-1
o
o.....
....
en
CD
Ci"
t/)
Absolute Maximum Ratings
Supply Voltage
Power Dissipation (See Curve)
Short Circuit Duration .'.
Output Current
Operating Temperature 'Range .
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Electrical Characteristics
40V
600mW
Continuous'
±20inA
-55°<:: to +125°C
-65°C to +150°C
300°C
(Note 1) ,
PARAMETER
CONOITIONS
MIN
TYP'
MAX
UNITS
Output Voltage
LH0070
10.000
V
LH0071,
10.240
V
Output Accuracy
·-0,"':1
±0,03
±0.1
%
-2"
±0.02
±0.05
%
Output Accuracy
-0,-1
±0.3
-2
±0.2
Output Voltage Change With
(Note
%
%
I
2)
Temperature
-0
%
± 0.2
-1
±O.02
± 0.1
%
-2
±0.01
±0.04
%
0.02
0.1
%
0.Q1
0.03
%
40
V
Line Regulation
13V -:; Y,N -:; 33V, TC = 25°C
-0,-1
,-2
Input Voltage Range
Loa~ Regulati«:>n,
12.5
o mA -:; lOUT -:; 5 mA
•. ".
Quiescent Curren:t"
. ,-'
'13\1-:; Y,N -:; 33V, lOUT = 0 mA
2
0.01
0.03
3
5
1.5
Change In Quiescent Current
AV,N = 20V From 13V To 33V
0.75
Output Noise Voltage
BW= 0.1 HzTo 10 Hz, TA = 25°C
20
Ripple Rejection
f = 120 Hz
0.01
%
mA
mA
I-lVp-p'
%!Yp-p
"
Output Resistance
Long Term Stability
n
0.2
T A = 25~,C, (Note 3)
-o,-,-y
±0.2
%/yr.
-2
:±0.05
%/yr.
.:
~
.
,
Not. 1: - Llriless 'Otherwise specified, these specifications apply for V IN = 15.0V, R L = 10
+125·C. _
Nota
'''.''
kn, and over the temperature range o.f _55· CST A S
:z: Thi~ 'specification' is the differ~nce ,in output voltage measured at T A = 85"(: and T A = 25·C or T A = 25· C and T A = _25· C with readings
taken .fter.test chamber and device-under-te.st stabilization at temperature using a suitable precision voltmeter.
Note 3: This parameter is gu.rant~ed b't,design and not tested." ,
6-2
....%
Typical Performance Characteristics
Maximum Power Dissipation
700
100°C
~
.s
~
I-- ~·IV.TJI~AX)"50C
500
200°C
°JA= - -
::
i=
400
ill
C
300
"~
200
2
°
600
"
_TAD-55°C
TA=+25°C
-TA· +125°Cl
_,....
I
-
N
....."'J > f""
W
<::
F
I\.
100
50
75
~
~ -500
100
"
125
/
150
'5
"
10
15'
20
25
3D
35
0
CASE TEMPERATURE rC)
12
I I~
I"
10
TA=+125°~'"
\
TA=-55°C~~
I I I
I I I
....
13V ~ VIN S JOV
TA=+25°C
CL = 10 pF
If-f.\
\\ 1
\\ \
CL = O.Dl"F
II I
!; -500
~
I--t--!--f-+-If--+-l
-0.3 1--'--'_-'--'-_'---1--'
-50 -25
25 50 75 100 125
Output Short Circuit
Characteristics
I I I
~
~
-0.1 ~0l!'=--t---t-+-1r=..,..~
-0.2
INPUT VOLTAGE IV)
=
'"
~~
co>
~
,./
~
~ 500
~ ~ 0.1 ~~=-!--f-+-Ic-:::;~~
-JW'Ir--t...:;'OOV CAL.
30k
3k
1/4W
Expanded Scale AC Voltmeter
6-3
25
30
o
o.....
o
....
%
o
o.....
.....
.
fh
.-CD
CD
........
Typical Applications
(Continued)
+
In
0
0
:::t
..
0
..J
Zl-32VOC
RAW INPUT
~
OUTPUT 1
a-21V
.....
i
..J
4.111
OUTPUl2
D-Z5V
,...-----------...
-""'1~---."v
~-_.,._-VOUT:
IIIVFOR20mA
DYfDR4mA
...- - ;_ _ I5V
ZERO
..._ _-'II'I1MY-___~:.
Precision Proces. Control Interface
6-4
Voltage References
~National
~ Semiconductor
LM103
, Reference Diode**
general description
The LM103 is a two-terminal monolithic reference
diode electrically equivalent to a breakdown diode_
The device makes use of the reverse punch·through
of double-diffused transistors, combined with active circuitry, to produce a breakdown character·
istic which i~ ten times sharper than single-junction
zener diodes at low voltages. Breakdown voltages
from 1.8V to 5.6V are available; and, although the
design is optim ized for operation between 100 ~A
and 1 mA, it is completely specified from 10 /lA to .'
10 mAo Noteworthy features of the device are:
• Performance guaranteed over full military tem·
perature range
• Planar, passivated junctions for stable operation
•
The LM 103, packaged in a hermetically sealed,
modified TO·46 header is useful in a wide range of
circuit applications from level shifting to simple
voltage regulation. It can also be' employed with
operational amplifiers in producing breakpoints to
generate nonlinear transfer functions. Finally, its
unique characteristics recommend it as a reference
element in low voltage power supplies with input
voltages down to 4V.
• Exceptionally sharp breakdown
•
Low capacitance.
Low dynamic impedance from 10 /lA to 10 mA
schematic and connection diagrams
Metal Can Package
+
R1
'"
Note: Pin 2 connected to CIIS!•.
TOP VIEW
Order Number LM103H
See NS Package H02A
typical applications
Saturating Servo Preamplifier
with Rate Feedback
200 rnA Positive Regulator
~~!OJ
02
V,,,>SSV
-";......--1......-.lf---,
AI
10K
C2
JOpf
.
LMIQ3
'"
**Covered by U.S. Patent Number 3,571,630
6-5
Voo.,·$V
.
22.
L.._""".-~:~
."'".
"
..'"
+
coU"F
R3
'khflll\laIum
lSaJ.:lkr"",,_ ...
,' ........
ItmpItlllUII.nll,
r
~
w
o
M
o
i...I
absolute maximum ratings
Power Dissipation (note 1 )
Reverse Current
Forward ,Current
Operating Temperature Range
Storage' Temperature Range
Lead Temperature (soldering, 60 sec)
~
,
250mW
20mA
100mA
_55°C to 125°C
-65°C to 150°C
300°C
..
.
electrical characteristic~
(Note 2)
\.
"
;PARAMETER
MIN
CONDITiONS
TYP,
MAX·
UNIT
,
"
"
10~A$IR $100MJX
Reverse Breakdown Voltage ChaTlge
I
'lOOIlA$IR$l mA
.,
,
.
50 '
15
1 mA~IR$10rnA
50
, 150
IR = 3 rnA
'5
25
IR=0.3mA
15
. 60
,
ReverSe Dynamic Impedance (Note 3)'
:'120
60
"
"
'
.'
Reverse Leakage Current
2
5
0.8
1.0
,VR = V z -0.2V
Forward Voltage Drop
IF = 10 rnA
Peak-to-Peak Broadband' Noise Voltage
10 Hz~f~100 kHz,I R = 1 rnA
Reverse Breakdown Voltage Change
with Current (Nole 4)
lOIlA$.IR $,.lOO IlA
,
0.7
mV
mV
.mV
n
n
"
IlA
V
Il V
300
I
1001lA~IR ~ 1 mA
200
mV
60
mV
200
mV
I
,;
1 mA~IR~10rnA
Breakdown Voltage Temperature
Coefficient (Note 4)
lOOIlA$,IR$, 1 mA
mVtC
-5.0
..
i
'.
.• I.
Note 1: For operating at elevated temperatures, the·device must be derated based on a 150°C maximum junction temperature
and a thermal resistance of 80°CIW iunction to case or 440°C/W junction to ambient (see curvel.
Note 2: These specifications,apply for TA '= 25°C and 1.8V < Vz < S.6V unless stated otherwise.'The d.iode should not be
operated with shunt capacitances between 100 pF and 0.01 IlF, unless isolated by at leasa 300n resistor; as it may oscillate at
some currents.
Note 3: Measured lJI!ith the peak-to peak chi;lnge
of reverse 'c~;rent equal to 10% of the DG reverse curren,t.
Nota 4: These specifications apply for -55°C < TA'< +125°C.
'''i
:
6-6'
~
r
3:
....
o
(,.)
guaranteed reverse characteristics
03
TA
0.2
~
~
..
-.J:I
r::r
A
f-
ICAL
~
~
-01
-02
i"
-
-sS-C
"
01
'"
03
1,I4v~ v}Jl~-
TA
02
II
~
.L
g'"
01
1.0
ReVERSE CURRENT (rnA)
-0.3
001
10
"
125·C
'-,
z
~
I
TA
01
g'"
"'"
MAXIMUM
-02
-0.3
"""
'~
~
-0.1
:-
lJLLU
02
,-
~
TYPICAL
1/
001
25·C
z
"
~
MAXIMUM
..
01
'"
03
-l\vdv,~,16IVI-
~
TYPICAL
-0.1
100-
-0.2
II
~ ~MAXIMUM
-03
01
10
'001
10
REVERSE CURRENT (mAl
1.0
01
10
REVERSE CURRENT (mAl
typical performance characteristics
Reverse Characteristics
~ I•
LM1D3·3.D
I
I
l~
a: 10-6
~
I1r'
125°C
_...Yt',
25"C
•
:;- lK
I
:
I
w
Temperature Drift
Reverse Dynamic Impedance
Iw,
II -J,-,;6t
10K
~
0,6
0.4
\ T... "_55°C
~
~
i;:
a;
c
z
~
~ 100
TA "25°C
u
'-55"C
i
~
~ r---.
001
REVERSE VOLTAGE (VI
10
01
TA
"
125°C
'":;«
0
>.
llf
10
III
'""
~
"
"
~
0.'
~
~
>
~. ·125·C
~
8
I - t - I-OUTPUT:-
4
t-
0.1
10
10
FORWARD CURRENT (mAl
300
z
~......
"
~
l:l
i'" ..........
200
"
~
~
~
0
0.01
125
400
'"z
w
T... "2SoC
75
Maximum Power Dissipation
~ 6
i-
~
2:
25
INPUT
10
~
-25
~
TEMPERATURE eel
11
T~ .I.!I·c ~
i'
-0.6
-75
2.4V$V z $56V-
10
I"~
-0.4
Response Time
1.5
~
-0.2
REVERSE CURRENT (mAl
Forward Characteristics
w
I'..
w
10
fI
I'
0.2
100
2.
4
10
TIME(~)
BREAKDOWN
VOLTAGE*
PART
NUMBER
1.8
2.0
2.2
2.4
2.7
3.0
3.3
3.6
3.9
4.3
4.7
5.1
5.6
LM 103H'·1.8
LM103H-2.0.
LM103H-2.2.
LM 1,03H·2.4
LM103H-2.7
LM103H·3.0
LM103H-3.3
LM103H·3.6
LM103H·3.9
LM103H-4.3
LM103H·4.7
LM103H-5.1
LM103H-5.6
6-7
100
o
25
'"
..........
75
100
50
AMBIENT TEMPERATURE (OCI
'"
• Measured at IR = 1 rnA.
Standard tolerance is ± 10%.
~National
Voltage References
~ Semiconductor
LM113/LM313 Reference'Diode
general description
The LM 113/LM313 are tem'perature compensated,
low voltage reference diodes. They feature ex·
tremely-tight regulation over a wide range' of
operating,currents in addition to an unusuallY·low
breakdown voltage and good temperature stability.
• Dynamic impedance of '0.3n from 500 JlA to
20mA
,
• Temperature stability typically 1% over -55°C
to 125°C range (LMl13). O°C to 70°C (LM313)
., Tight tolerance: ±5% standard, ±2% and ±1 %
on special order.
The characteristics of this reference recommend it
for use in bias-regulation circuitry, ,in low·voltage
power supplies or in battery powered e'quipment.
The fact that the breakdown voltage is equal to a
physical property of silicon-the energy~band·gap
voltage-makes it useful for many temperaturecompensation and temperature-measurement
, functions .
The diodes are synthesized using transistors and
resistors in a monolithic integrated circuit. As such,
they have the same low noise and long term
stability as modern 'IC op amps. Further, output
voltage of the reference depends only on highly·
,predictable properties of components in the IC;
so they can be manufactured and supplied to tight
tolerances. Outstanding features include:
• Low breakdown voltage: 1.220V
schematic and connection diagrams
Meta' Can Package
fll
R'
UK
RZ
zaa
IUK
.. Note: Pili 2 conntcted to cne..
ft,
TOPVLEW
n.
Order Number LM113H ar' LM313H
Nil Package H02A
, See
R5
"K
typical applications
Leve' Oetectar far Phatadiade
Low Voltage Regulator
r-------1~-.....,-
.,
lNJlZl
..,
R2
'"
R1
"
'"
OK' '
TTL.
OUTPUT
.,
"
LMJIJ
IZV
LM313
UV
.
ft'
123K
t-'VIi",,",I--'':':'''_---t- YOUT • 2\1
"'
17K
"
C2'
l .. f
tS ohdtanll1um.
6-8
r
absolute maximum ratings
operating conditions
Power Dissipation (Note 1)
Reverse Cu rrent
Forward Current
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Temperature (T A)
LM113
LM313
100 mW
50mA
SOmA
~5°C to +150°C
300°C
electrical characteristics
(Note
PARAMETER
......s::
MAX
UNITS
........
-55
+125
70
°c
°c
s::W
o
2)
Reverse Breakdown Voltage
LMl13/LM313
LMl13-1
LMl13-2
IR = 1 mA
Reverse Breakdown Voltage
Change
0.5 mA::; I R ::; 20 mA
MIN
TYP
MAX
1.160
1.210
1.195
1.220
1.22
1.22
1.280
1.232
1.245
6.0
15
UNITS
V
V
V
mV
..
Reverse Dynamic Impedance
IR = 1 mA
IR = 10 mA
0.2
0.25
1.0·
0.8
n
n
Forward Voltage Drop
IF = 1.0 mA
0.67
1.0
V
RMS Noise Voltage
10 Hz::;f::; 10kHz
IR = 1 mA
5
Reverse Breakdown Voltage
Change with Current
0.5 mA ::; I R ::; 10 mA
TMIN ::;TA ::;TMAX
Breakdown Voltage Temperature
Coefficient
1.0 mA ::; I R ::; 10 mA
TMIN ~TA ~TMAX
I1V
15
Note 1: For operating at elevated temperatures, the device must be derated based on a 150°C
25°C, unless stated otherwise. At high currents,
breakdown voltage should be measure9 with lead lengths less than 1/4 inch. Kelvin contact sockets are
also recommended. The diode should not be operated with shunt capacitances between 200 pF and
0.1 J.lF, unless Isolated by at least a 100 12 resistor, as it may oscillate at some currents.
typical performance characteristics
Temperature Drift
1.240
0.4
IA=l mA
a 1.230 I--t-+-+-+-+-+-I-t--l
-
'"~
~
w
g
:Jl
1.220
1--t--b....-+--+-+~-1000::1
.,.. ..... 1"'"
ffi
'"~ 1.210 1--t-+-++-+-t--1:-H
1.200 L-.L--'--'--'--'--I.-J_'--'
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (OC)
Reverse Characteristics
Impe~ance
FJeverse Dynamic
,-r--r--r--r-r-,.-"-"",-,
,.,... IllL
I"'"T -125"C
1'1
w
0.3
TAJJ
~
~
..,~
; / ~1
~ 0.2
,.,...
..
z
>-
1%I~fC
1111111
0.1
0.3
1
3
10
REVERSE CURRENT (rnA)
6·9
mV
%/"C
0.01
maximum junction and a thermal resistance of 800 C/W junction to case or, 4400 C/W jun~tion to
ambient .. /
=
r
...
W
CONDITIONS
Note 2: These specifications apply for T A
W
MIN
30
REVERSE CURRENT (rnA)
typical performance characteristics (con't)
Reverse Characteristics
Noise Voltage
Reverse Dynamic Impedance
,0-'
90
100
IR=5mA
TA =25°C
80
:s
..."'
.
.......II!!
Xi1VJ
25°C
,0-'
0.2
0.4
0.6
10
."z
...~
"
'.0
10k
Ik
~
,~
~
~~
0.5
~
o
iJi
"''"
«
!:;
i'TAI"25°C
Ii il'll
0.5
soC
100
Ik
UT -
!-.",
:NT
10
">
I
I
I
I I
o
12
1&
20
10"
TIME (pO)
FORWARD CURRENT (mA)
Ill"
+15V
130K
1%
10K
OUTPUT
INPUTS
L...-1~---15V
Constant Current Source
Amplifier Biasing for Constant Gain with Temperature
2"K
,%
.K
"%
12K
".AlliustforDVatIrC
tAdjustfDI 100mVtC 1
-IIV
Thermometer
6·10
111'
CAPACITANCE (pF)
typical applications (con't)
I3DK
1%,
10k
lOOk
FREQUENCY (Hz)
I~'UT
IJ
I
50
10
Our
~
z 0.5
V
~~
~.
10
Maximum Shunt Capacitance
I
.
1.5
TA "-56°C
1M
Response Time
1.5
> 1.0
lOOk
FREQUENCY (Hz)
2.0
~
-
30
100
'.2
2.0
,!:;
~
40
0.1
0.8
Forward Characteristics
....
60
f-"
REVERSE VOLTAGE (V)
~
~
z" 50
z
~
' -I
70
6
~
ts:c
~
10"
~National
Voltage References
~ Semiconductor
LM129, LM329 Precision Reference
general description
The LM 129 and LM329 family are precision multicurrent temperature compensated 6_9V zener references
with dynamic impedances a factor of 10 to 100 less than
discrete diodes_ Constructed in a single silicon chip, the
LM 129 uses active circuitry to buffer the internal zener
allowing the device to operate over a 0_5 mA to 15 mA
range with virtually no change, in performance. The
LM129 and LM329 are available with selected temperature coefficients of 0.001, 0:002, 0.005 and O.Ol%tC.
These new references also have excellent long term
stability and I?w noise.
simplifies biasing and the wide operating current allows
the replacement of many zener types.
The LM 129 is packaged in a 2-lead TO-46 package and is
rated for operation over a -55°C to +125°C temperature
range. The LM329 for operation over 0-70°C is available in both a hermetic TO-46 package and a TO-92
epoxy package.
features'
A new subsurface breakdow'n zener used in the LM129
gives lower noise and better long term stability than
conventional IC zeners. Further the zener and temperature, compensating transistor are made by a planar
process so they are imn:lUne to problems that plague
ordinary zeners. For example, there is virtually no
voltage shifts in zener voltage due to temperature cycling
and the device is insensitive to stress on the leads.
•
•
•
•
•
•
The LM129 can be used in place of 'conventional zeners
with improved performance. The low dynamic impedance
0.6 mA to 15 mA operating current
0.6n dynamic impedance at any current
Available with temperature coefficients of 0.001 %tc
711V wide band noise
5% initial tolerance
0.002% long term stability
• Low cost
• Subsurface zener
typical applications
Simple Reference
9VTO 40V
Low Cost 0-25V Regulator
H~--VOUT
Adjustable Bipolar Output Reference
240
SDk
15v
LM329
+15V
1,5k
510
SDk
OUTPUT
-6.9.$ VOUT S. 6.9
150
-10V
50k>ot---....::..j
10 TURN
OUTPUT
ADJUST
LM129
6.9V
-15V
6·11
3~
pF
absolute maximum ratings
Reverse Breakdown Current
Forward Current
Operating Temperature Range
LM129
LM329
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
30mA
2mA
-55°C to +125°C '
O°C to +70°C
-55°C to +150°C
300°C
,
electrical characteristics
(Note 1)
CONDITIONS,
PARAMETER
,
"
LM'329B, C, 0
LM129A, B,C
.. MAX
'MIN
TYP
MAX
MIN
'TYP'
6,7
6,9
i2
6.6
6.9
7,25
0.6 mA -::; I R -::; 15 mA
9
14
9
20
Reverse Dynamic Impedance
T A'; 25°C, IR = 1.mA
0.6
1
0.8
2
RM~
T A = 25°C,
7
20
7
100
Reverse Breakdow'n Voltage
TA
';'
.,'
25°C,
0.6 mA:5; IR -::;,i5 .~A
Reverse Breakdown Change
with Current
Noise
I
mV
Q
J).V
T A = 45°C ±O.l°C;
.. IA. = 1 mA ±0.3%
Temperature Coefficient
V
T A = 25°C,
10 Hz -::; F -::; 10kHz
Long Term Stability
UNITS
20 '
20
ppm
IR = 1 mA
ppmtC
LM129A
6
10
LM129B, LM329B
15
20
15
20
ppmtC
LM129C, LM329C
30
50
30
50
ppmtC
50
100
ppmtC
LM329D
Change In Reverse Breakdown
,',
1 mA -::; IR -::; 15 mA
1
1
1 mA-::; IR -::; 15mA
12
12
1 mA -::; I R -::; 15 mA
0.8
1
ppmtC
Temperature Coefficient
Reverse Breakdown Change
mV
with Current
Reverse Dynamic Impedance
Q
Note1:These specifications apply for-55°C:'; TA:'; +125°C for the lM129 and O°C:,; TA S; +70°C for the LM329 unless otherwise specified. The
maximum junction temperature for an LM129 is 150"C and LM329 is 100°C. For operating at elevated temperature, devices in TO·46 package
must be derated based on a thermal resistance of 440°C/W junction to ambient or 80"C/W junction to case. For the TO·92 package, the derating
is based on 180°C/W junction to ambient with 0.4" leads from a PC board and 160°C/W junction to ambient with 0.125" lead length to a PC
board.
.
,
"
6·12
typical applications (con't)
OV to 20V Power Reference
25VT040V---I~----------------------------------~-----------------'
LM195
Lr~129
6.9V
6-____4-__-4____~~__----e_--:~T020V
20k
100 pF
-5V
External Reference for Temperature Transducer
15V
lk
OUTPUT
} 10 mVrk
OUTPUT
LM129
6.9V
LX5600
INPUT
IN457
6-13
lk
typical applications (con't)
Positive Current Source
10VTO
40V-"'--~""'------"'-------,
350
0.1%
20k
0.1%
2N2219
LM129
6.9V
10k
20k
0.1%
Buffered Reference with Single Supply
+15V-+---------.,
9k
>~~-10V
LM129
6.9V
connection diagrams
Plastic Package
Metal Can Package
BOlTOMVIEW
BOTTOM VIEW
Order Number LM129AH. LM129BH
LM129CH. LM329BH. LM329CH
or LM329DH
See NS Package H02A
Order Number LM329BZ. LM329CZ
or LM329DZ
See NS Package Z03A
6-14
typical performance ·characteristics
Reverse Characteristics
Response Time
a
L
IJ Tj'\~ C- r-.r". r-r--
5
3
2
1
0
0
10
. T1'25 C
-\-~
TI'~ ..>"1--'
II
10-5
6.45 6.55
&.65
A j '125C
6.65
/
r--
(IVPut.~,.
.Lt. .:t'· r-r-INPUT-
o
I
&.15
,".
OUTPUT
J
6.95
7.05
100
REVERSE VOLTAGE (VI
200
r--
300
,400
TIME (/oIs)
Dvn8~ic:.lmpedance
Forward Characteristics
1,2
1,0
~
_~
0.8
> ·0.6
"'"
3l
~
0.4
'0.2
1--9----i---C-.+--j
0.1
0.01
10
0.1
~_-,--I_--,--_--,---:--,
10
100
FORWARD CURRENT (mA)
1\
10k
lOOk
FREQUENCV (Hz)
Reverse Voltage Change.
Zaner Noise Voltage
150
Tj' ~55' C-
2~
~
~25"CTj'12~~
'.'
.
!
100
1\
~
~
;;
z
~~
I ""25C
-
~
o
/
50
, ,0
10
10
100
REVERSE CURRENT (mAl
lk
10k
FREQUENCY (H"
Low Frequency Noi.e Voltage
0.01 HZS;'S;1
,1lI
;;
z
10
TIME (MIN UTESI
6-15
Hz~ •.•
lOOk
~National
~ Semiconductor
Voltage References
LM134/LM234/LM3343-Terminal
Adjustable Current Sources
General Description
The LM134/LM234/LM334 are 3-terminal adjustable
current sources featuring 10,000: 1 range in operating
current, excellent current regulation, and a wide dynamic
voitage range of 1V to 40V _ Current is established with
one external resistor and no other parts are required.
Initial current accuracy is ±3%_ The LM134/LM234/
LM334 are true floating current sources with no separate
power supply connections. In, addition, reverse applied
voltages of up to 20V will draw only a few microamperes
of current, allowing the devices to act as both a rectifier
and current source in AC applications.
LM134-3/LM234-3 and LM134-61LM234-6 are specified
as true temperature sensors with ,guaranteed initial
accuracy of ±3° C and ±6° C, respectively. These devices
are ideal in remote sense applications because series
resistance in long wire runs does not affect accuracy.
In addrtion, only 2 wires are required.
The LM134 is guaranteed over a temperature range of
-55°C to +125°C, the LM234 from -25°C to +100°C
and the LM334 from O°C to +70°C. These devices are
available in TO-46 hermetic and TO-92 plastic packages.
The sense voltage used to establish operating current in
the LM 134 is 64 mV at 25°C and is directly proportional to absolute temperature (OK). The simplest one
external resistor connection, then, generates a current
with ""+0.33%fC temperature dependence. Zero drift
operation can be, obtained by adding one extra resistor
and a diode.
Features
•
•
•
•
•
•
Applications for the ~e~ c~rrent sources' inciude bias
networks, surge protection, low power reference, ramp
generation. LED, driver, and temperature sensing. The
Operates from 1V to 40V
0.02%/V' current regulation
Programmable from 1 IJ.Ato 10 mA
Tru~ 2-terminal operation
Available as fully specified temperature sensor
±3% initial accuracy
Typical Applications
Basic 2-Terminal Current SOurce
Zero Temperature Coefficient Current SOurce
+vIN
~'
.
RSET :
RSEl
"',
.
RI~IO
RSEl
-VIN
-VIN
*Select ratio of Rl to RSET to obtain' zero drift. 1+" 2 ISET
Ground Referred Fahrenheit Thermometer
Terminating Remote Sensor for Voltega Output
R4
5&k
+VIN
RZ R3*
100
LM33&Z
Z.&V.
III
-=
":"
*Select R3 = VREF/583IJ.A. VREF may be any stable positive vol~age;:: 2V
Trim R3 to calibrate
6-16
Absolute Maximum Ratings
V+ to V- Forward Voltage
LM134/LM234
LM334/LM 134-3/LM 134-6/LM234-3/LM234-6
V+ to V- Reverse Voltage
R Pin to V- Voltage
Set Current
Power Dissipation
Operating Temperature Range
LM 134/LM134-3/LM134-6
LM234/LM234-3/LM234-6
LM334
Lead Temperature ,(Soldering, 10 seconds)
Electrical Characteristics
PARAMETER
40V
30V
20V
5V
10mA
200mW
'-55°C to +125°C
-25°C to +100°C
O°C to +70°C
300°C
(Note 1)
LM134/LM234
TYP
MIN
MAX
CONDITIONS
MIN
LM334
TYP
MAX
Set Current Error, V+ = 2.5V,
10IlAS ISETS 1 rnA
3
6
(Note 2)
1 mA < ISET S 5 mA
5
8
21lA S ISET < lOfJ.A
5
8
Ratio of Set Current to
V- Current
14
lOfJ.AS ISETS 1 mA
14
21lA S ISET S 10 fJ.A
Minimum Operating Voltage
18
23
14
14
1 mAs ISETS 5 mA
18
18
UNITS
%
%
%
26
14
23
14
18
26
2fJ.AS ISETS 100llA
0.8
0_8
V
lOOIlA
.s
~
:i'"1
~
~
'"'"
!:;
co
>
~
ffi
a:
=
Dynamic Impedance
2S0
100
IR"'lmA
3.0
Tj'12S"C
2.S
/.~
Z
1.0
0
./
0
/'
~
~
150
~
0
c;
I
Tj'ZS"C_
I
B
4
6
2
REVERSE CURRENT (mAl
200
!
./. ~'-SS"C
1.S
0.5
~
z
Ti' 25 "C"-
\
IR"l mA
g
~
1
_\
"-
u
10
'""co>
1
':i!
100
I
"
i!...
'"
III
.4
Tj'12S"CI~
~
Tj--SS"C
Tj'ZS"C-
50
10
10
100
lk
10k
FREQUENCY IHzI
6-25
0.1
lOOk
10
lk
100
lDk
FREQUENCY (HzI
.100k
Typical Performance Characteristics
Response Time
E
'"z
2
w
1
!
.~'"
>
.1
f--
OUTPUT
~r
l - t-
i-
f-'T
l- i0_
S
0
-i
1
I
E
w
I
0.8
;0
0.4
~
I
1
2
4
6
-
./
0.2
6
REVERSE VOLTAGE (~)
./
~/ V
1~125'CI'
i"'"
_
0
0.001
TIME (.,1
/
v/
V./
0.6 "- Tj" -55'C
I I I I I
0
...--..,--.......,r--,---'-,
1.0
~>
.
"
~'
~"'TUT
IINPUTI
1.2
T;'" 2slc
1
zu
j
Forward Characteristics
Reverse Characteristics
10-1 r-r-r-r-r-r-,-,-...,..-.,-,
I I II I
3
(Continued)
J
0.01
0.1
f--
I
10
,FORWARD CURRENT (rnA)
Temperature Drift
2.S90
2.S70
2.SS0
r:::r=tr~:t;;j==~~
Ib.-",......
q}oo-":.J.-I---i=i==!=:f=f
E 2.S30 Ioo-"F::=±....-+-+-+-+-+-I
~
2.510
: 2.490
~ 2.470
~ 2.450
~ 2.430
1-;:"'1=_~~i-i-+-++"","-.d
E;;j;..+-+-+-+-l-Ii;;:±_-;
1-o....+-+-+-+-1....I::r-::+_-1
1-"'+-+4-1._d_-I-I--.~~
F'*",*,,*,4-1.d-=i="';.....,j
~ ZAio I=t=:=!=="""-!-..J:-::--:J-:::::I-kl
r- .......
A+-+-+-+""I".....tr---:-i
2.390 IRI" I 7
2.370
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE ('C)
Application Hints
The LM 136 series voltage references are much easier to
use than ordinary zener diodes. Their low impedance
and wide' operating current range simplify biasing in
almost any circuit. Further,either the breakdown volt·
age or the temperature coefficient can be adjusted to
optimize circuit performance.
adjust for both the initial device tolerance and inaccuracies in buffer circuitry.
If minimum temperature coefficient is desired, two
diodes can be added in series with the adjustment potentiometer as shown in' Figure 2_ When the device is
adjusted to 2.490V the temperature coefficient is minimized. Almost any silicon signal diode can be used for
this purpose such as a 1N914, 1N4148 or a 1N457. For
proper temperature compensation the diodes should be
in' the same thermal environment as the LM136. It is
usually sufficient to mount the diodes near the LM136
on the printed circuit board. The absolute resistance of
R 1 is not critical and any value from 2k to 20k will work.
Figure 7 shows an LM136 with a 10k potentiometer'
for adjusting the reverse breakdown voltage. With the
addition of R1 the breakdown voltage can be adjusted
without affecting the temperature coefficient of the
device. The adjustment range is usually sufficient to
RS
RS
LM136
~~t--~_+(
Rl
.,..
10k
FIGURE 1. LM136 With Pot for Adjustment of
Breakdown Voltage
'
FIGURE 2. Temperature Coefficient Adjustment
6-26
Typical Applications
(Continued)
Low Cost 2 Amp Switching Regulator t
Y,N
BVTD2oV--~--~--------~~
47.F
'---4~~--------------~~~*~L~,,r~~----~--VDUT 5V
60,.H
+
+
VARD
20D.F
VSK330
620
390
*L1 60 turns #16 wire on Arnold Cor. A-254168-2
t Efficiency'" 80%
Precision Power Regulator with Low Temperature Coefficient
~----__------------~--VOUT
Uk
Rl
375
RZ
Zk
OUTPUT
ADJUST ':'
*Adjust for 3.?5V across R1
6V Crowbar
Trimmed 2.5V Referene.. with Temperature
Coefficient 'ndependent of Breakdown
Voltage
V+-------4~----~~------
10V
5k
SENSITIVE GATE
SeR
LM338
"
~.~~--...( ~~l~BRATE
-:::-
*Ooes oot affect temperature coefficient
6-27
Typical Applications
(Continued)
Linear Ohmmeter
Adjustable Shunt Regulator
RS
T
-------""1P- ~~VOU40V .
6V TO 40V'-JVV'oI-...- - - -....
2.Sk
1%
VOUT
Bipolar Output Reference
SV
Op Amp with Output Clamped
Sk
n'N
10k
1%
2k
f2V -"VV..........- ;
LM136
±I.ZSV
10k
1%
10k
"''''''1/111.--0 v+
Sk
~6V
2.5V Square Wave Calibrator
SV
....lI,....---1~--....- - OUTPUT
.,..",,;:-I~CAlIBRATE
6·28
Typical Applications
(Continued)
Low Noise Buffered Reference
5V Buffored Reference
SV
7VSV,NS36V -
....- - - - - - ,
20k
1%
2.2k
SV
2_SV
10k
CAL
10k
CAL
Connection Diagrams
. TO-92
Plastic Package
Metal Can Package
BOTTOM VIEW
BOTTOM VIEW
Order Number
LM336Z or LM336BZ
Soe NS Package Z03A
Order Number
LM136H. LM236H. LM336H. LM136AH.
LM236AH or LM336BH
See NS Package H03B
T0-46
J'
6-29
~National
Voltage References
~ Semiconductor
LM199/LM299/LM399 Precision Reference
general description
calibration standards, precision voltage or current sources
or precision power supplies. Further in many cases the
.LM199 can replace references'in existing equipment
with a minimum of widng changes.
The LM199/LM299/LM399 are precision, temperaturestabilized monolithic zeners offering temperature
coefficients a factor of ten better than high quality
reference zeners_ Constructed on a single monolithic
chip is a temperature stabilizer circuit and an active .
reference zener_ The active circuitry reduces the dynamic
impedance of the zener to about 0.5Q and allows the
zener to operate over 0.5 mA to 10 mA current range
with essentially no change in voltage or temperature
coefficient. Further, a new subsurface zener structure
gives low noise and excellent long term stability compared to ordinary monolithic zeners. The package is
supplied with a thermal shield to minimize heater power
and improve temperature regulation.
The LM 199 series devices are packaged in a standard
hermetic TO-46 package inside a thermal shield. The
LM199 is rated for operation from -55°C to +125°C
while the LM299· is rated for operation from -25°C to
+85°C and the LM399 is rated from O°C to +70°C.
I
features
The LM199 series references are exceptionally easy to
use and free of the problems that are often experienced
with ordinary zeners. There is virtually no' hysteresis in
reference voltage with temperature cycling. Also, the
LM199 is free of voltage shifts due to stress on the leads.
Finally, since the unit is temperature stabilized, warm up
time is fast.
•
•
•
•
•
•
•
•
•
The LM199 can be used in almost any application in
place of ordinary zeners w'ith improved performance.
Some ideal applications are analog to digital converters,
Guaranteed o.ociOi%tc temperature coefficient
Low dynamic impedance - 0.5Q
Initial tolerance on breakdown voltage - 2%
Sharp breakdown at 400llA
Wide operating current - 500llA to 10 mA
Wide supply range for temperature stabilizer
Guaranteed low noise
Low power for stabilization - 300 mW at 25°C
Long term stability - 20 ppm
schematic diagrams
D3
6lV
.,
,61<
"
,-
L---------4---4---4---~-----'--~~--4.
v-
connection diagram
functional block diagram
Metal Can Package
~
ttjJ
'
M
Reference
Temperature Stabilizer
r- --- ...,
Order Number LM199H, LM299H
or LM399H
See NS Package H04A or H04D
TOPVI£W
6-30
I
I
I
I
I
I
H
.
L ____ ..J
,
r
:s:
....
absolute maximum ratings
Operating Temperature Range
LM199
LM299
LM399
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
PARAMETER
........
r
:s:
N
to
to
........
-55°C to +125°C
-25°C to +85°C
O°C to +70°C
-55°C to +150°C
300°C
r
:s:
w
to
to
(Note 2)
LM399
LM199/LM299
CONDITIONS
MIN
Reverse Breakdown Voltage . 0.5 mA:S; IR :S;IOmA
Reverse Breakdown Voltage
Change With Current
to
to
40V
20mA
1 mA
40V
-D. 1V
Temperature Stabilizer Voltage
Reverse Breakdown Current
Forward Current
Reference to Substrate Voltage VCRS) (Note 1)
6.8
TYP
6.95
MAX
7.3
V
9
12
mV
0.5
1.5
Reverse Dynamic Impedance
IA = 1 rnA
0.5
1
Reverse Breakdown .
Temperature Coefficient
-55°C
TIME (MINUTESI
f T,.in- -
I.'.-r-
r--
n.
I-I--
'~G"' -
'"'"--
20
10
INPUT-
1DO
200
TIME (ps)
r--
300
400
typical applications
Split Supply Operation
Single Supply Operation
·"V--.....-----,
9V TO .0v -~....- - - . . . . ,
7,5k
Rs
TEMPERATURE
STABILIZER
lEMPERATURE
STABILIZER
69SV
6.95V
-1SV
Negative Heater Supply. with
Positive Reference
Buffered Reference
With Single Supply
.I5V--'------,
. , 5 V - - , . . - - - -...- - - - - - - - ,
9k
7.5"
10V
-9V TO
-J3V
Positive CUrrent Source
10VTO.OV-..._ _ _ _- ._ _- ._ _ _ _ _ _- ._ _ _ _ _-.
350
0.1",,'
TEMPERATURE
STABILIZER
6.9SV
lM199
4.3k
Standard Cen Replacement
15VT020V---1_---~....- - - - - - - - - - - - - ,
. 1% REGULATEo
1.6k
12k
0.1%
TEMPERATURE
STABILIZER
OUTPUT
20k
. 6.95V
2k
0.1%
6-33
typical applications (con't)
Nega~ive
Current Source
"
-25V---....- - - -..........-
--------....I
....- - - -....
Portable Calibrator*
Square Wave Voltage Reference
+ISV
15k
SOk
'01-'
...-w..,...-....
--..'II'\r---4~+'i.
~UTPUT
-1-
r
8.Sk
1%
200k
12VTO _
18V-lOOk
lN4!)7
19k
If.
TEMPERATURE
STABILIZER
6.9SV
oTO IOV
INPUT
SQUARE WAVE
3k
,--+__.:;lM;;;I.:;99:....._+-.....I TRIM
*Wllm-up time f'O seconds; intermittent operation does not,dlgrad.'ang term stability.
14V
R'~ference
Precision Clamp·
CLAMP
INPUT
R,
t--------1~-OUTPUT
lN914
·Cllmp 'MIl sink S mA w~ell.l!lpul gats m,Dlt.pOlltlVl than lettlillte
6·34
typical applications (con't)
OV to 20V Power
Ref~rence
25V T 0 4 0 V - - - t - - - - -.....---------------<~------__,
LM195K
TfMPERATURE
STAIlILIZER
Ii
'01
~5V
lB"
....--I--+---'V""'----i~- ~~ i~ ~~v
lM199
Ik
1001'F
IV
Bipolar Output Reference
751<
OUTPUT 69V
TEMPERATURE
STI\B1l1ZEFl
G !l5V
lW
LM199
-15V
6-35
30pF
~
I
IT,090"~
>
:"-r-,.
20
!::
OUTPUT
140
'i 120
=
~ 100
~
:s
40 f-+--t----'k-+~.
160
VH1.4riV
150
60 f-~--:t-l-::-:+--l-+--+-I
w
B
w
o
lOOk
250
~
~
'"
=.
=
FREOUENCY (Hz)
....
....
-4
100
10
'i 200
.§.
-1
,~~.J5'C
I
-3
50
I
0.01 Hl~t$1 Hz
STABILIZED
ITI ~gIl"'C)
300
400
Voltage References
~National
~ Semiconductor
LM3999 Precision Reference
general description
Some ideal applications are analog to digital converters,
precision voltage or current sources or precision power
supplies. Further, in many cases, the LM3999 can
replace references in existing equipment with a minimum of wiring changes.
The LM3999 is a precision, temperature-stabilized
monolithic' zener offering temperature coefficients
a factor of ten better than high quality reference zeners.
Constructed on a single monolithic chip is a temperature
stabilizer circuit and an active reference zener. The
active circuitry reduces the dynamic impedance of the
zener to about O.5.Q and allows the zener to operate
over 0.5 mA to 10 mA current range with essentially
no change in voltage or temperature coefficient. Further,
a new subsurface zener str\lcture gives low noise and
excellent long term stability compared to ordinary
monolithic zeners.
The LM3999 is packaged in a standard TO·92 package
and is rated from O°C to +70°C.
features
• Guaranteed 0.0005%fC 'temperature coefficient
•
The LM3999 reference is exceptionally easy to use
and free of the problems that are often experienced
with ordinary zeners. There is virtually no hysteresis in
reference voltage with temperature cycling. Also, the
LM3999 is free of voltage shifts due to stress on the
leads. Finally, since the unit is temperature stabilized,
warm up time is fast.
Low dynamic impedance - 0.5.Q
•
Initial tolerance on breakdown voltage - 5%
•
Sharp breakdown at 400llA
•. Wide operating current - 500llA to 10 mA .
• Wide supply range for temperature stabilizer
•
The LM3999 can be used in almost any application in
place of ordinary zeners with improved performance.
Low power for stabilization - 400 mW at 25°C
• : Long term stability - 20 ppm
.schematic diagram
Temperature Stabilizer
Reference
HEATER SUPPLY
~--'------'----~~------------------------~J v+
REFERENCE
Q1
2k
Zk
4.Z
Z.S'
3D'
1.
GND
.1 -
functional block diagram
typical applications
Basic Operation
9V TO 40V -
....._ - - - . ,
Rs
TEMPERATURE
STABILIZER
. S.9SV
LM3999
6·39
absolute maximum ra~ings
Te~peratu'r'e Stabil izer Voltage
Reverse Breakdown Current
Forward Current
Operating Temperature Range
Storage Temperature Range
Lead Temperattlre (Soldering. 10 seconds)
electrical characteristics
'\
36V
20mA
0.1 mA
O°C to +70°C
-SS"C to+1'SO°C
300°C
,
.
",
"
,. "
.,
,
;
" ,
:
"
,
I
,
"
(Note 1)
" ,
;(
.
"
CONDITIONS
PARAMETER
Reverse Breakdown Voltage
0.6 mA-::; IR -::; ~O mf\
Reverse Breakdown Voltage
Change With Cu;~e'nt. .
0.6 mA -::; I -::; 10 mA
MIN
.;.-
I
TVP
',"
6.6
MAX
,,
7.3
6.9S
,6
"
Reverse Dynamic Impedance
IR= 1 mA
Reverse Br~akdown Temperature
CoeffiCi'ent
0°C:::;TA:::;70°C
;
UNI,TS
V
.. 20
mV
'2.2
n
,0.6
0.0002
O.OOOS
%lC
;.;
RMS Noise
..
,7
10 Hz$f-::; 1() kHz
/lV
_
, Stabilized. 22"C < TA <
2It-C;-"
",
1000 Hburs. IR = 1 mA ±0.1%
Long Term Stabil ity
Temperature'Stab'ilizer
20
TA = 25°C; Still Air. VS;= 30V
.,
,
"
Initial Turn·on Current
"
.
9~
18.
ppm
.
rnA
\
"
\is -::;40. T,A'; 25°(;
,
36
,
,
'.
Vs ='30V.:TA = 2SOC
..
'
"
,
"
Warm·Up Time to O.OS%
.,
.. :' .. :
Temperature Stabilizer' Supply'
Voltage'
"
"12' '
V
,5,
"
Seeo'nds
206
140
inA
, No(e 1: Thes~ specifications apply for 30V ppplied to the temperature stabilizer and O°C 5. TA 5. +70°0, '''w •
.,
'.
':' ;
.
'.'
'
"
..
,
Reverse Cha.racteristics.
..,
'.
5
...
s,'
10- 2
",
~
."
~'.
15
0:
B10-3
~
J.;;'~ ~
w
~ 10-4
0:
V
. IU- 5
6,25
1
~
e
I
IT; • BU'CI'
6,65
6,85
3
ffi
~
2
1.U5
V
I
\
~
w
.
!!!
e
S;
lUU
50
10
"
lUO
,.
.'
,
.s...
-1
!;
-2
li:
STABILIZED ITj - B.O'C)":"
T;.'Z5'C·
I ,
I
-1~~'-5~C
j:
"...
':§
I '
I
".
,
I
I
,
1,k
10k
FREQUENCY 1Hz)
IUOk
0
VH ~ 15V
12
16
4
8
HEATER DN TIME -ISEC)
6·40
IUOk
Heater Current
e
-3
10k
FR~DUENCy I~~l
"
-4
,
lk
100
lU
80
TA .12S'C
~
Tj '25'C
0.1
10
I
'I'
;
0
~
8
,/"'
~
Stabiiization Time
,
15U
6
..
!
'1.0
REVERSE CURRENT ImA)
V~ltage ,',
Zener Noise
!
I
I
4
2
/'
STABILlZE~
IT; > BU'C)
"
".." '.
I
/'
U
J
, lU
"~co
~=25'C~
IP" i I '
REVERSE VDLTAGE IV)
2UU
w
,"
'.,.
ITi-9U;~ ~
STABILIZED
5
>
w'
a
,/
'6
'" .. '4'
~
~~BILIZED
6,45
Dynamic Impedance '1
.'
, ,'lUU
w
0:
"
. '.
""
,
,
"
ReveRe Voltage Change
.. ,s;'.
"
,
..
"
. '
typical performance characteristi~s,
Iu-l
'
20
,
~
~
~
...ffi
::l
'"
,6U
i'.
,I
1
~H'lUV
"J
,40
20
~
r... :-....
I~
-------,
Toi~~--...-----_
-------....J
______....- - -....
6-41
OTO -IOV
INPUT
SOUARE WAVE
s:
w
CO
CO
CO
typical applications (con't)
OV to 20V Power Reference
TO!~~---1----""--------""':-----'-'-------'
LM39SK
TEMPERATURE
STABILIZER
695V
LMJ999
-5V
Precision Clamp*
Bipolar Output Reference
CLAMP
INPUT
'5\
~-------<"""-OUTPUT
TEMPERATURE
STABILIZER
lN914
. I 5 V - -.....- - - - ,
OUTPUT
6.9V
5Ok~I---"I
695V
15k
-15V
LMJ9!19
JOpF
TEMPERATURE
STABILIZER
695V
INS1!!
lM3999
*Clamp will sink 5 rnA when input
goes more positive than reference.
Portable Calibrator*
connection diagram
-L
I
1ZVTO
-
Uk
1%
ZOOk
-
,...2.
~~
lM312
lBV-J
OUTPUT
>-- 10V
BOTTOM VIEW
1%
"r;"'.
Oider Number lM3999Z
See NS Package Z03A
6 95V"
lM3999
Jk
TRIM
Plastic Package
r:::l
'Z.:Y
51
m
] ;EMPERATURE
~ STABILIZER
/'
6
[1
*Warm-up time 10 seconds; intermittent operation
does not degrade long term stability.
6-42
Section 7
Analog Switches/
Multiplexers
•
~
I
...
/'
National
Analog
~ Semiconductor
~
Switches/Multiplexers
• Fully compatible with
These switches are particularly suited for use
. in both military and industrial applications such
as commutators in data acquisition systems, multiplexers, AID and O/A converters, long time
constant integrators, sample and hold circu its,
modulators/demodulators, ~nd other analog signal
switching ·applications. For information on other
National analog switches and analog interface· elements, see listing on last page_
The AH0014, AH0015 and AH0019 are specified
for operation over the _55°C to + 125°C military
temperature range. The AH0014C, AH0015C and
AH0019C are specified for operation over the
_25°C to +85°C temperature range. .
• LoiN ON resistance
• High OFF resistance
block and cOl'lnection diagrams
DPDT
Order Number AH0014D or AH0014CD
Sae NS Packaga D14A
QuadSPST
r--------l
AN"'~QG
It!
1111
I
I
DUll
AULaG
All:::
AIIALlla~""AlQG
"'lA~~~;~:~DG
MA~~~~:
,.
t
I: I
AULOI!
: DUl,
'NA~~'"
.u.UOG'
'
,
1 dAloa
: : f: a::~ao
11112
t~_~,i~~li~
LOile
Dual DPST
"l:~jD.~:-~
'Ii
.,..,....".uLAIII... l/i/l
,
on. or TTL logic
• Includes gating and level shifting
±10V
• Large analog voltage switching·
500ns
• Fast switching speed
• Operation over wide range of power supplies
I
la'
I
LI
__
~
,JCll ,.'Jel,
LOgiC la~lc u,~'c
AI
I
U!-VtC
__..Jl!...CND
A'
10;,IC LO::C
Nate: AlllDgic inputishown It tOlPe "1."
Order Numbar AH0015D or AH0015CD
Saa NS Package D14A
Gun
ill::::
fllfDIPandFlltpack.Alllogic
inputs shown It logic "1."
typical applications
Integrator
Reset Stabilized Amplifier
Your
'PreViously celled NHOO14/NHOO14C and NHOO19/NHOO19C
7-1
.
Notfl:Pinconnectionsarlidenticai
Order Number AH0019D or AH0019CD
See NS Package D14A
CO~
................
»
:r::r:
00
00
........
CO~
oS'
>
:r:
o
general description
features
00
99
AH0014/AH0014C DPDT TTLlDTL Compatible
MOS Analog Switches
AH0015/AH0015C Quad SPST TTL/DTL Compatible
MOS Analog Switches
AH0019/AH0019C Dual· DPST TTL/DTL Compatible
MOS Analog Switches
This series of TTLIDTL compatible MaS analog
switches feature higt) speed with internal level
shifting and driving.· The package contains two
monolithic ihtegrated: circu it chips: the MaS analog chip is similar to the MM450 type which
consists of four MaS analog switch transistors;
the second chip. is a·· bipolar I.C. gate and level
sh.ifter. The series is availal;lle in both hermetic
dual-in-line package and flatpack.
»
:r::r:
o....
en
........
»
:r:
o
9
01
S'
0
...
&n
....
8::J:
c(
......
&n
8
::J:
c(
.
.,
V cc Supply Voltage
v- Supply Voltage
'.
v+ Supply Voltage
V+IV- Voltage Differential
Logic Input Voltage
Storage Temperature Range
Operating TemperatUre Range
AHooI4. AHOOI5. AHoo19
AHOOI4C. AHoo15C, AHoo19C
Lead Temperature (Soldering, 10 seC)
:
"
absolute maximum ratings
.,
7.0V
-30V
+30V'
40V
5.5V
'-65°C·to +150~C
_55°C to +125°C
_25°C to +85°C
300°C
..
..
..
..
...
O(J
........
00
~O)
00
::J:::J:
c(c(
~(;;
........
88
::J:::J:
l>
:::J::::J:
analog switch characteristics
RON vs Temperature
125
V'N •
~
tou; .
100
w
u
z
~
~
~
15
50
V:N
-
.2
--
RON
]
,/
_IS"
25"
~
z
::i
50
...
0
25
IDS"
'" lOV
5
-15"
["or--.
~
w
~
~
0
z
z
.
-25
5
-50
w
2 fc'':';NEL "ON" r-CHANNEL "OFF"
V-· -20V
V-:: -lOV
1
-10 -8 -6 -4 -2 0+2+4+6 +8 +10
ANALOG
VIN
V' =+lDV
~
>
w
>
.~
t,
0
~
0
";iz
~
-15
0
0
r--
25'C
-5
-15
~
-20
-25
0
0.5
1.0
1.5
2.0
R,
'".
....
"
"~
' I,
,I
GV
lav
f
:
~""
I
I
~I
:
I
I
I
I
J
I
I
. . _:
r-.-1o.. -l
selecting power supply voltage
,
The graph shows the boundary conditions which
must be used for proper operation of the unit.
The range of operation for power supply V- is
shown on the X axis. It must be between -25V
and -avo The allowable range for power supply
v+ is governed by supply V-. With a value chosen
for V-, V+ may be selected as any value along a
vertical line passing through the V- value and
terminated by the boundaries qf the operating
region. A voltage difference between po.wer supplies of at /east 5V should be maintained for
adequate signal swing.
v-
7·3
~
V
-is
o
o.....
01
o
-55"C
2.5
INPUT VOL TAGE IVI
'~r::;'"
l>
:::J:
-10
',.-0-
DV
01
......
Vc~ = 5.0V
.,"':=::Jt-""'
'J
~"
'"
o
o
.....
V- ·-22V
V'· B.OV
Analog Switching Time Test Circuit
'" -f
l>
:::J:
IDS"
65"
125"C
IV)
AIlAUlIi
".
25"
+5
-10
Schematic (Single Driver Gate
and MOS Switch Shown)
..,... ~,
'" '"
;;;
r--.
VIN
-IS"
~
w
"
ANALOG
.... ....
Driyer Gate VIN YS VOUT
I'r---
(V)
OS>
./
+10
V-· NO EFFECT
+10
CO~
V
AMBIENT TEMPERATURE rCI
r--.
25
";2
./
150
100
-55"
25"
00
00
..........
V
125
IDS'
W
AMBIENT TEMPERATURE I'CI
50
CHANNEL "ON" CHANNEL "ON"v-", -20V
-V-·-OV
0
z
175
'"z
0
_55"
2
10
.
w
u
l>l>
:::J::::J:
200
Leakage V5 VIN (Channel "OFF")
~
I
CO~
............
V,~. Jour'· -1~V
t;
50
U
1/
~
15
"
,
/
15
z
CIN Y5 VIN
20
RON vs Temperature
225
_f-'"
u
AMBIENT TEMPERATURE I"cI
v~
~ou;· oJ
100
k
F
65"
•
Temperature
.2
~
f-""
25
0
-55"C
YS
125
+jov
00
00
..........
(Note 2)
.-15
V+
25
20
15
10
5
0
-5
-5
-10
-15
-20
-25 .
3.0
3.5
.......
o"'Itt/)
National
Analog
~ Semiconductor
~
"'(1)
0'-
J:a;
«CI)
.......
Switches/Multiplexers
AH0120/ AH0130/ AH0140/ AH0150/ AH0160
Series Analog Switches
00
MCO
,..
,..
00
genera I description
J:J:
..............
««
00
(\ILl)
,..
,..
The AH0100 series represents a complete fam ily
of junction FET analog switches. The inherent
flexibility of the family allows the designer to
tailor the device se"lection to the particular application. Switch configurations available include dual
DPST, dual SPST, DPDT, and SPDT. rds(ON) ranges
from 10 ohms th rough 100 ohms. The series is
available in both 14 lead flat pack and 14 lead
cavity DIP. Important design features include:
• TTL/DTL and RTL compatible logic inputs
• Up to 20V Pop analog input signal
• rds(ON) less than 10n (AH0140, AH0141,
AH0145, AH0146)
• Analog signals in excess of 1 MHz
• "OFF" power less than 1 mW
00
J:J:
««
• Gate to drain bleed resistors eliminated
• Fast switching, tON is typically 0.4 /lS, tOFF is
1.0/lS
• Operation from standard op amp supply voltages, ±15V, available (AH0150/AH0160 series)
• Pin compatible with the popular DG 100 series
The AH0100 series is designed to fulfill a wide
variety of analog switching applications induding
commutators, multiplexers, D/A converters, sample
and hold circuits, and modulators/demodulators.
The AH0100 series is guaranteed over the temperature range -55°C to +125°C; whereas, the
AH0100C series is guaranteed over the temperature
range -25°C to +85°C "
schematic diagrams
DUAL DPST and DUAL SPST
DPDT (diff.) and SPOT (diff.)
IN,
11
11
~
~
Note: Dotted line portions are not applicable to
Note: Dotted line portions are not applicable to
the dual SPST..
the SPOT (differentiall.
Order any of the devices below using the part number with a 0 or F suffix. See NS Packages D14A or F14A.
AH0133C. AH0134C, AH0151C, AH0152C available in N Package also.
logic and connection diagrams
DUAL SPST
DUAL ~PST
* Pinned out in N Package only_
,
y.
sw,
sw,
sw,
sw,
IN,
IN,
IN,
IN,
"
VRIENASLEJ
v-
HIGH LEVEL (±10V)
AH0140 (10n)
AH0129 (30n)
AH0126 (SOn)
MEDIUM LEVEL (±7.5V)
AH0153 (15n)
AH0154 (50n)
y.
"
"
DPDT (diff.)
SPOT (dill.)
y.
GATE 1-
y'
•
s,
"
"
.w,
.w,
sw,
IN,
IN,
VRlENABLE)
VR(ENABLE)
HIGH LEVEL (±10V)
AH0141 (1on)
AH0133 (30n)
AH0134 (SOn)
MEDIUM LEVEL (±7.5V)
AH0151 (15n)
AH0152 (50n)
y-
HIGH LEVEL (±10V)
AH0145 (10n)
AH0139 (30n.)
AH0142 (SOn)
MEDIUM LEVEL (±7.5V)
AH0163 (15n)
AH0164 (son)
7-4
c
"
VR IENA8LEJ
y-
HIGH LEVEL (±10V)
AH0146 (10n) ,
AH0144 (30n)
AHOl43 (Son)
MEDIUM LEVEL (±7:5V)
AH0161 (15n)
AH0162 (son)
absolute maximum ratings
High
Level
Medium
Level
34V
36V
Total Supply Voltage (V+ - V-I
25V
Analog Signal Voltage (V+ - V A or V A - V-I
30V
25V
25V
Positive Supply Voltage to Reference (V' - V RI
22V
22V
Negative Supply Voltage to Reference (V R - V-I
25V
25V
Positive Supply Voltage to Input (V+ - V,NI
±6V
±6V
Input Voltage to Reference (V ,N - VRI
±6V
±6V
Differential Input Voltage (V ,N - V ,N2 1
30 mA
30 mA
Input Current, Any Terminal
See Curve
Power Dissipation
-55°C to +125°C
Operating Temperature Range AH0100 Series
_25° C to +85° C
AH0100C Series
-65°C to +150°C
Storage Temperature, Range
300°C
Lead Temperature (Soldering, 10 secl
electrical characteristics
for "HIGH LEVEL" Switches (Note 11
DEVICE TYPE
PARAMETER
SYMBOL
DUAL
DPST
Logic ",'
Input Current
POSitiVI! Supply Current
SWitch ON
Negative Supply
Reference Input
IRION)
Positive Supply
Current SWl\ch OFF
Negative Supply
Current SWitch OFF
DPaT
(DIFF)
UNITS
v· '"
12.0V. V- '" -18
C,rcult~
av,
Nete 2
Ali Circuits
One Driver ON Note 2
Clrcul!~
One Driver ON Note 2
AI! ClrCUIIS
One Dnver ON Note 2
(S5°C for the AHOI OOC series. All typical values are for T A = 25°C .
Note 2: For the DPST and Dual DPST, the ON condition
i~
for "IN = 2.SV; th,e OFF condition
. is for VIN = o.av. For the differential sw.tches and SWI and 2 ON, V 1N2
For SW3 and 4 ON, VIN2 = 2.5V. VINI = 2.0V.
7-6
= 2.5V.
VINI
= 3.0V.
»
:::E::::E:
typical performance characteristics
Temperature
vs Temperature
100
2.4
laD
1"-
C 2.U
.!!
.......
I'...
~ 1.&
-
0:
z
.it
ii:
;g
0.8
0.4
F
r-
' - ~IONI
~
AHo129. AHo133.
A'1013~
=
~
z
"
125
rdslON) vs Temperature
AH0150/AH0160 Series
-75 -50 -25 0 25 50 75 I DO 125
TEMPERATURE {"CI
Leakage Current vs Temperature
Leakage Current vs Temperature
AH0120. AH0130. & AH0140
AH0150 & AH0160
o
.....
V· '" +12V
1000
.'oo~~
'"'"z~
~
i:i
0:
~
I I I
too
g
Z
~
v- • +15V
~:: i~55: +-+-+-+-+-1
~l.D
v-· -15V
AHo141.
' - AHo145. AHol46
AHo151.
~ AHo153. AHol61
o
~
....r-
"~
45
65
85
IDS
TEMPERATURE {'CI
125
25
B'!
!YIN' -
ALL SWlTCHek
O~ ~
I""'"
VIN21~ O.3~
0
"'"
z
,;
VR,.OY
V"-V-'JoV
-75 -50 -25
125
.......
~ ~
r- -
65
85
IDS
TEMPERATURE rCI
~
~L SWITCHES ON~~
~ b...
~
r- ALL ~WITCHES OFF
':;'L SWITCHES ON-
~ ;W
45
~
I
1,0
AHol54. AHoI52.AHol64. AHol62=
Differential Switch Input
Threshold vs Temperature
Threshold vs Temperature
!
J
y
0.1
25
Single Ended Switch' nput
9
A
-1.0
0.1
TEMPERATURE r'ci
Z
.
~ 10
"",I;oo~ EXCEPT AHo14o. AH~141.
!,..o
~ AHOI53.
AHo145. AHol46
Is -, rnA
1.0 L..:~~-1..-L_L-.L--L-I
-75 -50 -25 . 0 25 50 75 100 125
..ill
Vo OR Vs· :t:1.SV
.s 100
~ AHo14o.
-: 10
2.0
or '" +lSV
:<
Vo OR Vs" tl0V
.
10
..
1000
yo • 12.oV
or • -11.oV
AHol54. AHol52
AHol64. AHol62
25
50
-75 -50 -25
75 100 125
TEMPERATURE {"CI
0
25
50
75 100, 125
TEMPERATURE I'CI
switching time test circuits
Differential Input
Single Ended Input
'"
J"L
IV
'.
,~,,,,.,,,,.
.
,
IV
I
I.
I
,,,
--
"
V.. ,~·iV
IIW
.w.
...
.!!-it _
1
I
au,""
,
IITPU'
-au
~
I r
IV
III
am""
J
l
,
---'~r--
J
I
r
·'.1
I
1
--, 10" r-
,
'::'if":::
"I:
I
l
I
.v• . 1.
:
---,I_r--
7-7
!L-
"~ if'
: :.
J[
I
.IU
,
':'
cnw
-75 -50 -25 0 25 50 75 100 125
TEMPERATURE ("CI
vo'" 10V
ID '" 1 mA
V- • -18V
50
75
IDa
TEMPERATURE I' CI
00
..........
O~
(I»
CD:::E:
~·O
CD .....
r- I- ~IDNI
AHo14o. AHoI41..
_ AHo145. AHoI4~_
1.0
25
»
:::E::::E:
......
'"
V
10
~~
AHo143. AHo142.
AHoI2B. AHol34
.......
~
u
~ 1.2 r - I- r-IO~I
~
CIIN
. rdslON) vs Temperature
AH0120 thru AH0140 Series
ON SupplV Currant
Power Dissipation
VI
00
..........
I
r
I
--, 1011 ,......
tn~
applications information
1. INPUT'LOGIC COMPATIBILITY
terminal will open all switches. The VR,(ENABLE)
signal must be capable of rising to within O.8Vof
VINION) in the OFF state'and of sinking IR(ON)
milliamps in the ON state (at VIN(ON) - VR >
2.SV). The V R terminal can' be 'driven fr~m most
TTL and DTL gates.
.
,
3. DIFFE~ENTIAL INPUT CONSIDERATIONS:
A. Voltage Considerations
In general,. the AH0100 series is comp~tible with
most DTL, TTL, and RTL logic families, The ON·
input threshold is determined by the V BE of the
input transistor plus the V, of the diode in the
emitter leg: plus I x R 1, plus VR' ,At room
temperature and V R = OV, the nominal ON thres·
hold is: 0.7V+0.7V+0.2V,=.1 ,6V.Over temperature'
and manufacturing .tolerances, the threshold may
be as high as 2.SV and as low as 0.8V. The rules
for proper 'operation are:
. The differential switch driver is essentially a differ-,
ential amplifier. The input requirements for. proper
operation are:
IVIN1 - VIN21~ 0.3V
2.S -::; (V IN1 or VI~2):" V R -::; SV
VIN - V R ~ 2.SV All switches ON
VIN - V R ~ 0.8V All switches OFF
I~
.
l'he differential driver may be furnished by.a DC
level as shown below. l'he level mav"be derived
from Ii vo'itage divider to V+ or the 'SV Vee of
the DTL logic. In order to assure proper operation,
the divider should I;>e "sti,ff" with respect 'toIIN2'
Bypassing R1 with a 0.1 j.lF disc capacitor wili
'
prev'ent degradation of tON and t~FF'
II'
"
''''.'''.
~
y,~,
B.
...
Input Current Considerations
,~,
IINIONI, the current drawn by' the driver with
VIN -= 2.SV is typically 20 j.lA at 2SoC and is guar·
anteed less than 120 j.lA over temp~rature. 'DTL,
such as the DM930 series can supply 180 j.lA at
logic "1" voltages in excess of 2.SV. TTL output
levels are comparable at, 400 j.lA, The DTl and
TTL can drive the AH0100 series directly, However, at low temperature, DC noise m'argin in the
logic "1" state is eroded with DTL. A pull·up reo
sistor of 10 kS1 is recommended when using DTL
over military temperature range,
v.
l'V
,
Alternatively, the differential driver may be driven
from a TTL,flip-flop or inverter.
'~'"
a
OM~I:
Y'~I
___
v""
-
---
v.
If more than one driver is to be driven by a DM930
series (6K), gate, an external j:lull-up resistor should
be added. The value is' given by:
-=
11
Rp = N _ 1 for N > 2
~'
v,~,
+
__ _
-
---
v..,
'SDIoIr.t04
v.
y'
':"
V
Connection 'of a 1 mA current source between V R
and V- will allow operation over a ± 1 OV common
mode range. Differential input voltage must be less
than the 6V breakdown. and input thnishold of'
2.SV and 300mV differential overdrive still prevail.
where:
Rp = value of the pull-up resistor in kS1
N = number of drivers.
C. Input Slew Rate
The slew rate of the'logic input must be'in excess
of 0.3V Ij.ls in order to ,assure proPer operation of
the analog switc,h. DTL, TTL. and' RTl output
rise times are far in excess,of the mir:>imum'slew
rate requirements. Discrete logic designs. however.
should include consideration of input' rise time.
2. ENABLE CONTROL
The application of a positive signal at the V R
7-8
V A ~ V+ - VSAT - VSE - 1.0V or
4. ANALOG VOLTAGE CONSIDERATIONS
The rules for operating the AH01 00 series at
supply voltages other than those specified essen·
tially breakdown into OFF and ON considerations.
The OFF considerations are dictated by the maxi·
mum negative swing of the analog signal and the
pinch off of the JFET switch. In the OFF state,
the gate of the FET is at V- + VSE + VSAT or
about 1.0V above the V- potential. The maximum
V p of the FET switches is 7V. The most negative
analog voltage, V A, sWll1g which can be accomo·
elated for any given supply voltage is:
IV A I~ Iv-I- V p
-
V A ~ V+ - 2.0V or V+ ::: V A + 2.0V
For the standard high level switches, V A = 122.0V = +10V.
5. SWITCHING TRANSIENTS
Due to charge stored in the gate·to·source and
gate·to·drain capacitances of the FET switch, tran·
sients may appear in the output during switching.
This is ·particularly true during the OFF to ON
transition. The magnitude and duration of the
transient may be minimized by making source
and load impedance levels as small as practical.
VSE - VSAT or
Iv AI~IV-I-8.0 or IV-I?IV AI+8.0V
For the standard high level switches, VA <1- 181
+8 c: -10V. The value for V+ is dictated-by the
maximum positive swing of the analog input volt-
age. Essentially the collector to base junction of
the turn·on PNP must remain reversed biased for
all positive value of analog input voltage. The base
of the PNP is at V+ - VSAT - VSE or V+ - 1.0V.
The PNP's collector base junction should have at
least 1.0V reverse bias. Hence, the most positive
analog voltage swing which may be accommodated
for a given value of V+ is:
Furthermore, transients may be minimized by
operating the switches in the differential mode;
i.e., the charge delivered to the load during the
ON to OF F transition is, to a large" extent, can·
celled by the· OF F to ON transition.
typical applications
,Programmable One Amp Poyver Supply
,-_--'-''-4r-:; -
-;:"'~ ,
I.
"I
,I
;'<>-;~:'::::-::_=.:-:_=..-=,;;;l""',,-'V'oIv--+-'
"I i i
I
""71.-----.........,
I:', I ,: ' II
: I:
: I
I
1
I
I '
I :
I
I
!:
I
I
I
I
:
:
r
I
I
: I
:::~~:1=
,- --l
I
,O(ARlfI
.~."
l",.l",
~~.J""
'OJ
VOUT" (tPol."ty}_(BCDCOdl)_II RH
IQUT -2ApuIt,lAunl,nUQuS
lIo uT R.nft-,121i
FutrSulIAtqVIlIUonT'mII!-I,,1
Four to Ten Bit 0 to A Converter (4 Bits Shown)
AUlOG
(luuut
..
,'"
SettmgTime: 1 jlS
Acturacy:O.2%
"Note: AH rcsistonare 0.1%
7·9
......
o
~tn
typical applications (con't)
~Q.)
....
J:Q.)
Four Channel Differential Transducer Com'mutator
0'-
of the change of a paramelel
with the chanllt of a forcmg function.
.
Precision Long Time Constant I ntegrator with Reset
Analog Input Range - '1.5V
EOUl " lOx (Analog Input 2 - Analog Input 1)
Enor Rate - 0.01% F.S./sl'c
Four Channel Commutator
r--'!!".!!'!!!~ .....
I
I
I
:
. ,,:~,,~J~
'.~.~
·Note: Vas Idjust.d to zero
L_.r•.. ~.-1."'--r.I
....."" . --t+--t+---t........
Integration Internal = 10 sec
·Iotegration Error = IOO,N
Reset Time: 30J,is .
Analog Signal Range: 15Vp
Sample Rate: 1 MHz
Acquisition Time: 2DJis
Dllft Rate: 0.5 mV/sec
,
7-10
p
~National
Analog Switches/Multiplexers
~ Semiconductor
AH2114/AH2114C DPST Analog Switch
General Description
The AH2114 is a DPST analog switch circuit com·
prised of two junction FET switches and their
associated driver. The AH2114 is designed to fulfill
a wide variety of high level analog switching appli·
cations including multiplexers, A to D Converters,
integrators, and choppers. Design features include:
•
• Powered from standard op·amp supply voltages
of ±15V
•
jJ.S
The AH2114 is guaranteed ,over the temperature
range -55°C to +125°C whereas the AH2114C is
guaranteed over the temperature range O°C to
+85°C.
Low ON resistance, typically 75n
• High OFF resistance, typically lO 11 n
•
Input signals in excess of 1 MHz
• Turn·ON and turn·OFF times typically 1
Large output voltage swing, typically ±10V
Schematic and Connection Diagrams
Metal Can Package
'~,,--~------------~~~-+C:
"
CIfl:U'\'~
lOll(
.,
ShDWI'I
W,tbV5.. LDg,:"1"
ID8K
'.w
"
IOSK
,."
Order Number AH2114H or AH2114CH
See NS Package H 12C
AC Test Circuit and Wavefor~s
v, ...
'.w
L.._+_,..,
'.w
You?>
1-------.....,--1-"""'"
FIGURE 2,
FIGURE 1.
7·11
Absolute Maximum Ratings
Vplus SupplV Voltage
Vminus Supply Voltage
Vp/us-Vminus Differential Voltage
Logic Input Voltage
Power Dissipation (Note 3)
Operating Temperature Range
AH2114
AH2114C
+25V
-25V
40V
25V
1.36W
_55°C io +125°C
O°C to +8So C
_65°C to +125°C
300°C
Storage Temperature Range'
Lead Temperature (Soldering, 10 sec)
Electrical Characteristics
PARAMETER
Static Drain·Source
(Notes 1 and 2)
CONDITIONS
"On" Resistance
10 = 1.0 mA, VGS C OV, TA = 25°C
10 = 1.0mA, VGS = OV
Drain·Gate
Vos = 20V, Vas = -7V, TA = 25°C
AH2114
MIN
TYP
75
0.2
leakage Current
AH2114C
MAX
MIN
100
150
TYP
75
1.0
60
0.2
MAX
125
160
5.0
60
UNITS
n
n
nA
nA
FET Gate-Source
Breakdown Voltage
la = 1.O).lA
Vos = OV
Drain-Gate
VOG = 20V, Is = 0
1= 1.0 MHz, T A = 25°C
4.0
5.0
4.0
5.0
pF
Voa = 20V, 10 = 0
1= 1.0 MHz, T A = 25°C
4.0
5.0
4.0
5.0
pF
Capa~itance
Source-Gate
Capacitance
35
V
35
Input 1 Turn-ON Time
V ,N1 .~ 10V, T A" 25"'C
ISee Figure 11
Input.2 Turn-ON Ti,me
V ,N2 = 10V, T A - 25"'C
ISee Figure 11
1.2
1.5
1.2
1.2
).IS
Input 1 Turn-OFF Time V ,N1 = 10V, TA = 25°C
0.6
0.75'
0.6
0.75
).IS
35
60
35
60
ns
ISee Figure 11
Input 2 Turn·O~F Ti~e V ,N2 = 10V. TA = 25"'C
50
80
50
80
ns
ISee Figure 11
DC Voltage Range
TA = 25°C
ISee Figure 21
!9.0
±1O.0
±9.0
±10.0
V
AC Voltage Range
TA = 25'C
ISe. F.igure 21
±9.0
±10.0
±9.0
±10.0
V
Note 1: Unless otherwise specified these specifications apply for pin 12 connected to +15V, pin 2
connected to -1 5V, _55°C to 125°C for the AH21 14, and OoC to 85°C for the AH2114C.
Note 2: All
typical valu~s are lor TA = 25°C.
Note 3: Derate linearly at 10QoC/W above 25°C.
7-12
~National
Analog Switches/Multiplexers
~ Semiconductor
Monolithic N-Channel Junction FET Switches
with High Speed Drivers
AM181/AM281, AM 182/AM282
AM 184/AM284; AM 185/AM285
AM 187/AM287, AM188/AM288
AM 190/AM290, AM191/AM291
dual driver with SPST switches
dual driver with OPST switches
single driver with SPOT switches
dual driver with SPOT switches
General Description
These devices combine N-channel junction FETs and
bipolar transistors on a single chip for the first time in a
new N-channel Bi-FET process_
'
This technology provides the in9ustry's ot;lly low "ON"
resistance, high speed, m'onolithic N-channel junction
FET analog switch. Unique circuit techniques are
employed to achieve break-before-make switching action
and constant "ON" resistance over the analog voltage
range. The switch can block 20V peak-to-peak signals,
and because of the driver design, an "OFF" isolation
greater than 60 dB is achieved at 10 MHz.
Features
/
.
• Interfaces With standard DTL, TTL and CMOS
• Constant "ON" resistance with signals to ±,10V
Schemati'c Diagram
.:
• "ON" resistance match 2 n typ
• "OFF" isolation ahd crosstalk less than -60 dB at
10 MHz (typf ..
• tON/tOFF ~ 105 ns/95 ns typ
• Break-before-make action
Applications
• A-to-D/D-to-A converters
• Data acquisition
• Signal multiplexers
• Sample and hold
• Video switch
(Typical Channel)
'
l
SUBSTRATE
AlJplication Hints *
100
200
Series
Series
VIN
'VR
Logic Input
Vs
Vs
VL
Vee
VEE
Analog
Analog
Reference
Positive Negative
Logic
Volta,Ue
Supply Supply Supply
Supply
Signal
Voltage
VINHMinl
Voltage Voltage Voltage' Voltage VINLMaxRange
Range
(VI
(VI
(VI
(VI
(VI
(VI
(~I,
+15*·
-15
+5
Gnd
-7.5 to +15 -10 to +15
2.0/0.8
+10
-20
Gnd
2.0/0.8
-12.5 to +10 -15 to +10
..
... +5
+12
-12
+5
-4.5 to'+12 -7 to +12
Gnd
2.0/0.8
* Applications
Hints are for design aid only,
not guaranteed and not subject to production testing
**Electrical Parameter Chart based on Vee +
15V, VEE = -15V, VL = 5V, VR ~ Gnd
Absolute Maximum Ratings
VCC- VEE
VCc-Vo
Vo -VEE
VO-VS
VL-VEE
VL-VIN
VL-VR
VIN-VR
VR -VEE
VR -VIN
36V
33V
33V
±22V
36V
BV
8V
8V
27V
',2V
30mA
-,
Current (Any Terminal)
-Gsoe to +150°C
Storage Temperature
Operating Temperature,_
Power Dissipation *
Metal Can * * .
14-Pin DIP**~ .
-55°C to '+125°C
450mW
825mW
900mW
16.Pin Dlp·H!
• Ali leads soldered to PC board
Derate 6 mWfC above 75"C
Derate 11 'mWfC above 7SoC,
••• .- Derat~ ,12,mWfC above 7SoC
"
Connection Diagrams
AM18l/AM281. AM182/AM282'"
":
S1
.,
'12
NC
Metal Can Package
S.. NS Package HIDA
Order by Part Number
Followed by H Suffix
NC
ilL
INI
I.'
~cc
~u
vL
VII
Dual-In-Lina Package
S.e NS, Package D14A
Order by Part Number,
Followed by D Suffix '
TOPVI~W
Switch states are for logical lit" input
TOP VIEW ,',
AMl84/AM284. AM18S/AM28S'"
.,
NC
INI
, .3
14 "f:E
53
~
Dual-In-Line Packege
See NS Package D,16A
Order by Part Number
Foilo~ed by D SUffix:'
••
NC
"o----+=-..
•2
Switch states are for logical "0" input
TOPVIEW
AM187/AM287. AMl88/AM288'"
NC
.2
.,
NC
Matel Can Package
Sao NS Package Hl0A
Order by Part Number
Followed by H Suffix
Dual-In-Llne Package
See NS Package D14A
Ordar by Part Number
Followad by D Suffix
so
IN
IIcc
VL
VL
TOP VIEW
SWitch statas are for logical "I" input
"
AM110/AM21G. AM181/AM281'"
TOP VIEW
.,
~C
.3
'Dual-In-Lina Package
S .. NS Package D16A
Ordar by Part Number
Followed by D Suffix
S3
S4
••
NC
.2
TOP VIEW
Switch states are for logical "1" input
:;
'"Consult local sales representative or facto~ for information concerning the 14-pin flat package'
7-14
Electrical Characteristics AM1811 AM281, AM182/AM282
dc parameters are
100%
tested at
25°C;
ac parameters, high and low temperatures, and tON, tOFF are sampled to ensure
conformance with specifications.
-
Drain-Source
rOSION)
MAX LIMITS
TEST CONDITIONS. UNLESS NOTED:
PARAMETER
VCC· ISV. VEE = -ISV. VL = SV, VR = 0
IS -
10 mAo VIN - 0.8V
VO- 7.SV
UNITS
AM281
AM181
-5S"C
2S"C
12S"C
-20"C
2S"C
8S"C
30
30
60
SO
50
75
1
100
5
100
n
"ON" Resistance
ISIOFF)
Source "OFF"
Vs = 10V. Vo = -IOV.
Leakage Current
Vec = lOV. VEE = -20V
Vs - 7.5V. VD- 7.5V
1
100
5
100
Drain "OFF"
Vo = 10V. Vs = -lOV.
1
100
S
100
Leak 60 dB at 10 MHz TYPical, (Note 1 J
RL = 75 n
0.1
-5
0.1
-5
Both VIN '" 0, All Channels "ON"
4.S
-2
4.5
-2
mA
lEE
Negative Supply Current
IL
Logic Supply Current
IR
Reference Supply Current
0.1
-5
0.1
-S
Both VIN::: 5V, All Channels "OFF"
4.5
-2
Note 1: Typical values are for Design Aid only. not guaranteed and not subject to production testing.
-
7;15
4.S
-2
Electrical Characteristics AM184/AM284, AM185/AM285
dc parameters are 100% tested at 25°C; ac parameters, high and low temperatures, and tON, tOFF are sampled to ensure
conformance with specifications.
TEST CONDITIONS. UNLESS NOTED:
PARAMETER
VCC = 15V, VEE = -15V, VL = 5V, VR.= 0
IS=-10 mA, VIN = 2V VD = -7.5V
Drain-Source
rDS(ON)
,
MAX LIMITS
AM184
-55"C
25"C
AM284
UNITS
125"C
-20"C
25"C
85"C
30
60
50
50
75
1
100
5
100
1
100
5
100
1
100
5
100
1
100
5
100
-2
-200
-250
-250
10
20
30
n
ON Resistance
IS(OFF)
~
Source OFF
Vs
Leakage Current
VCC = 10V. VEE = -20V
10V, VD = -10V,
Vs = 7.5V, VD VIN = 0.8V
Drain OFF
ID(OFF) .
Leakage Current
7.5V
VD = 10V, Vs = -10V,
VD = 7.SV, Vs - -7.SV
ID(ON) + IS(ON)
IINL
nA
VCC = 10V, VEE = -20V
Channel ON
Leakage Current
VIN = 2V
Input Current, Input
VIN = 0
VD = Vs = -7.5V
-250
-250
-10
-200
-250
-250
10
20
Voltage I:-ow
p.A
IINH
Input Current, Input
tON
Turn ON Time
tOFF
Turn OFF Time
VIN ='5V
Voltage High
TEST CONDITIONS, UNLESS NOTED:
PARAMETER
VCC = 15V, VEE = -15V, VL = 5V, VR = 0
Drain-Source
rDS(ON)
I
See Switching Time Test Circuit
IS = -10V. VIN = 2V
150
180
130
150
ns
MAX LIMITS
AM185
-55"C 25"C
AM285
UNITS
125°C
-20°C
25"C
85"C
75
150
100
100
150
I
100 .
5
100
10V
I
100
5
100
VD = 10V, Vs = -IOV,
I
100
5
IDa
VD =-lOV
75
n
ON Resistance
IS(OFF)
Source OFF
Vs = 10V. VD = -IOV,
Leakage Current
VCC = 10V, VEE = -20V
Vs = 10V, VDVIN =O.8V
Drain OFF
ID(OFF)
leakage Current
VD - 10V, Vs - -IOV
ID(ON) + IS(ON)
VIN ~ 2V
Channel ON
nA
VCC = 10V, VEE = -20V
VD = Vs = -IOV
I
100
-2
-200
-250
-250
10
20
5
'100
-10
--200
-250
-250
10
20
Leakage Current
'IINL
Input Current, Input
-2S0
VIN =0
-250
Voltage Low
p.A
IINH
Input Current. Inpu"t
tON
Turn ON Time
tOFF
Turn OFF Time
V,N = 5V
Voltage High
See SWitching Time Test Circuit
TEST CONDITIONS, UNLESS NOTED:
PARAMETER
Vce = lSV, VEE = -15V, VL = 5V, VR = 0
eS(OFF)
Source OFF Capacitance
CD(OFF)
Drain OFF Capacitance
CD(ON) + CS(ON)
Channel ON Capacitance
ICC
Positive Supply Current
lEE
Negative Supply Current
IL
Logic Supply
IR
Reference Supply
"OF F" Isolation
~urrent
250
300
130
150
MAX LIMITS
AM184, AM185
-55"e
I 25"e
RL = 7S
125"e
AM284, AM285
I -20"e I 2Soe
VD = -5V, IS = 0
6 Typical, (Note 11
VD = Vs = a
14 TypIcal. (Note I)
pF
> 60 dB at 10 MHz TYPIcal: (Note 1)
n
0.1
-4
Both VIN = SV, All Channels "ON"
4.5
-2
0.1
-4
4.5
-2
Current
ICC
Positive Supply Current
lEE
Negative Supply Current
IL
Logic Supply Current
IR
Reference Supply
UNITS
85°C
9 TYPIcal, (Note 11
Vs = -5V, I D = 0
f= 1 MHz
ns
mA'
0.1.
0.1
-S.S.
-5.5
Both V,N = 0, All Channels "OFF"
4.5
-2
Current
Noto 1: Typical values are for Design Aid only. not guaranteed and not subject to production testing.
7-16
4.5
-2
Electrical Characteristics AM187 / AM287, AM188/AM288
dc parameters are 100% tested at 25°C; ac parameters, high and low temperatures, and tON, tOFF are sampled to ensure
conformance with specifications.
rOSION)
Drain·Source
IS =-10 rnA, VIN '" 2V. Ch. I "ON".
"ON" Resistance
VIN = 0.8V, Ch. 2 "ON"
Leakage Current
VIN = 2V, Ch. 2 "OFF"
VIN = O.BV. Ch. 1 "OFF"
Drain "OFF"
IOIOFF)
Leakage Current
IOION) + ISION)
Channel "ON"
Leakage Current
IINL
IINH
AM187
VCC = 15V. VEE = -15V. VL = 5V, VR = 0
Source "OFF"
ISIOFF)
MAX LIMITS
TEST CONOITIONS. UNLESS NOTED:
PARAMETER
VIN = 2V. Ch. 1 "ON"
VIN = 0.8V. Ch. 2 "ON"
Input Current. Input
Voltage Low
VIN = a
Input CUrrent, Input
VIN =SV
AM287
UNITS
-5SoC
25°C
12SoC
-20°C
25°C
8SoC
30
30
60
SO
50
75
Vs = 10V, Vo = -IOV,
VCC = 10V. VEE = -20V
1
100
5
100
Vs - 7.5V. Vo - -7.5V
1
100
5
100
Va = 10V. Vs = -10V.
VCC = 10V. VEE = -20V
1
100
5
100
Vo
1
100
5
100
-2
-200
-250
-250
10
20
Vo ==-7.SV
<:::
7.SV, VS=
7.SV
Vo = Vs = -7.5V
-10
-200
-250
-2S0
10
20
n
nA
i
-2S0
-250
~A
Voltage High
'ON
Turn "ON" TLme
'OFF
Turn "OFF" Time
180
150
ns
MAX LIMITS
TEST CONOITIONS, UNLESS NOTED:
PARAMETER
rOSION)
Drain-Source
IS = -10 mAo V,N = O.BV. Ch. 2
"ON" ReSistance
"ON". VIN
ISIOFF)
Source "OFF"
Leakage Current
IOCOFF)
Drain "OFF"
= 2V. Ch.
VO= -lOV
UNITS
125°C
-20°C
25°C
85°C
75
150
100
100
150
1
100
5
100
1
100
S
100
1
100
S
100
1
100
S
100
-2
-200
-2S0
-2S0
10
20
-5S"C
25°C
7S
n
1 "ON"
Vs = 10V. Vo = -lOV.
VCC = 10V. VEE = -20V
10V, VO=
10V
V,N = 0.8V. Ch. 1 "OFF"
Vs
V,N = 2V. Ch. 2 "OFF"
Vo = lOV. Vs = -lOV.
VCC = lOV. VEE = -20V
VO-l0V,VS- 10V
Leakage Current
IOION) + ISION)
AM288
AM188
VCC = 15V. VEE = -15V. VL = 5V, VR = a
IINL
ISO
130
See Switching Time Test Circuit
Channel "ON"
V,N = 2V. Ch. 1 "ON"
leakage Current
V,N = 0.8V. Ch. 2 "ON"
Input Current, Input
V'N=O
Vo = Vs = -10V
-250
-2S0
-10
-200
-2S0
-2S0
10
20
nA
Voltage Low
"NH
Input Current, Input
V,N = SV
-
Voltage High
tON
Turn "ON" Time
'OFF
Turn "OF;F" Time
2S0
300
130
150
os
See Switching Time Test Circuit
TEST CONOITIONS. UNLESS NOTEO:
PARAMETE~
VCC = ISV. \(EE= -lSV, VL = SV. VR = 0
CSIOFF)
Source "OFF" Capacltanc~
COIOFF)
oracn "OFF" Capacitance
"OFF" Isolation
Positive Supply Current
lEE
Negative Supply Current
MAX LIMITS
AM287, AM288
I
-5SoC I 2S~C I 125°C I-20°C 25°C 185°C
AM187, AM188
VS=-SV.IO=O
f= 1 MHz
VO' Vs
UNITS
9 Typical. (Note 11
pF
6 Typical, (Note 11
Vo = SV. 'S' a
COlON) + CSION) Channel "ON" Capacitance
ICC
~A
=a
14 Typical, (Note 11
> 60 dB at 10 MHz Typical. (Note 11
RL = 7Sn
0.1
-3
0.1
-3
VIN = O. Ch. 2 "ON", Ch. 1 "OFF"
'L
Logic Supply Current
IR
Reference Supply Current
ICC
Positive Supply Current
lEE
Negative Supply Current
'L
Logic Supply Current
IR
Reference Supply Current
3.2
-2
3.2
-2
mA
0.1
-3
0.1
-3
V,N = SV, Ch. 2 "OFF". Ch. 1 "ON"
3.2
-2
Noto 1: Typical values are for Design Aid only. not guaranteed and not subject to production testing.
7·17
3.2
-2
Electrical Characteristics AM1901 AM290, AM191/AM291
dc parameters are
100%
tested at
25°C;
ac parameters, high and low temperatures, and tON, tOFF are sampled to ensure
conformance with specifications.
TEST CONOITIONS, UNLESS NOTEO:
PARAMETER,
'OSIONI
ISIOFFI
MAX LIMITS
,
Vcc = 15V. VEE = -15V. VL = 5V, VR = 0
Draln·Source
Is=-lOmA, VIN=2V,Ch.l and2
ON Resistance
"ON", VIN = a.BV, Ch. 3and 4 "ON"
Vo = -7.5V
25"C
125"C
20"C
AM290
25"C
85"C
UNITS
30
30
60
50
50
75
Source OFF
Vs = liJV, Vo = -lOV,
1
100
5
100
Leakage Current
1
100
5
100
1
100
5
100
VIN = 2V. Ch. 3 and 4 "OFF"
VCC = 10V, VEE = -20V
Vs = 7.5V, Vo = -7.5V
Drain OFF
Leakage Current
VIN = 0.8V, Ch. 1 and 2 "OFF"
Vo = 10V, Vs = -lOV,
IOIONI + lSI aNI
Channel ON
VIN = 2V, Ch. 1 and 2 "ON"
Leakage Current
VIN = 0.8V, Ch. 3 and 4 "ON"
IINL
Input Current. Input
VIN = 0
IOIOFFI
-55"C
AM190
,
Vce = 10V. VEE = -20V
Vo - 7.5V, Vs - -7.5V
nA
,
Vo =' Vs = -7.5V
-250
1
100
-2
-200
-250
-250
10
20
5
-250
100
-10
-200
-250
-250
10
20
Voltage Low
pA
Input CUrrent. Input
IINH
n
VIN = 5V
Voltage High
'ON
Turn ON Time
'OFF
Turn OFF Time
180
130
150
ns
'OSIONI
VCC = 15V, VEE = -15V, VL = 5V, VR = 0
Drain-Source
IS=-10 rnA, VIN = O.BV. Ch. 3and
ON Resistance
4 "ON", VIN "" 2V, Ch. 1 and 2 "ON"
Source OFF
ISIOFFI
Drain OFF
,Leakage Current
IOIONI + ISIONI
Vo =-10V
-55"e
AM191
25"C
75
75
'VS = 10V, Vo = -lOV,
UNITS
125"C
200 e
AM291
25"e
85"C
150
100
100
150
1
100
5
100
VIN=-0.8V,Ch.1 and2"OFF"
VCC = lOV, VEE = -20V
Vs - 10V, Vo - -10V
1
100
5
100
VIN = 2V,.ch 3and 4 "OFF"
Vo = 10V, Vs = -10V,
1
100
5
100
5
100
leakage Current
IOIOFFI
MAX LIMITS
TEST CONDITIONS, UNLESS NOTED:
PAR'AMETER
IINL
150
See Switching Tlme Test CircuIt
VCC = 10V, VEE = -20V
Vo - 10V, Vs - -lOV
1
Channel ON
Leakage Current
VIN = 2V, Ch. 1 and 2 "ON"
Input Current, Input
VIN=O
VIN "" O.BV, Ch. 3 and 4 "ON"
n
nA
/
Vo = Vs = -lOV
-250
1
100
-2
-200
-250
-250
10
20
-250
-10
-200
-250
-250
10
20
Voltage Low
pA
IINH
Input Current, Input
VIN = 5V
Voltage High
'ON
Turn ON Time
'OFF
Turn OFF Time
\
See Switching Time Test Circuit
TEST CONDITIONS, UNLESS NOTED:
PARAMETER
CSIOFFI
Source OFF Capacitance
COIOFFI
Drain OFF Capacitance
VCC = 15V, VEE = -15V, VL = 5V, VR
"OFF" Isolation
Positive Supply Current
lEE
Negative Supply Current
IL
Logic Supply Current
IR
Reference Supply
ICC
Positive Supply Current
300
130
150
-55",C
AM290, AM291
25"C
I
UNITS
85"C
9 Typical, (Note 1)
6 TYPical, (Note 1!
Vo = VS=O
14 Typical, (Note 1)
pF
> 60 dB at 10 MHz Typical, (Note 1)
0.1
-5
=
~
I 25"C I 125"C I -20"C I
Vo = 5V, IS = 0
RL = 75 I!
Y,N
ns
MAX LIMITS
AM190, AM191
VS=-5V,IO=0
f= 1 MHz
COIONI + CSIONI . Channel ON Capacitance
ICC
=O·
'250
0, Ch. 3 and 4 "ON", Ch. 1 and 2 "OFF"
4.5
-2
0.1
-5
4.5
-2
Current
mA
lEE
Negative Supply Current
IL
Logic Supply Current
IR
Reference Supply
0.1
-5
VIN = 5V, Ch. 3 and 4 IIOFF", Ch. 1 and 2. "ON"
4.5
-2
Current
Note 1: Typical values are for Design Aid only, not guaranteed and not subject to production testing.
,
7-18
0.1
-5
4.5
-2
Typical Performance Characteristics
Vcc
= 15V, VEE =-15V, VL = 5V, VR =0 unless otherwise noted.
Typical delay, rise, fall, settling
times, and switching transients in
this circuit.
raSION) vs va anil
Capacitance vs V D or V S
Temperature
:;;
u
:i
~
~
i
2:
'
e
100
90
80 =VS--VA(MAXI
70 _IO"_IOmA ..
20
50
40
i--'"
3D
20
. . . r-
200 SERIES
....... ~';;;;IES
I---'"
-
.......
"
~,
g I~SS -3S -IS
~
-u
14
l3
10
.'"
w
12 I-
I
<:I,
1""-_
o
2S 45 65 85 IDS 12S
-
CS(ON) + CO(ONI
:t
2
S
VINL = O.BV
VINH = 2.0V
f=lMHz
IB
16
60
CS(OFFI
I
I- C~(OFtl
-10 -8 -6 -4 -2 0
T - TEMPERATURE f CI
2
4
6
B 10
Vo OR Vs - ORAIN OR SOURCE VOLTAGE (VI
If RGEN, R L or CL is increase~
there will be proportional in·
creases in rise and/or fall RC times.
Switching Time vs Vo and
Temperature
laIOFF) its Temperature
ISO
./
140
./
UO
1/
120
!w
";::
!
'ON (Vo = ±7.5~
110
100
I'
V 1/
V
~
P'
10
100
I-
tOFF.(VO = ±7.SVI_
90
80
1
~
~
10
F
1.0
""is
0.1
I
~
TEST LIMITS
VCC = 10V
.. 100SERIES
VEE = -20V
VL" 5V. VR "OV l - • 200 SERIES
Vo- -IOV
VS'IOV
E
0.01 I-'"
25
15
45
B5
65
. IDS
125
2
..
---
o
-
l-
I
f-~
It
VGEN=SV' \..
-2
1"1
1
!:;
e
:>
I-
IL
-I"1"-_
to...
0
'"
-IINL
II
IINH
1\
VGEN = 10V "-
-5
?!
w
12
"
I
f-~
SupplV Current vs Temperature
14
I.,.....
LOGIC INPUT
10
16
.... ....
I
1\
20
VINL = OV
VINH = 5V
IB
I-
,
l- I- r-IOO SERIES I '
20
10
g
T - TEMPERATURE eel
liN vs VIN and Temperature
~
~
!!!,
.......
:>
'" -2
T - TEMPERATURE (OCI
I-
'"
'"u
;;
e
50
-.55 -35 -IS 5 25 45 65 B5 105 125
..;;
I-
~
60
"is
?!
-lEE
-IR
-
-
r- r-.;.
'"~
,
e
e
:>
"
0
-2
~
2
.I
I
-2
ICC
1\
f- -VGEN =0
-4
f-""
I .
-4
-55 -35 -15 5' 25 45 65 85 IDS 125.
T - TEMPERATURE ('CI
. -55 -35 -IS 5 25 45 65' 85 105 125
T - TEMPERATURE ('CI
-6
f-
VGEN = -5V
cB
10
5
UOFF" Isolation vs
Frequency
Equivalent "OFF", ~ircuit .'
100
90
;
"e
BO
,11!
40
f'
20
30
10
J
;'
I
/VGEN.= -IOV0.4
0.8·· 1.2
t-
60
50
~
~
i"'"
10
3
-S
-10
-IS
VCC = 15V
VEE = -15V
VR =0
VL = 5V
RL = 1511
VIN 2:: 2Z0 mVrms
1'11111111
II
f - FREQUENCY (H.I
7·19
TIME ("51 •
1.6
Switching Time Test Circuit
Switch output waveform shown for Vs =constant with
logic input waveform as shown. Note that Vs may be +
state output with switch "ON". Feedthrough via gate
capacitance may result in spikes at leading and trailing
edge of output waveform.
or - as per switching time test circuit .. Va is the steady
LOGIC
INPUT
a...-+-c:~~......~VO SWITCH
tr
< 10ns
If"lOns
OUTPUT
JV
o--+'_____J
~~~~; vs--t::::--;;====~~--tON. Vs = 3V
tOFF. Vs = -3V
RL
VO=Vs
RL +rDS(ON)
(Repeat test for IN2 and S2)
Logic '''0'' = SW. "ON"
Typical Applications
Low Drift.compansatad Sa,!,pla and Hold
A2
. 5k
Cl
1500pF
AMI81
Al
5k
'IN
SI
A3
Uk
52
.,..
•
•
•
•
•.
•
•
Input impedance S kn
Slaw rate limiting and 3 dB point: 20V swing: 3:2K C; SV swing: 12K C; small signal: 21 K C
Droop rate @ 2S" C O.S nV per IlS
Sample to hold offoet adjustable to zero
Acqu ioition tlme-9S IlS
Aperture time-SO ns
Aperture uncertainty-2 ns
Video Switch with Very High "OFF" Isolation .
(f = de to 10 MHz)
OUTPUT
.....--'--+---....-+---CAMEAA 1 SELECT
CAMERA 2 SELECT
•
•
•
116 dB isolation at 10 MHz, "OFF" camera to "ON" camera
98 dB Isolation at 10 MHz. load from each camara whon both camerasar. "OFF"
".. < 1 dB on insertion loss
7·20
Typical Applications
(Continued)
A l6·Channel Data Acquisition Unit with Second Level Multiplexing
Ir---~--~-----------,
. .
I
15V
I , vI
-15V
I
I
I
I
I
I
,.
I
I
I'
I
I
I
I
I
I
I
S2·1
I
~--------
----~~~~
r--------
--:------,
.
I
I
Qce
I
I
I
I
I
I
LSBo.~==.
I
I
Ms80':'===+----......
3.9M
I
I
I
I
I
I
I
I
I
I
O.Dl,uF":"
I
·
':"
I
L ______
_
_ _ _ _•_8-811
_S.A.
_AID
15V_ _
-1
5_
V_
. _
10
DM25D2
ISV
ISV
5V
-ISV
~
•
•
•
•
•
~
Maximum A/D clock frequency: 4.5 MHz
Maximum throughput rate: 31.25k samples/sec.
Minimum switch·"ON" time for the 2·channel MUX: tON (min) 51/4.5 MHz.
Maximum input signal bandwidth 15.6 kHz
Maximum input signal variation during conversion for B·bit accuracy and 10V full scale: a V I N/ aT = 19.5 mV /p.s
Timing Diagram
eLK
f-
S2---'I
AD
I
-
I
r
I
I
I
AI
I
.,
A2
AO
r
"
I
I
r--;- u
1b
U
2.
U
"
U
7·21
,.
U
"
.~ U
I
4b
J?'A National
Analog Switches/Multiplexers
~ Semiconductor
AM2009/AM200~C, MM4504/MM5504
6-Channel MOS Multiplex Switches
General Description
The AM2009/ AM2009C/MM4504/MM5504 are designed for applications such as time division multiplexing of analog or digital signals. Switching
speeds are primarly determined by conditions
external to the device ·s·uch as signal source impedance, capacitive loading and the total n'umber of
channels used in parallel.
The AM2009/ AM2009C/MM4504/MM5504 are six
channel multiplex switches constructed on a single
silicon chip using low threshold P-channel MOS
·process. The gate of each MOS device is protected
by a diode circuit.
Features
•
•
•
•
•
150n
100 pA
Typical low "on" resistance
Typical low "off" leakage
Typicallarge·analog voltage range
Zero inherent offset voltage
Normally off with zero gate voltage
The AM2009/MM4504 are specified for oper-ation
over the -55°C to +125°C military temperature
range. The AM2009C/MM5504 are specified for
operation over the -25°C to +85°C temperature
range.
iiov
Schematic Diagrams
..
"
if
~t-
~t-
~
~"
~"
..
Pin numbers ill
parenthsslSlpply
far th! MM45D4J
J.,:
MM55D4 onlv.
~
"
~
~
~
"
f.!.o '"
SOURCE
1:
>--
"
J.,:
,
,
,
,
.
,
~
. .
.J..,
Order Number
Order Number
AM2009F or AM2009CF
AM2009D or AM2009CD
MM4504F or MM5540F
MM4504D or MM5504D
S•• NS Packag. F14A ,
Se. NS Pack_ D14A
Order Numb.r AM2009CN
orMM4504CN
S•• NS PaCkage N14A
Typical Applications
INPUT
CHANNELS
ANALOG INPUTS
AMZOOIfAM2DIIIIC
MM4504AtMS!i04
AM2009JAMZ009C
ANALOG
MM4504IMM5504
OUTPUT
ANALOG
OUTPUT
ADDRESSSElECT
,-I
.ll,DORESSSELECT'
32 Channel MUX
TTL Compatible 6 Channel MUX
7-22
1-1Z
Absolute Maximum Ratings
l>
(V BULK = OV)
Source or Drain Current
Gate Current (forward
~irection
Total Power Dissipation lat J A' = 2Soc)
Power Dissipation - each gate circuit
Operating Temperature Range AM2009
AM2009C
Storage Temperature Range,
-30V
-35V
+0.3V
SOmA
0.1 mA
Voltage on Any Source or Dram
Voltage on Any Gate
PositIve Voltage on Any Pin
of zener ciampI
900mW
150mW
-5SoC to +12SoC
-25'C to +85'C
-65'C to +150'C
300'C
Lead Temperature (Solderiag, 10 sec)
Electrical Characteristics
(Note 1)'
CONDITIONS
MIN
Threshold Voltage
VGs::: Vos. los'" -1 JJA
DC ON Resistance
V GS = -20V, los = -100
T A = 2SOC
DC ON ReSistance
DC O'N ReSistance
V GS = -20V, los'=
DC ON ReSistance
V GS = -IOV, V SB = -20V,
los = -100 ~A
Gate Leakage
VGs::: -20V. Note 2
Input Leakage
Output Leakage
-3,0
250
n
500
1250
n
n
-100~A
325
Vos = -20V. Note 2
Vos = -20V. Note 2, TA = 2S"C
100
Vso = -20V. Note 2
Vso = -20V, Note 2, T A = 25' C
Source·Draln Breakdown
Voltage
Drain-Source Breakdown
Voltage
s:
s:
CJ1
pA
1.0
~A
3.0
~A
pA
500
-10 IJ.A. Note 2
CJ1
o
~
......
~A
1.0
CJ1
o
~
pA
, -35
V
Iso": -10 p.A. VGO = 0,
Note 2
-30
V
los:: -lOp.A. VGS
Note 2
-30
= D.
V
Transconductance
4000
mhos
Gate Capacitance
Note 3, f = , MHz
4.7
8
pF
Input Capacitance
Note 3, f = , MHl
4.6
8
pF
Output Capacitance
Note 3, f = 1 MHz
20
pF
16
Note 1: Ratings apply over the specified temperature range and VBULK = 0, unless otherwise specified.
Noto 2: All other pins grounded.
Note 3: Capacitance measured on dual-in-line package between pin under measurement to all other pins. Capacitances are
guaranteed by design.
Typical Performance Characteristics
"ON" Resistance vs Gate-toSource Voltage
700
"ON"' Resistance vs T
Temperature
."'T"-,"'T"-,r-.....-.
40.
I
1~
•-3.
(
I
-25
-20
-15
Vos(V1
-10
.
-
§
300
}
'".
100
•
Input Leakage Current vs
Temperature
vV
50'
.
BOD r-~:s =z~!~DpA-+_+--II_-I
.....-V
.....- "-;;.,--tl
V: V
- kfit·f=
•-so
""""
-25
•
25
so
75
TEMPERATURE n)
7·23
~ 10,OGD
S
j"",ov
100
125
~
1000
~
100
;=
1D
o
25
50
l>
s:
N
s:
s:
~
n
1500
100
1GB =
V
150
V GS = -20V, Note 2, TA = 2SOC
Gate-Bulk Breakdown
Voltage
MAX
~A,
V GS = -10V, V SB = -20V,
'os::: -100 p,A, TA = 2SOC
)
UNITS
TYP
-1.0
o
o
CO
......
o
o
CO
51
LIMITS
PARAMETER
s:
N
75
TEMPERATURE
100
rei
125
~National
'
~ Semiconductor-
Analog Switches/Multiplexers·
AM370S/ AM370SC: a-Channel MOS Analog Multiplexer
General Description
The AM3705/AM3705C is an eight-channel MOS
analog multiplex switch. TTL. compatible logic
inputs tha.t require no level. shifting or input
pull-up res'istorsand operation over a wide range
of supply voltages is obtained by constructing the
device with low threshold P-channel enhancement
MOS technology. To simplify external logic requirements, a one.of:eight decoder and an output
enable are included in the device.
• Low ON resistance - 15012
• Input gate protection
.• Low leakage currents .- 0.5. nA
The AM3705/AM3705C is designed as a low cost
analog multiplex switch to fulfill a wide variety of
data acquisition and data distribution applications
including cross-point switching, MUX front ends
for AID converters, process controllers, autqmatic
test gear, programmable power supplies and other
military or industrial instrumentation applications_ .
Important design features include:
•
•
•
•
•
TTLlDTL compatible input logic levels
Operation from standard+5Vand-15Vsupplies
Wide analog voltage range - ±5V
One-of-eight decoder on chip
Output enable control
The AM3705 is specified for operation over the
_55°C to +125°C military· temperature range. The
AM3705C is specified for operation over the _25°C
to +85°C temperature range.
Schematic and Connection Diagrams
-------•
,.
..
r
Dual-I n-Line Package
'"
Va Z
"
2'
15
z'
.. "I'
OUT ,
...
13
Vn •
¥DD
12 $,
II
S, •
S,
,.
.. 7
"
s,a
S,
TO' VIEW
Order Number
AM3705D or AM3705CD
See NS Package D16A
Order Number
. AM3705F or AM3705CF
See NS Package F16A
Block Diagram
Truth Table
(MIL-STD-806Bl
CHANNEL
lOGIC INPUTS
. OATAtNPUT
CHANNEL NO:S
Lhhhhhhh
OOATAOUTrUT.
t'
. 2'
L
H
'L
H
L
H
L
H
L
L
H
H
L
L
H
H
X
X
2'
L
L
L'
L
H
H
H
'If
X
:OE
ON
H
H
's,
H '
H
H
H
H
H
.L
5,
5,
5,
S,
S,
5,
S,
OFF
Typical Application
(
Buffered B-Channel Muhiplex, Sample and Hold
~-------
LOGIC INPUT
Anllol Signal A.n" - O.SV
AcquiSition Time - 26 ItS
D,jh A,t. - U mV/llc
Aperltur, Time - 250 III
-BothVss lmnl'lIlnternllly
connlcted;litheronlo,
lIothmaylt.used.
7-24
»
s:
Absolute. Maximum Ratings
Positive Voltage on Any Pin (Note 1)
Negative Voltage on Any Pin (Note 1)
w
.....
o
+0.3V
-3SV
±30mA
iO.l rnA
SOOmW
-SS·C to +12S·C
-2S·C to +8S·C
-6S·C to +IS0·C
300·C
Source to Drain Current
Logic I"put Cu~rent
Power Dissipation (Note 2)
Operating Temperature Range AM370S
AM370SC
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
01
.........
»
s:
w
.....
o
01
o
Electrical Characteristics
PARAMETER
(Note 3)
SYMBOL
CONDITIONS
MIN
= Vss: lOUT = 100/lA
=-100/lA
Y'N = -SV; lOUT = -100/lA
ON Resistance
RON
Y'N
ON Resistance
RON
Y'N = -SV: lOUT
ON ReSIstance
RON
LIMITS
TYP
MAX
250
160
400
n
n
400
400
n
n
TA=+12S~C
AM370S
AM370SC
= +70·C·
Y'N = +SV; VOO = -ISV;
lOUT = 10Q /lA
TA
ON Resistance
RON
ON ReSistance
RON
Y,N = OV. Vee = -ISV.
lOUT = -100 /lA
ON Resistance
RON
Y'N = -SV; Vee
lOUT = -100/lA
OFF Resistance
ROFF
Output Leakage Current
I LO
I LO
I LO
AM370S
AM370SC
Data Input Leakage Current
AM370S
AM370SC
'LO"
I lOI
'lOI
Logic Input Leakage Current
AM370S
AM370SC
. 'Ll
ILl
ILl
,
100
n
150
n
2S0
n
n
=-ISV;
10'0
O.S
ISO
3S
Vss - V OUT = 15V
Vss - V OUT = ISV; T A = 12S"C
Vss - V OUT = ISV; TA = 70·C
Vss - Y'N
Vss - Y,N
Vss - Y'N
= ISV
= ISV; TA = 12S·C
= ISV; TA = 70·e
Vss - VL091C In
VSS - VL09lC In
=
=
15V
15V; TA "" 12S D C
VSS - VL091C In
=
15V; TA
=
0.1
2S
O.S
.001
.05
.05
70°C
= +S.OV
UNITS
80
10
SOO
SOO
nA
nA
nA
3.0
SOO
500
nA
nA
nA
1
10
10
pA
pA
pA
1.0
V,L
Logic Input LOW Level
Logic Input HIGH Level
Logic Input HIGH Level
V,L
V,H
Vss = +S.OV
Channel Switching Time-Positive
V'H
t+
1SwitchIOg Time
300
Channel Switching Time.N~gative
I
J Test
600
ns
62
dB
35
pF
Channel Separation
-
,
OulPUI Capacitance
Vss
f
Cdb
0.5
V
Logic Input LOW Level
Veo
3.0
Vss - 2.0
Circuit
= 1 kHz
= 1 MHz
= 1 MHz
Vss - VOUT = 0; f
Data I nput Capacitance
C",
Logic Input Capacitance
Co.
Vss - V Logic In = 0; f = 1 MHz
Power Dissipation
Pe
Voo
Vss - V OIP = 0; f
= -31V. Vss = OV
I
Vss - 4.0
3.5
Vss + 0.3
ns
pF
6.0
6.0
125
V
V
V
pF
175
mW
Note 1: All voltages referenced to VSS.
Note 2: Ratings applies for ambient temperatures to +2SoC, derate linearly at 3 mW/oC for ambient temperat~re5 above +2SoC.
Note 3: Specifications apply for TA = 2S·C. -24V
:c:;
VDD
:c:; -20V.
(all voltages are referenced to ground).
7-25
and +S.OV S; VSS S; +7.0V; unless otherwise specified
.
Typical Performance Characteristics
ON Resistance vs Analog
Input Voltage
300
~ITElT
250
ON Resistance vs
Ambient Tempetature
VDO '" -lOV
.00
r- Vss ' +7V
!OIiT
TA =+25"C .
lOUT'"
200
350
-100 p.A
.:; 150
100
Vss=t7V
-3
-1 '0 +1
+3
+5
0
25
50
TEMPERATURE
VOlT
.........
'+5·rV
Vour '
I
-5,~V-
"""I.
~:-o....
VOUT=~.oV- f--
75 100 125
-10
,-IS
rei
-20
-25
Voo SUPPLY (VI
Switching Time Test Circuit
Output Leakage Current vs
Ambient Temperature
~VOUT
.......
I
\.
\.
fT111
INPUT (VI
10'
........
50
V1NPUY = +7V
-75 -50 -25
+1
100
JL
o
-5
.i
1'1
50
o
.s; 150
V1NPUT "' -sV
100
50
'\..
200
ff
'i
TA , 25'e
Vss "+5V
IpuT· -1DOIolA
z;o
~lH
T~~N
lOUT'" -10o.A
'" 250
200
o
a:~ 150
TEST POINT'"
i"-r-.
.i
\
I. '-' I
Voo '" -ZOV
300
I 1/ I
ON Resistance VI VOD
Supply Voltage ,
Vss -15V
-
""-
. . s··
TEST PO'INTS ~
.~
./
~
_
'~.4Y---
V
,25
50
v..,.-I.
,75
100
,
"
125
TEMPERATURE ( e)
Typical Applications
(Continued)
Differe~tiallnput
MUX
16·Channel Commutator
. [
" ,""
CII. .'U
"
.
"M
m,"""[
VolllgeGain"'2DO
Dlff8JtntiallnputRHistallce z 10io n
eMRR" 100dB
InputCurrtnt.,O,5nA .
SoChannel
Demultiple"e~
,!"ith Sample and Hold
Wide Input Range Analog Switch
,.~
7·26
An.IOJ Input R.nge - 25V
Slew Rltl - 5 Vlp.1
~National
Analog Switches/Multiplexers
~ Semiconductor
AM9709/ AM97C09/ AH5009 Series
Monolithic Analog Current Switches
General Description
A versatile family of monolithic JFET analog switches
designed to economically fulfill a wide variety of multiplexing and analog switching applications.
• Active filters'
• Signal multiplexers/demultiplexers
• Multiple channel AGC
• Quad compressors/expanders
• Choppers/demodulators
• Programmable gain amplifiers
• High impedance voltage buffer
Even numbered switches may be driven directly from
standard 5V logic, whereas the odd numbered switches
are intended for applications utilizing 10V or 15V logic.
The monolithic construction guarantees tight resistance
match and track.
• Sample and hold
The AM97C09 series is specifically intended to be driven
from CMOS providing the best performance at lowest
cost.
Features
• Interfaces with standard TTL and CMOS
2 ohms
• On-resistance match
100 ohms
• Low "ON" resistance
50 pA
• Very low leakage
±10V peak
• Large analog signal range
• High switching speed
150 ns
80 dB
• Excellent isolation between
channels
at 1 kHz
Applications
• AD/DA converters
• Micropower converters
• Industrial controllers
• Position controllers
• Data a~quisition
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
,.
14
"
"
15
11
13
10
12
14
11
"
TOPVIEW
TOP\lIEW
Order Number AM9711CN, AM9712CN, AM97C09CN,
AM97C10CN, AH5011CN, AH5012CN, AH5015CN
orAH5016CN
See NS Package N 16A
Order Number AM9:l09CN, AM9710CN, AM97C09CN,
AM97C10CN, AH5009CN, AH5010CN, AH5013CN
orAH5014CN
See NS Package N14A
Functional and Schematic Diagrams
MUX Switches
14-Channel Version Shown I
SPST Switches
(Quad Version Shown)
(Additional type on other pages)
SPST Switches
(Quad Version Shown)
MUX Switches
(4-Channel Version Shown)
COMPENSATING FET
DIs
J~"----ol
I
20---..1
6~"----o'
I
* 0---1~--'
J*o--~----'
4
5*0--~--'
5*o-~~--'
70---...1
11~.&....-......o9
I
10O---.J
14
0---0"(~16
15o---.J
,,"o--t-----'
16
*Note: All diode cathodes are internally connected
to the substrate.
,,* 0-___
>__--'
13*0-_~-'--'
14
CQMMON DRAINS
7-27
UNCOMMITTED DRAINS
...'"
.!
Absolute Maximum Ratings
Q)
en
CJ)
o
oIt)
::r:
Electrical Characteristics
s:
CO
(Continued)
.....
PARAMETER
'GSX
Input Current "OFF"
CONDITIONS
V GO ~ l1V. Vso: 0.7V
T A: 8S"C
lSV TTL
lSV TTL
10-lSV CMOS
AM9709CN
AM9711CN
AHSOO9-1S
(ODD SERIES)
AM97C09CN
AM97CllCN
TYP
MAX
TYP
MAX
0.01
2
100
0.01
0.2
TYP
o
UNITS
MAX
nA
nA
10
I Gsx
Input Cunent "OFF"
VGo: lSV. Vso : 0.7V
T A : 8S"C
0.01
2
nA
100
nA
'OIOFFI
Leakage Current "OFF"
Vso : 0.7V. VGS : 9.3V
0.01
2
nA
100
nA
'OIOFFI
Leakllge Current "OFF"
TA : 8S"C
'GION)
Leakage Current "ON"
Vso: 0.7V. VGS : 1O.3V
TA : 8S"C
0.01
Vco :OV.ls: 1 mA
0.04
'GlON)
Leakage Current "ON"
Leakage Current "ON"
ReSistance
0.01
10
TA :8S"C
IG!oNI
2
0.5
0.04
0.07
V GO :OV, Is :-2mA
TA :8S"C
O.OS
nA
10
nA
0.5
2
2
1
2
S
100
2
20
Drtlin-Source
rOSIONl
Dram-Source Resistance
VGs: 1.5V, Is =2mA
TA = 8SoC
VOIODE
Forward Diode Drop
10 '= O.S mA
rOSION)
Match
V GS = 0, 10 : 1 mA
TA
=:
0.07
O.OS
60
Vcs: OV• ls=2mA
raS(ON)
0.04
100
100
V GO :OV.ls :2mA
T A: 8S"C
0.2
0.5
nA
100
nA
2
nA
1
/lA
5
nA
2
/lA
100
160
85°C
60
100
60 .
160
100
160
0.8
2
10
SO
2·
n
n
n
n
0.8
V
10
n
TON
Turn "ON" Time
See ac Test C.rcult
150
500
'150
500
150
SOD
ns
T OFF
Turn "OFF" Time
See ac Test Circuit
300
500
300
500
300
500
n,
CT
Cross Talk
See ac Test Circuit
120
7·29
120
120
dB
.!D
J>
s:
CO
.....
o
o
.!D
J>
:t:
01
o
o
CO
en
(I)
...
CD'
t/)
t/)
Q)
'':;
Schematic Diagrams and Pin Connections
Q)
FO!;lr Channel
U)
AM97C09CN (ROS(ON)
AM97Cl0CN (ROS(ON)
AM9709CN, AHS009CN
AM9710CN, AHSD1DCN
0)
o
o
It)
:'> lOon, 10-lSV CMOS)
:'> lson, S-10V CMOS) .
(ROS(ON) :'> loon, lSV TTL)
(ROS(ON) :'> lson, SV TTL)
AM97CllCN (ROS(ON):'> 100n,10-15VCMOS)
AM97C12CN (ROS(ON) :'> 150n, 5-1DV CMOS)
AM9711CN, AH5DllCN (ROS(ON):'> loon, lSV TTL) •
AM9712CN, AHSD12CN (ROS(ON) :'> lson, 5V TTL)
J:
loon, lSV TTL)
AHSOl4CN (ROS(ON) :'> 150n, 5V TTL)
AH5015CN (ROS(ON) :'> loon, lSV TTL)
AHSOl6CN (ROS(ON) :'> 150n, SV TTL)
.---.....---011
11
10 o---~---------I
0----<.---.,
12 O--~-----'
14·Pin OIP
16·Pin OIP
Test Circuits and Switching Time Waveforms
Cross Talk Test Circuit
ae TesfCircuit
+15V
"~
10k
·'E1
VA. s±10V
10k
VOUT
v"
7-30
16
Typical Performance Characteristics
Leakage Current, IO(OFFI
vs Temperature
Parameter Interaction
1000
-u"e
..........Z
~z
200
f3~
a:= 100
10k
VOSIOFFI@VDS = -15V, 10 = -1 nA
fOS @Io '" -1 mAo Viis = OV
g'I@VOS = -15V, VGs " OV PULSED
w-
-g~
loss
10
kB
:e".
<:
"
~
~
9
.Ii
~~
10
Ves
u
~
a:
'"'"
10
'":l
z
~
"
25
100
;
-70
B
-60
-50
-40
-30
-20
'"
:l
25
35
45
~
-10
1.0
1M
75
.65
85
Transconductance vs
Drain Current
TA '" 25 C
VaG = -5V
-g
f; 1 kHz
!'.
...
.
u
10
..'"
55
TEMPERATURE I'CI
100
t:::f=
~
lOOk
~~ c~~s C~OS ~
'1ll\O.~~
,~~1
f- ~
25
100
~
10k
85
ID=-2m~
w
Ik
75
50
::;;;.:--
T. "25 C
....
~
a:
I"
100
65
1000
:<
.g.
-80
5
55
75
Leakage Current vs
Drain-Gate Voltage
:1
....
!1i
45
GATE SOURCE CUTOFF VOLTAGE IVI
t
..
35
100
TEMPERATURE I'CI
I'V." !10Y
....,-::
~~lll
o
10
Cross Talk, CT vs Frequencv
-120
-110
-100
-90
'"~
Eia:
/'
100
w
1.0
1.0
~
.!l
/'
Ik
z
~'"
-1 rnA
",
125
~
;;
1/
10
.g.
!
'os
20
ISO
:<
-<
"'"
V
za:
;;:"
a:
On Resistance, rOS(ONI
vs Temperature
'"g
10 =-1 mA_
~ID"~
1-1'
"'"
"~
'"~
~ss~
1
o
5.0
10
15
~ VGSIOFFI" 2V
J.1'.~
-1.0
DRAIN
DRA1N·GATE VOLTAGE IVI
FREQUENCY IHzl
VGSIOFFI"
~lliOFFI =7.5'1
1
-0.1
25
20
10
CU~RENT
5V
W
-10
ImA}
Normalized Drain
Drain Current vs Bias
Voltage
-25
1....
ill
a:
-20
1\
1\
-15
1\
=
B
;;:
'"
."=
-10
-5
Resistance vs Bias
Voltage
100
VDS
"
.'"
w
-IOV_
In
T."25C -
\
Eia:
,
\ 1\
\
1.0
l-
20 I-
:5
5.0
.
=
1= 1=1=1
'os
t_
VGS
VGS(OFFI
_L
'"
\ \. '\.
'" '"
t-rOSb
10
:ii
1\ 1\
50
.~
:;
"- f'-..
VGSIOFFI@-10V.-10iJA
u
t = 1 kHz
I
.!l
l'.
2.0
2.0
,....1-"' ~+'
1.0
o
3.0
GATE·SOURCE VOLTAGE IVI
0.2
0.4
0.6
0.8
1.0
NORMALIZED GATE·
TO·SOURCE VOLTAGE IVI
IVc;sIVc;SIOFFII-
Applications Information
Theory of Operation
·(AM97Cl01. open collector 15V TTL (AM97091. and
10-15V CMOS (AM97C09).
The AMIAH series of analog switches are primarily
intended for operation in current mode switch ·applica.
tions; i.e., the drains of the FET switch are held at or
near ground by operating into the summing junction of
an operational amplifier. Limiting the drain voltage to
under a few hundred millivolts eliminates the need for a
special gate driver, allOWing the switches to be driven
dir~ctlY by standard TTL (AM9710), 5V-l0V CMOS
Two basic s~itch configurations are available: multiple
independent switches (N by SPST) and multiple pole
switches used for multiplexing (NPST·MUX). The MUX
versions such as the AM9709 offer common drains and
include a series FET operated at VGS = OV. The addi·
tiona( FET is placed in feedback path in order to
compensate for the "ON" resistance of the switch FET
as shown in Figure 1.
7-31
tn
Q)
Applications Information
''::::
(Continued)
In a typical app,lication, V A might = ±10V, Ao =0.1%,
O°C ::; T A ::; 85°C. The criterion of equation (2b)
predicts:
The closed-loop gain of Figure 1 is:
Q)
(/)
R2 + 'OS(ONIQ2
0)
Rl + 'OS(ON)Ql
o
o
it)
For Rl
'OS'ONI
between
accuracy
:t
-<~--i+
'
FIGURE 1. Use of Compensation FET
FIGURE 2. On Leakage Current, IGIONI
7·32
.,
Applications Information
~
3:
(Continued)
TTL Compatibility
both cases, t(OFF) is improved for lower values of R EXT
and the expense of power dissipation in the low state.
Two input logic drive versions of AM/AH series are
available: the even numbered. part types are specified·to
be driven from standard 5V-TTL logic and the odd
numbered types from 15V open collector TTL,.
The cost effective AM97C09 series of switches is
optimized for CMOS drive without resistor pull-up. The
AM97Cl0's and AM97C12's are specified for 5V-l0V
operation while the AM97C09's and AM97Cll's are
specified for 10V-15Voperation_
Definition of Terms
The terms referred to in the electrical characteristics
tables are as defined in Figure 6_
Likewise, the open-collector, high voltage TTL outputs
should use a pull-up resistor as shown in Figure 5. In
~
o
...CO
CMOS Compatibility
Standard TTL gates pull-up to about 3.5V (no load).
In order to ensure turn-off of the even numbered switches
such as AM9710, a pull-up resistor, REXT , of at least
10 kn should be placed between the 5V Vee and the
gate output as sho~n in Figure 4.
CO
~
3:
CO
~
oo
...CO
~
:::c
U1
o
o
CO
en
..._.
CD
CD
AI
CJ)
FIGURE 3.
r--------,
,
.,
:
I
I
I
I
ANALOG
INPUT (VAl'
'5V
I
I
REXT
12k
T.
ANALOG
OUTPUT
10k)
I
,I
I
I
,
__ I
~"'!::~_~_..:.J
FIGURE 4. Interfacing with +5V TTL
+5VORt15V
ANALOG
INPUT (VA)
ANALOG
OUTPUT
LOGIC
INPUT
(V..I
FIGURE 5_ Interfacing with +15V Open Collector TTL
7-33
Applications Information
(Continued)
COMPENSATING
ELEMENT I
ROSIONJ
R,
R,
SHUNT ____
ELEMENT
FIGURE 6. Definition of Terms
Typical Applications
Gain I:'rogrammable Amplifier
10k
>"--e--o
EOUT
11
I
10k
I
I
I
lOOk
I
I
I
1M
I
I
I
I
13
10M
I
-.J CHARACTERISTICS
L_
GAIN -
-~I:UT ~
RF8
12
GAIN SELECT
3·Channel Multiplexer with Sample and Hold
10k
ANALOG
INPUTS
2r--AM97D9iAMrno----,
I
I
I
I
I
10k
CHARACTERISTICS: TYPICAL OUTPUT
VOLTAGE DRIFT
12
I
SAMPLE/HOLD
SELECT
<5mV/SlI:
CHANNEL
SelECT
7·34
Typical Applications
(Continued)
16-Channel Multiplexer
I
"I
E'",3 o--'IIII-"':':'~"""--,
I
I
I
141
EIN4
0-""",..:..:.;...........--,
II""
I
I,
I
I,
13
l>
:::t
I"
CJ1
I
o
o
15 _ -1I
'-____
CD
EINS
en
..._.
CD
EING
CD
CJ)
EIN1
EINII
EOUT
E'N9
E1N10
E'NII
EtN12
I
I
I,
I
I
I,
1,.
CHARACTERISTICS
ERROR'" D.4$lV TYPICAL@25 C
1QIoIV TYPICAL@ 10 C
Note: The anllog $WItch between tbe op amp and the 16 Input
swltthesredUclstheenOlsdue to lelklfJe.
Allreslstars If I 10k
7-35
(/)
Q)
'':::
Typical Applications
(Continued)
Q)
CJ)
0)
o
oLt)
B-Bit Binary (BCD) Multiplying D/A Converter
10k
r---------,
20'
I
I
I
:t:
-....-.
v..
INPUT SIGNALS (VIS)
TERMINAL NOlol,C, 8,11
OUTPUT SIGNALS IV(5)
TERMINAL NOS. 2. 3. 8, 11
OUT
OUT
Not. 1: All switch '-chlnnll subltrltes IFI inll'l1Il1y connected to terminal No. 14.
Notl 2: All switdl N-d!annlt ",bstJlta Ir. intlrn.'1y CGnMctld to termjlJll No.7. ,
Normal oplrltion: Control·lin. biasina.
switch ON Vc "1"· VOD , sWitch OFF Vc "0"· Vss
Order Number CD4016MD or CD4016CD
Sea NS Package D14A
Order Number CD4016MF or CD4016CF
See NS Package F14A
Order Number CD4016MJ' or CD4016CJ
See NS Package J14A
I OIlTPU' ,
Order Number CD4016MN or CD4016CN
See NS Package N14A
• 1I1""e
Ordar Number CD4016MW or CD4018CW
Saa NS Package W14A
7·37
absolute maximum ratings
'~~5°C to + lS00C
Voltage at Any Pin (Note'l)
."
Operating Temperature Range CD4016M
CD4016C
electrical
VSS - 0:3V to VSS + 15.5V . Storage Temperature flange
_55°C to +12SoC Package Dissipation
,
_40°C to +8SOC Lead Temperature (Soldering, 10 seconds)
.
Operating V00 Range.' , .
characteristics CD4016M
CHARACTERISTIC
SYMBOL
::-_-l UNITS
I-_-:--::-_-r_-=LI",M:;,'T=:,:S'---,r-_ _
TEST CONDITIONS
-55"C
2S"C
MIN TVP MAX
QUIescent DISSipation
SOOmW
;300°C
VSS + 3V to VSS + lSV
MIN
JVP
12S"C
MAX
MIN typ MAX
VOLTS
TERMINALS
14
per Package
APPLIED
+10
5.6.12.13
GND
GND
1,4,8,11
~+10
7
All SWitches "OFF"
2,3.9: 10
Vss
Vc
V 15 '" Vos
Threshold Voltage
N·Channel
pW
01
. 300
pW
S +10
14
7
5,6,12.13
1-4,8-11
V DD
300
VOLTS
APPLIED
TERMINALS
All SWitches "ON"
01
+10
GND
+10
<+10
loS = 10,uA
Voo = 5V, lOV, or 15V'
1.7
1.5
1.3
V
-1.7
-1.5
-1.3
V
SIGNAL INPUTS (V",) AND OUTPUTS (Vosl
Vc'" Voo
Vss
VII
+7SV
120
360
+7.SV
-7.5V
-7.SV
120
360
to.25V
130
775
600
600
+5V
+15V
OV
+10V
t!. "ON" ReSistance
Between Any 2
of 4 SWitches.
Sine Wave Response
RL~10kU
f,~
IO,startlon)
+5V
130
130
'to.25V
+15V
325
1870
120
360
+O.2SV
120
360
200
400
93V
150
775
300
250
250
560
850
660
660
2000
+10V
130
600
+d 25V
'130
600
S.6V
300
1S70
OV
~+l7.5V
-7.5V
±75V
,5V
-SV
~SV
300
600
300
600
470
1230
400,
400
960
960
900
2600
300
~OO
600
600'
~l
n.
n
490, 1230
400
960
400
960
880
2600
n
10
15
%
+5V
= 1 k.~z
Input or Output
Leakage-Switch "OFF"
(EffectIve "OFF"
ReSIstance)
400
400
850
660
660
2000
400
-SV
-6V
"ON"Reslstance
200
200
280
250
250
580
200
rNotp3J
Voo
Vc" Vss
V"
+7SV
-7.SV
+7.5V
-7.5V
-.5V
,5V
-5V
+5V
:!:100
:!:100
N01e 2
NOle2
pA
125
125
nA
Vc '" Voo "" +5.V, Vss.= -5V
Frequency AesponseSWItch "ON"
(Sine Wave Input)
RL
";
I kU
20 Log lO
~
40
MHz
1.25
MHz'
0.9
MHz
= -'3 dB
V,. ~ 5V,lp·p.) Voo::: +5V, Vc'" Vss" -5V
• Feedtl1rough
, Switch "OFF"
20 Log 1o ' ~
V"
Crosstalk. Betwee~ any 2
of the 4 SWItches
. (Frequency at -50 dBI
. CapacItance
RL
"
~ -50 dB
Ve(A) " Voo" -+5V
VelBl '" Vss::: -5V
I kH
V"IAI"
5Vlp·pl
20 L0910' ~:(~:
"-50 dB
Voo::: +SV, Vc '" Vss = -5V
Input
CIS
Output
Cos'
4
Feedthrough
G IOS
02
V c '" Voo '" +IOV. Vss '" GND. CL '" 15 pF
VIS'" 10V (square wave)
PropagatIon Delay
SIgnal Input to
Signal Output
pF
10
I, '" I, '" 20 ns (input SIgnal)
CONTROL (Vel
Voo - Vss
Switch Threshold Voltage
~
15V, 10V, 5V
0.7
2.9
05
15
21
0.2
2.4
v
'tS'" '.Ot./A
Vee - Vss:=: 10V
Input Current'
Average Input Capacitance
CrosHalk. - '
Control Input to
SIgnal Output
Turn "ON"
PropagatIOn Delay
Maxlmum'Aliowabll;:
Control Input
Repell'Io'!,Rdtl?
tID
VC~VOD-VSS
pA
pF
Cc
Vpp - V'5S '" lOV
50
Vc'" 10V
(~quare Wave)
I", '" t'e" 20
V
mV
20
ns
oo " 10V. Vss '" GND. RL '" 1 kU
CL '" 15 pF
10
Vc" lOV (square wavel
MHz
I,'" 1,"" 20 ns
Note 1: The device should not be connected to circuits with the power on.
7·38
Nota 2: ±10 x 10.3 •
Note 3: Symmetrical about OV ..
(')
electrical characteristics
CHARACTERISTIC
C
CD4016C
·SYMBOL
LIMITS
TEST CONDITIONS
_40°C
MIN
QUiescent DISSIpatIon
per Package
TERMINALS
14
7
5; 6.12.13
Voo
Vss
VC
PT
V"
1,4,8,1,'
Yo.
2.3.9.10
Voo
All SWItches "ON"
V"
Vc
VIS"" Vos
P·ChanneJ
MAX MIN
TYP
5
0.1
UNITS
85°C
MAX
MIN TYP
TERMINALS
14
7
5.6.12.13
1-4. B-ll
0')
3:
.......
APPLIED
+10
GND
GNO
~ +10
r{ +10
5
BO
"w
~
5
0.1
5
BO
"w
1.7
15
1.3
V
VTHP
IDs"" 10jJA
Voo'" 5V. lOV, or 15V
-1.7
-1.5
-1.3
V
SIGNAL INPUTS IV.I AND OUTPUTS IV~I
V"
+7.SV
130 .370
200
260
520
-7.5V
130
370
200
400
260
520
±0.25V
160
790
280
850
400
lOBO
+5V
150
610
250
660
340
840
-5V
150
610
250
660
340
B40
±O.2SV
370
1900
5BO
2000
770
2380
+15V
130
370
200
400
260
520
+O.25V
130
370
200
400
260
520
9.3V
180
790
300
850
400
1080
+10V
6 "ON" ReSistance
Between Any 2
of
4 SWItches
R~= 10kfl
Sine Wave Response
(DIstortIon)
f" '" 1 kHz
Input or Output
leakage-Switch "OFF"
(Effective "OFF"
Resistance)
150
610
250
660
340
840
150
610
250
660
340
23BO
5.6V
350
1900
560
2000
750
23BO
-7.SV
±7.SV
10
+5V
-5V
±5V
15
+5V
-5V
5Vlp·pl
0.4
n
n
n
n
n
%
(Nott' 31
VC'" Vss
+7.SV
-7.5V
+5V
-5V
Frequency Re§ponse-
400
+025V
+75V
VOO
V"
T75V
-75V
+5V
-5V
t100
tl00
pA
125
(Note 2 125
(Note 2
nA
Vc'" Voo = +5V, Vss = -5V
SWitch "ON"
(Sme Wave Input)
RL
=
1 kn'
20
L0910
~ = -3 dB
40
MH,
1.25
MH,
09
MH,
V,s=5V{p'p) Voo=+5V.Vc=Vss=-SV
Feedthrough
SWitch "OFF"
20 Logto'Vos = -SOdS
V"
Crosstalk Between any :2
df the 4 SWItches
RL = 1 kS'!
VIS/A) '"
(Frequency at -SO dB)
Capacitance
5Vlp,pl
Input
VcfA) '" Voo = +5V
Ve(B) = Vss = -SV
20
LO~tO ~ :(~/
::: -SO dB
Voo'" +5V, Vc '" Vss '" -SV
Output
Feedthrough
Propagation Delay
Signal Input to
SIgnal Output
pF
4
CIOS
02
Ve'" Voo" +lDV. Vss '" GND. C L = 15 pF
V's"" 10V (square wave~
If'" If = 20 ns (Input signal)
10
CONTROL !Vel
Swftch Threshold Voltage .
Vaa - Vss = lSV. 10V. 5V
Its::: 10pA
Input Current
Voo - Vss "" 10V
Ve'::::: Voo - Vss
0.5
1.5
±10
Voo - Vss" 10V
Vc" 10V
(square wave)
50
Turn "ON"
Propagation Delay
MaXimum Allowable
Controlinpul
Rep~lItlon Rate
2.7
V
pA
pF
Average Input Capacitance
Crosstalk Control Input to
Signal Output .
mV
20
Voo - 10V. Vss '" GND. RL = 1 kH
CL - 15 pF
V c - 10V (sQuare wave)
10
MH,
If - If'" 20 n~
Note 1: The device should not be connected to circuits with the power on.
7-39
C
~
los'" tDp.A
Voo'" 5V, lOV, or 15V
OV
(')
o
YOLTS
APPLIED
+10
GNO
+10
~ +10
VTI'iN
+lDV
~
o
~
MAX
VOLTS
All SWitches "OFF"
Threshold Voltage
N·Channel
TYP
25°C
Note 2: ±10 x 10-3 .
Note 3: Symmetrical about 0 V.
0')
(')
oCO
'0
,g
o........
:a:
CO
o
~
Q
o
typical ON resistance characteristics
LOAD CONDITIONS
SUPPLY
CHARACTERISTIC·
CONDITIONS
Voo
IVI
Vss
IVI
RON
+15
0
RON (max.>
+15
0
RON
+10
0
RON Imax.)
+10
0
RON
+5
0
RON (max,)
+5
0
RON
RON
(max
I
RON
+7.5
-7.5
+7.5
-7.5
+5
-s
+5
-5
RON
+2.5
-2,5
RON (max.)
+2.5
-2.5
RON (max.)
RL -100kn
RL-10kO
RL"'1kO
Illi
V.
IVI
VALUE
Illi
V.
IVI
200
+15
200
200
0
200
300
+11
290
290
Illi
V.
IVI
+15
180
+15
'0
200
0
300
+9.3
320
-+9.2
+10
250
+10
240
+10
0
250
0
500
+7.4
560
+5.6
300
610
+5.5
860
+5
470
+5
450
+5
600
0
580
0
800
0
1.7k
+4.2
7.
+2.9
33.
+2.7
200
+7.5
200
+7.5
180
+7.5
200
-7.5
200
-7.5
180
-7.5 •
290
±0.25
280
.25
to.25 .
VALUE
VALUE
0
260
+5
250
+5
400
·240
310
-5
250
-s
240
-5
to.2S
+5
600
±O.2S
580
±0.25
760
590
+2,5
450
+2.5
490
+2.5
720
-2,5
520
-2.5
520
-2,5
232k
10.25
300.
to.2S
·Variation from a perfect switch: RON = on.
7-40
870k
±0.25
'
~ Semiconductor
Analog Switches/Multiplexers'
~National
CD4051 BM/CD4051 BC Single' 8-Channel
Analog Multiplexer/Demultiplexer
CD4052BM/CD4052BC Dual 4-Channel
Analog Mu Itiplexer/Demultiplexer
CD4053BM/CD4053BC Triple 2-Channel
Analog Multiplexer/Demultiplexer
general description
CD4053BM/CD4053BC is a triple 2-channel multiplexer
having three separate digital control inputs, A, Band C,
and an inhibit input. Each control input selects one of a
pair of channels which are connected in a single~pole
dOUble-throw configuration.
These analog multiplexers/demultiplexers are digitally
controlled analog switches having low "ON" impedance
and very low "OFF" leakage currents. Control of analog
signals up to 15 Vp·p can be achieved by digital signal
amplitudes of 3 - 15 V. For example, if V DO ~ 5 V,
Vss; OV and VEE; -5V, analog signals from -5V to
+5V can be controlled by digital inputs of 0-5V. The
multiplexer circuits dissipate extremely low quiescent
power over the full V DD - Vss and V DD - VEE supply
voltage ranges, independent of the logic state of the
cO[ltrol signals. When a logical "1" is present at the
inhibit input terminal all channels are "OFF."
features
.. Wide range of digital and analog signal levels: digital
3-15V, analog to 15Vp-p
.. Low "ON" resistance: 80n (typ) over entire 15Vp-p
signal-input range for V DO - VEE; 15 V
.. High "OFF" resistance: channel leakage of ±10pA
(typ) at V DD - VEE = 10V
CD4051BM/CD4051BC is a single 8-channel multiplexer
having three binary control inputs, A, Band C, and an
inhibit input. The three binary signals 'select 1 of 8
channels to be turned "ON" and connect the input, to
the output.
II
Logic level conversion for digital addressing signals of
3-15V (V DD - Vss = 3-15V) to switch analog
signals to 15 Vp-p (V DD - VEE; 15 V)
.. Matched switch characteristics: Ll.RON ; 5 n (typ)
for V DD - VEE = 15V
CD4052BM/CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an
inhibit input. The two binary input signals select 1 of 4
pairs of channels to be turned on and connect the
differential analog inputs to the differential outputs.
.. Very low quiescent power dissipation under all
digital-control input and supply conditions: 11lW
(typ) at V DD - Vss; V DD - VEE; 10V
.. Binary address decoding on chip
connection diagrams
IN/OUT
OUT/IN
IN/OUT
VDD~~·A
4'
6 OUT/IN
lNiOuT'
7
5
INiOuT'
INH
VEE
Vss
1
Oy
2v
v
Jy
1v
INiiiiiT ~UT/IN "iNiOiiT
INH
VEe
Vss
TOP VIEW'
TOP VIEW
TOP VIEW
Oider Number CD4051BMD
or CD4051BCD
See NS Package D16A
Order Number CD4051BMF
or CD4051BCF
See NS Package F16A
Order Number CD4051BMJ
or CD4051BCJ
See NS Package J16A
Order Number CD4052BMD
or CD4052BCD
S•• NS Package D16A
Order Number CD4052BMJ
or CD4052BCJ
See NS Package J16A
Order Number CD4052BMN
or CD4052BCN
See NS Package N16A
Order Number CD4052BMW
or CD4052BCW
See NS Package'W16A
Order Number CD4053BMD
or CD4053BCD
See NS Packag. D16A
, Order Number CD4053BMF
or CD4053BCF
See NS Package F16A
Order Number CD4053BMJ
or CD4053BCJ
See NS Package J16A '
Order Number CD4053BMW
or CD4053BCW
See NS Packege W16A
7-41
absolute maximum rating
voo
VIN
Ts
Po
TL
recommended operating conditions
DC Supply Voltage
-0.5 Vdc to +18 Vdc
Input Voltage
-0.5 Vdc to V DO + 0.5 Vdc
_65°C to +15.0°C,
Storage Temperature Range'
Package Dissipation
500mW
300°C.
Lead Temperature (soldering, 10 seconds)
dc electrical characteristics
Voo DC Supply Voltage
VIN Input Voltage
TA Operating Temperature Rangp
4051 BM/4052BM/4053BM
4051 BC/4052BC/4053BC
100
_55°C to +125°C
_40°C to +85°C
(Note 2)
+2S oc
_55°C
Parameter
+5 Vdc to +15 Vdc
OV to Voo Vdc
Conditions
Min
Quiescent Oevice Current VOO=5V
VOO = 10V
VOO = ISV
Max
Min
Typ
S
10
20
+12SoC
Max
Min
Max
Units
S
20
20
150
600
600
p.A
iJA
iJA
Signal Inputs (VIS) and Outputs (VOS)
RON
"ON" Resistance (Peak
for VEE ~ VIS <;;; VOO)
RL=10k12
(any channel
selected)
,
MON
lI"ON" Resistance
Between Any Two
Channels
RL=10k12
(any channel
selected)
VOO= 2.SV,
VEE = -2.5V
or VOO = SV,
VEE = OV
2000
270
?SOO
3S00
12
VOO= SV
VEE = -SV
orVOO= 10V,
VEE= OV
310
120
400
580
'n
VOO=7.SV,
VEE = -7.SV
or VOO = ISV,
VEE = OV
220
80
280
400
12
VOO= 2.SV,
VEE,= -2.SV
or VOO= SV,
VEE=OV
10
12
VDO= 5V,
VEE = -SV
or VOO= 10V,
VEE= OV
10
12
5
12
VOO = 7.5V,
VEE = -7.5V
or VOO = lSV,
VEE =OV '
"OFF" Channel Leakage
Current, any ch~nnel
"OFF"
VOO = 7.5V, VEE = -7.5V
0/1 = ±7.5V, I/O = OV
"OFF"·Channel Leakage
Current, all channels
"OFF" (Common
OUT/IN)
Inhibit = 7.SV C040S1
VOO= 7.SV,
VEE = -7.~V, C040S2
0/1 = OV,
I/O = ±7.SV
C040S3
,
±oo
±0.01
±SO
±OOO
nA
±200
±0.08
±200
±2000
nA
±200
±0.04
±200
±2000
nA
±200
±0.02
±200
±2000
nA
1.S
3.0
4.0
\.S
3.0 '
4.0
V
V
V
Control Inputs A, B, C and Inhibit
VIL
Low Level Input Voltage VEE = VSS R L = 1k12 to VSS
liS < 2iJA on all OFF channels
VIS = VDO thru 1k12
VOO= SV
VOO = 10V
VOO = 15V
VII;!
High Level Input Voltage VOO= 5
VOO= 10
VOO= 15
liN
,Input Current
1.S
3.0
4.0
3.5
7
11
VOO=15V" VEE=OV
VIN = OV
VOO = 15V, VEE = OV
VIN = 15V
3.5
7
11
-0.1
0.1
3.S
7
11
-10-5 -0.1
10- 5
0.1
V
V
V
-1.0
p.A
1.0
iJA
Note': "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to Imply that the devices should'be operated at these limits. The table of. "Electrical Characteristics" provides conditions for actual
device operation.
'
. Note 2: All voltages measured with respect to VSS unless otherwise specified.
7-42
dc electrical characteristics (can't)
(Note 2)
+2SoC
_40°C
Conditions
Parameter
100
Min
Quiescent Oevice Current VOO= SV
VOO= 10V
VOO=lSV
Max
Min
Typ
20
40
BO
+8SoC
Max
Min
Units
Max
20
40
BO
lS0
300
600
p.A
p.A
p.A
2S00
3200
fI.
Signal Inputs (VIS) and Outputs (VOS)
RON
"ON" Resistance (Peak
for VEE';;; VIS';;; VOO)
RL=10kfl.
(any channel
selected)
..
MON
b "ON" Resistance
Between Any Two
Channels
RL=10kfl.
(any channel
selected)
VOO=2.SV,
VEE = -2.SV
or VOO= SV,
VEE = OV
2100
270
,
VOO= SV,
VEE = -SV
or VOO= 10V,
VEE = OV
330
120
400
S20
fI.
VOO= 7.SV,
VEE r -7.SV
or VOO = lSV,
VEE = OV
230
BO
2BO
360
fl..
,
.
VOO= 2.SV,
VEE = -2.SV
or VOO = SV,
VEE = OV
10
fI.
VOO = SV
VEE = -SV
or VOO.= 10V,
VEE = OV
10
fI.
VOO = 7.SV,
VEE = -7.SV
or VOO = lSV,
VEE = OV
5
fI.
"OFF" Channel Leakage
Current, any channel
"OFF"
VOO = 7.SV, VEE = -7.SV
0/1 = ±7.SV, I/O = OV
"OFF" Channel Leakage
Current, all channels
"OFF" (Common
OUT/IN)
Inhibit = 7.SV C040S1·
VOO = 7.SV,
VEE = -7.5V, C040S2
0/1 = OV
I/O = ±7.5V
C040S3
,
r-
±SO
±0.01
±oo
±SOO
nA
±200
±O.OB
±200
±2000
nA
±200
±0.04
±200
±2000
nA
±200
±0.02.
±200
±2000
nA
1.S
3.0
4.0
1.S
3.0
4.0
V
V
V
Control Inputs A, B, C and Inhibit
VIL
Low Level Input Voltage VEE = VSS R L = 1 kfl. to VSS
liS < 2p.A on all OFF Channels
VIS = VOO thru 1kfl.
VOO= SV.
VOO= 10V
VOO= 15V
VIH
High Level Input Voltage VOO=5
VOO = 10
VOO=lS
liN
Input
~urrent
1.S
3.0
4.0
3.S
7
11
VOO=lSV, VEE=OV
VIN = OV
VOO=15V, VEE=OV
VIN = lSV
3.S
7
11
'3.S
7
11
V
V
V
-0.1
-10-5
-0.1
-1.0
0.1
lO-S
0.1
1.0
p.A
p.A-
Note 1: "Absolute Maximum Ratings' are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides cohditions for actual
device operation.
Note 2: All voltages measured with respect to VSS unless otherwise specified.
7-43
\
ac electrical characteristics
T A = 25°C, t, = tf = 20 ns, unless otherwise specified.
Typ
Max
'Units
tPZH,
tPZL
Propagation Delay Time from
Inhibit to Signal Output
(channel turning on)
VEE = VSS= OV
RL = 1 kil
CL = 50 pF
5V
10V
15V
600
225
160
1200
450
320
ns
ns
ns
tpHZ
tpLZ
Propagation Delay Time from
Inhibit to Signal Output
(channel turning off)
VEE = VSS=OV
RL=lkil
CL = 50 pF
5V
10V
15V
210
100
75
420
200
150
ns
ns
ns
CIN
Input Capacitance
Control Input
Signal Input (IN/OUT)
5
10
7.5
15
pF
pF
Conditions
Paraf!l.ter
Vpp
Min
COUT, Output Capacitance
(common OUT/IN)
CD4051
CD4052
C04053
CIOS
Feedthiough Capacitance
CPO'
Power Dissipation Capacitance
10V
10V
10V
VEE = VSS= OV
CD4051
CD4052
C04053
8
pF
pF
pF
0.2
pF
110
140
70
pF
pF
pF
%
30
15
Signal Inputs (VIS) and Outputs (VOS)
tPHL,
tPLI:I
Sine Wave Response
(Distortion)
RL=10kil
flS = 1 kHz
VIS= 5 V p _p
VEE= VSI = OV
10V
0.04
Frequency Response, Channel
"ON" (Sine Wave Input)
RL = 1 kil, VEE = VSS = OV, VIS = 5Vp:'p,
2010910 VOSIVIS = -3 dB
10V
40
MHz
Feedthrough, Channel "OFF"
RL = 1 kil, VEE = VSS = OV, VIS = 5Vp _p,
20 10910 VOSIVIS = -40 dB
10V
10
MHz
Crosstalk Between Any Two
Channels (frequency at 40 dB)
RL = 1 kil, VEE = VSS = OV, VIS(A) = 5Vp,:
10V
20 1091 0 VOS(B)IVIS(A) = -40 dB (Note 3)
3
MHz
Propagation Delay Signal
Input to Signal Output
VEE= VSS=OV
CL = 50 pF
5V
10V
15V
25
15
10
10V
65
5V
10V
15V
500
180
120
ns
ns
ns
55
35
25
Control Inputs, A, B, C and Inhibit
tPHL,
tPLH
Control Input to Signal
Crosstalk
VEE = VSS= OV, RL = 10 kil at both ends
of channel. '
Input Square Wave Amplitude = 10 V
Propagation Delay Time from
Address to Signal Output
(channels "ON" or "OFF")
VEE=VSS=OV
CL = 50 pF
mV (peak)
1000
360
240
ns
ns
ns
Note 3: A, B are two arbitrary channels with A turned "ON" and B "OFF".
",
7·44
block diagrams
CHANNEL IN/OUT
12
A
15
11
10
COMMON
OUT/IN
BINARY
TO
1 OF 8
OECOOER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
INH
CD4051 BM/CD4051 Be
X CHANNELS IN/OUT
, 3
11
15
14
Voo
COMMON X
OUT/IN
A
LOGIC
LEVEl
CONVERSION
INH
COMMON Y
OUT/IN
10
BINARY
TO
1 OF 4
OECOOER
WITH
INHIBIT
, 0
Y CHANNElS IN/OUT
CD4052BM/CD4052BC
7-45
block diagram (cont)
IN/OUT
VDD
cy
A
ex
-by
bx
OUT/IN
ax OR.y
BINARV TO
1 OF 2
DECODER
WITH INHIBIT
11
IV
----10
OUTflN
b. OR by
LOGIC
LEVEL
CONVERSION
----DUTflN
ex OR cy
INH
Vss
VEE
CD4053BM/CD4053BC
INPUT STATES
"ON" CHANNELS
INHIBIT C
B
A
0
0
0
0
0
1
ex, bx, ax
0
0
1
OX,OV
0
lX,lV
ex, bx. ay
0
0
1
0
2
2X,2V
ex, by, ax
0
0
1
1
1
3
3X,3V
ex, by. ay
0
0
0
1
4
5-
cy, bx. ax
1
0
1
1
6
cy, by;ax
0
.
1
0
1
0
0
1
1
CD4051B CD4052B CD4053B
cY,bx.ay
7
NONE
* Don't Care condition.
7-46
cy, by. ay
NONE
NONE
switching time waveforms
VDD
If
ADDRESS
INPUTS
A,B or C
VDD
1'----
VDD
I
~tPLH
-I
Vas
1
50%
I
I
I
0---+-
1
SIGNAL INPUT TO SIGNAL OUTPUT
VDD
IN/OUT or
OUT/IN
ANY CHANNEL
-
OUT/IN or IN/OUT
I--_-..-VDS
~ lKf!
INHIBIT~' _
150PF
VDD
VDD
90%
lKf!
D
DUT/IN or
IN/OUT
IN/DUTor
DUT/IN
r
IpZL
VDD
50PF
Vas
a
7-47
-.
~lpLZ
special considerations
o.a
I n certain applications the external load-resistor current
may include both V DD and signal-line components. To
avoid drawing V DO current when switch current flows
into IN/OUT pin, the voltage drop across the bidirec·
tiona) switch must not exceed
V at T A " 25°C, or
0.4 V atT A> 25°C (calculated from RON values shown).
No V DO current will flow through R L if the switch
current flows into OUT/IN pin.
typical performance characteristics
"ON" Resistance as a
Function of Temperature for
VDO - VEE = 15V
"ON" Resistance vs Signal
Voltage for TA = 2S"C
E
400
1
l50
S
lOO
l!j
z
..~
250
::
200
i.
150
P
100
~
'"
J,
III II
III II
""1
VDD~'IOV
I J...U.+1i
50
VDD
-
VEe
H-+++++I+t++++++1
l50
2
4
6
~
250 ~+lHr++~~f4-rrti1
iii
.
200 ~+lHr++~~f4-rrti1
i.
?
150
~
5
=1SV
o
-8-6-4-20
400
~ lOO ~+lHr++~~f4-rrti1
JDU J"I =15J
w
I
.
T. = +125·C H-+-I+t++J:o:H
~~~~~~~~~~
100
~':t:r·:'=51+;;25F·ci;::!:~::!:~::rIft~
50
0
TA=-5SOC
-8-6-4~202468
8
SIGNAL VOLTAGE IV,s) IV)
E
1S
w
'"'"
i
Function of Temperature for
VOO-VEE = 5V
400
\
1
350
300
S
lOO
l!j
z
Z5D
zoo
ISO
..5
T•• ~·C
~
150
~
z
~
T. = -ss·c
5
0
-8 -6-4-Z0
250
?
-(1 m
50
~
i3
.
TA =+125"C
z
z
"ON" Resistance as a
Function of Temperature for
VOO - VEE = lDV
400
100
w
"ON" Resistance as a
350
i.
?
SIGNAL VOLTAGE IV,,) IV)
Z
4
6
TA
SIGNAL VOLTAGE IV,s) IV)
"
+125"C
11111
TA .= +25"C
200
:~I=IJ~
1'1 I r I
IIIII
100
50
IIIII
o
-8-6-4-20
8:
.11111 .
2
4
SUPPLY VOLTAGE IV,,) IV)
7-48
6
8
'
~ Semiconductor
~National
Analog Switches/M ultiplexers
CD4066BM/CD4066BC Quad Bilateral Switch
general description
The CD4066BM/CD4066BC is a quad bilateral switch
intended for the transmission or multiplexing of analog
or digital signals. It is pin-for-pin compatible with
CD4016BM/CD4016BC, but has a much lower "ON"
resistance, and "ON" resistance is relatively constant
over the input-signal range.
•
Extremely low ;'OFF" switch leakage
0.1 nA typ
@VDD - VSS = 10V,
TA=25°C
• Extremely high control input
10 12n typ
impedance
• Low crosstalk between switches
-50 dB typ
@fis= 0.9 MHz, RL = 1 kn
• Frequency response, switch "ON"
40 MHz typ
features
3V to 15V
• Wide supply voltage range
0.45 VDD typ
• High noise immunity
• Wide range of digital and
±7.5 VPEAK
analog switching
80n typ
• "ON" resistance for 15V operation
ARON = 5n typ
• Matched "ON" resistance over
15V signal input
• "ON" resistance flat over peak-to-peak signal range
• High "ON"/"OFF" output voltage ratio
65 dB typ
@fis=10kHz,RL=10kn
• High degree of linearity
< 0.4% distortion.typ
@ fis = 1 kHz, Vis = 5 Vp-p,
VDD - VSS = 10V, RL = 10 kn
applications
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital/digital-to-analog conversion
• Digital control of frequency, impedance, phase,
and analog-signal gain
schematic and connection diagrams
IN/OUT
CONTAOL
Dual-In-Line Package
14
IN/OUT
Order Number CD4066BMD or CD4066BCD
See NS Package D14A
Order Number CD4066BMF or CD4066BCF
See NS Package F14A
Order Number CD4066BMJ or CD4066BCJ
See NS Package J14A
Order Number CD4066BMN or CD4066BCN
See NS Package N14A
Order Number CD4066BMW or CD4066BCW
See NS Package W14A
VOO
'--_-+1;:,3 CONTAOL A
OUTtIN
CONTROL 0
IN/our
IN/OUT
to
,CONTROL B 5
CONTAOL C
-=-+---,
Vss
OUT/IN
OUT/IN
IN/OUT
TOPVIEW
7-49
absolute maximum ratings
recommended operating conditions
(Notes 1 and 2)
(Note 2)
voo Supply Voltage
VIN Input Voltage,
Voo Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04066BM
C04066BC
-{).SV to +18V
-{).SV to VOO + O.SV
-6SoC to +IS0°C
TS Storage Temperature Range
Po Package Oissipation
SOOmW
T L Lead Temperature (Soldering. 10 seconds)
300°C
-
CD4066BM (Note 2)
, -55°C
Conditions
,
Min
25°C
125°C
Typ
Max
0.25
0.5
1.0
0.Q1
0.01
0.01
0.25
0.5
1.0
7.5
15
30
2000
400
220
270
120
80
2500
500
280
3500
550
320
Max
Quiescent, Device Current VOO = 5V
VOO= 10V
VOO=15V
100
-55"C to +125°C
-40°C to +85°C
-
.
dc electrical characteristics
Parameter
3V to ISV
OV to'VOO
Min
Min
Max
Units
p.A
p,A
p.A
Signal Inputs and Outputs
"ON" Resistance
RON
RL=10knto
~
Vc = VOO. VIS = VSS to VOO
VOO = 5V
VOO= 10V
VOD = 15V
Ll.RON
liS
Ll. "ON" Resistance
Between any 2 of
4 Switches
n
n
n
RL = 10 kn to VOO;VSS
Vc = VOO. VIS = VSS to VOO
VOO= 10V
VOO= 15V
n
n
10
5
Input or Output Leakage VC=O
VIS= 15Vand OV.
Switch "OFF"
VOS = OV and 15V
±50
±O.,
. ±50
±500
nA
1.5
3.0
4.0
V
Control Inputs
VILC
VIHC
liN
Low Level Input Voltage VIS = VSS and VOO
VOS = VOO and Vss
IIS=±10p.A
VOO = 5V
VOO= 10V
VOO=15V
High Level Input Voltage VOO.= 5V
VOO = 10 V (see note 6)
VOO=15V
Input Current
2.25
4.5
6.75
1.5
3.0
4.0
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.5
8.25
±10-5
±0.1
VOO - VSS = 15V
VOO;;' VIS;;' VSS
VOO;;'VC;;'VSS
1.5
3.0
4.0
V
V
V
3.5
7.0
11.0
±0.1
it
V
±1.0
p.A
.
dc electrical characteristics
Parameter
100
C04066BC (Note 2)
_40°C
Conditions
Min
Quiescent Oevice Current VOO = 5V
VOO = 10V
VOO=15V
Max
1.0
2.0
4.0
7·50
25°C
Min
85°C
Typ
Max
0.01
0.Q1
0.01
1.• 0
2.0
4.0
Min
Max
7.5
15
30
Units
p.A
p.A
p.A
dc electrical characteristics
o
_40°C
Parameter
C
.IlJI.
(Continued) C04066BC (Note 2)
Conditions
Min
Max
25°C
Min
Typ
85°C
Max
Min
Max
Units
Signal I nputs and Outputs
"ON" Resistance
RON
OJ
3:
.......
RL = 10 kn to V00"2 VSS
Vc = VOO, VSS to VOO
VOO= 5V
VOO = 10V
VOO=15V
lIRON
liS
lI"ON" Resistance
Between Any 2 of
4 Switches
Input or Output Leakage
Switch "OFF"
2000
450
250
270
120
SO
2500
500
2S0
3200
520
300
n
n
n
RL=10knto VOO-VSS
2
VIHC
n
10
5
VC=O
±50
liN
Low Level Input Voltage VIS = VSS and VOO
VOS = VOO and VSS
IIS=± IOIlA
VOO= 5V
VOO= 10V
VOO=15V
n
±0.1
1.5
3.0
4.0
High Level Input Voltage VOO = 5V
VOO= 10V (See note 6)
VOO= 15V
Input Current
3.5
7.0
11.0
2.25
4.5
6.75
3.5
7.0
11.0
2.75
5:5
S.25
±10-5
±0.3
VOO - VSS = 15V
VOO;;' VIS;;' VSS
VOO;;' VC;;'VSS
±50
±200
nA
1.5
3.0
4.0
1.5
3.0
4.0
V
V,
V
-
V
V
V
3.5
7.0
11.0
±0.3
±1.0
IIA
,.
ac electrical characteristics
TA = 25°C, tr = tf = 20 ns and VSS = OV unless otherwise specified
Parameter
tPHL, tpLH
tPZH, tPZL·
tPHZ, tpLZ
Propagation Oelay Time Signal
Input to Signal Output
Propagation Oelay Time
Control Input to Signal
Output High Impedance to
Logical Level
Propagation Oelay Time
Control Input to Signal
Output Logical Level to
High Impedance
Min
Conditions
Vc = VOO, CL = 50 pF, (Figure 1)
RL=200k
VOO = 5V
VOO = 10V
VOO = 15V
Typ
Max
Units
25
15
10
55
35
25
ns
ns
ns
125
60
50
ns
ns
ns
125
60
50
ns
ns
ns
R L = 1.0 kn, CL = 50 pF, (Figures 2
and 3)
VOO = 5V
VOO = 10V
VOO=15V
RL = 1.0 kn, CL = 50 pF, (Figures 2\
and 3)
.
,
VOO= 5V
VOO= 10V
VOO = 15V
Sine Wave Oistortion
Vc = VOO = 5V, VSS = -5V
R L = 10 kf~, VIS = 5 .vp-p, f = 1 kHz,
Frequency Response-Switch
"ON" (Frequency at -3 dB)
Vc = VOO = 5V, VSS = -5V,
RL = 1 kn, VIS = 5Vp _p,
20 Log 10 VOSIVOS(lkHz)-dB,
0.4
%
40
MHz
(Figure 4)
(Figure 4)
7·51
o
C
.IlJI.
o
0)
0)
VCC= VOO, VIS = VSS to VOO
VOO= 10V
VOO=15V
Control Inputs
VILC
o
0)
0)
OJ
o
ac electrical characteristics
(Continued)
T A = 25°C. tr = tf = 20 ns imd VSS = OV unless otherwise specified
Parameter
Typ
Min
Conditions
Units
Max
Feedthrough - Switch "OFF"
(Frequency at -50 dB)
Vee = SV. Vc = vss = -sv.
RL = I kll. VIS = SVp-p• 20 LogIO.
VOslVlS = -50 dB. (Figure 4)
1.2S
Crosstalk Between Any Two
Switch (Frequency at -SO dB)
Vee = VC(1) = SV; VSS = VC(2) = -SV.
RL·= I kll. VIS(A) = SVP_P• 20 Lo9IO
VOS(2)IVIS(I) = -50 dB.
O.g·
MHz
150
mVp-p
6.0
8.0
8.S
MHz
MHz
MHz
(Figure 5)
Crosstalk; Control Input to
Signal Output
Vee= 10V. RL = 10 kll
filN = I kll. VCC = 10V Square Wave.
CL = SOpF
(Figure 6)
RL = I kll. CL = SO pF. (Figure 7)
VOS(I) = '1,vOS(lkHz)
Vee= SV
Vee = 10V
Vee = ISV
Maximum Control Input
Cis
Signal Input Capacitance
B
pF
Cos
Signal Output Capacitance
Vee = 10V
8
pF
Feedthrough Capacitance
VC=OV
0.5
,
CIN
pF
pF
7.S
5
Control Input Capacitance
Note 1: "Absolute Maximum Ratings" afe those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the
devices should be operated at these limits, The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual
device operation,
Note 2: VSS '" OV unless otherwise specified.
Note 3: These devices should not be connected to circuits with the power "ON".
Nate 4: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in CL wherever it is specified.
Note 5: VIS is the voltage at the in/out pin and Vas is the voltage at the out/in pin. Vc is the voltage at the control input.
Note 6: Conditions for VIHC:
al VIS" VOD, lOS::' standard B series IOH
b) VIS::' OV, lOS'" standard Bseries taL
ac test circuits and switching time wavefonns
VC'VDD~
vI"
CONTROL
VIS
,w,;:"
VIS
..11-_....___...._
10F4
'N/DUT
VDD~',<.!,.
I,
1
Voo
DUTI'N
I ..L
CL
RL
I""
~
.... ,.
OV
10%
VDS
;f.~LH
VD: DD
-:2DUk
DV
C
FIGURE 1. tPHL. tpLH Propagation Delay Time Signal Input to Signal Output
T
VC~
tpZH
,,%
VDD~
r-::C;:;DN~T;;;RD;';"L-;';"VD':D-'I
r
10F4
•.
,N/DUT SWITCH" DUTI'N
1
.._ ....___...._
I 1.. ,
I~k" -:~t
DV
VDS
VDH~IPZH"'-DV
.
''''
VDD~VDD
''''
.DV~PHZ
VOH
''''
DV
FIGURE 2. tpZH. tpHZ Propagation Delay Time Control to Signal Output
tpZL
Vc
VIS '" OV
T
I
-:
IPlL
~
-'-CL
ISO"
IPlZ
.
VDD~
.'"
VDD~
.
Voo
VDD
RL
CONTROL
VDD
,~1k
10f4
'
IN/OUT SWITCHES OUT/IN
~ Vos
Vss
tpLZ
VDD
DV~
90%
,
..~
VOL
VOL
FIGURE 3. tPZL. tpLZ Propagation Dalay Time Control to Signal Output
7·52
""
ac test circuits and switching time waveforms
(Continued)
VC----,
IN/OUT ~'~~:ES
OUT/INI-~~-vos
Vss
RL
Vc = VOO for distortion and frequency response tests
Vc = VSS for feedthrough test
-SV
FIGURE 4. Sine Wave Distortion, Frequency Responsa and Feedthrough
VC(I)' Voo - - - - - .
IN/OUT
S~'~~H4ES OUT/INI-~~-VOS(I)
VSS
RL
Ik
-SV
2.SV-O
V'S(I)
VCI2)' Vss - - - - - ,
/ ' \
-2.:: '[};2j~
V'SI2)" DV
-SV
FIGURE 6. Crosstalk Between Any Two Switches
VC----..,
tr '" 20 ns
If" 20 liS
VOO----+-~~~-~
O V - - -......of'
IN/OUT ~'~~H4ES OUT/INI--...----4I~- VOS
CL
RL
10k
J
SOPf
Vos
f
CROSSTALK
j
FIGURE 6. Crosstalk: Control Input to Signal Output
VOO
Vc
Voo
Ve
OV
IN/OUT ~~~:ES OUT/INt--....- -...--VOS
VSS
CL
1
RL
ISOPF ':' lk
--,VOSi1kHz
VOl
FIGURE 7. Maximum Control Input Frequency
7-53
T
om
typical performance characteristics
CO
CO
o
~
c
o
........
:::i
m
CO
CO
~
"ON" Resistance as a Function
of Temperature for
VOO-VSS,;,15V
"ON" Resistance vs Signal
Voltage for T A = 25D C
400
f
c:c
:;;
250
~
200
150
f'
~
~
~
'"co
I 1.11 I
Jo~ l Js~ .15J
300
2
400
I III I
2: 350
300
'"
~
250
w
u
iiia:
~
~~.!Or
lQO
~
I JJ..H1i.
50
w
~
vuo - VSS· 15V
~
o
350
S
200
150
50
0
r.;~~~:t~~f11r~
TA"'-55°C
SIGNAL VOLTAGE IVls) IV)
SIGNAL VOLTAGE IVIS) IV)
"ON" Resistance as a Function
"ON" Resistance as a Function
of Temperature for
VOO - VSS = 10V
of Temperature for
VOO-VSS=5V
3
400
~
350
~
300
~
250
2:
250
~ 200
~
200
~
TA'" +25 c C
-8-6-4-204
-8-6-4-20
o
TA·~
100
400
2'
co
IIIII
350
TA
.e;. 300
~
TA·+125>C
150
TA·';25 C
50
'Il rn
1\
TA"'-55 C
o
TA'" +2S"C
a:
~
150
~
100
'"
;l
50
u
-8-6-4-20
.~ 1.IJ5..1C
I' I I I
IIIII
IIIII
o
-8 -6 -4 -2
SIGNAL VOLTAGE IVIS) IV)
=+12S-C
IIIII
u
0
6
8
SUPPL V VOLTAGE IVIS) IV)
special considera.tions
In applications where separate power sources are used
to drive VOO and the signal input, the VOO current
capability should exceed VOO/RL (RL = effective
external load of the 4 C04066BMlC04066BCbiiaterai
switches). This provision avoids any permanent current
flow or clamp actiori on the VOO supply when power is
applied or removed from C04066BM/C04066BC.
avoid drawing VOO current when switch current flows
into terminals 1, 4, 8 or 11, the voltage drop across the
bidirectional switch must not exceed 0.6V at T A::::; 25°C,
or O.4V at T A > 25°C (calculatec;l from RON values
shown).
No VOO current will flow through RL if the switch
current flows into terminals 2, 3, 9 or 10_
In certain applications, the external load-resistor current
may include both VOO and signal-line components. To
\
7-54
,~National
Analog Switches/Multiplexers
~ Semiconductor
CD4529BM/CD4529BC Dual 4-Channel or
Single a-Channel Analog Data Selector
General 'Description
Features
The CD4529B is a dual 4-channel or a single 8-channel
analog data selector, implemented with complementary
MOS (CMOS) circuits constructed with Nand P-channel
'enhancement mode transistors_ Dual 4-channel or 8channel mode operation is selected by proper input
coding, with outputs Z and W tied together for the single
8-bit mode. The device is suitable for digital as weil
as analog applications, including various 1-of-4 and
1-of-8 data selector functions_ Since the device is analog
and bidirectional, it can also be used for dual binary to
1-of-4 or single binary to 1-of-8 decoder applications.
3.0V to 15V
• Wide supply voltage range
0.45 VDD typ
• High noise immunity
0.005 /-lW/package typical
• Low quiescent
power dissipation
@5VDC
• 10 MHz frequency operation (typical)
• Data paths are bidirectional
• Linear ON resistance (120n typical @ 15V)
• TR I-STATE® outputs (high impedance disable strobe)
• Plug-in replacement for MC14529B
Connection Diagram
Logic Diagram
Dual-In-Line Package
Vl
Y2
Vl
w
2
xoO--r-t_i--r-t_--t_-----t-----i(
J
Xlo-~-+_i--r-t_--t_----_+----_4(
TDPVIEW
Order Number CD4529BMJ or CD4529BCJ
See NS Package J,SA
Order Number CD4529BMN or CD4529BCN
See NS Package N1SA
4
X2o--r-t_i~r-t_--t_----_+----_i~;t-+
Truth Table
STx STy
1
1
1
1
B
0'
0
,
A
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
~
1
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
1
0
X
X
Z
W
XO
Xl
X2
X3
YO
Yl
Y2
Y3
XO
Xl
X2
X3
YO
Yl
Y2
Y3
High
Impedance
(TRI-STATE®)
XJO--r-t_i~r-t_--------_+----_iC;~
Dual
} 4-Channel
Mode
2 Outputs
14
YO o-+__+-I--r-+----------+-------1~*_'
13
Single
8-Channel Mode
1 Output
(2 and W
tied together!
Y1o-~--__+-4~+_--------_+----_4(
12
Y2o-+---;----+----------t-----;~~
11
YJo----------------------t-----;C:~
x = Don't care
7-55
(J
III
Absolute Maximum Ratings
Recommended Operating Conditions
C\I
(Notes 1 and 2)
(Note 2)
(7)
lt')
V
C
(J
.......
:i
III
VDD DC Supply Voltage
VIN Input Voltage
-O,5V to +1SV
-Q,5V to VDD + 0,5V
TS Storage Temperature Range
-.£5"C to +150"C
Po Package Dissipation
SOOmW
TL Lead Temperature (Soldering, 10 seconds)
300'C
VDD DC Supply Voltage
VIN Input Voltage
3V to lSV
o to VDD
T A Operating Temperature Range
C04529BM
CD4529BC
-5S"C to +125"C
-40"C to +8S'C
(7)
C\I
lt')
V
C
(J
DC Electrical Characteristics
PARAMETER
100
VOL
VOH
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
CD4529BM (Note 2)
MIN
VIH
12S"C
TYP
MAX
MIN
MAX
UNITS
1.0
0.001
1.0
60
pA
VDD = 10V
1.0
0.002
1.0
60
pA
VDD = 1SV
2.0
0.003
2.0
120
pA
VDD = 5V
0.05
a
0.05
0.05
V
VDD = 10V
O.OS
0
0,05
0.05
V
VDD = 15V
0.05
a
0.05
0.05
V
VIL = OV, VIH = VDD, 1101 < 1 pA
VIL
=OV, VIH = VDD, 1101 < 1 pA
VDD = 5V
4,95
4.95
5.0
4,95
V
= 10V
VDD = 15V
9.95
9.95
l1J.0
9.95
V
14.95
14.95
14,95
15.0
V
VDD = SV
1.5
2.25
1.5
1.S
V
(Note 3)
VDD = 10V
3.0
4.50
3.0
3.0
V
VDD = 15V
4.0
6.75
4.0
4.0
High Level Input Voltage
Input Current
= 5V
3.5
2.75
3.5
V
VDD = 10V
7.0
7.0
5.50
7.0
V
VDD = 15V
11.0
11.0
8.25
il.0
V
VDD = lSV
VIN = OV
ON Resistance
V
3.S
VDD
VIN = 15V
RON
MIN
Low Level Input Voltage
(Note 3)
liN
MAX
VOO = SV
VDD
VIL
2S0C
-Ss"c
CONDITIONS
-0,1
-10-5
-0.1
-1.0
pA
0.1
lO-S
0.1
1.0
pA
-.
VDD = 5V, VSS = -5V
VIN = 5V
400
165
480
'640
VIN = --5V
400
100
480
640
VIN = ±0.25V
400
155
480
640
n
n
n'
VDD = 7.5V, VSS = -7.5V
= 7,5V
240
135
270
400
VIN = -7.5V
240
75
270
400
VIN = ±0.2SV
240
100
270
400
VIN = 10V
400
165
480
640
VIN = 0.25V
400
100
480
640
400
160
480
640
VIN
n
n
n
VDD = 10V, VSS = OV
VIN = 5.6V
VDD = 15V, VSS
=OV
250
110
400
n
n
n
Input to Output Leakage
VSS = -5V, VDD = SV, VIN = SV,
±125
±0.001
±125
±12S0
nA
Current
VOUT= -5V
VSS = -5V, VDD = 5V, VIN = -5V,
±125
±0.001
±125
±1250
nA
VOUT = 5V
VSS = -7.5V, VDD = 7.5V, VIN = 7.5V,
±250
±0.0015
±250
±2S00
nA
±250
±0.0015
±250
±2500
nA
VIN = 15V
250
135
270
400
VIN = 0.25V
250
75
270
400
VIN = 9.3V
IOFF
n
n
n
270
VOUT = -7.5V_
VSS = -7.5V, VDD = 7.SV,
VIN = -7.5V, VOUT = 7.5V
7-56
(")
DC Electrical Characteristics
PARAMETER
100
VOL
VOH
VIL
Quiescent D~vice Current
Low Level Output Voltage
High Level Output Voltage
~
liN
MIN
MIN
MAX
TYP
MAX
5.0
0.001
5.0
70
pA
VOO" 10V
5.0
0.002
5.0
70
pA
VOO" 15V
10.0
0.003
10.0
140
pA
VIL" OV, VIH = VOD, 1101
MIN
, MAX
UNITS
VOO" 5V
< 1 pA
VOO" 5V
0.05
0.05
0.05
V
VOO" 10V
0.05
0.05
0.05
V
VOO" 15V
0.05
0.05
0.05
V
VIL" OV, VIH" Voo, 1101
< 1 IlA
VOO" 5V
4,95
4.95
5.00
4.95
V
VOO" 10V
9.95
9.95
10.00
9.95
V
VOO" 15V
14.95
14.95
15.00
14.95
V
Low Level Input. Voltage
VOO" 5V
1.5
2.25
1.5
1.5
V
INote 3)
VOO" 10V
3.0
4.50
3.0
3.0
V
6.75
4.0
4.0
7.0
5.50
7.0
V
11.0
8.25
11.0
V
3.5
3.5
INote 3)
VOO" 10V
7.0
VOO" 15V
11.0
VOO" 15V
-{).3
-10- 5
-0.3
-1.0
pA
0.3
10-5
0.3
1.0
pA
VIN = 5V
410
165
480
560
VIN = -5V
410
100
480
560
VIN = ±0.25V
410
155
480
560
n
n
n
VIN" 15V
ON Resistance
V
3.5
VOO" 5V
Input Current
V
4.0 '
2.75
High level Input Voltage
VIN = OV
RON
85°C
25°C
-40°C
CONDITIONS
VOO" 15V
VIH
C
CD4529BC (Note 2)
VOO " 5V, VSS" -5V
VOO = 7.5V, VSS" -7.5V
VIN" 7.5V
250
135
270
350
VIN = -7.5V
250
75
270
350
VIN = ±0.25V
250
100
270
350
VIN" 10V
410
165
480
560
VIN "0.25V
410
100
480
560
VIN" 5.6V
410
160
480
560
n
n
n
VOO = 10V, VSS" OV
n
n
n
VOO= 15V, VSS=OV
10FF
I nput-Output Leakage
Current
VIN" 15V
250
135
270
350
VIN" 0.25V
250
75
270
350
VIN" 9.3V
250
110
27.0
350
n
n
n
VSS" -5V, VOO" 5V
VIN" 5V, VOUT = -5V
±125
±0.001
±125
±500
nA
VIN " -5V, VOUT" 5V
±125
±0.001
±125
±500
nA
VIN'" 7.5V, VOUT" -7.5V
±250
±0.0015
±250
±1000
nA
VIN" --7.5V, VOUT" 7.5V
±250
±0.0015
±250
±1000
nA
VSS" -7.5V, VOO " 7.5V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not me"ant to imply that the devices should be operated at these limits. The tables of "Recommended Operating
Conditions" and "Electrical Characteristics" provide conditions for actual device operation.
Note 2: VSS
= OV unless otherwise specified.
Note 3: Switch OFF is defined as 1101 ::; 10 /-LA, switch ON as defined QY RON specification,'
7-57
01
N
CO
m
3:
........
(")
C
~
01
N
CO
m
(")
U
to
AC Electrical Characteristics
C\I
TA
m
It')
PARAMETER
'¢
c
u
......
:E
m
m
CD4529BM/CD4529BC
= 25°C, RL = 1 k[2, tr = tf = 20 ns, unless otherwise specified.
tpLH. tpHL
tPLH. tPHL
CONOITIONS
VIN to VOUT Propagation Oelay
Control to ~utPut Propagation Delay
TVP
MAX
UNITS.
ns
VOO = 5V
20
40
VOO = 10V
10
20
ns
VOO = 15V
8
15
ns
VOO = 5V
200
400
ns
VOO = 10V
80
50 .
160
ns
120
ns
VIN = VOO or VSS, CL = 50 pF.
VIN"; 10V
C\I
It')
"It
C
U
MIN
VSS = OV. CL = 50 pF
VOO = 15V
fMAX
Maximum Control Input
Pulse Frequency
Crosstalk, Control to Output
Noise Voltage
VSS = OV, CL = 50 pF
VOO = 5V
5
MHz
VOO = 10V
10
MHz
VOO = 15V
12
MHz
ROUT = 10 kQ. CL = 50 pF, VSS = 0
VOO = 5V
5.0
mV
VOO = 10V
5.0
mV
VOO = 15V
5.0
mV
f= 100 Hz, VSS=OV
VOO = 5V
24
nV/VCYcle
VOO" 10V
25
nV/VcYCiS
VOO = 15V
30
nV/VCYcle
f = 100 kHz, VSS = OV
VOO = 5V
12
nV/VCYcle
VOO = 10V
12
nV/VCYcle
15
nV/VCYcle
.VOO = 15V
Sine Wave (Oistortion)
VIN = 1.77Vrms Centered
0.36
%
atOV, RL = 10 kQ, f= 1 kHz,
VSS
ILOSS
BW
= -5V,
VOO = 5V
Insertion Loss,
VIN = 1.77Vrms'Centered
VOUT
I LOSS = 20 Log 10 - VIN
at OV, VSS = -5V, VOO = 5V
Bandwidth, -3 dB
RL = 1 kQ
2.0
RL=10kQ
0.8
dB
RL = 100 kQ
0.25
dB
RL=lMQ
0.01
dB
dB
VIN = l.77Vrms Centered
at 0 Vde, VSS = -5V, VOO = 5V
RL = 1 kn
35
RL=10kn
28
MHz
RL= 100kn
27
MHz
RL = 1 Mn
26
MHz
MHz
Feedthrough and Crosstalk,
VSS = -5V, VOO = 5V
VOUT
20 Lo9l0 ..- - - = -50 dB
VIN
RL = 1 kn
B50
kHz
RL=10kn
100
kHz
RL=100kn
12
kHz
RL = 1 Mn
1.5
kHz
7-58
Test Circuits and Switching Time Waveforms
Output Voltage
RON Characteristics
Noise Voltage
QUAN·TECH
Vss
Vss
VDD
MODEL
Vss
Frequency Response
2283
OR EQUIV
Crosstalk
Vss
~'"
A OR B
VDD
X. Y INPUT
,,---2.5VdC
VIN
T'' '
0 Vdc
'--'---2.S Vdc
Propagation Delay
Rl
Vss
VDD
Turn-ON Delay Time
":'
T
Rl
STX.STy.
A DR B
Cl
T
Cl
Vx
VIN
20m
VDD
VDD
Vss
VSS
STX. STy
VIN
VOUT
A OR 8
VOUT
VOUT
7-59
VIN '" VOO
Vx '" 0 Vdc
VIN'" 0 Vdc
Vx'" VOO
(J
m
C»
Typical Performance Characteristics
C\I
lI)
'lit
C
Typical RON vs VIN
(J
........
::i
m
C»
C\I
lI)
'lit
C
(J
w
u
z
250
225
v~s'o ~5~
200
VOoo5V
175
in 150
~
15
I
15
a:
125
100
75
50
1/
k'
«
Typical Noise Characteristics
35 ~
i
."
V
-8
-6 -4 -2
0
2
II
4
20 I- 10 Vde
'"
15
w
.
~
I'
III
6
5 Vdc
10
~
11111
0
i\
~
,.~
·ITIII
25
v~~I!lll~ vJc'
I"
w
VSS ° -1.5V
VOO ° 1.5V
10"
30
25
II
5
II
0
8
10
VIN -INPUT VOL TAGE (Vdcl
100
f -
Typical Insertion Loss!
Bandwidth Characteristics
.,
10k
lOOk
1M
10M
'IN -INPUT FREQUENCY (Hzl
7·60
100M
lk
10k
FREQUENCY (Hzl
lOOk
II
Analog Switches/Multiplexers ..........
~~
~National
~ Semicon(juctor
NW
OW
..........
Quad SPST JFET Analog Switches
BI·FET Technology
II
,." "T1
LF11331/LF12331/LF13331
4 normally open switches with disable
LF11332/LF12332/LF13332
4 normally closed switches with disable
..........
..... .....
LF11333/LF123331LF13333
2 normally closed switches and 2 normally open switches with disable
OW
LF11201/LF12201/LF13201
·4 normally closed switches
NW
NN
LF11202/LF12202/LF13202
4 normally open switches
CJ)I
(I)."
general description
These devices are a monolithic combination of bipolar
and JFET technology producing the industry's first
one chip quad JFET switch. A unique circuit technique
is employed to maintain a constant resistance over the
analog voltage range of ±1 OV. The input is designed to
operate from minimum TTL levels, and switch operation
also ensures a break·before·make action.
•
•
•
•
•
•
Small signal analog signals to 50 MHz
Break-before-make action
tOFF < tON
-50 dB
High open switch isolation at 1.0 MHz
<1.0nA
Low leakage in "OFF" state
TTL, DTL, RTL compatibility .
Single disable pin opens all switches in package on
LFl1331, LFl1332, LFl1333
• LFl1201 is pin compatible with DG201
features
•
•
•
Analog signals are not loaded
Constant "ON" resistance for signals up to ±10V and
100 kHz
Pin compatible with CMOS switches with the advantage of blowout free handling
connection diagrams
01
51
VII
-Vu
52
02
LFI1332/LFI23321LFI3332
IN,
IN.
04
S4 DISABlE tYee:
53
IN,
01
51
S2
51
-Vu
OJ
IN,
IN,
01
51
VII
52
02
Order Number LF12201N, LF13201N,
LF12202N,LF13202N,LF12331N,
LF13331N, LF12332N, LFI3332N,
LFI2333N or LF13333N
Se. NS Package N16A
IN2
TOP VIEW
VII
-VEE
TOPYIEW
Order Number LF11201D, LF12201D,
LF13201D, LF11202D, LF122020,
LF132020,LF11331D,LF12331D,
LF13331D, LF11332D, LFI2332D,
LF13332D, LF11333D. LF12333D
or LFI3333D
See NS Package D16C
LF11201/LF12201/LF13201
01
VII -VEE
L F 11333/LF12333/LF 13333
TOPYIEW
TOP VIEW
IN,
These devices operate from ±15V supplies and swing a
±10V analog signal. The JFET switches ~re designed for
applications where a dc to medium frequency analog
signal needs to be controlled.
(Dual-In-Line Packages) (All Switches Shown are For Logical "0")
LFI1331/LFI2331/LFI3331
IN,
LF 11202/LF 12202/LF 13202
IN,
Dl
51
-Vu
VII
52
02
• TOP VIEW
test circuit and schematic diagram
AI
I ...
ANALOG -;--
INPUT!V ... I
r-------,I _ .~:
Is
0
~~
I
-'-w*1
LOGIC
INPUT V
.!!.t-o ':"
Iv.l~
I
__ ..1
ILDGIC"D""DI~ I
(LOGIC-I" .·lOVI
I
..
-Vu
tYee
LOGIC
_. ___
I
IN
III
+--+-+f:::",,:::
'---f-ii--.J
IU~_15V
J5
ICC 'tI5V
v.o----1_-+_--'
FIGURE 1. Typical Circuit for One Switch
FIGURE 2: Schematic Oiagram INormally Open)
7-61
IN,
::::!. -"
(I) .....
cnW
W
..W
absolute. maxi,mum ratings
;
Positive Supply": Negative
Reference Voltage
Logic Input Voltage
:Analog Voltage
Su~ply
(Vee-VEEJ
VEE
s:
s:
Operating Temperature'Range
·LFl1201, 2 and LFl1331, 2, 3
LF12201, 2 and LF12331, 2, 3
LF13201,2 and LF13331, 2, 3
Storage Temperature
_Lead Temper,ature (Soldering, 10 seconds)
36V
VEE
V R -4.0V V,N
VA Vee +6V; V A
s:
Analog Current
s: V R S:·Vee
s: V R +6.0V
s: VEE +36V
JI AI<20·mA
Power Dissipation (Note 1)
Molded DIP (N Suffix)
Cavity DIP ID Suffix)
.
SOOmW
900mW
..
electrical characteristics
(Notes 2, 7)
LF12331/2/3
-
LF11201/2
CONDITIONS
MIN
"ON" Resistance
Resist~nce
RON Match
"ON"
VA
Analog
'S(ON)
+
VA"" 0,1 0
"
TA
1 mA
= 25°C
TA "',25~C
Matching
Rang~ ,
±10
Leakage Current in "ON" CondItion
Switch "ON," Vs;::: Va"" ±10V
TA • 25°C
Source Current in "OFF" Condition
Switch "OFF," Vs;::: +10V,
TA = 2SoC
I
Va' -10V
IO(OFFI
.Drain Current in "OFF" Condition
Switch "OFF," Vs = i 'OV,
Vo • -10V
TVP
MAX
150
200
20G
300
5
20
TA "~'25°C
Logical "'" Input Voltage
VIN!..
Logical "0" Input Voltage
IINH
Logical "l"lnput Current
V IN :: 5V
TA =2St.'C
lIN!..
Logical "0" Input Current
VIN .:: 0.8,
TA " 25°C
TVP
UNITS
MAX
150
200
250
350
10
50
n
n
n
. ttl
V
3
5
100
0.3
3
10
30
nA
nA
0.4
3
5
100
0.4
10
30
nA
nA
10
30
nA
nA
0.1.
3
V,NH
MIN
±10
.11
0.3
'OION)
IS(OFFI
LF12201/2
LFI3331/2/3
LF13201/2
LF11331/2/3
PARAMETER
SYMBOL
RON
-ssoe to +12Soe
-2Soe to +8Soe
oOe to +70oe
-6Soe to +lS0oe
300°C
3
.5
0.1
3
100
2.0
2.0
V
O.S
0.8
3.6
10
25
3.6
0:1
1
V
40
100·
pA
pA
.0.1
1
pA
pA
tON
Delay Time
Vs:: ~ 10V, (Flgure3J
TA = 25·'C
500
500
os
tOFF
.Delay Time "OFF"
Vs = ±10V, (Figure3J
TA = 25·'C
90
90
os
tON -tOFF
Break·Before·Make
Vs:: !10V, (Figure3J
TA =25·C
eo
80
os
CSIOFF)
Source Capacitance
Switch "OFF:' Vs :: ±10V
' TA = 2SOC
4.0
4.0
pF
Switch "OFF," Vo = ±10V
TA • 25°C
3.0
3.0
pF
~witch
TA • 25°C
5.0
5.0
pF
dB
'~ON"
CoIOFF)
Drain Cap,acltance
CsION) +
Active Source and Drain
~apacitance
"ON," Vs :: Vo = OV
"
'.
COIONI
ISOIOFF)
'''OFF'' Isolation
IFigure 4), (Note 31
T;. • 2SoC
-60
-SO
CT
Cros!;talk
(Figure 4), INote 31
TA • 25··C
-65
-65
dB
SR
Analog Slew Rate
(Note 41
TA • 25°C
. 50
60
Vips
lOIS
Disable Current
(Figure 5), (Note 51
TA = 25°C
0.4
0.6
1.0
1.5
3.0
4.2
5.0
·7.S
6.0
2.0
2,8
4.0
6.0
' 4.5
6.0
9.0
"
I••
IA
Icc
Negative Supply Current
Reference Supply Current
Positive Supply Currant
All Switche:; "OFf," Vs r ±10V
All Switches "OFF," Vs :: ±10V
All Switches "OFF," Vs:: ±10V
'TA = 2SoC
T A =25°C
TA
= 2SoC
6.3
0.6
0.9
1.5
2.3
: mA
mA
7.0
10.5
mA
mA
3.8
5.0
7.5
mA
mA
1.0
9.8
.9.0'
13.5
mA
mA
4,3
2.7
Note 1: For operating at highl temperature ~he, molded DIP products must be derated based on a +100°C_ maximum junction temperature and a
thermal resistance of +150°C/W, devices in the cavity DIP are based on a +150°C maximum junction temperature and are derated at +100°C!W:
Noto 2: Unless otherwise specified, Vee = +15V, VEE = -ISV, VR = OV. and limits apply for -SSoe:5. TA:5. +125"C for the LFl1331,2,3 and
the LF11201,2, -2Soe:5. TA :5. +8Soe for the LF12331 ,2.3 and the LF12201,2, and Ooe:5. TA:5. +70o e for the LF13331,2,3 and the
LF13201,2.
.
.
Note 3: These parameters are limited by the pin to pin capacitance of the package.
Note 4: This is the analog signal slew rate above which the signal is distorted as a result of finite intern~1 slew rates.
Note 5: All switches in the device are turned "OFF" by saturating a transistor at the disable node as shown in Figure 5, The delay times will be
approximately equal to the tON or tOFF plus the delay introduced by the external transistor.
Note 6: This graph ind,icates the analog current at which 1% of the ,analog current is lost when the drain ~s positive with respect to the source.
7·62
II
~~
..........
test circuit and ,typical performance curves
Delay Time. Rise Time. Settling Time, and Switching Transients
.ISV
-ISV
I
VAl •••IOV
v" 5.~JU1
l
VA =+SV
L
1\
f-
\
\
v"
f-
I'.
V'N
JA .Jv
I
lO}
I
V~N
~
~.
'"
f-
f-L
VAl.
Vo
I
L
I
\
f--
J,.
,
V'N
20011S/dlV
20011Sfdlv
20011S/dlv
additional test circuits
v"
3DV
'ISV
-ISV
OV
L-~
________~--~
Va = .IDV·
lOV
BOV
'---!------'----I1-"4'-- , .
IOFF~,
.----+-.----------+
Vo
-BOV . -........
10k
.....'V'o"r---1"'-r
i
4001--+h4
Supply Current
Supply Current
of Fi!Jl!re 5
"<
8.0
I
~
oS
I
-60
>
6.0
4.0
B.D
oS
1
60
.
NEGATIVE (lEE) _
•
~
,4.0 I-~k::--+--+---t="---i
0:
2.0
it:
-80
Ol
2.0
REFErENCE
rR)
f--F-t--:-+-=:l::~
OL....~'-.......J_----'_---'-_---'
50
50
100
1M
150
Supply Current
Ci
Switch Leakage Currents
20
1-ttItt1t-+HHII!HtHl!H+IJ":!-.llJl~.JJtIlIII
~ '0
0.6
1
z
~
i'O,OOOOEiiii
~
IStONI
I
Uk
lOll
lOOk
I.OM
-100
50
50
Slew Rate of Analog Voltage
Above Whicp Signal LOB.ding
Occurs
0.4
~
100
0.2
f.,,Lb-'F--t-"=,.::='-J
0.4
L-_'------'_----'_---"-_--'
10
6.0
2.0
2.0
6.0
Vee =I'5V
15V
if
40
--I--
u:
20
---
~
-3
'"
-6
-9
o
-100
I.
'""c
I:
50
50
TEMPERATURE ( C)
100
150
-16
oS
;;;
.- -
g
iii
ct
10M
~t+CD(ON:
CS(OFFI
-12
100M
f
6.0
2.0
"\
-8.0
7-64
Vee" 15V
VEE; '" -15V
2.0
6.0
10
Logical"1"" Input Bias Current
61
".
8.0
e-----
-"
"-1"-...
-4.0
4.0
"
2.0
.'"
r......
6.0
"
'"'"
'"
o
-100
_
10
50
50
100
TEMPERATURE f C)
FREQUENCY (Hz)
./
I
CDIOFFI
10
10
L....--L....wu.J.J..W_-'-~.LLJ.w
1M
:::-
2.0
Maximum Accurate Analog
Current vs Temperatura
cc
VEE"
->
60
4.0
-20
."
~
"~
VA (VOLTS)
(NOTE
..::l
6.0
VA (VOLTS)
Small Signal Response
150
8.0
u
;:"
0.2
150
50
100
I
TEMPERATURE ( C)
'0
~.
~
'DO
80
50
Switch Capacitances
,--r---:-:--=,--,----,
TEMPERATURE ( C)
FREQUENCY (Hz)
-tOo
25
~
,
100
20
+ IOtONI
'0
10
15
Switch Leakage Current
10,000
4.0
10
SUPPLY VOLTAGE ('VI
oS
'"'"
'"
50
r.:---::-=-".---;-;-;;----,,""'''''''
100,000
.
10M
FREQUENCY 1Hz)
TEMPERATURE ( CI
150
-100
Vee'" 15\1'
VEE" 15V
VIN "'+5.0V
VR ;.OV
-- -
'\
\
..........
50
-
50
TEMPERATURE
r-100
rei
150
II
application hints
GENERAL INFORMATION
LEAKAGE CURRENTS
These devices are monolithic quad JFET analog switches
with "ON" resistances which are essentially independent
of analog voltage or analog current. The leakage currents
are typically less than 1 nA at 25°C in both the "OFF"
and "ON" switch states and introduce negligible errors
in most applications. Each switch is controlled by mini·
mum TTL logic levels at its input and is designed to turn
"OFF" faster than it will turn "ON." This prevents two
analog sources from being transiently connected together
during switching. The switches were designed for appli·
cations which require break-before-make action, no
analog current loss, medium speed switching times and
moderate analog currents.
The drain and source leakage currents, in both the ON
and the OF F states of each switch, are typically less than
1 nA at 25°C and less tilan 100 nA at 125°C. As shown
in the typical curves, these leakage currents are dependent on power supply voltages, analog voltage, analog current and the source to drain voltage.
II
DELAY TIMES
OW
The delay time OFF (tOFF) is essentially independent of
both the analog voltage and temperature. The delay time
ON (tON) will decrease as either (Vce - VA) decreases
or the temperature decreases.
CJ)I
POWER SUPPLIES
The voltage between the positive supply (Ved and
either the negative supply (VEE) or the reference supply
(V R ) can be as much as 36V. To accommodate variations in input logic reference voltages, V R can range
from VEE to (Vee - 4.5V). Care should be taken to
ensure that the power supply leads for the device never
become reversed in polarity or that the device is never
inadvertantly installed backwards in a test socket. If one
of these conditions occurs, the supplies would zener an
interal' diode to an unlimited current; and result in a
destroyed device.
Because these analog switches are JFET rather than
CMOS, they do not require special handling.
LOGIC INPUTS
The logic input (IN), of each switch, is referenced to two
forward diode drops (1.4V at 25°C) from the reference
supply (V R) which makes it compatible with DTL, RTL,
and TTL logic families. For normal operation, the logic
"0" voltage can range from 0.8V to -4.0V with respect
to V R and the logic "1" voltage can range from 2.0V to
6.0V with respect to V R, provided V IN is not greater
than (Vee - 2.5V). If the input voltage is greater than
(Vee - 2.5VI. the input current will increase. If the
input voltage exceeds 6.0V or -4.0V with respect to
V R, a resistor in series with the input should be used to
limit the input current to less than 1 DOpA.
SWITCHING TRANSIENTS
When a switch is turned OFF or ON, transients will
appear at the load due to the internal transient voltage at
the gate of the switch JFET being coupled to the drain
and source by the junction capacitances of the JFET.
The magnitude of these transients is dependent on the
load. A lower value RL produces a lower transient volt·
age. A negative transient occurs during the delay time
ON, while a positive transient occurs during the delay
time OFF. These transients are relatively small when
compared to faster switch families.
ANALOG VOLTAGE AND CURRENT
Analog Voltage
Each switch has a constant "ON" resistance (RON) for
analog voltages from. (VEE + 5V) to (Vee - 5V). For
analog voltages greater than (Vee - 5V), the switch will
remain ON independent of the logic input voltage. For
analog voltages less than (VEE + 5V), the ON resistance
of the switch will increase. Although the switch will not
operate normally when the analog voltage is out of the
previously mentioned range, the source voltage can go to
either (VEE + 36V) or (Vee + 6V), whichever is more
positive, and'can go as negative as VEE without destruction. The drain (D) voltage can also go to either
(VEE + 36V) or (Vee + 6VI. whichever is more positive, and can go as negative as (Vee - 36V) without
destruction.
DISABLE NODE,
This node can be used, as shown in Figure 5, to turn all
the switches in the unit off independent of logic inputs.
Normally, the node floats freely at an internal diode
drop ("" 0.7V) above V R' When the external transistor in
Figure 5 is saturated, the node is pulled very close to V R
and the unit is disabled. Typically, the current from the
node will be less than 1 mAo This feature is not available on the LFl1201 or LFl1202 series.
r----I
I
Analog Current
With the source (S) positive with respect to the drain
(DI. the RON is constant for low analog currents" but
will increase at higher currents (>5 mAl when the FET
enters the saturation region. However, if the drain is
positive with respect to the source and a small analog
current IQsS at high analog currents (Note 6) is tolerable,
a low RON can be maintained for analog currents greater
than 5 mA at 25°C.
,
,,.
FIGURE 5. Disable Function
7-65
3!3!
..........
NW
OW
..........
-n-n
..........
.....
.....
NW
NN
'"
CD-n
::::! ......
CD
.....
f/)W
W
~
typical applications
Sample and Hold with Reset
HOLD
'~'~---------~i
~
NN
MO
MN
,....
,....
I
,.... ,....
LLLL
MO
MN
,....
,....
,.... ,....
LLLL
"I
~
I I
~~
,.... ,....
I
VIN
I
1 - - -lFl1331
---j'I
I
II
I110
I
I
Lf--1
114
'I - - - - - 1
~Lt>-I
I
lF155
2
J
I
L.. _ _ _
-
l-ovov,
+
rOM
":'
~~
I
-=
3pF
Programmable Inverting Non-Inverting Operational Amplifier
r--7,';';;;'---.
J
lOOk
141
I
,,'
V'N
NON·INVERTING
Programmable Gain Operational Amplifier
r--~;;;----'
14
15
10k
1M
V'N
tOOk
500k
GAIN SELECT
7·66
~"""-oVOUT
typical ap PI"Ications
.
(con't)
r ____DemultiPlexe'
lFl1J31
~~
..........
..... .....
Multiplex'er/Mixer
I\)W
OW
100>
1
1
1
1
':'
1
,
toOk
1
1
1
I
1
1
I
. Lt4-tt.J
It-}ttj ' ~
- - 0 ANALOG
OUTPUT
7·67
00'
CDr..,"11
......
CD .....
cnW
W
_
~
~1112
I
1
1
lOOk
I
I
I I I
I
"~--"
,I
1 I 1
~17
,I _ I 1 I
1
1
1
"I
~
~:.I"
lOOk
I
I\)j')
r------
~~l
cw)
('I)
('1)0
typical applications (con't)
,..«1)
,..'LL'"
........~
NN
('1)0
,.. ,..
('I)N
,..
LL
LL"'"
........
......
,.. ,..
('1)0
('1)(\1
,..
,..
U:U:
...J..J
Chopper Channel Amplifier
I
•
10k
'frftl ~fo,-
1•• F
10k
V"~I'~ ~
. "J J ['I!'
. /
~
' .. 1 I 1
I' 1 1
I,
II
II
,.
1 1 1
1
II1
L___ ~______ J I
1M
I
L _____ ~~~_____ J
-sri
Self·Zeroing Operational Amplifier
ZERO
INPUTS
7·68
II
"T1"T1
...........
typical applications (con't)
Programmable I ntegrator with Reset and Hold
Zk
..... .....
NW
OW
..........
II
1--
"T1"T1
..........
..........
SELECT~
OW
.
NW
NN
...
I
SElECT~
.~
C/)I
RESET~
INTEGRATE
11
(1)"T1
CD .....
.......
:!......
L~3~
tn(N.
W
....W
ANDHDLO~
Staircase Transfer Function Operational Amplifier
7-69
cw)
('I)
en
typical applications (can't)
'('I)
.... (1)
~.a:
LL
Q)
DSB Modulator-Demodulator
....1(1)
...
NN
SL 1S
('1)0
('I)N
........
r-ft'~"l
U:U:
....1....1
1
I
I 1
......
'I"!'" 'P.'"
('1)0
.........
U:U:
('I)
N .
I,
I
I
I.·
'---';;'1--0'"
I I I I
1 I,
....1 .....1
I
r-
"
DEMODULATOR
MODULATOR
7-70
1
I"
~National
Analog Switches/Multiplexers
~ Semiconductor
LF1150S/LF1250S/LF1350S
S-Channel Analog Multiplexer
LF11509/LF12509/LF13509
4-Channel Differential Analog Multiplexer
BI-FET Technology
general description
The LF11508/LF12508/LF13508 is an 8-channel
analog multiplexer which connects the output to 1 of
the 8 analog inputs depending on the state of a 3-bit
binary address_ An enable control allows disconnecting
the output, thereby providing a package select function_
connect a pair of independent analog inputs to one of
any 4 pairs of independent analog outputs_ The device
has all the features of the LF 11508 series and should be
used whenever differential analog inputs are required_
features
This device is fabricated with National's 81-FET technology . which provides ion-implanted JFETs for the
analog switch on the same chip as the bipolar decode
and switch drive circuitry_ This technology makes
possible low constant "ON" resistance with analog
input voltage variations_ This device does not suffer
from latch-up problems or static charge blow-out
problems associated with similar CMOS parts. The
digital inputs are designed to operate from both TTL
and CMOS levels while always providing a definite
break-before-make action.
•
•
•
•
•
•
•
•
.'.
The LF1150siLF1250S/LF1350S is a 4-channel differential analog multiplexer_ A 2-bit binary address will
•
JF ET switches rather than CMOS
No static discharge blow-out problem
No SCR latch-up problems
Analog signal range 11 V, -15V
Constant "ON" resistance for analog signals between
-11V and 11V
"ON" resistance 380 n typ
Digital inputs compatible with TTL and CMOS
Output enable control
Break-before-make action: tOFF = 0.2 I-IS; tON
21-1s typ
Lower leakage devices available
functional diawarTis and truth tables
LFl150B/LF1250B/LF13508
A2
EN
51
S7
56
55
AI
S4
S3
AD
S2
Sl
SWITCH
EN
A2
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H,
L
H
H
H
H
L
H
H
H
H
51
S2
53
54
55
56
57
58
L
X
X
X
NONE
Al
AO
ON
L Fll509/L F12509/L F13509
AI
EN
AD
-VEE
GND
vee
D8
S48
538
S2B
SIB
S4A
S3A
S2A
SIA
DA
.7-71
EN
Al
AO
L
H
H.
H
H
X
X
L
L
H
H
L
H
L
H
SWITCH
PAIR ON
Nqne
51
S2
S3
S4
cx)'cn
00
absolute maximum rat.ings
lI)lI)
('1)('1)
,.... ,....
LLLL
..J..J
..............
'coO)
00
lI)lI)
NN
lLlL
..J..J
Positive Supply - Negative Supply (Vee - VEE)
Positive Analog .Input Voltage (Note 1)
Negative Analog Input Voltage (Note 1)
,.... ,....
lLlL
..J..J
LF12508.
LF13508.
LFl1509
LF12509
LF13509
36V
36V
36V
Vee
-VEE
Vee
-VEE
Vee
-5V
Vee
-5V
1151 < 10mA
IISI < 10mA
"
Vee
-VEE
Positive Digital Input Voltage
Vee,
-5V'
Negative Digital Input Voltage
Analog Switch Current
IISI<10mA
"
Power Dissipation (PO at 25° e) and Thermal
Resistanc~, (8jA). (Note 2)
..............
coO)
00
lI)lI)
LFl1508.
Molded DIP (N)
eavity DIP (D)
-
r-
Po
8jA
Po
8jA
Maximum Junction Temperature (TjMAX)
- 55° C
1500 e/W
900mW
900mW
900mW
1000 e/W
100°C/W
100°C/W
1500 e
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 seconds) .
500mW
-
-
110°C
:S TA:S; +125°C
100°C
Ooe:S;TA:S;+70°C
-:-25°C:S; TA:S; +85°C
~5°C to +150°C
~5°C to +150°C
300°C
~5°e to +150°C
300°C
300°C
..
electrical characteris,tics
(Npte 3)
.'
SYMBOL
PARAMETER
LFllS08. LFllS09
CONDITIONS
MIN
RON
-....--,
LOGIC
INPUT
10M,::,
-r'OPF
-15V
FIGURE 1. Transition Time
7·73
18
ac test circuits and switching time waveforms
(Continued)
ISY
Yee
SI
lF11508 S2-S81-<0---.
ENA8lE
lk
INPUT
-ISV
YDUT
~J
10pf
FIGURE 2. Enable Time.
15Y
lOY
Yee
EN
A2
..-......""'<:'""'i AI
S2-S71-<0-.....
YDUT
Lf115D8
lk~
INPUT
DRIVE
J'OPf
.
. ,
3V~
OY
-15V
FIGURE 3. araak·Safora-Maka
transition times and transients
.. VA= 10V
VA
a
5V
Y,N
>
>
~
~
GND
Yo
aND
. lpS/DIV'
lpS/DIV
VA",-5V
GND
aND
Y,N
.~
,~
1 pS/DIY
1 pS/DIV .
Test Circuit
GNa
ISY
Vee
>
EN
~
Al
_-~~Al
lf115D8
AD
-ISV
1 ps/DIV
7·74
II
3!3!
............
typical performance characteristics
800
400
700
-i5
360
a:
J40
r-I~=ioo"~
VCC -ISV
VEP-1SV
IA"O
TA' 2SoC
320
. . . . r--
500
V'
400
00
U)(X) .
..............
TA = 25 C
VCC = 15V
VEE = -15V
6QO
500
300
U'I(11
700
VCC = 15V
600 r-VEE=-15V
380
£
i5
a:
"ON" Resistance
"ON" Resistance
"ON" Resistance
-
....... i-'""
"
c
a:
I-""
II
"T1"T1
............
I-'
400
.~
300
200
200
100
100
NN
U'I(11
00
COOl
..............
0
300
-10 -8 -6 -4 -2 0
4
2
-55 -35 -15 5
8 10
6
25' 45 65 85 105 125
-2
TEMPERATURE I C)
ANALOG INPUT VOLTAGE IV)
II
"T1"T1
............
'0
-I
ANALOG INPUt CURRENT ImA)
WW
(J1(J1
Switch Leakage
Switch Leakage
Currents
Currents
10
1000
Vcc = 15V
,-VEE =-15V
TA=25"C
1
~
~
...
ISIOFF)
~
ffi
a:
~ -0.1
";2
ISIOFF)
;
-5
10
15
-15 -10
ANALOG VOLTAGE IV)
3.5
r-- 'TRA~
~
w
";::
1.5
~
~V
10
-5
:;..0"
0.1
""iSIOFFI
15
-55
~V
-25
35
65
95
125
TEMPERATURE rC)
Enable Delay Times
"OFF" Isolation and
(Figure 2)
Crosstalk
-30
vjc = 15~
I--- VEE" -15V
~
~
-IOIOFFI
ANALOG VOL TAGE IV)
Switching Times
(Figures 1 and 3)
, VCIC = 15~
r- VEE = -15V
I
2.5
m
0.01
10.
-15' -10
IOION)
w
-1
-10
H
10
i
IOION)
-.......,;IOIOFF)
100
~
IOIO~F)
COJ»
100
IO:ON)
0.1
00
Switch Leakage
Currents
/
-40
'ONEV
-50
~
'"
/
z
~
/"
0.5
-60
c
;:: -70
'OPEN
V
-80
-90
-100 IL
'OFFEN-
-110
-55
~25
35
65
95
125
-55
-25
35
TEMPERATURE I' C)
95
10k
125
TEMPERATURE 1°C)
10
~
VCC = 15V
VEE=-15V VLOGIC = OV
..........
I
"
lEN
-
r-
u
;:"
'-.. r- i"""-- ........
i3
-4,,"",OTO S/. OR A/a
NN
U::U::
..J..J
............
CX)CJ)
00
,.. ,..
,..
,...
lI)lI)
AD
A1
MM74C19l
A2
LLLL
..J..J
EN
t5V
-15V
FIGURE 10. A 16·Channel Multiplexer with Sequential Multiplexing
15V
-tSV
22M":"
51
22M
52
53
S4
:1:
5;
T
52
sj
I
s4
L
AD
Ova
Ch
1/4LF13333
•
At
~
CHANNEL
SELECT
::=n-
L--+-o-1SV
ZEAD PULSE
•
•
•
Differential multiplexer disabled during auto zeroing
Minimum zeroing pulse width will depend upon the integrator R1C
This scheme provides input offset adjust especiallv useful with high gain connections. The device, LF352,
provides pins for output offset adjust. For more details, see LF352 data sheet.
FIGURE 11. 4-Channel Differential Multiplexer with Auto Zeroed Instrumentation Amplifier
7·82 •
typical applications
....
....
....
II
."."
(Continued)
15V -15V
01(.1'1
00
COCO
................
IBM
II
51
."."
53
54
NN
00
COCO
................
Ik
0101
s; O-:.-Cl"""""tl--.
Sz
S3
II
."."
e".)e".)
0101
L. ____ _
5V
200
O.1J.1f
0
Aa
AI
13
"
CLR
CLOCK
MSB
5V
5V
5.
DIGITAL
OUT
CLK
1I2MM74C74
5UOpF
LS8
T
10k
'::"
MM74C09
5V
•
•
•
fCLOCK max = 200 kHz
The LF352 instrumentation amplifier is auto zeroed during offset correction cycle of the lF1~300 AID
The system accuracy will mostly depend on the instrumentation amplifier gain linearitY
FIGURE 12a. 4·Channel Differential MUltiplexer ,with Auto Zeroed Instrumentation Amplifier and 12·8it AID Converter
DC
PD
..JhL-___-..JnL--____r-t.
RR _ _ _ _
p~~~
n
..J
...,L_____....Jn
Aa _______________
r
r
L..-._ _ _---I
~
po: Polaritv Detection
OC: Offset Correction
RR: Ramp Reference
For more details. see LF13300 data sheet
AI _______________________________
ENABLE
.J
~P3'n -Ia
u
v.
u
Av IS3- Sj)
Vo
L
\
FIGURE 12b. System Timing Diagram for Differential MUX
7·83
00
COJ»
LF1150S/LF12508/LF1350S,
LF11509/LF12509/LF13509
~
sa
S5
OUT
::T
QI
3
III
ct,
n
Q.
m'
IQ
.@
3
(II
....
.~
A2
.,
AU
.-VEE
.NO
LF1150B/LF1250B/LF1350B
schematic diagrams
II
-n-n
..........
.....
.....
(Continued)
U1Cll
00
CD 00
"-"-
II
-n-n
..........
;;;0-;............
~-----.--~+-~4-----------~-4-------4~~
1\)1\)
(J1(Jl
00
CD 00
"-"II
-n-n
..........
(,,)(,,)
UlUl
00
CDsn
11
~
~
en
0
It>
~
LL
:::!
en
0
It>
;:!
LL
~
:::!
en
0
It>
~
lLoJ
tj
.,o
Q
(,
r---------~--+-~----~_.--------~~~
~--'''_r'
7-85
Section 8
Sample and Hold
r
Sample and Hold ::2
lI?'A National
CO
.......
~ Semiconductor
LF198/LF298/LF398
Monolithic Sample and Hold Circuits
(X)
r
."
N
general description
features
The LF198/LF298/LF398 are monolithic sample and
hold circuits which utilize BI-FET technology to obtain
ultra-high dc accuracy with fast acquisition of signal and
low droop rate_. Operating as a unity gain follower, dc
gain accuracy is .0.002% typical and acquisition time is
as low as 6J.1s to 0.01 %. A bipolar input stage is used to
achieve low offset voltage and wide bandwidth. Input
offset adjust is accomplished with a single pin and do~s
not degrade input offset drift. The wide bandwidth
allows the LF 198 to be included inside the feedback
loop of 1 MHz op amps without having stability
problems. Input impedance of 10 10 n allows high
source impedances to be used without degrading
accuracy.
• Operates from ±5V to ±18V supplies
•
."
W
Less than 10J.ls acqu isition time
• 0.5 mV typical hold step at Ch
•
=O.OlJ.1F
Low input offset
• 0.002% gain accuracy
•
Low output noise in hold mode
•
Input characteristics do not change d!-lring hold mode
•
High supply rejection ratio in sample or hold
• Wide bandwidth
L,ogic inputs on the LF198 are fully differential with
low input current, allowing direct connection to TTL,
PMOS, and CMOS. Differential threshold is l.4V. The
LF198 will operate from ±5V to ±18V supplies. It is
available in an 8-lead TO-5 package.
OFFSET
r-:--
~M
r,
• TTL, PMOS, CMOS compatible logic input
P-channel junction FET's are combined with bipolar
devices in the output amplifier to give droop rates as
low as 5 mV /min with a lJ.1F hold capacitor. The JFET's
have much lower noise than MOS devices used in previous 'designs and do not exhibit high temperature
instabilities. The overall design guarantees no feedthrough from input to output in the hold mode even
for input signals equal to the supply voltages.
functional diagram
CO
(X)
.......
I
I
I
I
I
3
-------------,I
z
I
OUTPUT
I
+
I
I
,
I
LOGlc!!>1
. I
LOGIC 11
REFERENCE
/'
I
I'
I
I
_ _ _ _ .....l
300
J/'
L _________ _
6
HOLD
CAPACITOR
typical applications
Acquisition Time
Typical Connection
I
Y'
10
=--~
YIN' 0 TO ,lOY
Tj '25'&
1%
.......
0.1%
0.01%
OUTPUT
100
1000
0.001
J I Nil
0.01
HOLD CAPACITOR I"Fl
8-1
.0.1
CO
(X)
co
0)
M
LL.
.;.J
........
co
0)
C\I
LL.
..J
........
,absolute maximum ratings
Supply Voltage
±18V
Power Dissipation (Package Limitationl (Note 11
500mW
Operating Ambient Temperature Range
LF198'
--s5"c to +125"C
LF298
-25°C to +85°C
LF398
O°C to +70°C
Storage Temperature Range
--55°C to +150°C
electrical characteristics
co
u:
..J
(Note 3)
'PARAMETER
0)
Input Voltage
Equal to Supply Voltage
Logic To Logic Reference Differential Voltage
+7V, -30V
(Note 21
Output Short Circuit Duration
Indefinite
Hold Capacitor Short Circuit Duration
10 sec
Lead Temperature (Soldering, 10 secondsl
300"C
LF198/LF298'
CONDITIONS
Input Offset Voltage, (Note 61
MIN
TYP
MAX
3
5
Tj = 25°C
Full Temperature Range
Input Bias Current, (Note 6)
MIN
5
Tj = 25°C
full Temperature Range
Input Impedance
Tj = 25°C
10 10
Gain Error
Tj = 25°C, RL = 10k
0,002
Feedthrough Attenuation Ratio
Tj - 25°C, Ch = O,Ol"F
25
75
MAX
2
7
UNITS
mV
mV
10
10
, 50
nA
nA
100
I
n
1010 ,
0,004
0,005
0,02
Full Temperature Range
86
LF398
TYP
96
80
0,01
0,02 .
.%
%
dB
90
at 1 kHz
Output 'Impedance
0,5
Tj = 25°C, "HOLD" mode
0,5
Full Temperature Range
4
n
4
6
n
"HOLD" Step, (Note 4)
Tj = 25°C, Ch = O.Ol"F, VOUT = 0
0.5
2,0
1.0
2,5
mV
Supply Current, (Note 61
Tj~25°C
4.5
5,5
4,5
6,5
mA
Logic and logiC Reference Input
Tj = 25°C
2'
10
2
10
Tj = 25°C, (Note 5)
Hold Mode
30
100
30
,200
dVOUT = 10V, Ch = 1000 pF
Ch = O,Ol"F
4
20
Current
Leakage Current into Hold
Capacitor (Note 6)
Acquisition Time to 0.1 %
Hold Capacitor Charging Current
VIN,-VOUT=2V
Supply Voltage Rejection Ratio
VOUT=O
80
110
Differential Logic Threshold
'Tj = 25°C
0,8
1.4
pA
4
20
/J.S
/1S
5
mA
2,4
80
110
0,8
1.4
dB
2,4
V
Note 1: The maximum juncti,on temp~rature of the LF198 is 150°C, for the LF298, 115°C, and for the LF398, 100°C, W'hen operating at
elevated ambient temperature, the TO-5 package must be derated based on a thermal resistance (GljA)'of 150°CIW,
Note 2: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the
supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below
the positive supply and 3V above the negative supply,
Note 3: Unless otherwise sp.x,ified, the following conditions apply, Unit is in"sample" mode, Vs = ±15V, Tj = 2SoC, -11,5V
VIN +11,SV,
Ch = 0.01"F, and RL = 10 kn, Logic reference voltage = OVand logic voltage = 2,5V,
' .
Nota 4: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an
additional 0,5 mV step with a 5V logic swing al'd a O,01"F hold capacitor, Magnitude of the hold step is inversely proportional to hold capaci-
s:
,tor value.
s:
'
Nota 5: Leakage current is measured at a junction temperature of 2SoC. The effects of junction temperature rise due to power dissipation or
elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input
signal range.
Note 6: These parameters guaranteed over a supply voltage range of ±5 to ±18V.
typical performance characteristics
Aperture Time*
25(1
]
~
~
225
200
115
150
125
100
75
50
25
o
vl<)'l~v
IY
Y
/1
"rou~~T
-
NEGATIVE
""-
I~~~~/,
/'
./
--
-50 -25 0
L
"VIN '10Y
./
./
10
;;
.5
10
;;
.5
..g;
'"
:i
~
±1
ffi
'"~
-10
/POSITIVE_
INPUT
/
25
Dynamic Sampling Error
capacitor Hysteresis
100
S~EP I -
10
50 75 _100 125 150
JUNCTION TEMPERATURE (OCI
SAMPLE TIME (m.1
·See definition
8-2
100
INPUT SLEW RATE (V/ml)
typical performance characteristics (con't)
"Hold" Settling Time·
Hold Step
Output Droop Rate
100
100
V+'V- o I6V
l.a
1.6
s:
iii
~ 10-2
10
fA
oS
]
~
...
~
!.
~
~
.,
'"
10- 3
I- SEnUNG TO I mV
1.2
I
....
0.8
0.6
0.1
OA
-
I-""
......
....
0.2
10-4
100 pF
1000 pF
O.OI.F
O.1.F
1000 pF
I.F
o
O.I~F
O.OIJJf
-50 -25 0
HOLD CAPACITOR
HOLD CAPACITOR
25
50 75 100 125 150
JUNCTION TEMPERATURE rCI
'See definition .
Leakage Current into Hold
Capacitor
100
~
80
VS' ,'5V
VOUT' 0
HOLD MODE
10
~
...
·Phase and Gain (Input to Output,
Small Signal)
70
=
:!!
V
~
""....
....
.,
/
.1
-5
60
-10
50
40
~
~
30
I
10-1
20
z
;;'
to
10
/
10-2
-50 -25
a
25
50
lk
75 100 125 150
10k
JUNCTION TEMPERATURE ('CI
.
120
"~
100
0:
z
fi"
60
0:
40
;;:
f..IJ.lIIlll
:<
oS
....
15
0:
POSITIVE
~UPPLV
NEGATIVE
SUPPLY
20
14
10k
lOOk
-
10
o
-50 -25
1M
-130
20
-120
15
-110
-"""'1
1 f""-.
a
rtI I
:!!
~
"
;:
,
-5
........ :--....
-10
-15
25
50
~
....
-0.4
.
25 50
"
0:
75 100 125 150
"
~ -0.8
~
-1
-15
JUNCTION TEMPERATURE rCI
-10
~
!!l
r-...
""
100
MOOE
60
I'
40
SAMPLE
a
75 100 12S 150
lrrruill
10
100
~
5;;
-80
FREQUENCV (Hzl
8·3
',00k
1M
1
1
1.8
1.5
::
fA
i)i
1.2
9
1
~
''"z"""
-70
10k lOOk
10k
Hold Step VI Input Voltage
2
g
lk
Ik
FREQUENCY (Hzl
-90
100
15
80
20
lSV
VIN -10 Vp·p
Vu oO
Ti' 25'C
10
10
-S
IJ
120
11". V- o
1
--
1-0.
~ -0.&
~
-50
a
-0.2
140
-60
-50 -25
::;
0
"~
Jl
iii -100
.......
l"-
~
,.<~
... .....
0.2
Faadthrough Rejection Ratio
(Hold Mode)
26
15
0:
al
~
JUNCTION TEMPERATURE rCI
Input Bia Current
10
5
~
Output Noise
L
SINKING
FREQUENCV (Hzl
1
...
~
""c
:;:
Tj'25'C
Rl"10k
SAMPLE MOOE
0.6
0.4
INPUT VOLTAGE (VI
SOURCING
12
2
a
lk
~
1 1
J
.,'"
"
0;::
100
~
160
16
80 i1+WIt'
~
Output Shon Cin:uit Current
20
18
T' -25'C
V~. V-'15V
VtiUT 0 OV-
140
:!!
1M
~
....
1
0.8
FREQUENCV (Hzl
Power Supply Rejection
160
lOOk
0
10M
Gain Error
~
0.8
0.5
r--:- ~ -...:Ti: ioo C
I-- Tj
0
25
c--. .......
.......
r--ITjo-55'C"
r- 1,-1'1
0.4
0.2
'""""" ...
r-
o
-15 -10
-5
INPUT VOLTAGE (VI
10
15
application hints
Hold Capacitor
'Hold step, acquisition time., and droop rate' are the
:major' trade-effs' in the ~election of a hold capacitor
'value_ Size and, cost may also become impor;tant for,
larger values.: Use of the curves included with this data,
sheet should be helpful in ,sele~ting a reasonable value
,of ,capacitance .• K;eep in mlnd'that for fast repetition'
,rates or tracking fast signals, the capacitor drive currents
may cause a si,gnificant temperature rise in the, !-F 198:
, A significant source of error in an accurate sample and
hold circuit is dielectric absorption in the hold capacitor.
A -mylar cap, 'for instance, may "sag back" up to 0.2%
after a quick change in voltage. A long "soak" time is
required before the circuit can be put back into the
hold mode with this type of capacitor. Dielectr.ics with, '
very low hysteresis "are polystyrene, polypropylene, and
Teflon; ,Other types such as mica and polycarbonate
, are not 'nearly as good. ee'ramic is unu,sable with> 1%
,hysteresis. The advantage of polypropylene ,over, poly., styrene is that it extends the maximum ambient tempera, tuni from 85° C to 100° C,' For more exact data, see t~e
curve labeled'dielectric absorpti~n error vs 'sam'ple time.,
,The 'hysteresis numbers' on the curve are final values,
taklln after full relaxation, The hysteresis error can be, '
,significantly reduced if the output of the Lf 198 is
digitized quickly after the 'hold mode is initiated. The
hysteresis relaxation time constant in polypropylene,
for instance, is 10-50 ms. If -A-to-D conversion can be
made 'within 1 ms, hysteresis error will be reduced by a
factor of ten.
DC and AC
,
,~,
Zer~,ing ,
differential for fast moving signals. In addition, although
the output may have settl~d, the hold capacitor has an
additional lag due to the 300n series resistor on the chip.
This mean's that at the moment the '~hold" command
arrives, the' hold capacitor voltage may be somewhat
different than the actual' analog input. The effect of '
, ,these delays is opposite to the effect created by delays
in the logic which switches the circuit from sample to
'hold. For example, consider an analog ,input of 20 VP-,P
ail0 kHz: Maximum dV/dt,is 0.6 VIps. With,no,analog
phase delay and 100 ns' iogic delay, oile could expect
up to (0.1I-1s)(0.6V/l-ls) = 60 mV error if the "hold"
signal arrived near maximum dV Idt of the input. A
positive-going input would give a ±60 mV error. Now
assume a 1 MHz (3 dB) bandwidth for the overall analog
loop. This generates a phase delay of 160 ns. If the hold
capacitor sees this exact delay, then error due to analog
delay will 'be (0.16I-1s)(0.6 V/l-ls) = -96 mV.'Total output error is +60 mV (digital) -96 mV (analog) for a
total of -36 mV. To add to the confusion, analog delay
is proportional to hold capacitQr value while digital
delay remains constant. A family of curves (dynamic
sampling: error) is included to help estimate e~rors.
A curve labeled' Aperture Time has been included for,
sampling conditions where, the, input is steady during
the ,Sampling period, but may experience a sudden
change nearly coincident with the "hold" command.
This curve is based on a 1 mV error fed into the output.
A second curve, Hold Settling Time indicat~s the time
required for the output to settle to 1 m V after the
"hold" command.
Digital Fe~through
'DC zeroing is accomplished by connecting the offset
,lmjust pin to the' wiper of a 1 kn potentiometer which
, ' hils one erid tied to V+ and the other end tied th rough a
:'resistor to grou'n'd, The resi,stor should be selected to
give ""0,6 mA through ,the lk potentiometer,
,"A,C zer~ing (hold step zeroing) can be obtained' by ,
adding an inverter with the adjustment pot tied input'
to ,output, A 10 pF capacitor from the wiper to the
hoid capacitor will give ±4 mV hold step adjustment
O,OII-1F hold capacitor and 5V logic 'supply.
with
For larger logic swings, a smaller capacitor « 10 pF)
, may be used.
a
Fast rise time logic signals can cause hold errors by
feeding externally into'the analog input at the same
time the amplifier is put into 'the hold mode. To ,minimize this problem, boar!Jlayounliould keep logic lines
as far as possible from the analog inp!!t. Grounded
guarding traces may also be used around the input
line, especially if it is driven from a high impedance
source. Reducing high amplituda Ipgic signals to 2.5V
will also help.
'
'
Guarding Technique
OFFSET
AOJU~T
Logic Rise Time
\
ONe,
\@
For proper"bp'eration,'logic signals into the LF198 must
have a minimum dV/dt of 0,2 V/l-ls, Slower signals will
cause excessive hold step. If a'R/C netwQrk is used in
front of the logic influt for'sign,al delay, calculate' the
slope of the wav,efor at'the threshold point to ensure
that it is at lea~t 0.2'V/l-ls.
~OGIC
,INm~
BOTTOM
VIEW
rn
Sampling Dynan:'l!cSignall
GUARO TOP AND
BOTTOM OF BOARD
Sample error due to m,oving ,input signals proba~ly
'causes more confusion, among sample-and-hpld u~ers'
·than any other parameter. The primary reason for'this
is that many users make the assumption that the sample
and hold amplifier is truly locked on to the input Signal
while in the sample mode. In actuality, there are finite
phase delays through the circuit creating an input-output
Use 101lin layout. Guard around
eh is tied to output.
8-4
r
logic input configurations
"TI
.....
TTL & CMOS
3V
(0
v+
S VL (Hi Statel S 7V
OJ
"r"TI
N
n
.J
HDLD
Rl'
(0
Z.8V
"r"TI
R2
LSAMPlE
5.6k
CMOS
7V
S VL (Hi Statel S 15V
v'
_ v'
20k
nSAMPLE
.J
2Dk
n
30k
.J .
LHDLD
Threshold
= 0.6
(V+) + 1.4V
HOlD
JOk
LSAMPLE
Threshold
= 0.6 (V+) - 1.4V
Op Amp Drive
D
J- L
'13~
- 13
:MPL_E-'\8"'_Z"'k.......
Threshold
~
HOLD
'13VD:LD
_lJ~J
4.7k
-
-=- B2k
LSAM-P-LE-""IIr-.... 4. 7k
+4V
Threshold
= -4V
typical applications (con't)
X1000 Sample & Hold
Sample and Difference Circuit
(Output Follows Input ill Hold Model
VOUT
OF~::~ I+-'V~M\iZ
"'""+-""-1
~
VOUT" Va'" ·.wIN (HOLD MODE)
O.OlI1F
ADJUST
Y,N
VOUT
-15V
~
1-1III1Ir-+-:---....I
~
.J
*For lower gains, the LM108 must be frequency compensated
100
Use
~
-
'
pF froni camp 2 to ground
AV
8-5
RESET
L. TRACK
W
(0
OJ
Threshold = 1.4V
*Select for 2.8V at pin 8
Threshold = 1 .4 V
OJ
typical applications (con't)
Integrater with Programmable
Rasat Level
Ramp Generator with Variable Rasat Level
V+
15Y
RI
-15Y
8.2k
01
LM113
1.2V
RESET
LEVEL
INPUT
RESET
LEVEL
INPUT
>=--+-+-oOUTPUT
RESET-n
RESET
5~-n
DV...J L..
RAMP
INTEGRATE...J
AV
·Select for ramp rate
R ;?10k
L..
DIFFERENTIAL
INTEGRATING
INPUT
1.2V
1
RI
1M
'"
o-.JV.>Iv-~I--=-t
AT
R3
1M
1%
1
VOUT (Hold Mode) = [ - - (RlI1Ch)
Output Holds at Average of
Sampled Input
J,t
°
Increased Slew Current
y+
INPUT
OUTPUT
27rf1N (Min)
Fast Acquisition, Low Droop Sample & Hold
Rasat Stabilized Amplifier (Gain of 1000)
Ik
III
1M
1%
15Y
15V
DirrpUT
>~_---~t-'OOUTPUT
-15Y
INPUT
5V-:-n
L..
--I I-
-j
OV...J
RESET PULSE
~2ms
1.2M
At
AVOS'
--"'O.l"VrC
AT
8-6
r-
~
LM3985
TIMER
VOS $: 'l0ILV (No trim)
ZIN'" 1 Mn
AVOS
- - '" 30ILV/sec
12m.
3.31
typical applications (con't)
Synchronous Correlatar for Recovering
Signals Below Noise level
2-Channel Switch
15V
15V
OUTPUT FREOUENCY
SET BY SWEEP RATE
"~~IV~--~-oO~
... A-V.A.
SI,GNAL
"\INPUT
"A" INPUT
"A" SELECT
5V-n
SYNCHRONOUS
ov-l L...
CLOCK INPUT
"B"SELECT
JLr
"B" INPUT
·8
7
I
2
8
7
A5
12k
Gain
LMI22H
TIMEA
LMI22H
TlMEA
ZIN
BW
AS
20k
-;; 10
4
C3
47DpF
R4
500
4.7k
6
5 10
A
B
1 ±O.O2%
10 10n
1 ±O.2%
~1
47 kn
MHz
~400
kHz
Crosstalk
@ 1 kHz
--BO dB
--BO dB
Offset
:SBmV
:S 75 mV
NC
*Select C1 to filter lowest frequency
component of input noise
TO SCOPE SWEEP
OUTPUT. SCALE R3
TO OBTAIN"" 0 TO 3V
"Select C2
@
~ 5 x lO- B/f IN
ATPIN6.
DC & AC Zeroing
Staircase Generator
15V
oJ
15V
24k
RESET
5V=rL
OV
RI
4.lk
OUTPUT
03
LMIIJ
1.2V
CLOCK
5V=rLJL
OV
R5
11k
C2
JOOpF
*"
':"
R4
8.2k
15V
CJ
R8
12k
O.Ol/JFT
Al
_
4.7k
-
....JVVII ............O 15V
R9
Jk
02
IN914
*Select for step height
50k~~ lVStep
8-7
RS'
50k
co
en
(W)
typical applications (con'tl
LL
..J
........
CO
en
C\I
LL
..J
........
CO
en
,...
Differential Hold
Capacitor Hysteresis Compensation
LL
..J
>::.....-.........0 OUTPUT
INPUT
"IVS + VCM) WHEN IN
SAMPLE MODE
SL
RI
Ch
200k
R2
200k
lOGIC
r
T
*Select for time constant C1
:= - -
lOOk
ill-
* Adjust for amplitude
connection diagram
Metal Can Package
Dual-In-Line Package
lOGIC
OffSET
ADJUST
2
lOGIC
REFERENCE
OFFSET
ADJUST
INPUT
CH
OUTPUT
TOP VIEW
TOP VIEW
Order Number LF198H, LF298H or LF398H
See NS Package HOSe
Order Number LF198J, LF298J or LF398J
See NS Package J08A
Order Number LF39SN
See NS Package NOSB
8-8
~National
Sample and Hold
N
W
........
LH0023/LH0023C,LH0043/LH0043C
Sample and Hold Circuits
r:t:
o
o
general description
The LH0023/LH0023C and LH0043/LH0043C
are complete sample and hold circuits including
input buffer amplifier, f;ET output amplifier,
analog signal sampling gate! TTL compatible logic
circuitry and level shifting. They are designed to
9perate from standard ±15V DC supplies, but
provision is made on the LH0023/LH0023C for
connection of a separate +5V logic supply in
minimum noise applications. The principal difference betwjlen the LH0023/LH0023C and the
LH0043/LH0043C is a 10: 1 trade-off in performance on sample accuracy vs sample acquisition
time. Devices are pin compatible except that TTL
logic is inverted between the two types.
hold applications. including data acquisition,
analog to digital conversion, synchronous demodulation, and automatic test setup. They offer
significant cost and size reduction over equivalent
module or discrete designs. Each device is available
in a hermetic TO-8 package and are completely
specified over both full military and instrument
temperature ranges.
The LH0023 and LH0043 are specified for opera·
tion· over the _55°C to +125°C military temperature rang~. The LH0023C ~nd LH0043C are
specified for operation ove~ the _25°C to +85°C
temperature range.
The LH0023/LH0023C and LH0043/LH0043C
are ideally suited for a wide variety of sample and
features
• Sample acquisition time-15 )J.s max for 20V .
4 )J.s typ for 5V
• Aperture time-20 nS typ
• Hold drift rate-'l mV /sec typ
• Sample accuracy-0_1% max
• Wide analog range-±10V min
• Logic input-TTLlDTL
• Offset adjustable to zero with ·single 10k pot
• Output short circu it proof
Sample accuracy-0.01% max
Hold drift rate-0.5 mV/sec typ
Sample acquisition time-1 00 )J.S max for 20V
Aperture time-150 ns typ
Wide analog range-±10V min
Logic input-TTLlDTL
Offset adjustable to zero with single 10k pot
Output short circuit proof
block and connection diagrams
LH0023/LH0023C
LH0043/LH0043C
UAlllt
'~PUI
Order Number LH0023H
LH0023CH, LH0043H
or LH0043CH
Se. NS Package H12B
OHsn
AII.IUn
, ,
u".. ~~.
'''~''':,"n
IHrlll
I
I
1.-_--:',,-0 c!J~:-T;gIR
-Til to pin 8 for op~ation without Vee supply.
r::t:
o
o
~
w
r::t:
........
o
o
()
LH0043/LH0043C
III'UT~
51
~
LH0023/LH0023C
lDGJ:~ ........ J
N
W
w
features
"Tiaforoperltion
with v+ "15Vonly
o
o
~ Semiconductor
•
•
•
•
•
•
•
•
r::t:
.... ,
.
UCIC~.
C::..
--0'"
.
IIIPU1~-
I
I
J
•
I'
.U
DUTPUT
Inll~An
UC:fAClTDR
---ov
.
"
--O~
-oGIO
--on.
"
--<>~
8-9
o(?
v
o
-0
::J:
.;;.J
.......
(?
v
o
o
::J:
..J
U
M
absolute maximum ratings
Supply Voltage (V+ and V-)
±20V
+7.0V
Logic Supply Voltage (Vee) LH0023, LH0023C
Logic Input Voltage (V 6)
+5.5V
,.
Analog Input Voltage (V 5)
±15V
Power Dissipation
See graph
Output Short Circuit Duration
Continuous
Operating Temperature Range LH0023, LH0043
-55°C to +125°C
LH0023C, LH0043C _25°C to +85°C
_65°C to +150°C
Storage Temperature Range
300°C
Lead Soldering (10 sec)
\
,
electrical characte.ristics
LH0023/LH0023C (Note 1)
N
o
o
::J:
LIMITS
PARAMETER
CONDITIONS
MIN
. LHOO23
TYP
MAX
MIN
LHOO23C
TYP
UNITS
MAX
..J
Sample (Logic "1 ")
Input Voltage
Vcc = 4.5V
N
Sample (logic "1 ")
Input Current
Vs = 2.4V, Vec = 5.5V
5.0
5.0
Hold (Logic "0")
Input Voltage
V cc =4.5V
0.8
. 0.8
Hold (Logic "0")
Input Current
Vs = O.4V, V cC.= 5.5V
0.5
0.5
.........
(?
o
o
::J:
..J
2.0
Analog Input.
Voltage Range
Supply Current - 110
Supply Current - 112
±10
Vs =OV, Vs =2V,
V" = OV
Vs = OV, Va= OAV,
V" = OV
2.0
±11
±10
V
±11
JlA
V
mA
V
4.5
6
4.5
6
mA
4.5
6
4.5
6
mA
Supply Current - 18
V8 =5.0V, Vs =0
1.0
1.6
1.0
1.6
mAo
Sample Accuracy
V OUT = ±10V (Full Scal~)
0.002
0.01
0.002
0.02
DC Input Resistance
Sample Mode
Hold Mode
% ..
kl1
kl1
Input Current -- Is
Sample Mode
1.5
JlA
500
20
'0.2
Input Capacitance
Vs = ±10V; V" = ±10V,
TA = 25°C
Vs = ±10V; V l l =±10V
Drift Rate
V OUT '= ±5V, Cs = 0.01 JlF,
TA = 25°C
Drift Rate
VJUT = ±10V,'
Cs = 0.01 JlF, T A = 25°C
V OUT = ±10V,
Cs
= 0.01
100
1.0
0.6
10
3.0
200
200
1.0
1.0
2
20
20
0.1
pA
nA
mV/s
0.5
50
0.2
150
50
Output Amplifier
Slew Rate
1.5
Output Offset Voltage
(without null)
Rs:<::: 10k, V5 =OV, V 6 =OV
Analog Voltage
Output Range
RL
RL
;;:::
pF
500
mV/s
mV/ms
/IF
AV OUT = 20V,
Cs = 0.01 /IF
;;:::
1000
25
0.3
0.5
Aperture Time
Sample Acquisition
Time
300
20
3.0
Leakage Current pin 1
Drift Rate
1000
25
lk, TA = 25°C
2k
3.0
50
1.5
±11
±12
100
3.0
±20
±10
±10
ns
150
100
V//ls
±20
±10
±10
±ll
±12
/lS
mV
V
V
Note 1: Unless otherwise noted, these specifications apply for V+ == +15V. Vee = +5V, V- =- -H?V, pin 9 grounded. a
, O.01pF capacitor connected between pin 1 and ground over the temperature range -5SoC to +125°C for the LH0023, and
-25°C to +85°C for the LH0023C. All typical values are for T A = 25°C.
I
8-10
electrical characteristics
r
::z::
o
o
LH0043/LH0043C: (Note 2)
PARAMETER
CONDITIONS
Hold (Logic "1",
I nput Voltage
Hold (Logic "1",
I nput Current
LHOO43
MIN
TYP
V6=D.4V
±10
Sample Accuracy
V5 =OV, V6 =2V, V" =OV
V5 = OV, V6 = O.4V,
V" =OV
V OUT = ±10V (Full Scale'
DC I nput Resistance
T e = 25°C
0.02'
UNITS
MAX
Input Current - Is
1.0
1.5
V
0.8
V
S'>
1.5
1.5
rnA
r
:::I:
±lD
±11
20
14
22
18
0.1
0.02
1010
5.0
V
22
18
0.3
10.0
nA
50
pA
1.5
pF
10
25
2
5
nA
10
25
20
50
mV/s
Drift Rate
V OUT = ±10V, Cs = 0.001 IlF
10
25
2
5
mV/ms
Drift Rate
V OUT = ±10V, Cs = 0.01 IlF,
Te= 25"C
1
2
5
mV/s
Drift Rate
V OUT = ±10V, Cs = 0.01 IlF
Sample Acquisition
Time
aVOU~ = 20V, Cs = 0.001 IlF
aV OUT = 20V, Cs = 0.01 IlF
!:NOUT = 5V, Cs = 0.001 IlF
Output Amplifier
Slew Rate
V OUT = 5V, Cs = 0.001 IlF
Output Offset Voltage
(without null)
Rs :::; 10k, V5 =OV, V6=OV
Analog Voltage
Output Range
RL~lk, T A = 25°C
RL::e: 2k
20
%
n
10'2
2.0
rnA
rnA
25
1
2.5
2.5
0.2
60
20
60
ns
10
30
15
50
10
30
15
50
IlS
Il S
Ils
4
3.0
1.5
3.0
±40
±10
±10
0.5 mV/ms
20
4
1.5
±11
±12
V/Ils
±40
±10
±10'
±11
±12
mV
V
V
Note 2: Unless other";ise noted, these specifications apply for V+ = +15V, V- = -15V, pin 9 grounded, a 5000 pF capacitor
connected between pin 1 and ground over the temperature range -5SoC to +12SoC for the LH0043. and -25°C to +BSoC
for the LH0043C. All typical values are for T C = 25° C.
8-11
N
W
0.8
10
Aperture Time
o
IlA
V 5 =.±10V;V" =±10.
Te = 25°C
V 5 =±10V;V" =±10V
V OUT = ±10V, Cs = 0.001 IlF,
Te = 25°C
Drift Rate
r
o
:::I:
5.0
10'2
Input Capacitance
Leakage Currentpin 1
TYP
.......
5.0
±11
20
14
10'0
MIN
2.0
V6 = 2.4V
Analog Input
Voltage Range
Supply Current
LH0043C
MAX
2.0
Sample (Logic "0'"
I nput Voltage
Sample (Logic "0'"
Input Current
N
W
LIMITS
,
o
o
~
~
r
:::I:
o
o
~
w
(")
o
('I)
'lit
typical performance characteristics
o
o
Power Dissipation
::t:
..J
........
Z.O
1.75 ' - -
'lit
..
1.5
o
~
1.0
0:
..J
!!£
f
('I)
o
::t:
.. $:
o
HEATSINK
".
z
;: 1.25
::
~STILLAIRWITHCL1P'ON
..J
........
('I)
C\I
o
o
::t:
..J
"
0.5
0.25
..
~ +10V
-
>
:l:
15
~
'"
100
OV
0:
.
..~
w
>
~
!!!
...~
...,...
~
~
I
I
125
-
150
-5
+5
>
-5
eo.,
II
0
-10
C
:...
w
-6
.....
~
1'\
Cs =0.01 F
TA "25°C
VSAMPlE '" S.OV
,
I.J'
"
t;
I~
+
I"- I-'.OUTPUT
NI
-- - _1.:'S.
5 10 IS 20 25 30 35 40 45 50
"'.1
vs Temperature
100
Vs "±15V
T. =25°C
~
...
10
ffi
0:
..~
'"
-VOUT=-I~
W
~~OUT':'O_
~
r--VOUT" +10 -
../L L
//
z
;;:
-16
-12V-I0-6-6-4 -2 0 2 4 8 8 1012V
TIME ""I
INPUT-
Pin 1 Leakage Current
-14
20 40 &0 80 100 120 140 160 200
II
'i"'!.
TIME
-10
I.J'
I\.
-- - -- -
"'.1
-6
~
I
-IOV
12'345618910
-2
+10
'I.
I
I
ov
~
Pin 1 Leakage Current
vs Output Voltage
10
5
-10
is +10V
>
:l:
.... OUTPUT
INPUT~
TIME
Time':'LH0023
w
w
-10
Sample Acquisition
~
..
~
,I\.
TEMPERATURE ('CI
8
::t:
r-~S:±I~V
r-CL -om.F
v L = O.OV
r- T. = 25°C
~
"- ~
C\I
Vs" ±15V
VL =5.0V .
TA " 2S"C
Cs· O.OOI.F
~ I\.
50
Time-LH0043
'aw
0.7&
25
Sample Acquisition
Time-LH0043
-
'\.
STILL AIR
('I)
Sample Acquisition
.01
o
25
50
1&
100
125
TEMPERATURE (OCI
OUTPUT VOLTAGE IVI
Drift vs Capacitance
Output Currant Limiting
15.0
.
iii...
.,.
!
z
~
'--
...... i:-....
'\
10.0
TA = 125°C
(LH0043)
Drift Rate vs Capacitance
10.000
1000
~
...>
11 100
~
0:
i;:
~
o
10
15
20
25
I- Tc ·= +125°1:"
~",
10
TA =25°C
1.000
.5 100
&.0
o
J'\l ~
I 1"-1
Vs = .15V
.01
30
OUTPUT CURRENT ("'AI
.1
.
r------------,I
SAMPlEJ
HOLD
LOGIC
INPUT
I
I
I
I'
I
I
I
I
IL ___________
GUAADSHIHII
'CIGARD ...JI
Note 1: C1 ilpolystyrene.
Note 2: C2. C3, C4 are cenmh: disc.
Note 3: Jumper 7-8 and C4 not requited for lH0043.
Note4: R1optionatifzerntrimisreqllirad.
How to Build a Sample and Hold Module
8·12
1"1"-
Tc =25°C
N
V"I-15l1t
~
1"-
1'\
.001
.01
.•1
CAPACITANCE litFI
typical applications
ANALOG
INPUJ
j[".,
I"-
1".1
.0001
Cs - CAPACITANCE litFI
I
I
[".,
[".,
10
10
Vs = t15
VOUT = ±10
10
ro
:::J:
typical applications (con't)
oN
DIGITA~{
W
........
;EVICE
} PINS
INPUT
CODE
r-
rTL.-_ _....-
::E:
o
o
Forcing Function Setup for Automatic Test Gear
N
W
~n
ANALOGSWITCH
MULTIPLEXERS
AHDOIS,
AMllll5,
AMl009,
ANALOG
INPUTS [
r-
DIGITAL
} OUTPUTS
::E:'
o
ORAH01ZDSERIES
o
SlHLOGIC
~
CHANNEL SELECT
w
........
r:J:
o
*Seillp amp selection guide for details. Most popular types indudillHOD52, LH175. LM1DB. LM112 and LM116:
Data Acquisition System
o
ANALOG
puLSE-l>-----;;::===~~f,:;;~I-----=.,-1tINPUT
DIGITAL
OUTPUTS
ANALOG
OUTflUTS
I
I
L
AM3705.
__
__
A~O
1
.J
Single Pulse Sampler
~ r---~-------,
COM~~~I!~o----...5~:--f1,......-....,. .n....._.r.-~
1J11UlI"
1
1
1
1
REFCE~RE~i~o-....--_+~·:r---I
L_~
1
SIGNAL.;' OUTPUT
1
__ _
L~_ _
1
....J
1
.T e•
5r-~--------l
TTL
INVERTER
1
I
I
I
1
I.
SIGNAL #Z OUTPUT
_J
L'!!!!!'_ _
.J
1
T"
Two Channel Double Sideband Demodulator
8·13
~
w
n
(J
(W)
~
schematic diagrams
o
I-H0043/LH0043C
SAMPLE
o
"'~","
--~----y----+t------r-r--rT""
J:
...J
.......
(W)
~
o
o
J:,
...J
L-----lI-_+-oOUTPUT
"
~
(J
(W)
N
8J:
...J
c;;
N
o
o
LH0023/LHOO23C
J:
...J
-------E----;.,
Gnu., 1,.'
Lt....,\I\o-6.t------t-.....""1:-"
8·14
OUTPUT
r-
applications information
will be stored on the capacitor, in much less time as
dictated by the slew rate and current capacity of
the input amplifier, but it will not be available at
the output). For larger values of storage capacitance, the limitation is the current sinking capability of the input amplifier. typically 10 mA. With
Cs = 0.01 MF, the slew rate can be estimated by
dV
10 10- 3
Cit = 0.01 .10 6 = 1 VIMs or a slewing time for a
1.0 Drift Errar Minimizatian
In arder to. minimize drift error, care in selectian
af Cs and layaut af the printed circuit baard is
required. The capacitar shauld be af high quality
Teflan, polycarbonate, or polystyrene canstruction. Baard cleanliness and layout are critical
particularly at elevated temperatures. See AN·63
for detailed recommendations. A guard conductar
connected to the output surrounding the storage
node (pin 1) will be helpful in meeting severe
enviranmental conditions which would otherwise
cause leakage across the printed circuit board.
0
w
r'"
::I:
o
o
I\)
3.0 Offset Null
(")
w
~
The size of the capacitor is dictated by the required drift rate and acquisition time. The drift is
determined by the leakage current at pin 1 and
IL
.
dV
~ay be calculated by Cit = Cs ' where IL IS the
4.0 Switching Spike Minimization-LH0043
A capacitive divider is formed by the' storage
capacitor and the capacitance of the internal F ET
switch which causes a small error current to be
injected into the storage capacitor at'the termination of the sample interval. This can be considered
a negative DC offset and nulled out as described in
(3.0), or the transient may be nulled by coupling
an equal but opposite signal to. the storage
capacitor. This may be accamplished by.connecting a capacitor af about 30 pF (or a trimmer)
between the logic input (pin 6) and the storage
capacitor (pin 1). Note that this capacitor must be
chosen as carefully as the storage capaCitor itself
with respect to leakage. The LH0023 has switch
spike minimization circuitry built into. the device.
total leakage current at pin 10f the device, and
Cs is the value af the storage capacitor.
2.1 Capacitor Selectian - LH0023
At room temperature leakage current far the
LH0023 is approximately 100 pA. A drift rate of
10 mV Isec would require a 0.01 MF capacitar.
Far values af Cs up to 0.01 MF the acquisition
time is limited by the slew rate af the input buffer
amplifier, A 1, typically. 0.5 VIMs. Beyond, this
point, current availability to charge Cs also. enters
the picture. The acquisition time is given by:
5.0 Eliminatian af the 5V Lagic Supply-LH0023
The 5V logic supply may be eliminated by
shorting pin 7 to. pin 8 which co.nnects a 10k
dropping resistor between the +15\1 and Vc'
Decoupling pin 8 to ground through 0.1 MF disc'
capacitor is reco.mmended in order to minimize
transients in the output.
where: R = the internal resistance in series with Cs
Lle o = change in voltage sampled
An average value for R is approximately
600 ohms. The expression for tA reduces to:
Cs
o
o
I\)
5 va It signal change of 5Ms.
Provision is made to null both the LH0023 and
LH0043 by use of a 10k pot between pins 3 and 4.
Offset null should be accomplished in the sample
mode at one half the input voltage range for
minimum average error.
2.0 Capacitar Selectian
For a -10V to +10V change and
acquisition time is typically 50 MS.
::I:
6.0 Heat Sinking
The LH0023 and LH0043G may be operated
without damage througho.ut the military temperature range of -55 to +125°C (-25 to. +85°C for
the LH0023CG and LH0043CG) with no explicit
heat sink, hawever power dissipation will cause the
internal temperature to rise abo.ve ambient. A
simple clip-o.n heat sink such as Wakefield"
#215-1.9 or equivalent will reduce the internal
temperature abo.ut 20°C thereby cutting the leak-age current and drift rate by one faurth at max.
ambient. There is no internal electrical connection
to the case, so it may be mounted directly to a
grounded heat sink.
.05 MF,
2.2 Capacitor Selection-LH0043
At 25°C case temperature, the leakage current for
the LH0043G is approximately 10 pA, so a drift
rate of 5 mV/s would require a capacitor of
Cs = 10 • 10- 12 /5 • 10- 3 = 2000 pF or larger.
For values of Cs below about 5000 pF, the
acquisition time of the LH0043G will be limited
by the slew rate of the output amplifier (the
signal will be acquired, in the sense that the voltage
7.0 Theary of Operatian-LH0023
The LH0023/LH0023C is comprised of input
buffer amplifier, AI, analog switches, 51 and S2, a
8-15
r-
::I:
o
o
~
w
r'"
:J:
o
o
~
w
(")
o('I)
~
o
o
::J:
...J
.......
('I)
~
8
::J:
...J.
U
('I)
N
o
o
::J:
...J
.......
('I)
N
o
o
::J:
applications information (con't)
closed and allows A1 to make the storage capacitor voltage equal to the analog input voltage. In
the "hold" mode (Va = 2.0V), Sl is open~d
isolating the storage capacitor from the input and
leaving it charged to a voltage equal to the last
,!nalog input voltage before entering the hold
mode. The storage capacitor voltage is brought to
the output by low leakage amplifier A2.
TTL to MOS level translator, and output buffer
amplifier, A2. In the "sample" mode, the logic
input is raised to logic "1" (Va ~ 2.0V) which
closes Sl and opens S2. Storage capacitor, CS, is
charged to the input voltage through Sl and the
output slews to the input voltage. In the "hold"
mode, the logic input is lowered to logic "0"
(Va ~ 0.8V) opening Sl and closing S2. Cs
retains the sample voltage which is applied to the
output via A2. Since Sl is open, the input signal
is ov.erridden, and leakage across the MOS switch is
therefore minimized. With 81 open, drift is prima·
rily determined by input bias current of A2,
typically 100 pA at 25°C.
8:0 Definitions
The voltage at pin 5, e.g., the analog
input voltage. ,
.
Va: The voltage at pin 6, e.g., the logic
control input signal.
V, , : The voltage at pin 11,. e.g., the qutput
. signal.
T A: The temperature of the ambient air.
T c: The temperature of the device case at
the center ot the bottom of the header.
V5:
7.1 Theory of Operation-LH0043
The LH0043/LH0043C is comprised of input
buffer amplifier A 1, FET switch Sl operated by a
TTL compatible level translator, and output buffer
amplifier A2. To enter the "sample" mode, the
logic input is taken to the TTL logic "0" state
(Va = 0.8V) which commands the switch Sl
Acquisition Time:
The time required for the output (pin 11)' to settle
within the rated accuracy after· a specified input
change is applied to the input (pin 5) with the
logic input (pin 6) in the low state .
...J
Aperture Time:
The time indeterminacy when switching from
sample mode to hold including the delay from the
time the mode control signal (pin 6) passes
through its threshold (1.4 volts) to the' time the
circuit actually enters the hold mode.
ANALOG
IIPPT
!-'-:'........LLL.LU.......u..&.J..L.I.L..._ _-Ll_ _---<1 '
Output Offset Voltage:
The voltage at the output terminal (pin 11) with
the' analog input (pin 5) at ground and logic input
(pin 6) in the "sample" mode. This will always be
adjustable to zero using a 10k pot between pins 3
and 4 with the wiper arm returned to V-.
ANALOG
OUTPUT
8-16
~National
Sample and Hold
~ Semiconductor
ro
:l:
o(J1
CN
......
r:l:
o
o
LH0053/LH0053C High Speed
Sample and Hold Amplifier
(J1
CN
o
general description
features
The LH0053/LH0053C is a high speed sample
and hold circuit capable of acquiring a 20V step
signal in under 5.0J.ls.
• Sample acquisition time 10,us max for 20V
signal
•
The device is ideally suited for a variety of high
speed data acquisition applications including analog
buffer memories for A to D conversion and
synchronous demodulation.
FET switch for preset or reset function
• Sample accuracy null
• Offset adjust to OV
•
An auxiliary switch within the device extends its
usefulness in applications such as preset integrators.
DTLlTTL compatible FET gate
• Single storage capacitor
schematic and connection diagrams
Metal Can Package
STORAGE
CAPACITOR
FEEDBACK,
PRESET
v-
GATE I
PRESET
GATEZ
GND
TOPVIEW
Order Number LHOD53H Dr LHDD53CH
S.. NS Package H12B
ac test circuit
!O.
sco!~ot--+-----.......
r--------------------------t
c,
47.
r- -
-
J
10k
t15V~
-15V~
Ll~&3
____ _
•
Acquisition Time Test Circuit
8·17
-----,
U
M
It)
o
o
J:
..J
........
M
It)
o
o
J:
..J
absolute maximum ratings
Supply Voltage (V+ and V-I
Gate Input Voltage (V 6 and V 7 )
Analog Input Voltage (V 4)
Input Current (Is and 15)
Power Dissipation
Output Short Circuit Duration
Operating Temperature Range
LH0053
LH0053C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds 1
electrical characte'ristics
±18V
±20V
±15V
±10 mA
1.5W
Continuous
-55°C to +125°C
-25°C to +85°C
-65°C to +150°C
300°C
(Note 11
LIMITS
CONDITIONS
PARAMETER
LHOO53
MIN
Sample (Gate "0")
Input Voltage
LHOO53C
TYP
MAX
I
,
Sample (Gate "0"')
V6 =O.5V,T A = 25°C
Input Current
V6
==
0.5
Hold (Gate "1")
MIN
TYP
UNITS
MAX
0,5
0,5
V
-5,0
-100
-5.0
-100
MA
MA
4.5
4~
V
Input Voltage
\Hold (Gate "1")
Input Current
V~ '" 4.5V, TAO: 25°C
Vo
~
1.0
1.0
4.5V
±lO
Analog Input
Voltage Range
Supply Current
V4
'"
1.0
1.0
±lO
±ll
±ll
nA
MA
V
13
18
13
18
mA
120
250
150
500
nA
9.0
10
11
9,0
10
11
kll
±lO
112
:tl0
±12
OV
V6 =O.5V
Input Bias Current
V4 =DV,T A =2SoC
(I,)
Input Resistance
Analog Output
RL '" 2.0k
V
Voltage Range
Output Offset
V 4.= OV, V6
Voltage
V4 =OV, V6 = O.SV
Sample Accuracy
(Note 2)
V4 =: ±lOV, V6
O.SV, T A
=
==
'"
O.SV, TA
2SoC
==
25°C
5.0
7,0
10
5.0
10
15
mV
mV
0.1
0,2
0,1
0,3
%
Aperture Time
I:::..V 6 == 4.5V, TA :: 25°C
10
25
10
25
ns
Sample Acquisition
Time
V4 :±lOV, TA '" 2SOC,
CF ~ 1000pF, V6~OV
5.0
10
8.0
15
MS
Acqul~ition
V4 =±10V, TA = 25°C,
CF~ 100pF. V6~OV
4,0
~V1N =±10V, TA = 25°C,
CF ~ 1000 pF
20
Large Signal
Bandwidth
V 4 = ±10V, TA
C F ~ 1000 pF
= 25°C,
200
Leakage Current
V 4 =±10V, TA
V 4 =±10V
= 25°C,
6,0
30
30
10
50
3.0
V 4 =±10V, TA
=25°C,
6.0
30
10
50
Sample
Time
Output Slew Rate
(Pin 5)
Drift Rate
CF
~
Drift Rate
V,
~±lOV.CF ~
Q2 Switch ON
V7 ='0.5V, Is
-
4,0
MS
20
V/l1s
200
kHz
pA
nA
mV/s
1000 pF
1000pF
3,0
30
= 1.0 mA, T A = 25°C
100
300
100
300
Vis
11
Resistance
Note 1: Unless otherwise noted, these specifications apply for \IS :: ~ 15V, pin 9 grounded, a 1000 pF capacitor between pin
5 and pin 11, pin 3 shorted to pin 11, over the temperature range -55°C to +125°C for the LH0053 and -25°C to +85°C for
'
the LH0053C. All typical values are for TA = 2SoC,
Note 2: Sample accuracy may be nulled by inserting a potentiometer in the feedback loop. This compensates for source
impedance and feedback resistor tolerances.
8·18
~
o
O.
c.n
typical performance characteristics
Power Dissipation
Z.O
~
1.S
S
iii
is
a:
STILl AIR
I _
CLlp·ON HEAT SINK
~~
"' "'"
~
~ 0.5
o
~
.:'\.
~
........ i'-..
13
....... r-....
~
~
~
1~
100
0
75
100 lZ5
5.0
10'
15
ZO
OUTPUT CURRENT (mAl
~
~CF-l00Pf/
~E
r-- r-
/
~ 100
./
~
r- r--
CF jl000'r=
../
10
o
o
-55
-15
25
65
105
145
25
TEMPERATURE rCI
+10
II
::S
ZO 1 - - C; =1'00
10
>
!; 20
~ 30
co
I
I
,~
10
~F
I
I
I
I I I
!~'I'ooo'PF
~;: C~ =100~F
I
I
I
10
20
Z5
I
40
10
B.o
TIME ""I
12
16
'1
I
-
;:: 4.0
"
I
I
-50 -25
20
,
I
o· 25
+15V~
"I
c,'
·'5V
I
4
..-.!J
I
OUTPUT
.
.
-15V~IIO~ _ _ _ _ _
SIH LDlilC
0--------------'•
"'Polystyreneconsttuctlon.
Increasing Output Drive ea';"bility
, 8-19
./
I
I
./
,L
I
50
75
TEMPERATURE (OC)
TIME"'''
-----------,
INPUT
I
~15.ov t-- t--
Z.o
typical applications
ANALOG
125
.vi
t...-"
f"""""1 1-~
:;
-
-10
4.0
100
V,N "±1oy
] 6.0
I I I
I I I
50
I
Vs = ±15V
CF ".loopF
V.= ov
B.o
TA =Z5'C _
V.=oV
I
75
Acquisition Time vs
Temperature
w
+10
50
TEMPERATURE rCI
1/
-10
I I I
3D
L-~~~~~~~~~~
o
lZ5
..,I
TA' 25'C
Vo- ov
I
100
F'
:'S ;::C
_looopF r~
I I I
'INPUT J20 JST~P
I
I
. 75
Output Slew Rate
40
30
50
TEMPERATURE rCI
Sample Acquisition Time
~
Z5
Leakage Current at Pin 5
OV
-ISV
o
o
c.n
w
o
Vs:: .t15V
1000
i'.
50
Drift
r-J,. ~15~
f-v 3 -
Z5
l-
e-- Ti -I Z5",C
I I
I I I
TEMPERATURE rCI
Input Bias Current
>"
TA=25°C
~ 8.0
4.0
-50 -Z5
1~
::J:
12
1Ji
....
........
12
TEMPERATURE I'CI
Z50
~
11
o
r-
~
::;
"-
W
.......
I-J, ."15~
16
1'4 i"
STlLLAI~'
1.0
ZO
I-v;-±ilv
I
~ITH
"'
~
Output Current Limiting
Supply CUrrent vs Temperature
I
100 125
typical applications (con't)
c,
-.....!--~"-l
I
I
LO~~~o---------,,-I
:~~~T:lLOOG~~C.:~:'o-
_ _ _ _ _ _ _ _ _ _ _---'
Sample and Hold with Reset
.....
v " o - - - - - - -_ _ _ _ _-'
Preset Integrator
applic~tions
information,
SOURCE IMPEDANCE COMPENSATION
The drift is' dictated by leakag'e current at pin 5
and is given by:
The gain accuracy (linearity') of the LH0053!
LH0053C is set by two internal precision resistors.
Circuit applications in which the source impedance
is non-zero will result in a closed loop gain error,
e.g. if Rs' = lOn, a gain error of 0.1% results.
. Figure 1 and 2'show methods for accommodating
non-zero source impedance.
dt
CF
Where, IL is the leakage current at pin 5 and CF
is the value of the capacitance. Th.e room temperature leakage of the LH0053 is typical 6.0 pA, and
a 1000 pF capacitor will yield a drift rate of
6.0 mV per second.
DRIFT ERROR MINIMIZATION
/
IL
dv
For values of CF below 1,000 pF a~quisition fpr
the LH0053 is primarily gover'ned by the' slew
rate of th~, input amplifier (20V!IlS) and the
setting time of output amplifier (~ 1.0lls). For
values above CF = 1000 pF, acquisition time is
given by:
I n order to minimize drift error, care in selection
CF and layout of the" printed circuit board is
required. The capacitor should be of high 'quality
teflon, polycarbonate or polystyrene construction.
Board layout and clean lines are critical particularly
at elevated temperature.
CF AV
t. = - , - - , +.'.tS2
loss
Where:
CF '=, The value of the capacitor
A ground guard (shield) surrounding pin 5 will
minimize leakage currents to and from the summing
junction, arising from extraneous signals. See,
AN-63 for detailed recommendations.
AV = The magnitude of the input step;
e. g. 20V
CAPACITOR SELECTION-
loss = The ON current of switch Q1
~ 5.0 mA
The size of the capacitor is determined by the
required drift rate usually at the expense ,of
acquisition time.
ts2
= The setting time of output amplifier
~
8-20
1.01ls
r
X
applications information (con't)
o
o
en
CtJ
.......
c,
r~'
I
rX
o
o
en
CtJ.
HZ
(')
FIGURE 1. Non·Zero Source ImP,l!dance Compensation
c,
FIGURE 2. Non-Zero Source Impedance Buffering
GATE INPUT CONSIDERATIONS
Unused Switch, 02
5.0V TTL Applications
In applications when switch 02 is not used the
logic input (pin 7) should be' returned tc;> +5~OV
(or +15V for HTL applications) through a 10k[/.
resistor: Analog Input, preset (pin 8) should be
grou·ndea.
.
The LH0053 Gate inputs Gate 1 (pin 6) and Gate
2 (pin 7) will interface directly with 5.0V TTL.
However, TTL gates typically pull up to 2.5V in
the logic '"1''' state. It is therefore advisable to
. use a 10k ·pull·up resistor between the 5.0V, Vee,
and the output of the gate as shown in Figure 3.
To .obtain the highest speed and fastest acquisi·
tion time, the gate' drive shown in Figure 6 is
recommended.
10k
Vee 50VT015V
IlIk
GATE!illm
lHD053
LHIID5]
BINPUl
FIGURE 3. TTL Logic Compatibility
CMOS Applications
FIGURE 4. CMOS Logic Compatibility
The LH0053 gate inputs may be interfaced directly
with 74C, CMOS operating off of Vee's from
5.0V to 15V. However transient currents of
several milliamps can flow on the rising and
f~lIing edges of the input signal. It is, therefore,
advisable to parallel the outputs of two 54C174C
gates as shown in Figure 4.
HEAT SINKING
The LH0053 may be operated over the military
temperature range, -55°C to +125°C, without
incurring damage to the device. However,. a clip
on heat sink such as the Wakefield 215 Series or
Thermolloy 2240 will reduce the internal tempera·
ture rise by about 20°C. The result is a two·fold
improvement in drift rate at temperature.
It should be noted that leakage at pin 5 in the
hold mode will be increased by a factor of 2 to 3
when operating into 15V logic levels.
8·21
o('I)
Il)
applications information (con',t)
X
Since the case of the device is electrically isolated
from the circuit, the Ui0053 may be mounted
directly to a grounded heat sink .
o
o
..I
......
('I)
capacitors in order to prevent oscillation. Should
this procedure prove inadequate, the disc capacitors
should be paralled with 4.71lF solid tantalum
'electrolytic capacitors.
POWER SUPPLY DECOUPLING
DC OFFSET ADJUST
, Output offset error may be adjusted to zero using
the circuit shown in Figure 5. Offset null should
be accomplished in the sample mode (V6 ::; 0.5V)
and analog input (pin 4) equal to zero volts.
Il)
8
x
..I
Amplifiers.A1 and A2 within the LH0053 are very
wide band devices and are sensitive to power supply'
inductance. It is advisable to by-p.ase V+ (pin 12)
and V- (pin 10) to ground with O:WF disc
."v~'
...
,...
,
-
i'._~
'-'-:'
"
-l
'
I
I
I
hn
I
I
>-+'....-oOlllPllt
,~n"..
".
L"f--'-":"
I~V
G
•
':"
FIGURE 5. Offset Null Circuit
FIGURE 6. High Speed Drive Circuit
definition of terms
Voltage, V4: The voltage at 'pin 4, i.e., the analog
input voltage.
(pin 4) with logic input, Gate 1, (pin 6) in the
logic "0" state.
Voltage, V6: The voltage at pin 6, i.e., the logic
control signal. A logic "'" input. V6 ::; 4.5V,
places the LH0053 in the HOLD mode; a logic
"0'" input (V 6 ::; 0.5V) places the device in
sample mode.
Aperture Time: The time, indeterminacy when
switching from the "sample i ' mode to the HOLD
mode measured from time the logic input passes
through it's threshold (2.0V) to the time the device
actually 'enters tlie HOLD mode. .
'
Acquisition Time: The time required for the output
(pin 11) to settle within the rated accuracy after a
specified input chang~ is applied to Analog Input 1
Sample Accuracy: Di,fference between input voltage and output voltage while in the sample mode.
expressed as a percent of input voltage.
8-22
Section 9
Amplifiers
.
~ Semiconductor
~National
Amplifiers
lF152/lF252/lF352
FET Input Instrumentation Amplifier
r-
3!
CJ1
N
"r"T1
N
BI·FET Technology,
CJ1
N
"-
general description
The LF152 series is the first monolithic JFET input
instrumentation amplifier. The well·matched high voltage
JFET input devices provide very high input impedance
and extremely low bias currents, making the LF 152
ideal in applications where high source impedances
are encountered.
accurate because it has a very low initial gain error and
non-linearity. The bandwidth and slew rate are externally
controlled and the sense input and device output are
pinned out separately for added versatility.
The LF152 very accurately amplifies a differential
input.signal and rejects common·mode signal and noise.
It is not an op amp, but operates with an internal
closed loop gain connection which allows good linearity
with no external feedback. The LF 152 eliminates the
need for extremely precise resistor matching to obtain
high common-mode rejection (CMR) and provides high
input impedance as compared to the use of conventional
op amps connected as a difference amplifier.
• JFET inputs
• High input impedance
• Low bias currents
3 pA
II Low noise currents
0.Q1 pA rms
• Low gain nonlinearity
0.02%
.. High common-mode rejection ratio
110dBmin
(G = 100)
II Single resistor gain adjust
II External
compensation for extended gain and
frequency ranges
II Both input and output offset adjust capability to
~lIow a change of gain wi.~hout rezilroing
II Low supply current
1 mA
features
The LF 152 utilizes internal differential current feedback
eliminating the need for precision external feedback
components. The amplifier gain can be easily adjusted
from 1 to 1000 by changing the value of a single resistor. The transfer function for the LF 152 is highly
connection diagram
Dual·ln-line Package
OUTPUT
OFFSET
nUll
-VIN
ne
SENSf,
RS
COMP
VH
+Vcc
"
Order Number LF152D, LF252D
or LF352D
See NS Package D16A
Voos
OUTPIJT
BIAS
OffSET
+VIN
RS
RO
COMP
1,'0
NULL
simplified schematic
typical circuit
'v
vo
FIGURE 1
FIGURE 2
9-1
rn
w
CJ1
N
C\I
It)
C")
absolute maximum ratings
LL
..J
.......
C\I
It)
C\I
LL
..J
"'C\I
It)
u:..J
Supply Voltage
Differential Input Voltage
Input Voltage Range
Output Short Circuit Duration
Power Dissipation and Thermal Resistance
(Note 1)
Cavity DIP (D) Po (25°C)
LF152
LF252
LF352
±22V
±44V
±22V
Continuous
±18V
±36V
±18V
Continuous
±18V
±36V
±18V
Continuous
I
°jA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering. 60 seconds)
900mW
100°C/W
+150°C
-55°C-::;TA -::; +125°C
-65°C-::;TA -::;+150°C.
300°C
'dc electrical characteristics
(Notes '2 and 3)
900mW
100°C/W
+110°C
-25°C -::; T A -::; +85°C
-65°C -::; TA -::; +l50~C
300°C
900mW
100°C/W
+100°C
O°C -::; TA'-::; +70°C
-65°C -::; TA -::; +150°C
300°C
PARAMETER
LF152
CONOITIONS
MIN
GR
G'
Gam Range
. Gam Equation
RC'= IS0n, CC"
0.002~F
TYP
1
LF252/LF35:r.
MAX
.MIN
1()oq
1
TYP
MAX
UNITS
1000
G = RS/RG
GE
Error From Ga!n Eqll3tlon
TA = 25 C, G = 1-100, RL = 10k
0.05
0.1
0,05
0,2
%
GNL
Gam Nonlmearlty
TA = 25'C, G = 1-100, RL
=10k
0,02
0.05
0,02
0,1
%
f
IIG liT
Gam Temperaturp CoeffiCient
Vo
Output Voltage Range
RL = 2k
RO
Output Resistance
T A = 25" C, G = 1
3
Input Voltage Range
IS
Input Bias Current
TA = 25"C
',0
Input Offset C\-Irrent
TA=25'C
R'N
Input ReSistance
±9
i 10
CMRR
3
0.5
0,3
±12
40
pA
20
0.2
3
nA
10
0,5
20
pA
2.0
0.05
O.S
nA
2.,0'2
n
2.,0'2
n
Differential
2.5
2,5
pF
Common-Mode
5.0
5.0
pF
Common-Mode ReJe~tlon
G=1
IRTI) INot.41
G = 10
Input Offset Voltage
c
75
85
95
105
110
115
TA = 25' C
Supply Sensitivity
VOOS
lIVOOS,lIT
Output Offset Voltage'
65
85
80
dB
100
dB
125
100
125
105
120
120 .
dB
8
'10
Temperature CoeffiCient
- lIV,OS/lIV S
,
15
100
TA'25'C
15
SOO
Supply Sensitivity
~VIV
800
20
RREF
Reference Input ReSistance
500
250
IS
Supply Current
2.2
mV
~vfc
15
0.7
~VIV
600
400
. 9-2
mV
~vfc
400
Reference Current
TA" 25"C
30
200
·200
Temperature CoeffiCient
dB
10
IREF
lIVOOS lIVS
V
3
TA=2S'C
G = 1000
VIOS.
20
2.'0 '2
2.10 '2
G = 100
lIV'OS,lIT
±10
3
TA = 25'C
Differential
Input Capacitance
V
n
1.5
±12
Common-Mode
C,N
ppmfC
±9
1.2
,
VIN
3
1.2
~A
Mn
2.2
mA
ac electrical characteristics
Noi.e Voltage (RTII (Note 51
en
I
lf252/lf352
lf152
CONDITIONS
PARAri4ETER
MIN
TA = 2.5"C
0.1 HZ-10Hz
10 Hz - 10 kHz
TYP
MIN
MAX
TYP
1.3 I 670/G
in
Noi.e Current (RTII (Note 51
TA = 2S"C, 10 Hz - 10 kHz
Small Signal Bandwidlh
TA = 25"C, .JdB
G=1
G = 10
G = 100
G·l000
TA '" 2S"'C• .1;1%'Flatness
G=1
G = 10
I'Vp·p
pVrms
0.01
0.01
pArms
140
140
50
'30
kHz
kHz
50
30
7
5
4
2
I.S
G = 100
G = 1000
UNITS
MAX
1.J'670/G
B'4S0/G
81450/G
GBW
7
kHz
kHz
5
4
2
1.5
kHz
kHz
kHz
kHz
PBW
Full'Power Bandwidth
25
25
kHz
SR
Slew Rale
1
.1
VII's
ts
Setlling.Time 0.1%
15
15
40
15
15
40
200
200
TA = 2SoC
G= 1
G= 10
G = 100
G = 1000
I'S
I'S
I'S
I'S
Nata 1: The maximum power dissipation for these devices must be derated at elevated temperatures and .is dictated bV Tj MAX, 6jA, and the
ambient temperature, TA' The maximum available power dissipation at any temperature is Po = ITJ MAX - TAII6jA or the·25"C Po MAX,
whichever is less.
Nate 2: These specifications applv for Vs = .,5V and over the absolute maximum operating temperature range ITl ~ TA ~ TH) unles. otherwise
noted. Parameters are specified for RC = lS011, Ce = 0.0021'F, and a proper lavout such as the PC board in Figure 7, which i. laid out for
Figure 2 and Figure 4.
Nate 3: If VOOS adjust i. not used, pins 1,2 and IS MUST be shorted to VCC.
Nat. 4: Referred to input IRTII. Mav be referred to output bV subtracting gain in dB.
Nat. 5: Referred to input IRTI). Mav be referred to output by multiplving by gain G.
typical performance characteristics
Input Bi.. Current
Supplv Current
10k
i...
..
1l
YA
It
Ci
.!
...
.....
i..
::l
,15V:5 Vs :5 daV ~
IOU
10
!!
• 5Y
I
-25
sV'r" tlOV
25
75
:1
"I::
i~
"or
ZD
II
:::~-
f-- +12r'~:.......
12
.... • II"'....." ~
~
-
-
-
-.,., ~
~~
-.
,,-
-II
I:::
-12
"I::
B~
.....
-I
~
-4
> ..
+!::~::-.. t-....
-55"C-""':
~~
;::>
!AI
10
15
POSITIVE SUPPLY VOLTS lVI
2D
~
[--.....~ I""'"
0
4
8
I
12
I
16
28
24
Z8
i.,...
......
Vs - 'ISV
15
10
i!:
"""'= ~ ~
1\ i'.: I'-.
\
5
+125 C
-55 C
>
E
+251C
2
9-3
'-I.
..."
.A ~
-I.
-IS
NEGATIVE SUPPLY VOLTS (V)
G -I
Positive Currant Limit
c
.!:;
>
",.
-I
o =IIHHI
G -10
LOAD RESISTANCE Iknl
a
5
..,..,
0.1
20
15
~
.,
-
II
G -IOU
18
-20
~
C
Noptive Comman-Mada Input
Voltage Limit
i:!ls
I
~
SUPPLY VOLTAGE (,VI
4
•
+IU'r-
I
0.01
5
125
u!:;
2:>
i
+2~ ~
O.S
Politive Common-Mode Input
Voltage Limit
~
~~
....,.. ~ I -
,...-
1.0
..:s
...."
..
.,
>I::
1.S
TEMl'ERATURE ('CI
...
Vs' ,ISV
TA -ZS'C
§
u
~
ii
...
i!
Gain Nonlinearitv
10
Z.O
::l
I
I
!
(Notes 2 and 3)
-20
0
5 10 IS 20 25 30 35
OUTPUT SOURCE CURRENT (mAl
typical performance characteristics (can't)
Cammon-Mode Rejection
Ratio (RTII
eoinmon-Mode Rejection
Ratio (RTII
Negative Current Limit
~
.'"
~
w
-IS
'"
~
c
>
~,
-5
- '\"
c
~
.=
"
t
;;;
=
, w
.
...
~
-10
5
e:
c"
m
:s
VS' 'lsV
-
,... \\
-+2s'C
-i
~
"
c
+125 C
\-SS"C
10
25
IS. 20
3D
.
"fi1
160
l' \'il'SOURC'E'
UNBALANCE
140
,,"s= +t5V
1,2~
TA"2s"C
'1111
G'1000
80
~l'l~b
60
~1,~
40
8
20
'~!~,,1
c
-= ~~I§II~i"~""~~"""
5
':
Q
0
10
100
~ 1~1=11°~I°="IIITIA=12SI·CI
..
10k
lk
m
:s
c
~
CI:
z
20
8
0
w
..
60
40
lOOk
100
160
"!:;
,6~
=
~
!!!=
~
.
a; 160
..
TA=2S-C
140
120
= 100
G = 1000
!!i
t
G = 100
;;;a:
8 =10
G ~1
20
G = 1000
8 = 100
80
G =10
>-
,~~
8 '1
!!!=
20
't'
i;j
40
40
~
o
10
FREQUENCY lib)
100
lk
10k
10
Vs= ±15V
I-+--+-+++-+TA • 2S"C
1-+--+-+++-+8 ;,0
I-+---b-+-+++~~: ~:~;:F
'"
.
lk
s
VS·"SV'
1-1-+--+-++-+ TA • 2S'C
1-1-1-1-+-+--1- 8 ·100
~
g
..
'2
~
w
ovl-t-+--+-++-+-+-f--'1H
~
.~
. ,1-f-+--+-++-R\-+-f-4H
~
OV
I-I--,++++-+;~: ~:~;-F
I
,
~
>
5
..~
.~
....
",
TIME IS.,/DIV)
TIME f5J,1s/DIV):'
s
~E
Vs = t15V
TA"WC
G = 1000
Cc =0.002.F
RC ~ 160ll
.
'"
OV
II
1\
1\
'(G = 10)
s
s
;;
.>
:~
..
.'"
~.
'"
~
VS' .15V
TA' 2S"C
G = 10
Cc' O.OO2pF
RC -160n
'~
ovl--H--+-+++-+--+-f----'H
i..
'"
"
OV
!:;
co
>
.~
"~
Large Signal Pulse Response
(G = 1)
">
c
...>
TIME 120.,/DIV)
Large Signal Pulse Response
Small Sillnai Pulse Response
(G = 1000i
10k
'
(G= 100)
s
2
.'
Small Signal Pulse Response
(G = 10)
~
.
FREQUENCY IHt)
-~
Small Signal Pulse Response
~E
100
.
FREr;J.U,ENCY (Hz),
Small Signa) Pulse Response
(G = 1)
1M
Negative Power Supply Rejection
~
80
lOOk
Ratio (RTW
120
;;;
10k
.
:s
100
lk
SOURCE IMPEOANCE UNBALANCE Ill)
140
CI
.t
'"~
G=1
..
i
0:
Positive Power Supply Rejection
Ratio (RTII
Frequency Response
w
G =10
~ ·120
80
FREQUENCY 1Hz)
OUTPUT SINK CURRENT ImAl
~
-FCM=&OHz
Vs = :t15V
140
160
100
lor
"
3S
'.
:','
5
~
co
c
1-1-
I
I
'I
TIME 120.S/OIV)
TIME (lOO.,IDIY)
9-4 ..
typical performance characteristics (con't)
Larg~ Signal Pulse Response
(G = 1001
;;
~
."
w
;;
Vs - t15V
TA -25'C
G -100
Cc - 0.002pF
R -160!!
~
"
Large Signal Pulse Response
(G = 10001
(
~
"
z
~
,
ov
" ov f-if-t-t-t--t--tt--j---t--t---t
~
\
"....>
'"....
"'"
1
~
>
....
.~'"
~
"
TIME (1DO/Js!DIV)
Equivalent Input Noise
Voltage
~
Output Resista":ce
lOOk
~
w
.."
10k
~
>
"w
~
;;
z
lk
....
'" 100
;;;
'"
~
....
;.
10
'"
"
>
;;
ffi
10
100
. lk
10k
lOOk
10
FREQUENCY IH,)
100
Ik
10k
FREOUENCY (Hz)
application hints
BASIC OPERATION
The lF152 is. a monolithic JFET input differential
current feedback instrumentation amplifier. The BIFET process used to fabricate the LF152 makes it
possible to· ta~e advantage of JF ETs throughout the
design_ In the simplified schematic of Figure 1, the
differential input voltage is impressed across resistor
RG via the input JFETs, while the difference between
the sense and reference voltages is impressed across
the resistor RS. The gain of the amplifier is determined
by the ratio of resistor RS to resistor RG (G = RS/RG).
(For clarity let's follow a signal through the amplifier:)
common·mode rejection, low gain non-linearity,
extremely low bias currents and very high,· input
impedance.
INPUTS,
The P-channel JFET input devices of the LF152 series
provide very low bias currents and very high input
impedances.
The maximum differential input voltage is independent
of the supply' voltages, however, neither of the input
voltages should be allowed to exceed the negative supply,
as this will cause large currents to floiN, which can 'result
in a destroyed unit.
'
In Figure 1, let RG = RS = 1 Mr!, the (-) input be
grounded, and the (+) input be 1 V; the output should
be 1 V. The 1 V signal applied developes lilA through
RG from right to left and unbalances the current drive
to the second stage amplifier. The additional current
driven into the (+) input of the second stage amplifier
causes the output to increase. As Va increases, the
sense input voltage increases and the left side of RS
also increases. When the sense input has risen lV, lilA
will flow through RS from lilft to right and, thus, subtract lilA from I,. An opposite action simultaneously
occurs in 12 which brings the currents into the second
stage and thus the system back into balance.
Exceeding the negative voltage range on either input
cause a reversal of phase to the output and force
the amplifier output to. the corresponding high or
low state. Exceeding the negative input voltage range
on both inputs will force the amplifier output to a high
state. Exceeding the positive input voltage range on a
single input will not change the phase of the output;
however, gail) linearity will degrade. If both inputs
exceed the positive input voltage range, .the output of
the amplifier will be forced to a high state.
~ill
The common-mode slew rate of the inputs should be
'limited to 5V IllS to insure low input bias currents.
The LF 152 series is designed to optimize key parameters
in instrumentation amplifiers: The device has very high
9-5
application hints (con't)
USING THE SENSE, REFERENCE, AND OUTPUT
PINS
independent of gain while the input offset (Vias) is
multiplied by the, gai~ of the amplifier to the output.
The sense input and the output cif the device are pinned
out separately to allow increased flexibility in system
designs (see' applications). The reference input allows
biasing of the output voltage, from +10V to --10V.
The ac input resistance of both the sense and reference
inputs is unusually high because their input currents are
forced to be constant with voltage (typically 20j.lA).
Vas = Vias (G)
+ VOOS
The output offset of the Lf 152 can' be adjusted as
shown in Figure 2. In addition" the LF152 features
input offset adjust which is not common to monolithic
instrumentation amplifiers and is normally available
only on expensive modules. The simple adjust scheme
shown in Figure 5 has only a slight increase in non-linearity compared to that of Figure 4 and is recommended
for most applications. Nulling both input and output
offset makes the overall' offset zero, independent of gain.
The maximum linear output swing is determined by
the magnitude of resistor RS:
1VOMAXI= 10j.lA (RS)
The output offset is affected by adjustment of the
input offset. For every mV of input offset adjust, the
output offset will' change by approximately 32 mV.
Adjustment of the output offset has no effect on the
input offset, so it should always be done last.
If the output of the amplifier is to be abruptly changed
more than 6V, a PNP transistor should be connected,
as shown in Figure 3, to prevent the slew rate of the
output from exceeding the slew rate of the sense stage.
If this precaution is not taken;the base-emitter junction
of the input transistor in the sense stage will transiently
break down and its (3 will degrade, resulting in a permanent negative' shift in output of,fset voltage.
.!......-.....-o
,')I-'
Offset adjustment changes the temperature coefficient
of the Vas drift. The typical i'nput offset drift of the
unadjusted device is '-10j.lVtC. If ~he input offset is
adjusted, the "105 drift in:creases' by approximately
Vias drift"" -10j.lVioC + 2j.lVtC/(mV of adjustment)
OUTPUT
The VOOS drift will be improved by output offset
adjust because the magnitudes of the 'current sources
adjusted become less sensitive to VBE variations. If
VOOS adjust is not used, pins 1, 2 and 16 must be
shorted to the positive supply for Circuit operation.
I _ _ _ _ _ -'
L
OFFSET
VOLTAGE ADJUSTMENT PROCEDURE
FIGURE 3. Large Signal Transient Suppression
For gains less than 100, only output offset,adjustment is
needed. For gains greater than 100, input'offset adjust is
usually necessary since'the input offset voltage amplified
to the output may be out of the range of the output
offse~ adjust. Input offset adjust is also needed if zero
overall offset is desired while varying 'the amplifier gain.
OFFSET VOLTAGE
Because of the two stage design of the instrumentation
amplifier, there are two independent contributors to
offset voltage (Vas). The output offset (VOOS) is
2DDk
lOOk
SDk;
3.9M
2.
51k
50.
10V
~
I
L
-15V
21
FIGURE 5. Simple Input Offset Adjust
FIGURE 4. Input Offset Adj,ust
9-6
52
application hints (con't)
RS and RG should be minimized and the capacitance
from these nodes should also be minimi1.ed for optimum
frequency response. If RC = 160n and Cc = 0.002j.!F in
the printed circuit board of Figure 7, the amplifier will
be compensated for all gains ,from 1 to 1000. Gains
from 0.1 to 10,000 may be obtained with different
compensation.
To adjust the input offset, the following procedure
should be used:
The effective input offset voltage appears directly
across RG when both inputs are connected to ground,
and can be measured by a voltmeter referenced to
ground. This offset error across RG can be zeroed by
the input offset adjustment circuit 'shown in Figure 4
or 5. The remaining error at the output is strictly due
to the output offset voltage which can then be nulled
out with the circuit shown in Figure 2. The amplifier
is now offset nulled independent of gain.
GAIN ERROR AND NONLINEARITY
Gain error of the LF 152 is the error between the average
slope of. the transfer function compared to the slope of
RS/RG. In the LF 152, the small gain error is essentially
constant with gain and may be nulled out by trim·
ming RS.
COMPENSATION
The variable bandwidth and slew rate of the LF152 are
controlled by an RC network betw~en the co~pensa·
tion pins of the amplifier as shown in Figure 2. RC and
Cc may be varied for optimum operating characteristics
in a particular application.
Of the existing monolithic instrumentation amplifiers,
the LF152 is among the lowest in gain nonlinearity
error. Gain nonlinearity is the curvature of the transfer
function from the th~oretically perfect function as shown
,
in Figure 6 . '
Layout of accompanying circuitry may influence the
value of this RC network. The lead lengths to resistors
G IV,N) - VOUT
50mV
0.1% NONLINEAR
...............
I
=r-=+-t-i v,"
~t--F,,,,,,.,.o;'It-....
-10V
-.",.,'
"0V
IDEAL
TRANSFER
FUNCTION
FIGURE 6. Gain Error and Nonlinearity
,',:'
. ..:
LF152
.','
~.'
. >::' ~ ;; :.' ..
~."
. . ,;:
'>~;.
.~ . :: ..~.
<
,.
\•
.,~: ~; '.:'~~i~tsL~·.
FIGURE 7. PC Layout (Bottom View)
9-7
UI
N
.......
r
"'T1
N
UI
N
.......
~
eN
UI
N
N
&I)
M
LL
detailed schematic
...I
.......
N
&I)
N
U.
...I
.......
Col
&I)
~
LL
...I
typical applications
Automati;' V lOS Adjust (G ? 100)
General Purpose Instrumentation Amplifier
+Vcc
200k
ZOOk
LOAD
......
"
~
.
Va
14
For
v,o----....-;-----9
RS
= 1
RG
VO=Va+VREF-Vi,
10 SOURCE OR SINK
S 5 mA
Isolated Sensor
01J'F
{LOW LEAKAGE!
IL
lERO
PULSE
~UT
NC = Normally Closed
NO
= Normally Open
Minimum pulse width to drive
Va to
zero is 400,Us.
9·8
r-
::2
(J1
typical applications (can't)
Automalic VOOS Adjusl (For G
S
N'
100)
.......
r-n
N
(J1
N
.......
r-n
w
:>~~---------------------1~---
'VSENSE RG/RS' The output goes high turning "ON" the heater. If
Va -, Vb < VSENSE RG/RS. The output goes low turning "OFF" the
heater.
'
Alternate Input Offset (VIOS) Adjust Scheme
39Gk
definition of terms
Closed loop gain. G = RS/RG
Gain error. A rotational error of the transfer
function' about the origin.
GNL
Vas
9·10
Gain nonlinearity. Curvature of the transfer
function.
Offset voltage. Voltage offset of the transfer
function at the origin Vas = VIOS(G) + Voas
r-
~National
Amplifiers
~ Semiconductor
."
.....
U1
U1
........
r-
LF155/LF156/LF157 Series Monolithic
JFET Input Operational Amplifiers
3!
(II
BI·FET Technologv
0)
LF155. LF155A. LF255. LF355. LF355A. LF355B low supply current
LF156. LF156A. LF256. LF356. LF356A. LF356B wide band
LF157. LF157A. LF257. LF357. LF357A. LF357B wide band decompensated (AVMIN
........
r-
."
.....
5)
U1
.....
General Description
These are the first monolithic JFET input operational
amplifiers to incorporate well matched, high voltage
JFETs on the same chip with standard bipolar transistors
(BI-FET Technology). These amplifiers feature low input
bias and offset currents, low offset voltage and offset
voltage drift, coupled with offset adjust which does not
degrade drift or common-mode rejection. The devices
are also designed for high slew rate, wide bandwidth,
extremely fast settling time, low voltage and current
noise and a low 1If noise corner.
•
•
•
•
en
(LF155A, LF156A, LF157A)
• Low input bias current
• Low input offset current
• High input impedance
• Low input offset voltage
• Low input offset voltage temperature
drift
• Low input noise current
• High common-mode rejection ratio
• Large dc voltage gain
Replace expensive hybrid and module FET op amps
Rugged JFETs allow blow·out free handling compared
with MOSFET input devices
Excellent for low noise applications using either high
, or low source impedance-very low 1If corner
Offset adjust does not degrade drift or common-mode
rejection as in most monolithic amplifiers
New output stage allows use of large capacitive loads
(10,000 pF) without stability problems
Internal compensation and large differential input
voitage capability
30pA
3pA
10 12[2
1 mV
3p.VtC
0:01 pA/v'Hz
100dB
106 dB
Uncommon Features
LF155A LF156A LF157A
(Av= 5)*
•
Applications
•
• Precision high speed integrators
• Fast DI A and AID converters
• High impedance buffers
• Wideband, low noise, low drift amplifiers
• Logarithmic amplifiers
•
•
Extremely
fast settling
time to
0.01%
Fast slew
rate
Wide gain
bandwidth
Low input
noise voltage
1.5
1.5
p.s
5
2.5
12
5
50
20
V/p.s
20
12
12
nV/-.!Hz
16)
OUT
LF157
9-11
UNITS
4
Simplified Schematic
*c = 2 pF'on
..._.
C'D
Common Features
Advantages
•
•
en
C'D
• Photocell amplifiers
• Sample and Hold circuits
MHz
rn
Q)
't:
Q)
en
l"'-
'll)
u:
..J
......
co
II)
u:
..J
......
II)
II)
u:
..J
Absolute Maximum Ratings
LF155A/6A17A
Supply Voltage
LF355B/6B17B
LF255/6/7
LF355B/6B17B
LF155/617
±22V
±22V
150"C
150°C
LF355A16A17A
LF355/617
±22V
±18V
Power Dissipation (Pd at 25" C)
and Thermal Resistance (BjA) (Note 1)
TjMAX
(H and J Package)
(N Package)
(H Package)
Pd
115"C
115°C
10Cfc
670mW
670mW
570mW
10Cfc
570mW
150"C/W
150°CIW
150°CIW
15CfcIW
(J Package)
BjA
,Pd
670mW
570mW
570mW
140"CIW
140°CIW
140°C/W
140°CIW
(N Package)
BjA
Pd
670mW
,
BjA
Differential Input Voltage
±40V
Input Voltage Range (Note 2)
±20V
Output Short Circuit Duration
PARAMETER
Continuous
Continuous
-65°C to +150°C
-65"C to +150°C
300°C
300"C
300°C
300"C
(Note 3)
J
MIN
RS= 50n, TA = 25°C
Average TC of Input
LF355A16A/7A
LFl55A16A/7A
TVI'
MAX
MIN
2
1
Over Temperature
aVOS/aT
±30V
±16V
Continuous
CONDITIONS
Input Offset \loltage
VOS
±40V
±20V
-65°C to +150°C
Lead Temperature (Soldering, 10 seconds)
DC Electrical Characteristics
500mW
155°CIW
-65°C to +150°C
Continuous
Storage Temperature Range
SYMBOL
±40V
±20V
500mW
155°CIW
TYP
1
2
2.3
;a'
5
2.5
RS = son
3
RS = 50n, (Note 4)
o.s
5
UNITS
MAX
mV
mV
Ilvfc
Offset Voltage
aTC/aVOS
Change in Average TC
Ilvfc
0.5
with VOS Adjust
,
lOS
3,
Tj = 25°C, (Notes 3, 5)
I nput Offset Current
10
Tj~THIGH
IB
30
50
TJ~THIGH
TJ = 25°C
AVOL
Large Signal Voltage
Vs ~ ±15V, TA = 25"C
50
Gain
Vo = ±IOV, RL = 2k
Over Temper.ature
25
I nput Common-Mode
CMRR
50
pA
5
nA
50
200
±12
:t13:
±10
±12
+15.1
±11
-12
I
VlmV
±12
Common-Mode Rejection
VlmV
- 25
±13
±11
nA
n
200
±12
VS= ±15V
Voltage Range
' 30
. ±10
Vs = ±'15V, RL = 10k
Vs = ±15V, RL = 2k
VCM
pA
1012
10 12 ,
Input Resistance
Output Voltage Swing
10
1
25
RIN
Vo
.
3
10
TJ ='25°C, (I\jotes 3, 5)
Input Bias Current
permV
V
V
V
V
+15.1
-I.2
85
100
85
100
dB
85
100
!l5
100
dB
Ratio
PSRR
Supply Voltage Rejection
, (NoteS)
Ratio
AC Electrical Characteristics
SYMBOL
SR
CONDITIONS
PARAMETER
Slew Rate
TA; 25°C, Vs; ±15V
,
LFI55A/6A;AV= 1,
LFl55A1355A
MAX
TVI'
MIN
5
3
LF156A1356A
MIN
TVI' MAX
10
2,5
Gain Bandwidth
4
4.6
UNITS
Vllls
12
LF157A; AV = 5
GBW
LF157A1357A
MAX
''fYP
MIN
40
50
15
20
V/lls
>
MHz
Product
~.Ol%
ts
Settling Time to
en
Equivalent Input Noise
Voltage
(Note 7)
RS= lOon
f=100Hz
f= 1000Hz
in
CIN
Equivalent Input
f= 100 Hz
Noise Current
f=1000Hz
I nput Capacitance
.'
4
1,5
1.6
IlS
"
,15
12
15
'nW/Hz
12
nVI$.
0.01
0.01
0.01
'0.01
0.01
0.01'
pAl$.
pAl$.
3
a
3
25
. 25
9-12
pF
r-
DC Electrical Characteristics
~VOS/~T
I nput Offset Voltage
Average Te of Input
LF355/6i7
LF355B/6B/7B
MIN
(J1
(J1
MAX
.......
mV
".....
MAX
RS =.50n, T A = 25°e
Over Temperature
3
5
7
RS= 50n
5
5
5
pvfe
RS = 50n, (Note 4)
0.5
0_5
0.5
pvfc
Tj ,= 25°C, (Notes 3, 51
3
TVP
TVP
UNITS
TVP
MIN
VOS
LF255/6f7
LF155/6f7
CONOITIONS
PARAMETER
SYMBOL
".....
(Note 3)
MIN
5
3
r-
MAX
10
13
3
6.5
(J1
mV
en
.......
r-
Offset Voltage
~Te/~VOS
Change in Average TC
Input Offset Current
Tj:::;THIGH
IB
30
T J = 25°C, (Notes 3, 5)
Input Bias Current
AVOL
Va
VCM
20
20
3
100
30
20
1
3
100
30
5
50
TJ:::;THIGH
RIN
pA
nA
200
pA
8
nA
1012
10 12
1012
50
2
n
Input Resistance
TJ = 25°C
Large Signal Voltage
VS= ±15V, TA = 25°C
Va = ±10V, RL = 2k
Over Temperature
.50
Gain
Output Voltage Swing
VS=±15V,RL= 10k.
±12
t13
±12
t13
±12
±13
VS=±15V,RL=2k
±10
±12
±10
±12
±10
±12
V
V
±11
+15.1
-lZ
±11
+15.1
,V
VS=±15V
B5
100
B5
100
BO
100
dB
B5
100
85
100
80
100
dB
Input Common-Mode
Voltage Range
CMRR
Common-Mode Rejee-
PSRR
Supply Voltage Rejec-
200
25
25
200
50
25
VlmV
200
VlmV
15
,
+15,1
±10
-12
-12
V
tion Ratio
(Note 6)
Ratio
DC Electrical Characteristics
TA; 25°C. Vs; ±15V
,
LFI55A/155,
LF255.
LF355A/355B
PARAMETER
LF156A/156,
LF256/356B
LF355
I
MAX
TVP
I
MAX
TVP
I
MAX
TVP
2
I
4
2
I
4
5
I
7
5
AC Electrical Characteristics
SYMBOL
SR
GBW
PARAM~TER
Slew Rate
I
LF357A1357
MAX
TVP
MAX
TVP
I
MAX
10
5
7
5
I
10
UNITS
mA
TA; 25°C. Vs; ±15V
CONOITIONS
LF155/6: AV = 1,
LF157: AV = 5
Gain Bandwidth
LF157A/157
LF257/357B
LF356A1356
TVP
Supp'y Current
LF155/2551
355/355B
LF156/256,
lF356B
LF156/2561
356/356B
TVP
MIN
TYP
S
7.5
12
LF157/257,
LF357B
MIN
LF157/2571
357/357B
TYP
UNITS
Vips
30
50
Vips
MHz
2.5
5
20
Product
ts
Settling Time to 0.01%
(Note 7)
4
1.5
1.5
I-IS
en
Equivalent Input Noise
RS= lOOn
f= 100 Hz
25
15
20
12.
15
12
nV/VHz
f= 1000Hz
Equivalent Input
f = 100 Hz
0.01
0.01
pA/VHz
Current Noise
f=1000Hz
0.01
0.01
0.01·
0,01
3
3
3
Voltage
in
CIN
Input Capacitance.
"
permV
with Vas Adjust
lOS
.....
9-13
nV/VHz
pA/VHz
pF
(J1
~
-
en
(1)
:::!.
(1)
UJ
CI)
Q)
'~
G)
UJ
.....
....
It')
LL
..J
.......
co
It')
u::
..J
.......
It')
It')
....
LL
..J
Notes for Electrical Characteristics
Not8 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX. 8jA, and the
ambient temperature, T A. The maximum available power dissipation at any temperature is Pd
= (TjMAX
- TA)/OjA or the 25°C PdMAX. which~
ever is less.
'
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage .
Note 3: Unless otherwise stated, these test conditions apply:
L F155A16A17A
LF155/617
LF255/617
LF355A/6A17A
±15V
TA
s: Vs s: ±20V
-55°C s: TA s: +125°C
s: Vs s: ±20\(
-25°C s: TA s: +85°C
s: Vs s: ±18V
O°C s: TA s: +70°C
THIGH
+125°C
+85°C
+70°C
Supply VoltagerYs
±15V
±15V
LF355B/6B/7B
LF356/6/7
s: Vs ±20V
O°C s: TA s: +70°C
_±15V
VS= ±15V
s:
s: +70°C
O°C TA
+70°C
+70°C
and VOS. IS and lOS are measured at VCM = O.
Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (O.5p.V JQe tYr,lically) for each mV of
adjustment from its oli9inal unadjusted value. Common-mode rejection and apen loop voltage gain are also unaffected by offset adjustment •
Note 5: The input bias currents are junction leakage currents which,approximately d?uble for every 10°C increase in the junction temperature, TJ.
Due to limited production test time, the input bias curren.ts measured are correlated to junction temperature, In normal operation the junction
temperature rises above the ambient temperature as a result of internal power dissipation, Pd. Tj = T A + 0jA Pd where 0jA is the thermal
resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum .
Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common
practice.
Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kn resistors for the LF155/6. It is the time required for the error
voltage (the voltage at the inverting input pin on the amplifier) to'settle to within 0.01 % of its final value 'from the time a 10V step input is applied
to the inverter. For the LF157, AV = -5, the feedback resistor from output to input is 2 kH and the outputt step is 10V (See Settling Time Test
Circuit, page 9).
Typical DC Performance Characteristics
Curves are for LF155, LF156 and LF157 unless otherwise specified.
Input Bias Current
!
5
ll1t1k
10k 1--1~-+-+-t--+-"
j
10k
ffi
I'
~u
:.!
iii
~;!
1k
Input Bias Current
Input Bias Current
,---.,---r-,.--,.---,--'-,
lOOk
r-~~~-+--t-~~,
~
100
10 1--t--:'-:;':fZ~--1I--+-I
:.!
iii
80
".,.
l-
~
~
100
:!
iii
10
~
!;
~
LF1S6/7
OJ L.....-'-_-L--lL..--L-_.L-....I
-25
3S
65
95
-55
125
-25
5
35
65
95
Voltage Swing
ii
RL -2k
TA a 25"C
....~
.e
~
/
I.-- V
/
20
10
SUPPLY VOLTAGE I,VI
-15
ii,
'"~
-10
r'" t'-.. -......"
\ "\
~
!;
.
S
-5
-- -
~
15
'"
ii
w
~
~'C
"-:5'C
15
20
v
~
-
~.
125",
!::
~
;:
5
10 15 20 25 30
OUTPUT SINK CURRENT (rnA)
35
II
C
a
10
15
20
SUPPLY VOLTAGE (
+125°C
16
/
'"~
'"'"
B~
..
+25"&
5 • 10
;/
-55'C ';;TA ';;125"C
--r
t\
10
25
Positive Common-Mode. Input
• Voltage Limit
20
i
$
l(LJc
", ......
··I"T
2
VS'''15V
,.~
\
eriC
..... ~
L~lsJn
25
Positive Current Limit
VS-~15V
~~
'"
10
0;!-5~'C
SUPPLY VOLTAGE (±V)
Negative Current Limit
~
5
;I
.i
I
LF155
15
-5
I
TC'25"C'
~
~
-10
1
f-- t:;: ~125"C
10
Lf15lJ7
W1TIfHEATStllC
~:~~5AIR, J.....V
20
,.- J-.l.- ~
10
lFI5S
I-"
I I
a
P
COMMON-MODE VOLTAGE (VI
TC'-55'C
/
10
r-~
30
WlTNlfEATSlftK
125
I
I
V
V
UI56/7
40
V'
Supply Current
V
30
20
I
50
Supply Current
40
'"
V
RL -SDk
50
CASE TEMPERATURE I"CI
CASE TEMPERATURE 10e),
~
Vs= ::!:.15V
TA-Z5"'C
70
40
V
5
V
10
15
POSITIVE SUPPL Y VOLTS IV)
za
r-
Typical DC Performance Characteristics
U1
U1
Nagative Common·Made Input
Voltage Limit
10M
,
",
,,-
W"
~z
C
co
co
Z8
RL -Zk
RS'5D
~
TA' -55'C
~
co
>
24
to-
20
~
co lOOk
~
~
co
~
'"~
""
1M
~
~
~
3!
U1
0)
.......
r-
16
."
-'"
12
U1
"~
4
-15
r-
~i"'"
"
o
-10
VS'" ±.15V
TA·25'C
to-
z
Il!
co
-5
.......
Output Voltage Swing
Open Loop Voltage Gain
-zo
r-T1'-5Jc __
~
TA'Z5'C
r--TA-1Z5'C ~
3!
(Continued)
-ZO
10
15
SUPPLY VOLTAGE (.V)
NEGATIVE SUPPLY VOLTS (V)
20
......
V
o
1.0
OUTPUT LOAD RL (k!l)
10
C/)
...
CD
CD'
til
Typical AC Performance Characteristics
Gain Bandwidth
\.
r- Vs -'.,0V- -
~ ~. - I Vs-±\5V_
~ ~.J- Vs - ±20V
~
...
I I I I I
~-
LF155
~
Normalized Slew Rate
Gain Bandwidth
5
LF151 CURVES IDENTICAL
BUT MULTIPLlEO 8Y 4
\.\.
-
1.2
1.0
~
I
v~ • •i5V
i'J'5L
~r;sp
0.8
-
±10V
.ZOV ~ IIr
~V
r
I
LF155 Small Signal Pulse Response,
AV-+l
1.4
I I
~
-55 -35 -15 5 Z5 45 65 85 105 lZ5
TEMPERATURE ('C)
1.6
LFI56
~
roo !""
1.8
-55 -35 -15 5 25 45 65 85
TEMPERATURE ('C)
0.6
0.4
0.2
===lZ5
105
o
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE I'C)
LF156 Small Signal Pulse Response,
AV =+1 '
LF157 Small Signal Pulse Response,
AV=+5
I
II
I
I
-= -
' 1m --
I
I
II
TIME (O.5""OIV)
TIME (0.5 "siDIV)
TIME (0.1 ""OIV)
LF155 Large Signal Pulse Response,
AV-+l
LF156 Large Signal Pulse Response,
AV-+1
LF157 Large Signal Pulse Response,
AV=+5
.1
I
I
a
I
I
I
I
-t--t-t-';
-I-
I!!!!
I
"
TIME (1 ""OIY)
TIME (1 ""OIV)
9·15
TIME (D.5.siDIV)
Typical AC Performance Characteristics
10
lF155
TA'25°C
.VS' ,'5V
~
1111
~
111
/J
~
/
110
10 '--""""""'T"!'TT1"I'MrM-'-'T"1-rnm
iit
Ih mV
"0mvj
ff:
Open Loop Frequency·
Response
Inverter Settling Time
I nverter Settling Time
e;
(Continued)
~
....
'"..
~
-5
II/III
o
0.5
SETILING TIME
VS' "5V
1-'
-25
-30
.1-
.
.
15
75
10
-"- i"i::....u
-5
-
50
.
-25
-75
r\
!1l
!z
-10
12 -'-
.F156
w
..
..l5~
~
c-.
i
cr:
Av"
<1% OIST
FREQUENCY (Hz)
75
50
25
~
0
-25
~
''''1
-50
-75
-100
::
~
..
~
j;;-
:s
!!
;;
!1l
lk
10k
lOOk 1M 10M
I I II II f'·
25
20 I-GAI'N
15
I
10
I·
-10
-15
.50
25
,PHASE
1\
o
'"
.,
m
-125 .
-150
11111111
-175
10
100
FREQUENCY (MHz)
Ratio
.
iit
120
~
cr:
100
~;;J
80
:s
z.
40
I--f--+-+--Pl<:\-;
·lk
10k
lOOk
~!
".
. 100
.
;
oS
..
100
>
IlIlin
lIliK
1
10
!!
....
~
c
111m
'1l1li
9·16
It·
101r"
.........
lOOk'
'IM
10M:
Ik
10k
>
:;
::l
TA'2~~':"""
' Vs ~';!:~5V
,.
80
60
...~
if
FREQUENCY (Hz)
......
"-
100
!l!
5 '40
z
o
"
.1 ..
Equivalent Input N.oise
Voltage (Expended Scale)
~);
60
10M
..
_NE~ATIVEISUPPlY
w
20
I'"
20
I
\
L\
\1\.
.....
20
'LF155
.tFI56/7· .
10
.
. "."" "
fREQUENCY (Hz).:·: .'
120
lFIS6n
"........
fjl
cr:
1M
TA·25°C
VS' ±15V
40
{O~~T:~~SUPPl ~~
40
Equivalent Input Noise Voltage
140
VS .. ±15V:
"-
+~lFI~
~
100
TA' 25°C
.........
cr:
~
II:
'20
60
r-..
~
-100!!!
It,
I
~
-25 ~
-50 en
-75
-~.
=~.
-20
-150
100
10
100
75
lF157
VS~±15V
""'-.L
-5
-125
80
lF157
AV'S
·IM·
30
I--t-''''r+-''Irl--
10
g~
lF15
lOOk
100
~
~
....
X'N
10k
100
FREQUENCY 1Hz)
VS' ±15V
Rl'2k
TA=2SoC
20
35
60
1M 10M'
.... -+-++
~
125
~.
Undistorted Output Voltage Swing.
~
z
~
-~
""
FREQUENCY 1Hz)
28
'X
,.
10
z
';>'
8
100
~ l'\.
Power Supply Rejection
~lF!57
~
10
I\.'\.
10
0
-10
Power Supply Rejection Ratio
Vs "tl'5V
Rl' 2k
TA'2SoC-
:;
20
30
FREQUENCY (MHzI .
'\'I\. .
lF155~ "\
z
~
-,
1
Common·Mode Rejection
Ratio
100
=
-
. -. I
lF156
r---lFI5~ ."-
FREQUENCY (HzI
. 'lFI'5J II
II
FREQUENCY (MHzI
iit
III
iit
-,
n157
""~
-
(.,1
I ~~lSE. Vs ±15V
'lIl"i'
3!
;;
rrp'
-15
-20
z
,",,'\.
I\.'\.
Bode Plot'
100
25
VS' ±15V--'
~
Bode Plot
I
I
iit
:s -10
:~ cr:
50
10
10
1.0
GAIN
-S
..
...
..'"
;
:'1-..1
~Hls~1. f-l~'5~ I I.
S
:s
70
~.
Bode Plot
18
.
w
::
10mV, lmV
SETTliNG TIME ,",I
-10
z
90
...
'"
~
:s
Ik
FREQUENCY (Hzl
lOOk
Typical AC Performance Characteristics
Output Impedance
§
100
w
z
:5'"
~
3!
~
10
~
10
~
r
100
w
~
.......
Output Impedan,:e
Output Impedance
1000
§
r
."
.....
01
01
(Continued)
l-
..'"~
::!
;§
.~
I-
!;
..
.
~
0.1
'"
m
.......
r
lOOk
10k
1M
10M
FREQUENCY 1Hz)
FREQUENCY 1Hz)·
FREQUENCY 1Hz)
"TI
.....
01
.....
0:1
0.01 L-1...LJ.J_--'-J.JJ.WlL--I-JoL-UWJ.....w.........
. 10M
lOOk
1M
Ik
10k
10M
01
1=0'*11""--'::::
'"~
::'"
10k·
10
(J)
CD
:!'..
CD
(J)
Detailed Schematic
r----------------1~----------._~~--------~1r------~._---------------O.vcc
III
BALANCE
""'
R7
RS
3k
SO
""
'EE
,"
*C = 2 pF on LF157
Connection Diagrams
(Top Views)
Dual-In-Line Package
BALANCE
Metal Can Package
Ne
INPUT
Order Number
LF157AH'
LF155AH
LF156AH
LF155H
LF156H
LF157H
LF255H
LF256H
LF257H
LF355AH
LF356AH
LF357AH
LF355H
LF356H
LF357H
Sea NS Package HOSB
INPUT
vvNote 4: Pin 4 connected to case.
Order Number LF35'5N. LF356N or LF357N
See NS Package NOSA
Order Number LF355J. LF356J or LF357J
See NS Package JOSA
9-17.
Application Hints
The LF155/6/7 series are op amps with JFET input
devices. These' JFETs have large reverse breakdown
voltages 'from gate to source and drain eliminating the
need for' ~Iamps' across the inputs. Therefore large
differential input voltages can easily be accomodated
without ~ large increase in input current. The maximum
differential input voltage is independent of the supply
voltages. However, neither of the ',input voltages should
be allowed to exceec\ the negative supply as this will
cause large currents to flow, which can result in a
destroyed' unit.
in polarity or that the unit is not inadvertently installed
"backwards in 'a socket as an unlimited current" surge
through the resulting forward diode within the 'IC could
cause fusing of the internal conductors and result in a
destroyed unit.
Because these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.
All of the bias currents in these amplifiers 'are, set by FET
current sources. The drain currents for the amplifiers are
therefore ,essentially independet1t of supply voltage.
Exceeding the negative c~mmon'mode limit 'on'either
input will ,cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state. Exceeding the negative common·mode
limit on both inputs will force the amplifier output to a
high state. In neither case does a latch occur since
raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a
normal operating mode.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. For example,'resistors from the
output to an input should be placed with the body 'close
to the input to minimize "pickup" and maximize the
frequency of the feedback p~le 'by minimizing the
capacitance from the input to ground.
Exceeding the positive common-mode limit on a single
input will not change the phase of the output however,
if both inputs exceed the limit, the output of the
amplifier will be forced to a high state.
A feedback pole is created when the feedback around
any amplifier is resistive. The parallel resistance and
capacitance from the input of the device, (usually the
inverting dnput) to ac grou(1d set the frequency of the
pole. In many instances the frequency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and consequently there is negligible
effect on stability margin. However, if the feedback pole
is less than approximately six times the expected 3 dB
frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the
added capacitor should be such' that the RC time
constant of this capacitor and the resistanc~ it parallels
is greater than or equal to. the original feedback pole
time constant.
These amplifiers will operate with the common-mode
input voltage "equal to the positive supply. In fact: the
common-mode voltage can exceed the positive supply by
approximately 100 mV independent of supply voltage
and over the full operating temperature range. The
positive supply can therefore be used as a reference on
an input as; for example, in a supply current monitor
and/or limiter.
'
Precautions should be taken to ensure that the power
supply for the integrated circuit never becomes reversed
Typical Circuit Connections
Vos AdjustmQt1t
Driving Capacitive Loads
LF157. A Large Power BW Amplifier
v'
'II<
50
,v'
v-
v-
•
VOS is adjusted with a 25k
potentiometer
•
The potentiometer wiper is
connected to V+
•
For potentiometers with
temperature coefficient of
•
100 ppmr C or less the
additional drift with adjust
is "', 0.5 I'VrC/mV of
adjustment
Tvpical overall drift: 51'V /
·C t10.5 I'VrC/mV 'of
adj.)
",
*LF155/6 R =5k
LF157
R = 1.25k
Due to a unique output stage 'design, these ampH· '
fiers have the ability to drive large capacitive loads
and still maintain stabilitY. CLIMAX)' '" ~.01 I'F.
Overshoot :s. 20%
, ; settli~g time Its) '" 51'S
9,18
For distortion < 1%' and .. 20 Vp'p
VOUT swing; poWer bandwidth' is:
500 kHz.
r-
::2
Typical Applications
01
01
........
Settling Time Test Circuit
r-
::2
.,5V
01
........
0)
21<.0.\%
*400;0.1%
IU·S
D
•
VOUT
511,0.1%
.0
*1.0k.0.l%
SUMMING
-15Vo.-4'""""-=---+-----...1
•
•
NODE~
Settling time is tested with the LF155/6 connected
as unity"gain inverter and LF157 connected for
~=~
•
FET used to isolate the probe capacitance
r.....
."
01
......
(J)
CD
Output = 10V step
AV = -5 for LF157
..._.
CD
+15V
f/)
Large Signal Inverter Output, VOUT (from Settling Time Circuit)
LF357
LF356
LF355
>
i
I ""DIV
Low Drift Adjustable Voltage Reference
-----,..J
25~ >o....
V+"'5V
•
AVOUT/AT = ±O.002%I"C
•
All resistors and potentiometers should be wire-wound
•
•
•
P1: drift adjust'
P2: '(OUT adjust
Use LF155 for
.. LowlS
.. Lawdrift
...
RJ
18Dk
9-19
Low supply current
t/J
Q)
.~
Typical Applications
(Continued)
Q)
Fast Logarithmic Converter
tn
A,
SOk
,....
r - - - - , . - -.....---'IIIIIr_:=::=O VREF"5~
,...
lI)
I,
+lSV
C2
JDOpf
LL
..J
........
U)
•
lI)
,...
'.
Transient response: 3 I-lS for -tllj = 1 decade
•
Cl, C2, R2, R3: added dynamic compensation
•
Vosadjustthe LF156to minimize quiescent
error
•
RT: Tel Labs typ;OBl + 0.3%tC
LL
..J
........
; Vo
lI).
lI)
,...
LL
..J
IVOUTI
~
[1 + RRT2] kT
q
In Vi [ _ _
R_r_]
VREF Ri
log Vi
Ri Ir
Dynamic rarige: .100 !LA :::: Ii :::: 1 mA
15 decades I , IVOI ~ lV/decade
R2 ~ 15.7k, RT ~ lk, 0.3%(C· (for temperature compensationl
Precision Current Monitor
VO~5Rl/R2IV/mAofISI·
•
•
•
Rl, R2, R3: 0.1% resistors
Use LF155·for.
... Commo~·niode range to supply range
.. Low Is
... LowVbs
...
Low
sUPpl~
current
8·Bit D/A Converter with Symmetrical Offset' Binary Operation
I5V
AI
5k
/
Eo .
-15V
•
R1., R2 should be matched within
Full:scale response time: 3 ps
•
±O.O~%
EO
B1
B2
B3
B4
B5
B6
B7
B8
COMMENTS
+9.920
+0.040
1
1
1
1
1
1
1
1
Positive Full·Scale
1
0
0
0
0
0
0
0
1+1 Zero·Scale
-0.040
-9.920
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
I-I Zero·Scale
Negative Full-Scale
9-20
Typical Applications
(Continued)
Wide BW Low Noise, Low Drift Amplifier
Isola~ing
Large Capacitive Loads
0'
"
5.111
...------.....--'Vvv-.....-o VOUT
0'
'MAX"" 2411 kHz
-~:~~
01
+Z~:f
-,v
l
•
Overshoot 6%
ts 10"s
When driving large C L, the VOUT slew rate deter·
mined by CL and IOUT(MAX):
'"
Power BW: IMAX =
240 kHz
2"Vp
Parasitic input capacitance Cl " (3 pF lor'
LF155, LF156 and LF157 plus any additional
layout capacitance) interacts with leedback
•
V-
•
•
•
" 0.02 V II'S = 0.04 V II'S (with CL shown)
0.5
elements and creates undesirable high frequency
pole. To compensate add C2 such that: R2C2",
R1Cl.
Low Drift Peak Detector
. Boosting the LF156 with a Current Amplifier
0'
s.a
v·
01
5.1k
V,.
0,
5.1k
•
By adding 01 and. Rf, VOl = 0 during hold mode. Leakage of
02 provided by feedback path through Rf.
Leakage of circuit is essentially Ib (LF155, LF156) plus capaci·
tor leakage of Cpo
.
.
• Diode 03 clamps VOUT (Allto VIN-V03 to improve speed and
to limit reverse bias of 02.
• Maximum input frequency should be « 1/27TRfC02 where
· C02 is the shunt capaCitance of 02.
T°.1"
•
•
.•
•
IOUT(MAX) '" 150 mA (will drive RL;? lOOn)
AVOUT
0.15
~ = 10-2 VII's (withCLshown)
No additional phase shilt added by the current amplifier
3 Decades VCO
c
O.1l1/lF
Non-lnverting"Unity Gain Operation for LF157
0'
Vpu- 5V
',1
R1C;? (2,,) (5 MHz)
Rl = R2+RS
OS
10k
.
4
AV(OC) = 1
f- 3dB '" 5MHz
Inverting Unity Gain for LF157
R1C;? (27T) (5 MHz)
R2
Rl= 4
VC(R8+R7). ,O!5:'Vc!5:30V,10'Hz!5:f~10kHi'
[8 VPU R8 Rl)C
Rl, R4 matched. Linearity 0:1% over 2 decades:
f=
AV(OC) =-1
f_3 dB'" 5 MHz
9·21
Typical Applications
(Continued)
High Impedance. Low Drift Instrumentation Amplifier
+11Y
+
AJ
+15V
Al
~~",,-oVOUT
AZ
+t5V
-'IV
"
R3 [\2R2
]
.' VOUT=- - - + 1 AV.V-+2VS.VINco~mon"",odesV+
Rl
R
• System VOS adjusted via A2 VOS adjust
• Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier
Resistor array RA201 (National Semiconductor) r
",
"
VINCh
• RON is of SWI
IOUT(MAX)
If inequality not satiifled: T A" VIN Ch
20mA
LFI66 developes full Sr output capability for VIN ~ IV
Addition of SW2 improves accuracy by putting tha voltage drop across SWI Inslda the feedback
loop
Overall accuracy of systein determined by tha accuracy of both ampUfia ... AI and A2
9·22
..,
rTypical Applications
(Continued)
~
01
01
High Accuracy Sample and Hold
..,r........
RI
51k
+1SV
~
01
+ISV
0)
..,r........
>'-<~-OVOUT
~
01'
.....
en
CD
.._.
-15V
-15V
•
•
•
CD
By closing the loop through A2, the VOUT accuracy will be determined uniquely by Al.
No VOS adjust required for A2.
T A can be estimated by same considerations as previously but. because of the added
propagation delay in the feedback loop (A21 the overshoot is not negligible.
Overall system slower than fast sample and hold
•
R 1, Cc: additional compensation
•
Use LF156 for
... Fast settling time
"
tJ)
LowVOS
High Q Band Pass Filter
CI
D.DOlpF
IpF
RI
&2k
VI.
•
By adding positive feedback (R21
•
fBP
Q increases to 40
o-"'""IV'.........-~
R&
&2k
VOUT
VIN
>=--....-'-0 VOUT
R2
•
JOOk
= 100 kHz
•
=
10v'O
Clean layout recommended
Response to a 1 Vp-p tone burst:
300!,s
-ISV
":"
-15V
High Q Notch Filter
V+
>~~-oVOUT
9·23
•
2Rl = R = 10 Mil
2C = Cl = 300 pF
•
Capacitors should be matched to obtain high Q
•
•
fNOTCH = 120 Hz, notch = -55 dB, Q
Use LF155 for
.
"
Low IB
...
Low supply current
> 100
~National·
Amplifiers
~ Semiconductor
LF347 Wide Bandwidth Quad JFET
Input Operational Amplifier
General Description
Features'
The LF347 is a low cost, high speed quad JFET input
operational amplifier with an internally trimmed input
offset voltage (BI-FET "TM technology). The device
requires a low supply current and yet maintains a large
gain bandwidth product and a fast slew rate. In addition',
we" matched high voltage JFET inP!Jt devices provide
very low, input bias and offset currents. The lF347 is
pin compatible with the standard LM348. This feature
allows designers to immediately upgrade the overall
performance of existing LF348 and LM324, d~signs.
•
•
•
•
•
•
•
•
•
2mV
Interna"y trimmed offset voltage
50pA
Low input bias current
Low input noise voltage
16nW/FfZ
0.01 pA/y'Hz
Low input' noise current
4MHz
Wide g~in bandwidth
High slew rate
13 V//1s
7.2mA
Low supply current
1012n
High input impedance
Low total harmonic distortion AV = 10,
<0.02%
RL = 10k, Va = 20 Vp-p, BW = 20 Hz-20 kHz
• Low 1If noise corner
50 Hz
• Fast settling time to 0.01 %
2/1s
The LF347 may be 'used in applications such as high
speed integrators, fast D/A converters, sample-and-hold
circuits and many ,othl!r circuits requiring low input
offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The device
has low noise and offset voltage drift.
Simplified Schematic
BI.FET "TM Technology
1/4 Quad
vcco--------1~----------~~----_,
Yo
INTERNALLV
TRIMMED
INTERNALLV
TRIMMED
-VEE o---~~-----(l-------~~----....J
Connection Diagram
Dual-In-Line Packalle
Order Number LF347N, LF347AN
or LF347BN
Sea NS Package N 14A
TOPYIEW
9-24
I
"T1
eN
Absolute Maximum Ratings
Power Dissipation (Note 1 )
500mW
115°C
Tj(MAX)
Differential Input Voltage
±30V
Input Voltage Range (Note 2)
±15V
Output Short Circuit Duration (Note 3)
Continuous
-65°Cto+150°C
Storage Temperature Range
300°C
Lead Temperature (Soldering. 10 seconds)
DC Electrical Characteristics
VOS
.lVOS/.lT
PARAMETER
Input Offset Voltage
Average TC of Input Offset
......
O°C to +70°C
Operating Temperature Range
SYMBOL
-Ila
±18V
Supply Voltage
(Note 4)
CONOITIONS
LF347A
MIN
TYP
RS= 10 kn, TA = 2S"C
Over Temperature
1
RS'10kn
10
Ti = 2S"C, INotes 4, 5)
25
LF347B
MAX
MIN
2'
TYP
3
4
LF347
'MAX
MIN
5
TYP
MAX
5,
10
7
13
10
UNITS
mV
mV
pvfc
10
Voltage
lOS
Input Offset Current
IS
Input Bias Current
Tj = 25"C, INotes 4, 5)
50
Ti~ 70·C
Input Resistance
Tj = 2S·C
AVOL
Large Signal Voltage Gain
VS= ±lSV, TA = 2S·C
Output Voltage Swing
VCM
Input Common-Mode Voltage
Range
25
100
4
50
10 12
RIN
Vo
50
2
Tj:::; 70"C
50
25
100
4
pA
200
8
50
200
pA
nA
8
10 12
100
50
10 12
=12
±13,5
V
±11
+15
-12
V
25
±12
±13,S
±12
"'3,5
±11
+15
-12
:tt1 .
+15
-12
25
100
V/mV
15
CMRR
Common-Mode RejectLon Ratio
RS$10kn
80
100
80
100
70
100
PSRR
Supply Voltage Rejection Ratio
INote 6)
80
100
80
100
70
100
IS
Supply Current
AC Electrical Characteristics
SYMBOL
PARAMETER
Amplifier to Amplifier Coupling
7,2
11
n
V/mV
25
VS=±lSV,RL= 10kn
7,2
nA
100
VO=±10V,RL=2kn
Over Temperature
Vs = ±lSV
100
4
11
7,2
V
dS
dB
11
mA
(Note 4)
CONOITIONS
LF347A
MIN
TA = 25"C,
f = 1 Hz-20 kHz
TYP
120
LF347
LF347B
MAX
MIN
TYP
120
MAX
MIN
TYP
120
MAX
UNITS
dB
(Input Referred)
SR
Slew Rate
VS=±lSV,TA=25°C
13
13
13
Vips
GBW
Gain-Bandwidth Product
VS=±15V, TA=2SoC
4
4
4
MHz
en
Equivalent Input Noise Voltage
TA = 2S"C, RS = lOOn,
f=1000Hz
16
16
16
nV/yHz
in
Equivalent Input Noise Current
Tj ~ 25"C, f· 1000 Hz
0.01
0,01
0,01
pA/yHz
Note 1: For operating at elevated temperature, the device must be derated based on a thermal resistance of 1250 e/W junction to ambient or
95°CIW junction to case.
Nota 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: Po max rating cannot be exceeded.
Note 4: These specifications apply for VS = ±15V and O· C ~ T A ~ +70° C. VOS. I B and lOS are measured at VCM = O.
Note 5: The input bias currents are junction leakage currents which apprqximately double for every Hfc increase in the junction temperature, Tj.
Due to limited production test time, the input -bias currents measured Bre correlated to junction temperature. In normal operation the junction
temperature'rises above the ambient temperature as a result of internal power dissipation, PO. Tj = T A + 9jA Po where 8jA is the ther~al resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
Note 6: Supply voltage rejection ratio' is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice.
9·25
Typical Performance Characteristics
Input Bias Current
Input Bias Current
Supply Current
It
100
VS" ,15V+-t-+-+--+--I
TA = 25-C -+--1f--+-+-l-f
;;:
.!>
illa:
80
8.8
o ';TA$+10 C
VCM"O
VS= ±15V
;;:
oS
1-+-1-+--+-11-+-+--1
:I
;;
....
ii!
40
1-+-1-+--+-1'-+-+--1
:!!
20
1-+-1-+--+-11-+-+--1
01-..!-.-L-...I-.....L......J...--l..--l.~
-10
-5
O"C::;;TA::;;+10~C
V
15
!!=
~~
..:~
/
10
B~
w",
::>
....
..
" "....
~~
....
V
o
.5
10
15
'20
1/
0
10
15
10
20
Voltage Swing
.I.
z
.."
>
..
R: =2k'
t- TA =25"C
~
30
~w
'""~
'">
20
~
25"C
e>
>
-5
w
;;
~
o~c
10"C
>
'"
o
10
20
I-
~z
..
........
3.5
§
3
o
10
20
30
40
10
~
15
10
20
50
TEMPERATURE I-C)
60
V
0.1
10
RL - OUTPUT LOAD Itn)
10
10
Slew Rate
150
I'~s=
r-1'>
";;:
.......
";;:
20
;
........
~
15
Bode Plot
30
_
RL -2k
CL = 100 pF-
V
20
SUPPLY VOLTAGE I'V)
Gain Bandwidth
'" 4.5
l!
Vs= ±15V
TA = 25"C
25
o
0
0
V;='I~V
40
~
OUTPUT SINK CURRENT ImA)
."
30
30
~
10
40
30
20
Output Voltage Swing
ij
;;
"-
C
O-C
OUTPUT SOURCE CURRENT ImA)
w
'"e>
r
i\ 2
10-C
NEGATIVE SUPPL Y VOLTAGE IV)
~
~ -10
>
!::
,~
40
.
l-
1
1
~
L
Negative Current Limit
w
..
.-. t""-o
/
-15
-0
25
20
0
'"z
~
15
Positive Current Limit
/
~
ij
"
10
/
10
POSITIVE SUPPLY VOLTAGE IV)
~
r'
SUPPLY VOLTAG.E I-V)
15
z
z:
5.6
D"C::;;TA~+10~C
~
:Ow
:0"
/
:0"
o
fi·
,/
Negative 'Common-Mode Input
Voltage Limit
....
l-
/
~!::
~
6.4
20
~
z:!
>
TEMPERATURE I-C)
20
"'~
:ow
i:l
010203040506010
Positive Common-Mode Input
Voltage Limit
~a
,,/
1.2
a:
10
10
.COMMON·MOOE VOLTAGE (VI
:!!
'~"
/'"
~
GAIN
-10
'15V
RL =2k
CL '100 pF
50
pH1slE
-50
~
-100
-30
1\
-150
FREQUENCY IMHz)
9-26
:l! ~
~
100
14
13
m~
12
~
FALLING
~
w
....
'"m
~
10'
Vs= ±15V
RL = 2t
AV'1
100
-20
0.1
15
~
~
-
RISING-
11
o
10
20
30
40
50
TEMPERATURE rC)
60
10
Typical Performance Characteristics
Undistorted Output Voltage
Swing
Distortion vs Frequency
30
0.2
..i
;::
a:
.
(Continued)
VS' 'ISV
TA=25 C
0.115
I
0.15
I I
I
.
~
~VO'20VP'P
0.125
~
0.1
10k
. ~
ti 0.07S
~
...~
..
..~
5
.."e:
AV' IOO
>
O.OSO
AV"OZ'ri
0.02S
0
100
10
vS' , 15V
RL ·2k
TA' 25"C
AV·l
\<11\ OIST
~
a:
I\.
60
>
10
'\.
40
"-
20
'\.
0
10k
lOOk
1
1M
10
100
lk
10k lOOk 1M 10M
FREQUENCY 1Hz!
FREQUENCY IH,)
Equivalent Input Noise
Voltage
120
100
vs' '1SV
RL -Zk
TA."ZSC
~
80
§2?FkVi
60
I
Ii'
:::
I\.
80
Ratio
40
,.,.~
Vs.,,5VTA'25"C
Power Supply' Rejection
a:
;;:
R~ '2~
~
Ratio
.... H-.
I. I
..§
....
~
~ I
...!l!.
z
~
-
Comm~n-Mode Rejection
:!!
;::
.......
..'"
..
::
..~
~
FREQUENCY 1Hz!
;;
m
:!! 100
0
lOOk
lDk
lk
20
Open Loop Frequency Response
120
"-
CMRR' ZO LOG
+ OPEN LQOP
VCM
ZO
I
VOL JAGE jAIN
100
lk
10k
lOOk
1M
;::
a:
a:
~
II:
'"a:"
;
2
0
10
...
..'"
§
:!!
;;:
"
I I
I
~
;; 140
10M
lZ0
~
100
,"
t---
80
60
I"",,SUPPLY
I'-.
-SUPPLY""
ZO
1"'-
0
10
100
FREQUENCY 1Hz! .
."
.
...
'"..
...
~
"
40
~
...
Vs= ,'5V
TA = 25'C
lK
10k
lOOk
1M
40
z
3D
"
~
20
~
10
§i"
10M
50
>
...
r-..
70
60
0
~
10
100
lk
10k
lOOk
FREQUENCY IH,)
FREQUENCY 1Hz!
I
Open Loop Voltage Gain (V!VI
Output Impedance
.....
..
..::
..~
~
~
TA = DoC TO +2SoC
V
lOOK ~
S
EVS"'5V
TA'25C
r- RL = 2k
~
'"C
Inverter Settling Time
100
1M
.......
~
......-:
..'"
...~
e:"
".
I
~Av =100
10
i,.
,
>
~
10K
~V"~ ~
I
1
AV'10
!:;
>
..;r: '/
0.1
0.01
S
10
15
SUPPL YVOLTAGE "V)
20
100
lk
10k
...
....~"
.....
.."~
:l:
z
TA' 70"C
lOOk
FREQUENCY 1Hz!
10
1M
10M
10mV
S
If
'I
VS' ,'5V
TA·25°C
lmV
0
lmV
10mV
-5
I
I
-10
0.1
~\
\\
1
10
SETTLING TIME c",)
,
9-27
Pulse Response
Small Signal Inverting
Small Signal Non-Inverting
TIME (O.2Ils/DlV)
TIME (O.2Ils/DIV)
Large Signal Inverting
Large Signal Non-I nverting
sCi
~
'"z
i...
, IU
'"
'"~
~
....
Q
Q
>
>
I-
I-
::>
::>
~
~
::>
::>
C>
Q
TIME (2/lS/DIV)
Current Limit (RL = 100m
'"z
ii
'"~
....
IU
Q
>
I-
::>
~
Q
TIME (5Ils/DIV) ,
Application Hints
The LF347 is an op amp with an internally trimmed
input offset voltage andJFETinputdevices(BI-FET II™).
These JFETs have large reverse breakdown voltages from
gate to source and drain eliminating the need for clamps
across the inputs. Therefore, large differential input
voltages can easily be accommodated without a large
increase in input current. The maximum differential
input voltage is independent of the supply voltages.
However, neither of the input voltages should be
allowed to' exceed the negative supply as this will cause
large currents to flow which can result in a destroyed
unit.
Exceeding the negative common·mode limit on either
input will cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state. Exceeding the negative common·mode'
limit on both inputs will force the amplifier output to a
9·28
Application Hints
(Continued)
high state. In neither case does a latch occur since
raising the input back within the common·mode range
again puts the input stage and thus the amplifier in a
normal operating mode.
backwards in a socket as an unlimited current surge
through the resulting forward diode within the IC could
cause fusing of the internal conductors and result in a
destroyed unit.
Exceeding the positive common·mode limit on a single
input will not change the phase of the output; however,
if both inputs exceed the limit, the output of the amplifier will be forced to a high state.
Because these aniplifiers :are JFET rather than MOSFET
input op amps they do not require· .special handling.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the
output to an input should be placed with the body close
to the input to minimize "pick-up" and maximize the
frequency of the feedback pole by minimizing the
capacitance from the input to ground.
The amplifiers will operate with a common-mode input
voltage equal to the positive supply; however, the gain
bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings
to within 3V of the negative supply, an increase in input
offset voltage may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on ±4V power'
supplies. Supply voltages less than these may result in
lower gain bandwidth and slew rate.
The LF347 will drive a 2 kU load resistance to ±10V
over the full temperature range of O°C to +70°C. If the
amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on
the negative voltage swing and finally reach an active
current limit on both positive and negative swings.
Precautions should be taken to ensure that the power,
supply for the integrated circuit never becomes reversed
in polarity or that the unit is not inadvertently installed
A feedback pole is created when the feedback around
any amplifier 'is resistive. The parallel resistance and
capacitance from the input of the device '(usually the
inverting input) to AC ground set the frequency of the
pole. In many instances the frequency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and consequently' ther~ is negligible
,effect on stability margin. However, if the feedback
pole is less than approximately 6 times the expected
j dB frequency a lead capacitor should be placed from
the output to the input of the op amp. The value of the
added capacitor should be such that the RC time constant of this capacitor and the ,resistance it parallels
is greater than or equal to the original feedback pole
time constant.
Detailed Schematic
Vcco-----------~-.~------------~._--_t~----_t~--------~~------__,
R5
22
",---oVo
R6
30
D3
-VEEo---~----~----~--------~--~~--~--~~--~--~~------~~--~
9-29
Typical Applications
Digitally Selectable Precision Attenuator
Vo
V,.
v.
All resistors 1% tolerance
-v.
A1
A2
A3
0
"0
0
0
0
0
0
1
0
0
1
_'_ :::n:::
Vo
F
ATTENUATION
0
-1 dB
-2 dB
-3 dB
-4 dB
-5 dB
-6 dB
-7 dB
0'
1
0
1
0
i
AnENUATION SELECT INPUTS
• 'Accuracy of better than 0.4% ";ith istandard 1% value resistors
• No offset adjustment ne~e ... ry
• Expandable to any nurnber of stages
• Very high input impedance
, Long Time Integrator with Reset, Hold and Starting Threshold Adjustment
,--...,
V,.
VOUT
-15V
"
-<>--,,,
VTH.,._ _ _ _ _
o SET THRESHOLD
liV
o-"""""'-'IoM-WlI-oO
-1&V
,.
tak
10k
VOLTAGE
THRESHOLD
ADJUST
• , VOUT start. from zero and i. equal to the integral.of the input voltage with respect to the threshold voltage:
1
VOUT=RC
•
•
•
f
t'
0 (VIN-VTH)dt
Output starts when,VIN ~ VTH
Switch S1 permits.•topping and holding any output value
Switch S2 resets syste'!' to zero
9·30
Typical Applications
(Continued)
Universal State Variable Filter
tOOk
'Ok
1110k
INPUT
O--'VVV....~
lOWPASS
OUTPUT
-1SV
'Ok
NOTCH
OUTPUT
For circuit shown:
fo = 3 kHz, iNOTCH = 9.5 kHz
Q=3.4
Passband gain:
Highpass - 0.1
Bandpass - 1
Lowpass -1
Notch - 10
•
•
ioxQ:S.200kHz
10V peak sinusoidal output swing without slew limiting to 200 kHz
•
See LM348 data sheet for design equations
9-31
....
it)
('I)
U.
....I
~National
•Amplifiers
~ Semiconductor
LF351 Wide Bandwidth JFET
Input Operational Amplifier
BI.FET II ™ Technology
General Description
tioris where these requirements are critical, the LF356 is
recommended. If maximum supply current is important,
however, the.LF351 is the better choice.
The LF351 is a low cost high speed JFET input opera·
tional amplifier with an internally trimmed input offset
voltage (BI·FET IITM technology). The device requires a
low supply current and yet maintains a large gain band·
. width product and a fast slew rate. In addition, well
matched high voltage JFET input devices provide very
low input bias and offset currents. The LF351 is pin
compatible with the standard LM741 and uses the same
offset voltage adjustment circuitry. This feature allows
designers to immediately upgrade. the overall perfor·
mance of existing LM741 designs.
Features
• Internally trimmed offset voltage
2mV
50pA
• Low input bias current
• Low input noise voltage'
16 nVIYHz
• Low input nois.e current
0.01 pA/vIHz
4 MHz
• Wide gain bandwidth
• High 'slew rate
13 V/IlS
• Low supply current
1.8 mA
• High input impedance
10 12n
• Low total'harmonic distortion AV = 10,
<0.02%
RL = 10k, Va =20 Vp·p, BW =20 Hz-20 kHz
• Low 1If noise corner
50 Hz
• Fast settling time to 0.01%
21ls
The LF351 may be used in applications such as high
speed integrators, fast 01 A conver.tets, sample·and·hole
circuits and many other circuits requiring low input
offset voltage, low input bias current, high input imped·
ance, high slew rate and wide bandwidth: The device
has low noise and offset voltage drift, but for applica· .
Typical Connection
Simplified Schematic
VCCo---------~------------~e_--~--~
Rt
VCC
Ri
Vo
+
-VEEo-----e_------~----------e_------~
Connection Diagrams
(Top Views)
Dual·ln·Line Package
Metal Can Package
NC
Order Number
BALANCE
INPUT
LF351H
LF351AH
LF351BH
See NS Package HOSC
INPUT
NON·INVERTING
INPUT
VNote. Pin 4 connected to case.
9·32
Order Number
LF351N
LF351AN
LF351BN
See NS Package NOSA
r-
"T1
Absolute Maximum Ratings
(,.)
Supply Voltage
Power Dissipation .( Note 1 )
Operating Temperature Range
TjlMAX)
Differential Input Voltage
Input Voltage Range (Note 2),
Output Short Circuit Duration
Storage Temperature Range
Lead 'Temperature (Soldering, 10 seconds)
DC Electrical Characteristics
SYMBOL
VOS
Input Offset Voltage
LF351A
MIN
TYP
RS = 10 k!'!, TA'= 25'C
1
Over Temperature
aVOS/aT
Average TC of Input Offset
Voltage
lOS
Input Offset Current
Input Bias Current
Input Resistance
AVOL
Large Signal Voltage Gain
MIN
2
TYP
3
25
. Tj = 25'C, INates 3, 41
50
50
25
100
50
50
TYP
5
5
50
±13,5
±12
10
10
25
100
50
200
25
100
UNITS
mV
mV
p.vfc
100
pA
4
nA
200
pA
8
nA
1012
1012
100
MAX
13
8
1012
VS=±15V, TA=25'C
MIN
4
4
. Tj = 25'C
MAX
10
2
Tj - 25'C, INotes 3, 41
LF351
"
7
10
RS= 10k!'!
Tj 5 70'C
RIN
LF351B
MAX
4
Tj5 7O'C
18
..10
(Note 3)
CONDITIONS
PARAMETER
(J1
±18V
500mW
O°C to +70°C
115°C
±30V
±15V
Continuous
-65°Cto +150°C
300°C
!'!
100
V/mV
Vo = ±10V, RL = 2 k!'!
Over Temperature
Vo
Output Voltage Swing
VCM
Input Common-Mode Voltage
Vs
Range
CMRR
Vs = ±15V, RL - 10 k!'!
C9mmon-Mode Rejection Ratio
PSRR
Supply Voltage Rejection Ratio
IS
Supplv Current
=±15V
PARAMETER
+15
±ll
-12
100,
80
.lNate 51
15
25
±11
RS~ 10k!'!
80
100
1.8
AC Electrical Characteristics
SYMBOL
25
±12
+15
±ll
-12
80
100
80
100
2.8
±12
±13.5
1.8
V/mV
±13.5
V
+15
V
-12
70
100
70
. 100
2.8
1.8
V
dB
dB
3.4
mA
(Note 3)
CONOITIONS
LF351A
MIN
TYP
LF3518
MAX
MIN
TYP
LF351
MAX
MIN
TYP
MAX
UNITS
SR
Slew Rate
VS=±15V,TA=25 C
13
13
13
Vlp.s
GBW
Gain Bandwidth Product
VS=±15V, TA=25'C
4
4
4
MHz
en
Equivalent Input Noise V~ltage
TA = 25'C, RS = lOon,
16
16
16
nV/VHz
0.01
0.01
0.Q1
pA/VHz
!=1000Hz
in
Equivalent Input Noise Current
Tj = 25'C, !
= 1000 Hz
Nota 1: For operating at elevated temperature, the device must be derated based on a thermal resistance of lSj,A is the thermal resistance from junction to ambient: Use of a heat sink is recommended if input bias current is to be kept to a minimum.
.
Note 5: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice.
9·33
Typical Performance Characteristics
Input Bias Current
Input Bias Current
SupplV Current
1k
l
..e.
il
:/
100 I-Vs- ,15V
I-T -25"C
......,.
l!
20
. . ...v
......
80
40
o
10
-10
10
-5
10
0"C';;TA';;+7D"C
....
,...,.".!!!
Be
IS
IS
..:.1
.....
,. ..
"' ..
10
,~
'\ zr c
10
....
/
l<
/
l:l
z
:>
E
~
POSITIVE SUPPLY VOLTAGE IVI
DoC
7D"C
0
ZO·
15
25
ZO
r- ...... ~
.:>
/
s~
~~
/
.
~..
..~
1/
·10
16
Positive Current Limit
16
'"
Ii!
/
z!!!
/
o
10
SUPPLY VOLTAGE l.vl
a
• t:
/
i!:>
o
&0 '70
D"C::;TA::;+70°C
i!
~~
/
10
o
60
Negative Common·Mode Input
Voltage Limit.
.
~
V
....
i
40
• 20
20
~~
3D
TEMPERATURE eCI
,"ositive Common-Mode Input
Voltage Limit.
.1:
.....
ZO
10""'"
V
t.2
o
COMMON·MOOE VOLTAGE IVI
~
D"::; TA ::;+70"C
i=VCM" 0
I=vs' "6V
80
;;
....
.i!
Z.Z
° OUTPUT10 SOURCEZOCURRENT30 ImAI
NEGATIVE SUPPLY VOLTAGE IVI
40
I
aco -16
~
..~
..
.~..
V~ltage Swing
Negative Current Limit
Output Voltage SWing
'"i!:..
~
-10
l:l
z
..~
......
..'"'"
:>
IrC
70"C
10
ZO
Gain Bandwidth
:c
:;
~
~.
z
co
.'"
>-
~
3.6
3
o
16
0.1
ZO
.l.
ZO
10
10
20
~
:---...
r--...
30
40
50
TEMPERATURE lOCI
-
,60
10
RL - OUTPUT LOAD 1~1lI
,...
Slew Rate
ISO
r-.
VS·,I6V
RL -Zk
16
100
CL::w100pF
~
70
r--
z
;;:
l\
co
-10
~
60
;!l
-50
a ~
III
;: is
~.
ii
"'"
;;:
3D
VS·,16V _
RL '2k
CL·IOOpF-
r--...
10
Bode Plot
.• 1
4.5
/
SUPPLY VOLTAGE I±VI
OUTPUT SINK CURRENT (mAl
l!
10
o
~~~~~~~~~~
o
40
30
i
zo
I!:
o
o
,/
co
c . 16
!:;
25°C
-0
VS. :t15V
TA"Z5°C
Z6
co
:>
~
30
14
Vs' 'I5V
RL -Zk
AV·I·
i!:
.
l1! 01
13
FALLING
..
i--
RisiNG
IZ
-100
-ZO
-160.
-3D
10
0.1
FREQUENCY IMHzl
9·34
100
"
0, 10
ZO
3D
40
50
TEMPERATURE ( CI
60
70
Typical Performance Characteristics
(Continued)
Undistorted Output Voltage
Distortion vs Frequency
30
0.2
vS' !15V
TA' 25"C
' , I I
0.115
..
0.15
gj
'""
~
~VQ;20~PP
~O.125
>=
Open Loop Frequency Response
Swing
0.1
~
t; 0.015
C
0.050
\=..
Q
"'
15
~"'
g
:;
15
8"
120
100
80
60
I\.
0
1
10
100
lk
10k lOOk 1M 10M
FREQUENCY 1Hz)
FREQUENCY 1Hz)
Equivalent Input Noise
Voltage
H-..
VS"'15V
RL =2k
TA '25"C
Ilh
r-~VQ
VC~
i
'"
2k
~
'
~
I
I
~
"+ OPEN LOOP
I I
VCM
VOLTAGE GAIN
I.
10
100
1
lk
I
10k
lOOk
1M
iii
'">=
Q
::!
15
140
120
~"'
80
;;:
40
ffi
20
::it
~
10M
"
100
-.....
'"
60
..
w
...'"
~
'"
1"-.
10k
lOOk
~
i'
1M
40
~
c
3D
20
t-
..'"~
10M
:;
:;l
10
0
10
Open Loop Voltage Gain (V/V)
0
E
w
"
..'"
-:I
TA = 7o"C
I
~AV"00
10
c
~
l!
!;
Q
~
Q
~
~
~
Q
:IE
Q
/
:::
~V""" ~
I
1
Avo 10
/I
10mV
S
i
w
'"'"~
..
15
SUPPLY VOLTAGE (>VI
20
"
c
100
lk
10k
lOOk
FREQUENCY 1Hz)
9-35
1M
10M
Vs= :!:15V
TA·2S'C
lmV
lmV
lDmV
-S
I
!;
0.01
10
If
0
I!:
10K
lOOk
'"
Q
£
0.1
10
1:
TA' 2S"C
TA O"C TO +25"C
10k
I nverter Settling Time
E
~VS"'SV
r- RL -2k
lk
FREQUENCY 1Hz)
Output Impedance
100
S
100
.FREQUENCY 1Hz)
1M
~V
60
w
."'SUPPLY
lK
70
oS
'"~ so
~
0
100
~
Q
-SUPPLY'\.
10
,.
~'5V
Vs'
TA',2S"C
FREQUENCY 1Hz)
~ lOOK
*
I\.
20
Ratio
0
.."
.
I\.
Power Supply Rejection
20
w
\.
Ratio
CMRR = 20 LOG
'"~
'\.
Common-Mode Rejection
40
~
1M
lOOk
RL '2k
VS'±15VTA o 25"C
"-
40
Q
lOOk
10k
lk
60
~
0
10
80
~
10
~
0
w
"'"~
Q
"
f--
= 100
'"'"~
.
"
AVo ,.oZrt
0.Ol5
20
'"~
AV o loo
~
VS·tI5V
RL' 2k
TA' 25"C
AVo 1
'\
120
1
-10
0.1
\.\
,\\
1
SETTLING TIME ",,)
10
.....
LI)
('I)
Pulse Response
LL
...J
Small Signal Non-Inverting
Small Signal Inverting
:;;
:;;
~e
~e
e
e'"
w
Iiw
CI
'"
!:i
CI
co
...z
Ii
...
...'"....
...z
...
>
>
....
::>
....a..
::>
....
::>
1=
::>
CI
CI
TIME (O.2I'SiDIV)
TIME (O.2I's/DIV)
Large Signal Jnverting
Large Signal Non-J nverting
:;;
:;;
~e
>
eo
Iiw
iiw
CI
CI
Ci
...z
...z
...
'".......
>
...........
...
.......'"
>
....
::>
a..
....
::>
::>
::>
CI
CI
TIME (2I'SiDIV)
TIME (2I'SiDIV)
Current Limit (RL
=100m
:;;
~...
z
Iiw
...
~CI
>
....
~CI
::>
TIME (51's/DIV)
Application Hints
The LF351 is an op amp with an internally trimmed
input offset voltage and JFETinputdevices (BI-FET II™).
These JFET$ have large reverse breakdown voltages from
gate to source and drain eliminating the need for clamps
across the inputs. Therefore, large differential input
voltages can easily be accommodated without a large
increase in input current. The maximum differential
input voltage is independent of the supply voltages.
However, neither of the input voltages should be
allowed to exceed the negative supply as this will cause
large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either
input will cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state. Exceeding the negative common-mode
limit on both inputs will force the amplifier output to a
9·36
Application Hints
r(Continued)
high state. In neither case does a latch occur since
raising the input back within the common·mode range
again puts the 'input stage and thus the amplifier in a
normal operating mode.
backwards in a socket as an unlimited current surge
through the resulting forward diode within the IC could
cause fusing of the internal conductors and result in a
destroyed unit.
Exceeding the positive common·mode limit on a single
input will not change the phase of the output; however,
if both inputs exceed the limit, the output of the ampli·
fier will be forced to a high state.
Because these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.
As with most amplifiers, care 'should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the
output to an input should be placed with the body close
to the input to minimize "pick·up" and maximize the
frequency of the feedback pole by minimizing the
capacitance from the input to ground.
The amplifier will operate with a common·mode input
voltage equal to the positive supply; however, the gain
bandwidth and slew rate may be decreased in this condi·
tion. When the negative common·mode voltage swings
to within 3V of the negative supply, an increase in input
offset voltage may occur.
A feedback pole is created when the feedback around
any amplifier is resistive. The parallel resistance and
capacitance 'from the input of the device (usually the
inverting input) to AC ground set the frequency of the
pole. In many instances the frequency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and consequently there is negligible
effect on stability margin. However, if the feedback
pole is less than approximately 6 times the expected
3 dB frequency a lead capacitor should be placed from
the output to the input of the op amp. The value of the
allded capacitor should be such that the RC time can·
stant of this capacitor and the resistance it parallels
is greater than or equal to the original feedback pole
time constant.
The LF351 is biased by a zener reference which allows
normal circuit operation on ±4V power supplies. Supply
voltages less than these may result in lower gain band·
width and slew rate.
The LF351 will drive a 2 kn load resistance to ±10V
over the full temperature range of aOc to +70°C. If the
amplifier is forced'to drive heavier load currerits, how·
ever, an increase in input offset voltage may occur on
the negative, voltage swing and finally reach an active
current limit on both positive and negative swings.
Precautions should be taken to ensure that the power
supply for the integrated circuit never becomes reversed
in polarity or that the unit is not inadvertently installed
Detailed Schematic
VCCo-------------~~--------------~----~------~----------------------~
Vas
ADJUST
03
...
-VEEo---~----~----t_--------~--~----~--~--~t_--~--------~---9·37
'TI
W
01
~
~
lI)
M
U.
Typical Applications
..J
Supply Current Indicator/Limiter
Hi-ZIN Inverting Amplifier
CZ
RS
VSUPPl y
o-~"'_"",NIt-.---+----. ~~~;!~~~~~~E\YTION
RZ
IS
'+
Vo
lN914
Rl
•
VOUT switches high when RSIS
V-
> Vo
Parasitic input capacitance Cl '" (3 pF for LF351
plus any addi,tional layout capacitance) interacts
with feedback elements and creates undesirable
high frequency pole. To compensate, add C2 such
that: R2C2", R1C1.
Ultra-Low (or High) Duty Cycle Pulse Generator
lN914
Long Time Integrator
v,
Rl
RESET
IN914
RZ
..-.t---''V\I'v--....-o OUTPUT
---,
~
INTEGRATE
V-
c*
c*
v,
-::r
1M
v,
1M
1
VOUT"
'2
RC ./"
'I
1M
V-
4.8 -2Vs
•
tOUTPUT HIGH ~ RIC Qn
V-
4.8 -Vs
•
tOUTPUT LOW
where Vs
~ R2C Qn
= V+ +
* Low teakage capacitor
2Vs -7.8
•
Vs -7.8
IV-'
*Iow leaka'ge capacitor
9·38
50k pot used for less sensitive VOS adjust
Y,N OIT
~National
Amplifiers
~ Semiconductor
LF353, LF354 Wide Bandwidth Dual
JFET Input Operational. Amplifiers
r-
BI-FET II ™ Technology
These devices are low cost, high speed, dual JFET input
operational amplifiers with an internally trimmed input
offset voltage (BI-FET IITM technology)_ They require
low supply current yet maintain a large gain bandwidth
product and fast slew rate_ In addition, well matched
high voltage JFET input devices provide very low input
bias and offset currents_ The LF353 is pin compatible
with the standard LM1558 allowing designers to immediately' upgrade the overall performance of existing
LM15!i8 and LM358 designs_ The LF354 is pin compatible with the LM747 and is identical in performance
to the LF353 with the additional feature of offset
nulling capability.
impedance, high slew rate and wide bandwidth. The
devices also exhibit low noise and offset voltage drift.
Features'
2mV
• Internally trimmed offset volta.ge
50pA
• Low input bias.current
16 nV/yHz .
• Low input noise voltage
0.01 pA/yHz
• Low input noise current
4MHz
• Wide gain bandwidth
13 V/p.s
• High slew rate
3.6mA
• Low supply current
10 12n
• High input impedance
• Low total harmonic distortion AV = 10,
<0.02%
RL = 10k, Vo = 20 VP-Il' B.W = 20 Hz-20 kHz
• Low 1If noise corner
50 Hz
• Fast settling time to 0.01%
2 p.s
These amplifiers may be used in applications such as
high speed integrators, fast D/A converters, sample and
hold circuits and many other circuits requiring low
input offset voltage, low input bias current, high input
Typical Connection
Connection Diagrams
LF353H Metal Can Package (Top View)
v'
6
INVERTING
INPUT B
V-
Order Number L F353AH or L F353BH '
See NS Package HOSC
LF353N Dual-In-Line Package (Top View)
OUTPUT A
...."'-r--
~
INVERTING INPUT A
Simplified Schematic
NON.INVERTING
3
0----",------"",--""
v-4--.J
OUTPUT B
INVERTING INPUT B
INPUT A
1/2 Dual
5
NON.INVERTING
INPUT 8
Order Number LF353AN, LF353BN or LF353N
See NS Package NOSA
LF354N Dual-In-Line Package (Top View)
+
INVERTING INPUT A
NON·INVERTING INPUT A
OFFSET NULL ~
yOFFSET NULL B
INTERNALLY
TRIMMED
-VEE
,.
(,.)
CJ1
General Description
vee
."
NDN-INVERTING INPUT B
0--"'---"'----"'--"""
INVERTING INPUTB.
14
OFFEST NULL A
V+A·
OUTPUT A
Ne
OUTPUTB
v+s*
OFFSET NULL B
Order Number LF354AN, LF354BN or LF354N
Se. NS Packag. N14A
*V+A and V+B are internallv connected
9-39
~
it')
M
LI.
...I
(f)
-Absolute Maximum Ratings
"
±18V
Supply Voltage
500mW
Power Dissipation (Note 1 )
it')
Tj(MA~)
(f)
Differential Input Voltage
~
Input Voltage Range (Note 2)
,
O°C to +70°C
Operating Temperature Range
115°C
±30V
±15V
Continuous
Output Short Circuit Duration (Note 3)
-65°C to +1.50°C
Storage Temperature Range
300°C
Lead Temperature (Soldering; 10 seconds)
DC, Electrical Characteristics
SVMBOL
PARAMETER
(Not~ 4)
LF353A,
LF354A
CONDITIONS
MIN
.-
TVP
LF353B,
LF354B
MAX
VOS
Input Offset Voltage
RS'I~kn, TA=25°C
Over Temperature
1
IlVOS/IlT
Average TC of Input ,Offset
Voltage
RS= 10kn
10
lOS
Input Offset Current
Tj = 25°C, (Notes 4, 5),
Tj~ 70°C
25
50
2
IB
Input Bias
Tj = 25°C, (Notes~, 5)
, Tj~70°C
50
100
4
RIN
Input Resistance
Tj = 25°C
AVOL
Large Signal Voltage Gain
VS=±15V,TA=25°C
Vo = ±10V, RL = 2 kn
Vo
Output Voltage Swing
VCM
Input COmmon·Mode Voltage
Cu~rent
,2
4
Vs = ±15V
MAX
3
5
7
MIN
mV
mV
p.vtc
10
100
4
25
100
4
pA
nA
60
200
8
50
200
8
pA
nA
1012
1012
n
100
25
±12
±13.5
±12
±13,5
V
±11
+15
-·12
±11
+15
-12
V
V
50
±12
±13,5
±11
+15
-12
25
100
V/mV
Common-Mode Rejection Ratio
RS:'> 10 kn
80
100
80
100
70
100
PSRR
Su.~plv Voltage Rej:ction Ratio
(No!e 6)
80
100
80
100
70
100
IS
Supply Current
5.6
V/mV
15
CMRR
3,6
UNITS
'25
-
100
25
Vs = ±15V, RL = 10 kn
TVP
10
1012
50
Over Temperature
Range
MIN
LF353.
LF354
,TVP
MAX
10
5
13
3.6
5,6
3.6
d8
dB
6,5
.mA
\
AC Electrical Characteristics
SVMBOL
(Note 4)
PARAMETER
CONDITIONS
~mplifier to Amplifier Coupling
TA = 25°C, f= 1 Hz20 kHz (Input Referredl
LF353A, LF354A
MIN
TVP
-120
MAX
LF363B, LF364B
MIN
TVP
-120
MAX
LF353, LF364
MIN
TVP
-120
MAX
UNITS
d8
SR
Slew Rate
VS=±15V,TA=25°C
13
13
13
V/p.s
GBW
Gain-Bandwidth Product
VS=±15V, TA=25°C
4
4
4
MHz
en
Equivalent Input Noise Voltage
TA = 25°C, RS = lOOn,
f=loo0Hz
16
16
16
nV/VHz
in
'Equivalen~ Input Noise Current
Tj = 25°C, f = 1000 Hz
0,01
0.01
0,01
pAlVHz
Note 1: For operating at elevated temperature, the device must be derated based on a thermal resistance of 16Cfc/W junction to ambient for
,the N package, and 150°C/W junction to ambient for the H package.
.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power suppiy voltaga.
N'!ta 3: The power dissipation limit, however, cannot be exceeded.
Note 4: These specifications apply f~r Vs ±15V and O·C::;: TA::;: +70°C. VOS,'IS and lOS are measured atVCM = O.
Note 5: The input bias currents are junction leakage currents which approximetely doubla for every 1Cfc increase in, the junction temperature,
Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction
temperature' rises above the ambient temperature as Ii result of internal power dissipation, PD. Tj = TA + EljA Po where EljA is the thermal resis·
tanee from junction to ,an:'bient. Use of a heat sink is recommended if input bias current is to be kept to a minImum.
Note 6: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with com·
man practice.
=
9-40
Typical Performance Characteristics
Input Bias Current
~
>-
60
;;
40
~
'"
~c~=oi
' - r -i -
'"
"'"
......
./V
o
I-- 10
-5
10
Positive Common-Mode Input
Voltage limit
"
~
o C~TA:::;;+10 C
w>
::;;-
z!
"'~
::;;w
::;;'"
10
8~
V
w'"
»
;::
~
'"
~~
"'~
::;;w
15
.
'"z
~
w
o
~
-
~
-5
w
~
Z
70'C
Z
.......
>
.......
3.5
-
10
ZO
30
40
50
TEMPERATURE ("CI
60
10'
ZO
10
40
30
~
'"z
~
Output Voltage Swing
30
/-
VS' ±15V
TA"25"C
25
20
w
15
!:;
Q
>
~
10
/
g
o
10
15
0.1
ZO
10
RL - OUTPUT LQAO (kill
30
. Slew Rate
20
.....
~
150
I'~s= '15V
.....
lW~E
Z
,~
GAIN
-10
15
VS' ,15V
RL 'Zk
Av=1
100
RL =Zk
CL =100pF
f-
50
:Jl
~
~
-50
~
111
]
14
2:
.'",
~
13
~
12
FALLING
-
RlsiNG-
-100
-ZO
-150
-30
3
o
o
OUTPUT SOURCE'CURRENT (mAl
I-+--+-l-f--+--+,A----j
m
;;:
o
,20
..
10
f'..
Z
t::
§
~
15
Bode Plot
I'-...
::!
..
w
10
5
1. .
I
2t'C
o'c
10"C
SUPPLY VOLTAGE ('VI
.I
VS·,15V _
RL' Zk
CL = 100pF-
4.5
i"i
'">
..'"
Gain Bandwidth
~
\~
;::
o
40
30
10
1;
'"
20
25
20
~
5
....
-0
3E
Q
~>
/
OUTPUT SINK CURRENT (mAl
:;;'"
..
"~
DC
10
~
w
~
>
25' C
>
- r.....
15
'""
'"
..
'">
15
Positive Current Limit
z:
Voltage Swing
30
5
10
SUPPLY VOLTAGE (,VI
NEGATIVE SUPPLY VOLTAGE (VI
~
-10
o
/
20
(J1
~
2.4
/
Negative Current Limit
-15
Z.O
70
'/
10
POSITIVE SUPPLY VOLTAGE IVI
2:
60
/
>'"
->
>-
15
~
/" '"
~
w~
10
3.2
w
u
~~
"'"'::;;'"....
o
50
D"C~TA:::+1D'C
~
Z
o
40
Negative Common-Mode Input
Voltage limit
>-
/
/
30
ii!
/
/
QQ>-
ZO
20
15
~
TEMPERATURE ( CI
COMMON·MOOE VOLTAGE (VI
>-
J.6
L-~~_~-L_L-J-~
o
10
."
W
,,/
ffi
'"~
~
"
r-
.§
100
z
20
0"S;TAS;+10"C
;;:
;;
20
-10
--...:
r--
....
z
u
Supply Current
4.4
Vs' '15V
%'
-
80
~
~
:1
-
-
100 'f-VS' '15V
TA' 25 C
Input Bias Current
lk
10
0.1
FREQUENCY (MH.I
9-41
100
11
o
10
20
30
40
50
TEMPERATURE I CI
&0
70
Typical Performance Characteristics
(Continued)
\
".
Undistorted Output Voltage
Distortion 'vs Frequency
Swing
....
.
Vs' ,ISV
0.175
I I
1
2:
~VO'ZOVP'P
~
~L L
i..
TA~2S"C
I
O.IS'
;O.IZS
;::
or:
Open Loop F requenciy, Response
30
0.2
I,
..
..
':'
>
is
0
10
10k
Ik
120
~
c
100
ill
z
e
.
......
OJ
or:
8'0
,
60
~
~
~
z
8
40
I_ I
~
VCM
Zk
~
I
ZO
I
VOLt GE GAIN
.
0
10
I
I
100 ,Ik
..
..""
·5
m
I
1M
or:
100
~
r....:.
60
40
a:
20
~
10M
80
II:
iil
I.I
10k 'IOOk
120
'" "'......
IK
100
~ tOOK
~
~
~
10k
is
"f
","--
~
.......
....-
lOOk
1M
~
">:;
10M
'"
~
10
"'"
TA"IO"C
":;:
~
~
.."
9
i
3D
ZO
10
0
10
y
~V'I§ ~
~
5
lOOk
FREOUENCY 1Hz)
"
9-42
lOOk
1M
10M
~
vS' ilSV
TA =25°C
ImV
0
ImV
>
-5
.""
-10
10mV
I
~\
, II \\
~
10k
10k
III
1111
I-
Ik
Ik
10mV
~
~
100
ZO
SUPPLY VOLTAGE I'V)
..
.
i...
....
~
AV'IO
0.1
100
10
i!:
0.01
10K
15
50
40
Inverter SettUng Time
/
~AV'IOO
I
I-
10
60
:il
~
I
10k lOOk 1M 10M
FREQUENCY 1Hz)
VS' '15V
TA' Z5 C
TA' O"C TO +Z5'C
Ik
10
Output Impedance
~
5
100
I-
100
..:::::: ;::;.....
10
Voltage
FREQUENCY 1Hz)
RL -2k
~
.
..~
.:
I,""SUPPLY
-SUPPLY'\.
10
Open Loop Voltage Gain (V/V)
.."..
..
~>>
2 ,0
1M
az
\.
I
Equivalent'lnput Noise
vS' ;15V
TA "IZ5'C
"-
FRE.oUENCY 1Hz)
;;
\.
FREQUENCY 1Hz)
140
'"
;::
;;;or:
"-
..!.! + OPEN lOOP
VCM
\.
40
1M
lOOk
Power Supply Rejection
Ratio
RL -Zk
TA·25'C
i I""
CMRR·20 LOG
\.
60
FREQUENCY 1Hz)
Vs = ·,SV
FrvoI
or:
t\..
80
0
10k
lOOk
Ratio
r-+-.J.
Ri· Zkl
Vs' ,ISVTA'2S"C
z
Common·Mode Rejection
:!!
~
9
FREQUENCY 1Hz)
..
.."."
..""
..
..:e. zo
0
ioo'
10
r- "-
:!! 100
~
"~
AV'I07':~
O.02S
IZO
>
I-
0.050
..
~
~
AV" 100
':'
,zo
~
'10k
0.1
In 0.015
Vs' , 16V
RL' Zk
TA" Z6"C
AV-l
\<1% OIST
0.1
I
SETTLING TIME c".) ,
10
Pulse Response
Small Signal Inverting
Small
S
S
co
=-coe
~e
Sign~1
Non-Inverting
Ci
!!l
!!l
'"z
'"z
...~
...~
;:....'"
'"c:c
co
I....
co
l-
I-'
>
>
...
::>
.~
l-
I-
::>
::>
co
co
TIME (O.2/ls/DIV)
TIME (O.2/ls/DIV)
Large Signal Inverting
Large Signal Non-I nverting
S
S
Ci
Ci
='"z
=-!!l
'"z
!!l
....~
~
...
'";:....
'";:....
co
co
>
>
l-
I-
l-
I::>
...
...
::>
::>
::>
co
'co
TIME(2/l~/DIV)
TIME (2/ls/DIV)
Current ~imit (RL = lOOn!
TIME (5/ls/DIV)
Application Hints
These devices are op amps with an internally trimmed
input offset voltage and JFET input devices.(BI-FET II).
These JFETs have large reverse breakdown voltages-from
gate to source and drain eliminating the need for clamps
across the inputs. Therefore, large differential input
voltages can easily be accommodated without a large
increase in input' current. The maximum differential
input voltage is independent of the supply voltages.
However, neither of the input voltages should be
allowed to exceed the negative supply as this will cause
large currents to flow which can result in a destroyed
unit.
.
Exceeding' the negative common-mode limit on either
input will cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state. Exceeding the negative common-mode
limit on both inputs will force the amplifier output to a
9·43
Application Hints
(Continued)
high state. In neither case does a latch occur since
raising the input back within the common·mode range
again puts the input stage and thus the amplifier in a
normal openiting mode.
'
backwards in a socket as an unlimited current surge
through the resulting forward diode' within the IC could
cause, .fusing of "the internal conductors ,and result in a
destroYed'unit. '
Exceedi~g ~he positive comm,on·mode limit pn' a single
input'will not'chang~ the p\lase of,the output; !1owever.
if both inputs' exce'ed ,the lim,it; the output of the ampli·
fier Will bef?rced toa hi9h'st3te,.. "
"
,
Because ~hese amplifiers are JFET rath~r tha~'MOSFET
input
op amps', ,they'
handling.
,. .
.. " do not
. : require special
.
~
As vvith ·most amplifiers. 'care should be taken with lead
dress., component placement and supply' decoupling in
order'to ensure stabilitY. For example. ,resist6rs from the
output to an input sh,olild be placed with the body close
to the input to minimize ,"pick~up" 'and mal\imi~e the
frequency of the, ,'feedback' p~le by minimizing the
'
capacita'nce from the i~p';'t to ground.
The amplifiers will operate'with"~ common·mode input
voltage equal tli ihe'P9Sitive s~iiply; however. the, gain
bandw'idth"an'd,slew rate, maY be decreased in this condi·
tion. Wh'en the, negative, common·mode voltage swings
to wi,thin 3V of the negative supply,'an increase in input
offset voltage may occur.
A feedback pole is created when the feedback around
any amplifier is resistive. The parallel, resistance and
capacitance from the input of the device' ('usually the
inverting'input) to AC groun(l set the freql;lency of the
pole. In many ir]sta'n~es the' frequency of this p.ole is
much greater than the expected 3 dB frequency of the
closed, lo~p gain and consequently there is negligible
effect on stability' ~argin. 'However. :if the 'feedback
pol~ is less than approxim~tely 6 'times the':expected
3 dB frequeri~y, a leacl"capacitor'should be pl~ced from
the output"'io the,inpll,i:',of,the op am'p, The v,alue of the
added capacitor should ,be such that ,the,'j:IC time con·
sta~t ,of this capacito~ and the resistance 'it' parallels
is greater than 'or equal"to ,th,e o[igil']al, feedback pole
time constant.
'.'
,
Each amplifier is individually biased by a zener reference
which allows normal circuit operation, on ±4V power
supplies. Supply voltages less than these "may result in
lower ~,ai':l ba'1dwi,dth and ,slew rate"
'
The amplifiers'wif'l.drille a 2'kn load tesista'nce'to ±10V
over th'e full 'temperature range of O°C, to +70°C. If the'
amplifier 'is'f~rced' to 'drive heavier:IOqd currents. how·
ever, an increase in:-input ,offset voltage may occur on
the negative :volta!ie 'swing and finally reach an active
currerit: 'Iii-(:lit
b~th 'positive an'd I)egative svvings.
on'
' d '
.
,",
Precautio;;'sshould':'be take~ to ertsuril that the power
supplv'~o't' the integrated circuit' never becomes reversed
in po[arhy, 'o'~ ,that theunit not inadvertently installed
is
\
Detailed Schematic
vcco-------------~--------------~~--~------~--------------------_,
,
..
D3
-VEEo---__-----4~--__--------~~--__----e_--__----~--~~--------__----~
*LF354 only
9·44
Typical Applications
.-"T1
Three-Band Active Tone Control
(,.)
BOOST - CUT
(J1
~
BASS
11k
3.6k
1.8k
>-IIt--oOUT
11111111
(NOTE 2)
+20
+15
(NOTE 4)
1\
;;:
'"
'"
WillI I
I1iJbTJA,U]
+10
~
111111
ffilll7flllllll
+5
~
V
-5
f'\
-10
-15
"
lJ
-20
WJJ
IIIII
UU!
~111~)1
I r~nIE 5/.
10
100
lk
I nTIl
10k
lOOk
FREUUENCY (Hz)
Note 1: All controls flat.
Note 2: Bass and treble boost, mid flat.
Note 3: Bass-·and_treble cut, mid flat.
Note 4: Mid boost, bass and treble flat.
Note 5: Mid cut, bass and treble flat.
•
All potentiometers are linear taper
•
Use the LF347 Quad for stereo applications
9-45
Typical Applications
(Continued)
Improved CMRR Instrumentation Amplifier
Vs
C+I()ojH----f-If-=-!
R4
R5
Vo
HO+-+--+lH
-VS
Vs
Vs'
-'L
-'L
-
-
-
h
h
!
!
-Vs
-VS'
SEPARATE
RS
m
and
*
R4
are separate isolated grounds
Matching of R2's, R4's and RS's control CMRR
With AVT = 1400, resistor matching,= 0.01%: CMRR = 136 dB
•
•
Very high input impedance
Super high CMRR
Fourth Order Low Pass Butterworth Filter
VOUT
03'
m
•
•
•
•
•
•
Corner frequency (fe) ==
j
-15V
i
R1R'2CC1
Passband gain (HO) = (1 + R4/R3) (1 + R4'/R3')
First stage Q = 1.31
Second stage Q = 0.541
Circuit shown uses nearest 5% tolerance resistor values for a filter with a corner frequency of 100 Hz and a passband gain of 100
Offset nulling necessary for accurate DC performance
9·46
Typical Applications
(Continued)
Fourth Order High Pass Butterworth Filter
R1
200k
VIN~
r-
R1'
240k
."
,
W
01
0.001
>"':""+--oVOUT
R3
200k
Corner frequency (fcl
=
j
1 2
R1R2C
•
2rr
2"
•
•
•
Passband gain (HO) = (1 + R4/R3)(1 + R4'/R3')
First stage Q = 1.31
Second stage Q = 0.541
•
Circuit shown uses closest 5% tolerance resistor values for a filter with a corner frequency of 1 kHz and a passband gain of 10
Ohms to Volts Converter
10M
RX
VOUT'" lV
FUll SCALE
1.J5k
'---"'--o-15V
Va
1V
=
x RX
RLi\DDER
Where RLADDER is the resistance from switch 51 pole to pin 10 of the LF354.
9-47
~
<0
II)
M
t:..J
"II)
II)
M
t:
.~National
Amplifiers
~ Semiconductor
LFT155/LFT156, LFT355/LFT356
Low Offset Monolithic JFET Input
Operational Amplifiers .
.
BI-FET Technologv
..J
General Description
cD
II)
These monolithic JFET input operational'. amplifiers
have guaranteed low offset voltage and offset voltage
drift along with high common-mode rejection which
allows their use in applications requiring precision
to 0.01%. In addition, .they have the same low bias and
offset currents, high slew rate, wide bandwidth, extremely
fast settling time, low voltage and current noise and low
llf corner as do the normal LF155/LF156 BI-FET
operational amplifier families.
• Precise analog computer amplifiers and integrators
• Replace op amps in existing systems requiring:
• Offset voltage adjustment
• Drift selection
• Fast settling
• Low noise
• Low bias current
Advantages
Features
•
•
LFT155/LFT156 .
t:
..J
"II)
II)
t:
..J
•
•
•
•
Ultra·low offset-12-bit accuracy without adjust
Rugged JFETs allow blow-out free handling compared
with M05FET input devices
Excellent for low 'noise applications using either high
or low source impedance-very low l/f corner
Offset adjust does not degrade drift or common-mode
rejection as in most monol ithic amplifiers
New output stage allows use of large capacitive loads
(10,000 pF) without stability problems
Internal compe'nsation and large differential input
voltage capability
•
•
•
•
•
•
•
•
~pplications
• Output amplifiers in 10 and 12-bit current mode D/A
)
converters
• Data acquisition front-end amplifiers: (DC coupled·
difference amplifier, buffer)
• Output buffer in 5/H circuits
• Low pass filters with DC gain
• Amplifier for auto-zeroing loops
• Long time integrators
Typical Applications
Low input offset voltage
Low input offset voltage temperature
drift
Low input bias current
Low input offset current
High common-mode rejection ratio
High input impedance
Low input noise current
Large DC voltage gain
0.5 mV max
5I1V(C max
50 pA max
10 pA max
95dB min
1012n,
0.01. pA/y'Hz
106 dB
I-FT156/LFT356
•
•
•
•
Fast slew rate
Wide gain bandwidth
Extremely.fast settling
'Low input noise voltage
10 V/I1S min
4 MHz min
1.5 ps to 0.01%
12 nV/y'Hz
Simplified. Schematic
12-Bit Accurate Buffer
FROM HI·Z
SOURCE
LFT156
~
(6)
TOOATAANALYSIS
SYSTEM
+
Greater than'12-bit accuracy without adjustment
9-4B
Absolute Maximum Ratings
LFT155/LFT156
LFT355/LFT356
Supply Voltage,
Power Dissipation (Pd at 25°C)
and Thermal Resistance (8jA) (Note 1)
±22V
670mW
150°C/W
150°C
±40V
±20V
Continuous
-65°C to +150°C
300°C
±18V
570mW
150°C/W
115°C
±30V
±16V
Continuous
-65°C to +150°C
300°C
TjMAX
Differential Input Voltage
Input Voltage Range (Note 2)
Output Short-Circuit Duration
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
DC Electrical Characteristics
SYMBOL
VOS
AVOS/AT
r-
(Note 3)
LFT155/LFT156
LFT355/LFT356
MIN
TYP
MAX
CONDITIONS
PARAMETER
Input Offset Voltage
Average TC of Input Offset
UNITS
RS= 50n, TA= 25°C
0.5
mV
Over Temperature
1.0
mV
RS= 50n
3
5
r-
:!l
/lVfC
(,.)
Change in Average TC
RS = 50n, (Note 4)
0.5
Tj =.25° C, (Notes 3, 5)
3
permV
Input Offset Current
Tj ~THIGH
Input Bias Current
IB
U1
en
/lVfC
with Vas Adjust
lOS
Tj = 25° C, (Notes 3, 5)
30
TjSTHIGH
RIN
I nput Resistance
Tj = 25°C
AVOL
Large Signal Voltage Gain
Vs = ±15V, TA = 25°C
10
pA
1
nA
50
pA
5
nA
10 12
50
n
200
V/mV
Va = ±10V, RL = 2k
Over Temperature
Output Voltage Swing
Va
VCM
'Input Common·Mode Voltage
25
±12
±13
V
Vs = ±15V, RL = 2k
±10
±12
V
±11
+15
-12
V
VS= ±15V
CMRR
Common-Mode Rejection Ratio
PSRR
Supply Voltage Rejection Ratio
V/mV
Vs = ±15V, RL = 10k
Range
V
95
(Note 6)
dB
85
100
dB
LFT156, LFT356
I TYP I MAX
UNITS
T A = 25°C, Vs = ±15V
SYMBOL
PARAMETER
IS
Supply Current
AC Electrical Characteristics
SYMBOL
PARAMETER
SR
Slew Rate
GBW
Gain Bandwidth Product
ts
Settling Time to 0.01%
en
Equivalent Input Noise Voltage
in
CIN
Equivalent Input Noise Current
U1
U1
.......
Voltage
ATC/AVOS
"-I
(,.)
MIN
LFT155, LFT355
I TYP I MAX
I
2
I
MIN
4
5
I
7
mA
TA = 25°C, Vs = ±15V
CONDITIONS
AV= 1
LFT155,LFT355
MIN
TYP
MAX
3
5
2.5
\ (Note 7)
LFT156, LFT356
MIN
TYP
MAX
UNITS
\ 10
12
V//lS
4
4.5
MHz
4
1.5
/ls
RS= lOOn
f= 100Hz
25
15
nV/YHz
f= 1000 Hz
20
12
nV/YHz
f= 100Hz
0.01
0.01
pA/YHz
f= 1000 Hz
om
0.01
pA/~
3
3
I nput Capacitance
9-49
pF
Notes for Electrical Characteristics
Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX, 8jA, and the
ambient temperature, TA. The maximum available power dissipation at any temperature is Pd = (TjMAX.- TA)/fijA or the 25°C PdMAX, whichever is less.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to th~ negative power supply voltage.
Note 3: Unless otherwise stated, these test conditions apply:
LFT155/LFT156
Vs ~ ±20V
-55°C ~ TA ~ +125°C
+125°C
LFT355/LFT356
, ±15V ~ Vs ~ ±IBV
~15V ~
Supply Voltaga, Vs
TA
THIGH
0°C~TA~+70°C
+70°C
and VOS, IB and lOS are measured at VCM = O.
Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5 p.Vfc typically) for each·mV of
adjustment from its original unadjusted value. Common·mode rejection and open loop voltage gain are also unaffected by offset adjustment.
Note 5: The input bias currents are junction·leakage curren'ts which approximately double for every
1ffc increase in the junction temperature, Tj.
Due to limited production test time. the input bias currents measured are correlated to junction temperature. In normal operation the junction
temperature rises above the ambient temperature as a result of internal power disSipation, Pd. Tj = T A + ejA Pd ,where E>jA is the thermal
resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum ..
Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common
practice.
Note 7; Settling time is defined here, for a unity gain inverter connection using 2 k!l resistors. It is the tim.e required for the error voltage (the
voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the
inverter.
Typical DC Performance Characteristics
Curves are for LFT155 and LFT156 unless otherwise specified.
Input Bias Current
"0' r--r--r--,-.,....-,-,
i 10. 1-:--1-+--+-+-+-,,/
-I
0-
-
::
~
<
!
.---r-'-+-,--.--,--.
10k
1--+-+--1-4--1--.11
~ "
1k
100
~
Input Bias Current
lOOk
~-+-~~~4--t-~
1
c:;~~+--+-+-+--l
35
~
,.
~
'0
V
~
~
/
"
"
15
SUPPLY VOLTAGE ltV)
-15
I
Q
m
Ii
~
-'0
•
" "
'0 15 '0 25
OUTPUT SINK CURRENT (lI'IA)
21
10
15
20
SUPPLY VOLTAGE I'V)
25
-,-55°C
-55"c S:TA :S:125~C
/
"
\
10152025303540
OUTPUTSOUR&E CURRENT (mAl
9·50
V
/
/
'0
/
... 25·C
I
25
Positive Common-Mode
Voltage Limit Input
+25"C
5
"" Jd,z1c
I-I I
I ~FT1~'
zo
"
i
~'
15
VS"':115V
'0
~!::
-5
J::
.:-
I
" !!ooo ....
~
;:
~
Positive Current Limit
~
=
.~
~
TC=25 C
LFT155
ID
lir
V
/
SUPPLY VOLTAGE (:tV)
Negative Current Limit
'0
~-5~C
':::: ~l25QC
~
a
UTtSS
-5
Supply Current
TC"-55"C
~
10
"~
~
l-I-- ~y
WlTIiHEATS.R.
J
I
I
--
V
~
=
/
L
COMMOIl-MOOE VOLTAGE tV)
Supply Current
RL -21t
TA"25"C
--
"0
CASE TEMPERATURE fCi
Voltage Swing
~
ZD
LnlK
.-~
~~~~E.n ••• l j
?
F.\'(T:::
J..-1/
-10
35
.0
~
3D
/
...-
I I
o
-25
CASE TEMPERATURE 14&)
m
VS"'±15V
TA-2S"C
ftL -SDk
3D
;;;
&5
Input Bias Current
50
:: 100
'0
.
i ..
.;:: ...
/
"
"
POSITIVE SUPPl'f VOLTS IV)
ZD
Typical DC Performance Characteristics
Negative Common-Mode
Input Voltage Limit
(Continued)
Open Loop Voltage Oain
Output Voltage Swing
.,...
21
V" .IIV
..
Z4 TA-2&IIC
~
28
Ii
II
i
..
CI
c
~
12
I!
~
OL-~~~~~--~~
-5
-10
-IS
4
10
-2D
IS
20
I
a
1.0
OUTPUT LOAD RLlkll)
SUPPLY VOLTAGE ('V)
NEGATIVE SUPPLY VOLTS (V)
10
Typical AC Performance Characteristics
Gain BandWidth
Gain Bandwidth
Normalized Slew Rate
1.1
~
~
.I'Iav"Il IJI.:o 1--1r-- Vs
VS' 'I5V_
.-
"Ii! ~.J- vs,,zov
~
LFTl51 -
l\
I,\,
LFTI55
1.6
1.4
12
,",
I--
'lit..I,\:
r-
1.0
~
~
I
-
0.4
a.z
a
-55 -35 -IS 5 zs 45 &5 IS IDS 125
CASE TEMPERATURE I"C)
-55 -35 -IS 5 25 45 65 IS 105 125
CASE TEMPERATURE ("C)
-55 -35 -15 5 25 45 6& IS 105 125
TEMPERATURE I"C)
LFT156 Small Signal Pulse Response.
AV= 1
LFT155 Small Signal Pulse Response,
AV= 1
LFT156 Large Signal Pulse Response,
AV=1
LFT155 Large Signal Pulse Response,
AV= 1
Bode Plot
10
.
I
-10
z
C -15
-20
-
-25
I
.
'
50
25
,
-25
-30
(j>l'
~
•
1\
-'~
-35
I
-75
-100
~
"'"10
FREOUENCY IMHz)
9-51
i
.
~
G2I
-so ;:
-,~
-125
100
125
lao
75
50
25
r.....
1111 ILF·hr!.111
10
I"'""' ..,. ...jJ I ~~lsE. vs' ,I5V
5
75
VS' ,I5V
GAIN
-5
§
Bode Plot
IS
lao
~Hls~l- -L~TI~511
,a
'7;~
0.6
-
1"""= =:::
I
I
V;. 'II5V
~~I~
0.1
>lOV
-zav ~ ~ { ,I5V
F""
J
~
~
"IJl'l
o
;;
-5
f--
:!. -10
!
-15
.. -20
-zs
-31
-35
-40
iit
~
~
~tP
t--I'\.
r-'I
.+
~
III
10
FREOUENCY (MH,)
-Z5
-50
-75
-I"
-125
-150
lDO
:l!
!li
...
~
~
Typical AC PerforlT'!ance Characteristics
Open Loop Frequency
, Response
""
110
..
~:.
... sa
... ,
9
~
90
~
~
UT15S
TA"ZS'C
VS· '15V
VS·,15V"':'
J
I'I..'\..
~
:E
,
"~
""
...:
ii ,1:
~
-s
10mV,\
lmV
1111
.1-J
~,
-10
10
100
1k
-10
10k lOOk 1M 111M
o
0.5
FREQUENCY IHzI
1.0
~EnllNG
Output Impedance
Output
10DO
+,
~
1-'
I'I..'\..
.
E 100
~
'II ~
z
Common-Mode Rejection
Ratio
Impedan~e
10
z
S·
~
, 1
~R~~
5
I!:
"
, co'
"
10
120 ,,--,.---,---.,.-::--::::-.
'"~
100
'"z
§"
u:;
'"g
:!i
~
10
10
SETTLING TIME 1.,1
TIME ,".1
~
"
~
\Imv
10
lDO
...
lFT1S6
VS' .'ISV
TA'Zs,c
il.~V
lo!
i
~
3D
1/
E
lFT155~
z
W
10 m,,/ /;,mV
..
'" ..,
Inverter Settling Time
YII
1111
"
'Il:
~ lFT1S&
10
>
Inverter S~ttling Time
10
~
(ContiilUedl ",
.
!==t~"'+ot:i:..k--+
80 t--t--+--<---'ld....
60t--t---t---t----t-~'Ir--j
~
0.1
·40
z
"~
20
8
lDO,k
10k
1M
10M
10k
FREQUENCY 1Hz!
Power Supply Rejection Ratio
!,
lOOk
1M
10M
100
FREQUENCY 1Hz!
Power Supply_ Rejection Ratio
aD ~--~~~~~--
I,Z
,
POSITIVE SUPPLY
.g
z
~
lli
" 40
'I
Ci
, ZO' ,1--4:-"-+-rl---p.~-l
AV"oo
.,
0,4
.L.
02
za
..
...
E
z
~
10k lOOk
FREQUENCY IHzI
Ik
VS' 'ISV
Rl-2k
TA'Z5'C
AV'1
~I-
!,-
""
~
120
~
100
AV -10
./
Ik
lOOk
10k
~
TA =25'C
100
TA o 25'C
VS"'S"-
~ ao
' Vs' ,15V
..~
~. ~
~o
ll1lIL
JIIUII.
111111
,10M
Equivalent I'nput Noise
Voltage (Expanded Scalel
ao
LFT1S6
fREQUENCY IH,I
10M
~
40
1M
'IM
<-CO
l,F,~,1SS
lOOk
lOOk
111111
llIlIl
60
11111
10k
140
1\
1111
1111
~
10k
Equivalent Input Noise
Voltage
~~
~
lFT156
IZ
Ik
o
FREO\lENCV (Hz!
Undistorted Output Voltage
Swing
24
100,
1M
10M
d.•
, t;. 0.6
. ,10
lD!Jk. 1M
LFT156
VS' '15V
lA'Z5C
20VSWING
RL' 2k
1,4
"
10k
Distortion
1,&
100,
"
S"
lk
FREQUENCV (Hz!'
.6·
z
LFT1SS
o
1
ii!
IlIIH
!!!'
1-'
~.
111111
lDO
FREQUENCV 1Hz!
9-52
'~O
1-.
Iurn
10
60
lk
'10k
~
;;
S
~
~
,
:~
~
ZO
lFT155
, ',LFTI56,
0
10
Ik,
FREQUENCY IHzI
lOOk
Detailed Schematic
r---------~----,_----------t_------------~--------t_-------------o+VtC
171
BALANCE
+---4.--+-Jliiilr-+-o
OUT
(BI
Connection Diagram
Metal Can Package
Ne
Order Number
LFT155H, LFT156H,
LFT355H or LFT356H
See NS Package HOBB
vTQPVIEW
Note. Pin·4 connected to case.
Application Hints
The LFT155/6 series are op amps with JFET input
devices. These JFETs have large reverse breakdown
voltages from gate to source and drain eliminating the
need for clamps across the inputs. Therefore large
differential input voltages can' easily be accomodated
without a large increase in input current. The maximum'
differential input voltage is independent' of the supply
voltages. However, neither of the input voltages'should
be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a
destroyed unit.
Exceeding the negative common·mode limit on either
input will cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state. Exceeding the negative common-mode
limit on both inputs will force the amplifier output to a
high state. In neither case does a latch occur since
raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a
normal operating mode.
Exceeding the positive common-mode limit 011 a single
input will not change the phase of the output however,
if both inputs exceed the' limit, the output of the
amplifier will be forced to'a high state.
These amplifiers will operate with the common-mode
input voltage equal to the positive supply. In fact, the
common-mode voltage can exceed the positive supply by
approximately 100 mV independent of supply voltage
and over the full' operating temperature range. The
positive supply can therefore be used as a reference on
an input as, for example, in a supply current monitor
and/or limiter.
Precautions should be taken to ensure that the power
supply for the integrated circuit never becomes reversed
in polarity or that the unit is not inadvertently installed
backwards in a socket as an unlimited current surge
through the resulting forward diode within the Ie could
cause fusing of the internal conductors and result in a
destroyed unit.,
9-53
Application Hints
(Continued)
A 'feedback pole is created when the feedback around
any a,mplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the
inverting input) to ac ground set the frequency of the
pole. In' many instances the frequency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and consequently there is negligible
effect on stability margin. However. if the feedback pole
is less than approximately six times the expected 3 dB
frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the
added capacitor should be such that the RC time
constant of this capacitor and the resistance it parallels
is greater than or equal to the original feedback pole
time constant.
Because these amplifiers are JFET rather than MOSFET.
input oP> amps they do not require special handli~g.
All of the bias currents in these amplifiers are set-by FET
current sources. The drai.n currents for the amplifi~~s are
therefore essentially independent of supply voltage.
As with most amplifiers. care should be taken with lead
dress. component placement and supply decoupling in
order to ensure stability. For example. resistors 'from the
output to an input should be placed 'withthe body closl!
to the input to minimize "pickup" and, maximize th'e
frequency of the feedback pole -by minimizing the
"
capacitance from the input to ground.
Typical Applications
(Continued)
Vos Adjustment (Usually Not Needed)
Driving Capacitive Loads
y'
5k
,v'
+2Y
- 2y
r
-l
y-
• vas
is adjusted with a 25k
potentiometer
•
Th'e potentiometer
wiper is
Due to a unique output stage design,.these ampli-
connected to V+
• For potentiometers with
,temperaturS coefficient of
100 ppmf C or ,less the
additional drift, with adjust
is .. ' 0.5 "VtC(mV of
adjustment
• TvPical overall drift: 5 "V (
·C ±(0.5 "VtC(mV of
adj.)
fiers have the ability to drive large capacitive loads
end still maintain stability. CLIMAX) '" 0.01 "F.
Overshoot
~
20%
Senling time (ts )' '" 5"s
9·54
Typical Applications
r-
."
(C~ntinued)
:::1
(J1
Errors Created by VOS. lB. lOS. CMRR. AOL in Some Basic Op Amp Circuits
and How the LFTXXX Series Minimizes Them
(J1
.......
r-
R2
~
15V
(J1
0)
r-
>~_::>VDUT
."
Output Erro'r: f'" (±Vos x AV ±R210s)+ [
-15V
•
EX: LFT356A as unity gain follower }
1 ) -1]
(1 + AA: ) -1
L
_
( 1+
CMRR
~¥: 110t C :S TA:S 70 ,C
o
-I
(V)
V OUT
,
R2 + Rl
_AV=Rl""""
W
(J1
(J1
.......
r-
:!:I
1.01 mV- 381'V > f >-1,01 mV- 5BI'V
VOUT VOUT
w
(J1
0)
15V'
R
>~~::>VDUT
-15V
•
t
Output Error: f = ±VOs - R (lB ±IOs) ± RC IVOs ±RIOs)
•
EX: LFTI56A, R = lOOk, C = O.II'F
t = Integration Time
1.1 mV
1.1 mV
1.4mV+-- >f>-1.6mV--10ms
10ms
A2
15V
Rl
A'I
' -1
• .' = I±VOs 11 + AV) >, R2 lOS)
R'2
-15V
( 1 + AV )
AOL
•
e' = ±2cS (%) : Error on AV due to resistor tolerance
•
CMR ICircuit) = 20 log
,.
•
.
(1 +
'
:Output Error due to Vas, lOS, AOL
~)
[~ '(I - CMRR
_1_ )
AOL, b + 1,
+
'R2 ± 6
-a '] -1 a=---
CMR ICircuit) 'MIN occurs for a 'MAX, b 'MAX
EX: LFT356A, AV = '10, R2 = 10k, O°C:S TA:S 70°C, 6 = 0.01%
11.01 mV ~. 2:-11.01 mV, f' = ±0.02%, CMR ICircuit) 'MIN = 85.3 dB
9·55
Rl ± 6
AV 1100±6)
IlooU)
b = _R'_I_±_6 = -;-,-ll..,00,=,=:±:-6.:..1:7
R'2±6 AV(100±6)
Typical Applications
(Continued)
High CMR"R. Low Drift Instrumentation Amplifier with "Floating Input Stage
'.
.
,~
3
4.
Z.717k
Z5k
25k
25k
6.25k
25k
10k
10k
25k
6.25k
25k
2.771k
15O--W"'"'....--...I\M_-~f-....
12
10
11
4
TO.22~F
10
LM325H
•
•
•
Input amplifier fully floating. Develop ± input voltage for the floating regulator, LM325, from a
second center tapped secondary winding.
All resistors, except the two 10k ones. are from National resistor array RA20~.
CMRR (instrum. amplifier) '" CMRR (difference amplifier) x AV ,; AVI = gain of the input stage.
GAIN SET-UP
Input Stage Gain
1
l'
1.
10
10
10
100
100
100
199
•
Output Stage Gein
1
2
5"
1
2
5
1
.~
5
5--
Overall Gain
1
2
5
10
20'
50
100
200
500
995
Jumper Pins
Expected Minimum
on RA201
CMRR (Overall Circuit)
5 to 7, 12 to 10
6t07,11tol0
2to 15
~ to 15,5 to 7, 12 to
2to 15,6 to 7,11 to
1 to 16
1 to 16,5 to;> 7, 12" to
1 to 16,6to 7,11 to
. 1 to14,6t07,11 to
10
10
10
10
10
83.4
82
86
103.4
102
106
123.4
122
126
131 dB
Gain error: ±0.01% on the output stage, ±0.01% on the input stage for a gain of 10, and ±1% for a gain of 199.
9·56
Typical Applications
(Continued)
Using the LFTXXX Series to Auto-Zero Ultra Fast Hybrid Op Amps (General Scheme)
15V
*Vos AOJUST OF
THE CIRCUIT
15V.
10k
lk
lOOk
lOOk
-----...::.j
VINo-+......- - - -.........
>:.:...t............+-oVOUT
Rl
• Vas. <1 Vas olthe circuit: The Vas ~nd drift of the LFT355 .
. <1T
I
~
Speed of the circuit: The GBW product and ts of the LH0032,
•
The circuit can also be used for inve'rters and integrators applications.
•
•
Due to the ultra high speed .of the LH0032C proper layout is recommended.
Compensation capacitor Cc is not needed for gains above 50. For more details see LH0032 data
sheet.
By adjusting·of the Vas of the LFT we adjust the Vas of the whole circuit.
•
9-57
Typical Applications
(Continued)
Settling Time Test Circuit
21<.0.1%
+1SV
Your
•
•
•
•
Settling time is tested with the LF16516 connected
as unity gain inverter and LF167 connected for
AV=-6
FET used to isolate the probe capacitance
Output ~ 10V step
AV = -5 for LF157
Large Signal. Inverter Output; VOUT (from Silttling Time Circuit)
1I:'T355
,
I'•
i
t
~
LFT366
,
I
I
•
I
z"s!DIV
1 ""DIV
Isolating Large Capacitive Loads
Boosting the LFT166 with a Current Amplifier
02
S.1k
01
5.1k
.+2~::F
-ZV
•
•
•
Overshoot 6%
ts lOps
When driving large CL. the VOUT slew rate determined by CL and IOUT(MAXI:
4VOUT = lOUT
4T
CL
•
0.02
'" (i.5 VIps = 0.04 VIps (with CL shown)
9-58
•
IOUT(MAX) '" 160 mA (will drive RL? 100nl
4VOUT
0.15
~ = 10-2 VI/ls (with CL sh~wn)
•
No additional phase shift added by the current amplifier
r-
Amplifiers
~National
~ Semiconductor
w
0)
.......
r::E:
lH0036/lH0036C Instrumentation Amplifier
o
o
w
0)
general description
The LH0036/LH0036C is a true micro power
instrumentation amplifier designed for precision
differential signal processing. Extremely high accu·
racy can !Je obtained due to the 300 Mil input
impedance and excellent 100 dB common mode
rejection ratio. It is packaged in a hermetic TO·8
package. Gain is programmable with one external
resistor from 1 to 1000. Power supply operating
range is between ±1V and ± 18V. Input bias current
and output bandwidth are both externally ad·
Justable or can be set by internally set values.
The LH0036 is specified for operation over the
-55°C to +125°C temperature range and the
LH0036C is specified for operation over the
'-25°C to +85°C tem'perature range.
features
•
•
•
•
•
•
•
•
High input impedance
High CMRR
Single resistor gain adjust
Low power
Wide supply range
Adjustable input bias current
Adjustable output bandwidth
Guard drive output
equivalent circuit and connection diagrams
INPUT
BIAS
GUARD
DRIVE
BANDWIDTH
ADJUST
OUTPUT
COIHROL
v'"
V-
rL-- ' __ -11___ .t2 __ j,~
INY.
INPUT
03
GAIN
SET
os
4
0'
I
I
I
I
I
.............&.:.:"'" OUTPUT
0'
GAIN
SET
o.
NON·INV.
INPUT
::E:
o
o
..
,
01
I,
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..J
GUARD DRIVE
OUTPUT
INVERTING
INPUT
OUTPIIT
CMOO
TRIM
TOP VIEW
Order Number LH0036H Dr LH0036CH
See NS Package H12B
9·59
eMOO
PRESET
CMRR
TRIM
300 Mil
100 dB
1 to 1000
90/lW
±lV to ±18V
o
U
<0
CW')
o
o
:t
..J
.......
<0
CW')
o
o
absolute maximum ratings
Supply Voltage
Differential Input Voltage
Input Voltage Range
Shield Drive Voltage
CMRR Preset Voltage
CMRR Trim Voltage
Power Dissipation (Note 3)
±laV
Short Circuit Duration
Operating Temperature Range
±30V
±Vs
±Vs
±Vs
±Vs
1.5W
electrical characteristics
Continuous
LH0036
LH0036C
Storage Temperature Range
'Lead Temperature, Soldering 10 seconds
-5SoC to +12SoC
-25°C to +BSoC
-6SoC to +150°C
300"C
(Notes 1 and 2)
:t
LIMITS
..J
PARAMETER
CONDITIONS
LHOO36
MIN
TYP
LH0036C
MAX
MIN
TYP
UNITS
MAX
Input Offset Voltage
IV,osl
Rs '" 1.0kfl., T A = 25°C
Rs = 1.0kl1
0.5
1.0
2.0
1.0
2.0
. 3.0
mV
mV
Output Offset Voltage
(Voas )
Rs =- 1.0kU. TA = 2SOC
2.0
= 1.0kl1
5.0
6.0
5.0
Rs
10
12
mV
mit
Rs
<; 1.0kl1
Input Offset Voltage
TempeD (AVlos/AT)
Output Offset Voltage
TempeD (.:.l.voos/AT)
Overall Offset Referred
Av
= 1.0
to Input (Vos)
Av
= 10
Av = 100
Av = 1000
Input Bias Current
TA
= 25"C
TA
;;:
10
10
MVtC
15
15
MV/'C
2.5
0.7
0.52
0.502
6.0
1.5
1.05
1.005
40 .
100
150
50
125
200
nA
nA
10
40
80
20
50
100
nA·
nA
(1.1
Input Offset Current
25°C
11051
Small Signal Bandwidth
Full Power Bandwidth
Input Voltage Range
Av = 1.0. RL = lOkl1
Av c 10, RL = 10kl1
Av = 100, RL = 10kl1
Av = 1000. RL = 10kn
350
35
3.5
350
350
.35
3.5
350
kHz
kHz
kHz
Hz
VIN ~ ±lOV, Rl. '" 10k,
Av:::: 1
5.0
5.0
kHz
Differential
Common Mode
±lO
±1O
±12
±12
Gain Nonlinearity
Av :::: 1 to 1000
PSRR
±5.0V:::;Vs ::;±15V,
Av = 1.0
±5.0V <; Vs <; ±15V,
Av = 100
Output Voltage
±lO
±10
0.03
Deviation From Gain
Equation Formula
CMRR
mV
mV
mV
mV
Av = 1.0
Av:::: 10
Av = 100
±1O
±0.6
0.03
%
±l.D
±1.0
±3.0
%
1.0
2.5
1.0
5.0
mVIV
0.05
0.25
0.10
0.50
mVIV
1.0
0.1
50
2.5
0.25
2.5
0.25
50
5.0
0.50
100
mVIV
mVIV
MVIV
= 1.Ok
Vs :::: ±15V, Rl. = 10kn,
Vs = ±1.5V. RL = 100kl1
V
V
±O.3
DC to
100 Hz
ARs
±12
±12
100
±13.5
±O.S
±1O
±0.6
±13.5
±O.S
V
V
Output Resistance
0.5
Supply Current
300
Equivalent Input Noise
Voltage
20
20
MV/p-p
0.3
0.3
VIM'
3.8
180
3.8
180
Slew Rate
6.V LN := ±lOV,
RL lOkl1, Av
=
Settling Time
To flO mV, Rl.
6.Vou; "" 1.0V
Av == 1.0
A v = 100
11
0.5
400
400
= 1.0
600
MA
= 10k!l,
M'
M'
Note 1: Unless otherwise specified, all specifications apply for Vs "" ±15V, Pins 1,3, and 9 grounded, -25°C to +8SoC for the
LH0036C and -55" C to +125" C for the LHOO36.
Not.
2: Ali typical values are for T A
= 25"C.
Note 3: The maximum junction temperature is 150°C. For operation at elevated temperature _derate the G package on a
thermal resistance of 90°C/W, above 25°C.
9-60
rX
o
typical performance characteristics
·J20
f--
Jl0
¢ JOO
.3 290
....
ffia:
~
~
~
1000
r-- r- V.'-'15~
¢
.3
....
ffi
280
~
f-- r-- r- Vs!O ±1.5V
40
w
.1. .l
o
Q
25
50
75
100
2.0 4.0 6.0 8.0
125
Peak to Peak Output
Voltage Swing vs RL
1111111
24
..
..'"~
~>
1
IJ;~li15J
Q
28
11111111
I
2.4
1 ~~I~~1.5~
20
2.0
>
1.6
....
11111111
11111111
1,2
. ..
0.8
TA = 25 C
PINS I, 3, & 9 GROUNDED
D
1.0k
10k
16
1/
10
'"
18
±2.0
i6.0
c
:;j
c
-!
~ "'
a
~ ....z
-!
~
~
0.4
60
50
240
>
=
210
S
100
'";;:
'"
150
~
90
'"z
~
..
JO
'"~
20
>
60
-!
40
w
..
120
~:~:~on
IIl'NII
R~ ~1!H!l>
Vs =±15V
RL = 10k
TA - 25'C
PINS 1 & 3 GROUNDED
I II IIIi
1111111
R~ I~~I.~~
1111111
1111111
10
Ra'~:::'
30
b
....
0
1.0a!
lOOk
..'"'"~
±18
Gain vs Frequency
Vs= ±15V
PIN 1 GROUNDED
270
±14
Closed Loop Voltage
300
.s
.!:10
SUPPLY VOLTAGE (V)
Total Input Noise Voltage*
vs Frequency
36
34
10 12 14
w
en
(")
/
SUPPLY VOLTAGE ('V)
TEMPERATURE ('C)
"'
"'"~
20
o
1/
/
::'"
"
X
o
PIN " 3 &9 GROUNDED
JO
10
-55 -25
32
"'"~
...>
/'
100
TA =ZS"C
40
PIN 11, J &19 GRyUND~D
10
-;;;
;:!
-.;
;:!
~
I
20
r-
RL = 10k
1= b
~
JO
w
en
........
50
= t=::: t=:::
TA -25'C
PINS l,J, & 9 GROUNDED ~
o
Output Voltage Swing vs
Supply Voltage .
Supply Current vs Supply Voltage
Supply Current vs Temperature
1111111
10
100
1.0k
100
10k
l.Ok
FREQUENCV (Hz)
LOAD RESISTANCE (n)
10k
lOOk
1.OM
FREDUENCY (Hz)
'NOI5(!volt<>geU'ldUdescontrlblJl.OIl iromSOlJrCereS<5wnce
Common Mode Voltage vs
Closed Loop Voltage Gain
CMRR vs Frequency
100 -~..
90 . .lII~
80 AvcL -l0
WJJrAvcL=lDO-
Supply Voltage
40
RL "'10k
t-14Hz
TA "'25°C
PINS 1,3, & 9 GROUNDED
Vs"'±lSV
VcM =1.0Vp.p
TA"'25°C
A~~~ Ill\l~o -t+ftHllN:HtIlIll-+H+tlIIl
70
60
50 rttffiM~++ftHllrttffiffiP~+tlIIl
40 H+ttttlll--H-ttttHt-t-tttttltl-ttffl~
30 H+ttttlll--H-ttttHt-t-tttttltl-t+tt(-IIII
20 H+ttttlll--H-ItIIHt-t-tttttltl-t+tt(-IIII
/
/
10 H-++IJtj(f-ttltHfll--H-tttI~-t+1tttIII
oH+tt!r!tIt-++ftttIlf-++tt(tItt-+H-tffIII
10
100
Ra - GAIN SET RESISTOR (n)
1.0k
10k
,-
;'
V
lOOk
15.0
FREQUENCV 1Hz)
,15
110
,20
SUPPL V VOLTAGE ('V)
Output Voltage Swing vs
Input Bias Current
50
....~
Vs = ±15V
ffi
a:
JO
:'l
20
~
iii
~
l!i
-
~
•
l
§:
10
5
I!:
o
-55 -25
Vs .'7±1.5V
25
50
75
TEMPERATURE ('CI
100 125
16
14
12
."
/1111
18
w
'"~
10
11111 L I
20
1
40
Large Signal Pulse Response
Frequency
22
PINS I, 3, & 9 GROUNDED
\
11111 11't
-
II
Illi
+10
AVCL = 1.0
~~~L =' lJD~
w
"'"~
>
...
~
\
III
..
Vs =±15V
Rl"'10k
2.0
o
TA"25'C
:~
PINS 1 3 &9 GROUNDED
100
1.Dk
10k
FREQUENCV (Hz!
9·61
~
~
Q
8.0
6.0
4.0
I
~
lOOk
II
-10
40
\
Vs = ±15V
RL "10k
AVCL =1.0
PINS I, 3, & 9 GROUNDED
80
120 160 200 240 280
T1MEl!41
U
<0
C"')
typical applications
o
t2.1tlV
o
J:
'NPUT
..J
.......
<0
C"')
o
o
r------1~--'~I---I----oOUT'UT
J:
..J
tl0",V
INPUT
ENABLE
'------------0\1-·-1.0\110-15\1
·RBW A/fD RII ARE OPTIONAL BANDWIOTH AND INPUT BIAS CURRENT
CONTROLLING RESISTORS.
±IOV
INPUT
Instrumentation Amplifier with Logic Controlled
Shut·Down
Pre MUX Signal Conditioning
OUTPUT
Isolation Amplifier'for Medical Telemetry
.----.....-+--....
--4-+1&\1
,
I
/
,,.
J
-<~>--_~---"""_IIiV
DIODES IN THERMAL
CQNTACTWITHAMBIENT
THERMOCOUPLEJUNCTlONS
Thermocouple Amplifier with Cold Junction Compensation
GAIN
JDeL
v'
"OmA
CURRENT
1
10
LOOP
OUTPUT
v"
F~
FH
I
Fl
F..
~
9·62
bRGC(I
A FUNCTION OF SELECTED AVCl • R. AND Raw
High Pass Filter
Process Control Interface
-
s:
o
applications information
THEORY OF OPERATION
signal bandwidth 350 kHz for Ave!- = 1. In some
applications, particularly at low frequency, it may
be desirable to limit bandwidth in order to mini·
mize the overall noise bandwidth of the device. A
resistor Raw may be placed between pin 1 and
ground to accomplish this purpose. Figure 2 shows
typical small signal bandwidth versus Raw.
r------------,I
>-t-""iI.-t-~Wv-__,:
I
I
>--b-J~l1_oDUTPUT
"
1M
o
w
0)
......
r-
::z::
o
o
w
0)
o
glf10k
L _ _ _ _ _ _ _ _ _ _ _ _ .J
~
~
~
FIGURE 1. Simplified LH0036
The LH0036 is a 2 stage amplifier with a high
input impedance gain stage comprised of A, and
A2 and a differential to single·ended unity gain
stage, A3 • Operational amplifier, A" receives
differential input signal, e" and amplifies it by a
factor equal to (Rl + RG)/R G.
I.OM
Rl + RG
= ---e,
Rl
10M
100M
1DOOM
Raw - RESISTANCe FROM PIN I TO GROUND In)
FIGURE 2. Bandwidth vs RBW
A, also receives input e2 via A2 and R2. e2 is seen
as an inverting signal with a gain of R 1IR G. A,
also receives, the common mode signal eCM and
processes. it with a gain of +1.
Hence:
V,
IDle
It also should be noted that large signal bandwidth
and slew rate may be adjusted down by use of
Rsw. Figure 3 is plot of slew rate versus Raw ..
I .•
0.1
(1)
~
RG
~
w
S 0.01
By similar analysis V2 is seen to be:
R2+ RG
R2
V2 = --,- - e2 - e, + eCM
RG
RG
~
~O.ODI
(2)
For Rl = R2:
10k
,DOk
t.OM
10M
100M
Raw - RESISTANCE FROM PIN 1 TO GROLiND tnt
V2-V, =[C:J+l](e2 -e,)
FIGURE 3. Output Slew Rat~ vs RBW
(3)
CMRR CONSIDERATIONS
Also, for R3 = R5 = R4 = R6, the gain of A3 = 1,
and:
.
Use of Pin 9, CMRR Preset
Pin 9 should be grounded for nominal operation.
An .internal factory trimmed resistor, R6, will
yield aCMRR in excess of 80 dB (for AvcL = 100).
Should a higher CMRR be desired, pin 9 should
be left open and the procedure, in this section
followed.
eo=(1)(V2 -V,)=(e2- e,) [1+(::1)] (4)
As can be seen for identically matched resistors,
eCM is cancelled out, and the differential gain is
dictated by equation (4).
DC Off-set Voltage and Common Mode
Rejection Adjustments
Off·set may be nulled using the circuit shown in
. Figure 4.
For the LH0036, 'equation (4) reduces to:
eo
50k
AvcL = - - - = 1 + - e2
RG
-e,
(5a)
The closed loop gain may be set to any value from
1 (R G = co) to 1000 (R G e; 50n). Equation (5a)
re·arranged in more convenient form may be used
to select RG for a desired gain:
RG =
50k
Avc!- -1
HI
(5b)
.....WY_~I ...
vv-
USE OF. BANDWIDTH CONTROL (pin 1)
FIGURE 4.
In the standard configuration, pin 1 of the LH0036
is simply grounded. The amplifier's slew rate in
this configuration is typically 0.3V//ls and small
Vas
Adjustment Circuit
Pin 8 is also used to improve the common mode
rejection ratio as shown in Figure 5. 'Null is
9·63
o
CO
C")
~
.-J
.......
applications information (con't)
a~hieved by alternately applYing ±10V (for V+ &
·+1111
V- = l5vl. to the inputs and adjusting R 1 for
minimum change at the output.
'
CO
+t5V
C")
o
o
::t:
ourpll'T
...I
FIGURE 8.lmprovod,AC CMRR Circuit
Atter adjusting Rl for best dc CMRR as before,
R2 should be, adjusted for minimum peak-to-peak
voltage at the output while applying' an ac
common, mode signal of the maximum amplitude
and frequ~ncy of interest.
FIGURE 5. CMRR Adjustment Circuit
The circuits of Figure 4 and 5 may be combined
as shown in Figure 6 to' accomplish both Vos
and CMRR null. However, the Vas and CMRR
adjustment are interactive and several iterations
are required. The, procedure for null should start
with the inputs grounded.
INPUT BIAS CURRENT CONTROL
Under nominal operating conditions (pin 3 ground·
ed). the LH0036 requires input currents of 40 nA.
The input 'curr~~t may, be reduced by ,inserting a
resistor (Rs) between 3 and ground or, alter·
natively, between 3 and V-. For Rs returned to
ground, the input bias current may b~ predicted
by:
V+ -0.5
---,----4xl0 B +800R s
(6a)
V+ - 05- (4 X 108 ) (ISlAS)
Rs = - - - - - - - - - 800 ISlAS
(6b)
ISlAS
or
-15\1
FIGURE 6. Combined CMRR,
Vos
~
Adjustment Circuit
R2 is adjusted for Vos null. An 'input of +10V
is then applied and Rl is adjusted for CMRR null.
The procedure is then repeated until the optimum
is achieved.
"
,
" ' ,',
Where:
ISlAS = Input Bitis";urrent (nA)
, , : Rs =, External Resistor connected between
, 'pin 3 and ground (Ohms)
A circuit which overcomes adjustment 'interaction
is shown in Figure 7. In this case, R2 is adjusted
first for, output null cif the LH0036. R 1 is 'then
adjustea for 'output null with +10V input. It is
.always a good idea to, check CMRR null with, a
-10V input. The optimum nlill' achievable will
yield the highest CM R R over the amplifiers com·
mon mode range.
V+ = Positive Supply Voltage (Volts)
Fig~re
"
'
9 is a' plot 'of input bias current versus Rs .
100mRF.I.
10
1.0
..'IiV
ov.'~:~~ 0-<,.---'1
-tOV
,---..-'0+16V
...."'
100k
t.OM
10M
100M
Ra - RESISTANce FROM PIN 3 TO GROUND (0)
FIGURE 9. Input Bias Current as a Function of RB
• NOTE: NOMINAL VALUE RI TO ACKIEVE OPTIMUM CMRR'""-"'-"-'-
.....0 -1&\1
As indicated above, Rs may be' returned to the
negative supply voltage. I nput bias current may
then be pr.edicted by:
FIGURE 7. Improved Vas, CMRR Nulling Circuit
AC CMRR Considerations
The ac eM R R . may be improved u'sing the circuit
~F~reR
'
,
(V+ - V-I - 0.5
I SIAS'''''
- 4 X lOB + 800 Rs
9-64
applications information (con't)
or
In a typical application, Vs ; ±15V, IB1 :::; IB2 :::;
40 nA, the total current, IT, would flow through
R ISO causing a voltage rise at point A. For values
of Rlso. ~ 150 Mn., the. voltage at point A exceeds
the +12V common range of the device. Clearly,
,for Rlso ; 00, the LH0036 would be driven to
positive saturation.
(8)
800 IBIAS
'
Where:
lalAs ; Input Bias Current (nA)
RB' ; External resistor connected between
pin 3 and V- (Ohms)
The implication is that a finite impedance .must
be supplied between the input and power supply
ground. The· value of the resistor is dictated by
the maximum input bias current, and the common
mode voltage. Under worst case conditions:
V+ ; Positive Supply Voltage (Volts)
V-; Negative Supply Voltage (Volts)
100
Rlso
10
VCMR - VCM
< --''''-''-'---'--
(9)
IT
Where:
1
VCMR
j
1.0
Common . Mode Range (10V for
the LH0036)
VCM ; Common Mode Voltage
IT.; lal + IB2
100k
toM
10M
100M
In applications in which the signal source is floating, such as a thermocouple, one end of the source
may be grounded dir~ctly or through a resistor:'
AB - RESISTANCE FROM PIN 3 V- (nl
FIGURE 10. Input Bias Current as a Function of RB
GUA'RD OUTPUT
Figure 10 is a plot of input bias current versus
Ra returned to V- it shou Id be noted that bandwidth is affected by changes in RB. Figure 11 is a
plot of bandwidth versus Ra.
Pin 2 of the LH0036 is provided as a guard drive
pin in those stringent applications wh ich require
very low leakage and minimum input capacitance.
Pin 2 will always be biased at the input common
mode voltage. The source impedance looking into
pin 2 is approximately 15 kn.. Proper use of'the
guard/shield pin is shoWn ·in Figure 13.
+1SV
Ro - RESISTANCE FROM PIN lTD GROUND In)
FIGURE 11. Unity Gain Bandwidth as a Function of RB
FIGURE 13. Usa of Guard
BIAS CURRENT RETURN
PATH CONSIDERATIONS
For applications requiring a lower source impedance
than 15 kn., a unity gain buffer, such as the
LH0002 may be inserted· between pin 2 and the
input shields as shown in Figure 11.
The LHp036 exhibits input bias currents typically
in the 40 nA region in each. input. This current
must flow through R lso as shown in Figure 12.
·,5V
OUTPUT
OUTPUT
FIGURE 14. Guard Pin With Buffer
FIGURE 12. Bia. Current Return Path
9·65
~
o
o
w
0)
......
r-
:::t
o
o
w
0)
o
~National
Amplifiers
~ Semiconductor
LH0037/LH0037~ ,Low'·~ost Instrumentation Amplifier
general description
The LH0037/LH0037C is a true instrumentation amplifier ,'designed for precision differential signal' processing_ ExtrelT\ely ·high accuracy c~n be obtained due to
the 300 MO input impedance and, excellent 100 dB
co~mon-mode rejection ratio ... It is packaged in a
hermetic TO-S package_ Gain is programmable with one
external resistor from 1 to 1000. Power supply operating
range is between ±5V and ±22V.
is specified for operation over the -25°C to +S5°C
temperature range.
features
•
300MO
100dS
1 to 1000
250mW
±5V to ±22V
High input impedance
• High CMRR
• Single ,resistor gain adjust
•
•
•
The LH0037' is specified for. operation over the
-55°C to +125°C temperature'range and the LH0037C
Low power
Wide supply range'
Guard drive output
equivalfmt circuit and connectiot:' diagrams
GUARD
DRIVE
OUTPUT
r---
Metal Can Package
v-
y+
, --.-~- -1...:.:._J,2,
GUARD DRIV£
OUTPUT
INV.
INPUT
.5
R3
.,
GAIN
SET
">-6-j-:'::.,'0 OUTPUT
.,
GAIN
SET
••
••
> .....- -.....I\I\fV-+---"\Mr---=<>::S~T
I.
.T
NDN-tNV.
INPUT
CMRR
TRIM
1.._'_",:, _ _ -.:... _ _ _ _ _ _ _ _ .J
typical applications
eM••
TRIM
TOPVIEW
Order Number LH0037H or LH0037CH
Sea NS Package H12B
.-
OUTPUT
IlOlation Amplifier for Medical Telemetry
9-66
r-
:I:
absolute maximum ratings
Supply Voltage
±22V
±30V
Differential Input Voltage
Input Voltage Range
Shield Drive Voltage
±Vs
±Vs
±Vs
±Vs
CMRR Preset Voltage
CMR R Trim Voltage
Power Dissipation. (Note 3)
Continuous
Shart Circuit Duration
Operating Temperature Range
LH0037
LH0037C
Storage Temperature Range
Lead
Tem~era.ture
-55°C to +125°C
-25°C to +85°C
-55°C to +150°C
300°C
(Soldering. 10 seconds!
l,5W
electrical characteristics
(Notes 1 and 2)
CONDITIONS
LHOO37
MIN
= 1.0kU, TA = 25°C
= 1.0 kU
= 1.0 kU, T A = 25°C
= 1.0 kU
Input Offset Voltage (Vias)
Rs
Rs
Output Offset Voltage (V aas )
Rs
Rs
Input Offset Voltage
Tempco (LlV,as/LlT)
Rs::; 1.0 kU
Output, Offset Voltage
Tempeo (LlVoas/LlT)
Overall Offset Referred to
Input (Vas)
Av
Av
Av
Av
Input Bias Current (I B )
TA
= 1.0
= 10
= 100
= 1000
= 25°C
Input Offset Current (los)
TA
= 25°C
Small Signal Bandwidth
Av
Av
Av
Av
Full Power Bandwidth
Input Voltage Range
MAX
0.5
2.0
MIN
MAX
1.0
2.0
1.0
2.0
3.0
mV
mV
5.0
6.0
5.0
10
12
mV
mV
10
}J.vtc
15
15
}J.vtc
2.5
0.7
0.52
0.502
6.0
1.5
1.05
1.005
500
1.5
200
200
= 1.0, RL = 2 kU
= 10,
R L = 2 kU
= 100, RL = 2 kU
= 1000, RL = 2 kU
V ,N = ±10V, RL = 2 kU
Av = 1
Differential
= 1 to
1000
500
0.8
250
nA
}J.A
nA
350
35
3.5
350
kHz
kHz
kHz
Hz
5.0
5.0
kHz
±12
±12
0.03
Av
mV
mV
mV
mV
350
35
3.5
350
±12
±12
Gain Nonlinearity
UNITS
TYP
10
. 200
Common Mode
Deviation From Gain
LHOO37C
TYP
±0.3
V
V
0.03
±1
±1.0
%
±3
%
Equation Formula
PSRR
±5.0V::; Vs ::; ±15V,
Av = 1.0
±5.0V::; Vs::; ±15V,
Av = 100
CMRR
Av
Av
Av
= 1.0
= 10
= 100
Output Voltage
RL
= 2 kU
OCto
100 Hz
LlRs = 1.0k
10
Output Resista,":,ce
1.0
2.5
1.0,
5
mVIV
0.05
0.25
o.io
0.25
mVIV
1.0
0.1
25
2.5
0.25
100
2.5
0.25
25
5,0
1.0
100
mVIV
mVIV
}J.VIV
13
10
0.5
Supply Current
4.5
Slew Rate
LlV ,N = ±10V,
RL = 2 kU, Av
Settling Time
To ±10 mV, RL
LlV auT = 1.0V
Av = 1.0
Av = 100
8.4
13
V
0.5
U
. 4.5
0.5
0.5
3.8
180
.3.8
180
8.4
mA
V/}J.s
= 1.0
= 2 kU
}J.s
}J.s
Note 1: Unless otherwisespeciffed, all specifications apply for Vs - ±15V, pin 9 grounded, -25°C to +85°C for the LH0037C and -55°C to +125°C
for the LH0037.
Note 2: All typical values are for T A = 25° C.
Note 3: The maximum junction temperature is 150°C. For operation at elevated temperature derate the G package on a thermal resistance of
90°C/W, above 25°C.
9·67
W
.......
.......
r-
:I:
0
0
W
.......
LIMITS
PARAMETER
0
0
(')
(,)
'"oo
('I)
typical performance characteristics
Output Voltage Swing vs
Frequency
Closed Loop Voltage Gain
::J:
22
1000
.
.'"~
-I
........
>
~
('I)
"g
......
o
o
::J:
-I
!
>
....=>
10
~
1111111
f-
6.0
4.0
o
RG
-
1.0k
10k
lOOk
~~;c .',cio~
II
II
10
8.0
2.0
100 .
I~
11111
14
12
w
0
0
11111
20
18
16
~
100
Large Signal 'Pulse Response
VS =!15V
RL =,10k
TA =25:C
PIN 9 GROUNOED
100
1.0k
'10
AVCL '" 1.0
II
~
'"
1\
1\
~
>
....
~<
1\
1\
10k
II
",
10k
AVCl '" 1.0
PIN 9 GROUNOED
40
lOOk
80
120
160 200
240 280
TIME (",1
FREQUENCY 1Hz)
GAIN SET RESISTOR I!ll
1\
VS '" t15V
Rl
-10
typical applications (con't)
/
I
,I
"'AN
COLD JUNCTION
ADJUST
tOk
'5k
.-----...-+--.....----If-
-15V
420 rnA
CURRENT
i'
10
80·
LOOP
'A VCl
0
63
ZERO
I
\.
J
lOOk
-15V
Process Control Interface
30k
./
DIODES IN THERMAL
_
........- -. . .- - - -.... -15V
CONTACT WITH AMBIENT
THERMOCOUPLE JUNCTlDNS
Thermocouple Amplifier with Cold Junction Compensation
·2.118V
INPUT
v'
v,.
OUTPUT
"OOmV
INPUT
vGAIN
"OmV
INPUT
-IOV
INPUT
High Pass Filter
: Pre MUX Signal Conditioning
'9:68
Amplifiers
~National
~ Semiconductor
LH0044 Series Precision Low Noise
Operational Amplifiers
general description
The LH0044 Series is a low n.oise, ultra-stable, high gain,
precision operational amplifier family intended to replace
either chopper-stabilized monolithic or modular ampli.fiers. The devices are particularly suited for differential
mode, inverting, and non-inverting mode applications
requiring very low initial offset, low offset drift, very
high gain, high CMRR, and high PSRR. In addition,
the LH0044 Series' low initial offset and' offset drift
eliminate costly and time consuming null adjustments
at the systems level. The superior performance afforded
by the LH0044 Series is made possible by advanced
processing and testing techniques, as well as active
laser trim of critical metal 'film resistors to minimize
offset voltage and drift. Unique construction eliminates
thermal feedback effects.
guaranteed over the temperature range of -55°C to
+125°C, and the LH0044AC, LH0044B, and LH0044C
are guaranteed from -25°C to +B5°C. The device is
available in standard TO-5 op amp pin out and is
compatible with LM10BA, LM725, and LM741 type
amplifiers,
features
251lV max
• Low input of,fset voltage
±lIlV!month max
• Excellent long-term stability
0.5JlVtC max
• Low offset drift .
• Very low noise
0.7JlVp-p max 0.1 Hz to 10Hz
• High CMRR and PSRR
120 dB min
• High open loop gain
120 dB min
±13V min
• Wide common-mode range
±2V to ±20V
• Wide supply voltage range
The LH0044 Series is an excellent choice for a wide
range of precision applications, including strain gauge
bridges, thermocouple amplifiers, and ultrastable refer·
ence amplifiers, The LH0044 and LH0044A are
equivalent circuit and connection diagram
OVER COMP
Metal Can Package
COMP
COMP
O-:'-------+------II---~H
OUTPUT
v-
.,
INVERTING
INPUT
2
TOP VIEW
em ileltchlwly isollted
sao
Note: Camp.nat.OII illiDI norm,lly requited. HawlYet', for mll(imLim
IlIblllty.IO.DIJ1FClpI~ltorlhouldb.pllcedl"1W"npinsllndawhen
dl'litl is used belowdoSld loop pins of 10.
D.
NON·INVERTING
3
.2
••
500
INPUT
TO-S Metal Can Package (HI
Order Number LH0044AH or LHO(J44H
(-5SoC to +12SoCI
Order Number LH0044ACH, LH0044BI1
or LHOO44CH (_25°C to +8SoCI
See NS Pack_ H08B
L----4----------~---~~----~v-
9·69
tn
.-CI)...
CI)
U>
~
~
0
0
::z::
...I
absQlute maximum ratings
Supply Voltage
Power Dissipation
Differential Input Voltage (Note 4)
Input Voltage (Note 5)
Output Short-Circuit Duration
±20V
600mW
±16V
±15V
Continuous
dc electrical characteristics
Operating Temperature Range
LHOO44, LH0044A
LHOO44AC,LH0044B,LH0044C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
-S5°C to +126°C
-25°C to +85°C
~5°C to +150°C
300°C
(Note 1)
LIMITS
PARAMETER
CONDITIONS
LHOO44AfLHOO44AC
MIN
Input Offset Voltage
T A = 25°C. Rs = 5OIl, VCM • OV
LHOO44C Onlv
Input Offset Voltage
Rs = 501l, VCM = OV
LH0044A and LH0044B Only
Average Input Offset Voltage Drift
Long·Term Stab[1i1Y
Input Noise Voltage (Note 3)
LHoo44ILHOO44BILHOO44C
TVP
MAX
MIN
TVP
8
25
12
50
75
,
0.5
0.2
50
100
p.V
p.V
150
75
p.V
p.V
TMIN S;TA S;TMAX
LH0044B Only
0.1
(Note 2)
0.2
1
0.3
2
0.35
0.50
0.7
0.9
0.35
0.50
O.B
1.0
'BW=O.I Hz to 10 Hz, Rs· 50n
Rs = 10 kn Imbalance
Thermal Feedback Coefficient
0.006
UNITS
MAX
p.vtc
p.vtc
1.3
0.5
p.Vlmonth
p.Vp-p'
p.Vp-p
0.005
p.VfmW
Open Loop Voltage Gain
RL = 10 kll
120
145
114
' 140
Common-Mode Rejection Ratio
-IOV S; VCM S; + 10V
120
145
114
140
dB
Power Supply Rejection. Ratio,
±3V S; Vs S; ±18V
120
145
114·
140
d8
V
Input Voltage Range
,Output Voltage Swing
Input Off.et Current
RL = 10kn
±13
±13.8
±12
±13.5
£,3
±13.7
±12
±13.5
1,0
2.5
5.0
1.5
5
40
15
80
25°C S;TA S;TMAX
TMIN S;TA <25°C
8.5
15
50
10
30
100
nA
nA
50
300
100
600
pAtC
Average Input Bias Current Drift
Differential Input Impedance
10
5
Common-Mode Input Impedance
Supply Current
V
'26DCS;TA S;TMAX
TMIN S;TA <25°C
Average Input Offset Current Drift
Input 8ia. Current
dB
Power Dissipation
ac electrical characteristics
PARAMETER
nA
nA
pAtc
8
2.6
2 x 10"
IL =0
5.0
10.0.
Mn
Il
2 X 10"
0.9
3.0
1.0
4.0
mA
27
90
30
120
mW
TA '= 25°C, Vs'= ±15V
TVP
UNITS
Rs = 1 kll, fo = 10 ,Hz
Rs = 1 kll, fo = 1 kHz
11
9
nVI"fHz
nVI"fHz
Slew Rate
Av ='+1,
RL = 10 kll. Y'N = ±10V
0.06
Large Signal Bandwidth
Av =+1,
RL = 10 kll, Y'N = ±IOV
I
Overload Recovery Time
Av =+IOO,V'N =..,-IOOmV\.
10 ~
~
co
!lco
20
V~'~'. 15V
Rs=lkn
TA =25"C
~
!
Input Voltage Range
Input Bias Current
..
.
~
20 1--+-+-+-1-~+-+-+
A
A
15
PDSITIV~
co
0<
!:;
>
$
10
A
~
~
z
~
..
NEGATIVE
A
A
l;
~
o
10
100
Ik
10k
lOOk
,10
,20
:!:.15
FREQUENCY (Hz!
Input Bias Current vs Common·
Supply Current vs
Mode Input Voltage
Supply Voltage
,15
Open Loop Frequency
Response
160
1.2
"~V
Vs =t15V
1.1
TA =211'C
1 '0.5 I----j'----t-+-+--t--tl
10h.-I--+,..-+-~""l""'~
1':
~
9.5
t+-t---+--!---+--t---l
~_
8.0
1-t-+--t-~1---+--+-4
1.5
L..L..--'-__'--...J..__.l.-...J..---l
-15
-10
-5
0
5
10
"
i1':
1.0
~
0.1
~
I-
>
0.1
0.5
0.4
..
..~
c
~
.
.
>
.4
~
co
•2
.'5
co
co
80
0<
~
:>
- '\
"
60
40
"
20
I
o
.,5
0.01 0.1
120
1
10 100 Ik 10k lOOk 1M
FREOUENCY (Hzl
I
~ ±10
Response
,
~
=10k
TA =25"C
..~~
"
10k
15
Vs "'±15V
"
TA =125"C
'"
'"co
1k
100
Large Signal Pulse
\
100
120
z
;;:
Output Swing
RL
.6
~
V; =
R, =10k
TA =25°C
SUPPLY VOLTAGE (VI
Vs'=~!i~'
\
1
TA =+12S"C
o
IS
Large Signal Voltage
Response
~ .,0
~
~ ii"'"
0.6
COMMON·MOOE INPUT VOLTAGE (VI
"2
..
f'
140
TA =-55"C
TA=25"Ch
0.9
,20
SUPPLY VOLTAGE (VI
SUPPLY VOLTAGE (VI
11 r-~--~-'---r--r--n
~~
,
...
..
~
'0
/
:>
.T'=25"CT
.5
I-
'"
.'"
~
I-
TA I=-55"C,
III
.2
lOOk
FREQUENCY (Hz!
-5
\
I
/
Vs '"±15V
R, -10k
Cs =O.8'"F
-10
-15
.8
.4
\
'I
0<
!:;
o
~
0.2 0.4 0.6 0.8 1.0 1.2 1.4
TlME(m~
OUTPUT CURRENT (mAl
Power Supply Rejection
Ratio vs Frequencv
160
JsI1~IJ~~ I.
140
~
120
..
iii
~
&!
CMRR vs Frequency
140
120
.6. Vs =±IDV
T.· 25"C
100
100
..
80
60
.;
80
~
&0
40
40
20
20
o
0.1
-
Maximum Power Dissipation
I
"- "\
Vs ""±15V
100
aV'"±10V
600
TA "'ZS"C
Ik
\
10
100
lk
10k lOOk 1M
FREQUENCY (Hz!
9-71
" "\
300
'"
i'-.r\.
AMBIENT
~'\
~
~
200
\
0.1
!
~
~
'\.
CASE
SOD
.. 400
1,\
o
10
100
FREQUENCY (Hzl
800
I
'DO
25
50
15
100
TEMPERATURE ("CI
125
150
applications information
\
LOW DRIFT CONSIDERATIONS
COMPENSATION
Achieving ultra-low drift in practical applications
, requires strict attention to board layout, thermocouple
effects, and input guarding. For specific recommendations
refer to AN-63 and AN-79.
A point worth stressing with regarc;! to low drift specifications is testing of the LH004,4. Simply stated-it is
virtuallY impossible to test the device using a thermoprobe or other form of local heating. A one degree
centigrade temperature gradient can account for tens
of microvolts of virtual offset (or drift). The test circuit
of Figure 1 is recommended for use in a stabilized oven
or continuously stirred oil bath with the entire circuit,
inside the oven or bath. Isothermal layout of the resistors
is advised in order to minimize thermocouple induced
EMF's.
For closed loop gains in excess of Hi, no external components are required for frequency stability. However,
, for gains of 10 or less, 'a 0.01,uF disc capacitor is
recommended between pin, 7 (V+) and pin B (Comp).
An improvement in ac PSRR will also be realized by
use of the 0.01,uF capacitor.
OFFSET NULL
In general, further nulling of LH0044 is neither necessary
nor recommended. For most applications the specified
initial·offset is sufficient.
However, for those applications requIring additional
null, an, obvious temptation might be to place a pot
between pins 1 and B with the wiper returned to V+.
This technique will usually result in reduced gain and
increased offset drift due to mismatch in the TCR of
the pot and R1 and R2. The technique is, therefore, not
generally recommended.
1
.---_--..-4:>_+"v
.---:-:----+--~-:"'I
I
o,I,FI
I
The recommended techni,que for offset nulling the
LH0044 is shown in Figure 2. Null is accomplished in
A2 and all errors are divided by the closed loop gain of
the LH0044. Additional offset and drift incurred due
to use of A2 'is less than 1,uVIV for V+ and V- changes
and O.Ol,uV/"C drift for the values shown in Figure 2.
>,'-4I-t-;:>_v.." -
ISOTHERMAL
I IODOVos
I
t----;-~:>_-"v
I
I
I~
OVEN.-&5"C~TA S"125°C
"W'.. I-wound construction (Ten s 10 ,ppfel
EDGE -
CONNECTOR
1M
FIGURE 1. LH0044 Temperature Test Circuit
OVER COMPENSATION
The LH0044 may be overcompensated in order to
minimize noise bandwidth by paralleling the internal
100 p F capacitor with an external capacitor connected
between pins 1 and 6. Unity gain frequency may be
pred icted by:
f=
4
X
10-5
100 pF + Coxt pF
(Hz)
FIGURE 2. LH0044 Null Technique
typical applications
.,
VO",
':"
GIiIl~t2~10-JtRI+R2)fDrvlN:SlamY
"Win-wound millen
X1000 Instrumentation Amp
Buffered Output for Heavy Loads
9-72
I"'"'
:x
o
typical applications (con't)
o
~
~
17.
MIN
en
CD
1-------1~-----:;;;Q;[""'"--o() +15V OUTPUT
...CD'
AI
".
0.1%
v
Vz (R2"R31
OUT"--AIlOUT
tn
$1DOmA
eo =IDV
+".
41D.uF
'ouT:5'00mA
i:,~o-~-------6--~
10V Reference Supply
~---'!!O----o() -15V OUTPUT
"Will'WDWd 101 mJRlmum dnft.
lin •• ndlllldlliUlltloft$O.OD5%
Precision Dual Tracking Regulator
82
2.111k
83
25k
AI
261.5
OUTPUT
NON"NVE~J~~~o-
___=-I
A'
16 252.5
.
15 unk
All
A\3
&l5k
15k
..
\I
AIO
\I
10
25k
13
(All Resistors are Part of National's RA201 Resistor Array).
OVERALL
GAIN
INPUT STAGE
GAIN
OUTPUT STAGE
GAIN
Xl
X2
X5
Xl0
X20
X50
Xl00
X200
X500
X995
Xl
Xl
Xl
Xl0
Xl0
Xl0
Xl00
Xl00
Xl00
X199
Xl
X2
X5
Xl
X2
X5
Xl
X2
X5
X5
. Precision Instrumentation Amplifier
9·73
JUMPER PINS
ON RA201
5 to 7, 12 to 10
6to 7,11 to 10
2 to
2 to
2 to
1 to
1 to
1 to
1 to
15
16,5 to 7. 12 to 10
15,6 to 7, 11 to 10
16
16, 6 to 7,12 to 10
16,6 to 7, 11 to 10
14,6t07.11 to 10
noise test circuit
0.1 Hz HIGH PASS FILTER
10 Hz lOW PASS FILTER
51<
VERT: '200 !'IV/DIV
HDRIZ: 5 SEC/DIV
9-74
~National
Amplifiers
~ Semiconductor
LM146/LM246/LM346
Programmable Quad Operational Amplifiers
General Description
Features
The LM 146 series of quad op amps consists of four
independent, high gain, internally compensated, low
power, programmable amplifiers. Two external resistors
(RSET) allow the user to program the' gain bandwidth
product, slew rate, supply current, input bias current,
input offset current and input noise. For example, the
user can trade-off supply current for bandwidth or
optimize noise figure for a given source resistance. In a
similar way, other amplifier characteristics can be
tailored to the application. Except for the two programming pins at the end of the package, the LM 146 pin-out
is the same as the LM 124 and LM 148.
•
•
•
•
•
•
•
•
•
•
Connection Diagrams
(ISET = 101-lA)
Programmable electrical characteristics
Battery-powered operation
Low supply current
350 I-IA amplifier
Guaranteed gain bandwidth product
0.8 MHz min
Large DC voltage gain
120 dB
Low noise voltage
28 nV!.../Hz
Wide power supply range
±1.5V to ±22V
Class AB output stage-no crossover distortion
Ideal pin out for Biquad active filters
Input bias currents are temperature compensated
(Dual-In-Line Packages, Top Views)
PROGRAMMING EQUATIONS
Total Supply Current ~ 1.4 mA (lSET/10 I'AI
Gain Bandwidth Product ~ 1 MHz (lSET/10 I'A)
Slew Rate = 0.4V/l's (lSET/10 I'A)
Input Bias Current = 50 nA (lSET/10 I'A)
ISET ~ Current into pin 8, pin 9 (s.e schematicdiagram I
y'
SET~81-_.J L._--1!-=g~ SET
~B
LM1U
~D
LM146·2
Ordor Number LM146J, LM246J or LM346J
Soo NS Package ~J16A
Ordor Numbor LM146-2J, LM246-2J, LM346-2J
.
See NS Package J16A
Order Number LM246N or LM346N
See NS Package N16A
Order Number LM346-2N
See NS Packago N16A
Schematic Diagram
r------------....------.----.. . .
- O y' (41
.....--ll---.J---OOUT.
TO OTHER
v'"
DP,,!,PS
y"
RSET
ISET
SET A.B, D.
II)
9-75
(0 ,
'lit
M
Absolute, PJI,aximum Ratings
LM146
:E
..J
......
(0
,'lit
N
:E
..J
......
(0
'lit
,..
:E
..J
-
(Note 1)
Supply Voltage
Differential Input Voltage (Note 1)
CM Input Vo'itage (Note 1)
Power Dissipation (Note 2)
Output Short-Circuit Duration (Note 3)
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Solderi,ng, 10 seconds)
Thermal Resistance (OjA), (Note 2).
Cavity DIP (D) (J) Pd
Molded DIP (N)
L~346
LM246
±22V
±30V
±15V
900mW
In'definite
-55°C to +125°C
150°C
-65°C to +1500 t
300°C
500mW
Indefinite
-25°C to+85°C
110°C
-65°Cto+150°C,
300°C
900mW
90°C/W
900mW
90°C/W
IIjA
, Pd
±18V
±30V
±15V
500mW
rndefinite
0°Cto+70·C
100°C
-65°C to'+150°C
300°C
±18V
±30V
±15", '
'
900mW
90°Cm
,500mW
140°C/W
'
IljA
DC Electrical Characteristics
(VS=±,15V,ISET= 10llA, Note 4)
LM146
/
PARAMETER
CONDITIONS
MIN
TYP
LM246/LM346
MAX
MIN
TYP
MAX
UNITS
,Input Offset Voltage
VCM=OV, RS~50il,,:rA=25°C
0.5
5
0.5,
6
mV
I ~put Offset Currerit
VCM = 'OV, TA = 25°C
2
20
2
100
nA
InpufBias Cu~rent
VCM = OV, TA = 25°C
50
100
50
250
nA
Supply Current (4 Op Amps)
TA=25°C,
1.4
2,0
1.4
2.5
mA
Large Signal Voltage Gain
RL = 10 kn, Ll.VOUT = ±10V,
-,
TA = 25°C
,
100
1000
"
50
,
1000
V/mV
Input CM Range
TA = 25°C
CM Rejection Ratio
RS~ 10kn, TA = 25°C
80
100
70
100
dB
Power Supply Rejection
Ratio
RS ~ 10 kn, T A = 25°C
80
100
74
100
dB
Output Voltage Swing
RL~ 10 kil, TA = 25°C
±12
±14
Short-Circuit Current
TA = 25°C
5
20
Gain 8andwidth Product,
,TA = 25°C
,0.8
Phase !IIargin
TA = 25°C
60 '
60
Deg
Slew Rate
TA=25°C
0.4
0.4
V/p,s
Input Noise Voltage
f= 1 kHz, TA = 25°C
28
28
nV/YHZ
Channel Separation
RL = 10 kil, Ll.VOUT= OV to
±12V, TA;' 25°C
120
120
dB
I nput Resistance
TA= 2,5°C
1.0
1.0
Mil
Input, Capacitance
TA = 25°C
2.0
2.0
pF
Input Offset Voltage
VCM=OV,~S~50n
0.5
6
0.5
7.5
Input Offset Current
VCM" OV
2
25
2
100
nA
Input Bias Current
VCM" OV
50
100
50
250
nA:
1.5
2.0
1.5
2.5
±13,5
,
Supply Current (4 Op Amps)
Large Signal Voltage Gain
. RL = 10 kn, Ll.VOUT ~ ±10V
Input CM Range
, CM Rejection Ratio
Power Supply Rejection
Ratio
50
±13.5
±14
±13.5
30
1.2
1000
±14,
±14
±12,
±14
5
.20
0.5
-- 25
±13.5
V
V
30
1.2
1000'
±14
mA
MHz
mV
rnA
V/mV
V
RS~50il
70
100'
70
1,00
dB
RS~50il
76
100
74
100
dB
-,
Output Voltage Swing
RL~10kil
±12
9-76
±14
±12
±14
V
oc
Electrical Characteristics
PARAMETER
r-
(VS = ±15V, ISET
s:
....
= lilA)
LM146
CONDITIONS
MIN
TYP
LM246fLM346
MAX
MIN
TYP
UNITS
MAX
Input Offset Voltage
VCM=OV,RS::S;50n,
TA = 2SoC
0.5
S
O.S
7
mV
Input Bias Current
VCM = OV, T A = 2SoC
7.5
20
7.5
100
nA
Supply Current (4 Op
Amps)
TA = 25°C
140
250
140
300
JlA
Gain Bandwidth Product
TA = 25°C
80
DC Electrical Characteristics
pARAMETER
(Vs
100
Input CM Range
TA=2SoC
CM Rejection Ratio
RS::S; 50 n, T A = 25°C
Output Voltage Swing
RL210kn,TA=25°C
kHz
LM246fLM346
TYP
MAX
0.5
5
MIN
UNITS
TYP
MAX
0.5
7
mV
V
±0.7
80
dB
80
±0.6
V
±0.6
Nota 1: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
Note 2: The maximum power dissipation for these devices must .be derated at elevated temperatures and is dictated by TjI\llAX, 9jA, and the
ambient temperature, T A. The maximum available power dissipation at any temperature is Pd = (TjMAX - TAII9jA or the 25'C PdMAX, whichever is less.
Note 3: Any of the amplifier outputs can be shorted to ground indefinitely; however, more than one should not be simultaneously shorted as the
maximum junction temperature will be exceeded.
<
Nota 4: These specifications apply over the absolute maximum operating temperature range unless otherwise noted.
Typical Performance Characteristics
Supply' Current vs ISET
lk
!...
z
W
a:
.ii
..
:s
:;:
:50:
0:
::>
u
t
i
120
100
:;
80
'">"'"5
>-
10
160
140
co
w
co
..
I-
0:
Open Loop Voltage Gain vs
ISET
z
.!
::>
u
I-
.
·10
100
0.1
iJ:
60
40
~
Vs = =15V
TA=25°C
20
'"
o
1.0
10
100
10,
ISET'(pAI
.
100
!
e
l-
::>
..
~
0:
.~
1M
0:
'"'"g:
'" 10Uk
I:i
i
'"z
~
0.1
...
0.01
z
ffi -
e
z
;;
60
60
~
20
:.!
10k
r-..
70
'30
:E
co
90
80
....
0:
:;:
0.001
"
40
VS=±15V
TA=25°C
10
.u
'--.w..l.J.LIIIl..~J....L.WIlI.....:"""'........
0.1
10
ISET wAI
100
Phase Margin vs ISET
10M
I
10,
ISET wAI
Gain Bandwidth Product vs
.ISET
10
]
0.1
100
ISET wAI
Slew Rate vs ISET
10
100
ISET wAI
9-77
I\)
~
en
r-
"-
s:
W
~
±0.7
Input Bias Cu rrent vs ISET
s:
en
LM146
MIN
VCM = OV, RS::S; SO n,
TA=25°C
100
=±i .5V, ISET =10 IlA)
CONDITIONS
Input Offset Voltage
50
~
en
"r-
100
0.1
10
ISET(PAI
100
Typical Performance Characteristics
Oi 120
:!!.
c
;;; 0.9
.! 0.1
w
~
c
...
E
l!!
~
100
z
c
10
IE:
co . 0.7
>
....
0.1
0.5
80 1-t-++ltItll--+++-fttHl-t-+H!I-H!
~
OA
i5rz:
60
"::II!
40
c
20
w
c
D.l
0.2
0.1
z
,VS'·,&V
T'A" 25°C
:IE
:IE
c
u
0
0.1
10
40 1-t-++t+ItlI--++tIfttHl-t-+H!I-H!
o
100
10
0.1
..
18
16
14
12
zco
crz:
10
~
...>
100
1
e
12
rz:
10
~
=
c.
co
=
c
~
...
U
.
0
8
10 12
14
TA=2S0C
'SET"10.A
0
SUPPLY VOLTAGE ('VI
...zw
oS
IE:
IE:
E
4
E
i
....
o
-8& -35 -1& S
2S 4& 8& 8& 1,0& 12&;
TEMPERATURE (OCI
Supply Current
Temperature
l!!
vs
8
~
~SET".A
:::>
u
::;
.
I:
3
0.1
:::>
VS··1SV
1
lSEr""Ollf~
o
-5!i -35-1&
15
='SET"O.A
i
7
&
10
-&
INPUT COMMON-MOOE VOLTAGE (VI
10
•
:::>
...u
c,
ISET" I .A
18
10
C
ii
14
Input Offset Current vs
Temperature
VS"'&V
ISET"'hA
10 12
2, .
vS' .ISV
TA _2&OC
0.1
-15 -10
SUPPLY VOLTAGE ('VI
Input Bias Current vs
Temperature
...
!!
0
16
ISET" O.hA
~
!!
0
'SET' I.A
10
IE:
...=>
TA"2&OC
'SET" 10.A
RL =10H!
30
20
10
100
Input Bias Current vs
Input Common-Mode
Voltage
~
c
i
10
'SET(PAI
w
100
90
~ 80
70
iii
IE:
rz: 80
=
u
&0
~ 40
0.1
'SET"O.A
~
w
co
...
oL-J..J...J.JllIIL......J....u..wuI........i:"""'......u
100
Input Voltage Range vs
Supply Voltage
14
vs , .,5V
1-t+tlt:IIlI-++tIft1t1I-TA =2&° C
ISET (PAl
Output Voltage Swing vs
Supply Voltage
!w
20 I-H+H-IHt-f-+1H+flft-
Vs= ±15V
TA' 25°C
ISET (pAl
~
Power Supply Rejection
Ratio vs ISET
Common-Mode Rejection
.Ratio vs ISET
Input Offset Voltage VI ISET
~c
(Continued)
5 25 4&. 1& 15 IDS 12S
TEMPERATURE rCI .
9-78
VS" .,SV
0.01
-&5 -3& -1& & 2& 4& 8& IS 10& 12&
TEMPERATURE lOCI
Typical Performance Characteristics
.
.
...
".
"
z
140
!
'-ISET = I pA TO 10pA
120
G
:::>
;;:
w
~
>
60
9
40
~
20
"
""g:
100
aD
...
."
~
w
~
>
w
Ci
z
~
i!:
'"
10 5
:;;"
104
,]
C
ISET= IOpA
FF
ISET= I"A
~~
~ ISET = 0.1 "A
1
0,1
.'"
ISET=I"A- t--
z
..
FF
ISET-l0"A- t--
106
I-
"
3i
w
I-
~
ISET = 0.1 "A t--
1
0.01
;;:
,Vs = ±15V
o
-55 -35 -15
~
Slew Rate vs
Temperature
Gain Bandwidth Product
vs Temperature
Open Loop Voltage Gain
vs Temperature
;;!.
(Continued)
10 3
-55 -35 -15
5 25 45 65 85 105 125
Input Noise Voltage vs
Frequency
Input Noise Current vs
Frequency
110
100
90
80
~
70
60
50 ~
40
100..
3D
20
Vs = ±15V
10
TA = 25'C
11111111
r-
IS~T ~ 121~~1
:§.
I::;
IS~T ~ 151!~1
'"'"
B
ISET= 10pA
.
ISET= 2o"A
ii!
100
Ik
Powe,r Supply Rejection
Ratio vs Frequency
120 r----.--,----r--r--,----.
w
Z
I-
0.4
i!:
1---+-.3k-+-'~I--_+--;
il:
ill
ffi
.~
0.2
10k
80
::;'"
ISET= 10pAISET=SpA I
-I A SIE~III~III _
~
0.6
I-.,.........~+-+-+--l
~
f\:SET = 20 "A
0.8
Ci
~ 100
."'"
1.2
11111111
o
10
~
ISET-l pA
10
FREQUENCY (Hzl
100
lk
20 .
, 0 '-'--'-_"'---L_..l----l_..3J
10k
10
1
FREQUENCY (Hzl
Voltage Follower Transient
Responfe
20
..
..~~
1 1
12
1 1
~
z
"
-8
-12
1
I
II
-4
S
oS
TA =~5'~L
INPUT
w
>
ISET =,lo"A
Vs = ±15V
I I
50
I
l-
ii!
I-
1
"
-50
50
S
oS
\
l-
ii! -50
i!:
-16
~
I
:::>
\ 1
1
\OUTPUT
---
\
ISET= 10"A
J--- Vs = ±15V
I--
TA = 2S'C
CL = 100 pF
RL=10kn
-20
100
200
100
300
TIME,",)
TIME (",I
Transient Response Test Circuit
9-79
Ik
10k
FREQUENCY (Hz)
Voltage Follower Pulse
Response
16
1
TEMPERATURE ('C)
Vs = ±15V
TA = 25'C
'IA
1
·VS·±15V
1 1
0.001
-55 -35 -15 5 25 45 65 85 105 125
5 25 45, 65 85 105 125
TEMPERATURE ('CI
1
'I'
Vs = +15V
TEMPERATURE ('CI
1
lOOk
1M
Application Hints
Avoid reversing the power supply polarity, the device
will fail.
Common-ModI! Input Voltage: The negative commonmode'voltage limit is one diode drop above the negative
sup'ply voltage_ Exceeding this limit on either input will
result in an output phase reversal. The positive commonmode limit is typ'icallY 1V below the positive supply
voltage. No output phase reversal will occur if this limit
is exce~ded by either input.
"Output Voltage' Swing vs ISET: For a desired output
voltage swing the value of the minimum load depends on
the' positive and negative output curent capability of the
op amp. The maximum available positive output current,
IICL+), of the device increases with ISET whereas the
negative output current IICL-) is independent of ISET.
Figure 1 illustrates the above.
28
C
oS
24
LM146 Typical Performance Summary: The LM146
typical behavior is shown in Figure 3. The device is fully
predictable. As the set current, ISET, increases, the
speed, the bias current, and the supply' current increase
while the noise power decreases proportionally and the
Vos remains constant. The usable GBW range of the op
, amp is 10 kHz to 3.5-4 MHz.
10M
i
f-+- -CURRENT LIMIT (lCL_I-1-
...
1M
Ii
co
tOOll
ii
OA
20
~,
1&
~
12
IE
+CURRENT LIMIT (levi
I-:p.-I-
....
1-'
~.
i
&I
i:
~
''C
co
~
i:l
Isolation Between Amplifiers: The LM 146 die IS ISOthermally layed out such tllat crosstalk between all 4
amplifi!1rs is in excess of':"'105 dB (DC). Optimum
isolation (better than -110 dB) occurs between amplifiers A and D, Band C; that is; if amplifier A dissipates
power on its output stage" amplifier D is the one which
will be, affected the least, and vice versa. Same argument
holds for amplifiers Band C.
• .14
l:
i
!:
'1111<
U
VS· t15V
o
TA -2S'C
o
SUPPlVCuaR£1lTI#AJ
10
I
U
ISET"'AI
FIGURE 1_ Output Current Limit vs iSET
Input Capacitance: The input capacitance, CIN, of the
LM146 is approximately 2 pF; any stray capacitance,
CS, (due to external circuit circuit layout) will add to
CIN. When resistive or active feedback is applied, an
additional pole is added to the open loop frequency
response of the device. For instance with resistive feedback (Figure 2), this pole occurs at 1/2Tr (R1I1R2)
(CIN + CS). Make sure that this pole occurs at least
2 octaves beyond the expected -3 dB frequency corner
of the closed loop gain of the amplifier;, if not, place a
lead capacitor in the feedback such that the time constant of this capacitor and the resistance it parallels is
equal to the, RI(CS + CIN), where RI is the input resistance of the circuit.
I t 111111
I
1 11111111
"
•
"n!J,AI
I "ItI I •;'2(":)
(1S12
~L~
5
18
FIGURE 3. LM146 Typical Characteristics
Low Power Supply Operation: The quad op amp operates down 'to ±1.3V supply. Also, since the internal
, . circuitry is biased through programmable current sources,
no degradation of the device speed will occur_
Speed vs Power Consumption: t.M146 vs LM4250
(single programmable). Through Figure 4, we observe
that the LM146's power consumption has been optimized for GBW products above 200 kHz, whereas the
LM4250 will reac;h a GBW of no more than 300 k'Hz, for
GBW products below 200 kHz, the LM4250 will consume less.
!i
OA
FIGURE 2
::
Ii
Temperature ,Effect on the GBW: The GBW (gain
bandwidth product), of the LM146 is directly proportional to ISET and inversely proportional t~ the absolute temperature. When using resistor~ to set the
bias current, ISET, of the device, the GBW product will
decrease with increasin,g temperature. Compensation
can be provided by creating an ISET current directly
proportional to temperature (see typical applications).
0.04
a
'<
!
OJlO4
SUPPL V CURRENT "'AI
FIGURE 4_ LM146 vs LM4250
9-80
Typical Applications
Dual Supply or Negative Supply Biasing
Single (Positive) Supply Biasing
v-
v+ 0--11----1
v+
RSET
SET 9
SET
RSET
LM346
LM34&
V+ -O.6V
ISET = --:R::-S-E-T-
Current Source Biasing
with Temperature Compensation
Biasing all 4 Amplifiers
with Single Current Source
":"
LM334Z
v+
v+
RSET
-
ISET
8 SET
SET
67.7mV
ISET= - - RSET
•
RI
'SET I
_8
R2
-
LM346
'SET 2
LM34&
ISET1
R2
- - = ~, ISET1 + ISET2
ISET2
Rl
The LM334 provides an ISET directly proportional to
absolute temperature. This cancels the slight GBW product
temperature coefficient of the LM346.
9·81
•
67.7 mV
=- - RSET
For 'SET1 = ISET2 resistors Rl and R2 are not required
if a slight error between the 2 set currents can be tolerated.
If not, then use Rl = R2 to create a 100'mV drop across
these resistors.
Active Filters Applications
Basic (Non-I nverting "State Variable") Active Filter Building Block
IODle
10k
•
The LM146 quad programmable op amp is especially suited for active filters because of their adequate GBW product' and low power
consump~ion.
Circuit synthesis equations (for circuit analysis equations. consult with the AF100 and LMI48 data sheed.
Need to know desired:
•
f 0 = center frequency measured at the BP output
00 = quality factor measured at the BP output
Ho = gain at the output of interest (BP or HP 'or LP or all of them)
Relation between different gains: Ho(BP)
5.033 x 10-2
(sec)
fo
•
R xC=
•
For BP output: RQ = (
~
0.316 x 00 x Ho(LP); Ho(LP) = 10 x Ho(HP)'
3.478 00 - Ho(BP)'
105 '
-1
'Ho(BP)
)
105 x 3.478 x 00
. R
_,
• IN -
00
(_3._4_78_
_ -1)
Ho(BP)
+ 10-5
RQ
.2..
1.1
---1
1.1 x 105
RQ = 3.478 Qo (1.1 _ Ho(HP)) - Ho(HP)
R
IN
= Ho(HP)
1
_+10-5
RQ
..
For HP output:
•
11
11 x 105
Ho(LP) - 1
For LP output: AQ = 3.47800 (11 _ Ho(LP)) _ Ho(LP) ; RIN = _1_+ 10-5
. Note. All resistor values are given in ohms,
RQ
..
For BR (notch) output: Use the 4th amplifier of the LM146 to sum the LP and HP outp4ts of the basic filter.
LP OO..JINI.-.....
HP o--,\Mr-'
RF
fnotch = ~L Ho(LP). Ho(BR) f»
Determine RF according to the desired gains: Ho(BR) f«
•
RF
fnotch = RH Ho(HP)
Where to use amplifier C: Examine the above gain relations and determine the dynamics of the filter. Do not allow slew rate limiting
in any output (VHP. VBP. VLP). that is:
VIN(peak)
<
63.66 x 103 x ISET x __
1_ (Volts)
10jlA fo x Ho
- '
\
If necessary. use amplifier C. biased at higher ISET. 'where you get the largest output swing.
Deviation from Theoretical Predictions: ,Due to the finite GBW products of the op amps the f o • 00 will be slightly different from the
theoretical predictions.
fo '
freal ~ ~ • Qreal ~
1+-GBW
9·82
Active Filters Applications
(Continued)
A Simple-to-Design BP, LP Filter Building Block
3.9k
3.9k
•
If resistive biasing is used to set the LM346 performance, the 0 0 of this filter building block is nearly insensitive to the op amp's GBW
product temperature drift; it has also better noise performance than the state variable filter.
Circuit Synthesis Equations
HoIBP) = QoHo{LP); R xC = 0.159 ; RQ =
fa
•
Co x R; RIN = ~= _R__
Ho(BP)
Ho(LP)
For the eventual use of amplifier C, see comments on the previous page ..
A 3-Amplifier NotcJ'! Filter (or Elliptic Filter Building Block)
3.9k
3.9k
>~HOVOUT (8R)
Circuit Synthesis Equations
0.159xf
0.159
.
R-xC= - - ;RQ=OaxR;RIN=
2
a
fa
C'. x f notch
R
Ho(BR) If«
•
fnotch = RIN Ho{BR) If»
C·
fnotch
C
For nothing but a notch output: RIN = R, C' = C ..
9-83
Active Filters Applications
(Continued)
Capacitorless Active Filters (Basic Circuit)
R3
R2
RID
RD
BR
RI
R7
•
SDOk
•
This is a BP, LP, BR filter. The filter characteristics are created by using the tunable frequency response of the' LM346.
(
)
63.66 x 103
ISET b.A)
limitations: 00 < 10, fo x 00 < '.5 MHz, output voltage should not exceed Vpeak out $.
fo
x
•
.
.
R6+R5
Design equations: a = ~' b
--;o;;p;-
Ho( LP)
=:
' R2
= Ri+R2'
c
=
R3
R3 + R4 ' d
=
R7
RS + R7 ' e =
R10
Fiii+"R1ii'
= fu
fb
J 8""
Ho(BP) "e x c,
,00 = ,j;';b"
fo(BR) = fo(BP) (1
-i-) ~
fo(BP)
(e«
1) provided that d = Ho(BP) x e, Ho(BR) =
:~O.
•
Advantage: f o • 00. Ho can be independently adjusted; that is, the filter is extremely easy to tune.
•
Tuning procedure (ex. BP tuning)
1.
2.
3.
4.
fo(BP)
(V)
Pick up a convenient value for b; (b < 1)
Adjust 00 through R5
Adjust Ho(BP) through R4
Adjust fo through RSET
A 4th Order Butterworth Low Pass Capacitorless Filter
':'
R4
VIN
10k
R3
51
':'
VOUT
R2
51
Ex: fc = 20 kHz, Ho (gain of the filter) = 1, 001 = 0.541, 002 = 1.306.
•
Since for this filter the GBW product of all 4 amplifiers has been designed to be the same (-1 MHz) only one' current source can
be used to bias the circuit. Fine tuning can be further accomplished through Rb.
9-84
Miscellaneous Applications
A Unity Gain Follower
with Bias Current Reduction
Circuit Shutdown
VIN 0-....- - - - ;
VOUT
5V
b
ON
OFF OV
ZOk
•
For better performance, use a matched
NPN pair.
•
By pulling the SET pin(s) to V- the op amp(s) shuts down and its
output goes to a high impedance state. According to this property,
the LM346 can be used as a very low speed analog switch.
Voice Activated Switch and Amplifier
V+
v+
D.1.uF
MICIN~o-1 ~t---~~
CONTROL
lOOk
9·85
Miscellaneous Applications
(Continued)
X10 Micropower Instrumentation Amplifier with Buffered Input Guarding
R3
R4
25k
25k
R
m
Rl
5.55k
R2
Z5k
R
Z5k
16
R3
Z5k
D'I"~
V-=-1.5V
9-86
R3
Z5k
•
CMRR: 100 dB (typ)
•
Power dissipation: 0.4 mW
•
All resistors part of RA201 array
Section 10
Resistor Arrays
~National
Resistor Arrays
~ Semiconductor
RA201 Precision Instrumentation
Amplifier Resistor Network
General Description
The RA201 is a family of precision instrumentation
amplifier networks. This device, when combined with
3 operational amplifiers, provides a precision instru·
mentation amplifier with common·mode rejection up to
100 dB. All gain setting resistors are provided within
the device. This feature assures excellent thermal tracking
and thermal matching of all resistors. This network is
manufactured using a high stability thin·film technology.
Thin·film resistors provide tracking temperature coef·
ficients of better than 5 ppm/DC. The thin-film resistors
are laser trimmed to guarantee resistor matching to
0.05% for the RA201·2, and 0.1% for the RA201·1.
Other applications include process control interfacing
and precision decade dividers.
Features
• Gain programmable
• Matching accuracies to 0.05%.
• Matching temperature coefficient to 5 ppmtC .
• Absolute temperature coefficient to 80 ppmtC
• Close thermal proximity of all resistors
• Standard dual·in·line package
•
Low·cost
Connection Diagram
Dual-In-Line Package
16
14
15
13
R9
"
11
"
10
'"
'13
R4
R6
1,
R1 = 252.525 .. n
R2 = 2.777 ... kn
R3 = 25k
R4 = 25k
R5 = 25k
R6 = 6.25k
R7 = 25k
RS = 252.525 ... n
R9 = 2.777 ... kn
R10 = 25k
Rll = 251<
R12=25k
R13 = 6.25k
R14 = 25k
~
'"
'10
RJ
R5
R2
RI
3
2
1
5
4
rI
,
6
18
TOPVIEW
Order Number RA201D
Sea NS Package D16C
R3:R2 = 9:1
R3:Rl = 99:1
R311R2 = 2.50k
R31lRl = 250.qr!
R51lR6 ,; 5.0k
Order Number RA201N
Sea NS Package N 16A
Typical Application
RJ
R2
2 2.171k
•
Z5k
3
RI
1 252.6
,-
INVERTING
3
INPUT
S
R4
lHOD44
8
Z5k
8
R8
6.25k
+
,
25k
8
RS
25k
LHDD44
RU
~
8
25k
20k
-
3
3
NON·INVERTING
INPUT
2
R8
t8 252.5
+
R10
R9
15 2.711k
14
'"
'"'"
"
'-
8
OUTPUT
+
R14
R13
6.25k
11
Overall
Gain
Input Stage
Gain
Output Stage
Xl
X2
X5
Xl0
X20
X50
Xl00
X200
X500
X995
Xl
Xl
Xl
Xl0
Xl0
Xl0
Xl00
Xl00
Xl00
X199
Xl
X2
X5
Xl
X2
X5
Xl
X2
X5
X5
Gain
Jumper Pins
on RA201
R'
,
REFErENCE
5107,12tol0
6to 7, 11 to 10
2 to 15
2 to 15, 5 to 7,12 to
2to 15,6t07, 11 to
1 to 16
1 to 16,5 to 7, 12to
1 to 16,6t07, 11 to
1 to 14,6t07, 11 to
10
Precision Instrumentation Amplifier
13
10·1
10
10
10
10
10
·~
Absolute Maxi,mum Ratings
«
a:
"
"'.'
Rated Voltage Between Sections
Rated Voltage Across Resistors
Package Power Dissipation at 2S0c (See Curve)
Individual Resistor Power at 2SOC
Operating Temperature Range
RA201-1N, RA201-2N
RA201-lD, RA201-2D
StorageTempe~ature Range.
. Lead Temperature (Soldering, 10 seconds)
Electrical Characteristics
200V
(Note 1)
2.0W
0.2SW'
-2S0C to +BSoC
-5SoC to +12SoC
-SSoC to +lS0°C
300°C
T A = .2SoC(Note 2)
CONDITIONS;
RESISTORS TESTED
PARAMETER
Input Stage x10
TVP
RA201-2
MAX
RA201-1
MAX
R2:R3
1:9
±0.05
±O~ 1
%
(R2I1R9):(R3fIR10)
1:9
±0.05
±0.1
%
R1:R3
1:99
±1
±1
(RBIIRl ):(R31IRl0)
1:99
±1
±1
%
%
R7:RS
1:1
±0.05
±0.1
R14:R'12
1:1
±0.05
±0.\1
"
Input Stage x100
Output Stage x,l
Outp!it' S~age ~2
Output Stage x5
UNITS
(R4I1R5):R,7
1:2
±0.05
±0.1
(R12I1Rll):·R14
1:2
±0.05
±0.1
%
%
%
%
(R6iIR5.):,Ri'
1:5
±0.05
±0.1
(R12I1R13):R14
1:5
±9.05
:to. 1
%
%
Output Stage CMRR
(R7:R5):(R14:R12), (Note 3)
1:1
±O.OS
±0.1
%
Absolute Tolerance
R3
±5
±5
2Skn
Absolute Tempco
%
ppm/oC
80
Note 1: Rated voltage is limited by the individual resistor power rating of 0.25W; For example, a 25k resistor could withstand a maximum of
V = -1(0.25) (25,000) = 79V. This rating may need to be reduced to be consistent with maximum package power if several resistors are dissipating
power simultaneously.
"
,
Note 2: Resistor ratios shown apply at TA = 25°C; for TMIN S T AS TMAX the ratio tolerances are double the specifica60ns shown.
Note 3: This test guarantees the CMRR contributed by resistance mismatch. In low gain applications, all 3 amplifiers contribute strongly to the
overall CMRR. In high gain applications, the degradation due to resistor mismatch and output stage CMRR are divided by the gain of the input
stage.
I.
..
,:
.. '
...
'..
!
l , . ,
Typical Performance Gharacteristics
Power Derating
1.
'~2.0 I-+-+-h!----!----!----f--f---H
~
':l:
~
'1.5
HHHH-'+-+--+--+--+--l
1\
:::
1.0
I---'HHH--i--i'ri--i--i-l
I\,
i"
0.5
II---'HHHHH--i-',*+-l
~
I
-50
I\,
-10
30
70
110
TA - AMBIENT TEMPERATURE reI
10-2
150
::JJ
»
9
Applications Information
N
15V
LHOD70
I
-1D,OOV
'="
•
3
02
2
2.7171k
5
6
R4
06
6.25k
m
~
10V
I
03
01
16
252.52
03
25k
OS
25k
01
25k
06
252.5
010
25k
012
25k
01.
15
*
09
Oil
25k
6.25k
12
II
m
,
1
m
'~~~~~o--....,r--H~ . . >-~~-oDVto1DV
~
1.61V . ._.J\J""~"""
9
~
013
5k
AOII06
,'3
"
10
OVT05V}
INPUT
ov TO tV
1
J+...
1VT05V
OUTPUT~
OVTO 10V
RA201 Process Control Interface No.1
.f:
4
OZ
2.7171k
5~
6
Equivalent Circuit
I
15V
00
Z5k
06
6.25k
,.
1
LHOO1D
16
01
252.52
03
25k
OS
25k
0'
2S2.5
010
25k
m
01
13
OIl
25k
013
6.25k
12
II
01.
Z5k
01
Z5k
'="
::>-..--0() ii~~~Jf 10V
9
9.3750
15k
(R411R5 + R211R31
10
1
IVT05V
IN PUT
10V
m
012
15
09
2.1717k
10
013
6.25k
2.1117k
....
,
OUTPUT
37.5k
'010 + RIIIIR12)
to.
C
...
-tOY YO IOV
OUTPUT
RA201 Process Control Intorfaco No.2
Equivalent Circuit
10·3
,...
~
Applications Information
(Continued)
--'lM.............-
16
A'-
A'
25Z.52
A'
25k
25k
25k
252.5
AID
,Z5k
A12
25k
A14
25k
..
15
All
A'
A'
5k
R411R6
, IV TO IV
~~
~
A"
25k
6.25~
12
11
2.7777k
14
13
ID
DYTO IOV
0-+----------------...1
RIN=10.4157k
INPUT
IVT05V
L-----------------------------~------------OOU~UT
ROUT-Uk
Equivalent Circuit
RA201 Process Control Interface No.3
V,N
•
A'
25k
,
.-----4_---<) v,
A'
A'
252.52 ••• k
2.777 ..• k
1"
'::'
51 closed-:-Vo= VIN/l0Q
52 closed - Va = VIN/l0
Precision Decade Divider
','.
1.6&lV~
-
Section 11
Active Filters
III
"
l>
~National
Active Filters
~ Semiconductor
AF100 Universal Active Filter
general description
features
The AF100 state variable active filter is a general second
order lumped RC network. Only four external resistors
program the AF100 for specific second order functions.
Lowpass, highpass, and bandpass functions are available
simultaneously at separate outputs. Notch and all pass
functions are available by summing the outputs in the
uncommitted output summing ampl ifier. Higher order
systems are realized by cascading AF100 active filters'
with appropriate programming resistors.
• Military or commercial specifications
• Independent Q, frequency, gain adjustments
• Low sensitivity to external component variation
• Separate lowpass, highpass, bandpass outputs
• Inputs may be differential, inverting, or non·inverting
• Allpass and notch outputs may be formed using
uncommitted amplifier
• Operates to 10k Hz
• Q range to 500
±5V to ±lBV
• Power supply range'
±1% unadjusted
• Frequency accuracy
• Q frequency product::; 50,000
Any of the classical filter configurations, such as Butterworth, Bessel, Cauer, and Chebyshev can be formed.
connection diagrams
Dual-In-Line Package
NO
PIN
NO
PIN
INT 1
BANDPASS
OUTPUT
-V
Metal Can Package
AMP
AMP
OUTPUT -INPUT
GNO
INT1
AMP
OUTPUT
INPUT2
INn
INPUT
INPUT HIGHPASS
OUTPUT
+V
LOWPASS
AMP
OUTPUT + INPUT
INT 2
NO
PIN
TOP VIEW
Order Numbe' AF100HY
See rils Package HY13A
Order Number AF10DHY
See NS Package ,H 12A
11-1
TOP VIEW
:]
o
o
o
o
,..
u.
c:(
absolute maximum ratings
±isv
Supply Voltage
Power Dissipation
Operating Temperature
AF100·1CJ/AF100·2CJ/AF100·1CG/AF100·2CG -25°C to +S5°C
-55°C to +125°C
AF100·1G, AF100·2G
900 mW/Package (500 mW/Amp)
±36V
Differential Input Voltage
Output Short Circuit Duration (Note 1)
Lead Temperature (Soldering, 10 seconds)
Storage Temperature
Infinite
300°C
electrical characteristics
AF100·1G, AF100·2G,
AF100·1CG, AF100·2CG
AF100·1CJ, AF100·2CJ
(Complete Active Filter) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency Range
fc x Q
:s: 50,000
10k
Hz
Q Range
fc x Q:S: 50,000
500
Hz/Hz
±2.5
%
±1.0
%
fo Accuracy
AF100·l, AF100·1C
fc x Q:S: 10,000, T A
AF100·2, AF100·2C
fc x Q:S: 10,000, T A
= 25°C
= 25°C
fc x Q:S: 10,000, T A
= 25°C
f 0 Temperature Coefficient
±50
±150
ppmi"C
I
Q Accuracy
±7,5
Q Temperature Coefficient
Power Supply Current
Vs
= ±15V
electrical characteristics
±300
±750
2,5
4,5
%
ppmi"C
mA
(Internal Op Amp) (Note 3)
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
1.0
6.0
mV
I nput Offset Current
4
50
nA
Input Bias Current
30
200
Input Resistance
2,5
Input Offset Voltage
Rs:S: 10 kD
Large Signal Voltage Gain
RL
?: 2k
RL
RL
160
V/mV
= ±10V
V OUT
Output Voltage Swing
25
nA
MD
= 10 kD
= 2 kD
Input Voltage Range
±12
±14
V
±10
±13
V
V
±1~
Common Mode Refection Ratio
Rs:S:
io kD
70
90
dB
Supply Voltage Rejection Ratio
Rs:S: 10 kD
77
96
dB
Output Short Circuit Current
25
mA
Slew Rate (Unity Gain)
0.6
V/l1s
Small Signal Bandwidth
1
Phase Margin
60
MHz
Degrees
Note 1: Any of the amplifierscan be shorted to ground indefinitely, however more than one should not be simultaneously shorted as the maximum
junction temperature will be exceeded.
Not. 2: Specificationsapply for Vs = ±15V, over _25°C to +S5°C for-the AF100·l C and AF100·2C and over _55°C to +125°C for the AF100·1
and AF100-2, unless otherwise specified.
Note 3: Specifications apply for
Vs = ±15V, TA
=<
25°C.
11-2
»."
....
applications information
HIGHPASS
BANDPASS
lOWPASS AMP IN -
o
o
..,
r
IN2o-T-~~AA~4---4-------r------t--~--~
.'>---:--0
+
IN Io-...........----~AA,.....---------'
AMPIN+
FIGURE 1. AF100 Schematic
CIRCUIT DESCRIPTION AND OPERATION
Using proper input and output connections the circuit
can also be used to generate the transfer functions for a
notch and all pass fi,lter.
A schematic of the AF100 is shown in Figure 1.
Amplifier A 1 is a summing amplifier with inputs from
integrator A2 to the non·inverting input and integrator
A3 to the inverting input. Amplifier A4 is an uncommitted
amplifier.
In the transfer function for a notch function a2 becomes
zero, a1 equals 1, and a3 equals Wz 2. The transfer
function becomes:
By adding external resistors the circuit can be used to
generate the second order system
(notch)
The denominator coefficients determine the complex
pole pair location and the quality of the poles where
In the allpass transfer function a1 = 1, a2 = -wo/O and
a3 = w0 2 The transfer function becomes:
Wo = y'b, = the radian center frequency
Q
s2 _ Wo S + w02
Q
=Wo =the quality of the complex pole pair
T{s)=-----
{all pass)
b2
If the output is taken from the output of A 1, numerator
coefficients a1 and a2 equal zero, and the transfer func·
tion becomes:
COMMON CONFIGURATIONS
The specific, transfer functions ,for some of the most
useful circuit configurations using the AF100 are ill·
ustrated in Figures 2 through 8. Also included are the
gain equations for each transfer function in the fre·
quency band of interest, the Q equation, center fre'·
quency equation and the Q, determining resistor
equation. '
(highpass)
S2
Wo
+ - S + w0 2
Q
If the output is taken from the output of A2, numerator
coefficients a1 and a3 equal zero and the transfer function becomes:
'
T{s) = ___a_2_s___
lOOk
.
,
(bandpass)
If the output is taken from the output of A3, numerator
coefficients a3 and a2 equal ~ero and the transfer func~n~~~:
T{s) = _ _ _a_1_ __
looapF
RF ,-
lOOk
•
RO"
"
HIGHPASS
(lowpass)
"
BANDPASS
*htelllllcOlllpOllents
FIGURE 2. Non·inverting Input (a
See Q Tuning Section)
11·3
> aMIN,
"
LOWPASS.
o
o
inf~rmation
applications
u:
1.1 +--
Jo.l~
0=
W,
(
104
1.1+-RIN2
lOS
RO=--~O-------------
RO=
Jo.l~
w,
)'
[1+~+~1
R'N
0
1.,... R'N2
-,'
10
.
4
:w=wo
=VO.l wl.w 2
( 1.1+-,
10") -1
Jo,l~
R'N
w,
11·5
(1.1+~)
RIN2
_
1 ,_ lOS
RIN1
"
lOWPA5S
8,...
applications information (con't)
u.
lOOk
~
applications information (con't)
RC tuning for fo
is required. Using external capacitors allows the user to
go as low in frequency as he desires. "T" tuning and
external capacitors 'can be used together.
0.05033
R - ------,:f - fa (e + 1 x 10-9)
Two resistor tu'ning for ;200 Hz to 10 kHz
Rf =
50.33 x 106
fa
o
o
< 200 Hz
n
R,
R,
I"
AF1DDJ
AF100J
I'
I"
R,
FIGURE 11. Low Frequency RC Tuning
FIGURE 9. Resistive Tuning
G RAP.H A. Resistive Tuning
Q TUNING
1000
To tune the Q of an AF100 requires one resistor from
pins 1 or 2 to ground. The value of the Q tuning resistor
depends on the input connection and input resistance
as well as the value of the Q. The Q of the unit is
inversely proportional to resistance to ground at pin 1
and directly proportional to resistance to ground from
pin 2.
C!
'"
w
u
100
'"'"
I;;
ilia:
~
a:
10
lk
10k
lOOk
GRAPH C. aMIN.
Non·lnverting Input-
fe-FREQUENCY (H,)
"T" resistive tuning for fo
R2
R,=--'--
Rf
-
2R,
< 200 Hz
R
t
< RF
;2
AF10nJ
Q
For Q> Q M1N in non-inverting mode:
RS
RQ=----_=_
105
3.48Q-1 - -
FIGURE 10. T Tuning
R'N
GRAPH B. "T" Tuning
lOOk
9:w
u
Rw
o--'lM......-.:..j+
10k
z
AFIDD
'"
I
I
.l
lk
Ro
100 L-Ll.UJ.lllL.-L.LULlWL-J....L.lllJ.llJ
10
100
lk
FIGURE 12. a Tuning for a
Non-tnverting Input· .
FREQUENCY (H,)
11-7
>
aMIN'
.
o
o
'!""!'
applications information (con't)
LL
GRAPH D. 0 > 0MIN.
Non-Inverting Input
GRAPH F. a Tuning.
look_
:1.
lOOk.
Rn
ZRn
IZ
.".
.".
VIZ (PSEUDO GROUND)
FIGURE 18. Single PQwer Supply Connection Using
Uncommitted Amplifier to Split:Supply
. '"
FIGURE 19. Single Power Supply
Connection Using Resistive Dividers'
..'"
11
..
11
.
lOOk
..'"
1.04511:
V-
Performana
,O.f dB npple passband ,
0.1 dB no1Chwidth .. 100Hl
40dBnotchwidth-U5HI
'-,
4th Order, 1010 Hz Notch
r---.
-10
'"
:s
-20
~
-30
/'
\
/
~
I
-40
-50
-60
; ;
960
980
1000
1020
1040
FREQUENCY (Hz)
FIGURE 20. 1010 Hz Notch-Telephone Holding Tone Reject Filter
FILTER DESIGN
Since most filter tables 'are in terms of a normalized
lowpass prototv'pe~ 'the _filter to be designed is usually
reduced to
lowpass' prototype: After the lowpass
transfer function is found, it is transformed to obtain the
transfer function for the actual filter desired. Graph I
shows the lowpass amplitude response which can be
defined by four 'quantities.
11-10
»
"T1
applications information (con't)
GRAPH I. Lowpass Prototype Response
=
:s
GRAPH L. Notch Response
t=~~~
1\
AMAX
'"~
I
-+-+-il-r-- +--Ie
Is
LOG, FREQUENCY
Normalized Lowpass Transformed To Un-Normalized
Lowpass
AMAX = the maximum peak to peak ripple in the
passband.
The normalized lowpass filter has the passband edge
normalized to unity., The un-normalized lowpass filter
instead has the passband edge at f e . The normalized and
un-normalized lowpass filters are related by the transformation s = sW c ' This transforms the normalized
passband edge s = j to the un-normalized passband
edge s = jWe.
AMIN = the minimum attenuation in the stopband.
= the passband cutoff frequency.
fe
= the stopband start frequency.
fs
By defining these four quantities for the lowpass
prototype the normalized pole and zero locations and
the 0 (quality) of the poles can be determined from
tables or by computer programs.
To obtain the lowpass prototype for the highpass filter
(Graph J) AM AX and AMIN are the same as for the
lowpass case but fe = 1/f2 and fs = l/fj.
GRAPH J. Highpass Response
L
I
/
AMAX
AMIN
L \Ii
~,
The transformation that can be used for lowpass to
bandpass is 5 = (s2 + wo2 )/BWs where wo2 is the center
frequency of the desired bandpass filter and BW is the
ripple bandwidth.
f5 - f,
'fe = 1 fs = - f4 - f2
f3 = vf,f;; = ~
Normalized Lowpass Transformed To Un-Normalized
Bandstop (Or Notch)
i.e. geometric symrretry
fs - f, = A M1N , bandwidth
f4 - f2 = Ripple bandwidth
The bandstop filter has a reciprocal response to a
bandpass filter. Therefore a bandstop til ter can be
obtained by first transforming the lowpass prototype
to a high pass and then performing the bandpass
transformation.
GRAPH K. Bandpass Response
I
The transformation that can be used for lowpass to
highpass is 5 = we/so Since 5 is inversely proportional to
s, the low frequency and high frequency responses are
interchanged. The normalized lowpass 1/(52 + 5/0+1)
transforms to the un-normalized highpass
s2
Normalized Lowpass Transformed To Un-Normalized
Bandpass
I,
To obtain the lowpass prototype for a bandpass filter
(Graph K) AM AX and AMIN are the same as for the
lowpass case but
where
Normalized Lowpass Transformed To Un-Normalized
Highpass
SELECTION OF TRANSFER FUNCTION
1\
The selection of a function which approximates the
shape of the response desired is a complicated process.
Except in the simplest cases it requires the use of tables
,or computer programs. The form of the transfer function desired is in terms of the pole and zero locations.
The most common approximations found in tables are
Butterworth, Tschebycheff, Elliptic, and Bessel. The
decision as to which approximation to use is usually
a function of the requirements and system objectives.
Butterworth filters are the simplest but have the disadvantage of requiring high order transfer functions to
obtain sharp roll-offs.
To obtain the Ibwpass prototype for the notch filter
(Graph L) AMAX and AMIN are the same as for the
lowpass case and
fe= 1
where
11-11
.....
o
o
8
lL
."
......
applications information (con't)
o
3. In cascaded filters of more tban two sections the
first section should be the section with "0" closest
to 0.707 and then additional stages should be
added in order of least difference between first
stage a and their O.
1. The highest "0" pole pair should be paired with
the zero pair closest in frequency.
2. If highpass and lowpass stages are cascaded the
lowpass sections should be the higher fr¢quency
and hlghpass sections the lower frequency.
100k
3.9lk
Lowpass Elliptic Filter
Fe
=1
Fs = 1.3
A MAX
AMIN
= 0.1
dB
=40dB
6th Order Elliptic Filter
N=6
f o , = 1.0415
0, = 7.88
f z , = 1.329
(~)
fz/fo = 1.28
2
=
1
I
1.63
-6
f02
= 0.9165
O 2 = 1.79
f03
= 0.649
03
= 0.625
fZ2
= 1.664
fz/fo
= 1.82
(~r
= 3.30·
fZ3
= 4.1285
Iz/l o'
= 6.36
(~r
=
I
-12
-18
-2.
-30
40.5
-36
-42
-48
-54
(503.3)
RF3 = - - f03 X
0.01
Ie
0.1
10
FREQUENCY IkHzl
at 1000 Hz = Ie
RF , = 4B.3k
RF2 =
R F3
54.9k
= 71.6k
FIGURE 21. Lowpass Elliptic Filter Example
v.
500/1000 Hz Switchable
Butte~orth lowpass Filter
1DOk
INPUT
D--AJVV-.--'-i
+6
AF10QJ
IrTn
Tilnl
OUTPUT
217k
-6
"
-12
13
1\.1\.
iii -18
;
-24
1\
'\
~ -30
25.m.
-36
-42
-48
-54
100
1000
GIHI itdc "'-t13dB
Gamatl kHzI5DOHz"'10IlB
FREQUENCY (Hz)
FIGURE 22. Switchable Filter Example: 500 HZ/l000 Hz Butterworth Lowpass
11-13
10,000
o
o
o
u:
applications information (con't)
v.
V.
A(I}S-,2+R(1 }S+Z(I}1\2
1
1
0
0
(From Une 2, 1)
(From Une 2,2)
59,471339
60,533361
REAL POLE
COMPLEX POLE PAl RS
F
Q
56.93601 11.31813
63.228877 11.31813
1
2
FREQUENCY
40,000
45.000
50.000
55.000
56,000
57,000
58,000
58,200
58.400
58,600
58,800
59,000
59,200
59.400
59.600
59.800
60.00
60.200
60.400
NOR, GAIN (DB)
PHASE
.032
.060
.100
-.795
-2.298
-5.813
-12,748
-14,740
-17,032
-19.722
-22,983
-27.172
-33.235
-46,300
-42.909
-36,897
-35.567
-36.887
-42,757
347.69
342.20
330.70
290.54
270.61
245.51
220.19
215.54
211.06
206.76
202.61
198.60
194,72
190,94
7.24
3.60
360.00
356.41
352.81
DELAY
.002275
.004107
.. 009983
.046620
.063945
.072894
,065758
,063369
.060979
.058692
.056588
,054724
.053139
,051856
.050888
.050242
.049916
.049907
.050206
(From Unes 2.3 and 2.4)
(From Unes 2.5 and 2.6)
NOR. DELAY
FREQUENCY
NOR, GAIN (OBI
5.847169
8.749738
21.268142
99.324027
136,234562
155.299278
140.096912
' 135.006390
129.914831
125.043324
120,561087
116,589928
113.212012
110.478482
108.417405
107.040235
106.346516
106.326777
106.963750
60.600
60.800
61.000
61.200
61.400
61.600
61.800
62.000
63.000
64.000
65.000
66.000
67.000
70.000
75.000
80.000
85.000
90.000
-47,102
, -33,650
-27.577
-23.418
-20,198
-17.554
-15.308
-13.362
-6.557
-2.936
-1.215
-.463
-.138
.091
.085
.060
.043
.032
11·16
,
PHASE
DELAY
,050801
169.17
,051677
165.48
.052809
161.72
157,87
.054167
153,92
.055712
149,85
,057391
145,65
.059136
141.33
.060869
,.118.23 ' .065975
.059402
95.30
.045424
76.38
.032614
62.43
,023498
52.44
35.43
.010452
.004250'
23.44
17.80
.002310
14.50' ' ,001460
12.31
.001011
NOR, DELAY
108.232021
110.096278
112,508334
115.403169
118,694436
122,270086
125,989157
129.681062
140,559984
126,556312
96.774832
69.484716
50.062947
22.267368
9.054574
4.921727
3.110493
2.154297
l>
."
applications information (con't)
~
o
o
PROGRAM NO.4
DESIGN OF FIRST SECTION
)RUN
WHICH FILTERAF100-JORG?
?1.
WHAT TYPE OF FILTER SECTION? HIGHPASS-BANDPASS-LOWPASS-NOTCH-ALLPASS
? NOTCH
INPUT FC AND Q VALUES
?56.93601.11.31813 (FROMLlNES2.3AND2.4)
INPUT REAL POLE AND CAPACITOR VALUES IF NONE ENTER 0
?Q
INPUT ZERO LOCATIO~J
? 59.471339
(FROM LINE 2.1J
ARE TUNING INSTRUCTIONS REQUIRED?
? YES
TUNI NGI NSTRUCTION
PHASE SHIFT FROM INPUT TO PIN 13 SHOULD BE 180 DEG. AT 56.93601 HZ.
I F TUNING IS REQUI RED, RF2 FROM PINS 7 TO 13 SHOULD BE ADJUSTED.
PHASE SHIFT FROM INPUT TO PIN 13 SHOULD BE 135 DEG. AT 59.506798HZ.
OR 225 DEG. AT 54.476284 HZ.
IF TUNING IS REQUIRED RQ FROM 1 OR 2 TO GROUND SHOULD BE ADJUSTED
GAIN AT PIN 11 AT 59.471339 SHOULD BE 0 I F NOT
ADJUST RHP FROM PIN 3 TO 10 FOR NULL
FC= 56.93601
GAIN AT F» FC=
Q= 11.31813
.OODB
FUNCTION
R IN
F(H-3DB) = 59.506798
F(L-3DB) = 54.476284
CONNECTION
TO
FROM
INPUT
RQ
VALUE OF EXTERNAL
RESISTORS IN OHMS
100000.000
GND
2675.931
RFl
3
14
883960.996
RF2
7
13
883960.996
RLP
5
10
100000.000
RHP
3
10
10910.413
RG
10
11
357910.697
+V
4
-V
12
GND
9
GND
6
OUTPUT
PIN 11
11-17
oo
,...
applications information (con't)
U.
....o'TI
applications information (con't)
o
RHP
RHP
RLP
RLP
R,.
INPUT
O-"'VII'v-+-"'"I
R'
OUTPUT
RO
Q.ldBtrllldWldlh 15Hz
-J5dBbandwldlh 1.5 Hz
4th Order 60 Hz Notch Filter
+,0
\
-10
iii -20
:s
f
\ I
'"to
;;: -30
-40
-50
-60
40
50
60
DO
70
90
FREQUENCY 1Hz)
FIGURE 26. Implementation of a 60 Hz Notch From Computer Calculations
TEST PROCEDURE (Ref. Figure 24)
Gain
Center Frequency
To measure the gain, set the amplitude of the signal
generator to lV RMS (0 dBV) and set the frequency to
the center frequency of the filter. Then read the output
on the ac vbltmeter. The output amplitude at highpass
output is -10 dBV ±0.15 dB, which equals 0.316V
±0.006V RMS. The output amplitude at bandpass
output is 0 dBV ±0.15 dB, which equals 1.000V
±0.017V RMS. The output amplitude at lowpass output
is +10 dBV ±0.15dB, which equals3,16V ±0.06V RMS.
The output at the amplifier output is 0 dBV ±0.1 dB,
which equals lV ±O.OlV RMS.
The center frequency is measured by adjusted the signal
generator for a 180° phase shift and then reading the
input frequency on the counter.
Q
The Q is measured by measuring the bandwidth and
dividing by the center frequency. To measure the bandwidth, increase the frequency of the signal generator
until the phase shift reads 180°-45° ,(135°) and read the
frequency on the frequency counter. This is f-45°'
Decrease the frequency of the Signal generator until the
phase meter reads 180° + 45 (225°) and read the frequency on the frequency counter. This is f+ 45o.
DC Offset
The dc offset is measured with the DVM connected to
the lowpass output by setting the input signal level to
zero and reading the DVM.
PS Current
To calculate the Q:
The power supply current is measured by connecting the
DVM across a 10n resistor in the positive power supply
lead with the input level set to zero. The DVM should
read less than 45 mY.
Q = fa (center frequency)
f-45° - f+ 45o (BW)
11-19
o
o
applications information (con't)
LL,
DEFINITION OF TERMS
BIBLIOGRAPHY:
AMAX
R. W. Daniels: "Approximation Methods for Electronic
Filter Design," McGraw-Hili Book Co., New York, 1974
~
~
(Continued)
(J1
BAND PASS
HIGH PASS
14
o
LOW PASS
5
13
-,
I
I
I
I
L- _
......I
FIGURE 1. AF150 Schematic
The following discussion gives a step·by·step procedure
for designing filters with several examples given for clarity.
If the output is taken from the output of A3, numerator
coefficients a3 and a2 equal zero and the transfer func·
tion becomes:
FREQUENCY TUNING
T(s) = _ _ _ _
a 1_ _ __
(low pass)
Two equal value frequency setting resistors are required
for frequencies above 1 kHz., For low,er frequencies, T
tuning or the addition of external capacitors is required,
Using external capacitors allows the user to go as low in
frequency as he desires. T tuning and external capaci·
tors can be used together,
Using, an external op amp and the proper input and
output connections, the circuit can also be used to
generate the transfer functions for a notch and all pass
filter.
Two resistor tuning for 1 kHz to 100 kHz
In the transfer function for a notch function a2 becomes
zero, al equals wz 2 and a3 equals 1. The transfer func·
tion becomes:
s2 + wz2
T(s)
= ----=--
228.8 x 106
Rf=----n
fo
(1)
(notch)
s2+ wo s + w02
RI
Q
In the all pass transfer function a3 = 1, a2
al = w0 2 . The transfer function becomes:
T(s) =
1,4
= -wo/Q and
AF150
I'
(all pass)
Rt
FIGURE 2. Resistive Tuning,
The relationships between the generalized coefficients
and the external resistors will be found in the appendix.
It is not, however, necessary, to use these theoretical, if
not "messy", equations to solve for the proper external
resistor values. In general, it is assumed that the user
has knowledge of, the frequency and Q of the specific
filter he is designing. For higher ord~r filters of various
types, the reader is directed to any of the available
texts on filters (see bibliography) for information and
tables concerning the location of the poles and zeros.
Once the specifics of the filt,er are found from the tables,
it is simply a matter of cascading the sections with proper
attention to some general guidelines which are included
later in the application section.
1000_
GRAPH A. Resistive Tuning
~~ 100~11
iiia:
I
10l1li11
10 10k
I~~UUW-~~~~~~
Ik
Ie - FREQUENCY 1Hz)
11-23
lOOk
oII)
,...
LL
«
Applications Information
(Continued)
T resistive tuning for fo < 1 kHz
o DETERMINATION
(2)
Af from equation 1.
Setting the a requires one resistor from either pin 1 or
pin 2 to ground. The value of the a setting resistor
depends on the input connection and input resistance as
well as the value of the a. The a will be inversely pro, portional to the, resistance from pin 1 to ground and
directly' proportional to resistance from pin 2 to ground.
NON-INVERTING CONNECTION*
Afl5D
To determine the a resistor, choose a value of input
resistor, RIN, (Figures 5 and 6) and calculate OMIN,
(graph C).
104
1+--
RS
RS
RIN
OMIN=--3.48
FIGURE 3. T Tuning
GRAPH B. T Tuning
If the 0 required in the circuit is greater than OMIN,
use the circuit configuration shown in Figure 5 and
equation 4 to calculate RO; the a resistor. If the 0 of
the circuit is less than OM IN, use the circuit configuration shown in Figure 6 and equation 5.
~
..."
w
10k
!;;
!1i
'"
I
lk
it
100
lk
*The discussion of "non-inverting" and "inverting" hB~ to do
with the phase relationship between the input port and the
low pass output port. Refer'to Figure 1 for other output port
phase re"itionships,
'
10k
, FREQUENCV 1Hz!
If external capacitors are used for fo
equati,on 3 should be used.
Rf=
0.05033
fo (C + 220'x 10- 12 )
< 1 kHz,
n
then
(3)
GRAPH C. QMIN,
Non-Inverting Inpu,t
AF15D
FIGURE. 4.
L~w
Frequency I'IC Tuning
Q
11-24
Applications Information
For 0> OMIN in non-inverting mode:
RO =
>
.....
."
CJ1
(Continued)
INVERTING CONNECTION*
. 104
o
For any 0 in inverting mode:
(4)
~----'---..-
104
3.480-1- - -
RO=--~----__~--
RIN
3.160
D--'\M......-""!+
---~1.1 + -2Xl03)
RIN
(6)
-1
AFI50
AF150
Rn
-==-
FIGURE 5. Q Tuning for Q
> QMIN,
Non·lnverting Input
GRAPH D. RQ for Q
Non-Inverting Input
-==-
> QMIN,
FIGURE 7.
10k
Q
Tuning, Inverting Input
GRAPH F. Q Tuning,
Inverting Input
lk
a:'"
10k
-
100
~
lk
10
~~WWill-~~~-LLU~
0.1
100
10
a
For 0
< OMIN in non-inverting mode:
Q
2 x 103
RO = - - - - - - , - - - - -
(5)
*The 'discussion of "n~n-inverting" and "inverting'" has' 'to do
with the phase relationship between the input port and the
low pass output port. Refer to Figure 1 for other output port
phase relationships.
4
( 1 + _10 )
RIN
o
0.3162
1
.-1.1
DESIGN EXAMPLE
+
AFI50
Non-I nverting Band Pass Filter
Center frequency 38 kHz = fa, 10 Hz/Hz = 0, 10k =
RIN·
Rn
FIGURE 6. Q Tuning for Q
< QMIN,
,NPUT
Non-Inverting Input
GRAPH E. RQ for Q
Non·ln~erting Input
o--IVVV-=i
AF15D
< QMIN,
lOOk
Rn
OJ
m
~"VI""""""I---o OUTPUT
10k
Using equation 1
228.8 x 106
Rf
=-----~
lkllllll
0.01
0.1
1.0
10
Rf =.
11-25
. fa
228.8 x 106
38 x 103
6020n
Applications Information
GRAPH G. Input RC_Notch
(Continued)
Using equation 6
RO =
3.160
2 x 103 )
( 1.1+---
-1
RIN
RO = 250n
From equation 33, the center frequency gain is found to
be 6.3 V/V (16 dB). If the center frequency gain is to be
adjusted, equation 33 can be solved for R0 in terms of
RIN and this substituted into equation 6 to find the
required RIN and RO.
101iZ
For the low pass/high pass summing technique,
Rh =
(tz)
fa
2 RL
10
(8)
NOTCH FILTERS
Rg
HP •
AF150
Notches can be generated by two simple methods:
using RC input (Figure 8) or low pass/high pass summing
(Figure 9). The RC input method requires adding a
capacitor to _pin 14 and a resistor connects to pin 7. The
summing method requires tWo resistors connected to
the low pass and high pass output.
LP
RL
FIGURE 9. Output Notch
GI'IAPH H. Output Notch
The difference between the two possible methods of
generating a notch is that the capacitor connection
requires a high quality precision capacitor and the gain
of the circuit is difficult to adjust because the gain- and
zero location are both dependent on Gz ar)d RZ. The
amplifier summin~ method requires 3 precision resistors
and an external operational amplifier. However, the gain
can be adjusted independent of the notch frequency.
10
100
IZllo
For input RC notch tuning:
DESIGN EXAMPLE
2
R = CZ Rf X 1012
Z
220
fz
(~)
fz
n
19 kHz notch using RC input.
(7)
Center frequency 19 kHz
Zero frequency - 19' kHz
=freque~cy of notch (zer~ location)
20
or
13
AF150
to
fZ
0
y-
OUTPUT
AFtiO
Rn
146
13
"::"
RZ _
INPUT
OUTPUT
0--""------""
INPUT
HZ
FIGURE B. Input RC Notch
12.04.
11-26
l>
Applications Information
3!
TRIALS, TRIBULATIONS AND TRICKS
Using equation 1:
Rf
=
228.Bx 106
Certainly, there is no substitute for experience when
applying active filters, working with op amps or riding
a bicycle. However, the following section will discuss
some of the finer points in more detail, and hopefully
alleviate some of the fears and problems that might
be encountered.
fo
, .iI1 f = 12,040n,
Using equation 4 with RIN = 00:
RO
104
------,,..--n
104
3.480-1- - RIN'
RO = 146n '
TUNING'TIPS
In applications where 2 to 3% accuracy is not sufficient
to provide the required filter response, the AF150 stages
can be tuned by adding trim pots or trim resistors in
series or parallel with one of the frequency determining
resistors and the 0 determining resistor.
Using equation 7:
2
R =,CZ RF x
Z \
220
1012)(~)
fz
When tuning a filter section, no matter what output
configuration is to be used in the circuit, measurements
are made between the input and the band pass (pin 13)
output.
RZ = 12,0400
DESIGN EXAMPLE
19 kHz notch using low pass/high pass summing
Center frequency
Zero frequency
Before any tuning is attempted the low pass (pin 5)
output should be checked to see that the output is not
clipping. At the center frequency of the section the low
pass output is 10 dB higher than the band pass output
and 20 dB higher than the high pass. This should be kept
in mind because if clipping occurs the results' obtained
when tuning will be incorrect.
19 kHz fo
19 kHz fZ
0
20
Using equation 1:
228.8 x 106
Rf=---fo
Frequency Tuning
Rf = 12,040n
By adjusting the resistance betwelln p'ins 7 and 13 the
center frequency of a section can be adjusted. If the
input is through pin 1 the phase shift at center fre·
quency will be 1800 and if the input is through pin 2
the phase shift at center frequency will be 00 • Adjusting
center frequency by phase is the most accurate but
tuning for maximum gain is also correct.
Using equation 4, choose RIN = 10 kS1:
104
RO=
104 n
3.480-1-RIN
RO= 148n
o Tuning
Using equation 8:
Rh,=
(:~r
The 0 is tuned by 'adjusting the resistance between
pin 1 or pin 2 and ground. Low O'tuning resistors will be
from pin 2 to ground' (0 < 0.6). High 0 tuning resistors
will be from pin 1 to ground. To tune the 0 correctly,
the signal source must have an output impedance very
much lower than the input resistance of the filter since
F\L
10
Choose RL = 20k, then Rh = 2k
A,
12.040
GAIN
101<
v,
A,.
10k
1
INPUT
5 ...
AFl5D
AL
~~
20k
2~
~LF~i':6>8:.... . .-
(Continued)
the low frequency and high frequency responses are
interchanged. The normalized low pass 1/(S2 + S/Q + 1)
transforms to the un:normalized high pass:
High Pass Response
}I==*==
AMAX
Wc
s2 + - s + we
2
Q
To obtain the band pass from the low pass filter tables,
AMAX and AMIN are the same as for the low pass case,
but:
fc
~
Normalized Low Pass Transformed to Un-Normalized
Band Pass
The transformation tl)at can be used for low pass to
band pass is:
1
where f3 ~ y-~ ~ ~ i.e., geometric sym·
metry
S=
s2 +w 2
0
BW's
f5 - f1
f4 - f2
~
~
AMIN bandwidth
Ripple bandwidth
where w0 2 is the center frequency of the desired band
pass filter and BW is the ripple bandwidth.
Band Pass Response
L
Normalized Low Pass Transformed to Un-Normalized
Band Stop (Or Notch)
1
AMAX
AMIN
j
\V''\
If 'Vi
,\"
13
The bandstop filter has a reciprocal response to a band
pass filter. Therefore, a bandstop filter can be obtained
by first transforming the low pass prototype to a high
pass and then performing the band pass transformation.
" ,l
To obtain the notch from the low pass filter tables,
AMAX and AMIN are the same as for the low pass case
and
where f3 ~ ~ ~
SELECTION OF TRANSFER FUNCTION
The selection of a function which approximates the
shape of the response desired is a complicated process.
Except in the simplest cases, it requires the use of tables
or computer programs. The form Mthe transferfunction
desired is in terms of the pole and zero locations. The
most common approximations found in tables are
Butterworth, -Chebychev, Elliptic and Bessel. The
decision as to which approximation to use is usually a
function of the requirements and system objectives.
Butterworth filters are the simplest but have the disadvan tage of requiring high order transfer functions to
obtain sharp roll-offs.
v'f2-f4
Notch Response
AMIN
\
/
f--+-,Wr...f-+---f1
A fJ
The Chebychev function is a min/max approximation
in the pass band. This approximation has the property
that it is equiripple whicjl means that the error oscillates
between maximums and minimums of equal amplitude
in the pass band. The Chebychev approximation, because
of its equiripple nature, has a much steeper transition
region than the Butterworth approximation.
1415
Normalized Low Pass Transformed to Un-Normalized
Low Pass
The normalized low pass filter has the pass band edge
normalized to unity. The un-normalized low pass filter
instead has the pass band edge at fc . The normalized and
un-normalized low pass filters are related by the transformation s ~ sWc. This transforms the normalized
pass band edge s ~ j to the un-normalized pass band
edge s = jwc.
The ell iptic filter, also known as Cauer or Zolotarev
filters, are equiripple in the pass band and stop band and
have a steeper transition region than the Butterworth or
the Chebychev.
For a specific low pass filter three quantities can be used
to determ ine the degree of the transfer function: the
maximum pass band ripple, the minimum stop band
attenuation, and the transition ratio (tr ~ ws/wcl.
Decreasing AMAX, increasing AMIN, or decreasing tr
will increase the degree of the transfer function. But for
Normalized Low Pass Transformed to Un-Normalized
High Pass
The transformation that can be used for low pass to high
pass is S = wc/s. Since S is inversely proportional to s,
11-29
3!
o
(J1
o
It)
u::
«
Applications Information
(Continued)
the same requirements the elliptic filter will require
the lowest order trahsfer function. Tables and graphs
are available in reference books 'such' as "Reference
Data for Radio Engineers", Howard W. Sams & Co., Inc.,
5th Edition, '-970 and Erich Christian and Egon Eisen·
mann, "Filter Design Tables and Graphs", John WHey
and Sons, 1966.
For specific transfer functions and their pole locations
such text as Louis Weinberg, "Network Analysis and
Synthesis", McGraw Hill Book Company, 1962 and
Richard W. Daniels, "Approximation Methods for Elec·
tronic Filter Design", McGraw·HiII Book Company,
1974, are available.
(all pass)
Each of the second order functions is realizable by using
an AF150 stage. By cascading these stages the desired
transfer function is realized.
CASCADING SECOND ORDER STAGES.
The primary concern' in cascading second order stages
is to minimize the difference in amplitude from input to
output over the frequencies of interest. A computer
program is probably required in very complicated cases
but some general rules that can be used that will usually
give satisfactory results are:
DESIGN OF CASCADED MUL TISECTION FILTERS
The first step in designing is to define the response
required and define the performance specifications:
1. Type of filter:
Low pass, high pass, band pass, notch, all pass
2. Attenuation and frequency response
3. Performance
Center frequency/corner frequency plus tolerance
and stability
Insertion loss/gain plus tolerance and stability
Source impedance
Load impedance
Maximum output noise
Pow~r consumption
Power supply voltage
Dynamic range
Maximum output level
Second step is' to find the pole and zero location for
the transfer function which nieet the above require·
ments. This can be done by using tables and graphs or
. network synthesis. The form of the transfer function
which is easiest to convert to a cascaded filter is a
product of first and second order terms in these forms:
First Order
K
1. The highest a pole pair should be paired with the
zero pair closest in frequency.
2. If high pass and low pass stages are cascaded, the low
pass sections should be the higher frequency and'high
pass sections the lower frequency.
3. In cascaded filters of more than two sections, the
first section should be the section with a closest
to 0.707 and then additional stages should be added
in order of least difference between first stage a and
their O.
DESIGN EXAMPLES OF CASCADE CONNECTIONS
Example 1.
Consider a 4th order Butterworth low pass filter with a
10kHz cutoff (-3 dB) frequency and input impedance
~30 kn.
From tables, the normalized filter parameters are:
Fl = 1.0
F2= 1.0
01 = 0.541
02 = 1.306
Thus, relative to the design required
Second Order
Fl
F2
K
= (1.0)(10 kHz) = 10 kHz
= (1.0)(10 kHz) = 10 kHz
(low pass)
s+Wr
Section 1
F = 10 kHz, 0= 1.306
Ks
Ks2
(high pass)
s+,Wr
----·n
fo
Rf
Ks
(band pass)
= 22,880n
Select input resistor 31.6 kn
104
1+ - - '
RIN
(notch)
3,48
OMIN = 0.378 ,
11-30
(Using equation 1)
Applications Information
»
3!
(Continued)
Example 2.
Thus, Q> QMIN
01
Consider the design of a low pass filter with the following
. performance:
Therefore:
(Using equation 4)
fc = 10kHz
fs = 11 kHz
AMAX = 1 dB
AMIN = 40 dB
3.48Q - 1 RQ
= 309m
It is found that a 6th or'der elliptic filter will satisfy the
above requirements. The parameters of the design are:
First Stage
A'N
31.6k
INPUT
to (kHz)
Q
fz (kHz)
5.16
0.82
29.71
2
8.83
3.72
13.09
3
10.0
20.89
11.15
STAGE
22.88k
0-'VIi"v-'-""I
OUT
lP
An
3091
13
Stage 1
22.8!lk
a) From equation 1, RF is found to be 44.34k
b) From equation 4, RQ is found to be 11.72k; assuming
RIN (arbitrary) is 10 kD.
Section 2
To create the transmission zero, fz, at 29.71 kHz, use
equation 8.
Since fo is the same as for the first section:
Rf = 22.88 kD
Select RIN = 31.6 kD
Thus,
(Using equation 4)
104
3.48Q-1 - - RIN
RQ = 17,661Q
If RL is arbitrarily chosen as 10 kD, Rh
33.15k.
Thus, the design of the first stage is:
Complete Filter, Example 1
INPUT
22.S8k
INPUT
AI
44.J4k
Ah
l3.15k
13
JUk
A'N
IDk
AF15D
SECTION 1
31.6k
AF150
3091
An
14
1t72k
22.88k
'----.,-::--.,--TI;:;'3---',~~
AI
44.J4k
13
AF150
TO SECOND
STAGE
OUTPUT
SECTION 2
17.SSk
"
where the feedback resistor, R, around the external op
amp may be used to adjust the gain.
22.SSk
11-31
o
Applications Information
(Continued)
Stage 2
Stage 3
The second stage design follows exactly the same proce· .
dure as the first stage design. The results are:
The third stage design, again, is identical to the first
2 stages and the results are (for RIN = l' Ok):
228.8 x lOS
.
= 22.88k
fo
104
RO = - - - - - 1 - 04'0" 141.4U
Rf =
a) From equation 1, Rf = 25.91k
b) From equation 4, RO = 913.SU, again assuming RIN
is arbitrarily 10k.
2
13.09) RL
c) Rh=,( - - -orRh,:,0.22RL
8.83
10
3.480-1- RIN
, _ (fz)2RL_ (11.5)2 RL
Rh- -- fo 10
10
10
Selecting RL = 10k, then Rh = 2.2k, the second stage
design is shown below.
Rh = 0.124 RL
Let RL = 20k, Rh = 2.48k
Second Stage
A
(loti
A'N
IN:~T~~~~ 0-...1
"0.,., . ........
A,
An
10t
913.8
13
"'
25.91.
Filter for Example 2
AI
(Ukl
33.15k
INPUT
R2
(ll.17k)
2.2k
25.9"
10t
AF150
10k
10'
11.72k
13
13
44.34k
25.9n
R3
(l32.2k)
2.48k
22.88.
10k
20k
141.4
"
Note 1: Select R1, R2, R3 for desired gain.
Note 2: All amplifiers LF356.
22.88k
-,
11·32
-=
OUTPUT
Applications Information
»"T1
(Continued)
~
01
11
AV1=-----RIN
RIN
1+
104
o
Similarly, the DC gain of the second and third sections
are:
From equation 13, the DC gain of the first section is
AV2 = 0.850
AV3=0.151
+-RQ
11
AV1 = - - - ; - - - - : - - - - ; 3.86 VIV
104
104
1 + - - + ------,,104
11.72x103
Therefore, the overall DC gain is 0.495 and can be
adjusted by selecting R 1 with respect to 10k, R2 with
respect to 10k or R3 with respect to 20k.
For convenience, a standard resistor value table is given below.
Standard Resistance Values are obtained from the Decade Table by multiplying by multiples of, 1O. As ,an example, 1.33 can
represent 1.33n, 133n, 1.33 kn, 13.3 kn, 133 kn, 1.33 Mn.
Standard 5% and 2% Resistance Values
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
10
27
180
470
30
33
510
3,300
3,600
8,200
9,lDO
22,000
24,000
56,000
62,000
150,000
160,000
0,24
0,27
36
39
43
47
200
220
240
270
1.200
1,300
1,500
0,62
11
12
13
15
16
18
68
75
3,900
4,300
10,000
11,000
27,000
30,000
68,000
75,000
180,000
200,000
0,30
0,33
4,700
5,100
5,600
12,000
13,000
15,000
82,000
91,000
220,000
20
22
24
51
56
62
6,200
6,800
,7,500
16,000
18,000
20,000
33,000
36,000
39,000
43,000
47,000
100,000
110,000
0.36
0,39
0,43
0,47
0.75
0,82
0,91
120,000
130,000
0,51
0,56
82
91
100
110
120
130
150
160
300
330
360
390
430
560
620
1,600
1,800
2,000
680
750
820
910
1,000
2,200
2,400
2,700
1.100
3,000
51,000
OHMS
MEGOHMS
0,68
1.0
1.1
1.2
1.3
1.5
Decade Table Determining 1/2% and 1% Standard Resistance Values
1,00
1.02
1.05
1.07
1.10
1.13
1.15
1.18
1.21
1.24
1,27
1.30
1.33
1.37
1,40
1.43
1,47
1.50
1.54
1.58
1,62
1.65
1,69
,1.74
1.78
1.82
1,87 ,
2.15
2,21
1,91
2.32
2,37
1.96
2,00
2.05
2.10
2.26
2,43
2.49
2,55
2,61
'2,67
2,74
3,16
3,24
3,32
3,40
3,48
2.80
2,87
2,94
3,01
3,09
357
3.65
3.74
\
11·33
3,83
3,92
4,02
4,12
' 4,22
4.64
4.75
4,87
4,99
5,11
4,32
4,42
5,23
5,36
4.53
5.49
5,62
6,81
5.76
5,90
6,04
6,19
6.98
7,15
6,3,4
6.49
6,65
7.32
7.50
7.68
7,87
8,06
825
8,45
8.66
8,87
9,09
9,31
9,53
9,76
o
It)
,..
Appendix
0MIN)
design. However. for completeness. the equations given
are exact.
11-34
(16)
. w1
(17)
Appendix
»
:2
(J1
(Continued)
2 x 103
1.1 + - - -
b) Non·inverting input (Figure 11) transfer equations are:
I
eQ
s2
eh
elN
3
1.1 + - - RO ]
[
"10
RIN
1+-104
J
eb
1.1+--3
RO
"10
- sw l [
RIN
1+ - 104
elN
A
wl w 2
eQ
elN
(18)
(high pass)
A
elN
RQ
s->-o =
(
RIN)
0.1 1 +-4
10
I
eh
;;;
I
eb
elN
.
[ "'~]
1.1 + - - RO
(20)
(low pass)
A
0-
104
1+ - RIN
w-wo
1+
Rfl • 220
, w2=
(24)
RIN
104
1012
Rf2 • 220
l 1~ l
1+ - BIN
2 x 103
1.1+--RO
)0.1 w2
(25)
WI
2 x 10 7
1.1+--1:40
1+-RIN
(23)
RIN
1·+-104
wO= '1'0.1 wlw2
RIN
1+-104 .
[ "'~]
s->-oo =
10 12
wl=
where
A = s2 + s wI
2 x 103
1.1+--RO
(19)
(band pass)
(22)
RO-
.
~, 1~)~!02)
(21)
+0.1 wlw2
wI
RIN
0
" m
22DpF
"N o-"""'_I-tV
10k
'.
13
HIGH PASS
*external components
'.
BAND PASS
FIGURE 11. Non·lnverting Input (0
.11·35
< 0MINI
'0
lOW PASS
(26)
- 1.1
0
oIt)
....
Appendix
00
(32)
,
+.~
(33)
(center freq. gain)
RIN
(29)
Q= [
Rf2 • 220
"
(31)
wO=y'O.l w1 w2
(low pass)
, wi'" ----'--
where
(low pass) (DC gain)
RIN
0
1.1
.
10,12
Rf1 • 220
5 ->
----->.--::3~-' (band pass)
~2X
eQ
I
2 x 104
(28)
.6.
3
10-w1 w 2 - RIN
I
3 ( 1 04 )
2x101+-RIN
RQ
3
sW1 (2X10 ) ,
RIN
,
(band pass)
elN
eQ
elN
y]
4
1+-RQ
, 10
'J
(34)
104
1.1+-RIN
(35)
RQ=
Q
3
'(1 .'2x
1 + -10
- - ) -1
+,0.1 w1 w2 (30)
RIN
1+RQ
14
Rf1*
2k
m
220pF
RIN*
'IN
.".
10k
RO'
..
13
'b
, HIGH pASS
BAND PASS
* E'xternal components
FIGURE 12. Inverting Input, Any Q
11.·36
';
lOW PASS
Appendix
>.
"TI
-'"
(Continued)
(J1
o
d) Differential input (Figure 13) transfer function equations are:
eh
3
s2 (2X 10 )
RIN2
elN
A
2 x 104
(high pass)
(DC Qain) (low pass)
10
-swl
3 .
2x
- - - (high freq. gain) (high pass)
RIN2
(2Xl0 3 ..
RIN2
~=
(37)
(band pass)
2 x 103 (1 +
A
elN
__RIN2
2 x 103 )
wl w 2 ( - - -
Wl= - - - - ,
Rfl • 220
RINl
W2=
Q=
Rf2' 220
1 +4- + - 4'[ '10
10 ]
RQ
RINl
2 x 103
1.1 + - - RIN2
where
RIN2
1+ 104 + ~
RQ
RINl
+0.1 wlw2 (39)
)0.1 w2
.wl
2 x 103 )
( 1.1+--RIN2
~
';0.1
::::?
wl
14
2",
220 pF
Rf1*
2'
220 pF
R1NZ*
"N{ .
(center freq. gain)
(band pass), (42)
(43)
104
RQ=---Q-----------------
3
1.1 + _2x_10 ]
[
RQ
RIN2 .
(38) ,
(low pass)
(41)
~ + 104 )
3
( 1.1 + 2 x 10 )
RIN2
(40)
RIN2
(36)
RIN1*
"::"
"::"
tok
Rn'
'.
13
'b
BAND PASS
HIGH PASS
* External components
FIGURE 13. Differential Input
11-37
';
lOW PASS
104
-1--RINl
(44)
oIn
u::
0
Rg
Rh
.
RIN
Rg
, ) - (high freq. gain) (47)
RIN Rh
104
RQ
1+-+-
,wO=VO.1W1W2
1iO'Rh.
en
elN
wZ=WOV ~-
RL
II
I
=0
(48)
w= Wz
,_
20.
2ZDpF
220pf
LOW PASS
RIN*
'IN
RL"
10k
13
RO"
-=
•
Rh"
R "
lOUT
HIGH PASS
-=
FIGURE 14. Notch Filter Using an External Amplifier
11·38
Appendix
(Continued)
j) Input notch filter (Figure 15) transfer function equa-
tions
a~re;.:.;_....._ _!"
Cz
'
220 x 10- 12
,wO= VO.l wl w 2
C
RZ Z
(50)
[s2+wZ 2]
J
(49)
,
[ 1.1
s2+SWl
4 RO +w02
10 + RO
wl=
Rf2' 220 x 10- 12
wz=wO
10 12
,w2=---Rfl • 220
,Af2 • 220
10 12
14
en
elN
I w .... O
en
elN
I w ....
-RF2
(51)
RZ
Cz
(52)
220x 10- 12
OO
2Dk
10k
Rn*
13
rOUT
'IN
* External components
FIGURE 15. Input Notch Filter Using 3 Amplifiers
g) All
pass (Figure 16) transfer function equations are;
0=
s2 - s wl
s2 + s Wl
(54)
1.1
1012
1012
wl = Afl • 220 ,w2 =
Af2' 220
+wo2
AIN
2+-RQ
eo
elN
[_"]
~ + ~~~
(53)
[_"
AIN ] 'wo'
2+-
wO= VO.l wlw2
Time delay at wo is
AQ
14
20k
20
seconds
wO
13
220pF
101Jlc*
'IN
o-...-",,,,,,,,...-C'"
R*
10k
2R*
&>.....-00·0
RQ*
* External components
FIGURE 16. All Pass
11-3,9
Definition of Terms
AMAX
Maximum pass band peak-to-peak ripple
AMIN
Minimum stop band loss
fz
Frequency of jw axis pole pair
fo
Frequency of complex pole pair
Q
Quality of pole
fc
Pass band edge
fs
Stop band edge'
Rf
Pole frequency determining resistance
Bibliography
R.W. Daniels: "Approximation Methods for Electronic
Filter Design", McGraw·Hili Book Co:; New York, 1974
G.S. Moschytz: "Linear Integrated Networks Design",
Van Norstrand Reinhold Co., New York, 1975
E. Christian and E. Eise~mann, "Filter Design Tables
and Graphs", John Wiley & Sons, New York, 1.966
A.1. Zverev, "Handbook of Filter Syiithesis", John
Wiley & Sons, New York, 1967
Rz
Zero Frequency determining resistance
RQ
Pole quality determining resistance _:
fH
Frequency above center frequency at which
the gain decreases by 3 de for a'''bana pass'
filter
fL
Frequency below center frequency at which'
the gain decreases by 3 dB for a band pass
filter
'
11-40
~National
Active Filters
~ Semiconductor
AF151 Dual Universal Active Filter
General Description
Features
The AF15'l consists of 2 general purpose state variable
active filters in a single package. By using only 4 external
resistors for each section, various second order functions
may be formed. Low pass, high pass and band pass
functions are available simultaneously at separate
outputs. In 'addition, there are 2 uncommitted operational' amplifiers which are available for buffering or
for forming all pass and notch functions. Any of the
classical filter configurations, such as Butterworth,
Bessel, Cauer and Chebyshev can be easily formed.
• Independent Q, frequency and gain adjustment
• Very low sensitivity to external component variation
• Separate low pass, high pass and bandpass outputs
• Operation to 10 kHz
• Q range to 500
• Wide power supply range-±5V to ±18V
• Accuracy-±I%
• Fourth order functions in one package
Circuit Diagrams
lOOk
1000 pF
, 10k
1000 pF
> ....-04
HIGH PASS
OUTPUT
21 ......._--., ......
LOW PASS
OUTPUT
8
lOOk
24
1
12
20
Y
Y
Y
v+
v+
v-
':"
lOOk
1000 pF
10k
15 .
1000 pF
13
> ....HIGH
-014
PASS
>-4I-C:> 16
LOW PASS
OUTPUT
OUTPUT
lOCk
Order Number AF151HY
See NS Package HY24A
11-41
18~17
19~
»
."
.CJ1
.-
Absolute Maximum Ratings
Supply Voltage
Power Dissipation
Differential Input Voltage.
Output Short·Circuit Duration (Note 1)
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
±18V'
900 mW/Package
±36V
Infinite
-25°C to +85°C
-25°C to +100°C
300°C
,
Electrical Characteristics (Complete Active Filter)
Specifications apply for Vs = ±15V anp over -25°C to +85°C unless otherwise specified. (Specifications apply for each section) .
. "','
.,
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency 'Range
fc x Q::; 50,000
10k
Hz
Q Range
.fc x 0 ::; 50,000
500
Hz/Hz
,
fo Accuracy'
AF151·1C
fc x Q::; 10,000, TA = 25°C
. ±2.5
%
AF151·2C
fc x Q::; 10,000, T A = 25°C
±1.0
%
±150
ppm!"C
±7.5
%
±300
±750
ppm!"C
2.5
4.5
TYP
MAX
1.0
6.0
mV
I nput Offset Current
4
50
nA
Input Bias Current
30
200
nA
fo Temperature Coefficient
±50
fc x Q::; 10,000, T.A = 25~C
Q Accuracy
Q Temperature Coefficient
Power Supply Current
VS=±15V
Electrical Characteristics
(Internal Op Amp)
PARAMETER
(Note 2)
CONDITIONS
Input Offset Voltage
mA
MIN
RS::; 10kn
I nput Resistance
UNITS
"
2.5
Mn
Large Signal Voltage Gain
RL ~ 2k, VOUT = ±10V
Output Voltage Swing
RL = 10 kn
±12
±14
V
RL = 2 kn
±10
±13
V
70
90
dB
77
96
dB
25
mA
Input Voltage Range
25
160
V/rnV
±12
Common·Mode Rejection Ratio
RS::; 10kn
Supply Voltage Rejection Ratio
RS::;10kn
Output Short·Circuit Current
Sle~ Rate (Unity .Gai,n)
V
"
,
Small Signal Bandwidth
Phase Margin
,
0.6
V//lS
1
MHz
Degrees
60
I
Note 1: Any of the amplifiers can be shorted to ground indefinitely; however,. more than one should not be simultaneously
mum junction temperature will be exceeded.
Note 2: Specifications apply for Vs = ±1SV, TA = 2S'C.
11·42
shorte~
as the maxi-
I
Applications Information
The AF151 consists of 2 identical filter sections and
2 uncommitted op amps. The op amps may be used for
buffering. inputs and outputs, summing amplifiers (for
notch filter generation), adjusting gain through the
filter sections, additional passive networks to create
higher order filters, or simply used elsewhere in the
user's system.
If the output is taken from the output of A 1, numerator
coefficients a1 and a2 equal zero, and the transfer function becomes:
T(s) =
The design equations given apply to both sections;
however, for clarity, only the pin desi"gnations for
section 1 will be shown in the examples and discussion.
(high pass)
If the output is taken from the output of A2, numerator
coefficients a 1 and a3 equal zero and the transfer functions becomes:
See. the AF100 data sheet for additional information on
this type of filter.
T(s) =
The design equations assume that the user has knowledge
of the frequericy and Q values for the particular design
to be synthesized. If this is not the case, various references and texts are available to help the user in determining these parameters. A bibliography of recommended
texts can also.be found in the AF1 00 data sheet.
(band pass)
If the output is taken from the output of A3, numerator
coefficients a3 and a2 equal zero and the transfer function becomes:
a1
T(s) =
(low pass)
CIRCUIT DESCRIPTION AND OPERATION
A schematic of one section of the AF151 is shown in
Figure 1. Amplifier A1 is a summing amplifier with
inputs from integrator A2 to. the non-inverting input
and integrator A3 to the inverting input. Amplifier A4
is an uncommitted amplifier.
.
Using proper input and output connections the circuit
can also be used to generate the transfer functions for a
notch and all pass filter.
In the transfer function for a notch function a2 becomes
zero, a1 equals wz 2 and a3 equals 1. The transfer function becomes:
By adding external resistors the circuit cim be used to
generate the second order system.
s2+wi
T(s)
In the all pass transfer function a1 = wo2, a2 = -wo/Q
and a3 = 1. The transfer function becomes:
The denominator coefficients determine the complex
pole pair location and the quality of the poles where
Wo =
v'b1
(notch)
Wo
s2 - -s+wo2
= the radian center frequency'
Q
T(s)
Q=
(all pass)
s2 + Wo s +wo2
the quality of the complex pole pair
Q
HIGH PASS
BAND PASS
23
r- -
LOW PASS AMP IN-
..,
22
lOOk
IN2o-,--1~~~--+---~------~------~--------.
I
10k
I
I
21,
INIo-~~~----~~~--------~
I
I
-
- -
L.. _
.:..J
AMP IN+
FIGURE 1. AF151 Schematic (Section 1)
11-43
Applications Information (Continued)
F'REQUENCY CALCULATIONS
For operation above 200 Hz, the frequency of each
section of the AF151 is set by 2 equal valued resistors.
These resistors couple the output of the first op amp
(pin 2) to the input of the second op amp (pin 1) and
the output of the second op amp (pin 23) to the input
of the third op amp (pin 22).
To determ'ine which connection is required for a parti·
cular Q, arbitrarily select a. value of RIN (Figure 4) and
calculate,OMIN according to equation 3.
'
105
1+-RIN
(3)
3.48
The value for Rf is given by:
50.33 x 106
Rf= _ _ _ _ QI
fo
(1 )
If the '0 required for the circuit is greater than OMIN,
use equation 4 to calculate the value of RO' and the
connection shown in Figure 4.
.
10 5
(4)
RO=
For operation below 200 Hz, ''T'' tuning should be
used as shown in Figure 3.
3.480 - 1 -
For ,this configuration"
a
If the
required for the circuit is less than OMIN, use
equation 5 to calculate the value of RO and the connec·
tion shown in Figure 5.
(2)
RS=
Rf - 2RT
where RT or RS can be chosen arbitrarily, once Rf is
fou nd from equation 1.
RO =
(5)
0.3162
5)
10( 1+
-1.1
, RIN
a
Both connections shown in Figures 4 and 5 are "non·
inverting" relative to the phase relationship between the
input signal and the low pass output.
.
Q CALCULATIONS
To set the a of each section of the AF 151, one resistor
is required. The vallJe of the a setting resistor depends
on the input connection (inverting or non·inverting)
and the input resistance. Because the input resistance
does ,affect the a, it is often desirable to use one of
the uncommitted op amps to provide a buffer between
the signal source impedance and the input resistor used
to set the O.
AF151
For any a, equation 6 may be used with the "inverting"
connection shown in Figure 6.
10 5
RO=
2
RT
RT
~
O~_.......R....'N,.."... .-=2.:..f' +
.::1
FIGURE 2. Frequency Tuning
22
Rn
Rn
"1
RS
'
-'-
FIGURE 3. ~'T" Tuning for Low Frequency
FIGURE 4. Connection for Q
RIN'
~
R1N
21
+
AF151
.3
Rn
~---------------------~
FIGURE 5. Connection for Q
AF151
23
~
AT
RS
...
(6)
RIN
AF151
1
3.160(1.1+~)"-1
> QMIN
3_
21
AF151
+
~--~--~------~
< QMIN
FIGURE 6. Connection for Any Q. Inverting
11·44
Applications Information
(Continued)
NOTCH TUNING
When the low pass output and the high pass output are
summed together. the result is a notch (Figure 1).
"LP
14
.1
LP
~
AF15t
HP
12
1
For Figure 6:
10 5
AL= - RIN
104
"HP
FIGURE 7. Notch Filter
The relationship between RLP. RHP. fo and fz. the
location of the notch. is given by equation 7.
RHP=
(
fz)2 RLP
fo
W
5 (
101+
RIN
(7)
105
11+-RIN
Again. it is advantageous to use one of the uncommitted
op amps to perform this summing function to prevent
loading of this stage or the resistors RLP and RHP from
effecting the Q of subsequent stages. Resistor R can be
used to set the gain of the filter section.
For Figure 1:
At low frequency. when fo
of the summing op amp is:
The following list of equations will be helpful' in calcu·
lating the relationship between the external components
and various important parameters. The following defini·
tions are use:
AB
At high frequency. when fo
of the summil)g op amp is:
\RHP
RIN
RIN)
( 1+--+-RQ
10 5
11
AB =
A=
> fz. the gain to the output
1./~)
For Figure 4:
-(1+
the gain to the output
RIN)
(1 +RIN
-- +-10 5
RQ
- Gain from input to low pass output at DC
- Gain from input to high pass output at high
frequency
- Gain from input to band pass output at
center frequency
1.1
AH= A
< fz.
11(~)
RLP
GAIN CALCULATIONS
AL
AH
5 )
10RQ
At the notch. ideally the gain is zero (0).
TUNING TIPS
~)
10 5
--+
RQ
RIN
In applicat,ions where 2% to 3% accuracy is not sufficient
to provide the r~quired filter response. the AF151 stages
can be tuned by adding trim pots or trim resistors ir)
series or parallel with one of the frequency determining
resistors and the Q determining resistor.
A
RIN
RIN
1 + -- +
10 5
RQ
--
When tuning a filter section. no matter what output
configuration is to be used in the circuit. measurements
are made between the input and the bane! pass output..
For Figure 5:
10 5
11+-RQ
Before any tuning is attempted. the low pass output
should be checked to see that the output is not clipping.
At the center frequency of the section. the low pass
output is 10 dB higher than the band pass output and
20 dB higher than the high pass. This should be kept in
mind because if clipping occurs. the results obtained
when tuning will be incorrect.
.
11·45
.....
tt')
u::
(Continued)
+v
INPUT
v+
RFI
OUTPUT
RF2
RIN
lOOk
10k
21
10k
20k
INPUT
INPUT
10k
300k
Ra
519
-v
FIGURE B. Dual Band Pass Filter
FIGURE 9. Telephone Multifrequoncy 1M F) Band Pass Filter
FREO
BW
fc
f1
700
900
1100
1300
1500
1700
75
75
75
75
75
75
69B.4
898.7
1098.8
1298.9
1499.0
1699.1
665.6
865.8
1065.7
1265.8
1465.8
1665.9
100 Hz
I
01 & 02
f2
RFl
RF2
RO
17
21.8
26.7
31.6
36.4
41.3
732.B
932.9
1132.9
1332.9
1532.9
1733.0
75.62k
58. 13k
47.23k
39.76k
34.34k
30.21k
6B.6Bk
53.95k
44.43k
37.76k
32.83k
29.04k
1.749k
1.354k
1.100k
926.2n
802.W
.705.6n
900 Hz
1100 Hz
!300 Hz
1500 Hz
1700 Hz
I
I
I
I
I
AFll0
AFll0
AFll0
I
I
I
I
I
I
AF151
100 Hz
A:: 6dB
AF151
900 Hz
A·6 dB
AF151
1100 Hz
A'6dB
AF151
1300 Hz
A'6dB
AF151
1500 Hz
A'6 dB
AF151
I
1
1
~t-
J
1100 Hz
A'6dB
J
1
1
AF104
. AGe
FIGURE 10. MF Tone Receiver
51.43k
40.11k
22
INPUT 301k
21
21.02k
AF151
":"
Cutoff 1270 Hz
Stop Band Edge 2025 Hz
Band Pass Ripple 1.5 dB
Rejection 59 dB
fel
01
fZl
fR
876.3 Hz
1.75
3201.7 Hz
356.9 Hz
fe2
02
fz2
1254.8 Hz
8.21
2113.3 Hz
9
31.6k
13
18
14 16
11
50k
44.59k
OUTPUT
51.43k
4222k
lOOk
0.01 "F
40.11k
14.1Bk
3164
FIGURE 11. Low Pass Low Speed Asynchronous FSK Modem Filter
11-47
111.5k
'TI
.....
en
.....
Applications Information
(Continued)
24.56k
~
111 ,110
MZ2
O.OIp:F
3D1k
0-1 (
Cutoff 2025 Hz
Stop Band Edge 1270 Hz
Banil Pass Ripple 1.5 dB
Rejection 59 dB
fel
Ql
IZl
fR
2049.6 Hz fe2
'02
8.21
1216.9 Hz fz2
7206 Hz
2209
21
"
AF151
3671
r Sj19'f'
24.56k
2934.8 Hz
1.75
803.3 Hz
'=
104.
r rr
301k
91I13
4
10.61k
tOOk
1'4
n.15k
'DDk
,!'6
30'k
I
2255
24A5k
,
FIGURE 12. High Pass Low Speed Asynchronous FSK Modem Filter
Standard Resistance Values are obtained from the Decade Table by multiplying by multiples of .10. As an example,l.33
can represent 1.33.11, 133.11, 1.33 kn, 13.3 kn, 133 kn 1.33 Mn.
Standard 5% and 2% Re~i5tance Values
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
OHMS
'0
11
12
13
. 15
27
30
33
36
39
43
47
51
56
62
68
75
82
91
100
110
120
130
150
160
180'
470
510
560
620
680
750
820
910
1,000
1,100
1.200
1.300
1.500
1,600
1,800
2,000
2,200
2,400
' 2.700
3.000
3.300
3.600
3.900
4,300
(700
5,100
5,600
6,200
6,800
7,500
8.200
9.100
'10,000
11,000
12,000
13,000
15,000
16,000
18,000
20,000
22.000
24.000
27,000
30,000
33,000
36,000
39,000
43;000
47.000
51,000
56.000
62.000
68,000
75,000
82,000
91,000
100,000
11 0,000
120,000
130,000
150.000
160.000
180,000
200,000
220,000
16
18
20
22
24
200
220
240
270
300
330
360
390
430
MEGOHMS
0.24
0.27
0.30
0.33
0.36
0.39
0.43
0.47
0.51
0.56
0.62
0.68
0.75
0.82
0.91
1.0
1.1
1.2
1.3
1.5
Decade Table Determining 1/2% and 1% Standard Resistance Values
1.00
1.02
1.05
1.07
1.10
1.13
1.15
1.18
1.21
1.24
1.27
1.30
1.33
1.37
1.40
1.43
1.47
1.50
1.54
1.58
1.62
1.65
1.69
1.74
1.78
1.82
1.87
1.91
1.96
2.00
2.05
2.10
2.15.
2.21
2.26
'2.32
2.37
2.43
2.49
2.55
2.61
2.67
2.74
2.80
2.87
2.94
3.01
3.09
3.16
3:24
3.32
3.40
3.48
3.57
3.65
3.74
11-48
3.83
3.92
4.02
4.12
4.22
4.32
4.42
4.53
4.64
4.75
4.87
4.99
5.11
5.23
5.36
5.49
5.62
5.76
5.90
6.04
6.19
6.34
6.49
6.65
6.81
6.98
7.15
7.32
7.50
7.68
7.87
8.06
8.25
8.45
8.66
8.87
9.09
9.31
9.53
9.76
Section 12
Successive
Approximation
Registers
~National
~ Semiconductor
DM2502,DM2503,DM2504
Successive Approximation
Registers
Successive Approximation Registers
general description
DM2503 and DM2504 operate over -55°C to +125°C;
the DM2502C, DM2503C and DM2504C operate over
O°C to +70o C.
The DM2502, DM2503 and DM2504 are 8-bit and 12-bit
TTL registers designed for use in successive approxima,tion AID converters. These devices contain all the logic
and control circuits necessary in combination with a
D/A converter to perform successive approximation
analog-to-digital conversions.
features
The DM2502 has 8 bits with serial capability and is not
expandable. ,
• Complete logic for successive approximation AID
converters
• 8-bit and 12-bit registers
• Capable of short cycle or expanded operation
• Continuous or start-stop operation
• Compatible with D/A converters using any logic code
• Active low or active high logic outputs
• Use as general purpose serial-to·parallel converter or
ring counter
The DM2503 has 8 bits and is expandable without serial
capability.
The DM2504 has 12 bits with serial capability and
expandability.
All three devices are available in' ceramic DIP, ceramic
flatpak, and molded Epoxy-B DIPs. The DM2502,
logic diagram
DO
(OM25tl2,
DM25G4) 07 UI)
~[~~E~I-
0.6(1111
-
~ ~(;1-
--
~
I
I
I
I
I
I
I
I
aD
07(111
C~IIIDgIC
Note l'
t------~-'-------7L-_-_-_-+-_-_-_-_-_-_-_-_~J----I
IS repeated 101 leglsler sUges
g::~ ~~ g~~~~!. DM25DJ
Note 2. Numbers," pllenlhml ile lor OM2504
connection diagrams
(Dual-In-Line and Flat Packages)
DM2502, DM2503
Vee
I..
0)
O'
. 01
15
0,
"
14
DM2504
DO'
11
12
10
Vc;:c
,
Qfi
I.. "
Nt
011
II
21
010
og
08
" "
07
18
D6
11
Nt
16
15
CP
r-
r-
1
(DM25021
00
1
Dcc
,
QO
,
4
01
02
(DM250JI
E
"
14
lDPVIEW
•
0'
1
1
-
~ND
"
1
DO
1
Dec
5
0
DO
Q1
~
02
1
OJ
8
04
,
Q5
10
Nt
11
0
TOP VIEW
Drder Number DM2502J. DM2502CJ, DM2503J
or DM2503CJ
See NS Package J16A
Order Number DM2502CN or DM2503CN
See NS Package N16A
Order Number DM2502W, DM2502CW, DM2503W,
orDM2503CW
Sae NS Package W16A
Order Number DM2504F or DM2504CF
Sae NS Package F24A
Order Number DM2504J or DM2504CJ
Sae NS Package J24A
Order Number DM2504CN '
Sae NS Package N24A
12-1
112
GND
\
absolute maximum rating~
Supply Voltage
Input Voltage
Output Voltage
operating conditions
(Note 1)
7V
5.5V
.5.5V
--ti5·C to +150·C
300·C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Supply Voltage, VCC
DM2502C, DM2503C,
DM2504C
DM2502, DM2503,
DM2504
A
.. Temperature, T
DM2502C,DM2503C,
DM2504C.
DM2502, DM2503,
DM2504
electrical characteristics
(Notes 2 and 3)
PARAMETER
Logical "''''nput Voltage (V. H )
Vee = 5.0V,
CONDITIONS
, , ,
TA =
MIN
MA~
4.75
5.25
V
'4.5
5.5
V
o
+70
'C
-55
+125
·C
UNITS
25°C, CL = 15 pF, unless otherwise specified.
TYP
MAX
UNITS
2.0
Vce = Min
V
Logical .. ". Input Current (lIH)
CP Input
0, E. S Inputs
All Inputs
Vcc
Logical "0" Input Voltage (V rd
Vee
Logical "0" Input Current (IlL)
CPo Sinputs
D. Elnputs
Vee = Max
V'L = OAV
Logical "'" Output Voltage (V OH I
Vce = Min, IOH ::: -0,48 rnA
2A
3.6
Output Short Clrcu;t Current
(Note 41 (losl
Vee::: Max; VOUT = O.OV;.
Output HIgh; CPo D. 5, High;
-10
=
MIN
Max
V,H = 2AV
V,H " 2AV
V ,H = 5.5V
mA
0.8
V
-1.6
. -3.2
mA
mA
,-20
-45
mA
0.2
OA
V
65
65
60
60
90
90
95
85
90
80
124
110
18
28
ns
16
24
ns
26
38
ns
13
19
ns
= Min
-1.0
-1.0
V IL = O.4V
~A
40
80
1.0
6
6
~A
V
E Low
Logical "0" Output
Volt~gc (VOL)
Supply Current {'eel
Vee::: Min, IOL = 9.6 rnA
Vee::: Max, All Outputs Low
DM2502C
DM2,502
DM2503C
DM2503
DM2504C
DM2504
10
Propagation Delay to a Logical "0"
From CP to Any Output (t pdO )
Propagation Delay to a logical "0"
From E to 07 (011) Dutput (tpdol
CP High,S Low
..
;"A
mA
rnA
mA
mA
mA
DM2503, DM2503C. DM2504,
DM2504C Only
10
Propagation Delay to a Logical "1"
From CP to Any Output (tpd,1
Propagation Delav to a Logical "1"
From E to 07 (011) Output Itpd,1
~
CP High,S Low
DM2503, DM2503C. DM2504.
DM2504C Only
ns
Set·Up Time Data Input (t 5 (O))
-10
4
8
Set· Up Time Start Input (1515))
o
9
16.
ns
Minimum Low CP Width (tpwd
30
42
ns
Minimum High CP Width (tPWHI
17
24
15
Maximum Clock Frequency (f MAX )
,
ns
.MHz
21
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they ale not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwi,se specified minimax limits apply across the -55·C to +125·C temperature range for'the DM2502, DM2503 and DM2504,
and across the O·C to +70·C, range for the DM2502C, DM2503C and DM2504C. A'II typicals are given for Vec 5.0V and TA 25'C.
=
=
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
12-2
application information
OPERATION
they drive). Thus, even at very slow dV Idt rates at the
clock input (such as from relatively weak comparator
outputs). improper logic'operation will ncit result.
The registers consist of a set of master latches that act
as the control elements in the device and change state
on the input clock high-to~low transition and a set of
slave latches that hold the register data and change, on
the input clock low-to-high transition. Externally the
device acts as a special purpose serial-to·parallel converter
that accepts data at the D input of the register and sends
the data to the approp'riate slave latch to appear at the
register output and the DO output on the DM2502 and
DM2504 when the clock goes from low-to-high. There
are no restrictions on the data input; 'it can change state
at any time except during a short interval centered about
the clock low-to-high transition. At the same time that
data enters the register bit the next less significant bit
register is set to a low ready for the next iteration.
LOGIC CODES
All three registers can be operated with various logic
codes. Two's complement code is used by offsetting the
comparator 1/2 full range + 1/2 LSB and using the
complement of the MSB (07 or ell1) with a binary D/A
converter. Offset binary is used in the same manner but
with the MSB (Q7 or Qll). BCD D/A converters ca~ be
used with the addition of illegal code suppression logic.
ACTIVE HIGH OR ACTIVE LOW LOGIC
The register can be used with either DI A converters that
require a low voltage level to turn on, or DfA converters
that require a high voltage level to turn the switch on. If
D/A converters are used which turn on with a low logic
level, the resulting digital output from the register is
active low. That is, a logic "1" is represented as a low
voltage level. If D/A converters are used that turn on
with a high logic level then the digital output is active
high; a lo'gic "1" is represented as a high voltage level.
The register is reset by holding the if (Start) signal low
during the clock low-to·high transition. The register
synchronouslY,resets to the state Q7 (11) low, and all
the remaining register outputs high. The Qcc (Conversion Complete) signal is also set high at this time. The S
signal should not be brought back high until after the
clock low-to-high transition in. order to guarantee
correct resetting. After the clock has gone high resetting
the register, the S signal must be removed. On the next
clock low-to-high transition the data on the D input is
set into the Q7 (11) register bit and the Q6 (10) register
bit is set to a low ready for the next clock cycle. On the
next clock low-to-high transition data enters the Q6 (10)'
register bit and Q5 (9) is set to a low. This operation is
repeated for each register bit in turn until the register
has been filled. When the data goes into QO, the Q cc
signal goes low, and the register is inhibited from further
change until reset by Start signal.
EXPANDED OPERATION
An active low enable input, E, on the DM2503 and
DM2504 allows registers to be connected together to
form a longer register by connecting the clock, D, and 5
inputs in parallel and connecting the Q cc output of one
register to the E input of the next less significant
register. When the start signal resets the register, the E
signal goes high, forcing the Q7 (11) bit high and
inhibiting the register from accepting data until the
previous register is full and its Q ce goes low. If only
one register is used the E input should be held at a low
,logic level.
a
The DM2502, DM2503 and DM2504 have a specially
tailored two-phase clock generator to provide 'non·
overlapping two·phase clock pulses (i.e., the clock
waveforms intersect below the thresholds of the gates
timing diagram
DM2502. DM2503
"' I
06 I
I
I
" I
0' I
I
I
L-J
L-J
Dl:c::::J
OUTPUTS
0'1
L-J
I
D':c::::J
DOr::::::J
0"
I
I
DO
12-3
...
C")
o
it)
N
:E
application information (con't)
definition of terms
SHORT CYCLE
CP: The clock input of the register.
0: The serial data input of the r.egister.
DO: The serial data out. (The 0 input delayed one bit).
E: The register enable. This input is used to expand the
length of the register and when high forces the 07 (11)
register output high and inhibits conversion.'When not
used for 'expansion the enable is held at a low logic level
(ground).
OJ i = 7 (11) to 0: The outputs of the register.
Oce: The conversion complete, output. This output
remains high during a conversion and goes low when a
,
conversion is complete.
07 (11): The true output of the MSB of the register.
07 (tli: The complement output of the MSB of the
register.
S: The start input. If the start input is held low for at
least a clock period the register will be reset to 07 (11)
low and all the remaining outputs high. A start pulse that
is ,low for a shorter period of time can be used if it
meets the set-up time requirements of the S input.
If all bits are not required, the register may be truncated
and conversion time saved by using a register output
going low rather than the Occ signal to indicate the end
of conversion. If the register is truncated and operated
in the continuous conversion motte, a lock·up condition
may occur on power turn-on. This condition can be
avoided by making the start input the OR function of
Occ and the appropriate register output.
c
COMPARATOR BIAS
To minimize the digital error below ±1/2 LSB, the
comparator must be biased. If a D/A converter is used,
which requires a low voltage level to turn on, ,the
comparator should be biased +1/2' LSB. If the D/A
converter requires a high logic level to turn on, the
comparator must be biased -1/2 LSB.
truth table
DM2502, DM2503
TIME
INPUTS
OUTPUTS'
D
S
E2
00 3
07
06
05
04
03'
02
01
00
0
1
2
3
4
5
6
7
8
',X
L
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
~
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
01
01
01
L
X
02
02
02
02
L
H
03
03
03
03
03
L
X
04
04
04
04
04
04
L,
X
05
05
05
05
05
05
05
H
H
9
06
06
06
06
06
06
06
06
L
10
07
07
07
.07
07
07
07
07
07
L
L
L
L
L
07
06
05
04
03
02
01
00
00
00
L
L
X
X
H
X
H
NC
NC
NC
NC
NC
NC
NC
NC
tn
07
06
05
04
03
02
01
00
H
H
H
H
L
L
Nate 1: Truth table for OM2504 is extended to include 12 outputs.
Note 2: Truth table for DM2502 does not Include E column or last Ime
Note 3: Truth table for DM2503 does not include DO column.
In
H
L
X
truth table shown.
= HIgh Voltage Level
e
Low Voltage Level,
= Don't Care
NC ., No Change
typical applications
o.
o.
CLOCK
CPo
07 06 06 04 03 D2 01
DMZ5DZ
CLOCK
DM2502
no
Q1
na
05 04 03
Q2
a, no
DIA CQNVERTER
D/A CONVERTER
Active High
Active Low
BCD Illegal Code Suppression
12·4
' Occ
H
-
c
typical applications (con't)
3:
N
(,J'I
o
High Speed 12·Bit AID Converter
N
'Y"L,y
'Y""Y
c
L t
J11l.JU
0."
S
~~~~~o-___'~J CP
r' r
(,J'I
o
DD~~~~I:U\
DMZ504
':'
-b
3:
N
SA"
w
I
0
LSB
~
c
MSB
~'~~Z,:,~"~'~'~I~'~'~16~l1~l1~'~'r.,=,~,~,~
3:
N
(,J'I
o
~
PARALlel
OUTPUT
." 0----.,","""---, .--__-+'!.,!-'LJ~':L.:'~6~1.L.!.'L.!J~L.!'~'..:."~12*=""\.
~
~
_::0----+--<~p,+:r---"i::
"'~,:, l~
~A
MSO " "
A"'"
'--------'r lJ21 11 16
24
I
~
~" 'V
LSO
, ..
REFIN
'OOV
-vv/
'Ok
REFoUT
L....-,
REF
"
1B
± 1".91.
L
.,
/
1.2M
V"
Gvro fOV
switching time waveforms
AT LEAST
AT LEAST
INPUTS
WAVefORMS
....-
IDM""......._. _ _ _ _ __
(DM2503.DM25~).______---'.f-------'r:========1.5V
1:.
~_~JJJ
Q7t111 _ _ _ _ _ _ _;....
' .. "" • .,
~
12·5
....", • .,
'.'Y
-
Muslbel~ldv
Will be lleady
Mlychlnge hom
H to L
W,lIb'chlnllng
hom,H tal
May thnte from
LtDH
Will be ch.ngmg
fram L to H
Don'l cue' Iny
chlnppfl'mrtltd
IInbown
ENABLE
CP' H TO Q1 I'll
~'L
OUTPUTS
Ch.nglng ItUe
.
~ Semiconductor
~National
Successive Approximation
Registers
MMS4C90S/MM74C90S
12~Bit Successive Approximation Register
general description
The MM54C905/MM74C905 CMOS 12-bit successive
approximation register contains all the digit control and
storage necessary for successive approximation analogto-digital conversion. Because of the unique capability
of CMOS to switch to each supply rail without any offset
voltage, it can also be used in pigital systems as the
control and storage element in repetitive routines.
•
High noise immunity
•
Low power TTL
compatibility
0.45 Vee typ
fan out of 2
driving 74L
., Provision for register extension or truncation
• Operates in START/STOP or continuous conversion
mode
features
Drive ladder switches directly. For 10 bits or less
with 50k/l00k R/2R ladder network
•
• Wide supply voltage range
1.0V
• Guaranteed noise margi n
3.0V to 15V
connection diagram
Dual-In-Line Package
vr
24
on
NC
011
22
23
21
010
09
ZQ
DB
19
01
18
Q6
11
CP
NC
16
14
15
13
2
1
~
00
4
00
5
6
7
m m m
8
M
9
M
to
~
Order Number MM54C905D or MM74C905D
See NS Package D24A
Order Number MM74C905N
•• See NS Package N24A
truth table
TIME
INPUTS
OUTPUTS
cc
D
5
'E
DO
011
010
09
08
07
05
04
03
02
01
00
o
x
L
X
H
X
H
x
X
x
X
X
·x
X
X
H
X
L
x
D11
X
X
x
1
L
L
H
H
,', H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
'H
H
H
H
H
H
H'
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
06'
2
DlO
H
L
D11
Dll
L
3
D9'
H
L
Dl0
Dl1
Dl0
,L
H
H'
H
4
5
6
7
D8
H
L
D9
Dll
Dl0
D9
L
D7
H
L
D8
Dl1
Dl0
D9
D8
L,
H
H
D6
D5
H
'H
L
D7
Dll
D10
D9
DB
D7 '
L.
H
L
D6
Dl1
Dl0
D9
D8
D7
D6
L
H
H
H
8
·9
D4
H
Dl1. Dl0
,Dll
Dl0
·D9
D9
D7
D6
'D5
L
H
D5
D4
D8
D3
L
L
D8
D7
D6
D5
D4 ,-
10
D2
H
L '
D3
Dll
Dl0
D9
H
H
L
D2
D11
Dl0
D9
1)5
D5
L
H
D6
66
D3
Dl
D7
D7
D4
11
DB
D8'
D4
D3
D2
L
H
H
12
DO
H
L
Dl
Dll
Dl0
D9
D8
D7
D6
D5
D4'
D3
D2
Dl
L
H
13
x
x
x
H
L
DO
Dl1
Dl0
D9
D8
D7
D6
05
D4
D3
D2
Dl
DO
L
x
x
L
x
x
Dll
Dl0
D9
D8
D7
D6
D5
D4
DO
L
NC
NC
NC
NC
NC
NC
NC'
D2
'Ne
Dl
H
D3
NC
NC
NC
NC
14
H
H'
H '" High level
L = Low level
X " Don'\ care
NC .. No change
12:6
absolute maximum ratings
Voltage at Any Pin
s:
s:
01
(Note 1)
-o.3V to Vee +0.3V
.a::..
Operating Temperature Range
0
-55°C to +125°C
MM54C905
CD
0
01
-40°C to +85°.C
MM74C905
Storage Temperature Range
--65°C to +150°C
500mW
Package Dissipation
Operating Vee Range
16V
Absolute Maximum Vee
300°C
Lead Temperature (Soldering, 10 seconds)
dc electrical characteristics
PARAMETER
........
s:
s:
3.0V to 15V
~
.a::..
Minimax limits apply across temperature range, unless otherwise noted.
CONDITIONS
MIN
TYP -
MAX
UNITS
CMOS TO CMOS
3.5
8.0
Logical "1" Input Voltage (V ,NI ,))
Vee = 5.0V
Vee = 10V
Logical "0" Input Voltage (V,NIOII
Vee = 5.0V
Vee = 10V
Logical "1" Output Voltage (V OUTI '))
Vee = 5.0V, 10 = -101lA
Vee = 10V, 10 = -lallA
Logical "a" Output Voltage (VOUTIO))
Vee = 5.0V, 10 = 10llA
Vee = 10V, 10 = 10llA
V
V
1.5
2.0
Logical "1" Input Current (I,NI1I)
Vee = 15V, V ,N =15V
Logical "0" Input Current (I,NIOI)
Vee = 15V. Y'N = OV
Supply Current (Icc)
Vee = 15V
4,5
9.0
V
V
0.5
1.0
0.005
-1.0
V
V
1.0
-0.005
0.05
V
V
IlA
IlA
300
IlA
CMOS/LPTTL INTERFACE
Logical-,"l" Input VoltagE (V IN I'))
MM54C905
MM74C905
Vee = 4.5V
Vee = 4.75V
Logical "a" Input Voltage (V 'NIO ))
MM54C905
MM74C905
Vee = 4.5V
Vee = 4.75V
Logical "1" Output Voltage (V OUTI '))
MM54C905
MM74C905
Vee = 4.5V, 10 = -3601lA
Vee = 4.75V, 10 = -3601lA
Logical "0" Output Voltage (VOUT(O()
MM54C905
MM74C905
Vee = 4.5V, 10 = 360llA
Vee = 4.75V, 10 = 360llA
V ee -1.5
V ee -l.5
V
V
0.8
0.8
V
V
V
V
2.4
2.4
0.4
0.4
V
V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheed
Output Source Current (lsou ReE)
(P-Channel)
Vee = 5.0V, VOUT = OV
TA = 25°C
-1.75
-3.3
mA
Output Source Current (lsouRcEI
(P·Channell
Vee = 10V. V OUT = OV
T A = 25'C
-8.0
-15',
mA
Output Sink Current (I SINK )
(N·Channel)
Vee = 5.0V. V OUT = Vee
TA = 25'C
1.75
3.6
mA
Output SlI1k Curren.t (lSIt .....----0 'OUT
14
I
I
I
16
"N ~ . . . -<_'lllr_~
v+o!!--o
v-o!--o
GND~
2
~
+
-'
A,
Note: Dotted lines ,denote external connections.
13·1
4
Y
GND
,...
en
8
absolute maximum ratings
:J:
..J
Supply Voltage
Input Voltage
Output Short Circuit Duration
Operating Temperature Range
LH0091
LH0091C
Storage Temperature Range
LH0091
LH0091C
.'
Lead Temp~rature (Soldering, 10 seconds)
electrical characteristi.cs
±22V
±15V peak
Continuous
TMIN
TMAX
125°C
-55°C
-25°C
85°C
-65°C to +150°C
-25°C to +85°C
300°C
Vs = ±15V, TA = 25°C, unless otherwise specified.
~ IT0
Transfer Function = EO(DC)='j
.T
. PARAMETER
ACCURACY (See Definition of Termsl
EIN 2 (t)dt
I
CONDITIONS
I
MIN
I
TYP
Total Unadjusted Error
50 mVrms::; VIN::; 7Vrms (Figure 1)
20, .±0.5 :
Total Adjusted Error
50 mVrms::; VIN::; 7Vrms (Figure 3)
0,5, ±0.05
:otal Unadjusted Error vs Temperature
-25°C::; TA::;' +70°C
I
MAX
UNITS
40, ±1.0
mV,%
1, ±0.2
mV,%
mV, %('C
0.25, ±0.02%
Total Unadjusted Error vs Supply Voltage
I
1
mVIV
AC PERFORMANCE
Frequency for Specified Adjusted Error
Input = 7Vrms, Sinewave (Figure 3)
Input = 0.7Vrms, Sinewave (Figure 3)
Input = 0.1 Vrms, Sinewave (Figure 3)
30
70
40
20
kHz
kHz
kHz
Frequency for 1% Additional Error
Input = 7Vrms, Sinewave (Figure 3)
Input = 0.7Vrms, Sinewave (Figure 3)
Input = 0.1 Vrms, Sinewave (Figure 3)
Hio
200
75
50
kHz
kHz
kHz
2
1.5
0.8
MHz
"
Bandwidth (3 dB)
Crest Factor
.
.
Input = 7Vrms, Sinewave (Figure 3)
Input = 0.7Vrms, Sinewave (Figure 3)
Input = 0.1 Vrms, Sinewave (Figure 3)
Rated Adjusted Accuracy Using the High
Crest Factor Circu'it (Figure 5)
5
For Rated Performance
±0.05
MHz
Ml;lz
10
INPUT CHARACTERISTICS
.Input Voltage Range
Input Impedance
..
OUTPUT CHARACTERISTICS
Rated Output Voltage
4.5
±11
Vpeak
5
kn
·22
mA
1
n
'
10
RL<=: 2.5 kn
Output Short Circuit Current ..
Output Impedance
V
POWER SUPPLY REQUIREMENTS
±5
Operating Range
Quiescent Current
Vs = ±15V
14
±20
V
18
mA
..
13·2
r"
op amp electrical characteristics
PARAMETER
Vs
CONDITIONS
MIN
Input Offset Voltage
Vas
::r:
=±15V. T A =25°C unless otherwise specified
TYP
MAX
1.0
10
mV
nA
lOS
I nput Offset Current
4.0
200
19
Input Bias Current
30
500
RIN
Input Resistance
2.5
AOL
Large Signal Voltage Gain
VOUT = ±10V. RL ~ 2 kf!
Va
Output Voltage Swing
RL
VI
Input Voltage Range
CMRR
Common-Mode Rejection Ratio
RS:::; 10
15
= 10 H2
UNITS
nA
Mn
160
±10
V/mV
±13
V
RS:::; 10 kf!
90
dB
kn
±10
V
PSRR
Supply Voltage Rejection Ratio
96
dB
ISC
Output Short-Circuit Current
25
mA
,Sr
Slew Rate (Unity Gainl
0.5
Vips
BW
Small Signal Bandwidth
1.0
MHz
typical performance characteristics
Error vs Frequency
Error vs Frequenc.y
Error vs Crest Factor
1
0.3
O.1Vrms
'"z
i
E
::i
a:
f-H+H-Htr-t-H~~ 2Vrms
~
c
C 0.1
a:
c
...~
~
c
BAJ I I
CONNECTION
0'2I-HII'+'+'+-1vHvHvHV""71
!;
~
,--;-.-.-,--,---,--r-r-,
0.1
V
/
......
1'-+--+:...r"'HIGH CREST.......
~
~ACTJOR ~IRc~rT I
THIS TEST IS DONE WITH A PULSETAAIN
Vp~
0.1
0.01
lk
10k
lOOk
1M
10
FREOUENCY 1Hz).
typical applications
lC1V,PW
~
200U5 DUTY CYCLE CHANGED
TO OBTAIN DJFHRENT CREST FACTORS
II
L-.J!o.L~lJn...ww..uUlll..-l...LJ.JJJJJJ
100
FREQUENCY
10k
lk
IHzl
'OUT
LH0091
<: l/lF; frequency <: 1
kHz
FIGURE 1. LH0091 Basic Connection (No Trim}
13-3
2
3
4
5
6
1
CRESTFACTOR
(AII'applications require power supply by-pass capacitors.)
CEXT
1
B 9 10
0
0
CD
-"
....
8
:::t
CJ)
-'
typical applications (con'd)
R3
10k
RT = 240k
CEXT ~ ljlF, f
~
1 kHz
~----~~--------~'our
3M
Note. The easy trim procedure is used for ae coupled input
signals. It involves two trims and can achieve accuracies of 2 mV
offset ±0.1 % reading.
R4
500
Procedure:
1. Apply 100 mV rms (sine wavel to input, adjust R3 until
the output reads 100 mVOC.
2. Apply 5 V rms (sine wave) to input, adjust R4 until the
output reads 5 VOC'
3. Repeat steps 1 and 2 until the desired initial accuracy is
achieved.
LH0091
FIGURE 2. LH0091 "Easy Trim" (For Be Inputs Onlyl
R3
Rl
R2
R3
. R4
If' Qo....JV\10,.,k_-o V_
= de symmetry balence
= Input offset
= Output offset
= Gain adjust
~ote.
This pro~edure will give accuracies of 0.5 mV offset
±0.05% reatling for inputs from 0.05V pea~ to 10V peak .
3M
R2
10k
Procedure:
1. Apply 60 mVOC to the input. flead and record the output.
2. Apply -50 mVOC to the input. Use R2 to adjust for an
output of the same magnitude as in step 1.
.
3. Apply '50 mV to the input. Use R3 to adjust the output for
5OmV,
4. Apply -50 mV to input. Use R2 to adjust the output for
50mV.
.
5. Apply ±10V alternately to the input. Adjust Rl until the
output readings for both polarities are equal (not necessary
that they be exactly 10VI6. Applv 10V to the input. Use R4 to adjust for 10V at the
output.
7, Repeat this procedure to obtain the desired accuracy.
CEXT
V-
If'
·our
R4
600
If'
'IN
16
16
14
13
12
11
10
LH0091
FIGURE 3. LH0091 Standard de Trim Procedure
FILTERED
OUTPUT .,.__________..,
Note. The additional op amp in the LH0091 may be used as a
low pass filter as shown in Figure 4.
LH0D91
Cl
Rl
Rl =R2=16k
Cl =C2 = ljlF
f o O!10Hz
FIGURE 4. Output Filter Connection USing the Internal Op Amp
13-4
typical applications (con'd)
10k
Note. When converting signals with a crest factor;::: 2, the
LH0091 should be connected as shown. Note that this circuit
V+o-...J""""'-QV-
utilizes a 20k resistor to drop the input current by a factor of
five. The frequency response will correspond to a voltage which
is I/S eiN.
3M
Note that the extra op amp in the LH0091 may be used to
build a gain of 5 amplifier to restore the output voltage,
10k
10pF
V+~V-
'IN
'OUT
20k
'INo-~""""",,=~o
16
3M
15
14
LH0091
LH0091
V-
40k
":"
10k
10k
Note. Response time of the de output voltage is dominated
by the RC time constant consisting of the total resistance
between pins 9 and 10 and the external capacitor, CEX.
FIGURE S. High Crest Factor Circuit
definition of terms
True rms to dc Converter: A device which converts
any signal (ac, dc, ac + dc) to the d!= equivalent of the
rms value.
Error: is the amount by which the actual output differs
from the theoretical value. Error is defined as a sum of a
fixed term and a percent of reading term. The fixed
term remains constant, regardless of input while the
percent of reading term varies with the input.
Total Unadjusted Error·: The total error of the device
without any external adjustments.
Bandwidth: The frequency at which the output dc
IIoltage drops to 0.707 of the dc value at low frequency.
, 13·5
Frequency for Specified Error: The error at low fre·
quency is governed by the size of the external averaging
capacitor. At high frequencies, error is dependent on the
frequency response of the internal circuitry. The fre·
quency for specified error is the maximum input
frequency for which the output will be within the
specified error band (i.e., frequency for 1% error means
the input frequency must be less than 200 kHz to
maintain an output with an error of less than 1% of the
initial reading.
Crest Factor: is the peak value of a waveform divided
by the rms value of the same waveform. For high crest
factor signals, the performance of the LH0091 can be
improved by using the high crest factor connection.
v
0)
o
o
:::E:
.-1
~National
Functional Blocks
~ Semiconductor
LH0094 Multifunction Converter
General Description
The LH0094 multifunction converter gerierates an output
voltage per the transfer function:
Eo = Vy
•
•
i'!.!:_)m, 0.1 ~ m ~ 10: m continuously
\ \Ix
Minimum component count
Internal matched resistor pair for setting m = 2 andm =0.5
Applications
adjustable
m is set by 2 resistors.
Features.
• Low cost.
• Versatile
• High accuracy~0.05%
• Wide supply range-±5V to ±22V
•
•
•
•
•
•
•
Precision divider, multiplier
Square root
Square
Trigonometric function generat9r
Companding
Linearization
Control systems
•
Log a!11P
.Block and Connection Diagrams
Dual-ln·Line Package
v,
Y.
E.
lH0094
Vy
E.
vc
Vy
A4-
v-
RA
RCOMMON
TOPVIEW
Order Number LH0094HV
See NS Package HV 168
Simplified Schematic
12
13
Y.
lOOk
-=
Y,
lOOk
16
I
E.
Vy
lOOk
6 100. g loii
6~
68
13-6
Rs
r-
::J:
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Output Short·Circuit Duration
±22V
±22V
o
Storage Temperature Range
LH0094D
LH0094CD
Lead Temperature (Soldering, 10 seconds)
Continuous'
Operating Temperature Range
-65°C to +150°C
-55°C to +125°C
300°C
-25° C to +85° C
-55°C to +125°C
LH0094CD
LH0094D
Electrical Characteristics
Vs ~ ±15V, TA ~ 25°C unless otherwise specified. Transfer function: Eo~Vy
PARAMETER
I
CONDITIONS
MIN
eZf
Vx
;O.1-:;m-:;10;OV-:;Vx ,Vy ,Vz -:;10V
I
LH0094
TYP
MAX
0.25
0,45
I
LH0094C
MIN
TYP
MAX.
0,45
0.9
UNITS
ACCURACY
Multiply
Untrimmed
External Trim
Divide
V V
Eo ~...!..2 (0.03< Vy < 10V;0.01 1
For basic applications (multiply, divide, square, square
root) it is possible to use the device without any external adjustments or components. Two matched resistors
are provided internally to set m for square' or square
root.
~3
Rl + R2
R2
m=---
When using external resistors to set m, such resistors
should be as close to the device as possible.
ACCURACY (ERROR)
SELECTION OF RESISTORS TO SET m
The accuracy of the LH0094 is specified for both externally adjusted and unadjusted cases.
Internal Matched Resistors
Although it is customary to specify the errors in percent
of full-scale (1 OVI. it is seen from the typical performance curves that the actual errors are in percent of
reading. Thus, the specified errors are overly conservative 'for small input voltages. An example of this is the
LH0094 used in the multiplication mode. The specified
typical error is 0.25% of full-scale (25 mV). As seen
from the curve, the unadjusted error is "" 25 mV at 10V
input, but the error is less than 10 mV for inputs up to
1V. Note also that if either the multiplicand or the
multiplier is at less than 10V, (5V for example) the
unadjusted error is less. Thus, the errors specified are at
full-scale-the worst case.
RA and RB are matched internal resistors. They are
lOOn ±10%, but matched to 0.1%.
(a) m = 2*
.J. ''''
(b) m = 0.5*
'~
14
C)
The 'LH0094 is designed such that the use"r is able
to externally adjust the gain and,offset of the devicethus trim out all of the errors of conversion. In most
applications, the gain adjustment is the only external
trim needed for super accuracy-except in division
mode, where a denominator offset adjust is needed
for small denominator voltages.
3
......
*No external resistors required, strap as indicated
EXPONENTS
External Resistors
The LH0094 is capable of performing roots to 0.1 and
powers up to 10; However, care should be taken when
applying these exponents-otherwise" results may be
misinterpreted. For example, consider the 1/1 Oth
power of a number: i.e., 0.001 raised to 0.1 power is
0,5011; 0.1 raised to the 0.1 power is 0.7943; and 10
raised to the 0.1 power is 1.2589. Thus, it is seen that
while the input has changed 4 decades, the output has
only changed a littl.e more than a factor of 2. It is also
seen that with as little as 1 mV of offset, the output will
also be greater than zero with.zero input.
The exponent is set by 2 external resistors or it may
be con'tinuously varied by a single trim pot. (Rl +
R2:::;500n.
(a) m= 1,
~3
13-8
Applications Information
(Continued)
1. CLAMP DIODE CONNECTION
01
IN914
--*--+-----.
V,o------+--i--,
LHDD94
0.1 $.m $.10
Note. This clamp diode con'·
nection is recommended for
those applications in which
Eo
the inputs may be subject to
open circuit or negative signals.
Vy 0-----.....1.
FIGURE 1. Clamp Diode Connection
2. MULTIPLY
0.4
MULTlPLV
V,
10.00V
Eo = VyVz
10
D.l
0--1------+--;-....,
WITHOUT EXTERNAL
ADJUSTMENTS
~
....-+-0 Vz
~
a:
Q
a:
a:
I
0.2
Vy =IOV
w
LHDD94
II"
0.1
l.,.;
Eo = Vy Vz
10
Vy
o
0--+--..1
0-+----.....
~,
o
'"rll i~1
V
0.1
10
V z (V)
FIGURE 2a. LH0094 Used to Multiply (No External Adjustment)
FIGURE 2b. Typical Performance of
LH0094 in Multiply Mode Without
External Adjustment
01
IN914
IDV REF
(LHD07D OR
. LH0075)
r--*--
0--------------------1--,
Vz
RI
2M
Eo = Vy Vz
10
Eo = Vy Vz
10
lH0094
m
=I
0-----+-+---11
R2
10k
Trim Procedure
SetVz=Vy=IOV'
Adjust R2 until output = 10.000V
FIGURE 3. Precision Multiplier (0.02% Typ) with 1 External Adj~stmei1t
13·9
Applications Information
(Continued)
3. DIVIDE
01
·IN914
OA
r---.,.--
DIVIDE
Vz
Eo=IO Vx
I
I
I
I
0.3
V,
WITHOUT EXTERNAL
Zf
...
Vz
~
a:
a:
a:
AOJWITilu TS
0.2
Vx = 0.5'(/
Q
'"
LH0094
ED = 10 Vz
Vx
~
0.1
~
o
0--+.,-..1
Vx=W.L
~Vx= 10V
.,.
~
o
II
11111
0.1
10
Vz(V)
Vy = 10V REF
0------......
FIGURE 48. LH0094 Used to Divide (No External Adjustment)
FIGURE 4b. Typical Performance, Divide Mode,
Without External Adjustments
V-·
RJ
10k
I -.
I
':"
v+
~ ~~914
I
r---------~--~-i---r--~-~
Trim Procedures
Apply 10V to Vy·• O.IV to Vx and Vz.
Adjust R3 until Eo = I O.OOOV.
Apply 10.000V to all inputs.
Adjust R2 until Eo = IO.OOOV
Repeat procedure.
Rl
2M
m= I
ED = 10
~ 0-----+-....--1
Vx
10V REF
(LH0070 DR
LH0075)
R2
10k
o---.I\IV'v-....- - -....
FIGURE 5. Precision Divider (0.05% Typ)
4. SQUARE
01
lN914
0.5
r------+--*-Vxo-----~~
SQUARING
Eo=10(~~)
0.4
r--f--Ovz
~
~
0.3
IL
2.
WITHOUT EXTERNAL
ADJUSTMENT
1
.I
a:
.L
Q
IIC
IIC
0.2
'"
0.1
o
ED
V y o - - -....
--
.,.
o
1
2
3
..,,~
4
5
V
6
7
B 9
Vz(V)
FIGURE 6a. Basic Connectionlof LH0094 (m = 2) without
External Adjustment Using Internal Resistors to Set m
·13·10
FIGURE 6b. Squaring Mode without
External Adjustment
10
Applications Information.
4. SQUARE (Continued)
v.
r
::x:
o
o
(Continued)
01 r1
CI-_ _ _ _ _ _ _ _ _ _.,N914
w
+
lDVREF
to
.~
r--t-OVz
. Rl
Eo = 10
2M
j
Vz
10
R2
10k
Vy~~~~~-~~
lDV REF
Trim Procedure
Apply 10V to all inputs.
Adjust R2 until Eo = 10.000V
FIGURE 7. Precision Square Rooter (O.15% Typ)
5. SQUAR E ROOT
01
lN914
r--*--
0.4
/
snROO~
Vz
Eo "D
V.~----+-~~~
0.3
Vz
en
..:
~
a:
a:
a:
c
V
0.1
o
V y o - - t - -.......
LI
V
0.2
w
Eo~-t-...
10
WITHOUT EXTERNAL
ADJUSTMENT
I
i""
o
Vz) 1/2
Eo= Vy ( Vx
10
0.1
VZ(V)
FIGURE ab. Typical Performance Curve Square Root,
No External Adjustment
FIGURE 8a. Basic Connection of LH0094 (m = 0.5)
without External Adjustment Using Internal Resistors
to Set m
01
lN914
.----..--+4--. V.
r----r-------~~,DVREF
Rl
2M
Eo~--------~+_~
VVy
R2
10k
Trim Procedure
10V REF o--'V'V'Ii..-...- - - - - '
Apply 10V to V z
Adjust R2 for 10.000V at output
FIGURE 9. Precision Squaring Circuit (O.15% Typ)
13-11
Applications Information
(Continued)
6. LOW LEVEL SQUARE ROOT
01
lN914
r--*--
Eo~--~------------~--,
v+
m=1
Eo = 10 V z
Eo
Rl
2M
E02 = 10 V z
:. Eo = -/10 Vz
SmV:;> Vz :;> 10V
R2
10V
10k
(LH0070 ~...I\NII-"----'"
DR LH0075)
Trim Procedure
Set Vz = 10V
Adjust R2 until output = 10.000V
FIGURE 10. ·3·Decade Precision Square Root Circuit Using the LH0094 with m = 1
Typical Applications
01
lN914
VXC~
r--*--
________________~__.,
10V
r--+-+~:> Vz
m
Eo = 10
(~~)
Eo~--------+-~
Vy~~~~~~____~
10V
R2
.10k
Trim Procedure
Apply 10V to all inputs
Adjust R2 for output of 10.000V
For m = 5
For m = 0.2
.~
014
Rl
m
9 99
~
3
R2
=---;
Rl+R2
R2
ChoOse Rl
R2
= son
m=
:.R2=200n
Rl + R2
R2;
10
Rl
Choose R2
:. Rl
FIGURE 11. Precjsion EXl,lonentiator (m = 0.2 to 5)
13·12
14
3
= SOll
= 200ll
r-
Typical Applications
:I:
(Continued)
(m= 1)
o
o
R
CO
~
IV11
VO
LH0094
Eo ~-"--v\IV"""~-I
...-----+--oIV21
R
,R
VO+V2
R
Note. The LH0094 may be used to generate a voltage equivalent to:
VO = v'V1 2 + V2 2
V1 2
VO= V2+ - - VO+V2
V02 + VO V2 = V2 VO + V22 + V1 2
V02 = V1 2 + V22
VI, V2 0-10V
R'" 10k
Nat,ianal Semiconductor resistor array RA08-10k is recommended
FIGURE 12. Vector Magnitude Function
(m= 1)
10
(m= 1)
Eo=10~
r----.....,1--"";'---1v
Vr
v
Vt>P
""''''-0
Note. The LH0094 may be used in direct measurement of gas flow;
Flow=k
J(PaP
T
Eo=10VPXVt>P
VT
Eo
E02=10 VpVtip
VT
EO=jl0 Vp Vt>P
VT
p = Absolute pressure
T = Absolute temperature
.6.P = Pressure drop
FIGURE 13. Mass Gas Flow Circuit
13·13
Eo
'lit
m
o
o
Typical Applications
(Continued)
l:
..J
-
R
R
R2
10
R1
14
r------...-~-O Va
= ELOG
R1
R2
Ex~-----+--i-~
Ez
-
LH0094
V-
Note. The LH0094 may also be used to generate the Log of a
ratio of 2 voltages. The output is taken from pin 14 of the
LH0094 for the Log application.
.
ELOG
=
where Kl
If K1
K1 KT 2n V z
q
Vx
=
R1 + R2
R2
= KT/q2n10
Rl = 15.9 R2
R2 "" 400n
R2 must be a thermistor with a tempcc:> of :~',O.33%/OC to
be compensated over temperature.
\
FIGURE 14. Log Amp Application
13·14
~National
Functional Blocks
~ Semiconductor
MM74C925, MM74C926, MM74C927, MM74C928 4-Digit
Counters with Multiplexed 7-Segment Output Drivers.
general description
carry·out is an overflow indicator which is high at
2000, and it goes back low only when the counter is
reset. Thus, this is a 3 1/2·digit counter.
These CMOS counters consist of a 4-digit counter, an
internal output latch, NPN output sourcing drivers for
a 7-segment display, ·and an internal multiplexing
circuitry with four multiplexing outputs. The multiplexing circuit has its own free·running oscillator,
and requires no external clock. The counters advance
on negative edge of clock. A high signal on the Res·et
input will reset the counter to zero, and reset the carry·
out low. A low signal on the Latch Enable input will
latch the number in the counters into the internal output latches. A high signal on Display Select input will
select the number in the counter to be displayed; a low
level signal on the Display Select will select the number
in the output latch to be displayed.
features
•
•
•
•
Wide supply voltage range
3V to 6V
Guaranteed noise margin
1V
High noise immunity
0.45 Vee typ
High segment sourcing current
40 mA
@Vee-1.6V, Vee = 5V
• Internal multiplexing circuitry
design considerations
The MM74C925 is a 4-decade counter and has Latch
'Enable, Clock and Reset inputs.
·Segment resistors are desirable to minimize power
dissipation and chip heating. The DM75492 serves as a
good digit driver when it is desired to drive bright
displays. When using this driver with a 5V supply at
room temperature, the display can be driven without
segment resistors to full illumination. The user must use
caution in this mode however, to prevent overheating of
the device by using too high a supply voltage or by
operating at high ambient temperatures.
The MM74C926 is like the MM74C925 except that it
has a display select and a carry-out used for cascading
counters. The carry-out signal goes high at 6000, goes
back low at 0000.
The MM74C927 is like the MM74C926 except the
second most significan\digit divides by 6 rather than 10.
Thus, if the·clock inpur,frequency is 10 Hz, the display
would read tenths of seconds and minutes (i.e., 9:59.9).
The input protection circuitry consists of a series resistor,
and a diode to ground. Thus input signals exceeding
Vec will not be clamped. This input signal should not be
.
allowed to exceed 15V.
The MM74C928 is like the MM74C926 except the most
significant digit divides by 2 rather than 10 and the
conne~tion
diagrams
Dual-In-Line Package
Dual-ln·Line Package
tARRY
aUT
Order Number MM74C925N
See NS Package N 16A
Run Clilt.
Ilo.o-o
eo..
Order Number MM74C926N, MM74C927N
or MM74C928N
See NS Package N 18A
functional description
Reset
Asynchr6nous, active high
Display Select
High, displays output of counter
Low, displays output of latch
Latch Enable
High, flow through condition
Low, latch condition
Clock
Negative edge sensitive
13-15
Segment Output _. Current sourcing with 80 mA @
VOUT = Vcc - 1.6V typical.
Also, sink capability = 2 LTTL
loads
Current sourcing with 1 mA @
Digit Output
/
VOUT = 1.75V. Also, sink capa·
bility = 2 LTTL loads
2 LTTL loads. See carry·out
Carry·out
waveforms.
absolute maximum ratings
Voltage at Any Output Pin
Voltage at Any Input Pin
Gnd - 0.3V to Vee+0.3V
Gnd - 0.3V to +15V
-40°C to +85°C
Operating Temperature Range (T A)
Storage Temperature Range
Package Dissipation
Operating Vee Range
(Note 1)
--65°C to +150°C
Refer to PO(MAX) vs T A Graph
~3V to 6V
6.5V·
Vee
Lead Temperature (Soldering, 10 seconds)
dc electrical characteristics
300°C
MinImax limits apply at -40°C
PARAMETER
s:; T j s:; +85°C, unless otherwise noted.
CONOITIONS
MIN
TVP
MAX
UNITS
CMOS TO CMOS
V ,NI "
Logical "1" Input Voltage
Vee = 5.0V
V'NIO)
Logical "0" Input Voltage
Vee = 5.0V
Logical "1" Output Voltage
Vee = 5.0V, 10 =-10/.lA
V OUTI1l
3.5
V
V
4.5
.-
(Carry·out and Digit Output
Only)
V
1.5
V ouno)
Logical "0" Output Voltage
Vee = 5.0V, 10 = 10/.lA
I'NI"
Logical'''l''lnput Current
Vee = 5.0V, Y'N = 15V
I'NIO)
Logical "0" Input Current
Vee = 5.0V, Y'N = OV
lee
Supply Current
Vee = 5.0V, Outputs Open Circuit,
0.005
-1.0
0.5
V
1.0
/.IA
-0.005
20
/.IA
1000
/.I A
Y'N =.OV or 5V
CMOS/LPTTL INTERFACE
V'NI"
Logical "1" Input Voltage
Vee = 4.75V
V'NIO)
Logical "0" Input Voltage
Vee =4.75V
V~UTI"
.Logical ".1" Output Voltage
Vec = 4.7SV,
10 =-360·/.IA
(Carry·Out and Digit
V ee -1.5
V
V
0.8
\
2.4
V
Output Only)
Vouno)
Logical "0" Output Voltage
0.4
Vee =4.7SV,
V
10 = 360~A
OUTPUT DRIVE
-V OUT
Output Voltage (Segment
Sourcing Output)
RON
Output Resistance (Segment
Sourcing Output)
louT =-135 mA, Vee = SV, Ti = 25°C
lOUT = -40 mA, Vee = 5V
{ T = 100°C
T; = 150°C
Vee -l·.6
V ec -2
V
V
V
20
lOUT = -65 mA, Vee = 5V, Ti =.25°C
lOUT = -40 rnA, Vee = 5V
Vee -l.3
V ee -1.2
V ee -1.4
30
{ 1'i = 100:C
T j =150C
Output Resistance (Segment
40
3~
50
0.6
0.8
n
n
,n
%(C
Output) Temperature Coefficient
Vee = 4,75V, V OUT = 1.75V, T j = 150°C
-1
-2
mA
Output Source Current
(Carry·out)
Vee = 5V, V OUT = OV, T j '= 25°C
-1.75
-3,3
mA
'SINK
Output Sink Current
(Ali Outputs)
Vee = 5V, V OUT = Vee, Ti = 25°C
1.75
3.6
mA
6 iA
Thermal Resistance
Mlvi74C925
'SOURCE
Output Source Current
(Digit Output)
'SOURCE
(Note 4)
MM74C926, MM74C927, MM74C928
75
100
°C/W
70
90
°C/W
Note 1: "Absolute Maximum Ratings" are those values be..,·.:md which the safety of the device cannot be guaranteed. Except for "Operating
Range" they afe not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing ..
Note 3:. ·CPO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN-90.
Note 4: OjA measured in free-air with device soldered into printed circuit board.
13-16
ac electrical characteristics
TJ = 25°C, C L
f MAX
TVP
T, = 100°C
2
1.5
4
3
Vee = 5.0V
TI = 25°C
T; = 100°C
250
320
100
125
ns
ns
Vee = 5.0V
T; = 25'C
Tj = 100°C
250
320
100
ns
ns
Vee = 5.0V
Tj .= 25°C
Tj = 100°C
2500
3200
1250
Vee =5.0V
Tj = 25'C
0
-100
ns
Tj = 100°C
0
-100
ns
T, = 25°C
T j = 100°C
320
160
200
ns
ns
CONDITIONS
Maximum Clock Frequency
tr.tf
Maximum Clock Rise or Fall Time
tWA
Reset Pulse Width
tWLE
Latch Enable Pulse Width
tSET(CK,lEI
Clock to Latch Enable Set·Up Time
Vee = 5.0V
Multiplexing Output Frequency
Vee = 5.0V
Input Capacitance
Any Input (Note 2)
!;;
~
!2
~
j
5;;
~
00
.oS 2200
~ 1800
I--!+--I.(-
~
~ 1600
1---.l1--+_-+_-+_--1
x
~
I
x
~
5.0
4.0
30
2.D
~
1,0
400
200
0
~~
0
W
~
00
I~C)
~
10
20
30
40
50
60
10
SEGMENT RESISTOR (n)
= Voltage across digit
MM74C926
RESET
V"
CARRY·
OUT
CLOCK
I+------f.!!.o CLOCK
DISPLAY
SELECT
LATCH
ENABLE
LATCH
ENABLE
AOUT
BOUT
Cour
Dour
AOUT
BOUT
COUT
DOUT
GNO
GNO
MM74C927
O':':'1--....-~r--.....---,
MM74C928
RESET
1+------+:>0 CLOCK
AOUT
~
Note. Vo
driver.
MM74C925
DISPLAY
SELECT
LATCH
ENABLE
Typical Average Segment
Current vs Segment Resistor
Value
MM74C!J25
logic and block diagrams
RESET
Hz
BOD
600
TAo -AMBIENT TEMPERATURE
Your IV)
ns
ns
1600
MM74C926/MM74C927/MM74C928
1400
~ 1200
~ 1000
~
125
J1U
S 2000
40
20
Maximum Power Dissipation
vs Ambient Temperature
1--1-1-1-1'/-+--+---1
400
I's
pF
typical performance characteristics
i.
MHz
MHz
1000
f MUX
.
UNITS
15
C'N
Typical Segment Current vs
Output Voltage
MAX
Vee = 5.0V
Reset to Latch Enable Set·Up Time
tSET(R,LE)
Tj = 25°C
Vee = 5.0V,
Square Wave Clock
Latch Enable to Reset
Wait Time
tLA
= 50 pF, unless otherwise specified
MIN
PARAMETER
.....!Lr-..%...--r-''-T""...L--r-''-,...--~
CARRY·
OUT
O-:4-....-~'""'"-.....- .....~-..,
i+------f.!!.o CLOCK
D~~~~~~ o-4---r~~I~:-r-:~T~;t==:::!1
LATCH
ENABLE
,..JLr--"'---'''--....L::---'I.::...,
BOUT
COUT
DOUT
GNO
13·17
04r---t...::.:;:J'::';:.L:;:J':;~j:==:1
Segment Output Driver
Input Protection
fROM
INPUT
DECODER
OUTPUT
"---"",,S
~1L,
Segment Identification
Common Cathode LED Display
MM14C926
MM14C92S
MM74C921
M""C02B
BV,7V
y
I ' -I
1-1 I
!~~~~
,=_,e,C ,I
o'~' _
LI:;
switching time waveforms
Input Waveforms
Multiplexing Output Waveforms
I
CLOCK
r-l
' r-l
I
--.J
L....J
L--.J
tSETfCKLE,I--1
LATCH
ENABLE
I
Aou,Ji!---_----"1
n
1-71J2T-II--IIJZT
BOUT
----~
tOUT
MM74C926
CA,RRY.OUT
~----------
n
----~
_ _ _---'
RESET
I~R--
Carry-Out Waveforms
Dour
T= llfMUX
13·18
MM74C921
CARRY·OUT
L-_ _
r----1
.
L--
---1
COUNT
5999-6000
COUNT
9999-0000
COUNT
5599-6000
COUNT
9599-0000
r------1
--.....J
L--
Functional B'locks
~National
~ Semiconductor
NSB5388 3 1/2-Digit 0.5 Inch LED Display
General Description
The NSB5388 is a 3 1/2-digit, 0.5 inch high GaAsP
LED display. Basically a common cathode multiplexed
display, the NSB5388 features separate access to the
± sign and decimal points and is directly compatible with
the ADD3500, ADD3501 DVM circuit. Electrical connection is by PCB type terminals on the edge of the
display.
Rosin core solder, solid core solder, and low activity
organic fluxes are recommended. Freon TF, Isopropanol,
Methanol or Ethanol solvents are recommended only at
room temperature and for short periods. The use of
other solvents or elevated temperature use of the recommended solvents may cause permanent damage to the
lens or display.
The optical design of this unit creates a distinct, easy to .
read display with a wide viewing angle, excellent ONI
OFF contrast and segment uniformity. The NSB5388
provides tl)e designer with an effective, easy to implement answer to the need for an inexpensive large numeric
display.
•
Applications.
Digital instrumentation
Power supply readouts
Multimeters
Panel meters
Recommended Display Processing
The multidigit series display is constructed on a standard
printed circuit board substrate and covered with a
plastic lens. The edge connector tab will stand 230°C
for 5 seconds. Permanent damage to the display will
result if lens temperature exceeds 70°C. Since the display is not hermetic, immersion of the entire package
during flux and clean operation may cause condensation
of flux or cleaner on the underside of the lens. Only the
edge connectors should be immersed.
Absolute Ratings
Average Current per Segment
Peak Current per Segment
Rev.erse Voltage per Segment
Operating and Storage Temperature
Relative Humidity at 35°C
Lead Temperature (Soldering,
5 seconds)
Electrical and Optical Characteristics
PARAMETER
20 mA max
75 mA max
3.0V max
-20°C to +70°C
98%
230°C
T A = 25°C
TVP
CONDITIONS
MIN
Segment Light Intensity (peak)
10 mA/Seg. Peak
0.10
0.20
Digit and D.P. Light Intensity (Peak)
10 mA/Seg. Peak
0.80
1.6
Segment Forward Voltage
10 mA/Seg. Peak
Segment Reverse Voltage
100IlA/Seg.
1.7
3.0
8.0
MAX
UNITS
mcd
mcd
2.0
V
V
Peak Wavelength
660
Spectral Width, Half-Intensity
40
nm
Viewing Angle, Off Axis
60
degr~es
'±33
%
Intensity Matching
10 mA/Seg. Avg.
13-19
nm
NSB5388
Typical Applications
NSB5ll1
12
l
1'-'
1
I---;;~;;;;;;;;;~--l
LMOl~0.5!
ii "",""
~R
i
[
/
LMl09
>7V
JODmA
I
f~~ ~a-
!lID'
=r
Tv
.1.FI
10 I
VOCI
O.I.F
~,
~"N914
"",""
.
20n
Rl
R2[
.
I
!'_1%1I
I
POWER
GNO
r s4 A
'"
T
I
I
22Mn
I
L
____
OFFSET
ADJUST
SIGNAL
GNO
17
61
19
J. ~
l
.
I
I
I
I
71
20
~V"
r'""--
II
VSS
1. ~
1. l
J.
r
--'
. r ~::--:k- ~
I
51
I
.~ ~~
L-.
w
o
16
OS75492
212
I
-
ZI
41
B2Uu:
Il-I l-Il-I i!
IT/~T/:=JT/~T :
17
-'-
~
115
•2»2
"~
2Stt--,
'I
7.5k
200n .
Rl
. 16
17
~
II
<
~
"m
g
..
19
20
g
....
.. ..L . . ..
..
,
21
;;;
::;
23
i5
::;
W
::;
'"
2S'
24
;;;
::;
'"
t6
~
2
- .
27
121
N
lOOk
AOOlSOICCN
__-.l
\
..;±:
<:
I
0.41
Tr
(l)F
~
p4
III
<:
z
1:
.
~
....
~
~
112-'11
po
.. ,.
~!!l
~
c
;;:
~g
z"
< ....
.... z
19
IB
m<
,.
.. .
·2
~
~
~
c
P
6
~
S
.
14
g
~
Jl
R'
g
2
1
*O.47.F
(3)
lOOk
1
.
+ 1Dpf
Tl0VoC
.VIN
OVTo
+1.999V
Note 1: All resistors 1/4W ±5% unless otherwise specified.
Note 2: All capacitors ±10%.
Nota 3: Low leakage capacitor required.
Note 4: Rl R2/Rl + R2
FIGURE 1.3 1/2·Digit DPM. +1.999V Full-SCale
~
R3 ±250.
Typical Applications
(Continued)
120n
NSBS3B8
43
12
330
hIT
:Jl
r-----------l
f---1 ___..:2..:.V..:.R..:.;EFERENCE
lM309
DR
1
16
17
19
I
lM340-5
1
232
1
;1'101
....,
20n
---.....L
1
+2500
-p'
TSVDC
r--
'----4------+-I1-t---,
250pF
w
J £~~onI17
~
liB
IS
50k
150k
~~
g
.~
'~
~
OFFSET
~
ADJUST
~
GUARD
12
Mil
»-----.. .
lOOk
~
~
~
119
z
~
t:
~
"c;
:::;
18
0
ADD3501CCN
~dj
"
z
n
~
g g
0
<
"I "1:
4 3 111
r r
n-<
<
-<
£
~
110
0"
,,~
<-<
19
"
5~
~n
m<
IB
0
0
J,
O.47jlF
JIJI
6
1
Is
14
3
1
I'
11
51k ~ 51k
lOOk '0.01%
>
14 15
":::;c; c"
O.2V
~
VI-J
"c;
:::;
~I~~01~~
<
d
13
21
1,1
§
-<
A
lV
v(+) )
Sk
,
....!. 10 pF
T 10VDC
Note 1:
Note 2:
Note 3:
Note 4:
All resistors 1/4W ±5% unless otherwise specified.
All capacitors ±10%.
Low leakage capacitor required.
R1 R21R1 + R2 = R3 ±25£1.
FIGURE 2. 3 112-Diglt DVM, 4-Decade, ±O.2V, ±2V, ±20V and ±200V Full-Scale
88£S8SN
co
~
Pin Connections
it)
m
U)
Z
PIN NO.
ELECTRICAL
CONNECTION
1
Digit No .. 1 Segment G Anode
2
Digit Nq. 1 Segment G Cathode
3
Digit No. 1 S~gment H Anode'
4
Digit No.1 Segment J Cathode'
5
Digit No.1 Segment DP An6de
6
Digit No.2 Segment DP Anode
7
. Digit No.3 Segment DP Anode
8
Digit No.4 Segment DP Anode
9
Segment D Anode
10
Segment C Anode
11
Segment B Anode
12
Segment A Anode
13
Segment E Anode
14
Segment F Anode
15
Segment G Anode
16
Digit No.1 Cathode
17
Digit No.2 Cathode
18·
NC
19
Digit No.3 Cathode
20
Digit No.4 Cathode
*Segments Hand J internali v connected in series
Phy~ical Dimensions
inches (millimeters)
----------------.---(~::~------------------~I
1----~-lSPACES@ ,~~5::1~ (~~5.~:)----------1
" . TOl NDN·ACCUM
-1
1.0110
(2540)
D.1D11
!
"T'
"'["
DADO
0100
2GPLACES (2540 )
B.MB
1---------------19 SPACES *I:.~::) " (4~~::D)·-------;---:-I
'J
I1.01ii
0.0&2
~
DIAMETEII
HOLE20
PLACES
1--'l.On,UAK
,.,..
11.280
--(1.110'--
Note 1: Material: super-punch circuit board or approved equivalent 0.062 thick.
Note 2: All tolerances are 0.015 (0.38).
13·22
~National
Functional Blocks
~ Semiconductor
NSB5918 3 3/4-Digit 0.5 Inch LED Display
General Description
The NSB5918 is a 3 314-digit, 0.5 inch high GaAsP
LED display. Basically a common cathode multiplexed
display, the NSB5918 features separate access to the'
± sign and decimal points and is directly compatible
with the ADD3701 DVM circuit. Electrical connection
is by PCB type terminals on the edge of the display'. The
3 314-digit is distinguished from 3 1/2 and 4 1/2-digit
designs by the fact that the overflow sign is followed
by 4 full 7-segment digits.
of flux or cleaner on the underside of the lens. Only the
edge connectors should be immersed.
'
Rosin core solder, solid core solder, and low activity
organic fluxes are recommended_ Freon TF, Isopropanol,
Methanol or Ethanol solvents are recommended only at
rodm temperature and for short periods. The use of
other solvents or elevated temperature use of the recommended solvents may cause permanent damage to the
, lens or display.
The optical design of this unit creates a distinct, easy to .
read display with .a wide· viewing angle, excellent ONI
OFF contrast and' segment uniformity. The NSB5918
provides the designer with an effective, easy to implement answer to the need for an inexpensive large numeric
display.
•
Recommended Display Processing
Absolute Ratings
The multidigit series display is constructed on a standard
printed circuit board subst~ate and covered with a
plastic lens. The edge connector tab will stand 230°C
for 5 seconds: Permanent damage to the display will
result'if lens temperature exceeds 70°C:Since the display is not hermetic, immersion of the entire package
during flux and clean operation may cause condensation
Average Current per Segment
Peak Current per Segment
Reverse Voltage per Segment
Operating and Storage Temperature
Relative Hu~idity at 35°C
Lead Temperature (Soldering,
5 seconds)
EI~ctrical
and Optical Characteristics
PARAMETER
Applications
Digital instrumentation
Power supply readouts
Multimeters
Panel meters
20 rnA max
75 rnA max
3.0V max
-20°C to +70°C
98%
T A = 25°C
- CONDITIONS
MIN
Segment Light Intensity
10 mA/Seg. Avg.
0.10
TYP
0.20
mcd
Digit and D.P. Light Intensity
10 mA/Seg. Avg.
,0.80
l.fl
mcd
Segment Forward Voltage
10 mA/Seg.
Segment Reverse Voltage
100 !lA/Seg.
1.7
3.0
MAX
2.0
UNITS
V
8.0
V
Peak Wavelength
660
nm
Spectral Width, Half-I ntensity
40
nm
Viewing Angle, Off Axis
60
degrees
±33
%
Intensity Matching
10 mA/Seg. Avg.
13-23
NSB5918
-I
'<
NS85918
43
r-----
"!.cr
»
""2-c::r
!.
> 1V
.------------,
2V REFERNCE
I
~~
I
0'
:::J
(II
I
232
±Ik
I
I
~nl_
POWER GND
>-.....- ....f--4-+--"71I\'i:--..---j.J
'"~
:t
r
I
~
l
I
I
1..._____
22Mn
..--------.f----1
I
ru
iI
18
I
19
20
21
22 -
23
24
25
28
~~g~BS!:~
~
I
I
:
V~
F-----t
-t
CJ
lOOk
_...1
ADD3101CCN
DFFSET
ADJUST
SIG::~>
I I
j
"
,,~
""~~
",.
z'"
<-t ;;1<
~u,
~r~
19
18
,.
z
~
.,"
"
"11
~
r
1&
15
<
g
12
11
g
~
14
3
1
lOOk
OVTO>
VIN
+1.999V
T
FIGURE 1.3 3/4-Digit DVM, +3.999 Count Full-Scale
Note 1:
Note 2:
Note 3:
Note 4:
+ 10.F
10VDC -
All resistors 1/4W ±5% unless otherwise specified.
All capacitors ±10%.
Low leakage capacitor" required.
R1R2/Rl + R2 = R3 ±25n.
-~
::J
tlSVAC
"
r.:-:-
~
,.-------------,
,I
H~+---2V-AE.,FEANCE
I
CJ:iJ n 0 OOu."
-;Pto_u u u. ~
:.~"
.•.
!
I
l>
'tI
"2-
0'
a0'
til
(5
o
~
2121
""
:r
c:
50'"
-+--t-
~
I
_"F15VDC
!.
::::J
1
.2500
~0'
tOZklf
I
n
I
I
r
I
Cr'
I
'"t:n
1
1
1
4QOk
:!:1%
GUARD
»____-1
mAcE3r4
-v •
VI+) ),-
5;
ADD3701CCN
1 MU:!:l%
'WI! -
I
!~~k
\
~..LD.41
T III
/'Vvl
"F
400V
1!
~
g
"1'1
<
j14"
~ ~
<
:s
in
2
£
I
-t
1'2
n~ ~n
m
18
~ ~~ ~~
1'0 (9
~
0>
O
O.041J1f
~
0
h
a
I I
-6
5
~
i
iL
14 13 121
--=r,ll
51k
>m
....!lDJ.lF
L-------~r------------
T'0VDC
90.
:10.81%
VI-l
>
•
'0'
:to.Dl%
1M"
±1%
Note 1:
Note 2:
Note 3:
Note 4:
All resistors 1/4W ±5% unless otherwise specified.
All capacitors ±10%.
Low leakage capacitor required.
R1 R2/Rl + R2 = R3 ±25!l..
,FIGURE 2.3 3/4-Digit DVM, 4-Decade. ±O.4V. ±4V. ±40V and ±400V Full-Scale
8l6SBSN
co
0;
Pin Connections
It)
CD
UJ
Z
PIN NO.
ELECTRICAL
CONNECTION
1
Digit No.1 Segment G Anode
2
Digit No.1 Segmenf G Cathode
3
4,
Digit No.'1 Segment H Anode"
5
Digit No. '2 Seg~ent DP Anode
6
Digit No.3 Segment DP Anode
7
Digit No.4 Segment DP Anode
Digit No.1 Segment J Cathode"
8
Digit,No. 5 Seg~ent DP Anode
9
Segment D Anode
10
Segment C Anode'
11
Segment 8 Anode
12
Segment A Anode
13
Segment E Anode
14
Segment F Anode
Segment
16
Digit No.2 Cathode
17
Digit No.3 Cathode
18
NC
19
Digit No.4 Cathode·
20
Digit NO',5 Cathode
;*~egments
Physical Dimensions,
c; Anode
15
Hand J inte'rnally.connected 'in series
inches (millimeters)
7 TVP
[I+--ECJDh
1.1DD
(ZU4)
901D' DIAPAD
(1.111
--+-~--'!lSPAI:ES~~~~: :
TOL NON·ACCUM
,:::,----------1
4SPACES@ f~:::1 "1!:::'-------1
lOL NON·ACCUM
Note 1: Material: super-punch circ~it board or approved equival~nt 0.062 thick ..
Note 2:, All tolerances are 0.015 (0.38),
13-26
Section 14
Application Notes
I
I
I
I
I
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
I
,I
I
I
!
I
I
I
I
I
I
I
National Semiconductor
Application Note 156
Jim Sherwin
February 1976
Specifying AID
and ·01A Converters
l>
ZI
.....
C1I
0)
en
'C
CD
n
_.
=i;
'<
::::s
CC
l>
C
........
Q)
::::s
Q.
C
l>
........
The specification or selection of analog·to·digital (AID)
or digital·to·analog (D/A) converters can be a chancey
thing unless the specifications are understood by the
person making the selection. Of course, you know you
want an accurate converter of specific resolution; but
h~w do you insure that you get what you want? For
example, 12 switches, 12 arbitrarily valu'ed resistors, and
a reference will produce a 12·bit DAC exhibiting 12
quantum steps of output voltage. In all probability, the
user wants something better than the expected perfor·
mance of such a DAC. Specifying a 12·bit DAC or an
ADC must be made with a full understanding of accuracy,
linearity, differential linearity, mondtonicity, scale, gain,
offset, and hysteresis errors.
Accuracy is sometimes considered to be a non·specific
term when applied to D/A or AID converters. A linearity
spec is generally .considered as more descriptive. An
accuracy specification describes the worst case deviation
of the DAC output voltage from a straight line drawn
between zero and full scale; it includes all errors. A
12·bit DAC could not have a conversion accuracy better
than ±Y:z LSB or ±1 part in 212+1 (±0.0122% of full
scale due to finite resolution). This would be the case in
figure 1 if there were no errors. Actually,' ±0.0122% FS
represents a deviation from 100% accuracy; therefore
accuracy shoUld be specified as 99.9878%. However,
convention would dictate 0.0122% as being an accuracy
spec rather than an inaccuracy (tolerance or error) spec. '
This note explains the meanings of and the relationships
between the various specifications encountered in AID
and D/A converter descriptions. It is intended that the
meanings be presented in the simplest and clearest.
practical terms. Included are transfer curves showing the
several types of errors di~cussed. Timing and control
signals and several binary codes are described 'as they
relate to AID and DIA converters.
Accuracy as applied to an ADC would describe the
difference between the actual input voltage and the full·
scale weighted equivalent of the binary output code;
included are quantizing and all other errors. If a 12·bit
ADC is stated to be ±1 LSB accurate, this is equivalent
to ±0.0245% or twice the minimum possible quantizing
error of 0.0122%. An accuracy spec describes the
maximum sum of all errors including quantizing error,
but is rarely provided on data sheets as the several errors
are listed separately.
MEANING OF PERFORMANCE SPECS
Resolution describes the smallest standard incremental
change in output voltage of a DAC or, the amount of .
input voltage change required to increment the output of
an ADC between one code change and the next adjacent
code change. A converter with n switches can resolve 1
part in 2n. The least significant increment is then 2· n, or
'one least significant bit (LSB). In contrast, the most
significant bit (MSB) carries a weight of 2.1,. Resolution
applies to DACs and ADCs, and may be expressed in
percent of full'scale or in binary bits. For example, an
ADC with 12·bit resolution could resolve 1 part in 212
(1 part in 4096) or 0.0245% of full scale. A converter
with 10V full scale could resolve a 2.45mV input change.
Likewise, a 12·bit DAC would exhibit an output voltage
change of 0.0245% of full scale when the binary input
code is incremented one binary bit (1 LSB). Resolution
is a design parameter 'rather than a performance specifi·
cation; it says nothing about accuracy or linearity.
14·.1
FS
O~----------------000 001 010 011 100 101 110 111
DIGITAL CODE
FIGURE 1. Linear DAC Transfer Curve Showing Minimum
Resolution Error and Best Possible Accuracy
()
o::::s
<
CD
...S-en
~
~
CP
>
C
o
o
«.......
c
"0
C
co
C
Quantizing Error is the maximum deViation from a
straight line transfer function of a perfect ADC. As, by
its very nature, an ADC quantizes the analog input into
a fihite number of output codes, only an infinite
resolution ADC would exhibit zero quantizing error. A
perfect ADC, suitably offset Y, LSB at zero scale as
shown in figure 2, exhibits only ±y, LSB maximum
output error. If not offset, the error will be +6 LSB as
shown in figure 3. For example, a perfect 12·bit ADC
will show a ±y, LSB error cif ±O.0122% while the
quantizing error of' an 8·bit ADe is ±y, part in 2 8 or
±O.195% of full scale. Quantizing error is not strictly
applicable to a DAC; the equivalent effect is more
properly a resolution error.
,
FS
./
IDEAL SLDPE
/
/
/}
1 LSB
~ / / / /-
/
/
O~----------------~
000 001 010 011 100 101 110 111
DIGITAL CDDE
.......
«
FIGURE 4. Linear,1 LSB Scale Error
m
c
111
.-
~
o
'CP
c.
110
w
c
B
Gain Error is essentially the same as scale error for an
ADC. In the case of a DAC with current and voltage
mode outputs, the current output could be to scale
while the voltage output could exhibit a gain error. The
amplifier feedback resistors would be trimmed to correct
the gain error.
101
lOU
..
~
~ 011
cOlO
C/)
Offset Error (zero error) is the output voltage of a DAC
'with zero code input, or it is the required mean'value of
input voltage of an AQC to set zero code out. (See
figure 5.) Offset error is usually cau~ed by amplifier or
comparator input offset voltage or current; it can usual,ly
be trimmed to zero with an offset 'zero adjust potentio·
meter external to the DAC or ADe. Offset error may be
expressed in % FS or in fractional LSB.
001
0000
t
FS
II LSB
FIGURE 2. ADC Transfer Curve, Y.. LSB Offset at Zero
FS
111
/
/
110
101
'w
8 100
.
~
011
Ci 010
001
FS
ANALOG INPUT
DIGITAL CDDE
FIGURE 5. Linear;Y.. LSB Offset Error
FIGURE 3. ADC Transfer Curve, No Offset
Scale Error (full scale error) is the departure from design
output'voltage of a DAC for a given input code, usually
full·scale code. (See figure 4.) 111 an ADC it is the depar·
ture of actual input voltage from design input voltage for
a full·scale output code. Scale errors can be caused by
errors in reference voltage, ladder resistor values, or
amplifier gain, et. al. (See Temperature Coefficient.)
Scale errors may be corrected by adjusting output
amplifier gain or refe'rence voltage. If the transfer curve
resembles that of figure 7, a scale adjustment at % scale
cquld improve the overall ± accuracy compared to an
adjustment at full scale, '
Hysteresis Error in an ADC causes the voltage at which' a
code transition occurs to be dependent upon the direction
from which the transition is approached. This is usually
caused by hysteresis in the comparator inside an ADC.
Excessive hysteresis may be reduced by ,design; however,
some slight hysteresis is inevitable and may be objec·
,tionable in converters if hysteresis approaches Y, LSB.
Linearity, or, more accurately, non·linearity specifica·
tions describe the departure from a linear transfer curve
for either an ADC or a DAe. Linearity error does not
include quantizing, zero, or scale errors. Thus, a specifi·
14·2
l>
cation of ±~ LSB linearity implies error in addition to
the inherent ±~ LSB quantizing or resolution error. In
reference to figure 2, showing no errors other than
quantizing error, a linearity error allows for one or more
of the steps being greater or less than the ideal shown.
Figure 6 shows a 3-bit DAC transfer curve with no more
than ±~ LSB non·linearity, yet one step shown is of zero
amplitude. This is within the specification, as the maxi·
mum deviation from the ideal straight line is ±1 LSB
(~ LSB resolution error plus ~ LSB non·linearity). With
any linearity error, there is' a differential non-linearity
(see below). A ±~ LSB linearity spec guarantees
monotonicity (see below) and';;; ±1 LSB differential nonlinearity (see below). In the example of figure 6, the
code transition from 100 to 101 is the worst possible
non-linearity, being the transition from 1 LSB high at
code 100 to 1 LSB low at 110. Any fractional nonlinearity beyond ±~ LSB will allow for a non-mo{lotonic
transfer curve. Figure 7 shows a typical non-linear curve;
non-linearity is 1y.. LSB yet the curve is smooth and
monotonic.
FS
1
1 LSB DlFF
NDN. UNEA
5
~c
Yz LSD DIFF
NON·LINEAR
g
+
.'"
/
/ } LSB
z
o /
ODD 001 010 011 100 101 110 111
DIGITAL CODE
FIGURE 6.
Differential Non-Linearity, indicates the difference between actual analog voltage change and the ideal (1 LSB)
voltage change at any, code change of a DAC. For
example, a DAC with a 1.5 LSB step at a code change
would be said to exhibit ~ LSB differential non,linearity (see figures 6 and 7). Differential non-linearity
may be expressed in fractional bits or in % FS.
Differential linearity specs are just as important as'lin·
earity specs because the apparent quality of a converter
curve can be'significantly affected by differential nonlinearity even though the linearity spec is· good. Figure 6
shows a curve with a ±~ LSB linearity 'and ±1 LSB
differential non-linearity while figure 7 shows a curve
with +1 y.. LSB linearity and ,±~ LSB differential non·
linearity. In many user applications,'the curve of figure 7
would be preferred over that of figure 6 because the
curve is smoother. The differential non-linearity spec
describes the smoothness of a curve; therefore it is of
great importance to the user. A gross example of differential non-linearity is shown in figure 8 where the
linearity spec is ±1 LSB and the differential linearity
spec is ±2 LSB. The effect is to allow a transfer curve
with grossly degraded resolution; the normal a·step curve
is reduced to 3 steps in figure a. Similarly, a 16·step
curve (4·bit converter! with only 2 LSB differential nonlinearity could be reduced to 6 steps (a 2.6-bit conver·
ter?). The real message is, "Beware of the specs."
Do not ignore or omit differential linearity characteristics on .a converter unless the linearity spec is tight
enough to guarantee the desired differential linearity. As
this characteristic is impractical to measure on a production basis, it is rarely, if ever, specified, and linearity is
the primary specified parameter. Differential non·linear·
ity can always be as much as twicethe non-linearity, but
no more.
±% lSB Non-linearitv (Implies 1, lSB Possible
Error), 1 lSB Differential Non-linearitv (Implies
FS
Monotonicity)
/
j//
/
/'
5
~
% LSD DIFF
NDN.UNEA")
FS
c
'"
c
2LSB DlFF
NDN'r EAR / /
5
~
=
'"
::
'"z
'"
%LSBDIFF'"
NON·L1NEAR
'"z
'"
/
~
LSD
/
'3,
~SB
--!t,
~
h-/""';"/
,/
oDOD
/
JLSB
2LSB DI FF
NON·LlNEAR
DOl DID' 011 100 101 110 111
DIGITAL CODE
O~--~-------------000 001 010 011 100 101' 11D 111
FIGURE B..• 1 LSB Line.r,' 02 LSB Differential Non·linear
DIGITAL CqDE
FIGURE 7. ,111. lSB NO,n·linear, % lSB Differential NonLinearity
Linearity specs refer to either ADCs or to DACs, and do
not include q'uantizing, gain, offset, or scale errors.
Linearity errors are of prime importance along with
differential linearity in either ADC or :DAC specs, as all
other errors (except quantizing, and temperature and
long-term drifts) may be adjusted to zero. Linearity
errors may be expressed in % FS or fractional LSB.
,14-3
Monotonicity. A monotonic curve has no change in sign
of the sio'pe; thus all' incremental ele';'ents ot' a mono·
tonically increasing curve will have positive or zero, but
never negative slope. The converse is true for decreasing
curves. 'The transfer curve' of a ';'onotonic' DAC will
contain steps of only positive or zero height, and no
negative steps. Thus a smooth line connecting all output
voltage points will contain no peaks or dips. The transfer
function of a monotonic ADC will provide no decreasing
output code for increasing input voltage.
ZI
......
(J1
CJ)
en
"C
CO
n
~
_.
:::J
CC
l>
.......
C
Q)
:::J
Q.
C
.......
l>
(')
o
:::J
<
CO
i...
en
~
~CI)
c>
o
u
«.......
c
'tJ
C
CO
C
.......
«
Figure 9 shows a non-monotonic DAC transfer curve.
For the curve to be non-monotonic, the linearity error
must exceed ±y. LSB no' matter by how 'little. The
greater the linearity error, the more significant the
negative step might be. A non·monotonic curve may not
be a special disadvantage in, some systems; however, it is
a disaster 'in closed-loop servo systems of any type
(including a DAC-controlled ADC). A ±'h LSB maximum
linearity spec on an n-bit converter guarantees monotonicity to n bits. A converter exhibiting more than ±'h
LSB non-linearity may ,be monotonic, but is not
l1ecessarily monotonic. For example, a 12·bit DAC with
±'h bit linearity to 1Obits (not ±'h ,LSB) will be monotonic at 10 bits but mayor may not be monotonic at12
bits unless tested and guaranteed to, be 12-bit monotonic .
lV/OIV
_
I ~t.: ~
II
2",/OIV
S.tl!LlNG TIM
OAC OUTPUT
CONTROL LOG C
I-
SLEV TIME
(a) Full-Scale Step
0)
c
~
u
FS
USB OIFF
NON·lINEAR
J
Go)
c.
"
10mV/DIV
\/
/~/ J1%LSS"
CONTROL LOGIC
I I
1% 1 / ILSB
tJ)
LSB
"
I
\.
lHSBOlfF
I~
co'
Lt)
-
SETILING TIME
I
.....
,1,1
z•
«
'/lsJDlV
0011 001,010 011 100 101 110 111
OIGITAL COOE
(b) 1 LSB Step
FIGURE 9.
Non-Mo~otonic
(Must be
'>
1% LSB Non·Linear)
FIGURE 10.
Settling Time is the elapsed time after a code transition
for DAC output to reach final value within specified
limits, usually ±'h LSB. (See also Conversion Rate below.)
Settling time is 'often listed along with a slew ratespecification; if so, it may not include slew time. If no
slew rate spec is included, the settling time spec must be
expected to include slew time. Settling time is usually
summed with slew time to obtain total elapsed time for
the output to settle to final value. F:igure' 10 delineates
that part of the total'ehipsed time whIch is considered to
be slew, and that part which is settlirig time. It is,
apparent from this figure that' the total time is greater
for a major than for a minor code change due to
amplifier slew limitations, but settling time may also be
,different depending upqn amplifier overload recovery
characteristics.
Slew Rate is an inherent limitation of the output
amplifier in a DAC which limits the rate, of .change of
output voltage after code ,tran~itions. Slew rat~ is u~ually
anywhere from 0.2 to several hundred volts/Ils.' Delay in
reaching final vaiu'e of DAC output voltage is the sum of
slew time and settl!ng time as' shown in figure '10.
Overshoot and Glitches 'occur whenever a code transition
occ\Us in a DAC. There are two causes. The 'current
output of a DAC contains switching glitches due to
possible asynchronous switching of the bit' currents
(expected to be worst at half·scale transition when all
14-4
DAC Slew and Settling Time
bits are 'switched). These glitches are- normally of
extremely short duration but could be of 'h scale
amplitude. The current switching glitches are generally
somewhat attenuated at the voltage output of the DAC
because the output amplifier is unable to slew at a very
high rate; they are, however,' partially coupled around
the amplifier via the amplifier feedback network and
seen at the output. The output amplifier introduces
overshoot and some non-critically damped ringing which
may' be minimized but not entirely eliminated except at
the expense of slew rate and settling time.
Temperature Coefficient of the various components of a
DAC or ADC can produce or increase any of the several
errors as the operating temperature varies. Zero scale
offset error can change due to the TC of the amplifier
and comparator input offset voltages and currents. Scale
error can occur due to shifts in the reference, changes in
ladder resistance or non-compensating RC product shifts
in'dual-slope ADCs, changes in beta or reference current
in current switches, changes in amplifie'r bias current, or
drift in amplifier gain-set resistors. Linearity and monotonicity of the DAC, can be affect!!d by differential
temperature drifts of the ladder resistors and switches.
Overshoot, settling time, and slew rate can be affected
by temper.atLire'due to internal change in amplifier gain
and bandwidth. In short, every specification except
resolution 'and quantizing error can be affected by
temperature changes:'
l>
Z
Long-Term Drift, due mainly to resistor and semiconductor aging can affect all those characteristics which
temperature change can affect. Characteristics most
commonly affected are linearity, monotonicity, scale,
and offset. Scale change due to reference aging is usually
the most important change.
Supply Rejection relates to the ability of a DAC 'or ADC
to maintain scale, offset, TC, slew rate, and linearity
when the supply voltage is varied. The reference must, of
course, remain constant unless considering a multiplying
DAC. Most affected are current sources (affecting
linearity and scale) and amplifiers or comparators
(affecting offset and slew rate). Supply rejection is
usually specified only as a % FS change at or near full
scale at 25° C.
Conversion Rate is the speed at which an ADC or DAC
can make repetitive data conversions. It is affected by
propagation delay in counting circuits, ladder switches
and comparators; ladder RC and amplifier settling times;_
amplifier and comparator slew rates; and integrating time
of dual-slope converters. Conversion rate is specified as a
number of conversions per second, or conversion time is
specified as_ a number of microseconds to complete one
conversion (including the effects of settling time). Sometimes, conversion rate is specified for less than full
resolution, thus showing a misleading (high) rate.
Clock Rate is the minimum or maximum pulse rate at
which ADC counters may be driven. There is a fixed
relationship between the minimum conversion rate and
the clock rate depending upon the converter accuracy
and type. All factors which affect conversion rate of an
ADC limit the clock rate.
coded system. For example, a 12·bit BCD system has a
resolution of only 1 part in 1000 compared to 1 part in
4096 for a binary system. This represents a l,oss in
resolution of over 4:1.
Offset Binary is a natural binary code except that it is
offset (usually Yo scale) in order to represent negative and
positive values. Maximum negative scale is represented to
be all "zeros" while maximum positive scale is represented
as all "ones." Zero scale (actually center scale) is then
represented as a leading "one" and all remaining "zeros."
The comparison with binary is shown in figure 11.
Twos Complement Binary is an alternate and more
widely used code to represent negative values. With this
code, zero arlCj positive values' are represented as in
natural binary while all negative values are represented
in a twos complement form. That is, the twos comple·
ment of a number represents a negative value so that
interface to a computer or microprocessor is simplified.
The -twos complement is formed by complementing each
bit and then adding a 1; any overflow is neglected. The
decimal number -8 is represented in twos complement
as follows: 'start with binary code of decimal 8 (off
scale for. ± representation in 4 bits so not a val id code in
the ± scale of 4 bits) which is 1000; complement it to
0111; add 0001 to get 1000. The comparison with offset
binary is shown in figure 11. Note that the offset binary
representation of the ± scale differs from the twos
complement representation only in that the MSB is
complemented. The conversion from offset binary to
twos complement only requires that the MSB be inverted.
110
..
w
Output Drive Capability describes the digital load driving
capability of an ADC or the analog load driving capacity
of a DAC; it is usually given as a current level or a voltage
output into a given load.
8
101
100
...~ 011
5
a 010
001
CODES
Complementary Binary (or Inverted Binary) is the
negative true binary system. It is identical to the binary
code except that all binary. bits are inverted. Thus, zero
scale is all "ones" wl1ile full scale is all ";leros."
Binary Coded Decimal (BCD) is the representation of
decimal numbers in binary form. It is useful in ADC
systems intended to drive decimal displays. Its advantage
over decimal is that only 4 lines are needed to represent
10 digits. The disadvantage of coding DACs or ADCs in
BCD is that a full 4 bits could represent 16 digits while
only 10 are represented in BCD. The full·scale resolution
of a BCD coded system is less than that of a binary
0)
en
'C
CD
(')
_.
~
:::J
Ul
l>
......
C
OJ
:::J
Co
C
......
l>
oo
:::J
<
CD
i...
0.
111
Input Impedance of an ADC describes the load placed
on the analog source.
Several types of DAC input or ADC output codes are in
common use. Each has its advantages depending upon
the system interfacing the converter. Most codes are
binary in form; each is described anc;l compared below.
Natural Binary (or simply Binary) is the usual 2 n code
with 2, 4, 8, 16, ... , 2 n progression. An input or output
high or "1" is considered a signal, whereas a "0" is
considered an absence of signal. This is a positive true
binary signal. Zero scale is then all "zeros" while full
scale is all "ones."
•
"""
U'I
~
%
t
'Is
ANALOG SCALE
(al Zero to + Full-Scale
011 011 111
010 010 110
001 001 101
000
100
100 000
-%
101 111 011
110 110 DID
111 101 001
100 000
t
L OFFSET BINARY
TWOS COMPLEMENT BINARY
SIGN + MAGNITUDE
r
(bl ± Full·Scale
FIGURE 11. ADC Codas
o
~
~
CI>
>
C
o
U
~
""
C
"C
C
ca
C
""
'~
m
.5
~
(.)
CI>
Q,
(J)
co
Sign Plus Magnitude coding contains polarity
informa~ion
data is valid. Typically, an EOC output can be connected
to an SC input to cause the ADC to operate in'continuous conversion mode. In non-continuous conversion
systems, the SC signal is a cqmmand from the system to '
the ,ADC.' A DAC does not supply im EOC signal.
in the MSB (MSB '= 1 indicates a negative sign); all
other bits represent magnitude only. This ~ode is compared to 'offset bin'ary and twos complement in'figure 11.
Note that one code is used up in providing a double
code for zero.: Sign plus magnitude code is used in
certain instrument and, audio systems; its advantage is
that only one bit'need be changed for small scale changes
in the vicinity of zero; and plus and minus scales are
symmetrical: A DVM might be an example of. its use.
Clock signals are required or must be generated within
an ADC to control counting or, successive approximation
registers. The clock ,controls the conversion speed within
the Iimitati(;lOS, of the ADC. DACs do not require clock
signal~. ,
CONTROL
Each ADC must accept and/or provide digital cqntrol
signals telling it and/or the external system what to do '
and when to do it. Control signals should be compatible
with one or more ,types of logic in common use. CQntrol
signal timing must be such that the converter or connected system will accept, the signals., Common control
signals are listed, below,
Start' Conversion (SC) is a digital signal to anADC which
initiates a single conversion cycle. Typically, an SC signal
must be present'atthe fall (or rise) of the clock waveform
to initiate the cycle. A DAC needs no SCsignal; however,
such could be provided to gate digital inputs to a DAC.
End of Conversion '(EOC) is a digital signal from an ADC
which informs the extern'a'-'system that the digital output
it)
.,..
,.
Z
~
14-6
CONCLUSION
Once the user has a working knowledge of DAC or ADC
char~cteristics, and specifications, he should be able to
select a converter to suit a specific system need. The
likelihood of overspecification, and therefore an unnecessarily high cost, is likewise reduced. The user will
also' be aware that specific parameters, test conditions,
test circuits, a'nd even definitions may vary from
manufacturer to manufacturer. For practical production
reasons, parameters may not be tested in the same
manner for all converter types, even those supplied by
the same manufacturer. Using information in this note,
the user should, however, be able to sort out and under- .stand those specifications (from' any manufacturer)
pertinent to 'his needs.
»
z
National Semiconductor
Application Note 159
Jim·Sherwin
April 1976
Data Acquisition System
Interface to Computers
....
I
01
to
c
Q)
Q)
»
(")
.c
_.
INTRODUCTION
The need of interfacing several analog data channels to
computers has not escaped the attention· of the data
system firms. There are presently available a number of
data acquisition units (DAUs) which will directly interface 8-64 analog data channels to one or more types of
computers or microcomputers, and more appear on the
market almost monthly. Some of these DAUs are even
constructed to plug into the mainframe of the cOt!1puter
for which they are designed. Nearly all of these commercially available DAUs are of more or less ·conventional design, operating in either a r~ndom' channel
address or sequential address mode. Figure 1 shows a
typical functional· diagram of such a random channel
address DAU. Its advantages are simplicity, straightforward design, and comparatively low cost (depending
upon performance and .special features). In operation,
the computer addresses a specific channel, the analog
multiplexer (MUX) is set to the desired channel, a
sample and hold (S&H) circuit acquires and holds the
analog signal, an analog-to-digital converter (ADC)
digitizes the signal, a ready signal is returned to the
computer, and the data is presented to the data bus via
TRI-STATE® bus drivers. If the data is 12-bit and the
data bus is 8-bit, the data word must be broken into two
bytes and addressed separately. The prime disadvantage
of these DAU designs is that the computer must either
enter a wait mode while data is readied or it can proceed
with its assigned task, watch for a data-ready flag signal,
and return for the data.
16·CH
;..
ANALOG
DATA
16·CH
MUX
From the standpoint of microprocessor system design,
it is clearly desirable to access input data as if it were
main memory. It is further desirable that input data
access time be equivalent to that of main memory so that
the processor need not enter a wait mode while data is
readied for input. One attractive method of accomplishing this is to use one AID converter (of a type containing
TR I-STATE output data latches) on each input data
channel. Henceforth I shall refer to this as parallel
conversion. Figure 2 shows such a system containing only
an address decoder and multiple AID converters with all
outputs wired in parallel onto the data bus:. Note the
absence of S&H modules.
The advantages of this DAU system are the immediate
data access and its simplicity. However; one's first
thought on considering a parallel-conversion system
might be that the cost of ADCs would exclude their
consideration. on a one-per-~hannel basis. But, although
this may hav~ been true in the past, currently available
monolithic and hybrid ADCs are priced such that this
system concept is entirely feasible. Furthermore, the
.converter price trend is definitely downward as more
monolithic units are released, so the economic feasibility
can only improve in the next few years, thus extending
the application to an ever larger segment of the market.
The ideal converter for use in the system of Figure 1
includes co~verter, cornparator, and buffered TR I-STATE
output data latches in one package. The unit would
12-BIT
ADC
S&H
CLOCK AND
TIMING LOGIC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .~CO~~~~~~OR
~
ADDRESS
FROM
PROCESSOR'
& CONTROL
CONTROL
...... TO/FROM
...._ _ _ _...
PROCESSOR'
FIGURE 1. Random-Addrossed Multiplexed DAU
14-7
s::::
tn
;::;:
O·
::::s
en
--
'<
tn
(1)
3
::::s
S'
~
Q)
(")
(1)
S'
(')
o
3
-...
"C
s::::
(1)
tn
...en
.!
:J
Co
E
o
o
ADC
.s
ADC
#1
ADC
#16
#2
Q)
(,)
~
.!
c
~r8J1J~~'
~• • • FROM PROCESSOR
ADDRESS BUS
I'
AND
CONTROL
E
Q).
en
~
FIGURE 2. Paranel Data Conversion Concept
en
c
o
E
.:J~
C"
(,)
«
CO
CO
C
m
Lt)
,...
•
Z
ZI
-a.
DATA TO
PROCESSOR
12·BIT
ADC
S& H
C1I
CO
o
Q)
Q)
CLOCK AND
SEQUENCING LOGIC
l>
n
.c
c:
ttl-----I
ADDRESS
COMPARATOR
AD~lliSS I'
ADDRESS
FROM
PROCESSOR
__C_O_N_T_R_O_L~~¥g~lRROO~
..__&
PROCESSOR
(ii'
;::;:
S'
::s
en
---...
'<'
FIGURE 3. Multiplexed Immediate·Oata·Access OAU
en
C'D
3
::s
mined from Figure 4. Sixteen channels of 10Hz data
could be available if each channel were sampled once
every 20ms. This is a data throughput rate of 16ch x
1120ms = 800Hz., The higher cost DAUs of this type
have capability of 50-100kHz throughput rates. However,
if the computer waits while. data is made ready, it will be
cO\Tlpletely occupied with gathering data when the
maximum throughput rate is utilized.
C'D
Q)
n
C'D
The parallel conversion DAU without S&H 'circuits is
destined to operate on low-bandwidth data as' indicated
in Figure 4.' To be economically feasible the ADCs must
be of low cost. This means an 8- or 10-bit successive
approximation register (SAR) or a 12-bit integrating
monolithic ADC must be used. New ADC designs using
tracking counters could ,increase data bandwidth capability over that possible witl:l SAR counters., For purely
economic reasons, then, use of parallel·conversion DAU
sy~tems will be limited:to low bandwidth data - 10-30 Hz
on 8·bit, 2-5 Hz on 10-bit, and less than 1 Hz on 12-bJt
systems. These bandwidth figures for 8- to 10-bit systems
could be considerably improve'd, say by 8-,10 times, if
tr'acking converters were used in place of SAR conv~rters.
This definitely suggests that there is a need for low-cost
tracking converters. Note that S&H circuits ani not
needed in the parallel-conversion systems.
or data throughput rate principilily by the S&H and ADC
operating times, its cost per channel is only slightly
higher than that of the conventional DAU, and it allows
the computer 'to operate in the most efficient manner.
The multiplexed DAU with memory can serve any
segment of the data market. It is limited in 'bandwidth
A comparison of system costs must include the following
for a 16-channel system. '
Parallel Coi\Ve~sion
o
(")
CONVERSION TIME illS)
o
3
"C
c:
FIGURE 4. 'Oata Bandwidth vs: Conversio~ Time
Random Addressed Multiplexed
,Multipl~xed with Memory
1 AID Converter
16 AID Converters
1 AID Converter
16 Anti-Aliasing Filters,
1 S&H Module
1 S&H Module
Control Circuits,
1 16-Chann,el Multiplexer
1 16-Channel Multiplexer
Additional power for extra' conver~ers
16 Anti-Aliasing Filters
16 Anti-Aliasing Filters
Lower data bandwidth'
More co,~plex control' circuits
1 "6,,12 RAM
Simple software
Longer data access time
More complex control circuits
Po'ssibly more complex software
'High-speed data access
Simple Software
14-9
...enCD
(I)
t..
S~
c.
'E
o
......
~
ANALOG
CHANNELS
2 EAAM3705
16·CH
MUX
o
, lF298
I,
S&H
2
3
'""---r-_..J
TO
DATA
BUS
o
o
4
5
Q)
(J
4
3
2
I
CO
't:
Sc
-E
Q)
( I)
>-
U)
6
7
ClK
DM86L13
QUAD
D·lATCH
0
FROM
ADDR
BUS
A
B
C
D
E
F
DM8131
6-BIT
MAGNITUDE
COMPARATOR
% DM8094
DM74lS74
D·lATCfj
c
.2
:t::
.~
~
0(J
«
Sco
C
0)
U')
.....
I
Z
«
FIGURE 5. Conventional DAU for 8080
The future trends' in DAU designs will include an
increasing number of paralhil-cohv,ersion DAUs, especially as cost reductions appear on' monolithic ADCs with
TRI-STATE output circuits (or latches). We should also
start to see some tracking converters in the low-cost
monolithics with TRI-STATE, output data- latches.'
Expect to see multiplexed DAUs' with memory appearing
in the near futwe. Its simplicity from a circuit and
software standpoint cannot long go unnoticed.
RANDOM ADDRESSED t;>ATA ACQUlsrTioN UNIT
A conventional, random-addressed, 16-channel, 12-bit
DAU is diagrammed in Figure 5. The analog section
contains a 16-channel analog multiplexer, a sample-andhold block, and a 12-b,it ADC. A more complete system
might contain a differential multiplexer and/or a differential (or il"!strumentation) amplifier preceding the S&H
block. The data output circuits are arranged to interface
an 8-bit data bus as found on an 8080 or 6800 microcomputer (/-IC). Since the data word is 12 bits, the /-IC
must accept it in two' 8-bit bytes, Normally the /-IC would
address the DAU with two consecutive address locations
corresponding to a 0 and a 1 at the address LSB to load
the two bytes of data. The DM8123 multiplexers are
ideally suited to this use. They have TRI-STATE output
circuits, and the chaFmel-select input, may be directly
driven from the address LSB. If a 16-bit address bus were
being' interfaced, such as in the PACE /-IC; the output
multiplexers would be ,replaced with DM8097 or equivalent TRI-STATE output buffers (see Figure 11). In
both instances, low-power versions of these parts, the
DM81 L23 and DM80L97, could be used to ,drive a
lightly loaded dpta bus. '
The address decoding, is accomplished with a DM8161
6-bit magnitude comparator 10Clking at the six most
significant address bits. These 6 bits are compared with
an address code hard wired into a DIP header, which can
be different for each DAU card in, a system. Comparing
only 6 address' bits allows a possible 64 cards in a
single system and uses up to 64 pages of memory
position. If this is not satisfactory, two address compara·
tors ORed together (DM8163) could select from 12 bits
of address. The magnitude comparator(s) plus the four
address lines to the 16·ch MUX make up the complete
address decoding. The, output of the magnitude comparator(s) indicates when this DAU has been addressed, and
the four address lines to the MUX sele,ct the 1·of-16
,channels of this DAU.
This circuit is designed to interface the 8080 /-IC. Thus,
a'memory read command MRDC must be received, and
an 'acknowledgement XACK must be issued to indicate
"when data is ready. Operation is' as follows: A valid
address on address lines A-F causes comparator output
to go low. This gates the inputs of the quad D latch to
accept the 1-of-16 address word from address lines 14.
At the occurrence of MRDC the address is clocked into
the quad D latch and presented 'to the 16-ch MUX which
selects the addressed channel. When 0: and M RDC are
both low, the output of' OR gate A goes low, which
enables the XACK signal buffer. If the address LSB is 0
(byte 1 of a 2-byte data request), OR gate B output goes
low to trigger a one-shot.
o
The one-shot circuits are a simple means of timing the
sample period and the converter start cpmmands. There
are other methods (see Figure 15) of accomplishing this
timing without the 'hazards associated with one-shot
circuits; however, the simplicity of this scheme lends'
, itself to easy understanding of the timing required. The
first one-shot generates a sample pulse of 5-30/-ls as
required for the S&H to acquire and settle to 0.01 % of
value. Its 0' output presets the single D latch (0 = 1).
The trail,ing edge of this,pulse returns the S&H to HOLD
condition and triggers the next one-shot to generate a
start conversion' command of about 3/-1s. When the ADC
completes conversion, its CC output goes low, thus
clocking a 0 into the single D latch to reset its Q output
low. Both inputs to OR gate C now being low will
enable the output MUX and return a low on the XACK
14-10
line ilJdicating to the IlC that data is ready. Address
LSB = 0 selects the 8 LSB of the data word for presen·
tation to the data bus. A subsequent address with LSB
= 1 selects the 8 MSB of the data word, but wi II not
trigger the one·shot or preset the D latch because the
output of OR gate B will remain high. Since the output
of OR gates A and ,C will be low, XACK is returned and
the output MUXs are enabled to present byte 2 of the
data word on the data bus. When MRDC returns high,
the output circuits are disabled. If the 6·bit comparator
does not see a valid address, no action is taken by the
DAU.
This represents the simplest possible DAU f9r interfacing
to computers. The interface to the 8080 is one of the
simplest. Only minor modifications are required to
interface, for example, the 6800 or PACE IlCS (see
Figures 9 and 11). The only timing anomaly in the logic
system shown is that when the XACK buffer is enabled
there will be a 10·40ns pulse of 0 output. The computer,
however, does not act on an XACK signal at this time
and so will enter a wait mode until XACK is returned
later on.
The analog signal section has purposely been omitted
from this discussion of interfacing to processors because
its details will depend upon analog signal levels. the'
possible requirement for differential channels, the pos·
sible need of. an instrumentation amplifier following the
multiplexer, and S&H timing requirements. The analog
section of the DAU may be made up of various com·
ponents, depending upon the required performance and
,operating conditions. A pair of 8·channel multiplexers
will. give the flexibility of connecting as differential
8·channel or as single ended 16·channel whereas a single
16·channel MUX with space and wiring on the board for
another 16·channel MUX would allow for either 32
channels or, 16 differential channels. A pair of AM3705s
could be used for lowest cost where analog signals are no
greater than ±5V. The S&H circuit couid be monolithic
LF198, hybrid LH0023, LH0043 or LH0053, made up
of individual discrete and integrated circuits, or it could
be any of several available modules.
The ADC used in this system may be of a conventional
design with speed and accuracy being the only important
technical considerations. No special TR I·STATE output
or output data latches are needed as the data is latched
in the register until a new start conversion (SCI command
is given. The ADC could be made up of an AD1200 ADC
building block plus DM2504 or MM74C905 successive·
approximation register, it could be an' AD1210 plus
LH0071 reference and appropriate MOS·TTL and TTL·
MOS buffers, or it could be anyone of a number of
other ADCs on the market.
Total power is about 2.8 watts and cost is about $9.50
per channel for components as indicated in Table 1.
Note that output drivers are standard TTL circuits
whereas low power TTL may be used for lower power
dissipation where a lightly loaded data bus is to be
driven.
PARALLEL·CONVERSION OATA ACQUISITION
UNIT
Parallel data conversion is likely the simplest possible IlC
data system concept which will eff~ct immediate access
to latest input data as if it were main memory. It rt:1ay be
treated as main memory by the processor and is only
slightly more complex than the simplified system of
Figure 2. The individual ADCs in Figure 2 include TRI·
STATE output for direct wire ORing on the data bus.
However, to make each capable of driving a heavily
loaded system bus would require significant and un·
necessary power dissipation in each ADC. Accordingly,
except in minimally loaded systems, a separate set of
TR I·STATE TTL output data buffers would be added to
Figure 2. Small differences in the address decoder and
control circuits will exist, depending upon which IlC
system will be used.
The control circuits are exceptionally simple, being
required primarily to accept the memory read command
and to return a memory ready signal. The most complex
part of the control circuits is that required of IlC systems
which accept data in two 8·bit bytes rather than in one
16·bit byte, yet even this added complexity is minimal.
::::J
S'
;.n
(I)
S'
o
o
3
'C
C
S'
...
tn
Table 1. Conventional DAU Power & Cost
Po (mWI
$ (100s)
1-
16·Channel MUX
300
19.55
1-
S&H
500
74.50
1-
ADC
600
40.00
2 - DM8123
Quad 2·lnput MUX
800
2.56
1 - DM8161
Hex Comparator
250
2.56
1 - DM86L13
Ouad D· Latch
30
1.28
1 - DM74LS221
Dual One·Shot
30
3.00
60
2.00
1 - DM74LS132
Ouad Schmidt NAND
1 - DM7432
Quad OR Gate
1 - DM74LS74
Dual D'F·F
1 - DM8094
TRI·STATE 4 x Buffer
100
.49
20
3.00
144
.71
2834
150.05
$9.38/Channel
14·11
D
.~
.!:::s
a.
E
<3
.s
Q)
(J
~
.!c
0)
It)
....•
Z
Z
.!..
U'I
CO
4
3
2
1
FROM
ADDR
BUS
DM74L154A
4:16
DECODER
TO
DATA
BUS
0
A
B
C
0
E
F
DMa131
6-BIT
MAGNITUDE
COMPARATOR
DMa123
TRI-STATE
QUAD
2-INPUT
MUX
-=
FIGURE 7. 16-Ch, 12-Bit Parallel·Conversion DAU for 8080
As 12-bit data is likely of greater interest in the market,
the remainder of the discussion will consider the logic
necessary to handle 12-bit data. Accordingly, Figure 7
shows a 16-channel, 12-bit parallel-conversion DAU for
the BOBO. No part number designation appears on the
ADCs because they are hypothectical units possessing
the characteristics considered desirable in this application. The converters contain the DAC switches, ladder
network, comparator, up/down counter (for tracking
conversion). control logic, and TRI-STATE buffered
outputs. They operate continuously with the output
data buffer updated at the end of each conversion. Such
a converter containing CMOS logic could settle in less
than 1-4/ls (after an initial but longer acquisition period)
without being costly to construct, and would thus
provide i 2-bit accuracy to ±'I:z LSB at data bandwidth
of 10-20 Hz. A single external buffered reference could
suffice for all converter channels. An external gated
clock could drive all converters. Address decoding is the
same as outlined for the B-bit system. The LSB address
bit is used to select byte 1 or byte 2 of the 12-bit
output data word by means of the two DMB123 quad,
TRI-STATE, 2-input multiplexers. Address bits 1-4 are
decoded into 1-of-16 select bits to enable the TRISTATE output of the selected ADC. Since the 1·of-16
output select of the DM75L 154A decoder is 0 true, it is
desirable that the ADC enable input be 0 true. Otherwise,
16 inverters would be required. The control timing may
be considered in reference to the BOBO timing requirements shown in Figure B.
The DMB131 address comparator provides an output to
gate the 4:16 decoder and to enable the DMB093 quad
TRI-STATE line driver. This occurs (+30ns) only if the
address is valid for this data card. If the address is valid, ,
the 4: 16 decoder accepts the address and the DMB093
is set to accept'the MRDC command at inputs 5 and 6
(+250 ns). The decoder output to the ADC enable lines
is available (+1 BOns). and valid data is available frofl) the
selected ADC (+330ns). As the data card must return a
data ready signal (+440ns) to prevent extending the
memory access cycle, the DMB093 transmits the MRDC
a
ADDRESS BUS
STABLE ADDRESS
MRDC
DATA BUS
XACK
+__
REQ'D
ADC ENABLE
DATA OUT
TIME
In.)
FIGURE 8. Timing and Control for 8080
14·13
o
(")
o
3
"C
C
CD
...
en
...en
s
=
E
back out to the fJ.C on the XACK ,line (+3OOns) in
advance of the time required. A 0 is placed on the XACK
line for the duration of the MRDC command. The
MRDC signal also enables the output multiplexer enable
lines (+300ns) via the DMB093. This signal also interrupts the clock drive to the ADCs to prevent a change in
data output during the remainder of the memo~y read
cycle. A desirable built-in design feature of the ADC for
this application might be a clock inhibit or data transfer
inhibit operating from the EN input: Valid data is
,present on the data bus (+460ns) at least 200ns before
it is require~. Valid data remains stable until the end of
the MRDC command when XACK and data output lin'es
, return to their normal high-impedance states.
Co
o
o
.s
G)
(,)
co
't:
Sc
-E
Data is placed on the data bus in two B-bit bytes as
controlled by the LSB address code. A 0 selects the B
LSB data, and a 1 selects the MSB data. Two consecutive
~
~
en
c
o
Po (mW)
80'80
:!!
16-
=
C"
(,)
«
C
Total address decode, control, clock, and output drive
logic circuitry is contained in six DII' circuits (only one
of 24 pins). To this must be added a code-select header,
a reference, and 16 converters. Total power required is
4.2 watts for 16 channels of 12-bit data from ±5 V analog
signals of 10Hz bandwidth (see Table 3). Low Power
TTL output drive capability would reduce power drain
by 370mW. Total cost of parts (assuming a future price
of $251 ADC) would run to about $26 per channel
(see Table 4).
Table 3. Power Required, 16·Channel, 12-8il
+i
SCO
memory addresses will then read the entire data word in
two bytes. As there are only' 12 data bits, zeros are
placed on the remaining data lines. For 2s complement
binary data' coding of ± input analog signals, the 12th
bit would be inverted and extended to the remaining
data lines so that signals would appear as valid data to
the microprocessor.
ADC
PACE
3200
1 - LH0071
Reference
45
1 - DM74LS132
4 x 2-lnput NAND Schmidt
60
1 - DM74L 154A
4:16 Decoder
1 - DMB131
6-Bit Comparator
1 - DMB093
4 x Buffer
or
1 - DMB099
6 x NAND Buffer
or
3 - DMB097
6 x Buffer
or
6800
2 - DMB123
4 x 2-lnput MUX
1 -DMB6L13
4x D-Latch
24
250
170
175
975
400
400
30
4199
4154
, 45B4
Table 4. Cost of Components, 16-Channel, 12-8it
$ (100s)
8080
16 -
or
6800
Reference
5.00
1 - DM74LS132
4x 2-lnput NAND Schmidt
2.00
1 - DM74L154A
4:16 Decoder
2.46
1 - DM8131
6-Bit Comparator
2.56
1 - DM8098
6x Inverter
1 - DMB099
6 x NAND Buffer
1.65
1.70
6 x Buffer,
2 - DMB123
4 x 2-lnput MUX
1 - DMB6L13
4x D-Latch'
PACE
400.00
1 - LH0071
or 3 - DM8097
or
ADC
5.55
2.56
2.56
1.2B
416.23
416.28
"" $26/Channel
14-14
41B.B5
l>
Z
.!..
6800 Interface
by ANDing the VMA and R/W signals together in a
TRI·STATE 2·input .AND gate. When enabled by the
comparator output, this gate returns a READY signal to
the J.!C and enables the output multiplellers. The
appropriate data byte is selected by the LSB address bit
as with the 8080 system. The necessary 10 ns data hold
time is provided by the ADC and output multiplexer
disable delays. The remainder of the DAU is identical to
that of Figure 7. Cost and power required are also
similar to those of the 8080 system interface.
For other J.!C systems, the logic will change slightly.
Figure 9 shows the logic section of the DAU of Figure 7
modified as necessary to interface· with the 6800 !lC.
The 6800 timing and control signals are shown in Figure
10. With the 6800, the address information, the valid
memory address VMA signal, and the read/write W/R
signal all come up approximately simultaneously and
remain for about one clock period of 1J.!S (min.). The
data need not appear on the data bus until lOOns
thereafter. The valid address decoding is accomplished
U1
to
...c
OJ
OJ
l>
n
.c
c
iii"
;:;:
O·
::s
en
'<
en
S'
3
TO
DATA·
BUS
FROM
ADDR
BUS
EN
SEL
DM8123
TRI·STATE
QUAD
2·INPUT
MUX
4
5
6
7
-S'::s
=.
OJ
n
CD
So
R/W VMA
O
3
......
FIGURE 9. 16·Ch. 12·Bit Parallel·Conversion DAU for 6800
'C
C
CD
en
ADDRESS BUS
-f"==;.;.1
VMA
RIW
DATA BUS
READY
ADe ENABLE
DATA OUT
200
400
600
800
1000
. TIME Ins)
FIGURE 10. Timing and Control for 6800
1200
1400
...enC»
~~
c.
E
o
(,)
.s
C»
(J
cu
't:
Sc
-
PACE 'Interface
ADC CHARACTERISTICS'
Figure 11 shows the logic section of the DAU of Figure
7' modified to interface with a PACE !lC. The PACE
timing is shown in Figure 12. Since the PACE!lC has but
a single address/data bus, address latches are required for
address decoding. The DM8131 address comparator
contains' output latches, but the DM74L154A 4:16
decoder does not, so a quad latch is inserted ahead of the
4: 16 decoder. The latches all set on the rising edge of
the NADS signal provided by PACE during the time that
address information is on the bus, and drop 'out on the
next NADS signal. Comparat«;lr output applied to gate
the 4:16 decoder provides an enable ADC signal lasting
until the falling edge of the nex't NADS pulse. The IDS
signal ANDed with the comparator output enables the
TRI-STATE output buffers and inhibits the clock. An
additional MSB inverter would be needed for ± analog
signals in order to provide the 2s complement code.
Total address decode, control, clock, and output drive
circuitry is contained in seven DIP packages, one more
than required for the 8080 system interface. Total power
and cost are comparable to those given for the 8080
system interface.
'
The ADC for use on a parallel-converSion DAU must
contah, TRI-STAIE output data latches. Otherwise it
may be conventional. The MM5357 was designed for
direct connection to a data bus, therefore it contains the
necessary output latches. At this writing there are other
ADCs with the TR I-STATE, output latches appearing on
the market. and more can be expected. The MM5357 is
nearly ideal for use in an 8-bit parallel-conversion DAU.
It would be even more suitable to this use 'if it were a
tracking converter, and the polarity of its enable input
and of its data output were of opposite polarity. The
data polarity is of lesser importance as the bus drivers
probably needed may as well be inverting as non-inverting
except for common usage. The enable polarity should
match the decoder output to obviate the need for 16
inverters (3 logic packages. though of little cost). See the
later discussion of ADC hardware for additional thoughts
on this subject.
This parallel-conve~sion data system has data bandwidth
limited to about 10Hz for 8-bit SAR converters, but
may be increased to 150-300 Hz with 8-bit tracking
TO
DATAl
ADDRESS
0)
,...
it)
I
Z
(')
Q)
4·BIT ADDRESS
CC
....
Q)
(')
Q
Q TRIG
ONE-SHOT A.
1200n,) TRIG
% OM74LS221 B
START·UP
cQ)
10
12
50
...
(/)
S::s
c.
E
o
()
.9
Q)
(.)
CO
't:
Sc
-E
oS(/)
~
en
.
c
o
'iii
'S
C"
(.)
c(
trigger input to the first one-shot_ If a CC signal occurs
during the time the 0 is present on the B input, the oneshot will not be ,ttiggered until. the B input returns to al.
Data, on, each channel is sampled and ,held in the Sl!tH
module while the ADC converts the analog data' to
digital. At the completion of conversion, the digital
outpu,t of the ADC is written into the RAMs before the
multiplexer selects the next channel. The timing and
sequencing of channels _IS acco~plis!1ed 'With a 4:bit
binarY (+ 16) couriter and thre~ one-shot: pulse generators: 'Where one-shots' are undesirable, an alternate
approaph using shift regIster ti~!ng could provide the
same function. A valid address output from the address
comparator, switches th'e RAM address input from the
""16 counter to the address bus input, thereby addressing
the RAM 'to the desired channel for data readout. If the
data "conversion 'sequence is in ihe memory write
condition, the gate applied to 'WE prevents switching the
MUX to the address bus
returning an XACK signal
until the memory has been loaded. Thereupon, the
sequence is interrupted as outlined above. The interruption of the s'equence lasts for about 1300 ns (8080
system) while the address is 'valid_
'
or.
The sequential data conversion cycle' is shown in the
timing signals of Figure 14. The conversion-complete CC
output of' the ADC triggers a 'one-shot to generate a
200ns memory write pulse. The trailing edge of this,
pulse advances the address .,. 16 cOl!nter to the next
channel and triggers a second one-shot to produce a lOps
sample period_ At the completion of the sample period,
the S&H goes into hoid mode 'and a third one-shot
generates a 3ps start conversion SC pulse. When the
DAU is in the command read mode, a 0 appears at B, '
An ,alternate sequencing circuit without one-shot circuits
is shown in Figure 15 with timing relationships in
"Figure 16. It makes use of a shift register and exclusiveOR gates to generate the gates' needed to write into
memory, sample and hold, and start conversion. The
AD'C clock is genenitect at twice the desired Cl'ock
frequency and divided by 2 in a D flip-flop. In this
manner, the 'minimum gate width is 1/4.of the ADC
clock period (620ns in this example). The CC signal is
clocked into a 0 flip-flop .with a delay of 620ns. The
delayed output clears the shift register (SR) and is
clocked in'to the SR after an' additional 620ns delay_
An exclusive-OR of the SR' input and Q1 output
generates a 620ns gate to write data into the HAMs_
The trailing edge of this WE gate clocks the'" 16 counter
to advance the MUX and RAM address to the next
channel. Exciusive-ORing of SR 01 and 07 produces an
8.75ps samplEi gate. (If the acquisition and settling time
of the S&H is greater than 8.75ps, additional circuit
complexity is required.) 'ExclLJsive-ORing of 07 and 08
produces a synchronized 1.251.ls gate to start the ADC.
This circuit may not be the most versatile or elegant for
the purpose. For those applications with longer S&H
acquisition times or other requirements, some alternate
~ircuit may be designed if that of Figure' 15 is
unacceptable .
...------,
co
10
c
C»
it)
,...
I
Z
ELK ---+lr;;-----:----;~
a: OF ADDR ..... " '........w
. COMPARATOR
c(
FIGURE 1,5_ Sequencing Logic with SR
elK
ClK/2 TO ADC
,Ct
SA INPUT
-.J
01
LJ
I~~========~---
---u
07
RAM & MUX ADDR
Q1
®
Q7
START CONVERSION
~~;;;;;;-N:E;W;A~D~D;RE~S~S;;;;;;~=============
----.J
I
==~~==--~~~,~-====
SAMPLE
HOLD
FIGURE 16. Titning for S-R Sequencing
14-18
CONVERTER CHARACTERISTICS
The /l-computer interfaces shown in Figures 17 and 18
are similar to that of Figure 5_ The PACE interface is seen
to be slightly less complex than that of Figure 17 for
8-bit data-bus machines. A single DAU card with plug·in
or strap options could be built to interface any of the
three /lCS considered. Such a universal circuit is shown
in Figure 19. This circuit also includes an option to
provide binary output for unipolar analog signals or
complementary binary output for ± signals. In the case
of binary output, the 13-16th data bits are set to O. In
the case of complementary binary, the sign bit is'
extended to the 13·16thdata bits for valid recognition by
the /lC.
Each approach to the DAU requires different characteristics of the ADC. Table 6 summarizes the requirements
for each of the three DAU types. The sequential or
addressed DAU types require similar ADCs. If the
conventional addressed DAU must utilize bus drivers,
the 'desired ADC characteristics are identical to those for
the sequential DAU with memory. Only the parallelconversion DAU is seen to require buffered TR I-STATE
output latches.
By far the most important characteristic of an ADC for
use in a parallel-conversion DAU is that it have buffered
TR I-STATE output latches. It is desirable that it also
have the other characteristics checked in Table 6. Items
1 and 2 are by far the most important of the desired
characteristics. The need for item 1 has been discussed. '
TTL compatible control and data signals are desirable so
that TTL-MaS and MOS·TTL interface buffers are not.
required between the ADC and, the rest of the system.
Dual output strobing makes it possible to wire-OR
interface directly to an 8-bit data bus or to use only an
8-line buffer without the need for the output multi-
The total dissipation is 3.5 watts and c<;lst is $11 per
channel as shown in Table 5. Botti are only slightly
greater than those for the conventional DAU.
The ADC desired for this application is similar to the
conventional ADC except that the ADC data output
should be complementary to compensate for the data
inversion within the RAMs. The AD1210 or AD1200 are
thus ideal choices for an ADC in the multiplexed DAU
with memory.
"
c
Q)
Q)
l>
(')
JJ
C
-,
UJ
~
0'
::::J
en
'<
UJ
S'
3
-
::J
CD
4·,
~
Q)
(')
CD
DATA
0-3
3
-
4·,
'C
I
C
I
01234ABCDEF
VMA
~
ADDRESS
0'
(")
o
R/W
...
CD
UJ
FIGURE 17. Address Comparator and Control for 8080 (68001
DATA
0-3
DATA
4-,
DATA
B,B
1-__......>1
DM8097
5
BuHFEF~R
DATA
C·F
L.------+jrn
IDS
'-----~v~----~
ADDRESS
FIGURE 18. Address Comparator & Control for PACE
14-19
EXTEND
...en
Q)
::s
Q,
Q
E
t},NAlOG
16-CH
o
L.,rM'T'"'-....
u
o
DATA
E
~
en
~
C/)
C 4
o 5
E 6
F 7
I:
o
~~~~~~:g~J
EXTEND (PACE)
!e
.-en::s
C'
CJ
ZI
....a.
The National MM5357 is the choice for an 8-bit ADC
having buffered TR I-STATE output latches and TTL
compatibility when converting ±5 or 0-5V analog inputs,
If converting 0·10V inputs, it becomes 10V CMOS:
compatible. Several monolithic ADCs of 8 to 12 bits
have been announced. These monolithic converters and
future versions of them promise to bring converter
prices down to a level which will make parallel·conversion
economically feasible. Several hybrid converters have
also been announced with attractive prices; however, it is
the monolithics which promise the lowest ultimate cost.
Features of several of these 'new products are compared
in Table 7. Although only the MM5357 and the AD7550
are suitable in present form, their prices and characteristics show that the desired attributes are and will be
possible at the needed prices,
plexers shown in Figure 5 et. al., although a separate
buffer is required in most systems. Tracking operation
provides the higher speed useful in a conversion circuit
without an S&H. Inhibiting data transfer to output data
latches when the output is enabled prevents changing the
output code while data is being read f~om the data bus.
This function can be accomplished with an external gate,
but could be convenient if handled within the ADC
logic. Straight binary (not complemented) output is
desired for all pC interfaces (except the 8080 when
operating with Intel system bus drivers and receivers).
As it may be necessary to add TR I-STATE line drivers
to drive the data bus, data inversion can be' handled by
inverting buffers when required. The availability of both
Q and Q outputs on the MSBsimplifies data readout as
binary or 2s complement without adding an external
inverter. Table 6 has been arranged in the approximate
order of preference for parallel-conversion DAU use; the
preference will be different for multiplexed data.
01
to
c
Q)
Q)
l>
n
.c
c
en'
;::;:
S'
::s
The future ADC most suited for use in a parallelconversion DAU might appear as in Fig'ure 20. This
en
--
'<
en
Table 6. Desired AID Converter Characteristics
( I)
Parallel
Conversion
Sequential
w/Memory
wlo Memory
x
.x
x
x
x
UP/ON
SAR
SAR
x
x
Data"
x
x
x
Buffered TR I-STATE Output Data Latches
TIL-Compatible Control & Data Signals
Dual Output-Enable (Bits 0-7 & Bi~s 8-11)
Counter Logic
Internal Comparator
Botti Q & QOutputs on MSB
Binary Output Polarity
!.
x
x
Data
Data"
x
x
x
Busy Output (TRI·STATE w/ Enable)
Internal Clock
Continuous Recycle when CC" SC
Inhibit Data XFR to Latches when Enabled
Addressed
::s
S'
~
Q)
n
(I)
S'
oo
3
-...
x
x
"C
C
* Unimportant if Buss drivers used.
( I)
en
Table 7. Low-Cost Monolithic and Hybrid ADes
National
MM5357
3
Analog Devices
AD7570L
Teledyne
8702
National
AD1210 (Hybrid)
Analog Devices
AD7550
Number of Bits
8
10
12
12
13
Cost (in 100s),
$7.95
$69.00 (1-49)
$29.50
$24.95
$25.00
Conversion Method
Potentiometric
R-2R
Differential Charge R-2R
Balancing
Integrating
Logic Type
PMOSSAR
CMOSSAR
CMOS Integratin!!
CMOSSAR
CMOS Quad Slope
Conversion Time
251ls
20ps + Compo
Settling
20ms
130 lls
40ms
Logic Interface at 5 V
Analog Sig. 0·10V
TTL
CMOS
TIL
TIL/CMOS
TIL
TIL
TTL
CMOS
TIL
TTL/CMOS
External Circuits Required Ref + Clock
Ref + Comparator
Ref
Ref + Clock
Ref
Output Buffered Latch?
Yes'
No
Yes
No
Yes
TRI-STATE Output?
Yes
Yes
No
No
Yes
Separate Output Enables?
NA
Yes
Not Strobed
No
Yes
Output Code
Inverted
Normal
Normal
Inverted
2s Complement
Power Dissipation
170mW Dynamic 10mW Standby
+ Dynamic
+ Comparator
20mW Dynamic
140mW Dynamic
10mW Dynamic
14-21
...
s
f/)
~
Q.
E
o
BINARY DATA
i'i
UP/ON BINARY
COUNTER
11
10
9
8
7
6
5
4
3
u
.s
CD
> ....---1Uii
ClK
(,)
2
1
CO
--E
't:
CD
c::
TRI-STATE
OUTPUT
DATA
i-
(0'= 1) 0
lATCH
-
o
al--H-"
CD
f /)
~
C/)
EN
ClK
0·7
c::
EN
8·11
o
.=::
.~
~
FIGURE 20. Tracking ADC for Parallel-Conversion OAU
C'
(,)
«
CO
CO
C
Q)
u')
"';'
Z
«
A two-chip approach would likely be the choice today.
We will certainly see some .of these desired design
features appearing on ADCs in the near future.
design meets all the goals of Table 6. It could run at a
clock rate of 0.25-1 MHz (1-4lls conversion time)
because it is a tracking converter, it contains TRI·
STATE buffered output data latches, the separate high
and low bit·enable lines allow two·byte operation of an
B·bit data bus, the output latches will 'not change state
when the output is enabled, and the CC and SC
terminals may be strapped for continuous conversion
without missing a clock period. An B- or 1O·bit converter
and possibly a 12-bit converter of this type could be
built on' a single chip without much difficulty. If not,
a hybrid or two·chip design is practical. Where speed is
not of importance, monolithic 10· or 12-bit converters
can be built with integr~ting or voltage-to· frequency
conversion techniques. The· integrating technique possibly allows the greatest accuracy with the least circuitry,
and is a prime contender for the application. As the
integrating ADC utilizes both linear and digital circuits,
it is normally of multi-chip design. However, as technology advances, it will become increasingly practical to
produce the low-drift, low-offset amplifiers, integrators,
and current sources required of a 12-bit ADC on a single
reasonably small chip along with the necessary logic.
As far as ADCs and DACs are concerned, the entire
makeup of their internal logic sections is differeni: from
that of conventional converters of today (except for the
MM5357 and AD7550). Tables 6 and 8 outline the
desired characteristics of AD~s and DACs for parallel-,
conversion and multiplexed systems. Figures 20 and 21'
indicate the logic .required. The ADC of Figure 20 is
suitable for relatively high speed data acquisition without
S&H circuits, while that of Figure 21 is suitable for
slowly varying data only.
,
DATA DISTRIBUTION SYSTEMS
Until now, the discussion has centered entirely around
the data acquisition end of the system. At first thought,
the data distribution may seem almost trivial. However,
there is still the address recognition and decoding pills'
the control functions. The conventional data distribution unit (DDU) has used a single DAC, a multi-channel
analog demultiplexer, low·pass filters and possibly S&H
Table 8. Desired 0/A Converter Characteristics
Hi·Z Digital Input Circuits
Strobed Data Input Latches
Dual Input Data Strobes ,(Bits 0-7 & Bits B-ll)
Optional Internal Inversion of MSB
Internal Output Amp & FB Resistors
Internal Reference
Parallel
Conversion
Multiplexed
System
x
x
x
x
x
x
x
x
x
7·
x
14·22
»
z
.....
I
<.n
CD
11
10
TRI-STATE
OUTPUT
DATA
LATCHES
9
8
7
6
5
Q)
TRI-STATE
OUTPUT
DATA
4'
STROBE
EN
0-7
EN
8-11
cQ)
11
VIN
3
2
1
0
»
n
.c
c_.
t/)
;:::;:
O·
::::I
en
EN
0-7
EN
8-11
-
'<
t/)
CD
3
FIGURE 21_ V-F ADC for Parallel-Conversion DAU
circuits on each channel reconverted to analog form_
Such a system could benefit from a DAC with input data
latches and separate (double-byte) input gating' or
strobing controls while a parallel-conversion DDU has
even more need of these input characteristics_
The parallel-conversion DDU shown in Figure 22 would,
if constructed with available DACs, require 12-bit input
data latches ahead of each DAC_ The characteristics
desired of a DAC for this use are listed in Table 8_ High
impedance digital inputs prevent loading the data bus
while a strobed input data latch allows entering data
only in the addressed DAC and holding it until updated
(thus performing the function of DAC and S&H)_
Separate input data strobes for low and high bits are
used for the same reason as with the ADC, for alternate
enabling on successive input data bytes_ Figure 23 outlines the desired DAC for use in a parallel-conversion
DDU_
The DDU address decoding and complexity is similar to
that of the DAU_ Input data strobing separated as 8 LSB
and the remaining MSB is an adva,ntage when used on
8-bit data bus systems_ The cost per channel is essentially
that of the DAC used_ Likewise, for power dissipation_
Practicality will be entirely dependent on ultimate cost
of the converters_ Advantages over a demultiplexed
system are that only minimal output filters are required
and that an output ampl ifier per channel is not required
(already exists in each DAC)_
type of DAU is extremely attractive at this time because
the DAU cost per channel is essentiaily that of an ADC
which is as low as $8 in lots of 100_
It would seem that the multiplexed DAU with memory
exhibits all of the advantages of the conventional
random-addressed DAU plus all those of the parallel data
conversion DAU except that the data in any specific
channel may be older_ Offsetting this single comparative
disadvantage are significantly lower cost per channel,
lower power requirements, and no requirement for
special ADCs with buffered output latches_ The multiplexed approach with memory is only slightly more
complex or costly than a standard DAU, yet it brings
'the great advantage of high-speed immediate data access
with significant cost savings over the parallel conversion
technique_
Although the character of an ADC or DAC used in a
parallel-conversion data system differs markedly from
those used in the usual multiplexed data system, the
processor interface requirements are similar qr identical.
The sense of Jic bus control signals is of relativE\ly minor
importance so long as they are standardized among the
several f-LC units available_ Positive-true data and address
signals are possibly a slight advantage over, zero-true'
signals when TR I-STATE circuits are used_ For the
multiplexed system described, data inversion through
the RAM would suggest the advantage of complementary
binary output data' from an ADC_
Conventional ADCs and DACs available today (except
the MM5357 and AD7550) do not have the characteristics needed for parallel-conversion systems_ However,
this picture is changing as more units are designed for
direct data bus interface_ Fortunately, however, the
multiplexed DAU with memory does not require the bus
oriented type of ADC_ The're is at least one available
DAC which includes the dual-strobed input data latches
suggested for direct data bus interface; I would expect to
see others appearing in future designs, both monolithic
and hybrid_
CONCLUSION
Each type of DAU described exhibits unique advantages
as indicated in the comparisons of Table 9_
Further reduction in the costs of monolithic converters
will make the parallel-conversion type of DAU attractive
where low-speed data is handled_ For 8-bit data, this
14-23
::::I
CD
~
Q)
n
CD
0'
o
o
3
"C
..
C
CD
t/)
In
~
. . . . . . . . .D.A.C.B.IT.S.O•.~~P.A.RA.L.L.E.L.W.IT.H.B.IT.S.8.·'.'. . . . . . . . . . . . .
S:::s
~:+l
BUS
a.
E
o
o
S
CI)
(,)
co
't:
Sc
-E
fi'E"A'ij'y
---iSOBOr-
WR
~68001--
R/W VMA
NC
MWfC
NC
TO ADDRESS BUS
S
In
f'lIGURE 22. Parallal-Convelsion OOU for 6800·or, 8080 ,
-:-.,
en
",,,,,,,,,,,,-- FB
c
o
;;
~-vVV--OS/FB
, {7
:il
:::s
6
.
5
BINARY'
4
INPUT
3
,
'2
C"
,
CJ
«
SCO
1
o
FIGURE 23. OAe for P.~all.I·Convarsion OAU
C
en
It)
"7
Z
DIFFUSION
p-
BURIED LAVER
FIGURE 2. Functional Block Diagram
FIGURE 1. SUbsurfac'e Zener Construction
14·25
"C
"C
3
"C
CD
...
c
CD
CC
CD
CD
...
...C::::;,:
-
-..
.-
Q
..
,g'
..
CD
CD
Q
CD
Q.
E
Q.
Q.
,....
(/)
CO
.c
CD
CJ
..
C
CD
circuits ,is the isolation diode inherent in any junction·
isolated integrated circuit. The zener may be used with
or without ,the temperature stabilizer powered. The only
operating restriction is that the isol~tion diode must
nElVer become forward biased and the zener must not be
biased above the 40V breakdown of the isolation diode.
07 is provided as base drive to a Darlington composed of
, Oland 02: The Oarli ngton is connected across the
supply and initially draws 140 mA (set by current limit
transistor 03). As the chi p heats, the turn on voltage for
04 decreases and 04 starts to conduct. At about 90°C
th~ current through 04 appreciably increases and less
drive is applied to 01 and 02. Power dissipation decreases
to whatever is necessary to hold the chip at the stabillza·
tion temperature. In this manner, the chip temperature
,is regulated to better than 2°C for'a 100°C temperature
range.
The actual circuit is shown in Figure 3. The temperature
stabilizer is composed of 01 through 09. FEt 09
provides' current to zener 02 and 08. Current through
08 turns a loop consisting of 01, 05, 06, 07, Rl and
R2. About 5V is applied to the top of Rl from the base
of 07. This causes 400llA to flow through the divider
R1, R2. Transistor 07 has a controlled gain of 0.3 giving
07 a total emitter current of about 5001lA. This flows
through 'the emitter of 06 and drives another controlled
gain PNP transistor 05. The gain of 05 is'about 0.4 so
01 is driven' with· about 2001lA. Once current flows
througH 05, 08 is reverse biased and the loop is' self·
s'ustaining. This circuitry ensures start·up.
The zener section is relatively straight·forward. A buried
zener 03 breaks down biasing the base of transistor 013:-'
Transistor 013 drives two buffers 012 and 011. External
current changes through the circuit are fully absorbed
by the buffer transistors rather than 03. Current through
03 is held constant at 250llA by a 2k resistor across the
emitter base of 013 while the emitter-base voltage of
013 nominally temperature compensates the reference
voltage.
The resistor divider applies 400 mV to the base of 04
while 07 supplies 120llA to its collector. At temperatures
below the stabilizati.on point, 400 mV is insufficient to
cause 04 to con'duct. Thus, all the collector current from
The other 'components, 014, 015 and 016 set the
operating current of 013. Frequency compensation is
accomplished with two junction capacitors .
-!CD
a:
CD
C)
S
>
'0
~
,....
CO
'7
Z
«
4,2
1k
L-________~~__~--~--__~----~----~--~4
v-
OJ
6.3V ,
2.6k
L-______~--~--------~----------__~~_;2
FIGURE 3. Schematic Diagram of LM199 Precision Reference
14-26
-
PERFORMANCE
A polysulfone thermal shield, shown in Figure 4, is
supplied with the LM199 to minimize power dissipation
and improve temperature regulation. Using a thermal
shield as well as the small, high thermal resistance TO-46
package allows operation at low power levels without
the problems of special IC packages with built·in thermal
isolation. Since the LM199 is made on a standard IC
assembly line with standard assembly techniques, cost is
significantly lower than if special techniques were used.
For temperature stabilization only 300 mW are required
at 25°C and 660 mW at "-55°C.
l>
ZI
zoo
-"
~
150
ifi
l~O
~
en
-"
1\
~
"-
-
~ 90'C!_
STABILiZED (TI
(1
TI '" 25~C
<
o::;
50
100
10
10k
lk
lOOk
.~
FREQUENCY (Hz)
FIGURE 5. Wide band Noise of the LM199 Reference
en
..:xJ
0.01 Hz:;: f:;:; 1 Hz
STABILIZED
IT, • 90'C)
en
en
en
:::l
o
en
:::l"
Q)
t/)
-"
TIME (MINUTES)
FIGURE 4. Polysulfone Thermal Shield
Temperature stabilizing the device at 90°C virtually
eliminates temperature drift at ambient temperatures
less than 90°C. The reference is nominally temperature
compensated and the thermal regulator further decreases
the temperature drift. Drift is typically only 0.3 ppm/C.
Stabilizing the temperature at 90°C rather than 125°C
significantly reduces power dissipation but still provides
very low drift over a major portion of the operating
temperature range. Above 90°C ambient, the temperature
'
coefficient is only 15 ppm/C.
,A low drift reference would be virtually useless without
equivalent performance in long term stability and low
noise. The subsurface breakdown technology yields both
of these. Wideband and low frequency noise are both
exceptionally low. Wideband noise ,is shown in Figure 5
and low frequency noise' is shown over a 10 minute
period in the photograph of Figure 6. Peak to peak
noise over a 0.01 Hz to 1 Hz bandwidth is only about
0.7/lV.
Long term stability is perhaps one of the most difficult
. measurements to make. However, conditions for longterm stability measurements on the LM 199 are considerably more realistic than for commercially available
certified zeners. Standard zeners are measured in ±0.05°C
temperature controlled both at an operating current of
7.5 mA ±O.05JJ.A. Further, the standard devices must
have stress-free contacts on the leads and the test must
not be interrupted during the measurement interval. In
contrast, the LM199 is measured in still air of 25°C to
2SoC at a r~verse current of- 1 mA ±0.5%. This is more
typical of actual operating conditions in instruments.
When a group of 10 devices were monitored for longterm stability, the variai:ions all correlated, which- indicates changes in the measurement system (limitation of
20 ppm) rather than the LM199_
FIGURE 6. Low'Frequency Noise Voltage
"C
"C
Because the planar structure does not exhibit hysteresis
with temperature cycling, long-term stability is not impaired if the device is switched on and off.'
"C
The temperature stabilizer heats the small thermal mass
of the LM199 to 90°C'very quickly. Warm-up time at
25°C arid -55°C is shown in Figure 7_ This fast warm-up
is significantly less thim the several minutes needed by
ordinary diodes'to reach equilibrium_ Typical specifications are shown in Table·1.
3
..
en
C
..
..
en
(C
en
en
C
TA .. 125 C
;;
oS
-1
....
.... -z
~
~
i , '~A'-5\
I ,
/.
--
~
c
Q
-,
I
I
VH = 15V
-4
12
·16
20
HEATER ON TIME - (SEC)
FIGURE 7. Fast Warmup Time of the LM199
Table I. Typical Specifications for the LM199
6.95V
Reverse Breakdown Voltage
0_5 mA to 10 mA
Operating Current
TemPerature Coef.ficient
0.3 ppmtC
Dynamic Impedance
0.5!2
RMS Noise (10 Hz to 10 kHz)
7/lV
Long-Term Stability
~20 ppm
Temperature Stabilizer Operating Voltage
9V to 40V
Temperature Stabilizer Power Dissipation
(25°C)
300mW
3 Seconds
Warm-up Time
-=
'':;:
c
CD
~
m
..
CD
C
CD
c.
E
c.
c.
APPLICATIONS
I
The only restrictioh on biasing the zener is the bias
applied to the isolation diode.' Firstly, the isolation diode
must not be forward biased. This restricts the voltage at
either terminal of the zener to a voltage equal to or
greater than the V-.
A dc return is needed bet~een the zener and heater to
insure the voltage limitation on the isolation diodes are
not exceeded.' figure 8 shows the basic biasing of the
LM199.
The active circuitry in the reference section of the LM199
reduces the dynamic impedance of the zener to about
0.5U. This is especially useful in biasing the reference.
For example, a standard reference diode such as a 1 N829
operates at 7.5 mA and has a dynamic impedance of
15U. A 1% change in current (75MA) changes the
reference voltage by 1.1 mV. Operating the LM 199 at
1 mA with the same 1% change in operating current
(10MA) results in a reference change of only ,5MV. Figure
9 shows reverse voltage change with current.
,..
CO
";"
Z
I
The LM199 is easier to use'than standard zeners, but the
temperature stability is so good-even better than precision resistors-that care must be taken to prevent
external circuitry from limiting performance. Basic operation only requires energizing the temperature stabilizer
from a 9V to 40V power'source and biasing the reference
with between 0.5 mA to 10 'mA of current. The low
dynamic impedance minimizes the current regulation
required compared to ordinary zeners.
Biasing current for the reference can be anywhere from
0.5 mA to 10 mA with little change in performance. This
wide current range allows direct repla'cement of most
zener types with no other circuit changes besides the
temperature stabilizer connection. Since the dynamic
impedance is constant with current changes regulation
+t5V--....- - - - - ,
STABILIzeD
(Tj-90;~
4'25'&-
;I'
".
./
"
,
I
I
I
to
REVERSE CURRENT (rnA)
FIGURE 9_ The LM199 Shows Excellent Regulation
Asainst Current Changes
is better than discrete zeners. For optimu'm regulation,
lower operating current~ are preferred since the ratio of
source resistance to zener impedance is higher, and the
attenuation of input changes is greater. Further, at low
currents, the voltage drop in the wiring is minimized.
Mounting is an important consideration for optimum
performance. Although the thermal shield minimizes
the heat low, the LM199 should not be exposed to a
direct air flow such as from a cooling fan. This can cause
as much as a100% increase in power disSipation degrading
the thermal regulation and increasing the drift. Normal
conviction currents do not degrade, performance.
Printed circuit board layout is also important_ Firstly,
four wire sensing should be used to eliminate ohmic drops
in pc traces. Although the voltage drops are small the
temperature coefficient of the voltage developed along
a copper trace can add significantly to the drift. For
example. a trace with 1U resistance and 2 mA current
flow will develop 2, mV drop. The TC of copper is
o.o04%fC so the 2 mV drop will change at 8MVfc, this
is an additional 1 ppm drift error. Of course, the effects
of voltage drops in the printed circuit traces are eliminated with 4-wire operation. The heater current also
should not be allowed to flow through the voltage
reference traces. Over a -55°C to +125°C temperature
+.5V-------,
c(
9V TO 40V
1,5h
TEMPERATURE
STABILIZER
6,95V
-9VTO
-33V
-15V
/
~
.":"
+.5V--....- - - -....- - - - - - - - ,
9k
1.5h
TEMPERATURE
tOv
STABILIZER
FIGURE Ii. Basic Biasing of the LM199
14-28
--1""""----,
range the heater current will change from about 1 rnA
to over 40 rnA. These magnitudes of current flowing
reference leads or reference ground can cause huge errors
compared to the drift of the LM199.
from a single 15V supply. About 1% regulation on the
input supply is adequate 'contributing less than 10llV of
erro~ to the output. Feedback resistors around the LM308
scale the output to 10V.
Thermocouple effects can also cause errors. The kovar
leads from the LM 199 package form a thermocouple
with copper printed circuit board traces. Since the
package of the 199 is heated, there is a heat flow along
the leads of the LM199 package. If the leads terminate
into unequal sizes of copper on the p.c. board greater
heat will be absorbed by the larger copper trace and a
temperature difference will develop. A temperature
difference of 1°C between the two leads of the reference
will generate 'about 301lV. Therefore, the copper traces
to the zener should be equal in, size. This will generally
keep the errors due to thermocouple effects under about
Although the absolute values of the resistors are not
extremely important, tracking of temperature coefficients
is vital. The 1 ppm!"C drift of the LM199 is easily
exceeded by the temperature coefficient of most resistors.
Tracking to better than 1 ppm is also not easy to obtain.
Wirewound types made of Evenohm or Mangamin are
good and also have low thermoelectric effects. Film
types such as Vishay resistors are also, good. Most
potentiometers do not track fixed resistors so it isa good
idea' to minimize the adjustment range and therefonl
minimize their effects on the ou'tput TC. Overall temp.
erature coefficient of the circuit shown in Figure 10 is
worst case 3 ppm!" C. About 1 ppm is due to the
reference, 1 ppm due to the resistors and 1 ppm due
to the op amp.
-
151lV.
The LM 199 should be mounted flush on the p.c. board
with a minimum of space between tile thermal shield
and the boards. This minimizes air flow across the kovar
leads on the board surface which also can cause thermo·
couple voltages. Air currents across the leads usually
appear as ultra·low frequency noise of about 10llV to
20llV amplitude.
It is usually necessary to scale and buffer the output of
any reference to some calibrated voltage. Figure 10
shows a simple buffered reference with a 10V output.
The reference is applied to the non·inverting input of the
LM108A. An RC rolloff can be inserted'in series with
the input to the LM 108A to roll·off the high frequency
noise. The zener heater and op amp are all. powered
Figure 11 shows a standard cell replacement with a
1,01 V -output. A LM321 and LM308 are used to minimize op amp drift to less than 1IlVtC. Note the
adjustment connection which minimizes the TC effects
of the pot. Set-up for this circuit requires nulling the
offset of the op amp first and then adjusting for proper
output voltage.
The drift of the LM321 is very predictable and can be
used to eliminate overall drift of the system. The drift
changes at 3.6IlV!"C per millivolt of offset so 1 mV to
2 mV of offset can be introduced to minimize the
overall TC.
+15V--....---_....--------,
Q)
CC
CD
-...
lJ
CD
CD
CD
::l
n
CD
::l",
Q)
en
~
'C
'C
3
'C
CD
...
c
9k
l,5k
0'
<
o
;::;
CD
...
CC
TEMPERATURE
CD
CD
IOV
STABILIZER
...C
-
6.95V
=i;
FIGURE 10_ Buffered 10V Reference
15V-1~---_.--------------_.------------1.5V
12k
lOOk
0.1%
ADJ
6.BV
OUTPUT
2M
LM199
20k
2k
30k
~DOPF
2k
0.1%
----..-.-15V
1..--....
FIGURE 11_ Standard Cell Replacement
100pF
==
''::
Q
cb
Q)
...
C)
Q)
Q
...
Q)
Q.
E
Q.
Q.
....
For circuits with a wide input voltage range, the reference
can be powered from the output of the buffer as is shown
in Figure 12. The op amp supplies regulated voltage to
the resistor biasing the reference minimizing changes due
to input variation. There is some change due to variation
of the temperature stabilizer voltage so extremely 'wide
range operation' i's not recommended for highest pre·
cision. An additional resistor (shown 80 kill is added to
the unreguiated' input to insure the circuit starts up
properly at the application of power.
CO
Q)
(.)
C
...
Op amp choice is important for this"circuit. A low drift
device such as the LM108A or a LM108-LM121 combination wi II provide excellent performance. The pot should
be a precision wire wound 10 turn type. 'It should be,
noted that the output of this circuit is not linear.
CONCLUSIONS
A new monolithic reference which exceeds the performance .of conventional zeners has been developed. In fact,
the LM199 performance is limited more by external
components than by reference drift itself. Further, many
of the problems associated with conventional zeners
such as hysteresis, stress sensitivity and temperature
gradient sensitivity have also been eliminated. Finally,
long-term stability and noise are eq~al of the drift
performance of the new device.
'
A precisiOn power supply is shown in Figure 't3. The
output of the op amp is buffered by an Ie power
transistor the LM395. The LM395 operates' as an ,NPN
power devi~e but requires only 5pA base current. Full
overload protection inherent in the LM395 includes
current limit, safe~area protection, imd thermal'limit.
tn
.c
as was shown earlier. A ten·turn pot will adjust the
output from +Vz to ...,.Vz· continuously. For negative
output the op amp operates as an inverter while for
positive outputs it operates as a non-inverting connection.
A reference which can suppiy either a positive or a
negative continuously variable output is shown in Figure
,14. The reference is biased from the ±15V input supplies
10VT025V"""''"""---....- - - - - - - ' ' - - - - - . . ,
30k
Q)
.!
Q)
a:
OUTPUT
Q)
...
'0
C)
CO
>
FIGURE 12. Wide Range Input Voltage Reference
25VTO 4 0 V - -.....- - - _ , . . . . . - - - - - - - - - - - -.....- - - - - - . . . ,
~
6k
....
LMI95K
TEMPERATURE
SJABILIZER
....
Z
«
U)
6.95V
I
lM199
1k
·,v
FIGURE 13. Precision Power Supply
'Ok
..15V--.....-~---.
Uk
TEMPERATURE
STABILIZER
OUTPUT ±6.9V
"k~---..!f
B.9SV
-I5V
LMl!!19
30pf
-15V
FIGURE 14. Bipolar Output Reference
14-30
l>
Ie Zener
ZI
National Semiconductor
Application Note 173
Robert C. Dobkin .
November 1976
Eases Reference Design
....,
~
eN
-
n
N
C'D
:s
...C'D
m
Q)
f/)
C'D
f/)
::XJ
C'D
description
A new IC Zener with low dynamic impedance and wide
operating current range significantly simplifies reference
or regulator circuit design. The low dynamic impedance
provides better regulation against operating current_
changes, easing the requirements on the biasing supply.
Further, the temperature coefficient is independent of
operating current, so that the LM 129 can be used at any
convenient current level. Other characteristics such as
temperature coefficient, noise and long term stability
are equal to or better than good quality discrete Zeners.
The LM129 uses a new subsurface breakdown IC Zener
combined with a buffer circuit to lower dynamic
impedance. The new subsurface Zener has low noise and
excellent long term stability since the breakdown is in
the bulk of the silicon. Circuitry around the Zener
supplies internal biasing currents and buffers external
current changes from the Zener. The overall breakdown
is about 6.9 V with devices selected for temperature
coefficients.
The Zener is relatively straightforward. A buried Zener
01 breaks down biasing the base of transistor 01.
Transistor 01 drives two buffers 02 and 03. External
current changes through the circuit are fully absorbed by
the buffer transistors rather than by 01. Current through
01 is held constant at 250 pA by a 2k resistor across the
emitter base of 01 while the emitter·base voltage of 01
nominally temperature compensates the reference
voltage.
Dl
6.3 v
The other components, 04, 05 and 06, set the operating
current of 01. Frequency compensation is accomplished
with two junction capacitors.
All that is needed for biasing in most applications is a
resistor as shown in figure 2. Biasing current can be
anywhere from 0.6 mA to 15 mA with little change in
performance. Optimally, however, the biasing current
should be as low as possible for the best regulation. The
dynamic impedance of the LM 129 is about 1 nand
is independent of current. Therefore, the regulation of
the LM 129 against voltage changes is 1IRs.
Lower currents or higher Rs give better regulation. For
example, with a 15 V supply and 1 mA operating
current, the reference change for a 10% change in the
15V supply is 180/LV. If the LM129 is run at 5mA,
the change is 900/LV or 5 times worse. 8y comparison,
a standard IN821 Zener will change about 17 mV. All
discrete Zeners have about the same regulation since
their dynamic impedance is inversely proportional to
operating current.
If the Zener does not have to be grounded, a bridge
compensating circuit can be used to get virtually perfect
regulation, as shown in figure 3. A small compensating
voltage is generated across R1, which matches the
dynamic impedance of the LM129. Since the dynamic
impedance of the LM129 is linear with current, this
circuit will work even with large changes in the unregulated input voltage.
V+
k-
30pF
10k
-=-
2k
Z.6k
VOUT
lM129
FIGURE 2. Basic Biasing
FIGURE 1. Ie Reference Zener
14-31
CD'
CD
:s
(')
C'D
C
C'D
f/)
cO'
:s
c
.~
U)
Q)
c
Q)
(J
c
!
.e
Q)
a:
An AC square wave or bipolarity output reference can
easily be made with an op·amp and FET switch as shown
in figure 5. When 01 is "ON," the LM108 functions as a
normal inverting op·amp with a gain of -1 and an output
of ·-6.9 V. With 01 "OFF" the op·amp acts as a
giving 6.9 V at the output. Some non·symmetry will
occur from loading change on the LM 129 in the different
states and mismatch of R 1 and R2. Trimming either R 1
or R 2 can make the output exactly symmetrical around
ground.
Other output voltages are easily obtained with the
simple op,amp circuit shown in figure 4. A simple non·
inverting amplifier is used to boost and buffer the Zener
to 10 V; The reference is run directly from the input
power rather than the output of the op·amp. When the
Zener is powered from the op·amp, special starting
circuitry is sometimes necessary to insure the output
comes up in the right polarity. For outputs lower than
the breakdown of the LM 129 a divider can be connected'
across the Zener to drive the op·amp.
U)
Q)
U)
co
w
...
Q)
cQ)
15 V
N
~
v+----~~------.,
JOk
>-411.----10 V
R.
M
r-.....
VOUT
I
In
Z
RI
o
o
c.......
--i-:-EQ} ~~~~P
1
1
1
1
'1
I
I
~----~--------------------------------------~~--------+--+O)~~~·
1
,I
'::"
L ____ J
STORAGE SCOPE
FIGURE 1. Block Diagram for AID Tester
14-34
-15V
4
z
~"\15V
r-"~15V
ah[F~F~·
~
.
'---!!:!....-..
•
LMI99
Uk
I
1
.-----------~~,
'
.
.---------,.-~-iJ,b;:1OJ.'---
i
S3..,....~
MANUAL
START
CONVERT
". MM74COO
·-I~
lz--.,
.r.:;,..
.
MM14""
6
13
J
•
5
ADC121B
OUT NO.'
"
15
16
__
12
J.
10
11
•Ii
11
MM"'174
NO.1
9
INPUT
'-"
~
o
,
,--;:::-"\
OD
'--..!E.....I
15V
1&~:;q'"
~'" '+' •
PB
LK''''': -.
,-C"'
....13
,
.ll"L-,r-----i,
•
. '
•5
f'
w
(11
5
I .
Z1
Z2
LH"" ~ •
To r
150
I
I
I
II
!..-.
".
I
,'7
"
I
1M
'ULLS'ALE
.
.DJUST
11
15V
".
.
"T
r---4
+ '.
~1 •
LHOOD2;s.oY
'----i',
~
I
_
5
-,
,'7
~
-
3
-15V
•
---,
~MP~ ~t,...L
LMJ2D
I
V
1r
~
.,::;::
5V 5
LH_AH+
1
V,
fL-~ '.0'"
-
TRIGGER
SWITCH
J
+
.15V
.
,
•
4
.15V
NTAl
UT
(RATon
GINPUT
~
~
15V
•
5.
·1
'"
0.'"
'M
~
..----,
:;'::'.0'"
'~,.~
~~
~
,+'
I
VERTI'ALI
-15V
c:m:::::::)
"
AOC08"
DUTND.'
1
r--
~':':"+--H--t12
14
~
~':.:.'+-_I-_~
.~~
2
B
TV
1/4MM14'14
10k
....
3
500"=$=
4
".
f>J~
ZERO
ADJUST
"v~-15vl
L __ .!:~
0.01%
".
r!!I....L.. o.".,
Z3
LHD044AH~
Y
0.01.'
.!.J! T'
15V
~.::.'-.._..G:."'t(!J
'M
P-,oo.,
rO~,
T
ZO
Z1
,
1&
,;""
I
__ J
19
1";'rI+H-t-t;-,
'i,
I .1.
~~
~'
'M
,
15
18
.
10
,
1Z'
•
~15V~
~
0.14'174
NO.'
~t::::.
I
I
'"
5,
',.,IT
0/'
lOt
15V
4
-1&.
~7
14
'D."ZOO
0."%
fi'" CJD
~.O"';=;- ~ , ,
.
CE:)
".
:
I
L _______
J·
15Y
2 -
;:
I
51
I
I
LHODoMAH
•
,
J
RAD7
IOOkN
',t---.20
r
15
'M
~
-IV
t!;
"•
8
8
~.
~",
19
ZO
,. • '.
-15V
::1--1
~
n,,!,. .
~ Li~
IDDpF
ANALOG
VOLTAGE
~". •.
r ~100
lL=L'3~
Wl4,
1&
11
12
u-L
V"
<,~
1Z
7
10
LHO~:'
11k
-;I;"
V
2
-5
5V
a",
,
-;I;"
B 16 9
,
2
'LM'''H
•
Not~
1: All op amps should have 0,01 "F power supply bypass capacitors.
FIGURE 2
6UIlsai JaIJaAU0:J a/'fJ
6L~-N'fJ
m
c
:;:
,0
......
CI)
CI)
t:
~
c
o
o
~
.......
l
~
0
0
~
0
FIGURE 4. "Component Placement" on Component Side of P.C. Board
+15V
l>
........
C
(")
o
:::J
<
CD
~
"'I
C)
.-en
c
..~
Q)
I-
~
c
o
o
....,....
o
~
~
•
00
o
~.
0
'0
·:uc~c:..
~~~
------ _0,
-
-
0
••
-
0
-
,
0
00
, .~
: • •••• -=
':t
..,
0
•
00
I II
_
_
~ 000
-..
• .....
\:
___
---7" • "
/
:
•
••
....
•"
I.
00 0:\.
~
.~==;--r
-o--...!.-. • .-
;:::'
f! ff"
___
'#00 0
•
0
0
•
-N=:==---~:~
...=-r
s-~~.-::~
- ".
~.
..!;
'.~.
;..
I
----:
D
~
•
FIGURE 5. Component Side of P.C. Board
14-38
~
L.y~ut
••
,
»'
Z
.....
.....
(0
I
FIGURE 6. Backside of P.C. Board Layout
14·39
'
....en
References for
~CI) AID Converters
National Semiconductor
Application Note 184
Robert C. Dobkin
July 1977
>
c
o
o
'0
<....
o
Interfacing between lIigital and analog signals is becoming
increasingly important with the proliferation of digital
signal processing. System accuracy is often limited by
the accuracy of the converter and a limitation of the
converter is the voltage reference. Design can be diffi·
caul if the reference is external.
For a 10V output with a 6.9V zener, the drift contribution of resistor mistracking is about 0.4 since the gain
is 1.4. The range of temperature coefficient'errors for
different components used to make a 10V reference
from a 6.9V zener are sh-own in Table III. Another
potential source of error, input supply variations,
are negligible if the input is 1% regUlated, and the
resistor feeding the zener is stable to 1%.
en
CI)
(J
cCI)
....CI)
CI)
a:
The accuracy of any converter is limited by the tempera'
ture dirft or long term drift of the voltage reference,
even if conversion linearity is perfect. Assuming that the
voltage reference is allowed to add 1/2 least significant
bit error (LSS) to the converter, it is surprising how
good the reference must be when even small temperature
excursions are considered. When temperature changes
are large, the reference design is a major problem.
Table I shows, the reference requirements for different
converters while Table II shows how the same problems
exist with digital panel meters.
Less frequently specified sources of, error in voltage
reference zeners are hysteresis and stress sensitivity.
Stress on either a zener-diode junction or the seriestemperature-compensating junction will cause voltage
shifts. The axial leads on discrete devices can transmit
stress from outside the package to the junction, causing
1 mV to 5 mV shifts.
Temperature cycling the discrete zener can also induce
non-reversible changes hi zener voltage., If a zener is
heated from 25°C to 100° C and then bac~ to 25° C,
the zener voltage may not return to its original value.
This is because the temperature cycle has permanently
changed the stress in the die, changing the voltage. This
effect can be as high as ~ mV in some diodes and may
be cumulative with many temperature cycles. The new
planar IC zeners, such as 'the LM199 (temperature
stabilized) or the LM 129 are insensitive to stress and
show only about 50 p.V ~f hysteresis for a 150°C temperature cycle since the package .does not stress the
silicon chip.
The voltage reference circuitry is required to do several
functions to'maintain a stable output. First, input power
supply changes must be rejected by the reference circuitry. Secondly, the zener used in the reference must be
biased properly, while other parts of circuitry scale the
typical zener voltage and provides a low impedance'
output. Finally, the reference circuitry must reject
, ambient temperature changes so that the temperature
drift of the reference circuitry plus the drift of the zener
does not exceed the desired drift limit.
'
While zener temperature coefficient is obviously critical
to reference performance, other sources of drift can
easily add as much error as zener - even in voltage
references with, modest performance of 20 ppm/" C
temperature drift. Zener drift and op amp drift add
directly to the drift error, while resistor error is only a
function of how well the scaling resistors track. Resis·
tors which have a high TC can be used if they track.
DESIGNING THE REFERENCE
If moderate temperature performance such as 20 ppm/
°c is all that is needed, 2 different approaches can be
used in the reference design. In the first, the temperature drift error is split equally between the zener and the
amplifier or scaling resistors. This requires a moderately
low drift zener and op amp with 10 ppm resistors.
TABLE I. Maximum Allowable Reference Drift for 1/2 Least Significant Bits Error of Binary Coded Converte,
6
8
BITS
10
310
160
80
63
80
40
20
16
20
10
5
3
TEMP CHANGE
25°C
50°C
100°C
125°C
12
14
5
2.5
1,2
1.25
0.6
0.3
0.2
1
ppmtC
ppm/"C
ppmtC
ppmtC
TABLE II. Maximum Allowable Reference Drift for 1/2 Digit Error of Digital Meters
TEMP CHANGE
25°C
5°C
2
21/2
3
200
100
20
100
DIGITS
31/2
4
10
50
2
10
41/2
5
51/2
1
5
0.2
1
0.1
0.5
*O.Ql%tC = 100 ppm/·C, O.OOl%I'C = 10 ppmtC, O.OOOl%tC ~ 1 ppmtC
14·40
ppmfC
ppmfC
TABLE III. Drift Error Contribution From Reference Components for a 10V Reference
DEVICE
lOV
OUTPUT DRIFT
ERROR
Zener Drift
0.5 ppm/"C
1 ppmfC
2ppmfC
5ppmfC
10-50 ppm/"C
20-100 ppmfC
Offset Voltage Drift
1 pV/"C
5pvfc
15pV/oC
30 pV/oC
Zener
LM199A
LM199, LM399A
LM399
1N829, LM3999
LM129, lN823A, lN827A, LM329A
LM329, lN821, lN825
OpAmp
LM725, LH0044, LM121
LM108A,LM208A,LM308A
LM741, LM101A
LM741C, lM301A,LM308
Resistors
1% (RN55D)
0.1 % (Wirewound)
Tracking 1 ppm Film or Wirewound
0.5 ppm/"C
1 ppmfC
2ppmfC
5 ppm/"C
10-50 ppm/"C
20-100 ppm/"C
0.15 ppm/"C
0.7 ppm/"C
2 ppmfC
4 pprrifC
Resistance Ratio Drift
20-40 ppm/"C
50-100 ppm
2-4 ppm
5-10
0.4 ppm/oC
-
l>
ZI
.....
(X)
~
JJ
CD
...at
CD
~
(")
CD
-...
tn'
o
l>
.......
C
oo
~
<
CD.
:\.
In Figure 1b, a low drift reference and op amp are used
to give a total drift, exclusive of resistors of 3 ppm/" C.
Now the resistor tracking requirement is relaxed to
about 50 ppm, allowing ordinary 1% resistors to be used.
The circuit in Figure 1b is modified easily for applica·
tions requiring 3 ppm/"C to 5 ppm/"C overall drift by
tightening the tracking of the resistors. For more accurate
applications, the Kelvin sensing for both output and
ground should be used. For even lower drifts, substituting
a 1 jJ.V /"C op amp, 1 ppm tracking resistors and an
LM199A zener, overall drifts of 1 ppm/"C can be
achieved. In both of the circuits, it is important to
remember that the tracking of resistors can, at worst·
case, be twice temperature drift of either resistance.
The second approach uses a very low drift zener and
allows the buffer amplifier or scaling resistor to cause
most of the drift error. This type of design is now made
economical by the availability of low cost temperature
stabilized IC zeners with virtually no TC. Further, the
temperature coefficient of this reference is easily up·
graded, if necessary. The 2 reference circuits are shown
in Figure 1a and Figure 1b.
.
In Figure 1a, an LM308 op amp is used to increase the
typical zener output to 10V while adding a worst·case
drift of 4 ppmfC to the 10 ppm/"C of the zener.
Resistors R3 and R4 should track to better than
10 ppm bringing the total error so far to 18 ppm. Since
the output must be adjusted to eliminate the initial
zener tolerance, a pot, R5 and R2 have been added. The
loading on the pot by R2 is small, and there is no track·
ing requirement between the pot and R2. It is necessary
for R2 to track R3 and R4 within 50 ppm.
In both circuits, the zener is biased by a single resistor
from the supply, rather. than from the reference output.
This eliminates possible start·up problems and, because'
of the 1.11 dynamic impedance of the IC zeners, only
R3*
14.Bk
7
Rl
Bk
1%
2
R6
10k
R21%
LM329Ar, ~
(10 ppmfC)" ~
1 36k
RS
SDk
WWDR
CERMET
R4*
40k
*
LM30B
6
'+rr;,
DUTPUT 10V
20 ppmfC
*10 ppm tracking
FIGURE 1•• 10V, 20 ppm Reference Using a Low Cost Zener and Low Drift Resistors
14·41
...CD
tn
...tn
~
,Q)
49.9k*
lZV-15V
1% REGULATE 0
Y",
>
C
o
1%
14.Bk
Bk
o
• 1%
C
~
...o
10'
.... 1
2
6\
LM30BA
-
3+/
]
LM399
"4
1%'
TEMPERATURE
STABILIZER
..
-
13~!
6.95V~ ~
OUTPUT 10V
20 ppmfC
B
==100pF
• 50k
WWOR
CERMET I
•
1%
40k
,
'...1..
T
*Optional-improves line regulation
FIGURE 1b. 10V Reference has Low Drift Reference and Standard 1% Resistors.
Kelvin Sensing is Shown with Compensation for Line Changes.
l%RE~~~A~~~---4~~--------------------"
, FIGURE 2. Low Voltage Reference
adds about 20 jJ.V of error. Compensation for input
changes is shown in Figure 1b. 'Conventional zeners do
not allow this biasing. A conventional 5 ppm reference
such as the 1N829 has a dynamic impedance of about
15ft If it is biased from a resistor from a 1% regulated
15V supply, the operating current can change by 1.7%
or 127 jJ.A. This will shift the zener voltage by 1.9 mVor
60 ppm. With the IC zeners operating at 1 mA, a 1%
shift in the supply will change the reference by 20 jJ.V
or 3 ppm. Further, power dissipation in the IC is only
7 mW, giving low warm-up drift compared to 7.5 mA
zeners. The biasing resistor for the IC zener need'not be
any better than an ordinary 1% resistor since performance
is independent of current.
,-
In this case, zener drift contributes proportionally to
the output drift while op amp offset drift adds a greater
rate. With the '1 OV reference, 15 jJ.Vt C from the op amp
contributed 2 ppm/DC drift, but for the 5V reference,
15 jJ.vfc adds 3 ppmfC. This makes op amp choice
more important as the output voltage is lowered. Of
. course, if a high. output impedance is tolerable, the
op amp can be eliminated.
APPROACHING THE ULTIMATE DRIFT
To obtain the lowest possible drifts, temperature coefficient trimming is necessary. With discrete zeners, the
operating' current can sometimes be trimmed to change
the TC of the reference; however, the temperature
coefficient is not always linear or predictable. With the
new IC zeners, TC is independent of operating current
so trimming must be done elsewhere in the circuit.
The lowest drift components should be used since
When output voltages less than the' zener voltage are
desired, the IC zeners significantly simplify circuit design
since no auxiliary regulator is needed for biasing. Figure
2 sho~s a 5V reference circuit for use with a 15V input.
14-42
1~~
____
~
________
~~
e-__ ________ ________-.
______________________
~
~
49.9k
m
14.Bk*
8k
:n
(I)
(;
1%
:::::s
(')
(I)
LM121
LM199A
6.95V
TEMPERATURE
STABILIZER
en
.....
o
...
136k
0.1%
50k
40k*
500 pF
WW
100 pF
»
.......
c
n
o
.....--"---------...;..... . ; . . - - - - - -15V
* 1 ppm tracking
FIGURE 3. Ultra Low Drift Reference
trimming can only remove a linear component of drift.
High TC devices can have a highly non-linear drift,
making trimming difficult.
Figure 3 shows a circuit suitable for trimming. An
LM199A reference with 0.5 ppmtC drift is used with
a 121/108 op amp. ,Resistors should be 1 ppm tracking
to give overall ,untrimmed drifts of about 0.9 ppm.
The 121/108 is a low drift amplifier combination where
drift is predictably proportional to offset voltage. An
offset can be set for the, 108/121 combination to cancel
the measured drift with 1 pass calibration.
Trimming procedure is as follows: the zener is disconnected and the input of the op amp grounded. Then the
offset of the op amp is nulled out to zero: Reconnecting
the zener, the output is adjusted to precisely 10V.
A temperature run is made and the drift noted. The op
amp will drift 3.6 p.V tc for every 1 mV of offset, so for
every 5 p.vtc drift at the output, the offset of the
op amp is adjusted 1 mV (1.4 mV measured at the out·
put) in the opposite direction. The output is readjusted
to 10V and the drift checked.
14-43
Although this trimming scheme was chosen since only a
single 'adjustment is usually required, compensation is
not always perfect. Hysteresis effects can appea~ in
resistors or op amps as well as zeners. Best results can be
obtained by cycling the circuit to temperature a few
times before taking data to relieve assembly stresses on
the components. Also, oven testing can sometimes
cause thermal gradients across circuits, giving 50 p.V to
100 p.V of error. However, with careful layout and
trimming, overall reference drifts of 0.1 ppmtC to
0.2 ppmtC can be achieved.
.
There are 2 other possible problem areas to be considered
before final layout. Good single point grounding is
important. Traces on a PC board can easily have
O.ln and only 10 mA will cause a 1 mV shift. Also, since
these references are close to ,high-speed digital circuitry,
shielding may be necessary to prevent pick·up at the
inputs of the op amp. Transient response to pick·up or
rapid loading changes can sometimes be improved by a
large capacitor (1 p.F-l0 p.F) directly on the op amp
output; but this will depend on the stability of the
op amp.
:::::s
<
(I)
it...
en
U)
C ...
00
O~
CQ)
...... -""",,,,,,,...,.....____-1
All
'lOOt
G~g~:~ <>--....-
START
se-
cc
ee
01
01
DO
DO
....---1
L -_ _ _ _P.GND
_- '
DIGITAL
":" GROUND
FIGURE 4. Positive Polarity AID Operating from 5V Supply. Input
Range is +1.999V.
'
14·46
l>
AID PORT
V,.
r--
OE
mrn
SC
IJiiW
0000-
OBI
OBI
OBB
OB6
~
08228
f!!!..!.
0"'
r2ll
oaz
oaz
OBI
OBI
OBO
DBO
'---
o
o
f-01
f-D6
1-- 05
f-D4
f-D3
f-D2
f-Dt
1--00
caDBDA
2=AO
AI
AD I
mr--
FIGURE 6. Flow Chart for Single Channel A/D Converter
14-47
Z
I
I\)
o
o
INITIALIZATION
INTERRUPT SERVICE
:::J
CD
~
I»
(')
CD
o
(X)
o
(X)
o
>
FIGURE 8. Flow Charts of AID Routines
14·49
«o
CO
oCO
-8
o
co
't:
oS!
c
ROTAte TWICE, CLEAR
LOWER4 BITS,SAVE IN B
FIGURE 8. Flow Charts of AID Routines (Continued)
LABEL
lAD:
8
N
I
Z
«
OPCODE
OPERAND
PUSH
PUSH
PSW
W
PUSH
B
PUSH
D
LXI
H,ADWD
MOV
LXI
6,M
H, PRTBL
MOV
A. B
-ANA
M
JNZ
FIND
INX
H
JMP
LXI
TEST
H,RTBL
ORA
RAR
JC
INX
INX
JMP
MOV
GTAD
H
H
GTBIT
E,M
INX
MOV
H
D,M
COMMENT
LABEL
; interrupt from AID
;saveH& Lon
stack
;saveB&Con
stack
;saveD&Eon
stack
; pickup AID status
word
; move word into B
; pickup priority tbl
FIND:
GTBIT:
GTAD:
A
OPERAND
XCGH
PCHL
COMMENT
; exchange DE. HL
; jump to input
routine
INAD1:
LXI
H,AD1
; pickup pointer to
AID 1
CALL
ADIN
; call common input
MOV
JMP
LXI
M,A
DONE
H,AD2
CALL
MOV
ADIN
M,A
JMP
DONE
; all done
DONE:
POP
POP
POP
POP
EI
RET
D
B
H
PSW
PRTBL:
DB
04H
DB
03H
; restore D
; restore B
; restore H
; restore PSW
; enable interrupts
; return to main
program
; 0000C100 AD3
highest priority
; 00000011 AD2 &
AD 1 next priority
INAD2:
pointer
TEST:
OPCODE
; place status word
in accum.
; mask with priority
, table
; match jump to
Find
; point to lower
priority ,
; try again
; pickup routine tbl
pointer
routine
,; start new conversion
; all done
; pickup pointer to
AID 2
; call input routine
; start new conversian
; reset carry
; rotate thru carrY
; bit was found
; point to
; next routine
; try again
; move first byte
into E
; point to next byte
; move second byte
into 0
Routine 2. 8-Channel Interrupt Service Routine with Software Priority
14-50
LABEL
OPCODE
OPERAND
PRTBL:
DB
10H
RTBL:
DW
DW
1000H
100CH
ADIN:
DW
MOV
1060H
A,M
MOV
ORA
RAL
A,M
A
JC
OFL
PLUS:
PLUS
20H
RAL
RAL
ANI
FO
MOV
OCR
MOV
MOV
ANI
OR
B,A
H
A,M
A,M
OF,
B
; Q0010000 AD5
lowest priority
; routine for AID 1
; routine for AID 2
; routine for AID 8
; input MSD plus
OFL&SIGN
; delay
; reset carry
; rotate left thru
carrY,OFL
; jump to overflow
if set
; rotate left thru
carry. sign
.; jump .to plus if set
; ORl into BCD,
MSB for minus
RAL
JC
OR1
LABEL
COMMENT
OPCODE
OPERAND
MOV
DCR
MOV
MDV
RAL
RAL
RAL
RAL
ANI
MOV
DCR
MOV
MOV
ANI
OR
MOV
SHLD
MOV
ACI
B,A
H
A,M
A,M
64
MOV
L,A.
COMMENT
; save in B
; point to LSD + 1
; input LSD + 1
; delay.
Routine 2.
MOV
ACI
MOV
MOV
INX
MOV
LHLD
RET
; into
; upper
;4 bits
FO
C,A
H
A,M
A,M
OF
C
C,A
TEMP
A, L
; mask lower bits
; save in C
; point to LSD
; input LSD
; delay
; mask upper bits
; pack
; save in C
; store HL in temp
; move L in accum.
; generate lower
address
; above memory
A,H
; converter addresses
o
; include carry
; to upper bits
; store C
; then
; store B
H,A
M,C
H
M,B
TEMP
; retrieve H L
; return,
8·Cha~·nel Interrupt Service Routine with Software Pri~rity (Continued)
ADJUSTMENT AND TESTING
Adjustment and testing of a single channel AID is done
by monitoring the memory space where the interrupt
routine stores the data word. The microprocessor is
forced to loop around a section of program with interrupts enabled. As the input voltage of the converter is
changed, this data word should also change as the converter updates it. A precision voltage reference is con·
nected to the input of the A/D and incremental voltage
steps are applied. The A/D data word should also change
according to the voltage steps.
Debugging may most easily be done by single stepping
through the program at these critical areas. No timing
problems should be encountered since the AID port
appears to be a standard peripheral or memory. In the
ADC3511 and ADC3711 the desired output is merely
addressed the same as a memory location.
At full·scale input Voltage, the data word should be at its
maximum value. If not, check the full·scale adjust on
the A/D by adjusting it so the OFL bit goes high when
the input is exactly 2.000V.
\
Multichannel systems are more difficult to check. Start
by individually checking the full·scale adjustments so
the converters overflow at 2.000V. Check the software
priority routine by forcing all status bits of the status
word high. This corresponds to all converters being
ready at the same time, a very unlikely worst-case
condition. The microprocessor should respond by out.'
putting the address of all 4 digits of the A/D port with
the highest priority along with the memR strobes,
then with a memW strobe to start a new conversion.
The next highest priority converter should then receive
its a.ddresses and memR strobes and so on down the
line.
The memory requirements of the interface depends,
of course, on the complexity of the system. The single
channel converter requires approximately 60 bytes of
program storage plus 2 bytes for data storage and 4
peripheral addresses. "
The multichannel system requires about 40 bytes for
the priority routine. and 10 bytes of program for each
converter routine. The common input routine r~quires
about_50 bytes of program and is used by all the con·
verter routines in the form of a subroutine.
Memory mapped I/O causes 64 memory locations to be
used to input an 8-channel system. The data space is
located directly above the address space for the converters a"nd 16 memory locations are used to store the
data for 8 converters.
CONCLUSION
The ADC3511 and ADC3711 microprocessor compatible
AID converters eliminate the difficulties previously
encountered in applying DPM chips to microprocessor
systems. The low parts count and low cost per channel
make distributed or remote A/D conversion practical
for a variety of data acquisition applications.
Once the priority routine has been debugged, each data
word is monitored as the input to its converter is adjusted.
_Since a common input routine is used, once 1 channel
operates, all the other channels should iliso.
14·51
N
o
'0
; rotate
mapped
; mask lower order
bits
; save in B
; point to MSD-l
; input MSD-l
; delay
; mask higher 4 bits
;' pack MSD and MSD-l
l>
ZI
s::o
_. s::
~O
.gcn
"'l>
0 ........
~C
en O
~O
... ::J
cn<
'<~
en.... CD
CD'"
30
_.
en::J'"
'C
en
m
Q)
~.
~
::J
CD
~
Q)
(')
CD
Q
0)
o0)
o
l>
«o
CO
o
co'
o
( I)
o
CO
't:
'(I)
c
~
APPENDIX A
The DC value of this pulse train is:
THEORY OF OPERATION
tON
Vour = VREF
tON +tOFF /
A schematic for the analog loop is shown in Figure A 1,
The output of SW 1 is either at VREF or OV, depending
on the state of ,the D flip·flop, If Q is at a high level,
VOUT = VREF and if Q is at a low level VOUT = OV.
This voltage is then applied to the low pass filter com·
prised of R1 and C1. The output of this filter, VFB,
is connected to the negative input of the comparator,
where it is compared to the analog input voltage, VIN.
The output of the comparator is connected to the D
inpl!t of the D flip·flop. Information is then transferred
from the D input to th~ Q and Q outputs on the positive
edge of clock. This loop forms an oscillator whose duty
cycle is precisely related to the analog input voltage,
VIN·
The low pass filter will pass the DC value and then:
VFB = VREF (duty cycle)
Since the closed loop system will always force V FB to
equal VIN, we can then say that:
VIN = VFB = VREF (duty cycle)
or
VIN
- - = (duty cycle)
VREF
An example will demonstrate this relationship. As~ume
the input voltage is equal to 0.500V. If the Q output of
the D flip·flop is high, then VOUT will equal VREF
(2.000V) and V,FB will charge toward 2V with a time
constant equal to R1C1. At some time VFB will exceed
0.500V and the comparator output will switch to OV.
At the next clock rising edge, the Q output of the D
flip·flop will switch to ground, causing VOUT to switch
to OV. At this time, VFB will 'start discharging toward
OV with a time constant R1C1.-When VFB is less than
0:5V, the comparator output will switch high. On th,e
rising edge of the next clock, the Q output of the D
flip·flop will switch high and the process will repeat.
There exists at the output of SW 1 a square wave pulse
train with positive amplitude VREF and negative ampli·
tude OV.
The duty cycle is logically ANDed with the input
frequency fiN. The resultant frequency f equals:
f = (duty cycle) x, (fiN)
Frequency f is accumulated by counter no. 1 for a time
determined by counter no. 2. The count' contained in
counter, no. 1 is then:
f
(duty cycle) x (fiN)
VIN
count = - - - . :
=--x N
(fIN)/N
(fIN)/N
VREF
For the ADC3511 N = 2000.
For the ADC3711 N = 4000.
V,N
o
o
N
I
Z
«
.,
fIN6-~""""'1
RESET
COUNTER NO.2 (+2NI
VIN = VFB = vREF x (duty cycle)
f = (duty cycle) x fiN
, Count in Counter No.1 = _I_
,
flNIN
= VREF (duty cycle)'
,
=
(duty cycle) x liN
liNIN
=~
x N
VREF
FIGURE A1. Analog Loop Schematic Pulse ModulationA/D Converter
~LECTRICAL
l>
ZI
CHARACTERISTICS
ADC3511CC, ADC3711CC 4.75 ~ VCC ~ 5.25V; -40°C ~ TA +85°C, fc = 5 cQnv./sec
(ADC3511 CC): 2.5 conv./sec (ADC3711 CC); unless otherwise ·specified.
CONDITIONS
MIN
TYP
(Note 2)
(Note 3)
VIN = 0-2V Full·Scale
ViN = 0-200 mV Full·Scale
-0.05
±0.025
PARAMETER
Non- Linearity
o
o
-1
Organization. Error
Offset Error
VIN =OV. (Note 4)
Rollover Error
Analog Input Current'
VIN+. VIN_
N
TA = 25°C
-0.5
MAX
UNITS
0.05
% of Full·Scale
3:0
-'3:
Counts
.gcn
0
mV
3.0
1.0
-0
0
Counts
-5
5
nA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
·'Operating Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Ch'aracteris·
tics'~
~O
0"'l>
........
£0
en
O
~O
"'::::1
provides conditions for actual device operation.-
Note 2: All typicals are given for TA = 25°C.
.
'
Note 3: For the ADC3511CC: full-scale = 1999 cou~ts; therefore, 0.025% of full-scale = 1/2 counts and 0.05% of full-scale = 1 count.
For the ADC3711CC: full-scale = 3999 counts; therefore. 0.025% of full-scale = 1 count and 0.05% of full-scale = 2 counts.
Note 4: For full-scale = 2.000V: 1 mV = 1 count for the ADC3511CC; 1 mV = 2 counts for'the ADC3711CC.
cn<
'<~
en_CD
CD'"
30
_.
en::::l"
'C
en
m
en
_.
D)
START CON V
~
-S'
::::I
DIGITAL TIMING
AND CONTROL.
FREDIN
;.n
CD
102
FRED OUT
S'
.103
• 104 .
0)
COMPARATOR
tiMING
+
o
0)
1
------
GND IIo-Vss
-+-I-------;
OIGITAL VCC .....
100
ANALOG vcc~=:j:=~=::;_-1
VFILTER-
l~~===============:OVERFlOW
14-_ _ _...:-_ _ _ _ _
C ·
CONY COMPLETE
SIGN
--1
VR
.,
~SWI
.vIN .......--4~~-+-I
SW2
H---.:H--.... : . . . . - - - - - - - - - - - - - _ - - - - - -.............. -VREF
v" ....._____----1
FIGURE A2_ ADC3511 3 1/2-Digit AID (*ADC3711 3 3/4-Digit A/D) Block Diagram
14-53
o
l>
~
('I)
c
C
10Mn
20V TO 2 kV RANGE, 10Mn
Note 4: All op amps have a 0.1 p.F capacitor connected across
the V+ and V- supplies.
Note 5: All diodes are 1N914.
Note 1: All VCC connections should use a single VCC point
and all ground/analog ground connections should use a single
ground/analog ground point,
Note 2: All resistors are 114 watt unless otherwise specified, .
Note 3: All capacitors are ±10%.
< ±1% ACCURACY
2V, 20V, 200V, 2 kV
(40 TO 5 kHz SINEWAVEI
IZlla
< ±1% ACCURACY
200 p.A, 2 rnA, 20 rnA, 200 rnA, 2A
DC AMPS
RANGES
AC RMSAMPS
RANGES
< ±1% ACCURACY
200 p.A, 2 rnA, 20 rnA, 200 rnA, 2 A
OHMS
RANGES
< '1% ACCURACY
200 n, 2 kn, 20 kn, 200 kn, 2 Mn
I I
I
I
~.~
... ,,-l
L
~]I~f
Pl
""
ISfH;n
"
50kn
IZ"
OffSET
ADJUST
t
~f+I!III'1 1'81111
0,
<.n
II
-t
-
Accuracy
<1%F.S.
<1% F.S.
<1%F.S.
< 1% F.S.
<1%F.S.
Overral'!ge
Display
±OFLO
+OFLO
±OFLO
+OFLO
+OFLO
C2
r-_____...
20v·nv-____...,.......,~o"~
TOVINio
fADD3501)
vCOMMON
F'IGURE 2. AC/DC Converter
14-56
l>
ZI
N
o
N
l>
C
3
,r
AX
RESISTANCE
lOBE
MEASUAED
cS'
::;:
Q)
FIGURE 3. Constant-Current Sour.ce
CALIBRATION
provements to the basic circuit of Figure 1 are possible in the following areas:
Calibrate the DMM according to the following sequence
of operations:
DC Volts
2V Range
DC Volts
2V Range
Ohms
2 MS1 Range
AC Volts
2V Range
1. Adjust P1 until the cathode voltage
of the reference c;liode, LM336,
equals 2.49V. This reduces the
diode's temperature coefficient to
its minimum value.
2. Short the (+) and (-) probe inputs
of the ADD3501 and adjust P2
until the display reads 0000.
3. Apply 1.995 volts across the (+)
and (-) probe inputs and adjust P3
until the display reads 1.995.
4. Select a precision resistor with a
value near full-scale or the 2 MS1
range, and adjust P4 until the appropriate value is displayed.
5. Apply a known 1.995V rms sinewave
signal to the DMM and adjust P5 ,
until the display reads the same.
PC BOARD LAYOUT
1. Expand the VOLTS mode to include a 200 mV
full·scale range;
2. Decrease the full-scale current·measurement loading
voltage from 2V to 200 mV; and,
3. Provide a true-rms measurement capability.
4. Increase 'resolution by substituting the ADD37013 3/4-digit DVM chip-which is interchangeable
and provides a maximum display count of 3.999.
The first 2 improvements involve a dividing down
of the AD 0350 1 feedback loop by a ratio of 10: 1,
which reduces the 2V full-scale input requirement
to 200 mV, This not only allows
200 mV signal
between the ADD3501's V'N+ and V'N- inputs to
display a full-scale reading, but implies that the maximum voltage dropped across the current-measuringmode resistance also will be 200 m V. Note, though,
that the values of the current-measurement resistors
must be scaled down by a factor of ten.
a
Additionally, a 200 mV full-scale input implies a resolution of 100 /LV/LSD. At such low input levels, the
DMM may require some clever circuitry to eliminate
the gain and linearity distortions that can arise from
the offset currents in the AC-to-DC converter.
It is imperative to have only one, single·point, analog
signal ground connection for the entire system. In
a multi·ground layout,' the presence of ground-loop
resistances will cause the op amps' offset currents and
AC response to have a devastating effect on system gain,
linearity, and display LSD flicker. Similar precautions
must also be taken in the layout of the analog and
high-switching-current (digital) paths of the ADD3501.
The third possible improvement-the reading of truerms values-can be implemented by replacing the AC'to-DC converter of Figure 2 with National's LH0091,
a true-rms-to-DC converter, and appropriate interfa?e
circuitry.
A FINAL NOTE
REFERENCES:
1. ADD3501 Data Sheet.
2. LH0091 Data Sheet.
3. LM336 Data Sheet.
The digital multimeter described in this note was developed with the goals of accuracy and low cost. For
the high-end DMM market segments, however, im-
14-57
4. Application Note AN-20.
5. ADD3701 Data Sheet.
c:
(J)
S·
CC
l>
C
C
CN
01
o....
Section 15
Physical Dimensions
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
"tJ
::r
All dimensions in inches(millimeters).
'<
(J)
r)'
-c_.
Q)
(7.1121
MAX
~~~~~~~~
rl "",~JJ
C
T ,· B
0.165
[1.310
/7.874)
MAX
~~D04S'D01S
t4J
0.008-11.012
(0.203-D.30SJ
l
0325+D.025
~~-J
(8.255
~~:~~~
0.310
(7.8741J
MAX
(4.iiij
0.050,0.010.
(1.270 !D.ZS41
D015-D.D19
{OJSI-D4S3}
O.10D!DOID
JL
0.009-0.012
(O.20J-0.305)
~.J25~~:~~LJ
~
Jril.14J'03811
0.100l0.010...J
(8.255~:~i~)
(3175)
MIN
=~D045'DD15
IOENT
,D' 81 1
3
0.11i5
(4.1911
0.037-0.050
0.02010.010
(O.SIIB!.O.254Jli
PlNND.l
II
1--0015_0019
(O.J81-D.48JI~~
(2.54oi0.254)
(~:~~:)
MIN
(2.540 to 254)
NS Package D14A
l4-Lead Cavity DIP (D)
NS Package D16A
l6-Lead Cavity DIP (D)
0.025
(0.6J5)
RAD
~
0.298
(7.569)
MAX
~~mn~~~~~~
•
0.054
R
~(I~~815g)------1~(~;~21
(~:~:~J
I
I'
MAX
rrrr~=rrr:;::'::r"=f
~
O'OD8-D'Ol~
~
LD.JOO--! 0.050'0.010
17.620)
(1.210 ~D.2541
REF
0.054
MAX
0.020-0.060
_-----.r(O'5DS-l'524J
JL
~
~ + D'D"_D'015~
D.JOO
___
D.015-D·02J-IL ~
(0.]81-0.584)
13.175)
0.10otO.ol0
MIN
(D.2OJ-D.""
0.050iO.OIO
1--(7R~2FOI--l
I--
J
IU70 .to.254)
.
0.10010.010'
(2.S40±0.254)
12.540tD.254)
--IIr--
0.015-0.02J
(0.J81-0.584)
0.020-0.060
0.125 (0.508-1.524)
(J.175)
MIN
NS Package D18A
l8-Lead Cavity DIP (D)
(Side Brazed)
NS Package D16C
l6-Lead Cavity DIP (D)
(Side Brazed)
1.010
~--------~----------~I
MAX
14
13
U
~
11
"I
0198
0.J85
PIN NO.1
MAX
~~~~~~~~
'--m-r-;r-r;lr...,-;-r-c;rr.r......,-+.,...,.."..."..,J .J.
F.l0.300
1--(7.62)--1
REF
(1372)11
0.054
~
~
rl12·3191-----1
(4,191)
{::::EvvvvvwvwMAX
{WjMAX
(:~~~=~::~:l r 0.100tO.01D
(2.540tO.254)
~
~
--H-- ~y~B4-o.3811
0.023-0.015
0.050
II------~I ~
0.165
(4.191)
MAX 0.020-0.060
~)
..
0.125
(~~~51
0.J98
(9.779) (10.109)
MAX
MAX
IDENT~
(7.569)
1---------.+I00.16 )
0.400
o.loO.tO.OIO _ I
(2.540±0.254) - ,
I
t
0.015-0.02J
_
NS Package D20A
20-Lead Cavity DIP (D)
(Side Brazed)
NS Package D22B
22-Lead Cavity DIP (D)
(Side Brazed)
15·1
II _
~II
REF
0.125
(J.17S)
MI.
CD
:::l
_.
(J)
o:::l
(J)
tA
c
.2
tA
c
n
CD
.-E
Q
0.530
0.550
iWiii
PIN NO. 1
IDENT
fii.9j)'
~rr.~~~~rr.~~~~rr.~~~MAX
MiX
'200
r---..!:!!!..MAX~
(15.494)
~
~'rD.05D±O.ul0
~~~'.
J~ ~ ~ -J~ .=±'
0.010±0.010
~
0.100iO.Ol0
~
0.011±0.002
~
(3.175)
MIN
NS Package 024A
24-Lead Cavity DIP (D)
1.400
1-------(35...' - - - - - - - - 1
MAX
(13.462)
'rn--r;n"...rn;::::;::;:;:::r=r.=;::::m:=;~n;;r-mr'j
0.200
I~-I
~11.z10:ia.zi41
I--~
12.540:1;0.254)
..j~ 0.018tO.DB2
~
0.125
13.1761
MI.
NS Package 028A
28-Lead Cavity DIP (D)
f-I-'------(3~!~,---------I1
21z·%&"O"""·. . """""1
0.510
(12.9541
MAX
~FU~IF~=rr~~[F~~·~,~,=m,,~,~,R[,,~,~·~
0.185
0.100±0.010
~
NS Package 0280
28-Lead Cavity DIP (D)
15-2
0.045
f1.1.iJJ
c_.
RADIUS TVP ___
3
(I)
~
tJ)
_.
0.165
O.GIO
I:~MAX:1
F
:."5.0."5
0.035±0.015
en
+o.oos_o.01'J
I--~----j
(15.815 ~~:~~~)
10.20J-0.J051
I
_
I
0.05010.010
r-(1.210~0.254)
II
0.100&010
0.125
(3.115J
MIN
0.018tO.002
-1t-~
1-(2.540!0.254)
NS Package 0400
40-Lead Cavity OIP (0)
0.275
--l II I
0.004-0.006
(0.102-0.152)
~~
l
1'
9B5f
MAX
16.
0.080
(2.03Z)
MAX 0.010-0.025
GLASS,
1 1 IIrt(SQUARE)
(0.254-0.635)
0.050 ~0.005
0.004-0.006
---HIT
(0.102-0.15Z)
1111
0.190
O.DBO
(Z.01Z)
MAX
0.007-0.018
I-
0.050 '0.005
_,m
I
,J""
PIN NO. I
IDENT~
r- 1O .5OB-1.0161
f~~9~;--
'''''~~, I~I
(1.270tO.1Z7)
--r,
JII ,.~,
o~
0.750-0.770
0.880-0.900
(22.352-22.860)
II 0.015-0.[119
--l ~ (0.lBI-O.48J)
!
(0.381-0.4B3)
NS Package F16A
16-Lead Flat Package (F)
NS Package F14A
14-Lead Flat Package (F)
0.390
O.OBO
0.004-0.006
~lO.015-0.019
0.020-0.040
1--(0.50B-l.016)
-1,(z.Ol2}
MAX
"
10.102:-0.1521--111
0.050 ~0.O[J5
{1.21[J.<:O.121}
.
PINNO.1
IOENT
JL'. .~'
•
{0.S[J8-1.016}
0.880-0.900
(22.J52-Z2.860)
-.-l
--llO.01S-0.019
{0.J81-0.483}
NS Package F24A
24-Lead Flat Package (F)
15-3
--.l
.~~
II
I
(6.308-&.&83)
0.178-0.195 ~
14521-U53)
0.185-0.185
.!:!!!!::!!:!!!
11.90.-2.3621
SEATING
PlANE-..
0.030
iD.mi
MAX
2 LEADS
..!:!!!::!:!!!. DIA
10~0'-0.483)
0.500
~&OD
~040
(12.701
fUll)
j.
DIA
~
8
I·~"'·
I
MIN
~ ~~
1.
0~55-0.370
(iTui":i.3iii
orLJlrr
4L
MAx
0.201-1.219
~
I---f+~
SE:~~:~l~1LJfi'4'521_UO:~'-II'0"
~
11.905-ZA131
O.IDO
'12.70) MIN
o 0 0_
~--I~
0.018-0.019
~DIA
(0.305-0.483)
0,040
11.01&)
MAX
.!!!!.
12.540)
o
I--I---(;:!::,
.
~~~~
10.914-1.168)
10.111-1.219)
NS Package H02A
2-Lead T0-46 Metal Can Package (HI
NS Package H03B
3-Lead TO-S Metal Can Package (HI
NS Package H03H
3-Lead T0-46 Metal Can Package (HI
..!:!1!=!:!!!
OIA
C4.521-4.163J
0.110-0.210
(4.512-5.3341
0.019-0.096
i'2.D-iAij
~MIN
(12.700)
.!:!!!.MAX·
SEATING'lA'''-I--='--
11.016)
.!:!!!.:!!!!.OIA
(IAOS-DAB3) of
(1.270)
NS Package H04D
Thermal Shield for H04A
NS Package H04A.
4-Lead TO-46 Metal Can Package (H I
0.358-0.310
ii.iii=i:iii)
0.305-0.335
I-----t+_~
I-_D::'::,A_~ (~:.:=::) DIA
DIA·
0.050
OJ4D-D.2BO
0.1&5-0.185
~4-~~::i~OOF~~~~
.!:!!!...
14.'91~.199~)~~~~=m~~nrr:l
112.700)
MIN
~~t~
(8.4GB-DAB3)
1---+
NS Package HOSC
S-Lead TO-S Metal Can Package (HI
0.2211-0.240
NS Package H10A
10-Lead TOoS Metal Can Package (HI (High Profile I
15-4
I
DJ50-U70
18."'~J'''+-------~
r--
DIA
I
r-I
+--1
~
14.191-4.699)
~
MAX
0.500-'.'60
112.1Qo}
MI.
(12.'00~~ ~ ~ ~ ~
~
.~J.
T
~
~)
-J ~(::::=:!!!J
rr~
~~ (D.4D6-U83)
I
(1I.116_11.684,DIA.
I
DIA
I+
I
U U U UU .:fo.o,"
0.148-0.181
~
SEATING PLANE
0.44D-DA6D
0.545-0.555
(13.B43-14.0971----i
o.•
::~:]I4·2ZJJ ~ ~ ~
0.022-0.010
(0.559-0.1621
c-,
3
CD
~DIA
~
U)
12 LEADS
0'
0.200
~
U)
0.595-0.605
US.l11-1S.161)
DIA
j
NS Package H12A
12-Lead TO-S Metal Can Package (H)
-'---'<--
O.026-0.nJ6
(0.660-0.914)
NS Package H12B
12-Lead TO-S Metal Can Package (H)
,-
NS Package H12C
12-Lead TO-S Metal Can Package (H)
0000000
1&
15
14
0.3DO±O.Dl0
{l.620!01S4}
13
IZ
11
10
!
1
0.420
0.500:1:0.010
(10.61)
~
~ -'--"-~""";;"""''''''';;'''''''---'-.~---'----'--L-.l-1
.
j
~.
O.D8D
(2m2)
MAX
,:!::,
0.060
(1.524)
MIN
MAX
..L
l..1
~.
-I -LOA'
• . .-.1 ~j
iffi"AiIMAXi
13.1151 MIN
I
l - r I---l \-I-- 0.6DO~:: ---I
~1:,~'0±0.2541
~:,~0±0.2541
0.05hO.Ol0
a.l0D±O.OfD
(15.241:) .
0.190
(4.82GI MIN
----~---II
l
0.015-0.020
~DIA
NS Package HY13A
13-Lead Epoxy/Ceramic Package (J) (Hybrid)
IB
15
14
13
12
11
O.'' !..020
000000
Z
~MAX
(3.810)
NS Package HY16B
16-Lead Metal DIP (0) (Hybrid)
000000
,
-
1
4
5
8
:.~::) TYP
NS Package HY16C
16-Lead DIP (J) (Hybrid)
15-5
en
c
o
U
_L. l_l~
'iii
-ru" -c-""-
cQ)
_D._B1_
o ±U1U
_
, J15.494
E
,-
OA9D :to.01U
r~541
c
-
D
~
U
1-1
m
11
"
17
'5
15
"
~
~02~.-I1i5.iiBoi
!-;D.090
(2.186'
TVP
0.025
1m
i~:J--f'~~!:'
1
{O.635)RAD
0291
(12.448 j'~~'
1
,
'1
2
3.
4
5
(/)
>t,
..
Ii
C , . U D ' D..,D
(28.194±0.254)
n.DSO±D.tI1D
(2&.610:1:0.254)
'
GLASS
1.25010.010
(31.750_D.Z54)
MAX
BOTH
ENDS
D."D
(15.240)REF
j t ~";'D.D I
II
(2.540::!:0.051)
(3.175)
0.100 to.Olo
(2.540±0.2541
MIN
.DJ.,3
0.017 -0.002
10A32 +0..078)
~
-0.051
TVP
NS Pa~kage J08A. .
8-Lead Cavity DIP (J) .
: NS Package HY24A
.
24-Lead Epoxy/Ceramic Package .(J) (Hybrid)
D.azs
0.025(0.6351.
(0.635)
RAD
RAD,
1
0.160
173"_'.12B' '(~~':'
~
GLASS
SEALANT
~~::=~~, JGf~~~~~~~~;;;
I
j L --II-
O.Doa-ODI2J
(0,203-0.305)
~0.3B5±0025*!
0.100.
(9.779:t0.6351
12.5401
MAX BOTH ENDS
tl'
0.160
o.290-'.32D
~J
--<
D.385 'D.02''t"
(9.719 'D.63"
I--
, ...,
IIM"A'X'
D.""'.D02
(0.457±0.0511
0.100:1:0.010
~
NS Package J14A·.
l4:!-ead Cavity DIP (J)
NS Package J16A
'l6-Lead Cavity DIP (J)
lii;~:OI
I"
~~~~~~~~~~~~~~~~,
GL~
0.025
(D.6351
0.515-0.525
RAD
L-r.T~rr,",orr.T,"rr,",orr.rrcmrr.~Hr~(I3~B1rl3'3351
l---
0.590-0.620
0200
(5.080)
--1
IH=ii1".02'
~
MAX 0.020-0.070
j-r~
r
11.008-0.012 ~
6.25° ...,015
1--(15.875 -+(1.635)----1
-(1.381
0.060-0.100
11.524-2.5401
I-~I
I .
'. NS ~ackage J24A
24-Lead Cavity DIP (J)
15-6
_L
D.'" 'D.DD2
~ II(DA5JiO.DS1)
IZ.540±0.254)-l
0.125
(11751
MIN
D.125
{O.457±O.D51J
(4.445)
I
.
0.280-0.320
. ID.'DB-I.718'
~
~j I- -11-
.1
-----l
D.ZOD
0.160
~
f D.J.S
L
---L
.
(.\0.&35 .D.I21)
-D.3B1
(2.159)
4
'Bo.D20_0.010
SEALANT
. I:·:::,J
(U54±D.0511
3
"M~
-----1
~
5+0·005
0.02 -0.015
~
2
0.060;;0.005
.c
0.
MAX GLASS
(1.3911
MAX
(1.524)
CO
,~
ilml
8"',
DADO
r;.r.o.m
0.092
fzT3i,
01.
NOM
0.010
~
I
M=4
0.13010.005
i~--L~'''·'·''5 'JJ
I (0.22B-0·!~~5!0015
1·
+0.025
0.325-0.015
---
0.030
(0.16Z1
MAX
~Il
~
I::)
TV.
(8.Z55~:~~)
13.3"".12)1
-/1---,
t.t
~(~~~B'
I
-l
(3.115)
0.01810.003 MIN
(0451:1:.0.0161
~
f--
(8.255~:;:~)
:r:
]
4
3
.040
~
i1.iiiif
o13D:l:.O.o05
11~&511
_TV'
~D"D.12l)
'J
I
0.32S+0.025
c_.
ii.35ii1iilli1
--.i
SQUAR'
0.030
(0.762)
MAX
02S0:t0005
iW2i
bffi=;F.FF.~--.i
0.300-0.320
(1.&20-1.121)
MAX:1
0009-0015
(0.229-0.381)
D.045.toDI5
11.14310.381)...J
=rt.zo
J I-I-lL 0.018:1:.0.003
l-
(0.45hO.0161
'(::~~)
~
13.1151
0.125
MIN
10.5081
MIN
,
TV'
NS Package NOBA
B-Lead Molded Mini-DIP (N)
NS Package NOBB
B-Lead Molded Mini-DIP (N)
D.ol2
i2IDi
DlA NO!'tl
0.300-0.320
0.030
0.030
117n:.:'''~2)
MAX
_
Ro.o,,·o.D15
I
0.325
~:~:
I
(iU62j
0.300-0.320
0.065
0.130 10 DOS
11.&511
~
'J
I0.2Z9-~~::110.o1S
11.90510.381)
1 1-
~
~
Pr 'J
==r},
L
II 0.01810003 ~ (OM~~I'
~ -1~(0.451iO.076)(t!~5)
I
.
0.325::~~:
MAX
[
0.065
0.040
(1.651)
re_~________~~-+,.~I~.127;
0.0"·0.015
10.229-0.381)
0.07510.015
(1.905±D.311)
~yS:O)
(a.255~:~~)
NS Package N14A
l4-Lead Molded DIP (N)
PIN NO. IIDENT
17:f
0.030
(0.7621
D.'"
~
.j
U25 :::::
~ 1"~'~""·""·""~
(1.255 ~::~)
0."'.0.."
I"" .0381)
0.130:1:0.005
....,--------...!.!.::....-H---i
11.&511 ......
(0.229-0.38'1
I
0.100
(2.5401
TV'
NS Package N16A
l6-Lead Molded DIP (N)
0.092
IU37)
DIA NOM
0.300-&.328
~J
I
too
J I_"
(2.~0~
NS Package N 1 BA.
la-Lead Molded DIP (N)
15-7
0." . .0.0113'
~1t--IOA5"•.D16)
0.13010.005
CD
::I
en
c)'
::I
en
en
c
1.210
.-en
I
0
cQ)
1
0.082
if.iffi
.5
C
O.540!D.D05
RAD
~I
j
-co
.~
en
0.030
~
(0.162)
0.075'
MAX
J:
0.160±0.005
D.
NS Package N24A
24-Lead Molded DIP IN)
1A1D
".,: I
1
D.'"
(1.5151
RAD
PIN NO.1 IDENT
0.550tO.D05
~~r.r~-r.rr.~~,,"-r.~~~~~rr..,~(13'71D'1211
0.050
0.100
(2.5401
TV'
II
O.018.±O.o03
-II-- (OASl ±O.o76)
NS Package N28A
28-Lead Molded DIP IN)
2.070
I---------------------(~··")----------------------~·~I
Q393131l&35M3312
MAX
21
1
o.O&z
(1.5151
a.sso±o.ODS
, RAD
PIN NO. 1 !DENT
0.030
iD.iiii
:.'
.
0.050
~O.600-D.620~11.524IMAX ~.
\.'
11.2101
0.130io.005
0.060
Ir(1U~7")~L~.:
rI---
,,0"
~L.
~(:~::=:::::~.
---t
0.825-0:015
0.015±O.o15
(1.905 .DJ81)
(15.875 ...635)
-0.311·
I
,--
-I
I -
--,
.
r-
. '---If-
0.100
(U40)
TYP
.
NS Package N40A
.40-Lead Molded DIP IN)
15-8
==r1,
.
0.018iO.003
(0.457 '0.076) _
•
012510.5081
(3:17&) MIN
MIN
"'tJ
:::r
'<
en
_.
(")
Q)
0.050-0.080
D.0D4-0.006
(0.102-0.152)
a.aSDtO.ODS
0.010-0.025
~t+
IIII
_.
(~ ~~:=~D~~~)--
f-
(1.270-2.032,---j
0.337-0.350
(a.5£a-B.BgD)'-1------~
0010-0025
10254-06351
(0.254-D.635)
iI 1
0050 0005
~I
::J
0300
(76211)
MAX
GLASS
I
,_wl
(0.508-0.889)
PIN NO.'.............
IDENT
~
w~"' JI~.
D.840-0.B611
0.015-II.01S
(0.381-0.483)
II
---II--
TV'
l,,·ri2~.b'..;4~5~5".",.,b't .. I
0.940-0.960
(23.815-24.3B4)
O.Ol!i-O.DI9~1
(O.l8t-O.4HZ)
l--
lo.508_,.016I
NS Package W14A
14-Lead Flat Package (Wl
0.115-0.185
0.115-0.185
(4.445-4.699)
SEATING
PLANE
1114.445-4.6991
1 .
~ L___ J-----r
I-o--i
~
0.500
0.090
(12.70)
MIN
(Z.286)
NOM
.
0.025
~ ~ ~
(D.6J5)
MAX
UNCONTROLLED
L--d !t";:,;"
I
NS Package W16A
16-Lead Flat Package (Wl
I-----TV'
(0.457)
0.045-0.055
(1.143-1.397)
~ ~ (::~~:~ =::~;~~)
(2.413-2.667)
..
0.045-0.055
::::'"" ~
JWt
10Q NOM
10Q NDM
1:::::=:::::1
NS Package Z03A
3-Lead TO-92 Plastic Package (Zl
15-9
TVP
BEfORE LEAD FINISH
D.agS-D.lUS
en
o
:::J
en
1615141l12111D9
PINNO.!
IDENT
c
3(D
~
The Data
Bookshelf:
To·ols For
The Design
Engineer
National Semiconductor's Data Bookshelf
is a compendium of information about a .
product line unmatched in its breadth in
the industry. The many Data Books
referenced here represent National's
entire line of devices, devices that span
the entire spectrum of semiconductor
processes, and that range from the
simplest of discrete transistors to
microprocessors - those
most-sophisticated marvels of modern
integrated-circuit technology.
Active and passive devices and circuits;
hybrid and monolithic structures; discrete
and integrated components ... Complete
electrical and mechanical specifications;
.charts, graphs, and tables; test circuits
and waveforms; design and application
information ... Whatever you need you'll
find in the designer's ultimate reference
source - National Semiconductor's Data
Bookshelf.
Ordering
Information
All orders must be prepaid. Domestic
orders must be accompanied by a check
or a money order made payable to
National Semiconductor Corp.; orders
destined for shipment outside of the U.S ..
must be accompanied by U.S. funds.
Orders will be shipped by postage-paid
Third Class mail. Please allow
approximately 6-8 weeks for domestic
delivery, longer for delivery outside of the
U.S.
Nationa~'s
Data Bookshelf
Order Form
Please send me the volumes of the National Semiconductor DATA BOOKSHELF that I have selected below.
I have enclosed a check or money order for the total amount of the' order, made payable to National
Semiconductor Corp.
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Purchase Order # _ _ _ _ _ _ _ __
Street Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _--'-_ _ State/Country _ _ _ _-'-_~_ ___'_Zip _ _ _ _ __
Description
Available
_ _copies @ $4.00, CMOS Databook, 1978 ........ ; ............... Now ......... Total $ _ __
_ _copies@$4.00,DataAcquisitic:>nHandb()()k,,1978.: ............ September ... Total $ _ __
_ _copies @ $4.00, Interface Databook, 1978 .. : .......... : ......... October ...... Total $ _ __
_ _copies@$4.00,LinearApplicationsHandbook,1978,; .......... October ...... Total $ _ __ _copies@$4.00,LinearDatabook,1978.: ........... ~ ......... September ... Total $ _ __
_ _copies @ $3.00, Voltage Regulator Handbook, 1978 ........... : September ... Total $ _ __
-copies @ $4.00, Memory Databook, 1978" .............. : ...... Now ......... Total $_----:_
_ _copies @$4.00, Memory Applications, 1978· .......... :: ....... Now ......... Total $ _ __
_ _copies @ $3.00, Microprocessor Applications in Business,
Science and Industry, 1977 ;.: ....... ~ .. :; ... Now ......... Total $ _ __
_ _copies @ $4.00, SC/MP Microprocessor Applications, 1977 ...... Now ......... Total $_~_
_ _copies@$4.00,MOS/LSIDatabook,1977 ...................... Now ..... , ... Total $ _ __
-copies @ $3.00, Pressure Transducer l:iandbook,.1977 ..... : ... Now· ......... Total $ _ __
.
t.
-copies @ $3.00, Special Function Databook, .1978 ............. November .... Total $ _ __
_ _copies@$4.00,DiscreteDatabook,1978 ........... ,' ........ ,... Now ......... Total $ _ __
_ _copies @ $4.00, TTL Databook, 1976 .......................... Now ......... Total $ _ __
Sub~otal $ _ __
California residents' add 6% Sales Tax*$ _ __
Grand Total $ _ __
Send a facsimile of the above form to:
National Semiconductor Corp., c/o Mike Smith
P.O. Box 60876, Sunnyvale, CA 94088
Postage will be paid by National Semiconductor Corp. Please allow four to six weeks f0r"delivery.
'San Francisco Bay Area residents add 6V2% Sales Tax.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:06:20 09:12:55-08:00 Modify Date : 2017:06:20 09:50:06-07:00 Metadata Date : 2017:06:20 09:50:06-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:1eb96f8b-459c-f946-9c9c-9af7756d7b8f Instance ID : uuid:b70771b9-f79a-7a41-925b-1bb7bab37ca4 Page Layout : SinglePage Page Mode : UseNone Page Count : 642EXIF Metadata provided by EXIF.tools