1978_National_Memory_Applications_Handbook 1978 National Memory Applications Handbook

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MEMORY
APPLICATIONS
HANDBOOK

Edited by
Charles B. Mitchell
Manager, Memory Components Applications
and
William C. Johnston
Senior Memory Applications Engineer

National does not assume any responsibility for use of any circuitry described; no circuit patent licenslls are implied; and National reserves the right, at any time without notice, to change said circuitry.

MEMORY
APPLICATIONS
HANDBOOK

Introduction
Dynamic Read/Write Memory
Static Read/Write Memory
Read Only Memory
PROMs and EPROMs

•DI
III
III

CRT Display Applications

[II

Charge Coupled Devices

III

Memory Support Components

DII

Microprocessor Guide

DI
mJ
III

Systems Applications
Reliability
Definitions and Standards

[fJ

National's Literature Index

iii
III

Memory Databook Referral Index
iii

Table of Contents

SO
0

:::J

••
••
•

President's Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1·1
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1·2
Future Memory Technology Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1·3
Static or Dynamic - The Selection Process for a Memory System . . . . . . . . . . . . . . . . . . . 1-8

Section 2- Dynamic Read/Write Memory

••

Dynamic RAM Board Design Made Easy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·1
A Memory Design for an aOaOA·Based Microprocessor System. . . . . . . . . . . . . . . . . . . . . 2·9

•
••
••
• • ••

•

fit

Section 1-lntroduction

••

MM5290 16k RAM Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Trouble Shooting Check List for Memory Systems Using the MM5290 . . . . . . . . . . . . . . . 2-25
MM5290 Bit Map and Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
MM5290 RAM Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Trouble Shooting Check List tor Memory Systems Using the MM52aO . . . . . . . . . . . . . . . 2-33

Section 3-Static Read/Write Memory
Static RAM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 3·1
Interfacing Static Read/Write Memories to the 80aO . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Interfacing the 6800 Microprocessor to National CMOS MM74C910 Memory . . . . . . . . . . . 3-7
1k CMOS RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

. . . . . . . . . . . . . . . . . . . 3-9

IDM2901 A File Expansion Using the DM85S68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

Section 4-Read Only Memory
PROM Patches fonhe MAXI-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ROM Emulator Using a Non-Volatile RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

•

•••
••
•• •

Custom ROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
How to Design with Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Section 5-PROMs and EPROMs
A Guide to Implementing Logic Functions Using PROMs . . . . . . . . . . . . . . . . . . . . . . . .

5-1

MOS Encoder Plus PROM Yields Quick Turnaround Keyboard Systems. . . . . . . . . . . . . ..

5-5

PROM Power-Down Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-9

A PROM Programmer for the SC/MP LCDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Bipolar PROM Programming Procedure . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . _ ... 5-36
Programming Equipment for National PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5·38
EPROM Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39

DESIGN AID
APPLICATION NOTE
BACKGROUND INFORMATION
TECHNICAL DESCRIPTION
v

Table of Contents

Section 6-CRT Display Applications

•

•
•

•

Simplify CRT Terminal Design with the DP8350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

••
•

•• •
••
••

•

••
•
•
••

•
•

6-1

DP8350 Series Programmable CRT Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
DM8678 Bipolar Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
128 Characters with the DM8678 . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . 6-26

DM8678 Character Generator Emulator . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . 6-28

Section 7- Charge Coupled Devices
The MM2464: A Practical Charge Coupled Device for Digital Memory Applications . . . ..

7-1

Section a-Memory Support Components
Memory Support Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8·1

Improving Power Supply Reliability with IC Power Regulators .. . . . . . . . . . . . . . . . ..

8·5

A Cheap and Easy DC·DC Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8·8

National's Voltage Regulator Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

Section 9-Microprocessor Guide
National's Full Spectrum of Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

9·1

National's Fast IDM2900 Bit-Slice Microprocessor Family. . . . . . . . . . . . . . . . . . . . . ..

9-2

National's Spectrum of Microprocessors and Peripherals. . . . . . . . . . . . . . . . . . . . . . ..

9-3

Section 10-Systems Applications
Systems Application of MM5270 4k Dynamic RAM
Systems Application of MM5290 16k Dynamic RAM . . . . . . . . . . . . . _ . . . . . .
Systems Application of MM74C929 CMOS RAM . . . . . . _ . . . . . .

10·6
10-10

Section 11-Reliability
National's Reliability Programs _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Section 12-Definitions and Standards
Definitions of Frequently-Used Acronyms . . . . . . . . . . . . . . . . .

12-1

Excerpts from the Proposed I EEE Standard for Semiconductor Memory
Data Sheet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

Section 13-National's Literature Index
Databooks Available from National. .... _ . . . . . . . . . . . . . . . . . . . .

. ..... 13-1

Section 14-Memory Databook Referral Index
Referral Index to National's Memory Databook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

DESIGN AID
APPLICATION NOTE
BACKGROUND INFORMATION
TECHNICAL DESCRIPTION
vi

Page Index of
Devices Discussed

::::l

i><

Device

Page

IDM2900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·1
IDM2901 A . . . . . . . . . . . . . . . . . . . . . 3·22,9·1, 9-2
I NS2650 . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1, 9·3
INS4004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
INS8060 (SC/MP) ............. .4·3,5-13,9-1,9-3
INS8080A . . . . . . . . . . . . . . . . . . . 2-9,3-3,9·1,9·3
INS8900 . . . . . . . . . . . . . . . . . . . . . . . 3-1,9-1,9-3
DM74S97 . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11
DM74S188. . . . . . . . . . . . . . . . . . . . . . . . 5·36, 5-38
DM74S287 .......... 4·1,4·11,5-9,5-36, 5-38, 11-3
DM74S288. . . . . . . . . . . . . . . . . . . . . 4-1,5·36,5-38
DM74S387 . . . . . . . . . . . . . . . . . . . . 5-36,5-38, 11-3
DM74S570 . . . . . . . . . . . . . . . . . . . . . . . . 5-36,5-38
DM74S571. _ .... _ . . . . . . . . . . . . . . . . . 5-36,5-38
DM74S572/573 .. _ .. _ . . . . . . . . . . . . . . 5-36,5-38
DM74S574 ........... _ ........ 5-36, 5-38, 6-28
DM85S68 ......... __ . . . . . . . . . . . . . . . . . 3-22
DM8575/6 ..... _ ... ___ . . . . . . . . . . . . . . . .4-14
DM8678 ....... _ ......... 6-12, 6-22, 6-26, 6-28
DM87S2951296 .. _ .. _ . _ ..... _ ...... 5-36,5-38
DP8350 ........ _ ..... _ . . . . . . . . . . . . 6-1,6-10
MM17020_ ..... _ .... _ ..... _ .. 5-38,5-39,11-3
MM2102A_ . . . . . . . . . . . . . . . . _ ........ _ .11-3
MM2111A ..... _ ..... _ ..... _ ........ _ . 3-5
MM2112A_ .......... _ ..... _ .......... 4-3
MM2316E _ . . . . . . . . . . . . . . . . . . . _3-5,4-11,4-12
MM2464 ....... _. _ . . . . . . . . . . . . . . . . . . 7-1
MM27080 ............ 4-11,4-12,5-38,5-39, 11-3
MM52030 . . . . . . . . . . . . . . . . . 5-7,5-38,5-39, 11-3
MM52040 .............. 4-3,5-7,5-13,5-38,5-39
MM5235 _ ............ __ . . . . . . . . . . . _ .. 4-1
MM5257 ......... _ ........... _ .... 3-1,7-8
MM5270 _ ..... " ..... _ ........ 2-6,10-1,11-3
MM5280 .. _ ....... ___ . . . . . . . . . . . . 2-39,11-3
MM5290 .......... 2-9,2-17,2-25,2-26,2-29, 10-6
MM52157 ...... _ . _ . . . . . . . . . . . . . . . . _ .. 6-12
MM52179 . . . . . . . . . . . . . . . . . . . . . . . . . _ .. 6-12
MM5740 _ .. _ .............. _ ... __ ..... 5-5
MM74C910 .............. _ ......... _ .. 3-7
MM74C920 ..... _ . . . . . . . . . . . . . . . __ . _ .. 3-9
MM74C921 ..... _ . _ . . . . . . . . . . . . . . . . . . . 3-9
MM74C929 ..... _ . . . . . . . . . . . . . . . . _3-9,10-10
MM74C930 ....... _ ... _ . . . . . . . . . . . . _ .. 3-9

vii

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Section 1

Introduction

President's Message

Dear Customer:
The exciting future of memory applications is
limited only by our collec~ive abilities to make
use of the continuing stream of rapid
technological advances. Annual consumption of
semiconductor memory components has already
surpassed a half billion dollars per year and will
cross the one billion dollar level within the next
three years. Years ago National established the
reputation as a high volume supplier of high
quality, cost-effective components for the
complete range of discretes, linears,
optoelectronics, transducers, A/D and D/A,
hybrids and large scale integrated memory,
microprocessor, and logic arrays. We are pleased
to continue our expansion of this broad product
line to include the memories you will require in
the future. Our world-wide network of factory
representatives, local stocking distributors, and
field applications engineers is at your service to
help meet your needs - just give any of them a
call.
We appreciate your interest in National's
products and services, and look forward to
supplying your present and future requirements.
National Semiconductor
Corporation

/
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1-1

~
-

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Preface

0..

We would like to express our appreciation to the authors
of the applications and support material whose names
are listed at the head of their work. We also express our
appreciation to the people listed below who helped in
data gathering and preparation.

The application of today's memory components can
present either another day-to-day engineering problem
or an immense task involving a full team of design and
components specialists. This does not mean that designing
an add-on memory for a large mainframe computer is
more difficult than producing a memory system based
on a two-chip microprocessor (it most likely is not).
The difference in complexity may well depend on how
your organization is structured. In some organizations
the memory designer concerns himself strictly with
memory proper. In other organizations, a given engineer
may be directly involved in designing the entire system,
from the screws that hold the enclosure together to the
choice of memory components. But whether your
interest in this book is solely to obtain the MM5290 bit
map or because you want help with your first dynamic
RAM design, we hope the end result will be the same:
optimization of your design engineering effort.

J. Bizjak
E. Bohn
C. Boettcher
D. Brown
C. Carinalli
P. Clemo
D. Cole
W. Curtis

T. F redri ksen
M. Frie
W. Fowler
P. Hillen
H. Holt
H. Marks
G. Miles
R. Pease

M. Rampleburg
G. Rice
N. Sevastopoulous
A. Shultz
F. Smith
J. Sutherland
D. Whetstone
F. Wickersham

In addition we would like to thank all those who helped
in proofreading and typing.
Memory Component Applications
National Semiconductor Corporation
Santa Clara, California

It would be impossible to make a memory applications
handbook comprehensive. However, we have tried to
make the scope of this book broad with respect to
application as well as product type (made possible by
the broad range of product National produces). In order
to relate to the real-life problems of the design engineer,
we have attempted to present actual systems as examples.
Todo this we have enlisted the aid of National's systems'
divisions and their personnel. To provide full credit to

THE FINE PRINT

The circuit diagrams and schematics contained in this handbook
are presented as a means of illustrating typical memory component appl icatians. Un less otherwise stated, they have been
checked and breadboarded and in some cases are in production.
However, complete information for circuit construction is not
presented, as these circuit diagrams are intended only as representative examples. National Semiconductor cannot assume any
responsibility for errors, oversights, or other examples of human
frailty.

these contributors, we have included their names with
the applications,· bllt we ask that, should questions arise,
you do not initially contact these perple directly. We
ask instead that you contact your local National sales
representative or this Memory Applications group.

P.S.: You don't get the patent rights. either.

If you find any errors or omissions or have other contributions to make, please contact us. We welcome your
suggestions and will try to include them in future
editions.

'----_ _J
1-2

Future Memory
Technology Development

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National Semiconductor
Thomas Klein*
January 1978

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ABSTRACT: Semiconductor integrated circuit based
memory devices became the dominant Random Access
Memory technology in less than 8 years. They were able
to achieve this because their batch manufacturing process allowed a very rapid reduction of cost per bit of
storage through technological changes to increase batch
density. Continued progress in densitY improvement at
essentially unchanged rates is still feasible. It will,
however, require major changes in manufacturing,
device and material technology.

These trends can be classified under the following categories:
a. Continued evolutionary process of memory cost
reduction through more advanced circuit and device
design techniques and improved process and manufacturing efficiencies.
b. A significant change in device and circu it sizes
through major changes in pattern definition technology
and an electrical scaling of devices to take advantage of
the size reduction.

Since the beginning ofthe 70's, semiconductor integrated
circuits used as digital storage elements have become a
very significant factor in the total spectrum of information storage technology. They became the dominant
technology for random access memories and are beginning to make inroads into the slower serial access memory
market, presently dominated by magnetic discs and
drums.

c. Charge Coupled Device and Magnetic Bubble Domain
device based memory technologies.

The ability of integrated circuit technology to continue
to offer digital data storage at very rapidly decreasing
cost per bit of storage is a consequence of the batch
manufacturing process. It allows introductions of new
products which are cost effective even at very low
manufacturing efficiency level, obtain very steep cost
reduction during product life by rapid increase of
manufacturing efficiency and continue to stay on the
steep cost reduction curve by going to a higher level of
integration when cost improvements through improved
manufacturing efficiencies are starting to flatten out.

INITIAL
PRDDUCT

However, to go to a higher level of integration, which in
case of Random Access Memory circuits, usually means
a four-fold increase in number of bits on the chip, a
significant improvement in batch densitY is required,
otherwise no benefit is derived (Figure 1).

\
\

This batch density (i.e., number of potentially good
storage elements processed together as a single unit
(Le., a silicon wafer) has shown an even higher rate of
growth than the much more visible increase in the number storage bits/memory circuit.

\\ OVERALL LONG·TERM TREND

\ OF COST/FUNCTION

\
TIME (YEARS)

During the past eight years the number of potentially
good storage elements contained on a single silicon wafer
has risen from about 50,000 to over 6 million, with the
cost of processing a wafer rising only very slowly and
manufacturing efficiency expressed as the percentage
of good units staying level or improving slightly.

NOTES:

Future progress in memory technology can be examined
in terms of this single variable common to all present
and future solid state memory technologies.

(1)

Product is introduced, very little or no competition.

(2)

Product is multiple sourced but prices still hold up as
production is limited.

(3)

Production expands dramatically as yields improve, com·
petition is fierce, prices tumble, marginal suppliers are
beginning to drop out.

(4)

Significant yield improvements are no longer available, new

product is beginning to compete for the same market,
competition is still intense, suppliers still drop out.

(5)

There are several technological trends that are unfolding
right now which are likely to impact future memory
technology developments.

Major market share is taken by new generation of product,
market shrinks but prices hold up as competition is minimal.

FIGURE 1_ Typical Decrease of Memory Products'
Prices/Costs During Product life

*Refer to Introduction. This paper presented at COMPeON 1977

1-3

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a. EVOLUTIONARY PROCESS
defines a theoretical minimum cell size of 4 f2 where f is
the minimum feature size determined by the limits of
pattern definition technology.

This approach has so far been the most successful and
continued improvements may still be expected. In fact,
as long as this is a viable path for future development,
it is likely to be the most vigorously pursued approach.

Cell size eight years ago was a rich 200 f2 leaving plenty
of room for improvement. Today's cell size of 20 f2 or
less is sufficiently close to the theoretical limit of 4 f2
that we can no longer project a rate of improvement
comparable to past norms. We will do extremely well if
we can extract a further 3-fold improvement.

In terms of its future potential, we might examine past
contributions to batch density improvements.
The total batch density improvement of 120·fold in
eight years was contributed by:

Wafer size improvement will continue at an essentially
constant rate. Wafer size increases are important not
only for increased productivity, but wafer size is strongly
correlated to maximum economically manufacturable
die size (Figure 3). Wafer diameter has been increasing
at a rate of about 1.4 times every four years. This rate of
increase is tied not only to the rate at which equipment
manufacturers can develop new tooling to handle the
larger wafer size, but also to the rate at which capital
is invested in the semiconductor industry.

1. Higher bit density through design and process innova·

tion: 13.5x
2. Larger wafer area: 4x
3. Smaller feature sizes and tighter alignment tolerances:
2.2x
Continued improvement based on comparable contribu·
tions from the same sources is no longer feasible for
the following reasons:
Design and process improvements, the most profitable
source of past batch density improvement, is getting
sufficiently close to its theoretical limits so that progress
in it is Iikely to slow down (Figure 2). It is clear that
regardless of whatever technique we use to design or
build a memory cell, it must have at least 2 features in
both x and y directions, one to store the information
and one to separate it from the adjacent cell. This

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4.00"

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(1973)

(1971)

(1981)

WAFER DIAMETER
~
~

FIGURE 3. Maximum and Economic Die Size as a
Function of Wafer Diameter (Time)

10'

Feature size reduction. While we expect significant pro·
gress in this area, little of it can be considered evolu·
tionary. In the past, progress in this area was completely
evolutionary; contributing relatively little to density
improvement. In the next 5 to 10 years we expect
major changes in the technology and we will discuss
those changes in detail later.

>
~

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107

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~

10'

We also expect that manufacturing yields will increase in
the next 5 to 10 years. This will be a factor in cost
reduction but not in density.
1969

1971

197]

1975

1977

1979

1981

1983

The reason for yield improvement is the expected
reduction in the rate of density improvement due to
design and process improvements. Present manufacturing
yields which include losses in wafer manufacturing,
die sort, assembly and final test vary from under 5% for
a leading edge product to about 25% for a mature
product.

1985

YEAR

NOTES:

(1)
(2)

Theoretical limit, current wafer and feature sizes.
Theoretical limit, assuming continued improvements in
wafer size increase and feature size reduction.

(3)

Theoretical limit, assuming constant rate of wafer size

(4)
(5)

increase and an increasing rate of feature size reduction.
Increase due to design and process innovations.
Increase due to feature size improvement.
I ncrease due to wafer size.

(6)

In the past, as long as significant density improvements
were available from design and process innovations,
engineering effort and talent was better utilized in
trying to improve a new high density product's yield
from 5% to 25%. Trying to extract the yield improve·
ment available between 25% and 50%-60% which is

FIGURE 2. Past and Projected Contributions to Batch
Density Improvements
1-4

probably the practical upper limit for any semiconductor product, was both harder and less rewarding. With
less potential improvement available from design and
process innovations, we can probably expect higher
overall yields for mature products.

smaller defect sizes the most immediate consequence of
feature size reduction is yield reduction.

In summary, the evolutionary trend, while it will still
contribute significantly to future cost reductions, its
contribution will be proportionately less than it has been
in the past.

S107

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b. FEATURE SIZE IMPROVEMENT
SH]6

Minimum feature size has been remarkably stable over
the past 20 years of integrated circuit technology
development. This was probably due to the fact that
there was very little change in pattern definition techno·
logy. Up to 1975 the pattern definition technology,
at least at wafer level, was basically unchanged from
what it was in the late 50's and progress was obtained by
better engineering, controlling and understanding the
process and using improved photochemical materials.

====

ElECTRONBEAM

WAFES~~::~SURE

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S105

------'------PROJECTION ALIGNER

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I CONTACT PRINT

5104

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AliGNER

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Maskmakinq technology made much more consistent
progress, converting from an essentially manual drafting
to a completely computerized pattern definition process.

~--~t---

Since the mid-70's, very significant changes are begin·
ning to occur at wafer level too. Availability and accep·
tance of projection aligners is the first and probably the
most significant of these changes.

MINIMUM FEATURE SIZE, f (J.1)

FIGURE 4. Cost of Key Equipment for Various
Pattern Definition Technologies and Minimum
Feature Sizes

Their introduction did not lead to an immediate reduction in feature size, but the control, reproducibility and
accuracy of mask dimensions that they allow, makes
feature size reduction a much more realistic task.

X-ray lithography techniques have still to resolve three
basic problems.
a. Maskmaking technology

Improved high resolution photoresists are also becoming
available.

b. Sufficiently intensive X-ray sources
c. Pattern registration

Dry etching techniques are important technological
achievements and will also be contributing to feature
size reduction.

If they can solve these problems, they can be potentially
very powerful as they can use a fixed mask and do not
have to regenerate the entire pattern at every exposure.

Electron beam and X-ray lithography- are the most
frequently mentioned technologies to achieve significant
reductions in feature size.

Summarizing present status of pattern definition technologies, we can project improvements in optical pattern
definition technology to yield a 5 to 8-fold increase in
batch density over the next 5 to 8 years. This will
represent a 2.5 to 4-fold increase in the rate of progress
compared to past experience. Even higher rates of
progress are possible if electron beam and/or X-ray lithography matures sufficiently to become cost effective,
over the next 5 to 8 years.

There is undoubtedly significant progress being made in
these areas and some of the results are impressive.
However, they have to overcome some very significant
technical and economic hurdles before they can make an
impact on memory technology (Figure 4).
Electron beam writing techniques are already available
for maskmaking purposes where they offer some very
real advantages. For direct writing on wafers, however,
they still have to improve significantly and come down
in price before they can make an impact on memory
technology. Presently, projected machine costs and
throughput times are such that processing wafers with
electron beam writing instead of conventional maskingassuming no other technical problems-would raise wafer
processing cost by a factor of 5. This cost increase would
take care of all cost reduction achieved by the smaller
feature size at equal yield. Since the smaller feature
size means more densely built circuits sensitive to much

Electrical Scaling of Devices
In the previous discussion, we have made the implicit
assumption that feature size reduction is equivalent to
circuit area reduction.
This is most certainly not the case. Feature size reduction
will merely define limits to circuit size reduction. The
actual reduction available will be determined by how
closely the electrical device and circuit characteristics
allow us to approach the limits imposed by pattern
definition technology.
1-5

All three presently used major memory technologies
(i.e., MOS dynamic, MOS static and bipolar static) are
more limited by device and circuit design considerations,
rather than optical pattern resolution.

nature of the leakage current. Typically any junction's
leakage current represents a spatial averaging over a
relatively large number of defects. Reducing junction
area will increase fluctuation in number of defect sites
from one storage area to the next. Since dynamic RAM
design imposes requirement that all storage areas have
less than certain pre-determined amount of leakage current, scaling will typically reduce ratio of stored charge
to leakage current. Since the signal available is already
reduced by both scaling and the resulting increase in
density, designers of future generation of dynamic
RAM's face some formidable challenges. It is possible
that the only way they will be able to overcome these
challenges is to impose very strict environmental limitations on the finished product, namely cooling or even
refrigeration of memory systems.

In case of MOS devices, their performance is a function
of the operating voltages and their ability to handle high
operating voltages decreases very rapidly with reduced
device sizes. Consequently, if denser memory circuits
were to be built by taking advantage of feature size
reduction, the operating voltages will have to be reduced.
The resulting device and circuit performance reduction
can be regained by re-engineering the entire device,
reducing oxide thickness, junction depth and increasing
substrate dopi ng to make the device deliver an equivalent
performance at lower operating voltages.

Feature size reduction and electrical scaling will impose
some very stringent demands on process engineering in
terms of both control and the degree of perfection
required for good yields from the scaled structures. We
are assuming that these problems are solvable by evolutionary improvements in processing techniques. We
should not be surprised, however, if progress in those
areas from time to time fails to keep up with the more
visible improvements available from pattern definition
technology.

This total re-engineering of device structure, processing
and manufacturing technology is called "scaling" and it
is obviously a major engineering and manufacturing
task, involving all aspects of wafer technology.
Bipolar memory circuits do not appear to suffer from
this limitation; their's is, however, a different one.
Device sizes can be reduced but their density cannot be
significantly increased, because current drain of a
bipolar device does not scale with size. Consequently,
any attempt to take advantage of reduced device size by
increasing number of bits/chip will run into severe power
dissipation limits. Again the problem is technically
solvable at an expense of major circuit design/process
re-engineering efforts to "current scale" bipolar device/
process technology.

c_ NEW TECHNOLOGIES
Success in semiconductor integrated circuit based random access memory technology prompted considerable
interest in solid state replacements for serial memories.
The two most often considered candidates are Charge
Coupled Devices and Bubble Domain Memory devices.

12 l technology appears technically attractive from this
point of view (i_e., it would be able to take advantage of
feature size reduction with the least amount of device
and/or process engineering changes). Its problem is that
it has so far not been able to establish a sufficiently
attractive price/performance combination to gain a
significant position in the memory market.

Charge Coupled Devices represent the densest silicon

based technology we know. However, their speed and
ease of use is considerably inferior to random access
memories and as long as random access memories can be
made with comparable circuit density, C.C_D. is hard
pressed to carve out a market position. Typically, for a
C.C.D. circuit to be competitive with RAMs, it has to
offer a 4: 1 density advantage over a comparably sized
RAM circuit. So far it has not been able to do it, partly
because RAM technology very quickly adopted all
process improvements made for C.C.D. circuits and
used them to make competitively sized RAMs.

Feature size reduction and the required electrical scaling
of devices will have some very important consequences
in terms of relative impact on various memory technologies. When we scale devices, we adjust some basic device
parameters and operating voltages so as to obtain as
nearly identical device and circuit characteristics as
possible. This can be achieved quite successfully for the
type of circuits whose design is by and large based on
the device characteristics that we have scaled (i.e., MOS
static devices). For these devices, reduction of supply
voltage also brings about a reduction in power dissipation, so one limitation to higher density, characteristic
of static devices has also been removed.

However, C.C.D. technology is expected to establish a
4: 1 density advantage over RAMs in the reasonably near
future because its technology and organization permits:
a. '1proaching the theoretical minimum storage area
of 4 f qoth more easily and more closely than RAMs.
b. Meeting the challenges of featu re size reduction and
device scaling more easily than dynamic RAM's.

MOS dynamic circuits which have traditionally enjoyed
a 4: 1 density advantage over static devices, rely more
on second order effects like leakage currents, subthreshold
conduction and signal to noise ratio in their sense amplifier designs, do not benefit quite as readily from scaling.

Several features of C.C.D. technology contribute to
these advantages. Absence of P-N junctions allows storage and transfer functions to be very similar structurally
and either very closely spaced, or used interchangeably
for both functions.

leakage current, whose relation to stored charge is
vitally important to the successful operation of MOS
dynamic random access memory circuits, does not scale
proportionately with voltage, due the point defect

Although charge is stored dynamically, it is not held at
any location for longer than a clock cycle so effect of
1-6

defect density fluctuation is averaged out over a large
area. Signal strength is comparable to RAM's but there is
more flexibility in sense amplifier design. Absence of
contacts and P-N junctions allows more efficient layout
and easier scaling of devices.

2. Although present bit density is not impressive, it is
based on a relatively simple design with bit area being in
the 200 f2 region for a T bar configuration, indicating
very much room for improvement, some of which has
already been implemented experimentally.

Bubble Memory Technology

3. Because it has only one critical masking step and no
critical alignment requirements, it is the technology best
positioned to take advantage of improvements in pattern
definition techniques.

Although both its device and material technology is
significantly different from silicon integrated circuits,
it is also based on a batch manufacturing process with
the cost of a function very strongly dependent of the
functional density per batch and manufacturing yields.

It is difficult today to determine the point both in time
and in level of complexity at which Bubble Memory
Devices will be able to enter the market and compete
successfully. But once they do, they will enjoy a very
rapid growth comparable to silicon integrated circuit
based memory circuits for exactly the same reasons.

Examined from this point of view, it has some very
major disadvantages coupled with some even greater
potential long-term benefits.
First of all, as a device it is very well suited to serial
storage of data. Although it is slower than any silicon
I.C. based storage circuit, it is non-volatile-or at least it
can be designed to be-and it can also be used to perform
very simple logic functions which allow data to be
stored and retrieved efficiently. Also, it can be used to
pre-amplify the otherwise very small signal magnetically
so it can be used to design a reasonably self-contained
memory chip.

Summarizing these trends, there is sufficient visibility
for the continued technical progress of memory technology at essentially unchanged rates for the next 5 to 8
years.
One word of caution, however, is worth mentioning
here. The key to past success and the continued objective of memory technology development is cost reduction.

Its known major disadvantages are:
1. Very high material cost, caused by both very high
initial substrate cost and a very costly, difficult and low
productivity liquid phase epitaxy deposition process.
Material cost is 30-50 times higher than silicon.

Technical developments to continue to increase density
of memory circuits are worthwhile only if they can
make a significant contribution to this overall objective.
They cannot do it if the cost of improvement is so high
that it swallows up all future cost benefits.

2. Very high packaging cost. Every circuit has to have an
individually adjusted bias field and a rotating magnetic
field built into the package.

Even if their cost is less than potential cost reduction
benefit, they still represent a very significant investment
in design, process development, production and testing
facilities and product start-up costs for the component
manufacturer.

3. A batch density which is presently not significantly
higher than what is achievable with silicon.
Set against these disadvantages we can consider the
potential long-term benefits which motivate the ever
increasing activity in the field:

Such an investment will only be economically attractive
if the market for memory products continues to expand
at a fast rate.

1. Processing typically requires only 3 masking steps,
only one of which is critical, compared to 6+ for silicon.

1-7

National Semiconductor
Memory Systems Division
J.C. Blackie t
November 1977

Static or Dynamic The Selection Process
for a Memory System
INTRODUCTION

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Today's memory system designer is faced with a bewildering number of technology choices for his memory
devices. He is offered overlapping performances from
different technologies, different cell structures, and
different packages. In addition, he is told of new developments daily that will obsolete all of the information he
has already gathered. He is placed in the position where
he must choose a technology, not on today's price, but
on a projected price based on estimated minimum costs
from vendors who are not yet in production with the
devices they are offering.
There are many charts available showing the relationship
between cost per bit, and learning experience, and the
relationship between die size, and cost, on devices
sharing the same learning experience; yet the driving
reasons behind the costs are not always discussed. In
addition, the device costs given do not reflect any additional expense that the user must incur in additional
test costs. This additional testing can require significant
capital expenditure and additional processing cost if
the memory system is to achieve the reliability levels
possible from semiconductor memories.

systems that are cost effective against core modules.
Using a composite of predicted pricing from many
vendors, the lowest cost per bit anticipated in mid-1978
for dynamic memory is 0.06¢/bit for both a 4k x 1 configuration and a 16k x 1 configuration. The lowest cost
per bit anticipated for static devices is 0.15¢/bit for a
lk x 1 configuration or a 4k x 1 configuration. In each
type, pricing per bit of the higher density configurations
are projected to be on a significant downward trend
while the lower densities are flat. Another fact that
emerges is that static devices can be cost effective with
core at low densities, but do not yield the lowest cost
per bit solution in applications that can accept dynamic
devices. Static devices greatest application appears to
lie in areas where:
a. System performance is severely impacted by cycle
stealing for refresh of dynamic memory.
b. Board space limitations do not allow space for additional logic required for dynamic interface
c. Memory requirements are small and can share a board
with other system components.

In an attempt to identify these costs more clearly, this
paper will outline the decision processes and qualification testing to be followed by a design team choosing
devices to be used in a line of standard memory systems
that are to be competitive with existing core systems .

As the system design goal is to replace core systems,
there are many situations where the requirement to
interrupt system usage for refresh cycles is impractical,
thus there is a requirement for static versions of all
modules.

The systems were required to be single-card products
utilizing power available in the user's system. They cover
memory ranges from 16k x 18 to 128k x 18, in increments of 16k. The fact that the systems are to compete
directly with well-established core modules, places a
high emphasis on low cost and reliability. In addition, it
dictates that static memory devices have to be seriously
considered for potential applications where dynamic
memories can not meet existing interface restrictions.
In order to be cost effective with core systems, a volume
selling price goal of 0.3¢/bit for the lowest density system, dropping to 0.18¢/bit at the highest density, was
required. An analysis of the manufacturing costs of a
wide range of sem iconductor memory systems cu rrently
in production provided a set of non·storage cost constants. These constants define price goals for the memory
devices. The systems analyzed had complexities ranging
from cards with transparent error correction and power·
down modes for battery back-up operation, to those
offering high-storage densities with minimal overhead
logic.

Figure 1 shows that even with devices currently in pro·

duction (lk x 1 static and 4k x 1 dynamic) semiconductor memory can be cost effective up to 32k " 18; the
choice becomes marginal at 128k x 18. However, with
the advent of the higher density devices in 1978 (16k x
1 dynamic), semiconductor systems establish a clear
price advantage over the entire range (16k - 128k).
Having established that cost effective devices are availa·
ble, the designer is now faced with the task of choosing
which device and which vendor should be selected. Since
the goal is core replacement, the designer can restrict
his choices to MOS devices that provide access times in
the 150 ns to 200 ns range. These speeds allow him to
provide systems to match or exceed typical core performance, even if a transparent EGG scheme is used to
enhance rei iabil ity.
MEMORY SYSTEM
CAPACITY

Figure 1 shows total non·storage costs in cents per bit

of memory system versus memory system size. Although
this data was compiled from dynamic memories, static
figures were obtained by deducting the cost of all elements whose sale purpose is to support the need to
refresh the system. Using the numbers shown in the
table, one is able to establish maximum prices for
memory devices that allow the design of semiconductor

*TYPIGAL NON-STORAGE
COST TO BUILD/BIT
DYNAMIC
STATIC

16k x 18

O.046¢

32k x 18

0.04¢

0.027¢

64k x 18

0.039¢

0.027¢

128k x 18

0.039¢

0.032¢

*Includes PC board, peripheral circuitry and assembly

**Single card product not available

FIGURE 1

tRefer to Introduction. This paper presented at COMPeON 1977

1·8

Because it is uncertain when the higher density parts
will be available at a lower cost per bit than established
product, careful consideration should be given to a design
approach that will allow a single board to use both high
and low density devices. However, this approach should
only be followed if an analysis of the devices and vendors
shows that the compatible devices offered meet all of
the performance and cost goals. The cost of designing a
card for each type is not great enough to warrant com·
promising performance or reliability with a single card
design. Thus, the designer should feel free to make an
unbiased choice of device for high and low density
products as he starts the device selection phase of his
design.

cost standpoint, because its die may not fit in CERDIP
and a high performance device may suffer degraded performance in plastic.
The fourth factor really concerns the choice of vendor
rather than a specific product or process, but it is a key
consideration from a cost viewpoint. An evaluation of
the component supplier's process control program and
his level of quality and reliability activity is important.
Absence of a meaningful program will affect the level
of yield improvement that can be expected within a
certain time frame, and will raise the cost of administering product through the system designer's facility.
Troublesome vendors with marginal product create
extra costs.

DEVICE SELECTION
Application of the above factors to the devices, in our
case, allowed the device selection to be narrowed down
to a 16k x 1 RAM from 4 viable vendors, and a 4k x 1
static from 4 viable vendors. These 2 parts offered the
lowest potential cost per bit through 1979. This choice
did not take into account the high performance static
product announced at the Solid State Conference in
Philadelphia in February 1977 because that level of
performance was not needed. In addition, the technologies outlined, although very significant in terms of
superior performance at a lower bit cost, will not be
cost effective in lower performance applications in the
near future.

A survey of product available shows several choices of
4k x 1 dynamic configurations, an 8k x 1 dynamic device,
and a couple of 16k x 1 dynamic configurations. In addi·
tion, there are several choices of 4k x 1 static configurations. (In order to reduce the choices to a more manageable number, the designer must compile a list of factors
that will impact the potential cost of a device).
The first and major factor is pressure of competition.
The availability of several qualified vendors committing to volume production ensures a long-lived product
with an industry-wide commitment to maximize yields.
Because volume production commitments from several
vendors is dependent on large users choosing a particular
configuration, a knowledge of who is committing to use
the device tYpes selected, and when, is significant in the

Having chosen the devices and vendors, the designer
must develop a detailed specification for the parts he
needs to procure. This leads him to the next phase of
his device selection.

selection of a device.

The second factor is die size. This is more difficult to
evaluate because the smallest die sizes might be obtained
with special processing technology that has not been
optimized and therefore will take longer to reach an
optimum yield. This would have a serious impact on a
product that must be introduced into an established
market place as soon as possible. It is necessary to weigh
projected die cost by a process learning factor. (Learning
experience on a product typically leads to a 3: 1 improvement in yield over a one-year period of volume production). Thus, the means employed to reach a small die size
is more important than the actual size. A small die
achieved by unique chip design without resorting to
especialiy tight masking tolerances or critical processing
techniques certainly would give a vendor a definite
cost advantage which would be available to a system
designer. The variation in die size offered by the vendors
who scored high on the other factors outlined in this
paper was not significant enough to influence the
potential die cost.

CHARACTERIZATION
The error·free performance of any memory device is a
function of the stability of the memory element and its
ability to function correctly in the presence of electrical
noise and temperature variation. I n order to ensure that

a system design does not exceed the tolerance of the
memory device, a designer must have these limitations
defined so he can structure his design correctly. The
purpose of the characterization phase of the system
design is to define these optimum operating conditions.
Each potential vendor chosen during the device selection
stage submitted a small quantity of his devices for initial evaluation. This evaluation merely allows one to
gain a familiarity with the device and is used as a vehicle
to set up a characterization program. Any potential
problems that would eliminate further consideration are
noted, but this sample cannot be considered as suitable
for final characterization. This device characterization
must be performed on a group of devices comprised of
samples from each speed range offered by the vendor.
Each vendor's composite group is split into 2 groups.
One is scheduled for a lOOO-hour life test and the other
for board characterization. This characterization' and
Iife test evaluation is the first and most critical phase of
any memory system design. It must establish, as much
as possible, each vendor's distribution. This will allow
the designer to optimize his system around the chip
design. Observing parts from the entire distribution
allows him to identify operating region limitations
with temperature, patterns, and voltage levels without

The third factor is the type of package that will be
offered. Several considerations can create package limitations that may not be obvious from the initial evaluation samples which are usually supplied in a hermetic
side-brazed ceramic package which, although expensive,
places the fewest restrictions on the device's performance. The lowest cost product will be one that can be
packaged in CERDIP and plastic. CERDIP can put a
restraint on the die size, and plastic can restrict its
operating speed. Thus, the choice of a high-performance
part with a wide die may be a poor choice from a low1-9

regard to specific data sheets. Potential pattern problems
can often be identified by investigating anomalies in
the device operating regions that are far outside the
range specified in the data sheet using fairly simple test
patterns. Once identified, these same anomalies can
often be seen to move within the specified operating
range when subjected to more complex patterns.

CONCLUSIONS

The rapid development of the semiconductor memory
market has made available a wide range of products, offering potential performance and cost advantages. However, the market place is limited and not all of the devices
offered will reach their cost goals. Thus, the system
designer's task is to first select a device that has wide
acceptance, and has several viable vendors. Device performance must be obtained without resorting to stateof-the'art technologies. He must then accept the fact
that to obtain the optimum cost device it is necessary to
precisely specify the performance needed and he must
assure himself that each vendor's device comfortably
meets that performance. He must accept the fact that he
will be required to perform a significant amount of
device characterization so that his design can be optimized to meet the twin goals of low cost and high
reliability. Finally, his system test plan must be structured to thoroughly exercise all discovered pattern
sensitivities in the basic devices. The choice of static
or dynamic is one of system interfacing and not cost,
and the use of static devices does not eliminate the
need for careful device evaluation.

During the earlier selection phase every vendor supplies
some level of characterization and life test data. Unfor·
tunately in the early stages of new devices, the vendor
has very little to offer. The most meaningful data is
generated by device users and is not available for review.
This is especially true for life test evaluations where it is
very difficult to measure the need for extended burn-in
from vendor's data. Most vendors offer some level of
burn-in as part of their standard process flow, but do
not define the level of infant mortality that might remain in the product shipped. This criteria is very critical
to systems planned for high reliability. Therefore, the
system designer must structure a life test evaluation that
monitors infant mortality as well as long-term shifts in
operating parameters. Infant mortality problems in semiconductor devices are shipping-lot dependent, thus lots
should be continuously sampled for evidence of infant
mortality problems remaining after the vendor's standard
burn-in. This problem can be avoided by providing 100%
extended burn-in, but this is prohibitively expensive for
a low-cost product. An incoming program that required
a sample burn-in of all lots can effectively identify lots
requiring extended burn-in. In addition, it gives valuable
information on the control levels implemented by each
vendor. So armed with the data collected from the
characterization phase the system designer can proceed
to the design of his peripheral logic, and the structuring
of his system. He can weigh the impact of interface logic
design against chip performance and arrive at the most
cost effective and reliable memory system. His system
test plan can be designed to effectively catch marginal
devices that could create field problems, and achieve
the highest levels of reliable operation.

With the advent of the 16k x 1 dynamic device, the
semiconductor industry is moving toward a standard
configuration which will remove a significant amount
of the present confusion of choice. The industry is also
starting to extend the life of MOS products with cost
reductions obtained by optimizing and shrinking existing designs. This will further simplify the designer's
choice, as cell designs and chip structures will remain
the same. However, it appears that the user of memory
devices will still be faced with a need to carefully evaluate the devices he intends to use and perform some
device screening if semiconductor memory systems are
to reach the highest levels of reliability.

1-10

Section 2

Dynamic
Read/Write Memory
Worldwide consumption of dynamic MOS read/write
memory today exceeds that of any other type of semiconductor memory component. This has resulted in
volume costs of devices such as the 4kx 1 at under
50 millicents ($0.0005) per bit. Despite the low cost and
extreme widespread usage, there still exists some
concern and even mistrust regarding dynamic memory
even among professionals_ This is usually reflected in an
effort to "avoid the hassle" at resulting higher costs. If
you have experienced doubts regarding the application
of dynamic RAM to your needs, this section should
prove helpful. It is intended to reduce "problem pollution" and to eliminate the "hassle."

Dynamic RAM Board Design
Made Easy

National Semiconductor
Memory Application
Stephen Calebotta*
November 1977

INTRODUCTION
Many new memory system designs are being done with
dynamic RAMs. This is especially true as the new 16k
RAM chips become more readily available. This applica·
tion note is aimed at those engineers who are doing their
first dynamic RAM designs. Its intent is to give some
direction in how to design a RAM board so that it will
give the greatest production yield with the least amount
of difficulty.

as the static. However, in a large memory system,
dynamic RAMs save total system power since only one
bank of RAMs is ever accessed during a memory cycle.
All other banks draw minimal current except during
refresh cycles. The duty cycle for refresh is approx i·
mately 1 Y, to 3%.
Die Size: Dynamic RAMs te~d 10 be smaller. Due to the
difference in cell designs, the die siie of the dynamic
RAM is often at least 20% smaller than that of a com·
parable static RAM from the same manufacturer.

We shall not talk about specific RAMs or interface to
a specific processor. Most engineers can design control
and interface logic for RAMs and most board designers
can layout a PC board for that design. However, the
quality of that design will become apparent only after
the RAM board is built and phased into production.
Does it come up easily? Does it go through testing
with little or no RAM chip fallout? Is it reliable in the
field?

Price: Because of smaller die sizes and much larger
production runs, dynamic RAMs should always remain
considerably cheaper than comparable static RAMs.
I n addition, dynamic RAMs save money in larger systems.
Less chip power means smalier and cheaper power
supplies. Smaller supplies mean a further saving in
reduced cooling requirements. In general, the larger the
memory system, the greater the savings by using
dynamics.

The key to success in a dynamic RAM system, or any
other system for that matter, is margin. A system
designed to maximize power supply and timing margins
will be reliable and easy to manufacture. One that
doesn't will be a manufacturing and field service night·

WORD LINE

mare.

VDD

In this application note we shall discuss RAM chip
characteristics, power supply and control signal distribu·
tion on PC boards, and control logic implementation
suggestions. As successful examples, in the appendix We
shall provide the schematics and foils for some memory
boards that are in production.
RAM CHIP CHARACTERISTICS

VSs

For reference we shall compare dynamic and static
RAMs at the chip level. Then we shall describe the
unique characteristics of dynamic RAMs which must be
considered in a memory system design.

Static RAM Cell
WORD LINE

,"7-T

Dynamic RAMs versus Static RAMs

~~..,.

The basic difference between dynamic and static RAMs
is the way they store data. The static RAM uses a flip·
flop to store a bit, while the dynamic RAM uses a
capacitor to store a bit. (See figure 1.1
It is their respective cell designs that give each RAM its
advantages over the other. Let's compare the RAMs for
ease of use, power dissipation, die size, and price.

Dynamic RAM Cell
Figure 1.

Dynamic RAMs

Ease of Use: The static RAM is easier to use because no
refresh logic is required. In addition, static RAM control
signals tend to be easier to generate because cycling is
usually unnecessary.

Refresh: Since charge leaks off the storage capacitors, it
must be replenished periodically in order for a dynamic

RAM chip to retain its data. The charge in anyone cell
is replenished, or refreshed, every time that ceil is
accessed for a read or a write, At the same time, all the
other cells in the same row are also refreshed. For that
reason the entire RAM chip can be refreshed by doing
only 64 cycles (for 4k RAM; a 16k RAM needs 128

Power Dissipation: The dynamic RAM draws less power.
The static RAM draws power continuously to sustain
its flip·flops, while the dynamic RAM draws minimal
power (1 to 2 mAl between cycles. With continuous
cycling, the dynamic RAM draws about as much power
*Refer to Introduction.

--=

DATA

2·1

cycles) in 2 ms while sequencing through all the row
addresses. The bit pattern presented to the column
addresses does not matter. However, the setup and hold
times must still be met. Unstable column addresses
during refresh will cause data loss.

We will discuss only VDD since the other supplies have
similar characteristics. Figure 2 shows the I DO current
waveform for a typical dynamic RAM chip during a
memory cycle.

The hardware required for refresh amounts to a 6or 7-bit counter for the refre,h addresses, some way
to multiplex the counter onto the RAM row address
lines, a timer to signal when a refresh should be done,
and the miscellaneous gating needed to couple into the
usual read/write logic.

CHIP
ENABLE

l00mA

100

In some systems no extra refresh logic is needed. For
example, in CRT systems normal operation sequences
through all the row addresses in less than a 2 ms refresh
period. This will be true only if the row address bits on
the RAM chip are driven from the least significant
address bits of the system. As a rule, this is good practice
in all systems. By placing the most active system address
bits on the RAM row add resses, normal system
operation will automatically refresh the bulk of the
RAM.

o
1\
I

\_____7

nr
L - Z- 4mA

0--1

Figure 2.

At the beginning and end of chip enable, each RAM chip
draws 50 to 100 mA current spikes with rise times of
20 ns. In addition, each RAM package draws a 20 to
40 mA DC current lasting for the duration of chip
enable. The power distribution system must supply these
currents while the voltages at the RAMs remain constant.
Figure 3 is a schematic of the VDD supply for a row of
eight RAMs. The inductors are due to PC trace inductance which is about 10 nH per inch for a 13 mil trace.
If the RAMs are on Y2-inch centers there is 10 n!-l total
between RAMs.

Cycling: One of the key functional differences between
static and dynamic RAMs is the fact that dynamic RAMs
must run through a cycle in order to read or write.
Aborting the cycle by removing the chip enable too
early or- by trying to start a second cycle too soon after
the first will probably cause data loss. Minimum chip
enable on and off times must be observed.
Summary
Static RAMs are easier to use. Dynamic RAMs are
cheaper, use less power, must be refreshed, and must be
cycled.
MEMORY SUBSYSTEM DESIGN CONSIDERATIONS

Figure 3.

Some memory board designs are easy to manufacture,
while others, functionally identical, have low manufacturing yields seemingly due to the many "bad" chips.
The difference between them is usually the amount of
margin designed into each system. Power supply and
timing margins are both critical, and as the margins go
to zero or negative, the amount of "soft" errors goes up.
(A chip has a "hard" error if a location consistently
cannot be written and read back properly. It has a
"soft" error if it only occasionally fails.)

If there is only one capacitor per row, and if that row
capacitor, Crow, were infinite, the voltage spikes at the
first, second, and last RAMs would be:
.
di
100mA
Vl spike = Lx8-= 10nHx8x--dt
20ns
= 400mV
V2 spike = Lx 15':!.! = 750mV
dt

On careful analysis, "soft" errors usually occur during
a memory cycle in which some system parameter has
gone out of spec. Since the RAM chips themselves have
variations in their margins, replacing the offending RAM
with one that has a greater margin in the out-of-spec
parameter seems to cure the problem. This results in a
large pile of "bad" RAMs. However, the real solution
to this type of problem is in a careful system design and
boarj layout in the beginning.

V8 spike = L x

36~

= 1800mV

These spikes, especially the last two, are unacceptable.
If each RAM had its own decoupling capacitor, CRAM,
in series with 10 nH of trace inductance, the voltage
spikes would be:

Power Distribution

di
100mA
Vspike = L- = 10nH x - - - = 50mV
dt
20ns

By far the single most important aspect of a successful
RAM system is good power distribution consisting of
carefully designed decoupling and power gridding. The
importanc.e of good power distribution cannot be overemphasized.

which is very good. Local decoupling should be used
to overcome the spiking problem.
The ability of the power distribution system to supply
the 20 to 40 mA per chip during a RAM cycle is also a
function of the series inductance. For example, see
figure 4.

Let's examine the problem. All dynamic RAMs have at
least two supplies (VDD and VBB; VSS is the RAM
internal ground). Most also have a third called VCC.
2-2

For bulk decoupling, solid tantalum capacitors are
recommended. They have better transient response than
most other large value capacitors and they put a lot of
capacitance into a small package which simplifies board
layout.
A word about power gridding. If there are a number of
rows of RAMs, all power supply traces to all RAMs
should be run both vertically and horizontally through·
out the array. Providing multiple paths through the array
reduces the effective inductance of the power distribu·
tion system.

Figure 4.

To summarize power distribution, we can say the
following:

Let the total power supply lead inductance be 50 nH.
(We are ignoring the PC trace inductance within the
RAM array itself.) What would the voltage step have to
be at the RAMs to get 40 mA x 8 flowing in 20 ns?
The equation is:
E=

1. It is the single most important aspect of a good RAM
boa rd layout.
2. Use plenty of decoupling. The decoupling caps not
only reduce voltage spikes, but also provide most of
the RAM power during the cycling. Layout the
board for a 0.1 f.1F capacitor per power supply per
RAM chip (up to three capacitors per chip). As
production history accumulates, it may be possible
to omit half the capacitors. However, layout the
board for one per supply per chip. Use 50 to 200 f.1F
of bulk decoupling on +12V. On +5V and -5V use
25 to 100f.1F.

L~ = 50nH x 8x 40mA= 800mV
dt

20 ns

which is a large step which should not occur with
adequately designed decoupling. Therefore, the bulk of
the DC current for cycling the RAMs comes from de·
coupling caps themselves, and therefore they should be
large enough to supply these currents with little droop.
They should also be close enough to the RAMs to minimize the effect of the spikes. If we use a 0.1 f.1F cap,
the droop for a 250 ns cycle would be:

3. The decoupling capacitors should have the shortest
possible traces back to their respective RAM power
supply and ground pins. To reduce inductance
further, these traces should be as wide as room will
allow.

I
40mA
Vdroop = V = - t = - - x 250ns = 100mV
C
0.1 f.1F

4. Traces running the power supply voltages throughout
the array should be as wide as possible. However,
with good decoupling design, even minimum trace
widths will probably be acceptable. If some power
supply traces can be wider than others, make VSS
(Ground) wider first, VDD next, VBB next. and
finally VCC. Ground is the key. Grid the supplies
even if the traces are heavy in one direction and light
in the other.

which is acceptable. Obviously, a larger capacitor will do
an even better job of handling the droop. In addition, to
help keep the droop to a minimum, the board should
have about 50 to 200f.1F of bulk decoupling on the
+12 V supply. The other supplies can have less. Half
should be placed near the point where the supplies enter
the board. The other half should be placed at the far side
of the RAMs so that the array lies between the bulk
decoupling capacitors.

5. We have purposely omitted any discussion of multilayer boards. They tend to simplify power distribution problems, but the types of problems that must
be solved are the same. Only the magnitudes have
been somewhat reduced. Almost everything that has
been said up to now is still applicable to multilayer
boards.

Alternatively, half of the bulk capacitors can be spread
throughout the array. If this is done, use approximately
5 to lOf.1F per eight RAM chips for VDD and VBB.
For VCC, 5 to 10f.1F for 32 chips should be adequate.
Intuitively, this second approach seems better. However,
the first technique works fine and is probably more cost
effective.

Data and Control Signal Distribution

The choice of capacitor types is very important. In all
of the above decoupling calculations we have ignored the
effective series resistance (ESR) of the capacitors. The
effect of the ESR of real capacitors is probably at least
as large as the effect of PC trace inductance and is a
function of the capacitor type.

The second most important aspect of the successful
RAM system is address, data, and control signal distribution.
Let's discuss the chip enables first. This is the most
important signal to the RAM and all timing is referenced
to it. There are two types of chip enables in common use
today: 12 volt and TTL level swings. Running chip
enable lines through an array tends to be less of a
problem than one would think. There are only two
things to keep in mind. First, place the actual driver
chip near the RAM array it is driving, making the chip
enable run short and direct. Second, put a damping
resistor near the driver. Do this for either TTL level or
12 volt chip enables. Select the value of this resistor to

For best results, use ceramic capacitors for the local
decoupling. The Memory Systems Group at National
Sem iconductor has had good results with ceramic
capacitors of Z5U material from A VX and Sprague.
To illustrate how important the Memory Systems Group
feels these capacitors are to good memory board performance, every lot is subjected to an incoming inspection
which includes, among other things, a transient response
test.
2-3

enable will help some in reducing crosstalk. However,
as stated earlier, there seem to be very few problems
associated with chip enable. Neither CE itself nor
crosstalk to other signals will be troublesome if the
above guidelines are observed.
DRIVER

Address, data, and control signals such as read/write (or
equivalent) should be run as directly as possible. Their
layouts tend to be non·critical. The critical thing is
timing. The control logic should be designed to maxi·
mize setup and hold times with respect to chip enable.
Again, high production yield is related to margins. As
an example, consider a RAM board that was built for an
8080 system. The chip used was MM5271 4k RAM
which has a low true TTL level clock input. The signal
that controls read, write, and refresh is called TSP.
The MM5271 data sheet says that the setup time for TSP
is zero ns with respect to the leading edge of chip
enable. When doing a refresh, TSP must be low at the
beginning of chip enable. The original timing brought
TSP down at the same time as chip enable. The system
seemed to work. However, it would make an error once
every half hour or so. With an oscilloscope everyth ing
appeared to be within specification. When TSP and chip
enable were superimposed on the scope, their leading
edges were absolutely coincident in both time and
waveshape. The TSP/chip enable relationship was
examined very, very carefully and pronounced okay.
Finally, in an attempt to cure the problem, the TSP
timing was changed to give about 50 ns of setup time
and the problem disappeared.

Figure 5.

give the best clock waveform at the RAM chips. Its
value will probably be between 10 and 51.11. Figure 5
shows the commonly used arrangements.
The reasons for these two recommendations stem from
the fact that, at the frequencies encountered here,
the clock lines are, in fact, transmission lines. The
impedance of the line is determined by:

The point was that the original design was done to the
limit of the memory data sheet even though there was
no need to do so. The success of the operation depended
on the shape of the two waveforms to keep the system
in spec. Once margin was designed in, with no hardship
at all in the design, the system operated flawlessly.

where the impedance of the clock line within the array
of chips is in the range of 10 to 15 n while the unloaded
line between the clock driver and the chip array is in the
range of 30 to 50.11.

In high·speed systems where it is hard to design in extra
margin, use damping resistors in address, data, and
control lines to help control their waveshapes. A resistor
in every address, data, and control line allows these
waveforms to be optim ized, wh ich gives the system
improved margin over an undamped design. Use damping
resistors only where necessary. Leave them out of signals
that have time to settle down before they are needed.

In order to drive the clock line cleanly, some attempt
must be made to match the clock driver's output imped·
ance to that of the line. The actual output impedance of
most monolithic clock drivers varies as much as 3 to 1
and so we choose a fast clock driver with low output
impedance and put a damping resistor in series to
empirically set the effective output impedance to match
the line (with only about 10% variation).

Summarizing the use of damping resistors: always put
them in chip enable lines, whether they are TTL levels
or 12 V levels. Use them as necessary in those address,
data, and control lines whose timings are approaching
the limits of the RAM chip data sheet. Design in margin
first. Tune it in when it can't be designed in.

Long clock lines or long lengths of unloaded clock lines
can cause problems. In the case of the long clock line,
the open circuit at the far end of the line causes the
reflection from the end of the line to return to the
driver after the end of the rise time, resulting in ringing.
In the case of the long unloaded length of line, the
reflection from the junction of the unloaded and loaded
sections of the line (due to the mismatch) causes glitches
in the clock transitions.

LOGIC CONSIDERATIONS

These also affect yield. For example, a RAM cycle
must never be aborted before its normal completion.
The control logic must be designed to never permit a
shortened cycle. At this point we shall briefly discuss
some techniques for timing and control.

To minimize crosstalk from chip enable to other signals,
try to run chip enable at 90° to other signals. This is
usually hard to do in an actual layout. As an alternative,
leave as much room as possible between chip enable and
adjacent traces as it runs through the array. Typically,
signals in the array are on 50 mil centers. Moving the two
adjacent signals more than 50 mils away from chip

Timing Generation
The actual phasing of control signals can be done a
number of ways. Existing system level control signals
can be used. This is easy in some 8080 and PACE
systems. When the available system control signals
aren't quite up to the job, another technique that works
2-4

quite well is to use a high frequency oscillator and a
shift register connected as a Johnson counter. Any
tim ing signal that is necessary can be generated from a
Johnson counter using a 2 input gate. This technique
has a minor drawback if the high frequency oscillator
is asynchronous with respect to the main system timing.
The RAM cycle timing will always have a finite uncer·
tainty with respect to the system cycle timing. This
uncertainty is equal to the clock period of the high
frequency oscillator. To apply the same technique but
to avoid the timing uncertainty, use a gated delay line
oscillator instead of a crystal or RC oscillator. Delay
line oscillators can be started and stopped reliably.
Crystal and RC oscillators take a few cycles to settle
down and therefore are not reliable in a start·stop
mode. How about one·shots? Do not, under any circum·
stances, use one-shots in critical timing applications!

be low true. The reason for th is is that, as control transfers from the CPU to the DMA device and back again,
there will be short periods of time when the control
lines are floating since neither device is driving the lines.
In a TTL system, floating lines look high. If control
signals have been defined as high true, then as the lines
momentarily float, devices such as our RAM board will
think that a command has been issued and will start an
unintended cycle. Then the problem gets compounded.
During the unintended cycle comes the command for
a real cycle. Either the unintended cycle will be aborted,
which destroys some RAM contents, or the intended
cycle will start too late, causing other problems in the
external system. An example of a bus with this problem
is the S100, or hobby standard bus. It mixes signal
polarities and, therefore, makes dynamic RAM control
logic unnecessarily complex. If there is only one can·
trolling device, signal polarities are academic. But if
control can transfer, make the control lines low true.

Refresh Timeouts
A counter and oscillator are best. An astable oscillator
is acceptable but must be carefully designed for worst
case minimum frequency with respect to temperature
to ensure the RAM gets refreshed often enough. At the
end of the timeout a flip·flop should be set. When the
refresh cycle is finally completed, that flip-flop should
be reset. The timing should be such that it doesn't
matter when the RAM gets refreshed within the refresh
timer period.

SUMMARY
Refresh requirements make dynamic RAMs slightly
harder to use than static RAMs. However, they pay the
designer back for his efforts by reducing overall system
cost in three ways. First, dynamic RAMs tend to be
cheaper than static RAMs of the same size. This is
primarily due to smaller chip sizes and higher production volumes than comparable static RAMs. Second,
dynamic RAMs use less power. When a dynamic RAM is
not being accessed it draws much less cu rrent than a
static RAM. During access, dynamic and static RAMs
draw similar amounts of power. However, in a large
array, only that bank being accessed draws full power.
All others sti!1 draw standby currents so that the total
system power is lower than for a comparable static
system. Because of the reduced power requirements,
power supplies are cheaper. And, third, due to lower
power dissipation, cooling requirements are reduced,
allowing a further saving.

Transparent versus Non-Transparent Refresh
Most microprocessors have predictable periods of time
when they will not access the RAM board. Usually it
takes little effort to insert refresh cycles in these times,
thereby making refresh transparent to the CPU. When
the CPU is very fast and is using the bus almost continuously, the refresh will have to hold up the processor.
Even then, some clever design will minimize the time
spent doing non·transparent refresh.
Single Step

There are three things the system designer can do to
maximize RAM board yields during manufacture. First,
design proper power supply d~coupling. This is probably
the single most important consideration for the designer.
A good high frequency 0.1 fJ-F capacitor per supply per
memory chip is recommended. A capacitor per supply
per two chips is probably okay, but the board should be
laid out for one capacitor per supply per chip and then
capacitors can be left out as yield data becomes available.
For bulk decoupling use about 50 to 200fJ-F per board
on +12V, less on +5V and -5V.

Some systems need the capability of single stepping
through programs. Since dynamic RAMs must be
refreshed continuously, the output data from RAM
should be latched. This permits single stepping because
every time the address changes, the RAM is read and the
data is latched. Then the refresh proceeds behind the
latches, never disturbing the data. The RAM appears
static.

DMA
DMA should be little different from normal cycles.
One thing that must be considered is how to handle
refresh. Three techniques immediately come to mind.
First, have the DMAing device permit refresh period·
ically. Second, limit the DMA frequency. Make the
period between DMA cycles equal to a normal RAM
cycle plus a refresh cycle. This way the refresh can be
handled transparently to the DMA. The third technique
would be to limit the DMA time to something under
2 ms and at the end of the DMA do a burst refresh of
the entire memory. There are a number of other ways
to handle refresh and DMA. Performance of the system
will determine which technique is most appropriate.

Second, design in as much margin as possible in all
control signal timing. Use damping resistors where
necessary. If timing is designed right to the minimum
specs, periodically the right combination of data pattern,
power supply noise, temperature, cosmic radiation, etc.,
causes the system to fail. The combined worst case
parameters push a signal beyond specification and the
memory fai Is.
Third, never allow spurious, shortened memory cycles to
occur. Shortened or aborted memory cycles are guaran·
teed to destroy data in the row that was addressed
during the aborted cycle.

From a system standpoint, the most important aspect
of DMA and dynamic RAMs is the polarity of the
system level control signals. In a TTL system where
bus control can change hands, the control signals must

Any designer who uses reasonable Care can successfully
design dynamic memory systems which will be easy to
manufacture and very reliable in the field.

2-5

APPENDIX A
Appendix A shows a simplified timing diagram and schematics for a 16kx8 RAM board used by a PACE microprocessor
for byte mode data storage.
RAMs are MM5270 4k RAMs with 12 V chip enables. All timing is generated from existing system signals. DMA is not
now in use, but is possible in the future. Control signals from the bus are low true. Refresh is transparent, done at any
time in the absence of any address, data in, or data out strobes, coincident with the rising edge of clock.
PACE 110 CYCLE

NClK
AOOR/DATA

!WRITE!
(READ)

NEXT lIO CYCLE

A....~
I
.-------' I
:~
V-.
~ I D:Itl~N I f;\-

BAOS-

ADDR VALID

DATA OUT VALID

>Jr,

r------,

TSP TO RAMs _-iIr-_!_R.,FS_H_:___R.,ONl_R_L::;::::.:
CETI] RAM!

RFSH

L _____ -'

IL:.::.:..:....J
WRITE I

j'--r---o'

11~~~fs~RCE::

t OCCUR HERE

G~~

. . . §~~~~~~FIl~g

'OD~; C>--j--~i>-..:;;;==.,

'""

BlOt C>--j--~i>o--===h

GN4~
8CLK39

C>--j--~i>~-="-+i--'

- UtiLESSOTHERWISESPECIHED1. ALL RESISTANCES ARE IN OHMS;
tAl'ACITANCES ARE IN PICOFARADS.
Z. At.LIC.HAVEPIN7ATG.ROUNDANDI'IN14

:~~:T

14lS28J.J4lSI57. OS30015.14LS109. 14J93,
0&3&71,08]649 _I'INBATGNQPIN '&AT

EX~~~T:
0S3673 -PIN I ATGNII. PIN

'4AT+~V.

EX~:;"~ AND aAT +12V,
MM52JD, PIN 1 AT -5V. PIN 14 AT +12V, AND

PIN1IATGND.
l. JLlMPEATABlE

151-1.

:UH~W2MUST B~ INSTALLED, BUT NOT

Figure 6. Control Logic, 16 x 8 R/W Memory Board

2-6

2-7

APPENDIX B

in Appendix B we show the printed circuit board layout for a 16kx 16 RAM board which uses MM5270 18-pin 4k
RAMs. It is an excellent example of the proper way to grid and decouple the power supplies on a two-sided board. Also
shown are the centrally located chip enable drivers with their series damping resistors.

2-8

A Memory Design for
an 8080A-Based
Microprocessor System

National Semiconductor
Memory Application
T. Landgraf*
November 1977

INTRODUCTION
This technical note describes a memory design for a
system which can provide up to 64 kilobytes of R/W
memory in 16k-byte increments. Provision is made for
further address decoding (up to a megabyte). Multiple
refresh modes are described, along with handshake
signals to and from the CPU. Power supply estimates and
parts count are included to allow the reader to get an
idea of his own system requirements. Circuit diagrams
are also provided.

Data Bus Elements: A pair of quad TRI-STATE® MaS
memory I/O registers (DS3647) latch the OOUT outputs
from the RAMs for read operations and drive the DIN
lines for write operations. They also drive the data bus
of the system. The 3647s have TRI-STATE outputs and
are inverting in both directions. Control of the 3647s
comes from the sequencer. The 3647s are fast (20 ns on
memory reads, 15 ns on memory writes), medium power
(95 mAl, and can source -5.2 mA at 2.4 VOUT and sink
30 mA at 0.4 VOUT when driving the bus. When receivingfrom the bus, 3647s source 100J-lA and sink -500J-lA.
Fqr 16-bit wide memory systems, one card supplies the
lower data byte. A second RAM card handles the upper
data byte by jumpering the data lines to edge pins
DATA8/through DATAF/.

THEORY OF OPERATION
The design of the memory system can be studied by
several blocks in detail. The blocks are identified as
follows: (a) the four 16·kilobyte memory banks, the
RAM address multiplexer, and the data latch-bus driver/
receiver, (b) the timing sequencer section, and (c) the
address decoding.

Timing Sequencer
The timing sequencer provides all the appropriate signals
for the memory banks for system read/write cycles,
refresh cycles to maintain data, and acknowledge handshake signals to bus masters.

Memory Banks, Address Multiplexer,
and Data Bus Element
Memory Banks: There are four memory banks of 16
kilobytes each, made up of eight MM5290 16k-by-1
dynamic memories. The dynamic RAMs require 14
address bits to address any unique location. These
addresses are multiplexed over 7 address pins during
memory access. Two strobe inputs on the RAMs indicate
which 7 bits are on the internal data bus - the 7 row
addresses or 7 column addresses. The strobes are Row
Address Strobe (RAS) and Column Address Strobe
(CAS). A third control input is the write enable signal,
WE. There are two data lines: DIN for input and DOUT
for output. In this system they are tied together for
common I/O, since gating of CAS and WE determines
whether data is latched in on 0 IN or will appear at
DOUT. Finally, a ground and three supplies (+12, +5,
-5) occupy the other 4 pins.

An 8224 clock generator supplies a 45.2 ns period clock
pulse to drive the sequencer. The 45.2 ns clock, ClK, is
divided by 2 by a OM74lS74 flip-flop, which drives two
OM74lS161A 4-bit counters. One counter divides ClK
by 16 to produce a clock with a 13.02J-1s period and
814 ns width. This is the on-card distributed refresh
request clock, used to refresh a new row of the memory
every 13J-1s. The other DM74lS161A driven by ClK+2
is used fOr the 8 cycles of refresh required immediately
after system power-up. Actually, 9 cycles of refresh are
performed. The first one is used to get the sequencer out
of any illegal ~tates. When this counter counts up to
"1111," the carry output goes high, is inverted, and
stops the counter by making Ep (parallel enable) low,
inhibiting furth'er counts. During the power-up burst
refresh, bus master memory accesses are blocked until
the burst refresh is finished.

To provide bank selection within the memory array, 4
different CAS signals are provided, to give effective chip
selects.

The sequencer itself is comprised of a pair of J-K flipflops (OM74S112) and a quad 0 flip-flop (DM74S175)'
which form a 14-state ring counter. When START
CYCLE (J input to first OM74S112) goes high, ones are
clocked through the sequencer in 45.2 ns intervals. The
DM74S175 is wired in shift register fashion (01 to 02,
02 to 03, etc.) to propagate the timing pulses. When
T4 goes high (OM74S175 03), the K input of the first
DM74S112 goes high. On the next rising edge of ClK,
this will cause the sequencer to begin shifting in Os
(count down) until all outputs are 0, at which point the
cycle is over. During refresh cycles, the sequencer counts
for 450 ns (495 ns max - one clock period uncertainty).

Address Multiplexer: The addresses to the memory array
are selected by the 3242 multiplexer. The 3242 allows
the row address (ADR 0 through AOR 6), the column
address (ADR 7 through ADR 0), or the refresh row
address (output of a 7·bit counter internal to the 3242)
to be placed on the RAM address bus. The 3242 select
controls are derived from the sequencer outputs. In
addition, the 3242 has an input to increment its internal
refresh row counter. 33 n series resistors in the address
(WE and CAS) lines serve to limit undershoot on the
heavy capacitance lines. This is because MaS RAMs
cannot withstand inputs less than -1 volt.
*Refer to Introduction

2-9

However, during system memory cycles, the sequencer
begins to count down Os immediately after T4 goes high
because DT4 (delayed T4) NANDed with RAMREQ
(system cycle. request) clears the first DM74S112. This
allows us to spec memory cycle times of 405 ns (450 ns
max).

clocked on the rlsmg edge of memory read MR DS/
indicates the 8080 is decoding the current instruction
and it will not use the bus for approximately 500 ns
to 600 ns. The memory card will then use this time to
perform a refresh of its RAM and will be ready for the
next bus master memory request. The impact is to
eliminate refresh entirely from the picture and the
memory will appear static - no refresh delays at all.
In the case of bus masters without this Ml output
(e.g., DMA cards) the memory still can be r~freshed by
its on-card requestor circuit.

Outputs of the sequencer drive the CAS/, WE!, CASO!
through CAS3/, BUSY /, and acknowledge circuitry.
Acknowledge Circuitry
Advanced acknowledge AACK/ is produced by clocking
REF! (high during non-refresh cycles) on a selected edge
of the sequencer (Tl for default). A Iowan RAM R EQ!
brings the AACK/ gate out of TRI-STATE.

As mentioned before, two cards can be paired together
to produce a 16-bit wide data word memory. The signal
MACK/ (memory acknowledge) is used to synchronize
the XACK/ (transfer acknowledge) signals between the
two cards. To synchronize the refresh of the two cards,
three signals are used and brought out to the P2 connector. Through these signals the master card supplies the
power-up refresh and distributed refresh to both cards,
ensuring a minimum number of wait states to a bus
master's request.

XACK, Transfer Acknowledge, is the result of REF!
clocked on the T4! rising edge (the end of T4). It is also
gated with AACK to ensure .AACK has occurred. To
synchronize a pair of memory cards for a 16-bit wide
memory word, MACK! (Memory Acknowledge) is used.
The master card sends out MAC K/ on the bus to the
slave card which uses MACK/ to enable its TRI-STATE
XACK/ gate. The slave card is the only card of the pair
to send out XACK!. (The bus master does not test for
MACK/.)

Address Decoding
Address bits ADRF! and ADRE/ are decoded by a
DM74S139 2-to-4 decoder and the four outputs are
supplied to four wire wrap pin matrices_ The matrices
assign a base address on 16k boundaries (0000, 4000,
8000, COOO) to the CASt of each of the four 16k
memory banks. (For smaller memory cards, the number
of matrices is reduced to the number of memory banks
installed; e.g., for 48k, or 3 banks, matrices for banks
1, 2, and 3 would be installed.)

Request Arbitration Circuitry
This section, consisting of two D flip-flops (DM74S74)
and several gates, handles the different cycle requests
(bus master, power-up burst refresh, hidden refresh, or
1311S distributed refresh) and starts the sequencer in its
cycles. The circuit handles the five cases of requests and
decides which requests will be honored and which will
be queued until the system is ready for a new cycle.
However, at power-up, 9 cycles of refresh are performed
in rapid succession (approximately once overy 812 ns)
and no bus master requests will be accepted. The total
power-up burst refresh time is approximately 9 x 812 +
450 ns, or 7. 7611S.

To assign a base address to the bank, the user installs
a jumper at the bank and address desired.
The OR of the bank selection is fed to a 4-input NAND
gate with the RAM-inhibit signal INH1!, the OR of the
memory commands MRDS! and MWTC!, and a signal
from the optional megabyte decoder. This NAND
output is called RAM R EQ/ and generates Board Write
and Board Read with the memory commands. RAMREQ/
is also inverted and applied to the memory cycle request
arbitration circuit described earlier.

Another feature of this memory card is to provide true
hidden refresh with the INS8080A system. Provisions
have been made to indicate M1 cycles of the CPU
machine cycles on an auxiliary connector pin. Ml

Table I. Memory Request Arbitration Conditions

Request

Cu rrent Cycle

Action

Bus Master Cycle

None

Begin Bus Master Cycle

Bus Master Cycle

Refresh

Complete Refresh Cycle, then begin Bus Master Cycle

Refresh Cycle

None

Begin Refresh Cycle

Refresh Cycle

Bus Master Cycle

Complete Bus Master Cycle, then begin Refresh Cycle

Refresh Cycle and
Bus Master Cycle

None

Accept Bus Master Cycle, begin Refresh Cycle after
Bus Master Cycle goes to completion
Table III. Parts Count

Table II. Power Supply Requirements (estimate)

Card Size

ICC (+5)

IBB (-5)

100 (+12)

Card Size

Memory Chips

Support

Total

64k RAM

1.5A

0.0064 A

0.94A

64k

48k RAM

0.82A

0.0048 A

0.73A

48k

32k RAM

0.74A

0.0032 A

0_51 A

32k

16k RAM

0_66A

0.0016A

0.29A

16k

2-10

Megabyte Decoder
This circuit decodes four more address bits - ADR 13/
through ADR 10/ - via an 8-bit data selector. These
address bits are derived from the Pl spares Imain
connector) and the P2 (auxiliary connector). This
decoder output is true if the lower 3 bits (10 through 12)
match the switch array (one switch is opened) and if the
highest bit (131 or its complement causes the DM74LS151

STROBE to go low. The decoder output goes to the
RAMREQ/ gate.
Parts Count and Power Supply Requirements
The parts count (estimated) is shown in table III. Power
supply requirements are shown in table II.

PRELIMINARY SPECIFICATIONS - 64k-BYTE MEMORY CARD

DC Specifications
Signal

ADRO/-ADRF/,
MWTC/, MRDC/,
ADR10/-ADR13/
AACK/, XACK/

MACK/
W17 B-D

MACK/
W17 A-C

INH1/

Min

Conditions

Parameter

DATAO/-DATA7/

VIN(l)
VIN(O)
IINIl)
IINIO)
VOUTll)
VOUT(O)
IOUT(l)
IOUT(O)

I nput Voltage Logic 1
Input Voltage Logic 0
Input Current Logic 1
Input Current Logic 0
Output Voltage Logic 1
Output Voltage Logic 0
Output Current Logic 1
Output Cu rrent Logic 0

VIN(l)
VIN(O)
IINIl)
IINIO)

Input
Input
Input
Input

VOUT(l)
VOUTIO)
IOUTll)
IOUTIO)

Output
Output
Output
Output

VINll)
VIN(O)
IINIl)
IINIO)

I nput
I nput
I nput
Input

VOUT(1)
VOUT(O)
IOUT(l)
IOUTIO)

Output
Output
Output
Output

VIN(l)
VINIO)
IINll)
IINIO)

Input Voltage Logic 1
I nput Voltage Logic 0
Output Voltage Logic 1
Output Volgage Logic 0

Voltage
Voltage
Current
Current

Logic
Logic
Logic
Logic

Voltage
Voltage
Current
Current

1
0
1
0

Logic
Logic
Logic
Logic

Voltage
Voltage
Cu rrent
Cu rrent

0.8
100
-500
VCC
VCC
VCC
VCC

=
=
=
=

5V
4.5V
5V
4.5V

IOUTll) = -5.2 mA
IOUTIO) = 30 mA
VOUT(1) = 3.0V
VOUT(O) = 0.4 V

1
0
1
0

Vcc=max
VCC = max

VINlll=2.7V
VIN(oI = 0.5V

Vcc=min
VCC= min

IOUT(1I=-5.2mA
IOUTIO) = 16mA

VCC = min

VOUT(OI = 0.4 V

1
0
1
0

VCC = max
VCC = max

VIN( 11 = 2.4 V
VIN(O) = 0.4 V

Vcc=min
VCC = min
VCC = min
VCC = min

IOUT(1)=-400pA
IOUT(OI = 8 mA
VOUTll) = 2.7V
VOUT(OI = 0.5V

Vee = 5.5V VIN(l) = 2.7V*
Vce = 5.5V VIN(O) = 0.5V·

I_'AS

I~'CO~I

TRI-STATE

0-7/ 0

C:!l

1-· 4!

1_...
\.
I_IRH~I

MR~C~ I ~

'NVAL" DATA

VAUD DATA

, -----'---; 1-'"
\

~ TRISTATE"

1'IW!:ffjff

ADAO/-tS/ 0 ~~_ _ _ _ _S_TA_8_LE_AD_D_RE_SS_ _ _ _ _ _

T"'TATE ®

TRI-STATE ®

TRl-STATE®

1-_---_.·. . _-_.,,_'----..\ :'~~~:(r
JJ
I-I----"TR=I-ST=ATE"-®I
1

AACK/ : _ _ _

XACK!

WRITE

D~!~

0.8
50

-2
2.4
0.4
-5.2
16

-----"=""--

-'C'-I
f---'DH~I
I--------wr---------'-----,>
/\
STABLE DATA

0 _ _ _ _ _ _- '

Bus Characteristics (AC)

2-11

0.8
40

-1.6
2.7

!RI'STATE®

Units

V
V
pA
pA
V

V
mA
mA

V
V
pA
mA

V
V
mA
mA

V
V
pA
mA
V

0.5
-400
8

pA
mA

0.8
50
-2.58

V
V
pA
I1A

2.0

*includes 10k pull-up

READ DATA

0.4
-5.2
30

Timing Waveforms

-I

3.0

-2.0

1
0
1
0

Logic
Logic
Logic
Logic

Max

2.0

AC Specifications

Parameter
tAS

(refer to figure 1)

Min

Max

(ns)

Description

Remarks

Address Setup to Command

tAH

Address Hold from Command

tCH

Command Hold from XACK/
375

Command to Read Data Access Time

565

Read Cycle Time

210

Command to AACK/

for W18 B-H

280

440

Command to XACK/

forW17 A-B

tco
tRCY, tWCY
t80
tACK

455

tCI

Command to Write Data Setup Time
Write Data Hold Time from Command

tDH

tAKH

t80H

tRD

550

tRH

End of Command to Data Buffers go
Hi-Z

tA80

AACK/ Off Time from Bus Ack

Timing Wavefonns

OSC

End of Command to Hi-Z on XACK/
End of Command to Hi-Z on AACK/
Refresh Delay Time

Since Refresh is asynchronous, tRD may
be added to tco, tRCY, tAAK, tACK-

(Continued)

~n,_
•.21

•

REFREOI : .

START·1~

CYCLE 0

T1
12

TJ
TO

,
,
,
,
,
,
0

(

I
I

ROWEN
0

,
,
,

CAS!

I
11

AAS!

,
BUSyl

I
I
I

I·

I
I

REFRESH DELAY TIME

Sequence of Events. Refresh Cycle

2-12

I
I

·1

Timing Wavefonns

(Continued)

osc
;~~

MRDe! OR

MWTC/

______________________________________-J;--

:---f/l////////!II/;;

START
CYCLE

TO
Tl
T2

13
T4

L--

~------------------------~,--

BUSYI

RAS!

CASn!

WRITE DATA
WRITTEN INTO

,...,RAMsHERE

WE/WRITE
CYCLE ONt Y

LATCHi
READ CYClE
LATCH/ 1

WAITE CYCLE 0 - - 1

______~========~------~I
'--___

AACK/

XACKI

_ -_ _ _·_ _ _ _ _ CYClETIME _ _ _ _ __

Sequence of Events. Read or Write Cycle

ADRO/

7 BITS

BUFFERS

I-~---I~ DAiAD/
BANK1

8ANK2

BANKJ

BANK4

/1o-+......p--I~

ADRD!

DATA7/
DATABI

J LINES •

_ _ _ _ _. . .~-----. .

---------.--1

OATAF/

f:
-::: : : :;~_~_-~ _-~ _-~ _-~ _-_~_~ :J:"._'_______~~~~~~~1-..,1---r-J---:::-::=-------.·~ ii~;~\~ ~ NTROl
AORE/

AORF/

ADR101

---------+-1

ADDRESS

10 LINES

DECODER

MROcl-------------------'
MWTC/

Mll------------------------'

Block Diagram

2-13

I-----------_~

AACKI

I------------~

XACKI

REF!

__________________________________________________________,

T2 ~------------------~.~~E~-----------------------------'
DefAULT JUMPER STRAPPING
FOR64k

ADDRESS

1YJ

74S04

7 COOO

68000

BANK
4

C~I

CASJI

5 4000

40000

BANK

CAS21

CAS1/

:~~~~

---------------------::::=---,

c::::>--....

>-------_..

6-------------.
.-11>,0.;---_

RAMREW
RAMREW

WRITE!

C:::;:..........__ot:>-....,-Ibo-o-~!!!.~...JL----~~2!MWT!rL'-_+::~~r..,:-t'"----- BOARD WRITE
L _______.1-.-!M!!R!!!D'!..I.......:::~l"5r--------

+5 - - - -....._ H _........,

0.8 XXXX
1,9 XXXX ....~--""1I--'++-J-I4+-I

t--II;-.----+++-H-+-I
-II;-.----....+-'H-+~
4,C XXXX t--II;-.-----...H-+-I
5,D XXX X +--II,.-------......~4~
6,E xxx X t--II,.---------4-+-I
7" XXXX +--II,......._________...

2,A XXXX

3,8 XXXX ....

A~r_'~
EXTERNAL ADRI21

A~r:~6

7eLS1"

r-::>.........-----o[>--I

c:::::>-----

> eLK
CIA

C:::>,","...---.q>~

c:::::>----r;<:-'...:----<1>--t_~--J
~~~
ffi
ADR1Di c:::::>-----

EXTERNAL ADRI!I

ADRIOI

EXTERNAL

8XXXX-FXXXX

A~r::a
EXTERNAL ADRI31

e>--- ...-oII>....D*c::>-----

OXXXX-1XXXX

Memory Select logic

2-14

BOARD READ

IIII

r.~~!;'..

+-----t:

•
~ ~I"

.a: ...... O .... eA

2-15

'"."AIA,.,,,'o'"l!,""o_

,,,"
.'I".Q"~""
""I".~"nT1 ""_A".e" ...
0;',.,011"." """""UCK'"

~::::;::::

,:~r.--

':;:~IJ'~~
.:

t:,
-1""'-'[-tI-;;----..-,"_III------1H

" ~

.. ..

""",,,'"'' '"' "'"'' '"''''''''''''''''

--~

~~~

Memory Array

2-16

National Semiconductor
B. Johnston

MM5290 16K RAM
Functional Description

INTRODUCTION
This functional description covers the operation of the
MM5290 16k dynamic RAM currently manufactured
by National Semiconductor. This device is directly
interchangeable with the MK4116. The National design
has some internal differences, but these are transparent
to the user, making the MM5290 a direct replacement
for the MK4116.

column lines. Noise margin is improved because column
line length is minimized.
Clock Generation
The MM5290 has multiplexed addressing necessitating
separate row (Row Address Strobe, RAS) and column
(Column Address Strobe, CAS) strobes. The timing
relationship between these two strobes is made noncritical by gating CAS with the internal RAS clock. This
is shown in Figure " along with the fact that CAS gates
the write enable (WE) control. These three signals are the
source of the internal clocks (row, column and write
clocks). Another way to describe this is: 1} the row
clocks are referenced to RAS; 2} the column clocks are
referenced to either RAS or CAS, depending on the
RAS to CAS delay; and 3} the write clocks are referenced
to CAS or WE, depending on which occurs later. The
block diagram in Figure 1 indicates which blocks of
circuitry the internal clocks control.

Block Diagram
The block diagram shown in Figure 1 shows the func·
tional relationship between major blocks of circuitry in
the MM5290. The multiplexed address, unlatched
output and gated CAS featu res are shown. The row
decoder column decoders and two 64 x 128 memory
arrays with sense amplifiers between them are drawn in
blocks that indicate their actual physical relationship on
the die. This arrangement, with sense amplifiers in the
middle and column decoders duplicated along each side,
reduces cross talk (coupled noise) between address and

FIGURE 1. MM5290 Block Diagram

2-17

Memory Cell
The basic memory cell consists of a transistor and
capacitor as shown in Figure 2. Data is stored by
selecting a cell and charging or discharging the storage
capacitor Cs through transistor 01. 01 is then turned
OFF (cell deselected) and data is retained until charge
is lost through leakage current or the cell is refreshed.
Each memory cell must be refreshed every 2 ms to
guarantee data retention.

umns. The row and column coincidence selects an
individual cell for either reading or writing data.
Read Operation
Figure 4 shows a simplified version of the array of cells

with the read/write circuitry. The array consists of
16,384 memory cells plus 2 rows of 128 reference cells.
These are separated into 2 arrays by 128 sense amplifiers
as shown. If row address AX5 is a logic "0", a row in the
top half of the memory is being selected while the
reference cells on the other side of the sense amplifier
are also selected. Data is stored in complementary form
in this half (top) of the array. The other half (bottom)
of the array stores the data in true form when row
address AX5 is a logic" 1". A logic "0" in the array is
defined as OV stored in the cell and a logic "1" as +V.

COLUMN

CST
Voo

Although the usual time reference in a cycle of opera·
tion is the high·to·low transition of RAS, the prior
events of discharging all row lines (to OV) and precharging
all column lines (to VDD) must occur before a cycle of
operation can be successfully completed. The starting
point then is all row lines discharged and all column
lines precharged. Then a row address is latched and the
128 cells connected to the selected row line are "read"
by the 128 sense amplifiers. This also refreshes them.
When a column address is latched, 1 of the 128 columns
is connected to the I/O bus and the data of the selected
cell becomes available on the DO pin.

FIGURE 2. Basic Memory Cell
Cell Selection
Figure 3 shows a block diagram indicating how an

individual memory cell is selected (addressed). First,
the row address is latched in by RAS. This is decoded
to select 1 out of the 128 raws. Actually, there are 128
cells tied to each row so that 128 cell transistors (01 in
Figure 3) are turned ON. Second, the column address is
latched in. This is decoded to select 1 of the 128 col-

T7liaus

CAS
ROWClOGKS

COLUMN
DECODERS
1:128

(128)

A2
A3

A'
AO
AS

=----oj
1Z8X 128

Cell MATRIX

1/0 BUS

FIGURE 3. Block Diagram of Cell Selection

FIGURE 4. Simplified Read·Write Circuitry

2-18

Sense Amplifier Operation
Figure 5 shows a simplified version of a sense amplifier

the reference cell labeled 1/2 Cs and CCl. (All reference
cells begin the cycle with a "0" stored on the storage
capacitor.) This means that the sense amplifier will have
a voltage difference of±1/2 AV across it with the polarity
depending on the data stored in the memory cell. The
sense amplifier regeneratively amplifies the difference
and restores the data in the memory cell. This signal is
also amplified by the output buffer and made available
at the output pin (DO).

together with a selected memory cell and the reference
cell associated with "reading" the cell. When the cell is
selected by the row address. a reference cell on the
opposite side of the differential sense amplifier is also
selected. (In fact. the entire row of 128 reference cells
is selected.) If the selected memory cell contains a "1 ",
then the storage capacitor Cs has the same potential
as the left column line and no charge is transferred
through 01. If the selected cell contains a "0", then
charge will be transferred through 01 and shared
between Cs and CCl. The voltage of the column line
will be reduced by tJ. V where AV is a function of the
ratio of Cs to CCl.

Write Operation
Figure 6 shows a block diagram of the write circuitry.

The Data In buffer drives the column line of the selected
cell either low (to ground) or high (to VOO) depending
on the logic level of 01. Transistor 01 is ON because
the cell has been selected and the storage capacitor Cs
is written to the voltage of the column Iine. Then 01 is
turned OFF and Cs retains the data.

Simultaneously with the events happening with the
memory cell and the left column line, the right column
line will always be reduced by 1/2 AV because charge
wi II be transferred th rough 02 between the capacitor of

LEFT
COLUMN
LINE

1
1

II
1

VDD

IL.. MEMORY
CELL ..JI
____

BUFFER

r----'
•.. - tRCD max)?

Are all address set-up and hold times within spec?
tAS Rand tRAH for the row address?

tASC and tCAH (CAS limited timing) } f
th
I
dd)
or tAR (RAS limited timing)
or e co umn a ress.

Are the WE set-up and hold times within spec?

tRCS and tRCH for a read cycle?
tRWL and tCWL
tWCH (CAS limited timing)
or tWCR (RAS limited timing)

for a write cycle?

twcs for an early-write cycle?
tCWD (CAS limited timing)
}
or tRWD (RAS limited timing)

10.

for a read-write or a
read-modify-write cycle")

Are the DI set-up and hold times within spec?
tDS and tDH relative to later of CAS or WE
}
or tDHR relative to RAS for RAS limited timing.

2-25

MM5290 Bit Map
and Address Decoding

I NTRODUCTI ON

Disturb testing requires a detailed knowledge of the
topology and address decoding of a dynamic RAM.
The MM5290 has its own unique topology and address
decoding which is described in this write-up.

Terminology is listed for those of us who may be can·
fused by vertical rows, horizontal columns, bit lines,
word lines, etc., so that definitions are clear. The terms
"row" and "column" will be used from now on in this
paper. X and Y address counter definitions are shown
also. Note that even though the data out is not inverted
from a user's point of view, the data is stored in complementary form in the left cell array.

Figure 1 shows the MM5290 cell array diagram. It is
oriented with a top view, as if a die were in a dual·inline package, with pin 1 in the upper left hand corner.
In this orientation the row decoders are across the
bottom and the column decoders are along the sides.
(Actually the column decoders are duplicated on each
side.)

Figure 2 ,haws the address decoding. This is shown with
the cells indicated in a regular array. This is not the case
and the actual topology will be discussed later. The
assumptions are:

1. This is the same orientation as in figure 1.

2. One chooses the lower left hand corner of the array
as the starting reference.

DATA

~TORED

DATA flORED

a:
i4:

COMPLEMENT

3. The row address counter is the faster of the two
address counters providing the binary addresses.

TRUE

4. The leads are translated on the test fixture as shown

L._ : _.J
~

(ROWS)
(WORD LINES)

(METAL)

(GATES)

in figure 3.
5. The cells may be numbered in decimal from 0 to
16,383 and the numbers of the cell correspond to the
binary format as shown in figure 4.
Based on these assumptions, figure 2 shows the position
of the cells addressed by stepping through the binary
addresses in sequence, rows fast. Several cells are
numbered in figure 2 to indicate the sequence. Another
way to show the address decoder translation is shown
in figure 5. The row address counter counts 4 left to
right (arrow a); then during the next 4 counts the

(X) - (FASTEST ADDRESS COUNTER IN TEST SYSTEM)

Figure 1. MM5290 Cell Array Diagram

COLUMNS
(V)

I
I
I
I

I
I
I
I
I

0
0
0
0
0

I
I
I

1
0

•
0
0
0
0

1
I
I

•

0
0
0
0
I
I
I
I

CELL
I
I

0
I

I
0
0
I
1

0
0
0
0

0
0
0

0
0
0
0

0
0

I
I
0
0

15.872--

•
1
0

""z

1024---

I
0
I

••• ••• • •• •• •
•
• •• •
0
0
0
0
0

i 11

• ••

1
0
1

AO
AS
AI
ROWS A,
(X)
A3

512-

,•

255254 253 252
123127126125124

lCELLO
0
0
0
•
0

A4 •
A,

128129130131
0 I 2 3 7

I
0
0
0
0
0
0

•

• •
•
•• • • :-•
•
1
0

I
I

0
0

1
I

1
0
0
0
0

1
1
0

I
0

0
0

I
0
0
0
0

0-0
0--

0 __

--I

1
1 1
1

--a

r--- 1I
c--

Figure 2. MM5290 Bit Map and Address Decoding

2-26

I
I

1 I
I

0
I
I
I
I
I
I

•
,
I
I

I
1

0
0
I
I
1
I
1

reading adjacent cells in rows would require reading ±5
rows from the row of interest. Similarly, a column can
have diagonally adjacent cells 2 column addresses away
so that it requires ±2 columns to assure addressing all
physically adjacent cells.

physical connections make it address cells from right to
left (arrow b). This left·to·right, right·to·left sequence
(in groups of 4) is repeated for 128 rows. The column
address counters count in normal sequence starting with
o at the bottom and up through 127 at the top. If the
column address counter increments once for each 128
row count, then all cells of the array are addressed as
follows: Column 0 is addressed (in the 4 left·to·right,
then 4 right·to·left sequence), then column 1 and on to
column 127, where the number of the column corre·
sponds to the decimal equivalent of the binary column
address.

Further analysis indicates that the diffused column lines
electrically isolate the cells between them from the rest
of the array. Also, one of the adjacent cells (on the left
or right) is always connected to the row line of the cell
being investigated. This adjacent cell cannot be exercised
without refreshing the cell of interest and all other cells
in that row. The most practical and efficient disturb
testing would exercise only the adjacent cell (on the left
or right) not connected to the row line of the cell of
interest and the two diffused column lines that isolate
the cell in question from the rest of the array.

Now that we can "follow the map" to any cell location,
there is one more step to determine which cells are
physically adjacent (as opposed to having sequential or
"adjacent" address). Figure 6 shows a simplified sketch
of the topology of the MM5290. The orientation
(vertical rows, horizontal columns and lower left corner
reference) is the same as in the other figures. The decimal
numbering of the rows and columns, corresponding to
figure 5, are shown. The shaded lines are metal rows.
The clear lines are diffused column lines.

SUMMARY

The purist will exercise all 8 physically adjacent cells.
A pragmatist will exercise the one adjacent cell not
connected to the same row and the diffused column
lines which isolate the cell. The efficient pragmatist will
not use sequential binary addressing to exercise only one
cell and two column lines when doing a disturb test on
a cell.

Examining the sequencing of the rows shows that rows 3
and 6, 4 and 9, etc., have physically adjacent cells. A test
program using sequential binary addressing to assure
SYSTEM
CLOCK

COLUMN

ROW_

(MSB)

CELL NO.

lSB

(LSB)

AS A4 AJ A2 A1 A6 Ao

0
0

AS A4 A] A2 Al A6 AO

0
D

0
0

··
·

LSB

512

16,383

0
0

0
1

··
·

·
·

TO
5290

CLOCK . - - - - - '

0
0

Figure 4. MM5290 Address Coding

MSB

~
~

Figure 3. Test System Address Counters Showing X Counter as
the "Fastest" Changing Address Counter

!t
:i

i-=;~I-----+---~~---+-----r~~---i
-.
~ ~----;~b

CHlO.( 0

9 10 11 15 14 13 12

DECIMAL COUNT - ROWS

Figure 5. Addressing Bit Location

2·27

METAL ROW

-lL

OIFFUSED COLUMN

ROWS (DECIMAL EQUIVALENT OF ROW ADDRESS)

Figure 6. Simplified Topology (lower left corner of array)

2-28

MM5290 RAM
Test Description

INTRODUCTION
National Semiconductor's 16k dynamic RAM is done
with sophisticated computer controlled RAM test
systems.

proper device operation is achieved. Any 8 cycles which
perform refresh are sufficient.
No input signal (including transients) can be more negative than VSS by 0.5V. This can forward bias the substrate and may cause damage to the device. This should
be especially considered in burn-in ovens in which signals
may not be well controlled.

This test description covers the general flow of the
MM5290 done to insure a high quality product.
Wafer sort and quality assurance programs generally
follow the descri bed parametric and pattern testing and
these are not included.

Capacitive decoupling at the test fixture should maintain
the peak-to-peak transients on VDD, V8S and VCC lines
at equal to or less than 400 mVas measured between the

The following points are important to successful testing
of the MM5290.

appropriate voltage pin and ground pin on the device
under test (not open socket or the backside of the fixture).

The following VBB rule should be observed to prevent
possible damage to a unit under test:

This MM5290 final test description is in a preliminary
form. It indicates the flow, the burn-in and the basic
intent. It will be several months before the testing of
this complex RAM is firmly established. The patterns,
correlated limits and timing are all subject to shifts to
guarantee a quality part. Notice also that no page mode
testing is shown. This will probably only be done if the
customer requires it. National currently has test capability in place on the Teradyne J387 test system.

a. Power-up: VBB must be brought up prior to any
power supply or input signal.
b. Power-down: V BS must be maintained until all other
supplies and inputs have been brought to zero.
Several cycles are required after power-up or after the
maximum refresh period has been exceeded before

2-29

16k RAM BURN-IN

Burn-In Timing

PERIOD T

TI2

1\
I

T/4

V
-T/8--

\
I--

BDns
MIN

I-- 10 ns MIN-

AD-A&

COLUMN
ADORESSES

DATA
IN

2.8 IlS ~ Poriod T

V
ROW
ADDRESSES

HIGH FOR 1&,384 CYCLES, LOW FOR 1&,384 CYCLES

5.6 IlS

Note 1: Input timing points: VIH =2.2V, VIL =O.SV.
Note 2: Address lines: TR::; 250 ns, TF::; 250 ns.
Noto 3: RAS, CAS, WE: TR::; 150 ns, TF::; 150 ns.

Burn-In Connection Diagram
Dual-In-Line Package
1&

VIa

lIB

Pin Names

m
RAS
CAS
WE
AO-AS

DO
A&

DO
VDD
VCC
VSS

Vss

VBB

Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Data Input
Data Output
Power (12V)
Power (5V)
Ground
Power (-5V)

VCC

VDD

TOP VIEW

13.8V - - . - - - - - - - - PINI

GND

--+---.....1----- PINg
--...---+---- PIN 1&
",D.l.F*

-5.7IV

------.....
+----

PIN 1

*0.1 IlF capacitors between 5V and GND, -5V and GND alternate every other
socket in each column, 0.1 IlF capacitors between 12V and GND every socket.

2-30

OUTPUT LOADING

VOH

I.D6V

VREF
1.31V

110

DATA OUT

0-...._""".,.,........- - .
110

100pF

VOL
O.86V

ISOURCE

ISINK

2.4 -1.31

= ~ = 4.95 rnA

1.31 -0.40
220

= 4.14 rnA

BYPASS CAPACITANCE

On Handler Backplate

VBB

-.l
T
Vss

0.1 pFd

VDD

Vee

-.l

-.l
T

VSS

Vss

TO.1PFd

On Siemens Handler Teeth

VDD

-.l
T
Vss

2·31

o.1PF

0.1 pFd

GENERAL TEST FLOW

ASSEMBLY

ADL 0.40

r
QA ATZ5°C

LTPo 5

BOX STOCK

FINAL TEST FLOW
FROM DYNAMIC BURN·IN

+
SHORTS

-3 TIMING

r
-2 REFRESH

MM5290·2

-3 REFRESH

MM5290·3

2-32

-4 TIMING

~
MM5290-4

Trouble Shooting Check List For
Memory Systems Using the
MM5280

Is CE rise time greater than 10 ns and less than 40 ns?
Is this true at all points on the board?

D
D

Does CE meet the min-max VIHC and VI LC spec including ringing at all points on the
board?

Are the CE on and off time specs being observed?

Are the bypass capacitors big enough and close enough so that the power supply
variation plus the peak-to-peak noise on the supplies does not exceed the ±S%
specifications?

Do all TTL level signals reach their respective VIH and VI L levels before CE reaches 2V?

Is the output loaded properly?
No more than one TTL load and no more than SO pF. Is the VCC bypassed properly?

D
D

Is the memory being refreshed properly?
Are all rows (AO through AS) being refreshed every 2 ms?

D
D

Are address setup and hold time specs being observed (including CS)?

Are address setup and hold times being observed during refresh, including column
addresses and CS?

Is timing of output data strobe meeting access time spec? Is it being strobed at a time
when noise from other signals is at a minimum?

11.

Is WE input at VI H level for entire read cycle?

12.

Is minimum WE width (twp) spec being observed?

13.

Are the write timing specs (tcw and tWI) with respect to CE being observed?

10.

14.

Is the DIN stable early enough before the end of CE in order to meet the tD spec
(1 SO ns)?

lS.

Does the data on DIN remain stable until CE has reached 2V at the end of CE?

16.

Are the clock drivers bypassed with high frequency capacitors close to the clock driver
package?

Do the clock drivers have damping resistors? Are they large enough value for the lower
CE capacitance of the MMS280?

18.

Are the clock lines short to reduce ringing?

19.

Are the clock drivers close to the memory array to avoid the impedance mismatch
between loaded and unloaded lines?

Are data input and output lines running perpendicular to clock lines or at least far away
to minimize coupling?

Is part being conditioned (refreshed) after power-up?

17.

20.

21.

2-33

Section 3

Static
ReadIWrite Memory
The growth in usage of static RAMs, particularly lk, and
more recently 4k, has been phenomenal. Primary factors
in this growth are low cost, ease of use, TTL signal and
power supply compatibility, standard DIP packaging,
and multiple sourcing. National supplies a broad line of
MOS and bipolar static RAMs for the spectrum of
today's applications. This section is intended to assist
you in matching industry standard static RAMs to your
particular needs.

Static

RAM Applications

Figure 1 illustrates the ease of designing a static RAM
support memory for a microprocessor, in this case the
IS-bit I NS8900. Full buffering has been included to a
system bus which carries common input/output data and
address. Operation may be from a 5·volt power supply
or on·board regulation may be used. Oecoupling should
follow the same practices as used for TTL boards.

Figures 2 and 3 depict possible configurations for power
down of the MM5257, while figure 4 shows allowable
input conditions. These power down techniques apply
to others of National's static RAM family including the
MM2114, MM2101A, MM2102A, MM2111A, and
MM2112A series.

%DMl41SOZ

NADS

(ADDRESS

DATA
STROBE)

,....,

-=
~
-=

iffiI

."
f=

~RDSEl

Tlr->-

DUT

T21--

TJ~

OM8131

n8.'
T4

WIRE

l~::~fs

DM.W5

r ••

CONNECT
ADDRESS

6TR

ADDRESS

lUAU
MUSh

LATCH

;::::

=
~

DM8IS15

ill.

r ••

STR

I" -"
AQ-An

AQ·A11
_&251
01

....::::
~

."'D4

J-~
c

DD a

aWE

oC~

'--

II
II

ONE DATA

UIETO

EACH MM5Z51

RAM ARRAY -1& ..,.62671

DilDO

I--

T/R
DATA BUFFER
CD

D"'D4

-~l--'

~~fllH T~5251

DI.DD

1--.

riii
IDS

IREAD
STROlE)
D••

IWRITE
STROBE)

1:Ll::r
~

~_\/CC

~
~

.....

)-_.
"IUI. CE.
DN"""'"

,.c[*.

~
. ;[]~cc
~

...--

)I"'"
~s

Figure 1. Example Application of MM5257 4kx 1 Static RAM: 4kx 16 Memory Card for 16·Bit Microp,oc.sor System

3-1

VIN 1-35V

POPERATINGMAX "II: VIN x 60mAJPKG
PSTANDBY'" VIN x 20mA/PKG

Figure 2. 4k Static Power Down 1

1-...-4--1. TO MM5251 Yee

L.._ _ _ _ _ _ _ _ _ _ _ _ _

POPERATING MAX

~ YIN

TOMM5251CE

x 60mAIPKG

PSTANDBY '" 3V JI. 20mA/PKG

Figure 3. 4k Static Power Down 2

v e e - - - - -...

~:~~-------:~:
I.: ::1
<

,.,,2.0Y

~----------------------.cp·D
'R' READ CYCLE TIME

Figure 4. 4k Static Power Down Mode

3-2

Interfacing Static R/W
Memories to the 8080A

Addressing Techniques
The INS8080A has a 16-bit address bus that is capable
of addressing up to 65k bytes of memory and up to 256
input and 256 output devices_ In small systems with
minimum memory and input/output requirements,
buffering of the A15-AO Address Bus may not be
required. However, as memory and input/output device
requirements increase, buffering is required for the bus.
This address buffering function can be implemented by
using two National Semiconductor DM81LS95 TRISTATE Octal Buffers as shown in figure 1. Note that the
system Bus Enable (BUSEN) signal is connected to the
buffers so that they are forced into their high-impedance
state during a DMA data transfer (BUSEN = logic 1) or
any other time that bus access is desired, thereby allowing other devices to gain access of the address bus. As
mentioned above, up to 65k bytes of memory and up to
256 input and 256 output devices can be directly
addressed via the A15-AO Address Bus of the INS8080A.
The INS8080A microcomputer system can be configured
so that memory and input/output devices are either
treated separately (isolated input/output) or as a single
memory array (memory mapped input/output) as
described below. The mapping for the isolated input/
output and memory mapped input/output addressing
techniques is shown in figure 2. With both of these

~
Al

A3
A4

AS
A6
A7

A9
Al0
All
A12
A13
A14
A15

When the INS80BOA system is configured for isolated
input/output addressing, the memory address space is
separated from the Input/output device's address space
by using system control signals for the input/output
architecture as· shown in figure 3. Also, with isolated
input/output addressing, the input/output devices
communicate only with the Accumulator using the IN
and OUT Instructions. Thus, since the memory address
space is not affected by input/output device addressing,
the full address space of 65k bytes is available for
memory.

DM81LS95

AO
Al
A2
A3

INS8080A
MICROPROCESSOR
A8

addressing techniques, the most common method of
addressing memory or input/output devices is to decode
some of the address bus bits as "chip selects" (using a
device such as the National Semiconductor 74LS138) to
enable the addressed memory or the input/output device.
The linear select method is another way of addressing
the input/output devices using either of the addressing
techniques. In linear select, a singular address bus bit is
assigned as the exclusive enable for a specified input/
output device. Using this method limits the number of
input/output devices that can be addressed but eliminates
the need for extra decoders. In small system design this
is an important consideration.

1+
BUSEN

SYSTEM
ADDRESS
BUS

BuSeiii

DMB1LS95

G2
J19

Figure 1. Address Buffor Design Using DM81 LS95 Devices

3-3

A8
A9
Al0
All
A12
Al3
Al4
Al5

~t-4
~f=---------J

256
INPUT/OUTPUT
DEVICES
ADDRESS SPACE

A. ISOLATED INPUT/OUTPUT

32K

65K
INPUT/OUTPUT
DEVICES
ADDRESS SPACE

MEMORY
ADDRESS SPACE

B. MEMORY MAPPED INPUT/OUTPUT

Figure 2. Mapping for Isolated Input/Output and Memory Mapped Input/Output Techniques

OP8228/0P8238
SYSTEM CONTROLLER
lOR EQUIVALENT
DISCRETE

COMPONENT
LOGIC!

MEMW kr~------------~

VOR

}

~~MORY
ARRAY

kr~25~__________~~} TO

I/OW ~~27~___________ ~

.....- - - - - - '

INPUT/OUTPUT
DEVICES

Figure 3. System Control Signals for Isolated Input/Output Addressing

OP8228/0P8238
SYSTEM CONTROLLER
lOR EQUIVALENT
DISCRETE COMPONENT

LOGIC!
MEM R

MEMW ~--------~--+---------------------------------~~

}

NOT
USED

I/ORIMM!

} ~~MORY
ARRAY

} ;~PUT/

OUTPUT

0-,W",I:..cM"M:c:!__. .
1o..-"1/.c:

Figure 4. System Control Signals for Memory Mapped Input/Output Addressing

3-4

DE VICES

When the INS8080A system is configured for memory
mapped input/output addressing, an area of the memory
array is assigned to the input/output devices by using
system control signals for the input/output architecture
as shown in figure 4. In this configuration, new input/
output control signals [I/O R (MM) and I/O W (MM)]
are generated by gating the MEM Rand MEM W signals
with most significant address bit A15. (Since these new
input/output signals connect in exactly the same manner
as the corresponding signals of the isolated input/output
configuration, the system bus characteristics are unaltered.) Address bit A15 is used because it allows up to
32k bytes of memory addressing, and because it is easier
to control with software. However, any other address
bit may be used for this gating function. When bit A15
is low, the memory address space is active and when bit
A 15 is high, the input/output device's address space is
active.

These devices are still considered addressed "PORTS"
but instead of the Accumulator being the only data
transfer medium for the peripherals, any of the internal
registers of the INS8080A can also be used for this
purpose. Thus, memory mapped input/output addressing
is suited for small systems that require high throughput
and have less than 32k bytes of memory.
Memory Interfacing
The CPU group of the N8080 microcomputer family
interfaces with standard semiconductor memory components (and input/output devices) via a 3-bus architecture that includes an 8-bit bidirectional External Data
Bus, a 6-bit Control Bus, and a 16-bit Address Bus. A
typical interface to a memory array having 8k bytes of
ROM storage and 512 bytes of RAM storage is shown in
figure 5. This typical memory interface is suitable for
almost any size of memory array. However, in larger
systems, buffers may be required for driving the three
buses and decoders may be required for generating the
chip select signals for the memory array (and input/
output devices).

With memory mapped input/output addressing, all of
the instructions that can be used to manipulate memory
locations (for example, MOV M, r; LDA; STA; LHLD;
et cetera) can also be used for the input/output devices.

MEMORY MAPPING

~-----.o

ROM
ADDRESS
SPACE

---------------- 8KBYTES
RAM
ADDRESS
SPACE

......_ _ _ _ _... BK + 512 BYTES
ROMs

RAMs

;2
MM2111-2

RIW 00

ii
II

9
MEMW

FROM
cPU

GROUP

I/O 1-4

AO-A7

]

MEMR

1-3
;1
MM2111-2

R/W 00

I/O '·4

AO-A7

]

9 9
AO-A7

MEMWj

AO-A7

j MEMR

I
I

f:~
~11.
A12

I
I

Figure 5. Typical Memory Interface

3-5

1-4

MM2316

CSI

01·08

AO·Al0

0
jMEMR

AO-AlO

I
I

DATA BUS 181

CONTROL BUS (6)

I
ADDRESS BUS (16)

The memory array of figure 5 includes ROMs (MM2316)
and RAMs (MM211l-2) that have an access time of 850
nanoseconds (maximum)_ When the INS8080A microprocessor is operated from a clock generator with a
tCY of 500 nanoseconds, the requfred memory access
time is from 450 to 550 nanoseconds_ Therefore, to use
the slower memory components in the system, the
INS8080A microprocessor must contain a synchronization provision to allow the memory components to
request the wait state (tW)- (The actual number of tw
states to be inserted is determined by external logic that
is user designed_) This provision can be implemented for
any slow memory (RAM or ROM) by a simple logic
control of the READY input of the INS8080A as
follows_ When the addressed slower memory receives a
MEM R or MEM W signal, it places a low-level on the
READY line of the microprocessor, causing the
INS8080A to enter the WAIT sequence_ After the slower
memory has had time to respond, it places a high-level
on the READY line, thereby allowing completion of the
instruction cycle_

As shown in figure 5, the interlacing to the National
Semiconductor MM23l6 static ROMs is quite straightforward_ The DO-D7 output lines of the ROMs are
connected to the bidirectional External Data Bus; the
AO-A1O address inputs are connected to corresponding
bits of the Address Bus; the CS2 and CS3 chip select
inputs are connected to the All and Al2 bits (most
significant) of the Address Bus; and the CSl chip select
input of the ROMs is connected to the MEM R signal of
the Control Bus_ During a FETCH or MEMORY READ
machine cycle, the CPU group may output an address in
the ROM address space of the memory array_ When this
occurs, the data stored at the addressed ROM location
are then gated onto the External Data Bus with a lowlevel MEM R signal. In this way, data are read from the
ROMs in the INS8080A.
The interfacing to the four National Semiconductor
MM2l11-2 static RAMs is also straightforward_ The
1/01 -1/04 common input/output lines of the RAMs
are connected to corresponding bits of the bidirectional
Data Bus; the AO-A7 address bits are connected to corresponding bits of the Address Bus; and the RIW and OD
inputs of the RAMs are connected to the MEM Wand
MEM R (or DBIN) signals, respectively, of the Control
Bus_ During a FETCH, MEMORY READ, or STACK
READ machine cycle, the CPU group reads data from
the RAMs in exactly the same manner as descri bed
above for the ROMs_ During a MEMORY WRITE or
STACK WRITE machine cycle, the CPU group outputs
an address in the RAM address space of the memory
array_ When this occurs, the data to be written into
memory are then strobed into the addressed RAM
location with a low-level MEM W signal_ In these ways,
data are read from and written into RAMs in the
I NS8080A microcomputer system_

3-6

Interfacing the 6800
Microprocessor to National
CMOS MM74C910 Memory

National Semiconductor
Bill Kopek*
October 1977

INTRODUCTION

CONCLUSION

The applications of solid state non-volatile memory are
numerous. One such application involves an Area Navigation System used on aircraft. Waypoint information
can be conveniently stored upon engine shutdown and
becomes readily available at power-up. This is especially
useful for cross-country flying so that the same waypoint data does not have to be entered into the Area
Navigation System at each aircraft takeoff.

National CMOS RAMs are competitive in solid·state
non-volatile memory applications. Projections for
battery life of 10 years have been made using lithium
batteries with average current drains of 1O!lA.
One other approach using MOS technology for Electrically Alterable ROMs can be competitive in larger
systems, although the Read Cycle of approximately
20 ms and the Write Cycle of approximately 60 ms are
prohibitively long compared to those of CMOS RAMs.

6800 AND MM14C910 INTERFACE
A 6800 is utili~ed in the Area Navigation System for
processing and computations. Figure 1 shows a block
diagram of the system which includes 2k x 8 ROM and
64x4 RAM.
Non·volatile memory for way point storage is obtained
by usage of the MM74C910. This device is a 64-word
by 4-bit RAM consisting of six address lines, four data
input lines, four data output lines, a Write Enable (WE)
and a Memory Enable (ME). Typical supply current for
the device is 0.05 !lAo
Interface of the 6800 and MM74C910 is accomplished
via the DS8T28 8us Transceiver. However, additional
hardware and software are required to extend the data
time on the bus to read and write 4-bit data. (Two
MM74C910 CMOS RAMs organized by 8·bit words
would simplify software.)
Figure 2 shows the clock circuit hardware required to
extend the data time during Write. Clock phase 2 is
extended from 500 ns to 550 ns by increasing the time
constant of the Monostable generator. The output is
passed through one NAND and two INVERTER circuits
to the Data 8us Enable input of the microprocessor.
A data extension of approximately three gate delays is
thereby accomplished, allowing Data Input Hold Time
tHO (min) of 30 ns to be met before WE from the 6800
goes high. When the MM74C910 is not being accessed
the Data Bus Enable input of the 6800 is high and the
clock 1 and clock 2 monostable generators are a symmetrical 500 ns.

*Refer to Introduction.

3-7

POWER
~OWN

Figure 1.

DATA ENABLE . - - - - CLOCK 2
CLOCK 1

Figure 2.

3-8

6800

1k CMOS RAMs

National Semiconductor
Karl Rapp
March 1977

1. INTRODUCTION
memory using passive column pull-up devices or (2)
synchronous memory using active (strobed) column
pull-up devices.

Static CMOS memory with typical access time of only
120 ns-such performance has been made possible by the
combination of an advanced silicon-gate CMOS process
and contemporary circuit-design performance.

With (1) r~ssive pull-ups, cell pass transistors must be
designed to have relatively high impedance to prevent
cell·to-cell interaction, should overlap occur in row
selection. Alternatively, row-address decoders must be
designed to ensure turn·off of a selected row before
turn·on of a new row-with suffici"nt interim delay to
achieve column pull-up. Moreover, cell sense current
must be kept relatively small since sense current from
every cell in a selected row goes into the column
pull-ups-causing power dissipation. The net result is
sacrifice of potentially smaller access time and the
dissipation of power in selected chips.

Four different products comprise National Semiconductor's 1024-bit silicon-gate CMOS RAM family.
Characteristics and differences of these memories are
summarized in Table I. The MM54C921/MM74C921 is
identical to the MM54C920/MM74C920, except that
inputs and outputs are internally connected and share
package pins. The MM54C929/MM74C929 is identical
to the MM54C930/MM74C930, except that the 3 chip
selects are internally connected and brought to a single
pin. All 4 memories use the same basic logic design and
sub·system components. All are synchronous static
memories.

National Semiconductor's CMOS memories are type (2),
synchronous devices. A chip strobe is used to control column pull-ups. Pull-up transistors precharge column lines
high while the strobe is absent; address decoders are inhibited during this time. When the strobe is applied."column pull-ups turn OFF, thereby avoiding any DC path for
sense current; address decoders are enabled. Availability
of the strobe makes possible important design advantages
including high·speed sense ampl ifiers and on-ch ip registers
for address and output data.

2. SVNCHRONOUS VS ASVNCHRONOUS STATIC
MEMORV
Memory Cell
Static memory cells almost invariably are constructed
using 6 devices connected as a pair of cross-coupled
inverters, with pass devices (also called transmission
gates) for selection control. (Figure 1). If the pass
transistors are N-channel, data stored in the flip-flop can
more readily be affected by pulling down on a column
line; the pass transistor then conducts in commonsource mode. Pulling up has significantly less effect
because of the weaker source-follower behavior of the
pass device. Writing into the cell, therefore, consists
predominantly of pulling down the required side of the
flip-flop. Internal cell regeneration causes most of the
rising-voltage action on the other side. It thus follows
that both DATA and DATA column lines must be held
high during ROW address change or data can be
destroyed.

COLUMN
(OATA)

P1i..11- -II

1 "-

Data Protection During Address Change

COLUMN
(OATA)

Vee

II- -II
ROW (WORD) LINE

Two basic techniques are available for protecting stored
data as the selected ROW is changed: (1) asynchronous

FIGURE 1

TABLE I

ORGANIZATION

NO.OF
PINS

I/O

NO. OF CHIP SELECTS
(lNCL. STROBE)

STROBED CHIP
SELECT?

MM54C920/MM74C920

256 x 4

Separate

Ves

MM54C921/MM74C921

256 x 4

Common

Ves

MM54C929/MM74C929

1024 x 1

Separate

MM54C930/MM74C930

1024 x 1

Separate

3-9

3. MEMORY STRUCTURE
General organizations of the 256 x 4·bit and 1024 x
l·bit memories are shown in Figures 2 and 3, respec·
tively. The basic structures of the 2 designs are identical.

While STROBE is LOW, the data®falls through the dataout latch to the TR I·STATE buffer input. When
STROBE next goes HIGH, the data·out latch locks and
stores the data. Note from the diagrams,Figures 2 and 3,
that STROBE has no control over the TRI-STATE
buffer.' Only the other 2-chip selects and the writeenable terminal control TRI·STATE. In WRITE mode
(write·enable LOW), the output is disabled even though
the 2·chip selects are active (LOW).

Each of the designs has address registers controlled by
the strobe terminal (ST for the 256 x 4-bit memories,
CS 1 for the 1024 x l-bit memories). The general term
STROBE used throughout this application note refers to
ST for the MM54C920/MM74C920 and MM54C92T/
MM74C92T and to CST for the MM54C929/MM74C929
and MM54C930/MM74C930. A HIGH level at the strobe

Writing into either of the memory types requires that
STROBE, the other 2chip selects, and write enable all
be LOW, i.e., the chip must be selected and write enable
be LOW. In read mode (write enable HIGH), however, a
chip need not be selected completely for new data to be
stored in the data·out latch. Each chip in a system will
react as its strobe terminal is brought LOW, independent
of the status of its other chip-select terminals. New

terminal allows the external address code to fall through
the address-register latches and reach the decoder inputs;
the decoders, however, are inhibited from selecting any
row or column while the strobe input is HIGH. When
STROBE falls, the address code then contained by the
address registers is latched and external code changes
have no further effect. STROBE LOW simultaneously
enables the decoders, causing the selected location(s) to
be read, and sends the data to the output latch(es).
AO
AI

*ExcePt for the MM54C929/MM74C929 which has the strobe
and other 2 chip selects connected together.

32
X

ADDRESS
REGISTER

ROW

AND

DECODER

INVERTERS

32
X

DO I

011

012

WAITE

013

CONTROL

002

DATA OUT
REGISTER

003

014

004

S'f

CES

ADDRESS REGISTER
AND INVERTERS

FIGURE 2. MM54C920/MM74C920 Logic Diagram

FIGURE 3. MM54C930

3-10

data corresponding to the buss address code will be
fetched and stored in the data-out latches_ The other
chip selects choose which chip delivers its data to the
data buss. Page-mode memory organization thus is
available .••

the end of the cycle, i.e_, until STROBE again falls at
the beginning of the next cycle. The CEl (Chip Enable,
levell control is not latchable. It functions completely
independently of STROB E. Chip selects CS2 and CS3 on
the 1024 x 1-bit RAMs both are level actuated and
operate independently of STROBE eS1.

The only difference between the 2 memory types,
4_ MEMORY TIMING

Figures 2 and 3, aside from the word organization,

lies in the chip-select input circuits. One-chip select
of the 256 x 4-bit RAMs is latched by STROB E exactly
as addresses are latched. CES (Chip Enable, Strobed)
thus must be establ ished at the proper level prior to the
fall of STROBE. As with address inputs, set up and hold
time requirements must be met by CES with respect to
the negative-going edge of STROBE. Once latched by
STROBE, the captured CE level remains constant until

AC specifications for the memories are given in Tables
II and III. timing diagrams in Figures 4 and 5. Typical
values of the parameter as a function of temperature
are given in Figure 6.
**For description of a page-mode application, see Section 7.
paragraph 5.

TABLE II. MM54C920/MM74C920, MM54C921/MM74C921 AC Electrical Characteristics

Vce = 5V ±10%, T A = Operating Range

TTL Interface (VIH

= Vee -

MM74C920, MM74C921

MM54C920. MM54C921

PARAMETER

I
2V, VIL

MIN

TYP

= 0.8V,lnput tRISE = tFALL = 5 ns,

I
Load

MAX

MIN

TYP

MAX

Cycle Time

tAce

Access Time From Address

120

275

120

250

tACS

Access Time From Strobe

110

250

110

225

tAS

Address Setup Time

tAH

Address Hold Time

tOE

Output Enable Time

too

Output Disable T tme

120

255

120

10
15

150

130

150

130

tsf

Sf Pulse Width

tST

ST Pulse Width (positive)

140

125

twP

Write Pulse Width (Negative)

150

130

tos

Data Setup Time

100

tOH

Data Hold Time

(Negative)

150

UNITS

TTL Gate + 50 pF)

290

130

TABLE III. MM54C929/MM74C929, MM54C930/MM74C930 AC Electrical Characteristics

Vce = 5V ±10%, TA = Operating Range
MM54C929. MM54e930

PARAMETER
MIN
TTL Interface (VIH

= Vec -

2V, VIL

TYP

= a.av, Input tRISE = tFALL = 5 ns.

MM74C929, MM74C930
MAX

Load

MIN

TYP

UNITS
MAX

= 1 TTL Gate + 50 pF)
255

135

Cycle Time

tACC

Access Time From Address

105

265

105

240

tACSl

Access Time From CSl

100

250

100

225

290

135

tAS

Address Set-Up Time

tAH

Address Hold Time

ns
ns

tOE

Output Enable Time

150

130

too

Output Disable Time

150

130

tCSf.
(Note 3)

C51 Pulse Width (Negative)

150

tCSI

CSl Pulse Width (Positive)

140

125

twP

Write Pulse Width (Negative)

150

130

tos

Data Set-Up Time

150

140

tOH

Data Hold Time

-30

130

-30

ns
ns

Typical -= Nominal at 25°C
Note 3: Greater than minimum CST pulse width must be used when reading data from the MM54C929/MM74C929 to ensure that output TAISTATING does not occur before data becomes valid. Writing has no such limitation.

3-11

AO-A7

tST

\~
11\

.-J
tAS

tAH

" .

tACS

.1 •

toe

tACC

- - - - - - - - - - - - - TRI·STATE-------------

DOUT

la) Read Cycle

1m = VIH)

---1~

tST

AO-A7 ~~

tST

tAS

tAH

~ ....

1\
~~

~
twp

tos-- - t oH
DIN

\1;

--~

j~-

(b) Write Cycle

\ ....

,,~

~
toe

'= ------- ",,"m -----

-~. . . -----------.}---too

Ic) Output Enable/Disable

fiGURE 4. MM54C920/MM74C920. MM54C921/MM74C921 Switching Time Waveforms

3·12

*CS!

AU-A9

~\.

J\.
tAH

tAS

,
I •

DOUT

- - - -- -

-----

tCS1

tOE

tACS!
tACC
TRI-STATE"l- -

tCS!

-- .:.~~

DATA OUT VALID

---~~I-o-----tcS!---~-1

AU-A9

CS2 AND CS3
I------twp-----~~

----~

r-----------------

(b) Write Cycle

CS2 OR CSJ

'1\
-tOD-

,-tOEDOUT -

-TRI-STATE®- - -

I
\.

DATA OUT VALID

J,~------

FIGURE 5_ MM54C929/MM74C929, MM54C930/MM74C930 SWitching Time Waveforms

3-13

400

300

rr--,-~-r~'-~~'-~"

200

TA 01,5"C
250

150

300
200

1""- r-.....

]

200

150

--... :--

S100
100

100

o
-55 -40

25
TA

-55 -40

5.5

4.5

3.5

eel

(a) Access Time vs Ambient Temperature

(b) Access Time vs Power Supply Voltage

125

T A ('C)

Vee (V)

(e) Minimum Write Pulse Width vs
Ambient Temperature

100

200

150

rr-'-~--r---'r-~~..-~"

100

-55-40

125

(d) Data·ln Setup Time
Temperature

Ambient

rr--'~--r-'~~~'-~-'-'

I++~-+---i~~~t-.

TAn:)

125

-55 -40

reI

125

TA (DC)

(e) Data-In Hold Time vs Ambient
Temperature

(f) Minimum

Sf Pulse Width

(Positive) vs

Ambient Temperature

200

3D rr'-~'--r-----r---"

150

100 t-t~"",Y"""''''''"",~'I7~~

-5
-55-40

-55 -40

125

(g) Address Hold Time
Temperature

25
TA

TA (UC)

Ambient

125

(h) Address Setup Time vs Ambient

;

Test Limit MM54C920. MM54C921

100

Test Limit MM74C920, MM74C921
-55 -40

125

TAl CI

Minimum ST Pulse Width (Negative)
vs Ambient Temperature
FIGURE 6. Typical Performance Characteristics

3-14

125

(j) Output Enable Time vs Ambient
Temperature

rr,----,--,-----,---,-,

150

TA ( C)

T emperatu re

200

-55--40

eel

General
Set-up and hold time requirements, with respect to
STROBE, must be met by all address inputs and by CES
(MM54C920/MM74C920 and MM54C921/MM74C921
only). A minimum down time is specified for STROBE
to ensure that new data reach the output latch during
READ and to provide sufficient time to reliably enter
new data during WRITE. A minimum STROBE up time
is specified to allow for pulling up columns and for
precharging se'nse amplifiers. The sum of these 2
STROBE time specifications establishes minimum
cycle time.

minimum set-up time, tDS, before the first posltlvemoving control-signal edge and be maintained a minimum hold time, tDH, beyond that edge. For successive
WRITE cycles, note that WE and/or the auxiliary
chip selects may be kept LOW. STROBE alone then
would establish the write period.
Disabling of the output buffer when write-enable, WE,
is LOW is useful for common-data-I/O applications.
These CMOS memories have been designed to keep
their outputs disabled when WE and the auxiliary chip
selects simultaneously go LOW. Note, however, that if
the chip selects fall prior to WE, outputs can become
briefly enabled until the falling WE signal takes control.
Conflict between external data drivers and the on-chip
data buffers could occur during this interval, causing
unexpected data-buss transients. No damage to the
CMOS RAM's will occur, however.

READ Cycle
Access time is specified both from address change and
from the falling edge of STROBE. Access from address
change is the more meaningful measure of the speed
with which new data can be fetched_ It is important,
however, to recognize that access from STROB E will
limit if more than minimum address set-up time is
provided.

5. DC CHARACTERISTICS

Note that the asynchronous character of all auxiliary
chip-select controls except CES (MM54C920/MM74C920
and MM54C921/MM74C921) permits them to fall after
STROBE _ Provided that the selection occurs at least
tOE (output-buffer enable time) before new data are
made internally available by STROBE, no effect on
access time occurs.

DC Specifications for the memories are contained in
Tables IV and V. Over their operating voltage and
temperature ranges, the memories easily can drive a
TTL load. Current sinking capability is guaranteed to be
at least 2 mA at OAV, while an rnA source current is the
minimum available at 2AV. Typical output currentvoltage characteristics are given as a function of temperature in Figure 7.

The MM54C929/MM74C929 is different from the
other 3 parts in that all 3 of its chip selects are internally
tied together_ Data-access control and output-buffer
control, therefore, are no longer isolated. Consequently,
STROBE should be kept LOW the full access time to
prevent turn-off of the TR I-STATE buffer before new
data are available.

For battery-backup applications where low power is
extern ely important, these RAMs will retain data with
VCC supply voltage as low as 2V. Supply current,
guaranteed to be no more than 10 JlA at full VCC,
typically is only a few nanoamperes.
.Typical operating supply current is shown as a function
of supply voltage in Figure 8. These current values are
for 1 MHz operating rate. Operating current is linear
with frequency, however, and can be directly scaled
for other frequencies.

WRITE Cycle
WRITE circuits on a chip are activated only when
STROBE, the other chip selects, and WRITE ENABLE
all are LOW. To satisfy the specified minimum writepulse width, then, these signals must be jointly LOW for
at least the specified tWp.

6_ MEMORY LOGIC AND CIRCUIT DETAILS
Logic symbols and their circuit equivalents are defined
for this section in Figure 9.

The first of the above control signals to move HIGH
ends the write operation. Input data must be valid a
-20

40
Vee = 5V

Vee'" 5V

-11.5

-15
-12.5

"1oS

=-i5'C

-1.5

/,/

-5

lL: :.::::: :;..-

I;p5

4.5

3.5

.§

- TT

2.5

TA = 12S"C

I I
2

1.5

'1/ V
10
II Y'
o If'
o

/r/

0.5

la) Output Source Current YS Output
Voltage

.,/" V

./
./

I-""To =125'C

o
1.5

2.5

3.5

VOUT IV)

TA =25"C

TA=25 C

...J-

TA '" _55°C

T~
....,~ "

-10

-2.5

I I
I I

Ib) Output Sink Current YS Output
Voltage

FIGURE 7

3-15

3.5

4.5

5.5

Vee IV)

FIGURE S. Dynamic Current YS Power
Supply Voltage IV,H = VCC, VIL = OV)

TABLE IV. MM54C920/MM74C920, MM54C921/MM74C921 Absolute Maximum Ratings and DC Electrical Characteristics

Supply Voltage, Vee

Vee

Operating Temperature Range
MM54C920. MM54C921
MM74C920. MM74e921

7V
-0.3V to Vee + 0.3V
-65°C to +150°C

Voltage at Any Pin
Storage Temperature Range

= 5V ±10%, TA = Operating

-55°C to +125°e
-40°C to +85°C

Range

PARAMETER

MM54C920. MM54C921

CONDITIONS

MIN

TYP

MM74C920, MM74C921

MAX

MIN

VIH

Logical "1" Input Voltage

Vee-2.0

Vee

Vee-2.0

VIL

Logical "0" Input Voltage

0.8

VOHI

Logical "1" Output Voltage

IOH: -1.0mA

TYP

MAX
Vee
0.8

Vee-O.Ol

V
V
V

2.4

UNITS

VOH2

Logical "1" Output Voltage

lOUT: 0

Vall

Logical "0" Output Voltage

IOL: 2.0mA

0.4

VOL2

Logical "0" Output Voltage

lOUT: a

0.01

IlL

Input Leakage

OV ~ VIN

<:: Vee

-1.0

0.001

1.0

-1.0

0.001

1.0

Output Leakage

OV ~ Va ~ Vee. eEL: Vee

-1.0

0.001

1.0

-1.0

0.001

1.0

jlA

ICC

Supply Current

VIN: Vee. Va: OV

0.1

jlA

Vee-om

V
V
jlA

elN

Input Capacitance

(Note 1)

Output Capacitance

(Note 1)

ella

Data Input/Output Capacitance

MM54C9211MM74C921 Only

VDR

Vee for Data Retention

eEL: Vee

2.0

Note 1: Capacitance is guaranteed by periodic testing.

TABLE V. MM54C9291MM74C929, MM54C930/MM74C930 Absolute Maximum Ratings and DC Electrical Characteristics

Supply Voltage. Vee

Vee

Operating Temperature Range

7V
-O.3V to VCC +O.3V

Voltage at Any Pin
Storage Temperature Range

MM54C929, MM54C930
MM74e929. MM74e930

~5"eto+150oe

= 5V ±10%. TA = Operating

-55°C to +125°C
-40oe to +85°C

Range
MM54C929. MM54C930

CONDITIONS

PARAMETER
VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

VOHI

Logical "1" Output Voltage

VOH2

Logical "1" Output Voltage

IOUT=O

VOLI

Logical "0" Output Voltage

IOl =2 mA

MIN

TYP

Vee-2.0
0

MIN

Vee

Vce-2.O

0.8

2.4

IOH=-1 mA

MM74C929, MM74C930

MAX

TYP

MAX
Vee

0.8

2.4

Vec-O·01

0.4

0.01

Logical "0" Output Voltage

IOUT=O

Input Leakage

OVSVINSVee

-1.0

0.001

Output leakage

OV S Va S Vee. eS2 or CS3 : Vee

-1.0

ICC

Supply Current

VIN = Vee. Vo = OV
VIN = Vee = 2V. Va: OV. at 25°C

0.25

Vec-O.D1

III

0.4

VOl2

UNITS

0.01

V
V

1.0

-1.0

0.001

1.0

-1.0

0.001

1.0

jlA

0.5

100

0.5

jlA
p.A

1.0

0.25

jlA

VIN: Vee = 2V. Va: OV. at 125°e

jlA

e'N

Input Capacitance

(Note 1)

Output Capacitance

(Note 1)

ecg

Chip Select Capacitance

(Notes 1 and 2)

VOR

Vee for

CS2 or eS3 = eSl = Vee

Data Retention

2.0

Note 1: Capacitance maximum is guaranteed by periodic testing.
Note 2: MM54C929/MM74C929.

3-16

2.0

Memory Cell and Selection Structure
for the output of either decoder type to go HIGH.
Address bits AS and A9 are used only for the 1024-by-l
memories.

The basic 6-transistor memory cell has already been
described in Section III and Figure 1_ Figure 10 illustrates
how each cell fits into the ROW/COLUMN and READ/
WRITE selection structure_ The memory cells are laid
out in a 32-by-32 matrix_ Hence, the ROW-SELECT
signals have a 1-of-32 code; the selected row goes HIGH;
the other rows remain LOW_ The pass transistors Nl and
N2 of all cells on the selected row then conduct_
Similarly, selected COLUMN lines go high_ The select
code is 4-of-32 for the 2S6-by-4-bit memories and
1-of-32 for the 1024-by-l-bit memories_ A HIGH COLUMN-SELECT signal turns ON both the WRITE access
transistors N3 and N4 and the column sense amplifier.
If the chip is in WR ITE mode, the WR ITE circuits pull
either the WRITE "1" or the WRITE "0" buss LOW;
the other one floats. In READ mode, both busses float.
During selection, column-pull-up transistors PI and P2
are turned OFF (STROBE is HIGH).

Address Latches
Address registers comprise fall-through latches of the
type shown in Figure 12_ When STROBE is HIGH, the
external address code is transmitted directly through
to AK and AK. STROBE latches the code by going LOW.
CES Latch
The CES latchable chip select on the 256-by-4 RAM's is
implemented using 2 latches of the type shown by
Figure 12, to produce a dual-rank D flip-flop. Positive
STROB E transitions thus do not disturb the stored
state for CES. *

Address Decoders
*Early prototypes of the 256-by-4 memories used only a single
latch stage. The external level on CES then would fall through
when STROBE went HIGH.

ROWand COLUMN address decoders are logically as
shown in Figure 11. Note that STROBE must be LOW

~~ ~--Vee

-t>o-{

Vee

•

•
•

(a)

Vee

I
I

(b)

~~""---------f~:
I

•
•

I
I

PATH CLOSED
WHEN M IS HIGH
M

AK-+-------------~....~

tf---

--fiT
M

(e)

(d)

FIGURE 9

3-17

Vec

STROBE

VCC

"~~I~1~1~~
I

ROW
SELECT

~
I
I

I
I

WRITE 'T' -i--+---4--~~-+-
WRITE "0"

- i - -...--4-----+--

_ _ _ _ _ _-e~-+_---_+----SENSE
DATA

___________...___-+___

BUS
COLUMN
SelECT
FIGURE 10

STROBE~
AS

STROBE
AD

Al.....,~:r-'
A2

--r;:J.._.1

A6
A7

ROW
SELECT

COLUMN
SELECT

(AS) - -.I I

(A9)---.I '

Ib)

la)

FIGURE 11

-----+Aj{
ADDRESS
INPUT

FIGURE 12

3-18

WRITE Control Logic

Data Latch and Output Buffer

Figure 13 presents the logic used to control writing.
Note that pass transistors N 1 and N2 conduct only when
all input controls are LOW, thus placing the chip in
WRITE mode.

Figure 15 diagrams the fall-through output-data latch
and the TRI·STATE buffer. When the TRI-STATE
control is LOW, both Pl and Nl turn OFF and the
output floats.

Sense Amplifier

7_ APPLICATION CONSIDERATIONS

The high-speed sense amplifier, shown in Figure 14,
consists of differential-amplifier pairs at the end of each
column, all connected via the sense-data buss to a
single pair of load devices, L1 and L2. When STROBE
falls, current flows in the selected-column differential
amplifier, causing an amplified voltage differential
between the 2 lines of the sense-data buss.

Latch-Up Precautions
The structure of CMOS Ie's (Figure 16) intrinsically is
similar to the PNPN structure of SeA's. If a junction
becomes sufficiently forward-biased, the resulting
minority-carrier injection can set off regenerative PNPN
firing and thus cause large supply currents (100's of
WRITE "0"

WRITE "1"

FIGURE 13

Vcc

SENSE
DATA
BUS

----t--e----+-

----1--+--...-+-

~.::.:::!t;~"

LATCH

FIGURE 14

TRI·STATE@
CONTROL

FROM
SENSE
AMP
FIGURE 15

Vee

Vec

3·19

FIGURE 16

milliamperes) which pull down Vee. It is important,
therefore, to prevent input or output terminals from
being driven more than 0.5V beyond the supply-voltage
range.

higher values than Vee as the supply is reduced or
supply latchup can occur, (2) inputs should be maintained during reduced-voltage standby at either GROUND
or the present Vee-and not some intermediate voltageto prevent input inverters from drawing ICC, (3) control
signal levels must be arranged to stay out of WR ITE
mode to avoid affecting stored data.

Input Stages and ICC
Input inverter stages are designed to accept TTL levels_
It should be recognized, however, that some ICC will
be drawn by an inverter if the input-voltage level causes
both P and N-channel transistors to conduct. Since the
threshold voltage for both transistor types is about
0.7V, an input more positive than 0_7V and more
negative than Vee-O. 7V will cause conduction. A curve
showing typical ICC versus temperature is given in
Figure 17 for the case where all inputs are at the TTL
V IH level. Not only the worst-case TTL level was used,
but worst-case supply voltage of 5.5V also, to provide
the highest typical currents one might expect.

During recovery of Vee to its full value, the STROBE
logic state must be maintained constant (either HIGH or
LOW) until address-line logic levels stabilize. This
precaution on STROBE is necessary to avoid data destruction should STROB E experience a brief LOWHIGH-LOW transition as signals stabilize_ Such a brief
transition could permit the fast-acting address-latch
circuits to enter a new code, but might not allow sufficient time for data columns to be pulled up.
One useful method for providing battery back-up,
consistent with the preceding precautions. is shown in
Figure 18_ The proper action for calling in the back-up
battery is the following: (1) when removing VMAIN
or sensing that it is being lost, bring es LOW. Cs then
assumes the moving Vee potential and keeps the chip
de-selected. (2) bring all other input signals to GROUND
potential. (Actually, address inputs need not be controlled if STROBE is grounded since external signals
then are locked out_ See Section7, paragraph 2).

To produce minimum power dissipation during standby,
it is necessary to bring input levels to either OV or a full
Vee·
Reduced-Voltage Data Retention
These CMOS RAM's will retain data with the supply
voltage reduced to as low as 2V. They consequently
find useful application in battery-backup data storage.
In such applications, as Vee is reduced, 3 precautions
must be observed: (1) input voltages must not be left at

As VMAIN is re-established, hold STROBE LOW until
address inputs stabilize.

I-..

...... ~:>

<
..§
I2:

::0

a:
a:

'"
>
--'
<><>::0
en

VCC

MM54C920/MM74C920,
MM54C921/MM74C921,
MM54C929/MM74C929,
MM54C930/MM74C930

r... .....

.......

......

, ...

......, ...........-0

+VMAIN
+VBACKUP

:.
~

"--

1 - -.....

CS"~.

~......

3
-55 -40

125

TA - AMBIENT TEMPERATURE (DC)
FIGURE 17_ Typical DC Supply Curr~nt with
TTL Input Levels vs Ambient Temperature
VCC ~ 5_5V. VIH ~ 3_5V .

For MM54C920/MM74C920
MM54C921/MM74C921
For MM54C929/MM74C929
MM54C930/MM74C930

FIGURE 18

3-20

cs ~ CS2 or CS3

CCS

Designing with Slower Transition Times

Page-Read Memory

AC performance (Tables II and III) is specified and
measured from 50% points of signal transitions. In
applications where system-signal transition times are a
significant fraction of specified times, V IH and V IL
levels should be used as the measurement points. For
example, to ensure adequate address set-up time,
measurement as defined in Figure 19a should be used.
For hold time. define as in Figure 19b.

Because new data are latched into all chips in which
STROBE is pulsed LOW-regardless of chip·selection
status-page-organized memory can be implemented.
Figure 20 shows an example. Here, all chips are connected in parallel to STROBE and to the address lines.
One cycle of STROB E brings data, corresponding to the
address code, to all chip data-out latches. The M words
of N data bits then can be scanned by successively
selecting chip selects CSO through CSM. Since outputenable time typically is only 50 ns, such a block of
data can be read much more quickly than the 120 ns
typical a full access would require.

ADDRESS

(al

(bl

FIGURE 19

For MM54C920/MM74C920
MM54C921/MM74C921
For MM54C930/MM74C930

Cs = CS2 or CS3

FIGURE 20

3-21

~
~

IDM2901A File Expansion
Using the DM85S68

::E

;;
m

'ii)
:::::)

File Expansion

In certain applications the number of registers must be
expanded beyond the 16 which are contained within the
IDM2901A. The expansion is quite easily obtained with
the use of the DM85S68 addressable 0 register file
element. This array of registers is structured the same as
the IDM2901A in that there are 16 words of 4 bits each.
This component is clock edge senstivie when writing.
Figure 1 shows the two components (lDM2901A and
DM85S68) connected together so the effective size of
the file is 32 words deep. It is easy to see how further
expansion can be obtained if desired. There are several
possibilities which could be used for address decode of
this 32 word file. The most versatile usage would be to
have separate address selection for each of the files. The
IDM2901A would have an A address input and a B
address input and the DM85S68 would have a distinct
address input. If this cannot be obtained because of the
system requirements then common address decoding for
the 32 registers into two five bit fields can be obtained
as in figure 2. In this schematic the external file is now
limited in function to that of the internal portion of the
file with the exception of shifting.

What can you do with this file extension?
Assume the following:
file locations RO through R15 are in 29015
R16 through R31 are in DM85S68
Then:
RO-15 + BO-15

What does this schematic not do well?
I Single cycle shifts do not work, except RO.15
Shift Right or Left is OK.
Shifts can be performed by making a transfer to the Q
register, then shifting, and then transferring back to the
R 15.31 register.

.,~-"
"",:'ru~~UTS
1-<",
EI(PANSIOIV

ENABLE

BO-15
R16-31

R16-31 + BO·15 -+ BO-15
-> R16·31
R16·31 + RO·15 -+ BO-15
R16·31
R16·31 + RO·15 -> Q

E~'AIISION

LOW FILE

->
->

INTERFACE

HI~::~t~,--------------'

File Expansion & Control

3·22

"IGHFllE
II.OOAESS

Section 4

Read Only Memory
Program storage for microprocessors has become the
fastest growing area of ROM application. As the performance of microprocessors and the sophistication of users
increase, so will the requirements for large amounts of
program storage. Also influencing larger ROM sizes is
the trend toward higher level languages for microcomputers. The MAXI-ROMTM is a perfect vehicle for
"Silicon Software™" - which is National's name for
putting high level languages such as I NS8080A BASIC,
PACE BASIC, and NIBL (National Industrial Basic
Language) for the INS8060 (SC/MP) into mask-encoded
ROM - at a reasonable cost. Refer to National's Memory
Data Book for the pin·compatible series of MAXI-ROM
data sheets and current Silicon Software. Refer to this
section for appl ications.

PROM Patches for the
MAXI-ROM

National Semiconductor
C. Mitchell
October 1977

The introduction of the MM5235 8kx8 MAXI-ROMTM*
by National Semiconductor provides the system designer
with cost-effective ROM to increase system capability
with reduced package count and cost.

Here the first level PROM (DM74S287) provides address
decode and the more significant address bits to the
second level PROM(s) (DM74S288). These in turn
provide substitute data to the bus. Note that use is made
of the maskable chip selects on the MM5235. Conserva·
tive system design should allow fo~ the possibility of
patches. Board layout should follow the same philosophy
providing for the patch circuitry.

This 65,536-bit mask programmable ROM creates an
understandable reluctance to commit such a large bit
pattern to mask without extensive field testing.
This extensive field testing has associated costs in terms
of EPROM programming overhead, parts count, component costs, and time wh ich provide strong incentive to
achieve an early masked ROM solution. One way to an
early MAXI-ROM solution with minimal field testing is
presented here.
The fundamental concept is to provide the capability
of correcting errors in the MAXI-ROM program with
system design/hardware (rather than by regenerating the
masks). This also would provide for future changes to
extend the market life of the system or to create additional capability.

Use of this dual rank approach allows greater adaptability as well as tighter packing density. Notice that
data must (again) be replaced in blocks starting at
location (binary) aaaA AAAA AAAO 0000 where the
page address (represented by As) is programmed into the
first level PROM. This allows block size to be a function
of first level PROM output width and to be altered to
provide less program redundancy between MAXI-ROM
and the second level PROM. Regardless of block size the
second level devices must copy the MAXI-ROM from
start address to the ending location, correcting the
erroneous locations in between.

This PROM Patch consists of providing a decode for the
address location(s) of the MAXI-ROM which are to be
altered, disabling the ROM and providing the corrected
data to the data bus. The most cost-effective solution is
through the use of a coincidence gate and a bipolar
PROM as shown in figure 1.

The only timing restriction imposed upon the circuit in
figure 2 is that the time between settl ing of the address
lines and the leading edge of CE must exceed the access
time of the DM74S287 (50 ns). This is most easily
accomplished in most systems by making CE a function
of the Read Strobe.

This configuration allows correction of a single block of
32 bytes (one page). This block must start at a MAXIROM address divisible by 32. This is dictated by the
requirement that A5 through A 12 must remain unchanged for the 32 combinations of AO through A4 in
order to get all 32 bytes. The su bstituted 32 bytes of the
DM74S288 must contain the correct data originally
stored in that page of the MAXI-ROM as well as provide
altered data for those locations requiring correction.

The ultimate in efficiency and flexibility for a PROM
patch could be provided by a field programmable logic
array (FPLA). Unfortunately the present high cost of
these devices precludes their use in any but the most
demanding parts count minimization.

More sophisticated techniques involving the use of
adders to set initial starting addresses can be visualized.
The primary drawback to such visualizations and the
realization in figure 1 is the same. They are restricted by
the requirement to hardwire page addresses. A technique
not requiring jumpers or wired addresses utilizes a minimum of 2 PROMs. This approach is shown in figure 2
using 3 PROMs.

Reviewing briefly, we have seen that there are a number
of configurations which allow alteration of masked ROM
configurations in a production system. The ultimat~
decision concerning the amount and type of patch
provided for a MAXI-ROM can only lie with those
software and/or hardware designers knowledgeable of
the system, and must be based on experience and
confidence. If this is done correctly enormous advan·
tages in system capability can be realized through the
use of large fixed program devices, i.e., MAXI-ROM.
*A trademark of National Semiconductor Corporation

4·1

DM8130
AS-AI4

..•=

P
WIREDADDR

AD-A4

!l
II:

co
co

)

AD-An

DATA BUS

Figure 1. PROM Patch for MAXI·ROM (1)

CE------. DM74S287

II:

i~~------------------~~~------------~
=~~~.--------~~~
co~~'-I-_

!
!

II:

DATA BUS

Figure 2. PROM Patch for MAXI·ROM (2)-

4-2

ROM Emulator Using
a Non Volatile RAM

National Semiconductor
Memory Application
Manfred Schwarztrauber*
November 1977

INTRODUCTION

The purpose of this article is to show how a read-write
memory with battery backup can be implemented in
order to use it as emulator for PROMs or ROMs in
microprocessor systems_

cable to all connecting points of the ROM emulator
should be provided. This is a flexible cable harness,
terminated with a plug (connector 2) that is pin compatible with the PROM MM5204Q (or any other PROM).
In this method, the possibility exists of plugging the
ROM emulator through its cable directly in a corresponding socket of the ROM or PROM in a field application. Addresses, data, and control signals of the ROM
emulator will then be connected to the bus of the
desired application. A separate, smaller cable is used to
supply the external read-write signals (connector 3).

Fixed, dedicated, unchangeable program portions are
stored in read only memories (ROMs) or in programmable
read only memories (PROMs) in microprocessor systems_
These application programs are often created on a microcomputer or on a prototyping system with the aid of
assembler or cross-assembler programs_ One cannot
assume that the programs, which are error-free
assembled, function perfectly for a specific application
the first time around.

In the example described here, a 512-byte RAM with 4
chips of MM2112N was built. Naturally, any other
configuration with other RAM chips (for example
CMOS) can be used, according to requirements_ It is
essential always to have compatibility between the
emulator card and the corresponding ROM or PROM.

In most cases, several corrections are necessary involving
a learning curve until a program functions optimally
and error-free.
The above considerations show:

The supply of power to the memory board is buffered
by 4 rechargeable batteries, so that the retention of data
in the RAM is assured while providing portability (transport from prototyping machine to application). If power
is required from batteries a switch should be placed in
Position B (see figure 1). All 4 batteries are then in series
and deliver the required operating voltage.

1. It is necessary that program parts can be
changed easily.
2. The memory must be non-volatile so as to not
lose data in case of power failure or work
interruption.
Both requirements can be easily realized with a readwrite memory (RAM) that is provided with a battery
backup to ensure data retention. In addition, there
should be an easy way to store cross-assembled programs
in the RAM and to test them in their specific applications environment.

During the operation with the main power supply,
Switch 1 should be in Position L. This allows the batteries to be charged in pairs, permitting a higher charging
current (power) per battery. With the help of Switch S2,
the batteries can be separated entirely from the power
supply and board.

In this manner the battery powered RAM becomes a
ROM replacement in the particular machine or application. From this comes the choice of the name ROM
emulator.

Figure 1 shows the principal construction of transportable RAMs with the buffered battery, the wiring configuration to the backplane, as well as to the PROM/ROM
compatible flexible cable.

ROM EMULATOR HARDWARE

LOADING THE EMULATOR

Figure 1 shows an example of a ROM emulator. With
regard to hardware there are certain conditions in
treating the RAM card as a ROM emulator:

The transportable RAM (the ROM emulator) can be
loaded with data in different ways_ Two basic possibilities will now be discussed:

It is advantageous to install the ROM emulator (battery
powered transportable RAM) as a plug-in daughter board
on a prototyping card_ The prototyping card itself serves
solely as a mechanical interface in the card cage of the
microcomputer to its bus. In addition, the wiring of the
daughter board (connector 1) is made to correspond to
the wiring of the microcomputer bus, for example the
SC/MP Low Cost Development System bus.

The first possibility concerns the SC/MP Introkit, a
microprocessor kit with teletype interface from National.
The other refers to a prototyping machine. In both cases
the ROM emu lator serves as an extension of the RAM
of the system.
Figure 2 shows the memory configuration of the SC/MP
Introkit. Here the only practical way is to use the ROM
emulator via its flexible cable as RAM extension. On the
Introkit there is a provision through a corresponding
socket to connect its addresses, data, and control signals
easily to the ROM/PROM pin combatible plug of the
emulator. After this connection is completed, it is
possible to load the ROM emulator with data over the
teletype interface of the Introkit.

Likewise, special software must be created which
permits the program to be stored in the ROM emulator.
This software is basically a data loader.
In order to facilitate the use of the ROM emulator in a
specific application, a further hardware requirement
must be fulfilled_ Parallel to the backplane a second
-Refer to Introduction.

4-3

DATA/r -

IU'

110.

liDS

liliiii2112

r-- '"

.IW

~<1"

-..n

".!W

"1'1>-

.. ~

.--.

LLJ

-------------------

-THIIRJWCOIITROlIllAYNOT U AVAILAILE
AT A'ftOfll OR AOMIOCKU.

~(f.

1/01

MM2112

....IW

Tl>""

MMlI1Z

./W

'"
1

.~ rlll~Ea

Ji"

-----·----1

I'"'''' l..._,,·"

-!-

160n

!i "

,roo

1IM!1IZ

I
$3

Ii-1"""

1/01

r--(i

Ve,

.MIll

--"'"",'"

BI!:

.".

Figure 1. Portable PROM/ROM Emulator

CONCLUSION

The second possibility concerns a prototyping system.
As already mentioned, the ROM emulator is plugged
into the daughter board on a prototyping card, and this
is installed into a prototyping system. The data is loaded
via the microcomputer bus and the backplane into the
ROM emulator. With the help of software it is now
possible to load data directly - that means the creation
of the program itself can occur at the assembler level.

The principle, as explained here utilizing the MM2112,
MM5204Q, Introkit, and prototyping system, can be
applied through enlargement of the RAM and change of
the PROM·ROM compatible plug to any presently
available PROMs or ROMs of any size. For bigger
memories it is advantageous to install CMOS in order to
keep the battery power necessary for the retention as
small as possible. The emulator principle described here
can be used on another microcomputer machine with
another processor in the desired application. In this case,
the load program must, of course, be created in the
respective assembler mnemonic of the microcomputer
being used and also in the corresponding cross-assembler
(if necessary) for the processor in the desired application
at hand.

A program must be generated to allow the loading of
modules, as they are produced, from the prototyping
machine directly into the ROM emulator. Naturally, the
wiring of the ROM emulator's address field must be
determined and established.
With the help of this program it is possible to load "load
modules" in the ROM emulator as they are generated.
The program which is stored directly in the ROM
emulator in machine code can now be directly tested in
the desired application.
After testing, debugging, and verifying an application
program, it can be loaded into a corresponding PROM.
The programmed P"ROM can now be plugged into the
desired application, and substitutes for the ROM
emulator.
4-4

OATA BUS

.--------1"
CONNECTOR 2 (FIGURE I)
CAN PLUG IN THIS SOCKET
IEMUlATOR USES ADDRESS
RANGE ZOO TO lFFJ
MM5204

AD!

L..-(I

AD7

SC/MP

OB4

D~3

\1 0;,

A;'
NWDS

-I>

I I lIS:
"S

AD1I

)

I I

/ 8

ADDRESS BUS

I--

'---CHIP

SELeCT
lOGIC

,J>-

+- \
:

""
MM2111

EE
RIW

:
~

RIW

Figure 2. Memorv Configuration of SC/MP Introkit Showing PROM/ROM Emulator Connection

lf~4

1101
MM2112

National Semiconductor
Application Note
Bill Johnston

Custom ROM
Programming

INTRODUCTION
National Semiconductor Corporation uses a computerized system to service customers with accurate, fastturnaround processing of custom ROM orders. This
system is called the Mask Programming System (MPS).
It provides (1) easy customer interface, (2) fast turnaround, (3) automatic error checking, and (4) pattern
verification. The following discussion describes the MPS
input formats and procedures allowing the customer to
uti Iize the system efficiently.

Mixed definitions, positive for inputs and
negative for outputs, or vice versa, cannot be used_

program.

I/O Definitions
Addresses:

This application note applies specifically to ROMs. The
general approach is the same for the many other types
of circuits produced by NSC which utilize the MPS, but
their unique requirements are not covered here_

AO is the least significant address bit. (Some earlier types
have no AO and start with A1 as the least significant
address bit.) LO is the least significant line address bit
and AO is the least significant character address bit in
character generators. The highest address subscript
indicates the most significant address bit. (Some control
pins have been labeled like address pins, e.g_, A8 on the
MM4221; these should not be treated as addresses.)

MPS FORMATS

Outputs:

01 or B 1 is the least significant output bit. The highest
output subscript is the most significant output bit.

GENERAL
The MPS is designed to convert custom ROM programs
into machine language, accomplish error checking and
data processing, and then output magnetic tapes and a
verification listing. The magnetic tapes are used for mask
production and test tape generation. Technically, the
MPS includes the CALMA and DAVID MANN systems
used in generating "masters" and "working plates."
These "working plates" are the masks used in fabricating
the wafers with a custom ROM pattern.
The MPS will accept several formats, but using the standard MPS format will eliminate preprocessing steps. This
will reduce turnaround time and decrease the possibility
of error.
DEFINITIONS
Logic Definitions
Negative Logic:

A logical "1" is the more negative logical voltage level.

Programmable Chip Select/Enable Functions

Positive Logic:
Chip Selects (MOS ROMs):

A logical "1" is the more positive logical voltage level.

Some device types have programmable chip selection.
The one-zero pattern, which selects the chip, must be
specified with the same logic definition as the addresses
and the outputs.

Usually bipolar ROMs and N-channel MOS ROMs are

electrically specified in positive logic. This means their
data sheets will indicate a logical "1" is the more positive
logical voltage level for inputs (addresses and chip
selects/enables) and for outputs. Conversely P-channel
MOS ROMs are often electrically specified in negative
logic. This means their data sheets will indicate a logical
"1" is the more negative logical voltage level for inputs
and outputs. The MPS is designed to generate programs
consistent with the electrical specifications of the "1"
and "0" logic voltage levels of each device type. ROM
program data may be submitted with either logic definition but the MPS will automatically complement the
data (addresses, outputs, and chip selects/enables) when
the logic definition of the submitted data does not
match that of the data sheet. The customer must specify

Chip Enable Options (Bipolar ROMs):

Some device types have programmable chip enable
options. The customer must select the desired option
from the data sheet.
Terms
TB:

The total number of "1" bits in a column expressed in
decimal.
SUM:

The total number of "1" bits in a row (output word)
expressed in decimal.

which definition has been used when submitting a

4-6

ORDER INFORMATION

The following information must be submitted with each custom ROM program. An order will not be processed unless
it is accompanied by this information.

NATIONAL PART NUMBER
ROM LETTER CODE (NATIONAL USE ONLY)
NAME

DATE

ADDRESS

CUSTOMER PRINT OR 1.0. NO.

STATE

CITY

ZIP

PURCHASE ORDER NO.

NAME OF PERSON NATIONAL CAN CONTACT (PRINT)

TELEPHONE

AUTHORIZED SIGNATURE

DATE

LOGIC DEFINITION:

CHIP ENABLE OPTION (BIPOLAR ROMs):

POS (positive logic on addresses, outputs, and ch ip
select/enable)

Choose the desired option from data sheet and enter the
option number here. Write N/A if not applicable.

NEG (negative logic on addresses, outputs, and chip
select/enable)

OPTION NO. _ _ _ _ _ _ _ _ _ _ _ _ __
PAPER TAPE DEFINITION
(BINARY COMPLEMENT OR BINARY ONLY):

CHIP SELECT ONE·ZERO PATTERN (MOS ROMs):

A punch equals

Show the one·zero pattern that selects the chip (use the
same logic as.specified above). Write N/A in each space
where this is not applicable. (Chip enables should be
treated as chip selects, e.g., CEl = CS1, CE2 = CS2, etc.)

0"1"

CSl =

"0"

N/A

(Check N/A if not used.)

CS2=
Figure 1. Order Information Form

STANDARD FORMATS FOR';; lk WORDS
Cards

ally. Should a correction be necessary, only a single
card (or a few) need be changed.

Cards are the first preference for data entry for ROMs
with up to 1024 addresses (words). Data entered on
cards in the MPS format can be directly processed
by the MPS with no additional processing and all information can be checked for errors/omissions automatic-

The following coding forms show the MPS card format
with its minor variations depending on the number of
outputs. See figures 2, 3, and 4.

......

Figure 2. MPS Card Format for ROMs with 4 Outputs

4-7

~."~AT'"

Figure 3. MPS Card Format for ROMs with 8 Outputs

!fa=--

1=.._

~:::,+-rrT[ff~'g

~~, .. ",.""",." .... " .. "~,.., .. ,.~,,:,;::,...-~~.;;.... .,,-:-,I;.,,,.",.,.... '...,...... ,.... ", ,,;.;~
,:":'~"
\ I " ,,"

Figure 4. MPS Card Format for ROMs with 12 Outputs
Notes:
1. Specify product type including the two-letter prefix - OM for bipolar ROMs or MM for MOS ROMs.
2. Specify the type of logic - either positive (use POS) or negative (use NEG). See the "Definitions" section for further explanation.

3. Some MOS ROMs have programmable "chip select" codes. Show the logic level for each chip select that will select the ROM. Use the same logic
definition (NEG or POS) as chosen for the addresses and outputs. If no programmable chip selects are involved, make no entry. Chip selects are

numbered from 1 up; they do not start with zero.
4. The first ROM input address per line (per card) is entered in decimal form and preceded by the letter A. The first address is zero. Leading
zeroes must be shown (punched).
Use:
AXX for 0 to 63 addresses
AXXX for 0 to 511 addresses
AXXXX for 0 to 1023 addresses
The last address shown will be n -4 where n = number of addresses (output words) of the ROM.

5. All addresses must be programmed. Four output "words" (addresses) are entered per line (punched per card).
The number of "data" cards is equal to the total number of addresses divided by 4.
Use the same logic definition (NEG or POS) for outputs, addresses, and chip selects.
The least significant output bit (bl) is entered on the right. This is the logic state of output 1 for a given address. The most Significant output
bit (b4, bS, or b12) is entered on the left. This corresponds to the logic state of the highest order output for the corresponding address. Outputs
are numbered from 1 up; they do not start with zero.
6. The total number of "1" bits in the output word is entered one space after the output word. This is for error checking. Leading zeros must be
entered for ROMs with 12-bit output words.
7. The total number of "1" bits in each output bit position (column) is entered. Leading zeros must be entered (punched). Four digits are shown
for 1 024 addresses, but only 3 are necessary for 512 addresses, and only 2 are necessary for 64 addresses. The last 4, 8, or 12 cards, depending
on the number of outputs, will show these sums for error checking.

4-8

Paper Tape
The second preference for data entry is paper tape using
the MPS format. Using the 7·bit ASCII code on 8·punch
tape allows customers to utilize more readily available
equipment. This a'lso allows direct entry into the MPS
complete with automatic error checking. The disad·
vantages are the length of tape required with larger
ROMs and the requirement of making a complete
new tape to correct errors.

The format is essentially the same as for cards except
that each address is punched together with the output
word. The following coding forms (figure 5) show the
MPS paper tape format.

II=:=I::::..

II=-

,------

Figure 5. MPS Paper Tape Format
Notes:
1. Specify product type including the two-letter prefix -- OM for bipolar ROMs or MM for MOS ROMs.

2. Specify the type of logic - either positive (use POS) or negative (use NEG). See the "Definitions" section for further explanations.

3. Some MOS ROMs have programmable "chip select" codes. Show the logic level for each chip select that will select the ROM. Use the
same logic definition (NEG or POS) as chosen for the addresses and outputs. If no programmable chip selects are involved. make no
entry. Chip selects are numbered from 1 up; they do not start with zero.

4. Each ROM address is entered in decimal form together with the output word in binary form starting at Address zero and ending at
Address n -1. where n is the total number of addresses (output words). Leading zeroS must be entered.
Use:
AXX for 0 to 63 addresses
AXXX for 0 to 511 addresses
AXXXX for 0 to 1023 addresses
AI/ addresses must be programmed.

5. Begin the output word 2 spaces after the address. The least significant output bit (b,) is entered on the right. This is the logic state of
output 1 for a given address. The most significant output bit (b4. bS. or b12) is entered on the left corresponding to the logic state of
the highest order.output. The same logic definition must be used for outputs as with address and chip selects (enables).
6. The total number of "'" bits in the output word is entered one space after the output word. Leading zeroS must be entered for
ROMs with 12 outputs. This is for error checking.
7. The total number of "1" bits in each output bit position (column) is entered. Leading zeros must be entered. Four digits are shown
for 1024 addresses r but only 3 are necessary for 512 addresses, and only 2 are necessary for 64 addresses.

4·9

STANDARD FORMAT FOR> 1k WORDS

("1" or "0")
A punch =
logic (POS or NEG)
This is
Chip select information if applicable

The binary complement paper tape format shown in
figure 6 is the only standard format used with ROMs
having more than 1024 addresses (output words). The
preparation and handling burden of long paper tapes and
large quantities of punched cards is reduced with this
format as compared to the standard MPS format. It is
imperative that complete order information be submitted with the paper tape! In addition, the following
information should be written on the tape as a safety
precaution to avoid the problem of the tape getting
separated from the order information.
Company Name
NSC Part No.

'" l

r------~:------_,

As shown in figure 6, the tape has nothing on it except
a RUBOUT character to indicate the start and the data.
There are two words of data per address: first the actual
data followed immediately by the complement of
the data. For example, the figure shows word 0 as
11111100 (LSB on the right, a punch equals a "1 ") and
its complement immediately following it as 00000011.

. . . . . . : : . . . . : . . . «"

o0
o0

r--------::------,_BITI

0
0

...

OMS!i!!1

OM7415J

.----

~r---

1
OM1415J

f--<>

-I--

f--<>
f--<>

'---

r---

WORD

OM1I591

.--r--

INSTRUCTION
REGISTER
INPUT

f--<>

..-r--

OM741S3

'---

.---OM8S91

OM7415J

f--<>
f--<>
f--<>

f--<>
f--<>
f--<>
f--<>

,----

OMI59I

t----o
t----o
t----o
f--<>

'---

~fll:

MAJOR!
CYCLE
TIMING
DATA!
INPUT

I------<>
I------<>

SUB T~~~~~ (

FIGURE 5.

INSTRUCTION
CODE INPUT

lIMING
COOEINPUT

Or'
Ot--<·
Ot--<·
Or'
FIGURE 6.

4-18

28·BITOUlPUTWORO

OUTPUT
CONTROL

waRD

I20-BI1
WORD)

CLOCK

FIGURE 7.

FIGURE 8.

4·19

lem. The input control code is 14-bits wide and
the output control word is 28-bits wide, Figure 9.
This means that we would use four PLA's to
generate the decoder solution if none of the packages required more than 96 partial product terms.
In our example assume that there are four output
codes which have 90 partial product solutions
without considering the terms required by the
four other output terminals of the PLA under
question.

Note that the state diagram Figure 8 shows that
the maximum time interval X is checked to be
greater than the present value of the A elapsed
time counter. If this is true, the state counter
indexes to the next machine state (state B). The
output data transmitted to the holding memory
(DM8551 's in Figure 7) will be changed with every
state step in the system. The four packages of
holding memories are used to store the control
information for the traffic indicators. The memories
(DM8551 's) are sequentially updated by using the
same scan decoder which is used as a multiplex
decode of remote traffic counters (DM85L54's).

The initial thought about solving this problem,
would suggest the use of an additional PLA with
inputs and outputs connected together to obtain
the extra product terms. Since the four PLA's
have a total of 32 outputs and only 28 are required,
the 4 unused additional outputs may be coupled
from a second PLA to the PLA which first contained the 4 high usage partial product groups of
terms (Figure 9).

The control coding developed allows a state
interval to be shortened because one of the cross
streets has detected on coming traffic. Also, the
state interval can be lengthened if no cross or left
turn traffic is detected. As the sequencer steps from
state to state the other state conditions are tested.
In other words, while in state B state conditions for
A, C and D are tested for the necessary conditions
which might modify the timing of state 8. The four
traffic counters which are shown in Figure 7 as
DM8554 elements are multiplexed sequentially into
the PLA sequencer controller where they are logically "ANDed" with present state timing. Using this
information the sequencer period is modulated per
the equations defined by the state equations.

lNPl.>T
ADDRESS
GROUP

It should be noted that the sequence order need
not be orderly. The sequence of states through a
complete cycle may have repeat intervals or jump
commands in any step within the vastly variable
complete sequence loop. There is no special require·
ment that the sequencer be designed with order in
mind if some sort of disorder will yield an improvement in performance. The performance advantage
may relateto a dynamic performance improvement
or it may relate to a cost performance improvement. Generally a cost improvement results when
fewer parts are required in the overall solution.

OUTPUT
CONTROL

CODe

(2QOUTPUTSl

FIGURE 9.

DESIGNING WITH A PLA
How should a PLA solution be developed? An
orderly approach to the solution is necessary when
the control word is wide and complex in form. The
following techniques may be of some help in
determining the decode combinations when using
a PLA solution.

Doing this allows half of the partial product terms
to be placed in each of two separate PLA's. PLA's
can be connected with common inputs and common
outputs. It should be noted that the output code
for the common terms must be programmed using
a negative true logic for, since this permits "wire·
OR'ing" the outputs. This very significant design
possibility would not be allowed if standard ROM
techniques are used.

1. List all input control codes which are required
for each output.
2. Reduce this list logically to minimize the number
of partial product terms.

This interesting observation shows that memory
expansion for this product (PLA) is different than
other memory elements. The normal Read Only
Memory (ROM) or Random Access Memory (RAM)
elements have ch ip select inputs wh ich must be
decoded and selected before the package is actio
vated. When these types of memories are expanded,
additional decoder logic elements are required to
select the proper memory array Figure 4. In case
where there are more than one output terminal,

3. Combine similar terms which may be used on
more than one output terminals.
4. Group outputs which can share the largest per·
centage of the same partial product terms.
There are some additional considerations with the
general solution. Let's assume the following prob-

4-20

it is necessary to activate the entire package group
and therefore an entire memory word must be
used for the address.

CONCLUSION
The two example applications, that of the control
decoder within the digital processor and the traffic
light sequencer, show the economic advantages of
using the PLA because a reduction in circuit
complexity and quantity results. The processor
example application results also in an improve·
ment in dynamic performance. Additionally both
of these examples have a convenience of design
which allows the system's work function to be
modified without changing the overall system.
Only a change of PLA programming need be
accomplished to change the function of the decoder
or controller system.

Neither of these conditions are necessary for the
PLA. If the partial product does not exist as a
decoder or programmed condition, the outputs do
not change but if that product term does exist the
outputs respond to the solution. In the PLA case
it is possible for anyone or combination of outputs
to be selected from different but mutually con·
nected packages (Figure 9). This element technique
of grouping common control codes can simplify the
solution. The technique may be used with multiple
outputs to any degree which can prove economically
efficient to the system design.

There are many more design ideas which will
become apparent within your system when the
PLA is applied to the system design. More design
flexibility than that available with the ROM or
random logic design can be achieved with the appli·
cation of PLA elements to the system. The overall
result will be more logic function per system
dollar.

This last technique is a variation of items 3 and 4
in the design suggestions listed earlier. Utilization
of this technique can result in significant improve·
ments in memory storage efficiencies when com·
pared different PLA solutions.

4·21

Section 5

PROMs and EPROMs
Field Programmable Read Only Memory has made a
remarkable impact upon the art of logic design. Not
many years ago the instruction sets of minicomputers
were defined in combinatorial logic; today such defini·
tion is accomplished with PROM in microcode. The
practical application of microprocessors could not be
possible without EPROM. Because the in·circuit
function, aside from speed considerations, is exactly the
same for PROM and EPROM, the two are combined
in this section. It may pay to occasionally remind oneself
that MOS EPROM can do logic functions and that
bipolar PROM is quite usable as microprocessor instruction store.

A Guide to Implementing
Logic Functions
Using PROMS

National Semiconductor
Application Note
C. Mitchell
November 1977

"The cost per bit of read only memory has declined to
the point where ROMs or PROMs are competitive with
gates." Most of us have heard th is statement accompan ied
by estimates of the number of bits equivalent to a gate.
These statements and estimates are only valid if efficient
use is made of the memory. Efficiency of use is defined
as the number of memory bits used to realize a function
compared to the number of bits available. This applica·
tion note intends to illustrate some techniques which
allow the designer to achieve this efficiency.

Efficiencies may drop dramatically if MSI replacement
occurs. An analysis shows that if the circuit depicted in
figure 10, using a lk PROM, replaces the conventional
MSI/gate solution with equal component cost. the
PROM need only be used at 1.56% efficiency or better.
A PROM can be considered as an array of gates. Figure 1
depicts a 2NxM PROM as such an array. Using a 1024x4
device as an example, there are N (10) inputs to the
array. Each of these is routed to 2N (1024) AN D gates
with selectable true or false inputs. All of the AND
gates provide inputs to each of M (4) OR gates with
selectable true or false inputs. Other visualizations
include diode arrays driven by decoders and sensed
through multiplexers (figure 2).

No attempt will be made to derive relative costs of
package counts using gates versus read only devices
based on testing, insertion, and printed circuit board
area overhead. Current costs of PROMs, disregarding
these factors, can be directly compared to those of gates.
Such a comparison shows that bipolar PROMs can be
used at very low efficiencies and can be extremely com·
petitive. The following table reflects efficiencies required
based solely on purchase price.

Regardless of the technique of description, the end
result is the same: for any specific combination of
inputs each of the outputs may be assigned a logic state.

Table I. Efficiencyl Required in PROM Use to Effect Cost-

Effective Replacement of Gate Solutions
AO

PROM Size
256
1024
2048
4096

bits
bits
bits
bits

Efficiency

10-15%
4-6 %
3-5 %
4-6 %2

Notes:
1. Percent efficiency has been calculated based on gate equivalencies of PROMs.
2. As production experience is gained, efficiencies required for
replacement will decrease.

OUTPUT

Figure 2. Read Only Device Portrayed as a Diode Array

ZN, N INPUT
AND GATES

M,2 N INPUT

OR GATES

MOUTPUTS

Figure 1. Visualization of a 2 N -Word by M-Bit PROM

5-1

Combinatorial Logic
one state should the input glitch high during the active
state of the clock); second, in a system with feedback
the clock strobe must be of shorter duration than the
quickest propagation delay of the system. In an edge
triggered design clock pulse width is not a critical
parameter.

When replacing combinatorial logic with PROM, two
factors must be kept in mind. First, recognize the prime
implicants of the equation. Too often an original design
has been accomplished with a gate solution and a hasty
retrofit is attempted. Unnecessary complexity may be
added because the entire system has not been considered.
The signals, which in a gate realization must be present,
may not be important or even advisable when using a
PROM. In a gate design, for example, logic signals A·B,
A.B, and A+B may be present; only A and Bare
required with a PROM. Second, recognize "don't care"
situations. "Don't care" states often exist in machines
with multiple operating modes. For example, mode one
may require signals A and B, and mode 2 may require
A and C. In many systems, it is possible to pack these
various states using two levels of PROM and thereby
reduce end cost (figure 3).

Figure 4b depicts a divide·by-N sequencer/counter.
PROM output 01 determines N. 01 is normally high,
allowing the counter to count successively. At address
(counter output) N-1, 01 is programmed to be a zero.
On the next rising clock edge the counter is cleared, 01
goes high, and the sequence repeats. The other outputs

1,-......__....___--1

l------r--,
CONTROL
OUTPUTS

)

Figure 4a. _Controller Using Asynchronous Device
8.

Single Level Implementation

B...2.LJ'
~

SIb'
PROM

c~~

\d
M

DM74LSI6J
32d
PROM

~---I

PROM

CONTROL
) OUTPUTS

1,-----1

Figure 4b. Controller Using Synchronous Device

b. Two Level "Packing"
Figure 3. Reducing Memory Size by Recognizing Don't Care
States

are used to drive the control inputs to logic devices.
If these control inputs are synchronous or "gated 0"
inputs (similar to the clear input on the OM74LS163),
the system clock (fs ) need never be gated through other
devices. This is a feature greatly desired. An ungated
clock is one without slivers and also one without
clock-derived races. Figure 5 shows a circuit using a
gated 0 component and the sequencer /cou nter of the
previous diagram.

The outputs of the 512x4 PROM in figure 3b may be
a packed code which does not contain the specific
desired output signals, but due to the encription allows
a significant reduction of the number of memory cells
required. Generally, the more complex the system, the
more cost-effective this technique becomes.
Synchronous Logic
In most clocked systems it is preferred that clocked
devices be edge sensitive and fully synchronous. Note
that in figures 4a and 4b the asynchronously cleared
counter (OM74LS161) required an extra gate and flipflop over the fully synchronous part (OM74LS163).

CLR

The need for synchronous components is basic. PROM
outputs are the result of possible non-simultaneous
arrival of address bits and unequal propagation delays
through the PROM. This can result in output glitching.
When (as in most synchronous parts) the input data
need be valid for only a short interval prior to the rising
clock edge, glitches following the clock transition are
an allowable condition_ Level sensitive components are
avoided for two reasons: first, many level sensitive
devices are "ones catching" (Le., they will assume a

DM74LS173
INPUT
ENABLE

L->______-'

I, _ _ _~~--------...J

Figure 5. Gated 0 Control

5-2

Notice that although the clock is ungated the DM74 LS173
need capture data only during the state(s) determined by
the contents of the PROM and retains the data until
next enabled.

Obvious variations exist in the preceding concepts. Some
examples are shown in figures 9 through 11.

Naturally, the inputs of an unclocked device may be
controlled through the PROM outputs. Figure 6 depicts
a multiplexer in the data path.

EXTERNAL
CONDITIONS

DATAl ~

< r<
LD

~ DATA2

CLR

DM74LS163

PROM

")---+

CONTROL

" ----~------------------~
CLOCKED
DATA OUT

Figure 6. Sequencer Controlling Clocked & Unclocked Devices

So far the PROM has done little more than could be
accomplished through the use of a gate package or two.
Suppose, however, we provide the PROM with the
capability to sense external conditions and allow it
to determine the starting point in the count sequence by
controlling the preset and data inputs of the DM74LS163
(figure 7).

Figure 9. Control Sequence Determined by External Conditions

a-BIT
SHIFT
REGISTER

~:K

Oc
00
0,

PROM

Os
OH

L - . _.....

Figure 10. 256-5tate Controller Using Shift Register & PROM

EXTERNAL
INPUTS

Figure 7. Determination of Next State Using External Inputs

At this point we may eliminate the count function, as
the next state in the sequence may be determined by
the PROM through a register (figure 8).
CONTROL
OUTPUTS

TOGGLING QA AT ADDRESS N ALLOWS
OPERATION ON CLOCK EOGE N+Y.

Figure 11. Operation on Either Clock Edge

Figure 8. Elimination of the Counter

5-3

Speed Considerations

generally preferred.) PROM output data is loaded into
the latch which in turn drives the control output. While
the functions under the control of the latch are being
performed, a new address is accessing the PROM.
Address information is changed at the same time data is
loaded to the latch; therefore, system operation overlaps
in time with PROM access. Obviously, care must be
taken if next state information is to be provided. Two
possible pipelined configurations are shown in figures
12a and 12b.

The maximum clock speed at which these examples can
operate is easily determined. The minimum allowable
clock period is equal to the sum of the worst case
propagation delays around the feedback loop or through
the path under control, whichever is greater. Consider
figure 10 as an example. The loop delay is equal to the
sum of the clock·to-output delay of the sh ift register,
the propagation delay of the PROM, and the setup time
of the DM74LS164 data input. For this case,

tPHL(164) + tAA + tSETUP(164),

Further advantages in speed may be achieved by paralleling PROMs through a multiplexing arrangement.

where tAA is the address access time of the PROM.
Using a DM74S387 256x4 PROM, f smax becomes
more than 9 MHz. Careful attention should be paid to
all AC electrical characteristics when designing for
maximum speed. One parameter of special importance
(in addition to those already mentioned) is data hold
time. This should seldom, if ever, be a problem, but the
designer should make sure that the hold time of the
clocked component is significantly less than the typical
propagation delay of the PROM.

The use of PROMs to realize logic functions can be
beneficial to the system designer from a number of
points of view. Some of these are:
- component count reduction
- design flexibility
- power budget economy
- device standardization

In some systems the apparent speed of a PROM can be
enhanced by using a technique known as pipelining.
Pipelining is generally achieved through the use of a
memory data latch. (Edge triggered registers are occasion·
ally used here, but the fast fall-through time of a latch is

The limit of logic implementation with PROMs has, by
no means, been explored to great lengths in this note.
Thousands of useful, cost-effective designs have yet to
be uncovered. Hopefully, this discourse will provide
some impetus to the reader's own creativity.

Conclusion

ADDRESS
COUNTER

~J-jr:::l\_.
/[~J
~I\O/\
~R

."-"

jDUTPUTS

tPW«tAA

Figure 12a. PROM Pipelining Configuration #1
DM855J
TRI.sTATE
110 LATCH

ADDRESS

DATA RELATES

CONTROL
OUTPUTS

TDtlOCK EDGE

fs&ROM
ODCONTROl

~OU~~~%-----,

Figure 12b. PROM Pipelining Configuration #2

5-4

National Semiconductor
Dom Richiuso**

MOS Encoder Plus PROM
Yield Quick Turnaround
Keyboard Systems *

INTRODUCTION
programmed key cndes is received. In addition, the
usefulness of being able to reassign key codes quickly
in the PROM makes system debugging and alteration
an easy task.

Most modern keyboard designs employ MaS/LSI key·
board encoder Ie's to implement all the necessary
electronic functions. The key codes specified by the
customer are programmed into a read only memory
which is an inherent part of the encoder. Although some
common encoder formats are available off the shelf, such
as ASR33 teletype (MM5740AAE or MM5740AAFl,
there are many instances where variations of common
formats are needed. Since these formats are mask
programmed into the keyboard encoder, there is a certain
amount of lead time (approximately 12 weeks) before a

The basic configuration for this implementation is shown
in the simplified block diagram of Figure I. The key
switches and all timing signals are configured in the
normal manner. The keyboard encoder chip will emit
binary codes for each valid keyswitch closure. These
binary outputs are used as addresses for the PROM
which is programmed with the desired actual code for
each keyswitch. Each key closure is transformed first
to an address by the encoder and then to the final code
by the PROM. In this manner, a general design is
possible, with the only variable being the contents of
the PROM which is easily and quickly programmed.
When changes are necessary, the PROM may be erased
and reprogrammed quickly making it an easy task to
finalize design alterations.

customer receives his tinal circuit.

By using a binary coded keyboard encoder in conjunction
with a programmable read only memory, customers can
build prototype keyboard systems or fill small volume
orders in minimum time. This approach keeps
all the encoding electronics and timing the same as in
the final system, so that a minimum of redesign is
necessary to configure the actual final version. This is
done when the keyboard encoder with the final mask

KEY

~
KEYBOARD
ENCODER

SWITCH
MATRIX

BINARY
OUTPUTS

~lKEYCODE

ADDRESS
INPUTS ~

f--+

FIGURE 1. Simplified Block Diagram

*REFERENCE: AN·80 MOS Keyboard Encoding by Dam Richiusa
**Refer to Introduction.

5-5

OUTPUTS

KEYBOARD IMPLEMENTATION

A typical implementation of this approach is shown in
Figure 2. The encoder employs a dynamic scanning
technique to identify key closures. Each keyswitch is

defined by a particular X drive Iine and Y sense line of
the encoder. In addition to the basic operation of translating a switch closure to a coded output, the MM5740

:}'M
4:'M

M.-+,

11 15
2
18
KBM DE VLL VGG

12 X,

,'v
GNO

I, T. I"

J2
v~

,
•
,
6

•

"
B1~

.. f!!--

B2~A7

B3 --.,;,.;, A6

B4~A5

89.!............! A4

.. f!!---+
f!!--+
f!!---+.

MM5204

B5~A3

X,
MM5140AAC
OR
MM5740AAO

• X,

Z2 Y,u
23 Y,
24 Y2

Bl~A8

11 X 2

.
2

86~A2

87~AT

88~AD

K' Y

co DE
DO TPUTS

26 Y4
27 Y5

os~

29 V7

30 VB
31 Vg

elK

---,++
tk

S60k

....

=i='P't

LM555 3

i
;!:-

rW,
lM555

SHIFTlK 20
SHIFT CONTROL
21
19

RPT

'.0

~16

~~
10Hz

DATA STROBE

OSC 14

Jr-

K~'

SHIFT

CONTROL

SHIFT
R

r"' .I?=t

1
-!

'"
Y ~

'5V

Note 1: N·lley rollover-MM5140AAC
2·key roll,",r -MM5740AAD
NoteZ:
Notel:
Note 4:
NoteS:
Notl6:

CID~kfrvquencv" lDOkHl.
SllImcyde= 9011p •.
Repeat nte = 10 eharacmB per second.
K bCMI12mi1sktime=4ms.
Dltastroln=IGtApu".

FIGURE 2. Typical Keyboard System

5-6

SHIFT
LOCK

r--l

v~
I

(Q)

12V
'-.:_.J
40mA

CM2·137t

.k-

EN22!2

,,.
~
-Tlv

provides all the functions necessary for modern keyboard
system design. This includes all the logic necessary for
key validation. 2-key or N-key rollover, bounce masking,
mode selection and strobe generation. Table I illustrates
the relationship between keyswitch matrix position, key
mode and the binary coded outputs of the MM5740 AAC
or AAD encoder. The AAC version provides for N-key
rollover while the AAD is a 2-key rollover encoder.
Since there are nine X lines, ten Y lines and four modes,
360 nine-bit codes are possible.

the PROM, it should be noted that the MM5740 uses
a bit paired coding system. Any particular key will have
5 common bits (B 1, B2, B3, B4, B9) and 4 variable
bits (B5, B6, B7, B8) which may change when going
from one mode to another. In addition, encoder coding
is specified in terms of negative logic so that it may be
necessary to complement positive logic PROM contents
when ordering encoder masks.

By careful PC board layout, the encoder/PROM prototyping system can utilize the same PC board as the final
system with the PROM removed. This can be accompi ished by arranging the traces so that it is possible to
provide jumpers from the encoder outputs to the PROM
outputs. Utilizing this approach allows for a minimum
of tooling, parts counts and quick turnaround time for
new designs.

In the general application using 90 four mode keys, a 4k
PROM (MM5204) should be used. If less than 64 fourmode keys are all that is required, a 2k PROM (MM5203)
may be substituted. I n this case, the most significant
bit (B 1) from the encoder is dropped and Table I
addresses would go from 0-255. When programming

TABLE I. Encoder/PROM Mapping

ADDRESSES
(ENCODER OUTPUT)

KEY CODE OUTPUTS
(PROM CONTENTS)

B1 B2 B3 B4 B9 B5 B6 B7 B8

B7 B6 B5 B4 B3 B2 B1 BO

KEY POSITION
MODE
X

1
1
1

1
2
2

Shift
Control
Shift Control

9
9
9
9

10
10
10
10

Shift
Control
Shift Control

Unshift
Shift
Control
Shift Control
Unshift

Unshitt

0
0
0
0
0
0
0
0

1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0

0
0
0

0
0
0
0
0

1
1
1
1

*Encoder outputs are listed in positive true logic notation.

5-7

0
0

0
0
0

0
0
0
0
0

0
0

0
0
0

1
1

0
0
0
0

1
1

0
0
0
0

0
0
0
0
1
1

1
0
0

0
0

0
1
0
1
0

1
1

0
0

USER
DEFINED
KEY
CODES

TABLE II. Truth Table
MM5740/AAC or MM5740/AAD
MATRIX
ADDRESS
1
1
1
1
1
1
1
1
1
1

1
2
3

•

2
2

5
6
7
8
9
10
1
2
3

2
2

5
6
7
8
9
10
1
2
3

2
2

3
3
3
3
3
3
3
3
3
3

•
4

•

5
6
7
8
9
10
1
2
3

•
••• •
••
9
••
5
6
7
8

5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7

7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9

10
1
2

•
5
6
7

8
9
10
1
2
3
4

5
6
7
8
9
10
1
2

•

5
6
7
8
9
10
1
2

3
4
5
6
7

8
9
10
1
2
3
4
5

6
7
8
9
10

COMMON
82

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

0
0
0
0
0

0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1

1
1

1
0

a
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

a
0
0
0
0
0

a
a

SHIFT

UNSHIFT

1
1
0
0
0
0
0
0
0
0
1

1
1
1
1
1
1
1
0
0
0
0

a
0
0
0
1
1
1
1
1
1
1
1
0
0

0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0

0
1
1

1
1
0
0
0
0
1
1
1
1

0
0
0
0
1
1
1

1
0
0

a
a
1
1
1
1
0
0
0
0
1
1

1
0
0
1

1
0
0
1
1

0
0
1
1

0
0
1
1
0
0
1
1
0

SHIFT CONTROL

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
1

1
1
1
1
1
1

0
0
1
1
0
0
1

1
0
0

0
1
0
1
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0

0
1
0
1
0
1
0
1

1
1

1
1
1
1
1
1
1

1
0
1

1
1
1
1
1
1
1

1
1

1
0

CONTROL

0
0
1
1

0
0
1
1
0
0
1
1
0
0
1

1
0

0
1
0
1

1
1
0
0
1
1

1
1

0
0
1
1
0
0
1
1

5-8

0
1
0
1
0
1
0
1
0

a
a

*NEGATIVE lOGIC NOTATION °T" '" -. "0" = +

0
1

a
1

0
1
0
1
0
1
0
1
0
1

1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1

1
0

1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1

0
0
1
1

1
0
0
1
1

a
1
1

a
a

0
0
0
0
0
0
0
0
0
0

1
1
0
0
1
1
0
0
1
1

0
1

0
1
0
1
0
1
0
1

a
1
0
1
0
1

a
1
0

a
0

a
0
0
0
0
0
0
0
0
0

a
0
0
0
0
0

1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

a
0
1
1
0
0
1
1

a
a
1
1
0
0
1
1

1
1

0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0

a
0

a
0
0
0

a
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

a
0
0
0
0
0
0
0
0
0
0
0
0
0

a
0

National Semiconductor
Jonathan Stinehelfer*

PROM Power-Down Circuits

description
Inexpensive bipolar PROMs can be used in high performance, low power applications if powered down when
they are not being accessed. Since the access time of the
circuit of Figure 1 is less than 80 nanoseconds, the
power saving can be greater than 10 to 1 if cycled every
microsecond. Longer cycle times, or decoding of the
power switching to multiple packages, can yield even

system cycle. Turning the PROM off when it is not
needed saves power and the access time is increased
by only the delay of the power down circuit.
The basic power down circuit is illustrated in Figure 2.
A TTL level input signal drives the TTL logic input of
the power down circuit. The logic input is drawn as a
non inverting buffer; however, circuit operation is not
limited to noninverting buffers. Logic Table 1 illustrates
several logic implementations of both inverting and
noninverting inputs with different speed-power tradeoffs.

more impressive ratios.

8ipolar PROMs with on-chip power-down have power-up
to power-down ratios of 3:1. Using the PROM powerdown technique illustrated in Figure 1, ratios considerably higher than 3:1 can be obtained. National's PROMs
perform well in this application. With power removed,
the Tri-State® parts revert quickly to the third (open
high Z) state. Because there are no clamp diodes from
the outputs to V cc, the powered down device presents
only leakage to the output bus.

Circuit operation is as follows. When the logic input to
R2 goes low, base drive is supplied to the PNP switch,
turning the switch on. C, is a speed-up capacitor which
decreases the switching time of the PNP switch. In
applications where high speed is not important C, is
not necessary. When the PNP saturating switch is on
Vcc (+5 V) is applied to the PROM. The time delay
from power up command to power up on the PROM
ranges from about 10 ns to 100 ns, depending upon the
PNP switch and the TTL logic driving the switch .

PROMs do not need to be continuously powered in
many applications. Often data is required from a PROM
on system power up or for a small percentage of a

1JlJfJ

820n

TllEVEl

....---1----.------------5 V

INPUT SIGNAL
(ACTIVE lOW)

O.2f..1F

PASS TRANSISTOR
PN431J or 2N3467
4

....-..I-',::,::,,_ _-,-,OUTPUT

IT1iT2l
fii7lEVEl
U
U INPUT SIGNAL

100 pF
DM74S281

Figure 1. PROM Power Down Circuit

Figure 2. PROM Power Down Circuit

*Refer to Introduction.

5-9

We are now ready to calculate the value of resistor R2.
Resistor R2 is used to limit the base drive current of
the PNP 2N3467 transistor. The value of R2 is calculated
from the voltage across R2 and the base current required
to supply the Icc current required for the PROM.

logic table

~
~

Resistor calculation:
I

vce

cs=D74S00

•

74lS00

Active High Selects
74S00 Speed
74LSOO Speed and Low Power

RI
IB

I
I
I
I

VOL

I
I
I
I

• Fast

cs-l>-l>14S04

74lS04

• Active Low Selects
74S04 Speed Only
74LS04 Speed and Low Power

IB=

~ • Active Low Selects
MM74C9D2
Buffers can be connected in
parallel for additional current

r:.

MM74C42

IJOmAMAX
FOR PROM

DRIVING THE
PNP SWITCH

• Very Low Power

2NJ467

vBE SAT' I VMAX

TTl OUTPUT
OF LOGIC CIRCUIT

cs ----"---~

1110
~I - -DECODER
----lIO

vce

I
I
I

• Fast

130 mA = Icc
hie = 40

3.25 mA

min

Base current calculation:
Vce - (VBE(SAT) + VOLlMAX))
R2 = - - - - - - - - - VBEISAT)
IB+--R, = 820

I. Very Low Power
• Memory Expansion
• No Resistors Required
Rl and R2, Figure 2, not
required

R2=

5 - (1 +0.5) V
(3.25 + 1.0) mA

R2=~=823n
4.25mA

design example

R2 = 820 n, rounding to the nearest standard value.

Design a minimum power memory that has a 200 ns
access time, a 1000 ns cycle time, and a 256x8 memory.

R, is chosen to be equal to the R2to simplify the parts
list and this allows resistor packs (8 identical resistors
in a 16·pin package) to be used when appropriate.

Two DM74S287 PROMs will be used for the 256x8
memory. DM74S287s have a ± 5% power supply toler·
ance. Since there will be about a 0.2 V drop across the
PNP switch we need to ensure that the Vcc requirement
of the PROM is met.

Figure 3A is the final circuit for the 256 x 8 memory.
Performance of the 256x8 power down memory is:
Power when selected 1345 mW max
Power when deselected 0 mW with 74C902 buffer
Access time 180 ns max

Since speed is not of prime importance in this application
we will select "slow" low power parts in the power
down circuit. The 74C902 noninverting buffer will be
used as the logic input device. This device is selected for
its low power. 2N3467 PNP switch will be used as the
pass transistor.

Average power is a function of duty cycle, and for
our 256x8 power down example average power is:
P
= on time
ave(max) off time

From the data sheets:
2N3467 PNP Saturating Switch
VCEISATI
Ic = 150 mA typ = 0.165 max = 0.3
hie
IC = 150 mA typ = 120
min = 40
VBEISATI
IC = 150 rnA typ = 0.8
max = 1 V
DM74S287 PROM
Icc = 80 mA typ, 130 mA max
74C902 Buffer
Icc=15f.1Amax

Power max = 200 ns . (665) (2)
1000 ns

1
Pavelmax) = -(1330) = 265 mW max
5

The 265 mW assumes that all parts are maximum at
the same time. The more likely situation is that parts
will be at or near their typical value.
For our example:
1
Paveltyp) =-(830) = 166 mW avetyp
5
5·10

VCC

Rl
820n

SELECT

---I zoo \ "H"

800 _ _ \

L.:r

EMORY

ENABLE
SIGNAL

TTL T'

_ _ 118ons
MAX

Figure 3A. 256x8 Power Down Memory

Vcc

1/674C902

1/674C90Z

Figure 3B.

VCC

1/674C902

Figure 3e.

5-11

Cz O.2MF

VCC

C2 O.2pF

1/3 74C902

SELECT
Figure

3~.

resistor

performance table

RAOB
16

Typ
Access Time Max
74C902 Buffer
2N3467 PNP Switch
74S287 PROM

Power Selected
Is 2N3467
74C902
74S287 at 5 V, 6.65 mW each

54 ns
20 ns
35 ns
--109 ns

Max

90 ns
40 ns
50 ns

---

180 ns

•

TOP VIEW

15mW

buffer

-1330 mW

MM54C9D2/MM74C902
MM54C904/MM74C904

Vee

1345 mW
Power Unselected
Is 2N3467
74C902
74S287

o (leakage)
o (75fJ.W)
0
OmW
TOP VIEW

GND

3B since the base current for the 2N3467 will be at least
9 mA, and typically will be higher. This adds some
power dissipation when the PROMs are powered up.

Figure 3B illustrates a circuit simplification of removing
R1 (the Ib2 resistor). Eliminating R1 saves a resistor and
the power dissipated by the resistor. R2 still determines
the base drive current which is V fR. This circuit will be
slightly slower than the circuits in figures 3A or 3C.

Figure 3D represents a minimum part count circuit for
the 256x8 PROM memory.
This application note illustrates several ways to power
down National's Schottky TRI-STATE® PROMs.
Powering down PROMs is a cost-effective method for
obtaining low power and fast access time.

Figure 3C illustrates a further reduction in the number
of resistors. Neither R1 nor R2 i~ used. Speed will be
good and power will be higher than in figures 3A or

5-12

National Semiconductor
Application Note AN-1a9
Fran Terry*
Keith Winter
July 1977

A PROM Programmer
for the SC/MP LCOS

ABSTRACT

Loading an LM Tape and Programming

This application note describes for the user of the
SC/MP Low Cost Development System (LCDS) a
method of programming MM5204 or MM4204 Programmable Read Only Memories (PROMs) that is both
inexpensive and highly efficient.

-L1000 CR
(CR ~ carriage return)

Load tape into memory starting
at address X'1000.

-GO CR

A fter tape loads, the user transfers to programmer software.

?Pl000 CR

Check PROM for erased condition, then program from X'l 000.

?Vl000 CR

Verify PROM against memory.

INTRODUCTION
In the development cycle, there is a point in software
development between read/write memory program
debug and commitment to mask programmed ROMs.
This is generally filled by using erasable PROMs; this
allows the user to test the program in the end application, and then to correct any errors that occur. Also,
for the small quantity user, ill the end application
PROMs may be more practical to use instead of ROMs
This can be inconvenient, however, if a PROM programmer is not readily available.

Ready for next command.
NOTE
The PROM is now programmed. Pressing the
HALT button returns to the DEBUG monitor if
desired. The following examples show the initial
system state to be in DEBUG.
Duplicating a PROM
-GO CR

With the method described in this application note. the
LCDS user can construct, using wire-wrap techniques,
an inexpensive PROM programmer that plugs into the
SC/MP LCDS backplane and programs a 512-by-8
PROM in less than 10 seconds. The only additional item
required is a 65 V power supply capable of delivering
500mA.

Transfer to programmer routines.
Put PROM to be duplicated in
socket on programmer card.

?Cl000 CR

Copy PROM data into memory
starting at X'l 000_
Put blank PROM in socket.

CAPABI LI TI ES
The driver software has the ability to copy a PROM into
memory for subsequent duplication, to verify a PROM
against memory, to program a PROM from any memory
area, and to verify that a PROM is erased.

?Pl000 CR

Program PROM.

?Vl000 CR

Verify PROM.
Ready for next command.

Program PROM Without Check for Erased Condition
-GO CR

An added feature of the PROM programmer is an LED
that is active when the high voltage is being applied to
the PROM socket.

Transfer to programmer routines.
Put PROM in socket.

NOTE
Damage to the PROM and/or the programmer may
result if the PROM is inserted or removed when
the LED is turned on.

?Yl000 CR

Program PROM from X'1000
without check for erased.

?Vl000 CR

Verify PROM.
Ready for next command.

Checking PROM for Erased Condition

Listed in Appendix 1 are two versions of the driver software. If the user has a Teletype, the first program can
be used. If no Teletype is available, the second program
uses the LCDS control panel for all entries.

-GO CR

Transfer to programmer routines.
Put PROM in socket.

?E
EXAMPLES OF TELETYPE OPERATION

PROM is checked.
Ready for next command.

The Teletype@ (TTY) program works in conjunction
with the TTY DEBUG package contained on the LCDS
Motherboard. The following are some examples of TTY
operational routines; the user's read/write memory is
assumed to be located from X'1000 to X'17FF.

Listing Contents of a PROM"
-GO CR

Transfer to programmer routines.

?Cl000 CR

Copy PROM contents into
memory.

Put PROM in socket.

NOTE
The 65 V power supply should be turned on
throughout all of the following operations.

Press HALT button to transfer
to DEBUG routines.

(A dash H denotes a debug prompt, a question mark
[?] denotes a programmer prompt.)

-Tl000:llFF CR

"Refer to Introduction.

5-13

Type contents of buffer area.

Erro r Messages
If PROM cannot be programmed:
?P1000 CR
BAD PROM @OXXX

It is suggested that a low or zero insertion force socket
be used for the PROM to make insertion and removal
easier. This also reduces the possibility of bent pins
which can cause errors in programming or damage to the
part.

where OXXX denotes the address
of the PROM that cannot be
programmed

Three waveform photos are included to aid in verification and debug of the circuit. Photo 2 shows the programming pulse from the DM9334 addressable latch and
at pin 4 of the PROM. Photo 3 shows the voltage levels
of input data for both the logic "0" and logic "1" states.
Photo 4 shows the levels of V BB and V DO, All these
values are shown during the time of the programming
pulse.

If PROM is not erased:
?P1000 CR
NOT ERASED
or
?E
NOT ERASED
If PROM does not verify against memory:
?V1000 CR
NO VERIFY

PARTS LIST

EXAMPLES OF PANEL OPERATION
For panel operation, the user enters the starting address
of the routine to be executed into the Program Counter
and the address to be used for copying, verifying against,
or programming from into Pointer 1. After placing the
PROM in the socket, the RUN button is pressed. The
system halts when the operation is completed or if an
error is detected. The error halts and their explanations
follow:
X'0035
X'0085
X'015A

PROM is not erased.
PROM cannot be programmed.
PROM does not verify.

The following are entry points:
X'ODDl
X'DD35
X'DD48
X'D1Dl
X'012C

Check PROM for erased condition.
Program PROM without check for erased.
Program PROM with check for erased.
Copy PROM into memory.
Verify PROM against memory.

Type

Description

Quantity

DH3725CN
MM74C173
DM80C95N
CD4040N
DM8223N
DM8131N
DM8D9DN
DM9334N
NSL5026
2N4250
2N29D5
lN93
LM317T
RESISTORS

Quad Core Drivers
Quad Latch
Hex Tri-State Buffer
12-Stage Binary Counter
1-of-8 Decoder
6-Bit Bus Comparator
Miscellaneous Gates
Addressable Latch
LED
PNP Transistor
PNP Transistor
Germanium Diode
Voltage Regulator
May be Resistor Arrays

6
2
2

1
2
4
2

A suggested board for construction is National Semiconductor part no. IPC-16C/8Dl prototyping board.
However, any prototype board that has a 72-pin edge
connector on 0.100 inch centers (plug compatible with
the SC!MP LCDS busl and room for at least 32 16-pin
IC sockets can be substituted.

When using the panel program, the HALT INST switch
on the LCDS Motherboard must be in the DEBUG
position before execution. Other than the method of
inputting commands and parameters, the TTY program
and PANEL program are functionally identical.
Appendix 2 contains generalized flowcharts of the
PROM programmer software routines.

Each TTL and CMOS circuit should be bypassed by a
D.l!J.F capacitor across Vee and GND as well as bulk
capacitors across Vee and GND and -12V and GND at
the input to the board. These capacitors should be
tantalum and should be in the 2D!J.F to 30!J.F range.

These programs are intended to be assembled at X'OODD
so they can be placed in PROM on the SC!MP CPU
card. For the P-channel card, an MM52D4 is used. On
the N-channel card, an 87S296 bipolar PROM must be
used. If N-channel is used, the delay constants in the
programming routines must be doubled to allow the
correct timing for the programming pulses.

CONCLUSIONS
BOARD CONSTRUCTION

This PROM programmer greatly extends the use of the
SC/MP LCDS as a prototyping!development system by
giving the use; the ability to program PROMs for debug
and test purposes while remaining much less expensive
than commercially available PROM programmers. Also,
since it is to be used in the LCDS, no special formats for
the data are required. Load modules created by the
SC!MP LCDS can be loaded by the firmware provided
without conversion to binary, complemented binary, or
BPNF formats.

Referring to the schematic diagram, figures 1 and 2,
standard wire-wrap techniques are used in the construction of the board. Refer to photo 1 for a suggested
placement layout. This placement should be followed as
closely as possible, as the transistor drivers and their
associated passive components should be near the PROM
socket to reduce line inductance. The decoding and
control circuits are placed near the board edge connector
for access to the data and address buses.

5-14

LED

HIGH VOLTAGECONTROL CIRCUITRY

VOLTAGE
REGULATORS

INPUT DATALATCHES AND
ADDRESS COUNTER

-PROM DATA AND

ADDRESS DRIVERS

--OUTPUT DATA

PERIPHERAL DECODING
AND
CONTROL
CIRCUITRY

BUFFERS

Photo 1.

Top

GND

4BV
Bottom
+5V

GND
Photo 2. top:Vp@SV/DIV&200I's/DIV
bottom: Vp (PROM)@20V/DIV & 200l's/DIV

+60 V
4BV
Top

+5V

GND
37 V

GND

Bottom

GND
Photo 3. top: DATA "'O"'@ 20 V/DIV & 300 I's/DIV
bottom: DATA "1"@20V/DIV & 3001's/DIV

-12V
Photo 4. top: VBB@20V/DIV & 300l's/DIV
bottom: VDD@ 10 V/DIV & 300 I's/DIV

5·15

ABSOLUTE DEVICE ADDRESS;
X'BOOO - X'B3H

+5
AD15

AD14

AD13

I]>

B3
11

A012

OMB131

AD11

10
12

AD10
MEMSEl*

NRDS
NWDS

~
B090
LOP

ADO
ADl
AD2

[]»
43

CLOCK'

ol---RDP*

DM8223
13

B090
13

RESET

ENBL*

AD3
AD4

AD5

A2
13

BOO

INIT'

Figure 1.

5-16

VSS, VOD, VBB
RD

OM9334

VP
CS

.," I

VR'
lM31l

FROM 86 V. 500 mA
PDWERSUPflLY

ALL NPH TRANSISTORS
ARE DH3125

,..

ADI

.----

<5V

9
,.

8GBO

,.
,.~

2N42511

KZN4'5G

".,.

y
INI3

NSl&028q

.. JI

'DOn

Vas. Yoo. VB8

Q ....".

-_.

:----:1.
J.,'N" -

-12

....

;;;.3

iii
!"

lN~

lUU

'80
" }p
PROM SOCKET

CD4II4DCN

5·

•

" '80
" ,1"'.

Vaa

•,

.OUKs

100ICs

3,1K

3.1K

3,11

3.1K

1"
VDD

J.-

CLOCK·

80C95

IB'

,....!

•,

*
J

rrrf:

~nnnnnn~n

3.1K

"
•

'0 •

':'

.....

80C9S

~
""l

IZ'

~2NZ905

VDD

+5V~

rrt:'f:

.......--

':'

,;;'

tJ 1

':'

vahv

':'

VR'
LM311

15
1 M

RESET

Rr.lR~

~~~~
•

101

..
BD8

GND

-105

.804

3rii'

7
GI192

14en3

lOP

G,&Gz
GND

14Ct13

..
803

.. ...

aDZ

80'

800

Appendix 1

SC/t1P ASSEt'18LER RE'./-A
TT'T'PGt'l SC,.,"I'1F' PR0I1 PF.:OGF.:A~lNEP

, TITLE

TT'T'PGt1.,

SC/11P PF.:OI'l

PROGIi:AI1~lER

"TT'T'PGt1" I S A PROGRfl11 THAT AL.LOl,lS THE SC/~1P L.CDS TO
PROGRAN 1'11152134 OR t'1I1421<:14 PFWMS,

4
~

'-'

THE COI'1I'lAN[:oS AND THE I R FOF.:I'1ATS ARE:

::::

COP'T' PR0I1 I tHO MEMOR'T'

9
10
1i
12
13:

'./ERIF'T' PRON AGAINST 11E1'10R'.,o

VER I F'T' PROI'l I S ERASED

14
15

PROGRAt'l PROI'1 FROM t1E~10R'.,o
IHTH CHECK FOR EF:ASED

16
17

PROGRAN PIi:0I1 FROM t'lEI10R'.,o
~'H THOUT CHECK FOR EIi:ASED

19
20

21.
22
23

THE PROGRAI1 REG,UIRES THAT THERE ARE 512 CONTINUOUS t1EMOR'r'
LOCAT I ONS UP~~ARDS FIi:OI'l ~1,,"813013

W8JFF

W701313

~-:;'~7FFF

35
36
37

;

LOCAT IONS OCCUP I E[) 8'.,0
PROGRAMt1ER HARDWARE
LOCAT IONS USEe) 8'.,0 LCDS

A TELET'.,oPE IS REC!UIF:E[:o FOR EXECUTION,

5-18

ASSEMBLER REV-A
TTYPGM SC,...'MP PROM PROGRAMMER
POINTERS AND CONSTANTS
SC~MP

38
39
413 13131313
41
42
1313131
43
1313132
44
1313133
45
46
8131313
47
48
131314
49
0013C
513
1313134
51
13131C
52
121131313
53
1313131
54
1313132
55
56
1313133
57
1313134
58
59
7AE2
613
7A91
61
7B513
62
7B17
63
7BB3
64
77013
65
66
FFEF
67
FFEE
68
FFED
69
FFEC
713
FFEB
71
F:'FEA
72
FFE9

. PAGE

'POINTERS AND CONSTANTS'

. =13
P1
P2

1
2
3

PPRGMR

138131313

VP
RD
VSS

1314
13C
134
131C

.-.~

_.;;;)

LOAD
CLK
RDPRM

€I
1

CLR
ENBL

PUTC
GECHO
GHEX
MESG
PH EX
STACK

137AE2
137A91
137B513
137B17
137883
1377D13

HI
LO
SAVLO
SAVHI
HCNT
DPLO
DPHI

-17
-18
-19
-213
-21
-22
-23

5-19

; PERIPHERAL ADDR. OF PROM
; PROGRAMMER BOARD
.; ORDER CODE FOR PROG. VOLTAGE
; ORDER CODE FOR READ
; ORDER CODE FOR VSS, VBB., VDD
; ORDER CODE FOR CHIP SELECT
; ORDER CODE TO LOAD DATA
; ORDER CODE TO CLOCK COUNTER
; ORDER CODE TO READ PROM
; DATA
; ORDER CODE TO CLEAR COUNTER
; ORDER CODE TO ENABLE CONTROL
.; LATCH
; PUT CHARACTER POINTER
; GET CHARACTER W/ECHO POINTER
; POINTER TO GET 4 HEX DIGITS
; PO I NTER TO MESSAGE ROUTI NE
; POINTER TO PUT ·HEX ROUTINE
; STACK POINTER TO MOTHERBOARD
.; R~W MEMORY
; TEMPORARY LOCATIONS OFFSET
; FROM STACK POINTER

SC/~lP

tiSSH1BLEP PEV-A
TT'T'PGt-l Selt'lP PPOt-l PPOGI':At·1t·lEP
Cm1t1AND INPUT PPOCESS I NG

. PAGE

75
76

77
78 l':100l':1 08
79

***

COt-lt-lAND ENTPY ROUTINE

***

NOP
ENTF.:'T' :

80 \':1["):1 (:477
8:1 0003: 26
82 00\':14 C4D0
83:

... COt-lt'lAND INPUT PPOCESS I NG ...

(u:;)(16

.JS

P3:., t'lESG

,PPot'lPT FOP COt'lNAND

PI':t'lPT
F'J:) GECHO

.' GO TO GET CHAR

~3>:::188
i74 0g8C
:1.75 £11218E
i76 1211219121

:177 ~31391
:1.78 1211393
179
i8121
181
182
i83:
184
:185
186

1312195
1312196

13097
0099

£11219A
0£19C
13139E
1211219F
187 OOAl
:188 12I0A3:
189 01::1A5
190 (n3A7
191
192 121I21A9
19~; 013A8
:1.94
:1.95 I2II21AC
i96 1210AE
197 I2II21AF
i98 12112181
i99 12112183
2121121 012184
2121:1. 12112186
2[12 [11218::::

PF.:OG:
C478
3:7C4
4F3:3:
3F
C6>31
131
C601
CAED
41::1
CAEC
C43:A
31
3:D
C2ED
3:1
C2EC
F4£12

::::(5
C41211
CAEF
C4(1I::1
CAEE
C81213

P3 .. GHE:''';

LD
)<:AE
LD
ST
LDE
ST
LDI
XPAL
)";PPC
LD
:":PAL
LD
ADI
>O:PAH
LDI
ST
LDI
ST
ST

@i(P2)

; RETR I E··... E AC·DF.:.

FRot1 STACK

1]11. (P2)

SAVLO(P2)

;SAVE

F.~W

MEI'10RY

SA1·lH I (P2)
L ( EF.:ASED ) -1
P1
P:1.
SFI\.tLO(P2)
P1
SA',,"H I (P2::'

; CHECK PROM FOF.: ERASED

.; ADD 5:1.2 OFFSET

P1
1
HI (P2)
0

LO(P2)
CLR(P3)

.; SET UPPEF.: LOC COUNT
;SET LOWEF.: LaC COUNT
; CLEAR PROM COUNTER

N>~TLOC:

C5FF
[11

LD
>':AE

IE-1(P1)

; GET DATA TO PROGF.:At·l
; SAVE IN EXTENSION F.:EG.

L[)I

H(PPRot'l)
P1
SA'.,.'H I (P2)
L (PPF.:ot·!;'-l
P1
SAVLO(P2)

; SET ADDR

-2

.; SET COUNT
; SAVE HIT COUNT IN RAI'1

THSLOC:
C4>::11
3:5
CAEC
C42i
31
CAED
CAFE
CAEB

203
21214 1211218A
21215 12112188
206 1211218C
207 I2II21BE
208 1210CI2I
21219
2:1.£1 121121(:2
I2II21C4
",1121(:6
I2I121e8

SET:

.JS

~.::PAH

ST
LDI
XPAL
ST
LDI
ST

HCNT(P2)

PROGRAt1~1 I

NG F.:TN

.; SAVE PTR ADDF.:.

GO:
>(PPC
:":RE
.JZ
DLD
Jt·c

3D
6",1
9818
8AE8
9CF8

P1
.; CHECk: PRot1 DATA
OK
HCNHP2)

.. PRO,..l DATA

COR~:ECT,.

130

;DECF.:EI'1ENT HIT COUNT
.; CHECK FOR I'1A)·':. HIT

P3:,. t'lESG

; HIT COUNT OVER MAK.

DO X+5X

NPF.:OG:
C478
37C4
163:3:
3:F

.JS

5-22

8A[) PRot1

SC,.'MP ASSE~lBLER REV-A
TT'T'PGt1 SC,.'~lP PROM PROGRAt1t1ER
PROrl ACCESS AND PROGRAMt1 I NG ROUTINES
2:1..:1.. lZIeC9 e:1.DD
2:1..2
2:1..3 IOIOCB C4B2
2:1..4 IOIOCD 3:3:
215 IZIIOCE C2EF
2:1..6 IZIIODIO 3F
2:1..7 lZIeD:1.. C2EE
2:1..8 e(:C1[)3 102
2:1..9 IOIZID4 F4FF
2210 IOIZID6 3F
22:1.. IZI1OD7 9109£1
222
223 IZI1Z1D9 102
224 IZIIZ1DA C41Z11Z1
225 IZIIZ1DC CAE9
226 1C11C1DE FAEB
227 lZIeEe CAE8
228 lZIeE2 132
229 IZI1Z1E3 F2E8
2310 IZI1Z1E5 CAEA
23:1. lZIeE7 C4elZl
232 IZI1Z1E9 F2E9
233 IZI1Z1E8 CAE9
234 IZIIZ1ED 132
235 m;:lEE C2EA
236 IZIIZ1FIZI F2EA
237 1Z10F2 CAEA
238 a0F4 C2E9
239 aaF6 F2E9
2410 lZIaF8 CAE9
24:1.. IZIIZ1FA 102
242 IZI1Z1F8 C2E8
243 IZIIZ1FD F2EA
244 IZIIZ1FF CAEA
245 13:1..13:1.. C4aa
246 10:1..103 F2E9
247 10:1..105 CAE9
248
249 10:1..137 3D
2513 10:1..138 BAEA
25:1.. 1ZI:1..IZIA 9CFB
252 a:1..ac BAE9
253 a:1..aE 94F7
254 13:1..:1..0 C2ED
255 aii2 3:1.
256 13:1..:1..3 C2EC
257 0i:1..5 35
258
259 10:1..:1..6 CBa:1..
260 10:1..:1..8 8AEE
26:1. aHA 9C8D
262 a:1..:1..C BAEF
263 lZliiE 9489
264 13:1..213 9135:1.

. DB'T'TE

BADPRrl

LDI
XPAL
LD
XPPC
LD
CCL
ADI
XPPC
Jt'lP

L< PHE:>( )-:1..

LOC:
P3:
HI (P2:)
P3
LO(P2)
-:1..
P3
RETN2

.: CLEAR CARRYAINK FLAG
; CORRECT COUNT

OK:
CCL
LDI
ST
CAD
ST
CCL
ADD
ST
LDI
ADD
ST
CCL
LD
ADD
ST
LD
ADD
5T
CCL
LD
ADD
ST
LDI
ADD
ST

10
DPHI(P2)
HCNHP2)
HCNT(P2)

; CLEAR UPPER D. P. COUNT
.: COMPLEMENT HIT COUNT
.: CLEAR CARR'T',.'LINK FLAG
.: CONPUTE 5~<

HCNT(P2)
DPLO(P2)
10
DPHI(P2)
DPHI(P2)

.' 2~<

DPLO(P2)
DPLO(P2)
DPLO(P2)
DPHI(P2)
DPHI(P2)
DPHI(P2)

;

HCNHP2)
DPLO'::P2)
DPLO(P2)
a
DPHI<"0085
X'" 01.5A

THE ERF.:OR

PRO~l

NOT ERASED
PF.:ot1 CANNOT BE PROGRAt'lMEC,
PROfo1 DOES I·IOT ..... ERIF',..

44
45
46
47

;

THE "HALT INST" S~HTCH ON THE LCDS ~10THERBOARD MUST BE
It.J THE "DEBUG" POSITION BEFORE E),-,
0'0

SAI,/l

SA'·... HI

Hun

-4

DPLO
DPHI

-6

5-28

,PERIPHERAL ADDP OF PROM
PPOGPAMMER BOARD
: OP[)EP CO[:oE FOP PROG.
•·... OL TAGE
: OP[:'EP CO[:'E FOP REti[)
.. OPDER CO[:'E FOR V55_. \.IBB .. '",ID[)
: OF.DEP CO[:'E FOP CHIP SELECT
.. OF.:[:'EF: CODE TO LOAD DATA
.: OF:DEP CO[:'E TO CLOCK COUNTER
.; OPDEP CODE TO PEAD PRot'l
;
DAni
,ORDER CODE TO cLEAR COUNTER
,ORDER CODE TO ENABLE CONTROL
: LATCH
,pAM POINTER TO MOTHEPBOARD
.: R.····!·J t'IEr'IOR'T'
,TEMPORARY LOCATIONS IN RAM

SC/MP ASSEMBLER REV-A
Pt·ILPCJt·j sc/r·jp PRm'j PPOGRAr'U'jEP
PPOM ACCESS AND PPOGRAMMING ROUTINES
. F'ffGE

***
(1(1[10

'PROM ACCESS AND PPOGRffMMING ROUTINES'

ROUTINE TO CHEC¥ F'POM FOP ERffSED CONDITION ***
IJOp

(:It;

Cf'::EP'::;[:'

85 '3[u)1 C:4(1:3
86 [1(1[1]: ::<::1

LDI

>;PAL
LDI
;;;;PAH

87 Of104 C4f10
-:·c
:38 0006 "::"-'
:3'3 ~3(H::17 ::<:[:.

:':PF'C

f1(1

HALT

[1[1(18

92
93

L 0:: ERASED) ·-1
Pi
H(EF.:ASED)
P:1
Pi.

, HALT IF EF.:ASED

THIS SUBROUTIt~E IS ALSO CAl.LEE' B'T "PF.:OG." TO ··... EPIF\' THAT
THE PROM IS EPASED

94
95
96
97

EF.:ASED:
~~1(1f19

,x't"m

C40')

LDI
;;PAL
LDI

98 0[10C C477
99 OO,)E 3:6

if15

106
HJ7

i[1B
1<)9

11[1
111
L12

, INIT RAM POINTER

H0:: PPRca'lR)
P3:
L 0:: PPRCH'1R)
P3:

;SET ADOR.

,SET UPPEP couln
;5TACV IS EMPTY, USE AS PTR
,SET READ t10DE
; SELECT PROM SOCKET
;SET LOWER COUNT

ERAS2:

1'~1(1

101
H'i2
1.']3
104

;";PAH

LO:: RAt·j::P2
Ho:.RAt·j)
P2

')OOF C4:::::,,-1
[1011 "::.,
(11)12 C4[1(1
0014 -;:.-:.
[1(1i5 C401
0017 CAO[1
f-::H'li9 CB'~1C:
O[11B CB1C
[101[:' C40':'I
[1I3·1F CAFF
0021 CB,33:
[11];23: CB[1,::'

LOI
>,;PAH

LDI
>TAL
LDI
ST
ST
ST
LDI
ST
ST
ST

1.13
114 ~3~~125 C:3:02
115 ~3027 9COB
116 121(129 CB[11
117 [u~12B BAFF
:1H,: 0,32D 9CF6
L19 [u)2F BAO[1
12') ')[Cl 94F2
121 0(13::i: 3D

ELOOp·

:1.22

NOT·

123: 003A
1.24

LD
JNZ
5T
OL.D
TNZ
DLD

JP
>';PPC

HI (P2:'
R["(P3:)
CS(F'J:)

C1
LO(P2)
LOFID"o:. F':!.::-

; CLEAR PROM COUNTER
,CLEAR OATA LATCHES FOR READ

p['PRr·j(p:;:)
r·lOT
CLV(F'3:)
LO(P2)
ELOOP
HI(P2)
EL.OOP
Pl

.' REAO ['ATA OUT OF PROt'l
;OATA NOT ZERO? NOT ERASEO
,OATA C~, BUMP COL~TER
;OECPEMENT LOWER COUNT
; NOT DONE 'T'ET
; DECREMENT UPPER COUNT
.' NOT [:'ONE ',-'ET
.; PROt'j IS ERASE[:'

I~:LF.: 0::

P-;:::-

HALT

0(1

;HALT IF PROM NOT ERASED

*.,,-+, EIHR'T' PO 1 NT TO PPOGRAt'l PROt'1

:125

126
127

OF PROGRAMMER

(,J,.

·'0 CHEU:: FOF.: EF.:ASE[:· ***

~·JOCHf':

12(1 l-3ff3:::;: 3:6

ceL.
L.DI
;,·WFtH

1:;::1
132

128 J.]O:i:5 (12

129 J.)(1J:6 (:477
~3039

(:400

LOJ

[1[CE:

~··c,

;';PflL

H(Ptit-l}

P2
L.':PAH
lOI
ST
LEd
ST
ST

~:: .. _I

::;:0

C2FE
::;::1
C2FD
~t6::;: 005E F402
-;.c,~t64 ..:1(160 -'::"-'
:t65 'X16:1 C401.
1.66 (106::; CAt.3(1
1.67 0065 CA[1~3
i6:::: ~)f167' CAFF
1.69 1.](169 C8'3::;:
1.70
1. 71. €n36E: C5FF
1.72 01.::'16[:. (1:1

:17::

SET

l (PAr'l)
P2
H(PAt'l:)
P2
Pi.
SA ',lLO(P2)
P:1
SA"iHI (P2)
L 0: EPAS2";o-:1
Pl
P:1
SH'·/LO (F'~~ >
P:l
SA',iH I (F';;;:~ )
2
P:1

,SAVE A[:oOPE5S.

; CHECK

PP(~

FOP ERASED

-' AOD 5:12 OFF:;ET

H I (P:? )
0
LO(P;?")
CLPO::P::;:";o

;SET UPPEP lOC COUNT
-,SET LOWEP LOC COUNT
; CLEAR PRot'l COUtHER

t·i>:TL.OC
LD
:::AE

(!i-1.(PL'

,GET DATA TO PPOGRAM
SAVE IN EXTENSION PEG.

L[:'I
> ee8C
223 ee8E
224 e~3BF
225 eeC1

CAFA
FAFC
CAFC
e2
F2FC
CAFE:
C4e\:1
F2FA
CAFA
e2
C2F8
F2F8
CAFE:
C2FA
F2FA
CAFA
e2
C2FC
F2FE:
CAFB
C413e
F2FA
CAFA

t1[)[)

ST
L['1
A[;-eST
CCL
LD
ADD
ST
U)

.: CHECK FOF.: t·lA:":.

HIT

.: HIT COUNT OVEP

~lA>(

. E:A[:O PRot1

€I

[WHI(P2)
HCNT(P2)
HCNT(P2)
HCNT(P2)
[)PLO(P2)
\:1
DPHI(P2)
DPHI(P2)
[)PU](P2)
DPLO(P2)
DPLO(P2)
DPHI(P2)
DPHI(P2)
DPHI(P2)

AD[5T
CCL
LD
AD[)
ST
LDI
AN)
5T

Hct-JT(P2)
DPLO(P2)
DPLO(P2)

:'<:PPC
[)LD
JNZ
DLD
JP
LD

P1
DPLO(P2)
PF:LP
DPHI(P;;::)
PRLP

.: CLEAR UPPER D. P COUNT
.' COI'lPLEt'lEtH HIT COUNT
.: CLEAR CAPF':-.,' /L 1Nt< FLAG
.. COMPUTE 5::-::

.; 2X

; 4>':

€I

DF'HI (P2)
DPHI(P2)

; 5;'::

PRLP:
::;:D
8AF8
9CFE:
8AFA
94F7
C2FE
31
C2FD

><:rtlL

LD
i<:PAH

226

227 00C2 CBel
228 13eC4 BAFF
229 eeC6 9CA3
23:0 eeC8 BAee
23:1. eeCA 949F
232 eecc (113
23::;:
23:4 eec[;- C4e(1
23:5 e0CF CB(lC
23:6 0eDl CB1C
23:7 013[;03: 4(1
23::3 0eD4 CBe0
2::9 (1eD6 C401.
240 e0D8 C8e4

SAVLO(P2)

.: PROGRAt1 PF':Ot'l
; DECREMENT LOWEI': COUNT
. NOT DONE
-' DECREMENT UPPER COUNT
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P1
5AVHI(P2)
P1.

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.' DELA',.' :1. 1'15

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; SELECT PRC~ SOCKET

LOAD(P:3:)
F.:DPPI'1(P:::()
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; CLEAR DATA LATCHES
.' PEAD DATA FROI'1 PPot'l

COpy PROM TO PANGE IN MEt-lORY

***

C:()F"T' :

0:1.01
():1.02
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.' ADD 5:1.2 OFFSET

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3:5

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,GET DATA FRON P~)M
,COMPAPE AGAINST NEMORY DATA
,DOES NOT VERIFY
,BUNP PROM COUNTER
,DECREMENT LOC COUNTEP LOW
.' NOT DONE
,DECREMENT LOC COL~TER HIGH
.' r~OT DONE
, HALT !,JHEr'J DONE

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TO ENABLE
CIRCUIT

5-37

:!
oa:

a..

Programming Equipment
for National PROMs

.e
sQ):::

C-

C')

s:::

E
f!

National Semiconductor manufactures both Schottky
TTL and MaS PROMs in the industry standard pinouts
and organizations_ See the table below for available
device types_

National's Tri-Safe™ programming procedure ensures
fast, reliable programming_ After the proper address
location is selected and the output and VCC pins have
been raised to 10.5 V DC, the devices are programmed
when the enable pin is taken low_ Since only an enabled
device is programmed, it is possible to program these
devices at the board level.

The 2k and 4k MOS PROMs are fabricated using a silicon
gate, p-channel process_ The MM2708 is fabricated using
a silicon gate, n-channel process. Different personality
modules are required for each device type.

For complete programming procedures and specifications, consult National Semiconductor.

The bipolar PROMs are all fabricated using a Schottky
TTL process. The fuses are of Ti-W material. A single,
generic module is used for all bipolar PROMs. All bipolar
PROMs are also supplied with all outputs low in the
initial state. Positive logic is used to "program" logic 1s
where desired.

~
c..

Commercially Available Authorized Programming Equipment

Data I/O

Pro Log

Size

Module

DM54174S1881288

32x8

909-1063-5

715-1037

PM9047

32x8 ILl

PA16-2

DM54174S387/287

256x4

909-1063-5

715-1035-1

PM9047

256x4 (LI

PA16-1

DM54i74S570/571

512x4

909-1063-5

715-1035·2

PM9047

512x4 III

PA16-1

DM54174S572/573

1024x4

909-1063-5

715-1039-3

PM9047

1024x4 (LI

PA18-2

DM54174S574

1024x4

909-1063-5

715-1406

PM9047

1024x4 (LI

PA18-4

DM77/87S295/296

512x8

909-1063-5

715-1033-2

PM9047

512x8 (LI

PA24-1

MM1702A

256x8

909-1183-1

715-1047

PM9001A

MM5203

256x8

909-1178-1

715-1047

PM9002A

MM5204

512x8

909-1177-1

715-1033

PM9006A

MM2708

1024x8

909-1174-1

715·1033·3

PM9005A

Device

Adapter

Module

Configuration

Adapter

BIPOLAR PROMs

MOS EPROMs

Data I/O
1297 N.W. Mall
Issaquah, Washington 98027
(2061 455-3990

5-38

Pro Log
2411 Garden Road
Monterey. California 93940
(408) 372-4593

EPROM Notes

z
o
Sen

Although EPROMs are in widespread use there are
continuing problems associated with erasure and programming. The following indicates some of the pitfalls:

Often the operating voltages of an EPROM are shifted
to ease interface design in the system. This results in the
parts being programmed to operate with the data sheet
voltages and then operated with a different set of
voltages in the system. This may lead to some of the
parts not functioning correctly in the system even
though they are properly programmed. This is especially
true for the MM5204 which has the trip point of the
internal sense amplifier altered if VLL does not meet the
conditions VLL ~ VSS - (5.0V ± 5%1.

Erasure
Erasure seems sO simple that it is often not considered
when a problem arises. Under·erasure can be a direct
cause of under·programming when an inter-active programmer is used. Periodic calibration of the erase system
is all that is necessary to provide proper erasure.
Changing bulbs (and aging bulbsl, changing manufac·
turers, changing distance from the lamp and changing
package tYpe, especially the quartz lid, should be a
stimulus for recalibrating the erase system. Over-erasure
has so far not been a proven problem, but erasing. more
than 10 times longer than the time needed to erase a
part should be avoided. Then there will be no question
of over·erasure. Lamps with short wavelength « 1800AI
and high intensitY are believed to ionize oxide with long
exposure. The theory is that this will shift the threshold
until the part will not function correctly. This is not a
permanent shift and an overnight bake at 225°C for gold
plated parts or a 24-hour bake at 150°C for tin plated
parts should correct the problem.

Bootstrap circuitry in some EPROMs is slow to respond
when the component is powered down (to save power 1
and then powered up to be accessed. The first cycle of
operation can have a significantly longer access time and
can be a function of the rise time of the power supply,
if power is being switched.
If the part was not under-erased, has no system/component access time problem, is not operating under
voltages different from the program (really the read
conditions of programmingl set, and provision for the
longer access time of power-up has been made, perhaps
the part was programmed improperly. Unfortunately,
the symptoms can look the same in a system. If may
appear to be access time, output levels, sensitivity to
voltage and temperature variations, or just intermittent

Some EPROMs exhibit a sensitivity to ambient light.
This does not erase them, but they may not function
properly when minute photoelectric currents (Ieakagel
are being generated. This is a common phenomenon with
most semiconductors. Covering the Iid with some
opaque material is a prudent practice.

operation.

There are three basic problems encountered in programming EPROMs. The one most often encountered is
improper voltage levels. The voltage applied to any pin
must be maintained between the specified min and max
levels for proper programming. This statement sounds
reasonable but frequently this is not done. The high
voltage levels required by some EPROMs are provided
by designs with resistive pullups on the address inputs.
The drop across the resistor during the program time
causes the input voltage to be out of tolerance; active
pullups eliminate this problem. Similarly, the power
supplies must be able to supply sufficient current so
that they maintain the specified voltage level. The
FAMOS memory cells in EPROM must have sufficient
voltage developed across them or they do not program!
A second cause of programming malfunction may be
incorrect timing. A third programmer problem occurs
when not adhering to the duty cycle limitations. If the
junction temperatures are raised too high due to power
dissipation, a part maY not program.

Programming

Programming seems to be the assumed cause of all
EPROM problems. As noted in the section on erasure,
if a part is not fully erased, an interactive (intelligentl
programmer will under-program the part. This would
really be an erasure problem.
If the part is slow, or the system requires a faster access
time than the part provides, intermittent operation
sometimes occurs and the designer often assumes the
parts aren't programmed correctly. This is a system/
component specification problem.

5-39

Section 6

CRT
Display Applications
The introduction of microprocessors into the design of
CRT terminal systems has greatly reduced component
count. With this reduction has come an even further
emphasis on cutting the number of parts in the video
display portion of the system. National Semiconductor
has addressed this problem with the introduction of the
DP8350 series of CRT controllers and the DM8678
family of character generators. Together with LSI
memory and microprocessors these devices allow con·
struction of a low end terminal consisting of less than 20
components, while retaining wide flexibility for use in
more sophisticated terminal designs. Additional component types are being developed for terminal applications and will be announced in the near future.

Simplify CRT Terminal
Design with the DP8350

National Semiconductor
Application Note 198
Helge H. Mortensen*
March 1978

INTRODUCTION

This application note is a description of a "low cost"
CRT data terminal card design, based upon National's
CRT Controller (DP8350) and 8-bit N-channel microprocessor (SC/MP). The terminal has a minimum parts
count and implements all TTY functions. Even with this
minimum number of parts, the terminal provides some
"smart" features by efficiently utilizing the available
hardware. Screen scroll, RS-232C interface and adjustable
baud-rate (up to 1200-baud) are featured on the card.
Higher baud-rates are available on a word-by-word basis
if the RS-232-handshake signal is used. The design also
demonstrates use of 2 new microprocessor-interface
parts: the Asynchronous Communications Element
(ACE), for serial I/O; and the RAM Input/Output
(RAM I/O). for keyboard scanning and scratch pad
memory _ A 2-kilobyte video RAM is implemented with
four 1024 x 4·bit, static RAM chips (MM2114),anddot
generation uses the DM8678 5 x 7 Character Generator.

still not affected. However, with the saving of the data
buffer and the address buffer, a well-organized "time
share" of the busses is required. How does this limited
bus access affect the time-critical features such as scroll
and high baud rate?
Scroll

Several scrolling methods may be implemented with the
CRT Controller. The most straightforward is a rewrite of
memory. This requires long processing time and bus
access and is not feasible with the minimum hardware
indicated in Figure 2. Sensing when the CRT is scanning
character-row 24 and then loading a new "row start"
requires additional overhead circuitry. An alternative
approach is to load a new "top of page" address for each
scroll and have the video RAM "wrapped-around" when
it is accessed by the CRT!

The card is self-contained except for the CRT monitor
and power supply. It holds a keyboard and monitorinterface circuitry. Monitors requiring separate video and
sync signals (Ball Brothersl. and those requiring composite video (Motorola) are accommodated.

In the latter approach, the processor only has to clear a
row in video RAM and load a register in the CRT
Controller to perform a total·screen scroll. The only
problem remaining is handling the location of the
scratch pad in the video RAM address space. By using
the RAM I/O chip for a keyboard scanning and scratch
pad RAM, the problem is solved. An additional feature
for the software programmer is that the keyboard and
RAM are addressable within the reach of one 8-bit
index register.

System Architecture
Since system cost is typically somewhat proportional to
parts count, arriving at a minimum parts count solution
has been a goal throughout this design effort.

Maximizing Communication Baud Rate
A full-blown CRT terminal is shown in Figure 1 and its
low cost counterpart in Figure 2. Address decoding details
are omitted in both cases.

Assuming that the processor has bus access only during
the vertical blanking period and the ACE interrupt
service subroutine is executed in less than this time,
only one received data word could be processed per
frame! The processor's task is to transfer the word
from ACE to scratch pad memory, check for terminal
or system control functions, write into the proper loca~
tions in video RAM and check the keyboard for "Break"
(BRK). A quick calculation reveals 60 bits/second as
the maximum baud rate! To improve communication
speed, the processor must have bus access during the
video frame scan time. Three of the 10 scan lines making
up a character row are blanked except during cursor
time. Using these three lines (minimum decoding
required) for processor bus access during video time
allows us to communicate at 1200 baud.

Removing overhead circuitry shown in Figure 1, and
making use of the TR I-STATE® concept greatly facilitated the parts reduction effort.
Obviously, extreme time conflicts for communicating
on the system busses are created because all essential
parts require access. Let us investigate this problem a
little further.
Because the CRT Controller does the CRT display
refresh function, it must have access to a memory
containing current data for display. This memory may
be a shift register (octal, BO-bit line buffer in Figure 1)
which is loaded at the first video line in a character row
and then recirculated for the number of video lines in
that character row. Using such a line buffer allows the
microprocessor access to the system busses for more
than 90% of the video time (screen time). On the other
hand, by removing the buffer, the refresh circuit needs
direct memory access (DMA) during video display time.

Note that the baud rate is limited by the frame rate in
the first approach; in the second approach, the limitation is the real time required to execute the service
routine. The calculation is performed as follows. Estimated execution time for service routine with 100%
availability of the bus is 2 ms. However, bus access is
only granted during 3 video lines in each character row
which is worth 192 JlS. In terms of video time, we need
10 character rows to finish the routine and be ready for
the next interrupt. Display time for 10 character rows is
6.4 ms, which in turn is the time interval for one 10-bit
word. This translates into a 1600-baud maximum capa~
bility if scroll is not included in the service routine.

However, with the bidirectional data buffer and the
TRI-STATE address buffer in the system, the situation
is not yet too serious. (We are only preventing the
SC/MP microprocessor from updating video RAM data
or using the scratch pad during character display time.)
Instruction fetch (ROM) and keyboard scanning are
"Refer tq Introduction.

6-1

VIDEO
INTERFACE

I
ITO

SERIAL D U T + - - - - - - - - - -....
SERIAL IN ~------....,

f-....,-----~ATTAIBUTE
DECODE

I
I

KEYBOARD

I
I
I

'---:;;~~·I}

H ~5:AD9 P~:}
[Sl~VCL
1
U12
ESCf"=---+-HH-++++,"O( UI6
2
AD11 J6 SC/MP

RAM 1'0
l

Y X W V

1201l

'BlI::12O--i-H-+-,

'''t::t:::::::::t:::~4:::t:::~~h
r.;

.--!1 P81

S 16 PA7

N M

K 11

1 H

A @l

,~~

5-=-30

2401l-lf-,:l-'~H:H'-",!-,'I-'1'H'::I;; PA3
4800

PAl
23 PAl

;-28

2-::-21

1~26

24 PAO
Ig200-lH-+S"i'H-+-++-Fl
SH [R

AODf!-25

[ONT - - - - - --__

[I,ez

AD10JS

4;;-29'

19 PM

9600

lB,

M!ITi~n

PA6
[18 pA5

NWOS

~8
-I..................~...........

8R~g9

£7

'-=_______--"t
TO [I. [2 PIN 1,2

1/41'1

fROM(UI8(::::~
UI6PIN~~"""
116 15

14.

OAT~~ ,.!LAOD
AI~AOI

lSBAUil1i1JT
[
9 ReLK

12V

.--- ~_______~'~·~2

DSI4~

5
4
~~---~--~~U44

A2~A02

26
27

CSOr-::- A010

CS:2..,.f.LAOll

CSI +LA09

vee

41i<

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9 A4

ADS 30

10 A5

A06 31
A07 32

11 A6
lJ A7

AOS 33

14 A8

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33 mR
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1, -

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38 R

OS1489

6
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DOSTR

1 0 ' t - -.....-:"""'.....

'14'

VOS1489

'HP-H-,,-H--~

FROM
U6 PIN!

Vss

vcc....!§

(+)

U10
MM14lS156 lH~-t-:-;;--+--~

310SR

v::~:

13~t----------TI-,-------------

::..:'"T'"I.:.:-r-I:.:..:""T'
"c::.:"'T":r:.=..,..I=.:..,..:::·:.:p::..::.:
......
::::::=.J"f~~t:..:
: :,=':"'T":r:.=""'I:":-:'I~"""c.::..:-r-:::::,:,:""":r:.=I='Ii
=::::':::LII
I'
""?2- ......
I' "
...-'I

OUTPUTS ::::-::::==:-::-::::::-::::=:-:t::::::-::::-ti??=:-::::::-::=:-:~[:.::.::==:.::..::..::.::.::=::.::.::
I
- '!(; I
CLEAR LINE COUNTER --------------+----_'r?[-- -----i_------------It N£ COUNTER

ADDRESS OUTPUTS

LINE
MAX-l

ROW X

MAX

(NOTE 4)

==:.::.::.::.::.:::r:_::_::::~p:::-:E

- - -:- - - - - - - - - - - - - - --

RECIRCULATE --------------tll-----i?'tl-------'II[II:~O:TE~3:1=::.::.::.::.::.::==::.::.::
CURSOR OUTPUT -------------....:,,--~2
I
ENABLE OUTPUT

•

'''''I"",~~ --------------- t----- il~-:.::..::..::.:..:.=~I:..:c:::::-::-::==:-::::::-:::-::=
ClM~,]-m

ADDRESS OUTPUTS
liNE

RECIRCULATE
ENABLE OUTPUT

• POINT A (NOTE 3)

t- ,..............

~(___1__~---I----------------

::.:~::..::.:~:::.::.:~::..::.::.:t!::::..::.:~~~-:.::.:~-:.::::.:~I,~ltIN~OT~E:31~~::~~::::::~=
_

CURSOR OUTPUT --------------+--~It(-------i_------------ROW
X+1

LINE
1

CLEAR LINE
COUNTER

:::::==::=:-::::::-:=::=t::::::-:=~~·I~=:-:::::::=::I~[I• :.:==:..::.::.::.::.:==:.::..::
~
I
(2
1

ADDRESS OUTPUTS

==:.::.::..::.::.:::rl:_:::=~~---;----------------

LINE COUNTER

OUTPUTS

• POINT B (NOTE 3)

EN~i1Ir&~~~~f

-_-_-_-_-_-_-_-_-_--_-_-_-_-_-_-_+!-_-_-_-_-_,~~?t------------------;-~-J,-----------:. . O'_'--------------I~----_'r)i)~------~I~----------------CURSOR OUTPUT . lO~G~IC~
((

Note1: The load video shift register output is not active during vertical or horizontal blanking (remains in the logic "1" state during these

intervals.
Note 2: The horizontal sync output start and stoP point positions are user-programmable at character width intervals.
Note 3: The position of the recirculate enable output logic "0" level is dependent on the state of the character generator program input (CGPI L
With CGPI "" "0," recirculate enable occurs on the max line of a character row (solid line) and the address counter outputs rollover to the new
row address at point A. With CGPI = "1," recirculate enable occurs on the first line of a character row (dashed line) and the address counter
outputs roll over to the new row address at point B.

Note 4: The address counter outputs clack to the address of the last character of a video row plus 1. This address is then held during the horizontal
blanking interval until video minus three character times. At this point the outputs are modified to the contents of the Row Start Register (RSR).
With no external loading of the RSR the contents will be either the character address of the first character in the present row or the character
address of the first character of the next video row (depending on the state of the Character Generator Program input) which will be sequential
from the last character address of the last row. If the RSR was loaded, then the address outputs will be modified to the contents of the register.
Figure 3. Character/Line Rate Functional Diagram

6-15

Timing Waveforms (cont'd.)

Note 1: One full row before start of video the line counter is set to zero state - this provides line counter synchronization in cases where the
number of lines in vertical blanking are not even multiples of the number of lines per row.

Note 2: The stop point of vertical blanking is programmable at line intervals within the last character row before start of video.
Note 3: The Vertical Sync Output start and stop points are programmable at line rate increments.

Figure 4. Line/Frame Rate Functional Diagram

'Ilr---------

'ow2

-l'S' r:::
-I t::-----------"'X'-------------------'I
'H1

"EGISIERSHECT
AOAINPUTS
BAND _ _ _ _ _ _ _ J
ADDRESS

"- _ _ _ _ _ _ _ _

ENABLE
INPUT

-I

r=;:

ILZ

£,

f. -

VOL _ _ _ _ _- ' - _....

VOH

~1.5V

.....1.1

INPUT _ _ _ _

~'.5V

_ _ _ _-_'-'....,ZL

I 1-=

\=;D.• V

D.5V

'a_D_
.•_V_ _ _

ENABLE

\ ....- - - - - - -

.•

~, .• V

~1.'V

VOL

-;-...J/lr:....t.7-0.-,V---

_____

-I 'ZM ....1.

'HZ

ADDRESS OUTPUTS ENABLE/DISABLE WAVHQRMS

Test Load Circuits
Vec

... ,...
TO OUTPUT
UNDER (lTE
...S.T_ _ _.....~.....
L~I-""

,,"

Rl = 1k

TO OUTPUT
UNDER

~~
7::-

-=-

ClT'..:S~T~---4>-"~.-.

I
.J:
f';~~"I

1 ..... ~,
fs',; ~Do":"I:!:
~,

... "

oJ: .. }

LOAD CIRCUIT 1

LOAO CIRCUIT 2.

NOTE: CllNCLUDES PROBE AND JIG CAPACITANCE
All DIODES ARE 1N914 OR EQUIVALENT.

6-16

-r

VOH

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage, VCC
7.0V
Input Voltage
-1 V to +5.5 V
Output Voltage
5.5V
_65°C to +150°C
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
300°C

Electrical Characteristics

Min

VIL

5.25
+70

V
°c

Conditions

Min

Typ

Max

Units

Logic "1" Input Voltage
(System Clear)

2.6

(All Other Inputs Except Xl, X2)

2.0

Logic "0" Input Voltage
(System Clear)

0.8

(All Other Inputs Except Xl, X2)

0.8

VIH-VIL

System Clear I nput Hysteresis

Vclamp

Input Clamp Voltage
(All Inputs Except Xl, X2, &
Char/Line Rate Clock)

IIH

Logic "1" Input Current

IlL

4.75

Units

Vce ~ 5 V ± 5%, T A ~ O°C to + 70°C (Notes 2 and 3)

Parameter
VIH

VCC, Supply Voltage
TA, Ambient Temperature

Max

0.4

-0.8

J1A

Enable Input ~ 0 V,
5.25V, VIN ~ 0.5V

-20

J1A

VCC ~ 5.25 V, VIN ~ 0.5 V

-20

J1A

liN

-12mA

(Address Outputs)

Enable I nput ~ 0 V,
VCC ~ 5.25 V, VR ~ 5.25 V

(All Other Inputs Except Xl, X2)

VCC

5.25 V, VR

5.25 V

Input Current
(Address Outputs)

VCC~

(All Other Inputs Except Xl, X2)
VOH

Logic "1" Output Voltage

IOH ~ -100J1A
IOH

-1 mA

VOL

Logic "0" Output Voltage

10L ~ 5mA

lOS

Output Short Circuit Current

VCC ~ 5 V, VOUT ~ 0 V,
(Note 4)

ICC

Power Supply Current

VCC ~ 5.25V

3.2

4.1

2.5

3.3

0.35
-40

170

0.5

V
mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

Note 2: Unless otherwise specified. minImax limits apply across the O°C to +70D C temperature range and the 4.75 V to 5.25 V power supply
range. All typical values are for T A = 25° C and Vee;; 5.0 V.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referencf;i'O to
ground, unless otherwise specified. All values shown as max or min are so classified on absolute value basis.
Note 4; Only one output at a time should be shorted.

6·17

Switching Characteristics

VCC = 5.0 V, TA = 25°C (Notes 1 and 21

Parameter

Conditions

Typ

Min

Max

Unit

tOl

Dot Clock to Load Video Shift
Register Negative Edge

CL = 50pF, RL = 1 krl,
Load Circuit 1

t02

Dot Clock to Load Video Shift
Register Positive Edge

CL = 50pF, RL = 1 krl,
Load Circuit 1

t03

Dot Clock to Latch Character
Generator Positive Edge

CL = 50pF, RL = 1 kl2,
Load Circuit 1

t04

Dot Clock to Latch Character
Generator Negative Edge

CL = 50pF, RL = 1 kS"l,
Load Circuit 1

t05

Dot Clock to Line Buffer
Clock Negative Edge

CL = 50pF, RL = 1 kS"l,
Load Circuit 1

tPWl

Line Buffer Clock Pulse Width

CL = 50pF, RL = 1 k~2,
Load Circuit 1

N(OT)*

t06

Dot Clock to Cursor Enable
Output Transition

CL = 50pF, RL = 1 kl2,
Load Circuit 1

t07

Dot Clock to Valid Address
Output

CL = 50pF, RL = 1 k~2,
Load Circuit 1

t08

Latch Character Generator to
Line Rate Clock Transition

CL = 50pF, RL = 1 kS"l,
Load Ci rcu it 1

300+20T

t09

Latch Character Generator to
Clear Line Counter Transition

CL = 50pF, RL = 1 kS"l,
Load Circuit 1

400+20T

tOlO

Line Rate Clock to Line
Counter Output Transition

CL = 50pF, RL = 1 kn,
Load Circuit 1

180

t011

Line Rate Clock to Line Buffer
Recirculate Enable Transition

CL = 50pF, RL = 1 kn,
Load Ci rcu it 1

200

t012

Line Rate Clock to Vertical
Blanking Transition

CL = 50pF, RL = 1 kn,
Load Circuit 1

200

t013

Line Rate Clock to Vertical
Sync Transition

CL = SOpF, RL = 1 k>2,
Load Circuit 1

200

t014

Latch Character Generator to
Horizontal Sync Transition

CL = 50pF, RL = 1 kS"l,
Load Circuit 1

100

----_..

. :S~_I_"'"'"'' S""VMom""

Address Setup Time Prior to
Register Load Negative Edge

tHI

tPW2

150

fMAXdot

Maximum Oat Rate Frequency

MHz

fMAXchar

Maximum Character Rate
Frequency

2.5

MHz

tLZ, tHZ

Delay from Enable Input to
High Impedance State from
Logic "0" and Logic "1"

CL = 15pF, Load Circuit 2

tZL, tZH

Oelay from Enable Input to
Logic "0" and Logic "1" from
High Impedance State

15 pF, Load Circuit 2

Note 1: Unless otherwise specified, all AC measurements are referenced to the 1.5 V level of the input to 1.5 V of the output.
Note 2: When external clock inputs are used, the input characteristics are ZOUT == 50 nand tR ~ 10 ns, tF ..;; 10 ns.
""DT" is defined as the duration On ns} of one full cycle of the Dot Rate Clock (Item 20 of the ROM Program Table). "N" denotes the number of DTs per definition in Item 24 of the ROM Program Table.

6-18

DP8350 Series Option Program Table
Item
No.

(Notes 1, 2, and 3)

Parameter

Value

Dots per Character

1
Character (Font Size)

Scan Lines per Character

Dots per Character

3
Character Field (Block Size)

Scan Lines per Character

4
5

Number of Video Characters per Row

Number of Video Character Rows per Frame

Number of Video Scan Lines (Item 4 x Item 6)

Frame Refresh Rate (Hz) (two frequencies allowed)

Delay after/before Vertical Blank start to start of Vertical Sync (+/- Number of Scan Lines)

Vertical Sync Width (Number of Scan Lines)

Delay after Vertical Blank start to start of Video (Number of Scan Lines)

Total Scan Lines per Frame (Item 7 + Item 11 = Item 13.;. Item 8)

Horizontal Scan Frequency (Line Rate) (kHz) Item 8 x Item 12)

Number of Character Times per Scan Line

Character Clock Rate (MHz) Item 13 x Item 14)

Character Time (ns) (1 .;. Item 15)

Delay atter/before Horizontal Blank start to Horizontal Sync Start (+/- Character Times)

Horizontal Sync Width (Character Times)

Dot Frequency (MHz) (Item 3 x Item 15)

Dot Time (ns) (1 ';'Item 19)

Vertical Blanking Stop before start of Video (Number of Scan Lines)
(Range = Item 4 - 1 line to 0 lines)

Cursor Enable on all Scan Lines of a Row? (Yes or No) If not, which Line?

Does the Horizontal Sync Pulse have Serrations during Vertical Sync? (Yes or No)

Width of Line Buffer Clock logic "0" state within a Character Time
(Number of Dot Time increments)

Serration Pulse Width, if used (Character Times)

Horizontal Sync Pulse Active state logic level (1 or 0)

Vertical Sync Pulse Active state logic level (1 or 0)

Vertical 81anking Pulse Active state logic level (1 or 0)

to=

Note 1: If the Cursor Enable, Item 22. is active on only one line of a character row, then Item 21 must be either "1" or "0" unless it is the same
as the line selected for Cursor Enable.

Note 2: Item 24 x Item 20 should be > 250 ns.
Note 3: 11em 11 must be greater than Item 4 + 1.

6·19

DP8350 Series Option Program Table
DP8350 Option: 80 Characters x 24 Rows, 5 x 7 Character Font, 7 x 10 Character Field
Item
No.

Parameter

Value

Dots per Character

Scan Lines pe~ Character

Dots per Character

Character (Font Size)

Character Field (Block Size)
4

Scan Lines per Character

Number of Video Characters per Row

Number of Video Character Rows per Frame

Number of Video Scan Lines (Item 4 x Item 6)

Frame Refresh Rate (Hz) (two frequencies allowed)

Delay after/before Vertical Blank start to start of Vertical Sync (+/- Number of Scan Lines)

240
f1

60Hz

50Hz

----

Vertical Sync Width (Number of Scan Lines)

Delay after Vertical Blank start to start of Video (Number of Scan Lines)

Total Scan Lines per Frame (Item 7 + Item 11

Horizontal Scan Frequency (Line Rate) (kHz) Item 8 x Item 12)

Number o\Character Times per Scan Line

Character Clock Rate (MHz) Item 13 x Item 14)

Character Time (ns) (1 .,. Item 15)

Delay after/before Horizontal Blank start to Horizontal Sync Start (+/- Character Times)

Horizontal Sync Width (Character Times)

Dot Frequency (MHz) (Item 3 x Item 15)

10.920 MHz

Dot Time (ns) (1'" Item 19)

Vertical Blanking Stop before start of Video (Number of Scan Lines)
(Range ~ Item 4 - 1 line to 0 lines)

Cursor Enable on all Scan Lines of a Row? (Yes or No) If not, which Line?

Yes

Does the Horizontal Sync Pulse have Serrations during Vertical Sync? (Yes or No)

Width of Line Buffer Clock logic "0" state within a Character Time
(Number of Dot Time increments)

Serration Pulse Width, if used (Character Times)

Horizontal Sync Pulse Active state logic level (1 or 0)

Vertical Sync Pulse Active state logic level (1 or 0)

Vertical Blanking Pulse Active state logic level (1 or 0)

Item 13'" Item 8)

312

260

15.6kHz
100
1.56MHz
641 ns

91.6 ns
1

FULL/HALF ROW CONTROL (PIN 5)
Device pin 5 converts the DP8350 programmed display
from 80 characters by 24 rows to 80 characters by 12
rows.
Full/Half
Row (Pin 5)
Logic State

Display
Size

80 by 24

80 by 12

With pin 5 in logic "0" state, the 12 character rows are
equally spaced vertically on the CRT. Each row is spaced
by one full row of blanked video.
Also in th is mode the address counter outputs address
the same memory space for two rows - the video row
and the blanked row. Thus one half of the CRT memory
space is addressed with pin 5 in logic "0" state as
compared to pin 5 in logic "1" state.
6-20

PERIPHERAL

VIDEO

INTERFACE

1
1

:--"'P------"'!--I

..._____~'l¥TR'BuTE

1-_~

!DECODE

MICRO-

PROCESSOR

CONTROL
ROM

OR
OMB678

1
1

I ...........

II--~--~I

ADDRESS BUS

I
VIDEO
1
L.._ _ _O",U",T.:;PU::.;T'-I

HORIZONTAL
1
. -_ _ _......::s"-yN"'C'-1

.-_%...___"--____

...L...I-_ _ _-'-..,

1
1

VERTICAL

THREE·TERMINAl

MONITOR

1-_ _-'S"-yN"'C'-1

SYSTEM CONTROL BUS

CURSOR
1
r_-"EN::.:A:::B"'''. .

CRT CONTROLLER

I
1

Figure 6. System Diagram Using a Line Buffer
PERIPHERAL

VIDEO

INTERFACE

I
1

:--""r-------pioi---l

..---------..

1-_~---

1
1

------..;'l~TR,BUTE
DECODE
1
1

1
1

MICROPROCESSOR

CONTROL
ROM

RAM

i.._____________I______~..1

1
1

DISPLAY
CONTROL
BUS

1
1

VIDEO
I
L-_ _.....;O::.:U::.:T~PU"'T_I

HORIZONTAL

.--_ _ _....:Sy.:;N"'C. . . 1

-...::.----=-----.. . . . . .----'---,

~::::::::::::::~-=::::Sy:S:TE:M:C:O:N:TR:O:':B:U:S::::~

CRT CONTROLLER

VERTICAL

SYNC

THREE-TERMINAL
MONITOR

CURSOR

ENABLE

Figure 7. System Diagram with no Line Buffer
Note 1: If the Cursor Enable, Item 22. is active on only one line of a character row, then Item 21 must be either "1" or "0" unless it is the same
as the line selected for Cursor Enable.
Note 2: Item 24 x Item 20 should be > 250 ns_
Note 3: Item 11 must be greater than Item 4 + 1.

6-21

DM8678 Bipolar
Character Generator

The DM8678 is a 64 character bipolar character generator
with serial output, and packaged in a standard 16-pin
DIP designed primarily for the CRT display marketplace.
The DM8678 incorporates several CRT system level
functions, as well as a 7 x 9 row scan character font.
The DM8678 performs the system functions of parallel
to serial shifting, character address latching, character
spacing, and character line spacing which are normally
done with extra packages. Figure 1 is a block diagram of
the DM8678.

Address Latch
The address latches are "Fall Through" or "Feed
Through" latches. The address latches are illustrated in
Figure 2. When the address latch control signal is high,
the character addresses "Fall Through" the latch. And
when the address latch control signal goes low, the
character addresses are latched. A 40 ns address set-up
time is required.

ADDRESS
LATCH
CONTROL
A6

C~~~~~~~R

64 X 63

DECODER

ROM

1/64
A3

A2
Al

CLOCK _ _ _ _ _ _ _; - - " ' " - - - - ,
CONTROL
4-BIT
COUNTER

MUX

EDGE·TRIGGER
GENERATOR

LINE
CLOCK

CLEAR--------------------~

OUTPUT

OUTPUT
ENABLE

FIGURE 1. Block Diagram

ADDRESS
IN--+--.::.t._/

.------li.

ADDRESS
LATCH
CONTROL

FIGURE 2. Address Latch

6-22

:::O-z

a
a
a

a a

0
0
0

The line counter is a mod 16 counter and its count can
be shortened by clear, which resets the counter to its
first state, when it goes to low state.

Logic operation is as follows: When the address latch
control signal is high, "AND" Gate A1 is enabled and
"AND" gate A2 is disabled. In this mode, data "falls
through" the latch. When the address latches control
signal goes low, Gate A 1 is disabled, blocking any new
address inputs. Gate A2 is enabled by a high on input
"A" which allows the feedback to determine the output
of gate A2. If the feedback is low, the output of A2 will
be low. If the feedback is high, the output of gate A2
will be high. Note that there are two inversions from the
output of gate A2 (01 and 11) to the feedback loop.
Thus the feedback maintains the level that was present
on inverter 11 when the address latch control goes low.

7-Bit Shift Register
A 7·bit parallel·in serial·out shift register is used to
serialize the output data. Seven "0" flip·flops and
seven 2-line-to-1-line multiplexers are used to perform
the paraliel to serial conversion. (Figure 4) .
Operation of the parallel to serial converter is as follows:
the cycle begins with load enable going low. This routes
data from the ROM via the MUX to the "0" inputs of
the 7 flip·flops. The data at the "0" inputs is clocked
into the flip·flops on the next low-to-high transition of
the dot clock. Next, the load enable, goes high switching
the mux. Now data at the "0" input comes from the
"0" output of the preceding flip-flop stage.

ROM
The ROM is 64 x 7 x 9 ~ 4032 bits. The ROM comes
with a standard upper case character set. And, it is possi·
ble to have custom fonts. A coding sheet is included
with the data sheet. Obviously it is possible to make
smaller characters by not using all of the ROM. For
example, a 5 x 7 character set could be made. Also, it is
possible to use two chips to obtain a larger character set.

The first stage in the shift register is an exception and
the mux routes a low to its "0" input, with the first
stages "0" input low. After 7 clocks, all stages are low
and any additional clocks will produce a low output.
This feature is used for horizontal spacing between
characters.

Line Counter
The line counter consists of a 4·bit ripple counter with
an asynchronous clear input. The input clock is shaped
by an edge·triggered clock generator. The clock generator's output clock pulse is enabled by the clock control
signal. The output pulse from the clock generator goes
to one input of a two input "AND" gate and the clock
control signal goes to the other input of the "AND"
gate. When the clock control signal is low the clock pulse
is blocked by the "ANO" gate. The line counter is
illustrated in Figure 3.

Output Buffer
The output buffer is a standard TTL TRI-STATE® out·
put circuit. The output enable is the TR I-STATE control
and when the enable is high, the output is in the Hi-Z
state. The output can sink 16 mA at 0.45V for a low
signal out, and, will source 2 mA at 2.4V for a high
signal out.

LINE CP

co~~~g~

_______

..J

Cl'AR-------i~~---~~----~----~-----~

FIGURE 3. Line Counter

LOAD
E.NABLE

......r CLgg~-----I.>----'
FIGURE 4.

7~Bit

Parallel-In Serial-Out Shift Register with Synchronous load

6·23

on the next low·to-high transition of the dot clock
with Line 1 of the character "N." The next 6 dot clocks
will shift out the rest of the first line of character "N,"
If only a single character in a row was generated, the
line clock would go from low-to-high advancing the line
counter which in turn switches the multiplexer to Line 2
of the character. Line 2 contains the next 7 bits required
for generating "N." This would continue until the 9th
line has been clocked out. Any additional line clocks
will put a vertical space between characters. This is
illustrated in Figure 5.

OPERATION OF THE DM8678 CHARACTER
GENERATOR

To illustrate operation of the DM8678, an example is
given tracing the sequence of events involved in
generating a character. The character "N" is used in this
example. (Figures 1 and 5).
Generation of the character uN" begins with the appro·
priate 6·bit character address becoming valid on the
address inputs Alto A6. This address can be latched by
bringing the address latch control signal low. There are
address set·up and hold times of 50 ns and 40 ns
respectively.

In a typical application, more than one character is
displayed in a row.(Figure6) The sequence is as follows:
Line 1 of the first character is clocked out. Note that
7 dot clocks are required to shift out one line in a character. Additional dot clocks will add lows to the end of
the line. This provides a horizontal space between
characters. There is no limit to the number of clocks
which can be used to generate horizontal spacing. The
address is changed to select the second character. Then
the first line of the second character is clocked out,
next, the first line of the third character is clocked out,
continuing until the first line of the last character in the
row has been clocked out. At this time, the line counter
of the DM8678 is clocked, advancing the line counter
to Line 2. The first character is addressed again, and the
process of the scanning continues until the 9th line of
the last character in the first row has been shifted out.

The output of the address latch is decoded in the
character address decoder. This is a 1/64 active high
decoder. The word line which contains the code would
go high.
The ROM contains the code required for generating the
64 7 x 9 characters. The ROM is organized 64 words
each, 63 bits long (7 x 9 = 63). In the ROM, the first
7 bits of 63 are line 1 of the character, the next 7 bits
store line 2 of the character and so on. Note that 1 bit =
1 dot. The lines and dots for our example "N" are
illustrated in Figure 5. The code for "N" would be:
1000001
Line 1

1000001
Line 2

1100001
Line 3

1000011
Line 7

1000001
Line 8

1000001
Line 9

Then the line clock is again clocked, incrementing the
line counter to Line 10. All characters in the row are
scanned. (Figure 6) The output of the character generator for lines 10 to 16 is all lows. This provides a vertical
space between rows. The number of lines used to space
can be controlled by clear going low after the desired
number of lines of vertical space have been generated.

After the access time has elapsed (tasl = 350 ns), the output of the ROM for Line 1 of the character (N for this
example) can be loaded into the shift register. When
load enable is brought low. the shift register is loaded

2.'.
1

COLUMNS
3 4 5

•

•••
5.•• •• ••
7. ••••
••

CH 1

ROW 1 _______

3 ••

4 •

LINES

•
•
•

8 •

9 •

10
11

OOTS

DISPLAY CAN BE UP TO
80 CHARACTERS/ROW
AND 24 ROWS

VERTICAL SPACE

13
14

• • • • 0

12
SPACE

CH 2

0 0 0
0
0

RDW''''''_

DTD D • • • • 0
--i 1-----HORIZONTAL SPACE

COLUMN 1

COLUMN"N"~

FIGURE 6, Display Example

FIGURE 5, Character Example

6-24

Clear: Active low clear for mod 16 row counter, (can
be used to truncate mod 16 counter).

Next, the first line of the first character of the seco[1d
row is addressed and scanned.This continues until the 9th
line plus lines for vertical spacing of the last character
in the last row has been scanned. At this time the
display field has been written. For a CRT Display, it is
necessary to refresh the display. Displays are typically
refreshed 30 to 50 times each second. Memory is required
to store the character address so that they may be called
up when required for refresh.

Line Clock: Clock that advances the line counter.
Advances counter on the 10w·to.lJigh transition.
Clock Control: Enables line clock when high and
disables line clock when low.
Load Enable: Active low load command which routes
data from the character ROM to the "0" inputs of the
/·bit shift register.

Figure 7 is the connection diagram and logic symbol.

Dot Clock: A low·to·high transition of the dot clock
loads the shift register if load is low or shifts data if load
is high.

DEFINITIONS

Output Enable: An active low output enable. When high
the output is in the Hi·Z state.

A 1-A6: Character address. A 5·bit code which selects
1 of the 64 characters in the font.

Output: A TTL TR I-STATE output buffer.

Dual-In-Line Package
16

A1
ADDRESS LATCH

CONTROL
12

CLEAR

LINE CLOCK

A5
A6

OUTPUT ENABLE
OUTPUT

CLOCK CONTROL

Vec

LOAD ENABLE
DOT CLOCK

GNO

TOP VIEW

FIGURE 7(a). Connection Diagram

ADDRESS LATCH

CONTROL
A1
A2
A3
A4
A5
A6

LINE
CLOCK

CLOCK
CONTROL

FIGURE 71bl. Logic Symbol DM8678

6·25

co
.....
<0
co
:?!

128 Characters with the
DM8678

National Semiconductor
W. Johnston
C. Mitchell

The purpose of this brief is to describe the control logic
necessary to generate 128 characters and attributes .
The example used is for the upper and lower case set of
characters from the DM8678BWF and DM8678CAE
with cursor (underl ine) and blanking.

Second, the standard ASCII format requires that bits
6 and 7 be exclusive-ORed to select upper and lower
case characters. Pipelining this altered most significant
bit (bit 6 and bit 7) synchronizes the signal to control
the OUTPUT ENAB LE of the appropriate character
generator. This either enables or TR I-STATES® the
DM8678 outputs. Figure 1 shows an implementation
using the DM7486-exclusive-OR gate and the DM8511gated D fl ip-fl op.

-Q,)

.J:
. J:

en
....

Q,)

co
....

.J:

There are 2 important factors to consider when using
2 DM8678's. First, the character set of each ROM pat·
tern is based on a 6·bit ASCII format. A seventh bit
must be added for selection of upper or lower case.

,....
~

1/2 DM7486
ASCII BI17
ASCII BIT 6

CLR
Q

r
-

ADDRESS
LATCH
STROBE

at---

STRB
j

DM8511

CLR

B
G2

r-- P> Gl

il
G2

P-

J.
DU TPUT ENABLE (UPPER CASEI

ASCII BIT 5

ASCII BIT 4

ASCII BIT 3

ASCII BIT 2

ASCII BIT 1

COMBINED SERIAL OUTPUTS
(UPPER AND LDWER CASE)

DMB678
BWF

LOAD ENABLE

OUTP UT ENABLE (LOWER CASE)

i . . - A6

I-- r-

A5
A4

DM8678
CAE

DOT CLOCK

A2
Al

LINE
CLOCK

CLOCK
CONTROL

FIGURE 1. Upper and lower Case Character Generator

6-26

The selection bit is latched into the first flip-flop on the
trailing edge of the address latch strobe. If the strobe of
the DM8678 is not in use (as in low character rate
systems), then this first flip-flop (A) may be eliminated.
The second flip-flop (B) is gated on by the same signal
that drives LOAD ENABLE on the character generator.
Clocking of both the DM8678's and flip-flop (B) occurs
on the positive ed~e of the dot clock. Q and Q drive the
OUTPUT ENABLE inputs of the lower and upper case
generators, respectively.

character blanking or underlining. Here the attribute
bits are pipelined using DM8511's and DM7474's.
In Figure 2, a cursor (which occurs on the video display
as an underline) is gated on only during the eleventh
scan line of a character. Apart from this gating the
attributes are pipelined in the same manner as the
OUTPUT ENABLE's in Figure 1, except that the out·
puts of the DM8511 's are logically combined with the
video.

Figure 2 indicates how attribute bits can be inserted
into the combined serial output of Figure 1 to produce

1/20M7474
CURSOR BIT

112 OM8511

STRB

VIDEO

LINE 11
DOT CLOCK
1/20M7474
CHARACTER
BLANK BIT

1/20M8511

LOAOENABLE--------------------------------~

COMBI NED SERIAL OUTPUT ______________________________________....
(FROM FIGURE 1)

FIGURE 2. Pipelining Attribute Bits

6-27

...o

.!!!
~

DM8678 Character
Generator Emulator

National Semiconductor
C. Mitchell

When developing new character fonts or graphic symbol
sets for the DM8678 character generator, it is desirable
to have a field programmable emulator. The purpose of
this brief is to describe such a circuit.

The counter/adder combination provides an altered line
count to the memory when the B inputs are activated.
In this way, the address representing line location is
shifted by an amount equal to the 2's complement of
the input (Figure 2). Another way to accomplish this
would be to offset the PROM location of the descended
character (in other words, the starting location of a
y, for example, would be at line count 4 instead of 0,
as in a normally placed character). However, use of an
adder in conjunction with the counter provides a closer
approximation to operation of the DM8678.

...o
...CO

I:
Q)

...

CJ
CO
CO
J:

...

CO
,....
CO
CO

::E

Working from the DM8678 block diagram, the device
can be partitioned into MSI logic components and
bipolar PROMs .
A DM86S75 hex latch will serve as a functional replace·
ment for the address input latch. Address decoding and
output mUltiplexing are included in modern memories;
therefore, the 3 blocks depicting the memory function
are realized with PROM. DM74S574 1024 x 4 PROMs
are used here, but any 4-bit or 8-bit wide bipolar PROM
will suffice, depending on programming and partitioning

Note that the DM86S75 latch is inverting; therefore,
address inputs as programmed into PROM should
be complemented.

preferences. *

Alternatively, an inverter may follow the latch, or 2
DM7475 latches may replace the DM86S75.

The line count may be emulated with a DM74161
counter and DM74LS283 adder. Inclusion of the adder
is required if descending characters (I.e., y, g, j, etc.)
are desired.

The output stage may be implemented with a DM74166
shift register and a TR I-STATE® buffer completes the
circuit (Figure 3).

For a 4-line descent, the B inputs of the adder should be
driven to 1100 by a PROM Tag Bit (for a 2-line descent,
B inputs should be 1110, etc.)". The Tag Bit (active
high) should be programmed into the PROM for each
descending character. Locations addressed by line counts
1"100-1111 should be programmed (except for Tag Bits)
as all zeros.

*Note that the DM74S574 is pin compatible with the MM2114
1 k x 4 read/write memory. Use of the MM2114 would be

attractive in emu lations where a more exhaustive study of
symbols is desired.
**4-line descent is generally used in 7 x 9 character fonts, 2-line
descent is used with 5 x 7 characters.

---------T---------------ADDRESS LATCH
A
B
CONTROL
LATCH

A6
LATCH

LATCH

64 X 64 BIT
FDNT
MATRIX

lATCH
AJ

LATCH
A2

LATCH
A1

c-------- L
CLOCK
CONTROL

LINE
CLOCK

tm\Ii

--I
I
I

9·TO·1 MULTIPLEXER

I
LL._T"_,.....,-rT""T---r--A
__ .1. __ ___ _
I

I
I

---------------~
I
I

0
TAI·STATE'~

OUTPUT SHIFT REGISTER

I C~g~K

FIGURE 1. Block Diagram
6-28

LOAD
ENABLE

OUTPUT
BUFFER

OUTPUT
ENABlE

SERIAL
OUTPUT

TAG BIT

COUNT

ADDRESS

LINE NO.

0
1

1100

1
2

I { 1ADDRESS

r--{EJDDER }

1101

1110

1111

0000

1001

r-------~-----------L------,
I

ALL
COMPONENTS _ _
CORNER
POWER

CLOCK

1100

TAG BIT

PROM

t
9

t
FIGURE 2

Al A2 A3 A4 A5 A6

(,I. 16 11011Zj1.

(

ADDRESS lATCH CONTROL

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I

11 13

5
1 A6
AZ
DM74S574
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~

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OUTPUT

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OUTPUT

ENABLE

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LINE

CLOCK

CONTROL

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CLOCK

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elR

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5 10 1'" 12 14

":"

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PINS

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LOAD

ENABLE

FIGURE 3

6·29

Section 7

Charge
Coupled Devices
Recent breakthroughs in n·channel MOS technology
have made possible the implementation of single chips
containing 64k bits of storage, based on memory cells
called charge coupled devices. Anticipated eeo yields
in volume production will be much higher than more
conventional dynamic RAM of the same density, because
the basic eeo cell itself contains no contacts, no metal,
and no diffusions. Thus, bit cost is expected to be a
factor of three or more lower than that of dynamic
RAM as eeo production grows in the early 1980s. As
a result, much innovation is occurring in equipment
designs now on the drawing boards. This section is
intended to help you in the development of new archi·
tectures for your next generation systems.

The MM2464: A Practical
Charge Coupled Device for
Digital Memory Applications

National Semiconductor
Memory Application Note
e. B. Mitchell

,()~.s

~~~

~~y*

INTRODUCTION

• ecos i are constructed using MaS processes very
similar to those used for'dynamic RAMs; therefore,
power supply voltages and interface requirements are
familiar.

Charge-coupled devices (CCOs) exhibit the highest
density silicon based memory capacity available. Because
storage and transfer are achieved by multi phase clocking
of closely packed MOS capacitors, significant amounts
of circuit detail may be eliminated from a memory cell.
The resulting increase in density may exceed four times
that of a dynamic RAM using similar processing technology. Thus, the recent introduction of a number of
very dense, sequentially accessed memory components,
including the MM2464 64k-bit CCD from National
Semiconductor. CCOs provide a practical answer to a
need in memory technology. This need becomes apparent
upon examination of current memory products with
respect to access time and density. On one hand are high
speed medium density devices such as semiconductor
RAM and magnetic core, on the other are techniques
typified by high density and low speed. These include
tape and disk storage. The gap in access time runs from
the one or two microsecond upper boundary of RAM
and core based systems to a lower bound on disk
systems of tens of milliseconds. CCOs fall within this gap
providing a significant density increase over RAM and
latency times of hundreds of microseconds. Therefore,
the CCD provides a powerful tool in the system design
engineer's effort to increase memory size and bandwidth.

• The ceo is a serial device; therefore, the architecture
will reflect this sequential nature.
• As ceos are a natural result of the growth of MaS
technology, it is reasonable to eKpect products to
mature in much the same way as MOS dynamic
RAMs and microprocessors have grown (i.e., cost,
size, speed, interfacing, etc.).
There are currently two major design philosophies in
eeos intended for digital storage which are reflected in
the architecture of the devices available. These two
architectures are referred to as "long loop" and "short
loop." In both cases, the devices resemble a number of
recirculating shift registers arranged in parallel (figure 1).
Each SIR input and output is then addressed to provide
a path to the package I/O pins.
The terms long loop and short loop relate to the shift
register length, N. Long loops seem to have reached a
de facto standard of N = 4096 bits, while for short loops
N = 256 bits. Long loop eeos are generally constructed
with a buried or bulk eco channel while short loop
parts are built with surface channels. Buried channel
techniques tend to result in devices with lower signal
levels than those of surface channel parts, hence refresh

What are the basic facts concerning eCOs?
• As mentioned, information is stored in the form of
charge on a capacitor; therefore, the eco must be
refreshed, as in MaS dynamic RAM.

.-BIT RECIRCULATING SHIFT REGISTER

ll-+

CLOCKS

M REGISTERS

DOUT

Figure 1. Block Diagram

*Oue to publishing deadlines, some of the circuit diagrams
tained in this note have not yet been fully tested.

Con~

7-1

requirements of long loop parts may be more demandi~
than those of the short loop configuration. Charge
biasing (fat zero) is generally done in surface channel
devices to increase noise immunity and mayor may not
be done in bulk devices. Surface channel CCO designs
produce a less complex manufacturing sequence, as well
as more efficient sense amplifier realizations.

clock capacitance. Many system designs constrained by
such high capacitance have required as many as one
clock driver package for every three CCO packages. Even
more devastating than the parts count requirement has
been the effect of these clock drivers on system power
levels. Although the CCO itself is inherently a low power
device at lower clock speeds, addition of clock drivers
has raised system power requirements significantly. This
is not true of the MM2464, where a single OS3628 5-volt
clock driver can easily service a megabyte or more of
memory. Alternatively, TTL or CMOS can be used to
provide clock signals. The MM2464 requires only 2 TTL
level clock signals, SENSE ENAB LE (SE) and SYNCHRONIZE (SYNC). SYNC occurs once for every four SE
cycles_ To the user it appears as if SE is clocking the
256-bit shift registers, and indeed, the device may be
viewed in this manner. By examining the diagram (figure
2) below one can see this is not actually the case.

While long loop CCOs may be clocked faster than short
loop components, clock rate is not usually the most
important speed parameter in a CGO. Latency time, or
the amount of time it takes to get to any given word, is
generally a more critical requirement. Due to the rela·
tively few clock cycles required both the average and
maximum latency times of a short loop CCO are much
less than those of a long loop CCO. When applying long
loop CGOs it is normal to use them in a serial mode, in
other words, treating the device as 16 (in a 64k·bit part)
dynamic shift registers. Another mode becomes available
with a short loop CCO. A page (each position in the shift
registers is known as a page) in a short loop part is 256
bits wide, a size practical for treatment as read/write
memory. With this treatment comes high data rate and
greatly reduced power dissipation. Because National
Semiconductor is interested in bringing viable memory
components with a wide range of applications to the
market place, the MM2464 is configured as a 64k short
loop device.

Each of the 256-bit shift registers is composed of four
63·bit CCOs and a decoding/sense amplifier/multiplexing
circuit, with SYNC providing the stimulus for clocking
the array. The arrangement provides a major advantage
over a continuous 256·bit register while maintaining a
single sense amplifier. As power dissipation in a CCO is
directly dependent upon clock rate (CV 2 f), higher
speeds are made possible for a given power dissipation as
SYNC occurs at one fourth the rate of SE. SE provides
the clocking signal for the multiplexion, selecting each
of the four register outputs for amplification. Upon
completion of this refresh operation for the four bits in
the holding register, SYNC clocks four new data bits
into the register and the sequence is repeated. This one
bit delay in the holding register provides the extra four
bits to produce the 256·bit register (63 x 4 + 4 ~ 256).

MM2464 TTL COMPATIBLE 65,536·BIT CGO
The single most significant improvement achieved by the
MM2464 over existing 64k CCOs is its ease of interface.
Previous CCOs have required multiple (3 or more) high
level clocks and exhibited very large clock and clock-to-

HOLDING
REGISTER

TRANSMISSION
GATES

HOLDING
REGISTER

SYNC~~~-------------------------------------t--~

Figure 2. Block Diagram of One 2S6-Bit Recirculating Shift Register

7-2

period of time between the rise of SE and the rise of
SYNC. 1004 is a constant term for each device. A brief
study of the equation and the values for the 100i in
the data sheet indicate the page mode of operation can
be extremely attractive. Figure 3 reflects the VOO
power supply current versus the modes and frequencies
of operation.

257 of these registers are provided on the MM2464. The
odd (or 257th) register provides a reference level for the
sense amplifiers, thus the requirement for a number of
clock cycles immediately following power·up to stabilize
the reference voltages. This technique of providing
power supply and temperature stable reference voltages
reveals another advantage of the short loop configura·
tion. Addition of a 256·bit reference loop requires only
1/256 of the device die area to accomplish. In a 4096·
bit oriented device 1/16 of the die area would be
necessary to construct a similar reference loop. Through
comparison and feedback techniques utilizing the refer·
ence loop, noise immunity is significantly enhanced.
The remaining 256 registers are available as storage.

SOr--------------------------------------,
70

100 vs DATA DR CLOCK RATE
60

Each register I/O in the memory array is accessible
through a data steering multiplexer controlled by an
eight·bit address port. A TRI-STATE® Oata output and
a Oata input are provided wh ich may be tied together in
common bus systems provided the Write Enable (WE)
signal is lowered prior to or simultaneously with Chip
Enable (CE) when writing data into the part. The 256·
bit page may be utilized as RAM within the restraints
imposed by the timing limitations expressed in the AC
electrical characteristics in the MM2464 data sheet.

SERIAL "
MODE /.

/ ' Zm.

--~~

A refresh cycle in the MM2464 is defined as a single
passage of all data bits through the sense amplifier for
regeneration. Thus, refresh takes place every 256 SE
cycles. It is worthwhile to recall that refresh in a CCO is
required because of charge degradation due to thermally
generated "dark current" and transfer inefficiency
between cells. Therefore, in systems with controlled
environments, refresh, or maximum page time require·
ments, may be adapted to temperature conditions (for
refresh, 2tREF for every 10°C decrease in temperature).

REFRESH

"
4m.
REFRESH OR
/,~REFRESH
SEARCH MOOE\,; '/
10m.
,{/
LREFRESH

_ - .... ......------

100kHz

MODE

1 MHz

Figure 3. 100 vs Clock or Data Rate @+70°C

The reduced number of clock cycles permits far lower
power supply drain in page mode than that in serial
mode even though data rates are higher. The page mode
current characteristics shown are plotted versus data rate
and reflect the use of a burst refresh scheme where the
burst frequency is either the maximum clOCk frequency
of the CCO or a frequency,

SYSTEM DESIGN CONSIDERATIONS

f~ ____l_ __

tREF - N . tCYC

Power Supply Considerations

256

Power supply voltage requirements of the MM2464 are
12V, -5V and ground. Power supply current may vary
widely according to system design and clock speed.
This variation is reflected in the equation below.

where tCYC is the read or write cycle time in page mode
and N is the number of memory access cycles required
during the refresh period tREF to achieve a given data
rate.

tCE
N
tSSYl
100AVE ~--IOOl +-ID02 +---1003 + 1004
t
t
t

Obviously, under the condition of current drain
described above, current variations will exist on system
power supply lines. It is advisable to provide bypass
capacitors to ground, located in close proximity to the
VOO pin, for each MM2464 in the system. It is further
recommended to make these capacitors relativelY large
(0.1 flF) in the early development stages and adjust the
size for acceptable noise levels after printed circuit board
layout is implemented. Similar precautions should be
made with respect to VBB transient currents. Power
supply layout and distribution should follow the same
rules as those utilized in dynamic RAM design." Clock
and data distribution will be far less critical than in CCO
or RAM designs with high voltage and/or high capacitance
clocks; however, good practices will always provide more
margin for noise immunity and device variation.

1001 -1004 are parameters listed in the data sheet and
t should be a span of time covering all modes of use of
the component (i.e., t will be the period of a cyclic wave
form which reflects the system operation). In most
systems, the first two terms of the 100 equation will be
first order effects and the latter two of second order.
tCE is the amount of time (during t) in which the chip
enable line is active; therefore, some attention should be
given to generating a minimum chip enable "on time"
(tCE) in power critical systems. Likewise, as "N" is the
number of SE cycles during t, clock frequencies should
not exceed those needed for required system perfor·
mance. Adaptive clocking (i.e., minimum clock rate
during periods when the system is not in use) may also
be attractive. Although not so critical, the third portion
of the current may be minimized, as can the first, by
careful control circuitry design. This term reflects the

*Dynamic RAM Board Design Made Easy, Memory Applications

Handbook.

7-3

Clock Generation

Ease of clock implementation will be a function of desired system requirements. Figure 4 depicts one logic realization for SE
and SYNC at a 1 MHz clock rate; figure 5 shows the waveforms. Several clock generation circuits are depicted; selection of one
of these will depend upon design preferences. The circuit schematic of figure 6 presents alteration of the 1 MHz generator to
allow maximum clock rates. (Refer to section on Serial Mode Techniques.) Figure 7 presents a less complex circuit which may
be realized with CMOS logic. Each of these implementations has been achieved with a clock enable input to allow page or search
mode operation. Note that if clock rates exceeding 770 kHz are not required a simple 50% duty cycle SE clock may be utilized
as in figure 8.

CLOCK ENABLE

"1"

"0"

.------1.....[:><..... SE2
"3

,.-co. . . . --t-

SYNCl

~C----If- SYNC2

t-cv---""1r-

SYNCJ

I
_________ J

Figure 4. 1 MHz Clock Generator

lOMHz

OlK

••
·0

·c
SE (Qol

., --.l

".,

.,"

U
J

·3

SYNC (Il4J

______________________-Jr--lL-_______________________________

Figure 5. Waveforms for 1 MHz Clock Generator

7·4

COUNT ENABLE

SYNC

''I''

"0"

IL____________.....I
Figure 6. 1.23 MHz Clock Generator

.,~

1-7nnns __I_1

J5nn~

.2~

.3 ________~t~r-----,~
SE CLOCK RATE

Figure 7. CMOS 950 kHz Clock Generator

Figure 8. 750 kHz Clock Generation - 50% Duty Cycle SE Clock

"Refer to AN·IIS, CMOS Osciliators, CMOS DatabooK.

7·5

95D kHz

Refresh Techniques

Page Mode

Several techniques of achieving refresh are available to
the system designer. Among. these are burst refresh
(where a burst consists of 256/b clock cycles at maximum clock frequency and b is the number of bursts
during tREF - b = tREF/tPTM t ), distributed refresh
(one clock cycle each tREF/256 microseconds) and
adaptive refresh. An adaptive refresh circuit monitors
system utilization of the CCDs and the various timing
restrictions placed upon the memory, assuming command of the system to provide clocking when those
restrictions are exceeded. In the case of the adaptive
refresh SUb-system shown in figures 9 and 10, temperature has been added as a parameter in determining
the maximum page times and tREF, the refresh time.

As mentioned previously, the MM2464 may be treated
as read/write memory, and the same design techn iques
may be used for the CCD as are used for static RAM.
An address latch or register may be desirable at the card
edge for buffering and to meet address hold time require·
ments. Chip enable and READ/WRITE input specifica·
tions should be noted. A ready or busy signal should be
sent to the main system to prevent short cycling of the
system or the MM2464. This signal may be the "page
change required" signal of figure 10 in faster systems
or a decoded output of the page time counter in those
with slower reaction times.

Serial Mode
Serial mode consists of treating the MM2464 as a series
of addressable parallel shift registers, a worthwhile
configuration in display and scanner applications.
However, because of the power and speed considerations
and because there is no penalty in support parts count,
use of the CCD in page mode with addressing being performed by a counter is advisable in the majority of cases.
One exception to this will occur in systems where data
may be accepted with a random starting location. In
this case there is no latency time; the shift register
desired is immediately selected and data manipulation
commenced at once. When using the MM2464 in this
mode, care should be exercised with respect to docking
schemes such as the one shown in figure 6. Here the SE
off time with no SYNC pulse (tSC1) has been reduced
to data sheet minimum; this time is less than the minimum chip enable time (tCE). Regardless of mode of
operation, attention should be paid to the parameters
describing the relationship of SE and SYNC to CEo One
way of doing this is to assure that chip enable is active
(low) only when both SE and SYNC are in the low state.

Figure 9. Block Diagram of Adaptive Refresh Circuit

The temperature controlled oscillator generates the
clocks for two counters. The refresh counter is counted
up by the TCO and down by the SE clock; if a carry is
generated a clock cycle is required. A counter determines
page time and is reset each time SE occurs; if a carry is
generated a clock cycle is enabled. Although this type of
refresh control is the most flexible method, many applications such as CRT display and other serial data
systems will not need refresh control or may use much
less complex techniques requiring fewer components.

MM2464 APPLICATIONS
The MM2464 may be considered as an alternate choice
to either read/write memory or rotati ng magnetic
memory in a wide variety of applications. And, as is the
case with most innovative products, heretofore uncon-

sidered applications will arise. Several factors can be
indicative of applicability.

Search Techniques
Search mode differs from refresh mode only in speed.
While refresh mode implies clocking at very low rates
to maintain data integritY, search mode is intended to
advance the shift registers to a desired page as quickly
as feasible. To achieve this, a counter must keep track
of the present page location. In order to access a particular page, the controlling system loads the corresponding address into a register, the output of which is
compared to the count state. When the proper page is
reached, the clock is stopped and the system is signaled
that it may access the requested page. Figure 11 depicts
a block diagram of the circuit.

•

Bulk Store - wherever large amounts of data must
be processed, analyzed or maintained.

•

Serial Formats - where sequential ordering of information is inherent in the system philosophy.

•

Low Latency - where rotating memories must be
replaced or augmented to achieve greater bandwidth.

•

Human Interface - where dense random access
storage is required and lower speed than conventional
RAM is not detrimental.

Examples of each of these will be examined in varying
depth.

ttPTM ~ tSCYl MAX or tSSYl MAX, whichever is less.

7-6

."
4.7k

410

TEMPERATURE CONTROLLED

OSCIllATOR

DM74LS14
"1"

"'"

DM14LS74

"'"

"1"

"'"
EN'
ENT
RCO 1-_.c;PA;:';:.EC:...H:...A;;.;NG;;;E.c;AE.c;O;;.UI;;.;R;:EO,---,

2DM14LS160

Figure 10. Adaptive Refresh Circuit

Figure 11.

7-7

Bulk Store

Obviously, the CCO may be used, as indicated previously,
in page mode by a processor. However, the limitations
of maximum page-time may impose restrictions which
are unacceptable to the system designer. In such a case,
the addition of a R/W memory buffer may resolve the
dilemma. Figure 12 blocks out a memory configuration
consisting of a page mode driven array of MM2464s
which supplies data to, and accepts data from, a buffer
consisting of MM5257 4k static RAM. A one-half
megabit memory consisting of sixteen memory devices
and associated logic will fit on a reasonably small printed
circuit board and consume far less power than a system
consisting of RAM alone.

ferred to or from the buffer. In large systems, this
content addressable technique may be realized by the
implementation of wide word lengths and searching with
masked "don't care" states using either page/serial or
serial/page techniques. Information retrieval of the type
accomplished in large data processing systems thus may
be realized with minimal CPU time. Bulk memory
formats may consist of these techniques or others,
but in any case recognition of both the strengths and
weaknesses of CCOs can result in high performance
arch i tectu res.

Serial Formats

This type of system is expandable in many ways. Additional CCO storage is easily added to form multiple
megabyte capability. A second RAM page may be added
for increased throughput. Loading or storing one page
while utilizing the other could result in effectivelY a zero
latency time. An expansion of utility can be achieved
by switching from the absolute addressing of figure 12
to a scheme in wh ich the processor assigns a label to
each 4k page by writing the label in the first location in
the page. To find that page the control system compares
an inputted label to data in the shift register in location
zero wh ile operating in serial mode. When the label is
found a switch is made to page mode and data is trans-

Sequentially formatted data obviously lends itself to
CCO application and especially to the "square" arrangement of the MM2464. The block diagram of figure 13
depicts a possible configuration for a CRT graphics
system. Four MM2464s are arranged in parallel. The
resulting 1024-bit word contains the video data for two
512-bit horizontal scan lines of the CRT. The scan lines
are arranged one above the other on the screen in an

interlaced display; therefore, one of the 512-bit words
is accessed during each vertical scan. The CCOs are read
via page mode (during the horizontal sweep) at a rate of
2.4 MHz, allowing for 10 microseconds of horizontal
retrace time. Clocking the CCO once during horizontal

~)
PROCESSOR

DATA BUS

DM141S374
PAGE &
CONTROL
REGISTER

ceo 110

CARRY

LOAD

STORE
RAMI/a

MM5167

ARRAY

4kxB

RAM
RAM RIW ENABLE

READy--..-_ ...... , .

RAM RM

PROCESSOR
ADDRESS BUS

Figure 12.

7-8

ct DECODE

MM2464. The combination of low power operation and
ease of interface of the MM2464 and the programmability
of the processing device results in a programmable calculator with 8192 possible (8·bit) program steps or
memory locations. The processor can easily drive the
two CCO clocks, data input and chip enable with flag
and data lines as well as the address port with its own
address lines or latched data port.

retrace will not maintain data at extended temperature
ranges. In light of this, the clocking scheme shown in
figure 14 is proposed. Here the MM2464 is clocked eight
times during the first 31 horizontal retrace periods; on
the 32nd retrace the device is clocked nine times. Using
this method, the CCO page sequence is 0, 7, 15, ... ,
223,231,239, 248, 1, .... Figure 11 depicts a 512 x 512
interlaced black and white or two·tone display. Figure 15
shows four of these 512x512 blocks combined to
produce sixteen gray levels or color tones. The OiA
function may be implemented with two National integrated circuits, LM1889 and LM1886. Techniques
similar to the ones described here may be used in other
types of scanning devices.

Further application of CCOs may be found in distributed
systems such as point-of·sale terminals which reload data
each day from a central processing or storage unit and
require only human interface speed for random access.
SUMMARY

Low Latency Applications
CCO memory technology has progressed to the point
where a practical device for bulk memory storage has
evolved. This device, the MM2464, is a TTL compatible
65,536-bit CCO organized as 256 pages of 256-bit
memory. The CCO fulfills a requirement for a dense
memory with access times far less than those of rotating
magnetic media. A wide variety of applications exist for
charge coupled devices in many differing types of systems.

Multi-task or multiple user processing systems are often
limited in their performance by the latency time of disk
and tape memories. Th is performance can be improved
by addition of a buffer or swapping memory into which
the contents of the rotating memory may be loaded.
The lower latency time (orders of magnitude) and
density of the MM2464 make it an obvious choice for
the swapping memory, thus providing greatly increased
computer bandwidth at a fraction of the cost of other
techniques. The configuration of the MM2464 a!lows
construction of a disk·like sector oriented architecture
which permits the use of the same software drivers
utilized for the rotating device. Thus, the costly penalties of software revision are avoided in addition to
accomplishing increased user capacity.

A debt of gratitude is owed to Bob Pease of National's
Advanced Linear Integrated Circuit design group and
Nello Sevastopoulos and his staff in the Linear Applications section for their contribution of time and effort
in conceiving and testing the temperature controlled
oscillator.
RECOMMENDED READING

HUMAN INTERFACE APPLICATIONS

Charge Coupled Devices: Technology and Applications,

Moving from the macro world of the mainframe computer to the micro world of calculators, consider a
single·chip microprocessor or calculator oriented device
such as an INS8030 or COP420 coupled to a single

Edited by R. Melen and D. Buss, IEEE Press, NY, 1977.
Charge

Transfer

Devices,

Academic Press, NY, 1975.

VIDEO
DATA

AD
Al
A2
AJ

~!
A7
A8

L__-===~===~,-_

SCAN 112

Figure 13. %-Megabit CRT Displi· \' Memory Using CCDs

7·9

Sequin

and

Thompson,

DISPLAY

LINE 1

LINE 2

11111111

LINE 32

""1111

2."~

11111111

1111'"11

J
~~~~~~~ORIZONTAL :NRO;~2BL~~n

''''''"

' -8 CLOCK BURST

Figure 14.

ceo Clock Timing

During Display

16-BIT
OATA BUS

CRT
CONTROL

TIMING
GENERATOR

ADDRESS GENERATOR
AND
WRITE CONTROL

y
PROCESSOR ADDRESS BUS

Figure 15. CeO-Based Color Graphics CRT Display

7-10

Section 8

Memory
Support Components
Memory support components are unlike ladies' support
garments. Memory support circuits don't merely enhance
the appearance of memories; memories must have the
support circuits to work at all. A memory system does
not have the option of going braless; it must have the
necessary voltage regulators, clock drivers, and registers
to be functional. A few concepts are presented here.
For further, in-depth applications information, consult
the National Voltage Regulator Handbook and the
Interface Integrated Circuits Data Book.

s::

Memory Support Circuits

S
en
c

National offers a selection of memory support circuits
to facilitate the interface of memory components in
systems architecture. The memory support circuits were
developed specifically to accommodate the addressing,
clocking, data I/O, and control signals associated with
memory systems application as shown in figure 1.
Additional circuits are available to interface with data
bus structured computers and microprocessors. For
additional information contact National's Interface
Product Marketing Manager.

time of the OS3628 is as fast as or faster than those
of the 74S TTL, but most obvious is the rise time of
the OS3628 - much faster than that of the 74S TTL.
In addition, the 74S has an objectionable glitch in its
rise time. The output high (VOH) level of the OS3628 is
higher driving capacitance due to a bootstrap effect in
the circuit.
The switching response of the circuits interfacing with a
memory array is important since any delay subtracts
from the overall memory access time. The switching
response driving a capacitive load is more important;
as an example, the address drivers might be expected to
drive 420 pF in a memory containing 64 MOS RAMs
with 5 pF input capacitance each plus 100 pF of board
capacitance. The same is typical of clock signals, select
signals, and read/write signals.

FEATURES OF THE TTL LEVEL MOS DRIVERS

Figure 2 compares the switching response of the OS3628
with a 74S TTL gate. Two features can be observed from
the switching waveforms: 1) the OS3628 is as fast as
the 74S TTL driving TTL loads, and 2) the output high
level (VOH) of the OS3628 is higher than that of the
74S TTL.

The input logic levels of MOS RAMs are generally higher
than TTL gate levels (typically 400 mV higher). Therefore, the higher output high level (VOH) of the OS3628
is preferable for noise immunity and switching overdrive.

In a memory system composed of MOS RAMs the load
is capacitive and not resistive. Figure 3 compares the
switching response of the OS3628 with a 74S TTL
gate driving capacitive loads of 50pF, 150pF, and
300 pF. The switching waveforms show that the fall

REFRESH
COUNTER

The features of the OS3628 are typical of the other
TTL level memory support circuits shown in the Selection
Guide.

ADDRESS
DRIVER

I
r

-------- ---

I
CLOCK
DRIVER

-.....,
I

MDS
RAM MATRIX

I
I

~-------~~-------~

I/O

Figure 1. Memory System Block Diagram

8-1

CHIP
SELECT
READ/WRITE

DAMPING RINGING OF CLOCK SIGNALS

has a 15 n dampening resistor, or the OS3679 which is
functionally the same without a dampening resistor.

Ringing of clock signals in a system where the logic
fan-out is less than lOis not generally a big problem,
but with higher fan-out the increased capacitive load
associated with even a small amount of wiring inductance
is a problem_ When the capacitance is small the switching
currents are small, but as the load increases the increased
current through the inductance makes the effect of the

FALL-THROUGH LATCH

In many memory applications a holding register is
required either for address or data I/O. Most commercially available registers have an objectionable propagation delay since the circuit's response is the sum of many
gate delays. The address and data I/O paths are critical
to the memory system access time and a faster register
is preferred. The memory support circuits provide a
selection of faster latches_ These circu its are the
OS3645175 and the OS3647/77/147/177 series. These
registers are faster since the latch function is in parallel
instead of series with the Signal path.

inductance increase.

To reduce the associated ringing on the clock signals a
resistor may be placed in series with the output of the
clock driver to critically dampen the signal response.
Many of the memory support circuitS are available with
this resistor in the output, such as the OS3649 which

14820 OUTPUT

TTL lOAD
Cl=50pF
Rl = 280<>

Figure 2. Switching Response with TTL Load

8-2

Memory Support Circuit Selection Guide

Device Number & Name

Available 5 Volt
Second
Clock
Source
Drivers

DS3628
Octal TRI_STATETMo MOS Driver

12 Volt
Clock
Drivers

4k
RAM
Address

16k
RAM
Address

Drivers

Timing

8.
Data
1/0

DS3640/70
Quad TRI-SHARE™o Port Driver

DS3642/72
Dual Bootstrapped MOS Clock Driver

DS3643/73
Quad Decoded MOS Clock Driver

DS3644/74 (3235. MC3460)
Quad MOS Clock Driver

DS3245
Quad MOS Clock Driver

DS3645/75
Hex TRI-STATE MOS Driver latch

DS3646/76
6-Bit TRI-STATE MOS Refresh Counter/Driver
DS364 7/77 /14 7/177
Quad TRI-STATE MOS Memory I/O Register

Control
Drivers

DS3648/78
TRI-STATE MOS Multiplexer/Driver

DS3649/79
Hex TRI-STATE MOS Driver

DS36149/179
Hex MOS Driver

DS75322/DS3622
Dual TTl-to-MOS Driver

DS75361
Dual TTl-to-MOS Driver

DS75362
Dual TTl-to-MOS Driver

DS75364
Dual TTl-to-MOS Driver

DS75365
Quad TTL-to-MOS Driver

DP8304
8-Bit 8idirectional Transceiver

DP8216/26
4-Bit Bidirectional Transceiver

DS8T26/28
Quad TRI-STATE Bus Driver

DP8212
8-Bit Input/Output Port

CD4024B
7-Stage Ripple-Carry Binary Counter/Divider

·A trademark of National Semiconductor Corporation.

8-3

INPUT

\-+--+--+--+--+-/"--+--+S/DiV--+OS3628

OM74S20

--t--:-,

;--t---i--t--+-+--

OUTPUT 50pF LOAD

It
\
\

\
OS3628

DM74S20

---i--t-,

",
,

OUTPUT 150pF LOAD

1\
\

.....'....

.... ...f--t---i--t---

\_1

OS3628

--"1--+-

OUTPUT 300pF LOAD

'to-,

DM74S20

.....·-1

.... 1"
'.•• .j. ....

Figure 3. Switching Response with Capacitive Load

8-4

--l---

J-- +

......... ..,

''I-,,

National Semiconductor
Application Note 182
Robert Dobkin
April 1977

Improving Power Supply
Reliability with Ie
Power Regulators

:e-.3-

-"0
::r
...

-0
o-oj
~.

otO

:e-C
CDO

...:CCD:e

Three-terminal IC power regulators include on-chip
overload protection against virtually any normal fault
condition. Current limiting protects against short circuits
fusing the aluminum interconnects on the chip. Safearea protection decreases the available output current at
high input voltages to insure that the internal power
transistor operates within its safe area. Finally, thermal
overload protection turns off the regulator at chip
temperatures of about 170 C, preventing destruction
due to excessive heating. Even though the IC is fully
protected against normal overloads, careful design must
be used to insure reliable operation in the system.

Newer regulators have improved current limiting circuitry. Devices like the LMl17 adjustable regulator,
LM123 3A,5V logic regulator or the LM120 negative
regulators have a relatively temperature-stable current
limit. Typically these devices hold the current limit
within ±10% over the full -55°C to +150°C operating
range. A device rated for 1.5A output will typically have
a 2.2A current limit, greatly easing the problem of
input overloads.

Many of the older IC regulators can oscillate when in
current limit. This does not hurt the regulator and is
mostly dependent upon input bypassing capacitors.
Since there is a large variability between regulator types
and manufacturers, there is no single solution to eliminating oscillations. Generally, if oscillations cause other
circuit problems, either a solid tantalum input capacitor
or a solid tantalum in series with 5n to 10n will cure
the problem. If one doesn't work, try the other.

SHORT CIRCUITS CAN OVERLOAD THE INPUT

The IC is protected against short circuits, but the value
of the on-chip current limit can overload the input
rectifiers or transformer. The on-chip current limit is
usually set by the manufacturer so that with worst-case
production variations and operating temperature the
device will still provide rated output current. Older types
of regulators, such as the LM309, LM340 or LM7800
can have current limits of 3 times their rated output
current.
The current limit circuitry in these devices uses the
turn-on voltage of an emitter-base junction of a transis·
tor to set the current limit. The temperature coefficient of this junction combined with the temperature
coefficient of the internal resistors gives the current
limit a -0.5%tC temperature coefficient. Since devices
must operate and provide rated current at 150°C,
the 25°C current limit is 120% higher than typical.
Production variations will add another ±20% to initial
current limit tolerance so a typical lA part may have a
3A current limit at 25°C. This magnitude of overload
current can blow the input transformer or rectifiers if
not considered in the initial design-even though it does
not damage the IC.

Start-up problems can occur from the current limit
circuitry too. At high input-output differentials, the
current limit is decreased by the safe-area protection.
In most regulators the decrease is linear, and at input·
output voltages of about 30V the output current can
decrease to zero. Normally this causes no problem since,
when the regulator is initially powered, the output
increases as the ihput increases. If such a regulator is
running with, for example, 30V input and 15V output
and the output is momentarily shorted, the input·
output differential increases to 30V and available
output current is zero. Then the output of the regulator
stays at zero even if the short is removed. Of course,
if the input is turned OF F, then ON, the regulator
will come up to operating voltage again. The LM117 is
the only regulator which is designed with a new safe-area
protection circuit so output current does not decrease
to zero, even at 40V differential.

One way around this problem (other than fuses) is by
the use of minimum size heat sinks. The heat sink is
designed for only normal operation_ Under overload
conditions, the device (and heat sink) are allowed to
heat up to the thermal shut-down temperature. When
the device shuts down, loading on the input is reduced.

This type of start-up problem is particularly load
dependent. Loads to a separate negative supply or
constant-current devices are among the worst. Another,
usually overlooked, load is pilot lights. Incandescent
bulbs draw 8 times as much current when cold as when
operating. This severely adds to the load on a regulator,

8-5

CD ...

to(/)

£C

Q)"O
-"0
0
-.,<

"':c
CD

-_.

and may prevent turn-on. About the only solutions are
to use an LM 117 type device, or bypass the regulator
with a resistor from input to output to supply some
start-up current to the load. Resistor bypassing will not
degrade regulation if, under worst·case conditions of
maximum input voltage and minimum load current, the
regulator is still delivering output current rather than
absorbing current from the resistor. Figure 1 shows the
output current of several different regulators as a func·
tion of output voltage and temperature.

Perhaps the most likely sources of transients are external
capacitors used with regulators. Figure 2 shows the
discharge path for different capacitors used with a posi·
tive regulator. Input capacitance, C1, will not cause a
problem under any conditions. Capacitance on the
ground pin (or adjustment pin in the case of the LMl17)
can discharge through 2 paths which have low current
junctions.

If the output is shorted, C2 will discharge through the
ground pin, possibly damaging the regulator. A reverse·
biased diode, D2, diverts the current around the regulator, protecting it. If the input is shorted, C3 can
discharge through the output pin, again damaging the
regulator. Diode D 1 protects against C3, preventing
damage. Also, with both D 1 and D2 in the circuit,
when the input is shorted, C2 is discharged through both
diodes, rather than the ground pin.

When a positive regulator (except for the LMl17) is
loaded to a negative supply, the problem of start-up
can be doubly bad. First, there is the problem of the
safe·area protection as mentioned earlier. Secondly,
the internal circuitry cannot supply much output cur·
rent when the output pin is driven more negative than
the ground pin of the regulator. Even with low input
Voltages, some positive regulators will not start when
loaded by 50 mA to a negative supply. Clamping the
output to ground with a germanium or Schottky diode
usually solves this problem. Negative regulators, because
of different internal circuitry, do not suffer from this
problem.
DIODES PROTECT
CHARGE

AGAINST

CAPACITOR

In general, these protective diodes are a good idea on all
positive regulators. At higher output voltages, they
become more important since the energy stored in the
capacitors is larger. With negative regulators and the
LMl17, there is an internal diode in parallel with D1
from output·to-input, el im inating the need for an
external diode if the output capacitor is less than 25,uF.

DIS-

It is well recognized that improper connections to a 3terminal regulator will cause its destruction. Wrong
polarity inputs or driving current into the output (such
as a short between a 5V and 15V supply) can force high
currents through small area junctions in the IC, destroying them. However, improper polarities can be applied
accidently under many normal operating conditions,
and the transient condition is often gone before it is
recognized.

Another transient condition which has been shown to
cause problems is momentary loss of the ground can·
nection. This charges the output capacitor to the unregulated input voltage minus a 1-2V drop across
the regulator. If the ground is then connected, the output
capacitor, C3, discharges through the regulator output
to the ground pin, destroying it. In most cases, this
problem occurs when a regulator (or card) is plugged
into a powered system and the input pin is connected

3.5
3

5....
::'a:i
a:

~
....

:::>

2.5
2
1.5

- - - POSITIVE REGULATOR
LM117, LM120
-

r---

; ; : "L,

...
r- --'

Ti = -55°C

I I

L~117

~
-, ~ 1"',

~ Ti=25°C

~~
, ,, -....:: ~l'

0.5

T·=
J 150°C' ,

LM120

0
10

INPUT·OUTPUT DIFFERENTIAL (VI

FIGURE 1. Comparison of LM117 Current
Limit with Older Positive Regulator

8-6

before the ground. Control of the connector configura·
tion, such as using 2 ground pins to insure ground is
connected first, is the best way of preventing this prob·
lem. Electrical protection is cumbersome. About the
only way to protect the regulator electrically is to make
02 a power zener 1 V to 2V above the regul ator voltage
and include lOQ to 50Q in the ground lead to limit
the current.

THERMAL LIMITING GIVES ABSOLUTE PROTECTION

Without thermal overload protection, the other protection circuitry will only protect against short term
overloads. With thermal limiting, a regulator is not
destroyed by long time short circuits, overloads at high
temperatures or inadequate heat sinking. In fact, this
overload protection makes the IC regulator tolerant of
virtually any abuse, with the possible exception of highvoltage transients, which are usually filtered by the

LOW OPERATING TEMPERATURE INCREASES LI FE
Like any semiconductor circuit, lower operating temper·
ature improves reliability. Operating life decreases at
high junction temperatures. Although many regulators
are rated to meet specifications at 150° C, it is not a
good idea to design for continuous operation at that
temperature. A reasonable maximum operating tempera·
ture would be 100°C for epoxy packaged devices and
125°C for hermetically sealed (TO·31 devices. Of course,
the lower the better, and decreasing the above tempera·
tUres by 25°C for normal operation is still reasonable.

capacitors in most power supplies.

One problem with thermal limiting is testing. With a
3·terminal regulator, short·circuit protection and safearea protection are easily measured electrically. For
thermal limiting to operate properly, the electrical
circuitry on the IC must function and the IC chip must
be well die-attached to the package so there are no hot
spots. About the only way to insure that thermal limiting
works is to power the regulator, short the output, and
let it cook. If the regulator still works after 5 minutes
(or morel the thermal limit has protected the regulator.

Another benefit of lowered operating temperatures is
improved power cycle life for low cost soft soldered
packages. Many of today's power devices (transistors
includedl are assembled using a TO·220 or TO·3 alumi·
num soft solder system. With temperature excursions,
the solder work·hardens and with enough cycles the
solder will ultimately fail. The larger the temperature
change, the sooner failure will occur. Failures can start
at about 5000 cycles with a 100°C temperature excur·
sion. This necessitates, for example, either a large heat
sink or a regulator assembled with a hard solder, such as
steel packages, for equipment that is continuously
cycled ON and OFF.

This type of testing is time consuming and expensive for
the manufacturer so it is not always done. Some regulators, such as the LM 117, LM 137, LM 120 and LM123,
do receive an electrical burn-in in thermal shutdown as
part of their testing. This insures that the thermal
limiting works as well as reducing infant mortality. If it
is probable that a power supply will have overloads
which cause the IC to thermally limit, testing the regula·
tor is in order.

....
......
01

VIN~ ~VOUT

INPUT

OUTPUT

GNO

." Al

"'- Cl

"'- C2

~R2
.......
~

~02

-'-C3

FIGURE 2. Positive Regulator with Diode

Protection Against Transient Capacitor Discharge

8-7

....
.Q)...

>
s::

A Cheap and Easy
DC-DC Converter

National Semiconductor
Application Note 183
Paul Brown
May 1977

Many circuits do not live on a positive supply voltage
alone; they also require a negative supply voltage. A
separate transformer power supply can provide the
negative voltage, but this is not always a practical solution. If only a 5V logic supply exists, for example, or if
the system is battery powered, an alternate method of
obtaining the negative supply voltage must be found.

resistor to enable the tON/(tON + tOFFI of the switching transistor 01 to be more than 50%_

o
o
CI

o
C

W
"C

s::
co
a.

.s::.

--......- - - -....-oVOUT= -7V
*See Hints and Kinks

The pulse generator (Figure 3) is a standard astable
LM555 circuit with a diode in parallel with the discharge

FIGURE 5. Complete Circuit

8-8

DESIGN EQUATIONS

•
(VS - VSAT) + IVOUT - ¢11

tON = (L) (I LOAD)

0.2
C1=-80J.1s=160J.1F
0.1

Now calculate R 1, R2:

(VS - VSAT)2

•

R1 =

(VS - VSAT)
• tOFF =

tON

-42 J.1S

- - - - - - - - = 4.5k
1.8 - 5
(0.01 J.1F) In - - 1.8 - 10

IVOUT- ¢11

•

ILOAD

R2
tON

(0.01 J.1F) (0.693)

= 11.5k

C.VOUT

Resistors R3, R4 and R5 can be calculated from the
following considerations:

R1 = _ _ _ _to_FF_ _
C21n

3¢2 - Vs

For ilQ1(MIN) = 20, VOUT low from the LM555 = 1V
VBE(Q1)(MAX) = 1.2V

302 - 2VS

R2=

For IC(MAX) = 800 mA

tON
(0.693) C2

IB(MAX) = 40 rnA
(5-1-1.2)
R3 =
40mA

IVOUTI = (VBEQ2 + VZ1) (1 + : : )

70n

Allow for an overdrive factor of 3.5
Where: tON = Time Q1 is ON
tOFF = Time Q1 is OFF
Vs = Supply voltage
VSAT = Saturation voltage of Q1
C.VOUT = Peak-Peak output ripple
¢1 = VBE D1
¢2 = VBE D2

OUTPUT OF LMm

mCOLLEtTOR

R3 = 20n
Given:
VOUT
R4 + R5

Calculate R4, R5:

R5= VBEQ2+ V Z1 = ~ = 38k
VOUT
150J.1A

.---

~,------,

150 )lA, VZ1 = 5.1V, VOUT = -7V

-1.~~ ~

R4 + R5

F
-7V~

VOUT -6,9V

R4 = VOUT _ R5 =
150 )lA

'--------

TIMING CAPACITOR H3V

- 3Bk

1.67V~
L -_ _ _ _ _ _ _
• t
t

DERIVATION OF DESIGN EQUATIONS

FIGURE 6. Ideal Waveforms

Flyback Circuit (Figure 7)
SAMPLE CALCULATIONS
For the inductor
Given:

V=L~"" L~
dt

L = 550 J.1H, I LOAD (MAX) = 200 rnA, C2 = 0.Q1 J.1F,
¢2""'0.60V
Vs = 5V, VSAT = 1V, ¢1 = 0.7V,
VOUT = -7V, C.VOUT = 100 mVp-p

lit

v,
LJl

R3
Qt

Calculate tON, tOFF and C1:
(550J.1H) (0.2) (4+7.7)
(4)2
(550 J.1H) (0.2) (4 + 7.7)
tOFF = - - - - - - - - - (4) (7.7)

'ON = Q1SAT
'OFF = Q10FF
FIGURE 7. Flyback Circuit

*See Hints and Kinks

8-9

= 8.7k

During tOFF AI INDUCTOR = I LOAD + ICl

For tJ.t ~ tON

AIINDUCTOR ~

Vs - VSAT
L

From (5)
tON

(11
"IINDUCTOR

I LOAD [IVS - VSAT) + IVOUT - ¢lll
IVS - VSAT)

(6)

For At ~ tOFF
AIINDUCTOR ~

IVOUT - '1>11
tOFF

From (1) and (6)

(2)

tON

IL) (lLOAD) Ilvs-VSAT) +IVOUT-¢lil
0

(7)

For the capacitor
dv
ICl = Cl -

AV
">

From (2) and (6)

tOFF

For At = tON

IL)(lLOAD)IIVS-VSAT)+lvoUT
0

¢liJ

(8)

IVS - VSAT) IIVOUT - ¢11i

ICl tON ~ ILOAD

ILOAD
AVOUT= - - - tON
Cl

(3)

Since the change in the energy stored in the inductor
during tON equals the energy lost by the inductor
during tOFF,AIINDUCTOR (1) ~ AIINDUCTOR (2),

Combining (1) and (2)

FIGURE 9. Charge Circuit

Vs - VSAT
tOFF =

(4)

tON

Pulse Generator (Figures 8-10)

IVOUT -¢11
During tOFF the capacitor voltage will be restored
with an average current 1C1_
-

IC1~Cl

For the LM555
2VS
Vs
, - >VT>-

tJ.VOUT
--AtOFF

tON
tOFF

From circuit theory:

-t/T

Combining with (3)

ICl =

VT = VF + (Vi - VFle

I LOAD

~
M555

Combining with (4)
-

IC1~

(9)

ILOADI V oUT-¢ll

(5)

(VS- VSAT)

FIGURE 10. Discharge Circuit

I T
141a

Where VF = Final voltage on capacitor
Vi = I nitial voltage on capacitor
VT = Threshold voltage

r::----t-OOUTPUT
J

For charge time:
LM555

VF=VS-¢2

2VS
VT= -3Vs
Vi=T
7">

R1C2

After substitution in (9)

FIGURE 8. Pulse Generator--Astable LM555

8-10

3¢2 - Vs
tOFF (output high) = -R1C2 In - - - 3¢2 - 2VS

shown in Figure 12 eliminated the spikes on the prototype. The ferrite beads in conjunction with the ceramic
capacitor filter out the fast rising spikes. Paralleling the
2 halves of the filter capacitor has the effect of reducing
the ESR (Effective Series Resistance) of the filter
capacitor.

(10)

For discharge time:
VF = 0.04 (saturation voltage of discharge transistor)

The full load regulation can be improved by decreasing
R 1 to compensate for circuit losses.

Vs
VT=T
2VS
Vi=-3
T'"

FERRITE

BEADS
D1

R2C2

I
-

After substitution in (9)
Vs - 0.12
tON (output low) = -R2C2 In - - - - 2VS - 0.12

TO PIN 6

OF lM!i!i5
VOUT

Rearranging

FIGURE 13. Short Circuit Protection

TO PIN 6

OF LM555

:=r""'"-~

R!i

'.1V

o--.......;."",....-+-.t-<~o

VBE
RSC= - ISC

(12)

v" v"o

CERAMIC

13 shows a simple scheme for short circuit
protection and Figure 14 shows a scheme for electronic
shutdown.

VOUT )
(- - R5 = VBEQ2 + VZl
R4+ R5

2N4215

O.l.,F

Figure

Regulator Circuit (Figure 11)

:jj.

Ct/2

FIGURE 12. Filter Circuit for Removing Glitches

(11 )

'" (0.693) R2C2

rI
-

C1I2

VOUT

FIGURE 11. Regulator Circuit
FIGURE 14. Electronic Shutdown

HINTS AND KINKS

REFERENCES

The output voltage has more than the predicted amount
of ripple as well as some fast high amplitude spikes.
These anomalies are due to the reverse recovery time of
the rectifier diode and the pulse response of the filter
capacitor. The ripple can be reduced to the desired level
by increasing the size of the filter capacitor. The spikes,
however, are a bit more troublesome. The filter circuit

Mortensen, Helge H., "+5 to -15 Volts DC Converter"
LB-18, National Semiconductor Corporation.
Widlar, R.J., "Designing Switching Regulators" AN-2,
National Semiconductor Corporation.

8-11

~
CJ

...

National's Voltage
Regulator Guide

C)
Q)

a::

Q)
C)

==o

Vo. NOMINAl REGULATED OUTPUT VOLTAGE

VOLTS

Note: All devices with TO-3 package designation (K and K STEEL) are supplied in steel TO-3 packages
unless otherwise designated as IAII aluminum TO-3 package

THREE-TERMINAL VOLTAGE REGULATORS

Positive Output Voltage
Fixed
Output Voltage

Output

Current
3 Amp

1.SAmp

~'">C

Negative Output Voltage

Fixed
Output Voltage

Adjustable 2

Output Voltage

Device

LM323

LM350

LM345

Output Voltage

+5_0V

+1.2V to +33 V

-5.aV, -5.2V

Package

TO-3

Device

LM340-XX, LM78XX

Output Voltage

+5V, +6V, +8V, +10V,
+1 2V to +37V
-5 av, -5 2V, -6 av, -8 OV,
+12V, +15V, +18V, +24V Hign Voltage (HV) -9 OV, -12V, -15V, -18V,
1+1 2V to +57V I -24 V

-l.2V to -37V

Package

TO-3, TO-220

TO 3, TO 220
. LM337M

._--Device

Output Voltage

I TO-3

LM317

;ILM320 XX, LM79XX

'O',
- 'Om

,I ,~"

---~

LM341 XX, LM78MXX

LM317M

+5V, +6V, +8V, +lOV,

+1 2V to +37V

+12V, +15V, +18V, +24 V

. _ -mm
----

----

lM320M, LM79MXX
-5 av, -5 2V, -6 OV, -8 OV'I
1-9
av, -12V, -15V -18V

Package

TO-202

Device

LM342-XX

IOutput Voltage

TO~a2:. TO-39i_T~202' TO 3il 1
LM320ML

+5V, +6V, +8V, +lDV,
+12V, +15V, +18V, +24V

1-5.av, -6.0V, -80V, -10V,
-12V, -15V, -18V, -24V

~~.20~_~.

Package

TO-202

Device

LM340LA-XX, LM78L-XX

LM320L-XX, LM79L-XX

Output Voltage

+5V, +6V, +8V, +lOV,
+12V, +15V, +18V, +24V

-5V, -6V, -8V, -9V,
-12V, -15V, -18V, -24V

.---~~--

0.10 Amp

LM337
High Voltage (HV)

-1 2V to -47V

-12V'0-37V

-24V

------~-

0.25 Amp

Adjustable 2

Output Voltage

Package

---

I
i 1"0-39, TO·92

TO·92, TO-39

Note t· Some voltage OPtions are rated only 10 200 mA
Note 2: Ad!u~table voltage regulators can regulate voltages to Infinity.

8-12

TO-202, TO 39

Section 9

Microprocessor
Guide
Microprocessors, or digital computers for $4 to $200,
are more than simply the well-publicized "in" things of
today's technical press and the electroni~ industry.
These "microcomputers" have caused a major upheaval
- computers are free - or nearly free. In the past,
computers used to occupy large air conditioned rooms,
consumed large amounts of power, and were so expensive
that even small amounts of rental time kept them out
of reach of the average application. Revolutions in high·
density digital silicon MOS fabrication have created new
low·cost Ie components which allow single board
computers which can be economically applied in both
simple industrial controls and even consumer products.
National offers a full range of microprocessors and
support circuits for the full range of applications.

as·

National's
Full Spectrum
of Microprocessors

::J

Cit

National Semiconductor offers the broadest line of
microprocessors of any semiconductor manufacturer in
the world. With 4-bit, 8-bit, 16-bit and bit-slice devices,
this selection offers the designer an intelligent choice in
capabil ities, speeds and costs. Some of the benefits of
dealing with National are:

National's INS8900 Family
The 8900 is a complete, 16-bit "m inicomputer on a
chip." Its wide word length, hardware-vectored interrupt
structure, and sophisticated addressing modes make it
ideal for laboratory instrumentation, data acquisition
and process control application, where number handling
and fast response are most important.

• Cost effectiveness - because of our variety of microprocessors for a full range of applications
•

Among the outstanding features of the 8900 are its 8-bit
or 16-bit data handling, exceptional data-processing
throughput, compatibility with National's IMP-16
microprocessors, and large variety of support chips.

16-bit COMPUTATION microprocessors for precision
control functions

• 8-bit BYTE HANDLING microprocessors forterminals
4/8-bit LOW-COST CONTROL microprocessors for
industrial controllers

National's SC/MP Family

• Second sourced families
•

SC/MP is National's simple, cost-effective microprocessor.
It is the lowest-cost replacement for electrical,
mechanical and hydraulic control systems.

Ready, off·the-shelf availability

• MICRO+ - special reliability and quality program
•

The growing family of SC/MP devices includes an NMOS
CPU (lNS8060). a RAM-I/O chip with 16 I/O lines, and
a variety of bus-oriented interface and memory devices.
The SC/MP CPU itself incorporates unique multiprocessor control logic to facilitate distributed processing
systems with the lowest number of components. The
INS8060 also has a built-in Clock, Parallel and Serial
I/O; it uses low power; and it can interface to standard
memory and peripheral products_ Also available is a
BASIC-type high-level language called NIBL, which is
available in a MAXI-ROM form for fast software
development.

Full development system support - all the way from
the high-powered Universal Development System (a
disk operating system with numerous software
packages) to low-cost development systems.

National Semiconductor also offers the most extensive
line of CPU-to-peripheral support products - for digital
input/output, communications, peripheral control, and
memory. And National is constantly expanding these
support lines.
National's INS8080A Family
Positioned between the cost-effective SC/MP and the
highly versatile 8900, National's 8080A can be used in
systems which range from a few family components to
designs which utilize its full capabilities. National offers
the broadest line of peripheral circuits and memories to
complement the basic 8080A CPU. National's 8080A
features:

INS4004 is National's second source to the MCSA
family. This was the first production microprocessor
system, and it is still a popular 4-bit microprocessor
because of its simplicity and low cost. Some of National's
INS4004 features are:

•

National's INS4004 Family

Family approach to system design

• Complete CPU group

Four-bit parallel CPU

• Applicable for use in test systems, terminals, billing
machines, process control, and random logic replacement

• Programmable input/output concepts
• Multiple source availability

•

• Complete line of support components

Readily interfaces with keyboards, switches, displays,
A/D converters, and various peripheral equipment

• Ability of CPU to address 4k 8-bit instruction words,
5,120 bits of RAM, up to 16 4-bit input ports, and
16 4-bit output ports

National's INS2650 Family
The 2650 Family consists of a series of memory and
peripheral components built around the 2650A 8-bit
microprocessor. This second-sourced processor family
offers excellent byte and bit manipulation for a variety
of applications.

National's IDM2900 Family
The IDM2900 Bipolar Slice Family uses very fast,
unique, low-power SCL (Schottky/ECL) technology.
The heart of the 2900 family is the 2901A 4-Bit Slice
CPU, which has become the industry standard in slice
architecture. The IDM2900 family may be used in
sundry combinations to emulate a multitude of CPU
architectures - in contrast to fixed-instruction microprocessors. The word length of a 2900-based microprocessor may be any mUltiple of 4 bits. Each 2900
device performs a basic function, which is controlled by
an appropriate microinstruction of a microprogrammed
system.

Seventy five variable-length instructions - one, two, and
three bytes - comprise the instruction set, thus minimizing memory requirements. Some of National's
INS2650 family features are:
• Single-phase clock
• Single 5-volt power supply
• TRI-STATE data and address signals
• Single-level, address-vectoring interrupt mechanism.

9-1

"50

!...
c

3
9.

o·

a
an

en
en
o
Cil

National's Fast
IDM2900 Bit-slice
Microprocessor Family
No matter how you sl ice it, the 60 nanosecond IDM2900
bipolar microprocessor family of components from
National Semiconductor is the best bit-slice solution to
your system design problems.
Until now, computer system designers had to choose
between high speed and low power. They couldn't have
both. It was a choice between power-draining emitter
coupled logic on the one hand, and low power Schottky
designs, such as previous 2900 bit-slice architectures, on
the other.
With National's IDM2900 series, systems designers can
have both - ECl speeds and lS bipolar power consumption. We call this new technology "SCL."

IDM29750, a 256-bit field programmable read only
memory with open collector outputs, organized as
thirty two 8-bit words, with on·chip decoding and
5·bit binary addressing. It is useful for logic replace·
ment, logic extension and as an external multiplexer.

IDM29751,
IDM29750.

IDM29760/61, field programmable 1024-bit PROMs
with open collector and TR I-STATE outputs, respec·
tively. These parts are frequently used for logic
replacement, gate matrices, multiplexers and so on.

IDM29803, a branch controller with 16 separate
instructions that is capable of performing a 2-, 4-, 8-,
or 16-way branch in one microprogram execution
cycle. Useful in complex processor/controller systems
for address controller systems for address modifica·
tion and as a variable input mask for systems using
the 2909A/2911A address controllers.

IDM29811, a next state controller unit that is used
with the 2909A/2911 A for microprogram control.

IDM29902, an eight·line to three-line priority
encoder that is useful in interrupt-driven systems.

The 60 ns Slice
Centerpiece of the industry's new bipolar bit-slice standard is National's IDM2901 A, a 4-bit microprocessor
slice with an on-chip 16-word by 4-bit two-port RAM, a
high speed eight function arithmetic logic unit, as well as
the associated shifting, decoding and multiplexing
circuitry.

The IDM2901 A features a typical microcycle time of
only 60 nanoseconds, a 30 to 50 percent improvement
over lS bipolar implementations of previous generations.
But power consumption is no more than that for low
power Schottky versions - only 800 milliwatts.

I n addition, National's I DM2901 A has significantly
improved almost every timing parameter. The read·
modify·write cycle and the minimum clock period, for
example, are 43 percent less; and the maximum clock
frequency is 68 percent greater. Moreover, the IDM2901A
provides higher drive current capability, with attendant
lOS increase.

cu
Z

And also available is an even higher performance speed
selected version - the IDM2901 A·1.

J'cu!.
r:::

+=i

the

Incr eased Efficiency

IDM29901, an octal, edge-triggered flip-flop with
TRI·STATE outputs designed to drive high capaci·
tance loads or those of relatively low impedance.
This part is useful as a utility register or for temporary
data storage_

IDM29903, a 16-word by 4-bit clocked RAM
organized as an addressable "D" register file. Any
word can be asynchronously read out of or written
into on the next clock transition. The data is not
complemented; thus, this part is an ideal choice for
file extension.

IDM2902, a high speed carry lookahead generator
capable of anticipatory carry across four binary
adders or groups of adders. Th is part is frequently
used to propagate carry terms to the most significant
package when multiple 2901 A parts are required.

With National's family of standard IDM2900 components, sYstem designers can have both ECl·type
throughputs and lS bipolar power consumption and
interface capability.

IDM2909A/2911A, four-bit-wide address controllers
used to sequence through a series of microinstructions
contained in ROM or PROM. The 2911A is functionally adequate for most applications; however, the
input word cannot be masked, as can be done with
the 2909A.

Used in a typical design, system microcycle time is in
the 100 to 150 ns range, about one half to two th irds
that of previous lS bipolar parts.
Execution time for a typical operation, such as an add
and shift (multiply) is 95 ns maximum and 60 ns typical;
again, a significant gain over previous 2900 implemen-

o IDM29702, a 64-bit RAM with TRI-STATETM'
outputs, organized as sixteen 4-bit words and fully
decoded with chip enable input. This part can be used

tations.

National Semiconductor chose the 2900 four-bit bipolar
bit·slice architecture because, as the industry standard,
it is the most popular and widely understood. And,
except for speed, it has been the most versatile bit·slice
around. Now, with the IDM2900 family from National,
users get ECl high speeds, too.

as a file extension register, a memory stack or for

other similar applications.
o

To improve the efficiency and throughput of the 2900
architecture, National is also introducing new proprietary
bit-slice components that take advantage of the basic
process-related speed improvements. These include:

A Full Family

counterpart

All these parts are plug· and function·compatible with
lS bipolar components of the previous generation of
2900 parts. And both commercial and military applications can be served by National's IDM series of parts.

There's more to National's bit-slice bipolar microprocessor story. In addition to the IDM2901A, twelve of the
industry standard components in the IDM2900 family
are being introduced, most with equivalent performance
and power consumption improvements. The new SCl
bipolar parts:
o

TRI-STATE

IDM29703, a 64-bit RAM with open collector
outputs, organized as sixteen 4-bit words, and fully
decoded with chip-enable input. It is useful in systems
that use data bus lines with a defined pull-up impedance.

*A trademark of National Semiconductor Corporation.

9-2

MID RANGE

Future Lower Cost, Higher Integration

Future High Performance

Single Chip CPU

8·Bil CPU

16·Bil CPU

SC/MP MICROPROCESSOR FAMILY (8060)
PART

PART

NUMBER

DESCRIPTION

NUMBER

DESCRIPTION

INS8060
INS6060NI

Single Chip a·Bit CPU
Single Chip a·Bit CPU
- 40°C to + 85 Q C
Single Chip 6·Bit CPU
- 40°C to + 85°C

INS2650
INS2650A

a·BiI N·Channel

INS806001

INS2650A·1
INS265!

PART
NUMBER

INS2656

DESCRIPTION
8-Bit
8·8il
a·BlI
8·Bil
B·Bi!

INS8060AD
INS8080AN
INsaoaOAD·1
INsa080AD·2
INSB080AN·2
tNS8080AOt

a·Bit N·Channet (Improved
Device Operating Margins)
8·Bil N·Channel (1.5 ).lsi
Progrllmm8ble

Communications Interlace
INS2652

Multi·Protocol
Communications Coni roller
System Memory Inlerlace

INS80aOAOIIB83
INS8224
INSS22S
INS8238

PART
NUMBER

INS8208
INS8213
INS8216
INS8226
INS8255
INS8253
tNS8257
INS82S9

INS82C06
INS8212
INS82LS05

CPU (2 fls)
CPU (2 us)
CPU (1.3 ~s)
CPU (1 5 us)
CPU (1.5 us)
8·6i~ CPU (2 us)
- 40QC to + 85 Q C
8·Bit CPU (2 us)
- 40 Q C to + 85 Q CI863B
Clock Generator & Driver
System Conlroller & Bu!'>
Driver
Sys~em Controller & Bus
Driver (Advanced Timing)

[)

PART
NUMBER

DESCRIPTION

INSB900
INSB20B
MM74C04

16·Bit CPU
Bi·Dlrectional Bus Driver
Inverler-Clock

J
DESCRIPTION
Tri·Slate a·BiI BU$ Driver
Tri·State 8·8it Bus Driver
(Imoer1ingl
8·Bit BI·Directional Bus
Driver
!!·BIt Bi·Direction~1 110 Port
4·Blt Bi·Oirectional Bus
Driver
4·Bit Bi·Directional Bus
Driver (inverting)
Programmable Peripheral
Interlace
Programmable Timer
Programmable DiMA
Controller
Programmable Interrupt
Conlroller
8·811 110 Lalch
8·Bil 110 Port
"01·8 Binary Decoder

COMMUNICATIONS
PART
NUMBER
INSB250

DESCRIPTION
Asynchronous
Communications Element
(ACE)
Programm~ble

INS8251
INSB252'"
INS8261
INS8274
INS8283*
INS1671

Communications Interlace
Advance~ P'?grammable
CommunlclII.ons Interlace
Programmable
Communicalions Inlarlace
Multi·Protocol
Comm~lfliciltions Controller
Advanced SOLC. AOCCP
Protocol Controller
ASTRQ Communicalions
Interlace

I
PART
NUMBER

INS6272i<
INS8276
tNS8285
INS6292
INS8294
INSB295
INS8298
INS1711.1

DESCRIPTION

0) CD CD
-0(,)

MEMORY

PART
NUMBER

DESCRIPTION

IN56154

128" 8 Stalic RAM wilh
Common 110
8192" 6 MOS Mask ROM
(E has 2708 Compal!bilil~1
INS8101A·4
256,. 4 Static RAM with
Separate 110
lNS8102A
1024" 1 Static RAM
INS81t1A·4
256,. 4 Static RAM with
Common HD
INSB316A!E
2048" 8 MOS Mask ROM
(270B Compatible)
4096" 8 MOS ROM
INSB332E
(2706 Compatible)
INS6104
512,. S EPROM
256" 8 EPROM
MM1702A
MM21 XX
256" 4 Slatic RAM
MM2114*
1024,,4StalicRAM
MM2316AIE
2K ,. 8 ROM
MM270801870eO lK x 6 EPROM
512" 8 EPROM
MMS204
4K ~ 1 Sialic RAM
MM5257
MM5290*
16K Dynamic RAM

INS8364!8364E

256

MM74C921
MM74C929
DM74S472
DM87S29S

:rOcn
~(')'C

MM74C920

*Available very soon. Call your National Representative.

::lIO _
'C 'C

-.c

90·Key Keyboard Encoder
16·Key Keyboard Encoder
20·Key Keyboard Encoder
4·Digit Display Controller
6·Digil Display Con!roller
Programmable 16·Bil.
Addressable Peripheral
Interface
Floppy Disk Formalhlf!
Controller
Programmabte CRT Controller
Character Generator
8-Bit AID Converter with
16·Channel Analog MUX
3 l~-.oigil DVM With
Multiplexed BCD Oulput
NI6L "BASIC" Interpreter WIth
SC/MP-Resident Assembler
lLL 8080A "BASIC"
Interpreter Plus HEX
Debugger
Floppy Disc Controller

(')::::J
CD -'0)

PERIPHERAL CONTROL

INS8244
INS8245
INS8246
INS82l17
INS8246
INS8254

Q.3:cr.
."
_. 0

00~
0-.

MICROBUST.

DIGITAL VO

IN5a202
INS8203

8900 MICROPROCESSOR FAMILY

8080A MICROPROCESSOR FAMILY

2650 MICROPROCESSOR FAMILY

O)az
::::J
0)

HIGH END

LOW END

4 CMOS Sialic RAM

with Separate 110
256" 4 CMOS Slatic RAM
with Common 110
1024,. 1 CMOS Static RAM
512" 8 Bipolar PROM
512 ~ 8 Bipolar PROM

SleJalld!Jad pue SJOssa:xudoJ:>!W

,0 WnJl:>ads SJeUO!leN

Section 10

•

Systems
Applications
Memory system applications range from a chip used in a
microprocessor system to an add-on memory for a large
mainframe computer. Today's memory components
allow the memory for many systems to be implemented
on a single card (or multiples of a single card). Examples
of this type of system are presented here_

Systems Application of
MM5270 4k Dynamic RAM

DESCRIPTION - STORAGE BOARD
This document describes the general features of the
1617 Storage Card. It includes a description of the
functional capabilities and the physical and electrical
specifications.

Read/Write
'"

c::i!:!-

,..

"
~

'"
~

Figure 4. 4k RAM Array

10-4

~
_~

OSli1l
A12 _ _ _ _ _ _ _.!.IJ~I-'-'

- - - - - - _ "2V(VOOI

AU _ _ _ _ _ _ _!..j4 A2
Vr;CJ,~I'--"22"'~!""""""'''''''LC:;:''-4:!.!16
~ m
OUT4rU_ _~M--- CE ROW3
Of _ _.!:":f).o!'U'r-:::-~':!..j0 UP 09 OUT] 9
CE ROW 2
EFH
.....AB
11 REF
OUT2~''-_ _'''''''''''_ _ _ CEROWI
CE

--t:;E>lo-,+---1l'

ounf.!...'- - - - ' l M - - -

4ClK

~74DII

~
..g.B4

OA------,

"f-

Y3r!--

-t

~A4
~B3

CE ROW

::r':"'--Jt------

- i ::

DO 16

10';:0096 9

~")""i.-_l.....~

'>---;:===2=:":"~'H'....-="--"

1/015 ....

I. A4

4....

lIn

3....

~::

OMl213

Y4i-!!.12l-l---""""1~-

AI4 Yl~'4--+--~+--

7~ j

---'"+-O-+-'-+-- 11011

l'011>------......"H~
~----+~--_2!:~~

Y4~'~2r_+_--""""1---

'~">_---+~...-----J!.I_-4_I'&:: All Y3r'4--+--..,-+--

'~:",);'-----1~...j.;::.....I-r-+:~

,:;:====~==~'~3~
~:~

V4~'~'r_+_---1__- ' 0 1
Y1r't--t---1H--

14 A4

./06

'~;,----++---l'4B2

~ I

·>-----+-1f-+-+1

$PAAEGATES

8096

II03;::::===i:==~"~~
14 A4

Y4~,,,-2r_+_---1---'C1

IIOZ",.
r----Z:~
Yl'f"+-+--~+--.C2
,'">----+-+--'!-< 82 Al ,I-'-'+_+--o-HI_-

~[~ E :: .

1/00

~
~

_____________
_______________ W

r--Efi •

~
~

Figure 5. Interface Circuitry

10-5

Systems Application of
MM5290 16K Dynamic RAM

SYSTEM DESCRIPTION
This section defines the functional capabilities of the
NS340 Storage Card. The NS340 Storage Card contains
a random-access semiconductor memory array utilizing
the MM5290 16k dynamic RAM and appropriate·drivers
and receivers to permit data storage and retrieval. Proper
DC power and I/O connections are required to operate
the card.
Memory Configurations
The NS340 Storage Card has a maximum storage capacity
of 131,072 (128k) words, each 22 bits long. Other
permissible memory configurations are shown in table 1.

'READ/DELAYED WRITE tlmong includes processor
modification if the READ/DELAYED WRITE is actually
a READ/MODIFY/WRITE. A maximum modification
time of 2.8 microseconds is allowed.

NOTE
Prior to performing any valid memory operations,
the card must be initialized by executing aRE·
FRESH cycle at each val id REF RESH address
( 128 cycles).

INTERFACE DESCRIPTION
Measurements

Table 1. Memory Configurations

Single Byte
256k x 8
256k x 9
256k x 10
256k x 11

All timing measurements given above and in figures 1
through 4 are taken at the edge connectors of the NS340
Storage Card. Proper line termination, on both input and
output lines, is assumed and signal timing measurements
are referenced to the +l.5V level of the signal transition.

Double Byte
128k x 16
128k x 18
128k x 20

Input Definitions

128k x 22

Logic levels are defined as follows:
Logic HIGH +2.5V to +5V
OV to +0.5V
Logic LOW

Modes of Operation
The NS340 Storage Card has four basic modes of
operation:
READ
WRITE
READ/DELAYED WRITE
REFRESH

SELECT (-SELECTO, 1): The -SELECTO and -SELECT
1 signals enable the current memory operation to be
performed on either or both of bytes 0 and 1. The
-SE LECT signals must be true 20 ns before to' and must
remain true a minimum of 275ns and a maximum of
lOps after to for a READ or WRITE cycle, and a
minimum of 300ns and a maximum of lOps after to
for a READ/DELAYED WRITE cycle.

The first three modes are concerned with data storage
and retrieval. The last mode, REFRESH, is necessary to
prevent loss of the data stored in the NMOS storage
chips. NMOS Random Access Memory (RAM) devices
store data as an electrical charge on the gate capacitance
of a field-effect transistor. The stored charge tends to
deteriorate and must be renewed at least every two
milliseconds. Therefore, 1/128 of the memory (1/128
of each memory chip) is recharged (refreshed) every
15 microseconds. The seven low·order address bits
determine the portion of memory to be refreshed.

*to is defined as the starting time of the memory or
REFRESH cycle at the NS340 Storage Card itself (i.e.,
the leading edge of -ADSTB).

ADDRESS (-ADD 00-16): All seventeen ADD lines are
used to select the desired memory word during READ,
WRITE, and READ/DELAYED WRITE cycles. The
-ADD 00-06 lines select 1/128 of the memory during
REFRESH cycles (see Refresh Control). The ADD lines
must be stable a minimum of 20 ns before the leading
edge of -ADSTB and must remain stable a minimum of
o ns after the trailing edge of -ADSTB. However, it is
desirable to keep the ADD lines stable until the trailing
edge of -SE LECT, as this helps reduce card noise to a
minimum.

Access and Cycle Times
The access and cycle times are listed below.
READ, WRITE, REFRESH cycles:
Access Time 250 ns max
Cycle Time 450 ns min

ADDRESS STROBE (-ADSTB): The ADDRESS
STROBE signal is used to generate the internal row·
address and column-address strobes for the 16k storage
chips. The signal must be true at the start of the cycle
(time to) and must remain true a minimum of 275 ns

READ/DELAYED WRITE cycle:
Access Time 250 ns max
Cycle Time 500 ns min
3450nsmax'
10-6

teI-CYCLE,.+,

to-CYCLEN

ADDR

m:m

smCt

AI!m

Aiiffi

WRTST

ii'li'lii

WRTBD,Bl

DATAIN

DATA
OUT

LCHDI

Figure 1. READ Cycle Timing

Figure 2. WRITE Cycle Timing

(times given in nanoseconds)

to - CYCLE N
REF
ADOR

ADD"

10-61

WRTST

Figure 4. REFRESH Cycle Timing
(times given in nanoseconds)
DATA OUT

DATAIN

-1r::==-;;;;;;==1:~+~1!l

-1r------~t~~jb~----+-

WRT.IO,BI

Figure 3. READ/DELAYED WRITE Cycle Timing
(times given in nanoseconds)

10-7

to - CYCLE N+1

and a maximum of lOllS for a READ or WRITE cycle,
and a minimum of 300ns and a maximum of lOllS for
a READ/DELAYED WRITE cycle.

up to -5.2 mA in the high level and 100 mA in the low
level. Data will be output from the -DOBYO (byte 0)
lines if -SELECT 0 and -DOENB are both true, and
from the -DOBYl (byte 1) lines if -SELECT 1 and
-DOEN B are both true_

DATA OUTPUT ENABLE (-DOENB): The 3647 TRISTATE@ 1/0 register chips receive data that is read from
the memory chips, latch it, and send it to the host
system. Since these chips may provide either a unidirectional or a bidirectional data interface, the -DOENB
signal enables the chips to function in the proper direction (A-to-B) for output of data. -DOENB must go true
50 ns minimum before data out is to be valid.

OPTIONS
The NS340 Storage Card contains oPtional features that
may be implemented by proper I/O connector wiring_
The options are listed below.
External Column Address Strobe
Refresh Control:
Burst Mode
Distributed

LATCH DATA OUT (-LCHDO): Data read from the
memory chips is latched into the 3647 output data
register chips by -LCHDO. -LCHDO must be high for a
minimum of lOOns before its leading edge. The leading
edge of -LCHDO occurs a minimum of 10 ns before the
trailing edge of -ADSTB, and a minimum of 250 ns after
to·

These options are discussed in the following paragraphs.
External Column Address Strobe

WRITE BYTE 0,1 (+WRTBO,l): The +WRTBO and
+WRTB 1 signals control whether data is written into the
byte a and/or byte 1 memory chips. Both of these
signals are gated by +WRTST. Data is written into byte a
(1) only if +WRTBO (1) and -SELECT a (1) are both
true_

A jumper option is provided on the card that allows the
storage chips to use either the internal column address
strobe signal generated from the -ADSTB signal (from
the host system), or an external column address strobe
supplied from the host system. If the external strobe
(-CASTB) is used, it must go true a minimum of 75 ns
after -ADSTB. -CASTB must be true for 180 ns minimum and 270 ns maximum.

WRITE STROBE (+WRTST): The +WRTST signal gates
the +WRTBO and +WRTBl signals to the WRT inputs of
all 16k memory chips_ During a WRITE cycle +WRTST
goes true a maximum of 25 ns after to and remains true
until a minimum of 20 ns after the trailing edge of
-ADSTB. During a READIDELAYED WRITE cycle,
this signal must go Iowa maximum of 25 ns after to
and remain Iowa minimum of 200 ns after to. After this,
the signal is allowed to go high for lOOns minimum to
gate the +WRT BO, Bl signals to the chips to perform
the WR ITE portion of the cycle.

The -CASTB signal must be used if it is desired to perform page-mode memory operations. A memory "page"
consists of 1/128 of the memory as addressed by one
row address (-ADD 00-06). If -ADD 00-06 are held
constant, -ADD 07 -13 may be cycled to perform the
same type of memory operation at any or all locations
of the memory "page." After the initial memory operation is performed, -CASTB goes high at 220 ns after
the leading edge of -ADSTB. -CASTB then remains
high for 60 ns, after which -CASTB again goes low for
the next cycle. 20 ns before -CASTB goes low, the next
column address must be stable on the -ADD 07-13
lines. This procedure may be repeated to cycle aft
address locations in the same memory "page."

DATA IN (-DIBYOOO-10, -DIBY100-10): Data to be
stored into the memory is input via the DATA IN lines_
During a WRITE cycle, input data must be valid no more
than 50ns after to and remain valid at least until 150ns
after to. During a READ/DELAYED WRITE cycle,
input data must be valid at least 20 ns before the positivegoing edge of WRTST and remain valid at least until
20 ns after the trailing edge of -ADSTB.

Refresh Control
REFRESH cycles may be performed in either of two
modes as described in the following paragraphs.

LATCH DATA IN (-LCHDIl: Data to be stored into the
memory chips is latched into the input data register
(3675 chips) by the -LCHDI signal. -LCHDI must be
high for a minimum of 50 ns before its leading edge.
The -LCHDI signal occurs a minimum of 75 ns after the
leading edge of -ADSTB_ -LCHDI cannot occur later
than 20 ns before the input data is to be off of the bus.

Burst Mode: Burst mode is intended for use in battery
backup mode, but may also be implemented in normal
mode. When this option is used, an external oscillator
with a period of 2 ms must be used. At the start of every
2 ms period, a seven-bit REFRESH counter is initialized
to zero. These 7 bits are used as address bits 0-6 to
address 1/128 of the memory for refreshing_ At the
conclusion of each REFRESH cycle (450ns), this
counter is incremented and another REFRESH is
immediately performed. This continues until 128
REFRESH cycles hav~ been performed, and all of the
memory is thus refreshed with a burst of 128 REFRESH
cycles. Total time to refresh the entire memory is
approximately 60 microseconds.

REFRESH (-RFSH): The -RFSH signal performs the
function of both -SELECT signals during a REFRESH
cycle. -RFSH gates -ADD 00-06 to the memory chips,
disables the column-address strobe, and provides a rowaddress strobe to each chip so that -ADD 00-06 may be
latched into each chip's address register. -RFSH goes
true a minimum of 10 ns before to and must remain true
a minimum of 275 ns and a maximum of lOllS after to.

Distributed: This option is similar to burst mode, except
that one REF R ESH cycle is performed every 15 m icroseconds instead of 128 REFRESH cycles being performed consecutively at the start of a 2 ms period_ This
option requires an external oscillator with a period of
15 microseconds, and utilizes a seven-bit REFRESH

Output Definitions
The only output from the NS340 Storage Card is via the
-DOBYO and -DOBYl (DATA OUT) lines. These lines
are driven by 3647 TRI-STATE drivers, which can drive
10-8

MECHANICAL DESCRIPTION

address counter as does burst mode. Now however, the
REFRESH address counter is incremented at the end of
each 15 microsecond oscillator period instead of at the
end of each 450 ns REFRESH cycle.

The physical and mechanical details of the NS340 are
described in this section.

POWER REQUIREMENTS
Parameters and Conditions

General

Three DC voltages are required to operate the NS340
Storage Card. These voltages and the current requirements are listed in this section.

The NS340 Storage Card is completely contained on
one multilayer printed circuit board (internal voltage
and ground planes are used). which requires only the
application of DC power to become functional.

Table 5 identifies the worst case power requirements
of the NS340 Storage Card. The conditions and parameters used are defined as follows:
Standby

Quiescent mode with one REFRESH
cycle every 15115.

Dimensions
Thickness
Height
Length

Operating 450ns cycle - continuous READ/
WRITE memory operation, including
REFRESH.
Typical

The NS340 Storage Card is designed to mount on a
minimum center·to-center board spacing of 0.625".
Two card ejectors (BIRTCHER 83-1·2 or equivalent)
permit easy removal of the card.

Nominal supply voltages.

Maximum Worst case supply voltages.
Power Consumption
Table 5. Standard Power Consumption

Operating
Voltage
+12V
+5V
-5V

Typ

Max

0.65A
1.53 A

0.92A
2.52A
0.02 A

0.01 A

Standby
(REFRESH only)
Typ
Max
0.26A
1.4 A
0.01 A

0.0625 inches
11.75 inches
15.40 inches

0.39A
2.3 A
0.02A

10-9

Systems Application
of MM74C929 CMOS RAM

SYSTEM DESCRIPTION

INTERFACE DESCRIPTION

This section defines the functional capabilities of the
NS400-CL and NS400-CC Storage Cards. The NS400-CL
and NS400-CC Storage Cards each contain' a static
random-access semiconductor memory array and appropriate drivers and receivers to permit data storage and
retrieval. Proper DC power and I/O connections are
required to operate the cards.

The following paragraphs describe the interface to the
NS400-C Storage Cards.

The NS400-CL and NS400-CC Storage Cards both
utilize the MM74CS2S CMOS storage device to form
4kx8, 4kxS, or 4kx 10 memory arrays. However, the
NS400-CL Storage Card uses CMOS logic for its array
and TTL for its I/O interface, whereas the NS400-CC
Storage Card uses CMOS logic for its array and I/O interface. The NS400-CL Storage Card requires a supply
voltage of +5.0V ± 5%. The NS400-CC, however, can
operate with any VCC voltage within the range of 3.5 V
through 5.5 V. An increase in VCC will result in a
decrease in access time. Figure 2 shows a graph of access
time versus VCC voltage for the NS400-CC Storage Card.

MEASUREMENTS
All timing measurements are taken at the edge connectors
of the Storage Card. Proper line termination, on both
input and output lines, is assumed. Signal timing measurements for the TTL 10Sic are referenced to the +1.5V
level of the signal transition.
INPUT DEFINITIONS
Logic Levels are defined as follows:

NS400·CL

Logic 0; LOW

Because the NS400-CC can operate at a lower VCC
voltage, the card is more suitable in applications where
VCC is supplied from a battery. This is discussed later.
MODES OF OPERATION

Component

OV to +0.5V

Logic 0

NS400-CC
Logic 1

Logic 0

O.OOS"A

0.005 "A

40"A

1.6mA

74 L542174C42

20"A

0.4mA

l"A

74L86/74C86

20"A

0.36 rnA

O.OOS"A

0.005 "A

74 L20/74C20

20"A

0.36mA

O.OOS"A

0.005 "A

Table 2_ Input Loading by Signal Name

Signal

Read or Write
Cycle Time

NS400-CL
400ns max
(VCC = +5.0V ± 5%)

500ns

NS-410-CC
575ns max
(VCC = +5.0V ± 5%) (25 pF data bus)
700ns max
(150pF data bus)

700ns

500 ns - SOO ns*
(25 pF data bus)
600ns-1100ns*
(150pFdatabus)

+3.0V to +3.5V

OV to+1.5V

80S7/80C97

The access and cycle times are as follows:

NS400-CC
(VCC = +3.5V +5.5V)

+3.5V to +5.0V

NS400-CL
Logic 1

ACCESS AND CYCLE TIMES

Read
Access Time

OV to +0.5V

Tabl. I. Input Loading by Component Type

The NS400-C Storage Cards have two basic modes of
operation: READ and WRITE. These two modes of
operation permit data storage into and data retrieval
from the memory array. Although the Storage Cards are
not designed to perform a dedicated READ/MODIFY/
WR ITE cycle, such a cycle may be performed under
user control as a separate READ cycle and WRITE
cycle, with time allowed between the two cycles to
allow data modification.

Storage Card Type

NS400-CC (+5VI NS400-CC (3.5VI

Logic 1 = HIGH +2.5V to +5.0V

1100ns

*For access time for any given supply voltage on the NS400-CC
Storage Card, consult figure 2.

10-10

NS400-CL
Logic 1

AO-AS

40"A

Logic 0

NS400-CC
logic 1

Logic 0

1,6 rnA

O.OOS"A

O.OOS"A
0.005"A

010-019

40"A

1.6mA

O.OOS"A

Al0,All

20"A

0.4 rnA

l"A

MEM EN

20 "A

0.36 rnA

O.OOS"A

A12, A13, A14

20"A

0.36 rnA

O.OOS"A

512,513,514

20 "A

0.36 rnA

O.OOS"A

R/W

20"A

0.36mA

O.OOS"A

NS·400 ACCESS TIME

1000

9DD

800

CYCLEN+l

, " "',

JDD

"
25pF DATA BUS

SOD

ADDRESS

lsDpF DATA BUS

.. J

600

400

CYCLEN

vs. VOLTAGE
1100

....r--

- '-

I
4.0

3.5

(AD-AS)

4.5

lL2~~~wr'----------+...J

MEMORY

ENABLE

(MEMEN)

-SE!~i~

-+----,

5.5

5.0

VDLTAGE
DATA IN
1010-019)

Figure 1. NS400 Access Time vs Voltage
TO

I:VCLEN

C.VClEN+l

'JiEAIj/wRT

Figure 3. Write Cycle Timing

MEMORY
ENABLE
IMEMEN}

~SE1"l~~

Table for Figure 3

Card Types

-+----'"
NS400-CL

NS400-CC
Fixed

Ons max

70ns max

Ons min

lOOns min

250ns min

350ns min

500ns min

60ns min

130 ns min

130ns min

75ns max

100 ns max

lOOns min

350ns min

600ns min

Time
READ/WRT

-OATA~~r.
STB~
DATA

(OOO.~~:'

-+-------*''-___1-./

NS400-CC
Variable

Ons max

100 ns max

lOOns max

500ns max

700ns max

1100ns max

250ns min

350 ns min

600ns min

Figure 2. Read Cycle Timing
Table for Figure 2
Card Types

Time

MEMORY ENABLE (MEM EN)

Ons max

70 ns max

ons min

Onsmin

100nsmin

250 ns min

350 ns min

500 ns min

62ns min

130nsmin

lOOns min

350 ns min

600 ns min

MEMORY ENABLE, in conjunction with ADDRESS IN
lines A12-A14 and SELECT ADDRESS IN lines
S12-S14, enables selection of the memory devices on
the Storage Card. When the card is selected, - SELECT
ACKN is driven active. MEMORY ENABLE must be
activated at to and remain active for a minimum of
250 ns for the NS400·CL version, 350 ns for the fixed
VCC NS400-CC version, and 600 ns for the variable
VCC NS400-CC version.

400ns max

575ns max
(25pF)
700ns max
(150pF)

consult
figure 2

ADDRESS IN (AO-A14)

NS400-CL

NS400-CC
Fixed

NS400-CC
Variable

The fifteen ADDRESS IN lines are used as follows
during both READ and WRITE memory cycles:

25ns min

50 ns min

lOOns min

50ns max

2Jls max

500ns max

700ns max

1100 ns max

200ns min

300ns min

400ns min

250 ns min

350ns min

600ns min

A 12-A 14 select 1 of up to 8 Storage Cards.

10·11

A 10, A 11

select one of the four 1k columns of
memory devices on the Storage Card.

AO-A9

select one of the 8·, 9·, or 10·bit words in
the selected memory device column of
the selected Storage Card.

Table 4. Output Drive by Signal Name

On the NS4o'o'-CL Storage Card, the ADDRESS IN lines
must be stable no later than to' and remain stable for the
duration of MEM EN (memory enable). On the NS4o'o'-CC
Storage Card, the ADDRESS IN lines must be stable not
later than 10'0' ns after to'. The ADDRESS lines must
remain stable for the duration of MEM EN for fixed
VCC operation, or for a minimum of lo'o'ns after the
trailing edge of MEM EN for variable VCC operation.

Signal

NS400-CL

NS400-CC

Logic 1

Logic 0

Logic 1

Logic 0

000-009

S.2mA

32mA

4.3SmA

SELECTACKN

200l'A

3.6mA

1.7SmA

ACKNOWLEDGE (- SELECT ACKN)
SELECT ADDRESS IN (S12-S14)
The selected Storage Card generates - SELECT ACKN
in response to the correct ADDRESS IN (A12-A14) and
MEM EN. On the NS4o'o'-CL card, - SELECT ACKN
goes active a minimum of 60' ns after to' and remains
active until 60' ns after the trailing edge of both the
ADDRESS IN lines and MEM EN. On the NS4o'o'-CC
card, the minimum time is 130' ns in both cases instead
of 60' ns. - SE LECT ACKN may be jumpered to - DATA
STB to provide an instantaneous data strobe. Loading
and capacitance should be kept to a minimum on the
- SELECT ACKN line.

The three SELECT ADDRESS IN lines assign the
Storage Card to one of eight address ranges (one of
0'0'0'2-1112). If ADDRESS IN lines A12-A14 respectively mismatch the SELECT ADDRESS IN lines, the
Storage Card is selected if MEM EN is active. The
address range assignment and card selection are explained
in detail later.
DATA IN (Dlo'-Dl9)
Data to be stored into the memory array enters via the
010-019 lines, and must be stable not later than 75 ns
after to' for the NS4o'o'-CL card or 10'0' ns after to' for
the NS4o'o'-CC card. For the NS4o'o'-CL card, data must
be stable for at least 10'0' ns after the trailing edge of
MEM EN. For the NS4o'o'-CC card, data must be stable
for at least 350' ns after the trailing edge of MEM EN for
fixed VCC (+5.o'V) operation, or for at least 60'0' ns after
the trailing edge of MEM EN for variable VCC (+3.5V+5.5V) operation.

DATA OUT (DOO-D09)
Data read from the memory array during a READ cycle
i's placed on the DO lines when - DATA STB is active.
Data is valid on the DO lines a maximum of 40'0' ns after
to' (NS4o'o'-CL) or 575 ns to 70'0' ns after to' (NS4o'o'-CC
card with fixed VCC operation). The time when data is
valid for an NS-4o'o'-CC card with variable VCC operation
may be determined by consulting figure 1.

READIWRITE (R/W)

INTERFACE SIGNAL LIST

The RIW signal controls the type of cycle to be performed. RIW must be LOW for a READ cycle and HIGH
for a WR ITE cycle. RIW must be stable at to' for the
NS4o'o'-CL card and be stable at a maximum of 10'0' ns
after to' for the NS4o'o'-CC card.

Table 5 lists the I/O connector signal pin assignments.
The table lists by pin number, signal function (including
options available). and a mnemonic of each signal.

The RIW signal must remain stable until after the trailing
edge of MEM EN: 10'0' ns minimum after the trailing
edge of MEM EN for the NS4o'o'-CL card, 350' ns
minimum after MEM EN for the NS4o'o'-CC card with
fixed VCC operation, and 60'0' ns minimum after M EM EN
for the NS4o'o'-CC card with variable VCC operation.

The NS4o'o'-CL and NS4o'o'-CC Storage Cards contain
optional features that enable the cards to be used in a
variety of applications. The options are listed below:
TTL or CMOS interface
Variable Access - NS4o'o'-CC Storage Card
Delayed Data Strobe
Address Range Assignment
Storage Card Depopulation

OPTIONS

DATA STROBE (- DATA STB)
The DATA STROBE signal gates data read from the
memory array onto the DO (data out) lines. It must be
activated a minimum of lo'o'ns before it is desired for
data to be valid on the DO lines.

These options are discussed in the following paragraphs.
TTL OR CMOS INTERFACE
As mentioned throughout this specification, there are
two types of NS40o'-C Storage Cards: the NS4o'o'-CL
and the NS4o'o'-CC. Each card utilizes the MM74C929
storage device for its memory array. However, the
NS4o'o'-CL card uses TTL drivers and receivers and a
TTL card-selection logic network, while the NS4o'o'-CC
card uses CMOS drivers and receivers and a CMOS cardselection logic network. The NS4o'o'-CL card, although
low power, requires a fixed VCC of +5.o'V. The
NS4o'o'-CC card can operate with any VCC from +3.5V
to +5.5V. This is useful in applications where VCC must
be obtained from a low voltage battery, or when
operating the card in certain heavy industrial areas where
brown-outs are quite common and a +5.o'V supply
operating from the AC line may put out a substantially
lower voltage than +5.o'V due to the reduced AC input
voltage.

OUTPUT DEFINITIONS
The NS4o'o'-CL and NS4o'o'-CC Storage Cards output
- SELECT ACKN during a WRITE cycle and Data Out
during a READ cycle. The output lines are defined in
the following paragraphs, and output drive is shown in
tables 3 and 4.

Table 3. Output Drive by Component Type
Component

NS400-CL

NS400-CC

Logic 1

Logic 0

Logic 1

Logic 0

8097/80C97

5.2mA

32mA

4.35mA

74 L20/74C20

200l'A

3.6mA

1.7SmA

10'-12

VARIABLE ACCESS - NS400-CC CARD

STORAGE CARD DEPOPULATION

The NS400-CC Storage Card, as discussed previously,
operates with any VCC from +3.5V to +5.5V. Figure 1
shows VCC voltage versus access time. Note that a higher
VCC results in a shorter access time and hence a shorter
cycle time, whereas a lower VCC results in a longer
access time and hence a longer cycle time. Varying VCC
from 3.5V to 5.5V changes the access time from a low
of 500 ns to a high of 900 ns with a 25 pF data bus, or
from a low of 600ns to a high of 1100ns with a 150pF
data bus.

The NS400-C Storage Cards may each provide 4kx8,
4kx9, or 4kx 10 storage. The card must be fully populated to provide 4kxl0 storage. To provide 4kxS or
4kx 9 storage, chips need not be present in rows K and
L, or row L, respectively.

POWER REQUIREMENTS
Proper VCC voltage levels and current requirements for
the NS400-C Storage Cards are listed in tables 7 and 8,
which identify the worst case power requirements of
each Storage Card. The conditions and parameters are
defined as follows:
Quiescent mode - memory enable low
Standby
I/O. Pins 14, 17,22, and 27 HIGH.
Operating Continuous READ and WRITE cycle
memory operation.
Typical
Nominal supply voltages.
Max
Worst case supply voltages.

DELAYED DATA STROBE
Both Storage Cards allow instantaneous or delayed
strobing out of data read from the memory array. In
many applications, - SELES:;T ACKN is jumpered to
- DATA STB. As soon as the card is selected, - SE LECT
ACKN becomes active, and in turn activates - DATA
STB to permit instantaneous strobing of data to the
interface.
Data strobe can, however, be controlled externally after
the receipt of an acknowledge or the strobe can be tied
LOW for a constant enable.

POWER REQUIREMENTS FOR NS400-CL
One +5V supply is required to operate the NS400-CL
Storage Card. Table 7 identifies the worst case power
requirements of this card.

ADDRESS RANGE ASSIGNMENT
Several Storage Cards may be used to form a memory
system. Cards may be connected in series to increase
word length and/or cards may be connected in parallel
to increase storage capacity.
When connecting cards in parallel, only one card must
output a particular 10·bit word, while all other cards
remain disabled. For this reason the card provides three
normally HIGH address·bit·select lines, called S12, S13,
and S14. S12, S13, and S14 can specify anyone of eight
binary numbers.

Table 7. NS400-CL Power Consumption

A card is assigned a binary number by jumpering the
correct ones of S12, S13, and S14 to ground. When an
address enters the card, S12, S13, and S14 are compared
on a respective one·to·one basis with address input bits
A 12, A 13, and A 14. If all corresponding bits of both
sets of address bits mismatch, the card will be selected
if MEM EN is active.

Voltage/Mode

Typical

Maximum

+4.75V Standby/
Operating

250mA
3l0mA

300mA
370mA

+5.25 V Standby /
Operating

280mA
350mA

345mA
420mA

POWER REQUIREMENTS FOR NS400-CC
The NS400-CC Storage Card may be operated with any
VCC voltage from 3.5V to 5.5V, including a low voltage
battery. Table 8 identifies the worst case power requirements of this card.

Table 6 shows the jumpering required for S12, S13, and
S14 to assign a card to one of the eight address ranges:
Table 8.

2Sk-32k
24k-2Sk
20k-24k
16k-20k
12k-16k
Sk-12k
4k-Sk
0-4k

Typical

Maximum

3.5V Standby
1100 ns Operating

23JlA
34mA

28JlA
41 mA

4.75V Standby
1100 ns Operati ng
700 ns Operating

30JlA
54mA
72mA

36JlA
65mA
87mA

5.25V Standby
1100 ns Operating
700 ns Operating

55JlA
62mA
S4mA

66JlA
74mA
101 mA

5.5V Standby
1100 ns Operating

200JlA
67mA

240JlA
80mA

S14

S13

S12

X
X
X
X

X
X

Power Consumption

VCC Voltage/Mode
Table 6. Address Range Assignment

Address
Range
Assignment

NS400~CC

X
POWER-UP CONSIDERATIONS
Memory enable (MEM EN) must be held LOW during
power-up to prevent memory device latch-up.

Note: X indicates a jumper to ground.

10-13

MECHANICAL DESCRIPTION

Cooling

Both NS400-C Storage Cards are fabricated with twosided printed circuit boards and require only the application of DC power to become functional.

Suggested minimum air flow for the NS400-CL and
NS400-CC Storage Cards is 15 cfm and 10 cfm respectively_

DIMENSIONS

SHIPPING AND STORAGE CONDITIONS

Thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.062"
Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.93"
Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3"

Non-operational environmental limits are detailed as
follows:

The cards are designed to mount on a minimum centerto-center board spacing of 0.0625". No ejectors are
present on the card.

Temperature
The NS400-C Storage Cards can withstand a temperature
range of _40°C to +85°C during shipment or storage.

I/O CONNECTORS

Thermal Shock

One 60-pin edge-type I/O connector provides an interface to the NS400-CL or NS400-CC Storage Card. The
spacing of these connector fingers is 0.125", center-tocenter. The material is gold over copper. The recommended mating connector is an ELCO 00-6307-060-309001 or equivalent.

A thermal rate of change as high as 10°C per minute can
be tolerated.
Altitude
The maximum shipping altitude is 40,000 feet.
Mechanical Shock

ENVIRONMENTAL DESCRIPTION

The Storage Cards, each housed in its shipping container,
can tolerate mechanical shock resulting from drop tests
performed in accordance with MIL-STD-810B, Method
516, Procedure V, without exhibiting damage or degradation.

The Storage Cards are designed to operate over a variety
of environmental conditions.
Operational environmental limits are defined below:
Temperature
Ambient air temperature range is 10°C to 50°C.

RELIABILITY AND MAINTENANCE
The Storage Cards were designed to provide high reliability of operation and rapid corrective maintenance in
case of component failure.

Thermal Shock
Both NS400-C Storage Cards can withstand a thermal
shock with a maximum rate of change of 30°C per hour
during operation.

RELIABI LlTY

Humidity

The cards were designed to the best commercial standards of workmanship, and a high degree of testing was
conducted (including tests over operating temperature
range) to insure a reliable service of ten years at twentyfour hours a day usage (exclusive of routine maintenance
time). The design is such that catastrophic failure occurrence is minimized and minimal propagation of such
failure will be experienced.

The Storage Cards have been designed to operate in a
relative humidity of up to 95% (without condensation).
Altitude
This system is capable of operation at altitudes from
-1,000 feet MSL to +1 0,000 feet MSL.

10-14

IIIClJllInCli

NOTES:

1. ALL RESISTOR PACKS ARE IN OHMS, t!i%,

1/IW,
2. ALL CAPACITOR VALUES ARE IN

MICROFARADS,
3, ICs DESIGNATED Cl·C4, 01·04, Et-E4, Fl·F4,
G1·G4, H1·H4, 11·14, Jl-J4, Kl·K4. LH4 ARE ALL
TYPE MM14C929, TYPICAL PINOUT
CONFIGURATION IS AS SHOWN BelOW,

, - - - b====i

r--

~==-'I ~I==-, :===~

~===; ~=-=-'II:==~ r==-,

= _ !====---,

====-~I :=1=_---, :===--,
1 :=1

==----, ;:::=="\

:===---'1 ~I==------, :===-,
~=i 1
1:=1=~ ~=--"\
1 :=1

'--1-.----

In:II

DTl :,A.
,
noW

I'"

UMDI,II,ZI,34D
U,4I,liZ,iii

.IAI.ICZ

leI

lBv

I~Y

Figure 6. NS400·CC Logic Diagram

II
Y~CII·3IID

4. It VOL TAGE AND GND PINS ARE AS FOLLOWS:
A1, A3.A4. 81, 83, AND B4

GROUND PIN D, Vee PIN 16. A2.82
GROUND PIN 7, Vec PIN 14.
5. Ie LOCATION OESIGNATIIIN USED:

Section 11

Reliability

iII

National consistently maintains tighter quality levels
than the industry for standard commercial products.
If you should decide that you need extraordinary
reliability levels, still tighter guarantees are available
from National through the B+, the A+, and the MICRO+
programs which are explained in brochures available
through your local National Field Sales Representative.

National's
Reliability Programs

OVERVIEW

SPECIAL REPORTS

The Microcircuits Reliability Assurance Department
routinely conducts a number of large~scale programs
which generate reliability data on National's products~
These programs include:

From time to time, Reliability Assurance also publishes
"tutorial" reports. These reports are intended to give
users of National's microcircuits better insight into the
subject of IC reliability.

• Product reliabil ity audits
•

New~product

•

New~process

•

Customer~funded

•

Engineering investigations

PACKAGE RELIABI LlTY

qualification tests
Package integrity remains the single largest stumbling
block to IC reliability. National has achieved a position
of leadership in package reliability. We maintain this
position with a heavy commitment to package~oriented
reliability studies. Much of this data has been "declas~
sified" and compiled into reports suitable for general
circulation.

qualification tests
qualification programs

Our Product Reliability Engineers and Failure Analysis
Engineers also work directly with many customers in
assisting their Component Reliability people in the
performance of reliability studies.

HOW TO OBTAIN REPORTS
The following lists those reports and other literature
currently available from the Microcircuit Reliability
Assurance Department. To obtain copies, call (408)
737·6686 or write to:

LIFE TEST DATA
Most of the reports generated by these reliability pro~
grams are proprietary to National or National's cus~
tomers~ However, we frequently do extract data for
uncontrolled circulation~ Copies of these "declassified"
reports are maintained on file in Reliability Assurance.
On special request, we can assemble generic Iife test data
on virtually every device manufactured by National.

Reliability Assurance, MIS 320
National Semiconductor Corporation
2900 Semiconductor Drive
Santa Clara, CA 95051

RELIABILITY BRIEFS
Reliability Assurance regularly publishes brief items of
current interest~ These Reliability Briefs are distributed
to all National sales offices when they are first issued.
Additional copies are available upon request.

NATIONAL RELIABILITY REPORT LISTING

•

Brief No.

Reliability Briefs

Anti~Static

Rails
Ultrasonic Cleaning
All That Glitters Is Not Gold
Epoxy B Flammability
Microcircuit Failure Analysis Requests

2
5
18
23
24

Report No.

• Other General Reliability Publications
The A+ Reliability Program brochure
The B+ Reliability Program brochure
The MICRO+ Reliability Program brochure
Semiconductor Device Reliability and the Arrhenius Model
(A primer on reliability nomenclature and temperature acceleration factor)
Microcircuit Failure Analysis Program
Epoxy B and the Quiet Revolution
National Epoxy B (The Epoxy B Story)
The Automotive Environment: The Ultimate Challenge
(A cost effective approach to reliability)
11·1

G~ 11
G~19

G~21

G·22

III

NATIONAL RELIABILITY REPORT LISTING (continued)

Package

Device

Report No.

Life Test Reports on Linear ICs

ALiC
LF311H
LM104
LM104H
LM108
LM109
LMl18
LM121H
LM308
LM308
LM3l1D
LM318

Voltage Comparator
Voltage Regulator
Voltage Regulator
OpAmp
Voltage Regulator
OpAmp
Precision Preamplifier
Op'Amp
OpAmp
Voltage Comparator/Buffer
OpAmp

H
H
H
H
K
H
H
N
H
D
N

L·117
L-98A
L·l00
L-96A
L-92A
L-l05
L·ll5
L-l02
L-86A
L-91A
L-l06

Voltage Comparator
Quad OpAmp
Quad Op Amp
Quad OpAmp
Quad Comparator
Quad Op Amp
Amplifier/Detector
Audio Power Amplifier
Low Noise Dual Preamplifier
Audio Power Amplifier
TV Video Detector
Chroma Subcarrier Regenerator
Quad Comparator
Chroma Subcarrier Regenerator
Quad Amplifier

D
N
N
N
H
N
N
N
N
N
N
N
N
N

L-l04
L-l11
L-l09
L-ll0
L-128
L-l0l
L-136
L-119
L-125
L-134
L-123
L-116
L-112
L-130
L-118

OpAmp
Three·Terminal Positive Voltage Regulator
Voltage Regulator
Voltage Regulator
OpAmp
OpAmp
OpAmp

H, N, J
P
P
H
N
H
H

L-127
L-122
L-90
L-99
L-88
L-93
L-114

OpAmp
Voltage Regulator
Three·Terminal Positive Voltage Regulator
Three·Terminal Voltage Regulator
Oscillator and Buffer
Timer
Voltage Regulator
Voltage Regulator
OpAmp
OpAmp
OpAmp
OpAmp
Modulator·Demodulator
Transistor Array
Programmable Op Amp

N
T
T
P
N
H
D
H
H
J
N
N
N
N
N

L-87
L-l03
L-126
l-131
L-133
L-129
L-97
L-137
L-107
L-124
L-85
L-89
L-132
L-120
L-121

CliC
LM239D
LM324J
LM324N
LM324N
LM339N
LM358
LM373
LM380
LM381N
LM390
LM1821
LM1887N
LM1901D
LM2887
LM2900,
LM3900
SliC
LF356
LM78L05
LM105
LM105H
LM301A
LM301A(E)
LM301AH,
LM741H
LM307
LM340T
LM340T
LM341-5
LM375N
LM555H
LM723
LM723
LM741
LM741J
LM741C
LM741C
LM1496N
LM3046
LM4250

11-2

(continued)
Package

Device

Report No.

• Life Test Reports on Memories
DM74S287,
DM74S387
DM7588N
MM1702A
MM2102
MM2708
MM5203Q
MM5280D
MM5280J
MM5270,
MM5280

Titanium·Tungsten Schottky Bipolar PROMs

M·4

256·Bit Programmable ROM
Electrically Reprogrammable ROM
N·Channel Silicon Gate 1024-Bit Static RAM
8k UV Erasable PROM
2k Static EPROM
N·Channel Silicon Gate 4096·Bit Dynamic RAM
N-Channel Silicon Gate 4096-Bit Dynamic RAM in CERDIP
Reliability Report on the 4k Dynamic RAM

N
Q
J, D, N
Q
Q
D
J

D·72
M·l
M·2
M·5
M-41
M·3
M-6

J
D
N

C-9
C-l0
C·ll

Shift Register
Eight·lnput Positive NAND Gate
Quad Two·lnput NAND Gate
Quad Two·lnput NAND Gate
Quad Two·lnput NAND Gate

N
N
D
N
N, J

D·80
D·74
D-76
D·82
D-73

TRI-STATE Quad Buffer
Hex-Inverter Buffer/Driver
Counter

N
N
N

D-78
D-81
D·83

J, N

D-79

D,N

RM·14

• Life Test Reports on CMOS Logic ICs
74C and 4000 series - CMOS Logic in CERDIP
54C and 4000 series - CMOS Logic in Hermetic DIP
74C and 4000 series - CMOS Logic in Epoxy B Package
• Life Test Reports on TTL ICs
DM74L95N
DM74S30
DM5400J
DM7400
DM54LSOOJ,
DM74LSOON
DM7093N
PM7406
DM7563

• Life Test Reports on I nterface I Cs
DM7880

Decoder/Driver

• Life Test Reports on Microprocessor ICs
I NS8080A,
SC/MP

N·Channel Microprocessor

11-3

NATIONAL RELIABILITY REPORT LISTING (continued)
• Package Reliability Reports
Subject

Package
CEROIP
EPOXY B
Hermetic DIP
Epoxy B
(TO·220)
Epoxy B
TO·5
Epoxy B
Epoxy B
Epoxy B
Epoxy B
(TO·92)
Epoxy B
CEROIP
Epoxy B
(TO·220)
TO·5, CEROIP,
Epoxy B
Epoxy B
Epoxy B
(TO·126)
Epoxy B
Epoxy B
Epoxy B
Epoxy B
Quartz·Lid DIP
Epoxy B
Hermetic
Hermetic

Epoxy B
Hermetic
CERDIP
Hermetic
Epoxy B
CERDIP
Epoxy B
CERDIP
Epoxy B
Epoxy B
CERDIP
Epoxy B
Epoxy B
Epoxy B
Epoxy B
Epoxy B

Report No.

National Semiconductor Ceramic Dual·ln·Line Package Reliability Report
The Reliability of Epoxy B in Accelerated Temperature and Humidity
Environments
The Effects of High Humidity and Bias on Hermetic Dual-In-Line Package
Power Cycle

G-17
G-18
G-20
L-103

and Humidity, Pressure Pot, Temperature Cycle, Thermal

L-l08

Cycle, Thermal Shock
and Humidity
Cycle
Cycle

L-114
L-116
L-118
L-119
L-122

Thermal Shock, Temperature Cycle, Pressure Pot
Thermal Shock, Temperature Cycle
Thermal Shock, Pressure Pot, Power Cycle

L-123
L-124
L-126

Thermal Shock, Temperature and Humidity

L-127

Temperature Cycle
Temperature and Humidity, Pressure Pot, Power Cycle, Temperature Cycle,
Thermal Shock, Solderability
Temperature and Humidity
Temperature and Humidity
Temperature and Humidity
Temperature and Humidity
Temperature Cycle, Thermal Shock
Temperature Cycle, Temperature and Humidity, Thermal Shock,
Solderabil ity, Lead Integrity
Thermal Shock, Temperature Cycle
Temperature Cycle, Thermal Shock, Solderability, Lead Integrity

L-128
L-131

M-4

Thermal Shock, Temperature Cycle, Mechanical Shock, Vibration
Temperature Cycle

M-6
RM-14

Temperature Cycle, Thermal Chock, Acceleration, Mechanical Shock,
Solderability, Moisture Resistance, High Temperature Storage
Temperature Cycle, Thermal Shock, Pressure Pot, Moisture Resistance
Temperature and Humidity, Pressure Pot, Temperature Cycle, Power
Cycle
Pressure Pot, Temperature Cycle, Power Cycle
Temperature and Humidity

C-9

Temperature
Temperature
Temperature
Temperature

D-80
D-81
D-82
D-83

Temperature
Shock
Temperature
Temperature
Temperature
Temperature
Power Cycle

and
and
and
and

Humidity,
Humidity,
Humidity,
Humidity,

Temperature
Pressure Pot,
Pressure Pot,
Temperature

11-4

Cycle
Temperature Cycle
Temperature Cycle
Cycle, Pressure Pot

L-132
L-133
L-134
L-136
M-l
M-2
M-3

C-11
D-73

D-74
D-79

Section 12

Definitions
and Standards
Standardization of terms used in memory specifications
is essential. Excerpts of I EEE proposed standards are
presented here for future reference. A short list of
acronyms is also included in this section.

Definitions
of Frequently-Used
Acronyms

ACE

Asynchronous Communications Element (lNS8250)

ASCII

American Standard Code for Information Interchange

BCD

Binary Coded Decimal

BPNF

Begin/Positive/Negative/Finish

BRK

Break

CAS

Column Address Strobe

CCD

Charge Coupled Device

Chip Enable

CERDIP

Ceramic Dual-In-Line Package

CFM

Cubic Feet per Minute

CMOS

Complementary Metal Oxide Semiconductor

CPU

Central Processing Unit

CRT

Cathode Ray Tube

CRTC

CRT Controller (DP8350)

Chip Select

DED

Darkness Emitting Diode

Data Input

DMA

Direct Memory Access

Data Output

EPROM
12L

Erasable Programmable Read Only Memory

I/O

Input/Output

LCDS

Low Cost Development System

LED

Light Emitting Diode

LSB

Least Significant Bit

Integrated Injection Logic

LSI

Large Scale Integration

MOS

Metal Oxide Semiconductor

MPS

Mask Programming System

MSB

Most Significant Bit

MSI

Medium Scale Integration

MSL

Mean Sea Level

NSC

Memory Support for you

Output Enable

Printed Circuit

PROM

Programmable Read Only Memory

RAM

Random Access Memory

RAS

Row Address Strobe

RMW

Read/Modify/Write

ROM

Read Only Memory

RIW

ReadIWrite

RWM

ReadIWrite Memory

Sense Enable

TSP

Tri-Share Port

TTL

Transistor - Transistor - Logic

Write Enable

12-1

Excerpts from the Proposed
IEEE Standard for
Semiconductor Memory
Data Sheet Generation*

Table of Contents

Introduction

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1

The purpose of this standard is to provide guidelines
under which data sheets for new semiconductor memories are to be generated. Following these standards
should produce data sheets that are concise and that
consistently define the operation and characteristics of

Product Description . . . . . . . . . . . . . . . . . . . . . 1
1. Logic Definitions . . . . . . . . . . . . . . . . . . . . . . . 1
2. Logic Diagrams . . . . . . . . .

......... 2

semiconductor memory devices.

3. Input/Output Definitions . . . . . . . . . . . . . . . . . 2

Product Description

4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . 2
5. Operating Conditions . . . . . . . . . . .

Product description consists of information typically
(but not necessarily) contained on the front pages of a
memory data sheet. It should include all of the following

....... 2

6. Electrical Parameter Nomenclature . . . . . . . . . . . 2

information:

Product name and number
Manufacturer's name
Summary of product features and advantages
Description of product
Identification of technology used
Logical block diagram
Pin assignments
Function tables
Logic symbol
Input/output definitions
Description of device operation

7. Power Supply Nomenclature . . . . . . . . . . . . . . . 2
8. Other Electrical Parameter Nomenclature . . . . . . . 2
9. Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 3
10. Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . 3
11. Transition Definitions ..

. ........ 3

12. Nomenclature for Timing Parameters . . . . . . . . . 3
13. Transition Measurement Points . . . . . . . . . . . . . 4
14. Incorporation of Transition Measurement
Points in Timing Parameter Nomenclature . . . . . 4

1. Logic Definitions

15. Refresh Time . . . . . . . . . . . . . . . . . . .. .. ... 4

Care should be taken in all definitions and descriptive
information to consistently define logic states, particularly in the use of the terms TRUE/FALSE, HIGH/LOW,
Active/Inactive, and ONE/ZERO. A logic TRUE is by
definition a logic ONE and is logically Active; it may be
electrically a HIGH or a LOW. Conversely, a logic
FALSE is by definition a logic ZERO and is logically
Inactive and may be an electrical HIGH or LOW. For
positive logic a logic TRUE is a HIGH and a logic FALSE
is a LOW whi Ie the opposite is true for negative logic.
For positive logic, a non-barred signal is TRUE (Active)
when HIGH, a barred signal is TRUE (Active) when
LOW. Positive logic is assumed unless otherwise stated.
This can be represented as:

16. Alternate Forms of Commonly Used Terms . . . . . 4
17. Symbols for Alternate Form . . . . . . . . . . . . . . . 5
18. Examples of Alternate Forms . . . . . . . . . . . . . . 5
19. Additional Descriptive Information . . . . . . . . . . . 5
20. Definition of Maximum and Minimum . . . . . . . . . 5
21. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
22. Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . 6
23. Uncertainties . . . . . . . . . . . . . . . . . . . . . . . . . 6
Appendix I Definition of Input/Output (Pin)
Names . . . . . . . . . . . . . . . . . . . . . . . . 6

Logical Terms

Electrical Terms
Positive Logic

*The material in this section was excerpted from a document

prepared by the IEEE Task Force, P662, on Semiconductor
Memory Terminology and Specifications in cooperation with
JEOEC JC-42 committee on Semiconductor Memories 11/16/77.
All rights to this material are reserved by the Institute of Electrical

Negative logic

Active == True == 1

HIGH

LOW

Inactive == False == 0

LOW

HIGH

and Electronics Engineers, Inc.

HIGH is defined as the most positive and LOW as the
most negative electrical level.

12-2

6. Electrical Parameter Nomenclature
Since it is very common to mix active HIGH and active
LOW inputs/outputs on a single memory device, care
should be taken not to confuse HIGH with logic ONE.
It is recommended that input and output levels be
referred to as HIGH and LOW. When it becomes neces·
sary to describe the logical operation of a device, the
preferred terms are TRUE and FALSE. The use of ONE
(1) and ZERO (0) should be avoided on the data sheet.

Electrical parameters are specified with an initial symbol
that specifies the type of the parameter and subsequent
symbols that further define the type of measurement.
Initial symbols include:
V = Voltage
I = Current
P = Power
e = Capacitance

2. Logic Diagrams

Although electrical parameters have traditionally Qeen
written as subscripted symbols, they may be used in the
non'subscripted format.

The logic diagram should logically and functionally
define the operation of the memory device. Drawings
should adhere to IEEE Standard 91·1973/ANSI
Y32.14·1973.
3. Input/Output Definitions (Pin Names)

Subscripted

Non·Subscripted

VIH

10L

VCC

Where multiple symbols of a single type are required,
such as for multiple addresses and/or data inputs/outputs,
numbering should begin at 0 and go to N-1. Unlike
address and data inputs, multiple control inputs which
perform the identical function, such as multiple chip
selects, etc., should be numbered from 1 to N. Control
inputs which do not perform identical functions should
be given separate names.

10L

vec

7. Power Supply Nomenclature
Power supplies should be designated as a three·letter
symbol:
VCC = principal collector bias voltage
VEE = principal emitter bias voltage
VBB = principal base or substrate bias voltage
VOD = principal drain bias voltage
VGG = principal gate bias voltage
VSS = principal source bias voltage

A logical bar should be used over I/O names and symbols
to designate negative TRUE (i.e., active LOW, low
TRUE). In cases where the use of a logical bar is not
practical a letter B may be appended to the pin name to
indicate that the signal is negative TRUE (i.e., RE would
be REB). The logical bar should be omitted when
forming symbols for timing intervals.

If other designators are used, they shou Id follow the
same format and should be defined in the data sheet.
The second and third letter in a power supply symbol
shall always be the same. In some systems, a single
power supply will be used for multiple purposes such as
a collector bias supply for some devices and a drain bias
supply for other devices. On devices commonly used
with other logic families, the generic power supply name
can be substituted.

4. Absolute Maximum Ratings
The absolute maximum ratings define the range of
conditions to which the device can be submitted without
affecting the operation of the device after it is subse·
quently returned to the specified operating range. All
conditions which might impair the operation of the
device such as signal and power supply sequencing, time
limits on stress conditions, or static discharge conditions,
should be clearly stated. Since the absolute maximum
ratings are outside the operating range, device operation
is not implied.

In all cases substitution of I or P for V in the above list
wi II define the current or power, respectively, associated
with that power supply_ PD shall be the symbol for the
total power dissipation in the device with no external
load.

5. Operating Conditions

8. Other Electrical Parameter Nomenclature

The range of conditions under which the product speci·
fications are warranted should be clearly stated at the
beginning of .the product specification section of the
data sheet or at each location in the data sheet where
device parameters are given. These conditions should
always include temperature and voltage range. If opera·
tion of the device also depended on transient conditions
on the power supplies or other inputs, these constraints
should be clearly stated in the operating conditions.
Additionally, timing measurement reference points and
output load conditions should be given. Where addi·
tional conditions are not specified, the parameter limits
shall be assumed to apply over the full operating range
of the device.

The second letter of a non·power supply symbol desig·
nates the type of Input/Output pins to which the
measurement applies:
I = Input
0= Output
The third symbol designates the state applied to an
input or to the state of an output (or the state the
output would be in if not externally forced to some
other state) of this/these I/O pin(s) during the measure·
ment.

H = HIGH
L = LOW
Z = OFF (High Impedance state)

12·3

A fourth symbol may designate an external cond ition
forced on an output.
S ~ Short circuit (connected to ground unless otherwise specified)
H ~ HIGH
L = LOW
Z = OFF (High Impedance state)

The five symbols and their definitions are:
H ~ A transition from any level to a HIGH logic level.
L

A transition from any level to a LOW logic level.

A transition from any level to a valid steady-state
level.

A transition from any level to an unknown,
changing, or don't care level.

A transition from any level to a high-impedance
"OFF" state.

Examples:
VOH

Voltage on an output in the HIGH state.

IlL

Current through an input in the LOW state.

IOHS

Output short circuit (to ground unless
otherwise stated) current with the device
output driving HIGH.

IOZH

12. Nomenclature for Timing Parameters
Timing parameters are the measurement of the time
elapsing between a transition on one pin and a transition
on the same or another pin. These timing intervals can
be written as:

Output current with the output in the
high-impedance state (OFF) and driven
HIGH.

T ABCD

tABCD

where:
Although the symbols may be used in a subscripted
form, they may also be listed as a single, uppercase, nonsubscripted line in data sheets and related material.
Conventional current (not electron current) flowing into
the device is defined as positive; current flowing out of
the device is defined as negative.

Tor t

indicates time.

is the name of a signal or the terminal
at which a transition occurs marking
the beginning of the time interval
being specified.

designates the direction (and possibly
the measurement point) for the
transition at terminal A.

is the name of a signal or the terminal
at which a transition occurs marking
the end of the time interval being
specified.

designates the direction (and possibly
the measurement point) of the
transition at terminal C.

9. Timing Parameters
The timing parameters section of the data sheet defines
the time dependent performance of the device. The
timing parameters shoUld be divided into two groups:
timing requirements of the device and timing responses
of the device. Timing requirements define the requirements on the input signals required for correct (specified)
device operation and are always measured from one
timing transition on an input or output to a timing
transition on a device input. Timing responses specify

An inverter provides a simple example. If the input is
labeled I and the output is labeled Y, then the two delay
parameters for the inverter become TI HYL and TI LYH.

device performance and are measured from an input or

output timing transition to a device output timing
tranSition. Timing requirementS should be clearly
separated from timing responses by grouping in a
separate table or a separate section of a single table and
by appropriate labeling.
10. Logic States (Levels)
Logic states (levels) are defined as a condition on an
input or output. The states are;
1)

HIGH

LOW

VALID

Defined data satisfying one of the
two above conditions, 1) or 2)

INVALID

Data either not satisfying 1) or 2)
above or undefined or don't care

OFF

In the high impedance third state
or OFF state

? Minimum VIH or VOH

.;; Maximum VIL or VOL

I--TIHYL~

11. Transition Definitions
There are five kinds of transitions which are used as
beginnings and ends of time interval measurements. The
transitions are defined in reference to the final state to
which the change is made.

12-4

kTILYH..j

\~_l

The first interval is the delay from I HIGH to Y LOW
and the second from I LOW to Y HIGH.

would represent timing point 1 on that transition to a
HIGH level. Transition H2 would represent timing point
2 in the transition to a HIGH level. Similarly, transition
L2 would be timing point 2 in a transition to a LOW
level and transition point L1 would be timing point 1
during a transition to a LOW level.

All types of timing parameters can be described in this
format. Examples of timing intervals are:
1)

Combinational Delays - from input transition to
output transition.

Set·up and Hold Times - from input transition
to another input transition.

Pulse Widths (Duration) - from input going
LOW (or HIGH) to the same input going HIGH
(or LOW).

Cycle Times - from an input transition to the
next occurrence of the same transition.

Transition Times - from the beginning of an
input or output transition to the end of the same

Measurement points associated with high impedance
OFF state are dependent on external loads applied to
the device. Therefore, the data sheet should clearly show
the external load and the specific voltage measurement
points used to define the Z level.
The use of numbered timing points is illustrated below:

transition.

13. Transition Measurement Points
Transitions should be measured from fixed, clearly
defined voltage points. These voltage points should be
expressed as fixed voltages referenced to one of the
power supply pins.
VALID

Examples:
1.5 Volts
VDD - 2.0 Volts
2.0 Volts

It is recommended that timing points not be expressed
as a percentage, i.e., do not use 10% and 90%. Do use,
for example, 1.2 Volts and VDD - 1.2V.

_TEH2AX---!

Data sheets should clearly define both the beginning and
the ending voltage levels and the transition measuring
points for all transitions.

15. Refresh Time
Refresh is the operation of restoring charge in a dynamic
memory cell. Refresh time is the time between successive
refresh operations.

14. Incorporation of Transition Measurement Points
in Timing Parameter Nomenclature
In some cases, it is desirable to define more than one
timing point in a transition. Particularly in MaS circuits
it is desirable to define for a single LOW to HIGH

Since refresh is a complex operation to define logically
it is suggested that R be used as the symbol to define the
refresh operation. The symbol for refresh time is there·
fore written as TRVRV. TREF or tREF may also be
used to designate the refresh interval. A logical definition
of the meaning of refresh should be given in the data
sheet (e.g., cyclic, charge pump, planar, etc.).

transition:

a point at or near VI L

a point at or near VIH

Likewise, when making a HIGH to LOW transition, two
similar timing points can be defined.

16. Alternate Forms of Commonly Used Terms
Certain terms such as access, cycle, hold, set·up, pulse
duration, and transition times are commonly used to
define certain classes of timing intervals. An alternate
format for naming these intervals is desirable for reasons
of tradition and efficiency. These timing intervals can be
written as:
TX(Y)

VALID

tX(Y)

where:

Multiple Timing Points in a Transition

Where it is necessary to define more than one timing
point on a single transition, these timing points should
be followed by a number. For example, transition H1
12·5

Tor t

indicates time.

is the type of timing interval as shown in
section 17.

is a pin name as defined in section 3 and
tells something about the timing interval
X. See section 17.

19. Additional Descriptive Information

17. Symbols for Alternate Form
Significance of Y

Interval

Symbol
A

Access Time

Beginning measurement point

Cycle Time

Measurement point

Hold Time

Ending measurement point
Beginning measurement point

Set-up Time

Width (duration) Signal name
Time

Transition Time Signal name

REF

Refresh Time

In some cases it is desirable to include additional descriptive information to further define a symbol. This infor·
mation sometimes limits the definition to a certain mode
of operation such as read or write or program mode.
This information can be included in the TX(Y) format
by adding it after the information in parentheses and can
be included in the TABCD format by including it in
parentheses after the normal symbol as shown below.
Examples:
TC (E) RD
} Read cycle time
TEHEH (RD)

(not used)

TW (E) WR
} Chip Enable duration for Write
Cycle
TEHEL (WR)
TS (A) P
TAVEH (P)

18. Examples of Alternate Forms
TA (A)

= TAVQV

T A (E)

T A (G)

= TGHQV
= TEHEH or

TC (E)

TEHQV

Chip Enable access
Output Enable access

20. Definition of Maximum and Minimum

Cycle time of Chip Enable

TC (EH1)

TH (A)

= TEHAX

Add ress hold time

TH (D)

= TWHDX

Data hold time from Write

TH (D)

TS (A)

= TAVEH

TS (D)

TDVWL

Data set-up time with respect
to Write Enable

TW (E)

TEHEL or
TELEH

Chip Enable
(duration)

pulse

width

TW (W)

= TWHWL or

Write Enable
(duration)

pulse

width

TELDX

TWLWH

Address set-up time in programming mode for a PROM

In each case, any additional descriptive information such
as RD for READ or P for PROGRAM should be defined
in words or table form.

Add ress access

TELEL
TEH1EH1

}

In all tables in the product specification section, it is
important to define wherever possible values for maximum, typical, and minimum specifications. Typical
specifications can be especially important when using
statistical design techniques. Whether a parameter is
specified as a minimum or maximum depends on whether
it is considered from the system standpoint (what must
be done to the device) or from the device standpoint
(how thedevice responds to inputs). Timing requirements
should be specified from the system standpoint. Therefore, set·up time is specified as a minimum since the
system must provide this set-up time to the device.
Timing responses are specified from a device standpoint.
Access time is specified as a maximum, since it is the
maximum response time of the device. The typical
values are measured under the nominal operatin~ conditions (voltage, temperature, etc.) and are defined as the
median value taken over a wide number of samples
which span the normal variations for that parameter
which are found in the production situation. It is particularly important in capacitance measurements and
current levels that typical as well as maximum levels be
given.

Same as above with specified
measuring point

Data hold time from Chip
Enable
Address set-up time

TT (E)

= TEHl EH2 or Chip Enable transition time

TREF

= TRVRV

TEL2EL1
Refresh time

Care should be taken in defining three-state outputs to
always specify the minimum time to the output turning
ON and the maximum time to the output turning OF F
such that the user can insure that an overlap condition
does not occur.

Notice that in several cases the alternate form is
ambiguous. Care should be taken to precisely define the
interval by reference to the precise symbol in the TABCD
format. When the TX(Y) format is used, the TABCD
equivalent symbol. should be included in the timing
parameter specification table to define the alternate
symbol. Either or both forms can be used in the timing
diagram and other sections of the data sheet once the
TX(Y) symbols have been defined by equating them to
a T ABCD symbol.

21. Timing Diagrams
As described in section 10, five discrete logic levels
exist. These five logic states are shown graphically below
as used in timing diagrams.

Whenever the timing interval cannot be defined as one of
the seven types of intervals defined in the TX(Y) format,
it must be defined in the TABCD format. Use of the
TX(Y) format is optional since all intervals can be
defined in the TABCD format.

12·6

HIGH

LOW

VALID

INVALID

OFF

• •••••••••••••••

22. Transitions

23. Uncertainties

Transitions from one state to another are shown by
connecting the symbol for one state with that of the
final state with a sloped line. The slope of the line

In cases where the exact time of the transition may vary
or be unimportant, the transition should be drawn as a
series of parallel transition lines. This series of transition

lines should span the region in which the transition may

represents a non-zero transition time.

occur.

11111/11111

\-------....................
v

Definition of Input/Output (Pin) Names
Recommended
Symbol

Definition

Name

Address

Those input(s) whose logic states select a particular cell or group of cells.

Data Input

The input(s) whose logic state(s) determine(s) the data to be written into
the memory.

Data Output

The output(s) whose logic state (s) represent(s) the data read from the
memory.

Data Input/Output

The portIs) that function as data input during write operations and as
data output during read operations.

Shift Clock

The input(s) that when operated in a prescribed manner shift internal
data in a serial memory.

Write Enable

The input(s) that when true enable(s) writing data into the memory. The
data sheet must define the effect of both states of this input on the
reading of data and the condition of the output.

Program

The input(s) that when true enable(s) programming, or writing into, a
programmable read only memory JPROM).

Output Enable

The input(s) that when false cause(s) the output to be in the OFF or high
impedance state. This pin must be true for the output to be in any other
state.

Not Connected

The input(s)/output(s) that are not connected to any active part of the
circuit or any other pin or any conductive surface of the package.

Chip Enable

The input(s) that when true permit(s) input, internal transfer, manipula'
tion, refreshing, and output of data and when false causes the memory to
be in a reduced power standby mode.

Chip Select

The input(s) that when false prohibit(s) writing into the memory and
disables the output of the memory.

NOTE;
Chip Enable is a clock or strobe that significantly affects the power dissipation of the memory. Chip
Select is a logical function that gates the inputs and outputs. For example, Chip Enable may be the cycle
control of a dynamic memory or a power reduction input on a static memory.
RE

Row Enable (RAS)

The input which is used to strobe in the row address in multiplexed
address RAMs.

Column Enable (CAS) The input which is used to strobe in the column address in multiplexed
address RAMs .
. . National will continue to use 00

Output Disable on selected parts - Ed.

12·7

Section 13

National's
Literature Index
National Semiconductor's Data Bookshelf is a compen·
dium of information about a product line unmatched in
its breadth in the industry. The sixteen independent
volumes that comprise the Bookshelf - over 5000 pages
- describe in excess of 10,000 solid·state devices;
devices that span the entire spectrum of semiconductor
processes, and that range from the simplest of discrete
transistors to microprocessors.
Active and passive devices and circuits; hybrid and
monolithic structures; discrete and integrated com·
ponents ... complete electrical and mechanical specifi·
cations; charts, graphs, and tables; test circuits and
waveforms; design and application information
Whatever you need you'" find in the designer's ultimate
reference source - National Semiconductor's Data
Bookshelf.

The Data Bookshelf:
Tools For The
Design Engineer
CMOS DATABOOK

LINEAR APPLICATIONS, VOL. II

National's Series 54C/74C logic is pin-for-pin, functionfor-function equivalent to standard 7400 TIL. As such,
you can take full advantage of your knowledge of 7400
when you use 54C/74C; all the design tricks of the one
work with the other. Further, 54C/74C logic follows
strict, consistent design rules set-up to simplify system
design by giving you realistic, workable parameters with
which to wOrk.

The second volume of National's Unear Applications
Handbook picks up where Volume I left off. Applications, notes and briefs, and pertinent articles published
in the 3 years since Volume I was printed are included
in this handbook. Volume II retains the same format as
Volume I, to facilitate its use.
In this volume, as in Volume I, application schematiCS
call out the generic family, which, by coincidence, is the
military temperature range version of the device. Generally, any device in the generic family will work in the
circuil. For example, an amplifier marked LM108 refers
to the generic 108 family, and does not imply that only
military-grade devices will work. Military (or industrial)
grade devices need only be considered when their
tighter electrical limits or wider temperature range warrant their use. As a reminder to our users, our numbering system is:

The CMOS Databook completely specifies our 54C174C
logic products, as well as Series-4000 CMOS. Functions
described include gates, buffers, flip-flops, counters,
shift registers, decoders/demultiplexers, arithmetic functions, and more. For those who may be unfamiliar with
CMOS logic, the text incorporates a series of application
notes that define 54C/74C logic and show how to use il.
Mar. 1977, 560 pages, $4.00

INTERFACE DATABOOK

Device
No.

Peripheral/power drivers, level translators/buffers, line
drivers and receivers, memory and clock drivers, sense
amplifiers, display drivers, opto-couplers ... you'll find
them all in the Interface Databook; page after page of
specifications that describe one of the industry's
broadest line of interface products.

LM1XX
LM2XX
LM3XX

SpecIfied
Grade
Military
Industrial
Commercial

Temperature Range
-55°C,.; TA ,.; +125°C
-25°C,.; TA ,.; + 85°C
O°C,.; T A ,.; + 70°C

Because commercial parts are less expensive than
military or industrial, these points should be kept in mind
when trying to determine the most cost-effective approach to a given design.

And to help you get the most from the circuitry, the text
includes application notes that discuss such topics as
transmission lines, data transmission in high-noise
environments, driving gas-discharge and LED displays,
and more. There are also product guides - listings that
help you pick just the right circuit for your job from the
many available; and even a cross-reference guide that
lists product type numbers from other makers and gives
the exact-replacement National part number.

July 1976, 256 pages, $4.00
LINEAR DATABOOK

LINEAR APPLICATIONS
HANDBOOK, VOL. I

This edition of National's Unear Databook has been reformatted to make it more useful. Several new sections
have been added which reflect National's larger and
more diverse Linear product line. Added are Voltage
References, Instrumentation Amplifiers, Sample and
Hold circuits, and NO and O/A converters. What was
formerly the Consumer section is now Audio, Radio and
TV, and the old Functional Blocks are now Industrial/
Automotive/Functional Blocks.

This handbook provides you a fully-indexed, crossreferenced collection of linear integrated-circuit applications for National's monolithic and hybrid circuits.

The BI-FET process is a technological breakthrough
pioneered by National, integrating implanted JFETs on
the same chip with standard bipolar tranSistors.

Individual application notes are normally written to explain the operation and use of one particular device, or
to detail various methods of accomplishing a given function. The organization of the Unear Applications Handbook takes advantage of this innate coherence: it keeps
each application note intact, arranges them in numerical
order, and provides detailed subject indices. The indices
are composed Of more than a thousand references to
the main body of each text, and are the key to effiCient
access to the linear-applications experience garnered by
National Semiconductor during the past eight years.

The dramatic results are order-of-magnitude improvements in input characteristics, slew rates, and noise
specifications. Products include LF156 series op amps,
LF198 sample and hold, LF152 instrumentation
amplifier, and LF11331/LF11201 series quad analog
switches.

The Interface Databook concludes with discussions of
MIL-STO-883 and MIL-M-38510, and three pages of dimensioned package-outline drawings.

19n,560 pages, $4.00

Guides pertinent to a particular section are now found at
the beginnning of that section. Included are section contents, selection guides and/or definition of terms. This
now allows the user to find all information conceming
any particular product in one section without looking
through the entire catalog. Ordering information, table of

Feb. 1973, 432 pages, $4.00
13-1

contents, reliability programs, and any other information
common to all sections is located in the front or back of
the catalog.

prepared this booklet of articles reprinted from industrial
publications.
Starting with fundamentals, it details National's microprocessor technology - the devices, the support
equipment, and the technical considerations. Equally
important, it describes the spectra of successful applications from successful companies. By examining the
technology and the applications you can see the microprocessor solution to your problems.

National's Linear line is moving in new directions, summarized by looking at several developments which have
taken place in the past year.
A family of 15 D/A and AID products are being manufactured including 8-, 10- and 12-bit D/A and AID converters, successive approximation registers, dual slope
AID's for panel meters, and precision voltage references. We have the distinct advantage of using anyone
of our many proceSSing technologies to optimize the
D/A, AID design.

1977,128 pages, $3.00

MOS/LSI DATABOOK

A low noise, ultra stable subsurface zener pioneered at
National, is combined with a temperature stabilizer on a
single chip to make the LM199 series precision voltage
references. The LM199 features 1 ppml"C guaranteed
drift, 20 ppm long term stability, and 0.5!1 dynamic impedance at highly competitive prices. An LM129 series
unheated version is also available.

This Databook presents National's broad capability in
the MaS/LSI areas - the fastest growing segment of
the integrated circuit industry.
This 14 chapter, 750 page catalog covers a wide spectrum of product categories such as: Digital Electronic
Clock circuits, Counter/Timers, Electronic Organ circuits,
TV circuits, Analog-to-Digital (A/D) Converters, Communications/CB Radio circuits, Digital Watch circuits,
Calculator circuits, and Keyboard Encoder circuits, all of
which are described in complete electrical and mechanical specifications.

New directions in Linear are aimed at development of
building block circuits. Quad devices such as the
LM124, LM139 and LM1900 series are finding wide acceptance as cost-saving alternatives to single and dual
devices. The new LMI48, LM149 quad 741 family is a
versatile addition to this group which provides class AB
outputs and wideband operation. The building block
trend also includes timers (LM556), audio, radio and TV
circuits, and in particular, automotive circuits (LM2907,
LM2917 frequency to voltage converter).

Custom MaS/LSI capabilities are also described for six
MaS technologies. In addition, National's new family of
Controller Oriented Processor Systems (COPS) is presented. This family addresses a wide variety of low-cost
controller applications such as: Appliance Timers, Photo
Timers, Lawn Sprinkler Controllers, Electronic Scales,
Electronic Cash Registers and Traffic Controllers.

June 1976, 968 pages, $4.00

Two support circuit sections are also included. These
are Display circuits and Interface Drivers. A separate
section also covers Clock Modules, which describes
completed modules employing National's electronic digital clock circuits and LED displays.

MEMORY DATABOOK
Most of National's memory and memory-related products, regardless of their technology, are grouped
together in the Memory Databook: a convenient,
single-volume source of information and specifications
about bipolar, MaS, and CMOS RAMs, field- and
mask-programmable ROMs (bipolar and MaS), MaS
shift registers, and PLAs.

The MaS/LSI Databook presents state-of-the-art
semiconductor products with LSI complexity for all MaS
products except for MaS Memories and Microprocessors which are represented in separate
Databooks.

In addition, the Memory Databook describes interface/
support circuits for memory operation, and National's
line of complete memory systems. Nor is how-to-use information neglected: there is a selection of memoryoriented application notes, including one on designing
with PLAs. To aid you further, there are RAM, ROM,
and PROM cross-reference guides, and even a
production-status guide to National memories.

1977,720 pages, $4.00

PRESSURE TRANSDUCER HANDBOOK
This is the new catalog and handbook of integratedcircuit pressure transducers from National Semiconducto.r. In addition to complete specifications and a
quick selection guide for National's IC transducer products, this edition includes comprehensive discussions
of transducer theory, device structure, reliability and indepth application data including circuits for the new
easy-to-use autoreference compensation technique for
improving accuracy in any application.

1977,544 pages, $4.00

MICROPROCESSOR APPLICATIONS IN
BUSINESS, SCIENCE AND INDUSTRY

Because IC transducers are finding use in many and diverse disciplines, the breadth of application information
includes traditional, non-traditional and state-of-the-art
fields as well. National hopes this catalog/handbook
provides the requisite insight and data for your own
special applications.

For years National's microprocessors have impacted
every facet of the application spectrum - from consumer games and point-of-sale terminals to scientific instruments and heavy industrial controls. Their use is
growing rapidly. Today, those who are not actually using
or conSidering microprocessors in their products stand
to lose the competitive edge. And, that's why we have

1977, 142 pages, $3.00
13-2

In conjunction with other SC/MP support documents,
this Applications Handbook provides the user with sufficient information to build, checkout, and utilize a wide
variety of SC/MP based systems. The information is organized in capsule form; thus, the designer can, with
minimum effort, expand, modify, or customize a given
application.

Besides specification sheets and package outline drawings, the book includes Process Characteristics sheets.
These sheets describe and illustrate the many chip
types used in National's discretes, and fully specify (via
tables and curves) the performance of any device built
with given process. Thus, a relatively-limited number of
Process Characteristics sheets describes thousands of
devices; a Standard Transistor Parts list refers each
transistor type to a particular Process Characteristics
sheet that determines the specifications for the device.

The applications are organized by class - Analog-toDigital/Digital-to-Analog Systems, Keyboard/Display Systems, Multiprocessor Systems, and so on. Chapter I and
the appendices provide general design data as regards
the instruction set, addressing modes, input/output
capabilities, interrupt structures, and other applications
related features.

The Discrete Databook includes a great deal of helpful
information apart from the specifications themselves:
Mil-STD qualification data; bipolar and FET dice availability; a bipolar-transistor equivalents list; how to
choose the proper JFET; a JFET applications guide;
and a JFET cross-reference listing. There is also an extensive glossary of JFET terms and symbols.

1977,160 pages, $5.00

Feb. 1978, 480 pages, $4.00

SPECIAL FUNCTION
DATABOOK

TTL DATABOOK

SC/MP MICROPROCESSOR
APPLICATIONS HANDBOOK

This collection of circuits contains detailed information
for the specification and application of a large number
and variety of products, which are grouped together because most of them are hybrid modules with unusual
characteristics.

This volume of the Data Bookshelf has become one of
the industry's best-known sources of DTLlTTUECl product information. It fully specifies National's extremelybroad line of bipolar logic; standard 54/74TTl; lowpower 54U74l; high-speed 54H/74H; ultrahigh-speed
Schottky 54S/74S; low-power Schottky 71 lS/81 lS;
Series 9000 TTL; Series 10,000 ECl; and Series 930
DTL.

In the Sample-and-Hold Amplifiers section, for example,
you'll find precision sample-and-holds, fast S/H, veryfast S/H, and a compact, complete-with-everything S/H
module. Under the Analog Switch heading are DPDT
and DPST MOS/FET and JFET switches, quads, duals,
low-cost switches, high-speed switches, multiplexers,
commutators, etc. And under Amplifiers you'll find micropower and low-power op amps, high-voltage types,
wideband types, high-slew-rate amps, and so on. Besides the product categories just mentioned, the Special
Function Databook also describes AD/DA converters,
buffers, comparators, MOS clock drivers, digital drivers,
resistor arrays, and active filters; there are three op amp
selection guides, and FET op amp and analog switch
cross-reference listings as well.

These logic families include just about any function a
designer is likely to need: gates; buffers/drivers; flipflops, latches, and storage registers; counters; shift registers; multiplexers/demultiplexers; decoders/decoder
drivers; display drivers; comparators; parity generators;
one-shots; multipliers; arithmetic circuits; etc. Specifications include complete electrical performance characteristics and package dimensions; separate sections describe ac test circuits and switching waveforms.
Feb. 1976, 592 pages, $4.00

Apr. 1976, 308 pages, $3.00

ORDERING INFORMATION
All orders must be prepaid. Domestic orders must be
accompanied by a check or a money order made payable to National Semiconductor Corp.; orders destined
for shipment outside of the U.S. must be accompanied
by U.S. funds. Orders will be shipped by postage-paid
Third Class mail. Please allow approximately 6-8 weeks
for domestic delivery, longer for delivery outside of the
U.S.

DISCRETE DATABOOK
National's discrete. semiconductors are described and
specified in the Discrete Datebook. In addition to
bipolar and JFET small-signal transistors, the text
covers multiple-bipolars, multiple JFETs, and power
transistors, including commercial, industrial, and JAN/
JANTX/JANTXV types.

13·3

DATA BOOKSHELF ORDER FORM
Please send me the volumes ofthe National Semiconductor DATA BOOKSHELF that I have
selected below. I have enclosed a check or money order for the total amount of the order,
made payable to National Semiconductor Corp.
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Purchase Order # _ _ _ _ __
Street Addres"-s_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _ _ State/Country _ _ _ _ _ _ _ _ Zip _ _ __
_ _ copies @ $4.00, CMOS Databook, 3/77 ................... Total
_ _ copies @ $4.00, Interface Databook, 1977 ................. Total
_ _ copies @ $4.00, Linear Applications, Vol. I ................. Total
_ _ copies @ $4.00, Linear Applications, Vol. 11 ................ Total
_ _ copies @ $4.00, Linear Databook, 6/76 .................... Total
_ _ copies@$4.00,MemoryDatabook,1977 .................. Total
_ _ copies @ $4.00, Memory Applications, 1978 ............... Total
_ _ copies @ $3.00, Microprocessor Applications in
Business, Science and Industry, 1977 ...... Total
_ _ copies @ $4.00, SC/MP Microprocessor Applications, 1977 .. Total
_ _ copies @ $4.00, MOS/LSI Databook, 1977 ................. Total
_ _ copies @ $3.00, Pressure Transducer Handbook, 1977 ...... Total
_ _ copies@$3.00,SpeciaIFunctionDatabook,4/76 ........... Total
_ _ copies @ $4.00, Discrete Databook, 2/78 .................. Total
_ _ copies @ $4.00, TTL Databook, 2/76 ...................... Total
Subtotal

$ _ _ __
$ _ _ __
$ _ _ __
$ _ _ __
$ _ _ __
$, _ _ __
$ _ _ __
$ _ _ __
$ _ _ __
$ _ _ __
$ _ _ __
$, _ _ __
$ _ _ __
$ _ _ __
$ _ _ __

(California Residents Add 6% Sales Tax» $ _ _ __
Grand Total $ _ _ __

Mail To:
NATIONAL SEMICONDUCTOR CORP., clo MIKE SMITH
P.O. BOX 60876, SUNNYVALE, CA. 94088
Po8tage will' be paid by Nallonal S.mlconductor Corp. Pi.... allow 4-8 _k8 for dellftry.

·(San Francisco Bay Area Residents Add 61f2% Sales Tax)

13-4

Section 14

Memory Oatabook
Referral Index
Virtually no data sheets have been included in this
handbook. National's Memory Databook contains a
complete collection of the specifications of your favorite
components. Be our guest and use this section to list
part numbers and Memory Databook page numbers for
future reference.

Referral Index to

National's Memory
Oatabook
This section provides a convenient place for you to make note of your favorite components from National's Memory
Databook.
Just jot down the part number and page for easy reference in the future. Space has been left for several editions of the
Memory Databook.
Part Number

Page in '17 Edition

Page in '78 Edition

MOS RAMs

Bipolar RAMs

CMOS RAMs

Charge Coupled Devices

MOS EPROMs

14·1

Edge Index

Referral Index to
National's Memory
Oatabook

Part Number

Page in '77 Edition

Page in 78 Edition

Edge Index

Bipolar PROMs

Bipolar ROMs

MOS ROMs

C
__ha_r_a_d_e_r_G_e_n_e_~_ro_~
____________~___________________~

Code Converters

--------------i(I]
. , .. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14-2

Referral Index to
National's Memory
Databook

Part Number

Page in '77 Edition

Page in '78 Edition

Edge Index

Shift Registers

-----------------1 r1
Interface

14-3

Notes

~National

~ Semiconductor

ERRATA

The following two diagrams represent improved methods for implementing the memory design beginning on page 2 - 9_ This
approach, implementing "RAS/only refresh," will result in significant power savings_ These diagrams can replace pages 2-14 and
2-16.
14800
74804

T1
REFI

TO/-~-'~-----------------------------'
BASE
ADDRESS

74800
tV3

74504

DEFAULT JUMPER STRAPPING

FOR 64k

7 CDOO

68000

74802

RAS4/

EXTERNAL
AORF/

RASJI

RAS2/

RAS1/

.,
~~H~i

10k

L.;>-.....-------------;;:::';7--,

Mp~~\4 C:::>-~-_cIl::>_.....__1>o-=::..._._--c:lh,~
E)(A\E:~~~:~:B~y

c::>----

~~ C:::>_~

E~TRW~~~~~~2~y

_ _cIl::>_.....__1>o-~~_r-6-----_r-=~-~-ol::I

c::>----

xxxx
xxxx +-~-'--6+_+_H_++_I
2.A xxxx ....-e--'--.....+-H-++-i
l,B xxxx +-~-'---....H_++_I

0,8

1,9

4,[

5,0

.,
Ik

xxx x +-~-'-----~----o[>--I
EXTERNAL AOR121

> eLK

D--r.

ern

A~r!~i L';>~----o[>--I
EXTERNAL ADR11/

c::>----

A~f!~~ r==>~----O[>--I
EXTERNAL AOR101

A~r_lt4
EXTERNAL ADAUI

D-----

STii

-,-xx-x""x:;;.-_.....

8XXXX ..

c::>-D-----

TVPICAll Y DONE DURING INSTRUCTION

OP-CODE DECODING IN CPU

Memory Select Logic

2-14

)06 ~ O()O) 00))

) )!)!)

-~
Q

0 _ .... M..,.

l' i! ~ iC ~ ~

"
~
"

+
-4+ +"
~0

~~
:::

r-t"

eL·

~-4-

eL,

<=> _

0:> _
...... ,.., "" ' " ' "
a
oo
cocc
<:(<(
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