1978_Series_8000_Microprocessor_Family_Handbook 1978 Series 8000 Microprocessor Family Handbook
User Manual: 1978_Series_8000_Microprocessor_Family_Handbook
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SERIES 8000
MICROPROCESSOR
FAMILY
HANDBOOK
NATIONAL
SEM ICON DUCTOR
Edge Index
~National
~ Semiconductor
Table of Contents
Introduction
The MICROBUS
The Series 8000 Microprocessor Family CPU Group
Designing Series 8000 Microprocessor Family Systems
Memory Components
MAXI-ROMs
Input/Output Components
Peripheral Control Components
Communications Components
Development Support
Programming
MICROBUS Electrical Specifications
Series 8000 Microprocessor Family Design Example
Additional Information Sources
Data Sheets
APPENDICES
CPU Group
DATA
SHEETS
Digital 110 Components
Peripheral Control Components
Communications Components
National does not assume any responsibility for use of any circuitry described, no circuit patent Licenses are
implied, and National reserves the right, at any lime without notice, to change said Circuitry.
© 1978 National Semiconductor Corp.
.1 .•
,
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~National
Preface
~ Semiconductor
This handbook replaces the N8080 System Design Manual. The Series 8000 Microprocessor Family encompasses not only the INS8080A, but also many peripheral control components as well. The title change
reflects this increased emphasis on peripherals. This handbook provides design information pertaining to
the National Semiconductor Series 8000 Microprocessor Family . The material contained in this handbook is
presented at a level-of-detail 'sufficient for use in the design and development of microprocessor systems
using the proven INS8080A CPU and support components. The material is up-to-date at the time of publication and is subject to change without notice.
Copies of this publication and other National Semiconductor publications may be obtained from the
National Semiconductor sales office or distributor serving your locality.
Available data sheets are included in appendix D.
Related National Semiconductor Publications:
•
•
•
•
•
•
•
•
•
•
National's 8080A Microprocessor Family Quick Reference
Pace Resident Macro Assemblers Manual (for UDS - ba:sed8080 cross assembler)
Universal Development System Users Manual
Universal Development System Editor Users Manual
Universal Development System PROM Programmer Users Manual
LLL Basic Interpreter Users Manual
Microprocessor Family Product Guide
National's Spectrum of IC Components for Terminals
Microprocessor System Design Training
Microprocessor Applications in Business, Science and Industry
iii
Data Sheet Index
The Series 8000 Microprocessor Family Data Sheets availabl.e at time of publication are listed below and
included in. appendix D in the order shown (for memory data sheets refer to National's Memory
Databook):
0.1
INS8080A
INS8224
I NS8228/8238
0.2
TRI-STATE® 8-Bit Bus Driver 0000000000000000000000000000000000000000000 D-25
TRI-STATE 8-Bit Bus Driver (Inverting) 0000 000000000000000000000000000000 D-25
8-Bit Bidirectional Bus Driver 0000000000000000000000000000000000000000000 D-29
8-Bit I/O Port 0000000000000000000000000000000000000000000000000000000000 D-35
4-Bit Bidirectional Bus Driver 000 0000000000000000000000 0000000000 00or: 0000 D-43
4-Bit Bidirectional Bus Driver
(Inverting) 0000000000000000000000000000000000000000000000000000 00000; 000 D-43
Programmable Peripheral Interface 00000000000000000000000000000000000000 D-47
INS8255
PERIPHERAL CONTROL COMPONENTS
DP8350
INS1771-1
INS8253
INS8254
INS8257
INS8259
INS8298E*
0.4
8-Bit.Microprocessor 0000000 '00000000000000000000000000000000000000000000 D- 3
Clock Generator and Driver 000000000000000000000000000000000000000000000 D-13
System Controller and Bus Driver 000000000000000000000000000000000000000 D-19
DIGITAL I/O COMPONENTS
INS8202
INS8203
INS8208
INS8212
INS8216
INS8226
0.3
Page
CPU GROUP
Series Programmable CRT Controller 00 00. 0000000 0000000000000; 0000000000 D-59
Floppy Disk Formatter/Controller 0000000000000000000000000000000000000000 D-73
Programmable Timer 00; 000000000000000000000 000000000000000000• 00000000 D-91
Programmable 16-Bit Addressable
Peripheral Interface 000000000000 000000000000000000000000000000000000000 0 D-101
Programmable DMA Controller 00 0. 000000. 000000000000000000000000 000000 D-115
Programmable Interrupt Controller 0000000000000000000000000.0000000000. D-127
LLL BASIC Interpreter 0000000000000000.0.0000. 0000000000000000.0000000. D-139
COMMUNICATIONS COMPONENTS
INS1671
INS8250
INS8251
*NOTE:
ASTRO Communications Interface 00000000000000000000000.000000000000. D-145
Asynchronous Communications Element (ACE) 00000000000.0000000000.00 D-157
Programmable Communications Interface 0000000. 000000000000000000000.0-173
For the following devices, contact National's Microprocessor Marketing regarding
availability of devices and data sheets:.
INS9298E
INS8316
INS8332
INS8364
LLL BASIC Interpreter
(same as MM52116) 16K bit (2K x 8) ROM
(same as MM52132) 32K bit (4K x 8) ROM
(same as MM52164) 64K bit (8K x 8) ROM
iv
~National
~
Table of Contents
Semiconductor
Chapter 1 INTRODUCTION
1.1 GENERAL DESCRiPTION ........................................................................ 1·1
1.2 HANDBOOK ORGANiZATION .................................................................... 1·3
1.2.1 Introduction ................................................................................... 1·3
1.2.2 The MiCROBUS ............................................................................... 1·3
1.2.3 The Series SOOO Microprocessor Family CPU Group .............................................. 1·3
1.2.4 Designing Series SOOO Microprocessor Family Systems .......................................... 1·3
1.2.5 Memory Components .......................................................................... 1·3
1.2.6 MAXI·ROMs ................................................................................... 1·4
1.2.7 Input/Output Components .. : ........................................... , ...................... 1·4
1.2.S Peripheral Control Components ....... " ...........•........................................... 1·4
1.2.9 Communications Components ................................................................. 1·4
1.2.10 Development Support ..................'".. " ........................................... , ........ 1·4
1.2.11 Programming ......... " .............. " ............................. " ......................... 1·4
1.2.12 Appendices ...... " ............ " ................................... "." ........ " ............... 1·4
A MICROBUS Electrical Specifications
B Series SOOO Microprocessor Family Design Example
C Additional Information Sources
D Data Sheets
Chapter 2 THE MICROBUS
2.1 INTRODUCTION ......................................... " ...................................... 2·1
2.2 GENERAL DESCRIPTION ............................................... , ........................ 2·1
2.2.1 Basic MICROBUS Interface .........................................................•.......... 2· 1
2.2.1.1 Data Bus (D7·DO) ............................................................................. 2· 1
2.2.1.2 Chip Select (CS) .............................................................................."2·3
2.2.1.3 Read Strobe (RD) ............................................................................. 2·3
2.2.1.4 Write Strobe(WR) ............................................................................ 2·3
2.2.1.5 Reset (RESET) ............................................................................... 2·3
2.2.1.6 Ground (GNDJ ................................................................................ 2·3
2.2.2 Addressing Techniques .................................... ".................................... 2·3
2.2.2.1 Input Case ................................................................................... 2·3
2.2.2.2 Address/Chip Select Relationship ............................................................. 2·4
2.2.2.3 Bidirectional Addresses ...... " .. , ......... '" ............................................... 2·4
2.2.3 Interrupt Convention ............... , ........................................................... 2·4
2.2.4 Direct Memory Access (DMA) Transfers ...................................................... .'... 2'4
2.2.5 Ready Signal .................................................................................. 2·5
2.2.6 The Basic Interface Model ...................................................................... 2·5
Chapter 3 THE SERIES 8000 MICROPROCESSOR FAMILY CPU GROUP
3.1 INTRODUCTION ................................................................................ 3·1
3.2 INSSOSOA MICROPROCESSOR ...............................................•.................. 3·2
3.2.1 Architecture of the INSSOSOA ................................................................... 3·2
3.2.1.1 Register Array and Address Logic ............................................................. 3·2
3.2.1.2 ALU and Registers ........................................................................... 3·2
3.2.1.3 Instruction Register and Decoder .............. : ......................... , .................... 3·6
3.2.1.4 Timing and Control Unit ...................................................................... 3·6
3.2.1.5 Data Bus Buffer/Latch ........................................................................ 3·6
3.2.2 Operating Cycle ............................................................................... 3·6
3.2.2.1 Instruction Cycle and Related Timing ......................................................... 3·6
3.2.2.2 State Transition Sequence ................................................. " ................. 3·7
v
Table of Conte.nts (qontiriue~t
3.2.3 Data and Instruction Representation ............................................................ 3·9
3.2A Status Information ....................................................... , ...................... 3·9
3.2.5 Addressing Capabilities . .'..........................................................•........... 3·9
3.2.5.1 Immediate Addressing ...................................................................... 3·13
3.2.5.2 Direct Addressing ........................................•................................. 3·13
3.2.5.3 Register Addressing ....... -..................•.............................. : ....... , ....... 3·13'
3.2.5.4 Register Indirect Addressing .................... ~ ................................•.......... 3·13
3.2.6 Input/Output Operation and Control ...................................................... '" .. 3·13
3.2.6.1 Data Input Operations ....................................... : ....•........................... 3·13
3.2.6.2 Data Output Operations ..................................................................... 3;14
3.2.7 Interrupts ...................... : ..........................•............... : ................... 3·14
3.2.8 Ho.,d Oper~tions ............ " ......................... '.' .....................•................. 3·16
3.2:9 Microprocessor Halt .......................•... '................... : ......... : ......... ·........ 3·17
3.2.10 Initialization .................................................................................. 3·17
3.3 I NS8224 CLPCK GENERATOR AND DRiVER ................ : .................................... 3·17
3.4 INS822818238 SYSTEM CONTROLLER AND BUS DRIVER. '.' ...................................... 3·21
3.5 CPU CHIP SET ............................................ .' ..................................... 3·22
3.5.1 DM8131 6·Bit Unified Bus Comparator .... '.......................................... , .......... 3·22
3.5.2INS82[S050ne·of·Eight Binary Decoder ....................................................... 3·22
3.5.3INS8257 ProgrammableDMA Controller ........................................................ 3·24
3.5.4 INS8259 Programmable Interrupt Controller .............. , ............ ' ......................... 3·24
Chapter 4 DESIGNING SERIES 8000 MICROPROCESSOR FAMILY SYSTEMS
4.1 INTRODUCTION ..................................... '........................................... 4·1
4.2 CPU GROUP DESIGN ............................................................................ 4·1
4.2.1 Clock Generator and Driver Design .............................................................. 4·1
4.2.2 System Controller and Bus Driver Design ................................................ , ....... 4·1
4.3 ADDRESSING CONSIDERATIONS AND TECHNIQUES ............................................ 4·3
4.4 INTERFACING TO MEMORy ......... , ... ,' ......................................~ ................. 4·6
4:5 DYNAMIC MEMORy ....... , ..................................................................... 4·8
4.5.1 Introduction ........................................................................ : .. : ........ 4-8
4.5.2 RAM Chip Character'istics .......................................................... ; ........... 4·8
4.5.3 Memory Subsystem Design Considerations ........ : ............................................ 4·9
4.5.4 Summary .................................................................................... 4·11
4.6 INTERFACING TO INPUT/OUTPUT DEVICES .............................. ; ...................... 4·11
4.6.1 Input/Output Addressing ...................... : ............................................... 4·12
".6;2 Interfacing 8·Bit Peripherals ................ ; ........................ '" ....................... 4·14
. 4.6.3 Interfacing Serial Devices .......................... , .......................................... 4·14
4.7 EXPANDING INTERRUPTS ........................................ '............................... 4·15
4.8 USE OF INS8080A SUPPORT CHiPS ........................ '" .......... : '" ...... .- ............. 4·15
Chapter 5 MEMORY COMPONENTS
5.1 GENERAL DESCRIPTION ............................ " ......................... ; ............... : 5·1
5.2 ADDRESSING CONSIDERATIONS ............................................................... 5·1
5.3 INTERFACING TO MEMORy ..... ; ........................................ ,' ...................... 5·2
5.4 DYNAMIC MEMORy ............................................................,.................. 5.5
5.5 INS8154 128-by·8 BitRAM 110 .................................................................... 5·5
5.6 OTHER MEMORY COMPONENTS (DATA SHEETS IN APPENDIX D) ............................. ; ... 5·5
RAM
STATIC
1K
,
5.6.1
INS8101A·41K (256x4) Static RAM With Separate 1(0 ............ '............................. 5~5 .
5.6.2
INS8111A·4 1 K (256x4) RAM With Common 110 ........................•... : ... ; .... : ....... . 5-t
5.6.3
INS8102A 1K (1024x1) Static RAM .......... , ................ ;.; ........................... 5·10
4K
'
MM2114 4K (1024x4) Static RAM ..................... : .................................... 5·12
5.6.4
J,
vi
Table of Contents (Continued)
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
MM5257 4K (4096x1) Static RAM .......................................................... 5·14
DYNAMIC
4K
MM5281 4K (4096x1) Dynamic RAM ....................................................... 5·17
16K
.
MM5290 16K (16,384x1) Dynamic RAM .................................................... 5·18
EPROM
MM1702A (256x8) EPROM ............................................................... ~ 5·23
MM4204/MM5204 4K (512x8) EPROM ...................................................... 5-25
INS8704 4K (512x8) EPROM .............................................................. 5-29
I NS8708A 8K (1024x8) EPROM ............................................................ 5-32
ROM
M M4242/M M5242 8K (1024x8) ROM ....................................................... 5-35
INS8316A/E 16K (2048x8) ROM ............................................................ 5-37
INS8332E/MM52132 MAXI-ROM 32,768 Bit Read Only Memory (2708 Compatible)., .......... 5-39
INS8364E/MM53164 MAXI-ROM 65,536 Bit Read Only Memory .... : ......................... 5-40
(Also Available as 8298, See Chapter6, MAXI-ROMs)
Chapter 6 MAXI-ROMs
6.1 GENERAL DESCRiPTION ...............................................................·.......... 6-1
6.2 INTERFACING TO MEMORy ..................................................................... 6-1
6.3 UNPROGRAMMED MAXI-ROMs ............... : .................................................. 6-1
6.4 INS8298E'LLL BASIC INTERPRETER ........................................ , .................... 6-1
Operation
System Configuration
Chapter 7 INPUT/OUTPUT COMPONENTS
7.1 GENERAL DESCRiPTION ...........................' ............................................· .. 7-1
7.2 INTERFACING I/O COMPONENTS ............................................................... 7-1
7.3 INS8212 8-BIT INPUT/OUTPUT PORT ............................................................. 7-5
7.4 I NS8202/1 NS8203TRI-STATE OCTAL BUFFERS .................... ~ .......•....................... 7-6
7.5 I NS8208B 8-BIT BIDIRECTIONAL BUS DRIVER .................................................... 7-7
7.6 INS8216/INS8226 4-BIT BIDIRECTIONAL BUS DRiVER ........................................... 7-10
Chapter 8 PERIPHERAL CONTROL COMPONENTS
8.1 GENERAL DESCRIPTION .......... : ........................................ : ..................... 8-1
8.2 INTERFACING THE PERIPHERAL CONTROL COMPONENTS ...................................... 8-1
8.3 KEYBOARD ENCODERSIDISPLAY CONTROLLERS ............... : ................. ; ............. 8~1
8.3.1 I NS8244 90-Key Keyboard Encoder .............................................................. 8-2
8.3.2INS8245I1NS8246 Keyboard Encoders ................................................. ; ......... 8-3
8.3.3 INS824711NS8248 Display Controller ............................................•............... 8-4
8.4 PROGRAMMABLE INTERVAL TIMER (INS8253) ................................................... 8-5
8.5 FLOPPY DISC FORMATTER/CONTROLLER (INS1771·1) ........................................... 8·6
8.6 PROGRAMMABLE CRT CONTROLLER (DP8350) ................................................. 8-12
8.7 CHARACTER GENERATOR (I NS8285) ...................................................... : .... 8·14
8.8 CMOS 8-BIT A/D CONVERTER (I NS8292) ......................................................... 8-15
8.93·3/4 DIGIT DIGITAL VOLTMETER (INS8294) (MICROPROCESSOR COMPATIBLE) ................... 8-16
Chapter 9 COMMUNICATIONS COMPONENTS
9.1 GENERAL DESCRiPTION ........................................................................ 9-1
9.2 INTERFACING THE COMMUNICATIONS COMPONENTS .......................................... 9-1
9.31NS8250 ASYNCHRONOUS COMMUNICATIONS ELEMENT (ACE) .................................. 9-2
9.4 INS8251 PROGRAMMABLE COMMUNICATIONS INTERFACE .... : ................................ 9·3
9.5 INS1671 ASYNCHRONOUS/SYNCHRONOUS TRANSMITTER/RECEIVER ............ , .............. 9-4
vii
Table of Contents (Continued)
Chapter 10 DEVELOPMENT SUPPORT
10.1 GENERAL DESCRiPTION ...................................................................... 10-1
10.2 UNIVERSAL DEVELOPMENT SYSTEM (UDS1) .................................................. 10-1
10.2.1 Hardware Support.; ......................................................................... 10-3
10.2.1.1 Dual Diskette Drives ....................................................................... 10-3
10.2.1.2Disk/CRT Interface Card .................................................................... 10-3
10.2.1.3 Universal Development System .......... ; ...................... , ........................... 10-3
10.2.1.4 Peripherals ............................................................................ " .. 10-3
10.2.2 Software Support ............................................................................ 10-3
10.2.2.1 Monitor System (MONITOR) ........... ; .................................................... 10-5
10.2.2.2 File Input/Output Subsystem (FIOSYS) ...................................................... 10-5
10.2.2.3 File Manager Program (PACFM) .................... , ............ '" ........ , ................ 10-5
10.2.2.4 Supporting System Software ............................................................... 10-5
10.2.2.5 PACE 12K Resident Assembler (PAC 12ASM) ................................................ 10-5
10.2.2.6 Cross Assemblers for B060, B070, and BOBO .... ........ , ..................................... 10-5
10.2.2.7 UDS1 Editor (EDITOR) ...................................................................... 10-5
10.2.2.B Linkage Editor(LlNKEDiT) .................................................................. 10-5
10.2.2.9 Diskette Diagnostic Program (PFDDIA) ...................................................... 10-5
10.2.2.10 UDS1 Utility Programs ................................................................... 10-5
10.3 INSBOBOA CROSS ASSEMBLER ................................................................ 10-5
10.4 PROM PROGRAMMING ... : ............................ , ....... , .............................. 10-8
10.4.1 UDS1 PROM Programmer (Peripheral~ ......................................................... 10-B
10.4:2 UDS1 Serial Link Card .................... , ................................................. 10-'0
10.5 SERIES/SO FAMILY INCLUDING UNIVERSAL PROTOTYPE BOARD (BLC 905) ............... , ... 10-10
10.5.1 Series/80 System Design Aids ............................................................... 10-10
10.5.2 Board-Level Computers ...................................................................... 10-10
10.5.3 OEM Rack Mountable Computers ........................................................... 10-10
10.5.4 Memory Boards ............................................................................ 10-10
10.5.5InputlOutput and'Memory Expansion Boards ............................................•.... 10-10
10.5.6 BLC 604 System Chassis and BLC 614 Expansion Board Cage ................................. 10-10
10.5.7 RMC 660 System Chassis ................................................................... 10-11
10.5.S BLC 635 Power Supply .......................................... ; ........................... 10-11
10.5.9 BLC 6.65 Heavy Duty Power Supply .......................................................... 10-11
'10.6 PUBLICATIONS ............................................................................... 10-11
10.7 TRAINING ................................................................ : .................. 10-11
10.S NATIONAL'S MICROPROCESSOR l,JSERS GROUP ............................................. 10-12
10.9 Technical Support Programs ................................... ~ •.....•........................ 10-13
10.10 MICRO+ PROGRAM (Quality Control and Testing Process) .....•............................. 10-13
Chapter 11 PROGRAMMING
11.1 I NSBOBOA INSTRUCTION SET .................................................................. 11-1
11.1.1 Instruction and Data Formats ................................................................ 11·1
11.1.2 Addressing Modes ................".......................................................... 11-1
11.1.3 Condition Flags ............................................................................. 11-2
11.1.4 Presentation Format ......................................................................... 11-2
11.1.5 Data Transfer Group ......................................................................... 11-2
11.1.6 Arithmetic Group ............................................................................ 11-7
11.1.7 Logical Group .............................................................................. 11-10
11.1.S Branch Group .............................................................................. 11-13
APPENDICES
Appendix; A MICROBUS ELECTRICAL SPECIFICATIONS
A.1 GENERAL DESCRiPTION ........................................................ ·............... A-1
A.2 LOGICAL AND ELECTRICAL STATE RELATIONSHiPS ............................................ A-1
viii
Appendices (Continued)
A.3 DRIVER REQUIREMENTS ....................................................................... A·2
A.4 RECEIVER REQUIREMENTS .................................................................... A·2
A.4.1 Receiver Specifications, Standard ..................... ,........... , ............................ A·2
A.5 BIDIRECTIONAL SIGNALS ...................................................................... A·2
A.6 READ CYCLE TIMING ...................................... , ..................... , ............... A·2
A.7 WRITE CYCLE TIMING ........................... '" ................. , ..................... '..... A·5
A.B MICROBUS AND DEVICES ...................................................................... A·6
Appendix B SERIES 8000 MICROPROCESSOR FAMILY DESIGN EXAMPlE ............................ B·1
Appendix C ADDITIONAL INFORMATION SOURCES ............................................... ; .C·1
Appendix D DATA SHEETS
0.1. CPU GROUP ................. ; ........................ '......................................... 0·3
0.2 DIGITAL 1/0 COMPONENTS ................................................................... 0·25
0.3 PERIPHERAL CONTROL COMPONENTS ............................................. '" ....... 0·59
0.4 COMMUNICATIONS COMPONENTS ........................................................... 0·145
list of Illustrations
Figure
Title
Page
1·1 National Semiconductor Series BOOO Microprocessor Family Basic System Model (Example Using
INSBOBOA CPU Group) ........................................................................... 1·1
1·2 Series BOOO Microprocessor Family ............................................................... 1·2
2·1 Read Cycle· Fundamental Timing Relationships .................................................. 2·1
2·2 Write Cycle· Fundamental Timing Relationships .............. , ................................... 2·1
2·3 Interrupt Service . Interface Device Waveforms ... ~ ................................................ 2·4
2·4 Single Cycle DMA Transfer from an Interface Device to Memory ......................... '........ ',' . 2·5
2·5 Relationship of R'EADY toCS, WR, and RD ......................................................... 2·5
2-6 INSBOBOA S~ ~tem Model for tlfe Basic MICROBUS Interface ....................................... 2·6
2·7 INSBOBO Family CPU Group to MICROBUS Configuration ...................•...................... 2·7
2·B INSB060 System Model ................ ; ......................................................... 2·8
2·9 INS8070' Family System Model ..... ; .............................................. , ............. 2·B
3·1
3·2
3·3
3·4
3·5
3·6
3·7
CPU Architecture and Pinouts of INSBOBOA ., ..................................................... 3·3
Basic Instruction Cycle ........................................................ '...... : ........ '...-3·7
INSBOBOA CPU State Transition Flowchart ....................................................... . 3·B
Data Word Format ............................................................................... 3·9
Instruction Formats .................................. , ...................................... ' .. 3·10
I NSBOBOA Status Latch Circuit .................................................... , ...... : ...... 3·11
Data Input Operation Timing .......................................................... : ......... 3·14
3·B Data Output Operation Timing .................................................................. 3·15
3·9 Interrupt Timing .....................' ....................... , ................................... :3·15
3·10 Hold Operation Timing for MEMORY READ or INPUT Cycle .................................... , .3·16
3·11 Hold Operation Timing for MEMORY WRITE or OUTPUT Cycle ................................... 3·17
,3·12 Halt Timing ............................. , ........... , ......................................... 3·1B
3·13 Halt Sequence Flowchart .................................................................... " 3·1B
3·14 Relationship Between HOLD and INT in the HALT State ................................. , ....... 3·19
3·15 Initialization Timing ................................. , .................................... ~' ..... 3·19
3·16 I NSB224 Functional Block Diagram.'.................................................... , ....... 3·20
3·17 Relative Timing of I NSB224 Clock Output Waveforms ..................... '....................... 3·21
3·18 INSB224 to I NS8080A Interconnection .......................................................... 3·22
3·19 INS822811NS8238 Functional Block Diagram .................................................... 3·23
3·20 INSB22BIINSB238 to INSBOBOA Interconnection .. : .............................................. 3·24
3·21 Preferred Method of CPU Group Implementation ...................... , ......................... 3·25
ix
List of Illustrations (Continued)
3-22 DM8131 6-Bit Un.ified Bus Comparator ............................ , ........................... , .. 3-26
3-23 I NS82LS05 One-of-Eight Binary Decoder ........................................................ 3-26
3-24 INS8257 Programmable DMA Controller .......................... ; ............................. 3-27
3'251NS8259 Programmable Interrupt Controller ..................................................... 3-28
4-1 Preferred Method of CPU Group Implementation .................................................. 4-2
4-2 System Clock Generator and Driver Using Discrete Components ................................... 4-3
4-3 System Controller and Bus Driver Using Discrete Components ..................................... 4-4
4-4 Address Buffer Design Using INS8202 Devices ................. : .................................. 4-5
4-5 Mapping for Isolated Input/Output and Memory mapped Input/Output Techniques ................... 4-5
4-6 System Control Signals for Isolated Input/Output Addressing .............................. _....... 4·6
4-7 System Control Signals for Memory Mapped Input/Output Addressing .............................. 4-7
4-8 Typical Memory Interface ......................................' .................................. 4-7
4-9 Cell Comparison ................................................................................ 4-8
4-10 IDD Current Waveform ...............................•.......................................... 4-9
4-11 Damping Resistor Placement .................................................................. 4-10
4-12 Typical Input/Output Interface .............................. : .................................. 4:12
4-13 Example of Addressing INS8255 Devices Using Isolated Input/Output Technique and Linear Select. 4-13
4-14 Example of Addressing INS8255 Devices Using Memory Mapped Input/Output Technique and
Linear Select ................................................................................. 4-13
4-15 Addressing Format for INS8255 and INS8212 Devices ........................................... 4-14
4-16. Addressing Format for INS8251 Device ............ ,............................................. 4-15
4-171NS8259 Programmable Interrupt Controller ..................................................... 4-16
4-18 INS8259 Interrupt Expansion ................................................................... 4-17
5-1 Address Buffer Design Using INS8202 Devices .................................................... 5-1
5-2 Mapping for Isolated Input/Output arid Memory Mapped Input/Output Techniques ................... 5-2
5-3 System Control Signals for Isolated Input/Output Addressing ............................ " ........ 5-3
5-4 System Control Signals for Memory Mapped Input/Output Addressing ......... , .................... 5-3
5-5 Typical Memory Interface .......•.......................... , .......... ; .......................... 5-4
5,61NS8154 Block Diagram .................................................. : ....................... 5-6
5·7 INS8154 MICROBUS Connection .......................................... : ...................... 5-6
7-1 Typical InputlOutput Interface ........................................................... , ....... 7-2
7·2 Example of Addressing INS8255 Devices Using Isolated Input/Output Technique and Linear Select ... 7-3
7-3 Example Of Addressing INS8255 Devices USing Memory Mapped Input/Output Technique and Linear
Select .......................................................................................... 7-3
7-4 Addressing Format for INS8255 and INS8212 Devices ............................ ; ................. 7-4
7-5 Addressing Format for INS8251 Device ........................................................... 7-4
8-1 Interfacing the Peripheral Control Components ................................................... 8-1
8-2 INS8244 Internal Block Diagram .................................................................. 8-2
8-3 Typical Interrupt Driven Keyboard Interface ........................................................ 8-2
8-4 INS8246 Block Diagram ........................ : ................................................. 8-3
8-5 Typical MICROBUS Connection .................................................................. 8-3
8-6 INS8247 Internal Block Diagram ............................................... ; .................. 8-4
8-71NS8247 MICROBUS Interface .............•.................•.................................... 8-4
8-8 INS8253 .Internal Block Diagram .................................................................. 8-5
8-9 INS8253 MICROBUS Connection ............................................................ : ..... 8-5
8-10 Diskette Layout (Example) ............ ; ..............................................,........... 8-6
8-11 Read Timing ................•.................................................................. 8-7
8·12 Track Form",t (Diskette) ......................................................................... 8-8
8,~3 Interface to System Bus ......................................•.•............................... 8-9
8,14INS1771-1 Block Diagram .......................................................•.............. 8-10
8-15 Seek Command ... _..........................................•..........• ; ............. : ....... 8-11
10-1 Universal Development System (UDS1) ...................•.......................•... ~., ....... 10-1
10-2 UDS1 Block Diagram .......................................................................... 10-2
10-3 Top Internal View of Universal Development System .. _...........................•.............. 10-4
x
List of Illustrations (Continued)
10-4 Operational Sequence of the UDS1 Editor and Assemblers ....................................... 10-7
10-5 Universal Development System Configuration .................. " .............................. 10-9
11-1 Presentation Format .......................................................................... 11-3
A-1 Read Cycle Waveforms ......................................................................... A-3
A-2 Write Cycle Waveforms ......................................................................... A-5
B-1 Design Example (Basic Computer System) ....................................................... B-1
List of Tables
Table
Title
Page
2-1 Signal Lines (Referenced to the Interface Device) .................................................. 2-2
3-1 Input/Output Signal Descriptions ................................................................. 3-4
3-2 Status Information Distribution and Definition ................................................... 3-12
3-3 Status Bit Outputs for Each Type of Machine Cycle ............................................... 3-13
8-1 INS1771-1 Register Selection .................................................................... 8-9
8-2 Commands Summary ........................................................................... 8-11
10-1 Assembler Peripheral Options ................................................................. 10-6
11-1 Symbols and Notations ........................................................................ 11-3
11-28080 Instruction Summary .................................................................... 11-19
A-1 Class 1 Read Cycle Timing Specifications ........................................................ A-4
A-2 Class 1 Write Cycle Timing Specifications ........................................................ A-6
xi
r-o
MEMORY
~
Chapter 1
Introduction
INPUT10UTPUT
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MICROPROCESSOR
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* Trademark, National Semiconductor Corporation
-_.
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Introduction
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1.1 GENERAL DESCRIPTION
The National Semiconductor Series 8000
Microprocessor Family covers the broad
general-purpose- segment of microprocessor
applications (see figure 1-1 for INS8080A example).
Included in the Series 8000
M,icroprocessor Family are the proven
INS8080A CPU and components of proprietary
designs as well as a wide range of multiple
source devices.
The Series 8000
microprocessor family finds use in 8-bit
microprocessor system designs ranging from
complex controls to highly sophisticated communications applications. Some of the user
benefits are listed below:
•
•
•
•
•
•
Family approach to system design
Complete CPU group
Programmable input/output concepts
Multiple source availability
Complete line of support components
Total product support
Most components of the Series 8000 Microprocessor Family are shown in figure 1-2. (For a
more nearly complete list, see chapter 10
references and specific publications such as
National's Memory Oatabook). Components
are discussed by type (see 1.2). Representative
of the type of CPU that can be used with the
Series 8000 Microprocessor Family is the INS8080A, an 8-bit CPU chip that may be used interchangeably with the Intel 8080A. The Series
8000 Microprocessor Family can be used in
systems that range from a few family components to designs that utilize the extensive
capabilities available. The INS8080A falls between the cost-effective 8-bit INS8060 chip and
the highly versatile 16-bit INS8900 chip in
National Semiconductor's microprocessor
spectrum. Any of these three microprocessors
can be used with Series 8000 peripheral
components.
The designer can satisfy memory requirements
,-----------,
,
rl~3r
~GM~
I~
...
~.------
~
R~
~
L---",_-,~
t
OPTIONAL
:
:
ADDRESS
BUFFERS
INS8212
OR
1-______.,...,.:
I :
INS8080A
MICROPROCESSOR
INS8216
M,
~~~~E~L....::.""-'--"'-I~I""'"u, n.
~'
..-----,
I
~
~
RAMs
I
: ADDR ES$
I BUS (16)
C
L-_ _ _ _- '
R
I
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WAIT _ _
OMA REO_)
ROMs
',f----------1
~
INS 8224
CLOCK
RESET
GENERATOR ~
AND
READY
DRIVER
I---.
CHIP
SELECT
0
INTR
:
+-+
5
L-_ _ _ _- '
+l TM"
H~I+-I_ _ _ _"DA"T_A"BUiiiSoii(8")
DIGITAL 110
COMPONENTS
081N
ViR
INTA
"::::--I
INS8228llNS8238
. ._ _ _...O..
7-..
00-.t
A~~~~~O~~I~~R
L-_ _
SYSTEM
~
~
PERIPHERAL
CONTROL
COMPONENTS
,
I
CONTROL (6)
COMMUNICATIONS
COMPONENTS
'---_--' I
L ____________
J
Figure 1-1.
National Semiconductor Series 8000 Microprocessor Family
Basic System Model (Example using INS8080A CPU Group)
• Trademark, National Semiconductor Corporation
1-1
SERIES 8000
MICROPROCESSOR
I
I
i\:1
PART
'NUMBER
INS8101A·4
INS8102A
INS8111A·4
INS8154
INS8298E
INS8316A/E
INS8332E
INS8364/
8364E
INS8704
I NS8708A
MM1702A
MM2114
MM5204
MM5242
-MM5257
MM5281
MM5290
1'1
MICROBUS™
J fl
I rI
MEMORY
INPUT/OUTPUT
DESCRIPTION
256 x 4Static RAM with
Separate If0
1024 x 1 Static RAM
256 x 4 Static RAM with
Common I/O
128 x 8 Static RAM with
Common I/O
8080A LLL Basic Interpreter
2048 x 8 MOS Mask ROM
(2708 Compatible)
4096 x 8 MOS ROM
(2708 Compatible)
8192 x 8 MOS Mask ROM
(E has 2708 Compatibility)
512 x 8 EPROM
1024x8 EPROM
256x8EPROM
1024 x 4 Static RAM
512x8 EPROM
1024 x 8 ROM
4K x 1 Static RAM
4096 x 1 Dynamic RAM
16K Dynamic RAM
PART
NUMBER
INS8202
INS8203
INS82LS05
INS8208B
INS8212
INS8216
DESCRIPTION
Tri State 8 Bit Bus Driver
Tri State 8 Bit Bus Driver
(Inverting)
1 of 8 Binary Decoder
8 Bit Bidirectional 8us Driver
8 Bit I/O Port
4 Bit Bidirectional Bus
Driver
INS8226
INS8253
INS8255
INS8257
I NS8259
4 Bit Bidirectional Bus
Driver (Inverting)
Programmable Timer
Programmable Peripheral
Interface
Programmable DMA
Controller
Programmable Interrupt
Controller
PART
NUMBER
DP8350
INSI771·1
INS1791
INS8244
INS8245
I NS8246
INS8247
INS8248
I NS8254
INS8277
INS8285
I NS8292
INS8294
I r1
I rI '
PERIPHERAL
CONTROL
COMMUNICATIONS
DESCRIPTION
Series Programmable CRT Controller
PART
NUMBER
INS1671
Floppy Disk Controller
Dual Density Floppy Disk
Controller
90 Key Keyboard Encoder
16 Key Keyboard Encoder
20 Key Keyboard Encoder
4 Digit Display Controller
6 Digit Display Controller
Programmable 16 Bit Addressable
Peripheral Interface
Programmable CRT Controller
Character Generator
8 Bit AID Converter with
16 Channel Analog MUX
3'14 Digit DVM with Multiplexed
BCD Output
Figure 1-2. Series 8000 Microprocessor Family
I NS8250
INSB251
n
DESCRIPTION
ASTRO Communications
Interface
Asynchronous Communications
Element (ACE)
Programmable Communications
Interface
Development Support, covering how the
designer is aided, and then programming. Appendices are included next which give
reference data such as MICROBUS specifications, additional sources of information and
complete the manual with the available Data
Sheets for the devices referenced.
from the wide range of National Semiconductor's RAM, ROM, PROM, and MAXI-ROMTM*
components. IProgrammable input/output and
peripheral functions enable the system
designer to configure and adapt interface lines
to his own requirements. Data communications may be accomplished by using a variety of
Series 8000 Communications Peripherals.
1_2_1. Introduction
The Series 8000 Microprocessor Family is supported by industry standard design kits, easyto-use development systems, and a full complement of cross and resident
assemblers.
Various components and software also are
available to support the Series 8000
Microprocessor family from experimentation to
final production (see chapter 10, Development
Support).
Chapter 1, Introduction, gives a general view of
the Series 8000 Microprocessor Family and
discusses the plan of the Handbook. It identifies the key concepts that are used
throughout the Handbook such as the
MICROBUS, and discusses the relationship of
the various chapters to each other.
1.2.2 The MICROBUS
1.2 HANDBOOK ORGANIZATION
The MICROBUS chapter describes the use of
the system bus and its conventions. The bus
concept is developed, indicating bus usage for
various size systems, recognizing that most
systems will not need the entire MICROBUS
capability.
The major portions of the Series 8000
Microprocessor Family Handbook are as
follows:
•
•
•
•
•
•
•
•
•
•
•
•
Introduction
The MICROBUS
The Series 8000 Microprocessor Family
CPU Group
Designing Series 8000 Microprocessor
Family Systems
Memory Components
MAXI-ROMs
Input/Output Components
Peripheral Control Components
Communications Components
Development Support
Programming
Appendices
1.2_3 The Series 8000 Microprocessor Family
CPU Group
The discussion of the CPU Group includes as
an example, the INS8080A Microprocessor, the
INS8224 Clock Generator and Driver and the
INS8228/INS8238 System Controller and Bus
Driver. The architecture of the INS8080A is
discussed along with the operating cycle, data
Other key
and instruction representation.
topics such as addressing capabilities, Input/Output operation and control, and interrupts are examined in this chapter and then
referenced in following chapters. In particular
the next chapter on Designing Series 8000
Microprocessor Family Systems relies he.;tvily
on an understanding of the CPU Group as
discussed in this chapter.
The handbook takes the approach of introducing the system concept of the MICROBUS first,
since this is the System Bus used to interconnect the various Component Device Groups.An
example of a CPU group is discussed next to
form a base for discussing the various sizes of
systems that follow. With this base of information, the chapter on designing Series 8000
Microprocessor Family Systems is presented
next followed by detailed discussion of other
device types, so that the designer can pick the
chapters of interest that follow and skip the
rest. Chapters 5 and 6 discuss memory components including MAXI-ROMs, and their use in
storing large programs in ROM. Having covered
the various memory options, it is possible .to examine how Input/Output is included in the
system. This is treated in two chapters (7 and 8)
so that individual Input/Output Components
can be selected more easily.
1.2_4 DeSigning Series 8000 Microprocessor
Family Systems
The handbook is organized so that a designer
might start with this chapter and refer toeach
of the other chapters as needed, while considering the design requirements of the system
being designed for a particular application. For
example, a particular system might need powerful input/output capability and therefore
chapters 7 and 8 might be reviewed while con~idering approaches for the design of a system
with that capability.
1.2.5 Memory Components
The communications components allow data
transfer to remote locations, and are covered in
chapter 9. We next turn our attention to
* Trademark, National Semiconductor Corporation
The diversity of Memory options range from
small RAM to the mask programmable MAXIROM.
1-3
1.2.6 MAXI·ROMs
imagination gOing, and emphasize the range of
devices available, rather than give cook book
solutions to particular problems. (See appendix
C for .additional information sources.)
Mask programmable MAXI'ROMs may contain
complete programs. As an; example of the
possibilities, the 8298 LLL (Lawrence Livermore
Laboratory) BASIC interpreter for the INS8080A
is discussed. This program .resides in an INS·
8298E, (65,536 bit) static mask·programmable
ROM.
Various communications devices are covered
in this chapter.
1.2.7 Input/Output Components
1.2.10 Development Support
These devices receive a somewhat lighter
discussion than the Peripheral Control Com·
ponents because of their simplicity.
The
devices of a more complex nature (i.e.
Peripheral Control Components), are given a
more extensive treatment to make it easier for a
designer to feel comfortable in designing with
the devices. It is assumed that the designer
has considerable bacl(ground in the use of
similar I/O devices and other COmponent
Groups of concern in his deSign. The next two
chapters are companions to this one and are in·
tended to be used with it.
1.2.8 Peripheral'Control Components
The discussion of these devices is somewhat
grouped because of their typical use together,
although no rigid division is implied by chapter
divisionIS or order of discussion of devices. The
statement that the only limitation is the im·
agination of the designer applies perhaps
stronger with the I/O, than any other area of
design, for here is the interface capability to
other devices, equipment, and systems in the
outside world. The treatment in the two In·
put/Output chapters (7 and 8) and the com·
municationlSchapter (9), is intended to get the
1.2.9 Communication Components
This chapter identifies items of general sup·
port, such as the 8080 cross assembler, PROM
Programmer and the Universal Development
System (UDS), training ,and technical support.
(Also see appendixC for additional information
sources.)
1.2.11 Programming
In this chapter, programming topics are
covered from machine language through high
level languages. Reference is also made to
related programmable devices, such as Pro·
grammable Peripheral Control Components.
1.2.12 Appendices
In addition to general reference data, additional
information sources are identified in appendiX
C.
j
Available data sheets for the referenced
devices are grouped in Appendix D. Notice that
they are grouped by area of concern (i.e., CPU
group, Memory components, Digital I/O Com·
ponents, Peripheral Control Components,and
Communication Componentsl.
r"'r--
,......
.....-
MEMORY
Chapter 2
MICROBUS™
INPUT/OUTPUT
M
SERIES 8000
MICROPROCESSOR
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~
• Trademark, National Semiconductor Corporation
MICROBUS™
2.1 INTRODUCTION
MICROBUS, the National Semiconductor Stan·
dard for Microprocessor Interfaces, deals with
systems that use a·bit parallel means to
transfer digital data between MOS/ LSI
microprocessor CPUs and interfacing devices.
The interface system described herein allows
proximate components to communicate over a
unified bus system.
I
This standard applies to relatively small
systems representative of users' end products.
Typi'cally, these are systems where fewer than
ten integrated circuits are interconnected to a
common system bus, with buffering kept to a
minimum.
strobes and peripheral device (I/O) strobes.
Because it is actually the option of the system
designer whether he implements both sets of
strobes, only the generalized strobes are dis·
cussed in detail. The mnemonics to be used for
the memory strobes are MEMR and MEMW. The
mnemonics for peripheral strobes are IIOR and
IIOW. (Refer to Section 4.3 for discussion of
mapping peripherals in memory vs. I/O address·
ing space.)
GS
-J/
RD - - - - - - - - \ ' - -_ _
Application of this standard will provide the
user with a broad line of support devices which
can be effectively "plugged" into systems
without regard to complex timing or electrical
analysis, thereby making interfacing easy for
the system designer.
DoOD
.--~
70~-----
---
2.2 GENERAL DESCRIPTION
This standard applies to interface systems
used to interconnect electronic devices with
MOS/ LSI microprocessor systems. Devices
should have the following characteristics:
•
•
•
Data exchanged among the interconnec·
ting devices is digital (as distinct from
analog).
Total transmission path among intercon·
necting devices is electrically short. That
is, transmission line considerations are
negligible.
Number of devices interconnected on the
system bus is small (ten or fewer).
This standard defines the most general system.
The large majority of interfacing devices
employ only a subset of the signals. Signal
Lines are described in table 2·1. For details con·
tact National Semiconductor.
Figure 2·1.
DATA BUS DRIVEN
BY THE INTERFACE
DEVICE IN THIS
INTERVAL
4-
Read Cycle· Fundamental Timing
Relationships
r-
CS~
\\......_ _ _ _--'1
WR------~\~
__~/
x==
I
1
___---'x
DATA VALID
DATA BUS
PROVIDES VALID
DATA TO THE
INTERFACE DEVICE
IN TillS INTERVAL
Figure 2·2. Write Cycle· Fundamental Timing
Relationships
.
2.2.1 Basic MICROBUS Interface
The following paragraphs define the Basic
MICROBUS Interface S'ignals. Figures 2·1 and
2·2 illustrate the fundamental read and write cy·
cle timing.
The Basic MICROBUS Interface defines
generalized read and write strobes· RD and WR.
In actual systems there may be both memory
'Trademark, National Semiconductor Corporation
2.2.1.1 Data Bus (07-00)
These signal lines carry bit·parallel data infor·
mation, typically, implemented as eight TRISTATE input/output lines. In such a typical application status, control and data information is
transferred. In most applications, eight bits are
implemented.
2·1
)
,-<"
j
Table 2-t SIGNAL LINES (Referenced to the Interface Device)
FUNCTION
MNEMONIC
~UMBER
1:!f5
Data
07-00
8
Bidirectional
Genera:Jjzed Read Strobe
RD
Input
Generalized Write Strobe
WR
Input
Memory Read Strobe
MEMR
Input
Memory Write Strobe
MEMW
Inpuf
110 Read Strobe
IIOR'
Input
110 Write Strobe
1I0W
Input
Device (Chip) Select
CS
Inpu~
Reset
RESET
Input
Ground
GND
Power Supply
Address
A15-AO
Interrupt
16
Input
.INTR
Output
DMA Request
ORO
Output
DMA Acknowledge
DACK
Input
TC
input
Ready
READY
O.C. Output
Early Write Strobe
EWR
InPlit
Data Buffer Enable
DBE
Output
Data Buffer Out
DBO
Output
Address Buffer enable
ABE
Address Buffer Out
ABO
Terminal
C~unt
2-2
1~
Output
Output
In simpler, dellicated, interface applications,
these signal lines maybe unidirectional. Ex·
amples are, simple interface latches, keyboard
controllers, and display controllers.
reset, it should restore the head to track zero. A
mag tape device, however, should terminate
tape movement operations.
Each electro·
mechanical device must be considered
separately when determining what effect the
RESET input will have on its controlling states.
2.2.1.2 Chip Select (CS)
Whenever the RESET signal is applied, the interface device shall place its data bus and other
TRI·STATE system outputs into the high impedance state.
The device designer may
assume that the RESET input will be low for a
minimum of 100 /Lsec.
This input pin enables communication between
the interface device and the system. This
signal is a combinational active low state in·
dicator that the device is being addressed by
the system. The user/designer must accom·
modate transients on this signal during
changes in the address bus. Therefore, this
signal should be used as a combinational
enable function, i.e., level sensitive applica·
tions are O.K., edge sensitive are not.
Many MOS/LSI interface devices require an active high voltage RESET signal while most ex·
isting TTL devices use RESET. For this reason,
most systems will require both RESET and
RESET. Either reset signal is acceptable for
this standard. Future interface devices should
standardize on the RESET convention.
2.2.1.6 Ground (GND)
In a data transfer, the CS signal will envelope
the RD or WR signals.
2.2.1.3 Read Strobe (RD)
This signal provides Ov reference t6 the inter·
face device. All signals and voltages are ref·
erenced to GND.
A low state on this input pin enables the inter·
face device to send information to the system
via the data bus. This signal is the indicator to
the interface device, to provide data to the
MICROBUS whenever CS is also active (low).
Otherwise, the interface device data bus drivers
should be in the high impedance state.
2.2.2 Addressing Techniques
The first extension of complexity beyond the
Basic MICROBUS is the addition of addressing
capability. The addition of address signals to
the interface device provides a binary encoded
selection of device internal registers or memory
locations.
2.2.1.4 Write Strobe (WR)
A low on th~nput signal in combination with a
low on the CS input signal enables the transfer
of information from the MICROBUS to the interface device.
2.2.2.1 Input Case
Thes~JnputJilllnals,in
conjunction with the CS
and RD or WR inputs, control the selection of
data, control, or status information transfer be·
tween, the MICROBUS and the interfacing
device.
'
The data bus (DrDo) will be valid to the inter·
face device before the high to low transition of·
WR and will remain valid until after the low to'
high transition of WR.
A common example is the 8255 Programmable
Peripheral Interface. This device has .. two
address inputs (A1 and AO)' . Internal to the
device, there are three data ports - A, B, and C; a
status register; and a control register. The A, B,
and C data ports may be read or written and are
~ecifi~by the address inputs during the time
RD or WR is low. In this case, port A, B, or Cis
specified when the A1AO inputs are 00, 01:or 10
respectively. When the address inputs are 1t
and a read operation is performed, the 8255 pro·
vides.information from its status register to the
data bus. When the address inputs are 11 and 'a
write is performed, the 8255 command register
is loaded from the data bus.
.
Designers of new interface 'devices should not
rely upon data being valid on the leading edge
of the write strobe because some existing and
future microprocessors do not provide data
valid at this time.
2.2.1.5' Reset (RESEn
The RESET signal is supplied by the system to
all interfacing devices at power on time and
typically by a manual (pushbutton) operation.
Devices are'to be reset whenever the RESET
signal is in the low voltage state.
In this example, a write only and a read only
register share a common address. This is not a
preferred practice as it adds complexity to the
controlling software. Data written to write only
control or data registers must often be duplicated in RAM when independent bit operations
are to be performed on the register.
The reset signal should place all interfacing
devices into a known initial state. It is desirable
that every sequential storage element within an
interface device be initialized by this signal. For
example, when a floppy disk interface device is
2·3
2.2.2.2
signal with an interrupt output (INTR). The
START CONVERSION .input is replaced or
supplemented by a programmed I/O operation.
Address/Chip Select
Relationship
It is implied that the chip select signal, CS
(2.2.2) isa combinationalfunctionof the~system
address bus. Because of this relationship, transitions of CS are delayed from change:;; in the
addre:;;s bus. The timing specifications for the
C$ signal are derived from the typical implementation presented in appendix B.
DEVICE ACKNOWLEDGES
SERVICE COMPLETE
I
~
.....
DEVICE
INTR
~
2.2.2.3 Bidirectional Addresses·
In the future, interface devices will provide their
own address information during direct memory
access (OMA) transfers. In this class of interface device the address lines are outputs during OMA transfers and inputs during conven·
tional, programmed 110 transfers as described
in section· 4.3. Special control signals are
required to control external TRI-STATE address
buffers and latches needed for this type of
device. These sigf)als control the direction of
data through the TRI-ST ATE buffer and the TRIST ATE enable. They are named Address Buffer
Out (ABO) and Address Buffer Enable (ABE)
respectively.
cs
~,
SERVICE
REQUEST
/
)(
~
RD.WR
v
Figure 2-3. Interrupt Service - Interface Device
Waveforms
In the simplest case, the INTR output is set
high at END OF CONVERSION. The systemresponds to the interrupt by reading the AID output buffer ;.vhich sets the INTR low and simultaneously starts a new conversion. The 'reader
will notice that the START CONVERSION input
is not required. In practice it is desirable to
implement control and status registers to allow
the system to select how the interrupt and start
conversion systems will function.
2.2.3 Interrupt Convention
Interface devices often provide interrupts to the
system to request the initiation or indicate the
completion of a task.
In the standard bus environment, interface
devices may provide one or more interrupt
signals. In the singular case, this signal is
named INTR.lt is an active high signal that is
asserted in the high voltage state to request a
Program interruption.
In an 8080 system, the interrupt feature may be
implemented by adding an 8259. The interrupt
controller is added to the CPU group to provide
the MICROBUS interrupt inputs for interfacing
devices.
Once asserted high by the interface device lhe
interrupt signal must remain high unti.1 it is'serviced by the system. Typically, interrupts may
be serviced by the system taking action to
either identify or service the condition which
caused the interrupt. In all cases, this must be
implemented by a programmed 1/0 transfer between the system and the device. The particular
protocol for removal of the interrupt is depen·
dent upon the-type of device producing it.
2.2.4 Direct Memory Access (DMA) Transfers
Systems that provide DMA capability interface
to devices via two dedicated and one common
signal. Each DMA device controls its own OMA
request signal (ORO). The system responds to
ORO with a dedicated OMA acknowledge signal
(OACK). The third special signal forDMA is .the
terminal Gount (TC) indicator provided by the
system to the device to indicate that the present OMA cycle should be the last cycle for this
data block.
The interrupt signal may be asserted asynchronouslywith respect to other signals in the
system. See figure 2-3. It must be- removed~
th€ completion of the appropriate RO or WR
strobe when the CS and address inputs are
.
active.
An example of implementation is an AID converter designed to interface to the MICROBUS.
The device designer who wishes to make his
AID converter compatible with the MIC'ROBUS
will modify the classical control and timing
logic to replace the END OF CONVERSION
Figure 2-4 illustrates a typical OMA cycle in
which the device is providing data to the
In this type of DMA channel, a
system.
simultaneous read peripheral (lIOR) and write
memory operation (MEMR) is performed.
2-4
nDn
Typically, use of the READY signal requires
complex electrical design and timing analysis.
r'
~
\'--'''---J
Figure 2-5 illustrates timing relationships for
the READY signal. In this example, the system
initiates a read or write cycle to the device by
activating its RD or WR and CS inputs. If the interface device cannot respond within the
system access time requirements, it may assert
the READY signal low indefinitely until it has
had time to stabilize the data bus in a read
operation or accept the data in a write operation.
The device designer is cautioned to use the
READY feature only for access time extension
and not for synchronization because it may
severely impact system throughout.
TC
Figure 2-4. Single Cycle DMA Transfer from an
Interface Device to Memory.
~~--------~(F---------~;-))
The interface device designer should consider
the DACK signal to be equivalent to a special
chip select signal with equivalent timing relationships to the read and write strobes and TRISTATE enables of the MICROBUS.
RD or WR
\
__
r-
'------ifj----J
READY
Refer to manufacturer's literature for the standard 8257 DMA Controller for further detailed
discussion of the various modes and relationships possible for DMA interface devices.
Figure 2-5. Relationship of READY to CS, INR,
and RD.
In an 8080 system, DMA capability may be implemented by adding an 8257 DMA controller
and an 8212-8-Bit 1/0 Latch to the basic system
model.
2.2.6 The Basic Interface Model
From a device designer's viewpoint, this addition may be implied as part of the MICROBUS.
The specific. implementation and model for the
Basic MICROBUS Interface (Class 1) is the combination of the INS8080A CPU, 8224 Clock
Generator, 8228 System Bus Controller, and
This system model is
Chip Select Logic.
depicted in Figure 2-7. The expanded CPU
Group is shown in Figure 2- 8. Note the
use of the INS8259 at the bottom of the figure
to expand interrupts. See section 4.7 for expansion using INS8259.
2.2.5 Ready Signal
The READ'f.2.!.gnal is used to extend the period
of a RD or WR strobe. It is a system input that
may be driven by any number of interfacing
devices. Interfacing devices that cannot otherwise meet the access time requirements of the
system should provide a READY output to the
system. This output should not have an active
or passive connection to VCe( + 5V). It should
be open-collector (open drain if n-channel). The
system will provide a common resistive pull-up
• device for the READY signal.
Class 1 devices will also interface directly with
the INS8060 (SCIMP II) microprocessor system
model depicted in Figure 2-9. INS80T) system
model is shown in Figure 2-10.
2-5
AI5-AO
INS
80aOA
......
rc
A,S-AO
Jr.
,.
&So
CHIP
SELECT'
LOGIC
CSI
~
&Sj
M
I
.t
07-00
~1
~
07-00
~
p-
"II
MEMR
/12
INS
8228
I'
.
07-00
.
MEMW
IIOR
..
C
R
O
B
U
S
~
STSTO
IIOW
.
INS
8224
,..RESET
RESET
1
~1r1
~
Figure 2·6, INS8080A System Model for the
Basic MICROBUS Interface
For purposes of clarification:
°
• Class
devices are those which may
require special conditioning of their inter·
face to successf.ully function with micro·
processor systems.
load
limits:
I NS8080A.
INS8060,
INS8070,
• Class 2 devices are tailored for next·
generation microprocessors.
The
specification will be available in the
future.
• Class 1 devices perform with the'following
microprocessor CPUs when other bus
loading is within. the D.C. and capacitive
2·6
..-
REm
READY
.1
.2
RESET
READY
OP8224
CLOCK
GENERATOR
&
.~
DRIVER
SYNC
.L
"
WAIT_
HOLD
HLOA
INTR
I
CONTROL
SIGNALS
WR,OBIN
",
"
•
INS8080A
MICROPROCESSOR
HLOA
INTA
STSTB
CHIP
SELECT
CPU
DATA
BUS (8)
~
r--'"
MEMR
MEMW
DP8228/0P8238
SYSTEM
CONTROLLER
B1JS£Il
A15-AO
l7lJlI
ww
"&
07-00
READY
CS
RESET
i7ifW
If
-
110 R
MEMW
MEMR
MEMR
MEMW
IIOR
I/OW
RESET
elK
A7-AO
INS8257
A7-AO
i!J\CKO
M
I
C
R
0
B
U
S
OROO
IlAffi
cs
OROl
OACK2
OR02
ifACK3
OR03
READY
HOLD
HlOA
07-00
07-00
AEN AOSTB
•~
OS2
STB
INS8212
A15-A8
A15-A8
07-00
07-00
OSl
MO
ins 8259
~
07-00
07-00
INTR
CS
iNTA
AD
lfij
' 1 ' > - - SP
VIR
CS
AD
RO
WR
-INTR7- INTRO
IR7-IRO
~
Figure 2-7, INS8080 Family CPU Group to MICROBUS Configuration
2-7
CHI P
SElECT
LOG I C
&so
CSl
tTl
INS 8060
A11 • AO
M
I
C
R
0
8
U
S
NAOS
087·080
+5V
ifij
NlIDli
W1!
NWOS
Figure 2-8. INS8060 System Model
&so
CHI P
SELECT
LOG I C
{)
INS 8070
r-
CS 1
m
A15 - AD
A15 - AD
M
I
C
R
0
8
U
S
07-00
+5VT
ifij
NlIDli
W1!
NWDS
Y.rJ
Figure 2-9.
~
INS8070 Family System Model
2-8
MEMORY
Chapter 3
The Series 8000
Microprocessor
Family
CPU Group
INPUTIOUTPUT
INS8080A
MICROPROCESSOR FAMILY
Part Number/Description
M
::/(~i~j~r~ri~M))r\.
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PERIPHERAL
CONTROL
COMMUNICATIONS
• Trademark, National Semiconductor Corporation
INS8080A
8 Bit CPU (2J'S)
INS8080A-1
8 Bit CPU (1.3/1s)
INS8080A-2
8 Bi~ CPU (1.5I's)
INS8080ADI .
8 Bit CPU (2J'S)
- 4O·C to + 85·C
INS8080ADI/883
8 Bit CPU (2J'S)
-40·Cto +85·C/883B
INS8224
Clock Generator & Driver
INS8228
System Controller & Bus Driver
INS8238
System Controller & Bus Driver
(Advanced Timing)
INS8257
Programmable DMA Controller
INS8259
Programmable Interrupt Controller
-t
:::r
The Series 8000
Microprocessor Family
CPU Group
CD
CJ)
CD
::l.
CD
en
Q:)
3_1 INTRODUCTION
This chapter provides detailed information on
the Series 8000 Microprocessor family of support chips that comprise. the INS8080A CPU
Group_ The information within this chapter is
intended to assist the Series 8000 designer by
providing both descriptions of the operating
characteristics of the devices and typical interconnection diagrams. Detailed parametric information on each of the CPU Group devices is
contained in appendix 0, Device Data Sheets.
•
•
Micro-Plus - testing, special reliability
and quality program
Full development system support - all the
way from the high-powered PACE
development system (with numerous
software packages and a DOS) to lowcost development systems (for PACE and
SC/MP) to do-it-yourself PACE and
SC/MP kits
National Semiconductor also offers the most
extensive line of CPU-to-peripheral support products - for digital input/output, communications, peripheral control, and memory. And National Semiconductor is expanding the support
lines, so you can expect to see even more!
National Semiconductor offers the broadest
line of microprocessors of any semiconductor
manufacturer in the world. National has expanded its microprocessor base so any
microprocessor application can be designed
and produced using its products. From the
simplest electronic toy or control mechanism
to large control arrays, point-of-sale systems,
and large data-processing systems, National
can supply your needs. Some of the features
and benefits of dealing with National follow.
National's INS8080A Family
Positioned between the cost-effective INS8060
and the highly versatile 16-bit I NS8900, Na-
o
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3:
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CD
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Digital 1/0
•
•
•
•
•
•
•
Cost effectiveness - because of our variety, our microprocessors afford designs
that can be tailored to a multitude of applications
Broad product family of microprocessors
and peripherals
16-1;!it COMPUTATION microprocessors
for precision control functions
8-Bit BYTE HANDLING microprocessors
for terminals
418-8it LOW-COST CONTROL micropro. cessors for industrial controllers
Second sourced families
Ready availability - off-the-shelf shopping
tional's INS8080A can be used in systems
which range from a few family components to
designs which utilize its full capabilities. National offers the broadest line of peripheral circuits and memories to complement the basic
INS8080A CPU. National's INS8080A features
and benefits:
•
•
•
•
•
•
3-1
Family approach to system design
Complete CPU group
Programmable input/output concepts
Multiple source availability
Complete line of support components
Total product support
National'is .lNS8080A family is supported by
industry-standard design kits, easy-to-use
, development systems, and a full complement
of cross and resident assemblers. Various
c'omponents and software also are available to
support the INS8080A family from experimenta·
tion to final production.
Register-Select Multiplexer. The Register array
is organizec,f into six 16-bitregisters as follows.
A Program Counter
A Stack Pointer
Three register pairs (BC, DE, and HL)
composed of six 8-bit {JEmeral-purpose
registers.
• . A register pair (Wand Z) composed of two
8-bit telTlPorary registers.
•
•
•
3.2 INS8080A MICROPROCESSOR
The basic INS80BOA CPU Group consists of
three components:
•
•
•
The Program Counter (PC) is a special-purpose
register that coritains the address of the instruction being executed; the PC is incremented during each instructi,on fetch. The
Stack Pointer (SP) is also a special-purpose
register and contains the address of the next
available stack' location in the external
read/write memory (RAM).
Using the SP
register, any area of the external memory may
be reserved as a last·in-first-out (LIFO) external
stack. The stack is used primarily for temporary
storage of the contents of the PC ,and all
general-purpose registers (including the AccumUlator) during subroutine execution and In·
terrupt Service Routine execution. The Stack
Pointer is decremented when data are
"pushed" onto the stack and incremented
when data are "popped" off the stack. In other
- words, the stack is filled from top to bottom.
The INS8080A Microprocessor
The INS8224 Clock Generator and
,
'Driver
The INS8228 System Controller
The INS8080A is an 8-bit microprocessor housed in a'standard 40-pin dual in·line package. The
chip is fabricated using N-channel silicon-gate
technology. The INS8080A has a 16-bit address
bus capable of addressing up to 65k bytes of
memory, 256 input/output devices. Data is
transmitted on a separate bidirectional 8-bit
TRI-STATE bus. The INS8080A directly provides signals to cqntrol the interface to memory
and I/O ports. The INS8080A has:
•
•
•
•
•
74 Instructions· Variable Length
6 General Purpose Registers plus an
accumulator
Variable Length Stack
Add.resses 256 Input and 256 Output
Ports
Multiple Addressing Modes
General-purpose registers B, C, 0, E, H, and L
can be used by the programmer as either single
S-bit secondary accumulators or as 16-bit
register pairs that function as data counters.
The HL register pair is the primary data counter
and provides the indirect memory address for
most memory-reference instructions (refer to
3.2.5). The BC and DE register pairs are used as
data counters for a limited number of memoryreference instructions (for example: STAX B,
STAX 0, LDAX B, AND LDAX D). Temporary
registers Wand Z, which are not under software
control,are only used as a 16-bit register pair
for the internal execution of instructions.
The INS8080A is an 8-bit CPU chip that may be
used interchangeably with the Intel 8080A. It
can be used in systems that range from a few
family components to designs that utilize its
full capabilities.
Detailedqescriptions of both the INS8080A In·
struction Set and the INS8080A parametric information is contained in the INS80S0A Data
Sheet in appendix D.
The Register-Select Multiplexer enables S-bit
data transfers between the Internal Data Bus
and the Register Array. Sixteen-bit transfers oc- .
cur between the Register Array and either the
Address Latch or the Incrementerll'-ecrementer. Any of the three register pairs (BC, DE, or
HL) routes its 16-bit data output to the Address
Latch, which in turn drives both the 16·bit
A15-AO Address Bus (via the associated 16-bit
unidirectional TRI-STATE Address Buffer) and
the Incrementer/Decrementer. The data output.
of the IncrementerlDecrementer is routed to the
Register Array. The 16-bit data may be either in. cremented; decremented, or merely transferred
betwee,n registers.
.
3.2_1 Architecture of the INS8080A
Figure 3-1 illustrates CPU architecture and the
pinouts of the chip. ' (Refer to table 3-1 for
descriptions of the INS80S0A chip pinouts.) The
INS8080~consists of the following major functional units: (1) Register Array and Address
. Logic, (2) Arithmetic and Logic Unit (ALU) and
Registers, (3) Instruction Register and Decoder,
(4) Timing and Control, and (5) Data Bus B,uf·
fer/Latch. Each of the major functional units
and its logic units are briefly discussed below.
3_2_1.1
Register Array and Address Logic
3.2.1.2 ALU and Registers
. This functional section of the CPU chip comprises a static RAM Register array, and Incre'menter/Decrementer, an Address Latch, and a
This functional section of the CPU chip includes the Arithmetic Logie Unit (ALU), an S-bit
3-2
DATA BUS
BUFFER/LATCH
I
(8·BIT)
INTERNAL OAT A BUS
~U-
-- - - - - - - - - - - - - - ,
AND
REGIST ERS
TEMP
REGISTER
(TMP)
ACCUMULATOR
AND LATCH
(ACe A ACT)
I
I
I
I
I
I
I
I
I
I
I
I
I
FLAG
REGISTER
t
I
ARITHMETIC
lOGIC UNIT
l
(ALU)
I-
Cf>
l
c.>
DECIMAL
ADJUST
L_
--------------(
128)
--::::::-- + 12V
PQWE
SUPPL
I
_
1
_ _ ...J
REGISTER
AND
DECODER
I
I
I
I...f..- r-t
I r
INSTRUCTION
REGISTER
I
L
r----
-- J
"NS~UC-:;ON-
(S-BITI
INTERNAL DATA BUS
I
I
I
I
I
I
I
:
I
I
INSTRUCTION
'OECODER
I
AND MACHINE
CYCLE
ENCODING
I
I
I
I
I
___ __ -.l
~
WR
(18)
DATA BUS
CONTROL
D81N
(17)
INTERRUPT
CONTROL
INTE
(16)
INT
(14)
HOLD
CONTROL
HOLD
ACK
(21)
HOLD
(13)
WAIT
124)
READY
(23)
W
TEMP REGISTER
B
REGISTER
0
REGISTER
H
REGISTER
SYNC
(19)
lOW ORDER --..
z
TEMP REGISTER
C
REGISTER
E
REGISTER
L
REGISTER
REGISTER
ARRAY
STACK POINTER (SP)
INCREMENTER/DECREMENTER
AND ADDRESS LATCH
r
SYNC
r
PROGRAM COUNTER (PC)
L ____
- - - - __ -1
ADDRESS BUFFER
1
CLOCKS
01
.2
122)
(15)
RESET
(12)
Figure 3·1. CPU Architecture and Pinouts of INS8080A
/"
HIGH ORDER ______
I
WAIT .
CONTROL
REGISTER-SELECT
MUL TIPtEXER
-;EG-;"E;l
ARRAY
AND
ADDRESS
LOGIC
I
TIMING AND CONTROL UNIT
WRT
----
ADDRESS BUS
140·29,27-25, 11
NOTE: APPLICABLE PINOUT NUMBE'RS
ARE INCLUDED WITHIN
PARENTHESES.
NSI0600
Table 3-1.
SIGNALMNEMONIC/
PIN DESIGNATION
Input/Output Signal Descriptions
DESCRIPTION
FUNCTIONAL NAME
READY (Input)
Memory or I/O
Synchronization
When high (logic 1), indicates that valid memory
or input d.ata are available to the CPU on the
I NS8080A External Data Bus. The READY signal
is used to synchronize the CPU with slower memory
or input/output devices. If the I NS8080A does not
receive a high READY input after sending out an
address to memory or an input/output device, the
I NS8080A enters a WAIT mode for as long as the
READY input remains low (logic 0). The CPU may
also be single stepped by the use of the READY
signal.
HOLD (Input)
Hold or DMA
Operations
When high, requests that the CPU enter the HOLD
mode. When the CPU is in HOLD mode, the CPU
address and data buses both are in the highimpedance state. The HOLD mode allows an external device to gain control of the INS8080A address
and data buses immediately following the completion of the current machine cycle by the CPU. The
CPU acknowledges the HOLD mode viathe HOLD
ACKNOWLEDGE (HLDA) output line. The HOLD
request is recognized under the following conditions:
The CPU is in the HALT mode .
The READY signal is active and the CPU is in
theT2 orTw state.
•
•
I
INT (Input)
I nterrupt Request
When high, the CPU recognizes an interrupt request on this line after completing the current
instruction or while in the HALT mode. An interrupt request is not honored if the CPU is in the
HOLD mode (H LOA = logic 1) or the Interrupt
Enable Flip·flop is reset (lNTE = logic 0).
RESET (Input)
Reset
When activated (high) for a minimum of three clock
periods, the content of the Program Counter is
cleared and'the internal Interrupt Enable and Hold
Acknowledge Flip-flops are reset. Following jI
RESE,T, program execution starts at memory location O. It should be noted that the Status Flags,
Accu":1ulator. Stack Pointer, and other registers are
not cleared during the RESET sequence.
SYNC (Output)
Synchronizing Signal
When activated (high), the beginning of a new
machine cycle is indicated and the status word
information is outputted on the External Data Bus.
WAIT (Output)
Wait Mode
When high, acknowedges that the CPU is in the
WAIT mode.
WR (Output)
Write
When low, the data,on the External Data Bus are
stable for WR ITE memory or OUTPUT operation.
3-4
Table 3-1.
Input/Output Signal Descriptions (Continued)
SIGNAL MNEMONIC/
PIN DESIGNATION
FUNCTIONAL NAME
HLDA (Output)
Hold Acknowledge
DESCRIPTION
Goes high in response to a logic 1 on the HOLD
line and indicates that the data and address buses
will go to the high-impedance state. The H LOA
begins at one of the following times:
The T3 state of a READ memory input
operation.
The clock period following the T1 state of a
WR ITE memory output operation.
I n both cases, the H LDA signal starts after the
rising edge of the 1 clock, and high impedance
occurs after the rising edge of the 2 clock.
•
•
I NTE (Output)
I nterrupt Enable
Indicates the content of the internal Interrupt
Enable Flip·flop. The Enable and Disable Interrupt
(EI and 01) Instructions cause the Interrupt Enable
Flip·flop to be set and reset, respectively. When the
flip·flop is reset (INTE ~ logic 0). it inhibits inter·
rupts from being accepted by the CPU. In addition,
the internal interrupt Enable Flip·flop is automat·
ically reset (thereby disabling further interrupts) at
the Tl state of the instruction fetch cycle, when an
interrupt is accepted; it is also reset by the RESET
Signal.
DBIN (Output)
Data Bus In
When high, indicates to external circuits that the
External Data Bus is in the input mode. The DBIN
Signal should be used to gate data from memoryor
an input/output device onto the External Data Bus.
A15 -Ao (Output)
Address Bus
This bus comprises 16 TRI·STATE®output lines.
The bus provides the address to memory (up to
65k bytes) or denotes the input/output device number for up to 256 input and 256 output peripherals.
DrDo (I nput/Output)
Data Bus
This bus comprises eight TRI-STATE input/output
lines. The bus provides bidirectional communication between the CPU, memory, and input/output
devices for instructions and data transfers. A status
word (which describes the current machine cycle)
is also outputted on the External Data Bus during
the first state of each machine cycle. (SYNC ~
logic 1).
1 and 2 (Inputs)
Clock Inputs
Two non-TTL compatible clock phases that provide nonoverlapping timing references for internal
storage elements and logic circuits of the CPU.
+12V (Input)
+5V (Input)
-5V (Input)
GND
V OD Supply
Vce Supp.Jy
V BB Supply
,
Ground
Vss (0 volt) reference
3-5
\
Accumulator (ACC)" an 8-bit Temporary Accumulator (ACT), a 5-bit Flag Register, and an
8-bit Temporary Register (TMP)_ The 'ALU performs arithmetic, logical,'and rotate operations.
It is fed by the ACe, the ACT,and the Carry Flipflop of the 5-bit Flag Register. The results of
the ALU operation are transferred to either the
Internal Data Bus or the Accumulator. In addition, the ALU feeds the Flag Register. This
register contains flip-flops Which provide
storage for the five condition flags (Zero, Carry,
Sign, Parity, and Auxiliary Carry) associated·
with the execution of instructions in the
INS8080A. The Carry, Flag may be set or complemented by execution of the Set Carry or the
Complement Carry Instruction (refer to 8080
Data Sheet), respectively. The 8'bit Temporary
Register is loaded via the Internal Data Bus and
routes all or portions of its data to the ALU, the
Flag Register, and/or the Internal Data Bus. The
Accumulator serves as a link between the external memory and all other software-controlled
registers. The Accumulator is used in performing arithmetic and logic operations and for storing the results of these operations. Immediate
instructions, data transfers, shifts, and rotates
also use the Accumulator. The Accumulator
receives data from the ALU and the Internal
Data Bus and routes data to the Temporary Accumulator and the Internal Data Bus. During
the execution of the Decimal Adjust Ac- cumulator Instruction, the contents of the Accumulator and the Auxiliary Carry Flip-flop may
be tested for decimal correction (utilizing the
'
Decimal Adjust logic).
3.2.1.3
Units (both internal and extermil to the CPU) for
execution of the specified operation.
3.2.1.5 Data Bus Buffer/Latch
This major functional unit includes ,an 8-bit
Data Buffer and an 8·bit Latch. The 8-blt, Data
Buffer is a bidirectional TRI-STATE interface
that provides isolation between the Internal
Data Bus and the 0]"00 External Data Bus. In
the output mode, data or internal status infor·
mation on the Internal Data Bus initially is loaded into the 8-bit Latch. The outputs of the Latch
are then transferred to the External Data Bus via
the output Data Bus Buffer, which is in the highimpedance state during input or nontransfer
operations. In the input mode, external data are
transfered to the Internal Data Bus via the input
Data Bus Buffer, which is in the high·
impedance state during output or nontransfer
(DMA) operations. With the exception of the T3
state of a machine cycle (refer to 3.2.2.1), the Internal Data Bus is precharged at the start of
each internal state.
'
3.2.2, Operating Cycle
3.2.2.1 Instruction Cycle and Related Timing
An 1nstruction cycle of the INS8080A consists
of fetching an instruction from the program
stored in external memory and executing the
operation specified by the instruction. The
fetch routine first causes the instruction address to be transferred from the Program
Counter to the Address Bus via the output Address Latch. Next, an input data transfer (fetch
from memory) is initiated. When the selected
instruction (which may be one, two, or three
bytes in length) is subsequently placed on the
External Data Bus, the operation code byte is
loaded into Instruction Register. If the instruction consists of more than one byte, additional
states are required to fetch each byte of the in·
struction. In this case, the subsequent bytes
are place~ in temporary storage registers.
Instruction Register and Decoder
This functional section includes an 8-bit Instruction Register and an Instruction Decoder.
The Instruction Register stores byte 1 of the in:
struction during the execution cycle. This byte,
which contains the operation code, is transfer- '
red to the Instruction Register via the 'Internal
Data Bus. The succeeding Instruction Decoder
and control logic circuits thengerierate the required signals to, control the internal data
transfers and the timing of the new instruction,
which may require from one to five machine
cycles for execution (refer to 3.2.2.1).
After the complete instruction is present in the
INS8080A, the Program Counter is incremented
and the instruction is then executed in the reo
maining states of the instruction cycle. The
'instruction may call for a memory·read, a
memory-write, or an internal CPU operation
such as a register-to-register transfer or an addregisters operation.
3.2.1.4 Timing and Control Unit
TheTiming and Control Unit generates the state
and cycle timing signals, and maintains the proper sequences of events required for any proceSSing task. Two nonoverlapping external
clock inputs (1 and 2) are accepted by the
Timing and Control circuits to furnish the timing references f9r all microprocessor actions.
In addition, the output of the Instruction
Decoder is combined with various timing
signals and external control inputs at the Tim·
ing and Control circuits to provide the control
and gating signals required by other functional
The basic instruction cycle (see figure 3-2) contains from one to five machine cycles, which
are referred to as M1, M2, M3, M4, and M5. Each
machine cycle, in turn, contains from three 'to
five states, which are referred to as T1, T2, T3, ,
T4, and T5. The duration of a T state is determined by the interval between two successive
positive-going transitions of the-1 clock pulse.
Depending on the 'type of instruction being ex-
3-6
STATES
/r----------------------------------L---------------.----------------___~
Ti
T,
0'
.2
b==db
.
h
'
-I
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/A
•
I I
II
X
II
SYNC
~
READY
WAIT
I~
II, ,
ODIN
WR
~
w
M2
OF REQUIRED I
~
">u
w
M3
(IF REOUIRED I
Z
;:
U
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M.
(IF REOUIRED I
MS
(IF REQUIRED I
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1
,1"15 Ao MEMORY
ADDRESS
07-00 STATUS
INFORMATION
A15 AO MEMORY
ADDRESS
07-00 ST A1 US
INFORMATION"
I
SAMPLE: READY
HOLD
SAMPLE: READY·
HOLD
HlTA
SAMPLE: READY·
HOLD
ADDRESS
SAMPLE: READY
°7-00 STATUS
INFORMATION
A15 An MEMOR'f
ADDR£SS
07-00 STATUS
INFORMATION
HOLD
I
,
-
L-.. WR ITE MODE
I
I
1\
I
I
II
I 1\
I
\
I
UNKNOWN
FLOATING
MEMORY ACCESS
TIME ADJUST
OPTIONAL
HALT OR
MEMORY ACCESS
TIME AnJ""T
OPTIONAL
MEMORY ACCESS
TIME ADJUST
OPTIONAL
MEMORY ACCESS
TIME ADJUST
MEMORY ACCESS
TIME ADJUST
I
I
I
I
I
I
I
I
I
01TA
OPTIONAL
I
~
OITA
FETCH
INSTRUCTION
INSTRUCTION
EXECUTION
INSTRUCTION
EXECUTION
{IF REQUIREDI
FETCH OR·
WRITE DATA
(IF REOUIRED)
FETCH ORWRITE DATA
FETCH 9R
WRITE DATA
OPTIONAL
. SAMPLE: READY
HOLD
\...
I
I
I
I
I
I
A15 AO MEMORY
ADDRESS OR I/O
NUMBER*" °7-00
STATUS INFO.
A15 AO MEMORY
~
I
V
rSTABLE
t LL-.REAOMODE
I
II (DATA
I
I
I
I
I
STATUS
INFORMATION
h
(HI-Z)
II
I
I
TS
h
I
I
-1
T.
h
.'~
I I
It
I
M'
\
T3
~I
.~
I
(
Tw
FETCH OR
WRITE DATA
INSTRUCTION
EXECUTION
(IF REQUIRED)
-EXCEPT DAD INSTRUCTION
NS 1060 1
Figure 3-2. Basic Instruction Cycle
INS8080A inputs an instruction byte from the
External Data Bus. During a MEMORY READ,
STACK READ, or INPUT machine cycle, the
INS8080A inputs a data byte from the External
Data Bus. In an INTERRUPT machine cycle, an
interrupt instruction of up to three bytes is jammed onto the External Data Bus and is routed to
the CPU. The I NS8080A outputs a data byte onto the External Data Bus during a MEMORY
WRITE, STACK WRITE, or OUTPUT machine cycle.
ecuted, a total of from 4 to 18 T states are required for a full instruction cycle.
Machine cycle M1 is always the operation-code
fetch cycle and lasts from four to five T states.
The duration of machine cycle M2, M3, M4, or
M5 is normally three T states. During state T1
of a machine cycle, the following occur: the
content of the Program Counter is placed on
the A15-AO Address Bus; the SYNC Signal
(related to the leading edge of the <1>2 clock) is
activated (high); and status information pertaining to the current machine cycle (refer to 3.2.4)
is outputted onto the External Data Bus. State
T1 is always followed by T2, during which time
the conditions of the READY and HOLD Signals
are tested. In order to proceed to the T3 state,
the READY Signal must be high (logic 1). If this
signal is low (logic 0), the INS8080A enters the
wait state (TW) and remains there until the
READY Signal goes high.
States T4 and T5 are available if required for
execution of a particular instruction. If the instruction being executed does not require
either of these states, the CPU proceeds from
the T3 state of a machine cycle directly to the
T1 state of the next machine cycle. The T4 and
T5 states are only used for internal processor
operations.
3.2.2.2 State Transition Sequence
The type of machine cycle in progress determines the events that take place during the T3
state. During a FETCH machine cycle, the
Figure 3-3 illustrates in flowchart form how the
INS8080A proceeds from the T1 through T5
3-7
YES
READY - HLTA
HOLD
MODE
[D
RESET HLTA
NOTES:
INTERRUPT ENABLE FLlP·FLOP ,
10
IS RESET IF INTERRUPT FLlp·FLOP
L../ IS SET.
~
INTERRUPT FLlp·FLOP IS RESET
IF INTERRUPT ENABLE'FLlP·FLOP
L/ IS RESET.
iJ"'- READY Nch SAMPLED FOR DAD
~ INSTRUCTION DURING M2 AND M3.
REFER TO HOLD SEQUENCES
DISCUSSION (2.9).
r.;-\.
L/
Figure 3-3. fNS8080A QPU State Transition,Flowchart
3-8
NS'0602
states of a machine cycle during the execution
of an instruction. The actual number of states
involved in a machine cycle depends on the instruction being executed and on the particular
machine cycle of the instruction. The flow
diagram also shows how the READY, HOLD,
and INT lines are sampled during the machine
cycle, and how the conditions on these lines affect the basic transition sequence. Only the
basic sequence and the WAIT sequence are
discussed below. The HOLD and INTERRUPT
sequences are discussed later in this chapter.
ecuted. The first byte of an instruction contains the operation code. The second or third (if
applicable) byte of a multiple-byte instruction
contains either data or addressing information.
Multiple-byte instructions must be stored in
consecutive memory locations. For a multiplebyte instruction, the address of the first byte is
used as the address of the instruction.
3.2.4 Status Info,rmation
The I NS8080A outputs an 8-bit status word onto
the D7-DO External Data Bus during the first
state (SYNC interval) of each machine cycle to
identify the machine cycle in progress. A latch
circuit for storing the status word for control of
external circuits is illustrated in figure 3-6. (A
similar latch is included in the I NS8228JINS8238 System Controller and Bus Driver.)
Table 3-2 defines the status information and indicates how this information is distributed on
the External Data Bus. Table 3-3 lists the status
bit outputs for each type of machine cycle.
In the basic sequence, the INS8080A does not
wait for memory, does not hold, and is not
halted. During this sequence, the READY input
is held high, the HOLD input is held low, and
the HALT Instruction is not executed. The
I NS8080A enters the WAIT sequence as a result
of sampling a low READY Signal during the T2
state of every machine cycle, except for DAD
(add Register Pair to Hand L Registers) Instructions. (When executing DAD Instructions, the
READY input is only sampled during the M1
machine cycle.) The WAIT sequence enables
the·INS8080A to adjust its processing cycle
time to match the slower access time of the
state.
memory which requested the WAIT
Beginning at T2, the memory must hold the
READY line low for a number of clock cycles
equal to the number to TW states to be inserted
in the machine cycle. The actual number of TW
states to be inserted is determined by external
logic that is user-designed. The INS8080A
does not furnish a control output during each
state to directly indicate its internal state. Instead the microprocessor indicates the internal
state by supplying INTE, HLDA, DBIN, ViTR, and
WAIT control signals to the external circuits.
3.2.3
3.2.5 Addressing Capabilities
The INS8080A chip has a 16-bit address
capability, thus allowing anyone of 65,536
memory locations to be uniquely specified.
Data to be operated on are often stored in
memory. When multi-byte numeric data are
used, the data must be stored in consecutive
memory locations. In this case, the least
significant byte is stored first, followed by progressively more significant bytes.
Either the Program Counter, the Stack POinter,
or one of the 16-bit register pairs (BC, DE, and
HL) is used in each memory-reference instruction. The Program Counter is always used to
specify the addresses of program instructions
(or data); it provides for the increasingly sequential execution of instructions, except when
an interrupt or a branch instruction is effected.
The Stack Pointer and the register pairs are
used for other addressJdata requirements. The
INS8080A has four different modes for addressing data· stored in memory or in registers:
these are immediate, direct, register, and
register indirect.
Each of the addressing
modes is discussed below.
Data and Instruction Representation
An 8-bit binary word or byte (see figure 3-4) is
used to represent data in the INS8080A. Bit DO
is the least significant bit (LSB) of the data
word. The INS8080A instruction repertoire includes 1-byte, 2-byte, and 3-byte instructions
(see figure 3-5). The exact instruction format
depends on the particular operation to be ex-
BYTE
/
,
I
1~__D_7__~__D_6__~_'_D_5__~__D_4__~__D_3__~__D_2__~__D_l__~__D_O__-,I----BOTNUMBE.
NSf 0603
Figure 3-4. Data Word Format
3-9
1~__ ~ os __~___ ~_0_4 ~
0_7__
___
05 __
__
__0_3__
~
__0_2__
~_0 '~
__0_0__
~1 OPCODE
lo,coDE
___
A. One-Byte Instruction
Bv"'l
07
Os
05
°4
03
O2
0,
DO
BVT"I
07
Os
05
04
03
02
0,
DO
1
DATA OR
ADDRESS
B. Two-Byte Instruction
I
07
Os
05
04
03
O2
0,
DO
IO'COOE
BVT"I
07
Os
05
04
03
02
0,
DO
1ADORESS
DATAOR
BVTE31
07
Os
05
04
03
02
0,
DO
IADDRESS
DATAO~
BVTE1
I
C. ThrH-Byte Instruction
NS'0604
Figure 3-5. Instruction Formats
3-10
10
DO
01
9
O2
8
DO
01
O2
7
°3
07
SYNC
06
::6
07
19
17
STATUS
LATCH
OBIN
92
4>1
~
...
CPU EXTERNAL
05
5'
06
l
0 4 , DATA BUS
4
05
I NS8080A
MICROPROCESSOR
03
3
04
J 22
15
3......
DOD
Dll
5
7
9.....
16
~
INS8212
INPUT/OUTPUT
PORT
(TTL)
22......
r,i
HLTA
~ INP
20
¢i
STACK
~ OUT
~
18.....
CLOCK
GENERATOR
AND DRIVER
~ INTA
wo
~
8
Ml
~
Dl8
CLR
OS2
.13
00 7
MO
12
I
VCC
Figure 3-6, INS8080A Status Latch Circuit
I
BASIC
CONTROL
BUS
~ MEMR
OSl
11
~
OBIN
NS70605
Table 3·2. Status Information Distribution and Definition
SIGNAL MNEMONIC
DATA BUS
BIT NUMBER
INTA
Do
Acknowledge signal for an Interrupt Request. When
DBIN signal is high, the INTA signal should be used
to gate an instruction (for example, Restart <;>r
Jump to Interrupt Service Routine) of up to three
bytes onto the DrDo Data Bus. The INTA signal
can also be used to control the flow of data onto
the External Data Bus.
WO
0,
When low, indicates that the current machine cycle
will be either a WRITE memory or OUTPUT oper·
atipn. When high, a READ memory or INPUT
operation will be executed.
STACK
0,
When high, indicates that the A'5 -Ao Address Bus
contains the pushdown stack address from the
Stack Pointer (SP).
HLTA
D3
Goes high to acknowledge a Halt Instruction.
OUT
04
When high, indicates that the A15-AO Address Bus
contains the address of an output device and that
the External Data Bus will contain the output data
when the WR is low.
M,
DEFINITION
Goes high to indicate that the INS8080A is in the
fetch cycle for the first byte of an instruction.
~ D5
INP
D6
When high, indicates that the A15-AO Address Bus
contains the address.of an input device and that
the Data Bus will contain the input data when the
DBIN signal is high. The INP signal can also be
used to control the flow of data onto the Data Bus.
MEMR
D7
When high, indicates that the Data Bus will be used
for READ memory data. The MEMR signal can
also be used to control the flow of data onto the
Data Bus.
3·12
Table 3-3. Status Bit Outputs For Each Type of Machine Cycle
DATA BUS BITS
STATUS
WORD
TYPE
D7
D6
Instruction Fetch
1
1
Memory Read
2
1
Memory Write
3
Stack Read
4
TYPES OF MACHINE CYCLES
D5
D4
D3
D2
D1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
Do
Stack Write
5
0
0
0
0
0
1
0
0
Input Read
6
0
1
0
0
0
0
1
0
0
Output Write
Interrupt Acknowledge
7
0
0
0
1
0
0
0
8
0
0
1
0
0
0
1
1
9
1
0
0
0
1
0
.1
0
10
0
0
1
0
1
0
.
Halt Acknowledge
Interrupt Acknowledge While Halt
3.2.5.1 Immediate Addressing
1.
1
bits of the address are in the second 8-bit
register (C, E, or L).
In this mode, the instruction contains the required data in either the second byte (8-bit data
quantity) or the second and the third bytes
(16-bit data quantity). When the data represent
a 16-bit quantity, the least significant byte is
first, followed by the most significant byte. The
immediate addressing mode is relatively fast
because an additional data address is not
formed, nor is an additional memory access required to fetch data.
.
3.2.6
Input/Output Operation and Control
High-speed data transfers between the
microprocessor, memory, and input/output
peripheral deyices are made in parallel. The
data and address ports of the INS8080A chip
are connected to memory or other peripherals
via an 8-bit bidirectional External Data Bus and
a 16-bit unidirectional Address Bus, respective- ,
Iy. Various timing and control signals (for example, SYNC, DBIN, and so forth) and status
information are generated during the data
transfers.
3.2.5.2 Direct Addressing
In this mode" the instruction contains the exact
memory address of the required data or instruction in the second and third bytes. Byte'2 contains the lower-order bits of the memory address and byte 3 contains the higher-order bits.
Jump and Branch Instructions are executed via
the direct addressing mode. It is also used for a
limited number of memory-reference instructions.
3.2.6.1 Data Input Operations
The input cycle consists of reading data from
either a specified memory location or from an
input peripheral device. Timing is shown in
figure 3-7 for a data-input operation. As shown,
status information is initially transferred onto
the 07-00 External Data Bus during the SYNC
signal interval. The low-to-high transition of the
<1>2 clock during state T2 clears the status inforrnation from the External Data Bus, preparing
the bus for the receipt of incoming data. At this
time, the A15-AO Address Bus contains a valid
address and anyone of 65,536 memory locations or 256 input peripheral devices may be
selected. Data subsequently placed on the
07"00 Data Bus by memory or an input
peripheral device then are sampled during the
T3 state of a machine cycle. During the inputting of data to the microprocessor, the INS8080A generates a high DBIN Signal which is
used externally to enable the data transfer. The
DBIN signal is initiated by the leading edge of
the <1>2 'clock during state T2 and is terminated
by the leading edge of the <1>2 clock during state
3.2.5.3 Register Addressing
The register addressing mode is conceptually
identical to the direct addressing mode. In the
register addressing mode, a one-byte instruction is used to specify the register or the
register pair in which the required data are
located.
3.2.5.4 Register Indirect Addressing
In this mode, a 1-byte instruction specifies a
register pair (or Stack Pointer) that contains the
exact memory location of the required data or
instruction. The high-order bits of the memory
address are in the first 8-bit register-.(B, 0, or H)
of the specified register-pair and the low-order
3-13
.'
.'
At5-Ao
07-0 0
SYNC
oalN
REAOV
WAIT
Wi!
"0"
"'"
I
STATUS
INFORMATION
+-_...J
I
INPUT
READ
FETCH
CYCLE
CYCLE
I
I
NOTE: THE READY, WAIT, ANDWR SIGNALS DO NOT CHANGE STATE AND
ARE IN THE LOGIC STATES DESIGNATED CONTINUALI. Y
NS10606
Figure 3-7. Data Input Operation Timing
3.2.7 Interrupts
T3. (During the WAIT sequence, the DBIN
signal is extended one or more clock periods by
any TW states intervening between states T2
and T3.) Machine cycles during which the DBIN
signal is generated include FETCH, MEMORY
READ,. STACK READ, and INTERRUPT.
Figure 3-9 illustrates the timing for an interrupt.
A peripheral device requests an interrupt by
raising the microprocessor's INT line high. The
INS8080A acknowledges the asynchronous interrupt request at the completion of the instruction in progress, providing interrupts have not
been disabled either by an interrupt service not
followed by a new Enable Interrupts Instruction
of by a Disable Interrupts Instruction. During
the first clock period (SYNC interval) of the INTERRUPT machine cycle, the microprocessor
outputs a high INTA status bit (DO) to indicate
acknowledgement of the external request.
3.2.6.2 Data Output Operations
The output cycle consists of writing data into
either a specified memory location or to an out·
put peripheral device. Figure 3-8 shows the timing for a data-output operation. The outputting
of status information onto the D7-DO Bus and
address information onto the A15-AO Bus is as
described above for data-input operations. The
rising edge of 2 within state T2 clears status
information from the D7-DO Data Bus and loads
in the data that are destined for memory or for
peripherals .. 'Note that a high READY signal is
also re.quired during an output cycle. If a high
READY signal is not present, the microprocessor enters the TW state following the T2
state. In this case, data on the D7-DO lines remain stable during the wait state, and the processing cycle will not proceed until the READY
goes high. During the outputting of data from
t~e microprocessor (MEMORY WRITE, STACK
. WRITE, and OUTPUT machine cycles), the INS8080A generates a low WR output fo~n
chronization of external transfers. The WR is
initiated by the leading edge of the first 1
clock foltowing T2 and is terminated by the
leading edge of the 1 clock during the state
following T3. During the WAIT sequence, the
WR output is extended one or more clock
periods by any TW states intervening between
states T2 and T3.
The asynchronous interrupt request is reclocked by internal logic to establish a proper relationship with the 2 clock. As shown, an interrupt request that is made when the INTE line i.s
high (enabled), causes the internal interrupt
flip-flop to be set by the 2 clock pulse during
the last state of the instruction cycle in progress. This action ensures the completion of '
any instruction being executed before the processing of the interrupt. .The INTERRUPT
machine cycle that. follows an enabled interrupt
request is similar to a FETCH machine cycle,
except that the. Program Counter is not incremented during the acceptance of the interrupt
instruction and the contents of the Program
Counter and status information are pushed on·
to the external stack. In this way, the correct
pre-interrupt instruction address is maintained
in the external stack during the, interrupt
machine cycle.
"'
The interq.lpting device identifies its required
service routine by jamming an instruction of up
3·14
.pI
.2
A1S-AO
°7-0 0
SYNC
DBIN
READY
WAIT
"0"
WR
STATUS
INFORMATION
NOTE:
THE READY AND WAIT SIGNALS DO NOT CHANGE STATE
AND ARE IN THE LOGIC STATES DESIGNATED CONTINUALLY
NS'D607
Figure 3-8. Data Output Operation Timing
",
SYNC
+-----+-i--'-J
DBIN
WR
~--~~+-~--~~~--~~~---+---+---+--~
II
RETURN M,
IINTERNAL)
INTE
1
+--~~.;...,."\
, I
I I
I I'
III
+_..J
~'!'~'~~:~:!AO~
1_--...,:1 I. I
4-----~----~
~I~I~--~--~-+--~--~~--~~
INT
INT F/F
IINTERNAL)
\j-----+-+-"---+---+---+---..:....~-"-_:__..:...--..;..--_l
INFOR~~~T~:
_----.-!'....;.,---'!---1---+---~--.l----"---...:u.--~----l
INTERRUPT
L -_ _---L_ _ _...l- ACK~~~C:DGE ~_--L_--'-_--L--=:":"':::=---..l_ _~:":"::':=-:.......J
NS'0608
Figure 3-9. Interrupt Timing
3-15
address and data buses, thereby allowing the
device to effect direct data transfers to
memory.
to three bytes onto the D]"DO External Data Bus
during state T3, when the DBIN signal is high
(for example, a Call Conditional, a Jump Conditional, or a Restart Instruction). During this
time, memory and other peripherals are temporarily in the high-impedance state, thereby
allowing the interrupting device to control the
External Data Bus. The Restart Instruction, for
instance, includesa 3-bit variable field that is
used to call a routine in one of eight memory
locations with the following hexadecimal addresses: 0000, 0008, 0010, .0018, 0020, 0028,
0030, and 0038. Any of these addresses may be
used to store the first instruction of a service
routine for the requesting device.
Figure 3-10 shows the timing of a HOLD operation for a READ MEMORY or INPUT machine cycle, and figure 3-11 shows the timing of a HOLD
operation for a WRITE MEMORY or OUTPUT
machine cycle. Note that in both cases, the
asynchronous HOLD request is re-clocked by
internal logic to establish the proper relationship with the <1>2 clock. As shown, a HOLD request that is made when the READY line is
high, causes the internal hold flip-flop to be set
by the <1>2 clock pulse. With the flip-flop set, the
subsequent leading edge of the <1>1 clock pulse
causes the HLDA output to go high at either the
T3 state for a READ MEMORY or INPUT cycle or
at the clock period following the T3 state for a
WRITE MEMORY Of OUTPUT cycle. In either
case, the A15-AO Address Bus and 0]"00 External Data Bus are floated (high-impedance state)
after the leading edge of the next <1>2 clock
pulse.
3.2.8 Hold Operations
Direct Memory Access (DMA) is a method frequently used to effect data transfers between
peripherals and memory. Using this technique,
data transfers can be directly implemented
without involving the microprocessor. In the
I NS8080A, provisions are included for DMA
transfers. A peripheral requests a DMA transfer
by placing a high level on the HOLD line of the
INS8080A. This, in turn, may cause the microprocessor to suspend temporarily its operations and the address and data buses to go to
the high-impedance state (float). The I NS8080A
acknowledges the asynchronous HOLD request by placing a high on the HLDA line.
When its HOLD request is acknowledged, the
related peripheral device takes control of the
Once the address and data buses of the
INS8080A are floated; the microprocessor
usually suspends its operations. However, if
the HOLD request was acknowledged at the T3
state and if a particular machine cycle requires
the T4 and T5 states, the microprocessor continues these operations internally. Thus, the internal processing activities do not end until the
machine cycle is terminated.
Tl
¢1
¢2
I
II
I II
HOLD
REQUEST
HOLD
(INTERNALLY
RE·CLOCKED)
' -1-1-1- ..Ii
II
III I
II
READY
INTERNAL
HOLD F/F
HLDA
*T4 AND T 5
~!IIPE~R~A~TI~O~N~CA~N~B~E~"";
DONE INTERNALLY.
NS10609
Figure 3-10. Hold Operation Timing for MEMORY READ or INPUT Cycle
3-16
T1
it>2
A15"":Ao
+---+---+--'V+---+-....-+--~,-+ - - -- +-- (HI-Zl
-r..;.__..,....;._...._...l._ _ I _..J..FLOATING
_ ---..!..- -~'
WR
HOLD
REQUEST
HQLD
READY
INTERNAL
HOLD F/F
HLDA
+-_-.1
1
I
I
I
I·
I
~---~------~------~---~-~-~---~---~---~
+o----!-----!----..:......I
~---~---~---~---..:..-~-~
NS10610
Figure 3-11. Hold Operation Timing for MEMORY WRITE or OtJTPUT Cycle
When the peripheral device has completed the
DMA transfer, it places a low level on the HOLD
line of I NSBOBOA. This low level causes the
microprocessor to leave the HOLD state
through a sequenc~ similar to that by which it
entered. Fo"owing the leading edge of the next
4>1 clock pulse, the HLDAoutput returns to a
low level. Normal processing then resumes
with the machine cycle following the last cycle
that was executed.
INTE output line is high, causes the
INSBOBOA to exit the halt state and
enter state T1 On the leading edge of
the next 4>1 clock pulse (see figure
3-14).
3.2.10. Initialization
When pOwer is first appplied to the INSBOBOA,
an external high-level signal of at least three
clock periods in duration is placed on the
RESET line to clear the Program Counter (see
figure 3-15). Thus, the first instruction is always
fetcheq from memory location 000016 after the
power-up initialization cycle. The Status Flag
Register, the Stack Pointer, and other working
registers (Accumulator,S Register, C Register,
and so forth) are unaffected -by the active
RESET signal. Instead, these registers are in·
itialized by related instructions within the
program.
3.2.9 Microprocessor Halt
The Halt (HLT) Instruction is used to effect a
programmed halt condition. When the HLT Instruction is executed, the INSBOBOA enters the
halt state (T WH) after state T2 of the next
machine cycle as shown in figure 3-12. The
microprocessor can exit the halt state in only
the following three ways, which are shown in
the Halt Sequence Flowchart of figure 3-13.
1.
2.
3.
3.3
A high level on the microprocessor's
RESET line resets the INSBOBOA to
state T1, and clears' the Program
Counter as described in 3.2.10.
A high level on the HOLD line causes
the microprocessor to enter' the
HOLD state as described. in 3.2.B.
When the HOLD line is subsequently
driven low, the I NSBOBOA reenters the
halt state at. the leading edge of the
next 4>1 clock pulse (see figure 3-14).
A high level on the INT .line, while the
INS8224
DRIVER
CLOCK
GENERATOR, AND
The INSB224 is a single-chip crystal controlled
cloc'k generator and driver for the INSBOBOA.
Figure 3-16 is a functional block diagram of the
INSB224 chip. The INSB224 provides 4>1 and 4>2
MOS clocks, a power-on RESET Signal, and a
synchronized READY Signal for the I NSBOBOA.
In addition, the INSB224 provides a Status
Strobe (STSTS) for the INSB22B/lNSB23B
System Controller and Sus Driver, and a 4>2 TTL
3·17
¢2
r-~~~----~----~--~/~~~------~---
- --' ",- - - "-""-Jr--:-SYNC
OBIN
WAIT
STATUS
INFORMATION
FETCH
CYCLE
HALT
ACKNOWLEDGE
CYCLE
I
NS10611
Figure 3-12. Halt Timing
TO STATE
T,
TO STATE T,
Figure 3·13_ Halt Sequence Flowchart
3-18
¢1
¢2
A1S-AO
0 7 -00
SYNC
I
I
I
I
I
I
I
I
I-....:-FL.OATING
---I-T;~L~;T~~~(H~j-+-rii--t--¥,..:..--.....
I ,...._
; --...
.....~_..,.:: (HI-Z)
1
1
--Tn--r-lfnrTTr J
I I
I
DBIN
HOLD
I
HOLD F/F
(INTERNAL)
I
HLDA
iI
I
I
I
I
I
I
II
I
I
I
I
INTE
INT
INT F/F
(INTERNAL)
I
I
II I II
I II
II I
III
III
\
I
I I I
I
I
-,-RST
11:
1("
II
II
I ,
1;~IBll
INHIBIT
HOLD
I
I
STATUS
INFORMATION
INTERRUPT
ACKNOWLEDGE
~
__~____~____- L____~____L -____~__- J____-LWHILEHALT
CYCLE
NSI0613
Figure 3-14.
Relation Between HOLD and INT in the HALT State
¢1
¢2
A 1S -Ao
0 7 -0 0
1. ____ 1 ____..:...___
•
~FLOATINGI(HI-Z)
-1'1- - - - - -I' - -I""\_-~-N.!;"I!!O"~-!!::X""--"""--
,.__I..:.l_ _~-:-_ _ _-+I____ :;L ____
. . . -- II
I
I
~
- -1- - - -
~
RESET
INTERNAL
RESET
SYNC
DBIN
STATUS
INFORMATION
I
I
I
t
'-----'-I---..:...-
I
~~I---~~I---~~---~~I~
+----:-----:....---...;...---.f~----:....---...:..----:.--I
I
I
I
I
I
I
(1) THE RESET SIGNAL MUST BE ACTIVE FOR A MINIMUM OF THREE CLOCK
I
FETCH
CYCLE
CYCLES. WHEN RESET SIGNAL IS ACTIVE. ALL OF CONTROL OUTPUT
SIGNALS WILL BE RESET IMMEDIATELY OR SOME CLOCK PERIODS LATER.
(2) IN THE ABOVE TIMING DIAGRAM. nAND i MAY BE ANY INTEGER.
NSI0614
Figure 3-15. Initia.lization Timing
3-19
Clock, and an Oscillator (OSC) Signal to accom'
, modate user reqUirement;;.
may have to be connected in series with the
crystal to produce the exact desired frequency.
The stable, crystal-confrolled oscillator output
is routed to the OSC chip pinout via a buffer for
external, timing purposes, arid, to the clock
generator circuit.
The INS8224:
•
•
•
Has Crystal-Controlled Oscillator for
Stable Operation
Provides Status Strobe for INS8228
Provides Power-On Reset forlNS8080A
The clock generator circuit comprises a divideby-nine counter and the associated decode
gating logic. The circuit generates the 1/>1 and
1/>2 clocks (see figure 3-17) and internal timing
signals. All of the nonoverlapping waveforms
generated follow a simple 2-5-2.pattern. Two of
the clock generator outputs are routed to highlevel drivers, which convert the TTL1 and 2
clocks to MOS level clocks. A- third output of
the clock generator is ,routed to the 2 (TTL)
chip pinout for external timing purposes.
An external, series-resonant crystal provides
frequency control for the oscillator circuit as
shown in figure 3-16. Normally, a fundamental
mode crystal is used to determine the basic
operating frequency of the oscillator. However,
an overtone mode crystal (which generally'has a '
lower gain) mayal~obe used. When an overtone mode crystal is used, th~ TANK input of
the chip is connected to a parallel'LCnetwork
(AC coupled to ground) to offset the lower gain
of the overtone mode crystal. Regardless of the
type of crystal used,. the crystal frequency is
nine times the desired microprocessor speed
(crystal frequency = 1/tCY x 9). When the
crystal frequency is above 10 megahertz,a
selected capacitor of from 3 to 10 picofarads
The STSTB Signal is generated by gating a highlevel SYNC input from the INS8080A with the
1A internal timing signal from the clock
generator circuit. The STSTB Signal is used to
clock status information onto the status latch
of the INS822811NS8238 System Controller and
Bus Driver.
BUFFER
~------------------------~~12~~
>-------------~
11
>------~ 10
~--------""-'-----------.....,~.!.J
.'
..
..(nLi
~NC 5~----------------__--~~--~::::::j[:J~::r:~--------~7 ~
2'1-----1
RESiN
1------'1--"'"1 D
NOTES:
ii 1----:---'
1. ONLY USED FOR OVERTONE
CRYSTALS.
2. A 3-10 pf CAPACITOR MAY
BE NEEDED WHEN THE CRYSTAL
FREQUENCY IS ABOVE 10 MH~.
RDVIN
Vee
3
l------------------+-~
1-------------------t::<'4IjREADY
Oil---- +5V
VDD~tl2\!
GND~av
I
NS10749
Figure 3-16. INS8224 Functional Block Diagram
3-20
r-tCY~
~1 CLOCK~
~
r--\'--~f
r--\
1
''----------
I
2 UNITS
1
I
,
1
1
1
1
I
!I I I I I \! 1 1 '
cJ>2 CLOCK _____If1: 2 : 3: 4 :5' : 2 :
' - v - " '-..,.-'
5 UNITS 2 UNITS
1 UNIT
Figure 3-17.
,'-----I'
1
fosc
Relative Timing of INSB224 Clock Output Waveforms
A Schmitt Trigger circuit is used in conjunction
with a D-type flip-flop to provide an automatic
system reset and startup upon application of
power as follows. The RESIN input, which is
obtained from the junction of an external RC
network that is connected between Vce and
ground, is routed to the internal Schmitt Trigger
circuit. This circuit converts the slow transition
of the power supply rise into a sharp, clean
edge when its input reaches a predetermined
value.
When this occurs, the succeeding
D-type flip-flop is synchronously reset, thereby
providing the RESET output signal. For manual
system reset, a momentary contact switch that
provides a low (ground) when closed, is also
connected to the RESIN input.
structure of small systems that require only one
basic vector, and an Interrupt Acknowledge
Signal (INTA) for each byte of a multibyte CALL
Instructon.
Advanced 110 Write (I/O W) and
Memory Write (MEM W) Signals are provided
only by the INSB23B chip for large-system timing control. Figure 3-19 is a functional block
diagram of the INSB22B/INSB23B chip.
The bidirectional bus driver is a parallel B-bit,
TRI-STATE circuit that buffers the INSBOBOA
Dy-DO External Data Bus from memory and
input/output devices. The bus driver circuit also
assures that the input/output requirements of
the CPU data bus (3.3 volts minimum input and
1.9 milliamperes maximum drive output) are exceeded, thereby enhancing noise immunity. In
addition, the bus driver circuit has sufficient
output drive capability (up to 10 milliamperes)
for directly connecting a large number of
memory and input/output devices to the system
data bus. The chip gating array (figure 3-20)
controls the operation of the bidirectional bus
driver so that proper bus flow is maintained,
and so that the driver circuit is driven into
the high-impedance state during a DMA data
transfer.
The synchronized READY signal is generated
by a D-type flip-flop, which is clocked by the
20 internal timing signal output of the clock
generator. The D-type flip-flop re-clocks an
asynchronous Ready Input (RYDIN) signal to
provide the synchronous READY Signal to the
INSBOBOA.
A typical INSB224-to-INSBOBOA interconnection
is shown in figure 3-1B.
3.4
I
The status latch uses the "low-level Status
Strobe (STSTB) from the INSB224 Clock
Generator and Driver to store the status word
that is outputted onto the CPU data bus by the
INSBOBOA at the start of each machine cycle.
The latched outputs of the status latch are, in
turn, routed to the chip gating array.
INS822811NS8238 SYSTEM CONTROLLER
AND BUS DRIVER
The INSB22BIINSB23B generates all the read
and write control signals required to directly interface the memory and input/output components of the NBOBO family.
The INSB22B/
INSB23B also provides drive and isolation for
the bidirectional data bus of the INSBOBOA
Microprocessor, a: user-selected single-level interrupt vector (RST7) for use in the interrupt
The gating array generates read and write control signals by gating the status latch outputs
with various control signals from the INSBOBOA
3-21
NST0751
Figure 3-1B. INSB224 to INSBOBOA Interconnection
~icroprocessor.
The read control signals (MEM
R, IJOR, and INTA) .are obtained by gating the
appropriate status latch bit(s) with a high-level
DBIN signal from the INSBOBOA. Similarly, the
write control signals (MEM Wand IJOW) are ob-'
tained by gating theapproPfiate status latch
6it(s) with a low level WR signal from the INSBOBOA. During a DMAdata transfer, the gating
array and bidirectional bus driver are driven to
the high-impedance state by high-level BUSEN
and HLDA inputs. When using a multibyte
CALL as an Interrupt Instruction, thelNSB22BJ
INSB23B generates an INTA pulse for. each of
the three bytes of the instruction, When an in~
terrupt is acknowledged by the INSBOBOA.
For descriptions of the devices required to expand the minimal CPU Group into .one with an
expanded capability refer to the sections listed
below:
• Expanded chip selects (see section 4.4)
• Interrupt expansion (see section 4.7)
• Aqdress expansion (see section 4.3)
For INSBOBOA instruction set, see chapter 11.
3.S_1 DM8131 6-Bit Unified Bus Comparator
The DMB131 compares two 6-bit binary words
and indicates equality by the output going low.
The application shown utilizes the DMB131 to
select a 2K block of memoryJperipheral space
with the INSB2LSOS selecting B blocks of 256
each, within the 2K block.
The INSB22BJINSB23B can be used to insert a
single-level interrupt vector (RST 7) onto the
CPU data bus with a high-level DBIN signal,
when an interrupt is acknowledged by the INSBOBOA. To use this feature of the chip, the INTA
outpu't (pin 23) must be connected to an external12-volt power supply via a 1-kilohm resistor.
A typical INS822BIINSB23B-to-INSBOBOA interconnection is shown in figure 3-20.
Features:
• Low Bus Current Input
• High Bus Ncilselmmunity
• TTL Output
3.S CPU CHIP SET
3.S_2 INS82LSOS One-of-Eight Binary .
Decoder
The I NSBOBOA and its two CPU Group support
devices,. the INSB224 and the I NSB22BII NSB23B,
constitute the minimum components to implemeri!the MICROBUS. The minimum CPU Group
is slJfficient for implementing a minimal system
with only a linear select addressing capability.
The INSB2LS05 decodes one of eight lines, based upon the conditions at the three binary
select inputs and the three enable inputs. It is
designed to be used in high-performance
memory-decoding or data-routing application,
requiring very short propagation delay times.
An illustration of a minimal CPU Group is
shown in figure 3-21. For expanded CPU Group
see figure 2-B, INSBOBO family CPU group to
MICROBUS Configuration .. Refer to appendix
A;B for System Timing Diagram.
Features:
• Three enable inputs simplify cascading
• Schottky clamped for high speed
3-22
----
CPU
DATA
BUS
~
--.~------.---
DO
DBO
0,
DB,
02
DB2
03
DB3
BIDIRECTIONAL
BUS DRIVER
0/1
DB4
05
DB5
Os
DBS
07
SYSTEM
DATA
BUS
DB7
CONTROL
Ie..:>
'"
e..:>,
.J
I
Si'ffi
DJ
::~
HLDA
2
BUsEN
~
v" [i!]
m
GND
I
STATUS
LATCH
j
·1
•: ""
ov
r
~
I
GATING
ARRAY
tr
.@] M'EMR
-I
12!] MEMW
I
:~
27
J-CONTROL
SYSTEM
IIOR
BUS
Ilow
.@]
I
INTA
NS70112
Figure 3-19.
INS822811NS8238 Functional Block Diagram
~
INS8080A
MICROPROCESSOR
10
00
15
13
9
01
17
18
8
02
12
11
7
03
10
9
3
04
6
5
4
Os
19
5
06
21
6
07
8
18
WR'
17
OBIN
4
23
iNTA
21
HLOA
2
24
MEMif
22
26
MeMW
3
080
DB;
OB2
08 3
OB4
18
INS8228/8238
SYSTEM
CONTROLLER
&
8USORIVER'
SYSTEM
DATA
BUS'
085
20
OB8
7
087
"}
iiUsEN
Sffii
1
25
FROM PIN 7
OF OP8224
SYSTEM
CONTROL
BUS
1/0 R
27
iT--Gl
Ax+6-AlI+8
A,B,C
b..
"
Internal BloCk Diagram
Figure 3-22.
Typical MICROBUS Interface
DM8131 6-bit Unified Bus Comparator
vcc~
rc
AtS-AD
YO
GND~
INS82lS05
Ax-AJt.+2
Yl
A,B,C
Gl
Y2
C57 -CSo
'o-vo
ENABLE/ G2A
INPUTS
G28
Y3
~t-
'1'>---
M
I
Gl
C
R
0
B
GZ'
G28
Y4
U
INS8ZLS05
A (1)
S
Y5
A,B,C
SELECT
INPUTS
B
CS15
Y6
(2)
fsa
Y7-YO
G1
C
Y7
(3)
lriternal Block Diagram
Figure 3-23.
F
GZA
628
Typical MICROBUS Interface
INS82LS05 One-of-Eight Binary Decoder
3-26
b-
07-05
04-00
DATA
BUS
BUFFER
(19)
.. CHO
~.:
~
""'-ORQO
16
BIT
MEMR
MEMR
MEMW
MEMW
IIOR
1.1
1
~I
READ}
WRITE
lOGIC
~I
A7-A4
111)
•
~
READY~
16
BIT
CONTROL
lOGIC
AND
r"ODE
II
r
.'",
SET
~DRn2
I CH2
"I
" "'" -t
iiEMR
STB
•
OROI
OACK2
cs
OR02
READY
07·00
AEN
OACKl
OROl
ADST8
DS2
STB
A15·A8
A7-AD
008-001
~DRa3
,
I'
,'I
BI1
115) _ _
....J!L...
•
INS8212
DSI
STB-
13)
MEMW
'EN
CLK
ADDRESS BUS
REG
HlDA
Cs
iiACi<1
RESET
CLK
READY
DROD
I/ow
RESET
A7·AO
DACKO
IIOR
IIOW
CPU
GROUP
I
1----
A3·AD-'
Os
I .f:l~DRQI
I
INS8257
A7·AO
I')
.....!!!!- Vee
1=
~GND
BUS
136)
Te-
15)
MARK . . -
•
Typical MICROBUS Interface
Internal Block Diagram
Figure 3-24.
INS8257 Programmable DMA
Controller
M
I
C
R
0
B
U
S
INTERNAL
BUS
(4·11)
DATA 8US
07·00
{1a.25}
INTERRUPT
REQUEST
REGISTER
DATA
BUS
BUFFER
IRO·IR7
'"'C
PRIORITY
RESOLVER!
REGISTER
I.
INS8Z59
01-00
(17)
INT
{=:
TO
SERVICE
REGISTER
CPU
GROUp
'1'
,..-_:%.._-,
CASCADE
CO~A~~~~~OR
1CWl-ICW2/
INTERRUPT
ACKNOWLEDGE
COUNTER
(121
INTR
Os
AO
INTA
>--SP
07·0n
•
i[jj
WR
IR1·IRO
...
cs
AO
M
I
c
R
AD
a
WR
B
U
S
INTR7·INTRO
....... CASO
(1J)
X
~::;
b..
rI~• • •~I
ICWJ
Internal Block Diagram
Figure 3-25.
~
Single Device Configuration
INS8259 Programmable Interrupt Controller
3-28
r-~
..-...
,.....
MEMORY
Chapter 4
. Designing Series
8000 Microprocessor
Family Systems
...........
INPUT/OUTPUT
.....-.!
M
SERIES BODO
MICROPROCESSOR
"-
I
C
R
L)-
0
B
U
S
TM·
....
PERIPHERAL
CONTROL·
~
COMMUNICAnONS
I""-,
.
~
• Trademark, National Semiconducto( Corporation
c
_.
Designing Series 8000
Microprocessor Family Systems
CD
(J)
CO
::l
::l
CO
en
CD
~.
4.1 INTRODUCTION
CD
(J)
This chapter provides detailed information to
aid the system designer in the design of
INSSOSOA microcomputer systems. Included in
the chapter are the following: CPU group
design, details on interfacing to memory and
peripheral devices, techniques for expanding
interrupts, and a method of implementing a
simple control panel.
outputs. These TTL clock outputs are in turn
capacitively coupled to the clock driver circuit.
The Clock Driver is a two-phase interface circuit
that converts the TTL ¢1 and <1>2 clocks to MOS
level <1>1 and <1>2 clocks. The MOS clocks have a
voltage swing of from 0.6 to 11 volts, and rise
and fall times typically less than 10
nanoseconds into a 20-picofarad capacitive
load. To obtain the required output voltage
swing, the clock driver is biased from the VBB
supply (- 5V) and the VDD supply (+ 12V) via a
simple resistive divider.
A low-resistance
series network is included between each driver
output and the I NSS080A to eliminate any pulse
overshoot.
4.2 CPU GROUP DESIGN
The preferred design approach for the CPU
group is to use the INSSOSOA Microprocessor
with the INSS224 Clock Generator and Driver
and the INSS22S/lNS8238 System Controller
and Bus Driver as shown in figure 4·1. The use
of this approach yields significant benefits in
system timing and decreased component
count. An alternative design approach, which
uses standard TTL components and National
Semiconductor general·purpose peripheral
devices to implement the basic functions of circuits of the two supporting chips is described
below. This design approach achieves operational characteristics that closely approximate
those of the INSS224 and INSS22S/lNSS23S
chips.
4.2.1
The 20-megahertz oscillator also prOVides its
TTL output to the ClK input of a D-type flip-flop
of the Auxiliary Functions circuits. This flipflop, in turn, generates an advanced timing
signal (1A) that is used to clock two D-type
flip-flops associated with the e)1 A timing signal is also gated
with the SYNC signal from the INSSOSOA to
generate a low-level status strobe (STSTB) output. This output can be used as the'latching
signal for the status word that is outputted onto
the 07"00 External Data Bus by the I NSSOSOA at
the first state of each machine cycle.
Clock Generator and Driver DeSign
Figure 4-2 shows the design of the Clock
Generator and Driver using discrete components_
The circuits generate two nonoverlapping timing references (<1>1 and <1>2
clocks) for the internal storage elements and
logic circuits of the INSSOSOA Microprocessor.
(Refer to the INSSOSOA Data Sheet for the levels
and timing relationships of the two reference
clocks.) The circuits also provide auxiliary
functions such as the synchronization of external requests and the generation of the'status
word strobe.
4.2.2
System
Design
Controller and
Bus
Driver
Figure 4-3 shows the design of the System
Controller and Bus Driver using discrete components. The circuits generate the read and
write control signals for memory and input/output devices, and provide buffering of the 07"00
External Data Bus.
The System Controller comprises an eight-bit
latch and associated gating circuits (four NAN 0
gates and an inverter). The latch uses the
status strobe (STSTB), which occurs at the start
of each machine cycle, as the latching signal to
store the status1 and <1>2 clock
4-1
CO
0
0
0
s
Cr
0"'"
"C
a0
(')
CD
(J)
(J)
0
"'"
."
s:u
3
-<
en
-
'<
(J)
CD
3
(J)
..
2
GNO
AO
20
A,
'5V
"..
-5V
A2
..
2.
+12V
A3
INS8080A
MICROPROCESSOR
A.
A'0
A"
1.'
INT
A'2
A'3
16
INTE NABLE
INTE
A,.
A'15
~
WAIT
I
14
TANK
ROYIN
-!
+12V
+5V
~
~
----
-:
HlOA
22
"
',1
00
.2
0,
15
10
\
°2
INS8224
03
CLOCK
GENERATOR
AND
DRIVER
•
1
5
8
GNO
A.
A5
32
A6
33
23
READY
D.
RESET
05
12
"
D.
SYNC
,
0,
ADDRESS BUS
A,
34
A.
35
A.
1
A'0
'0
A"
3,
A'2
3.
A 3
'
3'
A"
36
,.
A'5
17
21
15
osc ~
---!..3
-
'WR
OBIN
~Ir~r
AJ
A5
A6
A2
2.
30
Ag
SYSTEM IN TREQ
2'
31
A,
HOLD
AO
A,
A.
13
SYSTEM OM AREO
25
2.
>1
.1
3
10
15
•
•
,
17
16
12
"
3
,
5
•
13
OBO
OB ,
OB2
•
10
6
OB3
5
DB.
"21
•
INS8228/8238
SYSTEM
CONTROLLER
AND
Blls DRIVER
., 18
..
08.
20
,
DB6
DB,
23'
2.
'5V _ _
2.
GNO~
2~
,.
STATUS STROBE
l
r"'·
INTA}
MEMR
MEM W
CONTROL BUS
25
I/OR
22
BUSEN
2'
"OW
NS10616
Figure 4-1_
Preferred Method of CPU Group Implementation
4-2
WAVEFORMS
~tTTL)
~
---Il~
_
!...-
U
50ns
!fJ2 (TTLI
--l t-- 50n$
50ns --I ~
~)'A(TTLI~
--~-----,~
SYNC
SYNC
o
----------~~r-----
74874
r--I
CLOCK GENERATOR - -
t;il
20MHz
~
__ . ______ _~STSTB
t------------...
",lA (TTL!
.-----l-----ICLK Q
\
WAIT REO
OSCILLATOR
o
O~--_
READY
74S74
elK
330
OMA REO
o
a t----
HOLD
74574
74S04
elK
CLOCK DRIVER
"2V
47~1
OA
OA
t------\l--...
DB
74163
08
DC
,2
CLOCK
GND
NSI0616
Figure 4-2_ System Clock Generator and Driver Using Discrete Components
These control signals are directly' interfaced to
the memory and input/output devices,
by forcing the outputs of each 4-bit bidirectional
IC of the bus driver to the high-impedance state.
The Bus Driver comprises two 4-bit, parallel
bidirectional IC components that buffer the
INS8080A DrDo External Data Bus from
The
memory and input/output devices.
INS8080A data bus has an input requirement of
3.3 volts(minimum)and output drive capacity of
1.9 milliamperes (maximum). The bus driver ensures that these requirements are not only met
but exceeded for enhanced noise immunity. In
small systems with minimum memory and
input/output requirements, buffering of the
07-00 External Da~a Bus may not be required.
4.3
ADDRESSING CONSIDERATIONS AND
TECHNIQUES
The INS8080A has a 16-bit address bus that is
capable of addressing up to 65K bytes of
memory and up to 256 input and 256 output
devices.
In small systems with minimum
memory and input/output requirements, buffering of the A15-AO Address Bus may not be required. However, as memory and input/output
device requirements increase, buffering is
requireo for the bus. This address buffering
function can be implemented by using two National Semiconductor INS8202 TRI-STATE Octal Buffers as shown in figure 4-4. Note that the
system Bus Enable. (BOSEN) signal is connected to the buffers so that they are forced into their high-impedance state during a DMA
data transfer (BUS EN :::: logic 1) or any other
time that bus access is desired, thereby allowing other devices to gain access of the address
As shown in figure 4-3, the Direction Control
(OlEN) and Chip Select (CS) ipputs of the Bus
Driver are connected to the DBIN output of the
INS8080A and the system Bus Enable (BUSEN),
respectively. The DBIN signal ensures that the
proper data flow is maintained on the data bus.
The BUSEN is an asynchronous signal that
allows other devices to gain access of the data
busduringaDMAdatatransfer(BUSEN:::: logic1)
4-3
~BUSDAIVER
~
~
10
o
INS82161
INsa226
~
a
D2
12
~
7
D3
DBO
ri:-
9
0,
"
3
.
10
13
OlEN
1S
t
•
cs
•
DBl
DB2
DB3
~1
BUSEN
SYSTEM
DATA BUS
(SEE NOTE)
D.
D5
r+
3
,
5
DO
07
0
INsa2l61
INSB226
1+
0
OlEN
"t
MICROPROCESSOR
10
13
12
INS8080A
-
7
191NP
9
21 MEMR
T
-
1
~
la
SYSTEM
CONTROL
aus
150UT
20
.l.Q..!:!.hI.L
22
~
~TST8~
"
1
INS8212
10
OBIN
BUSEN
~
.
DB5
DBO
DB7
.1
"4INTA
5
DB'
cs
~ SYSTEMCDNTRO"ER
3
--
3
r-+r-T
.~
V"
~
Y>
t:rFNOTE:
iVA la
THE INS8216 J~S A NON-INVERTING
DEVICEANDT HE lNS8226IS AN
INVERTING DE VICE
NS1D617
Figure 4-3. System Controller and Bus Driver Using Discrete Components
of the addressing techniques. In linear select, a
singular address bus bit is assigned as the exclusive enable for a specified input/output
device. Using this method limits the number of
input/output devices that can be addressed but
eliminates the need for extra decoders. In
Small system design, this is an important consideration.
bus. As mentioned above, up to 65K bytes of
memory and up to 256 input and 256 output
devices can be directly addressed via the
A15-AO Address Bus of the I NS8080A. The
INS8080A microcomputer system can be configured so that memory and input/output
devices are either treated separately (isolated
input/output) or as a single memory array
(memory mapped input/output) as described
below. The mapping for the isolated input/output and memory mapped input/output addressing techniques is shown in figure 4-ti. With
both of these addressing techniques, the most
common method of addressing memory or input/output devices is to decode some of the address bus bits as "chip selects" (using a device
such as the National Semiconductor
INS82LS05 to enable the addressed memory or
the input/output device). The linear select
method (refer to 4.5.1) is another way of· addressing the input/output devices using either
When the INS8080A system is configured for
isolated input/output addressing, the memory
address space is separated from the input/output devices address space by using system
control signals for the input/output architecture
as shown in figure 4-6. Also, with isolated input/output addressing, the input/output devices
communicate only with the Accumulator using
the IN and OUT Instructions. Thus, since the
memory address space is not affected by input/output device addressing, the full address
space of 65Kbytes.is available for memory.
4-4
~25
2
3
26
4
5
27
6
7
29
8
30
12
11
31
14
13
A5
32
16
15
A6
33
18
Al
A2
A3
A4
A5
A6
A7
A8
Ala
All
A12
A13
A14
A15
Al
A2
9
INSS202
A3
A4
17
A7
G2
CIT
INSB080A
MICROPROCESSOR
A9
AO
~9
1+
SYSTEM
f- ADDRESS
BUS
34
2
3
35
4
5
1
6
7
40
8
37
12
11
38
14
13
39
16
15
36
18
AS
A9
Al0
9
INSS202
All
A12
A13
A14
17
1
1+
aUSEN
A15
G2
Gi"
9
NS70678
Figure 4-4. Address Buffer Design Using INS8202 Devices
0
J
t
65K
MEMORY
ADDRESS SPACE
r
JJ
0
256
INPUT/OUTPUT
DEVICES
ADDRESS SPACE
A. ISOLATED INPUT/OUTPUT
0
32K
65K
INPUT/OUTPUT
DEVICES
ADDRESS SPACE
MEMORY
ADDRESS SPACE
B. MEMORY MAPPED INPUT/OUTPUT
NS10619
Figure 4-5.
Mapping for Isolated Input/Output and Memory Mapped Input/Output Techniques
4-5
INS8228/INS8238
SYSTEM CONTROLLER
MEM R
--MEMW
I/O R
I/OW
24
.. }
26
TO
MEMORY
ARRAY
25
}
27
TO
INPUT/OUTPUT
DEVICES
NSI0620
Figure 4-6. System Control Signals for Isolated Input/Output Addressing
family interfaces with standard semiconductor
memory components (and input/output
devices) via the MICROBUS. Atypical interface
to a memory array having 6K bytes of ROM
storage and 512 bytes of RAM storage is shown
in figure 4-8. This typical memory interface is
suitable for almost any size of memory
array.However, in larger systems, buffers may
be required for driving the three buses and
decoders may be required for generating the
chip select signals for the memory array (and input/output devices).
.
When the INS8080A system is configured for
memory mapped input/output addressing, an
area of the memory array is assigned to the input/output devices by using system control
signals for the input/output architecture as
shown in figure 4-7. In this configuration, new
input/output control signals (110 R (MM) and 170
W (MM)) are generated by gating the fiifEMR and
MEMW signals with most significant address
bit A15' (Since these new input/output signals
connect in exactly the same manner as the
corresponding signals of the isolated input/output configuration, the system bus characteristics are unaltered). Address bit A15 is used
because it allows up to 32K bytes of memory
addressing, and because it is easier to control
with software. However, any other address bit
may be used for this gating function. When bit
A15 is low, the memory address space is active
and when bit A15 is high, the input/output
devices address space is active.
As shown in figure 4-8, the interfacing to the
three National Semiconductor INS8316 ROMs
is quite straightforward. The DO-D70utput lines
of the ROMs are connected to the bidirectional
Data Bus; the AO·A1Q address inputs are connected to corresponding bits of the Address
Bus; the CS2 and csa chip select inputs are
connected to the A11 and A12 bits (most significant) of the Address Bus; and the CS1 chip
select input of the ROMs is connected to the inverted MEM R signal of the Control Bus. During
a FETCH or MEMORY READ machine cycle, the
CPU group may output an address in the ROM
address space of the memory array. When this
occurs, the data stored at the addressed ROM
location are then gated onto the External Data
Bus with the MEM R signal. In this way, data
are read from the ROMs in the INS8080A
microprocessor system.
With 'memory mapped input/output addressing,
all of the instructions that can be used to
manipulate memory locations (for example,
MOV M, r; LDA; STA; LHLD; et cetera) can also
be used for the input/output devices. These
devices are still considered addressed
"PORTS" but instead of the Accumulator being
the only data transfer medium for the
peripherals, any of the internal registers of the
INS8080A can also be used for this purpose.
Thus, memory mapped input/output addressing
is suited for small systems that require high
throughput and have less than 32K bytes of
memory.
The interfacing to the four National Semiconductor INS8111A-4 static RAMs is also straightforward. The 1101-1104 common input/output
lines of the RAMs are connected to corresponding bits of the bidirectional Data Bus; the AO-A;
address bits are connected to corresponding
bits of the Address Bus; and the R/W and 00 in-
4.4 INTERFACING TO MEMORY
The CPU group of the INS8080A microprocessor
4-6
INS 8228/INS8238
SYSTEM CONTROLLER
}
~--------~~--------------------------------~
}
NOT
USED
I/OR(MM)
TO
MEMORY
ARRAY
} ~~PUT/
OUTPUT
10-1!_O_W-,-(M_M-,-l-i~
DEV ICES
NSI0621
Figure 4-7. System Control Signals for Memory Mapped Input/Output Addressing
r-
"
INS8111A·4
MmR
00
MEMW
RIW
Al3
eEl
CEZ
Al.
01
04
A7
AD
-#2
1104 1101
A1
AD
,
1m:
#2
1900
RAM
"
MEMR
1800
M
MEMW
17FF
I
Al3
#3
1000
ROM
RAM
#1
18FF
#2
0800
C
R
0
B
"
S
00
#2
r-
R/W
CE1
.14
ill
03 DO
A7
AD
'"
A7
07FF
"
INS8111A·4
'01
AD
0000
MEMORY MAPPING
MEMR
A11
C5,2
A12
01
"
INS8316A
C51
-"
00
07
00
ROM
A10 . AD
AlO
Figure 4-8.
AD
I
Typical Memory Interface
4·7
~
CS3
puts of the RAMs are connected to the MEM W
and MEM R(orDBIN)signals, respectively,of1the
Control Bus. During a FETCH, MEMORY READ,
or STACK READ machine cycle, the CPU group
reads data from the RAMs in exactly the same
manner as described above for the ROMs. Our·
ing a MEMORY WRITE or STACK WRITE
machine cycle, the CPU group outputs an ad·
dress in the RAM address space of the memory
array. When this occurs, the data to be written
into memory are then strobed into the address·
ed RAM location with a low·level MEM W
signal. In these ways, data are read from and
written into RAMs in the INS8080A micro·
processor system.
describe the unique characteristics of dynamic
RAMs which must be considered in a memory
system design.
Dynamic RAMs versus Static RAMs
The basic difference between dynami,c and
static RAMs IS the way they store data. The
static RAM uses a flip·flop to store a bit, while
the dynamic RAM uses a capacitor to store a
bit. (See figure 4·9.)
WORD LINE
Voo
The memory array of figure 4·8 includes ROMs
(INS8316A) and RAMs (INS8111A·4) that have an
access time of 450 nanoseconds (maximum).
When the INS8080A microprocessor is oper·
ated from a clock generator with atCY of 500
nanoseconds, the required memory access
time is from 450 to 550 nanoseconds. Therefore,
when slower memory components are used in
the system, the INS8080A Microprocessor must
contain a synchronization provision to allow the
memory components to request the wait state
(TW)' (The actual number of TW states to be in·
serted is determined by external logic that is
user designed.) This provision can be im·
plemented for any slow memory (RAM or ROM)
by a simple logic control'of the READY input of
the INS8080A as follows. When the addressed
slower memory receives a MEM R or MEM W
signal, it places a low·level on the READY line
'of the microprocessor, causing the INS8080A
to enter the WAIT sequence (refer to 3.2.2.2).
After the slower memory has had time to res·
pond, it places a high·level on the READY line,
thereby allowing completion of the instruction
cycle.
Static RAM Cell
WORD LINE
.
"'~
~,-""
DATA
-::-
Dynamic RAM Cell
Figure 4·9,
Cell Comparison
It is their respective cell designs that give each
RAM its advantages over the other. Let's com·
pare the RAMs for ease of use, power dissipa·.
tion, die size, and price.
Ease of Use: The static RAM is easier to use
because no refresh logiC is required. In addi·
tion, static RAM control signals tend to be
easier to generate because cycling is usually
unnecessary.
4.5 DYNAMIC MEMORY
4.5.1 Introduction
Many new memory system designs are using
dynamic RAMs, particularly in large memory
systems due to the availability of 16K RAM
chips.
Power Dissipation: . The dynamic RAM draws
less power. The static RAM draws power con·
tinuously to sustain its flip·flops, while the
dynamic RAM draws minimal power (1 to 2mA)
between cycles. With continuous cycling, the
dynamic RAM draws about as much power as
the static. However, in a large memory system,
dynamic RAMs save total system power since
only one bank of RAMs is ever accessed during
a memory .cycle. All other banks draw minimal
current except during refresh cyc'les. The duty
cycle for refresh is approximately 1V2 to 3%.
The key to success in a dynamic RAM system,
or any other system for that matter, is margin. A
system designed to maximize power supply
and timing margins will be reliable and easy to
manufacture.
'
In this section we shall discuss RAM. chip
characteristics, power supply and control
signal distribution on PC boards, and control
logic implementation suggestions.
Die Size: Dynamic RAMs tend to be smaller.
Due to the difference in cell designs, the die
size of the dynamic RAM is often at least 20%
smaller than that of a comparable static RAM
from the same manufacturer.
4.5.2 Ram Chip Characteristics
For reference we shall compare dynamic and
static RAMs at the chip level. Then we shall
4·8
Price: Because of smaller die sizes and much
larger production runs, dynamic RAMs should
always remain considerably cheaper than comparable static RAMs. In addition, dynamic
RAMs save money in larger systems. Less chip
power means smaller and cheaper power supplies. Smaller supplies mean a further saving in
reduced cooling requirements. In general, the
larger the memory system, the greater the savings by using dynamics.
4.5.3
Memory Subsystem Design
Considerations
Some memory board designs are easy to
manufacture, while others, functionally iden·
tical, have low manufacturing yields seemingly
due to the many "bad" chips. The difference
between them is usually the amount of margin
designed into each system. Power supply and
timing margins are both critical, and as the
margins go to zero or negative, the amount of
"soft" errors goes.up. (A chip has a "hard" error if a location consistently canno(be written
and read back properly. It has a "soft" error if it
only occasionally fails.)
,
Dynamic RAMs
Refresh: Since charge leaks off the storage
capacitors, it must be replenished periodically
in order for a dynamic RAM chip to retain its
data. The charge in anyone cell is replenished,
or refreshed, every time that cell is accessed for
a read or a write. At the same time, all the other
cells in the same row are also refreshed. For
that reason the entire RAM chip can be refreshed by dOing only 64 cycles for 4K RAM, (a 16K
RAM needs 128 cycles) in 2ms while sequencing through all the row addresses. The bit pattern presented to the column addresses does
not matter. However, the setup and hold times
must still be met. Unstable column addresses
during refresh will cause data loss.
On careful analysis, "soft" errors usually occur
during a memory cycle in which some system
parameter has gone out of spec. Since the
RAM chips themselves have variations in their
margins, replacing the offending RAM with one
that. has a greater margin in the out·of-spec
parameter seems to cure the problem. This
results in a large pile of "bad" RAMs. However,
the real solution to this type of problem is in a
careful system design and board layout in the
beginning.
Power Distribution
The hardware required for refresh amounts to a
6 or 7-bit counter for the refresh addresses,
some way to multiplex the counter onto the
RAM row address lines, a timer to signal when a
refresh should be done, and the miscellaneous
gating needed to couple into the usual read/write
logic.
By far the single most important aspect of a
successful RAM system is good power distribu·
tion consistingdf carefully designed decoupl·
ing and power gridding. The importance of
good power distribution cannot be overemphasized.
Figure 4·10 shows CE, IDO current waveform for
a typical dynamic RAM chip during a memory
cycle.
In some systems no extra refresh logic is needed: For example, in CRT systems normal operation sequences through all the row addresses
in less than a 2ms refresh period. This will be
true only if the row address bits on the RAM
chip are driven from ,the least significant address bits of the system. As a rule, this is good
practice in all systems. By placing the most
active system address bits on the RAM row ad·
dresses, normal system operation will automatically refresh the bulk of the RAM.
1~··2~0",~1
CHIP
ENABLE
Cycling: One of the key functional differences
between static and dynamic RAMs is the fact
that dynamic RAMs must run through a cycle in
order to read or write. Aborting the cycle by
removing the chip enable too early or by trying
to start a second cycle too soon after the first
will probably cause data loss. Minimum chip
enable on and off times must be observed.
100
~
\'--,-
:~.'f\-Jt
0----1
!..
_ _ _ _ 2_4mA
Summary
Static RAMs are easier to use. Dynamic RAMs
are cheaper, use less power, must be refreshed,
and must be cycled.
Figure 4·10.
4-9
'100 Current Waveform
First, place the actljal driver chip nearthe RAM
array it is driving, making the chip enable run
short and direct.
Second, put a damping
resistor near the driver. Do this for ,either TTL
level or 12 voltchip enables. Select the value of
this resi,stor to, give the best clock waveform at
the RAM chips. Its value will probably be between 10 and 5Hl Figure 4-11 shows the commonly used arrangements.
At the beginning and end ,of chip enable, each
RAM chip draws 50 to 100mA current spikes
with rise times of 20ns. In additon, each RAM
package draws a 20 to 40mA DC current lasting
for the duration of chip enable. The,power
distribution system must supply these cwrents
while the voltages at the RAMs remi;lin constant. If there are a number ,of rows of RAMs, all
power supply traces to all RAMs should be run
both vertically and horizontally throughou~ the
array. Providing multiple paths through the array redljces the effectjve ind.uctance of the
power distribution system.
Power Distribution Rules:
,1. It is the single most important aspect of a
, good RAM board layout'.
,',
:'
'2. Use plenty of decoupling. The decoupling
caps not only reduce voltage spikes, but
also provide mos,t of the RAM power d,l,Jring the cycling. Layout the board for a
0.1iF capacitor per power supply per RAM
chip (up to three capacitors per chip). As
production history accumulates,it may be
pOl!lsibleto omit half the
capacitors.
However, layout the board for one per supply per chip. Use ,50 to 200jn
• Single bit I/O operations with single
instruction
• Reduces system package count
• Independent operation of RAM and I/O
• MICROBUS™Compatible (see figure 5-7
for MICROBUS connection)
5.4 DYNAMIC MEMORY
Many new memory system designs are using
dynamic RAMs, particulary in large memory
systems, or systems using dedicated memory
such as CRT displays.
5.6 OTHER MEMORY COMPONENTS
Refresh requirements make dynamic RAMs
slightly harder to use than static RAMs. The
designer is paid back for his efforts however, by
reduced overall system cost using dynamic
RAMs in three ways:
•
•
•
This section describes other memory components. (Refer to appendix D for the data
sheets.)
5.6.1
Dynamic RAMs tend to be cheaper than
static RAMs of the same size.
Dynamic RAMs use less power, especially in a large array.
Power supplies are cheaper, because of
the reduced power requirements and
therefore cooling requirements are
reduced, allowing a further savjng.
INS8101A-4 IK (256 x 4) Static RAM With
Separate 1/0
General Description
The National INS8101A-4 is a 256 word by 4-bit
static random acess memory element
fabricated using N-channel .enhancement
mode Silicon Gate technology. Static storage
cells eliminate the need for refresh and the additional peripheral circuitry associated with
refresh. The data is read out nondestructively
and has the same polarity as the input data.
A sample of dynamic memory devices available
is referenced in section 5.6.6 and 5.6.7. (See
section 4.5 for discussion covering the design
of memory systems).
The INS8101A-4 is directly TTL compatible in
all respects: inputs, outputs, and a single + 5V
supply. Two chip-enables allow easy selection
of an individual package when outputs are ORtied. An output disable Is provided so that data
inputs and outputs can be tied for common I/O
systems. The features· of this memory device
Can be combined to make a low cost, high performance, and easy to manufacture memory
system.
5.5 INS8154 128-BY-8-BIT RAM 1/0
The INS8154 provides two 8-bit peripheral inter·
face inputloutput ports and 1024 bits of RAM,
organized as 128 x 8 bits of read/write memory
for data storage.
The I/O portion consists of two peripheral ports
of eight bits each. Each port may be read or
written in a parallel (8-bit byte) mode.
National's silicon gate technology also provides protection against contamination, and
permits the use of low cost Epoxy B packaging.
In addition to basic 1/0, one of the ports, port A,
may be programmed to operate in several types
of strobed mode with handshake. Strobed
mode together with optional interrupt operation
permit both high speed parallel data transfers
and interface to a wide variety of peripherals
with no external logic.
Features
•
•
•
•
Each bit of each port may be defined as an input
or an output and each bit may be set, cleared, or
read with a single instruction.
5-5
Organization 256 Words by 4 Bits
Access time - 0.5 101.0"s Max.
Single + 5V Supply Voltage
Directly TTL Compatible - All inputs and
Outputs
~
NRST~
ct.ili~
a..
CS1
M/iO)~
(38)
NWOS~
NRD S........
READ
WRITE·
CONTROL
LOGIC
...
~
PORT
. A
.....
OUTPUT
DEFINITION
REGISTER
.A
t
r
MODE
DEFINITION
REGISTER &
HANDSHAKE
LOGIC
,
"
.............
..,..
DATA.
BUS
BUFFER
BIT
OPERATIONS
AD6 -
(32-2~)
ADOii
.....
., .....
.....
"
.....
...
....
..,.
OUTPUT
DEFINITION
REGISTER
B
....,. .... ....,.
...
PORT
B
~INTFi
I+--t
+5V
t-
_ _. . ._ _ _ _ _ _ _ _ _ _• •
NOTE: APPLICABLE PINOUT NUMBERS
ARE INCLUDED WITHIN
PARENTHESES.
Figure 5-6. INS8154 Block Diagram
...... A6-AO
01- 001
ADDRESS
BUS
DATA
BUS
CPU
GROUP
.
CONTROL
BUS
M
Ia4
_'I'r-
I
C
R CS
B MEMR
U
S MEMW
RESET
INRI
0
"
~J9, 1- 7)
PB7-PB o
128 X 8 RAM
"
t
(16-f9, 21-24)
PA7-P AO.
. r"'""'"
i
(8-15)
DB7-DBO "If
I+--t
-
Ab6-AOO
DBI-DBO
MJjij
PORTA BUS
CSI
CSO
INSBI54
. PORT B BUS
NRDS
NWDS
NRST
INTR
NOTE
The ,NTR signal becomes active only in the
strobed mode wben a data transaction has
occurred.
Figure 5-7. INS8154 MICROBUS Connection
5-6
II
4
(40)
(20)
VCC
GND
•
The INS8111A-4 is directly TTL in all respects:
inputs, outputs, and a single + 5V supply. The
two Chip-enables allow easy selection of an individual package when out-puts are OR-tied.
The features of this memory device can be combined to make a low cost, high performance,
and easy to manufacture memory system.
Static MOS - No Clocks or Refreshing
Required
Simple Memory Expansion - Chip Enable
Input
Low Cost Packaging - 22 Pin Epoxy B
Dual-In-Line Configuration
Low Power - Typically 150 mW
Tri-State® Output - OR-Tie Capability
Output Disable Provided for Ease of Use
in Common Data Bus Systems
•
•
•
•
•
5.6.2
National's silicon gate technology provides excellent. protection against contamination and
permits the use of low cost Epoxy B packaging.
Features
INSS111A-4 1K (256 x 4) RAM With Com·
man 1/0
•
•
•
•
General Description
The NationallNS8111A-4 is a 256 by 4 static random access memory element fabricated using
N-channel enhancement mode Silicon Gate
technology. Static storage cells eliminate the
need for refresh and the peripheral circuitry
associated with refresh. The data is read out
nondestructively and has the same polarity as
the input data. Common Data Input/Output
pins are provide,d.
•
•
•
•
•
•
Organization 256 Words by 4 Bits
Common Data Input and Output
Single + 5V Supply Voltage
Directly TTL Compatible - All Inputs and
Outputs
Static MOS - No Clocks or Refreshing
Required
Access Time - 0.5 to 1.0p.s Max.
Simple Memory Expansion - Chip Enable
Input
Low Cost Packaging - 18 Pin Epoxy B
Dual-In-Line Configuration
Low Power - Typically 150 mW
Tri-State® Output - OR·Tie Capability
Block and Connection Diagrams (INS8101A-4)
-E..ovcc
AO
22
A3
+-.!o GNO
21
A2
Vee
A4
A'
20
AI
CELL ARRAY
ROW
SELECT
A2
RIW
32 ROWS
32 COLUMNS'
10
AO
CEI
A3
1B
AS
17
AS
00,
COLUMN 1/0 CIRCUITS
002
COLUMN SElECT
01,
01,
"
16
Al
003
'4
10
13
11
IZ
01 3
A6
00,
Al
OIZ
01, '5
PIN NAMES
rn
(15)
(10)
01 1 01 4
AO A7
A/W l161
R/W
GEl CE2
00
0°1 0°4
00
003
13
AS
ffi
00 4
01 4
01,
INPUT
DATA
CONTROL
eEZ
15
GNO
00,
01 3
00
INS8101A 4
A4
Vee
19>
5-7
DATA INPUT
ADDRESS INPUTS
READ/WRITE INPUT
CHIP ENABLE
OUTPUT DISABLE
DATA OUTPUT
POWER (+5V)
OOz
Switching Time Waveforms (INS8101A-4)
WRITE CYCLE (2)
READ CYCLE (RIW ='"1")
(3)'--+--"'\
00 (COMMON 110)
Note 1: tOF is with respect to the trailing edge of CE1, CE2, or 00, whichever occurs first.
Note 2: During the write cycle, 00 is a logical 1 for commOn 1/0 and "don't care" for separate
1/0 operation.
.
Note 3: 00 should be tied low for separate 1/0 operation.
Switching Time Waveforms (INS8111A·4).
WRITE CYCLE
~----~---IWCY'----------~
READ CYCLE (R/W = '"1';)
Note 1: tOF is with respect to the trailing edge of CE1, CE2, or 00, whichever occurs first.
5·8
Block and Connection Diagrams (INS8111A-4)
~vcc
A3
...-...!o GND
A2
18
VCC
2
17
A4
A1
3
16
R/W
AJ
AO
4
15
CE1
A4
A5
5
14
1/°4
A6
6
13
1/°3
A7
7
12
11°2
GND
8
11
110 1
00
9
10
CE2
AO
A1
CelL ARRAY
32 ROWS
32 COLUMNS
ROW
SHECT
A1
COLUMN 110 CIRCUITS
COLUMN SELECT
1/01
INPUT
DATA
CONTROL
1102
I/O 3
A5
A6
A7
PIN NAMES
1/04
ADDRESS INPUTS
OUTPUT DISABLE
READ/WRITE INPUT
CHIP ENABLE 1
CHIP ENABLE 2
DATA INPUT/OUTPUT
AOA?
00
R/W
GEl
en
en
RiW
(15)
CE2
(101
11°1 1/°4
{l61
rc
A7-AO
INSB111A-4
A7-AO
00 (9) ~
03-00
1/04-1/01
MEMR
M
Truth Table
OD eEl
eE2
R/W
MEMW
MY
I
DIN DOUT
X
X
H
X
X
Hi-Z
X
l
l
l
l
l
X
l
l
l
H
l
l
l
H
H
X
X
H
X
X
X
X
X
X
X
H
DO
DOUT
MODE
ff1
C
Not selected
Write "0"
B
A7-AO
..
07-04
.
U
Write "I"
Read
S
Hi-Z
Hi-Z
,.
...
MEMR
5-9
INSBlllA-4
A7-AO
1/04-1/01
DO
MEMW
tA.-
CE 2
.~
ts
R
0
Rlii
ts
ff1
I
CE 2
.~
5.6.3 The INS8102A 1 K (1024 x 1) Static RAM
General Description
In addition to the INS8102A, a low power version, the INS8102Al, is also available. This
selection offers a maximum operating current
of 33 mA and a guaranteed standby mode down
to a power supply voltage of 1.5V.
The INS8102A family of high speed 1024 x 1·bit
static random access read/write memories are
manufactured using N-channel depletion-mode
silicon gate technology. Static storage cells
eliminate the need for clocks or refresh circuitry and the resultant cost associated with
them.
Features
low threshold silicon gate N-channel
technology allows complete DTI,./TTl compatibility of all inputs and outputs as well as a
single 5V supply. The separate chip enable input (CE) controlling the TRI-STATE® output
allows easy memory expansion by OR-tying individual devices to a data bus. Data in and data
out have the same polarity.
•
•
.,
•
•
•
Single 5V Supply
All Inputs and Outputs Directly DTL/TTl
Compatible
Static Operation- No Clocks or Refresh
TRI-STA TE Output for Bus Interface
All Inputs Protected Against Static
Charge
Access Time Down to 250 ns
Block Diagram
Connection Diagram
Dual-In-Line Package
AO
16
A6
Al
CElL
ARRAY
32 ROWS
32 COLUMNS
ROW
SELECTOR
A2
A7
A5
..,.!..o GNO
R/W
A3
Al
12 DATA OUT
A2
A4
11 DATA IN
A3,
lD
R/W
OATA
OUT
A4
VCC
AD
GNO
TOP VIEW'
CE
A5
A6
A7
AS
A9
logic Symbol
Truth Table
AD
Al
R!W
DIN
H
X
X
Hi-Z
Not selected
L
L
L
L
Write "0"
L
L
H
H
Write "1"
A7
Read
AS
L
H
X
DOUT
DOUT
DIN
A2
CE
MODE
AJ
A4
A5
A6
A9
5-10
°OUT
RiW
CE
Switching Time Waveforms
VIH
CD
ADDRESS
VIL
VIH
CHIP
ENABLE
VIL
VOH
DATA
OUT
VOL
FIGURE 1. Read Cycle
r-----------twc----------~
ADDRESS
1-------- tcw - - - - - I
VIH---'
READ/
WRITE VIL - -_ _ ' - _ _ _ _ _ _ _ _J
DATA
IN
DATA STABLE
FIGURE 2. Write Cycle
, NoteG);
Note@;
Note@:
Note@) :
Input reference level for timing is 1 ,5V.
VOH = 2V is reference level for output high,
VOL
=
0,8V is reference .level for output low,
Input rise and fall times are 10 ns,
Standby Waveforms (lNS8102AL)
VCC - - -....
CE
L5V
1.5V sVpD s 4.75V
1.5V s VpD s C'E s 2v
When: 2V s VpD s VCC MAX
CE must be ~V minimum.
-::.:..,f----''-------
~-------------~----
5-11
5.6.4 MM2114 4K (1024
x 4)
Static RAM
General Description
National's silicon gate technology provides excellent protection against contamination and
permits the use of l.ow cost Epoxy B packaging.
The National MM2114 is a 1024 by 4 static. ran.
dom access m!lmory element fabricated using
N-channel enhancement mode Silicon Gate
technology. Static storage cells eliminate the
need for refresh and the peripheral circuitry
associated with refresh. The data is read out
nondestructively and has the same polarity as
the input data. Common Data Input/Output
pins are provided. No address setup times are
required.
Features
•
•
•
•
The 2114 is directly TTL compatible in all
respects: inputs, outputs, and a single+5V
supply. The Chip select allows easy selection
of an individual package when outputs are ORtied. The features of this memory device can be
combined to make a low cost, high performance and easy to manufacture memory
system.
•
•
•
•
•
Organization 1024 Words by 4 Bits
Common Data Input and Output
Single + 5V Supply Voltage
Directly TTL Compatible - All Inputs and
Outputs
Static MOS - No Clocks or Refreshing
Required
Identical Cycle and Access Time
Simple Memory Expansion - Chip Select
Input
Low Cost Packaging - 18 Pin Epoxy B
Dual-In-Line Configuration
Tri~State Output - OR-Tie Capability
A6
AJ
A4
.......,!!..o,vcc
J
18
Vee
A5
2
17
A7
A4
3
16
AS
A3
4
15
Ag
Ao
5
14
1/0 1
A1
6
13
1/0 2
A2
7
12
1/°3
es
S
11
1/°4
9
10
R/W
....--!o GNO
AS
ROW
SELECT
CHL ARRAY
64 ROWS
64 COLUMNS
A6
A7
AS
17
16
liD 1
1/02
I/O J
1104
11
GND
11
PIN NAMES
CS
R1W
10
,5-12
AO·Ag'
ADDRESS INPUTS
RIW
,READ/WRITE INPUT
cs
CHIP SELECT
11°1'11°4
DATA INPUT/OUTPUT
Switching Time Waveforms
READ CYCLE (RiVi
="1")
~-----------------tRC------------------~
~--------------tA----------------~
DOUT------------------------------------~~
~I----~
NOTES:
1. A Read occurs during the overlap of a low CS and a high RI'W
2. A Write occurs during the overlap of a low l!S and a low RlW
3. If the CS low transition occurs simultaneously with the R/W Low
transition, the output buffers remain in a high impedance state.
4.R/W must be high during all address transitions.
WRITE CYCLE
~-------------------twC:------------------~~
~-----------tw'----------~~
R/W
OOUT~~~~~~~~~~----~--------r_----------------tow -~-----~- tDH
5-13
5.6.5 MM5257 4096 x 1 Static RandomAccess
Memory
Features
General Description
The MM5257 is a 4096 word by 1·bit static ran·
dom access memory fabricated using
N-channel silicon-gate technology. All internal
circuit~ arefully static and therefore ~Elquire no
clocks or refreshing for operation. The data is
re.ad out nondestructively and has the same
polarity as the input data.
•
•
•
•
•
•
•
•
The separate chip enable input (CE) controlling
the TRI-ST ATE® output allows easy memory
expansion by OR-tying individual devices to a
data bus.
All Inputs and Outputs Directly TTL
Compatible
Static Operation - No Clocks or
Refreshing Required
.
Low Power - 200 mW Typical'
High Speed - 250 ns Typical
TRI-STATE Output for Bus Interface
Separate Data In and Data Out Pins
Single + 5V Supply
Standard 18-Pin Dual-in-Line Package
The output is held in a high impedance state
during write to ~implify common I/O applications.
Connection Diagram
Logic Symbol
Dual-In-Line Package
18
AD
A1
VCC
01
A2
A3
A4
A5
A6
A7
AS
A9
A1D
01
DO
A11
CE
TOP VIEW
Truth Table
- MODE
CE
WE
01
H
X
X
DOUT
Hi-Z
Not Selected
L
L
H
Hi-Z
Write 1
L
L
L
Hi-Z
Write 0
L
H
X
DOUT
Read
5-14
WE
Functional Description
Two pins control the operation of the MM5257.
Chip Enable (GE) enables write and read operations and controls TRI-STATING of the dataoutput buffer. Write Enable (WE) chooses between READ and WRITE modes and also control
output TRI-STATING. The truth table details
the states produced by combinations of the CE
and WE controls.
Iy during the time both CE and WE are low.
Minimum write-pulse width, twP, refers to this
simultaneous low region. Data set-up and hold
times are measured with respect to whichever
control first rises. Successive write operations
may be performed with CE continously held
low. WE then is used to terminate WRITE between address changes. Alternatively, WE may
be held low for successive WRITES and CE used for WRITE interruption between address
change.
READ-cycle timing is shown in the section on
Switching Time Waveforms. WE is kept high.
Independent of CE, any change in address code
causes new data to be fetched and brought to
the output buffer. CE must be low, however, for
the output buffer to be enabled and transfer the
data to the output pin.
In any event, either WE or CE (or both) must be
high during address transitions to prevent er'
roneous WRITE.
Address access time, tA, is the time required
for an address change to produce new data at
the output pin, assuming CE has enabled the
output buffer prior to data arrival. Chip Enableto-output delay, tco, is the time required for
CE to enable the output buffer and transfer
previously fetched data to the output pin.
Operation with CE continously held low is permissible.
Stand-by operation allows data to be maintained with approximately 50% less operating current. The 2 requirements to guarantee data
retention are: a) the power supply voJt~ must
meet the condition VCC~ 1.5V, and b) CE must
be controlled; to disable the chip prior to reducing VCC, to keep it disabled during the time
VCC is reduced, and to maintain the disabled
state long enough after VCC is increased to
normal for the chip' to recover. These requirements are shown by the stand-by
waveforms and characteristics.
WRITE-cycle timing is shown in the section on
Switching Time Waveforms. Writing occursonBlock Diagram
18
,+-0 Vec
AZ
(LSBI
9'
+-OGNO
A3
AU
CELL ARRAY
64 ROWS
64 COLUMNS
ROW SELECT
1 Of 64
Al
A6
COLUMN 1/0 CIRCUITS
00
COLUMN SELECT
""""_--1
REAO/WRITE
CONTROL
All
(MSB)
A1D
5-15
A9
A8
A5
A4
(LSBI
Switching Time Waveforms
. Read Cycle
ADDRESSES V'I{
=:::~~y-:--"';"--:--------'II
V,L
==:;F1'----.:.........,--.:......:..--....;t
WRITE ENABLE
VIH~~~~~-------~--------:--r-t-----------~~~~~~~~
'(NOTE 31
V,L
CHfPEPofA8LE
V,H
==========~~--------~:.-.::....:.+-+~-,t"-----:----:....,.-
V,L
---------:c~_r.--------
DATA OUT
.......-W../
-
-- -
-OPEN- - -
-"- -OPEN- - - - -
Write Cycle
ADDRESSES'
V,H
V,L
twp (NOT~
CHIP ENABLE
(NOTE 51
V,H
WRITE ENABLE
(NOTE 51
V,H
DATA IN
V,L
V,L
V,H
V,L
DATA OUT
2.0
2.
Note 3: WE is high during a read cycle (WE
V'H(M'NII.
Note 4: twp defines the period yvhen both CE and
and tWR are referenced to the earlier of CE
~~
- - OPEN-
0.8
cr
wt are
orWE going
low. tAW is referenced to the later of
or WE going low while
high. tWOT and two are referenced to WE with CE low.
Note 5: Either WE or CE {or bothl must be hi'gh d~ring address transitions to prevent erroneous write.
Standby Waveforms
VCES ------:,.----------~---~.
,~ :::-----~-~--2-:-p~ ~J_5V
.• .
VpD
VALID
_____________
-
5-16
_J~::~
tos, tDH
5.6.6
MM5281 4096·BIT Fully TTL Compatible
Dynamic RAM
General Description
technology, which is an ideal choice for high
density integrated circuits. The MM5281 uses a
single transistor cell to minimize the device
area. The single device cell, along with unique
design features in the on-chip peripheral circuits, yields a high performance memory
.
device.
National's MM5281 is a 4096 word by 1 bit fully
TTL compatible dynamic RAM. It incorporates
the latest memory design features and can be
used in a wide variety of applications, from
those which require very hlgh speed to ones
where low cost and large bit capacity are the
prime criteria.
Features
The MM5281 must be refreshed every two ms.
This can be accomplished by performing a
READ cycle at each of the 64 row addresses
(AO-A5)' The chip select input can be either
high or low.for refresh.
•
•
•
•
•
•
•
•
The MM5281 has been designed with minimum
production costs as a prime criterion. It is
fabricated using N-channel silicon gate MOS
Organization: 4096 x 1
Access Time 250 ns Maximum
Cycle Time 400 ns Minimum
TTL Compatible
Address Registers On-Chip
TRI-STATE® Output
Simple Read-Modify-Write Operation
Industry Standard Pin Configuration
Block and Connection Diagrams
WE (12)
CS (5)
----------------------j CQ~~~Ol
CS
LATCH
Dua!.! n·Line Package
All (4)
Al0(J)
Vss
A9(2)
AS
J11
AS (21)
11
A7
10
AG
Vao
18
19
IT
Nt
11
16
AS
15
A4
14
AJ
13
WE
12
Al (2(})
AS (19)
AS (15)
A4114}
COLUMN DECODER 11 '"
A30l)
A2 (10)
-I BU~~.11
t
SENSE AMPLIfiERS (64)
AIlS)
,
ADla)
D'N
Dotn
(6)
(7)
CEll
ARRAV
4096 SlTS
2
1
TIU1}
'100
V"B
A9
3
4
AID
All
5
CS
5
7
O'r>.!
[lOUT
-
-
,
B
AO
A1
TOP VIEW
i14J - - +12V
Order Number MM5281 0
Vss (181--0v
v.. ( 1 ) -_ _ SV
Vcc l11j--·5V
Pin Names
AD-A11
Address Inputs
CE
Chip Enab!e
CS
Chip Select
V DD
D'N
Data Input
Vss
Ground
Do~
Data Output
WE
Write Enable
NC
Not Cpnnected
l<-
"Refresh Address AO-A5
5-17
V BB
Power (-5V)
.V ~c
Power (+5V I
Power (+12VI
10..1 11
A2
Vc ,
5.6.7 MM5290 16,384 x 1 Bit Dynamic RAM
General Description
ture of the MM5290. This process c.ombines
high density and performance with reliability.
GreClter system densities are achievable by the
use of a 16-pin dual-in-line package for the
MM5290.
The MM5290 is a 16,384 x 1 bit dynamic RAM. It
features a multiplexed address input with
separate row and column strobes. This added
flexibility altows the MM5290 to be used in page
mode operation.
Features
The MM5290 must be refreshed every 2
ms. This can be accomplished by performing
any cycle which brings the Row Address Strobe
active including an RAS-only cycle at each of
the 128 row addresses.
•
•
•
•
•
N·channel double-poly silicon gate technology,
developed by National, is used in the manufac-
•
•
Access Times: 150 ns, 200 ns, 300 ns
Low Power: 462 mW Max
.
TTL Compatible: Ait Inputs and Output
Gated. CAS - Noncritical Timing
Read, Write, Read-Modify-Write and RASonly Refresh Cycles
Page Mode Operation
Industry Standard 16-pin Configuraton
Block and Connection Diagrams
~
Al-
~
12V
A2-
Vss
Vee
VOO
AO-
~
GNO
5V
01
-5V
A3-
MASA6ROW
CLOCKS
ROW
CLOCKS
rn---OI
MEMORY AARAV
64 X 128
CAS -'-L..-L....==-.J
COLUMN
CLOCKS
SENSE AMPLIFIERS (1281
MEMORV ARRAY
WRITE
Wf--<.JL..-L=::'::"J
00
64 X 128
CLOCKS
Dual-In-Line Package
16 Vss
VB'
Pin Names
15 CAS
01
"
WE
13
AAS
12
AD
11
A2
10
AI
9
VOO
00
A6
A3
A.
AS
Vee
TOP VIEW
5-18
RAS
CAS
Row Address Strobe
Column Address Strobe
WE
Write Enable
AO-A6
DI
DO
VDD
VCC
VSS
VSB
Address Inputs
Data Input
Data Output
Power (12V)
Power (5V)
Grou~d
Powed-5V)
Switching Time Waveforms
Read Cycle
----IcAc
____________
~
~-.:__-.:__-_-.:_.:_.:_.:__-~-O-PE-N-------:.--'-R-AC-----------------
__----V-A-L-IO----'O-F-FJ-_·----------------•
Write Cycle (Early Write)
RAS
CAS
AU-A6
VIHCVll-
V1HCVll-
VIHVll-
WE
VIHCVIL-
01
VIH -
Vil -
VOH-
OPEN
00
VOl-
5-19
DATA
)
SiNitching Time Waveforms (Continued)
Read-Write Cycle, Read-Modify-Write Cycle
100
CAS
AD-A6
VIHCVll-
VIHC-
Vll-
VIHVll-
WI
DO
VtHC -
Vll-
VOHVOL -
f---------tRAC-~-ttos
tOH
I
ot .:::=_"--~A-A~-t:--~~
RAS-Only Refresh Cycle
AU-A6
00 VOH- ----------------------O.'N----------------------VOl-
Note. CAS = V'HC, WE = don't car.
5-20
Switching Time Waveforms (Continued)
Page Mode Read Cycle
rn
I!)[!
VIHCVll-
VIHC Vll-
AD-A6
DO
V'HVIL-
VOH VOl-
WI'
VIHC VIL-
--
tACS
tRCH
Page Mode Write Cycle
WE
VIHC-
VIL- ~~~~~~~~____~~~~~~~~____~~~~~~~I~~~~~____~~~~~~~~~~~
VIH01
Vll-
=...."""=..
5-21
Timing Flow Chart
ACTIVE
TRANSFER DATA FROM SelECTED
COLUMN IN MEMORY ARRAY
TO liD LINES IN READ MODE
AND VICE VERSA IN WRITE MODE
PRECHARGE
DISABLE SELECTED ROW.
PRECHARGE ROW:ADDRESS LATCH,
ROW DECODER AfjDMEMORY ARRAY
5·22
5.6.8
MM1702A 2048·Bit
Programmable ROM
Electrically
General Description
The MM1702A is fabricated with silicon gate
technology. This low threshold technQlogy
allows the design and production of higher performance MOS circuits and provides a higher
functional density on a monolithic chip than
conventional MOS technologies.
The MM1702A is a 256 word by 8-bit electrically
programmable ROM ideally suited for uses
where fast turn-around and pattern experimentation are important. The MM1702A undergoes
complete programming and functional testing
on each bit position prior to shipment, thus insuring 100% programmability.
Features
•
The MM1702AQ is packaged in a 24-pin dual-inline package with a transparent lid.
The
transparent lid allows the user to expose the
chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written into the
device. The MM1702AD is packaged in a 24-pin
dual-in-line package with a metal lid and is not
erasable.
Fast Programming - 30 Seconds for all
2048 Bits
All 2048 Bits Guaranteed Programmable
-100% Factory Tested
Fully Decoded, 256 x 8 organization
Static MOS - No Clocks Required
Inputs and Outputs DTL and TTL
Compatible
TRI-STATE® Output - OR-tie Capability
Simple Memory Expansion - Chip Select
Input Lead
Direct Replacement for the Intel 1702A
•
•
•
•
•
•
The circuitry of the MM1702A is entirely static;
no clocks are required.
•
A pin-for-pin metal mask programmed ROM, the
MM1302 is ideal for large volume production
runs of systems initially using the MM1702A.
Dual-In-Line Package
VOD
I..
Block and Connection Diagrams
Vee
13
Vee
22
A]
A4
A5'
20
21
A6
19
18
A1
VGG
11
Vas
16
15
PRO·
GRAM
CS
"
13
PROGRAM
AD
A1~ INPUT
I
DRIVERS
A1-4
&
DE·
COOER
20'~BIT
DATA
OUT 1
ROM
MATR'X
(256 x 8)
-
r--
DATA
OUT8
Note: In the reall mode a logIc
"1" at the address IIlputs and data
outpub is a high and logIC "0" is
a low.
2
1
A2
A1
3
AO
•
5
6
1
8
9
10
11
~~~"'B--"-.;....-.O.;..AT~A...;O-UT--"-~.,.,M:~~
rz
Vee
TOP VIEW
"This pin is the data input lead during programming.
Pin Names
AD-A7
Address Inputs
CS
Chip Select Input
DOUT 1 - DOUT s
Data Outputs
. Order Number MM1702AD
Order Number MM1702AQ
Pin Con'nections*
MODE/PIN
12
13
14
15
16
22
(Vce)
(PROGRAM)
(eS)
(VBB)
(VGG)
(Vee I
23
(Vee!
Read
Vee
Vee
GND
Vee
VGG
Vee
Vee
Programming
GND
Program Pulse
GND
Vss
Pulsed VGG (V ,L4P )
GND
GND
*The external lead connections to the MM1702A differ, depending on whether the device is being programmed or used in
read mode. (See following table.) In the programming mode, the data inputs 1.-8 are pins 4-11 respectively.
5-23
Read Operation Switching Time Waveforms
(b) Power~Down Option (Note 1)
(a) Constant VGG Operation
r----'
CYCLE TlIVIE
l/f
----'~
VtH -Y10%
~
90%
"---
fi-
ADDRESS
1L
L
!
cs V'H~
V
V"
DATA
OUT
V~H
-j
I '9 W
I .
I
I r;;;A OUT
.'
V~l ~~~~,___ ~~~_.
_IN~~AlID
t-------'''' ---------t
.
DESElECTION Of DATA OUTPUT IN ORTIE OPERATION
V'"\/
OESElECTlON OF DATA OUTPUT IN OR-TIE OPERATION
C
ADD.ES<~X:
-Jh...}-_ _ _ _ _ _ _-:-_ __
ADDRESS
-
V"~(NDTE2I----_.'m
V
r---""':tr.---,H
os
VtH~~O%'
-
I
I
V"
VOH---t
~90%
'.---1.1'901.--.
v
"v::
"-
ClOCKEO
DATA
VGG
OUT
vo,
i
I
'0""
I
''"
---i
II
[--
I
V GO
'L.
"-+---"
teo : -
ConditIOns of Test:
Input puiS/! amplitulie5: 0-4V, t,. tl S 50 liS. Output load IS 1 TTl
ments made at output of TTl gate (tpo S Hi ns), Cl ~ 15 pF,
-1
\1
VO
DATA OUT
gat~.
measure
Note I, Tile output Will ,em~tn valid fOI IoHc as long as clocked Vee IS at Vee, An
addless [h~n~ may occur as soon as tile outpull! sen~ed (docked 'Vee may stll! be atVed. O~t~ b~C\lme~ Invalid fOI the old addre$ when docked Vee IS returned to Vee
Note 2: "CS make~ a tranSition from V,L to V,H while docked VCG IS at Vce, then
desele'ctton of output oceuls at too as Ihown In static operatlol'! wltll constant VGG ·
Operation of the MM1702A in Program Mode
desired bit information patterns on the data input terminals.
Initially, all 2048 bits of the ROM are in the "0"
state (output low). Information is introduced by
selectively programming "1 's" (output high) in
the proper bit locations.
During the programming, VGG, VOD, and the
Program Pulse are pulsed SIgnals.
MM1702A Erasing Procedure
The MM1702A may be erased by exposure to
high intensity short-wave ultraviolet light at a
wavelength of 2537.8.. The recommended integrated dose (i.e. UV intensity x exposure
time) is 6W sec/cm 2. Examples of ultraviolet
sources which can erase the MM1702A in 10 to .
20 minutes are the Model UVS-54. and Model
S-52 short-wave ultraviolet lamps manufactured
by Ultra-Violet Products, i Inc. (5114 Walnut
Grove Avenue, San Gabriel, California). The
lamps should be used without short-wave
filters, and the MM1702A to be erased should
be placed about one inch away from the lamp
tubes. There .exists no absolute rule for erase
time. Establish a worst case time required with
the equipment. Then over-erase by afactor.of 2,
i.e., if the device appears erased after 8
minutes, continue exposure for an additional 16
minutes for a total of 24 minutes. (May be expressed as x + 2x.)
.
Word address sel.ection .Is done by the same
decoding circuitry used in the READ mode (see
table for logic levels.) All 8 address bits must
be in the binary complement state when pulsed
VDD and VGG move to their negative levels.
The addresses must be held in their binary complement state for a minimum of 25Jls after VDD
and VGG have moved to their negative levels.
The addresses must then make the transition to
their true state a minimum of 10Jls before
the program pulse is .applied. The addresses
should be programmed .in the sequence 0-255
for a minimum of 32 times. The eight output terminals are used as data inputs to determine the
information pattern in the eight bits of each
word. A low data input level (- 48V) will program a "1"and a high data input level. (ground)
will I~ave a "0:.'. All eight bits of one word are
programmed simultaneously by setting the
5-24
5.6.9 MM4204/MM5204
Electrically
Programmable 4096·Bit Read Only
Memory (EPROM)
General Description
•
The MM4204/MM5204 is a 4096-bit static Read
Only Memory which is electrically program·
mabie and uses silicon gate technology to
achieve bipolar compatibility. The device is a
non·volatile memory organized as 512 words by
8 bits per word. Programming of the memory is
accomplished by storing a charge in a ceilloca·
tion by applying a - 50V pulse. A logic input,
"Power Saver," is provided which gives a 5:1
decrease 'in power when the memory is not be·
ing accessed.
•
•
•
Applications
•
•
•
•
•
•
Features
•
•
•
Field Programmable
Fast Program Time: Ten Seconds Typical
for 4096-Bits
Fast Access Time
MM4204
1.25/Ls
MM~M
•
•
•
Easy Memory Expansion • TRI·ST ATE outputs allow for memory expan·
sions.
Applications
Programming of the memory array and chip·
sele.ct active levels is accomplished by changing two masks during fabrication.
Block and Connection
,',
•
•
•
Microprocessor Instruction Store
Control Logic
Table Look-Up
Diagram~
DUal'ln·Line Paj:kage
01
.24
AI
A1~-'"----'
D2
Z3
A&
A2
Vee
.AO
OJ
ROW DECODE'
OS
00
07
O'
~.
1=
rr
A.
22 AI
A4
21 Al2
AJ
2~
A2
19 AID
O'
8192 x'a
ROM
ARRAY
eSI
AI
18 All
AO
11 08
01
16 01
02 10
15 0&
11
14 05
OJ
"
GND 12
04
TOPVIEW
AO
A9
Al0
All
Al2
eSI
Switching Time Waveforms
2.4V
ADDRESS
Z.4V
1.5V
ADDRESS .
Mv
DAV
zAV
Z.4V
1.5V
CHIP SelECT
CHIP SELECT
D.4V
DAY'
'DFF
TRI·STATE@
OUTPUT
OUTPUT
'AC
5-40
TRI·siAT~
VALID
I
Chapter 6
MAXI·ROMs
MEMORY
Part Number/Description
INPUT/OUTPUT
~
SERIES 8000
MICROPROCESSOR
l"-
M
I
C
I.)-
R
0
B
U
5
PERIPHERAL
CONTROL
TM~
COMMUNICATIONS
• Trademark, National Semiconductor Corporation
INS8298E
8080A LLL Basic Interpreter
MM52132
-MAXI·ROM (32K, 450 ns Access)
INS8364E/MM52164
MAXI·ROM (64K, 450 ns Access)
3:
MAXI-ROMs
l>
-:0><•
o
3:
(/)
6.1 GENERAL DESCRIPTION
The BASIC interpreter accepts both program
statements and control commands. Program
statements describe (to the BASIC interpreter)
operations to be performed on program data. A
program statement preceded by a line number
is inserted into the program for later execution
at a spot determined by the line number. If no
line number precedes the statement, it is ex·
ecuted. immediately and then discarded. This
latter mode, known as "immediate" or "direct,"
is especially valuble during program checkout.
Control commands specify actions that alter
the status of the user's program; for example,
they direct the execution, saving, and retrieval
of programs.
MAXI·ROMS are 32K, 64K and up static mask·
programmable ROMS. This large size
allows
storage of complete programs, tables, etc .. Any
user program or data may be mask programmed.
6.2 INTERFACING TO MEMORY
Basically, interfacing to memory is the same as
any other ROM. Memory address location
assignments should be coordinated with loca·
tions that the MAXI·ROM stored program
requires.
6.3 UNPROGRAMMED MAXI·ROMs
Two unprogrammed MAXI·ROMs are currently
available, as follows:
•
•
A Hexadecimal Debugging Routine (HOT) is
also available on the INS8298E ROM. HOT
allows the user to examine internal registers
and memory locations and modify their con·
tents. HOT is called from the BASIC interpreter
to help debug user·developed software. Input
and output data representation is in
hexadecimal format. In addition to the usual
debugging capabilities, HOT also has com·
mands to perform the following functions:
• Test a specified range of memory loca·
tions
• Load programs in hexadecimal, NSC, and
Lll binary formats
• Save the contents of a specified range of
memory locations
MM52132 (4096 x 8 bits)
INS8364E/MM52164 (8192 x 8 bits)
These devices can be mask·programmed with
any user program or data.
6.4 INS8298E 8080A LLL BASIC
INTERPRETER
The 8080A LLl BASIC interpreter operates with
the 8080A microprocessor system to provide a
high·level, easy·to·use language for perforl\ling
both control and computational functions.
Designed for use in data acquisition and con·
trol applications, the LLL BASIC interpreter
enables the user to write and debug a program
on·line ..
System Configuration
BASIC's internal I/O assumes a system con·
figured in the manner of the BLC (or SSC) 80/10
or 80/20 Single·Board Computers, which use an
INS8251 USART for console I/O. The data and
status ports are at I/O addresses EC and ED
(hex), respectively. It is also assumed that the
user's system includes a monitor program (e.g.,
the SlC 80p Monitor) to initiate execution of
BASIC and to initialize the USART.
The LLL BASIC interpreter (resident on the
INS8298E ROM) is used to translate, debug, and
execute user·written ASCII programs in
read/write memory (RAM). Each statement is in·
terpreted from its ASCII BASIC format and then
executed line·by·line.
The minimum hardware configuration required
to support the LLL BASIC interpreter is as
follows:
See the National Semiconductor LLL BASIC
users manual for a description of the LLL
BASIC language. While this manual describes
the LLl BASIC language, it is not intended as a
primer. Familiarity with high·level computer
programming languages is assumed; familiarity
with BASIC is desirable but not required. There
are many excellent introductory textbooks on
BASIC that should be consulted if a more
tutorial approach is desired. See also the
INS8298E 8080A LlL BASIC interpreter data
sheet.
•
•
•
•
•
•
6·1
8080A Central Processing Unit (CPU)
110·Baud ASCII Terminal Illterface
INS8298E 8K·by·8 Read Only Memory
(ROM)
At least 512 bytes of Read·Write Memory
(RAM) for user·written programs
Model 33 ASR Teletype (TTY) or similar
terminal
Power Supplies (±5V, :!:12V)
MEMORY
Chapter 7
Input/Output
Components
Part Number/Description
INS8202
Tri-5tate 80Bit Bus Driver
INS8203
Tri-State 80Bit Bus Driver (Inverting)
INS8208B
80Bit Bi-Directional Bus Driver
INS8216
4-Bit Bi-Directional Bus Driver
INS8226
4-Bit Bi-Directional Bus Driver
(Inverting)
INS8212
80Bit 110 Port
M
~
I
SERIES 8000
C
R
MICROPROCESSOR ~.)---fO
~::::::::::::~
B
U
5
TM"
PERIPHERAL
CONTROL
COMMUNICATIONS
* Trademark, National Semiconductor Corporation
:::::J
Input/Output
Components
-
"C
C
oc
-
"C
C
( ')
7.1 GENERAL DESCRIPTION
The general purpose of the Digital Input/Output
components is to supplement the functions
already present in other devices. Typical func·
tions of these devices are 110 buffers, data/ad·
dress latches, address decoders, and program·
mabie 110 ports. (See also Chapter B.)
•
Input/Output Addressing
Depending on the system input/output environment, the input/output devices of the typical in·
terface (figure 7·1) may be addressed using
either the isolated input/output or memory map·
ped input/output technique and linear select.
Thus, no decoders are required for generating
chip select signals and each device has an ex·
clusive enable bit. Figure 7-2, shows an exam·
pie of how to address six National Semiconductor INS8255 Programmable Peripheral Interface
devices using the isolated input/output addressing technique and linear select. In this ex·
ample, the addressing format shown is the second byte of an IN or an OUT Instruction.
. Similarly, figure 7·3 shows an example of how
to address 13 INS8255 devices using the
memory mapped input/output addressing
technique and linear select. In this example,
the addressing format shown could be second
and third bytes of any memory reference in·
struction that is used for the input/output
devices (for example, MVI M, LOA, STA, SHLD,
ADD M, ANA M, Et cetera). See chapter 11 "Programming for INS8080A instruction set.
Programmablei nput/output and peripheral
functions enable the system designer to con·
figure and adapt interface lines to his own reo
quirements. In the Series BOOO family, the
INSB212 B·Bit Input/Output Port, the INSB255
Programmable Peripheral Interface and the
INSB251 Programmable Communication Interface (see chapter 9) can satisfy· these system input/output requirements. The INS8212 is a
multimode chip fabricated using National
Semiconductor's Schottky bipolar technology.
The device may be used to implement latches,
gated buffers, or multiplexers. Thus, the chip
can be used in a microcomputer system as
either an address buffer, a priority interrupt ar·
bitrator, or an input/output peripheral interface.
The INSB255 is a general-purpose programmable parallel input/output chip fabricated us·
ing the silicon gate MOS process. This device
is designed to interface peripheral equipment
to the BOBOA system bus.
•
Interfacing 8·Bit Peripherals
As shown in the typical input/output interface
of figure 7-1, two National Semiconductor
INS8255 Programmable Peripheral Interface
devices and three National Semiconductor
INS8212 Input/Output Port devices are provided
for interfacing 8-bit peripherals (keyboards, sen·
sors, paper tape, displays, et cetera) to the
system. Since each INS8255 has three ports,
up to 24 bits of programmable input/output data
and control. signals are provided by each
device. Note that the 110 Wand 110 R signals
from the Control Bus are used as write and read
command signals for the transfer of data
(01'00) to and from the INS8255 devices. Also,
note that the 110 W signal is used in conjunction with the A5 address bit to select the
INS8212 device that functions as an output
port; and that the I/O R signal is used in conjunction with either the A6 or the A7 address bit
to select one of two INS8212 devices that function as interrupting input ports. The addressing
formats for the INS8255 and INS8212 devices
\ are shown in figure 7-4.
Due to the simplicity of the devices contained
in this chapter, the majority of the devices will
not be covered in any detail.
The digital 110 components illustrated in this
section are but a small sample of those
available from National Semiconductor. Detail·
ed operational and parametric information on
each of the devices is contained in Appendix 0,
Device Data Sheets.
7.2 INTERFACING INPUT/OUTPUT
COMPONENTS
The input/output devices use the same
MICROBUS for interfacing to the' CPU group as
the semiconductor memory components. A
typical input/output interface is shown in figure
7·1.
This interface enables the INSBOBOA
Microprocessor to communicate with
peripheral devices or structures such as
keyboards, paper tape, floppy disks, printers,
displays, data communication interfaces, sensors, relays and motor controls ..
' . Interfacing Serial Devices
As shown in the typical interface of figure 7-1,
one National Semiconductor INS8251 Program7-1
o
3
"C
o
:::::J
('I)
:::::J
CJ)
SERIAL DATA
COMMUNICATION
,...
#2
INS8255
INS8251
RDWR
..
flOW
iTOR
J
CE
07-00
~
.
C/O
RD
C
,.
WR
07-00
..
(
A4
~
M
#1
INS8255
CS
I
C
R
...
,..
A7
AO
RD
A1
WR
07·00 CS
I,)
flow
IIOR
AO
A3
AO
A1
IIOR
...
,..
B
0
U
N
SYSTEM
CLEAR
~
CLR
#3
INS8212
(INTERRUPTING
INPUT PORT)
1I0W
STB
P-
~C CLR
FROM INPUT
DEVICE
DS2
#2
INS8212
(INTERRUPTING
INPUT PORT)
STB
MD
t
NOTE:
INT
TO
MULTI·
LEVEL
PRIORITY
CIRCUIT
OR
INS8080A
(SEE
NOTE)
,.
A5
DS2
MD
~
G~D
FROM INPUT
DEVICE
A1
#1
INS8212
(OUTPUT PORT)
MD
t
G~D
P-
Ao
I
DS1
INT
A1
\
S
...
DS1
A2
...
AS
DS2
AO
.. II.
(
DS1
-..j
...
....
~
Jcc
TO
MULTI·
LEVEl
PRIORITY
CIRCUIT
OR
I NS8080A
(SEE
NOTE)
IF ONLY ONE INS8212 INTERRUPTING INPUT DEVICE IS USED, THE INT SIGNAL SHOULD BE CONNECTED TO THE INT PINOUT OF THE
INS8080A VIA AN INVERTER. IN Tt-:lIS W~Y, A USER SELECTED SINGLE LEVEL INTERRUPT (RST 7) IS GATED ONTO THE INS8080A DATA
BUS WITH A HIGH·LEVEL DBIN SIGNAL, WHEN THE INTERRUPT REQUEST IS ACKNOWLEDGED.
Figure 7-1 Typical Input/Output Interface
ADDRESS
BITS
A7
A6
A5
A4
A3
A2
#5
#4
#3
#2
#1
Al
AO
\~----------~----------~/\~--~~I
PORT
SELECTS
DEVICE SELECTS
NSI0624
Figure 7-2. Example of Addressing INS8255 Devices Using
Isolated Input/Output Technique and Linear Select
ADDRESS
BITS
(BYTE 1)
I
\
A7
A6
#6
#5
I
"A5
A4
A3
A2
#4
#3
#2
#1
Al
A15
\
1\
/\
PORT
SELECTS
A14
A13
A12
All
Al0
A9
AS
#13
#12
#11
#10
#9
#6
#7
I/O FLAG:
1 - I/O
o • MEMORY
DEVICE SELECTS
NSI0743
Figure 7-3. Example of Addressing INS8255 Devices Using Memory
Mapped Input/Output Technique and Linear Select
7-3
I
!
DEV'ICE SELECTS
ADDRESS
BITS
(ElYTE 2)
AO
I
/
maple Communication Interface device is provided for interfacing serial data devices
(MODEMs, communications links, et cetera)
the system. Note that the I/O Wand I/O
signals are also used as write and read command signals for the transfer of data to and
from the INS8251 device. The addressing format for the INS8251 is shown in figure 7-5.
tR
ADDRESS
BITS
I
.;.,."
0
0
I,
0
I
1
,\
A3; ,
A2
#2
#1
I
I
/\
,A1
DEVICE
SELECTS:
0" SELECT
1 .. DESELECT
I
I
AO
I
I
PORT
SELECTS:
00 - PORTA
01 .. PORTB
10" PORTC
11 .. COMMAND
A. INS8S Devices
ADDRESS
, BITS
\
A7
AS
#3
#2
I
AS
#1
1
I
I
1
, [)«[)1
DATA LATCH
-O~AT'A.
I-c:..+..::.-j___
-_
..=~----
LATCH
~t: ~:TCH l
AiN-----'
-,--
OAT
f-~+..:..-tL--~joATAlC1
---- --,
CLR ~- resets d-_-------------'
NOTE: INS8208 B
identical to
DP8304
Logic Table
Inputs
Chip Disable Transmit/Receive
0
a
1
0
1
X
x
B PORT
6
A60--:
'
A7 ~-------L _______ _
VCC
A1
A5
---------,0----0
--------- ...
INS8208B
1
20
A6
~B4
A40---:
A5 e>----J -------L _______ _
A PORT
~B2
_________ "0----0 B3
---~------,
AO
Resulting Conditions
A Por.t
B Port
OUT
IN
IN
OUT
TRI-STATE
TR I-STATE
= Don't Care
7·8
Switching Time Waveforms and AC Test Circuits
VCC
tr = tt<10ns
INPUT
AaOR Ba
OV
R1
VCC
INPUT
10% to 90%
OUTPUT
G
IpDLH
OUTPUT
BaORAa
1.SVt
DEVICE
UNDER
TEST
---~
J
C1
R2
NOTE: C1 INCLUDES TEST FIXTURE CAPACITANCE.
Propagation Delay from A Port to B Port or from B Port to A Port
VCC
tr.:::: tf<10 ns
10%to 90%
APORTo---------~--_4
DEVICE
OUTPUT---h
A PORT
Vce ...-0
1-----..---------<0 B PORT
UNDER
TEST
S2:::: 1
R3
R4
TIR
B PORT
OUTPUT - - - - - '
NOTE: C2 AND C3 INCLUDE TEST FIXTURE
CAPACITANCE
Propagation Delay from T /R to A Port or B Port
tr::::. rf
INPUT
<
10n$
1QO/"to 90%
CD
OV
PORT OUTPUT - - - h
tpHZ
PLZ
~
-
I·
O.SV
--1.
PORT OUTPUT
Vee
PORT
INPUT
2.4V 0
MV
,rC1-----------r--'--l------..--------o
S4
INPUT
PORT
OUTPUT
DeVICE
UNDER
TEST
RS
VCC
NOTE. C4INCLUDES TEST FIXTURE CAPACITANCE
PORT INPUT IS IN A FIXEO LOGICAL
CONDITION. SEE AC TABLE
Propagation Delay to/from TRI-STATE'" from CD to A Port or B Port
7-9
7.6
I.NS8216/82264·BIT BIDIRECTIONAL BUS
DRIVER
The INS8216/8226 are 4·bit bidirectional bus
drivers for bus·oriented systems. Each line of
the driver consists of two separate TRI·STATE
buffers. On one side of the driver the output of
one buffer and the input of the other are tied
together to create a bidirectional TTL port for a
, system bus. The other side of the port has both
a separate input and a separate output to pro·
The
vide for maximum system flexibility.
INS821~ contains non-inverting buffers and the
INS8226 contains inverting buffers.
Features
•
•
•
•
•
DID 0
Low Input Load Current
High Bus Drive Capability
TRI-STATE Outputs
Inverting or Non-Inverting Outputs
MOS compatible High-Voltage Outputs
DID 0
DBO
DBO
DOD 0
DOD 0
Dll
Dll
OB t
OBI
DOt
DDt
01 2
01 2
OB2
OB2
00 2
002
OIJ
OIJ
OB3
OB3
OOJ
OlEN
OOJ
OlEN o---~I_---...J
o---.-_---.....A
L------~--~cs
L-----~--~cs
. INS8216
INS8226
7·10
MEMORY
Chapter 8
Peripheral Control
Components
Part Number/Description
INPUT/OUTPUT
M
SERIES 8000
MICROPROCESSOR
~'--""'6
tF~u
~::::::::::::~
s
COMMUNICATIONS
• Trademark, National Semiconductor Corporation
DP8350
Programmable CRT Controller
INS1771-1
Floppy Disk Formatter/Controller
INS8244
9O-Key Keyboard Encoder
INS8245
16-Key Keyboard Encoder
INS8246
2o-Key Keyboard Encoder
INS8247
4-Digit Display Controller
INS8248
6-Digit Display Controller
INS8253
3-16 bit Programmable Interval Timers
INS8285
Character Generator
INS8292
8-Bit AID Converter with 16-Channel
AnalogMUX
INS8294
3 3/.1-Digil DVM with Multiplexed
BCD Output
"tJ
CD
Peripheral Control
Components
~.
"C
';j'
CD
""'I
Q)
o
o
The Series 8000 Microprocessor Fam i Iy
peripheral control components provide the in·
terface between the microcomputer system
and its commonly used peripherals (or the man·
machine interface to the microcomputer). Be·
ing software programmable, these components
are able to provide complex control functions
that eliminate most of the discrete devices
previously needed to implement the controlling
functions.
The components contained in this chapter pro·
vide complex control functions for some com·
monly used peripherals. Thanks to Large Scale
Integration, these devices allow both a reduced
system chip count and reduced system design
time, particularly because these, devices are
MICROBUS compatible. Due to the extreme
flexibility of the INS8080A Instruction set,
these peripheral control devices may be used
as either memory mapped I/O or as peripherals
(using the INS8080A I/O Control Group Instruc·
tions).
Detailed information on use of the Series 8000
Microprocessor Family Peripheral Control
Components is contained in the following sec·
tions. Parametric information for the com·
ponents is located in appendix D, Device Data
Sheets.
8.2 INTERFACING THE PERIPHERAL
CONTROL COMPONENTS
Figure 8·1, illustrates the general interfacing of
peripheral control components. Most controll·
ed devices will be interfaced directly with the
associated peripheral control component.
Optional circuits might be used for interfacing
to SpeCial devices or to Enhance device
capability.
8.3 KEYBOARD ENCODERS/DISPLAY
CONTROLLERS
A variety of keyboard encoders are available
from a 16·key CMOS device up to a gO·key
MOS/LSI device. All have TRI·STATE·TM
outputs.
.------ ...
rl-
SYSTEM
PROCESSOR
M
I
C
R
0
B
U
S
-::::J
8.1 GENERAL DESCRIPTION
PERIPHERAL
CONTROL
COMPONENT
~
.. ----_ ....
I
I
I
I
I
I
..
I
I
OPTIONAL
CIRCUITS
:I I
_----_ ..
I
Figure 8·1. Interfacing the Peripheral Control Components
"Trademark, National Semiconductor Corporation 8-1
CONTROLLED
DEVICE
"
I
..._------
" "'I
o
o
o
3
"C
o
::::J
CD
::::J
f /)
8.3.1 INS8244 90·Key Keyboard Encoder
Features
The INS8244 is an MOS/LSI keyboard encoder
capable of encoding 90 indiviqual single-pole,
single-throw switch closures into a usable 9·bit
code.
•
•
•
•
•
TRI-STATE Data Outputs
Function Inputs TTL Compatible
Single TTL Clock
N key/Two Key Rollover
Key Bounce Masking
'"
BOUNCE
(17) MASK
VID-V1
¥
U4)
~ DATA
1+----=-0 ~1~~~~l
l_.._~:__...J~~~~~'l13;;"'-,
CLOCK
LD~~!I~ri
+=----+1
CONTROL
o-=--~--.J
STROBE
DATA
XU-XI
(15)
OUTPUT
L _ _ _ _ _ _- . . -_ _ _ _ _ _jf--<~"'ENABlE
~9-81
Figure 8-2. INS8244 Internal Block Diagram
INS8244
KEVBOUNCE
MASK
50Upf
INS8203
8J.B1
J
~~iiI••••~B8-81
C.
R
ol--;;;--r
~
.' ,
.figureS-.. 1 which shows .the read timing. Data
. ,r:nustoccur. withIn the snaded. P9rtion of ,the
timing diagram in Qrder to. be val.ld. The..track
format is ,shown .in figure. 8-12 .. After .. the
..physical!)ensing of the Index and.a nominal
:delay,: the Index' Address Mark is written.' This
gives us the electronic start of that particular
track. The ID record 'contains the sector adress
and also the CRC (Cyclic Redundancy Check).
This Will be used by the error checking circuits
to confirm valid data for ID record. This ID
r~cord is shown expanded in the left center of
.figure 8-~2. A data field record is shown to the
right. Byte one of the data field record is called
the, Data or Deleted Data Address Mark. This
byte will all()w recovery of deleted data prior to
packing of the diskette, because the data is still
there, although byte one is changed to indicate
deleted data: The 128 bytes of user data is
followed by C;RC Bytes for error checking.
The INS1771·1 Floppy Disk Formatter/Con·
troller will function with eitherthe standard size
floppy orthesmallel' mini.floppy;
',.'"
;,
'
" ~,,1
READlWIllTE
HEAD OPENING
INDEX
ACCESS
HOLE
1.5" DlA.·
i.:,
REGISTRATION
OPENING
INDEX
HOLE
TRAcK 00
OPENING FOR
ORIVE HUB
TRACK 76
PLASnC
. ENVELOPE
"; Figure 8-10. Diskette Layout (Example)
8-6
NOTES:
1. ABOVE TIMES ARE DOUBLED WHEN ClK = 1 MHz.
2. CONTACT NSC FOR EXTERNAL CLOCK/DATA
SEPARATOR CIRCUITS.
Read Timing (XTDS
I'
tpWI
I
= 0)
IPWI
IPWI
1-- -'1 1--
FDDATA
~--tCI--_"""'---
NOTES:
1. INTERNAL DATA SEPARATION MAY WORK FOR
SOME APPLICATIONS. HOWEVER FOR APPLlCA·
TIONS REQUIRING HIGH DATA RECOVERY
RELIABILITY, NSC RECOMMENDS THAT EXTER· .
NAl DATA SEPARATION BE USED.
2. FDClOCK MUST BE TIED HIGH.
Read Timing (XTDS
= 1)
Figure 8·11. Read Timing
8-7
PHYSICAL
INDEX
.. ",,,j.-1
NOMINAL
f
DATA
FielD
RECORD
26
GAP 4
PRE INDEX
320 BYTES
INDEX
ADDRESS
MARK
GAP 1
POST
INDEX
32
BYTES
ID
RECORD
#1
GAP 2
10
GAP
17
BYTES
DATA
FIelD
RECORD
#1
GAP 3
DATA
GAP
33
BYTES
10
RECORD
#2
-I
GAP
2
DATA
FIELD
RECORD
#2
ID
RECORD
#3
GAP
3
GAP
2
OJ
TRACK
ADDRESS
SECTOR
ADDRESS
ZEROES
32 fS
~
GAP
2
I
BYTE
2·129
ZEROES
CRC
BYTE 4
DATA OR
DELETED
DATA
ADDRESS
MARK
CRC
BYTE 2
Co
--I
ID
RECORD
#26
--..-
~
BYTE
4
ID
ADDRESS
MARK
DATA
FielD
RECORD
#3
I
I
128 BYTES
OF USER
DATA
I
I
130
131
CRC
BYTE 1
CRC
BYTE 2
I
,,
GAP 2
.,,,
,,
,,
,,
,,
GAP 3
1~11 BYTES~I"-6 BYTES~I
-.11 BYTE
WRITEGATE /
TURN ON FOR UPDA TE
OF NEXT DATA FIELD
Figure 8-12. Track Format (Diskette)
1-
' - WRITE TURN·OFF
FOR UPDATE, OF
PREVIOUS DATA FIELD
DATA
FIELD
RECORD
#26
GAP
4
The chip is programmed by the system software, and program control information is
transferred to the INS1771-1 over the system
bus lines. This includes control words, status
information, and all data transfers.
These
transfers for the INS1771-1 Floppy Disk Formatter/Controller are multiplexed on the system
bus along with data for other bus-oriented
devices. Interface to the system bus is shown
in figure 8-13.
The INS1771-1 provides for control of floppy
disk drives including writing of the disk format
by program control. This soft sector formatting
may be either IBM3740 compatible or a userselected, sector format. The INS1771-1 is programmed to carry out operations without continual control by the CPU, therefore freeing the
CPU for other Operations. See figure 8-13 Interface to System Bus. The interleaved clock and
data pulses are sent to a Data Separator, then
the individual pulse streams are sent to the
INS1771-1.
Selection of registers within the INS1771-1 is
shown in table 8-10 Register select lines (AO,
A 1) are used in conjunction with either an active (low) RE or WE input to select an INS1771-1
register to read from or write into, as indicated
in the table.
Figure 8-14 is a functional block diagram of the
INS1771-1 device. The INS1771-1 includes error
checking circuits and storage of status information such as sector and track location.
rc
SYSTEM
PROCESSOR
-
INSl77H
07.00
OAL7·0ALO
S
Y
S
T
E
M
CS
8
INTH
U
S
ORO
lID
Wll
Al AO
om
RESET
FDDATA
cs
lID
FOCLOCK
SEP
DATA
DATA
SEPARATOR
SEP
CLOCK
.--
Wll
WRITE
DATA
Al,AO
WR DATA
INTRO
CONTROL IN
ORO
DACK
mSK {
INTERFACE
CONTROLS
CONTROL OUT
RESET
0Figure 8-13. Interface to System Bus
Table 8-1. INS1771-1 Register Selection
A1
AO
RE
WE
Selected Register
0
0
0
1
Status Register
0
0
1
0
Command Register
0
1
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
0
1
8-9
Track Register
Sector Register
Data Register
FLOPPY
DISK
DRIVE
INTERFACE
ORO
INTRO
(30
(29)
(36)
(
(35)
(34)
CONTROL
(38),....-_......
(39)
t.m
CS
lIE
WE
COMPUTER
INTERFACE
CONTROL
CONTROL
PLA
CONTROL
(190 x 16)
CONTROL
DISK
INTERFACE
CONTROL
(17)
(18)
(37)
(28)
23)
CLK~
'------'
I
VOO
POWER
SUPPLIES
(40)
• +12V
VCC~+5V
VBB~-5V
VSS~ GNO
(15)
(16)
NOTE:
APPLICABLE PINOUT NUMBERS
ARE INCLUDED-WITHIN
PARENTHESES
Figure 8-14_ INS1771-1 Block Diagram
8·10
WG
T643
Wi'lff
WI'
ii'
TIIlIlI
READY
JiiI1/STEP
PH2/D1RC
PH3
311M
IliNT
HLO
HLT
There are eleven commands grouped into four
types are summarized in table 8-11. These command types are:
TYPE
GROUP
I
II
III
IV
Head Positioning
Data Write/Read Commands
Track Commands (Format Disk)
Force Interrupt
head to a particular addressed track. Step, Step
In, and Step Out are incrementa-I· step commands. Step In or Step Out cause movement to
the adjoining track in the direction specified.
Step will cause movement in the current direction to the next track.
Refer to figure 8-15 Seek Command, and also
the Block Diagram in figure 8-14 for the following discussion. Recall that the data lines will
transfer data, address and control information.
During the Seek operation the track number
which we desire is loaded into the Data
Register. The current track is stored in the
Track Register. When they are not equ~I, step
commands will be issued. When they compare
the Read/Write head has reached the desired
position, and an interrupt will then be sent to·
the CPU via the system bus.
Table 8-2. Commands Summary
Type Command
I
I
I
I
I
I
II
II
III
'III
III
IV
Bits
6
5
4
3
2
1
0
0 0
0 0
0 0
0 1
0 1
Read Command 1 0
Write Command 1 0
Read Address
1 1
Read Track
1 1
Write Track
1 1
0
0
1
0
1
0
1
u
u
u
h
h
h
h
h
V r1
V r1
r1
V r1
V r1
ro
ro
ro
ro
ro
7
Restore
Seek
Step
Step In
Step Out
Force Interrupt
1
0 m b
1 m b
E 0 0
E a1 ao
0
E
E
E
0
1
1 0
0
0
0
0
S
0
0
1 13 12 ,11
10
0
1 0 0
1
Type II Commands cauSe writing or Reading of
data in one or more sectors. Error checking is
performed and the command is terminated with
an interrupt if a valid 10 field is not found within
two revolutions of the disk. The ID field must
have a valid track number, sector number and
CRC for proper operation, otherwise the Record
Not Found status bit (bit 4) is set.
Type III commands are used to format the
diskette. They are Read Address, Read Track,
and Write Track. The Read Address command
causes a read of the next 10 field and transfers
the data to the CPU.
Type I commands are basically head positioning commands. Included are Restore, Seek,
Step, Step In, and Step Out. Restore will cause
positioning to track 00. Seek will position the
FDC
DATA_
ADDRESS
Type IV Commands may be loaded into the
command register at any time and will cause
termination of any command under execution
and an interrupt t.o be genera1ed.
+
I
I
DATA REGISTER
10
=
FOC
J
WRITE
COMPARE
3. INTERRUPT AS COMMAND ENDS
1. LOAD DATA REGISTER
2. SEND 'SEEK' COMMAND
-
1
-
TRACK REGISTER
50
=
1-
INTERRUPT
UPDATE
I
l
DATA REG.
10
=
I
TRACK REG.
=10
J
C
o
M
M
A
N
o
---
CONTROL
PLA
STEP
HEAD
REG.
Figure 8-15. Seek Command
8-11
CONTROL
PLA
I
8.60P8350. PROGR.AMMABLE
CONTROLLER
CRT
The DP8350 is' a mask-progiamn1able dedicated
CRT display 1fresh controller. It ,isa single
chip bipolar (I L technology) circuit in a 40 pin
package. The DP8350 contains a crystal controlled dot rate clock, to ease system synchronizatiofl and a complete. set of video synchronization· output signals. -' Internal maskprogrammable ROMs are used to provide a wide
range of program control: _
•
•
The 'CRT controller (CRTC) also provides program inputs,' (including 50/60 Hz control),
system clear, and characterslline rate clock.-.
The DP8350 operates on a single + 5V power
supply. Outputs and inputs are TIL compatible.
For systems where a,dot rate Ciock is already
provided, an external ,qlock input may be. used
by the CRT controller. In either case, system
sy~chronization is made possible with the use
of the buff~ed Dot Rate Clock Output.
Features
•
•
•
•
•
•
•
•
•
There are eleven character generation related
outputs for use with system character ROMs
and three on-ohip registers that provide for external loading of the.new row starting address,
cursor address,. and top-of-page. address. The
DP8350 can dir~ctly interface with up to 4K of
memory via the three on-chip registers provided
. for external loading of the new row starting address, cursor address, and top ofpagl:} address ..
•
•
A complete set of video sync outputs is
available-including cursor enable, programmable vertical blanking, programmable horizon.
tal.- blanking, programmable horizontal sync,
and programmable vertical sync.
•
•
•
.•
•
•
The DP8350' Programmable CRT Controller
allqws a wide range of program contrOl:
•
Characters per Row
Character Rows per Video Frame
Character Field (both number of
dots/character and number of scan
" lines/character)
8,12
Internal Crystal Controlled bot Rate
Oscillator
.
.Externai Dot Rate Clock Input
Buffered Dot Rate Clock Output
Timing Pulses for Character Gl:}neration
Character Memory Addressing
Scrolling Capability
Internal Cursor Addres.s Register
Internal Row Starting Address Register
Programmable- Character Field Size (up
t016 x 16)
Programmable Character/Row (5 to 110)
Programmable Character Rows/Frame (1
to 64)
Programmable Horizontal and Vertical
Sync. Outputs
Programmable Cursor Enable Output
Programmable Vertical Blanking Output
50/60 Hz Refresh Rate
Inputs and Outputs TIL Compatible
Single + 5V Power Supply
ADDRESS --.:13:::.71~_ _ _ _ _ _ _ _ _ _~
ENABLE
REGISTER
LOAO
REGISTER
SELECT A
REGISTER
SELECTB
HORIZONT AL
SYNC
LINE BUFFER
RECIRCULATE
ENABLE
VERTICAL
SYNC
LlN~
CLEAH
COllNrfR
VERTICAL
BLANKING
LINE RATE
CLOCK
CURSOR
ENABLE
LINE BUFfER
SYSTEM
CLOCK
CLEAR
CHARACTER
GENERATOR PROGRAM
LOAD VIDEO
SHIFT REGISTER
50/60 Hz
CONTROL
[JOT RATE
CLOCK
(40)
~
(17)
..
..
(6-9)
LINE COUNTER OUTPUTS
EXTERNAL
CHAR/LIlliE
V"
(20)
OND
151
N.C .
CLOCK
rc
VIDE o
INTER FACE
07-00
BI-DIRECTIONAl
BUFFER
"'I
I
I
~
- ...
...
...
S
,..
~
~
AI5-AO
..
...
I
I
I
INS8285
CHAR
GEN
OUTPUT
VIDEO
RAM
~
...
VIDEO
OUTPUT
,.
.. ...
DISPLAY
THREETERMINAL
MONITOR
CONTROL
BUS
TRI-STATE
BUFFER
...
~
•
,.
REGISTER
LOAD
LOGIC
•
...
~
b..
,
'"
"NTROLBUS
0
B
U
I
...
M
I
~
I
OP8350
XI
X2
~.~
I
I
8-13
TO
ATTRIBUTE
DECODE
HOfllZONTAL
SYNC
,.
VERTICAL
SYNC
.
CURSOR
ENABLE
8.7 INS8285 CHARACT~R G.ENERATOR
Features
The INS8285 is a 64-charac;:ter bipolar character
generator with a serial outP\Jt. The I NS8285 performs the system functions of parallel-to-serial
shifting, character address -------. OVERflOW
---t--t-----.
' - - _ - - - -__- - - - - - - - _ . . . . CONY COMPLETE
100
ANALOG Vee
VFlLTER
---t--t-----.
--+--+--,
C
L,-----------------.-SIGN
nl-'------------------' ~+VREF
fll.SWl
SW2
-VIN
.. -VREF
1-l---44--4>-----'----'-.--.,-----'-.---------~-
VFB __- - - - - - - - '
8-16
INSB294
INSB202
V4-V1
M
I
A4-A1
V5
A5
V6
AS
V7
A7
+VINI......t - -
-VIN .....I I - -
VB
C
R
0
B
U
AB 1......1-..-.;~-tSI GN
START
CONVERSION
S
£)o-----IoLE
\
0,
~-~----------------------~·101
o
~----~----------------------------_;..IOo
r----I CONVERSION
NOTE: This application shows free running conversion,
i.e., start conversion connected to conversion complete.
Because there is a finite (low) probability that internal
latches will be modified while the microprocessor is
accessing the data, the service program should read the
data twice and compare the two samples to insure its
validity.
8-17
COMPLETE
MEMORY
I'r--
Chapter 9
Communications
Components
Part Number/Description
-
INPUTIOUTPUT
r-M
SERIES 8000
MICROPROCESSOR
"
!J-
I
C
R
0
B
U
5
...,j
TM-
,.......,
PERIPHERAL
CONTROL
• Trademark, National Semiconductor Corporation
INS8250
Asynchronous Communications
Element (ACE)
INS8251
Programmable Communications
Interface
INS1671
ASTRO Communications Interface
.'..
"", ".j.
~
oo
Communications'
Components
3
3
c:
_.
:::J
n
Q)
_.
o
9.1 GENERAL DESCRIPTION
The Communications Components provide the
serial link to either a data communications link
or an RS·232 interface (or any other type inter·
face) for a microcomputer. The programmable
components in this chapter allow the user ex·
treme flexibility when implementing serial data
transfers.
The general operational concepts of the
devices in this section are the same; parallel
data transfers occur on the MICROBUS to/from
the interface device and the interface device
then converts and transmits the data to/from
the peripheral device interface drivers over one
or more serial 110 lines. In addition to performing the data transfer functions, the Communications Components also provide control
signals to both the system and the peripheral
interface to facilitate data transfers.
:::J
Detailed parametric information on each of the
Communications Components is contained in
appendix D, Device Data Sheets.
9.2
INTERFACING THE COMMUNICATIONS
COMPONENTS
The communications components provide the
serial interface to either a data communication
link or an RS-232 interface. The devices contained in this section are all softwareprogrammable which allow the ,user greater
flexibility when implemeting serial data
transfers.
Due to the memory-mapped 110
capability of the I NS8080A, these devices are
compatible with the MICROBUS as far as data
transfers are concerned. The remaining nonMICROBUS control signals on the communications components are for use with the
peripheral devices.
9-1
(I)
oo
3
o
"C
:::J
CD
:::J
( I)
9.3
INS8250 ASYNCHRONOUS
MUNICATIONS ELEMENT (ACE)
COM·
The INS8250
is a programmable Asynchrdnous Communications Element (ACE;:) that
functions as a serial data input/output interface. The INS8250 performs serial-to-parallel
conversion on data characters 'received from
a peripheral device or a MODEM, and parallel-toserial conversion on data characters received
,trom the CPU. An important feature available
'with the INS8250 is the availability of the CPU
to read the status of the INS8250 at any time.
Features
•
•
•
•
•
•
Adds or Deletes Bits (Start, Stop, and
Parity) to or from Serial Data Stream
Full Double Buffering
Independently Control/ed Control
Functions
Programmable Baud-Rate Generator
Complete Status Reporting Capabilities
TRI-ST ATE Bus Drivers
INTERNAL
DATA BUS
RClK
A,
A,
A2
eso
DOSTR
DOSTR
DOIS
CSOUT
XTAll
XTAL2
rn
ffi
ii'fR
iiSR
iIT!b
If!
OUll
DUT2
(30)
INS8250
07-00
01-00
MEMRnriToR
MEMWori/nw
ooSfR
tNTR
INTRPT
M
C
RESET
MR'
A'
B
U
A'
5
A2
ElA
DRIVERS
R
0
SOUT
OISTR
A'
.
TO RS·232
INTERFACE
A'
A2
ADS
XTALI
DOSTR
CS
'"
_
OISTR
I
ffi
eS1
'"
XTAL2
~
eso
9-2
3.012MHI
fNTRPT
9.4
INS8251 PROGRAMMABLE
MUNICATIONS INTERFACE
COM·
The INs8251 is a programmable Universal Syn·
chronous/Asynchronous Receiver/Transmitter
(USART) that provides·a variety of synchronous
and asynchronous serial data communication
. options.
The INS8251 performs serial·to·
parallel conversion on data characters received
from a peripheral device or a MODEM, and
parallel·to·serial conversion on data characters
received from the CPU. This device is par·
ticularly suitable for implementing BISYNC pro·
tocol.
Features
•
•
•
•
•
•
Synchronous and Asynchronous Full
Duplex Operation
Selectable Character Length
Selectable Baud Rates
Transmission Error Detection Capabilites
Double Buffering of Data
TTL Compatible
INTERNAL
DATA BUS
"·5.2)
11.28.27)
(19)
TRANSMIT
BUFFER
07- 00
RESET
(151
TxRDY
eLK
TRANSMIT
CONTROL
C/O
iiii
Wi!
'"
....!!L-TiC
RECEIVE
BUFFER
POWER
(18)
III
Ax"
.{.....!!!L.
+5V
~GNO
SUPPLY
(14)
RxRDV
Rill
SYNDET
rc
INSBZ51
INTRk
. Tx E
INTRj
RxRDV
INTR;
TxRoV
~
M
I
C
R
0
B
U
S
SERIAL
DATA OUT
07·00
RESET
-MErolR
-MEMW
-cs
AD
07·00
Txo
RESET
Rx o
-Ro
-oTR
RTS
-oSR
-eTS
-WR
-
es
C/O
-TxC
,
BAUD
RATE
GENERATOR
9·3
..
TO R8-Z32
INTERFACE
EIA
DRIVERS
-RxC
+ +
0-
SERIAL
DATA IN
9.5
INS1671 ASYNCHRONOUS/SYNCHRON·
OUS TRANSMITTER/RECEIVER
General Description
Features
The INS1671 is a programmable Asyn·
chronous/Synchronous Transmitter/Receiver
(ASTRO) chip housed in a standard,'40'pin dual·
in·line package. The chip, which is fabricated
using N·channel silicon gate MOS technology,
pr,ovides a serial data input/output interface in a
bus·structured system. The chip is capable of
full duplex operation with synchronous or ~syn·
chronous data communications systems.
•
•
The INS1671 is designed to operate on a
multiplexed, bidirectional bus with other busoriented devices. The functional configuration
of the INS1671 is programmed by the system
software via the bus and all parallel data
transfers within the system are accomplished
over the bus lines. In additon, the INS1671 contains a provision for hardwiring a unique 5-bit
identification code to a chip, thereby allowing
up to 32 INS1671 devices to be addressed via
the multiplexed bus.
•
•
•
•
•
•
•
•
•
•
INS1671 General System Configuration
Synchronous and Asynchronous Full
Duplex Operations
Synchronous Mode Capabilities
- Selectable 5·to-8·Bit Characters
- Two Contiguous SYN Characters
Provide Synchronization
- Programmable SYN and OLE
Characters Stripping
- Programmable SYN and SYN-DLE
Characters Insertion
Asynchronous Mode Capabilities
- Selectable 5-to-8·Bit Characters
- Line Break Detection
- 1-, 11/2-, or 2-Stop Bit Detection
- False Start Bit Detection
- Automatic Serial Echo Mode
DC to 1M Baud Rate
8 Selectable Clock Rates (4 Programmable)
Transmission Error Detection Capabilities
- Parity·
- Overrun
- Framing
Double Buffering of Data
8-Bit Bidirectional Bus for Data, Status,
and Control Words
All Inputs al'1d Outputs TTL Compatible
On-Line Diagnostic Mode
Reduces System Component Count
Direct Plug-In Replacement for Western
Digital FD1671
PERIPHERAL
~I
INTERFACE
/
I
IN$1671
rl
DATA IADDRESS BUS
SYSTEM
PROCESSOR
~L
I+LOCAL 32X
CLOCKS (Rl . R4)
CONTROL BUS
TRANSMITTER
SECTION
t
n
RECEIVER
SECTION
~r
.I
L
.I
9-4
J
CONTROL
SECTION
t
BUS
INTERFACE
SECTION
MEMORY
I
I
SERIAL DATA OUT
I
SERIAL DATA IN
J
I
J
I
I
(9)
TIMING & CONTROL
COMMUNICATIONS
LINK
(MODEM OR
DATA SET)
r'"
MEMORY
~
,.......,
Chapter 10
Development
Support
INPUT/OUTPUT
M
SERIES 8000
MICROPROCESSOR
'-
J-
I
C
R
0
B
U
S
PERIPHERAL
CONTROL
TM·
~
COMMUNICATIONS
~
~
* Trademark, National Semiconductor Corporation
c
Development
Support
CD
<
-
CD
o
3
"C
-en
CD
::::s
10.1 GENE.RAL DESCRIPTION
National supports its microprocessor-based
systems with a variety of software routines,
hardware development systems, applications
engineering services, and training services.
To ensure full support capability, all of the ancillary devices required are supplied by National and have been thoroughly tested in
systems produced by National. The BOBOA
family is supported by industry-standard design
kits, easy-to-use development systems, and a
full complement of cross and resident
assemblers. Various components and software
also are available to support the BOBOA family
from experimentation to final production.
Design aids for the BOBOA provide unique
development and test capabilities, including
comprehensive system control and debug, the
examination/modification of all CPU registers
and memory, and simulation of the user's
PROM, RAM, or I/O. All of the capabilities and
speed of execution of the BOBOA microprocessor chip are available for the efficient implementation of the target system.
10.2
UNIVERSAL DEVELOPMENT SYSTEM
(UDS1)
The Universal Development System (UDS1) is a
disk-oriented operating system that can be
used in the development of any NSC microprocessor-based system. UDS1 provieds all the
capabilities of the Universal Development
System, and further increases throughput and
flexibility by providing the convenient mass
storage capability of dual floppy disk drives.
See figure 10-1, pictorial of UDS1 and figure
10-2, UDS1 block diagram.
/------
_r_r+--,(/---...-;---
TTY INTERfACE
PACE MICROPROCESSOR
DEVELOPMENT SYSTEM
DUAL FLOPPY
DISK DRIVE
DISK/CRT
INTERFACE
HIGH·SPEED
PAPER TAPE fJEADER
(OPTIONAL!
TELETYPE ® (TTY)
(OPTIONAL)
CRT
Figure 10-1. Universal Development System (UDS1)
10·1
c
"C
"C
o....
lL------------------------1
DUAL DRIVES
1
1
ROM-
I
I
....IIJr~ '''''0
PRINTER
~
DISC/CRT
INTERFACE
CARD
1
'--_ _C_R_T_ _
-,.11. 1
(MONITOR)
T"
I
LO~...
PRINTER
·1 INTC~:~CE ~
1
'--.,.-_ _ _-...1.
l.
[JRAM2:12K
I
I
I
r
I
r---'----"
JfR
I
HIGH-SPEED
I
:
PAPER TAPE
READER (Or-'ionol)
1
1
I
L _______ ...l
r - - - -'----,
II
TELETYPE@
I1____
(TTY)
• _______
(Optional)
L
Ji---
I
I
l
TTY/CARD
READER INTER-/~~---~
I
I
I
L _______________________ .J
I
FACE CARD
ROM - PACTTY
Universal Development System Enclosure
Figure 10-2. UDS1 Block Diagram
The Universal ,Development System and its
associated peripherals provide a means
whereby software for an application system can
be readily developed, egited, and assembled.
The inherent features of the Universal Development System make it a flexible tool suitable for
use in developing a wide variety of microprocessor - oriented ·software applications. The
combination of a CRT and the Universal
Development System provides the minimum
equipment necessary for immediate evaluation
and development of software using UDS1.
Getting Acquainted With UDS1
This paragraph summarizes the procedures required to "turn on" and initialize UDS1, to access and use the various system programs.
1.
Turn on the power to the dual floppy
disc drives, and insert the Master
Diskette containing the system programs (refer to the UDS1 Users
Manual).
.
2.
Initialize UDS1 by setting the appropriate switches on the PACE
Development System Control Panel
(refer-fo iheUDS1 Users Manual). The
Monitor System will then ask you to
identify the available peripheral
devices by displaying the following:
The Programmers and Operators Controls
facilitate software development/debugging and
provide a convenient means of controlling UDS
operation. Complete descriptions of the Programmers and Operators Contro·ls are
presented in the Universal Development
System Users Ma.nual.
MON'ITOR
PERIPH:
The Universal Development System can be
user-expanded to include the optional
peripherals that are available to ease software
development. In additon, to ease expansion,
the basic Universal Development System is
prewired to accept additonal memory aM
peripheral interface cards.
3.
Type in the peripheral name designations. For Example; if all peripherals
are available, type in • AL. The Monitor
will then ask you to type in a command
by displaying the colon prompt symbol
(:).
10-2
4.
10.2.1.2 Disk/CRT Interface Card
Transfer control to the program you wish
to access by typing in the Execute Disc
File Command. For example, to transfer
controlto the Editor, type the following:
@EDITOR
The Diskllnterface Card provides interfacing
between the microprocessor, the dual disk
drives, and a CRT terminal. The disk input/·
output firmware, contained in ROMs .mounted
on the Disk/CRT Interface Card, provides con·
trol of the disk mechanisms, data transfer, and
a diskette formatting.
@
The Editor will then prompt for a com·
mand with a question mark (?). Editor
commands are described in the Editor
Users Manual.
5.
PDSKIO (PACE Disk I/O) is the firmware
program responsible for the communication
between the Universal Development System
and the floppy disk. It resides on the Disk/CRT
Interface Card and supports a two drive disk
system. The UDS1 TTY firmware on the
TTY/Card reader Interface Card handles data
transfer between PACE and
terminal at
transmission rates of either 300 or 1200 baud to
the EIA RS·232 I nterface and 110 baud to the
20·milliampere current loop for the Teletype
(TTY). For additional information, refer to the
Universal Development System Users Manual.
To transfer control from the Editor to
another Main Program, type in the com·
mand "@ filename." For example, to
transfer to the assembler, type the
following:
?@P8012ASM
@
Or, to return to the Monitor, type:
6.
Upon completing your work at the Con·
sole, first remove your diskette(s) from
the dual floppy disc drives, then turn off
the power to the. drives and the Control
Panel.
See Universal Development
System Users Manual and Universal
Development System Editor Users
Manual. See also Preface for a list of
related publications.
10.2.1.3 Universal Development System
The Universal Development System is a flexible
tool designed to facilitate the functions and
operations involving UDS1. The system pro·
vides an economical and convenient means of
expediting the development of both hardware
and software with UDS1.
UDS1 requires an Universal Development
System with 12K of memory and a heavy duty
power supply for its minimum configurati!?n.
Development Systems with model serial
numbers 6150 and above will accommodate the
required hardware without any additional
modifications.
10.2.1 Hardware Support
The UDS hardware components consist of dual
floppy disc drives mounted in a stand·alone
enclosure, a Disk/CRT Interface Printed Circuit
Card (containing disk input/output firmware),
and the Universal Development System. UDS1
will also support several peripherals, such as, a
Teletype (TTY), a Documation M300 Card
Reader a Centronics 702 High·Speed Printer, a
Plessey 1000' CPS Paper Tape Reader, and a
Hazeltine 1500 or equivalent CRT; refer to figure
10.2.1.4 Peripherals
Peripherals linked with the UDS1 Development
System are as follows:
• Documation M300 Card Reader
• ASR·33 Teletype (TTY)
• Plessey 1000 CPS Paper Tape Reader
• Centronics 702 High·Speed Printer
• Hazeltine 1500 Video Display Terminal
10·2.
10.2.1.1 Dual Diskette Drives
The dual disC drive enclosure contains two flop·
py disc drives and the power supplies required
by the drive electronics and mechanisms. Each
drive can accept a diskette capable of storing
over 2.5 million bits (aproximately 158,000 16·bit
words). A single·element read/write head is us· ed in each drive and straddle erase elements
provide erased areas between data tracks to en·
sure diskette interchangeability between
drives. Each diskette contains 77 tracks, ad·
dressable as 0 through X'4C, or 616 sectors, ad·
dressable as 0 through X'267.
10·3
The user has the option of using the various
peripherals by connecting the hook·up (~xtend.
ed from the peripheral) to the designated
pmipheral interface card enclosed within the
Universal Development System (refer to figure
10-:3).
10.2.2 Software Support
The main software components of the Universal
Development System are as follows:
CRT
FlOPPY DISK
PRINTER
(A2-J5) CENTRONICS PRINTER
INTERFACE CARD (OPTIONAL)
(A2-J4) FlOPPY DISK/CRT
INTERFACE CARD
(A2-J3) MEMORY STORAGE
CARD (12-16K) (OPTIONAL)
(A2-J2) MEMORY STORAGE
CARD (8-12K)
(A2-J1) MEMORY STORAGE
CARD (4-8K)
(A1-J6) MEMORY STORAGE
CARD (O-4K)
'-____
(A 1-J5) ROM MEMORY CARD
(Al-J4) CRiTTY INTERFACE
CARD
CARO READER
(A1-J3) UDS
CPU CARD
TTY
HIGH SPEED TAPE READER
(A1-J2l IMP-16
.cARD (OPTIONAL)
(A1-J1) CONTROL PANEL
INTERFACE CARD
Figure 10-3. Top Internal View of Universal Development System
10-4
Stored in ROM
10.2.2.7 UDSl Editor (EDITOR)
• Monitor System (MONITOR)
• File Input/Output Subsystem (FIOSYS)
Stored on Diskette
• File Manager (PACFM)
• Supporting System Software
10.2.2.1 Monitor System (MONITOR)
The Monitor System (MONITOR) resides on the
Read·Only Memory (ROM) card. It provides con·
trol over system configuration and linkage to
the Paper Tape Loader, Card Read Loader,
Diskette, and the Debug Subsystem.
The UDSl Editor program (EDITOR) allows a
user to read, write, correct, display, and save
source files. The Editor may be used to
generate source files in a format suitable for in·
put to the PACE assembler, other cross
assemblers, or the PACE BASIC interpreter; or
the Editor may be used to generate documenta·
tion such as lists, tables, directories, or
manuals. Refer to the UDS Editor Users Manual
for a complete description of the Editor
program.
10.2.2.8 Linkage Editor (LINKEDIT)
10.2.2.2 File Input/Output Subsystem (FIOSYS)
The File Input/Output Subsystem (FIOSYS) is a
collection of software subroutines that reside
on the Read·Only Memory (ROM) Card. These
software subroutines provide the. means of
peripheral communication required by the remainder of the Universal Development System.
The Linkage Editor (LINKEDIT) is a relocating
and linking loader program that links one or
more Load Modules (LMs) produced by the
PACE Resident Assembler
(PAC12ASM).
LlNKEDIT performs relocation and resolves ex·
ternal linkages, and writes a memory image to
the disc in a format suitable for bootstrapping
into memory for execution.
10.2.2.3 File Manager Program (PACFM)
Each LM must be in the standard format (as
described in the PACE Assembly Language
Programming Manual). Each LM and the com·
mands that control the loading process are
then input to LlNKEDIT. LMs can be input from
cards, paper tape, or from the disc itself.
The File Manager Program (PACFM) is a diskresident manager of the directories on the disk.
It gives the user control over file maintenance,
space allocation and deallocation, and file protection. The files are identified by name, with
the sector assignment handled automatically.
10.2.2.9 Diskette Diagnostic Program (PFDDIA)
10.2.2.4 Supporting System Software
The Diskette Diagnostic Program (PFDDIA) is a
complete diagnostic program for checking out
the diskettes and the disc drives. In addition,
PFDDIA initializes the diskette, the diskette's
File Directory, and system tables.
A disc-resident software package resides on a
Master Diskette and includes a number of programs provided with the Universal Development System. These programs are described.
briefly below.
10.2.2.10 UDS1 Utility Programs
The UDS1 Utility Programs consist of the
following:
• DPATCH (disc·patching utility)
• LIST (file-listing utility)
• IPCOPY (IMP to PACE copy)
• UPROM (Universal PROM Programming
Software)
•
XREF (Symbol-Listing Utility)
10.2.2.5 PACE 12K Resident Assembler
(PAC12ASM)
The PACE 12K Resident Assembler
(PAC12ASM) is a three-pass assembler, with
macro capabilities, that loads and executes on
a PACE Development System. The assembler
accepts free-format PACE assembly language
source statements as source input, assembles
the statements, and outputs a program listing
and/or a load module (LM) on paper tape or
diskette. The load module can be loaded by the
appropriate PACE loader, then exeouted, or it
may be c.onverted to a Main Program by
LlNKEDIT. The operating instructions for the
assembler are contained in the PACE Macro
Assemblers Operating Instructions. Information on the PACE assembly language, inc.luding
instructions, directives, the assignment statement, macros, and the assembler input/output
formats is contained in the PACE Assembly
Language Programming Manual.
DPATCH is used duringdebugglng to make cor·
rections to Main Program files on diskettes.
LIST is used to list any file on a diskette and
provides numerous editing and formatting op·
tions. IPCOPY is used to convert an existing
file on an IMp·16P diskette to an equivalent file
on.a PACE diskette. UPROM is used to convert
a PACE, 8060,8070, 8080, or IMP·16P LM to the
proper format for generating a PROM or ROM.
XREF is used to· generate a oross· reference
listing of tlie symbols contained in a symbolic
file on disk.
10.31NS8080A CROSS ASSEMBLER
The' UDS1 Macro Assembler Programs are.
three·pass assemblers that are loaded and ex·
10.2.2.6 Cross Assemblers for 8060, 8070, and
8080 (See Section 10.3)
10·5
Parameter driven Macros
Local Symbols
Parameters called by number
Macro Time Looping
Nested Macro Calls
Nested Macro Definitions
Recursive Macro Calls
ecuted on a Universal Development System.
The assemblers accept free-format assembly
language source statements of a target
microprocessor as source input, assemqle the
statements, and output a program listing and/or
a load module (LM).The target microprocessor
is the microprocessor that will execute the object (machine) code contained in the. load
module. For example, the UDSl Macro,
Assembler accepts 8080 assembly language
source statements. and produces a load
module. The load module may be loaded by an
appropriate loader and executed by the target
microprocessor. The load module may also be
used to program PROMS.
• Absolute Load Module Generation
• Relocatable Load Module Generation (PACE
Assembler Only)
• Assembly Time Operators( + ..:.
% &!
<' = > "EQ NE)
• Parenthesized expressions (SC/MP and
8080 Assemblers Only)
• . Diagnostic Messages .that include Error
Position in Soun;:e Line
• Wide Variety of Directives
• US.er Control over allocation of Literal Pool
and Pointer Space (PACE Assembler Only)
*/
Salient features of the PACE Assemblers are as
follows:
• DOS Capabilities (12K Assemblers Only)
• Conditional Assemblies using the following
Operators
IF Directive
ELSE Directive
ENDIF Directive
. IFC Directive
• Macros with the following features
8080A
For information on the assembly languages,
see the appropriate Assembly Language Programming Manual,. Input/Output device options
are listed in table 10-1.
The UDS1 Editor provides the normal method
used for generating and/or correcting source
programs on p,aper tape or diskette.
Microprocessor programs may be assembled by using the 8080A cross assembler
program 'in the Universal Development System (UDS1).
Program Number
Program Name
Title and Description
P8012ASM
PACE 8080 Cross-Assembl.er 12K version. An 8080 Cross-Assembler for
, the Universal Development system
requires 12K anq uses NSC
Assembler Directives.
430305394-000
Table 10-1.
Assembler Peripheral Options
'Function
Peripi1eral Options.
Control Input
"Source Input
Teletlee® or CRT/Ke~board
Teletype Paper Tape Reader
High Speed Paper Tewe Reader
Card Reader (12K and DOS only)
Dual Diskette (12K and DOS onlv!
Teletype Printer
High Speed Printer
CRT
Dual Diskette (12K ~nd DOS only)
Teletype Paper Tape Punch
Dual Diskette (12K and DOS only)
Prpgram ListingOl,ltput
Load Mod.uleOutput
".
/
' ..
"
10·6
SOURCE INPUT
SOURCE
LISTING
OUTPUT
EDITOR
SOURCE
SOU RCE
OUTPUT
INPUT
MACRO
ASSEMBLER
(EXECUTES ON
A PACE MDS)
PROGRAM
LISTING
OUTPUT
DISKETTE
112KAND
UDSONLY)
DISKETTE
OR (12K AND
UDSONlY))p.. . . . . .__. .__________. .~1
LOAD MODULE OUTPUT
DOWN
lOAD TO
80/10
SYSTEM
OR BlC 80 P
OR PROTOTYPING ,SYSTEM
Figure 10-4. Operational Sequence of the UDS1 Editor and Assemblers
10-7
10.4 PROM PROGRAMMING
10.4.1 UDS1 PROM Programmer (Peripheral)
ports, such as a port for a serial link to one or
more prototyping systems.
Because of the requirement that micropro·
cessor based equipment be. ready to operate
when power is turned on, most manufacturers
store their applications software in read-only
memory (PROMs or ROMs) so that it is always
ready for execution.
An additional advantage of the Model 7 and 9
programmers is the customer suppport provided by Data 1/0. They provide publications such
as PROM comparison charts, field bulletins
which describe improved programming techniques, and technical bulletins which also
discuss programming techniques and specific
subjects related to programmers and specific
PROMs. They also provide field service, usually
through a direct field service department.
Even in an environment where application programs are read into memory from off-line
storage for exaction, it is advantageous to put.
often·used routines in ROM or PROM so that
they are available without the overhead involved in loading them each time.
The Model 7 Programmer is a fairly basic programmer designed expressly for interfaCing to
a microprocessor through a serial interface of
up to 9600 baud. Although the Model9 is priced
higher, it can be used stand alone as well as
. connected to a microprocessor system.
A critical factor in the development of
'microprocessor software is the capability of the
user, once he has completed initial checkout,
to program PROMs with the necessary routines
and data for continued checkout and, perhaps,
initial production. Then, after his product has
been in the field for initial shakeout, he will
need to make programming tapes from these
same PROMs in order to commit his product to
masked ROMs for the additional cost savings.
By insertion of the proper personality card and
socket adapter, the PROM Programmer can be
set up to program any of the most widely used
PROMs:
National
One of the major advantages of owning a
"Universal Development System" is that program development may be done right in. the lab
without the need for outside services.
2708,2716, 1702A, 5204, 54/74S570, 54/74S387,
54/74S287, 54/74S470, 54/74S472, 54/74S572,
etc.
The Data 110 Model 7 and 9 PROM Programmers
connnected to our Universal Developmen~
System (UDS1), provide these facilities. (See
PROM Prograsmmer Software Manual and Data
1/0 Company for peipheral orderinginformation.) This gives the UDS1 user a complete, integrated, efficient capability f.or microprocessor software development. .The Model 7
and 9 programmers are directly interfaced to
UDS1 via a slave RS-232 serial I/O port.
Intel
1702A, 2704, 2708, 2716, 8748
Motorola
2,5003, 10149 ECl, 68708 (2708)
AMD
2708, 1702A
The software package to support the programmer is PROM-independent.· The Model 7 and 9
are "universal" PROM Programmers, which can
program any of the widely used PROMs with only a change of a personality card or adapter.
Generally personality cards and adapters are
available as soon as the PROM itself is
'
available.
Electronic Arrays
2708
Fairchild
93438,93448,93452,93453
The UDS1 PROM Programmer is interfaced to
UDS through an RS-232 serial port. This port is
located on a card which contains other RS-232
As other PROMs are developed, additional personality cards and socket adapters allow use
with the PROM Programmer.
10·8
The capabilities of the PROM Programmer and
the UDS1 Software package are:
•
•
•
•
•
•
•
•
•
•
•
Input of any standard NSC Load Module
(LM) from paper tape or diskette.
Input of UDS Main Program (MP) files
from diskette.
Input of binary (BI), binary complement
(BC), or BPNF PROM programming tapes.
Input or editing of hexadecimal or binary
data from system console.
PROM duplication, by performing READ
of one PROM; then PROGRAM a
duplicate PROM.
Generation of BI, BC, or BPNF ROM programming tapes from input data or PROM
data.
Test of PROM for proper erased condition.
PROM verification.
Printout of PROM data, memory data,
PROM checksum or write·buffer
checksum on console or high-speed
printer.
•
•
•
Extensive legality checks of input data.
Handling of portions of single programs
as well as of multiple programs.
Automatic setting of buffer to un·
programmed state.
Interruption of long operations other than
programming and, loading or punching of
bi nary tapes.
Programmipg of PROMs directly from
UDS1 memory.
The Data 1/0 Model 7 and 9 programmers
operate as a peripheral to National's UDS 1 as
shown in figure 10·5.
Detailed information on the Model 7 and 9
PROM Programmers and generCiI information
on PROM usage and PROM programming can
be obtained from:
Data 1/0
990 East Arques Avenue, Suite 106
Sunnyvale, California, 94086
(408)732-8246
TTY/CRT
HIGH-SPEED
PAPER TAPE
READER
UNIVERSAL
PROM
PROGRAMMER
FLOPPY
DISK
PRINTER
UNIVERSAL
ICE BOX
UDS
Figure 10-5 Universal Development System Configuration
10·9
10.4.2 UDS
Serial Link Card
This optional card available at extra cost, plugs
into a Universal Development System (UDS1).
The card has an RS-232 Port which can be used
to link the Data I/O Prom Programmer to the
Universal Development System.
See section 10.4.1
10.5
•
The BlC 80/10 is a self-contained single
board computer. It Includ'es the central
processor, system clock, RAM and ROM
memories, I/O lines, serial communications interface, and the bus logic and
drivers on a 6.75 inch, by 12.00 inch
printed circuit board. The BlC 80/10 is
plug compatible with SBC 80/10.
SERIES/80 FAMilY INCLUDING
UNIVERSAL PROTOTYPE, BOARD
(BlC905)
•
This section presents a brief description of the
devices available.
Series/80 BlC 80/11,80/12,80/14
The BlC 80/11, 80/12, and 80/14 share all
basic features and capabilities of the
BlC 80/10 but add 'jumper-selectable I/O
pins for RS-232 interface and have
greater memory capacity.
Series/80 from National Semiconductor is an
expanding new concept in OEM computer planning and design. A growing and varied family of
microcomputer products based on the National
BlC 80/10 Board level Computer, Series/80
gives the user more options for flexible design
by offering an increasing variety of memory,
supporting periphrals, and design packaging
alternatives.
•
BlC 80/204
The BlC 80/204 is a plug-for-plug replacement for the Intel SBC 80/204. It is completely bus'compatible with Series/80
boards, system peripherals, and expansion boards. The BlC 80/204 has parallel
and serial interfaces, an interval timer for
three software-controlled 16-bit counters
(two of which may be cascaded to 32
bits), and eight vectored interrupts.
The BlC 80/10 isa direct plug-for-plug replacement for the sec 80/10.
Complete system design is faCilitated by a
variety of prototype packages, board chassis
and power supplies.
10.5.3 OEM Rack Mountable Computers (RMC
80·10,80/14,80/204)
National Semiconductor rack-mountable computers (RMC 80/10, 80/14, and 80/204) can be
easily incorporated into OEM'deslgned
systems. They are complete and self contained.
The National RMC line combines a
Series/80 Board level Computer with front
panel, on/off and reset switch, power> supply,
system monitor firmware, and capacity for up to
three Series/80 expansion boards .- all in one
3-V2 inch RETMA chassis.
10.5.1 Serles/80 System Design Aids (BlC 80P
Prototype Package)
,
Prototype Package includes:
•
•
•
•
Seriesi80 BlC 80/10
BlC 80 Board level Computer
BlC 604 System Card Cage
BlC 905 Universal, Prototype Board
BlC 910 System Monitor
The BlC 905 Universal Prototype Board is
available separately as are the other Items
listed. The BlC 905'allows the user to design
and construct customized BlC-related circuits.
The BlC 910 System Monitor is supplied with
the kit in two preprogrammed MM2708 ,
EPROMs. The Monitor enables the user to load, '
execute and debug BlC 80/10-related programs, and to examine and modify any RAM
location or CPU register.
"
10.5.2 Board-level Computers
The BlC 80110, 80/11, 80/12, 80/14, and 80/204
are complete computers on a board. They use
the National 8080A microprocessor and have
on-board RAM memory and sockets for ROM/PROM memory. Expansion boards are available
to increase system memory and I/O
capabilities.
10.5.4 Memory Boards
ExpansionMOS RAM boards of 16K, 32K, 4aK,
and 64K bytes and expansion ROM, PROM,
EPROM, cards in 16K or 32K capacities are
available. All are plug-for-plug replacements for
corresponding Intel SBC mem9ry boards.
10.5.5
Input/Output and Memory Expansion
Boards '
Input and output port capacity can be expanded
with boards that provide different configurations of I/O ports and expansion memory:
10.5.6 BlC, 604 System Chassis and BlC 614
Expansion Board Cage
\
The BlC604 system Chassis and BlC614 Expansiop Board Cage provide immediate and
10-10
economical solutions for housing, interconnection, and expansion of Series/80 systems.
Stand-alone BLC 604 or 614 Board Cage holds
up to four Series/80 systems. Stand-alone BLC
604 or 614 Board Cage holds up to four
Series/80 boards in a molded chassis with interconnection backplane, bus signal terminating
networks, and connectors.
10_5_7 RMC 660 System Chassis
The RMC 660 Systems Chassis suports the
Board Level Computer and full complement of
Series/80 expansion boards. The Chassis includes board cage for eight boards. The
Chassis includes board cage for eight boards,
seven-inch standard RETMA chassis, and BLC
665 heavy duty power supply. It also includes
power-fail detect for orderly power-down sequence, and has current-limited outputs with
overvoltage protection. Power on-off and reset
switches on front panel are connected to
system bus for external system control.
See appendix C for more detailed reference
material. For list of currently available
literature, refer to the Literature Index.
10.7 TRAINING
National Semiconductor operates two
microprocessor training centers:
in Santa
Clara, Calif., and in Boston, Mass. Each training center is fully equipped and professionally
staffed to provide students with a good mix of
hardware/software theory and hands-on laboratory experience. Courses offered are Microprocessor Fundamentals, 8060 SC/MP Applications, and complex peripherals. A brochure is
available that describes the courses.
Microprocessor Fundamentals - 4- V2 Days
10_5_8 BLC 635 Power Supply
Ready-made, low cost power for BLC 80/10,11,
12, 14, and 204 is provided by the BLC 635
power supply. It suppor,ts most configurations
of BLC memory, and I/O expansion boards. DC
power is provided on mating cables for direct
connection to BLC 604 System Card Cage. The
BLC 635 senses AC power failure and
generates a TTL signal for orderly system
power shutdown. It has"current-limited outputs
with over-voltage protection, and 100, 115, 200,
230, VAC input voltage; 50/60 Hz input frequ.ency.
A course intended for engineers, senior techniCians, managers, and others who may have little
or no experience with microprocessors or computers. The Fundamentals course provides a
sound introduction to microprocessors and
microcomputers and their potential applications. The course also provides a comparison
of various types of microprocessors, and provides an insight on their appropriate applications. Extensive lab sessions allow the participant to become familiar with use of Development Systems and microprocessor programming.
10_5.9 BLC 665 Heavy Duty Power Supply
OUTLINE
The BLC 665 supplies approximately twice the
rated current of the BLC 635. The BLC 665 will
power a fully loaded BLC 80110 and most combinations of seven additional expansion
boards.
See National Semiconductor publications:
• Series/80 BLC 80P Prototyping Package
Users Manual
• BLC 80/10 Hardware Reference Manual
• Series/80 Microcomputer System
Brochure
Monday - Getting Started
1. Microprocessor Concepts and Terminology
2. Review of Digital Logic, Boolean Algebra,
and Number Systems
3. Microprocessor Architecture, Instructions, Addressing
4. Introduction to Programming - Flowchart
ting, Coding
5. Lab - Operating a Microcomputer Load
and run a simple program
10.6 PUBLICATIONS
PUblications are available covering the various
devices manufactured by National Semiconductor. The available literature is grouped in
the following categories:
•
•
•
•
•
•
•
•
•
•
Tuesday - Learning the Tools
1. Assembly Language Instruction Set
2. Microprocessor Development Systems
3. Software Development Tools - Editors,
Assemblers
4. Lab - Using the Development System
Literature Index
Handbooks
Manuals
Linear ApplicationS, Vol I and II
Databooks
Guides
Product Selection Guides
Briefs
Individual Application Notes
.Individual Data Sheets
Wednesday - Getting Involved
.
1. Additional Addressing Modes
2. Programming Techniques
3. Software Development Tools - Loaders
4. Lab - Programming with the Development
System
10-11
Thursday - Putting it all Together
1. Microprocessor System Design Con~
siderations
2. Microprocessor Applications
3. The Floppy Disk Universal Development
System
4. High Leyel Languages
5. Lab - Develop a Moderately Difficult Program
. 7. Programmable Interface Tin'le'r -INS8253
. 8.DMA Controller - INS8257
. .
Day 3 - Floppy Disk Drive and CRT Termin.al
Design
1. i=loppy Disk Drive Overview
2. Floppy Disk Controlle'r/Formatter
-INS1771-1'
.
3. Keyboard Encoder- I NS8244
4. Programmable CRT Controlier - DP8350
. 5... Character Generator - INS8285/DP8678
6. Example System: CRT Terminal
.
Friday (Morning only) - Wrapping it up
1. Review, Questions and Answer Session
2. Survey of Microprocessors and I Appropriate Applications
3. Lab - Complete Programming Exercises
10.8
NATIONAL'S MICROPROCESSOR
USERS GROUP
National Semiconductor sponsors a
microprocessor users group and a monthly
newsletter, both calied COMPUTE, as .a service
to users and potential users of National's
microprocessors, and for anyone else. who is In·
terested in what is going on in the micro·
processor industry. This provides a forum for
members to exchange ideas, opinions, software, and products. National maintains the
group's software library as a service to COM·
PUTE members. Products, services, and soff·
ware. offered for sale by COMPUTE members
will often be published in the newsletter.
.
Complex Peripheral Chips for Microprocessors
.
-3 Days
This course is intended for the engineer with
microprocessor system design experience,
who needs applications information on the
many complex peripheral chips available for
microprocessors. Although oriented towards
the 8080A it is appropriate for ttlose using any
of the popular microprocessors (8085, Z80,
etc.). The MICROBUS™ is explained In detail,
followed by sessions on interfacing the various
support chips to the MICROBUsTM. This intensive course covers some 20.complex support
chips, so to keep the class ~easonably short,
lab sessions have not been included. This
course can save you weeks of time and stimulate new microprocessor ideas.
.
The newsletter Is packed with articles on
microprocessors and peripherals. In addition,
therel!-re:
• Product Announcements
• Application Notes
• Construction Projects
• Programming Hints
• Programming Aids
• Microprocessor Class Schedules
• Consultant Lists
• Announcements of Coming Events
• Literature Reviews
• Data Sheets
• Letters to the Editor
• Library Program Listings
• Contents
• . Services
• Classified Ads
OUTLINE
Day 1 - The MICROBUSTM, Paraliel Ports and
Other I/O Devices
1. Definition
2. Description - Data, Address, and Control
Bus
3. Interface - Implementing the MICROBUSTM
.4. Octal Latch - INS82C06/MM74CS74
5. 8 Bit I/O Port - INS8212
.
6. Bit Programmable Peripheral Interface
-I NS8254
7. Programmable Peripheral Interface
-INS8255
8. AID Converter - INS8292
9. Programmable Interrupt Controller
-I NS8259 .
.
'.
.
In summary, everything you need to know about
microprocessors. .
.
The software library Contains utility programs,
math routines, I/O routines, games,
assemblers, compilers, translators, etc. Most
of the library program listings are free; sOL/rce
paper tapes are available for a nominal charge.
Day 2 - Communications: Concepts and New
Devices
1. Serial Codes
2. 20ma Current Loop and RS232 Interfaces
3. Modems and Line Protocol (BiSYNC,
SDLC)
. .
4. Programmable Communications Interface - INS8251/1 NS826111 NS2651 '
5. Multi-protocol Com'munications Controlier - INS8274/1NS2652
6. Asynchronous Control Element - INS8250
National Semiconductor is not responsible for
software_ in the software library, and will not
. provide applications support for that software.
Descriptions published are those of t.he contributor, and National cannot guarantee their
accuracy or the applic~bility of the software.
Any product, service, or software offered for
10-12
sale in the newsletter is the responsibility of
the person or company who offers it. Publication in COMPUTE does not constitute endorsement by National Semiconductor. Of course,
any products or services offered for sale by National Semiconductor in the newsletter, will
carry National's normal warranty and applications support.
10.10
MICRO+ PROGRAM (QUALITY CON·
TROL AND TESTING PROCESS)
The MICRO + Program from National Semiconductor is a specially designed quality control
and testing process that ensures our micro-'
processor parts meet extraordinary standards
of quality and reliability. The MICRO+ Program serves users who cannot perform incoming inspection of microprocessors or who need
significantly better quality and higher reliability
levels than normally required.
You are invited to join COMPUTE, National's
microprocessor users group.
A lifetime
membership to COMPUTE will cost you only
$15.00 (DLR 15.00 for Australia) - a real bargain!
Users who specify MICRO+ processed parts
will find that the program offers the following
benefits:
10.9 TECHNICAL SUPPORT PROGRAMS
•
Reduces the cost of reworking assembly
boards
• Reduces field failures
• Simplifies system checkout
• Reduces equipment downtime
• Eliminates the need for, and thus the added cost of, independeht testing
laboratories
• Reduces the need for excess inventories
due to yield loss incurred as a resuit of
processing performed at independent
testing laboratories
• Eliminates incoming electrical inspection
To provide a high quality level to all outgoing
parts, an Acceptable Quality Level (AQL) is
established. The AQL is the percentage of faulty devices that escape detection during inspection and testing at the manufacturer's facility;
with the MICRO+ Program, the AQL is reduced
to such an extent that the customer can
eliminate incoming inspection and test.
National Semiconductor has the strongest onthe-scene technical support team· in the U.S
and abroad - of any semiconductor manufac·
turer. Our large network of independent sales
representatives and franchised distributors
is backed by our Field Application Engineers
(FAE's) and microprocessor applications
engineers. The FAE's are available domestically and internationally to offer on-site technical
assistance, and are equipped technically to
help analyze your application, translate your
needs into a viable hardware/software configuration, and then follow it through to system delivery. The microprocessor applications
engineers are National's home-base technicalsupport specialists who support the FAE's in
the field, and who help you use your
microprocessor most effectively; they are
always available to answer specific technical
questions regarding the use of National's
microprocessor and peripheral components.
10-13
r"r-
SERIES 8000
MICROPROCESSOR
~
r
,....
MEMORY
,.....
INPUT/OUTPUT
Chapter 11
Programming
M
I
C
R
0
B
U
S
TM"
,.....
PERIPHERAL
CONtROL
COMMUNICATIONS
~
~
• Trademark, National Semiconductor Corporation
."
'"'I
Programming
o
CC
'"'I
Q)
3
3
:::J
(Q
11.1
INS8080A INSTRUCTION SET
Five different types of instructions are included
in the 8080 instruction set. These are:
TWO-Byte Instructions
Data Transfer Group - moves data between
registers or between memory and registers.
Arithmetic Group Adds, subtracts,
increments or decrements data in registers
or in memory.
1....0...!,7.L1--L--''--L-.L-.£-.. .1.:..0~01
B t T
ye wo
Oata or
I..0-"7. I. --J'--........-'-~--"_L~-'OU
I I Address
Op Code
Three-Byte Instructions
• Logical Group - AND, OR, EXCLUSIVE OR,
compare, rotate, or complement data in
registers or memory.
• Branch Group - Conditional and unconditional jump instructions, subroutine call
instructions and return instructions.
Byte One
1071
1001 Op Code
Byte Two
1071
1001 Oata
Byte Three
1071
or
• Stack, 1/0 and Machine Control Group - 1/0,
stack maintenance, and flag control.
11.1.1
Byte One
1001 Address
Instruction and Data Formats
11.1_2
Memory for the 8080 is organized into 8-bit
groups called bytes. Each byte has a unique
16-bit binary address corresponding to its
sequential position in memory.
Addressing Modes
The 8080 machine code is stored sequentially
in memory. Multi-byte data is stored in successive memory locations, starting with the
least significant byte, and ending with the most
significant byte. The 8080 has four different
modes for addressing data stored in memory or
in registers:
The 8080 can directly address up to 65,536
bytes of memory, which may consist of both
read-only memory (ROM) elements and randomaccess memory (RAM) elements (read/write
memory). Data in the 8080 is sorted in the form
of 8-bit binary bytes:
• Direct
-Bytes 2 and 3 of the instruction
contain the exact memory
address of the data item. Byte 2
contains the low-order bits of the
address. Byte 3 contains the
high-order bits.
• Register
-The instruction specifies the
register or register-pair in which
the data is located.
• Register
Indirect
-The instruction specifies a
register-pair which contains the
memory address where the data
is located. The high:order bits
of the address are in the first
register of the pair, the low-order
bits are in the second.
DATA WORD
1071061051041031021011001
MSB
LSB
In the 8080, the Least Significant Bit (LSB), is
called BIT 0, and the Most Significant Bit (MSB),
is referred to as BIT 7 (of an 8-bit byte).
The 8080 instructions are one, two or three
bytes in length. Multiple byte instructions must
be stored in successive memory locations. The
address of the first byte is always used as the
address of the instruction. The exact instruction format will depend on the particular operation to be executed.
. Single Byte Instructions
• Immediate -The instruction contains the data
itself. This is either an 8-bit
quantity or a 16-bit quantity (least
significant byte first, mo'st significant byte second).
10...!,7.L1--L--I.--'
..
--''--L-.L10-,,-,01 Op Code
11-1
011
wise it is reset. This ~Iag is affected
by single preCision additions, subtractions, increments, decrements,
comparisons, and logical operations,
but is principally used with additions
and increments preceding a DAA
(Decimal Adjust Accumulator)
instruction.
Unless' otherwise directed by an interrupt or
branch 'instruction, the execution of instructions ,proceeds through consecutively increasJflg memory locations. A branch instruction can
··change the address of the next instruction to be
executed in either of two ways. They are:
• Direct
• Register
Indirect
-The brancn instruction contains
the addresa of the next instruction to be executed. Except for
the "RST" instruction, byte 2
contains the low-order address
and byte 3' the high-order
address.
11.1.4
Figure 11~1 indicates the format used for
describing each instruction. The symbols utilized are listed in table 11·1. (See page 11·3.)
11.1.5
-The branch instruction indicates
that the HL register pair contains
the address of the next instruction to. be executed. The highorder bits of the address are in
the H register, the low-order bits
in the L register.
Data Transfer Group
. This group of instructions transfers data between registers or between registers and
memory. Data may be transferred one byte at a
time or two bytes at a time, depending on
whether a single register or register pair is
specified by the instruction. Condition'flags are
not affected by any instruction in this group.
The RST instruction is a special one-byte call
instruction (usually used during interrupt
sequences). R$T includes a three-biffield; program control is transferred to the instruction
whpse (iddress is eight times the contents of
this three-bit field.
11.1.3
Presentation Format
MOVE REGISTER
MOV
10
Condition Flags
!
r 1,
1 I
r2
S
D
(r1) - (r2)
The content of register r2 is moved to. register
r,1.
'
There are five condition flags associated with,
the execution of the 8080 instructions. They are
Zero, Sign, Parity, Carry, and Auxi.liary Carry.
Each is represented by a 1·bit register in the
CPU. A flag is "reset:' by forcing the bit to O.
Unless otherWise indicated, when an .instruction affects a flag" it does so in the following
manner:
Cycles:
States:
Addressing:
Flags:
1
5
register
none
MOVE FROM MEMORY
Zero: If the result of an instruction has the
value 0, this flag is set; otherwise It
is reset.
MOV
Sign: If the, most Significant bit of the
result of the operation has the value
of 1, this flag is set; otherwise it is
.
reset.
(r) - ((H) (L))"
r,
M
D
S
TI>1e content of the memory location, whose
address is in registers Hand L, is moved to
register r.
Parity; If the modulo 2 sum of the bits of .
the. result of,the operation is 0, (Le.,
if the result has even parity), this
flag is set; otherwise (i.e., if the
result has odd parity) it is reset.
Cycles:
States:
Addressing:
Flags:
Carry: If the instruction resulted in a carry
,(from addition), or a borrow (from
subtraction or comparison) out of
the high-order bit, this flag is set;
otherwise it is reset.
2
7
register indirect
none
MOVE TO MEMORY
a
MOV
M'
,
S
Auxiliary If the instruction caused a carry out
Carry: of bit 3 and inlo bit 4 of the resulting
value, the auxiliary carry is set; 'other-
! '
((H) (L)) - (r)
,11-2
}
}
SUBTRACT REGISTER
SUB
OPERATION
MNEMONIC
}
OP CODE
(A) - (A) - (r)
}
SYMBOLIC
REPRESENTATION
The content of register r is subtracted from the
content of the accumulator. The result is placed
in the accumulator. '
}
DESCRIPTION
}
FLAGS AFFECTED
BY THE INSTRUCnON
°
11,0,0,
Cycles:
States:
Addressing:
Flags:
S
4
register
Z,S,P,CY,AC
Figure 11-1. Presentation Format
Table 11-1. Symbols and Notations
Symbol and
Notation
A
B
C
D
E
H
l
M
D,S
Meaning
Symbol and
Notation
byte 2
Register A (Accumulator)
Register B
Register C
Register D
Register E
Register H
Register l
Memory Byte (Address in Hl
register pair)
The bit pattern designating
destination or source. (D =
Destination, S = Source):
!2.2LS O!;!signation
000
001
010
} Reglste,
011
100
101
M Memory
110
A Accumulator
111
byte 3
port
r,r1,r2
PC
SP
~
()
11-3
'Meaning
The second byte of the
instruction.
The third byte of the
instruction.
8-bit address of an 1.0 device.
One of the registers A,B,C,
D,E,H,l
16-bit program counter
register (PCH and PCl are
used to refer to the high-order
and low-order 8 bits,
respectively.)
16-bit stack pointer register
(SPH and SPl are used to
refer to the high-order and
low-order 8 bits, respectively).
'Thecontents of the memory
location or registers enclosed
in, the parentheses
"Is replaced by"
Table 11-1 Symbols and Notations (Continued)
Meaning
Symbol and
Notation
II
4/V
Symbol and
Notation
logical AND
Exclusive OR
Inclusive OR
Addition
Twos complement subtraction
Multiplication
"Exchange"
The ones complement (for example, (A))
The restart number 0 through
7
The binary representation 000
through 111 for restart number
o through 7, respectively
"Not affected"
"Reset"
"Set"
Unknown
Flags affected according to
Standard Rules, except as
noted
The bit pattern designating a
register pair.
The mnemonic designating a
reg'ister pair.
+
n
N
o
1
x
RP
rp
data 16
16 bit data quantity.
C
Bit combination in branch
instruction
o
[
H
SP
PSW
11
C
Flag
Condition
13$113
13131
NZ-Not zero
Z-zero
1130
(Z=13)
(Z= 1)
(CY=0)
(Cy= 1)
(P5Q)
101
(P= 1)
1116
(8=0)
(S,;, 1)
-------------
0116
$111.
111
addr
addr H
addr l
. data
data H
datal
rH
rm
B
Meaning
B-Pair (B and C)
D-Pair (0 and E)
H-Pair (H and l)
SP (Stack Pointer
Register)
PSW (Processor
Status Word)
Consisting of
Accumulator and
Flag Register.
Note: Mnemonic PSW generates
11 for certain instructions,
therefore SP is invalid for
them.
11-4
P=o
NC-No carry
C-carry
PO-parity
odd
PE-parity
even
P-plus
M-minus
16-bit address quantity
High-order address byte
low-order address byte
8-bit data quantity
High-order data byte
low-order data byte
The high-order register of a
deSignated register pair
The low-order register of a
designated pair
Bit m of the register r (right to
left,J3 through 7)
The content of register r is moved to the
memory location whose address is in registers
Hand L.
Cycles:
States:
Addressing:
. Flags:
.
high-order data
"
r,
Byte 1
data
Byte 2
Cycles:
States:
Addressing:
Flags:
3
fie
00
01
10
(Register)
B-Pair (B and C)
D-Pair (D and E) .
H-Pair (H and l)
,SP (Stack POinter)
11
(r) - data
immediate
none
lDA
addr
2
7
immediate
none
Byte 1
low-order addr
MOVE TO MEMORY IMMEDIATE
MVI
10
lOAD ACCUMULATOR DIRECT
The contents of byte 2 of the instruction is
placed in register r.
Cycles:
States:
Addressing:
Flags:
Byte 3
I
These instructions are used to load a specific
register pair with a 16-bit operand. The operand
immediately follows the instruction in the form
of two B-bit bytes.
data
D
I
(rH) - dataH
(rL) - datal
2
7
register indirect
none
MOVE IMMEDIATE
MVI
,I
M,
DATA
, 0 11
,0
I
Byte 2
high-order addr
~
'---1..--1..--1------,----,---,-'~
Byte 1
Byte 3
(A) - (addrH addrd
This instruction will load the accumulator with
a data byte from memory, specified by the two
bytes which immediately follow the instruction.
((H) (l)) - data
Cycles:
States:
Addressing:
Flags:
The content of byte 20f the instruction is
moved to the memory location whose address
is in registers Hand L.
.
Cycles:
States:
Addressing:
Flags:
4
13
Direct
none
STORE ACCUMULATOR DIRECT
3
10
STA
immediate/register indirect
none
addr
o
0
, o1
Byte 1
,J
Byte 2
L-h~:9_h_-L~r_d_eL~_ad~~_r~__L'.~
Byte 3
lOAD REGISTER PAIR IMMEDIATE
LXI
rp,
I
I tI
0 , 0
'I
data 16
R
low-order data
0 , 0 ,0 ,11
low-order addr
Byte 1
Byte 2
(addrH addrl) - (A)
11-5
l1li
The contents of the acCumulator will be.stored
in memory, at a location specified by. th.e two
, bytes which immediately follow the instruction.
Addressing:
Flags:
.
direct
none
LOAD ACCUMULATOR INDIRECT
Cycles:
States:
Addressing:
Flags:
4
13
.direct
none·
LDAX rp
o
LOAD HAND L REGISTERS DIRECT·
\
LHLD
(A) - ((rp»
addr
The content of the memory location, whose
address is in the register pair rp, is moved to
register A. Note: only register pairs B (registers
Band C) or D (registers D and E) may be
specified.
Byte 1
Byte 2
high-order addr .
I
I
1
Cycles:
States:
Addressing:
Flags:
.
STORE H'
'
B-Pair
D-Pajr
STORE ACCUMULATOR INDIRECT
STAX
I
0
5
16
direct
none
I
rp
0 1 R, P 1 0
0
I
0 I
((rp» - (A)
The' content of register A is moved to the
memory location whose address is in the
register pair rp. Note: 'only register< pairs B
(registers Band C) or D (registers D and.E) may
be specified.
AJiiD L..DIRECT
SHLD
register indirect
none
RP
00
01
This instruction enables the Hand L Registers
(H-pair) to be loaded with two consecutive
bytes from memory. Register H is loaded by the
second memory byte; L is loaded with 1he first
memory byte, (which is specified by the two
bytes that immediately follow the instruction).
";:
7
Byte 3
I
(L) - (addrH addru
(H) - (addrH addrL +'1)
Cycles:
States:
Addressing:
Flags:
2
addr
Cycles:
States:
Addressing: .
Flags:
2
7
register indirect
none
EXCHANGE HAND L WITH D AND E
low·order addr
XCHG
11 1
high-order addr
.
I
oj
I
I'
(addrH addru - (L)
(addrH addrL + 1) - (H)
o
(H) - (D)
(L) - (E)
The content of registerL is moved to the
memory location whose address is specified in
byte 2 and byte 3. The conteht of register H is
mo¥e.d to the succeeding memory location.
Cycles:
States:
o
The contents of registers .Hand L are exchanged with the contents of registers D and E.
Cycles:
1
States:
4
Addressing: register
Flags:
none
5
16
11-6
11.1.6
Arithmetic Group
data
, I
This group of instructions performs arithmetic
operations on data in registers and memory.
Unless indicated otherwise, all instructions in
this group affect the Zero, Sign, Parity, Carry,
and Auxiliary Carry flags according to the standard rules. All Subtraction operations are performed using two's complement arithmetic.
The carry flag is set to indicate that a borrow
occurred and is cleared to indicate that no
borrow occurred.
Byte 2
(A) - (A) + data
The content of the second byte of the instruc·
tion is added to the content of the accumulator.
The result is placed in the accumulator.
Cycles:
States:
Addressing:
Flags:
The following ADD Instructions (ADD, ADI,
ADC, ACI) perform addition of a data byte or
register with the accumulator, the result of the
operation being placed in the accumulator.
2
7
immediate
Z,S,P,CY,AC
ADD REGISTER WITH CARRY
ADC
ADD REGISTER
S
ADD
(A) - (A) + (r) + (CY)
The content of register r and the content of the
carry bit are added to the content of the
accumulator. The result is placed in the
accumulator.
(A) - (A) + (r)
The content of register r is added to the content
of the accumulator. The result is placed in the
accu mu lator.
Cycles:
States:
Addressing:
Flags:
4
Cycles:
States:
Addressing:
Flags:
register
Z,S,P,CY,AC
ADD MEMORY WITH CARRY
1
ADD
M
M
Ct:0 , 0
1
I
(A) -
register
Z,S,P,CY,AC
ADC
ADD MEMORY
I
1
4
0
I
0
0
0
I
(A) -
The content of the memory location whose
address is contained in the Hand L registers is
added to the content of the accumulator. The
result is placed in the accumulator.
2
I
data
0
0
l1li
+ (CY)
2
7
register indirect
Z,S,P,CY,AC
ADD IMMEDIATE WITH CARRY
ACI
I 1
ADD IMMEDIATE
~,O
((H) (L))
Cycles:
States:
Addressing:
Flags:
7
register indirect
Z,S,P,CY,AC
ADI
+
The content of the memory location whose
address is contained in the Hand L registers
and the content of the CY flag are added to the
accumulator. The result is placed in the
accumulator.
(A) + ((H) (L))
Cycles:
States:
Addressing:
Flags:
(A)
0
data
I
II
Byte 1
0
0
1
data
(A) - (A) + data + (CY)
11·7
0
I
Byte 1
Byte 2
The content of the second byte of the instruction and the content of the CYflag are added to
the contents of the accumulator_ The result is
placed in the accumulator.
(A) - (A) - data
Cycles:
States:
Addressing:
Flags:
The content of the second byte of the instruction is subtracted from the content of the
accumulator. The result is placed in the
accumulator.
data
2
7
immediate
Z,S,P,CY,AC
Subtract Instructions (SUB, SUI, SBB, SB!) subtract a data byte or register from the contents of
the accumulator and place the result in the
accumulator. All subtraction operations are performed using two's complement arithmetic and
either set the carry flag (CY) to indicate a borrow or clear it to indicate no borrow.
Cycles:
States:
Addressing:
Flags:
Byte 2
2
7
immediate
Z,S,P,CY,AC
SUBTRACT REGISTER WITH BORROW
r
SBB
SUBTRACT REGISTER
SUB
II 1
°° °
S
(A) - (A) - (r) - (CY)
The content of register r and the content of the CY
flag are both subtracted from the accumulator. The
result .is placed in the accumulator.
(A) - (A) - (r)
The content of register r is subtracted from the
content of the accumulator. The result is placed
in the accumulator.
Cycles:
States:
Addressing:
Flags:
Cycles:
States:
Addressing:
Flags:
1
2
7
register indirect
Z,S,P,CY,AC
4
register
Z,S,P,CY,AC
SUBTRACT MEMORY WITH BORROW
SBB
M
SUBTRACT MEMORY
SUB
M
(A) - (A) - ((H) (L)) - (CY)
°
The content of the memory location whose address
is contained in the Hand L registers and the content
of the CY flags are both subtracted. from the accumulator. The result is placed in the accumulator.
(A) - (A) ~ ((H) (L))
The content of the memory iocation -.yhose
address is contained in the Hand L registers is
subtracted from the content of the accumulator. The result is placed in the
accumulator.
Cycles:
States:
Addressing:
Flags:
Cycles:
States:
Addressing:
Flags:
2
7
SUBTRACT IMMEDIATE WITH BORROW
register indirect
Z,S,P,CY,AC
SBI
data
Byte 1
°
SUBTRACT IMMEDIATE
SUI
2
7
register indirect
Z,S,P,CY,AC,
data
data
L--L..-,L_0-..L.---,_O--,-__",---,i_O---,·1
Byte 1
(A) - (A) - data - (CY)
11-8
Byte 2
The contents of the second byte of the instruction
and the contents of the CY flag are both subtracted
from the accumulator. The result is placed in the accumulator.
DECREMENT REGISTER
OCR
o
2
Cycles:
States:
Addressing:
Flags:
7
register indirect
Z,S,P,CY,AC
(r) -
INR
Cycles:
States:
Addressing:
flags:
o
+
1
5
register
Z,S,P,AC
DECREMENT MEMORY
The content of register r is incremented by one.
Note: All condition flags except CY are affected.
Cycles:
States:
Addressing:
Flags:
(r) -
The content of register r is decremented by
one. Note: All condition flags except CY are
affected.
INCREMENT REGISTER
(r) - (r)
·r
OCR
M
1
5
register
Z,S,P,AC
«H) (L» - «H) (L» - 1
INCREMENT MEMORY
INR
The content of the memory location whose address is contained In the Hand L registers is
decremented by one. Note: All conditions flags
except CY are affected.
M
«H) (L» - «H) (L»
Cycles:
States:
Addressing:
Flags:
+1
The content of the memory location whose address
is contained in the Hand L registers is incremented
by one. Note: All condition flags except CY are affected.
Cycles:
States:
Addressing:
Flags:
register indirect
Z,S;P,AC
DECREMENT REGISTER PAIR
DCX
rp
3
10
register indirect
Z,S,P,AC
(rH q) - (rH rL) - 1
INCREMENT REGISTER PAIR
INX
3
10
The content of the register pair rp is
,decremented by one, Note: No condition flags
are affected.
rp
(rH rL) - (rH rL)
Cycles:
States:
Addressing:
Flags:
+1
1
5
register
none
ADD REGISTER PAIR TO HAND L
The content of the register pair rp is
incremented by one. Note: No condition flags
are affected.
Cycles:
States:
Addressing:
Flags:
DAD
rp
1
5
register
none
. (H) (L) -,(H) (L)
11-9
+
(rh) (rl)
l1li
The contents of a speCific ,register pair (rp) will
be added to the, Hand L-Registers (H-Pair). The
result is placed in the register pair Hand L.
Note: Only the CY flag is affected. It is set if
there is a carry out of the double precision add;
otherwise it is reset
Cycles:
States:
Addressing:
FlagS:
, with the content of the accumulator. The, result
is placed in the accumulator. The CY flag is
cleared.
Cycles:
States:
Addressing:
Flags:
3
10
register
CY
1
4
register
Z,S,P,CY,AC
AND MEMORY
ANA
M
DECIMAL ADJUST ACCUMULATOR
DAA
--'-I~0..LI_01L-1
1L-1-L'_0
o
(A) - (A) A «Irl) (L))
0
The contents of the memory location whose address is contained in the Hand L registers is
logically AND'ed with the content of the
accumulator. The result is placed in the
accumulator. The CY flag is cleared.
The eight-bit number in the accumulator is adjusted to form two four-bit BCD (Binary-CodedDeCimal) digits by the following process:
1. If the value of the least significant 4-bits of
the accumulator is greater than 9 or if the
AC flag is set, 6 is added to the accumulator.
2.
Cycles:
States:
Addressing:
Flags:
If the value of the most significant 4-bits of
the accumulator is now greater than 9, or if
the CY flag is set, 6 is added to the most
significant 4-bits of the accumulator.
2
7
register indirect
Z,S,P,CY,AC
AND IMMEDIATE
ANI
Cycles:
States:
Flags:
11.1.7
Logical Group .'
data
The content of the second byte of the instruction is logically AND'ed with the contents of the
accumulator. The result Is placed in the accumulator. The CY flag is cleared.
Cycles:
States:
Addressing:
Flags:
ANA
o
2
7
immediate
Z,S,P,CY,AC
For exclusive OR Instructions (XRA, XRI), a
register, data byte or memory is exclusive OR'd with the contents of the accumulator,
with the result being placed in the accumulator.
AND REGISTER
I
Byte 2
(A) - (A) A data
For AND Instructions (ANA, ANI): A register,
data byte or memory byte may be AND'ed with
the contentsof the accumulator with the results
being placed into the accumulator.
0
data
3
10
Z,S,P,CY,AC
The logical Group of instructions performs
logical (Boolean) operations on data in registers
or memory and on condition flags. These
'instructions are: AND, OR, XOR, Compare,
Rotate, and Complement. Unless otherwise
indicated the Zero (Z), Sign (S), Parity (P), Auxiliary Carry (AC) and Carry (CY) flags will be
affected according to the standard rules.
11,
0]
---L.-....L1
.L....'
EXCLUSIVE OR REGISTER
0
S
XRA
11
(A) - (A) A (r)
The content of the register r is logically AND'ed
I
0
o
I
(A) - (A) -V- (r)
11·10
s
'I
The content of register r is exclusive - OR'd
with the content of the accumulator. The result
is placed in the accumulator. The CY and AC
flags are cleared.
The content of register r is inclusive - OR'd
with the content of the accumulator. The result
is placed in the accumulator. The CY and AC
flags are cleared.
Cycles:
States:
Addressing:
Flags: .
1
4
register
Z,S,P,CY,AC
Cycles:
States:
Addressing:
Flags:
EXCLUSIVE OR MEMORY
OR MEMORY
XRA
ORA
M
1
4
register
Z,S,P,CY,AC
M
o
o
(A) - (A) V ((H) (L))
The content of the memory location whose
address is contained in the Hand L registers is
OR'd with the content of the accumulator. The
result is placed in the accumulator. The CY and
AC flags are cleared.
.
(A) - (A) ¥ ((H) (L))
The content. of the memory location whose
address is contained in the Hand L registers is
exclusive - OR'd with the content of the accu·
mulator. The result is placed in the accumu·
lator. The CY and AC flags are cleared.
Cycles:
States:
Addressing:
Flags:
2
Cycles:
States:
Addressing:
Flags:
I
7
register indirect
Z,S,P,CY,AC
2
7
register indirect
Z,S,P,CY,AC
OR IMMEDIATE
EXCLU.SIVE OR IMMEDIATE
ORI
XRI
11
data
data
o
01
1
Byte 1
Byte 1
data
data
(A) - (A) V data
Byte 2
The content of the second byte of the instruction IS inclusive - OR'd with the'content of the
accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.
(A) - (A) ¥- data
The content Of the second byte of the instruc·
tion is exclusive - OR'd with the content of the
accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.
Cycles:
States:
Addressing:
Flags:
Cycles:
States:
Addressing:
Flags:
2
7
immediate
Z,S,P,CY,AC
2
7
immediate
Z,S,P,CY,AC
The Compare instructions (CM?, CPI) allow a
register, data 'byte or memory location to be
compared with the accumulator. Results of the
operation are reflected by the condition flags,
and the contents of the accumulator will temain
unchanged.
The OR Instructions (ORA, ORI) cause a
register, data byte or memory location to be
OR'd with the contents of the accumulator; the
result being placed in the accumulator.
OR REGISTER
COMPARE REGISTER
ORA
CMP
o
Byte 2
S
S
(A) - (r), (A) unchanged
(A) - (A) V (r)
11-11
The content of registerr is subtracted from the
accumulator. The accumulator remains unchanged. The condition flags are set as a result
of the subtraction. The Z flag is set to 1 if (A) =
(r). The CY flag is set to 1 .if (A) < (r) ..
Cycles:
States:
Addressing:
Flags:
ROTATE LEFT
RLC
1
4
register
Z,S,P,CY,AC
ACC
C
COMPARE MEMORY
CMP
The content of the accumulator is rotated left
one position. The low order bit and the CY flag
are both set to the value shifted out of the high
order bit position. Only the CY flag is affected.
M
(A) - ((H) (L», (A) unchanged
The content of the memory location whose
address is contained in the Hand L registers is
subtracted from the accumulator. The accumulator remains unchanged. The condition flags
are set as a result of the subtraction. The Z flag
is set to 1 if (A) = ((H)(L». The CY flag is set to 1
if (A) < ((H)(L».
'Cycles:
States:
Addressing:
Flags:
1-
Cycles:
States:
Flags:
4
CY
ROTATE RIGHT
RRC
2
7
register indirect
Z,S,P,CY,AC
The content of the accumulator is rotated right
one position. The high order bit and CY flag are
both set to value shifted out of the low order bit
position. Only the CY flag is affected.
COMPARE IMMEDIATE
CPI
data
datq
Byte 1
Cycles:
States:
Flags:
Byte 2
ROTATE LEFT THROUGH CARRY
1
4
CY
RAL
(A) - data, (A) unchanged
The content of the second byte of the instruction 'is subtracted from the accumulator. The
condition flags are set by the result of the subtraction. The Z flag is set to 1 if (A) = (data). The
CY flag is set to 1 if (A) < (data).
ACC
C
Cycles:
States:
Addressing:
Flags:
2
7immediate
Z,S,P,CY,AC
The content of the accumulator is rotated left
one position through the Coy flag. The low order
bit is set equal to the CY flag and the CY flag is
set to the value shifted out of the high orderbit.
Only the CY flag is affected.
Rotate Instructions (RLC, RRC, RAL, RAR) provide a method of recirculating the contents of
the accumulator one position to the right or left.
During Rotate Instructions, only the Carry flag
(CY) is affected.
'
Cycles:
States:
Flags:
11-12
1
4
CY
ROTATE RIGHT THROUGH CARRY
(CY) - 1
RAR
The CY flag is set to 1. No other flags are
affected.
Cycles:
States:
Flags:
1
4
CY
11.1.8
ACC
C
This group of instructions may alter normal
sequential program execution. Condition flags
are not affected by an instruction in this group.
The two types of branch instructions are unconditional and conditional.
The content of the accumulator is rotated right
one position through the CY flag. The high
order bit is set equal to the CY flag and the CY
flag is set to the value shifted out of the low
order bit. Only the CY flag is affected.
Cycles:
States:
Flags:
Branch Group
Unconditional transfers perform the specified
operation on register PC (the program counter).
Conditional transfers examine the status of one
of the four processor flags to determine if the
specified branch is to be executed.
1
4
CY
COMPLEMENT ACCUMULATOR
JUMP (Unconditional)
CMA
JMP
addr
o
(A) -
o
0
0
0
Byte 1
(A)
ONE's Complement of the accumulator is per·
formed (zero bits become 1, one bits become 0).
Cycles:
States:
Flags:
1
4
none
Byte 2
high-order addr
Byte 3
I
!
I
I
(PC) - addrH addrL
Complement Carry and Set Carry (CMC, STC)
are provided for direct control of the Carry flag:
These will allow the Carry flag to be set. No
other flags will be affected by the operation.
Jump (unconditional) provides for loading of
the Program Counter with the two bytes which
immediately follow the instruction. Therefore,
control is transferred to the instruction whose
address is specified in byte 3 and byte 2 of the
current instruction.
COMPLEMENT CARRY
CMC
3
10
Cycles:
States:
Addressing:
Flags:
(CY) - (CY)
immediate
none
CONDITIONAL JUMP
The CY flag is complemented. No other flags
are affected ..
Cycles:
States:
Flags:
low-order addr
JZ,JNZ,JC,JNC,JPO,JPE,JP,JM
1
4
CY
C
SET CARRY
o
addr
Byte 1
low-order addr
Byte 2
high-order addr
Byte 3
STC
o
11-13
l1li
«SP) ((SP) (SP) (PC) ...,
If the specified condition is true, control is
tranferred to the instruction whose address is
specified in byte 2 and byte 3 of the current
instruction; otherwise, control continues
sequentially. The conditions that may be
specified are as follows:
\
The high-order eight bits of the next instruction
address are moved to the memory location
whose address is one less than the content of
register SP. The low-order eight bits of the next
instruction address are moved to the memory
location whose address is two less than the
content of register SP. The content of register
SP is decremented by 2. Control is transferred
to the instruction whose address is specified in
byte 3 and byte 2 of the current instruction;
Note: C denotes the bit combination in the
Branch Instructions.
C.
Condition
NZ· Not Zero
.z - Zero
NC - No Carry
C - Carry
PO - Parity Odd
PE· Parity Even
P- Plus
M - Minus
Flag
(Z=O)
(Z= 1)
(CY:::O)
(CY=1)
(P=O)
(P= 1)
(S = 0)
(S=1)
000
001
010
011
100
101
110
111
Cycles:
States:
Addressing:
Flags:
Conditional jumps may occur for any Condition
flag except Auxili!'lry Carry (AC).
Cycles:
States:
Addressing:
Flags:
10
immediate
none
low-order addr
Byte 2
high-order addr
Byte 3
I
If(C),
((SP) - 1) ..., (PCH)
. (SP) - (SP) - 2
(PC) ..., addrH addrL
If the specified condition is true, the actions
specified in the CALL instruction (see above)
are performed; otherwise, control continues
sequentially.
C denotes the bit combination in Byte 1 of the
Instruction.
C
000
001
010
011
100
101
110
111
CALL
addr
.0
addr
Byte 1
C
Call instructions may be unconditional, in
which case the transfer of program control
occurs immediately; or conditional, which
checks for a specific condition flag before the
call is executed.
0
17
immediate/reg'ister indirect
none
CZ,CNZ,CC,CNC,CPO,CPE,CP,CM
3
Call
5
CONDITIONAL CALL
Call Instructions (CALL, CZ, CNZ, CC, CNC,
CPO, CPE, CP, CM), like the Jump Instructions,
provide for loading of the Program Counter with
the two bytes which immediately follow the
instruction. However, prior to loading the Program Counter, the current contents of the
counter (which point to the next sequential
memory location) are stored in Memory in an
area specified by the Stack Pointer (SP), i.e.
"pushed" onto the stack. Once the PC is,stored
on the stack, the PC is loaded with the two
bytes immediately following the. .instruction
and program control is transferred to the new
location:
o
1) ...,. (PCH)
2) - (PCLJ
(SP) - 2
addrH addrL
Byte 1
Flag
(Z=O)
(Z = 1)
(CY=O)
(CY=1)
(P=O)
(P= 1)
(S =0)
(S= 1)
Condition
NZ· Not zero
Z- Zero
NC- No Carry
C- Carry
PO- Parity Odd
PE- Parity Even
p. Plus
M- Minus
Note: / means depends on condition flags.
low-order addr
high-order addr
!
-,
Byte 2
Cycles:
States:
Addressing:
Flags:
Byte 3
I
11-,14
3/5
11/17
immediate/register indirect
none
Cycles:
States:
Addressing:
Flags:
Return Instructions (RET, RZ, RNZ, RC, RNC,
RPO, RPE, RP, RM), provide a method of transferring program control back to a location from
which an exit had occurred during a Call
instruction. It is accomplished by "popping"
the top two bytes from the stack into the Program Counter. Return instructions are unconditional or conditional.
The Restart instructions (RST) are nearly identical to the Call instructions except:
1. The address to which program control is
transferred is one of eight memory locations.
RETURN
2.
RET
o o
(PCl) - «SP))
(PCH) - «SP) + 1)
(SP) - (SP) + 2
RST
3
10.
register indirect
none
Control is transferred to an eight-byte Restart
block starting with the location whose address
is eight times the content of N. (See chart).
C
(PCLl - «SP))
(PCH) - «SP) + 1)
(SP) - (SP) + 2
N
000
001
010
011
100
101
110
111
If the specified condition is true, the actions
specified in the RETURN Instruction are performed; otherwise control continues sequentially.
C denotes the bit combination in Byte 1 of the
Instruction.
000
001
010
011
100
101
110
111
Flag
(Z=O)
(Z= 1)
(CY=O)
(CY = 1)
(P=O)
(P= 1)
(S= 0)
(S= 1)
1) - (PCH)
2) - (pel)
(SP) - 2
8* (N)
The high-order bits of the next instruction
address are moved to the memory location
whose address is one less than the content of
register SP. The low-order eight bits of the next
instruction address are moved to the memory
location whose address is two less than the
content of register SP. The content of register
SP is decremented by two.
RZ,RNZ,RC,RNC,RPO,RPE,RP,RM
k
n
«SP) «SP) (SP) (PC) -
CONDITIONAL RETURN
If (C),
All Restart instructions are unconditional.
Although these instructions can be supplied by software, they are normally forced
into the microprocessor by the hardware
during interrupt operations so that program control may be transferred to a
selected location.
RESTART
The content of the memory locc;ltion whose
address is specified in register SP is moved to
the low-order eight bits of register PC. The content of the memory location whose address is
one more than the content of register SP is
moved to the high-order eight bits of register
PC. The content of register SP is incremented
by 2.
Cycles:
States:
Addressing:
Flags:
1/3
5/11
register indirect
none
LOCATION
000016
000816
0010 16
001816
0020 16
002816
0030 16
003816
Program counter bit positions 3, 4, and 5 contain value of N. Other bit positions are forced to
zero.
Condition
NZ - Not Zero
Z - Zero
NC - No Carry
C - Carry
PO - Parity Odd
PE - Parity Even
P - Plus
M - Minus
151413121110 9 8 7 6 5 4 3
10,O:,O,O,O,O,O,OIO,ol,N,
Program Counter
11-15
2
°
10 ,0,01
Cycles:
States:
Addressing:
Flags:
3
11
register indirect
none
register of register pair rp is moved to ,the
memory location whose address is two less
than the content of register SP. The content of
register SP is decremented by 2.
Note: Register pair rp
specified.
LOAD PC FROM HAND L REGISTER
=SP may not be'
PCHl
o
o
RP
00 B-Pair (B and C-Registers)
01 D-Pair (0 and E-Registers)
10 H-Pair (H and l-Registers)
0
(PCH) - (H)
(PCU - (l)
Cycles:
States:
Addressing:
Flags:
The content of the H-Register is loaded into upper S-bits of the PC and the L-Register is loaded
into the lower S-bits of the PC. Program control
is transferred to the new address.
Cycles:
States:
Addressing:
Flags:
11_1_9
PUSH PROCESSOR STATUS WORD
PUSH
PSW
1
5
o
register
none
((SP) - 1) - (A)
((SP) - 2) - (flags)
(SP) - (SP) - 2
Stack, 110, and Machine Control Group
This group of instructions manipulates the
stack, handles I/O data transfer and machine
controls such as interrupt and internal control
flags.
The content of register A is moved to the
memory location whose address is one less
than register SP. The contents of the condition
flags are assembled into a byte and the byte is
moved to the memory location whose address
is two less than the content of register SP. The
content of register SP .is decremented by two.
Stack instructions manipulate the stack,
transferring data between the register pairs
(within the microprocessor) and the s,tack. Data
is transferred to the stiilck using PUSH instructions while data \ is removed from the stack by
POP instructions.
flags
MSB
The PUSH instructions (PUSH B, PUSH 0,
PUSH H, PUSH PSW) provide a method of storing the contents of various register pairs into
memory. The area in which they are saved is the
STACK, which is addressed by the Stack
Pointer Register.
IS ,Z
lSB
0
0
AC
Cycles:
States:
Addressing:
Flags:
PUSH
Push
3
11
register indirect
none
P
,
cvl'
3
11
register indirect
none
The POP instructions (POP B, POP 0, POP H)
provide a method of loading register pairs with
data contained on the stack.
rp
o
POP REGISTER PAIR
((SP) - 1) - (rH)
((SP) - 2) - (rL)
(SP) - (SP) - 2
The content of the high-order register of
register pair rp is moved to the memory location
whose address is one less than the content of
register SPO The content of the low-order
pop
rp
11,
I
R,P
I
(rl) - ((SP))
(rH) - ((SP) +1)
(SP) - ((SP) + 2)
11-16
0
0
0
The content of the memory location, whose
address is specified by the content of register
SP, is moved to the low-order register of
register pair rp. The content of the memory
location, whose address is one more than the
content of register SP, is moved to the highorder register of register pair rp. The content of
. register SP is incremented by 2.
Note: Register pair rp
- - specified.
Cycles:
States:
Addressing:
Flags:
MOVE HAND L TO SP
SPHL
= SP may not be
o
RP
00 8-Pair (8 and C-Registers)
01 O-Pair (0 and E-Registers)
10 H-Pair (H and L-Registers)
Cycles:
States:
Addressing:
Flags:
3
10
register indirect
none
Cycles:
States:
Addressing:
Flags:
1)
(SP) - (SP) + 2
3
10
register indirect
Z,S,P,CY,AC
EI
The interrupt system is enabled following the
execution of the next instruction.
Cycles:
States:
. Flags:
EXCHANGE TOP OF STACK WITH H & L
1
4
none
DISABLE INTERRUPTS
XTHL
01
11
(L) - (SP)
(H) - (SP)
1
5
register
none
ENABLE INTERRUPTS
The content of the memory location whose
address is specified by the content of register
SP is used to restore the condition flags. The
content of the memory location whose address
is one more than the content of register SP is
moved to register A. The content of register SP
is incremented by 2.
Cycles:
States:
Addressing:
Flags:
I
Interrupt Control instructions (EI, 01) are provided for the control of interrupts. An Enable
Interrupt must be executed before the microprocessor will recognize any interrupt requests
from the devices in the system. Once an interrupt is recognized by the microprocessor it will
ignore all further requests until another EI is
executed. If interrupts are enabled and the programmer wishes to ignore them a 01 (disable
interrupts) instructions may be used.
(flags) - ((sp))
+
1
The contents of registers Hand L (16-bits) are
moved to register SP.
PSW
(A) - ((SP)
0
(SP) - (H) (L)
POP PROCESSOR STATUS WORD
POP
5
18
register indirect
none
o
0
!
.
The interrupt system is disabled immediately
following the execution of the 01 instruction.
+
The content of the L-Register is exchanged with
the content of the memory location whose
address is specified by the content of register
SP. The content of the H-Register is exchanged
with the content of the memory location whose
address is one more than the content of
register SP.
Cycles:
States:
Flags:
1
4
none
110 Data Transfer Instructions (IN, OUT) provide
a method of transferring a byte of data to or
from an 1/0 port external to the microprocessor,
11-17
l1li
J
into or out of the accumulator. The port is
selected by the second byte of the instruction.
bit bidirectional data bus for transmission to
the specified port.
Cycles:
,3
States:,
10
A VIH an internal active pullup will
be switched on to the Oat? Bus.
3. A I supply 1AT A = -0.45% I' e.
DATA BUS CHARACTERISTIC DURING ODIN
:r-G
0
0-4
VIN
VCC
ac electrical characteristics
3
Min. Max. Unit
Parameter
Symbol
0.48
2.0
Ji.S
t r , tf
Clock Rise and Fall Time
0
50
ns
tq,1
"'1 Pulse Width
60
ns
t2
"'2 Pulse Width
220
ns
0
ns
70
ns
tCY
Clock Period
t01
t02
t03
2
tOA
2
too
toc
80
2
Signal Output Delay from "'1 or "'2 (SYNC, WR,
WAIT, HLDA)
2
DBIN Delay from "'2
tOF
tOI
"'1 to "'2
Delay "'2 to "'1
Delay "'1 to "'2 Leading Edges
Address Output Delay from "'2
Data Output Delay from "'2
Delay
1
25
Delay for Input Bus to Enter Input Mode
"'1 and DBIN
tOSl
Data Setup Time During
tOS2
Data Setup Time to "'2 During DBIN
tOH
tiE
1
2
ns
200
ns
220
ns
120
ns
140
ns
tDF
ns
30
ns
150
ns
1
Data Hold Time from "'2 During DBIN
INTE Output Delay from "'2
ns
tRS
READY Setup Time During "'2
120
ns
tHS
HOLD Setup Time to "'2
140
ns
120
ns
"'1
INT Setup Time During "'2 (During
tH
Hold Time from "'2 (READY, INT, HOLD)
tFO
Delay to Float During Hold (Address and Data Bus)
tAW
tow
two
tWA
tHF
2
120
ns
2
Output Data Stable Prior to WR
6
ns
2
Output Data Stable from WR
7
ns
2
Address Stable from WR
7
ns
HLDA to Float Delay
3
ns
WR to Float Delay
9
ns
-20
ns
2
Address Hold Time After DBIN During HLDA
Notes:
1. Oata input should be enabled with OBIN status. No bus conflict
'
.
"
*
T-Fi
:::m
can then occur and data hold time is assured. tDH .., 50ns or tOF,
whichever is less.
2. Typical load circuit:
<5V
tuaOA
OUTPUT
.
C,
I!iOpA
3. tCY = t03 + t,2 + tl/>2 + t02 + tfl/>2 + trl/>l ;. 480n,.
TVPICAl.l OUTPUT DISPLAY VS . .lCAPACHANCE
o
'SPEC
-1110
-50
0
+SO
.::. CAPACITANCE \pf)
(CACTUAl-CSI'EC)
+100
} CL
= 50pF
CL
= 50pF
~.
CL
CL
= 100pF : Address, Da ta
= 50pF: WR, HLDA, DBIN
4. The following are relevant when interfacing the INS8080A to
devices having VIH = 3.3V:
a) Maximum output rise time from 0.8V to 3.3V = lOOns @
CL = SPEC.
b} Output Delay when measured to 3.0V = SPEC + 60ns @
CL = SPEC.
c) If CL SPEC. add 0.6ns/pF if CL > CSPEC. subtract
0.3ns/pF (from modified delay) if CL <'CSPEC'
5. tAW = 2tCY - t03 - tr2 - 140ns.
6. tow = tCY - t03 - trl/>2 - 170ns.
7. If not HLOA, two = tWA = '03 + trl/>2 + IOns. If HLOA. two =
tWA =tWF·
8. tHF '" t03 + trl/>2 - 5Ons.
9. twF = t03 + 'rl/>2 - IOns.
10. Oata in must be stable for this period during OBIN . T3' Both
'OSl and tOS2 must be satisfied.
11. Ready Signal must be stable for this period during T2 or TW'
(Must be externally synchronized.)
'*
12. Hold signal must be stable for this period during T2 or TW when
entering hold mode, and during T3, T4, TS. and TWH when in
-10
-20
= 100pF
ns
5
2
CL
ns
0
Address Stable Prior to WR
tWF 2
tAH
in Halt Mode)
}
ns
200
tiS
Test Condition
hold mode. (External synchronization is not required.)
13. Interrupt signal must be stable during this period of the -last
clock cycle of any instruction in order to be recognized on the
following instruction. (External synchronization is not required.)
14. This timing diagram shows timing relationships only; it does not
represent any specific machine cycle.
0-5
[14]
timing waveforms
,
Note: Timing measurements are made at the following reference
voltages: CLOCK '1' = 8:0V, '0' = 1.0V; INPUTS '1' = 3.3V,
'0' = 0.8V; OUTPUTS '1' = 2.0V, '0' = 0.8V .
<1>1
. ~1r~Rfnfn
frfr---*'-~
r-----,
I:-----!j
<1>2
~
It
r=----\
~
'1
1021_
A1S·AD
[~~--- ~., t
I: :.
07.00
0'
-r
SYNC
m
-tIDC
OBIN
~,d
f
L,OF}
WI!
_ -
IH-tI~Cl-
READY ___________ _
WAIT
IRS\-
IH_II-I
HLOA
'"
INTE
~
-IJ~IWF-I
I-IIOC
xmx
~
10C-
HOLD
..:::L.J-- IAH
-ltOCr:::;:-~_ _.....j_ _
~RSr:::rtOC~
!-IHF-
IH-tl ' -
-J!srr I
II
-- tdJ211t:
':'>::JL
4J=-
I
~
L
L::.Jl.l_____
INS8080 A CPU
functiona I block diagram
tl
(3-10)°7.°0
BIDIRECTIOfliAl DATA BUS
I
DATA BUS
BUFFER/LATCH
~
(8 BIT)
INTERNAL DATA BUS
It
ACCUM~LATO~
LATCH
(S)
I
t
L
TEMP. REG.
(8 BIT)
INTEANAL DATA BUS
t {51'"
1)1
INSTRUCTION IJ~
REGISTER (8)
FLAG
FlIp·flOPS
181
~
t
~
ARITHMETIC
lOGIC
UNIT
(AlU)
'"
-
t
DECIMAL
ADJUST
POWER
SUPPLIES
MACHINE
CYCLE
ENCODING
1
TIMING
ANO
CONTROL
r~"'v
~-'Vl,
~+5V
(2)
-""""GNO
1
WRT
WR
(18)
DATA BUS
CONTROL
~
DBIN
(11)
INTERRUPT
CONTROL
~
INTE
(16)
t
tNT
(14)
WAIT
HOLD
CpNTROL
~
HOLO
ACK
t
HOLO
(13)
CONTROL
~
WAtT
(24)
t
SYNC
REAOY
(23)
~
SYNC
119}
(2~1
tOCKSt
q,1
(22)
rlOWOROER,
W
(8)
,
z
181
~
~
DECODER
ANO
1-
rHlGHORDER,
TEMP REGISTER
INSTRUCTION
181'-
*
IT
1
MULTIPLEXER
¢2
(15)
TEMP REGISTER
c
0
REGISTER
'81
H
REGISTER.
181
E
'81
REGISTER
l
REGISTER
STACK POINTER
PROGRAM COUNTER
INCREMENTER/DECREMENTER
.....
ADDRESS BUFFER
REGISTER
ARRAY
181
(16)
(16)
(16)
ADDRESS LATCH
l
RESET
(12)
181
REGISTER
REGISTER
--<0.....-
-
(8)
{l61
,a.
AI5-AO
ADORESSBUS
(40-29.21-25.1)
NOTE: Applielhl~ pin numberllare incillded
wlthinpilrenthelles_
INS8080A functional pin definition
memory location O. It should be noted that the status flags,
accumulator, stack pointer, and registers are not cleared
during the RESET sequence.
The following describes the function of all of the INS8080A
input/output pins. Some of these descriptions reference
internal timing periods.
•
,
•
".""
,
n.i"""" ,.!.'"
40 Lead Cera~ic Dual·in-Line Package (0)
Order Number I NS8080AD
, ,
... .. ,
'
"""
..
"
,,",
..
40-Lead Plastic Dual·in-Line Package (N)
Order Number I NSB080N
w
Manufactured under one or more (If the folicw'ng U.S. patents: 3083262, 3189758, 3231797, 3303356. 3317671, 3323071, 3381071, 3408542,34,21025,3426423,3440498,3518750,3519897, 3557431, 3560765,_
35M218, 3571630, 3575609, 357~059" 3593069, 3~97040< 3607469,3611859, 3631312, 3633052, 3638131, :3648071, 3651565, 3693248.
National Semiconductor Corporation
2900
S~tniConduclor
Drive. Santa Clara. California 95051, (408) 737·50001TWX (910) 339·9240
National Semiconductor GmbH
808 Fuerstenfeldbruck, Industriestrasse 10, West Germany, Tele. (06141) 13711Telex 05·27649
Nalional Semiconductor (UK) Ltd.
Larktield Industrial Estate, Greenock. Scotland, Tele. (0475) 33251/Telex 778·632
N3tlonal OilH not assume any responSibIlity for use 01 any
Cfrt~llry
descrllm.l; no weul! patent licenses are unpiled; and
0-12
Na!lI~nal
reserves tile rtght, at any time wltllout lIotlce, to c!Jange sall1 CIrcuitry.
~National
APRIL 1978
~ Semiconductor
INS8224 Clock Generator and Driver
General Description
Features
The I NS8224 is a clock generator/driver contained in a
standard, 16-pin dual-in-line package. The chip, which is
fabricated using Schottky Bipolar technology, generates
clocks and timing for National Semiconductor's INS8080
microcomputer family.
Included in the INS8224 is an oscillator circuit that is
controlled by an external crystal, which is selected by
the designer to meet a variety of system speed requirements. Also included in the chip are circuits that provide:
a status strobe for the I NS8228 or I NS8238 system
controllers, power-on reset for the INS8080A microprocessor, and synchronization of the READY input to
the I NS8080A.
•
Crystal-Controlled
Operation
•
Single Chip Clock Generator and· Driver for INS8080A
Microprocessor
•
Provides Status Strobe for I NS8228 or I NS8238
System Controllers
•
Provides
Power-On
Oscillator
Reset for
for
Stable
I NS8080A Micro-
processor
•
Synchronizes READY Input to INS8080A Microprocessor
•
Provides Oscillator Output for Synchronization of
External Circuits
•
Reduces System Component Count
INS808() Family CPU Group to MICROBUSTM* Configuration
,...
A15-AO
A15-AO
~
CSO
-",.
CHIP
SELECT
lOGIC
see
(I NS82LS05)
CS1
··
ESi
INS8080A
07-00
01-00
02
t t
.t: i.•· .·•••••.. ··/.
I,;i'•. i . ti?
MEMR
MEMW
INS822S
S
IIOR
RESET
4D~,
~ESET
IV"
I)"
*Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
S
U
IIOW
SISTS
D-13
INTERFACE
DEVICE
GROUP
M
I
C
R
0
07-00
01
System
r
PERIPHERAL
CONTROL
COMMUNICATIONS
DIGITAL 110
MEMORIES
Absolute Maximum Ratings
Operating Conditions
(NOTE 2)
Supply Voltage, vee . . . . . . . . . . . . . . . . . . . . . 7 V
voo . . . . . . . . . . . . . . . . . . . . 15V
Input Voltage . . . . . . . . . . . . . . . . . -1.0V to +5.5 V
Storage Temperature Range ........ _65°C to +150°C .
Lead Temperature (Soldering, 10 seconds) ..... 300°C
Supply Voltage
Vee
Voo
Temperature
Min,
Max.
Units
4.75
11.4
0
5.25
12,6
70
V
V
°c
,
DC Electrical Characteristics
TA = O°c to +70°C; Vee = +5.0 V ± 5%; Voo = +12 V ± 5%.
'"
Limits
Parameter
Symbol
Min.
Typ.
Input Current Loading
IF
Max.
Units
Test Conditions
-0.25
mA
VF = 0.45 V
10
I1A
VR=5.25V
V
le=-5mA
--~---
=t'0~' L">,,, Con,o'
.Vc . __ 'o,o~fo'wwd e',m, V"',,~
VIL
.
Input "Low" Voltage
------,
-1.0
0.8
----,- ,--
VIH
Input "High" Voltage
2.6
2.0
VIH-VIL
RESIN Input Hysteresis
0.25
------ ----,-------
.
0.45
VOL
V
Vee= 5.0 V
V
V
RESIN Input
All Other Inputs
V
Vee= 5.0 V
V
Output "Low" Voltage
0.45
(q,1. q,21. Ready, Reset, STSTB
IOL = 2.5 mA
V
All Other Outputs
IOL=15mA
V
V
V
IOH = -100 I1A
IOH= - lOO I1A
IOH = -1 mA
Output "High" Voltage
VOH
Ise[l]
---_..- - f-'
q,l, ¢2
READY, RESET
All Other o'utputs
Output Short Circuit Current
(All Low Voltage Outputs Only)
9.4
3.13
2.4
-10
-60
.,' mA
Icc
Power Supply Current
115
mA
100
Power Supply Current
12
mA
-'-----
Vo=OV
Vee= 5.0 V
Notes:
1. Caution -- 1>1 and rP2 output drivers do not have short circuit protection.
2. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be 'guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devtces should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device oper~;ltion.
Crystal Requirements *
Tolerance ...... ; . . . . . . . . 0.005% at O°C to +70°C
Resonance ........................ F undamental*
Load Capacitance . . . . . . . . . . . . . . . . 20 pF to 30 pF
Equivalent Resistance . . . . . . . . . . . . . . . 75 n to 20 n
Power Dissipation (min). . . . . . . . . . . . . . . . . . 4mW
*1 t is good design practice to ground th~ case of the crystal
*With tank circuit Lse 3rd overtone mode,
0-14
AC Electrical Characteristics
TA = o°c to +70°C; Vcc = +5.0 V ± 5%; Voo = +12 V ± 5%.
Symbol
Limits
Parameter
Min.
Typ.
Units
Max.
ttJ>1
<1>1 Pulse Width
2tCY
- - - 20n5
ttJ>2
<1>2 Pulse Width
5tCY
- - - 35ns
t01
<1>1 to <1>2 Delay
0
t02
<1>2 to <1>1 Delay
2tCY
---14ns
t03
<1>1 to <1>2 Delay
--
tR
<1>1 and <1>2 Rise Time
20
tF
<1>1 and <1>2 Fall Time
20
tOtJ>2
<1>2 to <1>2 (TTL) Delay
-5
+15
<1>2 to STSTB Delay
6tCY
- - - 30ns
6tCY
toss
tpw
STSTB Pulse Width
Test Conditions
9
9
ns
CL = 20 pF to 50 pF
9
2tCY
2tCY
- - + 20n5
9
9
<1>2 TTL, C L = 30 pF
,
Ins
-9
9
tCY
- - - 15ns
STSTB, C L = 15 pF
R1 = 2 kD
R2 = 4 kD
9
- - - 1----tORS
RDYIN Setup Time to Status Strobe
tORH
RDYIN Hold Time After STSTB
tOR,
READY or RESET to <1>2 Delay
tClK
ClK Period
R1 = 300D
R2 = 600D
4tCY
50n5- - , -
9
4tCY
I
-9
Ready 8, Reset
CL = 10pF
R1 = 2 kD
R2 = 4kD
4tCY
- - - 25ns
9
tCY
-
-
fMAX
Maximum Oscillating Frequency
CIN
I nput Capacitance
9
MHz
27
8
Test Circuit
Vee
.,
.,
INPUT
!"
GND
0-15
~
GND
pF
Vcc = +5.0V
Voo=+12V
V BIAS = 2.5 V
f = 1 MHz
Waveforms
~-----------------~------tCY ----~------------~--~
tR --'
i--'
'4>1
¢1-----'I
I.
--.I ,-- tF
"
!
t~2
"'2
--
----,-+lI't
tD2 ----~
I::.tD2
¢2!TTL) _ _ _ _ _ _ _ _ _ _ _ _...,Ii"/,
I
f-----,-
tOR - -
._----- ---- - --- ----'-- ---""'.j,..------+------------
READY OUT _ _ _ _ _ _ _ _ _ _ _ _ _~-IJ1'
________ ,_
I--::-- tOR
---------------~--------.
-----00
RESET OUT
VOLTAGE MEASUREMENT POINTS: 1/>'1,1/>2 Logic "0" = 1.0 V, logic "1" = 8.0 V. All other signals measured at 1.5 V.
AC Electrical Characteristics
TA
(For tey =488.28 ns)
=O°C to +70o 'C"; Vee =+5.0 V ±5%; Voo =+12 V ± 5%.
Symbol
"
,
.,'>
,
~
Parameter
Limits
Typ.
Min.
-
"
Max.
Units
tl/>l
' rPl PulseWidth
89
ns
tl/>2
rP2 Pulse Width
236 '
ns
tOl
Delay ifil to rP2
0
ns
t02
Delay '¢2 to rPl
95
t03
Delay rf>1 to rf>2 Leading Edges
109
tr
tf
toss
rf>2 to STSTB Delay
ns
129
ns
Output Rise Time
20
ns
Output Fall Time
20
ns
326
ns
Test Conditions
tey
=488.28 ns
,
rPl & rf>2 Loaded to
CL = 20 to 50 pF
,
tOtJ>2
rf>2 to rf>2(TTL) Delay
tpw
Status Strobe Pulse Width
tORS
RDYIN Setup Time to STSTB
tORH
tOR
fMAX
Oscillator Frequency
296
-5
+15
ns
40
ns
~167
ns
RDYIN Hold Time after STSTB
217
ns
READY or RESET to ~2 Delay
',192
ns
18.432
-D·16
MHz
Ready & Reset Loaded
to 2 mA/l0 pF
All measurements
referenced to 1.5 V
unless specified
otherwise.
INS8224 Functional Pin Definitions
The following describes the function of all of the
INS8224 input/output pins. Some of these descriptions
reference internal circuits.
For manual system reset, a momentary contact switch
that provides a low (ground) when closed is also connected to the RESIN input.
INPUT SIGNALS
Ready In (RDYIN): An asynchronous READY signal
that is re-clocked by a D-type flip-flop of the I NS8224 to
provide the synchronous READY output discussed below.
Crystal Connections (XTAL 1 and XTAL 2): Two inputs
that connect an external crystal to the oscillator circuit
of the INS8224. Normally, a fundamental mode crystal
is used to determine the basic operating frequency of
the oscillator. However, overtone mode crystals may
also be used. The crystal frequency is nine times the
desired microprocessor speed (that is, crystal frequency
equals l/tCY x 9). When the crystal frequency is above
10 MHz, a selected capacitor (3 to 10 picofarads) may
have to be connected in series with the crystal to produce
the exact desired frequency. Figure A.
+5 Volts: V cc supply.
+12 Volts: VDD supply.
Ground: 0 volt reference.
OUTPUT SIGNALS
Oscillator (OSC): A buffered oscillator signal that can
be used for external timing purposes.
4>1 and rh. Clocks: Two non-TTL compatible clock phases
that provide nonoverlapping timing references for
internal storage elements and logic circuits of the
INS8080A microprocessor. The two clock phases are
produced by an internal clock generator that consists
of a divide-by-nine counter and the associated decode
gati~g logic. Figure B.
Tank: Allows the use of overtone mode crystals with
the oscillator circuit. When an overtone mode crystal is
used, the tank input connects to a parallel LC network
that is ac coupled to ground. The formula for determining the resonant frequency of this LC network is as
follows:
1
rh. (TTL) Clock: A TTL 4>2 clock phase that can be used
tor external timing purposes.
F=
2rrv'lG.
Status Strobe (STSTB): Activated (low) at the start of
each new machine cycle. The STSTB signal is generated
by gating a high-level SYNC input with the 4>1A timing
signal from the internal clock generator of the INS8224.
The STSTB signal is used to clock status information
into the status latch of the INS8228 system controller
and bus driver.
Synchronizing (SYNC) Signal: When high, indicates the
beginning of a new machine cycle. The I NS8080A
microprocessor outputs a status word (which describes
the current machine cycle) onto its data bus during the
first state (SYNC interval) of each machine cycle.
Reset In (RESIN): Provides an automatic system reset
and start-up upon application of power as follows. The
RESIN input, which is obtained from the junction of
an external RC network that is connected between V cc
and ground, is routed to an internal Schmitt Trigger
circuit. This circuit converts the slow transition of the
power supply rise into a sharp, clean edge when its input
reaches a predetermined value. When this occurs, an
internal D-type flip-flop is synchronously reset, thereby
providing the RESET output signal discussed below.
Reset: When the RESET signal is activated, the content
of the program counter of the INS8080A is cleared.
After RESET, the program will start at location 0 in
memory.
Ready: The READY signal indicates to the INS8080A
that valid memory or input data is available. This signal
is used to synchronize the I NS8080A with slower
memory or input/output devices.
Logic Diagram and' Pin Configuration
rn::>
XTAll
DD
XTAl2
G>
TANK
OSC
RESET
.,
.1
CLOCK
GEN.
+,
., (TTl)
.'0
CI>
IT>
DI>
STSTB
ROYIN
XTAL I
CI>
READY
TANK
INSB214
IT>
RESET
IT>
READY
G>
0·17
OSC
,,2 (TTl)
11
4>1
mrs
10
4>1
GND
n
VCC
XTAL1
DD
RESIN
RDYIN
16
RESiN
SYNC
SYNC
SCHMITT
INPUT
CD
DD
voo
1m
F
=__1_
2. VIC
1 UNIT
= _ _1__
OSC. FRED.
USED ONLY
FOR OVERTONE
CRYSTALS
3-10pF
(ONLY NEEDED
ABOVE 10MHz)
13
11
22
10
15
4
23
4
- - SP
(,.)
m
INS8080 Family CPU Group to MICROBUS Configuration
INS8Z5S:
il1I'i
*Trademark, National Semi.conductor Corp.
© 1978 National Semiconductor Corp.
z
en
0-19
en
C
::!.
<
...CD
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . O°C to +70°C
Storage Temperature . . . . . . . . . . . . _65°-C to +150°C
Supply Voltage. Vee . . . . . . . . . . . . . -0.5 V to +7 V
Input Voltage . . . . . . . . . . . . " .... -1.5 Vto +7 V
Output Current . . . . . . . . . . . . . . . . . . . . . . 100 mA
DC Electrical Characteristics
TA = o°c to +70°C; Vee = 5 V ± 5%.
Symbol
Ve
Parameter
Min.
Input Clamp Voltage. All Inputs
Limits
Typ)1]
0.75
Max.
-1.0
Units
Test Conditions
V
Vee = 4.75V; Ie =
~5
mA
I nput Load Current
STSfB
IF
IR
02& Os
00.01.04.05. & 07
. All Other Inputs
500
750
250
250
/lA
/lA
/lA
/lA
Vee,: 5.25 V
VF = 0.45 V
I nput Leakage Current
STSTB
OBo- DB7
All Oth~r Inputs
100
'20
100
/lA
/lA
/lA
Vee =5.25 V
VR = 5.25 V
2.0
V
Vee= 5 V
190
mA
Vee = 5.25 V
0.45
0.45
V
V
Vee = 4,75 V; 10L = 2 mA
10L = 10 rnA
V
V
Vee = 4.75 V; 10H = -10 /lA
IOH=-1mA
90
mA
Vee=5V
100
-100
/lA
/lA
Vee= 5.25 V; Vo = 5.25 V
Vo = 0.45 V
mA
(See Test Conditions-Pg. 3)
VTH
Input Threshold Voltage. All Inputs
lee
Power Supply Current
0.8
VOL
Output Low Voltage
OO-D7
All pther Outputs
VOH
Output High Voltage
00- 0 7
All Other Outputs
3.6
2.4
los
Short Circuit Current. AII.Outputs
15
10 (off)
Off State Output Current
All Control Outputs
liNT
INTA Current
140
3.8
5
Not.. :
1. Typical values are for T A
=
25°C and nominal supply voltages.
Capacitance
Th-is parameter is periodically sampled and not 100% tested.
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
COUT
Control Signals
.
I/O
I/O Capacitance
(0 or DB)
Limits
Min. Typ.!1] Max.
Units
8
12
pF
7
15
pF
8
15
pF
!
VSIAS "2.5 V.Vee = 5.0 V. TA = 25°C, f = 1 MHz.
0-20
AC Electrical Characteristics
T A = 0° C to +700 C;
v cc = 5 V ± 5%.
Symbol
Limits
Parameter
Min.
Max.
Units
Condition
tpw
Width of Status Strobe
22
tss
Setup Time, Status Inputs Do - D7
8
ns
tSH
Hold Time, Status Inputs Do-D7
5
ns
toc
Delay from STSTB to any Control Signal
20
60
ns
CL = 100 pF
tRR
Delay from DBIN to Control Outputs
30
ns
CL = 100 pF
tRE
Delay from DBIN to Enable/Disable 8080 Bus
45
ns
CL = 25 pF
tRO
Delay from System Bus to 80!!O Bus during Read
30
ns
CL = 25 pF
tWR
Delay from WR to Control Outputs
45
ns
C L = 100 pF
tWE
Delay to Enable System Bus DBo - DB7 after STSTB
30
ns
CL=100pF
two
Delay from 8080 Bus DO - D7 to System Bus DBo - DB7 during Write
40
ns
C L =100pF
tE
Delay from System Bus Enable to System Bus DBo- DB7
30
ns
C L =100pF
tHO
H LDA to Read Status Outputs
25
ns
Cl.. = 100 pF
tos
Setup Time, System Bus Inputs to HLDA
10
ns
tOH
Hold Time, System Bus Inputs to HLDA
20
ns
5
5
ns
Test Conditions
Test Load l2J
Vee
Rl
OUTPUT
PIN
2. For DO - 07: R1
~
4 kn, R2
=~,
l:
R2
~NO
CL = 25 pF.For ali other outputs: R1 = 500 n, R2 = 1 kn, CL = 100 pF.
INTA Test Circuit (for RST 7)
~
+12 V
lku±10%
1.
OP822818238
liNT
23
INTA
D·21
Waveforms
4>1
4>2
STATUS STROBE
----=\"'lr'---------..:-....
8080DATABUS~~~~~~~~~==~~~~~~~~~~~~
HLDA:::::~~=f~==:J~==5JH=~~===============
DBIN
1ImI,i1l1!,l\lmI!
IN1AU~~:G ~t~:
SYSTEM BUS DURING READ : : : : : : : :
INS8080A BUS DURING READ - - - - - - - -
INS8080A BUS DURING WRITE : : : : : : : : :
SYSTEM BUS DURING WRITE - - - - - - - - -
:1~~~~~__
~§~*-~tw~D~~~~~~~~~
...
CD
Physical Dimensions·
en
:s
to
"0
C
...CD
«I
-e
0.025
RAO ~"
-o
-~
c
o
GLASS
E
,0,055
1I.20G
,
~-'I
CD
.~
I
--1
10.060
10.100
I
I
I__ U.l01l_1 1 _
'11.010
~l :f~~
-~O.1Z&O.010
0.018
l'O.OOl
MIN
Ceramic Dual-in-line Package (J)
Order Number INS8228J/INS8238J
~
~
en
z
ii
~
~
""
I
(1.600) ~
z
RAO
0.540 iO.OOS
'''''rffim-ffiT.iffi'Ff:fFm-ffi''ffiffiFfffi9im=,!!
-
B
0.[175
0.600-0.620
1"
11.040
.11l·90S}
I-~rn.i40:;5.148i----ti
f
,
II
0.625 :::~:
'-
10
11
Ill."'!'.""
12
I---
0.160 ~U05
(4.064 !O.121)
jr-r----=-t+-------,~J:"I::::I
.
___ I f
(::::=::~~~I
f--~(1!i.815~:;:~)--1 G.G75~
(1.905
~0.J81)
~ ~I::::I --Ij--'(:::~~:::::!I
I_
I-
TVI'
t-
MI.
(::!~:l
MIN
24-Le.d Molded DIP (N)
Order Number INS8228N/INS8238N
National Semiconductor
Corporalion
2900 Semiconductor Drive
Santa Clara. California 95051
rel: (408) 737-5000
TWX: (910) 339·9240
National Semiconductor GmbH
NS Int,rnationallm:" Japan
8000 MOncnen 21
61f2 Elsenheimerstrasse
West Germany
Tel: 0891915027
Te!ex' 05·22772
Miyake Building
1-9 Yotsuya. Shmjuku-ku 160
Tokyo, Japan
Tel: (03) 355-3711
TWX: 232·2015 NSq-J
NS Eleclronics (Hong Kong) Lid.
8th Floor.
Cheung Kong Electronic Bldg.
4 Hing Vip Street
Kwun Tong
Kowloon, Hong Kong
Tel: 3-411241-8
Telex: 73866 NSEHK HX
Cable: NATSEMI
NS El,ctronics 00 BrasH
HS (Iectronics Ply. Lt•.
Avda Bngade!ro fafla Lima 844
11 AMar Conjunto 1104
Jardlm Paulistano
Sao Paul(l, Brasil
Telex' 1121008 CABINE SAO PAULO
Cor. Stud Rd. & Min, Highway
Bayswat~r.
Victoria 3153
Australia
Tel: 03·729-6333
Tetell": 32096
National (Ioes not assume any responsibility for use of any circuitry desett,bed; no circuit patent licenses are implied; and National reserveS'the right, at any ,time without, notice, to change said Circuitry
0-24
.
~ Semiconductor
~National
JULY 1978
INS8202J8203 TRI·STATE® Octal Buffers
General Description
Features
These devices provide eight two-input buffers in each
package. All employ the newest low power Schottky
TTL technology. One of the two inputs to each buffer
is used as a control line to gate the output into the
high-impedance state, while the other input passes
the data through the buffer. The INS8202 presents
true data at the outputs, while the INS8203 is
inverting. All eight TRI·STATE enable lines are
common, with access through a 2-input NOR gate.
The outputs are placed in the TRI·STATE condition by
applying a high logic level to the enable pins. These
devices represent octal, low power Schottky versions
of the very popular DM8095 and 96 TRI-STATE hex
buffers.
• Identical to DM81 LS95 and DM81LS96
• Octal versions of popular DM80LS95, 80LS96
• Typical power dissipation
INS8202 - 80mW
INS8203 - 65mW
• Typical propagation delay
INS8202 - 13ns
INS8203 - 10ns
• Low power Schottky TRI-STATE technology
• MICROBUSTM- compatible
INS820218203 MICROBUS Configuration
INS8202/820J
INS8202/820J
EIGHT
HIGH
CURRENT
DRIVE
USER
OUTPUTS
Y8-Y1
+:=T
USER
INPUTS
M
I
C
R
M
I
C
R
0
0
8
U
S
B
U
S
CS
WR
G1
G2
iITi
CS
MICROBUS
RECEIVER
MICROBUS
DRIVER
-Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
D·25
,.••
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
INS820218203
Parameter
Conditions
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VI
Input Clamp Voltage
10H
High Level Output Current
VOH
High Level Output Voltage
Min
Typ
Max
2
V
Vee;" min, II = -18mA
10L
Low Level Output Current
VOL
Low Level Output Voltage
Vee = min, VIH = 2V, IIOH = max
VIL = 0.8V
IIOH = -5mA
Vce = min, VIH = 2V, VIL
=
max, VIH
10(OFF) Off-State (High·lmpedance State) Vee
Output Current
VIL = 0.8V
= 2V I Vo
II
Input Current at Maximum Input
Voltage
Vc.c = max, VI = 7V
IIH
High Level Input Current
Vee = max, VI
IlL
Low Level Input Current
A Input
Vee = max
= 0.8V, 10L
= max
mA
V
20
VI
Vee
16
0.5
-20
G Input
Vcc = max (Note 2)
mA
= 0.4V
VI
Short Circuit Output Current
-2.6
I Vo = 2.4V
Both G Inputs at 0.4V
Supply Current
V
V
= max
VI
los
V
-1.5
2;4
= 2.7V
Ice
0.8
2.7
Soth G Inputs at 2V
Units
= 0.5V
= 0.4V
= 0.4V
0.1
mA
20
,..A
-.20
,..A
-0.36
-0.36
-30
,..A
-60 -130
INS8202
16
26
INS8203
13
21
mA
mA
mA
=
Note 1: All typical values are at VCC
5V, TA = 25 "C.
Note 2: Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
Connection Diagrams
V[ y i
2B
19
8
18
YB
11
r
Yl
AI'
16
15
,.
V6
13
i'
Vee
Y,
]"2B
11
12
'G~
A8
1,9
V8
118 .
AI
17
VI
116
.6
15
114
V6
A5
13
V5
112
11
~,~I~I~~ ~,~~~~
,
~1
~NJ.~~
2
"
Jll
4
.2
)25
6
•3
J31
8
A.
.1. 9 •
V•
.,
J.'B
GNB
1
FA~~~
2
Al
v,b
A2
•
15
V2
6
A3
INS8203
INS8202
0-26
b
V3
••
8
19
V.
I,·
GNO
Switching Characteristics
Vee
= 5V, TA = 25°C
INS8202
Conditions
Parameter
Min
INS8203
Typ
Max
11
16
15
Min
Typ
Max
Units
6
10
ns
22
13
17
ns
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tZH
Output Enable Time to High Level
16
25
17
27
ns
tZL
Output Enable Time to Low Level
13
20
16
25
n's
tHZ
Output Disable Time from High Level
13
20
13
20
ns
tLZ
Output Disable Time from Low Level
19
27
18
27
ns
CL
RL
= 15pF
= 2kn
CL
= 5pF, RL = 2kfl
G1
G2
A
H
X
L
L
X
H
L
L
X
X
Z
Z
H
L
H
Truth Tables
Inputs
G2
A
. Output
Y
H
X
X
H
L
X
X
Z
Z
H
H
L
L
L
G1
L
L
Inputs
L
ou~ut
20~Lead Dual-In-Line Package
Order Number INS8203(N)
20-Lead Duai-ln'Line Package
Order Number INS8202(N)
1'.:.1
D-27
!
CD
Physical Dimensions
inches (millimeters)
::s
In
a:s
( ,)
i.070
(27.178)
MAX
0.092
(2.337)
DIA NOM
0
"F~':::':::':::':::'.e::~~~!::±':::!:~-f
[U
~
Ii)
..:..
a:
0.250 ±0.005
(6.350 ±0.127)
I;;;?,r:;=:;:;=;=:;:r=;=:;::r=r:=r~r.;:;:=;=~~~
0.300-0.320
(7.620-8.128)
t-
co
en
0.030
0.065
r\:"=~i==:=!
I
(1.651)
-(0.229-0.254)
I
TYP
0.075 '.0.005
(1.905 '0.1211
I
--I
0 040 '
--
I'
I
.
=
0.130 '0.005
(3.302 'Olli)
-,
~
"t_J
j--
z
1- (2.286)
TYP
_,_
0.009-0.01-0
(8.763)
MAX
2. 3
0 090
~(1
016)
~-
M~X
~ _0.345 _
I,
NOM
(0.762)
C")
~~
J
J
---r-r-
~
I
0.100'0.010
I
1_(2.540'0.254)--1
I
r-- 0.018 !0.003
(0.457'0.076)
I ~O
~1-·--~5 (0.508)
I.......
(3.:175)
MiN
MiN
20·lead Dual·in·Line Package
Order Number INS8203{N)
NS Package Number N20A
N.tlon.1 Semiconductor
CorpDrltlon
2900 Semiconductor Drive
Santa Clara, California 95051
Tel.: (408) 737-5000
TWX: (910) 339·9240
Nalional Semiconductor GmbH
8000 Miincllefl 21
Elsenheimerstrasse 6'1/2
West Germany
Tel.: 089/9 15027
Telex: 05-22772
NS International Inc" Japan
Miyake Building
1·9 Yotsuya, Shlnjuku-ku 160
Tokyo, Japan
Tel.: (03) 355·3711
TWX: 232·2015 NSCJ·J
National Semiconductor
(Hong Kooglltd.
8th Floor,
Cheung Kong Electronic Bldg.
4 Hing Yip Street
Kwun Tong
Kowloon, Hong Kong
Tel.: 3'411241-8
Telex: 73866 NSEHK HX
Cable: NATSEMI
NS Electronics Do Brasil
NS Electronics Pty. ltd,
Avda Brigadeiro Faria Uma 844 CnL Stud Rd. & Min. Highway
11 Andar Conjunlo 1104
Bayswater, Victoria 3153
Jardim PauJistano
Australia
Sao Paulo, Brasil
Te!.: 03-729-6333
Telex
Telex: 32096
1121008 CABINE SAO PAULO
National does not assume any responsIbility lor usa of any Circuitry described; no circuit patent licenses are imphed, and National reserves the righI, al ally time without notice, 10 change said circuitry.
0\-28
~National
a
APRIL 1978
-enz
(X)
Semiconductor
N
o
(X)
INS8208 8-Bit Bidirectional Transceiver
cp
General Description
Features
to
;::;:
The INS8208 is an 8-bit TRI-STATE® low power
Schottky transceiver. It provides bidirectional drive for
bus-oriented microprocessor and digital communications
systems. Straight through bidirectional transceivers are
featured, with low power Schottky drive capability on
the A ports and 48mA bus drive capability on the B ports.
PNP inputs are incorporated to reduce input loading.
• B-Bit Bidirectional Data Flow Reduces System
Package Count
• Bidirectional TR I-STATE® Inputs/Outputs Interface
with Bus-Oriented Systems
• PNP inputs Reduce Input Loading
• 3.6V Output High Voltage Interfaces with TTL,
MOS, and CMOS
One input, Transmit/Receive, determines the direction
of logic signals through the bidirectional transceiver:
Transmit enables data from A ports to B ports; Receive
enables data from B ports to A ports. The Chip Disable
input disables both A and B ports by placing them in a
TRI-STATE® condition.
• 48mA/300pF Bus Drive Capability
• Pinouts Simplify System Interconnections
• Transmit/Receive and Chip Disable Simplify Control
Logic
• Compact 20-Pin Dual-In-Line Package
The output high voltage (VOH) is specified at 3.6 V
minimum to allow interfacing microprocessors, .TTL,
MOS, CMOS, RAM, or ROM.
•
Low ICC Power (BmA per bidirectional bit)
• MICROBUS TM • Compatible
INS8208 MICROBUS™ Configuration
rADDRESS
BUS
CPU
GROUP
DATA
BUS
CONTROL
BUS
M
I
C
R
07·00
Bl·BO
CS.
CD
0
B
U
s
INS8208I.....
A7·AD , ....
...Jo.
-y
PERIPHERAL
MEMR-[>o- Tii!
I.JI~
* Trademark, National Semiconductor Corporation
© 1978 National Semiconductor Corp.
D-29
"
~Iute
Maximum Ratings
(Note 1)
7V
5.5V
5.5V
-65°C to +150°C
300°C
' 600!11W
Supply Voltage
Input Voltage
Output Voltage
Storate Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dis~ipation
",
Recommended Operating Conditions
-
Supply Voltage (VCC)
Temperature (TA)
Min
Max
Units
4.75
0
5.25
70
V
°c
DC Electrical Characteristics
(Notes :l and 3)
Parameter
Symbol
Limits
Conditions
Description
Typ
Min
Max
Units
A Port (AO-A7)
VIH
Logical "1" Input Voltage
CD = O.BV, T/R = 2.0V
VIL
Logical "0" Input Voltage
CD = O.B'V, T/R = 2.0 V
VOH
Logical "1" Output Voltage CD = O.B V, T/R = O.B V 10H = -0.4 mA
VOL
Logi.cal "0" Output Voltage CD = 0.8 V, T/R = O.B V,IOL
lOS
Output Short Circuit
Current
CD = O.BV, T/R = O.BV, Vo = OV,
VCC = 5.25 V, Note 4
IIH
Logical "1" Input Current
CD = O.BV, T/R = 2.0V,VIH = 2.7\;
II
I nput Current at Maximum
Input Voltage
CD = 2.0 V, VCC = 5.25 V, VIH = 5.25 V
IlL
Logical "0" Input Current
VCLAMP Input Clamp Voltage
Output/Input
TRI·STATE®Current
10D
V
2.0
0.8
VCC-l.15
=' 5mA
-10
V
VCC-O.B
0.3
0.45.
V
-22
-75
mA
1
BO
p.A
1
mA
p.A
CD = O.BV, T/R = 2.0V, VIL = 0.4 V
-70
-250
CD = 2.0 V, liN = -12mA
-0.2
-1.5
-200
BO
VIN=O.4V
VIN=4:0V
CD = 2.0V
V
V
p.A
p.A
B Port (BO - B7)
.
Logical "1" Input Voltage
CD = O.BV, T/R = O.BV
VIL
Logical,"O:' Input Voltage
CD = 0.8 V, T /R = O.B V
VOH
10H = -0.4 rnA
Logical "1'.' Output Voltage CD = O.BV, T/R = 2.0V 10H = -5mA
10H - -lOrnA
VOL
Logical
lOS
Output Short Circuit
Current
CD = 0.8V, T/R = 2.0V, Vo = OV,
VCC = 5.25 V, Note 4
IIH.
Logical "1" Input Current
CD = 0.8V, T/R = 0.8V, VIH = 2.7 V
II
Input Current at Maximum
Input Voltage
CD = 2.0 V, VCC = 5.25 V, VIH = 5.25 V
IlL
Logical "0" I nput Current
CD = 0.8V, T/R = 0,8V, VIL = 0.4V
CD = 2.0V, liN = -12mA
VIH
,
"O~'
Output Voltage CD = O.B V,
VCLAMP Input Clamp Voltage
100
Output/Input
TRI·STATE®Current
T/R = 2.0V
2.0
0·30
.vCC-1.15
2.7
2.4
-
V
V
V
V
Vce- O.B
3.6
3.3
0.3
0.4
10L '" 20mA
101:. = 48mA
VIN = 0.4 V
VIN = 4.0V
CD = 2.0V
V
O.B
0.4
0.5
V
V
-35
-150
mA
1
80
p.A
1
mA
-12
-250
p.A
-0.3
-1.5
-200
+200
V
p.A
p.A
DC Electrical Characteristics
continued
Parameter
Symbol
(Notes 2 and 3)
Limits
Conditions
Description
Min
Max
Typ
Units
Control I nputs CD, T /R
VIH
Logical "1" I n put Voltage
VfL
Logical "0" Input Voltage
2.0
IIH
Logical "l"lnput Current
VIH ='2,7 V
II
I nput Current at
Maximum Input Voltage
VCC = 5.25V, VIH = 5.25V
IlL
Logical "0" Input Current
VIL = 0.4 V
VCLAMP Input Clamp Voltage
V
0.8
V
20
IJ.A
1.0
mA
0.4
0.8
mA
mA
-1.5
V
0.5
ITIR
ICD
IIN=-12mA
0.23
0.45
-0.8
Power Supply Current
ICC
Power Supply Current
CD = 2.0 V, VCC = 5.25 V, VIN = 0.4 V
AC 8ectrical Characteristics
100
65
mA
Vcc = 5V, TA = 25°C
Conditions
Parameter
Min
Typ Max
Units
A Port Data/Mode Specifications
Propagation Delay to a Logical "0" from
tPDHLA B Port to A Port
CD = 0.4 V, T/R = 0.4 V (figure A)
Rl = 1k, R2 = 5k,C1 = 30pF
24
40
ns
Propagation Delay to a Logical "1" from
tPDLHA B Port to A Port
CD = 0.4 V, T /R = 0.4 V (figure A)
R 1 = 1k, R 2 = 5k, C 1 = 30 pF
11
20
ns
tPLZA
Propagation Delay from a Logical "0" to
TRI·STATE® from CD to A Port
BO to B7 = 0.4 V, T/R = 0.4 V (figure C)
S3 = 1, R5= 1k, C4 = 15pF
12
18
ns
tPHZA
Propagation Delay from a Logical "'" to
TRI·STATE® from CD to A Port
BO to B7 = 2.4 V, T/R= 0.4 V (figure C)
S3 = 0, R5 = 1k, C4 = 15pF '
8
15
ns.
tPZLA
Propagation Delay frorn TRI·STATE® to
a Logical "0" from CD to A POrt
BO to B7 = 0.4 V, T/R = 0.4 V (figure C)
S3= 1, R5= 1k,C4=30pF
32
50
ns
tPZHA
Propagation Delay from TRI·STATE® to
a Logical "'" from CD to A Port
BO to 87 = 2.4 V, T/R = 0.4 V (figure C)
S3 = 0, R5 = 5k, C4 = 30 pF
16
25
ns
Propagation Delay to a Logical ':0" from
tPDHLB A Port to B Port
CD = 0.4 V, T /R = 2.4 V (figure A)
R1 = lOOn, R2 = 1k, C1 = 300pF
17
27
ns
Propagation Delay to a Logical ,"1" from
tPDLHB A Port to B Port
CD = 0.4 V, T/R = 2.4 V (figure A)
Rl = lOOn, R2 = lk, C,,= 300p~.
15
23
ns
B Port Data/Mode Specifications
tPLZB
Propagation Delay f~om a L:;ogical "0" to
TRI·STATE® from CD to B Port
AO to A7 = 0.4 V, T/R = 2.4 V (figure C)
S3=l,R5=lk,C4=15pF'
25
40
ns
tPHZB
Propagation Delay from a Logical "1" to
TRI·STATE®from CD to B Port
AO to A7 = 2.4 V, T/R = 2.4 V (figure C)
S3 = 0, R 5 = 1k, C4 = 15 pF
16
25
ns
tPZLB
Propagation Delay from TRI·STATE® to
a Logical "0" from CD to B Port
AO to A7 = 0.4 V, T/R = 2.4 V (figure C)
S3 = 1, R5 = lOOn, C4 = 300pF
33
50
ns
tPZHB
Propagation Delay from TRI·STATE®to
a Logical "1" from CD to B Port
AO to A7 = 2.4 V, TIR = 2.4 V (figure C).
S3 = 0, R5 = lk, C4 = 300pF
16
25
ns
0-31
.....
AC 8ectrical Characteristics
continued
VCC = 5V, TA = 25QC
I
Param.eter
I I I I
Conditions
Min Typ Max
Units
TransmitiReceive Mode Specifications
tPHZR
Propagation Delay from a'Logical "1" to
TRI-STATE®from T/R to A Port
CD '= 0.4 V (figure B)
Sl = 1, R4= 100n;C3= 300pF
S2 = 0, R3 = 1k, C2 = 15 pF
14 '22
tPLZR
Prnpagation Delay from a Logi'cal "0" to
TRI·STATE® from T/R to A Port
CD = 0.4 V (figure B)
Sl = 0, R4 = lk, C3 = 300pF
S2= 1, R3= lk,C2= 15pF
20
Propagation Delay from a Logical "1" to
rRI-STATE® fromT/R to B Port
CD = 0.4 V (figure B)
Sl = 0, R4 =lk, C3 = 15pF
S2 = 1, R3 = 5k, C2 = 30pF
22
33
"s
tPLZT
,Propagation Delay from a Logical "O".to
TRI·STATE® from T/R to B Port
CD = 0.4 V (figure B)
Sl ='1, R4 = lk, C3 = 15pF
S2= 0, R3 = lk, C2 = 30pF
34
50
ns
tPRL
Propagation Delay trom Transmit Mode
to a Logical "0," T IR to A Port
tPRL = tPHZT + tpDHLA
46
70
ns
tPRH
Propagation Delay from Transmit Mode
to a Logical "1," T fR to A Port
tPHH = tpLZT +, tpDLHA
45
70
ns
tPTL
Propagation Delay from Receive Mode
to a Logical "0," T fR to B Port
tPTL = tPHZR + tpDHLB
31
50
' ns
tPTH
Propagation Delay from Receive Mode
to a Logical "1," T /R to B Port
tPTH = tPL.ZR + tpDLHB
35
50
ns
tPHZT
"
ns
30
ns
",
,"
Note1: "Absolute Maximum Ratings" are those values beyond which ,the safety of ,the device cannot,be guaranteed. Thev are not
meant to imply that the devicl'S should be operat~ at these limits~ The tables of "Electrical Characteristics" provide conditions for
actual device operation.
Note 2: Unless otherwise specified, min/max·limits apply across the 0° C to +70°C temperature range and the 4,75 V to 5.25 V power
supply range. All typical val ues given are for V CC ~ 5 V and T A = 25° C.
Note 3: All Currents into device pins are pOSitive; all currents out of device pins are negative. All voltages are referenced to ground
unless otherwise spec.ified:
_:
Note 4: Only onll output at a time should be shorted.
LogI~ and Connection Diagrams'
r------------,
,o-4-t?
'
~.D
Top View
I
AD
;
,
_ 1----- -____ ...I....r-o' B.
____
1-____ .__.;. ;;.. -___
...J"'""O
A.
:::J----AZ
~
A3
APORT
~____
__
_ ___
..J'"""'O
BZ
B3
:: 8:::::
1-____ ::
__ :::::::J=;::
___
AI
~
A1
0-;...____
BPORT
APORT
AO-'
20-VCC
A...... 2
19-BO
A2-3,
18-B1
A3-4
11-B2
A4- •
'Nsa20B
.a-B3
A5-6
15-84
,_~"
A6-1
14-B'
_ ___ ..J--O B1
A1-a
13-a6
CH'PDlSABLE- 9
12-B1
GND- ,10
11 -
i..
logic Table
Inputs
Chip Disable
o
o '
Resulting Conditions
Transmit/Recei.e
'0
A Port
B Port
OUT
IN
IN
x
TRI·STATE
x = Don't Care
TRI-STATE,
Note: INSB2DB is identical to the DPB3D4
0-32
BPORT
TRAN/ill
Switching Time Waveforms and AC Test Circuits
tr '" tf .;; 10ns
liIYoTO 9i1Yo
1,
INPUT
An OR 8n
OV
OUTPUT
Bn OR An
Vee
Vee
RI
INPUT
OUTPUT
DEVICE
UNDER
TEST
NOTE: CllNClUDES TEST FIXTURE CAPACITANCE.
FIGURE A. Propagation Delay from A Port to 8 Port or from B Port to A Port
tr = tf <; 100s
INPUT
10% TO 90".4
T/1i
OV
rOUTPUT
,
=-tr::~~:
,APORTl
I=-tr
'PHZT
PlZT
-
osv
---L
O,SV
--L
OUTPUT
B PO RT
I,
Vee
t---1----o B PORT
A PORT C>----1~-_I
S,:< 1
S2'" 1
Vee-+o
R3
R4
Vee
I •.,..
NOTE: C2 AND C31NCLUOE TEST FIXTURE
CAPACITANCE.
FIGURE B. Propagation Delay from T/R to A Port or B Port
0·33
~National
,APRIL 1978
~ Semiconductor
INS8212 8-Bit
Input/Output Port
General Description
Features
The INS8212 is an 8-bit input/output port contained in
a standard 24-pin dual-in-line package_ The device, which
is fabricated using Schottky Bipolar technology, is part
of National Semiconductor's INS8080A microprocessor
family. The INS8212 can be used to implement latches,
gated buffers, or multiplexers. Thus, all of the major
peripheral and input/output functions of a microcomputer system can be implemented with this device.
• 8-Bit Data Latch and Buffer
• Service Request Flip-Flop for Generation and Control
of Interrupts.
• 0.25 mA Input Load Current
• TRI-STATE TTLOutp\lt Drive Capability
• Outputs Sink 15 mA
• Asynchronous Latch Clear
• 3.65V Output f9r Dire.ct Interface to INSS080A
• Reduces System Package Count by Replacing Buffers,
Latches, and Multiplexers in Microcomputer Systems
• MICROBUSTM* Compatible
The INS8212 includes an 8-bit latch with TRI-STATE®
output buffers, and device selection and control logic.
. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.
INS8212 MICROBUS Configuration
~
07-00
INTR
OOB-OOI
~
~
Rm'f
CPU
GROUP
DATA
BUS
CONTROL
..
OS2 lNSB212
CLR
PERIPHERAL
..r1.
OSI
STB
MO
~
ADDRESS
BUS •
-,-
DIB~DII
TNT
M
I
C
R
0
.B
U
S
..
D7-0B
~
~
INTR
-RESET
CS
Lr
DIB-DI1
INT
~Os-~Ol
CLR INS8212
DS2
OS1
STS
MO
"'A
"1"
*Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
0-35
PERIPHERAL
.J"""L
I •.,;.w
Absolute Maximum Ratings
Temperature Under Bias Plastic ..... -65°C to +75°C
Storage Temperature" ..•....• ; -65°C to +160°C
All Output or Supply Voltages. . . . . .. -0.5V to +7V
All Input Voltages ............... -1.0Vt05.5V
Output Currents .. '. . . . . . . . . . . . . . . . . .. 125 mA
Note: Maximum ratings indicate limits beyond which. ~'rmanent damage may occur. Continuous operatioo at these Ilmi.ts is not intended and
should be limited to those conditions specified under de electrical characteristics.
,
,
.
DC Electrical Charac.ristiC$
TA = o°c to +75°C; Vee = +5V± 5%
Symbol
limits
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
IF
Input Load Current
STB,OS2, CLR, Ol,,-Ols Inputs
-0.25
mA
VF = 0.45V
IF
I nput Load Current
MO Inpu~
-0..75
mA'
VF = 0.45V
IF
Input Load Current
Ds,lnpul
-1.0
mA
VF = 0.45V
IR
Input Leak~Current
STB, OS2, c::LR, OI,-OISlnputs
10
IdA
VR ,=.5.25V
IR
Input Leakage Current
MO Input
30
p.A
VR = 5.25V
IR
os, Input
40
p.A
VR = 5.25V
V
Ie = -5mA
I nput
Lea~a!Jl!
Current
"
Ve
Input ForwardVoltl!.ge Clamp
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
VOL
Output "Low" Voltage
VOH
Output "High" Voltage ,
Ise
Short Circuit Output Corrent
1101
Output Leakage Current
High Impedance State
lee
Power Supply Current
,r
-1
051, MO Input Capacitance
COUT
0.45
V
"
10L = 15mA
V
10H=-lmA
-75
mA
Vo'= OV
20
p.A
Va = 0.45V/5.25V
130
mA'
V
3.65
4.0
-15
90
F = 1 MHz, VSIAS = 2.5\;, Vee =);~V, TA = 25°C
. Test
V
:;1:0
Capacitance*
Symbol
0.S5
Limits
Typ.
Max.
9pF
'12pF
OS2, CLR, STB, 011-01S Input CapacitanCjl
5pF
9pF
001-00S Output Capacitance
SpF
12pF
*This parameter is sampled and not 100% tested.
,0-36
AC Electrical Characteristics
TA
= o°c to +75°C.
Symbol
Vee
= +5V ± 5%
Parameter
Min.
Limits
Typ.
Max.
Units
tpw
Pulse Width
tpD
Data to Output Delay
30
ns
tWE
Write Enable to Output Delay
40
ns
tSET
Data Setup Time
15
tH
Data Hold Time
20
tR
Reset to Output Delay
ts
Set to Output Delay
30
ns
tE
Output Enable/Disable Time
45
ns
te
Clear to Output Delay
55
ns
30
Test Conditions
ns
ns
ns
40
ns
Switching Characteristics
Conditions of Test:
1. Input Pulse Amplitude = 2.5V.
2. Input Rise and Fall Times = 5n5.
3. Between 1 V and 2 V Measurements made at 1.5V
with 15mA & 30pF Test Load.
Test Load
15mA& 30pF
Alternllte Test Load
Vee
Vee
300
10.
::]
TO
:::'f
TO
»
600
.
1•
~
~
* including jig & probe capacitance
0·37
'·fJl
Timing Diagram
.__________'5:",,-", _
X
~'------------
DATA
STBORDS,.DS2
---,
5V
·.LI·-tH~ "'-------
.. j;==tPw____
~15Z-
__
"5V
------~--------~
____________________ . . . __ .." 1~.5_V_____..,..----
I---- tWE::l
OUTPUT
~Sl.DS2______'-.J57C
lI~
--------
~5V
.
_,"::x-~""~'""'"""-J:::-~-~--~-:~-~---~----:--.--O..t!V VOH
OUTPUT__-_-_-__-_-__-_-__.!::_:.
=-------------~~ j'
~I--- tPW----II
f
"0. _
15 V
I-00
._------
te
•
5V
O.5V
'I,,.--------)E
_____________________ ..J
'
15V
-
----~
X'-----------X
5V
-::-;:--_ _-f=~tSE::..:T=--l--"
1'--STBOROS,.OS2
~I --tH-----l -------~
'5V
DATA
. __________ j
.
1.5V
x
tPD~
l,,-------
OUTPUT
________________, 1.5V
STB
,
'
--------
---------
1.5V, .r--\.
__---,,1:
"\.1.5~-----I---t""':
V
DS1·0S2
1.5V
1.5V
tR.....!
D·38
VOL
INS8212 logic Diagram
DEVICE SELECr
IJI>
IJI>
0:::>
ST.
CLR
MO
DO,
£I>
004.
[]I>
01,
DO,
IJI> '
DI> 01,
DO,
or>
CIT>
DO,
rn::>
Logic Table A
---r-----T
STB
MO:
OATA OUT
EQUALS
IOS,·OS2)
CI>01,
TRI·STATE
TRI·STATE
~---------~-----------D-A-TA--LA~T~C~H-~
DATA LATCH
a
DATA LATCH
DATA IN
DATA IN
DATA IN
CLR '"""'\... resets data latch to the output low state.
DI>
Logic Table B
~--r(D~.Ds;I
a RESET
o
o
o
srn-ra-:-Tliii---0'
0
1"",-1
0
t------t---c---+---+---r--1 RESET
,
0
"Internal Service Request flip-flop.
01,
INS8212 Functional Pin Definitions
The foilowing describes the function of all the INS8212
input/output pins. Some of these descriptions reference
internal circuits.
enabled and the service request flip-flop is asynchronously
reset (cleared) when the device is selected.
Mode (MO): When high (output modeL the output
buffers are enabled and the source of the data latch
clock input is the device selection logic (OS1' OS2).
When low (input mode), the state of the output buffers
is determined by the device selection logic (OS1 . OS2)
and the source of the data latch clock input is the strobe
(STB) input.
INPUT SIGNALS
Oevice Select (OS1, OS2): When OS1 is low and OS2 is
high, the device is' selected. The output buffers are
D-39
.·1'11
INS8212 Func:tional Pin Definitions
continued
Strobe (STS): Used as data latch clock input when the
mode (MO) input is low (input mode). Also used to synC
chronously set the service request flip-flop, which is
negative edge triggered.
Pin Configuration
Data In (011-018): Eight-bit data input to the data
latch, which consists of eight O:type flip-flops. While the
data latch clock input is high, the Q output of each flipflop follows the data input. When the clock input
returns low, the data latch stores the data input. The
clock input high overrides the clear (CLR) input data
latch reset.
.
os;
Clear (CLR): When low, asynchronously resets (clears)
the data latch and the service request fl ip-flop. The
service request flip-flop is in the non-interrupting state'
when reset.
Vee
23
01,
22
01 8
DO'
2,
008
01 2
20
01,
002
'9
DO,
01 3
'8
01 6
003
17
006
'6
015
INS8212
01,
OUTPUT SIGNALS
Interrupt (INTI: Goes low (interrupting ,state) when
either the service request flip-flop ,is synchronously set
by the strobe (STB) input or the device is selected.
Data Out (0°1-0°8): Eight-bit data output of data
buffers, which are TRI-STATE, non-inverting stages.
These buffers have a common control line that either
enables the buffers to transmit the data from the data
latch outputs or disables the buffers by placing them in
the high-impedance state.
TNT
MO
004
'0
'5
005
STB
11
14
Clli
GNO
'2
'3
052
NOTE: INS8212
Identical to
DPB212
Applications in· Microcomputer Systems
Bidirectional Bus Driver
Vce
Gated Buffer
(TRI-STATE)
S B
r ......---,OATA
DATA r----"-.I
BUS'--x_ _yl
vce-.....- _ _ _ _ _--,
8US
STB
INPOT
DATA
(250,AI
GATING
CONTROL
DATA BUS
CONTROL
OUTPUT
DATA
(15mA)
(l.65V MIN)
(0 = l ~ R)
(I = R ~ L)
F
1=------.. . ---..
GNO
0-40
Applications in Microcomputer Systems
continued
Interrupting Input Port
S~~~~~ . .- - - . ,
{FROM INPUT
Interrupt Instruction Port
DATA
BUS
VCC
STB
DEVICE}
SYSTEM
INPUT
RESTART
INSTRUCTION
(RST 0 ~ RST7)
SYSTEM
RESET
I-
PORT
SELECTlDN1=,.-_ _ _ _..J
TO PRIORITY CKT
(ACTIVE LOW)
DR
INTERRUPT ACKNOWLEDGE _ - - -......
TO CPU
INTERRUPT INPUT
Output Port (with Hand-Shaki~g)
DATA
BUS
. - - -....,... OUTPUT STROBE
(HAND-SHAKING
SIGNAL FROM
OUTPUT DEVICE)
STB
SYSTEM OUTPUT
SYSTEM RESET
i=1 PORT SelECTION
'-----'!:J (LATCH CONTROL)
INS8080A Status Latch
~"
0, 9
0, 8
03
04
05
06
0,
INS8(J80A
SYNC
.,
12V
ov J
.,
081N
21
n
\...-~
0,
0,
OJ
'
3
4
5
6
03
0,
0,
06
0,
lL.!.LSTATUS
LATCH
15
---t 01
'-----f
.----..,
00
'----]
1
18
INS8212
20
CLOCK GEN
& DRIVER
DATA BUS
~LI
22
fi g~~ MD DS1
131' Y'
----.I
Vee
D-41
~ INTA
ri- Wli
HLTA
~
OUT
~
11
M'
'NP
~ MEMR
rll-
STACK
CSIN
BASIC
CONTROL
BUS
DATA
STATUS
I---"-+-+r-,.---t-'''----i
DATA
BUS
~
Physical Dimensions
'$
C.
'$
1.290
1---------(32.766) - - - - - - - - 1 -
0,600
(15,240)
I
MAX
fMAX
r-=-='-",.....=='-'-""-'-:.:J,..=..L:.:J..J.:~==-II GLASS
~c.
0,025
(0,635)
0,515-0,525
RAD
c
081
:t::
'-T-:-r-r"...,.,.,-r,:-r-,."."T":T"1=-r.:T"'T':'T"T.':',.."".,..=....... (13,
toI
CO
N
N
CO
,...
U)
;::
r
~~
0,685 '0,025
f - - - - (17,399 '0,635)
~I
3
'335J
0,200
(5,080)
0,160
0,590-0.620 § 1 j 4 )
If--c: (14,986-15.748)
MAX
II
f
J·
0,008-0,012
(0,203-0.305)
r-:'"
_
I
0.060-0,100
(1.524-2,540)
(0,508-1,778)
_II _
0,018'0.002
11(0,457,0,051)
t--
0,125
(3,115)
MIN
Ceramic Dual-in-Line Package
(J)
Order Number INS8212J
1.270
(32.258)
------~·..jl
MAX
13
1
0,062
(1,575)
0,540'0,005
RAD
0.030
(0762)
MAX
0,075
(1 905)
0040.
-160.0005
°
~~~L
.---L
I
0,009-0015
(0229-0381)
0075'0015
(1905'0381)-
I
1-
-I
f--~v~401
0,100
0018'0,003
--If--I0457'0,076)
0015
0125 iOJaij
(3,175) MIN
MIN
Epoxy DuaHn-Line Package {N}
Order Number INS8212N
National Semiconductor
Corporation
2900 Semiconductor Onve
Santa Clara. California 95051
Tel. (40a)' 737-5000
TWX' (910)339·9240
National SemIconductor GmbH
8000 Munchen 21
61f2fisenl'ieimerstrasse
·,·WestGermany
1el.089/915027
Telex. 05-22772
NS Inlernalionallnc., Japan
NS Eleclronics{Hong Kong) lid.
HSElectronics Do Brasil
NS ElaclrenicsPly.lId.
Miyake Buildmg
1-9Yotsuya. Shlfljuku-ku 160
Tokyo,Japan
Tel: (03) 355-3711
TWX. 232-2015 NSCJ-J
SthFloor,
Avda Bngadel¥oFan3 LlmaB44
11 AndarConJunto 1104
Jardlm Paullslano
SaoPauJO,Brasll
Telex' 1121006 CABINE SAO PAULO
Cm Stud Rd & Min Highway
Cheung Kong ElectroniC Bldg
4 Hmg VIP Street
Kwu~ Tong
KOWloon. Hong Kong
1eI3'411241-8
Telex 73866 NSEHK HX
Cable NATSEMI
Bayswater, Vlctona 3153
Australia
Tel 03-729·6333
Telex' 32096
National does not assume any responsibility for use of any circuitry described, no CIrCUit patent licenses are Implied and National reserves the fight. at any time without notice. to change said circuitry.
0-42
'
AUGUST 1978
~National
~'Semiconductor
INS821618226 4-Bit Bidirectional
Bus Transceivers
General Description
The OlEN input controls the direction 01 data flow,
which is accomplished by forcing one of the pair of
buffers into its high-impedance state and allowing
the other to transmit its data. A simple two-gate
circuit is used for this function.
The INS8216 and INS8226 are four-bit bidirectional
bus drivers for use in bus oriented applications. The
non-inverting INS8216 and inverting INS8226 drivers
are provided for flexibility in system design.
Each buffered line of the four-bit driver consists of
two separate buffers that are TRI-STATE'" to achieve
direct bus interface and bidirectional capability. On
one side of the driver the output of one buffer and the
input of another are tied together (DB);' this side is
used to interface to the system side components
such as memories, 1/0, etc., because its interface is
TTL compatible and it has high drive (50mA). On the
other side of the driver the inputs and outputs are
separated to provide maximum flexibility. Of course,
they can be tied together so that the driver can be
used to buffer a true bidirectional bus. The DO
outputs on this side of the driver have a special high
voltage output drive capability so that direct interface to the 8080 type CPUs is achieved with an
adequate amount of noise immunity.
Features
• Data bus buffer driver for 8080 type CPUs
• Low input load current -
• Power up-down protection
• The INS8216 has non-inverting outputs.
• The INS8226 has inverting outputs.
• Output high voltage compatible with direct inter·
face to MOS
'
• TRI·STATE outputs
The CS input is a device enable. When it is "high" the
output drivers are all forced to their high-impedance
state. When it is a "low" the device is enabled and
the direction of the data flow is determined by the
OlEN input.
• Advanced Schottky processing
• Available in military and commercial temperature
ranges
• MICROBUSTM' compatible
INS821618226 MICROBUS
Configuration
Logic Diagrams
DlO
INsa2lS/8226
USER
INPUTS
3-0
0.25mA maximum
• High output drive capability for driving system
data bus - 50mA at 0.5V
Dlo
DBo
DBO
000
DOo
0]-00
OBJ-DBO
mrn
01,
OUTPUTS
3-D
M
00,
0.,
DO,
01,
I
C
R
0
DI,
lOB,
USER
ilTEN
01,
0.,
DB,
e!,
DO,
B
U
S
DI,
DI,
DB,
IllEN
USER
INPUTS
).,
083- 0BO
USER
OUTPUTS
J.4
DB,
DO,
D03
iiTEN
OlEN
07-04
cs
INsa21S
INSB216/122S
'Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
0-43
INS8226
'"
II."
Absolute Maximum Ratings
All Output and Supply Voltages
All Input Voltages
Output Currents
Lead Temperature
(soldering, 10 seconds)
Storage Temperature
Power Dissipation'
Cavity Package
Molded Package
Min
-0.5
-1.0
-65
Operating Conditions
(Note 1)
Max
+7.0
+5.5
125
+300
Units
V
V
mA
Supply Voltage, Vcc
INS8216, INS8226
4.75
'c
Temperature, T A
INS8216, INS8226
0
+ 150
'c
1160
1000
Min
Max
5.25
+70
Units
V
'c
mW
mW
"Derate Cavity Package at BO·C/W above 70'C;-derate Molded
Package at 90'C/W above 70'C_
,
DC Electrical Characteristics Vcc = 5V
,
± 5% (Notes 2, 3, and 4)
Limits
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVERS
VIL
Input Low Voltage
ViH
Input High Voltage
IF
Input Load Current
VF
fR
Input Leakage Current
V R ::: 5.25V
Vc
Input Clamp Voltage
Ic
VOL1
Output Low Voltage
10L = 25mA
0.3
0.45
V
VOL2
Output Low Voltage
INS8216 INS8226 -
0.5
0.6
V
VOH
Output High Voltage
10H = -10mA
Isc
Output Short Circuit Current
Vcc
1101
Output Leakage Current TRI·STATE
Va = 0.45V/5.5V
0.95
2
= 0.45V
=
-0.03
= 5.0V
-0.25
mA
10
JAA
-1.2
-5mA
10L ::: 55mA
10L = 50mA
V
V
2.4
3.0
-30
-75
V
V
-120
100
mA
JAA
RECEIVERS
V1L
Input Low Voltage
V 1H
Input High Voltage
IF
Input Load Current
VF
Vc
Input Clamp Voltage
Ic = -5mA
VOL
Output Low Voltage
10L = 15mA
0.95
2
= 0.45V
=
VOH1
Output High Voltage
10H
Isc
Output Short Circuit Current
Vo::: OV
1101
Output Leakage Current TRI·STATE
Vo
-1mA
-0.08
0.3
3.65
-15
V
V
-0.25
mA
-1.2
V
0.45
4.0
-35
= 0.45V15.5V
V
V
-65
mA
20
JAA
0.95
V-
CONTROL INPUTS (CS, OlEN)
V 1L
Input Low Voltage
V1H
Input High Voltage
IF
Input Load Current
VF = 0.45V
IR
Input Leakage Current
VR ::: 5.25V
Icc
Power Supply Current
INS8216
INS8226
2
V
-0.15
95
85
D-44
-0.5
mA
20
JAA
130
120
mA
mA
.-
AC Electrical Characteristics
(Notes 2, 3, and 4)
Limits
Symbol
Parameter
INS8216/8226 -
= 5.0V
Vee
Conditions
Typ
Max
Units
15
25
ns
20
16
30
25
ns
ns
45
35
65
54
ns
ns
20
35
ns
± 5%
= 30pF, R1 = 300Q,
= 600Q
= 300pF, R2 = 90Q,
= 180Q
t p01
input to Output Delay, DO Outputs
CL
R2
tp02
Input to Output Delay, DB Outputs
INS8216
INS8226
CL
R2
Output Enable Time
INS8216
INS8226
DO Outputs: C L
R1 = 300Q/10kQ,
R2
600Q/1 kQ
tE
Min
= 30pF,
=
= 300pF,
=
=
C L = 5pF,
R, = 300Q/10kQ,
R2 = 600Q/1 kQ
DB Outputs: C L = 5pF,
R1 = 90Q/10kQ,
R2 = 180Q/1 kQ
DB Outputs: C L
R1
90Q/10kQ,
R2
180Q/1 kQ
to
Output Disable Time
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for
actual device operation.
Nota 2: Unless otherwise specified, minimax limits apply across the O'C to + 70'C temperature range for the INS8216 and INS8226. All
typical values are given for Vce = 5V and TA = 25'C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground
unless otherwise specified.
Note 4: Only one output at a time should be shorted.
Capacitance
TA
= 25'C
Note: This parameter is periodically sampled and is not
100% tested. Condition of measurement is f = 1MHz,
VSIAS = 2.5V, Vec = 5.0V, and TA = 25 'C.
Limit
Symbol
Min
Parameter
C,N
Input Capacitance
COUT
Output Capacitance
DO Outputs
DB Outputs
Max
Units
4
6
pF
6
13
10
18
pF
pF
Typ
Test Conditions
Test Load
Input pulse amplitude of 2.5V.
Input rise and fall times of 5.0ns between 1.0V and 2.0V.
Output loading is 5.0mA and 10pF.
Speed measurements are made at 1.5V levels.
Cl
¥'V
,v
i--tpo-I
~'V
I
1---'-1, ---.1
OUTPUTS
R2
3V
I
OUTPUT
[NABLE
.,
OUT
SWitching Time Waveforms
INPUTS
I
Cim~;
)('V
X'V
1-'01~
I
VOH
~VOl
I
D-45
3V
OV
I.W.
f~
Pin Configuration
.~
U)
CHIP SElECT
cs
16
Vee
DATA OUTPUT
DOD
15
DlEN
DATA BUS
s:::
,.
DBo
BIDIRECTIONAL
!lATA IN ENABLE
(DIRECTION CONTROL)
003
DATA OtiTPUT
DB,
DATA BUS
C\'I
D~TA INPUT
010
DATA OUTPUT
001
13
INS821S1
8226
11
Oil
DATA INPUT
DATA BUS
DBl
11
002
DATA OUTPUT
U)
BIDIRECTIONAl
01,
10
DB2
DATA BUS
.:
:::s
DATA INPUT
m
GNO
012
BIDIRECTIONAL
BIDIRECTIONAL
DATA INPUT
NOTE: THE INS8216/8226 ARE
IDENTICAL TO THE
DP8216/6226.
Physical Dimensions
inches (millimeters)
0.185
1---
0.310
-I
09.939)
MAX
!
0.025
(7.874)
[MAX
-- --
fu~~·~
GLASS
11.291
a:J911
MAX
~
11.290-0.320
(7.366-8.128)
0.150
(4.1164)
GLASS
SEALANT ~
r-----"-l__
~
MA~
'_1
--
.
.
-
-
0.008-0.012
iO.203-03D51
MAX
10.127)--; i- "'_ IV1AX
0.070-.0.070
~' _lmj'T7il
I
+-
I.
_~5~
-J'e-- I
(1.210)--
I
i
0.l85 '0.1115
'-----(9.779 0.635)
~
(5.080)
a.060 '0.0115
~.524
II
i
I I
~
I
.---
~018 '0.002
II
.;__
(iI.457 --;0:051) --',
----,-t-
~~:~~: :~:~~.:)
---I
0.125
(i175j
MIN
l6·Lead Cavity DIP (J)
Order Numbers INS82l6J, INS8226J
NS Package Number J16A
0.870
-(22.0981--·-MAX
0.092
l6·Lead Molded DIP (N)
Order Numbers INS82l6N, INS8226N
NS Package Number N16A
Note: The IN$821618226 are identical to the DP821618226.
Nalir.mal Semlcondiictat
Corporation
290D Semiconductor Drive
Santa Clara, California 95051
Tel.: (408) 737-5000
TWX, (9101 339·9240
NatiollJl Semiconductor GmbH
8000 Munchen 21
Eisenheimerslrasse 61/2
West Germany
. Tel.: 089/9'15027
Telex: 05-22772
NS International Inc., Japan
Miyake Building
1-9 Yotsuya. Shinjukllcku 160
Tokyo, Japan
Tel.: (03) 355-3711
TWX: 232-2015 NSCJ-J
National Semiconductor
(Hong Kong) Ltd.
81h Floor,
Cheung Kong .Electronic Bldg
4 Hlng Yip Street
Kwufl Tong
Kowloon, Hong Kong
Tel.: 3-411241-8
Telex: 73866 NSEHK HX
Cable: NATSEMI
NS Electronics Dc Brasil
Avda Brigadelro Faria lima 844
11 Andar Conjunto 1104
Jardim Paulistano
Sao Paulo, Brasil
Telex:
112..1008 CABiNE SAO PAULO
NS Elletronlcs Ply. ltd.
Cnr. Stlld Rd. & Mtn. Highway
Bayswater, Victoria 3153
Australia
Tel.: 03-729·6333
Telex: 32096
National does not assume any responsibility for use of any circuitry d6SGribed; no circuit palefi! licenses are implied, and National reserves the right, at an1 time withOut notice, to change said circuitry.
0-46
APRIL 1978
~National
-z
~ Semiconductor
en
(X)
INS8255 Programmable Peripheral Interface
(II
(II
N
""CJ
General Description
The INS8255 is a programmable peripheral interface
contained in a standard, 4().pin dual·in·line package. The
chip, which is fabricated using N·charinel silicon gate
technology, functions as a general·purpose parallel
input/output interface in National Semiconductor's
N8080 microcomputer family. The functional configura·
tion of the INS8255 is programmed by the system
software so that normally no external logic is required to
interface peripheral devices.
signals with the peripheral device. In the third mode
(Mode 2), the INS8255 enables communications with a
peripheral device or structure via one bidirectional 8·bit
bus port (Port A). "Handshaking" signals are provided
over the lines of Port C in this mode to maintain proper
bus flow discipline.
The INS8255 has three basic modes of operation that
can be selected by the system software. In the first mode
(Mode 0), the INS8255 provides simple input and
outqut operations for three 8·bit ports. Data is simply
written to or read from a specified port (port A, 8 or C)
without the use of "handshaking" signals. In the second
mode (Mode 1), the INS8255 enables the transfer of
input/output data to or from a specified 8·bit port
(Port A or BI. in conjunction with strobes or "hand·
shaking" signals. Ports A and B use the lines of Port C in
this mode to generate or accept the "handshaking"
Features
• Outputs Source 1 mA at 1.5 Volts
• 24 Programmable Input/Output Pins
• Direct Bit Set/Reset Capability
• TTL Compatible
•
Reduces System Component Count
• MICROBUSiM * Compatible
INS8255 MICROBUS Configuration
c8
iil
3
3
m
...
"6"
C"
CD
""CJ
CD
::::T
CD
-i;D1
(")
CD
ADDRESS
BUS
DATA
BUS
CPU
GROUP
CONTROL
BUS
Typical Diagram of MODE 0 operation. The 8 bit ports A, B. C
are defined by the user's program to be either an input or an
output from/to the peripherals.
*Trademark. National Semiconductor Corp.
© 1978 National Semiconductor Corp.
0·47
'1•.1
DC Electrical Characteristics
Symbol
Min.
Parameter
VIL
Input Low Voltage
V 1H
Input High Voltage
VOL
Output Low Voltage
V OH
Output High Voltage
Typ.
Max.
Unit
0.8
V
Test Conditions
:
'.
V
2.0
--;-
IOH[l]
Darlington Drive Current
Icc
Power Supply Current
V
IOL =.1.6mA
V
IOH = -50,uA (-100/1A for D.B. Port)
2.0
mA
VOH= 1.5 V, REXT = 390n
40
mA
0.4
-
2.4
---- I-----
NOTE:
1. Available on 8 pins only of ports Band C. Selected randomly.
AC Electrical Characteristics
Symbol
-
Parameter
Min.
Typ.
Mal<.
Unit
tww
Pulse Width of WR
400
ns
tow
Time D.B. Stable before WR
50
ns
two
Time D:B. Stable after WR
35
ns
tAW
Time Address Stable before WR
20
ns
tWA
Time Address Stable after WR
20
tcsw
Chip Select on to WR
tWB
Delay from WRto Output
tRP
Pulse Width of RD
405
ns
tlR
RD Set-Up Time
0
ns
ns
450
'.
500
100
ns
ns
tHR
Input Hold Time
tRD
De!ay from R 0 = 0 to System
B~s
295
ns
ns
tRH
Delay from RD =.1 to System Bus
150
ns
tHZ
RD = 0 to TRI.STATE oLBus Drivers
150
ns
tAR
Time Address Stable before RQ
tCSR
Time CS Stable before R 0
tAK
Width of ACK Pulse
tST
tps
10
..
ns
50
70
ns
500
ns
Width of STB Pulse
500
ns
Set-Up Time for Peripheral
60
ns
tPH
Hold Time for Peripheral
180
ns
tRA
HolE...Time, Address Bus Trailing Edge
to RD
0
ns
tRC
Hold Time for CS after RD = 1
5
tAD
Address Bus Valid to Data Valid
ns
400
ns
tKD
Time from ACK = 1 to Output Floating
480
ns
two
Time from WR = 1 to OBF = 0
650
ns
tAO
Time from ACK = 0 to OBF = 1
450
ns
tSI
Time from STB =0 to IBF
450
ns
tRI
Time from RD = 1 to IBF = 0
360
ns
tACSO
Address Bus Valid to CS
40
ns
tACSl
Address Change to CS OFF
40
ns
20
0-48
I
Test Conditions .'
Timing Waveforms
.
tRP---_
-~
---'f;:
r--tjR---------
.-tHR~1
INPUT
__
r
)
tACSO-----..-..
cs
_ _ tRA--------......,.
tAR_~_
K
~
tCSR
I
-----------------
07- 00
tACSl
-----tRA----
--
)
1~--~---~:_:_-tRO--=
tRH~--~-__1
0-
-"-tHZ---~
Mode 0 (Basic Input)
.
\oVR
'WW----~
~r
C
-c r-
=!
I--tWO
tDW -
07-00
tAW
~-"--~'WA--~
-~
=> r-tcsw
K=
.
tACSO-
~
OUTPUT
twB
Mode 0 (Basic Output)
__
-~tST
__
STB------------~
IBf _ _ _ _ _ _ _ _ _ _- - 1
INTR
----------------1--'
Ro--------~---------I------~
_---tps-_~
Mode 1 (Strobed Input)
0-49
____ tACSl
Timing Wavefonns (confd.)
w. - - - - - - - - -...
0IfF-----~----_+--~---~-~
INTR
----------+--""
Mi----------------+---------------~----~
OUTPUT
Mode 1 (Strobed Output)
i'VR---",
OBF---------~~--+_-'"
INTR - - - - - -.........,.
~----------------------+-~I
STi------________
'1
"F ----___________
~
~
~
E
H
P
I
R
E
P
..,(1
_______________ _
.Ro------~----------------_r--~--~~----------~----...,.
DATA FROM
PERIPHERAL TO 8266
Mode 2 (Bidirectional)
0:50
INS8255 Block Diagram
t
I
r-
......
""-
GROUP
A
CONTROL
GROUP
A
PORT
A
""-
:...
1/0
...... PAl
- PAO
r 131-40.1-4)
(8)
f-
I
l
.
07 - DO
127-34)
+-+
OATA
BUS
BUFFER
+
GROUP
A
PORT C
UPPER
(4)
~
.....
1/0
PCl -PC4
110-13)
.....
1/0
PC3- PCO
114-171
I-
...
8-BIT
INTERNAL
OATA 8US
...
t
r
GROUP
B
PORT C
LOWER
(4)
~
l-
t
I
AD
~
WR ~
AI
AO
RESET
~
~
~
REAO/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
~
(26)
POWER
SUPPLIES
......
.tL
.-
...
I
(6)
1--.J!l.....-
I-~
+5 V
GND
GROUP
B
PORT B
(8)
~
I/O'
PB1-PBO
~ 118-25)
Ij
NOTE. APPLICABLE PINOUT NUMBER{;
ARE INCLUDED WITHIN
.
PARENTHESES.
INS8255 Functional Pin Definitions
The following describes the function of all the INS8255
input/output pins. Some of these descriptions reference
internal circuits.
bits of the A 15 - AO Address Bus, control the selection
of one of three 8·bit ports (A, B and C) or the internal
control word register as indicated below_
INPUT SIGNALS
A,
Ao
Selected
Chip Select (Cs), Pin 6: When low, the chip is selected.
This enables communication between the INS8255 and
the I NS8080A microprocessor.
0
0
1
1
0
1
0
1
Port A
Port B
Port C
Control Word Register
Read (RD), Pin 5: When low, allows the INS8080A to
read data or status information from the I NS8255.
Write (WR), Pin 36: When low, allows the INS8080A to
write data or control words into the INS8255.
Port Select (AO, A1 ),'Pins 9 and 8: These two inputs,
which are normally connected to the least significant
.
Reset, Pin 35: When high, clears all the internal registers
of the chip and sets Ports A, Band C to the input high
impedance mode.
+5 Volts, Pin 26: VCC supply.
Ground, Pin 7: O-Volt reference.
0·51
'1.1
INPUT/OUTPUT SIGNALS
and B. The system software includes a Bit Set/Reset
Control Word (see figll'e) for setting or resetting any of
the eight bits of Port C_ When Port C is being used· as a
status/control for Port A or B. the Port C bits can be set
or reset by using the Bif Set/Reset Control Word as the
second byte of OUT Instruction(s).
Data (07-00) Bus. Pins 27-34: This bus comprises eight
TRI-STATE input/output lines, The bus provides bidirectional communication between the I NS8255 and
the I NS8080A_ Data is routed to or from the internal
data bus buffer upon execution of an OUT or IN
Instruction, respectively. by the INS8080A. In addition.
control words and status information are transferred
through the data bus buffer.
Pin Configuration
Port A (PA7-PAOl. Pins 37~40. 1-4: This 8-bit input!
output port forms one 8-bit data output latch/buffer
and!or one 8-bit data input latch. .
PA3
PA2
PA,
PAo
NOTE
The system software uses a Mode Definition
Control Word (see figure) as the second byte of
OUT Instruction(s) to program the functional
configuration of Ports A through C.Whenever the
mode is changed. all output registers (and status·
flip-flops) are reset.
RD
E
GNO
A,
AO
'PC7
Port B (PB7-PBO). Pi~s 18-25: This 8-bit input/output
port forms one 8-bit data output latch/buffer or one
8-bit data input buffer.
"., I.. ..I
MSW
\~-_----'r- __..JI
flAG:
'
1 = ACTIVE
MODE SELECTION:
00 = MODE 0
01 =MODE 1
IX' MODE 2
'0
Pe6
PCs
PC4
PCO
PC,
Port C (PC7-PCO). Pins 10-17: This 8-bit input/output
port forms one 8-bit data output latch/buffer or one
8-bit data input buffer. The port can be split into two
4-bit ports under the mode control. Each of these 4-bit
ports contains a 4-bit latch that may be used for the
control and status signals. in conjunction with Ports A
11
03
'3
,4
'5
'6
,9
20
02
RESET
00
0,
02
03
04
05
06
07
VCC
PB7
0,
DO
PORT B:
l ' INPUT
0= OUTPUT
PORT C
ILOWER):
1 = INPUT
0= OUTPUT
PB6
PB5
PB4
PB3
I
PORT A:
1" INPUT
0= OUTPUT
MODE
SELECTION:
O'MODEO
\ 1 = MODE 1
PORTe
IUPPER):
l ' INPUT
0= OUTPUT
I
GROUP B
\~____________~I____________- - J
1
GROLIPA
Mode Definition Control Word Format
I · I .. I .. I
01
00
SET7~1sET \~--~--.,-__-,-_-,I \\.._--_--,,:-------JI SETI~lSET:
FLAG:
0= ACTIVE
Wi!
3'
30
29
28
27
26
25
24
23
22
21
INS8255
,2
PC2
PC3
PSo
PS,
PB2
04
PA4
PAS
PA6
PA7
39
38
37
36
35
34
33
32
°
NOTUSED
BIT SE'LECT:
000 =
001 =1
010= 2
011 =3
100' 4
101 =5
110 =6
11.1 = 7
Bit Set/Reset Control Word Format (Port COnly)
0-52
1 = SET
0 = RESET
1
Operating Modes
Mode 0 (Basic Input/Output)
In this mode, simple input and output operations for each of the three ports are provided. No "handshaking" is required; data is
simply written to or read from a specified port.
-,-----------------=t=--
Mode 0 Port Definition Chart
i
No.
Control Word Bits
r;-r~~-fo:-l
o
1
n 0- at
I
-1-f----,~-1
3
I
0
6
1
0
~:_;l--~~~~~--;~rtB
0
i
0
0
OUTPUT
OUTPUT
OUTPUT
0 -----+
0
1
OUTPUT
au-TPUT
OUTPUT
INPUT
0
0
0
1
0
OUTPUT
OUTPUT
INPUT
OUTPUT
0
I
0
0
_~l
I 1
h
1
I
0
0
1
1
OUTPUT
OUTPUT
INPUT
INPUT
0
OUTPUT
INPUT
OUTPUT
OUTPUT
0
1
OUTPUT
INPUT
OUTPUT
INPUT
+--~-+--~m~ 0 1 L~ OUTPUT INPUT INPUT
1 I ~~i
1 tyUTPU-r+INPUT-I-NPUT
t_o _
___8 __ ~_
0_ I 1
0
~_ ~-+---~r------:+_L~_I_~-t1-- ~ 0
0 I 1
-
1~-
-'2
I
I
0
1[
0
0
1
0
1
0
0 --J-1
1
I
0 I
o I
1
1
1
1
I
13
1
0
14
1
0
o
15
01>10
0
I
I
0
I
1
I
1
I
0
1
i
0
0
0
0
0
I
0
1
I
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
OUTPUT I OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT! INPUT
INPUT
0
INPUT
I NPuTToUTPUT
OUTPUT
1
INPUT
INPUT
OUTPUT
INPUT
INPUT
I INPUT
INPUT
OUTPUT
INPUT
INPUT
!NPUT
INPUT
~Io
o
1
OUTPUT
0
--7- -:;- -r a-HI0 1-=-0:=
~_~
(~:~~)
0
0
t~--~J
I-
--~~-~lT-~~
0
!
-~_ _1_t~_ _0_1
___~_ _1_
D3 -
---
Group B
O~O
I
I
1
0 ~
I
D4
Group A
BASIC INPUT TIMING
W7-00 FOllOWS INPUT,
NO LATCHING)
AD
---t'--____/
\~_--J/
INPUT
D)-DO
------------j.------------- --
t DELAY TIME
- - t DELAY TIME
FROM RD
FROM INPUT DATA
BASIC OUTPUT
TIMING
(OUTPUTS LATCHED)
WR------------~
r--- SH-UP VIOLATION
-------------)(--
01- 0 0
-------------
----------
OUTPUT
t DATA
SET-UP
'---M""TOATA
Mode 0 Timing
0-53
)(----------
Operating Modes (cont'd.)
Mode 1 (Strobed Input/Output)
In thismode,a means for transferring input/output data to or from a specified port in conjunction with strobes or "handshaking"
signals is provided. Port A and Port B use the lines on Port C to generate or accept these "handshaking" signals in Mode 1. The
programmer can read the contents of Port C to test or verify the status of each peripheral device. Since no special instruction is
provided in the INS8080A microcomputer system to read the Port C status information, a normal read operation must be
executed to perform this function.
STBB
1BFa
INTR8
CONTROL WORD
0706050403°20100
11 f D 11
CONTROL WORD
07060504030201 DO
11 11IOtxJXt><]
11
I
1XWXlXI1/ 1 !XI
PC67
L_ _ _ _ _-... ::WJ~~T
STATUS WORD
Notes:
1. INTEA is controlled by bit set/reset of PC4 ,
2. 1NTES is controlled by bit set/reset of PC 2 ,
Mode 1 Input
IBF
(INPUT BUFFER FUIII - - - -......t---..J
STROBE ------t-~
NO PROTECTION
FOR THIS OPERATION
DATA
INPUT
------t---J
INTERNAL
INPUT lATCH
------t---J
AD
--------+------__________~----------------------------~
INTR _ _ _ _..........-'-_ _ _ _ _ _.J
Mode 1 Input Timing
D-54
Operating Modes (cont'd.)
MODE 1 (PORT AI
CONTROL WD.RD
CONTROL WORD
07060504030201 DO
D7 06 05 04 03 02 0100
11 I011 I011/0@D<1
11
Mode 2 Combinations
0-57
H4> 250 ns.
Note 3: Item 11 must be greater than Item 4 + 1.
only one line
~f a charact~r row, then
0-68
Item 21 must be either "1"
'
o~ "0" unless it
is the same
DP8350 Series Option Program Table
DP8350 Option: 80 Characters x 24 Rows, 5 x 7 Character Font, 7 x 10 Character Field
Item
No.
Parameter
1
Value
Dots per Character
5
Scan Lines per Character
7
Character (Font Size)
2
3
Dots per Character
7
Scan Lines per Character
10
Character Field (Block Size)
4
5
Number of Video Characters per Row
80
6
Number of Video Character Rows per Frame
24
7
Number of Video Scan Lines (Item 4 x Item 6)
240
8
Frame Refresh Rate (Hz) (two frequencies allowed)
9
Delay after/before Vertical Blank start to start of Vertical Sync (+/- Number of Scan Lines)
fl
10
Vertical Sync Width (Number of Scan Lines)
11
Delay after Vertical Blank start to start of Video (Number of Scan Lines)
12
Total Scan Lines per Frame (Item 7 + Item 11
13
Horizontal Scan Frequency (Line Rate) (kHz) Item 8 x Item 12)
14
Number of Character Times per Scan Line
15
Character Clock Rate (MHz) Item 13 x Item 14)
16
Character Time (ns) (1 7 Item 15)
17
Delay after/before Horizontal Blank start to Horizontal Sync Start (+/- Character Times)
18
Horizontal Sync Width (Character Times)
19
Dot Frequency (MHz) (Item 3 x Item 15)
20
Dot Time (ns) (1 7 Item 19)
21
Vertical Blanking Stop before start of Video (Number of Scan Lines)
(Range = Item 4 - lime to 0 lines)
22
Cursor Enable on all Scan Lines of a Row? (Ves or No) If not, which Line?
= Item
13';' Item 8)
= 60 Hz
fO
= 50Hz
4
30
10
10
20
72
260
312
15.6kHz
100
1.56MHz
641 ns
I
I
0
43
10.920MHz
91.6 ns
1
.'
Ves
I
I
•
23
Does the Horizontal Sync Pulse have Serrations during Vertical Sync? (Ves or No)
24
Width of Line Buffer Clock logic "0" state within a Character Time
(Number of Dot Time increments)
25
Serration Pulse Width, if used (Character Times)
26
Horizontal Sync Pulse Active state logic level (lor 0)
27
Vertical Sync Pulse Active state logic level (lor 0)
0
28
Vertical Blanking Pulse Active state logic level (lor 0)
1
No
4
-
1
FULL/HALF ROW CONTROL (PIN 5)
Device pin 5 converts the DP8350 programmed display
from 80 characters by 24 rows to 80 characters by 12
rows.
Full/Half
Row (Pin 5)
logic State
1
0
I
I
I
With pin 5 in logic "0" state, the 12 character rows are
equally spaced vertically on the CRT. Each row is spaced
by one full row of blanked video.
Also in this mode the address counter outputs address
the same memory space for two rows - the video row
and the blanked roW. Thus one half of the CRT memory
space is addressed with pin 5 in logic "0" state as
compared to pin 5 in logic "1" state.
Display
Size
80 by 24
--
80 by 12
D-69
PERIPHERAL
INTERFACE
I
VIDEO
INTERFACE
I
I
I
I
I
I
I
I
I
1--...-_----iI~h~~EUTE
I
I
I
1
I
I
I
I
I
I
I
MICRO
PROCESSOR
I
I
I
1
1
1
I
1
I
I
I
I
1
I
I
I
I
VIDEO
OUTPUT
1
I
I----~----~--~~-+I
HORIZONTAL
I
r _ _ _-'S'-'y"'NC'-'1
.-...:!~
1
I
I
:I
1
I
_ _.:!:.._ _ _.....I..J..._'-_..L.....,
VERllCAl
C. .
1-_ _",SYw:N..
CURSOR
ENABLE
1
THREE·TERMINAL
MONITOR
I
1
I
I
,I
Figure 6. System Diagram Using a Linb Buffer
PERIPHERAL
INTERFACE
VIDEO
INTERFACE
I
1
1
1
:----~----------~~
l-_p__..________.._____
I
I
I
1
I'
I
I
1
1
IDECODE
I
I
I
I
-ijl~TR1BUTE
I
I
MICRO·
I
PROCESSOR
1
1
I
I
I
I
I
I
I
I
1
I
I
VIDEO
1
OUTPUT
I
DISPLAY
:--~-~-i-~~~I
CONTROL
BUS
I
I
'---.-OR'"' ' ' O'"NT'' .':',' I
. -_ _ _~SYw:N..
C.... :
VERTICAL
I
.--"'-__""-___-''-'-___...L..,
~~~~~oTri.RMiNAl
1-,-_2.lSY~Nl:.C~I
SYSTEM CONTROL BUS
CRT CONTROLLER
CURSOR
I
I-_-"",N",AB""..
, ~I
~~---T--------------~
1
Figu,re 7. System Diagram with no Line Buffer
Note 1: If the Cursor Enable. Item 22, is"active ~n only one line of a character row, then Item 21 must be either "1" or "0" unless
it is the same as the line selected for Corsor Enable.
Note 2: Item 24 x Item 20 should be> 250 ns.
Note 3: Item 11 must be greater than Item 4 + 1.
D-70
Physical Dimensions
11052
ii575) -~,
RAD
0.5511 OJJ05
"
m.970 !I.127\
PIN NO. lINDENT--"
"
f--
0.600--0.620
Ir-115.240-15.7481
f 0':"
1_ _ _
--+O~~61;5
(15.815 0 ,381)
40-Lead Molded DIP (N)
NS Package Number N40A
2.020
:-------151.3(181
I
-I
I
i
0.520
m.Ws!-
MAX
saUAR~
"
1
r
,
i
0598
115.11191
MAX
40-Lead Cavity DIP (D)
NS Package Number D40C
Natlonal Simicondutfor
Corporation
2900 Semiconductor Drive
Santa Clara, California 95051
Tel.: (408) 737-5000
TWX: (910) 339-9240
National Semiconductor GmbH
8000 Muncher! 21
Eisenheimerslrasse 61/2
West Germany
Tel.: 089/9 15027
Telex: 05-22772
NS Internationallne .. Japan
Miyake Building
1-9 Volsuya. Shinjuku-ku 160
TOkyo, Japan
TeL: (03) 355-3711
TWX: 232-2015 NSCJ-J
National Semiconductor
(Hong Kong) lid.
8th Floor,
Cheung Kong Electronic Bldg
4 Hing Yip Sireet
Kwun Tong
Kowloon, Hong Kong
Tel.: 3-411241-8
Telex: 73866 NSEHK HX
Cable: NATSEMI
NS Electronics Do 8rasll
Avda Brigadeiro Faria Uma 844
11 Andar Conjunt(11104
Jardim Paulislano
Sao Paulo, Btasil
Telex:
1121008 CABINE SAO PAULO
NS Elactronici Ply. ltd.
Cnr. Stud Rd. & MIn. Highway
Bayswatsr, Victoria 3153
Australia
Tel.: 03-729-6333
Telex: 32096
National does not assume any responsibility for use of any circuitry described; no Circuit patent licenses are implied, and National reserves the right, at any time without notice, to change said Circuitry.
0-71
~National
SEPTEMBER 1978
Pub. No. 426305468'()Ol
~ Semiconductor
INS1771-1 Floppy Disk Formatter/Controller
General Description
The INS1771-1 is a programmable floppy disk formatter/
controller chip contained in a standard 40'pin dual-in·
line package. The chip. which is fabricated using
N-channel silicon gate technology. interfaces a floppy
disk drive directly to a computer interface bus. The
I NS1771-1 provides soft sector formatting. which may
be either IBM 3740 compatible or a user-selected sector
format.
•
Read Mode Capabil ities
Single/Multiple Record Read with Automatic
Sector Search or Entire Track Read
Selectable 128-8yte or Variable Record Length
• Write Mode Capabilities
Single/Multiple
Sector Search
Record Write
with Automatic
Entire Track Write for Diskette Initialization
•
The INS1771-1 is designed to operate on a multiplexed.
TR I-ST A TE® S-bit bidirectional bus with other busoriented devices. The c!1ip is programmed by the system
software via the bus and all data. status information. and
control words are transferred over the bus lines.
Programmable Controls
Selectable Track-to-Track Stepping Time
Selectable Head Settling and Head Engage Times
Selectable Three Phase or Step and Direction and
Head Positioning Motor Controls
•
Double Buffering of Data
• TTL Compatible
•
DMA or Programmed Data Transfers
Features
•
Reduces System Component Count
•
Soft Sector Format Compatibility
•
On-Chip CRC Generation and Checking
•
Automatic Track Seek with Verification
•
•
Provisions for Miniature Floppy Disk Interface
Direct Plug-in
FD1771-1
Replacement
for Western
INS1771-1 General (System Configuration
PARAllEl!
SERIAL
DATA
INTERFACE
flOPPY
DISK
DRIVE
© 1978 National
Se~iconductor Corp.
0-73
Digital
AbsolU_ Maximum Ratings
,
"
""
"'"
VOO with Respect to VB . . . . . . . . . . . . . . . . . . +20 V to -0.3 V
Max Voltage to Any Input with Respect to VBB ... +20V to -0.3 V
Operating Temperature . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
,
0
°
Storage Temperature . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
.'
,
"
"
"
,
Note: Maximum ratings indicate limits' beyond which permanent
damage may occur. Continujs operation at these limits is not
intended and should be limite to those conditions specified under
dc electrical characteristics.
"
DC Electrical Characteristics
TA = o°c to +700 C, VOO = +12.0V ± 0.6V, VBB = -5.0 V ± 0.25 V, VSS = OV, VCC = +5V ± 0.25V, 100 = 10mA
nominal, ICC = 30mA nomin~l, IBB = 0.4 nA nominal.
;
,
Symbol
Characteristic
III
Input Leakage
ILO
Output Leakage
VIH
Input High Voltage
Min
Input Low Voltage (All Inputs)
VOH
Output High Voltage
VOL *
OutP~t
Unit
Conditions
10
jJA
VIN =VOO
10
jJA
VOl,JT= VOO
V
0.8
V
2.8
Low Voltage
0.45
Note: VPl- .. 0.4 V when int~rfacing with 101l\l-power Schottky part.
~
Max
2.6
VIL
'VOL
Typ
V
10 = -100jJA
V
10 = 1.6mA
(10 < 1 mAl.
0.5Von WG.
.
AC Electrical Characteristics
TA;" o°c to +70°C, VOO = +12V ± 0.6V. Vaa = -5V ± 0.25 V, Vss =,OV. VCC = +5 V.± 0.25 V.
Symbol
Characteristic
Min
Typ
Max
Uni1
Conditions
Read.Operations
tET
Setup AOOR & CS to RE
tHLO
Hold AOOR & Cs from
tRE
RE Pulse Width
tORR
ORO Reset from RE
INTRa Reset
tlRR
f~om
RE
100
:ns
10
,ns,
500
RE
tOACC
" Data Access from RE
tOOH
Data Hold from RE
CL';' 2SpF
os
50
500
ns
3000
450
ns "
ns '
CL = 25pF
150
ns"
CL = 25pF
Write Qperations
tSET
Setup AO.DR &:CS to WE
tHLO
Hold AOOR & CSfrom WE
twE
tORR
WEPuise Width
c'" ,
,.
Hio
ns
10
ns
350
ns
ORO Reset from WE
ens
,ns
500
tlRR
INTRa Reset from WE
tos
Data Setup to WE
250
tOH
Data Hold from WE
150
3000
'o.
0-74
ns
ns
(see note)
i'
AC Electrical Charac1eristics (cont.)
TA ~
o°c to +70°C, VDD
~ +12 V ± 0.6 V, VBB ~ -5 V ± 0.25
v,
VSS ~ 0 v, VCC ~ +5 V ± 0.25 V.
,
---------,--------~-----r_----~-----,-----,--------,------~-----------------------~
Symbol
I
Characteristic
External Data Separation (XTDS
Min
Typ
Unit
Max
tpwx
tcx
Pulse Width Rd Data & Rd Clock
150
Clock Cycle Ext
2500
ns
tOE X
Data to Clock
500
ns
tDDX
Data to Data Cycle
2500'
ns
350
ns
____'--_____==-_~___________=----.l~___ '___~__~
Internal Data Separation (XTDS
tPWI
I
Conditions
~ 0)
I
~ 1)
I
Pulse Width Data & Clock
_~_l...~I~c~:~~~~rna~ _______
I
150
I
I
1000
'1 ~~~_ J______ l_~OOO
I
ns
.L~___.l_______________________
Write Data Timing
I
tWGD
Write Gate to Data
tpww
Pulse Width Write Data
tCDW
Clock to Data
tew
Clock Cycle Write
tWGH
Write Gate Hold to Data
1200
ns
I
20 0 0
140 0 0
00
I
1'1 0 0
300ns ± ClK tolerance
I
n~ S:s _~LI_±_0_'5_%_±
500
±0.5% ± ClK tolerance
o
____________Li________
Miscellaneous Timing
tCD 1
Clock Duty
175
ns
tCD2
Clock Duty
210
ns
tSTP
Step Pulse Output
3800
tDIR
Di r Setup to Step
tMR
Master Reset Pulse Width
4200
ns
I
24
10
2 MHz ± 1% (see note)
J.1S
These times doubled
when ClK ~ 1 MHz
J.1S
lip
Index Pulse Width
10
J.1S
tWF
Write Fault Pulse Width
10
J.1S
Note: Timings are given for 2 MHz Clock. For those timings noted, values will double when chip is operated at 1 MHz.
Timing Waveforms
121
r--_--,--I-,I-----IO-R-R-~-----c-c ""-1
--I"' ---:-1 _________.....r---'
~--IIRR-I
DAO VOL
INTRO
IHlO~1 I_I
I
AD, Al, CS(1)
~!
INTRO
VOL
I
(BUFFERS TAI·STATEDI
. ISET
I
AD. Al.;:S1ll
~
WE
r-hJ
----i--.....
I....-.-i
tDACe
ORO VOL
~~~---,
Ai' --:-I.--,.I-IRE-rl-----~-
DATA VAUO IDAll
READ DATA
r·~-----c-----------O'"
--l I-tORR
VOH
i---
__------~r-
---i--;;;;;::Jf:"L-----I
-I I+- I
IHlO
I
~I
:-IWE
----~I
--=j..- - - - - - - -
I
II~
~IOS-
I-
____~
"DH
NOTES:
1. E§ MAY BE PERMANENTL Y TIED LOW IF
DESIRED.
2. WHEN WRITING DATA INTO SECTOR, TRACK,
OR DATA REGISTER, USER CANNOT READ
THIS REGISTER UNTIL...AT LEAST B/.I.s AFTER
THE RISING EDGE OF WE. WHEN· WRITING INTO
THE COMMAND REGISTER, STATUS IS NOT
VALID UNTil SOME 12/.1.$ LATER. THESE TIMES
ARE DOUBLED WHEN eLK'" 1 MHz.
Write Enable Timing
Read Enable Timing
D·75
VOL
IIL-------- Vil
---1.-.. .
taoH
NOTES:
1. CS MAY BE PERMANENTl V TIED LOW IF
DESIRED.
2. FOR READ TRACK COMMAND, THIS TIME MAY
BE 12 TO J2/.1.s WHEN s '" O. (THIS TIME
DOUBLES WHEN CLK '" 1 MHz.)
--I
1--.tIRR~
1-'
tSET
DATA VALID (OAl)
WRITE DATA
L.- - - - - - -
32",
V,H
Timing Wavefonns (cont.)
--I 1- t,wx
_I I-- tpwx
FDClDCK
-1l~
-I 1- tpwx
1---- t c x _ l _ 'cx -~I
MISSIN.G.
DAr
FDDATA
'1:'~'CNKG
____~n~____~n~______~t____
tpwx
+j . I--
tpwx
n
I-- tDEX -I
tpwx
1---1 I--
+j
n
I.JL
j..tDEx~l- tDEX - j _ t D D x _ 1
1_--tDDX
--l
NOTES,
1. ABOVE TIMES ARE DOUBI.ED WHEN eLK'" 1 MHz.
2. CONTACT Nse FOR EXTERNAL CLOCK/DATA
SEPARATOR CIRCUITS.
Read Timing (XTDS
= 0)
FODAlA
NOTES:
1. INTERNAL DATA SEPARATION MAY WORK FOR
SOME APPLICATIONS. HOWEVER, FOR APPLlCA·
TIONS REQUIRING HIGH DATA RECOVERY
RELIABILITY, Nse RECOMMENDS THAT EXTER·
NAl DATA SEPARATION BE USED.
2. fOCLOCK MUST BE TIED HIGH.
Read Timing (XTDS
WG
= 1)
-Jr------------------------------~I~
1- tWGD -1
tpww
'PWW
'PWW -I 1-I 1- --I r-
'PWW ~I
'WGH ~I 11- -I I-- tpww
..
- ____
...,.:0;,.·
WO _ _ _.....J
I
I
cw --..
1 - - tew -----t----t
I
t-'CDW-I
LAST DATA BIT
TO BE WRITTEN
Write Data Timing
TI' I
( VIH
l-tlP-1
Wi' ?
I
I+-. 'W' ----I
MR
I
tCYC
ClK
1---1
r--
I
tWR
I VIH
DIRe
VOH
VOL
J
STEP IN
tSTP
~I
V,H
'.DI""R'
-.1
STEP
VOL -----I
LrL
-I. J- tCD,
....:t 1.- teD2
Miscellaneous Timing
0-76
n
11
tSTP
STEP OUT
tSTP
~
J. -I I-- I-- -I I- +j I-- tSTP
n
tOIR n
n
L--J
L..t~
L--I
~(I--
INS1771-1 Block Diagram
FDCLOCK
FDDAlA
...._....l.:"'-__
XTDS
CONTROL
DRn
(30)
WG
129)
TG43
WPRT
WF
INTRO
MR
Os
Rl'
COMPUTER
INTERFACE
CONTROL
WE
AD
A1
CONTROL
PLA
CONTROL
(190 x 16)
CONTROL
DISK
INTERFACE
CONTROl
1-""",;:-_ PH2/DIRC
elK
HLT
POWER
SUPPLIES
r
Vee
VB8
Vss
140)
121)
(1)'
120)
~
•
•
~
+12V
'5V
NOTE: APPLICABLE PINOUT NUMBERS
ARE INCLUDED WITHIN
PARENTHESES.
-5V
GND
INS1771-1 Functional Pin Definitions
INPUT SIGNALS
The following describes the function of all INSl771-1
input/output pins, Some of these descriptions reference
internal circuits,
Chip Select (CS): When low, the chip is selected, This
enables communication between the INSl771-1 and the
CPU.
NOTE
In the following descriptions, a low represents a
logic 0 (0 Volt nominal) and a high represents a
logic 1 (+5 Volts nominal).
Read Enable (RE): When low coincident witb an active
(low) CS input, allows the CPU to read data or status
information from a selected register of the chip,
D-77
IIICI
Functional Pin Definitions (cont.}
Write Enable (WE): When low cON1cident with an active
(low) CS input, allows the CPU to write data or control
words into a selected register of the chip.
Index Pulse (iP): Goes low for 10 microseconds
(minimum) whenever an index mark is encountered
(once per revolution) on the diskette.
Register Select (AD, Al) Lines: These two inputs are
used in conjunction with either an active (low) REar
WE input to select an INSl771-1 register to read from
or write into as indicated below.
Track 00 (TROD): Goes low whenever the Read/Write
head is positioned over track 00 of the diskette.
,
Al
AD
RE
WE
0
0
0
1
Status Registe,
0
0
1
0
Command Register
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
Ready: When high before the execution of a Read or
Write command, indicates that the floppy disk drive is
ready for a Read or Write operation. When low, the
Read or Write operation is not performed and an interrupt is generated. However, a Seek operation is always
performed. The complement of the Ready input appears
as bit 7 (Not Ready) of the Status Register.
Selected Register
Track Register
Three-Phase Motor Select (3PM): When low, the threephase motor control interface is selected for the floppy
disk drive by the INSl771-1- When high or open, the
step-direction motor control interface is selected by the
INS1771-1.
Sector Register
Data Register
Master Reset (MR): When low, clears the Command
Register, resets bit 7 (Not Ready) of the Status Register
low, and makes the PH llSTEP output active low. When
the MR returns high, a Restore command is execufed
(regardless of the state of the Ready input from the
floppy disk drive).
Clock (ClK): This input pin requires a 2·megahertz
(±1%) squarewave clock as a reference for all internal
timing.
Oisk Initialization (DINT): When low coincident with a
Write Track command from the CPU, causes the Write
Track operation to be terminated and bit 6 (Record
Type/Write Protect) of the Status Register to be set
high.
Test: This input pin is normally tied to +5 Volts.
However, it may be used to disable the programmed
stepping rate delays for testing the INSl771-1 or for
. disk drives that do not require the long delay times to
change tracks. These delays are disabled by tying the
Test input to ground.
Head load Timing (Hl T): When high, the Read/Write
head is assumed to be engaged against the recording
medium (diskette). The Hl T input is sampled after each
10 millisecond internal delay after HlD is asserted.
NOTE
For a miniature floppy disk, a 1-MHz (±1%)
squarewave clock is required.
External Data Separator (XTOS): When low, the
composite read disk serial data (data bits and clock)
from the floppy disk drive is separated externally
by the user. When high or open, the composite read
disk data is separated by the internal data separator
of the chip.
VBB: -5 Volt supply.
VCC: +5 Volt supply.
VOD: +12 Volt supply.
VSS: Ground (0 Volt) reference.
Floppy Disk'Oata (FDDATA): This ·input pin provides either of the following serial data: both clock
and data bits (composite read disk data) when the
XTDS input is high; or externally separated data bits
when the XTDS input is low.
OUTPUT S'IGNAlS
Data Request (ORO): Open·drain output to the CPU
that goes high when the INSl771-1 is ready to transfer
a byte of data during a Read or Write operation. The
ORO output is reset low upon the completion of a byte
Read or Write operation.
Floppy Disk Clock (FDClK): This input pin provides
the externally separated clock when the XTDS input is
low. The FDClK input should be connected to +5 Volts
(logic 1) when the XTDS input is high.
Interrupt Request (lNTRO): Open-drain output to the
CPU that goes high at the completion or t.\lrmination of
any operation. The INTRO output is reset low when a
new command is loaded into the Command Register,
or Status Register Read.
Write Protect (WPRT): When low, immediately terminates a Write command and sets bit 6 (Record Typel
Write Protect) of the Status Register high. In addjtion,
an interrupt is generated when the WPRT input is low.
The WPRT input is sampled whenever a Write command
is received from the CPU.
Write Data (WD): Composite write disk 1:lata (both clock
and data bits of 500 nanoseconds in duration) output
to the floppy disk drive. The WD output can drive two
TTL loads.
Write Fault (WF): When low coincident with an active
(high) Write Gate (WG) output, causes th~ current Write
command to be terminated and sets bit 5 (Record Typel
Write Fault) of the Status Rsgister high. The WF input
should be made inactive (high) coincident with an
inactive (low) WG output. If not used, tie high.
Write Gate (WG): Active (high) whenever data is to be
written on the diskette. As a precaution to erroneous
writing, the first data byte must be loaded into the Data
Register (in response to a DRO output from the
INSl771-1) before the WG output can be activated.
0-78
Functional Pin Definitions (cont.)
Track Greater Than 43 (TG43): When high during a
Read or Write operation, informs the floppy disk drive
that the Read/Write head is positioned between tracks
44 and 76.
-Three·Phase Motors/Step·Direction Motors Control Lines
(PH1/STEP, PH2/DIRC, PH3): These three control lines
provide either of the following outputs: successive
three-phase pulses (active high PH3 signal and active
low PH1 and PH2 signals) over the lines for three·phase
stepping motors; or a level over the PH2/DI RC line
(high level for stepping in and low level for stepping out)
and 4 microsecond high-level pulses over the PH1/STEP
line to determine the direction and stepping rate for
step-direction motors. For direction control of threephase motors, the stepping sequence is 1-2-3-1 when
stepping in and 1-3-2 when stepping out. The particular
motor interface selected is determined by the hardwiring
of the 3PM input. The PH1/STEP output is made active
low after a master reset.
INPUT/OUTPUT SIGNALS
Data Access Lines (DAUBus: This TRI-STATE bus
comprises eight inverted input/output lines (DAlODAl7). The bus provides bidirectional communications
between the CPU and the INSl771-1. Data, control
words and status information are transferred via the
DAl Bus.
Pin Configuration
v"
WE
39
liE
38
37
36
os
AD
Al
CAL 0
lfAIl
OAl2
OAl3
iJAi4
Head load (HlD): High-level output that controls the
loading of the Read/Write head against the recording
medium (diskette). A Read or Write operation does not
occur until a high-level H l T input is sampled by the
INSl771-1. The HlD becomes active at the beginning of
a Read, Write (E flag is set high) or Verify operation, or
a Seek or Step Operation with the H flag set high; it
remains active until the third index pulse following the
last operation that used the head.
DAl5
DAl6
iTIi:I1
PHl/STEP
PH2/01RC
PH3
3PM
MR
Vss
10
11
11
13
INSl771·1
14
15
16
17
18
19
,.
3'
3.
33
31
31
30
19
18
11
16
15
14
13
21
11
VOO
INTRO
ORQ
DINT
WPRT
iP
TROD
WF
READY
wo
WG
TG43
HLO
FDDAlA
rOClK
XTns
eLK
HLT
TEST
vee
INS1771-1 Commands
The INSl771-1 accepts and executes the eleven commands listed and summarized in table 1. Flags associated
with these commands are summarized in table 2. With
the exception of the Force Interrupt command, a
command word should be loaded into the internal
Command Register only when bit 0 (Busy) of the Status
Register is inactive (low). Whenever a command is being
executed, the Busy status bit is set high. When a com·
mand is completed or an error condition exists, an
interrupt is generated and the Busy status bit is reset
low. The Status Register indicates whether a completed
command encountered an error or was fault free.
The Type I Commands contain a head load (h) flag
(bit 3) that determines whether or not the head is to be
loaded at the beginning of the command. If h = 1, the
head is loaded at thebeginning of the command (HlD
output made active high). If h = 0, the HlD output is
made inactive low. Once the head is loaded (HlD is
active), the head will remain engaged until the INS 1771-1
receives a command that specifically disengages the head.
If the INSl771-1 does not receive any commands after
two revolutions of the disk, the head will be disengaged
(HlD made inactive). The Head load Timing (HlT)
input is only sampled after a 10 millisecond delay, when
actual reading or writing on the diskette is to occur.
Note that a verification, described below, requires
reading off the diskette.
As indicated in table 1, the eleven commands accepted
and executed by the INSl771-1 are divided into four
types. The following paragraphs describe the eleven
commands under these four divisions.
The Type I Commands also contain a verification (V)
flag (bit 2) that determines whether or not verification is
to take place on the last track. If V = 0, no verification is
performed. If V = 1, a verification is performed.
TYPE I COMMANDS
Type I Commands are basically head positIOning commands and include the Restore, Seek, Step, Step-In, and
Step-Out commands. Each of the Type I Commands
contains a rate (rlro) field (bits 0 and 1) that determines
the stepping motor rate as defined in the table below:
During verification, the head is loaded (H lD is active)
and after an -internal 10 millisecond delay, the HL T
input is sampled. When the HlT input is active (high),
r1
ro
elK = 2MHz
TEST = 1
elK = 1 MHz
TEST = 1
12 ms
0
0
6 ms
0
1
6 ms
12 ms
1
0
10 ms
20 ms
1
20 ms
40 ms
1
I
0-79
elK = 2MHz
TEST= O.
elK = 1 MHz
TEST =0
J
J
-400",
-.00",
Table 1. Commands Summary
-Type
COInn'iand
.' '-\~
(
-C-Res_tore
I
,II
Bits
7
6
5-
4'
3
2
0
0
h
V
Seek
0, 0
,0 0
Step
0
Step In
0
Step Out
0
0
Read Command
0
II \
Write Command
0
III
Read Address
III
Read Track
III
Write, Track
IV
Fo~ce'lnterruPt
0
ro
h
V
'1
q
V
rJ
ro
0
u h
u, h
V
'1
ro
:1
u
h
V
'1
0
in
b
E
b
ro
0
al
0
ao
0
,
0
'-
0
ro
m
b
E
0
0
E
0
0
E'
0
0
E
0
0
13 12
11
10
0
Table 2. Command Flags Summary
! '
h = Head Load flag (bit 3 of Type I)
b = Block Length flag (bit 3 of Type II) ,
h = 1, Load head at beginning
h = 0, Do not load head at beginning
b = ,', IBM format (128 to 1024 bytes)
b = 0, Non·IBM format (16 to 4096 bytes)
V = Verify flag (bit 2 of Type I)
E = Enable HLD & 10ms delay (bit 2 of Type II)
V = 1, Verify on last track
V = 0, No verify
E = 1, Enable HLD, HLT'& 10ms delay
E =0, Head is assumed engaged & no 10 ms delay
'1 ro = Stepping Motor Rate (bits 1 70 of Type I) ,
fi'ro = 00, 6 ms'between
'1 ro = 01, 6 ms between
r,ro = 10, 10ms between
,r,l ro = 11, 20
between
ms
a,ao = Data Address Mark (bits 1 - 0 of Type II)
alao = 00, FB (Data Mark)
alao = 01, FA (Data Mark)
alao = 10, F9' (Data Mark)
alao = 11, F8(DataMark)
steps
steps
steps
steps
u = Update flag (bit 4 of Type I)
5 = Synchronize flag (bit 0 of T,ype III)
s= 0, Synchronize to AM
s= 1, Do not synchronize to AM
u = 1, Update Track Register
u = 0, No update
m = 'Multiple Record flag (bit 4 of Type-II)
In = Interrupt,Condition flags (bits 3 - 0 of Type IV)
m = 0, Single Record
m = l~Multiple Records
10 =
11 =
12 =
13 =
1, Not Ready to Ready Transition
1, Ready to Not Ready Transition
1, Index Pulse
Immediately
INS1771-1 Commands (cont.)
the first encountered ID field is read off the diskette.
The track address of the 10 field is then compared to the
Track Register. If there is a match and a valid ID CRe.
the verification is complete, an interrupt is generated,:
and the Busy status bit'isreset. Inhere is not a match
and II valid ID CRC, an interrupt is generated, the Seek
Error status .bit (bit 4) is set high, and t~e Busy status
bit is reset low. If there is not a: valid CRC, the CRC
Error status bit (bit 3) is set high; and the next encoun-
tered 10 field is read off the diskette for verification. If
an 10 field with a valid CRC cannot be found after four
revolutions' 'of the diskette, the INS 1771-1 term inates
the operation and sends an interrupt (I NTRQ) Signal to
,the CPU.,
0-80
The Step, Step-In and Step-Out commands contain an
update (u) flag (bit 4)_ When u = 1, the Track Register
Is updated by one for each step. When u = 0, the Track
Register is not uj:ldated.
INS1771-1 Commands (cont.)
Restore (Seek Track 0): Upon receipt of this command,
the Track 00 (TROO) input is sampled. If TROO is active
low (indicating the Read/Write head is positioned over
track 0), the Track Register is loaded with zeros and an
interrupt is generated. If TROO is not active low, stepping
pulses at a rate specified by the rlro field (bits 0 and 1)
are issued until the TROO input is active low. At this
time, the Track Register is loaded with zeros and an
interrupt is generated. If the TROO input does not go
active low after 255 stepping pulses, the INSl771-1
gives up and interrupts with the Seek Error status bit
set. Note that the Restore command is executed when
the MR input goes from an active (low) to an inactive
(high) state. A verification operation takes place if the
V flag (bit 2) is set. The setting of the h flag (bit 3)
allows the head to be loaded at the start of the command.
allows the head to be loaded at the start of the command. An interrupt is generated at the completion of the
command.
Step-Out: Upon receipt of this command, the INSl771-1
issues one stepping pulse in ttie direction towards track
O. If the u flag (bit 4) is set, the Track Register is decremented by one. After a delay determined by -the rFO
field (bits 0 and 1), a verification takes place if the V
flag (bit 21 is on. The setting of the h flag (bit 3) allows
the head to be loaded at the start of the command. An
interrupt is generated at the completion of the command.
TYPE II COMMANDS
The Type II Commands include the Read sector(s) and
Write sector(s) commands. Prior to loading the Type II
Commands into the Command Register, the computer
must load the Sector Register with the desired sector
number. Upon receipt of the Type II Commands, the
Busy status bit is set. If the E flag (bit 2) = 1 (this is the
normal casel, HLD is made active and HLT is sampled
after an internal 10 millisecond delay. If the E flag = 0,
the head is assumed engaged and there is no' internal
10 millisecond delay.
Seek: This command assumes that the Track Register
contains the track number of the current position of the
Read/Write head and that the Data Register contains the
desired track number. The INSl771-1 will update the
Track Register and issue stepping pulses in the appropriate direction until the contents of the Track Register
are equal to the contents of the Data Register. A verification operation takes place if the V flag (bit 2) is set.
The setting of the h flag (bit 3) allows the head to be
loaded at the start of the command. An interrupt is
generated at the completion of the command.
When an ID field (see figure 1) is located on the diskette,
the INSl771-1 compares the Track Number of the ID
field with the Track Register. If there is not a match, the
next encountered I D field is read and a comparison is
made. If there is a match, the sector number of the ID
field is then compared with the Sector Register. If there
is not a match, the next encountered ID field is read and
a comparison is made. If there is a match, the CRC field
is read. (The polynomial for the eRC is G (x) = x 16 +
x 12 + x 5 + 1. The CRe includes all the information
starting with the address mark and up to the CRC
characters.) If there is a CRC error, the eRC Error status
bit is set and the next I D field is read off the diskette
and comparisons are made. If the eRC is correct, the
data field is located and will be either written or read,
depending upon command. The INSl771-1 must find an
ID field with a valid track number, sector number, and
CRe within four revolutions of the diskette; otherwise,
the Record Not Found status bit (bit 41 is set and the
command is terminated with an interrupt.
Step: Upon receipt of this command, the INSl771-1
issues one stepping pulse to the floppy disk drive. The
stepping motor direction is the same as in the previous
step command. After a delay determined by the f1 ro
field (bits 0 and 1), a verification takes place if the V
flag (bit 2) is set. If the u flag (bit 4) is set, the Track
Register is updated. The setting of the h flag (bit 3)
allows the head to be loaded at the start of the command. An interrupt is generated at the completion of the
command.
Step-In: Upon receipt of this command, the INSl771-1
issues one stepping pulse in the direction towards track
76. If the u flag (bit 4) is set, the Track Register is
decremented by one. After a delay determined by the
rl ro field (bits 0 and 1), a verification takes place if the
V flag (bit 21 is set. The setting of the h flag (bit 3)
f . o - - - - - - - - - - - I D FIELD
IDAM
'" 10 ADDRESS MARK; DATA'" (FE), elK == (t7)
DATA AM'" DATA ADDRESS MARk; DATA'" (Fa, f9, FA, OR FB). eLK = (t1)
Figura 1. IBM 3740 10 Field and O.ta Field Formats
0-81
INS1771-1 Commands (cont.)
provided that the CPU has previously read the Data
Register, If one or more characters are lost, the Lost
Data status bit is set. This sequence continues until, the
data field has been inputted to the computer. If there is
a CRC error in the data field, the CRC Error status bit is
set, and the command is terminated (even if it is a
multiple record command). At the end of the operation,
the type of Data Address Mark encountered in the data
field is recorded in the Status Register (bits 5 and 6) as
shown below:
Each of the Type II Commands contains a b flag (bit 3),
which in conjunction ,with the sector length field
contents of the ID, determines the length (number of
characters) of the data field. For IBM 3740 compatibility,
the b flag (bit 31 should equal 1. The numbers of bytes
in the data field (sector) is then 128 x 2 n where n = 0,
l,2,or3.
For b = 1:
Sector Length
Field (hex)
Number of Bytes
in Sector (decimal)
00
01
02
03
128
256
512
1024
01
02
03
16
32
48
64
04
FB
FA
F9
F8
a
•
•
FF
00
Data AM (hex)
o
Write Command: Upon receipt of this command, the
Read/Write head is loaded, (HLD active) and the Busy
status bi,t is set. When an ID field is encountered that has
th'e correct track number, correct sector number, and
correct CRC, a ORO output is generated, The INSl771-1
counts off 11 bytes from the CRC field and the Write
Gate (WG) output is made active if the ORO is serviced
(i,e., the Data Register has been loaded by the computer).
If ORO has not been serviced, the command is terminated and the Lost Data status bit is set. If the 0 R has
been serviced, the WG is made active and six bytes of all
Zero levels are then written on the diskette. At this
time, the Data Address Mark is then written on the
diskette, as determined by the alao field (bits a and 1)
of the ,command as shown below:
For b = 0:'
Number of Bytes
in Sector (decimal)
Status Bit 6
o
o
a
When the b flag (bit 3) equals zero, the sector length
field (n) multiplied by 16 determines the number of
bytes in the sector or data field as shown below:
Sector Length
Field (hex)
Status Bit 5
4080
4096
~
0
0
Q
Each of'the Type II Commands also contains an m flag
(bit 4) that determines whether multiple records (sectors)
are to be read or written, depending lipan the command.
If m = 0, asingle sector is read or written and ~n inter:
rupt is generated at the completion of the command. If
m = 1, mUltiple records are read or written with. the
Sector Register' internally updated so that an address
verification can occur on the next record, The INSl771-1
continues to read or write multiple records and update
the Sector Register until the Sector Register exceeds the
number of sectors on the track or until the Force
Interrupt command is loaded into the Command Register.
When either of these occurs, the command is terminated
and an interrupt is generated.
0
Data Mark (hex)
Clock Mark (hex)
FB
FA
F9
F8
C7
C7
C7
C7
The INSl771-1 then writes the data field by generating
ORO outputs to the, computer. If the ORO is not
serviced in time, the Lost Data status bit is set and a
byte of zeros is written on the diskette. The command is
not terminated. After the last data byte has been written
on the diskette, the two-byte CRC is computed internally
and written on the diskette followed by one byte of all
One levels, WG is then made inactive.
TYPE III COMMANDS
Read Command: Upon receipt of this command, the
Read/Write head is loaded and the Busy status bit is set,
Then, when an 10 field is encountered that has the
correct track number, correct sector number, and.
correct CRC, the data field is inputted to the computer.
The Data Address Mark of the data field must be found
within 28 bytes of the correct 10 field. ·If not, the
Record Not Found status bit is set and the operation is
terminated, When the first character or byte of the data
field has been shifted through the Data Shift Register,
it is transferred to the Data Register and a Data Request
(ORO) output is generated, When the next byte is
loaded into the Data Shift Register, it is transferred to
the Data Register and another ORO output is generated,
Read Address: Upon receipt of th is command, the head
is loaded and the Busy status bit is set. The next encountered 10 f.ield is then read in off the diskette, and the
six data bytes of the 10 field are assembled and transferred to the Data Register, and a ORO output is generated for each byte. (The six bytes of the 10 field are
shown in figure 1,)
Although the CRC characters are inputted to the computer, the INSl771-1 checks for validity and the CRC
Error status bit is set if there is a CRG error. The Sector
Address of the 10 field is written into the Sector
Register. At the end of the operation, an interrupt is
generated anti the Busy status bit is reseL
D-82
INS1771-1 Commands (cont.)
TYPE IV COMMANDS
Read Track: Upon receipt of this command, the head is
loaded and the Busy status bit is set. Reading starts with
the leading edge of the first encountered index mark and
continues until the next index pulse. As each byte is
assembled, it is transferred to the Data Register and the
Data Request (DRO) output is generated for each byte.
No CRC checking is performed. Gaps are included in the
input data stream. If the flag (bit 0) of the command
is a low, the accumulation of bytes js synchronized to
each Address Mark encountered. Upon completion of
the command, the interrupt is activated.
Force Interrupt: This command carl 'be loaded into the
Command Register at any time. If there is a current
command under execution (Busy status bit is set), the
command is termi(lated and an interrupt is generated
when the condition specified in the 10 through 13 field
(bits 0 through 3) is detected. More than one condition
may be specified. The interrupt conditions are indicated
below:
s
10 = Not Ready·to·Ready Transition
11 = Ready-to-Ready Transition
12 = Every I ndex Pulse
13 = Interrupt Occurs Immediately
The INS1771·1 handles single density frequency modu·
lated (FM) data. Each data cell is defined by clock
pulses. A pulse recorded between clock pulses indicates
the presence of a logic 1 bit; the absence of this pulse
is interpreted as a logic 0 bit. The Address Marks for
Index, I D, and Data are identified by a particular pattern
not repeated in the remainder of the ID field or Data
field. This is accomplished by reading patterns that are
recorded with missing clock bits (logic 0) as shown
below:
NOTE
If 10 through 13 = 0, no interrupt is generated;
however, the current command is terminated and
the Busy status bit is reset.
INS1771-1 Status Register
An 8-bit register is provided in the INS1771-1 to hold
device status information. This Status information varies
according to the type of command executed as shown
in table 3. The contents of the Status Register, which
can be read into the DAL Bus by a Read operation,
are described below.
For initial ization:
Write 2 CRC Characters
Data
1 1 1 1 0 1 1 1 = F7
Clock 1 1 1 1 1 1 1 1 = FF
Index Address Mark
Data
1 1 1 1 1 1 0 0 = FC
Clock 1 1 0 1 0 '1 1 1 = D7
I D Address Mark
Data
1 1 1 1 1 1 1 0 = FE
Clock 1 1 0 0 0 1 1 1 = C7
Data Address Mark
Data
1 1 1 1 1 0 1 1
Clock 1 1 0 0 0 1 1 1
Deleted
Data Address Mark
Data
Clock 1 '1 0 0 0 1 1 1 = C7
Spare
Data
Clock
Bit 0: When high (set), indicates that a command is
under execution. When low (reset), indicates that no
command is under execution.
'
= F9 - F B
= C7
1 1 1 1 1 0 0 0 = F8
Bit 1: For Type I Commands, this bit is the comple·
ment of the Index Pulse (iP) input. When set, it indicates
that an inde« mark has been detected on the diskette.
1 1 1 1 1 1 0 1 = FD
(user designated)
For Types II and III Commands, this bit is a copy of the
Data Request (DRO) output. When set, it indicates that
the Data Register is full during a Read operation or that
the Data Register is empty during a Write operation. Bit
1 is reset to zero when updated.
These patterns are used as synchronization codes by the
INS 1771·1 when reading data and are recorded by the
formatting command (Write Track) when the INS 1771·1
is presented with data F7 through FE.
Bit 2: For Type I Commands, this bit is the complement
of the Track 00 (TROO) input. When set, it indicates
that the Read/Writ,e head is positioned over track O.
Write Track: Upon receipt of this command, the head is
loaded and the Busy status bit is set. Writing starts with
the leading edge of the first encountered index pulse
and continues until the next index pulse,at which time
the interrupt is activated. The Data Request output is
activated immediately upon receiving the command and
writing does not start until after the first byte has been
loaded into' the Data Register. If the, Data Register has
not been loaded by the second index pulse, the operation
is terminated. This sets the Not Busy and Lost Data
status bits, and activates the interrupt. If a byte is not
present in the Data Register when needed, a byte of
zeros is substituted. Address Marks and CRC characters
are written o'n the diskette by detecting certain data
byte patterns in the outgoi ng data stream as shown
above. The CRC generator is initialized to all Ones when
any data byte from F8 to FE is about to be transferred
from the Data·Register to the Data Shift Register.
For Types II and III Commands, this bit is set to indicate
that the computer did not respond to the DR 0 output
from the INS1771-1 in one byte time. Bit 2 is reset to
zero when updated.
Bit 3: For Type I Commands, this bit is set when one or
more CRC errors were encountered on an unsuccessful
Track Verification operation. Bit 3 is reset to zero when
updated.
For Type II and III Commands, bit 3 is set when an
error is found in one or more I D fields, while bit 4 is set.
Bit 3 is reset low when updated.
Bit 4: For Type'l Commands, this bit is set to indicate
that the desired track was not verified. Bit 4 is reset
low when updated.
For Type II and III Commands, bit 4 is set to indicate
th,at the desired track and sector were not found. Bit 4 is
reset low when updated._
The Write Track command does not execute if the D INT
input is grounded. Instead, the Write Protect statUs bit
is set and the interrupt is activated. One F7 pattern in
the Data Register generates 2 CRC characters.
Bit 5: For Type I Commands, this bit is set to indicate
that the ReadlWrite head is loaded and engaged. Bit 5
D-83
'1"
INS1771-1 Commands (cont.)
is the.logicill AND of the H~ad Load (H LD) output
and the Head Load Timing (HL T) input,
For Type II and III Commands,. bit 6 indicates the
following: the MSB of the record.type code from the
data field address mark during execution of a Read
Command; and a write fault during execution of a Write
or Write Track command. Bit 6 is reset low when up·
dated.
'
.
For Type II and· II I CO(Ylmands, bit 5 indicates the
'following: the LSB of the record'type code· from the
data .field address' mark durirlg. executiOn of a Read
Command; and a write' fault during execution of a Write
or Write Track Command. Bit 5 is reset low when
updated.
Bit 7: When set, indicates that the floppy disk drive is
not ready. Wh~n reset, indicates that the drive is ready.
Bit 7 is the complement of the Ready input and is
logically ORed with the Master Reset (MR) input. The
Types II and III Commands are I"\ot executed unless the
floppy disk drive is ready.
Bit 6: For Type I Commands, this bit is the complement
of the Write Protect (WRPT) input. When set, i.t indicates
that the write protect is activated.
Table 3. Status Register Summary
Commands
Bit
All Type I
Commands
Read
Adqress
- Not Ready
Read
Read
Track
Write
Track
Write
Not Ready
Not Ready
Not Ready
Not Ready
Record Type
0
Write Protect
Write Protect
0
Record Type
0
Write Fault
Write Fault
10 Not Found
Record Not Found
0
Record Not Found
0
CRC Error
0
CRC Error
0
Lost Data
Lost Data
Lost Data
Lost Data
ORO
ORO
ORO
ORO
ORO
Busy
Busy
Busy
Busy
Busy
S7
Not Ready
S.6
Write Protect
S5
Head Engaged
S4
Seek Error
53
CRC Error
CRG Error
52
Track 0
Lost Data
Sl
Index
SO
Busy
0
Programming Examples
Some examples of the software <;ontrol of the INSl771·1
·are shown in flowchart form. The first example (figure 2)
shows the writing of information onto a particular track
and sector. TI~e second example (figure 3) shows acces·
sing of information from successive sectors. The third
example (figure, 4) shows how information may be
sought by using Track 00 as a table ofcont,ents.
When t'ransfer of data with the INSl771·1 is required
by the host processor, the device address is decoded and
CS is made low. The least significant address bits A 1 and
AD, combined with the signals FiE during a Read opera·
tion or WE during a Write operation, are interpreted a,s
selecting the following registers:
Al
AD
Read (RE)
Write (WE)
INS17.71-1 Operation
0
D
Thefollowing.'describes the operation of the INSl771·1.
Use the block diagram on page 5, as necessary, to follow
these descriptions.
D
Status Register
Track Register
Sector Register
Data Register
Command Register
Track Register
Sector Register
Data Register
INSl771-1 PROCESSOR ,INTERFACE
All commands, status and data are transferred over the
TRI-STATE bidirectional OAt. (Data Access Lines) Bus.
The B lines of the DAL Bus (DALD -DAL7) present an
open circuit to the com man processor peripheral bus
until activated by the low·level CS (Chip Select) signal.
An active CS combined with a low-level RE(Read
Enable) sets the DAL Bus into the 'transmitter mode,
while. the CS combined with a low·level WE (Write
Enable) sets the DAL Bus in the receive.r mode.
D
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the INS1771·1
and the processor, the Data Request (ORO) output is
used in Data Transfer control. This signal also appears as
status bit 1 during Read and Write operations.
On Disk Read operations, the Data Request (ORO)
output is activated (set hi.gh) when an assembled serial
input byte is transferred in parallel to the Data Register.
Th,is bit is cleared when the Data.Register is read by the
processor. If the Data Register is read after one or more
D-84
INS1771-1 Programming Examples (cont.)
TRACK = A3
ADDR = 01
SEND DESIRED
TRACK NO. TO
TRACK REG =
WE =0
10100011
SEND DESIRED
SECTOR NO. TO
SECTOR REG =
SECTOR = 16
ADDR = 10
WE = 0
0001 0110
HEAD LOAD ACTIVATED
VERIFY REQUESTS
6m, STEP RATE
MDR = 00
WE=O
ADDR = 00
RE = 0
REPEAT SEEK
OPERATION OR
DO DIAGNOSTIC
TESTS
YES
HEAD IS ASSUMED LOADED FROM
SEEK OPERATION. WRITE SINGLE
SECTOR,IBM SECTOR FORMAT
(128 BYTES).
DATA ADDRESS MARK = FB
ADDR = ~O, WE =0
ORO
READ THE
BYTE FROM
MEMORY AND
INCREMENT ADDR
READ STATUS
REGISTER
AODR =11
WE = 0
PERFORM ERROR
DIAGNOSTICS
ORO
PERFORM ERROR
DIAGNOSTICS
YES
•.
,Figure 2. Writing Data
0-85
fNS1771-1 Programming Examples (cont.)
,i';,'
ASSUM!S:
- TRACK,IS ~I}cATED
- DESIRED SECTOR IS LOADED
READ STATUS
REGISTER &
MASK 00111000
ENABLE HEAD LOAD AND
MULTIPLE SECTORS
ENABLE IBM FORMAT
(128 BYTES/SeCTOR)
INTRQ
",'
:,. J.\
AD DR = 11.liE = 0
STORE IN
MEMORY AND
INCR ADDR
NO
NOTE:
NO. OF BYTES TRANSFERRED
SHOULD ENCOMPASS TOTAL
SECTORS TO ALLOW VALID
CRC CHECKS.
YES
READ STATUS
REG & MASK
FOR ERRORS
= 0011 0000
YES
REREA'P OR
PERFORM ERROR ....----_~
DIAGNOSTICS
ADDR =00,
iiE = 0
NO
SEND, FORCE
INTERRUPT CMD
TO CMD REG
=,11010000
ADDR = 00
WE= 0
CONTINUE
"
Figure 3. Ree!ling Successive Sectors of Data
0·86
INS1771-1 Programming Examples (cont.)
SEND RESTORE
CMD TO CMD REG
= 0000 1101
ADDR = 00, WE = 0
ENABLE HEAD LOAD AND VERIFY
ENABLE 6 ms STEP RATE
INTR!l
READ STATUS
REG AND MASK
= 0001 1000
DO DIAGNOSTIC
SUCH AS READ
ADDRESS CMD
YES
ADDR
= 00, m: =0
NO
COMPARE LABEL
AND DERIVE
TRACK AND SECTOR
LOCATION
PERFORM LOCATE
DATA AND
READIN
ASSEMBLED DATA
m: = 0
COMPLETE
Figure 4. Using Track 00 as Table of Contents
characters are lost, by having new data transferred into
the register prior to processor readout, the Lost Data bit
is set in the Status Register. The Read operation con·
tinues until the end of sector is reached.
The Lost Data bit and certain other bits in the Status
Register will activate the Interrupt Request (lNTRO),
output. The interrupt line is also activated with normal
completion or abnormal termination of all controller
operations. The INTRO signal remains active until reset
by reading the Status Register to the processor or by the
loading of the Command Register. In addition, the
I NTRO output is generated if a Force Interrupt command condition is met.
On Disk Write operations, the Data Request output 'is
activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data byte,
It is reset when the Data Register is loaded with new
data by the processor. If new data is not loaded at the
time the next serial byte is required by the floppy'
disk drive, a byte of zeroes is written on the diskette and
the Lost Data bit is set in the Status Register.
D-87
I.ICI
INS1771-1 FLOPPY DISK DRIVE INTERFACE
The INSI771-1 floppy disk drive interface consists of
head positioning controls, write gate controls, and data
transfers. A 2.0 MHz ± 1% square wave clock is required
at the ClK input for internal control timing. (A 1.0 MHz
clock is required for a miniature floppy disk.)
Head Positioning
Four commands cause positioning of the ReadlWrite
head (see INSI771-1 Commands section). The period of
each positioning step is specified by the r field in bits 1
and 0 of the command word. After the last directional
step, an additional 10 milliseconds of head settling time
takes place. The four programmable stepping rates
(rl ro) are tabulated under the Type I Commands description.
The '1 ro rates can be applied to a three-phase motor or
a step-direction motor through the device interface.
When the 3PM input is connected to ground the device
operates with a three· phase motor control interface,
with one active signal per phase on the three output
signals (PHI, PH2 and PH3). The stepping sequence
is 1·2-3-1 when stepping in and 1-3-2-1 when stepping
out. Phase 1 is active low after Master Reset.
The Step-Direction Motor Control interface is activated
by leaving input 3PM open or connecting it to +5 Volts,
The phase 1 pin (PH I) becomes a step pulse of 4 microseconds width. The phase 2 pin (PH2) becomes a direction control, with a high voltage on this pin indicating
a Step In, and a low voltage indicating a Step Out. The
Direction output is valid a minimum of 24 microseconds
prior to the activation of the step pulse.
When a Seek, Step or Restore command is executed,
an optional· verification of Read/Writehead position can
be performed by setting bit 2 in the command word to
a logic 1. The verification operation begins at the end of
the 10 millisecond settling time after the head is loaded
against the medium. The track number from the first
encountered I D Field is compared against the contents
of the Track Register. If the track numbers compare
and the ID Field Cyclic Redundancy Check (CRC) is
correct, the verify operation is complete. If track comparison is not made but the CRC checks, an interrupt is
generated, the Seek Error status bit (bit 4) is set, and the
Busy status bit is preset. If there is no track comparison
nor a valid CRC, a step is made in the same direction as
specified and the verify operation is repeated. The
additional stepping can be repeated twice to account for
two defective tracks. If no verification is received at
this pOint, the Seek Error (bit 4) is set in the Status
Register.
The Head load (HDL) output controls the movement
of the ReadlWrite head against the diskette. for data
recording or retrieval: It is activated at the beginning of
a Read, Write(E flag on} or Verify operation, ora Seek
or Step operation with the tiead loadbit (h) a logic high; it
remains activated until the third index pulse following
the last operation which uses the Read/Write head.
Reading or Writing does not occur until a minimum of
10 milliseconds after the HDl signal is made active. If
executing the Type II Commands with tne E flag off,
there is no 10 millisecond delay and the head is assumed
to be engaged. The delay is determined by sampling of
the Head load Timing (HL T) input every 10 milliseconds. A low logic state input,· generated from the
Head Load output transition and delayed externally,
identifies engagement of the head against the diskette.
In the Seek and Step commands, the head is loaded at
ttle start of the command execution when the h bit is a
logic 1. In a verify command, the head is loaded before
stepping to the destination track on the diskette whenever the h bit is a logic O.
Disk Read Operation
The 2.0 MHz external clock provided to the device is
internally divided by 4 to form the 500 kHz clock rate
for data transfer. When reading data from a diskette, this
divider is synchronized totransitions of the Read Data
(FDDATA) input. When a transition does not occur on
the 500 kHz clock active state, the .clock divider circuit
injects a clock to maintain a continuous 500 kHz data
clock. The 500 kHz data clock is further divided by 2
internally to separate the clock and information bits.
The divider is phased to the information by the detection of the address mark.
In the internal data read and separation mode, the Read
Data input toggles from one state to the opposite state
for each logic 1 bit of clock or information. This signal
can be derived from the amplified, differentiated, and
sliced Read Head signal, or by the output of a flip-flop
toggling on the Read Data pulses. This input is sampled
by the 2 MHz clock to detect transitions.
The ch ip can also operate on externally separated data,
as supplied by methods such as phase-lock loop, oneshots, or variable frequency oscillators. This is accomplished by grounding the External Data Separator
(XTDS) input. When the Read Data input makes a highto-low transition, the information input to the FDDATA
line is clocked into the Data Shift Register. The assembled 8-bit data from the Data Shift Register are then
transferred to the Data Register.
The normal sector length for Read or Write operations
with the IBM 3740 format is 128 bytes. This fprmat or
binary multiplex of 128 bytes will be adopted by setting
a logic 1 in bit 3 of the Read Track and Write Track
commands. Additionally, a variable sector length feature
is provided which allows an indicator recorded in the ID
Field to control the length of the sector. Variable sector
lengths can be read or written in Read or Write commands respectively by setting a logic 0 in bit 0 of the
command word. The sector length indicator specifies the
number of 16'byte groups, or 16 x N, where N is equal
to 1 to 256 groups. An indicator of all zeros is interpreted as 256 sixteen-byte groups.
Disk Write Operation
After data is loaded. from the processor into the Data
Register, and is transferred to the Data Shift Register,
data will be shifted serially through the Write Data (WD)
output. Interlaced with each bit of data isa positive
clock pulse of 0.5 microsecond (Juration. This signal may
be used to externally toggle a flip-flop to control the
direction of write current flow.
0-88
INS1771-1 FLOPPY DISK DRIVE INTERFACE (cont.)
When writing is to take place on the diskette, the Write
Gate (WG) output is activated, allowing current to flow
into the ReadIWrite head. As a precaution to erroneous
writing, the first data byte must be loaded into the Data
Register in response to a Data Request from the
INSl771-1 before the Write Gate signal can be activated.
detect write current flow when the Write Gate (WG) is
activated. On detection of this fault, the INS1771-1
terminates the current command and sets the Write
Fault bit (bit 5) of the Status Register. The Write Fault
(WF) input should be made inactive when the Write
Gate (WG) output becomes inactive.
Writing is inhibited when the Write Protect (WPRT)
input is a logic 0, in which case any Write command is
immediately terminated,. an interrupt is generated, and
the Write Protect status bit is set. The Write Fault (WF)
input, when activated, signifies a writing fault condition
detected in disk drive electronics such as failure to
Whenever a Read or Write command is received, the
INSl771-1 samples the Ready input. If this input is
logic 0, the command is not executed and an interrupt is
generated. The Seek or Step commands are performed
regardless of the state of the Ready input.
0-89
Physical Dimensions
2.020
15i.J081 -----..:.O.-52-0-----------~J·
MAX
l--~ (13.20B)
!
snUARE
:-------1
I
21
1
0.032
~~
0.590
RAD
(14.986)
~~~~;;;n;;n;orr,;r'_.lX
"i'
,....
.....
.....
Ceramic Dual-In-line Package (0)
Order Number INSl771D-l
NS Package Number J40A
lii
z
-
--1
0.062
(1.575)
0.550 '_0.005
(13.970 '0.121)
RAD
PIN NO.1 INOENT-........
~~~~~J
~.
Plastic Dual-In-Line Package IN)
Order Number INSl771 N-l
NS Package Number N40A
National Semiconductor
CD{poratlon
2900 Semiconductor Drive
Santa Clara. California 95051
Tel.: {40B) 737-5000
TWX: (910) 339-9240
National Semiconductor GmbH
8000 MUnchen 21
Eisenheimerstrasse 61/2
West Germany
Tel: 089/9 15027
Telex: 05-22772
NS International Inc., Japan
Miyake Building
1-9 Yotsuya, ShinJuku-ku 160
TOkyo, Japan
Tel.: (03) 355-3711
TWX: 232-2015 NSCJ-J
National does not assume any responsibility for use 01 any circuitry described; no circuit
National Semiconductor
(Hong Kong) ltd.
8th Floor,
Cheung Kong Eleclronic Bldg
4 Hing Yip Street
Kwun Tong
Kowloon. Hong Kong
Tel.: 3-411241-8
Telex: 73866 NSEHK HX
Cable: NATSEMI
patenl'D~n9b are
NS Electronits Do BrasU
NS Electronics Ply. Ltd.
Avda Bngadeiro Faria lima 844 Cnr. Stud Rd. & Min. Highway
11 Andar Conjunto 1104
Bayswater. Victoria 3153
Jardim Pal1lislano
Australia
Sao Paulo, Brasil
Tel.: 03-729-6333
Telex
Telex: 32096
1121008 CABINE SAO PAULO
implied, and National reserves the right, at any time without notice, to change said circuitry.
~National
Preliminary
~ Semiconductor
JULY 1978
General. Description
W
"tJ
c8
The contents of each counter may be read either
directly or through an auxiliary register. A direct
reading of the counter can be made whenever the
counter is inhibited from counting. A count value can
also be read without interfering with the counting
process. This is done by transferring the counter's
current value to an auxiliary register and then
reading that register. This counter-to-register
transfer can be executed without affecting the
normal count sequence.
The INS8253 is a programmable timer/counter device
contained in a standard, 24-pin dual-in-line package.
The chip, which is fabricated using N-channel silicon
gate technology, provides counting or time-out
services in a microcomputer system. The various
operating modes and other functional characteristics of thelNS8253 are programmed by the system
software.
The INS8253 provides three independent 16-bit down
counters, each of which is capable of count rates in
the range DC to 2MHz. Through software initialization, each counter can be made to operate in anyone
of six modes. The modulus and counting system
used are also specified by system software. The
operating characteristics of any individual counter
can be modified by the software at any time to meet
changing system requirements.
Features
• 3 Individually Programmable 16-Bit Counters
• 6 Operating Modes
• DC to 2MHz Count Rates
• Individual Count Rate and Modulus for Each
Counter
The modulus of any given counter can be changed at
the program's discretion by loading a new value into
the counter. A counter load operation may be limited
to the counter's least significant byte or to its most
significant byte, or it may revise both halves of the
counter.
• Selectable Counting System (Binary or BCD) for
Each Counter
• TRI-STATE@ TTL Drive Capability for Bidirectional
Data Bus
• Single + 5 Volt Power Supply
Count sequences may be in either binary or BCD.
This choice is also individually specified for each
counter by the software.
• 24-Pin Dual-in-Line Package
• MICROBUSTM' Compatible
INS8253 MICROBUS Configuration
P""
INSBZ53
07-00
ClKO
07-00
Ail
WR
C~
Al
AD
GATED
OUTO
II-
r-
Ail
ClKl
I-
Wii
GATEl
cs
I-
OUTl
Al
AD
Lc
'A trademark of National Semiconductor Corporation.
0-91
r---
IGATEZ
IClKZ
OUTZ
© 1978 National Semiconductor Corp.
~
N
en
INS8253 Programmable Interval Timer
M
I
C
R
0
B
U
S
z-
r---
FROM
PERIPHERAL
CONTROL
lOGIC
0;
3
3
D)
C"
CD
-;.
3'
CD
::I
3
...
CD
Ab~olute
Maximum Ratings
AmbientTemperature Under Bias .............. 0 °C to + 70°C
Maximum Voltage to Any Input
with Respect to GND ........................ - 0.5V to + 7V
Storage Temperature .................... - 65°C to + 150°C
Power DIssipation .................................. 1 Watt
Note: Absolute maximum ratings indicate limits beyond which
permanent damage may occur. Continuous operation at these
limits is not intended and should be limited to those conditions
specified under DC Electrical Characteristics.
DC Electrical Characteristics
(TA = O°C to + 70°C; Vec = 5V ± 5%)
Symbol
Parameter
Max
Min
Input Low Voltage
-0.5
VIH
Input High Voltage
2.2
VOL
Output Low Voltage
VOH
Output High Voltage
IlL
Input Load Current
IOFL
Output Float Leakage
Icc
Vee Supply Current
VIL
Unit
0.8
V
Vee + O.5V
V
0.45
V
2.4
Test Conditions
Note 1
V
Note 2
±10
lAA
VIN
±10
lAA
VOUT = Vee to OV
140
mA
= Vee to OV
Note 1: INS8253, IOL = 1.BmA.
Note 2: INS8253,IOH = -150~A.
,
Capacitance
TA = 25°C; Vee = GND
= OV.
Symbol
Parameter
Max
Unit
CIN
Input Capacitance
10
pF
CliO
110 Capacitance
20
pF
Min
Test Conditions
Ic
= 1 MHz
Unmeasured pins returned to Vss
'-
0-92
AC Electrical Characteristics
= O·Cto +70·C;Vcc = 5.0V ± 5%;GND = OV
TA
Bus Parameters:
Parameter
Symbol
Max
Min
Unit
READ CYCLE
tAR
Address Stable Before READ
50
tRA
Address Hold Time for READ
5
ns
ns
tRR
READ Pulse Width
400
ns
tRo
Data Delay from READ (Note 2)
tOF
READ to Data Floating
25
300
ns
125
ns
Address Stable Before WRITE
50
ns
tWA
Address Hold Time for WRITE
30
ns
tww
WRITE Pulse Width
400
ns
tow
Dat'a Setup Time for WRITE
300
ns
two
Data Hold Time for WRITE
40
ns
tRY
Recovery Time Between WRITEs
1
ns
WRITE CYCLE
tAW
,Note 1: AC timings measured at VOH
Note 2: Test conditions: INS8253, CL
= 2.2V, VOL = O,8V,
= 100pF.
Input Waveforms for AC Tests
--I
AO'l'CS~
K
-....tWA
k--tAwT
)(
DATA BUS
I--
c=
'J
'
1- -C --1
tow
v.~
WR
tWD
WRITE TIMING
"'"'=1==
--I )<
--tAR------.1
DATA BUS
j-tRA
l·tRR-1
RD
HI·Z
~
VALID
Hl·Z
!
READ TIMING
2.4
2.2
0.8
> <
TEST
2.2
POINTS
,0.8
0.45
0·93
1-••
Clock and Gate Timing
Min
Max
Unit
tClK
Clock Period
380
DC
tpWH
High Pulse Width
.230
tpWl
low Pulse Width
150
tGW
Gate Width 'High
150
tGl
Gate Width low
100
tGS
Gate Setup Time to ClK t
100
tGH
Gate Hold Time After ClK t
50
Parameter
Symbol
, too
t ODG
Output Delay From ClK
(Note 1)
+
400
ns
ns
ns
ns
ns
ns
ns
ns
Output Delay From Gate
(Note 1)
+
300
ns
Note 1: Test conditions: INS8253, CL = 100pF.
~
elK
I '\ "-1
GATE G
tClK---
......-·PWl-
~.
I.
~"GW
\.
I-- I---'Gl~
.
OUTPUT 0
I
:x<_'00G--'-'"
0·94
--
-'GH
]\~I
...... '001
'
I--
r---\
/\
t~
'GH-
tGs---'"
){
I
INS8253 Functional Block .Diagram
07-00
DATA
-BUS
BUFFER
COUNTER
o
..,i!!!. CL K 0
..,!!ll. GATE 0
110)
OUTO
AO 119)
READ!
WRITE
LOGIC
COUNTER
1
~
Al 120)
~121)
t
CONTROL
WORD
REGISTER
COUNTER
2
VCC~
NOTE: APPLICABLE PINOUT NUMBERS
ARE INCLUDED WITHIN
PARENTHESES.
GNU.!.!:!..
Clock (CLKO-CLK2): Each counter has a separate
clock input that drives the counter.
INS8253 Functional Pin Description
The following describes the functions of all INS8253
input/output pins. Some of these descriptions refer
to internal circuits.
Gate (Gate O-Gate 2): Each counter is individually
controlled by a separate Gate input (1 = enable,O =
inhibit). In some modes, the positive edge of Gate is
used to initiate the counting process. Specific use of
Gate depends on the counter's operating mode.
Details are provided in the section entitled INS8253
Programming.
NOTE
In the following descriptions, a low represents
a logic (0 Volt, nominal) and a high represents
a logic 1 (+ 2.4 Volts, nominal).
°
INPUT SIGNALS
OUTPUT SIGNALS
Chip Select (CS): When low, the chip is selected. This
enables communication between the INS8253 and
the microprocessor.
Output (Out O-Out 2): Each counter has a single output
that indicates whether or not the counter has reached its
terminal count. Specific operation of this output
depends on the counter's mode_ Details are provided in
the section entitled INS8253 Programming.
Read (RD): When low, allows the microprocessor to
read contents of counter specified by AO, A1.
Write (WR): When low, writes control word into
control word register or loads new count value into
selected counter. Destination of data (control word
register or counter 0, 1 or 2) is specified by AO, A 1.-
INPUT/OUTPUT SIGNALS
Data (07 - DO) Bus: This bus, which comprises eight
TRI-STATE input/output lines, provides for bidirectional communication between the INS8253 and the
microprocessor. Control words and count value
bytes are transferred over these lines.
AO, A1: These inputs are used to select one of the
counters for reading or writing or to select the
control word register for writing. AO, A1 may be controlled via address bus lines.
0-95
WRITING CONTROL WORDS
INS8253 Pin Configuration
07
VCC
06
05
Wli
Rii
04
cs
03
Al
02
Au
01
CLK 2
Each counter's mode and counting system (binary or
BCD) are specified by an eight-bit control word. See
figure 1. An I/O write operation with AO, A1 = 11 will
load the control word into the control word register.
The control word contains four fields:
•
07, 06 (SC1, SCO) - This field specifies which
counter will be affected by the other control fields.
•
05, 04 (RL 1, RLO) - A bit pattern of 00 in this field
causes the contents of the selected counter to be
latched in an auxiliary register. The count value
can then be read without inhibiting the counter.
The other three bit patterns specify which byte(s)
of the selected counter will be affected by any
subsequent read/write operations addressed to
that counter.
•
03,02,01 (M2. M1, MO) - This field specifies the
mode 'Of operation for the selected counter.
•
DO (BCD) - This one-bit field specifies the
counting system to be used by the selected
counter.
OUT 2
00
CLK 0
GATE 2
OUT 0
CLK 1
GATE 1
GATE 0
GND
OUT 1
INS8253 Programming
This section provides basic information for programming the INS8253 and describes the methods for
reading counter status. Table 1 summarizes the
control signals needed to writecomrnand words and
new count values into the INS8253 and to read the
contents of individual counters.
Table 1. Bus Control lor INS8253 1/0 Operations
Output Operations
LOAD COUNTER 0
CS
WR
A1
AD
0
0
0
0
0
LOAD COUNTER 1
0
0
LOAD COUNTER 2
0
0
WRITE CONTROL WORD
0
0
RD
1
0
Input Operations
READ COUNTER 0
0
0
0
READ COUNTER 1
0
0
0
READ COUNTER 2
0
0
0
1
0
Any time after a counter is initialized by a control word,
its initial count value can be loaded. This is done by
means of a write operation addressed to that. counter.
Details are' given in the section entitled Loading Initial
Count Value.
Programming of the three counters can be executed in
any sequence, with only two requirements.
1. A counter must be issued a control word before it is
given an initial count value.
2. Read and write operations addressed to a counter
, must conform to the byte-selection rules specified by
the RL 1, RLO field in the control word. For example, if
the counter's RL 1, RLO bits = 10, subsequent counter
load operations addressed to that counter must be
intended for the most significant byte only.
, r - - - - - - - - - - B I T NUMBERS-----------..,\
SElECT,COUNTER
00 - COUNTER 0
01 - CO,UNTER 1
10 - COUNTER 2
11 - NOT VALIa
READ/LOAD
00 -LATCH COUNT'
01 - READ/LOAD
LSB ONL Y
10 - READ/LOAD
MSB ONL Y
11 - REAO/LOAD LSB
FIRST, MSB NEXT
MODE
000 - MODE 0
001 -MOOE 1
xlD - MODE 2
xli - MOOEJ
100 - MODE 4
101 - MODE 5
Figure 1. Control Word Format
0-16·BIT
BINARY
COUNT
1-4 OECADE
BCO COUNT
COUNTER MODE DESCRIPTIONS
Gate can be used to retrigger the counter. Each
positive transition of Gate causes the counter to
begin decrementing from the initial count value.
Figure 2 provides timing information for the six
INS8253 operating modes.
If a new initial count value is loaded during a
count cycle, the new value will not take effect until
the next rising transition of Gate. -
• Mode 0, Timed Interrupt - In this mode, OUT goes
low when the mode is set. The counter begins
_counting eLK cycles when the count is loaded.
OUT remains low until the terminal count is
reached, at which point it goes high and remains
high until either the mode or count is reloaded.
The gate input will inhibit the count when low.
If the counter is loaded with a new value during a
count cycle, counting will stop when the first byte
is loaded and will begin decrementing from the
new value after the second byte is loaded.
• Mode 2, Rate Generator - In this mode, OUT goes
low for one eLK cycle at the end of each count
sequence. The leading edge of each pulse occurs
at the start of the terminal eLK cycle. The counter
will repeat count sequences as long as Gate
remains high. Any positive transition of Gate will
start a new count sequence -at the initial count
value. This allows the counter to be synchronized
by Gate.
• Mode 1, Retriggerable One Shot - In this mode,
OUT goes low on the first eLK after a rising transi·
tion on Gate. OUT goes high again on-the terminal
count.
If a new initial count value is loaded during a
count sequence, the current sequence will run to
completion and the following sequence will then
start at the new initial count value.
MODE 0
MODE 3
CLOCK
CLOCK
I
Wl!"~
OUTPUT
~21i
OUTPUT INTERRUPT
tn = 41
OUTPUT (n::!i)
OUTPUT In'" 4)
~E:i~)~
OUTPUT INTERRUPT
A+8=m
MODE 1
MODE 4
CLOCK
CLOCK
W1i"~
TRIGGER
IGATE)
_ ______~4~3~2~1~O
- - - Ir - - - 4
2
J
(."':'4iI
OUTPUT
1
0
I
LOAD" ~r------------------
TRIGGER~
IGATE)
OUTPUT
---''i.-=-=__
4
3
2
~
OUTPUT
4
3
2
L.....Jr-----
GATE
1
~:'''':'''':''''j-------
4
OUTPUT
MODE 2
4
J
2
1
0
U--
MODE 5
CLOCK
CLOCK
'WAn ~
GATE
4321014)321013)210
OUTPUT
~
0(3)
OUTPUT (n =- 3)
RESET
IGATE)
J
2
1 Ot]) 2
1
0(3) 2
OUTPUT (n '" 4)
J 2
1 0
-~~~~LJr-------
1
~
~
GATE
OUTPUT (n = 4)
Figure 2. Mode Timing Waveforms
0·97
~
LJr----
'-ICI
• Mode 3, Square Wave Generator - In this mode,
the counter generates a square wave signal at the
OUT pin so long as Gale remains high. The period
of the square wave is equal to one count cycle. If
the initial count value is even, OUT will be high for
the first half of slich count sequence and low
during each second half. For an odd count, OUT. is
high for (N + 1)12 counts and low for (N - 1)/2
counts.
Read/load
Conditions
RL1 RLO
o
If a new initial count value is loaded during a
count sequence, the current sequence will run to
completion and the following sequence will then
start at the new initial count value.
Any positive transition of Gate will start a new
count sequence at the initial count value. This
allows the counter to be synchronized by Gate.
• Mode 4, Software Triggered Strobe - In this mode,
OUT is normally high and goes low for one CLK cycle
after the terminal count is reached. Counting is
enabled when Gate is high. Counting is initiated by
loading the modulus.
WR loads 07 - 00 into lSB of counter
selected by A 1, AO.·
o
WR loads 07-00 into MSB of counter
selected by A 1, AO.
1
First WR loads 07-00 into LSB of
counter selected by A1, AO. Next WR
loads 07-00 into counter's MSB.
-A1
AO
0
0
0
1
0
i-
Selects Counter 0
Selects Counter 1
Selects Counter 2
Figure 3. Initial Count Loading Summary
READING COUNT VALUES
The current status of a count sequence can be
examined at any time by the program. This can be
done either by reading the counter contents directly
or by latching the counter contents intQ an auxiliary
register and then reading that register.
If a new initial count value is loaded during -a
count sequence, the current sequence will run to
completion and the fullowing sequence will then
start at the new initial count value.
A low on the Gate input inhibits the count.
A counter can be read directly with th.e following bus
conditions:
• Mode 5, Hardware Triggered Strobe - In this
mode, any positive transition of Gate will initiate a
new count sequence. OUT then goes low for one
CLK cycle when the terminal count is reached.
RD A1 AD
LOADING INITIAL COUNT VALUE
Each counter's modulus is determined by presetting
the counter to the desired value. This is done by
means of one or two, I/O write operations with A1, AO
selecting the counter to be preset. The write opera·
tion loads the contents of the data bus (07 - 00) into
the upper or lower half of the selected counter, as
determined by the control word's RL 1, RLO field.
Figure 3 summarizes the various counter loading
conditions.
To Read Counter 0
000
To Read Counter 1
001
To Read Counter 2
o
0
The count should remain stable during direct reading
of a counter. Stability'is assured by holding the Gate
input low or inhibiting the CLK input (by means of
external logic) for the duration of the read operation.
Counter status can also be sampled without
inhibiting the count sequence. This is done by
issuing a control word to the counter with RU, RLO
00, followed by an 110 read of that counter's
location. The RL 1, RLO bits cause the conterits of the
addressed counter to be latched into the auxiliary
register. The subsequent read operations access the
auxiliary register.
After a counter's initial count value is loaded, it is
ready for operation in the specified mode. It begins
counting ClK cycles when its Gate input goes high.
Each CLK decrements the enabled counter by one
until the full count cycle has been completed.
=
The initial count value of any counter can be changed
by loading a new value into the counter's:
When reading either a counter or the auxiliary
register, the read operation must follow the format
programmed for that counter by RLO and RL 1. Note
00 does
that issuing a latch command of RL 1, RLO
not alter the previously programmed RLO and RL 1.
• LSB only (RU, RLO = 01),
• MSB only (RU, RlO
Effect of Subsequent Write Operation
= 10), or
=
• LSB first, and then MSB (RU, RLO = 11).
D-98
Physical Dimensions
inches (millimeters)
1.290
- --------- 62:7661
MAX
PIN NO.1
WENT
O.2ao
i5.08ii)
UGH}
O.lilO
-,~-~MAX~
: - - - -(15.494jMAX -"-!
____
_MAX
0.050 -0,010
~~ __t~'12)"2541
~ ~ ~ ~.--0~ ~ VV~ VV[1- .
,
-·~l
0.125
-~I
0.070'0.1110
OHIO'I).OID
0018-0.002
(i"i7!i)
(1~17e:-O.254~
(2.5400.2541
(0.451-00511
MIN
24·Lead Hermetic DIP (D)
NS Package Number D24A
0.n62
11.575)
""
0.030
11.600-0.&20
t
.r~--:
f
~
+0.025
0,&25_0,015
(~~6:)
-
,
(15.115~~:~~~}~
(~':;:l
~
0.009-0.015
(0.229-0.381)
_
0.1600:0.1105
(1.~~~--j:-
L
L
(~_]"4'"71
~
.-I
~~ .
0,905'0.381)
I
1__
I
_.1
~--.---.-
:
__1
!
I
I_.. ~
I
~2y~40l
_--1L--.O,018'O.OOr,I
(0.451'0,076)
------t-
0.125
MIN
24·Lead Molded DIP (N)
NS Package Number N24A
0·99
1).015
{iG81i
f3.175j MIN
'·ml
I
"
~National
JULY 1978
D Semiconductor
INS8254 N-Channel Bit Programmable
Per~pherallnterface
General Description
Features
The INSS254 is an LSI device which provides two S-bit
ports of peripheral interfacing capability for microcomputer systems. The I/O chip contains two peripheral
ports of eight bits each. Each of the I/O pins in the two
ports may be defined as an input or an output to provide
maximum flexibility. Each port may be read from or
written to in a parallel (S-bit byte) mode. To improve
efficiency and simplify programming in control-based
applications, a single bit of I/O in either port may be
set, cleared or read with a single microproCessor instruction. In addition to basic I/O, one of the ports, port A,
may be programmed to operate in several types of
strobed mode with handshake. Strobed mode together
with optional interrupt operation permit both high
speed parallel data transfers and interface to a wide
variety of peripherals with no external logic.
•
Single +5-volt power supply
•
Low power dissipation
•
Fully static operation
•
Completely TTL compatible
•
Two S-bit programmable,I/O ports
•
I/O port A has TRI-STATE® capability
•
Handshake controls for strobed mode of operation
•
Single bit I/O operations with single instruction
"tJ
c8
OJ
3
3
Q)
•
Reduces system package count
•
Direct interface with SC/MP-II
CD
•
MICROBUS TM* compatible
"tJ
CD
CT
...
is"
The INS8254 is an n-channel silicon gate device packaged
in a 40-pin dual-in-line package. It operates with a single
5-volt power supply and is fully TTL compatible.
i
i
INS8254 MICROBUS Configuration
r'- cs
r
I
cso
CSI
M
I
C
R
0
B
U
S
AS-AD
AD6-ADO
PORT A BUS
PA7-PAO
07·00
WR
RiJ
RESET
INTR
DB7-0BO
NWDS
INS8254
NRnS
NRST
PORT B BUS
. PB7-PBO
INTR
"'-
IIIC.
*Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
D-101
Absolute Maximum Ratings"
Voltage at Any Pin
Operating Temperature Flange
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
,~.
"'
..,0.5 V to +7.0V
O°C to +70°C
-65°C to +150°C
300°C
* Absolute Maximum Ratings are those values beyond whic~ the
safety of ·the device cannot be guaranteed. ,Continuous operation
at these limits is not intended; operation should be limited to those
conditions specified under Electrical Characteri~tics.
DC Electrical Characteristics
(T A within operating temperature range, VCC ; 5 V ± 5% unless otherwise specified.)
Parameter
Conditions
Min
VIH
Logical "1" Input
Volt~ge
2.0
VIL
Logical ,"0" Input Voltage
-0.5
VOH
Logical "1" Output Voltage
IOH ; -100/LA
VOL
Logical "0" Output Voltage
10L; 2.0mA
III
Input Load Current
ILO
Output Leakage Current
ICCI
Power Supply Current
All Outputs Open, TA; 25°C,
NRST";0.8V
Typ
Max
Units
VCC+0.5
V
0.8
V
2.4
V
0.4
V
VIN; OV to 5.25V
±10
/LA
High Impedance State
±10
/LA
60
mA
45
-
AC Electrical Characteristics
(T A within operating temperature range, VCC; 5 V ± 5% unless otherwise specified - see Note 1.)
Parameter
Conditions
Min
Typ
Max
Units
250
liS
READ CYCLE
tsw
STB Pulse Width (Mode 2 only)
tSI
STB .j, to IBF t Delay (Mode 2 only)
300
tps
Peripheral Setup
50
ns
tPH
Peripheral Hold
120
ns
ns
tAH
Address Hold
50
ns
tCH
CS Hold
50
ns
tRD
NRDS .j, to Data Valid
350
ns
tA
Access
560
ns
tco
Chip Select to Output
520
ns
to 1-1
Data Valid After NRDS t
0
125
ns
75
Output L:oad Capacitance
,pF
WRITE CYCLE
tAS
Address Setup
50
ns
tAH
Address Hold
0
ns
tcs
CS Setup
50
ns
tCH
CS Hold
0
ns
tDS
Data Setup
50
ns
tDH
Data Hold
50
ns
0-102
AC Electrical Characteristics (cont'd.)
Parameter
twp
NWDS Pulse Width
tAO
ACK
~
Conditions
Min
Typ
Max
300
ns
to OBF, t (Modes 3 & 4 only)
tACW
ACK Pulse Width (Modes 3 & 4 only)
two
Port Data Valid After NWDS
250
300
300
ACK
~
to Valid Output (Mode 4 only)
tpD
ACK
t
to Hi-Z (Mode 4 only)
300
0
Output Load Capacitance
tWRST Master Reset Pulse
300
v.
Timing Diagrams
Sfii(tNI
,,,-cY--I '" I:: 1
IBftollT)
""~
'1
INT~(OllTl
1:,,,-1 '''1-
peflII'HERAl~~
INPUT
STROBED MODE 2
BASIC INPUT
I
,I--"s-l '" I-
,
~}""
1
1 ,
)CI:I~
r=,1 '''I -
cso AND CSI
°1
'LL-::t:=-I '" 1- '''1-
NRDS
DATABUS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~~----
,
I
Read Cycle
=x=
===>Et:
1--'''--1
I
ADS-ADO
CSOANOCSi
1-'''--1
I
=1"'1-
VAUOA[}{IRESS
Nwns
INTR (OUT)
'~=r
iLl"rrr-
I.
I ~-t1-
ili(PB/)
LWO-j
PERIPHEflAL8US
(BASIC OUTPUT OR
MODE3
r
.
--I ";
I ----------------
~DATA
0'ii"F(I'B6)
STROaED OUTPUT)
X
I:IX
::1,,,1OATAilUS
IST
125
OLD DATA
~
VALID NEW DATA
I
I.
1
1
--I '" I:: --l '" j)------------~~----------~--
.
Write Cycle
0-103
ns
ns
ns
75
Note 1: All times measured from a valid logic "0" level = 0.8 V or a valid logic "1" level = 2.0
ns
ns
~
tpE
Units
pF
ns
INS8254 Block Diagram
(36)
N~~
CSO~
CSl(J8)
NWDS~
NRDS~
REA;)
PA7- PM
WRITE
CONTROL
LOIllC'
INTR
081- DBO
P81- PBO
(40)
.....--VCC
{lU);{J3!
.....--GNO
ADS
Basic Functional Description
The 16·bit input/output provides interface capability between a microcomputer and its peripherals bV '" ans of the two
8·bit I/O ports. The ability to program the configuration and operating modes of the I/O ports allows interfacing a
microcomputer to a yvide variety of peripherals with minimum external logic. Major functional blocks of the chip are
shown in figure 1; an operational summary of the chip is provided in figure 2. A description of the chip pinouts and a
summary of the internal chip registers is given below.
(DBl - DBO) Data Bus Buffers
(NWDS) Write Strobe
The data bus buffer is a TR I·STATE, bidirectional, 8·bit
buffer that is used to interface the INS8254 to a micro·
computer data bus. Data, control, and status information
is transmitted to and received from the INS8254 via the
data bus buffers. Execution of aSTOR E instruction by
the microprocessor may be used to transmit data and
control information from the CPU to the I NS8254.
Execution of a LOAD instruction may be used to trans·
mit data and status information from the INS8254 to
the CPU.
NWDS is an active·low write strobe. A Iowan this pin
enables data or control information to be written into
the INS8254.
(PAl - PAO, PBl - PBO) Peripheral Ports A and B
The INS8254 contains two eight·bit I/O ports: port A
and port
Each port consists of an eight·bit output
data latch with buffer and an eight· bit input data latch.
Full flexibility is provided with the ability to define any
bit of the two ports either as an input or as an output.
Bit set, clear and read of all I/O pins are also provided.
Moreover, port A may be operated in strobed input or
strobed output modes.
(ADS-ADO) Address Inputs
The address input bus determines where in the INS8254
communication will take place. The address determines
which I/O or control register will be enabled for com·
munication with the CPU. These pins are normally
connected to the seven low address lines of the micro·
processor.
B:
(MDR) Mode Definition Register
The Mode Definition Register is an internal control
register that determines the operating mode of port A,
This register is write only. If a read operation is per·
formed with the address set to that of the MDR, the
data bus will remain in the high impedance state.
(CSO and CS1) Chip Select Inputs
The combination of a low on CSO and a high on CS1
input pins enables communication between the INS8254
and the microprocessor.
(NRDSI Read Strobe
NRDS is an active· low read strobe. A low on this pin
enables data or status information to be read from the
INS8254.
0·104
(N RST) Master Reset
NRST is .the master reset input for the INS8254 chip.
A low on this pin clears al.lregisters in the I/O portion
of the chip (MDR, ODRA, ODRB, and the port output
data latches) and places the data bus in the high imped·
ance state independent of any other control strobes.
After a master reset, the I/O ports will both be in the
basic I/O mode and configured as inputs.
UNTR) Interrupt Request
which of the I/O pins in the respective port are to be
used as outputs. ODRA controls .the direction of port
A and ODRB controls the direction of port B. Both
ODRs are write only registers. If a read operation is
performed with the address set to that of an ODR, the
data bus will remain in the high impedance state.
The interrupt request (INTR) output is an active high
signal used to interrupt the microprocessor when a
strobed mode data transaction has occured. This signal
is active only when port A is in the strobed mode. I NTR
will be set to a low when a master reset is applied (N RST
set low).
Output Definition Registers - ODRA and ODRB
Associated with each port is an output definition register
(ODR). Each ODR is an eight·bit latch that defines
Pin Names
Pin Configuration
PB6- 1
"I-vee
PB5- ,
391-.87
3B I-NWDS
.84- 3
PBJ- 4
P82- 5
'81- 6
'80- 7
DBl- 8
DB6- 9
085-"
DB4- 11
083- 12
08'- 13
3J I-NRDS
"I-N"Sf
"I-CSii
34l-e51
3J I-GND
"rAD'
31 f--AD5
3C ..... AD4
29 f--AD3
2B f--AD2
INS8254
087 - OBO
DATA BUS
GND
0 VOLTS
21 ~AOl
081- 14
DBO- 15
26 f--ADO
PA1- 16
25
'A6PA5PA4GND-
24 f--pAO
23 -PA1
22 -PA'
21 ~PA3
17
18
19
20
~INTR
1.-_ _ _---1
Figure 1. Pin Identification
BIT OPERATIONS
~
Set Bit Port A
Clear Bit Port A
Read Bit Port A
Set Bit Port B
Clear Bit Port B
I
Read Bit Port B
PORT OPERATIONS
~
1
o
o
o
1
1
I
I
1
1
I
!
o
: I
o
o !
o
o
o
o
~ I oo
o
1
I
:I
o
o
o
Data Bus
o
1
~
Port A
1
o
Port B -+ Data Bus
o
1
o
o
o
Data Bus -+ Pdrt B
1
o
-0
: I
o
o
o
o
o
o
o
o
o
Port A
~
Data Bus
o
o
o
o
o
o
o
o
o
o
o I
o I 0
o
o
1
o
o
1
CONTROL OPERATIONS
Data Bus
-+
Output Definition A
Da.ta Bus
-+
Output Definition B
Data Bus
-+
Mode Definition Register
o
o
o
DISABLE FUNCTION
Master Reset
Data Bus .... Hi·Z
Data Bus .... H i · Z '
D_a_·t_a_B_u_s_~_H_i_.Z______________
___
~ ~ ~ ~ ~ I ~ I ~ I ~ I ~ ~ I ~I ~
I
I
I
I
l~ X_·~ ~_X ~~-L.~X~1L-X~~ ~I__ ~I__ L-X~__
1
- L__
X
__
X
__X
__
1
Xo
__
Figure 2. Truth Table
0-105
II
X
X
X
X
__X__
X I
x__
X
X__
X
I·IC.
Detailed Operation
Mode Definition Register
The mode definition register defines the operating mode
for port A. Port B is always in the basic I/O mode. There
are four operating modes for port A:
Mode 1 - basic I/O
Mode2 - strobed input
Mode 3 - strobed output
Mode 4 - strobed output with TRI-STATE control
In mode 1, basic 1/0, there is no handshaking and data
is simply written to or read from the 'specified port.
Port B is always in this mode. When NRST goes low,
both port A and port B are set to the basic I/O mode
with all bits set to input. Mode 2, strobed input,
provides a means .for transferring data from the peripheral into port A in response to handshake or strobe
signals. Mode 3, strobed output, provides a means for
transferring data from port A to the peripheral in
response to strobes or handshake signals. Mode 4,
strobed output with TRI-STATE control is similar to
mode 3 except that port A is in the high impedance
state until the handshake signal goes active. Figure 3
summarizes what data should be written into the MDR
to place port A in the desired mode. When port A is
operated .in anyone of the three strobed modes, two
pins of port B are used for handshake control functions;
accordingly, only six of the eight port B pins are
available for data inputloutput bits.
Output Definition Registers
Altho,ugh addressed separately from the ports, the
output df'finition registers are an integral part of the I/O
ports as shown in figure 4. This figure shows the input
data latch and output data latch/buffer of a bit in a port
and the bit of ths ODR associated with it. Thus there is
one bit of an ODR associated with each peripheral I/O
pin in port A and port B. If a low or "0" is written into
the ODR, the output data buffer associated with it will
be disabled, and the I/O bit is in the input mode: If a
high or "1" is written into the ODR, the I/O bit is in the
output mode.. When strobed mode operation (modes 2
through 4) is defined for port A via the MDR, it is also
necessary to set up proper input/output definition in
ODRA for port A.
Basic I/O - Mode 1
In the basic I/O mode of operation data. is simply
written to or read from a port without handshake
signals; the interrupt request (INTR) is always low when
port A is operated in this mode. Port B. is always in the
basic I/O mode, whereas the MDR bit 5 (M in figure 3)
must be set to zero to define port A in the basic I/O
mode. Since the MDR, ODRA and ODRB are all cleared
by a master reset, both port A and port B will be in the
basic input mode after a master reset (N RST set low).
Figure 5 shows a timing diagram for basic output. When
the microprocessor performs a'write operation to a.port,
the data on the data bus is latched in the output latch
on the leading edge of the write strobe. The data will
remain valid until another write to the port with new
data occurs. If the new data written is the same as the
old data, then no change will occur so long as the
proper data and strobe timing is maintained.
Figure 6 shbws a timing diagram for basic input. When
the microprocessor reads the port, the peripheral data is
latched in the input latch on the leading edge of the read
strobe. The data bus buffers are enabled so the contents
of the latch are gated on to the system· data bus. The
data remains latched unti I the end of the read cycle
(i.e., until the trailing edge of the read strobeL Latching
the input data in this manner allows the chip to synchronize asynchronous peripheral signals with slow rise and
fall times to the microprocessor.
A port .can have some input pins and 'some output pins,
since th'ere is an ODR latch for each bit in the port. A
write to a pin defined as an input will load a new value
into the output data latch, but since the output data
buffer is disabled, it will have no effect on the I/O pin.
A data. read from I/O pins defined as outputs will read
the data from the output data latch. The data will be
read properly only if the I/O lines are permitted to be
greater than VI H for a logic 1 output' and less than VI L
for a logic 0 output. If the I/O pins are loaded in such a
way that valid levels are not reached, the data read will
not always agree with the data stored in the output data
latch'.
Bit Set, Clear, and Read
In addition to reading and writing each port as an eightbit parallel byte, it is ~Iso possible to set, clear or read
any individual bit in either port. Bit set or clear is performed by doing a write operation with the chip selected
and the proper address. Since the address determines
which bit is operated on and whether it is set or cleared,
the eight data bus lines are all don't-care for a bit set or
clear. This permits the microprocessor to do a bit set
or clear with a single instruction without initially setting
up the accumulator. The three low order bits of the
address determine which bit of the port is set.or cleared
(e.g., AD2 ~ 0, ADl ~ 1 and ADO ~ 0 would indicate
bit 2). Address bit 3 (AD3) determines if port A.or port
B is acted upon. Address bit 4 (AD4) determines if the
operation is a bit set or clear.
When a bit read is performed, the selected bit is placed
on data bus bit 7 (DB7) and all other bits of the data
bus are set to zero, The bit is selected by reading from
the chip with the same addresses described for bit set
and clear. All bit operations are summarized in figure 7.
Besides simplifying programming in control applications,
bit operations are used to control interrupt enable when
port A is in the strobed mode. The timing for bit operations is the same as that for basic input/output except
that, for bit set and bit clear operations, the data bus is a
"don't care." A bit set to a pin whose previous value was
a "1" or a bit clear to a pin whose previous value was a
"0" will not cause that pin to leave its previous value,
even momentarily.
D-106
DB7
DB4
DB5
DB6
DB3
DB2
_.
TS
OUT
M
-
-
OBI
DBO
-
_.
Bit Location
MDR Bit Name
X
X
0
X
X
X
X
X
Basic I/O
X
0
1
X
X
X
X
X
Strobed Input
0
1
1
X
X
X
X
X
Strobed Output
1
1
1
X
X
X
X
X
Strobed Output with TRI·STATE Control
Figure 3. Mode Definition of Port A with MDR
r<1---------~~~------~
INPUT
DATA
LATCH
SET
INTE~:~k _ _...._ _ _ _-:-_~O
01-_ _-_ _ _ _ _-1
BUS
OUTPUT
I
DATA
LATCH
:>-_....__ r/~R~r~ERAL
."
".
RESET
L-_ _ _ _ _ _ _ _ _
_____
roo-
~.o
o~
OUTPUT
DEFINITION
REGISTER
Figure 4. Internal Logic of One Bit of an I/O Port with ODR.
AD6-ADO
x:=:
VALlDA~~RESS
=::>{
~tAH=I
i=tAS---1
CSOANDCSt=X
=-1
1
tcs
DATA 8US----......) (
tDs_1
::
I1
PERIPHE~~~
1-
C
1
'AD6- AD0
1
-l
}tDH
two
:=:X
CSOAND CSt
X'-________
I
VALID DATA
I-tps-l tPH !-=
VfllDADD~:SS
--1
XII::
~t~o-j
I-
1
x==
1-
x=
tAH
-!tCH!-=
NRDS~~
-1 1- =l
NWOS~:=y-~
I
'1~-tA+--1
-JtcHI-
VALI~ DATA
==x
1-
tRD
PERIPHE~~~ _ _ _Ol_D_D_A_T_A_ _.JX'--V-A-l-'D-N-E-W-D-A-T-A---
OATABUS---------FvALIODATA
~.
l - t OH
I ---I
Figure 6. Basic Input Timing
Figure 5. Basic Output Timing
NRDS NWDS
A4 A3 A2 Al AO
BIT SET & CLEAR
Bit Set, Port A
1
0
1
0
B2 Bl
BO
Bit Clear, Port A
1
a
0
0
B2 Bl
BO
Bit Set, Port B
1
0
1
1
B2 Bl
BO
Bit Clear, Port B
1
a
a
1
B2 Bl
BO
Bit Read, Port A
a
1
X
a
B2 Bl
BO
Bit Read, Port B
0
1
X
1
B2 Bl
BO
BIT READ
Selected Bit -+ DB7
0-+ DB6 - DBa
Bit Operations Enabled When
eso ~ 0, eSl
= 1, A6 = 0, & A5 =
82,81, & BO select which bit is selected (80 is least significant bit).
Figure 7. Bit Operations
0-107
DDI
O.
Strobed Input (Port A) - Mode 2
r
that data has been read in the microprocessor and that
the next transaction can now take place. The microprocessor can override IBF by doing a bit set or bit clear
to flB6.
This mode allows data to be read from, a peripheral. in a
two-step transaction. First, the 'peripheral strobes data
into the I NS8254 input latch and notifies the 'microprocessor that data is ready to, be read. Second, the
processor reads the contents of the I'NS8254 input latch
and resets the handshake control signals for the next
transaction tc;> take place. Transferring data in two steps
frees the microprocessor to undertake ottier, tasks in
between data transfers from the port A peripheral:
Figure 8 shows the signal timing and figure 9 shows a
logic diagram for the handshake signals. The handshake
control signals are as follows:
IE (Interrupt Enable)
IE is the output data latch of PB7, whose output is
AN Dep with the interrupt request latch to produce' the
I NTR signal. IE is zero after a master reset (NHST) but
may be written into from the microprocessor by doing a
bit set/dear to PB7.
INTR (Interrupt Request),
STB (Str0b8)
When enabled 'by IE, INTR is an output that is set on
the trailing edge of STB, requesting the microprocessor
to read the data in the port A input data latch. When
the microprocessor responds to read port A, the trailing
edge of NRDS resets INTR. Should IE not be set, INTR
will remain low.
The STB signal is an, active-low strobe generated by a
peripheral to signify that data is valid at the peripheral
bus on the trailing edge of this strobe. This signal is fed
into pin PB7 of the INS8254. STB latches peripheral
bus data into the I NS8254 input data latch on its
trail ing edge. This does not require the INS8254 to be
selected. Should STB pulse low more than once before
the arrival of NRDS, the data stored in the INS8254
input data latch will be the last stored data.
In a multiple-interrupt application, the microprocessor
can poll the INS8254 for the existence of an interrupt
request by doing a bit read of PB7. Being able to read
the INTR status on the microprocessor system bus is
useful in multi-interrupt schemes to'find the originator
of an interrupt.
IBF (Input Buffer Full)
The 18F signal is an output from the INS8254 driven
by pin PB6; IBF is set ,by the leading edge of STB and
is reset by the trailing edge of NRDS when the microprocessor is performing a byte-read from port A. IBF
high tells the peripheral that data is latched in the port A
input data latch. ISF goes low on th,e trailing edge of the
microprocessor NRDS strobe to notify the peripheral
Parallel write operations to port B while port A is in any
one of its strobed modes will leave bits PB6 and PB7
unaffected. Thus, port B now has 6 data I/O bits
associated with it and the handshake bits PB6 and PB7
respond only to valid changes in handshake status or to
bit set/bit clear operations.
/-,sw-I
mIPB11~;
~'slt=.1
--I'r-.,. ...;...---.. .u;.------------(A--'
-'.,
IBFIPBBI _ _
INTRIOUT)~l
'PS-j
PERIPHERAL
INPUT
A06-ADO
'PH
~......_ __
I .
1-=
--~----------~I-----
X!=='A---j
VALIDAOD~~SS I x===
-l'CHr: '
---JX I: I X,--_
_ _ _ _ _- - J
mAND CS1 _ _ _ _ _ _ _ _ _ _ _
~.Co1·
I~
4~OHr'
NRDS
HI·Z
~
O A T A B U S - - - - - - - - - - - - - - - - - - - - - - ~ALlDDATA
Figure 8. Strobecllnput, Mode 2 Timing
0-108 '
\HI·Z
{ ----
Initializing Strobed Input - Mode 2
Prio( to operation, ·an initialization procedure must be
undertaken. The MDR must have a "1" written into bit
5 and a "0" written into bit 6. The ODRA must have
"Os" written into it to identify the pins in port A which
will function in mode 2. The ODRB must have a "0"
written into PB7 in order to make it an input which will
receive STB from the peripheral. Also, PB6 must be
defined as an output so that it can drive the I BF signal.
The remaining six lower bits of ODRB are configured as
needed for the basic input/output transactions occuring
in port B.
TS OUT M
I 07-I 060 I05 I
I-I
I 0 I06 I -I
I-I I-I
1
1
07
MOR
DO
Mode 2
OORB
DO
ODRA = "Os" at mode 2 pins.
..-LM~
Writing to the MDR to define mode 2 operation will
automatically initialize both IBF and INTR in such a
manner that they will be expecting the peripheral to
begin the first I/O transaction with a STB strobe, i.e.,
both INTR and IBF will initialize low when the above
write to the MDR takes place.
Handshake Status
Handshake status control signals IBF and INTR will be
reset by a microprocessor LOAD instruction only if it
is addressed to port A as a byte read. A parallel write or
bit write or bit read to port A will not affect handshake
status. A byte read or write to port B wi II not affect
handshake status either, since PB6 and PB7 are masked
from byte writes to port B when port A is in any of its
strobed modes. It is possible, however, to override I BF
or IE by an appropriate bit write to PB6 or PB7, respec·
tively .
I
----------------
CSOANDCS1==X
'DH
DATAOUS----"""X
VAl+ATA
NWDS~Jr--1
-
-
_--+-I----;,-h
INrR (OUT)
r--/
~"--:l
I
-
OBF(DUT)=PB6-~I-----/I~D,.---+~I-
L" ::1
'.,
ACKIIN)=PB7
Cl
.
.
'\.yr---
' "\,II:-'ACW
I
t WD
,
PERIPHERA~ BUS _ _ _ _O_lD_D_A_T_A_ _-JX~------~v"'~,-L-ID-N-E-W-D-AT_A_ _ _ _ _ _ __
Figure 10. Strobed Output, Mode 3 Timing
D-110
Initializing Strobed Output - Mode 3
Writing to the MOR to define mode 3 operation will
automatically initialize both OBF and INTR such that
the INS8254 will be expecting the first strobed opera·
tion to take place. Both INTR and OBF are initialized
high for mode 3, provided I E is set to a "1." If I E is
set to "0," INTR will not initialize high.
To initialize for mode 3 operation, tHe MOR must have
"ls" written into bits 5 and 6. A "0" must also be
written into bit 7.
The OORA must have "1 s" written into it to identify
the bits of port A which will function in mode 3. The
OORB must have a "0" in PB7 in order to make it an
input which will receive ACK from the peripheral. Also,
PB6 must be defined as an output so that it can drive
the OBF signal. The remaining 6 lower order bits of port
Bare configu red as needed for the basic I/O transactions
Handshake
occurring in port B.
TS OUT M
I0 I I
MDR
D7
DO
I0 I
I-I
D7
Statu~
- Mode 3
Handshake status control signals OBF and INTR will be
reset low by a CPU STOR E instruction only if it is
addressed to port A as a parallel write. A parallel read or
any bit operation to port A will not affect handshake
status. A word read or write to port B will not affect
handshake status either, since PB6 and PB7 are masked
from word writes to port B when port A is in any of its
strobed modes. It is possible, however, to override OBF
or I E by an appropriate bit write to PB6 or PB7, respectively.
Mode 3
ODRB
DO
OORA = "ls" at mode 3 pins.
M:=l
M" 0
PBI
INPUT
ElATA
LATCH
BIT SET PB7
INTERNAL
DATA
PBl
BUS
PBl
INPUT PIN
OUTPUT
DATA
LATCH
IIEI
IACKI
BIT ClEAR PH1
OUTPUT
DEFINITION
REGISTER
t - - - - - -.....ooj0INTERRUPTQ .---.._.J------<~---.,....., ~NU\RpUT PIN
HANDSHAKE
REOUEST
lOGIC
LATCH
PB6
INPUT
DATA
LATCH
BIT SET
PB6
:>--....------.-, PB6
OUTPUT PIN
IOBFI
BIT CLEAR
PB6
OUTPUT
DEFINITION
REGISTER
Figure 11. Strobed Output, Mode 3 Handshake Logic
0-111
Strobed Output with TRI-STATE Control - Mode 4
TS OUT M
This mode, is si~ilar to mode 3 in thatit"uses the same
handshake signals and transfers data in. the same direction. A timing diagram for mode'.Ij is shown in figure 12.
Handshake logic is shown in figur~ 11. Th'e main
difference from mode 3 is the fact that the peripheral
bus is in the TRI-STATE condition at all times except
when ACR is low, enabling the INS8254 to drive the
peripheral bus to its valid state.
I 07 I
.'
I
,
I
t'CS"
Handshake Status - Mode 4
'Handshake status control signals OBF and INTR will be
reset low by a CP-U STORE instruction only if it is
addressed to port A as a parallel write. A parallel read or
any bit operation to port A will. 'not affect handshake
status. A word read or write to port B will not affect
handshake status either, since PB6 and PB7 are masl',
. S
HI·Z
,
PERIPHERALBU .---:--:------':""----~-'""'--:-_;.
Figu";' 12. Strobed Output with TRI.sTATE Mod. 4 Timing
0-112
'PD
r-
).
HI·Z
VALIDDAT~ ( - - - -
SC/MP·II
16·81T I/O
AOOO - A006
AOOO - A010
ADO - A06
+5 V
--
AOll
SIN
CSI
~
SOUT
PA 10 -71
~
_S8
IOS8060
_FO
NROS
ill
IN58254
NRDS
_Fl
P8 10-7)
_F2
NWDS
If PERIP~ERAll
!\PERIP~ERAll
NWDS
SENSE A
INTR
0810 -7)
0810-7)
NRST
NRST
+
f
ADIO~
OUT (0
~
7)
256
TO
2048
A 10-91
ADll
CSi
NRDS
RESET
BYTE ROM
CSi
Figure 13. Typical Application - Three*Chip SC/MP Family System
with 22 Bits of I/O and Up to 2048 Bytes of ROM.
r'-
CS
i> !
A15~AO
eso
A15-AO
INS8080A
CSi
AND
(INS82lS05)
CS;
087·080
M
I
e
R
0
8
U
S
OJ-DO
07-00
MEMR
DBIN
82
+
PORT A BUS
07-00
ViR
ViR
81
J
1'D
RESET
INTR
PA7-PAn
NWOS
INS8254
NRDS
PORT 8 8US
PBJ-PBO
NRST
INTR
MEMW
I NSa228
OJ-DO
STST8
OUT
I/OR
Al0-AO
I/OW-
"'-
RESET
T ......
256
TO
2048
A
IN58224
L~DrJ
eso
A06ADa
INT
01-00
eSI
AS-AD
CHIP
SElECT
lOGIC
All
RESET
CSI
MEMR
BVTE ROM
cst
"\.
Figure 14. Typical Application -
INS8080 System with 16 Bits of
I/O and up to 2048 Bytes of ROM.
0·113
~
•
Physical Dimensions
Inches/Millimeters.
- :L
2.020
(51.J08)
MAX
0.520
1
0.032
(D.all)
,AD
0.590
(14.986)
~~~~;;;n;;n;;n;;r'j
40·Lead Ceramic Oual·in·Line Package (01
0.062
{1.~~~.~
(13.970,(1.127)
PIN NO. llNDENT ~
~~7Fr.T~=r.FT.~7Fr.r~g~~"~,,~,~,~,,fT,"~~"~"rT.,~,~,,~,,~a~~
0.030
0.060 (0.162)
.
' . __ (15.240-15.748)
~.OO_O'6."_
.. _-.J
C
-1 (1.524~
t
~
J.
M.AX.
O.OSIJ
~.
0.210)
!1l0±O.005
(3.302
±O.12l)
. . ~;'5 1-
.=
'..~
-~iD.229-iill" I '
r--- h~~~-;;+O.6J5)---I ~TaU-- I--
f
.'.015
0.625 -0.015
I
I \
I
0.075 '0.015
--
-0.381
I·.
I
D.WO
(2.540)
TVP
--l,0.020
0125 (D.50B)
I
0.018,0.003
--- ---(0.451 '.0.076)
(3:175) MIN
MIN
40·Lead Plastic Oual·in·Line Package (NI
Ordering Information
The INS8254 may be ordered through the local National Semiconductor sales representative or by contacting our
world or internatio,nal headquarters listed below.
For "N" Package: INS8254N
For "0" Package: INS82540
Hatlonal Semiconductor
Corporation
2900 Semico'nductor Drive
Santa Clara, California 95051
Tel.: (406)737-5000
TWX: (91O)'339c9240
National SemIconductor GmbH
8000 Mlinchen 21
,
Eisenheimerstrasse 61/2
West Germany
Tel.: 089/9 15027
Telex: 05-22772
NS Internallonallnc., J.p.n
Miyake Building
1-9 Votsuya, Shlnjuku-ku 160
Tokyo, Japan
Tel.: (03) 355-3711
TWX: 232-2015 NSCJ-J
Nallonal Semiconductor
NS Electronics 00 Brasil
(Hong Kong) Ltd.
8th Floor.
Cheung Kong ElectroniC Bldg
4 Hing Yip Street
Kwun Tong
Kowloon, Hong Kong
Tel.: 3-411241-8
Telex: 73866 NSEHK HX
Cable: NATSE~I
Avda Brigaaeiro Faria- lima 844
11 Andar Conjunto 1104
Jardim PauHstano
Sao Paulo, Brasil
Telex:
1121008 CABINE SAO PAULO
NS Electrpnlcs Ply. ltd.
Cnr. Stud Rd. & Mtn. Highway
Bayswater. Victoria 3153
Australia
Tel.: 03-729-6333
Telex: 32096
National does flat assume any responsibility for use of any circuitry described: no circuit patent licenses are implied, and National reserves the right, at any time without notice, to change-said circuitry.
o -114
'.
~National
Preliminary
~ Semiconductor
JULY 1978.
INS8257 Programmable DMA Controller
General Description
The INS8257 is a Direct Memory Access (DMA) con·
troller contained in a standard 40·pin dual·in·line
package. The chip, which is fabricated using
N·channel silicon gate technology, performs direct
control of high speed data transfers to and from
memory over four separate channels. Data can be
transferred in single bytes or in blocks containing up
to 16,384 bytes.
The channel control registers consist of four 16·bit
DMA address registers and four 16·bit terminal count
(TC) registers. These registers provide the means for
con·trolling DMA transfers on their respective
channels.
The auto load feature permits the repetition of block
transfers or the chaining of data blocks with a mini·
mum of register initialization required.
The INS8257 accepts requests for memory access
from peripheral devices attached to its four DMA
channels and acquires control of the system bus
whenever the DMA request is honored. Competing
requests are resolved according to a programmable
priority scheme (fixed or rotating).
Features
• Four·Channel DMA Controller
• Priority DMA Request Logic
• Channel Inhibit Logic
• Terminal Count and Modulo 128 Outputs
• Auto Load Mode
• Single TTL Clock
• Single + 5V Supply
The mode set register contains fOllr individual
channel enable bits plus option select bits for the
following options: rotating priority, extended write,
TC stop and auto load.
• Expandable
• MICROBUSTM* Compatible
INS8080 Family CPU Group MICROBUS Configuration
A7- AO
ilJiCKijl------I~1
OROO 1 _ - - - - - 1
iiAcKi I------I~I
-tt===:::::1 ~
ORO'
1
1_-----1
J-;:===~~
J-;:===~~
INSB257 DAm
DRozl....
~====::jl :~~~v
HOLD....
HLOA - - - - -__
DACK3
DR031 ...
iiiiSEN_------+
0I8·OI'I+1----11j
INS8212
m
ST.
·Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
Z
~
"tJ
c8;;
3
3
S»
C"
CD
c
3:
»
g
Program control of the INS8257 is exercised via a
mode set register and four pairs of channel control
registers (one pair per channel). A status register is
also Included, which provides terminal count status
for each channel. The status register also contains a
register programming flag, which is a valuable aid in
maintaining byte synchronization when pJogram·
ming channel control registers.
eLK
-
0·115
...a:::s
..CD
Absolute' Maximum Ratings
Maximum Voltage to Any Input with
RespecttoGND ............................. -0.5Vto +7V
Operating Temperature .............•......... O·C to + 70·C
Storage Temperature .................... - 65·C to + 150·C,
Power Dissipation .................. '.•. : ............ 1. Watt
.'
Note: Maximum ratings indicate limits beyond which permanent
damage may occur. Continuous operatlQn at these limits is not
intended ,and should be limited to those conditions specified
under DC Electrical Characteristics.
..
DC Electrical Characteristics
Symbor
VIL
TA
= O·Cto
Parameter
+10'C,Vee
=
+5V ± 5%, GND
= OV
Min
Max
Units
Input Low Voltage
-0.5
0.8
Volts
2.0
Vee + 0.5
Volts
0.45
Volts
Vee
Volts
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
Test Conditions
= 1.6mA
IOH = -15()j.lA for AB,
IOL
DB and AEN
IOH = - 80,..A for others·
IOH = ..,. 80,..A
VHH
HRQ Output High Voltage
Vee
Volts
Icc
Vee Current Drain
120
mA
IlL
Input Leakage
10
,..A
VIN
IOFL
Output Leakage During Float
10
,..A
VOUT (Note 1)
3.3
= Vee
Note 1: Vee> VOUT > GND + O.45V.
I
Capacitance TA = 25°C, Vcc = GND = OV
Symbol
Parameter
Min
Max
Units
CIN
Input Capacitance
10
pF
tc
CliO
I/O Capacitance
20
pF
Unmeasured pins
returned to GND
,
.p·1113
Test Conditions
= lMHz
AC Electrical Characteristics
TA
= o·c to
+ 70·C, Vee
= + 5V
± 5%, GND
= OV (Note 1)
Max
Units
Bus Parameters
READ CYCLE
Symbol
Parameter
tAR
Adr or C~ Setup to
Min
RD~
tRA
Adr or CSt Hold from ROt
TRO
Data Aceess from
tOF
tRR
0
0
RD~
Test Conditions
ns
ns
0
300
ns
DB - Float Delay from ROt
20
150
ns
RD Width
250
(Note 2)
ns
WRITE CYCLE
WR~
tAW
Adr Setup to
20
ns
tWA
Adr Hold from WRt
0
ns
tow
Data Setup to WRt
200
ns
two
Data Hold from WRt
0
ns
tww
WR Width
200
ns'
ns
OTHER TIMING'
tRsTW
Reset Pulse Width
300
tRSTO
Power Supplyt (Vee) Setup to ReseH '
500
tR
Signal Rise Time
20
ns
tF
Signal Fall Time
20
ns
t RSTS
Reset to First IOWR
ns
2
tey
Note 1: All timing measurements are made at the following reference voltages unless otherwise specified:
Input "1" at 2.0V, "0" at O.BV; Output "1" at 2.0V, "0" at O.BV.
Note 2: CL = 100pF.
Timing Waveforms (Peripheral Mode)
Write Timing
Read Timing
'AWl
ADDRESS BUS
twA
I
'AR
==r
___t:=
__
'''''Aw''------j
DATA BUS
CHIP SELECT
)t
~
ADDRESS BUS
y-
IIORO
I ~tWA--
_ _ _~______~~j'DW_1:r~tw~D_~__
~
__
i70Wii
'--'
Reset
'AR~tRA
'
,
DATA BUS
J::::;-;! 'RA
~r='OF
'RD
I!jII!IIiII'&
if}"
Input Waveforms for AC Tests
'RSTW
_
'RST~ ~tww-I
2.0
o,;-
RESET
o~: -----JX
-j--/·tRSTO-lr"-'-------------
vcc--,"
0-117
2.0
TEST
POINTS-;.l'-___
".
AC Electrical Characteristics
"
' '
,
,"
TA = O·Cto +70·C. Vcc = +sv ± S%"GND=OV
DMA (Master) Mode
Parameter
Symbol
Cycle Time (Period)
tCY
t6
' . Clock Active (High)
"
-
Min
Max
Units
0.320
4
/AS
120
O.BtCY
lsst Conditions
"
ns
, ns
".
teis
DRat Setup to 8~(SI,S4)
tOH
ORa. Hold from HLDAt
too
HRat oUDelay from 8t(SI,S4)
at 2.0V)
160
ns"
Load =.1 TIL
. t001
HRat or melay from 8t(SI,S4)
(measured at 3.3V)
160
ns
Load = 1 TIL + (R L =
3.3k), VOH = 3.3V
~Setup
to 8t(SI,S4)
120
0
Tracking· Specification
ns
tHS
HLDAt or
tAEL
AENt Delay from 8t(S1)
100
tAET
AEN. Delay from 8t(SI)
tAEA
Adr(AB) (Active) Delay from AENt(S1)
tFAAB
Adr(AB) (Active) Delay from 8t(S1)
2S0
ns
Load = 1 TTL + SOpF
tAFAB
Adr(AB) (Float) Delay from 8t(SI)
1S0
ns
Load'= 1 TIL + SOpF
tASM
Adr(AB) (Stable) Delay from 8t(S1)
2S0
ns
Load = 1 TIL + SOpF
tAH
Adr(AB) (Stable) Hold from 8t(S1)
300
200
20
ns
ns
·ns
Load = 1 TIL
Load == 1 TIL
Tracking Specification
tASM - SO
ns
Load = 1 TIL + SOpF
tAHR
Adr(AB) (Valid) Hold from Rdt(S1,SI)
60
ns
Tracking Specification
tAHW
Adr(AB) (Valid) Hold from Wrt(S1,SI)
300
ns
Tracking Specification
tFAOB
Adr(DB) (Active) Delay from 8t(S1)
ns
Load = 1 TTL + SOpF
tAFOB
Adr(DB) (Float) Delay from 8t(S;!)
tssT + 20
ns..
Load = 1 TIL + SOpF
tASS
Adr(DB) Setup to AdrStbHS1-S2)
100
ns
T~acking
tAHS
Adr(DB) (Valid) Hold from AdrStbt(S2)
50
ns
Tracking Specification
tSTL
AdrStbt Delay from 8t(S1)
200
ns
Load = 1 TIL
tsn
AdrStbt Delay from 8t(S2)
140
ns
Load = 1 TIL
tsw
Adr'Stb Width (S1-S2)
tCY - 100
ns·
Trackil)g Specification
tASC
Rd. or
Wr(Ext~
70
ns
Tracking Spec'ification
t OBC
Rd. or Wr(Ext). Delay from Adr(DB)
(Float)(S2)
20
ns
Tracking Specification
tAK
DACKt or mefay from 8.(S2,S1) and
TC/Markt, Delay from9t(S3) and
TC/Markt Delay from 8t(S4)
,
250
ns
Load = 1 TIL,
AtAK < 50ns
tOCL
Rd. or Wr(Ext). Delay from 8t(S2) and
Wrt Delay from 8t(S3)
200
ns
Load = 1 TIL + SOpF,
AtOCL ---- rl~t~
ADR IH (lOWER AORj - - - - - - - - - -
~
~
Q.
e
AEN
ADR)
c.o
-----DAtI( 11-3
-------------t~k!---_1_----+_1_~
'FAt
- - - - - DADKG-l
'O",-!]:-
O'ORO/IIORO----------
MEM WRII/a WR -
-
-
- - - -
- - -
__________
READY
----------
TC/MARK _ _ _ _ _ _ _ _ _ _
-----../
1--
",.--....:.~'1\t;;...~.,.------__:;--,--"7--"""".L - - - - - -'
I~,
f
'AHR--I
~-
,f ---------'
IAHW'-_I
\\- _ ~
twwM~-·1
-i----
...-----
.
'- - - - - - - - -
~
\'
't'"
\....
I
-t'
1-
tRS--
-----
M'MRO/IIORO
-- -
MEM ROIIIO WR
~
_
I~--,AK
~
AOR STI
READY
-------
r=\
c--\
I
\
___
TeMARk
INS8257 Functional Block Diagram
(11-13)
(16-30)
07-05
04-00
~ORQ6
CH4
4
Il.ATA
BUS
BUFFER
~
16
BIT
(15)
CHI
DACK6
ORQ 1
16
BIT
OACK 1
ClK
RESET
CHI
A3-AO
cs
ORQI
16
BIT
(II)
OACKI
t
CH3
A7-A4
CONTROL
lOGIC
AND
MODE
SET
REG
READY
HOLD
HlDR
MEMR
MEMW
AEN
ST8
TC
MARK
ORQ3
16
BIT
(34)
6}
--
PRIORITY
RESOLVER
INTERNAL
BUS
NOTE: APPLICABLE PINOUT NUMBERS
ARE INClUDEO WITHIN
PARENTHESES_
0-120
(l5)
"DJiCi(j
..Jill-
VCC
....Jill-
GND
INS8257 Functional Pin Description
The following describes the functions of all INS8257
input/output pins. Some of these descriptions refer
to internal circuits.
Address Enable (AEN): The INS8257 may use this
output to disable the system data bus and the
system control bus. It does this by applying AEN to
the Bus Enable input of the CPU's System Controller
chip (e.g., INS8228). It may also be used to isolate
non·DMA devices from the system address bus
during DMA operations. This is done by applying
AEN to the enable input of each address bus driver
chip to be disabled.
INPUT SIGNALS
Data Request (DRQO- DRQ3): Each channel interface
has a separate DRO input, which is used' by the
peripheral to request DMA cycles. To make a request
for DMA service, a peripheral raises its DRO line and
holds it high so long as DMA cycles are needed. The
peripheral drops its DRO n when the DMA acknow·
ledge (DACK n) is received for the last DMA cycle in
the data block. See Output Signals for a description
of the DACK signal.
Clock (ClK): This clock is supplied by the ~2 (TTL)
output of the INS8224 Clock Generator and Driver
(pin 6) or its equivalent.
Reset: When raised to the high logic level, this input
clears all INS8257 registers and control lines, ex·
cepting the channel address registers. It would nor·
mally be supplied by the INS8224 Clock Generator
and Driver (pin 1) or its equivalent.
Terminal Count (TC): The INS8257 uses this output to
notify the selected peripheral that thE! current DMA
cycle is the last cycle in the data block. If the mode
set register's TC Stop bit (bit 6) is set, the selected
channel is automatically disabled at the end of that
DMA cycle. The INS8257 control logic issues TC
when the terminal count register decrements to 0
(excluding bits 14and 15).
Modulo 128 Mark (MARK): The INS8257 uses this out·
put to notify the selected peripheral that 128 DMA
cycles have occurred since the previous MARK
output. MARK always occurs at 128 (and all multiples
of 128) cycles from the end of the data block.
Chip Select (CS): When this input is low, the chip is
selected. This enables the INS8257 read/write inter·
face logic.
Ready: This input inserts wait states into the
INS8257's memory read and write cycles if required
by the addressed memory.
Hold Acknowledge (HlDA): When high, this input
from the CPU notifies the INS8257 that it has control
of the system bus.
OUTPUT SIGNALS
DMA Acknowledge (DACK3- DACKO): Each channel
interface has a separate DMA acknowledge output.
When a channel's DMA request (DRO) is honored by
the priority logic, that channel's DACK output is
brought low to notify the peripheral that it has been
selected for a DMA cycle.
Address lines (A7-A4): These four TRI·STATE® ad·
dress outputs carry bits 7 through 4 of the memory
address produced by the INS8257 during the addres·
sing phase of DMA cycles.
Hold Request (HRQ): The INS8257 raises this output
in order to request control of the system bus.
Memory Read (MEMR): The lNS8257 brings this TRI·
STATE output low in order to read data from memory
during DMA read operations.
Memory Write (MEMW): The INS8257 brings this TRI·
STATE output low in order to write data into memory
during DMA write operations.
Address Strobe (ADSTB): The INS8257 uses this
output to strobe address bits A15-A8 from the
INS8257's bidirectional data lines (D7 - DO) into the
memory's address buffer (e.g., INS8212).
INPUT/OUTPUT SIGNALS
Data (DO- D7) Bus: This bus, which comprises eight
TRI·STATE input/output lines, provides for bidirec·
tional communication between the INS8257 and the
CPU. When the CPU is initializing the INS8257, this
bus may carry data for the DMA address register,
terminal count register or mode set register. Read
data is carried by these lines when the CPU reads a
DMA address register, a terminal count register or
the status register. During the address phase of a
DMA cycle, these lines carry the eight high·order bits
of the memory address. During the data transfer
phase of a DMA cycle, this bus carries the data byte
being written into or read from memory.
110 Read (1I0R): This is a low·true, bidirectional TRI·
STATE line. It is used by the CPU to read INS8257
registers (DMA address register, terminal count
register or status register) and by the INS8257 to
input data from a selected peripheral during DMA
write operations.
I/O Write (1I0W): This is a low·true, bidirectional TRI·
STATE line. It is used by the CPU to write into
INS8257 registers '(DMA address register, terminal
count register or mode set register) and by the
INS8257 to output data to a selected peripheral
during DMA read operations.
Address lines (A3-AO): These lines, which carry the
four least significant system address bits, are bidi·
rectional. They function as input lines when the CPU
uses them to select one of the INS8257 registers.
They function as output lines during DMA cycles
when they ci;lrry the four least significant bits of the
memory address.
D·121
PROGRAMMING
Pin Configuration
IIDR
40
A7
IIDW
MEMR
MEMW
MARK
READY
HlDA
ADOSTB
AEN
HRD
39
A8
As
cs
elK
RESET
OACK2
OACK3
OiID 3
ORD2
ORO 1
ORO 0
GND
38
37
36
35
4
5
6
A4
A3
A2
AI
AD
33
32
31
30
INS8257
12
13
14
15
16
17
Vec
DO
29
28
27
26
25
24
23
22
21
18
19
20
The OMA address registers and TC registers can be
programmed in any order. However, the mode set
register sho\lld not be programmed until after the
OMA address and TC registers are initialized. This
precaution is intended to prevent invalid access of
memory in the event a spurious OMA request (ORO n)
is generated.
Te
34
10
11
There are three types of registers that must be initial·
ized:
1. Four OMAaddress registers (one per channel)
2. Four terminal count registers (one per channel)
3. One mode set register.
NOTE
For any transfer on the system data bus involv·
ing position·weighted bits, 07
most signifi·
cant bit and DO = least significant bit.
01
02
03
04
OACKO
OACK 1
05
D6
07
=
Because each channel register is two bytes wide,
two I/O read, or write operations are required to read
or load an entire register. When one of these
registers is selected by the CPU, INS8257 logic
automatically accesses the register's lower half for
the first I/O operation and the upper half for the
second I/O operation.
INS8257 Programming Information
This section provides basic information for program·
ming the INS&257 and describes the status infor·
mation available to the programmer. Table 1 sum·
marizes the bus controls needed to output control
information to the INS8257 and to read INS8257
status.
Table 1. INS8257 System Bus Controls
(Note 1)
Function
A,
A2
A,
Ao~
Load ChO DMA AddrFlSS Register
0
0
0
0
0
1
0
Lqad Ch1
0
0
1
0
0
1
0
Load Ch2
0
1
0
0
0
1
0
Load Ch3
0
1
1'
0
0
1
0
Read ChO OMA Addr~ss Register
0
0
'0
0
1
0
0
Read Ch1
0
0
1
0
1
0
0
ReadCh2
0
1
0
0
1
0
0
Read Ch3
0
1
1
0
1
0
0
Load ChO TC Register
0
0
0
1
0
1
0
Load Ch1
0
0
1
1
0
1
0
Load Ch2
0
1
0
1
0
1
0
CS
Load Ch3
0
1
1
1
0
1
0
Read ChO TC Register
0
0
0
1
1
0
0
Read Chl
0
0
1
1
1
0
0
Read Ch2
0
1
0
1
1
0
0
Read Ch3
0
1
1
1
1
0
0
LO~d
1
0
0
0
0
1
0
1
0
0
0
1
0
0
Mode Set Register
Read Status Register
Part of this logic is a firstllast flip·f1op (FILl that
toggles with each I/O operation directed to a channel
register. This flip·flop controls which half of the
register is affected. It is essential that the state of
this flip·flop notbe lost through any of the following
conditions:
• Loading the mode set register when only the lower
half of a channel register has been accessed,
• Clocking CS while either I/OR or I/OW is active,
• Allowing the microprocessor to be interrupted
when only the lower half of a channel register has
been accessed,
• Not completing both halves of. a channel register
read or load sequence.
LOADING DMA ADDRESS REGISTERS
Each channel is assigned a separate 16·bit OMA
address register. This register is loaded with the
starting memory address for the next OMA operation
to be conducted on the corresponding channel.
Loading of a single OMA address register requires
two I/O write operations, with the chip selected by CS
and the register selected by system address lines
A3'-AO.
The OMA address information is presented to the
INS8257 via the system data bus in the following
manner:
DMAAddr
Register
Note 1: First IIOW. or /IDA loads or" reads low-order byte, second IIOW or 1I0R
toads or reads high-order byte.
0·122
First I/OW
LS Byte
D7-00
Second I/OW
MSByte
07-00
LOADING TC REGISTERS
Each channel is assigned a separate TC register.
This register's 14 least significant bits are loaded
with a value equal to one less than the number of
OMA cycles in the channel's next block transfer. For
example, if the next OMA operation for channel 0 will
require 32 (hex 20) OMA cycles, the value 31 (hex 1F)
should be loaded into channel O's TC register.
The terminal count information is presented to the
INSB257 via the system data bus in the following
manner:
TC
Register
Bits 14 and 15 of each TC register are loaded with
mode control bits for the corresponding channel.
There are three possible operating modes to be
specified by these bits. How they are implemented
depends on whether the INSB257 is part of a
standard (Isolated) I/O bus structure or whether a
memory-mapped I/O configuration is used. Figure 1
identifies the mode control functions of TC register
bits 14 and 15 for both I/O schemes.
First 1I0W
LS Byte
07-00
Second I/OW
MS Byte
07-00
LOADING MODE SET REGISTER
The contents of the mode set register are used to
individually enable/disable the four OMA channels
and to selectively implement four optional functions
in the INSB257. Mode set register bit functions are
identified in figure 2 and are described in the follow·
ing paragraphs,.
Bit
'NS8257
MEMRD -'MEMRD
MEMWR -MEMWR
_ _ iiOifii
iiOifii _ _ iiOViR
i7ifWR
Bit
14
Function
15
DMA Verify
a
DMAWrite
a
a
DMA Read
1
a
Illegal
1
1
I
'NS8257
MEMRg'/ORD
MEMWR
IIOWR
110 R0
MEMift)
iiOViR
MEM"Wif
Function
15
DMA Verify
a
DMAWrite
1
a
a
DMA Read
a
1
Illegal
1
1
Figure 1. TC Register Mode Control Bits
AUTO
LOAD
I I I I I I I
6
TC
STOP
0- NORMAL 0
5
EXTENDED
4
l
PRIORITY'
WRITE
I
2
0
CHANNEl ENABLE
CHl
CH2
CHI
DISABLE 0- NORMAL 0- FIXED
O-DISABLE
1 - ENABlE 1 - EXTEND I - ROTATING
1- ENABLE
I
CHO
Figure 2. Mode Set Register Bit Functions
1
Bit
14
7
1 - CHAIN
Loading the mode set register requires a single 110
write operation, with the chip selected by CS and the
register selected by A3-AO.
Memory Mapped 1/0
Bit
_. - MOO~ SET ·REGISTER BITS
"----
r
Isolated 1/0
DMA Channel Enables (Bits 3- 0)
These four bits can be individually set or reset by the
program in order to enable or disable their respective
channels. If the TC stop bit (mode set register bit 6) Is
set, the channel enable bit of the currently selected
channel is automatically reset after Terminal Count
(TC) goes true. This assures the disabling of a
channel after it completes its OMA operations. If the
TC stop bit is not set, the program should reset any
channel enable bit whose OMA address and TC regis·
ters are not currently valid.
Rotating Priority Option (Bit 4)
The OMA verify mode allows pseudo OMA cycles to
be performed in which no data is transferred. In this
mode, the INSB257 responds to OMA requests in the
same manner as in other modes, except that MEMR,
MEMW, IIOR and I/OW are inhibited. This mode
allows a peripheral to cycle through a block of data
for internal control or housekeeping purposes
without affecting memory.
In a OMA read cycle, the INSB257 issues MEMR in
order to read the contents of the addressed memory
location and I/O to write that same data byte into the
selected peripheral.
In a OMA write cycle, the INSB257 issues I/OR in
order to read the data byte presented by the selected
peripheral and MEMW to write that same data byte
Into the addressed memory location.
Loading of a single TC register requires two I/O write
operations, with the chip selected by CS and the
register selected by system address lihes A3-AO.
When this bit = 0 (e.g., following power on reset), the
pri,ority control logic resolves competing DMA
requests according to a fixed priority scheme. In this
fixed priority mode, channel 0 always has highest
priority and channel 3 always has lowest priority.
When mode set register bit 4 is set, the rotating
priority mode is selected. In this mode, 'the
completion of a DMA cycle will cause the channel
just serviced to be assigned lowest priority. All other
channels then move up one priority level. Channel 0
will always have highest priority after a reset or mode
set operation.
Extended Write (Bit 5)
The extended write option is useful when the
INSB257 is accessing a high-speed memory or 110
device whose Ready response is activated by the
leading edge of MEMW or IIOW. Ordinarily, the late
arrival of Ready would cause the INSB257 to insert a
0-123
"ICI
wait state into the DMA cycle, even thOugh the
device is capable of completing the transfer without
that wait state. This unnecessary wait state can be
avoided by use of the extended write option.
When the extended write biUbit 5) is set, the INS8257
generates MEMW or IIOW earlier in the DMA cycle.
This Rermits the memory or 1/0 device td issue its
Ready response earlier in the cycle, thereby avoiding
unnecessary wait states in the INS8257.
TC Stop Blc (Bit 6)
Setting this bit assures that a channel will be
disabled as soon as it performs the last DMA cycle in
a programmed DMA transfer. When Terminal Count
(TC) goes true at the end of a transfer sequence, the
channel enable bit of the currently selected channel
is 'automatically reset. This channel remains
disabled until its channel enable bit is set again by
the program.
The channel 3 register contents are copied into the
channel 2 registers during an update cycle, which
occurs right after the TC output goes true. Each t:ime
an update cycle begins, an update flag is set. This
flag is available to the program via bit 4 of the status
register. Following ie-initialization of .channel 2, the
first DMA cycle of the new data block begins. The
update flag is reset when this first DMA cycle is
completed.
'
To continue a block chaining sequence, the auto load
bit is left in the set state and the channel 3 registers
are programmed for the next data block. Before
loading new parameters into the channel 3 registers,
the update flag should be tested to be certain the
channel 2 update operation has been completed.
NOTE
DMA transfers can be performed on channel 3
when the auto load bit is set. However, any
parameters loaded into channel 3 registers will
be copied into channel 2 registers during the
next update cycle.
Auto Mode (Bit 7)
This mode provides the means for automatically
repeating block transfers or for chaining of multiple
block transfers, without requiring direct control by
the progra"1 between blocks. In this mode, the
channel 2 and channel 3 registers operate in tandem.
The contents of the 'channel 2 registers are used to
control the first DMA operation ..
The channel 3 regis~ers temporarily store the para·
meters required for the next block to be transferred.
Upon completion of the first DMA block transfer, the
contents of the channel 3 registers are automatically
copied into the channel 2 registers and the next
block is transferred under channel 2 register control.
Reading Status Register
Five status bits are available to the system at one
register address.
7
1
0
6
1
0
5
1
0
4
1
3
1
2
1
1
1
I
0
1
I
1" TC AT CHANNEL 0
' - - - - - - 1" TC AT CHANNEL 1
' - - - - - - - '1" TC AT CHANNEL 2
1" TC AT CHANNEL 3
1" UPDATE CYCLE
NOTE
The TC stop ,bit does not affect the channel 2
enable bit 'when in auto load mode.
A channel's TC status bit is set when tnat channel is
selected and the TC output is activated. Reading the
status register rese:ts all TC bits.
When the auto load bit is set, writing new parameters
into the channel 2 registers automatically loads
those same parameters into the channel 3 registers.
In this way, all parameters required for a repeat block
transfer are loaded in a single channel programming
sequence.
The update flag (bit 4) is set at the start of an update
cycle and resets at the end of the update cycle. The
update flag is also cleared by resetting the auto I;oad
bit and by resetting the INS8257. It is not cleared
when the status register is read.
If different parameters are required for the second
block transfer (for chaining block transfers), channel
3 can be programmed afte:r channel 2.
Reading the status register requires a single 1/0 read
operation, with the chip selected by CS and the
register selected by system address lines A3-AO.
0-124
~
.!!
-8
ec
Physical Dimensions
inches (millimeters)
-.$ti·. . .·
";,
• A trademark of National Semiconductor Corporation.
© 1978 National Semiconductor Corp.
Z
~
m
INS8259 Programmable Interrupt Controller
DP8224
CLOCK
GENERATOR
-
0-127
!
W;.;;I\f-oII----=---t
.'.,'.'.
1;;
3
3
S»
C'"
CD
5"
CD
~
c
"9.
Absolute Maximum Ratings
Ambient Temperature Under Bias .............. O·C to + 70'·C
Storage Temperature .................... - 65·C to + 150·C
Voltage on Any Pin with Respect to Ground ..... - 0.5Vto + 7V
Power Dissipation .................................. 1 Watt
Note: Absolute maximum ratings indicate 'limits beyond which
permanent dama!;le may occur. Continuous operation at these
limits is not intended and should be limited to those conditions
specified ,under DC Electrical Characterlsfics.
DC Electrical Characteristics
TA = O·Cto +70·C;Vee = +5V ± 5%,GND
- Symbol.
VIL
I
= OV
Parameter
Min
Input Low Voltage
-0.5
2,0
V1H
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
VOH.INT
Interrupt Output High Voltage
IIL(IRO-7)
Input Leakage Current tor IRo-7
IlL
Input Leaka\le Current for other Inputs
IOFL
Output Float Leakage
Icc
Vee Supply Current
Max
Typ
Unit
0.8
Test Conditions
V
V
Vee + 0.5V
0.45
= 2mA
= -400"A
V
IOl
2.4
V
IOH
2.4
3.5
V
V
IOH = -400"A
IOH = -50"A
-300
10.
"A
"A
VIN = OV
VIN = Vee
10
"A
p,A
VIN '= Vee to OV
± 10
100
Your
= 0.45V to Vee
mA
Capacitance
= +25·C; Vee = GND = OV
TA
Symbol
Parameter
Min'
Typ
Max
Unit
CIN
Input Capacitance
20
pF
CliO
I/O Capacitance
20
pF
-
/
0·128
Test Conditions
te = 1 MHz
Unmeasured pins to
ground
AC ,Electrical Characteristics
TA
= O·Cto
+70·C;Vcc
= +5.0V
± 5%,GND
= OV
,
Symbol
Parameter
Min
Max
Unit
Test Conditions
BUS PARAMETERS
READ
tAR
CS/Ao Stable before RD or INTA
50
ns
tRA
CSiAo Stable after RD or INTA
5
ns
tRR
RD Pulse Width
420
tRO
Data Valid from RD/INTA
300
tOF
tOF
Data Float after RD/INTA
200
ns
20
ns
CL
ns
CL
CL
= 100pF
= 100pF
= 20pF
-
WRITE
tAW
Ao Stable before WR
50
ns
tWA
Ao Stable afterWR"
20.
ns ,
tww
WR Pulse Width
400
ns
tow
Data Valid to WR (T.E.)
300
ns
two
Data Valid after WR
40
ns
OTHER TIMINGS
tlw
Width of Interrupt Request Pulse
100
ns
tiNT
INT t after IR t
400
ns
tiC
Cascade Line Stable after INTA t
400
ns
Timing Waveforms
Read Timing
~-,. ~
ERIP"Sm'fT
ADDRESS BUS
===:J
r
-l.
-'
~
~
...-:.--- TAR______.
~hj~
i7iiii
"'"=-
TRD_
DATA BUS
oTDF
HI-Z
HI-Z
~
_ _ TAW_
Write Timing
~r
mwmrn
ADDRESS BUS
DATA BUS
_TRA
"l~
=:) r
'-
.
(
TAW _ _
)~
--.
_TWA
~K=
. .---TDW~ _T~D-'
iiifW
~
~TWW~
0-129
-
•.
.-
Timing Waveforms (cont'd.)
~
QtherTiming
,,3tT_~~
~
INT
________\~
_ _ _ _ _ _ _ __
INTA
DS
HI~Z
eO~2
NOTE: INTERRUPT REQUEST MUST REMAIN "HIGH" (AT LEAST) UNTIL LEADING EDGE OF FIRST
INTA~
Initialization Sequence
OATA BUS - - - - - , .
STORE BYTE
L
STORE BYTE 2
STORE BYTE 3
Read Status/Poll Mode
!
\
!
\
/
\
\1
OATA BUS
HI~Z
X
oew3
X
HI~Z
D-130
X
I
OATA
X
HI-Z
INS8259 Block Diagram
INTERNAL
BUS
INS8259 Functional Pin
Description
Write (WR): When low, allows the microprocessor to
write control words (ICWs and OCWs) to the INS8259.
The following describes the functions of all INS8259
input/output pins. Some of these descriptions refer
to internal circuits.
AO: This input is used in conjunction with the WR
signal to write command words Into specific
command registers and with the RD signal to read
specific status registers. AD can be controlled via
one of the microprocessor address lines.
INPUT SIGNALS
Chip Select (CS): When low, the device is selected,
enabling communication between the INS8259 and
the microprocessor.
Read (RD): When low, allows the microprocessor to
read contents of Interrupt Request Register (IRR), In
Service Register (ISR) or Interrupt Mask Register
(lMR) or the BCD value of the current interrupt level.
Interrupt Acknowledge (INTA): This input is generally
provided by the CPU group's System Controller
element (e.g., INS8228). Each INT is acknowledged by
a sequence of three INTA pulses, which causes the
INS8259 to output a three-byte CALL instruction onto
the Data Bus.
0-131
INS8259
Interrupt Request (lR7 -IRa): These eight inputs are
used by external circuits to request servicing by th.e
CPU. A low-to-high transition on one of these lines
represents a new interrupt request from the circuit_
controlling that line. Each positive transition on the
IR lines causes the INS8259 to issue a separate interrupt to the microprocessor. The IR line must remain
high through the first INTA pulse or the INT line will
go .low. Concurrent interrupt requests are resolved
according to their relative positions in the priority
scheme. Typically, an active (high) IR input is reset by
the interrupt service routine associated with. that
line.
.
Program~ing
Information
Two types of command words are used to program
the INS8259. These are:
• Initialization Command Words (ICWs) A
sequence of two or three ICWs is required to'
prepare the INS8259 for operation. Two words are
used if a single INS8259 Is being initialized. A
three-word sequence is used if a master/slave configuration is being initialized. See figure 1 for an
illustration of this sequence. Each ICW is timed by
a separate WR pulse.
• Operation Command Words (OCWs) - These
command words are used to specify various operating characteristics of the INS8259 and to read
the status of certain registers.
Slave Program (SP): This control input is used in
systems having cascaded INS8259s, where one
INS8259 operates as the master and all others
operate as slaves. A high level at the SP input
appOints that INS8259 as master, while a l.ow level
assigns the role of slave.
Figure 1 summarizes the bus controls needed to
output command words to the INS8259 and to read
INS8259 status.
OUTPUT SIGNALS
Interrupt (lNT): This output is applied to the microprocessor's interrupt input (e.g., pin 14 ofINS8080A).
Operation
INPUT/OUTPUT SIGNALS
Data (07 - DO) Bus: This bus, which comprises eight
TRI-STATE input/output lines, prOvides bidirectional
communication between the INS8259 and the CPU.
Command words, status words and CALL instructions are transferred over these lines.
Cascade (CAS2-CASO): These three lines are used in
systems having cascaded INS8259s. The master
INS8259 outputs the three-bit ID ofa slave device on
CAS2-CASO in order to select that slave for interrupt
servicing.
READ
0
0
1
0
(Note 1) IRR, ISR or
Interrupt Level to Data
Bus
1
0
1
0
IMR to Data Bus
WRITE
0
1
X
1
0
0
Data Bus to ICW1
0
0
0
1
0
0
Data Bus to OCW2
0
0
1
1
0
0
Data Bus to OCW3
1
X
X
1
0
0
(Note 2) Data Bus to
OCW1, ICW2, ICW3
Pin Configuration
Data Bus to Hi-Z
Data Bus to Hi-Z
cs
vcc
WR
AO
jfii
INTA
07
IR7
06
IR6
D5
IR5
04
IR4
OJ
IRJ
·02
IR2
01
IR1
DO
IRO
CASO
INT
CAS 1
SP
GNO
Notes:
1. Selection of IRR, ISR or Interrupting Level controlled by
OCW3 written prior to the Read operation.
2. Proper sequence set by on-Chip sequencer.
Figure 1. Basic Control for INS8259 I/O Operations
INITIALIZATION COMMAND WORDS (ICWs)
Figure 2 summarizes the command format for ICW1,
ICW2 and ICW3. There are two variations of the ICW3
format,. one for the master device and one for the
. '
slaves.
CAS2
Figure 3 describes
sequence.
0-132
the
INS8259
initialization
I
AO
01
AO
A1
06
05
A6
A5
04
03
02
01
DO
0
ICWI
1
DEFINED
AS
0
' - - LOWER ROUTINE ADDRESS BITS - - '
(WHEN CALL ADDRESS INTERVAL
IS 8 BYTES, A51S FIXED BY INS8259.
WHEN 4 BYTES, FIXED BY PROGRAM)
AD
DEFINED
AS
I
DEFINED
AS
I
02
01
DO
AIO
A9
AB
04
03
AI5
AI4
AI3
AI2
All
DEFINED
AS
0
1
01
06
05
04
03
02
01
DO
S1
S6
S5
54
S3
S2
SI
SO
I
SLAVE LOCATIONS
o -IR INPUT HAS NO SLAVE
I - IR INPUT HAS SLAVE
'1
06
05
04
03
X
X
X
X
DON'T CARE
Icm
I
UPPER ROUTINE ADDRESS BITS.
X
DEFINED
AS
I
0- MORE THAN
liNE INSB259
IN SYSTEM
I-SINGLE
INSB259IN
. SYSTEM
05
01
1,
CALL
ADDRESS
INTERVAL
O·B BYTES
1-4 BYTES
06
1,
AO
DEFINED
AS
0
01
1,
AO
DEFINED
AS
I
I
"
02
01
DO
102
10,
100
1
I
ICW3
(MASTER)
ICW3
(SLAVE)
1
I
SLAVE 10
(MUST EQUAL THE REQUEST LINE OF MASTER
TO WHICH THE SLAVES INT OUTPUT IS TIED)
~ ~-r~~-r~", ~-r~~-r;02 ~-L~~~C~~~-L~~
Figure 2. Initialization Command Word Format
0-133
1-.1
When an ICW1 is received, the follo,wing functions
are performed i[l the INS8259.
ICW3 Is used only If a master/slave configuration Is
being initialized. The ICW3 Issued to the master
INS8259 Identifies which IR Inputs have slaves
attached. Each bit position corresponds to a
separate IR input (00 = IRO and 07 = fR7). For each
IR input that has a slave attached, the corresponding
ICW3 bit is set to 1. Those IR positions without a
slave are Identified by Os In the corresponding ICW3
bit positions. The ICW3 Is also used to assign threebit identi,flers to the slave INS8259s. A separate ICW3
Is sent to each slave with a unique 10 ,contained in
bits 00- 02. The 10 must correspond to which master
IR 1,lne the slave's INT is connected to. Later, when a
slave's Interrupt request Is selected for servicing, the
master INS8259 automatically Issues byte '1 of the
CALL sequence and sets the 10 assigned to that
slave on the CAS2-CASO lines. This enables the
specified slave to release bytes 2 and 3 of the CALL
sequence.
• The edge sense circuit is reset, which prepares it
to detect a positive transition at an IR input.
• The Interrupt Mask Register (lMR) is cleared.
• The IR7 input is, assigned lowest priority (I.e.,
priority level 7).
• The special mask mode and status read flip·flops
are reset. ICW1 also contains three types of programming information.
- Single INS8259 or Master with Slave(s)
configuration, as set by 01 of ICW1.
- Four- or eight·byte CALL address Interval, as
set by 02 of ICW1.
- If the four-byte CALL Interval Is used, bits
A5-A7 of the CALL address are specified by
05-07 of ICW1 and bits AO-A4 are provided by
the INS8259. If the eight-byte Interval Is used,
bits A6 and A7 are specified by bits 06 and 07
of ICW1" while bits AO-A5 are provided by the
INS8259. Refer to table 1.
The contents of ICW2 specify bits A8-A15 of the
CALL address.
AD
G
ICWl
ICW2
NO
Icwa
READY FOR OPERATION
IN FUllY NESTED MODE
Figure 3. Initlallzallon Sequence
0-134
Table 1.
=4
Interval
=8
Interval
Lower Memory Routine Address
07
06
05
04
03
02
01
DO
07
06
05
04
03
02
01
DO
IR7
A7
1
1
1
1
a
a
A7
A6
1
1
1
a
1
a
a
A5
A5
1
a
a
1
a
a
a
a
a
1
a
a
a
a
A7
A7
A6
A6
A5
A5
a
a
a
a
A5
a
a
a
A7
A7
A6
A6
a
1
A6
a
a
a
1
a
a
a
a
a
a
a
a
a
A7
a
a
a
AS
A6
A6
A6
a
a
A6
A6
A7
A7
A7
A7
a
1
A7
A7
a
a
1
1
1
1
A5
a
a
A6
A6
a
a
A7
A7
a
1
a
a
a
a
A7
A5
A5
1
IR6
IR5
IR4
A6
A6
IR3
IR2
IR1
IRa
D7
AD
I
1
DEFINED
AS
1
I
I
0
DEFINED
AS
0
0
DEFINED
AS
0
I
M7
I
05
I
M6
07
R
I
PRIORITY
ROTATE
I
I
I
DON'T
CARE
ESMM
I
END OF
INTERRUPT
0- NO ACTION
1 - RESET
HIGHEST PRI<
ORITY BIT OF
ISR
I
SMM
l
0
0
1
0
I
No Action
M3
0
DEF<'NED
AS
0
I
0
DEFINED
AS
0
02
I
I
DEFINEO
AS
0
1
~
Reset
Set
Special speCi~11
Mask Mask
OEFINED
AS
1
I
M2
DO
I
M1
I
I
MO
DCW1
I
DO
01
L2
a
a
I
L1
I
Lo
DCW2
' - - - PRIORITY LEVEL CDDE---.I
BCD Level to be Reset
or Put into lowest Priority
0
0
0
1
1
0
0
2
0
1
0
D2
03
1
a
01
02
LO
Ll
L2
I
a
a
a
0
0
1
a
a
03
D4
SMM
0
1
I
INTERRUPT MASK
0- MASK RESET
1 - MASK SET
D5
' - SPECIAL MASK MODE.....I
ESMM
M4
1
a
03
04
EOI
06
X
I
05
SEol
D7
04
M5
06
SPECIFIC
END OF
INTERRUPT
0- NO ROTATE 0 - NO ACTION
1- ROTATE
1 - USE BITS
L2, L1, Lo
AU
I
06
\
AD
1
a
a
1
I
p
4
0
0
1
3
1
1
0
D1
I
ERIS
5
1
0
1
6
,
0
1
1
1
1
1
DO
I I
RIS
oeW3
/
\
POLLING
1
1
CALL address is released. No interrupt will be issued
for an interrupt request so long as a higher level
interrupt is in service.
The polled mode is used when the program assumes
full control of device servicing and does not allow
processor interrupts.
As part of the completion of an interrupt service
routine, the microprocessor must issue an End of
Interrupt (EOI) command, which resets the highest
levellSR bit. After an ISR bit resets, the ISR or IRR bit
then having the highest priority is serviced. The EOI
Is issued by means of an OCW2, in which bit 05 = 1.
To maintain the operating characteristics of the fully
nested mode, bit 07must equal O.
ROTATING PRIORITY MODE
In the rotating priority mode, an interrupt level is
automatically assigned lowest priority immediately
after it is serviced. Highest priority then passes io
the next lower interrupt level. For example, when
servicing of interrupt level 3 is completed (lSR bit 3 is
reset), interrupt level 3 is assigned lowest priority
and interrupt level 4 assumes highest priority.
To operate in rotating priority mode, the EOI issued
at the end of each service routine must have bit 7 and
bit 5 set to 1.
.
The lowest priority can be program·assigned by
means of an OCW2. The OCW2 used to make a
specific priority assignment would need to be in the
range (hex) CO-C7. For example, if the OCW2 value is
C3, interrupt level 3 is assigned lowest priority and
level 4 is given highest priority.
INTERRUPT MASKING AND SPECIAL MASKING
OCW1 can be used to mask off individual interrupt
levels. This command is specified byAO = 1. Each
data bit In OCW1 controls a separate bit in lhe
Interrupt Mask Register (lMR). When an IMR bit is set,
the corresponding !;lIt position is masked at the IRR
and, when in special mask mode, at the ISA.
If an ISR bit is already set at the time it is masked,
the lower priority interrupts willi-emain inhibited by
the masked interrupt level. These lower priority levels
can be enabled by an EOI command that resets that
ISR bit or by issuing a special mask command.
The special mask command is issued by means of an
OCW3, in which bit 05 = 1 and 06 =1. This sets the
special mask mode flip·flop, which enables all
unmasked Interrupt levels. These remain enabled
until the special mask mode flip-flop is reset by an
OCW3 with bit 05 = 0 and bit D6 = 1.
In this mode, the microprocessor disables Its inter·
rupt Input and, when it wishes to service a device
attached to the INS8259, it issues an OCW3 with bit
02 = 1. This' is followed by ariRO pulse with AO = O.
If any IRR bits are set when the RO pulse is received,
the INS8259 sets the ISR bit corresponding to the
highest priority level requesting service. It also
identifies that priority level on the data bus in the
fonowing manner:
07
06
05
04
03
02
01
DO
I I - 1- 1 - I -IW21 W1 1WO 1
I
WO-2 - BCO code of the highest priority level
requesting service.
I-
Equal to a "1" inhere.is an interrupt.
This mode is useful if there is a routine command
common to several levels - so that the INTA
sequence is not needed (and this saves ROM space).
Another application is to use the poll mode to
expand the number of priority levels to more than 64.
END OF INTERRUPT (EO I) AND SPECIFIC END OF
INTERRUPT (SEOI)
.
The EOI command is used in the fully nestedmodl[l to
reset the appropriate ISR bit when that interrupt
level's. service routine Is concluding. The nonspecific EOI command always resets the highest
level ISR bilthat is currently set. For this reason, it is,
reliable only in a fixed priority scheme, such as the
fully nested mode. When priority assignments are
changed from the standard order (I.e., IR7 = lowest),
the specific EOI command must be used. This
-command contains the BCO value of the interrupt
level that is to be reset.
Both specific and non-specific EOI are issued by
means of an OCW2. For the non-specific EOI version,
bit 05 of the command is set to 1 and bit 06 is O. For
the specific EOlversion, bit 050f the command is set
to 1 and bit 06 is set to 1. In the specific EOI
command, the BCO value of the ISR bit to be reset is
contained in command bits 00-02.
READING INS8259 REGISTERS
Four types of status can be read from the INS8259:
the contents of IRR, the contents..of ISR, the contents
of IMR and the BCO value of the interrupt level
requesting service.
The microprocessor reads the contents of IRR by
issuing an OCW3, in which bit DO 0 and bit 01
1.
This Is followed by a RO pulse, during which the
INS8259 places the IRR status on the data bus with
the IRR low order bit (0) present on DO and the IRR
high order bit (7) present on 07. The contents of ISR
are read in the same manner, except that OCW3 bit
DO is set to 1 as well as bit 01. The contents of IMR
can be read by setting AO
1 and Issuing a REi
pulse.
=
contain the slave address code from the trailing edge.
of this pulse until the trailing edge of the third lNTA
pulse. This allows the corresponding slave to release
the two-byte service routine address during the
second and third iiifi'A pulses.
=
Because the CAS lines default to 000, no slave
should be connected to IRO on the master unless
master request Inputs IR1 through IR7 are connected
to slaves.
=
The BCD value of the interrupt level requesting
service Is placed on the data bus in response to a poll
command. This technique was described earlier
under Polled Mode.
Each INS8259 in the system must follow its own
initialization sequence and can be programmed to
operate In any mode. Two EOI commands must be
Issued: one for the master and one for the slave.
CASCADE OPERATION
A typical cascading system is shown In figure 5.
The EOI allows the respective request input to
generate a new interrupt. To allow a slave to have
nested Interrupts, the master should be sent an EPI
as soon as possible in the service routine.
Once a slave line Is activated and later acknowledged, the INS8080 CALL code is released by the
master during the first iiifi'A pulse. The CAS lines will
~
~
MICROBUS
---------- fo-.- --- ------- -- ------
rl
r-.
B
AO
DATA CONTROL INT
BUS
CASU
INS8259
ICAS 2 I-
SLAVE 2
II'
TO
CPU
GROUP
l:r AO
CAS1
DATA CONTROL INT
I
B
BUS
CAS 0
IN58259
CASt
CAS 1
CAS2
CAS 2
SLAVE 1
DATA CONTROL INT
BUS
CASU
INS1259
MASTER
II'
'!1"
.[ !!!.t 11 !t
t
AO
1 UH!!!!
Jc
1 t!!t!!
(INTERRUPT REQUESTS)
Figure 5. Cascads Opsratlon
Instruction
AO
D7
De
D5
D4
D3
D2
D1
DO
O......lIon DaocripUon
A7
A7
A7
A6
A6
1
1
0
1
1
1
0
0
0
Byte 1 initialization, format = 4, single.
Byte 1 InitiaUzation. format = 4, not single.
A6
A5
A5
A5
1
ICW1D
0
0
0
0
A6
A5
1
0
0
ICW2
1
1
2
ICW1A
ICW1B
3
4
ICW1C
5
6
ICW3M
7
ICW38
8
9
0
= 8, single.
= 8, not single.
0
1
0
Byte 1 Initialization, format
0
0
0
Byte 1 Initialization, format
119
A6
Byte 2 Initialization (Address no. 2).
"7
A15 A14 A13 A12 A11 A10
S4
'0
53
82
81
master.
81
Byte 3 initialization -
slave.
M4
M3
M1
MO
Load mask reg, read mask reg.
0
0
0
0
L2
a
L1
a
La
Non-specific EOI.
1
M5
1
1
82
M2
SO
SO
Byte 3 Initialization -
a
1
0
1
a
0
0
0
a
Ro1ato at EO! (lIu10 Mode).
1
1
1
0
a
L2
L1
La
'·1
1
87
S6
0
85
0
OCW1
1
M7
M6
OCW2E
OCW25E
0
0
0
0
10
a
11
OCW2 RE
12
OCW2 R5E
0
0
a
0
Specific EOI, L2, L1, LO coda of ISFF to be
reset.
13
OCW2 R5
a
1
1
14
15
OCW3P
OCW3RIS
0
-
0
16
OCW3 RR
17
OCW35M
a
a
18
OCW3R8M
a
Not••:
1. In the master m098
2. (-) = don't care.
a
-
SP pin::
0
0
a
a
1
1
L2
1
0
0
0
a
a
0
a
a
1
a
1
1
0
1
0
1
a ..
0
1
a
L1
a
1
1
0
0
LO
Rotate at EOI (Specific Mode). L2. L1. LO.
code of line to be reset and selected as
" bottom priority.
L2. L1, LO code of bottom priority line.
a
1
Poll mode.
Read IS register.
0
0
Read requests register.
Set special mask mode.
0
Reset special mask mode.
1; in slave mode SP = 0.,
Figure 6. INS8259 Instruction Set
0-137
I-ICI
tD
e-
Physical Dimensions
Inches (millimeterS)
c
8
a
E
CD
--
1
0.530
C
CD
:is
ca
E
E
r ________
0.045
(:~~~
i1.1iJj
MAX
r
-k========~~~~~T~~~~,-~-t· ~
11.27-0.2541
~-t=~
..
t!
---1
~~~ (:":~:I
1
(0.451 '0.0511
I-
MIN
28-Lead Ceramic Dual-In-Llne Packaga (D)
Order.Numbar INS8259D
NS Packaga Number D28A
z
(1.062
11.575)
'"
I'INND.lINDENT~.
1
1
r-
0.030
iO.7621~
_ 0 ..600-0.620 __ ~."_
(15240-15.148)
~
Z
3
4
5
B
1
_
0.009-0.015
l.--.-~-------:-l
(15.815
~:~~~)
10.229-03811
9
lQ
11
1l
13
1.
0.050
.
~.
.
.(1:"270)
0.130=0.005)
TVP
13.302~0.1211
=Wt~I··I
0625 ,o.025
8
I
1I,1175'0.Q15"-1
IUD5 '11.3811
f--
,~I--'H4111
TVP
I
0.100
L
-rJ.o
--11--
0.0111'11.003
(0.457 '0.016)
~sffii8J
(3.m) MIN,
MIN
28-Lead Plastic Dual-ln-Llne Packaga (N)
Order Number INS8259N
NS Package Number N28A
Nalional Semieondvclor
Corporation
NaUona! Semiconductor GmbH
8000 Mllnchen 21
29QOSemiconductor Drive
61f2EIsenheimerstrasse
SantaCtara.Calilorma95051
Te!: (408) 737·5000
TWX. (910)339-9240
~estGermany
Tel. 089/9 15027
Telex, 05-22772
NS Internalionallnc., Japan
Miyake BUlldmg
t-9Yotsuya,ShtnJuku-kuI60
Tokyo. Japan
Tel. (03)355-3711
TWX 232-2015 NSCJ-J
NS Eleclronics (Hong Kong) Lid.
BthFloor,
Cheung Kong ElectrcllIc Bldg
4 Hmg YIp Street
'
KwunTong
Kowfopn, Hono Kong
"Tel'3-411241-S
Tele~: 73866 NS£HK HX
Cable' NATSEMI
NS ElettronitsDo Brasil
Avda BngadelroFaria lima'S44
11 AndarConjunto 1104
Jardlm Paullslano
Sao Paulo. BraSil
Tele)(: 1121008 CABINE SAO PAULO
NS Electronics ptr. Lid.
Cnr. Stud Rd. & Min. Highway
Bayswater, Viclorla 3153
Australia
Tel: 03-729-6333
Telex. 32096
National ooes nol assume any responsibility for use of any circUitry described; no Circuit patent licenses are Implied; and National reserves the nght. at any time without notice, to change said CirCUitry.
D-138
~National
MARCH 1978
~ Semiconductor
INS829811NS8298E 8080A LLL BASIC Interpreter
General Description
Features
The INS8298/1NS8298E is a 65k MAXI-ROMTM*,
organized into 8192 8-bit words, that is preprogrammed
ore Laboratory (LLL)
with the 8080A Lawrence
BASIC Interpreter. Unp
versions of the
INS8298 and INS8298E are t
pin,800ns
access) and I NS8364E/MM5216
access).
respectively. Both the INS8298 and
complete TTL compatibility and single
supply. Three chip selects controlling TRIoutputs allow for memory expansion.
• Reduces software effort in microcomputer applications
The 8080A LLL BASIC Interpreter operates with the
INS8080A microprocessor system to provide a high-level,
easy-to-use language for performing both control and
computation functions in the INS8080A. Designed for
use in data acquisition and control applications, the LLL
BASIC Interpreter enables the user to write and debug
a program on-line. The interpreter executes source code
statements directly, thus avoiding the need to translate
into machine language. This approach has the advantage
of easier source code manipulation (because the source
is always available). and instant revision of the program
when errors are detected.
• Provides easy source code manipulation and instant
program revision
• Allows immediate-mode execution of program statements to assist program checkout
Ineludes floating-point arithmetic package to provide
I computational capability
. h-speed, machine-language sub-
Available as INS8298 (28 pin, 800 ns access) and
INS8298E (24 pin, 450 ns access)
• MICROBUSTM* compatible
* A trademark of National Semiconductor Corporation.
General System Configuration
R....
411 1412 CLOCKS
'NSl2BI
CONTROL SIGNALS
(RESET. READV)
INSlII8DA
MICROPROCESSOR
BASIC
INTERPRETER
f
HEXADECIMAL
DEBUGGER
(HOT)
.....- - -.....'""1
@ , 978 National Semiconductor Corp.
0-139
The LLL BASIC Interpreter is used to translate, debug,
and execute user-written ASCII programs in read/write
memory (RAM). Each statement is interpreted from its
ASCII BASIC format, and then executed line-by-line.
An LLL BASIC Compiler, written in FORTRAN, will
soon be available in the pubnc~omain.· (See figure 1.)
The BASIC Interpreter accepts both program statements
and control commands. Program statements describe
(to the BASIC Interpreter) operations to be performed
on program data. A program statement preceded by a
line number is ·inserted into the program for later execution at a spot determined by the line number. If no
nne number precedes the statement, it is executed
immediately and then discarded. This latter mode,
known as "immediate" or "direct," is especially valuable
during program checkout. Contml commands specify
actions that alter the status of the us~r's program; for
example, they direct the execution, saving, and retrieval
of programs. Program, statements are summarized in
table 1; control commands are summarized in table 2.
The BASIC Interpreter is located in ROM from 100016
through 2FFF16. BAsIC assumes that its RAM starts
at location 3DD016. The ll1emory map is shown in table
3. All I/O routines used by the INS8298 are located in
the upper 256 bytes of the address space so that a simple
address decoding circuit can allow the substitution of a
special user-supplied I/O package, if necessary. As an
alternative scheme for allowing the user to tailor I/O to
h is own needs, entry poi nts to the interpreter are
provided that allow the page"zero initialization program
to channel all BASIC 1/.0 through ,its own routines.
contents. HDT is called 'from the BASIC Interpreter to
help debug user-developed software, Input and output
data representation is in hexadecimal format. In addition
to the 'usual debugging capabilities, HDT also has
commands to perform the following functions:
• Test a specified range of memory locations
•
Load programs in hexadecimal, NSC, and LLL binary
formats
• Save the contents of a specified range of memory
locations
In addition to the features summarized previously, LLL
BASIC has many capabilities found in other standard
BASIC systems (see tables 1 and 2). However, 'LLL
BASIC does not include built-in operations as intrinsic
functions, e.g., trigonometric or string-manipulation
functions.' Also, LLL BASIC does not permit arbitrary
arithmetic expressions beyond those of the form:
variable op variable
where the first variable in the expression may be preceded by a minus (-); opmay be a plus (+), minus (-),
asterisk' (*) for multiplication, or slash (/) for division;
and either variable can be an identifier, function, Dr
number.
*For additional information, contact:
Argonne Code Center
A hexadecimal debugging routine (HDT) is also,available
on the INS8298 ROM. HDT allows the user to examine
internal registers and memory locations and modify their
Argonne National Laboratory
9700 South Cass Avenue
Argonne, Illinois' 60439
USER'S
ASCII .
PROGRAM
(RAM)
INS8080A
CPU
BASIC
COMPILER
(FORTRAN)
COMPILED
CODE
(PROM OR
ROM)
I
I
___.!A~~~T~~~_____ J
Figure 1. Operation of the LlL BASIC Interpreter and Compiler with the INS8080A
0,140
Table 1. BASIC Statements
1-
Statement
Function
CALL
Calls user·written assembly·language routines.
DIM
Declares a one·dimensional array. (Indexing is from zero.)
'END
Terminates a program and returns control to BASIC.
FOR
Causes program to iterate through a loop a designated number of times.
GET expression
Reads input data from a specified port.
GOSUB nn
Transfers control to a subroutine beginning at line nn.
GOTO nn
Transfers control to line nn.
I F expression THEN nn
Transfers to line nn if the condition of the expression is met.
INPUT list
Allows the user to supply numeric data to a program directly from the terminal.
LET identifier = expression
Assigns the value of an expression to the identifier on the left side of the equal sign.
NEXT
Signals the end of a loop.
PRINT
Allows numeric data and character strings to be printed on the terminal.
PUT expression
Writes output data to a specified port.
REM
Allows comments to be inserted in the program listing.
RETURN
Returns control to the line after the last GOSUB.
STOP
Suspends program execution and returns.
Table 2. BASIC Commands
Command
Function
CONTROLIH (backspace)
Deletes the previous character typed during input.
CONTROLIS
Interrupts program during execution and returns to immediate mode.
DEBUG
Transfers control to the Hexadecimal Debugger program (HDT).
LIS,.
Prints out all or part of a program at the terminal.
PACK
Frees memory locations in RAM to allow the user more working space.
PLiST
Punches paper-tape copy of a program.
PTAPE
Reads in paper-tape copy of program using high-speed reader.
RUN
Begins execution of the program currently in memory.
SCR
Erases the program in memory
Table 3. Memory Map for BASIC Interpreter
ROM Address (hex)
Function
1000 - 100B
BASIC entry points for initialization.
1009 - 27FF
BASIC Interpreter.
2800 - 2EFF
Hexadecimal Debugger (HDT) and loaders.
2FOO- 2FFF
System I/O routines for INS8251 USART (ports EC and ED).
RAM Address (hex)
Function
3DOO - 3DFF
BASIC RAM scratch area (buffers, variables, etc.).
3EOO upward
BASIC user program space.
Top of RAM downward
BASIC stack area.
Chip Selects
CSl
Active low (0).
CS2
Active high (1).
CS3
Active low (0).
I-ICI
D-141
Block and Connection Diagrams
Vee
AI
AD
NC
01
A2
02
A3
0'
O.
A4
01
A1
02
os
A.
A2
D'
D.
8192X8
A4<>--I>--i
ROW DECODE
ROM
AS
O'
CSi
07
CSl
O'
CS3
A7
A12
OUTPUT BUFFER
'ARRAY
••
17
AS
13
16
A.
14
IS
AIO
Al1
12
NC
GNO
07
.,
A7
A'
.,
AIO
A1Z
Al1
NOTE: CS2 AND CS3 NOT
AVAILABLE IN INS8298E.
Absolute Maximum Ratings
m
CSi
CS2
Vee
A6
AB
AS
A'
A4
.12
A3
A2
INS8298E
AI
AD
m
Dl
20
ffi
19
AIO
18
Al1
17
0'
16
07
D'
D2
10
IS
D'
11
GND
12
"
13
os
D4
Chip Selects
(Note 1)
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
A7
-0.5V to +6.5V
O°C to +70°C
-65°C to +150°C
CS No.
Active Level
Pin No.
I NS8298
1
2
3
lW
+300°C
21
20
0
1
0
19
I NS8298E
1
0
20
DC Electrical Characteristics
(TA within operating temperature range, VCC = +5V ± 5%, unless otherwise specified.) See AC test circuit and switching time
waveforms.
Parameter
(Note 3)
Conditions
Min.
= OV to VCC
ILl
Input Current
VIH
Logical "1" Input Voltage
2.2
VIL
Logical "0" Input Voltage
-0.5
VOH
Logical "1" Output Voltage
IOH
= -200 11A
VOL
Logical "0" Output Voltage
IOL
= 3.2mA
ILOH
Output Leakage Current
VOUT
= 4 V, Chip Deselected
ILOL
Output Leakage Current
VOUT
= 0.45V, Chip Deselected
ICCl
Power Supply Current
All Inputs
Open
VIN
Typ,
(Note 4)
Max.
10
I1A
VCC+1.0
V
0.6
2.4
= 5.25V, Data Output
0-142
Units
V
V
100
0.4
V
10
I1A
-20
I1A
130
mA
Capacitance
Parameter
(Note 3)
Conditions
Min.
Typ.
(Note 4)
Max.
Units
CIN
Input Capacitance (All Inputs)
VIN = OV, T A = 25°C, f = 1 MHz,
(Note 2)
7.5
pF
COUT
Output Capacitance
VOUT = OV, TA
(Note 2)
15.0
pF
= 25°C, f = 1 MHz,
AC Electrical Characteristics
Vee = +5V
(TA within operating temperature range,
waveforms.
± 5%; unless otherwise specified.) See AC test circuit and switching time
Limits
INS8298
Typ.
Max.
Min.
(Note 4)
)
Conditi!,ns
Parameter (Note 3)
tA
Address Access Time
tAC
Chip Select Access Time
See AC Load Circuit. All times except
tOFF measured to 1.5 V level with tr
and tf of input < 20 ns (figures 2 & 3),
tOFF TRI·STATE output level
measured to less than ±20 flA output
tOFF Output Turn OFF Delay
Cycle Time
tc
tAS
1300
550
current.
Address Set·Up Time
Referenced to Chip
Select
INS8298E
Typ.
Min. (Note 4) Max.
Units
450
150
800
450
250
150
ns
ns
150
250
150
ns
ns
450
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Nota 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used: logical "1" "" most positive voltage level,logical "0" "" most negative voltage level.
Note 4: Typical values are for T A"" 25°C and nominal supply voltage.
AC Test Circuit and Switching Time Waveforms
~
5V
TEST
POINT
Rl
100,F'
J
.....
...."
1.66k
I-
25k "
";1-
...!:-
,
"
I-
'::"
*INCLUDES JIG CAPACITANCE.
r--
2.4V
ADDRESS
0.4V
te
2.4V
1\ 1.5V
CHIP SELECT
0.4V
OUTPUT
I.. tAS"
tOfF
TRI'STATE®
-..t
2.4V
~
Ir1.5V
1.5V
&
ADDRESS
D.4V
2.4V
CHIP SElECT
~>-
O.4V
OUTPUT
DATA VALID
tAC
=x
~te~
~t~
TRI.STATE®~DATA INVALID~ DATA VALID
Figure 3. Address Follows Chip Select'
Figure 2. Address Precedes Chip Select
0·143
.
IIIC.
Physical Dimensions
inches (millimeters)
1.400
-(35.56)
MAX
{13.462J
.,--;rTrr"Ti"rr.rr"1rrrn=i7ri'ii'n'iT'iior.,..n;;nr,;r='
II
1%
13
14
(5.08)
MAX
1:--(1~:;41---:,l
I
~__
0.050 ±O.OtD
(l.2l !0.254)
. _~+TVP1:: :1
!r
0625 to.U25.
.
_I
0.200
0.610
.
0.015
-. (1S.an ~m-~
--,
---iI
0.12S
(3.115)
MIN
28-Lead Cavity Dual-In-Line Package (DI
Order Number INS8298D
NS Package Number D28A
PIN NO.1
WENT''-
24-lead Cavity Dual-In-Line Package (DI
Order Number INS8298ED
NS Package Number D24A
National S.lfticonductor
c;orporatloJl
2900 Semiconductor Driye
Santa Ctara. California 9.5051
Tel: (408) 737·5000
TWX: (910,339-9240
National S.mltonduCior GmbH
as IlIftm.lioaallnc., Japan
NS Electronics (Hong 'onul ltd.
SOOO MUnchen 21
Eisenheimerstrasse 6112
Miyake Building
1-9 Yotsuya, Shinjuku-ku 160
West Germany
Tet: 08919 15027
Telex: 05·22772
Tet: (03) 355·3711
TWX: 232-2015 NSCJ-J
8th Floor,
Cheung: KOIIO Electronic Bldg.
4 Hing Yip Street
Kwun Tong
Kowloon, Hong Kong
Tel: 3-411241·8
Telex: 73866 NSEHK HX
Cable: NATSEMI
Tokyo, Japan
HS EIect,."ic, 00 Brlsil
Avila Brigadeiro Faria Uma 844
11 Anda~,Gonjunto 1104
Jardim Paulistano
Sao Paulo, Bras!1
Telex: 1121008 CABINE SAO PAULO
HI EltCl,.,,!,. Pty. UII.
CnL Stud Rd. & Min. Highway
8ayswaler, Victoria 3153
Australia
Tel: 03-729-6333
Tel.x: 32096
National does not assume any res'ponsibility for use of any circuitry described; no circuil patent licenses are Implied: and National reserves the right. 'at any tIme Without notice, to change said circuitry
0-144
~National
~ Semiconductor
MARCH 1977
Pub. No. 42630545Hl01A
INS1671 Asynchronous/Synchronous Transmitter/Receiver
General Description
The INS1671 is a programmable Asynchronous/Synchronous Transmitter/Receiver (ASTRa) chip housed' in
a standard, 40-pin dual-in-line package. The chip, which is
fabricated using N-channel silicon gate MaS technology,
provides a serial data input/output interface in a busstructured system. The chip is capable of full duplex
operation with synchronous or asynchronous data
communications systems.
The INS1671 is designed to operate on a multiplexed,
bidirectional bus with other bus-oriented devices. The
functional configuration of the INS1671 is programmed
by the system software via the bus and all parallel data
transfers within the system are accomplished over the
bus lines. In addition, the INS1671 contains a provision
for hardwiring a unique 5-bit identification code to a
chip, thereby allowing up to 32 INS1671 devices to be
addressed via the multiplexed bus.
Features
• Synchronous and Asynchronous Full Duplex Operations
• Synchronous Mode Capabilities
- Selectable 5- to 8-Bit C'haracters
•
•
•
•
•
•
•
•
•
•
- T.wo Contiguous SYN Characters Provide Synchronization
Programmable SYN and DLE Characters Stripping
Programmable SYN and SYN-DLE Characters
Insertion
Asynchronous Mode Capabilities
- Selectable 5- to 8-Bit Characters
Line Break Detection
- 1-,1%-, or 2-Stop Bit Detection
- False Start Bit Detection
- Automatic Serial Echo Mode
DC to 1M Baud Rate
8 Selectable Clock Rates (4 Programmable)
Transmission Error Detection Capabilities
- Parity
- Overrun
- Framing
Double Buffering of Data
8-Bit Bidirectional Bus for Data, Status, and Control
Words
All Inputs and Outputs TTL Compatible
On-Line Diagnostic Mode'
Reduces System ComponentCount
Direct Plug-In Replacement for Western Digital
FD1671
INS1671 General System Configuration...---_....,
PERIPHERAL
INTERfACE
SERIAL DATA OUT
SERIAL DATA IN
SYSTEM
PROCESSOR
COMMUNICATIONS
LINK
(MODEM OR
DATASET)
TIMING & CONTROL
lOCAl32Xi""1~~;;!f4~~~
CLOCKS
(R1 - R4)
CONTROL BUS
Ii!JI
MEMORY
© 1977 National Semiconductor Corp.
0·145
.
Absolute Max,imum Ratings
'
"
"
VOO with Respect to Vss (Ground) .......•....... +20 V to -0.3 V:
Maximum Voltage to Any Input ,with Respect to Vss ... +20 V to -0.3 V
Operating Temperature .......................... O°C to +70°C
Stonj~e Temperature .... ; ., ........... : .........55"'C to +1:!5QC
Power Dissipation .................. ; " ........... 1000mW
.
"
,
'
,
;
Note: Maximum ratings indicate limits beyond which permanent damage
may ·occur. Continuous operation at these limits is not intended and
should be ,limited to those conditions specified under dc electrical characteris~ics. '
DC Electrical Characteri,stics
T A = O°C to +70°C. VOO = +12.0V ± 0.6 V. Vss = -5.0V ± 0.25 V. Vss = OV. Vee = .+5 V ± 0.25 V
Symbol
Parameter
Unit
Min
Typ
Max
Conditions
III
I nput Leakage
/.lA,
10
V 1N = Voo
ILO
Output Leakage
/J A
10
VOUT= VOO
Iss
V ss Supply Current
mA
1
leeAVE
Vee Supply Cu rrent
mA
SO
IOOAVE
V 00 Supply Current
mA
VIH,
Input High Voltage
V
Lo~
VIL
Input
VO H
Output High Voltage
Voltage (All Inputs)
V
VOL
Output Low Voltage
V
Vss = -5V
10
2.4
V
O.S
2.S
10,= -100/.IA
0.4
10 = 1.6mA
AC Electrical Characteristics
TA = o°c to+70°C. Voo=+12.0V ±0.6V. vss= -5.0 V ±O:25V. Vee =+5.0\f:l: O.25V. Vss= OV.CLMAX =20pF
"
Symbol
Parameter
Unit
Address Setup Time
tAS
Min
ns
0
150
tAH
Addr~ss Hold Time
ns
tARL
Address to RPL Y Delay
ns'
tes
CSWidth
ns
250
CS to Reply Off Delay
tesRLF
READ CYCLE
ns
0
tARE
Address to R E Spacing
'ns
250
tRECSH
RE and CS Overlap
ns
20
tREes
RE to CS Spacing
ns
250
tREO'
RE to Data Out belay
ns
tRE
RE Widtb
ns
200
250
Typ
Max
400
250
RL =2.7kn
180
CL = 20pF
1000
WRITE CYCLE
J
Adctress to WE spacing
ns
WE and CS Overlap
ns
20
WE Width
ns
200
tos
Data Setup Time
ns
150
tOH
Data Hold Time
tWEes
WE to CS Spacing
tAwE
tWECSH
, tWE
"
ns
100'
ns
250
"
"
0-146
Conditions
1000
Interrupt
Unit
Min
tCSI
CS to IACKI Delay
Parameter
os
tCSRE
CS to R E Delay
ns
tCSREH
CS and R E Overlap
ns
tRECS
R E to CS Spacing
ns
tpi
IACKI Pulse Width
ns
0
250
20
250
200
tlAD
IACKI to Valid ID Code Delay
ns
tRED
RE Off to DAL Open Delay
ns
tlARL
IACKI to RPL Y Delay
ns
tCSRLF
CS to RPL Y Off Delay
ns
tlAIH
IACKI On to INTR Off Delay
ns
til
IACKI to IACKO Delay
ns
tREI
RE Off to IACKO Off Delay
ns
Symbol
Typ
Max
Conditions
250
180
250
250
300
200
250
0
(Note 1)
RL
= 2.7 kn
Note 1: If RE goes low after IACKI goes low, the delay will be from the falling edge of RE.
Timing Waveforms
(j) = VIH (MINI = 2.4 V
(j) = VIL (MAX) = 0.8 v
® = VOH (MIN) = 2.8 V
® = VOL (MAX) = 0.4 V
•
DALBUS
(j)
~
(j)
~
ADDRESS
VALID
0rlAS1
DATA
VALID
'n
Operation or read into the DAL Bus by a Read Opera·
tion. The contents of Control Register 1 can be changed
at any time, while the contents of Control Register 2
(usually loaded first) should be changed only when the
Receiver and Transmitter sections of the chip are both in
the idle mode. The contents of the two control registers
are shown in figures 1> and 2 and ~re described below.
CONTROL REGISTER 1 (CR1) CONTENTS
I
Bit 0: Controls the> generation of the Data Terminal
Ready (DTR) output. When high (logic 11. enables the
Carrier Detector and Data Set Ready interrupts. When
low (logic 0), enables only the >Ring Indicator On inter·
rupt.
Bit 3: When high while in the Asynctjronqus mode, >
enables a parity check> on each receJved character and
the generation of a parity bit for each transmitted
character. When high while in the Synchronous mode;
enables a parity check on each received character.
Bit 4: When high while the Receiver section is enabled
(bit 2 of Control Register 1 is high) and,in the Asynch·
ronous mode, causes the INS1671 to enter the Echo
mode. In this mode, the Transmitted Data (TDATA)
output is obtained directly from the clocked regenerated
data (assembled received> characters) instead of the
transmission characters from the Transmitter Register.
Echoing does not start until a character has been received
and the Transmitter sectiOn is idle. The Transmitter
section does not have to be enabled in the Echo mode.
When high while the Receiver section is disabled and in
the Synchronous mode, causes the generation of a low·
level Miscellaneous (MISC) output from the chip. (This
When low while the Transmitter section is enabled and
in the Asynchronous mode, causes 2 Stop bits to be
transmitted for character lengths of 6, 7, or 8 bits and
1Yo Stop bits for a character length of 5 bits.
When high while the Transmitter section is disabled and
in the Asynchronous mode, causes the generation of a
low-level Miscellaneous (MISC) output from the chip.
(This output may be used for a Make Busy signal on a
Model 103 Data Set, a Secondar>y Transmit signal on a
Model 202 Data Set, and a Dialing Signal on a CBS Data
Coupler.)
When high in coinCidence with a low·level bit 6 of
Control Register 1 while in the Synchronous mode,
enables transmit parity. If bit6> is high or bit 5 is low, no
parity is generated.
Bit 6: When high while the Transmitter section is enabled
and in the Asynchronous mode, holds the Transmitted
Data (TDATA) output of the chip in a SpaCing (low)
condition, starting at the end of any current transmitted
character. In this case, normal transmitter timing continues so that the Transmission Break condition is timed
out after the loading of new characters in the Transmitter Holding Register.
Bit 2: When high, enables the INS1671 to> perform the
following: (1) transfer a new character into the Receiver
Holding Register; (2) update Receiver status bits 1
through 4; and (3) generate Data Received interrupts.
When low, disables> the Receiver section and clears
Receiver status bits 1- through 4.
>
When high while the Receiver section is enabled and in
the Synchronous mode, causes stripping of received
characters that match the contents of the .oLE Register.
In addition, parity checking is >disabled at this time.
Bit 5: When high while the Transmitter section is enabled
and in the Asynchronous mode, causes a single Stop bit
to be transmitted.
When high in coinciden>ce with a high·level bit 6 while in
the Synchronous mode, causes the cOntents of the DLE
Register to be transmitted before the loading of the next
character in the Transmitter Holding Register, as part of
the Transmit Transparent mode.
Bit 1: Controls the enabling of the Request to Send
(RTS) output. When high in coincidence with a lOW-level
Clear to Send (CTS) input, >enables the Transmitter
section of the chip and allows the generation of Transmitter Holding Register Empty (THRE) interrupts.
When low, disables the Transmitter section and disables
the Request to Send (RTS) output. Before the Tr.ansmitter section is disabled, any character in the Transmitter Register is completely transferred to the MODEM
or data set.
NOTE
Only the first character of a break condition of all
zeros (null character) .is echoed when a Line
Break condition is detected. Fo~ all subsequent
null characters with low·level Stop bits, a steady
Marking (high) condition is transmitted until
nor["al character reception is resumed.
output may be used as a New Sync signal on a Model 201
Data Set.) With a 32X clock selected, a high·level bit 4
causes the Receiver bit timing to be synchronized on
Mark·Space (high-low) transi~ions.
When high while in the Synchronous mode, conditions
the Transmitter> section to the Transmit Transparent
mode, which implies that the idle Transmitter time will
be filled by DLE·SYN charaCter transmission and that
a DLE can be> forced ahead of any character in the
Transmitter Holding Register by setting bit 5 of Control
Register 1 high, prior to loading the THR.
Bit 7: When low, the INS1671 is configured to provide
an internal data and control loop (On·line Diagnostic
mode), and the Ring Indicator On interrupt is disablec:i.
When high, the chip is in the normal full duplex configuration and the Ring Indicator ·On interrupt is
enabled.
In the On·line Diagnostic mode, the following occur
(via internal logic):
1. The TDATA output (pin 37) is connected to
the RQATA input (pin 27). The TDATA
output is held in the Marking (high) condition
and the RDATA input>from the MODEM or
c:iata ~et is disregarded.
>
2. The Transmitter clock is also used as the
Receiver clock, when the 1X clock is selected
by bits 0 - 2 of Control Register 1.
3. Bit 0 (Data Terminal Ready) of Control Register
1 is connected to the i5SR input (pin 28).
The DTR output (pin 16) is held in the Off
(high) condition and the DSR input from the
> MODEM or data set is disregarded.
4. Bit >1 (Request to Send) of Control Register 1
is connected to both the CTS input (pin 36)
0-151
1•• 1
and th~ CARi'i" input (pin 29). The RTS'output'
{pin ~8) is held in the Off: 1high) condition '
, and 'the mand ,CAffR inputs from the
MODEM or data set are disregarded.
5. The Mise output (pin 19) is held in the Off'
(high) condition.
" ,
NOTE
3 must: be high (logic 1) for the 1X ,clock
,selection by pits 0 - 2 of Control R~gister 2.
~.t
When high while it'! the Synchronous mode, causes
, stripping of aU OLE andSYNcharacters in,tHe Transmit
Transparent mode ,(selected by bit 6 of Control Register
1) or ,of all SYN characters, in the, Transmit N.onTransparent mode'. In, addition, no Data Received
interrupt is generated and the SYN Detect 'status bit is
set ',high with the reception' of the next 'assembled
character.
CONTROL REGISTER 2 (CR2) CONTENTS
Bits 0 -:- 2: Select clocks for Receiver and Transmitter
, secitions of the chip as indicated below.
B2
B1
So
0
0
'0
0
0
1
1
0
0
1
Clock Selected
0
0
1
1
1
1
1
--,
1
0
1
0,
1
0
1
,
,
"
lXTC an'd rXRC inputs for
Transmitter and Receiver sec·
t'inns, respectively'
Rl (32X)inpui
R2 (32X) input
R3 (32X) input
R4 (32X) input
R4 (64X) input +2
R4 (128X) input +4
R4 (256X) input +8
,
Bit 4: When high while parity is enabled (bit 3 and/or
bit 5 of Control Register 1 are high), selects Odd parity.
When low whil,e, parity is enabled~ selects Eve,n pa,ity.
lJit 5: When high, selects the Synchronous mode for the
"INS1671.When low, selects the Asynchronous mode for
the c~ip.
''
,
,
Bits 6 and7: Select the character length' as indicated
below.
Bit 3: When low while in th,e Asynchronous mode,
selects the 'R 1 (32X) clock inputfor the ,Receiver section
of the chip. When high, selects the same 32X clock rate
for ,the Receiver section, as selected fo~ tIle Transmitter
\
section.
B7
B6'
Character Length'
0,
0'
0
8 bits
7 bits
6 bits
5 bits
1
0
1
1
1
'
BIT NUMBERS ------------------------------------~\
f
I
SYNC/AIYNe
MYNC !!~ANS, ENABLEDI
O-LDD'MODE
a - NON,BREAK MODE
1 - NORMAL MODE 1 - BREAK MODE
a -1% DR UTD' BIT
o- TRANSPARENT
TRANSMIT NON,
MODE
1 - TRANSMIT,
TRANSI'ARENT MODE
,
I
0 - NDN,ECHD MODE
SElECTION
1 .:.. AinO ECHO MODE
1 - SINGLE STOP 81T SELECTION
AlYNC (TRANS: DISABLEDI
SYNC (REC, ENABLED)
D- OLE STRIPPING
8 - MISC OUT • 1
NOT ENABUD
1 - iii1CDUT • 0
1 - OLE STRIPPING
snc(BITB'I)
0- NO PARITV .GENERATED
ENABLED
·'1
=::
SYNC !REC. DISABLEDI
1 - TRANsMIT PAR'TY ENA8~ED :
SYNC lilT 6
0- NO FORCE,OLE
1 - FORe'E OLE
I' I
I
AIlli
:~~:!
0 - RECEIVER 0 - m OUT· 1 0 - m OUT .. 1
DISABLED l-fflDUT.O l~iffiioUT'O
o - NO PARITY ENAIlLED
1_"
'ENABLED"
ION
N$MITTER
1 -RECEIVER
'ENABLED
~
a - RECEIVER PARITY CHECK IS.
DISABLED
1 - RECEIVER PARITY CHECK IS
ENA8LED
.
Figure 1. Control Register 1 Contents
.lXwms
CHARActER LENGTH SELECT
,OO..,IBITS
"01-1 BITS
10=. BITS
l1'58ITS
0- ASYNCHRONOUS'MODE
1 - SV,~~HRONOUS MODE
1 - ODD PARITY SELECT
0 - EVEN PARITY SELECT
" ..: RECEIVER CLOCK
DETERMINED BY
81TS8'Z
o- ~~~W~R CLK ,
SYNC ICRI 'BIT ,'. o~
a-NDSYNSTRIP ,
1 - SYN ST,RI,
SYNC
"
(coi' BIT •• 11
O-'ND DLE-IYNSTRIP
"
,1- DlE..sVN'STRI'
",,'
'Figure 2. Control Register 2 Contents
0·152
CLDC~ SELECT
009 -IX CLOCK
001 - RATE 1 CLOCK
01. - RATE 2 CLOCK
011 - RATE 3 ClO'CK
100 - RATE 4 CLOCK
111-'RATE 4 C'LOCK+2
.. 110 - RAT~ 4 CLP~K+4
111 ,-,~ATE4C~0.CK+'
INS1671 Status Register
The Status Register of the INS1671 holds information
that defines data conditions of the Receiver and Transmittenections of the chip, and the status of the MODEM
or data set. This 8-bit register can be read onto the DAL
Bus by a Read operation. The contents of the Status
Register are shown in figure 3 and are described below.
Bit 0: When high, indicates that no character is contained in the Transmitter Holding Register while the
Transmitter section is enabled. Bit 0 is set high when the
contents of the Transmitter Holding Register are transferred to the Transmitter Register. Bit 0 is reset low
when the Transmitter Holding Register is loaded from
the DAL Bus or when the Transmitter section is disabled
by forcing the CTS input to a high level.
,Bit 1: When high, indicates that the Receiver Holding
Register has been loaded from the Receiver Register
while the Receiver section isenabled. Bit 1 is reset low
when the Receiver Holding Register is read onto the
DAL Bus or when the Receiver Section is disabled by
forcing bit 2 of Control Re'gister 1 to a low level.
Bit 2: When high, indicates an overrun error that occurs.
if the previous character in the Receiver Holding Register
has not been read onto the DAL Bus and Data Received
status bit 0 has not been reset low, at the time a new
character is to be transferred to the Receiver Holding
Register. Bit 2 is reset low when no overrun error is
detected or when the Receiver section is disabled.
Bit 3: When high while DLE stripping is enabled (bit 4
of Control Register 1 is high) and the Receiver section is
enabled, indicates that the character previous to the
presently assembled character matched the contents of
the DLE Register. Bit 3 is reset low when a no match
condition exists between the previous character and the
contents of the DLE Register.
When high while DLE stripping is disabled, parity
checking is enabled (bit 3 of Control Register 1 is high)
/
and the Receiver section is enabled, indicates that the
last received character has a parity error. Bit 3 is reset
low when a correct parity condition exists.
NOTE
Bit 3 is reset low during DLE stripping or parity
error checking when the Receiver section is
disabled.
Bit 4: When high while in the Asynchronous mode,
indicates that the Received Data (R DATA) input contains a low-level Stop bit after the last bit of the character (framing error), while the Receiver section is
enabled, Bit 4 is reset low when the proper high-level
Stop bit is detected.
Wl;len high while in the Synchronous mode, indicates
that the contents of the Receiver Register matched the
contents of the SYN Register, while the Receiver section
is enabled. Bit 4 remains high for the duration of a full
character assembly.
NOTE
Bit 4 is reset low in both modes when the Receiver
section is disabled.
Bit 5: Complement of the active low-level Carrier
Detector (CARR) input.
Bit 6: Complement of the active low-level Data Set
Ready (DSR) input. Bit 6 may be used for a Secondary
Receive signal on type 202 data sets.
Bit 7: When high, indicates that there is a change in the
state of the Data Set Ready (DSR) or Carrier Detector
(CARR) input to the INS1671, while the internal Data
Terminal Ready signal (bit 0 of Control Register 1) is
high (On); or that the Ring Indicator (RING) input is
low (On) while the internal Data Terminal Ready signal
(bit 0 of Control Register 1) is low (Off). Bit 7 is reset
low when the contents of the Status Register are read
onto the DAL Bus.
BiT NUMBERS
DATA SET CHANGE DATA SET READY CARRIER DETECTOR FRAMING ERROR! OLE DETECTI
SYN DETECT
PARITY ERROR
OVERRUN ERROR DATA RECEIVED
Figure 3. Status Register Contents
D-153
1
TRANSMITTER HOLDING
REGISTER EMPTY
INS1671 Operation
Register,' status bits are not updated, .nd the Receiver
interrupt is not activated. After the detection of the first
SYNcharacter, the Receiver section assembles subsequent bits into characters whose length is determined by
the contents of Control Register 2. If, after the first
SYN character detection, a second SYN ch,aracteris
present, the Receiver section enters the synchronized
state until the Receiver Enable Bit (bit 2 of Control
Register 1) is turned Off. If a second successive $YN
character is not detected, the Receiver reverts to the
Search mode.
The following describes the operation of the INS1671
chip. Use the functional block diagram on page 5 as
necessary to follow these descriptions.
ASYNCHRONOUS MODE
Framing of asynchronous characters is provided by a
low· level (logic 0) Start bit at the beginning of a charac·
ter and a high·Jevel (logic 1) Stop bit at the. end of a
character. R~cePtion of a character is initiated on
recognition of the first Start bit after a preceding Stop
bit by a positive transition of the receiver clock. The
Start and Stop bits are stripped off while assembling the
serial input into a parallel character.
The character assembly is completed by the reception
. of the Stop bit after reception of the last character ·bit.
If this bit is high, the character is determined to have
correct framing and the INS1671 is prepared to receive
the next character. If the Stop bit is low, the Framing
Error flag (bit 4 of Status Register) is set and the
Receiver section assumes this bit to be the Start bit of
the next character. Character assembly continues from
this point if the input is still low, when sampled at the
theoretica,l center of the assumed Start bit. As long as
the Receiver input is a Spacing (low) condition, all
zero characters are assembled and error flags and Data
Received interrupts are generated so that Line Break
conditions can be detected. After a character of all
zeroes is assembled along. with a zero in the Stop bit
location, the first received Marking (high) condition
is determined as a Stop bit and this resets the, Receiver.
section to a Ready state for assembly of the next
character.
In the Asynchronous mode, the character transmission
occurs when information contained in the Transmitter
Holding Register is transferred to the Transmitter
Register. Transmission is initiated by the insertion of a
Start bit, followed by the serial output of the character
least significant bit first with parity (if enabled) following
the most significant bit; then the insertion of a 1-, 1%-,
or 2-bit length Stop condition. If the Transmitter
Holding Register is full, the next character transmission
starts after the transmission of the Stop bit of the
present character in the Transmitter Register. Otherwise,
the Marking condition is continuously transmitted until
the Transmitter Holding Register is loaded.
In the Synchronous mode, 'a continuous stream of
characters is transmitted once the Transmitter section is
enabled. If the Transmitter Holding Register is not
loatled at the time the Transmitter Register has completed
transmission of a character, this idle time will be filled
by a transmission of the character contained in the SYN
register in the Transmit Non-Transparent mode, or the
characters contained in the OLE and SYN registers
respectively while in the Transmit Transparent mode of
. operation.
DETAILED OPERATION
Receiver Section: The data input to the Receiver section
is clocked into the Receiver Register by a 1 X Receiver
clock from a MODEM or dataset, or by a local 32X bit
rate clock selected from one of four externally supplied
clock inputs. When using the 1 X clock, the Received
Data (RDATA) input is sampled on the positive transition of the clock in both the Asynchronous and Synchronous modes. When using a 32X clock in the Asynchronous mode, the Receiver sampling clock is phased to
the l'iIIark-To-Space transition of the Start bit of the data
input and defines, through clock counts, the center of
each received data bit within +0%, -3% at the positive
transition 16 clock periods later.
In the Synchronous mode, the Receiver sampling clock
is phased to all Mark-To-Space transitions of the data
inputs when using a 32X clock. Each transition of the
data causes an incremental correction of the sampling
clock by 1/32 of a bit period. The sampling clock can be
immediately phased to every Mark-To-Space data
transition by setting bit 4 of Control Register 1 high,
while the Receiver section is disabled.
In order to allow re-transmission of data received at a
slightly faster character rate, means are provided for
shortening the Stop bit length to allow transmission of
characters to occur at the same rate as the reception of
characters. The Stop bit is shortened by 1/16 of a bit
period for 1-Stop bit selection and 3/16 of a bit period
for 1%- or 2-Stop bit selection, if the next character is
ready in the Transmitter Holding Register.
SYNCHRONOUS MODE
Framing of characters is carried out by a special Synchronization (SYN) Character Code transmitted at the
beginning of a block of characters. When the Receiver
section is enabled, it searches for two continuous characters matching the bit pattern contained in the SYN
Register. During the time the Receiver section is searching, data is not transferred to the Receiver Holding
When the complete character has been shifted into the
Receiver Register, it is then transferred to the Receiver
Holding Register; the unused, higher number bits are
filled with zeroes. At this time, the Receiver status bits
(Framing Error/SYN Detect, Parity ErrorlDLE Detect,
Overrun Error, and Data Received) are updated in the
Status Register and the Data Received interrupt is
activated. Parity Error is set, if encountered while the
Receiver parity check is enabled in Control Register 1.
The Overrun Error flag (bit 2 of Status Register) is set
if the Data Received status bit (bit 1) is not cleared
through a Read operation by an external device, when
a new character is ready to be transferred to the Receiver
Holding Register. This error flag indicates that a character has been lost, as new data is lost and the old data
and its status flags are saved.
The characters assembled in the Receiver Register that
match the contents of the SYN or DLE Register are not
0-154
loaded into the Receiver Holding Register, and the
Data Received interrupt is not generated, if bit 3 (SYN
Strip) of Control Register 2 or bit 4 (OLE Strip) of
Control Register 1 are set respectively; the SYN-DET
and DLE-DET status bits are set with the next non-SYN
or non-OLE character. When both the SYN Strip and
OLE Strip bits are set (Transmit Transparent mode),
the DLE-SYN combination is stripped. The SYN comparison occurs only with the character received after the
OLE character. If two successive OLE characters are
received, only the first OLE character is stripped. No
parity check is made while in this mode.
section selects one of the four selected rate inputs and
divides the clock down to the baud rate. This clock is
phased to the Transmitter Holding Register Empty flag
(bit 0 of Status Register) such that transmission of
characters occurs within two clock times of the loading
of the Transmitter Holding Register, when the Transmitter Register is empty.
Transmitter Section: Iriformation is transferred to the
Transmitter Holding Register by a Write operation.
Information can be loaded into this register at any time,
even when the Transmitter section is not enabled.
Transmission of data is initiated only when the Request
to Send (RTS) bit (bit 1 of Control Register 1) is set
high and the Clear to Send (CTS) input is low. Information is normally transferred from the Transmitter
Holding Register to the Transmitter Register when the
latter has completed transmission of a character.
However, information in the OLE Register may be
transferred prior to the information contained in the
Transmitter Holding Register if the Force OLE signal
condition is enabled (bits 5 and 6 of Control Register
1 set high). The Force OLE control bit (bit 5 of Control
Register 1) must be set prior to loading of a new character in the Transmitter Holding Register to ensure
forcing the OLE character prior to transmission of the
data character. The Transmitter Register output is
applied to a flip-flop which delays the output by one
clock period. When using the 1 X clock generated by the
MODEM or data set, the output data changes state on
the negative clock transition and the delay is one bit
period. When using a local 32X clock, the Transmitter
When the Transmitter section is enabled, a Transmitter
interrupt is generated each time the Transmitter Holding
Register is empty. If the Transmitter Holding Register
is empty when the Transmitter Register is ready for a
new character, the Transmitter section enters ·an idle
state. During this idle time, a high will be presented to
the Transmitted Data (TDATA) output in the Anynchronous mode or the contents of the SYN Register will
be presented in the Synchronous Transmit NonTransparent mode. 1n the Synchronous Transmit Transparent mode (enabled by a high-level bit 6 of Control
Register 1)' the idle state will be filled by a DLE-SYN
character transmission in that order. When entering the
Transmit Transparent mode, the DLE-SYN fill will not
occur until the first forced OLE.
If the Transmitter section is disabled by a reset of the
Request to Send control bit, any partially transmitted
character is completed before the Transmitter section of
the I NS1671 is disabled. As soon as the Clear to Send
(CTS) input goes high, the Transmitted Data output will
go high.
When the Transmit parity is enabled, the selected Odd
or Even parity bit is inserted into the last bit of the
character in place of the last bit of the Transmitter
Register. This limits transfer of character information
to a maximum of seven bits plus parity or eight bits
without parity. Parity cannot be enabled in the Synchronous Transmit Transparent mode.
'·B'
0-155
Physical Dimensions
2.020
1------(51.308).·----------------1
.
MAX
"
0.032
(0.813)-
1
0.590
RA~
(14.986)
~~~~~j
0.165
0.050
~
TI
Ceramic Dual-In-Line Package (0)
Order Number INS16710
Z.Olll
-----------(52.5781------------[
MAX
~
~
18
31
~
~
~
n
H
H
2J
~
~
M
n
u
ft
I
i
0550-0.005
(13.970'0.127)
PIN NO.1 INDENT
I
~~T.n~PT.~~T.rr.~~~~~~
lr=
r
=r 0.060
O.600~O.620-----1. ,,~
(15.240-15.7481 .
".025
-1
-
~(15.875+0.635)----1
0.625_0.015
•
0,030
!IIJ62)
-
,_
0.009-0. 015
(0.229-0.3811
0.050
~.,. . . . .
TYP
(3.302 ~O.I27!
L
1
.
0.1115'0.015
(1.905<0.3111)-1--
~(Hi40)
0.100
-I
~
.
0.018'0.003
---11--(0.45],0.076)
~
~
-----I~
0125(0.508)
(3:175) MIN
~
Plastic Oual·ln-Line Package (N)
Order Number INS1671N
Manufactured under one or more cf the following U.S. patents: 3083262, 3189758, 3231797, 3303356, 3317671. 3323071, 3381071, 3408542,3421025,3426423,3440498,3518750,3519897, 3557431, 3560765,
3556218,3571630,3575609.3579059,3593069,3597640,3607469,3617859,3631312,3633052,3£38131.3648071,3651565,3693248.
National Semiconductor Corporation
2900 Semiconductor Drive, Santa Clara, California 95051, (408) 737 5000/TWX (910) 339 9240
M
M
National Semiconductor GmbH
808 Fuerstenteldbruck, Industriestrasse 10, West Germany, Tele. (08141) 1371/Telex 05 27649
M
National Semiconductor (UK) Ltd.
Larkfield Industrial Estate, Greenock, Scotland. Tele. (0475) 33251/Telex 778 632
M
National does not assume any responsibility for use of any circuitry described; no circuit patenllicences are implied; and National reserves the right, at any time without notice. to change said circuitry.
0-156
I?A National
Preliminary
JULY 1978
~ Semiconductor
N
(J1
INS8250 Asynchronous Communications Element
o
»
~
General Description
The I NS8250 is a programmable Asynchronous Communications Element (ACE) chip contained in a standard
40-pin dual-in-line package. The chip, which is fabricated
using N-channel silicon gate technology, functions as a
•
serial data input/output interface in a microcomputer
system. The functional configuration of the I NS8250 is
programmed by the system software via a TRI-STATE®
8·bit bidirectional data bus.
The I NS8250 performs serial-to-parallel conversion on
data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversion on data
characters received from the CPU. The CPU can read the
complete status of the I NS8250 at any time during the
functional operation_ Status information reported
includes the type and condition of the transfer operations
being performed by the I NS8250, as well as any error
conditions (parity, overrun, framing, or break interrupt).
In addition to providing control of asynchronous data
communications, the INS8250 includes a programmable
Baud Generator that is capable of dividing the timing
reference clock input by divisors of 1 to (2 16 - 1), and
producing a 16x clock for driving the internal transmitter
logic. Provisions are also included to use this 16x clock
to drive the receiver logic. Also included in the I NS8250
is a complete MODEM-control capability, and a processorinterrupt system that may be software tailored to the
user's requirements to minimize the computing time
required to handle the communications link.
Features
•
Z
en
Q)
Designed to be Easily Interlaced to Most Popular
Microprocessors.
Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or from Serial
Data Stream
•
Full Double Buffering Eliminates Need for Precise
Synchronization
•
Independently Controlled Transmit, Receive, Line
Status, and Data Set Interrupts
•
Programmable Baud Rate Generator Allows Division
of Any Input Clock by 1 to (2 16 - 1) and Generates
the Internal 16x Clock
•
Independent Receiver Clock Input
•
MOOEM Control Functions (CTS, RTS, DSR, DTR,
R I, and Carrier Detect)
•
Fully Programmable Serial-Interface Characteristics
-
5-,6·, 7-, or 8-Bit Characters
Even, Odd, or No-Parity Bit Generation and Detection
1-, 1 %-. or 2-Stop Bit Generation
Baud Rate Generation (DC to 56k Baud)
•
False Start Bit Detection
•
Complete Status Reporting Capabil ities
• TRI-STATE TTL Drive Capabilities for Bidirectional
Data Bus and Control Bus
•
Line Break Generation and Oetection
•
I nternal Diagnostic Capabilities
Loopback Controls for Communications Link Fault
Isolation
Break, Parity, Overrun, Framing Error Simulation
•
Full Prioritized Interrupt System Controls
•
Single +5-Volt Power Supply
•
MICROBUSTM* Compatible
INS8250 MICROBUS Configuration
~
1-.;;.::;"-....,
~
I---'-"-"-.......~,
~ 1---'-"-....... ,
~
r.....;::..........~'
"0"
"1"
*Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
® TRt-STATE IS a trademark of National Semiconductor Corp.
0-151
::::J
(")
...
':1'
o
8
en
g
3
3
c
::::J
~.
cr.
o
~
m
CD
3
CD
a.
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . O°C to' + 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
All Input or Output Voltages with Respect to VSS .... -0.5 V to +7.0 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . '. ,., . , . . . . 400.mW
Absolute maximum ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is not intended;
operation should be limited to those conditions specified under DC
Electrical Characteristics,
DC Electrical Characteristics
T A: O°c to + 70°C, VCC : +5, V ± 5%, VSS : 0 \J, unless otherwise specified.
Parameter
Symbol
V,lX
Clock Input Low Voltage
Min
V,HX
Clock Input High Voltage
V,l
Input low Voltage
-0.5
V,H
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Typ
-0.5
2.0
Max
Units
0.8
V
VCC
V
0.8
V
VCC
V
0.4
2.4
V
V
ICC (AV)
Avg Power Supply Current (Vec)
80
mA
',l
Input Leakage
±10
/lA
ICl
Clock leakage
±10
/lA
65
Test Conditions
}'Ol: 1.6mA on all
IOH : - lOO /lA,
out~uts,
Capacitance
TA: 25°C, VCC: VSS: OV
Symbol
Parameter
CXIN
Clock Input Capacitance
Min
Typ
Max
15
20
pF
Units
CXOUT
Clock Output Capacitance
20
30
pF
C,N
Input Capacitance
6
10
pF
COUT
Output Capacitance
10
20
pF
Test Conditions
fc: 1 MHz
Unmeasured pins returned to VSS
TYPICAL SUPPl Y CURRENT vs
TEMPERATURE. NORMALlZED(J)
1.5
....
....
'"
'"::>'"u
1.0
>
....
,
r---
...
~
::>
'"
0.5
0
I
----
+25
+50
AMBIENT TEMPERATURE (OC)
0-158
-
+75
AC Electrical Characteristics
T A ~ O°C to ± 70°C, VCC ~ +5 V ± 5%
tAW
Address Strobe Width
tAS
Address Setup Time
tAH
Address Hold Time
tcs
Chip Select Setup Time
Max
Units
ns
110
-
0
-
ns
110
-
ns
Min
Parameter
Symbol
90
ns
tCH
Chip Select Hold Time
0
-
ns
tess
Chip Select Output Delay from Strobe
0
90
ns
tDID
DISTR/DISTR Strobe Delay
0
-
tDIW
DISTR/DISTR Strobe Width
175
tRC
RC
Read Cycle Delay
1735
-
ns
ns
2000
-
ns
tDD
Read Cycle ~ tAW + tDID + tDIW + tRC
DISTR/DISTR to Driver Disable Delay
-
150
tDDD
Delay from DISTR/DISTR to Data
-
250
tHZ
DISTR/DISTR to FloatingData Delay
100
tDOD
DOSTR/DOSTR Strobe Delay
-@
100 pF loading
ns
-@
100 pF loading
ns
-@
100 pF loading
-
ns
-@
100 pF loading
50
-
ns
-@
100 pF loading
ns
tDOW
DOSTR/DOSTR Strobe Width
175
-
ns
twc
WC
Write Cycle Delay
1785
-
ns
2100
_.
ns
tDS
Write Cycle - tAW + tDOD + tDOW + twc
Data Setup Time
175
-
ns
tDH
Data Hold Time
60
-
ns
tCSC*
Chip Select Output Delay from Select
200
ns
tRA'
Address Hold Time from DISTR/DISTR
50
-
ns
tRCS*
Chip Select Hold Time from DISTR/DISTR
50
-
ns
tAR*
DISTR/DISTR Delay from Address
110
-
ns
tCSR'
DISTR/DISTR Delay from Chip Select
110
-
ns
tWA*
Address Hold Time from DOSTR/DOSTR
50
-
ns
tWCS'
Chip Select Hold Time from DOSTR/DOSTR
50
-
ns
tAW'
DOSTR/DOSTR Delay from Address
160
-
ns
tCSW'
tMRW
DOSTR/DOSTR Delay from Select
Master Reset Pulse Width
160
-
25
-
ns
[J.s
-
'Applicable only when ADS input is tied permanently low.
0·159
Test Conditions
AC Electrical Characteristics (cont'd.)
Parameter
Symbol
Min
Max
Units
Test
Conditions
BAUD GENERATOR
N
Baud Rate Divisor
tBLD
Baud Output Negative Edge Delay
tBHD Baud Output Positive Edge Delay
tLW
1
-
2 16 - 1
250 typ
ns
250 typ
ns
100 pF Load
425 typ
ns
100pF Load
330 typ
ns
100pF Load
100 pF Load
,
Baud Output Down Time
tHW Baud Output Up Time
RECEIVER
tSCD Delay from RCLK to Sample Time
tSINT Delay from Stop to Set Interrupt
tRINT Delay from DISTR/DISTR (RD RBR/RDLSR) to
Reset Interrupt
'
2 typ
/1S
2 typ
/1S
100 pF Load
1 typ
/1S
100 pF Load
1 typ
/1S
100 pF Load
, TRANSMITTER
tHR
Delay from DOSTR/DOSTR (WR THR) to Reset Interrupt
lIRS
Delay from InitiallNTR Reset to Transmit Start
16 typ
BAUDOUT
Cy'cles
tSI
Delay from Initial Write to Interrupt
24 typ
BAUDOUT
Cycles
tss
Delay from Stop to Next Start
1 typ
/1s
tSTI
Delay from Stop to Interrupt (THR E)
8 typ
BAUDOUT
Cycles
tlR
Delay from DISTR/DISTR (RD IIR) to Reset Interrupt
(THRE)
1 typ
/15
MODEM CONTROL
100.pF Load
"
tMDO Delay from DOSTR/DOSTR (WR MCR) to Output
1 typ
/1S
tSIM
Delay to Set Interrupt from MODEM Input
1 typ
/1S
100.pF Load
tRIM
Delay to Reset Interrupt from DISTR/DISTR (RD MSR)
1 typ
/1s
100pFLoad
0·160
• 100pF Load
--
INSB258
VCC
INSB258
XTALI
OPTIONAL
OSC. CLOCK TO
BAUD GEN LOGIC
OSC. CLOCK TO
r-_...._ _.....I\I"'..+_____..B.AUO GEN LOGIC
o.ca:=:=I-----""'"
o~i~~~ ....
XTALI
Timing
'XH
'XL
Min
140
140
Units
..
lIS
CRVSTAL
3.1MH,
A. External Clock Input (3.1 MHz Max ••
10-3DpF
4D-BOpF
B. Typical Crystal Oscillator Network
Timing Waveforms
-APPLICABLE ONLY WHEN OJ IS TIED lOW.
Reed Cycle
0·161
Timing Waveforms (confd.)
.
I--'AW-J
-----------?I~
r---,
L.I
"
AOS~
,
A2,A"AO
==><
f--IAS=±1tA"
VALID
I Xi'-'----'--------""':x·~
. '.I-Ies-,-I:+e"
HtwA'
,----:X=
j--twes·--j
CSi,es"eso ~ .
, Ltese' j+-Iess ==I
eSOUT
--1---1--,'- _____ 1____ _
I. I· :
we-----'---_,I
1-'000
-toow==-l-twe---~,.jl
------------....X
X
:
E
lesw"
,
'AW'
DOSTR/DOSTA
ACTIVE
I'------?,'-----+
E
I:
I
(
I-,os--/-,o"=1
D~~1~ ----------------«
~
DlSTR/DISTR
ACTIVE
.
VALID DATA
*APPlICABlE ONLY WHEN ADS IS TIED lOW.
Write Cycle
XTAL'
IIAU1!lfijf
1+2)
BAUD OUT
1+3)
I'
'I
IHW· IN - 2) XTAL1 CYCLES
'-------'r~
I -·c------+l,1
>
=
'LW 2 XTAL' CYCLES
BAUDOUT Timing
0-162
TIming Waveforms (cont'd.)
AeLK
--u---Lr
LJ
1
I8ClKS---------1-1
___________________________________
-1~~~D
lJ
SAMPLE eLK
SAMPLE
eLK
-----~~-Il'~I~--~~I--I~~
-I
INTERRUPT
IL
I-'SlNT
fir
(DATA RCVRfRR)
READY OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'
~
iiTffiifDISTR@)
(READREC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
DA~~ ~u:{s~~
~~'A'NT
.
ACTlVE
Receiver Timing
Transmitter Timing
DOSTR/DOSTR G)
'WRMeA'
ouWoW!
iii
NOTES:
CD See Write Cycle Timing
@See Read Cycle Timing
--\
\ . .---:--------1r-'MDD~
\. .--------.1i--.MDD-I
1,----
\
\
MODEM Controls Timing
0-163
/
.
._______
INS8250 Block Diagram
D7- DO
AD
A,
A2
DIVISOR
LATCH (LS)
DIVISOR
LATCH (MSl
z
C/l
ex>
IV
,..,
L ___________
A5
rrlV
c: ~
S;
,'17
."
or
c
_
~5.
DATA 0
~
DATA 1
2:
~
..,
DATA 2
g:
DATA 3
"
VI
~
-!
DB6
~
DB7
~
.j
IloR
1>2 (TTL)
;.
g
RESET
DP8224
CLOCK
GENERATOR
&
DRIVER
I
IloW
21 _I
r------.......::.!...j
...
I
1.
:1
35 II
31
'":J
z
C/l
INS8250
(ACE)
RI
..1L+5V
RLSO
.1!
DAlA4
DSR
-.ll
5
CTS
DAlA
3
OUT 2'
_ 36
ex>
o
ex>
o
»
~
<1>
3
'"
DAlA6
:J
DATA 7
:J
"-
3
OISTR
1
DOSlA
i)'
(3
"3o
'0
c:
~
:'i
~
iti
3
:;;
;::>'
:T
'":T
,0'
:r
~
l>
"0
'2..
(;'
a
0'
il
Typical Applications (cont'd)
INS8250
(ACE)
I
I
+I
l+oliD.ATioiAOil'ilIUS"'~07· DO
MICROCO~~~~i: l+oliDIIIATjiAW'WjU,S
Figure 2. Typical Interface for a High-Capacity Data Bus
Physical Dimensions
inches (millimeters)
~----{5~:~::)------O.-52-0----------~·-'
MAX.
1
-~ UJ.ZD8)
saUARE
-----I
I
0.032
i
(Ojtj)
0.590
,AD
~
'II
(14.986)
MAX
I
L;"--",..,.,..,.."rr;rr;~:;:::;:;;:;:=r.~~"""".",..-r,;r-r.;r-r;;;r-",,..~l
+
..
.
~OB-0012 I'
1
1----------05.241--REF
---O.&DO
1D.2D3~O.30"
I
---,
I---{1.27I1'.O.254)
0.050 '0.010
0.100 'O.OtD
!
I
0.050
~-I[
TV'
0.018 '0.002
.
II
~)--I,-'-
/2.540'0254,--1:-
'jMAX 1::::=::::,
0.23
=r-~
-.'
. . -+-
0125
(3:175)
MIN
Ceramic Dual·ln-Line Package (D)
Order Number INS8250D
NS Package Number D40C
0.062
(1.575)
0.5500.005
03.910 0.127)'
'AD
PIN NO. I INDENT
~~~~rr.n~~~~~~~--j
0.030
0.060
(0.7621
0,050
~_j 'T' 'i' ~."'".
lr(1'~)481~~~~. ~IL
1--.
r
O•.•••
+0025
I
r--
I
0.625 0:015
(15.875 +O.635)-~---~
0.009-0. 015
1
(0.229-0,J81)·
0.0150,015'
(1.905 '0.381)--
I
.
---
I
---
I
r-
0.100
(2.540J
~
II
~
~
0.020
0.018 0.003
---- ---(0.457 ·0.0~6)
0125(0.508)
(3:175) MIN
~
Plastic Dual-In-Line Package (N)
Order Number INS8250N
NS Package Number D40A
Nlllon,l SemlconductlN"
Corpor,tlon
2900 Semiconductor Drive
Santa Clara. California 95051
Tel (408) 737-5000
TWX' (910) 339·9240
Natlon,l Semiconductor GmbH
8000 MUnchen 21
Eisenheimerstrasse 61/2
WeslGermany
Tel.' 089/915027
Telex: 05-22772
NS Int,rnatlonal Inc., Japan
/' Miyake Building
,.g Yolsuya.
Shinjuku·ku 160
Tokyo, Japan
. "Tel: (03)355-3711
TWX: 232·2015 NSCJ-J
National Semiconductor
(Hong Kong) Ltd.
8lhFloor,
Cheung Kong ElectroniC Bldg
4 Hing Yip Stree1
Kwun Tong
Kowloon, Hong Kong
Tel 3-411241·8
Telex' 73866 NSEHK HX
Cable. NATSEMI
NS Electronics 00 Brasil
Avda Btlgadeiro Faria Lima 84\t
11 Andar Conjunto 1104
.
Jardim Paulislano
Sao Paulo, Brasil
Telex
1121008 CABINE SAO PAULO
NS Electronics Pty. Lid.
Cnr Stud Rd. & Mtn Highway
8ayswater, Vicioria 3153
Australia
Tel,' 03-729-6333
Telex 32096
National does nol assume any responsibility lor use of any.circuitry described: no circuit patent licenses are implied, and National reserves the righi, at any time Without notice, 10 change said circuitry.
0-172
.
~ Semiconductor
~National
AUGUST 1978
Pub. No. 426305429-001 A
."
INS8251 Programmable Communication Interface
c8
Features
General Description
The INSB251 is a programmable Universal Synchronous/
Asynchronous Receiver/Transmitter (USART) chip
contained in a standard 2B-pin dual-in-line package_ The
chip, which is fabricated using N-channel silicon gate
technology, functions as a serial data input/output
interface in National Semiconductor's NBOBO microcomputer family. The functional configuration of the
INSB251 is programmed by the system software for
maximum flexibility, thereby allowing the system to
receive and transmit virtu .-'Iy any serial data communica. tion signal presently in use (including IBM Bisync).
• Synchronous and Asynchronous Full Duplex
Operations
• Synchronous Mode Capabilities
- Selectable 5- to B-Bit Characters
- Internal or External Character Synchronization
- Automatic Sync Insertion
• Asynchronous Mode Capabilities
- Selectable 5- to B-Bit Characters
- 3 Selectable Clock Rates (1 x, 16x or 64x the
Baud Rate)
- Line Break Detection and Generation
- 1-, 1%-, or 2-Stop Bit Detection and Generation
- False Start Bit Detection
The INSB251 can be programmed to receive and transmit
either synchrpnous or asynchronous serial data_ The
INSB251 performs serial-to-parallel conversion on data
characters received from an input/output device or a
MODEM, and parallel-to-serial conversion on data
char~cters received from the CPU. The CPU can read the
complete status of the INSB251 at any time during the
functional operation. Status information reported
includes the type and the condition of the transfer
operations being performed by the INSB251, as well as
any transmission error conditions (parity, overrun, or
framing).
•
Baud Rates
- DC to 56k Baud (Synchronous Mode)
- DC to 9.6k Baud (Asynchronous Mode)
Transmission Error Detection Capabilities
- Parity
- Overrun
- Framing
Double Buffering of Data
TTL Compatible
Single TTL Clock
Reduces System Component Count
MICROBUSTM* Compatible
•
•
•
•
•
•
INS8251 MICROBUS Configuration
INTRk
TxE
INTRi
RxRoy
INTR;
Tx Roy
07 - 00
ADDRESS
BUS
DATA
BUS
CPU
GROUP
CONTROL
,
M
I
C
R
0
B
U
S
SERIAL
DATA OUT
--" 07 - 00
Txo
I'
IIOR
RESET
Rxo
iiQ
oTR
IIOW
RTS
WR
Cs'
AD
Dsii
Cs'
CTS
CID
TxC
RxC
t
t
BAUD
RATE
GENERATOR
*Trademark, National Semiconductor Corp.
© 1978 National Semiconductor Corp.
0-173
I
SERIAL
DATA IN
INSBZ!1
RESET
TO RS -232
INTERFACE
EIA
DRIVERS
~
ii1
3
3Q)
C"
CD
~
3
3
c
::::s
~
s·
::::s
Absolute ,Maximum Ratings
Ambient Temperature Under Bias . . . . . . . . . . . . . . O°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . _65°C to +150°C
Voltage on Any Pin with Respect to Ground ...... -0.5 V to +7 V
Power Dissipation . . . . . . . . . . . . . . . . . : ........... 1 Watt
Note: Maximum ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is not
intended and should be limited to those conditions specified under
de electrical characteristics.
DC Electrical Characteristics
TA = o°c to +70°C; Vee = 5.0V ± 5%; GND = OV
Symbol
Min
Parameter
VIL
Input Low Voltage.
VIH
Input High Voltage
Typ
Max
-0.5
0.8
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
IOL
Data Bus Leakage
IlL
I nput Leakage·
lee
Power Supply Current
Unit
Test Conditions
V
Vee
V
0.45
V
IOL = 1.6mA
V
IOH = -100/.LA
-50
10
J.tA
/.LA
VOUT= 0.45 V
VOUT= Vee
10
/.LA
VIN = Vee
45
80
mA
Typ
Max
Unit
2.4
Capacitance
T A = 25°C; Vee = GN D = 0 V
Symbol
Parameter
I
Min
Test Conditions
CIN
I nput Capacitance
10
pF
fe = 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to GND.
Test Load Circuit
Typical
~
.~~.
~
+10
!
510n
0
0
l-
=>
I!:
=>
0
W
Clock Pulse Width
220
0.7 tCY
ns
tR, tF
Clock Rise and Fall Time
0
50
ns
tD,x
TxD Delay from Falling Edge of TxC
1
IlS
Gl=100pF
tSRx
Rx Data Set·Up Time to Sampling Pulse
2
IlS
Gl =100pF
tHRx
Rx Data Hold Time to Sampling Pulse
2
IlS
G l = 100pF
f Tx
Transmitter Input Glock Frequency
,. lx Baud Rate
16x and 64x Baud Rate
DG
DG
Transmitter Input Glock Pulse Width
lx Baud Rate
16x and 64x Baud Rate
12
1
Transmitter Input Glock Pulse Delay
lx Baud Rate
16x and 64x Baud Rate
15
3
Receiver Input Glock Frequency
1x Baud Rate
16x and 64x Baud Rate
DC
DG
Receiver I nput Clock Pulse Width
lx Baud Rate
16x and 64x Baud Rate
12
1
tCY
tCY
Receiver Input Clock Pulse Delay
lx Baud Rate
16x and 64x Baud Rate
15
3
tCY
tCY
tTPW
tTPD
fRx
tRPW
tRPD
56
520
kHz
kHz
tCY
tCY
,
56
520
tCY
tCY
kHz
kHz
tTx
TxRDY Defay from Center of Data Bit
16
tCY
tRx
RxRDY Delay from Center of Data Bit
20
tCY
tiS
Internal SYNDET Delay from Center of Data Bit
25
tCY
tes
Internal SYNDET Set-Up Time Before Falling Edge of RxC
16
tCY
tTxE
TxEMPTYDelay from Center of Data Bit
16
tCY
twc
Control Delay from Rising Edge of WRITE (TxE, DTR, RTS)
16
tCY
16
tCY
Control to READ Set·Up Time (DSR, CTS)
teR
NOTES:
1. AC timings measured at VOH = 2.0 V, VOL = 0.8 V. and with test load circuit of page 2.
C l = 50pF
C l =50pF
2. This recovery time is for initialization only. when MODE. SYNC1, SYNC2. COMMAND and first o'ATA BYTES are written into the USART.
Subsequent writing of both COMMAND and DATA are only allowed when TxRDY =. 1.
3. The 'fXC and Rxe frequencies have the following limitations with respect to eLK:
for 1x Baud Rate, fTx or fRx" 1/30 teyl
for 16x and 64x Baud Rate, fTx or fAX':;:;:; 1/4.5 tey)
4. Reset Pulse Width = 6 tCY minimum.
0-175
.-*,
Timing Waveforms
READ AND WRITE TIMING
J:=:
elK
--.£-
=1-;""__1:----"'\I..__-..J,r---""""""'-tCY
CW
t
::II
clii.cs
*WRITE AND READ PULSES
HAVE NO TIMING LIMITATION
WITH RESPECT TO eLK.
lAW
Tx£, OTA. RTS
EICR--:=:!
TRANSMITTER CLOCK
AND DATA
_
f.<.ellXBAUD)~::-;;:rC.=typo=~5:---'-'
- - = = - 1 6 TxC PERIODS
TxC (16 x BAUD)
-
_ -f-:
===~-==~---------------------===v---.-tDTX
TxO
_
"'-------
RECEIVER CLOCK
AND DATA
RiC (16 x BAUD)
INTERNAL
SAMPLING
PULSE
Tx ROY AND Rx ROY
TIMING (ASYNC MODE)
RxD - - - , START BIT
I
DATA 81TS
~;
I PARITY BIT ,- STOP BIT I
START BIT
c==
R:::: _____________________________________IR_X_-1--J~r-.-.-.----
WRITE ht BYTE WRITE 2nd BYTE
TxD M"A'R'i<'iN'G1 START BIT I
DATA BIT
I.
htDATABVTE
INTERNAL SYNC DETECT
RxO
(OUTPUT)
SYNDET _____________________________________
EXTERNAL SYNC DETECT
~
SYNDET
(INPUTI
---,l______r-----~I~~--r-----:--1------1~~
_ _ _1Ft'S
---------- -,\.
RxD _ _ _ _ _ _ _ _ _
0-176
ht OA'TA BYTE
INS8251 Block Diagram
INTERNAL
DATA BUS
TRANSMIT
BUFFER
RESET
ClK
TxD
(151
TRANSMIT
CDNTRDl
C/D
jjjj
TxRDV
TxE
Txf
Wii
Ci"':'~---'"
RECEIVE
BUFFER
PDWER
SUPPLY
RxD
{~<5V
~GND
RxRDY
NDTE: APPLICABLE PINDUT NUMBERS
ARE INCLUDED WITHIN
PARENTHESES.
RxC
SYNDET
INS8251 Functional Pin Definitions
The following- describes the function of all the INS8251
input/output pins. Some of these descriptions reference
internal circuits.
INPUT SIGNALS
Chip Select (CS): When low (logic 0), the chip is selected.
This enables communication between the INS8251 and
the I NS8080A microprocessor.
Read (RD): When low, allows the INS8080A to read
data or status information from the INS8251.
Write (WR): When low, allows the INS8080A to write
'
data or control words into the INS8251.
Control/Data (C/O): Used in conjunction with an active
RD or WR input (logic 01 to determine overall device
operation as indicated below.
cs C!D RD WR
0
'0
0
0
Operation
0
1
Data character read from INS8251
0
1
0
Data character written into INS8251
1
0
1
Status information read from INS8251
0
1
1
0
Control word written into INS8251
1
x
x
x
Device not selected
Reset: When high (logic 1), places the INS8251 in the
idle mode. The device remains in this mode until a new
set of control WOrds is written into the INS8251 to
program its functional definition. Minimum Reset pulse
width is 6 tey.
Clock (ClK): TTL ~Iock that is used to generate internal
timing signals for the INS8251. The minimum frequency
of the CLK input is 30 times the receiver/transmitter
clock frequency for the synchronous mode, and 4.5
times ~he receiver/transmitter clock frequency for the
asynchronous mode. The ClK input is normally connected to the' ¢2 (TTL) output of the INS8224 Clock
Generator and Drive'r device.
Transmitter Clock (TxC): This clock input controls the
rate at which a data character is to be transmitted. The
frequency. of the 'fXC input is equal to the Baud Rate
for the synchronous mode, and is a multiple (1 x, 16x or
64x) of. the Baud Rate for the asynchronous mode. A
portion of. the Mode Instruction Word (see t'igure) selects
the value of the Baud Rate Factor when iii the asynch·
ronous mode. Transmitter Data are clocked out of the
INS8251, on the falling edge of the 'fXC input.
Data Set Ready (i5SR): General-purpose input whose
condition can be tested by the INS8080A using a status
read operation. However, a low-level i5SR input is
normally used to test data set ready conditions.
0·177
Ii!II
Clear to Send (CTS): If low when the TxEN bit (DO) of
the Command Instruction Control Word (see figure) is
set high, E\nabljls the INS8251, to transmit serial data,
mitter buffer is empty, and' the ,sync char~cter(s!, of .a'
data block are soon to be transmitted automatically as
fillers.
,Receiver Data (RxD): Serial data input from a ,MODEM
or an input/output device.
Receiver Ready (RxRDY): When high, alerts the
INS8080A that the receiver contains a data' character
that is, ready to be inp\Jtto the CPU. The RxROY
output, wh ich is automatically r,eset whenever a char-,
acter is read from the INS8251, can be used as an
interrupt to' the system. For polled operation, the
condition of the RxRDY signal can be tested by the
I NS8080A using a status read operation.
Receiver Clock (RxC): This clock inpOt controls the rate
at which a data,character is to be received. The frequency
and selection of the RxC input is as described above for
the TXC input. Receiver data are clocked into the
INS8,251 on the rising edge of the RxC input.
Vee: +5·volt supply.
'INPUT/OUTPUT SIGNALS
Ground: O·volt reference;
Data (07 - DO)' Bus: This bus cOmprises eight TR I-STATE
input/output lines. The ,bus provides bidirectional
communications between the INS8251 and the
INS8080A. Data are routed to or from the internal data
bus buffer ,upon execution of an INS8080A OUT or
IN instruction, respectively. In addition, control words,
command words and status information are transferred
through the data bus buffer.
OUTPUT SIGNALS
Data Terminal Ready (DTR): General.pu;pose output
which can be set to an active low by programming the
OTR bit (0,) of the Command Instruction Control
Word. However, a low-level OTR output is normally
used for data termimil ready or rate select control.
Requestto Send (RTS): Gen~rSlI-purpose output whicH'
can be set to an active low by programming the RTS bit
(0 5) of the Command Instruction Control Word.
However, the RTS output is normally used for request
to send control in the transmit mode.
Transmitter Data (TxD): Composite serial data output
to, a MODEM or input/output device. The TxO output
is held in the marking state (logic 1) upon a Reset',
operation.
Sync Detect (SYNDET): This pin may be used in the
synchronous mode only: System software can program
SYNOET as either an input or an output. When used as
an output (internal sync detect mode), a high-level
SYNOET indicates that the INS8251 has detected sync
character(s) in the received ser!.al data. The SYNOET
output is automatically ~eset upon a status read opera-tion by the INS8080A. When used as an input (external
sync detect mode), a high-leVel SYNOET causes the
INS8251to start assembling data characters on the
falling edge of the next Rxe'input.
Transmitter Ready (TxRDY): When high, alerts the
INS8080A that the transmitter is ready to accept a data
character. The TxROY output, which is automatically
reset whenever a character is written into the INS8251,
can be used as an interrupt to 'the system. For polled
operation, the condition of the TxROY signal can be
tested by the INS8080A using a status read operation.
,Transmitter Empty (TxE): Goes high to indicate the end
of a, transmit mode. The TxE output is automatically
reset whenever a character is writtenJnto the INS8251.
In the synchronous mode, a high-level TxE output
indicates that a character has not been loaded, the trans-
INS8251 Programming
The system software uses a Mode Il'\struction Control
Word and a Command Instruction Control Word (see
figures) to establish 'the complete'fun'ctional defi'nition
of the lI'i1S8251. These control words must immediately
follow an internal or external reset operation. Once the
Mode Instruction Control Word has been 'written into
the INS8251 by the CPU, sync characters (when applicable) or Command Instruction Control Words may be
inserted as shown in the typical data block transfer
diagram.
Pin Configuration,
02
'03
28
DO
26
vee
Rxe
GNO
26
04
24
OTR
, Os'
",06
23
RTS
22
iiiii
INS8251
21
RESET
Txe
20
eLK
Viii
CS
19
TxO
1,8
TxEMPTY
e/ii
17
m
iiii
f6
SYNOET
IS,
TxROY
07
, .!,'.:
01
27
RxROY
14
0-178
05
06
07
04
EVEN
PARITY
PARITY
ENABLE,
GENERATIONI 1 = ENABLE
CHECK,
= DISABLE
1 = EVEN
0= 000
NO. OF STOP BITS,
DO = INVALID
01 = 1 BIT
10 = 1~ BITS
11 = 28ITS
02
03
I \
I
CHARACTER
LENGTH,
DO = 5 BITS
01 = & BITS
10= 7 BITS
11 = 88ITS
o
DO
01
I
BAUD RATE
FACTOR,
DO SYNC MODE
01
XI
10
Xl&
11
X&4
ASYNCHRONOUS MODE
07
SINGLE
CHARACTER
SYNC,
1 = SINGLE
SYNC
CHARACTER
o = DOUBLE
SYNC
CHARACTER
0&
05
04
03
EXTERNAL
EVEN
PARITY
SYNC
PARITY
ENABLE,
DETECT,
GENERATIONI
1
=
ENABLE
CHECK,
1 = SYNOET
o = DISABLE
ISAN
1 = EVEN
INPUT
0= ODD
o = SYNOET
ISAN
OUTPUT
02
00
01
I \
CHARACTER
LENGTH,
DO = 5 BITS
01 = & BITS
10=7BIT5
11 = BBITS
I
SYNC MODE, 00
SYNCHRONOUS MODE
mode instruction control word format
07
05
04
OJ
02
01
00
REIlUEST
TO SEND
(RTS),
ERROR
RESET
(ER),
1 = RESETS
PE, DE
& FE
ERROR
flAGS
SEND
BREAK
CHARACTER
(SBRK),
1 = FORCES
T.O OUTPUT
lOW
0= NORMAL
OPERATION
RECEIVE
ENABLE
(RxE),
1 = ENABLE
o = DISABLE
DATA
TERMINAL
READY
{DTR},
1 = FORCES
1ffli0UTPUT
lOW
TRANSMIT
ENABLE
(TxEN),
1 = ENABLE
o = DISABLE
0&
INTERNAL
ENTER
HUNT
RESET
(iR),
MODE
(EH),
1 = RETURNS
1 = ENABLES
8251 TO
MODE
SEARCH
FOR SYNC
INSTRUCTION
CHARACTERS WORD FORMAT
M
FORCES
T OUTPUT
lOW
/
command instruction control word format
MODE INSTRUCTION WORD
SYNC CHARACTER 1
SYNC CHARACTER 2
SYNCHRON. DUS MODE
} ONL Y (SEE NOTEI
COMMAND INSTRUCTION WORD
C/D = "0"
C/D
= "1"
CID
=
CID
= "1"
"0"
DATA
CHARACTER(S}
COMMAND INSTRUCTION WORD
DATA
CHARACTER(S}
COMMAND INSTRUCTION WORD
typical data block transfer
0·179
NOTE,
WHEN THE MODE INSTRUCTION
WORD HAS PROGRAMMED THE
INS8251 TO SINGLE SYNC
CHARACTER (BIT 07 = "1't
SYNC CHARACTER 21S
OMITTED. BOTH SYNC
CHARACTERS ARE OMITTED
IN THE ASYNCHRONOUS MODE.
lilGl
INS8251 $tatus
The INS8251 has provisions for allowing the programmer to read the status of the device at any time during the'
functional operation. When the ,C/O input is a high-level, a normal read operation i's executed to read 'this status
information. The figure below shows the bits in the Status Read Word format. Since some of the status word bits
have identical meaning. to external output' pins, the INS8251 can be used in a completely polled environment or in an
interrupt driven environment.
.
: 'D6
D7
DSR
(SEE NDTE)
D5
J
SYNDET
(SEE NOTE)
I
D4
D2
Dl
T.E
(SEE NDTE)
R.RDY
(SEE NDTE)
D3
' FRAMING
PARITY'
OVERRUN
ERRDR
ERRDR
ERRDR
(PE):
(OE):
(FE):
1 • PARITY,
1 • CPU
1 • VALID
ERROR
DOES NOT
STDP BIT
READ A
DETECTED
DETECTED
CHARACTER
ATEND
o • WHEN
OF EVERY
BEFDRE
ER BIT OF
NEXT DNE
CHARACTER
COMMAND
BECOMES
o • WHEN AVAILABLE
INSTRUCTION
,WORD IS
ER BIT
o • WHEN
(04) OF
AT'
ER BIT,OF
COMMAND
INSTRUCTION COMMAND
INSTRUCTION
WORD IS
WORO IS
AT'
AT'
I
DO'
T.RDY
(SEE NOTE)
NOTE:
BITS 00·02,08 II D7
HAVE IDENTICAL
MEANINGS'TO EXTERNAL
OUTPUT PINS:
I
FE, OE II PE FLAGS 00
NOT INHIBIT THE OPERATION
OF THE INSB251
status read word format
Physical Dimensions
-------',
..:-----
r:~~:[J~]~
28·Load Cavity DIPID)
Order Number INS8251D
N.S. Package Numb~ D28A
',,'
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Table of Contents
Introduction
The MICROBUS
The Series 8000 Microprocessor Family CPU Group
Designing Series 8000
Micropro~essor
Family Systems
Memory Components
MAXI·ROMS
Input/Output Components
Peripheral Control Components
Communications Components
Development Support
Programming
MjCROBUS Electrical Specifications
Series 8000 Microprocessor Family Design Example
Additional Information Sources
Data Sheets
••11
CPU Group
• • •..J
Digital.1I0 Components
'.ICJ
Peripheral Control Components
•.•'
Communications Components
APPENDICES
DATA
SHEETS
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