1979_AMI_MOS_Products 1979 AMI MOS Products

1979_AMI_MOS_Products 1979_AMI_MOS_Products

User Manual: 1979_AMI_MOS_Products

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AMII
MOS Products Catalogue
Winter 1979

EDGE INDEX
1 GENERAL INFORMATION

AMI Sales Offices
Domestic Distributors
Domestic Reps
International Reps
Ordering Information
Packaging
Terms of Sale
Product Assurance Program
MOS Processes

I
I
I
I

2 MEMORIES
RAMs, ROMs and EPROMs

3 S6800 FAMILY
4 S2000 FAMILY

5 S9900 FAMILY
6 TELECOMMUNICATIONS
7 CONSUMER INTERFACE PRODUCTS
8 APPLICATION NOTES

I
I
I

Copyright© 1978 American Microsystems, Inc. (All rights reserved.)
Trade Marks Registered®
Information furnished by AMI in this catalog is believed to be accurate and reliable. Devices
sold by AMI are covered by the warranty and patent indemnification provisions appearing in
its Terms of Sale. AMI makes no warranty, express, statutory, implied, or by description
regarding the information set forth herein or regarding the freedom of the described devices
from patent infringement. AMI reserves the right to change specifications and prices at any
time and without notice. Advanced Product Desription means that this product has not been
produced in volume, the specifications are preliminary and subject to change, and device
characterization has not been done. Therefore, prior to designing any product into a system, it
is necessary to check with AMI for current information.
This catalog prepared for American Microsystems, Inc., by Briteday, Inc.

MOSILSI is the Business of AMI
... and MOS/LSI is AMI's only business. The first company to produce commercial quantities of MOS circuits
starting in 1966, AMI has ever since been among the leaders in circuit design, process technology and new
product and market development. Today, the company is a major producer of standard products for the electronic data processing, telecommunications, and consumer product industries.
DESIGN EXPERIENCE - Many areas of applications in which MOS is used today were pioneered with an
AMI-designed device. This accumulated experience results in a line of high performance standard products
and imaginatively designed, cost-effective custom circuits.
PROCESS VERSATILITY - AMI's head start in the industry gives it a mature capability in everyone of
the major production processes: P-channel - high voltage and ion implanted metal gate, and silicon gate;
N-channel - silicon gate, ion implanted silicon gate with depletion loads, high density and narrow geometry
"H" MOS; and CMOS - metal and silicon gate, and high density, isoplanar silicon gate. AMI's new patented
process, VMOS, is already producing high speed, low power state-of-the-art memory products.
PRODUCTION CAP ABILITY - AMI has three major facilities worldwide. Headquarters in Santa Clara,
California has 327,000 square feet of office and manufacturing space and about 1,000 employees. Administration, R&D, the majority of the engineering staff, one of the company's two wafer fabrication facilities, pilot
assembly and a final test facility are located there. The other major fabrication facility is at Pocatello, Idaho
with 103,000 square feet and about 600 employees. The plant includes an engineering group, four fabricating
lines and some final test activity. Located at Inchon, Korea is KMI, the company's major circuit assembly
plant. It covers 116,000 square feet, employs about 1,300 persons. This combination of facilities can produce
over 2,000,000 LSI circuits per month using the latest production equipment to maximize yields in today's
more complex circuits.
PRODUCT RELIABILITY - By designing reliability into the product - a standard procedure for AMI, the
most experienced designer of custom MOS circuits - problems are minimized or eliminated. Process control
(and we run more processes than any other MOS manufacturer) is the second most important step in maintaining our reputation for reliability. Design and process control are buttressed by a closed feedback loop that
continually collects AMI internal data and field data from our customers to analyze and solve design, layout
and process problems. These activities are further supported by accelerated tests to determine failure rates
and the activation energies for observed failure modes.
IT'S STANDARD AT AMI - The company's dedication to the design and manufacture of high performance
MOS/LSI products is reflected in the variety of products listed in this catalog.

AMI and Made-to-Order MOS
Since 1966, AMI has designed and manufactured over 1,000 custom MOS circuits. The largest design engineering staff in the industry has helped to keep AMI in the number one position among custom MOS producers.
If your product can be controlled by an MOS circuit, and you plan to manufa~ture it in high volume, you should
contact your nearest AMI Sales Office or the main office in Santa Clara, California. AMI will be happy to
discuss the possibility of designing a custom circuit for your application, or manufacturing such a circuit from
your tooling.

iii

Numerical Index

Device

Page

Device

Page

Device

Page

TCK 100 ..........
81103A ...........
81424A ...........
81424C ........ ' ...
81425A ...........
81427A ...........
81856 ............
81883 ............
81998A ...........
81998B ...........
810110 ...........
810111 ...........
810129 ...........
810130 ...........
810131 ...........
810377 ...........
810430 ...........
82000 ............
82000A ...........
82114 ............
82114H ...........
82147 ............
82150 ............
82150A ...........
82193 ............
82200 ............
82200A ...........
82222 ............
82222A ...........
82350 ............
82400 ............
82400A ...........
82559A ...........
82559B ...........
82559C ...........
82559D ...........
82560A . . . . . . . . . ..
82560B ...........
82561 ............
82562 ............
82567 ............
82600 ............

7.9
2.3
7.2
7.2
7.2
7.2
7.2
3.170
7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2
4.1
4.2
2.4
2.7
2.10
42
4.2
7.2
4.2
4.2
2.2
2.2
3.171
4.2
4.2
6.3
6.3
6.3
6.3
6.13
6.13
6.21
6.29
7.2
7.3

82601 ............
82709 ............
82733 ............
82742 ............
82743 ............
82811 ............
82900 ............
82901 ............
83514 ............
84006 ............
84008 ............
84015 ............
84017 ............
84025 ............
84028 ............
84216B ...........
84264 ............
84532 ............
84716 ............
85101 ............
85204A . . .. . .. . ...
85232 ............
850145 ...........
850240 ...........
850241 ...........
850242 ...........
850243 ...........
850244 ...........
86508 ............
86508A . . . . . . . . . ..
86518 ............
86518A . . . . .. . .. ..
86800 ............
868AOO ...........
868BOO ...........
86801 ............
86802 ............
86809 ............
86810A ...........
86810A-1 .........
868A10 ...........
868B10 ...........

7.3
7.2
7.2
7.26
7.26
6.39
6.40
6.40
2.3
2.3
2.3
2.13
2.16
2.13
2.19
2.35
2.38
2.47
2.48
2.20
2.49
2.3
7.2
7.2
7.2
7.2
7.2
7.2
2.25
2.25
2.30
2.30
3.3
3.3
3.3
3.21
3.22
3.31
3.32
3.32
3.36
3.36

86820 ............
86821 ............
868A21 .. . .. . . . . ..
868B21 ...........
86830 ............
86831 ............
86831A . . . . . . . . . ..
86831B ...........
86831C ...........
86834 ............
86840 ............
86846 ............
86850 ............
868A50 . . . . . . .. . ..
868B50 .... . . . . . ..
86852 ............
86854 ............
868A54 .. .. . . . . . ..
868047 ...........
868332 ...........
868488 ...........
88564 ............
88771 ............
88773 ............
88865 ............
88890 ............
88996 ............
89260 ............
89261 ............
89262 ............
89263 ............
89264 ............
89265 ............
89266 ............
89660 ............
89900 ............
89901 ............
89902 ............
89903 ............
89940 ............
89980 ............
89981 •............

3.2
3.39
3.39
3.39
2.3
2.3
2.41
2.41
2.3
2.55
3.53
3.68
3.88
3.98
3.98
3.109
3.124
3.124
3.147
2.44
3.159
2.3
2.3
2.3
2.3
7.2
2.3
7.13
7.13
7.19
7.13
7.13
7.13
7.19
7.2
5.3
5.33
5.44
5.68
5.69
5.70
5.70

Functional Index

Device

Page

RAMs
81103A ...........
82114 ............
82114H ...........
82147 ............
82222 ............
82222A ...........
84006 ............
84008 ............
84015 ............
84017 ............
84025 ............
84028 ............
85101 ............
86508 ............
86508A . . . . . . . . . ..
86518 ............
86518A . . . . . . . . . ..
868AlO ...........
868B10 ...........

2.3
2.4
2.7
2.10
2.2
2.2
2.3
2.3
2.13
2.16
2.13
1.19
2.20
2.25
2.25
2.30
2.30
3.36
3.36

ROMs
83514 ............
84216B ...........
. 84264 ............
85232 ............
86830 ............
86831 ............
86831A ........ '"
86831B ........ ...
86831C ...........
868332 ...........
88564 ............
88771 ............
88773 ............
88865 ............
88896 ............

2.3
2.35
2.38
2.3
2.3
2.3
2.41
2.41
2.3
2.44
2.3
2.3
2.3
2.3
2.3

EPROMs
84532 ............
84716 ............
85204A ...........
86834 ............

2.47
2.48
2.49
2.55

Character Generator
88564 ............ 2.3

Page

Device

86800 Microcomputer
Family
86800 ............ 3.3
868AOO ........... 3.3
868BOO ........... 3.3
86801 ............ 3.21
86802 ............ 3.22
86809 ............ 3.31
86810A ........... 3.32
86810A-1 ......... 3.32
868A10 ........... 3.36
868B10 ........... 3.36
86820 ............ 3.2
86821 ............ 3.39
868A21 .. .. .. . .... 3.39
868B21 ........... 3.39
86830 ............ 2.3
86831 ............ 2.3
86831A . .. .. .. .... 2.41
86831B ........... 2.41
86831C ........... 2.3
86834 ............ 2.55
86840 ............ 3.53
86846 ............ 3.68
86850 ........... _ 3.88
868A50 .. .. .. .. ... 3.98
868B50 .. , .. .. .... 3.98
86852 ............ 3.109
86854 ............ 3.124
868A54 ......... " 3.124
868047 ........... 3.147
868332 ........... 2.44
868488 ........... 3.159
82000 Family
82000 ............
82000A ...........
82150 ............
82150A ...........
82200 ............
82200A ...........
82400 ............
82400A ...........

4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2

89900
89900
89901
89902
89903
89940
89980
89981

5.3
5.33
5.44
5.68
5.69
5.70
5.70

Family
............
............
............
............
............
............
............

Data Communication
Circuits
81883 ............ 3.170
82350 ............ 3.171

Device

Page

Telecommunication
82559A ...........
82559B ...........
82559C ...........
82559D ...........
82560A . . . . . . . . . ..
82560B ...........
82561 ............
82562 ............
82811 ............
82900 ............
82901 ............

6.3
6.3
6.3
6.3
6.13
6.13
6.21
6.29
6.39
6.40
6.40

Remote Control Circuits
82600 ............ 7.3
82601 ............ 7.3
82742 ............ 7.26
82743 ............ 7.26
Interface Circuits
fTouchControU
TCK100 ..........
89260 ............
89261 ............
89262 ............
89263 ............
89264 ............
89265 ............
89266 ............

7.9
7.13
7.13
7.19
7.13
7.13
7.13
7.19

Organ Circuits
810110 ...........
810111 ...........
810129 ...........
810130 ...........
810131 ...........
810377 ...........
810430 ...........
850145 ...........
850240 ...........
850241 ...........
850242 ...........
850243 ...........
850244 ...........

7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2
7.2

Watch/Clock Circuits
81424A ........... 7.2
81424C ........... 7.2
81425A ........... 7.2
81427A ........... 7.2
81856 ............ 7.2
81998A ........... 7.2
81998B ........... 7.2
82709 ............ 7.2
82733 ............ 7.2

1
General Information

AMI Sales Offices
Domestic Distributors
Domestic Reps
International Reps
Ordering Information
Packaging
Terms of Sale
Product Assurance Program
MOS Processes

Sales Offices

DOMESTIC
725 So. Central Expressway, Suite A-9
Richardson, Texas 75080
Tel: (214) 231-5721
(214) 231-5285
TWX: 910-867-4766

Western Area
100 East Wardlow Rd., Suite 203
Long Beach, California 90807
Tel: (213) 595-4768
TWX: 910-341-7668
3800 Homestead Road
. Santa Clara, California 95051
Tel: (408) 249-4550
TWX: 910-338-0018
20709 N.E. 232nd Avenue
Battleground, Washington 98604
Tel: (206) 687-3101

Eastern Area
237 Whooping Loop
Altamonte Springs, Florida 32701
Tel: (305) 830-8889
TWX: 810-853-0269
1420 Providence Turnpike, Suite 220
Norwood, Massachusetts 02062
Tel: (617) 762-0726
TWX: 710-336-0073
20 Robert Pitt Drive, Room 212
Monsey, N-ew York 10952
Tel: (914) 352-5333
TWX: 710-577-2827
Axe Wood East
Butler & Skippack Pikes, Suite 230
Ambler Pennsylvania 19002
Tel: (215) 643-0217
TWX: 510-661-3878

Central Area
500 Higgins Road, Suite 210
Elk Grove Village, Illinois 60007
Tel: (312) 437-6496
TWX: 910-222-2853
Suite Number 204
408 South 9th Street
Noblesville, Indiana 46060
Tel: (317) 773-6330
TWX: 810-260-1753
29200 Vassar Ave., Suite 303
Livonia, Michigan 48152
Tel: (313) 478-9339
TWX: 810-242-2903
INTERNATIONAL
England
AMI Microsystems, Ltd.
108 A Commercial Road
Swindon, Wiltshire
Tel: (793) 31345 or 25445
TLX: 851-449349
France
AMI Microsystems, S.A.R.L.
124 A venue de Paris
94300 Vincennes ,France
Tel: (01) 374 00 90
TLX: 842-670500
Holland
AMI Microsystems, Ltd.
Calandstraa t 62
Rotterdam, Holland
Tel: 010-36 14 83
TLX: 844-27402

Italy
AMI Microsystems, S.p.A.
Via Pascoli 60
20133 Milano
Tel: 29 37 45 or 2360154
TLX: 843 32644
Japan
AMI Japan Ltd.
502 Nikko Sanno Building
2-5-3, Akasaka
Minato-ku, Tokyo 107
Tel: Tokyo 586-8131
TLX: 781-242-2180 AMI J
West Germany
AMI Microsystems, GmbH
Rosenheimer Strasse 30/32, Suite 237
8000 Munich 80, West Germany
Tel: (89) 483081
TLX: 841-522743
Rapifax: (89) 486591

1.2

Domestic Distributors

ALABAMA
Huntsville
Resistacap (205) 881-9270
ARIZONA
Phoenix
Kierulff (602) 243-4101
Sterling Electronics (602) 258-4531
R.V. Weatherford Co. (602) 272-7144
CALIFORNIA
Anaheim
R.V. Weatherford Co. (714) 634·9600
Glendale
R. V. W ea therford Co. (213) 849-3451
Irvine
Schweber Electronics (213) 537-4320 or
(714) 556-3880
Los Angeles
Kierulff (213) 685-5511
Palo Alto
Kierulff (415) 968-6292
R.V. Weatherford Co. (415) 493-5373
Pomona
R.V. Weatherford Co. (714) 623-1261 or
(213) 966-8461
San Diego
Intermark Electronics (714) 279-5200
Kierulff (714) 278-2112
R.V. Weatherford Co. (714) 278-7400
Santa Ana
Intermark Electronics (714) 540-1322 or
(213) 436-5275
Sunnyvale
Intermark Electronics (408) 738-1111
Western Microtechnology (408) 737-1660
Tustin
Kierulff (714) 731-5711
COLORADO
Denver
Kierulff (303) 371-6500
Englewood
R.V. Weatherford Co. (303) 770-9762
Wheatridge
Century Electronics (303) 424-1985
CONNECTICUT
Danbury
Schweber Electronics (203) 792-3500
Hamden
Arrow Electronics (203) 248-3801
FLORIDA
Ft. Lauderdale
Arrow Electronics (305) 776-7790
Hollywood
Schweber Electronics (305) 927-0511
Palm Bay
Arrow Electronics (305) 725-1480
St. Petersburg
Kierulff Electronics (813) 576-1966
GEORGIA
Atlanta
Schweber Electronics (404) 449-9170
Doraville
Arrow Electronics (404) 455-4054
ILLINOIS
Elk Grove Village
Kierulff (312) 640-0200
Schweber Electronics (312) 593-2740
Schaumburg
Arrow Electronics (312) 893-9420
Westmont
RIM Electronics (312) 323-9670

INDIANA
Indianapolis
RIM Electronics (317) 247-9701
LOUISIANA
Metairie
Sterling Electronics (504) 887-7610
MARYLAND
Baltimore
Arrow Electronics (301) 247-5200
Gaithersburg
Schweber Electronics (301) 840-5900
MASSACHUSETTS
.
Natick
Future Electronics Corp. (617) 237-6340
Waltham
Schweber Electronics (617) 890-8484
Sterling Electronics (617) 894-6200
Woburn
Arrow Electronics (617) 933-8130
MICHIGAN
Ann Arbor
Arrow Electronics (313) 971-8220
Livonia
Schweber Electronics (313) 525-8100
Wyoming
RIM Electronics (616) 531-9300
MINNESOTA
Bloomington
Arrow Electronics (612) 887-6400
Eden Prairie
Schweber Electronics (612) 941-5280
NEW HAMPSHIRE
Manchester
Arrow Electronics (603) 668-6968
NEW JERSEY
Moorestown
Arrow Electronics (609) 235-1900
Perth Amboy
Sterling Electronics (201) 442-8000
Saddle brook
Arrow Electronics (201) 797-5800
Somerset
Schweber Electronics (201)469-6008
NEW MEXICO
Albuquerque
Century Electronics (505) 292-2700
Sterling Electronics (505) 345-6601
NEW YORK
Farmingdale
Arrow Electronics (516) 694-6800
Fishkill
Arrow Electronics (914) 896-7530
Rochester
Schweber Electronics (716) 424-2222
Westbury
Schweber Electronics (516) 334-7474
NORTH CAROLINA
Kernersville
Arrow Electronics (919) 996-2039
OHIO
Beechwood
Schweber Electronics (216) 464-2970
Kettering
Arrow Electronics (513) 253-9176
Solon
Arrow Electronics (216) 248-3990

1.3

OREGON
Beaverton
Parrott (503) 641-3355
PENNSYLVANIA
Horsham
Schweber Electronics (215) 441-0600
TEXAS
Dallas
Component Specialities, Inc.
(214) 357-6511
Schweber Electronics (214) 661-5010
Sterling Electronics (214) 357-9131
R.V. Weatherford Co. (214) 243-1571
Houston
Component Specialities, Inc.
(713) 771-7237
Schweber Electronics (713) 784-3600
Sterling Electronics (713) 627-9800
R.V. Weatherford Co. (713) 688-7406
UTAH
Salt Lake City
Century Electronics (801) 972-6969
Kierulff (801) 973-6913
VIRGINIA
Richmond
Sterling Electronics (804) 226-2190
WASHINGTON
Seattle
Kierulff (206) 575-4420
R.V. Weatherford Co. (206) 575-1340
WISCONSIN
Oak Creek
Arrow Electronics (414) 764-6600
CANADA
Alberta
Edmonton
Bowtek Electric Co. (403) 452-9050
British Columbia
Vancouver
Bowtek Electric Co. (604) 736-1141
Manitoba
Winnepeg
Bowtek Electric Co. (204) 633-9525
Ontario
Downsview
Cesco Electronics, Ltd. (416) 661-0220
Future Electronics Corp. (416) 663-5563
Ottawa
Cesco Electronics, Ltd. (613) 729-5118
Future Electronics Corp. (613) 820-9471
Quebec
Montreal
Cesco Electronics, Ltd. (514) 735-5511
Future Electronics, Corp. (514) 735-5775
Quebec
Cesco Electronics, Ltd. (418) 524-4641

Domestic Reps

ALABAMA
Huntsville
Rep. Inc.
Tel: (205) 881-9270
TWX: 810-726-2101
ARIZONA
Phoenix
Hecht. Henschen & Assoc .. Inc.
Tel: (602) 275-4411
TWX: 910-951-0635
CALIFORNIA
Long Beach
Application Representatives
Tel: (213) 594-6608
TWX: 910-341-6599
Mt. View
Thresum Associates. Inc.
Tel: (415) 965-9180
TWX: 910-379-6617
San Diego
Hadden Associates
Tel: (714) 565-9445
TWX: 910-335-2057
COLORADO
Parker
R 2Marketing
Tel: (303) 841-5822
CONNECTICUT
Orange
CPS Corp.
Tel: (203) 795-3515
GEORGIA
Tucker
Rep. Inc.
Tel: (404) 938-4358
ILLINOIS
Elk Grove Village
Oasis Sales Tel: (312) 640-1850
TWX: 910-222-2170
INDIANA
Ft. Wayne
Technical Representatives. Inc.
Tel: (219) 484-1432
Indianapolis
Technical Representatives
Tel: (317) 849-6454
TWX: 810-260-1792
IOWA
Cedar Rapids
Comstrand. Inc.
Tel: (319) 377-1575
KENTUCKY
Louisville
Technical Representatives. Inc.
Tel: (502) 451-9818
MARYLAND
Baltimore
Coulbourn DeGreif. Inc.
Tel: (301) 247-4646
TWX: 710-236-9011

MASSACHUSETTS
Lexington
Circuit Sales Company
Tel: (617) 861-0567
MINNESOTA
Minneapolis
Comstrand. Inc.
Tel: (612) 788-9234
TWX: 910-576-0924
MISSOURI
Grandview
Beneke & McCaul
Tel: (816) 765-2998
St. Louis
Beneke & McCaul
Tel: (314) 434-6242
NEW YORK
Clinton
Advanced Components
Tel: (315) 853-6438
Endicott
Advanced Components
Tel: (607) 785-3191
Melville
Astrorep. Inc.
Tel: (516) 423-2266
TWX: 510-226-6147
NEW YORK
North Syracuse
Advanced Components
Tel: (315) 699-2671
TWX: 710-541-0439
Scottsville
Advanced Components
Tel: (716) 889-1429
NORTH CAROLINA
Raleigh
Rep. Inc.
Tel: (919) 851-3007
OHIO
Centerville
S.A.1. Marketing
Tel:(513) 435-3181
TWX: 810-459-1647
Shaker Heights
S.A.1. Marketing
Tel: (216) 751-3633
TWX: 810-421-8289
Zanesville
S.A.1. Marketing
Tel: (614) 454-8942
OKLAHOMA
Oklahoma City
Ammon & Rizzos
Tel: (405) 942-2552
OREGON
Portland
SD-R2 Products & Sales
Tel: (503) 246-9305

1.4

PENNSYLV ANIA
Pittsburgh
S.A.1. Marketing
Tel: (412) 782-5120
TEXAS
Austin
Ammon & Rizos
Tel: (512) 454-5131
Dallas
Ammon & Rizos
Tel: (214) 233-5591
TWX: 910-860-5137
Houston
Ammon & Rizos
Tel: (713) 781-6240
TWX: 910-881-6382
TENNESSEE
Jefferson City
Rep. Inc.
Tel: (615) 475-4105
TWX: 810-570-4203
UTAH
Salt Lake City
R2 Marketing
Tel: (801) 972-5646
TWX: 910-925-5607
VIRGINIA
Charlottesville
Coulbourn DeGreif. Inc.
Tel: (804) 977-0031
WASHINGTON
Bellevue
SD-R2 Products & Sales
Tel: (206) 747-9424 or (206) 624-2621
TWX: 810-443-2483
WISCONSIN
Menomonee Falls
Oasis Sales
Tel: (414) 251-9431
CANADA
Ottowa, Ontario
Cantec Reps, Inc.
Tel: (613) 225-0363
TWX: 610-562-8967
Point Claire, Quebec
Cantec Reps, Inc.
Tel: (514) 694-4049
Tlx: 58-22790
Toronto, Ontario
Cantec Reps. Inc.
Tel: (416) 675-2460 or 2461
TWX: 610-492-2655

International Reps

AUSTRALIA
Rifa Pty. Ltd.
202 Bell Street
Preston, Victoria 3072
Tel: (03)480 1211
TLX: AA31001
BRAZIL
Datronix Electronica Ltda.
Av. Pacaembu, 746 - Conj. 11
Sao Paulo
Tel: 209-0134
TLX: 391-1122372
CENTRAL AMERICA
ROW, Inc.
3421 Lariat
Shingle Springs, Calif. 95682
Tel: (916) 677-2827
ENGLAND
Ritro Electronics {U.K.)
Grefell Place
Maidenhead
Berkshire
Tel: (0628) 36227
FINLAND
OY Atomica AB
PL 22
02171 Espoo 17
Tel: 80-423533
TLX: 12-1080
FRANCE
Produits Electronique
Professionals S.A.R.L.
2 - 4 Rue Barthelemy
92120 Montrouge
Tel: 8353320
TLX: 204534
HOLLAND
AMI Microsystems, Inc.
Calandstraat 62
Rotterdam
Tel: 010-36 14 83
TLX: 844-27402
HONG KONG
Apcom Systems, Ltd.
1201 Kimberly Center
35 Kimberly Road
Kowloon
Tel: 3-694659
TLX: 64095
INDIA
ROW International
149 Kimble Rd.
Los Gatos, Calif.
Tel: (408) 354-7698
ISRAEL
CVS Technologies {1974) Ltd.
9 Jobotinsky St.
Box 946 Bnei Brak
Tel: 799156
TLX: 341109

ITALY
Paolo Meoni & Associates
Giovanni Pascoli 60
20133 Milano
Tel: 29 37 45
TLX: 843-32644
JAPAN
Micro-Systems, Inc.
15-29 Mita 4-Chome
Minato-ku, Tokyo 108
Tel: (03) 452-4994
Matsushita Electric
Trading Company, Ltd.
71, 5-Chome, Kawaramachi
Higashi-ku
Osaka
Tel: (06) 204-5510
TLX: 781-63417
MALAYSIA
Dynamar International Ltd.
208 Shaw House, Orchard Rd.
Singapore 9,
Tel: 2351139
TLX: RS26283
MEXICO
ROW, Inc.
3421 Lariat
Shingle Springs, Calif. 95682
Tel: (916) 677-2827
NEW ZEALAND
David P. Reid {NZ) Ltd.
Box 2630, Auckland 1
Tel: 492-189
TLX: 791 2612
SINGAPORE
Dynamar International Ltd.
208 Shaw House, Orchard Rd.
Singapore 9 Tel: 2351139
TLX: RS 26283
SOUTH AFRICA
Tecnetics
P.O. Box 56310
Pinegowrie 2123, Transvaal
Johannesburg
Tel: 48-5712
TLX: 960-80838
SOUTH AMERICA
ROW, Inc.
3421 Lariat
Shingle Springs, Calif. 95682
Tel: (916) 677-2827
SWEDEN
A.B. Rifa
Fack, S-16300 Spanga
Tel: (08) 751 00 20
TLX: 13690

1.5

SWITZERLAND
W. MoorAG
Bahnstrasse 58,
8105 Regensdorf
Zurich
Tel: (01) 8406644
TLX: 52042
TAIWAN
Dynamar {Taiwan) Ltd.
2nd Fir., No. 14, Lane 164
Sung Chiang Road
Taipei,104
Tel: 541-8252 thru 54
TLX: 785-11064
WEST GERMANY
Aktiv Electronics GmbH
Leonorenstrasse 49
D-1000 Berlin 46
Tel: (030) 771 4408
TLX: 185327
Gustav Beck KG
Eltersdorfer Strasse 7
8500 Nurnberg 15
Tel: (0911) 34966
TLX: 622334
U1tratronik
Munchenerstr.6
D-8031 Oberalting-Seefeld
Tel: (08152) 7696
TLX: 526459
Ditronic, GmbH
1m Asemwald 48
D-7000 Stuttgart 70
Tel: (0711) 724844
TLX: 7255638
Miktrotec, GmbH
Johannesstr.91
D-7000 Stuttgart 1
Tel: (0711) 22807
TLX: 722818
YUGOSLAVIA
Iskra Standard
Celovska 122
61000 Ljubljana
Tel: (061) 551093
TLX: 31300 YU-ISKRA

Ordering Information

Any product in this MaS Products Catalog can be ordered using the simple system described below. With
this system it is possible to completely specify any
standard device in this catalog in a manner that is
compatible with AMI's order processing methods.
The example below shows how this ordering system
works and will help you to order your parts in a manner that can be expedited rapidly and accurately.

triticy damage under all normal handling conditions.
Either container is compatible with standard automatic IC handling equipment.

Any device described in this catalog is an AMI Standard Product. However, ROM devices that require
mask preparation or programming to the requirements
of a particular user, devices that must be tested to other
than AMI Quality Assurance standard procedures, or
other devices requiring special masks are sold on a
negotiated price basis.

All orders (except those in sample quantities) are normally shipped in plastic carriers or aluminum tube
containers, which protect the devices from static elec-

S6821A-1P

Device Number - prefix S, followed by four (or five*)
numeric digits that define the basic device ~ype. If
there are versions to the basic device, the numeric
digits will be followed by additional alphanumeric
digits, in this example A -1. The last digit should always
be followed by a space.

Package Type - a single letter designation which identifies the basic package type. The letters are coded as
follows:
P - Plastic package
E - Cer-DIP package
S - SLAM package
C - Ceramic (three-layer) package
T - TO type package

*Organ Circuits

1.6

Packaging
PLASTIC PACKAGE

The AMI plastic dual-in-line package is the equivalent of the widely accepted industry standard, refined by AMI
for MOS/LSI applications. The package consists of a plastic
body, transfer -molded directly onto the assembled lead frame
and die. The lead frame is Kovar or Alloy 42, with external
pins tin plated. Internally, there is a 50j1in. gold spot on the
die attach pad and on each bonding fingertip. Gold bonding
wire is attached with the thermocompression gold ball bonding
technique.
Materials of the lead frame, the package body, and the
die attach are all closely matched in thermal expansion coefficients, to provide optimum response to various thermal
conditions. During manufacture every step of the process is
rigorously monitored to assure maximum quality of the AMI
plastic package.
Avaliable in: 8, 14, 16, 18, 22, 24, 28 and 40 pin
configurations.

Cer-DIP PACKAGE

The Cer-DIP dual-in-line package has the same high
performance characteristics as the standard three-layer ceramic
package, yet approaches plastic in cost. It is a military approved
type package, with excellent reliability characteristics. Although
the Cer-DIP concept has been around for a number of years,
AMI leads the technology with this package, having eliminated
the device instability and corrosion problems of earlier Cer-DIP
processes.
The package consists of an Alumina (A1 2 0 3 ) base and
the same material lid, hermetically fused onto the base with
low temperature solder glass. Inert gasses are sealed inside the
die cavity.
Available in: 16, 18,22,24,28 and 40 pin configurations.

1.7

GOLD SONDlNG Wi RE
GOLD PLATING
BODY

LEAD FRAME
SEALANT
TtNPLATING

Packaging
SLAM PACKAGE
The SLAM (single layer metallization) dual-in-line package is an AMI innovation that offers a lower cost alternative
to three-layer ceramic packages, without sacrifice of performance or reliability.
The SLAM package uses the same basic materials as
ceramic, but is constructed in a simpler and thereby more
reliable manner. It uses a 96% Alumina base, one basic
refractory metallization layer, coated with an Alumina passivation layer, and brazed-on Kovar leads. The leads are suitable
for either socket insertion or soldering. Either a ceramic or a
Kovar lid is used to hermetically seal the package. The ceramic
lid is attached with an epoxy resin sealant, but a gold -silicon
eutectic solder is used for Kovar lids.
Avaliable in: various 14 to 40 pin configurations.

PLATED
KOVAR
LEADS

Ni PLATING
REFRACTORY
METAL

EPOXY SEAL PACKAGE

CERAMIC PACKAGE

Industry standard high performance, high reliability
package, made of three layers of A1 2 0 3 ceramic and nickelplated refractory metal. Either a low temperature glass sealed
ceramic lid or a gold tin eutectic sealer Kovar lid is used to form
the hermetic cavity of this package. Package leads are available
with gold over nickle or tin plating for socket insertion or
soldering.

1.8

Ni
PLATING
REFRACTORY
METALLIZATION

Packaging
PIN 1 IDENTIFIER
PIN 1 IDENTIFIERb

0'040

0.065

0100 TYP _

'-Jj1L

g:g~~L_
.

90 MIN
0.0

I 0.400I MAX

0.280
0.220

g:~~gIIBEND

110.200 MAX

o.oro."

,R'r-,'\

d
W MAXJ

L JL g:g6~

'rr

a 200 MAX

1- 0280

o'~~~:~.j, .ot -O~OO;:l
f.

000,,0.026
,
0.090 MIN t

0.030

"
_ ' .0.310

~ r- OM'012N0l.fj~'

"""'''"

0.290

BEND
"
0012
;,-",- 0:008

'"'

15" MAX

1.9

Packaging
I8-PIN CERAMIC

I8-PIN Cer-DIP

PIN 1 IDENTIFIER

MARKINGS
ON LID
SURFACE

0200 MAX
.

;:-JJHo
~

0090

0.295
0.275

r-]

0.295
0.250

8 E N D t J 0.290
0.310

,F3t

200 MAX

0020 MIN

0.310
.0.290

0
15 MAX

: : ;=r

ONLY

0
15 MAX,,/

JLO.012
0.008

22-PIN PLASTIC

L-

Jla'012
0.008

22-PIN Cer-DIP
PIN 1 IDENTIFIER

PIN 1 IDENTIFIER

;~r

0015

;:-J¥-

11-_ _""- 12

0090

0200 MAX

''--1
0.3----'95

I--

0.355

-,1

0015MIN

BENDto.410i
0.390

I---

:1E3~

150MAX~ ~
22-PIN CERAMIC
PIN 1 IDENTIFIER

0.020
0. 015

PIN 1 IDENTIFIER-

J-

0.090 MIN

--1'

","M"

1__

24-PIN PLASTIC

-I:

1
0.100

Jlg:~

MARKINGS

1.270MAX

OrJ_

0065

0.020
11

0200 MAX
.

l.... 0.395
0.375

0.090 MIN

>- 0.410---1

0.020MIN--iL

0.390

15° MAX,,'

I-

J~J:
I

I-

AJI~

0:040

0.016

U
---.

ON LID
~~ SURFACE
ONLY

0.200 MAX

0.020 MIN

BEND

0.5BO_J
0.515

1- g:~~g I

¥=~\JI'

iI
~ I-

15°MAX

I - g:g6~

1.10

0.012
1--O.OOB

Packaging
24-PIN Cer-DIP

24-PIN SLAM

PIN 1 IDENTIFIER

24-PIN CERAMIC
PIN 1 IDENTIFIER

28-PIN PLASTIC

lib

----r

MARKINGS
ON LID
SURFACE
ONLY

0.100

0.020
0.Q15

1
I

0.090 MIN -

0.595
0.575

---'- 0.200 MAX -

0.610
0.590

0.020 MIN - -

28-PIN Cer-DIP

40-PIN PLASTIC

PINlIDENTIFIER\

0.065

O·04°i
~;

0.020

--1_.•

1__

0015

1-1 [
0.090MINJ

- -

0.590---1
0.480

0.015 MIN --11--+0.200 MAX

r-- ~:~~~ -+

8END

.:R
I

150MAX~' ~

-JL g~

1.11

Packaging
40-PIN SLAM

40-PIN CERAMIC
PIN 1 IDENTIFIER ........

g:~l

l~'"

, -,--- _L~

II;
;
H--o.200MAXFo.575

O.59S

0.090 MIN -

g:~

O.020MIN - -

~
40-PIN CER-DIP

64-PIN CERAMIC

L.-

INDEX

1-l~O.020MIN
0.120 MIN

~OT

PtNSPAC5NGO.1DOT.P

IseeN'''''L

0.020
0.015-L

0.090 MIN.J

0.040

0015MIN.r

20
0.200 MAX.
BEND

,21

L ~:!:~ --J

O.614

.....L...._ _ _ _ 33

~32,-

1,0.608-,1

:1'

'-I/ ~

15' MAX.

o.~

I~.

0.020

0.012
0.008

NOTE A. EaCtipIMcenlerllnelslocaledwlllllnOD10oll!s!ruelonglludlnalPOtlllDn

~
~
1.....--0.900· 0.020----+1

1~~

1.12

SEATING
PLANE

_\l_~~~O

Terms of Sale

PROVISION IS STATED IN LIEU OF ANY OTHER EXPRESSED, IMPLIED,
OR STATUTORY WARRAIHY AGAINST INFRINGEMENT AND SHALL BE
THE SOLE AND EXCLUSIVE REMEDY FOR PATENT INFRINGEMENT OF
ANY KIND

ACCEPTANCE: THE TERMS OF SALE CONTAINED HEREIN APPLY TO
ALL QUOTATIONS MADE AND PURCHASE ORDERS ENTERED INTO BY
THE SELLER. SOME OF THE TERMS SET OUT HERE MAY DIFFER FROM
THOSE IN BUYER'S PURCHASE ORDER AND SOME MAY BE NEW. THIS
ACCEPTANCE IS CONDITIONAL ON BUYER'S ASSENT TO THE TERMS
SET OUT H[RE IN LIEU OF THOSE IN BUYER'S PURCHASE ORDER.
SELLER'S FAILURE TO OBJECT TO PROVISIONS CONTAINED IN ANY
COMMUNICATION FROM BUYER SHALL NOT BE DEEMED A WAIVER
OF THE PROVISIONS OF THIS ACCEPTANCE. ANY CHANGES IN THE
TERMS CONTAINED HEREIN MUST SPECIFICC;LLY BE AGREED TO IN
WRITING BY AN OFFICER OF THE SELLER BEFORE BECOMING BIND
ING ON EITHER THE SELLER OR THE BUYER. All orders or contracts must
be approved ami accepted by the Seller at Its ilOlne office. These terms shall be
applicable whether or not they are attached to or enclosed with the products to
be sold or solei her cLJl1cler. Prices for the Items described dbove and acknowledged

able opportunity to Inspect the material. No material shall be returned without
Seller's consent. Seller's Return Material Authorization form must accompanv
such returned material.

PAYMENT:
(a) Unless otherwise agreed, all inVOices are due and payable
from date of inVOice. No discounts are authorized. Shipments,
performance of work shall at all times be sublect to the approval of the

products which shall, within one (11 year after shipment, be returned to the
Seller's factory of origin, transportation charges prepaid, and which are, after
examination, disclosed to the Seller's satisfaction to be thus defective. THIS
WARRANTY IS EXPRESSED IN LIEU OF ALL OTHER WARRANTIES,
EXPRESSED, STATUTORY, OR IMPLIED, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND OF ALL OTHER OBLIGATIONS OR LIABILITIES ON
THE SELLER'S PART, AND IT NEITHER ASSUMES NOR AUTHORIZES
ANY OTHER ~ERSON TO ASSUME FOR THE SELLER ANY OTHER LIABILITIES IN CONNECTION WITH THE SALE OF THE SAID ARTICLES.
This Warranty shall not apply to any of such products which shall have been
repaired or altered, except by the Seller, or which shall have been subjected to

or deliveries or perform any work except upon receipt of payment or upon terms
and conditions or security satisfactory to such department.

(bl If, in the judgment of the Seller, the finilncial condition of the Buyer at any
time does not justify continuation of production or shipment on the terms of

payment originally specified, the Seller may require full or partial payment in
advance and, in the event of the bankruptcy or insolvency of the Buyer or in the
event any proceeding is brought by or against the Buyer under the bankruptcy
or insolvency laws, the Seller shall be entitled to cancel any order then outstanding and shall receive reimbursement for its cancellation charges.

(cl Each sh ipment shall be considered a separate and independent transaction,
and payment therefor shall be made accordingly. If shipments are delayed by
the Buyer, payments shall become due on the date when the Seller is prepared
to make shipmenc If the work covered by the purchase
is delayed by the
Buyer, payments shall be made based on the purchase
and the percentage
of completion. Products held for the Buyer shall be at the risk and expense of
the Buyer.
TAXES:

WARRANTY: The Seller warrants that the products to be delivered under this
purchase order will be free from defects in material and workmanship under
normal use and service. SeHer's obligations under this Warranty are limited to
replacing or repairing or giving credit for, at its option, at its factory, any of said

credit department and the Seller may at any time decline to make any shipments

Unless otherWISe speCIfied and agreed upon, the material to be

of the nlaterral. Notwlthstilndlng the foregoing, If, upon receipt of such material
by Buyer, the same shall appear not to conform to the contract, the Buyer shall
i9"medlately notify the Sellel of such conditions and afford the Seller a reason-

hereby are f,rrn and not subject to audit, price reVISion, or price redetermination.

INSPECTION:

furnished under thiS order shall be subject to the Selier's standard inspect:vn at
the place of manufacture. If It has been agreed upon and specified in this order
that Buyer IS to Inspect or prOVide for inspection at place of manufacture such
Inspection shall be so conducted as to not interfere unreasonably with Seller's
operations and consequent approval or rejection shall be made before shipment

misuse, negligence, or accident.

The aforementioned provisions do not extend

the original warranty period of any product which has either been repaired or
replaced by Seller.
It is understood that if this order calls for the delivery of semiconductor devices
which are not finished and fully encapsulated, that no warranty, statutory,
expressed or implied, including the implied warranty of merchantability and fitness for a .particular purpose, shall apply. All such devices are sold as is where is.

Unless otherwise provided herein, the amount of any present or future

sales, revenue, excise or other taxes, fees, or other charges of any nature, imposed

by any public authority, (national, state, local or otherl applicable to the
products covered by this order, or the manufacturer or sale thereof, shall be
added to the purchase price and shall be paid by the Buyer, or in lieu thereof,
the Buyer shall provide the Seller with a tax exemption certificate acceptable to
the taxing authority.

GENERAL:
(a)

The validity, performance and construction of these terms and all sales

hereunder shall De governed by the laws of the State of California.
(bl
The Seller represents that with respect to the production of articles and!
or performance of the services covered by this order it will fully comply with all
requirements of the Fair Labor Standards Act of 1938, as amended, Williams·
Steiger Occupational Safety and Health Act of 1970, Executive Orders 11375
and 11246, Section 202 and 204.
(cl
In no event shall Seller be liable for consequential or special damages.
(dl
The Buyer may not unilaterally make changes in the drawings, designs or
specifications for the items to be furnished hereunder without Seller's prior

F.O_B. POINT: All sales are made F.O.B. point of shipment. Seller's title passes
to Buyer, and Seller's liability as to delivery ceases upon making delivery of
material purchased hereunder to carrier at shipping point, the carrier acting as

Buyer's agent. All claims for damages must be filed with the carrier. Shipments
will normally be made by Parcel Post, Railway Express, Air Express, or Air
Freight. Unless specific instructions from Buyer specify which of the foregoing
methods of shipment is to be used, the Seller will exercise his own discretion.

consent.

DELIVERY:
Shipping dates are approximate and are based upon prompt
receipt from Buyer of all necessary information. In no event will Seller be liable
for any re-procurement costs, nor for delay or non-delivery, due to causes beyond
its reasonable control including, but not I imited to, acts of God, acts of civil or
military authority, priorities, fires, strikes, lock·outs, slow-downs, shortages,

(el

Except to the extent provided in Paragraph 10, below, this order is not

subject to cancellation or termination for convenience.

(f!
Buyer acknowledges that all or part of the products purchased hereunder
may be manufactured andlor assembled at any of Seller's facilities, domestic or
foreign.
(g)
I n the event that the cost of the products are increased as a result of
increases in materials, labor costs, or duties, Seller may raise the price of the

factory or labor conditions, errors in manufacture, and inability due to causes

beyond the Seller's reasonable control to obtain necessary labor, materials, or
manufacturing facilities. In the event of any such delay, the date of delivery
shall, at the request of the Seller, be deferrea for a period equal to the time lost
by reason of the delay.

products to cover the cost increases.

(hi

if Buyer is in breach of its obligations under this order, Buyer shall

remain liable for all unpaid charges and sums due to Seller and will reimburse

Seller for all damages suffered or incurred by Seller as a result of Buyer's breach.
The remedies provided herein shall be in addition to all other legal means and
remedies available to Seller.

In the event Seller's production is curtailed for any of the above reasons so that
Seller cannot deliver the full amount released hereunder, Seller may allocate
production deliveries among its various customers then under contract for similar

goods. The allocation will be made in a commercially fair and reasonable manner.
When allocation has been made, Buyer will be notified of the estimated quota
made available.
6.

PATENTS:

10.

The Buyer shall hold the Seller harmless against any expense or loss

GOVERNMENT CONTRACT PROVISIONS: If Buyer's original purchase order
indicates by contract number, that it is placed under a government contract, only
the following provisions of the current Armed Services Procurement Regulation
are applicable in accordance with the terms thereof, with an appropriate sub·

resulting from infringement of patents, trademarks, or unfair competition arising

stitution of parties, as the case may be -

from compliance with Buyer's designs, specifications, or instructions. The sale
of products by the Seller does not convey any license, by implication, estoppel,

"Buyer", "Contractor" shall mean "Seller", and the term "Contract" shall
mean th is order:

or otherwise, under patent claims covering combinations of said products with
other devices or elements.

7-103.1, Definitions; 7-103.3, Extras; 7-103.4, Variation in
Quantity; 7-103.8, Assignment of Claims; 7·103.9, Additional
Bond Security; 7-103.13, Renegotiation; 7-103.15, Rhodesia
and Certain Communist Areas; 7-103.16, Contract Work Hours
and Safety Standards Act - Overtime Compensation; 7-103.17,
Walsh-Healey Public Contracts Act; 7-103.18, Equal Opportunity Clause; 7-103.19, Officials Not to Benefit; 7-103.20,
Covenant Against Contingent Fees; 7-103.21, Termination for
Convenience of the Government (only to the extent that
Buyer's contract is terminated for the convenience of the
government); 7-103.22, Authorization and Consent; 7-103.23,
Notice and Assistance Regarding Patent Infringement; 7-103.24,
Responsibility for Inspection; 7·103.25, Commercial Bills of
Lading Covering Shipments Under FOB Origin Contracts;
7·103.27, Listing of Employment Openings; 7-104.4, Notice
to the Government of Labor Disputes; 7-104.11, Excess
Profit; 7-104.15, Examination of Records by Comptroller
General; 7-104.20, Utilization of Labor Surplus Area.Concerns.

Except as otherwise provided in the preceding paragraph, the Seller shall defend
any suit or proceeding brought against the Buyer, so. far as based on a claim that
any product, or any part thereof, furnished under this contract constitutes an
infringement of any patent of the United States, if notified promptly in writing
and given authority, information, and assistance (at the Seller's expense) for

defense of same, and the Seller shall pay all damages and costs awarded therein
against the Buyer. In case said product, or any part thereof, is, in such suit, held
to constitute infringement of patent, and the use of said product is enjoined, the
Seller shall, at its own expense, either procure for the Buyer the right to continue
using said product or part, replace same with non-infringing product, modify it
so It becomes non-infringing, or remove said product and refund the purchase
price and the transportation and installation costs thereof. In no event shall
Seller'S total liability to the Buyer under or as a result of compliance with the
provisions of this paragraph exceed the aggregate sum pa'ld by the Buyer for the
allegedly infringing product.

The foregoing states the entire liability of the

Seller for patent infringement by the said products or any part thereof.

i.e., "Contracting Officer" shall mean

TH IS

1.13

Product Assurance Program

INTRODUCTION

QUALITY CONTROL

Quality is one of the most used, least understood, an.d
variously defined assets of the semiconductor industry. At
AMI we have always known just how important effective
quality assurance, quality control, and reliability monitoring
are in the ability to deliver a repeatably reliable product.
Particularly, through the manufacture of custom MOS/LSI,
experience has proved that one of the most important tasks
of quality assurance is the effective control and monitoring of
manufacturing processes. Such control and monitoring has a
twofold purpose: to assure a consistently good product, and
to assure that the product can be manufactured at a later date
with the same degree of reliability.

The Quality Control function in AMI's Product Assurance Program involves constant monitoring of all aspects of
materials and production, starting with the raw materials
purchased, through all processing steps, to device shipment.
There are three major areas of Quality Control:
• Incoming Materials Control
• Microlithography Control
• Process/Assembly Control

Incoming Materials Control

To effectively achieve these objectives, AMI has developed a Product Assurance Program consisting of three major
functions:

All purchased materials, including raw silicon, are checked
carefully to various test and sampling plans. The purpose of
incoming materials inspection is to ensure that all items required
for the production of AMI MOS circuits meet such standards
as are required for the production of high quality, high reliability devices.

• Quality Control
• Quality Assurance
• Reliability

Incoming inspection is performed to specifications agreed
to by suppliers of all materials. The Quality Control group
continuously analyzes supplier performance, performs comparative analysis of different suppliers, and qualifies the suppliers.

Each function has a different area of concern, but all share the
responsibility for a reliable product.

The AMI Product Assurance Program
The program is based on MIL-STD-883, MIL-M-38510,
and MIL-Q-9858A methods. Under this program, AMI manufactures highest quality MOS devices for all segments of
the commercial and industrial market and, under special adaptations of the basic program, also manufactures high reliability
devices to full military specifications for specific customers.

Tests are performed on all direct material, including
packages, wire, lids, eutectics, and lead frames. These tests
are performed using a basic sampling plan in accordance with
MIL-S-19500, generally to a Lot Tolerance Percent Defective
(LTPD) level of 10%. The AQL must be below 1% overall.
Two incoming material inspection sequences illustrate
the thoroughness of AMI Quality Control:
• Purchased packages are first inspected visually. Then, dimensional inspections are performed, followed by a full functional inspection, which subjects the packages to an entire
production run simulation. Finally, a full electrical evaluation is made, including checks of the insulation, resistance,
and lead-to-lead isolation. A package lot which passes these
tests to an acceptable LTPD level is accepted.

The three aspects of the AMI Product Assurance Program - Quality Control, Quality Assurance, and Reliabilityhave been developed as a result of many years of experience
in MOS device design and manufacture.
Quality Control establishes that every method meets, or
fails to meet, product parameters - QA checks results.
Quality Control establishes that every
method meest, or
fails to meet, processing or production standards - QC checks
methods.

• Raw silicon must also pass visual and dimensional checks.
In addition, a preferential etch quality inspection is performed. For this inspection, the underlayers of bulk silicon
are examined for potential anomalies such as dislocation,
slippage, or etch pits. Resistivity of the silicon is also tested.

Reliability establishes that QA and QC are effective Reliability checks device performance.
One indication that the AMI Product Assurance Program
has been effective, is that NASA has endorsed AMI products
for flight quality hardware since 1967. The Lunar Landers and
Mars Landers all have incorporated AMI circuits, and AMI
circuits have also been utilized in the Viking and Vinson
programs, as well as many other military airborne and reconnaissance hardware programs.

Microlithography Control
Microlithography involves the processes which result in
finished working plates, used for the fabrication of wafers.
These processes are pattern or artwork generation, photoreduction, and the actual printing of the working plates.

1.14

Product Assurance Program

Pattern generation now is the most common practice
at AMI. The circuit layout is digitized and stored on a tape,
which then is read into an automated pattern generator, which
prints a highly accurate lOx reticle directly.

specifications. This involves checks on operators, equipment
and environment. Operators are tested for familiarity with
equipment and adherence to procedure. Equipment is closely
checked both through calibration and maintenance audits.
Environmental control involves close monitoring of temperature, relative humidity, water resistivity and bacteria content,
as well as particle content in ambient air. All parameters are
accurately controlled to minimize the possiblity of contamination or adverse effects due to temperature or humidity excesses.

In cases where the more traditional method of artwork
generation is used whether Rubylith, Gerber Plots, AMI generated or customer generated - the artwork is thoroughly inspected. It is checked for level-to-level registration and dimensional tolerances. Also, a close visual inspection of the workmanship is made. AMI artwork is usually produced at 200x
magnification and must conform to stringent design rules,
which have been developed over a period of years, as part of
the process control requirements.

Experience has proven that such close control of the
operators, equipment, and environment is highly effective towards improved quality and increased yields.
In addition to the specification adherence activities of
the QC Fabrication Group, a QC Laboratory performs constant
process monitoring of virtually every step of all processes.
Specimens are taken from ·all production steps and critically
evaluated. Sampling frequency varies, depending on the process, but generally, oxidation, diffusion, masking, and evaporization are the most closely monitored steps.

Acceptable artwork is photographically reduced to a 20x
magnification, and then further to a lOx magnification. The
resulting lOx reticles are then used for producing Ix masters.
The masters undergo severe registration comparisons to a registration master and all dimensions are checked to insure that
reductions have been precise. During this step, image and geometry are scrutinized for missing or faded portions and other
possible photographic omissions.

Results are supplied both to manufacturing and engineering. When evidence of a problem occurs, QC provides recommendations for corrections and follows up the corrective
action taken.

For a typical P-channel silicon gate device, master sets
are checked at all six geometry levels in various combinations
against each other and against a proven master set. Allowable
deviations within the die are limited to 0.5 micron, deviations
within a plate are limited to I micron, and all plate deviations
are considered cumulatively.

Optical inspections are performed at several steps;
quality control limits are based on a 10% LTPD. The chart ,in
Figure 1 shows process steps and process control points.

Upon successful completion of a device master set, it is
released to manufacturing where the Ix plates are printed. A
sample inspection is performed by manufacturing on each 30plate lot and the entire lot is returned to Quality Control for
final acceptance. Quality Control performs audits on' each
manufacturing inspector daily, by sample inspection techniques.

QUALITY ASSURANCE
The Quality Assurance function in the Product Assurance Program involves checking the ability of manufactured
parts to meet specifications. In addition, the QA group also
is responsible for calibration of all equipment, and for the
maintenance of AMI internal product specifications, to assure
that they are always in conformance with customer specifications, or other AMI specifications.

The plates can be rejected first by manufacturing, when
the 30-plate lots are inspected, or by Quality Control when
the lots are submitted for final acceptance. If either group
rejects the plates, they are rescreened and then undergo the
same inspection sequence. In the rescreening process, the plates
undergo registration checks; visual checks for pin holes, protrusions, and faded or missing images, as well as all critical
dimension checks.

After devices undergo 100% testing in manufacturing,
they are sent to Quality Assurance for acceptance. Lots are
defined, and using the product specifications, sample sizes are
determined, along with the types of tests to be performed
and the test equipment to be used. Lots must pass QA testing
either with an LTPD or 10%, or less, if the specification requires tighter limits.

Process Control
Once device production has started in manufacturing,
AMI Quality Control becomes involved in one of the mqst
important aspects of the Product Assurance Program - the
analysis and monitoring of virtually all production processes,
equipment, and devices.

Three types of tests are performed on the samples:
visual/mechanical, parametric, and functional. All tests are
performed both at room temperature and at elevated temperature. In addition, a number of other special temperature
tests may be performed, if required by the specification.
0
Generally, high temperature tests are at 125 C.

Process controls are performed in the fabrication area, by
the Quality Control Fabrication Group, to assure adherence to

To perform the tests, QA uses AMI PAFT test systems,
ROM test systems, Macrodata testers, Fairchild Sentry systems,

1.15

Product Assurance Program

in engineering is initiated. As evidence of the problem is detected, the parts may also be traced all the way back to the wafer
run, to analyze the cause.

Figure 1. Flowchart of Product Assurance Program
Implementation

1-----

When a lot is acceptable, it is sent to packaging and then
to finished goods. When parts are sent from finished goods,
they are again checked by the QA group to a 10% LTPD, with
visual/mechanical tests. Also, all supporting documentation for
the parts is verified, including QA acceptance, special customer
specifications, certificates of compliance, etc. Only after this
last check are devices considered ready for plant clearance.

OC INSPECTION

If there are customer returns, they are first sample
tested by QA, to determine the cause of the return. (Many
times an invalid customer test will incorrectly cause returns.)
After QA evaluates all returns, they are sent to Reliability
for failure analysis.

OC INSPECTION

ASSEMBLY
Scribe/Break
lSI Optical

PACKAGING
OC INSPECTION

- - - - t - - Ole Attach
Bond 2nd

RELIABILITY

Optlcal5eal

The Reliability function in the Product Assurance Program involves process qualification, device qualification, package qualification, reliability prog(am qualificatioI)., and failure
analysis. To perform these functions AMI Reliability group is
organized into two major areas:

OC INSPECTION

J-----

MANUFACTURING

• Reliability Laboratory
• Failure Analysis

Reliability Laboratory
AMI Reliability Laboratory is responsible for the following functions:
J-----

OA INSPECTION

1-----

QA INSPECTION

•
•
•
•
•
•
•
•
•
•

New Process Qualification
Process Change Qualification
Process Monitoring
New Device Qualification
Device Change Qualification
New Package Qualification
Device MonitOring
Package Change Qualification
Package Monitoring
High Reliability Programs

There are various closely interrelated and interactive phases
involved in the development of a new process, device, package, or reliability program. A process change may affect
device performance, a device change may affect process repeatability, and a package change may affect both device performance and process repeatability. To be effective, the
Reliability Laboratory must monitor and analyze all aspects
of new or changed processes, devices, and packages. It must
be determined what the final effect is on product reliability,
and then evaluate the merits of the innovation or change.

Western Digital Spartan systems, Impact testers, and various
bench test units. In special instances a part may also be tested
in a real life environment, in the equipment which is to finally
utilize it.
If a lot is rejected during QA testing, it is returned to
the production source for an electrical rescreening. It is then
returned to QA for. acceptance, but is identified as a resubmitted lot. If it fails again, it is discarded and corrective action

1.16

Product Assurance Program

Process Qualification

Process Monitoring

For example, AMI Research and Development group
recommends a new process or process alteration when it feels
that the change can result in product improvement. The
Reliability Laboratory then performs appropriate environmental and electrical evaluations of new process. Typically, a
special test vehicle, or "reI chip", generated by R&D during
process development, is used to qualify the recommended new
process or process change.

In addition to process qualification, the Reliability group
also conducts ongoing process monitoring programs. Once
every 90 days each major production process is evaluated using
rei chips as test vehicles. The resulting test data is analyzed for
parameter limits and process stability. In this manner AMI can
help assure repeatability and high product quality.

Package Qualification
The reI chip is composed of circuit elements similar to
those that may be required under worst-case circuit design
conditions. The reI chip elements are standard for any given
process, and thus allow precise comparisons between diffusion
runs. The following is an example of what is included on a
typical reI chip:

New packages are also qualified before they are adopted.
To analyze packages, a qualification matrix is designed, according to which the new package and an established package (used
for control) are tested concurrently. The test matrix consists
of a full spectrum of electrical and environmental stress tests,
in accordance with MIL-STD-883.

• A discrete inverter and an MOS capacitor
• A large P-N junction covered by an MOS capacitor
• A large P-N junction area (identical to the junction
area above, but without the MOS capacitor)
• A large area MOS capacitor over substrate
• Several long contact strings with different contact
geometries.
• Several long conductor geometries, which cross a series
of eight deeply etched areas.

Failure Analysis
Another important function of the Reliability group
is failure analysis. Scanning electron microscopes, high power
optical microscopes, diagnostic probe stations, and other
equipment is used in failure analysis of devices submitted
from various sources. It is the function of the Reliability group
to determine the cause of failure and recommend corrective
action.
The Reliability group provides a failure anlaysis service
for the previously mentioned in-house programs and for the
evaluation of customer returns. All AMI customers are provided a failure analysis service for any part that fails within
one year from date of purchase and the results of the analysis
are returned in the form of a written report.

Each circuit element of a reI chip allows a specific test
to be performed. As an example, the discrete inverter and
MOS load device accommodate power life tests. As a consequence, any type of parameter drift can be observed. The MOS
capacitor, covering the large P-N junction, can serve to indicate the presence of contamination in the oxide, under the
oxide, or in the bulk silicon. If unusual drift is evidenced, the
location of contamination can be determined through analysis
of the additional MOS capacitor and the large P-N junction
area. The metal conductor interconnecting contacts is useful
for life testing under relatively high current conditions. It
facilitates the detection of metal separation when moisture or
other contaminants are present.

SUMMARY
The Product Assurance Program at AMI is oriented towards process control and monitoring, and the evaluation of
devices. The Program consists of three major functions:
Quality Control, Quality Assurance, and Reliability. Constant
monitoring of all phases of production, with information feedback at all levels, allows fast and efficient detection of problems, evaluation and analysis, correction, and verification of
the correction. The overall result is a line or' products which
are highly repeatable and reliable, with a very low reject level.

The conductors crossing deeply etched areas allow the
checking of process control. Rather than depending upon
optical inspection of metal quality, burned out areas caused
by high currents are readily identified and provide a quantitative measure of metal quality.
If the Reliability Laboratory determines that a recommended new process or process change is viable for manufacturing purposes, further analysis is necessary to determine
that production devices can be manufactured in high volume,
in a repeatable and reliable manner.

1.17

MOS Processes

PROCESS DESCRIPTIONS

Each of the major MaS processes is described on the
following pages. First, the established production proven processes are described, followed by those advanced processes,
which are starting to go into volume production now. In each
case, the basic processes is described first, followed by an explanation of its advantages, applications, etc.
P-CHANNEL METAL GATE PROCESS

Of all the basic MaS processes, P-channel Metal Gate
is the oldest and the most completely developed. It has served
as the foundation for the MaS/LSI industry and still finds
use today in some devices. Several versions of this process have

evolved since its earliest days. A thin slice (8 to 10 mils) of
lightly doped N-type silicon wafer serves as the substrate or
body of the MaS transistor. Two closely spaced, heavily doped
P-type regions, the source and drain, are formed within the
substrate by selective diffusion of an impurity that provides
holes as majority electrical carriers. A thin deposited layer of
aluminum metal, the gate, covers the area between the source
and drain regions, but is electrically insulated from the substrate
by a thin layer (1000-1500 J\) of silicon dioxide. TheP-channel
transistor is turned on by a negative gate voltage and conducts
current between the source and the drain by means of holes as
the majority carriers.
The basic P-channel metal gate process can be subdivided in two general categories: high-threshold and low-

FIGURE 10-1. SUMMARY OF MOS PROCESS CHARACTERISTICS

P-CHANNEL METAL GATE
Variations:
1. High Threshold (Hi VT)
2. Low Threshold (Lo VT)

{

Materials: N-Silicon substrate - (111) for high VT • (JOO) for low VT .
Aluminum gate, source, and drain contacts.
Performance: Poor speed-power product: VT/V TF tradeoff
Complexity: Typically 15 or less process steps.

ION IMPLANTED P-CHAN. METAL GATE
Variations:
1. With enhancement and depletion mode
devices on same chip

1
SILICON GATE
(Usually with Ion Implantation)
Variations:
1. With buried interconnect layer
2. With enhancement and depletion mode devices
on same chip

{

Materials: Same as above, always (111) silicon.
Performance: Lower VT by altering QB term; high
VTF of (111) silicon; enhancement and
depletion mode transistors possible.
Complexity: Over 15, less than 20 process steps.

P-CHANNEL

Materials: (11 J) substrate, doped polycrystalline Silicon.gate
Performance: Lower VT through ~s term, but high VTF of
(111) silicon
{ Complexity: 15-20 process steps, but over 25 with combined
enhancement and depletion mode devices

N-CHANNEL

Materials: U 00) P-silicon substrate, doping polysilicon gate, ion implanted field
Performance: Fast circuits, through high mobility (IJ) of electrons
{ Complexity: Same as P-channel Si-gate

DOUBLE PO LY

Materials: (100) P-silicon substrate, doped polysilicon gate
Performance: All N-channel Si-Gate advantages, plus compactness
{ Complexity: Over 30 process steps

CMOS
Variations:

1. Silicon Gate
2. Metal Gate

(Both commonly use ion
implantation)

{

Materials: N-silicon substrate, either polysilicon or aluminum gate
Performance: Low power, high speed
Complexity: Over 25 process steps

1
VMOS

Static RAM, ROM and General Logic

{

Materials: (100)" epitaxial layer on an N+ doped substrate,
Poly silicon gates and resistors
Performance: N-channel silicon gate, extremely compact through
use of vertical direction
Complexity: Complex, over 30 process steps

1.18

MOS Processes

deposited, but before the source, gate, and drain metallization
deposition. The wafer is exposed to an ion beam which penetrates through the thin gate oxide layer and implants ions
into the silicon substrate. Other areas of the substrate are
protected both by the thicker oxide layer and sometimes also
by other masking means. Ion implantation can be used with
any process and, therefore could, except for the custom of
the industry, be considered a special technique, rather than
a process in itself.

threshold. Various manufacturers use different techniques
(particularly so with the low threshold process) to achieve
similar results, but the difference between them always rests
in the threshold voltage VT required to turn a transistor on.
The high threshold VT is typically -3 to -5 volts and the low
threshold VT is typically -1.5 to -2.5 volts.
The original technique used to achieve the difference in
threshold voltages was by the use of substrates with different
crystalline structures. The high VT process used OlD silicon,
whereas the low VT process used (00) silicon. The difference
in the silicon structure causes the surface charge between the
substrate and the silicon dioxide to change in such a manner
that it lowers the threshold voltages.

The implantation of P-type ions into the substrate, in
effect, reduces the effective concentration of N-type ions in
the channel area and thus lowers the VT required to turn the
transistor on. At the same time, it does not alter the N-type ion
concentration elsewhere in the substrate and therefore, does
not reduce the parasitic field oxide threshold voltage VTF (a

One of the main advantages of lowering VT is the ability
to interface the device with TTL circuitry. However, the use
of (100) silicon carries with ita distinct disad van tage also.
Just as the surface layer of the (100) silicon can be inverted
by a lower VT , so it also can be inverted at other random
locations - through the thick oxide layers - by large voltages
that may appear in the metal interconnections between circuit
components. This is undesirable because it creates parasitic
transistors, which interfere with circuit operation. The maximum voltage that can be carried in the interconnections is
called the parasitic field oxide threshold voltage VTF , and generally limits the overall voltage at which a circuit can operate.
This, then, is the main factor that limits the use of the low VT
process. A drop in VTF between a high VT and low VT process
may, for example, be from -28V to -17V.

FIGURE 10-2. DIAGRAM OF ION IMPLANTATION STEP

Boroll IP-type) iOlls /rum III/piallter Accelerator

The low VT process, because of its lower operating voltages, usually produces circuits with a lower operating speed
than the high VT process, but is easier to interface with other
circuits, consumes less power, and therefore is more suitable
for clocked circuits. Both P-channel metal gate processes
yield devices slower in speed than those made by other MaS
processes, and have a relatively poor speed/power product.
Both processes require two power supplies in most circuit
designs, but the high VT process, because it operates at a high
threshold voltage, has excellent noise immunity.

lOllS Implanted Here

Note: Implantation step is performed after gate oxidation.

problem with the low VT P-channel Metal Gate process,
described above). The (111) silicon usually is used in ionimplanted transistors.
In fact, if the channel area is exposed to the ion beam
long enough, the substrate in the area can be turned into Ptype silicon (while the body of the substrate still remains Ntype) and the transistor becomes a depletion mode device. In
any circuit some transistors can be made enhancement type,
while others are depletion type, and the combination is a
very useful circuit design tool.

ION IMPLANTED P-CHANNEL METAL GATE PROCESS
The P-channel Ion Implanted process uses essentially the
same geometrical structure and the same materials as the high
VT P-channel process, but includes the ion implantation step.
The purpose of ion implantation is to introduce P-type impurity
ions into the substrate in the limited area under the gate
electrode. By changing the characteristics of the substrate in
the gate area, it is possible to lower the threshold voltage VT
of the transistor, without influencing any other of its properties.

The Ion-implanted P-channel Metal Gate process is
very much in use today. Among all the processes, it represents
a good optimization between cost and performance and thus
is the logical choice for many common circuits, such as memory
devices, data handling (communication) circuits, and others.

Figure 10-2 shows the ion implantation step in a diagrammatic manner. It is performed after the gate oxide is

1.19

MOS Processes

Because of its low VT , it offers the designer a choice
of using low power supply voltages to conserve power or
increase supply voltages to get more driving power and thus
increase speed. At low power levels it is more feasible to implement clock generating and gating circuits on the chip. In
most circuit designs only a single power supply voltage is
required.

and often allows the reduction of the total chip size. Because
the polysilicon gate electrode is deposited in a separate step,
after the thick oxide layer is in place, the simultaneous deposition of additional polysilicon interconnect lines is only a matter of masking. These interconnect lines are buried by later
steps, as shown in Figure 10-3.
FIGURE 10-3. CROSSECTION OF A SILICON GATE
MOS TRANSISTOR

N-CHANNEL PROCESS
Intercollnect deposit (to be
buried by next oxide diffusion)

Historically, N-channel process and its advantages were
known well at the time when the first P-channel devices were
successfully manufactured, however it was much more difficult
to produce N-channel. One of the main reasons was that the
polarity of intrinsic charges in the materials combined in such
a way that a transistor was on at OV and had a VT of only a
few tenths of a volt (positive). Thus, the transistor operated as
a marginal depletion mode device, without a well-defined
on/off biasing range. Attempts to raise VT by varying gate
oxide thickness, increasing the substrate doping, and back
biasing the substrate, created other objectionable results and it
was not until research into materials, along with ion implantation, silicon gates, and other improvements came about that Nchannel became practical for high density circuits.
The N-channel process gained its strength only after
the P-channel process, ion implantation, and silicon gate all
were already well developed. N-channel went into volume
productions with advent of the 4K dynamic RAM and the
microprocessor, both of which required speed and high density. Because P-channel processes were nearing their limits in
both of these respects, N-channel became the logical answer.
The N-channel process is structurally different from any
of the processes described so far, in that the source, drain,
and channel all are N-type silicon, whereas the body of the
substrate is P-type. Conduction in the N-channel is by means
of electrons, rather than holes.
The main advantage of the N-channel process is that
the mobility of electrons is about three times greater than
that of holes and, therefore, N-channel transistors are faster
than P-channel. In addition, the increased mobility allows
more current flow in a channel of any given size, and therefore N-channel transistors can be made smaller. The positive
gate voltage allows an N-channel transistor to be completely
compatible with TTL.
Although metal gate N-channel processes have been used,
the predominant N-channel process is a silicon gate process.
Among the advantages of silicon gate is the possibility of a
buried layer of interconnect lines, in addition to the normal
aluminum interconnections deposited on the surface of the
chip. This gives the ci!cuit designer more latitude in layout

=LlCONGATE~

(a) Transistor Ready for Source and Drain Diffusions

ALUMINUM OVER THE BURIEO
SILICON INTERCONNECT

( b) Finished Transistor

One minor limitation associated with the buried interconnect lines is their location. Because the source and drain
diffusions are done after the polysilicon is deposited [see (a)
of Figure 10-3] the interconnect lines cannot be located
over these diffusion regions.
A second advantage of a silicon gate is associated with
the reduction of overlap between the gate and both the
source and drain. Thi~ reduces the parasitic capacitance at each
location and improves speed, as well as power consumption
characteristics. Whereas in the metal gate process, the P
region source and drain diffusion must be done prior to deposition of the gate electrode, in silicon gate process, the
electrode is in place during diffusion, see (a) of Figure 10-3.
Therefore, no planned overlap for manufacturing tolerance
purposes need exist and the gate is said to be selfaligned. The
only overlap that occurs is due to the normal lateral extension
of the source and drain regions during the diffusion process.
The silicon-gate process produces devices that are mQre
compact than metal gate, and are slightly faster because of
the reduced gate overlap capacitance. Because the basic silicon
gate process is relatively simple, it is also economical. It is a
versatile process that is used in memory devices and most any
other circuit.

1.20

MOS Processes

Because N-channel is relatively new, however, its production techniques and variations in applications still are undergoing development. However, the combination of high speed,
TTL compatibility, low power requirements, and compactness
have already made N-channel the most widely used process.
The cost of N-channel has been coming down also.
In addition to its use in large memory chips and microprocessors, N-channel has become a good general purpose
process for circuits in which compactness and high speed are
important. The addition of a second layer of polysilicon to
this process has allowed the formation of overlapping electrodes
making possible charge coupled devices for very compact dynamic memory cells. for filters, and for analog/digital conversion.

CMOS
The basic CMOS circuit is an inverter, which consists
of two adjacent transistors - one an N-channel, the other a
P-channel, as shown in Figure 10-4. The two are fabricated
on the same substrate, which can be either Nor P type.

The CMOS inverter in Figure 10-4 is fabricated on an
N-type silicon substrate in which a P "tub" is diffused to
form the body for the N-channel transistor. All other steps,
including the use of silicon gates and ion implantation, are
much the same as for other processes.
The main advantage of CMOS is its extremely low
power consumption. When the common input to both gate
electrodes is at a logic 1 (a positive voltage) the N-channel
transistor is biased on, the P-channel is off, and the output is
near ground potential. Conversely, when the input is at a logic
o level, its negative voltage biases only the P-channel transistor on and the output is near the drain voltage +Voo' In
either case, only one of the two transistors is on at a time and
thus, there is virtually no current flow and no power consumption. Only during the transition from one logic level to the
other are both transistors on and current flow increases
momentarily.
Silicon Gate CMOS is also fast, approaching speeds of
bipolar TTL circuits. On the other hand, the use of two
transistors in every device makes CMOS slightly more complex,

FIGURE 10-4. CROSSECTION AND SCHEMATIC DIAGRAM OF A CMOS INVERTER

INPUT

--{::>c>-

OUTPUT

P-CHANNEL TRANSISTOR

N·CHANNEL TRANSISTOR

N-TYPE SUBSTRATE

1.21

MOS Processes

costly, and requires more chip size. For these reasons, the
original popularity of CMOS was in SSI logic elements and
MSI circuits - logic gates, inverters, small shift registers,
counters, etc. These CMOS devices constitute a logic family
in the same way at TTL, ECL, and other bipolar circuits do
and in the areas of very low power consumption, high noise
immunity, and simplicity of operation, are still widely accepted
by discrete logic circuit designers.

In producing a VMOS device, the source diffusion,
epitaxial growth of the channel layer, drain diffusions and
insulating oxide all are completed first and only then the
V-groove is etched. The precise V shape of the groove results
because of the interaction of the etchant with the anisotropic
crystal structure.

The VMOS process has several significant advantages:
Low power CMOS circuits made the watch circuit possible and also have been used in space exploration, battery
operated consumer products, and automotive control devices.
As experience was g_ained with CMOS, tighter design rules and
reduced device sizes have been implemented and now LSI
circuits, such as lK RAM memories and microprocessors, are
being manufactured in volume.

• Because it uses the sides of the V -groove for device
construction, the VMOS transistor requires a much
smaller chip surface area than any planar transistor. For
this reason, very high density circuits can be built
with VMOS.
• Devices with very short channels and large WjQ ratios can
be built, making possible the design of very high speed
circuits, that can carry large currents. In any planar
process the channel length can be no smaller than the
physical limits of photolithographic masks, whereas in
VMOS the effective channel length is controlled only
by diffusion and epitaxial thickness, and can be 2 Mm
orless. On the other hand, channel width is the perimeter
distance around all four sides of the V-groove (at the
channel elevation) and this clearly is an advantage in
getting a high WjQ ratio without using up a large surface
area. (The perimeter distance is 2-3 times that of a corresponding chip surface area planar device.)

CMOS circuits can be operated on a single power supply
voltage, which can be varied from +3 to about + 18 volts, with
a higher voltage giving more speed and higher noise immunity.

VMOS
AMI's patented VMOS process is a significant departure
from the other processes described so far. The VMOS transistor is constructed along the sides of a V -shaped groove, that
has been etched into the silicon, as shown in the simplified
diagram of Figure 10-5(a). (A distinction arises between the
VMOS transistor and the planar transistor, whose source, gate,
and drain are laid out in the usual manner, along the surface
plane of the substrate.)

• The 1T type epitaxial layer isolates the heavily doped N+
drain from the P channel and thus reduces substrateto-drain capacitance and increases drain breakdown voltage. Other parasitic capacitances are also typically
smaller than those of planar devices and so the overall
power consumption at a given operating speed is smaller
than that of other processes (with the exception of
CMOS).

The source is a heavily N doped region, diffused into
the substrate (heavy doping is denoted by + after the N).
An epitaxially grown layer over the source constitutes the
channel. The lower part of this layer is more heavily P-doped
and its depth determines the effective channel length. The
upper part, designated 1T, is very lightly P-doped and is used
as ail· isolating layer, to improve device performance characteristics (as described below). The drain is a heavily N-doped
diffusion on the surface of the structure.

On the strength of its density and speed advantages,
VMOS appears to be most promising for next generation
memories - the 16K and larger RAMs. However, various other
device configurations, besides the floating source transistor
shown in Figure 10-5, are possible and thus VMOS can become a good all-purpose process - usable on ROMs, EPROMs,
microprocessors, and random logic. For example, in a ROM
the N+ source diffusion is eliminated and ~nstead, the entire
substrate is N type. In this manner all the cells have a common
grounded source and a very simple straightforward structure
results.

The gate oxide and gate electrode are deposited all along
the bias surfaces of the V -groove, as shown in the crossection
(b), and a field oxide layer extends over the drain. On the
surface of a die, the VMOS transistor appears as in (c).

1.22

MOS Processes

FIGURE 10-5. THE VMOS TRANSISTOR

a. The V-groove of a Floating Source
VMOS Transistor
POLYSILICON
ELECTROOE

c. Photograph of Two Parallel VMOS Transistors with
Surface V-Groove Dimensions of 6/lm x 23/lm

b. Crossection of a Completed Floating Source
VMOS Transistor

FIGURE 10-6. COMPARATIVE DATA ON MAJOR MOS PROCESSES

P METAL GATE HI VT

ftf-

P METAL GATE LO VT

1000-

-I- CMOS

f- P METAL GATE HI VT
1000-

1000-

PSI-GATE
P ION IMPLANT

I- PSI-GATE

t= ~ ~~i:[~ATE LO VT

t- NSI-GATE
t- N SI-GATE LO VT
100>-

...... P METAL GATE LO VT

P METAL GATE HI VT

PSI-GATE

~PJONIMPlANT

I- N SI-GATE LO VT

I-

N SI-GATE LO VT

I- NSI-GATE

NSI-GATE DEPLD

VMOS

P-CHANNELSI-GATE

- I - P-CHANNEL METAL GATE ION IMPLANT

f10-

-~ N-CHANNEL SI-GATE LO VT

-~ N-CHANNEL SI-GATE

f- P ION IMPLANT
100-

- I - N-CHANNEL SI-GATE (DEPLETION LOADI

N SI-GATE DEP LD, VMOS

100-

-~ P-CHANNEL METAL GATE LO VT

10-

-~ P-CHANNEL METAL GATE HI VT

I- CMOS

CMOS

I-

I-- CMOS
.-- N SI-GATE DEP LO

0>RELATIVE SPEEDPOWER PRODUCT

INS-MWI

10-

RElATIVE POWER
(AT FIXED SPEEDI

RELATIVE COST

PER lOGIC FUNCTlON

I-

VMOS

RELATIVE

PROPAGATION

1.23

1.24

2
Memories
(RAMs, ROMs
and EPROMs)

MOS STATIC RANDOM ACCESS MEMORIES
ORGANIZATION

PROCESS

MAX. ACCESS
TIME (ns)

MAX. ACTIVE
POWER (mW)

MAX. STANDBY
POWER (mW)

POWER
SUPPLIES

PACKAGE

S68810

128 x 8

NMOS

250

420

N/A

+5V

24 PIN

S68A10

128 x 8

NMOS

360

420

N/A

+5V

24 PIN

S4015-2

1024 x 1

VMOS

660

N/A

+5V

16 PIN

S4025-2

1024 x 1

VMOS

660

N/A

+5V

16 PIN

PART NO.

S2114H3

1024 x 4

VMOS

790

N/A

+5V

18 PIN

S2114A-1

1024 x 4

VMOS

150

265

N/A

+5V

18 PIN

S2114L-1

1024 x 4

VMOS

150

370

N/A

+5V

18 PIN

S2114-1

1024 x 4

VMOS

150

525

N/A

+5V

18 PIN

S2114A-2

1024 x 4

VMOS

200

265

N/A

+5V

18 PIN

S2114L-2

1024 x 4

VMOS

200

370

N/A

+5V

18 PIN

S2114-2

1024 x 4

VMOS

200

525

N/A

+5V

18 PIN

S2114A-3

1024 x 4

VMOS

300

265

N/A

+5V

18 PIN

S2114L-3

1024 x 4

VMOS

300

370

N/A

+5V

18 PIN

S2114-3

1024 x 4

VMOS

300

525

N/A

+5V

18 PIN

S4017-3

4096 x 1

VMOS

660

N/A

+5V

18 PIN

S4017

4096 x 1

VMOS

660

N/A

+5V

18 PIN

S2147-3 3
S2147 3

4096 X 1

VMOS

945

160

+5V

18 PIN

4096 X 1

VMOS

840

105

+5V

18 PIN

S4028 3

2048 X 8

VMOS

200

525

N/A

+5V

24 PIN

CMOS STATIC RANDOM ACCESS MEMORIES
PART NO.

ORGANIZATION

MAX. ACCESS
TIME (ns)

MAX. ACTIVE
POWER (mW)

MAX. STANDBY
POWER (mW)

POWER
SUPPLIES

PACKAGE
16 PIN

S2222 1

512 X 1

350

.05

+10V

S2222N

512 x 1

700

.25

+10V

16 PIN

S5101 L-1

256 x 4

450

115

.055

+5V

22 PIN

S5101 L

256 x 4

650

115

.055

+5V

22 PIN

S5101L-3

256 x 4

650

115

.735

+5V

22 PIN

S5101L-8

256 x 4

800

115

2.7

+5V

22 PIN

S5101-8

256 x 4

800

115

2.7

+5V

22 PIN

S6508-1

1024 x 1

300

.055

+5V

16 PIN

S6508

1024 x 1

460

.55

+5V

16 PIN

S6508A-1

1024 x 1

+4V to +11V

16 PIN

1024 x 1

12.5/502
12.5/50 2

1.1

S6508A

275/115 2
4601185 2

5.5

+4V to +11V

16 PIN

S6518-1

1024 x 1

300

.055

+5V

18 PIN

S6518

1024 x 1

460

.55

S6518A-1

1024 x 1

275/115 2

1.1

+5V
+4V to +11V

18 PIN

S6518A

1024 x 1

460/185 2

12.5/50 2
12.5/50 2

5.5

+4Vto+11V

18 PIN

2.2

18 PIN

MOS DYNAMIC RANDOM ACCESS MEMORIES
MAX. ACTIVE
PDWER (mW)

MAX. STANDBY

TIME (ns)

POWER (mW)

PDWER
SUPPLIES

PACKAGE

PMOS

205

425

2.0

+16/ +19

18 PIN

1024 x 1

PMOS

400

450

- 12/ +5

16 PIN

102-1 x 1

PMOS

800

450

-12/ +5

16 PIN

PART NO.

ORGANIZATION

PRDCESS

Sl103N

1024 x 1

S4006 1
S4008-9 1

MAX. ACCESS

UV ERASABLE ELECTRICALLY PROGRAMMABLE READ ONLY MEMORIES
PART NO.

ORGANIZATION

PRDCESS

MAX. ACCESS
TIME (ns)

MAX. ACTIVE
POWER (mW)

MAX. STANDBY
PDWER (mW)

POWER
SUPPLIES

PACKAGE

S6834

512 x 8

PMOS

575

750

N/A

+5/ -12

24 PIN

S6834-1

512 x 8

PMOS

750

N/A

+5/ -12

24 PIN

S5204A

512 x 8

PMOS

750

N/A

+5/ -12

24 PIN

S4716 3

2048 X 8

VMOS

250

525

132

24 PIN

S4532 3

4096 X 8

VMOS

250

525

132

24 PIN

MAX. ACTIVE
POWER (mW)

POWER
SUPPLIES

PACKAGE

MOS READ ONLY MEMORIES
PART NO.

ORGANIZATION

PROCESS

MAX. ACCESS
TIME (ns)

2560 Bit Static ROM

256x 10or512x5

PMOS

600

+5/ -12

24/28 PIN

S8564 1

64 x 7 x 9 Charac. Gen.

64 Words

PMOS

450

1100

+5/ -12

28 PIN

S3514 1

4096 Bit Static ROM

512 x 8 or 1024 x 4

PMOS

1000

500

+5/ -12

24 PIN

S5232 1

4096 Bit Static ROM

512x8orl024x4

PMOS

1000

500

+5/ -12

24 PIN

S8771 1

5120 Bit Static ROM

512 x 10 or 1024 x 5

PMOS

450

1000

+5/ -12

28 PIN

S6830 1

8192 Bit Static ROM

1024 x 8

NMOS

575

680

24 PIN

S8865 1

8192 Bit Dynamic ROM

1024 x 8

PMOS

1700

635

+5/ -12

24 PIN

S4216B

16,384 Bit Static ROM

2048 x 8

VMOS

250

500

24 PIN

S6831 1

16,384 Bit Static ROM

2048 x 8

NMOS

450

420

24 PIN

S6831A

16,384 Bit Static ROM

2048 x 8

NMOS

450

420

24 PIN

S6831 B

16,384 Bit Static ROM

2048 x 8

NMOS

450

420

24 PIN

S6831 C1

16,384 Bit Static ROM

2048 x 8

NMOS

450

420

24 PIN

S8996 1

16,384 Bit Dynamic ROM

4096 x 4

PMOS

1800

370

+5/ -12

24 PIN

S8996 1

16,384 Bit Dynamic ROM

2048 x 8

PMOS

1800

370

+5/ -12

24 PIN

S68332

32,768 Bit Static ROM

4096 x 8

NMOS

450

630

24 PIN

S4264

65,536 Bit Static ROM

8192 x 8

VMOS

350

800

24 PIN

S8773

DESCRIPTION

NOT RECOMMENDED FOR NEW DESIGNS
FIRST NUMBER IS AT +5V, SECOND IS AT +10V
TO BE ANNOUNCED

2.3

52114
4096 BIT (1024x4)
STATIC VMOS RAM
Features

General Description

High Speed Operation:
Access Time: 150ns Maximum (-1)

High Density 18 Pin Package

Single +5 Volt Power Supply

The AMI S2114 is a 4096 bit fully static RAM organized as 1024 words by 4 bits. The device is fully TTL
compatible on all inputs and outputs and has single
+5V supply. The common data input/output pins facilitate interface with systems utilizing a bidirectional
data bus. The stored data is read out non -destructively
and is the same polarity as the original input data.

Completely Static Operation:
No Clocks Required

Completely TTL Compatible

Common Data I/O:
Three-State Outputs

Fan-Out of 5 TTL:

10L

The S2114 is fully static requiring no clocks or refreshing for operation. This simplifies device operation as no
address setup times are required. The chip select function facilitates memory system expansion by allowing
the input/output pins to be OR-tied to other devices.
The S2114 is fabricated using AMI's proprietary
VMOS technology. This process permits the manufacture of high performance memory devices suitable for
high volume production.

= 8mA@ O.4V

Block Diagram

Pin Configuration

Logic Symbol

ADDRESS
DECODER
DRIVER

x 64

ARRAY

1/01

A3
1/02

A4
A5
ADDRESS

COLUMN

DECODER
DRIVER

1/0,
1/0 2
1/0 3
1/0 4

1/03

A6
A)

1/04

CS
877310

877309

Truth Table
871308

CS
H

Pin Names
Ao -All
CS
1/01 - 1/04

Address Inputs
WE
Chip Select
VCC
Data Input/Output

L
L
L

Write Enable
+5V Power

2.4

Inputs
WE
DIN
X
L
L
H

X
L

H
X

Outputs
DOUT
Hi-Z
Hi-Z
Hi-Z
DOUT

Mode
Not Selected
Write "0"
Write "1"
Read

S2114

Absolute Maximum Ratings*

Ambient Temperature Under Bias .............................................. - 10° C to 80° C
Storage Temperature ....................................................... - 65° C to 150° C
Voltage on Any Pin With Respect to Ground ........................................ - 0.5V to 7V
Power Dissipation ................................................................... 1 \V
*eOMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or at any other condition above those indicated in the opera·
'tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
effect device reliability.

D.C. Operating Conditions (VCC

5V ±5%; TA

O°C to 70°C)

S2114A·1
S2114A·2
S2114A·3
Symbol

Parameter

Min.

I/O Leakage Current

Icc

Power Supply Current

VII,

Input LOW Voltage

-0.5
2.0

VIH

Input HIGH Voltage

VOL

Output LOW Voltage

VOH

Output HIGH Voltage

los

Output Short Circuit Current

2.4

Max.

Units

10
10

J.1A

rnA

100

rnA

0.8

Vee
0.4

10L = 8mA

Vee

100

rnA

10H = -lmA
Duration not to
exceed 30 sec.

Max.

Input Leakage Current

ILl
IILOI

S2114·1
S2114·2
S2114·3

S2114L·1
S2114L·2
S2114L·3
Min.

Max.

0.8

-0.5

0.8

Vce
0.4

2.0

Vee
0.4

Vee

2.4

-0.5
2.0
2.4

Vce

100

Min.

100

Conditions
VIN = OV to 5.25V
CS=2.4V;
VIla = O.4V to Vee
VIN = 5.25V;
TA = 25°C
VIN = 5.25V;
TA = O°C

Capacitance (TA = 25°C; f = 1.0MHz)
Max.

Units

Conditions

CIjO

Input/Output Capacitance

CIN

Input Capacitance

VIla = OV
VIN = OV

Symbol

Parameter

Min.

Typ.

A.C. Characteristics (V CC = 5V ±5%; TA = O°C to 70°C)
Read Cycle
S2114A·1
S2114L·l
S2114.1
Symbol Parameter

Min.

Max.

S2114A·2
S2114L·2
S2114·2
Min.

Max.

S2114A·3
S2114L·3
S2114·3
Min.

Max.

Units

tRe

Read Cycle Time

Access Time

150

200

300

teo

Chip Selection to Output Valid

100

tcx

Chip Selection to Output Active

150

tOTD Output 3 ·State from
Deselection
tOHA Output Hold from
Address Change

200

300

60
30

2.5

Conditions

See
Test
Circuit
and
Waveforms

S2114

A.C. Characteristics (Continued)
Write Cycle
S2114A·1
S2114L·1
S2114·1
Symbol Parameter

Min.

Max.

S2114A·2
S2114L·2
S2114·2
Min.

Max.

S2114A·3
S2114L·3
S2114L·3
Min.

Max. Units

twc

Write Cycle Time

150

200

300

Write Time

120

150

tWR

Wri te Release Time

tOTW Output 3-State from Write

Conditions

See
Test
Circuit
and
Waveforms

tDW

Data to Write Time Overlap

120

150

tDH

Data Hold from Write Time

Write Cycle (note 2)

Read Cycle (note 1)
Propagation Delay From Address Inputs

lwe

877312

Propagation Delay From Chip Select

DOUT

leo
877313

sr=

DOUT

DIN
817314

NOTES:
1. A read occurs during the overlap of a LOW CS and a HIGH WE.

2.
3.
4.
5.

A write occurs during the overlap of a LOW CS and a LOW WE.
tWR is referenced to the positive transition of WE.
WE must be HIGH during all address transitions.
If the CS LOW transition occurs simultaneously with the WE LOW transition, then the output buffers remain in the high
impedance state.

A.C. Test Conditions

A.C. Test Load
+5V

510n

Input Pulse Levels ........

O.8V to 2.4V
S2114

Input Rise & Fall Times

.......... lOns

Input and Output Timing Level ... "

390n

1.5V

2.6

ADVANCED PRODUCT DESCRIPTION

S2114H

4096 BIT (1024x4)
HIGH SPEED STATIC VMOS RAM :
Features

General Description

High Speed Operation:
Access Time: 70ns Maximum

High Density 18 Pin Package

Single +5 Volt Power Supply

The AMI S2114H is a 4096 bit fully static RAM organized as 1024 words by 4 bits. The device is fully TTL
compatible on all inputs and outputs and has a single
+5V supply. The common data input/output pins facilitate interface with systems utilizing a bidirectional
data bus. The stored data is read out non-destructively
and is the same polarity as the original input data.

Completely Static Operation:
No Clocks Required

Completely TTL Compatible

Common Data I/O:
Three- State Outputs

The S2114H is fully static requiring no clocks or refreshing for operation. This simplifies device operation as no address setup times are required. The chip
select function facilitates memory system expansion
by allowing the input/output pins to be OR-tied to
other devices.
The S2114H is fabricated using AMI's proprietary
VMOS technology. This process permits the manufacture of high performance memory devices suitable
for high volume production.

Fan-Out of 5 TIL: IOL= 8mA @O.45V

Block Diagram

Logic Symbol

Pin Configuration

A,
A5

ADDRESS

64 X 64

DECODER

ARRAY

DRIVER

As
Ag

1 - - . . - - - 1/0,

ADDRESS

COLUMN

1--+...--

I--++-.I--++-t.....-

1/0 2
1/0 3
liD,

L..--.-----.""T""'1r--r----'

877310

877309

Truth Table
WE-----L~
877308

CS
H
L
L
L

Pin Names
AO - All
CS
I/Ol - 1/04

Address Inputs
WE
Chip Select
VCC
Data Input/Output

Write Enable
+5V Power

2.7

Inputs
WE
DIN
X
L
L
H_

X
L
H
X

Outputs
DOUT
Hi-Z
Hi-Z
Hi-Z
DOUT

Mode
Not Selected
Write "0"
Write "I"
Read

S2114H

Absolute Maximum Ratings*
Ambient Temperature Under Bias .............................................. - 10° C to 80° C
Storage Temperature ....................................................... - 65°C to 150°C
Voltage on Any Pin With Respect to Ground ....................................... - 0.5V to 7V
Power Dissipation ........ ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 W
*COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or at any other conditiort above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
effect device reliability.

D.C. Operating Characteristic (Vee = 5V ± 5%, TA = O°C to 70°C)
Symbol
ILl
II~O

lee
VIL
VIH
VOL
VOH

los

Parameter
Input Leakage Current
I/O Leakage Current
Power Supply Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output Short Circuit Current

Min.

Typ.

-0.5
2.0

Max.

Units

10
10
150
0.8

VIN = OV to 5.25V
CS = 2.4V; VIla = O.4V to Vee
VIN = 5.25V, TA = o°c

Vee
10(1

JJ.A
JJ.A
rnA
V
V
V
V
rnA

Max.

Units

Conditions

10
5

pF
pF

VIla = ov
VIN = OV

Vee
0.45

2.4

Conditions

IOL = SmA
IOH = -lmA
Duration not to exceed 30 sec.

Capacitance (TA = 25°C; f = 1.0 MHz)
Symbol
CIO
CIN

Parameter

Min.

Typ.

Input/Output Capacitance
Input Capacitance

A.C. Characteristics (Vce = 5V ± 5%, TA = 0° C to 70° C)
Symbol

Parameter

Conditions

Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address
Chip Select Access Time
Chip Select to Output Active
Output H-Z from Chip Select

Write Cycle Time
Write Time
Write Release Time
Output H-Z from Write Enable
Data to Write Time Overlap
Data Hold Time

70
50
0

tRC
tA
tOHA
teo
tex
tOTD

70
0
40
0
30

ns
ns
ns
ns
ns
ns

See A.C. Test
Conditions
&

Load

Write Cycle
twc
tw
tWR
tOTW
tDW
tDH

30
40
0
2.8

ns
ns
ns
ns
ns
ns

See A.C. Test
Conditions
&

Load

S2114H

Read Cycle (note 1)
Propagation Delay From Address Inputs

DOUT

'Re

Propagation Delay From Chip Select

'A_ _ _ _ _ _ _ __
tOHA

~------877313

Write Cycle (note 2)
'we

NOTES:
1. A read occurs during the overlap of a LOW CS and a HIGH WE.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is referenced to the positive transition of WE.
4. WE must be HIGH during all address transitions.
5. If the CS LOW transition occurs simultaneously with the WE LOW transition, then the output buffers remain in the high
impedance state.

A.C. Test Conditions

A.C. Test Load
+5V

510n

Input Pulse Levels ........

O.8V to 2.4V
S2114H

Input Rise & Fall Times

.......... IOns

Input and Output Timing Level ..... 1.5V

I'""
2.9

390n

ADVANCED PRODUCT DESCRIPTION

S2147

4096 BIT (4096 x 1)
HIGH SPEED STATIC VMOS RAM
Features

General Description

High Speed Operation:
Access Time: 55ns Max. (-3)

Automatic Power-Down

High Density 18 Pin Package

The AMI 82147 is a high speed 4096 bit fully static
RAM organized as 4096 one-bit words. The device is
fully TTL compatible and has a single +5V power
supply. It has separate data input and output pins for
maximum design flexibility. The three-state output
facilitates memory expansion by allowing the output
to be OR-tied to other devices. The stored data is
read out non-destructively and is the same polarity as
the input data.

Single +5V Power Supply

The automatic power down feature offers significant
system power savings. This feature causes no performance degradation, as chip enable access and address
access are equal. The 82147 is fully static eliminating
the need for clocks or address set up and hold times as
well as maximizing data rates since access times and
cycle times are equal.

D Completely Static Operation
D Completely TTL Compatible Inputs
D Three-State TTL Compatible Output

Fan-Out of 5 TIL: IOL = 8mA@ 0.45V
Block Diagram

The 82147 is fabricated using AMI's proprietary
VM08 technology. The process permits the manufacture of high performance memory devices suitable for
high volume production.
Logic Symbol

Pin Configuration

A,
A7

DDUT

A8
A9
AID
A11

D,N

Dour

CE
877312

Truth Table
Output

Inputs

Pin Names

Ao- A11 Address Inputs DIN
Data Input
CE
Chip Enable
DOUT Data Output
WE
Write Enable
Vcc
+5V Power

DIN

H
L
L
L

L
H

H
X

DOUT
H-Z
H-Z
H-Z
DOUT

Mode

Power

Deselected
Write "0;'
Write "I"
Read

Standby
Active
Active
Active

52147

Absolute Maximum Ratings*

Ambient Temperature Under Bias .............................................. _10° C to BO° C
Storage Temperature ....................................................... -65°C to 150°C
Voltage on Any Pin With Respect to Ground ....................................... -0.5V to 7V
Power Dissipation ................................................................... 1 W
*eOMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
-effect device reliability.

D.C. Characteristics: Vee

Symbol

= 5V ± 5%, TA = O°C to 70°C

Parameter

Min.

VOL
VOH
VIL
VIH
ILl
IILO I

Output LOW Voltage
Output HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current

los

Output Current Short
Circuit to Ground
S2147
Operating Current
S2147-3
S2147
Standby Current
S2147-3

lee
ISB

Typ.

Max.

Units

0.45

10
50

V
V
V
V
jJ.A
jJ.A

-100
160
1BO
20
30

rnA
rnA
rnA
rnA
rnA

Max.

Units

pF
pF

2.4
O.B

2.1

Conditions
IOL = BmA
IOH = -4.0mA

Vee = Max., VIN = a to Vee
CS = 2.1 V, Vee = Max.
VOUT = 0.4 to 4.5V
Vee = Max., for not more than
one second.
Vee = Max., CE = VIL,
TA = O°C, Outputs Open
Vee

= Max., CE = VIR

Capacitance: TA = 25° C, f = 1.0MHz

Symbol
CIN
COUT

Parameter

Min.

Typ.

Input Capacitance
Output Capacitance

A.C. Characteristics: TA

Conditions
VIN

VOUT

OV
=

= O°C to 75°C, Vee = +5V ± 5%

Read Cycle
Symbol
tRe
tAA
tAe
tOH
tLZ
tHZ
tpu
tpD

Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output LZ
Chip Enable to Output HZ
-Chip Enable to Power Up Time
Chip Disable to Power Down Time

S2147-3
Min. Max.
55
55
55
10
10
30

a
40

2.11

S2147
Min. Max.
70
70
70
10
10
30
50

Units
ns
ns
ns
ns
ns
ns
ns
ns

Conditions

See A.C. Test
Conditions
and
Waveform

52147

Write Cycle
Symbol
twc
tcw
tAW
tAS
twp
tWR
tDW
tDH
twz
tow

82147-3
Min. Max.
55
45
45
5
35
10
25
10
0
25
0
25

Parameter
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output HZ
Output Active from End of Write

READ CYCLE
Propogation Delay From Address Inputs

ADDRESS~:-

_'AA~

-'OHDATA OUT

----------'We
IT

IRC

--,

SUP~E~

HI Z

_LXXX*-

OATA VALID

.... --

lAS _ _ . .

-----,-----~~~I

.
I

!..

.,tWR.

twp _____

~-------

~~\\W+---=----JI

(I;

"-tHz~1

_lAC_I

"-'-tlz......---------i
DATA OUT

----------l~1

~bt------- lew --.-----~___

Propagation Delay From Chip Enable

8ee A.C. Test
Conditions
and
Waveforms

APORESS~l'--_ _ _ _ _ _ _ _ _ _ _ __ _ J [ ' _ - - - - -

DATA VALID

PREVIOUS DATA VALID

Conditions

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE

'"'

82147
Min. Max.
70
55
55
5
40
15
30
10
0
30
0
30

1·-low_~1

DATA OUT _ _ _----=O:.:..:AT.:.:.A.::.;:UN:.:.:OE::...:fl.::..:NE.:..O_ _ _-"L-_.c..cHI.::..Z_ _-'*I,-_DA_TA_O_UT-OA_TA-'N
HIZ

ee-------.--"'--..,..-----------l
..-tpo--"

....--tpu-----"

CURRENT I S B - - - - - - - , - - ; f

NOTES:
1. A read occurs during the overlap of a LOW CE and a HIGH WE.
2. A write occurs during the overlap of a LOW CE and a LOW WE.
3. tWR is referenced to the positive transition of WE.
4. WE must be HIGH during all address transitions.
5. If the CE LOW transition occurs simultaneously with the WE LOW transition, then output buffers remain in the high
impedance state.

A.C. Test Load

A.C. Test Conditions
ALL INPUTPUL5ES

Vee
- -------------

slon

DDIIT

90'"

- ----1-- - - - - - - - - - - - - +- - -

~~_-'I

GND

Joon

- -- -

:_10",

'::'

-+1

---10","

:_10n,

JOpF

L---_ _ _ _- ' GND

-, - - - - - - - - - - - - - - - - - - - - - - - 1 0 " "
I
I

3.5 Vp_p

GNDT

2.12

-i-- - - ---- ------- ---L-90 "o
I

!_10n,

...--10n,

54015/54025
1024 BIT (1024x1)
HIGH SPEED STATIC VMOS RAM

Features

General Description

Pin Compatible with 93415 IS40151 and
93425 IS40251

Single + 5V Power Supply

Completely TTL Compatible

Open Collector Output - S4015

The AMI 84015/84025 family of 1024x1 bit high speed
VM08 RAMs offers fully static operation with a single
5V supply. The device is completely TTL compatible
on inputs and output. The family is available in two
output configurations. The 84015 has an open collector
(open drain) output and the 84025 has a three-state output. The stored data is read out nondestructively and
is the same polarity as the original input data.

Three-State Output - S4025

Fan-Out of 10 TTL - IOL

Completely Static - no Clocks or Refreshing

= 16mA

The family is completely static requiring no clocks
or refreshing for operation. Chip 8elect (C8) controls
the output and simplifies memory system expan-sion.
The fast chip select time allows decoding the chip
select from the address without increasing address
access time.

@0.45V

Logic Symbol

Block Diagram

Ao
Al

Pin Configuration

D'N

1
2

A,
ADD RESS

32 X 32

Vee

D'N

A:J

A)
As

DOUT

GND

877249

877250

DOUT

As
As

Pin Names

Ao-Ag

Chip Select
Address Inputs

Write Enable

CS
DIN

DDUT

DIN
DOUT

Data Input
Data Output

Truth Table

DOUT

2.13

Output (DOUT)
S4015 84025

H-Z
H-Z
H-Z

H
877236

Inputs
WE DIN
X
X
L

H
H

Mode
Not selected
Write "0"
Write "I"
Read

S4015/S4025

General Description (Continued)
The S4015/S4025 is fabricated using AMI's proprietary VMOS process, thus allowing the production of high
speed MOS RAMs that are fully compatible with bipolar RAMs but offering the advantage of lower power
dissipation.

Absolute Maximum Ratings*
Ambient Temperature Under Bias
Storage Temperature
Output or Supply Voltages
Input Voltages
Power Dissipation

- 0.5V to + 7V
- 0.5V to + 5.5V
1 Watt

*COMMENT: Stresses above those listed under" Absolute Maximum Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

D. C. Characteristics: Vcc = 5V ± 5%, TA = O°C to 75°C
Symbol

Parameter

VOL
VOH
VIL
Vm
IIL

Output LOW Voltage
Output HIGH Voltage (S4025 Family)
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output Leakage Current
(S4015 Family)
Output Current (High Z) (S4025 Family)
Output Current Short Circuit to
Ground (S4025 Family)

ICEX
IOFF
los
Icc

Min.

Typ.

Max.

Units

0.45

V
V
V
V

2.4
0.8
2.1

Power Supply
Current

Conditions
Vcc=Min, IOL=16mA
Vcc=Min, IOH=-5.2mA

-40
40

J.lA
J.lA

J.lA

Vcc=Max, VOUT=4.5V

50
-50

J.lA
J.lA

-100

rnA

125

rnA

Vcc=Max, VouT=2AV
Vcc=Max, VOUT=0.5V
Vcc=Max, for not more
than 1 second
Vcc=Max
All Inputs Grounded
Output Open

Max.

Units

5
8

pF
pF

Vcc=Max, VIN-OAV
Vcc=Max, VIN=4.5V

Capacitance
Symbol

Parameter

CIN
COUT

Input Capacitance
Output Capacitance

Min.

2.14

Typ.

Conditions
All inputs=OV
Output=OV

54015/54025

A.C. Characteristics: VCC
Read Cycle
Symbol

5V ± 5%, TA

O°C to 75°C
84015(25) ~ 2
Min.
Typ.
Max.
40
40
60

Parameter
Chip Select Time
Chip Select Recovery Time
Address Access Time

tACS
tRCS
tAA

Units
ns
ns
ns

Conditions
See Test
Circuit &
Waveforms

ns
ns
ns
ns
ns
ns
ns
ns
ns

See Test
Circuit &
Waveforms

Write Cycle
Write Disable Time
Write Recovery Time
Write Pulse Width
Data Set-up Time Prior to Write
Data Hold Time After Write
Address Set-up Time
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time

tws
tWR
tw
tWSD
tWHD
tW8A
tWHA
tWSCS
tWHCS

40
40

0
40
5
5
5
5
5
5

Write Cycle

Read Cycle
Propagation Delay From Address Inputs

_t==_tAA~._ _
DOUT

U_~_:E_~FIN_EE~DD)K~V_A_Ll_DD_A_TA____________

_______________

Propagation Delay From Chip Select

~tACS----"

DOUT (S4015)

tRCS~

VALID DATA

DOUT (S4025)

V
J

VALID DATA

DATA
UNDEFINED

DOUT (S40251
877305

D'N

877304

A.C. Test Conditions

A.C. Test Load

All INPUT PULSES
Vee

----90%

I
Rl

I
1

- ---<------------ __ +__ ---10%

DOUT

GND - . - - - - - ' ,
30pF

270n
220n

600n
150n

:_10n,

':'

GNDT

877307

877306

2.15

~10n'

----------------------10%

3.5 Vp. p

GND

-1--

------------ --L-- SO%

1'-----------------';1

i-lon,

:-'--10n,

--...:

PRELIMINARY

S4017
4096 BIT (4096x1)
HIGH SPEED STATIC VMOS RAM
Features

General Description

The AMI S4017 is a high speed 4096 bit fully static
RAM organized as 4096 one-bit words. The device is
fully TTL compatible and has a single + 5V power
supply. It has separate data input and output pins for
maximum design flexibility. The three-state output
facilitates memory expansion by allowing the output
to be OR-tied to other devices. The stored data is read
out non-destructively and is the same polarity as the
original input data.

High Speed Operation:
Address Access Time: 55ns Maximum
Chip Select Access Time: 30ns Maximum

o
o
o
o
o

Fast Chip Select Optimizes Access Time
High Density 18 Pin Package
Single +5V Power Supply
Completely Static Operation
Completely TTL Compatible Inputs

Three-State TTL Compatible Output

Fan- Out of 5 TTL: IOL = 8mA @ 0.45V
Block Diagram

The fast chip select access time offers a significant
performance advantage. As the chip select is normally
decoded from the address, the time required to decode
the chip select will not impact the overall access time.
The S4017 is fabricated using AMI's proprietary
VMOS technology. The process permits the manufacture of high performance memory devices suitable for
high volume production.
Pin Configuration

Logic Symbol

DDUT

817312

Truth Table

CS
H
L

Pin Names

Ao -Au Address Inputs DIN
Data Input
CS
Chip Select
DOUT Data Output
Write Enable
Vee
+5V Power

2.16

Inputs
WE
DIN
X
X
L
L
H
L
X
H

Output
DOUT
H-Z
H-Z
H-Z
DOUT

Mode
Not Selected
Write "0"
Write "1"
Read

54017

Absolute Maximum Ratings*
Ambient Temperature Under Bias .............................................. _10° C to 80° C
Storage Tern perature ....................................................... - 65° C to 150 ° C
Voltage on Any Pin With Respect to Ground ....................................... -0.5V to 7V
Power Dissipation ................................................................... 1 W
*eOMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
effect device reliability.

D.C. Characteristics: Vee = 5V ± 5%, TA = O°C to 70°C
Symbol

Parameter

Min.

VOL
VO H
VIL
VIH
ILl
IILO I

Output LOW Voltage
Output HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current

los

Output Current Short
Circuit to Ground

Typ.

Max.

Units

0.45

10
50

V
V
V
V
pA
pA

-100

rnA

125

rnA

Max.

Units

5
8

pF
pF

2.4
0.8
2.1

Conditions
IOL
IOH

= 8mA
= -4.0mA

\ce = Max., VIN = 0 to Vee
CS = 2.1 V, Vee = Max.
VOUT = 0.4 to 4.5V
Vee = Max., for not more than
one second.
-

Power Supply
Current

Icc

Vee = Max., CS = VIL
Output Open

Capacitance: TA = 25°C, f = 1.0MHz
Symbol
CIN
COUT

Parameter

Min.

Typ.

Input Capacitance
Output Capacitance

A.C. Characteristics: TA

Conditions
VIN = OV
VOUT = OV

O°C to 75°C, Vee = +5V ± 5%

Read Cycle

Symbol
tRe
tAA
tAes
tOH
tLZ
tHZ

Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Select to Output L - Z
Chip Select to Output H - Z

S4017-3
Min. Max.
55
55
30
10
10
30

2.17

S4017
Min. Max.
70
70
40
10
10
30

Units
ns
ns
ns
ns
ns
ns

Conditions
See A.C. Test
Condition
and
Waveform

S4017

Write Cycle
S4017·3

S4017
Min. Max.

Symbol

Parameter

twc

Write Cycle Time

tcw
tAw
tAS
twp

Chip Select to End of Write

40
45
5
35

Min.

Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write

tWR
tDW
tDH
twz

Data Hold Time
Write Enable to Output HZ

tow

Output Active from End of Write

Write Cycle

Max.

55
5
40
15

25
10

30
10

ns
ns

and
Waveforms

ns
ns

Read Cycle
II
ADDRESS

es ~

..-~. ~--lRe

.
..

J--l

_twp_

I·

DATA IN

f--1DW_

.'WZ--l

DATA UNDEfiNED

DATA OUT

DATA IN VALID

. . . . - - - tAA------.
"'-'-tOH~

.'WR~

(})

~\\\\l

Propogation Delay From Chip Select

'We

III
tAW
......-...tAs--~1

DATA DUT_ _...:.::..::_ _.................WUI'-_ _..;cDA_T_AV_A_lID_ _ _-'-_HI_Z_

DATA DUT

See A.C. Test
Conditions

ns
ns
ns

Propagation Delay from Chip Enable

ADDRESS

Conditions

Units

..-tDW ___ 1

HIZ

DATA DUT" DATA IN

DATA VALID

PREVIDUS DATA VALID

A.C. Test Load

A.C. Test Conditions
ALL INPUT PULSES

Vee

----90%

I
I

510n

DOUl

- ----1--------------

-..----' ,
GNO

30010

'::"

:_10ns

+- I---10%
I

:~lOns

30pF

GND

-----

----~---------

- -_
- -_- _
- -_- _
- J" ~- _L
-L- - -_- _
I -~

GNoT ~

877307

877306

2.18

----'-10%

I
I

3.5 Vp~p

90%

II _ ' O n s

-I

,-IOns

ADVANCED PRODUCT DESCRIPTION

84028
16,384 BIT (2048 X 8)
8T ATIC VM08 RAM
Features

General Description

High Speed Operation:
Access Time: 200ns Max.

Single + 5V Power Supply

Pin Compatible with 16K EPROM/ROM

Fully Static Operation

The AMI 84028 is a 16,384 bit fully static VM08 random
access memory organized as 2048 words by 8 bits. The
device is fully TTL compatible on all inputs and outputs and has a single +5V power supply. The common
data input/output pins and output enable function
facilitate interface with systems utilizing a bi-directional data bus. Data is read out non-destructively and
is the same polarity as the input data.

Completely TTL Compatible

Common Data Input/Output:
Three-State Outputs

Output Enable Function for Easy Control of
Data Output

The 84028 is fully static requiring no clocks or refreshing for operation. This simplif~es device operation as
no address setup or hold times are required. The chip
select and output enable functions facilitate memory
expansion by allowing the input/output pins to be ORtied to other devices.
The 84028 is fabricated using AMI's proprietary
VM08 technology. This permits the manufacture of
high performance memory devices suitable for high
volume production.
Pin Configuration

Logic Symbol

Block Diagram

A,
A,

A,
ADDRESS

DECODER

DRIVERS

16,J84BIT

AD
A,

AlO

A,
A,

Vee

ADDRESS
DECODER

liD,

DRIVERS

liD,

I/O,

AlO

liD,

I/O s

GND

1/0 4

AlO
I/O,
I/O,
I/O,

WE-----0--01

liD,

CS ----....-+<"----J

I/Os
liD,

Truth Table

I/O,
I/O,

DE - - - - - - 0 1

OUTPUT ENABLE

Pin Names
Ao - A IO
1/0 8

I/O I

MODE

Deselected

Read

Address Inputs
Data Inputs/Outputs
Chip Select

OE
WE

Vee

Output Enable
Write Enable
+ 5V Power Supply

Write
Write

Selected, Output Hi - Z

Data In Data Ou

Hi-Z

Data Out
Hi-Z

Data In

Hi-Z

55101
1024 BIT (256x4)
STATIC CMOS RAM
Features

General Description

Ultra Low Standby Power

o
o

Data Retention at 2V (L Version)
Single +5 Volt Power Supply

Completely Static Operation

Completely TTL Compatible Inputs

Three- State TTL Compatible Outputs

The AMI S5101 family of 256 x 4-bit ultra low power
CMOS RAMs offers fully static operation with a single
+ 5 volt power supply. All inputs and outputs are
directly TTL compatible. With data inputs and outputs on adjacent pins, either separate or common data
I/O operations can easily be implemented for maximum design flexibility. The three-state outputs will
drive one full TTL load and are disabled (high impedance state) by output disable (OD), either chip enable
(CEI or CE2), or in a write cycle (R/W = LOW). This
facilitates the control of common data I/O systems.

Pin Configuration

Logic Symbol

Block Diagram

Ao--------I
A,

--------i
AD

A,-------I

A3 - - - - - - - - - - I
A, _ _ _ _ _-----I

Az
A3
Zl

A4
A5
As

A5 - - - + - - - - - - - I

----1----1

A,---+-------I

011

001

Olz

OOz

DI,

0°3

01 4

0°4

eEZ

DO,

CEl----oj

RIW CE2

DO,

--,"""...,--00 3
L

871301

Pin Names

CEI

CE2

R/W

DIN

Output

Mode

H
X
X
L
L
L

X
X
H
H
L
L

X
X
H
L
L
H

HighZ
HighZ
HighZ
HighZ
High Z
Dout

Not selected
Not Selected
Output- Disabled
Write
Write
Read

H
H
H

877302

Truth Table

ill

_ _ _ _ _~ ......._'___OO,

001-------~

X
X
X
X
X

AO-A7
OIl - OI4
DOl- D04
OD

2.20

Address Inputs
Data Inputs
Data Outputs
Output Disable

CEI
CE2
R/W
VCC

Chip Enable
Chip Enable
Read/Write Input
+5 Volt Power Supply

85101

General Description (Continued)
The stored data is read out nondestructively and is
the same polarity as the original input data. The S5101
is totally static, making clocks unnecessary for a new
address to be accepted. The device has two chip enable
inputs (CE1 and CE2) allowing easy system expansion.
CE2 disables the entire device but CE1 does not disable the address buffers and decoders. Thus, minimum
power dissipation is achieved when CE2 is low.

The L version of the S5101 has the additional feature
of guaranteed data retention with the power supply
as low as 2 volts. This makes the device an ideal choice
when battery augmented non-volatile RAM storage is
mandatory.
The S5101 is fabricated using a silicon gate CMOS
pro~ess suitable for high volume production of ultra
low power, high performance memories.

Absolute Maximum Ratings*
Ambient Temperature Under Bias .............................................. -IO°C to 80°C
Storage Temperature ....................................................... -65°C to 150°C
Voltage on Any Pin with Respect to Ground ................................ -O.3V to Vee +O.3V
Maximum Power Supply Voltage ...................................................... IIV
Power Dissipation ................................................................... I W
*eOMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

D.C. Characteristics: TA = O°C to 70°C, Vee = 5V ± 5% (Unless otherwise specified)
Symbol

Limits
Min. Max.
1

ILl

Parameter
Input Leakage Current

ILO

Output Leakage Current

Icc

Operating Supply Current

rnA

leeL

Standby Supply Current

VIL
VIH
VOL
VOH

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage

10
140
500
0.65
Vee
0.4

pA
pA
pA
V
V
V
V

S5101L1,S5101L
S5101L3
S5101L8, S5101-8
-0.3
2.2
2.4

Units
pA

Conditions
VIN = OV to Vee
CE1 = VIH
VOUT = OV to Vee
Outputs = Open,
VIN = VIL to Vee
VIN = OV to Vee
except
CE2 <0.2V

10L = 2 rnA
10H - -1 rnA

Capacitance
Symbol
CIN
Co

Limits
Min. Max.
8
12

Parameter
Input Capacitance
Output Capacitance
2.21

Units
pF
pF

Conditions
VIN = OV, on all Input Pins
Vo =OV

55101

A.C. Characteristics for Read Cycle: TA

Symbol

Parameter

TRC
TACC
TC01
TC02
TOD

Read Cycle Time
Access Time
CE1 to Output Delay
CE2 to Output Delay
Output Disable to Enabled
Output Delay

TDF

Output Disable to Output
B-Z State Delay

TOB1

Output Data Valid Into Next
Cycle with respect to
Address
Output Data Valid Into
Next Cycle with respect
to Chip Enable

TOB2

= oce to 70 ce, V cc = 5V ± 5% (Unless otherwise specified)
S5101L
S5101L3
Limits
Max.
Min.
650
650
600
700

S5101L1
Limits
Min.
Max.
450
450
~OO

500

350

250
0

S5101L8
S5101·8
Limits
Max.
Min.
800
800
800
850

130

150

Units
ns
ns
ns
ns

450

200

Conditions

See AC.
Conditions
of Test and
AC. Test
Load

Read Cycle

,1/

ADDRESS

)1\

-11\

\J
eE2

V
- 1-11

V
/ - - TOH2 -

"!\

TC01

K
UT-

f - - TOH1 -

TCOI

DATA 0

TRC

1--- - - - - - - - - -

Too---

----'V

-t----------------J~
TACC

F TOF -

DATA OUT
VALID

---,1/

----rAce

___ .11\.

DATA OUT VALID

H-Z
STATE

---

1076145

Note:
1. OD may be tied low for seaprate I/O information.
2. The output will go into a high impedance state if either CE1 is high, CE2 is low, OD is high or R/W is low.

2.22

55101
A.C. Characteristics for Write Cycle - Separate or Common Data I/O Using Output Disable

= oOe to

Vcc

= 5V ± 5% ( Unless otherwise specified)

Symbol

Parameter

TWC
TAW
TCW1
TCW2
TDW

Write Cycle Time
Address To Write Delay
CE1 to Write Delay
CE2 to Write Delay
Data Set-Up to End of
Write Time
Data Hold After End of
Write Time
Write Pulse Width
End of Write to New
Address Recovery Time
Output Disable to
Data-In Set-Up Time

TDH
TWp
TWR
TDS

85101L
S5101L3
Limits

85101L1
Limits
Min.
450
130
350
350

Max.

Min.
650
150
550
550

85101L8
85101-8
Limits

Max.

Min.
800
200
650
650

Units

Max.
ns
ns
ns
ns

250

400

450

50
250

100
400

100
450

ns
ns

100

130

150

200

Write Cycle - For Separate or Common Data I/O

ADDRESS

JIL-

--11\

TCWl

CE2

TCW2

- t--I1
00

V--Tos--

TOH-

DATA IN

'V
)f\

DATA IN STABLE

Tow

RIW

--TAW

Twp

TWR - - -

1~'"'1",----r _ _ _~C
HIZSTATE

DATA OUT

1076147

2.23

Conditions

•

8ee A.C.
Conditions
of Test
and A.C.
Test Load

S5101

Low VCC Data Retention Characteristics for S5101 L, S5101 L1, S5101 L3 and S5101 L8
TA = O°C to 70°C
Symbol
VDR

Parameter
Vcc for Data Retention

ICCDR

Data Retention
Supply Current

TCRD
TR

Min.
2.0

S5101L1, S5101L
S5101L3
S5101L8
Chip Deselect to Data Retention Time
Operation Recovery Time

Notes:
[1] For guaranteed low Vee Data Retention
[2] 'IRe = Read Cycle 'TIme.

Limits
Max.
10
140
500

0
TRd 2J

Units
V
IJ,A
IJ,A

""A
ns
ns

[1]

Conditions
CE2$0.2V
Vcc = VDR
TR = TF = 20ns
CE2$0.2V

2.0V, order must specify S5101L, S5101L1, S5101L3 or S5101L8.

Low Vee Data Retention Wave Form

fVee

eE2

0_\

...f\CD
.3

....

TeDR

-I
S1CD

. . - - TR

(j)

G:r't
1.
2.

DATA RETENTION
MODE

-r0CD

4.75V

VDR
VIH

O.tV

477215

A.C. Test Load
1.73V

I---

(

.:>

I--S5101
D.U.T.

t---

660Sl

A.C. Conditions of Test
O.65V to 2.2V
Input Levels
20ns
Input Rise and Fall Time
Timing Measurement Reference Level
1.5V

-=1076146

2.24

S650S/S650SA
1024 BIT (1024 X 1)

STATIC CMOS RAM
Features

General Description

Ultra Low Standby Power

S6508 Completely TTL Compatible

S6508A Completely CMOS Compatible

4V to 11 V Operation (S6508A)

Data Retention at 2V

Three-State Output

Low Operating Power: 10mW

Fast Access Time: 115ns

The AMI S6508 family of 1024x1 bit static CM08
RAMs offers ultra low power dissipation with a single
power supply. The device is available in two versions.
The basic part (86508) operates on 5V and is directly
TTL compatible on all inputs and the three-state output. The S6508 "A" operates from 4V to 11V and is
fully CMOS compatible. The data is stored in ultra
low power CMOS static RAM cells (six transistor).
The stored data is read out nondestructively and is
the same polarity as the original input data. The
address is buffered by on-chip address registers. These
internal registers are latched by the HIGH to LOW
transition of chip enable (CE). The write enable and
chip enable functions are designed such that either
separate or common data I/O operations can be easily
implemented for maximum design flexibility.

1MHz (5V)

10V

Block Diagram

Pin Configuration

Logic Symbol
CE

DIN

AO
AI

AO----j
AI _ _----'
A2
A3

ROW

~~~;!~

A2
32,32
ARRAY

OECOOER

A4----j

A5--+-I

A 6 - - + - l COLUMN

~~~;!~

A7
AS

DECODER

A91--+-I
DOUT
DOUT
DINI----+--+-~J

Pin Names
AO-A9

Address Inputs

DIN

Data Input

Wri te En able

DOUT

Data Output

VCC

Power Supply

2.25

Chip Enable

S650S/S650SA

General Description (Continued)
The S6508 is fabricated using a silicon gate CMOS
process suitable for high volume production of high
performance, ultra low power memories. When
deselected (CE = HIGH), the S6508-1 draws less than
10 microamps from the 5V supply. In addition, it

offers guaranteed data retention with the power
supply as low as 2 volts. This process makes the device
an ideal choice where battery augmented nonvolatile
RAM storage is mandatory.

CMOS to TTL - S6508/S6508-1
Absolute Maximum Ratings
Supply Voltage .................................................................... 8.0V
Input or Output Voltage Supplied .................................... GND - 0.5V to VCC + 0.5V
Storage Temperature Range ................................................. -65°C to 150°C
Operating Temperature Range, Commercial ........................................ O°C to 70°C
D.C. Characteristics (Vce
Symbol

= 5.0V ± 10%, TA = O°C to 70°C)

Parameter

Min.

VIH
VIL
IlL
VOH2
VOH1

Logical "1" Input Voltage
Logical "0" Input Voltage
Input Leakage
Logical "1" Output Voltage
Logical "1" Output Voltage

VOL2
VOL1
10

Logical "0" Output Voltage
Logical "0" Output Voltage
Output Leakage
IS6508
Standby Supply Current, S6508-1

ICCL
ICC
CIN
Co

Units

Max.

V
V
fJ.A
V
V

VCC-2.0
0.8
1.0

-1.0
VCC- 0.01
2.4

GND+O.Ol
0.45
1.0
100
10

-1.0

Supply Current S6508/S6508-1
Input Capacitance
Output Capacitance

2.5
7.0
10.0

Conditions

OV < VIN < VCC
lOUT = 0
10H = -0.2mA

V
V
fJ.A
fJ.A
fJ.A
rnA
pF
pF

lOUT = 0
10L = 2.0mA
OV< VO< VCC,CE=VIH
VIN = VCC
f = 1MHz

A.C. Characteristics (VCC = 5.0V ± 10%, CL = 50pF (One TTL Load), TA = O°C to 70°C)
Symbol

Parameter

tACC
tEN
tDIS
tCEH
tCEL
twp
tAS
tAH
tDS
tDH
tMOD

Access Time from CE
Output Enable Time
Output Disable Time
CE HIGH
CELOW
Write Pulse Width (LOW)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Data Modify Time

S6508-1
Min. Max.

S6508
Min. Max.

300
180
180

460
285
285

200
300
200
7
90
200
0
0

300
460
300
15
130
300
0
0
2.26

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Conditions

See A.C. conditions of
test and A.C. test load.

S6508/S6508A

CMOS to CMOS - S6508A!S6508A-1
Absolute Maximum Ratings

Supply Voltage ................................................................... 12.0V
Input or Output Voltage Applied ......................................... -0.5V to VCC + 0.5V
Storage Temperature Range ................................................. _65°C to 150°C
Operating Temperature Range, Commercial ........................................ O°C to 70°C
D.C. Characteristics (VCC = 4V to 11V, TA = O°C to 70°C)
Symbol
VIH
VIL
IlL
VOH
VOL
10

ICCL
ICC
CIN
Co

Min.

Parameter

Max.

Logical "1" Input Voltage
70% VCC
Logical "0" Input Voltage
20% VCC
-1.0
1.0
Input Leakage
Logical "1" Output Voltage
VCC- 0.01
GND+0.01
Logical "0" Output Voltage
-1.0
1.0
Output Leakage
500
S650SA
Standby Supply Current
100
S650SA-1
Supply Current
2.5
VCC=5V
(S650SA/S650SA-1)
VCC=10V
5.0
7.0
Input Capacitance
10.0
Output Capacitance

Units
V
V
J.1A
V
V
J.1A
J.1A
J.1A
mA
mA
pF
pF

Conditions

OV< VIN< VCC
lOUT = 0
lOUT = 0
OV < V 0 < V CC, CE = V IH
VIN = VCC
f = IMHz

A.C. Characteristics (VCC = VCC ± 10%, TA = O°C to 70°C)
Symbol

Parameter

tACC

Access Time from CE

tEN

Output Enable Time

tDIS

Output Disable Time

tCEH

CE HIGH

tCEL

CELOW

twp

Write Pulse Width (LOW)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tMOD

Data Modify Time

VCC
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V

S650BA-l
Min. Max.

S6508A
Units
Min. Max.
460
lS5
285
120
285
120

275
115
165
75
165
75
175
80
275
115
175
80
7
7
80
40
175
80
0
0
0
0
2.27

300
125
460
185
300
125
15
15
130
60
300
125
0
0
0
0

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Conditions

See A.C. conditions
of test and A.C. test
load.

S6508/S6508A

Read Cycle

Write Cycle

AO·A9

DIN

\'----_.---J1

~I_-'CEH--I '--

r=:~6--'CEL

- - - - - - l..

X'----_ _ _ __

----------X'--__---JX~----

Read Modify Write Cycle

L
-1---'CEH--I
1

di1 , ,

\ ' - - - -_ _- . . . J

AOA9~

_ _ _ __

I
I' '" -ICD
~l~ll~
~I~I

DOUT

=itl

-----l~ ,~ I
~.

"~I
-..JXr--------'lXr------

DIN _ _ _ _ _ _ _ _ _ _ _

NOTES:
1. The write operation is terminated on any positive edge of Chip Enable (CE) or Write Enable (WE).

2. The data output will be in the high impedance state whenever WE is LOW.
3. WE is HIGH during a read operation.
4. Rise and fall times of VCC equal 20ns.

2.28

S6508/S6508A

Low VCC Data Retention Characteristics (TA = O°C to 70°C)

Min.

Parameter

8ymbol

VCC for Data Reten tion
Data Retention
8upply Current
Deselect 8etup Time
Recovery Time

VDR
ICCDR
tCDR
tR

Max.

2.0

Units
V

10
1.0

8650B,8650BA
8650B-l,8650BA-l

tCEH
tCEH

J1A
J1A

Conditions
CE = 2.0V
VCC = VDR Min.
VIN = VCC

ns
ns

Low VCC Data Retention Waveform (note 4)

Vee

----------'\I-KG)

~l~

CD
I \CD
~------------------~

-.....

teoR~

r'"

@~
877243

A.C. Test Load

2.217V

()

A.C. Test Conditions
.~

OUTPUT ~o--------.

909[2

Input Levels .................... VIL to VIH
Input Rise & Fall ....................... 20ns
Timing Measurement Reference Level
8650B/8650B-l ...................... 1.5V
8650BA/S650B-l ................. 50% V CC

877244

2.29

1 vee MIN
22.0V

3 vlH
4 vlL

S6518/S6518A
1024 BIT (1024x1)
STATIC CMOS RAM
Features

General Description

Ultra Low Standby Power

S6518 Completely TTL Compatible

S6518A Completely CMOS Compatible

4V to 11 V Operation (S6518A)

Data Retention at 2V

Three-State Output

Low Operating Power: 10mW @lMHz (5V)

Fast Access Time: 115ns @10V

The AMI S6518 family of 1024xl bit static CMOS
RAMs offers ultra low power dissipation with a single
power supply. The device is available in two versions.
The basic part (S6518) operates on +5V and is directly
TTL compatible on all inputs and the three-state output. The S6518 "A" operates from +4 V to +11 V and
is fully CMOS compatible. The data is stored in ultra
low power CMOS six transistor static RAM cells. The
data is read out non-destructively (into a data latch)
and is the same polarity as the original input data.
The address is buffered by on-chip address registers.
These internal registers are latched by the HIGH to
LOW transition of chip enable (CE). In addition,
there are two chip selects (CSI and CS2) which
facilitate memory expansion. The write enable, chip
enable and chip select functions are designed such
that either separate or common data I/O operations
can be easily implemented.
Pin- Configuration

Logic Symbol

Block Diagram

CSI CSl

AO
16

0,.

A2
A3
A4
A5

DOUI

ffi

Vee

0,.

DOUI

GND

Truth Table
Output

Inputs

Pin Names

CSI

CS2

DoUT

Hi·Z

Write "0"

Hi·Z

Write "I"

DoUT
Hi·Z

Deselected
Deselected

Addrpss Inputs

CSl, CS2

Chip Selects

Hi·Z

Data Input

Write Enable

Hi·Z

Data Output

Vee

Power Supply

DoUT

Chip Enable

2.30

Mode

Read

Deselected
Output Latched
To Last Data

AMI,

S6518/S6518A

General Description (Continued)

supply. In addition, the 86518 family of[prs guaranteed data retention with the power supply as low as
2 volts. This makes the device an ide'al choice when
battery augmented non-volatile nAl\1 storage' is
mandatory.

The S6518 is fabricated using a silicon gate CMOS
process suitable for high volume production of high
performance, ultra low power memories. When deselected (CE = HIGH, CSI or CS2 = HIGH), the
S6518-1 draws less than 10 microamps from the +5V
CMOS to TTL - S6518/S6518-1
Absolute Maximum Ratings

Supply Voltage .................................................................... 8.0V
Input or Output Voltage Supplied .................................... GND - 0.5V to Vec + 0.5V
c
Storage Temperature Range ................................................. -65°C to 150 C
Operating Temperature Range, Commercial ........................................ O°C to 70"C
D.C. Characteristics (VCC = 0.5V ± 10%, TA = O°C to 70°C)
Symboli Parameter

A.C. Characteristics (VCC

Min.

Parameter

tACC
tEN
tDIS

Access Time from CE
Output Enable Time
Output Disable Time
CE HIGH
CE LOW
Write Pulse Width (LOW)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Data Modify Time

tCEL
twp
tAS
tAH
tDS
tDH
tMOD

Max.

= 5.0V ± 10%, CL = 50pF (One TTL

Symbol

~EH

Units

Load), TA = O°C to 70°C)

S6518-1
Min. Max.

86518
Min. Max.

300
180
180

460
285
285

200
300
200
7
90
200
0
0

300
460
300
15
130
300
0
0
2.31

Conditions

Units

Conditions

ns, ns
ns
ns
See A.C. conditions of
ns
test and A.C. test load.
ns
ns
ns
ns
ns
ns

S6518/S6518A

CMOS to CMOS - S6518A/S6518A-1

Absolute Maximum Ratings
Supply Voltage ................................................................... 12.0V
Input or Output Voltage Applied ......................................... -0.5V to VCC + 0.5V
Storage Temperature Range ................................................. -65°C to 150°C
Operating Temperature Range, Commercial ........................................ O°C to 70°C
D.C. Characteristics (VCC

= 4V to 11V, TA = O°C to 70°C)

Symbol

Parameter

VIH
VIL
IlL
VOH
VOL

Logical "I" Input Voltage
Logical "a" Input Voltage
Input Leakage
Logical "1" Voltage
Logical "a" Voltage
Output Leakage
Standby
S6518A
Supply Current
S6518A-1
Supply Current
VCC = 5V
(S6518A/S6518A-1) VCC = 10V
Inpu t Capaci tance
Output Capacitance

ICCL
ICC
CIN
Co

A.C. Characteristics (VCC
Symbol

Min.

tACC

Access Time from CE

tEN

Output Enable Time

tDIS

Output Disable Time

tCEH

CE HIGH

tCEL

70% VCC

CELOW

twp

Write Pulse Width (LOW)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tMOD

Data Modify Time

20% VCC
1.0

-1.0
VCC-0.01

GND+0.01
1.0
500
100
2.5
5.0
7.0
10.0

-1.0

VCC ± 10%, TA

Parameter

Units

Max.

VCC
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V

Conditions

V
V
I1A

V
V
I1A
I1A
I1A

rnA
rnA
pF
pF

.~ 909~!

Input Levels

..................... VIL to VIH

Input Rise & Fall .................. . . . .. 20ns
Timing Measurement Reference Level
OUTPUTD::;----.

S6518/S6518-1 ..... , ........... , ... 1.5V
S6518AjS6518A-1

877244

2.34

..............

50% VCC

PRELIMINARY

S4216B
16,384 BIT (2048 X 8)
STATIC VMOS ROM
Features

General Description

Fast Access Time: 250ns Maximum

Fully Static Operation

Single +5V ± 10% Power Supply

Directly TTL Compatible Inputs

The AMI S4216B is a 16,384 bit static mask programmable VMOS ROM organized as 2048 words by 8 bits.
The device is fully TTL compatible on all inputs and
outputs and has single + 5V power suply. The threestate outputs facilitate memory expansion by allowing
the outputs to be OR-tied to other devices.
The S4216B is fully compatible with 16K UV EPROMs
(+ 5V version) making system development much easier

Three-State TTL Compatible Outputs

Three Programmable Chip Selects

EPROM Pin Compatible

Fan-Out of 5 TTL: IOL = 8mA @ O.4V

Block Diagram

and more cost effective. It is fully static, requiring no
clocks for operation. The three chip selects are mask
programmable, the active level for each being specified
by the user.
The S4216B is fabricated using AMI's proprietary NChannel VMOS technology. This permits the manufacture of very high density, high performance mask programmable ROMs.

Logic Symbol
CSI

CS1

Pin Configuration
CS3

AO
AO
Al
A1
A3
A4

ADDRESS
DECDDER
DRIVER

AS
AS

ADDRESS
DECODER
DRIVER

CHIP
SELECT
DECDDER"

877299

877300

Pin Names
Ao -AlO
01- 0 8
CSI - CS 3

"PROG RAMMABLE CHIP SELECTS
877273

Vee

2.35

Address Inputs
Data Outputs
Chip Select Inputs
+5V Power Supply

542168

Absolute Maximum Ratings*
Ambient Temperature Under Bias .............................................. -10°C to SO°C
Storage Temperature ....................................................... -65°C to 150°C
Output or Supply Voltage ...................................................... -0.5V to 7V
Input Voltage ............................................................. -0.5V to 5.5V
Power Dissipation ................................................................... 1 W
*eomment:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any other condition above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

D.C. Characteristics: TA

O°C to 70°C, Vee

Parameter

VOL
VOH
VIL
VIH
ILl
ILO

Output LOW Voltage
Output HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current

lee

Power Supply Current
=

25°C, f

5V ± 10%

Min.

Symbol

Capacitance: TA

Typ.

2.4
- 0.3
2.2

Max.,

Units

0.4

V
V
V
V

O.S

Conditions
IOL = SmA
IOH = -SOOJ1A

Vee
10
10

JlA

rnA

Max.

Units

Conditions

S
10

pF
pF

VIN = OV
VOUT = OV

Max.

Units

250
100

ns
ns

100

VIN = 0 to 5.5V
Vo = 0.4 to 5.5V, Chip
Deselected
Vee = Max., TA = O°C,
Outputs Open

J.1A

1Mhz

Symbol

Parameter

CIN
COUT

Input Capacitance
Output Capacitance

Min.

Typ.

A.C. Characteristics: TA = 0 to 70°C, Vee = 5V ± 10%
Symbol

Parameter

tAA
tAes

Address Access Time
Chip Select Access Time
Chip Select Tum-off
Time

tOFF

Min.

Typ.

Conditions
See A.C. Test
Conditions
& Waveforms

Waveforms

~-,.====t='''--j.

tOFF

0, - 08

*:,--VA_lI_D_DA_TA_ _ _ __

1071319

Propagation From Chip Select

Propagation From Address

2.36

84216B

A.C. Test Load

A.C. Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input/Output Timing Levels

O.BV to 2.2V

IOns

450n

1.5V
S4216

Boon

1077318

Custom Programming

The preferred method of pattern submission is the AMI Hex format as described below, with its built- in address
space mapping and error checking. This is the format produced by the AMI Assembler. The format is as follows
and may be on paper tape, punched cards or other media readable by AMI.
Position
1
2

3,4

5,6,7,B
9, ... ,N

N+l, N+2

Example:

Description
Start of record (Letter S)
Type of record
0- Header record (comments)
1 - Data record
9 - End of file record
Byte Count
Since each data byte is represented as two hex characters, the byte count must be multiplied
by two to get the number of characters to the end of the record. (This includes checksum and
address data.) Records may be of any length defined in each record by the byte count.
Address Value
The memory location where the first data byte of this record is to be stored. Addresses should
be in ascending order.
Data
Each data byte is represented by two hex characters. Most significant character first.
Checksum
The one's complement of the additive summation (without carry) of the data bytes, the address,
and the byte count.

Sl13000049E9FI0320F0493139F72000F5EOF00126
S9030000FC
><

'E'E
00 ~~
_
CJ CJ

ell
ell

~~ § ~

§
~

'Cfo8 ~
~<

--~ ~tAE--J,~~'''j

DO-D)

VALID DATA

See Test Circuit
& Waveforms

2.42

t=. .=0r---_
Y{~..

DO-D) _ _ _ _ _ _ _

>$-

VALID

S6831 AlB

A.C. Test Conditions

Output Load ................................................... 1 TTL Gate and CL = 100 pF
Input Pulse Levels ............................................................. O.B to 2.4 V
Input Rise and Fall Times (10% to 90%) ................................................ 20 ns
Timing Measurement Reference Level

Input ...................................................................... IV and 2.2V
Output .................................................................. O.BV and 2.0V
Custom Programming

The preferred method of pattern submission is the AMI Hex format as described below, with its built-in address
space mapping and error checking. This is the format produced by the AMI Assembler. The format is as follows
and may be on paper tape, punched cards or other media readable by AMI.
Position
1

3,4

5,6,7,B

9, ... ,N
N+1, N+2

Example:

Description
Start of record (Letter S)
Type of record
o - Header record (comments)
1 - Data record
9 - End of file record
Byte Count
Since each data byte is represented as two hex characters, the byte count must be multipli~d
by two to get the number of characters to the end of the record. (This includes checksum and
address data.) Records may be of any length defined in each record by the byte count.
Address Value
The memory location where the first data byte of this record is to be stored. Addresses should
be in ascending order.
Data
Each data byte is represented by two hex characters. Most significant character first.
Checksum
The one's complement of the additive summation (without carry) of the data bytes, the address,
and the byte count.
Sl13000049E9F10320F0493139F72000F5EOF00126
S9030000FC

'E'E
00 ~1
_
U U
~~ § ~
c.>

,"'"

til

llA~1

Sll3000049E9F10320F0493139F72000F5EOF00126
NOTES:
1. Only positive logic formats for CSI and CS2 are accepted. 1 = VHIGH; 0 = VLOW
2. A "0" indicates the chip is enabled by a logic O.
A "1" indicates the chip is enabled by a logic 1.
3. Paper tape format is the same as the card format above except:
a. The record should be a maximum of 80 characters.
b. Carriage return and line feed after each record followed by another record.
c. There should NOT be any extra line feed between records at all.
d. After the last record, four (4) $$$$ (dollar) signs should be punched with carriage return and line feed indicating end of file.

2.46

ADVANCED PRODUCT DESCRIPTION

54532
32, 768 BIT (4096 X 8)
UV ERASABLE VMOS EPROM
Features

General Description

Single + 5 Volt Power Supply

Fast Access Time: 250ns Maximum

Automatic Power Down

Pin Compatible with AMI's 32K ROM: S68332

Fully TTL Compatible During Read and
Program

The 84532 is a 32,768 bit ultraviolet light erasable,
electrically programmable read-only memory (EPROM)
organized as 4096 words by 8 bits. It is fabricated using
AMI's proprietary N-channel VM08 technology. The
device is fully static requiring no clocks for operation.
All the inputs and outputs are fully TTL compatible
during both the read and~ program modes. The 84532
operates from a single +5V supply (read mode) and has
a static power down feature that significantly reduces
power dissipation.

+ 15V Programming Power Supply:
Easy On-Board Programming

The 84532 is pin compatible with AMI's 32K ROM, the
868332. Thus for volume production, the user can
switch to lower cost ROM.
The 84532 requires a + 15V supply for programming
but all the programming signals are TTL compatible.
This considerably eases on-board programming.

Block Diagram

Logic Symbol

Pin Configuration

.A D
PD/PGM

A,
A2

ADDRESS

DECODER

DRIVER

32,768 BIT
AD
A,

As
A6

O2
0,

A,
A,
As

ADDRESS

DECODER

A'D

DRIVER

Vcc GND_
Vpp_

Vee
As

"Vpp

PD/PGM

A,
A2

A'D

0,
A,

A6
A,

°5
06

A'D
POWER
DDWN&
PROGRAM
LOGIC

PD/PGM

A,
A6

GND

0, 02 0, 0, 0 5 0 6 0, Os

Truth Table
---,----r--

Mode
- - - - - - ~GM
Read
VII.

Pin Names
Ao - Au
0, - 08
PD/PGM

Address Inputs

vee

+5V Power Supply

Data Outputs
Power Down Program

VPP

+ 15V Power Supply

Vpp

Outputs

+ 5V

Data Out

+5V

High Z

Program

Pulsed VII! to
VII. to VlIl

+5V

+15V

Data In

Program
Inhibit

VIH

+5V

+15V

High Z

Power Down
----

2.47

Vee
+5V

ADVANCED PRODUCT DESCRIPTION

84716
16,384 BIT (2048 X 8)
UV ERASABLE VMOS EPROM
Features

General Description

Single + 5 Volt Power Supply

Fast Access Time: 2500s Maximum

Pin Compatible with AMI's 16K, 32K and
64K ROMs

Low Power Dissipation
525mA Maximum Active Power
132mW Maximum Standby Power

The 84716 is a 16,384 bit ultraviolet light erasable, electrically programmable read-only memory (EPROM)
organized as 2048 words by 8 bits. It is fabricated using
AMI's proprietary N-Channel VM08 technology. The
device is fully static requiring no clocks for operation.
All the inputs and outputs are fully TTL compatible dur.ing both the read and program modes. The 84716
operates from a single + 5V power supply and has a
static power down feature that significantly reduces
power dissipation.

Fully TTL Compatible During Read and
Program

o + 15V Programming Power Supply: Easy OnBoard Programming
Block Diagram

The 84716 is fully pin compatible with the 84216B and
86831B 16K ROMs, the 868332 32K ROM and the 84264
64K ROM. Thus for volume production, the user can
switch to a lower cost ROM.
The 84716 requires a + 15V supply for programming
but all the programming signals are TTL. This considerably eases on-board programming.
Logic Symbol
CS

Pin Configuration
PO/PGM

AS
AS
AlO

POiPGM

GNO--

Truth Table

V pp - - . .

MODE
Read
Deselect

Pin Names

Power
Down

Ao - AlO Addresses

PD/PGM

Power Down Program

00 - 07 Data Outputs

Chip Select

?rogram
Program
Verify
Program
Inhibit

2.48

PDIPGM

Vpp

OUTPUTS

VIL

VI(,

+5V

Data Out

Don't Care

V IH

+5V

High Z

VIH

Don'teare

+5V

High Z

VIH

+5V

+ 15V

Data In

VIL

+5V

+lSV

Data Out

VIL

VIH

+5V

+15V

High Z

Pulsed
VH to VIH to VIL

Vee

S5204A
512 x 8 BIT ERASABLE AND
ELECTRICALLY REPROGRAMMABLE
READ ONLY MEMORY
Features

General Description

o
o
o

The S5204A is a high speed, static, 512x8 bit, erasable and electrically programmable read only memory
designed for use in bus-organized systems. Both input
and output are TTL compatible during both read and
write modes. Packaged in a 24-pin hermetically sealed
dual i?-linhe pahc.katge, theltbit ?altttel~hctan be ertahsed b y
exposmg t e c Ip 0 an u ravlO e Ig source rough
the transparent lid, after which a new pattern can be
written.

o
o

o
o
o
o
o

On-Board Programmability
Fast Access Time - 750ns Max.
High Speed Programming - Less than 1 Minute
for all 4096 Bits
Programmed with R/W, CS and VPROG Pins
Completely TTL Compatible - Excluding the
VpROG Pin during Read or Write
Ultraviolet Light Erasable - Less than
10 Minutes
Static Operation - No Clocks Required
Three-State Data I/O
Standard Power Supplies - +5V and -12V
Mature P -Channel Process

Block Diagram

Pin Configuration

Al
A2
A3

64x64 BIT
PROM ARRAY

A4
A5
A6
A7

Y ·GATING

(;So
RWORCSI

SENSE AMPLIFIERS
3·STATE
INPUT/OUTPUT
BUFFERS

VPROG-+-----'

Typical Applications
0001020304050607

o
o
o
o
o
o
o
o

77675

2.49

ROM Program De bugging
Code Translation
Microprogramming
Look-up Tables
Random Logic Replacement
Programmable Waveforms
Character Generation
Electronic Keyboards

I
_:

S5204A

ABSOLUTE MAXIMUM RATINGS
+0.3 to -20V
+0.3 to -60V
O°C to +70°C
-55°C to +85°C
-55°C to 150°C

Voltage on any pin relative to VSS except the VPROG pin
Voltage on the VPROG pin relative to VSS
Operating Temperature
.....
Storage Temperature (programmed)
Storage Temperature (unprogrammed)

NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields, however,
it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to
this high-impedance circuit.

DC (STATIC) CHARACTERISTICS (VCC = +5.OV ± 5%, VGG = -I2.0V ± 5% T A = 0 -70 C unless otherwise noted).
SYMBOL

MIN

CHARACTERISTIC

VIL

INPUT VOLTAGE LOW

VIH

INPUT VOLTAGE HIGH

VOL

OUTPUT VOLTAGE LOW
IOL::: 1.6 rna

VOH

OUTPUT VOLTAGE HIGH

VCC -2.25

MAX

UNIT

0.8

Vcc +.3

0.4

V
V

2.4

IOH = 200J.,lA
ILl

INPUT LEAKAGE CURRENT

J..la

ILO

J..la

IGG

OUTPUT LEAKAGE CURRENT
CS = 5V
VGG SUPPLY CURRENT

rna

ICC

VCC SUPPLY CURRENT

rna

POWER DISSIPATION

750

NOTE: Program input VpROG may be tied to VCC during the Read.

AC (DYNAMIC) CHARACTERISTICS (Loading is as shown in Figure 1 unless otherwise noted).
SYMBOL

CHARACTERISTIC

MIN

MAX

UNIT

TACC

ACCESS TIME

750

TCO

CHIP SELECT TO
OUTPUT DELAY
CHIP DESELECT TO
OUTPUT DELAY

400

TDD

2.50

S5204A

FIGURE I - TEST CONDITIONS

FIGURE 2 -READ CYCLE TIMING WAVEFORMS

\~~---------------~
"IJllRfSS

---_.J1V,L

22 P

. \..----

16K

I)·\T,\

PROGRAM CHARACTERISTICS (R/W Gnd' Program pulse rise and fall time (10% to 909'(,) are both at l,us max)
MAX

UNIT

CHARACTERISTICS

MIN

TAS

ADDRESS SET UP TIME

,us

TCSS

CHIP SELECT SET UP TIME

,us

TDS

DATA SET UP TIME

,us

TAH

ADDRESS HOLD TIME

,us

TCSH

CHIP SELECT HOLD TIME

,us

TDH

DA T A HOLD TIME

TpWL

PROGRAM PULSE WIDTH
LOW
PROGRAM PULSE WIDTH
HIGH
PROGRAM AMPLITUDE

SYMBOL

TpWH
VpROG*
IpROG

,us

500
-55

PROGRAM CURRENT

-50

rna

TWS

WRITE SET UP TIME

,us

TWH

WRITE HOLD TIME

,us

TRS

READ SET UP TIME

,us

*Note that in the WRITE mode the MIN value of VpROG should not be exceeded and that chip select, address, and data lines may remain at TTL
level, as in the READ mode

2.51

S5204A

FIGURE 3 -PROGRAMMING CYCLE TIMING WAVEFORMS

~-------------------------------------------(JF(---------------------------R/W

--------------~r-DATA

tpWH

VPROG
FIRST PULSE

FIGURE 4 -READ/PROGRAM/READ CYCLE TIMING WAVEFORM

R/W

~ --~--------~-----------------------Jr-----------------~--------~~-------------------~r----------

-----

---tACC----

--------~r--------DATA

VpROG
READ
MODE

PROGI'AM MODE

2.52

READ
MODE

S5204A

INTERF ACE DESCRIPTION

Function

Label

(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)

DO
DI
D2
D3
D4
05
D6
D7

Data Lines - with the R/W line selected for Read (VILl. the Data Lines (DO through D7) are
set to reflect the contents of the selected memory location. When the R/W line is set for'
Write (VIR). the Data Lines are stored at the addressed location of the 5204A when VPROG
is present. The Data Bus output drivers are three-state devices that remain in the high impedance (off) state whenever CS is in the VIR state or when R/W is in the VIL state.

(2)

R/W

Read/Write - When this input line is set to VIH, the device is in the Write mode, a low (VId
signal puts it into the Read mode.

(3)

Chip Select - This input line must be set to VIL for a Read or Write operation to be performed. When it is High (V:H) the output data bus is set to a high-impedance three-state
condition.

(4)

(5)
(6)
(7)
(8)
(9)
(10)
(11)
(13)
(14)

VpROG

AO
Al
A2
A3
A4
A5
A6
A7
A8

Program - In the Write mode, a SOVolt programming pulse at this input causes the data at
the Data Lines to be stored in the selected address location. This pin should be tied to Vee
for normal Read operations.
Address Lines - These lines select the 8 bit word in memory for Read or Write operation.

2.53

S5204A

CONTROL FUNCTION TRUTH TABLE
OUTPUTS

R/W

VPROG

MODE

VpROG

Write

Active Data Inputs

Read

Active

Vee
X

Standby

Floating

OPERATION

of the chip select input as during read operations.
The amount of program energy required to insure
memory retention may be defined as a function of the number
of program pulses (N) times the program pulse width (tpw )
(N x tpw ;;;;. 60 msec). This means if a 3 ms pulse is used, 20
program pulses are required, and if a 5 ms pulse is used 12
program pulses are required.
The read operation is accomplished by a l-OW at the
R/W input with the program input connected to Vss potential.
True data (data out= date in) is valid after the address is stable.
The es input will disable (float) the outputs when HIGH to
allow capability with bus organized systems. ,
Erasure is accomplished by exposing the array to a 2537A
ultra-violet light source (such as Ultra-Violet Products, Inc.
Lamp Model S52 or UVS-54, Turner Designs PROM Eraser,
Model 30 or equivalent) for a period of 7 to 10 minutes. The
clear optical lid should be approximately one inch away from
the lamp tubes.

Initially, and after each erasure, all bits of the 5204A are
in the LOW state (output 0 volts). Data is stored by selectively
programming a HIGH into the desired bit locations. The R/W
inpu t (pin 2) is used to select the desired mode of operation.
When the R/W input is HIGH the chip is in the write enable
mode of operation. The outputs (DO - Ih) are disabled (floating). with the corresponding pins becoming the data inputs.
The word address is selected in the same manner as in the Read
mode. Data to be programmed is presented 8 bits in parallel
and after the address and data are set up a programming pulse
(Vp = - 50 volts) is applied. VPROG electrically writes the data
into the memory array. Writing may be inhibited by deselecting
the chip with the es input at a HIGH during the write cycle.
This feature allows true "on board" programming in bus
organized systems where the R/W and VPROG inputs are
common and the device to be programmed is selected by means

2.54

S6834
ERASABLE AND
ELECTRICALLY REPROGRAMMABLE
READ ONLY MEMORY
Features

General Description

The S6834 is a high speed, static, 512 x 8 bit, erasable
and electrically programmable read only memory designed for use in bus-organized systems. Both input
and output are TTL compatible during both read and
write modes. Packaged in a 24 pin hermetically sealed
dual in-line package the bit pattern can be erased by
exposing the chip to an ultra-violet light source through
the transparent lid, after which a new pattern can be
written.

o
o
o
o
o
o
o
o
o
o

On-Board Programmability
Fast Access Time - 57 5ns Typ.
Pin Configuration Similar to the S6830 lK x
8 Bit ROM
High Speed Programming - Less than 1 Minute
for All 4096 Bits
Programttled with R/W, CS and VPROG Pins
Completely TTL Compatible - Excluding the
VPROG Pin
Ultraviolet Light Erasable - Less than
10 Minutes
Static Operation - No Clocks Required
Three-State Data I/O
Standard Power Supplies +5V and -12V
Mature P-Channel Process
Block Diagram

Pin Configuration

GNO

AO
Al
A2
A3

64,64 BIT
PROM ARRAY

A4
A5
AS
A7

GSO

VGG

Y·GATING

RW OR CSI

SENSE AMPLIFIERS
3·STATE
INPUT/OUTPUT
BUFFERS

VPROG

R/W

Vee

0001020304050607

Typical Applications

VPROG

o
o

o
o
o
o
o
o
2.55

ROM Program Debugging
Code Translation
Microprogramming
Look-up Tables
Random Logic Replacement
Programmable Waveforms
Character Generation
Electronic Keyboards

I
:

86834

ABSOLUTE MAXIMUM RATINGS
+0.3 to -20V
+0.3 to -60V
O°C to +70°C
-55°C to +85°C
-55°C to 150°C

Voltage on any pin relative to VSS except the VpROG pin
Voltage on the VPROG pin relative to VSS
. . . . .
Operating Temperature
Storage Temperature (programmed)
Storage Temperature (unprogrammed)

DC (STATIC) CHARACTERISTICS (VCC = +5.0V
SYMBOL

± 5%, VGG = -12.0V ± 5% TA = 0 -70 u C unless otherwise noted).
MAX
0.8

VCC -2.25

VCC +.3

0.4

INPUT VOLTAGE LOW

VIL

UNIT

MIN

CHARACTERISTIC

VIH

INPUT VOLTAGE HIGH

VOL

OUTPUT VOLTAGE LOW
IOL::: 1.6 rna

VOH

OUTPUT VOLTAGE HIGH
IOH = 200,uA

ILl

INPUT LEAKAGE CURRENT

ILO

OUTPUT LEAKAGE CURRENT
CS= 5V
V GG SUPPLY CURRENT

rna

ICC

V CC SUPPLY CURRENT

rna

POWER DISSIPATION

750

IGG

2.4

NOTE: Program input VpROG may be tied to VCC during the Read.

AC (DYNAMIC) CHARACTERISTICS (Loading is as shown in Figure 1 unless otherwise noted).
SYMBOL

MIN

CHARACTERISTIC

(6834)

MAX
(6834-1)

UNIT

TACC

ACCESS TIME

575

750

TCO

CHIP SELECT TO
OUTPUT DELAY
CHIP DESELECT TO
OUTPUT DELAY

300

400

250

325

TDD

2.56

56834

FIGURE I-TEST CONDITIONS

FIGURE 2 - READ CYCLE TIMING WAVEFORMS

>f~----------------X

+5V'5%

1.8K

ADDRESS - - - - - '

\..- __ _

I-I

TYPE 1

co -

INPVT

_ V,L

cs
THREE STATE
(HIGH 21

22PFI

VOH

(HI Z(

!_I,tCC-

DATA

PROGRAM CHARACTERISTICS (RjW Gnd' Program pulse rise and fall time (10% to 90%) are both at 1}JS max}.
CHARACTERISTICS

MIN

TAS

ADDRESS SET UP TIME

J..IS

TCSS

CHIP SELECT SET UP TIME

J..IS

TDS

DATA SET UP TIME

J..IS

TAH

ADDRESS HOLD TIME

J..IS

TCSH

CHIP SELECT HOLD TIME

J..IS

TDH

DAT A HOLD TIME

TpWL

VpROG*

PROGRAM PULSE WIDTH
LOW
PROGRAM PULSE WIDTH
HIGH
PROGRAM AMPLITUDE

IpROG

PROGRAM CURRENT

TWS

WRITE SET UP TIME

J..IS

TWH

WRITE ijOLD TIME

J..IS

TRS

READ SET UP TIME

J..IS

SYMBOL

TpWH

MAX

J..IS

500
-55

UNIT

ms
J..IS

-50
35

V
rna

*Note that in the WRITE mode the MIN value of VpROG should not be exceeded and that chip select, address, and data lines may remain at TTL
level, as in the READ mode

2.57

S6834

FIGURE 3 -PROGRAMMING CYCLE TIMING WAVEFORMS

________________________________________~~FC__________________________

R'W

--------------~~-DATA

VpROG

VPROG

_ _ tpWL

i"----------.Ji
FIRST PULSE

FIGURE 4 -READ/PROGRAM/READ CYCLE TIMING WAVEFORM

~ --~--------~------------------------1~------------------~--------~-+-------------------~~---------

-------tACC~

--------~r--------DATA

VpROG
READ
MODE

PROGRAM MODE

2.58

READ
MODE

56834

INTERFACE DESCRIPTION

Function

Label

(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

DO
DI
D2
D3
D4
D5
D6
D7

(14)

R/W

Read/Write - When this input line is set to VIH, the device is in the Read mode, a low (VIL)
signal puts it into the Write mode.

(15)

Chip Select - This input line must be set to VIL for a Read or Write operation to be performed. When it is HIGH (VIH) the output data bus is set to a high-impedance three-state
condition and disables the Write operation.

(11)

(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)

VpROG

AO
Al
A2
A3
A4
A5
A6
A7
A8

Data Lines - with the R/W line selected for Read (Vrd, the Data Lines (DO through D7)
are set to reflect the contents of the selected memory location. When the R/W line is set
for Write (VIH), the Data Lines are stored at the addressed location of the 5204A when
VPROG is present. The Data Bus output drivers are three-state devices that remain in the
high impedance (off) state whenever es is in the VIH state or when R/W is in the V1L
state.

Program - In the Write mode, a -50V programming pulse at this input causes the data at
the Data Lines to be stored in the selected address location. This pin should be tied to Vee
for normal Read operations.
Address Lines - These lines select the 8 bit word in memory for Read or Write operation.

2.59

56834

CONTROL FUNCTION TRUTH TABLE
CS

R/W

VpROG

MODE

VpROG

Write

Vee
X

OUTPUTS
Active Data Inputs

Read

Active

Standby

Floating

OPERATION
Initially, and after each erasure, all bits of the 6834 are
in the LOW state (output 0 volts) Data is stored by selectively
programming a HIGH into the desired bit locations. The R/W
input pin 14 is used to select the desired mode of operation.
When the R/W input is LOW, the chip is in the write enable
mode of operation. The outputs (01 - 08) are disabled (floating) with the corresponding pins becoming the data inputs
(01 ~ DIN 1 etc.). The word address is selected in the same
manner as in the read mode. Data to be programmed is presented 8 bits in parallel and after the address and data are set
up a programming pulse (Vp = - 50 volts) is applied. VPROG
writes the data into the memory array. Writing may be inhibited
by deselecting the chip with-the es input at ~ LOW during the
write cycle. This feature allows true "on board" programming
in bus organized systems where the R/W and VPROG inputs
are common and the device to be programmed is selected by

means of the chip select input as during read operations.
The amount of program energy required to insure
memory retention may be defined as a function of the number
of program pulses (N) times the program pulse width (t pw)
(N x tpw ~ 60 msec). This means if a 3 ms pulse is used, 20
program pulses are required, and if a 5 ms pulse is used 12
program pulses are required.
The read operation is accomplished by a HIGH at the
R/W input with the program input connected to VSS potential.
True data (data out = data in) is valid after the address is stable.
The es input will disable (float) with the outputs when HIGH
to allow capability with bus organized systems.
Erasure is accomplished by exposing the array to a high
intensity ultra-violet light source (such as, Ultra-Violet
Products, Inc. Lamp Model S52 or UVS-54) for a period of 7
to 10 minutes. The clear optical lid should be approximately
one inch away from the lamp tubes.

2.60

3
S6800 Family

Selection Guide

THE AMI 56800 MICROCOMPUTER SYSTEMS FAMILY
PART NO.
S6800
S68AOO

DESCRIPTION
8-Bit Microprocessor (1.0MHz Clock Rate)
8-Bit Microprocessor (1.5MHz Clock Rate)

+5V
+5V

INPUT/OUTPUT
TTL
TTL

PACKAGES
40 Pin
40 Pin

S68BOO

8-Bit Microprocessor (2.0MHz Clock Rate)
8-Bit Microcomputer

+5V

TTL

40 Pin

S6801

+5V

TTL

TBA

S6802

1024 Bit (128x8) Microprocessor

TTL

S6809
S6810A
S6180A-1
S68A10

POWER SUPPLIES

High Performance Monolithic Microprocessor

+5V

TTL

40 Pin
TBA

1024 Bit (128x8) Static Read/Write Memory
(450ns Access Time)

+5V

DTL/TTL

24 Pin
40 Pin

1024 Bit (128x8) Static Read/Write Memory
(350ns Access Time)
1024 Bit (128x8) Static Read/Write Memory

+5V

TTL/CMOS

24 Pin

(360ns Access Time)

+5V

TTL/CMOS

24 Pin

S68B10

1024 Bit (128x8) Static Read/Write Memory
(250ns Access Time)

+5V

S6820

Peripheral Interface Adapter (PIA)

+5V

TTL
TTL

24 Pin
40 Pin

S6821
S68A21

Peripheral Interface Adapter (PIA)
Peripheral Interface Adapter (PIA)

+5V
+5V

TTL
TTL/CMOS

40 Pin

S68B21
S6831A

Peripheral Interface Adapter (PIA)
16,384 Bit (2048x8) ROM

+5V
+5V

TTL/CMOS

S6831B

16,384 Bit (2048x8) ROM

S6834

4096 Bit (512x8) EPROM

S6840
S6846

Programmable Timer
NMOS Combination ROM, I/O, Timer

S6850
S68A50
S68B50
S6852

40 Pin
40 Pin

+5V
+5V, -12V

TTL
TTL
Three-State

+5V

TTL

28 Pin

Asynchronous Communication Interface Adapter
Asynchronous Communication Interface Adapter

+5V
+5V
+5V

TTL
TTL
TTL

40 Pin
24 Pin
24 Pin

Asynchronous Communication Interface Adapter
Synchronous Serial Data Adapter (SSDA)

+5V
+5V

TTL
TTL

24 Pin
24 Pin

S6854

Advanced Data Link Controller

+5V

TTL

24 Pin

S68A54

Advanced Data Link Controller

+5V

TTL

24 Pin

S68047
S68488

Video Display Generator
General Purpose Interface Adapter (GPIA)

+5V
+5V

TTL
TTL

40 Pin
40 Pin

3.2

24 Pin
24 Pin
24 Pin

S6800/S68AOO/S68 BOO
8-BIT
MICROPROCESSOR

VCC
GNO
GNO

181
(1)

.--_-+,,136:,::1 OBE

1211
ACCUM A

1331 DO
(32)
01
(31) 02
(30)
03
1291
04
(28) 05

ACCUM B
STACK PTR HR

STACK PTR LR

INDEX HR

INDEX LR

1271 06
RESET

fRO
NMI

1401

1261 07

141
161
131

",2
""

HALT

1.3...7.~JI'~_ _ _ _ _~

121

(5)

171
R/W

GND
HALT

IRQ

VMA
NMI
BA
Vee

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All

10
11
12
13
14
15
16
17
18
19
20

86800
868AOO
868800

RESET

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TSC
~2
DBE

R/W
DO
Dl
D2
D3
D4
D5
D6
D7
A15
A14
A13
A12
GND

1341

1391
TSC

A15 A14 A13 A12 All Al0 A9 A8

BLOCK DIAGRAM

PIN CONFIGURATION

FEATURES

•
•
•
•
•

•
•
•
•

•
•

Eight-Bit Parallel ProcessiI1g
Bi-Directional Data Bus
Sixteen-Bit Address Bus - 65536 Bytes
of Addressing
72 Instructions - Variable Length
Seven Addressing Modes - Direct, Relative,
Immediate, Indexed, Extended, Implied and
Accumulator
Variable Length Stack
Vectored Restart
2 Microsecond Instruction Execution
Maskable Interrupt Vector

•
•

3.3

Separate Non-Maskable Interrupt - Internal
Registers Saved in Stack
Six Internal Registers - Two Accumulators,
Index Register, Program Counter, Stack Pointer
and Condition Code Register
Direct Memory Access (DMA) and Multiple
Processor Capability
Clock Rates - S6800 -1 .0 MHz
S68AOO - 1.5 MHz
S68BOO - 2.0 MHz
Simple Bus Interface Without TTL
Halt and Single Instruction Execution Capability

S6800/S68AOO/S68 BOO
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC
Input Voltage VIN

O°C to + 70°C
Operating Temperature Range TA
-40°C to +8S o C
Industrial Temperature Range
-55°C to +12S o C
Military Temperature Range
Storage Temperature Range Tstg - 55°C to + 150°C

- OJ to + 7.0V

ELECTRICAL CHARACTERISTICS
(VCC = S.OV, ± 5%, VSS = 0, TA unless otherwise noted.)
SYMBOL

CHARACTERISTICS

VIH
VIHC

Input High Voltage (Normal Operating Levels)

VIL
VILC
lIN

Input Low Voltage (Normal Operating Levels)

ITSI
VOH

VOL

Po
CIN

COUT
f

tCYC
PWH
tUT
tr, tf
td

Input Leakage Current
(VIN = 0 to S.2SV, VCC = Max)
(VIN = 0 to S.2SV, VCC =O.OV)
Three-State (Off State) Input Current
VIN = 004 to 2AV, VCC = Max
Output High Voltage
(ILOAD = - 20SMAdc, VCC = Min)
(ILOAD = - 14SMAdc, VCC = Min)
(ILOAD = - 100MAdc, VCC = Min)
Output Low Voltage
(ILOAD = 1.6mAdc, VCC = Min)
Power Dissipation
Capacitance tf
(VIN =0, TA = 25°C, f = 1.0 MHz)

Frequency of Operation
Clock Timing (Figure 1)
Cycle Time
Clock Pulse Width
Measured at VCC - 0.6V
Total 1 and 2 Up Time

Logic
1, 2
Logic
1, 2

MIN

TYP

MAX

UNIT

VSS + 2.0
VCC - 0.6

Vdc

VSS - OJ
Vss - 0.3

VCC
VCC + 0.3
VSS + 0.8
Vss + 0.4

1.0

2.0
-

2.5
100
10
100

VSS + 204

VSS + 204
VSS +204

VSS + 0.4

0.5

1.0

Vdc
MAdc

Logic*
1, 2
DO-D7
AO - A1S, R/W

MAdc
Vdc

DO-D7
AO - A1S,
R/W, VMA
BA

Vdc
W
pF

1
2
DO-D7
Logic Inputs
AO - A1S, R/W, VMA
S68AOO
S68BOO
S68AOO
S68BOO
1, 2 - S68AOO
1, 2 - S68BOO
S68AOO
S68BOO

Rise and Fall Times
Measured between VSS + 0.4 and VCC - 0.6
Delay Time or Clock separation
Measured at VOV = VSS + 0.6V

6.5

0.1
0.1
0.666
0.50
230
180

1.5
2.0
10
10
9500
9500

pF
MHz

MS
ns
ns

600
440
5.0

100

9100

*Except IRQ and NMI, which require Knpullup load resistor for wire-OR capability at optimum operation.
#Capacitances are periodically sampled rather than 100% tested.

3.4

35
70
12.5
10
12

S6800/S68AOO/S68 BOO
READ/WRITE TIMING
86800
8ymbol
tAD

Parameter
Address Delay

Min.
C = 90pF
C = 30pF

t ACC

868AOO
Typ.

Max.

Min.

868800
Typ.

Max.

Typ.

Max.

100

300

180
165

150
135

575

360

250

Peripheral Read Access Time
tAC = tUT - (tAD + t DSR )

Min.

Units
ns

ns
ns

t DSR

Data Setup Time (Read)

100

Input Data Hold Time

Output Data Hold Time

tAH

Address Hold Time
(Address, R/W, VMA)

tEH

Enable High Time for
DBE Input

tDDW

Data Delay Time (Write)

tpcs

Processor Controls
Processor Control
Setup Time

470

220

280
165

200

160

200

t pcr ; t pcr

Processor Control
Rise and Fall Time

100

tBA
t TSE

Bus Available Delay

270

Three-State Enable

t TSD

Three-State Delay

270

tDBE

Data Bus Enable Down
Time During ¢1 Up Time

tDBEr'

Data Bus Enable

tDBEr

Rise and Fall Times

150
25

Measurement point for ¢1 and 1>2 are shown below.
Other measurements are the same as for MC6800.

1-----------'CyC ---l

/StartofCYCle

FIGURE 1 CLOCK TIMING WAVEFORM

FIGURE 2
877235

3.5

READ/WRITE TIMING WAVEFORM

S6800/S68AOO/S68 BOO

, . - - START CYCLE

teye
Ql ______________

' -_ _ _ _ _ _ _ _ _

O.3V

_ - - - - - - - - - - - - _ V CC ·O.3V
O.3V

1-_.......:c::.......,......1---------------------,.,.~~

R/W

2AV

ADDRESS-------?7:ii~~~_==__:::::;o...J.~---------------_t~~
FROM MPU _ _ _ _ _ _ _~~~~~~~~__-----------------~~~~
VMA

DATA FROM _ _ _ _ _ _ _ _ _ _
MEMORY OR
PERIPHERALS

~_ _ _ _ _ _....:_ _ _ _ _---;~2.~OV~~~:~~1~
0.8 V

677110

FIGURE 3

DATA NOT VALID

READ DATA FROM MEMORY OR PERIPHERALS

START CYCLE

¢1--------------t
92

OAV

R/W
ADDRESS

OAV

---------~~~_~-J-.-------+---------------~;;;;:::_

2AV

FROM MPU ____________~~~~~~~=------+_---------~~=- OAV

....j':~2:~;:;;~------_+------------+.....:::s~

VMA

-----------~~~~
DATA FROM
MPU
DBE

=92

-------------+--------------1~*~~t~~~~~~=
--------__.

677221

FIGURE 4

DATA NOT VALID

WRITE DATA IN MEMORY OR PERIPHERALS

3.6

2AV

S6800/S68AOO/S68 BOO

INTERF ACE DESCRIPTION
Label

¢!

Function

(3)
(37)

Clocks Phase One and Phase Two - Two pins are used for a two-phase non-overlapping
dock that runs at the VCC voltage l~vel.

RESET

(40)

Reset - This input is used to reset and start the MPU from a power down condition, resulting from a power failure or an initial start-up of the processor. If a positive edge is detected
on the input, this will signal the MPU to begin the restart sequence. This will start execution
of a routine to initialize the processor from its reset condition. All the higher order address
lines will be forced high. For the restart, the last two (FFFE, FFFF) locations in memory
will be used to load the program that is addressed by the program counter. During the restart routine, the interrupt mask bit is set and must be reset before the MPU can be interrupted by IRQ.
Reset must be held low for at least eight clock periods after VCC reaches 4.75 volts
(Figure 4). If Reset goes high prior to the leading edge of ~2, on the nex t ¢1 the first restart
memory vector address (FFFE) will appear on the address lines. This location should contain
the higher order eight bits to be stored into the program counter. Following, the next
address FFFF should contain the lower order eight bits to be stored into the program counter.

FIGURE 5
INITIALIZATION OF MPU AFTER RESTART

Reset

~----- ?- 8 Clock Times

II
II

-------ooll

- - I t--

First Instruction Loaded into MPU

VMA

(/,22227222««//// //2Z2ZZ2Z222//2//22222~"I . . .
Address Out
= FFFE

I..

Li
Address Out = Contents of
FFFE + FFFF

Address Out
= FFFF

VMA

(5)

Valid Memory Address - This output indicates to peripheral devices that there is a valjd
address on the address bus. In normal operation, this signal should be utilized for enabling
peripheral interfaces such as the PIA and ACIA. This signal is not three-state. One standard
TTL load ,and 30 pF may be directly driven by this active hjgh signal.

3.7

S6800/S68AOO/S68BOO

Label

(9)

•
•
•

Function
Address Bus - Sixteen pins are used for the address bus. The outputs are three-state bus
drivers capable of driving one standard TTL load and 130 pF. When the output is turned
off, it is essentially an open circuit. This permits the MPU to be used in DMA applications.

A15

(25)

TSC

(39)

Three-State Control - This input causes all of the address lines and the Read/Wdte line to
go into the off or high impedance state. This state will occur 500 ns after TSC = 2.4 V.
The Valid Memory Address and Bus Available signals will be forced low. The data bus is not
affected by TSC and has its own enable (Data Bus Enable). In DMA applications, the ThreeState Control line should be brought high on the leading edge of the Phase One Clock. The
<1>1 clock must be held in the high state and the <1>2 in the low state for this function to
operate properly. The address bus will then be available for other devices to directly address
memory. Since the MPU is a dynamic device, it can be held in this state for only 5.0 IlS or
destruction of data will occur in the MPU.

(33)

Data Bus - Eight pins are used for the data bus. It is bi-directional, transferring data to and
from the memory and peripheral devices. It also has three-state output buffers capable of
driving one standard TTL load at 130 pF.

•

(26)

DBE

(36)

Data Bus Enable - This input is the three-state control signal for the MPU data bus and will
enable the bus drivers when in the high state. This input is TTL compatible; however in
normal operation, it can be driven by the phase two clock. During an MPU read cycle, the
data bus drivers will be disabled internally. When it is desired that another device control
the data bus such as in Direct Memory Access (DMA) applications, DBE should be held low.

R/W

(34)

Read/Write - This TTL compatible output signals the peripherals and memory devices
whether the MPU is in a Read (high) or Write (low) state. The normal standby state of this
signal is Read (high). Three-State Control going high will turn Read/Write to the off (highimpedance) state. Also, when the processor is halted, it will be in the off state. This output
is capable of driving one standard TTL load and 130 pF.

(2).

Halt - When this input is in the low state, all activity in the machine will be halted. This
input is level sensitive. In the halt mode, the machine will stop at the end of an instruction,
Bus Available will be at a one level, Valid Memory Address will be at a zero, and all other
three-state lines will be in the three-state mode.
Transition of the Halt line must not occur during the last 250 ns of phase one. To insure
single instruction operation, the Halt line must go high for one Phase One Clock cycle.

(7)

Bus Available - The Bus Available signal will normally be in the low state; when activated, it
will go to the high state indicating that the microprocessor has stopped and that. the address
bus is available. This will occur if the Halt line is in the low state or the processor is in the
WAIT state as a result of the execution of aWAIT instruction. At such time, all three-state
output drivers will go to their off state and other outputs to their normally inactive level.
The processor is removed from the WAIT state by the occurrence of a maskable (mask bit
I = O)or nonmaskable interrupt. This output is capable of driving one standard TTL load
and 30 pF.

3.8

S6800/S68AOO/S68 BOO

Label

Function

IRQ

(4)

Interrupt Request - This level sensitive input requests that an interrupt sequence be generated within the machine. The processor will wait until it completes the current instruction
that is being executed before it recognizes the request. At that time, if the interrupt mask
bit in the Condition Code Register is not set. the machine will begin an interrupt sequence.
The Index Register, Program Counter, Accumulators, and Condition Code Register are
stored away on the stack. Next the MPU will respond to the interrupt request by setting the
interrupt mask bit high so that no further interrupts may occur. At the end of the cycle,
a l6-bit address will be loaded that points to a vectoring address which is located in memory
locations FFF8 and FFF9. An address loaded at these locations causes the MPU to branch
to an interrupt routine in memory.
The Halt line must be in the high state for interrupts to be recognized_
The fRQ has a high impedance pullup device internal to the chip; however a 3 kD external
resistor to VCC should be used for wire-OR and optimum control of interrupts.

(6)

Non-Maskable Interrupt - A low-going edge on this input requests that a non-mask interrupt
sequence be generated within the processor. As with the Interrupt Request signal, the
processor will complete the current instruction that is being executed before it recognizes
the NMI signal. The interrupt mask bit in the Condition Code Register has no effect on NMI.
The Index Register, Program Counter, Accumulators, and Condition Code Register are
stored away in the stack. At the end of the cycle, a 16-bit address will be loaded that
points to a vectoring address which is located in memory locations FFFC and FFFD. An
address loaded at these locations causes the MPU to branch to a non-maskable interrupt
routine in memory.
NMI has a high impedance pullup resistor internal to the chip; however a 3 kD external
resistor to Vcc should be used for wire-OR and optimum control of interrupts_
Inputs IRQ and NMI are hardware interrupt lines that are acknowledged during ¢2 and will
start the interrupt routine on the ¢l following the completion of an instruction.

3.9

56800/568AOO/568BOO

INTERRUPTS - As outlined in the interface description the S6800 requires a 16-bit vector
address to indicate the location of routines for Restart, Non-maskable Interrupt, and Maskable Interrupt. Additionally an address is required for the Software Interrupt Instruction
(SWI). The processor assumes the uppermost eight memory locations, FFF8 - FFFF, are
assigned as interrupt vector addresses as defined in Figure 6.
After completing the current instruction execution the processor checks for an allowable interrupt request via the IRQor NMI inputs as shown by the simplified flow chart in
Figure 7. Recognition of either external interrupt request or a Wait for Interrupt (W AI) or
Software Interrupt (SWI) instruction causes the contents of the Index Register, Program
Counter, Accumulators and Condition Code Register to be tranferred to the stack as shown
in Figure 8.

FIGURE 6

MEMORY MAP FOR INTERRUPT VECTORS
Vector

Description

FFFE

FFFF

Restart

FFFC

FFFD

Non-maskable Interrupt

FFFA

FFFB

Software Interrupt

FFF8

FFF9

Interrupt Request

3_10

S6800/S68AOO/S68 BOO

FIGURE 7

MPU FLOW CHART

FIGURE 8

SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK

SP '=
CC '=
ACCB'=
ACCA '=
IXH'=
IXl '=
PCH '=
PCl '=

Stack Pointer
Condition Codes (Also called the Processor Status Byte)
Accumulator B
Accumulator A
Index Register, Higher Order 8 Bits
Index Register, lower Order 8 Bits
Program Counter, Higher Order 8 Bits
Program Counter, lower Order 8 Bits

m-9
m-8
m-7
cc

m-6
m-5
m-4
m-3
m-2

m-2

m-1

ACCB
ACCA
IXH
IXl

m -1
m

m+1

- - - SP
-

PCH
pel

m+ 1
m+ 2

m+ 2

BEFORE

3.11

I
AFTER

S6800/S68AOO/S68BOO

MPU REGISTERS

FIGURE 9

PROGRAMMING MODEL OF THE
MICROPROCESSOR

The MPU has three l6-bit registers and three 8-bit registers available for use by the programmer.
Program Counter - The program counter is a two byte (16bits) register that points to the current program address.
Stack Pointer - The stack pointer is a two byte register that
contains the address of the next available location in an external push-down/pop-up stack. This stack is normally a
random access Read/Write memory that may have any location (address) that is convenient. In those applications that
require storage of information in the stack when power is lost,
the stack must be non-volatile.
Index Register - The index register is a two byte register
that is used to store data or a sixteen bit memory address for
the Indexed mode of memory addressing.

ACCUMULATOR A

L-------------~o

PROGRAM COUNTER

~r---------------~l

STACK POINTER

~---------------~o
CONOITION CODES

Accumulators - The MPU contains two 8-bit accumulators
that are used to hold operands and results from the arithmetic
logic unit (ALU).

L.-L-lL..,-Ji-.,-Ii-.,-I......-&......-&~ REGISTER
CARRY (FROM BIT 71
OVERFLOW

Condition Code Register - The condition code register indicates the results of an Arithmetic Logic Unit operation:
Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C),
and half carry from bit 3 (H). These bits of the Condition
Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit (I).
The unused bits of the Condition Code Register (b6 and b7)
are ones.

ZERO
' - - - - - NEGATIVE
' - - - - - - INTERRUPT MASK BIT
' - - - - - - - - HALF CARRY (FROM BIT 3)

3_12

S6800/S68AOO/S68 BOO

MPU ADDRESSING MODES

DIRECT ADDRESSING

The S6800 eight-bit microprocessing unit has seven
address modes that can be used by a programmer, with the
addressing mode a function of both the type of instruction
and the coding within the instruction. A summary of the
addressing modes for a particular instruction can be found
in Figure 9 along with the associated instruction execution
time that is given in machine cycles. With a clock frequency
of I MHz, these times would be microseconds.

ADDRESS
0-255
Two byte instructions with the address of the operand
contained in the second byte of the instruction. This format
allows direct addressing of operands within the first 256
memory locations.

EXTENDED ADDRESSING
OPCODE

ACCUMULA TOR ADDRESSING (ACCX)

OPCODE

A single byte instruction addressing operands only in
accumulator A or accumulator B.

IMPLIED ADDRESSING

OPCODE

ADDRESS
HIGHER

ADDRESS
LOWER

Three byte instructions with the higher eight bits of the
operand address contained in the second byte and the lower
eight bits of address contained in the third byte of the instruction. This format allows direct addressing of all 65,536
memory locations.

INDEXED ADDRESSING

INDEX
ADDRESS

Single byte instruction where the operand address is implied by the instruction definition (i.e., Stack Pointer, Index
Register or Condition Register).

IMMEDIA TE ADDRESSING

Two byte instructions where the 8 bit unsigned address
contained in the second byte of the instruction is added to
the sixteen bit Index Register resulting in a sixteen bit
effective address. The effective address is stored in a temporary
register and the contents of the Index Register are· unchanged.

RELA TIVE ADDRESSING
HIGHER

OPERAND

RELATIVE
ADDRESS

OPERAND
LOWER

Two or three byte instructions with an eight or sixteen
bit operand respectively. For accumulator operations the eight
bit operand is contained in the second byte of a two byte
instruction. For Index Register operations (e.g. LDX) sixteen
bit operand is contained in the second and third byte of a three
byte instruction.

Two byte instructions where the relative address contained in the second byte of the instruction is added to the
sixteen bit program counter plus two. The relative address is
interpreted as a two's complement number allowing relative
addressing wi thin a range of -126 to +129 bytes of the present
instruction.

Q 1 Q

S6800/S68AOO/S68 BOO
FIGURE 10 S6800 INSTRUCTION SET
Condition Reg

Addressing Mode

Instruction
Load accumulator
Load stack pointer
Load index
register
Store accumulator
Store stack
pointer
Store index
register
Transfer accumulators
Transfer Ace. to
condo reg.
Transfer condo reg.
to Ace.
Transfer stck ptr to
index
Transfer index to
stck ptr
Pull data

Push data

Add accumulators
Add
Add with carry
Subtract
accumulators
Subtract
Subtract with
carry
Increment

Increment stack
pointer
Increment index
reg.
Decrement

Decrement stack
pointer
Decrement index
register
Complement (I's)

Complement (2's)

Decimal adjust
accumulator

Implied

Immediate

Direct

Extended

Indexed

Relative

Boolean/ Arith

51 4 13 121 1 10

OP MC PB

OP Me PB

Operation

HI'INIZI''jC

LOAA
(DAB
LOS

H6
('6
XE

2
2
.1

96 .1
06 .1
9E 4

2
2
2

B6
Fb

4
4

1
.1

A6 5
E6 5
AE (,

LOX

DE 4

EE 6

STAA
STAB
STS

97
D7
9F

4
4
5

2
2

B7 5
F7 5
BF 6

3
.1
3

A7 6
107 6
AF 7

2
2
2

STX

DF 5

FF 6

EF 7

Mnemonic

2
2

~I- A
M-B
M - SPIl. (~1 + 1)
-SPL
M - XH.(M + 1)
-XL
A-M
B-M
SPH - M. SPL (M + I)
XH - M. XI.(M + I)

TAB
TBA

16
17

2
2

I
I

A .... B
B .... A

TAP

A .... CrR

• • I I R·
• • ! I R.
•
•
l) ! R·
• •

! R.

• • ! I R·
• • ! ! R·
• •

t R·

•

t R•

•

• • I I R.
• • ! I R·

NOlc 12

TPA

CCR .... A

TSX

SP + I .... X

TXS
PULA

35
32

4
4

I
I

X ~ I .... SP
SP+ I .... SP.MSP
.... A
SP + I .... SP.
MSP .... B
A - MSp. SP I
.... SP
B- MSp. SP I
.... SP

·.·.·.
·.·.·.
··..··..··..
·.·.·.
·.·.·.
·.·.·.

PULB

PSHA

PSHB

ABA
ADDA
ADDB
ADCA
ADCB

SBA
SUBA
SUBB

SBCA
SBeB
INCA
INCB
INC

4C
5C

2
2

8B
CB
89
C9

2
2
2
2

9B
DB
99
09

3
3
3
3

2
2
2
2

BB
FB
B9
F9

4
4
4
4

3
3
3
3

AB
EB
A9
E9

5
5
5
5

2
2
2
2

A+ B-+ A
A+M .... A
B+ M .... B
A+M+C .... A
B+M+C .... B

t • t t t t
t • t t t t
t • t t t t
t • t t t t
t • t t t t

80
CO

2
2

90 3
DO 3

2
2

BO 4
FO 4

3
3

AO 5
EO 5

2
2

A-B .... A
A-M .... A
B - M .... B

• • t t t t
• • t t I I
• • t Itt

82
C2

2
2

92
02

2
2

B2
F2

3
3

A2 5
E2 5

2
2

A-M-C .... A
B-M·-C .... B
A+ 1 .... A
B+I .... B
M+ l .... M

• • I t
• • t I
I I
I I
t I

3
3

4
4

I
I
7C

INS

SP+ I .... SP

INX
DECA
DECB
DEC

08 4
4A 2
SA 2

I
I
I

X+ I .... X
A-I .... A
B-I .... B
M-I->M

DES

SP- l .... SP

DEX
COMA
COMB
COM
NEG A
NEGB
NEG

09
43
53

4
2
2

I
I
I

40
50

I
I

X-I->X
A->A
If.... B
M->M
OO-A .... A
OO.-B .... B
OO-M .... M

DAA

OP = Operation Code

7A 6

6A 7

···...
·.·.
···...
·.
·.·.
··..
··..
··..
·.

·Ie

• I ·Ie
I t 41I I 41-

t t

41-

.1-

• Ii ·Ie
I t R~
t t RS
t t RS
t t 1 2

t t I 2

t t

·.

I 2

t t t 3

MC = Number of MPU Cycles

I I
I I

5 •
5 •
5 •

PB = Number of Program Bytes

3.14

S6800/S68AOO/S68 BOO
FIGURE 10

S6800 INSTRUCTION SET (CONT'D.)
Condition Reg

Addressing Mode

Instruction

Mnemonic

Logical and

A1\[)A
N\[)1l
OKAA
OKAIl
LOKA
LORIl

Inclusive or
Exclusive or

Shift len arithmetic

Shift right
arithmetic

Shift right logical

Rotate left

Rotate right

Compare accumu·
lators
Compare
Compare index
register
Test (zero or
minus)

Bit test

Branch
Branch if carry
clear
Branch if carry
set
Branch if overflow
clear
Branch if overflow
set
Branch if equal to
zero
Branch if greater
or equal to zero
Branch if greater
than zero
Branch if less
than zero
Branch if less than
or eq ual to zero
Branch if not equal
to zero
Branch if minus
Branch if plus
Branch if higher
Branch if lower
or same

OP = Operation Code

Implied

Immediate

Direct

Extended

Indexed

Relative

Booleall/Arilh

OP MC PB

Operation

X4
C4
XA
CA
XX
CX

'14
04
'JA
OA
<)/l

B4
F4
BA
FA
B8
F/l

4
4
4
4
4
4

7/l

4X
5X

ASK A
ASRIl
ASR
LSRA
LSRIl
LSR
ROLA
ROLB
ROL
RORA
RORB
ROR

47
57

2
2

I
I

44
54

I
I

CBA
CMPA
CMPB

49
59
46
56

2
2
2
2
2

BltA
BITB

40
50

2
2

3
3
3

5
5
5
5
5
5

2
2
2

A4
E4
AA
EA
A8
E8

3
3

2
2

A~
B

0 __ = _

91
01

3
3

2
2

BI
FI

4
4

3
3

AI
EI

5
5

2
2

AC 6

70 6

4
4

3
3

A5
E5

5
5

2
2

95
D5

3
3

2
2

B5
F5

b 7 - bO

~! GJC - annm::J

b7-bO

A-B
A-M
B-M
XH

M, XL - (M+ I)

A-OO
B- 00
M -00
A·M
B.M
TEST

BRA

BCC

C=O

BCS

C= I

BVC

V=O

BVS

V= I

BEQ

Z= I

BGE

N®V=O

BGT

Z +(N 0 V) = 0

BLT

20 4

N®V= I

BLE

Z+(N0V)=1

BNE
BMI
BPL
BHI

26
2B
2A
22

4
4
4
4

2
2
2
2

Z=O
N= I
N=O
C+Z=O

BLS

C+Z=l

MC = Number of MPU Cycles

PB = Number of Program Bytes

3.15

GJ __ am;:m::J

'1'.1

I
1
85
C5

AI 0 - --= - - 0
B
b7
bO
C

1'.1

I
I

2
2

t
t
t
t t
t t
t t

~ ( c:hImm -- C

A(
B

81
CI

••t
• • tt

__ 0

P12 11 10

HIIINlz/v/c

A.M - A
B.M - B
A+ M-A
B+ 1'.1 - B
A0M->A
B0M->B

I
I

CPX
TSTA
TSTB
TST

I
I

ASLA
ASLIl
ASL

.1
3

514

··• ..•
·.
··..
·.
··..
··..
··..
··..

R·
R·
R·
R.
R·
R·

t t 6 t
t t 6 t
t t 6 t

• •

• •
• •
• •

t t 6 t
t t 6 t
t t 6 t
R t 6 t
Rt 6 t
R t 6 t
t t 6 t
t t 6 t
t t 6 t
t t 6 t
t t 6 t
t t !> t

• • t t t t
• • t t t t
• • t t t t

·.

7 t 8 •

• • t t
• • t t
• • t t
• • t t
• • t t

R R
R R
R R
R.
R.

·.·.·.
·.·.·.
·.·.·.
·.·.·.
·.·.·.
·.·.·.
··..·.·.
·.·.
·.·.·.
·.·.·.
··..··• ..• ··..
··..·.·• .•
·.·.·.

S6800/S68AOO/S68 BOO
FIGURE 10

S6800 INSTRUCTION SET (CONT'D.)
Addressing Modes

Instruction

Branch to
subroutine
Jump to
subroutine
Jump
Return from
subroutine
Return from
interrupt
Software interrupt
Wait for interrupt

Mn~mol1ic

Direct

Immediate

Extended

Indexed

Relative

OP Me PB

OP MC P.B

OP Me PB

OP MC PB

OP Me PB

BI) ()
7l 3

AD X
<>E 4

Xl)

IlSI{
JSI{
J~lP

I{TS

I{TI
SWI
\\AI

.Ill 10
31' 12
.IE q
02

No operation

~OP

Clear

Cl.I{A
CLI{Il
CLI{
CLC

Clear carry
Clear interrupt
mask
Clear overtlow
Set carry
Set interrupt
mask
Set overtlow

Condition Reg.

Implied

I
I

Boolean/ Arith

51 ~ 31 21 110

Operation

HlllNlzlvlc

Special
OpcralilHls

PC+I~PC
OO~

'iF
71'

61'

OO~

;\
Il
M

O~C

CI.I
CLV
SEC

O~I

0;\

o~v

IlD

I~C

SI:I
SEV

OF
Oil

I~V

·.·.·.
··..··..··..
·.·.·.
·.·.
·.··..··..
···...
·.·....
··..··..
·.··..·.
:\(lIC

• S
• II

I{ S I{I{
I{S I{ I{
I{S R I{
• I{

I{.

I{ •

• S

S •

CONDITION CODE SYMBOLS:
H
N
Z
V
C

•

Half-carry from bit 3;
Interrupt mask
Negative (sign bit)
Zero (byte)
Overflow, 2's complement
Carry from bit 7
Reset Always
Set Always
Test and set if true, cleared otherwise
Not Affected

OP
MC
PB
+

Operation Code (Hexadecimal):
Number of MPU Cycles;
Number of Program Bytes;
Arithmetic Plus;
Arithmetic Minus;
•
Boolean AND;
MSp Contents of memory location pointed to by Stack Pointer;
+
Boolean Inclusive OR;
ED
Boolean Exclusive OR;
.M
Complement of M;
Transfer Into;
O B i t = Zero;
00
Byte = Zero;
Note - Accumulator addressing mode instructions are included in the IMPLIED addressing.

CONDITION CODE REGISTER NOTES:

1
2

3
4
5
6
7
8
9
10
11
12

(Bit V)
(Bit C)
(Bit C)
(Bit V)
(Bit V)
(Bit V)
(Bit N)
(Bit V)
(Bit N)
(All)
(Bit I)
(ALL)

(Bit set if test is true and cleared otherwise)
Test: Result = 10000000?
Test: Result = OOOOOOOO?
Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set.)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to result of N e C after shift has occurred.
Test: Sign bit of most significant (MS) byte = I?
Test: 2's complement overflow from subtraction of MS bytes?
Test: Result less than zero? (Bit 15 = 1)
Load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs, if previously set, a Non-Maskable Interrupt is required to exit· the wait state.
Set according to the contents of Accumulator A

3.16

S6800/S68AOO/S68 BOO

SPECIAL OPERA nONS

JMP, JUMP;

6E
'NDXD (

MAIN PROGRAM

IT
n+1

X+KI

MAIN PROGRAM
7E

JMP

OFFSET

EXTENDED {

JMP

n+ 1

NEXT ADDRESS

n+2

NEXT ADDRESS

NEXT INSTRUCTION
KI

NEXT INSTRUCTION

JSR, JUMP TO SUBROUTINE:
MAIN PROGRAM

AD = JSR
'NDXD {

n+1
n+2

= OFFSET*

n+1

SL = SUBR. ADDR.

n+3

NEXT MAIN INSTR.

SUBR. ADDR.

SUBROUTINE

1st SUBR. INSTR.

+ 2) H

(n + 2) L
(n + 2) HAND (n

8-BIT UNSIGNED VALUE

n+2

MAIN PROGRAM
BD = JSR

INX + K

SP - 1

NEXT MAIN INSTR.

STACK

_SP-2

2) L FORM n + 2

STACK

SP - 2

SP -1

(n + 3) H

(n + 3) L

SUBROUTINE

1st SUBR. INSTR.

FORMED FROM SH AND SL)

- = STACK POINTER

AFTER EXECUTION.

BSR, BRANCH TO SUBROUTINE:
MAIN PROGRAM

±K

n+1
n+2

= BSR

= OFFSET*

NEXT MAIN INSTR.
*K

= 7-BIT SIGNED VALUE;

STACK

SUBROUTINE
.-------------~

n+2:!:K

SP - 2
(n

SP -1

+ 2) H

SP L-____________
(n + 2) L
....J
n + 2 FORMED FROM (n + 2)H
AND (n + 2)L

3.17

1st SUBR. INSTR.

56800/568AOO/568BOO

SPECIAL OPERATIONS

RTS, RETURN FROM SUBROUTINE:

fk
S

SUBROUTINE
39

RTS

Ie>

SWI, SOFTWARE INTERRUPT
~

SWI

SP + 2

MAIN PROGRAM
3E

WAI

MAIN PROGRAM

NEXT MAIN INSTR.

STACK

SP - 7
SP - 6

INTERRUPT PROGRAM
INT. ROUTINE

ml
mH
mL
H

SP - 5

ACCB

SP - 4

ACCA

SP - 3

SP - 2

SP - 1

(n + l)H

(n + l)L

STACK

SP - 7
SP - 6

SP - 5

ACCB

SP - 4

ACCA

SP - 3

SP - 2

SP - 1

(n + l)H

(n + l)L

WAI, WAIT FOR INTERRUPT

MAIN PROGRAM

---

SP + 1

e.c.

~
~

(H - 0005)
(H - 0004)

ADDRESS WITH
ALL ADDRESS LINES
IN HIGH STATE

INTERRUPT PROGRAM

INT. ROUTINE

mH ~ (H - 0007)
mL ~ (H - 0006)
H ~ ADDRESS WITH
ALL ADDRESS LINES
IN HIGH STATE

PROGRAM PROCEEDS AT m ONLY AFTER
EXTERNAL INTERRUPT REQUEST

RTI, RETURN FROM INTERRUPT:
~

INTERRUPT PROGRAM
3B~

RTI

Ie>

STACK

SP + 1

SP + 2

ACCA

SP + 3

ACCB

SP +4

SP + 5

SP + 6

SP +7

3.18

MAIN PROGRAM

NEXT MAIN INSTR.

J
J

S6800/S68AOO/S68 BOO

SYSTEMS OPERATION
To demonstrate the great versatility of the functional
building block concept, a typical system configuration is
shown. This configuration will demonstrate how easily a basic
system may be upgraded and expanded for a number of
different applications.
The Microprocessing Unit (MPU) may be configured
with a Read Only Memory (ROM), Random Access Memory
(RAM), a Peripheral Interface Adapter (PIA), restart circuitry
and clock circuitry to form a minimum functional system
(Figure 10). Such a system can easily be adapted for a number
of small scale applications by simply changing the content of
the ROM.

Device

AI4

AI3

Hex Addresses

RAM
PIA
ROM

o
o

0000-007F
2004- 2007 (Registers)
6000-63FF

Other addressing schemes can be utilized which use any
combination of two of the lines A I 0 through A I 4 for chip
selection.
PERIPHERAL CONTROL-All control and timing for
the peripherals that are connected to the PIA is accomplished
by software routines under the control of the MPU.
RESTART AND NON-MASKABLE INTERRUPT-Since
this basic system does not have a nonvolatile RAM, special
circuitry to handle loss of power using NMI is not required.

TWO-PHASE CLOCK CIRCUITRY AND TIMING-The
MPU requires a two-phase non-overlapping clock which has a
frequency range as high as 1 MHz for the S6800, 1.5 MHz for
the S68AOO, and 2.0 MHz for the S68BOO. In addition to the
two phases, this circuit should also generate an enable signal E,
and its complement E, to enable ROMs, RAMs, PIAs and
ACIAs. This Enable signal and its complement is obtained by
ANDing 92 and VMA (Valid Memory Address).

CHIP SELECTION AND ADDRESSING- The minimum
system configuration permits direct selection of the ROM,
RAM, ACIA and PIA without the use of special TTL select
logic. This is accomplished by simply wiring the address lines
AI3 and A14 to the Enable or chip select lines on the
memories and PIA. This permits the devices to be addressed
as follows:

Circuitry is, however, required to insure proper initialization
of the MPU when power is turned on. This circuit should
insure that the Restart signal is held low for eight ¢1 clock
cycles aft~r the V CC power supply reaches a voltage of
approximately 4.75 volts DC. Also, in order to insure that a
PIA or ACIA is not inadvertently selected during the power-on
sequence, Three-State Control (TSC) should be held high until
the positive transition of Restart.

HALT-The Halt line is tied to VCC and will automatically place the MPU in the run state when power is turned
on. This signal may be used to halt the MPU if a switch is
used to tie the line to ground for HALT and to V CC for
RUN.

3.19

1-:-_:

S6800/S68AOO/S68BOO
FIGURE 11

MINIMUM SYSTEM CONFIGURATION

VMAe02

TWO-PHASE
CLOCK

AO-A9

.10..
AO-A9

AOA9

RESTART

OBE

J '-:.

TSC

S6831
00-07
AO-A9

A14

RES

r--.

Mf1I

00-07

HALT

VCC

A14

R/W

AO-A6

IRO

~
E

00-07

RAM
S6810

Vcc

PAO-PA7

f--<> VCC

....-

PERI~~.~RAL

}

~
S6820

---

A13

CA2

-"\
----v'

....

CAl

00-07

AQ-Al

S6800

RES

~E
_E

A13

L.-.

•

!l.QM

02 VMA

::;

RSO-RSl
CSO
CSl
CS2
R/W
PBO-PB7
CBl
00-07

TFiOA

CB2

¢=>

...---

IROB

DATA BUS 00-07

AUGUST 1977

3.20

ADVANCED PRODUCT DESCRIPTION

56801
MICROCOMPUTER
UNIT (MCU)*
Features

General Description

• Expanded 86800 instruction set

The ~86801 MeU is an 8-bit microcomputer system
which is expandable, using the 86800 microprocessor
family. The 86801 MeU is object code compatible with
the 86800 instruction set with improved execution
times of key instructions plus several new 16-bit and
8-bit instructions. The 86801 MeU can operate single
chip or be expanded to 65K words. The 86801 MeU is
TTL compatible and requires one + 5.0 volt power supply. The 86801 MeU has 2K bytes of ROM and 128
bytes of RAM on board. In addition, the 86801 MeU
has on board serial and parallel I/O and three 16 stage
timer function.

• Object code compatible with 86800
• 8ingle chip or expandable to 65K words.
•

2K bytes of ROM

• 128 bytes of RAM (64 bytes retainable)
• 31 parallel I/O lines
• Internal Clock/Divide·by·Four mask option
(86801)
• External Clock/Divide·by·One mask option
(86801E)

• Available 1st Quarter 1979

• TTL compatible inputs and outputs
• Interrupt capability
• Hardware Multiply
Block Diagram

A7 0 7 1/0 28
A61ls 1/027
A5 05 1/0 26
A,O,I/O 25
A3 Do 1/024
A2 02 1/023
A, 0,1/022
Ao Do I/O 21

I/O
I/O
I/O
I/O
I/O

I/O PORT
NO.3

OTiN
1 TOUT
2T/R
3SClK
4SI0

R/WOS
AS is

A'51/O 20
A"I/O 19
A'31/O 18
A'21/0 17
A"I/O 16
A,ol/O 15
A9 I/O 14
As I/O 13

1/05
I/O 6
1/07
I/O 8
I/O 9
1/010
I/O 11
1/012

I/O PORT
NO.4

VOO STANDBY

3.21

ADVANCED PRODUCT DESCRIPTION

56802
MICROPROCESSOR
WITH CLOCK AND RAM
Features

General Description

D On-Chip Clock Circuit

The S6802 is a monolithic 8-bit microprocessor that
contains all the registers and accumulators of the
present S6800 plus an internal clock oscillator and
driver on the same chip. In addition, the 86802 has
128 bytes of RAM on board located at hex addresses
0000 to 007F. The first 32 bytes of RAM, at hex
addresses 0000 to 001F, may be retained in a low
power mode by utilizing Vee standby, thus facilitating memory retention during a power-down situation.

D 128 x 8 Bit On-Chip RAM
D 32 Bytes of RAM Are Retainable
D Software-Compatible with the S6800
D Expandable to 65K Words
D Standard TTL-Compatible Inputs and Outputs
D 8-Bit Word Size

The 86802 is completely software compatible with the
86800 as well as the entire 86800 family of parts.
Hence, the 86802 is expandable to 65K words. When
the 86802 is interfaced with the 86846 ROM - I/O Timer chip, as shown in the Block Diagram below, a
basic 2-chip microcomputer system is realized.

D 16-Bit Memory Addressing
D Interrupt Capability

Pin Configuration

Typical Microcomputer Block Diagram

Vss

HAiT
MR

RESET
XTAL
EXTAL

lim
VMA

S6846

NMI

MR
VMA

RESET

CLOCK
8·BIT MPU

12B BYTES RAM

RE
Vee STANDBY
Rm

Vee

Rm ON BOARD CLOCK
NMI
PARALLEL
00 - 07

If 0

DO - 07

A15

XTAL
AO- A15

AO - A15

EXTAL

Vss

"::'

A14

A13

Al0

A12

All

Vss

"::'

BLOCK OIAGRAM OF A TYPICAL COST EFFECTIVE MICROCOMPUTER. THE MPU IS THE CENTER OF THE MICROCOMPUTER SYSTEM AND IS
SHOWN' IN A MINIMUM SYSTEM INTERFACING WITH A ROM COMBINATION CHIP. IT IS NOT INTENDEO THAT THIS SYSTEM BE LIMITED TO
THIS FUNCTION BUT THAT IT BE EXPANDABLE WITH OTHER PARTS IN THE S6800 MICROCOMPUTER FAMILY.

This is advance information and specifications are subject to change without notice

3.22

56802

Absolute Maximum Ratings
Supply Voltage ............................................................ -0.3V to + 7.0V
Input Voltage
., .......................................................... -0.3V to + 7.0V
Operating Temperature Range .................................................. O°C to + 70°C
Storage Temperature Range ................................................ -55°C to + 150°C
Thermal Resistance .................................................. ~ .......... , 70°C/W
*eOMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

D.C. Electrical Characteristics (Vee
Symbol

= 5.0V ± 5%, Vss = 0, TA = O°C to

Parameter

VIH

Input High Voltage

V1L

Input Leakage Voltage
Input Leakage Current
(VIN = 0 to 5.25V, Vee = Max)
Output High Voltage
(ILOAD = - 205J1A, Vee = Min)
(ILOAD = -145pA, Vee = Min)
(ILOAD = - 100pA, Vee = Min)
Output Low Voltage
(ILOAD = 1.6mA, Vee = Min)
Power Dissipation
Capacitance tt=
(VIN = 0, TA =25°C, f=1.0MHz

lIN
VOH

VOL
PD**
Cm

COUT

+70°C unless otherwise noted.)
Min.

Typ.

Logic, EXtal
Reset
Logic, EXtal, Reset
Logic *

Vss +2.0
Vss +4.0
Vss - 0.3

DO-D7
AO-A15, R/W, VMA,E
BA

VSS +2.4
Vss +2.4
VSS +2.4

1.0

DO-D7
Logic Inputs, EXtal
AO - A15, R/W, VMA

Max.
Vee
Vee
Vss_+ 0.8
2.5

VSS + 0.4

Unit
V
V
pA
V
V
V
V
V

0.600

1.2

10
6.5
-

12.5
10
12

Min.

Typ.

Max.

Unit

0.1
1.0
1.0
450

1.0
4.0
10
4500

MHz

W
pF

Clock Timing (Vee:::: 5.0V ± 5%, Vss :::: 0, TA = 0° C to +70° C unless otherwise noted)
Symbol

Parameter

f
fXtaI
teye
PW¢Hs
PW¢L
t¢

Frequency of Operation

Input Clock-+-4
CrysUti Frequency

Cycle Time
Clock Pulse Width
Measured at 2AV
Fall Time
Measured between Vss + OAV and Vss -2.4V

ps
ns

*Except IRQ and NMI, which require 3Kr2 pull up load resistors for wire-OR capability at optimum operation. Does not include
EXtal and Xtal, which are crystal inputs.
**1n power-down mode, maximum power dissipation is less than 40mW.
Heapacitances are periodically sampled rather than 100% tested.

3.23

56802

Read/Write Timing (Figures 1 through 5; Load Circuit of Figure 3).

(Vcc

5.0V ± 5%, VSS

0, TA

O°C to + 70°C unless otherwise noted.)

Symbol

Parameters

tAD
tACC
tDSR
tH
tAH
tDDW

Address Delay
Peripheral Read Access Time
tACC = tut - tDSR)
Data Setup Time (Read)
Input Data Hold Time
Address Hold Time (Address, RjW, VMA)
Data Delay Time (Write)
Processor Controls:
Processor Control Setup Time
Processor Control Rise and Fall Time
(Measured between 0.8V and 2.0V)

tpcs
tpcr, tpcf

Figure 1. Read Data From Memory or Peripherals

Min.

Typ.

Max.

Unit

270
530

100
10
20

ns
ns
ns
ns
ns
ns

165

225

200

100

ns
ns

Figure 3. Bus Timing Test Load

R/W
ADDRESS ?~~~~;::-~;..---------------t'th:~
________________

FRDMMPU~~~~~=-~1-

~~~-

Rl = 2.2K

TEST POINT

O-......--

w
Q

I- Vec: 5.0V

I-'"""

-""

100

400 r- TA

---

100

I,.....- ~

200

b----- ~~

200

300

-----------

.......- ADDRESS. VMA f - R/W

100

CL INCLUDES STRAY CAPACITANCE

: 25'C

~
i= 300

200

IOH: -145/iA MAX @2.4V
1.6mA MAX@0.4V

500 I- IOL:

500

400

600

C INCLUDES STRAY CAPACITANCE
L

200

100

CL• LOAD CAPACITANCE (pF)

500

400

300

Figure 6. 56802 Expanded Block Diagram

A15
25

MEMORY READY

A14
24

A13
23

A12
22

All
20

AID
19

A9
18

A8
17

ENABLE 37

REID

NON·MASKABLE INTERRUPT

HALT

INTERRUPT REQUEST

XTAL 39
EXTAL 38
BUS AVAILABLE

VALID MEMORY ADDRESS

REAON/RITE 34

Vee: PIN8.35
Vss : PIN 1,21

26
07

600

CllOAD CAPACITANCE (pF)

27
06

28
05

29
04

30
03

31
02

3.25

32
01

33
DO

A7
16

A6
15

A5
14

A4
13

A3
12

A2
11

Al
10

AO
9

56802

Functional Description

MPU Registers

information in the stack when power is lost, the stack
must be non-volatile.

A general block diagram of the 86802 is shown in
Figure 6. As shown, the number and configuration of Index Register - The index register is a two byte
the registers are the same as for the 86800. The 128 register that is used to store data or a sixteen-bit
x 8 bit RAM has been added to the basic MPU. The memory address for the Indexed mode of memory
first 32 bytes may be operated in a low power mode addressing.
via a Vee standby. These 32 bytes can be retained
during power-up and power-down conditions via the Accumulators - The MPU contains two 8-bit accumulators that are used to hold operands and results from
RE signal.
The MPU has three 16-bit registers and three 8-bit an arithmetic logic unit (ALU).
registers available for use by the programmer (Figure 7). Condition Code Register - The condition code
Program Counter - The program counter is a two register indicates the results of an Arithmetic Logic
byte (16-bits) register that points to the current pro- Unit operation: Negative (N), Zero (Z), Overflow (V),
gram address.
Carry from bit 7 (C), and Half Carry from bit 3 (H).
8tack Pointer - The stack pointer is a two byte These bits of the Condition Code Register are used as
register that contains the address of the next available testable conditions for the conditional branch instruclocation in an external push~own/pop-up stack. This tions. Bit 4 is the interrupt mask bit (I). The used bits
stack is normally a random access Read/Write memory of the Condition Code Register (b6 and b7) are ones.
that may have any location (address) that is conven- Figure 8 shows the order of saving the microprocessor
ient. In those applications that require storage of· status within the stack.
Figure 7. Programming Model of
the Microprocessing Un it

I
I
I

L--J

ACCA

ACCB

I
I
I
I

m -9

ACCUMULATOR A

m -8

Figure 8. Saving the Status of
the Microprocessor in the Stack

0
IX

INDEX REGISTER

0
PC

m --6

m-5

ACCB

m -4

ACCA

m -3

IXH

-2

m -2

IXL

m-1

PCH

PROGRAM COUNTER

0
SP

~SP

m -7

ACCUMULATOR B

PCL

~SP

STACK POINTER

m+1

m+2

v--.

CONDITION CODES
REGISTER

1, <1>2 in the machine will be halted. This input is level
input, and two unused pins have been eliminated, and sensitive. In the halt mode, the machine will stop at
the following signal and timing lines have been added: the end of an instruction, Bus Available will be at a
high state, Valid Memory Address will be at a low
RAM Enable (RE)
state, and all other three-state lines will be in the
Crystal Connections EXtal and Xtal
three-state mode. The address bus will display the
address of the next instruction.
Memory Ready (MR)
To insure single instruction operation, transition of
Vee Standby
the Halt line must not occur during the last 250ns of
Enable <1>2 Output (E)
E and the Halt line must go high for one Clock cycle.
The following is a summary of the S6802 MPU signals: Read/Write (R/W) - This TTL compatible output
Address Bus (AO - A15) - Sixteen pins are used for signals the peripherals and memory devices whether
the address bus. The outputs are capable of driving the MPU is in a Read (high) or Write (low) state. The
one standard TTL load and 130pF.
normal standby state of this signal is Read (high).
Figure 9. Power-up and Reset Timing

20ms
MIN
RESET

--+--'1
20ms
MIN

.-,-----------il--------~~~~ ___ :1°~ __
l-t
t ~~T~~~~lOW)
__
__

J'"

-------~J_-----

RESET - - - - - r -

PCf

------=

1
1

RE _ _ _ _ _....;.0....;..8_V

1
1

2.0V

(SEE

1 _ _ _ _ _ _ _ _ _ __

OPTION 2
SEE FIGURE 10 FOR
POWER OOWN CONOITION

"J. . .

-------

_ t PCr ";;;100ns

\---------

VMA. - - - - - - . . . . , /

NOTE: IF OPTION liS CHOSEN, RESET AND RE PINS CAN BE TIED TOGETHER.

3.27

56802

When the processor is halted, it will be in the logical
one state. This output is capable of driving one standard TTL load and 90pF.
Valid Memory Address (VMA)-This output indicates
to peripheral devices that there is a valid address on
the address bus. In normal operation, this signal
should be utilized for enabling peripheral interfaces
such as the PIA and ACIA. This signal is not threestate. One standard TTL load and 90pF may be
directly driven by this active high signal.
Bus Available (BA) - The Bus Available signal will
normally be in the low state; when activated, it will
go to the high state indicating that the microprocessor
has stopped and that the address bus is available. This
will occur if the Halt line is in the low state or the
processor is in the WAIT state as a result of the execution of a WAIT instruction. At such time, all threestate output drivers will go to their off state and
other outputs to their normally inactive level. The
processor is removed from the WAIT state by the
occurrence of a maskable (mask bit I = 0) or nonmaskable interrupt. This output is capable of driving
one standard TTL load and 30pF.
Interrupt Request (IRQ) - This level sensitive input
requests that an interrupt sequence be generated
within the machine. The processor will wait until it
completes the current instruction that is being executed before it recognizes the request. At that time, if
the interrupt mask bit in the Condition Code Register
is not set, the machine will begin an interrupt sequence.
The Index Register, Program. Counter, Accumulators,
and Condition Code Register are stored away on the
stack. Next the MPU will respond to the interrupt
request by setting the interrupt mask bit high so that
no further interrupts may occur. At the end of the
cycle, a 16-bit address will be loaded that points to
a vectoring address which is located in memory locations FFF8 and FFF9. An address loaded at these
locations causes the MPU to branch to an interrupt
routine in memory.

tion in the registers will be lost. If a high level is
detected on the input, this will Signal the MPU to
begin the restart sequence. This will start execution
of a routine to initialize the processor from its reset
condition. All the higher order address lines will be
forced high. For the restart, the last two (FFFE,
FFFF) locations in memory will be used to load the
program that is addressed by the program counter.
During the restart routine, the interrupt mask bit is
set and must be reset before the MPU can be interrupted by IRQ. Power-up and reset timing and powerdown sequences are shown in Figures 9 and 10,
respectively.
Figure 10. Power-Down Sequence

Vee

--------_1

tpCf .;;; 100"s

Non-Maskable Interrupt (NMI) - A low-going edge
on this input requests that a non-mask-interrupt
sequence be generated within the processor. As with
the Interrupt Request signal, the processor will
complete the current instruction that is being executed before it recognizes the NMI signal. The
interrupt mask bit in the Condition Code Register
has no effect on NMI.

The Halt line must be in the high state for interrupts
to be serviced. Interrupts will be latched internally
while Halt is low.

The Index Register, Program Counter, Accumulators,
and Condition Code Register are stored away on the
stack. At the end of the cycle, a 16-bit address will
be loaded that 'points to a vectoring address which is
located in memory locations FFFC and FFFD. An
address loaded at these locations caused the MPU
to branch to a non-maskable interrupt routine in
memory.

The IRQ has a high impedance pull-up device internal
to the chip; however a 3kn external resistor to Vee
should be used for wire-OR and optimum control of
interrrupts.

NMI has a high impedance pull-up resistor internal to
the chip; however a 3kn external resistor to Vee
should be used for wire-OR and optimum control of
interrupts.

Reset - This input is used to reset and start the MPU
from a power down condition, resulting from a power
failure or an initial start-up of the processor. When
this line is low, the MPU is inactive and the informa-

Inputs IRQ and NMI are hardware interrupt lines that
are sampled when E is high and will start the interrupt
routine on a low E following the completion of an
instruction.

3.28

56802

Figure 11 is a flow chart describing the major decision
paths and interrupt vectors of the microprocessor.
Table 1 gives the memory map for interrupt vectors.

When MR is low, it may be stretched integral multiples of half periods, thus allowing interface to slow
memories. Memory Ready timing is shown in
Figure 12.

RAM Enable (RE) - A TTL-compatible RAM enable
input controls the on-chip RAM of the 86802. When Enable (E) - This pin supplies the clock for the MPU
placed in the high state, the on-chip memory is and the rest of the system. This is a single phase, TTL
enabled to respond to the MPU controls. In the low compatible clock. This clock may be conditioned by
state, RAM is disabled. This pin may also be utilized a Memory Ready 8ignal. This is equivalent to ¢2 on
to disable reading and writing the on-chip RAM the 86800.
during power-down situation. RAM enable must be Vee 8tandby - This pin supplies the dc voltage to
low three ps before Vee goes below 4.75V during the first 32 bytes of RAM as well as the RAM Enable
power-down.
(RE) control logic. Thus retention of data in this
EXtal and Xtal - The 86802 has an internal oscilla- portion of the RAM on a power-up, power-down, or
tor that may be crystal controlled. These connec- standby condition is guaranteed. Maximum current
tions are for a series resonant fundamental crystal. drain at 5 .25V is 8mA.
(AT out.) A divide-by four circuit has been added to
the 86802 so that a 4MHz crystal may be used in lieu Table 1. Memory Map for Interrupt Vectors
of a IMHz crystal for a more cost effective system.
VECTOR
DESCRIPTION
Pin 38 of the 86802 may be driven externally by a
MS
LS
TTL input signal if a separate clock is required. Pin
FFFE
FFFF
RESTART
39 is to be left open in this mode.
Memory Ready (MR) - MR is a TTL compatible
input control signal which allows stretching of E.
When MR is high, E will be in normal operation.

3.29

FFFC

FFFD

NON·MASKABLE INTERRUPT

FFFA

FFFB

SOFTWARE INTERRUPT

FFF8

FFF9

INTERRUPT REQUEST

S6802

Figure 11. MPU FlowChart

Figure 12. Memory Ready Control Function
B - RELEASE

A - SETUP

-21

2.0V
MR

Contact AM I for complete product description.

0.4V

r--~300NS

3.30

ADVANCED PRODUCT DESCRIPTION

56809
HIGH PERFORMANCE
MICROPROCESSOR*
Features
Block Diagram

• Upward source compatible with 86800
•

Bus compatible with 86800 family

A'5 A14 A'3 A'2 A" A10 Ag As

20 19

18 17

A5 Ao

A2 A, AD

14 13

• 2MHz Bus operation
• Pin-out compatible with 86800/86802
•

On-chip Oscillation/Clock Driver

• TTL compatible I/O

• 3 priority Interrupts

• Fast Interrupt - Cuts Response Time
Interrupt acknowledge allows vectoring by device

• Memory Ready 8ignal for slow memory
• +5V Power 8upply
• Expandable to 64 K words

INSTRUCTION
DECODE
AND
CONTROL

General Description

The 86809 is a monolithic microprocessor that contains .
all the registers of the 86800 plus an additional clock
oscillator and driver on chip.
The 86809 gives the user 8- and 16-bit word capability,
while retaining software compatibility with the basic
86800 family. Four 8-bit-wide registers and five 16-bitwide ones process the data, with the 8-bit accumulators
supplying routing computation.
The 86809 is compatible with the complete set of 86800
peripheral and memory devices. It is designed for the
middle and high end of the microprocessor scale.
'Availabl.> 1st Quarter 1979

3.31

2627
07

:JJ

313233

Os D5 Do 0 3 02 0,
PRELIMINARY PINOUTS

S6810/S6810A-1
128x8 STATIC
READ/WRITE MEMORY
Features

General Description

o
o

The S6810A is a static 128 x 8 Read/Write Memory
designed and organized to be compatible with the
S6800 Microprocessor. Interfacing to the S6810A
consists of an 8-Bit Bidirectional Data Bus, Seven
Address Lines, a single Read/Write Control line, and
six Chip Enable lines - four negative and two positive.

Organized as 128 Bytes of 8 Bits
Static Operation
OBi-Directional Three-State Data Input/Output
o Six Chip Enable Inputs (Four Active Low,
Two Active High)
o Single 5-Volt Power Supply
o TTL Compatible
o Maximum Access Time = 450ns for S6810A
350ns for S6810A - 1

For ease of use, the S6810A i!) a totally static memory
requiring no clocks or cell refresh. The S6810A is
fabricated with N-channel silicon gate depletion mode
technology to be fully DTL/TTL compatible with
only a single +5 volt power supply required.

Block Diagram

Pin Configuration

12100
AOl231

13101

AI 1221

14102

GNO

A21211

15103

A3(20)

16104
01

MI191

17105

A511S1

18106

A61111

19107

REAO/ 1161
WRITE
E31131

RIW

EOIIO)
rs 1151
[41141
Ei 1121

Ei 1111

111 1241
GNO Vee 1+5VI

3.32

Vee

S6810A/S6810A-1

Absolute Maximum Ratings
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields, however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit.
Supply Voltage Vcc ........................................................ - 0.3 to +7.0V
Input Voltage VIN .......................................................... - 0.3 to +7.0V
Operating Temperature Range TA ............................................... O°C to +70°C
Storage Temperature Range Tstg ............................................ - 55°C to +150°C

DC (Static) Characteristics
Vcc = 5.0V ± 5%; TA = 0° C to + 70° C unless otherwise noted
Symbol

Parameter

Input High Voltage
Input Low Voltage
Input Current (An, R/W, En, En)
(VIN = 0 to 5.25V)
Output High Voltage (IOH = 205 J.1.A)
VOH
Output Low Voltage (IOL = 1.6mA)
VOL
Output Leakage Current (DO - D7)
ILIH
(Va = 2.4V, E = 0.8V, E = 2.0V)
ILOL Output Leakage Current (DO - D7)
(Va = O.4V, E = 0.8V, E = 2.0V)
Supply
Curren t
Icc
(Vcc = 5.25V, TA = O°C)
S6810A
S6810A -1
Input Capacitance *
CIN
Output
Capacitance*
COUT
Vrn
VIL
lIN

Min.
2.0
- 0.3
-

Typ.
-

2.4

Max.

Unit

5.25
0.8
2.5

V
V
J.1.A

0.4
10

V
V
J.1.A

J.1.A

rnA
rnA
pF

70
80
7.5

Condition

f=l.OMHz, TA =25° C
f=1.0MHz,TA =25°C

*This parameter periodically sampled rather than 100% tested.

AC (Dynamic) Characteristics
Vcc = 5.0V ± 5%, TA = O°C to +70°C
Symbol
tAS
tAH
tcs

Parameter

Min.

Address Setup Time
Address Hold Time
Chip Enable Pulse Width

20
0
230
180

S6810A
S6810A -1

3.33

Max.
-

Unit
ns
ns
ns
ns

S6810A/S6810A-1

Read Cycle
(All timing with low input pulse 0.8V, high input pulse 2.0V, tr
Symbol
tCYC

= tf = 20ns, Load of Figure 1)

Parameter
(R)

S6810A
S6810A -1
S6810A
S6810A -1
S6810A
S6810A -1
S6810A
S6810A -1

Read Cycle Time

tDD

Outpu t Disable Delay Time

tAcC

Read Access Time

tRCS

Read to Select Delay Time

Min.

Max.

Unit

450
350
10
10

450
350

0
0

ns
ns
ns
ns
ns
ns
ns
ns

Max.

Unit

ns
ns
ns
ns
ns
ns
ns
ns

Write Cycle

= tf = 20ns, Load of Figure 1)

(All timing with low input pulse 0.80, high input pulse 2.0V, tr
Symbol
tCYC

Parameter
(W)

Min.
S6810A
S6810A -1
S6810A
S6810A -1
S6810A
S6810A -1
S6810A
S6810A -1

Write Cycle Time

twp

Write Pulse Width

tDS

Data Setup Time

twcs

Write to Select Delay Time

Figure 1. AC Test Load

5 .0V

RL = 2.5k
MMD6150
:J--4lI--iCI ......3--... OR
EOUIV
1.A

TEST POINTO-...

130pF*:;::::::

11.7k

~~~~~~~~~

~~
1176162

'Includes Jig Capacitance

3.34

450
350
300
250
190
150
0
0

S6810A/S6810A-1

Timing Characteristics
Figure 2. Read Cycle Timing

Figure 3. Write Cycle Timing

ED DON'T CARE

1176160

Physical Dimensions

"0, i--""

1176161

-:)-"., '"

[[J

DON'T CARE

Ordering Information

LPIN 110ENTIFIER

065

li o

~LL
T
.

020
•
015~

ON LID
SURFACE
ONLY

Order No.

No.
Pins

Package

Temp.
Range

S6810AP

Plastic

o -70°C

S6810A

Ceramic

o -70°C

S6810A-1P

Plastic

o -70°C

S6810A-1

Ceramic

o -70°C

12
090MIN.$.200MAX
020 MIN.

L:595~

575

[""J
.590

--..1
I

f9~0"

.008

15' MAX

3.35

Description
NMOS 128 x 8 Static
RAM, TAA =450ns Max
NMOS 128 x 8 Static
RAM, TAA =450ns Max
NMOS 128 x 8 Static
RAM, TAA =350ns Max
NMOS 128 x 8 Static
RAM, TAA =350ns Max

S68A 10/568810
128 X 8 STATIC
READ/WRITE MEMORY

Features

General Description

o
o
o
o

Organized as 128 Bytes of 8 Bits

The S68A10 and S68B10 are static 128x8 Read/Write
Memories designed and organized to be compatible
with the S68AOO and S68BOO Microprocessors. Interfacing to the S68A10 and S68B10 consists of an 8-bit
bidirectional data bus, seven address lines, a single
Read/Write control line, and six chip enable lines,
four negative and two positive.

o
o
o

Single 5 Volt Power Supply

Static Operation
Bidirectional Three-State Data Input/Output
Six Chip Enable Inputs (Four Active Low,
Two Active High)

For ease of use, the S68A10 and S68B10 are a totally
static memory requiring no clocks or cell refresh. The
S68A10 and S68B10 are fabricated with N-channel
silicon gate depletion load technology to be fully
DTL/TTL compatible with only a single +5 volt power
supply required.

TTL Compatible
Maximum Access Time:
-360ns for S68A10
-250ns for S68B10

Block Diagram

Pin Configuration

Vee
M
01
(21 DO

A7
A3

AO(231

(3101

AI (221

(4102

A2(211

(1103

A3(201

(S104

A4 (191

(7101

AS 1181

(810S

R/W

A6 (111

(9107

~~~~; (161-t--------'~..--_ _ _ _....I
E3(131

EO (101

AC Test Load

t5 ( 1 1 1 ' - + - - - < > " , E4 ( 1 4 1 - t - - - - Q j

I.OV

[2(121-+---<>1
E1(1I1-+---<>I

RL"2.Sk
(II

TEST POINT

(241

o-...............-iCa-~ ~~~~~,~

GNO Vee (+5VI
130pF"
MM07000

OR EQUIV

*lndudesJig Capacitance

3.36

568A 10/568810

Absolute Maximum Ratings

Supply Voltage
Input Voltage
Operating Temperature Range
Industrial Temperature Range
Military Temperature Range
Storage Temperature Range
DC Characteristics (V CC

Symbol
lIN
VOR
VOL
ILO
ICC

tcyc(R)
tacc
tAS
tAH
tDDR
tRCS
tDHA
tH
tDHW

Parameter
Input Current
(An' R/W, CS n , CS n )
Output High Voltage

Symbol
tcyc(W)
tAS
tAH
tcs
twcs
tDSW
tH

Min. Typ. Max.

Vdc

204

Units
pAdc

2.5

Output Low Voltage
Output Leakage Current
(Three -State)
Supply Current

004
10

Vdc
pAdc

mAdc

Conditions
VIN = OV to 5.25V
IOH = - 205pA
IOL = l.OmA
CS = O.BV or CS = 2.0V, VOUT = OAV
to 2AV
V CC = 5.25V, all other pins grounded,
TA = O°C

0, TA = O°C to +70°C unless otherwise noted.)

Parameter
Read Cycle Time
Access Time
Address Setup Time
Address Hold Time
Data Delay Time (Read)
Read to Select Delay Time
Data Hold from Address
Output Hold Time
Data Hold from Write

Write Cycle (V CC

= +5.0V ± 5%, V SS = 0, T A = 0 C to +70 C unless otherwise noted.)

AC Characteristics
Read Cycle (VCC = +5.0V ±5%, VSS

Symbol

-0.3V to +7.0V
-0.3V to +7.0V

S6BAI0
Min.
Max.
360
360
20
0
220
0
10
10
60
10

S6BBI0
Max.

Min.
250

250
20
0

IBO
0
10
10
10

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns

= +5.0V ± 5%, VSS = 0, T A = 0 0 C to +70 0 C unless otherwise noted.)

Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Chip Select Pulse Width
Write to Chip Select Delay Time
Data Setup Time (Write)
Input Hold Time

S6BAI0
Min.
Max.
360
20
0
250
0

BO
10
3.37

S6BBI0
Min.
250
20
0
210
0
60
10

Max.

Units
ns
ns
ns
ns
ns
ns
ns

568A 10/568810

Read Cycle Timing
~--------------

'cyclRI--------------.I

ADDRESS

DATADUT

-------------<
~DDNTCARE

Note: CS and CS can be enabled for consecutive read cycles provided R/W remains at VIH.

Write Cycle Timing

_-------------- 'CYclWI-------------§{--~

'"""'" -~~~~.8V~_____________________________
I:
CS

'AS

_ _ _ _ _ _ _ __ _

'AH

2.0V

----------~~~~~~

O.8V

R/W

O.8V

~ 'DSW~'H~

~2.~OV~-----------------

DATA IN

y.8V

DATA IN STABLE

~DDN'TCARE
Note: CS and CS can be enabled for consecutive write cycles provided R/W is strobed to VIH before or
coincident with the Address change, and remains high for time tAS'

3.38

S6821/S68A21/S68B21
PERIPHERAL INTERFACE
ADAPTER (PIA)
Features

General Description

8-Bit Bidirectional Data Bus for
Communication with the MPU

Two Bidirectional8-Bit Buses for Interface
to Peripherals

o
o
o

Two Programmable Control Registers

The S6821/S68A21/S68B21 are peripheral Interface
Adapters that provide the universal means of interfacing peripheral equipment to the S6800, S68AOO and
S68BOO Microprocessing Units (MPU). This device is
capable of interfacing the MPU to peripherals through
two 8-bit bidirectional peripheral data buses and
four control lines. No external logic is required for
interfacing to most peripheral devices.

Two Programmable Data Direction Registers
Four Individually-Controlled Interrupt Input
Lines: Two Usable as Peripher'll Control
Outputs

Handshake Control Logic for Input and
Output Peripheral Operation

High-Impedance Three-State and Direct
Transistor Drive Peripheral Lines

Program Controlled Interrupt and
Interrupt Disable Capability

CMOS Compatible Peripheral Lines

The functional configuration of the PIA is programmed
by the MPU during system initialization. Each of the
peripheral data lines can be programmed to act as an
input or output, and each of the four control/interrupt
lines may be programmed for one of several control
modes. This allows a high degree of flexibility in the
overall operation of the interface.
The PIA interfaces to the S6800/S68AOO/S68BOO
MPUs with an eight-bit bidirectional data bus, three
Pin Configuration

Block Diagram
Tii1iA38:--f------------I

CAl

PAO

CA2

PAl

IRIlA

PA2

IRIlB

PA3

RSO
RSI

GNO

PA4

PA5

PAS

PA7

ffi23

817255

'fiiOii31

3.39

PBO

PBl

S6821
S68A21
S68B21

RESET

PB2

PB3

P84

P8S

PB6

PBI

CSI

CBl

CS2

CB2

CSO

VCC

RIW

I
:
-:

S6821 IS68A21 IS68B21

General Description (Continued)

chip select lines, two register select lines, two interrupt request lines, read/write line, enable line and reset line.
These signals, in conjunction with the S6800/S68AOO/S68BOO VMA output, permit the MPU to have complete
control over the PIA. VMA may be utilized to gate the input signals to the PIA.

Absolute Maximum Ratings

-0.3V to +7.0V
-0.3V to +7.0V

Supply Voltage
Input Voltage
Operating Temperature Range
Industrial Temperature Range
Military Temperature Range

Note:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high
impedance circuit.

Electrical Characteristics (Vee
Symbol
VIH
VIL
lin
ITSI
IIH
IlL
VOH

VOL

IOH

ILOH
PD
Cin

Cout

= +5.0V ±5%, VSS = 0, TA = oOe to +70 o e unless otherwise noted.)

Parameter

Min.

Input High Voltage
Input Low Voltage
Input Leakage Current

Typ.

Max.

Units

Vdc
VCC
VSS+0.8 Vdc
2.5
/JAdc

VSS+2.0
VSS- 0.3

1.0
R/W, Reset, RSO, RSl, CSO, CS2,
CSl, CAl, CEl, Enable
10
2.0
Three-State (Off State) Input Current DO-D7, PBO-PB7, CB2
/JAdc
- 200 -400
Input High Current
PAO-PA7, CA2
/JAdc
-2.4
-1.3
mAdc
Input Low Current
PAO-PA7, CA2
Output High Voltage
DO-D7 VSS+2.4
Vdc
Other Outputs VSS+2.4
Vdc
Output Low Voltage
DO-D7
VSS+O.4 Vdc
Other Outputs
VSS+O.4 Vdc
Output High Current (Sourcing)
- 205
DO-D7
/JAdc
-100
Other Outputs
/JAdc
-1.0
-10
-2.5
mAdc
PBO -PB7, CB2

Output Leakage Current (Off State)
Power Dissipation
Capacitance

IRQA, IRQB

DO-D7
__
PAO-PA7, PBO-PB7, CA2, CB2
Enable, R/W, Reset, RSO, RSl, CSO, CSl, CS2, CAl, CBl
IRQA, IRQB

1.0

10
550

/JAdc
mW

12.5
10
7.5
5.0

pF
pF
pF
pF

Conditions

Yin = OVdc to +5.25Vdc
Yin = O.4Vdc to 2.4Vdc
VIH = 2.4Vdc
VIL = O.4Vdc
ILoad = - 205/JAdc
I Load = - 200/J Adc
ILoad = 1.6mAdc
ILoad = 3.2mAdc
VOH = 2.4Vdc
Vo = 1.5Vdc, the current
for driving other than TTL,
e.g., Darlington Base
VOH = 2.4Vdc

Yin = 0, TA = +25°C,
f = 1.0MHz

Note: The PAO-PA 7 Peripheral Data lines and the CA2 Peripheral Control line can drive two standard TTL loads. In the input mode, the
internal pullup resistor on these lines represents a maximum of 1.5 standard TTL loads.

3.40

S6821 IS68A21 IS68B21

A.C. (Dynamic) Characteristics Loading = 30pF and one TTL load for PAO-PA7, PBO-PB7, CA2, CB2
= 130pF and one TTL load for DO-D7, IRQA, IRQB
(VCC = +5.0V ±5%, TA = O°C to +70°C unless otherwise noted.)

Read Timing Characteristics (Figure 1)

Timing Characteristics (Vee = + 5.0V ± 5%, Vss = 0, TA = O°C to + 70°C unless otherwise noted,)

8ymbol
tpDSU
tpDH
tCA2
tRSl
t r • tc
tRS2
tpDw
tCMOS
tCB2
tDC
tRSl
PWCT
t r , tc
tRS2
tIR
tRS3
PWr
tRL

Parameter

86821
Min. Max.

200
Peripheral Data Setup Time
Peripheral Data Hold Time
a
Delay Time. Enable Negative Transition
to CA2 Negative Transition
Delay Time. Enable Negative Transition
to CA2 Positive Transition
Rise and Fall Times for CAl and CA2
Input Signals
Delay Time from CAl Active Transition
to CA2 Positive Transition
Delay Time. Enable Negative Transition
to Peripheral Data Valid
Delay Time. Enable Negative Transition
PAO-PA7. CA2
to Peripheral CMOS
Data: Valid
Delay Time. Enable Positive Transition
to CB2 Negative Transition
Delay Time. Peripheral Data Valid to
20
CB2 Negative Transition
Delay Time, Enable Positive Transition
to CB2 Positive Transition
Peripheral Control Output Pulse Width.
550
CA2/CB2
Rise and Fall Time for CBl and CB2
Input Signals
Delay Time. CBl Active Transition to
CB2 Positive Transition
Interrupt Release Time. IRQA and IRQB
Interrupt Response Time
Interrupt Input Pulse Width
500
1.0
Reset Low Time*

868B21
Min. Max. Units

135
0

100

a
0.670

0.5

p's

1.0

0.670

0.5

p's

1.0

p's

2.0

1.35

1.0

p's

1.0

0.670

0.5

p.S

2.0

1.35

1.0

p's

1.0

0.670

0.5

p's

0.5

0.670

1.0

550

p's
ns

550

1.0

p's

2.0

1.35

1.0

p's

1.6
1.0

1.1
1.0

0.85
1.0

p's
p's
ns

500
0.66

500
0.5

Conditions

ns
ns

1.0

*The Reset line must be high a minimum of LOlls before addressing the PIA.

3.41

868A21
Min. Max.

p.S

I
Vce - 30% Vcc;
Figure 6. Load C

S6821/S68A21/S68B21
Bus Timing Characteristics (Vee = + 5.0V ± 5%, Vss = OV, TA = O°C to + 70°C unless otherwise noted,)
Read

Symbol

Parameter

tcycE
PWEH
PWEL
tAS
tDDR
tH
tAH
tEr' tEf

Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and R/W Valid to
Enable Positive Transition
Data Delay Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable Input

S6821
Min. Max.

S68A21
Min. Max.

S68B21
Min.
Max.

1.0
0.45
0.43

0.666
0.280
0.280

0.50
0.22
0.21

fJ-S
fJ-S
fJ-s

160

140

320

220

10
10

180

10
10
25

Units

ns
ns
ns
ns

Write

Symbol

Parameter

tcycE
PWEH
PWEL
tAS
tDsw
tH
tAH
tEr' tEf

Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and R/W Valid to
Enable Positive Transition
Data Setup Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable Input

Figure 1. Peripheral Data Setup Time
{Read Mode}

S6821
Min.
Max.

S68A21
Min.
Max.

S68B21
Min.
Max.

1.0
0.45
0.43

0.666
0.280
0.280

0.50
0.22
0.21

fJ-S
fJ-S
fJ-S

160

140

195
10
10

80
10
10

60
10
10

ns
ns
ns
ns

Figure 2. CA2 Delay Time
{Read Mode; CRA·5

P A O . P A 7 = ; j 2.0V
PBOPB7

ENABLE

._-,-,0"'-8V_ _ _ _ _ _ __

t-;1

'PDSU

Units

CRA·3 = 1, CRA·4 = O}

O.4V
'CA2

2.4V

CA2

ENABLE _ _ _ _---J

*Assumes part was deselected during the previous E pulse.
877259

877260

3.42

S6821 IS68A21 IS68B21

Figure 3. CA2 Delay Time
(Read Mode; CRA·5 = 1, CRA-3 = CRA-4 = 0)

Figure 4. Peripheral CMOS Data Delay Times
(Write Mode: CRA-5 = CRA-3 = 1, CRA-4 = 0)

ENABLE
ENABLE
tr.11

CAl

''''~
CA2
O.4V

PAO·PA7

'""- '''J=:--

CA2 _ _ _ _ _J

Figure 5. Peripheral Data and CB2 Delay Times
(Write Mode; CRB-5 = CRB-3 = 1, CRB-4

Figure 6. CB2 Delay Time
(Write Mode; CRB-5

= 0)

= CRB-3 = 1, CRB-4 =

ENABLE
ENABLE

PBOPB7
CB2

CB2

CB2 Note:
CB2 goes low as a result of the positive transition of Enable.
877263

*Assumes part was deselected during the previous E pulse.
877264

Figure 7. CB2 Delay Time
(Write Mode; CRB-5

Figure 8. IRQ Release Time

= 1, CRB-3 = CRB-4 = 0)

"'~'~

2.0V

CBl

O.8V

If~""~r-2_.4V

--J

___

,"".~ ,,,L
r-----II

""'~
CB2
O.4V

*Assumes part was deselected during any previous E pulse.
877266

Figure 9. RESET Low Time

Figure 10. Bus Read Timing Characteristics
(Read Information from PIA)

*The Reset line must be a VIH for a minimum of Laps
before addressing the PIA.
877267

877268

3.43

S6821/S68A21/S68B21

Figure 11. Bus Write Timing Characteristics
(Write Information into PIA)

Figure 12. Peripheral Data Hold Time
(Read Mode)

2'OV~

PAO.PAI
PBD·PBI _ _ _ _--"0.~8V

~D.8~

ENABLE

877269

_ _ _ __

877270

Figure 13. Peripheral Control Output Pulse Width

Figure 14. Interrupt Pulse Width and "iROResponse

PWI
CA1,C A2
CB1,C B2

2.DV

D.8V

CA2
CB2
iRiJij

'RS3·

* Assumes I nterrupt Enable Bits are set.
877271

877272

Figure 15. Bus Timing Test Loads

LOAD B

(iRO ONLY)
S.DV

LOAOA
(00·071
5.0V

RLo2.5k
TEST POINT

O-.....~rl_--i ~RM~~~;~

TEST POINT

0-----.

C
13DpF
MMOIDDD
OR EOUIV

LOAD C
(CMOS LOAD)

TEST POINT

O----I-.~

LOAD 0
(PAD·PAl, PBD·PBI, CA2, CB2)

,.,

TEST POINT

O-......---2 and
VMA (Valid Memory Address).
Chip Selection and Addressing - The minimum system
configuration permits direct selection of the ROM,

RAM, ACIA and PIA without the use of special TTL
select logic. This is accomplished by simply wiring the
address lines A13, A14 to the Enable or chip select
lines on the memories and PIA. This permits the devices to be addressed as follows:
Device

A14

A13

Hex Addresses

RAM
PIA
ROM

a
a

0000-007F
2004 -2007 (Registers)
6000-63FF

1
1

Other addressing schemes can be utilized which use
any combination of two of the lines A10 through
A14 for chip selection.
Peripheral Control - All control and timing for the
peripherals that are connected to the PIA is accomplished by software routines under the control of the
MPU.

Figure 16. Minimum System Implementation

A13
A14
S68A21
S68B21
RSO·RSI

MPU
S6821
S68A21
S68821

CSO
CSI

CS2
R/W

RIW
PBO·PB7
CBl

TRIT

DATA BUS 00·07

817258

3.51

00·07

CB2

IRUA

IRUB

l '"

PERI:'~.7RAL

S6821/S68A21/S68B21

Expanded Block Diagram
IROA 38
INTERRUPT STATUS
CONTROL A

39 CA2

DO 33
01 32
02 31
03 30
04 29

DATA DIRECTION
REGISTER A
(DORA)

DATA BUS
BUFFERS
(oBB)

05 28
06 27
07 26

2 PAO
OUTPUT
REGISTER A
(ORA)

3 PAl
4 PA2
PERIPHERAL
INTERFACE

(/)

BUS INPUT
REGISTER
(BIR)

::>

'"
>-

5 PA3
6 PA4
7 PA5

::>
Cl.

8 PA6

PA7
VCC =PIN 20
GNo = PIN 1

10 PBO
OUTPUT
REGISTER B
(ORB)

CSO 22

11 PB 1
12 PB2
PERIPHERAL
INTERFACE
B

CSI 24
CS2 23
RSO 36
RSI 35

13 PB3
14 PB4
15 PB5

CHIP
SELECT
AND
R/W
CONTROL

16 PB6
17 PB7

R/W 21
ENABLE 25
RESET 34
CONTROL
REGISTER B
(CRB)

DATA DIRECTION
REGISTER B
(ooRB)

18 CBl
INTERRUPT STATUS
CONTR OL B

IROB 37

877248

3.52

19 CB2

ADVANCED PRODUCT DESCRIPTION

56840

PROGRAMMABLE TIMER
Features

General Description

D Operates from a Single 5 Volt Power Supply

The S6840 is a programmable subsystem component
of the S6800 'family designed to provide variable
system time intervals.

D Fully TTL Compatible
D

Single System Clock Required (Enable)
D Selectable Prescaler on Timer 3 Capable of a
4MHz Input
D Programmable Interrupts (IRQ) Output to
MPU
D Readable Down Counter Indicates Counts to
Go to Time-Out
D Selectable Gating for Frequency or PulseWidth Comparison
D RESET Input
D Three Asynchronous External Clock and Gate/
Trigger Inputs Internally Synchronized
D Three Maskable Outputs

The S6840 has three 16-bit binary counters, three
corresponding control registers and a status register.
These counters are under software control and may
be used to cause system interrupts and/or generate
output signals. The 86840 may be utilized for such
tasks as frequency measurements, event counting,
interval measuring and similar tasks. The device may
be used for square wave generation, gated delay signals, single pulses of controlled duration, and pulse
width modulation as well as system interrupts.
Pin Configuration

Block Diagram

RIW

RSO

RS1

RS2

ill

ENABLE
(SYSTEM,,2f

CS1

Vss

iii

...cc
'"
Q

ii3 C3

ill C2

3.53

S6840

RESET

iRii

20
19

RSo

RS1

RS2

ENABLE

RiW

CS1

Vee

ill

I
:
-:

56840

Absolute Maximum Ratings

Supply Voltage Vee ........................................................ - 0.3 to + 7.0V
Input Voltage VIN .......................................................... - 0.3 to +7.0V
Operating Temperature Range TA ............................................... 0° C to + 70° C
Storage Temperature Range Tstg ............................................. -55°C to +150°C
Thermal Resistance eJA ......................................................... 82.5° CjW
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit.

Electrical Characteristics (Vee = 5.0V ± 5%, VSS = 0, TA = O°C to +70°C unless otherwise noted)

Symbol
Vrn
VIL
lIN
ITSI
VOH

Characteristic
Input High Voltage
Input Low Voltage
In pu t Leakage Curren t
Three-State (Off State)
Input Current
Output High Voltage

Min.

DO-D7
DO-D7
Other Outputs

VOL

Typ.

Max.

Unit

Condition

1.0

Vee
Vss +0.8
2.5

V
fJ.A
fJ.A

VIN=O to 5.25V

2.0

fJ.A
V

Vss +2.0
Vss - 0.3

ILOAD= -205fJ.A
ILOAD= -20 0 fJ. A

Vss +2.4
Vss +2.4

Output Low Voltage

V
DO-D7
01 - 03, IRQ

ILOH
PD
CIN

COUT

Output Leakage Current
(Off State)
Power Dissipation
Inpu t Capacitance

VIN = 0.4 to 2.4 V

ILOAD = 1.6mA
ILOAD = 3.2mA

Vss +0.4
Vss +0.4

IRQ

1.0

10
550

DO-D7
All Others

12.5
7.5

IRQ
01,02,03

5.0
10

Output Capacitance

fJ.A
mW
pF

VOH = 2.4V
VIN=O, TA=25°C,
f = 1.0MHz

pF
VIN =0, TA=25° C,
f = 1.0MHz

Bus Timing Characteristics

Read (See Figures 1 and 7)
Symbol

Characteristic

Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and RjW valid to enable
positive transition
Data Delay Time
tDDR
Data Hold Time
tH
Address Hold Time
tAH
tEr, tEf Rise and Fall Time for Enable input

teyeE
PWEH
PWEL
tAS

3.54

Min.

Max.

Unit

1.0
0.45
0.43

1.0
4.5

fJ.s
fJ.s
fJ.s

160
320
10
10
25

ns
ns
ns
ns
ns

Condition

56840

Bus Timing Characteristics (Continued)
Write (See Figures 2 and 7)
Symbol

Characteris tic

Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and RjW valid to enable
positive transition
Data Setup Time
tDSW
Data Hold Time
tH
Address Hold Time
tAH
tEr, tEf Rise and Fall Time for Enable input
tCYCE
PWEH
PWEL
tAS

Min.

Max.

Unit

1.0
0.45
0.43

10
4.5

/lS

Condition

/lS
/lS

160
195
10
10
25

ns
ns
ns
ns
ns

Max.

Unit

1.0*

/lS

AC Operating Characteristics
Symbol

Characteristic

Min.

t r , tf

Input Rise and Fall Times

PWL

C, G and Reset
Input Pulse Width Low (Figure 3)
C, G and Reset
Input Pulse Width High (Figure 4)

PWH

C,G
tsu

thd

tco
tcm
tcmos
tIR

tCYCE +tsu +thd

200

Input Setup Time (Figure 5)
(Synchronous Mode) C, G and Reset
C3 8-8 Prescaler Mode only)
Input Hold Time (Figure 5)
(Synchronous Mode) C, G and Reset
C3 8-8 Prescaler Mode only)
Load A
TTL
Load C
MOS
Load C
CMOS
Interrupt Release Time

700
450
2.0
1.6

*tr and tf ,,;; 1 x Pulse Width or 1.0I1S, whichever is smaller.

3.55

ns
ns
/lS
/lS

Condition

VOH=2.4V
VOH=2.4V
VOH=0.7VDD

56840

Figure 1. Bus Read Timing Characteristics
(Read Information from PTM)

Figure 2. Bus Write Timing Characteristics
(Write Information into PTM)

__----tcvcE------1~
~---tcy'E------I~

ENABLE

RS,

ENABLE

CS, R/W

RS,

CS, RNi

DATA BUS
DATA BUS

Figure 3. Input Pulse Width Low

Figure 4. Input Pulse Width High

Figure 5. Iinput Setup and Hold Times

Figure 6. Output Delay

ENABLE

t.,

-1'.

2.0V
~Gl·G3

o.sv

01·03

RESET

3.56

\~-

56840

Figure 7. fRQ Release Time

T~'"),,,

ENABLE

iRli

Figure 8. Bus Timing Test Loads

LOAO A
(00-071

LOAO B
(01,02,031

TEST POINT

= 2_5k

MMD6150
OR EUUIV_

L..ol

Vee OF DEVICE UNDER TEST

5_0V

f""'II

TEST POINT

......

1Uk

40pF

,Ir
-

-=:?

MMD6150
OR EUUIV_

l""'Ir

130pF ;:~

.>
~

1Uk

MM07000
OR EUUIV_

~Ir

"*"

--E="

= 1.25k

MMD7000
OR EUUIV_

LOAD C

(iRli ONLYI

5_0V
LOAD 0
(CMOS LOADI
3k

nm""l

TEST POINT

100pF

I~'

-±

3.57

56840

Device Operation

The three timers in the S6840 may be independently
programmed to operate in modes which fit a wide
variety of applications. The device is fully bus compatible with S6800 systems and is accessed by load and
store operations from the MPU in much the same
manner as a memory device. In a typical application,
a Timer will be loaded by first storing two bytes of
data into an associated Counter Latch. This data is
then transferred into the counter via a Counter
Initialization cycle. The counter decrements on each
subsequent clock period which may be an external
clock or Enable (System ¢ 2) until one of several
predetermined conditions causes it to halt or recycle.
The timers are thus programmable, cyclic in nature,
controllable by external inputs or the MPU program,
and accessible by the MPU at any time.
Bus Interface

The Programmable Timer Module (PTM) interfaces to
the S6800 Bus with an eight- bit bidirectional data bus,
two Chip Select lines, a Read/Write line, an Enable
(System 2) pulses. Three Enable periods are used to
store operations of the S6800 family microprocessors synchronize and process the external clock. The
(STS and STX) transfer data in the order required by fourth Enable pulse decrements the internal counter.
the PTM. A Store Index Register Instruction, for This does not affect the input frequency, it merely
example, results in the MSB of the X register being creates a delay between a clock input transition and
transferred to the selected address, then the LSB of internal recognition of that transition by the PTM.
the X register being written into the next higher loca- All references to C inputs in this document relate to
tion. Thus, either the index register or stack pointer internal recognition of the input transition. Note that
may be transferred directly into a selected counter a clock high or low level which does not meet setup
and hold time specifications may require an additional
latch with a single instruction.
Enable pulse for recognition. When observing recurring
A logic zero at the Reset input also initiatizes the events, a lack of synchronization will result in "jitter"
counter latches. In this case, all latches will assume a being observed on the output of the PTM when using
maximum count of 65,536 10 • It is important to note asynchronous clocks and gate input signals. There are
that an Internal Reset (Bit zero of Control Register two types of jitter. "System jitter" is the result of the
1 Set) has no effect on the counter latches.
input signals being out of synchronization with the
Enable (Systemrf> 2), permitting signals with marginal
setup and hold time to be recognized by either the
Counter Initialization
bit time nearest the input transition or the subseCounter Initialization is defined as the transfer of quent bit time.
data from the latches to the counter with subsequent
clearing of the Individual Interrupt Flag associated
with the counter. Counter Initialization always occurs
when a reset condition (Reset = 0 or CR10 = 1) is
recognized. It can also occur - depending on Timer
Mode - with a Write Timer Latches command or
recognition of a negative transition of the Gate input.
Counter recycling or re-initialization occurs when a
negative transition of the clock input is recognized
after the counter has reached an all-zero state. In
this case,· data is transferred from the Latches to the
Counter.
"Input jitter" can be as great as the time between
input signal negative going transitions plus the system
jitter, if the first transition is recognized during one
Asynchronous Input/Output Lines
system cycle, and not recognized. the next cycle, or
Each of the three timers within the PTM has external vice versa.

3.62

56840

Asynchronous Input/Output Lines (Continued)
(VOL) regardless of the operating mode.

The Continuous and Single-Shot Timer Modes are the
only ones for which output response is defined.
Signals appear at the outputs (unless CRX7 = 0)
during Frequency and Pulse Width comparison modes,
but the actual waveform is not predictable in typical
applications.

ENABLE
INPUT

5-+-----,
PTM
RECOGNIZES
THIS EOGE

---L..._-?~

PTM

External clock input C3 represents a special case
when Timer 'II 3 is programmed to utilize its optional
-+- 8 prescaler mode. The maximum input frequency
and allowable duty cycles for this case are specified
under the AC Operating Characteristics. The output
of the -7- 8 prescaler is treated in the same manner as
the previously discussed clock inputs. That is, it is
clocked into the counter by Enable pulses, is recognized on the fourth Enable pulse (provided setup and
hold time requirements are met), and must produce
an output pulse at least as wide as the sum of an
Enable period, setup, and hold times.
Gate Inputs (G1, G2, G3) - Input pins G1, G2, and
G3 accept asynchronous TTL-compatible signals which
are used as triggers or clock gating functions to
Timers 1, 2, and 3, respectively. The gating inputs are
clocked into the PTM by the Enable (System ¢2)
signal in the same manner as the previously discussed
clock inputs. That is, a Gate transition is recognized
by the PTM on the fourth Enable pulse (provided
setup and hold time requirements are met), and the
high or low levels of the Gate input must be stable for
at least one system clock period plus the sum of setup
and hold times. All references to G transition in this
document relate to internal recognition of the input
transition.
The Gate inputs of all timers directly affect the
internal 16-bit counter. The operation of G3 is therefore independent of the-7- 8 prescaler selection.
Timer Outputs (01, 02, 03) - Timer outputs 01,
02, and 03 are capable of driving up to two TTL
loads and produce a defined output waveform for
either Continuous or Single-Shot Timer modes. Output waveform definition is accomplished by selecting
either Single 16-bit or Dual 8-bit operating modes.
The single 16-bit mode will produce a square-wave
output in the continuous timer mode and will
produce a single pulse in the Single-Shot Timer
mode. The Dual 8-bit mode will produce a variable
duty cycle pulse in both the continuous and single
shot Timer modes. One bit of each Control Register
(CRX7) is used to enable the corresponding output.
If this bit is cleared, the output will remain low

Timer Operating Modes

The S6840 has been designed to operate effectively
in a wide variety of applications. This is accomplished
by using three bits of each control register (CRX3,
CRX4, and CRX5) to define different operating
modes of the Timers. These modes are outlined in
Table 3.
Table 3. Operating Modes
CONTROL REGISTER
CRX3

CRX4

CRX5

TIMER OPERATING MODE

CONTINUOUS

SINGLE-SHOT

FREQUENCY COMPARISON

PULSE WIDTH COMPARISON

*Defines Additional Timer Functions

In addition to the four timer modes in Table 3, the
remaining control register bit is used to modify counter
initialization and enabling or interrupt conditions.
Continuous Operating Mode (Table 4) - Any of the
timers in the PTM may be programmed to operate in
a continuous mode by writing zeroes into bits 3 and 5
of the corresponding control register. Assuming that
the timer output is enabled (CRX7 = 1), either a
square wave or a variable duty cycle waveform will
be generated at the Timer Output, ox. The type of
output is selected via Control Register Bit 2.
Either a Timer Reset (CR10 = 1 or External Reset =
0) condition or internal recognition of a negative
transition of the Gate input results in Counter Intialization. A Write Timer Latches command can be
selected as a Counter Initialization signal by clearing
CRX4.
In the dual 8-bit mode (CRX2 = 1) [Refer to the
example in Figure 10] the MSB decrements once for
every full countdown of the LSB + 1. When the LSB
= 0, the MSB is unchanged; on the next clock pulse
the LSB is reset to the count in the LSB Latches and

3.63

S6840

Table 4. Continuous Operating Modes

CONTINUOUS MODE
(CRX3 =0, CRX5 = 0)
CONTROL REGISTER
CRX2

G-lW
R
N
L
M
T
to
TO

CRX4

INITIALIZATION/OUTPUT WAVEFORMS
COUNTER INITIALIZATION

G-l- + W + R

G-l- + R

G-l- +W + R

G-l-+ R

*TIMER OUTPUT (OX) (CRX7

= 1)

(N + 1)(TI - r - ( N + I ) ( T l T ( N + I)(TI---,

,-VOH
VOL

~(L+I)(M+1)(T)--t---(L+I)(M+I)(TI~

~(L)(TI~

-I

-VOH

~VOl

(L)(TI

NEGATIVE TRANSITION 0 F GATE INPUT.
WRITE TIMER LATCHES COMMAND.
TIMER RESET (CRlO = lOR EXTERNAL RESET =0).
16-BIT NUMBER IN COUNTER LATCH.
8-BIT NUMBER IN LSB COUNTER LATCH.
8-BIT NUMBER IN MSB COUNTER LATCH.
CLOCK INPUT NEGATIVE TRANSITIONS TO COUNTER.
COUNTER INITIALIZATION CYCLE.
COUNTER TIME OUT (ALL ZERO CONDITION).

*AII time intervals shown above assume that the Gate (G) and Clock (C) signals are synchronized to enable (System ¢2)
with the specified setup and hold time requirements.
Figure 9. Timer Output Waveform Example
(Continuous Dual 8-Bit Mode using Internal Enable)
'TIME
OUT

EXAMPLE: CONTENTS OF MSB = 03 = M
CONTENTS OF LSB = 04 = L

M(L+II+I
ALGEBRAIC EXPRESSION
03(04+11+1 =
16 ENABLES

- - - - - - l I - - - - 2.4V
------H----O.4V
COUNTER OUTPUT

ENABLE
(SYSTEM¢21

I+L
I
I+l
I
I+L
I
5ENABLE-I--5ENABlE-I--5ENABLE~
PULSES

PULSES

1+ L

J--- 5 ENABLE

I
I

~-'------:--I- . ; - - - - ( M + I)(L+1)

i ~

(M + I)(L + II = PERIOD
M(L + II + I = LOW PORTION OF PERIOD
L = PULSE WIDTH
·PRESET LSB AND MSB TO RESPECTIVE LATCHES ON THE NEGATIVE TRANSITION OF THE ENABLE
··PRESET LSB TO LSB LATCHES AND DECREMENT MSB BY ONE ON THE NEGATIVE TRANSITION OF THE ENABLE

3.64

PULSES

ALGEBRAIC EXPRESSION
(04 + 1)(03 + II = 20 ENABLE UR
EXTERNAL CLOCK PULSES

I
I
I
~

S6840

Timer Operating Modes (Continued)

the MSB is decremented by 1 (one). The output, if
enabled, remains low during and after initialization
and will remain low until the counter MSB is all zeroes.
The output remains high until both the LSB and MSB
of the counter are all zeroes. At the beginning of the
next clock pulse the defined Time Out (TO) will
occur and the output will go low. In the normal 16-bit
mode the period of the output of the example in
Figure 9 would span 1546 clock pulses as opposed to
the 20 clock pulses using the Dual 8-bit mode.
The counter is enabled by an absence of a Timer
Reset condition and a logic zero at the Gate input.
The counter will then decrement on the first clock
signal recognized during or after the counter initialization cycle. It continues to decrement on each clock
signal so long as G remains low and no reset condition exists. A Counter Time Out (the first clock after
all counter bits = 0) results in the Individual Interrupt
Flag being set and re-initialization of the counter.
A special condition exists for the dual 8-bit mode
(CRX2 = 1) if L = O. In this case, the counter will
revert to a mode similar to the single 16-bit mode,
except Time Out occurs after M + 1 clock pUlses. The
output, if enabled, goes low during the Counter Initialization cycle and reverses state at each Time Out.
The counter remains cyclical (is re-initialized at each
Time Out) and the Individual Interrupt Flag is set
when Time Out occurs. If M = L = 0, the internal
counters do not change, but the output toggles at a
rate of 1h the clock frequency.
The discussion of the Continuous Mode has assumed
that the application requires an output signal. It
should be noted that the Timer operates in the same
manner with the output disabled (CRX7 = 0). A
Read Timer Counter command is valid regardless of
the state of CRX7 .
Single-Shot Timer Mode - This mode is identical to
the Continuous Mode with three exceptions. The
first of these is obvious from the name - the output
returns to a low level after the initial Time Out and
remains low until another Counter Initialization
cycle occurs. The waveforms available are shown in
Table 5.
As indicated in Table 5, the internal counting mechanism remains cyclical in the Single-Shot Mode. Each
Time Out of the counter results in the setting of an
Individual Interrupt Flag and re-initialization of the
counter.
The second major difference between the Single-Shot
and Continuous modes is that the internal counter

enable is not dependent on the Gate input level
remaining in the low state for the Single-Shot mode.
Another special condition is introduced in the SingleShot mode. If L = M = 0 (Dual8-bit) or N = 0 (Single
16-bit), the output goes low on the first clock received
during or after Counter Initialization. The output
remains low until the Operating Mode is changed or
non-zero data is written into the Counter Latches.
Time Outs continue to occur at the end of each
clock period.
The three differences between Single-Shot and
Continuous Timer Modes can be summarized as
attributes of the Single-Shot mode:
1. Output is enabled for only one pulse until it
is reinitialized.

2. Counter Enable is independent of Gate.
3. L = M = 0 or N = 0 disables output.
Aside from these differences, the two modes are
identical.
Time Interval Modes - The Time Interval Modes are
provided for those applications which require more
flexibility of interrupt generation and Counter
Initialization. Individual Interrupt Flags are set in
these modes as a function of both Counter Time Out
and transitions of the Gate input. Counter Initialization is also affected by Interrupt Flag status.
The output signal is not defined in any of these modes,
but the counter does operate in either Single 16-bit or
Dual 8-bit modes as programmed by CRX2. Other
features of the Time Interval Modes are outlined in
Table 6.
Frequency Comparison or Period Measurement Mode
(CRX3 = 1, CRX4 = 0) - The Frequency Comparison
Mode with CRX5 = 1 is straightforward. If Time Out
occurs prior to the first negative transition of the
Gate input after a Counter Initialization cycle, an
Individual Interrupt Flag is set. The counter is disabled,
and a Counter Initialization cycle cannot begin until
the interrupt flag is cleared and a negative transition
on G is detected.
If CRX5 = 0, as shown in Table 6 and Table 7, an
interrupt is generated if Gate input returns low prior
to a Time Out. If Counter Time-Out occurs first, the
counter is recycled and continues to decrement. A
bit is set within the timer on the initial Time Out
which precludes further individual interrupt generation until a new Counter Initialization cycle has been
completed. When this internal bit is set, a negative

3.65

S6840

Timer Operating Modes (Continued)

transition of the Gate input starts a new Counter
Initialization cycle. (The condition of G t • T • TO
is satisfied, since a Time Out has occurred and no
individual Interrupt has been generated.)
Any of the timers within the PTM may be programmed

to compare the period of a pulse (giving the frequency
after calculations) at the Gate input with the time
period required for Counter Time-Out. A negative
transition of the Gate input enables the counter and
starts a Counter Initialization cycle - provided that
other conditions as noted in Table 7 are satisfied.
The counter decrements on each clock signal recognized during or after Counter Initialization until an
Interrupt is generated, a Write Timer Latches command is issued, or a Timer Reset condition occurs. It
can be seen from Table 7 that an interrupt condition
will be generated if CRX5 = and the period of the
pulse (single pulse or measured separately repetitive
pulses) at the Gate input is less than the Counter
Time Out period. If CRX5 = 1, an interrupt is generated if the reverse is true.

Assume now with CRX5 = 1 that a Counter Initialization has occurred and that the Gate input has
returned low prior to Counter Time Out. Since there

is no Individual Interrupt Flag generated, this automatically starts a new Counter Initialization Cycle.
The process will continue with frequency comparison
being performed on each Gate input cycle until the
mode is changed, or a cycle is determined to be
above the predetermined limit.

Pulse Width Comparison Mode (CRX3 = 1, CRX4 = 1)
This mode is similar to the Frequency Comparison
Mode except for a positive, rather than negative,
transition of the Gate input terminates the count.
With CRX5 = 0, an Individual Interrupt Flag will be
generated if the zero level pulse applied to the Gate
input is less than the time period required for Counter
Time Out. With CRX5 = 1, the interrupt is generated
when the reverse condition is true.
As can be seen in Table 8~ a positive transition of the
Gate input disables the counter. With CRX5 = 0,
it is therefore possible to directly obtain the width of
any pulse causing an interrupt. Similar data for other
Time Interval Modes and conditions can be obtained,
if two sections of the PTM are dedicated to the
purpose.

Table 5. Single-Shot Operating Modes

SINGLE-SHOT OPERATING MODES
(CRX3 = 0, CRX7 = 1, CRX5 = 1)
CONTROL REGISTER

INITIALIZATION/OUTPUT WAVEFORMS

CRX2

CRX4

COUNTER INITIALIZATION

Gt + W + R

Gt + R

Gt + W + R

Gt + R

TIMER OUTPUT (OX)

r-F

(N + lilT)
f.--(N)(T)

==:oj"

(N + 1liT)

r"''''"'''"'~'''''''''''''l
II
- - , (LilT)

Symbols are as defined in Table 4.

3.66

56840

Table 6. Time Interval Modes
CRX3 = 1
CRX4

CRX5

APPLICATION

CONDITION FOR SETTING INDIVIDUAL INTERRUPT FLAG

FREQUENCY COMPARISON

INTERRUPT GENERATED IF GATE INPUT PERIOD (l/F) IS LESS THAN
COUNTER TIME OUT (TO)

FREQUENCY COMPARISON

INTERRUPT GENERATED IF GATE INPUT PERIOD (1/F) IS GREATER
THAN COUNTER TIME OUT (TO)

PULSE WIDTH COMPARISON

INTERRUPT GENERATED IF GATE INPUT "DOWN TIME" IS LESS
THAN COUNTER TIME OUT (TO)

PULSE WIDTH COMPARISON

INTERRUPT GENERATED IF GATE INPUT "DOWN TIME" IS GREATER
THAN COUNTER TIME OUT (TO)

Table 7. Frequency Comparison Mode
CRX3 = 1, CRX4 =0
CONTROL REG
BIT 5 (CRX5)

COUNTER
INITIALIZATION

COUNTER ENABLE
FLIP·FLOP SET (CE)

COUNTER ENABLE
FlIP·FLOP RESET (CE)

INTERRUPT FLAG
SET (1)

Gt-T-(CE+TO-CE)+R

Gt-W-R-T

W+ R + 1

G t BEFORE TO

Gt-I+R

Gt-W-R-T

W+ R+ 1

TO BEFORE G t

T represents the interrupt for a given timer.
Table 8. Pulse Width Comparison Mode
CRX3

CRX4 = 1

CONTROL REG
BIT 5 (CRX5)

COUNTER
INITIALIZATION

COUNTER ENABLE
FLIP·FLOP SET (CE)

COUNTER ENABLE
FlIP·FLOP RESET (CE)

INTERRUPT FLAG
SET (1)

Gt-T+R

Gt-W-R-T

w+R+T+G

G t BEFORE TO

Gt-T+R

Gt-W-R-T

w+R+T+G

TOBEFOREGt

Package Dimensions
/PIN , IDENTIFIER

020
016
1.425
MAX

o-!-oo
I

065
.050

0.020
00[5

I
a090MIN --

0.590
0480

O.020MIN----r--_+__ 0.200 MAX

f--

g:~~~---t

BEND

.555
535

090
MIN

.020
MIN

15 MAX

"'I

.200

R
I 15° MAX

---1;'-0.010

28·Pin Ceramic Package

:1,

28·Pin Plastic Package

3.67

ADVANCED PRODUCT DESCRIPTION

56846
ROM-I/O-TIMER
Features

General Description

o
o

The 86846 combination chip provides the means, in
conjunction with the 86802, to develop a basic 2-chip
microcomputer system. The 86846 consists of 2048
bytes of mask-programmable ROM, an 8-bit bidirectional data port with control lines, and a 16-bit programmable timer-counter.

2048x8-Bit Bytes of Mask-Programmable ROM
8-Bit Bidirectional Data Port for Parallel
Interface Plus Two Control Lines

Programmable Interval Timer-Counter
Functions

Programmable I/O Peripheral Data, Control
and Direction Registers

Compatible with the Complete S6800 Microcomputer Product Family

o
o

TTL- Compatible Data and Peripheral Lines
Single 5 Volt Power Supply

This device is capable of interfacing with the 86802
(basic 86800, clock and 128 bytes of RAM) as well as
the 86800 if desired. No external logic is required to
interface with most peripheral devices.
The 86846 combination chip may be partitioned into
three functional operating sections: programmed storage, timer-counter functions, and a parallel I/O port.

Pin Configuration

Block Diagram

40
39

DO
01
02
03
04
05
06
07

38
37
81DIRECTIDNAl DATA

8rU~S_ _ _ _--,

36
35
34
COMPOSITE
STATUS
REGISTER

CSO*
CS1*
AD
Al
A2
A3
A3
A5
A6
A7
A8
A9
Al0
All

33
32

CPl

CP2

VSS_
VCC _

PPO
PPl
PP2
PP3
PP4
PP5
PP6
PP7

2048
8YTE
ROM

*MASK PROGRAMMABLE

3.68

56846

General Description (Continued)

Programmed Storage
The mask-programmable ROM section is similar to
other AMI ROM products. The ROM is organized in
a 2048 by 8 -bit array to provide read only storage
for a minimum microcomputer system. Two maskprogrammable chip selects are available for user
definition.
Address inputs AO-AlO allow any of the 2048 bytes
of ROM to be uniquely addressed. Internal registers
associated with the I/O functions may be selected
with AO, Al and A2. Bidirectional data lines (DO-D7)
allow the transfer of data between the MPU and the
S6846.
Timer-Counter Functions
Under software control this l6-bit binary counter
may be programmed to count events, measure frequencies and time intervals, or similar tasks_ It may
also be used for square wave generation, single pulses
of controlled duration, and gated delayed signals. Interrupts may be generated from a number of conditions selectable by software programming.
The timer-counter control register allows control of

the interrupt enables, output enables, and selection of
an internal or external clock source. Input pin CTC
(counter-timer clock) will accept an asynchronous
pulse to be used as a clock to decrement the internal
register for the counter-timer. If the divide- by- 8
prescaler is used, the maximum clock rate can be four
times the master clock frequency with a maximum of
4 MHz. Gate input (CTG) accepts an asynchronous
TTL-compatible signal which may be used as a trigger
or gating function to the counter-timer. A countertimer output (CTO) is also available and is under software control via selected bits in the timer- counter control register. This mode of operation is dependent on
the control register, the gate input, and the external
clock.
Parallel I/O Port
The parallel bidirectional I/O port has functional
operational characteristics similar to the B port on the
S682l PIA. This includes 8 bidirectional data lines
and two handshake control signals. The control and
operation of these lines are completely software
programmable.
The interrupt input (CPl) will set the interrupt flags
of the peripheral control register. The peripheral control (CP2) may be programmed to act as an interrupt
input or as a peripheral control output.

Figu re 1. Typical Microcomputer

S6846
ROM, liD, TIMER

COUNTERI \
TIMER 110

STANDBY
VCC

Vee

VCC

fRO
MR
VMA

CSO .....- ' - " " - ' - - - - - 1 VMA
2K BYTES ROM
10110 LINES
J LINES TIMER

S6B02
MPU
12B BYTE
RAM
CLOCK
00-07

RIW

PARALLEL 110

VCC

RES
HALT
RE

NMi
SA
XTAL

D
CONTROL

CP2
CP1

AO-A15

I-_----._ _.....J

SYSTEM EXPANSION
IF REaUIREO

3.69

XTAL

86846

Absolute Maximum Ratings

-0.3Vdc to +7.0Vdc
Supply Voltage
-0.3Vdc to +7.0Vdc
Input Voltage
Operating Temperature Range ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to +70 e
Storage Temperature Range ................................................ -55°e to +150 e
Thermal Resistance .............................................................. 70° e/w
0

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields: however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high·
impedance circuit.

Electrical Characteristics (Vee
Symbol

= 5.0V ± 5%, Vss = 0, TA = O°C to +70°C unless otherwise noted.)

Parameter

Min.

Input High Voltage

All Inputs

VIL

Input Low Voltage

All Inputs

VOS

Clock Overshoot/Undershoot - Input High Level
- Input Low Level

lin

Input Leakage Current

ITSI

Three·State (Off State) Input Current

VOH

Output High Voltage

VIH

IOL

Unit

VCC

Vdc

VSS -0.3

VSS + 0.8

Vdc

Vee + 0.5
VSS + 0.5

Vdc

1.0

2.5
100

,uAdc

2.0

10
100

,uAdc

00·07
PPO .PP7, CR2
VSS + 2.4
Vss + 2.4
VSS + 2.4

VSS + 0.4
VSS+O.4

Output Leakage Current (Off State)

Cin

Capacitance

-205
-200
-1.0

00·07
Other Outputs

1.6
3.2

-10

mAOC

IRQ

,uAdc

1000

20
12.5

PPO·PP7, CP2, CTO

5.0
10

1.0

MHz

Frequency of Operation

0.1

tcycE

Clock Timing
Cycle Time

1.0

,us

IlS

tIR

Interrupt Release

ILoad
ILoad

-205,uAdc,
-145,uAdc,
-100,uAdc

1.6mAdc
3.2mAdc

2.4Vdc

Vo ~ 1.5Vdc, the current
for driving other than TTL,
e.g., Darlington Base

1.6

3.70

VOL

OAVdc

VOH

2.4Vdc

Yin ~ 0, TA ~ 25°C,
f ~ 1.0MHz

10
7.5

Reset Low Time

VOH

PPO·PP7, CP2
AO.A10,R/W,Reset,CSO,CS1,CP1,CTC,CTG
IRQ

tRL

ILoad
ILoad
ILoad

mAdc

00·07

Cout

0 to 5.25Vdc

,uAdc
00·07
Other Outputs
CP2, PPO·PP7

Output Low Current (Sinking)

Power Oissipation

Vdc

Output High Current (Sourcing)

ILOH

Yin

Yin 0.4 to 2.4Vdc

Vdc

Output Low Voltage

Conditions

Vdc

00·07
Other Outputs
IOH

Max.

Vee -0.5
VSS -0.5

R/W, Reset, CSO, CS1
CP1, CTG, CTC, E, AO·All

00·07
CP2, PPO ·PP7
Other Outputs
VOL

Typ.

VSS + 2.0

,us

Read/Write Timing

Typ.

Symbol

Parameter

Min.

PWEL

Enable Pulse Width, Low

430

Max.

PWEH

Enable Pulse Width, High

430

tAS

Set Up Time (Address CSO, CS1, R/W)

160

tDDR

Data Delay Time

Data Hold Time

tAH

Address Hold Time

tEf, tEr

Rise and Fall Time

tDSW

Data Set Up Time

320

25
195

Unit

Conditions

ns
ns

Bus Timing

Peripheral I/O Lines
Symbol

Parameter

Min.

tPDSU

Peripheral Data Setup

200

Typ.

Max.

Unit

tPr, tpc

Rise and Fall Times CP1, CP2

1.0

Il S

tCP2

Delay Time E to CP2 Fall

1.0

IlS

tDC

Delay Time I/O Data. CP2 Fall

tRSl

Delay Time E to CP2 Rise

1.0

IlS

tRS2

Delay Time CP1 to CP2 Rise

2.0

IlS

tpDW

Peripheral Data Delay

1.0

Il S

100

Il S

Timer- Counter Lines
tCR, tCF

Input Rise and Fall Time CTC and CTG

tPWH

Input Pulse Width High
(Asynchronous Mode)

tcyc + 250

tPWL

Input Pulse Width Low
(Asynchronous Mode)

tcyc + 250

tsu

Input Setup Time
(Synchronous Mode)

200

thd

Input Hold Time
(Synchronous Mode)

tCTO

Output Delay

1.0

3.71

IlS

Conditions

56846

Figure 2. Bus Read Timing
(Read Information from S6846)

Figure 3. Bus Write Timing
(Write Information from MPU)

! - . - - - t c y c ------I~I

A/W, A, CS

AM, A, CS

DATA BUS

Figure 4. Peripheral Data and CP2 Delay
(Control Mode PCR5 = 1, PCR4 = 0, PCR3

2,OV

Figure 5. IRQ Release Time

= 1)

2,OV

O.BV

PPO·PP7

ENABLE

2.0V

CP2

Figure 6. Peripheral Port Setup Time

Figure 7. CP2 Delay Time
(PCR5 = 1, PCR4 = 0, PCR3

= 0)

2,OV

PPO·PP7

ENABLE

~2.0V

~_O'BV_t=--tPDSU--ENABLE

2.0V

CPl

\ ...._ _ _ __

CP2

3.72

'~F
.

O,4V

2.4V

56846

Figure 8. Input Pulse Widths

Figure 9. Input Setup and Hold Times
2.4V
ENA8LE

CTC or
CTG

~..:....:-----

0.8V~_ _---'I

NOTE: Thismodeisvalidonlyfof
synchronous operation.

Figure 10. Output Delay

Figure 11. Bus Timing Test Loads
LOAD A

100·07, CTO, CP2, PPO·PP7)
5.0V

ENA8LE

{.
L..

CTO

\
tCTfi

Rl = 2.5k

~'"

LOAD 8
(i"RaoNLY)

TEST POINT

0.4V

C = lJOpF for 00·07
= JOpF for CTO, CP2, PPO·PP7
R = 11.7kn for 00-07
= 24kSlfor CTO, CP2, PPO·PP7

Signal Description

Reset - The active low state of the Reset input is
used to initialize all register bits in the I/O section of
Bus Interface - The S6846 interfaces to the S6802 or the device to their proper values. (See the section on
S6800 Bus via an eight-bit bidirectional data bus, two Initialization for Reset conditons for timer and periChip Select lines, a Read/Write line, and eleven address pheral registers.)
lines. These signals, in conjunction with the S6800/
02 V:l\1A output, permit the MPU to control the S6846. Enable (¢>2) - This signal synchronized data transfer
between the MPU and the S6846. It also performs an
Bidirectional Data Bus (DO-D7) - The bidirectional equivalent synchronization function on the external
data lines (DO-D7) allow the transfer of data between clock, reset, and gate inputs of the S6846 Timer
the MPU and the S6846. The data bus output drivers section.
are three-state devices which remain in the high-impedance (Off) state except when the MPU performs Read/Write (R/W) - This signal is generated by the
an S6846 register or ROM read (R/W = I and I/O MPU and is used to control the direction of data
Registers or ROM selected).
transfer on the bidirectional data pins. A low level on
the
R/W input enables the S6846 input buffers and
Chip Select (CSO, CSI) - The CSO and CSI inputs
are,used to select the two major sections of the S6846. data is transferred to the circuit during the ¢>2 pulse
They are mask programmed to be active high or active when the,part has been selected. A high level on the
R/W input enables the output buffers and data is
low as chosen by the user.
transferred to the MPU during ¢>2 when the part is
Address Inputs (AO-AIO) - The Address Inputs allow selected.
any of the 2048 bytes of ROM to be uniquely selected
when the circuit is operating in the ROM mode. In Interrupt Request (IRQ) - The active low IRQ outthe I/O-Timer mode, address inputs AO, AI, and A2 put acts to interrupt the MPU through logic included
select the proper I/O Register, while A3 through AIO on the S6846. This output utilizes an open chain con(together with CSO and CSI) can be used as additional figuration and permits other interrupt request outputs
qualifiers in the I/O Select circuitry. (See the section from other circuits to be connected in a wire-OR
configuration.
on I/O-Timer Select for additional details.)
3.73

56846

Peripheral Data (PO-P7) - The peripheral data lines
can be individually programmed as either inputs or
outputs via the Data Direction Register. When programmed as outputs, these lines will drive two standard
TTL loads (3.2 mAl. They are also capable of sourcing
up to 1.0 mA at 1.5 Volts (Logic "I" output.)
When programmed as inputs, the output drives associated with these lines enter a three-state (high impedance) mode. Since there is no internal pull-up for
these lines, they represent a maximum 10llA load to
the circuitry driving them - regardless of logic state.
A logic zero at the Reset input forces the peripheral
data lines to the input configuration by clearing the
Data Direction Register. This allows the system designer to preclude the possibility of having a peripheral
data output connected to an external driver output
during power-up sequence.
Interrupt Input (CPl) - Peripheral input line CPl is
an input-only that sets the Interrupt Flags of the
Peripheral Control register. The active transition for
this signal is programmed by the control register for
the parallel port. CP1 may also act as a strobe for the
peripheral data register when it is used as an input
latch. Details for programming CP1 are in the section
on the parallel peripheral port.
Peripheral Control (CP2) - Peripheral Control line
CP2 may be programmed to act as an Interrupt input
or Peripheral Control output. As an input, this line
has high impedance and is compatible with standard
TTL voltage levels. As an output, it is also TTL compatible and may be used as a source of 1 mA at 1.5V
to directly drive the base of a Darlington transistor
switch. This line is programmed by the Control Register for the parallel port.
Counter Timer Output (CTO) - The Counter Timer
Output is software programmable by selected bits in
the timer counter control register. The mode of op-

eration is dependent on the Timer control register,
the gate input, and the external clock. The output is
TTL compatible.
External Clock Input (CTC) - Input pin CTC will accept asynchronous TTL voltage level signals to be
used as a clock to decrement the Timer. The high and
low levels of the external clock must be stable for at
least one system clock period plus the sum of the
setup and hold times for the inputs. The asynchronous
clock rate can vary from dc to the limit imposed by
System cp2, setup, and hold times.
The external clock input is clocked in by Enable (System cp2) pulses. Three Enable periods are used to
synchronize and process the external clock. The fourth
Enable pulse decrements the internal counter. This
does not affect the input frequency; it merely creates
a delay between a clock input transition and internal
recognition of that transition by the S6846. All references to CTC inputs in this document relate to internal
recognition of the input transition. Note that a clock
transition which does not meet setup and hold time
specifications may require an additional Enable pulse
for recognition.
When observing recurring events, a lack of synchronization will result in either "System jitter" or "Input
jitter" being observed on the output of the S6846
when using an asynchronous clock and gate input signal. "System jitter" is the result of the input signals
being out of synchronization with the system cp 2 clock
(Enable), permitting signals with marginal set-up and
hold time to be recognized by either the bit time
nearest the input transition or subsequent bit time.
"Input jitter" can be as great as the time between the
negative going transitions of the input signal plus the
system jitter if the first transition is recognized during
one system cycle, and not recognized the next cycle
or vice -versa.

Figure 12.

OUTPUT

INPUT

¢2

ill INPUT

_ _ _ _ _ _...,

RECOG.
INPUT
EITHER
HERE

---i

-------!!

'-1

LORHERE

3.74

r--

56846

Gate Input (CTG) - The input pin CTG accepts as
asynchronous TTL-compatible signal which is used as
a trigger or a clock gating function to the Timer. The
gating input is clocked into the S6846 by the Enable
(System 2) signal in the same manner as the previously
discussed clock inputs. That is, a CTG transition is
recognized on the fourth Enable pulse (provided setup and hold time requirements are met), and the high
or low levels of the CTG input must be stable for at
least one system clock period plus the sum of setup
and hold times. All references to CTG transition in
this document relate to internal recognition of the
input transition.
The CTG in pu t of the timer directly affects the in ternal
l6-bit counter. The operation of CTG is therefore
independent of the -7- 8 prescaler selection.
Functional Select Circuitry

I/O Timer Select Circuitry - Two chip select inputs
are provided with the S6846, and are programmed active high or low simultaneously with the ROM pattern.
The I/O -Timer selection can therefore be made to

correspond to anyone of the four possible state combinations of the two chip select inputs. (CSO-CSl,
CSO-CSl, CSO-CSl, or CSO-CSl)
Address lines A3, A4, and A5 are also used as 1/0Timer Select inputs. Specifically, these lines must be
at a logic zero (low) for the I/O-Timer section to be
selected. Address line A6 can also be used as a qualifier for I/O -Timer selection, as can anyone of the
four high Address lines (A 7 through Ala). A6 is unique
among these selector inputs in that it is possible to
program either the high or low state of A6 as an 1/0Timer select input.
The circuit of Figure 13 is representative of the 1/0Timer select circuitry on the S6846. The mask programmable options are represented by switches.
Internal Addressing - Seven I/O Register locations
within the S6846 combination circuit are accessible
to the MPU data bus. Selection of these registers is
controlled by AO, AI, and A2 as shown in Table l.
CSO and CSI must be in the I/O state and the proper
register address must be applied to access a particular
register. The combination status register is Read-only;
all other Registers are Read/Write.

Figure 13. I/O-Timer Select Circuitry
CSl O - -........- - - f

~.o---~

CSO O - -........- - - f

~'O----oO-...

Al0

v---~

A9 0----0
A8 0----0

A7 0 - - - - 0
'SWITCHES REPRESENT MASK PROGRAMMABLE INTERCONNECTS.

AS O - -........- - - f ~K>---oO-...

o----------------~

o-----------------~

AJ o------------------~

3.75

56846

ROM Select - The active levels of CSO and CS1 for
ROM and I/O select are a user programmable option.
Either CSO or CS1 may be programmed active high or
active low, but different codes must be used for ROM
or I/O select. CSO and CS1 are mask programmed simultaneously with the ROM pattern. The ROM Select
Circuitry is sh own in Figure 14.

Table 1. Internal Register Addresses

Registered Selected
Comb ination Status Register
Peripheral Control Register
Data Direction Register
Peripheral Data Register
Combination Status Register
Timer Control Register
Timer MSB Register
Timer LSB Register
RD MAddress

0
0

0
1

Ti mer Operation

The Timer may be programmed to operate in modes
which fit a wide variety of applications. The device is
fully bus compatible with the S6800 system, and is
accessed by Load and Store operations from the MPU.

Initialization - When the Reset input has accepted a
low signal, all registers are initialized to the Reset state.
The data direction and data registers are cleared. The
Peripheral Control Register is cleared except for bit 7
(the Reset bit). This forces the parallel port to the input mode with Interrupts disabled. To remove the
Reset condition from a parallel port, an "0" must be
written into the Peripheral Control Register bit 7
(PCR7).
The counter latches are preset to their maximal count,
the Timer control register bits are reset to zero except
for Bit 0 (CCRO) (which is set), the counter ouput is
cleared, and the counter clock disabled. This state
forces the timer counter to remain in an inactive state.
The combination status register is cleared of all interrupt flags. During timer initialization, the reset bit
(CCRO) must be cleared.
ROM - The Mask Programmable ROM section is similar in operation to other AMI ROM products. The
ROM is organized as 2048 words of 8-bits to provide
read-only storage for a minimum microcomputer sys-.
tem. The ROM is active when selected by the unique
combination of the chip select inputs.

In a typical application, the timer will be loaded by
storing two bytes of data into the counter latch. This
data is then transferred into the counter during a
Counter Initialization cycle. The counter decrements
on each subsequent clock cycle (which may be system
¢2 or an external clock) until one of several predetermined conditions causes it to halt or recycle. Thus
the timer is programmable, cyclic in nature, controllable by external inputs or MPU program, and accessible to the MPU at any time.
Counter Latch Initialization - The Timer consists of
a 16- bit addressable counter and 16 bits of addressable
latches. The function of the latches is to store a binary
equivalent of the desired count value minus one.
Counter initialization results in the transfer of the
latch contents of the counter. It should' be noted that
data transfer to the counters is always accomplished
via the latches. Thus, the counter latches may be accurately described as a 16-bit "counter initialization
data" storage register.
In some modes of operation, the initialization of the
latches will cause simultaneous counter initialization
(i.e., immediate transfer of the new latch data into
the counters). It is, therefore, necessary to insure that

Figure 14. ROM Select Circuitry

CSI o---.--~

>c>-----<:L
ROM
SELECT

CSO

o - -.......-~ ~:>-----Q
'SWITCHES REPRESENT MASK PROGRAMMABLE INTERCONNECTS,

3.76

S6846

all 16 bits of the latches are updated simultaneously.
Since the S6846 data bus is 8 bits wide, a temporary
register (MSB Buffer Register) is provided for in the
Most Significant Byte of the desired latch data. This
is a "write-only" register selected via address lines
AO, AI, and A2. Data is transferred directly from the
data bus to the MSB Buffer when the chip is selected,
R/W is low, and the timer MSB register is selected
(AO = "0"; Al = A2 = "I").
The lower 8 bits of the counter latch can also be referred to as a "write-only" register. Data Bus information will be transferred directly to the LSB of a
counter latch when the chip is selected, R/W is low and
the Timer LSB Register is selected (AO = Al = A2 =
"I"). Data from the MSB Buffer will automatically
be transferred into the Most Significant Byte of the
counter latches simultaneously with the transfer of
the Data Bus information to the Least Significant Byte
of the Counter Latch. For brevity, the conditions for
this operation will be referred to henceforth as a
"Write Timer Latches Command."

example, results in the MSB of the X register being
transferred to the selected address, then the LSB of
the X register being written into the next higher location. Thus, either the index register or stack pointer
may be transferred directly into a selected counter
latch with a single instruction.
A logic zero at the Reset input also initializes the
counter latches. All latches will assume maximum
count (65, 536) values. It is important to note that
an internal Reset (Bit zero of the Timer Control Register Set) has no effect on the counter latches.
Counter Initialization - Counter Initialization is defined as the transfer of data from the latches to the
counter with attendant clearing of the Individual
Interrupt Flag associated with the counter. Counter
Initialization always occurs when a reset condition
(external Reset = 0 or TCRO = 1) is recognized. It
can also occur (dependent on the Timer Mode) with
a Write Timer Latches command or recognition of a
negative transition of the Gate input.
Counter recycling or reinitialization occurs when a
clock input is recognized after the counter has reached
an all- zero state. In this case, data is transferred from
the Latches to the Counter, but the Interrupt Flag is
unaffected.

The S6846 has been designed to allow transfer of two
bytes of data into the counter latches from any source,
provided the MSB is transferred first. In many applications, the source of data will be an S6802 or S6800
MPU. It should therefore be noted that the 16-bit
store operations of the S6800 family of microproces- Timer Control Register - The Timer Control register
sors (STS and STX) transfer data in the order required (see Table 2) in the S6846 is used to modify timeropby the S6846. A Store Index Register instruction, for eration to suit a variety of applications. The Control

Table 2. Format for Timer/Counter Control Register

Control Register
Bit
TCRO

State

Bit Definition

Internal Reset

TCRl

Clock Source

TCR2

0
1

TCR3
TCR4
TCR5
TCR6

8 Prescaler
Enabler

Timer Enabled
Timer in Preset State
Timer uses External Clock (CTC)
Timer uses 2 System Clock
Clock is not Prescaled
Clock is Prescaled by 7 8 Counter

X
X

Operating Mode Selection

See Table 3

Timer Interrupt Enable

TCR7

State Definition

Timer Output Enable

1
3.77

IRU Masked from Timer
IRU Enabled from Timer
Counter Output (CTO) Set LOW
Counter Output Enabled

56846

Register has a unique address space (AO = 1, A1 = 0,
A2 = 1) and therefore may be written into at any time.
The least significant bit of the Control Register is used
as an Internal Reset bit. When this bit is a logic zero,
all timers are allowed to operate in the modes prescribed by the remaining bits of the control registers.

Writing "one" into Timer Control Register Bit
(TCRO) causes the counter to be preset with the contents of the counter latches, all counter clocks to be
disabled, and the timer output and interrupt flag
(Status Register) to be reset. The Counter Latch and
Control Register are undisturbed by an Internal Reset
and may be written into regardless of the state of
TCRO.
Timer Control Register Bit 1 (TCR1) is used to select
the clock source. When TCR1 = 0, the external clock
input CTC is selected, and when TCR1 = "1", the
timer uses system rp2.

TCR6 = 1, the Interrupt Flag is enabled into Bit 7 of
the Composite Status Register (Composite IRQ Bit),
which appears on the IRQ output pin.
Timer Control Register Bit 7 (TCR 7) has a special
function when the timer is in the Cascaded Single Shot
mode. (This function is explained in detail in the section describing the mode.) In all other modes, TCR7
merely acts as an output enable bit. If TCR 7 = 0, the
Counter Timer Output (CTO) is forced low. Writing
a logic one into TCR 7 enables CTO.
Timer Operating Modes - The S6846 has been designed to operate effectively in a wide variety of
applications. This is accomplished by using three bits
of the control register (TCR3, TCR4, and TCR5) to
define different operating modes of the Timer, outlined in Table 3.

Timer Control Register Bit 2 (TCR2) enables the -08 prescaler (TCR1 = "1 "). In this mode, the clock
frequency is divided by eight before being applied to
the counter. When TCR2 = "0" the clock is applied
directly to the counter.
TCR3, 4, 5 select the Timer Operating Mode, and are
discussed in the next section.
'
Timer Control Register Bit 6 (TCR6) is used to mask
or enable the Timer Interrupt Request. When TCR6 =
0, the Interrupt Flag is masked from the timer. When

Continuous Operating Mode (TCR3 = 0, TCR5 = 0)The timer may be programmed to operate in a continuous counting mode by writing zeros into bits 3
and 5 of the timer control register. Assuming that the
timer output is enabled (TCR7 = 1), a square wave will
be generated at the Timer Output CTO (see Table 4).
Either a Timer Reset (TCRO = 1 or External Reset = 0)
condition or internal recognition of a negative transition of the CTG input results in Counter Initialization.
A Write Timer Latches command can be selected as a
Counter Initialization signal by clearing TCR4.

Table 3. Operating Modes

TCR5

0
0
0
0
1
1
1
1

TCR4

0
0
1
1
0
0
1
1

TCR3

Timer Operating Mode

0
1
0
1
0
1
0
1

Continuous
Cascaded Single Shot
Continuous
Normal Single Shot
Frequency Comparison
Pulse Width Comparison

R = Reset Condition
W = Write Time Latches
T.O. = Counter Time Out

Counter Initialization

CTG++W+R
CTG+ + R
CTG+ + R
CTG+ + R
CTG+ . I . (W + T.O.) + R
CTG+ . 1+ R
CTG+ • 1+ R

CTG-l- = Negative Transition of Pin 17
CTGt = Positive Transition of Pin 17
I
= Interrupt Flag (CSRO ) = 0

3.78

Interrupt Flag Set

T.O.
T.O.
T.O.
T.O.
CTG+ Before T.O.
T.O. BeforeCTG-lCTGt Before T.O.
T.O. Before CTGt

86846

Table 4. Continuous Operating Modes

Continuous Mode
(TCR3 =0, TCR7 =1, TCR5 =0)
Control Register
Register
TCR2
TCR4

Initialization/Output Waveforms

Counter
Initialization
G+W+ R

G+R

I
,
I

*-(N + 1) (T) --+

Timer Output (2X)
*-(N + 1) (T) --+
*-(N + 1) (T)--+

I
I

T.O.

I
, - VOH
VOL

= Period of Clock input to Counter.
T
to = Counter initialization Cyele.
T.O. == Counter Time Out (All Zero Condition).

Negative transition of GATE input.

W == Write Timer Latches Command.
R == Timer Reset (TC RD == 1 or External RESET = 0)
N = 16 Bit Number in Counter Latch.

The discussion of the Continuous Mode has assumed
the application requires an output signal. It should be
noted the Timer operates in the same manner with
the output disabled (TCR 7 = 0). A Read Timer Counter
command is valid regardless of the state of TCR 7.
Normal Single-Shot Timed Mode (TCR3 = 0, TCR4 =
1, TCR5 = 1) - This mode is identical to the Continuous Mode with two exceptions. The first of these
is obvious from the name - the output returns to a
low-level after the initial Time Out and remains low
until another Counter Initialization cycle occurs. The
output waveform (CTO) is shown in Figure 15.
As indicated in Figure 15, the internal countingmechanism remains cyclical in the Single -Shot Mode.
Each Time Out of the counter results in the setting
of an Individual Interrupt Flag and reinitialization
of the counter.
The second major difference between the Single-Shot
and Continuous modes is that the internal counter
enable is not dependent on the CTG input level remaining in the low state for the Single- Shot mode.
Aside from these differences, the two modes are
identical.

3.79

Figure 15. Single-Shot Modes
to

CTO

I
( N + l ) _i - ( N + l ) -

(N+ 11

(AI NORMAL SINGLE·SHOT MODE OUTPUT WAVEFORM

" " " 'I j
(N+l)

(N+l)

(N +1)

(N + 1)

-I-

T.O.

1.0.

,,"" ""CO"' :

(B) CASCADED SINGLE·SHOT MODE OUTPUT WAVEFORM
1 =WRITE A "1" INTO TCR·7
0= WRITE A "0" INTO TCR· 7
'POINT ATWHICH AN INTERRUPT MAY OCCUR
Note: All time intervals shown aboveassum. the GatelCTG)and

Clock 1m) signals are synchronized to sysb!m 4>2 with specified
setup and hold time requirements.

-I

86846

Time Interval Modes (TCR3 = 1) - The Time Interval
Modes are provided for applications requiring more
flexibility of interrupt generation and Counter Initialization. Individual Interrupt Flags are set in these
modes as a function of both Counter Time Out and
transitions of the CTG input. Counter Initialization
is also affected by Interrupt Flag status. The output
signal is not defined in any of these modes. Other
features of the Time Interval Modes are outlined in
Table 5.
Cascaded Single-Shot Mode (TCR3 = 0, TCR4 - 0,
TCR5 = 1) - This mode is identical to the single-shot
mode with two exceptions. First, the output waveform
does not return to a low level and remain low after
timeout. Instead, the output level remains at its initialized level until it is reprogrammed and changed by
timeout. The output level may be changed at any
timeout or may have any number of timeouts between
changes.

The second difference is the method used to change
the output level. Timer Control Register Bit 7 (TCR 7)
has a special function in this mode. The timer output
(CTO) is equal to TCR7 clocked by timeout. At every
timeout, the content of TCR 7 is clocked to and held
at the CTO output. Thus, output pulses of length
greater than one timer cycle can be generated by cascading timer cycles and counting time outs with a
software program. (See Figure 15).
An interrupt is generated at each timeout. To cascade
timer cycles, the MPU would need an interrupt routine
to: 1) count each timeout and determine when to
change TCR7; 2) write into TCR7 the state corresponding to the next desired state of the output waveform (only necessary during the last timer cycle before
the output is to cnange state); and 3) clear the interrupt flag by reading the combination status register.
It is also possible, if desired, to change the length of the
timer cycle by reinitializing the timer latches. This
allows more flexibility for obtaining desired times.

Table 5. Time Interval Modes

TCR4

TCR5

TCR3 = 1
Application
Frequency
Comparison
Frequency
Comparison
Pulse Width
Comparison
Pulse Width
Comparison

3.80

Condition for Setting Individual Interrupt Flag
Interrupt Generated if CTG Input Period (1/F)
is Less Than Counter Time Out (T.O.)
Interrupt Generated if CTG Input Period (1/F)
is Greater Than Counter Time Out (T.O.)
Interrupt Generated if CTG Input "Down Time"
is Less Than Counter Time Out (T.O.)
Interrupt Generated if CTG Input "Down Time"
is Greater Than Counter Time Out (T.O.)

56846
Frequency Comparison Mode (TCR3 =1, TCR4 =0) The timer within the S6846 may be programmed to
compare the period of a pulse (giving the frequency
after calculations) at the CTG input with the time
period required for Counter Time Out. A negative of
the CTG input enables the counter and starts a Counter
Initialization cycle - provided that other conditions
as noted in Table 6 are satisfied. The counter decrements on each clock signal recognized during or after
Counter Initialization until an Interrupt is generated,
a Write Timer Latches command is issued, or a Timer
Reset condition occurs. It can be seen from Table 6
that an interrupt condition will be generated if TCR5 =
and the period of the pulse (single pulse or measured
separately repetative pulses) at the CTG input is less
than the Counter Time Out period. If TCR5 = 1, an
interrupt is generated if the reverse is true.

is no individual Interrupt Flag generated, this automatically starts a new Counter Initialization Cycle.
The process will continue with frequency comparison
being performed on each CTG input cycle until the
mode is changed, or a cycle is determined to be above
the predetermined limit.
Pulse Width Comparison Mode (TCR3 = 1, TCR4 =1) This mode is similar to the Frequency Comparison
Mode except for the limiting factor being a positive,
rather than negative, transition of the CTG input.
With TCR5 = 0, an Individual Interrupt Flag will be
generated if the zero level pulse applied to the CTG
input is less than the time period required for Counter
Time Out. With TCR5 = 1, the interrupt is generated
when the reverse condition is true.

As can be seen in Table 7, a positive transition of the
Assume now with TCR5 = 1 that a Counter Initiali- CTG input disables the counter. With TCR5 = 0, it is
zation has occurred and that the CTG input has therefore possible to directly obtain the width of any
returned low prior to Counter Time Out. Since there pulse causing an interrupt.

Table 6. Frequency Comparison Mode

Control Reg
Bit 5 (CRX5)
0
1

Counter
Initialization
G'('·I·(CE+TO·CE) + R
G-t-·I+R

CRX3 =1, CRX4 =0
Counter Enable
Flip-Flop Set (CE)
G,(,·W·R·I
G,(,·W·R·I

Counter Enable
Flip-Flop Reset (CE)
W+R+I
W+R+I

Interrupt Flag
Set (1)
G-t- Before TO
TO Before G-t-

I represents the interrupt for the timer.
Table 7. Pulse Width Comparison Mode

Control Reg
Bit 5 (CRX5)
0
1

Counter
Initialization
G-t-·I+R
G-t-·I+R

CRX3 = 1, CRX4 =1
Counter Enable
Flip-Flop Set (CE)
G,(,·W·R·I
G,(,·W·R·I

3.81

Counter Enable
Flip-Flop Reset (CE)
W+R+I+G
W+R+I+G

Interrupt Flag
Set (1)
Gt Before TO
TO Before Gt

·56846

Differences Between the S6840 and the S6846 Timers
1) Control registers 1 and 3 are buried (access
through control register 2 only) in the S6840
timer. In the S6846, all registers are directly
accessible.
2) The S6840 has a dual 8 bit continuous mode
for generating non -symmetrical waveform&. The
S6846, instead, has a cascaded one shot moq~
which can accomplish the same function, but
also allows the user to generate waveforms
longer than one timeout.
3) Because of the different modes, there is a difference in the control registers between the
S6840 and the S6846.
Control
Register
Bit
2
7

R1 internal reset
R2 control register select
R3 timer 3 clock control

The Composite Interrupt Flag (CSR7) is clear only if
all enabled Individual Interrupt Flags are clear. The
conditions for clearing CSR1 and CSR2 are detailed
in a later section. The Timer Interrupt Flag (CSRO)
is cleared under the following conditions:
1) Timer Reset - Internal Reset Bit (TCRO)
or External Reset = O.
2) Any Counter Initialization condition.

S6846

S6840
16 bit or dual8 bit
mode control
output enable (all modes)

S6846.) Three individual interrupt flags in the register
are set directly via the appropriate conditions in the
timer or peripheral port. The composite interrupt flag
- and the IRQ Output - respond to these individual
interrupts only if corresponding enable bits are set in
the appropriate Control Registers. (See. Figure 16).
The sequence of assertion is not detected. Setting
TCR6 while CSRO is high will cause CSR 7 to be set,
for example.

78 prescale enable

3) A Write Timer Latches command if Time
Interval (TCR3 = 1) are being used.

output next state
{cascaded one shot
mode on,lyl. output
enable all other modes

4) A Read Timer Counter command, provided
this is preceded by a Read Composite Status
Register while CSRO is set. This latter condition
prevents missing an Interrupt Request generated
after reading the Status Register and prior to
reading the counter.

internal reset

Composite Status Register - The Composite Status
Register (CSR) is a read-only register which is shared
by the Timer and the Peripheral Data Port (of the
Figure 16. Composite Status Register and Associated Logic

Note: BitsCSR3·CSR6
are not used.

PCRU

TCR6

3.82

5) The remaining bits of the Composite Status

56846

6) The Peripheral Data lines (and CP2) of the
86846 feature internal current limiting which
allows them to directly drive the base of Darlington NPN transistors.

I/O Operation
Parallel Peripheral Port - The peripheral port of the
86846 contains 8 Peripheral Data lines (PO-P7), two
Peripheral Control lines (CP1 and CP2), a Data Direction Register, a Peripheral Data Register, and a Peripheral Control Register. The port also directly affects
two bits (C8R1 and C8R2) of the Composite 8tatus
Register.
The Peripheral Port is similar to the "B" side of a
PIA (86820 or 86821) with the following exceptions:
1) All registers are directly accessible in the 86846.
Data Direction and Peripheral Data in the
86820/6821 are located at the same address,
with Bit Two of the Control Register used for
register selection.
2) Peripheral Control Register Bit Two (PCR2)
of the 86846 is used to select an optional input
latch function. This option is not available with
86820/6821 PIA's.
3) Interrupt Flags are located in the 86846 composite status register rather than Bits 6 and 7
of the Control Register as used in the 86820/
6821.
4) Interrupt Flags are cleared in the 86820/6821
by reading data from the Peripheral Data Register. 86846 Interrupt Flags are cleared by either
reading or writing to the Peripheral Data Register - provided that a sequence of a) Flag 8et,
b) Read Composite 8tatus Register, c) Read/
Write Peripheral Data Register is followed.
5) Bit 6 of the 86846 Peripheral Control Register
is not used. Bit 7 (PCR 7) is an Internal Reset
Bit not available on the 86820/6821.

Data Direction Register - The MPU can write directly
to this eight- bit register to configure the Peripheral
Data lines as either inputs or outputs. A particUlar bit
within the register (DDRN) is used to control the corresponding Peripheral Data line (PN). With DDRN = 0,
PN becomes an input; if DDRN = 1, PN is an output.
As an example, writing Hex 80F into the Data Direction Register results in PO through P3 becoming outputs and P4 through P7 being inputs. Hex 835 is the
Data Direction Register results in alternate ou tputs and
inputs at the parallel port.
Peripheral Data Register - This eight-bit register is
used for transferring data between the peripheral data
port and the MPU. Any bit corresponding to an output line will be used to drive the output buffer
associated with that line. Data in these output bits is
normally provided by an MPU Write function (Input
bits - those associated with input lines - are unchanged by a Write Command.) Any input bit will
reflect the state of the associated input line if the input latch function is deselected. If the Control Register
is programmed to provide input latching, the input
bit will retain the state at the time CP1 was activated
until the Peripheral Data Register is read by the MPU.
Peripheral Control Register - This eight- bit register is
used to control the reset function as well as for selection of optional functions of the two peripheral control
lines (CP1 and CP2). The peripheral Control Register
functions are outlined in Table 8.

Table 8. Peripheral Control Register Format (Expanded)

PCR7

PCR6

PCR5

PCR4

PCR3

PCR2

PCRl

CP2 DIRECTION CONTROL

o~ CP2 is INPUT

1 ~ CP2 is 0 UTPUT

I
I

1--------------o NORMAL OPERATION
~

1 ~ RESET CONDITION (CLEARS PERIPH
DATA & DATA DIRECTION REG + CSRl & CSR2)

[

CP2 is INPUT (PCR5
PCR4

CP2 ACTIVE EDGE SELECT
o~ NEGATIVE (n EDGE
1 ~ POSITIVE (t) EDGE

PCR3

CPl INT. ENABLE
CPl INT. MASKED
1 ~ CPl INT. ENABLED

CPl ACTIVE EDGE SELECT

RESET (SET BY EXT. RESET ~ 0 OR WRITING
ONE INTO LOCATION: CLEARED BY
WRITING ZERO TO THIS LOCATION)

PCRO

I
I

CP2 INT. ENABLE
o~ CP2 INT. MASKED
1 ~ CP2 INT. ENABLED

3.83

o~ NEGATIVE (t) EOGE
1 ~ POSITIVE (t) EOGE

CPl INPUT LATCH CONTROL
o~ INPUT OATA NOT LATCHED
1 ~ INPUT DATA LATCHED ON ACTIVE CPl

CP2 IS OUTPUT (PCR5

PCR4

PCR3

INTERRUPT ACKNOWLEDGE

INPUT/OUTPUT ACKNOWLEOGE

o DR 1

PROGRAMMABLE OUTPUT
(CP2 REFLECTS DATA
WRITTEN INTO PCR3)

56846

Peripheral Port Reset (PCR 7) - Bit 7 of the Peripheral
Control Register (PCR 7) may be used to initialize the
peripheral section of the S6846. When this bit is set
high, the peripheral data register, the peripheral data
direction register, and the interrupt flags associated
with the peripheral port (CSR1 and CSR2) are all
cleared. Other bits in the peripheral control register are
not affected by PCR 7.
PCR 7 is set by either a logic zero at the External RESET input or under program control by writing a "one"
into the location. In any case, PCR 7 may be cleared
only by writing a zero into the location while RESET
is high. The bit must be cleared to activate the port.
Control of CP1 Peripheral Control Line - CP1 may
be used as an interrupt request to the S6846, as a
strobe to allow latching of input data, or both. In
any case, the input can be programmed to be activated
by either a positive or negative transition of the signal.
These options are selected via Control Register Bits
PCRO, PCR1 & PCR2.

Control Register Bit
(PCRO) is used to enable the
interrupt transfer circuitry of the S6846. Regardless
of the state of PCRO, an active transition of CP1 causes
the Composite Status Register Bit One (CSR1) to
be set. If PCRO = 1, this interrupt will be reflected in
the Composite Interrupt Flag (CSR7), and thus at
the IRQ output. CSR1 is cleared by a Timer Reset
condition or by either reading or writing to the peripheral data register after the Composite Status Register
is read. The latter alternative is conditional - CSR1
must have been a logic one when the Composite
Status Register was last read. This precludes inadvertent clearing of interrupt flags generated between
the time the Status Register is read and the manipulation of peripheral data.
Control Register Bit One (PCR1) is used to select
the edge which activates CPl. When PCR1 = 0, CP1
is active on negative transitions (high to low). Low to
High transitions are sensed by CP1 when PCR1 = l.
In addition to its use as an interrupt input, CP1 can
be used as a strobe to capture input data in an internal
latch. This option is selected by writing a one into
Peripheral Control Register Bit Two (PCR2). In operation, the data at the pins designated by the Data
Direction Register as inputs will be captured by an
active transition of CPl. An MPU Read of the Peripheral Data Register will result in the captured data
being transferred to the MPU - and it also releases
the latch to allow capture of new data. Note that successive active transitions with no Read Peripheral Data

Command between does not update the input latch.
Also, it should be noted that use of the input latch
function (which can be deselected by writing a zero
into PCR2) has no effect on output data. It also does
not affect Interrupt function of CPl.
Control of CP2 Peripheral Control Line - CP2 may
be used as an input by writing a zero into PCR5. In
this configuration, CP2 becomes a dual of CP1 in regard to generation of interrupts. An active transition
(as selected by PCR4) causes Bit Two of the Composite
Status Register to be set. PCR3 is then used to select
whether the CP2 transition is to cause CSR 7 to be
set - and thereby cause IRQ to go low. CP2 has no
effect on the input latch function of the S6846.
Writing a one into PCR5 causes CP2 to function as an
output. PCR4 then determines whether CP2 is to be
used in a handshake or programmable output mode.
With PCR4 = 1, CP2 will merely reflect the data written
into PCR3. Since this can readily be changed under
program control, this mode allows CP2 to be a programmable output line in much the same manner as
those lines selected as outputs by the Data Direction
Register.
The handshaking mode (PCR5 = 1, PCR4 = 0) allows
CP2 to perform one of two functions as selected by
PCR3. With PCR3 = 1, CP2 will go low on the first
Enable (System ¢2) positive transition after a Read or
Write to the Peripheral Data Register. This Input/
Output Acknowledge signal is released (returns high)
on the next positive transition of the Enable signal.
In the Interrupt Acknowledge mode (PCR5 = 1, PCR4
= PCR3 = 0), CP2 is set when CSR1 is set by an active
transition of CPl. It is released (goes low) on the first
positive transition of Enable after CSR1 has been
cleared via an MPU Read or Write to the Peripheral
Data Register. (Note that the previously described
conditions for clearing CSR1 still apply.)
Restart Sequence - A typical restart sequence for
the S6846 will include initialization of both the Peripheral Control and Data Direction Registers of the parallel port. It is necessary to set up the Peripheral Control
Register first, since PCR 7 = is a condition for writing data into the Data Direction Register. (A logic
zero at the external Reset input automatically sets
PCR7.)

Summary - The S6846 has several optional modes
of operation which allow it to be used in a variety of
applications. The following tables are provided for
reference in selecting these modes.

3.84

56846

Table 9. S6846 Internal Register Addresses

0
0
0
0
1
1
1
1
X

0
0
1
1
0
0
1
1
X

0
1
0
1
0
1
0
1
X

Register Selected
Combination Status Register
Peripheral Control Register
Data Direction Register
Peripheral Data Register
Combination Status Register
Timer Control Register
Timer MSB Register
Timer LSB Register
ROM Address

Table 10. Composite Status Register

CSR7

CSRJ·CSR6 NOT USED. DEFAULT
TO ZERO WHEN READ

J
COMPOSITE INTERRUPT FLAG
0= NO ENABLED INTERRUPT FLAG SET
1 = ONE OR MORE ENABLED INTERRUPT FLAGS SET.

CSR2

CSRI

CP2 INTERRUPT FLAG
0= NO INT REQ
1 = INT REQUESTED

CSRO

TIMER INTERRUPT FLAG
0= NO INT REQ
1 = INT REQUESTED

INVERSE OF THIS BIT APPEARS AT IRQ OUTPUT
CPl INTER RUPT
0= NO INT REO
1 = INT REQUESTED

STATUS OF THIS BIT CAN BE EXPRESSED AS:
CSR7 = CSRO . TCR6 + CSRI • PCRO + CSR2 . PCRJ

Table 11. Timer Control Register

TCR7

TCR6

TCR5

TCR4

TCRJ

I
I

~------------

FOR CASCADED SINGLE SHOT
0= OUTPUT GOES LOW AT TIME OUT
1 = OUTPUT GOES HIGH AT TIME OUT

TCR5

TCR4

TCRJ

0
0
0
0

0
O.

TIMER OPERATING MODE
CONTINUOUS

CASCADED SINGLE SHOT

CONTINUOUS

NORMAL SINGLE SHOT

FREQUENCY

0
0

COMPARISO~

TCRO

TIMER OUTPUT ENABLE
0= OUTPUT DISABLED (LOW)
1 = OUTPUT ENABLED

INTERNAL RESET
0= TIMER ENABLED
1 = RESET STATE

CLOCK SOURCE
0= EXTERNAL CLOCK (CTC)
1 = INTERNAL CLOCK (4)2)
78 PRESCALE ENA8LE
0= CLOCK NOT PRESCALED
1 = CLOCK PRESCALED (78)

COUNTER INITIALIZATION

INTERRUPT FLAG SET

CTG. +W+ R

T.O.

CfG. + R
CfGp R

T.O.

CTIlp R

T.O.

CfG •. I • (W + T.O.) + R

erG. BEFORE T.O.

CTG •• 1+ R

T.O. BEFORE CTG.

1
PULSE WIDTH COMPARISON

CTG •. 1+ R

CfGt BEFORE T.O.
T.O. BEFORE CRGt

= RESET CONDITION

CTG. = NEG TRANSITION OF PIN 17

= WRITE TIMER LATCHES

CTGt = POS TRANSITION OF PIN 17

T.D. = COUNTER TIME OUT

TCRI

INTERRUP ENABLE
0= IRQ MASKED
1 = i1fii ENABLED

TCR2

=INTERRUPT FLAG (CSRO) =0

3.85

S6846

Table 12. Peripheral Control Register

PCR7

PCR6

PCR5

PCR3

PCR4

PCR2

1--------------0= NORMAL OPERATION
1 = RESET CONDITION (CLEARS PERIPH
DATA & DATA DIRECTION REG + CSRI & CSR2)

CP2 ACTIVE EDGE SELECT
0= NEGATIVE (I) EDGE
1 = POSITIVE (I) EOGE

PCR3

INPUT/OUTPUT ACKNOWLEDGE

oDR 1

CP2 CP2
"'.INT.
""
"
0=
MASKED
1 = CP2 INT. ENABLE~_

EXAMPLE:

Type of record

o3-4

5,6,7,8

CP2 IS OUTPUT (PCR5 = 1)
INTERRUPT ACKNOWLEDG E

ASCII

N+l, N+2

Start of record (S)

CPl ACTIVEEDG E SELECT
0= NEGATIVE It) EDGE
1 = POSITIVE (t) EDGE

The preferred method of pattern submission is the
AMI Hex format as described below with its built-in
address space mapping and error checking. This is the
format produced by the AMI Assembler/Loader. The
format is as follows and may be on paper tape, punched
card or other media readable by AMI. In addition the
value for Eo, El , E2 * is required to program the mask.

CPl INT. ENABLE
0= CPl INT. MASKED
1 = CPl INT. ENABLED

PCR3

9, ... , N

Description

PCR4

S6846 Custom Programming

Character

CP2 is INPUT (PCR5 = 0)
PCR4

PCRO

CPl INPUT LATCH CONTROL
0= INPUT DATA NOT LATCHED
1 = INPUT DATA LATCHED ON ACTIVE CPl

CP2 DIRECTIDN CDNTRDL
0= CP2 is INPUT
1 = CP2 is 0 UTPUT

RESET (SET BY EXT. RESET = 0 OR WRITING
ONE INTO LOCATION: CLEARED BY
WRITING ZERO TO THIS LOCATION)

PCRI

PROGRAMMABLE OUTPUT
(CP2 REFLECTS DATA
WRITTEN INTO PCR3)

Data
Each data byte is represented by two
hex characters. Most significant character first.
Checksum
The one's complement of the additive
summation (without carry) of the data
bytes, the address, and the byte count.

Sl13000049E9Fl0320F0493139F72000F5EOFOOllD
S9030000FC

~cE

ocr:>::
w<..> ....
crw."
u..cr::o
Ou..o

<">0-

Headerrecord

1 - Data record
9 - End of file record
Byte Count
Since each data byte is represented as
two hex characters, the byte count
must be multiplied by two to get the
number of characters to the end of the
record. (This includes checksum and
address data.) Records may be of any
length being defined in each record by
the byte count.
Address Value
The memory location where this record
is to be stored.

on
w
cr

C
0

2 clock.

(13)

R/W

READ/WRITE CONTROL SIGNAL-The Read/Write line is a high impedance input that is
TTL compatible and is used to control the direction of data flow through the ACIA's
input/output data bus interface. When Read/Write is high (MPU Read cycle), the ACIA
output driver is turned on and a selected register is read. When it is low, the ACIA output
driver is turned off and the MPU writes into a selected register. Thus, the Read/Write signal
is used to select the Read Only or Write Only registers within the ACIA.

(8)
(I 0)
(9)

CSO
CSI

CSL

CHIP SELECT SIGNALS-These three high impedance TTL compatible input lines are used
to address an ACIA. A particular ACIA is selected when CSO and CS 1 are high and CS2 is
low. Transfers of data to and from ACIA are then performed under the control of Enable,
Read/Write, and Register Select.

(II)

REGISTER SELECT SIGNAL-The Register Select line is a high impedance input that is
TTL compatible and is used to select the Transmit/Receive Data or Control/Status registers
in the ACIA. The Read/Write signal line is used in conjunction with Register Select to select
the Read Only or Write Only register in each register pair.

(7)

INTERRUPT REQUEST SIGNAL-Interrupt request is a TTL compatible, open drain active
low output that is used to interrupt the MPU. The Interrupt Request remains low as long
as the cause of the interrupt is present and the appropriate interrupt enable within ,the
ACIA is set.

ACIA/MODEM OR PERIPHERAL INTERFACE
Pin

(4)

Label
CTX

FUNCTION
TRANSMIT CLOCK-The Transmit Clock is a. high impedance TTL compatible input
used for the clocking of transmitted data. The transmitter initiates data on the negative
transition of the clock. Clock frequency of 1, 16, or 64 times the data rate may be selected.

3.92

56850

Label

FUNCTION

(3)

CRX

RECEIVE CLOCK-The Receive Clock is a high impedance TTL compatible input used
for synchronization of received data. (In the -;- 1 mode, the clock and data must be
synchronized externally.) The receiver strobes the data on the positive transition of the
clock. Clock frequency of 1, 16, or 64 times the data rate may be selected.

(2)

RXD

RECEIVED DATA-The Received Data line is a high impedance TTL compatible input
through which data is received in a serial NRZ(Non Return to Zero) format. Synchronization
with a clock for detection of data is accomplished internally when clock rates of 16 or 64
times the bit rate are used. Data rates are in the range of 0 to 500 Kbps when external
synchronization is utilized.

(6)

TXD

TRANSMIT DATA-The Transmit Data output line transfers serial NRZ data to a modem or
other peripheral device. Data rates are in the range of 0 to 500Kbps when external
synchronization is utilized.

(24)

CTS

CLEAR-TO-SEND-This high impedance TTL compatible input provides automatic control
of the transmitting end of a communications link via the modem's "clear-to-send" active low
output by inhibiting the Transmitter Data Register Empty status bit (TDRE).

(5)

RTS

REQUEST-TO-SEND-The Request-to-Send output enables the MPU to control a peripheral
or modem via the data bus. The active state is low. The Request-to-Send output is controlled
by the contents of the ACIA control register.

(23)

DCD

DATA CARRIER DETECTED-This high impedance TTL compatible input provides
automatic control of the receiving end of a communications link by means of the modem
"Data-Carrier-Detect" or "Received-Line-Signal Detect" output. The DCD input inhibits and
initializes the receiver section of the ACIA when high. A low to high transition of the Data
Carrier Detect initiates an interrupt to the MPU to indicate the occurrence of a loss of carrier
when the Receiver Interrupt Enable (RIE) is set.

(12)

VCC

+5 volts ± 5%

(1)

GND

GROUND

3.93

S6850

APPLICA T10N INFORMATION

INTERNAL REGISTERS-The ACIA has four internal registers
utilized for status, control, receiving data, and transmitting
data. The register addressing by the R/W and RS lines and the
bit definitions for each register are shown in Figure 4.

FIGURE 4 - DEFINITION OF ACIA REGISTERS
BUFFER ADDRESS
RS e R/W

RS eR/W

RS e it/W

RS e R/W

Transmit
Data
Register

Receiver
Date
Register

Control
Register

(Write Only)

(Read Only)

(Write Only)

Status
Register
(Read Only)

Data Bit 0*

Data Bit 1

Clk. Divide
Sel. 2(CRl)

Tx Data Reg.
Empty (TDRE)

Data Bit 2

Word Sel. 1
(CR2)

Data Carrier
Del.
(DCD)

Data Bit 3

Word Sel. 2
(CR3)

Clear-to-Send
(CTS)

Data Bit 4

Word Sel. 3
(CR4)

Framing Error
(FE)

Data Bit S

Tx Cantrall
(CRS)

Receiver Overrun
(OVRN)

Data Bit 6

Tx Control 2
(CR6)

Parity Error (PE)

Data Bit 7***

Data Bit 7**

Rx Interrupt
Enable (CR7)

Interrupt Request
(IRQ)

Data Bus
Line
Number

Notes:
*
Leading bit = LSB = Bit 0
**
Unused data bits in received character will be "O's."
*** Unused data bits for transmission are "don't care's."

3.94

Clk. Divide
Sel. 1 (CRO)

Rx Data Reg.
Full (RDRF)

56850

ACIA STATUS REGISTER-Information on the status of the
ACIA is available to the MPU by reading the ACIA Status
Register. This Read Only register is selected when RS is low
and R/W is high. Information stored in this register i~dicates
the status of: transmitting data register, the receiving data
register and error status and the modem status inputs of the
ACIA.
Receiver Data Register Full (RDRF) [Bit 0] - Receiver
Data Register Full indicates that received data has been
transferred to the Receiver Data Register. RDRF is cleared
after an MPU read of the Receiver Data Register or by a
Master Reset. The cleared or empty state indicates that the
contents of the Receiver Data Register are not current. Data
Carrier Detect being high also causes RDRF to indicate empty.
Transmit Data Register Empty (TDRE) [Bit 1] -The
Transmit Data Register Empty bit being set high indicates that
the Transmit Data Register contents have been transferred and
that new data may be entered. The low state indicates that the
register is full and that transmission of a new character has not
begun since the last write data command.
Data Carrier Detect (DCD) [Bit 2] - The Data Carrier
Detect bit will be high when the DCD input from a modem
has gone high to indicate that a carrier is not present.
This bit going high causes an Interrupt Request to be generated
if the Receiver Interrupt Enable (RIE) is set. It remains high
until the interrupt is cleared by reading the Status Register and
the data register or a Master Reset occurs. If the DCD input
remains high after Read Status and Read Data or Master Reset
have occurred, the DCD Status bit remains high and will follow
the DCD input.___~
Clear-to-Send (CTS) [Bit 3] - The Clear-to-Send bit
indicates the state of the Clear-to-Send input from a modem.
A low CTS indicates that there is a Clear-to-Send from the
modem. In the high state, the Transmit Data Register Empty
bit is inhibited and the Clear-to-Send status bit will be high.
Master Reset does not affect the Clear-to-Send status bit.
Framing Error (FE) [Bit 4] - Framing error indicates
that the received character is improperly framed by the start
and stop bit and is detected by the absence of the 1st stop bit.
This error indicates a synchronization error, faulty transmission,
or a break condition. The framing error flag is set or reset
during the receiver data tr-ansfer time. Therefore, this error
indicator is present throughout the time that the associated
character is available.
Receiver Overrun (OVRN) [Bit 5] - Overrun is an error
flag that indicates that one or more characters in the data
stream were lost. That is, a character or a number of characters
were received but not read from the Receiver Data Register

3.95

(RDR) prior to subsequent characters being received. The
overrun condition begins at the midpoint of the last bit of the
second character received in succession without a read of the
RDR having occurred. The Overrun does not occur in the
Status Register until the valid character plior to Overrun has
been read. The RDRF bit remains set until Overrun is reset.
Character synchronization is maintained during the Overrun
condition. The overrun indication is reset after the reading of
data from the Receive Data Register. Overrun is also reset by
the Master Reset.
Parity Error (PE) [Bit 6] -The parity error flag indicates
that the number of highs (ones) in the character does not agree
with the preselected odd or even parity. Odd parity is defined
to be when the total number orones is odd. The parity error
indication will be present as long as the data character is in the
RDR. If no parity is selected, then both the transmitter parity
generator output and the receiver parity check results are
inhibited.
Interrupt Request (IRQ) [Bit 7] -The IRQ bit indicates
the state of the IRQ output. Any interrupt that is set and
enabled will be indicated in the status register. Any time the
IRQ output is low the IRQ bit will be high to indicate the
interrupt or service request status.
CONTROL REGISTER-The ACIA control Register consists
of eight bits of write only buffer that are selected when RS
and R/W are low. This register controls the function of the
receiver, transmitter, interrupt enables, and the Request-toSend modem control output.
Counter Divide Select Bits (CRO and CRl)-The Counter
Divide Select Bits (CRO and CR1) determine the divide ratios
utilized in both the transmitter and receiver sections of the
ACIA. Additionally, these bits are used to provide a Master
Reset for the ACIA which clears the Status Register and
initializes both the receiver and transmitter. Note that after a
power-on or a power-fail restart, these bits must be set High to
reset the ACIA. After resetting, the clock divide ratio may be
selected. These counter select bits provide for the following
clock divide ratios:

CRl

CRO

Function.

a
a

0
1

-;.- 1
-;.-16
-;.-64
Master Reset

S6850

Word Select Bits (CR2, CR3, and CR4)-The Word Select bits
are used to select word length, parity, and the number of stop
bits. The encoding format is as follows:
CR4

0
0
0
0

CR3
0
0

0
0

CR2

0
I
0
I
0
I
0

Function
7 Bits + Even Parity + 2 Stop Bits
7 Bits + Odd Parity + 2 Stop Bit
7 Bits + Even Parity + I Stop Bit
7 Bits + Odd Parity + I Stop Bit
8 Bits + 2 Stop Bits
8 Bits + I Stop Bit
8 Bits + Even Parity + I Stop Bit
8 Bits + Odd Parity + I Stop Bit

Word length, Parity Select, and Stop Bit changes are not
double-buffered and therefore become effective immediately.
Transmitter Control Bits (CRS and CR6)-Two Transmitter Control bits provide for the control of the Transmitter
Buffer Empty interrupt output, the Request-to-Send output
and the transmission of a BREAK level (space). The following
encoding format is used:
CR6

CRS

Function

RTS = low, Transmitting Interrupt Disabled
RTS = low, Transmitting Interrupt Enabled

character is being t~ansmitted, then the transfer will take place
within one bit time of the trailing edge of the Write command.
If a character is being transmitted, the new data character will
commence as soon as the previous character is complete. The
transfer of data causes the Transmit Data Register Empty
(TDRE) bit to indicate empty.
RECEIVE DATA REGISTER (RDR)-Data is automatically
transferred to the empty Receive Data Register (RDR) from
the receiver deserializer (a shift register) upon receiving a
complete character. This event causes the Receiver Data
Register Full bit (RDRF) (in the status buffer) to go high
(full). Data may then be read through the bus by addressing
the ACIA and sel.e~ting the Receiver Data Register with RS
and R/W high when'the ACIA is enabled. The non-destructive
read cycle causes the RDRF bit to be cleared to empty
although the data is retained in the RDR. The status is
maintained by RDRF as to whether or not the data is current.
When the Receiver Data Register is full, the automatic transfer
of data from the Receiver Shift Register to the Data Register is
inhibited and the RDR contents remain valid with its current
status stored in the Status Register.

OPERATIONAL DESCRIPTION

R TS = high, Transmitting Interrupt Disabled
RTS= low, Transmitting Interrupt Disabled
and Transmits a BREAK level on the Transmit Data Output.

Receiver Interrupt Enable Bit (RIE) (CR7)-Interrupts will be
enabled· by a high level in bit position 7 of the Control
Register (CR7). Interrupts caused by the Receiver Data
Register Full being high or by a low to high transition on the
Data Carrier Detect signal line are enabled or disabled by the
Receiver Interrupt Enable Bit.
TRANSMIT DATA REGISTER (TDR)-Data is written in the
Transmit Data Register during the peripheral enable time (E)
when the ACIA has been addressed and RS • R/W is selected.
Writing data into the register causes the Transmit Data
Register Empty bit in the status register to go low. Data can
then be transmitted. If the transmitter is idling and no

3.96

From the MPU Bus interface the ACIA appears as two
addressable RAM memory locations. Internally, there.are four
registers; two read-only and two write-only registers. The
read-only registers are status and receive data, and the write
only registers are control and transmit data. The serial
interface consists of serial transmit and receive lines and three
modem/peripheral control lines.
During a power-on sequence, the ACIA is internally
latched in a reset condition to prevent erroneous output
transitions. This power-on reset latch can only be released by
the master reset function via the control register; bits b(j and
bi are set "high" for a master reset. After master resetting the
ACIA, the programmable control register can be set for a
number of options such as variable clock divider ratios,
variable word length, one or two stop bits, parity (even, odd,
or none) and etc.
TRANSMITTER-A typical transmitting sequence consists of
reading the ACIA status register either as a result of an
interrupt or in the ACIA's turn in a polling sequence. A
character may be written into the Transmitter Data Register if
the status read operation has indicated that' the Transmit Data

S6850

Register is empty. This character is transferred tll a shirt
register where it is seriali/ed aild transmitted from the Tx Data
output preceded by a start bit and followed by one or two
stup bits. Internal parity (udd or even) can be optionally
added tll the character and will occur between the last data bit
and the first stup bit. After the first character is written in the
dat:.l register, the status register can be read again to check for
a Transmit Data Register Empty condition and current
peripheral status. If the register is empty, anuther character
can be loaded fur transmission even though the first character
is in the process uf being tr:.lllsmitted. This secund clwractcr
will be automatically transferred into the shift register when
the first character transmissiUn is completed. The above
sequence continues until all the characters have been transmitted.
RECEIVER--Data is received frum a peripheral by means of
the Rx Data input. A divide by one dock ratio is provided for
an externally synchroI1Ized dock (to its data) while the divide
by 16 and 64 ratios arc pruvided for internal synchronization.

3.97

Bit synchronization in the divide by 16 and 64 modes is
obtained by the detection of the leading mark-to-space
transition of the st:.lrt bit. False start bit deletion capability
insures that a full half bit of a start bit has been received
before the internal dock is synchronized to the bit time. As a
character is being received, parity (odd or even) will be
checkrd and the error indication will be available in the status
register along with framing error, overrun error, and receiver
data register full. In a typical receiving sequence, the status
register is read to determine if a character has been received
from a peripheral. If the receiver data register is full, the
character is placed on the 8-bit ACIA bus when a Read Data
command is received from the MPU. The status register can be
read again to determine if another character is available in the
receiver data register. The receiver is also double buffered so
that a character can be read from the data register as another
character is being received in the shift register. The above
sequence continues until all characters have been
received.

ADVANCED PRODUCT DESCRIPTION

S68A50/S68B50
ASYNCHRONOUS COMMUNICATION
INTERFACE ADAPTER (ACIA)
Features

General Description

The S68A50/S68B50 Asynchronous Communications
Interface Adapter (ACIA) provides the data formatting
and control to interface serial asynchronous data communications to bus organized systems such as the
S68AOO/S68BOO Microprocessing Units.

o
o
o
o
o
o
o
o
o

8 Bit Bidirectional Data Bus for
Communication with MPU
False Start Bit Deletion
Peripheral/Modem Control Functions
Double Buffered Receiver and Transmitter
One or Two Stop Bit Operation
Eight and Nine-Bit Transmission with
Optional Even and Odd Parity
Parity, Overrun and Framing Error Checking
Programmable Control Register
Optional-:-1, -:-16, and -;-64 Clock Modes
Up to 500,000 bps Transmission

The S68A50/S68B50 includes select enable, read/
write, interrupt and bus interface logic to allow data
transfer over an eight- bit bidirectional data bus. The
parallel data of the bus system is serially transmitted
and received by the asynchronous data interface, with
proper formatting and error checking. The functional
configuration of the ACIA is programmed via the data
bus during system initialization. Word lengths, clock
division ratios and transmit control through the Request to Send output may be programmed. For modem
operation three control lines are provided.

Block Diagram

Pin Configuration

CTX ;.14'--j}- - - - - - - - - - - - - - 1

E
CSO

CS1

114}

1--_ _ _ _+""-161

I8
}
1101

SELECT
&

CS2 191

RiW

1--_ _ _ _+1=241 ill

CONTROL

Rsilli
R/W

TXO

1131

17ljjffi
00
01
02
03
04

05
06
U7

1221

1--_ _ _ _ _-I-'-1=:!!.23IlJCij
f--_ _ _ _ _-+~151 RfS

1211
1201
1191
OATA
BUS
BUFFERS

1181
1171
1161
1151

f--_~~_~121 RXO

877253
CRX

17617

131

'-'--j--------------I

VCC

PIN 12

GROUND

PIN 1

3.98

S68ASO/S688S0

Absolute Maximum Ratings

Supply Voltage ........................................................... -0.3V to +7.0V
Input Voltage ............................................................ - 0.3V to +7.0V
Operating Temperature Range .................................................. oOe to +70 o e
o
Storage Temperature Range ................................................ -55°C to +150 e
Note:
This device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields, however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high
impedance circuit.

Electrical Characteristics (Vee
Symbol
VIH
VIL
lIN
ITSI
VOH

= +5.0V ±5%, VSS = 0, TA = oOe to +70 o e unless otherwise noted.)

Parameter

Min.

Input High Voltage (normal operating level)
VSS+2.0
Input Low Voltage (normal operating level)
VSS- 0.3
Input Leakage Current
R/W, ES, CSO, CSl, CS2, Enable
Three·State (Off State) Input Current
DO-D7
Output High Voltage (all outputs except IRQ)
DO-D7 VSS+2.4

Typ.

1.0
2.0

Max.

Vdc
Vdc

Tx Data, RTS VSS+2.4
VOL

Output Low Voltage (Enable pulse width < 25/1s)

ILOH
PD
CIN

Output Leakage Current (Off State)
Power Dissipation
Input Capacitance

Units

Vdc
VCC
VSS+O.S Vdc
2.5
/1Adc
10
/1Adc

VSS+O.4

Vdc

IRQ

1.0
300

10
525

/1Adc
mW

DO-D7
E,Tx,CLK,Rx Clk,R/W,RS,Rx Data,
CSO,CSl,CS2,RXD,CTS,DCD,CTX,CRX

12.5

7.0

7.5
10
5.0

pF
pF
pF
ns
ns
kHz
kHz

COUT

Output Capacitance

PWCL
PWCH
fC

Minimum Clock Pulse Width, Low
Minimum Clock Pulse Width, High
Clock Frequency

tTDD
tRDSU
tRDH
tIR
tRTS
tr,tf

Clock-to-Data Delay for Transmitter
Receive Data Setup Time
Receive Data Hold Time
Interrupt Request Release Time
Request-to-Send Delay Time
Input Transition Times (Except Enable)

RTS,Tx Data
IRQ
716,764 Modes
716,764 Modes
71 Mode
716,764 Modes

600
600

71 Mode
71 Mode

500
500

500
SOO
1.0

1.2
1.0
1.0*

*1.0/1 or 10% of the pulse width, whichever is smaller.

3.99

/1S
ns
ns
/1S
/1S
/1S

Conditions

VIN = OVdc to 5.25Vdc
VIN = O.4Vdc to ?.4Vdc
ILOAD = - 205/1 Adc,
Enable Pulse Width <25/1s
ILOAD = -100/1Adc,
Enable Pulse Width <25/1s
ILOAD = 1.6mAdc,
Enable Pulse Width <25/1s
VOH = 2.4Vdc

VIN= 0, TA = 25°C,
f = 1.0MHz

S68ASO/S688S0

Bus Timing Characteristics (VCC

= +5.0V ±5%, VSS = 0, TA = O°C to +70°C unless otherwise noted.)

Read

Symbol
tcycF
PWEH
PWEL
tAS
tDDR
tH
tAH
tEr,tEf

Parameter
Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and RjW Valid
to Enable Positive Transition
Data Delay Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable Input

S68A50
Min.
Max.

S68B50
Min.
Max.

0.666
0.28
0.28

0.50
0.22
0.21

140

I1S

180

220
10
10

I1 S
I1S

10
10

Units

ns
ns
ns
ns

Write

Symbol
tcycE
PWEH
PWEL
tAS
tDSW
tH
tAH
tFr,tEf

Parameter
Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and RjW Valid
to Enable Positive Transition
Data Setup Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable Input

S68A50
Min.
Max.

S68B50
Min.
Max.

0.666
0.28
0.28

0.50
0.22
0.21

I1S

I1S
I1S

140

80
10
10

60
10
10

ns
ns
ns
ns

3.100

Units

S68A50/S68850

Figure 1. Clock Pulse Width, Low State

Figure 2. Clock Pulse Width, High State

PWCL

Tx ClK

Tx CLK

or
Rx CLK

RxClK

PWCH

Figure 3. Transmit Data Output Delay

Figure 4. Receive Data Setup Time
(-;-1 Mode)

Rx DATA

Tx ClK

O.BV

'Too

TxOATA

2.0V

_~O~.BV~

--------'>1=

Figure 5. Receive Data Hold Time
(-;-1 Mode)

Rx CLOCK

_ _ _ _ _ _ _ _ _ _ _ __ _

tROSU

-----

O.BV

Figure 6. Request-to Send Delay and
Interrupt- Request Release Times

4 _~
x

ENABLE

2 OV

RX_'"

RxOATA

tRTS

_tROH

__r

O.BV

Figure 7. Bus Read Timing Characteristics
(Read Information from ACIA)

Figure 8. Bus Write Timing Characteristics
(Write Information into ACIA)
I - . . - - - t c y c E - - -_ _

t-.---tcycE---~

ENABLE

RS,CS,R/W

DATA BUS
DATA BUS

3.101

S68A50/S68B50

Bus Timing Test Loads

100 07,

LOAD A
RfS, Tx DATAl

LOAD B
IfRii ONLY}
5.0V

I.OV

RL"2.5k
TEST POINT

0--+-_>-1"--'

MM06150
OR EQUIV

TEST POINT

MM07000
OR EQUIV

C ~ 130p F FOR 00·07
" 30,F FOR RfS AND Tx DATA

87725\

0-----.

R~lUWFOR0007

" 24kSl FOR

AND Tx DATA

Expanded Block Diagram
TRANSMIT CLOCK 4

-------------------...-j

ENABLE 14 - - - - - - ,

REAOIWRITE 13
CH1P SELECT 08

TRANSMIT
QATA
REGISTER

CH1P SELECT 1 10
CHIPSELECT 2

r - - - - - _ 6 TRANSMIT DATA

0022
STATUS
REGISTER

0121
0220
0319
0418

7 INTERRUPT REQUEST
DATA
8US
BUFFERS

13 DATA CARRIER DETECT

0517
~

0616
07 15

5 REQUEST-TO-SEND

CONTROL
REG1STER

Voo

~ PIN 12
VSS ~ PIN 1

RECE1VE
DATA
REG1STER

RECEIVE
SHIFT
REGISTER

RECEIVE CLOCK 3 ---------------------t~L -_ _ _- '

3.102

1-+---+---1 RECEIVE DATA

S68A50/S68850

MPU/ACIA Interface

Function

Label

(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)

DO
D1
D2
D3
D4
D5
D6
D7

ACIA Bidirectional Data Lines - The bidirectional data lines (DO-D7) allow for data
transfer between the ACIA and the MPU. The data bus output drivers are three-state
devices that remain in the high impedance (off) state except when the MPU performs
an ACIA read operation. The Read/Write line is in the read (high) state when the ACIA
is selected for a read operation.

(14)

ACIA Enable Signal - The Enable signal (E) is a high impedance TTL compatible input that enables the bus input/output data buffers and clocks data to and from the
ACIA. This signal will normally be a derivative of the S6800 ¢2 clock.

(13)

R/W

Read/Write Control Signal - The Read/Write line is a high impedance input that is
TTL compatible and is used to control the direction of data flow through the ACIA's
input/output data bus interface. When Read/Write is high (MPU Read cycle), the ACIA
output driver is turned on and a selected register is read. When it is low, the ACIA
output driver is turned off and the MPU writes into a selected register. Thus, the
Read/Write signal is used to select the Read Only or Write Only registers within the
ACIA.

(9)

CSO
CS1
CS2

Chip Select Signals - These three high impedance TTL compatible input lines are used
to address an ACIA. A particular ACIA is selected when CSO and CS1 are high and CS2
is low. Transfers of data to and from ACIA are then performed under the control of
Enable, Read/Write and Register Select.

(11)

Register Select Signal - The Register Select line is a high impedance input that is TTL
compatible and is used to select the Transmit/Receive Data or Control/Status registers
in the ACIA. The Read/Write signal line is used in conjunction with Register Select to
select the Read Only or Write Only register in each register pair.

(8)

(10)

(7)

Interrupt Request Signal - Interrupt request is a TTL compatible, open drain active
low output that is used to interrupt the MPU. The Interrupt Request remains low as
long as the cause of the interrupt is present and the appropriate interrupt enable within the ACIA is set.

3.103

S68ASO/S68BSO

ACIA/Modem or Peripheral Interface

Label

Function

(4)

CTX

Transmit Clock - The Transmit Clock is a high impedance TTL compatible input
used for the clocking of transmitted data. The transmitter initiates data on the negative
transition of the clock. Clock frequency of 1, 16, or 64 times the data rate may be
selected.

(3)

CRX

Receive Clock - The Receive Clock is a high impedance TTL compatible input used
for synchronization of received data. (In the -:-1 mode, the clock and data must be
synchronized externally.) The receiver strobes the data on the positive transition of the
clock. Clock frequency of 1, 16, or 64 times the data rate may be selected.

(2)

RXD

Received Data - The Received Data line is a high impedance TTL compatible input
through which data is received in a serial NRZ (Non Return to Zero) format. Synchronization with a clock for detection of data is accomplished internally when clock rates
of 16 or 64 times the bit rate are used. Data rates are in the range of 0 to 500Kbps
when external synchronization is utilized.

(6)

TXD

Transmit Data - The Transmit Data output line transfers serial NRZ data to a modem
or other peripheral device. Data rates are in the range of 0 to 500Kbps when external
synchronization is utilized.

(24)

Clear-to-Send - This high impedance TTL compatible input provides automatic control of the transmitting end of a communications link via the modem's "clear-to-send"
active low output by inhibiting the Transmitter Data Register Empty status bit (TDRE).

(5)

Request-to-Send - The Request-to-Send output enables the MPU to control a peripheral or modem via the data bus. The active state is low. The Request-to-Send output is
controlled by the contents of the ACIA control register.

(23)

Data Carrier Detected - This high impedance TTL compatible input provides automatic control of the receiving end of a communications link by means of the modem
"Data-Carrier-Detect" or "Received-Line-Signal Detect" output. The DCD input inhibits and initializes the receiver section of the ACIA when high. A low to high transition of the Data Carrier Detect initiates an interrupt to the MPU to indicate the occurrence of a loss of carrier when the Receiver Interrupt Enable (RIE) is set.

(12)

VCC

+5volts ±5%

(1)

GND

Ground

3.104

S68A50/S68850

Application Information

Internal Registers - The ACIA has four internal registers utilized for status, control, receiving data and
transmitting data. The register addressing by the RjW
and RS lines and the bit definitions for each register
are shown in Figure 4.
Figure 4 - Definition of ACIA Registers

RS. RjW
Transmit
Data
Register
(Write Only)
Data Bit 0*

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7***

Data Bus
Line
Number

Buffer Address
RS. R/W
RS. R/W
Received
Control
Data
Register
Register
(Write Only)
(Read Only)
Clk. Divide
Data Bit 0*
Sel. (CRO)
Clk. Divide
Data Bit 1
Sel. (CR1)
Word Sel. 1
Data Bit 2
(CR2)
Data Bit 3
Word Sel. 2
(CR3)
Data Bit 4
Word Sel. 3
(CR4)
Tx Cantrall
Data Bit 5
(CR5)
Data Bit 6
Tx Control 2
(CR6)
Rx Interrupt
Data Bit 7**
Enable (CR 7)

Notes:

*
**
***

Leading bit = LSB = Bit 0
Unused data bits in received character will be "O's"
Unused data bits for transmission are "don't care's"

3.105

RS. R/W
Status
Register
(Read Only)
Rx Data Reg.
Full (RDRF)
Tx Data Reg.
Empty (TDRE)
Data Carrier
Det. Loss (DCD)
Clear -to -Send
(CTS)
Framing Error
(FE)
Overrun (OVRN)
Parity Error (PE)
Interrupt Request
(IRQ)

S68A50/S68B50

ACIA Status Register - Information on the status of
the ACIA is available to the MPU by reading the ACIA
Status Register. This Read Only register is selected
when RS is low and R/W is high. Information stored
in this register indicates the status of: transmitting
data register, the receiving data register and error status
and the modem status inputs of the ACIA.
Receiver Data Register Full (RDRF) [Bit 0] - Receiver Data Register Full indicates that received data
has been transferred to the Receiver Data Register.
RDRF is cleared after an MPU read of the Receiver
Data Register or by a Master Reset. The cleared or
empty state indicates that the contents of the Receiver
Data Register are not current. Data Carrier Detect
being high also causes RDRF to indicate empty.
Transmit Data Register Empty (TDRE) [Bit 1] -The
Transmit Data Register Empty bit being set high indicates that the Transmit Data Register contents have
been transferred and that new data may be entered.
The low state indicates that the register is full and that
transmission of a new character has not begun since
the last write data command.
Data Carrier Detect (DCD) [Bit 2] - The Data Carrier
Detect bit will be high when the DCD input from a
modem has gone high to indicate that a carrier is not
present. This bit going high causes an Interrupt Request
to be generated if the Receiver Interrupt Enable (RIE)
is set. It remains high until the interrupt is cleared
by reading the Status Register and the data register
or a Master Reset occurs. If the DCD input remains
high after Read Status and Read Data or Master Reset have occurred, the DCD Status bit remains high
and will follow the DCD input.
Clear-to-Send (CTS) [Bit 3] - The Clear-to-Send
bit indicates the state of the Clear-to-Send input from
a modem. A low CTS indicates that there is a Clearto-Send from the modem. In the high state, the Transmit Data Register Empty bit is inhibited and the Clearto-Send status bit will be high. Master Reset does
not affect the Clear -to -Send status bit.

Framing Error (FE) [Bit 4] - Framing error indicates
that the received character is improperly framed by
the start and stop bit and is detected by the absence
of the 1st stop bit. This error indicates a synchronization error, faulty transmission, or a break condition.
The framing error flag is set or reset during the receiver data transfer time. Therefore, this error indicator
is present throughout the time that the associated
character is available.

Receiver Overrun (OVRN) [Bit 5] - Overrun is an
error flag that indicates that one or more characters
in the data stream were lost. That is, a character or a
number of characters were received but not read from
the Receiver Data Register (RDR) prior to subsequent
characters being received. The overrun condition begins at the midpoint of the last bit of the second
character received in succession without a read of the
RDR having occurred. The Overrun does not occur in
the Status Register until the valid character prior to
Overrun has been read. The RDRF bit remains set until Overrun is reset. Character synchronization is maintained during the Overrun condition. The overrun indication is reset after the reading of data from the Receiver Data Register. Overrun is also reset by the Master
Reset.

Parity Error (PE) [Bit 6] - The parity error flag indicates that the number of highs (ones) in the character
does not agree with the preselected odd or even parity.
Odd parity is defined to be when the total number of
ones is odd. The parity error indication will be present
as long as the data character is in the RDR. If no parity is selected, then both the transmitter parity generator output and the receiver parity check results are
inhibited.

Interrupt Request (IRQ) [Bit 7] - The IRQ bit indicates the state of the IRQ output. Any interrupt
that is set and enabled will be indicated in the status
register. Any time the IRQ output is low the IRQ bit
will be high to indicate the interrupt or service request
status.

3.106

S68A50/S68850

Control Register - The ACIA Control Register consists of eight bits of write only buffer that are selected
when RS and R/W are low. This register controls the
function of the receiver, transmitter, interrupt enables,
and the Request-to-Send modem control output.
Counter Divide Select Bits (CRO and CR1) - The
Counter Divide Select Bits (CRO and CR1) determine
the divide ratios utilized in both the transmitter and
receiver sections of the ACIA. Additionally, these bits
are used to provide a Master Reset for the ACIA which
clears the Status Register and initializes both the receiver and transmitter. Note that after a power-on or
a power-fail restart, these bits must be set High to reset the ACIA. After resetting, the clock divide ratio
may be selected. These counter select bits provide for
the following clock divide ratios:
CR1

CRa

Function

0
0
1
1

0
1
0
1

-:.-1
-:.-16
-:.-64
Master Reset

Word Select Bits (CR2, CR3, and CR4) - The Word
Select bits are used to select word length, parity, and
the number of stop bits. The encoding format is as
follows:
CR4 CR3
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

CR2
0
1
0
1
0
1
0
1

Transmitter Control Bits (CR5 and CR6) - Two Transmitter Control bits provide for the control of the
Transmitter Buffer Empty interrupt output, the Request-to -Send output and the transmission of a
BREAK level (space). The following encoding format
is used:
CR6 CR5
0

Function
R TS = low, Transmitting Interrupt Disabled
RTS = low, Transmitting Interrupt Enabled
RTS = high, Transmitting Interrupt Disabled
RTS = low, Transmitting Interrupt Disabled and Transmits a BREAK level on
the Transmit Data Output.

Receiver Interrupt Enable Bit (RIE) (CR7) - The Interrupts will be enabled by a high level in bit position
7 of the Control Register (CR 7). Interrupts caused by
the Receiver Data Register Full being high or by a low
to high transition on the Data Carrier Detect signal
line are enabled or disabled by the Receiver Interrupt
Enable Bit.

Function
7
7
7
7
8
8
8
8

Bits + Even Parity + 2 Stop Bits
Bits + Odd Parity + 2 Stop Bits
Bits + Even Parity + 1 Stop Bit
Bits + Odd Parity + 1 Stop Bit
Bits + 2 Stop Bits
Bits + 1 Stop Bit
Bits + Even Parity + 1 Stop Bit
Bits + Odd Parity + 1 Stop Bit

Word length, Parity Select, and Stop Bit changes are
not double-buffered and therefore become effective
immediately.

Transmit Data Register (TDR) - Data is written in
the Transmit Data Register during the peripheral enable time (E) when the ACIA has been addressed and
RS • R/W is selected. Writing data into the register
causes the Transmit Data Register Empty bit in the
status register to go low. Data can then be transmitted.
If the transmitter is idling and no character is being
transmitted, then the transfer will take place within
one bit time of the trailing edge of the Write command.
If a character is being transmitted, the new data character will commence as soon as the previous character
is complete. The transfer of data causes the Transmit
Data Register Empty (TDRE) bit to indicate empty.

3.107

S68ASO/S68BSO

Receive Data Register (RDR) - Data is automatically
transferred to the empty Receive Data Register (RDR)
from the receiver deserializer (a shift register) upon
receiving a complete character. This event causes the
Receiver Data Register Full bit (RDRF) (in the status
buffer) to go high (full). Data may then be read through
the bus by addressing the ACIA and selecting the Receiver Data Register with RS and R/W high when the
ACIA is enabled. The non-destructive read cycle causes
the RDRF bit to be cleared to empty although the
data is retained in the RDR. The status is maintained
by RDRF as to whether or not the data is current.
When the Receiver Data Register is full, the automatic
transfer of data from the Receiver Shift Register to
the Data Register is inhibited and the RDR contents
remain valid with its current status stored in the Status
Register.

mitter Data Register if the status read operation has
indicated that the Transmit Data Register is empty.
This character is transferred to a shift register where
it is serialized and transmitted from the Tx Data output preceded by a start bit and followed by one or
two stop bits. Internal parity (odd or even) can be
optionally added to the character and will occur between the last data bit and the first stop bit. After the
first character is written in the data register, the status
register can be read again to check for a Transmit Data
Register Empty condition and current peripheral
status. If the register is empty, another character can
be loaded for transmission even though the first character is in the process of being transmitted. This second character will be automatically transferred into
the shift register when the first character transmission
is completed. The above sequence continues until all
the characters have been transmitted.

Operational Description

From the MPU Bus interface the ACIA appears as
two addressable RAM memory locations. Internally,
there are four registers; two read-only and two writeonly registers. The read-only registers are status and
receive data, and the write-only registers are control
and transmit data. The serial interface consists of
serial transmit and receive lines and three modem/
peripheral control lines.
During a power-on sequence, the ACIA is internally
latched in a reset condition to prevent erroneous output transitions. This power-on reset latch can only be
released by the master reset function via the control
register: bits bO and b1 are set "high" for a master reset. After master resetting the ACIA, the programmable control register can be set for a number of options such as variable clock divider ratios, variable
word length, one or two stop bits, parity (even, odd,
or none) and etc.
Transmitter - A typical transmitting sequence consists
of reading the ACIA status register either as a result
of an interrupt or in the ACIA's turn in a polling sequence. A character may be written into the Trans-

Receiver - Data is received from a peripheral by means
of the Rx Data input. A divide by one clock ratio is
provided for an externally synchronized clock (to its
data) while the divide by 16 and 64 ratios are provided
for internal synchronization. Bit synchronization in
the divide by 16 and 64 modes is obtained by the detection of the leading mark-to-space transition of the
start bit. False start bit deletion capability insures that
a full half bit of a start bit has been received before the
internal clock is synchronized to the bit time. As a
character is being received, parity (odd or even) will
be checked and the error indication will be available
in the status register along with framing error, overrun
error, and receiver data register full. In a typical receiving sequence, the status register is read to determine if a character has been received from a peripheral.
If the receiver data register is full, the character is
placed on the 8-bit ACIA bus when a Read Data command is received from the MPU. The status register
can be read again to determine if another character
is available in the receiver data register. The receiver
is also double buffered so that a character can be read
from the data register as another character is being
received in the shift register. The above sequence
continues until all characters have been received.

3.108

ADVANCED PRODUCT DESCRIPTION

S6852
SYNCHRONOUS SERIAL
DATA ADAPTER (SSDA)
Features

General Description

Programmable Interrupts from Transmitter,
Receiver, and Error Detection Logic

Character Synchronization on One or Two
Sync Codes

External Synchronization Available for
Parallel- Serial Operation

o
o
o
o

The S6852 Synchronous Serial Data Adapter provides
a bi-directional serial interface for synchronous data
information interchange. It contains interface logic for
simultaneously transmitting and receiving standard
synchronous communications characters in bus organized systems such as the 86800 Microprocessor
systems.

Programmable Sync Code Register

o
o
o

Up to 600kbps Transmission
Peripheral/Modem Control Functions
Three Bytes of FIFO Buffering on Both
Transmit and Receive
Seven, Eight, or Nine Bit Transmission
Optional Even and Odd Parity
Parity, Overrun, and Underflow Status

The bus interface of the S6852 includes select, enable,
read/write, interrupt, and bus interface logic to allow
data transfer over an 8 -bit bi -directional data bus.
The parallel data of the bus system is serially transmitted and received by the synchronous data interface
with synchronization, fill character insertion/deletion,
and error checking. The functional configuration of
the SSDA is programmed via the data bus during
system initialization. Programmable control registers
provide control for variable word lengths, transmit
control, receive control, synchronization control, and
interrupt control. Status, timing and control lines
provide peripheral or modem control.
Typical applications include floppy disk controllers,
cassette or cartridge tape controllers, data communications terminals, and numerical control systems.

Block Diagram

Pin Configuration
ADDRESS/CONTROL
AND INTERRUPT

PERIPHERAL!
MODEM
CONTROL

RECEIVE
DATA
DATA BUS
I/O
TRANSMIT
DATA

3.109

I
~

56852
Maximum Ratings

Supply Voltage ........................................................... -0.3V to +7.0V
Input Voltage ............................................................ - 0.3V to +7.0V
Operating Temperature Range. . . . . . . . . . . . . .
. ............................. O°C to +70°C
Storage Temperature Range ...............
. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to +150°C
Thermal Resistance ......................
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. +70°C/W
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit.

Electrical Characteristics (Vee = +5.0V ±5%, VSS = 0, TA = O°C to 70°C unless otherwise noted.)
Symbol

Parameter

VIH

Input High Voltage

Min.

VIL

Input Low Voltage

lin

Input Leakage Current

ITSI

Three-State (Off State) Input Current

VOH

Output High Voltage

VOL

Typ.

Max.

Units

Conditions

Vdc

VSS + 2.0
VSS + 0.8

Vdc

1.0

2.5

J.LAdc

Yin = OVdc to 5.25Vdc

2.0

J.LAdc

Yin = Oo4Vdc to 204Vdc,
VCC= 5.25Vdc

Vdc

ILoad = - 205J.LAdc,
Enable Pulse Width <25J.Ls
ILoad = -100J.LAdc,
Enable Pulse Width <25J.Ls

VSS + 004

Vdc

ILoad = 1.6mAdc,
Enable Pulse Width <25!ls

1.0

!lAdc

300

525

DO-D7
Other Inputs

12.5
7.5

Yin = 0, TA = 25°C,
f= 1.0MHz

Tx Data, SM/DTR, TUF, IRQ

10
5.0

Yin = 0, TA = 25°C,
f= 1.0MHz

Tx CIk, Rx Clk, Rx Data, Enable,
Reset, RS, R/W, CS, DCD,CTS
DO·D7
DO·D7

VSS+204

Tx Data, DTR, TUF

VSS + 204

Output Low Voltage

ILOH

Output Leakage Current (Off State)

Power Dissipation

IRQ

Cin

Input Capacitance

Cout

Output Capacitance

PWCL

Minimum Clock Pulse Width, Low

700

Figure 1

PWCH

Minimum Clock Pulse Width, High

700

Figure 2

600

VOH = 204Vdc

kHz

Clock Frequency

tROSU

Receive Data Setup Time

350

tROH

Receive Data Hold Time

350

Figure 3

tSM

Sync Match Delay Time

1.0

!lS

Figure 3
Figure 4

Figure 3,7

tTOO

Clock-to-Data Delay for Transmitter

1.0

!lS

tTUF

Transmitter Underflow

1.0

J.LS

Figure 4,6

tOTR

DTR Delay Time

1.0

!lS

Figure 5

!lS

Figure 5

tIR

Interrupt Request Release Time

tRes

Reset Minimum Pulse Width

tCTS

CTS Setup Time

200

toco
t r , tf

DCD Setup Time

500'

Figure 7

Input Rise and Fall Times (except Enable)

1.0*

J.LS

0.8V to 2.0V

1.2
1.0

!lS
Figure 6

*1.0!1S or 10% of the pulse width, whichever is smaller.

Figure 2. Clock Pulse Width, High-State'

Figure 1. Clock Pulse Width, Low-State
PWCl

Tx Clk
OR
Rx Clk

2.DV

TxClk
OR
Rx Clk
_ P W CH

3.110

56852
Bus Timing Characteristics
Read

Symbol

Parameter

Min.

Typ.

Max.

Unit

tcycE
PWEH

Enable Cycle Time

1.0

Enable Pulse Width, High

0.45

PWEL

Enable Pulse Width, Low

0.43

J.1S

tAS

Setup Time, Address and RjW valid
to Enable positive transition

160

tDDR

Data Delay Time

Data Hold Time

tAH

Address Hold Time

tEr, tEf

Rise and Fall Time for Enable input

Conditions

J.1S

320

jiS

Figures
8 and 10

ns
ns
ns

Max.

Unit

Write

Symbol

Parameter

Min.

tcycE

Enable Cycle Time

1.0

PWEH

Enable Pulse Width, High

0.45

PWEL

Enable Pulse Width, Low

0.43

f.1.S

tAS

Setup Time, Address and RjW valid
to Enable positive transition

160

tDSW

Data Setup Time

195

Data Hold Time

tAH

Address Hold Time
Rise and Fall Time for Enable input

tEr, tEf

Typ.

f.1.S

Rx Clk

Rx DATA

n = NUMBER OF BITS IN CHARACTER
[SS1=DON'TCARE
SYNC MATCH

3.111

f.1.S

ns
25

Figure 3. Receive Data Setup and Hold Times and Sync
Delay Time

Conditions

Figures
9 and 10

56852

Figure 4. Transmit Data Output Delay and Transmitter
Underflow Delay Time
Tx
Clk

Figure 5. Data Terminal
Release Times

Ready and Interrupt Request

2.0V
O.8V

ENABLE

Tx
DATA

IIR-)I---,
TUF

2.4V

------------------~
n = NUMBEA OF BITS IN CHAAACTEA

Figure 6. Clear-To-Send Setup Time

ill

Figure 7. Data Carrier Detect Setup Time

)u,

O.8V

Ax Clk

Ix elk

Tx DATA

O.BV

Figure 8. Bus Read Timing Characteristics
(Read Information from SSDA)

Ax DATA

~
O.BV

Figure 9. Bus Write Timing Characteristics
(Write Information into SSDA)
~-----lcycE-----l~

ENABLE
ENABLE

AS,Cs, A/W
RS, (;S, A/W

DATA BUS

3.112

56852
Figure 10. Bus Timing Test Loads

100-07,

LOAD B
(iRfiONLY)

LOAD A
DATA, TUF)

ilfA, Tx

5'OV

5.0V

~f'"'
3k

TEST POINT

-_-,.---+

0-__

MM06150
OR EnUIV.

TEST POINT

MM07000
OR EnUIV.

C = 130pF FOR 00-07
= 30pF FOR lffR, Tx DATA, AND TUF

R = 11.7kn FOR 00·07
= 24kn FOR ilfA, Tx DATA, AND TUF

Expanded Block Diagram

ENABLE

REAO,wRITE

1 - - - - - - - - - - - ' -....
REGISTER SELECT

. , . . . - - - - - - - - -...... 8
...---'-.............,
1+-.--------24

TRANSMIT
DATA
TRANSMITTER
UNDERFLOW
CLEAR·TO·SENO

mET

RECEIVE
DATA
RECEIVE
CLOCK

3.113

SYNC
MATCHI
DATA TERMINAL
READY

S6852
Device Operation

Other I/O lines, in addition to Clear-to-Send (CTS)
and Data Carrier Detect (i5CD), include SM/DTR
At the bus interface, the SSDA appears as two ad- (Sync Match/Data Terminal Ready) and Transmitter
dressable memory locations. Internally, there are seven Underflow (TUF). The transmitter and receiver each
registers: two read-only and five write-only registers. have individual clock inputs allowing simultaneous
The read-only registers are Status and Receive Data; operation under separate clock control. Signals to the
the write-only registers are Control 1, Control 2, Con- microprocessor are the Data bus and Interrupt
trol 3, Sync Code and Transmit Data. The serial inter- Request (IRQ).
face consists of serial input and output lines with
independent clocks, and four peripheral/modem Initial ization
control lines.
Data to be transmitted is transferred directly into the During a power-on sequence, the SSDA is reset via
3-byte Transmit Data First-In First-Out (FIFO) the Reset input and internally latched in a reset conRegister from the data bus. Availability of the input dition to prevent erroneous output transitions. The
to the FIFO is indicated by a bit in the Status Register; Sync Code Register, Control Register 2, and Control
once data is entered, it moves through the FIFO to Register 3 should be programmed prior to the prothe last empty location. Data at the output of the grammed release of the Transmitter and/or Receiver
FIFO is automatically transferred from the FIFO to Reset bits; these bits in Control Register 1 should be
the Transmitter Shift Register as the shift register cleared after the Reset line has gone high.
becomes available to transmit the next character. If
data is not available from the FIFO (underflow con- Transmitter Operation
dition), the Transmitter Shift Register is automatically
loaded with either a sync code or an all "l"s character. Data is transferred to the transmitter section in parallel
The transmit section may be programmed to append form by means of the data bus and Transmit Data
loaded with either a sync code or an all "l"s character. FIFO. The Transmit Data FIFO is a 3 -byte register
The transmit section may be programmed to append whose status is indicated by the Transmitter Data
even, odd, or no parity to the transmitted word. An Register Available status bit (TDRA) and its associated
external control line (Clear-to-Send) is provided to interrupt enable bit. Data is transferred through the
FIFO on Enable (E) pulses. Two data transfer modes
inhibit the transmitter without clearing the FIFO.
are provided in the SSDA. The 1-byte transfer mode
Serial data is accumulated in the receiver based on the provides for writing data to the transmitter section
synchronization mode selected. In the external sync
(and reading from the receiver section) one byte at a
mode, used for parallel-serial operation, the receiver
time. The 2-byte transfer mode provides for writing
is synchronized by the DCD (Data Carrier Detect)
two data characters in succession.
input and transfers successive bytes of data to the
input of the Receiver FIFO. The single-sync-character Data will automatically transfer from the last register
mode requires that a match occur between the Sync location in the Transmit Data FIFO (when it contains
Code Register and one incoming character before data data) to the Transmitter Shift Register during the last
transfer to the FIFO begins. The two-sync-character half of the last bit of the previous character. A character
mode requires that two sync codes be received in se- is transferred into the Shift Register by the Transmitter
quence to establish synchronization. Subsequent to Clock. Data is transmitted LSB first, and odd or even
synchronization in any mode, data is accumulated in parity can be optionally appended. The unused bit
the shift register, and parity is optionally checked. An positions in short word length characters from the
indication of parity error is carried through the data bus are "don't cares." (Note: The data bus inputs
Receiver FIFO with each character to the last empty may be reversed for applications requiring the MSB
location. Availability of a word at the FIFO output to be transferred first, e.g., IBM format for floppy
is indicated by a bit in the Status Register, as is a disks; however, care must be taken to properly program
the control registers - Table 1 will have its bit posiparity error.
The SSDA and its internru registers are selected by tions reversed.)
the address bus, Read/Write (R/W) and Enable control
lines. To configure the SSDA, Control Registers are
selected and the appropriate bits set. The Status Register is addressable for reading status.

When the Shift Register becomes empty and data is

-not available for transfer from the Transmit Data
FIFO, an "underflow" occurs, and a character is
inserted into the transmitter data stream to maintain

3.114

56852
character synchronization. The character transmitted
on underflow will be either a "Mark" (all "l"s) or
the contents of the Sync Code Register, depending
upon the state of the Transmit Sync Code on Underflow control bit. The underflow condition is indicated
by a pulse C"" 1 Tx Clk high period) on the Underflow
output (when in Tx Sync on underflow mode). The
Underflow output occurs coincident with the transfer
of the last half of the last bit preceding the underflow
character. The Underflow status bit is set until cleared
by means of the Clear Underflow control bit. This
output may be used in floppy disk systems to synchronize write operations and for appending CRCC.

to establish character synchronization. This requires
the detection of a single code or two successive sync
codes. Floppy disk and cartridge tape units require
sixteen bits of defined preamble and cassettes require
eight bits of preamble to establish the reference for
the start of record. All three are functionally equivalent to the detection of sync codes. Systems which do
not utilize code detection techniques require custom
logic external to the SSDA for character synchronization and use of the parallel-to-serial (external sync)
mode. (Note: The Receiver Shift Register is set to
ones when reset.)

Transmission is initiated by clearing the Transmitter
Reset bit in Control Register 1. When the Transmitter
Reset bit is cleared, the first full positive half-cycle of
the Transmit Clock will initiate the transmit cycle,
with the transmission of data or underflow characters
beginning on the negative edge of the Transmit Clock
pulse which started the cycle. If the Transmit Data
FIFO was not loaded, an underflow character will be
transmitted (see Figure 4).

Synchronization

The SSDA provides three operating modes with respect
to character synchronization: - one-sync-character
mode, two-sync-character mode, and external sync
mode. The external sync mode requires synchronization and control of the receiving section through the
Data Carrier Detect (DCD) input (see Figure 7). This
external synchronization could consist of direct line
control from the transmitting end of the serial data
.The Clear-to-Send (CTS) input provides for automatic iink or from external logic designed to detect the start
control of the transmitter by means of external system of the message block. The one-sync-character mode
hardware; e.g., the modem CTS output provides the searches on a bit- by -bit basis until a match is achieved
control in a data communications system. The CTS between the data in the Shift Register and the Sync
input resets and inhibits the transmitter section when Code Register. The match indicates character synchrohigh, but does not reset the Transmit Data FIFO. The nization is complete and will be retained for the
TD RA status bit is inhibited by CTS being high in message block. In the two-sync-character mode, the
either the one -sync -character or two -sync -character receiver searches for the first sync code match on a
mode of operation. In the external sync mode, TDRA bit -by -bit basis and then looks for a second successive
is unaffected by CTS in order to provide Transmit sync code character prior to establishing character
Data FIFO status for preloading and operating the synchronization. If the second sync code character is
transmitter under the control of the CTS input. When not received, the bit -by -bit search for the first sync
the Transmitter Reset bit (Tx Rx) is set, the Transmit code is resumed.
Data FIFO becomes available for new data with
Sync codes received prior to the completion of synTDRA inhibited.
chronization (one or two character) are not transferred
to the Receive Data FIFO. Redundant sync codes
Receiver Operation
during the preamble or sync codes which occur as
Data and a presynchronized clock are provided to the "fill characters" can automatically be stripped from
SSDA receiver section by means of the Receive Data the data, when the Strip Sync control bit is set, to
(Rx Data) and Receive Clock (Rx Clk) inputs. The minimize system loading. The character synchronizadata is a continuous stream of binary data bits without tion will be retained until cleared by means of the
means for identifying character boundaries within the Clear Sync bit, which also inhibits synchronization
stream. It is, therefore, necessary to achieve character search when set.
synchronization for the data at the beginning of the
data block. Once synchronization is achieved, it is
assumed to be retained for all successive characters
within the block.

Receiving Data

Once synchronization has been achieved, subsequent
characters are automatically transferred into the ReData communications systems utilize the detection of ceive Data FIFO and clocked through the FIFO to
sync codes during the initial portion of the preamble the last empty location by E pulses (MPU System 2).

3.115

56852
The Receiver Data Available status bit (RDA) indicates
when data is available to be read from the last FIFO
location (#3) when in the 1-byte transfer mode. The
2-byte transfer mode causes the RDA status bit to
indicate data is available when the last two FIFO register locations are full. Data being available in the Receive
Data FIFO causes an interrupt request if the Receiver
Interrupt Enable (RIE) bit is set. The MPU will then
read the SSDA Status Register, which will indicate
that data is available for the MPU read from the Receive Data FIFO register. The IRQ and RDA status
bits are reset by a read from the FIFO. If more than
one character has been received and is resident in the
Receive Data FIFO, subsequent E clocks will cause
the FIFO to update and the RDA and IRQ status bits
will again be set. The read data operation for the
2-byte transfer mode requires an intervening E clock
between reads to allow the FIFO data to shift. Optional parity is automatically checked as data is received,
and the parity status condition is maintained with
each character until the data is read from the Receive
,Data FIFO. Parity errors will cause an interrupt request
if the Error Interrupt Enable (EIE) has been set. The
parity bit is not transferred to the data bus but must
be checked in the Status Register. NOTE: In the
2-byte transfer mode, parity should be checked prior
to reading the second byte, since a FIFO read clears
the error bit.
Other status bits which pertain to the receiver section
are Receiver Overrun and Data Carrier Detect (DCD).
The Overrun status bit is automatically set when a
transfer of a character to the Receive Data FIFO
occurs and the first register of the Receive Data FIFO
is full. Overrun causes an interrupt if Error Interrupt
Enable (EIE) has been set. The transfer of the overrunning character into the FIFO causes the previous
character in the FIFO input register location to be lost
The Overrun status bit is cleared by reading the Status
Register (when the overrun condition is present), followed by a Receive Data FIFO Register read. Overrun
cannot occur and be cleared without providing an
opportunity to detect its occurrence via the Status
Register.

Chip Select (CS)- This high impedance TTL compatible input line is used to address the SSDA. The SSDA
is selected when CS is low. VMA should be used in
generating the CS input to insure that false selects will
not occur. Transfers of data to and from the SSDA
are then performed under the control of the Enable
signal, Read/Write, and Register Select.

A positive transition on the DCD input causes an
interrupt if the EIE control bit has been set. The
interrupt caused by .DCD is cleared by reading the
Status Register when the DCD status bit is high, followed by a Receive Data FIFO read. The DCD status
bit will subsequently follow the state of the DCD
input when it goes low.

Register Select (RS) - The Register Select line is a
high impedance input that is TTL compatible. A high
level is used to select Control Registers C2 and C3,
the Sync Code Register, and the Transmit/Receive
Data Registers. A low level selects the Control 1 and
Status Registers (see Table 1).

Input/Output Functions
SSDA Interface Signals for MPU

The SSDA interfaces to the S6800 MPU with an 8- bit
bi-directional data bus, a chip select line, a register
select line, an interrupt request line, read/write line,
an enable line, and a reset line. These signals, in conjunction with the S6800 VMA output, permit the
MPU to have complete control over the SSDA.
SSDA Bi-Directional Data (DO-D7)-The bi-directional
data lines (DO-D7) allow for data transfer between
the SSDA and the MPU. The data bus output drivers
are three-state devices that remain in the high-impedance (off) state except when the MPU performs an
SSDA read operation.
SSDA Enable (E) - The Enable signal, E, is a high
impedance TTL compatible. input that enables the
bus input/output data buffers, clocks data to and
from the SSDA, and moves data through the FIFO
Registers. This signal is normally the continuous S6800
System 2 clock, so that incoming data characters are
shifted through the FIFO.
Read/Write (R/W) - The Read/Write line is a hi~h
impedance input that is TTL compatible and is used
to control the direction of data flow through the
SSDA's input/output data bus interface. When Read/
Write is high (MPU read cycle), SSDA output drivers
are turned on if the chip is selected and a selected
register is read. When it is low, the SSDA output drivers
are turned off and the MPU writes into a selected
register. The Read/Write signal is also used to select
read-only or write-only registers within the SSDA.

3.116

86852
Table 1. SSDA Programming Model
CONTROL
INPUTS

AOORESS
CONTROL

RiW

AC2

AC1

BIT 7

BIT6

BIT 5

BIT4

BIT 3

BIT2

BIT 1

BIT 0

STATUS (S)

INTERRUPT
REQUEST
(IRQ)

RECEIVER
PARITY
ERROR
(PE)

RECEIVER
OVERRUN
(Rx Ovrn)

TRANS·
MITTER
UNDERFLbw
(TUF)

CLEAR·TO·
SEND
(CTS)

OATA
CARRIER
DETECT
(DCD)

TRANS·
MITTER
DATA
REGISTER
AVAILABLE
(TDRA)

RECEIVER
DATA
AVAILABLE
(RDA)

CONTROL 1
(Cl)

ADDRESS
CONTROL 2
(AC2)

ADDRESS
CONTROL 1
(AC1)

RECEIVER
INTERRUPT
ENABLE
(RIE)

TRANSMITTER
INTERRUPT
ENABLE
(TIE)

CLEAR
SYNC

STRIP SYNC
CHARACTERS
(STRIP SYNC)

TRANSMITTER
RESET
(Tx Rs)

RECEIVER
RESET
(Rx Rs)

RECEIVE
DATA FIFO

CONTROL2
(C2)

ERROR
INTERRUPT
ENABLE
(EIE)

TRANSMIT
SYNC CODE
ON
UNDERFLOW
(Tx Sync)

WORD
LENGTH
SELECT 3
(WS3)

WORD
LENGTH
SELECT 2
(WS2)

WORD
LENGTH
SELECT 1
(WS1)

l-BYTE/
2-BYTE
TRANSFER
(l-BYTE/
2-BYTE)

CONTROL 3
(C3)

NOT USED

SYNC CODE

TRANSMIT
DATA FIFO

PERIPHERAL PERIPHERAL
CONTROL 2 CONTROL 1
(PC2)
(PC1)

EXTERNAL/
ONE-SYNCCLEAR CTS
CLEAR
TRANSSTATUS
CHARACTER/ INTERNAL
(CLEAR CTS) TWO-SYNC- SYNC MODE
MITTER
CHARACTER
.CONTROL
UNDERFLOW
MODE
(E/I Sync)
STATUS
(CTUF)
CONTROL
(1 Sync/
2 Sync)

X = DON'T CARE

Status Register
IRQ Bit 7

The IRQ flag is cleared when the source
of the IRQ is cleared. The source is determined by the enables in the Control
Registers: TIE, RIE, EIE.

RIE

Bit 5 When "1", enables interrupt on
RDA (S Bit 0).

TIE

Bit 4 When "I", enables interrupt on
TDRA (S Bit 1).

Clear Sync

Bits 6-0

indicate the SSDA status at a point in
time, and can be reset as follows:

Bit 3 When "1", clears receiver character synchronization.

Strip Sync

Bit 6 Read Rx Data FIFO, or a "I"
into Rx Rs (Cl Bit 0).

Bit 2 When "I", strips all sync codes
from the received data stream.

Tx Rs

Rx Ovrn

Bit 5 Read Status and then Rx Data
FIFO, or a "I" into Rx Rs (Cl
Bit 0).

Bit 1 When "I", resets and inhibits the
transmitter section.

Rx Rs

Bit 0 When "1", resets and inhibits the
receiver section.

Bit 4 A "I" into CTUF (C3 Bit 3) or
into Tx Rs (Cl Bit 1).

Control Register 3

TUF

Bit 3 A "I" into ClearCTS (C3 Bit 2)
or a "I" into Tx Rs (Cl Bit 1)

CTUF

Bit 3 When "I", clears TUF (S Bit 4),
and IRQ if enabled.

Clear CTS

Bit 2 When "I", clears CTS (S Bit 3),
and IRQ if enabled.

1 Sync/2 Sync

TDRA

Bit 2 Read Status and then Rx Data
FIFO or a "I" into Rx Rs (Cl
Bit 0)
Bit 1 Write into Tx Data FIFO.

RDA

Bit 0 Read Rx Data FIFO.

Bit 1 When "I", selects the one-synccharacter mode; when "0", selects the two -sync -character
mode.
Bit 0 When "1", selects the external
sync mode; when "0", selects
the internal sync mode.

Control Register 1
AC2, ACI
Bits 7, 6 Used to access other registers,
as shown above.

3.117

E/I Sync

56852
Control Register 2
EIE

Bit 7 When "1", enables the PE, Rx
Ovrn, TUF, CTS, and DCD interrupt flags (S Bits 6 through 2).

Tx Sync

Bit 6 When "I", allows sync code
contents to be transferred on
underflow, and enables the TUF
Status bit and output. When "0",
an all mark character is transmitted on underflow.

WS3, 2, 1

PC2,PC1

Bits 5-3 Word Length Select

BIT 5
WS3

BIT 4
WS2

BIT 3
WS1

WORD LENGTH

6 BITS + EVEN PARITY

6 BITS + 0 DO PAR ITY

7 BITS

8 BITS

1
1
1
1

7 BITS + EVEN PAR ITY

7 BITS + 0 DO PAR ITY

1
1

8 BITS + EVEN PAR ITY

8 BITS + ODD PARITY

Bit 2 When "1", enables the TDRA
and RDA bits to indicate when
a I-byte transfer can occur;
when "0", the TDRA and RDA
bits indicate when a 2 -byte
transfer can occur.

1-Byte/
2-Byte

Bits 1- 0 SM/DTR Output Control

BIT 1
PC2

BIT 0
PC1

0
0

1
1

SM/DTR 0 UTPUT AT PIN 5

PULSE

J L l-BITWIDE ON SM
0
SM INHIBITED, 0

Note: When the SSDA is used in applications
requiring the MSB of data to be received and
transmitted first, the data bus inputs to the
SSDA may be reversed (DO to D7, etc.) Caution
must be used when this is done since the bit
positions in this table will be reversed, and the
parity should not be selected.

Interrupt Request (IRQ) - Interrupt Request is a
TTL compatible, open-drain (no internal pullup),
active low output that is used to interrupt the MPU.
The Interrupt Request remains low until cleared by
the MPU.
Reset Input - The Reset input provides a means of
resetting the SSDA from an external source. In the
low state, the Reset input causes the following:
1. Receiver Reset (Rx Rs) and Transmitter Reset

(Tx Rs) bits are set causing both the receiver and
transmitter sections to be held in a reset condition.
2. Peripheral Control bits PC1 and PC2 are reset to
zero, causing the SM/DTR output to be high.
3. The Error Interrupt Enable (EIE) bit is reset.
4. An internal synchronization mode is selected.
5. The Transmitter Data Register Available (TDRA)
status bit is cleared and inhibited.

Clock Inputs

Separate high impedance TTL compatible inputs are
provided for clocking of transmitted and received data.
Transmit Clock (Tx Clk) - The Transmit Clock input
is used for the clocking of transmitted data. The transmitter shifts data on the negative transition of the
clock.
Receive Clock (Rx Clk) - The Receive Clock input is
used for clocking in received data. The clock and data
must be synchronized externally. The receiver samples
the data on the positive transition of the clock.
Serial Input/Output Lines

Receive Data (Rx Data) - The Receive Data line is a
high impedance TTL compatible input through which
data is received in a serial format. Data rates are from
0 to 600 kbps.

Transmit Data (Tx Data) - The Transmit Data output
When Reset returns high (the inactive state), the trans- line transfers serial data to a modem or other periphmitter and receiver sections will remain in the reset eral. Data rates are from 0 to 600 kbps.
state until the Receiver Reset and Transmitter Reset
Peripheral/Modem Control
bits are cleared via the bus under software control.
The control Register bits affected by Reset (Rx Rs, The SSDA includes several functions that permit
Tx Rs, PC1, PC2, EIE, and E/I Sync) cannot be limited control of a peripheral or modem. The functions included are Clear-to-Send, Sync Match/Data
changed when Reset is low.

3.118

56852
Terminal Ready, Data Carrier Detect, and Transmitter
Underflow.

character" to the Transmitter Shift Register when the
last location (#3) in the Transmit Data FIFO is empty.
The Underflow output pulse is approximately a Tx
Clk high period wide and occurs during the last half
of the last bit of the character preceding the "Underflow" (see Figure 4). The Underflow output does not
respond to underflow conditions when the Tx Sync
bit is in the reset state.

Clear-to-Send (CTS) - The CTS input provides a realtime inhibit to the transmitter section (the Tx Data
FIFO is not disturbed). A positive CTS transition resets
the Tx Shift Register and inhibits the TDRA status
bit and its associated interrupt in both the one-synccharacter and two-sync-charactermodes of operation.
TDRA is not affected by the CTS input in the external
sync mode.
SSDA Registers
The positive transition of CTS is stored within the
SSDA to insure that its occurrence will be acknowl- Seven registers in the SSDA can be accessed by means
edged by the system. The stored CTS information of the bus. The registers are defined as read-only or
and its associated IRQ (if enabled) are cleared by write-only according to the direction of information
writing a "1" in the Clear CTS bit in Control Register flow. The Register Select input (RS) selects two regis3 or in the Transmitter Reset bit. The CTS status bit ters in each state, one being read -only and the other
subsequently follows the CTS input when it goes low. write-only. The Read/Write input (R/W) defines which
The CTS input provides character timing for trans- of the two selected registers will actually be accessed.
mitter data when in the external sync mode. Trans- Four registers (two read-only and two write-only)
mission is initiated on the negative transition of the can be addressed via the bus at any particular time.
first full positive clock pulse of the transmitter clock These registers and the required addressing are defined
in Table 1.
(Tx Clk) after the release of CTS (see Figure 6).
Data Carrier Detect (DCD) - The DCD input provides Control Register 1 (C1)
a real- time inhibit to the receiver section (the Rx FIFO
is not disturbed). A positive DCD transition resets
and inhibits the receiver section except for the Receive
FIFO and the RDRA status bit and its associated IRQ.
The positive transition of DCD is. stored within the
SSDA to insure that its occurrence will be acknowledged by the system. The stored DCD information
and its associated IRQ (if enabled) are cleared by reading the Status Register and then the Receiver FIFO,
or by writing a "1" into the Receiver Reset bit. The
DCD status bit subsequently follows the DCD input
when it goes low. The DCD input provides character
synchronization timing for the receiver duringthe external sync mode of operation. The receiver will be
initialized and data will be sampled on the positive
transition of the first full Receive Clock cycle after
release of DCD (see Figure 7).
Sync Match/Data Terminal Ready (SM/DTR) - The
SM/DTR output provides four functions (see Table 1)
depending on the state of the PC1 and PC2 control
bits. When the Sync Match mode is selected (PC1 =
"1", PC2 = "0"), the output provides a one-bit-wide
pulse when a sync code is detected. The SM output is
inhibited when PC2 = "1". The DTR mode (PC1 = "0")
provides an output level corresponding to the complemen't of PC2 (DTR= "0" when PC2 = "1"). (See
Table 1.)
Transmitter Underflow (TUF) - The Underflow output indicates tbe occurrence of a transfer of a "fill

Control Register 1 is an 8 - bit write -only register that
can be directly addressed from the data bus. Control
Register 1 is addressed when RS = "0" and R/W = "0".
Receiver Reset (Rx Rs), C1 Bit 0 - The Receiver
Reset control bit provides both a reset and inhibit
function to the receiver section. When Rx Rs is set, it
clears the receiver control logic, sync logic, error logic,
Rx Data FIFO, Parity Error status bit, and DCD interrupt. The Receiver Shift Register is set to ones.
The Rx Rs bit must be cleared after the occurrence of
a low level on Reset in order to enable the receiver
section of the SSDA.
Transmitter Reset (Tx Rs), C1 Bit 1- The Transmitter
Reset control bit provides both a reset and inhibit to
the transmitter section. When Tx Rs is set, it clears
the transmitter control section, Transmitter Shift
Register, Tx Data FIFO (which can be reloaded after
one E clock pulse), the Transmitter Underflow status
bit, and the CTS interrupt, and inhibits the TDRA
status bit (in the one-sync-character and two-synccharacter modes). The Tx Rs bit must be cleared after
the occurrence of a low level on Reset in order to
enable the transmitter section of the SSDA.
Strip Synchronization Characters (Strip Sync), C1
Bit 2 - If the Strip Sync bit is set, the SSDA will
automatically strip all received characters which match
the contents of the Sync Code Register. The characters
used for synchronization (one or two characters of
sync) are always stripped from the received data stream.

3.119

56852
Clear Synchronization (Clear Sync), C1 Bit 3 - The
Clear Sync control bit provides the capability of
dropping receiver character synchronization and inhibiting resynchronization. The Clear Sync bit is set
to clear and inhibit receiver synchronization in all
modes and is reset to zero to enable resynchronization.

Alternately, if 1-Byte/2-Byte is reset, the TDRA and
RDA status bits indicate when two bytes of data can
be moved without a second status read. An intervening
Enable pulse must occur between data transfers.

Receiver Interrupt Enable (RIE), C1 Bit 5 - RIE enables both the Interrupt Request output (IRQ) and
the Interrupt Request status bit to indicate a receiver
service request. When RIE is set and the RDA status
bit is high, the IRQ output will go low (the active
state) and the IRQ status bit will go high.

will transmit a Mark character (including the parity
bit position) on underflow. When the underflow is detected, a pulse approximately a Tx Clk high period
wide will occur on the underflow output if the Tx
Sync bit is set. Internal parity generation is inhibited
during underflow except for sync code fill character
transmission in 8-bit plus parity word lengths.
Error Interrupt Enable (EIE), C2 Bit 7 - When EIE is
set, the IRQ status bit will go high and the IRQ output will go low if:

Word Length Selects (WS1, WS2, WS3), C2 Bits 3,4, 5
- Word Length Select bits WS1, WS2, and WS3 select
Transmitter Interrupt Enable (TIE), C1 Bit 4 - TIE word length of 7,8, or 9 bits including parity as shown
enables both the Interrupt Request output (IRQ) and in Table 1.
Interrupt Request status bit to indicate a transmitter Transmit Sync Code on Underflow (Tx Sync), C2 Bit
service request. When TIE is set and the TDRA status 6 - When Tx Sync is set, the transmitter will automatbit is high, the IRQ output will go low (the active ically send a sync character when data is not available
state) and the IRQ status bit will go high.
for transmission. If Tx Sync is reset, the transmitter

Address Control 1 (ACl) and Address Control 2
(AC2), C1 Bits 6 and 7 - AC1 and AC2 select one of
the write-only registers - Control 2, Control 3, Sync
Code, or Tx Data FIFO - as shown in Table 1, when
RS = "I" and R/W = "0".
1. A receiver overrun occurs. The interrupt is cleared
by reading the Status Register and reading the Rx
Control Register 2 (C2)
Data FIFO.
Control Register 2 is an 8-bit write-only register

which can be programmed from the bus when the 2. DCD input has gone to a "1". The interrupt is
Address Control bits in Control Register 1 (AC1 and
cleared by reading the Status Register and reading
AC2) are reset, RS = "I" and R/W = "0".
the Rx Data FIFO.
Peripheral Control 1 (PC1) and Peripheral Control 2
(PC2), C2 Bits 0 and 1 - Two control bits, PCl and
PC2, determine the operating characteristics of the
Sync Match/DTR output. PC1, when high, selects
the Sync Match mode. PC2 provides the inhibit/enable
control for the SM/DTR output in the Sync Match
mode. A one- bit-wide pulse is generated at the output
when PC2 is "0", and a match occurs between the
contents of the Sync Code Register and the incoming
data even if sync is inhibited (Clear Sync bit = "1 ").
The Sync Match pulse is referenced to the negative
edge ofRx Clk pulse causing the match (see Figure 3).
The Data Terminal Ready (DTR) mode is selected
when PC1 is low. When PC2 = "I" the SM/DTR
output = "0" and vice versa. The operation of PC2
and PC1 is summarized in Table 1.

3. A parity error exists for the character in the last
location (#3) of the Rx Data FIFO. The interrupt
is cleared by reading the Rx Data FIFO.
4. The CTS input has gone to a "I". The interrupt is
cleared by writing a "1" in the Clear CTS bit, C3
bit 2, or by a TX Reset.
5. The transmitter has underflowed (in the Tx Sync
on Underflow mode). The interrupt is cleared by
writing a "1" into the Clear Underflow, C3 bit 3,
or Tx Reset.
When EIE is a "0", the IRQ status bit and the IRQ
output are disabled for the above error conditions. A
low level on the Reset input resets EIE to "0".
Control Register 3 (C3)

l-Byte/2-Byte Transfer (1-Byte/2-Byte), C2 Bit 2 - Control Register 3 is a 4-bit write-only register which
When 1-Byte/2-Byte is set, the TDRA and RDA can be programmed from the bus when RS = "I" and
status bits will indicate the availability of their respec- R/W = "0" and Address Control bit AC1 = "1" and
tive data FIFO registers for a single byte data transfer. AC2 = "0".

3.120

56852
External/Internal Sync Mode Control (E/I Sync), C3 not utilized for receiver character synchronization in
Bit 0 - When the E/I Sync Mode bit is high, the the external sync mode; however, it provides storage
SSDA is in the external sync mode and the receiver of receiver match and transmit fill characters.
synchronization logic is disabled. Synchronization The Sync Code Register can be loaded when AC2 and
can be achieved by means of the DCD input or by AC1 are a "I" and "0", respectively, and R/W = "0"
starting Rx Clk at the midpoint of data bit 0 of a and RS - "I".
character with DCD low. Both the transmitter and
receiver sections operate as parallel - serial converters The Sync Code Register may be changed ·after the dein the External Sync mode. The Clear Sync bit in tection of a match with the received data (the first
Control Register 1 acts as a receiver sync inhibit when sync code having been detected) to synchronize with
high to provide a bus controllable inhibit. The Sync a double-word sync pattern. (This sync code change
Code Register can serve as a transmitter fill character must occur prior to the completion of the second
register and a receiver match register in this mode. A character.) The sync match (8M) output can be used
"low" on the Reset input resets the E/I Sync Mode to interrupt the MPU system to indicate that the first
eight bits have matched. The service routine would
bit placing the SSDA in the internal sync mode.
then change the sync match register to the second half
One -Sync -Character /Two -Sync -Character Mode Con- of the pattern. Alternately, the one-sync-character
trol (1 Sync/2 Sync), C3 Bit 1 - When the 1 Sync/ mode can be used for sync codes for 16 or more bits
2 Sync bit is set, the SSDA will synchronize on a single by using software to check the second and subsequent
match between the received data and the contents of bytes after reading them from the FIFO.
the Sync Code Register. When the 1 Sync/2 Sync bit The detection of the sync code can be programmed
is reset, two successive sync characters must be received to appear on the Sync MatchfDTR output by writing
prior to receiver synchronization. If the second sync a "I" in PC1 (C2 bit 0) and a "0" in PC2 (C2 bit 1).
character is not detected, the bit by bit search resumes The Sync Match output will go high for one bit time
from the first bit in the second character. See the des- beginning at the character interface between the sync
cription of the Sync Code Register for more details.
code and the next character (see Figure 3).
Clear CTS Status (Clear CTS), C3 Bit 2 - When a "I"
is written into the Clear CTS bit, the stored status
and interrupt are cleared. Subsequently, the CTS
status bit reflects the state of the CTS input. The
Clear CTS control bit does not affect the CTS input
nor its inhibit of the transmitter section. The Clear
CTS command bit is self-clearing, and writing a "0"
into this bit is a nonfunctional operation.

Receive Data First-In First-Out Register (Rx Data
FIFO)

from the received data (a programmable option) as
well as automatic insertion of fill characters in the
transmitted data stream. The Sync Code Register is

Unused data bits for short word lengths (including the
parity bit) will appear as "O"s on the data bus when
the Rx Data FIFO is read.

The Receive Data FIFO Register consists of three
8 -bit registers which are used for buffer storage of received data. Each 8 -bit register has an internal status
bit which monitors its full or empty condition. Data
is always transferred from a full register to an adjacent
empty register. The transfer from register to register
occurs on E pulses. The RDA status bit will be high
Clear Transmit Underflow Status (CTUF), C3 Bit 3when data is available in the last location of the Rx
When a "1" is written into the CTUF status bit, the Data FIFO.
CTUF bit and its associated interrupt are reset. The
CTUF command bit is self-clearing and writing a "0" In an Overrun condition, the overrunning character
will be transferred into the full first stage of the FIFO
into this bit is a nonfunctional operation.
register and will cause the loss of that data character.
Successive overruns continue to overwrite the first
Sync Code Register
The Sync Code Register is an 8 -bit register for storing register of the FIFO. This destruction of data is inthe programmable sync code required for received data dicated by means of the Overrun status bit. The Overcharacter synchronization in the one-sync-character run bit will be set when the overrun occurs and
and two-sync-character modes. The Sync Code Regis- remains set until the Status Register is read, followed
ter also provides for stripping the sync/fill characters by a read of theRx Data FIFO.

3.121

S6852
Transmit Data First-In First-Out Register (Tx Data 2 -byte transfer mode. The Tx Data FIFO can be
loaded with two bytes without an intervening status
FIFO)
The Transmit Data FIFO Register consists of three read; however, one E pulse must occur between loads.
8 -bit registers which are used for buffer storage of TDRA is inhibited by the Tx Reset or Reset. When
data to be transmitted~ Each 8-bit register has an in- Tx Reset is set, the Tx Data FIFO is cleared and then
ternal status bit which monitors its full or empty con- released on the next E clock pulse. The Tx Data
dition. Data is always transferred from a full register FIFO can then be loaded with up to three characters
to an adjacent empty register. The transfer is clocked of data, even though TDRA is inhibited. This feature
allows preloading data prior to the release of Tx Reset.
by E pulses.
A high level on the CTS input inhibits the TDRA
The TDRA status bit will be high if the Tx Data FIFO status bit in either sync mode of operation (one -syncis available for data.
character or two-sync-character). CTS does not affect
Unused data bits for short word lengths will be han- TDRA in the external sync mode. This enables the
dled as "don't cares". The parity bit is not transferred SSDA to operate under the control of the CTS input
over the data bus since the SSDA generates parity at with TDRA indicating the status of the Tx Data
transmission.
FIFO. The CTS input does not clear the Tx Data
When an Underflow occurs, the Underflow character FIFO in any operating mode.
will be either the contents of the Sync Code Register
or an all "1"s character. The underflow will be stored
in the Status Register until cleared and will appear on
the Underflow output as a pulse approximately a Tx
Clk high period wide.
Status Register

Data Carrier Detect (DCD), S Bit 2 - A positive transition on the DCD input is stored in the SSDA until
cleared by reading both Status and Rx Data FIFO.
A "1" written into Rx Rs also clears the stored DCD
status. The DCD status bit, when set, indicates that
the DCD input has gone high. The reading of both
The Status Register is an 8 -bit read -only register Status and Receive Data FIFO allows Bit 2 of subsewhich provides the real-time status of the SSDA and quent Status reads to indicate the state of the DCD
the associated serial data channel. Reading the Status input until the next positive transition.
Register is a non-destructive process. The method of Clear-to-Send (CTS), S Bit 3- A positive transition
clearing status bits depends upon the function each bit on the CTS input is stored in the SSDA until cleared
represents and is discussed for each bit in the register. by writing a "1" into the Clear CTS control bit or the
Receiver Data Available (RDA), S Bit 0 - The Re- Tx Rs bit. The CTS status bit, when set, indicates
ceiver Data Available status bit indicates when receiver that the CTS input has gone high. The Clear CTS comdata can be read from the Rx Data FIFO. The receiver mand (a "1" into C3 Bit 2) allows Bit 3 of subsequent
data being present in the last register (#3) of the Status reads to indicate the state of the CTS input
FIFO causes RDA to be high for the 1- byte transfer until the next positive transition.
mode. The RDA bit being high indicates that the last
two registers (#2 and #3) are full when in the 2-byte
transfer mode. The second character can be read without a second status read (to determine that the character is available). An E pulse must occur between
reads of the Rx Data FIFO to allow the FIFO to shift.
Status must be read on a word- by-word basis if receiver data error checking is important. The RDA status
bit is reset automatically when data is not available.

Transmitter Underflow (TUF), S Bit 4 - When data is
not available for the transmitter, an underflow occurs
and is so indicated in the Status Register (in the Tx
Sync on underflow mode). The underflow status bit
is cleared by writing a "1" into the Clear Underflow
(CTUF) control bit or the Tx Rs bit. TUF indicates
that a sync character will be transmitted as the next
character. A TUF is indicated on the output only
when the contents of the Sync Code Register is to be
Transmitter Data Register Available (TDRA), S Bit 1- transferred (transmit sync code on underflow = "1").
The TDRA status bit indicates that data can be loaded Receiver Overrun (Rx Ovm), S Bit 5 - Overrun indiinto the Tx Data FIFO Register. The first register cates data has been received when the Rx Data FIFO
(#1) of the Tx- Data FIF"O being empty will be in- is full, resulting in data loss. The Rx Ovm status bit
dicated by a high level in the TDRA status bit in the is set when Overrun occurs. The Rx Ovm status bit
1- byte transfer mode. The first two registers (#1 and is cleared by reading Status followed by reading the
#2) must be empty for TDRA to be high_ when in the Rx Data FIFO or by setting the Rx Rs control bit.

3.122

S6852.
Receiver Parity Error (PE), S Bit 6 - The parity error
status bit indicates that parity for the character in the
last register of the Rx Data FIFO did not agree with
selected parity. The parity error is cleared when the
character to which it pertains is read from the Rx Data
FIFO or when Rx Rs occurs. The DCD input does
not clear the Parity Error or Rx Data FIFO status bits.

Interrupt Request (IRQ), S Bit 7 - The Interrupt Request status bit indicates when the IRQ output is in
the active state (IRQ output = "0"). The IRQ status
bit is subject to the same interrupt enables (RIE, TIE,
and EIE) as the IRQ output. The IRQ status bit simplifies status inquiries for polling systems by providing
single bit indication of service requests.

Physical Dimensions

24-PIN PLASTIC

24-PIN CERAMIC
PIN 1 IDENTIFIER

PIN 1 IDENTIFIER--,

---'-j

lib

0.100

----·--·-r···

1.310M AX

MARKINGS
ON LID
SURFACE
ONLY

i_
T

--I

II
0.090 MIN 0.020 MIN

0.040

+=11 -- - L __

12"--------" 13

._1

0.020
0.016

H-0200MAXf-.-g:~~~---I
I

0.090 MI N

L--I-I
0 200 MAX
I

-~I- 0.020 MIN

g~~g'-1

BEND

i---

L-. J
0.580

O~5

1- g~~g-I

/R\

!,r==JI

15° MAX -....;'

'-../

0.065

_~.i. 12 .

-ii-

1.270 MAX

Jf ~'jO i

0.065
0.020
0.015

i
II

15° MAX,J I

~1--0.012

I-

0.012

--I~OOOB

0.008

NOTE:

NOTES:

1. LEADS TRUE POSITIONED WITHIN

1. LEADS, TRUE POSITIONED
WITHIN 0.25mm (O.OlD) DIA.
AT SEATING PLANE AT
MAXIMUM MATERIAL CON·
DITION. (DIM. "D").

0.25mm (0.010) DIA. (AT SEATING
PLANE) AT MAXIMUM MATERIAL
CONDITION.

3.123

2. DIM. "L"TO CENTER OF
LEADS WHEN FO RMED
PARALLEL.

ADVANCED PRODUCT DESCRIPTION

S6854/S68A54
ADVANCED DATA
LINK CONTROLLER
o
o
o
o

Features

o
o

S6800 Compatible
Protocol Features
o Automatic Flag Detection and
Synchroniza tion
o Zero Insertion and Deletion
o Extendable Address, Control and Logical
Control Fields (Optional)
o Variable Word Length Info Field - 5, 6,7,
or 8-bits
o Automatic Frame Check Sequence Generation and Check
o Abort Detection and Transmission
o Idle Detection and Transmission
Loop Mode Operation
Loop Back Self-Test Mode
NRZ /NRZI Modes

Quad Data Buffers for Each Rx and Tx
Prioritized Status Register (Optional)
MODEM/DMA/Loop Interface
MIL-STD-883, Class Band C Devices Available

General Description

The S6854 ADLC performs the complex MPU/data
communication li'1k function for the "Advanced Data
Communication Control Procedure" (ADCCP). High
Level Data Link Control (HDLC) and Synchronous
Data Link Control (SDLC) standards. The ADLC provides key interface requirements with improved software efficiency. The ADLC is designed to provide the
data communications interface for both primary and
secondary stations in stand-alone, polling, and loop
configurations.

Block Diagram

Pin Configuration

"~ll rr:~
I

I-.-----E_------«
~

•
....-_ _ _...l-......!...,

(

iiCii

_ill

27....-0c0

LTIOI'iiN-TiNI

RxC

CONTROLliiTR

RECEIVER
TOSR
ROSR

S6854
22 -DO

FCS CHECK
DATA

BUS
00-07

RESET _ _

cs--

20-02

RS O- - 1 0

19~03

RS 1 - - 1 1

18-04

RIW--12

17-05
16-06
15-07

r-----:==~---~--t===·==~~L:OO:P:ON~-L:IN:E:CO:NT~~L~R

L-__~-~-~~Jr----~~~
Vss PIN 1

~-----«

RESET

Vee PIN 14

3.124

S6854/S68A54

Absolute Maximum Ratings*

Supply Voltage ........................................................... -0.3V to +7.0V
Input Voltage ............................................................ -0.3V to +7.0V
Operating Temperature Range .................................................. O°C to +70°C
Industrial Temperature Range ................................................ -40°C to +85°C
Military Temperature Range ................................................ -55°C to +125°C
Storage Temperature Range ................................................ - 55° C to +150° C
Thermal Resistance ............................................................. +70°C/W
*This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit.

Electrical Characteristics (Vee = 5.0V ± 5%, Vss = 0, TA = 0° C to 70° C unless otherwise noted.)

Symbol

Min.

Parameter

Vrn

Input High Voltage

VIL

Input Low Voltage

lIN

Input Leakage Current
All Inputs Except DO - D7

ITSI

Three-State (Off State)
Input Current
DO-D7

VOH

Output High Voltage
DO-D7

VOL

Output Low Voltage
Output Leakage Current
(Off State)

Power Dissipation

CIN

Capacitance

Max.

Unit

Conditions

Vdc

Vss +2.0
Vss +0.8

Vdc

1.0

2.5

pAdc

VIN =0 to 5.25Vdc

2.0

pAdc

VIN =004 to 204 Vdc
Vee = 5.25Vdc

Vdc

All Others

ILOH

Typ.

Vss+204

ILOAD =- 205pAdc

Vss+204

ILOAD =-100pAdc

1.0

Vss+Oo4

Vdc

ILOAD =1.6mAdc

pAdc

VOH=204Vdc

850

IRQ

DO-D7
All Other Inputs

12.5
7.5

IRQ
All Others

5.0
10

COUT

3.125

VIN = 0, TA =25°C,
f = 1.0MHz

S6854/S68A54

S6854
Symbol

Parameter

Min.

PWCL
PWCH

Minimum Clock Pulse Width, Low

700

Minimum Clock Pulse Width, High

700

Clock Frequency

tRDSU

Receive Data Setup Time

250

tRDH

Receive Data Hold Time
Request-to-Send Delay Time

120

tRTS
tTDD
tFD
tIYrR
tI1)C
tRDSR
tTDSR
tlR
tR,ES
t r , tf

S68A54

Max.

Min.

Max.

450

ns
1.0

MHz

200

100

ns
ns

680

460

Clock-to-Data Delay for Transmitter

460
680

320
460

Flag Detect Delay Time
DTR Delay Time

680

460

Loop On-Line Control Delay Time
RDSR Delay Time
TDSR Delay Time

680
540
540

460
400
400

ns
ns
ns
ns

Interrupt Request Release Time
Reset Minimum Pulse Width
Input Rise and Fall Times
Except Enable

1.2
1.0

0.9
0.65

1.0*

Conditions

450
0.66

Unit

1.0*

J.1s
J.1s
J.1s

0.8V to 2.0V

*1.0J.1s or 10% of the pulse width, whichever is smaller.

Bus Timing Characteristics (Vcc

5.0V ± 5%, Vss = 0, TA = O°C to +70°C unless otherwise noted.)

Read
Symbol

S6854
Min.
Max.

Parameter

tCYC
PWEH

Enable Cycle Time

PWEL

Enable Pulse Width, Low
Setup Time, Address and RjW Valid to Enable
positive transition

tAS

Enable Pulse Width, High

S68A54
Min.
Max.

1.0

0.666

0.45
0.43
160

0.28
0.28
140

tDDR
tH

Data Delay Time
Data Hold Time

320

tAH
tEr, tEf

Address Hold Time
Rise and Fall Time for Enable input

J.1s
J.1s
J.1s
ns
220

ns
ns

10
25

Unit

Write
tcYCE
PWEH

Enable Cycle Time

1.0

0.666

J.1s

Enable Pulse Width, High

0.45

0.28

PWEL

Enable Pulse Width, Low
Setup Time, Address and RjW Valid to Enable
positive transition

0.43
160

0.28
140

J.lS
J.1s
ns

tDSW
tH

Data Setup Time

195

Data Hold Time

tAH
tEr, tEf

Address Hold Time
Rise and Fall Time for Enable input

10
10

ns
ns
ns

tAS

3.126

S6854/S68A54

Figure 1. Bus Timing Test Loads

LOAOA
(00·07 ill, T.O, ROSR, roSR
FLAG DET, LOOP ON·LlNE CONTROLliffii)

LOAD B

(ifITl ONLY)

5.0V

3k
TEST POINT ( ) - -_ _ _ _...........--1

MMC6l50
OR EOUIV.

TEST POINT

MM07000
OR EOUIV.

R = l1.7kE FOR 00·07
= 24kE FOR OTHERS

C = l30pF FOR 00·07
= 30pF FOR OTHERS

Figure 2. Receiver Data Setup/Hold, Flag Detect and Loop On-Line Control Delay Timing

PW CH
2.0V

RxC

0,SV . !
2 OV

PW Cl I
RxO

l-...-tRDSU~

"II

LOOPON·LlNE

tRDH

IFD

O~V

2.4V

0.4V
2.4V

------------------+~----~ ~~-----------

CONTROL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+~-----J~-------------_l
_10.4V
lDC

3.127

S6854/S68A54

Figure 3. Transmit Data Output Delay and Request to Send Delay Timing

I-PWCH-I
2.0V

TxC

O.SV

~~------------~
-PWCl----;-k'..
2::::.4\ZV::~..

TxO

-t

TDD _

ATS

:!______________

__________________-+______

-J

JO.4V
I

}12::;;.4;:.v_ _ _ _ _ _ _ _ _ _ _ _ __

__________________-+__________

Figure 4. TDSR/RDSR Delays, IRQ Release Delay, RTS and DTR Delay Timing

2.0Vr_ _ _ _ _ _ _ _ _
E

iiTii

---.J

--__-+________________

~-------------J

2.4V

Figure 5. Bus Read/Write Timing Characteristics

READ

WRITE

CS, ASO
ANi, AS1

DATA BUS

3.128

S6854/S68A54

Frame Format

The ADLC transmits and receives data (information
or control) in a format called a frame. All frames start
with an opening flag (F) and end with a closing flag

(F). Between the opening flag and closing flag, a
frame contains an address field, control field, information field, and frame check sequence field.

Figure 6. Data Format of a Frame

I~·~-----------------------------------------AFRAME------------------------------··I
01111110

8·BITS
PER BYTE

(OPENING)
FLAG

ADDRESS*
FIELD

CONTROL*
FIELD

*EXTENOABLE (OPTIONAL)

8·BITS
PER BYTE

I
I
I
I

16-BIT

01111110

FRAME CHECK
SEQUENCE
FIE LO

(CLOSING)

VARIABLE
LENGTH
(5 - 8)

LOGICAL CONTROL
SUB·FIELD (OPTIONAL)

FLAG

1-4-INFO RMATION FIELO-'I

Flag (F) - The flag is the unique binary pattern
(01111110). It provides the frame boundary and a
reference for the position of each field of the frame.
The ADLC transmitter generates a flag pattern internally and the opening flag and closing flags are appended to a frame automatically. Two successive frames
can share one flag for a closing flag of the first frame
and for the opening flag of the next frame, if the
"FF IF" control bit in the control register is reset.
The receiver searches for a flag on a bit by bit basis
and recognizes a flag at any time. The receiver establishes the frame synchronization with every flag. The
flags mark the frame boundary and reference for each
field but they are not transferred to the Rx FIFO.
The detection of a flag is indicated by the Flag Detect
output and by a status bit in the status register.
Order of Bit Transmission - Address, control and
information field bytes are transferred between the
MPU and the ADLC in parallel by means of the data
bus. The bit on DO (data bus bit 0, pin 22) is serially
transmitted first, and the first serially received bit is
transferred to the MPU on DO. The FCS field is
transmitted and receives MSB first.
Address (A) Field - The 8 bits following the opening
flag are the address (A) field. The A-field can be
extendable if the Auto-Address Extend Mode is
selected in control register 'It- 3. In the Address Extend
Mode, the first bit (bit 0) in every address octet
becomes the extend control bit. When the bit is
"0", the ADLC assumes another address octet will
follow, and when the bit is "1", the address extension is terminated. A "null" address (all "a's") does
not extend. In the receiver, the Address Present status

bit distinguishes the address field from other fields.
When an address byte is available to be read in the
receive FIFO register, the Address Present status bit
is set and causes an interrupt (if enabled). The Address
Present bit is set for every address octet when the
Address Extend Mode is used.
Control (C) Field - The 8 bits following the address
field is the control (link control) field. When the
Extended Control Field bit in control register #3 is
selected, the C-field is extended to 16 bits.
Information (I) Field - The I-field follows the C-field
and precedl~s the FCS field. The I-field contains
"data" to be transferred but is not always necessarily
contained in every frame. The word length of the 1field can be selected from 5 to 8 bits per byte by
control bits in contrul register #4. The I-field will
continue until it is terminated by the FCS and closing
flag. The receiver has the capability to handle a
"partial" last byte. The last information byte can be
any word length between 1 and 8 bits. If the last
byte in the I-field is less than the selected word length,
the receiver will right justify the received bits, fill the
remaining bits of the receiver shift register with zeros,
and transfer a full byte to the Rx FIFO. Regardless
of selected byte length, the ADLC will transfer 8
bits of data to the data bus. Unused bits for word
lengths of 5, 6, and 7 will be zeroed.
Logical Control (LC) Field - When the Logical
control Field Select bit in control register #3 is
selected, the ADLC separates the I-field into two subfields. The first sub-field is the Logical Control field
and the following sub-field is the "data" portion of
the I-field. The logical control field is 8 bits and

3.129

S6854/S68A54

follows the C-field, which is extendable by octets, if
it is selected. The last bit (bit 7) is the extend control
bit, and if it is a "1", the LC-field is extended one
octet.
Note: Hereafter the word "Information Field" or
"I-field" is used as the data portion of the information field, and excludes the logical control
field. This is done in order to keep the consistency of the meaning of "Information Field"
as specified in SDLC, HDLC, and ADCCP standards.
Frame Check Sequence (FCS) Field - The 16 bits
preceding the closing flag is the FCS field. The FCS
is the "cyclic redundancy check character (CRCC)".
The poly-nomlal x l6 + xl2 + X S + 1 is used both for
the transmitter and receiver. Both the transmitter
and receiver poly-nominal registers are initialized to
all "l"s prior to calculation of the FCS. The transmitter calculates the FCS on all bits of the address,
control, logical control (if selected), and information
fields, and transmits the complement of the resulting remainder as FCS. The receiver performs the
similar computation on all bits of the address, control,
logical control (if selected), information, and received
FCS fields and compares the result to FOB8 (Hexadecimal). When the result matches FOB8, the Frame
Valid status bit is set in the status register. If the
result does not match, the Error status bit is set. The
FCS generation, transmission, and checking are performed automatically by the ADLC transmitter and
receiver. The FCS field is not transferred to the Rx
FIFO.

Zero Insertion and Zero Deletion - The Zero insertion and deletion, which allows the content of the
frame to be transparent, are performed by the ADLC
automatically. A binary 0 is inserted by the transmitter after any succession of 51's within a frame
(A, C, LC, I, and FCS field). The receiver deletes a
binary 0 that follows successive 5 continuous l's
within a frame.
Abort - The function of prematurely terminating a
data link is called "abort". The transmitter aborts a
frame by sending at least 8 consecutive l's immediately after the Tx Abort control bit in control register
#4 is set to a "1". (Tx FIFO is also cleared by the
Tx Abort control bit at the same time.) The abort
can be extended up to (at least) 16 consecutive l's,
if the Abort Extend control bit in the control register
#4 is set when an abort is sent. This feature is useful
to force mark idle transmission. Reception of 7 or
more consecutive l's is interpreted as an abort by the
receiver. The receiver responds to a received abort as
follows:
1) An abort in an "out of frame" condition - An
abort during the idle or time fill has no meaning.
The abort reception is indicated in the status
register as long as the abort condition continu~s;
but neither an interrupt nor a stored condition
occurs. The abort indication is suppressed after
15 or more consecutive l's are received (Received Idle status is set).
2) An abort "in frame" after less than 26 bits are
received after an opening flag - Under this
condition, any field of the aborted frame has
not transferred to the MPU yet. The ADLC
clears the aborted frame data in the FIFO and
clears flag synchronization. Neither an interrupt
nor a stored status occurs. The status indication is the same as (1) above.
3) An abort "in frame" after 26 bits or more are
received after an opening flag - Under this
condition, some fields of the aborted frame
might have been transferred onto the data bus.
The abort status is stored in the receiver status
register and the data of the aborted frame in
the ADLC is cleared. The synchronization is
also cleared.

Invalid Frame - Any valid frames should have at
least the A-field, C-field and FCS field 'between the
opening flag and the closing flag. When invalid frames
are received, the ADLC handles them as follows:
1) A short frame which has less than 25 bits between flags - The ADLC ignores the short
frame and its reception is not reported to the
MPU.
2) A frame less than 32 bits between the flags, or
a frame 32 bits or more with an extended Afield or C-field that is not completed. - This
frame is transferred into the R4 FIFO. The
FeS/IF Error status bit indicates the reception
of the invalid frame at the end of the frame.
3) Aborted Frame- The frame which is aborted
by receiving an abort or DCD failure is also an
invalid frame. Refer to "Abort" and "DCD
status bit."

Idle and Time Fill - When the transmitter is in an
"out of frame" condition (the transmitter is not
transmitting a frame), it is in an idle state. Either a
series of contiguous flags (time fill) or a mark idle

3.130

S6854/S68A54

(consecutive 1 's on a bit by bit basis) is selected for
the transmission in an idle state by the Flag/Mark Idle
control bit. When the receiver receives 15 or more
consecutive 1 's, the Receive Idle status bit is set and
causes an interrupt. The flags and mark idle are not
transferred to the Rx FIFO.
Operation

Initialization - During a power-on sequence, the
ADLC is reset via the RESET input and internally
latched in a reset condition to prevent erroneous output transitions. The four control registers must be
programmed prior to the release of the reset condition. The release of the reset condition is performed
via software by writing a "0" into the Rx RS control
bit (receiver) and/or Tx RS control bit (transmitter).
The release of the reset condition must be done after
the RESET input has gone high.
At any time during operation, writing a "1" into the
Rx RS control bit or TX RS control causes the reset
condition of the receiver or the transmitter.
Transmitter Operation - The Tx FIFO register cannot
be pre-loaded when the transmitter is in a reset state.
Mter the reset release, the Flag/Mark Idle control bit
selects either the mark idle state (inactive idle) or the
Flag "time fill' (active idle) state.This active or inactive mark idle state will continue until data is
loaded into the Tx FIFO.
The availability of the Tx FIFO is indicated by the
TDRA status bit under the control of the 2-Byte/
1-Byte control bit. TDRA status is inhibited by the
Tx RS bit or CTS input being high. When the 1-Byte
mode is selected, one byte of the FIFO is available
for data transfer when TD RA goes high. When the
2-Byte mode is selected, two successive bytes can be
transferred when TDRA goes high.
The first byte (Address field) should be written into
the Tx FIFO at the "Frame Continue" address. Then
the transmission of a frame automatically starts. If
the transmitter is in a mark idle state, the transfer of
an address causes an opening flag within two or three
transmitter clock cycles. If the transmitter has been
in a time fill state, the current time fill flag being
transmitted is assumed as an opening flag and the
address field will follow it.
A frame continues as long as data is written into the
Tx FIFO at the "Frame Continue" address. The
ADLC internally keeps track of the field sequence in
the frame. The frame' format is described in the
"FRAME FORMAT" section.

The frame is terminated by one of two methods.
The most efficient way to terminate the frames from
a software standpoint is to write the last data character into the Transmit FIFO "Frame Terminate"
address (RS1, RSO = 11) rather than the Transmit
FIFO "Frame Continue" address (RS1, RSO = 10).
An alternate method is to follow the last write of
data in the Tx FIFO "Frame Continue" address with
the setting of the Transmit Last Data control bit.
Either method causes the last character to be transmitted and the FCS field to automatically be appended along with a closing flag. Data for a new frame
can be loaded into the Tx FIFO immediately after
the old frame data, if TDRA is high. The closing Flag
can serve as the opening Flag of the next frame or
separate opening and closing Flags may be transmitted. If a new frame is not ready to be transmitted,
the ADLC will automatically transmit the Active
(Flag) or Inactive (Mark) Idle condition.
If the Tx FIFO becomes empty at any time during
frame transmission (the FIFO has no data to transfer
into transmitter shift register during transmission of
the last half of the next to last bit of a word), an
underrun will occur and the transmitter automatically terminates the frame by transmitting an abort.
The underrun state is indicated by the Tx Underrun
status bit.

Any time the Tx ABORT Control bit is set, the
transmitter immediately aborts the frame (transmits at least 8 consecutive 1 's) and clears the Tx
FIFO. If the abort Extend Control bit is set at the
time, an idle (at least 16 consecutive 1 's) is transmitted. An abort or idle in an "out of frame" condition can be useful to gain 8 or 16 bits of delay. (For
an example, see "Programming Considerations.")
The CTS (Clear-To-Send) input and RTS (RequestTo-Send) output are provided for a MODEM or other
hardware interface.
The TDRA/FC status bit (when selected to be Frame
Complete Status) can cause an interrupt upon frame
completion (i.e., a flag or abort completion).
Details regarding the inputs and outputs, status bits,
control bits, and FIFO operation are described in
their respective sections.
Receiver Operation - Data and a pre-synchronized
clock are provided to the ADLC receiver section by
means of the Receive Data (RxD) and Receive Clock
(RxC) inputs. The data is a continuous stream of
binary bits with the characteristic that a maximum of
five "1 's" can occur in succession unless Abort, Flag,

3.131

S6854/S68A54

Figure 7 A. AD LC Transmitter State Diagram
C1b refers to control register bit
l
DATA BEING TRANSMITTED:
F" flag

A ::: address
C " !linkl control
lC ::: logical control (optional)
I::: information
FCS :: frame check sequence
ABT " abort

FIFO EMPTY

Figure 7B. ADLC Receiver State Diagram

3.132

S6854/S68A54

Operation (Continued)

or Idling condition occurs. The receiver continuously
(on a bit-by-bit basis) searches for Flags and Aborts.
When a flag is detected, the receiver establishes frame
synchronization to the flag timing. If a series of flags
is received, the receiver resynchronizes to each flag.
If the frame is terminated before the internal buffer

time expires (the frame data is less than 25 bits after
an opening flag), the frame is simply ignored. Noise
on the data input (RxD) during time fill can cause
this kind of invalid frame.
Once synchronization has been achieved and the
internal buffer time (24 bit times) expires data will
automatically transfer to the Rx Data FIFO. The Rx
Data FIFO is clocked by E to cause received data to
move through the FIFO to the last empty register
location. The Receiver Data Available status bit
(RDA) indicates when data is present in the last
register (Reg. #3) for the 1 Byte Transfer Mode. The
2 Byte Transfer Mode causes the RDA status bit to
indicate data is available when the last two FIFO
register locations (Reg. #2 and #3) are full. If the
data character present in the FIFO is an address octet
the status register will exhibit an Address Present
status condition. Data being available in the Rx Data
FIFO causes an interrupt to be initiated (assuming
the receiver interrupt is enabled, RIE = "1 "). The
MPU will read the ADLC Status Register as a result of
the interrupt or in its turn in a polling sequence. RDA
or Address Pres en t will indicate that receiver data is
available and the MPU should subsequently read the
Rx Data FIFO register. The interrupt and status bit
will then be reset automatically. If more than one
character had been received and was resident in the
Rx Data FIFO, subsequent E clocks will cause the
FIFO to update and the RDA status bit and interrupt
will again be SET. In the two byte transfer mode
both data bytes may be read on consecutive E cycles.
Address Present provides for 1 byte transfers only.
The sequence of each field in the received frame is
automatically handled by the ADLC. The frame format is described in the "FRAME FORMAT" section.
When a closing flag is received, the frame is terminated.
The 16 bits preceding the closing flag are regarded as
the FCS and are not transferred to the MPU. Whatever data is present in the most significant byte portion of the receiver buffer register is right justified
and transferred to the Rx FIFO. The frame boundary
pointer, which is explained in the "Rx FIFO REGISTER" section, is set simultaneously in the Rx FIFO.
The frame boundary pointer sets the Frame Valid

status bit (when the frame was completed with no
error) or the FCSjIF Error Status bit (when the frame
was completed with error) when the last byte of the
frame appears at the last location of the Rx FIFO.
As long as the Frame Valid or FCSjIF Error status bit
is set, the data transfer from the second location of
the Rx FIFO to the last location of the Rx FIFO is
inhibited.
Any time the Frame Discontinue control bit is set,
the ADLC discards the current frame data in the
ADLC without dropping flag synchronization. This
feature can be used to ignore a frame which is addressed
to another station.
The reception of an abort or idle is explained in the
"FRAME FORMAT" section. The details regarding
the inputs, outputs, status bits, control bits, and Rx
FIFO operation are described in their respective
sections.
Loop Mode Operation - The ADLC in the loop mode
not only performs the transmission and receiving of
data frames in the manner previously described but
also has additional features for gaining and relinquishing loop control. In Figure 8a, a configuration is
shown which depicts loop mode operation. The
system configuration shows a primary station and
several secondary stations. The loop is always under
control of the primary station. When the primary
wants to receive data, it transmits a Poll sequence and
allows frame transmission to secondary stations on
the loop. Each secondary is in series and adds one bit
of delay to the loop. Secondary A in the figure
receives data from the primary via its Rx Data Input,
delays the data 1 bit, and transmits it to secondary B
via its Tx Data Output. Secondaries B, C, and D operate in a similar manner. Therefore, data passes through
each secondary and is received back by the primary
con troller.
Certain protocol rules must be followed in the manner
by which the secondary station places itself on-loop
(connects its transmitter output to the loop), goes
active on the loop (starts transmitting its own stations'
data on the loop), and goes off the loop (disconnects
its transmitter output). Otherwise loop data to other
stations down loop would be interfered. The data
stream always flows the same way and the order in
which secondary terminals are serviced is determined
by the hardware configuration. The primary controller
times the delay through the loop. Should it exceed
n + 1 bit times, where n is the number of secondary
terminals on the loop, it will indicate a loop failure.
Control is transferred to a secondary by transmitting

3.133

S6854/S68A54

Figure SA. Typical Loop Configuration
PRIMARY
CONTROllER
(NON·LOOP)

"POLL FRAME" + "SECONOARY
STATION FRAMES" + "11111111 ... "

SECONOARY STATIONS (A, B, C, D)
OPERATE IN LOOP MOOE

Figure S8. Example of External Loop Logic

r------------------,

ADLC

I
RxD

Up·LOOP OATA

I
DOWN LOOP OATA

TxD \ - - - - - , - - + - - - - - - - - - . . 1

I
I
I

I
I

IL __________________ I
~

a "Go Ahead" signal following the closing Flag of a
polling frame (request for a response from the secondary) from the primary station. The "Go Ahead"
from the primary is a "0" and 7 "l's" followed by
mark idling. The primary can abort its response
request by interrupting its idle with flags. The secondary should immediately stop transmission and return
control back to the primary. When the secondary
completes its frame, a closing flag is transmitted
followed by all "1 "s. The primary detects the final
01111111 . . . ("Go Ahead" to the primary) and
control is given back to the primary. Note that, if a
down-loop secondary (e.g., station D) needs to insert

information following an up-loop station (e.g., station
A), the go ahead to station D is the last "0" of the
closing flag from station A followed by "1 's".

The ADLG in the primary station should operate in a
non-loop, full duplex mode. The ADLC in the secondaries should operate in a loop mode, monitoring uploop data on its receiver data input. The ADLC can
recognize the necessary sequences in the data stream
to automatically go on/off the loop and to insert its
own station data. The procedure is the following and
is summarized in Table 1.

3.134

S6854/S68A54

Table 1. Summary of Loop Mode Operation

STATE

RX SECTION

TX SECTION

lOOP
STATUS BIT

OFF-lOOP

Rx section receives data from loop and searches for
7 ''1's'' (when On-loop Control bit set) to go ONlOOP.

Inactive
1) NRZ MODE
Tx data output is maintained "high" (mark).
2) NRZI MODE
Tx data output reflects the Rx data input state
delayed byone bit time. (Not normallyconnected
to loop.) The NRZI data is internally decoded
to provide error-free transitions to On-loop
mode.

"0"

ON-lOOP

1) When Go-Active on poll bit is set, Rx section
searches for 01111111 pattern (the EOP or 'Go
Ahead') to become the active terminal on the
loop.
2) When On-loop control bit is reset, Rx section
searches of 8 "1's" to go 0 FF-LOOP.

Inactive
1) NRZ MODE
Tx data output reflects Rx data input state
delayed one bit time.
2) NRZI MODE
Tx data output reflects Rx data input state
delayed 2 bit times.

"1"

ACTIVE

Rx section searches for flag {an interrupt from the
loop controller} at Rx data input. Received flag
causes FD output to go low. IRQ is generated if
mE and FDSE control bits are set.

Tx data originates within AD LC until Go Active on
Poll bit is reset and a flag or Abort is completed.
Then returns to ON-LOOP state.

"0"

(1) Go On-loop - when the ADLC powers up, the
terminal station wi~ be off line. The first task is to
become an active terminal on the loop. The ADLC
must be connected to a Loop Link via an external
switch as shown in Figure 8b. After hardware reset,
the ADLC LOC/DTR Output will be in the high state
and the up-loop receive data repeated through gate A
to the down Loop stations. Any Up-Loop transmission will be received by the ADLC. The Loop/
Non-Loop Mode Control bit (bit 5 in Control Register
3) must be set to place the ADLC in the Loop Mode.
The ADLC now monitors its Rx Data input for a
string of seven consecutive "1 's" which will allow a
station to go on line. The Loop operation may be
monitored by use of the Loop Status bit in Status
Register 1. After power up and reset, this bit is a
zero. When seven consecutive ones are received by the
ADLC the LOC /DTR output will go to a low level,
disabling gate A (refer to Figure 8b), enabling gate B
and connecting the ADLC Tx Data output to the
down Loop stations. The up Loop data is now
repeated to the down Loop stations via the ADLC. A
one bit delay is inserted in the data (in NRZI mode,
there will be a 2 bit delay) as it circulates through the
ADLC. The ADLC is now on-line and the Loop
Status bit in Status Register 1 will be at a one.

(2) Go Active after Poll - The receiver section will
monitor the up link data for a general or addressed
poll command and the Tx FIFO should be loaded
with data so that when the go-ahead sequence of a
zero followed by seven ones (01111111 ---) is detected, transmission can be initiated immediately. When
the polling frame is detected, the Go-Active-On-Poll
control bit must be set (bit 6 in Control Register 3).
A minimum of seven bit times are available to set this
control bit after the closing flag of the poll. When the
Go-Ahead is detected by the receiver, the ADLC will
automatically change the seventh one to a zero so
that repeated sequence out gate B in Figure 8b is now
opening flag sequence (01111110). Transmission now
continues from the Tx FIFO with data (address,
control, etc.) as previously described. When the ADLC
has gone active-on-poll, the Loop Status bit in Status
Register 1 will go to a zero. The receiver searches for
a flag, which indicates that the primary station is
interrupting the current operation.
(3) Go Inactive when On-Loop - The Go-Active-On
Poll control bit may be RESET at any time during
transmission. When the frame is complete (the closing Flag or abort is transmitted), the Loop is automatically released and the station reverts back to being

3.135

S6854/S68A54

just a one bit delay in the Loop, repeating up link
data. If the Go-Active-On-Poll control bit is not reset
by software and the final frame is transmitted (Flag/
Mark Idle bit = 0), then the transmitter will mark idle
and will not release the loop to up-loop data. A Tx
Abort command would have to be used in this case in
order to go inactive when on the loop. Also, if the Tx
FIFO was not preloaded with data (address, control,
etc.) prior to changing the "Go Ahead Character" to
a Flag, the ADLC will either transmit flags (active idle
character) until data is loaded (when Flag/Mark Idle
Control bit is high) or will go into an underrun condition and transmit an Abort (when Flag/Mark Idle
control bit is low). When an abort is transmitted, the
Go-Active-on-Poll control bit is reset automatically
and the ADLC reverts to its repeating mode, (TxD =
delayed RxD). When the ADLC transmitter lets go of
the loop, the Loop Status bit will return to a "1",
indicating normal on-loop retransmission of up-loop
data.

Chip Select - An ADLC· read or write operation is
enabled only when the CS input is low and the E
clock input is high. (E· CS).
RSO
RS1
Register Selects - When the Register Select inputs are
enabled by (E • CS), they select internal registers in
conjunction with the Read/Write input and Address
Control bit (control register 1, bit 0). Register addressing is defined in Table 2.
R/W
Read/Write Control Line - The R/W input controls
the direction of data flow on the data bus when it is
enabled by (E . CS). When R/W is high, the I/O
Buffer acts as an output driver and as an input buffer
when low. It also selects the Read Only and Write
Only registers within the ADLC.

4) Go Off-Loop - The ADLC can drop-off the Loop

RESET

(go off-line) similar to the way it went on-line. When
the Loop On-Line control bit is reset the ADLC
receiver section looks for 8 successive "1 's" before
allowing the LOC/DTR output to return high (the
inactive state). Gate A in Figure 8b will be enabled
and Gate B disabled allowing the loop to maintain
continuity without disturbance. The Loop Status
bit will show an off-line condition (logical zero).

Reset Input - The RESET Input provides a means of
resetting the ADLC from a hardware source. In the
"low state," the RESET Input causes the following:
D

Rx Reset and Tx Reset are SET causing both the
Receiver and Transmitter sections to be held in a
reset condition.

Resets the following control bits: Transmit Abort,
RTS, Loop Mode, and Loop On-Line/DTR.

Clears all stored status condition of the status
registers.

Outputs: RTS and LOC/DTR go high. TxD goes
to the mark state ("l's" are transmitted).

Input/Output Functions

All inputs of ADLC are high impedance and TTL
compatible level inputs. All outputs of the ADLC
are compatible with standard TTL. Interrupt Request
(IRQ), however, is an open drain output (no internal
pull-up).
Interface for MPU
DO-D7
Bidirectional Data Bus - These data bus I/O ports
allow the data transfer between ADLC and system
bus. The data bus drivers are three-state devices that
remain in the high impedance (off) state except when
the MPU performs an ADLC read operation.
E
Enable Clock - E activates the address inputs (CS,
RSO and RS1) and R/W input and enables the data
transfer on the data bus. E also move data through
the Tx FIFO and Rx FIFO. E should be a free running clock such as the S6800 MPU system clock.

When RESET returns "high" (the inactive state) the
transmitter and receiver sections will remain in the
reset state until Tx Reset and Rx Reset are cleared via
the data bus under software control. The Control
Register bits affected by RESET cannot be changed
when RESET is "low".
IRQ
Interrupt Request Output - IRQ will be low if an
interrupt situation exists and the appropriate interrupt
enable has been set. The interrupt remains as long as
the cause for the interrupt is present and the enable is
set.

Clock and Data of Transmitter and Receiver
TxC
Transmitter Clock Input - The transmitter shifts data

3.136

S6854/S68A54

on the negative transition of the TxC clock input.
When the Loop Mode or Test Mode is selected, TxC
should be the same frequency and phase as the RxC
clock. The data rate of the transmitter should not
exceed the E frequency.
RxC
Receiver Clock Input - The receiver samples the data
on the positive transition of the TxC clock. RxC
should be synchronized with receive data externally.
TxD
Transmit Data Output - The serial data from the
transmitter is coded in NRZ or NRZI (Zero Complement) data format.
RxD
Receiver Data Input - The serial data to be received
by the ADLC can be coded in NRZ or NRZI (Zero
Complement) data format. The data rate of the
receiver should not exceed the E frequency. If a
partial byte reception is possible at the end of a frame,
the maximum data rate of the receiver is indicated
by the following relationship:
1

fRxC ~---------2tE + 300ns

where tE is the period of E.

Data Carrier Detect Input - The DCD input provides
a real-time inhibit to the receiver section. A high level
on the DCD input resets and inhibits the receiver
register, but data in the Rx FIFO from a previous
frame is not disturbed. The positive transition of
DCD is stored within the ADLC to insure that its
occurrence will be acknowledged by the system. The
stored DCD information and its associated IRQ (if
enabled) are cleared by means of the Clear Rx Status
Control bit or by the Rx Reset bit.
LOC/DTR
Loop On Line Control/Data Terminal Ready output
- The LOC/DTR output serves as a DTR output in
the non-loop mode or as a Loop Control output in
the loop mode. When LOC/DTR output performs the
DTR function, it is turned on and off by means of the
LOC/DTR control bit. When the Loc/DTR control
bit is high the DTR output will be low. In the loop
mode the LOC/DTR output provides the means of
controlling the external loop interface hardware to
go On-line or Off-line. When the LOC/DTR control
bit is SET and the loop has "idled" for 7 bit times
or more (RxD) = 01111111 ... ), the LOC/DTR output will go low (on-line). When the LOC/DTR control
bit is low and the loop has "idled" for 8 bit times or
more, the LOC/DTR output will return high (off-line).
The RESET input being low will cause the LOC/DTR
output to be high.
FD

Peripheral/Modem Control
RTS
Request to Send Output - The Request-to-Send output is controlled by the Request-to-Send control bit
in conjunction with the state of the transmitter section. When the RTS bit goes high, the RTS output
is forced low. When the RTS bit returns low, the
RTS output remains low until the end of the frame.
The positive transition of RTS occurs after the
completion of a Flag, an Abort, or when the RTS
control bit is reset during a mark idling state. When
the RESET input is low, the RTS output goes high.
CTS
Clear to Send Input - The CTS input provides a realtime inhibit to the TDRA status bit an'd its associated
interrupt. The positive transition of CTS is stored
within the ADLC to insure its occurrence will be acknowledged by the system. The stored CTS information and its associated IRQ (if enabled) are cleared
by writing a "1" in the Clear Tx Status bit or in the
Transmitter Reset bit.

Flag Detect Output - An output to indicate the
reception of a flag and initiate an external time-out
counter for the loop mode operation. The FD output
goes low for one bit time beginning at the last bit of
the flag character, as sampled by the receiver clock
(RxC).
DMA Interface
RDSR
Receiver Data Service Request Output - The RDSR
Output is provided primarily for use in DMA Mode
operation and indicates (when high) that the Rx
FIFO requests service (RSDR output reflects the
RDA status bit). If the prioritized Status Mode is
selected, RDSR will be inhibited when any other
receiver status conditions are present. RDSR goes
low when the Rx FIFO is read.
TDSR
Transmitter Data Service Request Output - The
TDSR Output is proivded for DMA mode operation
and indicates (when high) that the Tx FIFO requests

3.137

S6854/S68A54

service (TDSR reflects the TDRA status bit). TDSR
goes low when the Tx FIFO is loaded. TDSR is
inhibited by: The Tx Rs control bit being SET, RESET
being low, or CTS being high. If the prioritized status
mode is used, Tx underrun also inhibits TDSR.

FIFO. When RDA status bit is "1", the Rx FIFO is
ready to be read. The RDA status is controlled by the
2 Byte/1 Byte control bit. When overrun occurs, the
data in the first byte of the Rx FIFO are no longer
valid.

ADLC Registers

Both the Rx Reset bit and Reset input clear the Rx
FIFO. Abort ("In Frame") and a high level on the
DCD input also clears the Rx FIFO, but the last bytes
of the previous frame, which are separated by the
frame boundary pointer, are not disturbed.

Eight registers in the ADLC can be accessed by means
of the MPU data and address buses. The registers are
defined as read only or write only according to the
direction of information flow. The addresses of these
registers are defined in Table 2; The transmitter FIFO
register can be accessed by two different addresses,
the "Frame Terminate" address and the "Frame Continue" address. (The function of these addresses are
discussed in the FIFO section.)
Table 2. Register Addressing

R!W RS1

Write Control Register # 1
Write Contiol Register # 2

Write Control Register # 3

Write Transmit FIFO
(Frame Terminate)
Write Control Register #4
Read Status Register # 1

Read Status Register # 2
Read Receiver FIFO

0
1
1
1

0
0
0
1

RSO

Address
Control Bit
(C1 bO)

1
1

0
1

0
0
1

0
1

Transmitter Data First-In First-Out Register
Tx FIFO
The Tx FIFO consists of three 8-bit registers which
are used for buffer storage of data to be transmitted.
Data is always transferred from a full register to. an
empty adjacent register; the transfer occurs on both
phases of the E input clock. The Tx FIFO can be
addressed by two different register addresses, the
"Frame Continue" address and the "Frame Terminate" address. Each register has pointer bits which
point to the frame boundary. When a data byte is
written at the "Frame Continue" address, the pointer
of the first FIFO register is set. When a data byte is
written at the "Frame Terminate" address, the
pointer of the first FIFO register is reset. RxRs
control bit or Tx Abort control bit resets all pointers.
The pointer will shift through the FIFO. When positive transition is detected at the third location of
FIFO, the transmitter initiates a frame with an open
flag. When the negative transition is detected at the
third location of FIFO, the transmitter closes a
frame, appending the FCS and closing Flag to the last
byte.

Receiver Data First-In First-Out Register
Rx FIFO
The Rx FIFO consists of three 8 -bit registers which
are used for the buffer storage of received data. Data
bytes are always transferred from a full register to an
adjacent empty register; and both phases of the E
input clock are used for the data transfer. Each register has pointer bits which point the frame boundary.
When these pointers appear at the last FIFO location,
they update the Address Present, Frame Valid or FCS/
IF Error status bits.
The RDA status bit indicates the state of the Rx

The Tx last control bit can be used instead of using
the "Frame Terminate" address. When the Tx last
control bit is written by a "1", the logic searches the
last byte location in the FIFO and resets the pointer
in the FIFO register.
The status of Tx FIFO is indicated by the TDRA
status bit. When TDRA is "I", the Tx FIFO is available for loading data. The TDRA status is controlled
by the 2BYTE/1BYTE control bit. The Tx FIFO is
r,eset by both Tx Reset and RESET input. During this
reset condition or when CTS input is high, the TDRA
status bit is suppressed and data loading is inhibited.

3.138

S6854/S68A54

Table 3. ADLC Internal Register Structure
RS1 RSO = 00
Bit#

0
1

2
3
4
5
6
7

RS1 RSO = 01

Status Register # 1
RDA
Status # 2
Read Request
Loop 0 n Line
Flag Detected
(When Enabled)
CTS
Tx Underrun
TO RA/Frame
Complete
I RQ Present

Status Register # 2
Address Present

Receiver Data
Register

Frame Valid

Bit 0
Bit 1

Inactive Idle Received
Abort Received

Bit 2
Bit 3

FCS Error
DCD
Tx Overrun

Bit 4
Bit 5
Bit 6

RDA (Receiver Data Available)

Bit 7

Not Used

Transmitter
Data
Control Register # 1

Control Register # 2
(C1 bO=0)

Address Control (AC)

Prioritized Status
Enable

Receiver Interrupt
2 Byte/l Byte
Enable (R IE)
Transfer
Transmitter Interrupt Flag/Mark Idle
Enable (TIE)
RDSR Mode (DMA)
Frame Complete/
TDRA Select
TDSR Mode (DMA)
Transmit Last Data

Bit #

c
a
....

~
CLR RxStatus

Rx Frame
Discontinue
Rx RESET

Tx RESET

RTS Control

RS1 RSO = 11

RS1 RSO = 10

CLR Tx Status

Control Register # 3
(C1bO = 1)

(Continue Data)

Transmitter
Data
(Last Data) Control Register #4
(C1bO = 0)
C1bO = 1)

Logical Control Field
Select

Bit 0

Extended Control
Field Select
Auto, Address
Extension Mode
01/11 Idle

Bit 1

Bit 2

Bit 3

Flag Detected
Status Enable
Loop/N on-Loop
Mode
Go Active on
Poll/Test
Loop On-Line
ControlDTR

Bit 4

Bit 5

Double Flag/Single
Flag Interframe
Control
Word Length Select
Transmit # 1
Word Length Select
Transmit #2
Word Length Select
Receive # 1
Word Length Select
Receive #2
Transmit Abort

Bit 6

Abort Extend

Bit 7

NRZI/NRZ

3.139

S6854/S68A54

Control Registers
Control Register 1 (CR1)

RS1 RSO RjW AC

TxRS

RxRS

Discontinue

TDSR

RDSR

TIE

RIE

Mode

ceived frame is ignored and the ADLC discards
bO Address Control (AC) - AC provides another RS
the data of the current frame. The DISCONTINUE
(Register Select) signal internally. The AC bit is
bit is automatically reset when the last byte of
used in conjunction with RSO, RS1 and R/W inputs
the frame is discarded. When the ignored frame is
to select particular registers, as shown in Table 2.
aborted by receiving an Abort or DCD failure, the
b1 Receiver Interrupt Enable (RIE) - RIE enables/
disables the interrupt request caused by the reDISCONTINUE bit is also reset.
ceiver section. 1 ... enable, a ... disable.
b6 Receiver Reset (Rx Rs) - When the Rx Rs bit is
"1", the receiver section stays in the reset condib2 Transmitter Interrupt Enable (TIE) - TIE enables/
tion. All receivel sections including the Rx FIFO
disables the interrupt request caused by the transregister and the receiver status bits in both status
mitter.1 ... enable, a ... disable.
registers, are reset. (During reset, the stored DCD
b3 Receiver Data Service Request Mode (RDSR
Mode) - The RDSR Mode bit provides the capastatus is reset but the DCD status bit follows the
DCD in put. Rx Rs is set by forcing a low level
bility of operation with a bus system in the DMA
on the RESET input or by writing a "1" into this
mode when used in conjunction with the prioribit from the data bus. Rx Rs must be reset by
tized status mode. When RDSR MODE is set, and
interru pt request caused by RD A status is inhibited,
writing a "a" from the data bus after RESET has
and the ADLC does not request data transfer via
gone high.
the IRQ output.
, b7 Transmitter Reset (Tx Rs) - when the Tx Rs bit
is "1", the transmitter section stays in the reset
b4 Transmitter Data Service Request Mode (TDSR
condition and transmits marks ("1 's"). All transMODE) - The TDSR MODE bit provides the
mitter sections, including the Tx FIFO and the
capability of operation with a bus system in the
DMA mode when used in conjunction with the
transmitter status bits in both status registers, are
prioritized status mode. When TDSR MODE is
reset (FIFO cannot be loaded). During reset, the
set, and interrupt request caused by TDRA status
stored CTS status is reset but the CTS status bit
is inhibited, and the ADLC does not request a
follows the CTS input. Tx Rs is set by forcing a low
level on the RESET input or by writing a "1" from
data transfer via the IRQ output.
the data bus. It must be reset by writing a "0"
b5 Rx Frame Discontinue (DISCONTINUE) - When
after RESET has gone high.
the DISCONTINUE bit is set, the currently re-

3.140

S6854/S68A54

Control Register 2 (CR2)

RS1 RSO R/W AC

RTS

CLR

FC/TDRA

F/M

2/1

PSE

TxST

RxST

Last

Select

Idle

Byte

bO Prioritized Status Enable (PSE) - When the PSE
bit is SET, the status bits in both status registers
are prioritized as defined in the Status Register
section. When PSE is low, the status bits indicate
current status without bit suppression by other
status bits. The exception to this rule is the CTS
status bit which always suppresses the TDRA
status.
b1 2 Byte/1 Byte Transfer (2/1 Byte) - When the
2/1 Byte bit is RESET the TDRA and RDA status
bits then will indicate the availability of their
respective data FIFO registers for a single byte
data transfer. Similarly, if 2/1 Byte is set, the
TDRA and RDA status bits indicate when two
bytes of data can be moved without a second
status read.
b2 Flag/Mark Idle Select (F /M Idle) - The F /M Idle
bit selects Flag characters or bit by bit Mark Idle
for the time fill or the idle state of the transmitter.
When Mark Idle is selected, Go-Ahead code can
be generated for loop operation in conjunction
with the 01/11 Idle control bit (C3b3). 1 ...
Flag time fill, 0 ... Mark Idle.
b3 Frame Complete/TDRA Select (FC/TDRA Select)
- The FC/TDRA Select bit selects TDRA status
or FC status for the TDRA/FC status bit indication.1 ... FC status, 0 ... TDRA status.
b4 Transmit Last Data (Tx Last) - Tx Last bit provides another method to terminate a frame. When
the Tx Last bit is set just after loading a data byte,

the ADLC assumes the byte is the last byte and
terminates the frame by appending CRCC and a
closing Flag. This control bit is useful for DMA
operation. Tx Last bit automatically returns to
the "0" state.
b5 Clear Receiver Status (CLR Rx ST) - When a
"1" is written into the CLR Rx ST bit, a reset
signal is generated for the receiver status bits in
status register tf 1 and =fI2 (except AP and RDA
bits). The reset signal is enabled only for the bits
which have been present during the last "read
status" operation. The CLR Rx ST bit automatically returns to the "0" state.
b6 Clear Transmitter Status (CLR TxST) - When a
"1" is written into CLR TxST bit, a reset signal is
generated for the transmitter status bits in status
register tf 1 (except TDRA). The reset signal is
enabled for the bits which have been present
during .the last "read status" operation. The CLR
TxST bit automatically returns to the "0" state.
b7 Request to Send Control (RTS) - The RTS bit
when high causes the RTS output to be low (the
active state). When the RTS bit returns low and
data is being transmitted, the RTS output remains
low until the last character of the frame (the
closing Flag or Abort) has been completed. If
the transmitter is idling when the RTS bit return
low, the RTS output will go high (the inactive
state) within two bit times.

3.141

56854/568A54

Control Register 3 (CR3)

RS1 RSO R/W AC

LOC/

GAP/

Loop

FDSE

01/11

AEX

CEX

LCF

DTR

TST

Idle

bO Logical Control Field Select (LCF) - The LCF
select bit causes the first byte(s) of data belonging
to the information field to remain 8 bit characters
until the logical control field is complete. The logical control field (when selected) is an automatically extendable field which is extended when bit
7 of a logical control character is a "1". When the
LCF Select bit is reset the ADLC assumes no logical control field is present for either the transmit
or received data channels. When the logical control
field is terminated, the word length of the information data is then defined by WLS1 and WLS2.
b1 Extended Control Field Select (CEX) - When the
CEX bit is a "1", the control field is extended and
assumed to be 16 bits. When CEX is "0", the
control field is assumed to be 8 bits.
b2 Auto/Address Extend Mode (AEX) - The AEX
bit when "low" allows full 8 bits of the address
octet to be utilized for addressing because address
extension is inhibited. When the A EX bitis "high",
bit 0 of address octet equal to "0" causes the
Address field to be extended by one octet. The
exception to this automatic address field extension is when the first address octet is all "a's"
(the Null Address).
b3 01/11 Idle (01/11 Idle) - The 01/11 Idle Control
bit determines whether the inactive (Mark) idle
condition begins with a "0" or not. If the 01/11
Idle Control is SET, the closing flag (or Abort)
will be followed by a 011111 ... pattern. This is
required of the controller for the "Go Ahead"
character in the Loop Mode. When 01/11 is
RESET, the idling condition will be all"l's".
b4 Flag Detect Status Enable (FDSE) - The FDSE
bit enables the FD status bit in Status Register
Tf 1 to indicate the occurrence of a received Flag
character. The status indication will be accompanied by an interrupt if RIE is SET. Flag detection will cause the Flag Detect output to go low
for one bit time regardless of the state of FDSE.

b5 LOOP/NON-LOOP Mode (LOOP) - When the
LOOP bit is set, loop mode operation is selected
and the GAP/TST control bit, LOC/DTR control
bit and LOC/DTR output are selected to perform
the loop control functions. When LOOP is reset,
the ADLC operates in the point to point data
communications mode.
b6 Go Active On Poll/Test (GAP/TST) - In the
Loop Mode - The GAP /TST bit is used to respond to the poll sequence and to begin transmission. When GAP /TST is set, the receiver searches
for the "Go Ahead" (or End of Poll, EOP). The
receiver "Go Ahead" is converted to an opening
Flag and the ADLC starts its own transmission.
When GAP /TST is reset during the transmission;
the end of the frame (the completion of Flag or
Abort) causes the termination of the "go-activeon-poll" operation and the Rx Data to Tx Data
link is re-established. The ADLC then returns
to the "loop-on-line" state.
In the Non-loop Mode - The GAP/TST bit is
used for self-test purposes. If GAP /TST bit is
set, the TxD output is connected to the RxD
input internally, and provides a "loop-back"
feature. For normal operation, the GAP/TST bit
should be reset.
b7 Loop On-Line Control/DTR Control (LOC/DTR)
- In the Loop Mode - The LOC /DTR bit is used
to go on-line or to go off-line. When LOC /DTR is
set, the ADLC goes to the on-line state after 7
consecutive "l's" occur at the RxD input. When
LOC/DTR is reset, the ADLC goes to the "offline" state after eight consecutive "l's" occur at
the RxD input.

3.142

In the Non-Loop Mode - The LOC/DTR bit
directly controls the Loop On-Line/DTR output
state. 1 ... DTR output goes to low level. a ...
DTR output goes to high level.

S6854/S68A54

Control Register 4 (CR4)

RSl RSO R/W AC

NRZI/NRZ

ABTEX

ABT

Table 4. I·Field Character Length Select
WLS2

I
Rx

0
"FF"/F

WLS2 WLS1 WLS2 WLSl

bO Double Flag/Single Flag Interframe Control ("FF"
/"F") - The "FF" /"F" Control bit determines
whether the transmitter will transmit separate
closing and opening Flags when frames are transmitted successively. When the "FF"/"F" control
bit is low, the closing flag of the first frame will
serve as the opening flag of the second frame.
When the bit is high, independent opening and
closing flags will be transmitted.
b1 Transmitter Word Length Select (Tx WLS1 and
WLS2).
b2 - Tx WLS1 and WLS2 are used to select the word
length of the transmitter information field. The
encoding format is shown in Table 4.

WLS1

I·Field Character Length Length

5 bits

6 bits

7 bits

8 bits

consecutive "1 's", the mark Idle State.
b7 NRZI (Zero Complement)/NRZ Select (NRZI/
NRZ) - NRZI/NRZ bit selects the transmit/
receive data format to be NRZI or NRZ in both
Loop Mode or Non-Loop mode operation. When
the NRZI Mode is selected, a 1 bit delay is added
to the transmitted data (TxD) to allow for NRZI
encoding. 1 ... NRZI, 0 ... NRZ.

NOTE: NRZI coding - The serial data remains in the
same state to send a binary "1" and switches to the
opposite state to send a binary "0".
Status Register
The Status Register 711 is the main status register.
The IRQ bit indicates whether the ADLC requests
service or not. The S2RQ bit indicates whether any
bits in status register 712 request any service. TDRA
and RDA, because they are most often used, are
located in bit positions that are more convenient to
test, RDA reflects the state of the RDA bit in status
register 712.

The Status Register 71 2 provides the detailed status
b3 Receiver Word Length Select (Rx WLS1 and WLS2) information contained in the S2RQ bit and these bits
b4 Rx WLS1 and WLS2 are used to select the word reflect receiver status. The FD bit is the only receiver
length of the receiver information field. The en- status, which is not indicated in status register 712.
coding format is shown in Table 4.
The prioritized status mode provides maximum
b5 Transmit Abort (ABT) - The ABT bit causes
efficiency in searching the status bits and indicates
an Abort (at least 8 bits of "1" in succession) to
only the most important action required to service
be transmitted. The Abort is initiated and the Tx
the ADLC. The priority trees of both status registers
FIFO is cleared when the control bit goes high.
are provided in Figure 9.
Once Abort begins, the Tx Abort control bit
assumes the low state.
Reading the status register is a non-destructive prob6 Abort Extend (ABTEx) - If ABTEX is set, the cess. The method of clearing status depends upon the
abort code initiated by ABT or the underrun bit's function and is discussed for each bit in the
condition is extended up to at least 16 bits of register.

3.143

S6854/S68A54

Status Register 1 (SRI)

RSI RSO R/W AC

IRQ

TDRA/FC

TXU

CTS

LOOP S2RQ

RDA

bO Receiver Data Available (RDA) - The RDA status
bit reflects the state of the RDA status bit in
status Register ff 2. It provides the means of achieving data transfers of received data in the full
Duplex Mode without having to read both status
registers.
bl Status Register ff2 Read Request (S2RQ) - All
the status bits (stored conditions) of status register
ff 2 (except RDA bit) are logically OR-ed and indicated at by the S2RQ status bit. Therefore S2RQ
indicated that status register ff 2 needs to be read.
When S2RQ is "0", it is not necessary to read
status register #2. The bit is cleared when the
appropriate bits in Status Register #2 are cleared
or when Rx Reset is used.
b2 Loop Status (LOOP) - The LOOP status bit is
used to monitor the loop operation of the ADLC.
This bit does not cause an IRQ. When Non-Loop
Mode is selected, LOOP bit stays "0". When Loop
Mode is selected, the LOOP status bit goes to "I"
during "On-Loop" condition. When ADLC is in
an "Off-Loop" condition or "Go-Active-On-Poll"
condition, the LOOP status bit is a "0".
b3 Flag Detected (FD) - the FD Status bit indicates
that a flag has been received if the Flag Detect
Enable control bit has been set. The bit goes high
at the last bit of the Flag Character received
(when the Flag Detect Output goes low) and is
stored until cleared by Clear Rx Status or Rx
Reset:
b4 Clear To Send (CTS) - The CTS input positive
transition is stored in the status register and causes
an IRQ (if Enabled). The stored CTS condition
and its IRQ are cleard by Clear Tx Status control
bit or Tx Reset bit. After the stored status is
reset, the CTS status bit reflects the state of the
CTS input.
b5 Transmitter Underrun (TxU) - When the transmitter runs out of data during a frame transmission, an underrun occurs and the frame is
automatically terminated by transmitting an·
Abort. The underrun condition is indicated by
the TxU status bit. TxU can be cleared by means
of the Clear Tx Status Control bit or by Tx Reset.

b6 Transmitter Data Register Available/Frame Complete (TDRA/FC) - The TDRA Status bit serves
two purposes depending upon the state of the
Frame Complete/TDRA Select control bit. When
this bit serves as a TDRA status bit, it indicates
that data (to be transmitted) can be loaded into
the Tx Data FIFO register. The first register
(Reg. #1) of the Tx Data FIFO being empty
(TDRA = "I") will be indicated by the TDRA
Status bit in the "I-Byte Transfer Mode". The
first two registers (Reg. #1 and #2) must be
empty for TDRI.. to be high and when in the "2Byte Transfer Mode". TDRA is inhibited by Tx
Reset, or CTS being high.
When the Frame Complete Mode of operation is
selected, the TDRA/FC status bit goes high when
a Flag or Abort has been transmitted. The bit
remains high until cleared by resetting the TDRA/
FC control bit or setting the Tx Reset bit.
b7 Interrupt Request (IRQ) - The Interrupt Request
status bit indicates when the IRQ output is in the
active state (IRQ Output == "0"). The IRQ status
bit is subject to the same interrupt enables (RIE,
TIE) as the IRQ output. The IRQ status bit
simplifies status inquiries for polling systems by
providing single bit indication of service requests.
Figure 9. Status Register Priority Tree (PSE = 1)

SR #1
(Tx)

DECREASING
PRIORITY

/CTS
• I

f
\

(Rx)
FD

.).

TXU

S2RU

.).

TDRA/FC

RDA

SR #2 (Rx)
ERR, FV, DCD,
OVRN, Rx ABT
.).

RxlDlE
.).

AP
.).

RDA

•Prioritized even when PSE = 0
NOTE: Status bit above will inhibit one below it.

14.4.

S6854/S68A54

Status Register 2 (SR2)

RS1 RSO R/W AC

RDA

OVRN

DCD

ERR

ABT

Idle

bO Address Present (AP) - The AP status bit provides
the frame boundary and indicates an Address octet
is available in the Rx Data FIFO register. In the
Extended Addressing Mode, the AP bit continues
to indicate addresses until the Address field is
complete. The Address present status bit is cleared
by reading data or by Rx Reset.
b1 Frame Valid (FV) - The FV status bit provides
the frame boundary indication to the MPU and
also indicates that a frame is complete with no
error. The FV status bit is set when the last data
byte of a frame is transferred into the last location of the Tx FIFO (available to be read by MPU).
Once FV status is set, the ADLC stops further
data transfer into the last location of the Rx
FIFO (in order to prevent the mixing of two
frames) until the status bit is cleared by the Clear
Rx Status bit or Rx Reset.
b2 Inactive Idle Received (Rx Idle) - The Rx Idle
status bit indicates that a minimum of 15 consecutive "1 's" have been received. The event is stored
within the status register and can cause an interrupt. The interrupt and stored condition are
cleared by the Clear Rx Status Control bit. The
Status bit is the Logical OR of the receiver idling
detector (which continues to reflect idling until a
"0" is received) and the stored inactive idle condition.
b3 Abort Received (RxABT) - The RxABT status
bit indicates that 7 or more consecutive "l's"
have been received. Abort has no meaning under
out-of-frame conditions; therefore, no interrupt
nor storing of the status will occur unless a Flag
has been detected prior to the Abort. An Abort
Received when "in frame" is stored in the status
register and causes an IRQ. The status bit is the
logical OR of the stored conditions and the Rx
Abort detect logic, which is cleared after 15
consecutive "1 's" have occurred. The stored

Abort condition is cleared by the Clear Rx Status
Control bit or Rx Reset.
b4 Frame Check Sequence/Invalid Frame Error
(ERR) - When a frame is complete with a cyclic
redundancy check (CRC) error or a short frame
error (the frame does not have complete Address
and Control fields), the ERR status bit is set
instead of the Frame Valid status bit. Other functions, frame boundary indication and control
function, are exactly the same as for the Frame
Valid status bit. Refer to the FV status bit.
b5 Data Carrier Detect (DCD) - A positive transition on the DCD input is stored in the status
register and causes an IRQ (if enabled). The
stored DCD condition and its IRQ are cleared by
the Clear Rx Status Control bit or RX Reset.
After stored status is reset, the DCD status bit
follows the state of the input. Both the stored
DCD condition and the DCD input cause the reset
of the receiver section when they are high.
b6 Receiver Overrun (OVRN) - OVRN status indicates that receiver data has been transferred into
the Rx FIFO when it is full, resulting in data loss.
The OVRN status is cleared by the Clear Rx
Status bit or Rx Reset. Continued overrunning
only destroys data in the first FIFO register.
b7 Receiver Data Available (RDA) - The Receiver
Data Available status bit indicates when receiver
data can be read from the Rx Data FIFO. When
the prioritized status mode is used, the RDA bit
indicates that non-Address and non-last data are
available in the Rx FIFO. The receiver data being
present in the last register of the FIFO causes
RDA to be high for the "1 Byte Transfer Mode".
The RDA bit being high indicates that the last
two registers are full when in the "2 Byte Transfer Mode". The RDA status bit is reset automatically when data is not available.

3.145

S6854/S68A54

Programm ing Considerations
1. Status Priority - When the prioritized status mode
is used, it is best to test for the lowest priority

conditions first. The lowest priority conditions
typically occur more frequently and are the most
likely conditions to exist when the processor is
interrupted.
Stored vs Present Status - Certain status bits
(DCD, CTS, Rx Abort, and Rx Idle) indicate a
status which is the logical OR of a stored and a
present condition. It is the stored status that
causes an interrupt and which is cleared by a
Status Clear control bit. After being cleared, the
status register will reflect the present condition
of an input or a receiver input sequence.
Clearing Status Registers - In order to clear an
interrupt with the two Status Clear control bits, a
particular status condition must be read before it
can be cleared. In the prioritized mode, clearing a
higher priority condition might result in another
IRQ caused by a lower priority condition whose
status was suppressed when a status register was
first read. This guarantees that a status condition
is never inadvertently cleared.
Clearing the Rx FIFO - An Rx Reset will effectively clear the contents of all 3 Rx FIFO bytes.
However, the FIFO may contain data from 2
different frames when an overrun, abort, or DCD
failure occurs. When this happens, the data from a
previously closed frame (a frame whose closing
flag has been received) will not be destroyed.
Servicing the Rx FIFO in a 2 Byte Mode - The
procedure for reading the last bytes of data is the
same, regardless of whether the frame contains
an even or an odd number of bytes. Continue to

read 2 bytes until an interrupt occurs that is caused
by an end of frame status (FV or ERR). When
this occurs, indicating the last byte either has
been read or is ready to be read, switch temporarily to the I-byte mode with no prioritized
status (control register 2). Test RDA to indicate
whether a I-byte read should be performed. Then
clear the frame and status.
6. Frame Complete Status and RTS Release - In
many cases, a MODEM will require a delay for
releasing RTS. An 8-bit or 16-bit delay can be
added to the ADLC RTS output by using an
Abort. At the end of a transmission, frame
complete status will indicate the frame completion. After frame complete status goes high, write
"1" into the Abt control bit (and Abt Extend bit
if a 16-bit delay is required). After the Abt control bit is set, write "0" into the RTS control bit.
The transmitter will transmit eight or sixteen 1 's
and the RTS output will then go high (inactive).
7. Note to users not using the S6800 --.:... (a) Care
should be taken when performing a write followed
by a read on successive E pulses at a high frequency rate. Time must be allowed for status
changes to occur. If this is done, the time that E
is low between successive write/read E pulses
should be at least 500ns. (b) The ADLC is a
completely static part. However, the E frequency should be high enough to move data
through the FIFO's and to service the peripheral
requirements. Also, the period between successive
E pulses should be less than the period of RxC or
TxC in order to maintain synchronization between
the data bus and the peripherals.

3.146

568047
VIDEO DISPLAY

GENERATOR

August 1978

Features

General Description

The S68047 Video Display Generator (VDG) is designed to produce composite video suitable for display
on a standard American NTSCcompatible black/white
television or color televison or monitor.

o
o
o

o
o
o
o

32 x 16 (512 total) Alphanumeric Two Color
Display on Black Background with Internal
or External Character Generator ROM.
Two Semigraphics Modes with Display
Densities Ranging from 64 x 32 to 64 x 48 in
8 and 4 Color Sets Respectively, plus Black.
Full Graphics Modes with Display Densities
Ranging from 64 x 64 to 256 x 192 in 2 and
4 Colors.
Full NTSC Compatible Composite Video with
Choice of Interlaced and Non-interlaced
Display Versions.
Provides Microprocessor Compatible Interface
Signals.
Generates Display Refresh RAM Addresses.
NMOS Device, Single 5V Supply, TTL
Compatible Logic Levels.
Color Set Select Pin Can Give 8 Color Displays
in Full Graphics Mode.

There are three major types of display which the
S68047 can generate. These include an alphanumerics
mode of which there are two types, each with normal
or inverted video; a semigraphics mode of which there
are also two types; and full graphics mode of which
there are eight types.

Alphanumeric Modes
The alphanumeric modes, internal and external, enable
the S68047 to display a matrix of 32 x 16 (512 total)
characters. The internal mode utilizes an on-chip 64
ASCII character ROM to display each character in a
5 x 7 dot matrix font. In the external alphanumeric
Pin Configuration

Block Diagram
MPU ADDRESS BUS

Vee

MPU DATA BUS

Vee

Vss

liS

GM4

6M2

GMl

VDG

fS
+5

JK
VC

6-12

AIS

A/G

INV

VSS

A9
A1D

5·50
pF

B-V

All

AI6
GM2
GM1
GM4

R-V

CHROMA BIAS

CSS
iNf/EXT

AZ
VIDEO CLOCK (VCl

6·8

A/S

3.147

568047

General Description (Continued)

mode, an external memory is required, either ROM or
RAM, which is used to display the 32 x 16 character
matrix with each character located within an 8 x 12 dot
matrix of customized font. Switching between internal
and external alphanumerics modes and normal and
inverted video can be accomplished on a character
by character basis.
Semigraphic Modes
The two semigraphic modes, semigraphic 4 (SG4)
and semigraphic 6 (SG6), subdivide each of the 512
(32 x 16) character blocks of 8 x 12 dots each into
2 x 2 and 2 x 3 smaller blocks respectively. In SG4
each block is created from 4 x 6 dots and in SG6 each
block consists of 4 x 4 dots. In addition the SG4 and
SG6 modes can each be displayed in 8 and 4 colors
plus black.
Display switching from alphanumerics to semigraphics
modes or vice versa during a raster display is called
minor mode switching and can take place on a character basis.
Graphics Modes
The eight full graphics modes are divided into two
major groups, 4 color and 2 color. The 4 color graphics
provide 4 display densities ranging from 64 x 64 for
Graphics 0 through to 128 x 192 elements for Graphics
6. The 2 color graphics also provide 4 display densities
ranging from 128 x 64 for Graphics 1 through to 256
x 192 elements for Graphics 7. The latter display has
the highest density of the eight graphics modes. The
amount of display memory increases proportionately
with increasing density of display to a maximum of 6K
bytes for Graphics 7. Switching between either the
alphanumeric modes or semigraphics modes and any
of the full graphics modes is called major mode switching. Major mode switching can only occur at the end
of every twelfth raster line scan.

Applications

Anywhere data can be more usefully presented graphically on a CRT and for a minimum cost, the VDG in
conjunction with a microprocessor based controller

can utilize a standard American NTSC compatible TV
or monitor for such a purpose. Applications are extremely broad ranging from educational systems, video
games, small low cost business/home computers to process control monitors and medical diagnostic displays.
The different modes of operation permit various cost/
display presentation tradeoffs. The alphanumerics
modes allow use of the TV screen as a video teletype
at the most limited level of operation. Only 512 bytes,
one for each character, need to be stored, each byte
being a minimum of six bits wide per the ASCII
code. If video inversion switching or alpha to semigraphics switching is required per character then two
extra bits are required in the display RAM as shown
in Fig. 5. The semigraphics modes each offer an intermediate range of graphics densities with tradeoffs in
density versus color. Typical semigraphics display
capabilities are bar graphs, charts, mini displays, etc.
which with minor mode switching to alphanumerics
modes allow annotation or captioning of the resultant
display. The various graphics modes provide greater
density displays with greater freedom of display presentations. The tradeoffs in increasing density are with
increasing display memory size and color versus density. A minimum Graphics 0 provides a display density
of 64 x 64 (4096) elements, each element being composed of a matrix of 12 (4 x 3) dots with a selection of
four colors per element. Since each of the even
numbered 4 color graphics modes map two bits of the
data word to one picture element, each data word of
memory provides four picture elements. Thus
Graphics 0 requires 4096/4 = 1024 bytes of display
RAM, Graphics 2 requires 8192/4 = 2048 and so on.
Graphics 1, like all the odd numbered 2 color graphics
modes, maps one bit of data word to one picture element. Each data word therefore maps eight elements.
Graphics 1 density of 128 x 8 (8192) elements therefore
requires 8192/8 = 1024 bytes of display RAM and
Graphics 7, the densest display, requires 49, 152/8 =
6144 bytes of RAM. At the higher density graphics
displays, the rate of change of elements approaches the
maximum qot frequency of 6MHz. This video rate
taxes the capabilities of most commercially available
television sets and thus the quality of the display
system (television or monitor) should be commensurate
with the highest video rate to be used.

Electrical Specifications
Absolute Maximum Ratings

Supply Voltage .................................................................... 7.0V
Input Voltage ...................................... : ...................... -O.3V to +7.0V
Operating Temperature ................ , ....................................... O°C to 70°C
Storage Temperature ....................................................... - 65°C to150°C
3.148

S68047

DC (Static) Characteristics (Vee = 5.0V ± 5% ; TA = 25°C, unless otherwise specified).
Symbol

Parameter

Min.

Typ.

Max.

Unit

VIH

Input Voltage High

2.0

Vee

VIH

Input Voltage High
(Color Clock only)

4.0

Vee

VIL

Input Voltage Low

- 0.3

+0.6

lIN

Input Leakage Current
(all inputs)

2.5

J1A

1.0

Conditions

VIN = 0 - 5.25V;
Vee = OV

IL(TS)

Tri-State Output
Leakage Current (AO - All)

J1A

Vee = 5.25V; MS = OV;
VIN = 0.4 -2.4V

ILO

Output Leakage Current
(HS, FS, RP)

J1A

VIN = 2.4V; Vee = OV

VOH

Output Voltage High
(AO - All, HS, FS, RP)

VOL

Output Voltage Low
(AO - All, HS, FS, RP)

2.4
0.4

IOH = -100pA (HS, FS, RP);
OpA (Ao - AU); CL = 30pF

IOL = 1.6mA (HS, FS, RP);
OmA (AO - AU); CL = 30pF

lee

Vee Supply Current

rnA

Vee = 5V; TA = 25°C

CIN

Input Capacitance

VIN =: 0, TA = 25°C;
f = 1.0MHz

COUT

Output Capacitance

VIN = 0, TA = 25°C;
f = 1.0MHz

AC Electrical Characteristics (Vee = 5.0V ± 5%; TA = 0 - 70°C except where noted).
Alpha Internal Mode (Figure 1)
Symbol
fvc
tch
tAec
tdot

Parameter

Min.

Typ.

Max.

Unit

Video Clock Frequency
Character Time
Access-Time of External
Refresh RAM
Dot Time

5.6
1.43

6.0
1.33

6.4
1.25

MHz

166

0.7
156

Jls

178

J1S

Alpha External Mode (Figure 1)
NOTE: All parameters are the same as in Alpha Internal Mode except tACC
tAee

Access-time of Refresh
RAM + Access-time of
External ROM

0.7

Semigraphics Mode (Figure 1)
tpic

Picture Element Duration

NOTE: All other parameters are the same as in Alpha Internal Mode.
3.149

J1S

Conditions

568047

Color Sub-carrier Input
Symbol

Parameter

fcc

Frequency

tr
tf
PWcc
VrL
Vrn
DR

Rise Time
Fall Time
Pulse Width
Zero Level
One Level
Duty Ratio

Min.

Typ.

Max.

10
10
140
0.6
50%

Conditions

MHz

3.579545
±10 Hz

4.0
40%

Units

ns
ns
ns
V
V

60%

Figure 1. Refresh RAM Interface Timing
VIDEO CLOCK (t/ll)

AO- All

DO - 07, CSS
A/S, INV, INT /EXT

LATCH DATA
(Internal to the chip)

Y, R-Y, B-Y

DOT BEING
DISPLAYED
(FUll ALPHA)
PICTURE ELEMENT
BEING DISPLAYED
(SEMIG RAPHICS)

Composite Video Timing (Figure 2 )
Typ.

Symbol

Parameter

tSYNC
tfp

Sync duration

4.888889

J.1s

Front Porch duration

1.536508

J.1s

tBLANK
t rs , tfs

Horizontal Blank Duration

t rv , tfv

Min.

Rise time and Fall time of
Horizontal Sync
Rise time and Fall time of
Horizontal Blank
3.150

Max.

Units

11.44

J.1s

250

340

Conditions

868047

Figure 2. Composite Video Timing on Y Pin

VBLANK--- - - - - - VBLACK---- - VWHITE _ _ _ _ _~

Chroma R and Chroma B Output Timing; CL = 10pF; 1K Load (Figure 3.)
Symbol

Parameter

trB, tf8
trR, tfR
tSCB
tBURST
tfcB, trcB

Color Signals rise and
fall time
Color Burst to Sync lag
Color Burst Duration
Color Burst rise and fall
times
Video to color signals lag

tCLl, tCL2

Typ.

Min.

Max.

Units

50
410
2.45

ns
ns
JiS

175
75

ns
ns

Conditions
Load = R-Y, B-Y
input of LM1889

V oltage Levels
Video (Y) and Chroma (R-Y, B-Y) Output Levels (Figure 3.) CL
Vcc = 5V ± 5%
Symbol

Parameter

VSYNC

Sync Voltage

VBLANK

Blanking Level

Min.

Typ.

Max.

0.1

0.5

= 10pF; Video Clock = 5.6MHz; TA = 25°C;
Units
V

1.5

V
V

VBLACK

Black Level

1.7

VWHlTE
VBl, VRl

White level

4.0

Vcc

4.0

VCC

0.5

V
V

2.4
2.4

2.0

VBO, VRO
0

VBURST

0.1
0.4

VCHROMA BIAS

2.0

VB3, VR3

3.151

Conditions

S68047

Figure 3. Chroma Timing

Video Display Format Timing (Figure 4.)
Symbol

Parameter

H
V
F

Horizontal Scan Time
Field Time
Frame Time
Field Rate
Active Display Duration
Active Display + Border
Duration
Row Preset Period
(12 Horizontal Scans)

ltv
tACTIVE
tVIDEO
tRP

Typ.

Units

63.55557
16.683337
33.366674
59.94004
41

ms
ms
sec 1

52.8
762.66684

Figure 4. Video Display Format

BORDER

ACTIVE
DISPLAY
AREA

" - - - - - - - ' gm
OF VERT.
BLANK

'-tACTIVE-1

1- - - t V I D E O - - I-------H-------I

3.152

I.Ls

I.LS
I.LS
I.LS

Conditions

568047

Pin Description (Figure 2.)

Vee

+5V

Vss
CC

OV
(Color Burst Clock 3.579545 MHz)

(Video Clock Oscillator == 6MHz)

AO - All

(Address Lines to Display Memory; high-impedance during MS low)

DO - D5

(Data from Display Memory RAM or ROM; D4 - D6 - Color Data in Semigraphics)

D6, D7

(Data from Display Memory in GRAPHIC Mode; Data also in ALPHANUMERIC Mode;
Color Data in ALPHA SEMIGRAPHIC - 6)

R - Y, B - Y, Y

(Color and Composite Video)

CHB

(Chroma Bias; References R - Y and B - Y Levels)

(Row Preset in any ALPHA Mode; goes low in all modes every 12 lines)

(Horizontal Sync)

INV

(Inverts Video in all FULL ALPHA Modes; no effect in Semigraphics or Graphics Mode) 1:-_:
(Switches to External ROM in ALPHA Mode; between SEMIG - 4 and SEMIG - 6 in
Semigraphics; no effect in all Graphics Modes)

EXTjINT
AjS

(AlphajSemigraphics: Selects between FULL ALPHA and SEMIGRAPHICS in ALPHA
Modes; no effect in all Graphics Modes)
(Memory Select; forces VDG Address Buffers to high-impedance state; also used as a strobe
in TEST and RESET functions). The TV screen is forced black when MS = low

AjG

(Switches between ALPHA and GRAPHIC Modes)

(Field Synchronization; LOW during vertical blanking time)

CSS

(Color Set Select: Selects between two ALPHA Display Colors; between two Color Sets in
SEMIGRAPHICS - 6 and FULL GRAPHICS: selects Border Color in 8 Graphic Modes)

GM1, GM2
GM4

(Graphics Mode Select; select one of eight Graphic Modes; no affect in Alpha and Semigraphic Modes; GM1, GM2 select TEST and RESET mode when AjG = 0 and MS pin is
strobed low)

I nternal Description

Internally the VDG is the combination of four integrated subsystems (timing and control, MUX, address
buffers and shift registers to form the VDG function. A
block diagram of the VDG is shown on Page 1. Each
subsystem is described below.

ternal RC and generates addresses AO - All to address the external refresh RAM.

Timing and Control

The EXT JINT input has two functions. In the full
alphanumeric mode, it is used to select either internal
ROM or external ROM. It is also used to select between semigraphic 4 and semigraphic 6 mode in semigraphic modes (AjS = 1).

The timing and control SUbsystem of the VDG uses
the 3.58MHz color frequency to generate timing information. It accepts the color clock (generated off-chip)
(CC) input and generates timing for the horizontal
sync, horizontal blank, field sync, vertical blank and
row preset signal (RP) for external character generator
ROM. The video clock is generated on-chip by ex-

The color-set-select (CSS) input to the Timing and
Control subsystem of the VDG is used to determine
the color-set of the display.

The INV input is utilized by the timing and control
subsystem to invert the display while in full alpha
mode.

3.153

S68047

Internal Description (Continued)

A/G, A/S, GM1, GM2, GM4 inputs to the timing and
control subsystem determine which of the fourteen
. VDG modes is to be used (Table 1).

on the TV screen. The shift registers output also goes
to the chroma encoder circuitry to determine the
color of each individual dot. Each shift register has
4-bits.

vnG
The VDG has fourteen modes, grouped in three sets.
They are:

MUX
The MUX provides the function of selecting the data
source to be displayed. The source can be either internal ROM or external ROM or RAM. For the internal
alphanumeric mode, the data source is the internal
ROM. For all other modes (semigraphic and graphics)
the data source is external ROM/RAM.

4 Alphanumerics Modes

2 Semigraphics Modes

o
o
o
o

o
o

Normal internal alpha
Inverted internal alpha
Normal external alpha
Inverted external alpha

Semigraphics 4
Semigraphics 6

8 Full-graphics Modes
Address Buffers
The address buffers provide the buffering required
for external drive (ROM/RAM). The buffers are tristated when the MS pin goes low and tri-states the
buffers so that VDG does not interfere with the MPU
operation. The FS pin (output) from the VDG
signals to the MPU that the TV is in the vertical retrace mode and the MPU can directly change the data
in the display memory during that time with no
interruption to displayed data.
Shift Registers
The two shift registers serialize bytes coming from
internal/external ROM/RAM for conversion to data

o
o

4 Graphics four-color modes
4 Graphics two -color modes

The six alphanumeric modes can be switched among
themselves on a character-by-character basis. Switching within the six alphanumeric modes is referred to
as minor-mode switching. All other mode switching is
referred to as major-mode switching.
The display can be major-mode switched on after
any multiple of twelve rows have been completed.
This is signalled to the MPU by RP output going low.
Switching among the full-graphics modes is permitted
.at the end of every twelfth row just as in majormode switching.

Table 1 tabulates the modes of the VDG. The data structures for each mode are listed in Table 7. Table 2 and
Table 3 show the Alpha Select Mode and Graphic Select Mode configurations respectively. Table 4 gives the
Two-color Graphics and Full-alpha Color Specification. Table 5 shows the semigniphics and Four-color
Graphics Color Specification.
Table 1. VDG Modes
Descri~tion

Mode
I.
IV.
V.

ALPHA
ALPHA
ALPHA
ALPHA
ALPHA

VI.

ALPHA SEMIGRAPHICS 6

VII.
VIII.
IX.
X.
XI.
XII.
XIII.
XIV.

GRAPHICS 0
G.RAPHICS 1
GRAPHICS 2
GRAPHICS 3
GRAPHICS 4
GRAPHICS 5
GRAPHICS 6
GRAPHICS 7

II.

III.

INTERNAL
INTERNAL INVERTED
EXTERNAL
EXTERNAL INVERTED
SEMIGRAPHICS 4

32 x 16 BOXES: 5 x 7 CHARACTER
IN 8 x 12 BOX
32 x 16 BOXES: 5 x 70 R 7 x 9 CHARACTERS
IN 8 x 12 BOX OR FULL 8 x 12 LIMITED GRAPHICS
32 x 16 BOXES: 2 x 2 ELEMENTS PER BOX;
EIGHT COLORS PLUS BLACK
32 x 16 BOXES 2 x 3 ELEMENTS PER BOX;
FOUR COLORS PLUS BLACK
64 x 64 ELEMENTS: FOUR COLORS PER ELEMENt
128 x 64 ELEMENTS: TWO COLORS PER ELEMENT
128 x 64 ELEMENTS: FOUR COLORS PER ELEMENT
128 x 96 ELEMENTS: TWO COLORS PER ELEME~T
128 x 96 ELEMENTS: FOUR COLORS PER ELEMENT
256 x 96 ELEMENTS: TWO COLORS PER ELEMENT
128 x 192 ELEMENTS: FOUR COLORS PER ELEMENT
256 x 192 ELEMENTS: TWO COLORS PER ELEMENT

3.154

Memor~

512x7-8
512x7-8
512x4-7
512xS-8
1K x B
1K x 8
2K x 8
1.5K x 8
3K x 8
3K x 8
6K x 8
6K x 8

568047

Table 7. Detailed Description of VDG Model

VDG DATA BUS

I'-v-'I I I I I I I

ALPHANUMERIC INTERNAL mode uses internal
character generator with on-chip 64 ASCII character ROM to display each character in 5x7 dot

I I I II I

ALPHANUMERIC EXTERNAL mode uses external
ROM or RAM to display 5t 2 characters In custom fonts each in 8x12 dot matnx

NOT
USED

ASC.,NPUT

matrix font

ONE ROWDF
CUSTDMCHARACTERS

Lx C2 C1 Co
0 X X X
0 0 0
0 0
0 1
0 1
1 1 0
1 1 0 1
1 1 1 0
1 1 1 1

Lx C1 Co
0 0 0
0 0
0 1
1 0
1

0
0

1 1 0
1 1 1

Color
Black
Green
YellOW
Black
Cyan
Red
Blue
Cyan/
Blue
Magenta
Orange
Black
Green
YellOW
Cyan
Red
Black
Blue
Cyan/
Blue
Magenta
Orange

C1 Co
0 0 Green
1 Yellow
1 0 Cyan
Green
1
Red
0
Blue
Cyan/
0 1 Cyan/ Blue
Blue
1 0 Magenta
1 1 Orange

0
0

0 ~

Lx
0

Color
Black

L __ ____ Q.r~'2._

Same color as
Graphics 0

Black
Cyan/
Blue

Green

-Cyan/

Same color as
Graphics t

Green

rcya;;;

Same color as
Graphics 0

..Q.
t

Same color as
Graphics 0

Same color as
Graphics t

64 Display
elements in rows

mined by 3 bits (CO-C3)

SEMIGRAPHICS 6 mode subdivides each of the
512 (32x16) character blocks of 8x12 dots into
six equal parts. The luminance of each part is
determined by the corresponding bits (LO-L5) on
the VDG bus. Color of each block is determined
~L5IL4Il3IL21L1ILO! by2bitS(CO.C1)

Ll.lO
L3L2
L5L4

48 Display
elements In rows

LUMIHEHCE

COLOR

LUMIHEHCE

GRAPHICS 0 mode uses a maximum of t 024
bytes of display RAM in which one parr 'of bits
(CO. C1) specifies on picture element. (Ex.)

WHEREEX

C1CO

GRAPHICS 1 mode uses a maximum of 1024
bytes of display RAM in which one bit (Lx)
speclfres one picture element

128 Display
elements in
columns
64 Display

128 Display
elements in
columns
64 Display
elements In rows

Icllcolcllcolcllcolcllcol

GRAPHICS 2 mode uses a maximum of 2048
bytes of display RAM in which one pair of bits
(CO. C1) specifies one picture element (Ex.)

128 Display
elements in
columns
96 Display
elements In rows

GRAPHICS 4 mode uses a maximum of 3072
by1es of display RAM in which one pair of bits
(CO. C1 specifies one picture element (Ex.)

GRAPHICS 5 mode uses a maximum of 3072
bytes of display RAM In which one bit (Lx)
specifies one picture element

Blue

256 Display
elements in
columns
96 Display
elements in rows

Green

128 Display
elements in
columns

Green

'ey;;;;(
Green

-Cyan/
-Cyan/
Blue

64 Display
elements in
columns

~ ~:;e~~~n~~t~Yb~Se ~o:l~ers~~~~~nhg b~~tc~L~s-~~:e~n
HOT COLOR
USED

GRAPHICS 3 mode uses a maximum of 1536
bytes of display RAM in which one bit (Lx)
specifies one picture element

Blue
Same color as
Graphics t

L3L2

128 Display
elements in
columns
96 Display
elements in rows

Green

Cyan/
Blue

32 Display
elements in rows

Blue

Blue
t

SEMIGRAPHICS 4 mode subdiVides each of the
512 (32x16) character blocks of 8x12 dots into
four equal parts. The dominance of each block is

64 Display
elements In
columns

64 Display
elements in
columns

COMMENTS

Green

-Cyan/
Blue

GRAPHICS 6 mode uses a maximum of 6144
bytes of display RAM in which one pair of bits

.1 clicoiclicoicllcolcllcol (co. C1) specifies one picture element (Ex.)

192 Display
elements in rows
256 Display
elements in
columns
t92 Display
elements in rows

I L71L6ll51L41L31L21LlllOI

3.155

GRAPHICS 7 mode uses a maximum of 6144
bytes of display RAM in which one bit (Lx)
specifies one picture element

568047

Table 2. Alpha Mode Select
GM2

GM1

A/G

A/S

INT/EXT

INV

MODE

INTERNAL ALPHANUMERICS
INTERNAL INV. ALPHA

EXTERNAL ALPHA

EXTERNALINV.ALPHA

SEMIGRAPHICS -4

STROBED LOW

TEST ROM

STROBED LOW

RESET

NOTES:

SEMIG RAPHICS - 6

1) GM4 pin has no effect when A/G = O.
2) I nvert pin has no effect except in I nternal Alpha or External Alpha.
3) Under normal operation, care should be taken not to take GM 1 pin HIG H, when A/G pin is LOW. If this happens, any of the follow·
ing conditions will occur depending on the status of MS and GM2 pin:
a) The VDG might go to TEST mode.
b) The VDG might be reset.
The VDG will not return to normal operation unless A/G and GM 1 pins are returned to LOW level and MS pin is strobed.
4) X = Don't care.

Table 3. Graphic Mode Select
GM4

GM2

o
o

GRAPHICS 2

o
o
o

GRAPHICS 3

A/G
GRAPHICSO
GRAPHICS 1

GRAPHICS 4
GRAPHICS 5

MODE

GM1

64 x 64 4 - CO LO R
128 x 64 2 - COLOR

128 x 64 4 - COLOR

128x962-COLOR

o
o

128 x 96 4 - COLOR

256 x 96 2 - COLOR

GRAPHICS 6

128x 192 4-COLOR

GRAPHICS 7

NOTE:

256 x 192 2 - COLOR

A/S, INT/EXT, INV pins have no effect when A/G

= 1.

Table 4. Two-Color Graphics and Full·Alpha Color Specification

CSS PIN

COLOR OF 'ON' DOTS

GREEN

CYAN·BLUE

3.156

S68047

Table 5. Semigraphics and Four-Color Graphics Color Specification

4-COLOR
GRAPH ICS

SEMIGRAPHICS - 6

SEMIGRAPHICS-4

EVEN BIT
ODD BIT
CSS

06
07
CSS

04
05
06
COLOR
SET

111

GREEN
YELLOW
CYAN
RED
BLUE
CYAN/BLUE
MAGENTA
ORANGE

0
0
0 1
0

COLOR
SET
2

NOTE:

In Semigraphics - 6, if any bit DO - 05 is '0', then picture element corresponding to that bit wouldbe black. In Semigraphics - 4, if
any bit DO - 03 is zero, then the picture element corresponding to that dot will be black.

Table 6. Two-Color Graphics and Four-Color Graphics Border Color Specification

CSS PIN

BORDER COLOR

GREEN
CYAN-BLUE

Typical System: A typical S6800 microprocessor based
S68047 system is shown on Figure 5. This system has
the capability of displaying internally and externally
generated characters, semigraphics 4 and 6 modes with
mode switching control from the microcomputer
input/output ports. A full graphics system configuration would be similar in complexity with possibly
additional display RAM for the denser graphics modes.
The National Semiconductor LM1889 RF modulator,
shown, has an on chip 3.58 MHz oscillator which can

provide the microcomputer system clock as well as
the color burst reference for the S68047. Other RF
modulators are available through various commercial
channels. Only 512 bytes are needed to display the
512 character blocks on a TV screen. However, because
of current static RAM configurations (ie. 1Kx1 &
1Kx4) the extra 512 bytes available in the 1Kx9 RAM
shown can be used as scratchpad by the host microcomputer system.

Ordering Information

Ordering No.
S68047

Description

No. Pins

Package

Temp. Range

Ceramic

0-70°C

VDG non -interlaced

S68047P

Plastic

0-70°C

VDG non -interlaced

S68047Y

0-70°C

VDG interlaced

S68047YP

Ceramic
Plastic

0-70°C

VDG interlaced

3.157

868047

Figure 5. Typical System (Alphanumeric Internal/External & Semigraphics 4 and 6 Modes.)

Physical Dimensions
40·Pin SLAM

40·Pin Plastic

P1NlIDENTIFIER"\,

t ---.1
!H\~~
/~

o.61016END
0.590

WMAX~

O.020 TyP

0'°1__
r-!
0.012
0.008

3.158

~--i- 0.020 MIN
---1l--0.200MAX

0.090 "IN-i

ADVANCED PRODUCT DESCRIPTION

S68488

GENERAL PURPOSE
INTERFACE ADAPTER
Features

General Description

The S68488 GPIA provides the means to interface between the IEEE488 standard instrument bus and the
S6800. The 488 instrument bus provides a means for
controlling and moving data from complex systems of
multiple instruments.

o
o
o

o
o
o
o
o
o
o

Single or Dual Primary Address Recognition
Secondary Address Capability
Complete Source and Acceptor Handshakes
Programmable Interrupts
RFD Holdoff to Prevent Data Overrun
Operates with DMA Controller
Serial and Parallel Polling Capability
Talk-Only or Listen-Only Capability
Selectable Automatic Features to Minimize
Software
Synchronization Trigger Output
S6800 Bus,Compatible

The S68488 will automatically handle all handshake
protocol needed on the instrument bus.

Block Diagram

Pin Configuration
"HANDSHAKE

S6800
DATA BUS

MGMT,
BUS{

Vss
DMA GRANT

cs
ill
R/W
¢2

DO
01

DATA 10
DI01·DIOB

NOTE 1:

TYP 16 PLACES

*The 3-wire handshake described is the subject
of patents owned by Hewlett-Packard Co.

3.159

568488
Functional Description

The IEEE 488 instrument bus standard isa bit-parallel,
byte-serial bus structure designed for communiation
to and from intelligent instruments. Using this standard, many instruments may be interconnected and
remotely and automatically controlled or programmed. Data may be taken from, sent to, or transferred between instruments. A bus controller dictates
the role of each device by making the attention line
true and sending talk or listen addresses on the instrument bus data lines; those devices which have matching
addresses are activated. Device addresses are set into
each GPIA from switches or jumpers on a PC board
by a microprocessor as a part of the initialization
sequence.
When the controller makes the attention line true,
instrument bus commands may also be sent to single
or multiple GPIAs.
I

Information is transmitted on the instrument bus
data lines under sequential control of the three handshake lines. No step in the sequence can be initiated
Figure 1.
DATA BUS
ES
)

IB Lr

DATA BYTE
TRANSFER
CONTROL

until the previous step is completed. Information
transfer can proceed as fast as the devices can respond,
but no faster than the slowest device presently addressed as active. This permits several devices of different speeds to receive the same data concurrently.
The GPIA is designed to work with standard 488 bus
driver Ics (83448As) to meet the complete electrical
specifications of the IEEE488 bus. Additionally, a
powered-off instrument may be powered-on without
disturbing the 488 bus. With some additional logic,
the GPIA could be used with other microprocessors.
The 868488 GPIA has been designed to interface between the 86800 microprocessor and the complex
protocol of the IEEE488 instrument bus. Many
instrument bus protocol functions are handled automatically by the GPIA and require no additional MPU
action. Other functions require minimum MPU
response due to a large number of internal registers
conveying information on the state of the GPIA and
the instrument bus.

GENERAL
INTERFACE
MANAGEMENT

OAV

....L1+-________-+-_______+-_ _ _ _ _ _ _ _ _ _ _ _

/AL---_ _

DI10

--I

ill

DAC

IFc

RFO

SFffi

EOl

------------:= ~41~~~~~ ~~1~~~~+-4 h~l-r~-r~~ ~~1~+_~4-~------~
v

~/ll

DEVICE A
ABLE TO TALK,
LISTEN, AND
CONTROL
e.g., CALCULATOR

vii

DEVICE B
ABLE TO TALK
AND LISTEN
e.g., DIGITAL
MUL TIMETER

vlt

'VI

DEVICE C
ONLY ABLE
TO LISTEN
e.g., SIGNAL
GENERATOR

S6B4BB

S6B02

3.160

DEVICE 0
ABLE TO TALK
AND LISTEN

568488
Maximum Ratings
Supply Voltage ........................................................ -0.3Vdc to +7.0Vdc
Input Voltage ......................................................... -0.3Vdc to +7.0Vdc
Operating Temperature Range .................................................. O°C to +70°C
Storage Temperature Range ................................................ -55°C to +150°C
Thermal Resistance ....... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. +82.5°C/W
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields, however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit.

Electrical Characteristics (Vee = 5.0V ±5%, VSS = 0, TA = O°C to +70°C unless otherwise noted)
Symbol

Parameter

Min.

VIH

Input High Voltage

VSS + 2.0

VIL

Input Low Voltage

VSS - 0.3

Typ.

Max.

Unit
Vdc
J1Adc

VIN = 0 to 5.25V

J1Adc

VIN = 0.4 to 2.4V

lIN

Input Leakage Current

1.0

Vee
VSS + 0.8
2.5

ITSI

Three -State (Off State)
Input Current
DO-D7

2.0

VOH

Output High Voltage
DO-D7

VOL

PD
CIN

Vdc

Iload = - 205J1A

VSS+O.4
VSS+O.4

Vdc

IJoad = 1.6mA
IJoad = 3.2mA

J1Adc

VOH = 2.4Vdc

VSS + 2.4

Output Low Voltage
DO-D7
IRQ

ILOH

Conditions

Output Leakage Current
(Off State)
IRQ
Power Dissipation

1.0
600

Input Capacitance DO-D7
All Others

12.5
7.5

Figure 2. Source and Acceptor Handshake
0101.0108

=:=>('--_____...JX'-___

SOURCE

OAV _ _ _---,

VAllO
RFO _ _
A_LL_RD_Y_-;.I--,

I I

NONE

ISOM:C~DY
i

OAC

I
I

ALL

IACCEPTOR

ALLI ACC

rrm'---_ACCEPTOR

OATA
TRANSFER

OATA
TRANSFER
END

BEGIN

SOURCE
SOME
ROY

3.161

VIN = 0,
TA=25°C,
f = 1.0MHz

568488
Bus Timing Characteristics
Read (See Figure 3)
Symbol

Parameter

Min.

Enable Cycle Time

1.0
0.45
0.43
160

tcycE
PWEH

Enable Pulse Width, High

PWEL

Enable Pulse Width, Low

tAS

Setup Time, Address and
R/W valid to enable
positive transition

tDDR

Data Delay Time

Data Hold Time

tAH

Address Hold Time

tEr, tEf

Rise and Fall Time for
Enable input

Typ.

Max.

Unit

Conditions

}J.s
}J.s
}J.s
ns

320
10
10

See
Figure 3

ns
ns
ns

Write (See Figure 4)
tcycE
PWEH

Enable Cycle Time

PWEL

Enable Pulse Width, Low

tAS

Setup Time, Address and
R/W valid to enable
positive transition

Enable Pulse Width, High

tDSW

Data Setup Time

Data Hold Time

tAH

Address Hold Time

tEr,tEf

Rise and Fall Time for
Enable input

}J.s

1.0
0.45
0.43
160

}J.s
}J.s
ns
See
Figure 4

195
10
10

ns
ns
ns

400

DAV, DAC, RFD,
EOr, ATN valid

400

TiR1, TiR2 valid

Output (See Figure 5)
tHD
Output Delay Time
tT/R1,2D
Figure 3. Bus Read Timing Characteristics
(Read Information from GPIA)
~

Figure 4. Bus Write Timing Characteristics
(Write Information into GPIA)

_ _ _ t",'E _ _~

ENABLE

RS,

CS, R/W

DATA BUS

3.162

568488
Figure 5. Output Bus Timing
ENABLE

----.J

(rAV, DAC, RFD, Elf!,

ATri

lusv
f.--tHD

2.0V
O.SV

~tT/Rl,2D - - - - - .

}

T/R1, T/R2

A.C. Time Values

Symbol*
T1

*
**

Parameter

Min.

Settling Time for Multiple Message

Response to A TN

Interface Message Accept Time

Response to IFC or REN False

Response to ATN • EOI

SH, AH, T, L

Typ.

Max.

~200

Unit

Conditions

/1s**
ns

T,TE,L,LE

<100

~200

/1S
ns

Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified
by an upper case T indicate the minimum time that a function must remain in a state before exiting.
If three -state drivers are used on the DIO - DA V and EOI lines, Tl may be:

(1) >1100ns
(2) Or ~700ns if it is known that within the controller ATN is driven by a three-state driver.
(3) Or ~500ns for all subsequent bytes following the first sent after each false transition of ATN [the first byte must be sent.
in accordance with (1) or (2)].

Time required for interface functions to accept, not necessarily respond to interface messages.

f Implementation dependent.
MPU bus clock rate - The current 6800 bus clock is
settling times (T1).

1MHz but part should operate at 1.5MHz (design goal), with appropriate

GPIA/MPU Interface Signals

The S68488 interfaces to the S6800 MPU with an
eight- bit bidirectional data bus, a chip select, Read/
Write line, reset line, three register select lines, an
interrupt request line, two DMA control lines, and an
address switch enable line.
Bidirectional Data (DO-D7) - The bidirectional data
lines allow the transfer of data between the MPU and
the GPIA. The data bus output drives are three-state
devices that remain in the high impedance (off) state
except when the MPU performs a GPIA read operation.

3.163

Chip Select (CS) - This input signal is used to select
the GPIA. CS must be low for selection of the device.
Chip select decoding is normally accomplished with
logic external to the chip.
Read/Write Line (R/W) - This signal is generated by
the MPU to control register access and direction of
data transfer on the data bus. A low state on the
GPIA Read/Write allows for the selection of one of
seven write-only registers when used in conjunction
with the register select lines RSO, RS1, RS2. A high

568488
state on the GPIA Read/Write allows for the selection
of one of eight read-only registers when used in conjunction with register select lines RSO, RS1, RS2.
Register Select (RSO, RS1, RS2) - The three register
select lines are used to select the various registers
inside the GPIA. These three lines are used in conjunction with the Read/Write line to select a particular
register that is to be written or read. Table 1 shows
the register select coding.

RS1

a
a
a
a
a
a
a
a

a
a
a
a

1
1
1
1
1
1
1
1

1
1
1
1
0

a
0

a
1
1
1
1

RSO R/W REGISTER TITLE

a
a

a
1

1
1

a
a

1
1

a
a

1
1

1
0

INTERRUPT STATUS
INTERRUPT MASK
COMMAND STATUS
UNUSED
ADDRESS STATUS
ADDRESS MODE
AUXILIARY COMMAND
AUXILIARY COMMAND
ADDRESS SWITCH*
ADDRESS
SERIAL POLL
SERIAL POLL
COMMAND PASS·THROUGH
PARALLEL POLL
DATA IN
DATA OUT

Address Switch Enable (ASE) - The ASE output is
used to enable the device address switch three-state
buffers to allow the instrument address switch to be
read on the MPU bus.
Clock Input (Clk) - The clock input is normally a
derivative of the MPU ¢2 clock.

Table 1. Register Access

RS2

The DMA request line is cleared when the DMA grant
is made true. The DMA grant line is used to signal the
GPIA that the DMA controller has control of the
MPU data and address lines. * DMA Grant must be
grounded when not in use!

GPIA/488 Interface Bus Signals
The GPIA provides a set of eighteen interface signal
lines between the S6800 and the IEEE Standard 488
bus.

Signal Lines (IBO-IB7) - These bidirectional lines
allow for the flow of seven bit ASCII interface messages and device-dependent messages. Data appears
on these lines in a bit-parallel byte-serial form. These
lines are buffered by the transceivers and applied to
the 488 but (DI01-DI08).

R2R
R2W
R3R
R3W
R4R
R4W
R5R
R5W
R6R
R6W
R7R
R7W

Byte Transfer Lines (DAC, RFD, DA V) - These lines
allow for prop~r transfer of each data byte on the bus
between sources and acceptors. RFD goes passively
true, indicating that all acceptors are "ready for data."
A source will indicate the "data is valid" by pulling
DAV low. Upon the reception of valid data by all
acceptors, DAC will go passively true, indicating that
the "data has been accepted" by all acceptors.

*External to S68488

Interrupt Request (IRQ) - The IRQ output goes to
the common interrupt bus for the MPU. This is an
open drain output which is wire-ORed to the IRQ
bus. The IRQ is set false (low) when an enabled interrupt occurs and stays false until the MPU reads from
the interrupt status register.

Bus Management Lines (ATN, IFC, SRQ, EOI, REN)These lines are used to manage an orderly flow of
information across the interface lines.

Attention (ATN) - This is sent true over the interface to disable current talker and listeners, freeing
the signal lines (IBO -IB7). During the ATN, active
state devices monitor the DI01 for addressing or an
Reset - The active low Reset line is used to initialize
interface command. Data flows on the DI01 lines
the chip during power on start up. Reset will be driven
when ATN is inactive (high).
by an external power-up reset circuit.

DMA Control Lines (OMA Grant, OMA Request) The DMA request line is used to signal waiting data
when Byte In (BI) or Byte Out (BO) is set high for a
DMA controller. The OMA request line is set high if
either the BI or BO interrupt flags are set in the Inter. rupt Status Register (ROW) and the corresponding
bits in the Interrupt Mask Register (ROR) are set true.

Interface Clear (IFC) - This is used to put the interface system into a known quiescent state.
Service Request (SRQ) - This is used to indicate a
need for attention in addition to requesting an interruption in the current sequence of events. This indicates to the controller that a device on the bus is in
need of service.

3.164

568488
Remote Enable (REN) - This is used to select one of
two alternate sources of device programming data,
local or remote control.

ing the parallel polling sequence. During parallel poll,
Em will be made an input by T/R1 while DAV and
IBO-IB7 lines are outputs.

End of Identify (EOI) - This is used to signal the end
of a multiple byte transfer sequence and, in conjunction with ATN, executes a parallel polling sequence.

GPIA INTERNAL CONTROLS AND REGISTERS*

Transmit/Receive Control Signals (T/R1, T/R2) These two signals are used to control the quad transceivers which drive the interface bus. It is assumed
that appropriate transceivers will be used where each
transceiver has a separate transmit/receive control pin.
These pins can support one TTL load each. The outputs
can then be grouped as shown in the Block Diagram
with SRQ hardwired high to transmit. The transmit/
receive inputs of REN, IFC, and ATN are hardwired
low to receive. ROI is controlled by T/R1 through
the S3448A (or an equivalent), allowing it to transmit
or receive. T /R1 operates exactly as T /R2 except dur-

There are fifteen locations accessible to the MPU data
bus which are used for transferring data to control
the various functions on the chip and provide current
chip status. Seven of these· registers are write only
and eight registers are read only. The various registers
are accessed according to the three least significant
bits of the MPU address bus and the status of the
Read/Write line. One of the fifteen registers is external
to the IC but an address switch register is provided
for reading the address switches. Table 2 shows actual
bit contents of each of the registers.
*N ote: Upper and lower case type designations will be used with
the register bits to indicate remote or local messages, respectively.

Table 2

ROW

IRQ

GET

APT

CMO

END

Interrupt "Mask" Reg.

ROR

INT

GET

APT

CMO

END

I nterru pt Status Reg.

R1R

UACG

REM

LOK

~
~
~

RLC

SPAS

OCAS

UUCG

Command Status Reg.

ATN

TACS

LACS

LPAS

TPAS

Address Status Reg.

hide

hlda

apte

Address Mode Reg.

fget

Auxiliary Command Reg.

R1W

~~~~~~~~

R2R

R2W

dsel

R3R

R3W

Reset

to
to

OAC

OAV

RFO

rfdr

feoi

dacr

msa

rtl

ulpa
dacd

Unused

R4R

U03

U02

UOl

A05

A04

A03

A02

AOl

Address Switch Reg.

R4W

Isbe

dal

dat

A05

A04

A03

A02

AOl

Address Register

R5R

R5W

SRQS
rsv

Serial Poll Reg.

R6R

R6W

PPR8

PPR7

PPR6

PPR5

PPR4

PPR3

PPR2

PPRl

Parallel Poll Reg.

R7R

017

016

015

014

013

012

011

010

Data In Register

R7W

007

006

005

004

003

002

001

000

Data Out Register

Data-In Register R7R - The data-in register is an
actual eight- bit storage register used to move data
from the interface bus when the chip is a listener.
Reading the register does not destroy information in
the data-out register. DAC (data accepted) will remain
low until the MPU removes the byte from the data-in

Command Pass-thru Reg.

register. The chip will automatically finish the handshake by allowing DAC to go high. In RFD (ready for
data) holdoff mode, a new handshake is not initiated
until a command is sent allowing the chip to release
holdoff. This will delay a talker until the available information has been processed.

3.165

S68488
Data-In Register (Read Only)

017

I I I I I
016

015

014

013

Interrupt Mask Register (Write Only)

012

011

010

II I I I I I I I
IRQ

010·017 correspond to 0101·0108 of the 488·1975 Standard and
IBO·IB7 of the S68488.

IRQ
BO
GET
APT
CMo
END
BI

GET

APT

CMO

END

- Mask bit for IRQ pin
- Interrupt on byte output
- Interrupt on Group Execute Trigger
- Interrupt on Secondary Address Pass· Through
- Interrupt on SPAS + RLC + dsel(oCAS + UUCG + UACG)
-Interrupt on EOI and ATN
- Interrupt on byte input

Data Out Register R7W - The data-out register is an
actual eight- bit storage register used to move data out
of the chip onto the interface bus. Reading from the
data-in register has no eff€·~t on the information in
the data- out register. Writing to the data-out register
has no effect on the information in the data-in register. Interrupt Status Register ROR - The Interrupt Status
Register is a seven -bit storage register which corresponds to the interrupt mask register with an additional
bit INT bit 7. Except for the INT bit, 'th~ other bits
in the status register are set regardless of the state of
the interrupt mask register when the corresponding
Data Out Register (Write Only)
event occurs. The IRQ (MPU interrupt) is cleared
when the MPU reads from the register. INT bit 7 is
0071 0061 0051 0041 0031 0021 001 000
the logical OR of the other six bits ANDed with the
respective bit of ROW.
000·007 correspond to the 0101·0108 of the 488·1975 Standard
and IBO·IB7 of the S68488.

Interrupt Status Register (Read Only)

Interrupt Mask Register ROW - The Interrupt Mask
Register is a seven -bit storage register used to select
the particular events that will cause an interrupt to be
sent to the MPU. The seven control bits may be set
independently of each other. If dsel (bit 7 of the
Address Mode Register) is set high, CMD bit 2 will
interrupt on SPAS or RLC. If dsel is set low, CMD
will interrupt on UACG, UUCG, and DCAS in addition
to RLC and SPAS. The Command Status Register
R1R may then be used to determine which command
caused the interrupt. Setting GET bit 5 allows an interrupt to occur on Group Execute Trigger Command.
END bit 1 allows an interrupt to occur if EOI is true
(low) and ATN is false (high). APT bit 3 allows an
interrupt to occur, indicating that a secondary address
is available to be examined by the MPU if apte (bit
o of Address Mode Register) is enabled and listener
or talker primary address is received and a Secondary
Command Group is received. A typical response for a
valid secondary address would be to set msa (bit 3 of
Auxiliary Command Register) true and dacr (bit 4
Auxiliary Command Register) true, releasing the DAC
handshake. BI i~dicates that a data byte is waiting in
the data-in register. BI is set high when data-in register
is full. BO indicates that a byte from the data-out
register has been accepted. BO is set when the data-out
register is empty. IRQ enabled high allows any interrupt to be passed to the MPU.

INT
INT
BO
GET
APT
CMo
END
BI

I BO I GET I

I APT I CMO I END I

- Logical OR of all other bits in this register ANoed with the
respective bits in the interrupt mask register
- A byte of data has been output
- A Group Execute Trigger has occurred
- An Address Pass-Through has occurred
- SPAS + RLC + dsel (oCAS + UUCG + UACG) has occurred
- An EOI has occurred with ATN = 0
- A byte has been received

Serial Poll Register R5R/W - The Serial Poll Register
is an eight-bit storage regiter which can be both
written into and read by the MPU. It is used for establishing the status byte that the chip sends out when it
is serial poll enabled. Status may be placed in bits 0
through 5 and bit 7. Bit 6 rsv (request for service) is
used to drive the logic which controls the SRQ line
on the bus telling the controller that service is needed.
This same logic generated the signal SRQS which is
substituted in bit 6 position when the status byte is
read by the MPU IBO-IB7. In order to initiate a rsv
(request for service), the MPU sets bit 6 true (generating rsv signal) and this in turn causes the chip to pull
down the SRQ line. SRQS is the same as rsv when
SP AS is false. Bit 6 as read by the MPU will be the
SPQS (Service Request State).

3.166

568488
Address Mode Register (Write Only)

Serial Po" Register (Read)

I I I I
SRQS

I I dsel
to

Serial Po" Register (Write)

S8 I rsv I S6

I I
S5

hdle
hdla
apte

Sl-S8 - Status bits
rsv
- Generate a service request

Parallel Poll Register R6W - This register will be loaded
by the MPU and the bits in this register will be delivered
to the instrument but IBO-IB7 during PPAS (Parallel
Poll Active State). This register powers up in the PPO
(Parallel Poll No Capability) state. The reset bit
(Auxiliary Command Register bit 7) will clear this
register to the PPO state.
The parallel poll interface function is executed by
this chip using the PP2 subset (Omit Controller Configuration Capability). The controller cannot directly
configure the parallel poll output of this chip. This
must be done by the MPU. The controller will be able
to indirectly configure the parallel poll by issuing an
addressed command which has been defined in the
MPU software.

PP7 I PP6

I I I
PP5

PP4

T ACS
T ADS
LACS
LADS
SPAS

PP2

PPl

rna
to
10

Bits delivered to bus during Parallel-Poll Active State (PPAS)
Register powers up.in the PPO state
Parallel Poll is executed using the PP2 subset

Address Mode Register R2W - The address mode
register is a storage register with six bits for control:
to, 10, hIde, hlda, dsel, and apte. The to bit 6 selects
the talker/listener and addresses the chip to talk only.
The 10 bit 5 selects the talker/listener and sets the
chip to listen only. The apte bit 0 is used to enable
the extended addressing mode. If apte is set low, the
device goes from the TP AS (Talker Primary Address
State) directly to the T ADS (Talker Addressed State).
The hlda bit 2 holds off RFD (Ready for Data) on
ALL DATA until rfdr is set true. The hIde bit 3 holds
off RFD on EOI enabled (low) and ATN not enabled
(high). This allows the last byte in a block of data to
be continually read as needed. Writing rfdr true (high)
will allow the next handshake to proceed.

X I hdle I hdla I X

apte

Talker Active State
Talker Addressed State
Listener Active State
Listener Addressed State
Serial Poll Active State

Address Status Register (Read Only)

rna

PP3

Address Status Register R2R - The address status
register is not a storage register but simply an eight- bit
port used to couple internal signal nodes to the MPU
bus. The status flags represented here are stored internally in the logic of the chip. These status bits indicate
the addressed state of the talker/listener as well as
flags that specify whether the chip is in the talk only
or listen only mode. The ATN, bit 4, contains the
condition of the Attention Line. The rna signal is true
when the chip is in:

Para"el Po" Register (Write Only)

PP8

to I

- Configure for automatic completion of handshake sequence
on occurrence of GET, UACG, UUCG, SOC, or OCl commands.
- Set to talk-only mode.
- Set to listen-only mode.
- Hold-off RFD on end.
- Hold-off RF0 on all data.
- Enable the address pass-through feature.

dsel

Sl-S8 - Status bits
SROS - Bus in Service Request State

ATN
TACS
lACS
lPAS
TPAS

I to

I ATN I TACS ILACS I LPAS ITPAS

- My address has occurred.
- The talk-only mode is enabled.
- The listen-only mode is enabled.
- The Attention command is asserted.
- GPIA is in the Talker Active State.
- GPIA is in the listener Active State.
- GPIA is in the Listener Primary Addressed State.
- GPIA is in the Talker Primary Addressed State.

Address Switch Register R4R - The address switch
register is external to the chip. There is an enable line
(ASE) to be used to enable three-state drivers connected between the address switches and the MPU.
When the MPU addresses the address switch register,
the enable line directs the switch information to be
sent to the MPU. The five least significant bits of the
eight- bit register are used to specify the bus address
of the device, and the remaining three bits may be
used at the discretion of the user. The most probable
use of one or two of the bits is for controlling the
listener only or talk only functions.

3.167

568488
Address Switch Register (Read Only)
UD31 UD21 UDl

I AD51

AD41 AD31 AD21 ADl

- Device address.
- User definable bits.

AD1-AD5
UD1-UD3

When this "register" is addressed, the ASE pin is set, allowing external
address switch information from bus device to be read.

Address Register R4 W - The Address Register is an
eight- bit storage register. The purpose of this register
is to carry the primary address of the device. The
primary address is placed in the five least significant
bits of the register. If external switches are used for
device addressing, these are normally read from the
Address Switch Register and then placed in the Address
Register by the MPU.
ADl through AD5 bits 0-5 are for the device's address.
The lsbe bit 7 is set to enable the Dual Primary Addressing Mode. During this mode, the device will
respond to two consecutive addresses, one address
",ith ADl equal to 0 and the other address with ADl
equal to 1. For example, if the device's address is
HEX OF, the Dual Primary Addressing Mode would
allow the device to be addressed at both HEX OF and
HEX OE. The dal bit 6 is set to disable the listener
and the dat bit 5 is set to disable the talker.
This register is cleared by the Reset input only (not
by the reset bit of the Auxiliary Command Register
bit 7).
When ATN is enabled and the primary address is
received on the IBO -7 lines, the S68488 will set bit
7 of the address status register (rna). This places the
S68488 in the TP AS or LP AS.
When ATN is disabled, the GPIA may go to one of
three states: T ACS, LACS or SPAS.

Address Register (Write Only)

'gb.

I I I
dal

dat

AD51 AD41 AD31 AD21 ADI

Isbe
- Enable dual primary addressing mode.
dal
- Disable the listener.
dat
- Disable the talker.
AD1-AD5
- Primary device address, usually read from address
switch register.
Register is cl~ared by the Reset input pin only.

Auxiliary Command Register R3R/W - Bit 7, reset,
initializes the chip to the following states: (Reset is
set 'true by external Reset input pin and by writing
into the register from the MPU.)

Source Idle State
Acceptor Idle State
Talker Idle State
Listener Idle State
Local State
Negative Poll Response State
Parallel Poll Idle State
Parallel Poll Unaddressed to Configure
State
- Parallel Poll No Capability
PPO
rfdr (release RFD handshake) bit 6 allows for completion of the handshake that was stopped by RFD
(Ready for Data) holdoff commands hlda and hIde.
fget (force group execute trigger) bit 0 has the same
effect as the GET (Group Execute Trigger) command
from the controller.
rtl (return to local) bit 2 allows the device to respond
to local controls and the associated device functions
are operative.
dacr (release DAC handshake) bit 4 is set high to allow
DAC to go passively true. This bit is set to indicate
that the MPU has examined a secondary address or an
undefined command.
ulpa (upper/lower primary address) bit 1 will indicate
the state of the LSB of the address received on the
DIOl-8 bus lines at the time the last Primary Address
was received. This bit can be read but not written by
the MPU.
msa (valid secondary address) bit 3 is set true (high)
when TP AS (Talker Primary Addressed State) or
LPAS (Listener Primary Addressed State) is true. The
chip will become addressed to listen or talk. The primary address must have been previously received.
SIDS
AIDS
TIDS
LIDS
LaCS
NPRS
PPIS
PUCS

RFD, DAV, DAC (Ready for Data, Data Valid, Data
Accepted) bits assume the same state as the corresponding signal on the S68488 package pins. The
MPU may only read these bits. These signals are not
synchronized with the MPU clock.
dacd (data accept disable) bit 1 set high by the MPU
will prevent completion of the automatic handshake
on Addresses or Commands. dacr is used to complete the handshake.
feoi (forced end or identify) bit 5 tells the chip to
send Eor low. The Ear line is then returned high after
the next byte is transmitted. NOTE: The following
signals are not stored but revert to a false (low) level
one clock cycle (MPU¢2) after they are set true (high):
1. rfdr
2. feoi
3. dacr
These signals can be written but not read by the MPU.

3.168

568488
Auxiliary Command Register
rfdr
RESET
reset -

msa

rtl
ulpa
fget

rfdr
feoi
dacr

dacd

feoi

dacr

OAC OAV

RFE

msa

rtl

-dacd
ulpa

fget

WRITE
READ

initialize the ch ip to the following status:
(1) all interrupts cleared
(2) following bus states are in effect: SI OS, AIDS, TI OS, LI OS,
LOCS, PPIS, PUCS, andPPO
(3) bit is set by Reset input pin
if GPIA is in LPAS or TOAS, setting msa will force GPIA to
LADS or TAOS
return to local if local lockout is disabled
state of LSB of bus at-Iast-primary-address receive time
Force group execute trigger command from the MPU has
occurred
continue handshake stopped by RFO holdoff
set EOI true, clears after next byte transmitted
MPU has examined an undefined command or secondary
address
prevents completion of automatic handshake on Addresses or
Commands

Command Status Register R1R - The command
status register flags commands or states as they occur.
These flags or states are simply coupled onto the
MPU bus. There are five major address commands. REM
shows the remote/local state of the talker/listener.
RLC bit 3 is set when a change of state of the remote/
local flip-flop occurs and reset when the command
status register is read. DCAS bit 1 indicates that either
the device clear or selected device clear has been received activating the device clear function. SPAS bit 2
indicates that the SPE command has been received
activating the device serial poll function. UACG bit 7

indicates that an undefined address command has
been received and depending on programming the
MPU decides whether to execute or ignore it. UUCG
bit 0 indicates that an undefined universal command
has been received.
Command Status Register
(Read)

UACG

UACG
REM
LOK
RLC
SPAS
OCAS
UUCG

REM

I LOKI X I RLC I SPAS I DCAS UUCG

Undefined Addressed Command
Remote Enabled
Local Lockout Enabled
Remote/Local State Changed
Serial Poll Active State is in effect
Device Clear Actr'Je State is in effect
Undefined Unive,-sal Command

Command Pass-Through Register R6R - The command pass-through is an eight-bit port with no storage.
When this port is addressed by MPU it connects the
instrument data bus (lBO - IE7) to the MPU data bus
DO -D7. This port can be used to pass commands and
secondary addresses that aren't automatically interpreted through to the MPU for inspection.
Command Pass- Through Register
(Read Only)
B7

I I I I I
B6

Bol

An eight-bit input port used to pass commands and secondary addresses
to MPU which are not automatically interpreted by the GPIA.

3.169

S1883
UART

NSB NPB POE NOB2 NOBl

DBB DB7 OB6 DB5 DB4 DB3 DB2 DBl

(36)

(33) (32)

(23)

(35)139)(37)

(38)

(31)

(3D)

(29)

(28)

(27)(26)

Vss

TCP
POE
NDBl
NDB2
NSB
NPB
CS
DBB
DB7
DBS
DB5
DB4
DB3
DB2
DBl
TSO
TEOC

VGG

CS
(34)

)

VSS

[

TBMT

VDD

(22)

ROE
ROB
RD7
RDS
RD5
RD4
RD3
RD2
RDl
RPE
RFE
ROR
SWE
RCP
RDA
ODA
RS(

(1)-1-

V~f~:_
Voo----L.,.
(3)

)

Tep

1
I

(40)

[

I - + - t - - T - T:~

I-+-t--+-T~~~
I
I

)

TRANSMITTER

t:
~:

------.------------~EII

RECEIVER

(18)

S1B83

TDS
TBMT
RESET

I\ljJ\
(19)

ODA

(~~-)- - - - ]

r-(N~)-I

~--W--~--~--IQP--~- -~~ -t:F~[=:~~\\K

Qm- -

j::;ru

RESET

(21)~TOALL

090

REGISTERS

(M)N)

010

"JI_

(NOMilr

RD7 RDS RD3 RD1

PIN/PACKAGE CONFIGURATION

S1883 BLOCK DIAGRAM

(Available in Pkgs. 3M, IT -see Sec. 1)
FEATURES

•
•

•
•
•

•

12.5 K Baud Data Rates
5-8 Bit Word Length
Parity Generation/Checking Odd, Even, None
Framing and Overflow Error Detection

•
•
•

Start and Stop Bits Generated and Detected

•

Tri-State Outputs

1, 1.5, or 2 Stop Bits

FUNCTIONAL DESCRIPTION

The S 1883 Universal Asynchronous Receiver Transmitter
(UART) is a single chip MOS/LSI device that totally replaces
the asynchronous parallel to serial and serial to parallel
conversion logic required to interface a word parallel controller or data terminal to a bit serial communication network.
For asynchronous data transmission with a non-contiguous
data bit stream, the UART automatically inserts a START bit

3.170

Double Buffered Input/Output
Independent Transmit/Receive Rates

Interchangeable with TMS60 11, COM20 17,
TR1602, AY-5-1013

preceding each character and under program control 1, 1.5, or
2 stop bits at the end of each character. .To detect incoming
characters in a noisy environment the UART employs a
START bit detection network and allows errorless recovery of
data with up to 42% distortion.
The UART will transmit or receive data characters of 5, 6, 7,
or 8 bit length. Options allow the generation and checking of
odd, even parity or no parity. The odd or even parity bit is
automatically added to the character length for transmission.

Sll§O
UNIVERSAL SYNCHRONOUS
RECEIVER/TRANSMITTER
(USRT)

GND Vee

GND

39
38
31
36
35

VCC
NPB
POE

CS
TOS 138::.;.1t--_ _ _ _-----,

TSO
FCT
SCR
TBMT
RPE
ROR
RDA

...--++-+- IFS

151
(39)

NOB,
(40)

NDB2

FiR

141
NPB

(3)

1361

RESET
DO
Dl
D2
D3
D4
D5

TSO

(13)
(37)

10
11

S2350

12
13
14
15
16
17
18
19
20

34
33
32
31
30
29
28
27
26
25
24
23
22
21

NDB2
NDBl
TDS
RCP
TCP
RDE
SWE
RDO
RDl
RD2
RD3
RD4
RD5
RD6
RD7
RSI
TFS
RSS
D7
D6

TBMT(91

RSS

171
181
RPE (10/
RDR (11)
ADA (12)

(14)

PIN/PACKAGE CONFIG URA TION

BLOCK DIAGRAM
FEATURES
•

500 KHz Data Rates

•

Internal Sync Detection

•

Fill Character Register

•

Double Buffered Input/Output

•

Bus Oriented Outputs

•
•
•
•
•

FUNCTIONAL DESCRIPTION
The S2350 Universal Synchronous Receiver Transmitter
(USRT) is a single chip MOS/LSI device that totally replaces
the serial to parallel and parallel to serial conversion logic
required to interface a word parallel controller or data terminal
to a bit-serial, synchronous communication network.
The USRT consists of separate receiver and transmitter
sections with independent clocks, data lines and status.
Common with the transmitter and receiver are word length and
parity mode. Data is transmitted and received in a NRZ format
at a rate equal to the respective input clock frequency.

5-8 Bit Characters
Odd/Even or No Parjty
Error Status Flags
Single Power Supply (+5v)
Input/Output TTL Compatible

Data messages are transmitted as a contiguous character
stream, bit synchronous with respect to a clock and character
synchronous with respect to framing or "sync" characters
initializing each message. The USRT receiver compares the
contents of the internal Receiver Sync Register with the incoming data stream in a bit transparent mode. When a compare
is made, the receiver becomes character synchronous formatting a 5,6,7, or 8 bit character for output each character
time. The receiver has an output buffer register allowing a full
character time to transfer the data out. The receiver status
outputs indicate received data available (RDA), receiver overrun (ROR), receive parity error (RPE) and sync character

3.171

AMI MICROCOMPUTER SYSTEMS
MICROCOMPUTER DEVELOPMENT CENTER

AMI Microcomputer
Development Center
An intelligent stand-alone software debugging station,
serving completely the combined needs of the design
engineer and the programmer. It consists of a 86800
based CRTlkeyboard microcomputer terminal, a dual
drive floppy disk memory, and an optional hard copy
printer.

A program in development (or in operation) can be
viewed on the CRT and edited on the keyboard. Program files can be assembled and stored in the floppy
disk memory, under control of the disk memory
operating system software. The modular bus oriented
card cage in the CRT terminal provides versatile
facilities for developing and testing 6800 hardware.

CRT/Keyboard Terminal

Floppy Disk Memory

Capability for generating 256 unique ASCII input
characters

D 12-inch diagonal CRT display - 25 lines of 80
characters
D

D IBM 3740 data format compatible
D

Data storage capacity of 256,256 bytes per
diskette

Fully supported by FDOS-II Disk Operating and
File Management System software

16K bytes of user available RAM, expandable to
48K

D Full cursor and editing controls

Optional Matrix Printer

Special function controls

D 132 column

Peripheral interconnects

Dot matrix, impact printing

120 or 180 characters per second

Logic Analyzer
D

General-purpose logic analyzer

52000 Support

Plugs into MDC-I00

82000 Designers can use the DEV -2000 Development
Board to provide a direct link between the MDC and
the user's prototype. As stand-alone systems, the
82000 designer can use the capabilities of either the
low-cost 8E8-2000 hardware emulator - which is a
pin-for-pin substitute for an 82000 microcomputer chip
and contains its own EPROM memory - or the
TE8-82000 functional go/no-go tester.

D Trace memory hold 1024 steps
D

All patterns 40 channels wide

Two separate event qualifiers

Data-dependent clock
Outbound trigger

3.172

M DC Hardware Capabilities
The AMI MDC is a multifunction development center
that single-handedly satisfies your requirements for
software development, hardware development, and
prototype checkout. The MDC can also double as a
stand-alone communications terminal, a general purpose data processing system, or as an incoming parts
tester.

Software Development - write, debug and operate
S6800 and S2000 programs on the CRT terminal, using its internal RAM and the dual drive floppy disk for
storage. The MDC comes with a full complement of
support software, including the FDOS-II Disk
Operating and File Management System, a Text
Editor, an Assembler, Debugger, Trace, Telecommunications and Utilities.
Hardware Development - breadboard such cicruitry
as interfaces or memories right on the MDC wire wrap
prototyping board and plug into the CRT terminal card
cage to operate with the MDC's S6800-based central

processor in solving development problems. Use the
control panel type functions of the CRT terminal for
single step, stop-on-address, display, alter, and other
similar program operations. The bus oriented card
cage, position interchangeable plug-in card modules,
and an extender card provide the flexibility to make
hardware development easy. There is also a complete
keyboard control led PROM programmer within the
CRT terminal.

Prototype Checkout - with the advantages of a realtime test environment, rapid test program retrieval,
single or multiple step execution, and hardware as well
as software breakpoints, the checkout of prototype
S2000and S6800 circuitry is easy and efficient.
Stand-alone Communications Terminal - the CRT terminal has both RS-232 and current loop interfaces, supported by telecommunications firmware, for operation
as a general purpose stand-alone intelligent terminal.

M DC Software Capabilities
The AMI MDC offers total facilities for rapidly
developing applications and systems software. The entire MDC software system is at the user's instant
disposal - a few simple keystrokes are needed to instantly access and execute any program. The FDOS-II
disk based operating system provides complete system
resource control to the programmer.

FDOS-II Disk Operating and File Management
System - contains a resident module for bootstrapping the floppy disk memory and for disk I/O handling.
It also contains an executive that performs all of the
disk memory command line interpretations, file
management and operational functions of the dual disk
system. In addition, there are utility I/O and EPROM
programming routines in FDOS-II.
.
The Text Editor - program provides the means for
rapidly creating, examining and modifying stored files.
The total capability of MDC's Text Editor exceeds that
of many large minicomputer systems, and includes
such features as storing searches and string substitutions.
The Symbolic Assembler - translates assembler
language statements into executable machine
language code. In conjunction with FDOS-II Operating
and File Management Systems, assembling has been
reduced to a series of simple operator keystrokes.
Results of the assembly, automatically stored on disk,
are immediately available for reference or execution.

MDC's Extensive Debug Program - effectively
automates the functions of a computer control panel.
Given control by simply pressing the DEBUG key or
via program traps, Debug immediately responds with
the display of machine and program status. Addition
functions include:
Register/data display and modification
Instruction/subroutine step
User definable debug macros
Snapshot debug data of a running program
Breakpoints (stop-on-address compare)
Comment and header line displays

MDC's Trace Package - gives Debug the ability to
display a trace of machine register contents, instruction mnemonics and operands before execution of any
instruction or subroutine in the user's program.
Microprocessor debugging has never been made
easier.

MDC's Test Programs - are a set of self-test and
diagnostics which verify that the hardware associated
with the MDC is operating correctly. The programs
are also helpful in isolating malfunctioning components. The program for testing the basic hardware is
resident in EPROM and is activated by the keyboard
TEST key.

3.173

AMI~

EVK SERIES
MICROCOMPUTER
BOARDS/KITS

Features

General Description

Expandable to 4K Bytes ROM

Expandable to 2K Bytes EPROM

Expandble to lK Bytes RAM

EPROM Programming for S6834

The EVK Series Board is a single PCB, hardware/
software system that can be used as a general purpose
microcomputer. It allows system development using a
functionally compatible system and reduced development time. With this system the basic 6800 family of
parts can also be evaluated. The 10-l/2"x12" card has
two edge connectors, one for the MPU Bus and one for
the I/O. The EVK 300 is a fully assembled and tested
board, while the EVK 200, EVK 100 and EVK 99 are in
kit form. All kits are fully expandable to EVK 300
capabilities.

Expandable to 3 PIA's = 58 I/O Lines

TTY Current Loop or RS232 Interface

ROM Subroutine Program Library

D Selectable DMA Mode

Series Block Diagram

Address Assignment Map
1K
1K

, . . - - - - - - - - - - , ffff
----oRAM---fCOO

liD

I - - - - - - - - - i f800

ROM

I - - - - - - - - - l E800
2K

EPROM

f----------1

EOOO

·RAM

512

3.174

0000

EVK Series

System Specifications

All of the S6800 microprocessor lines are available at
the bus edge connector and are buffered to allow 40mA
of drive capacity for expanding the development
system. The standard system clock is adjustable from
300kHz to 1MHz by using the potentiometers on the
board. An optional 1MHz crystal may be selected to
control the accuracy for those applications requiring
critical timings.
An on-board interval timer gives 1ms and lOOfts timing
marks for general use and for EPROM programming.
Three types of DMA operation are possible using the
EVK Board: Halt Processor, Cycle Steal or Multiplexing.
Memory

Memory and I/O addresses are assigned to the upper
8K bytes of the available memory space. (See memory
map for address assignments.) This gives the system
developer the flexibility to use the remaining 56K
bytes as he wishes. All of the memory and I/O on the
board may be disabled externally by an edge connector
line called MEMORY DISABLE, leaving the MPU free
to operate totally in an external memory.
The S6830 ROMs contain the Prototype Operating
Library (PROTO) and a ROM Subroutine Library (Rs)3.
An optional Assembler/Disassembler (M/AD) S6831
ROM is available to operate with PROTO. The 2K of
EPROM locations may also be used for program
verification.
The RAM is assigned to the upper 1K of available
memory space. The PROTO and (RS)3 programs require about 256 bytes of this RAM so the rest is
available for general programming. With all restart
vectors automatically assigned to the upper memory
addresses, restart vectoring is forced from a set of 16
switches. This allows the restart address to be vectored to any memory location.

The RAM has further been divided into two 512 byte
sections such that the upper 512 bytes remain fixed in
the assigned address block and the lower 512 bytes are
moveable through a switch selection option. 512 bytes
of RAM are relocatable to the lowest address space to
take advantage of the S6800's direct addressing mode.
This is only recommended if no external memory is
added. When adding external memory, it is advisable
to use the RAM in the upper address space and the external memory as the low addresses.
110

An S6850 ACIA is used to provide a 20m A current loop
interface to a TTY or RS232 terminal. A 20mA current
loop interface and an EIA RS232 interface are both
available on the board. A bit rate generator allows
operation using any of- the standard communication
frequencies (see table) so a large variety of terminal
types can be used.
Three S6820 PI As allow up to 58 I/O lines, giving flexibility in I/O through the parallel interfaces.
EPROM Programming

Unique to the AMI EVK Board is the ability to program S6834 EPROMs (512 x 8) on the board. The programming software can program an EPROM from any
memory location, RAM, ROM or EPROM. It can verify
a word and, if desired, change a single bit in the
EPROM, provided that the change is from LOW to
HIGH.
Software

The EVK Board Software is comprised of a TTY
Operating Program (PROTO) and is supported by a
ROM Subroutine Library (RS)3.

EVK Capabilities
ROM

RAM

EVK 99

2K
bytes

512
bytes

EVK lOa

2K
bytes

512
bytes

EVK 200

4K
bytes

IK
bytes

512
bytes

EVK 300

4K
bytes

IK
bytes

2K
bytes

EPROM

PIA

TTY
CURR
LOOP

ROM
SUB-ROUTINE
PROG. LIBRARY

TOTALLY
BUFFERED
MPU LINES

SGL
+5V
P.S.

RESTART
ADDRESS
SELECTION

SELECTABLE
DMA MODE

INTERVAL
TIMER

'AMI 6800 Tiny BASIC
-A high. level interpretive language derived from the standard Dartmouth BASIC. Furnisht>d to EVK 300 users at no chargt' upon suhmittal of warranty registration.

3.175

TINY
BASIC

eProoffrom

AMIs S2000 Family Compared to Other Mqjor Low-End Single-Chip Microcomputers

S2000

AIMII
INTEL

MOTOROLA
NATIONAL

S2150

S2400

YES

4.5 I 8 BIT

YES 1 4.5 I 8 BIT

lK 1 64x8 I NO 1 10.0' -

8022

2K 1 64x8 1 NO 1 10.0

I - I - I - I
I 45 I 8 I YES I
I 45 I 8 I YES I

YES

, -

YES 1 -

18BIT

YES 1 65+ 1 YES 1 YES 1 YES 1 YES

YES 1 -

1 881T

YES 1 65+

1 8 BIT 1 40

YES
YES

I - I 501601
I YES I ~tJ~ I
I YES I ~tJ~ I

I
I

YES 12200AI

1 YES 1 5

1 512 1 YES

I 13 I 24 I YES I YES I 2400AI

I 512

13
13

I
I

8
24

I
I

YES
YES

I
I

YES

I 2150AI

MK3870

2K 1 64x8 I NO 1 2.0 1 -

1 -

1 8 BIT 1 0

MK3876

2K I

I NO 1 2.0 1 -

1 -

1 8 BIT 1 0

01321 -IYESI - I -

4K 1128x81 NO

2.0

'8BIT

6805

1.lK 1 64x8 1 NO

2.0

, 8BIT

512

COP 420

lK 1 64x4 1 NO

MM76E
MM77

32x4

cOP4l0L

NO 1 16.0
4.0

2K 1128x41 NO 1 4.0 • -

, -

TMS1270

15.0

TMS1300

2K 1128x41 NO

15.0

YES' -

Microcomputer Development Cellter (MOC)

AMI's MDC is a fuUy «juipped, disk-based microcomputer
development facility, complete with FDOS-JI FIoppy.Disk~
Operating and File Management System. Controlled from Its

k~=~n:tcie~t~~~~i~~I~n~:!I~~Fo~Ot:=t~

~~:E:~f~i~e=;:O&;~~e::tt~~~i~~~~~g

SES-2000EmulatorBoard
The SES-2000!2ISO Emulator Board is a pin-ror-pin subslitute
for an S2000 microcomputer chip which uses conventional
UV-erasable PROMs for program storage. TIle SES-2000 thus
provides the equLvaIent of an S2000 micllX:omputerwith

~~~J2~fo~rap%~~~sog:e~n~~~i~~~gf~~~%U~i~~~~~'
rescentdisplays
Customer Assistance
AMI's S2000 Applicalions Ellgineering staff are avaiiable for
consultation regarding all aspects of S2000 usage. AMI'S slaff
isaIsoavail!lbletodiscussa~y~peciaImodil'icalionstoihe

S2000forhlghvolumeapphcalions

YES 1 YES 1 YES

YES 1 YES 1 YES 1 YES

YES'

I 512 I NO I TBA

YES I YES I YES'

256

PLA

256

PLA

512

YES

18
19

Cross·assemblers, edilorand simulator/debug softv.are are
also available on a major timesharing service

1 YES 1 YES 1 YES ' -

512 1 YES

YES

15.0

TheS2000single-chipmicrocomputerisfullysupportedbya
proven array of development aids. This inc1udes AMI's MicrocompUier Development Center, development software, SES2000 Emulator Board, MOC-I40 Logic Analyzer and customer
assistance by AMI Applications Engineering staff

1 YES 1 60+ 1 -

NO
CRT
NO
CRT
NO
CRT
NO
CRT

YES

MDC-I40 Logic Analyzer
llleMDC·I40LogicAnalyzerisanadvanceddebugloo!

1 YES 1 YES 1 YES ' -

YES 1 YES 1 YES

YES

PLA

, YES

YES

1 YES 1 YES 1 YES 1 YES

YES 1 YES 1 YES

1 YES 1 60+ 1 -

YES

1 YES'

YES I YES I YES 1 YES

~~ne~~~lac!::~~(~~)~.iF~~~~~~~~~icrocompul= ~.~

YES

12.5

~~~~g;.Assembler, Loader, and a sophisticated InsllUclion

256

2K 1128x4 1 NO

Development Software
MDC's standard software includes a comprehensive TellOt Editor
and PROM Programmer package that support S2000 softwarc
developmelll.llladdition,speciaIizedS2000sofrwarcmcludesa

YES

YES I YES I YES 1 YES

128

lK 1 64x4 1 NO

S2000FAMILY
DESIGN SUPPORT

59 I YES

I
I
I

YES' -

MM78

59 I YES

YES

TMS 1000

1 64x4

YES

49 I YES

I
I
I

YES 1 60+

12.5

I -

YES

RAM

12.5

320

YES

I 96x4 I

1 -11

YES

lK 1 48x4 1 NO

16 1 -

12.5

YES 1 5

640 1 48x4 1 NO

1.3K

YES

1321-IYESI-I-I-ll

MK3872

MM75

TEXAS
INSTRUMENTS

I 128x41
I 128x41

8021

COP 440

ROCKWELL

1.5K 1 80x4 1 YES 1 4.5 I

S2200

192 1 YES

384 1 YES

YES 1 YES 1 YES
YES 1 YES

YES

YES 1 YES 1 YES
YES 1 YES 1 YES
'PtfIER I YES
, PAPER YES
TAPE
'PtfIER 1 YES

~II

American Microsystems, Inc.
3800 Homestead Road
Santa Clara, California 95051
(408) 246·0330
TWX 910·338·0018

, -

4
52000 Family

4.2

October 1978

52000
SINGLE·CHIP
MICROCOMPUTER
FAMILY

4.3

82000 FAMILY
52000 5ingle·Chip Microcomputer Family

52000A/2150A Vacuum Fluorescent Display

AMI's 82000 family of single-chip microcomputers offers a wide range of capability to the user seeking flexible, adaptable system(s) at low cost. The 82000 family
provides the ideal solution to appliance and industrial!
process-control applications. With versatile keyboardoriented inputs, and outputs which can drive either
LED or fluorescent displays directly, the 82000 family is
designed specifically to minimize system parts count
and cost.

The 82000A/2150A are identical to the 82000/2150 but
provide high voltage fluorescent display capability. The
output buffer drive (VDD) is changed to a vacuum
fluorescent drive (VFD) and typically tied to 32 volts.
The Do through D7 and Ao through A4 are changed from
LED drivers (nominal 5 volts) to vacuum fluorescent
drivers (nominal 26 volts).

Table I. 82000 Family Features

The 82200/2400 provide a quantum jump in chip
features beyond the 82000. In addition to all the
features the 82000 offers, the 82200 gives the added
flexibility of interrupts and the sophistication of an onchip AID or D/A converter capable of multiplexing 8
channels of analog data making it suitable for a wide
range of applications.

ROM (x8)
RAM (x4)
Interrupts
AID CONV (8 Channel)
Cou nter ITimer
Max Subroutine Levels
Instructions
Cycle Time (p.s)
High Voltage
(Fluorescent Display
Drive Version)

S2000

S2150

S2200

S2400

1K
64

1.5K
80

4K
128
3
8-Bit
8-Bit
5
59
4.5
S2400A

+50/+60
3
51
4.5

2K
128
3
8-Bit
8-Bit
5
59
4.5

S2000A

S2150A

S2200A

The 82000 family provides the advantages of computer
architecture to low cost, minimum-parts-count display/
keyboard oriented control systems.
52000/2150 Features

52200/2400 Features

2048 x 8 Program ROM On Chip Expandable
to 8192 x 8 - S2200

4096 x 8 Program ROM On-Chip; Externally
Expandable to 8192 x 8 - S2400

o
o
o

128 x 4 Scratchpad RAM On Chip
RAM Save Power Down Mode (Mask Option I
Two-Level Maskable Priority Interrupt
System with Provision for Software Interrupt

Programmable 8-Bit TimerlEvent Counter On
Chip

1024 x 8 Program ROM On-Chip; Externally
Expandable to 8192 x 8 - S2000

13 Outputs, 9 Inputs, Plus 8 Bi-Directional
Three-State Lines

1536 x 8 Program ROM On-Chip; Externally
Expandable to 8192 x 8 - S2150

Touch Control™ Capacitive Switch Interface

64 x 4 Scratchpad RAM On Chip - S2000

80 x 4 Scratchpad RAM On-Chip - S2150

13 Outputs and Inputs, Plus 8 Bi·Directional
Three-State Lines

Touch ControlTM Capacitive Touchplate Interface

Seconds Timer for Both 60Hz and 50Hz Lines

7-Segment Decoder and LED Display Drivers
On Chip

o
o
o
o
o
o
o
o
o
o
o

Single 9.0 Volt Supply

Fast 4.5p.s Execution Cycle

Three-Level Subroutine Stack

TTL-Compatible Outputs

Reset, Test, and Single Step Modes

Access to All Internal Registers and Memory
for Debug and Test

Crystal Input for Accurate Clocking - S2150

Low Power RAM Retention, 20J,tAlBit Typ @
4V - 82150

o
o
o
o
o
o
4.4

7-Segment Display Decoders and LED Drivers
TTL-Compatible Outputs
Single + 9V Power Supply
4.5p.s Cycle Time
59 Instructions - 52 Single Byte and Single Cycle
3-Level Subroutine Stack
2-Level Interrupt Stack
Built-In Production Test Mode
Single-Step Capability
Power-Fail Detect, RAM Keep-Alive and
Power-On Reset Circuitry
8-Bit AID Converter (Up to 8 Channels I
DIA Converter Capability (Mask Optionl

Up to 256 General Purpose Flags
6 Special Flags
Table Look-Up Capability
S2200A/2400A Vacuum Fluorescent Display
Capability

52000 FAMILY
52000 Family

82200A
82400
82400A
82000 I 82000A I 82150 I 82150A I 82200
Product
Characteristics
ROM (Bytes)
1K
1K
2K
4K
1.5K
1.5K
2K
4K
128
64
64
128
128
128
80
80
RAM (Nibbles)
AID Converter (8-Bit)
YES
YES
YES
YES
Timer
50/60Hz 50/60Hz 50/60Hz 50/60Hz PROG 8BIT PROG 8BIT PROG 8BIT PROG 8BIT
Interrupts
3
3
3
3
Power Fail Detect
YES
YES
YES
YES
High Voltage Outputs
YES
YES
YES
YES
Crystal Clock Option
YES
YES
YES
YES
YES
YES
YES
YES
TouchControl Inputs
YES
YES
YES
YES
YES
YES
Levels of Subroutine
3
3
3
5
5
5
5
3
# of Flags
262
262
262
2
2
2
2
262
Power-Down
YES
YES
YES
YES
YES
YES
RAM Option
YES
YES
D/A Converter Option
YES
YES
Zero - Crossing
YES
YES
YES
YES
YES
YES
YES
YES
Detect
Cycle Time (jlsec)
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
59
Instructions - Total
51
51
51
51
59
59
59
Single Cycle & Byte
52
52
52
49
49
52
49
49
Development 8upport
Microcomputer
Development Center
Logic Analyzer
Hardware Emulator

YES

YES
#2150

YES
#2150A

YES
YES
#2150

YES
YES
#2150A

YES
YES
#2400

YES
YES
#2400A

YES
YES
#2400

YES
YES
#2400A

52000 Family Support
The S2000 single-chip microcomputer family, unlike many
microprocessors, does not leave the designer or industrial
OEM unsupported. The S2000 Family features a proven array
of development aids:
Microcomputer Development Center IMDCI - AMI's MDC is
a fully equipped, dual-floppy disk-based microcomputer
development facility, complete with FDOS-II Floppy-DiskOperating and File Management System. Controlled from its
CRT terminal, MDC provides instant access to program and
data files resident on removable diskettes.
Development Software - The MDC's software includes selfdiagnostics and a comprehensive Text Editor and PROM programmer package that support S2000 software development.
In addition, S2000 software includes a MACRO Assembler,
Loader, and Instruction Simulator.

- Captures 1024 Events of 40 Parallel Inputs
- Captures Data Under Control of Programmable Start on
Data Content
-Delay of - 1024 to + 64K Clock Periods
- Setup and Display of Captured Data Under Control of MDC
Software
-Display Format is User-Definable; Captured Data Can Be
Displayed in a Mix of Hex, Octal, Binary, ASCII and Special
Formats for Support of S6800, S6820, S2000, 8080, etc.
- Four Clock Sources
-Input Voltage Range = - 15 to + 15 volts
- Adjustable Input Thresholds
- Data-Dependent Output for Triggering an Oscilloscope

Cross-Assemblers editor and simulator debug - Available on
a major timesharing service.

SES-2150IAI/SES-2400IAI - The SES-2150/2400 Emulator
boards are pin-for-pin substitutes for S2000 microcomputer
family chips. The Emulator Boards use conventional UV
erasable PROMs for program storage.
In addition, a specialized module is used to provide emulation
of the S2150A/S2400A high voltage vacuum fluorescent
display drivers.

Logic Analylzer - The MDC-140 Logic Analyzer is an advanced debug tool connected as a peripheral device of the
AMI Microcomputer Development Center (MDC). Features
include:

Customer Assistance - AMI's 82000 Family Applications
Engineering Staff is readily available for consultation regarding any aspects of 82000 Family usage. The AMI staff is also
available to discuss any special modifications to the 82000 for
high volume applications.

4.5

52000 FAMILY
52000 Family Instruction Set Summary

The S2000 and S2150 contain 51 instructions, all single
byte, with 49 that are single cycle. The S2200 and S2400
contain 59 instructions, of which 52 are single cycle and
single byte.

Nearly all S2000/2150 instructions are common to the
entire family, which allows the programmer to develop
software expertise and easily move up the S2000 product line.

82000/2150

82200/2400

LAIX
LAB
LAE
XAB
XABU
XAE
LBE Y
LBZ Y
LBF Y
LBEP Y

LAIX
LAB
LAE
XAB
XABU
XAE
LBE Y
LBZ Y

SRB
RRB
LMDI X +
RAR
XAK
LANG
LNMA
MOD
RBIN

X - ACC, O::s; X ::s;15; (In S2000/2150 Select I and K Inputs also)
BL-ACC
E-ACC
BL-ACC
BU - ACC, (IN S2150, BITS 2, 1, AND 0; IN OTHERS, BITS 1 AND 0 ONLY)
ACC-E
Y -BU, E-BL, O::s; Y::s; 3
Y -BU, O-BL, 0::s;Y::s;3
Y-BU, 15-BL, 0::s;Y::s;3
Y -BU, E + 1-BL, 0::s;Y::s;3
1-BA
O-BA
X(6)-BA, X(5-4)-BU, X(3-0)-BL
ACC(I)-ACC(I -1), ACC (O)-CARRY, CARRY -ACC(3)
KSR-ACC
ACC-AR (3 - 0), RAM-AR(7 - 4)
ACC-NR(3- 0), RAM-NR (7 - 4), THEN NR-BIN
ACC - MOD(3 - 0), RAM - MOD(7 - 4)
BIN(3 - O)-ACC; BIN(7 - 4)-RAM

RAM Instructions

82000/2150

LAM y*
XC y*
XCI y*

82200/2400
LAM y*
XC y*
XCI y*

XCDY*

STM Z
RSM Z

STM Z
RSM Z
LMA
STMI Z +
RSMI Z+

RAM-ACC, BU$Y-BU
RAM-ACC, BU$Y-BU
ACC-RAM, BL + 1-BL, BU $ Y -BU SKIP IF BL = 0 (AFTER
INCREMENT)
ACC - RAM, BL - 1- BL, BU $ Y - BU SKIP IF BL = 0 (BEFORE
DECREMENT)
I-RAM BIT Z, 0::s;Z~3
O-RAM BIT Z, 0::s;Z::s;3
ACC-RAM
1- RAM BIT Z, O::s; Z ::s; 255, (RAM BANK 1)
O-RAM BIT Z, 0::s;Z::s;255, (RAM BANK 1)

Input/Output Instructions

82000/2150

82200/2400

INP
OUT
DISN

IND
OUT
DISN

DISB
MVS
PSH
PSL
EUR

DISB
MVS
PSH
PSL
INK

D3-DO-ACC, D7-D4-RAM
ACC-D3-DO, RAM-D7-D4 (NOT LATCHED)
ACC-SEGMENT DECODER-DISPLAY LATCH-D6-DO,
CARRY - DISPLA Y LATCH - D7
ACC-DISPLAY LATCH-D3-DO, RAM-DISPLAY LATCH-D7-D4
A-LINE MASTER STROBE LATCH-A LINES
PRESET HIGH [BL]-MASTER STROBE LATCH
PRESET LOW [BL]-MASTER STROBE LATCH
(EUROPEAN) SET 50/60Hz AND DISPLAY LATCH POLARITY
K3-KO-ACC, K7-K4-RAM

+ 8 bits in'the second byte of an instructIOn.
*Assembled code contains complement of those arguments (the assembler does it automatically).

4.6

82000 FAMILY
52000/52150 and 52200/52400 Instruction 5et 5ummary

Program Control Instructions

S2000/2150

PP X*

S2200/2400
PP X*

JMP X

JMS X

RT
RTS
NOP

RT
RTS
NOP
RTI
TLU

IF PREVIOUS INSTRUCTION = PP, X - PPR (0 $ X $15)
IF PREVIOUS INSTRUCTION = PP, X-PBR (O$X$7)
JUMP TO LOCATION X, X - LR (0 $ X $ 15)
EXCEPT IF PREVIOUS INSTRUCTION = PP
JUMP TO SUBROUTINE AT X, LR + l-L STACK, PR-P STACK,
X-LR, 15-PR EXCEPT IF PREVIOUS INSTRUCTION = PP
L STACK-LR, P STACK-PR
L STACK-LR, P STACK-PR, SKIP INSTR.
NO OPERATION
RETURN FROM INTERRUPT, RESTORE REGISTERS
IF PREVIOUS INSTRUCTION WAS A PP, DO A TABLE LOOK-UP
SEQUENCE:
pC+ I-STACK
RAM-PC(3 - 0), ACC-PC(7 - 4), PPR(3 - 2)-PC(9 - 8)
ROM(7 - 4)- RAM, ROM(3 - 0)- ACC
STACK-PC.
IF PREVIOUS INSTRUCTION WAS NOT A PP, DO AN INDEXED
SUBROUTINE CALL:
PC+ I-STACK
RAM-PC(3 - 0), ACC-PC(7 - 4)

5kip Instructions (5kip 1 Non·PP Instruction) (RAM = Memory at BU,BL)

S2000/2150

S2200/2400

SZC
SZM Z
SZK
SBE
SAM
SZI
SOS

SZC
SZM Z
SZK
SBE
SAM

TFI
TF2
SZMI Z +
SKFL X+

SKIP IF CARRY = 0
SKIP IF RAM BIT Z = 0, O$Z $3
SKIP IF K BIT(S) = 0, (BIT(S) IN LAST LAD
SKIP IF BL= E
SKIP IF ACC = RAM
SKIP IF I BIT(S) = 0, (BIT(S) IN LAST LAD
SKIP IF SF = I, O-SF. (SF = 'SECONDS' FLAG OUTPUT OF +50/+60
COUNTER)
SKIP IF FLAG 1 = 1
SKIP IF FLAG 2 = 1
SKIP IF RAM BIT = 0, (IN RAM BANK 1) 0 $ Z $ 255
SKIP IF FLAG = 1

Arithmetic and Logical Instructions

S2000/2150

S2200/2400

ADCS
ADIS X
ADD
AND
XOR
STC
RSC
CMA
SFI
RFI
SF2
RF2

ADCS
ADISX
ADD
AND
XOR
STC
RSC
CMA

SFLG X +
RFLG X +

RAM + ACC + CARRY -ACC + C, SKIP IF SUM $15
X + ACC-ACC, SKIP IF SUM $15, CARRY UNALTERED
ACC + RAM-ACC, CARRY UNALTERED
ACC & RAM-ACC
ACC $ RAM-ACC
I-CARRY
O-CARRY
15 - ACC-ACC (LOGICAL l's COMPLEMENT ACC)
I-FLAG 1
O-FLAG 1
I-FLAG 2
O-FLAG 2
I-FLAG X
O-FLAG X

+ 8 bits in the second byte of an instruction.
code contains complement of those arguments (assembler does it for you).

*Assembled

4.7

52000 FAMILY

AMI 52000/2150 Detailed Block Diagram
TOUCH

KEY

CONTROL SWITCH

ADDRESS/CONTROL LINES
AD ... 11 AND AI2/RAM POWER

DATA/SEGMENT LINES
13·STATE)

MASTER
LATCH
13

16
INTERNAL
CONTROLS'r---------,

VGG - LOGIC
VFD or VDD = OUTPUT BUFFERS
Vss - GROUND
'S2150-11 BITS
S2000 -10 BITS

52000/52150 Pin Configuration
(GRO) VSS

03
04
05

O2
01
DO
ROMS

07
SYNC

EXT
(P.C. MSB) A12
A11
A10
A9

RUN
KS
K4
K2

Kl
VGG (+9V)
IS AND TIMER

VoolVFO
A7
A6

14
12
11
KREF TOUCH CONTROL

A5
A4

A3
A2
Al
(P.C. LSB) AO

CLK*

POR
STATUS*

*May be used for crystal input on S2150/2150A

4.8

Kl.2.4.8

11.2.4.B

52000 FAMILY
Pin Descriptions -

52000/2150

PIN NO.

NAME

Vss

Most negative power-supply input. Typically grounded.

VGG

Most positive power-supply input. Typically + 9V.

VDD (S2000)
VFD (S2000A)

Power supply input for all output buffers. Typically tied to VGG or to a + 5V supply.
Power supply input for HV drive. Typically + 32V

4 - 2,
40 - 36

DO - D7

D Lines for input and output. Output during instructions OUT, DISN, DISB. Input
during INP. Float at reset time or after an MVS instruction; or if RUN pin is low;
or after a PSL with BL = 14. Display Latch outputs (DISN, DISB) can be inverted
using EUR.

20 - 13
11 - 7

AO - A12

ROMS

EXT

SYNC

DESCRIPTION

A Lines for addressing and control. Changed by MVS as set up by PSH/PSL.
When external program ROM is used, these lines output the contents of the
Program Counter during the first half of each instruction cycle.
ROM source control. Tied to a logic 1 or 0 to indicate internal ROM only, or internal plus external. Tied to SYNC to override Bank 0 with an external program, and
to inverted SYNC to verify internal ROM contents.
Active-low strobe output for D Lines. Generated by an OUT instruction during
time T7.*
Synchronization output for external devices or for external ROM control.
Continuous square wave, low in T1 and T3, high in T5 and T7.* fCLK .;- fsyNc
for S2000, 8 for S2150.

RUN

Run/Wait control for prototyping and single-step testing. Logic 1 to run, logic 0 to
wait with D Lines floating.

POR

Power-On-Reset. Needs only an external capacitor, typically .05 microfarad. A pullup to VGG (15jLA nominal) is provided internally.

CLK

On-chip oscillator connection. Runs at - 850kHz when connected to Vss through
47pf and to VGG through 30kO on the S2000. Crystal control possible; consult AMI.

STATUS

Monitors internal status for special designs. Logic 1 vs. logic 0 indicates: (during
T1)* D Lines flo.lting or not floating; (T3) BL equal or not equal to 13 for mUltiplex
control; (T5) Carry is 1 or 0; (T7) Next instruction will or won't be skipped. On the
S2150 a mask option allows use as a crystal oscillator pin.

KREF

K Lines voltage comparator reference input. Typically + 3.0V, supplied by an
external resistor divider.

30 - 33

K1, K2
K4, K8

K Lines, tested by SZK instruction. Any combination of these lines, selected by
the last executed LAI instruction, are gated into the signal input of the voltage
comparator. Unselected K Lines are discharged to Vss, at 160jLA typical.

25 - 28

11,12,
14, 18

I Lines, with internal pull-ups of lOOjLA nominal. Any combination of these lines,
selected by the last executed LAI instruction (S2000, S2150), are gated into a
common node tested by the SZI instruction. 18 also clocks a seconds timer whose
output is tested using SOS.

*Tl is the first quarter-cycle following the falling edge of the SYNC output, T3 is the second, T5 is the third, and T7 is the fourth.

4.9

52000 FAMILY
52000/2150

Absolute Maximum Ratings (All voltages measured with respect to VSS)
Storage Temperature ................................................................. - 55°C to + 125°C
Operating Temperature .................................................................... O°C to + 70°C
Operating Temperature (special request) ................................................. - 40°C to + 85°C
Maximum Positive Voltage ........................................................................ + 18V
Maximum Negative Voltage ...................................................................... - 0.3V
Maximum Output Currents ....................................................... (See "Conditions" below)
IDD Supply Current (depends on output loads) ..................................................... + 75mA
Total A verage Power Dissipation .............................................................. + 700m W

52000/2150

Electrical Characteristics
(Vss = OV, VGG = + 7.5V to + 10.0V, VDD = 5V*, TA = O°C to + 70°C, fSYNC = 125kHz to 225kHz)

Parameter
INPUTS

INPUTS

OUTPUTS

Kl thru K8
Low Level
High Level

Min.

Typ.

Max.

Units

Conditions
2.8 < KREF < 3.2V

0
KREF+ 0.5

KREF- 0.5
VGG

V
V
(Note 1)

11 thru 18, POR
Schmitt-trigger
Low Level
High Level

0
5.3

1.7
VGG

V
V

ROMs, RUN
Low Level
High Level

0
3.5

0.8
VGG

Do thru D7
Low Level
High Level - Program
High Level - Data

0
5.0
3.5

0.8
VGG
VGG

V
V
V

Ao thru A3
High Level
Low Level

3.5
0

*VDD
0.8

V
V

1= - 5mA**
1= + 25mA**

A4 thru A12
EXT, SYNC, & S
High Level
Low Level

3.5
0

*VDD
0.6

V
V

1= -5mA**
1= + 5mA**

Do thru D7
High Level
Low Level

3.5
0

*VDD
1.0

V
V

1= - 5mA**
1= + 12mA**

IGG

Supply Current

~RAM

RAM "Keep Alive"

20
30

rnA
/LA/Bit
/LA/Bit

NOTE 1: There is an internal pull-up of lOOJlA nominal (15JlA nominal on paR) from each of these inputs to VGG.
*VDD may be connected to VGG if single power supply operation is desired.
**At VGG
,

D/A

~CDNVERTER

l
....

SELECTOR

ILK

P.C. STACK
15-LEVEL11131

lLJ

PROGRAM COUNTER
1131

"'"

;:..

N 181

..--

BINARY
TlMERI

"'"'~
R

CD:r
ROM
S2200/A
12KI
S2400/A
14KI

....

...

LATCHES
7·SEG. DECODER

MOD
181

FLAGS
161
INTERRUPT
LOGIC

'--

CONTROL
LOGIC

..J.~
I

I ..

LATCH

a:
c

'" IA
Q

131

;-.

ACC 141

POR

B
r----

CLK/XTAL

STATUS/XTAL

BLI41

12·LEVELI

S2200/S24 00
LED ORIV E
VGG - LO GIC
Voo - OU TPUT BUFFERS
ADDER
141

F3~
ACC STACK
12·LEVELI

[

'"----

i ...

CARRY
111

BA,BU STACK
12·LEVELI

DECODER

RUN

SYNC

112Bx41
RAM

ROMS

EXT

E 141
ESTACK
12·LEVELI

S2200A/S2 400A
FLUORES CENT DRIVE
VGG - LO GIC
VFO - FL UDRESCENT
DRIVE BI AS
VSS - GR OUND

BL STACK
12·LEVELI

52200/2400 Block Diagram

For applications such as pulse width measurement, in- Another register, the MOD Register, controls the selec··
terval timing and event counting, the 82200/2400 has an tion of inputs and outputs for the Programmable Counter/
8-bit binary down-counter which counts 256 distinct Timer, as well as the Display Latch output polarity and
states. The number of states (1 to 256) is controlled by the voltage comparator's noninverting-input source.
the (Modulo-) N Register.
4.12

82000 FAMILY
S2200/2400

Absolute Maximum Ratings (All voltages measured with respect to Vss)
Storage Temperature ................................................................. - 55°C to + i25°C
Operating Temperature ................................................................... O°C to + 70°C
Operating Temperature (speci;!l request) ................................................. - 40°C to + 85°C
Maximum Positive Voltage ........................................................................ + 18V
Maximum Negative Voltage ...................................................................... - 0.3V
Maximum Output Currents .......................................................... (See Conditions p. 12)
IDD Supply Current (depends upon output loads) ................................................... + 75mA
Total Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 700m W
Electrical Characteristics
(Vss = OV. VGG = + 7.5V to + 10.0V; VDD = + 5V*. TA = O°C to + 70°C. fSYNC = 125kHz to 225kHz)

Parameter
INPUTS

Ko thru K7
Low Level
High Level

INPUT

KREF

INPUTS

Ko thru K7
For AID Conversion
Logic Low Level
Logic High Level

INPUT

INPUTS

OUTPUTS

POR
Low Level (POR Reset)
High Level
Power Fail
-No Interrupt
-Interrupt
ROMs. RUN
Low Level
High Level
Do thru D7
Low Level
High Level
Ao thru Aa
High Level
Low Level
A4 thru A12
EXT. SYNC. & S
High Level
Low Level
Do thru D7
High Level
Low Level

Min.

Max.

Units

Conditions

0
KREF+ 0.5

KREF- 0.5
VGG

V
V
V

For TouchControl and
Keyswitch
Inputs

2/3 VGG

2/3 VGG
0.8

V
V
V

1.0
VGG

V
V

VGG

V
V

0
3.5

0.8
VGG

V
V

0
4.5

0.8
VGG

V
V

3.5
0

*VDD
0.8

V
V

1= -5mA**
1= + 25mA**

3.5
0

*VDD
0.6

V
V

1= -5mA**
1= +5mA**

3.5
0

*VDD
1.0

V
V

1= -5rnA**
1= + 12mA**

rnA

Typ.

3.5
0
1/2 VGG

VGG+1

For AID
Conversion
As Logic Inputs

(Note 1)

IGG

Supply Current

IRAM

RAM "Keep Alive"
Current

*VDD may be connected to VGG if single power supply operation is desired.
**At VGG~8.5VDC
Note 1: There is an internal pullup of lOOItA nominal from each of these inputs to VGG'
4.13

/LA/Bit

VRAM=4.0V

82000 FAMILY
S2200A/S2400A Preliminary Electrical Specifications
Absolute Maximum Ratings (All voltages measured with respect to Vss)
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to + 125°C
Operating Temperature ................................................................... O°C to + 70°C
Operating Temperature (special request) ................................................ - 40°C to + 85°C
Maximum Positive Voltage, VFD, Ao-A4' Do-D7 ....................... ~ ............................... + 33V
All other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 18V
Maximum Negative Voltage ...................................................................... - 0.3V
Maximum Output Currents ......................................................... (See Conditions below)
Source Current, any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - lOrnA
Total Average Power Dissipation ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 700m W
Rate of Rise of VFD ........................................................................... 1.6V /msec.

Electrical Characteristics - Specifications noted only for parameters which change from the S2200/2400 to the
S2200A/2400A
(Vss = OV, VGG= 7.5 + 10.0V, VFD = VGG + 22V, TA = O°C to + 70°C. fSYNC = 125kHz to 225kHz)

OUTPUTS

Parameter

Min.

Do thru D7, Ao thru A4
High Level
Low Level

-3.5

A5 thru A 12, EXT,
SYNC, & STATUS
High Level
Low Level

Max.

Units

0.6

rnA
V

0.6

V
V

rnA

3.5

Supply Current

IGG
**At

Typ.

Conditions
VOUT = VFD - 6V**
I=250~**

1= - 5mA**
1= +5mA**
No Loads

VGG~8.5VDC

NOTE 1: The output buffers for lines A5-A12 are supplied from VGG.
NOTE 2: Xhe high voltage parts, when biased with normal VFD' are not TTL-compatible; when using external program ROM, it is necessary
to interpose buffers.
NOTE 3: When applying power, VFD must rise with or after VGG at a rate not to exceed 1.6V/msec.

S2200A Typical Microwave/Standard Oven Application

60Hz
FLUORESCENT DISPLAY

MEAT PROBE
OVEN TEMPERATURE SENSOR

AS
A6
A1
AB
Ag

STIRRER
MAGNETRON
BROWN

SPKR. FREn.

ODOR INTERLOCK

AO
AMI
S2200A

K1
Kl
K2
K3
K4

0
0
0
0

0
0

0
0
0
0

0
0

TOUCHCONTROL TM KEYBOARD
+10V

+32V

MAGNETRON&:

VACUUM FLUORES~ENT
fiLAMENTS

4.14

0
0

5
59900 Family

Selection Guide

THE AMI S9900 MICROCOMPUTER SYSTEMS FAMILY
PART NO.
S9900
S9901

DESCRIPTION
16-Bit Single Chip Microprocessor
Programmable Systems Interface Circuit

S9902

Asynchronous Communications Controller (ACC)

S9903
S9940
S9980
S9981

Synchronous
16-Bit Single
16-Bit Single
16-Bit Single

POWER SUPPLIES
+ 12V, ±5V
+5V
+5V
+5V

Communications Controller (SCC)
Chip Microcomputer
Chip Microcomputer
Chip Microcomputer

+5V
+5V
+5V

5.2

INPUT/OUTPUT

TTL
TTL
TTL
TTL
TTL
TTL
TTL

PACKAGES
64 Pin
40 Pin
18 Pin
20 Pin
18 Pin
40 Pin
40 Pin

ADVANCED PRODUCT DESCRIPTION

59900
16·81T MICROPROCESSOR
Features

General Description

The S9900 microprocessor is a single-chip 16-bit central processing unit (CPU) produced using N-channel
silicon-gate MOS technology. The instruction set of the
S9900 includes the capabilities offered by full minicomputers. The unique memory-to-memory architecture
features multiple register files, resident in memory,
which allow faster response to interrupts and increased programming flexibility. The separate bus
structure simplifies the system design effort. AMI provides a compatible set of MOS memory and support circuits to be used with an S9900 system. The system is
fully supported by software and complete prototyping
systems.

16-Bit Instruction Word

D· Full Minicomputer Instruction Set Capability

including Multiply and Divide
Up to 65,536 Bytes of Memory
3.3MHz Speed
Advanced Memory-to-Memory Architecture
Separate Memory, 1/0 and Interrupt-Bus Structures
o 16 General Registers
o 16 Prioritized Interrupts
o Programmed and DMA 1/0 Capability
ON-Channel Silicon-Gate Technology

o
o
o
o

Block Diagram

Pin Configuration

INTERRUPT

ADDRESS

I
CONTROL _

CONTROL

ClOCK-----'

CRU

DATA

5.3

89900

S9900 Electrical and Mechanical Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unl.ess otherwise noted)*

Supply Voltage, Vcc (See Note 1) .......................................................... -O.3V to +20V
Supply Voltage, VDD (See Note 1) .......................................................... -O.3V to +20V
Supply Voltage, Vss (See Note 1) .......................................................... - O.3V to + 20V
All Input Voltages (See Note 1) ............................................................ -O.3V to +20V
Output Voltage (with Respect to Vss). ........................................................ - 2V to + 7V
Continuous Power Dissipation ................ '" .............................. , .................. + 1.2W
Operating Free-Air Temperature Range ..................................................... O°C to +70°C
Storage Temperature Range ............................................................. - 55°C to + 150°C
·Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute·maximum·rated conditions ~or extended periods may affect device reliability.
NOTE 1: Under absolute maximum ratings voltage values are with respect to the most negative supply, VBB (substrate), unless otherwise
noted. Throughout the remainder of this section, voltage values are with respect to Vss.

Recommended Operating Conditions
Symbol
VBB

Parameter

Min.

Nom.

Max.

Unit

Supply voltage

-5.25

-5

-4.75

VCC

Supply voltage

4.75

5.25

VDD

Supply voltage

11.4

12.6

VSS

Supply voltage

High-level input voltage (all inputs except clocks)

VlH(l)

Clock -1 input capacitance

100

150

VBB = -5, f = 1MHz,
unmeasured pins at Vss

Ci(2)

Clock -2 input capacitance

150

200

VBB = -5, f = 1MHz
unmeasured pins at Vss

Ci(3)

Clock-3 input capacitance

100

150

VBB = -5, f = 1MHz,
unmeasured pins at Vss

Ci(4)

Clock-4 input capacitance

100

150

VBB = -5, f = 1MHz,
unmeasured pins at VSS

CDB

Data bus capacitance

VBB = -5, f = 1MHz,
unmeasured pins at VSS

Output capacitance (any output except
data bus)

VBB = -5, f = 1MHz,
unmeasured pins at VSS

rnA

t All typical values are at T A = 25 C and nominal voltages.
*D.C. Component of Operating Clock.

Switching Characteristics Over Full Range of Recommended Operating Conditions (See Figure 2)
Symbol
tpLH or tpHL

Parameter

Conditions

Propagation delay time, clocks to outputs

CL = 200pF

5.5

59900

Figure 1. Clock Timing

I14.. --------,,'~-------___l.1
f4---",,"o'"----+j
I
9.4V

CLOCK.;:.'

I
o.1V
1
1 0.7V 1
"~-l J-- -11-',,0,1

r-'."'-.j I
CLOCKo2

I
II
II

/---10'"°'"---+1

___Io'_L.""_H---!n :
I

I
ClOCKo]

f--'O,"¢4"--!

-'-~n:
I
I

----------"'\

t-1o,"O'"[1

______________lolL_¢4"H~z__t~~-~L-.¢'"--NOTE: All timing and voltage levels shown on ct>l applies to ct>2. ¢3. and cjA in the same manner.
Figure 2. Signal Timing

WE OUTPUT

tThe number of cycles over which input/output data must/will remain valid can be determined from the number of wait states required for
memory access. Note that in all cases data should not change during 1
<1>2
¢3
¢4

8
9
28
25

I.N
IN
IN
IN

Phase-l clock
Phase-2 clock
Phase-3 clock
Phase-4 clock

5.7

59900

Table 1. S9900 Pin Assignments and Functions (Continued)

Signature

I/O

OBIN

OUT

Data bus in. When active (high), OBIN indicates that the S9900 has disabled its output buffers
to allow the memory to place memory· read data on the data bus during MEMEN. OBIN remains low in all other cases except when HOLD A is active.

MEMEN

OUT

Memory enable. When active (low), MEMEN indicates that the address bus contains a memory
address.

OUT

Write enable. When active (low), WE indicates that memory-write data is available from the
S9900 to be written into memory.

CRUCLK

OUT

CRU clock. When active (high), CRUCLK indicates that external interface logic should sample
the output data on CRUO UT or should decode external instructions on AO through A2.

CRUIN

CRU data in. CRUIN, normally driven by 3-state or open-collector devices, receives input
data from external interface logic. When the processor executes a STC R or TB instruction, it
samples CRUIN for the level of the CRU input bit specified by the address bus (A3 through
A14).

CRUOUT

OUT

CRU data out. Serial I/O data appears on the CRUOUT line when an LOCR, SBZ, or SBO instruction is executed. The data on CRUOUT should be sampled by external I/O interface logic
when CRUCLK goes active (high).

Description
BUS CONTROL

---

INTERRUPT CONTROL

--INTREQ

Interrupt request. When active (low), INTREQ indicates that an external-interrupt is requested.
If INTR EQ is active, the processor loads the data on the interrupt-code-input lines ICO through
IC3 into the internal interrupt-code-storage register. The code is compared to the interrupt
mask bits of the status register. If equal or higher priority than the enabled interrupt level
(interrupt code equal or less than status register bits 12 through 15) the S9900 interrupt sequence is initiated. If the comparison fails, the processor ignores the request. INTREQ should
remain active and the processor will continue to sample ICO through IC3 until the program
enables a sufficiently low priority to accept the request interrupt.

ICO (MSB)
IC1
IC2
IC3 (LSB)

36
35
34
33

IN
IN
IN
IN

Interrupt codes. ICO is the MSB of the interrupt code, which is sampled when INTREQ is active. When ICO through IC3 are LLLH, the highest external-priority interrupt is being requested
and when HHHH, the lowest-priority interrupt is being requested.

HOLD

MEMORY CONTROL
64

Hold. When active (low), HOLD indicates to the processor that an external controller (e.g.,
OMA device) desires to utilize the address and data buses to transfer data to or from memory. The S9900 enters the hold state following a hold signal when it has completed its present
memory cycle.* The processor then places the address and data buses in the high-impedance
state (along with WE, MEMEN, and OBIN) and responds with a hold-acknowledge signal
(HO LOA). When HO LO is removed, the processor returns to normal operation.

*If the cycle following the present memory cycle is also a memory cycle, it, too, is completed before the S9900 enters the holdstate. The maximum
number of consecutive memory cycles is three.

5.8

89900

Table 1. S9900 Pin Assignments and Functions (Continued)

Description

Signature

I/O

HOLDA

OUT

Hold acknowledge. When active (high), HO LOA indicates that the processor is in the hold state
and the address and data buses and memory control outputs (WE, MEMEN, and DBIN) are in
the high-impedance state.

READY

Ready. When active (high), READY indicates that memory will be ready to read or write during the next clock cycle. When not-ready is indicated during a memory operation, the S9900
enters a wait state and suspends internal operation until the memory systems indicate ready.

WAIT

OUT

Wait. When active (high), WAIT indicates that the S9900 has entered a wait state because of a
not-ready condition from memory.
TIMING AND CONTROL

IAQ

OUT

Instruction acquisition. IAQ is active (high) during any memory cycle when the S9900 is acquiring an instruction. IAQ can be used to detect i"egal op codes.

LOAD

Load. When active (low), LOAD causes the S9900 to execute a nonmaskable interrupt with
memory address FFFC16 containing the trap vector (WP and PC). The load sequence begins
after the instruction being executed is completed. LOAD wi"~terminate an idle state. If
LOAD is active during the time RESET is released, then the LOAD trap wi" occur after the
RESET fuction is completed. LOAD should remain active for one instruction period. IAQ can
be used to determine instruction boundaries. This signal can be used to implement cold-start
ROM loaders. Additiona"y, front-panel routines can be implemented using CRU bits as frontpanel-interface signals and software-control routines to control the panel operations.

RESET

Reset. When active (low), RESET causes the processor to be reset and inhibits WE and CRUC LK.
When RESET is released, the S9900 then initiates a level-zero interrupt sequence that acquires
WP and PC from locations 0000 and 0002, sets a" status register bits to zero, and starts execution. RESET wi" also terminate an idle state. RESET must be held active for a minimum
of three clock cycles.

*If the cycle following the present memory cycle is also a memory cycle it, too, is completed before the S9900 enters the hold state. The maximum
number of consecutive memory cycles is three.

Timing
Memory
A basic memory read and write cycle is shown in
Figure 3. The read cycle is shown with no wait states
and the write cycle is shown with one wait state.
MEMEN goes active (low) during each memory cycle.
At the same time that MEMEN is active, the memory
address appears on the address bus bits AO through
A14. If the cycle is a memory-read-only cycle, DBIN
will go active (high) at the same time MEMEN and AO
through A14 become valid. The memory-write signal
WE will remain inactive (high) during a read cycle. If
the read cycle is also an instruction acquisition cycle,
IAQ will go active (high) during the cycle.

5.9

The READY signal, which allows extended memory
cycles, is shown high during <7>1 of the second clock cycle of the read operation. This indicates to the 89900
that memory-read data will be valid during <7>1 of the
next clock cycle. If READY is low during <7>1, then the
89900 enters a wait state suspending internal operation until a READY is sensed during a subsequent <7>1.
The memory read data is then sampled by the 89900
during the next <7>1, which completes the memory-read
cycle.
At the end of the read cycle, MEMEN and DBIN go inactive (high and low, respectively). The address bus
may also change at this time; however, the data bus remains in the input mode for one clock cycle after the
read cyde.

59900
A write cycle is similar to the read cycle with the exception that WE goes active (low) as shown and valid
write data appears on the data bus at the same time
the address appears. The write cycle is shown as an example of a one-wait-state memory cycle. READY is low
during <1>1 resulting in the WAIT signal shown.

ing as shown. If hold occurs during a CRU operation,
the 89900 uses an extra clock cycle (after the removal
of the HOLD signal) to reassert the CRU address providing the normal setup times for the CRU bit transfer
that was interrupted.

Hold

CRU

Other interfaces may utilize the 89900 memory bus by
using the hold operation (illustrated in Figure 4) of the
89900. When HOLD is active (low), the 89900 enters
the hold state at the next available non-memory cycle.
Considering that there can be a maximum of three consecutive memory cycles, the maximum delay between
HOLD going active to HOLDA going active (high) could
be tc(cj» (for setup) + (6 + 3W) tc(cj» + tc(cj» (delay for
HOLDA), where W is the number of wait states per
memory cycle and tc(cj» is the clock cycle time. When
the 89900 has entered the hold state, HOLDA goes active (high) and AO through A15, DO through D15 DBIN,
MEMEN, and WE go into a high-impedance state to
allow other devices to use the memory buses. When
HOLD goes inactive (high), the 89900 resumes process-

CRU interface timing is shown in Figure 5. The timing
for transferring two bits out and one bit in is shown.
These transfers would occur during the execution of a
CRU instruction. The other cycles of the instruction
execution are not illustrated. To output a CRU bit, the
CRU-bit address is placed on the address bus AO
through A14 and the actual bit data on CRUOUT. During the second clock cycle a CRU pulse is supplied by
CRUCLK. This process is repeated until the number of
bits specified by the instruction are completed.
The CRU input operation is similar in that the bit address appears on AO through A14. During the subsequent cycle the 89900 accepts the bit input data as
shown. No CRUCLK pulses occur during a CRU input
operation.

Figure 3. S9900 Memory Bus Timing

·----~~~
I

DBIN

______~~!~--------~~L______________~!~:----I

------~(~------~\~--------+I--------------~I----I
I
\'----------'1

AO·A14

VALID ADDRESS

READY

WAIT

VALID ADDRESS

DDN'T CARE

------~--------~----------~----~/

00·015

CPU DRIVEN

\'--_r----

CPU WRITE DATA

lAD

MEMORY READ CYCLE WITH NO WAITS

MEMORY WRITE CYCLE WITH ONE WAIT

RD = READ DATA

5.10

CPU DRIVEN

59900

Figure 4. S9900 Hold Timing

(,3

,;4

MEMEN

AO-AI4

~
~

'------------i

HI-Z

'----~------.,I\-\ _ _ _ _ _ _ _ - J

;

_________________X)~--~---H-I-Z------~\\-\
--------------CJC:
I
,
=====================Xr----~--~H~IZ~-----~I~I----------------~~
1,----------------_____
,
HI-Z

=*::::x

00-015

OBIN

WE
READY

WAIT

HOLDA

HOLD

-1

~~--~---------------.,I\-I-----------------~

~Oj~T:C!R~~
,

HIZ

'€ogc3~~rMH\?(XXXXXXXXX)
I
I
,

\
I
/
I
I
I
-1-_ _ _ _ _ _-:...1_--'/1
\

r+-

; :

I·

PROCESSOR OUTPUTS FLOATING

Figure 5. S9900 CRU Interface Timing
91

AO-A1S

I
I
I

CRUCLK

....
....

---4.X

-U-NK-NO-W-N

CRUIN

'-----.:C::;.RU:..:.A:.:.;DD:.;.::RE:.:;SS:..:::m_ _

"~~I--~II~-+--\\\-\---+--------~-I I I
j

CRUOUT

+---V-A....-..

UNKNOWN
',.----CR-U--'BIT-A-OO-RE"'-SS-n----,. ' - _ _CRUAODRESSn+l
__
_ _ _ _ _..J
_ _ _ _ _ _ _ _----J ' - -_ _ _-11-_ _---'

1
CRU DATA OUT n

I
CRU DATA OUT n + 1

X,-----UN-K-NO-WN---+-x==

eR3~§o}'~&€E~
I
j
I
~~~AlID
1

----.-----

CRU OUTPUT

CRU INPUT

5.11

INPUT BIT m

59900

Architecture
The 89900 operation is shown in Figure 6 and its architecture illustrated by Figure 7.
Figure 6. S9900 CPU Flow Chart

RESET SIGNAL
CAUSES IMMEDIATE
ENTRY HERE

GET RESET VECTOR
(WP AND PC)
FROM LOCATION 0, 2
STORE PREVIOUS PC,
WP, AND ST IN NEW
WORKSPACE. SET
INTERRUPT MASK
(ST12·ST15) = 0

Y
Y

GET LOAD VECTOR
(WP AND PC) FROM
LOCATION FFFCI6.
FFFEI6·
STORE PREVIOUS PC,
WP, AND ST IN NEW
WORKSPACE. SET
INTERRUPT MASK
(ST12·ST15) = 0

GET INTERRUPT LEVEL
VECTOR (WP AND PC)
STORE PREVIOUS PC,
WP, AND ST IN NEW
WORKSPACE. SET
INTERRUPT MASK (ST12
·ST15) TO LEVEL-1

5.12

59900

Figure 7. Architecture

rNTAEQ lCOIC3

AO AI4

HOLD
HOLOA

LOAD
WE
WAIT
MEMEN
RESET

CRUCLK

Registers and Memory
The S9900 employs an advanced memory-to-memory
architecture. Blocks of memory designated as
workspace replace internal-hardware registers with
program-data registers. The memory word of the
S9900 is 16 bits long. Each word is also defined as 2
bytes of 8 bits. The instruction set of the S9900 allows
both word and byte operands. Thus, all memory locations are on even address boundaries and byte instructions can address either the even or odd byte. The
memory space is 65,536 bytes or 32,768 words. The
word and byte formats are shown below.
MSB

LSB

101112131415161718191101111121131141151
SIGN
BIT

MEMORY WORD (EVEN ADDRESS)

MSB

LSB MSB

0 11
SIGN
BIT

LSB

I 213 1415 1 6 I 71819 110 111112113 b41151
SIGN
BIT

L-------~v~--------~~------~vr----------~

EVEN BYTE

ODD BYTE

The S9900 memory map is shown in Figure 8. The first
32 words are used for interrupt trap vectors. The next
contiguous block of 32 memory words is used by the extended operation (XOP) instruction for trap vectors.
The last two memory words, FFFC 16 and FFFE 16, are
used for the trap vector of the LOAD signal. The remaining memory is then available for programs, data,
and workspace registers. If desired, any of the special
areas may also be used as general memory.

89900

Figure 8. Memory Map
MEMORY
AOORESS16

AREA DEFINITION

MEMORY CONTENT
15
WP LEVEL 0 INTERRUPT

OOOE

INTERRUPT VECTORS

0002

PC LEVEL 0 INTERRUPT

0004

WP LEVEL 1 INTERRUPT

0006

PC LEVEL 1 INTERRUPT

>
OOlC

WP LEVEL 15 INTERRUPT

OOlE

PC LEVEL 15 INTERRUPT

0040

WP XOP 0

0042

PC XOP 0

007C

WO XOP 15

007E

PC XOP 15

XOP SOFTWARE TRAP VECTORS

0080

·
··

GENERAL MEMORY AREA
GENERAL MEMORY FOR
PROGRAM, DATA, AND
WORKSPACE REGISTERS

MAY BE ANY
COMBINATION OF
PROGRAM SPACE
OR WORKSPACE

··

LOAD SIGNAL VECTOR

FFFC

WP LOAD FUNCTION

FFFE

PC LOAD FUNCTION

NOTE: 1 interrupt level 0 is reserved for RESET.

Three internal registers are accessible to the user. The
program counter (PC) contains the address of the instruction following the current instruction being executed. This address is referenced by the processor to
fetch the next instruction from memory and is then
automatically incremented. The status register (ST)
contains the present state of the processor. The
workspace pointer (WP) contains the address of the
first word in the currently active set of workspace
registers.

ship between the workspace pointer and its corresponding workspace is shown below.

A workspace-register file occupies 16 contiguous
memory words in the general memory area (see Figure
2). Each workspace register may hold data or addresses and function as operand registers, accumulators, address registers, or index registers. During instruction execution, the processor addresses any
register in the workspace by adding the register
number to the contents of the workspace pointer and
initiating a memory request for the word. The relation5.14

GENERAL MEMORY
PROGRAM A

~
<

59900

-1

WORKSPACE REGISTER 0

(A)

ST (A)

i
WORKSPACE A

WORKSPACE REGISTER 15

<>
PROGRAM B

>
WORKSPACE B

S9900

The workspace concept is particularly valuable during
operations that require a context switch, which is a
change from one program environment to another (as
in the case of an interrupt) or to a subroutine. Such an
operation, using a conventional multi-register arrangement, requires that at least part of the contents of the
register file be stored and reloaded. A memory cycle is
required to store or fetch each word. By exchanging
the program counter, status register, and workspace
pointer, the S9900 accomplishes a complete context
switch with only three store cycles and three fetch
cycles. After the switch the workspace pointer contains the starting address of a new 16-word workspace
in memory for use in the new routine. A corresponding
time saving occurs when the original context is
restored. Instructions in the S9900 that result in a context switch include:
1. Branch and Load Workspace Pointer (BLWP)
2. Return from Subroutine (RTWP)
3. Extended Operation (XOP).
Device interrupts, RESET, and LOAD also cause a context switch by forcing the processor to trap to a service subroutine.
Interrupts

The S9900 employs 16 interrupt levels with the highest
priority level 0 and lowest level 15. Level 0 is reserved
for the RESET function and all other levels may be
used for external devices. The external levels may also
be shared by several device interrupts, depending
upon system requirements.
The S9900 continuously compares the interrupt code
(lCO through IC3) with the interrupt mask contained in
status-register bits 12 through 15. When the level of
the pending interrupt is less than or equal to the enabling mask level (higher or equal priority interrupt), the
processor recognizes the interrupt and initiates a context switch following completion of the currently executing instruction. The processor fetches the n-ew context WP and PC from the interrupt vector locations.
The, the previous context WP, PC, and ST are stored
in workspace registers 13, 14, and 15, respectively, of
the new workspace. The S9900 then forces the interrupt mask to a value that is one less than the level of
the interrupt being serviced, except for the level-zero
interrupt, which loads zero into the mask. This allows
only interrupts of higher priority to interrupt a service
routine. The processor also inhibits interrupts until
the first instruction of the service routine has been executed to preserve program linkage should a higher
priority interrupt occur. All interrupt requests should
remain active until recognized by the processor in the

device-service routine. The individual service routines
must reset the interrupt requests before the routine is
complete.
If a higher priority interrupt occurs, a second context

switch occurs to service the higher priority interrupt.
When that routine is complete, a return instruction
(RTWP) restores the first service routine parameters
to the processor to complete processing of the lowerpriority interrupt. All interrupt subroutines should
terminate with the return instruction to restore
original program parameters. The interrupt-vector
locations, device assignment, enabling-mask value, and
the interrupt code are shown in Table 2.
Input/Output

The S9900 utilizes a versatile direct command-driven
I/O interface designated as the communicationsregister unit (CRu). The CRU provides up to 4096
directly addressable input bits and 4096 directly addressable output bits. Both input and output bits can
be addressed individually or in fields of from 1 to 16
bits. The S9900 employs three dedicated I/O pins
(CRUIN, CRUOUT, and CRUCLK) and 12 bits (A3
through A14) of the address bus to interface with the
CRU system. The processor instructions that drive the
CRU interface can set, reset, or test any bit in the CRU
array or move between memory and CRU data fields.
Single-Bit CRU Operations

The S9900 performs three single-bit CRU functions:
test bit (TB), set bit to one (SBO), and set bit to zero
(SBZ). To identify the bit to be operated upon, the
S9900 develops a CRU-bit address and places it on the
address bus, A3 to A14.
For the two output operations (SBO and SBZ), the processor also generates a CRUCLK pUlse, indicating an
output operation to the CRU device, and places bit 7 of
the instruction word on the CRUOUT line to accomplish the specified operation (bit 7 is a one for SBO
and a zero for SBZ). A test-bit instruction transfers the
addressed CRU bit from the CRUIN input line to bit 2
of the status register (EQUAL).
The S9900 develops a CRU-bit address for the singlebit operations from the CRU-base address contained in
workspace register 12 and the signed displacement
count contained in bits 8 through 15 of the instruction.
The displacement allows two's complement addressing
from base minus 128 bits through base plus 127 bits.
The base address from W12 is added to the signed
displacement specified in the instruction and the result
is loaded onto the address bus. Figure 9 illustrates the
development of a single-bit CRU address.

S9900

Table 2. Interrupt Level Data

Vector Location
(Memory Address
In Hex)

Interrupt Level
(Highest priority) 0

00
04
08
OC
10
14
18
lC
20
24
28
2C
30
34
38
3C

1
2
3
4
5
6
7

8
9

10
11
12
13
14
(Lowest priority) 15

Interrupt Mask Values to
Enable Respective Interrupts
(ST12 through ST15)
othrough F*
1 through F
2 through F
3 through F
4 through F
5 through F
6 through F
7 through F
8 through F
9 through F
A through F
B through F
Cthrough F
o through F
E and F
F only

Device Assignment
Reset
External device

External device

*Level 0 can not be disabled.

Figure 9. S9900 Single-Bit CR U Address Development

'__x__'__x---'-_x--'-_--'------L_--'-------'_-'--~'_____L.__.L.._.__'__..L_____'_

__'__X___'I

W12

DON'T CARE

+
,~~~
BIT 8 SIGN
EXTENDED

I I I

SIGNED
DISPLACEMENT

~
9

ADDRESS BUS

SET TO ZERO
FOR ALL CRU
OPERATIONS

EFFECTIVE CRU BIT ADDRESS

5.16

Interrupt
Codes
ICO through IC3

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

59900
Multiple-Bit CRU Operations

The S9900 performs two multiple-bit CRU operations:
store communications register (STCR) and load communications register (LDCR). Both operations perform
a data transfer from the CRU-to-memory or from
memory-to-CRU as illustrated in Figure 10. Although
the figure illustrates a full 16-bit transfer operation,
any number of bits from 1 through 16 may be involved.
The LDCR instruction fetches a word from memory
and right-shifts it to serially transfer it to CRU output
bits. If the LDCR involves eight or fewer bits, those
bits come from the right-justified field within the addressed byte of the memory word. If the LDCR involves nine or more bits, those bits come from the
right-justified field within the whole memory word.
When transferred to the CRU interface, each suc-

cessive bit receives an address that is sequentially
greater than the address for the previous bit. This addressing mechanism results in an order reversal of the
bits; that is, bit 15 of the memory word (or bit 7)
becomes the lowest addressd bit in the CRU and bit 0
becomes the highest addressed bit in the CRU field.
An STCR instruction transfers data from the CRU to
memory. If the operation involves
byte or less
transfer, the transferred data will be stored rightjustified in the memory byte with leading bits set to
zero. If the operation involves from nine to 16 bits, the
transferred data is stored right-justified in the
memory word with leading bits set to zero.

When the input from CRU device is complete, the first
bit from the CRU is the least-significant-bit position in
the memory word or byte.

Figure 10. S9900 LDCR/STCR Data Transfers

CRU
OUTPUT
BITS

CRU
INPUT
BITS

N+l

N+l
INPUT (STCR)

EFFECTIVE MEMORY ADDRESS

OUTPUT (LOCR)
N+14

I N+14

N+15

N = BIT SPECIFIED BY CRU BASE REGISTER

5.17

59900

S9900 Instruction Set
Definition

Each 89900 instruction performs one of the following
operations:

Arithmetic. logical. comparison. or manipulation
operations on data

Loading or storage of internal registers (program
counter. workspace pointer. or status)

Data transfer between memory and external
devices via the CRU

Control functions.

Workspace Register Indirect Auto Increment Addressing
*R+
Workspace Register R contains the address of the
operand. After acquiring the operand. the contents of
workspace Register R are incremented.

( P C ) - / Instruction

~(WP)+ 2R

Addressing Modes

89900 instructions contain a variety of available modes
for addressing random-memory data (e.g .• program
parameters and flags). or formatted memory data
(character strings. data lists. etc.). The following
figures graphically describe the derivation of the effective address for each addressing mode. The applicability of addressing modes to particular instructions is
described later along with the description of the operations performed by the instruction. The symbols
following the names of the addressing modes [R. *R.
*R + .@LABEL. or @ TABLE (R)] are the general
forms used by 89900 assemblers to select the addressing mode for register R.

8ymbolic

(Dire~t)

Addressing @LABEL

The word following the instruction contains the address of the operand.

(PC)

--t

(PC) + 2

-+\

Instruction
Label

I-------!.~I

Operand

Indexed Addressing @TABLE (R)

Workspace Register Addressing R
The word following the instruction contains the base
address. Workspace Register R contains the index
value. The sum of the base address and the index value
results in the effective address of the operand.

Workspace Register R contains the operand.
Register R
(PC) - I Instruction

~(WP) + 2R1

Operand

Workspace Register Indirect Addressing *R
Workspace Register R contains the address of the
operand.

(PC)

~(WP)+ 2R1

AddressH

Operand

5.18

S9900

Immediate Addressing

Terms and Definitions

The word following the instruction contains, the
operand.

The following terms are used in describing the instructions of the S9900:
TERM
B

Program Counter Relative Addressing
The 8-bit signed displacement in the right byte (bits 8
through 15) of the instruction is multiplied by 2 and added to the updated contents of the program counter.
The result is placed in the PC.

C
D
DA
lOP
LSB(n)
MSB(n)

Jump Instruction

2· DISP

PC
Result
S
SA
CRU Relative Addressing
The 8-bit signed displacement in the right byte of the
instruction is added to the CRU base address (bits 3
through 14 of the workspace Register 12). The result is
the CRU address of the selected CRU bit.

Instruction
(PC)----+i

Inl
+

OPCODE

~------~----~

CRU Bit
Address
Register 12
(WP) + 2 ·12
23

AND
OR

<±>

CRU Base Add

ST
STn
TD
Ts
W
WRn
(n)
a-+b

14 15

5.19

DEFINITION
Byte indicator (1 = byte,
0= word)
Bit count
Destination address register
Destination address
Immediate operand
Least significant (right most) bit
of (n)
Most significant (left most) bit
of (n)
Don't care
Program counter
Result of operation performed
by instruction
Source address register
Source address
Status register
Bit n of status register
Destination address modifier
Source address modifier
Workspace register
Workspace register n
Contents of n
a is transferred to b
Absolute value of n
Arithmetic addition
Arithmetic subtraction
Logical AND
Logical OR
Logical exclusive 0 R
Logical complement of n

59900
Status Register
The status register contains the interrupt mask level and information pertaining to the instruction operation.

STO

ST1

ST2

ST3

ST4

ST5

ST6

Bit
STO

Name

Instruction

LOGICAL
GREATER
THAN

C,CB
CI
ABS
All Others

ST1

ARITHMETIC
GREATER
THAN

not used (=0)

ST12 ST13 ST14 ST15
Interrupt Mask

Condition to Set Bit to 1
If MSB(SA) = 1 and MSB(DA) = 0, or if MSB(SA) = MSB(DA)
and MSB of [(DA)-(SA)] = 1
If MSB(W) = 1 and MSB of lOP = 0, or if MSB(W) = MSB of
lOP and MSB of [IOP-(W)] = 1
If (SA) TO
If result T 0

ABS
All Others

If (SA) = (DA)
If (W) = IOP_
If (SA) and (DA) = 0
If (SA) and (DA) = 0
If CRUIN = 1
If (SA) = 0
If result = 0

EQUAL

C,CB
CI
COC
CZC
TB
ABS
All Others

ST3

CARRY

A, AB, A'BS, AI,
DEC,DECT,
INC, INCT, NEG
S,SB
SLA, SRA,
SRC, SRL

ST4

OVERFLOW

A,AB
AI
S,SB
DEC,DECT
INC,INCT
SLA
DIV

ST5

PARITY

CB,MOVB
LDCR, STCR
AB, SB, SOCB,
SZCB

ABS, NEG

ST128T15

If MSB(SA) = 0 and MSB(DA) = 1, or if MSB(SA) = MSB(DA)
and MSB of [(DA)-(SA)] = 1
If MSB(W) = 0 and MSB of lOP = 1, or if MSB(W) == MSB of
lOP and MSB of [IOP-(W)] = 1
If MSB(SA) = 0 and (SA) T 0
If MSB of result = 0 and result T 0

C,CB

ST2

ST6

XOP

INTERRUPT
MASK

LIM I
RTWP

If CARRY OUT = 1

If last bit shifted out = 1
If MSB(SA) = MSB(DA) and MSB of result T MSB(DA)
If MSB(W) = MSB of lOP and MSB of result T MSB(W)
If MSB(SA) T MSB(DA) and MSB of result T MSB(DA)
If MSB(SA) = 1 and MSB of result = 0
If MSB(SA) = 0 and MSB of result = 1
If MSB changes during shift
If MSB(SA) = 0 and MSB(DA) = 1, or if MSB(SA) = MSB(DA)
and MSB of [(DA)-(SA)] = 0
If (SA) = 800016
If (SA) has odd number of l's
If 1 < C < 8 and (SA) has odd number of 1 's
If result-has odd number of l's
If XOP instruction is executed
If corresponding bit of lOP is 1
If corresponding.bit of WR15 is 1

5.20

59900

Instructions
Dual Operand Instructions with Multiple Addressing Modes for Source and Destination Operand

General format:

OP CODE

8
D

If B = 1 the operands are bytes and the operand addresses are byte addresses. If B
and the operand addresses are word addresses.

0 the operands are words

The addressing mode for each operand is determined by the T field of that operand.

TS or TD

S orD

00
01
10
10
11

0,1, ... 15
0,1, ... 15

Addressing Mode

Notes

Workspace register
Workspace register indirect
Symbolic
Indexed
Workspace register indirect auto-increment

1,2, ... 15
0,1, ... 15

1
4
2,4
3

Notes:
1. When a workspace register is the operand of a byte instruction (bit 3 = 1), the left byte (bits 0 through 7) is
~ the operand and the right byte (bits 8 through 15) is unchanged.
2. Workspace register 0 may not be used for indexing.
3. The workspace register is incremented by 1 for byte instructions (bit 3 = 1) and is incremented by 2 for
word instructions (bit 3 = 0).
4. When TS = TD = 10, two words are required in addition to the instruction word. The first word is the source
operand base address and the second word is the destination operand base address.

RESULT
COMPARED
TO 0

STATUS
BITS
AFFECTED

Add

Yes

Add bytes

Yes
No

0-4
0-5
0-2

Compare bytes

0-2,5

Subtract

Yes

Subtract bytes

Yes

0-4
0-5
0-2
0-2,5
0-2
0-2,5
0-2
0-2,5

OP CODE
0 1 2

B
3
0

1 0 1
1 0 1
1 0 0

1
0

Compare

1 0 0

0
0
1
1
0
0
1
1

1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1

MNEMONIC
A
AB

SB
SOC
SOCB
SZC
SZCB
MOV
MOV'B

1
1
1
1
0
0

0
0

MEANING

Set ones corresponding

Yes

Set ones corresponding bytes

Yes

Set zeroes corresponding

Yes

Set zeroes corresponding bytes

Yes

Move

Yes

Move bytes

Yes

5.21

DESCRIPTION
(SA) + (DA)--+ (DA)
(SA) + (DA) --+ (DA)
Compare (SA) to (DA) and
set appropriate status bits
Compare (SA) to (DA) and
set appropriate status bits
(DA) - (SA)--+(DA)
(DA) - (SA)--+(DA)
(DA) OR (SA)--+(DA)
(DA) OR (SA)--+(DA)
(DA) AND (SA)--+(DA)
(DA) AND (SA)--+(DA)
(SA)--+(DA)
(SA)--+(DA)

59900

Dual Operand Instructions with Multiple Addressing Modes for the Source Operand and Workspace Register Addressing for the Destination

General format:

OP CODE

The addressing mode for the source operand is determined by the Ts field.
ADDRESSING MODE

00
01
10
10
11

0,1, ... 15
0,1, ... 15

Workspace register

1,2, °
... 15

Symbolic
Indexed

0,1, ... 15

Workspace register indirect auto increment

NOTES

Workspace register indirect

1
2

NOTES: 1. Workspace register 0 may not be used for indexing.
2. The workspace register is incremented by 2.

MNEMONIC

OPCODE
o1 2 3 4 5

COC

001 000

CZC

XOR
MPY

DIV

MEANING

RESULT
COMPARED
TOO

STATUS
BITS
AFFECTED

00101 0
o0 1 1 1 0

Compare ones
corresponding
Compare zeros
corresponding
Exclusive OR
Multiply

Yes
No

0-2

001 1 1 1

Divide

100 1

5.22

DESCRIPTION
Test (D) to determine if l's are in each bit
position where l's are in (SA). If so, set ST2.
Test (D) to determined if D's are in each bit
position where l's are in (SA). If so, set ST2.
(D)0(SA)-+ (D)
Multiply unsigned (D) by unsigned (SA) and
place unsigned 32-bit product in D (most
significant) and D+ 1 (least significant). If
WR15 is D, the next word in memory after
WR15 will be used for the least significant
half of the product.
If unsigned (SA) is less than or equal to unsigned (D), perform no operation and set
ST4. Otherwise, divide unsigned (D) and
(D+l) by unsigned (SA). Quotient -+ (D),
remainder -+ (D+ 1). If D = 15, the next
word in memory after WR15 will be used for
the remainder.

59900
Extended Operation (XOP) Instruction

General format:

The Ts and 8 fields provide multiple mode addressing capability for the source operand. When the XOP is executed, 8T6 is set and the following transfers OCI'111":
(4016 + 4D) - (WP)
(4216 + 4D) - (PC)
8A - (new WRll)
(old WP) - (new WR13)
(old PC) - (new WR14)
(old 8T) - (new WR15)
The 89900 does not test interrupt requests (INTREQ) upon completion of the XOP instruction.
Single Operand Instructions

General format:

OP CODE

The Ts and S fields provide multiple mode addressing capability for the source operand.
MNEMONIC

OP CODE
1 2 3 4 5 6 7 8 9

MEANING

RESULT
COMPARED
TO 0

STATUS
BITS
AFFECTED

DESCRIPTION

0000010001

Branch

SA~(PC)

Branch and link

(PC)~(WRll); SA~(PC)

BLWP

0000010000

Branch and load
workspace pointer

Clear operand

0 001 1 0 1 0

(SA)~(WP); (SA+2)~(PC);

(old WP)~(new WR13);
(old PC)~(new WR14);
(old ST)~(new WR15);
the interrupt input (INTREQ)
is not tested upon completion
of the BLWP instruction.

SETO

0000011100

Set to ones

INV

Invert

Yes

0-2

(SA)~(SA)

NEG

0000010100

Negate

Yes

0-4

-(SA)~(SA)

ABS

Absolute value*

0-4

SWPB

0000011011

Swap bytes

CLR

00000 1 001 1
0 0 0 10 1 0 1
000 1 1 1 0 1

O~(SA)

FFFF16~(SA)

I(SA) I~(SA)
(SA), bits 9 thru 7~(SA), bits
8 thru 15; (SA), bits 8 thru 15
~ (SA), bits 0 thru 7.
(SA)+l~(SA)

INC

0000010110

Increment

Yes

0-4

INCT

0000010111

Increment by two

Yes

0-4

(SA) + 2~(SA)

DEC

0000011000

Decrement

Yes

0-4

(SA)-l ~(SA)

0-4
-

Execute the instruction at SA.

DECT

0000011001

Decrement by two

Yes

0000010010

Execute

(SA)-2~(SA)

*Operand is compared to zero for status bit,
tIf additional memory words for the execute instruction are required to define the operands of the instruction located at SA,
these words will be accessed from PC and the PC will be updated accordingly. The instruction acquisition signal (IAQ) will not
be true when the S9900 accesses the instruction at SA. Status bits are affected in the normal manner for the instruction executed.

5.23

59900

CRU Multiple-Bit Instructions

General format:

OP CODE

The C field specifies the ·number of bits to be transferred. If C = 0, 16 bits will be transferred. The CRU
base register (WR12, bits 3 through 14) defines the
starting CRU bit address. The bits are transferred
serially and the CRU address is incremented with each
bit transfer, although the contents of WR12 is not affected. Ts and S provide multiple mode addressing
capability for the source operand. If 8 or fewer bits are

transferred (C = 1 through 8), the source address is a
byte address. If 9 or more bits are transferred (C = 0,9
through 15), the source address is a word address. If
the source is addressed in teh worksp~ce register indirect auto increment mode, the workspace register is
incremented by 1 if C = 1 through 8, and is incremented by 2 otherwise.

STATUS
RESULT
BITS
COMPARED
AFFECTED
TO 0

LDCR

Load communication
register

Yes

0-2,5t

STCR

Store communication
register

Yes

0-2,5t

MEANING

13
S

OP CODE
1 2 3 4

MNEMONIC

DESCRIPTION

Beginning with LSB of (SA),
transfer the specified number
of bits from (SA) to the CRU.
Beginning with LSB of (SA),
transfer the specified number of
bits from the CRU to (SA). Load
unfilled bit positions with O.

tST5 is affected only if 1 ~ C ~ 8.

CRU Single-Bit Instructions

SIGNED DISPLACEMENT

OP CODE

General format:

CRU relative addressing is used to address the selected CRU bit.

MNEMONIC

OP CODE
01234567

SBO
SBZ
TB

00011101
00011110
00011111

STATUS
BITS
AFFECTED

MEANING
Set bit to one
Set bit to z.ero
Test bit

5.24

DESCRIPTION
Set the selected CRU output bit to 1.
Set the selected CRU output bit to O.
If the selected CRU input bit=l, set ST2.

59900

Jump Instructions

General format:

0
0
0
0
0
0
0
0
0
0
0
0
0
0

JEQ
JGT
JH
JHE
JL
JLE
JLT
JMP
JNC
JNE
JNO
JOC
JOP

1
0
0
0
0
0
0
0
0
0
0
0
0
0

OP CODE
2 3 4 5
0 1 0 0
0 1 0 1
0 1 1 0
0 1 0 1
0 1 1 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1

6
1
0
1
0
1
1
0
0
1
1
0
0
0

7
1
1
1
0
0
0
1
0
1
0
1
0
0

DISPLACEMENT

OP CODE

is a word count to be added to PC. Thus, the jump instruction has a range of - 128 to 127 words from
memory-word address following the jump instruction.
No ST bits are affected by jump instruction.

Jump instructions cause the PC to be loaded with the
value selected by PC relative addressing if the bits of
ST are at specified values. Otherwise, no operation occurs and the next instruction is executed since PC
points to the next instruction. The displacement field
MNEMONIC

ST CONDITION TO LOAD PC

MEANING
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump

ST2 = 1
STI = 1
STO = 1 and ST2 = 0
STO = 1 or ST2 = 1
STO = 0 and ST2 = 0
STO = 0 or ST2 = 1
STI = 0 and ST2 = 0
unconditional
ST3 = 0
ST2= 0
ST4= 0
ST3 = 1
ST5 = 1

equal
greater than
high
high or equal
low
low or equal
less than
unconditional
no carry
not equal
no overflow
on carry
odd parity

Shift Instructions

General format:

OPCODE

and bits 12 through 15 of WRO = 0, the shift

STATUS
RESULT
BITS
COMPARED
AFFECTED
TO 0
Yes
0-4

MNEMONIC

OP CODE
0 1 2 3 4 5 6 7

MEANING

SLA

0 0 0 0 1 0 1 0

Shift left arithmetic

SRA

0 0 0 0 1 0 0 0

Shift right arithmetic

Yes

0-3

SRC

0 0 0 0 1 0 1 1

Shift right circular

Yes

0-3

SRL

0 0 0 0 1 0 0 1

Shift right logical

Yes

0-3

5.25

If C = 0, bits 12 through 15 of WRO contain the shift count. If C =
count is 16.

DESCRIPTION
Shift (W) left. Fill vacated bit
positions with O.
Shift (W) right. Fill vacated bit
positions with original MSB of
(W).
Shift (W) right. Shift previous
LSB into MSB.
Shift (W) right. Fill vacated bit
positions with O's.

59900

Immediate Register Instructions

General format:

OPCODE

lOP

MNEMONIC

OPCODE
o 1 2 3 4 5 6 7 8 9 10

0000001000 1

ANDI

0000001001 0

0000001010 0

STATUS
BITS
AFFECTED

Add immediate

RESULT
COMPARED
TOO
Yes

0-4

(W)+IOP--+(W)

AND immediate

Yes

0-2

(W) AND IOP--+ (W)

Compare immediate

Yes

0-2

Compare (W) to lOP and set
appropriate status hits

Yes
Yes

0-2

IOP--+(W)

0-2

(W) OR IOP--+(W)

MEANING

0000001000 0

Load immediate

ORI

0000001001 1

OR immediate

DESCRIPTION

Internal Register Load Immediate Instructions

o 1

apCODE

General format:

lOP

LWPI

OPCODE
0 1 2 3 4 5 6 7 8 9 10
0 0 o 0 0 010 1 1 1

LIMI

0 0

MNEMONIC

000 1 1 0 0

DESCRIPTION

MEANING

Load workspace pointer immediate

IOP--+(WP), no ST hits affected

Load interrupt mask

lOP, hits 12 thru 15--+ST12
thru ST15

Internal Register Store Instructions

o 1

OP CODE

General format:

I N -,

No ST bits are affected.
MNEMONIC
STST
STWP

OPCODE
0 1 2 3 4 5 6 7 8 9 10
0 0 o 0 0 0 1 0 1 1 0
0 0000010 1 0 1

MEANING

DESCRIPTION

Store status register

(ST)--+(W)

Store workspace pointer

(WP)--+(W)

5.26

89900

Return Workspace Pointer (RTWP) Instruction

10 1 0

0
0

General format:

11 11

The RTWP instruction causes the following transfers to occur:
(WR15) -- (ST)
(WR14) -- (PC)
(WR13) -- (WP)

External Instructions
0

OPCODE

General format:

External instructions cause the three most-significant address lines (AO through A2) to be set to the below
described levels and the CRUCLK line to be pulsed, allowing external control functions to be initiated.

OP CODE
012 3 4 5 6 7 8 9 10

MEANING

IDLE

Idle

RSET
CKOF
CKON
LREX

0 0 0 0 o
0 0 0 0 o
0 0 000
o0 o0 0

1
0
1
1

Reset
User defined
User defined
User defined

MNEMONIC

0 0 0 0 1 1 01

0
0
0
0

1
1
1
1

0
1
1
1

1
1
0
1

5.27

STATUS
BITS
AFFECTED
-

12-15

DESCRIPTION
Suspend S9900 instruction
execution until an interrupt,
LOAD, or RESET occurs
0""*ST12 through ST15

ADDRESS
BUS
AO A1 A2
L H L

59900

S9900 Instruction Execution Times

Instruction execution times for the 89900 are a function of:
1)
2)

Table 3 lists the number of clock cycles and memory accesses required to execute each 89900 instruction. For
instructions with multiple addressing modes for either
Clock cycle time, tc(q,)
or both operands, the table lists the number of clock
Addressing mode used where operands have multi- cycles and memory accesses with all operands adple addressing mode capability
dressed in the workspace-register mode. To determine
Number of wait states required per memory ac- the additional number of clock cycles and memory access.
cesses required for modified addressing, add the

Table 3. Instruction Execution Times

INSTRUCTION
A
AB
ABS (MSB = 0)
(MSB = 1)
AI
ANDI
B
BL
BLWP
C
CB
CI
CKOF
CKON
CLR
COC
CZC
DEC
DECT
DIV (ST4 is set)
DIV (ST4 is reset)*
ID LE
INC
INCT
INV
Jump (PC is
changed)
(PC is not
changed)
LDCR (C = 0)
(1~C~8)
(9~C~15)

LI
LlMI
LREX
RESET function
LOAD function
Interrupt context
switch

CLOCK
CYCLES
C
14
14
12
14
14
14
8
12
26
14
4
14
12
12
10
14
14
10
10
16
92-124
12
10
10
10

MEMORY
ADDRESS
ACCESS
MODIFICATIONt
SOURCE DEST
M
4
A
A
4
B
B
A
2
4
A
4
4
A
2
3
A
6
A
A
3
A
B
3
B
3
1
1
3
A
A
3
3
A
3
A
3
A
3
A
6
A
1
A
3
A
3
3
A

8
52
20+2C
20+2C
12
16
12
26
22

1
3
3
3
3
2
1
5
5

A
B
A

INSTRUCTION
LWPI
MOV
MOVB
MPY
NEG
ORI
RSET
RTWP
S
SB
SBO
SBZ
SETO
Shift (C*O)
(c=o, Bits 12-15
ofWRO=O)
(C=O, Bits 12-15
of WRP=N*O)
SOC
SOCB
STCR (C=O)
(1~C~7)

(C=8)
(9~C~15)

STST
STWP
SWPB
SZC
SZCB
TB
X**
XOP
XOR

Undefined op codes
0000-01 FF, 0320033F,OCOO-OFFF,
0780-07FF

CLOCK
CYCLES
C
10
14
14
52
12
14
12
14
14
14
12
12
10
12+2C

MEMORY
ADDRESS
MODIFICATIONt
ACCESS
SOURCE DEST
M
2
4
A
A
4
B
B
A
5
A
3
4
1
4
A
A
4
4
B
B
2
2
A
3
3

20+2N
14
14
60
42
44
58
8
8
10
14
14
12
8
36
14

4
4
4
4
4
4
4
2
2
3
4
4
2
2
8
4

A
B
A
B
B
A

A
B

A
A
B

A
B

A
A
A

*Execution time is dependent upon the partial quotient after each clock cycle during execution.
**Execution time is added to the execution time of the instruction located at the source address minus 4 clock cycles and 1 memory access time_
tThe letters A and B refer to the respective tables that follow.

5.28

59900

Table A Address Modification

ADDRESSING MODE
WR (Ts orTo = 00)
WR indirect (Ts or To = 01)
WR indirect auto-increment
(Ts orTO = 11)
Symbolic (Ts orTo = 10,
S or D = 0)
Indexed (Ts orTo = 10,
SorD=#:O)

Table B Address Modification

CLOCK
CYCLES
C

MEMORY
ACCESSES
M

0
4

0
1

ADDRESSING MODE
WR (Tsor TO =00)
WR indirect (Ts or To = 01)
WR indirect auto-increment
(T s 0 r To = 11)
Symbolic (Ts or To = 10,
S or D = 0)
Indexed (TS orTO = 10,
S or D=#:O)

appropriate values from the referenced tables. The
total instruction-execution time for an instruction is:
T = tc(q,)(C + W.M)
where:
T = total instruction execution time;
tc(cI» = clock cycle time;
C = number of clock cycles for instruction execution plus address modification;
W = number of required wait states per memory
access for instraction execution plus address modificatiol!:-- no wait states used
unless accessing sl@\' memory;
M = number of memory accesses.
As an example, the instruction MOVB is used in a
system with tc(q,) = 0.333 flS and no wait states are required to access memory. Both operands are addressed
in the workspace register mode:
T = tc(q,) (C + W ·M) = 0.333 (14 + 0·4) flS = 4.662flS.
If two wait states per memory access were required,

the execution time is:
T = 0.333 (14 + 2·4) flS = 7.326flS.

5.29

CLOCK
CYCLES
C
0
4

MEMORY
ACCESSES
M

a
1

If the source operand was addressed in the symbolic

mode and two wait states were required:
T = tc(q,) (C + W.M)
C = 14 + 8 = 22
M=4+1=5
T = 0.333 (22 + 2·5) flS

10.656flS.

System Design Examples
Figure 13 illustrates a typical minimum S9900 system.
Eight bits of input and output interface are im-.
plemented. The memory system contains 1024x16
ROM and 1024x16 RAM memory blocks. The total
package count for this system is 13 packages.
A maximum S9900 microprocessor system is illustrated
in Figure 14. ROM and RAM are both shown for a total
of 65,536 bytes of memory. The I/O interface supports
4096-output bits and 4096-input bits. Fifteen external
interrupts are implemented in the interrupt interface.
The clock generator and control section contains
memory decode logic, synchronization logic, and the
clock electronics. Bus buffers, required for this maximally configured system, are indicated on the system
buses.

89900

Figure 13. Minimum S9900 System

12 BITS
ADDRESS BUS
15 BITS
'~-----------------. r-------------~
r------------~
r------------~

AO·A14

8
BITS
IN

8
BITS
OUT

r--------+i CRUIN
r----------1 CRUO UT
~---------------1 CRUCLK

INTERRUPT CODE

ICO·IC3

INTERRUPT REQUEST

CLOCK GENERATOR
S9904

Figure 14. Maximum S9900 System

ADDRESS BUS

5.30

S9900

Instruction Summary

OP CODE

FORMAT

RESULT
COMPARED
TO ZERO

STATUS
AFFECTED

A
AB
ABS
AI

AOOO
BOOO
0740
0220

1
1
6
8

Y
Y
Y
Y

0-4
0-5
0-4
0-4

ADD(WORD)
ADD(BYTE)
ABSOLUTE VALUE
ADD IMMEDIATE

ANDI
B
BL
BLWP

0240
0440
0680
0400

8
6
6
6

Y
N
N
N

0-2

AND IMMEDIATE
BRANCH
BRANCH AND LINE (Wll)
BRANCH LOAD WORKSPACE POINTER

C
CB
Cl
CKOF

8000
9000
0280
03CO

1
1
8
7

N
N
N
N

0-2
0-2,5
0-2

CKON
CLR
CDC
CZC

03AO
04CO
2000
2400

7
6
3
3

N
N
N
N

DEC
DECT
DIV
IDLE

0600
0640
3COO
0340

6
6
9
7

Y
Y
N
N

0-4
0-4
4

INC
INCT
INV
JEQ

0580
05CO
0540
1300

6
6
6
2

Y
Y
Y
N

0-4
0-4
0-2

JGT
JH
JHE
JL

1500
1800
1400
lAOO

2
2
2
2

N
N
N
N

JLE
JLT
JMP
JNC

1200
1100
1000
1700

2
2
2
2

N
N
N
N

JNE
JNO
JOC
JOP

1600
1900
1800
lCOO

2
2
2
2

N
N
N
N

LDCR
LI
LlMI
LREX

3000
0200
0300
03EO

4
8
8
7

Y
N
N
N

0-2,5
0-2
12-15
12-15

LWPI

02EO

MOV
MOVB
MPY

COOO
0000
3800

1
1
9

Y
Y
N

0-2
0-2,5

MNEMONIC

2
2

5.31

INSTRUCTIONS

COMPARE (WORD)
COMPARE (BYTE)
COMPARE IMMEDIATE
EXTERNAL CONTRO L
EXTERNAL CONTROL
CLEAR OPERAND
COMPARE ONES CORRESPONDING
COMPARE ZEROES CORRESPONDING
DECREMENT (BY ONE)
DECREMENT (BY TWO)
DIVIDE
COMPUTER IDLE
INCREMENT (BY ONE)
INCREMENT (BY TWO)
INVERT (ONES COMPLEMENT)
JUMP EQUAL (ST2= 1)
JUMP
JUMP
JUMP
JUMP

GREATER THAN (ST1=1)
HIGH (STO= 1 AND ST2=0)
HIGH OR EQUAL (STO OR ST2=1)
LOW (STO AND ST2=0)

JUMP
JUMP
JUMP
JUMP

LOW OR EQUAL (STO=O OR ST2=1)
LESS THAN (STl AND ST2=0)
UNCONDITIONAL
NO CAR RY (ST3=0)

JUMP
JUMP
JUMP
JUMP

NOT EQUAL (ST2=0)
NO OVERFLOW (ST4=0)
ON CAR RY (ST3= 1)
ODD PARITY (ST5= 1)

LOAD CRU
LOAD IMMEDIATE
LOAD IMMEDIATE TO INTERRUPT MASK
EXTERNAL CONTROL
LOAD IMMEDIATE TO WORKSPACE
POINTER
MOVE (WORD)
MOVE (BYTE)
MULTIPLY

59900

Instruction Summary (Continued)
MNEMONIC

OP CODE

FORMAT

RESU LT
COMPARED
TO ZERO

STATUS
AFFECTED
0-4
0-2
12-15
0-6,12-15
0-4
0-5

INSTRUCTIONS

NEG
ORI
RSET
RTWP

0500
0260
0360
0380

7
7

Y
Y
N
N

S
SB
SBO
SBZ

6000
7000
1000
1EOO

1
1
2
2

Y
Y
N
N

SETO
SLA
SOC
SOCB

0700
OAOO
EOOO
FOOO

6
5
1
1

N
Y
Y
Y

0-4
0-2
0-2,5

SET ONES
SHIFT LEFT (ZERO FILL)
SET ONES CORRESPONDING (WORD)
SET ONES CORRESPONDING (BYTE)

SRA
SRC
SRL
STCR

0800
OBOO
0900
3400

5
5
5
4

Y
Y
Y
Y

0-3
0-3
0-3
0-2,5

SHIFT RIGHT
SHIFT RIGHT
SHIFT RIGHT
STORE FROM

STST
STWP
SWPB
SZC

02CO
02AO
06CO
4000

8
6
1

N
N
N
Y

SZCB
TB
X
XOP

5000
1FOO
0480
2COO

1
2
6
9

Y
N
N
N

0-2,5
2

XOR

2800

0-2

NEGATE (TWO'S COMPLEMENT)
OR IMMEDIATE
EXTERNAL CONTRO L
RETURN WORKSPACE POINTER
SUBTRACT (WO RD)
SUBTRACT (BYTE)
SET CRU BIT TO ONE
SET CRU BIT TO ZERO

(MSB EXTENDED)
CIRCULAR
(LEADING ZERO FILL)
CRU

STORE STATUS REGISTER
STORE WORKSPACE POINTER
SWAP BYTES
SET ZEROES CORRESPONDING (WORD)

0-2

SET ZEROES CORRESPONDING (BYTE)
TEST CRU BIT
EXECUTE
EXTENDED OPERATION

EXCLUSIVE 0 R

ILLEGAL OP CODES 0000-01 FF, 0320-033F, 0780-07FF, OCOO-OFFF
Physical Dimensions
64-Pin Ceramic

INDEX DDT

0.120 MIN: _~~_ 0.020 MIN

PIN SPACING 0.100 T.P.

(See Note A)

3.200±oLo

0.01~

±0.003

O.O~C-::;

1- 0.185 MAX

±0.02o
NOTE A. Each pin centerline is located within 0.010 oi its true Ion gitudinalposition

0.900
• -±O.020

t
-I

~SEATINGPLANE
.~:

5.32

-11--0.010 NOM

ADVANCED PRODUCT DESCRIPTION

S9901
Programmable Systems
Interface Circuit
Features

General Description

• N-Channel Silicon-Gate Process

The S9901 Programmable Systems Interface is a
multifunctioned component designed to provide low
cost interrupts and I/O ports in a 9900/9980 microprocessor system. It is fabricated with N -channel
silicon-gate technology and is completely TTL
compatible on all inputs including the power supply
(+5V) and single-phase clock. Figure 1 is a block
diagram of the S9901. The Programmable Systems
Interface provides a 9900/9980 system with interrupt
control, I/O ports, and a real-time clock as shown in
Figure 2.

• 9900 Series CRU Peripheral
• Performs Interrupt and I/O Interface Functions
- 6 Dedicated Interrupt Input Lines
- 7 Dedicated I/O Ports
- 9 Ports Programmable as Interrupts or I/O
• Easily Stacked for Interrupt and I/O Expansion
• Interval and Event Timer
• Single 5V Supply

Figure 1. Block Diagram

S9901 Pin Configuration

RSTI

VCC

CRUOUT
CRUCLK

CRUIN

TI
INTS

INT5

INT7jPI5

TNf4

INT8/P14

INT9jP13

INTJ

INTlO/P12
INTll/Pll

fNfjf[fi

IC3

INTl2/Pl0

IC2

ICI

INT14/p8

ICb

VSS

INTI

INT15/P7

INT2
PS

Figure 2. 9900/9980 System
ADDRESS 8US
.---------------------~

r-------------------,

PROGRAMMABLE
SYSTEMS
INTERFACE

MEMORY

59900/59980
CPU

DATA BUS

5.33

89901

S9901 Electrical Specifications

Absolute Maximum Ratings Over Operating Free Air Temperature Range (Unless Otherwise Noted)*
Supply Voltages, Vcc and Vss ................................................ -0.3V to +10V
All Input and Output Voltages ................................................ -0.3V to +10V
Continuous Power Dissipation ........................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.7 5W
Operating Free-Air Temperature Range .......................................... O°C to +70°C
Storage Temperature Range ................................................ -65°C to +150°C
*Strcsscs beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. '{his is a stress
rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute maximum rated conditions
for extended period may affect device reliability.

Recommended Operating Conditions
Parameter
Supply Voltage, V cc

Min.

Nom.

Max.

4.75

5.25

Unit
V

Supply Voltage, V ss

High-Level Input Voltage, VIH

0.8

Low-Level Input Voltage, VIL

Operating Free-Air Temperature, TA

V
°c

Electrical Characteristics Over Full Range of Recommended Operating Conditions (Unless Otherwise Noted)
Symbol
II

Parameter

Min.

Input Current (Any Input)

Typ.

Max.

Unit

Conditions
VI = OV to Vcc

±10

J.1A

2.4

loB = 100J.1A

lOB

IOL = 3.2mA

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

0.4

Icc

Supply Current from V cc

100

rnA

Iss

Supply Current from V ss

200

rnA

ICC(av)

Average Supply Current from V cc

rnA

Ci
Co

Capacitance, Any Input
Capacitance, Any Output

10
20

pF
pF

-400J.1A

tc(¢) = 333ns, TA = 25°C
f = IMHz,
All Other Pins at OV

Timing Requirements Over Full Range of Operating Conditions
Symbol

Parameter

Min.

Nom.

Max.

Unit

tC(L)

Clock Pulse Low Width

tw(H)

Clock Pulse High Width

55
240

tsu

Setup Time for SO-S4, CE, or CRUOUT before CRUCLK

200

tsu

Setup Time, Input Before Valid CRUIN

200

tsu

Setup Time, Interrupt Before ¢ Low

tw(CRUCLK) CRU Clock Pulse Width
Address Hold Time
th
5.34

100

S9901

Switching Characteristics Over Full Range of Recommended Operating Conditions

Symbol

Parameter

Typ.

Min.

Max.

Unit

Test Conditions

tpD

Propagation Delay, ¢ Low to Valid
INTREQ, Ico -IC3

CL = 100pF,
2 TTL Loads

tpD

Propagation Delay, SO -S4 or CE
to Valid CRUIN

400

CL = 100pF

Figure 3. Switching Characteristics

I.-

tw(ou-..J

_ _ _ _---...1

U
1

trlQ)

--.I!.- __

U
I
I

....

__ tw(oH) _ _

tsu---J

"'I----tc(¢)~
...--_ _ _..... 1

tflo)

I ~---_"I

\,----1_ _ _ _~:_ _~;

INTERRUPT

I
I

--l

~tPD

tpD

f.-

-IN-TR-EU------------~~~_ _ _ _ _ _ _ _ _ _ _ _ __ J ! r - - - - - - - ~'su --.j

I
~

j . - - t P D - - - i..
~1

;,..--------,

I~-~----~

I__

C_R_UC_LK_ _

~tw(CRUCLK)

~~~-----------------------------:--------------------I
I

I
--.j

tsu

~--tPD----i"~1

!.--th-l

VALID ADDRESS

VALID ADDRESS
SOS4

~-----~I-----------

I
I

I
L 'su---i
l
I

,-------X

.I.......--_---J
•

INTHNT15. PO·P15

•

CRUIN

VALID INPUT DATA

~I·---------'X
VALIDCRUIN

I
I
r-rrTTT-rT">~ 'su ~

~
I

CRUOJJT

I
I
I-- th --i ............".......,.................,..................,,..........,,.......,,.,....,,................................. , . . . .,..................,,.........,,.......,,.,....,,...,,.......,.........."I!"T"I!T

VALIOOATA

!
NOTE 1: ALL TIMING MEASUREMENTS ARE FROM 10%.nd 90% POINTS

5.35

59901

Pin Definitions

Table 1 defines the 89901 pin assignments and describes the function of each pin.
Table 1. S9901 Pin Assignments and Functions

Signature

I/O

INTREQ

OUT

INTERRUPT Request. When active (low) INTREQ indicates that an enabled interrupt has been received. INTREQ will stay active until all enabled
interrupt inputs are removed.

Description

ICO (MSB)
ICI
IC2
IC3 (LSB)

15
14
13
12

Interrupt Code lines. ICO -IC3 output the binary code corresponding to
the highest priority enabled interrupt. If no enabled interrupts are active
ICO-IC3 = (1,1,1,1).

OUT
OUT
OUT
OUT
IN

SO
SI
S2
S3
S4

39
36
35
25
24

IN
IN
IN
IN
IN

Address select lines. The data bit being accessed by the CRU interface is
specified by the 5-bit code appearing on SO-S4.

CRVIN

OUT

CRU data in (to CPU). Data specified by SO-S4 is transmitted to the CPU
by CRVIN. When CE is not active CRVIN is in a high-impedance state.

CRUOOT

CRU data out (from CPU). When CE is active, data present on the CRUOUT
input will be sampled during CRUCLK and written into the command bit
specified by SO-S4.

CRUCLK

CRU Clock (from CPU). CRUCLK specifies that valid data is present on
the CRUOUT line.

RSTI

Power Up Reset. When active (low) RSTI resets all interrupt masks to
"0", disables the clock, and programs all I/O ports to inputs. RSTI has
a Schmitt-Trigger input to allow implementation with an RC circuit as
shown in Figure 6.
Supply Voltage. +5V nominal.

Chip Enable. When active (low) data may be transferred through the CRU
interface to the CPU. CE has no effect on the interrupt control section.

Vee

Vss

Ground Reference

System clock (¢3 in S9900 system, CKOUT in S9980 system).

INTI
INT2
INT3
INT4
INT5
INT6

IN
IN
IN
IN
IN
IN

Group 1, interrupt inputs. When active.
(Low) the signal is ANDed with its corresponding mask bit and if enabled
sent to the interrupt control section. INTI has highest priority.

INT7/PI5
INT8/P14
INT9/PI3
INTI0/PI2
INT11/P11
INTI2/PI0
INT13/P9
INTI4/P8
IN'T15/P7

17
18
9
8
7
6
34
33
32
31
30
29
28
27
23

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Group 2, Programmable interrupt (active low) or I/O pins (true logic).
Each pin is individually programmable as an interrupt, an input port, or an
output port.

PO
PI
P2
P3
P4
P5
P6

38
37
26
22
21
20
19

I/O
I/O
I/O
I/O
I/O
I/O
I/O

Group 3, I/O ports (true logic). Each pin is individually programmable as
an input port or an output port.

5.36

S9901

Functional Description
CPU Interface

The S9901 interfaces to the CPU through the Communications Register Unit (CRU) and the interrupt
control lines as shown in Figure 1. The CRU interface
consists of 5 address select lines (SO-S4), chip enable
(CE), and 3 CRUlines(CRUIN,CRUOUT,CRUCLK).
When CE becomes active (low), the 5 select lines point
to the CRU bit being accessed (see Table 2). In the
case of a write, the datum is strobed off the CROUT
line by the CRUCLK signal. For a read, the datum is
sent to the CPU on the CRUIN line. The interrupt
control lines consist of an interrupt request line
(INTREQ) and 4 code lines (ICO-IC3). The interrupt
section of the S9901 prioritizes and encodes the highest priority active interrupt into the proper code to
present to the CPU, and outputs this code on the
ICO-IC3 code lines along with an active INTREQ.
Several S9901 's can be used with the CPU by connecting all CR U and address lines in parallel and
providing a unique chip select to each device.

are ANDED with their respective mask bits. If an interrupt input is active (low) and enabled (MASK=l),
the signal is passed through to the priority encoder
where the highest priority signal is encoded into a 4 -bit
binary code as shown in Table 3. The code along with
the interrupt request is then output via the CPU interface on the leading edge of the next ¢ to ensure proper
synchronization to the processor.
The output signals will remain valid until the corresponding interrupt input is removed, the interrupt is
disabled (MASK=O), or a higher priority enabled
interrupt becomes active. When the highest priority
enabled interrupt is removed, the code corresponding
to the next highest priority enabled interrupt is output.
If no enabled interrupt is active, all CPU interface
lines (INTREQ, ICO-IC3) are held high. RST1 (powerup-reset) will force the output code to (0,0,0,0) with
INTREQ held high and will reset all mask bits low
(interrupts disabled). Individual interrupts can be subsequently enabled (disabled) by programming the
appropriate command bits. Unused interrupt inputs
may be used as datum inputs by disabling the interrupt
(MASK=O).
Input/Output

System Interface

The system interface consists of 22 pins divided into
3 groups. The 6 pins in Group 1 (INT1-INT6) are normally dedicated to interrupt inputs (active low), but
may also be used as input ports (true data in). Group 2
(INT7/P15-INT15/P7) consists of 9 pins which can
be individually programmed as interrupt inputs (active
low), inpltt ~orts (true data in), or output ports (true
data out). The remaining 7 pins which comprise Group
3 (PO-P6) are dedicated as individually programmable
I/O ports (true data).

Interrupt Control

A block diagram of the interrupt control section is
shown in Figure 4. The interrupt inputs (6 dedicated,
9 programmable) are sampled by ¢ (active low) and

A block diagram of the I/O section is shown in Figure 5.
Up to 16 individually controlled I/O ports are available
(7 dedicated, 9 programmable). RST1 or RST2 (a
command bit) will program all ports to the input mode.
Writing a datum to any port will program that port to
the output mode and latch out the datum. The port
will then remain in the output mode until either RST1
or RST2 is executed. Data present on the Group 2
pins can be read by either the Read Interrupt Commands or the Read Input Commands. Group 2 pins
being used as input ports should have their respective
Interrupt Mask values reset (low) to prevent false interrupts from occurring. In applications where Group 1
pins are not required as interrupt inputs, they may be
used as input ports and read using the Read Input
commands. As with Group 2 ports, any pins being
used as input ports should have their respective Interrupt Masks disabled.

5.37

89901

Table 2. CRU Bit Assignments

CRU Bit

CRU Read Data

CRU Write Data

0
1
2
3
4
5
6
7
8
9
10

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

CONTROL BIT(I)
INTl/CLK1(2)
INT2/CLK2
INT3/CLK3
INT4/CLK4
INT5/CLK5
INT6/CLK6
INT7/CLK7
INT8/CLK8
INT9/CLK9
INTI0/CLKI0
INTll/CLKll
INTI2/CLKI2
INTI3/CLKI3
INTI4/CLKI4
INTI5/INTREQ
PO INPUT(5)
PI Input
P2 Input
P3 Input
P4 Input
P5 Input
P6 Input
P7 Input
P8 Input
P9 Input
PI0 Input
Pll Input
P12 Input
P13 Input
P14 Input
P15 Input

CONTROL BIT(I)
Mask I/CLKl(3)
Mask 2/CLK2
Mask 3/CLK3
Mask 4/CLK4
Mask 5/CLK5
Mask 6/CLK6
Mask 7/CLK7
Mask 8/CLK8
Mask 9/CLK9
Mask 10/CLKI0
Mask II/CLKll
Mask 12/CLK12
Mask 13/CLK13
Mask 14/CLK14
Mask 15/R8T2(4)
PO Output(6)
PI Output
P2 Output
P3 Output
P4 Output
P5 Output
P6 Output
P7 Output
P8 Output
P9 Output
PI0 Output
PII0utput
P12 Output
P13 Output
P14 Output
P15 Output

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

NOTES: (1)
(2)
(3)
(4)
(5)
(6)

0 = Interrupt Mode 1 = Clock Mode
Data present on INT input pin (or clock value) will be read regardless of mask value.
While in the Interrupt Mode (Control Bit = 0) writing a "I" into mask will enable interrupt; a "0" will disable.
Writing a zero to bit 15 while in the clock mode (Control Bit = 1) executes a software reset of the 1/0 pins.
Data present on the pin will be read. Output data can be read without affecting the data.
Writing data to the port will program the port to the output mode and output the data.

5.38

59901

Figure 4. Interrupt Control Logic

ICO

PRIORITIZER
ANO
ENCOOER

ICI

INTERRUPT INPUTS
(15MAX)

IC2

IC3

¢!

CRU
INTERFACE

CRU LOGIC

,r-------,

Table 3 Interrupt Code Generation

Interrupt/State

Priority

INTI
INT2
INT3/CLOCK
INT4
INT5
INT6
INT7
INT8
INT9
INTI0
INT11
INT12
INT13
INT14
INT15
NOINTERRRUPT

1 (HIGHEST)
2
3
4
5
6
7
8
9
10
11
12
13
14
15 (LOWEST)
-

ICO

ICI

IC2

IC3

INTREQ

0
0
0
0
0

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1

0
1
1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
0
0
0
0

()

0
1
1
1
1
1
1
1
1
1
5.39

1
1
1

1
1

0
0
0

59901

Programmable Real Time Clock

A block diagram of the programmable real time clock
section is shown in Figure 6. The clock consists of a
14- bit counter that decrements at a rate of F(¢ )/64
(at 3MHz this results in a maximum interval of 349ms
with a resolution of 21.3MS) and can be used as either
an interval timer or as an event timer.
The clock is accessed by writing a one into the control
bit (address 0) to force CRU bits 1-15 to clock mode.
(See Table 1.) Writing a nonzero value into the clock
register then enables the clock and sets its frequency.
During system set up this entire operation can be accomplished with one additional I/O instruction (LCDR)
as shown in Table 4. The clock functions as an interval
timer by decrementing to zero, issuing an interrupt,
and restarting at the programmed start value. When
the clock interrupt is active, the clock mask (mask bit
3) must be written into (with either a "1" or a "0")
to clear the interrupt.
If a value other than that initially programmed is re-

quired, a new 14 -bit clock start value is similarly programmed by executing a CRU write operation to the
same locations. During programming the decrementer

is restarted with the current start value after each start
value bit is written. A timer restart can be easily implemented by writing a single bit to any of the clock bits.
The clock is disabled by RST1 (power-up-clear) or
by writing a zero value into the clock register. Enabling the clock programs the third priority interrupt
(INT3) as the clock interrupt and disables generation
of interrupts from the INT3 input pin. When accessing
the clock all interrupts should be disabled to ensure
that system integrity is maintained.
The clock can also function as an event timer since
whenever the device is switched to the clock mode, by
writing a one to the control bit, the current value of
the clock is stored in the clock read register. Reading
this value, and thus the elapsed event time, is accomplished by executing a 14-bit CRU read operation
(addresses 1-14). The software example (Table 3)
shows a read of the event timer.
The current status of the machine can always be obtained by reading the control (address zero) bit. A "0"
indicates the machine is in an interrupt mode. Bits 1

Figure 5. I/O Interface

CRU
INTERFACE

CRU
lOGIC

I/O PORTS
(PO·P15 MAX)

5.40

59901

through 15 would normally be the interrupt input
lines in this mode, but if any are not needed for interrupts they may also be read with a CRU input command and interpreted as normal data inputs. A "1"
read on the control bit indicates that the 9901 is in
the clock mode. Reading bits 1 through 14 completes
the event timer operation as described above. Reading

bit 15 indicates whether the interrupt request line
is active.
A software reset RST2 can be performed by writing a
"1" to the control bit followed by writing a "1" to
bit 15, which forces all I/O ports to the input mode.

Table 4 Software Examples

Assumptions
- System uses clock at maximum interval
- Total of 6 interrupts are used
- 8 bits are used as output port
System
Setup for
Interrupt
System
Setup for
Output
Ports
Read
Programmed
Inputs

LI
LDCR
LDCR

- 8 bits are used as input port
- RST1 (power up reset) has already been applied

R12,PSIBAS
@X,O
@Y,7

Setup CRU Ba,se Address to point 9901
Program Clock with maximum interval
Re-enter interrupt mode and enable top 6 interrupts

R12,PSIBAS+ 16
R1,8

Move CRU Base to point 110 port
Move most significant byte of Rl to output port

R12,PSIBAS+ 24
R2,8

Move CRU Base to point to input ports
Move input port to most significant byte of R2

LDCR

STCR

(X)

•

(Y)

.7FXX

FFFF

Don't cares
BLWP

CLKVCT

Save Interrupt Mask

0
R12,PSIBAS+ 1
-1
R4,14
-1

Disable INTERRUPTS
Set up CRU Base
Set 9901 into Clock Mode, Latch Clock Value
Store Read Register Latch Value into R4
Reenter Interrupt Mode and Restarting Clock
Restore Interrupt Mask

•
•
CLKPC

LIMI
LI
SBO
STCR
SBZ
RTWP
0

•
•
CLKVCT

DATA

CLKWP, CLKPC
5.41

59901

Figure 6. Real Time Clock

CLOCK REGISTER

CRU
INTERFACE

CRU
LOGIC

DEC=O

System Operation
During power up RST1 must be activated (low) for a
minimum of 2 clock cycles to force the S9901 into a
known state. RST1 will disable all interrupts, disable
the clock, program all I/O ports to the mode, and force
ICO-IC3 to (0,0,0,0) with INTREQ held high. System
software must then enable the proper interrupts, program the clock (if used), and configure the I/O ports
as required (see Table 4 for an example). After initial
power up, the S9901 will be accessed only as needed
to service the clock, enable (disable) interrupts, or

CLOCK
INTERRUPT

read (write) data to the I/O ports. The I/O ports can
be reconfigured by use of the RST2 command bit.
Figure 7 illustrates the use of an S9901 with an S9900.
The S9904 is used to generate RST to reset the 9900
and the 9901 (connected to RST1). Figure 8 shows
an S9980 system using the S9901. The reset function,
load interrupt, and 4 maskable interrupts allowed in a
9980 are encoded as shown in Table 5. Connecting
the system as shown ensures that the.proper reset will
be applied to the 9980.

Table 5 9980 Interrupt Level Data

Interrupt
Code
(ICO-IC2)

Function

110
1 o1
100
011
001
010
000
111

Level 4
Level 3
Level 2
Levell
Reset
Load
Reset
No-Op

Vector Location
(Memory Address
In Hex)

Device Assignment

001 0
0 C
000 8
o 004
000 0
3 F F C
o0 0 0

External Device
External Device
External Device
External Device
Reset Stimulus
Load Stimulus
Reset Stimulus

5.42

Interrupt Mask Values
To Enable
(ST12 through ST15)
4 Through F
3 Through F
2 Through F
1 Through F
Don't Care
Don't Care
Don't Care
Don't Care

59901

89901 40 Pin Ceramic Package

Figure 7. 89900-89901 Interface

CROUT

TMS
99BO

(;

IC1·IC3

ICO·IC2

CE_
"-

AB·A12

SYSTEM
NTERRUPT

K=I

TMS
9901

MARKINGS
ON LID
SURFACE
ONLY

SO·S4

CRUIN
A131CRUOUTI
CRUCLK

1/0 PORTS

0.100
j

0.020
0.015

iiS'fi

VCC

0.595
0.575
0.610

0.590

1 1
89901 40 Pin Plastic Package

Figure 8. 89980-89901 Interface
iImmI

PIN 1 IDENTIFIER \

l/L-

ICO·IC3

CE_
Al0·A14

S9900

CRUIN

SO·S4

l/L-

CRUOUT

iiS'fi

2.040'MAX

1/0 PORTS

0. 050

---.l

5Jj
RST
VCC

-l

0020MIN----.j1

0.090 MIN

,I--!TIM
9904

S9901

CRUCLK
01-4>4

SYSTEM
INTERRUPTS

o 200 MAX

Lg~~g J

1---°610

0590

1---.1

END
B

/R\JlOOlO

15 MAX) ~

5.43

ADVANCED PRODUCT DESCRIPTION

S9902
Asynchronous Communications
Controller (ACC)
Features

General Description

•
•
•
•
•

The S9902 Asynchronous Communication Controller
(ACC) is a peripheral device for the S9900 family
of microprocessors. The ACC provides an interface
between the microprocessor and a serial asynchronous
communication channel, performing the timing
and data serialization and deserialization, thus facilitating the control of the asynchronous channel by the
microprocessor.

5 - to 8 -Bit Character Length
1, 1 1/2, or 2 Stop Bits
Even, Odd, or No Parity
Fully Programmable Data Rate Generation
Interval Timer with Resolution from 64 to
16,320/1s
• Fully TTL Compatible, Including Single
Power Supply.

Figure 2. Pin Configuration

Figure 1. Block Diagram

DSR

lNf
XOUT

RIN

SO-84

CRUIN

CRUOUT
CRUCLK
CRUIN

Vcc
c£

CPU
I/F
RIN

INT

CTS
RTS

XOUT

5.44

CRUCLK

RTS

DSR

CRUOUT

vss

59902

S9902 Electrical Specifications

Absolute Maximum Ratings Over Operating Free Air Temperature Range (Unless Otherwise Noted)*
Supply Voltage, Vec ........................................................ -0.3V to +10V
All Inputs and Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V to + 10V
Continuous Power Dissipation ......................................................... 0.7W
Operating Free-Air Temperature Range .......................................... O°C to +70°C
Storage Temperature Range ................................................ - 65° C to + 150° C
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended
Operating Conditions" section of this specification is not implied. Exposure to Absolute Maximum Rated conditions for extended
periods may affect device' reliability.

Recommended Operating Conditions
Parameter
Supply Voltage, V cc

Min.

Nom.

Max.

Unit

4.75

5.25

2.2

2.4

VCC

0.4

0.8

V
°C

Supply Voltage, V SS

High-Level Input Voltage, Vm
Low-Level Input Voltage, VIL
Operating Free-Air Temperature, TA

Electrical Characteristics Over Full Range of Recommended Operating Conditions (Unless Otherwise Noted)
Symbol

Parameter

Input Current (Any Input)

VOH

High-Level Output Voltage

Min.

Typ.

2.2

3.0

2.0

2.5

Max.

Unit

Conditions

±10

j1A

= OV to Vcc
IOH = -100j1A
IOH = - 400j1A
IOL = 3.2mA
tc(-----_

OUTPUT

Device Operation

Clock Input

Control and Data Output

The clock input to the ACC (¢) is normally provided
by the ([3 output of the clock generator (9900 systems) or the S9980 (9980 systems). This clock input
is used to generate the internal device clock, which
provides the time base for the transmitter, receiver,
and in.terval timer of the ACC.

Data and control information is transferred to the
ACe using CE, SO-S4, CRUOUT, and CRUCLK. The
diagrams below show the connection of the ACC to
the S9900 and S9980 CPUs. The high-order CPU
address lines are used to decode the CE signal when
the device is being selected. The low-order address
lines are connected to the five address -select lines
(SO-S4). Table 2 describes the output bit address
assignments for the ACC.
5.49

S9902

Connection of the ACC to the S9900

S9900

809902

o3TTl FROM CLOCK GENERATOR

CRUCLK

CRUCLK
CRUOUT

CRUOUT

CRUIN

AID

SO
Sl

All

A12

A14

J
1

DECODE

J<=

AO·A9

Connection of the ACC to the S9980 CPU's

S9980

S9902

CRUCLK

CRUCLK
CRUOUT

A13

CRUIN

AID

All

A12

l::J<=
5.50

AO·A7

S9902

Table 2 S9902 ACC Output Bit Address Assignments

Address2
SI S2 S3 S4

0
0

1
1
1
1

0
0
0
0

0
0
0

1
1
0

0
1

0
0

1
1

0
0

1
1

1
1
1
0

1
0
0
1

Addressl0

Name

31
30-22

RESET

1
0

DSCENB

TIMENB

Timer Interrupt Enable

XBIENB
RIENB
BRKON

Transmitter Interrupt Enable

0
1
0

19
18
17
16

1
0
1
0

15
14
13
12

11
10-0

RTSON
TSTMD
LDCTRL
LDIR
LRDR
LXDR

Description
Reset device.
Not used.
Data Set Status Change Interrupt Enable.

Receiver Interrupt Enable
Break On
Request to Send On
Test Mode
Load Control Register
Load Interval Register
Load Receiver Data Rate Register
Load Transmit Data Rate Register
Control, Interval, Receive Data Rate, Transmit Data
Rate, and Transmit Buffer Registers

Bit 31 (RESET) -

Writing a one or zero to Bit 31 causes the device to be reset, disabling all interrupts, initializing the transmitter and receiver, setting RTS inactive (high), setting all register load
control flags (LDCTRL, LDIR, LRDR, and LXDR) to a logic one level, and resetting
the BREAK flag. No other input or output operations should be performed for 11¢" clock
cycles after issuing the RESET command.

Bit 30-Bit 22 -

Not used.

Bit 21 (DSCENB) -

Data Set Change Interrupt Enable. Writing a one to Bit 21 causes the INT output to be
active (low) whenever DSCH (Data Set Status Change) is a logic one. Writing a zero to
Bit 21 causes DSCH interrupts to be disabled. Writing either a one or zero to Bit 21
causes DSCH to be reset.

Bit 20 (TIMENB) -

Timer Interrupt Enable. Writing a one to Bit 20 causes the INT output to be active
whenever TIMELP (Timer Elapsed) is a logic one. Writing a zero to Bit 20 causes TIMELP
interrupts to be disabled. Writing either a one or zero to Bit 20 causes TIMELP and
TIMERR (Timer Error) to be reset.

Bit 19 (XBIENB) -

Transmit Buffer Interrupt Enable. Writing a one to Bit 19 causes the INT output to be
active whenever XBRE (Transmit Buffer Register Empty) is a logic one. Writing a zero
to Bit 19 causes XBRE interrupts to be disabled. The state of XBRE is not affected by
writing to Bit 19.

Bit 18 (RIENB) -

Receiver Interrupt Enable. Writing a one to Bit 18 causes the INT output to be active
whenever RBRL (Receiver Buffer Register Loaded) is a logic one. Writing a zero to Bit
18 disables RBRL interrupts. Writing either a one or zero to Bit 18 causes RBRL to be
reset.
5.51

S9902

Bit 17 (BRKON) -

Break On. Writing a one to Bit 17 causes the XOUT (Transmitter Serial Data Output)
to go to a logic zero whenever the transmitter is active and the Transmit Buffer Register
(XBR) and the Transmit Shift Register (XSR) are empty. While BRKON is set, loading
of characters into the XBR is inhibited. Writing a zero to Bit 17 causesBRKON to be
reset and the transmitter to resume normal operation.

Bit 16 (RTSON) -

Request-to-Send On. Writing a one to Bit 16 causes the RTS output to be active (low).
Writing a zero to Bit 16 causes RTS to go to a logic one after the XSR and XBR are
empty, and BRKON is reset. Thus, the RTS output does not become inactive (high)
until after character transmission has been completed.

Bit 15 (TSTMD)-

Test Mode. Writing a one to Bit 15 causes RTS to be internally connected to CTS, XOUT
to be internally connected to RIN, DSR to be internally held low, and the Interval
Timer to operate at 32 times its normal rate. Writing a zero to Bit 15 re-enables normal
device operation.

Bits 14-11 -

Register Load Control Flags. Output Bits 14-11 control which of the five registers will
be loaded by writing to Bits 10-0. The flags are prioritized as shown in Table 3.

Table 3 S9902 ACC Register Load Selection

LDCTRL

LDIR

LRDR

Control Register

Interval Register

Receive Data Rate Register

Transmit Data Rate Register

Transmit Buffer Register

Bit 14 (LDCTRL) -

Load Control Register. Writing a one to Bit 14 causes LDCTRL to be set to a logic
one. When LDCTRL = 1, any data written to bits 0-7 are directed to the Control Register. Note that LDCTRL is also set to a logic one when a one or zero is written to Bit
31 (RESET). Writing a zero to Bit 14 causes LDCTRL to be reset to a logic zero, disabling loading of the Control Register. LDCTRL is also automatically reset to a logic
zero when a datum is written to Bit 7 of the Control Register which normally occurs as
the last bit written when loading the Control Register with a LDCR instruction.

Bit 13 (LDIR) -

Load Interval Register. Writing a one to Bit 13 causes LDIR to be set to a logic one.
When LDIR = 1 and LDCTRL = 0, any data written to Bits 0-7 are directed to the Interval Register. Note that LDIR is also set to a logic one when a datum is written to Bit
31 (RESET); however, Interval Register loading is not enabled until LDCTRL is set to
a logic zero. Writing a zero to Bit 13 causes LDIR to be reset to logic zero, disabling
loading of the Internal Register. LDIR is also automatically reset to logic zero when a
datum is written to Bit 7 of the Interval Register, which normally occurs as the last bit
written when loading the Interval Register with a LDCR instruction.

Bit 12 (LRDR) -

Load Receive Data Rate Register. Writing a one to Bit 12 causes LRDR to be set to a
logic one. When LRDR = 1, LDIR = 0, and LDCTRL = 0, any data written to Bits 0-10
are directed to the Receive Data Rate Register. Note that LRDR is also set to a logic
one when a datum is written to Bit 31 (RESET); however, Receive Data Rate Register
loading is not enabled until LDCTRL and LDIR have been set to a logic zero. Writing a
zero to Bit 12 causes LRDR to be reset to a logic zero, disabling loading of the Receive
Data Rate Register. LRDR is also automatically reset to logic zero when a datum is
written to Bit 10 of the Receive Data Rate Register, which normally occurs as the last
bit written when loading the Receive Data Rate Register with a LDCR instruction.
5.52

59902

Bit 11 (LXDR)-

Load Transmit Data Rate Register. Writing a one to Bit 11 causes LXDR to be set to a
logic one. When LXDR = 1, LDIR = 0, and LDCTRL = 0, any data written to Bits 0-10
are directed to the Transmit Data Rate Register. Note that loading of both the Receive
and Transmit Data Rate Registers is enabled when LDCTRL = 0, LDIR = 0, LRDR = 1,
and LXDR = 1; thus these two registers may be loaded simultaneously when data are
received and transmitted at the same rate. LXDR is also set to a logic one when a datum
is written to Bit 31 (RESET); however, Transmit Data Rate Register loading is not enabled until LDCTRL and LDIR have been reset to logic zero. Writing a zero to Bit 11
causes LXDR to be reset to logic zero, disabling loading of the Transmit Data Rate Register. Since Bit 11 is the next bit addressed after loading the Transmit Data Rate Register, the register may be loaded and the LXDR flag reset with a single LDCR instruction where 12 bits (Bits 0-11) are written, with a zero written to Bit 11.

Control Register

The Control Register is loaded to select character length; device clock operation, parity, and the number of
stop bits for the transmitter. Table 4 shows the bit address assignments for the Control Register.
Table 4 Control Register Bit Address Assignments

Addressl0

Name

SBSI

SBS2

Description

Stop Bit Select

PENB

Parity Enable

PODD

Odd Parity Select

CLK4M

¢ Input Divide Select

Not Used

RCLI

RCLO

}

Character Length Select

SBSI

SBS2

PENB

PODD

CLK4M

NOT USED

RCLI

RCLO

MSB
Bits 7 and 6
(SBSI and SBS2) -

LSB

Stop Bit Selection. The number of stop bits to be appended to each transmitter character
is selected by Bits 7 and 6 of the Control Register as shown below. The receiver only
tests for a single stop bit, regardless of the status of Bits 7 and 6.
SBSI
Bit 7

SBS2
Bit 6

Number of Transmitted
Stop Bits

a
a

Stop Bit Selection
5.53

S9902

Bits 5 and 4
PENB and PODD) -

Parity Selection. The type of parity to be generated for transmission and detected for
reception is selected by Bits 5 and 4 of the Control Register as shown below. When parity
is enabled (PENB = 1), the parity bit is transmitted and received in addition to the
number of bits selected for the character length. Odd parity is such that the total number
of ones in the character and parity bit, exclusive of stop bit(s), will be odd. For even
parity, the total number of ones will be even.
PENB PODD
Bit 5
Bit 4

PARITY

0
0

0
1

None
None

Even

Odd
Parity Selection

Bit 3 (CLK4M) -

¢ Input Divide Select. The ¢ input to the S9902 ACC is used to generate internal dynamic logic clocking and to establish the time base for the Interval Timer, Transmitter,
and Receiver. The if> input is internally divided by either 3 or 4 to generate the two-phase
internal clocks required for MaS logic, and to establish the basic internal operating frequency (fint) and internal clock period (tint). When Bit 3 of the Control Register is set
to a logic one (CLK4M = 1), ¢ is internally divided by 4, and when CLK4M = 0, ¢ is
divided by 3. For example, when f¢ = 3 MHz, as in a standard 3 MHz S9900 system,
and CLK4M = 0,1> is internally divided by 3 to generate an internal clock period tint of
1J1s. The figure below shows the operation of the internal clock divider circuitry. The
internal clock frequency should be no greater than 1. 1 MHz; thus, when fep > 3.3
MHz, CLK4M should be set to a logic one.

(jj External Input

-7

n=4 if CLK4m=1

¢>1 int

{ n=3 if CLK4m=0

¢>2 int

Internal Clock Divider Circuitry
Bits 1 and 0
(RCL1 and RCLO) -

to internal logic
}

fint=~
n
I
n
tint = fint = f¢j

Character Length Select. The number of data bits in each transmitted and received
character is determined by Bits 1 and 0 of the Control Register as shown below.
RCL1
Bit 1

RCLO
Bit 0

Character
Length

5 Bits

6 Bits

7 Bits

8 Bits

Character Length Selection
5.54

S9902

Interval Register

The Interval Register is enabled for loading whenever LDCTRL = 0 and LDIR = 1. The Interval Register is
used for selecting the rate at which interrupts are generated by the Interval Timer of the ACC. The figure
below shows the bit address assignments for the Interval Register when enabled for loading.

TMR5

TMR4

TMR3

TMR2

TMR1

TMRO

I TMR6

TMR7
MSB

LSB
Interval Register Bit Address Assignments

The figure below illustrates the establishment of the interval for the Interval Timer. As an example, if the Interval
Register is loaded with a value of 8016 (12810) the interval at which Timer Interrupts are generated is tITVL =
tint· 64 0 M = (llls) (. 64) (. 128) = 8.192 ms. when tint = 11ls.

.1- I
I l

signal

input to the ACC is a 3MHz signal. The ACC
will divide this signal frequency by 3 to generate an
internal clock frequency of 1MHz. An interrupt will
be generated by the Interval Timer every 1.6 milliseconds when timer interrupts are enabled. The transmitter will operate at a data rate of 300 bits per second
and the receiver will operate at 1200 bits per second.

LI
SBO
LDCR
LDCR
LDCR
LDCR

R12, >40
31
@CNTRL, 8
@INTVL, 8
@RDR, 11
@XDR, 12

Had it been desired that both the transmitter and
receiver operate at 300- bits per second, the "LDCR
@RDR,11" instruction would have been deleted, and
the "LDCR @XDR,12" instruction would have
caused both data rate registers to be loaded and LRDR
and LXDR to have been reset.
Initialization Program
The initialization program for the configuration previously described is as shown below. The RESET
command disables all interrupts, initializes all controllers, sets the four register load control flags
(LDCTRL, LDIR, LRDR, and LXDR). Loading the
last bits of each of the registers causes the load control
flag to be automatically reset.

INITIALI ZE CR U BASE
RESET COMMAND
LOAD CONTROL AND RESET LDCTRL
LOAD INTERVAL AND RESET LDIR
LOAD RDR AND RESET LRDR
LOAD XDR AND RESET LXDR

•
CNTRL
INTVL
RDR
XDR

•

BYTE
BYTE
DATA
DATA

>A2
1600/64

>1A1
>4DO

The RESET command initializes all subcontrollers,
disables interrupts, and sets LDCTRL, LDIR, LRDR,
and LXDR, enabling loading of the control register.
Control Register
The options described previously are selected by loading the value shown below.

SBSI I SBS21 PENB I

PODDICLK~I

MSB

LSB

VALUE

I..

'lO A1

~L _'

, ' L' ':T :HA:::"

.;; DI VI DE-BY-3
EVEN PARITY
1 STOP BIT

5.64

59902

Interval Register

The interval register is to be set up to generate an interrupt every 1.6 milliseconds. The value loaded into the
interval register specifies the number of 64 microsecond increments in the total interval.

25 X 64 MICROSECONDS = 1.6 MI LLiSECONDS

Receive Data Rate Register

The data rate for the receiver is to be 1200 bits per second. The value to be loaded into the Receive Data Rate
Register is as shown:

~~--------------~--------------~

SRDVS= 1

106 -;-1 -;-417 -;- 2 = 1199.04 BITS PER SECOND

Transmit Data Rate Register

The data rate for the transmitter is to be 300 bits per second. The value to be loaded into the Transmit Data
Rate Register is:
9

~-------------------y.------------------~

DOI6= 20S

SXDVS = S
1 X 106 -;-S-;-208-;-2= 300.48 BITS PER SECOND

5.65

89902

Data Transmission
The subroutine shown below demonstrates a simple loop for the transmitting of a block of data.

XMTLP

LI
LI
LI
SBO
TB
JNE
LDCR
DEC
JNE
SBZ

RO, LISTAD
Rl, COUNT
R12, CRUBAS
16
22
XMTLP
*RO+,8
Rl
XMTLP
16

INITIALIZE LIST POINTER
INITIALIZE BLOCK COUNT
INITIALIZE CRU BASE
TURN OFF TRANSMITTER
WAIT FOR XBRE = 1
LOAD CHARACTER INCREMENT POINTER RESET XBRE
DECREMENT COUNT
LOOP IF NOT COMPLETE
TURN OFF TRANSMITTER·

After initializing the list pointer, block count, and CRU base address. RTSON is set to cause the transmitter
and the RTS output to become active. Data transmission does not begin, however, until the CTS input becomes
active. After the final character is loaded into the transmit buffer register, RTSON is reset. The transmitter
and the RTS output do not become inactive until the final character has been completely transmitted.

Data Reception
The software shown below will cause a block of data to be received and stored in memory.
CARRET
RCVBLK
RCVLP

RCVEND

BYTE
LI
LI
LI
TB
JNE
STCR
SBZ
DEC
JEQ
CB
JNE
RT

>OD
'R2, RCVLST
R3, MXRCNT
R4, CAR RET
21
RCVLP
*R2,8
18
R3
RCVEND
*R2+, R4
RCVLP

INITIALIZE LIST COUNT
INITIALIZE MAX COUNT
SET UP END OF BLOCK CHARACTER
WAIT FOR RBRL = 1
STORE CHARACTER
RESET RBRL
DECREMENT COUNT
END IF COUNT = 0
COMP ARE TO EOB CHARACTER, INCREMENT POINTER
LOOP IF NOT COMPLETE
END OF SUBROUTINE

Register Loading After Initialization
The control, interval, and data rate registers may be reloaded after initialization. For example, it may be desirable to change the interval of the timer. Assume, for sample, that the interval is to be changed to 10.24
milliseconds. The instruction sequence is as follows:
SBO
LDCR

INTVL2

•
•
•

BYTE

13
@INTVL2,8

SET LOAD CONTROL FLAG
LOAD REGISTER, RESET FLAG

10240/64
5.66

S9902

Caution should be exercised when transmitter interrupts are enabled to ensure that the transmitter interrupt
does not occur while the load control flag is set. For example, if the transmitter interrupts between execution
of the "SBO 13" and the next instruction, the transmit buffer is not enabled for loading when the transmitter
interrupt service routine is entered because the LDIR flag is set. This situation may be avoided by the following sequence:
BLWP

lTV CPC

•
•
•

LI MI
MOV

SBO
LDCR
RTWP

ITVCHG
INTVL2

•
•
•

DATA
BYTE

@INTVCHG

CALL SUBROUTINE

MASK ALL INTERRUPTS
LOAD CRU BASE ADDRESS
SET FLAG
LOAD REGISTER AND RESET FLAG
RESTORE MASK AND RETURN

@24(RI3), RIZ
13
@INTVL2,8

ACCWP, ITVCPC
10240/64

In this case all interrupts are masked, ensuring that all interrupts are disabled while the load control flag is set.
Mechanical Data
l8-Pin Plastic Dual-in-Line Package

l8-Pin Ceramic Dual-in-Line Package

PIN I IDENTIFIER]

MARKINGS
ON LID
SURFACE
ONLY

0.930~AX

0.085 TYP
0.040

r----,

Ir---,I

,..."JEJ'
I-

5.67

0.310
G.290

0.'"
H.OOB

ADVANCED PRODUCT DESCRIPTION

S9903
SYNCHRONOUS
COMMUNICATIONS CONTROLLER
Features

General Description

Versatile CRU interface to synchronous and
asynchronous serial devices for the S99XX
series of microprocessors
D DC to 250 KBPS data rate, half- or fullduplex
o Dynamic character length selection
o Line protocols include BI-SYNC, SDLC, and
HDLC, as well as others
o Programmable-polynominal CRC generation
and detection
o Interface to unclocked or NRZI data with 32x
clocks
o Two programmable sync registers
o Interval timer 164Jls to 16.32msl on chip
D Automatic zero insert and delete for SDLC
and HDLC
D Single + 5V supply, 20-pin DIP, all inputs
and outputs TTL compatible
o N ·channel Silicon-Gate technology

The 89903 is a versatile device which provides the
system designer with a wide range of capabilities in
synchronous and asynchronous communications control.
The 89903 operates in a multi-mode configuration that
allows a broad range in the degree of active participation required in the control of high~speed serial communications. Most synchronous data-link control protocols can be supported through software control of
sync and fill characters, timing, CRC generation and
detection, etc. Established protocols such as BI-8YNC,
8DLC, and HDLC are implemented directly in hardware, with others implemented through various combinations of hardware and software.
Universal applicability is further assured through the
capability for dynamic character length selection from
5- to 9-bit data words plus parity. Definition and operation of all communications control is under software
control and as such make upgrading to another protocol simply a matter of changing software with no
hardware changes required.

Block Diagram

Pin Configuration

I---~-

ffi

iNT
XOUT

CRUCLK
CRUOUT
CRUIN

RIN

TRANSMIT
CONTROL

CRUIN

9900
IfF

5.68

CE
;)

CRUCLK

ill

ffi

DSR

CRUOUT

V'"

SCT

5CR

iNT
RECEIVE
CONTROL

Vee

ADVANCED PRODUCT DESCRIPTION

S9940

MICROPROCESSOR
General Description

Features
D
D
D
D
D
D
D
D

D
D
D

The 89940 is a single-chip, 16-bit microcomputer containing 01 CPU, memory (RAM and ROM), and extensive 110. The instruction set of the 89940 is a subset of
the 89900 instruction set and includes capabilities offered by minicomputers. The unique memory-to-memory
architecture features mUltiple register files, resident
in the RAM, which allow faster response to interrupts,
and increased programming flexibility. The memory
consists of 128 bytes of RAM and 2048 bytes of ROM.
The 89940 implements four levels of interrupts, including an internal decrementer which can be programmed as a timer or an event counter. All members
of the 89900 family of peripheral circuits are compatible with the 89940.

16-Bit Instruction Word
Minicomputer Instruction Set Including
Multiply and Divide
2048 Bytes of ROM on Chip
128 Bytes of RAM on Chip
16 General Purpose Registers
4 Prioritized Interrupts
On Chip Timer/Event Counter
32 Bits General Purpose I/O
256 Bits I/O Expansion
Multiprocessor System Interface
Single 5 Volt Power Supply
Power Down Capability for Low Stand-by
Power
N-Channel Silicon Gate MOS

Pin Configuration

Block Diagram

CONTROL

MEMORY (ROM/RAM)

I/O PORTS

5.69

ADVANCED PRODUCT DESCRIPTION

S9980A/S9981

16·811 MICROPROCESSOR
Features
o 16-Bit Instruction Word
o Full Minicomputer Instruction 8et Capability
Including Multiply and Divide
o Up to 16,384 Bytes of Memory
o 8-Bit Memory Data Bus
o Advanced Memory-to-Memory Architecture
o Separate Memory, I/O, and Interrupt-Bus 8tructures
o 16 General Registers
o 4 Prioritized Int~rrupts
o Programmed and DMA I/O Capability
DOn-Chip 4-Phase Clock Generator
o 40-Pin Package
ON-Channel 8ilicon-Gate Technology

The 89981 has an optional on-chip crystal oscillator
in addition to the external clock mode of the
89980A.
The pin-outs are not compatible for DO-D7, INTOINT2, and ;j;3.

Description
T,he 89980A/89981 is a software-compatible member of
AMI's 9900 family of microprocessors. Designed to
minimize the system cost for smaller systems, the
S9980A/S9981 is a single-chip 16-bit central processing
unit (CPU) which has an 8-bit data bus, on-chip clock,
and is packaged in a 40-pin package (see Figure 1). The
instruction set of the 89980A/89981 includes the capabilities offered by full minicomputers and is exactly the
The 89980A and the 89981 although very similar, have same as the 9900's. The unique memory-to-memory arseveral differences which are:
chitecture features mUltiple register files, resident in
1. The S9980A requires a VBB supply (pin 21) while memory, which allow faster response to interrupts and
the 89981 has an internal charge pump to generate increased programming flexibility. The separate bus
structure simplifies the system design effort.
V BB from Vee and V DD·
Pin Configuration

Block Diagram

9980A

ADDRESS

INTERRUPT

9981

HOLD

MEMEN

HOLDA

READY

lAO
A13/CRUOUT

CRUCLK

A12

Voo

All

AID

CKIN

OSCOUT

INTO

INTI

INTO

OBiN

INT2

INT 1

INT 2

.,,3

CONTROL

ClOCK---....J

CRU
CRutN

OATA

5.70

6
Telecommunications

Selection Guide

TELECOMMUNICATIONS
PART NO.
S1883
S2350

DESCRIPTION
Universal Asynchronous
Receiver/Transmitter (UART)
Universal Synchronous
Receiver/Transmitter (USRT)

S2559A/B
S2559C/D
S2560AlB
S2561

Digital Tone Generator
Digital Tone Generator
Key Pulser
Tone Ringer

S2562

Repertory Dialer

PROCESS
P-I'

POWER SUPPLIES
-12V, ±5V

INPUT/OUTPUT
TTL

PACKAGES
40 Pin

N·SiGate

+5V

TTL

40 Pin

CMOS
CMOS

+3.5V to +13V
+ 2.75 to + 10V

TTL/CMOS
TTL/CMOS

16 Pin
16 Pin

CMOS
CMOS
CMOS

+12V
+13.5V

6.2

18 Pin
18 Pin
40 Pin

52559A1B/C/D
DIGITAL
TONE GENERATOR
Features

General Description

The S2559 Digital Tone Generator is specifically designed to implement a dual tone telephone dialing
system. The device can interface directly to a standard
pushbutton telephone keyboard or calculator type
X-V keyboard and operates directly from the telephone lines. All necessary dual-tone frequencies are
derived from the widely used TV crystal standard providing very high accuracy and stability. The required
sinusoidal wave:':orm for the individual tones is digitally
synthesized on the chip. The waveform so generated
has very low total harmonic distortion. A voltage reference is generated on the chip which is stable over
the operating voltage and temperature range and regulates the signal levels of the dual tones to meet the
recommended telephone industry specifications.
These features permit the S2559 to be incorporated
with a slight modification of the standard 500 type
telephone basic circuitry to form a pushbutton dualtone telephone. Other applications of the device include radio and mobile telephones, remote control,
Point-of-Sale, and Credit Card Verification Terminals
and process control.

o
o
o
o
o

o
o

Wide Operating Supply Voltage Range: 3.5 to
13 Volts (A, B) 2.75 to 10 Volts (C, D)
Low Power CMOS Circuitry Allows Device
Power to be Derived Directly from the Telephone Lines or from Small Batteries, e.g., 9V.
Uses TV Crystal Standard (3.58MHz to Derive
all Frequencies thus Providing Very High
Accuracy and Stability
MUTE and Transmitter Drivers On Chip
Interfaces Directly to a Standard Telephone
Push-Button or Calculator Type X-Y Keyboard
The Total Harmonic Distortion is Below
Industry Specification
On Chip Generation of a Reference Voltage
to Assure Amplitude Stability of the Dual
Tones Over the Operating Voltage and Temperature Range
Dual Tone as well as Single Tone Capability
Four Options Available:
A: 3.5 to 13V Mode Select
B: 3.5 to 13V Chip Disable
C: 2.75 to 10V Mode Select
D: 2.75 to 10V Chip Disable
Block Diagram

Pin Configuration

VDn

MOSLlCD
Rl
R2

osco

6.3

S2559A1B/C/D

Absolute Maximum Ratings

DC Supply Voltage (VDD - VSS) S2559 A, B ........................................... +13.5V
DC Supply Voltage (VDD - VSS) S2559 C, D ........................................... +10.5V
Operating Temperature ..................................................... -25° C to +70° C
Storage Temperature ...................................................... -55°C to +125°C
Power Dissipation at 25° C .......................................................... 500m W
Input Voltage ....................................................... -0.6 ~ Yin ~ VDD + 0.6
S2559A & B Electrical Characteristics (Specifications apply over the operating temperature range of - 25° C to

+70° C unless otherwise noted. Absolute values of measured parameters are specified.)
(VDD-VSS)
Volts

Symbol

Parameter/Conditions

VDD
VDD

Supply Voltage
Tone Out Mode with One Valid Key Depressed
Non Tone Out Mode (No Keys Depressed)

Units

Supply Current
IDD

Standby (No Keys Selected, Tone, MUTE and
XMIT Outputs Unloaded)

IOD

Operating (One Key Selected, Tone, MUTE and
XMIT Outputs Unloaded)
Tone Output!
Row Tone RL = 600n
Single Tone
Row Tone RL = 320n
Mode, Output
Column Tone RL = 600n
Voltage
Column Tone RL = 320n
Ratio of Column to Row Tone
Distortion (Any Dual Tone)*

VOR
VOC
dBCR
% DIS

VOL

XMIT , MUTE Outputs
XMIT, Output Voltage
IOH = 15mA
High (Pin 2)
IOH = 50rnA
No Key Depressed
MUTE Output Voltage (Pin 10) Low
No Key Depressed, No Load

VOH

One Key Depressed, No Load

IOL

MUTE Output Sink
Current
MUTE Output Source
Current

VOH

IOH

13.0

130

I1A

5.0

rnA

660
600
880
790
3.7
10

mVrms
mVrms
mVrms
mVrms
dB
%

5.0
12.0
5.0
12.0
3.5-13.0
3.5-13.0

490
440
650
590
1.75

3.5
10.0

1.5
8.0

2.85

V
V
0.4
1.0

3.5
13.0
3.5
13.0
3.0
10.0

2.6
10.0
0.2
0.5

V
V
V
V
rnA
rnA

VOH = 2V
VOH = 9V

3.0
10.0

0.5
0.5

rnA
rnA

Sink VIL = 0.5V
Source VIH = 3.0V

3.5
3.5
3.5

0.34
0.23

rnA
rnA
mS

VOL

0.5V

Oscillator
IOH

Output Current

tsu

Startup Time

I
I

Input Currents
Row, Column Inputs,
Pull-up (Source) Current

0.45
3.5
rnA
13.0
1.48
rnA
0.1
3.5
rnA
Pull-down
(Sink)
Current
IlL
0.6
rnA
13.0
*Distortion measured in accordance with the specification described in Ref. 1 as the "ratio of the total power of all extraneous
frequencies in the voiceband above 500Hz accompanying the signal to the total power of the frequency pair."
lAmplitude specification limits apply at room temperature (+25°C) only.
IIH

VIH = 3.0V
VIH = 12.5V
VIL=2.1V
VIL=9.1V

6.0

6.4

S2559A1B/C/D

S2559C & D Electrical Characteristics (Specifications apply over the operating temperature range of _25°C
to +70°C unless otherwise noted. Absolute values of the measured parameters are specified.)
Symbol

Units

Parameter/Conditions
Supply Voltage
Tone Out Mode with Valid Key Depressed
Non Tone Out Mode (No Key Depressed)

Supply Current
Standby (No Key Selected, Tone, XMIT
and MUTE Outputs Unloaded)
IDD

3.0
10.0
3.0
10.0

Operating (One Key Selected, Tone XMIT
and MUTE Outputs Unloaded)

0.3
1.0
1.0
8.0

30
100
2.0
16.0

546
501
731
672
2.54

667
626
889
840
3.75
10

J1A
J1A
rnA
rnA

Tone Output l
VOR
VOC
dBCR
% DIS

Row Tone,
Row Tone,
Column Tone,
Column Tone,
Ratio of Column to Row Tone
Distortion (Any Dual Tone)*

Single Tone
Mode Output
Voltage

RL =
RL =
RL =
RL =

390[2
240n
390[2
240[2

5.0
10.0
5.0
10.0
3.0-10.0
3.0-10.0

424
376
573
504
1.75

3.0
10.0

1.5
8.5

mVrms
mVrms
mVrms
mVrms
dB
%

XMIT, MUTE Outputs
VOH

XMIT, Output Voltage, High
(No Key Depressed) (Pin 2)

(IOH = 15mA)
(IOH = 50mA)

VOH

XMIT, Output Source Leakage Current,
VOF = OV
MUTE (Pin 10) Output Voltage, Low,
(No Key Depressed), No Load
MUTE, Output Voltage, High,
(One Key Depressed), No Load

IOL

MUTE, Output Sink Current

VOL = 0.5V

IOH

MUTE, Output Source
Current

VOH = 2.5V
VOH= 9.5V

2.75
10.0
2.75
10.0
3.0
10.0
3.0
10.0

=
=
=
=

3.0
10.0
3.0
10.0

IOF
VOL

IOL
IOH
IlL
IIH
IlL

Oscillator Input/Output
Output Sink Current
One Key Selected
Output Source Current
One Key Selected
Input Current
Leakage Sink Current,
One Key Selected
Leakage Source Current
One Key Selected
Sink Current
No Key Selected

tSTART

Oscillator Startup Time

CI/O

Input/Output Capacitance

1 Amplitude

VOL
VOL
VOH
VOH

10.0

0.5V
0.5V
2.5V
9.5V

V
V

1.8
8.8

2.25
9.5
0.53
2.0
0.17
0.57

0
0
2.75
10.0
1.3
5.3
0.41
1.5

0.21
0.80
0.13
0.42

0.52
2.1
0.31
1.1

100

J1A

0.5
0.5

V
V
V
V
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA

10.0

1.0

J1A

VIH = O.OV

10.0

1.0

J1A

VIL = 0.5V
VIL = 0.5V

3.0
10.0
2.75
10.0
3.0
10.0

VIL

10.0V

specification limits apply at room temperature (+25 0 C) only.

6.5

47
65

93
130
0.4
0.25
12
10

J1A
J1A
1.2
0.75
16
14

mS
mS
pF
pF

S2559A1B/C/D

S2559C & D Electrical Specifications (continued)

Symbol

ParameterIConditions

Units

Input Currents
IlL
Row &
Column Inputs
IIR

IIR

Mode Select
Input (S2559C)

Chip Disable
Input (S2559D)

IlL

Sink Current,
VIL = 3.0V (Pull-down)
Sink Current,
VIL = 10.0V (Pull-down)
Source Current,
VIH = 2.5V (Pull-up)
Source Current,
VIH = 9.5V (Pull-up)
Source Current,
VIH = O.OV (Pull-up)
Source Current,
VIR = O.OV (Pull-up)
Sink Current,
VIL = 3.0V (Pull-down)
Sink Current,
VIL = 10.0V (Pull-down)

3.0

6.5

J.1A

10.0

9.2

J.1A

3.0

210

J.1A

10.0

280

740

J.1A

3.0

1.4

3.3

J.1A

10.0

J.1A

3.0

3.9

9.5

J.1A

10.0

143

J.1A

*Distortion measured in accordance with the specification described in Ref. 1 as the "ratio of the total power of all extraneous
frequencies in the voiceband above 500Hz accompanying the signal to the total power of the frequency pair."

Table 1. ComparisonsofSpecifiedvs Actual Tone Frequencies
Generated by S2559

OUTPUT FREQUENCY Hz

ACTIVE
INPUT

SPECIFIED

ACTUAL

% ERROR
SEE NOTE

R1
R2
R3
R4
C1
C2
C3
C4

697
770
852
941
1,209
1,336
1,477
1,633

699.1
766.2
847.4
948.0
1,215.9
1,331.7
1,471.9
1,645.0

+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73

Table 2. XMIT and MUTE Output Functional Relationship

NOTE: % Error does not include oscillator drift.

6.6

OUTPUT

'DIGIT' KEY
RELEASED

'DIGIT' KEY
DEPRESSED

COMMENT

XMIT

VOO

High Impedance

Can source at
least 50mA at
10V with 1.5V
max. drop

MUTE

VSS

VOO

Can source or
sink current

S2559A1B/C/D

Circuit Description

Keyboard Interface

The 82559 is designed so that it can be interfaced
easily to the dual tone signaling telephone system and
that it will more than adequately meet the recommended telephone industry specifications regarding
the dual tone signaling scheme.

The 82559 employs a calculator type scanning circuitry to determine key closures. When no key is
depressed, active pull-down resistors are "on" on the
row inputs and active pull-up resistors are "on" on
the column inputs. When a key is pushed a high level
is seen on one of the row inputs, the oscillator starts
and the keyboard scan logic turns on. The active
pull-up or pull-down resistors are selectively switched
on and off as the keyboard scan logic determines
the row and the column inputs that are selected. The
advantage of the scanning technique is that a keyboard
arrangement of 8P8T switches are shown in Figure 2
without the need for a common line, can be used.
Conventional telephone push button keyboards as
shown in Figure 1 or X-Y keyboards with common
can also be used. The common line of these keyboards
can be left unconnected or wired "high."

Design Objectives

The specifications that are important to the design
of the Digital Tone Generator are summarized below:
The dual tone signal consists of linear addition of two
voice frequency signals. One of the two signals is
selected from a group of frequencies called the "low
group" and the other is selected from a group of
frequencies called the "high group." The low group
consists of four frequencies 697, 770, 852 and 941
Hz. The high group consists of four frequencies 1209,
1336, 1477 and 1633Hz. A keyboard arranged in a
row, column format (4 rows x 3 or 4 columns) is
used for number entry. When a push button corresponding to a digit (0 thru 9) is pushed, one appropriate row (R1 thru R4) and one appropriate column
(C1 thru C4) is selected. The active row'input selects
one of the low group frequencies and the active
column input selects oneofthe high group frequencies.
In standard dual tone telephone systems, the highest
high group frequency of 1633Hz (Col. 4) is not used.
The frequency tolerance must be ±1.0%. However,
the 82559 provides a better than. 75% accuracy. The
total harmonic and intermodulation distortion of the
dual tone must be less than 10% as seen at the telephone terminals. (Ref. 1.) The high group to low group
signal amplitude ratio should be 2.0 ±2dB and the
absolute amplitude of the low group and high group
tones must be within the allowed range. (Ref. 1.)
These requirements apply when the telephone is used
over a short loop or long loop and over the operating
temperature range. The design of the 82559 takes
into account these considerations.
Oscillator

The device contains an oscillator circuit with the
necessary parasitic capacitances on chip so that it is
only necessary to connect a 10Mn feedback resistor
and the standard 3.58MHz TV crystal across the Osci
and Osco terminals to implement the oscillator function. The oscillator functions whenever a row input
is activated. The reference frequency is divided by 2
and then drives two sets of programmable dividers,
the high group and the low group.
6.7

Logic Interface

The 82559 can interface with CM08 logic outputs
directly. The 82559 requires active "high" logic levels.
8ince the active pull-up resistors present in the 82559
are fairly low value (500n typ), diodes can be used as
shown in Figure 3 to eliminate excessive sink current
flowing into the logic outputs in their "low" state.

Tone Generation

When a valid key closure is detected, the keyboard
logic programs the high and low group dividers with
appropriate divider ratios so that the output of these
dividers cycle at 16 times the desired high group and
low group frequencies. The outputs of the programmabIe dividers drive two 8-stage Johnson counters.
The symmetry of the clock input to the two divide
by 16 Johnson counters allows 32 equal time segments to be generated within each output cycle. The
32 segments are used to digitally synthesize a stairstep waveform to approximate the sinewave function
(8ee Figure 4.) This is done by connecting a weighted
resistor ladder network between the outputs of the
Johnson counter, VnD and VREF. VREF closely
tracks VDD over the operating voltage and temperature range and therefore the peak to peak amplitude
VP (VDD - VREF) of the stairstep function is fairly
constant. VREF is so chosen that Vp falls within the
allowed range of the high group and low group tones.

•
: ~

S2559A1B/C/D

Figure 1. Standard Telephone Push Button Keyboard

-a-.

r - -

-0- --0---0
I

0---0---0----,

r' ,
~"-I- -~--~--0c
UJ

0.6

:::;
ct

0.5

0.4
0.3
0.2
0.1
(Vref )

0
TIME SEGMENTS

6.9

S2559A1B/C/D

The individual tones generated by the sinewave synthesizer are then linearly added and drive a bipolar NPN
transistor connected as emitter follower to allow
proper impedance transformation, at the same time
preserving signal level.
Dual Tone Mode

When one row and one column is selected dual tone
output consisting of an appropriate low group and
high group tone is generated. If two digit keys, that
are not either in the same row or in the same column,
are depressed, the dual tone mode is disabled and no
output is provided.
Single Tone Mode

Single tones either in the low group or the high group
can be generated as follows. A low group tone can be
generated by activating the appropriate row input or
by depressing two digit keys in the appropriate row.
A high group tone can be generated by depressing
two digit keys in the appropriate column, i.e., selecting the appropriate column input and two row inputs
in that column.
Mode Select

S2559A and S2559C have a Mode Select (MDSL)
input (Pin 15). When MDSL is left floating (unconnected) or connected to VDD, both the dual tone and
single tone modes are available. If MDSL is connected
to VSS, the single tone mode is disabled and no output tone is produced if an attempt for single tone is
made. The S2559B and S2559D do not have the
Mode Select option.
Chip Disable

The S2559B and S2559D have a Chip Disable input
at Pin 15 instead of the Mode Select input. The chip
disable for the S2559B and S2559D is active "high."
When the chip disable is active, the tone output goes
to VSS, the row, column inputs go into a high impedance state, the oscillator is inhibited and the MUTE
and XMIT outputs go into active states. The effect is
the device essentially disconnects from the keyboard.
This allows one keyboard to be shared among several
devices.
Cry~tal

Specification

tone generation application. By relaxing the tolerance
specification the cost of the crystal can be reduced.
The recommended crystal specification is as follows:
Frequency: 3.579545MHz ±0.02%
RS ~ lOOn, LM = 96MHY
CM = 0.02pF Ch = 5pF
MUTE, XMIT Outputs

The S2559 A, B, C, D have a CMOS buffer for the
MUTE output and a bipolar NPN transistor for the
XMIT output. With no keys depressed, the MUTE output is "low" and the XMIT output is in the active
state so that substantial current can be sourced to a
load. When a key is depressed, the MUTE output goes
high, while the XMIT output goes into a high impedance state. When Chip Disable is "high" the MUTE
output is forced "low" and the XMIT output is in
active state regardless of the state of the keyboard
inputs.
Amplitude/Distortion Measurements

Amplitude and distortion are two important parameters in all applications of the Digital Tone Generator. Amplitude depends upon the operating supply
voltage as well as the load resistance connected on
the Tone Output pin. The on-chip reference circuit
is fully operational when the supply voltage equals or
exceeds 5 volts and as a consequence the tone amplitude is regulated in the supply voltage range above
5 volts. The load resistor, value also controls the
amplitude. If RL is low the reflected impedance into
the base of the output transistor is low and the tone
output amplitude is lower. For RL greater than
5Kn the reflected impedance is sufficiently large and
highest amplitude is produced. Individual tone amplitudes can be measured by applying the dual tone signal
to a wave analyzer (H-P type 3581A) and amplitudes
at the selected frequencies can be noted. This measurment also permits verification of the preemphasis
between the individual frequency tones.
Distortion is defined as "the ratio of the total power
of all extraneous frequencies in the voiceband above
500Hz accompanying the signal to the power of the
frequency pair." This ratio must be less than 10% or
when expressed in dB must be lower than -20dB.
(Ref. 1.) Voiceband is conventionally the' frequency
band of 300Hz to 3400Hz. Mathematically distortion
can be expressed as:

A standard television color burst crystal is specified
to have much tighter tolerance than necessary for
6.10

Dist. =

V(Vl)2+(V2)2+ .. +(Vn )2
V(VL)2+(VH)2

S2559A1B/C/D

where (VI) ... (V n ) are extraneous frequency (i.e.,
intermodulation and harmonic) components in the
500Hz to 3400Hz band and VL and VH are the individual frequency components of the DTMF signal. The
expression can be expressed in dB as:

An accurate way of measuring distortion is to plot
a spectrum of the signal by using a spectrum analyzer
(H-P type 3580A) and an X-Y plotter (H-P type
7046A). Individual extraneous and signal frequency
components are then noted and distortion is calculated by using the expression (1) above. Figure 6
shows a spectrum plot of a typical signal obtained
from a S2559D device operating from a fixed supply
of 4Vdc and RL = 10kS1 in the test circuit of Figure
5. Mathematical analysis of the spectrum shows

distortion to be -30dB (3.2%). For quick estimate of
distortion, a rule of thumb as outlined below can
be used.
"As a first approximation distortion in dB equals the
difference between the amplitude (dB) of the extraneous component that has the highest amplitude and
the amplitude (dB) of the low frequency signal."
This rule of thumb would give an estimate of - 28dB
as distortion for the spectrum plot of Figure 6 which
is close to the computed result of -30dB.
In a telephone application amplitude and distortion
are affected by several fadors that are interdependent.
For detailed discussion of the telephone application
and other applications of the 2559 Tone Generator,
refer to the applications note" Applications of Digital
Tone Generator."
Ref. 1:
Bell System Communications Technical
Reference, PUB 47001, "Electrical Characteristics
of Bell System Network Facilities at the Interface
with Voiceband Ancillary and Data Equipment,"
August 1976.

Figure 5. Test Circuit for Distortion Measurement

Voo

TONE
OUT

--w ~

.3...

XMIT

2...

....!.

r-!l

~C3

rE-

r!!-

MUTE

LOWIMPEO_
OC
POWER
SUPPLY

SIG

MOSL

Rl = 1Ok~~

Rl~

SPECTRUM
ANALYZER

X-Y
PLOTTER

H-P
TYPE
358UA

H-P
TYPE
7U46A

V
M

S25590

'--~

3_579545MHl~
CRYSTAL

Vss

OSCi

lUMn

OSC,

C4~

GNO

6.11

X OUT

f::=

X,.

YOUT

f::=

V,N

1
:

S2559A1B/C/D

Figure 6. A Typical Spectrum Plot

.....

VOICEBAND

/
/
/
/
/
/

-5

-10

-15

Vli-4.5J

1/
1/
1/

/
/
/
/

-25 I-

1/
V2i-32J

-4 5

-5 0

V
1/

V'i-48J

/
/
/
/
/

-6 0

-6 51-

V6i-47J

V4i-47J

0.5

1.0

1.5

\
2.0

2.5
FREOUENCY (KHz)

/
/

V3i-44J

-5 5

/
/

VSi-36J

/
/
/
/
/
/

-40

= S2559D
= ROOM
= 4V OC FIXED
= 10kn
= FIG URE 5

1/
1/

-35

Rl
TEST CKT

/
-30 I-

DEVICE
TEMP
(VOO - Vss)

V
V

-20 f-

V_i-1.51

V
/
/

3.0

3.5

I
4.5

5.0

Physical Dimensions
16 Pin Plastic

16 Pin Cer-DIP
PIN 1 IDENTIFIER-

90L~g~~g

,. 0.200 MAX

0"0.0>Y.p~

0.020'
,0.015
I
I
0.070

gg~~ I

olOr~J-~Ixl

r
g~m

0.795
MAX

iii :

t-Ji __U L-tg~~~

0.030

OOOOMIN
0.090 MIN

00651
0040

PIN 1 IDENTIFIER
0.310
0.290

J-0200MAX

",;." rI

"'"
0310

T-J""
,~,

15 0

MAx-//1~J~L\~
'~

6.12

- -0.008
0.012

ADVANCED PRODUCT DESCRIPTION

S2560A/S2560B
KEY PULSER

Features

General Description

Low Voltage CMOS Process for Direct
Operation From Telephone Lines

Inexpensive R-C Oscillator Design Provides
Better than ±5% Accuracy Over Temperature
and Unit to Unit Variations
Dialing Rate Can Be Varied By Changing the
Dial Rate Oscillator Frequency

The S2560 Key Pulser is a CMOS integrated circuit
that converts pushbutton inputs to a series of pulses
suitable for telephone dialing. It is intended as a
replacement for the mechanical telephone dial and
can operate directly from the telephone lines with
minimum interface. Storage is provided for 20 digits,
therefore, the last dialed number is available for
redial until a new number is entered.

o
o
o

o
o

Dial Rate Select Input Allows Changing
of the Dialing Rate by a 2: 1 Factor
Without the Need of Changing Oscillator
Components
Two Selections of Mark/Space Ratios
(33-1/3/66-2/3 or 40/60)
Twenty Digit Memory for Input Buffering
and for Redial With Access Pause Capability
Mute and Dial Pulse Drivers on Chip
Accepts Standard Telephone DPCT Keypad
Arranged in a 2 of 7 Format; Also Capable
of Logic Interface
Ignores Multi Key Entries

Unique Features of S2560A (18 Pin Package)

IDP scaled to the dialing rate such as to produce smaller
IDP at higher dialing rates. Additionally, the IDP can
1)8 changed by a 2:1 factor at a given dialing rate by
means of the IDP select input.
Unique Features of S2560B (24 Pin Package)

Separate IDP oscillator for selecting an IDP independent of the dialing rate. Provision for changing of the
IDP by a 2:1 factor without the need of changing external components.
Alternating pacifier tone output simulates dual tone
effects coincident with each keyboard number entry.

Data subject to change at any time without notice. These sheets transmitted for information only.

Block Diagram

Pin Configuration

PACIFIER
TO N E
OUT
R4
KEYBOARD
INPUTS
C1

C3
HOOK
SWITCH
DIAL
RATE
OSC

I RO

CD
RE

ITP

lOP 1 CI
OSC
RJ

MUTE

DRS

IPS

MIS TEST

6.13

C1
IPS

52560

KEY

DRS

PULSER

13
12

Voo
MIS

MUTE

liP

Vss

C3
C2

PACIFIER TONE

C3
C2
C1

52560

KEY

liP
Vss

7 PULSER

MUTE

MIS

liS

Voo

IPS

DRS

S2560A/S2560B

Absolute Maximum Ratings

+5.5V

Supply Voltage
Operating Temperature Range
Storage Temperature Range
Voltage at Any Pin
Lead Temperature (Soldering, 10 Seconds)

VSS -0.3V to Vnn + 0.3V

Electrical Characteristics Specifications apply over the operating temperature range and 1.5V':;;; Vnn to Vss
.:;;; 3.5V unless otherwise specified. Absolute values of the measured parameters are specified.
Symbol
IOLnp
IOHDP
IOLM
IOHM
IOLT
IOHT
Inn
IIL,IIH
IIL,IIH
Inn

fo
.:lfo/fo

VDD-VSS
(Volts)

Min.

3.5

125

J.l.A

VOUT = OAV

1.5
3.5
3.5

20
125

J.l.A
J.l.A

125

J.l.A

VOUT = IV
VOUT = 2.5V
VOUT = OAV

MUTE Output High
(Source) Current
Tone Output Low (Sink)
Current

1.5
3.5

20
125

J.l.A
J.l.A

1.5

J.l.A

VOUT = IV
VOUT = 2.5V
VOUT = OAV

Tone Output High (Source)
Current
Quiescent Current

1.5

J.l.A

VOUT = IV

J.l.A

"On Hook"
HS= Vnn
VIN = Open or Vnn

3.5

100

VIN = VSS or Vnn

3.5

J.l.A

3.5

J.l.A

DP, MUTE open, HS=VSS
("Off Hook")
Key board processing and dial
pulsing space fo = 2400Hz
DP, MUTE sourcing 20J.l.A, other
conditions as above

-5

10
+5

kHz
%

-5

VnD
-0.25

VnD

VSS

VSS +
0.25
7.5

Parameter
Output Current Levels
DP Output Low (Sink)
Current
DP Output High (Source)
Current
MUTE Output Low (Sink)
Current

Input Current Any
Pin (Keyboard Inputs)
Input Current Any
Other Pin
Operating Current

Oscillator Frequency
Frequency neviation

VIH

Input Voltage Levels
Logical "1"

VIL

Logical "0"

Cin

Input Capacitance
Any Pin

3.5
3.5

1.5
1.5 to
2.5
2.5 to
3.5

Max.

Conditions

Units

Fixed R-C oscillator components
50kn .;;; Rn.;;; 750kn;
100pF.;;; Cn* .;;; 3000pF;
1Mn.;;; RE';;; 5Mn
*330pF most desirable value
for CD. Indicated and over the operating
temperature range and unit to unit
variations

The deVIce power supply should always be turned on before the input signal sources, and the input signals should be turned off
before the power supply is turned off (VSS .;;; VI .;;; VDn as a maximum limit). This rule will prevent over-dissipation and
possible damage of the input-protection diode when tpe device power supply is grounded.

6.14

S2560A/S2560B

can be similarly obtained. If the IDP select pin is connected to the dial rate select pin, the IDP is scaled to
the dial rate such that at 10 pps an IDP of 800ms is
obtained and at 20 pps an IDP of 400ms is obtained.
The user can enter a number up to 20 digits long from
a standard 3 x 4 double contact keypad (Figure 1) or
a matrix keyboard arranged out of 12 SPST switches
to produce a 2 of 7 format (Figure 2). It is also possible to use a logic interface as shown in Figure 3 for
number entry. Antibounce protection circuitry is
provided on chip (min. 13ms) to prevent false entry.

Functional Description

The key pulser is available in two package configurations: 18 pin and 24 pin. The pin function designations for the two packages are outlined in Table 1.

18 Pin Configuration

This package is specifically designed for the most
common telephone application where the rotary dial
is to be replaced by a keypad to dial pulse conversion
system. Figure 5 shows a typical telephone interface
scheme.
OFF Hook Operation: The device is continuously
powered through a 27kn resistor during OFF hook
operation. The DP output is normally high and sources
base drive to transistor Ql to turn ON transistor Q2.
Transistor Q2 replaces the mechanical dial contact
used in the rotary dial phones. Dial pulsing begins
when the user enters a number through the keyboard.
The DP output goes low shutting the base drive to Ql
OFF causing Q2 to open during the pulse break. The
MUTE output also goes low during dial pulsing allowing muting of the receiver through transistors Q3 and
Q4. The relationship of dial pulse and mute outputs
are shown in Figure 4.
ON Hook Operation: The device is continuously powered through a 10Mn resistor during the ON hook
operation. This resistor allows enough current from
the tip and ring lines to the device to allow the internal memory to hold and thereby providing storage
of the last number dialed.

Any key depressions during the on-hook condition
are ignored and the oscillator is inhibited. This insures
that the current drain in the on-hook condition is
used to retain the memory.
Normal Dialing

The user enters the desired numbers through the keyboard after going off hook. Dial pulsing starts as soon
as the first digit is entered. The entered digits are
stored sequentially in the internal memory. Since the
device is designed in a FIFO arrangement, digits can
be entered at a· rate considerably faster than the output rate. Digits can be entered approximately once
every 50ms while the dialing rate may vary from 7 to
20 pps. The number entered is retained in the memory
for future redial. Pauses may be entered when required
in the dial sequence by pressing the "#" key, which
provides access pauses for future redial. Any number
of access pauses may be entered as long as the total
entries do not exceed twenty.

The dialing rate is derived by dividing down the dial Auto Dialing
rate oscillator frequency. Table 2 shows the relationship of the dialing rate with the oscillator frequency The last number dialed is retained in the memory and
and the dial rate select input. Different dialing rates therefore can be redialed out by going off hook and
can be derived by simply changing the external resis- pressing the "#" key. Dial pulsing will start when
tor value. The dial rate select input allows changing of the key is depressed and finish after the entire numthe dialing rate by a factor of 2 without the necessity ber is dialed out unless an access pause is detected.
of changing the external component values. Thus, In such a case, the dial pulsing will stop and will
with the oscillator adjusted to 2400Hz, dialing rates resume again only after the user pushes the "#" key.
of 10 or 20 pps can be achieved. Dialing rates of 7
and 14 pps similarly can be achieved by changing the
oscillator frequency to 1680Hz.
24 Pin Configuration
The Inter-Digit Pause (IDP) time is also derived from
the oscillator frequency and can be changed by a
factor of 2 by the IDP select input. With IDP select
pin wired to VSS, an IDP of 800ms is obtained for
dial rates of 10 and 20 pps. IDP can be reduced to
400ms by wiring the IDP select pin to VDD. At dialing
rates of 7 and 14 pps, IDP's of 1143ms and 572ms
6.15

All the functions previously described for the 18 pin
package configuration can be performed in this configuration. Additionally, the following features are
incorporated:
1. A separate IDP oscillator is provided. This allows
generation of an IDP time independent of the

I
~ ;

S2560A/S2560B

24 Pin Configuration (Continued)

dialing rate. The IDP select input allows generation of two IDP's with a 2:1 ratio without the
need of changing oscillator components. Thus,
for an oscillator frequency of 24.o.oHz, an IDP of
4.o.oms is obtained with IDP select pin wired to
VDD and an IDP of 8.o.oms is obtained with the
IDP select pin connected to V ss. Table 2 shows
the relationship between the IDP and the IDP
oscillator frequency. Typical resistance and capacitor values are also provided. The IDP oscillator
input can be driven by the dial rate oscillator output if scaling of IDP to dialing rate is desired.
2. A pacifier tone output is provided. As entries
from the keyboard are made, the pacifier tone

output alternates between two frequencies for
successive digits. This provides simulation of the
dual tone signaling in the user's earpiece. The
tone frequency is derived from the dial rate
oscillator and therefore depends on the dialing
rate selected. The pacifier tone output alternates
between a pair of audio frequencies.
3. A test input is provided to allow testing of the
dial rate and IDP oscillators. With the test pin
connected to Vss, the dial rate and IDP oscillators can be gated on. This facilitates calibration
of the required frequencies. In the normal operation, the test input must be connected to V DD .

Table 1. Pin/Function Descriptions

18 Pin Configuration
Pin

Number

Function

Keyboard
(Rl,R2,R3,R4,Cl,C2,C3)

These are 4 row and 3 column inputs from the keyboard contacts. These inputs are open when the keyboard is inactive. When a key is pushed, an appropriate
row and column input must go to VDD. A logic interface
is also possible as shown in Figure 3. Active pull up and
pull down networks are present on these inputs when
the device begins keyboard scan. The keyboard scan begins when a key is pressed and starts the oscillator. Debouncing is provided to avoid false entry (typ. 2.oms).

Inter-Digit Pause Select (IPS)

One programmable line is available that allows selection of the pause duration that exists between dialed
digits. It is programmed according to the truth table
shown in Table 3. Note that preceding the first dialed
pulse is an inter-digit time equal to the selected IDP.
Two pauses either 4.o.oms or 8.o.oms are available for
dialing rates of 1.0 and 2.0 pps. IDP's corresponding to
other dialing rates can be determined from Tables 2
and 3.

Dial Rate Select (DRS)

Mark/Space (MS)

A programmable line allows selection of two different
output rates such as 7 or 14 pps, 1.0 or 2.0 pps, etc. See
Tables 2 and 3.
This input allows selection of the mark/space ratio, as
per Table 3.

Mute Out (MUTE)

A pulse is available that can provide a drive to turn on
an external transistor to mute the receiver during the
dial pulsing.
6.16

S2560A/S2560B

Table 1. (Continued)

Number

Function

Dial Pulse Out (DP)

Output drive is provided to turn on a transistor at the
dial pulse rate. The normal output will be "low" during
"space" and "high" otherwise.

Dial Rate Oscillator

These pins are provided to connect external resistors
RD, RE and capacitor CD to form an R -C oscillator
that generates the time base for the Key Pulser. The
output dialing rate and IDP are derived from this time
base.

Hook Switch (HS)

This input detects the state of the hook switch contact;
"off hook" corresponds to Vss condition.

Power (VDD, Vss)

These are t'1e power supply inputs. The device is designed to operate from 1.5V to 3.5V.

18
24 Pin Configuration
In addition to the 18 pins listed above, the following pins are provided:
Pacifier Tone Out (Tone)

Square wave output that alternates between two frequencies as defined in Table 3 when keypad buttons
are depressed.

IDP Oscillator (RI, RJ, Cr)

These pins are for connecting external resistors RI,
RJ and capacitor CI to form an R -C oscillator thai
determines the duration of the inter-digit pause. This
oscillator functions independently of the dial rate
oscillator and thus permits the dialing rates and IDP to
be independent of each other.

Test

This input when connected to Vss turns the dial rate
and IDP oscillators on to allow easy calibration of the
frequencies desired. In normal operation it must be connected to VDD.

Physical Dimensions
PIN 1 IDENTIFIER]

~'B
0.930 MAX

g:~~TYP
_--.l

t=Jl±
0.090 MIN

0.200 MAX

lD
0.280

D220

~0020MIN BENDog:~

}R\
0

MAX)

I- --11--0008
II

D.D12

6.17

S2560A/S2560B

Figure 1. Standard Telephone Pushbutton Keyboard
I

10-----,

-cp--cp--cp
cp--cp--cp-- ~
~r- -cp--cp--cp
y--0--CP---, ~
~'

-1

COMMON
(CONNECT TO VOO OR
LEAVE FLOATING)
- - - MECHANICAL
LINKAGE

877184

RON (CONTACT RESISTANCE)"; lk!1

Figure 2. SPST Matrix Keyboard Arranged in the 2 of 7 Row, Column Format

_+--..-.11---_-

Cl
SPST MATRIX KEYBOARD:

877191

0=)140

Figure 3. Logic Interface For the S2560

---t"Ci\.

KEYBOARD
INPUTS

S2560

Gl through G7 any CMOS type logic gates

877192

6.18

S2560A/S2560B

Table 2. Table for Selecting Oscillator Component Values for Desired Dialing Rates and Inter-Digit Pauses
Dial Rate
Desired
5.5/11
6/12
6.5/13
7/14
7.5/15
8/16
8.5/17

Osc. Freq.
(Hz)

RD(RI)

IRE (RJ) I CD (CI)
(pF)
(kn)

(kn)

1320
1440
1560
1680
1800
1920

Dial Rate (pps)
DRS-VSS
DRS-VDD

To Be Determined

2040

IDP (ms)
IPS- VSS
IPS-VDD

5.5

1454

6
6.5
7
7.5
8

12
13
14
15

1334
1230
1142
1066

1000

533
500

727
667
615
571

8.5

942

471

9/18
9.5/19

2160
2280

9
9.5

18
19

888
842

421

10/20

2400

800

400

(fd/ 12O )

(1920
- - x 1 0 3)
fi

(9~0 x 103)

(fd/ 24O )/
(fd/ 12O )

(fd/ 24O )

444

Notes:
1. In the 18 pin package configuration, IDP is dependent on the dialing rate selected. For example, for a dialing rate of 10
pps, an IDP of either 800ms or 400ms can be selected. For a dialing rate of 14 pps, an IDP of either 1142ms or 571ms can
be selected.
2. In the 24 pin package configuration, the dialing rate and IDP can be independently selected of each other. The general formula outlined in the table may be used to figure out any IDP and dialing rate independent of each other where fd = dial rate
oscillator frequency in Hz as determined by components RD, RE and CD and fi = IDP oscillator frequency in Hz as determined by components RI, RJ and CI.

Table 3.

Function

Pin Designation

Input Logic Level

Selection

DRS

VSS
VDD

(f/240) pps
(f/120) pps

IPS

VDD

Dial Pulse Rate Selection
Inter-Digit Pause Selection

Vss

960 s
f
1920 s
f

Mark/Space Ratio

M/S

Vss
VDD

33-1/3/66-2/3
40/60

On Hook/Off Hook

VDD
Vss

On Hook
Off Hook

Note: f is the oscillator frequency and is determined as shown in Figure 5.

Figure 4. Timing
DIAL PULSES

LDDPCURRENTlLSLJTLIL
I
I
I
I

5P
lOP

IMARK

i I

SPACE

lOP

!
I

~~~I_ _ _ _ _ __

877293

6.19

S2560AlS2560B

Figure 5. AMI Key Pulser Application

AMI KEY PU LSER

r-~~

2500
NETWORK
/
RED

H_K~2~--~_¥~DJ)O_~~AR'Ar'-~~~~~-'~l~1'~?J'v-o-o----------'

_____

1.., .....

Jt'z,

.---+-",R",2'v-'

.,...

;::

MIS

OR2
IPS

~ DRS
L-.____

F
~

,..,..(?RR)-__

.'"'

~----------_RR-+----

--"""---.Jr· :

1
R44
RJI----

9
>-__-+-'Vv"v+---i
R10

,~RS

Rz I - - -

'>t .

Ro: IOMIl, R,: 27kn, Rz: 2kn, RJ: 470kn
R4, R5: 10kn, R,O: 47kn, RS, RS: 2kll
R7, R9: Jokll, ZI: J.9V, 0" 05: lV4oo4, C,: 15"F
RE, RD: 750kn, CD: JJopF, 06: IN914
Cz: .01pF

NOTE: INITIAL PARTS REQUIRE COMMON OF THE KEYBOARO CONNECTED TO Voo

6.20

11_~
MUTE

"]---'VV\r----~

----~--~'"'~
~---+----------~_+------------~AA,

MIC·D

OR,

1'-------------~--------------~~----~~~_1~
Q4

S25SoA

....

OC,~~

+--+~---.......--+_....._+__I'o Vss
R,
Cz

I--

I----

ADVANCED PRODUCT DESCRIPTION

52561

TONE RINGER
Features

o
o
o
o
o

CMOS Process for Low Power Operation
Operates Directly from Telephone Lines
with Simple Interface
Also Capable of Logic Interface for
Non-Telephone Applications
Provides a Tone Signal that Shifts Between
Two Predetermined Frequencies at
Approximately 16Hz to Closely Simulate
the Effects of the Telephone Bell
Push -Pull Output Stage Allows Direct Drive,
Eliminating Capacitive Coupling and
Provides Increased Power Output
50mW Output Drive Capability at 10V
Operating Voltage

Auto Mode Allows Amplitude Sequencing
such that the Tone Amplitude Increases in
Each of the First Three Rings and Thereafter
Continues at the Maximum Level
Single Frequency Tone Capability

General Description

The S2561 Tone Ringer is a CMOS integrated circuit
that is intended as a replacement for the mechanical
telephone bell. It can be powered directly from the
telephone lines with minimum interface and can
drive a speaker to produce sound effects closely
simulating the telephone bell.

Data subject to change at any time without notice. These sheets transmitted for information only.

Block Diagram

Pin Configuration

DUlL

DET
INH

OUlM

ffi

OUTPUT
STAGE

OSCRm
OSCRO

OUTH

OSCT;
OSCTm

OSCTo

AIM
Vss

OSCR,
OSCRm
DSCRo

5120Hl
(NOM)

12V

Voo

6.21

Vss

S2561

Absolute Maximum Ratings

+12V

Supply Voltage
Operating Temperature Range
Storage Temperature Range
V oltage at Any Pin
Lead Temperature (Soldering, lOsec)

VSS - O.3V to VDD + O.3V

Electrical Characteristics Specifications apply over the operating temperature range and 3.5V ~ VDD to Vss

< 12V unless otherwise specified.
Symbol
VDS
VDS
IDS
IDS

10HC
10LC
IOHM
IOLM
10HL
lOLL

Parameter
Operating Voltage (VDD to VSS)
Operating Voltage
Operating Current

Min.
8.0

Output Sink Current
(OUTL output)

Units

13.5

V
V

500

/lA

4.0

Operating Current
Output Drive
Output Source Current
(OUTH, OUTC outputs)
Output Sink Current
(OUTH, OUTC outputs)
Output Source Current
(OUTM output)
Output Sink Current
(OUTM output)
Output Source Current
(OUTL output)

Max.

Conditions
Ringing, THC pin open
"Auto" mode, non-ringing
Non-ringing, VDD = lOY, THC
pin open, DI pin open or V SS
Non-ringing, VDD = 6V, THC
pin open

VDD

= lOY, VOUT = 9V

VDD

= 10V, VOUT = 0.5V

VDD

= lOY, VOUT = 9V

VDD

= lOY, VOUT = 0.5V

VDD

= lOY, VOUT = 9V

VDD

= lOY, VOUT = 0.5V

CMOS to CMOS
VIH
VIL
VOHR
VOLR
VOZ

Cin
ilfo/fo

Input Logic "1" Level
Input Logic "a" Level
Output Logic "1" Level (Rate output)
Output Logic "0" Level (Rate output)
Output Leakage Current
(OUTH, OUTM outputs in high
impedance state)
Input Capacitance
Oscillator Frequency Deviation

0.7 VDD VDD + 0.3
VSS - 0.3 0.3 VDD
0.9VDD

-5

All inputs

V
V
V

All inputs
10 = 10JlA (Source)

0.5
1
-1

/lA
/lA

7.5
+5

pF
%

10 = 10JlA (Sink)
VDD = lOY, VOUT
VDD = 10V, VOUT

= OV
= 10V

Any pin
Fixed RC component values
lMn .;;; Rsi, Rti .;;; 5Mn;
100kn.;;; R sm , Rtm';;; 750kn
l50pF.;;; Cso , Cto .;;; 3000pF
330pF recommended value of so
and Cto, supply voltage varied from
9V ± 2V (over temperature and unitunit variations)
Tone Frequency Range = 300Hz to
3400Hz
Any input, except DI pin VDD = 10V

600

IIH,IL

Output Load Impedance Connected
Across OUTH and OUTC
Leakage Current, Yin = VDD or VSS

VTH
Vz

POE Threshold Voltage
Internal Zener Voltage

6.5
11

RLOAD

n
100
8
13

nA
V
V

= 5mA

The device power supply should always be turned on before the input signal sources, and the input signals should be turned off
before the power supply is turned off (VSS .;;; VI .;;; VDD as a maximum limit). This rule will prevent over-dissipation and possible damage of the input-protection diode when the device power supply is grounded.

6.22

52561

Functional Description

The S2561 is a CMOS device capable of simulating
the effects of the telephone bell. This is achieved by
producing a tone that shifts between two predetermined frequencies with a frequency ratio of 5:4 at
approximately 16Hz rate.

Voltage Sensing: The S2561 contains a voltage sensing
circuit that enables the output stage and the rate and
tone oscillators, only when the supply voltage exceeds a predetermined value. Typical value of this
threshold is 7.3 volts. This produces two benefits.
Tone Generation: The output tone is derived from a First, it insures that the audible intensity of the outtone oscillator that uses a 3 pin R-C oscillator design put tone is fairly constant throughout the ringing
consisting of one capacitor and two resistors. The period; and secondly, it insures proper circuit operaoscillator frequency is divided alternately by 4 or 5 at tion during the "auto" mode operation by reducing
the shift rate. Thus, with the oscillator adjusted for the power consumption to a minimum when the
5120Hz, a tone signal is produced that alternates be- supply voltage drops below 7.3 volts. This extends
the supply voltage decay time beyond 4 seconds (off
tween 512Hz and 640Hz at the shift rate. The shift
period of the ring signal) with an adequate filter caparate is derived from another 3 pin R-C oscillator
citor and insures the proper functioning of the
which is adjusted for a nominal frequency of 5120Hz.
"amplitude sequencing" counter. It is important to
It is divided down to 16Hz which is used to produce
note that the operating supply voltage should be well
the shift in the tone frequency. It should be noted
above the threshold value during the ringing period
that in the special case where both oscillators are adand that the filter capacitor should be large enough so
justed for 5120Hz, it is only necessary to have one
external R-C.network for one oscillator with the other that the ripple on the supply voltage does not fall
oscillator driven from it. The oscillators are designed below the threshold value. A supply voltage of 10 to
such that for fixed R-C component values an accuracy 12 volts is recommended.
of ± 5% can be obtained over the operating supply vol- In applications where the tone ringer is continuously
tage, temperature and unit-unit variations. See Table 1 powered and below the threshold level, the internal
for component and frequency selections. In the single threshold can be bypassed by connecting the THC pin
frequency mode, activated by connecting the SFS
to VDD. The internal threshold can also be reduced
input to V SS only the higher frequency continuous by connecting an external zener diode between the
tone is produced by using a fixed divider ratio of 4 THC and V DD pins.
and by disabling the shift operation.
Ring Signal Detection: The incoming 20Hz ring signal
can be applied to the "ENABLE" input after proper
voltage limiting by diode clamping (see Figure 2). It is
first squared up and then processed by an 2ms filter
followed by a dial pulse reject filter. The 2ms filter
removes undesirable noise transitions that may occur
on the ring signal. The dial pulse reject filter is clocked
by an 8Hz signal derived from the rate oscillator and
insures that frequencies below 16Hz will not pass
through. This helps eliminate dial pulse interference
and insures that the tone ringer will not trigger during
dial pulsing. Another benefit of the dial pulse reject
filter is that an output tone is not produced unless
the ring signal duration exceeds 125ms. This insures
that the tone ringer will not respond to momentary
bursts of ringing less than 125 milliseconds in duration (Ref. 1).

Auto Mode: In the "auto" mode, activated by wiring
the "auto/manual" input to V SS, an amplitude sequencing of the output tone can be achieved. Resistors
RL and RM are inserted in series with the OutL and
OutM outputs, respectively, and paralleled with the
OutH output (Figure 1). Load is connected across
OutH and Outc pins. RL is chosen to be higher than
RM. In this manner the first ring is of the lowest amplitude, second ring is of medium amplitude and the
third and consecutive rings thereafter are at maximum
amplitude. For the proper functioning of the "amplitude sequencing" counter the device must have at
least 4.0 volts across it throughout the ring sequence.
The filter capacitor is so chosen that the supply voltake will not drop below 4.0 volts during the off period. At the end of a ring sequence when the off period
substantially exceeds the 4 second duration, the counter will be reset. This will insure that the amplitude
sequencing will start correctly beginning a new ring
sequence. The counter is held in reset during the
"manual" mode operation. This produces a maximum
ring amplitude at all times.

In logic interface applications, the 2ms filter and the
dial pulse reject filter can be inhibited by wiring the
Det. INHIBIT pin to VDD. This allows the tone ringer
to be enabled by a logic '1' level applied at the
"ENABLE" input without the necessity of a 20Hz
ring signal.
Output Stage: The output stage is of push-pull type
6.23

'I
.
: ~

52561

Functional Description (Continued)

consisting of buffers L, M, Hand C. The load is connected across pins OutH and Outc (Figure 2). During
ringing, the OutH and Outc outputs are out of phase
with each other and pulse at the tone rate. During a
non-ringing state, all outputs are forced to a known
level such as ground which insures that there is no DC
component in the load. Thus, direct coupling can be
used for driving the load. The major benefit of the
push-pull arrangement is increased power output.
Four times as much power can be delivered to the
load for the same operating voltage. Buffers M and H
are three-state. In the "auto" mode buffer M is active
only during the second ring and in the "high impe-

dance" state at all other times. Buffer H is active
beginning the third ring. In the "manual" mode buffers H, Land C are active at all times while buffer M
is in a high impedance state. The output buffers are
so designed that they can source or sink 5mA at a
VDD of 10 volts without appreciable voltage drop.
Care has been taken to make them symmetrical in
both source and sink configurations. Diode clamping
is provided on all outputs to limit the voltage spikes
associated with transformer drive in both directions
VDD and VSS·
Normal protection circuits are present on all inputs.

Table 1. Pin/Function Descriptions

Number

Function

Power (V DD, V SS)

These are the power supply pins. The device is designed
to operate over the range of 3.5 to 13.5 volts. A range
of 10 to 12 volts is recommended for the telephone application.

Ring Enable (EN, EN)

Auto/Manual (AIM)

These pins are to connect the 20Hz ring signal. EN can
also be used for DC level enabling by wiring the DI pin
to Vnn.
"Auto" mode for amplitude sequencing is implemented
by wiring this pin to V SS. "Manual" mode results when
connected to VDD. The amplitude sequencing counter
is held in reset during the "manual" mode.

These are the push-pull outputs. Load is directly connected across OutH and Outc outputs. In the "auto"
mode, resistors RL and RM can be inserted in series
with the OutL and OutM outputs for amplitude sequencing (see Figure 1).

These pins are provided to connect external resistors
RRi' RRm and capacitor CRo to form an R-C oscillator
with a nominal frequency of 5120Hz. See Table 2 for
components selection.

Tone Oscillator
(OSCTi, OSCT m , OSCTo)

These pins are provided to connect external resistors
RTi' RTm and capacitor CTo to form an R-C oscillator
from which the tone signal is derived. With the oscillator adjusted to 5120Hz, a tone signal with frequencies
of 512Hz and 640Hz results. See Table 2 for components selection.

Threshold Control (THC)

The internal threshold voltage is brought out to this pin
for modification in non -telephone applications. It can
be bypassed by wiring the THC pin to VDD. It can be
reduced by connecting a suitable zener diode between
THC and VDD.

Oscillators
Rate Oscillator
(OSCRi' OSCRm , OSCRo)

6.24

52561

Table 1 (Continued)

Number

Function

Detector Inhibit (DI)

When this pin is connected to VDD, the dial pulse reject
filter is disabled to allow DC level enabling of the tone
ringer. This pin should be hardwired to V SS in normal
telephone -type applications.

Single Frequency Select (SFS)

When this pin is connected to V SS, only a single frequency continuous tone is produced as long as the tone
ringer is enabled. In normal applications this pin should
be hardwired to VDD.

Table 2. Selection Chart for Oscillator Components and Output Frequencies

Tone/Rate
Oscillator
Frequency
(Hz)

RI
(kD)

Oscillator Components
RM
(kD)

Co
(pF)

Rate
(Hz)

Tone
(Hz)

5120

512/640

6400

640/800

3200

To Be Determined

8000

320/400

800/1000

320

fo
10

I
6.25

52561

Applications

Typical Telephone Application: Figure 2 shows the
schematic diagram of a typical telephone application
for the S2561 tone ringer circuit. Power is derived
from the telephone lines by the network formed by
capacitor C1, resistor R1, diode bridge d1 through d4,
ahd filter capacitor C2. C2 is chosen to be large
enough so as to insure that the power supply ripple
during ringing does not fall below the internal threshold level (typ. 7.3 volts) and to provide large enough
decay time during the off period. A typical value of
C2 may be 47IJF. C1 and R1 are chosen to satisfy the
Ringer Equivalence Number (REN) specification
(Ref. 1). For REN = 1 the resistor should be a minimum of 8.2kn. It must be noted that the amount of
power that can be delivered to the load depends upon
the selection of C1 and R 1.
The device is enabled by limiting the incoming ring
signal through resistors R2, R3 and diodes d5 and
d6., Zener diode Z1 (typ. 9-27 volts) may be required
in certain applications where large voltage transients
may occur on the line during dial pulsing. The internal
2ms filter and the dial pulse reject filter will suppress
any undesirable components of the signal and will
only respond to the normal 20Hz ring signal. Ring
signals with frequencies above 16Hz will be detected.
The configuration shown will produce a tone with
frequency components of 512Hz and 640Hz with a
shift rate of approximately 16Hz and deliver at least
50m W to an 8n speaker through a 2000n :8n transformer. If "manual" mode is used, a potentiometer
may be inserted in series with the transformer primary
to provide volume control. If "automatic" mode is
used, resistors RL and RM can be chosen to provide
desired amplitude sequencing. Typically, signal power
will be down 20 log (

RLOAD )
RL + RLOAD

first ring, and down 20 log (

In applications where dial pulse rejection is not necessary, such as in DTMF telephone systems, the
ENABLE pin may be connected directly to VDD.
Det. Inh pin must be connected to VDD to allow
DC level enabling of the ringer.

Non-Telephone Applications: The configuration
shown in Figure 3 -A may be used in non -telephone
applications where it is desired to simulate the telephone bell. The internal threshold is bypassed by
wiring THC to VDD. The rate output (16Hz) is divided
down by a 7 stage divider type 4024 to produce two
signals: a 2 second on/2 second off signal and a 4
second on/4 second off signal. The first signal is connected to the EN pin and the second to the DI pin to
produce a 2 second on/4 second off telephone-type
ring signal. The ring sequence is initiated by removing
the reset on the divider. If "auto" mode is used, a
reset signal must be applied to the "amplitude sequencing" counter at the end of a ring sequence so
that the circuit will respond correctly to a new ring
sequence. This is done by temporarily connecting the
"auto/manual" input to VSS.
Figure 3 -B shows a typical application for alarms,
buzzers, etc. Single frequency mode is used by connecting the SFS input to VSS. A suitable on/off rate
can be determined by using the 7 stage divider circuit.
If continuous tone is not desired, the 16Hz output
can be used to gate the tone on and off by wiring it
into the ENABLE input.
Many other configurations are possible depending
upon the user's specific application.

dB during the
Reference 1. Bell system communications technical
reference:

RLOAD ) dB during
RM + RLOAD

the second ring with maximum power delivered to the
load beginning the third and consecutive rings.

PUB 47001 of August 1976
"Electrical characteristics of Bell System Network
Facilities at the interface with Voiceband Ancillary
and Data Equipment" - Sections 2.6.1 and 2.6.3.

6.26

52561

Figure 1· B. Output Stage Connected
for Manual Mode Operation.

Figure 1-A. Output Stage Connected
for Auto Mode Operation

-------~

TRANSFORMER

877276

Figure 2. Typical Telephone Application of the S2561

THC

~!(]d.

OUTm
6

OSCTm

OSCT,

AIM

Vss

OUT,

C,
.47"f/200V
C2
47"F/25V
0, . 04 IN4004

R,
R2
R3

2kn
51kn
10Mn

Rm
C,

lMn
200kn
330pF

6.27

Rl 1SKn
RM 3.3Kn

SP
T,
Z,

SnSPEAKER
1000n/sn XFMR
9 TO 27V ZENER

S2561

Figure 3-A. Simulation of the Telephone Bell in Non- Telephone Applications.

OSCR,
OSCRm

POWER
SUPPLY
12V MAX

"'''H

-v

Vss

Voo

THC

OUTH

OUTm

OUT,

II(}
LOGIC ENABLE

~~~ t~Ep~I~!~~~~~~OE~A;J;p~~ ~~~~~~t; !~~~~i~~E06~~~c~C~~~~s~OfH~NS~:t~:I:~l ~~GNEO~ACNO~:~~~N~
lAINED BELOW 12V OR SUPPl V CURRENT IS LIMITED TO SOmA.

Figure 3-B. Single Frequency Tone Application in Alarms, Buzzers, Etc.

Voo
(1B)

AIM
(8)
(16) 01

(17) THC

II()

(IS) OUTH
S2561C

};

(14) OUTM

(13) OUlL

(12) OUT,
11

EN (10)

RATE
(9)

m(l)

Vss

6.28

ADVANCED PRODUCT DESCRIPTION

52562
REPERTORY DIALER

Features

D CMOS Process Achieves Low Power Operation

D Inexpensive, but Accurate R-C Oscillator
Design Provides Better Than ±3% Accuracy
Over Supply Voltage, Temperature and UnitUnit Variations and Allows Different Dialing
Rates, IDP and Tone Drive Timing by
Changing the Time Base
D Power Fail Detection
D BCD Output with Update for Number Display
Applications

D 8 or 16 Digit Number Capability
(Pin Programmable)
D Dial Pulse and Mute Output
D Tone Outputs Obtained by Interfacing with
Standard AMI S2559 Tone Generator
D Two Selections of Dial Pulse Rate
D Two Selections of Inter-Digit Pause
D Two Selections of Mark/Space Ratio
(33-1/3/66-2/3 or 40/60)

General Description

D Memory Storage of 32 8-Digit Numbers or
16 16-Digit Numbers with Standard
AMI S5101 RAM

The S2562 Repertory Dialer is a CMOS integrated
circuit that can perform storing or retrieving, normal
dialing, redialing or auto dialing and displaying of
one of several telephone numbers. It is intended to be
used with the AMI standard S5101-256x4 RAM that
functions as telephone number storage. With one
S5101 up to 32 8-digit or 16 16-digit numbers can
be stored. It can provide either dial pulses or DTMF
tones with the addition of the AMI S2559 tone
generator for either the dial or tone line applications.

D 16-Digit Memory for Input Buffering and for
Redial with Access Pause Capability
D Accepts the Standard Telephone DPCT
Keypad or SPST Switch X -Y Matrix
Keyboards; Also Capable of Logic Interface
D Ignores Multi Key Entries

Data subject to change at any time without notice. These sheets transferred for information only.

Block Diagram

Pin Configuration
--0

VDO

--oVSS

Ct
RNI

OSCi
oSC m
oSC o

MODE
NLS
R1

KEYPAD

RS
C1
Cs

Voo

NLS

MIS

IPS

RNI

IPS

AAM 1/0 OATA
DISPLAY

MIS
DRS

PLA

AO
A1
A2
A3 RAM AODRESS
A4 TONE GENERATOR
A5
AS
AJ

MUTE

A.
AJ

As
A.

Pi'"

C6
Cs

MUTE
877283

6.29

DSC M

OSC I

C,
C,

Vss

ilP

AD
DSC D
]iF

OAS
MODE

jjp

52562

Absolute Maximum Ratings

Supply Voltage
Operating Temperature Range
Storage Temperature Range
V oltage at Any Pin
Lead Temperature (Soldering, 10 sec.)

13.5V

V ss - 0.3V to V DP +0.3V

Electrical Characteristics Specifications apply over the operating temperature range and 4.5V ,;;;; VDD to Vss
,;;;; 5.5V unless otherwise specified. Absolute values of measured parameters are specified.

Symbol

Parameter

IOLDP
IOHDP
IOLM
IOHM
IOLPF
IOHPF

Output Drive
DP Output Sink Current
DP Output Source Current
MUTE Output Sink Current
MUTE Output Source Current
PF Output Sink Current
PF Output Source Current

VIL
Vm
VOL

CMOS to CMOS
Logic "0" Input Voltage
Logic "1" Input Voltage
Logic "0" Output Voltage

VOH

Logic "1" Ou tpu t Voltage

IDD
IDD

Curren t Levels
Quiescent Current
Operating Current

IlL, 1m
IIL,lm
loz

Input Current Any Pin
(keyboard inputs)
Input Current All Other Pins
Output Current in High
Impedance State

~fo/fo

Oscillator Frequency
Frequency Deviation

CIN

Input Capacitance, Any Pin

Min.

Max.

Units

Conditions

400

/lA

VOUT

400
400
400
100
100

/lA

VOUT
VOUT
VOUT
VOUT
VOUT

= 3.6V, VDD
= O.4V, VDD
= 3.6V, VDD
= O.4V, VPP
= 3.6V, VDD

/lA
/lA
/lA
/lA
1.5

3.5
0.5
4.5

4
-3

V
V
V
V

O.4V, VDD

= 5V
= 5V
= 5V
= 3V
= 5V

All inputs, VDD = 5V
All inputs, VDD = 5V
All outputs except DP, MUTE, PF,
10 = 10/lA, VDD = 5V
All outputs except DP, MUTE, PF,
10 = -10/lA, VDD = 5V

25
500

/lA
/lA

Standby, VDD = 5V
All valid input combinations, DP,
MUTE, PF outputs open VDD = 5V

100

/lA

VIN

100
1

/lA

-1
10
+3

kHz
%

VIN = Vss or VDD, VPD = 5V
VDD = 5V, VOUT = OV dafa
outputs (D1-D4)
VDD = 5V, VOUT= 5V
VPP = 5V (min. duty cycle 30170)
VDD - Vss from 4.5V to 5.5V.
Fixed R-C oscillator components
50kQ';;;; RM ,;;;; 750kQ;
1MQ';;;; RI';;;; 5MQ;
150pF';;;; Co < 3000pF;
330pF most desirable value for
CO, fo < 10kHz over the operating
temperature and unit-unit variations

7.5

/lA

Vss or VDD, VDD = 5V

The device power supply should always be turned on before the input signal sources, and the input signals should be turned off
before the power supply is turned off (Vss .;;; VI';;; VDD as a maximum limit). This rule will prevent over-dissipation and possible damage of the input-protection diode when the device power supply is grounded.
6.30

52562

Functional Description

The S2562 is a CMOS controller designed for storing or
retrieving, normal dialing, redialing or auto dialing and
displaying of one of several telephone numbers. It is
intended to be used with the AMI standard S5101
256x4 RAM that functions as a telephone number
storage. A single S5101 RAM will store tip to 32 8digit or 16 16-digit telephone numbers. The S2562
can be programmed to work with either 8 -digit or
16-digit numbers by means of the Number Length
Select (NLS) input.
The S2562 uses an inexpensive, but accurate R-C
oscillator as a time base from which the dialing rate
and inter-digit pause duration (IDP) are derived. Different dialing rates and IDP durations can be implemented by simply adjusting the oscillator frequency.
The dialing rate and IDP can be further changed by a
2:1 factor by means of the dialing rate select (DRS)
and inter-digit pause select (IPS) inputs. Thus, for the
oscillator frequency of 8kHz, dialing rates of 10 and
20 pps and IDP's of 400 and 800ms can be achieved.
The mark/space ratio is fixed independent of the
time base and can be selected to be either 33 -1/3 / 662/3 or 40/60 by means of M/S input. Over supply voltage (5V ± 10%), operating temperature range and unitunit variations, timing accuracy of ± 3% can be achieved. A mute output is also available for muting of
the receiver during dial pulsing. See Figure 5 for timing
relationship.
The S2562can be programmed by means of the MODE
input for dual tone signaling applications as well. In
this mode, it can interface directly with the AMI
standard S2559 Tone Generator to produce the required DTMF signals. The tone on/off rate during an
auto dial operation in this mode is derived from the
time base. For the oscillator frequency of 8kHz, a
tone drive rate of 50ms on, 50ms off is obtained.
Different rates can be implemented by adjusting the
time base as desired. See Tables 2 and 3 for the various
cbmbinations. In the tone mode, the mute output is
used to gate the tone generator on and off. The 8 address lines that are normally used for addressing the
RAM are also used to address the tone generator roVl.',
column inputs. Figure 6 shows a typical system
application.
The S2562 can perform the following functions:
Normal Dialing
The user enters the desired number digits through the
keyboard after going off hook. Dial pUlsing starts as
soon as the first digit is entered. The entered digits
are stored sequentially in the internal memory. Since
6.31

the device is designed in a FIFO arrangement, digits
can be entered at a rate considerably faster than the
output rate. Digits can be entered approximately
once every 50ms while the dialing rate may vary from
7 to 20 pps. Debouncing (min. 20ms) is provided on
the keyboard entries to avoid false entries. The number entered is retained for future redial. Pauses may
be entered when required in the dial sequence by pressing the "#" key, which provides access pauses for
future redial. Any number of access pauses may be
entered as long as the total entries do not exceed the
total number of digits (8 or 16).
An update pulse is generated to update the display
digit as a new entry is made.
In the tone mode the tones will be transmitted at the
rate the user enters the digits.
Redialing
The last number entered is retained in the internal
memory and can be redialed by going "off hook" and
depressing the "redial" (RDL) key. The RDL key is a
unique 2 of 12 matrix location (R5, C3). The number
being redialed out is displayed as it is dialed out.
In the tone mode, the redial tone drive rate depends
upon the time base as discussed before.
Storing of a Normally Dialed or Redialed Number
into the External Memory
After the normal dialing or redialing operation, the
telephone number can be stored in ~he external memory for future repertory dialing use by going on hook
and initiating the following key sequence.
1. Push "store" (ST) button.
2. Depress the single digit key corresponding to the
desired address location.
Note that the "ST" key is a unique 2 of 12 matrix
location (R5, C1).
Storing of a Telephone Number into the External
Memory
This operation is performed "on hook'" and no outdialing occurs. A telephone number can be stored in
the desired address location by initiating the following
key sequence.

1. Push the "*,, key (This instructs the device to
accept a new number for storage into the internal
memory).
2. Enter the digits (including any access pauses) corresponding to the desired number.
3. Push the "ST" key.

52562
4. Push the single digit key corresponding to the desired address location.
The entire sequence can be repeated to store as many
numbers as desired.
Displaying of a Stored Telephone Number
This is an "on hook" operation. Either the last dialed
number or the number stored in the external memory
can be displayed one digit at a time. The key sequence
for displaying the last dialed number is as follows:
1. Push the "read" (R) key.
2. Push the "RDL" key.
The number in the external memory can be displayed
as follows:
1. Push the "R" key.
2. Push the single digit key corresponding to the desired address location. .
Note that the "R" key is a unique 2 of 12 matrix location (R5, C2).
The number is displayed one digit at a time at a rate
determined by the time base. With a time base of 8kHZ
the display will be on 500ms, off 500ms. The display
is updated by producing an update pUlse. The update
pulse must be decoded with external logic (one inverter
and one 2-input gate) as shown in Figure 6.
The display is blanked by outputting an illegal (non
BCD) code such as 1111. The 4511-type BCD to 7
segment decoder driver latch will blank the display
when the illegal code is detected. When other driver
circuits are employed, external logic must be used to
detect the illegal code.
Repertory Dialing
This is the most common mode of usage and allows
the user to dial automatically any number stored in
the memory. This mode is initiated by the following
key sequence after going off hook.

1. Push the "*" key.
2. Push the single digit key corresponding to the desired address location.
The number is displayed as it is dialed out. In the tone
mode, the tone driver rate is dependent on the time
base as described earlier.
Pause
Note that the out dialing in the repertory or redial operation continues unless an access pause is detected.
The outpulsing will stop and resume only when the
user terminates the access pause by pushing the "*"
key again.
Power Fail Detection
This output is normally high. When the supply voltage falls below a predetermined value, it goes low.
The output can then drive a suitable latching device
that will switch the memory to either the tip and
ring or an auxilliary battery supply.
Memory Expansion
The memory can be expanded by paralleling additional
S5101 RAM's. External logic must be used to enable
the desired RAM corresponding to a desired address
location. The S2562 can drive up to 2 RAM's without
the need of buffering address and data lines.
Keybounce Protection
When a key closure is detected by the S2562, an internal timeout (min. 4ms at fo = 8kHz) is started. Any
transitions that occur during this timeout will reset
the timer to zero so that a key will only be accepted as
valid after a noise free timeout period. The key must
remain closed for an additional 16ms before released.
Thus, the total make time of the key must be at le;:tst
20ms. The key must be released for at least 1ms before
a new key is activated. Any transitions occurring when
the key is released are ignored as long as the make time
does not exceed 4ms.

6.32

S2562

Table 1. Pin/Function Descriptions

Number

Function

These are the power supply inpu ts. The device is designed
to operate from 3.5V to 13.5V.

These are 6 row and 6 column inputs from the keyboard
contacts. When a key is pushed, an appropriate row and
column input must go to VDD or connect to each other.
Figures 1 and 2 depict the standard telephone DPCT and
x- Y matrix keyboard arrangements that can be used. A
logic, interface is also possible as shown in Figure 3. Debouncing is provided to avoid false entry (typ. 20ms for
oscillator frequency of BkHz). Key pad entry options
are shown in Figure 4.

Number Length Select (NLS)

This input permits programming of the device to accept
either B-digit numbers or I6-digit numbers.

Mode Select (MODE)

This input allows the use of the device in either dial pulsing applications or tone drive applications.

Dial Rate Select (DRS)

This input allows selection of two different dialing rates
such as 10 or 20 pps, 7 or 14 pps, etc. See Tables 2 and

Power (VDD, VSS)

3.
Inter-Digit Pause Select (IPS)

This allows selection of the pause duration that exists
between dialed digits. It is programmed according to the
truth table shown in Table 3. Note that preceeding the
first dialed digit is an inter- digit time equal to the selected
IDP. Two pause durations, either 400ms or BOOms are
available at dialing rates of 10 and 20 pps. IDP's corresponding to other dialing rates can be determined from
Tables 2 and 3.

Mark/Space Ratio Select (M/S)

This input allows selection of the mark/space ratio as
per Table 3.

Mute Output (MUTE)

A pulse is available that can provide drive to tum on an
external transistor to mute the receiver during dial pulsing. See Figure 5 for mute and dial pulse output relationship. It is also used as a keyboard disable in the tone
drive applications. See Figure 6.

Dial Pulse Output (DP)

Output drive is provided to tum on a transistor at the
dial pulse rate. This output will be normally high and go
low during "space" or "break."

Display Memory I/O Data (D1-D4)

These are 4 bidirectional pins for inputting and outputting data to the external memory and display driver.
6.33

·I:
..

52562

Table 1. (Continued)

Number

Function

Memory Enable (CE)

This line controls the external memory operation.

Memory Read/Write (R/W)

This line controls the read or the write operation of the
external memory. This output along with the CE output
can be used to produce a pulse to update the external
display. See Figure 6.

Tone Generator/Memory Address

These are 8 output lines that carry the external memory
address and tone generator row/column information.

Hook Switch (HS)

This input conveys the state of the subset. "Off hook"
corresponds to V SS condition.

Power Fail Detect (PF)

This output ,is normally high and goes low when the
power supply falls below a certain predetermined value.

Oscillator (aSCi, OSC m , OSC o )

These pins are provided to connect external resistors RI,
RM and capacitor Co to form an R-C oscillator that generates the time base for the repertory dialer. The output
dialing rate, tone drive rate and IDP are derived from
this time base.

(AO-A7)

6.34

52562

Figure 1. Standard Telephone Pushbutton Ke"boClrd

~,-

-8--8--0
8--8--8--

R3~'-- -

I
I

-I
.-.0--- R2

-cp--cp--cp
0--8--0---,
I

~R4

L-__~~____~~__~~~~____~ COMMON

(CONNECT TO VDD OR
LEAVE FLOATING)
- - - MECHANICAL
LINKAGE
RON (CONTACT RESISTANCE) <; lkn
877290

Figure 2. SPST Matrix Keyboard Arranged in the 2 of 12 Row, Column Format

--+---~-+----~--------+R4

I
Cl

C3 -

SPST MATRIX KEYBOARD:

877285

6.35

- C6

52562

Figure 3. Logic Interface For the S2562

.......

1"
I
I
I
I
I
I
I
I
I
I

KEYBOARD
INPUTS

I
I
I
I
I
I
I
I
I

.......
.......
G12

S2562
C6

D12

877286
G1 through G12 any CMOS type logic gates.
D1 through D12 DIODES type 1N 914. (Optional)

Figure 4. EXample of Keypad Entry - Options

CD
0

m CD

[TI IT]
[2J [II 0
[J 0 0

STORE

READ

REDIAL

[]
[2]

1·11 in parallel
with 1'''01
2 01 7 keypad

···
0

[2J IT] IT] @] ~ @]
0 IT] IT] ~ @] ~

IT] 0 @] @] @J

[2i] ~ @]

~ @] @] [EJ

@] @J ~ §] ~ @]

[] [I]

---------

IT]

877287

6.36

82562

Table 2. Table for Selection of Oscillator Component Values for Desired Dialing Rate, lop or Tone Drive Rate.

Dial Rate
Desired
(PPS)

Osc. Freq.
fo
(Hz)

Oscillator Components

I (kn)
RI
I(pF)
Co
(kn)
RM

Dial Rate (PPS)
DRS = VSS DRS= VDD

IDP (ms)
IPS = VSS
IPS = VDD

Tone Drive
On/Off
Time (ms)

5.5/11

4400

5.5

1454

727

90/90

6/12

4800

1334

667

83.3/83.3

77/77

6.5/13

5200

6.5

1230

615

7/14

5600

1142

571

71/71

7.5/15

6000

7.5

1066

533

66.7/66.7
62.5/62.5

To Be
Determined

8/16

6400

1000

500

8.5/17

6800

8.5

942

471

59/59

9/18

7200

888

444

55.5/55.5

9.5/19

7600

9.5

842

421

52.6/52.6

10/20

8000

800

400

50/50

fo/800

fo/400

6400 x 10 3
fo

3200 x 10 3
fo

400 x 10 3 /400 x 10 3
fo
fo

(fo/800)/
(fo/400)

Table 3.

Pin Designation

Input Logic Level

Selection

Dial Rate Selection

DRS

VSS
VDD

Inter-Digit Pause Selection

IPS

VDD
VSS

Mark/Space Ratio

M/S

VSS
VDD

Hook Switch

VDD
VSS

MODE

VSS
VDD

NLS

'VSS
VDD

(fo/800) pps
(fo/400) pps
(3200/fo) S
(6400/fo) S
33-1/3/66-2/3
40/60
On hook
Off hook
Dial pulse
Tone drive
8 digits
16 digits

Function

Mode Selection
N urn ber Length Selection

Note: fo is the oscillator frequency and is determined as shown in Table 2.

Figure 5. Mute and Dial Pulse Output Timing Relationship

DIAL~:u-L
I
I

I
I

: MARK: SPACE

I
I

MuTE

I
I
lOP

I
I

---i

r~L...-

877288

6.37

I
I

: MARK:
I

_____

52562

Figure 6. Typical Application of the S2562

R,
RJ
R,
REPERTORY

000000

DEPENDING
UPON APPLICATION

{

SINGLE
DIGIT
DISPLAY

Vs~

§]0~000

4S11

l[.

800 000
0CD[D 000
000 000
000 000

",",",","
Vao 0 R

TYPf

C,
C6

{

OSCILLATOR

.-.,=,

DIALER

S2S62

0',
0"

osc,

IT,

RM
OSCM

OSCo

AD
A,

256X4

55101

AJ
A,

Pi'

CMOS

RAM

CE,

MUTE

TONE
GEN

TELEPHONE

~2S59

INTERFACE

CJ
KBGS

Physical Dimensions

6.38

TONE

l1li
358MHl
CRYSTAL

ADVANCED PRODUCT DESCRIPTION

S2811
SIGNAL PROCESSING
PERIPHERAL
Features

Bus Oriented Parallel I/O for Easy Microprocessor Interface

High Speed VMOS Technology

Programmable for Digital Processing of Signals
in Voice-Grade Communications Systems and
Other Applications with Signal Frequencies in
the Range of DC to 10KHz

Additional Serial I/O for Easy A/D-D/A
Interface

Extremely Fast 12-Bit Parallel Multiplier On
Chip (300ns Max. Multiplication Time)

Built-In ROM (256 x 17), 3-Port RAM (256 x
16) and Add/Subtract Unit (ASU)

Pipeline Structure for High Speed Instruction
Execution (300ns Max. Cycle Time)

General Description

The S2811 Signal Processing Peripheral (SPP) is a high
speed special pur)ose arithmetic processor with onchip ROM, RAM, multiplier, adder/subtractor, accumulator and I/O organized in a pipeline structure to
achieve an effective operation of one multiply, add
and store of up to 12-bit numbers in 300 nanoseconds.

Block Diagram

SERIAL
INTERFACE

--s-------

Logic Diagram

SERIAL
I/O
INTERFACE

00-07

FO-F3

SIEN

R/W

SCK

lEN

fRU

SOEN

INTERFACE
CE

P
0

RST
}

ClK
TST

ROM
(256,17)
Voo
(5V)
LATCH

17
INSTRUCTiON BUS

6.39

Vss
(OV)

fUTURE
USE

ADVANCED PRODUCT DESCRIPTION

52900/52901

CMOS SINGLE CHANNEL
p.-LAW PCM CODEC/FILTER SET
Features

General Description

The S2900 and S2901 forma monolithic CMOS Companding Encoder/Decoder chip set designed to implement the per channel voice frequency. CODECS used
in PCM Channel Bank· and PBX systems requiring a
11-255 law transfer characteristic. Each chip contains
two sections: (1) a band-limiting filter, and (2) an
analog +7 digital conversion circuit that conforms to
the 11-255 law transfer characteristic. Transmission and
reception of 8-bit data words containing the analog
information is performed at 1.544Mb/s rate with
analog sampling occurring at 8KHz rate. A strobe
input is provided for synchronizing the transmissio.n
and reception of time mUltiplexed PCM information
of several channels over a single transmission line.

o
o
o

o
o
o
o
o

Full Independent Encoder with Filter and
Decoder with Filter Chip Set
Meets or Exceeds AT&T D3andCCITTG. 712
Specifications
On-Chip Phase-Lock Loop Derives All Timing
Low Power Dissipation - Power Down Mode
Wide Supply Voltage Range
Low Absolute Group and Relative Delay
Distortion
Single Negative Polarity Voltage Reference Input
Encoder with Filter Chip Has Built-In Auto
Zero Circuit that Eliminates Long Term Drift
Errors and Need for Trimming
Serial Data Rates from 56KHz to 3.088MHz
at 8KHz Nominal Sampling Rate
Programmable Gain Input/Output Amplifier
Stage
CCIS* Compatible A/B Signaling Option

*Common Channel Interoffice Signaling

S2900 Block Diagram Encoder with Filter

Pin Configuration
AZ

FILTER

SHIFT CLOCK

'---t:::===-~

STROBE 10KH,) o----~

lOOP FILTER

o-----.:::J-ri

ANAlOGGND~
DIGITALGND~

L~~=:!:====

POWER
DOWN

OUTCONTROL"

OSIG IN

*: NOT BONDED IN 16 PIN PACKAGE
1, CCIS AlB SIGNALING OPTION

S2901 Block Diagram Decoder with Filter·

Pin Configuration

Flt~~~ o--~------;::L--1~~
STROBE O--~t--~

..,-------0

I=~-;:-~------+-O
L

T~~c!=====~:
'------------0
... : eels AlB SIGNALING OPTION

6.40

SHIFT CLOCK

AOUT

BOUTSELECT IA/B IN)'
AlB

Vss IGNO OR-5V)

52900/52901

S2900/S2901 Typical Group Delay Characteristic

f=1000Hz

f=2600Hz

Relative Gr. Delay
Distortion lOver Band
of 1000Hz to 2600Hz
wrt 1000HzlflS

Encoder Low Pass
Encoder High Pass
Encoder (Total)

166.4
104.0
270.4

250
22
272

83.6
-82.0
1.6

Decoder Low Pass

153.0

250.0

97.0

Encoder + Decoder (Total)

423.4

522.0

98.6

Device

Abs. Gr. Delay
flS

I
6.41

6.42

7
Consumer and
Interface Products

Selection Guide

REMOTE CONTROL CIRCUITS
PART NO.

S2600

DESCRIPTION
Remote Control Transmitter

S2601
S2742
S2743

Remote Control Receiver
Remote Control Decoder
Remote Control Encoder

PROCESS

POWER SUPPLIES

VO BITS

CMOS
P_12

+ 7V to + 10V
+10V to + 18V

P-MOS
P-MOS

+9V
+9V

PACKAGES
16 Pin

22 Pin
18 Pin
16 Pin

TOUCHCONTROLTM INTERFACE CIRCUITS
PART NO.

S9260/61
S9263/64/65
S9262
S9266

DESCRIPTION
Seven-Switch Interface
Sixteen-Switch Interface

PROCESS
P_12
P_12

Fourteen-Switch Interface

P_12

Thirty-Two-Switch Interface

P_12

POWER SUPPLIES
-13.5V to -18V
-13.5V to -18V
-13.5V to -18V
-13.5V to -18V

INPUT/OUTPUT

CMOS/TTL
CMOS/ MOS/TTL
MOS/TTL
MOS/TTL

PACKAGES
22 Pin
40 Pin
22 Pin

40 Pin

CONSUMER CIRCUITS
PART NO.
S1424A

DESCRIPTION
Five Function LCD Watch with alternating
time/date mode and voltage tripler
display options

S1424C
S1425A

Five Function LCD Watch Circuit
Five Function LCD Watch Circuit
Five Function LCD Watch Circuit

S1427A
S1865
S1998A
S19988
S2709
S2733

Digital Clock Circuit - LED/Gas
Discharge Auto Clock
50/60Hz Line LED Clock Circuit
50/60Hz Line Clock - Gas Discharge
Fluorescent Automotive Digital Clock
Six Function LCD Watch Circuit

PROCESS
CMOS

POWER SUPPLIES

DIGITS

+1.5V

3V2

CMOS
CMOS

+1.5V
+1.5V

CMOS
P_12

+1.5V
+6V to +16V

3'/2
3'/2
3V2
3V2

P_12
P_12
P_12

+8V to +26V
+8V to +33V
+12V
+1.5V

CMOS

PACKAGES
Die

Die
Chip Carrier
40 Pin
40 Pin
40 Pin
40 Pin
22 Pin
40 Pin

ORGAN CIRCUITS
PART NO.

DESCRIPTION

S10110
S10111
S10129
S10130
S10131
S10377
S10430

Analog Shift Register
Analog Shift Register
Six-Stage Frequency Divider
Six-Stage Frequency Divider
Six-Stage Frequency Divider
Analog Shift Register
Divider-Keyer

S2193
S2567
S8890
S9660
S50240
S50241

Seven-Stage Frequency Divider
Rhythm Counter
Rhythm Generator
Rhythm Generator
Top Octave Synthesizer
Top Octave Synthesizer
Top Octave Synthesizer
Top Octave Synthesizer
Top Octave Synthesizer
Top Octave Synthesizer

S50242
S50243
S50244
S50145

PROCESS

POWER SUPPLIES

P_12
P_12
P_12
P_12
P_12

-24V
-24V
-14V, -27V
-14V, -27V
-14V, -27V

P_12 MOS
P_12 MOS
P_12
HI VT
P_12
P_12
P_12
P_12
P_12
P_12
P_12
P_12

7.2

-14V, -28V
-15V, -27V
-12V
-12V
-11V, -16V
-11V, -16V
-11V,
-11V,
-11V,
-11V,

-16V
-16V
-16V
-16V

POWER
DISSIPATION

PACKAGES

350mW
350mW
350mW

8
8
14
14
14
8
40

Pin
Pin
Pin
Pin
Pin
Pin
Pin

300mW
400mW
400mW
400mW
360mW
360mW
360mW
360mW
360mW
360mW

14
14
40
28
16
16
16
16
16
16

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

52600/52601
ENCODER/DECODER
REMOTE-CONTROL 2-CHIP SET
Features

Small Parts Count -

o 3 Analog (LP Filterable PWM) Outputs

No Crystals Required

o
o
o
o

o Easily Used in LED, Ultrasonic, RF, or Hardo

wire Transmission Schemes
Very Low Reception Error

Low Power Drain CMOS Transmitter for
Portable and Battery Operation

31 Commands - 5-bit Output Bus with Data
Valid

Muting (Analog Output Kill/Restore)
Indexing Output - 2112 Hz Pulse Train
Toggle Output (On/Off)
Mask-Programmable Codes

Block Diagram

Pin Configuration

S2600 Encoder

S2600

GNO"VSS

DATA

(1SIOUTPUT

:SCjTEST
J

KEY

BOARD

INPUTS

Pin Configuration
S2601

Vss
POR

: r'l'::::;,
: J

7.3

SIGNAL INPUT

VOO"GNO

52600/52601

Functional Description
The 82600/82601 is a set of two L8I circuits which
allows a complete system to be implemented for remote control of televisions, toys, security systems,
industrial controls, etc. The choice of transmission
medium is up to the user and can be ultrasonic, infrared radio frequency, or hard wire such as twisted pair
or telephone.
The use of a synchronizing marker technique has eliminated the need for highly accurate frequencies
generated by crystals. The 82600 Encoder typically
generates a 40kHz carrier which it amplitude-modulates with a base-band message of 12 bits, each bit
preceded by a synchronizing marker pulse.
Bits 1 and 12 denote sync and end-of-message, respectively, bits 2 thru 6 constitute a fixed preamble which
must be- received correctly for the command bits to
be received, and bits 7 thru 11 contain the command
data. The 82601 Decoder produces an output only
after two complete, consecutive, identical, 12-bit
transmissions. Marker pulses, preamble bits, and
redundant transmissions, have given the 82600/
82601 system a very high immunity to noise, without a large number of discrete components.
82600 Encoder
The 82600 is a CM08 device with an on-chip oscillator, 11 keyboard inputs, a keyboard encoder, a shift
register, and some control logic. The oscillator
requires only an external resistor and capacitor, and
to conserve power, runs only during transmission.
Keyboard inputs are active-low, and have internal
pull-up resistors to VDD. When one keyboard input
from the group A thru E is activated with one from
the group F thru K, the keyboard encoder generates
a 5-bit code, as given in the table entitled «82600/
82601 CODING," below. This code is loaded into
a shift register in parallel with the sync, preamble,
and end bits, to form the 12-bit message.

The shift register is clocked once per bit frame, so
that its 12-bit message is transmitted once in 38.4
milliseconds. The minimum number of tranmissions
that can occur is two, but if the keyboard inputs are
active after the first 3.6 milliseconds of any 12-bit
transmission, one more 12-bit transmission will result.
Transmissions are always complete, never truncated,
regardless of the keyboard inputs.
The Test Input is usee} for functional testing of the
device. A low level input will cause the oscillator
frequency to be gated to the Data Output pin. This
input has an internal pull-up resistor to VDD.
82601 Decoder
The 82601 is a PMOS L8I device with an on-chip
oscillator, five keyboard inputs, a 40 kHz signal
input, and 11 outputs. The oscillator requires only an
external R and C. The five keyboard inputs are activelow with internal pull-up resistors to Vss; activation
of any two causes one of 10 possible 5-bit codes to
be generated and fed to the outputs of the 82601,
overriding any 40 kHz signal input.
Two counters, the signal counter and the local
counter, are clocked respectively by the signal input
and a 40 kHz signal from the local RC oscillator
timing chain. A 40 kHz input lasting 3.2 milliseconds
(Le., an initial bit frame) causes the signal counter to
overrun and reset both itself and the local counter.
At specific intervals thereafter, the local counter
generates pulses used to interrogate the contents of
the signal counter. Resynchronization of the counters
occurs every bit frame so that the interrogation yields
valid data bits even if the transmitter oscillator frequency has deviated up to ± 24% with respect to the
receiver oscillator frequency.

Decoded data bits from the next five bit frames
following the initial synchronizing frame are compared
with the fixed preamble code. The next five decoded
The transmitter output is a 40 kHz square wave of bits, the command bits, are converted to a parallel
50% duty factor which has been pulse-code-modulated format and are compared against the command bits
by (i.e., ANDed with) a signal having a recurring saved from the prior transmission. If they match, and
pattern, a bit frame of 3.2 millisecond duration. This if the preamble bits are correct, the command bits
bit frame is comprised of three signals: the 8tart are gated to the receiver outputs. However, a mismatch
signal which is 0.4 milliseconds oflogic "1"; followed causes the receiver outputs to be immediately disabled,
by the Data signal which is 1.2 milliseconds of the_ and the new command bits are saved for comparison
lowest-order shift register bit; followed by the Mark against the command bits from the next 12-bit transsignal which is 1.6 milliseconds of logic "0" (except mission. In the case where 2 identical, proper, 12-bit
in the first bit frame where Mark = 1 to facilitate transmissions are immediately followed either by
transmissions with erroneous preamble codes or by
receiver synchronization).
7.4

52600/52601

nothing, the receiver outputs will be activated during
the end -frame of the second transmission, and will be
disabled 45 milliseconds thereafter. In the rest (disabled) state the five Binary Outputs are at a "1" logic
level; when not in the rest state, one or more of the
open-sourced output transistors will conduct to VDD.
The Data Valid output is low during the rest state, and
high whenever data is present at the Binary Outputs.

can provide 64 distinct DC levels suitable for control
of volume, color saturation, brightness, motor speed,
etc. Each Analog Output increases its duty factor in
response to a particular Binary Output code and
decreases its duty factor in response to another code
- 6 codes in all. The entire range of 0% to 100%
duty factor can be traversed in 26 seconds or at a rate
of the oscillator frequency divided by 262,144. All
three Analog Outputs are set to 50% duty factor
whenever 01011 appears at the Binary Outputs.
Analog A is mutable; 01100 sets it to 0% duty factor.
If 01100 then disappears and reappears, the original
duty factor is restored. This of course implements the
TV "sound killer" feature.

The 82601 has five other outputs: Pulse Train, On/Off,
Analog A, Analog B, and Analog C. The states of these
outputs are controlled by the 10 particular Binary
Output codes which the receiver Keyboard Inputs can
cause to be generated. The Pulse Train output provides
a 2.44 Hz square wave (50% duty factor) whenever
11011 appears at the Binary Outputs, but otherwise
it remains at a logic "0". This pulse train can be used
for indexing, e.g., for stepping a TV channel selector.

The 82601 has an on-chip power-on reset (POR)
circuit which sets the Pulse Train and On/Off Outputs
to "0," sets the Analog Outputs at 50% duty factor,
and insures that Analog A is muted. No external
components are required to implement POR, but a
POR input has been provided for applications whprc
externally controlled reset is desirable, e.g., where the
power supply voltage rise time is extremely slow. The
POR input has an internal resistor pull-up to Vss; pulling it low causes a reset.

The On/Off ("mains") output changes state each time
01111 appears at the Binary Outputs. In TV applications the On/Off output is most often used to kill and
restore the main power supply.
Analog Outputs A, B, and C are 10 kHz pulse trains
whose duty factors are independently controllable.
With a .simple low-pass filter each of these outputs

Message Bit Format

~:J"'-----'In n___ n ______.___ .l~--_--_--_--_--_--_-_--_--_---_--_-_--~nl
_

START
ALWAYS
=1

0
16

MARK
liN SYNC BIT

= 0 OTHERWISE

C4L~~~S ~---48\2L~~~S---...3.~2m....sf-ec-----~6C:~~KS
- - - TYPICAL -----------~

...

DECODER DATA OUTPUT
= liN SYNC AND END BITS
= TRANSMITTED DATA
IN FRAMES2THRU 11
(PREAMBLE OR COMMAND)

128 CLOCKS/BIT
(TYPICAL CARRIER = 40kHz)
"1" MEANS PRESENCE OF A 40kHz CARRIER (SQUARE WAVE); "0" MEANS ABSENCE OF A 40kHz CARRIER (SQUARE WAVEl.

IF MESSAGE BIT = "1" THEN DECODER DATA OUTPUT = ENCODER DATA INPUT = "0";
IF MESSAGE BIT = "0" THEN DECODER DATA OUTPUT = ENCODER DATA INPUT = "I".

Message Format
FIRST PREAMBLE BIT = 0

~ =

\
INPUT KEYED
STARTED HERE ~
KEY INPUTS 1
PRESSED 0

OSC

S D

•

RUN
HALT -<

S D

40kHz
0

L......,f- ~r
SYNC
BIT

S 0

DON'T CARE

S D

(;

5 BITSOF
PREAMBLE

5 BITS OF
COMMAND

ILEND
BIT

MESSAGE ONE

L......j;.. ~ r-SYNC
BIT

10 BITS OF
PREAMBLE
& COMMAND
MESSAGE TWO

76.8msec
TYPICAL

7.5

OUTPUT
DATA= 1

OUTPUT
DATA= 0

DECODE OUTPUT OATA
TRANSMITTED MESSAGE

S D

END
BIT

---+

52600/52601

S2600/S2601 Coding
Transmitter
Kevboard
Input Pins
Tied to Vss

Receiver
Kevboard
Input Pins

T~:~ ~o~O~

AB
AF
AG
AH
AI
AJ
AK
BF
BG
BH
BI
BJ
BK
CF
CG
CH
CI
CJ
CK
OF
OG
DH
01

DJ
OK
EF
EG
EH
EI
EJ
EK

NOTES:

Resulting
Receiver
Binary
Dutputs
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

DE
CE

AD
BD

3
0
0
0
0
1
1
1
1
0
0
0
0
1
1

1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

5
0
1
0
1
0
1
0
1
0
1
0
1
0

Receiver Dedicated
Functions
(Mask programmable
except for rest state)

Increase Analog C pulse width
Decrease Analog B pulse width

RESET Analog (See Note 2)
MUTE (See Note 3)

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
0
1
1
0
0
1
1

Toggle On/Off Output

Increase Analog B pulse width
Decrease Analog C pulse width
Increase Analog A pulse width

Activate Pulse Train Output
Decrease Analog A pulse width
Rest State

1. Receiver keyboard inputs override any remote signal input.
2. Sets Analog A, B, and C waveforms to 50% Duty Factor.
3. First operation sets Analog A to 0% Duty Factor; second operation restores former Analog A Duty Factor.

Electrical Specifications - 2600 Encoder
All voltages measured with respect to Vss.
Absolute Maximum Ratings
Operating ambient temperature TA ................................................ a to + 70° C
Storage temperature ...................................................... - 65° C to + 150° C
Positive voltage on any pin .......................................................... +14V
Negative voltage on any pin ................................•.......................... - 0.3V
Electrical Characteristics
Unless otherwise noted, VDD = 8.5 ± 1.5V and TA =
Symbol

fa
MO/fO

IDD
Vrn
VIL
IIL
IOH
IQL

Parameter
Oscillator frequency
Frequency deviation
Supply current
Standby
Input "1" threshold
Input "0" threshold
Input source currrent
Output source current
Output sink current

Min.

7
-10

Typ.
640

a to +70°C.
Max.

2000
+10
2
10

25
50
1
-.2

50
50

75
200

1.5
-.5

Note: Circuit operates with VDD from 3.0V to 12.0V.

7.6

Units
kHz
%
rnA
JJ.A
%VDD
%VDD
JJ.A
rnA
rnA

Conditions
Rose = 12K, Case = 100pF
Fixed Rose, Case, VDD ± 10%
During transmission,
Data Output = 1mA
No transmission (25°C)
VI = OV
Vo = VDD -3V
Vo = +0.5V

52600/52601

Electrical Specifications - S2601 Decoder

All voltages measured with respect to VDD.
Absolute Maximum Ratings

Operating ambient temperature TA ............................................... 0° C to 70° C
Storage temperature ...................................................... - 65° C to + 150° C
Vss power supply voltage ........................................................... +31 V
Positive voltage on any pin ...................................................... Vss +0.3V
Negative voltage on any pin ....................................................... VSS =-31 V
Electrical Characteristics

Unless otherwise noted, Vss = 14 ± 4V and TA = 0 to +70°C
Symbol

Parameter

Min.

Typ.

Max.

Units

Conditions

fO
MO/fO
Iss

Oscillator frequency
Frequency deviation
Supply curren t

7
-10

640

2000
+10
50

kHz
%
rnA
rnA

Rosc = 71K, Cosc = 25pF
Fixed Rose, Cosc, Vss
No loads, VDD = 18V
VDD = 10V

%VSS
%Vss
%Vss

Signal Input:
"1" threshold
Vru
"0" threshold
VIL
Vrn-Vn.. Vol tage hysteresis
Keyboard and POR Inputs:
"1" voltage
Vru
"0" voltage
Vn..
Source current
In..
Debounce delay
(Keyboard inputs only)
Binary Outputs (open source):
Sink current
IOL
Duration
Analog Outputs (open drain):
!::'Vstep Step Voltage change
Source current
IOH

34
28

30
5
Vss -.5
50
1.45

-1.28
- 0.50
34.9

1.0
Analog step rate
fstep
Data ValId, Pulse Tram, and On/Off Outputs:
Source current
1
IOH
Sink current
- 40
IOL
Risetime (.1 Vss to .9 Vss)
tr
Falltime (.9VSS to .1 Vss)
tf

70
48

35
Vss-3.0
150

Vs's - 5.5
300
2.2

V
V
J.lA

VI = VSS -lOV

msec

- 0.60

rnA
rnA
msec

Vo=Vss - 5.2V, Vss=18V
Vo=Vss - 5.2V, VsS=10V
fO = Max = 704 kHz

Vss/64
1.04
1.15
1.2
10

V
rnA
rnA
rnA
kHz

Vo=VSS'" 0.5V, Vss=lOY
Vo=VSS - 0.5V, Vss=18V
Vo=Vss -1 V
(fO -;- 64)

1.5
- 50

rnA
J.lA

10
10

Note: Circuit operates with Vgg from 7.0V to 30.0V

7.7

J.lsec
J.lsec

Vo = Vss - 2V
Vo = .. 7V
RL = 00, CL 50pF
RL = 00, CL 50 pF

52600/52601

Circuit Application

18
3
4
5

VOO

C
6
,--0
7
-E
9
F
10
G
11
H
12
I
13
J
14
K

RC
OSC

OSC
TEST

+V= 10TO 18VOC

'LtJ

0
0

'"~

12K

mOe'

+f-J.
50pF

33K

15
-NC

VSS

BOI
B02

___1~3_

B03

POR

B04

.".

DATA
OUT

VSS

KEYBOARD

TRANSMISSION
MEDIUM

r-<

,----'~

t·· ·

1
11

>------------- RC

8
7

~
5

B05
SIG
IN
KIA
KIB

j. ,,"'

14
17

DATA

WORD

16
3

DATA VALID

'"
'"~

0/0

----- 4
~-r~~

______~33

02ul

01ul

NOTE: DIODES ARE IN914

+9 VOLTS

Figure 1. Schematic of Typical Application

Figure 2. Schematic Program of Percussive Output

8.6

RI10

AUDIO
OUTPUT

S2000
MUSIC
APPLICATION

9VP-P

6.3V p.p

1
Figure 3. Sawtooth Outputs

YES

Appendix A. System Flow Diagram

8.7

Appendix B. Note Subroutine Flow Diagram

8.8

A.M.I. 82000 ASSEME~ER
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",.

TYPICAL VALUES
B
",.

......

Zl:

lN4742 ZENER 12 VOLT Ro: 10MSI

Rl:
0,:

RT: 10Kil
150S1 02: 2N4401
2N4401 R,: 10Kn, R2: JOKn, R3: 2.7KS2

R.:
2.4Kn, Rs: JOKn, Rs: 5.1 Kn
DR,DT:2N414J
01·04: lN4004
2500 NETWORK
X ~ HOOK SWITCH CONTACTS

Xl AL: J,579545MHz
C,: ,001"F

R2~

tE---

tl!--

.2!!

2 XMIT

C.~
OSCi

RO" XTAL

10 MUTE

'""

1 VOO

R,
S

C,~

"'Q

S25590

16 TONE
OUT

'<.V

C,.~

OSC,

Performance Evaluation

Figure 4 shows a test circuit suitable for these
measurements. Note that the circuit allows simulation
of DC Loop Conditions only. With this circuit, loop current can be varied over the range of 20mA to BOmA.

The two major criteria in the evaluation of the Digital
Tone Generator in the telephone application are 1) the
Amplitude/Loop Current characteristic, and 2) Distortion.

Figure 4. Bench Method for Measurement of Amplitude and Distortion Performance

50. Fll00V
WAVE ANAL YZER

H·P TYPE 3581A

SPECTRUM ANAL YZER

H·P TYPE 3580A

x Y PLOTTER

H·P TYPE 7046A

XOUT

XY
PLOTTER

SPECTRUM
ANALYZER

TONE
GENERATOR
DEVICE
TEST
CIRCUIT
OR
OTMF

ANAL YZER

600"

I",
Y,N

TELEP~ONE

YOUT

Amplitude Loop Current

Figure 5. Typical Amplitude/Loop Current Plot
for Circuit of Figure 2

-2

Figure 5 shows a typical plot of amplitude vs loop current superimposed on the recommended AT&T specification (ref. 1) obtained using the circuit of Figure 2
with RT = 1500 (external emitter follower stage disconnected) in the test configuration of Figure 4. The absolute amplitude can be increased or decreased in a
variety of ways. One way is to vary RL. RL typically
will be in the range of 100 to 2000. Increasing RL tends
to decrease amplitude but improve distortion. Another
alternative for increased amplitude is to use a bypass
capacitor across RL. This, however, tends to increase
distortion. An emitter-follower transistor can be connected on the tone output. This allows increased amplitude and reduced distortion at the same time. These
alternatives are shown in Figure 6. Use of the extra
emitter-follower stage, however, decreases the amplitude slope characteristic. In general, a trade-off between amplitude, amplitude slope and distortion is
necessary.

-3

-4

RT = 150£2

,1-

~
~

-8

'.::

", , ,

700Hz

4?t;-,

,
"-

,
0.,,;',
,o-9~;,,,-

(~V~~"
(OJ;, ,

,0-9',

-10

-11

,
"-

(~v',

4,t/1<',

-9

LOOP CURRENT (mAl

,
70

---+_

Figure 6. Alternatives for Increasing Amplitude
v"I--_ _ _-,

I-----<..--_~
V

Vss

TYPE 2N4401

b) INCREASES AMPLITUDE,

8) INCREASES AMPLITUDE BUT
INCREASES DISTORTION AND
DECREASES AMPLITUDE SLOPE

REDUCES DISTORTION BUT

DECREASESAMPlITUOESlDPE

Distortion

where VL and VH correspond to the rms voltage levels
of the low group and high group signal components in
the dual tone signal and Vi is the ith extraneous (either
intermodulation or harmonic) component in the voiceband (500Hz to 3400Hz). Individual component
amplitudes in dB can be readily read off from the spectrum plot, converted to (rmsv)2 by the use of the conversion chart shown in Table 1. Distortion is then
calculated by use of equation (1), above.

The AT&T specification (ref. 1) reads "The total power
of all extraneous frequencies in the voiceband above
500Hz accompanying the signal should be at least 20dB
below the level of the frequency pair." The key words
here are the total power, voiceband and level of frequency pair. The voiceband is normally defined to be
300Hz to 3400Hz. Therefore, the total power of all extraneous components in the 500Hz to 3400Hz is of interest. The measurement of total power is not easy. To
measure it precisely, first the total power of the DTMF
signal with extraneous components in the 500Hz to
3400Hz band should be measured. The DTMF signal
then should be removed by use of two notch filters
centered around the appropriate low group and high
group frequencies and the total power measured again.
The ratio of the two readings gives a measure of distortion. An alternative is to plot a spectrum of the dual
tone waveform and compute distortion using the
following formula.

Figures 7 and 8 show typical spectrum plo'ts obtained
in the test circuit of Figure 4 on a S2559D device in the
circuit of Figure 3. Detailed distortion calculations on
these spectrum plots are shown in Tables 2 and 3. The
results show the distortion at 20mA loop current to be
- 24.9dB and at 30m A loop current - 36.3dB. It is
evident that distortion decreases rapidly as the supply
voltage increases and as the modulation of the supply
voltage decreases.
A rule of thumb for quick estimate of distortion is: As a
first approximation, distortion in dB equals the difference between the levels in dB of the extraneous
component with the highest amplitude and the low
group signaI' component; or
Dist. (dB) = Vih (dB) - VL (dB)
(2)
Using this rule of thumb gives estimates of -25dB and
- 37dB respectively for the loop currents of 20 and
30mA which are close to the computed values of
-24.9dBand -36.3dB.

Table 1. dB to (rmsV) and (rmsV)2 Conversion Chart
dB
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-6.0
-6.5
-7.0
-7.5

(IImV)
0.8913
0.8414
0.7943
0.7498
0.7079
0.6683
0.6309
0.5957
0.5623
0.53088
0.5012
0.4732
0.4467
0.4217

(rsmV)!
0.79433
0.70795
0.63096
0.56234
0.50119
0.44668
0.39811
0.35481
0.31623
0.28184
0.25119
0.22387
0.19953
0.17783

(rsmV)!

(ramY)

(rsmY)!

(rsmV)

(rsmV)!

-20
-21
-22
-23
-24
-25
-26
-27
-28
-29

0.1
0.089
0.07943
0.0707
0.063
0.0562
0.050118
0.0446
0.0398
0.03548

0.0100000
0.0079433
0.0063096
0.0050119
0.0039811
0.0031623
0.0025119
0.0019953
0.0015849
0.0012589

-33
-34
-35
-36
-37
-38
-39

0.02238
0.01995
0.01778
0.01584
o.di 4125
0.01259
0.01122

0.0005012
0.0003981
0.0003162
0.0002512
0.0001995
0.0001585
0.0001259

~30

0.03162
0.02818
0.0251

0.0010000
0.0007943
0.0006310

0.01
0.0089
0.00794
0.00707
0.0063
0.00562

0.0001000
0.0000794
0.0000631
0.0000501
0.0000398
0.0000316

0.005011
0.00446
0.00398
0.00354
0.00316
0.002818
0.00251
0.00223
0.00199
0.00177
0.00158
0.0014125
0.001259
0.001122

0.0000251
0.0000199
0.0000158
0.0000126

-40
-41
-42
-43
-44
-45

-46
-47
-48
-49
-50
-51
-52
-53
-54

-31
-32

(rsmV)

C)n

~55

-56
-57
-58
-59

O.OOOOlOU
0.0000079
0.0000063
0.0000050
0.0000040
0.0000032
0.0000025
0.0000020
0.0000016
0.0000013

Figure 7. Typical Spectrum Plot of a 525590 Device in Circuit of Figure 3 with Test CKT of Figure 4
VH 1-2.51

lOOP CURRENT" 20rnA

-10

-20

-30

.;:

:1
-40 t--

-!#

.;:

.;;

;;

.;:

-50

;::

,;;'

-60

r-..

-70

\..

0.5

1.0

1.5

2.0

2.5

3.0

L.J

3.5

4.0

4.5

5.0 KHz

Figure 8. Typical Spectrum Plot of a 525590 in Circuit of Figure 3 with Test CKT of Figure 4
LOOP CURRENT" 30rnA

-10

t--

-20

t--

-30

-40

-50

-60

-70

0.5

1.0

1.5

2.0

2.5

8.21

3.0

3.5

4.0

4.5

5.0 KHz

Table 2. Distortion Calculations for Spectrum of Figure 7

Table 3. Distortion Calculations for Spectrum of Figure 8

Device: S2559D in Circuit of Figure 3, Test Circuit Figure 4,
20mA Loop Current

Device: S2559D in Circuit of Figure 3, Test Circuit Figure 4,
30mA Loop Current

Component

Measured
(dB)

VL
VH

-5.5
-2.5

V1
V2
V3
V4
V5
V6
V7
Va
Vg
V10
V11
V12
V13
V14
V15

-31
-57
-47
-42
-57
-38
-30
-50
-34
-41
-46
-38
-56
-47

rmsV
INV log dB
20

(rmsV)2

· 2 81 84
· 5 62 34
· 0 00 79 43
.0 00 00 20
· 0 00 01 99
· 0 00 06 31
· 0 00 00 20
· 0 00 1 5 85
· 0 01 00 00
· 0 00 01 00
· 0 00 39 81
.0 00 07 94
· 0 00 02 5 1
.0 00 1 5 85
.0 00 00 25
· 0 00 o 1 99

VL
VH

-6.0
-3.0

V1
V2
V3
V4
V5
V6
V7
Va
Vg
V10
V11
V12
V13
V14
V15

-46
-53
-46
-51
-44
-48
-47
-53
-52
-51
-47

rmsV
INV log dB
20

(rmsV)2

· 25118
· 5 o1 1 8
.0 00 02 5 1
· 0 00 00 50
· 0 00 02 51
.0 00 00 79
· 0 00 03 98
· 0 00 o1 58
.0 00 o1 99
· 0 00 00 50
.0 00 00 63
.0 00 00 79
· 0 00 01 99

E(Vj)2

· 0 02 73 33

E(Vj)2

i=1

o 1 777

i=1
· 8 44 1 8

(VL)2 + (VH)2

DIST

Measured
(dB)

Component

ji=l~ {V.)2
I

= 20 log -;::.=======

J (VL )2+(VH )2

j i=l~ (V·)2
I

DIST = 20 log-'-;:,::::::::=====
V (VL )2+(VH)2

= 10 {lOg [j~l (Vj)2] - log [(VLl2+(VH )2J )

= 101IOg L~l (Vj)2]- log [(VL)2+(VH)2])
=

10 {-2.56 -(-0.074)}

=-24.9dB (5.7%)

Other Considerations

The supply voltage available to the Tone Generator is
a function of the DC loop current flowing through the
telephone network and the DC impedance presented
by the network. The insertion of the diode bridge and
voltage drop in the transformer winding further
reduce the available voltage. Typically, the DC voltage
available to the device is 1.7 volts less than that

· 7 52 36

(VL)2+(VH)2

10 {-3.75 - (-0.124)}

=-36.3dB(1.5%)

measured at the TIP and RING terminals. The instantaneous minimum voltage as seen by the device. is even
smaller because of the DTMF signal riding on the DC
component. The instantaneous minimum voltage can
be expressed as V min =V de - Vae (peak). Because, the
signal amplitude is larger at lower loop currents, i.e.,
at lower DC voltages, the instantaneous minimum
voltage is significantly less than the average voltage
measured across the device. This causes higher distortion at lower loop currents.
8.22

The DC voltage across the device is under the
designer's control during DTMF dialing. The AT&T
specification (ref. 1) recommends a minimum DC
voltage of 6 volts (4 volts preferred) across the TIP and
RING during voice and initial off-hook condition at a
loop current of 20mA. However, during DTMF dialing,
the DC voltage is permitted to increase to 8 volts (6
volts preferred). The designer can take advantage of
this specification to insure adequate voltage across the
device at low loop currents. Even with a preferred 6
volt specification, allowing for 1.7 volts drop in the
bridge and transformer winding, the average voltage
across the device will be at least 4.3 volts. The instantaneous minimum voltage will not drop significantly
below 3.6 volts, assuring good distortion performance
down to lower loop currents. The voltage across the
device can be increased by allowing the telephone DC
impedance to increase during DTMF signalling. Since
the microphone is switched out during signalling, this
is directly a function of the DC current drawn by the
device. Since the DC current required by the device is
low, it is primarily a function of the load RL. Increasing
RL will increase the DC impedance and thereby increase the average supply voltage, thus reducing
distortion. Increasing RL, however, reduces signal
amplitude so a trade off has to be made between amplitude and distortion.

less than 1mS. It should also be noted that the zener
diode and the device are behind the network transformer winding and not directly across the telephone
terminals. These considerations allow selection of a
wide range of zener diodes as protection elements. A
zener diode of the type 1N4742 may be adequate in
most cases.
Ancillary Interface to Phone Lines

The Digital Tone Generator can be used in ancillary
station apparatus (such as alarm reporting devices,
automatic dialers, data terminals, etc.) for tone dialing
or low speed data transmission applications. A transformer interface, such as that shown in Figure 9, can
be used. Consideration must be given to the device
latch up possibility due to induced voltage spikes in the
transformer winding connected to the tone output.
Latch up can be prevented by diode clamping the tone
output to VDD and Vss.
Figure 9. T.ansformer Coupled Phone Interface
Voo 1

Consideration should also be given to insure adequate
base drive to the external transmit and mute transistors when operating at low loop currents if electronic switching is used.

PHONE
LINES

Transient Voltage Protection

An important consideration in the design of electronic
equipment to be connected to the telephone network is
that adequate transient voltage protection circuitry
must be incorporated such that the equipment can
withstand lightning surges without causing harm to
the telephone network. In particular, all equipment
must meet the metallic and longitudinal surge voltage
specifications outlined in the FCC part 68 (ref. 2),

600/900 OHMS TRANSfORMER

01,02: 1N914 TYPE OIOOES

Precise Dial Tone Generator

The Digital Tone Generator can be used in other single
or multi tone applications by selecting a crystal of appropriate frequency. The precise dial tone is defined to
be a multifrequency tone consisting of 350Hz and
440Hz. By selecting a crystal of 1.3071124MHz, a dial
tone of 346Hz and 444Hz can be obtained by activating
the R4, C1 inputs of the device.

When aplied to tone generator interface circuits, such
as those in Figures 2 and 3, transient voltage protection requires proper selection of components for the
diode bridge and the zener diode. It is necessary that
the diode bridge utilize high voltage breakdown and
high current capacity diodes. 1N4004 type diodes may
be adequate but higher rated diodes might be required.

References

Ref. 1:

Selection of the zener diode depends upon its transient
response characteristic. A slow zener diode will not
clamp voltage to its rated value. However, it should be
noted that the S2559 Tone Generator can withstand
pulse voltages that exceed the absolute maximum continuous DC voltage ratings (10.0V for S2559C, D; 13.5V
for S2559A, B). Typically, the S2559 devices can withstand up to 20 volts of pulse voltages for durations of

Bell System Communications Technical Reference (PUB 47001). Electrical Characteristics
of Bell System Network Facilities at the Interface with Voiceband Ancillary and Data
Equipment. August 1976.

Ref. 2: Rules and Regulations, FCC part 68. Connection of Terminal Equipment to the Telephone
Network. July 1977.
o

'1':)

Apelication

AMI

Note

_ _ _ American Microsystems, Inc. _______________________________

Touch Cont rol™ Ci rcu its
For Capacitance Switching

complex logic such as microprocessors. All outputs may be
used to drive a variety of logic levels such as MaS, CMOS,
and TTL.
TouchControl panels may be constructed from many
different materials, offering the engineer flexibility in his
design. Commonly used panel materials are glass, printed
circuit board, plexiglass, and polycarbonate. Selection of a
particular material depends on the intended application, as
discussed later in this note.
Technical specifications for all seven TouchControl
circuits may be found in two data sheets. One describes the
S9260, S9261 , S9263, S9264, and S9265; the S9262 and
S9266 are included in a separate data sheet.

INTRODUCTION

As more manufacturers turn to solid state electronics to
enhance the reliability and performance of their products, the
need arises for more reliable, noise-free, non mechanical
switches to control these products. To satisfy this need, AMI
offers a series of seven MaS TouchControl circuits that will
interface directly with a stationary panel to create a capacitive,
nonmechanical switching system. The individual capacitors, or
touch switches, are formed simply by conductive areas screened
or etched onto the panel's front and rear surfaces; connections
between the panel's rear surface and the TouchControl interface circuit create the capacitance switches. As many as 32
touch switches can be implemented with a single TouchControl
interface Circuit.
Outputs from the S926X series are offered in two configurations: S9260, S9261, S9263, S9264, and S9265 have an
individual output associated with each input; the S9262 and
S9266 outputs are encoded in binary for use with more

' \ SURFACE A \

SWITCH 1

KEYBOARD SCANNING DESCRIPTION
A TouchControl switch panel consists of a single sheet
of a rigid material with conductive surfaces applied on both
sides as shown in Figure 1.

~- SURFACE"
SURFACE C ~
"

SURFACE A

~ ~URFACEB
SWITCH 1

l----I

SWITCH 2
SCl

57610

SWITCH 2

ELECTRICALLY EQUIVALENT SCHEMATIC
SIDE VIEW

VIEWED FROM
FRONT SURFACE

SWl
SW2
SCl
VIEWED FROM
REAR SURFACE

FIGURE 1 CONSTRUCTION OF A TWO SWITCH TOUCHCONTROL PANEL
WITH EQUIVALENT ELECTRICAL CIRCUIT

K24

Regardless df the selected panel material, a touch switch
is formed by applying a single conductive area to its front
surface with two other conductive areas applied directly in line
on the reverse side of the panel. Figure I shows three views of
a typical touch panel containing two TouchControl switches.
On switch one, conductive surface A is applied to the front of
the panel and is the surface to be touched to effect a switch
"closure." Surfaces Band C are applied directly in line with A
on the opposite side of the panel. Surface A should cover
completely and may overlap surfaces Band C so that a capacitor is formed between "plates" B and A and another between
A and C. This forms two capacitors connected in series, their
common connection point being the surface to be touched to

effect switch operation. For all non-mUltiplexed parts, all "C"
surfaces are connected to the SCI output. Multiplexed parts
(S9262, and S9266) will be discussed later.
Shown in Figure 2, the SCI output appears as alternating sets of 16 pulses. The peak·to-peak voltage of the SCI
output is approximately equal to the VDD supply level, and
the logic 1 (negative) level duration is twice the period of the
oscillator frequency at pin 18. Since the SCI logic a level
between two adjacent pulses lasts one oscillator period, then
the duration of all 16 pulses is ( 2 + 1) x 16 = 48 oscillator
periods. Following the 16 pulses, a logic a level appears for a
duration of 96 oscillator periods before the next series of
16 pulses commences.

~NUt
----------------f

VINT

L--------_~r------t_"H SCl
VC=CLOCK VOLTAGE
VINU=PK. TO PK.INPUT SIGNAL
(SWITCH UNTOUCHED)

15 •

S9263

VINT=PK. TO PK. INPUT SIGNAL
(SWITCH TOUCHED)
Cp=CAPACITANCE OF TOUCH PAD
CB=HUMAN BODY CAPACITANCE
(WORST CASE ~ 50 PF.)
CS=STRAY CAPACITANCE AT CHIP
INPUT, INCLUDING CHIP INPUT
CAPACITANCE WHICH IS APPROX·
IMATEL Y 6 PF.
777231

FIGURE 2. KEYBOARD SCANNING WAVEFORMS

100KHz

r-----~------~~------------~----------------------------------~

50KHlr-------------~~------------~~----------------------------~~~

200KU

lOOKE

300KS2

400KS2

RESISTANCE ON RC INPUT.

777232

FIGURE 3. CURVES FOR TYPICAL RC VALUES FOR SCANNING FREQUENCY

The oscillator period is determined by the external RC
time constant with values for Rand C shown in Figure 3. Note
that, if several TouchControl interface parts are used in a given
system, all RC pins may be connected together to a single
RC time constant.
Each of the 16 pulses in the SC 1 signal corresponds to
an individual "I" input to the interface circuit. Figure 2 shows
the input IS for both the untouched (VINU) and touched
(VI NT) conditions. The SCI signal is coupled through to input
IS through the two touch panel capacitors, Cpo Note that
instead of observing 16 pulses at the 15 input as might be
expected, only one pulse appears for every 16 SC 1 pulses;
this is because of an active device on the MaS circuit that
grounds the 15 input at all times except for the duration of the
sixth of the 16 pUlses. (This technique allows the input conductors to be run close to each other, as described in the section
on "Proximity of Clock and Input Lines.") It is during this
sixth pulse that the touch switch connected to the 15 input is
interrogated. (The first SCI pulse related to 10, the second to

11, etc.) With the switch untouched, the voltage of the single
pulse at IS will be dependent on the ratio of Cp (touch switch
capacitance) to Cs (input stray capacitance, usually equal to
MaS input capacitance). For example, if VDD = - 15 volts
and Cp = CS, then VC = 15 volts, and VINU = 5 volts. When
the capacitive switch is touched, capacitor CB (human body
capacitance) loads the signal to ground; in this condition, the
higher VINU level decreases to a lower VINT level, and the
MaS comparator circuitry detects the change, causing the
appropriate output to occur. For every set of 16 pulses on the
SCI output, the circuit scans all 16 switches. Although the
values of VINU and VINT depend on all capacitances involved,
typical values might be VINU = 5 volts; VINT = 1 volt. Calculation of these values, required to insure a reliable system deSign,
is described in the section on "Capacitance Calculations."
Keyboard scanning behaves iden tically in the S9264 and
S9265. The S9260 and S9261 scanning is similar, although
only seven inputs are available instead of 16.

The S9266 employs a 2 x 16 matrix to scan 32 touch
switches. One set of 16 switches is clocked by SC 1 and the
other by SC2, as indicated in Figure 4. The first switch and the
seventeenth switch share input IO, the second and eighteenth
share input 11, etc. Every group of 16 pulses appearing on the
SCI output is followed immediately by a group of 16 identical
pulses on the SC2 output. Following the 16 SC2 pulses, both
outputs remain at a logic 0 level for a time equal to one set of
16 pulses, after which time the pulses on SCI again commence.
The S9262 device is similar to the S9266 , except that its
matrix of 2 x 7 (i.e. SCI and SC2 by seven inputs) scans 14
instead of 32 touch switches.

SWITCH

H~~

I-SC "

SWITCH

H~~

I
I
I

SWITCH

S9266
115

SWITCH

~~~
SWITCH

I
I
I
SWITCH

H~i

SC2

I--

NOISE IMMUNITY
Just as mechanical switches have a certain amount of
contact bounce associated with them, capacitance switches have
the same inherent problem. This contact bounce, or noise,
occurs as a finger makes contact with or removes contact from
the touched switch surface. All seven TouchControl interface
parts contain circuitry to prevent this "contact bounce" from
appearing on any output.
As discussed in the section on "Keyboard Scanning," the
S9263 scans all 16 keys in the time required for 48 periods of
the oscillator, and a total of 96 additional periods are required
before the scan begins again. During the first 48 of these 96
additional periods, the SC2 output scans its 16 key inputs.
Thus, for any of the seven parts, a complete scan of the keyboard occurs in 48 + 96 = 144 periods of the RC oscillator.
After every 23 of these complete keyboard scans, a signal is
generated on the circuit that clocks the most recent scan information into 32 two-bit shift registers (one for each of 32
switches). Thus, this load pulse occurs every 144 x 23 (=3312)
oscillator periods. If a logic one level is loaded into the first bit
of one of the registers, indicating a touched switch, no change
in output condition occurs, because the second bit of the
register is at a zero level. When the next load pulse is generated
3312 periods later, however, if the switch is still touched,
another logic one level is clocked into the register, and a one
level is transferred from register bit one to register bit two;
since both register bits are n0"Y "ones," the output is allowed
to change state. This means that a minimum of 3312 and a
maximum of 6624 oscillator periods are required between the
touching of any switch and the changing of any output condition. For an oscillator frequency of 90 kHz, for example, an
average of 55 ms of debounce time is obtained. The same
debouncing method is applied to the release of any touch switch.

777233

FIGURE 4. 2 X 16 MULTIPLEXED MATRIX WITH
S9266 INTERFACE CIRCUIT

8.27

DETERMINA TION OF TOUCH SWITCH SIZES
Because one of TouchControl's major advantages is the
versatility it offers the design engineer, the actual size of the
TouchControl switch becomes an important consideration. As
shown in Figure 1, a TouchControl switch consists of three
conductive areas, one of which is applied to the front surface
of a panel. The other two areas are each slightly less than half
the area of the first and are located directly behind on the
rear side of the panel so that each forms a capacitor, Cp , with
the larger conductive area on the front surface of the panel.
To insure a reliable TouchControl system, it is important
that each of these capacitors, Cp ' has the required capacitance
value. This value depends on a number of factors such as power
supply, reference voltage, scan clock voltage, and input stray
capacitance; it is discussed in detail in the section on "Determining ReqUired Capacitance Values."

Mter determining the required value for Cp , it is then
easy to calculate the area of the touch switch from the relationship,
- 0.225 KA
Cp t
in which K is the relative dielectric constant of the panel
material, A is the area in square inches of one of the two rear
surface conductive areas, and t the panel thickness in inches.
This equation calculates Cp in picofarads. Figure 5 provides
some nomographs for quick determination of pad area. Since
two of the three variables in the equation, K and t, depend
entirely on the touch panel, it is clear that the selection of the
panel material entails some electrical as well as aesthetic consideration. Touch switches of small area can be formed by
choosing a panel material of high dielectric constant and minimum thickness.

1.0

.--------,------~

~
~

CL:

15
Cp (picofarads)
t = 0.062"

Cp (picofarads)
t = 0.125"
1.0 . - - - - - - - - - - - - - 7 1

Cp = 0.225 KA
K = Dielectrrc constant of
panel material
T = Panel thickness
A

Area of each of the
two rear surface
conductors.

Cp (picofarads)
t = 0.031"

777234

FIGURE 5. DETERMINATION OF CAPACITANCE, Cpo

8.28

A typical touch switch area calculation might take these
steps: From the information determined in the section on
"Determining Required Capacitance Values" it is discovered
that a particular system requires 7 picofarad Cp capacitors.
The panel material is to be a .062 inch thick printed circuit
board with a dielectric constant of 5.0. From the relationship
Cp - 0.225 KA
t

it is seen that an area, A, of 0.386 square inches is required for
each of the two rear surface conductors. If the touch switch
area is to be approximately square, then each of the two rear
surfaces must have a length about twice its width. Each rear
surface conductor can be 0.44 x 0.877 inches, giving an area
of 0.3 86. Separating the two conductors by 0.125 inches, the
area required for the front surface touch switch then, is
(2 x.44 + 0.1 is) by .88 or 1.0 x 0.88 inches.
Of c~urse the touch switch can be designed in many
different shapes by altering the dimensions of the three conductors, keeping the rear surface areas constant and insuring
that each rear surface conductor is "covered" completely by
the front surface conductor (touch pad). If, in this example,
the 1.0 x 0.88 inch touch switches are too large, there are
several options available. The most obvious would be to use a
thinner panel material to increase the Cp capacitance, allowing
the switch areas to be smaller. Another alternative is to increase
the scan clock voltage, as described in the section on "Determining Required Capacitance Values," to allow the use of
smaller Cp capacitors.

DETERMINING REQUIRED CAPACITANCE VALUES
What is required for a reliable TouchControl system is
that the peak-to-peak signal level appearing at any "I" input of
the interface IC be equal to or greater than a certain value
when the switch is untouched and equal to or less than another
fixed value when the switch is touched. It is this variation in
amplitude that causes the circuit to recognize whether or not
a switch is being touched. Referring to Figure 2, the higher
voltage level appearing on an input and caused by an untouched
switch has been designated VINU The lower level, VINT,
occurs whenever the switch is touched. It can be seen that the
VINU level is determined by the peak-to-peak scan clock output level, VC, the value of the series touch capacitors, Cp , and
the value of stray capacitance, CS, at the input to the circuit.
The VI~n level is affected by all these parameters plus the
value of human body capacitance, CB, which ranges typically
from 100 to 200 picofarads with a typical minimum value of

Q ?Q

50 pF. Because most of the capacitances involved are on the
order of 10 pFs or less, it is not meaningful to measure VINU
to VINT with conventional equipment. However, it is possible
to calculate their values accurately, given VC, Cp , CS, and CB,
and these calculations are the first steps in determining the
required touch capacitors for a given system. The simplest
approach is to assume a Cp value and then determine VINU
and VINT.
To calculate VINU and VINT for all conditions:
_ Cp Vc
VINU - Cp + 2CS
VINT -

C 2VC
P
Cp + CpCB + CSCB + 2C p CS
2

As already stated, VINU must be equal to or greater than
a specified value, and VINT must be equal to or less than
another specified value. What these values are is determined by
the use of the input pin labeled VREF. This pin is used to
establish a reference voltage which the internal comparator
compares against the "I" input voltage levels to determine if a
switch is touched. In some cases it is possible to connect the
VREF pin to ground (VSS). In others, it may be beneficial to
set VREF, using two resistors, to a value that is 20 percent of
the VDD supply level. If VREF is connected to ground (VSS),
then VINU must be ~ 4.0 volts and VINT must be ~ 1.3 volts.
If these two conditions are met, the resulting TouchControl
system will operate satisfactorily.

In many proposed TouchControl systems, calculations
of VINU and VINT will indicate that the range of 4 to 1.3
volts is difficult to achieve due to high Cs capacitance or the
need for small switches. In such cases it may be beneficial to
use the VREF input to provide a reference voltage for the internal comparator. This comparator typically operates over a
VREF range of from - 2.5 volts to - 3.8 volts. Whenever VREF
is within this range, the TouchControl system will function
properly under the conditions: VINU ~ VREF + 1.0 volt and
VINT ~ VREF - 0.5 volt.
If the VREF voltage is derived from the VDD supply
voltage using two resistors as a voltage divider, an additional
advantage is obtained. As VDD varies, the Vc level (SCI output level) changes, and so does the VREF level. This causes the
VREF level to track the scan clock voltage, making the circuit
less vulnerable to supply fluctuations. If, for example, VREF
is set to a value 20% of the VDD supply voltage, then as the
supply, and hence VC, varies from - 13.5 to - 18.0 volts,
VREF will vary from - 2.7 to - 3.6 volts, remaining within the

comparator's operating range. Setting VREF equal to 20% of
the VDD (or VC) level, the following expressions will insure a
functioning TouchControl system:
UNTOUCHED
SWITCH CONDITION
VINU >VREF + 1.0
VREF = .2 Vc

TOUCHED
SWITCH CONDITION
VINT .2VC +1.0

Cp 2VC

--------C~+CpCB+CSCB+2CpCS

Cp +2CS

<.2 VC-0.5

or
CP

Cp + 2CS

Cp 2

>.2+ J

<.2 - 0.5

C~+CpCB+CSCB+2CpCS

'VC

From these expressions, it can be seen that the required
Cp value is highly dependent on the stray capacitance at the
TouchControl input, and only slightly on the fluctuation of
the Vc level. It is also of interest to note that, in both cases,
the "worst case" condition is the lowest expected Vc value,
and the highest expected Vc value is irrelevant. For calculation
of the required touch switch capacitance, Cp , for a given input
stray capacitance, CS, reference can be made to Figure 6. These
curves may be used for any TouchControl sy'stem in which the
reference voltage is set to between 18 and 22 percent of VDD,
VDD is within the specified limits of - 13.5 volts to - 18.0
volts, and Vc, the peak-to-peak scan clock voltage, is determined by the SCI output (Le., Vc = VDD and no external
amplification of Vc is used). The upper curve represents the
case where the switch is touched, and the lower corresponds to
the untouched condition. Operating TouchControl between
the two curves results in a properly functioning system.

25
TOUCHED SWITCH
CONDITION

E:
8LJ.J

VDD = Vc = -13.5 VO LTS
VREF = .2VC ± 10%
BODY CAPACITANCE = 50pFs.

'=
u

;;:

;3
::t:

15
"-UNTOUCHED SWITCH
CONDITION

~
::t:

:::>
0
f-

'"
LJ.J

40
Sl RAY CAPACITANCE, Cs ON I INPUT TO INTERFACE CIRCUIT (picofarads)
777235

FIGURE 6. Cp VS. Cs FOR Vc = VDD

As a specific example, assume that a proposed TouchControl system is to be implemented on a printed circuit board.
The traces that connect the individual switch areas to the I
inputs are to be arranged on the board such that the longer
traces contribute 4 pF to the stray input capacitance, while
the shorter traces contribute only I pF. Since the MOS input
capacitance is typically 6 pFs, then the total stray capacitance
on any input, CS, will vary from (1 + 6 pFs) to (4 + 6 pFs), or
7 to 10 pFs. Referring to the curves in Figure 6 again, it can be
seen that the system will function over the 7 to 10 pF Cs range
if a touch capacitor, Cp , is chosen between 8.2 pFs and
14.5 pFs. Now that the required Cp capacitance is known, the
switch area can be determined from the relationship

- .225 K A
CP - - - t as previously discussed. If the resulting switch area is too
large for the intended application, it is possible to decrease the
required Cp value by increasing the Vc scan clock level. This
is discussed in the following section.
INCREASING SCAN CLOCK VOLTAGE
As has been described, the capacitance required for
TouchControl switches, and hence the area required for the
switches, is dependent on input stray capacitance, CS, human
body capacitance, CB, and the scan clock output level, VC. If
it is necessary in a given system to use small switches, or if the
Cs loading is high, it is possible to reduce the required touch
pad capacitance, Cp , by increasing VC. Although it is not
advisable to increase VDDhigher than - 18.0 volts, it is possible

to insert external circuitry between the SCI output and the
keyboard clock bus to increase Vc.
One method of increasing Vc is to use a voltage doubler
circuit, such as shown in Figure 7. This circuit is driven by the
SCI (or SC2) output, doubles the voltage, and provides a scan
clock with a Vc of twice the VDD level (minus 3 to 4 volts).
At VDD := - 13.5 volts, the doubler consumes typically 20 rnA,
and at VDD := - 18 volts, it uses about 28 rnA. The curves in
Figure 8 can be used to calculate the required Cp , given CS.
The solid lines apply to a system in which a voltage doubler is
used to provide a Vc of 23 to 32 volts from a VDD supply of
- 13.5 to - 18.0 volts. The dotted lines represent the best
performance obtainable with the doubler circuit, describing a
a system with a 30 volt Vc and - 2.7 volt reference. It can be
seen that both these sets of curves allow the use of smaller
touch capacitors, Cp , than if the doubler were not used, as in
the curves of Figure 6.
If a still smaller Cp is required, Vc may be increased
further by use of a separate power supply and a non-inverting
buffer, as shown in Figure 9. For these higher Vc values, the
expressions already given for VINU and VINT can be used to
determine the required Cp values, keeping in mind the conditions that VINU> VREF+ 1.0 volts, VINT < VREF - 0.5 volts,
and VREF is set between - 2.5 and - 3.8 volts. For high values
of VC, it is possible to use very low touch capacitors, as indicated by Figure 10. These curves plot Vc vs. Cp for two values
of CS, 9 pFs and 14 pFs. A fixed VREF of - 3 volts is assumed.
If Cs := 9 pFs, for example, it can be seen that an 8 pF Cp is
required for a V C of 16.0 volts, whereas raising Vc to 40 volts
permits the system to function with a 2 pF Cp value.

150 pt.

22K
FROM
SC10R
SC2
OUTPUT ON
TOUCHCONTRO L
CIRCUIT

CLOCK OUTPUT
TO TOUCH PANEL

6800
2N4275
IN914

2N4275

];5/35

777237

FIGURE 7. TOUCHCONTROL SCAN CLOCK VOLTAGE DOUBLER

8.31

25r-------------------------~------------------------------------~------------_,

SOLID CURVES
Vc =23TO 32 VOLTS (USING VOLTAGE DOUBLER
OF FIGURE 6WITH -13.5 VOO

MULTIPLEXED OPERATION
EXTE RNAL SUPPL Y VO LTAG E
VSS' VE~-100VOLTS

TO COMMON
CLOCK LINE ON
TOUCHCONTROL
PANEL

777239

FIGURE 9. NON-INVERTING BUFFER FOR
AMPLIFYING SCAN CLOCK SIGNAL

To permit a larger number of switches to be interfaced
by a single TouchControl circuit, two parts employ a keyboard
matrix approach. The S9262 uses a 2 x 7 matrix to control
14 switches, and the S9266 uses a 2 x 16 matrix to control 32
switches. As described in the section on "Keyboard Scanning,"
these parts provide two scan clock outputs, SCI and SC2.
Each of the "I" inputs shares two touch switches, one clocked
by SCI and the other by SC2, as shown in Figure 4.
The multiplexed parts operate similarly to the nonmultiplexed circuits, and the expressions and curves already
presented for VINU and VINT calculations are valid for all
TouchControl parts. It is important to note, however, that
there are two touch capacitors connected to each input of the
multiplexed devices. When one of a pair is being scanned, the
other acts like two capacitors connected in series loading the
input, and that load must be added to CS. For example, if

\
\

100

I
\

\
~

\
80

>«
c..J

VREF ~ -3.0 VOLTS
-13.5V < VDO < -18.0V.
,

--*"-..-.\
\

\
\

OPERATING

~RANGE

c..J

en
a::

c..J

CS~ 14pF

\
\

OPERATING

\+--- RANG E

~
a

DOTTED CU RVES FO R Cs 0 F 14p F

SOLID CURVES FOR INPUT STRAY
CAPACITANCE. Cs. OF 9pF

a::
:::>

8a::

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1979_AMI_MOS_Products 1979 AMI MOS Products

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