1979_Fairchild_Bipolar_Memory 1979 Fairchild Bipolar Memory

User Manual: 1979_Fairchild_Bipolar_Memory

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I=AIRCHILC
@1979 FAIRCHILD CAMERA & INSTRUMENT CORPORATION. 464 ELLIS STREET. MOUNTAIN VIEW, CALIFORNIA 94042' 415/962-5011 • TWX 910-379-6435

TABLE OF CONTENTS

CHAPTER 1 INTRODUCTION . ......................................................... 1-3
CHAPTER 2 NUMERICAL INDEX OF DEVICES . ......................................... 2-3
CHAPTER 3 SELECTION GUIDES AND CROSS REFERENCE
RAMs, PROMs, Selection Guide .................................................•... 3-3
Bipolar Memory Selection Guide by Function ....................•.•............••.... 3-4
Bipolar Memory Cross Reference .......•..•.•..••..............•.•..........•....... 3-5
CHAPTER 4 GENERAL CHARACTERISTICS
Impact of Process Technology on Bipolar Memory Characteristics ........•..•....•..... 4-3
Memory Cell .........•...................•....•...........................•........ 4-4
Input Characteristics .....................••••.................•..............•...... 4-5
Output Characteristics ........................•.......•...•.•.•..................... 4-6
Timing Parameters .........................•...........................•.......•... 4-8
Read Mode ..................•..........••........•...•...•.....................•.. 4-8
Write Mode .......................................•.....•................•.....•... 4-8
Reliability ......................................................................... 4-10
References ..••........•...•............................•........•...•..•........ .4-10
CHAPTER 5 RAMs
Memory Organization ....................•......•...•.......•.••.......•............ 5-3
Addressing Techniques ......•.•...••...............................•............... 5-3
General Timing Considerations ..................................................•.•. 5-4
Interface .........................................••..•.....•.••.....•..........•... 5-7
Micro-Control Storage using Read/Write Memory .....•.....•.•.•........•............ 5-7
Buffer Memories ..................•................•...•........•..........•...•.... 5-7
Main Memories ..................•..•.......•....••...........•.......•..••.•...•.. 5-7
Conclusion .•...............................•..........................•....•..... 5-19
Reference .••...•.......................................•........•...............• 5-19
CHAPTER 6 PROMs
Applications ....•.................................................................. 6-4
4-Bit Comparator ...•..............................................................• 6-4
Hamming Code Generator/Checker/Corrector •..•..•......•.............•.......•.... 6-5
Encoder/Decoder ....................................•...........•.....•.......•... 6-5
8-Bit Binary to 3-Digit Decimal Display Decoder ...................................... 6-6
Programmed Logic Controller ....................•.......................•......•... 6-7
Address Word Expansion ..............•...••.•.•...•...................•.••........ 6-9
PROM Programming .................................•........•..•.....•....•..... 6-14
Power Switching .........•..............•.•....•...•............•................. 6-15
PROM Marking .........................•........•....•.......•...•....•........... 6-18
References .......•....•....•.......................................•............. 6-18

TABLE OF CONTENTS (Cont'd)

CHAPTER 7

PRODUCT INFORMATION/DATA SHEETS ..... ........................... 7-3

CHAPTER 8 ORDER AND PACKAGE INFORMATION
Package Style .....................................................................8-3
Temperature Ranges ................................................................ 8-3
Examples ......................................................................... 8-3
Device Identification/Marking ...................................................... 8-3
Package Information ............................................................... 8-4
Hi-Rei Processing ................................................................. 8-5
Hi-Rei Processing Flows ............................................. , .............. 8-6
Package Outlines .................................................................. 8-8
CHAPTER 9

FAIRCHILD SALES OFFICES, REPRESENTATIVES
AND DiSTRIBUTORS ..... ................................................ 9-3

INTRODUCTION

GENERAL CHARACtERISTICS ,

RAMs

PROMs

CHAPTER 1
• Introduction

Chapter 1

INTRODUCTION
At one time, bipolar memories were relegated to a very restricted list of applications. Their bit density
was quite low, while their power consumption per bit and their price per bit were quite high. Their only
advantage was speed; they were used only where speed was required at any cost.
Today's bipolar memories are still fast but other factors have changed in a most dramatic way. Density
has surged to 8K bits per package for ROMs and 4K for RAMs. Power density has tumbled spectacularly.
For the popular 1 K TIL RAM, for example, power density is below 0.5 mW per bit for the standard version
and less than 0.2 mW per bit for the low power version; their respective access times of 25 and 35 ns are
still on a downward trend.
And what about prices? System designers' acceptance has led to high volume production, while continuing advances in technology and design innovation have brought chip sizes down to MSllevels. These factors have brought prices down well below 1¢ per bit. Combine this low component cost with the advantages of having the same power supply and I/O characteristics as the logic circuits and the system cost
savings are very impressive.
The combination of speed, efficiency, cost effectiveness and design flexibility have made bipolar memories the standards by which other memories are compared.

1-3

a

INTRODUGTION·

NUMERICAL INDEX OF DEVICES

CHAPTER 2

• Numerical Index of Devices

Chapter 2
NUMERICAL INDEX OF DEVICES
DEVICE

PAGE

DESCRIPTION

ECl STATIC MEMORIES
F100414
256 x 1 RAM ........................................................................ 7-3
F100415
1024 x 1 RAM - High-Speed ......................................................... 7-8
F100416
256 x 4 PROM .............................. '" ..................................... 7-12
F100422
256 x 4 RAM ....................................................................... 7-15
F100470
4096 x 1 RAM ...................................................................... 7-16
16 x 4 RAM ............................•........................................... 7-20
F10145A
128 x 1 RAM ....................................................................... 7-25
F10405
256 x 1 RAM ....................................................................... 7-29
F10410
F10411
256 x 1 RAM - Low-Voltage ........................................................ 7-32
256 x 1 RAM ....................................................................... 7-36
F10414
1024 x 1 RAM ...................................................................... 7-39
F10415
F10415A
1024 x 1 RAM - High-Speed ........................................................ 7-39
F10416
256 x 4 PROM ...................................................................... 7-46
256 x 4 RAM ....................................................................... 7-49
F10422
4096 x 1 RAM ...................................................................... 7-50
F10470
TTL STATIC MEMORIES
93410
256 x 1 RAM - Open Collector ...................................................... 7-53
256 x 1 RAM - High-Speed, Open Collector ................ , ......................... 7-53
93410A
256 x 1 RAM - Open Collector ...................................................... 7-58
93411
256 x 1 RAM - High-Speed, Open Collector .......................................... 7-58
93411A
93L412
256 x 4 RAM - Low-Power, Open Collector .......................................... 7-64
256 x 4 RAM - Open Collector ............................... , ...................... 7-69
93412
93L415
1024 x 1 RAM - Low-Power, Open Collector ......................................... 7-73
93415
1024 x 1 RAM - Open Collector ..................................................... 7-78
93415A
1024 x 1 RAM - High-Speed, Open Collector ......................................... 7-78
93417
256 x 4 PROM - Open Collector .................................................... 7-82
93419
64 x 9 RAM - Open Collector ....................................................... 7-85
256 x 1 RAM - Low-Power, High-Speed, 3-State ................................... 7-90
93L420
93L421
256 x 1 RAM - Low-Power, 3-State .................................................. 7-96
93421
256 x 1 RAM - 3-State ............................................................. 7-100
93421 A
256 x 1 RAM - High-Speed, 3-State ................................................. 7-100
256 x 4 RAM - Low-Power, 3-State ................................................. 7-104
93L422
93422
256 x 4 RAM - 3-State ............................................................. 7-110
93L425
1024 x 1 RAM - Low-Power, 3-State ................................................ 7-114
93425
1024 x 1 RAM - 3-State ........................................................... 7-119
93425A
1024 x 1 RAM - High-Speed, 3-State ............................................... 7-119
93427
256 x 4 PROM - 3-State ........................................................... 7-123
93436
512 x 4 PROM - Open Collector ................................. " ................ 7-126
512 x 8 PROM - Open Collector ................................................... 7-129
93438
93446
512 x 4 PROM - 3-State ........................................................... 7-132
93448
512 x 8 PROM - 3-State ........................................................... 7-135
93450
1024 x 8 PROM - Open Collector .................................................. 7-138
93451
1024 x 8 PROM - 3-State .......................................................... 7-138
93452
1024 x 4 PROM - Open Collector .................................................. 7-144
93453
1024 x 4 PROM - 3-State .......................................................... 7-144
93458
16 x 48 x 8 FPLA - Open Collector ................................................. 7-149
93459
16 x 48 x 8 FPLA - 3-State ......................................................... 7-149
93L470
4096 x 1 RAM - Low-Power, Open Collector ........................................ 7-158
93470
4096 x 1 RAM - Open Collector .................................................... 7-164
2-3

•

Chapter 2
NUMERICAL INDEX OF DEVICES (Cont'd)
DEVICE
93L471
93471
93475

DESCRIPTON
4096 x 1 RAM 4096 x 1 RAM 1024 x 4 RAM -

PAGE

Low-Power, 3-State ................................................ 7-158
3-State ........................................................... 7-164
3-State ........................................................... 7-168

TTL DYNAMIC MEMORIES
93481
4096 x 1 RAM - 3-State ........................................................... 7-174
93481 A
4096 x 1 RAM - 3-State ........................................................... 7-174
TTL MACROLOGIC MEMORIES
9403
16 x 4 FIFO Buffer Memory - 3-State ............................................... 7-182
9406
16 x 4 LIFO Program Stack - 3-Stae ................................................ 7-196
9410
16 x 4 RAM with Register Stack - 3-State .......................................... .7-207
9423
16 x 4 FI FO Buffer Memory - 3-State ............................................... 7-211

2-4

INTRODUCTION

NUMERICAL INDEX OF DEVICES

SELECTION GUIDES AND CROSS REFERENCE
,

,

GENERAL CHARACTERISTICS

RAMs

PROMs

INFORIMA ,.

ON/DATA ~HEETS

CHAPTER 3

• RAMs, PROMs Selection Guide
• Bipolar Memory Cross Reference
• Bipolar Memory Selection Guide by Function

RAMs, PROMs, SELECTION GUIDE
BITS PER WORD
WORDS

1

16

2

8

4

9

MM

,,10

10145A
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u

4

zw

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aw

ff

3

V

u.
u.

/

/

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0
:>

u

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\.CURRENT ~
SWITCH
TRANSISTOR

~

~

"\

/OUTPUT
TRANSlrOR

I

.to

10

0.5
IC

Fig. 4-3.

~

50

COLLECTOR CURRENT - rnA

Cutoff Frequency of Isoplanar II Transistors
15

WORD LINE

12
..J

~
0

til

I

9

\

1\
\

UJ

~
til
..J
..J

\

'\

6

....... 1'

UJ
()

..............
3

mT

..............

BIT
LINE

LINE

o
1972

1974

WORD LINE

Fig. 4-4.

1976

1978

YEAR

Fig. 4-5.

Typical Memory Cell

4-4

Cell Size Evolution

1980

Wp

Wp

WN

N+

BIT LINE

a)

b) Device Structure

Cell Circuit
Fig. 4-6.

PLTM Cell used on 93481 4K RAM

vcc

o

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-0.1

E
I
f-

iE -0.2

D1

~
~

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- -V

::::J
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~ -0.3
a.

r-

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/"'"

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II

I

E-O.4

-0.5

o

+0.5

+1.0

+1.5

+2.0

+-2.5

VIN - INPUT VOLTAGE - V

Fig. 4-8.
Fig. 4-7.

Translator Input Characteristic

Showing Threshold Break

Input TTL-to-ECL Translator

INPUT CHARACTERISTICS
The decoding logic of bipolar memories uses Eel circuitry since this eliminates any need for gold doping
to control storage time, while the relatively small voltage swing of Eel enhances the delay-power product. TTL memories use a TTl-to-Eel converter such as that shown in Figure 4-7. When the input signal
is lOW, 02 conducts the current from the current source transistor 03. As the input signal rises through
the 1.5 V level, 01 collector voltage goes lOW. As the input signal goes through this transition region,
there is a slight break in the input current-voltage characteristic, as shown in Figure 4-8. This change
represents the base current required by 01 as it turns on. This base current is a fixed amount since 01
emitter current is fixed by 03 and R2. Thus as the input voltage continues to rise above this transition
region, the input I-V characteristic again has the slope of R 1. As the input signal rises above 2.1 V, current
from R1 is diverted away from D2; it starts flowing through D3 and the diode string that supplies the bias
voltage for 02 base. Those accustomed to TIL characteristics should note that the point where the input
current goes to zero is not the threshold; rather, the threshold is identified by the slight break in the I-V
characteristic. A clamping diode is provided on each input to limit undershoot and ringing. It is intended
only for transient currents and should not be used for steady-state clamping.
4-5

OUTPUT CHARACTERISTICS
The ECl memories have emitter-follower outputs with the same characteristics as ECl logic circuits. To
simplify data bussing, no pull-down resistors are used on the chip. TTL memories have either an open
collector output or a 3-state output. Figure 4-9 is a partial schematic of a 3-state output. The 06 - 07
Darlington provides the pull-up function for the HIGH state, while 08 is the pull-down transistor, with 05
providing current gain. Diode D1 clamps 08 out of saturation. On some of the later designs, a Schottky
diode is used for clamping. The pull-up and pull-down circuits are driven from the complementary outputs of the 03-04 current switch, which in turn is driven by signals from the sense amplifier. In the nonselected mode, the logic of the sense amplifier turns off the pull-down transistor. To achieve the high impedance condition of the 3-state outputs the pull-up circuit is turned off by the 01-02 current switch,
which in turn is activated by signals derived from the Chip Select and Write Enable logic.
Diode D2 limits overshoot and ringing, and also protects 08 from any overvoltage condition on the bus
lines. An external pull-up resistor is required for the open collector output to establish the HIGH state
voltage. The minimum load resistor value is determined by the current-sinking capability of the output.
The maximum value is determined by the leakage currents of OR-wired outputs as well as driven inputs,
which must be supplied to hold the outputs at VOH. The upper and lower limits on the pull-up resistor are
determined by the following equation.

VCC(min)
IOL FO (1.6)

RL is in kO
n = number of wired-OR outputs tied together
FO = number of TTL Unit Loads (UL) driven
ICEX = Memory Output Leakage Current
VOH = Required Output HIGH Level at Output Node
IOL = Output LOW Current

VCC(min) - VOH
n (ICEX) + FO (0.04)

02

05

Fig. 4-9.

01

3-State Output and Simplified Drive Circuitry

4-6

Note that the worst-case ac parameter limits shown in the data sheets apply over the recommended operating temperature and supply voltage ranges for the various devices.
Access times of bipolar memories have proven to be quite insensitive to the pattern of stored information.
Extensive investigation has shown that variations, if any, in the access time of a particular cell are related
only to the status of surrounding cells or to the status of cells in the same row or column. These relationships, wh.ich were predictable, can be appreciated by considering the symbolic representations of Figures
4-10 and 4-11. In Figure 4-10, the central cell abuts eight others and there is always a possibility of
crosstalk due to a random defect. The access time of a particular cell can be influenced by cells in the
same row or column because of loading effects on the common drivers (see Figure 4-11).
From these investigations, there have evolved some very effective ac test patterns in which the access
time of each cell is tested as a function of the status of cells in the same row and column and the adjacent
corner cells. For an n-bit memory the number of tests is 2n \,Ill. This method has proven to be fully as effective at detecting out-of-tolerance conditions as the exhaustive method of testing each cell as a function
of all other cells in the memory, i.e., N2 testing, yet consumes an order-of-magnitude less time; this is a
very important cost factor in large memories.

...!--COlUMN
X

,,
,
,

,
x

x

x

I

:
ROW

,,,
x
L_____

x

,

x '

______ J

x

Fig. 4-10.

ffi

Cl

o

u

w

Cl

X

Fig. 4-11.

4-7

II

Read Mode

WORST CASE MAXIMUM TIMES

Output is guaranteed to be valid:
• tAA after last address change

93410A

93415

F10405

tAA

45 ns

45 ns

15 ns

tACS

25 ns

35 ns

8 ns

tRCS

25 ns

35 ns

8 ns

• tACS after beginning of Chip Select
Output is guaranteed to be inactive (open):
• tRCS after end of Chip Select

TIMING PARAMETERS
Since ROM and PROM parameters are the same as those of a RAM in the Read mode, a discussion of RAM
parameters covers all three types. Compared to other technologies (MaS and core) the timing requirements of bipolar RAMs are very simple and can be explained in only a few statements. A RAM can be in
either Read or Write mode, determined by the level on the Write Enable input. Usually a LOW level means
Write, a HIGH level means Read.
READ MODE
In the Read mode, there are two important system parameters.
•
•

Read Access Time
Read Recovery Time

Read Access Time
Read Access Time is the time after which RAM data output is guaranteed to be valid. This time is specified
as tAA, address access time, and tACS, chip select access time. When the Address inputs have been stable
for the worst-case (longest) value of tAA and Chip Select has been active for the somewhat shorter worstcase value of tACS, the data outputs are guaranteed to represent the correct information.
Read Recovery Time
After deselect, the RAM outputs require some time to reach the inactive state; this time is called tRCS,
chip select recovery time. After the worst-case (longest) value of this time, the outputs are guaranteed to
be inactive.

WRITE MODE
In the Write mode (Write Enable active, usually LOW) there are two different and almost independent
considerations.
• The information must reliably be written into the addressed location.
• In the process of achieving this, no other locations may be disturbed.
These two considerations put separate constraints on the timing, and obviously both must be met by the
system design.
4-8

Write Mode

WE·CS

V;J///jFt

A m<---tA---.1

D

WORST CASE MINIMUM TIMES REQUIRED

w - ) ' - -_ _

M--·

--tD----I

~

~

93410A

93415

F10405

tw

30 ns

30 ns

8 ns

tA

40 ns

40 ns

12 ns

tD

35 ns

35 ns

11 ns

5 ns

5 ns

3 ns

tWHD

Guarantees desired data is written into proper location.

Write Operation
The Write operation occurs during the logic AND condition of Write Enable and Chip Select. Again, Write
Enable is usually active LOW and Chip Select is often a mUlti-input AND gate with some inputs active
LOW. This WE'CS condition must last for a minimum length of time, specified as tw, minimum required
write pulse width. It does not matter in which sequence this AND condition is established, whether WE
is there first and CS comes later, or vice versa, or whether they arrive or disappear simultaneously. It is
the longest value of this minimum required write pulse width that is the critical, worst-case value. Unfortunately, data sheets list it in the Min column.
Backtracking in time from the end of the write pulse, the Address inputs must be stable for tA and the
Data input must be stable for tD and data must also remain stable for tWHD, data hold time during write,
after the end of the write pulse. Obviously the data input may change during the early part of a sufficiently long write pulse. It is the data present during the final tD of the write pulse that ends up in the ad- •
dressed cell.
The second important consideration is that no other locations are unintentionally disturbed during the
write operation. To guarantee this, the Address inputs must have stabilized tWSA address write set-up
time, before the beginning of the write pulse, and they must remain stable for tWHA address write hold
time after the end of the write pulse. This write pulse is, again, the AND condition of Write Enable and
Chip Select.
Write Recovery Time
The Write Recovery Time, tWR, is the period during which the outputs remain deactivated after the end
of a write pulse. This recovery time is of no consequence to the system designer since it is shorter than,
and hidden in, the address access time of the subsequent read operation.
Write Mode

....IIr

WORST CASE MINIMUM TIMES REQUIRED

I

WE.CS _ _ _ _

A

§Z. . . .--"-I
tWSA

~
I

1->1{

93410A

93415

F10405

tWSA

10 ns

10 ns

4 ns

tWHA

5 ns

5 ns

3 ns

ItwHA

Guarantees no other location is disturbed.

4-9

•

RELIABILITY
Accelerated stress testing of Fairchild bipolar memories, both ECl and TTL, totaling more than 12 million
device hours in mid 1976, has demonstrated a failure rate of 0.29% per 1000 hours at +175°C. Using the
Arrhenius 5- 7 model assuming an activation energy of 1.1 eV (Figure 4-12), this extrapolates to a failure
rate of less than 0.001 % per 1000 hours at a junction temperature of +1 OooC. Experience in large mainframe applications is proving that the predicted low failure rates are being achieved in actual system
usage.
Reliability testing started with circuits in the solder-seal ceramic package with side-brazed leads. More recently, Fairchild bipolar memories have been qualified in the glass-seal CERDIP and in the plastic DIP
packages. Copies of the latest reliability reports are available from your local Fairchild representative or
through Bipolar Memory Marketing, MS 20-1050,464 Ellis Street, Mountain View, CA 94042.

500
300

I ARRHENIUS MODEL

~.J(~)~e
, ,

I

II

1

I

-Ea
T
R(T) TIME-TEMPERATURE DEPENDENT PROCESS
T ~ ABSOLUTE TEMPERATURE (DEGREES KELVIN)
EA~ ACTIVATION ENERGY
K " BOLTZMAN'S CONSTANT

.0

200

~

_f--"-

w 100

f--

----

0::

::;)

....

«
0::
w

c..

50

:;
w

....
THIS MODEL ASSUMES THAT DEGRADATION OF QUALITY OR SOME
FUNCTION OF QUALITY. IS A LINEAR FUNCTION OF TIME AT A FIXED
LEVEL OF STRESS AND THE LOGARITHMS OF THE SLOPES OF THE
DEGRADATION LINES YIELD A LINEAR FUNCTION OF THE RECIPROCAL
OF ABSOLUTE TEMPERATURE.

20

10
0.0001%

0.001%

0.01%

0.1%

1.0%

-

10.0%

FAILURE RATE IN PERCENT PER 1000 HRS

Fig. 4-12.

Arrhenius Plot

REFERENCES
1. Peltzer, D., Herndon, B., "Isolation Method Shrinks Bipolar Cell for Fast Dense Memories," Electronics,
March 1, 1971.
2. Baker, W., Herndon, W., longo, T. and Peltzer, D., "Oxide Isolation Brings High Density to Production
Bipolar Memories," Electronics, March 29, 1973.
3. Dhaka, V., Muschinske, J. and Owens, W., "Subnanosecond Emitter-Coupled logic Gate Circuit
Using Isoplanar II," IEEE Journal of Solid-State Circuits, Vol. SC-8, No.5, October 1973.
4_ Sander, W. and Early, J., "A 4096 x 1 (J3l) Bipolar Dynamic RAM," ISSCC Digest of Papers, Vol. XIX,
1976.
5. Thomas, R.E., "When is a Life Test Truly Accelerated. "Electronic Design, Jan. 6, 1964.
6. Thomas, R.E., Gorton, H. Clay, "Research Toward a Physics of Aging of Electronic Component Parts,"
Physics of Failure in Electronics, Vol. 2, RADC Series in Reliability, Air Force.
7. Zierdt, C.H., Jr., "Procurement Specification Techniques for High-Reliability Transistors," Bell Telephone labs, Allentown, Pennsylvania.
4-10

Ii>

INTRODUCTION·

DEVICl;S.

GENERAL CHARACTE.RISItC$ .

RAMs

CHAPTER 5

•
•
•
•
•
•
•
•
•

Memory Organization
Addressing Techniques
General Timing Considerations
Interface
Micro-Control Storage using Read/Write Memory
Buffer Memories
Main Memories
Conclusion
Reference

Chapter 5

RANDOM ACCESS MEMORIES
A RAM is an array of latches with a common addressing structure for both reading and writing. A Write
Enable input defines the mode of operation. In the Write mode, the information at the Data input is written into the latch selected by the address. In the Read mode, the content of the selected latch is fed to the
Data output.
All semiconductor memories have non-destructive readout as opposed to the destructive readout of most
magnetic core memories. With the exception of the 93481 PlTM element, bipolar RAM operation is static,
i.e., the information is stored in bistable transistor cells (latches) and requires no refreshing such as required in some popular MOS RAMs using capacitor storage. Data storage in all semiconductor read/
write memories is volatile; data can only be stored as long as power is uninterrupted. In contrast, a ROM
offers non-volatile storage; data is retained indefinitely, even when power is shut off.
Bipolar memories are an integral part of a large number of digital equipment designs. From a tenuous
beginning of 16 bits per package, bipolar RAMs have advanced to 4K bits per package. Performance figures also show an interesting comparison: the 1 K TIL RAM, which has been in volume production for
several years, has a typical access time of 30 ns versus 25 ns for the early 16-bit device; typical power
consumption is 475 mW versus 250 mW. These remarkable advances are the reasons that bipolar memories are so widely accepted by system designers.

MEMORY ORGANIZATION
Memory subsystems are generally identified by number of words, number of bits and function. For example, a 1024 x 16 RAM is a random access read/write memory containing 1024 words of 16 bits each.
Semiconductor memory device organizations follow the same rule. Since the advent of lSI allowing densities of hundreds of gates on a chip, most memory devices contain address decoders, output sensing, and
various control and buffer/driver functions in addition to the array of storage cells. High density RAM
devices tend to be organized n words by one bit to optimize lead usage (see logic symbols on following
pages). ROM devices tend toward n words by four or eight bits to reduce cost of truth table changes.
ADDRESSING TECHNIQUES
Addressing (word selection) in a semiconductor memory subsystem consists of two parts. First, a given
device or group of devices must be selected; second, a given location in a device or group of devices must
be selected. Device selection may be accomplished by linear select using a binary-to-n decoder feeding
the chip select function on n chips, or by coincident select using two binary-to-yn decoders and two chip
selects on each device. When n is large, linear select requires excessive hardware. For example, if n = 64,
linear select requires four 1-of-16 decoders and a 1-of-4 decoder, or nine 1-of-8 decoders; whereas coincident selection can be accomplished with two 1-of-8 decoders with final decoding at the two input
chip select gates included on the memory devices. Selection of a given location on a chip is accomplished
by connecting the binary address lines directly to the chip. In summary, 64256 x 1 RAMs in a 16K x 1bit array using coincident selection requires 14 address I ines, as follows: eight connected to 2 0 through 27
inputs on all chips (using necessary drivers), thre '''lding a 1-of-8 decoder to the CS 1 inputs, and three
feeding a 1-of-8 decoder connected to the CS2 inputs.
For maximum control, predictability and flexibility, an address counter should have certain characteristics-fully synchronous counting, synchronous parallel entry, a means of eliminating any ambiguity as to
its mode of operation, and capability for synchronous expansion. A few examples are the 9316 and the
9lS161 for TIL; examples for ECl are the F10016 and Fl0136. System designers should also bear in
mind that decoder outputs are subject to spikes when the inputs are changed. This can cause momentarily
false Address or Chip Select signals. Memory system timing should allow for the specified maximum
propagation delays for the decoders involved.
5-3

II

GENERAL TIMING CONSIDERATIONS
The various ac characteristics of memory chips are discussed in the preceding section. These delays, setup times and hold times must be combined with those of the other logic elements of a memory system to
determine the limitations on the basic timing signals. The scratchpad memory shown in Figure 5-1 offers
a simple example for discussion. For the sake of simplicity all of the elements are shown as blocks. Also,
in this form, elements from any circuit family can be assumed.
For this discussion, elements of the F10K Eel family are assumed. Table 5-.1 identifies the circuits and
lists only the ac parameters that are pertinent to the worst-case timing limits to be explored. The signals
in Figure 5-1 are shown in the timing diagram of Figure 5-2, except for the parallel data inputs and mode
control signals for the address counter. These are assumed to be in the desired state at time zero. The signals in Figure 5-2 are listed in the order of occurrence, and the indicated numerical values are cumulative
from time zero.

DATA

~===t=========:;]
~Egc~ss------------~---------,
INPUTS

ADDRESS
INPUT

Fig. 5-1.

Block Diagram of 64 x 4 Eel Scratch pad Memory

5-4

THROUGHPUT
DELAY, ns

FUNCTIONAL ELEMENT

SET-UP/HOLD
TIMES, ns

tp(min)

tp(max)

ts(max)

th(max)

ADDRESS COUNTER

F1 0136 HEXADECIMAL

1.3

2.9

-

-

CHIP SELECT DECODER

F10101 QUAD OR/NOR GATE

1.0

2.9

-

-

DATA OUTPUT LATCHES

F10153 QUAD LATCH

1.0

5.4

2.5

1.5

MEMORY CHIPS

F10145A 16 x 4 RAM

ACCESS TIMES

twSA
3.5

tWHA
1.0

tWSCS
0.5

tWHCS
0.5

tWSD
4.5

tWHD
-1.0

READ MODE:

WRITE MODE:

Address Access

tAA(min)
4.5

tAA(max)
9.0

Chip Select Access

tACS(min)
3.0

fACS(max)
6.0

Address Set-up/Hold

Chip Select Set-up/Hold

Data Set-up*/Hold
(*for 4 ns write pulse, tw)
Table 5-1.

Worst-case Parameters for 64 x 4 Eel Scratchpad

o
TIME (ns)
READ MODE
ADDRESS

CLOCK

10

-=f-

~/;j;j//;///&t

--tp(maJC1-

ADDRESS

11

12

13

14

15

16

17"

~--~--T---T---T---T---T---T---T---T---T---"---'--~---'---'---'---'
I
I
I

1.3 -tp(min)

•

/-,44

04

2.9

-----L~~:..:::..:I~---__:__:--~_=_I-- tAA(max)------------1

CHIP SELECT

15.9

11.9
DATA OUT
FROM MEMORY

LATCH ENABLE

--------------------~~~~~~~~~~~
10.4

°

WRITE MODE

DATA IN

- - - - - - -

- - - - - - -

-

-

-

-II"T'J.."..,.!,F--------.-m~

TO MEMORY
1-~_:_-tWSD---~1

2.9

WRITE ENABLE
tWSA---

Fig. 5-2.

----tw~

Timing Limitations for 64 x 4 Scratchpad

5-5

14.4

-1h(max)

One important assumption is that the Address Clock, the Latch Enable and, in the Write mode, the Write
Enable aI/ have the same waveform. This infers that alf three signals are derived from the same basic
function, which is perhaps the least complicated approach. This commonality also means thatfactorsfrom
both the Read and Write modes playa part in shaping this basic function. These factors become evident
by folfowing through the cycles in the timing diagram.
In the Read mode a new address appears at 1.3 to 2.9 ns, corresponding to the delay limits of the Fl 0136
counter. The Fl0101 gate delay is between 1.0 and 2.9 ns, which thus makes the net Chip Select delay
between 2.3 and 5.8 ns. The earliest time that new data can appear is 5.8 ns, determined by the minimum
address counter delay plus the minimum address access time of the memory chips. The latest time for
new data to appear is also determined by the counter and the address access, amounting to a total of
11.9 ns. The Fl0153 latch is transparent when the Enable is LOW; it is latched when the Enable goes
HIGH. The latch has a maximum set-up time of 2.5 ns from Data to Enable, which means that the Latch
Enable signal can go HIGH no earlier than 14.4 ns. Thus, under the commonality assumption, the cycle
time can be no less than 14.4 ns for either Read or Write, since the Address Clock and, in the Write mode,
the Write Enable go HIGH at that time.
Limitations on the time that the Address Clock/Latch Enable/Write Enable can go LOW are determined
in the Write mode, starting from 14.4 ns on the Write Enable and working backwards. The w.rite pulse
width requirement of 4 ns means that the Write Enable can go LOW no later than 20.4 ns. The maximum
address set-up time (for the Fl 0145A) of 3.5 ns added to the address counter delay of 2.9 ns means that
Write Enable must not go LOW before 6.4 ns, to avoid writing into the wrong location. Thus the Address
Clock/Latch Enable/Write Enable must go LOW between the times 6.4 and 10.4 ns.
The chart shows that the Data In should be stable no later than 9.9 ns. This is based on the data set-up
time of 4.5 ns, which is measured backwards from the end of the write pulse, i.e., from the time Write
Enable goes HIGH. It is important to note that on some data sheets the data set-up time is specified with
respect to the beginning of the write pulse. In these cases, adding the specified minimum set-up time to
the specified minimum write pulse duration wilf give the correct figure to use for minimum Data In setup time with respect to the end of the write pulse, regardless of how long the write pulse duration might
be in a given application. In this regard the memory behaves like any D-type latch, wherein the D input
can change randomly except for a certain period of time (the set-up time) preceding the active edge of
the enable.
Referring again to the timing diagram, if the write pulse starts at 6.4 ns the Data In must stilf be stable
from 9.9 ns onward. Note in Table 5-1 that the data hold time is -1.0 ns, meaning that the data can
change 1 ns before the end of the write pulse without affecting the reliability of the Write operation. Accordingly, the timing diagram shoWs that Data In can change any time after 13.4 ns.
Notice in the Read mode that the data out of the latches is assuredly stable after 17.3 ns. Thus if the basic
cycle time is 14.4 ns, this data can be sampled after 2.9 ns of the next cycle. Further, this data remains
stable until the Latch Enable next goes LOW, plus 1.0 ns.
At the expense of more complex timing signal generation, shaping the Address Clock, Latch Enable and
Write Enable separately can aI/ow faster operation. For example, the second positive-going edge of the
Address Clock can occur at 10.6 ns rather than 14.4 ns. The address counter output would then change
no sooner than at 11.9 ns, with the Chip Select folfowing no sooner than at 12.9 ns. The minimum delay
from Chip Select to Data Out of a memory chip is 3.0 ns. Thus the Data Out could change no sooner than
at 15.9 ns, which agrees with the timing requirement shown in Figure 5-2. Thus the opportunity exists
to reduce the read cycle time by 3.8 ns by offsetting the Latch Enable with respect to the Address Clock.
Similarly, in the write mode the Write Enable pulse can begin (go LOW) at 6.4 ns and end at 10.6 ns,
which would make the Write Enable coincide with the revised Address Clock. These modifications would
naturalfy have an effect on the timing requirements of the Data In signals and on the sampling window
at the latch outputs.
5-6

INTERFACE
In most bipolar-memory applications, the devices are combined with other TIL or ECl logic elements
into a subsystem such as a CPU buffer controller or other function. The memory device interface is at
standard logic levels, and the additional hardware required is usually limited to pull up resistors at the
outputs of most TIL memories, and load resistors or termination resistors for the ECl memories.
In some cases, the application may require location of the memory several feet or more away from the
other functions in the subsystem. The general subject of data transmission and the effects of cable length
and bandwidth on maximum data rates is discussed in the Fairchild Interface Handbook, which also discusses interface elements for TTL. Line drivers and receivers for ECl are discussed in the Fairchild ECl
Handbook and subsequent data sheets.
MICRO-CONTROL STORAGE USING READ/WRITE MEMORY
Early in semiconductor memory development, a significant amount of attention was devoted to Read-only
memories for micro-control storage. In many cases, difficulties were encountered in developing firmware
for new machines. These difficulties involved turnaround time of weeks and months in making firmware
changes, with costs ranging from tens to thousands of dollars per change. One solution to these problems
is to use RAMs for micro-control storage. Firmware may then be changed almost instantaneously, thus
greatly accelerating the development program and eliminating cost and downtime for pattern changes.
If desired, conversion from RAM to ROM can be made at the preproduction phase. Availability of 1024bit bipolar RAMs such as the 93415 and 10415 has prompted designers to consider this approach.
BUFFER MEMORIES
Buffer memories are small to medium memories inserted between I/O interfaces and CPU, between
main memory and CPU, or at other locations where fast intermediate storage is required. The availability
of 256 and 1024-bit RAM devices has resulted in many bipolar buffer memory designs.
MAIN MEMORIES
Main memories vary from 4K to 16K bits in minicomputers up to 256K or more words in large mainframes. Before the availability of bipolar 1024 RAMs, system designers were limited to low-cost core with
1 to 2 ps access, expensive core with 400 ns to 1 ps, or MOS with> 200 ns access. Some n-channel MOS
products offer faster access time. Present bipolar RAM technology allows implementing large main mem- •
ories with 50 to 80 ns worst case maximum access times for the subsystem. A Read-Modify-Write cycle
of less than 100 ns is possible.
Typical Applications
Word Expansion
The 93410 may be used in memories requiring expansion of both the number of words and number of
bits. A 512 x 2 array and the necessary signal interconnects for accomplishing expansion is shown in
Figure 5-3. The number of words may be expanded to 4096 by using only one 9321 dual 1-of-4 decoder.

256-Word by 8-Bit Buffw Memory System
A 256-word by 8-bit buffer memory based on the 93410 is shown in Figure 5-4. Input and output data
latches and a modulo 256 address counter may be implemented with MSI devices such as the 9308 quad
latch and 9316 binary counter.
Last In/First Out (LIFO) Push-Down Stack Memory
A last In/First Out (LIFO) push-down stack memory, 254 words deep by 4-bits wide, is shown in Figure 5-5. This synchronous memory system accepts data on four parallel inputs (10 - 13) and, controlled
by two independent inputs (Read and Write), presents the "youngest" word that has not yet been read
on the four outputs (00 - 03). It also provides status information on four outputs: Full, Almost Full,
Empty, Almost Empty.
5-7

Vee

III
,"

4r---,

~

111
AQ A, A2 A3
CS

~,.,

A4 AS A6 A7

93410

W,

--r-'

I

*

256·WORD
BV ONE BIT

READ WRITE

MEMORY

~

-----<:

w,

256 WORD

BY ONE BIT
READ WRITE

MEMORY

0"

I

Dour

,:n

A4 AS A6 "'7

93410

W,

0"

es

AD Al A2 A3

CS

AD A, A2 A3

III

I

A4 AS A6 A]

DOUl

~~

T
93410

~

*

256 WORD
BYON€. BIT
READ WRITE

MEMORY

Ao
es

Al AL A3

T
"

Dour -BIlO

A4 A5 A6 A7

93410

W,

256 WOAD

BY ONE BIT
READ WRITE

MEMORY

0"

0"

DOUT

DOUT

a. 512-Word by 2-Bit Array

DUAl' 4
DECODER 9321

A, A,,)
0"

Dour
w,

b. 4096-Word Memory Plane

Fig. 5-3.

Word Expansion

5-8

T"

DOUT

BIT 1

STROBE OUTPUT LATCH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , - - - - ,

WE - - - - - - - - - - - ,

'cr --'---~----jr--r,-"""';----,

t~e,--_+-',~e,~'-,~'-,+_e,~'~,~e-,----+_----+_--_.

I
~'S

Dour

t----qwe

~fS

t----qwf

J=B

DOUT

~'-+-~~

t----qWf

I ~, 2:~;)8D~uD~ OJ'
4 BII LATCH

0u 0, 02 U3

MH

'( [}ol,orL})"L4

DOUT

/

t----qWf

J=gDI'i'i'i'

u

l

EI

MR

2 ~u:: 0]

:3:8°
4 BIT LATCH

DOUT

~rs

93410
256 WORD
8Y ONE BIT
READ WRITE
MEMORY

00 01 02 03

we

I

D"

MOD 256 ADDRESS

DOUT

~CS

93410
256 WORD
BY ONE BIT
READ WRITE
MEMORY

we

m

PE Po PI P2P3'1
9316461T
CEl
BINARY
TC
CP
COUNTER
MR 00 01 02 03 I

D"

MR

?-JCS

DOUT

t--'---qwe

H-+---'Y

93410
256 WORD
BYONE BIT
READ WRITE
MEMORY

CS

Df"

DOUl
93410
256 WORD
BYONE BIT
READ WRITE
MEMORY

'---~"we

Fig. 5-4.

IIII
~

ADDRESS TO ALL
93410

I

~

cau

LOAD

256 Word by 8-Bit Buffer Memory System

5-9

A4 A5 AS A7

~)L!'!2!3

93164BI1
]
CET
BINARY
rr
CP
COUNTER
MR 00 a, 0203 ,

'------'Y ~I

•

AO
Write

'cc

0
1
500 "

CPlaisoto aI19JH72. and 9(24)

'I 'I ';

~
W

If

I' '0. ''''''',"'0, ,,,'w',"
IS

9322 QUAD

I

INPUTS

webl

Ie

Zb

93H7l

03

CP

t--

0

~

t--QO
t-- O,

t=::

~

7409

E Po PI P2 P3

5

°

~

93H72

0,

AD

r

f{

L

REGISTER

Mil 00 010203

'f

r

L
0,

Po PI P2 P3

o
~

00

~ ~ ~0,

REGISTER

"

0,

A4

AS

A6

A7

0
0

o
o

0
0

o
o

0
0

~

~

~

~

~

~

~

,.,,, ........... """'''''1

0
0
0
0
0

0

0

0

0

0

0

Empty

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0

1
1
1
1

1

Full

1
1

Almost Full

~>

0"'"

DOUT

0"
DOUl

0"

N :~"'
~

A3

o
o

AO e • • • • A7

15

ld

l

SF

0
0

2-INPUI MULTIPLEXER
Za

Read

A2

Al

1
0

4

"'W.

DOUT

we

"

~AO Al A2

"

A3 A4 AS A6 A7 A7

MH (JO 01 02 03

~

Y

o

341402

1 47402

Fl>-

~,

-

H5

,,-

1/49014

"

WeAI

I

0,'1'

J,

Id

I

I,

I'Mm

ALMOST EMPn

ALMOST FULL

MRClO 0\ 0) 03

'lili L

Ie

fUll

CONTROL OUTPUTS
EMPTY

READ

ONE MORE TO AEA[
MORE TO WRiTE

ON~

fULL

MEMORY ADDRESS

Fig. 5-5.

LIFO Push-Down Stack Memory

DO NOT WRITE

Operation is synchronous and edge-triggered on Data as well as Control inputs. It depends on the state
of the 10 - 13, Read and Write inputs, and a setup time (=30 ns) before the rising edge of the clock that
should not exceed 15 MHz at 50% duty cycle.
There are four different modes of operation:
W • R= Write - I is shifted into Q, the old information in Q is shifted into R, the address counter is incremented, and on the next clock Low period, the content of R is written into the new memory location.
W. R = Read - Data in the wired-OR D is shifted into Q, the information in R is maintained, the address
counter is decremented. If the previous clock cycle had executed a Write instruction, then D is controlled
by the register R. If the previous clock cycle had been one of the other three modes, then D is controlled
by the memory.
W. R = Read and Write Simultaneously - Input data is shifted into Q; register R and address counter
are maintained.
W. R = Do Nothing - No change.
The control outputs allow normal computer "handshaking", and also supply a warning signal one operation in advance.
The synchronous up/down address counter is built as a shift register counter. This is both faster and
more economical than using 9366 binary counters. The non-binary count sequence is no drawback in
this application, and the sacrifice of two of the 256 states is insignificant.
Bipolar RAM Design Example
The best way to illustrate the ease of design and other advantages of bipolar static RAMs is to give a design example. It is assumed that the designer needs a modular rack-mounted system to cover a broad
range of applications. Since all parts of the system-components, architecture, packaging, modularity,
testing, etc.,-are closely interrelated, they have equal importance and must all be considered. Conse- •
quently, for this design, the packaging for example assumes the same importance as the circuit considerations. No part of the design should be treated separately.

Memory Modularity
Basic Memory Cards: (Figure 5-6)

One with 8K words and 8 or 9 bits, i.e., one design with last row not inserted, for 8 bits.
One with 4K words and 8 or 9 bits, i.e., one 8K design may be used with 93L415s for 4K
words not inserted and for 8 bits, one row is not inserted.

Basic Memory Module: (Figure 5-7)

Expanded Memory Module: (Figure 5-7)

One memory card (basic)
One address drive card
One backplane
Power
Card cage (rack mount)

Modular from one to eight memory cards
One address drive card
One backplane
Power
Cables
Card cage (rack mount)
5-11

WORDS/BYTES

WORDS/BITS

CARDS/MODULE

4K x 8/9
4K x 16/18
8K x 8/9
8K x 16/18
8K x 24127
8K x 32136
8K x 40/45
8K x 48/54
8K x 56/63
8K x 64/72

112
1
1
2
3
4
5
6
7
8

4K x 8/9

----8K
16K
24K
32K
40K
48K
56K
64K

x 8/9
x 8/9
x 8/9
x 8/9
x 8/9
x 8/9
x 8/9
x 8/9

WORDS/BYTES
64K
128K
192K
256K
320K
384K
448K
512K

Memory Size Range Using Multiple
Cards in One Module

I-

WORDS/BITS

x 8/9
x 8/9
x 8/9
x 8/9
x 8/9
x 8/9
x 8/9
x 8/9

8K
16K
24K
32K
40K
48K
56K
64K

~,,
,

'0z"

I
I
I
I
I

;:

2K

3K

4K

5K

6K

19s041 I 9s041 19s041 I 9s041
,93l4151

1193L4161

19314151 193L4151 193141 S

193L41S1 193L415)

19381671 193L415)

""

I 98051

19314151

BIT 1

'3

BIT 2

19314

193L41s1

t):
.,"' 19351571 1931415)
~,
Z,
0,
z I 9S04 I 193141SI.
0,
,,, "'"
0
,,, iii'" I 9s051 '93l41S(
,,, "' 19381671 193L4151
,
193L415) 193L4151

1
2
3
4
5
6
7
8

-I

8K

I 9S04 1 19s041 19so4 1 19S041~

Z I 9804 1 19314151
, 0z
II:

7K

I 9s041

~

0

16/72
16/72
16/72
16/72
16/72
16/72
16/72
16172

Memory Size Range Using Multiple Modules

lOIN.

1K

x
x
x
x
x
x
x
x

NO. MODULES

8K

I-

x 9-BIT

1931415(

BIT 3

193141S1

BIT 4

193L41S)

BIT 5

193L4151

BIT 6

19314151

BIT 7

19314151

BIT 8

193L4151193l4151 193L4151 193L4151 1931415) 193L4151

BIT 9

MEMORY ARRAY

61N.

0

II:

I-

II:

e
p

1938138(

Fig. 5-6.

I.

Memory Board Component layout

11 IN.

_ - - - - - 1 1 IN. - - - - _
.. 1

1. .

+r~'

~ '--_____---' IN. ,"'..

MEMORY
BOARDS

TOP VIEW

Fig. 5-7.

0 CAG',

_ADDRESS AND
DRIVE BOARD

END VIEW

Physical layout for a Bipolar MemoryModule

5-12

Packaging system
Memory and Address Boards: Two-sided printed circuit boards with plated holes.

Backplane: A two-sided printed circuit board.
Memory Board Connectors: Conventional pc board connectors which permit wire wrap on the back side.
All memory address and control interconnections are directly on the backplane.
Byte-oriented systems: All wiring on the backplane; no wire wrap needed.
Word-oriented systems: The address and control lines remain on the backplane. The data input and
data output cables to the computer are brought directly to the pins on the respective memory cards.
Power Distribution: Power conducted along the backplane and distributed to pins on each pc card.
Power distribution bars for ground and the one voltage, +5 V, augment the copper on the backplane.
Cooling: Forced air cooling, 400 or more feet per minute flowing between the cards. Stacks of memories
up to four deep require about 500 feet per minute.
Card Cage: Available standard catalog-item card guides.
The Basic Memory Card
Figure 5-6 shows the layout of the components on the basic memory card. The contact pins are located
on the left. The resistors terminating the input data cables from the computer are in the first component
column. Next is a column of IC's with the following functions.

ITEM

NO. PACKAGES

SIGNALS

FIGURE

9504

2

Ao- A 9
WE

5-8
5-10

Drive In

93S157

1

Doun - DOUT3

5-12

Output Latches

9S04

1

Data Strobe
DIN1 - DIN3

5-12
5-11

Drive In

9S05

1

Doun - DOUT3

5-12

Drive Out

93S157

1

DOUT4 - DOUT6

5-12

Output Latches

9S04

1

DIN4 - DIN9

5-11

Drive In

9S05

1

DOUT4 - DOUT9

5-12

Drivt;! Out

93S157

1

DOUT7 - DOUT9

5-12

Output Latches

IC Column 1

5-13

FUNCTION

•

ROW

ITEM

Top

9S04

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

1
2
3
4
5
6
7
8
9

93L415
93L415
93L415
93L415
93L415
93L415
93L415
93L415
93L415

SIGNAL
COL. 2

SIGNAL
COL. 3

WE
AO
A2
A4
A6
AS

A3
A5
A7
A9

A'l

5-S
5-10
5-13

0-lK
0-lK
0-lK
0-lK
0-lK
0-lK
0-lK
0-lK
0-lK

1K-2K
1K-2K
1K-2K
1K-2K
1K-2K
1K-2K
1K-2K
1K-2K
1K-2K

5-13

FIGURE

IC Columns 2 and 3

The memory columns are organized in pairs. The 9804 inverters are used at the top to give drive to each
pair of columns. The schematic of this drive/fan-out is illustrated in Figures 5-8 and 5-10. 8ince there are
six inverters per package and 11 lines to be driven, i.e., Ao through Ag plus WE, two 9804 hex inverter packages are sufficient. The input characteristics of the 93L415 1024-bit RAM are such that two columns represent
only 4.1 unit loads for the 18 inputs. The four inverters represent 5 unit loads to the driver.
The same arrangement is used to provide four column pairs. The additional pairs implement memory
words as follows:
Pair #2: 2K-3K and 3K-4K
Pair #3: 4K-5K and 5K-6K
Pair #4: 6K-7K and 7K-8K
A 938138 1-of-8 decoder, located under column 4 of the array, performs the address selection to choose
the column representing 1K of the possible 8K words of memory. As illustrated in Figure 5-9, the decoder
drives each column separately to control chip selection. Addresses Al 0, All ,and A12 as well as El, Le.,
memory select, are the inputs controlling the decoder.
When arranged this way, all lines on the memory board are short enough so that terminating resistors
and controlled impedance lines are unnecessary. The longest line running from the address drive to the
last column is approximately eight inches. The vertical lines driving the array start at row 1, split into a
"U" shape and drive two columns with branches about five inches long. The 1-of-8 decoder drive lines
vary from the five to eight inches long. TTL system operate satisfactorily in this type of packaging
environment.
Memory Module Packing
Figure 5-7 shows one possible layout for a memory module. The backplane on the left is used to connectthe
address card with one to eight memory cards. For byte-oriented systems, the cables to other equipment are
connected to the backplane at one end. The cable termination and fan-out drive circuits are contained on the
address and drive board. For word-oriented systems, the address and control lines are routed to one end of
the backplane and through the address board to drive the memory cards. However, due to the large number
of cables involved, the data input and data output lines should be attached, i.e., wire wrap or other means,
directly to the data input and output pins of each memory card. The cards are designed so that termination
for data input is on the memory board (Figure 5-11) and sufficient drive is provided on the output (Figure
5-12), A pair of resistors to +Vcc and ground should be used to terminate the data output lines within
the receiving equipment.
5-14

ADDRESS AND
DRIVE CARD

MEMORY CARDS

ADDRESS AND
DRIVE CARD

MEMORY CARDS

I

I
-

BACKPLANE LINES

BACKPLANE lINES-

10UL MAX
3

BIT
Bil
BIT
BIT
BIT
BIT
BIT
BIT

TYPICAL FOR
ADDRESSES
AO THRU A9

,

'

,

,.

1
2

4

~5 ~6 ~' ~8

BIT 1

3
4

Vee

5
6
7
8

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

2
3
4

5
6
7

B
9

,

0:":::'::::'::::'::::'::::'::::'::
r-NMo:t~\Dr-

~-I'--'
ADDRESS PINS

Fig. 5-9.

Fig. 5-8. Address Selection for Bits
Within a 1024 RAM

ADDRESS AND

::'TARD

•

MEMORY CARDS

I
..-- BACKPLANE LINES _

~A

'"'~

Fig. 5-10.

Address Selection

Groups of 1024 RAMs

-81T
BIT
BIT
BIT
BIT
BIT
BIT
BIT
81T

1
2
3
4

5
6
7
B
9

Read/Write Selection

5-15

,

MEMORY CARDS

I

fOR BVTE
ORIENTED

-

BACKPLANE LINES lOUl MAX

MEMr'ES
DATA STROBE

1

9504

~

81T,
DATA OUT PINS

~~~

F

b~--t-[>--'-r--'--'--'---.-r-"-

BIT 6

b~--t-[>--.-r--'--'--'---.-r-"-

BIT 7

DATA OUTPUTS
(TYPICAL)

b--,----t---t>---.-,-,---,--r--,-,.-,.- BIT 8
WORD·ORIENTED
SYSTEM CONNECTION

81T 2

BIT 4
BIT 5

I=----,--,.-,---,-,--,-r-,.- BIT 9
9351575

TYPICAL 9 PLACES
AT FAR END OF CABLES

·Omit on boards.
Place on backplane in byte-oriented ayslems

Fig. 5-11.

Fig. 5-12.

Data Input System

0

Fig. 5-13.

'd.

'" CD CD
'Db

0

"b

'0,
@

'"

@

'Od

@

1

11d

Data Output System

h

E S

@@

(i)

93S 157 as a Pass Through latch for Data Output System

5-16

ITEM

'SIGNAl

FIGURE

9504

AO
A,
A2
A3
A4
AS

5-8

9504

'100 n terminating resistors to
ground are assumed on each input

-

AS
A7
AS
_A9_
WE

WE
9504

AlO
A"

5-8

-

-

-

-

5-10
5-9

~'2
E,

os

5-12

Address Board Components

For tightly packaged systems where the other logic is adjacent to the memory, omit the address card and
include the required signal drive and inverters as part of the computer. The memory card design provides
great flexibility for integration into other systems. Normal TTL circuit rules apply.
Address Board
The address board is a very simple two-layer pc board. It receives the address and control signals from
the equipment attached to the memory and provides the necessary fan-out drive. The inversion function
is also performed if required. There are few components and pin connections on the address board. In
tightly coupled systems, it may be omitted and the required circuits can be part of the other equipment.
In this case, it may be necessary to provide circuits that can drive 10 unit loads plus a terminating resistor mounted on the backplane opposite the input cable end. When using an address board, the longest output
line is less than nine inches so no terminating resistors are needed within the memory for a TTL design.
Memory Board Circuits and Layouts
Figures 5-8 through 5-12 are combination circuit and pseudo-physical routing schematics. Figure 5-8 •
through 5-10 illustrate (on the upper left side) the circuits that can be either on an address board or in attached equipment. The backplane lines for plugging in the eight memory boards are illustrated across the top.
An example memory board circuit/routing schematic is shown in each figure along with the relationships of bits and words in the rows and columns_ Refer to Figure 5-6 for the memory board layout. The
les include 8chottky TTL types 9804, 9805, 938138, 938157, and the TTL 1 K RAM 93L415. The faster
higher powered 93415 or 93415A can be substituted without any electrical design or layout changes.
The power supply must be increased and more cooling provided; also memory timing pulses must be adjusted to take advantage of these faster parts.
Figure 5-11 illustrates the data input system. If the cables for word-oriented systems come directly to the
memory card, the 100 n termi nating resistors are used. In byte-oriented systems, these resistors are omitted. The drive circuits for byte-oriented systems may be located either on the address drive board or in
the attached equipment. If sufficient fan-out drive is supplied from the equipment and long cables are
used, a terminating resistor is placed a the far end of the backplane.

The data output system is shown in Figure 5-12. The 93L415 outputs for each bit are connected together
and run to the 11x pin of a 938157 multiplexer. The multiplexer is connected to provide a pass through
latch as shown in Figure 5-13 to permit rapid data access, long data hold time, and to minimize $trobe
skew. 9805 drivers with open collectors are provided for output driveso the various bits ina byte-oriented
memory can be OR-tied together. A resistor network as illustrated in Figure 5-12 is placed a the receiving
end of the output data cables.
5-17

Some Interconnection Hints
The dual-in-line package is designed with space to run one pc board conductor between pins. Two-layer
printed circuit boards provide for running horizontal connections on the back and vertical connections
on the front. This and the regularity of connections in a memory array allow very tight packaging. IC
spacing on the memory board can be on a pitch of one inch horizontally and one-half inch vertically,
a common industry practice.
Interconnections may be made using straightforward simple wire routings on two-layer boards. Figure
5-14 presents part of the actual layout showing three columns of the array. The connections to the 9S04
address drive are at the top. Ground and +Vee trees are also illustrated; note that one ground and one +Vee
line go between each column. It is important that the designer run one line horizontally across the board
and attach it through plated holes to +Vee at every other package row. This forms a screen or mesh for
power distribution. A similar arrangement should be used for ground.
The vertical lines are routed to pin rows of the DIPs. This provides address, Read/Write and chip selection
on the front side of the pc board. The data input and output lines are on the back side along with the Vee
and ground cross connections. Appropriate capacitors should be placed between Vee and ground for
about every four packages. Normal TTL design rules apply.
Performance Characteristics
The chart below and Figure 5-15 summarize the performance that can be expected from a system using
Schottky TTL parts and 60 ns 93L4151 K RAMs. The power dissipation is calculated for worst-case conditions for the Schottky parts and for typical dissipation on the memory parts. This is reasonable, since so
many memory parts are used, the averages apply. The timing calculations are made using 2 ns/foot
delays for signals on conductors and worst-case Schottky values. The Read and Write cycle times for the
93L415 are assumed to be .60 ns for the example calculations; however the user may specify shorter access times at added cost. To adjust the. times shown, a designer may add the nanosecond differences for
maximum RAM times or subtract the differences if he uses faster parts.

ITEM
Size: Words/Bits

lotalBits

4K

8K

GND

Vee

Fig. 5-14. Memory Column Interconnection System

5-18

64K/72 or
512K/9

73.728

589.824

4.718.592

125 ns typ

135nstyp

Data Window

80 ns typ

SO ns typ

80 ns typ

Read Cycle

120 ns typ

125 ns typ

135nstyp

Write Cycle

120 ns typ

125 ns typ

135 ns typ

TTL

TTL

TTL
+5.0 V

Supply Voltage
(one)

+5.0 V

+5.0 V

Supply Current

3.11 A

24.9 A

199A

Power

15.6W

125W

99SW

OOC to 55°C

aoc to 55°C

O°C to 55°C

400 fpm

400fpm

500fpm

Cooling Air

9S04
93L415
93S138

SYSTEM
*S MODULES

8K/72 or
64K/9

120 ns typ

Inlet Air

D

8K/9

MODULE
S CARDS

Read Access

Inputs & Outputs
3K

SINGLE
8K x 9
CARD

*Two rows of four modules.

Table 5-2.
Memory Performance Summary Using
93L415 RAMs and Schottky TTL Parts

125 ns

I

X SKEW X

ADDRESSES STABLE AT 93L415

I _ADDRESSES

r-~~======::;:;:::========fo~7.--h5
f-'!
L ___
~I~ _ _ _ _ _ ---I

t===

-CHIP SELECT

i-WRITE/ENABLE

DATAOUT_===-=~OS3(~~~

t--_ _ _ _ _ _
D_AT_A_S_T_RO_B_E_-'/---30

ns

..\_15n5_1 __

BOd

READ

j

SKEW

X

ADDRESSES STABLE AT 93L415

I -AODRESSES

L~I=~g~.====O~A~T=A=IN=S~T=A~BL=E=======.~~r.=g~ I -

o+l-ls\-.:::=:;----------~===fo=---7~5hI-' I
1-20 "'-\'----_ _ _ _ _ _ _ _---1/---40 "'__

I

DATA IN

-CHIP SELECT

! -WRITE/READ

WRITE

Fig. 5-15. Timing Example for 93L415 Memory

Minor adjustments in timing may have to be made to accommodate a specific design. Layout dimensions
and the minimum and maximum times established for all components will affect the system delays. The
time values used in this example take line-length delays and circuit skews into account with appropriate
allowance for margins.

CONCLUSION
Smaller die size, increased yields and economical packaging have reduced bipolar 1 K RAM costs to the
point where bipolar memories have become attractive for some applications reserved, in the past, for
slower, lower cost MOS memories. Instead of emphasizing the cost per bit, the designer should look at
the total memory system cost and inherent device characteristics when choosing a RAM for a specific
application. The chief advantages of bipolar RAMs are outlined below .
• Simple design, construction, testing and field maintenance features of static bipolar TIL
memories mean lower total system-lifetime hardware costs .
•

Fast static memories greatly ease system interrupt and software storage and access problems
as well as enhance system throughput, thus providing system lifetime savings.

REFERENCE
Rice, R., Green, F. and Sander, W., "Design Considerations Leading to the ILLIAC IV Process Element
Memory," IEEE Solid-State Circuits Journal, October 1970.
5-19

•

INTRODUCTION

cnl\~L.'NDEXOFDEVICE..S

1·:q~NE.RAL .•C~ARACT~.~·rSTICS·

•.

CHAPTER 6
•
•
•
•
•
•
•
•
•
•
•

Applications
4-Bit Comparator
Hamming Code Generator/Checker/Corrector
Encoder/Decoder
8-Bit Binary to 3-Digit Decimal Display Decoder
Programmed Logic Controller
Address and Word Expansion
PROM Programming
Power Switching
PROM Marking
References

Chapter 6

PROGRAMMABLE READ ONLY MEMORIES

A Read-Only Memory is a random access memory in which the stored information is fixed and non-volatile. By convention, a semiconductor ROM is a circuit whose stored information is fixed by a masking
operation during wafer processing, whereas a PROM is one whose contents are uniquely determined after processing and packaging. A ROM is best suited for systems produced in large volume, where the tooling charge for a unique mask is relatively small on a per-unit basis and is often counterbalanced by the
economies of batch processing. PROMs are the best choice in low volume production, in systems having a
limited useful life, in short procurement cycle situations and for applications wherein some degree of
system tailoring is required for each installation. For developmental and prototype work, wherein design
changes are normal occurrences and short turn-around times are essential, PROMs are an obvious choice.
Bipolar ROMs and PROMs offer access times in the 25-50 ns range for TTL and 15-20 ns for ECl, which
represent an order of magnitude improvement over equivalent MaS circuits. Historically, MaS ROMs
and PROMs have offered greater bit densities than have bipolar circuits. More recently, however, technological advances have placed bipolar densities between those of PMOS and silicon gate NMOS; continuing development promises to narrow the gap even further.
Certain types of MaS PROMs (EPROMs) can be completely erased and reprogrammed but bipolar PROMs
cannot. Fairchild bipolar PROMs are manufactured with all bits in the HIGH state. As indicated in Figure
6-1, changing a bit from HIGH to lOW consists of steering an applied current from the pertinent output
back to the intersection of the word and bit lines for the addressed cell. The current causes the fuse to open,
and thus a bit that has been changed to the lOW state cannot be changed back to the HIGH state. Fairchild bipolar PROMs use nichrome fuses, since this material has a long history of usage in microelectroniCS l - 4 and a great deal of experience has been gained. The fuse has a notch in the middle to concentrate
the energy and assure a wide, clean break.
OUTPUT
PIN

•

IpROG

BIT
DECODE

BIT
DRIVER

ADDRESS

___~____~______ WORD
WORD
DECODE

"

LINE

BIT LINE

Fig. 6-1.

Programming Current Path

6-3

On older data sheets, ROM and PROM outputs were called On and were drawn with bubbles to show that
the open-collector output pulls LOW and to indicate that an unprogrammed output is HIGH. Since the
bars and bubbles are not normally used to convey such a meaning, this publication and all fu.ture data
sheets describe the outputs as active HIGH, call them On and, therefore, show no bubbles. When the
terms "0" and "1" are used in coding or describing ROMs and PROMs, positive-true logic is assumed,
i.e., a "0" is a LOW and a "1" is a HIGH signal.

APPLICATIONS
ROMs and PROMs are widely used in computers of all sizes. They are finding increased usage in other
areas such as peripheral controllers, terminals, instruments and digital controls of all kinds. Specific applications include data and instruction storage in computers, microprogrammed system control storage,
look-up and decision tables, and address and priority mapping. Other applications include character/vector generation, encoding/decoding and sequential controllers.
ROMs and PROMs are also finding increased usage as replacements for combinatorial logic, wherein they
can replace from two to twentypackages 5 . In this type of service a ROM or PROM is treated as a truth
table. For example, a 4K PROM organized as 512 x S bits implements the truth table for eight functions
of nine variables. As a matter of convenience, the application examples that follow use the PROM part
numbers.

4-BIT COMPARATOR
The 93417/93427 1 K (256 x 4-bit) memory can readily be used as a 4-bit comparator (Figure 6 -2). In
this example, four of eight address lines are assigned to each of the input variables. Unlike conventional
MSI comparators with outputs limited to A=B, AB, the four PROM outputs can be programmed
for a wide variety of functions. Some of the possible functions are:
1.
2.
3.
4.

A + B: = n, > n, <
A - B: = n, > n, <
B - A: = n, > n, <
A x B: = n, > n, <

n
n
n
n

5.
6.
7.
S.

A -;. B: = n,
B -;. A: = n,
n  n, <
> n, <

n
n

where nand m can be any number or set of numbers and can be assigned different
values for each output.
If a 2K (512 x 4-bit) memory (93436/93446) is used, the function can be programmed for two different values or sets of nand m. The desired value or set can then be selected by the AS input.

1\0-

AO

cs

A1- A1
A2_ A2

A3- A3
8 0 - A4

93417/93427
256 X4

PROM

81_ A5
82 -

A6

83_ A7

1 1 '1 1
Fig.6-2. 4- Bit Comparator
6-4

HAMMING CODE GENERATOR/CHECKER/CORRECTOR
A PROM can also be efficiently used as a Hamming code generator/checker/corrector. By adding three
additional check bits to a 4-bit code, it is possible to detect and correct a single error. A 1K (256 x 4-bit)
PROM can be used to generate the three additional bits and to check and correct the 7-bit code (see Figure 6-3).
ENCODER/DECODER
A 512 x 8-bit PROM (93438/93448) is used as an encoder/decoder in another simple application illustrated in Figure 6 -4.Since the ninth address (A8) is the Decoder/Encoder Select, both functions can be
implemented in a single package. Specific applications include emulation, mapping and code conversion.

~

".{

CODE

AO

~

cs

CS

".{

A1

CODE

A2
A3

X

A4

X

AS

X

AS

93417/93427
2SS X 4
PROM

AO
A1
A2
A3
A4

CHECK {
BITS

93417/93427
25S X 4
PROM

A5
AS

HIGH

A7

A7

x = Don't Care
Condition

'--y--/

'--y--/
CORRECTED
CODE

CHECK
BITS

Code-Checking/Correcting Mode

Check-Sit-Generating Mode

Fig. 6-3. Hamming Code Generator and Checker/Corrector

II
AO

CS

A1
A2
A3

DATA

A4

93438/93448
S12 X 8
PROM

AS
AS
A7

DECODER/ENCODER
SELECT

A8

Fig. 6-4. Encoder/Decoder

6-5

8-BIT BINARY TO 3-DIGIT DECIMAL DISPLAY DECODER
The popular 8-bit microprocessor has created a demand for 8-bit binary-to-decimal display converters,
since a 3-digitnumber is not only easier to read, interpret, and remember than an 8-bit binary word, but
also requires less panel space for read-out. ROMs and PROMs are particularly well suited for such code
conversion, but a brute-force textbook design would require a 256 x 10 ROM plus three 7-segment decoder/drivers. The circuit in Figure 6 -5 achieves the same result with only a 256 x 4 PROM, three 7segment decoder/drivers with input latches (9374) and two gate packages.

r
'-'---

tr

CS
AO
A,
A2

93417/93427
266 X 4
PROM

A3
A4

17 0 ,

A6

,
,

o 0
o ,

0

,,
,

A6

DISPLAY
HUNDREDS

0

A7

0,02 0 3 0 4

2

:::Do-

fDI
I

200 kHz

~

to

300

n

ho

:- 'OOO~

±

I 1!

lb

b

O.01IlF

Ao A, A2 A3 EL RBI

AO A, A2 A3 El RBI

AO A, A2 Aa El RBI

9374

9374

9374

ABO a

b

c

d

•

f

9

RBoa

b

c

d

I

I
"HUNDREDS"

e

f

9

ii

"TENS"

RBO a

I

b

cd.

f

9

I ILl
"UNITS"

0-;;:'

100n

~

±="'
A7~

R--u--u--

0:=0 0:=0 0:=0
0=0 0=0 0=0

COMMON
ANODE

I

1

1

I

,

+3 TO
+6 V

Fig. 6-5. 8- Bit Binary to 3- Digit Decimal Display Decoder

6-6

The total number of required PROM bits is reduced by excluding the least significant bit from the code
conversion (LSBin == LSBout) and by generating the three possible values of 'hundreds' information (0, 1,
2), according to the small truth table, by combining the 17 input with one PROM output. This reduces the
PROM requirement to 128 x (3+4+1) bits. Since a PROM of this size is not commercially available, a 256
x 4 PROM can be used in a time multiplexed arrangement with the latches at the decoder inputs for demultiplexing the PROM output information.

PROGRAMMED LOGIC CONTROLLER
This easy-to-understand TIL/MSI oriented design for a small dedicated controller is applicable where a
minicomputer would be too expensive and a microcomputer would be too slow, too cumbersome to program or too complicated to understand. This concept uses one or two dozen inexpensive TTL/MSI circuits plus one or two PROMs and can implement practically any control function with up to 16 inputs
and up to 50 outputs.

A simple open loop controller, as found in every washing machine, is a good beginning. Here a synchronous motor drives a reduction gear, which in turn drives a drum with programming pins or cams that
activate the output switches (Figure 6 -6). The electronic equ iva lent of this pin-drum controller is shown
in Figure 6 -7 where an oscillator (motor) drives a .;- 256 counter (gearbox) addressing a PROM (drum)
with eight outputs. If the objective were to generate eight arbitrarily changing, completely random outputs, the design would stop here. Fortunately the real world does not usually requ ire outputs that change
in a completely random fashion. Rather, the requirement is to be able to activate and hold certain outputs
(solenoids, valves, lights, etc.) starting at a certain position in the program, and deactivate them later at
a different position. For this purpose the PROM represents an overdesign. It is simple to reduce the number of PROM outputs and/or increase the number of system outputs by using additional inexpensive
MSI components.

MOTOR

II

Fig. 6-6. Simple Open-Loop Controller

6-7

ABC

D

E

_

r-

F

G

H

! II II

! IIII
-

~3~1~

--------1 eET

eET
Ie .....
CP BINARY COUNTER
MR 00 0,02 03

CP

~3~1~

Te
BINARY COUNTER
MR '00 0,02 03

~

256 x 8 PROM
(ONE 93448 OR TWO 93427)

....--~-_-+-+-I-+--+-------III
~

6

"

J.

~
I-

-

-

~

M

"

~~

<'

~~

M

a

--~ ;iffiB~+----1f--I cr 0 ~!a (] ~+-+----1f--I~ g ~ ~ a t--+-+--I-~I--fcP en ~ ~ 8 _

~~

:<

~~

8~

o~
0

M

-[UW

:~ ~

j

8~

"
'"

Y

8~

I

0::-

~o-

~

0-

~

IY

So000080-

>---<'

0-

:<

;g(f-

o

"

"s:
M

0

3!i(0-

0-

8d~

w

50-~o--

'So--

~o--

-~
~

'?:P-'?:P--

.., :5
§ ~P--0
~p-:<
"'~

:5

oP---

8p-" - 8P-0

M

0>

-

-....-

-b
ETC

6-8

w

~p--

sp--oP-op--8p---

The PROM outputs can be interpreted as addresses and instructions. As shown in the example of Figure
6 -7, the first four outputs are an address activating, through a 9311 1-of-16 decoder, anyone of up to 16
MSI circuits. The remaining four PROM outputs are used as instructions to the selected MSI circuit. Address 15 activates the first 4-bit register, changing its four outputs to the associated 4-bit instruction
code coming out of the PROM. Address 14 selects another 4-bit register while address 13 selects a 9334
8-bit addressable latch. The 4-bit instruction determines which output is to be changed and to what level
it is to be changed. For an insignificant increase in cost, the number of outputs has been increased from
eight to over 64, with the constraint that only one group can be changed simultaneously.

This is still a very unsophisticated open-loop controller. It can be improved by adding a controlled speed
reduction, consisting of a presettable counter (Figure 6 -8). One instruction can change the instruction
rate to anyone of 16 values, maintaining it there until it is changed again. The real power of this design
is shown, however, when a conditional feedback, or - in programming terms - a conditional jump capability is included (Figure 6 -9). One of the 16 addresses is used to interrogate the status of eight input
lines, and the associated instruction defines which input is to be interrogated and which level is the desired one. The subsequent PROM output is then not interpreted as an address/instruction pair, but rather
as a program jump address. If the input under test has the expected level (HIGH or LOW), this jump address is loaded into the program counter and the program continues from this new address. If the input
under test does not have the expected level, the jump address is ignored and the program continues without a jump.

Obviously this design can be made even more sophisticated by adding ari,thmetic capabilities, data memory, address stacks, etc., but carrying this too far would defeat the basic advantage of this design, its
simplicity and economy. The advantage of this approach over conventional logic implementation lies
in the flexibility that it gives to the circuit designer.

The design of a small control system usually starts with a clear knowledge of the number of outputs and
inputs required and their electrical characteristics. But, the exact definition of how the control inputs affect the outputs (under all normal and abnormal circumstances) takes most of the time and leads to most
of the usual errors. The classical logic design can only start when the system design is finished, and will
require extensive changes if the system design is changed due to mistakes or new requirements.

The programmed controller, however, can be designed, constructed and tested as soon as the required
inputs and outputs are defined, essentially simultaneous with the detailed systems design. System design, programming, and circuit design can be done in parallel, significantly reducing turn-around time.
System changes can be implemented by changing the PROM, and can be tested and verified in hours instead of weeks.

ADDRESS AND WORD EXPANSION
Many PROM applications require expansion of the word lengt/) or the number of words. Figure 6-10
shows the interconnection of two 256 x 4-bit memories to develop a 256 x 8-bit array. Address expansion is shown in Figure 6 -11, which illustrates the use of two 256 x 4-bit memories to form a 512 x 4-bit
array. A 512 x 6-bit array utilizing three 256 x 4-bit devices is shown in Figure 6 -12. As a final example
of the expansion versatility of PROMs, Figure 6 -13 shows how sixteen 512 x 4-bit memories are interconnected to form a 2048 x 16-bit array.
6-9

II

I

co co
n
m m

-c

-(,0

iii

m

E

oo

a

0

J,

P-

w

A3

'If---

'I

m

~

[l

lOF 16 DECODfR

'I'

I

'"

~

':2

yyyyyyyy",,]

I

"

"'C-u

:3

0

w~
",

I)

....

~

" f...P ~gz~ .J f--

0

000,02 OJ 04 o~ Db 070809010011°12013014015

o

r

1

r--

m

o ~

P-

f...p ~~~ .Jl f-0-<'"
P2 c : " f-P ;;:
J'f...W J:lri

a

-c

::C""'W

~

0

~

I

r-1

I

}\;2 ~w ~

n

-Q<..-c 0

5;>;'~ ~

o

~

"-'

o~

(j)

0

0

I

I
,..---

z

~

-(

~~

5,

,.----

E

10

11

12

I)

14

IS

16

17

'I~

9312
8 INPUT MULTIPLEXER

11f

,

5,
1

n

o

1

L '"~

A2~'-c 0

5}1;'f:-~

o~

9"'

~w

~

~

E

I

A,

AO

A,I

I
A3

0

Y YY YY y y y y YY

9311

A,

-

~~

~.

~~
O~

~

I
-(

D

AO

Al

1

'I
-J

'---

,TI rrr r r r r

CL 00 0, 02 °304 05 06 07

'11111111
v

K

p- '---

SHIFT REGISTER

MR 000, °203

Y

I

OUTPUTS

Fig. 6-9. Programmed Logic Controller. Conditional Jump

II

-<:

J

9300

CP 4 BIT UNIVERSAL 03
K SHin REGISTER

MR 000, 020)

'J'

I

'" ~

-4""m

P--

g

li---- ao ~:D~ID 0" f--f'
J:f---- ~ 8~; .:0 f--J1
~
f--JI
J:i---- o cz

:9

~i----

PE Po PI P2 P3
-

9300

CP 4 BIT UNIVERSAL OJ

1

1L

P2 P3

~

"m

f2
JI

~

'---

1

PE Po P,

-(

000, 02 03 04 05 06 07 08 °9°100110, ;>0, P14{)1:,

I

b

A,

9334
8 BIT ADDRESSABLE LATCH

1 OF 16 DECODER

"m

n~

E

A3

~8

'i:~

~

A,

~p

~'-e

"'~

W

~

I)

~

~

~8

Wm

I

'If---

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o c
z
o;;l

~

W

I

E

,..--

P--

"

~
w~

I

m

o~m

,,\"- -

i

0001020304 Os 06 07 080901001101201]01401S

I

~f-

::1
S

93111QF16DErODER

(f)

0

I

J

, 4

9322

-

'3

t)

~

co

~
"
6'f- ,..-- ao :D!I>-0,

2.7k

""' °2
-0-°,
~

~

Te

15

C MR 000,°203

'41312~

2.7.

0,

2,7k

"';.,
~

2.7k

2.7k

---0-"

..

-0-0,

2.711

,.

"<>-

IswtTCH CLoseD .,..
TO PROGRAMI

op!.

O.Ol#F~ Z

,

16
Q

RUN

9316

2.7k

2.7.

1,1,1.1.

C

Vee

0
93436/93446
512 X 4

PROM

93436

5
+-5.0 V

I
I

I
I

~o

!
I
I
30 pF

5600:

LOAD

I

300 0:

>

:

o

I

~-i-:-::-:-:-~_---l'
L ':...O~~ _______ J

93446
Fig.6-16.

Fig.6-17. Output Waveforms

Power Switching Circuit

PROM MARKING
Since PROMs come marked with a device type for the unprogrammed part, it is usually necessary for the
user to mark the parts after programming so that he can identify individual patterns. An ordinary pencil
works well on the common white ceramic packages but any convenient marking method can be used as
long as it is relatively permanent. Fairchild PROMs are marked with device type and date code on the
lower 2/3 of the top surface. This leaves the upper 1/3 available for customer marking, which can be
performed using a thermosetting ink such as Markem*. The ink can be applied with a stick stamp readily
available from many suppliers. Acetone removes illegible or incorrect marks and isopropyl alcohol can
be used for clean up. After marking, the packages should be baked for one hour at 150°C to fix the ink.
REFERENCES
1. Barnes, D.E., and Thomas, J.E., "Reliability Assessment of a Semiconductor Memory by Design Analysis," IEEE 12th Annual Proceedings on Reliability Physics, (1974).
2. Eisenberg, P.H., and Nalder, R., "Nichrome Resistors in Programmable Read Only Integrated Circuits," IEEE 12th Annual Proceedings on Reliability Physics, (1974).
3. Mo, R.S., and Gilbert, D.M., "Reliability of NiCr 'fusible link' used in PROMs," Journal of Electrochemical Society, Vol 120, No. 7 (1973), p. 1001.
4. Franklin, P., and Burgess, D., "Reliability Aspects of Nichrome Fusible Link PROMs," IEEE 12th Annual Proceedings on Reliability Physics, (1974).
5. 'The New LSI," Electronics, (July 10, 1975).
6. Devaney, J.R., and Sheble III, A.M., "Plasma Etching and Other Problems," IEEE 12th Annual Proceedings on Reliability Physics, (1974).
*Markem Corporation, 150 Congress Street. Keen, NH 03431. Stock. numbers 8055521 for cerdip, 8058791 for solderseal (white)
ceramic or 805933 for plastic.

6-18

INTRODUCTION

NUIVIERICALINDEX Of! DEVICES·

.

SELECTION
GUIDES AND CROSS REFERENCE
.

GENERAL CHARACTERISTICS

RAMs···

PROMs

PRODUCT INFORMATION/DATA SHEETS

CHAPTER 7
• Data Sheets

Eel ISOPlANAR MEMORY FI00414
256 x I-BIT FULLY DECODED RANDOM ACCESS MEMORY
FAIRCHilD TEMPERATURE AND VOLTAGE COMPENSATED ECl

GENERAL DESCRIPTION - The F100414 is a 256-bit Read/Write Random Access
Memory, organized 256 words by one bit. It has typical access time of 7 ns and is
designed for high-speed scratchpad, control and buffer storage applications. The device
includes full address decoding on the chip, has separate Data In and non-inverted
Data Out lines, and has three active lOW Chip Select lines.

LOGIC SYMBOL
(19)
1161
(20) (4)
56 7
13

With on-chip voltage and temperature compensation the F1 00414 is compatible with
the FlOOK and F95K series of ECl logic. The device is packaged in the hermetic
ceramic 16-pin Dual In-line Package. It is also available in either a 16-pin or 24-pin
flatpak. The device is specified for operation over the temperature range OOC to 85°C.

•
•
•
•
•
•
•
•
•

VERY HIGH SPEED
COMPATIBLE WITH F100K and F95K ECL LOGIC
READ ACCESS TIME ~ 7 ns TYP
CHIP SELECT ACCESS TIME ~ 4 ns TYP
POWER DISSIPATION ~ 1.8 mW/BIT
50 kG INPUT PULL-DOWN RESISTORS ON CHIP SELECT
OUTPUTS CAN BE WIRED-OR FOR EASY MEMORY EXPANSION
POWER DISSIPATION DECREASES WITH INCREASING TEMPERATURE
ORGANIZED ~ 256 WORDS X 1 BIT

PIN NAMES
CS1, CS2, CS3
AO-A7
DIN
DOUT
WE

ADDRESS
DECODER

Ao

(13) 2

A,

(14) 3

A2

(23) 4

A3

(24) 9

A,

(1 )10

As

(2) 11

A6

(11)12

A,

CS

Fl00414

DOUT

15 (8)

VCC=PIN 16(9)
(

VEe =PIN 8 (21)
)= FLATPAK

Chip Select Inputs
Address Inputs
Data Input
Data Output
Write Enable Input

Ne

A5
A6

17

Ne

NC

DiN

Ne

He

A,

Ne

A,

WORD

WE DOu"T Vee

Me

A7

Ao

~-----N-O-T-E-:N-C----N-o-c-o-n-n.-c-tio-n------~.

A:,:-fl--D-L.___-----'

=Lf

WE

DIN

CONNECTION DIAGRAM
24-PIN FLATPAK
(TOP VIEW)

LOGIC DIAGRAM

X

(12) 1

(7)
14

-==--

CONNECTION DIAGRAM
DIP (TOP VIEW)
AO

Vee

AI

DOUT

A2

WE

A3

D,N

CS1

A7

CS2

A6

CS3

AS

VEE

A4

NOTE:
The 16-pin Flatpak version has the same
pinouts (Connection Diagram) as the Dual
In-line Package.

7-3

FAIRCHilD ECl ISOPlANAR MEMORY. F100414
FUNCTIONAL DESCRIPTION - The F1 00414 is a fully decoded 256-bit Read/Write Random Access Memory, organized
256 words by one bit. Word selection is achieved by means of an 8-bit address AO through A7'
The active LOW chip select inputs are provided for increased logic flexibility. This permits memory array expansion up to
2048 words with the F1 00170 decoder. For larger memories, the fast chip select time permits the decoding of Chip
Select, CS, from the address without affecting system performance.
The read and write operations are controlled by the state of the active LOW Write Enable, (WE). With WE held LOW,
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH, and the chip
selected. Data in the addressed location is presented at DOUT and is read out non-inverted. The DOUT is LOW except
when reading a stored HIGH.
Open emitter outputs are provided on the F1 00414 to aliow maximum flexibility in output wired-OR connection for
memory expansion.
TABLE 1 - TRUTH TABLE
INPUT

CSl

CS2'

OUTPUT

CS3

-WE

DIN

MODE

X

X

H*

X

X

L

NOT SELECTED

L

L

L

L

L

L

WRITE "0"

L

L

L

L

H

L

WRITE "1"

L

L

L

H

X

DOUT

NOTE,
L = LOW Voltage Levels = -1.7 V
H = HI GH Voltage Levels = ...... 0.9 V
(Nominal Values)
X = Don't Care

READ

*One or more Chip Selects H IG H

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VEE Pin Potential to Ground Pin
Input Voltage (de)
Output Current (de Output HIGH)

_65°C to 150°C
_55°C to 125°C
-7.0 V to +0.5 V
VEE to +0.5 V
-30 mA to +0.1 mA

GUARANTEED OPERATING RANGE
SUPPLY VOLTAGE (VEE)
MIN
-5.7 V

I
I

I

TYP

j

-4.5 V

AMBIENT TEMPERATURE (TA)
(NOTE 4)

MAX
-4.2 V

.'

DC CHARACTERISTICS: VEE
SYMBOL

= -4.5

V, VCC

= GND,

TA

CHARACTERISTIC
B

= O°C

to 85°C, output load 500 to -2.0 V

LIMITS
TYP
(Note 3)

UNITS

CONDITIONS

A

VOH

Output HIGH Voltage

'-1025

-955

-880

mV

VOL

Output LOW Voltage

-1810

-1715

-1620

mV

VOHC

Output HIGH Voltage

-1035

VOLC

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current, CS
All others

lEE

Power Supply Current

VIN

= VIHA or VILB
Loading is
500 to -2.0 V

mV
VIN

= VIHB or

VILA

-1610

mV

-1165

-880

mV

Guaranteed HIGH Signal for All Inputs

-1810

-1475

mV

Guaranteed LOW Signal for All Inputs

220

/lA

VIN = VIHA

170

/lA

VIN

mA

All inputs and output open

0.5
-50
-140

-100

7-4

= VILB

FAIRCHilD ECl ISOPlANAR MEMORY. F100414
PRELIMINARY AC CHARACTERISTICS: "EE

SYMBOL

=4.5 V ±5%; Output Load =50n And 10 pFto -2.0V, T A OOC to 85°C (Note 4)
MIN
LIMIT

PARAMETER

TYP
(Note 3)

MAX
LIMIT

UNITS

CONDITIONS

READ MODE
tACS

Chip Select Access Time

4

6

ns

Fig. 1a & b Measured at 50%

tRCS

Chip Select Recovery Time

4

6

ns

of I nput to Valid Output

tAA

Address Access Ti me

7

10

ns

(VILA for VOL or VIHB
for VOH)' Note 5.

WRITE MODE
tw

Write Pulse Width

7

5

ns

tWSD

Data Set-up Time Prior to Write

1

0

ns

tWHD

Data Hold Time After Write

2

0

ns

tWSA

Address Set-up Time

1

0

ns

tWHA

Address Hold Ti me

2

0

ns

tWSA

tw

=

=

1 ns

7ns

Fig. 2 Measured at 50% bf
Input to Valid Output

tWSCS

Chip Select Set-up Time

1

0

ns

(VILA for VOL or

tWHCS

Chip Select Hold Time

2

0

ns

VIHB for VOH)

tws

Write Disable Time

4

8

ns

tWR

Write Recovery Time

5

10

ns

RISE AND FALL TIME
tr
tf

'1 Output Rise Time
Output Fall Time

3

ns

Measured between 20% &

3

ns

80% points. (Fig. 1a)

4

pF

7

pF

CAPACITANCE
CIN
COUT

1 Input Lead Capacitance
Output Lead Capacitance

Measured with a
Pulse Technique

NOTES:

1. Conditions for testing, not shown in the tables are chosen to guarantee operation under "worst case" conditions.
2. The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes,

additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at VEE = -4.5 V, TA = 25°C and maximum loading.
4. The temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and two minutes warm up period. Temperature range
of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at
maximum temperature are:
{)JA (Junction to Ambient at 400 FPM air flow) = 50°C/Watt for ceramic DIP; 65°C/Watt for plastic DIP; NA for Flatpak.
{)JA (Junction to Ambient with still air) = 90°C/Watt for ceramic DIP; 110°C/Watt for plastic DIP; NA for Flatpak.
{)JC (Junction to Case) = 25°C/Watt for ceramic and plastic DIPs; 10°C/Watt for Flatpak.
5. The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
6. DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA SHEET:

The symbols and terms used in this data sheet have been chosen to agree with the latest standards of the Electronics Industries Association and the International Electrotechnical Commission. The relative values of the specified conditions and limits will be referenced to an algebraic scale. The extremities of
the scale are: "A" the value closest to positive infinity, "8" the value closest to negative infinity.

AC TEST LOAD AND WAVEFORMS

LOADING CONDITIONS

~:::, d- -F100414

•

INPUT LEVELS

',;

15

------ -~

r--

_~

~80o/:0%
'Ii

tr = tf = 2.5 ns TYP

All Timing Measurements Referenced to 50% of Input Levels
CL = 10 pF including Jig and Stray Capacitance

O.01 1lF f i l i

-=

RL = 50

VEE

7-5

n to -2.0 V

FAIRCHILD ECLISOPLANAR MEMORY. F100414
READ MODE PROPAGATION DELAY
FROM CHIP SELECT

DOUT

Fig.1a

READ MODE PROPAGATION DELAY
FROM ADDRESS

AOO""'~_5_0_%
I~~~-tAA-~\1

_______________________

.D_O_U_T_____________________

A:::

Fig.1b

WRITE MODE

CS

ADDRESS

50%~----------------------__I_
50%~ 1\
It--------------

------ ---

r-- ! - - ~~
-I \ _ - - - - - - - _ . 1/~

~-,

--------

50%--,j? - - - - - - - -

DIN

I-twHD-

50%~ ~-----7 V_

WE

~tWHA_

I-tWSDI--twSA

- - - - - - ----DOUT

twscs

tw

\

twHCS

/

VILA

I--tws-

f-VIHB

r--- twR

Fig. 2
NOTE: Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-6

FAIRCHilD ECl ISOPLANAR MEMORY. F100414

4096 WORO X N-BIT SYSTEM
A, __________________________________________

~------

A, __

A, __
A, __
A,--

A,-A,-A,-"'----------'
A,
A,

II

II

II

ROW 14

''"-:===~=--h
g
L-_ _ _

DIN;:'

~~~~

DINn~O_ _ _ _ _ _====t:=======::I:j~======W_-

o
o
DOUTn

Fig. 3.

7-7

•

Eel ISOPlANAR MEMORY FI00415
l024xl-BIT FULLY DECODED RANDOM ACCESS MEMORY
FAIRCHilD TEMPERATURE AND VOLTAGE COMPENSATED ECl

OEseR IPTION - The F1 00415 is a 1024-bit Read/Write Random Access Memory organized as 1024 words by one bit per word and designed for high-speed scratchpad,
control and buffer storage applications. The device is specified with a maximum read
cycle time of 20 ns over the commercial temperature and voltage range.
With on-chip voltage and temperature compensation, this memory is compatible with
the FlOOK and F95K Series of ECl logic. Other features include full address decoding
on chip, separate Data In and non-inverting Data Out lines, and an active lOW Chip
Select input.
The F1 00415 is packaged in a hermetic ceramic 16-pin dual in-line package. It is also
available in either a 16-pin or 24-pin flatpak. The device is specified for operation
over the O°C to 85°C temperature range.

•
•
•
•
•

COMPATIBLE WITH FlOOK AND F95K ECl lOGIC
MAXIMUM ACCESS TIME: 20 ns OVER TEMPERATURE
OPEN EMIITER OUTPUTS FOR EASE OF MEMORY EXPANSION
ORGANIZATION - 1024 WORDS X 1 BIT
POWER DISSIPATION: 0.5 mW/BIT

lOGIC SYMBOL

(12) 2

(7)

(4)

14·

15

13

Ao

(13) 3

A1

('4) 4

A2

(17) 5

As

('9) 6

'"

(20) 7

(6)

F100415

As

(22) 9

As

(23) 10

M

(1)11

As

(2) 12

A9

DOUT

1

I")

vee = PIN

16(9)
VEE = PIN 8(21)
( )=FLATPAK

CONNECTION DIAGRAM
24 PIN FLATPACK
(TOP VIEW)

PIN NAMES
Chip Select Input
Address Inputs
Data Input
Data Output
Write Enable Input

CS
AO-A9
DIN
DOUT

WE

NC

lOGIC DIAGRAM

9

1.

11

17

A3

16

NC

15

NC

1.

A2

13
12

A,

DIN NC Vee NC DOUT AO
ADDRESS

WORD

DECODER

DRIVER

NOTE: NC -

No connection

CONNECTION DIAGRAM
DIP (TOP VIEW)
0001

DOUT

cs

we

0"

AD

DIN

A,

cs

A,

WE

A3

A,

A,

AS

A5

A,
A6

NOTE:
The 16-pin Flatpak version has the same
pinouts (Connection Diagram) as the Dual
In-line Package.

7-8

FAIRCHilD ECl ISOPlANAR MEMORY. F100415
FUNCTIONAL DESCRIPTION - The Fl00415 is a fully decoded 1024-bit Read/Write Random Access Memory organized 1024 words by one bit. Bit selection is achieved by means of a 10-bit address, AO through Ag. One Chip
Select input is provided for memory array expansion up to 2048 words without the need for external decoding. For
larger memories, the fast chip select time permits the decoding of Chip Select (CS) from the address without increasing
address access time. The read and write operations are controlled by the state of the active LOW Write Enable (WE).
With WE and CS held LOW, the data at DIN is written into the addressed location. To read, WE is held HIGH and CS
held LOW. Data in the specified location is presented at DOUT and is non-inverted.
An unterminated emitter-follower output is provided on the Fl 00415 to allow maximum flexibility in output connection.
In many applications it is desirable to tie the outputs of several Fl00415 together to allow easy expansion. In other
applications the wired-OR is not used. In either case an external 50 n pull down resistor to -2 V or an equivalent network must be used to provide a LOW at the output when reading a logic "0".

ABSOLUTE MAXIMUM RATINGS (above which the uselullile may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VEE Pin Potential to Ground Pin
Input Voltage (de)
Output Current (de Output HIGH)
INPUTS

TABLE 1TRUTH TABLE

-65'C to +150'C
-55'C to +125'C
-7.0 V to +0.5 V
VEE to +0.5 V
-30 mA to +0.1 mA

OUTPUT

MODE

OPEN EM ITTER

CS

WE

H
L
L
L

X

X

L
L
H

L
H

L
L
L

X

DOUT

DIN

NOT SELECTED
WRITE ··0··
WRITE •• , ••

L = LOW Voltage Levels = -1.7 V
H = HIGH Voltage Levels = -0.9 V
(Nominal values)
X = Don't.Care

READ

GUARANTEED OPERATING RAN·GES
SUPPLY VOLTAGE (VEE)
MIN
-5.7 V

I
I

DC CHARACTERISTICS: VEE
SYMBOL

I
I

TYP
-4.5 V

-4.2 V

= -4.5V, VCC = GND, TA = Q'C to 85'C
LIMITS

CHARACTERISTIC
B

AMBIENT TEMPERATURE (TA)
(NOTE 4)

MAX

(Note 4)

(Note 6)

TYP
(Note 3)

UNITS

CONDITIONS

A
VIN

= VIHA or VILB

VIN

= VIHB or VILA

VOH

Output Voltage HIGH

-1025

-955

-880

mV

VOL

Output Voltage LOW

-1810

-1715

-1620

mV

VOHC

Output Voltage HIGH

-1035

VOLC

Output Voltage LOW

-1610

mV

VIH

Input Voltage HIGH

-1165

-880

mV

Guaranteed HIGH Signal for All Inputs

VIL

Input Voltage LOW

-1810

-1475

mV

Guaranteed LOW Signal for All Inputs

IIH

Input Current HIGH

220

pA

VIN

IlL

Input Current LOW, CS
All others

170

pA

VIN

lEE

Power Supply Current

mA

All Inputs and Output open

mV

0.5
-50
-150

-105

Loading is
50n 10 -2.0 V

= VIHA
= VILB

NOTES:
1. Conditions for testing, not shown in the tables are chosen to guarantee operation under "worst case" conditions.
2. The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at Vee = -4.5 V, TA = 25° C and maximum loading.
4. The temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and two minutes warm up period. Temperature range
of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at
maximum temperature are:

8JA (Junction to Ambient at 400 FPM air flow) = 50' C/Watt for ceramic DIP; 65' C/Watt for plastic DIP; NA lor Flalpak.
8JA(Junction to Ambiant with slill air) = 90·C/Watt for ceramic DIP; l10·C/Watt for plastic DIP; NA for Flatpak.
8JC (Junction to Case) = 25'C/Watt for ceramic and plastic DIPs; 10'C/Watt for Flatpak.

5. The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.

6. DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA SHEET:
The symbols and terms used in this data sheet have been chosen to agree with the latest standards of the Electronics Industries Association and the International Electrotechnical Commission. The relative values of the specified conditions and limits will be referenced to an algebraic scale. The extremities of
the scale are: "A" the value closest to positive infinity, "8" the value closest to negative infinity.

7-9

•

FAIRCHilD ECl ISOPLANAR MEMORY. F100415
AC CHARACTERISTICS: VEE

=-4.5 V ± 5%, TA =OOC to 85°C, VCC =GND, output load = 50n and 30 pF to -2.0 V

SYMBOL

PARAMETER

tACS
tRCS
tAA

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

tw

Write Pulse Width
(to Guarantee writing)
Data Sep-up Time
Prior to Write
Data Hold Time
After Write
Address Set-up Time
Prior to Write
Address Hold Time
After Write
Chip Select Set-up Time
Prior to Write

tWSD
tWHD
tWSA
tWHA
tWSCS

MIN

TYP
(Note 3)

8
8

5
5
13

20

CONDITIONS

ns
ns
ns

Fig la and lb measured at
50% of input to valid
output (V,LA for VOL
or V,HB or VOH)

tWSA = 5ns

14

9

ns

4

0

ns

4

0

5

3

ns

3

0

ns

4

0

ns

4

0
5

10

ns
ns

Fig. 2 measured
at 50% of input
to valid output
(V,LA for VOL or

15

ns

V,HB for VOH)

ns
ns

Measured between 20%
and 80% points.
(Fig. la)

pF
pF

Measure with a Pulse
Technique

tws

Chip Select Hold Time
After Write
Write Disable Time

tWR

Write Recovery Time

7

tr
tf

Output Rise Time
Output Fall Time

5

C'N
COUT

Input Pin Capacitance
Output Pin Capacitance

4

tWHCS

UNITS

MAX

5

5
8

7

tW= 14 ns

AC TEST LOAD AND WAVE FORMS
INPUT LEVELS

LOADING CONDITIONS

INPUT LEVELS

Vee

All Timing Measurements Referenced to 5()OA> of Input Levels

CL
RT

30 pF including Jig and Stray Capacitance

=

50

n

Termination of Scope

READ MODE PROPAGATION DELAY
FROM ADDRESS

READ MODE PROPAGATION DELAY
FROM CHIP SELECT

A~50'

ADD~_ _ _ _ _ _ _ _ _ __
~--

'AA--

DOUT
DATA OUTPUT

Fig.1b

Fig.1a

7-10

FAIRCHilD ECl ISOPlANAR MEMORY. F100415
WRITE MODE

50%\-------~--------------r

cs
CHIPSELECT

Ao~Ag

AOORESS INPUTS

DATA INPUT

WE
WRITE ENABLE

-~;----

1--_ _ _ twscs

---~-I

'WA

Fig. 2
NOTE:

Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the

worst case limits are not violated.

APPLICATIONS

~J.
D"

cs

-f-<

FlO0415
DOUT WE

~

~t

-

-

D,N

----

-I--

-----<>

CS ,Fl00415

Dour WE

~J..
D,N

•

-I--

CS' Fl00415
DOUT WE

-

res

-

Fl00170

~

..;!,~
D,N

-f--

Fl00415
DOUT WE

~

AT

-2.0 v

4096-WORD X l-BIT SYSTEM

Fig. 3

7-11

DOUT

~

EeL ISOPLANAR MEMORY F100416
256 X4-BIT PROGRAMMABLE READ ONLY MEMORY
FAIRCHilD TEMPERATURE AND VOLTAGE COMPENSATED ECl

DESCRIPTION-The F100416 is a fully decoded high-speed 1024-bit field Programmable
Read Only Memory, organized 256 words by four bits. The 100416 is voltage and temperature compensated and compatible with the F100K family. The device is enabled when
CS is LOW. Prior to programming, all outputs are active HIGH in the enabled state. Programmed bits will furnish LOW levels at corresponding outputs. When the device is disabled
(CS is HIGH) all outputs are forced LOW.
•
•
•
•
•
•
•
•

lOGIC SYMBOL

13

CS

ADVANCED ISOPlANAR PROCESS
FAST ADDRESS ACCESS TIME-ll ns TYP
ORGANIZATION-256 WORDS X 4 BITS
COMPATIBLE WITH FlOOK AND 95K ECl lOGIC
CHIP SELECT INPUT PROVIDES EASY MEMORY EXPANSION
OPEN EMITTER OUTPUTS FOR MEMORY EXPANSION
STANDARD l6-PIN DUAL IN-LINE PACKAGE
FUll ADDRESS DECODING ON CHIP

4

AO

3

A2

9

A3

10

A4

AI

6

AS
A6

7

PIN NAMES
Chip Select Input
Address Inputs
Data Outputs

Fl00416

A7

.,'.

15 14 12 11

Vep = GND (Read only) = Pin 1
Vep = +12 V (Programming only) = Pin 1
Vee = GND = Pin 16
VEE = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

lOGIC DIAGRAM

IGNO) VcP

AI

®

0,

A2

02

AO

cs

028

AS

03

03@

AS

04

o,@

A7

A4

VEE

A3

04@

(VA3

Vcc(GNOI

A4

(J)A7
~~--------------------------------------------~

Vep = GND (Read only) = Pin 1
Vep = +12 V (Programming only) = Pin 1

VEE = Pin 8

o=

Pin Numbers

Vee = GND = Pin 16

7-12

NOTE
Vep (Pin 1) is connected to the
Programmer (+12 V) during
programming only

ECLISOPLANAR MEMORY. F100416
ABSOLUTE MAXIMUM RATINGS (above whieh the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VEE Pin Potential to Ground Pin
Input Voltage (de)
Output Current (de Output HIGH)

-65°C to +150°C
-55°C to +125°C
-7.0 V to +0.5 V
VEE to +0.5 V
-30 mA to +0.1 mA

GUARANTEED OPERATING RANGES

SUPPLY VOLTAGE (VEE)

I

MIN

-4.8 V

I

DC CHARACTERISTICS: VEE

SYMBOL

I

TYP

I

-4.5 V

AMBIENT TEMPERATURE (TA)
(Note 4)

MAX
-4.2V

= -4.5V, VCC = GND, TA = O°C to +85°C (Note 4); Output Load = 50 a to -2.0V
LIMITS (Note 6)

CHARACTERISTIC

B

TYP

UNITS

A

CONDITIONS

(Note 3)
VOH

Output Voltage HIGH

-1025

-955

-880

mV

VOL

Output Voltage LOW

-1810

-1705

-1620

mV

VOHC

Output Voltage HIGH

-1035

VOLC

Output Voltage LOW

-1610

mV

VIH

Input Voltage HIGH

-1165

-880

mV

VIL

Input Voltage LOW

-1810

-1475

mV

Guaranteed LOW Signal for All Inputs

IIH

Input Current HIGH

200

/LA

VIN

IlL

Input Current LOW, CS

130

/LA

VIN

lEE

Power Supply Current

mA

All Inputs and Outputs open

-150

-115

= VIHA or VILB

VIN

= VIHB or VILA

Loading is

mV

0.5

VIN

50ato -2.0V

Guaranteed HIGH Signal for All Inputs

= VIHA
= VILB

NOTES:
1. Conditions for testing, not shown in the tables.are chosen to guarantee operation under "worst case" conditions.
2. The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at VEE = -4.5 V, TA = 25° C and maximum loading.
4. The temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and two minutes warm up period. Temperature range
of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at
maximum temperature are:
8JA (Junction toAmbient at 400 FPM air flow) = 50° C/Watt for ceramic DIP; 65°C/Watt for plastic DIP; NA for Flatpak.
8JA (Junction to Ambient with still air) = 90°C/Watt for ceramic DIP; 110°C/Watt for plastic DIP; NA for Flatpak.
8JC (Junction to Case) = 25°C/Watt for ceramic and plastic DIPs; 10°C/Watt for Flatpak.
5. The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
6. DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA SHEET:
The symbols and terms used in this data sheet have been chosen to agree with the latest standards of the Electronics Industries Association and the Inter·
national Electrotechnical Commission. The relative values of the specified conditions and limits will be referenced to an algebraic scale. The extremities of
the scale are: "A" the value closest to positive infinity, "S" the value closest to negative infinity.

AC CHARACTERISTICS: VEE

= -4.5 V

± 0.3 V, Output Load 50 a to -2.0 V, TA

= -30°C to +85°C

LIMITS
SYMBOL

PARAMETER
MIN

tAA

Address Access Time

tACS

Chip Select Access Time

UNITS

CONDITIONS

20

ns

Measured at 50% Points of both
Input and Output

8

ns

Measured at 50% Points of both
Input and Output

TYP
(NOTE 3)

MAX

11
4

7-13

•

ECllSOPlANAR MEMORY. F100416
PROGRAMMING SPECIFICATIONS
A. PROGRAMMING PULSE SEQUENCE
VCC = PIN 16 = GND
VEE = PIN 8 = -5.2 V ± 5%

VT

= -2.0 V (Termination Voltage)

Fig. 1 PROGRAMMING PULSES

X

ADDRESS
PINS

(2.3,4,5.6,7,9,10)

_ _..J

L

"-_________

VIH
VIL

, -_ _ _ _ _ _ _ _ _ _"'"' +11.5 V ± 0.3 V

VCP

~

PIN 1

'----oV

SELECTED OUTPUT

/

PIN (11,12,14 or 15)

t-"l0

INTERNAL VOLTAGE
_ _ _ _-J
~I
FROM PROM
ALL OUTPUTS TERMINATED
I~
IN 5 k!1 TO VT _ _ _ _ _ _ _ _- ,
......_ _ _ _ _ _ _ _ 0 mA

"~,,,-z.U

CHIP SELECT
PIN 13

-40mA_14mA

VCLAMP = - 5.9 V

TABLE 1
PROGRAM
INPUTS
X Address Pins (2,3,4,5,6)

Y Address Pins (7,9,10)
Chip Select CS Pin 13

B.

VIH
0.00 V - 0.1 V
-0.87 V ± 0.1 V

VERIFY
VIL
-3.00 V ± 0.1 V
-1.75 V ± 0.1 V

VIH
-0.87 V ± 0.1 V
-0.87V±0.IV
-0.87 V ± 0.1 V

VIL
-1.75V±0.lV
-1.75 V ± 0.1 V
-1.75V± 0.1 V

PROGRAMMING PROCEDURE
(Refer to Figure 1 and Table 1)
1. Apply power to the part: Vcc = Pin 16 = GND; VEE = Pin 8 = -S.2 V ± S%
2. Terminate all outputs (Pins 11, 12, 14 and IS) with S kll resistors to VT = -2.0 V; NOTE: All input pins,
including CS, have internal SO kll pull-down resistors to VEE.
3. Select the word to be programmed by applying the appropriate voltage levels, as shown in the
"Program" column of Table 1, to the address Pins (2,3,4,S,6,7,9 and 10).
4. After the address levels are set raise VcP = Pin 1 from 0 V to +11.S V ± 0.3 V.
S. After VcP has reached its HIGH level select the bit to be programmed by applying a HIGH level of
+3.00 V ± 0.12 V to the output associated with it, i.e., Pins (11, 12, 14 or IS). Only one bit (output) at a
time may be selected for programming. Uncommitted outputs are terminated as outlined in 2.
6. After the HIGH level (+3.00 V) has been established at the selected output pin, source a current of
-40 mA ± 4 mA out of the Chip Select input (Pin 13) to program the selected bit; this applied current
pulse which is 100 I's wide and has an approximate risetime of 1 I's is to be furnished by a current
sink which clamps at VCLAMP = -5.9 V.
7. To verify a lOW in the bit just programmed follow this sequence:
(a) Remove current pulse from CS pin.
(b) Remove applied voltage from selected output pin.
(c) lower VcP from "HIGH level" to GND.
(d) Keep same address but change its levels to normal ECl levels as outlined in the verify
column of Table 1.
(e) Enable the chip by applying a lOW level (VIL) to CS (Pin 13), or leave it open.
(f) Sense the level at the selected output pin; a lOW level indicates successful programming
whereas a HIGH level is a fail indication; in the latter case reprogramming of the bit can
be attempted.
8. To program other bits in the memory repeat steps 3 through 7.

7-14

Eel ISOPLANAR MEMORY F100422
256 x 4 FULLY DECODED RANDOM ACCESS MEMORY
FAIRCHilD TEMPERATURE AND VOLTAGE COMPENSATED ECl

GENERAL DESCRIPTION-The F100422 is a 1024-bit Read/Write Random Access
Memory, organized 256 words by four bits per word. It has a maximum read access time
of 10 ns and is designed for high-speed scratchpad, control and buffer storage applications. The device includes full address decoding on the chip and has separate Data In
and non-Inverted Data Out Imes. Four active lOW Block Select lines are provided to
select each block independently.
The F 100422 is compatible with the FlOOK and F95K ECl families and includes on-chi p
voltage and temperature compensation for improved noise margin. The device is packaged
in a hermetic 24-pin dual in-line or 24-pin flatpak package and specified for operation
over the temperature range of 0° C to 85° C.
•
•
•
•
•
•

VERY HIGH SPEED
COMPATIBLE WITH FlOOK AND F95K ECl LOGIC
READ ACCESS TIME -1 0 ns MAX
POWER DISSIPATION - 800 mW TYPICAL
FOUR BLOCKS CAN BE INDEPENDENTLY SELECTED
ORGANIZED 256 WORDS x 4 BITS

PIN NAMES
BS, - BS4
Ao - A7
0, - 04

lOGIC SYMBOL
(12) (14) (5)

9

(22)19

Ao

(23)20

A,

(24) 21

A,

(1)22

A,

(2}23

A,

(18)15

A,

(1S) 16

A,

14

12

13

,3, ,4,
24

1

(20) 17

(11)

,.,3

(13)

(0)

Vee = Pin 6 19J
VeCA:= Pin 7 1101
VEE = Pin 18 121)
i ~

WE

4

F100422

Block Select Inputs
Address Inputs
Data Inputs
Data Outputs
Write Enable Input

0, - 04

(7) (17) (15) (16)

2

11

FLATPAK

CONNECTION DIAGRAM
FlATPAK (TOP VIEW)

A,

A.

Ao

VeE

A.

A,

A,

A,

lOGIC DIAGRAM

A,
D,

D,
D,

as,

BS2

0,

0,

WE

is:

Vee VeCA 0,

BS7

CONNECTION DIAGRAM
DIP ,TOP VIEW
Ao
D,

A,
A,

ROW
SELECT

256
BITS

256
BITS

256
BITS

A3
A,

256
BITS

D,

as;

A,

0,

A,

as,

A,

0,

A,

Vee

Ao

VeCA

V"

o.

COLUMN
SELECT

as.

A,

0,

A,

SS;
0.

7-15

D,

•

Eel ISOPLANAR MEMORY FI00470
4096 x I-BIT FULLY DECODED RANDOM ACCESS MEMORY
FAIRCHilD TEMPERATURE AND VOLTAGE COMPENSATED ECl

DESCRIPTION-The Fl00470 is a 4096-bit Read/Write Random Access Memory organized 4096 words by one bit per word. Designed for high-speed scratchpad, control
and buffer storage applications. The device is specified with a typical read cycle time
of 25 ns.

lOGIC SYMBOL

,.

With on-chip voltage and temperature compensation, this memory is compatible with
the FlOOK and F95K Series of ECl logic.

A2
A3
A.

The Fl00470 is packaged in a hermetic ceramic l8-pin dual in-line package and is
specified for operation over the O°C to 85°C temperature range.

AS
A.

COMPATIBLE WITH F100K and F95K ECl lOGIC
TYPICAL ACCESS TIME 25 ns
OPEN EMITTER OUTPUTS FOR EASE OF MEMORY EXPANSION
ORGANIZED-4096 WORDS X 1 BIT
POWER DISSIPATION OF 0.20 mW/BIT

15

Ao
A,

Other features include full address decoding on chip, separate Data In and noninverting Data Out lines, and an active lOW Chip Select input.

•
•
•
•
•

17

'0

A7

"

AS

'2

A9

13

A,O

,.

100470

A"

°OUT

PIN NAMES
Chip Select Input

CS
AO to A11

Address Inputs

Vee

DIN

Data Input

GNO

DOUT
WE

Write Enable Input

= Pin 18
= Pin 9

Data Output
CONNECTION DIAGRAM
DIP (TOP VIEW)

lOGIC DIAGRAM

Dour
AO

cs
WE
D,N

'-----~~,------~

Vec
D,N

A,

cs

A2

WE

A3

A"

A4

A,o

AS

Ag

AS

AS

VEE

A7

NOTE:
The F latpak version has the same

ADDRESS INPUTS

pinouts (Connection Diagram) as the

Dual In· line Package.

7-16

FAIRCHILD ECLISOPLANAR MEMORY. F100470
FUNCTIONAL DESCRIPTION - The F100470 is a fully decoded 4096-bit Read/Write Random Access Memory organized
4096 words by one bit. Bit selection is achieved by means of a 12-bit address, AD to A11. One Chip Select input is provided
for memory array expansion up to 8196 words without the need for external decoding. For larger memories, the fast
chip select time permits the decoding of Chip Select (CS) from the address without increasing address access time. The
read and write operations are controlled by the state of the active LOW Write Enable (WE). With WE and CSheld LOW,
the data at DIN is written into the addressed location. To read, WE is held HIGH and CS held LOW. Data in the specified
location is presented at DOUT and is non-inverted.
An unterminated emitter-follower output is provided on the F100470 to allow maximum flexibility in output connection.
In many applications such as memory expansion, the outputs of many F100470 can be tied together. In other applications the wired-OR is not used. In either case an external 50 n pull down resistor to -2 V or an equivalent network
must be used to provide a LOW at the output when it is off.

TABLE 1 - TRUTH TABLE
INPUTS

•

CS

WE

H
L
L
L

X
L
L
H

L

=:

OUTPUT
MODE

OPEN EMITTER

D,N
X
L
H
X

NOT SELECTED

L
L
L

WAITE "0"

WRITE "1"
READ

DOUT

LOW Voltage Levels

=:

-1.7 V

H =: HIGH Voltage Levels =-0.9 V
(Nominal values)

X

=

Don't Care

ABSOLUTE MAXIMUM RATINGS (above whieh the uselullile may be impaired)
Storage Temperature

-65°C to +150°C
-55°C to +125°C
-7.0 V to +0.5 V
VEE to +0.5 V
-30 mA to +0.1 mA

Temperature (Ambient) Under Bias
VEE Pin Potential to Ground Pin

Input Voltage (de)
Output Current (de Output HIGH)

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (VEE)
MIN
-5.7 V

I
I

DC CHARACTERISTICS: VEE
SYMBOL

I
I

TYP
-4.5 V

AMBIENT TEMPERATURE (TAl
(NOTE 41

MAX
-4.2 V

= -4.5 V, Vee = GND, Output Load = 50 nand 30 pF to
LIMITS

CHARACTERISTIC
B

VOH

Output Voltage HIGH

(Note 6)

TYP
(Note 3)

UNITS

-955

-880

mV

-1715

-1620

mV

VOL

Output Voltage LOW

-1810

Output Voltage HIGH

-1035

VOLC

Output Voltage LOW

VIH

Input Voltage HIGH

-1165

VIL

Input Voltage LOW

-1810

IIH

Input Current HIGH

IlL

Input Current LOW. CS
All others

0.5
-50

lEE

Power Supply Current

-195

= ooe to

+85°e (Note 41

CONDITIONS

A

-1025

VOHC

-2.0 V, TA

mV

VIN

= VIHA

or VILB

VIN

= VIHB

or VILA

Loading is
50 n to -2.0 V

-1610

mV

-880

mV

Guaranteed HIGH Signal for All Inputs

-1475

mV

Guaranteed LOW Signal for All Inputs

220

fJA

VIN

= VIHA

170

fJA

VIN

= VILB

mA

All Inputs and Output open

-160

7-17

•

FAIRCHilD ECl ISOPlANAR MEMORY. F100470
AC CHARACTERISTICS: VEE

= -4.5 V ±5%,TA = O°C to 85°C, Output load = 50 0, 30 pF to -2.0 V

SYM80l

PARAMETER

tACS
tRCS
tAA

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

tw

Write Pulse Width
(to Guarantee writing)
Data Set-up Time
Prior to Write
Data Hold Time
After Write
Address Set-up Time
Prior to Write
Address Hold Time
After Write
Chip Select Set-up Time
Prior to Write

tWSD
tWHD
tWSA
tWHA
tWSCS

MIN

TYP
(Note 3)

MAX

UNITS

10
10
25

15
15
35

ns
ns
ns

25

18

ns

5

1

ns

5

1

ns

5

ns

5

1

ns

5

1

ns

CONDITIONS
Fig 1a and 1b measured at
50% of input to valid
output (VilA for VOL
or VIHB or VOH)

Fig. 2 measured
at 50% of input
to valid output
(VILA for VOL or
VIHB for VOH)

tws
tWR

Chip Select Hold Time
Aher Write
Write Disable Time
Write Recovery Time

tr
tf

Output Rise Time
Output Fall Time

5
5

ns
ns

Measured between 20%
and 80% points.
(Fig.la)

C1N
COUT

Input Pin Capacitance
Output Pin Capacitance

4

pF
pF

Measure with a Pulse
Technique

tWHCS

5

ns
ns
ns

1.

7

15
20

10

7

NOTES:
1. Conditions for testing. not shQwn in the tables are chosen to guarantee operation under "worst case" conditions.
2. The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Tvpical values are atVEE=-4.5 V. TA =25°Cand maximum loading.
4. The temperature ranges arB guaranteed with transverse air flow exceeding 400 linear feet per minute and two minutes warm up period. Temperature range
of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at
maximum temperature are:
8JA IJunction to Ambient at 400 FPM air flow) = 50°ClWatt for ceramic DIP; 65° C/Watt for plastic DIP; NA for Flatpak.
(JJA {Junction to Ambient with still air} = 90°C/Watt for ceramic DIP; 110 0 C/Watt for plastic DIP; NA for Flatpak.
8JC (Junction to Case) = 25° C/Watt for ceramic and plastic DIPs; 10° C/Watt for Flatpak.
5. The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
6. DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA SHEET:
The symbols and term.s used in this data sheet have been chosen to agree with the latest standards of the Electronics Industries Association and the International Electrotechnical Commission. The relative values of the specified conditions and limits will be referenced to an algebraic scale. The extremities of
the scale are: "A" the value closest to positive Infinity, "S" the value closest to negative infinity.

AC TEST LOAD AND WAVEFORMS

INPUT lEVELS

LOADING CONDITIONS

Vee

O9V-1.7 V

--------Kr--:-

i

20%

----'I

Irl---1

r--- If,

-

t.

~

I,

~

2.5 ns TYP

All Timing Me~surements Refer~nced to 50% of Input Levels
CL = 30 pF including Jig and Stray Capacitance
RT = 50

7-18

n

Termination of Scope

FAIRCHilD ECl ISOPlANAR MEMORY • F100470

READ MODE PROPAGATION DELAY
FROM ADDRESS

READ MODE PROPAGATION DELAY
FROM CHIP SELECT

AO~"
50%

ADDRESS INPUTS

_ _ _ _ _ _ _ __

-+i

,

IAA _ _ _

DOUT
DATA OUTPUT

Fig.1b

Fig. 1.

WRITE MODE

cs
CHIP SELECT

AO -A"

~~-

------- ------------- ---r
J- --1'-__
___

50%~t\1
--i__-.JI \'-________________..J/\.'-_+-_

_AO_O_RE_'_"_N'_U_TS_ _

-0-;;;----- - - - - - , I
DATA INPUT

5m,J\=_.:..-~_~

_.:.=_./ '-_+__1-_
__ lWHO

50'" .... . - --.-IWSO ___

I\

-

--

- - - lWSA

~---+-+-----,<-

-o;;;,;----~---------t-"""\
DATA OUTPUT

/ ---

_ - _______ -

IWHA

-

lWHCS _ _

i
I
--I

I~

1 - - - - - t W S C S _ _ _~-I
VILA

1'---+-----'
--twS_

Fig. 2

NOTE
Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limIts are not violated

7-19

II

Eel ISOPLANAR MEMORY F10145A
16 x 4 REGISTER FILE (RAM)
FAIRCHilD VOLTAGE COMPENSATED ECl

GENERAL DESCRIPTION-The F10145A is a high-speed 64-bit Random Access
Memory organized as a 16 - word by 4- bit array. External logic requirements are
minimized by internal address decoding, while memory expansion and data bussing are
facilitated by the output disabling features of the Chip Select (CS) and Write Enable (WE)
inputs.
A HIGH signal on CS prevents read and write operations and forces the outputs to
the LOW state. When CS is LOW, the WE input controls chip operations. A HIGH
signal on WE disables the Data input (Dn) buffers and enables readout form the
memory location determined by the Address (An) inputs. A LOW signal on WE forces
the an outputs LOW and allows data on the Dn inputs to be stored in the addressed
location. Data exits in the same logical sense as presented at the data inputs, i.e.,
the memory is non-inverting.

LOGIC SYMBOL

(7)3

(1) 13

•
•

READ ACCESS TIME-7 ns TYP
50 kQ INPUT PULL·DOWN RESISTORS

•

OUTPUTS CAN BE WIRED·OR FOR EASY MEMORY EXPANSION

•

CHIP SELECT ACCESS TIME-4 ns TYP

•
•

VOLTAGE COMPENSATED, INSENSITIVE TO POWER SUPPLY VARIATIONS
FULLY COMPATIBLE WITH ALL 10,000 SERIES ECL

PIN NAMES
CS
AO-A3
00- 0 3
WE

00-03

Chip Select
Address lines
Data Input lines
Write Enable
Data Output li nes

Vee = Pin 16 (4)
VEE = Pin 8 (12)
(

LOGIC DIAGRAM

) = Flatpak

CONNECTION DIAGRAM
DIP (TOP VIEW)

WE

os

AO

"

DECODER
DRIVF.RS

ADDRESS
DECODER

0,

Vee

00

02

cs

03

0,

WE

00

03

A2

'3
vee = Pin 16 (4)
VEE = Pin 8 (12)

7-20

A3

02

A2

Ao

VEE

A1

FAIRCHILD ECl ISOPlANAR MEMORY. F10145A
ABSOLUTE MAXIMUM RATINGS (above whieh the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VEE Pin Potential to Ground Pin
Input Voltage (de)
Output Current (de Output HIGH)

-65°C to +150°C
-55°Cto+125°C
-7.0Vto+O.5V
VEEtO+O.5V
-30 mA to +0.1 mA

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (VEE)

I

MIN
-5.46 V

I

DC CHARACTERISTICS: VEE

TYP
-5.2 V

= -5.2 V,

I

I

AMBIENT TEMPERATURE
MAX

Note 4

-4.94 V

o°C to +75°e

= GND

Vec

INotes 1-4)

LIMITS INote 6)
SYMBOL
VOH

VOL

VOHC

CHARACTER ISTIC
Output Voltage HIGH

Output Voltage LOW

Output Voltage HIGH

B

TYP

UNITS

A

-1000

-840

-960

-810

mV

+75°C

-900

-720
-1665

-1850

-1650

+25°C

-1830

-1625

+75°C

mV

mV

-1645

mV

-1630

IIH

Input Voltage LOW

+25°C

-1045

-720

+75°C

-1870

-1490

-1850

-1475

+25°C

-1830

-1450

+75°C

200

220

lEE

Power Supply Current

0.5
-150

-100

7-21

mV

O°C

-810

WE,DO-D3
Input Current LOW

Loading is

50

n

to -2.0 V

VIN

= VIHB

or VILA

+75°C

-1105

Input Current HIGH

IlL

O°C

-840

200

VILB

O°C

-1145

CS,AO-A3

= VIHA or

+25°C

-1605

VIL

VIN

+75°e

Output Voltage LOW

Input Voltage HIGH

O°C

+25°C

-920

VIH

o°c

-1870

-1020

CONDITIONS

+25°C

-980

VOLC

TA
(Note 4)

mV

O°C

Guaranteed Input Voltage

HIGH for All Inputs

Guaranteed Input Voltage
LOW for All Inputs

p.A

+25°C

VIN

= VIHA

p.A

+25°C

VIN

= VILB

mA

+25°C

Inputs and Output Open

•

FAIRCHILD ECl ISOPlANAR MEMORY. F10145A
AC CHARACTERISTICS: VEE = - 5.2 V, TA = 25·C
SYMBOL

tACS
tRCS
tAA

CHARACTERISTIC
Access/Recovery Times
Chip Select Access
Chip Select Recovery
Address Access

B

LIMITS
TYP

A

3.0
3.0
4.5

4.5
4.5
6.5

6.0
6.0
9.0

4.5
4.5
3.5

3.0
2.5
1.5

ns
ns
ns

-1.0
0.5
1.0

-2.5
0.0
-1.0

ns
ns
ns

tWHD
tWHCS
tWHA

Write Times
Set·Up
Data
Chip Select
Address
Hold
Data
Chip Select
Address

tWR
tws

Write Recovery Time
Write Disable Time

3.0
3.0

4.5
4.5

tw

Write Pulse Width, Min

4.0

tcs

Chip Select Pulse Width, Min

tWSD
tWSCS
tWSA

tCSD
tcsw
tCSA
tCHD
tCHW
tCHA

tTLH
tTHL

Select Times
Set·Up
Data
Write Enable
Address
Hold
Data
Write Enable
Address
Transition Times
20% to 80%
80% to 20%

6.0
6.0

UNITS

CONDITIONS

ns
ns
ns

Figures 1, 3

Figures 1, 2a

ns
ns

Figures 1, 3

2.5

ns

Figures 1, 2a

4.0

2.5

ns

4.5
4.5
3.5

3.0
2.5
1.5

ns
ns
ns

-1.0
0.5
1.0

-2.5
0.0
-1.0

ns
ns
ns

1.5
1.5

2.5
2.5

3.9
3.9

ns
ns

Figures 1, 2b

Figures 1, 3

NOTES;
1. Conditions for testing, not shown in the tables are chosen to guarantee operation under "worst case" conditions.
2. The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes.
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are atVEE= -5.2 V, TA =25°C and maximum loading.
4. The temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and two minutes warm up period. Temperature range
of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at
maximum temperature are;
BJA (Junction to Ambient at 400 FPM air flow) = 50· C/Watt for ceramic DIP; 65" C/Watt for plastic DIP; NA for Flatpak.
BJA (Junction to Ambient with still air) = 90· C/Watt for ceramic DIP; 110· C/Watt for plastic DIP; NA for Flatpak.
BJC IJunction to Case) = 25· C/Watt for ceramic and plastic DIPs; 10· C/Watt for Flatpak.
5. The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
6. DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA SHEET;
The symbols and terms used in this data sheet have been chosen to agree with the latest standards of the Electronics Industries Association and the International Electrotechnical Commission. The relative values of the specified conditions and limits will be referenced to an algebraic scale, The extremities of
the scale are: "A" the value closest to positive infinity, "8" the value closest to negat~ve infinity.

7-22

FAIRCHilD ECl ISOPlANAR MEMORY. F10145A
SWITCHING CIRCUIT AND WAVEFORMS
Fig. 1

\

I

RTI

Vcc

Ir =lf=2.0 !O.2 ns

:

Q

{

+ 1.11

V =: H IG H

L1 and L2 = equal length 50 Q impedance lines
RT = 50 Q termination of scope
CL = Jig and stray capacitance...; 5.0 pF
Decoupling 0.1 ~F from gnd to VEE and VCC
VCC1 =VCC2=2.0 V
VEE= -3.2 V
Open input = LOW

O>-------

>~

u

-0.5

l'i

~

0

~

-1.0

I

>TA

115

u

~

100

Ii'

2.0

5.0

4.0

-:'::'c -

4.5 V

i'..

85

20
TA

0

'i
~

>Z

~

-1.0

u

of'"

~

-15

0.7

'"

V

DOUT +-

0
N

~

~
~

Vee = 5.0V

o

a

100

50

200

150

LOAD CAPACITANCE - pF

AMBIENT TEMPERATURE-

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS SUPPL Y VOL TAGE

=

05

55 C
'25 C
+125 C

~
~

E
I

-05

>-

~TA

/'

:;

140

100

,/'

~TA

-

../ V

V

~

"-

60

TA
TA
TA

>-

z

06

V

1.0

is"'

"~

i'..

0.5

oc

ooIUT-,1

u

'" '" "'"

20

r--- I -

"

55V

INPUT CURRENT VERSUS
INPUT VOL TAGE
VERSUS TEMPERATURE

~

0.5

I--

'"
"
w

~

-05

0.4

ill

""'- i'..

-60

I

0.3

2.0

80

E

0.2

NORMALIZED
ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE

,,- ~

«

W

POWER SUPPLY CURRENT
VERSUS TEMPERATURE

1"- ~ "- I'..

90

J
0.1

6.0

_55°C

=

Your - OUTPUT VOLTAGE "" VOLTS

I
U

u

30

TA

Your - OUTPUT VOLTAGE - VOLTS

95

oc

i!

""

-~e~r ",",vee

105

~

~

1.0

-

110

E

z

I

-1.5

-2.0
-1.0

~

V

j ~'

~

o

-55"C
Q

~

>-

=

~TA=25°C

I'-TA =i25 C

>-

"

- TA ""25

~

~

"

-

e

>-

>-

/

jV
~I
c~

TAOr

I

(

Z

~
~

!jt

vcc Js .ov

~

i3

f125 C

VCe"45~~
50V

.a ~~e 4S!
P' Vee
"Vee

Vee

=

55V

50V

- 5.5 V

-1.0

l-

t25 C

ii'

TA - -55"C

~

I

~

-1.5

z
20

--2.0
V CC

l 50V

TA -. j25 C

-2.5
-1.0

1.0

30

5.0

7a

90

-2.5
-1.0

11

10

3.0

5.0

70

9.0

VIN -INPUT VOLTAGE - VOLTS

VIN - INPUT VOL rAGE - VOLTS

7-56

11

FAIRCHILD ISOPLANAR TTL MEMORY. 93410j93410A
AC TEST LOAD AND WAVEFORM
LOADING CONDITION

INPUT PULSES

T~-(~
~I
I

300~!

-

h

-

-

-

-

-

--

-

--

u

-

-

-

-

-

-

- -

-

-

-

93410/9341OA

~I

-90

-

-10""

I~------------

t--- IOns

Th--------------1-..-j

30pF
ICAPACITANCE

35V pp

I

_'0""

I

t - ~ -- ------------- - ~ ---

INCLUDING SCOPE
r--~

- \-

, ,

Dour

I--r--

~h_

90'10

ANO JIG)

----

I

,

--

I

I

I

AC WAVEFORMS
READ MODE
PROPAGATION DELAY FROM CHIP SELECT

Cs1 C"S2
CHIP SELECT

CS3

x

PROPAGATION DELAY FROM ADDRESS

X

AO roA 7

_ _ _ _ J , ' -_ _ _ _J

X,'-----_

ADDRESS

______- J

_

,

' -_______________________

,

X

DOUT

DATA OUTPUT
DOUT

--r-----------'

,

,

~tRCS------.l

1 - ,_ .

: '---

---'AA-----,--~_l

(ALL TIME MEASUREMENTS REFERENCED TO 1.5 V)

WRITE MODE
cs,

CSl. CS3
CHIP SELECT

Aotoll 7

X"
X
--~x~----~x~~_ _ _ _ _- J

' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~,

' -_ _ _ __

,,

,

WE
WRITE ENABLE

I

!-tWHO-'

WHA

,-------...:'-twscs-------'
DATA OUTPUT

I

:---t

1--1WSA~

Dour

,

,

~IWSD_:

- -_ _-------'----'I
,
,
,
r-1WS--'

,

,

--!
tWHCS------

\-------,
,

,.-...-tWR - - - .

(ALL TIME MEASUREMENTS REFERENCED TO 1.5 V)
NOTE: Timing Diagram represents one solution which results in an optimum cycle time Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-57

•

TTL ISOPLANAR MEMORY 93411/93411A
256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93411 and 93411A are high -speed 256-bitTTL Random Access
Memories with full decoding on chip. They are organized 256 words by one bit and are
designed for scratchpad, buffer and distributed main memory applications. The devices
have three chip select lines to simplify their use in larger memory systems. Address input pin locations are specifically chosen to permit maximum packaging density and for
ease of PC board layout. An uncommitted collector output is provided to permit "ORties" for ease of memory expansion.
•
•
•
•

•
•
•
•

REPLACEMENT FOR 54/74S206 AND EQUIVALENT DEVICES
ORGANIZATION - 256 WORDS X 1 BIT
THREE HIGH-SPEED CHIP SELECT INPUTS
TYPICAL ACCESS TIME
93411A
Commercial
40 ns
45 ns
93411
Commercial
45 ns
93411
Military
ON CHIP DECODING
POWER DISSIPATION - 1.8 mW/BIT
POWER DISSIPATION DECREASES WITH TEMPERATURE
INVERTED DATA OUTPUT

A1

10

AS

11

A7
DOUT

Chip Select Inputs

DIN

Data Input

0.5 U.L.

DOUT
WE

Data Output

10 U.L.

Write Enable

0.5 U.L.

NOTES:
a. 1 Unit Load (U.L.I ~ 40 f.JA HIGH ;1.6 mA LOW
b, 10 U.L. is the output LOW drive factor. An external pull-up resistor is needed to provide HIGH
level drive capability. This output will sink a maximum of 16 rnA at VOUT = 0.45 V

VCC=Pin 16
GND'= Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

AD

LOGIC DIAGRAM

A,
WORD

CDAoliOECOOERGORIVER
16

It;

16

ARRAY

CSl

A2

CS2

D,N

CS3

WE

DOUT

A7

A4

A6

MEMORY CEll

'--.----r---'
WE@

Vee ~

o~

A3
93411/93411A

0.5 U.L.

GND

A2

15

A5

Address Inputs

@lA2
@A3

14

A4

CS1' CS2' CS3
AO-A7

®Al

345

LOADING
(Notes a, b)
0.5 U.L.

PIN NAMES

X ADDRESS

LOGIC SYMBOL

~

A5

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Une Package.

Pin 16
Pin 8

Pin Numbers

7-58

FAIRCHILD ISOPLANAR TTL MEMORY. 93411/93411A
FUNCTIONAL DESCRIPTION - The 93411/93411 A are fully decoded 256 - bit Random Access Memories organized
256 words by one bit. Word selection is achieved by means of an 8 -bit address, AO through A7.
Three Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select. CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable (WE, pin 12). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected.
Data in the specified location is presented at DOUT'
Uncommitted collector outputs are provided to allow maximum flexibility in output connection. In many applications,
such as memory expansion, the outputs of several 93411 s or 93411 As can be tied together. In other applications the
wired-OR is not used. In either case an external pull-up resistor of value RL must be used to provide a HIGH at the output
when it is off. Any value of RL within the range specified below may be used.

VCC(MAX)
16 - F.O. (1.6)

RL is in kO
n = number of wired-OR outputs tied together
F.O. = number of TTL Unit Loads (U.L.) driven
ICEX = Memory Output Leakage Current in mA
VOH = Required Output HIGH level at Output Node

VCc(MIN) - VOH
n (ICEX) + F.O. (0.04)

The minimum value of RL is limited by output current sinking ability. The maximum value of RL is determined by the output and input leakage current which must be supplied to hold the output at VOH'

TABLE I - TRUTH TABLE
INPUTS

OUTPUT

eS1
PIN 3

eS2
PIN 4

eS3
PIN 5

WE

DIN

DOUT

H
X
X
L
L
L

X
H
X
L
L
L

X
X
H
L
L
L

X
X

X
X
X

H
H
H

L
H
X

H
H

X
L
L
H

MODE
Not Selected
Not Selected
Not Selected
Write "0"
Write "1"
Read inverted data from
addressed location

DOUT

H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Don't Care (HIGH or LOWI

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
'Input Voltage (dc)
'Input Current (dc)
"Voltage Applied to Outputs (output HIGH)
Output Current (dc) (output LOW)

-65°C to +150 0 C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.50 V
+20 mA

*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (Vee)

PART NUMBER

AMBIENT TEMPERATURE
Note 4

MIN

TYP

MAX

93411Axe, 93411Xe

4.75 V

5.0V

5.25 V

oDe to +75°e

93411XM

4.50 V

5.0V

5.50 V

-55°C to +125°e

x

= package type;

F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-59

•

FAIRCHILD ISO PLANAR TTL MEMORY • 93411/93411A
DC CHARACTERISTICS' Over Operating Temperature Ranges Notes 1 2 and 4
SYMBOL

PARAMETER

MIN

LIMITS
TYP
(Note 3)

MAX

0.3

0.45

UNITS

CONDITIONS

V

VCC = MIN, IOL = 16 rnA

V

Guaranteed Input Logical HIGH
Voltage for all Inputs
Guaranteed Input Logical LOW
Voltage for all Inputs

VOL

Output LOW Voltage

V,H

Input HIGH Voltage

V,L

Input LOW Voltage

1.5

0.85

V

I,L

Input LOW Current

-530

-800

pA

VCC= MAX, Y,N =OV

I'H

Input HIGH Current

1.0

20

pA

VCC = MAX, Y,N = 4.5 V

'CEX

Output Leakage Current

1.0

50

pA

VCC = MAX, VO UT = 4.5 V

VCD

Input Clamp Diode Voltage

-1.0

-1.5

V

90
100
90
100

124
135
117
143

Power Supply
Current

ICC

2.0

93411XC
93411AXC
93411XM

1.6

VCC = MAX, "N = -10 rnA
TA =+75°C
TA - O°C
TA +125°C
55°C
TA

rnA

VCC = MAX, WE
Grounded, all other inputs
@ 4.5 V, see Power Supply
vs Temp. Curve

AC CHARACTERISTICS' Over Guaranteed Operating Ranges Notes 1 2 4 5 6
SYMBOL

CHARACTERISTIC

READ MODE
tACS
tRCS
tAA

DELAY TIMES
Chip Select Time
Chip Select Recovery Time
Address Access Time

WRITE MODE
tws
tWR

tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

DELAY TIMES
Write Disable Time
Write Recovery Time
INPUT TIMING
REQUIREMENTS
Write Pulse Width
(to guarantee write)
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

C,
Co

Input Lead Capacitance
Output Lead CapaCitance

tw

93411AXC
MIN TYP MAX
(Note
3)
25
25

10

40

30
25
45

20
25

40

35

MIN

93411XC
TYP MAX
(Note
3)
25
25
45

30
25
55

10

20
25

35
40

93411XM
MIN TYP MAX
(Note
3)
25
25
45

40

10

20
25

45
50

40

25

40

25

50

25

0
5
0
5
0
5

0
0
0
0
0
0

0
5
0
5
0
5

0
0
0
0
0
0

0
5
.0
5
0
5

0
0
0
0
0
0

4
7

5
8

4
7

4
8

4
7

35
65

UNITS CONDITIONS

ns

See Test Circuit
and Waveforms
Note 5

ns

See Test Circuit
and Waveforms
Note 6
ns

5
8

pF

Measured with
pulse technique

NOTES:
1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represents the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes. additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at V CC = 5.0 V, TA = +25°C, and MAX loading.
.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical
thermal resistance values of the ·package at maximum temperature are:
8JA (Junction to Ambient) (at 400 fpm air flow) = 50°C/Watt, Ceramic DIP; 65°C/Watt, Plastic DIP; NA. Flatpak.
8JA (Junction to Ambient) (still air) = 90°C/Watt, Ceramic OIP; 110°C/Watt, Plastic DIP; NA. Flatpak.
8JC (Junction to Case) = 25°C/Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 100 C!Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at tWSA = MIN, tWSA measured at tw = MIN.

7-60

FAIRCHILD ISO PLANAR TTL MEMORY. 93411/93411A
AC TEST LOAD AND WAVEFORM
LOADING CONDITION

INPUT PULSES

Vee

ALL INPUT PULSES

T~

--1- -------------~ ---

-90

~~

30Dn

-

- - -

- - - - -

- -

-- - -

BOOH

-- -10'\,

I~------------

n--------- -1-I

1

I

GNO

93411/93411A

~-\-

30pF

35j ?P _

(CAPACITANCE
INCLUDING SCOPE
AND JIG)

I - - IOns

___ I

---

~ __ _
I

_ _ _ _ _ _ _ _ _ _ _ _

I

-..

_

I

-10%

~ ___ 90%
I

, ,
----t

. - - IOns

~10ns

AC WAVEFORMS
READ MODE
PROPAGATION DELAY FROM CHIP SELECT
"Csl

Cs2

PROPAGATION DELAY FROM ADDRESS

!

Cs3

CHIP SELECT

ADDRE_"_ _ _- - '

,
,

r

I
I

,
,,

Dour
DATA OUTPUT

X

AOloA7

,I

OOUT

I

' -___________________________

X

:

-r:______________--' : '-_________

DATAO_U_TP_U_T______

,

,

:

,

I
I--tRCS-------.I
,
I

:----tAA------~:

(ALL TIME MEASUREMENTS REFERENCED TO 1.5 V)
WRITE MODE

CHIP SELECT

\ " - - - - - - -_
I
I

AO toA7
ADDRESS

x
,
,
I

D,N

DATA IN

!

,I

~

_

X

I

I
I

I

I

I
I

I

I

:

:--t

11
'-------tw - - - - - - - I
I
I
I
I
WSD ---:

I-----IWSA - - - - - - ,
I

I

DOUT

I

I

,

11-·~------twscS-----~·""'

DATA OUTPUT

~------~-

:
X~------------------~x~------T:---------r--­

I

I

I

I

WE

,

_- - - J

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ J

WRITE ENABLE.

,

_

:

I

I

__________________________________~: _____J

:

I
I
r-tWS-J

I

I

I
I

I

,

: - - tWHO --:

:

,

r~----IWHA--'
10;

I
I
I
I
I

,
I

,

tWHCS

\
I

r---tWR~

I

(ALL TIME MEASUREMENTS REFERENCED TO 1.5 V)
NOTE: Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-61

FAIRCHILD ISO PLANAR TTL MEMORY • 93411/93411A
TYPICAL ELECTRICAL CHARACTERISTICS
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH)
1.0

0.5

VCC=5.0V

"

TA"125C~

~

E

If v

35

;L;d~

vcc=ls.0V

E
I

I

i

-0.5

0
I

I"

~J'TA'-55 c

"

-1.0

t'TA ~r5~C

t;

"

'?

)

'?

-1.5

J

-20
-1.0

1,0

2.0

3.0

4.0

50

0.1

6,C

110

~

95

~

~I
""

90

0.3

0.4

0.5

0.6

2.0

1-

1-

~

;1

0.2

"

........

~c

r-..

4.5V

">=
~

"
~

~

£

N

:;

20

60

'"

Dour +-

!:1

Vee = S.ov

o
140

100

-

"~

......

r-......

0

.7

../ f"""

V

'"

~

DdUT)

-

1.0

0

.......

85

-

~

= 5.5 V

" """"I. . . .

"-

-20

.-

~

'"

",vee
~KT

I-,/

80
-60

0.7

NORMALIZED
ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE

105

100

W

POWER SUPPLY CURRENT
VERSUS TEMPERATURE

I

13

TA'" _55°e

Your - OUTPUT VOLTAGE - VOLTS

E

~

V'

Your - OUTPUT VOLTAGE - VOLTS

115

"

r-TA''''S''C~ /

15

~

'(1/

I

-

0
I

I,~TA - 25'C

~

20

~

'I

~

"t;

If

;} '/

TA'1,.··c

~

o

50

100

200

150

LOAD CAPACITANCE - pF
TA - AMBIENT TEMPERATURE _ °C

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS SUPPLY VOLTAGE

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE
0.5

~

E
I

--0.5

~

~

13

-1.0

T A '" 55'C
T A = +25'C
TA = +125'C

l"

~

~

-1.5

/'

0.5

VCC-4.5~~

~

VCC=5.0V

"
E
I

-0.5

~

-1.0

:;:

-1.5

r

"ri<"

~TA=+125'JC

~~A=+25°C

T A'" _55°C

~

r

~C'45!

Vee'" 5.5 V

Vee = 5.0 V
"vee"" 5.5 V

I

z

~
-20

-2.0
TA "'j25°C

VCCj5.0V
-2.5
-1.0

1.0

3.0

5.0

7.0

9.0

-2.5
-1.0

11

1.0

3.0

5.0

7.0

9.0

VIN -INPUT VOLTAGE - VOLTS

VIN -INPUT VOLTAGE - VOLTS

7-62

11

FAIRCHILD ISO PLANAR TTL MEMORY • 93411j93411A
APPLICATIONS
STROBE OUTPUT LATCH
WE

'CO

BOARD ENABLE

DD

F
WE

STROBE INPUT LATCH

9308

9308
4BIT LATCH 2

25681T

READ/WRITE

00 01 02 03

J

L

MEMORY

00 01 02 03

M'

D'

'(

I

I

D3

93411/9J411A

WE

MR

DO 01 D2

DO

4 BIT LATCH 2

M'

p)

r-

",
~

02 03

DO 01

MEMORY
D'

~ Tori' T
E

93411/93411A
256 BIT
READIWRITE

DO! oL

!

101 too

DO

F

93411/9311A

WE

.r. lIn
E

00

01 02 03
9308

"'

I

.r;

!

",
~

E

DO

00-01 02 03

93411/93411A
256 BIT

9308

READ/WRITE

4 BIT LATCH:2

4 BIT LATCH 1

MEMORY

WE
M'

00 01

02 Q3

D'

00 Ql 02 03

M'

I
,

at 6~5lo4

1

66 7

6

DO

~

93411/93411A
256 BIT
REAO/WRITE

WE

MEMORY

MOD 256 ADDRESS COUNTER

D'

iAArTI'At

!

PO

DO

~

-

93411/93411A

WE

25681T
READ/WRITE
MEMORY

0'

-

CP-

CEP

PI P2 P3

9316 UP

DECADE

CEO

•

ep
MR 00 01 02 03

Mi

'( I I I I

J,

ADDRESSTOALL

93411

DO

-fW

9341lf9311A
256 BIT
READ/WRITE

MEMORY

WE
D'

A(ArAiT

),
'"
~

PE PO PI

DD
93411193411A

256·81T
WE

AEADfWRITE
MEMORY

"-

-

'-----

eEP

P2

P3

9316 UP
DECADE
COUNTER

eET
ep

MR 00 01 02 03

D'

I
ADDRESS TO ALL
93411

256-WORD BY 8-81T BUFFER MEMORY SYSTEM

7-63

Te

TTL ISOPLANAR MEMORY 93L412
256x4-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93L412 is a 1024-bit Read/Write Random Access Memory organized 256 words by four bits per word. The 93L412 has uncommitted collector outputs and is designed primarily for buffer control storage and high-performance main
memory applications. the device has a typical address access time of 45 ns.

•
•
•
•
•
•
•

ISOPLANAR TECHNOLOGY
ORGANIZATION - 256 WORDS X 4 BITS
UNCOMMITTED COLLECTOR OUTPUTS
STANDARD 22-PIN DUAL IN-LINE PACKAGE
TWO CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
LOW POWER DISSIPATION - 0.27 mW/BIT TYP
TYPICAL READ ACCESS TIME - 45 ns

LOGIC SYMBOL

(4)4

Ao

(3)3
(2) 2

.,

0) 1

Ao

(23) 21

A,

A,

931412

5

A,

(S) 6

.,

(5)

(7) 7

A.

1810121416
(20) (10) (14J(16H18)

Vee ~ Pin 22 (24)
GND ~ Pin 8
1 I ~ FLATPAK

PIN NAMES
AO-A7

CONNECTION DIAGRAMS
DIP (TOP VIEW)

Address Inputs

D1 - D4

Data Inputs

CS1' CS2
WE

Chip Select Inputs
Write Enable Input

we

01 - 04

Data Outputs

Csl

OE

Output Enable

'cc
A,

Dc
A6

A,

LOGIC DIAGRAM

cs,
0,

0,
0,
@
@
@

0,

0,

0,

0,

0,

@

FLATPAK (TOP VIEW)

A,A, ~~~~~~ur~~~~~'cc
WE

"OW
SELECT

A2

A4

AO

CS,

A,

A,
A7

vee
GNO

~
~

D4

D,

03

O'~~~D'
02

Pin 22

02

NC

Pin 8

0-= Pin Number

o.

GND

Pin numbers specified

000

for DIP only.

7-64

FAIRCHILD ISOPLANAR TTL MEMORY. 93L412
FUNCTIONAL DESCRIPTION-The 93L412 is fully decoded 1024-bit Random Access Memory organized 256 words
by four bits. Word selection is achieved by means of an a-bit address, Aothrough A7.
Two Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select, CS, from the address without increasing address access time.
The 93L412 has uncommitted collector outputs to allow maximum flexibility in output connection. In many applications,
such as memory expansion, the outputs of several 93L412s can be tied together. In other applications the wired-OR is not
used. In either case an external pull-up resistor of value RL must be used to provide a HIGH at the output when it is off.
Any value of RL within the range specified below may be used.

VCC(MIN) - VOH

VCC(MAX)
a - F.O. (1.6)

RL is in kO
N = number of wired-OR outputs tied together
F.O. = number of TTL Unit Loads (U.L.) driven
ICEX = Memory Output Leakage Current in mA
VOH = Required Output HIGH level at Output Node

,;;; RL';;;

N (ICEX) + F.O. (0.04)

The minimum value of RL is limited by output current sinking ability. The maximum value of RL is determined by the output and input leakage current which must be supplied to hold the output at VOH'

TRUTH TABLE
OUTPUTS

INPUTS
OE
PIN 18

CS1
PIN 19

CS2
PIN 17

WE
PIN 20

01- 04
PINS 9.11.13,15

OPEN
COLLECTOR

X
X
L
X
X

H

X
L

X
X

H
H

H
H

H

X
X
X
L

H

L
L
L

X
L
L
L

H
H

H

L
L

H

H

H

L
L

H

01 - 04
H
H

H

X
L
H

H ~ HIGH Voltage; L ~ LOW Voltage; X ~ Don't Care (HIGH or
NOTE: Pin number specified are for DIP only

H
H
H

MODE

Not Selected
Not Selected
Read Stored Data
Write"O"
Write "1"
Output Disabled
Write "0" (Output Disabled)
Write "1" (Output Disabled)

LOW)

ABSOLUTE MAXIMUM RATINGS,(above whieh the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Lead Potential to Ground Lead
Input Voltage (de)'
Input Current (de)'
Voltage Applied to Outputs (output HIGH)"
Output Current (de)

-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.50 V
+20mA

*Either Input Voltage limit or Input Current limIt IS sufficient to protect the inputs.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (VCC)

PART NUMBER

AMBIENT TEMPERATURE
Note 4

MIN

TYP

MAX

93L412XC

4.75 V

5.0V

5.25 V

OoC to +75°C

93L412XM

4.50 V

5.0V

5.50 V

-55°C to +125°C

X

= package type;

F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-65

•

FAIRCHILD ISOPLANAR TTL MEMORY -93L412
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1. 2, 4)
SYMBOL

LIMITS

CHARACTERISTIC
MIN

MAX

0.3

0.45

VOL

Output LOW Voltage

V,H

Input HIGH Voltage

V ,L

Input LOW Voltage

1.5

',L

Input LOW Current

2.1

"H

Input HIGH Current

VCD

Input Diode Clamp Voltage

CEX

Output Leakage
Current

'

Power Supply
Current

CONDITIONS

V

VCC = MIN, IOL = 8 mA

V

Guaranteed Input HIGH Voltage
for a II Inputs

0.8

V

Guaranteed Input LOW Voltage
for all Inputs

-150

-300

IlA

VCC = MAX, V,N = 0.4 V

1.0

40

IlA

VCC = MAX, V ,N = 4.5 V

1.0

mA

VCC = MAX, V ,N = 5.25 V
VCC = MAX, "N = -10 mA

1.6

--1.0

-1.5

V

1.0

100

IlA

55

75

TA

60

80

TA = O°C

All Inputs and

93L412XM

50

70

TA = +125°C

Outputs Open

93L412XM

65

90

TA = --55°C

93L412XC
ICC

UNITS

TYP
(Note 3)

93L412XC

VCC = MAX, VO UT = 4.5 V
+75°C

VCC

mA

MAX,

AC CHARACTERISTICS: Over Guaranteed Operating Ranges (Notes 1, 2, 4, 5, 6)
93L412XC
SYMBOL

CHARACTERISTIC

MIN

TYP

93L412XM
MAX MIN

(Note 3)

TYP

MAX

UNITS

CONDITIONS

(Note 3)

READ MODE

DELAY TIMES

tACS
tRCS

Chip Select Time
Chip Select Recovery Time

20
20

35
35

20
20

45
45

tAOS
tROS

Output Enable Time
Output Enable Recovery Time

20
20

35
35

20
20

45
45

45

60

45

75

20
25

45
50

tAA

Address Access Time

WRITE MODE

DELAY TIMES

tws

Write Disable Time

20

40

tWR

Write Recovery Time

25

45

ns

See Test Circuit
and Waveforms

ns

INPUT TIMING REQUIREMENTS
tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

Write Pulse Width (to guarantee write)
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

C,

Input Pin Capacitance
Output Pin Capacitance

Co

45
5
5
10
5
5
5

30
0
0
0
0
0
0
3
5

7-66

55
5
5
10
10
5
10
5
8

See Test Circuit
and Waveforms

35
0
0
0
0
0
0
3
5

ns

5
8

pF

Measure with
Pulse Technique

FAIRCHILD ISOPLANAR TTL MEMORY. 93L412
NOTES:
1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "WOfst case" conditions.
2. The specified LIMITS represent the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at Vcc = 5.0V, TA =+25'C, and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range there is an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at maximum termperature are:
6JA (Junction to Ambient) (at 400 fpm air flow) = 50' C/Watt, Ceramic DIP; 65' C/Watt, Plastic DIP; NA. Flatpak.
6JA (Junction to Ambient) (still air) = 90' C/Watt, Ceramic DIP; 110' C/Watt, Plastic DIP; NA, Flatpak.
6JC (Junction to Case) = 25'C/Watt, Ceramic OIP; 25'C/Watt, Plastic DIP; 15'C/Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at tWSA = MIN, tWSA measured at tw = MIN.

TYPICAL ELECTRICAL CHARACTERISTIC CURVES
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH)

,

I
§

TA - -!)!) C
TA -+,25 C

TA

~

+12!) C

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

.

///

Vcc·s.OV

"

POWER SUPPLY CURRENT
VERSUS TEMPERATURE

-

-

-

TA-+12!) C

TA.JS

c

j

'I;

'/

~
}I(

J

f/

0.2

~

~

6

B

60

~

~
TA=I- 6Ei ' C

70

C

~

-

'r--

,, f--'-.
,

VCC

4

,

1l

....... -=::;;:

-....;::

,
0

0.3

VOUT - OUTPUT VOLTAGE - VOLTS

TA - AMBIENT TEMPERATURE -'C

ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE
VCC-5.0V

tt

90

~

:

•

50

i

-

VCC m5•SV

...... ~tcc-S.OV_
.......

/'I-4. SV

50

or- rr- r- i
~

-- ---<

~

/

0

~

~~~ ~

0

1/

)/"

-0.5

f-,#+--+---r-f----I--+--l

"

B -l.oHIII"<+--+---r-f----I--+--l
~

V-

i'
z

V-

J~

-1.5

k-

II"

TA-+125"C
TA-J5"C

I

-+--+-+--1

TA--5S'C

i .....
20

o

_2.5WL_.l.-_L-~L----'_-'-_....J
_1.0
1.0
~O
~O

100200 300400 500 600 100 800 900 1000

VIN - INPUT VOLTAGE - VOLTS

LOAD CAPACITANCE _ pF

7-67

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93L412
AC TEST LOAD AND WAVEFORM
LOADING CONDITIONS

INPUT PULSES

Vee

-4-

~

(

r - -- _- - --- --- . -

I.

3.5 V pop

t -

6000

GNO

°OUT
93412
93L412

15 pF

12000

-'0:--

ALL INPUT PULSES

1 . .

'I - - - - - - - - 1
1_10 ns
_I

_I

-

90%

10%

1 _ 10 n.

t _~-nnn-ff'~
I
I

3.5 V pop

t

-

-I

--------

,-90%

_I

Load A

l-l0ns

WRITE MODE

CSl.

es

2

CHIP SELECT

/

/\

/\

AO-A7
ADDRESS

/\

/\

101 - 041
DATA IN

/ f\

/\

I-'w-I

WE
WRITE ENABLE

'WSO-

.

twscs

-- \

--'WHO

-4--tWSA-""

-~

.

I

......-- tWHA-----'

.wsl-

LOAD A

tWHCS

~

I

-,wR--1

101 -041
DATA 0 UTPUT

READ MODE
PROPAGATION DELAY
FROM CHIP SELECT

PROPAGATION DELAY
FROM OUTPUT ENABLE

OE=:=\

.r-

l'

O~!:~~~

::::~I ~
°1- 0 4

LOAD A

I

AO-A7

_A_DD_R_E_SS__

V

~~~_____________

I+: 'RDS

DA~AII
1/

OUTPUTS

PROPAGATION DELAY
FROM ADDRESS INPUTS

DATA

-'AAj-r---

OUTPUTS

01 - 04
1

LOAD A

(All above measurements referenced to 1.5 V unless otherwise indicated)
NOTE: Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-68

TTL ISO PLANAR MEMORY93412
256

x 4 - BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93412 is a 1024-bit Read/Write Random Access Memory organized 256 words by four bits per word. The 93412 has uncommitted collector outputs and is designed primarily for buffer control storage and high-performance main
memory applications. The device has a typical address access time of 30 ns.

LOGIC SYMBOL

(4)4

40

(3)3

•
•
•
•
•
•
•

(2)2

ISOPLANAR TECHNOLOGY
ORGANIZATION - 256 WORDS x 4 BITS
UNCOMMITTED COLLECTOR OUTPUTS
STANDARD 22-PIN DUALIN-LiNE PACKAGE
TWO CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
POWER DISSIPATION - 0.475 mW/BITTYPICAL
TYPICAL READ ACCESS TIME - 30 ns

PIN NAMES
AO-A7
D1 - D4
CS1, CS2
WE

01 - 04
OE

1111
(23)21
(5)

CD
CD

@

(7) 7

18 10 12 14 16
120) (10) (141116)(16)

Vee ~ Pin 221241
GND ~ Pin 8
1 1 ~ FLATPAK

Address Inputs
Data Inputs
Chip Select Inputs
Write Enable Input
Data Outputs
Output Enable

CONNECTION DIAGRAMS
DIP (TOP VIEW)

AO
0,

A,
A2
A3

ROW
SELECT

32 x 32
MEMORY
ARRAY

OUTPUT
DATA
CONTROL

02
03

@
@

Pin 22
Pin 8

CS,

A,

OE

Ao

eS2

A7

0,

GNO

a,

0,

03

0,

03

02

02

•

®®0

Pin numbers specified
for DIP only

= Pin Number

7-69

A4

WE

AO

ESt
BE

~

~

WE

A1

A6

~

A,
AO

A3~~~~~~0Cl~~~~~~vee
A7
GND

o

Vee
A,

FLATPAK (TOP VIEW)

8

AS

GND

A3
A,

a' @

A,

AZ

vee

93412

A;

(6) 6

LOGIC DIAGRAM

(4)
(5)

'"
.,

A,

5

CS2

04
D4
~

0,

03

D2

02

NC

NC

FAIRCHILD ISO PLANAR TTL MEMORY • 93412
FUNCTIONAL DESCRIPTION - The 93412 is a fully decoded 1024-bit Random Access Memory organized 256 words
by four bits. Word selection is achieved by means of an 8-bit address, AO through A7.
Two Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select, CS, from the address without increasing address access time.
The 93412 has uncommitted collector outputs to allow maximum flexibility in output connection. In many applications,
such as memory expansion, the outputs of several 93412s can be tied together. In other applications the wired-OR is not
used. In either case an external pull - up resistor of value RL must be used to provide a HIGH at the output when it is off.
Any value of RL within the range specified below may be used.

VCC(MAX)

VCC (MIN) - VOH

8 - F.O. (1.6)

N (lCEX) + F.O. (0.04)

RL is in kO
N = number or wired-OR outputs tied together
F.O. = number of TTL Unit Loads (U.L.) driven
ICEX = Memory Output Leakage Current in mA
VOH = Required Output HIGH level at Output Node

The minimum value of RL is limited by output current sinking ability. The maximum value of RL is determined by the output and input leakage current which must be supplied to hold the output at VOH.

TRUTH TABLE
INPUTS

OUTPUTS

01 - 04

OE
PIN 18

CS1
PIN 19

CS2
PIN 17

WE
PIN 20

01- 0 4
PINS 9, 11,13, 15

OPEN
COLLECTOR

X
X
L
X
X

H
X
L
L
L

X
L
H
H
H

X
X
H
L
L

X
X
X
L
H

H
H
01 - 04
H
H

H
H
H

L
L
L

H
H
H

H
L
L

X
L
H

H
H
H

H

~

HIGH Voltage, L

~

LOW Voltage, X

~

MODE

Not Selected
Not Selected
Read Stored Data
Write "0"
Write "1"
Output Disabled
Write "0" (Output Disabled)
Write" 1" (Output Disabled)

Don't Care (HIGH or LOW)

NOTE: Pin number specified are for DIP only

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
*Input Voltage (de)
*Input Current (de)
**Voltage Applied to Outputs (output HIGH)
Output Current (de)

-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5,5 V
-12 mA to +5.0 mA
0.5 V to +5.50 V
+20 mA

*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES

MIN

SUPPLY VOLTAGE (VCCl
TYP

MAX

93412XC

4.75 V

5.0V

5.25 V

93412XM

4.5

5,OV

5.5

PART NUMBER

x=

V

V

AMBIENT TEMPERATURE
Note 4
O°C to +75°C
-55°C to +125°C

package type; F for FJatpak, D for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-70

FAIRCHILD ISO PLANAR TTL MEMORY • 93412
DC CHARACTERISTICS' Over Operating Temperature Ranges (Notes 1 2, 4)
SYMBOL

LIMITS

CHARACTERISTIC
MIN

MAX

0.3

0.45

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

IlL

Input LOW Current

2.1

IIH

Input HIGH Current

V CD

Input Diode Clamp Voltage

ICEX

Output Leakage
Current

ICC

Power Supply
Current

UNITS

TYP
(Note 3)

V

VCC - MIN, IOL - 8 mA

V

Guaranteed Input HIGH Voltage
for all Inputs

0.8

V

Guaranteed Input LOW Voltage
for all Inputs

-150

-300

/lA

VCC = MAX, \fIN = 0.4 V

1.0

40

/lA

VCC - MAX, VIN - 4.5 V

1.0

mA

VCC = MAX, VIN = 5.25 V

1.6

93412XC

CONDITIONS

-1.0

-1.5

V

VCC -MAX,IIN=-10mA

1.0

100

/lA

VCC = MAX, VOUT = 4.5 V

95

130

TA = +75°C

V CC - MAX,

93412XC

155

TA = O°C

All Inputs and

93412XM

120

TA = +125°C

Outputs Open

93412XM

170

mA
TA = -55°C

AC CHARACTERISTICS; Over Guaranteed Operating Ranges (Notes 1, 2, 4, 5, 6)
93412XC
SYMBOL

CHARACTERISTIC

MIN

93412XM

TYP
MAX MIN
(Note 3)

TYP
MAX
(Note 3)

READ MODE

DELAY TIMES

tACS
tRCS

Chip Select Time
Chip Select Recovery Time

20
20

30
30

20
20

45
45

tAOS
tROS
tAA

Output Enable Time
Output Enable Recovery Time
Address Access Time

20
20
30

30
30
45

20
20

40

45
45
60

WRITE MODE

DELAY TIMES

tws

Write Disable Time

20

35

20

45

tWR

Write Recovery Time

25

40

25

50

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

Write Pulse Width (to guarantee wnte)
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

CI
Co

Input Pin Capacitance
Output Pin Capacitance

UNITS

ns

CONDITIONS

See Test Circuit
and Waveforms

ns
INPUT TIMING REOUIREMENTS
30
5
5
10
5
5
5

40
5
5
10
10
5
10

20
0
0
0
0
0
0
3
5

5
8

See Test Circuit
and Waveforms

30
0
0
0
0
0
0
3
5

ns

5
8

pF

Measure with
Pulse Technique

NOTES:
1. Conditions for testing. not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represent the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and sup~
ply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at Vcc = 5.0 V, TA = +25'C. and MAX loading.
4. The Temperature Ranges are guaranteed with transverse ~ir flow exceeding 400 linear feet per minute. For military range there is an additional requirement
of a two minute warm - up. Temperature range of operation refers to a case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at maximum temperature are:

8JA(Junction to Ambient) (at 400 fpm air flow) = 50'C/Watt, Ceramic DIP; 65'C/Watt, Plastic OIP; NA, Flatpak.
8JA (Junction to Ambient) (still air) = 90'CIWatt, Ceramic DIP; 110' C/Watt, Plastic DIP; NA, Flatpak.
8JC (Junction to Case)= 25'C/Watt, Ceramic OIP; 25'C/Watt, Plastic DIP; 1O'C/Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw mtJasured at tWSA = MIN, tWSA measured at tw = MIN.

7-71

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93412
TYPICAL ELECTRICAL CHARACTERISTIC CURVES

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH)
1.0

L50 J

Vcc
~

TA

..iii
I

0

TA

55°C

=+12S o C

gj

0

a;
a;

::>

~ -0.5
::>

§

..

=125 c

lTA -

0.5

-1.0

::>
9-1.5

H

~ TA ~ -55'C
.~

~

TA =+25°C

I

TAT

25

'1

-2.0
1.0

0

1.0

2.0

3.0

4.0

5.0

6.0

VOUT - OUTPUT VOLTAGE -- VOLTS

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

POWER SUPPLY CURRENT
VERSUS TEMPERATURE
150

21;---;--'---'--~---r~-r--,

<



~

70

.o
.

~

::>

a;

52

90

50
-50 -25

VOUT - OUTPUT VOLTAGE - VOLTS

0.5
Vcc

110

lU 100

:;;
;::

90

::J'"U

80

<

70

::J'"a:

60

U

""<
<

It
r- f

-

50

75

100

125

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE

120

I

25

TA - AMBIENT TEMPERATURE - °C

ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE
~

.............

~ 60
0.7

:5

----.:::-

Vee = 5.5 V

--<.

<

E

~ -0.5

/

iiia;

TA~--550g~

J5.0 V

"

TA =+25°C

/'

TA -+L5 O C/

~ -1.0
U

J

5

~ --1.5

/

50

z

= -2.0

40

~

TA """+125°C

I

f--- TA =+25°C

~

I
TA-"- -55°C

30
20

-2.5

o

-1.0

100 200300 400 500 600700 800900 1000
LOAD CAPACITANCE

1.0

3.0

5.0

7.0

VIN - INPUT VOLTAGE

pF

AC Test Load and Waveforms same as 93L412, see page 7-68.

7-72

9.0

VOLTS

11.0

TTL ISOPLANAR MEMORY 93L415
l024xl-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The93L415 is a low power 1024-bit Read/Write Random Access Memory organized
1024 words by one bit. It has a typical access time of 35n5 and is designed for buffer and control
storage and high-performance main memory applications requiring low power.

LOGIC SYMBOL
15

14

The 93L415 includes full decoding on chip. has separate Data Input and Data Output lines and an
active LOW Chip Select line.
The device is fully compatible with the standard OTL and TTL logic families an9 has an uncommitted
collector output for ease of memory expansion.

A,
4

5

•
•
•
•
•
•
•
•
•

FULL MIL AND COMMERCIAL RANGES
TTL INPUTS AND OUTPUT
NON-INVERTING DATA OUTPUT
ORGANIZED 1024 WORDS X 1 BIT
READ ACCESS TIME 35 ns TYPICAL
CHIP SELECT ACCESS TIME 20 ns TYPICAL
POWER DISSIPATION 0.20 mW/BIT TYPICAL
UNCOMMITTED COLLECTOR OUTPUT
POWER DISSIPATION DECREASES WITH INCREASING TEMPERATURE

A2
A3
A4

93L415

A5

10

A6

11

A7

12

AS

13

Ag

DOUT

Vee = Pin 16
GND=Pin8

PIN NAMES
CS
AO- A9

WE

DIN
DOUT

Chip Select Input
Address Inputs
Write Enable Input
Data Input
Data Output

CONNECTION DIAGRAMS
DIP (TOP VIEW)

LOGIC DIAGRAM

cs

vee

Ao

DIN

A,

WE

A,

Ag

A3

A8

WOAO
DRIVERS

Vee=Pin16
AS

As

A]

AS

GND=Pin8

Ag

0= Pin
7-73

Numbers

A.

A)

DOUT

A6

GND

A5

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line "'ackage.

•

FAIRCHILD ISOPLANAR TTL MEMORY • 93L415
FUNCTIONAL DESCRIPTION - The 93L415 is a fully decoded 1024-bit Random Access Memory organized 1024 words by one bit. Bit
selection is achieved by means of a 10-bit address, AO through A9.
The Chip Select input allows memory array expansion. For large memories, the fast chip select access time permits decoding of the Chip Select
ICSI from the address without affecting system performance.
The read and write operations are controlled by the state of the active LOW Write Enable IWE, Pin 141. With WE held LOW and the chip
selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected. Data in the specified location
is presented at DOUT and is non-inverted.
Uncommitted collector outputs are provided on the 93L415 to allow maximum flexibility in output connection. In many applications such as

memory expansion, the outputs of many 93L415s can be tied together. In other applications the wired-OR is not used. In either case an
external pull-up resistor of RL value must be used to provide a HIGH at the output when it is off. Any RL value within the range specified
below may be used.

VCC Iminl

VCC Iminl - VOH

RL is in kf2

n = number of wired-OR outputs tied together

IOL - Fa 11.61 <; RL <; n IiCEXI + Fa 10.041

FO = number of TTL Unit Loads (UL) driven

=

'CEX
Memory Output Leakage Current
VOH = Required Output HIGH Level at Output Node

IOL = Output LOW Current
The minimum RL value is limited by output current sinking ability. The maximum RL value is determined by the output and input leakage

current which must be supplied to hold the output at VOH. One Unit Load = 40 itA HIGH/1.6 mA LOW.

TABLE I - TRUTH TABLE
OUTPUT

INPUTS

MODE

CS

WE

DIN

Open
Collector

H

X

X

H

NOT SELECTED

L
L

L

H
H

WRITE "0"
WRITE "1"

L

H

L
H
X

DOUT

READ

H
L
X

L

HIGH Voltage Level

LOW Voltage Level
Don't Care (HIGH or LOW)

ABSOLUTE MAXIMUM RATINGS Iabove which the useful life may be impairedl
Storage Temperature
Temperature IAmbientl. Under Bias
VCC Pin Potential to Ground Pin
"Input Voltage Idcl
"Input Current Idcl
Voltage Applied to Outputs IOutput HIGHI
Output Current Idcl IOutput LOWI

-65°C to +150 0 C
-55°C to +125 0 C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.5 V
+20 mA

* Either input voltage or input current limit is sufficient to protect the input.

GUARANTEED OPERATING RANGES
PART NUMBER
93L415XC
93L415XM

MIN
4.75 V
4.50 V

SUPPLY VOLTAGE IVCCI
TYP
5.0V
5.0 V

MAX

AMBIENT TEMPERATURE
INote 41

5.25 V

OoC to +75 0 C

5.50 V

-55°C to +125 0 C

X = package type; F for Flatpak, D for Ceramic DIP, P for Plastic DIP. See Packaging Information Section for packages available on this product.

7-74

FAIRCHILD ISOPLANAR TTL MEMORY • 93L415
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1, 2,4)
LIMITS
SYMBOL

CHARACTERISTIC

TYP
(Note 3)

MIN

MAX

V

VCC

= MIN, IOL = 16 mA

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

0.8

IlL

Input LOW Current

-150

-300

MA

VCC

1.0

40

MA

Vce

1.0

mA

VCC - MAX, VIN - 5.25 V

1.0

100

MA

VCC

-1.0

-1.5

V

IIH

Input HIGH Current

ICEX

Output Leakage Current

VCD

Input Diode Clamp Voltage

ICC

Power Supply Current

0.45

CONDITIONS

UNITS

0.35

V

1.6

2.1

45

V

Guaranteed Input HIGH Voltage
for all Inputs
Guaranteed Input LOW Voltage
for all Inputs

= MAX, VIN = 0.4 V
= MAX, VIN - 4.5 V
= MAX, VOUT - 4.5 V
= -10 mA

VCC = MAX, liN

55

mA

T A ;;, 75°C

65

mA

TA

75

mA

MAX

UNITS

CONDITIONS

ns

See Test Circuit and Waveforms

= O°C
TA = -55 0 C

VCC = MAX,
All Inputs
Grounded

AC CHARACTERISTICS: Over Guaranteed Operating Ranges (Notes 1, 2,4,5,6)
93L415XC
SYMBOL

CHARACTERISTIC

MIN

TYP

93L415XM
MAX. MIN

(Note 3)

TYP
(Note 3)

READ MODE

DELAY TIMES

tACS

Chip Select Time

20

40

20

45

tRCS

Chip Select Recovery Time

20

40

20

50

tAA
WRITE MODE

Address Access Time

35

60

35

70

tws

Write Disable Time

20

45

20

45

tWR

Write Recovery Time

20

45

30

55

-

DELAY TIMES

INPUT TIMING
REQUIREMENTS
Write Pulse Width

tw

45

25

50

25

5

0

10

0
0

(to guarantee write)·
tWSD

Data Set-Up Time Prior to Write

ns

tWHD

Data Hold Time After Write

tWSA

Address Set-Up Time

tWHA

Address Hold Time

tWSCS
tWHCS
CI

Input Lead Capacitance

4

5

4

5

Co

Output Lead Capacitance

7

8

7

8

5

0

10

10

0

10

0

5

0

10

0

Chip Select Set-Up Time

5

0

10

0

Chip Select Hold Time

5

0

10

See Test Circuit and Waveforms

0
pF

NOTES:
1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.

2. The specified LIMITS represent the "worst case" value to the parameters. Since these "worst case" values normally occur at the temperature
and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical limits are at VCC = 5.0 V, TA = +25°C. and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range there is an addi~
tiona! requirement of two minute warm~up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature
for all other packages. Typical thermal resistance values of the package at maximum termperature are:
8 JA (Junction to Ambient) (at 40a fpm air flow) = 50°C/Watt. Ceramic DIP, 65°C/Watt, Plastic DIP; NA, Flatpak.
8 JA (Junction to Ambient) (still air) = 90°C/Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
(J JC(Junction to Case) = 25° C/Watt, Ceramic DIP; 25°C/Watt, Plastic D1 P; 1 aOC/Watt, F latpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at t WSA = MIN, t WSA measured at tw = MIN.

7-75

•

FAIRCHILD ISOPLANAR TTL MEMORY • 93L415
AC TEST LOAD AND WAVEFORM
LOADING CONDITION

INPUT PULSES
ALL INPUT PULSES

Vee

,,
,

300n

--------------

-----00%

,

---w%

-~--------------,-

Dour
GND '"::"

1~10ns

93415
93415A
93L415

600

3DpF

n

3.5 Vp.p -

lCAPACITANCE
INCLUDING SCOPE
AND JIG!

,

~ -- -

- -

-..j

- -

- - -

- - -

~10ns

-1---

- - -

10 %

-~~-------------~~---OO%

----,-

...L
GND

-=

I

I

I

I
~ 10

--.j

ns

I

I

I

I
~ 10

----.

ns

AC WAVEFORMS
READ MODE
PROPAGATION DELAY FROM CHIP SELECT

PROPAGATION DELAY FROM ADDRESS INPUTS

cs
CHIP SELECT
AO'" Ag
ADDRESS INPUTS

I
I
I

Dour

ir

\

DATA OUTPUT

,

I

,

I

cs

AO . ,A9
INPUTS

,

r

11-.~---tAA-----'

WRITE MODE
~____________________________________________________________J

,

----r-~x'---_----Jx'---__T___
,

X

D'N
DATA IN

____________

~--------~------J

WE

I
I

Xc--r------;......_

~--------------------~ I

,

WRITE ENABLE

I
I

------

I

~twSO-:

~twSA----'

rl··--------~-~S

~

x=

------------~----------------

I

\

~--------------------

DOUT

:_tRCS~:

,

CHIP SELECT

ADDRESS

,,

DATA OUTPUT

I

I

l_tACS_1
I

x

--------~

I

I
I
I

•'

DATA OUTPUT

I

---~:
I

I

..-- tws .......
I
I

~tWHD-:

I

r---twHA-------!

~

;.
I

I

twHCS------·~"
\

:'----I

. - - - tWR - - - ,
I

(ALL TIME MEASUREMENTS REFERENCED TO 1.5 V)
NOTE: Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-76

FAIRCHILD ISOPLANAR TTL MEMORY • 93L415
TYPICAL ELECTRICAL CHARACTERISTICS

10

0
0

OUTPUT CURRENT
VERSUS OUTPUT
VOLTAGE (OUTPUT HIGH)

OUTPUT CURRENT
VERSUS OUTPUT VOLTAGE
(LOW STATE)

POWER SUPPLY CURRENT
VERSUS TEMPERATURE

V~CJAX I

10

)50t-+-+++~'±~+--H

)

0.5 ~+-CC_'+1+--1++++T.::A+--_25+-'C-+t--+h<-l

ALL INPUTS GND

TA ,-55"C

~

r--..

.......

0

r--.

r--- t--..

~O, -10~+--f-+-++++-+---I--+-+-+

20

0

20

60

r--.

2

:~T_A_-~~12~5'L'C~~~~__~__~__L-~

100

0.1

140

T J - JUNCTION TEMPERATURE _ 0(;

INPUT CURRENT
VERSUS INPUT VOLTAGE
TA - S5°C TA - 2S"C
II
05r=+:~~~
T A '" 125°C

F"1'

3.

0

~

,2S"C

02

03

0.4

05

0,6

-,.5l1li-1---1---+-+-+-++++-+--+--+
-2~11L.oLo!---".L,o--",I,0,....,l3.0,-l4."'0. ,I5"'".0-',L,. 0"""L.o."""1,.0--'0J.,.,-,,J.o"'0-1'1.0

0.7

Your - OUTPUT VOLTAGE - VOLTS

Your - OUTPUT VOLTAGE - VOLTS

INPUT THRESHOLO
VOLTAGE VERSUS
TEMPERATURE

NORMALIZED ADDRESS
ACCESS TIME VERSUS
TEMPERATURE

I--JCC i

5•0

t

I---

5

~

vc~ = ~.oJ

5

I

%
I

i

~

TA

~

SLOPE = -0.195 mArC (2S"C - l00Q C}

60

I

T A "-55"C

~ -0.5 HIIj-C-Tf-A_"-,-12_5"..,.C-+-+----;f-I---'TAf-"_'+12_5"+"-+.J

0
o

hV.,

rJ, A

I

z

-0.5H1-+-+---+---++--++-+---I--+-+-+

a -1.0 fll-t--t--+-+-+++++-+-+--+

~~ -1.6l1li-+---+---+--++++-+---1--+-+-+

~

/

2. 0

./

~

~

1.

1--

5

......

I-f-

~ ,.0
~

~

,I

O.

"

5

0

-60

Y,N -INPUT VOLTAGE - VOLTS

-20

0

20

60

100

140

TJ - JUNCTION TEMPERATURE _

-40

160

-20

°c

0

20

.0

100

"0

TJ - JUNCTION TEMPERATURE - °C

APPLICATIONS
VCC

VCC

VCC

300n

1/29321
DECODER

00

00

2

•

00

A,ooA12
)
ADDRESSES
DATA IN
DATA OUT
WE

93L415
TO ALL
93L415s

00

00

93L415

00

00

93L4t5

DATA OUT

93L415

00

93L4t5

BITO

93L415

BITt -

-

-

-

-

-

-

-

-

-

BITlS

Addressing for a 4096~bit ~emory plane by 16 bits (4K x 16) requires only half of a 9321 1~of~4 decoder and any necessary buffers.

7-77

TTL'ISOPLANAR MEMORY 93415/93415A
I024xl-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93415 and 93415A are 1024-bit Read/Write Random Access Memories organized 1024 words by one bit. They are designed for buffer control storage and
high-performance main memory applications. The devices have typical access times of
30 ns for the 93415 and 25 ns for the 93415A.
The 93415 and 93415A include full decoding on chip, separate Data Input and Data Output lines and an active LOW Chip Select. They are fully compatible with standard DTL
and TTL logic families and have an uncommitted collector output for ease of memory
expansion.

LOGIC SYMBOL

15

14

A1
A2

•
•
•
•
•

•
•
•

UNCOMMITTED COLLECTOR OUTPUT
TTL INPUTS AND OUTPUT
NON-INVERTING DATA OUTPUT
ORGANIZED 1024 WORDS X 1 BIT
TYPICAL READ ACCESS TIME
93415A
Commercial
25ns
93415
Commercial
30 ns
93415
Military
40 ns
CHIP SELECT ACCESS TIME 15 ns TYPICAL
POWER DISSIPATION 0.5 mW/BIT TYPICAL
POWER DISSIPATION DECREASES WITH INCREASING TEMPERATURE

A3
A4
93415/93415A

A5

10

AS

11

A7

12

AS

13

A9

°OUT

PIN NAMES

cs

Vee = Pin 16
GND = Pin 8

Chip Select

AO-A9

Address Inputs

WE

Write Enable

DIN

Data Input

DOUT

Data Output

CONNECTION DIAGRAM
DIP(TOP VIEW}

LOGIC DIAGRAM

os

Vee

AO

D,N

A,

WE

A,

Ag

"

A3

AS

.'J

A4

A7

DOUT

A6

GND

A5

ADDRESS

DO

'cs

'"'
O'N

,.,
,.

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

Vcc = Pin 16
GND = Pin 8

o = Pin Numbers
7-78

FAIRCHILD ISOPLANAR TTL MEMORY • 93415/93415A
FUNCTIONAL DESCRIPTION - The 93415/93415A are fully decoded 1024-bit Random Access Memories organized 1024 words by one bit_
Bit selection is achieved by means of a 10-bit address, Aothrough A9-

The Chip Select input provides for memory array expansion. For large memories, the fast chip select access time permits the decoding of Chip
Select (C51 from the address without affecting system performance_
The read and write operations are controlled by the state of the active j,pW Write Enable (WE, Pin 141. With WE held LOW and the chip
selected, the data at DIN is written into the addressed location_ To read, WE is held HIGH and the chip selected. Data in the specified location

is presented at DOUT and is non-inverted.
Uncommitted collector outputs are provided to allow maximum flexibility in output connection. In many applications such as memory
expansion, the outputs of many 934155 or 93415As can be tied together. I n other applications the wired-OR is not used. 1n either case an
external pull-up resistor of RL value must be used to provide a HIGH at the output when it is off. Any RL value within the range specified
below may be used.

VCC (MINI

RL is in kn
n:= number of wired-OR outputs tied together
FQ
number of TTL Unit Loads (UL) driven

=

VCC (MINI- VOH
.; RL .;

IOL - FO (1.61

I CE X := Memory Output Leakage Current
VOH = Required Output HIGH Level at Output Node
10 L = Output LOW Current

n (lcExl + FO (0_041

The minimum RL value is limited by output current sinking ability. The maximum RL value is determined by the output and input leakage
current which must be supplied to hold the output at VOH. One Unit Load = 40 JlA HIGH/1.6 mA LOW.

TYPICAL INPUT AND OUTPUT CHARACTERISTICS
INPUT CURRENT
VERSUS INPUT VOLTAGE

TABLE I - TRUTH TABLE
INPUTS

OUTPUT

OUTPUT CURRENT
VERSUS OUTPUT VOLTAGE
(LOW STATE)

MODE

Open
Collector

CS

WE

DIN

H

X

X

H

NOT SELECTED

L

L

L

H

WRITE "0"

L

L

H

H

WRITE"1"

L

H

X

DOUT

READ

II

H = HIGH Voltage Level
L = LOW Voltage Level

X

=

Don't Car. (HIGH or LOW)
VIN' INPUT VOLTAGE -- VOLTS

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impairedl
Storage Temperature
Temperature (Ambientl Under Bias
V CC Pin Potential to Ground Pin
'Input Voltage (dcl
'Input Current (dcl
Voltage Applied to Outputs (Output HIGHI
Output Current (dcl (Output LOWI

VOUT -- OUTPUT VOLTAGE

VOLTS

_650 C to +1500 C

_55 0 C to +1250 C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.5 V
+20 mA

* Either input voltage or input current limit is sufficient to protect the input.

GUARANTEED OPERATING RANGES

PART NUMBER

AMBIENT TEMPERATURE (TAl

SUPPLY VOLTAGE (VCCI
MIN

TYP

MAX

93415XC, 93415AXC

4.75 V

5.0V

5.25 V

93415XM

4.50 V

5.0V

5.50 V

x

(Note 41

== package type; F for 'FlatPak, 0 for Ceramic DIP, P for Plastic DIP. See Packaging Information Section for packages available on this product.

7-79

•

FAIRCHILD ISOPLANAR TTL MEMORY • 93415/93415A
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1,2,4)
SYMBOL

CHARACTERISTIC

LIMITS
MIN

TYP (Note 3)

UNITS

MAX

VCC = MIN, 10L = 16 mA

V

Guaranteed Input HIGH Voltage for all Inputs

V

Guaranteed Input LOW Voltage for all Inputs

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

0.8

IlL

I nput LOW Current

-250

-400

}J.A

1.0

40

}J.A

VCC - MAX, VIN - 4.5 V

1.0

mA

VCC = MAX, VIN - 5.25 V
VCC - MAX, VOUT - 4.5 V

Input HIGH Current

ICE X

Output Leakage Current

VCD

Input Diode Clamp Voltage

2.1

0.45

V

VOL

IIH

0.3

CONDITIONS

1.6

1.0

100

}J.A

-1.0

-1.5

V

95

115

mA

TA;;' 75°C

130

mA

TA = DoC

145

mA

TA =-55°C

Power Supply Current

ICC

VCC = MAX, VIN - 0.4 V

VCC - MAX, liN = -10 mA
VCC = MAX,
All Inputs Grounded

AC CHARA,CTERISTlCS: Over Guaranteed Operating Ranges (Notes 1, 2, 4, 5, 6)
93415AXC
SYMBOL

CHARACTERISTIC

MIN

TYP

93415XC

MAX

MIN

(Note 3)
READ MODE

TYP

93415XM

MAX

MIN

(Note 3)

TYP

MAX

CONDITIONS

DELAY TIMES

tACS

Chip Select Time

15

20

15

35

15

45

tRCS

Chip Select Recovery Time

15

20

20

35

20

50

Address Access Ti me

25

30

30

45

40

60

tAA
WRITE MODE

UNITS

(Note 3)

ns

See Test Circuit
and Waveforms

DELAY TIMES

tws

Write Disable Time

15

20

20

35

20

45

tWR

Write Recovery Time

20

25

25

40

45

50

ns

INPUT TIMING
REQUIREMENTS
Write Pulse Width

tw

20

15

35

25

40

25

5

0

5

0

5

0

See Test Circuit

(to guarantee write)
tWSD

Data Set.Up Time Prior to Write

tWHD

Data Hold Time After Write

5

0

5

0

5

0

tWSA

Address Set·Up Time

5

0

5

0

15

0

tWHA

Address Hold Time

5

0

5

0

5

0

tWSCS

Chip Select Set-Up Time

5

0

5

0

5

0

tWHCS

Chip Se[ect Hold Time

5

0

5

0

5

CI

Inp~t

Co

Output Pin Capacitance

Pin Capacitance

and Waveforms

ns

0

4

5

4

5

4

5

7

8

7

8

7

8

pF

NOTES:

1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified II MITS represent the "worst case" value to the parameters. Since these "worst case" values normally occur at the temperature
and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical limits are at VCC = 5.0 V, TA = +25°C, and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range there is an addi~
tional requirement of two minute warm~up. Temperature range of operation refers to case temperature for F latpaks and ambient temperature
for all other packages. Typical thermal resistance values of the package at maximum termperature are:
() JA (Junction to Ambient) (at 400 fpm air flow) = 50°C/Watt, Ceramic DIP, 65°!C/Watt, Plastic DIP; NA, Flatpak.
JA (Junction to Ambient) (still air) "'" 90°C/Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
8 JC (Junction to Case) = 25°C/Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 10o C!Watt, Flatpak.

e

5. The MAX address access time is guaranteed to be the "worst case" bit In the memory using a pseudo random testing pattern.
6. tw measured at t WSA MIN, t WSA measured at tw = MIN.
;:;0

7-80

FAIRCHILD ISOPLANAR TTL MEMORY • 93415/93415A
TYPICAL ELECTRICAL CHARACTERISTICS

OUTPUT CURRENT
VERSUS OUTPUT
VOLTAGE (OUTPUT HIGH)

,

NORMALIZED ADDRESS
ACCESS TIME VERSUS
TEMPERATURE

t~L)

/

,

V

,

f-'

POWER SUPPLY CURRENT
VERSUS TEMPERATURE

vc~· s,~v

,

V

,

INPUT THRESHOLD
VOL TAGE VERSUS
TEMPERATURE

t---t---H--l--t

vJ, ' J" I

I

ALL INPUTS GROUND

r-_
r-r-.

,

f..---

,

,
-1.0

SLOPE "-0 2 n,r'c

0
TJ

TJ - JUNCTION TEMPERATURE -"C

VOUT - OUTPUT VOLTAGE - VOLTS

JUNCTION TEMPERATURE

AC Test Load and Waveforms same as 93L415. see page

TJ - JUNCTION TEMPERATURE -"C

C

7~76.

APPLICATIONS

330

Vee

Vee

Vee

n

330

n

330

Q

I.
AO

DO

DO

1;29321
DECODER

93415/

93415/

93415A

93415A

DO

II

93415;

A2 TOA 12

ADDRESSES

DATA IN
DATA OUT
WE

}

93415A

TO ALL

93415;
93415As

DO

DO
93415/

93415/

93415A

93415A

es
DO

-------93415;
93415A

93415;
93415A

93415/

9341SA

DATA OUT

Do

DO

BIT 0

8IT1-----------

BIT 15

Addressing for a 4096-bit memory plane by 16 bits (4K by 16) requires only half of a 9321 1-of-4 decoder and any necessary buffers.

7-81

93417
ISOPLANAR SCHOTTKY TTL MEMORY
256x4-BIT PROGRAMMABLE READ ONLY MEMORY

DESCRIPTION - The 93417 is a fully decoded high-speed 1024-bit field Programmable ROM organized 256 words by four bits per word. The 93417 has uncommitted
collector outputs. The outputs are disabled when either CS1 or CS2 are in the HIGH
state. The 93417 is supplied with all bits stored as logic "1 "s and can be programmed
to logic "O"s by following the field programming procedure.

•
•
•
•
•
•
•
•
•

FULL MIL AND COMMERCIAL RANGES
FIELD PROGRAMMABLE
ORGANIZED 256 X 4 BITS PER WORD
UNCOMMITTED COLLECTORS
FULLY DECODED - ON-CHIP ADDRESS DECODER AND BUFFER
CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
WIRED-OR CAPABILITY
STANDARD 16-PIN DUAL IN-LINE PACKAGE
NICHROME FUSE LINKS - FOR HIGH RELIABILITY

LOGIC SYMBOL

CS, CS2
13 14

4

3

2

'5

12

11

10

9

PIN NAMES
AO-A7

Address Inputs

CS1,CS2

Chip Select Inputs

01 - 04

Data Outputs

VCC~Pin16

GND

lOGIC DIAGRAM

~

PIn 8

CONNECTION DIAGRAM
DIP (TOP VIEW)
1024 BIT CELL
32 X 32
MEMORY MATRIX

A6

A7

- - - - - --I
A,,_____
I

A,

CS,

@Ao---_ _- I

A3

CS,

@0

A

@ vee---,

o ::

Vee

AS

@

GNoJ...

Pin Numbers

0,
@

0,

®

-=7-82

AD

0,

A,

0,

A,

03

GNo

0,

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the

Dual In·line Package.

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93417
FUNCTIONAL DESCRIPTION - The 93417 is a bipolar field Programmable Read Only Memory (PROM) organized 256
words by four bits per word. Open collector outputs are provided for use in wired-OR systems. Chip Selects are active LOW;
conversely, a HIGH (logic "1") on the CSl or CS2 will disable all outputs.
The read function is identical to that of a conventional bipolar ROM. That-is, a binary address is applied to the AO through
A7 inputs, the chip is selected, and data is valid at the outputs after tAA nanoseconds.
Programming (selectively opening nichrome fuse links) is accomplished by following the sequence outlined below.

PROGRAMMING - The 93417 is manufactured with all bits in the logic "1" state. Any desired bit (output) can be programmed to a logic "0" state by following the procedure shown in Chapter 6, page 6 -14.

ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Temperature (Ambient) Under Bias
VCC
Input Voltages
Current into Output Terminal
Output Voltages

-65°C to +150 o C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
100 mA
-0.5 V to +5.5 V

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (VCC!

PART NUMBER

x=

--

MAX

AMBIENT TEMPERATURE

MIN

TYP

93417XC

4.75 V

5.0 V

5.25 V

O°c to +75"C

93417XM

4.50 V

5.0 V

5.50 V

-55°C to +125°C

package type; F for Flatpak, D for Ceramic DIP, P for Plastic DIP. See Package Information on this data sheet.

DC CHARACTERISTICS: Over guaranteed operating ranges unless otherwise noted.
LIMITS
SYMBOL

MIN

CHARACTERISTIC

TYP

MAX

UNITS

CONDITIONS

(Note 1!
VCC = 5.25 V, VCEX = 4.95 V, O°C to +75°C

ICEX

Output Leakage Current

50

MA

ICEX

Output Leakage Current

100

}1A

VOL

Output LOW Voltage

0.45

V

VCC = MIN, IOL = 16 rnA, AO = +10.8 V
Al through A7 = HIGH

VIH

Input HIGH Voltage

V

Guaranteed Input HIGH Voltage for All Inputs

VIL

I nput LOW Voltage

V

Guaranteed Input LOW Voltage for All Inputs

0.30

Address any HIGH Output
VCC = 5.5 V, VCEX = 5.2 V, _55°C to +125°C
Address any HIGH Output

..

2.0
0.8

Input LOW Current
IF

IFA (Address Inputs!

-160

-250

MA

IFCS (Chip Select Inputs!

-160

-250

MA

IRA (Address Inputs!

40

jJ.A

IRCS (Chip Se1ect Inputl

40

VCC = MAX, VF = 0.45 V

Input HIGH Current
IR

ICC

Power Supply Current

Co

Output Capacitanc~

Input Capacitance
CIN
----I nput Clamp Diode Voltage
Vc

...

85
7

110

_-

VCC - MAX, Outputs open
Inputs Grounded and Chip Selected

pF

VCC = 5.0 V, Vo = 4.0 V, f = 1.0 MHz

pF

VCC = 5.0 V, Vo = 4.0 V, f = 1.0 MHz

V

VCC = MIN, IA ~ -18 rnA

. - _.

4

-1.2

7-83

rnA

-----

1------..

VCC = MAX. VR = 2.4 V

IJA
-~~

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93417
AC CHARACTERISTICS: T A
SYMBOL

=

O°C to +75"C, VCC

CHARACTER ISTIC

=

5.0 V' 5%.
LIMITS
MIN

TYP (Note 11

MAX

UNITS

25

45

ns

tAA+

25

45

ns

tACS-

12

20

ns

12

20

ns

tAA-

Address to Output Access Time
Chip Select Access Jime

tACS+

CONDITIONS

See Waveforms
and Test Circuits

AC CHARACTERISTICS: TA = -55"C to +125"C, VCC = 5.0 V, 10%.

SYMBOL

CHARACTERISTIC

LIMITS
TYP (Note 11

MIN

Address to Output Access Time
Chip Select Access Time
Note 1:

Typical values are at

Vee =

60

ns

25

60

ns

12

30

ns

12

30

ns

AC WAVEFORMS

AC TEST OUTPUT LOAD

7-84

UNITS

25

5.0 V, +25°C and max loading.

15 rnA Load

MAX

CONDITIONS

See Waveforms
and Test Circuits

TTL ISOPLANAR MEMORY 93419
64x9-BIT FULLY DECODED RANDOM ACCESS MEMORY

OEseR IPTION - The 93419 is a 576-bit Read/Write Random Access Memory organized 64 words by nine bits per word with uncommitted collector outputs. It is ideally
suited for scratchpad, small buffer and other applications where the number of required
words is small and where the number of required bits per word is relatively large. The
ninth bit can provide parity for 8-bit word systems.
•
•
•
•
•
•
•

UNCOMMITTED COLLECTOR OUTPUTS
TTL INPUTS AND OUTPUTS
ISO PLANAR TECHNOLOGY
ORGANIZATION - 64 WORDS X 9 BITS
STANDARD 2B-PIN DUALIN-UNE PACKAGE
DATA OUTPUT IS THE COMPLEMENT OF DATA INPUT
POWER DISSIPATION-O.87mW/BIT

LOGIC SYMBOL

15 13 <;

25

AO

26

A,

27

A2

5

6

7

B

9

10 11 12

93419

A3
A4
A5

PIN NAMES

Ao- A 5

Address Inputs

DO- D8

Data Inputs

II

I

24 23 22 21 20 19 18 17 16

00- 0 8

Data Outputs

WE

Write Enable Input

vee

~

Pin 28

CS

Chip Select Input

GND

~

Pin 14

LOGIC DIAGRAM

CONNECTION DIAGRAM
DIP (TOP VIEW)

0 A5
0 A4
CD A3

ADDRESS
DECODER

32 X 18
CELL ARRAY

WORO
DRIVERS

@A2
@A1

PINS 0THRU

SENSE AMPS AND
WRITE DRIVERS

@
@

vee
GND

~
~

L-~t::f~~

______________

~r~-~-

--I

I

I

I

I

~X9

Pin 28

I
I
I

: DOUT I
IL _____
0-----..8 JI

Pin 14

0= Pin Numbers

28

A4

27

A2

A5

26

A,

DO

25

AD

0,

24

00

02

23

0,

03

22

02

04

21

03

05

20

04

06

WE

PINS

7-85

@

THRU

Vee

A3

05

D7

06

08

07

WC§13
GND

,14

't~
;5

CS

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93419
FUNCTIONAL DESCRIPTION - The 93419 is a fully decoded 576-bit Random Access Memory organized 64 words by
nine bits. Word selection is achieved by means of a 6-bit address, Ao to A5'
The Chip Select input provides for memory array expansion. For large memories, the fast chip select access time permits
the decoding of chip select (CS) from the address without affecting system performance.
The read and write operations are controlled by the state of the active LOW Write Enable (WE, pin 13). With WE held LOW
and the chip selected, the data at DJN is written into the addressed location. To read, WE is held HIGH and the chip selected. Data in the specified location is presented at DOUT and is inverted from Data In to Data Out.
Uncommitted collector outputs are provided to allow maximum flexibility in output connection. In many applications such
as memory expansion, the outputs of many 93419s can be tied together. In other applications the wired-OR is not used. In
either case an external pull-up resistor of RL value must be used to provide a HIGH at the output when it is off. Any RL
value within the range specified below may be used.
RL is in kO (limited to 8 mAl
VCC(MAX)
IOL - FO (1.6)

~ RL ~

= number of wired-OR outputs tied together
= number of TIL Unit Loads (UL) driven
'CEX = Memory Output Leakage Current
VOH = Required Output HIGH Level at Output Node
IOL = Output LOW Current
n

VCC (MIN) - VOH

FO

n (ICEX) + FO (0.04)

The minimum RL value is limited by output current sinking ability. The maximum RL value is determined by the output and
input leakage current which must be supplied to hold the output at VOH' One Unit Load = 40 JiA HIGH/l.6 mA LOW.
FOMAX = 5 UL.

TYPICAL INPUT AND OUTPUT CHARACTERISTICS
OUTPUT CURRENT
VERSUS OUTPUT VOLTAGE
(LOW STATE)

TABLE I - TRUTH TABLE
INPUTS

OUTPUT

INPUT CURRENT
VERSUS INPUT VOLTAGE

MODE

T:

0.5

CS

WE

D,N

Open
Collector

"E
,

H

L
L
L

X
L
L

X

H

L

H

H

H

H

X

DOUT'

NOT SELECTED
WRITE "0'"
WRITE "1'"
READ

~

-0.5

a:
a:

8- 1 .0
~

"

~-1.5

=

~~~~g

;{/

TA = +125 o C

0

A

f:

VI
~

~

10

-

- - t--

"

1.0

3.0

I

5.0

"

9

VfC" 5.0 V
7.0

9.0

VIN - INPUT VOLTAGE - V

"

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
'Input Voltage (de)
'Input Current (dc)
Voltage Applied to Outputs (Output HIGH)
Output Current (dc) (Output LOW)

.j

~

II
t--

tl ~t

+125°C ..

.......

5

I

... Memory inverts from Data In to Data Output

TA

TA"'+75 0 C "-

~

0

~

-2.5
-1.0

I

~

I

~-2.0

HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Don't Care (HIGH or LOW)
H

20

~

§
a:
"u

foTA +12.lC
- TA = +25°C

it== j-TAr550r

"E,

0

AtIC

TA

=

-55 DC

VI

~
0.1 0.2

0.3

0.4

0.5

0.6

0.7

VOUT - OUTPUT VOLTAGE - V

-65°C to +150 0 C
-55°C to +125°C
-0,5 V to +7.0 V
-0.5 V to +5,5 V
-12 mA to +5,0 mA
-0,5 V to +5.5 V
+10 mA

*Either input voltage or input current limit is sufficient to protect the input.

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (Vce)
PART NUMBER

AMBIENT TEMPERATURE
(Note 4)

MIN

TYP

MAX

93419Xe

4.75 V

5.0V

5.25 V

ooe to +75°e

93419XM

4.50V

5.0V

5.50 V

-55°e to +125°e

x = package type; F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-86

FAIRCHILD ISOPLANAR TTL MEMORY. 93419
DC CHARACTERISTICS' Over Operating Temperature Ranges (Notes 1 2 and 4)
SYMBOL

PARAMETER

LIMITS
MIN

TYP
(Note 3)

MAX

0.3

0.50

UNITS

CONDITIONS

VOL

Output LOW Voltage

V IH

Input HIGH Voltage

V IL

Input LOW Voltage

1.5

0.8

IlL

Input LOW Current

-250

-400

pA

VCC

1.0

40

pA

VCC

1.0

mA

1.0

100

pA

-1.0

-1.5

2.1

1.6

Input HIGH Current

IIH
ICEX

Output Leakage Current

V CD

Input Clamp Diode Voltage

Power Supply Current

ICC

100

Guaranteed Input HIGH Voltage for all Inputs

IOL

12mA

Guaranteed Input LOW Voltage for all fnputs

= MAX, VIN = 0.4 V
= MAX, V IN = 4.5 V
VCC = MAX, V IN = 5.25 V
VCC = MAX, VOUT = 4.5 V
VCC = MAX, liN = -10 mA
TA = 125°C
VCC = MAX,

V

mA

150

mA

TA - 25°C

165

mA

TA -

1

=

VCC

V
V

120'

= MIN,

V

55°C

All Inputs Grounded
Outputs LOW

AC CHARACTERISTICS' Over Guaranteed Operating Ranges (Notes 1 2 4 56)
93419XC
SYMBOL
READ MODE

CHARACTERISTIC

MIN

93419XM

TYP
MAX
(Note 3)

MIN

TYP
MAX
(Note 3)

CONDITIONS

DELAY TIMES

tACS

Chip Select Access Time

15

40

15

40

tRCS
tAA

Chip Select Recovery Time

20

40

20

40

Address Access Time

35

45

40

60

WRITE MODE

UNITS

See Test Circuit
ns

and Waveforms

DELAY TIMES

tws

Write Disable Time

20

40

20

45

tWR

Write Recovery Time

25

45

45

55

tw

Write Pulse Width
(to guarantee write)

tWSD

Data Set-Up Time Prior to Write

ns

INPUT TIMING REQUIREMENTS
35

20

45

25

5

0

5

0

See Test Circuit
and Waveforms

tWHD

Data Hold Time After Write

5

0

5

0

tWSA

Address Set-Up Time

5

0

10

0

tWHA

Address Hold Time

0

Chip Select Set-Up Time

0

5
5

0

tWSCS

5
5

tWHCS

Chip Select Hold Time

5

0

5

0

ns

0

CIN

Input Pin Capacitance

4

5

4

5

COUT

Output Pin Capacitance

7

8

7

8

pF

NOTES:
Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
The specified LIMITS represents the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes, additional nOise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.

3. Typical limits are at
4.

Vee::'::

5.0 V, TA = +25°C, and MAX loading.

The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range an additional requirement of a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambIent temperature for all other packages. Typical thermal resistance values of the package at maximum temperature are:
BJA (Junction to Ambient) (at 400 fpm air flow) = 50°C/Watt, Ceramic DIP; 65°CC/Watt, Plastic DIP; NA, Flatpak.
BJA (Junction to Ambient) (still aIr) = 90°C/Watt, Ceramic DIP; 110°C/Watt, PlastIC DIP; NA, Flatpak.
BJC (Junction to Case) = 25°C / Watt, CeramIc DIP; 25°C /Watt, Plastic DIP; 1DOC/Watt, Flatpak.

5.
6.

The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
tw measured at t WSA = MIN, t WSA measured at tw = MIN.

7-87

•

FAIRCHILD ISO PLANAR TTL MEMORY. 93419
TYPICAL ELECTRICAL CHARACTERISTICS

OUTPUT CURRENT
VERSUS OUTPUT
VOLTAGE (OUTPUT HIGH)
'.0
vci: =.'ov

.
~

0.11

!iW

0

~

NORMALIZED ADDRESS
ACCESS TIME VERSUS
TEMPERATURE

..•

t:I::~~

1

i
i

TA = +12&OC

..

~-o.6

~
g-1.0

V C=&.OV

It-TA = -66
rTA = 210C

'.0

2.0

~r

3.0

r-

~
!:
SLOPE

•
.....

4.0 5.0 8.0

I'··

Your - OUTPUT VOLTAGE - V

20

0

20

10

I

38 pare
100

140

t

TJ - JUNcnON TEMPERATURE - "C

POWER SUPPLY CURRENT
VERSUS TEMPERATURE

v~c ='I.o~v

-

Vee = MAX
ALL INPUTS GROUND

0

~- -r-.

1"

0

!

-r- 1-1--

~ '.0

o.
0

g

.... 1-

-I -I

2 ••

I

III r-:! 2.0

I

9

-2.0
-1.0

>

L f-+I-f-

0

t=TA"" 12&OC

I

5-1.6

r

INPUT THRESHOLD
VOLTAGE VERSUS
TEMPERATURE

0

r-

0

i"',

D••

r~o -20

0
0

20

80

100

oc

TJ - JUNCTION TEMPERATURE -

.2 mAlOC

SLOPE

-so

140

20 0

20

80

."I"

100

AC TEST LOAD AND WAVEFORM
LOADING CONDITION
C

INPUT PULSES

i=!t-t ---------- -:1= --

VCC

ALL INPUT PULSES

1,---_
- -- - - -- - \ -- - -

400n

3.6 Vp _p

DDUT

93419

BOO

n

I

-=- -I

GND

T-=- -III

GND

-t-

__________.

_n

o~p.P-+\;

(CAPACITANCE
INCLUDING SCOPE
AND JIG I

-

90%
10%

."'i 1__ '0 ns

1--10 ns

3.~ -

~ 30 pF

-

-

-

-

-

-

I

:-.. - - 10%
1--.-90%

II

~ 1--10 ns

1--10 ns

READ MODE

PROPAGATION DELAY FROM CHIP SELECT

Ci
CHIP SELECT

DOUT
DATA OUTPUT

I
I
I
I

PROPAGATION DELAY FROM ADDRESS INPUTS

;;::)K

)f

\

\
I

l-o'ACS~

I
I
I
I
I
I

AO - A6
ADDRESS INPUTS

r

DOUT
DATA OUTPUT

I

(ALL TIME MEASUREMENTS REFERENCED TO 1.5 V)

7-88

I

I
I

I-o-'RCS-i

140

TJ - JUNCTION TEMPERATURE - "C

i

L
I

I+---'AA------J

FAIRCHILD ISOPLANAR TTL MEMORY • 93419
AC WAVEFORMS (Cont'd)
WRITE MODE

\

;:

--------,----.)K

)Kr----r------

CS
CHIP SELECT

I ~------------------------------~

AO A5
ADDRESS INPUTS

...... I'----........------

---------:-----II~--------------------

i ~

DO-OS
DATA INPUTS

)K~~i____~____
I

I

WE
WRITE ENABLE

I tWSD-t---"'!

l-tWHCS------------..I

111

I-- tWSA -.!
~twscs_1

oo-OS
DATA OUTPUTS

I
I

i

\

I

I

I
I

I-tws--I

I-twR-I

I

(ALL TIME MEASUREMENTS REFERENCED TO 1.5 V)
NOTE: Timing Diagram represents one solution which results in an optimum cycle time Timing may be changed to fit various applications as long as the
worst case limits are not violated.

TYPICAL SYSTEM TIMING
WRITE

AO-A5
ADDRESS INPUTS

DO - Os

DATA INPUTS

WE
WR ITE ENASLE

..-5 ns ...\ ....- - - - 35

ns------I

cs
CHIP SELECT

READ

AO - A5
ADDRESS INPUTS ______J

cs
CHIP SELECT

WE
WRITE ENABLE

_ _ _ _.J

1...----·1--415 ns

oo-os
DATA OUTPUTS

7·89

•

TTL ISOPLANAR MEMORY 93L420
256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93L420 is a low power high -speed 256-bit Read/Write Random
Access Memory organized 256 words by one bit. It is designed for scratchpad, buffer
and distributed main memory applications requiring low power. The device has three
chip select lines to simplify its use in larger memory systems. Address input locations
are specifically chosen to permit maximum packaging density and for ease of PC board
layout. A 3-state output is provided to drive bus organized systems and/or highly capacitive loads.
• 3-STATE OUTPUT
• ORGANIZATION - 256 WORDS X 1 BIT
• THREE HIGH-SPEED CHIP SELECT INPUTS
• TYPICAL READ ACCESS TIME - 40 ns
• ON-CHIP DECODING
• POWER DISSIPATION - 275 mW TYPICAL
• POWER DISSIPATION DECREASES WITH TEMPERATURE
• INVERTED DATA OUTPUT

LOGIC SYMBOL

12

6

WE

LOADING
(Notes a, b)
0.5 U.L.

PIN NAMES
CS1' CS2,CS3

Chip Select Inputs

AO-A7

Address Inputs

0.5 U.L.

DIN

Data Input

0.5 U.L.

DOUT
WE

Data Output

10 U.L.

Write Enable

0.5 U.L.

NOTES:
a. 1 Unit Load (U.L.) ~ 40/lA HIGH I 1.6 rnA LOW
b. 10 U.L. is the output LOW drive factor. This output will.sink a maximum of 16 rnA at VOUT
will source a minimum of 10 rnA at 2.4 V

= 0.45 V,

and

?
6

Vee

~

Pin 16

GNO

~

Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

LOGIC DIAGRAM
X ADDRESS
DECODER

WORD
DRIVE8

AD
DOUT

®

A,

A3

CS1

A,

cs,

CD
Cs2 CD
CS3 CD
WE

@

DIN

@

D,N

WE
A7
A.

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.

Vee ~ Pin 16

GND

~

A5

Pin 8

0= Pin Numbers
7-90

FAIRCHILD ISO PLANAR TTL MEMORY • 93L420
FUNCTIONAL DESCRIPTION - The 93L420 is a fully decoded 256 -bit Random Access Memory organized 256 words by
one bit. Word selection is achieved by means of an 8-bit address, AO through A7.
Three Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select, CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable (WE, pin 12). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected.
Data in the specified location is presented at DOUT'
The 3-state output provides drive capability for higher speeds with high capacitive load systems The third state (high impedance) allows bus organized systems where multiple outputs are connected to a common bus.
During writing, the output is held in the high impedance state.

TABLE I - TRUTH TABLE
OUTPUT

INPUTS
CS,

CS2

CS3

WE

DIN

DOUT

H
X
X
L
L

X
H
X
L
L

X
X
H
L
L

X
X
X
L
L

X
X
X
L
H

HIGHZ
HIGH Z
HIGH Z
HIGH Z
HIGH Z

L

L

L

H

X

DOUT

MODE
Not Selected
Not Selected
Not Selected
Write "0"
Write "'"
Read inverted data from
addressed location

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care (HIGH or LOW)
HIGH Z = High Impedance

TABLE 2 - FUNCTION TABLE
FUNCTION

CHIP SELECT

INPUTS
WRITE ENABLE

OUTPUT

Write

L

L

Read

L

H

Stored Data

Not Selected

H

X

HIGH Z

HIGH Z

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
*Input Voltage (dc)
*Input Current (dc)
**Voltage Applied to Outputs (output HIGH)
Output Current (dc) (output LOW)

-65°C to +150 oC
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.50 V
+20mA

*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES

MIN

SUPPLY VOLTAGE (Vccl
TYP

MAX

93L420XC

4.75 V

5.0V

5.25 V

ooC to +75°C

93L420XM

4.50 V

5.0V

5.50 V

-55°C to +'25°C

PART NUMBER

x = package type; F for Flatpak, 0

AMBIENT TEMPERATURE
Note 4

for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-91

•

FAIRCHILD ISOPLANAR TTL MEMORY • 93L420
DC CHARACTERISTICS: Over Operating Temperature Ranges. Notes 1, 2 and 4
SYMBOL

PARAMETER

MIN

LIMITS
TYP
(Note 3)

MAX

0.3

0.45

UNITS

CONDITIONS

V

VCC = MIN, 10L = 16 mA

V

Guaranteed Input Logical HIGH
Voltage for all Inputs

V

Guaranteed Input Logical LOW
Voltage for all Inputs

VOL

Output LOW Voltage

V IH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

0.85

IlL

Input LOW Current

-530

-800

/lA

VCC = MAX, VIN = 0 V

IIH

Input HIGH Current

1.0

20

/lA

VCC = MAX, VIN = 4.5 V

50
-50

/lA

VCC = MAX, VOUT = 2.4V
VCC = MAX, VOUT = 0.5 V

-1.5

V

10FF

Output Current (HIGH Z)

VCD

Input Clamp Diode Voltage

2.0

1.6

-1.0

93L420XC
Power Supply
Current

ICC

VOH

70

55

mA
93L420XM

70

55

Output HIGH

93L420XC

2.4

V

10H = -10.3 mA

93L421XM

2.4

V

10H =-5.2 mA

-100

mA

AC CHARACTERISTICS: Over Guaranteed Operating Ranges. Notes 1, 2, 4, 5, 6

SYMBOL

CHARACTERISTIC

READ MODE
-tACS
tZRCS
tAA

DELAY TIMES
Chip Select Access Time
Chip Select to HIGH Z
Address Access Time

WRITE MODE

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

DELAY TIMES
Write Disable to HIGH Z
Write Recovery Time
INPUT TIMING REOUIREMENTS
Minimum Write Pulse Width
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

CIN
COUT

Input Capacitance
Output Capacitance

MIN

35
5
5
5
5
0
0

VCC = MAX, Note 7

I

93L420XM

93L420XC

tzws
tWR

VCC = MAX, WE
Grounded, all other inputs
@ 4.5 V, see Power Supply
vs Temp. Curve

Voltage

Output Current
Short Circuit to Ground

lOS

VCC = MAX, liN = -10 mA
TA = O°C
to +75°C
TA = -55°C
to +125°C

TYP
MAX
(Note 3)

MIN

TYP
MAX
(Note 3)

UNITS

20
25
40

25
30
45

20
25
40

40
40
55

ns

25
45

30
50

25
45

40
55

ns

15
0
0
0
0
0
0
2.5
5

40
5
5
10
5
0
0
3.5
7

15
0
0
0
0
0
0
2.5
5

CONDITIONS

See Test Circuit
and Waveforms
Note 5

See Test Circuit
and Waveforms
Note 6
ns

3.5
7

pF

Measured with a
pulse technique

NOTES:
1. Conditions for testing, not shown in the Table. are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represents the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at VCC = 5.0 V, TA = +25°C, and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical
thermal resistance values of the package at maximum temperature are:
8JA (Junction to Ambient) (at 400 fpm air flow) = 50°C/Watt, Ceramic OIP; 65°C/ Watt, Plastic DIP; NA, Flatpak.
8JA (Junction to Ambient) (still air) = 90°C/Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
8JC (Junction to Case) = 25°C/Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 10°C/Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at tWSA = MIN, tWSA measured at tw = MIN.
7. Duration of short circuit should not exceed one second.

7-92

FAIRCHILD ISO PLANAR TTL MEMORY • 93L420
TYPICAL ELECTRICAL CHARACTERISTIC CURVES
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH Z STATE)

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

90

35
Vee "5.0V

80

30

«

E

«

70
TA-i 300e ....

1

t-

~

3
~
t::>
0

E

60

TA = 25°C

50

I

TA·we,

30

1

t::>

0

25

::>

~

2 0 t - - TA = +125"C

t::>
0

15

";rt-

40

t::>

10

5
0
-10

Irrr

4

TA

-1.5

3

OA

0.5

55°C

0.5

0.6

Vee'" 5.0V

TA '"

1125 C/

«

0

I ....

*a

Y'

~yee'4.5v

Vc

-= 5.5V

vCC1 '" 5.0V

Vee

=

5.SV

-1.0'

t-

;r

I
I

TA=+25°C

f::=

~

E

~ -0.5

I'

vee~45~~

0

TA'" +125°C

2

'I

0.3

TA~+25'C ~

V

,-4

t-

;r

0.2

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS SUPPLY VOLTAGE

«

-1.0

0.1

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE

0

~13

6

Your - OUTPUT VOLTAGE - VOLTS

Vee = 5.0V

E

5

r--

TAI we

Your - OUTPUT VOLTAGE - VOLTS

0.5

~ -0.5

J

0
3

1

0

tl(

'II

.9

10

rL

'L

I!~I

j

1

20

.9

~

TA '" J5 C

,...1

IL V-

'3"
1

TA' -r5oe

-2.0

-1.5

-2.0
T A'" +2S C
D

-2.5
-1.0

1.0

3.0

5.0

7.0

9.0

1

-2.5
-1.0

11

1.0

VIN - INPUT VOLTAGE - VOLTS

AC WAVEFORMS

INPUT PULSES
ALL INPUT PULSES

t --- .-------------- ,

~

H--------------K--

-----90%

-10%

n---------1---

,I ,I

GNO

,I ,I

-I

l-l0ns

t--- 10ns

-10%

t

-i-

---

GNO

3.0

5.0

7.0

9.0

11

VIN - INPUT VOLTAGE - VOLTS

--------------

, ,
I

--

I

-,---90%

If

--

, ,

...... 10ns

7-93

t--l0ns

•

FAIRCHILD ISOPLANAR TTL MEMORY • 93L420
AC WAVEFORMS

READ MODE

PROPAGATION DELAY FROM CHIP SELECT

PROPAGATION DELAY FROM ADDRESS

AO to A7

CS 1 CS 2 CS 3
CHIP SELECT

ADDRESS

________J

¥
,

~

________________________

,

x

Dour'
lOAD A

Dour
DATA OUTPUT

Dour

------.-----------'

LOAD B

I

~-----

'------IAA-----. ,

(All time measurements referenced to 1.5 V)

WRITE MODE

CS2

CS1,C$3
CHIP SELECT

~{

~~

7

1\

Ao to A7

JK

J\.

ADDRESS

D'N
DATA IN

JK

J~
...--tw----+-

\

We
WRITt:: ENABLE

~twSD ....

-I

\

/

- -- -

....--lWSA~

•

twscs

HIGH Z

LOAD A

...tWHD~

.

. . - - tWHA-----'

--

1--,

twHCS

.

-'~

Dour
4---tWR~

DATA OUTPUT

V

LOAD B

HIGH Z

(All time measurements referenced to 1.5 V)

NOTE; Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-94

FAIRCHILD ISOPLANAR TTL MEMORY • 93L420
PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

t'"~tZRes-

cs1 cs2 cs3
CHIP SELECT

Dour

",--HiGHZ

--, ~

"0" LEVEL

DATA OUTPUT

I 0.5 V

LOADC

"'" LEVEL

-..:~lo.5V

li(iUT

I'\... __ ..!!!':!!.!

DATA OUTPUT

WRITE ENABLE TO HIGH Z DELAY

WE

WRITE ENABLE

- ' ~'.5V

_tzws,,'--HtGHZ

Dour
DATA OUTPUT

......, ~10.5V

"0" LI:VEL
"1" LEVel

-'

DOUT
DATA DUTPUT

r-- 10.5V

~\... - - -HtGHZ
-

(All tzxxx parameters are measured at a delta of 0.5 V from
the logic level and using Load C.)

•

AC TEST LOAD

5V

Vee

300n

750n

DOuT

°OUT

93L420
93L42,
9342'
9342' A

t

li"'

6

3DpF

93L420
93L42'
9342'
9342'A

f:n

Load A

30pF

93L420
93L42,
93421
9342'A

t~o

Load B

7-95

5pF

":"

Load C

TTL ISOPLANAR MEMORY 93L421
256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93L421 is a low power 256-bit Read/Write Random Access
Memory organized 256 words by one.bit. It is designed for scratchpad, buffer and distributed main memory applications requiring low power. The device has three Chip Select lines to simplfy its use in larger memory systems. Address input locations are specifically chosen to permit maximum packaging density and for ease of PC board layout.
A 3-state output is provided to drive bus organized systems and/or highly capacitive
loads.
•
•
•
•
•
•
•
•

3-STATE OUTPUT
ORGANIZATION - 256 WORDS X 1 BIT
THREE HIGH-SPEED CHIP SELECT INPUTS
TYPICAL READ ACCESS TIME - 45 ns
ON-CHIP DECODING
POWER DISSIPATION - 275 mW TYPICAL
POWER DISSIPATION DECREASES WITH TEMPERATURE
INVERTED DATA OUTPUT

LOGIC SYMBOL

14
15

10

LOADING
(Notes a, b)
0.5 U.L.

PIN NAMES
Chip Select Inputs

CS" CS2' CS3
AO-A7

Address Inputs

0.5 U.L.

DIN

Data Input

0.5 U.L.

DOUT
WE

Data Output

, a U.L.

Write Enable

0.5 U.L.

11

?
6

Vee ~ Pin 16
GND

~

Pin 8

NOTES:

a. 1 Unit Load lULl ~ 40 JlA HIGH /1.6 mA LOW
b. 10 U.L. is the output LOW drive factor. This output will sink a maximum of 16 rnA at VOUT = 0.45 V, and
will source a minimum of lOrnA at 2.4 V

CONNECTION DIAGRAM
DIP (TOP VIEWI

LOGIC DIAGRAM
X ADDRESS
OECODER

WORD
DRIVER

Dour

®

cs, 0)
cs, (0
CS3

®

WE

@

D"

@

AD

Vee

A1

A3

CS1

A,

CS2

DIN

CS3

WE

DoUr

A,

A4

A6

GNO

A5

NOTE:

Vee ~ Pin 16
GND

~

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In*Une Package.

Pin 8

O~ Pin Numbers

7-96

FAIRCHILD ISO PLANAR TTL MEMORY • 93L421
FUNCTIONAL DESCRIPTION - The 93L421 is a fully decoded 256 - bit Random Access Memory organized 256 words by
one bit. Word selection is achieved by means of an 8-bitaddress, Aothrough A7.
Three Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select, CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable (WE, pin 12). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected.
Data in the specified location is presented at DOUT'
The 3-state output provides drive capability for higher speeds with high capacitive load systems The third state (high impedance) allows bus organized systems where multiple outputs are connected to a common bus.
During writing, the output is held in the high impedance state.

TABLE I - TRUTH TABLE
INPUTS

OUTPUT

CS1

CS 2

CS"3

WE

DIN

H
X
X
L
L
L

X
H
X
L
L
L

X
X
H
L
L
L

X
X
X
L
L
H

X
X
X
L
H
X

MODE

DOUT
HIGH
HIGH
HIGH
HIGH
HIGH

Not Selected
Not Selected
Not Selected
Write "0"
Write "1"
Read inverted data from
addressed location

Z
Z
Z
Z
Z

DOUT

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care (HIGH or LOW)
HIGH Z = High Impedance

TABLE 2 - FUNCTION TABLE
FUNCTION

CHIP SELECT

INPUTS
WRITE ENABLE

OUTPUT

Write

L

L

HIGH Z

Read

L

H

Stored Data

Not Selected

H

X

HIGH Z

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
*Input Voltage (dc)
*Input Current (dc)
**Voltage Applied to Outputs (output HIGH)
Output Current (dc) (output LOW)

-65°C to +150 0 C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.50 V
+20mA

*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES

MIN

SUPPLY VOLTAGE (Vee!
TYP

93L421XC

4.75 V

5.0V

5.25 V

ooe to +75°C

93L421XM

4.50 V

5.0V

5.50 V

-55°e to +125°C

PART NUMBER

MAX

AMBIENT TEMPERATURE
Note 4

X = package type; F for Flatpak, D for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-97

•

FAIRCHILD ISO PLANAR TTL MEMORY • 93L421
DC CHARACTERISTICS: Over Operating Temperature Ranges. Notes 1, 2 and 4
SYMBOL

PARAMETER

MIN

LIMITS
TYP
(Note 3)

MAX

0.3

0.45

UNITS

CONDITIONS

V

VCC = MIN, 10L = 16 mA

V

Guaranteed Input Logical HIGH
Voltage for all Inputs
Guaranteed Input Logical LOW
Voltage for all Inputs

VOL

Output LOW Voltage

V,H

Input HIGH Voltage

V,L

Input LOW Voltage

1.5

0.85

V

',L

Input LOW Current

-530

-800

/lA

VCC = MAX, Y,N = 0 V

"H

Input HIGH Current

1.0

20

/lA

VCC = MAX, Y,N = 4.5 V

50
-50

/lA

VCC = MAX, VOUT = 2.4 V
VCC = MAX, VOUT = 0.5 V

-1.5

V

10FF

Output Current (HIGH Z)

VCD

Input Clamp Diode Voltage

Power Supply
Current

ICC

VO H

2.0

1.6

-1.0

93L421XC

55

70

93L421XM

55

70

mA

VCC= MAX, WE
Grounded, all other inputs
@ 4.5 V, see Power Supply
vs Temp. Curve

Output HIGH

93L421XC

2.4

V

10H = -10.3 mA

Voltage

93L421XM

2.4

V

10H =-5.2 mA

Output Current
Short Circuit to Ground

lOS

VCC = MAX, "N = -10 mA
TA = O°C
to +75°C
TA = -55°C
to +125°C

-100

mA

VCC = MAX, Note 7

AC CHARACTERISTICS: Over Guaranteed Operating Ranges. Notes 1, 2, 4, 5, 6
93L421XC
SYMBOL

CHARACTERISTIC

READ MODE
tACS
tZRCS
tAA

DELAY TIMES
Chip Select Access Time
Chip Select to HIGH Z
Address Access Time

WRITE MODE

tw
tWSD
tWHD
tWSA
tWHA
twscs
tWHCS

DELAY TIMES
Write Disable to HIGH Z
Write Recovery Time
INPUT TIMING REQUIREMENTS
Minimum Write Pulse Width
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

C'N
COUT

Input Capacitance
Output Capacitance

tzws
tWR

MIN

60
5
5
10
10
0
0

93L421XM

TYP
MAX
(Note 3)

MIN

TYP
MAX
(Note 3)

UNITS

30
30
45

40
40
90

35
30
45

50
50
100

ns

30
50

45
60

30
65

55
70

ns

20
0
0
0
0
0
0
2.5
5

70
5
5
15
10
0
0
3.5
7

20
0
0
0
0
0
0
2.5
5

CONDITIONS

See Test Circuit
and Waveforms
Note 5

See Test Circuit
and Waveforms
Note 6
ns

3.5
7

pF

Measured with a
pulse technique

NOTES:
1. Conditions for testing, not shown in the Table, are chosen
guarantee operation under "worst case" conditions.
2. The specified LIMITS represents the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes. additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at VCC = 5.0 V, TA = +25°C. and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical
thermal resistance values of the package at maximum temperature are:

to

8JA (Junction 10 Ambient) lat 400 fpm air flow) = 50o C/Watt, Ceramic DIP; 65°CI Watt, Plastic DIP; NA, Flatpak.
8JA (Junction to Ambient) (still air) = 90°C I Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
8JC (Junction to Case) = 25°C I Watt, Ceramic DIP; 25°C I Watt, Plastic DIP; 1DoC I Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at t WSA MIN, IWSA measured at tw MIN.
7. Duration of short circuit should not exceed one second.

=

=

7-98

FAIRCHILD ISOPLANAR TTL MEMORY • 93L421
TYPICAL ELECTRICAL CHARACTERISTICS

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH Z STATE)

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

90

35

"
E

I
f-

~

""'
"~

30

70
TA-i 3O° C
60

I

50

TA=75"C

0

I
f-

"
5'

...

E
I

~

'"

"

TA" J5 0 C

25

~I

2 0 - TA=+125 C
Q

I/!;/

U

40

f-

i£
f-

30

15

"

0

I
f-

20

"

10

5

Iff

-10

1

0

3

2

Your

~

0

4

5

6

0.1

TA

0.2

0.3

0.4

0.5

55 C
Q

VCC~4.5~

'?j!

Vee = S.OV

TA=+ 25° CJ.'

0

«

E

~ -0.5

~a
I

«

TA=1125ocl

E

~ -0.5

(

a~

-1.0

f-

~

'"

0

V

-1.5

3
-2.0

TA=+12SoC

'"

~

,-

~CC"4.5V

Vc

'" 5.5V

VCG = S.OV

Vee'" S.SV

•

-1,0

f-

I
T A == +2SoC
I

~

0.6

0.5

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS SUPPLY VOLTAGE

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE
Vee = S.OV

J

i--

TA =_55°C

Your - OUTPUT VOLTAGE - VOLTS

OUTPUT VOLTAGE - VOLTS

0.5

K
1/
J

lO

5'

0

J/

«

TA'" 25°C

U

f-

~ V-

Vee == 5.0V

80

i£z

I"

-1.5

3

TA"-i5'C

-2.0
TA ={25°C

-2.5
-1.0

1.0

3.0

5.0

7.0

9.0

-2.5
-1.0

11

VIN - INPUT VOLTAGE - VOLTS

1.0

3.0

5.0

7.0

9.0

VIN - INPUT VOLTAGE - VOLTS

AC Test Load and Waveforms same as 93L420, see page 7·93, 7·94 & 7·95.

7-99

11

TTL ISO PLANAR MEMORY 93421 /93421 A
256 X 1 - BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93421 and 93421A are high -speed 256-bit TTL Random Access
Memories with full decoding on chip. They are organized 256 words by one bit and are
designed for scratchpad, buffer and distributed main memory applications. The devices
have three Chip Select lines to simplify their use in larger memory systems. Address input pin locations are specifically chosen to permit maximum packaging density and for
ease of PC board layout. A 3-state output is provided to drive bus organized systems
and / or highly capacitive loads.
•
•
•
•
•

•
•
•
•

3-STATE OUTPUT
REPLACEMENT FOR 54/745200 AND EQUIVALENT DEVICES
ORGANIZATION - 256 WORDS X 1 BIT
THREE HIGH-SPEED CHIP SELECT INPUTS
TYPICAL READ ACCESS TIME
93421A
Commercial
30 ns
93421
Commercial
35 ns
93421
Military
35 ns
ON CHIP DECODING
POWER DISSIPATION - 1.8 mW/BIT
POWER DISSIPATION DECREASES WITH TEMPERATURE
INVERTED DATA OUTPUT

A,
14

93421/93421A
A5
10

A6

11

A7
DOUT

Chip Select Inputs

AO-A7

Address Inputs

0.5 U.L.

DIN

Data Input

0.5 U.L.

DOUT
WE

Data Output

10 U.L.

Write Enable

0.5 U.L.

NOTES:
a. 1 Unit Load (U.L.) ~ 40 J.lA HIGH /1.6 mA LOW
b. 10 U.L. is the output LOW drive factor. This output will sink a maximum of 16 rnA at VOUT = 0.45 V. and
will source a minimum of 10 rnA at 2.4 V.
WORD
DR!VER

A3
A4

CS1' CS2' CS3

DECODER

A2

15

LOADING
(Notes a, b)
0.5 U.L.

PIN NAMES

X ADDRESS

LOGIC SYMBOL

16 x 16

~

~Pin

Pin 16
8

CONNECTION DIAGRAM
DIP (TOP VIEW)

AD

vce

A,

A3

CS,

A2

LOGIC DIAGRAM

OS2

D,N

@

CS3

WE

Cs2 @

lJoUT

A,

CS3 @

A,

A6

WE @

GND

A5

Csl

ARRAY
MEMORY CELL

vee
GND

NOTE:

Vee ~
GND

~

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

Pin 16
Pin 8

o = Pin Numbers
7-100

FAIRCHILD ISOPLANAR TTL MEMORY. 93421/93421A
FUNCTIONAL DESCRIPTION - The 93421/93421 A are fully decoded 256 - bit Random Access Memories organized
256 words by one bit. Word selection is achieved by means of an 8 - bit address, AO through A7'
Three Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select, CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable (WE, pin 12). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected.
Data in the specified location is presented at DOUT'
The 3-state output provides drive capability for higher speeds with high capacitive load systems. The third state (high impedance) allows bus organized systems where multiple outputs are connected to a common bus.
During writing, the output is held in the high impedance state.

TABLE I - TRUTH TABLE
INPUTS

OUTPUT

CS1

CS2

CS3

WE

DIN

H
X
X
L
L
L

X
H
X
L
L
L

X
X
H
L
L
L

X
X

X
X
X
L
H
X

X
L
L
H

MODE

DOUT
HIGH
HIGH
HIGH
HIGH
HIGH

Z
Z
Z
Z
Z

Not Selected
Not Selected
Not Selected
Write "0"
Write "1"
Read inverted data from
addressed location

DOUT

H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Don't Care (HIGH or LOW)
HIGH Z ~ High Impedance

TABLE 2 - FUNCTION TABLE
FUNCTION

CHIP SELECT

INPUTS
WRITE ENABLE

L

Write

OUTPUT

L

HIGH Z

Read

L

H

Stored Data

Not Selected

H

X

HIGH Z

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.50 V
+20mA

Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
*Input Voltage (dc)
*Input Current (dc)
**Voltage Applied to Outputs (output HIGH)
Output Current (dc) (output LOW)
*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.

HOutput Current limit Required.

GUARANTEED OPERATING RANGES
MIN

SUPPLY VOLTAGE (VCC )
TYP

93421AXC, 93421 XC

4.75 V

5.0V

5.25 V

ooC to +75°C

93421XM

4.50 V

5.0V

5.50V

-55°C to +125°C

PART NUMBER

MAX

AMBIENT TEMPERATURE
Note 4

x = package type; F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-101

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93421/93421A
DC CHARACTERISTICS' Over Operating Temperature Ranges Notes 1 2 and 4
SYMBOL

PARAMETER

MIN

LIMITS
TYP
(Note 3)

MAX

0.3

0.45

UNITS

CONDITIONS

V

VCC = MIN, 10L = 16 mA

V

Guaranteed Input Logical HIGH
Voltage for all Inputs
Guaranteed Input Logical LOW
Voltage for all Inputs

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

0.85

V

IlL

Input LOW Current

-530

-800

pA

VCC = MAX, VIN = 0 V

IIH

Input HIGH Current

1.0

20

pA

VCC = MAX, VIN = 4.5 V

10FF

Output Current (HIGH Z)

50
-50

pA

VCC = MAX, VOUT = 2.4 V
VCC = MAX, VO UT = 0.5 V

VCD

Input Clamp Diode Voltage

-1.0

-1.5

V

93421XC
93421AXC

90
100
90
100

124
135
117
143

Power Supply
Current

ICC

VO H

Output HIGH
Voltage

2.0

93421XM

1.6

mA

VCC = MAX, WE
Grounded, all other inputs
@ 4.5 V, see Power Supply
vs Temp. Curve

TA - +125°C
55°C
TA

93421XC,AXC

2.4

V

10H = -10.3 mA

93421XM

2.4

V

10H =-5.2 mA

Output Current
Short Circuit to Ground

lOS

VCC = MAX, liN = -10 mA
TA = +75°C
TA - OoC

-100

mA

VCC = MAX, Note 7

AC CHARACTERISTICS' Over Guaranteed Operating Ranges Notes 1 2 4 5 6
SYMBOL

CHARACTERISTIC

READ MODE
tACS
tZRCS
tAA

DELAY TIMES
Chip Select Access Time
Chip Select to HIGH Z
Address Access Time

WRITE MODE
tzws
tWR

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

DELAY TIMES
Write Disable to HIGH Z
Write Recovery Time
INPUT TIMING
REQUIREMENTS
Minimum Write Pulse Width
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

CI
Co

Input Capacitance
Output Capacitance

93421AXC
MIN TYP MAX
(Note
3)
20
20
30

30
30
40

10

20
25

35
40

30
0
5
0
5
0
5

10
0
0
0
0
0
0
2.5
5

MIN

3.5
7

93421XC
TYP MAX
(Note
3)
20
20
35

30
30
50

10

20
25

35
40

30
0
5
0
5
0
5

10
0
0
0
0
0
0
2.5
5

3.5
7

93421XM
MIN TYP MAX
(Note
3)

UNITS CONDITIONS

25
20
35

40
40
60

ns

10

20
25

45
50

ns

40
0
5
0
5
0
5

10
0
0
0
0
0
0
2.5
5

See Test Circuit
and Waveforms
Note 5

See Test Circuit
and Waveforms
Note 6
ns

3.5
7

pF

Measured with
pulse technique

NOTES:
1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represents the "worst case" value for the parameters. Since these "worst case" values normally occur at the tem'perature and sup·
ply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at VCC ~ 5.0 V, TA ~ +25°C, and MAX loading.
4.

The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for aI/ other packages. Typical
thermal resistance values of the package at maximllm temperature are:

8JA IJunction to Ambient) lat 400 fpm air flow) = 50°C / Watt, Ceramic DIP; 65°C; Watt, Plastic DIP; NA, Flatpak.
8JA IJunction to Ambient) Istill air) ~ 90°C / Watt, Ceramic DIP; 110°C / Watt, Plastic DIP; NA, Flatpak.
8JC IJunction to Case) ~ 25°C; Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 10°C/Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at tWSA ~ MIN, tWSA measured at tw ~ MIN.
7. Duration of short circuit should not exceed one second.

7-102

FAIRCHILD ISO PLANAR TTL MEMORY • 93421/93421A
TYPICAL ELECTRICAL CHARACTERISTICS

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH Z STATE)

35

Ij'l

Vee'" s.ov

j.....

TA - 130"c

I---I--+---+ TA

25"C+'HH---i
t---t--t--J-TA! 75"C:t=tIH---i

I---

z

=

TA~J5OC

20
u

'PI

I-- TA'" +12S"C

11-"

o

~

15

~

10

,

}~

J

j

~

rl

/

03
VOUT-QUTPUTVOLTAGE

-

TA "'1-S50C

0.6

VOUT - OUTPUT VOLTAGE - VOLTS

VOLTS

POWER SUPPLY CURRENT
VERSUS TEMPERATURE

ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE

0
0

90

0
0

0'-0

:--

-- -r--

0

0

0

-<
.......

,......

~CC-50V_

r-:< . . .......
...

Vl'" 4.5V
I

vee

80

70
Vee'" S.SV

./

..:::--....

./

30

,/

50

o

->0
TA - AM81ENTTEMPERATURE -

100 200 300 400

'c

500 600 700 800 900 1000

LOAD CAPACITANCE - pF

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS SUPPLY VOLTAGE

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE

VCC-4.5~~

Vee'" S.OV

Vee

-f

~w,L

~

5.QV

Vc

=S.SV

vee'" S.OV
vee'" S:SV

TA '" +12SoC

-1.5

'/""
K

I
I

TA-+2S"C

--I--+-+-----1

TA=-55"C
-2.0
TA~t25C

YiN - INPUT VOLTAGE .. VOLTS

VIN

INPUT VOLT AGE • VOLTS

AC Test Load and Waveforms same as 93L420, see page 7-93, 7-94 "7-95.

7-103

•

TTL ISOPLANAR MEMORY 93L422
256x4-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93L422 is a 1024-bit Read/Write Random Access Memory organized 256 words by four bits per word. The 93L422 has 3-state outputs. and is designed primarily for buffer control storage and high-performance main memory applications. The device has a typical address access time of 45 ns.

•
•
•
•
•
•
•

TECHNO~ ~

6

f414

A.

(3)3

.,
.,

{21Z

1111
123)21

ISOPLANAR
ORGANIZATION - 256 WORDS X 4 BITS
3-STATE OUTPUTS
STANDARD 22-PIN DUAL IN-LINE PACKAGE
TWO CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
LOW POWER DISSIPATION - 0.27 mW/BIT TYP
TYPICAL READ ACCESS TIME - 45 ns

PIN NAMES
Ao- A 7
D1 - D4

LOGIC SYMBOL

fill 5

lei 6
(7)7

A,

.

93L422'

Ao

A,
A,

1810121418

12011101114111811181

Vee'" Pin 22 (241
GND '" Pin 8
( 1 ~ FLATPAK

CONNECTION DIAGRAMS
DIP (TOP VIEW)

Address Inputs
Data Inputs

Vee

A,
A,

Chip Select Inputs

CS1' CS2
WE

Write Enable Input

01 -04

Data Outputs

OE

Output Enable

es,

0,
0,

LOGIC DIAGRAM

0,
0,

We

®

'----'

es, @
CS, @
DE

@

A2

Vee ~ Pin 22
~

FLATPAK (TOP VIEW)

A'~~~llmJ~~~VCC
A,
WE

ROW
SELECT

GND

0,

Pin 8

O~ Pin Number

Pin numbers
specified for DIP only

7-104

~

AO

~1

AS

~

AS

CS2

~

~

0,

0,
03

~
0,
NC

~~~~ncE~~O'

~

FAIRCHILD ISOPLANAR TTL MEMORY. 93L422
FUNCTIONAL DESCRIPTION - The 93L422 is a fully decoded 1024-bit Random Access Memory organized 256 words
by four bits. Word selection is achieved by means of an 8-bit address, AO through A7.
Two Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select. CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable, WE (pin 20). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and chip selected.
Data in the specified location is presented at DOUT and not inverted.

TRUTH TABLE
INPUTS

OUTPUTS

OE
PIN 18

eS1
PIN 19

eS2
PIN 17

WE
PIN 20

D1 - D4
PINS 9. 11, 13 15

X
X
L
X

H
X
L

X
L
H

X
X
H

X
X
X

L

L

X

L

H
H

L

L
H

H

H

X

H
H

L
L

L
H

H
H
H

L
L
L

H = HIGH Voltage; L = LOW Voltage; X = Don't Care (HIGH or LOW); HIGH Z
NOTE: Pin numbers specified for DIP only

3-STATE

MODE

HIGH Z

Not Selected
Not Se lected
Read Stored Data
Write"O"
Write"1"

HIGH Z
HIGH Z
HIGH Z

Output Disabled
Write "0" (Output Disabled)
Write "1" (Output Disabled)

HIGH Z
HIGH Z
01 -04
HIGH Z

= High Impedance.

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Lead Potential to Ground Lead
Input Voltage (dc)*
Input Current (dc)*
Voltage Applied to Outputs (output HIGH)**
Output Current (dc)

-65°C to +150 0 C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0,5 V to +5.50 V
+20mA

*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.

**Output Current limit Required.

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (Vee!

PART NUMBER

AMBIENT TEMPERATURE
Note 4

MIN

TYP

MAX

93L422xe

4,75 V

5.0V

5.25 V

ooe to +75°e

93L422XM

4,50 V

5,OV

5.50 V

-55°C to +125°e

x

= package type;

F for Flatpak, D for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-105

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93L422
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1, 2, 4)
SYMBOL

LIMITS
TYP
(Note 3)

CHARACTERISTIC
MIN

VOL

Output LOW Voltage

V IH

Input HIGH Voltage

V IL

Input LOW Voltage

1.5

IlL

Input LOW Current

2.1

IIH

Input HIGH Current

V CD

Input Diode Clamp Voltage

10FF

Output Current
(HIGH Z)

V OH

Output HIGH
Voltage

lOS

Output Current
Short Circuit
to Ground

ICC

Power Supply
Current

0.3

UNITS

CONDITIONS

MAX
0.45

V

VCC = MIN, 10L = B mA

V

Guaranteed Input HIGH Voltage
for all Inputs

0.8

V

Guaranteed Input LOW Voltage
for all Inputs

-150

-300

/lA

VCC = MAX, V IN ~ 0.4 V

1.0

40

/lA

VCC = MAX, V IN = 4.5 V

1.0

mA

VCC = MAX, V IN = 5.25 V

1.6

--1.0

-1.5

V

VCC = MAX, liN = -10 mA

50

VCC = MAX, VOUT = 2.4 V

/lA

-50
2.4

VCC = MAX, VOUT = 0.5 V

V

-70

VCC = MIN, 10H = -5.2 mA

mA

VCC = MAX, Note 7

93L422XC

55

75

TA =+75°C

VCC = MAX,

93L422XC

60

80

TA = ooC

All Inputs and

93L422XM

50

70

TA = +125°C

Outputs Open

93L422XM

65

mA

TA = --55°C

90

AC CHARACTERISTICS: Over Guaranteed Operating Ranges (Notes 1, 2, 4, 5, 6)
93L422XM

93L422XC
SYMBOL

CHARACTERISTIC

MIN

TYP
MAX MIN
(Note 3)

TYP
MAX
(Note 3)

READ MODE

DELAY TIMES

tACS

Chip Select Time
Chip Select to HIGH Z
Output Enable Time

20

35

20

45

tZRCS
tAOS

20
20

35
35

20
20

45
45

tZROS
tAA

Output Enable to HIGH Z
Address Access Time

20
45

35
60

20
45

45
75

20
25

40
45

20
25

45
50

WRITE MODE

DELAY TIMES

tzws
tWR

Write Disable to HIGH Z
Write Recovery Time

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

Write Pulse Width (to guarantee write)
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

CI
Co

Input Pin Capacitance
Output Pin Capacitance

UNITS

ns

30
0
0
0
0
0
0
3
5

7-106

55
5
5
10
10
5
10
5

8

See Test Circuit
and Waveforms

35
0
0
0
0
0
0
3
5

See Test Circuit
and Waveforms

ns

INPUT TIMING REQUIREMENTS
45
5
5
10
5
5
5

CONDITIONS

ns

5

8

pF

Measure with
Pulse Technique

FAIRCHILD ISO PLANAR TTL MEMORY. 93L422
NOTES:
1. Conditions for testing, not shown in the Table. are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represent the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and sup·
ply voltage extremes. additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are atVcc~ 5.0V. TA~+25"C. and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range there is an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at maximum termperature are:
8JA (Junction to Ambient) (at 400 fpm air flow) = 50"C/Watt. Ceramic DIP; 65"C/Watt. Plastic DIP; NA. Flatpak.
8JA (Junction to Ambient) (still air) ~ 90"C/Watt. Ceramic DIP; 11 O"C/Watt. Plastic DIP; NA. Flatpak.
8JC (Junction to Case) ~ 25"C/Watt. Ceramic DIP; 25"C/Watt. Plastic DIP; 15"C/Watt. Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured attwSA == MIN, tWSA measured attw= MIN.
7. Duration of short circuit should not exceed one second.

TYPICAL ELECTRICAL CHARACTERISTIC CURVES
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH Z STATE)
9
8

, ,

~

,

TA~

TA- 25'e

5

TA~75'e

f-f--

I

,

~

I 3O"e

8

3
2

a

,

_: Ilr ,
0

2

3

,

vOUT - OUTPUT VOLTAGE

5

8

VOLTS

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

POWER SUPPLY CURRENT
VERSUS TEMPERATURE
80

"
~, "

~
a

~,
j

!l/
J '/

"ec-5.0"

TA-J5"C

"I-- I--

"r-

3

I//,I

., J

0

W

0.2

03

----

a sot--

i

.Q~

8

65

'fJ

TA-+125'C

9

"
~,
"
z

"

~ "

-

TA=r-SS"C

55

13

V CC B 4.5V
1

0.5

0.6

."

-so

0.'

~

~

~~

90

iii
~

,

~t- r-

"

."

~I"

-1.5

z

Y

:<

~
-0.5

a-\.o

V

: I

0

<

~

1

80

"Xl

"

'"

TA=55'C~

VCC-5.0V

."

-....

AMBIENT TEMPERATURE - 'c

0.5

,

;-- t-...... ~

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE

ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANC.E

f, , " o - f-

ce -5.0V-

so

"

0

'A

"OUT -OUTPUT VOLTAGE - VOLTS

110-

t

~r--.

"

"JO

0.'

Vcc-5.5V

-<.

TA:" +25'C ' : :

V

TA_1125 cl
o

l

I~

TA-+125'C

I

TA=+25·C
TA~

I

_55'C

-2.0

30 ......
-2.5

20
0

-1.0

100200 300400 500 600 700 800 900 1000'

'.0

3.0

5.0

'.0

9.0

'lIN - INPUT VOLTAGE - VOLTS

LOAO CAPACITANCE - pF

7-107

"

•

FAIRCHILD ISOPLANAR TTL MEMORYe93L422
AC TEST LOAD AND WAVEFORM
LOADING CONDITIONS

INPUT PULSES

T-X- --------'0:-ALL INPUT PULSES

Vcc
~

<

+ -

6000

DOUT

93422
93L422

I
I
"I - - - - - - - - r

3.5 V p.p

GND
93422
93L422

12000* 15 pF

lk!l

'5 pF

__I

1_10ns

__I

-

90

%

10%

1_10ns

t -~--------x-'"
__+_r - - - - - - - - ,3.5 V p.p

-

I

I

90%

Load B

Load A

GND

__I

I-lons

WRITE MODE

CSl. CS2
CHIP SELeCT

/ f\

AO-A7
ADDRESS

I 1\

J f\

/ 1\

(01 -041
DATA IN

/ f\

WE
WRITE ENABLE

tWSD-

.

J 1\

t-,w-l

--f\
-- -'-

/

-r-'WHO

I

-+---- tWSA-+-

......--tWHA - - - .

tWSCS------

tWHCS

LOAD B

~O.5V

.

•

-~'jr-

1\------;-nnn1
I

LOAD A

,~0.5V

I

(All above measurements referenced to 1.5 V unless otherwise indicated)
NOTE: Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-108

FAIRCHILD ISOPLANAR TTL MEMORY. 93L422

READ MODE
PROPAGATION DELAY
FROM CHIP SELECT

DATA
OUTPUTS

0,

04

PROPAGATION DELAY
FROM ADDRESS INPUTS

PROPAGATION DELAY
FROM OUTPUT ENABLE

OE~

AO

OUTPUT
ENABLE

A7

V

_AD_D_R_E_SS__-J~~___________

DATA
OUTPUTS

0,

- - tAA

I-r---

04

LOAD A

•

LOAD A

DATA
OUTPUTS

0,

04

LOAD B

7-109

TTL ISO PLANAR MEMORY 93422
256 x4-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93422 is a 1024-bit Read/Write Access Memory organized
256 words by four bits per word. The 93422 has 3-state outputs, and is designed
primarily for buffer control storage and high-performance main memory applications. The device has a typical address access time of 30 ns.
•
•
•
•
•
•
•

LOGIC SYMBOL

ISOPLANAR TECHNOLOGY
ORGANIZATION - 256 WORDS X 4 BITS
3-STATE OUTPUTS
STANDARD 22-PIN DUAL IN-LINE PACKAGE
TWO CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
POWER DISSIPATION - 0.475 mW/BIT TYPICAL
TYPICAL READ ACCESS TIME - 30 ns

PIN NAMES
AO-A7
D1 - D4
CS1,CS2
WE
01 - 04
OE

(1)1

(23)21

(6) 6

/717

18 10 12 14 16
(20) (10) (14)(16)(18)

Address Inputs
Data Inputs
Chip Select Inputs
Write Enable Input
Data Outputs
Output Enable

Vee

@

@

®

@

AO
0,

A3

ROW
SelECT

Pin 22 {241

CONNECTION DIAGRAMS
DIP (TOP VIEW)

@
@

A,

=-

GND ~ Pin 8
( (~FLATPAK

WE

CD

.,'"'0

(5) 5

@@@@

A2

.,"

(2) 2

LOGIC DIAGRAM

0
0

.,'0

(4) 4
(3)3

32)( 32

OUTPUT

MEMORY
ARRAY

DATA
CONTROL

02

03
04

A4

@
@
§
@

'3

Vee

'2

A.

A,

WE

AO

CSl

A,

DE

A.

CS2

A7

O.

GNO

O.

a,

03

0,

03

02

02

FLATPAK (TOP VIEW)

A3~~~~~~~~~~~~~VCC
We
~

~

A1

AO
~

COLUMN
SELECT

AS

Vee ~
GND

o

Pin 22
Pin 8
= Pin Number
~

7-110

~
CS2

A7
GND

04

~

~

O.

0'~~~n~~~D3

02

NC

Pill numbers
specified for DIP only

~1

02
NC

FAIRCHILD ISOPLANAR TTL MEMORY. 93422
FUNCTIONAL DESCRIPTION - The 93422 is a fully decoded 1024- bit Random Access Memory organized 256 words
by four bits. Word selection is achieved by means of an 8 - bit address, AO through A7.
Two Chip Select inputs are provided for logic flexibility. For larger memories, the fast chip select access time permits the
decoding of Chip Select, CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable, WE (pin 20). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected.
Data in the specified location is presented at DOUT and is not inverted.

TRUTH TABLE
INPUTS

H

OUTPUTS

OE
PIN 18

eS1
PIN 19

eS2
PIN 17

WE
PIN 20

D1 - D4
PINS 9,11,13,15

3·STATE

MODE

X
X
L
X
X

H
X
L
L
L

X
L
H
H
H

X
X
H
L
L

X
X
X
L
H

HIGH Z
HIGH Z
01 - 04
HIGH Z
HIGH Z

Not Selected
Not Selected
Read Stored Data
Write '"0"
Write '"1"

H
H
H

L
L
L

H
H
H

H
L
L

X
L
H

HIGH Z
HIGH Z
HIGH Z

= HIGH Voltage, L = LOW Voltage,

X

= Dan't Care (HIGH

or LOW); HIGH Z

Output Disabled
Write "0'" (Output Disabled)
Write '"1'" (Output Disabled)

=High Impedance.

NOTE: Pin number specified for DIP only

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
-65 aC to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5,5 V
-12 mA to +5.0 mA
-0,5 V to +5.50 V
+20mA

Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
'Input Voltage (de)
'Input Current (dc)
"Voltage Applied to Outputs (output HIGH)
Output Current (dc)
*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
HOutput Current Limit Required.

GUARANTEED OPERATING RANGES
MIN

SUPPLY VOLTAGE (Vee)
TYP

93422Xe

4.75 V

5.0 V

5.25 V

ooe \0 +75°e

93422XM

4.5

5.0 V

5.5 V

-55°e to +125°e

PART NUMBER

V

MAX

AMBIENT TEMPERATURE
Note 4

x = package type; F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-111

•

FAIRCHILD ISO PLANAR TTL MEMORY • 93422
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1. 2. 4)
SYMBOL

LIMITS
TYP
(Not,e 3)

CHARACTERISTIC
MIN

0,3

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

IlL

Input LOW Current

2,1

IIH

Input HIGH Current

VCD

Input Diode Clamp Voltage

IOFF

Output Current
(HIGH Z)

VOH

Output HIGH
Voltage

lOS

Output Current
Short Circuit
to Ground

ICC

0,45

CONDITIONS

V

VCC = MIN. IOL = B mA

V

Guaranteed Input HIGH Voltage
for all Inputs

0.8

V

Guaranteed Input LOW Voltage
for all Inputs

-150

-300

IlA

VCC = MAX. VIN = 0.4 V

1.0

40

IlA

VCC = MAX. VIN = 4,5 V

1.0.

mA

VCC = MAX. VIN = 5,25 V

V

VCC = MAX. IIN=-10mA

1.6

-1.0

-1.5
50

IlA

-50
2.4

V

-70

VCC = MAX. VOUT = 2.4 V
VCC = MAX. VO UT = 0,5 V
VCC = MIN. 10H = -5.2 mA

mA

VCC = MAX. Note 7

130

TA = +75°C

VCC= MAX.

93422XC

155

TA =ooC

All Inputs and

93422XM

120

TA = +125°C

Outputs Open

93422XM

170

93422XC
Power Supply
Current

UNITS
MAX

95

mA

TA = -55°C

AC CHARACTERISTICS: Over Guaranteed Operating Ranges (Notes 1 2 4 5 6)
93422XC
SYMBOL

CHARACTERISTIC

READ MODE

DELAY TIMES

tACS
tZRCS
tAOS
tZROS
tAA

Chip Select Time
Chip Select to HIGH Z
Output Enable Time
Output Enable to HIGH Z
Address Access Time

WRITE MODE

DELAY TIMES

tzws
tWR

Write Disable to HIGH Z
Write Recovery Time

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

Write Pulse Width (to guarantee write)
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

CI
Co

Input Pin Capacitance
Output Pin Capacitance

MIN

93422XM

TYP
MAX MIN
(Note 3)

TYP
MAX
(Note 3)

20
20
20
20
30

30
30
30
30
45

20
20
20
20

40

45
45
45
45
60

20
25

35
40

20
25

45
50

UNITS

ns

40

20
0
0
0
0
0
0
3
5

7-112

5
5
10
10
5
10
5
8

See Test Circuit
and Waveforms

30
0
0
0
0
0
0
3
5

See Test Circuit
and Waveforms

ns

INPUT TIMING REQUIREMENTS
30
5
5
10
5
5
5

CONDITIONS

ns

5
8

pF

Measure with
Pulse Technique

FAIRCHILD ISOPLANAR TTL MEMORY. 93422
NOTES:
1. Conditions for testing. not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represent the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system'operating ranges.
3. Typical values are at Vee = 5.0 V, TA == +25°C, and MAX loading.
4. The Temperature Rangesare guaranteed with transverse airflow exceeding 400 linear feet per minute. For military range there is an additional requirementof
a two minute warm - up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at maximum termperature are:
()JA (Junction toAmbient) (at 400 fpm air flow) = 50°C/Watt, Ceramic DIP; 65°C/Watt, Plastic DIP; NA, Flatpak.
OJA (Junction to Ambient)(still air) ~ 90°C/Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
()Jc(Junction to Case) = 25°C/Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 15°C/Watt, Flatpak.

5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at tWSA = MIN, tWSA measured at tw = MIN.
7. Duration of short circuit should not exceed one second.

TYPICAL ELECTRICAL CHARACTERISTIC CURVES

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH Z STATE)
1.0

L5.0 J

Vee

"•

~:A=+l:::~ ~

0-

ffi

"•

0

15r--

a:

12 r T A = +125°C

:>

:>

~ -0.5

~

0-

g -1.0
,

0-

:>
9-1.5

-2.0
-1.0

"

"..

...

:>

0

=~25°C

2.0

1.0

9

~

I
0-

6

:>

9
3.0

4.0

5.0

3
0

6.0

0.1

J

0.3

~ 130

z

~ 120

B110 r--r-a:

V

W

0.2

>-

.

~ 100

~

f

I
0.4

0.5

w 100

"•

;:: 90

a:
0

0
,

"
:;"

~ -0.5

k<-'l-'l,/

60

.'" r--

~ -1.0
u
0-

~

25

50

TA
TA

~

V

550~

-=+25 G C

TA - J25°C

TA -="t-125°C

~ TA ,,+25°e
I
~ TA -55°C
)

-1.5

,

,/

z

=

=

-2.0

40 / '
30
0

0

75

100

125

TA - AMBIENT TEMPERATURE - °e

isa:

I--

....... V

50

20

0.7

vcc - 5.0 V

80

--

"

!d 60
50
-50 -25

0

70

;-.r-:::-..:::::

70

0.5

110

::;

:tl'"

_ V c e =4.5V

INPUT CURRENT VERSUS
INPUT VOLTAGE
YERSUS TEMPERATURE

120

""
"ffi

12,

0.6

ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE

,

-r---~

~ 80 r--

TA~-55°e-

Vcc '- 5.5 V

-I----r<. ,<~15.ov

90

a:

VOUT - OUTPUT VOLTAGE - VOLTS

VOUT - OUTPUT VOLTAGE - VOLTS

~

~ 140

jV
~/

J V(

:>

~ TA ~1125°1
0

-I

0-

TA = -55°e
TA

T1 = +7l o c

0-

~

Il'

18

I
0-

ffi
a:

POWER SUPPLY CURRENT
VERSUS TEMPERATURE
150

IJ' /

Vec == 5.0 v
TA ",,1250c

0.5

,

a:
a:

2t

-2.5
-1.0

100 200 300 400 500 600 700 800900 1000

1.0

3.0

5.0

7.0

9.0

VIN - INPUT VOLTAGE - VOLTS

LOAD CAPACITANCE - pF

AC Test Load and Waveforms same as 93L422. see page 7-108.

7-113

110

•

TTL ISOPLANAR MEMORY 93L425
l024xl-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93L425 is a low power 1024-bit Read/Write Random Access
Memory organized 1024 words by one bit. It has a typical access time of 35 ns and is
designed for buffer and control storage and high-performance main memory applications requiring low power.

LOGIC SYMBOL
15

The 93L425 has full decoding on chip, separate Data Input and Data Output lines and
an active LOW Chip Select line. A 3-state output is provided to drive bus organized systems and/or highly capacitive loads. The 93L425 is fully compatible with standard
DTL and TTL logic families.
•
•
•
•
•
•
•
•
•

14

A1
A2
A3
A4

FULL MIL AND COMMERCIAL RANGES
3-STATE OUTPUT
NON-INVERTING DATA OUTPUT
ORGANIZED 1024 WORDS X 1 BIT
READ ACCESS TIME 35 ns TYPICAL
CHIP SELECT ACCESS TIME 20 ns TYPICAL
POWER DISSIPATION 250 mW TYPICAL
TTL INPUTS AND OUTPUTS
POWER DISSIPATION DECREASES WITH INCREASING TEMPERATURE

A5
10

A6

11

A7

12

AS

13

A9

93L425

Dour

vee = Pin 16
PIN NAMES
CS
AO-A9
WE

GND

= Pin 8

Chip Select Input
Address Inputs

DIN

Write Enable Input
Data Input

DOUT

Data Output

CONNECTION DIAGRAM
DIP (TOP VIEW)

LOGIC DIAGRAM

os

Vee

AO

DIN

A,

WE

A,

Ag

A3

AS

A,

A7

DOUT

A5

GND

A5

NOTE:
AO Al A2 A3 A4

vee = Pin 16

A5 A6 A7 AS Ag

0®0®® ®@@@l@

GND = Pin 8

o=

7-114

Pin Number

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n-Line Package.

FAIRCHILD ISOPLANAR TTL MEMORY. 93L425
FUNCTIONAL DESCRIPTION - The 93L425 is a fully decoded 1024- Bit Random Access Memoryorganized 1024wordsby
one bit. Word selection is achieved by means of a 10- bit address, AO through Ag.
The Chip Select input allows memory array expansion. For large memories, the fast chip select access time permits decoding of the Chip Select (CS) from the address without affecting system performance.
The read and write operations are controlled by the state of the active LOW Write Enable (WE, pin 14). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected. Data in the specified location is presented at DOUT and is non-inverted. During writing, the output is held in the high impedance state.
The 3-state output provides drive capability for higher speeds with high capacitive load systems The third state (high impedance) allows bus organized systems where multiple outputs are connected to a common bus.

TABLE 1 - TRUTH TABLE

H

INPUTS
es WE DIN

OUTPUT

H
L
L
L

HIGH Z
HIGH Z
HIGH Z

=

X
L
L
H

X
L
H
X

MODE

DOUT

DOUT

Not Selected
Write "0"
Write "1"
Read

HIGH Voltage Level

L ~ LOW Voltage Level
X ~ Don't Care (HIGH or LOW)
HIGH z~ High Impedance

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
-65°C to +150°C
-55°C to +125°C
-0.5 V to +7,0 V
-0.5 V to +5,5 V
-12 mA to +5,0 mA
0.5 V to +5.50 V
+20mA

Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
'Input Voltage (dc)
'Input Current (dc)
"Voltage Applied to Outputs (output HIGH)
Output Current (dc) (output LOW)
-Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (Vee)
PART NUMBER

AMBIENT TEMPERATURE
Note 4

MIN

TYP

MAX

93L425Xe

4.75 V

5.0V

5.25 V

ooe to +75°C

93L425XM

4,50 V

5.0V

5.50 V

-55°e to +125°e

x

= package type;

F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-115

•

FAIRCHILD ISO PLANAR TTL MEMORY. 93L425
DC CHARACTERISTICS' Over Operating Temperature Ranges Notes 1 2 and 4
PARAMETER

SYMBOL

MIN

LIMITS
TYP
(Note 3)

MAX

0.35

0.45

UNITS

CONDITIONS

V

VCC = MIN. 10L = 16 mA

V

Guaranteed Input HIGH Voltage
for all Inputs
Guranteed Input LOW Voltage
for all Inputs

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

V IL

Input LOW Voltage

1.5

0.8

V

IlL

Input LOW Current

-150

-300

pA

VCC = MAX. VIN = 0.4 V

1.0

40

pA

VCC = MAX. VIN = 4.5 V

1.0

mA

VCC

pA

VCC = MAX. VOUT = 2.4 V
VCC = MAX. VOUT = 0.5 V

mA

VCC = MAX. Note 7

2.1

1.6

Input HIGH Current

IIH

10FF

Output Current (HIGH Z)

50
-50

lOS

Qutput Current
Short Circuit to Ground

-100

VO H

Output HIGH 193L425XC
Voltage
93L425XM

VCD

Input Clamp Diode Voltage

ICC

I

2.4
2.4

V
V
-1.5

-1.0

Power Supply Current

45

V

MAX. VIN

5.25 V

10H = -5.2 mA, VCC = 5.0 V ±5%
10H- 5.2 mA, VCC - 5.0 V ±10%
VCC = MAX. liN = -10 mA

55

mA

TA;;' 75°C

65

mA

TA - ooC

75

mA

TA-

55°C

VCC= MAX.
All Inputs
Grounded

AC CHARACTERISTICS' Over Guaranteed Operating Ranges Notes 1 2 4 5 6
SYMBOL

CHARACTERISTIC

MIN

93L425XC
TYP
MAX
(Note 3)

MIN

93L425XM
MAX
TYP
(Note 3)

READ MODE
tACS

DELAY TIMES
Chip Select Access Time

20

40

20

45

tZRCS
tAA

Chip Select to HIGH Z

20

40

20

50

Address AccElsS Time

35

60

35

70

WRITE MODE
tzws

DELAY TIMES
Write Disable to HIGH Z

tWR

Write Recovery Time

20
20

45
45

20
20

45
55

tw

INPUT TIMING REQUIREMENTS
Write Pulse Width
(to guarantee write)

45

50

25

5

0

10

0

0

10

0

0

10

0

Address Hold Time

5

0

10

0

tWSCS

Chip Select Set-Up Time

5

0

10

0

tWHCS

Chip Select Hold Time

5

0

10

0

CI

Input Pin Capacitance
Output Pin Capacitance

Data Set-Up Time Prior to Write

tWHD

Data Hold Time After Write

tWSA

Address Set-Up Time

tWHA

Co

4

5

4

5

7

8

7

8

7-116

CONDITIONS

See Test Circuit
ns

and Waveforms

ns

See Test Circuit
and Waveforms

25

5
10

tWSD

UNITS

pF

FAIRCHILD ISOPLANAR TTL MEMORY. 93L425
NOTES:
1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represent the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at Vee = 5.0V. TA =+25'C. and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range there is an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typ·
ical thermal resistance values of the package at minimum termperature are:
eJA(Junction to Ambient)(at 400 fpm air flow) = 50'C/Watt. Ceramic DIP; 65°C/Watt. Plastic DIP; NA. Flatpak.
8JA (Junction toAmbient)(stili air) = 90°C/Watt. Ceramic DIP; 11 O'c/Watt, Plastic DIP; NA. Flatpak.
8JC (Junction to Case) = 25' C/Watt. Ceram ic DIP; 25' C/Watt. Plastic DIP; 10' C/Watt for Flatpak.
5. The MAX address access time is guaranteed to be thw "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at tWSA = MIN, tWSA measured at tw = MIN.
7. Duration of short circuit should not exceed one second.

AC TEST LOAD AND WAVEFORM
LOADING CONDITIONS

Vee
300n
.-----,DOUT

DOUT

t

93425
93425A
93L425

93425
93425A

30pF

n
600

93L425

t~n

30pF

-

Load A

Load B

INPUT PULSES

ALL INPUT PULSES

- - - - - 90 %
I

--------------1-

__ I

3.5

Vp~p - ~
-

-

- -

~ - \-

-

-

-

- -

-

-

-

- - -

-

-

-

-

-

- - - - -

-..,--11
I
I
GND
--.j
1.-- 10 ns

-

-

-

-

- 10 %

1_10ns

- - /-

-

- 10 %

~-

-

- 90 %

- -/-

II
I
I
--.j
1___ 10 ns

.-L

-=-

(All time measurements referenced to 1.5 V)

7-117

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93L425
AC WAVEFORMS
READ MODE

PROPAGATION DELAY FROM CHIP SELECT

PROPAGATION DELAY FROM ADDRESS INPUTS

~.-

Os

AO

~'--------

CHIP SELECT

X

Ag

ADDRESS INPUTS

I

I

,

DOUT
LOAD A

I
I

tACS- _ _

DOUT
LOAD B

~Hl...

_____

-,L

X

DOUT

....J

DATA OUTPUT

,

I

I

I

'AA

•

• I
I

I

WRITE MODE

-i

~

J

CHIP SELECT

AotoA.
ADDRESS INPUTS

~t

- - - - - I - - - J/

~f-

I\'-____________J/'I\'-_--i________

\
7~

DIN
DATA INPUT

_ _ _ _ _ _ _ _~--~--~

WE

/

7~

~ _ _ _ _ _ _ _ _ _ _ _ _J

~_ _+_--~-------------

------+---~---~-, ----~----

~.--

WRITE ENABLE

-~

~tWSD· \ ' -_ _-J/ ~tWHD·

_

_~tWHA-_

--~SA~twscs~~_

LOAD A
DOUT
DATA OUTPUT

HiGHZ--r-j===
l-t
-~~twHCS---

WR

LOAD B

-----HIGH Z

(All time measurements referenced to 1.5 V)
NOTE: Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long as the
worst case limits are not violated.

7-118

TTL ISO PLANAR MEMORY 93425/93425A
1024 X 1 -BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93425 and 93425A are 1024-bit Read/Write Random Access
Memories organized 1024 words by one bit_ They are designed for buffer control storage
and high-performance main memory applications_ The devices have typical address times
of 30 ns for the 93425 and 25 ns for the 93425A.

LOGIC SYMBOL

15

The 93425 and 93425A include full decoding on chip, separate Data Input and Data Output lines and an active LOW Chip Select and Write Enable_ They are fully compatible
with standard DTL and TTL logic families_ A 3-state output is provided to drive bus
organized systems and/or highly capacitive loads_
•
•
•
•

•
•
•
•

3-STATE OUTPUT
ORGANIZED 1024 WORDS X 1 BIT
TTL INPUTS AND OUTPUT - FULL 16 mA DRIVE CAPABILITY
TYPICAL READ ACCESS TIME
93425A
Commercial
25 ns
93425
Commercial
30 ns
93425
Military
40 ns
CHIP SELECT ACCESS TIME 15 ns TYPICAL
NON-INVERTING DATA OUTPUT
POWER DISSIPATION 0_5 mW/BIT TYPICAL
POWER DISSIPATION DECREASES WITH INCREASING TEMPERATURE

A,
A2
A3
A4
A5
10

A6

11

A7

12

AS

13

A9

CS

Chip Select
Address Inputs

WE

Write Enable

DIN
DOUT

Data Input
Data Output

93425/93425A

Dour

Vee=Pin16
GND=Pin8

PIN NAMES

AO- A9

CONNECTION DIAGRAMS
DIP (TOP VIEW)

cs

vee

Ao

DIN

A,

WE

A2

Ag

LOGIC DIAGRAM

AO A, A2 A3 A4

A5 A6 A7 AS Ag

00000

®@@@@

14

A3

AS

A4

A)

DOUT

A6

GND

A5

NOTE:
The Flatpak version has the same
Vee = Pin 16
GND = Pin 8

o = Pin Numbers
7-119

pinouts (Connection Diagram) as the
Dual In-Line Package.

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93425/93425A
FUNCTIONAL DESCRIPTION - The 93425/93425A are fully decoded 1024·bit Random Access Memories organized 1024
words by one bit. Word selection is achieved by means of a 10-bit address, AO through A9.
The Chip Select (CS) input provides for memory array expansion. For large memories, the fast chip select time permits the
decoding of chip select from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable (WE, Pin 14). With WE and CS held
LOW, the data at DIN is written into the addressed location. To read, WE is held HIGH and CS held LOW. Data in the specified location is presented at DOUT and is non-inverted.
The 3-state output provides drive capability for higher speeds with high capacitive load systems. The third state (high impedance) allows bus organized systems where mUltiple outputs are connected to a common bus.
During writing, the output is held in the high impedance state.

TABLE 1 - TRUTH TABLE
INPUTS

OUTPUT
MODE

CS

WE

DIN

DOUT

H

X

X

HIGH Z

NOT SELECTED

L

L

L

HIGH Z

WRITE "0"

L

L

H

HIGH Z

WRITE "1"

L

H

X

DOUT

READ

H = HIGH Voltage Level
L = Low Voltage Level
X = Don't care (HIGH or LOW)
HIGH Z = High Impedenee

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired.)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
'Input Voltage (dc)
'Input Current (dc)
"Voltage Applied to Outputs (Output HIGH)
Output Current (dc) (Output LOW)

_65°C to +150°C
_55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.5 V
+20mA

*Either input voltage or input current limit is sufficient to protect the input.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES
PART NUMBER

AMBIENT TEMPERATURE (TA)

SUPPLY VOLTAGE (VCC)
MIN

TYP

MAX

(Note 4)

93425XC, 93425AXC

4.75V

5.0 V

5.25 V

O°C to +75°C

93425XM

4.50 V

5.0 V

5.50 V

_550 C to +125° C

x = package type;

F for Flatpak, D for Ceramic DIP, P for Plastic DIP. See Packaging Information Section for packages available on this product.

7-120

FAIRCHILD ISOPLANAR TTL MEMORY. 93425/93425A
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1,2,41
SYMBOL

CHARACTERISTIC

LIMITS
MIN

TYP (Note 31

UNITS

MAX
0.45

0.3

CONDITIONS

= MIN,

10L = 16 rnA

V

VCC

V

Guaranteed Input HIGH Voltage for all Inputs

V

Guaranteed I nput LOW Voltage for all Inputs

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

0.8

IlL

I nput LOW Current

-250

-400

IJ-A

VCC - MAX, VIN - 0.4 V

Input HIGH Current

1.0

40

IJ-A

VCC - MAX, VIN - 4.5 V

IIH

1.0

rnA

VCC

1;6

2.1

50

Output Current (HIGH ZI

10FF

VCC

= MAX, VOUT = 0.5

rnA

VCC

= MAX, Note 7

2.4

V

10H

= -10.3

2.4

V

10H - -5.2 rnA

-100

to Ground

IL93425XC
93425XM

VOH

Output HIGH Voltage

VCD

Input Diode Clamp Voltage

V

-1.5

95

115

rnA

T A# 75°C

130

rnA

TA

145

rnA

TA

VCC

V

= 5.0 V

rnA, VCC

±5%

= MAX, liN = -10 rnA

-1.0

Power Supply Current

ICC

IJ-A

-50

Output Current Short Circuit
lOS

= MAX, VIN = 5.25 V

VCC - MAX, VOUT - 2.4 V

VCC

= O°C
= _55°C

= MAX,

All Inputs Grounded

AC CHARACTERISTICS: Over Guaranteed Operating Ranges (Notes 1,2,4,5,61
93425AXC
SYMBOL

CHARACTERISTIC

MIN

TYP

93425XC

MAX

MIN

(Note 31

TYP

93425XM

MAX

MIN

(Note 31

TYP

MAX

UNITS

CONDITIONS

(Note 31

READ MODE

DELAY TIMES

tACS

Chip Select Time

15

20

15

35

15

45

tZRCS

Chip Select to HIGH Z

15

20

20

35

20

50

tAA
WRITE MODE

Address Access Time

25

30

30

45

40

60

tzws

Write Disable to HIGH Z

15

20

20

35

20

45

twR

Write Recovery Time

20

25

25

40

45

50

tw

Write Pulse Width (to guarantee writel

20

15

35

25

40

25

tWSD

Data Set-Up Time Prior to Write

5

0

5

0

5

0

tWHD

Data Hold Time After Write

5

0

5

0

5

0

twSA

Address Set-Up Time

5

0

5

0

15

0

tWHA

Address Hold Time

5

0

5

0

5

0

twscs

Chip Select Set-Up Time

5

0

5

0

5

0

twHCS

Chip Select Hold Time

5

0

5

0

5

CI

Input Pin Capacitance

4

5

4

5

4

5

Co

Output Pin Capacitance

7

8

7

8

7

8

ns

See Test Circuit
and Waveforms

DELAY TIMES

-

ns

INPUT TIMING REQUIREMENTS

See Test Circuit
and Waveforms
ns

0
pF

Measure with

Pulse Technique

NOTES:
1. Conditions for testing, not shOVlIn in the Table, are chosen to guarantee operation under "worst case" conditions.

2. The specified LI M ITS represent the "worst case" value to the parameters. Since these "worst case" values normally occur at the temperature
and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical limits are at VCC =: 5.0 V, TA "'" +25°C, and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range there is an addi~
tional requirement of two minute warm-up. Temperature range of operation refers to case temperature for F latpaks and ambient temperature
for all other packages. Typical thermal resistance values of the package at maximum termperature are:
(J JA (Junction to Ambient) (at 400 fpm air flow) = 50°C/Watt, Ceramic DIP, 65°C/Watt, Plastic DIP; NA, Flatpak.

8 JA (Junction to Ambient) (still air) = 90o C/Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
0JC(Junction to Case) == 25°C/Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 10°C/Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
6. tw measured at t WSA = MIN, t WSA measured at tw = MIN.
7. Duration of short circuit should not exceed one second.

7-121

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93425/93425A
TYPICAL ELECTRICAL CHARACTERISTICS

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE
0.5

vee

E

TA

."

~ -0.5

Vee'" S.OV

,,"+~25OC

'"E
""=>

~ -1.0

">-

"-

TA "'+125°C

~

I

=
'" -2.0

Vee

=

5.5 V

e 4.5 V

Vee = s.ov
""""'vee = S.SV

Y
....:1.0

"

~

I

f--- TA -o-·---25°C

-15

f/!!;ee

A

~O.5

>z

'a:w"
~

veee4.5~~

TA =+25°C

V

..:

0.5

TA"-550~y

J5.0 V

o

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS SUPPLY VOLTAGE

~

I

-15

~

TA = -55°C

-2.0
TA = +25 C

-2.5
--1.0

1.0

3.0

5.0

7.0

9.0

I

-2.5
-1.0

11.0

VIN - INPUT VOLTAGE - VOLTS

7.0

11

9.0

VIN -INPUT VOLTAGE - VOLTS

INPUT THRESHOLO
VOLTAGE VERSUS
TEMPERATURE
2.5

5.0

3.0

1.0

POWER SUPPLY CURRENT
VERSUS TEMPERATURE
200

Ve~ 5.~V

Vde

0

0

JAX

I

I

ALL INPUTS GROUND

2.0
w

I-..

"~

§;

1.5

l- t- t-.

S

~

...

,.....

0

l"- t-

1,0

l'

0

f'.

">~
~

o. 5
SLOPE

o
-80

-20

20

60

100

0
-60

140

T J - JUNCTION TEMPERATURE -"C

=0

-0.25 mArc (25°C - 100°C)

-20

20

60

100

T J - JUNCTION TEMPERATURE - °C

AC Test Load and Waveforms same as 93L425, see page

7-122

7~117.

140

93427
ISOPLANAR SCHOTTKY TTL MEMORY
256x4-BIT PROGRAMMABLE READ ONLY MEMORY

DESCRIPTION - The 93427 is a fully decoded high-speed 1024·bit field Programmable
ROM organized 256 words by four bits per word. The 93427 has 3·state outputs. The
outputs are disabled when either CS1 or CS2 are in the HIGH state. The 93427 is supplied with all bits stored as logic "1 "s and can be programmed to logic "O"s by following the field programming procedure.

•
•
•
•
•
•
•
•
•

FULL MIL AND COMMERCIAL RANGES
FIELD PROGRAMMABLE
ORGANIZED 256 X 4 BITS PER WORD
3-STATE OUTPUTS
FULLY DECODED - ON·CHIP ADDRESS DECODER AND BUFFER
CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
WIRED-OR CAPABILITY
STANDARD 16-PIN DUAL IN-LINE PACKAGE
NICHROME FUSE LINKS - FOR HIGH RELIABILITY

LOGIC SYMBOL

15

12

11

10

9

PIN NAMES
Address Inputs

AO-A7
CS1,CS2

Chip Select Inputs,

Vee = Pin 16

01 - 04

Data Outputs

GND = Pin 8

LOGIC DIAGRAM

CONNECTION DIAGRAM
DIP (TOP VIEW)
1024 BIT CELL
32 X 32
MEMORY MATRIX

G)A2-----------1

CD

A,

------------1

o Ao------------I

A6

vee

A5

A,

A4

K--

)K

--~"·1 '\A> }';...-____-'-~.:..I---,'A::::A=--_{'-_ _ _ __

--OU-TP-U-T

AC TEST OUTPUT LOAD

5.0 V

15 rnA Load
Fig. 1

7-125

•

93436
ISOPLANAR SCHOTTKY TTL MEMORY
512x4-BIT PROGRAMMABLE READ ONLY MEMORY

DESCRIPTION - The 93436 is a fully decoded high-speed 204S-bit field Programmable
ROM organized 512 words by four bits per word. The 93436 has uncommitted collector
outputs. The outputs are off when the CS input is in the HIGH state. The 93436 is supplied with all bits stored as logic "1 "s and can be programmed to logic "O"s by following
the field programming procedure.
•

FAST ADDRESS ACCESS TIME - 30 ns TYP

•
•
•
•
•
•
•
•
•
•

FULL MIL AND COMMERCIAL RANGES
FIELD PROGRAMMABLE
ORGANIZATION - 512 WORDS X 4 BITS
UNCOMMITTED COLLECTORS - 93436
FULLY DECODED - ON-CHIP ADDRESS DECODER AND BUFFER
CHIP SELECT INPUT PROVIDES EASY MEMORY EXPANSION
WIRED-OR CAPABILITY
STANDARD 16-PIN DUAL IN·LlNE PACKAGE
NICHROME FUSE LlNKS.FOR HIGH RELIABILITY
REPLACES TWO 256 x 4 PROMS - DOUBLE DENSITY WITH SAME SPACE AND POWER

LOGIC SYMBOL

'3

AO
A,

CS

A2
A3
A4

93436

A5
A6
'5
,4

A7
AS

PIN NAMES
,2

Address Inputs
Chip Select Input
Data Outputs

AO- AS
CS
01- 04

"

,0

VCC""Pin16
GND = Pin 8

LOGIC DIAGRAM

1-0F-32
DECODER

CONNECTION DIAGRAM
DIP(TOP VIEW)

2048-BIT CELL
64X 32
MEMORY MATRIX

(DA2-----------4
A'-------I
Ao-----------4

®

GD

o=

@

VCC--,

®

GND---:L

0,

®

Pin Numbers

7-126

A6

vee

A5

A7

A4

A8

A3

os

AO

0,

A,

O2

A2

°3

GNO

°4

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY· 93436
FUNCTIONAL DESCRIPTION - The 93436 is a bipolar field Programmable Read Only Memory (PROM) organized 512
words by four bits per word. Open collector outputs are provided on the 93436 for use in wired·OR systems. Chip Select is
active LOW; i.e., a HIGH (logic "1 ") on the CS pin will disable all outputs.
The read function is identical to that of a conventional bipolar ROM. That is, a binary address is applied to the AO through
A8 inputs, the chip is selected, and data is valid at the outputs after tAA nanoseconds.
Programming (selectively opening nichchrome fuse links) is accomplished by following the sequence outlined below.

PROGRAMMING - The 93436 is manufactured with all bits in the logic "1" state. Any desired bit (output) can be program·
med to a logic "0" state by following the procedure shown in Chapter 6, page 6 -14.
.

ABSOLUTE MAXIMUM RATINGS
-65"C to +150"C
-55" C to +125" C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
100 mA
-0.5 V to 4.0 V

Storage Temperature
Temperature (Ambient) Under Bias

VCC
Input Voltages
Current Into Output Terminal
Output Voltages

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (VCC)

PART NUMBER

MIN

TYP

MAX

93436XC,

4."/5 V

5.0 V

5.25 V

93436XM,

4.50 V

5.0 V

5.50 V

x

=;

--

AMBIENT TEMPERATURE
O"C to +75"C
-55"C

to

+125"C

package type; F for Flatpak, 0 for Ceramic DIP, P for Plastic DIP. See Package Information on this data sheet.

DC CHARACTERISTICS: Over guaranteed operating ranges unless otherwise noted.

LIMITS
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNITS

CONDITIONS

(Note 1)
ICEX

Output Leakage Current

50

~A

ICEX

Output Leakage Current

100

~A

VOL

Output LOW Voltage

0.45

V

VIH

Input HIGH Voltage

VIL

I nput LOW Voltage

2.0
0.8

VCC - MIN, IOL - 16 mA, AD - +10.8 V
Al through A8 = HIGH
Guaranteed Input HIGH Voltage for All Inputs

V

Guaranteed Input LOW Voltage for Alt Inputs

-250

~A

-160

-250

~A

IRA (Address Inputs)

40

~A

IRCS (Chip Select Input)

40

~A

VCC = MAX, VF = 0.45 V

I FA (Address Inputs)
IFCS (Chip Select Inputs)

VCC = MAX, VCEX = 4.0 V, _55°C to +125°C
Address any HIGH Output

V
-160

I nput LOW Current
IF

0.30

VCC = MAX, VCEX = 4.0 V, DoC to +75°C
Address any HIGH Output

Input HIGH Current
IR

ICC

Power Supply Current

95

Co

Output Capacitance

7.0

CIN

I nput Capacitance

4.0

Vc

Input Clamp Diode Voltage

130

-1.2

7-127

mA

VCC = MAX, VR

=

2.4 V

VCC = MAX, Outputs open

Inputs Grounded and Chip Selected

pF

VCC = 5.0 V, Vo = 4.0 V, f = 1.0 MHz

pF

VCC = 5.0 V, Vo = 4.0 V, f = 1.0 MHz

V

Vec = MIN, IA = -18 mA

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY· 93436
AC CHARACTERISTICS: T A
SYMBOL
tAA-

~

DoC to +75°C. VCC

~

5.0 V

i

5%.
LIMITS

CHARACTER ISTIC

MIN

TYP (Note 1)

MAX

Address to Output Access Time

tAA+
tACS-

Chip Select Access Time

30

50

ns

30

50

ns

15

25

ns

25

ns

15

tACS+

UNITS

CONDITIONS

See Figure 1

AC CHARACTERISTICS: TA ~ _55°C to +125°C. VCC ~ 5.0 V ± 10%.
LIMITS

CHARACTERISTIC

SYMBOL

TYP (Note 1)

MIN

Address to Output Access Time
Chip Select Access Time
Note 1:

Typical values are at VCC ~ 5.0 V.

+250

MAX

UNITS

30

60

ns

30

60

ns

15

30

ns .

15

30

ns

CONDITIONS

See Figure 1

C and max loading.

AC WAVEFORM AND TEST OUTPUT LOAD

-=-t-J
CHIP SELECT

t-.AA_-=l--

't~cs~-----------t=tACS+

-OU-TP-UT---------~~------------=%-----

5.0V

RL2

600 n

15 rnA Load

Fig. 1

7-128

93438
ISOPLANAR SCHOTTKY TTL MEMORY
512x8-BIT PROGRAMMABLE READ ONLY MEMORY

DESCRIPTION - The 93438 is a fu,lly decoded 4096-bit field Programmable ROM organized 512 words by eight bits per word. The 93438 has uncommitted collector outputs.
The device is enabled when CS1 and CS2 are LOW and CS3 and CS 4 are HIGH. The
93438 is supplied with all bits stored as logic "1 "s and may be programmed to logic "O"s
by following the field programming procedure.

• FULL MIL AND COMMERCIAL RANGES
• FIELD PROGRAMMABLE
• ORGANIZATION - 512 WORDS X 8 BITS
• UNCOMMITTED COLLECTORS
• FULLY DECODED - ON-CHIP ADDRESS DECODER AND BUFFER
• CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
• WIRED-OR CAPABILITY
• STANDARD 24-PIN DUAL IN-LINE PACKAGE
• NICHROME FUSE LINKS FOR HIGH RELIABILITY

LOGIC SYMBOL

CS1 CS2 eS3 eS4
21 20 19 18

AO
A1
A2
A3
9343S

A4

4

A5
AS
A7
23

AS 01 02 030405 06 07 Os

PIN NAMES
9 10 11 13 14 15 16 17

AO-AS
CS1. CS2. CS3. CS4

01- Os

Address Inputs
Chip Select Inputs
Data Outputs

LOGIC DIAGRAM

Pin 24

~

Pin 12

A7

vee

AS

As

A5

Ne

A4

CS1

0 A ,------1

Aa

CS2

G)A,-----j

A2

CS3

0"0------1

A1

eS4

Ao

Os

® os,
@ CS3

@ cs,

-;=~~~+-~~-~-,-+-~~-~-,-+--,

CS4

@ Vcc----,
@GND~

o

~

CONNECTION DIAGRAM
DIP (TOP VIEW)

4096-BIT CELL
64X 64
MEMORY MATRIX

@

Vee
GND

01

07

02

06

03

05

GND

04

NOTE:
The Flatpak version has the same
pinouts (Conne~tion Diagram) as the
Dual In-Line Package.

0,
= Pin Numbers

7-129

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93438
ABSOLUTE MAXIMUM RATINGS

_65°C to +150°C
_55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
100 mA
-0.5 V to 4.0 V

Storage Temperature
Temperature (Ambient) Under Bias
VCC
Input Voltage
Current into Output Terminal
Output Voltages

GUARANTEED OPERATING RANGES
AMBIENT
TEMPERATURE

MIN

SUPPLY VOLTAGE (VCC)
TYP

MAX

93438XC

4.75 V

5.0V

5.25 V

OOC to +75°C

93438XM

4.50 V

5.0V

5.50 V

-55°C to +125°C

PART NUMBERS

x=

package type; F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

FUNCTIONAL DESCRIPTION - The 93438 is a bipolar field Programmable Read Only Memory (PROM) organized 512
words by eight bits per word. Open collector outputs are provided on the 93438 for use in wired-OR systems. Chip Select
follows the logic equation: CSl • CS2' CS3' CS4 = CS; i.e., if CS1 and CS2 are both active LOW and CS3 and CS 4 are both
active HIGH, all eight outputs are enabled; for any other condition all eight outputs are disabled.

The read function is identical to that of a conventional bipolar ROM. That is, a binary address is applied to the AO through
A8 inputs, the chip is selected, and data is valid at the outputs after tAA nanoseconds.
Programming (selectively opening nichrome fuse links) is accomplished by following the procedure in Chapter 6, page 6 -14.

DC CHARACTERISTICS' Over guaranteed operating ranges unless otherwise note
LIMITS
SYMBOL

ICEX
ICEX

VOL

CHARACTERISTIC

MIN

TYP
(Note 1)

Output Leakage Current
Output Leakage Current

0.30

Output LOW Voltage

MAX

UNITS

CONDITIONS

50

J1A

VCC = MAX, V CEX = 4.0 V, ODC to +75°C
Address any HIGH Output

100

J1A

VCC = MAX, VCEX = 4.0 V. -55 DC to +125° C
Address any HIGH Output

0.45

V

VCC = MIN, 10L = 16 mA
AO = +10.8 V, Al - A8 = HIGH

V

Guaranteed Input HIGH Voltage for All Inputs

V

Guaranteed Input LOW Voltage for All Inputs

--f--------

V IH

Input HIGH Voltage

V IL

Input LOW Voltage

IF

Input LOW Current
IFA (Address Inputs)
IFCS (Chip Select Inputs)

IR

Input HIGH Current
IRA (Address Inputs)
IRCS (Chip Select Input)

ICC

Power Supply Current

2.0
0.8
-160
-160

130

-250
-250

J1A
J1A

VCC = MAX, V F = 0.45 V

40
40

J1A
J1A

Vec - MAX. V R = 2.4 V

175

mA

Vec = MAX, Outputs Open
Inputs Grounded and Chip Selected
~e=~0~Vo=~0~f=10M~

Co

Output Capacitance

7

pF

CIN

Input Capacitance

4

pF

Vc

Input Clamp Diode Voltage

-1.2

7-130

V

~C=~0~VO=~0~f=10M~

VCC = MIN, IA = -18 mA

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY • 93438
AC CHARACTERISTICS: TA = O°C to +75°C, VCC = 5.0 V ±5%

SYMBOL

CHARACTERISTIC

MIN

LIMITS
TYP
(Note 1)

MAX

UNITS

tAAtAA+

Address to Output Access Time

35
35

55
55

ns
ns

tACStACS+

Chip Select Access Time

15
15

25
25

ns
ns

LIMITS
TYP
(Note 1)

MAX

UNITS

CONDITIONS

See Figure 1

AC CHARACTERISTICS: TA = -55°C to +125°C, VCC = 5.0 V ±1 0%

SYMBOL

CHARACTERISTIC

MIN

tAAtAA+

Address to Output Access Time

35
35

70
70

ns
ns

tACStACS+

Chip Select Access Time

15
15

30
30

ns
ns

Note (1 ): Typical values are at Vee

CONDITIONS

See Figure 1

= 5,0 V, +250 C and max loading.

ACWAVEFORM

ADDRESS

OUTPUT
CS,

CS2,

CHIP SELECT

d<'M

d<'AA' F
3

- - - - - - I(- -

r

+1.5 V

CS3 CS4..-/

-\:-----

OUTPUT
__

--

tACS-~

AC TEST OUTPUT LOAD
5.0

v

RLl

30011

RL2

600 H

OUTPUT

15 0F±

-=
t5 rnA Load

Fig. 1

7-131

-++1.5V
tACS+

•

93446
ISOPLANAR SCHOTTKY TTL MEMORY
512x4-BIT PROGRAMMABLE READ ONLY MEMORY

DESCRIPTION - The 93446 is a fully decoded high-speed 204S-bit field Programmable
ROM'organized 512 words by four bits per word. The 93446 has 3-state outputs. The
outputs are off when the CS input is in the HIGH state. The 93446 is supplied with all
bits stored as logic "l"s and can be programmed to logic "O"s by following the field programming procedure.
•
•
•
•
•
•
•
•
•
•
•

FAST ADDR ESS ACCESS TIM E - 30 ns TYP
FULL MIL AND COMMERCIAL RANGES
FIELD PROGRAMMABLE
ORGANIZATION - 512 WORDS X 4 BITS
3·STATE OUTPUTS
FULLY DECODED - ON·CHIP ADDRESS DECODER AND BUFFER
CHIP SELECT INPUT PROVIDES EASY MEMORY EXPANSION
WIRED-OR CAPABILITY
STANDARD 16-PIN DUAL IN-LINE PACKAGE
NICHROME FUSE LINKS FOR HIGH RELIABILITY
REPLACES TWO 256 x 4 PROMS - DOUBLE DENSITY WITH SAME SPACE AND POWER

LOGIC SYMBOL

'3

AD
S

AI

7

A2

4

A3

CS

A4

93446

AS
AS
15

A7

14

AS 0,

PIN NAMES
12

Ao-AS
CS

Address Inputs
Chip Select Input
Data au tpu ts

01- 04

@As
@A7
A6

o0 A4
A5

0

0

®

1 OF 64

DECODER

10

Vee == Pin 16
GND=Pin8

LOGIC DIAGRAM

CD

11

CONNECTION DIAGRAM
DIP(TOP VIEW)
64X32
MEMORY MATRIX

A3

A6

vee

A5

A,

A2 - - - - - - I

A,

AS

A'------i

A3

cs

AD

0,

A,

°2

A2

°3

GNO

0,

QDAO-----~

~~-~~-~---~~---~----,
@ vcc---,

®

NOTE:

GND--:J...

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

03

0= Pin Numbers

@

7-132

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY· 93446
FUNCTIONAL DESCRIPTION - The 93446 is a bipolar field Programmable Read Only Memory (PROM) organized 512
words by four bits per word. The 93446 has 3-state outputs which provide active pull-ups when enabled and high output
impedance when disabled. Chip Select is active LOW; i.e., a HIGH (logic "1") on the CS pin will disable all outputs.
The read function is identical to that of a conventional bipolar ROM. That is, a binary address is applied to the AO through
AS inputs, the chip is selected, and data is valid at the outputs after tAA nanoseconds.
Programming (selectively opening nichchrome fuse links) is accomplished by following the sequence outlined below.
PROGRAMMING - The 93446 is manufactured with all bits in the logic "1" state. Any desired bit (output) can be program·
med to a logic "0" state by following the procedure shown in Chapter 6, page 6 -14.

ABSOLUTE MAXIMUM RATINGS
-65"C to +150"C
-55"C to +125"C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
100 mA
-0.5 V to 4.0 V

Storage Temperature
Temperature (Ambient) Under Bias

VCC
Input Voltages
Current Into Output Terminal
Output Voltages

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (VCC)

PART NUMBER

AMBIENT TEMPERATURE

MIN

TYP

MAX

93446XC

4.75 V

5.0 V

5.25 V

DoC to +75"C

93446XM

4.50 V

5.0 V

5.50 V

-55"C to +125"C

x = package type; F for Flatpak, 0 for Ceramic DIP, P for Plastic DIP. See Package Information on this data sheet.

DC CHARACTERISTICS: Over guaranteed operating ranges unless otherwise noted.
LIMITS
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNITS

0.45

V

CONDITIONS

(Note 1)
VOL

Output LOW Voltage

VOH

Output HIGH Voltage

0.30

V

2.4

Output Leakage Current for
loll
loff

50

}J.A

VCC ~ MIN, IOL ~ 16 mA, AD
Al through AS ~ HIGH
VCC

~

~

HIGH Impedance State

-50

}J.A

VOL

Output Leakage Current for

100

}J.A

VOH~2.4V

HIGH Impedance State

-50

}J.A

VOL~O.4V

VIH

Input HIGH Voltage

VIL

I nput LOW Voltage

2.0
O.S

~

MIN. IOH

VOH~2.4V

~

+10.S V

-2.0 mA

0"Cto+75"C

0.4 V
-55°C to +125°C

V

Guaranteed Input HIGH Voltage lor All Inputs

V

Guaranteed Input LOW Voltage for All Inputs

I nput LOW Current
IF

IFA (Address Inputs)

-160

-250

}J.A

I FCS (Chip Select Inputs)

-160

-250

}J.A

IRA (Address Inputs)

40

gA

IRCS (Chip Select Input)

40

gA

130

mA

MAX. VF

~

0.45 V

VCC = MAX, VR

~

2.4 V

VCC

~

Input HIGH Current
IR

VCC = MAX, Outputs open

ICC

Power Supply Current

Co

Output Capacitance

7

pF

VCC = 5.0 V, Va = 4.0 V, I

~

1.0 MHz

CIN

Input Capacitance

4

pF

VCC = 5.0 V, Va

~

1.0 MHz

Vc

Input Clamp Diode Voltage

V

VCC ~ MIN, IA = -lS mA

95

-1.2

7-133

Inputs G rounded and Chip Selected
~

4.0 V, I

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY· 93446
AC CHARACTERISTICS: T A
SYMBOL

=

OuC to +75°C, VCC

=

5.0 V ± 5%.
LIMITS

CHARACTER ISTIC

tAA-

TYP (Note 1)

MIN

30

Address to Output Access Time

tAA+
tACS-

Chip Select Access Time

tACS+

AC CHARACTERISTICS: TA
SYMBOL

=

_55°C to +125°C, VCC

CHARACTERISTIC

= 5.0

Typical values are at V CC

50

ns

25

ns

15

25

ns

See Figure 1

V ± 10%.
LIMITS
TYP (Note 1)

MIN

UNITS

MAX

CONDITIONS

ns

30

60
60

15

30

ns

30

ns

30

15

= 5.0 V, +25 0 C and

50

15

Chip Select Access Time

tACS+
Note 1:

CONDITIONS

ns

30

Address to Output Access Time
tACS-

UNITS

MAX

ns

See Figure 1

max loading.

AC WAVEFORM AND TEST OUTPUT LOAD

-~::-t">J
CHIP SELECT

)b:-'AA_=l--

~:=-----------t='ACS+

--~~

-OUTPUT

==}-

____________

5.0V

RLl

300.11

RL2

600.n

15 mA Load

Fig. 1

7-134

93448
ISOPLANAR SCHOTTKY TTL MEMORY
512x8-BIT PROGRAMMABLE READ ONLY MEMORY

DESCRIPTION - The 93448 is a fully decoded 4096-bit field Programmable ROM organized 512 words by eight bits per word_ The 93448 has 3-state outputs_ The device is
enabled when CS1 and CS2 are LOW and CS3 and CS4 are HIGH. The 93448 is supplied
with all bits stored as logic "1 "s and may be programmed to logic "O"s by following the
field programming procedure.

•
•
•
•
•
•
•
•
•
•

FULL MIL AND COMMERCIAL RANGES
FIELD PROGRAMMABLE
ORGANIZATION - 512WORDS X 8 BITS
3-STATE OUTPUTS
FULLY DECODED - ON-CHIP ADDRESS DECODER AND BUFFER
CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
WIRED-OR CAPABILITY
STANDARD 24-PIN DUAL IN-LINE PACKAGE
NICHROME FUSE LINKS FOR HIGH RELIABILITY
REPLACES TWO 256 X 8 PROMs - DOUBLE DENSITY WITH SAME SPACE AND
POWER

LOGIC SYMBOL

CS1 CS2 eS3 eS4
21 20 19 18

AO
A1
A2
A3
93448

A4
A5
AS
A7
Aa

23

PIN NAMES
9 10 11 13 14 15 16 17

AO-A8
CS1. CS2. CS3. CS4

01- 0 8

Address Inputs
Chip Select Inputs
Data Outputs

·Vee

LOGIC DIAGRAM

CONNECTION DIAGRAM
DIP (TOP VIEW)
A7

4096·61T CELL

64 X 64
MEMORY MATRIX

Vce

A6

Aa

A5

Ne

A4

CS1

0 A, - - - - - I

A3

CS2

0

A2

eS3

A1

eS4

AO

Oa

A

'-----I

o Ao-----I

@ CSI
@ os,

01

07

®

CS3

@

C54

02

Os

03

05

GND

04

@ Vee----,
@GND~

o=

= Pin 24

GND = Pin 12

0,

Pin Numbers

@

7-135

o

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93448
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Temperature (Ambient) Under Bias

-65°C to +150°C
_55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
100mA
-0.5 V to 4.0 V

Vee
Input Voltage
Current into Output Terminal
Output Voltages
GUARANTEED OPERATING RANGES

AMBIENT
TEMPERATURE

MIN

SUPPLY VOLTAGE (Vee)
TYP

93448xe·

4.75 V

5.0V

5.25 V

O°C to +75°C

93448XM

4.50 V

5.0V

5.50V

-55°C to +125°C

PART NUMBERS

x

= package type;

MAX

F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

FUNCTIONAL DESCRIPTION - The 93448 is a bipolar field Programmable Read Only Memory (PROM) organized 512
words by eight bits per word. The 93448 has 3-state outputs which provide active pull-ups when enabled and high output
impedance when disabled. Chip Select for both devices follows the logic equation: CSl • CS2. CS3. CS4 = CS; i.e., if CSl
and CS2 are both active LOW and CS3 and CS4 are both active HIGH, all eight outputs are enabled; for any other condition
all eight outputs are disabled.
The read function is identical to that of a conventional bipolar ROM. That is, a binary address is applied to the AO through
A8 inputs, the chip is selected, and data is valid at the outputs after tAA nanoseconds.
Programming (selectively opening nichrome fuse links) is accomplished by following the procedures in Chapter 6, page 6-14 ..

DC CHARACTERISTICS' Over guaranteed operating ranges unless otherwise note
SYMBOL

VOL

CHARACTERISTIC

MIN

Output LOW Voltage

LIMITS
TYP
(Note 1)

MAX

UNITS

0.30

0.45

V

2.4

CONDITIONS
VCC = MIN, IOL = 16 mA
AO = +10.8 V, Al - A8 = HIGH

VOH

Output HIGH Voltage

loff

Output Leakage Current for HIGH
Impedance State

50
-50

pA
pA

VOH = 2.4 V
VOL =0.4V

ooC to +75°C

loff

Output Leakage Current for HIGH
Impedance State

100
-50

pA
pA

VOH = 2.4 V
VOL = 0.4 V

-55°C to +125°C

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

IF

Input LOW Current
IFA (Address Inputs)
IFCS (Chip Select Inputs)

IR

Input HIGH Current
IRA (Address Inputs)
IRCS (Chip Select Input)

ICC

Power Supply Current

V

V

Guaranteed Input HIGH Voltage for All Inputs

0.8

V

Guaranteed Input LOW Voltage for All Inputs

-250
-250

pA
pA

VCC = MAX, VF = 0.45 V

40
40

pA
pA

VCC = MAX, V R = 2.4 V

175

mA

VCC = MAX, Outputs Open
Inputs Grounded and Chip Selected

2.0

-160
-160

130

. VCC = MIN, IOH = -2.0 mA

Co

Output Capacitance

7

pF

VCC = 5.0 V, Vo = 4.0 V, f = 1.0 MHz

CIN

Input Capacitance

4

pF

VCC = 5.0 V, Vo = 4.0 V, f = 1.0 MHz

Vc

Input Clamp Diode Voltage

V

VCC = MIN, IA = -18 mA

-1.2

7-136

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93448
AC CHARACTERISTICS: TA = O°C to +75°C, VCC = 5.0 V ±5%

SYMBOL

CHARACTERISTIC

MIN

LIMITS
TYP
(Note 1)

MAX

UNITS

tAAtAA+

Address to Output Access Time

35
35

55
55

ns
ns

tACStACS+

Chip Select Access Time

15
15

25
25

ns
ns

LIMITS
TYP
(Note 1)

MAX

UNITS

AC CHARACTERISTICS: TA

SYMBOL

= -55°C

to +125°C, VCC

CHARACTERISTIC

See Waveforms
and Test Circuits

= 5.0 V ±10%
MIN

tAAtAA+

Address to Output Access Time

35
35

70
70

ns
ns

tACStACS+

Chip Select Access Time

15
15

30
30

ns
ns

Note (1 l: Typical values are at VCC

CONDITIONS

CONDITIONS

See Waveforms
and Test Circuits

= 5.0 V, 5.0 V, +25 0 C and max loading.

SWITCHING WAVEFORMS

ADDRESS

~

-:~r'tAA+ r,--1

OUTPUT
CS,
CHtPSELECT

CS2,

_-::::-:-=_-;-__""-:: -

-

-

-

-

-

Ij(- _

+'.5V

CS3 CS4--'

OUTPUT

--\ - - - - - - 1 +1.5 V
-+ tACS- ~.

__ tACS+

SWITCHING TEST OUTPUT LOAD
5.0V

RU

15 rnA Load

Fig. 1

7-137

300 n

•

93450/93451
l'sOPLANAR SCHOTTKY TTL MEMORY
1024 X 8 - BIT PROGRAMMABLE READ ONLY MEMORY
DESCRIPTION - The 93450 and 93451 are fully decoded 8192-bit field Programmable
ROMs organized 1024 words by eight bits per word. The devices are identical except for
the output stage. The 93450 has uncommitted collector outputs, while the 93451 has
3-state outputs. Either device is enabled when CS1 and CS2 are LOW and CS3 and CS4
are HIGH. The 93450/51 is supplied with all bits stored as logic "1's" and may be programmed to logiC "O's" by following the field programming procedure.
•
•
•
•
•
•
•
•
•
•
•

LOGIC SYMBOL

CS,

CS2
21 20

FAST ADDRESS ACCESSTIME-35 nsTYP
FULL MIL AND COMMERCIAL RANGES
FIELD PROGRAMMABLE
ORGANIZATION - 1024 WORDS X 8 BITS
UNCOMMITTED COLLECTORS - 93450
3-STATE OUTPUTS - 93451
FULLY DECODED - ON-CHIP ADDRESS DECODER AND BUFFER
CHIP SELECT INPUTS PROVIDE EASY MEMORY EXPANSION
WIRED-OR CAPABILITY
STANDARD 24-PIN DUAL IN-LINE PACKAGE
NICHROME FUSE LINKS FOR HIGH RELIABILITY

CS3 CS4
19 18

Ao
A1
A,
A,
A.

93450/93451

As
As
A7

PIN NAMES

Ao - A9
CS1, CS2, CS3, CS4
01- Os

2'
22

Address Inputs
Chip Select Inputs
Data Outputs

-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
100 mA
-0.5 V to +5.5 V

LOGIC DIAGRAM

A.
81t:l·BITCELL
128X64
MEMORY MATRIX

A,

As

9 10 11 13 14 15 16 17

ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Temperature (Ambient) Under Bias
Vee
Input Voltage
Current into Output Terminal
Output Voltages

A,

A.

vee = Pin 24
GND = Pin 12
CONNECTION DIAGRAM
DIP (TOP VIEW)

A7

Vee

As

A.

As

As

A.

CO,

A,

CO,

A,

es,

A,

es.

A<

O.

A.
A,

A'------I

A.--___-I

0,

07

0,

O.

0,

Os

GND

0,

cs.

v,'----...,
0.

0,

0.

0.

0,

0,

NOTE: The Flatpak version has the
same pinouts (Connection Diagram)
as the Dual In-line Package.

7-138

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93450/93451
GUARANTEED OPERATING RANGES

PART NUMBERS

SUPPL Y VOLTAGE (Vcc)

AMBIENT
TEMPERATURE

MIN

TYP

MAX

93450XC, 93451 XC

4.75 V

5.0 V

5.25 V

O°C to +75°C

93450XM,93451XM

4.50 V

5.0 V

5.50 V

-55°C to +125°C

x=

package type; F for Flatpack, D for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

FUNCTIONAL DESCRIPTION - The 93450 and 93451 are bipolar field Programmable Read Only
Memories (PROMs) organized 1024 words by eight bits per word. Open Collector outputs are
provided on the 93450 for use in wired-OR systems. The 93451 has 3-state outputs which provide active pull-ups when enabled and high output impedance when disabled. Chip Select for both
devices follows the logic equation: CS1 • CS2. CS3. CS4 = CS; i.e., if CS1 and CS2 are both active
LOW and CS3 and CS4 are both active HIGH, all eight outputs are enabled; for any other condition
all eight outputs are disabled.
The read function is identical to that of a conventional bipolar ROM. That is, a binary address
is applied to the Ao through A9 inputs, the chip is selected, and data is valid at the outputs after
tAA nanoseconds.
Programming (selectively opening nichrome fuse links) is accomplished by following the sequence
outlined under the table of PROGRAMMING SPECIFICATIONS.

PROGRAMMING - The 93450 and 93451 are manufactured with all bits in the logic "1" state.
Any desired bit (output) can be programmed to a logic "0" state by following the procedure
shown below. One may build a programmer to satisfy the specifications or purchase any of the
commercially available programmers which meet these specifications.
PROGRAMMING SPECIFICATIONS

PARAMETER
Address Input

Chip Select

SYMBOL

MIN

RECOMMENDED
VALUE

VIH

2.4

VIL

0

CS1, CS2

2.4

CS3, CS4

0

COMMENTS

MAX

UNITS

5.0

5.0

V

0

0.4

V

5.0

5.0

V

Pin 20 or 21 or both

0.4

V

Pin 18 or 19 or both

Applied to output to be programmed

-0

Do not leave inputs open

I

Either or both

I

Programming Voltage Pulse

Vop

20

20.5

21

V

Programming Pulse Width

tpw

0.05

0.18

50

ms

All bits can be programmed in S 8.2 s

%

'Maximum duty cycle to maintain Tc< 85° C

Duty Cycle Programming Pulse
Programming Pulse Rise Time

20
tr

Number of Pulses Required
Power Supply Voltage

Vcc

Case Temperature

Tc

Programming Pulse Current
Limit

lop

Low Vcc Read

Vcc

0.5

1.0

3.0

1

4

8

4.9

5.0

5.1

V

25

85

°C

100

mA

5.0

V

4.4

I's

11 pulse generator is used, set current
limit to this max value.
Programming Read Verify

PROGRAMMING SEQUENCE - The Fairchild 93450/93451 is programmed using the following
method.
1. Apply the proper power, Vee = 5.0 V, GND = 0 V.
2. Select the word to be programmed by applying the appropriate voltages to the address pins Ao
through Ag.
3. Enable the chip for programming by application of a HIGH (logic "1") to Chip Select CS1, (Pin
21) or CS2, (Pin 20), or by application of a LOW (logic "0") to Chip Select (CS3), Pin 19 or (CS4),
Pin 18.

7-139

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93450/93451
4. Apply the 20.5 V programming pulse to the output associated with the bit to be programmed. The
other outputs may be left open or tied to any logic "1" (output HI GH). i.e .• 2.4 V to 4.0 V. Note that
only one output may be programmed at a time.
5. To verify the logic "0" in the bit just programmed. remove the programming pulse from the output. lower Vcc to 4.4 V and sense the output after applying a logic "0" to Chip Selects CS, and
CS2 and a logic "1" to Chip Selects CS3 and CS4.
6. The above procedure is then repeated to program other bits on the chip.
BOARD PROGRAMMING

1. Memories 1 through 4 are OR-tied and connected to the programmer as shown (Figure 1).
2. Connect CS3 (Pin 19) and CS4 (Pin 18) of all the memories to a HIGH (logic "1") or leave
unconnected.
3. Connect CS2 (Pin 20) of all memories to ground.
4. Connect outputs of the TTL Decoder to CS,s (Pins 21) of the four memories on the board.
5. To program a bit in one of the four memories. connect the decoder supply voltages to Vcc =
+12.6 Vand VEE = +7.6 V and select an Address Ao. A, (HIGH = +10.6 V; LOW = +7.6 V).
6. Raise the programming voltage to 20.5 V; the memory whose CS, is LOW at +7.8 V (Memory 4 in
Figure 1) will program. all others with CS, HIGH at +10.6 V will remain deselected.
7. To verify the logic "0" in the bit just programmed remove the programming pulse and sense the
OR-tie after simultaneously lowering the decoder supplies to Vcc = 4.4 V. VEE = 0 Vand shifting
the decoder address Ao. A, down to its normal levels (HIGH = 3.0 V; LOW = 0 V).
8. Repeat procedure for other bits following the normal programming sequence.
9. To select a different memory on the board change decoder address Ao. A, .

. . rR- :::.::AM

.

II·~---------------.

PROMs

I

0.1-------,
0.1------,
0,1---

o'r--

~ +10 V
V

n

'---...---'
ADDRESS
LEVELS

o,I---H+H+-H

r~

:::...JL

0,1--t-++lH-+1
0, I---H-t-t-t-t
0.1---+-1-++1
0.1--t-+-H
o. I---H-4

ADDRESS
(PROGRAM
MODE)

o'r-o'r-t
l~v

o. I---H-t-t-t-++1
0,1--1-++-H--H
0,1---+-+-++-1-1

o·I---H+-H

0.1--H--H
0.1---t-t-t
0'1-0.1-I
I
I
I

0, 1---t-t-t-t-t-++1
0,1--H-+1-++1
o,I---H--t-H-t
o·I---H--t-H

I
I
I

I
I

:orJL
I

VERIFV

I I~______________~ ,,,

vI -

Fig. 1 Board Programming

7-140

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY. 93450/93451
DC CHARACTERISTICS: Over guaranteed operating ranges unless otherwise noted.
LIMITS

S YMBOL

CHARACTERISTIC

TYP
(Note 1)

MIN

MAX

UNITS

CONDITIONS

CEX

Output Leakage Current
(93450 only)

50

p.A

Vcc ~ 5.25, VCEX ~ 4.95 V, O°C to +75°C
Address any HIGH Output

ICEX

Output Leakage Current
(93450 only)

100

p.A

VCC ~ 5.5, VCEX ~ 5.2 V, -55°C to +125°C
Address any HIGH Output

VOL

Output LOW Voltage

0.45

V

Vcc ~ MIN, IOL ~ 16 rnA, Ao ~ +10.8 V,
Ag ~ +10.8 V, A, - As ~ Don't Care

VOH

Output HIGH Voltage (93451 only)

V

Vcc

~

MIN, IOH

~

loff

Output Leakage Current lor HIGH
Impedance State (93541 only)

50
-50

p.A
p.A

VOH
VOL

~
~

2.4 V
0.4 V

O°C to +75°C

loff

Output Leakage Current lor HIGH
Impedance State (93451 only)

100
-50

p.A
p.A

VOH
VOL

~

2.4 V
0.4 V

-55°C to +125°C

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

IF

Input LOW Current
IFA (Address Inputs)
IFCS (Chip Select Inputs)

IR

Input HIGH Current
IRA (Address Inputs)
IRCS (Chip Select Input)

Icc

Power Supply Current

Co

Output Capacitance

CIN

I nput Capacitance

VC

Input Clamp Diode Voltage

AC CHARACTERISTICS: TA

~

0.30
2.4

2.0
0.8

Guaranteed Input HIGH Voltage lor all Inputs

V

Guaranteed Input LOW Voltage lor All Inputs

p.A
p.A

Vcc

~

MAX, VF

~

0.45 V

40
40

p.A
p.A

Vcc

~

MAX, VR

~

2.4 V

175

rnA

Vcc ~ MAX, Outputs Open
Inputs Grounded and Chip Selected

7

pF

Vcc

~

5.0 V, Vo

~

4.0 V, I

~

1.0 MHz

4

pF

VCC

~

5.0 V, Vo

~

4.0 V, I

~

1.0 MHz

V

Vcc

~

MIN, IA

-1.2

~

V

-250
-250

-160
-160

130

O°C to +75°C, Vcc

~

-2.0 rnA

~

-18 rnA

5.0 V +5%
LIMITS

SYMBOL
AAAA+
ACSACS+

TYP
(Note 1)

MAX

UNITS

CONDITIONS

35
35

55
55

ns
ns

See Figure 2A and 2B

15
15

25
25

ns
ns

TYP
(Note 1)

MAX

UNITS

CONDITIONS

Address to Output Access Time

35
35

70
70

ns
ns

See Figure 2A and 2B

Chip Select Access Time

15
15

30
30

ns
ns

CHARACTERISTIC

Address to Output

Ac~ess

MIN

Time

Chip Select Access Time

AC CHARACTERISTICS: TA

~

-55°C to +125°C, Vcc

~

5.0 V ±10%
LIMITS

S YMBOL
AAAA+
ACSACS+

CHARACTERISTIC

MIN

Note (1): Typical values are at Vee = 5.0 V, +25°C and max loading.

7-141

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL MEMORY • 93450/93451
AC WAVEFORM

AOORESS{_~~. VA"

OUTPUTS

CH'PSELECT{-----=--=-~-)~ - CS3 CS,_

- - - -

0K-+l.SV
--------

OUTPUTS

-40

'ACS-

t--

AC TEST OUTPUT LOAD
5.0 V

Ru

5.0 V

300 n

Rll

OUTPUT

300 !l

OUTPUT

60011

6001\

15 mA Load
Applies 10 93450 Only

15 mA Load
Applies 10 93451 Only

Fig.2A

Fig. 28

PROM PROGRAMMING CIRCUIT (see Fig. 3)
This circuit will sequentially program all eight bits of a given word address of the 93450 or 93451.
Selection of the word to be programmed is made by the address switches.
Until the program switch is depressed, the contents of the 93450 or 93451 at the address set in the
address switch register is displayed on the eight FLV117 LEOs. If the content is a Logic "1" or the
chip is deselected, the LEO is turned on with current supplied by the 390 fl resistors. If the content
of the PROM is a logic "0" and the PROM is enabled, the output is Logic "0" turning the LEOs off.
The 1N4002s isolate the LEOs from the 20.5 V programming pulse.
The 9601 is a one-shot continuous 1.0 ms oscillator. One-half of a 9024 is used as a switch debouncer while the other half is the "run" flip-flop. When the program is initiated by depressing the
program switch, the first half of the 9024 (switch debouncer) is set and clocks the other half of the
9024 ("run" flip-flop) to the "run" state. This enables the counters to operate and disables the 93450.
The counter is preset to 5 on the 931 0 and 8 on the 9316. The counter provides the proper duty cycle
and program timing.
To avoid overlap problems between the programming pulse, the chip enable and the scan, the 9316
advances when the 9310 goes from state 3 to state 4. When the last bit has been programmed, the
counter presets itself and resets the "run" flip-flop. The programming sequence is now complete.
The bit to be programmed is decoded by the 9301 and ORed with the bit switch. The OR gate is a
high voltage driver supplying the drive to the programming transistors.

7-142

I

~

15
20.S ± !l.5

~

,\ !! d!!! H1'::

~~

__ -

1

I,
16
15
I.
I,

~_

~
~

-=

(CURRENT LIMIT laO mAl

""'7A~.

I l

'N"07A~.

93450/93451
1024XB
PROM

9316
9310

'"

9024
'NOO
9601
9N32
FlVl17
lN4002
2N2907A

IIIIIII I

,
,,,
,,

.

:D

9301

n

n

H Il () I

::I:

r-

'"

I I

C

I I I I .mW 600 0
~

7-148

93458/93459
ISOPLANAR SCHOTTKY TTL FPLA
16 x 48 x 8 FIELD PROGRAMMABLE LOGIC ARRAY
DESCRIPTION - The 93458 and 93459 are high -speed bipolar Field Programmable
Logic Arrays organized with 16 inputs, 48 product terms and eight outputs. The 16 units
and their complements are fuse linked to the inputs of 48 AND gates (48 product
terms). Each of the 48 AND gates are fuse linked to eight 48- input OR gates (eight
summing terms). Each output may be programmed active HIGH or active LOW. The
devices are identical except for the output stage. The 93458 has uncommitted collector
outputs while the 93459 has 3 -state outputs. In either case, the outputs are enabled
when CS is LOW.
•
•
•
•
•
•
•
•

"

FIELD PROGRAMMABLE (NICHROME FUSE LINKS)
FULL MIL AND COMMERCIAL TEMPERATURE RANGES
FAST CYCLE TIME - 25 ns TYP
ORGANIZATION - 16 INPUTS x 48 PRODUCT TERMS x 8 OUTPUTS
UNCOMMITTED COLLECTOR OUTPUTS - 93458
3·STATE OUTPUTS - 93459
CHIP SELECT PROVIDES EASY FUNCTIONAL EXPANSION
STANDARD 28-PIN PACKAGE

ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Temperatwe (Ambient) Unuer Bias
VCC Pin Potential to Ground
Input Voltage
Current Into Output Terminal
Output Voltages

LOGIC SYMBOL

""

..""
"
"

93458/93459

"
"
'"
'"

-65°C to + 150°C
-55°C to + 125°C
-0.5 V to + 7.0 V
-0.5 V to + 5.5 V
100 mA
-0.5 V to 5.5 V

'"
'"
'"
'"

Vee = Pin 28

PIN NAMES
AO-A15
CS

01- 0 8

GND ~ Pin 14
Vp = Pin 1

. Address Inputs
Chip Select Input
Data Outputs

LOGIC DIAGRAM (93458)

CONNECTION DIAGRAM
DIP (TOP VIEW)

PROGRAMMABLE
\LlNK

:1
I

V.
PRODUCT
MATRIX

16 INPUTS

: 1

A15~o-~i;M>-.Ht~+-----------1+HtHt-----_

PROGRAMMABLE LINK

48
321NPUT
AND GATES

-~----------==~g~=:r~~:rJ
SUMMING
MATRIX

08
cso---~I~------~

7-149

Vee

'7

AS

AS

A.

A.

A'0

A,

A11

A3

A'2

A2

A'3

A,

A'4

AO

A"

Os

es

07

0,

o.

02

O.

03

GNO

0,

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL FPLA • 93458/93459
GUARANTEED OPERATING RANGES
PART NUMBERS

SUPPLY VOLTAGE (VCC)
TYP

MAX

5.0 V

I
I

5.25 V

DoC to

5.0 V

I

5.50 V

-55°C to

93458DC, 93459DC

4.75 V

I
I

93458DM, 93459DM

4.50 V

I

MIN

TEMPERATURE

+ 75°C
+ 125°C

LOGIC RELATIONSHIPS
Input Term

An

Product Term

Pm

n

=TT6 5 (in An + in An)

= 0, ... , 15, one of 16 inputs

m = 0, ... , 47, one of 48 product terms
where:
a) in
in
0 for unprogrammed input
b) in
J;:; for programmed input
c) in = in
1 for don't care input

= =
=
=

=

r
1, ... , 8, the OR function of the 48
products terms
Summing Term

Sr

=

267 km Pm

where k m = 0 for product term inactive
(programmed)
km
1 for product term active
(unprogrammed)
OUTPUT

MODE
READ

CS

F,

S,

ACTIVE HIGH

0
0
0

1
1

0

0

1

1

1

0

0

X

0

1

1
1

X
X

X
X

1 (93458)
HI Z (93459)

1 (93458)
HI Z (93459)

DISABLE

ACTIVE LOW

Example - By programming, the eight outputs of an FPLA can be made to relate to the 16 inputs as
given by the following example:
01 = AOA6 A 14 + A2 A 15 + Ao A1··· A 15 + A8 A 10A13
~
16 input terms
max

'-________________

~v~------------------~J

48 product terms
max

8 outputs
total
02

=

AO A6 A14

+ A2 A15 (Output polarity programmed, active high.)

08 = (A8 AlO A13

+ A4 A7 Ag A11 A12) (Output polarity not programmed,
active low.)

FUNCTIONAL DESCERIPTION - The 93458 and 93459 are bipolar Field Programmable Logic
Arrays (FPLA) organized 16 inputs by 48 product terms by eight outputs. Open collector outputs are
provided on the 93458 for use in wired-OR systems. The 93459 has 3-state outputs which
provide active pull ups when enabled and high output impedance when disabled. Chip Select for
both devices is active LOW; i.e., a HIGH (logic "1 ") on the CS pin will disable all outputs.
The read function is identical to that of a conventional bipolar ROM. That is, a binary address is
applied to the AO through A15 inputs, the chip is selected, and data is valid at the outputs after
tAA nanoseconds,

7-150

FAIRCHILD ISOPLANAR SCHOTTKY TTL FPLA • 93458/93459
DC CHARACTERISTICS' Over guaranteed operating ranges unless otherwise noted
LIMITS
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

CONDITIONS

UNITS

(Note 1)
Output Leakage Current
ICEX

(93458 only)
Output Leakage Current

ICEX

(93458 only)

=

=

=

=

50

IJA

MAX, VCEX
VCC, DoC to + 75°C
VCC
Address any HIGH Output

100

IJA

VCC
MAX, VCEX
VCC, - 55°C to + 125°C
Address any HIGH Output

= MiN, 10L = 16 mA
= 0 V; AO-A5, A13, A15 = 5 V; and
A6-A12, A14 = 10.8 V
VCC = MIN, 10H = -2.0 mA
VOH = 2.4 V
DoC to + 75°C
VOL = 0.4 V
VOH = 2.4 V
-55°C to + 125°C
VCC

VOL
VOH

Output LOW Voltage
Output HIGH Voltage (93459 only)

0.30

0.45

2.4

V

Output Leakage Current for HIGH
loff

Impedance State (93459 only)

loff

Output Leakage Current for HIGH
Impedance State (93459 only)

lOS

Short Circuit Current

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

V

50
-50

IJA

100

IJA

-70

mA

/J A
/J A

-10

Vp, CS

VOL = 0.4 V
V OUT

= OV; Chip Enabled

V

Guaranteed Input HIGH Voltage for All Inputs

0.8

V

Guaranteed Input LOW Voltage for All Inputs

- 250
-250

IJA
IJA

VCC

= MAX, VF = 0.45 V

VCC

= MAX, VR = 2.4 V

2.0

Input LOW Current
IF

IFA (Address Inputs)

-160

IFCS (Chip Select Inputs)

-160

Input HIGH Current
IR

IRA (Address Inputs)

40

iJ A

IRCS (Chip Select Input)

40

iJ A

140

mA

MAX, Outputs Open
Vec
Inputs Grounded and Chip Selected (Note 2)

Power Supply Current

Co

Output Pin Capacitance

7

pF

VCC

CI

Input Pin Capacitance

4

pF

VCC

Vc

Input Clamp Diode Voltage

V

VCC

AC CHARACTERISTICS:

TA

105

=

ICC

-1.2

= DoC to + 75°C, VCC

= 5.0 V, Vo = 4.0 V, f = 1.0 MHz
= 5.0, Vo = 4.0 V, f = 1.0 MHz
= MIN, IA = -18 mA

5.0 V ± 5%
LIMITS

SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNITS

CONDITIONS

(Note 1)
tAA-

Address to Output Access Time

tAA+
tACStACS+

Chip Select Access Time

AC CHARACTERISTICS:

TA

= - 55°C to

25

45

ns

25

45

ns

15

25

ns

15

25

ns

+ 125°C, VCC

See Figure 1A and 1B

= 5.0 V +- 10%

LIMITS
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNITS

CONDITIONS

(Note 1)
25
25

65
65

ns

tAA+
tACS-

15

30
30

ns

tAA-

tACS+

Address to Output Access Time
Chip Select Access Time

15

ns

See Figure 1A and 1B

ns

NOTES: 1. Typical values are at Vee ~ 5.0 V, +25°e and max loading.
2. For programmed part, add .45 mA typical, .60 mA max per selected programmed product terms and add 2.9 mA typical,
3.9 mA max per enabled low output or 33 mA typical, 44 mA max for disabled states.

7-151

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL FPLA • 93458/93459

AC WAVEFORMS

ADDRESS

~

-~I "t
OUTPUT

.%

AA + .1--:_

AC TEST OUTPUT LOAD
5.0V

RU

5.0V

15 pF

PROGRAMMING characterized by:
•
•
•

300n

OUTPUT

±

RL2

-=-

RU

3000

OUTPUT

6000

~

15 rnA Load
Applies to 93458 Only

15 rnA load
Applies to 93459 Only

Fig.1A

Fig.1B

The 93458 and 93459 are delivered in an unprogrammed state,

all fuses intact
ali 8 output buffers in active LOW state
all outputs read HIGH

Programming and verifying the Product Matrix, the Summing Matrix, and the Output Polarity are
outlined below.
Program Product Matrix
All 48 AND gates of the product matrix are fuse linked to both the true and false lines of every
input buffer in the initial unprogrammed state. The initial logic expression for the 48
unprogrammed AND gates is AO
A1 A1 ... A15 A15 (where An or An is defined to be an input
term). Programming the fuse located by the selection of an input line, 'an', and the mth AND
gate replaces the input term An with '1' in the logic expression for the mth AND gate.

AD

1. Connect pin 28 (VCC) to 5.0 V.
2. Connect pin 14 (GND) to ground.
3. Connect pin 19 (CS) to a TTL HIGH level.
4. Apply TTL levels to pins 10 through 13, 15, and 16 (08 through 03) to address an on-chip one
of forty-eight decoder to select the AND gate to be programmed (08 LSB and 03 MSB).

=

5. Apply 10.8 V to ali input pins (AO through A15).

7-152

=

FAIRCHILD ISOPLANAR SCHOTTKY TTL FPLA • 93458/93459
6. Apply the proper TTL level to an Ax input pin as follows (program one Input at a time):
a. If the product term to be programmed contains the Input term Ax (where x = 0 through 15),
lower the Ax pin to a TIL HIGH level.
b. If the product term to be programmed contains the input term Ax, lower the Ax to a TIL
LOW level.
c. If the product term does not contain the input terms Ax or Ax (i.e., Ax is a DON'T CARE in·
put), perform steps 6a, 7, 6b, and 7.
7. Apply an 18 V programming pulse to pin 1 (Vp) according to the programming specifications
table.
8. Repeat steps 5 through 7 for each Input of the selected product term.
9. Repeat steps 4 through 8 for all other product terms to be programmed.
•
•

Program one input at a time.
All unused inputs of programmed product terms must be programmed as DON'T CARES.

•

Inputs of unused product lines are not required to be programmed.

•

Pin 18 (01) is in the read mode (open collector). Care must be taken so that this pin is
either left open, grounded, or loaded such that the current flowing into the pin does not
exceed 16 mAo

PROGRAMMING SPECIFICATIONS

SYMBOL

CHARACTERISTIC

MIN

RECOMMENDED
MAX UNITS
VALU'E

VIH
VIL

TTL Levels

2.4
0

5.0
0

5.0
0.4

V
V

CS

Chip Select

2.4

5.0

5.0

V

VOP

Programming Voltage Pulse

17.5

18.0

18.5

V

tpw

Programming Pulse Width

0.18

50

ms

20

.

0.5

1.0

3.0

1

4

8

4.75

5.0

5.25

V

25

85

·C

Duty Cycle,Programming Pulse
tr

Pragramming Pulse Rise Time
Number of Pulses Required

%

COMMENTS
Apply to appropriate address and
output pins. Do not leave pins
open.
I Apply to Vp or tne appropriate
output pin.
-MaXimum au y eye e
TC < 85°C.

0

main aln

,..5

VCC

Power Supply Voltage

tc

Case Temperature

IVp

Programming Pulse Current
Max (Vp Pin)

200

mA

" pulse generator is used, set cur·
rent limit to this max value.

lOp

Programming Pulse Current Max
(Any Output Pin)

100

mA

" pulse generator is used, set cur·
rent limit to this max value.

VCC

Low VCC Read

5.0

V

4.4

7-153

Programming Read Verify.

FAIRCHILD ISOPLANAR SCHOTTKY TTL FPLA • 93458/93459
Verify Product Matrix

1. Connect pin 28 (VCC) to 5.0 V.
2. Connect pin 14 (GND) to ground.
3. Connect pin 19 (CS) to a TIL HIGH level.
4. Apply TIL levels to pins 10 through 13, 15, and 16 (08 through 03) to address an on-Chip
one of forty-eight decoder to select the AN D gate to be verified (08 = LSB and 03 = MSB).
5. Apply 10.8 V to all input pins (AO through A15).
6. Test the state of the Ax input as follows:
a. Lower the Ax pin to a TTL HIGH level and sense the voltage on pin 18 (01).
b. Lower the Ax pin to a TIL LOW and sense the voltage on pin 18 (01).
7. The state of the Ax input is determined as follows:

LEVEL AT
OUTPUT 1

Ax=
TIL
HIGH
H
H
L
L

Ax=
TIL
LOW
H
L
H
L

CONDITION OF
Ax FOR SELECTED
PRODUCT TERM
DON'T CARE
Ax IN P-TERM
Ax IN P-TERM
UNPROGRAMMED

8. Repeat steps 5 through 7 for each input of the selected product term.
9. Repeat steps 4 through 8 for all other product terms.
10. Repeat steps 4 through 9 with Vee at 4.4 V (low Vee read).
NOTES:

1. 01 in this mode functions as an open coil ector output, H" 2.0 V, L" 0.8 V.
2. The table above is valid regardless of the polarity (active HIGH or active LOW) of 01'
3. Pin 1 (Vp) should be either floating or grounded.

Program Summing Matrix

All eight OR gates of the summing matrix are fuse linked to the outputs of the AND gates in the
initial unprogrammed state. The initial logic expression (sum of products) of the eight unprogrammed OR gates is PO + P1 + P2 + ... + P47 where Pm is the product term programmed into
the mth AND gate. Programming the fuse located by the selection of the mth AND gate and
the nth summing line replaces the product term Pm with '0' in the logic expression of the nth
OR gate. The nth summing line is selected by the selection of the nth output buffer where n = 1
through eight.
1. Connect pin 28 (VCC) to 5.0 V.
2. Connect pin 14 (GND) to ground.
3. Connect pin 19 (CS) to a TIL HIGH level.
4. Apply TTL levels to pins 4 through 9 (A5 through AD) to address an on-chip one- of-fortyeight decoder to select the AND gate to be programmed (AO = LSB and A5 = MSB).
5. Apply a TIL HIGH level to pins 20 and 21 (A15 and A14)'
6. Connect the remaining input pins to 10.8 V.
7. Apply an 18 V programming pulse (see programming speCifications table) at the pin of the
output to be programmed. Other output pins should be either left open or tied to a TIL
HIGH level.
•

Program one output pin at a time.

•

All unused product lines are not required to be programmed.

7-154

FAIRCHILD ISO PLANAR SCHOTTKY TTL FPLA • 93458/93459
Verify Summing Matrix

1. Connect pin 28 (VCC) to 5 V.
2. Connect pin 14 (GND) to ground.
3. Connect pin 19 (CS) to a TTL LOW level.
4. Apply TTL levels to pins 4 through 9 (A5 through AO) to address an on-chip,one-of-forty-eight
decoder to select the AN D gate to be verified (AO = LSB and A5 = MSB).
5. Apply a TTL HIGH level to pins 20 and 22 (A15 and A13).
6. Connect the remaining input pins to 10.8 V.
7. Sense the voltage on the output pin to be verified. The programming of the selected product
line to the output line can be determined as follows:
OUTPUT
READS
L
H

FUSE
LINK
BLOWN (INACTIVE)
UNBLOWN (ACTIVE)

8. Repeat steps 4 through 7 with VCC at 4.4 V (low VCC read).
•

The condition of the fuse link can be determined from the table above regardless of the
polarity (active HIGH or active LOW) of the output buffer being verified.

Program Output Polarity

The initial unprogrammed state of all eight output buffers is active LOW or inverting. To
program an output buffer into the active HIGH or non-inverting state proceed as follows:
1. Connect pin 28 (VCC) to 5.0 V.
2. Connect pin 14 (GND) to ground.
3. Connect pin 19 (CS) to a TTL HIGH level.
4. Apply a TTL HIGH level to pins 4 through 9 (A5 through AO).
5. Apply a TTL HIGH level to pin 20 (A15).
6. Connect the remaining input pins to 10.8 V.
7. Apply an 18 V programming pulse (see programming specifications table) to the pin of the
output to be programmed. Other output pins should be either left open or tied to a TTL
HIGH level.
•

Program one ouiput at a time.

Verify Output Polarity

1. Connect pin 28 (VCC) to 5.0 V.
2. Connect pin 14 (GND) to ground.
3. Connect pin 19 (CS) to a TTL LOW level.
4. Apply a TTL HIGH level to pins 4 through 9 (A5 through AO).
5. Apply a TTL HIGH level to pins 21 and 22 (A14 and A13).
6. Connect the remaining input pins to 10.8 V.
7. Sense the voltage on the pin of the output buffer to be verified. The condition of the output
can be determined as follows:
OUTPUT
READS
H
L

OUTPUT
STATE
ACTIVE LOW
ACTIVE HIGH

8. Repeat step 7 with Vee at 4.4 V (low Vee read).

7-155

•

FAIRCHILD ISOPLANAR SCHOTTKY TTL FPLA • 93458/93459
The table given below summarizes the full programming and verifying procedures.

SUMMARY OF PIN VOLTAGES (VOLTS)
Read

Program
Product
Matrix

Verily
Product
Matrix

Program
Summing
Matrix

Verily
Summing
Matrix

Program
Output
Polarity

Verily
Output
Polarity

1 (Vp)

...

lS

...

...

...

...

...

Pin 2 (A7)

TTL

10.S·

10.S·

10.S

10.S

10.S

10.S

Pin 3 (A6)

10.S·

10.S·

10.S

10.S

10.S

10.S

Pin 4 (A5)

TTL
TTL

10.S·

10.S·

TTL

TTL

TTL HIGH

TTL HIGH

Pin 5 (A4)

TTL

10.S·

10.S·

TTL

TTL

TTL HIGH

TTL HIGH

Pin 6 (A3)
Pin 7 (A2)

TTL
TTL

10.S·
10.S·

10.S·

TTL

Pin S (Al)

TTL

10.S·

TTL
TTL

TTL HIGH
TTL HIGH

TTL HIGH

10.S·
10.S·

TTL
TTL
TTL

TTL HIGH

TTL HIGH
TTL HIGH

Pin 9 (AO)

TTL

10.S·

10.S·

TTL

TTL

TTL HIGH

TTL HIGH

Pin 10 (OS)

READ

TTL

TTL

READ

****

READ

Pin 11 (07)
Pin 12 (06)

READ
READ

TTL
TTL

TTL
TTL

****

....

READ
READ

Pin 13 (05)
Pin 14 (GND)

READ

TTL

TTL

** ••

READ
READ
READ

****

READ

GND

GND

GND

GND

GND

GND

Pin 15 (04)

READ

TTL

TTL

****

READ

****

GND
READ

Pin 16 (03)

READ

TTL

READ

READ
READ

..

****

Pin 17 (02)

..

TTL

****

READ

READ

****

READ
READ

.* ••
.* ••

Pin

....
....
• ***

READ
READ
READ

Pin lS (01)
Pin 19 (eS)

TTL LOW

TTL HIGH
10.S·

TTL LOW

TTL HIGH

TTL

TTL HIGH
10.S·

TTL HIGH

Pin 20 (A15)

TTL HIGH

TTL HIGH

TTL HIGH

TTL LOW
10.S

Pin 21 (A14)

TTL

10.S·

10.S·

TTL HIGH

10.S

10.S

TTL HIGH

Pin 22 (A13)

TTL

10.S·

10.S·

10.S

TTL HIGH

10.S

TTL HIGH

Pin 23 (A12)

TTL

10.S·

Pin 24 (All)

TTL

10.S
10.S

10.S
10.S

10.S
10.S

10.S
10.S

Pin 25 (Al0)

TTL

10.8'
10.S·

10.S·
10.S·
10.S·

10.S

10.S

10.S

10.S

Pin 26 (A9)

TTL

10.S·

10.S·

10.S.

10.S

10.8

10.S

Pin 27 (AB)

TTL
5.0

10.S·

10.S·

10.S

10.S

5.0

10.S
5.0

10.S

5.0

5.0

5.0

5.0

Pin 2S (Vee)

'For selection of mput apply TTL HIGH or TTL LOW.
"Left open or TTL HIGH .
• uLeft open or grounded.
• .. ·Left open, TTL HIGH, or programming pulse.

7-156

****

FAIRCHILD ISOPLANAR SCHOTTKY TTL FPLA • 93458/93459

16 X 48 X 8 FPLA PROGRAM TABLE
PROGRAM TABLE ENTRIES
OUTPUT FUNCTION
PROD. TERM
PROD. TERM
PRESENT IN Fr
NOT PRESENT IN Fr

INPUT VARIABLE
DON't CARE

An

c

J:
0

NOTE.
Enter (-) for
P-terms

IX:

C(
u..
C

W
IW

5

11.

.

:E
0
0

t-

W
ID

a:

0

~

Z
0

UJ

I-

Cl

...0~

i=
IX:

co

0

11.

!!l

~
a:
UJ

CIJ

J:

R
><
><

~

Cl

UJ

::.
Uj

0

~

e

UJ

==>
0

<{

0

u..

CI)

a:

~

Cl

[:?
~

UJ
~
~

0
0

::.
UJ

a:

~

CI)

==>

0

[:?
a:
~

.. .
...
0

u..
0

UJ

UJ

...i:Cl

~
==>

a:

UJ

Cl

:;;

UJ

~ a:
0
a:
UJ
UJ CI)

e

• (period)

A

L

H

NOTES1) Polarity programmed once only
2) Enter (L) for all unused outputs

NOTES:
1) Entnes mdependent of output polarity
2) Enter (A) tor unused outputs 01 used P·terms

4

3

2

1

o

9

8

7

6

5- -4

3

2

1

0

r-~~+-~~~+-~~~-r~--~-r~--~-r~--+-~

....I

UJ
~

(dash)

unused Inputs of used

f---.-----------P~R~O~D~UC~'T~T~E~RM~"--------------~-·II~VIEL~-,I·INPUT VARIABLE
....L.
....L.....L.
NO. ~-r-,
1
1
1
1 f-:-.--.,-.:--r-.-r--:
-r----,---,---,-.-l =~
OUTPUT FUNCTION"
~=

>
ID

I-

-

L

H

:::!

OUTPUT ACTIVE LEVEL
ACTIVE
ACTIVE
LOW
HIGH

Cl

UJ

a: co
co

...

~

~

~ 0 ~ ~

Q..
Q..
~
0

e

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

7

6

5

4

3

2

1

0

•

"Input and Output fields of unused P-terms can be left blank.

7,157

TTL ISO PLANAR MEMORY 93L470/93L471
4096 X 1 - BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION-The 93L470 and 9;3L471 are low power 4096-bit TTL Read/Write Random
Access Memories organized 4096 words by one bit. The devices are identical except for
the output stage. The 93L470 has an uncommitted collector output, while the 93L471 has a
3-state output. The devices have full decoding on chip, separate Data Input and Data Output
lines and active LOW Chip Select lines. They are designed for high-performance main
memory application requiring low power and can be used to replace four 1024-bit RAMs.
•
•
•
•
•
•
•
•
•

Ao-All

17

lS

A2
A3
A.
AS
A.
10

A7

11

A8

12

A.

13

A'0

,.

PIN NAMES

WE
DIN
DOUT

,.
AD
A,

FULL MIL AND COMMERCIAL TEMPERATURE RANGES
ORGANIZATION-4096 WORDS X 1 BIT
READ ACCESS TIME-40 hs TYPICAL
CHIP SELECT ACCESS TIME-20 ns TYPICAL
UNCOMMITTED COLLECTOR OUTPUT-93L470
3-STATE OUTPUT-93L471
NON-INVERTING DATA OUTPUT
POWER DISSIPATION-0.09 mW/BIT TYPICAL
REPLACES FOUR 1024 BY ONE RAMs

CS

LOGIC SYMBOL

A11

Chip Select Input
Address Inputs
Write Enable
Data Input
Data oUtput

93L470/93L471

Dour

vee ~ Pin 18
GND ~ Pin 9

LOGIC DIAGRAM

CONNECTION DIAGRAM
DIP (TOP VIEW)

r---------------,
93L470

!

P-DOUT

L ______________

I

,
~

r---------------,
93L471

r--------:-I)-f>--OOUT

vee

- - -.....y-....- - -

GND

ADDRESS INPUTS

7-158

~
~

Pin 18
Pin 9

DDUT

vee

I

AO

DIN

A,

cs

A2

WE

A3

Al1

A4

A,O

A5

A9

A6

AS

GND

A7

FAIRCHILD ISOPLANAR TTL MEMORY. 93L470/93L471
FUNCTIONAL DESCRIPTION-The 93L470 and 93L471 are fully decoded 4096-bit Random Access Memories organized
4096 words by one bit. Word selection is achieved by means of a 12-bit address, AO through A11.

The Chip Select input is provided for logic flexibility. For larger memories, the fast Chip Select access time permits the decoding of Chip Select, CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable, WE (pin 15). With WE held LOW and
the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected. Data
in the specified location is presented at the Data Output.
The 93L471 has 3-state outputs which provide drive capability for higher speeds with high capacitive load systems. The third
state (high impedance) allows bus organized systems where multiple outputs are connected to a common bus.
The 93L470 has uncommitted collector outputs to allow maximum flexibility in output connection. In many applications, such
as memory expansion, the outputs of several 93L470s can be tied together. In other applications the wired-OR is not used. In
either case an external pull-up resistor of value RL must be used to provide a HIGH at the output when it is off. Any value of
RL within the range specified below may be used.

VCC(max)
IOL - F.O. (1.6)

.,----'--'::'''::-'''-;L"C:":" .;

RL .;

RL is in kfl
N
= number of wired-OR outputs tied together
F.O. = number of TTL Unit Loads (U.L.) driven
ICEX = Memory Output Leakage Current in mA
VOH = Required Output HIGH level at Output Node
IOL = Output Low Current

VCC(min) - VOH
N (lCEX) + F.O. (0.04)

-:-:--::-''--=-'~=-:::-=-~.:..':-.,.,..

The minimum value of RL is limited by output current sinking ability. The maximum value of RL is determined by the output
and input leakage current which must be supplied to hold the output at VOH.

TRUTH TABLE

INPUTS
es

-

OUTPUTS

WE

DIN

93L470
o.e.

93L471
3-STATE

MODE

H

X

X

H

HIGH Z

L

L

L

H

HIGH Z

Not Selected
Write "0"

L

L

H

H

HIGH Z

Write "'1"'

L

H

X

DOUT

DOUT

Read

H ~ HIGH Voltage, L ~ LOW Voltage; X ~ Don't Care (HIGH or LOW)
HIGH Z ~ High Impedance, OC ~ Open Collector

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
Input Voltage (dc)*
Input Current (dc)*
Voltage Applied to Outputs (output HIGH)**
OutPllt Current (de)

-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.50 V
-20 mA

'Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
"''''Output Current Limit Required.

GUARANTEED OPERATING RANGES

PART NUMBER

SUPPLY VOLTAGE (Vee)
MIN

TYP

MAX

AMBIENT TEMPERATURE
Note 4

93L470XC, 93L471Xe

4.75 V

5.0 V

5.25 V

DoC to +75°C

93L470XM, 93L471XM

4.50 V

5.0 V

5.50 V

-55°C to +125°e

x~

package type, F for Flatp,ak, D for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-159

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93L470/93L471
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1-4)
LIMITS
SYMBOL

CHARACTERISTIC

UNITS
MIN

VOL

Output LOW Voltage

TYP

MAX

0.3

0.50

CONDITIONS

V

VCC = MIN; 10L = 16mA

V

Guaranteed Input HIGH Voltage
for all Inputs

V

Guaranteed Input LOW Voltage
for all Inputs

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1.5

0.8

IlL

Input LOW Current

-250

-400

/LA

VCC = MAX, VIN = 0.4 V

1.0

40
1.0

/LA
mA

VCC = MAX, VIN = 4.5 V
VCC = MAX, VIN = 5.25 V

-1.0

-1.5

V

VCC = MAX, liN = -10 mA

1.0

100

/LA

VCC = MAX, VOUT = 4.5 V

50
-50

/LA

VCC = MAX, VOUT = 2.4 V
VCC = MAX, VOUT = 0.5 V

V

VCC = MIN, 10H = -5.2 mA

2.1

1.6

IIH

Input HIGH Current

VCD

Input Diode Clamp Voltage

ICEX

Output Leakage
Current

93L470

10FF

Output Current
(HIGH Z)

93L471

VOH

Output HIGH
Voltage

93L471

lOS

Output Current
Short Circuit
to Ground

93L471
93L470/71XC

67

'fA = +75'C

VCC = MAX,

Power Supply

93L470/71XC

80

TA = O'C

All Inputs and

Current

93L470/71XM

63

TA = +125'C

Outputs Open

93L470/71XM

86

ICC

2.4

-100

mA

mA

VCC = MAX, Note 7

TA = -55'C

AC CHARACTERISTICS: Over Guaranteed Operating Ranges (Notes 1-6)
93L470/71XC
SYMBOL

CHARACTERISTIC

READ MODE

DELAY TIMES

tACS
tRCS
tZRCS
tAA

ChipSelect Access Time
Chip Select Recovery Time (93L470)
Chip Select to HIGH Z (93L471)
Address Access Time

MIN

TYP
(Note 3)

93L470/71XM

MAX

MIN

TYP
(Note 3)

MAX

UNITS

20
30
30
40

20
30
30
40

ns

30
30
30

30
30
30

ns

25
5
0
5
0
0

25
5
0
5
0
0

CONDITIONS

See Test Circuit
and Waveforms

WRITE MODE DELAY TIMES
tws
tzws
tWR

Write Disable Time (93L470)
Write Disable to HIGH Z (93L471)
Write Recovery Time

tw
twSD
tWHD
tWSA
twHA
twscs
tWHCS

Write Pulse Width (to guarantee write)
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

CI
Co

Input Pin Capacitance
Output Pin Capacitance

INPUT TIMING REQUIREMENTS

0
4
7

7-160

See Test Circuit
and Waveforms
ns

0
5
8

4
7

5
8

pF

Measure with
Pulse Technique

FAIRCHILD ISOPLANAR TTL MEMORY. 93L470/93L471
NOTES
1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions,
2. The specified LIMITS represents the "worst case" value for the parameters. Since these "worst case" values normally occur at the temperature and supply
. voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are at VCC ~ 5.0 V, TA ~ 25"C, and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and a two minute warm-up. Temperature range of
operation refers to case temperature for Flatpaks and ambient temperature for all other packages. Typical thermal resistance values of the package at
maximum temperature are:
0JA (Junction to Ambient) (at 400 fpm air flow) ~ 50"C/Watt, Ceramic DIP; S5"C/Watt, Plastic DIP, NA, Flatpak.
0JA (Junction to Ambient) (still air) ~ 90"C, Watt, Ceramic DIP; 110"C/Watt, Plastic DIP, NA, Flatpak.
0JC (Junction to Case) ~ 25"C/Watt, Ceramic DIP; 25"C/Watt, Plastic DIP; 15"C/Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.
S. tw measured at tWSA ~ MIN, twSA measured at tw ~ MIN.
7. Duration of short circuit should not exceed one second.

TYPICAL ELECTRICAL CHARACTERISTIC CURVES
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE (OUTPUT HIGH
Z STATE) (93L471 ONLY)

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE (OUTPUT HIGH)
(93L470 ONLY)
Vee

-'=

5.0 V

TA"'-

E 0.5
,

I
U

~

I

~25°?

TA='-550~~
TA"'+125"~

<

~,
~

z

1---+-+-1TA = 25°C.-rnrr--.
1---+-+-1TA = ~50C -f-'tIl-l---I

~
~
~

u

-0.5

~

[;

TA

,

=

0 -1.0

TA

~

~

-55"C

o,

,

O
,+25 C

~
p

TA""" +125°C

9-1.5

1~-+-~-t--+-~~t--+

_~ IIf

-2·~lU.0.JL.-'---""1.L.0-'2.!..0-3,-1.0'-""4L..O-'5.!..0'-6"'.0

o

VOUT - OUTPUT VOLTAGE - V

Your - OUTPUT VOLTAGE - V

93L470/93L471
POWER SUPPLY CURRENT
VERSUS TEMPERATURE
105
100

Ii :r-- -- -80

~

75

~

70

,

6S

--

Vee

K

~

5.5 V

Vee 05.0V

...... r---.. IZ

7" r--...: .......... i'-.
.........

Vee - 4.5 V

.:::--.

U

!d

60

55
50

25

25

50

75

100

125

TA - AMBIENT TEMPERATURE - °C

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE

ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE

100...---,---r--r---,----,

120

,

~ 110

I 100

1=

;R/

-

90

I
/

~

~
~

80
70

o.,~....&.1Y
./

60

,/

50
,

40

$

30
20

/

V

V
o

100 200 300 400 500 600 700 800 900 1 000
LOAD CAPACITANCE - pF

VIN - INPUT VOLTAGE - V

7-161

•

FAIRCHILD ISOPLANAR TTL MEMORY -93L470/93L471
AC TEST LOAD AND WAVEFORM

LOADING CONDITIONS

INPUT PULSES

ALL INPUT PULSES

VCC

3Jp-p--;f----. ----~--90%

Q

t -/ ~ - - - - - - - - ~\

3000
DDUT

DDUT

----..1

GND

93470
93L470
93L471
93471

93471

30pF

600n

t pop
V
_t_-, --------

LOAD A

-10%

1....--.- 10 ns

-..1

GND

LOADB

-10%

I

3.5

-

-

----.[

30pF

lkn

93L471

1..- 10 ns

--I

I............... 10 ns

1-,0ns

WRITE MODE

/
J 1\

cs
CHIP SELECT

/ 1\

AO ~ A11
ADDRESS
INPUTS

/ 1\

/ 1\

DIN
DATA INPUT

/ 1\

WE
WRITE ENABLE
'WSD-

-

~tWSA

•

twscs

I-·w-I
1\

-- twsl-~

LOAD A

-..

t----'WHD

---------.

. . . . - tWHA-------'

~tzws

LOAD B
93471/93L471

tWHCS

~

i\

93470/93L470
DOUT
DATA OUTPUT

J 1\

Y

...-tWR----'

¥-05V

\------ I

v

n u

LOAD A
93471/93L471

i

O-5V

- - ,

I

(All above measurements referenced to 1_5 V unless otherwise indicated)

NOTE: Timing Diagram represents one solution which resuijs in an optimum cycle time_ Timing may be changed to fit various applications as long as the worst
case limits are not violated.

7-162

FAIRCHILD ISOPLANAR TTL MEMORY. 93L470/93L471
READ MODE
PROPAGATION DELAY
FROM CHIP SELECT
PROPAGATION DELAY
FROM ADDRESS INPUTS

AO - A11

/

ADDRESS INPUTS /

'\

'----DATA
OUTPUT

DATA

LOAD A

OUTPUT

93470;71
93L470171

WRITE ENABLE TO HIGH Z DELAY

5V

Wi
WRITE E"N:;:"::;"'-_ _ _"\
-'l-1.5 V

750 !'!
Dour

93L471
93471

_IZWS-

t~o

Dour

5pF

DATAOUTPur

'O"LEVEL

Dour

_t--!O.5V

DATA OUTPUT

'----..!!!~

LoadC

PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

CHIP SELECT

os

1-

---

1SV

-',"cs-

'---;IW

Dour

__ ! 0.5 V

DATA OUTPU_'_ _'_'O'_''_"_'_'_ _ _ _-,.."I~

-,.---Iosv

Dour
DATA OUTPUT

~--~~

(All tzxxx parameters are measured at a delta of D,S V from the logic
level and using Load Co)

7-163

•

TTL ISOPLANAR MEMORY 93470/93471
4096 x I-BIT FULLY DECODED RANDOM ACCESS MEMORY

DESCRIPTION - The 93470 and 93471 are 4096-bit TTL Read/Write Random Access Memories organized 4096 words by one bit. The devices are identical except for
the output stage. The 93470 has an uncommitted collector output, while the 93471
/:las a 3-state output. The devices have full decoding on chip, separate Data Input and
Data Output lines and active LOW Chip Select lines. They are designed for high-performance main memory application and can be used to replace four 1024-bit RAMs.
•
•
•
•
•
•
•
•
•

LOGIC SYMBOL

,.

'7

'S

Ao
A,

FULL MIL AND COMMERCIAL RANGES
ORGANIZATION-4096 WORDS X 1 BIT
READ ACCESS TIME-30 ns TYPICAL
CHIP SELECT ACCESS TIME-15 ns TYPICAL
UNCOMMITTED COLLECTOR OUTPUT-93470
3-STATE OUTPUT-93471
NON·INVERTING DATA OUTPUT
POWER DISSIPATION-0.15 mW/BIT TYPICAL
REPLACES FOUR 1024 X 1 RAMs

A2

A3
A4

AS
A.

'0
11

As

'2

AS

'3

,.

PIN NAMES

93470/93471

A7

A,O
A11

DOUT

CS

Chip Select Input

AO - A11

Address Inputs

WE

Write Enable

VCC ~ Pin 18

D,N

Data Input

GND ~ Pin 9

DOUT

Data Output
CONNECTION DIAGRAM
DIP (TOP VIEW)

LOGIC DIAGRAM
~-----------9~ro-~

,r-

: ---l>--OQUT
L _____________

,

~_~

r-------------~-,
I
93471
I

Dour

ADDRESS INPUTS

7-164

DOUT

AO

Vec
DIN

A,

Cs

A2

We

A3

A11

A4

A,O

AS

Ag

A6

AS

GND

A7

FAIRCHILD ISOPLANAR TTL MEMORY. 93470/93471
FUNCTIONAL DESCRIPTION- The 93470 and 93471 are fully decoded 4096-bit Random Access Memories organized
4096 words by one bit. Word selection is achieved by means of a 12 -bit address, AO through All.
The Chip Select input is provided for logic flexibility. For larger memories, the fast Chip Select access time permits the decoding of Chip Select, CS, from the address without increasing address access time.
The read and write operations are controlled by the state of the active LOW Write Enable,WE (Pin 15). With WE held LOW
and the chip selected, the data at DIN is written into the addressed location. To read, WE is held HIGH and the chip selected.
Data in the specified location is presented at the Data Output.
The 93471 has 3-state outputs which provide drive capability for higher speeds with high capacitive load systems. The
third state (high impedance) allows bus organized systems where multiple outputs are connected to a common bus.
The 93470 has uncommitted collector outputs to allow maximum flexibility in output connection. In many applications,
such as memory expansion, the outputs of several 93470s can be tied together. In other applications the wired-OR is not
used. In either case an external pull-up resistor of value RL must be used to provide a HIGH at the output when it is off.
Any value of RL within the range specified below may be used.

VCC(max)

VCC(min) - VOH

IOL-FO (1.6)

N (ICEX) + F 0 (0.04)

RL is in kO
N = number of wired-OR outputs tied together
F 0 = number of TTL Unit Loads (U.L.) driven
ICEX = Memory Output Leakage Current in mA
VOH = Required Output HIGH level at Output Node
IOL = Output Low Current

The minimum value of RL is limited by output current sinking ability. The maximum value of RL is determined by the output and input leakage current which must be supplied to hold the output at VOH.

TRUTH TABLE
INPUTS

OUTPUTS
93470
o.e.

93471
3-STATE

MODE

es

WE

DIN

H

X

X

H

HIGH Z

Not Selected

L

L

L

H

HIGH Z

Write "0"

L

L

H

H

HIGH Z

Write "1"

L

H

X

DOUT

DOUT

Read

H ~ HIGH Voltage; L ~ LOW Voltage; X ~ Don't Care (HIGH or LOW)
HIGH Z = High Impedance;
= Open Collector

ac

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
Input Voltage (dc)'
Input Current (dc)'
Voltage Applied to Outputs (output HIGH)"
Output Current (dc)

-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.50 V
+20mA

*Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (Vee)

PART NUMBER
MIN

TYP

MAX

AMBIENT TEMPERATURE (TA)
(Note 4)

93470xe, 93471 XC

4.75 V

5.0 V

5.25 V

ooe to +75°e

93470XM,93471XM

4.50 V

5.0V

5.50 V

-55°C to +125°e

x = package type, F for Flatpak, 0 for Ceramic Dip, P for Plastic Dip. See Packaging Information Section for packages available on this product.

7-165

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93470/93471
DC CHARACTERISTICS: Over Operating Temperature Ranges (Notes 1-4)

SYMBOL

LIMITS

CHARACTERISTIC

TYP

MIN

(Note 3)

VOL

Output LOW Voltage

V,H

Input HIGH Voltage

V,L

Input LOW Voltage

1.5

',L

Input LOW Current

0.3
2.1

"H

Input HIGH Current

VCD

Input Diode Clamp Voltage

'CEX

Output Leakage
Current

93470

IOFF

Output Current
(HIGH Z)

93471

VOH

Output HIGH
Voltage

93471

lOS

Output Current
Short Circuit
to Ground

93471

ICC

Power Supply
Current

UNITS

CONDITIONS

MAX
0.50

= 16 rnA

V

VCC = MIN, IOL

V

Guaranteed Input HIGH Voltage
for all Inputs

0.8

V

Guaranteed Input LOW Voltage
for all Inputs

-250

-400

p.A

VCC

1.0

40

p.A

VCC

1.0

rnA

VCC

= MAX,
= MAX,
= MAX,

-1.0

-1.5

V

VCC

=MAX, liN =-10 rnA

1.0

100

p.A

VCC

= MAX,

VOUT

= 4.5

V

VCC

= MAX.
= MAX,

VOUT

VCC

= 2.4
= 0.5

V

VCC

= MIN,

1.6

50
p.A

-50
2.4

V

-100

93470/71 XC

110

93470/71 XC

130

93470/71XM

100

93470/71XM

140

rnA

170
rnA

V ,N
V ,N
V ,N

= 0.4 V
= 4.5 V
= 5.25 V

VOUT

V

IOH = -5.2 rnA

V CC = MAX, Note 7
TA =75°C

VCC = MAX,

TA = O°C

All Inputs and

TA = 125°C

Output Open

TA = -55°C

180

AC CHARACTERISTICS: Over Guaranteed Operating Ranges (Notes 1-6)

93470/71 XC
SYMBOL
READ MODE
tACS
tRCS
tZRCS
tAA

CHARACTERISTIC

MIN

93470/71XM

TYP
MAX MIN
(Note 3)

TYP
MAX
(Note 3)

UNITS

CONDITIONS

DELAY TIMES
Chip Select Access Time
Chip Select Recovery Time (93470)
Chip Select to HIGH Z (93471)
i Address Access Time

WRITE MODE

DELAY TIMES

tws
tzws
tWR

Write Disable Time (93470)
Write Disable to HIGH Z (93471)
Write Recovery Time

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS

Write Pulse Width (to guarantee write)
Data Set-Up Time Prior to Write
Data Hold Time After Write
Address Set-Up Time
Address Hold Time
Chip Select Set-Up Time
Chip Select Hold Time

C,
Co

Input Pin Capacitance
Output Pin Capacitance

15
25
25
30

30
35
35
45

15
25
25
30

35
45
45
60

25
25
25

35
35
35

25
25
25

45
45
45

ns

ns

INPUT TIMING REQUIREMENTS
30
10
5
10
5
5
5

20
5
0
5
0
0
0
4
7

7-166

45
15
10
15
10
10
10
5
8

See Test Circuit
and Waveforms

20
5
0
5
0
0
0
4
7

See Test Ci rcu it
and Waveforms

ns

5
8

pF

Measure with
Pulse Technique

FAIRCHILD ISOPLANAR TTL MEMORY. 93470/93471
NOTES:
1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified LIMITS represent the "worst case" vaLue for the parameters. Since these "worst case" values normally occur at the temperature and supply voltage extremes. additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
3. Typical values are atVcc =5.0V, TA =+25°C, and MAX loading.
4. The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per ininute. For military range there is an additional requirement of
a two minute warm-up. Temperature range of operation refers to case temperature for Flatpak~ and ambient temperature for all other packages. Typical thermal resistance values of the package at minimum term perature are:
BJA(Junction to Ambient)(at400fpm airflow) = 50°C/Watt, Ceramic DIP; 65°C/Watt, Plastic DIP; NA, Flatpak.
BJA (Junction to Ambient)(still air) = 90° c/Watt, Ceramic DIP; 110° C/Watt, Plastic DIP; NA, Flatpak.
BJC (Junction to Case) = 25°C/Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 15°C/Walt, Flatpak.

5. The MAX address access time is guaranteed to be thw "worst case" bit in the memory using a pseudo random testing pattern.
S. tw measured at tWSA = MIN, tWSA measured at tw = MIN.
7. Duration of short circuit should not exceed one second.

TYPICAL ELECTRICAL CHARACTERISTIC CURVES
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE (OUTPUT HIGH
Z STATE) (93471 ONLY)

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE (OUTPUT HIGH)
(93470 ONLY)

r

1.0 r-...,.-,--r----r--,-r---,

5

vcc =

5.0 V

TA

2~25ob

f--+-+-+--+T:Ae~+~:::~~

J
10'e~
, 'i>..

t
TA

=

C-'---

25°C
I

TA

=

C--

75"C

~ ~0.5H-ff-f-+-+--+-+-+--I

~

TA

=

~65°C

~ -1.0 H-ffci:-:;T:-A:--,Cc+2::05-::
oc - i - - j - - - j - - l
O"",

,

9"

~-1.5 f+lH_T:..cA_~r-+1_2_5'rC_+---i_+-i

·1

-2~1"::.0-"--'--:"'.0::--::2'::.0-::3-':.0-4:-'-.0:--::'5.70---:!'.O
VOUT

~

OUTPUT VOLTAGE

1

1111
o
VOUT .. OUTPUT VOLTAGE

V

~

V

93470/93471
POWER SUPPLY CURRENT
VERSUS TEMPERATURE
180
178

I
U

~

"~
~

U

u

160
150
140
130

r--

r--

120

--

Vee

--<.

7" r--..:

4.5 V

I
I

90
80

50

25
TA

5.0 V

......... y,

Vee

100

5.5 V

Vcc

I
I
25

50

" i'--.:::--........

75

AMBIENT TEMPERATURE

100

ADDRESS ACCESS TIME
VERSUS LOAD CAPACITANCE

100

~

L

~

80

So

30

20

/

9~tt.1V
./

U

~-200
~

V

ro

V

=tl~5"C~ ~~A~~ +25'C
TA =-55°C
~

~

f*-

TA

f--TA

Z

,+125°C

=t 25OC

=-30 0

Iv
o

TA

~ ~10 0

;/
50

0

,

II

70

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE
Vec '"

RI

I-- I-

twtt

I+-tWSA

I

-- .zwsr

DATA _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~

J7

OUTPUT

INPUT _ _ _ _ _ _....;o;.;p..;E;;;N;...I_ _ _ _ _ _ _
DATA

tWHA---+

-- b=~'----}

'WR

OPEN

-c~ VALI:~:Dp:j)r

'WHD OPEN

\

~

J

~l

~.SW
OUTPUT
OATA

'\

I

I

r'

OPEN
tWH~

tcsw

WSA

,

MODE

C=.WSD
OPEN

'NPUT
DATA

l·WHD

(\.o.._ _......J)

OPEN

VALID INPUT DATA

_

DON'T CARE .NPUT COND.T'ON

(All above measurements reference to 1.5 V)
this parameter is necessary to guarantee the output at high Z state during the write
cycle using WE as the write strobe and while

tt

OPTIONAL
WRITE

CS

is LOW.

tw is measured from the falling edge of either CS or WE (whichever is last to go LOW) to
the rising edge of either CS or WE (whichever is the first to go HIGH).

7-171

(

•

FAIRCHILD ISO PLANAR TTL MEMORY. 93475
READ MODE

PROPAGATION DELAY FROM ADDRESS INPUTS

PROPAGATION DELAY FROM CHIP SELECT

ADDRESS

cs

~-tAcs1--F
LOADB

VALID OUTPUT DATA

NOTE: WE must remain HIGH during READ cycle

PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

LOAD B
DATA
110

(~

>

OPEN

______________- J
LOAD A

{All above measurements reference to 1.5 V}
(All tzxxx parameters are measured at a delta of 0.5 V from the logic level)

AC TEST LOAD AND WAVEFORM

-4-,..------------.-~'
.- --

ALL INPUT PUlses

T

VCC

3.5V.P·P

t -

6000
DOUT

93475

12000

GND

DDUT

~ 15 pF

93475

I

r- - -- - - - - r
I_IOn.

,.!.,_~n~_

_I

GND

_I

1_ 10 n.

Load B
LOADING CONDITIONS

INPUT PULSES

7-172

90%

-

10%

I_IOn.

----It -'"

__+_-, --------

-

Load A

15 pF

1 ktl

_I

I

_I

,-90%

I_IOns

FAIRCHILD ISOPLANAR TTL MEMORY • 93475
TYPICAL ELECTRICAL CHARACTERISTIC CURVES

OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH Z STATE)

INPUT CURRENT VERSUS
INPUT VOLTAGE
VERSUS TEMPERATURE
100

..

E
I

Vee.::: 5.0 V

t=-ko"cTA 25"C
I
'i'>
TA 75°C

7

I-

I

tEa:
a:

::>

CJ

..

E

;....

0

I

!z
~

..

~

::>
I~-200

I*-TA -,+125"C
I--TA "1+ 25 "C

~

I

I

I-

z

1

=-300

o
-1

o

Iff

-400
-2.0

4
VOUT - OUTPUT VOLTAGE - V

TA = -55°C

~

CJ

o

::>

~

-100

a:

~

9

I

TA - +1~5"C ..... 'f!~A,= +25"C

f:4t--TA =-55"C

IU
o

I

2.0

4.0

6.0

8.0

VIN - INPUT VOLTAGE - V

•
7-173

ISOPLANAR INTEGRATED
INJECTION LOGIC MEMORY 93481/93481A
4096 x I-BIT DYNAMIC RANDOM ACCESS MEMORY

DESCRIPTION - The Fairchild 93481 and 93481 A are address multiplexed fully decoded
4096 x 1 bipolar dynamic RAMs. The inputs and output are conventional TTl. The first
five address inputs are latched with AE and the last seven are applied after AE and are
used in conventional "ripple-through" fashion.

LOGIC SYMBOL

5 9

•
•
•
•
•
•
•
•
•
•
•

4096 X 1 BIT PER WORD
-FULLY TTL COMPATIBLE - NO SPECIAL CLOCK DRIVERS REQUIRIiD
ADDRESS MULTIPLEXED
ON-CHIP DATA LATCH
STANDARD 16-PIN DUAL IN·LINE PACKAGE
32·LINE REFRESH - 2 ms REFRESH INTERVAL
ACCESS TIME 120 ns MAX (93481), 100 ns MAX 193481A)
CYCLE TIME 280 ns MIN 1934811. 240 ns MIN 193481A)
POWER DISSIPATION 45 mW STANDBY, 350 mW TYPICAL AT MIN CYCLE TIME
3-5TATE OUTPUT
TEMPERATURE RANGE O°C - 70°C

PIN NAMES
AO-A4
A5-A6
CS1, CS2
DOUT
LE
DIN
AE
WE

10

11

AD
A,
A2
A3

,.

A.

's

A6

'3

93481/93481A

AS

Multiplexed Address Inputs
Non-multiplexed Address Inputs
Chip Select Inputs
Data Output
Output Latch Enable
Data Input
Address Enable
Write Enable

DOUT

LOGIC DIAGRAM
~

12

CONNECTION DIAGRAM
DIP(TOP VIEW)

AE------------~--------------------,

AD

Vee

A,

A6

A,

A5

A3

A,

cs,

AE

DATA LATCH

lE

o0®~~

A2
A3
A,
@AS

@0

@

As

vee

- Pin 16

WE

D,N

LE

GND

Pm 8

@

@

®

0

Pin Numbers

7-174

CS 1CS 2

®®

WE

DOUT

D,N

GNO

CS2

FAIRCHILD ISOPLANAR TTL MEMORY. 93481/93481A
FUNCTIONAL DESCRIPTION

Addressing - The storage array is organized in 32 rows of 128 cells. Twelve bits of address information are required to
uniquely define one storage cell out of 4096. To accomplish this within the constraints of a 16·pin package, the 93481 /93481 A
operates in conjunction with external addressing logic to examine sequentially five bits (ROW address) and then seven bits
(COLUMN) of address information. Signals on the AO-A4 inputs must be in the desired state at least a set·up time tAS
before the AE signal goes HIGH and must then remain fixed for at least the hold time tAH. These timing requirements insure
that the positive·going AE signal latches the AO - A4 information into the internal row addressing logic. To complete the
addressing operation, the AE signal must remain HIGH and the external addressing logic must present the final seven bits
of the address on the AO - A6 inputs.
Read Operation - The Write Enable input WE must be in the H IG H state for a read operation. After addressing a cell as
outlined above, its content will exit via the output latch, which is transparent when the Latch Enable input LE is HIGH. The
access delay tCAA is measured from the time that the column address becomes valid, as is the latch input set·up time tALS.
This latter parameter defines the earliest time that LE can go LOW and still insure that the desired data will be latched in.
The latest time that LE can go LOW, for the purpose of retaining the data, is determined by two constraints. LE must go
LOW no later than tALH, measured with respect to an address change. Also, LE must go LOW no later than tLH, which is
measured with respect to the negative·going edge of AE. If the LE signal timing satisfies these constraints, the latch will retain
the data for as long as desired. A subsequent read or write operation will not affect the state of the latch so long as LE
remains LOW. If LE subsequently goes HIGH while AE is LOW, the latch will no longer retain the data and its output will
go to the high impedance state. It will then remain in this condition so long as AE remains l.OW, regardless of the LE input
signal.
If either or both Chip Select inputs are HIGH, DOUT will be in the high impedance state.
Write Operation - After addressing a cell in the manner previously described, a LOW signal on WE will cause the data on the
DIN input to be stored, provided that both Chip Select inputs are LOW. To avoid writing in the wrong cell, WE should not
go LOW before the column address set·up time tWSA, and the address inputs should not be changed until after the address
hold time tWHA. Both the set·up time and hold time for DIN are measured with respect to the trailing (i.e., positive·going)
edge of the write pulse. If LE is HIGH during a write operation, DOUT will go HIGH regardless of :he state of DIN. After WE
goes HIGH at the end of a write pulse, the DOUT signal will be the same as the data just stored, assuming that the addres,s
remains constant and both Chip Select inputs remain LOW.
Refresh - A normal read or write cycle causes all cells in the addressed row to be refreshed. Also, cycling AE such that the
tTA and tTR requirements are met refreshes all cells in the addressed row, regardless of the WE and CS input signals. Each
row must be refreshed at intervals of 2 ms or less.
Power Dissipation - There are three distinct power states in the 93481 /93481 A. When AE is HIGH the ICC current is typically
100 mAo When AE is LOW, ICC is typically 20 mA if the output latch is retaining data or 10 mA if the latch is not retaining
data. When AE goes from LOW to HIGH the resultant increase in ICC is not accompanied by any significant overshoot above
the quiescent value. In a cyclical mode corresponding to minimum cycle time the average ICC is 65 mAo No significant
current transients occur when inputs other than AE change state.

•
7-175

FAIRCHILD ISOPLANAR TTL MEMORY. 93481/93481A
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
Input Voltage (de)
Input Current (de)
Voltage Applied to Output (Output High)
Output Current (de) (Output Low)

-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.5 V
+20 mA

GUARANTEED OPERATING RANGE
SUPPLY VOLTAGE IVcc)
MIN

I

TYP

I

MAX

AMBIENT TEMPERATURE ITA)
INote 4)

4.75 V

I

5.0 V

I

5.25 V

O°C to +70°C

PART NUMBER
93481 /93481 A

DC CHARACTERISTICS: Over Operating Temperature Ranges INotes 1,2,4)
LIMITS
SYMBOL

CHARACTER ISTIC
MIN

TYP
INote 3)

UNITS

CONDITIONS

MAX

VOL

Output lOW Voltage

VIH

Input HIGH Voltage

Vil

Input LOW Voltage

1.5

0.8

IlL

Input lOW Current

-100

-400

!lA

10

40

!lA

VCC - MAX, VIN - 4.5 V

1.0

mA

VCC - MAX, VIN - 5.25 V

100
-50

!lA

VCC - MAX, VOUT

-10

!lA

VCC = MAX, VOUT = 0.5 V

-55

-100

mA

IIH

Input HIGH Current

10FF

Output Current IH IGH Z)

0.3
2.1

10

Output Current Short Circuit
lOS

to Ground

VOH

Output HI G H Voltage

VCD

Input Diode Clamp Voltage
Power Supply Current

ICC

2.4

0.5

1.6

3.0
-1.0

V

VCC = MIN, 10l = 16 mA

V

Guaranteed Input HIGH Voltage for all Inputs

V

Guaranteed Input LOW Voltage for all Inputs

V
-1.5

V

VCC - MAX, VIN = 0.4 V

2.4 V

VCC = MAX, Note 7
10H - -5 mA, VCC - MIN
VCC = MAX, liN - -10 mA

65

mA

MIN CYCLE TIME

100

mA

AE = HIGH

All Remaining Inputs

9.0

mA

AE - lOW, LE - HIGH

Grounded

VCC = MAX,

NOTES:

1. Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
2. The specified LIM ITS represents the "worst case" value for the parameters. Since these "worst case" values normally occur at the tern·
perature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system
operating ranges.
3. Typical limits are at V CC = 5.0 V, T A = +25° C, and MAX loading.
4. The Operating Ambient Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute and a two minute
warm·up. Typical thermal resistance values of the package at maximum temperature are:
8JA IJunction to Ambient) lat 400 fpm air flow) = 50°C/Watt, Ceramic DIP; 65 Q C/Watt, Plastic DIP; NA, Flatpak.
8JA IJunction to Ambient} Istill air) = 90°C/Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
8 JC IJunction to Case) = 25°C/Watt, Ceramic DIP; 25° C/Watt, Plastic DIP; 10° C/Watt, Flatpak.
5. The MAX address access time is guaranteed to be the "worst case" bit in the memory using a pseudo random testing pattern.

6. tw measured at tWSA

= MIN, tWSA, tWSDE, and tWHD measured at tw = MIN.

7. Duration of short circuit shoUld not exceed one second.
8. Timing Diagram represents one solution which results in an optimum cycle time. Timing may be changed to fit various applications as long
as the worst case limits are not violated.

7-176

FAIRCHILD ISOPLANAR TTL MEMORY. 93481/93481A
AC CHARACTERISTICS OVER GUARANTEED OPERATING RANGES (Notes 5, 61
934Bl
SYMBOL

CHARACTERISTICS
MIN

MAX

TYP

UNITS

MULTIPLEX
tAS

Row Address Set-up Time

tAH

Row Address Hold Time

0

tTA

AE Active Time

140

tTR

AE Recovery Time

140

45

ns

READ CYCLE
tCAA

Column Address Access Time

tCAH

Output Valid Time After Column Address

10

75

tCSA

Chip Select Access Time

35

tCSR

Chip Select Recovery Time

30

tTH

Output Valid Time After AE

15

no

DATA LATCH
tALS

Address Set-up Time Before LE

tALH

Address Hold Time After LE

tLH

AE Hold Time After LE

tLR

Output Recovery from LE

35

tDLA

Output Valid Time After LE

10

75
0
ns

-10

WRITE CYCLE
tw

Write Pulse Width

25

twSA

Address Set-up Time

35

tWHA

Address Hold Time

tWSCS

Chip Select Set-up Time

twHCS

Chip Select Hold Time

twHT

AE Hold Time After WE

tWSDE

Data In Set-up Time Before End of WE

45

tWHD

Data In Hold Time After WE

30

tws

Output Disable Time After WE

tWR

Output Recovery Time After WE

40

CIN

Input Pin Capacitance

3.0

COUT

Output Pin Capacitance

5.0

5
0
ns

0
40

35

pF

USER TIMES
Row Column Addre.. Change Time

tRC
tMOD

Data Modify Time

tRFSH

Refresh Period

ms

2

AC TEST LOAD AND WAVEFORMS

LOADING CONDITIONS

INPUT PULSES
ALL INPUT PULSES

1---:--1

vee

t --- I --------------

(

3.5 V p . p

t-

300H
DOUT

93481'
93481A

t~

30pF

-

GND.J=-

I

I

~:

I

I
I

I
l.-l0ns

-,.-

7-177

~I

1....... ,0 ns

- - -10%

I
I

------1-__
-I

-------- ------

~II
!
I

-=

I
I

-T--------------.-

~-------GND

___ - _90%

1,,-'0ns

'0%

- 1 - --90%
II

1

~I

1
1-4-10 ns

•

FAIRCHILD ISOPLANAR TTL MEMORY. 93481193481A
AC CHARACTERISTICS OVER GUARANTEED OPERATING RANGES {Notes 5, 6t
SYMBOL

934B1A

CHARACTERISTICS
MIN

TYP

MAX

UNITS

MULTIPLEX
tAS

Row Address Set-up Time

tAH

Row Address Hold Time

tTA

AE Active Time

110

tTR

AE Recovery Time

130

0
35

ns

READ CYCLE
tCAA

Column Address Access Time

tCAH

Output Valid Time After Column Address

10

tCSA

Chip Select Access Time

35

tCSR

Chip Select Recovery Time

30

tTH

Output Valid Time After AE

15

65
ns

DATA LATCH
tALS

Address Set-up Time Before LE

tALH

Address Hold Time After LE

tLH

AE Hold Time After LE

tLR

Output Recovery from LE

35

tDLA

Output Valid Time After LE

10

65
0
ns

-10

WRITE CYCLE
tw

Write Pulse Width

25

tWSA

Address Set-up Time

35

tWHA

Address Hold Time

tWSCS

Ch ip Select Set-up Time

tWHCS

Chip Select Hold Time

tWHT

AE Hold Time After WE

tWSDE

Data In Set-up Time Before End of WE

35

tWHD

Data In Hold Time After WE

30

tws

Output Disable Time After WE

tWR

Output Recovery Time After

CIN

Input Pin Capacitance

3_0

COUT

Output Pin Capacitance

5_0

5
0
ns

0
10

35

m

40
pF

USER TIMES
tRC

Row Column Address Change Time

tMOD

Data Modify Time

tRFSH

Refresh Period

2

7-17B

ms

FAIRCHILD ISOPLANAR TTL MEMORY. 93481/93481A
READ-CYCLE - DATA NOT LATCHED

Addressing is accomplished by multiplexing the 5 bits of row address and 5 bits of the 7 bit column address on the same pins
(Ao through A4, pins 1, 2, 3, 4 and 13). Assume the 5 bits of row address are stable at time tlO (the beginning of the cycle).
At time t11 (tAS after tlO) the address has been internally set up and the AE signal rise strobes the row address and latches it
into the memory. The row address must be held stable until t12 (tAH after the AE rise) to assure proper operation. At time
t12, the address input lines can change and the 7 bit column address can be switched on to the address input lines Ao through
A6. The memory can tolerate an instantaneous change; however, the user circuitry will require some time (tRC) to accomplish
this change. Assuming this change is accomplished at t13, the part now acts like a 128-bit static RAM. With the column
address valid at t13 the output becomes valid at t15 with the data from the addressed cell. The time from t13 to t15 is tCAA
(column address access time). CS 1 and CS 2 must both be active low at t14 (tCSA before t15) for the output to be read at
t15. The chip selects can go low any time prior to t14. The output will remain valid as long as the chip is selected, the column
address is valid and AE remains high. The output will be in the high impedance state at time tCSR after the chip select goes
high. If the address is changed to a new column address with AE remaining high the same timing is applicable where the new
address valid point corresponds to t13.
If AE goes low at t16, the output will remain valid until t18 (tTH after t16). The column address must be held valid until
t17 (tCAH prior to t18) to guarantee the output is valid until t18. AE goes low at t16 and is held low until t21 (at least tTR
after t16). t21 corresponds to t11 in the first cycle.
Full Cycle Address Access Time is tAS + tAH + tCAA + tRC.

'"
ADDRESS

'12

~~MV,_

ADDRESS ENABLE

AE

DATA

__________J

'16

'14

____

'18

'20

'21

~C_O_LU_M_N ~ +-J~~~~~~~~~~Ir--+-----1
ADDRESS

____

__

~+_----___1-->~"\~I--+_--j_-'TR------/

our

CHIP SELECT

os

•

DATA LATCH OPERATION

When a column address is valid (t33) either after a row address, as illustrated, or after a previous column address, the Data
Latch may be used to hold the data read from the addressed cell. LE may be activated low at tALS after t33 or later (t3L1).
The address may change no less than tALH after (t37). The AE signal must be retained active high until t36 (defined by t3L 1
+ tLH). tLH is guaranteed negative meaning the AE signal may go low before LE goes low (i.e., t36 may be earlier than t3L1).
A useful mode of operation is for LE and AE to be tied together. The output is controlled by the state of the data latch
circuit and the chip select signals which can be activated at any time. The output will appear on the output pin tCSA after
chip select signal goes low. If the chip select signal goes low earlier in the cycle, the output data will be read tCAA after t33 as
7-179

FAIRCHILD ISOPLANAR TTL MEMORY. 93481/93481A
in the non·latched operation, but will remain valid until LE goes positive. If LE goes low while AE is low, an open is read at
the output regardless of the state of CS, and CS2.
When AE is low and Data has been latched the Data Output can be returned to the open state by either returning CS" CS2
or LE to the high state. The output will be open at t3L6, tCSR after CS, or CS2 is made high at t3L4 or tLR after LE is made
high at t3L5. If AE is active high with data latched then CS, or CS2 high will again cause the output to be open; or if LE
alone is made high, the latched data will remain valid for time tOLA on the output.

t3L 1

'36

'37

~----+---+-----I
COLUMN
ADDRESS

ADDRESS

ADDRESS ENABLE
AE

r--~ tALS _____________ ......- t L H - '

t3L6
1

LATCH ENABLE

1

,-.1-

LE

'-----+--+----' I
CHIP SELECT

'LR

.-

------------------~

Os

I

tCSR

i'DLAI-OPEN- (

DATA OUT

O::':[;'oT

»~OPEN----

'------"""~

WRITE OPERATION
When a column address is valid (t53) either after a row address as illustrated or after a previous column address, new data
may be written into the addressed cell. The write signal may go low (t5W2) tWSA after the column address is valid (t53).
The write pulse must be at least tw wide to assure writing. The CS, and CS2 must both be low (t5W') at least twscs before
the fall of WE (t5W2) and must remain low until at least tWHCS after the rise of WE (t5W5). AE must remain high until at
least tWHT after the rise of WE (t54). The column address must remain valid until at least tWHA after the rise of WE (t5W6).
Data .In must be valid at least tWSOE before the rise of WE and remain valid until at least tWHO after the rise of WE. Note
that Data In timing is independent of the fall of WE (t5W2).

COLUMN
ADDRESS

ADDRESS

ADDRESS ENABLE
AE

WRITE ENABLE

WE

DATA IN

7-180

FAIRCHILD ISOPLANAR TTL MEMORY. 93481/93481A
EXAMPLE OF SUCCESSIVE COLUMN CYCLES

Successive operations at different column addresses on the same Row may be performed much more rapidly than a cycle
requiring a new Row Address. This example illustrates a Read operation at Column Address 1 followed by a Write operation
at Column Address 2. The Data Latch is used to hold the Output Data from Column Address 1 through the Write Cycle at
Column Address 2. This kind of operation could be used to enter modified Data from Address 1 into the cell at Address 2.

AD

~\

,@

COLUMN ADDRESS 1 VALID

-

....---tCSA~

CHIP SEL ECT

1\

CS

•

tCAA

DATA

•

V~

'RC

~

OUTPUT VALID

OPEN

OUTPUT

COLUMN ADDRESS 2 VALID

tALS~

1\

COLUMN ADDRESS 1

......-.--tALH ______________

LATCH
ENABLE
LE

\
..-tWSA~ ~tw~

~tWHA

_______

E~~~LEE---------------------------""

DATA IN

READ·MODIFY-WRITE OPERATION

A Read-Modify-Write Cycle is performed by a normal Read followed by establishing DIN and providing a WE signal. Since
there are no special timing signals required for column operation this cycle is like a normal static Bipolar RAM. The Data
Output from the read cycle remains valid until tws after the WE is brought low at which time it goes active high. If LE is
high the output will again be valid tWR after the WE is brought high. If LE is low the Data output will remain valid with the
latched Data throughout the write portion of the cycle.
Read-Modify-Write cycle time is:

ADDRESS

tAS + tAH + tRC + tCAA + tMOD + tWSDE + tWHT + tTR

COLUMN ADDRESS

~tcAA---"'~~1

CHIP~LECT

CS

DATA OUT

DATA IN

WRITE ENABLE

WE

7-181

•

9403
FIRST-IN FIRST-OUT (FIFO) BUFFER MEMORY
FAIRCHILD TTL MACROLOGIC

DESCRIPTION - The 9403 is an expandable fall-through type high-speed First-In
First-Out (FIFO) Buffer Memory optimized for high speed disc or tape controllers and
communication buffer applications. It is organized as 16 words by four bits and may be
expanded to any number of words or any number of bits (in multiples of four). Data may
be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories.

LOGIC SYMBOL

7

6

5

4

3

The 9403 has 3-state outputs which provide added versatility and is fully compatible with
all TTL families.
9 --0 IES

•
•
•
•
•
•

10 MHz SERIAL OR PARALLEL DATA RATE
SERIAL OR PARALLEL INPUT
SERIAL OR PARALLEL OUTPUT
EXPANDABLE WITHOUT EXTERNAL LOGIC
3-STATE OUTPUTS
FULLY COMPATIBLE WITH ALL TTL FAMILIES

•

SLIM 24-PIN PACKAGE

IRF

CPSI

13

TOP

14 --0

TOS

9403

15 --0 DES
16 --0 CPSD

17 --0

ORE

EO

11

18

19 20

21

22

BLOCK DIAGRAM

(7) Os - - - - - - - - - - - - - - - - - - ,
(7)PL

CD

cPSi----O

INPUT
CONTROL

®IE"S--o

@m--o

STACK

CONTROL

14 X 4 STACK

it
@ors--Q

@

TOP

OUTPUT
CONTROL

@TOS---<)

@

CPSO---()

~w-------------------~~~----~\F~,~,~~J
NOTE:
VDD = Pin 24
Vss=Pin12

o

@@@@

The Flatpak version has the same
pinouts (Connection Diagram) as the

Dual In-line Package.

= Pin Numbers

7-182

23

FAIRCHILD • 9403
PIN NAMES
PIN
NAME

LOADING (Note a)
DESCRIPTION

HIGH

LOW

DO - 03
Os
PL

Parallel Data Inputs
Serial Data Input
Parallel Load Input

1.0 U.L.
1.0 U.L.
1.0 U.L.

0.23 U.L.
0.23 U.L.
0.23 U.L.

CPS1
IES
ns
OES
TOS

Serial Input Clock
Serial Input Enable
Transfer to Stack Input
Serial Output Enable Input
Transfer Out Serial Input

1.0
1.0
1.0
1.0
1.0

0.23
0.23
0.23
0.6
0.23

TOP

Transfer Out Parallel Input

1.0 U.L.

0.23 U.L.

MR
EO
CPSO

Master Reset
Output Enable
Serial Output Clock Input
Parallel Data Outputs
Serial Data Output
Input Register Full Output
Output Register Empty Output

1.0 U.L.
1.0 U.L.
1.0 U.L.
130 U.L.
10 U.L.
10 U.L.
10 U.L.

0.23 U.L.
0.2.'3 U.L.
0.23 U.L.
10 U.L.
10 U.L.
5 U.L.
5U.L.

00- 03
Os
IRF
ORE

U.L.
U.L.
U.L.
U.L.
U.L.

U.L.
U.L.
U.L.
U.L.
U.L.

COMMENTS

HIGH on PL enables DO - 03. Not edge triggered.
Ones catching.
Edge triggered. Activates on falling edge.
Enables serial and parallel input when LOW.
A LOW on this pin initiates fall through.
Enables serial and parallel output when LOW.
A LOW on this pin enables a word to be transferred
from the stack to the output register. (TOP must be
HIGH also for the transfer to occur). Not edge
triggered.
A HIGH on this pin enables a word to be transferred
from the stack to the output register. (TOS must be
LOW for the transfer to occur). Not edge triggered.
Active LOW.
Active LOW.
Edge triggered. Activates on falling edge.
(Note b)
(Note b)
LOW when input register is full (Note b).
HIGH when output register contains valid data.

NOTE: a 1 Unit Load IU L.J 40 /1A HIGH. 1 6 rnA Law.
b. Output fan-out wIth VOL '::::0 0.5 V

FUNCTIONAL DESCRIPTION - As shown in the block diagram the 9403 consists of three sections:

1. An Input Register with parallel and serial data inputs as well as control inputs and outputs for input handshaking
and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with self-contained control logic.
3. An Output Register with parallel and serial data outputs as well as control inputs and outputs for output handshaking
and expansion.
Since these three sections operate asynchronously and almost independently, they will be described separately below:

Input Register (Data Entry):
The Input Register can receive data in either bit·serial or in 4-bit parallel form. It stores this data until it is sent to the fallthrough stack and generates the necessary status and control signals.

Figure 1 is a conceptual logic diagram of the input section. As described later, this 5-bit register is initialized by setting the F3
flip·flop and resetting the other flip·flops. The O-output of the last flip.flop (FC) is brought out as the "Input Register Full"
output (IRF). After initialization this output is HIGH.

Parallel Entry - A HIGH on the PL input loads the DO - 03 inputs into the FO - F3 flip·flops and sets the FC flip-flop. This
forces the fRF output LOW indicating that the input register is full. During parallel entry, the CPSI input must be LOW.

7-183

•

FAIRCHILD • 9403
I

. - - 0 3 - - - - - - - - - I N P U O T 2D A T A - - - - O - , - - - - - - O ' O

PL--~~---------_4~----~~----+_r_----,

INITIALIZE --l---~-----,

°s---1---I

m===~~:J~--------_r------_r------~

CPSI

INPUT REG --> STACK --,=------t-+-----~~----~+_---___,
(PULSE DERIVED FROM TTsI

Fig. 1
CONCEPTUAL INPUT SECTION

Serial Entry - Oata on the DS input is serially entered into the F3, F2, F1, Fa, FC shift register on each HIGH-to-LOW transition of the CPSI clock input. provided IES is LOW. During serial entry PL input should be LOW.
After the fourth clock transition, the four data bits located in the four flip-flops FO - F3. The FC flip-flop is set, forcing the
iRF output LOW and internally inhibiting CPSI clock pulses from effecting the register. Figure 2 illustrates the final positions
in a 9403 resulting from a 64-bit serial bit train. BO is the first bit, B63 the last bit.
Transfer to the Stack -The outputs of Flip·Flops Fa - F3 feed the stack. A LOW level on the TTS input initiates a "fallthrough" action. If the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized.
Note that this initialization is postponed until PL is LOW again. Thus, automatic FIFO action is achieved by connecting the
I R F output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown in Figure 10) in the control section records the fact that data
has been transferred to the stack. This prevents multiple entry of the same word into the stack despite the fact the iRF and
TTS may still be LOW. The Request Initialization Flip-Flop is not cleared until PL goes LOW. Once in the stack, data falls
through the stack automatically, pausing only when it is necessary to wait for an empty next location. In the 9403, as in
most modern F I Fa designs, the MR input only initializes the stack control section and does not clear the data.

INPUT

R!9- I§.T.§£3. -----~------9403

Fig. 2
FINAL POSITIONS IN A 9403 RESULTING
FROM A 64-BIT SERIAL TRAIN

7-184

FAIRCHILD • 9403
Output Register (Data Extraction) - The Output Register receives 4-bit data words from the bottom stack location, stores it
and outputs data on a 3-state 4-bit parallel data bus or on a 3-state serial data bus. The output section generates and receives
the necessary status and control signals. Figure 3 is a conceptual logic diagram of the output section.

r--------QUTPUT FROMSIACK--------,

LOAD FROM STACK

cpso----r~~-----~~-----_+------~--~~-_t~

rnrs---~~~~_t---_1------_t------II-----II---t_l

MR=~_+--+_--_r--_+--~~

TOP

ro---qc>----+--~_i-----,~_t----~-~---_,

0...,3'--_ _ _ _ _ _0....
'_OUTPUT DATA--O!..._ _ _ _ _ _0-"-'0

1...1

I

Fig_ 3
CONCEPTUAL OUTPUT SECTION

Parallel Data Extraction - When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (OR'E)
output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the Output Register provided the "Transfer Out Parallel" (TOP) input is HIGH. As a result of the data transfer
ORE goes HIGH, indicating valid data on the data outputs (provided the 3-state buffer is enabled). TOP can now be used to
clock out the next word. When TOP goes LOW, ORE will go LOW indicating that the output data has been extracted, but the
data itself remains on the output bus until a HIGH level at TOP permits the transfer of the next word (if available into the
Output Register. During parallel data extraction CPSO should be LOW. TOS should be grounded for single slice operation
or connected to the appropriate ORE for expanded operation (see Expansion section).
TOP is not edge triggered. Therefore, if TOP goes HIGH before data is available from the stack, but data does become available before TOP goes LOW again, that data will be transferred into the Output Register. However, internal control circuitry
prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from
the stack, ORE remains LOW indicating that there is no valid data at the outputs.
Serial Data Extraction - When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (ORE) output is LOW_ After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred
into the Output Register provided TI)S is LOW and TOP is HIGH. As a result of the data transfer ORE goes HIGH indicating
valid data in the register. The 3-state Serial Data Output, aS, is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to-LOW transition of CPSO. To prevent false shifting, CPSO should be LOW
when the new word is being loaded into the Output Register. The fourth transition empties the shift register, forces ORE output LOW and disables the serial output, aS (refer to Figure 3). For serial operation the ORE output may be tied to the TOS
input, requesting a new word from the stack as soon as the previous one has been shifted out_

7-185

•

FAIRCHILD • 9403
EXPANSION Vertical Expansion - The 9403 may be vertically expanded to store more words without external parts. The interconnections
necessary to form a 46-word by 4-bit FIFO are shown in Figure 4. Using the same technique, any FIFO of (15n + 1) words
by four bits can be constructed, where n is the number of devices. Note that expansion does not sacrifice any of the 9403's
flexibility for serial/parallel input and output. For other expansion schemes, refer to the Macrologic/Bipolar Microprocessor Data Book.

PARALLEL DATA IN
I

,

,

PARALLEL
LOAD

MASTER
RESET

i

03 02 D1

SERIAL DATA IN

DO

PL Os 03 02 D,
-
s

Q

ORE REQUEST
f-Llf'-f-LOP

FX
(SEE FIGURE 21

Q

e

R

y

~

LOAD OUTPUT (DERIVED FROM TOP AND TOS
REGISTER

TOP

f5S
OES

(SEE FIGURE 1)

.--.

LATCH

.........

,

Fig. 10
CONCEPTUAL DIAGRAM, INTERLOCKING CIRCUITRY

7-190

0-

H>o-

FAIRCHILD • 9403
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise noted)

Input HIGH Voltage

VIL

Input LOW Voltage

VCD

Input Clamp Diode Voltage

VOH
VOL

MIN

MAX

0.7

XM

0.8

XC
-0.9

Output HIGH Voltage,
ORE,IRF
Output HIGH Voltage,

XM

2.4

3.4

XC

2.4

3.4

XM

2.4

3.4

2.4

-1.5

UNITS
V

Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage

V

VCC

V

VCC

= MIN,

10H

= -2.0 mA

V

Oo-03,OS

XC
XM

0.25

0.4

V

°0-03,OS

XC
XM

0.35

0.5

V

0.25

0.4

XC

0.35

0.5

Output LOW Voltage, ORE, TRF

IOZH

Output Off HIGH Current

IOZL

Output Off LOW Current 00-03, Os

IIH

Input HIGH Current

3.1

00-0 3, Os

100
1.0

Supply Current

IOH - -5.7 mA
IOL - 8.0 mA
10L

16 mA

= 4.0 mA
IOL = 8.0 mA

10L

VCC

= MIN

VCC

= MIN

VCC

= MIN

JiA

40

IlA

1.0

mA

= MAX, VOUT - 0.5 V, VE = 2.7 V
VCC = MAX, VIN = 5.5 V

mA

VCC

= MAX,

VIN

rnA

VCC

= MAX,

VOUT

rnA

VCC

= MAX, Inputs Open

-0.96

ICC

= -400 JiA

-100

Input LOW Current, OES
-30

10H

VCC - MAX, VOUT - 2.4 V, VE - 2.0 V

-0.36

Output Short Circuit Current
00-03,OS,ORE,OES

V

= MIN,IIN = -18 mA

JiA

Input LOW Current, all except OES

lOS

TEST CONDITIONS (Note 1)

V

Output LOW Voltage,

VOL

IlL

TYP

2.0

VIH

VOH

LIMITS

PARAMETER

SYMBOL

-130

XM

115

155

XC

115

170

VCC

2.0 V

VCC - MAX, VIN

= 0.4 V
= 0,

(Note 3)

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
for the applicable device type.
2. Typical limits are at V CC = 5.0 V, T A = 25 0 C.
3. Not more than one output should be shorted at a time.

AC CHARACTERISTICS: VCC = 5.0 V, CL = 15 pF, TA = 25°C
SYM80L

LIMITS

PARAMETER

MIN

TYP

MAX

UNITS

tpHL

Propagation Delay, Negative·Going
CP to IRF Output

18

25

ns

tpLH

Propagation Delay, Negative·Going
TTS to IRF

48

64

ns

Propagation Delay, Negative·Going

30

40

ns

CPSO to Os Output

17

23

ns

tpLH,
tpHL

COMMENTS

Stack not Full, PL LOW,
Figures 11 and 12

OES LOW, TOP HIGH,
Figures 13 and 14

40

56

ns

31

45

ns

Propagation Delay, Negative·Going
CPSO to ORE

32

42

ns

OES LOW, TOP HIGH,
Figures 13 and 14

tpHL

Propagation Delay, Negative·Going
TOP to ORE

40

54
ns

Parallel Output,
Figure 15

tpLH

Propagation Delay, Positive·Going
TOP to ORE

51

68

tDFT

Fall Through Time

450

600

ns

ITS Connected to IRF
TOS Connected to ORE
IES, OES, EO, CPSO LOW,
TOP HIGH, Figure 16

tpLH

Propagation Delay, Negative·Going
TOS to Positive·Going ORE

41

53

ns

Data in stack, TOP HIGH,
Figures 13 and 14

tPLH,

Propagation Delay, Positive·Going

tpHL

TOP to Outputs

tpHL

00 -

03

7-191

EO, CPSO LOW,
Figure 15

m, CPSO LOW,

•

FAIRCHILD • 9403
AC CHARACTERISTICS (Cont'd): VCC
SYMBOL

= 5.0 V,

CL

=

15 pF, TA

= 25°C
LIMITS

PARAMETER

MIN

TYP

MAX

UNITS

COMMENTS
Stack not Full,
Figures 17 and 18

tpHL

Propagation Delay, Positive-Going
PL to Negative-Going IRF

33

44

ns

tpLH

Propagation Delay, Negative-Going
PL to Positive-Going IRF

20

28

ns

tpLH

Propagation Delay, Positive-Going
OESto~

26

38

ns

tpLH

Propagation Delay, Positive-Going
IES to Positive-Going IRF

31

40

ns

Figure 18

tpZL,
tpZH

Propagation Delay,
OE to 00,01,02,03

9.0

14

ns

Propagation Delay Out of
the High Impedance State

tpHZ,
tpLZ

Propagation Delay,
OE to 00,01,02,03

7.0

14

ns

Propagation Delay Into
the High Impedance State

tpZL,
tpZH

Propagation Delay, Negative-Going
OES to Os

13

18

ns

Propagation Delay Out of
the High Impedance State

tpLZ,
tpHZ

Propagation Delay, Negative-Going
OES to Os

7.0

14

ns

Propagation Delay Into the
High Impedance State

tAP

Parallel Appearance Time,
ORE to 00 - 03

-12

-5.0

ns

Time elapsed between ORE
going HIGH and valid data

6.0

10

ns

appearing at output. Negativ,e

Serial Appearance Time,
tAS

ORE to

Os

AC SET-UP REQUIREMENTS: VCC
SYMBOL

= 5.0

V, CL

=

15 pF, TA

= 25°C
LIMITS

PARAMETER

number indicates data available
before ORE goes HIGH.

MIN

TYP

MAX

UNITS

COMMENTS

tpWH

CPSI Pulse Width (HIGH)

25

19

ns

Stack not full, PL LOW,

tpWL

CPSI Pulse Width (LOW)

20

11

ns

Figures 11 and 12

tpWH

PL Pulse Width (HIGH)

40

29

ns

Stack not full, Figures 17 and 18

tpWL

TIS Pulse Width (LOW) Serial or
Parallel Mode

20

9.0

ns

Stack not full,
Figures 11, 12. 17, 18

tpWL

MR Pulse Width (LOW)

25

13

ns

Figure 16

tpWH

TOP Pulse Width (High)

20

13

ns

CPSO LOW, data available in stack,

tpWL

TOP Pulse Width (LOW)

30

17

ns

Figure 15

tpWH

CPSO Pulse Width (HIGH)

32

18

ns

TOP HIGH, data in stack,

tpWL

~ Pulse Width (LOW)

30

16

ns

Figures 13 and 14

ts

Set-up Time, DS to Negative CPSI

28

17

ns

PL LOW, Figures 11 and 12

th

Hold Time, DS to CPSI

0

-6.0

ns

PL LOW, Figures 11 and 12

ts

Set-up Time, TIS to IRF Serial
or Parallel Mode

0

-20

ns

Figures 11, 12, 17, 18

ts

Set-up Time Negative-Going ORE
to Negative-Going TOS

0

-24

ns

TOP HIGH,
Figures 13 and 14

tree

Recovery Time MR to any Input

10

5.0

ns

Figure 16

ts

Set-up Time, Negative-Going IES to CPSI

32

23

ns

Figure 12

ts

Set-up Time, Negative-Going TIS to

76

58

ns

Figure 12

ts

Set-up Time, Parallel Inputs to PL

0

-22

ns

Length of time parallel inputs must be
applied prior to rising edge of PL.

th

Hold Time, Parallel Inputs to PL

0

ns

Length of time parallel inputs must
reamin applied after falling edge of PL.

CPS!

7-192

FAIRCHILD • 9403

1_
\--fuv

IpHL

~----------------------------------------------------~

',~ O--t::=='PLH--j

TTS----------------------------------------------------~~r;-3-V------------~'PWL::::j
Fig. 11
SERIAL INPUT, UN EXPANDED OR MASTER OPERATION
Conditions: stack not full, IES, PL LOW

TES _ _ _ _"\

~----------------------------------------------------~

Fig. 12
SERIAL INPUT, EXPANDED SLAVE OPERATION
Conditions: stack not full, IES HIGH when initiated, PL LOW

•
ORE ______________________________________________~___ ,

tpH L " -__________-J

ts"'O~

TOS----------------------__________________________

l............-t

PL H

~~r-----------------

1"-'PWL:.j
Fig. 13
SERIAL OUTPUT, UNEXPANDED OR MASTER OPERATION
Conditions: data in stack, TOP HIGH, IES LOW when initiated, OES LOW

7-193

FAIRCHILD • 9403

O'S _ _- ' -_ _....

CPSO _ _ _J

OR' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ;

TOS _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

Fig. 14
SERIAL OUTPUT, SLAVE OPERATION
Conditions: data in stack, TOP HIGH, IES HIGH when initiated

TOP _ _ _ _""""

OR' _ _ _ _ _ _-...
'3 V
tPLH---.J

_ _ _ _ _ _ _ _ _ _ _ _'~PH~L~Ir_----

'.3_V_-_-_--I*

00 - 03 _ _ _ _ _ _ _ _ _ _ _ _

N'W OUTPUT

Fig. 15
PARALLEL OUTPUT, 4-BIT WORD OR MASTER IN PARALLEL EXPANSION
Conditions: IES LOW when initiated, EO, CPSO LOW; data available in stack

MR

r- -----1
\-,,.---1.3V---tpw

=:j ,,,, f-=
PL _ _ _ _ _ _ _

-J~r~~~~==~~~'_.3_V______

1-:-,pw---l'DFT

00-03 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

.1
~3V

Fig. 16
FALL THROUGH TIME
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, EO, CPSO LOW, TOP HIGH

7-194

FAIRCHILD. 9403

I'"

Pl _ _

~i

tpw

l

--'f----------\----------~

"'I"'--I--_th---,>-.j

f.-.
1.3 V

t,"O~"

TTS (NOTE

tplH

~I

I

(NOTE 3)

2)----------------~----- fr"'-.3-V--------

~tPw:-::::j

Fig. 17
PARALLEL LOAD MODE, 4-BIT WORD (UNEXPANDED) OR MASTER IN PARALLEL EXPANSION
Conditions: stack not full, I ES LOW when initialized

t-----tpw-----I

Pl _ _ _ _ _ _ _...J

IRF-------~~---

=1

__

tplH

3V

Fig. 18
PARALLEL LOAD, SLAVE MODE
Conditions: stack not full, device initialized (Note 1) with

NOTES:
1.

Initialization requires a master reset to occur after power has been applied.

2. TTS normally connected to TRF.
3. If stack is full. IRF will stay LOW.

7-195

IES

HIGH

•

9406
PROGRAM STACK
FAIRCHILD TTL MACROLOGIC

DESCRIPTION - The 9406 is a 16·word by 4·bit "push·down pop·up" Program Stack.
It is designed to implement Program Counter (PC) and return address storage for nested
subroutines in programmable digital systems. The 9406 executes 4 instructions: Return,
Branch, Call and Fetch as specified by a 2·bit instruction. When the device is initialized,
PC is in the top location of the stack. As a new PC value is "pushed" into the stack (Call
operation), all previous PC values effectively move down one level. The top location of
the stack is the current PC. Up to 16 new Program Counter values can be stored, which
gives the 9406 a 15 level nesting capability. "Popping" the stack (Return operation)
brings the most recent PC to the top of the stack. The remaining two instructions affect
only the top location of the stack. In the Branch operation a new PC value is loaded into
the top location of the stack from the 50 - 53 Inputs. In the Fetch operation, the con·
tents of the top stack location (current PC value) are put on the Xo - X3 bus and the
current PC value is incremented.
The 9406 may be expanded to any word length without additional logic. 3·state output
drivers are provided on the 4·bit address outputs (Xo - X3) and data outputs (DO 03); the X·Bus outputs are enabled internally during the Fetch instruction while the O·
Bus outputs are controlled by an Output Enable (EOO). Two status outputs, Stack Full
(SF) and Stack Empty (SE) are provided. The 9406 is fully compatible with all TTL
families.
•
•
•
•
•
•
•
•

16-WORD BY 4-BIT LIFO
1S-LEVEL NESTING CAPABILITY
10 MHz MICROINSTRUCTION RATE
PROGRAM COUNTER LOADS FROM DATA BUS
OPTIONAL AUTOMATIC INCREMENT OF PROGRAM COUNTER
STACK LIMIT STATUS INDICATORS
SLIM 24-PIN PACKAGE
3-STATE OUTPUTS

LOGIC SYMBOL

2

7

3

21 19 17 15

CO

CP
9406

SE

6

20 18

16 14

8

9

10

11

VCC = Pin 24
GND=PinI2

CONNECTION DIAGRAM
DIP (TOP VIEW)

24
23

PIN NAMES
50-53
10,11
EX
CP
MR

Ci
EO O
°0-°3
XO-X3
CO
SF
SE

Data Inputs (Active LOW)
Instruction Inputs
Execute Input (Active LOW)
Clock Input
Master Reset Input (Active LOW)
Carry Input (Active LOW)
Output Enable Input (Active LOW)
Output Data Outputs (Active LOW)
(Note b)
Address Outputs (Note b)
Carry Output (Active LOW) (Note b)
Stack Full Output (Active LOW)
(Note b)
Stack Empty Output (Active LOW)
(Note b)

LOADING (Note a)
HIGH
LOW
0.23 U.L.
1.0U.L.
0.23 U.L.
1.0 U. L.
1.0 U.L.
0.23 U.L.
1.0 U.L.
0.23 U.L.
1.0 U.L.
0.23 U.L.
1.0 U.L.
0.23 U.L.
0.23 U.L.
1.0 U.L.
10 U.L.
130 U.L.
130 U.L.
10 U.L.
10 U.L.

10 U.L.
5 U.L.
5 U.L.

10 U.L.

5 U.L.

22
21
20
19

18
11

16
10

15

11

14

12

13

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

NOTES:
a. 1 unit load (U.L.) = 40 "A HIGH, 1.6 rnA LOW.
b. Output fan-out with VOL'; 0.5 V.
7-196

13

SF

1.0 EX

4

FAIRCHILD • 9406
BLOCK DIAGRAM

@@@@
03 52 0 1 DO

r-;:::;-

'3

~

I
II I

'2

"

DECODE~O I RETURN

CD 10

- . : . . . . - AO

X3 X 2

(POP)

01

~

BRANCH {LOAD PCl

1-_ _H:..;FE:.;.T;::CH:..;I.:;.'N"C:;:RE::.:M:.:;ENc:.;T..:.P.:;CI'--.._ _ _ _ _I-_______-'-FE:o:T.::.CH"-~'-SIOD IOC

r

CP

o EX

II

J

'---C;:;'P-T-ICP

~ I~

MR

~I ~

03 0, 0, DO

IM~

,3"(,

°10

Zc

Xo

110 11C 11S 11A

ZB

ZA

.-I_-.--+-_.-+_~

I

i~ ~1~~w9,
Q, 9, C2
f--L.-/

5

1-01 j -

Cl

STACK POINTER

Zo

1 ____
..

CALL

lOB IDA

INPUT MULTIPLEXER

MR

QDorn=IrI1'f!'~~~~~~~~~~~~~fl::::;;~'!~::'i=r-'=-~r:::~E
o

Xl

02~HI

@ll-A1

'0

INCREMENTER

liON

H++-t++---------+---+---I AO

16 X 4 RAM

A,
A,
A3

~

""'~

~E

CP

°3

03

0,

0,

°0

°2

0,

00

4BITLATCH
03

°2

0,

°0

I

-r-:::::
@Of----------1H-+-Ir--+-+++-----+

~

= Pin 24
GND = Pin 12
o = Pin Numbers
VCC

SE

@)

QD
SF

--Y ~7 ~7
I

co

02

0,

00

@

@

@

@

TABLE 1
INSTRUCTION SET FOR THE 9406
11 10

INSTRUCTION

INTERNAL OPERATION

X-BUS

O-BUS (WITH EOO LOW)
Depending on the relative timing of EX and

L

L

Decrement Stack Pointer

Return (Pop)

Disabled

CP, the outputs will reflect the current program counter or the new value while CP is
LOW. When CP goes HIGH again, the

output will reflect the new value.

L

H

Branch (Load PC)

Load D-Bus into Current

Program Counter Location

Current Program Counter until CP goes
Disabled

Increment Stack Pointer and
H

L

Call (Push)

Load D-Bus into New Program

HIGH again, then updated with newly

entered PC value.

Disabled

Depending on the relative timing of EX and
CP, the outputs will reflect the current program counter or the previous contents of
the incremented SP location. When CP goes
HIGH again, the outputs will reflect the

Counter Location

newly entered PC value.
See Figure 9 for detaiis.

H

H

H

Increment Current Program

Fetch
(Increment PC)

HIGH Level

Counter if

L

CT is LOW

Current Program Counter

Current Program Counter until CP goes

while both CP and EX are LOW,
disabled while CP or EX is HIGH

incremented PC value.

LOW Level

7-197

HIGH again, then updated with

•

FAIRCHILD. 9406
FUNCTIONAL DESCRIPTION - As shown in the block diagram, the 9406 consists of an Input Multiplexer, a 16 X 4 RAM
with output latches addressed by the Stack Pointer (SP), an incrementor, control logic, and output buffers. The 9406 is
organized around three 4-bit busses; the input data bus (DO - D3),output data bus (00 - (3) and the address bus (XO -X3).
The 9406 implements four instructions as determined by Inputs 10 and 11 (see Table 1). The a-Bus is derived from the RAM
output latches and enabled by a LOW on the Output Enable (EO O) input. The X-Bus is also derived from the output latches;
it is enabled internally during the Fetch instruction. Execution of instructions is controlled by the Execute (EX) and Clock
(CP) inputs.
Fetch Operation - The Fetch operation places the content of the current Program Counter (PC) on the X-Bus. If the Carry In
(CI) is LOW, the current PC is incremented in preparation for the next Fetch. If CI is HIGH, the value of the current PC is
unchanged, (Iterative Fetch).
The instruction code is set up on the I lines when CP is HIGH. The Execute (EX) is normally LOW at this time. The control
logic interprets 10 and 11 and selects the incrementor output as the data source to the RAM via the Input Multiplexer. The
current PC value is loaded into the latches and is available on the a-Bus if EO O is LOW. When CP is LOW the latches are
disabled from following the RAM output, when both CP and EX are LOW, buffers are enabled, applying the current PC to
the X-Bus. The output of the incrementor is written into the RAM during the period when CP and EX are LOW. If CI is
LOW, the value stored in the current PC, plus one, is written into the RAM. If CI is HIGH, the current PC is not incremented.
Carry Out (CO) is LOW when the content of the current PC is at its maximum, i.e., all ones and the Carry In (CI) is LOW.
When CP or EX goes HIGH, writing into the RAM is inhibited and the address buffers (XO - X3) are disabled.
Branch Operation - During a Branch operation, the data inputs (DO - D3) are loaded into the current program counter.
The instruction code and the EX Input are set up when CP is HIGH. The Stack Pointer remains unchanged. When CP goes
LOW (assuming EX is LOW) the D-Bus Inputs are written into the current PC. The X-Bus drivers are not enabled during a
Branch operation.
Call Operation - During a Call operation the content of the data bus is loaded into the top location of the stack and all previous PC values are effectively moved down one level.
The instruction code and the EX input are set up when CP is HIGH. When EX is LOW, a "one" is added to the Stack Pointer
value thus incrementing the RAM address. Since the output latches go to the nontransparent or store mode when CP is LOW,
the a-Bus outputs will reflect the RAM output at the CP negative-going transition. If EX goes LOW considerably before CP
goes LOW, the a-Bus will correspond to the previous contents of the incremented RAM address after CP goes LOW. If CP
goes LOW a very short time after EX, the a-Bus will remain unchanged until the LOW to HIGH transition of CPo
When CP is LOW (assuming EX is LOW) the D-Bus inputs are written into this new RAM location. On the LOW-to-HIGH
transition of CP, the incremented Stack Pointer value is loaded into the Stack Pointer and the a-Bus outputs reflect the
newly entered data. When the RAM address is "1111" the Stack Full output (SF) is LOW, indicating that no further Call
operations should be initiated. If an additional Call operation is performed SP is incremented to (0000), the contents of that
location will be written over, SF will go HIGH and the Stack Empty (SE) will go LOW.
The X-Bus drivers are not enabled during a Call operation.
Return Operation - During the Return operation the previous PC is "popped" to become the current PC.
The instruction is set up when CP is HIGH. When EX is LOW, a "one" is subtracted from the Stack Pointer value, thus
decrementing the RAM address. If EX goes LOW considerably before CP goes LOW, the a-Bus will correspond to the new
value after J;:X goes LOW. If CP goes LOW a short time after EX, the a-Bus will remain unchanged until the LOW-to-HIGH
transition of CPo
On the LOW-to-H IGH transition of CP the decremented Stack Pointer value is loaded into the Stack Pointer and the a-Bus
outputs correspond to the new "popped" value.
The X-Bus drivers are not enabled during a Return operation. When the RAM address is "0000", the Stack Empty output
(SE) is LOW, indicating that no further return operations should be initiated. If an additional Return operation is performed,
SP is decremented to "1111 ", the SE will go HIGH and the Stack Full output (SF) will go LOW. A LOW on the Master Reset
(M R) causes the SP to be reset and the contents of that RAM location (0000) to be cleared. The Stack Empty (SE) output
goes LOW. This operation overrides all other inputs.
EXPANSION - The 9406 may be expanded to any word length in mUltiples of four without external logic. The connection
for expanded operation is shown in Figure 1. Carry In (GI) and Carry Out (CO) are connected to provide automatic increment of the current program counter during Fetch. The GI input of the least significant 9406 is tied LOW to ground.
If automatic increment during Fetch is not desired, the

GI input of the

7-198

least significant 9406 is held HIGH.

FAIRCHILD • 9406

DATA
.~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_
A INPUT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~,

*Tie to

Vee to disable automatic increment.
Fig. 1
16 BY 12 PROGRAM STACK

DC CHARACTERISTICS OVER OPERATION TEMPERATURE RANGE (un)ess otherwise noted)
SYMBOL
VIH

Input HIGH Voltage

Vil

Input lOW Voltage

VCD
VOH
VOH
VOL
VOL

LIMITS

PARAMETER

MIN

TYP

MAX

2.0
XM

0.7

XC

0.8

Input Clamp Diode Voltage

-0.9

Output HIGH Voltage

XM

2.4

3.4

CO, SE, SF

XC

2.4

3.4

Output HIGH Voltage

XM

2.4

3.4

Xo - X3, 00 - 03
Output lOW Voltage

XC

2.4

3.1

-1.5

0.25

0.4

0.35

0.5

Output lOW Voltage

0.25

0.4

Xo - X3, 00 - 03

0.35

10ZH

Output Off HIGH Current

IDZl

Output Off lOW Current

IIH

Input HIGH Current

III

Input lOW Current

lOS

Output Short Circuit Current

ICCH

Supply Current

-30
100

Guaranteed Input HIGH Voltage
Guaranteed Input lOW Voltage

V

VCC

= MIN.

V

VCC

= MIN, 10H = -400 JjA

V

liN - -18 mA

10H - -2.0 mA
10H

= -5.7

mA

I
I

VCC

= MIN

VCC - MIN, 10l

= 4.0 mA

VCC - MIN, 10l

8.0mA

JjA

= MIN, IOl - 8.0 mA
VCC = MIN, IOl - 16 mA
VCC = MAX, VOUT = 2.4 V, VE = 2 V

100

JjA

VCC - MAX, VOUT

40

JjA

- 2.7 V

= 0.4 V
=0 V

0.5
100

1.0

V
V

V

-CO, SE, SF

TEST CONDITIONS (Note 1)

UNITS

V

VCC

1.0

mA

= MAX, VIN
VCC = MAX, VIN

-0.36

mA

VCC - MAX, VIN

100

mA

VCC - MAX, VOUT

160

mA

VCC

VCC

0.5 V, VE - 2V

- 5.5 V
(Note 3)

= MAX

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
2. Typical limits are at VCC = 5.0 V, TA = 25"C.
3. Not more than one output should be shorted at a time.

7-199

•

FAIRCHILD • 9406
AC SET-UP REQUIREMENTS - ALL MODES OF OPERATION: Vee = 5.0 V, TA = 25°e, eL = 15 pF
SYMBOL

PARAMETERS

LIMITS
MIN

TYP

MAX

UNITS

tcw

Clock Period

100

70

ns

tpWH

Clock Pulse Width (HIGH)

60

40

ns

tPWL

Clock Pulse Width (LOW)

40

25

ns

tsEX

Set-Up Time, EX to CP

0

ns

thEX

Hold Time, EX to CP

0

ns

tsl

Set-Up Time, 10, 11 to Negative-Going Clock

20

ns

thl

Hold Time, 10, 11 to Positive-Going Clock

0

ns

tsCI

Set-Up Time, CI to Negative-Going Clock

5

ns

th CI

Hold Time, CI to Positive-Going Clock

0

ns

tsO

Set-Up Time, 00-03 to Positive-Going Clock

20

ns

thO

Hold Time, 00 - 03 to Positive-Going Clock

0

ns

tPWLMR

MR Pulse Width (LOW)

40

25

ns

tree

MR to Negative-Going Clock

45

30

ns

COMMENTS

Figure 2

Figure 3

I-'PWL_I
MR\3V
luv

,

I~,_'L

Fig. 3
RESET OPERATION

Fig. 2
WAVEFORMS FOR ALL OPERATIONS

Refer to individual timing diagrams for each operation to determine output response.

7-200

FAIRCHILD. 9406
AC CHARACTERISTICS - FETCH OPERATION: VCC = 5.0 V, TA = 25 0 C, CL = 15 pF
SYMBOL

LIMITS

PARAMETERS

tPLH

Propagation Delay, Carry In (Gi) to

tPHL

Carry Out (CO)

MIN

TYP

MAX

11

16

7

12

tPLH

Propagation Delay. Positive·Going CP

28

41

tpHL

to Carry Out (CO)

46

66

tPLH

Propagation Delay. Negative·Going EX

34

45

tPHL

to Carry Out (CO)

38

60

a ______

_________________

~><~,v

UNITS

COMMENTS

ns

Figure 4

ns

Figure 5

ns

Figure 6

C'_lil

UV

I_'PLH_I

-"HL-I

tpHL

ro ______________________

'PCH

-J)*(~.,_v___________

--'><. .

Co _ _ _ _ _ _ _ _ _ _

'_v_ _ __

Fig. 5
CLOCK TO CARRY·OUT

Fig. 4
CARRY·IN TO CARRY·OUT

EX

V
_
\1....-....1.3

I-::~:-I

_

-JX. .

CO_ _ _ _ _ _ _ _ _

'_v_ _ __

Fig. 6
EXECUTE TO CARRY·OUT

•

AC CHARACTERISTICS AND SET·UP REQUIREMENTS - BRANCH (LOAD PC) OPERATION:
VCC= 5.0 V, TA = 25°C, CL = 15 pF
PARAMETERS

SYMBOL

LIMITS
MIN

TYP

MAX

tPLH

Propagation Delay t Positive~Going CP

28

41

tPHL

to Outputs (00 - (3)

45

66

ts

Set· Up Time. 10. 11 to Negative·Going EX

th

Hold Time 10, 11 to Positive·Going EX

th

Hold Time. 10, 11 to Positive·Going CP

ts

Set·Up Time, DO - D3 to Positive·Going CP

th

Hold Time, DO - D3 to Positive·Going CP

tpWL

EX Pulse Width

UNITS

ns

COMMENTS
EOO LOW
Figures 7 and 8

20

ns

0

0

ns

EX goes HIGH before CP, Figure 8

0

0

ns

CP goes HIGH before EX. Figure 7

25

16

ns

0

0

n!

45

30

ns

30

Figures 7 and 8

7-201

EX Goes HIGH Before CP, Figure 8

FAIRCHILD • 9406
CONDITIONS: EO O LOW

CONDITIONS, EOe LOW

'0

EX

CP

'._3~

00-03 _____________
C_UR_R_E_NT_V_A_L_UE___________

Fig. 8
BRANCH OPERATION, EX GOES HIGH BEFORE CP

Fig.7
BRANCH OPERATION, CP GOES HIGH BEFORE EX

AC CHARACTERISTICS AND SET-UP REOUIREMENTS - CALL (PUSH) OPERATION:
VCC ~ 5.0 V, T A ~ 25°C, CL ~ 15 pF (Figure 9)
SYMBOL

LIMITS

PARAMETERS
Positive~Going

tPLH

Propagation Delay.

tpHL

New Value of 00 - 03

MIN

CP to

TYP

MAX

25

40

75

130

tpLH

Propagation Delay, Negative-Going EX

22

35

tPHL

to Intermediate Value of 00 - 03

64

85

tPLH

Propagation Delay, Negative·Going EX

18

28

tpHL

to SE, SF

43

59

ts

Set-Up Time, Negative-Going EX to 10, 11

th

Hold Time, Positive-Going CP to 10, 11

-

-

UNITS

ns

ns

20

ns
ns

0

Set-Up Time, EX to Negative-Going CP which
ts1 EX

Guarantees Intermediate Data on 00 - 03 while

65

45

ns

CP is LOW
Set-Up Time, EX to Negative-Going CP which
ts2EX

Guarantees no Change in 00 - 03 While CP

0

ns

0

ns

is LOW

Hold Time, Positive·Going CP to
thEX

Positive·Going EX

ts

Set-Up Time, DO - D3 to Positive-Going CP

th

Hold Time, Positive-Going CP to DO - D3

30

20

0

7-202

EOO LOW
EOO LOW, Set·Up Requirements ts1 EX

must be met
ns

30

COMMENTS

ns
ns

FAIRCHILD • 9406
CONDITIONS

roo LOW

'0-----"""

,,---------,.

!-::~~---I ,----PREVIOUS CONTENTS OF
INCREMENTED SP LOCATION

00-63

(NOTE 1'_ _ _ _ _ _ _ _ _-;-_ _J

I

+ ____C_U"_"_"_'_V._'_U,_ _ _ _ _' -,,,:-r,-.-v.-,u-,--~A.~

00 -°3~I _________

(NOTE

1-4-IPLH--.-.[
IpHL

"..JX

r ----------------

SE.SF _ _ _ _ _ _ _ _ _ _ _ _

Fig. 9
CALL (PUSH) OPERATION
NOTES:
1. Condition which occurs when EX goes LOW considerably before CP goes LOWJ.!sl EX is metl.
2. Condition which occurs when EX goes LOW slightly before CP goes LOW (ts2EX is metl.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS - RETURN (POP) OPERATION:
Vce = 5.0 V, TA = 25 e, CL = 15 pF (Figure 10)
Q

SYMBOL

PARAMETERS

LIMITS
MIN

Propagation Delay, Positive-Going CP to
New Value of 00 - 03

TYP

MAX

25

40

103

130

23

40

101

130

Propagation Delay, Negative-Going EX

18

28

to §E, SF

43

59

Propagation Delay, Negative-Going EX
to New Value of

00 - 03

Set-Up Time, Negative-Going EX to 10, 11
Hold Time, Positive-Going CP to 10, 11

30

20

o

UNITS

ns

ns

65

ns
ns
ns

45

ns

While CP is LOW

Set-Up Time, EX to Negative-Going CP.
Either ts2EX or ts3EX must be met for

o

ns

Pr.oper Operation

Set-Up Time, EX to Positive-Going CPo
Either ts3EX or ts2EX (Above) must be met

45

30

for Proper Operation.

7-203

EOo LOW
EOo LOW, Set-Up Requirements tsl EX

must be met

Set-Up Time, EX to Negative-Going CP which
Guarantees the New Value on 00 - 03

COMMENTS

ns

•

FAIRCHILD • 9406
CONDITIONS:

rOo LOW

v

1.3

(NOTES 1 & 2)

1.3

cp

NEW VALUE

CURRENT VALUE

SE,SF

Fig. 10
RETURN (POP) OPERATION
NOTES:
1. Condition which occurs when EX goes LOW considerably before CP goes LOW (t 1 EX is met).
_
2. Condition which occurs when EX goes LOW slightly before or after CP goes LOW leither ts2EX or ts3EX are met).

AC CHARACTERISTICS AND SET-UP REQUIREMENTS - FETCH OPERATION:
VCC= 5.0 V, TA = 25°C, CL = 15pF
SYMBOL

PARAMETERS

LIMITS
MIN

TYP

MAX

tPLH

Propagation Delay Positive·Going CP

22

30

tPHL

to Incremented Value of 00 - 03

59

80

tpZL

Turn·On Delay, from CP or EX

13

18

tpZH

Whichever goes LOW last to Xo - X3

12

17

tpLZ

Delay Going into HIGH

7

12

tpHZ

Impedance State

10

16

ts

Set·Up Time, 10, 11 to Negative·Going EX

th

Hold Time, 10, 11 to CP or EX whichever
goes HIGH first
Set·Up Time, Negative Going EX

ts

ns

ns

30

20

COMMENTS

UNITS

EOO, CI LOW, Figures 13 and 14

-

EOX LOW, Figures 11,12,13 and 14

ns
ns
ns

0

Figures 11,12,13 and 14

40

25

ns

20

ns

to Positive·Going CP

ts

Negative.(3oing CI to Positive·Going CP

30

th

Positive·Going CI to Negative·Going EX

0

Fetch with Increment, Figures 13 and 14
Iterative Fetch, Figures 11 and 12

7-204

FAIRCHILD • 9406
CONDITIONS

Wo LOW, CP goes HIGH before EX
10. 11

CP

Fig. 11
ITERATIVE FETCH

CONDITIONS EOO LOW, EX '0", HIGH b'fo," C P I

r--+---------+----.:<~mmmm0:':

10- 11

•

CP

CURRENT VALUE

I-NoTE

2

~-~}(I...--

Fig. 12
ITERATIVE FETCH
NOTES:
1. Xo - X3 Turn·On Delay measured from the time both E~nd CP go LOW.
2, Xo - X3 Turn·Off Delay measured from the time either EX or CP goes HIGH,

7-205

FAIRCHILD • 9406
CONDITIONS EGO LOW, CP goes HIGH before

EX

EX

1.3

1.3 V

CP

Xo - X3

Fig. 13
FETCH WITH INCREMENT PC
CONDITIONS EGO LOW, EX goes HIGH before CP

10. 11

EX

CI

CP

CURRENT VALUE

NOTE 1

tpLZ
tpHZ

=J r-----------NOTE 2

r--------HIGH IMPEDANCE

1.3 V

CURRENT VALUE

1.3 V

Fig. 14
FETCH OPERATION WITH INCREMENT PC

NOTES:
1. Xo - X3 Turn·On Delay measured from the time both EX and CP go LOW.
2. Xo
X3 Turn·Off Delay measured from the time either EX or CP goes HIGH.

7-206

HIGH IMPEDANCE

9410
REGISTER STACK· 16x4 RAM
WITH 3-STATE OUTPUT REGISTER
FAIRCHILD TIL MACROLOGIC

DESCRIPTION - The 9410 is a register oriented high speed 64-bit Read/Write Memory
organized as 16-words by 4-bits. An edge triggered 4-bit output register allows new input
data to be written while previous data is held. 3-state outputs are provided for maximum
versatility. The 9410 is fully compatible with all TTL families.

LOGIC SYMBOL

17 15 13

•
•
•
•
•
•

EDGE-TRIGGERED OUTPUT REGISTER
TYPICAL ACCESS TIME OF 35 ns
3-STATE OUTPUTS
OPTIMIZED FOR REGISTER STACK OPERATION
TYPICAL POWER OF 375 mW
18-PIN PACKAGE

9410

LOADING (Note a)
HIGH
LOW
1.0 U.L. 0.23 U.L.
1.0 U. L. 0.23 U.L.
1.0 U.L. 0.23 U.L.
1.0 U.L. 0.23 U.L.
1.0 U.L. 0.23 U.L
1.0 U.L. 0.23 U.L.

PIN NAMES
Address Inputs
Data Injluts
Chip Select Input (Active LOW)
Output Enable Input (Active LOW)
Write Enable Input (Active LOW)
Clock Input (Outputs Change on LOW
to HIGH Transition)
Outputs

AO-A3
00- 0 3
CS
EO
WE
CP
00-03

11

130 U.L.

NOTES:
a) 1 Unit Load (U.L.l = 40",A HIGH, 1.6 mA LOW.
b) 10 LOW Unit Loads measured at 0.5 V.

10 U.L.
(Note b)

16

14

12

10

Vcc = Pin 18
GND = Pin 9

CONNECTION DIAGRAM
DIP (TOP VIEW)

,.

BLOCK DIAGRAM

17
16

15
14

(j)

13

Cp
16 X 4
MEMORY CELL
ARRAY

12
11

(0

cs--+--.

10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

VDD = Pin 18
VSS = Pin 9
= Pin Numbers

o

7-207

•

FAIRCHILD • 9410
FUNCTIONAL DESCRIPTION
Write Operation - When the three control inputs: Write Enable (WE), Chip Select (CS), and Clock (CP), are LOW the
information on the data inputs (DO - D3) is written into the memory location selected by the address inputs (AO - A3)'
If the input data changes while WE, CS, and CP are lOW, the contents of the selected memory location follows these
.
changes, provided set·up time criteria are met.
Read Operation - Whenever CS is LOW and CP goes from lOW-to-HIGH, the contents of the memory location selected by
the address inputs (AO-A3) is edge-triggered into the Output Register.
A 3-State Output Enable (EO) controls the output buffers. When EO is HIGH the four outputs (00 - 03) are in a high
impedance or OFF state; when EO is LOW, the outputs are determined by the state of the Output Register.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise noted)
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VCD

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

10ZH

Output Off HIGH Current

10ZL

Output Off LOW Current

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit Current

ICCH

Supply Current

MIN

TYP

MAX

2.0
XM

0.7

XC

O.B
-0.9

XM

2.4

3.4

XC

2.4

3.1

XM&

xc

XC

-1.5

UNITS

TEST CONDITIONS (Note 11

V

Guaranteed Input HIGH Voltage

V

Guaranteed Input LOW Voltage

V

VCC

= MIN,IIN -

10H - -2.0 mA
10H - -5.2 mA

I
1

-18 mA
VCC

= MIN

= MIN, 10L = 8.0 mA

0.25

0.4

V

VCC

0.35

0.5

V

VCC - MIN, 10L - 16 mA

1.0

-30
75

= MAX, VOUT -

100

p.A

VCC

-100

p.A

VCC - MAX, VOUT - 0.5 V, VE - 3 V

2.4 V, VE - 3 V

40

p.A

VCC - MAX, VIN - 2.7 V

1.0

mA

VCC - MAX, VIN - 5.5 V

-0.36

mA

VCC - MAX, VIN - 0.4 V

-100

mA

VCC -MAX, VOUT

110

mA

VCC - MAX, Inputs Open

o V (Note 31

NOTES:
1. For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
.
2. Typical limits are at VCC = 5.0 V, T A = 25°C.
3. Not more than one output should be shorted at a time.

7-208

FAIRCHILD • 9410
AC CHARACTERISTICS: T A = 25°C
SYMBOL

TEST CONDITIONS

PARAMETER

READ MODE
tpZH

9

15

ns

9

15

ns

Disable Time, Output Enable to Output

10
10

16
16

ns

Propagation Delay, Clock to Output

14
14

20

ns

20

ns

Enable Delay, Output Enable to Output

tpZL
tpHZ
tPLZ
tPLH
tpHL
tsAR

Set-up Time to Read from Address to Clock

thAR

Hold Time to Read from Address to Clock

38
0

25

21

12

ns

Figure 1

Figure 1
Figure 2

ns

Figure 2

ns

Figure 2

ns

Figure 3

WRITE MODE
Write Enable, Chip Select, or Clock Pulse Width
tw

Required to Write INote a)

tsAW

Set-up Time Address to Write Enable INote b)

5

ns

Figure 3

thAW

Hold Time Address to Write Enable INote b)

0

ns

tsDW

Set-up Time Data to Write Enable INote b)

ns

Figure 3
Figure 3

thDW

Hold Time Data to Write Enable

ns

Figure 3

9

16
0

NOTES:
a) Writing occurs when WE,

CE and CP are

LOW.

b) Assuming WE is utilized as Writing Strobe.

READ MODE AC PARAMETERS

EO

~..._1.3_V______..J-l13V
r---t=tPZH

0.,..03

HIGH "Z"

{

V,H

!-t--t

PHZ

V,H } - -

~~:~ZL

~t-tPLZ
Other Conditions:

Fig_ 1

CS = OE = LOW

Fig. 2

PROPAGATION DELAY CLOCK
TO DATA OUTPUTS, AND SET·UP
AND HOLD TIMES ADDRESS TO CLOCK TO READ

PROPAGATION DELAY
OUTPUT ENABLE TO DATA OUTPUTS

WRITE MODE AC PARAMETERS

Other Conditions:

CS =

CP = LOW

Fig. 3

WRITE ENABLE PULSE
WIDTH, SET-UP AND HOLD
TIMES ADDRESS AND DATA TO WRITE ENABLE
7-209

•

FAIRCHILD • 9410

FUNCTIONAL DESCRIPTION
Write Operation - When the three control inputs: Write Enable (WE), Chip Select (CS), and Clock (CP), are LOW the
information on the data inputs (DO - D3) is written into the memory location selected by the address inputs (AO - A3)·
If the input data changes while WE, CS, and CP are LOW, the contents of the selected memory location follows these
changes, provided set·up time criteria are met.
Read Operation - Whenever CS is LOW and CP goes from LOW·to·HIGH, the contents of the memory location selected by
the address inputs (AO-A3) is edge·triggered into the Output Register.
A 3·State Output Enable (EO) r:ontrols the output buffers. When EO is HIGH the four outputs (00 - 03) are in a high
impedance or OFF state; when EO is LOW, the outputs are determined by the state of the Output Register.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise noted)
SYMBOL
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VCD

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IOZH

Output Off HIGH Current

IOZL

Output Off LOW Current

IIH

LIMITS

PARAMETER

MIN

Input LOW Current

lOS

Output Short Circuit Current

ICCH

Supply Current

MAX

XM

0.7

XC

0.8
-0.9

XM

2.4

XC

2.4

-1.5

V

Guaranteed Input HIGH Voltage

V

Guaranteed Input LOW Voltage

V

= MIN, liN = -18 mA
= -2.0 mA T V = MIN
= -5.2 mA I CC
VCC = MIN, IOL = 8.0 mA
VCC = MIN, IOL = 16 mA
VCC - MAX, VOUT = 2.4 V, VE = 3 V
VCC = MAX, VOUT = 0.5 V, VE = 3 V
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 5.5 V
VCC = MAX, VIN = 0.4 V
VCC = MAX, VOUT = 0 V (Note 3)
VCC = MAX, Inputs Open

3.4
3.1
V

0.4

XC

0.35

0.5

V

100

IJ.A

-100

IJ.A

-30
75

VCC
IOH
IOH

0.25

1.0

TEST CONDITIONS (Note 11

UNITS

XM & XC

Input HIGH Current

IlL

TYP

2.0

40

IJ.A

1.0

mA

-0.36

mA

-100

mA

110

mA

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable

device type.
2. Typical limits are at VCC = 5.0 V, T A = 25°C.

3. Not more than one output should be shorted at a time.

7-210

9423
FIRST-IN FIRST-OUT (FIFO) BUFFER MEMORY
FAIRCHILD PL!M

DESCRIPTION - The 9423 is an expandable fail-through type high-speed First-In
First-Out (FIFO) Buffer Memory optimized for high speed disc or tape controllers and
communication buffer applications. It is organized as 64 words by four bits and may be
expanded to any number of words or any number of bits (in multiples of four). Data may
be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories.
The 9423 has 3-state outputs which provide added versatility and is fully compatible with
ali TTL families.

LOGIC SYMBOL

7

6

5

4

10 - - 0

9 - - 0 IES

IRF

8 - - 0 CPS I

•
•
•
•
•

SERIAL OR PARALLEL INPUT
SERIAL OR PARALLEL OUTPUT
EXPANDABLE WITHOUT EXTERNAL LOGIC
3-ST ATE OUTPUTS
FULLY COMPATIBLE WITH ALL TTL FAMILIES

•

SLIM 24-PIN PACKAGE

13

TOP

14 - - 0

TOS

9423

15 --0 OES
16 --0

CPSO

11 --0

EO

ORE

23

MR

11

18

19

20

21

2L

BLOCK DIAGRAM

o

DS~------------------------

___

INPUT
CONTROL

o

Vee

~

Pin 24

GND

~

Pin 12

CONNECTION DIAGRAM
DIP (TOP VIEW)
24
23

22

21
62

x4

STACK

20

19
18

17
16
OUTPUT

CONTROL

ID

15

11

14

12

13

w~-----------------qC>----~~7-~~7

@

NOTE:

@@@@
Vee ~ Pin 24
GND

~

The Flatpak version has the same

o

Pin 12

7-211

pinouts (Connection Diagram) as the
= Pin Numbers

Dual In-line Package.

•

FAIRCHILD • 9423
PIN NAMES
PIN
NAME

LOADING (Note a)

DESCRIPTION

HIGH

LOW

PL

Parallel Data Inputs
Serial Data Input
Parallel Load Input

1.0 U.L.
1.0 U.L.
1.0 U.L.

0.23 U.L.
0.23 U.L.
0.23 U.L.

CPSl
IES
ITS
OES
TOS

Serial Input Clock
Serial Input Enable
Transfer to Stack Input
Serial Output Enable Input
Transfer Out Serial Input

1.0
1.0
1.0
1.0
1.0

0.23
0.23
0.23
0.46
0.23

TOP

Transfer Out Parallel Input

1.0 U.L.

0.23 U.L.

MR

Master Reset
Output Enable
Serial Output Clock Input
Parallel Data Outputs
Serial Data Output
Input Register Full Output
Output Register Empty Output

2.0 U.L.
1.0 U.L.
1.0 U.L.
130 U.L.
10 U.L.
10 U.L.
10 U.L.

0.46 U.L.
0.23 UL
0.23 U.L.
10 U.L.
10 U.L.
5 U.L.
5 U.L.

00- 03

Os

EO
CPSO

00- 03
Os
IRF
ORE

U.L.
U.L.
U.L.
U.L.
U.L.

U.L.
U.L.
U.L.
U.L.
UL

COMMENTS

HIGH on PL enables DO - 03' Not edge triggered.
Ones catching.
Edge triggered. Activates on falling edge.
Enables serial and parallel input when LOW.
A LOW on this pin initiates fall through.
Enables serial and parallel output when LOW.
A LOW on this pin enables a word to be transferred
from the stack to the output register. (TOP must be
HIGH also for the transfer to occur). Not edge
triggered.
A HIGH on this pin enables a word to be transferred
from the stack to the output register. (TOS must be
LOW for the transfer to occur). Not edge triggered.
Active LOW.
Active LOW.
Edge triggered. Activates on falling edge.
(Note b)
(Note b)
LOW when input register is full (Note b).
HIGH when output register contains valid data.

NOTE: a. 1 Unit Load (U.L) ~ 40/1A HIGH. 1.6 mA l.OW.
b. Output fan~out with VOL:=;;; 0.5 V.

ABSOLUTE MAXIMUM RATINGS (above whieh the useful life may be impaired.)
Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
*Input Voltage (de)
*1 nput Current (de)
**Voltage Applied' to Outputs (Output HIGH)
Output Current (de) (Output LOW)

-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-0.5 V to +5.5 V
-12 mA to +5.0 mA
-0.5 V to +5.5 V
+20mA

*Either input voltage or· input current limit is sufficient to protect the input.
**Output Current Limit Required.

GUARANTEED OPERATING RANGES
SUPPLY VOLTAGE (Vee)

AMBIENT TEMPERATURE (TA)

PART NUMBER
MIN

TYP

MAX

(Note 4)

9423Xe

4.75 V

5.0 V

5.25 V

oOe to +75°e

9423XM

4.50 V

5.0V

5.50 V

-55°e to +125°e

x = package type;

F for Flatpak,D for Ceramic DIP,P for Plastic DIP.See Packaging Information Section for packages available on this product.

FUNCTIONAL DESCRIPTION - As shown in the block diagram the 9423 consists of three sections:
1. An Input Register with parallel and serial data inputs as well as contral inputs and outputs for input handshaking
and expansion.
2. A 4-bit wide, 62 -word deep fall-through stack with self-contained control logic.
3. An Output Register with parallel and serial data outputs as well as control inputs and outputs for output handshaking
and expansion.
Since these three sections operate asynchronously and almost independently, they will be described separately below:

7-212

FAIRCHILD •

9423

...----------IN.UT DATA-----------,
O2

01

00

I

.L--r~--------+-~---_r~----r1-----_,

INITIALIZE _~---.---..,

~:====~==t::>-1r_-----1_----_i-----1_J

CPSI

INPUTREG-STACK--:=-----~+-----,..._lr_---~+---_,
(PULSE DERIVED FROM TIs)

Fig. 1
CONCEPTUAL INPUT SECTION

Input Register (Data Entry):
The Input Register can receive data in either bit·serial or in 4-bit parallel form. It stores this data until it is sent to the fallthrough stack and generates the necessary status and control signals.
Figure 1 is a conceptual logic diagram of the input section. As described later, this 5·bit register is initialized by setting the F3
flip-flop and resetting the other flip·flops. The Q·output of the last flip·flop (FC) is brought out as the "Input Register Full"
output (lRF). After initialization this output is HIGH.
Parallel Entry - A HIGH on the PL input loads the DO - D3 inputs into the Fa - F3 flip·flops and sets the FC flip·flop. This
forces the iRF output LOW indicating that the input register is full. During parallel entry, the CPSI input must be LOW.
Serial Entry :..Q!ta on the DS input is serially entered into the F.3, F2, F 1, Fa, FC shift register on each H IGH-to-LOW transition of the CPSI clock input, provided IES is LOW. During serial entry PL input should be LOW.
After the fourth clock transition, the four data bits are located in the four flip-flops Fa - F3' The FC flip-flop is set, forcing
the I RF output LOW and internally inhibiting CPSI clock pulsed from effecting the register. Figure 2 illustrates the final positions in a 9423 resulting from a 256-bit serial bit train. 80 is the first bit, 8 25 5 the last bit.
Transfer to the Stack - The outputs of Flip-Flops Fa - F3 feed the stack. A LOW level on the TTS input initiates a "fallthrough" action. If the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized.
Note that this initialization i,s postponed until PL is LOW. Thus, automatic FIFO action is achieved by connecting the
i'RF output to the TTS input.

INPUT
R!Q.I~TI!!

____________ _

9423

OUTPUT
REGISTER

Fig. 2
FINAL POSITIONS IN A 9423 RESULTING
FROM A 256-BIT SERIAL TRAIN

7-213

•

FAIRCHILD • 9423
An RS Flip-Flop (the Request Initialization Flip-Flop shown in Figure 10) in the control section records the fact that data
has been transferred to the stack. This prevents multiple entry of the same word into the stack despite the fact the iffF and
TTS may still be LOW. The Request Initialization Flip-Flop is not cleared until PL goes LOW. Once in the stack, data falls
through the stack automatically~using only when it is necessary to wait for an empty next location. In the 9423, as in
most modern FIFO designs, the MR input only initializes the stack control section and does not clear the data.
Output Register (Data Extraction) ;. The Output Register receives 4-bit data words from the bottom stack location, stores it
and outputs data on a 3-state 4-bit parallel data bus or on a 3-state serial data bus. The output section generates and receives
the necessary status and control signals. Figure 3 is a conceptual logic diagram of the output section .

. - - - - - - - - O U T P U T FROM S T A C K - - - - - - - - ,

LOAD FROM STACK

Otfs---~~~~_t----_1------_t------_r-----_t-~-i_l

MR=~~--~--+_--4_--4_~

TOP

Fig. 3
CONCEPTUAL OUTPUT SECTION

Parallel Data Extra.ction - When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (CJRE)
output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the Output Register provided the Transfer Out Parallel Input (TOP) is HIGH. As a result of the data transfer
ORE goes HIGH, indicating valid data on the data outputs (provided the 3-state buffer is enabled). TOP can now be used to
clock out the next word. When TOP goes LOW, ORE will go LOW indicating that the output data has been extracted, but the
data itself remains on the output bus until a HIGH level at TOP permits the transfer of the next word (if available) into the
Output Register. During parallel data extraction CPSO should· be LOW. TOS should be grounded for single slice operation
or connected to the appropriate ORE for expanded operation (see Expansion section).
TOP is not edge triggered. Therefore, if TOP goes HIGH before data is available from the stack, but data does become available before TOP goes LOW again, that data will be transferred into the Output Register. However, internal control circuitry
prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from
the stack, ORE remains LOW indicating that there is no valid data at the outputs.

7-214

FAIRCHILD • 9423
Serial Data Extraction - When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (ORE) output is LOW. After data has been entered into the F IFa and has fallen through to the bottom stack location, it is transferred
into the Output Register provided TOS is LOW and TOP is HIGH. As a result of the data transfer ORE goes HIGH indicating
valid data in the register. The 3-state Serial Data Output (OS) is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to-LOW transition of CPSO_ To prevent false shifting, CPSO should be LOW
when the new word is being loaded into the Output Register. The fourth transition empties the shift register, forces ORE output LOW and disables the serial output, Os (refer to Figure 3). For serial operation the ORE output may be tied to the TOS
input, requesting a new word from the stack as soon as the previous one has been shifted out.
EXPANSION Vertical Expansion - The 9423 may be vertically expanded to store more words without external parts. The interconnections
necessary to form a 190-word by 4-bit F I Fa are shown in Figure 4_ Using the same technique, any F I Fa of (63 n+1 ) words
by four bits can be constructed, where n is the number of devices. Note that expansion does not sacrifice any of the 9423's
flexibility for serial/parallel input and output. For other expansion schemes, refer to the applications section of the
Macrologic/Bipolar Microprocessor data book.

PARALLE~

MASTER
RESET

PARALLEL
LOAD

DATA IN

I

I

D3 02 0,

DO

SERIAL DATA IN

J
L...- -

EO
MR

03 02 0, 00

as

Nle

L...--

9423

TOS
TOP

ORE

CPSO
EO

MR

Q3

Q3

-=-

°2

°2

l

Q

SERIAL
DATA OUT

Q, °0
I

I

PARALLEL DATA OUT

Fig.4
A VERTICAL EXPANSION SCHEME

7-215

DATA VALID

1 °0 Os

FAIRCHILD • 9423
Horizontal Expansion - The 9423 can also be horizontally expanded to store long words (in multiples of four bits) without
external logic. The interconnections necessary to form a 64-word by 12-bit FIFO are shown in Figure 5.. Using the same
technique, any FIFO of 64 words by 4n bits can be constructed, where n is the number of devices. The IRF output of the
right most device (most significant device) is connected to the TTS inputs of all devices. Similarly, the OR E output of the
most significant device is connected to the TOS inputs of all devices. As in the v.ertical expansion scheme, horizontal expansion does not sacrifice any of the 9423'5 flexibility for serial/parallel input and output.
It should be noted that this form of horizontal expansion extracts a penalty in speed. An expansion scheme that provides
higher speed but requires additional components is shown in the Applications section of the Macrologic/Bipolar Microprocessor data book.
Horizontal ,md Vertical Expansion - The 9423 can be expanded in both the horizontal and vertical directions without any
external parts and without sacrificing any of its FIFO's flexibility for serial/parallel input and output. The interconnections
necessary to form a 127-word by 16-bit FIFO are shown in Figure 6. Using the same technique, any FIFO of (63m + 1)
words by (4n) bits can be constructed, where m is the number of devices in a column and n is the number of devices in a row.

Figures 7 and 8 show the timing diagrams for serial data entry and extraction for the 127-word by 16-bit FIFO shown in
Figure 6.

rlD-3-D-2-Dl-D-O--------PARA~~E~6D~:A ~~PUT

,.

- - - - - - - - D --D--D--D--,8I
11 1O 9

III

I

•

risL Os D3 02 01
IES

IRF

--<: CPS I

~
~

PL DSD3 D2Dl
TTS
IES

DO

'-<:

OES
TOS
TOP
CPSG
EO

9423
ORE

MR 03 °2 Q 1 00

0S

U~
~

DO

PL

IRF

Y,

CPSI

OES
TOS
TOP

9423

~ EO

CPSG

OR EIo-

MR 03 02 01 00

u~

Os

~

TTS
IES
CPS I
OES
TOS
TOP
CPSG

Os

1

03 02 01

°0

IRF~
9423
DA TA
ADY

EO

OR EIo-

as

MR 03 02 01 00

DUMP

CPSG

'0
MR

03 02 °1 00

-=-

I

07 0 6

l Us a,

PARALlE L OAT A OUTPUT

Fig. 5
A HORIZON.TAL EXPANSION SCHEME

7-216

a"

1

9 °8

I

~

FAIRCHILD • 9423

I

INPUT CLOCK

r--I-<

~

I

~

PL DSD3 020100
TTS

c-IRF

IES

CPS I

1

DES

94'3

TOS
TOP

Lc
ORE

PL DSD3D2D1DO
TTS

IES
CPS I
OES

- - - < l TOS

,
9423

IRF

°302°1°0°5

-

~ EO

MR

Nle

MR

PL DSD3D2D1DO
TTS
IRF
IES
CPSI
ORE
DES

r-- I-<

,

'-<

ORE

9423

f---<:

TOP
CPSD

CPSG
EO

MR

f-8_ _ _ _ _ _ _ _0~IS'_O__".::4_0'_"3'_O~12CJI

Fig. 6
A 127 X 16 FIFO ARRAY

CPSI

1 I
I I
lD~

DEVfCE 1

k---------

~------------------~'r-

iRF

I

I

I

I

I

I

to ----+-l

DEVICE 2

t------

.,:,....;:..I1

L..__________________________________

IRF

," ,
'D+---<

DEVICE 3

I

IRF

'r,,

'--------;'-.:...11
I

~0~EV~I~eE~4~TT~S~A~L~L~O~E~V~le~ES~_________________________________________________________Ito~,

,

r--~

~

IRF

I

INPUTS
BITS

STDREO IN

:"lOIHD IN

DE'VICE 1

DlVIU 2

10

I

II

12

STOKfD IN
DEVICE 3

Fig. 7
SERIAL DATA ENTRY FOR ARRAY OF FIG. 6

7-217

13

I

14

STORED IN
DEVICE 4

•

FAIRCHILD • 9423

I I
I
lD~

DEVICE 5

I
I-+----

~------------------~,

ORE

I

I

I

I

t D-+---I

DEViCE 6

'---

...,:,....;.:.J\

ORE

L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

to+------!

~-

; II

DEVICE 7

ORE

I
I
~D~EV~'~CE~·B~,~TO~S~A~L~L~DE~V~'C~E~S

__________________________________________________~tlD~

I
I
~

I~rI,

aRE

DEVICE 5

DEVICE 6

DEVICE 8

DEVICE 7

Fig. 8
SERIAL DATA EXTRACTION FOR ARRAY OF FIG. 6

SERIAL
IN PUT

r

I I
Os

03

I"

I

O2

r r

I

I

f

I I

I

I

I

I

r
I

0,

Os

03

O2

0,

DO

DO

--------9423

9423

--------0 , 00 as

°3

°2

IIII

I

I

I

0,

Os

DO

--------2

03

00 as

Q

Q,

°0 Os

I I I I I

I I I I I
I

I

O2

03

9423

9423
a,

r IV
I I

--------9423

--------O2

I

I

Os

--------9423

03

I

1 I

I

I

I

I

Bl1 810 89

I

B8

Fig.9
FINAL POSITION OF A 2032-BIT SERIAL INPUT

7-218

I I I r
03

O2

0,

DO

--------9423

9423

--------o as
2 a,

03

Q

Q

I I I I I
I

I

I

I

SERI AL

QUIP UT

FAIRCHILD • 9423
Interlocking Circuitry - Most conventional F I Fa designs provide status signals analogous to iRF and OR E. However, when
these devices are operated in arrays, variations in unit to unit operating speed require external gating to assure all devices have
completed an operation. The 9423 incorporates simple but effective "master/slave" interlocking circuitry to eliminate the
need for external gating.
In the 9423 array of Figure 6 devices 1 and 5 are defined as "row masters" and the other devices are slaves to the master in
their row. No slave in a given row will initialize its Input Register until it has received LOW on its IES input from a row
master or a slave of higher priority.
In a similar fashion, the ORE outputs of slaves will not go HIGH until their OES inputs have gone HIGH. This interlocking
scheme ensures that new input data may be accepted by the array when the IRf output of the final slave in that row goes
HIGH and that output data for the array may be extracted when the OR E of the final slave in the output row goes HIGH.
The row master is established by connecting its IES input to ground while a slave receives its lESinput from the TRF output
of the next higher priority device. When an array of 9423 FIFOs is initialized with a LOW on the MR inputs of all devices, the
iRF outputs of all devices will be HIGH. Thus, only the row master receives a LOW on the TES input durinq initialization.
Figure 10 is a conceptual logic diagram of the internal circuitry which determines master/slave operation. Whenever MR and
IES are LOW, the Master Latch is set. Whenever TTS goes LOW the Request Initialization Flip·Flop will be set. If the Master
Latch is HIGH, the Input Register will be immediately initialized and the Request Initialization Flip·Flop reset. If the Master
Latch is reset, the Input Register is not initialized until TES goes LOW. In array operation, activating the TTS initiates a rip·
pie input register initialization from the row master to the last slave.
A similar operation takes place for the output register. Either a TOS or TOP input initiates a load·from·stack operation and
sets the ORE Request Flip·Flop. If the Master Latch is set, the last Output Register Flip·Flop is set and ORE goes HIGH. If
the Master Latch is reset, the ORE output will be LOW until an OES input is received.

IES

PL

-t>
-t>

-0

:::UMASTER
LATCH

or-I I

1
REG

STACK

IJERIVED FROM

TIs)

,

y

....

of-

s

REQUEST
INITIALIZATION

FLIP-FLOP

~R

INITIALIZE
(SEE FIGURE 11

- ....
S

R

0

1

f

II~PUT

op-

e
D

-t>v-

D

Fe
ISEE FIGURE 11

0
ORE REOUEST

FLIP-FLOP

~R

b?

6
s

0

FX
(SEE FIGURE 3)

II
C

R

p-

Y

4

LOAD OUTPUT {DERIVED FROM TOP AND TOS
REG:STER

TOP

f6S
DES

,

-

....
....

Fig. 10
CONCEPTUAL DIAGRAM, INTERLOCKING CIRCUITRY

7-219

f-t>o-

•

FAIRCHILD • 9423
DC CHARACTERISTICS: Over Operating Temperature Range (Notes 1, 2, 3, 4)
SYMBOL
VIH
VIL
VCD
VOH
VOH
VOL
VOL

LIMITS

PARAMETER

MIN

Input HIGH Voltage

2.0

Input LOW Voltage

0.7

XC

0.8

Input Clamp Diode Voltage

-0.9
XM

Output HIGH Voltage,

-1.5

3.4

TEST CONDITIONS

V

Guaranteed Input HIGH Voltage

V

Guaranteed Input LOW Voltage

V

VCC

=

MIN, liN

V

VCC

=

MIN, 10H

XC

2.4

3.4

Output HIGH Voltage,

XM

2.4

3.4

Go-0 3,OS

XC

2.4

3.1

Output LOW Voltage,

XM

0.25

0.4

V

10L

8.0 mA

°0-03,OS

XC
XM

0.35

0.5

V

10L

16 mA

0.25

0.4

XC

0.35

0.5

Output LOW Voltage, OR E, IRF

Output Off HIGH Current 00-03, Os
Output Off LOW Current 00-03, Os

IIH

Input HIGH Current

1.0

Input LOW Current, all except

ICC

2.4

UNITS

ORE, IRF

IOZL

lOS

MAX

XM

10ZH

IlL

TYP

DES,

MR

-30

XC

150

10L - 4.0 mA
10L

=

MIN

VCC

=

MIN

=

MIN

VCC

8.0 mA

=

VCC

100

J.lA

VCC

J.lA

VCC - MAX, VOUT - 0.5 V, VE - 2.0 V

40

J.lA

VCC - MAX, VIN - 2.7 V

1.0

mA

VCC - MAX, VIN - 5.5 V

mA

VCC

=

MAX, VIN

mA

VCC

=

MAX, VOUT

mA

VCC

=

MAX, Inputs Open

-130
150

5.7 mA

-400/lA

-100

-0.72

XM

V

=

10H - -2.0 mA
10H -

-0.36

Input LOW Current, OES, MR

Output Short Circuit Current
QO-0 3,OS,ORE,OES
Supply Current

V

-18 mA

=

=

MAX, VOUT

=

=

2.4 V, VE

=

2.0 Y

004 V
=

0, (Note 5)

NOTES:
1.
2.

Conditions for testing, not shown in the Table, are chosen to guarantee operation under "worst case" conditions.
The specified LI M ITS represents the "worst case" value for the parameters, Since these "worst case" values normally occur at the
temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system

3.

Typical limits are atVCC "" 5.0 V, TA = +25°C, and MAX loading.
The Temperature Ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. For military range an additional
requirement of a two minute warm-up. Typical thermal resistance values of the package at maximum temperature are:
8JA (Junction to Ambient) (at 400 fpm air flow) "" 50°C/Watt, Ceramic DIP; 65°C/Watt. Plastic DIP; NA, Flatpak.
8JA (Junction to Ambient) istill air) = 90°C/Watt, Ceramic DIP; 110°C/Watt, Plastic DIP; NA, Flatpak.
8JC (Junction to Case) = 25 C/Watt, Ceramic DIP; 25°C/Watt, Plastic DIP; 10°C/Watt, FJatpak.
Duration of short circuit should not exceed one second, not more than one output should be shorted at a time.

operating ranges,

4.

5.

AC CHARACTERISTICS: Vee ~ 5.0 V, eL ~ 15 pF, TA ~ 25°e (Note 3)
SYMBOL

LIMITS

PARAMETER

MIN

TYP

MAX

UNITS

tpHL

Propagation Delay. Negatlve·Golng
CP to IRF Output

27

ns

tpLH

Propagation Delay. Negatlve·Golng
TTS to IRF

62

ns

Propagation Delay. Negatlve·Golng

39

ns

26

ns

tpLH.
tPHL

CPSO to

Os

Output

COMMENTS

Stack not Full, PL LOW.
Figures 11 and 12

OES LOW. TOP HIGH,
Figures 13 and 14

tpLH,

Propagation Delay. Posltlve·GOIng

73

ns

tpHL

TOP to Outputs 00

61

ns

tpHL

Propagation Delay. Negative·Golng
CPSO to ORE

27

ns

OES LOW. TOP HIGH.
Figures 13 and 14

tpHL

Propagation Delay. Negative·Golng
TOP to ORE

40
ns

Parallel Output,
Figure 15

tpLH

Propagation Delay, Positive·Golng
TOP to ORE

70

tDFT

Fall Through Time

3.6

Jls

TTS Connected to IRF
TOS Connected to ORE
IES. OES, EO. CPSO LOW,
TOP HIGH. Figure 16

tpLH

Propagation Delay. Negative-Going
TOS to Positive-Going ORE

70

ns

Data In stack, TOP HIGH.
Figures 13 and 14

03

7-220

EO, CPSO LOW.
Figure 15

m. CPSO LOW.

FAIRCHILD • 9423
AC CHARACTERISTICS (Cont'd): VCC = 5.0 V, CL = 15 pF, TA = 25°C
SYMBOL

-

LIMITS

PARAMETER

MIN

TYP

MAX

UNITS

COMMENTS
Stack not Full,
Figures 17 and 18

tpHL

Propagation Delay, Positive· Going
PL to Negative-Going IRF

34

ns

tpLH

Propagation Delay, Negative-Going
PL to Positive-Going IRF

38

ns

tpLH

Propagation Delay, Positive-Going
OESto ORE

31

ns

tpLH

Propagation Delay, Positive-Going
iES to Positive-Going IRF

28

ns

Figure 18

12

ns

Propagation Delay Out of
the High Impedance State

14

ns

Propagation Delay Into
the High Impedance State

tpZL,
tpZH

-

ProQagation Delay,
DE to ° 0 ,° 1,°2,°3
Propagation Delay,

tpZL,
tpZH

Propagation Delay, Negative-Going
DES to Os

12

ns

Propagation Delay Out of
the High Impedance State

tpLZ,
tpHZ

Propagation Delay, Negative-Going
DES to Os

14

ns

Propagation Delay Into the
High Impedance State

tAP

Parallel Appearance Time,
ORE to 00 ~ 03

12

ns

Time elapsed between ORE
going HIGH and valid data

14

ns

DE to ° 0 ,° 1,°2,°3

Serial Appearance Time,
ORE to

Os

-

-

-

appearing at output. Negative
number indicates data available

before ORE goes HIGH

AC SET·UP REQUIREMENTS: VCC = 5,0 V, CL = 15 pF, TA = 25°C
SYMBOL

-

tPHZ,
tpLZ

tAS

-

-

LIMITS

PARAMETER

MIN

TYP

MAX

UNITS

COMMENTS

tpWH

CPSI Pulse Width (HIGH)

10

ns

Stack not full, PL LOW,

tpWL

CPSI Pulse Width (LOW)

15

ns

Figures 11 and 12

tpWH

PL Pulse Width (HIGH)

10

ns

Stack not full, Figures 17 and 18

tpWL

TTS Pulse Width (LOW) Serial or
Parallel Mode

23

ns

Stack not full,
Figures II, 12, 17, 18

tpWL

MR Pulse Width (LOW)

22

ns

Figure 16

tpWH

TOP Pulse Width (HIGH)

40

ns

CPSO LOW, data available In stack,

tpWL

TOP Pulse Width (LOW)

24

ns

Figure 15

tpWH

CPSO Pulse Width (HIGH)

10

ns

TOP HIGH, data In stack,

tpWL

Cl5Sn

16

ns

Figures 13 and 14

ts

Set-up Time,

6

ns

PL LOW, Figures 11 and 12

3

ns

PL LOW, Figures 11 and 12

-22

ns

Figures 11,12,17,18

0

ns

TOP HIGH,
Figures 13 and 14
Figure 16

Pulse Width (LOW)

Os

Os

to Negative CPSI

th

Hold Time,

ts

Set-up Time, TTS to IRF Serial
or Parallel Mode

to CPSI

ts

Set-up Time Negative-Going ORE
to Negative-Going TOS

-

-

-

tree

Recovery Time MR to any Input

23

ns

ts

Set-up Time, Negative-Going IES to CPSI

17

ns

Figure 12

ts

Set-up Time, Negative·Going TTS to CPSI

85

ns

Figure 12

ts

Set-up Time, Parallel Inputs to PL

-16

ns

Length of time parallel Inputs must be
applied prior to rising edge of PL

th

Hold Time, Parallel Inputs to PL

10

ns

7-221

Length of time parallel Inputs must

reamtn applied after fall1l19 edge of PL

•

FAIRCHILD •

9423

3V

tpHL
TIif ____________________________________________________
,Ik---

'\

1m

ITS ___________________________________________________::f==tPLH;:.:~_-_.j_________
0

~13V

r:='PWL=:j
Fig. 11
SERIAL INPUT, UNEXPANDED OR MASTER OPERATION
Conditions: stack not full, I ES, PL LOW

iEs ______"'\

~-----------------------------------------------------;

Fig. 12
SERIAL INPUT, EXPANDED SLAVE OPERATION
Conditions: stack not full, IES HIGH when initiated, PL LOW

Os
O~E

1.3V------lIlOOiW------I
______________________________________________

+-~,

tpHL :~ _ _ _ _ _ _ _J

',' °'--lI---tPLH---I
TOS------------------------------------------------~~r-----------------

l--tpwL::j
Fig. 13
SERIAL OUTPUT, UNEXPANDED OR MASTER OPERATION
Conditions: data in stack, TOP HIGH, I ES LOW when initiated, OES LOW

7-222

FAIRCHILD •

9423

OES _ _ _ _---.,

CPso _ _ _J

ORE ____________________________________________________~

TOS ____________________________________________________~~

Fig. 14
SERIAL OUTPUT, SLAVE OPERATION
Conditions: data in stack, TOP HIGH, IES HIGH when initiated

TOP ______- - .

ORE __________-..

1.3

V

*

tPLH-----J

________________________

'P~HL___:I~---

00 - 03

1.3

v-~

NEW OUTPUT

Fig. 15
PARALLEL OUTPUT, 4·BIT WORD OR MASTER IN PARALLEL EXPANSION
Conditions: IES LOW when initiated, EO, CPSO LOW; data available in stack

MR

r -4
""\-',--1.3V----tpw

~
PL _____________-J~~~~~~==~~~1_.3_V
I~tpw--.l tOFT

=:j ,,,,

___________

00 -- 03 ____________________________________

·1

~3 V

Fig. 16
FALL THROUGH TIME
Conditions: TTSconnected to

iRF,

TOSconnected to ORE, IES, OES, EO, CPSO LOW, TOP HIGH

7-223

•

FAIRCHILD • 9423

1.3 V
pL------------~-J

rnF----------------~------------~
3)

TTS (NOTE 2 ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

\-----I,--,·3v---'---~'PW~

Fig. 17
PARALLEL LOAD MODE, 4-BIT WORD (UN EXPANDED) OR MASTER IN PARALLEL EXPANSION

Conditions: stack not full, IES LOW when initialized

PL-----JtI" ----------'\-I ---------- --F
I

'pw

~
DO-D3~~~~.
iE8----------"'"

Fig. 18
PARALLEL LOAD, SLAVE MODE

Conditions: stack not full, device initialized (Note 1) with I ES HIGH

NOTES:
1.

Initialization requires a master reset to occur after power has been applied.

2.

TTS normally connected to IRF.

3.

If stack is full,

iFiF

will stay LOW.

7-224

I-'h

INTRODUCTION

NUMEfOCAllNOEX OP,' DE\/ICE~S

....

,.- ..

SELECTION GUIOES '

GENERAL CHARACTERISTICS

RAMs

,
,

"V"

PROMs,

, PRODUCTINFORMATior.i/DATASHEETS .
.

ORDER AND PACKAGE INFORMATION

~

-'

CHAPTER 8
•
•
•
•
•
•
•
•

Package Style
Temperature Ranges
Examples
Device Identification/Marking
Package Information
Package Information
Hi-Rei Processing
Hi-Rei Processing Flows
Package Outlines

ORDER AND PACKAGE INFORMATION
Fairchild bipolar memories may be ordered by using a simplified purchasing code where the package style and temperature range is defined as follows:
PACKAGE STYLE
D = Dual In-line - Ceramic (hermetic)
P = Dual In-line - Plastic
F = Flatpak
XXXXX

D

C

~Tempe,a,",e Range Code
Package Code
1-.-_ _ _ _ _ _

Device Type

In order to accommodate varying die sizes and numbers of pins (16, 18, 24, etc.), a number of different package forms are required. The Package Information list on the following pages indicates
the specific package codes currently used for each device type. The detailed package outline corresponding to each package code is shown at the end of this section.
TEMPERATURE RANGES
Two basic temperature grades are in common use: C = Commercial-Industrial, OOC to +75°C; M =
Military, -55°C to +125°C. Exact values and conditions are indicated on the data sheets.
EXAMPLES:
(a)

93415FM
This number code indicated a 93415 1024 x 1 RAM in a flatpak with military temperature
rating.

(b)

93421 DC
This number code indicates a 93421 256 x 1 RAM in a ceramic dual in-line package with
commercial temperature rating.

(c)

93436PC
This number code indicates a 93436 512 x 4 PROM in a plastic package with a commercial
temperature rating.

DEVICE IDENTIFICATION/MARKING
All Fairchild standard catalog bipolar memories will be marked as follows:

Device Type XX
Date Code

8-3

•

PACKAGE INFORMATION
Military (M)
DEVICE

-55°C to +125°C
Ceramic
DIP (D)

F10145A
F10405
F10410
F10411
F10414
F100414
F10415
F10415A
Fl00415
F10416
F100416
F10422
F100422
F10470
F100470

93410
93410A
93411
93411A
93L412
93412
93L415
93415
93415A
93417
93419
93L420
93L421
93421
93421A
93L422
93422
93L425
93425
93425A
93427
93436
93438
93446
93448
93450
93451
93452
93453
93458
93459
93L470
93470
93L471
93471
93475
93481
93481A

9403
9406
9410
9423

Flatpak (F)

-

60

3L

60

3L

-

-

60

3L

-

60

3L

8T
8T
60
60

4P
4P
3L
3L

60
7Y
60
60
60

3L
3L
3L
3L

-

8T
8T
60
60

4P
4P
3L
3L

-

-

60
60
7L
60
7L
7L
7L
8F
8F

3L
3L
4P
3L
4P

-

2E
2E
20
20
20
20
20

7T
7T
7T
7T
7T

-

-

6Y
6Y
8F
6Y

4M
4M
4M

Commercial (C)/Industrial
OOC to +75°C

DEVICE

Ceramic
DIP (D)

Plastic
DIP (P)

F10145A
F10405
F10410
F10411
F10414
F100414
F10415
F10415A
F100415
F10416
F100416
F10422
F100422
F10470
F100470

68, 4J
60
60
60
60
60
60
60
60
60
60
6Y
6Y
7T,8F
7T,8F

98

93410
93410A
93411
93411A
93L412
93412
93L415
93415
93415A
93417
93419
93L420
93L421
93421
93421A
93L422
93422
93L425
93425
93425A
93427
93436
93438
93446
93448
93450
93451
93452
93453
93458
93459
93L470
93470
93L471
93471
93475
93481
93481A

60
60
60
60
6S, 8T
6S,8T
60
60
60
60
7Y,8S
60
60
60
60
6S, 8T
6S,8T
60
60
60
60
60
7L
60
7L
7L
7L
8F
8F
8S
8S
7T,8F
7T,8F
7T,8F
7T,8F
7T,8F
6E
6E

98
98
98
98

9403
9406
9410
9423

6Y
6Y
8F
6Y

9U
9U
9M
9U

8-4

98
98

-

9U
9U

-

98
98
98
98
9Y
98
98
98
98
98
98
98
98
98
9N
98
9N
9N
9N
9M
9M
9Y
9Y
9M
9M
9M
9M
9M
98
98

Flatpak (F)

4L
3L
3L
3L
3L
3L,40
3L
3L
3L,40
3L
3L
4P
40
2F
2F,40

3L
3L
3L
3L
4P
4P
3L
3L
3L
3L
2E
3L
3L
3L
3L
4P
4P
3L
3L
3L
3L
3L
4P
3L
4P
4P
4P

2E
2E
20
20
20
20
20
48
48

4M
4M
4M

HI-REL PROCESSING
Fairchild's Bipolar Memory/ECl Products Division offers HI-REl processing for both military and commercial customers. Fairchild's UNIQUE 38510 program provides military customers an opportunity to
purchase state-of-the-art lSI memory circuits processed to the latest version of Mll-M-38510/MllSTD-883. The UNIQUE 38510 program is available for processing to specific customer drawings or may
be ordered directly from the QB or QC processing flow.
For commercial customers, the reliability of standard product can be improved by requiring burn-in on
all devices with the QP process flow.
All HI-REl TTL RAMs and ROM/PROMs may be purchased in dual in-line and flatpak ceramic packages,
with the exception of the 93419 which is only available in the dual in-line package.
In addition to the HI-REl processing flows shown, these additional HI-REl steps are available upon request:
- State-side assembly
- Radiography MTD 2012
- SEM Analysis
- PROM Programming (single or multiple pulse)
- Special lead form
- Read and record critical parameters before
and after burn-in

•
8-5

HI-REL PROCESSING FLOWS
MILITARY CUSTOMERS
UNIQUE 38510
MIL-STD-883A
METHOD 5004.3
Preseal Visual
MTD 2010

DESCRIPTION
Condo B Optimum Visual Criteria
~

QB

QC

PRESEAL VISUAL

PRESEAL VISUAL

COND.B

CONDo B

COMMERCIAL CUSTOMERS
STD PRODUCT PLUS BURN-IN
QP
PRESEAL VISUAL
FAIRCHILD STD
FICF·ST·2011

I
Bond Strength

Bond strength is monitored on a sample
basis three times per shift per machine

Seal

Devices are hermetically sealed for
compliance to MIL-STD-883 requirements

High Temp Storage

Condo C Tstg = 150°C

co
I

BOND STRENGTH
ACCEPTANCE

CJ)

I
SEAL

SEAL

I
r-MTD 1008

BAKE
COND.C
24 HRS.

BAKE
CONDo C
24 HRS.

I
Temperature Cycle

Condo C -65°j150 0 C 10 cycles

TEMP CYCLE

TEMP CYCLE

COND.C

CONDo C

TEMP CYCLE
MTD 1010, 5 CYCLES
CONDo C

~

MTD 1010

I
Constant Acceleration
MTD 2001

Condo E 30000 G's Y1

:--

CENTRIFUGE
CONDo E
Y1 0NLY

•

CENTRIFUGE
CONDo E
Y1 0NLY

t

,

,---

A Fine-Helium 5x10- 8 cc/sec
B Fine-Radiflo 5x10 -8cc/sec
C1 Gross-FC43/Hot 10-5 cc/sec
C2 Gross-FC78/Vacuum 10 -3cc/sec

Hermetic Seal
MTD 1014

Condo
Condo
Condo
Condo

Pre Burn-in
Electrical
5004

25°C DC electrical testing to
remove rejects prior to
submission to burn-in screen

-

HERMETICITY
CONDo A/B
CONDo C2

-

OPTIONAL
PRE B/I ELECT
25°C DC

HERMETICITY
CONDo A/B
CONDo C2

I
I
BURN-IN
168 HRS @l 125°C

Burn-in Screen
MTD 1015

I

'-...j
1"

Post Burn-in
Electrical
5004

Post Burn·in electrical screening
to cull out devices which failed as
a result of burn-in.

Quality Conformance
Inspection
MTD 5005

Group
Group
Group
Group

External Visual
MTD 2009

3X. 10X magnification: Verify
dimensions. configuration. lead
structure. marking and workmanship

-

POST B/I ElECT
25°C DC
t125°C DC
-55°C DC
25°C AC
25°C FUNCTION

FINAL ELECT
25°C DC
25°C FUNCTION

I
A:
B:
C:
D:

Electrical Characteristics
Package oriented Tests
Die-related Tests
Package Tests

~

QUALITY
CONFORMANCE
GPA.B.C.D

QUALITY
CONFORMANCE
GPA.B.C.D

I

•

I--

EXTERNAL VISUAL
MTD 2009

EXTERNAL VISUAL
MTD 2009

PACKAGE OUTLINES
20

18- Pin Flatpak

r~

~

18

F===f

.018 (0.48)

1===:::::1 .016TYP.
(0.38)

.420
(10.67)

l~

10

.

I.

-

J.

.1 .05~.j~.27)

NOTES:
Pins are tin - plated alloy 42 or equivalent
Cap isAI203
Base is BeO
Package weight is 0.7 gram

.300 (7.62)
MAlt

.006 (0.15)
.004 (o.lOU

T ~~====~§§§§§§~~§§§§§§:~~~~·~
I-I
~ f
[.045(1.14)
MAX
•

.39O(9.91) _ _ _.~
••300(7.62)

.065(2.16)

MAX.

SQ.

MAX.

28-Pin Flatpak

~PINNO.l

1_

r-

.310(7.871
MAX.

2E

J

~

~
1 28

1

.625
115.881
MAX.

.700
117.78,

~

+

i
.05011.271 TYP.

1415

NOTES:
Pins are tin - plated alloy 42 or kovar
Cap and base are AI203
Package weight is 1.0 gram

.040
11.021

L
r-===4==I~'~:===I~t*
.005
(0.131
REF.

~ .390 ~

f

(9.911

.049
[1.241

MAX.

MAX.

All dimensions in inches (bold) and millimeters (parentheses)

8-8

PACKAGE OUTLINES
18-Pin Flatpak
PIN #1
IDENT·7

r

1

~

18

r-

.018 10.48)
.016 10.38)
T YP.

.420
110.S71

I
.006,0.151
.00410. 101

10

9

.010 11.27)
TYP.

:

[.04511.14)
MAX.

I---

.390 19.91)
SQ.

16- Pin Flatpak

1.

".300 17.62t
MAX•

I

:

,

--1..300 17.62)~ .1..
MAX.

-

16

48

16- Pin Flatpak

1.

~

f

16

I

-

.060
(1.270)
TYP.
.410(1 0.414)
.370 (9.398)

.019 (.482)
.015 (.381)
TYP.

.050
(1.270)
TYP.
.410(1 0.414)
.370(9.398)

.019 (.482)
.015 (.381)
TYP.

~

.006 (. I 52)
. 004 (.101)

(2.16)
MAX.

3L

-

-,-

NOTES:
Pins are tin-plated alloy 42 or equivalent
Cap and base are AI203
Package weight is 0.7 gram

~

1

T

2F

8

~

.350
.250
(8.890)
(S.350)
TYP.

~

~

-,-

9

h·35t~
.250
(8.890)
(S.350)
TYP.

085 (2 IS)
.
.
.060(1.52)

.006 (. 152)

(8.890)
(S.350)
TYP.

9

.250
h·35~~
(8.890)
(S.35O}
TYP.

.004(.101).-.:::==={~~~~~~~~~~

4===E~~E~~
t
I
J
.280 (7. I 12)
~ .245 (S.223) - - ,

8

~ .250
.350 ~

4=-

.038 (0.97)
TYP.

NOTES:
Pins are tin - plated alloy 42 or kovar
Cap and base are AI203
PaCkage weight is 0.4 gram

I

.280 (7.112)
J
~ .245 (6.223) - - ,

8-9

t

~
.045(1.14)

NOTES:
Pins are tin - plated alloy 42 or kovar
Cap isAI203
Base is BeO
Package weight is 0.4 gram

All dimensions in inches (bold) and millimeters (parentheses)

.085 (2. I 59)
.060 (1.524)

TYP.

•

PACKAGE OUTLINES
16- Pin Ceramic Dual In-line

r---.
If\,

4J

7S5 (19.939)----1

A 11.756 (19.177)(\

(\

III

IS

(6.S83)
.271
(6.223)
.245

.025 (.635) R
NOM.

NOTES:
Pins are tin - plated alloy 42
Cap and base are AI203
Pins are intended for insertion in hole
rows on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Broad-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight is 2.0 grams

~~9TT~~~-r~rT~

.110(2.794)
.090 (2.286)

TYP

16-Pin Flatpak

24-Pin Flatpak

4M

.050 (1.270)
TYP

1

-

16

~:~~f'!.~~.~~~~§

!
.050
(1.2701
TYP.

I

.410(1 0.411
.370(9 .401

-r-

6

L
!
.019 (.463)

.019 (0.4831
.015 (0.3811
TYP.

7
8
9

.015(.381)

10
11

TYP

---L-

h· °ri

:gg::g::~~:

.250
36
(8.8901
(6.3601
TYP.

8

9
.250
h·35~oTi
(8.8901
(6.3501
TYP.

.28017.111.1
.24516.221 ~

.620
(1~~8)

~.350 (8.89~l~

.250 (6.350) .090 12.2861

.08512.161
.045(1.141

.06611.6511

~===I'-____-'F___
= =-.,_"-_
-l I
-rI-

22=
21=
201:=
19
18
17
16
16
14
13

3

4
6

j
.006 (.1521
.004 (.102)

.024(0.6101
TYP.

I

.395 (10.033)

1---.366 (9.271)

I
--I

NOTES:
Pins are tin-plated alloy 42
CapisAI203
Base is BeO
Package weight is 0.8 gram

NOTES:
Pins are tin-plated alloy 42
Cap and base are AI203
Package weight is 0.4 gram

All dimensions in inches (bold) and millimeters (parentheses)

8-10

PACKAGE OUTLINES
24 - Pin Flatpak

4P

.01910.481

~\\ //;.

T

T

TYP.

1 24

.567
114.401

.050
...L11.271

I

TYP.

T

1213

NOTES:
Pins are tin - plated alloy 42
Cap and base are AI203
Package weight is ~ 0.8 gram

fjj \\'

.08512.161
.0601~

1

I

1_

.045 11.141~
.02510.641

+

;

.400 110.161
.370~Q~.4OI

~_ .30017.621

~T.006
10.151
.00410.101

MAX. TYP.

24-Pin Flatpak

40

0'02~~~~4®,1
•

24

1/,=
,.-l-,¥-,..LLJlJ...l.J!....LL-,

I[~
0.050 TYP
11.271 TYP
Note (2)

.

NOTES:
Pins are tin - plated alloy 42 or equivalent
Cap is AI203
Base is BeO
Package weight is 0.8 grams

,'--"!'T'"T'T"rT"1T"!T"TT""""'

,
1

0.081 12.061_
0.055 (1.401

1-

.008 10.201
.00410.101

+

All dimensions in inches (bold) and millimeters (parentheses)

8-11

•

PACKAGE OUTLINES
16- Pin Ceramic Dual In -line

68

.785 (19.939)---------1
.755 (19.177) 1\ 1\

I-

!Ii

t

(6.883)
.271
(6.223)
.245

.025 (.635)

R

NOM.

-·-~~~-rrT~~~~~

NOTES:
Pins are tin-plated alloy 42
Cap and base are AI203
Pins are intended for insertion in hole
rows on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Broad-drilling dimensions should equal your
practice for .020" (0.508) diameter pin
Package weight is 2.0 grams

.110 (2.794)
.090 (2.286)
TVP

16- Pin Ceramic Dual In -line

60

r - - . 7 8 5 (19.941---,

I[) A A .755 119.181,

fiJlI
NOTES:
Pins are tin-plated kovar or alloy 42
Cap and base are AI203
Pins are intended for insertion in hole
rows on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight is 2.2 grams

r

:~~~~~:~~~~~~~=n~~~~~rd

*

SEATING
PLANE .16514.191

.10012.541

.11012.7~

.09012.271

.02710.681
STANDOFF

All dimensions in inches (bold) and millimeters (parentheses)

8-12

PACKAGE OUTLINES
16- Pin Ceramic Dual In-line
(Metal Cap)

6E

rr;

.785(19.94)
.770(19.S6)1]
_.470 (11.938)•
.430 (10.922)
.100 (2.540)

.--- 8
I
.300(7.62)
.280(7.11)

L

D

1
_

.130(3.302)
.026 (0.660)
NOM.

~NOM.

HF:~~g !j~~::

16 - - - ,
.004 (0.1 0)MIN050 1 27
11.095(2.411
.
I
L-~(1.8 1
.J~5(064)
9

.160 (4.064)
.110(2.794)

SE~~~~

.160 (4.06) t

.125(3.18~

.110 (2.794)
.090 (2.286)
TYP

Mix) ~5(1.401

II

r

-+

I

.285 (7.239)
.265(6.731)

-.i

.020 (0.508)...:11__
.015 (0.381) I 1
r+I .056 (1.42)
.050(1.27)

t

.01210.301
.00910.231

I_(9.525)--1
.375
I
MAX.

22-Pin Ceramic Dual In-line

~11

1

.38019.65)

r

65

.025 10.64) R.
NOTES:
Pins are tin-plated alloy 42
Cap and base are AI203
Pins are intended for insertion in hole
rows on .400" (10.16) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight is 2.2 grams

24

.364

NOTES:
Pins are gold-plated alloy 42
Cap is gold - plated kovar
Base is AI203
Pins are intended for insertion in hole
rows on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight is 2.0 grams

) "Tin-t"7T"1lT"lT""l'T"7"t""'rTt"7-riiT':

.100
12.54)

All dimensions in inches (bold) and millimeters (parentheses)

8-13

•

PACKAGE OUTLINES
24-Pin Ceramic Dual In-line

6Y

r-- 1.230 (31.241----1
1

"I\/V' 1.185 (30.101 \1\1\(1

1

~EI::::::::::::~r~~
~ .085(1.651
.045(1.141

_.[

.180
(4.571
.150(3.811

T-

i L.065(1.651

.040(1.021

---+j

.

.050(1.271

L~'641

1=

.150(3.811
.100(2,541

SEATING

~~

t

PLANE

--I,110(2.7941
~
. .037 (.9401--1\'-,020
(.5081
,016 (.4061
,.

.090(2.2861

.027 (.6861

~.400
(10.1601~
NOM.

~
.011 (.279

~

~

.515
(13.081

=I

NOTES:
Pins are tin-plated alloy 42
Cap and base are AI203
Pins are intended for insertion in hole
rows on .400" (10.16) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0,508) diameter pin
Package weight is 6.0 grams

MAX.

STANDOFF
WIDTH

24 - Pin Ceramic Dual In -line

7L

1---1.290132.7661----j

I

11\1\1\/1.235 131.3691 \1\1\/\

I

121110 9 8 7 6 5 4 3 2 1

.030 (0.7621 R
.020 (0.5081

.550 (13,971
.515 (13,081

NOTES:
Pins are tin - plated alloy 42
Cap and base are AI203
Pins are intended for insertion in hole
rows on .600" (15.24) centers
They aer purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0,508) diameter pin
Package weight is 6.5 grams

L~~~~A=H
r-.

088 11.731
....1
.190 14,S261
/.1.02810,711
.14~6...1_ _ _ _ _ _ _ _ _ _!-"1' :~g:~:g~:

L

,-..-i

r==,

.150 (3,81 I
.10012,541

I
--1

.037 10.9401
.02710.6861

.11012.7941
.090 12.2861

~~

f

.020 10.50S1
.01610.4061

STANDOFF
WIDTH

TYP.

All dimensions in inches (bold) and millimeters (parentheses)

8-14

PACKAGE OUTLINES
18-Pin Ceramic Dual In-line
(Metal Cap)

.880'22.351
,'00
,2286

7T

,

NOTES:
Pins are gold - plated kovar
Cap is gold - plated kovar
Base is AI203
Pins are intended for insertion in hole
rows on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight is 1.3 grams

28-Pin Ceramic Dual In-line
(Metal Cap)

.025 (.06351 R

j

L

(15.4941
.610

.060 {1.5241

tl:~g6-1-

.040 (1.0161
.095 (24131 (4.0641
.065(1.6511 .160

.045(1141
.025(0641

~.110

L~

T~
~ UUUU(1143~
UU~ lUI ~ UUUl
~ 1-!
l2794 1

.125 (3175)
MIN.

:6~g

:g~~

(22861
TYP.

(1.016)
TYP.

r

(1 ~~gol
:480
(126921

--11-.020 (5081
.016 (4061

=4

~g~~ Ui~:
~71451 I

(2794)>>"

I

'l

9

7Y

NOTES:
Pins are gold-plated kovar
Cap is gold-plated kovar
Base is AI2D3
Pins are intended for insertion in hole
rows on .600" (15.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight 4.0 grams

~X~-

All dimensions in inches (bold) and millimeters (parentheses)

8-15

•

PACKAGE OUTLINES
18- Pin Ceramic Dual In -line

t

.90012286'
.880122.351

SF

I

'

NOTES:
Pins are tin-plated kovar
Cap and base are AI203
Pins are intended for insertion in hole
rows on .300" (7.62\ centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight is 3.0 grams

28- Pin Ceramic Dual In -line

1-

.18014.57:

.14013.561

t·~;::;;::;;;;::;;~:;::;:;:;;:;;;;~ .025 (0.641
I

I~,

.145(3.68)
~----:
.100 12.54.,

600NOM
(15

24'-1

.055(1.40'

----I

I

.110(2.791

-MoT2:271

I~

il

I f i l l-PLANE

.037(0.94) _
-:027 (0.681

ST:~~~FF

I

-L.020(O.511
I,

_I

I ,..-----,,-----

I~SEATING
~016

(0.41)

8S

NOTES:
Pins are tin-plated alloy 42
Cap and base are AI203
Pins are intended for insertion in hole
rows on .600" (15.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Broad-drilling dimensions should equal
your practice for .020" (0.508) diameterpin
Package weight is 7.5 grams

I~_.750 (,
I
9.05----j
MAX

.068~1
.02810.711

All dimensions in inches (bold) and millimeters (parentheses)

8-16

PACKAGE OUTLINES
22-Pin Ceramic Dual In-line
(Metal Cap)

D

aT

r-----1.095 (27.812)--j

1 ___ 1.065(27.051)
11

I
1

12

I

1---.03210.81)R.

~.38~6~~61
~

22

----I f---

r-- -1

.330

.09512.411
.07511.901

1.430 I
10.92

.05011.271
.02510.641

'~'''GI L~.

"",r.;;-~

PLANE - ,

~.012
L J

T

II
]11-

~

I '

.125(3.175)
.11012.791 .020 (0.511 .03210.811
.09012.291 .01610.411 STANDOFF

.11512.921

~:J12.161

~

(0.301
.00810.201

.400
110.160)
NOM .

.05011.271
.03010.761

16-Pin Plastic Dual In-line

r----r-, ('-,

I

~: ~~:I:

-------j

.740118.801, !)

1

IJ I-

.065 11. 651
.045111431

r'l I

3

,11.9051

.012 10.3051

0

~

I L .02510.6351

--I

NOM.

.020 10.5081
I- .300 176201~ 010 10.2541
, .290173661 I'

~rrmrno" A ' +-1"-~TL
i
i

MAX...801
.20015,0
Seating ~
I
Plane

NOM.
. 10.3811

I

I

,

.

~

I

I!
,1__

98

.025 10.635)
.020 10.508)~

.770119.561

:::::]:i~~:,o4~iOl;i§
I'

NOTES:
Pins are gold - plated kovar
Cap is gold - plated kovar
Base is AI203
Pins are intended for insertion in hole
rows on .400" (10,16) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Broad-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight is 2.0 grams

11_'
I

,15013,81011
l.ll0,j
,100 12,540)[---1' ,090 I
12.794)
12.2861

***

t

.037 II ,020105081
,027-11-,01610.406)
10.9401
10.6861
STANDOFF
WIDTH

.'
L,375NOM .. I
,
19.5251--1

NOTES:
Pins are tin-plated kovar or alloy 42
Package material varies depending on
the product line
Pins are intended for insertion in hole
rows on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for ,020" (0.508) diameter pin
Package weight is 0.9 gram

,011
,009
(0.279)

102291

All dimensions in inches (bold) and millimeters (parentheses)

8-17

II
:

PACKAGE OUTLINES
18-Pin Plastic Dual In-line

~ ..

11\ (

____ .910(23.1'4)_~_~____,

~

.890 (22.606)

I

A

~:?:I~ ~ :~,:): :::L ~rm:
)

I .083 (2.108)

J

.200

(5.080)

~I

I

i

.073 (1 .854)

I<-~~~~ :~~g ~;.~~~j

.030 .085

.020 .075
(.508) (1 .905)

50 TYP.

~

r-------11231
-d--

241 (6121)

( 762) (2. 159)

I

I

(5867)

\I,olYP

'60(192)mrmmr-=9=F~~=F1=C-=~
1 ~-JI
145(368)
I i
JSp~~~~G L-O~'='=(~27~9-')'

t--I

J

(~~~)
MIN
050(127)
NOM.

I

I

ILL

II

!"""

~~(~~g)---.jl10
,'016

(20~904)

(.406)

(2.286)

_

_

r_~

__

1.260 (32.004) _ _

-1

1.240 (31.496)

1\

I

I
1.--

I

380(965)------1
NOM.

1
.050 R (1.27)

NOTES:
Pins are tin-plated kovar
Pins are intended for insertion in hole
rows on .600" (15.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board -drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight 3.5 grams

I

~. t:Fn::;r:rrn=;nr=rn=n=n=:#?
.065 (1.6511
-.045(1.143)

L_
_11_

--,I

.090 (2.286)
.065 (1.651)

.w""

.160 (4.061
.145(3.683)

.045 NOM
(1.14)

.020 (.508)

~~

I
T-

+----,

.130 (3.30)
.115 (2921)

9N-2

I

I
.560 (14.224)
.540 (13.716)

+~.

NOTES:
Pins are tin - plated kovar
Pins are intended for insertion in hole
rows on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight 2.0 grams

009(229)
125(318}
NOM

060
(1.524)

24-Pin Plastic Dual In-line

II

9M-2

--I

I

i (2.794)
110
I
1-:090 -j
(2.286)

_.1. SEATING
-~TPLANE

~

.037 (.940)
.027 (.686)
STANDOFF
WIDTH

~~.016

.020 (.508)
(A06)

All dimensions in inches (bold) and millimeters (parentheses)

8-18

PACKAGE OUTLINES
24-Pin Plastic Dual In-line

NOTES:
Pins are tin-plated alloy 42
Pins are intended for insertion in hole
rows on .400" (10.16) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameterpin
Package weight 2.5 grams

Iv

.065 (1.651)
1--.045 (1.143)

.165 (4.191)
.155(3.94)

t~

~-----------, .0~~~508)

+=

~~

i

.135 (3.429)
.115 (2.921)---j

.110
(2.794)
.090
(2.286)

h'

~

I

9U

SEATING
PLANE

II

.037 (.940)
.020 (.508)
.027 (.686) --I~.016 (.406)
STANDOFF
WIDTH

28-Pin Plastic Dual In-line

9Y-2

.050 R x .020 DP
(1.27) R x (0.51)
.555 (14.10)± .005(0.13)

NOTES:
Pins are tin - plated kovar, alloy 42 or copper
Pins are intended for insertion in hole
rows on .600" (15.24 centers)
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" (0.508) diameter pin
Package weight 4.0 grams

~miD.f.~~jffi';~28 ~
-i

L.075(1.91)TYP.

.050 ± .005
(1.27 ± .013)

-I Ir-

.020 MIN.

,..."...,,..,,,,-,,,,'1 (0.51)

~ SEATING

=r--:~~~:~~~l
Jl

PiAiifE

.037(0.94)
.027(0.68)

.018(0.46) NOM.

All dimensions in inches (bold) and millimeters (parentheses)

8-19

•

I
I
I
I
I

I
I
I
I
I
I
I

I
I
I
I

I

I
I
I
I

I
I
I
I

I
I
I
I

I
I
I
I
I
I
I
I
I
I

I
I
I

I

I
I
I
I

I
I
I
I
I
I

I
I
I
I

I
I

INTHODUCTION

NUMeR1CALINDEX 01=, DEVICES

SELECTION GUIDES AND CROSS REFERENCE

C;;ENERAlCHARACTERISTICS

RAMs"

PROMs

PRODUCT INFORMAT)ONJDATA'SHEETS

ORDER AND PACKAGE tNFORMATlON .
,

,

v

'.

~.:

.,:

FAIRCHILD FIELD SALES OFFICES,
REPRESENTATIVES AND DISTRIBUTORS

CHAPTER 9

• Fairchild Field Sales Offices,
Representatives and Distributors

Fairchild
Semiconductor

Franchised
Distributors

United States and
Canada

AI.bama

Wyle Distribution Group
9525 Chesapeake
San Diego. California 92123
Tel: 714-565-9171 TWX: 910-335-1590

Hamilton/Avne! Electronics
6700 Interstate 85 Access Road. SUite 1E
Norcross, Georgia 30071

Hallmark Electronics
4900 Bradford Drive
Huntsville, Alabama 35807
Tel' 205-837-8700 TWX: 810-726-2187
Hamllton/Avne! ElectroniCS
4692 Commercial Drive
Huntsville, Alabama 35805
Tel: 205-837-7210
Telex: None - use HAMAVLECB DAL 73-0511
(Regional Hq. in Dallas, Texas)

Arizona
Hamll10n/Avnet Electronics
505 S. Madison Drive
Tempe, Arizona 85281
Tel: 602·275-7851 TWX: 910·951-1535
Kierulff Electronics
4134 East Wood Street
Phoenix, Arizona 85040
Tel: 602-243-4101
Wyle Distribution Group
8155 North 24th Ave
Phoenix, Arizona 85021
Tel: 602·249-2232 TWX: 910-951-4282

California
Avnet Electronics
350 McCormick Avenue
Costa Mesa, California 92626
Tel: 714-754-6111 (Orange Countyl
213-558--2345 ~Los Angelesl
TWX: 910-595-1928
Bell Industries
Electronic Distributor Division
1161 N. Fair Oaks Avenue
Sunnyvale, California 94086
Tel: 408-734-8570 TWX: 910-339-9378
Wyle Distribution Group
3000 Bowers Avenue
Santa Clara, California 95051
Tel: 408-727-2500 TWX: 910-338-0541
Hamilton Electro Sales
3170 Pullman Avenue
Costa Mesa, California 92636
Te1: 714-979-6864
Hamilton Electro Sales
10912 W. Washin9ton Blvd.
Culver City, California 90230
Tel: 213-558-2121 TWX: 910-340-6364
Hamilton/Avnet Electronics
1175 Bordeaux Drive
Sunnyvale, California 94086
Tel: 408-743-3355 TWX: 910-379-6486
Hamilton/Avnet Electronics
4545. Viewridge Avenue
San Diego, California 92123
Tel: 714-571-7527
Telex: HAMAVELEC SDG 69-5415
Anthem Electronics
1020 Stewart Drive
P.O. Box 9085
Sunnyvale, California 94086
Tel: 408-738-1'"
Anthem ElectroniCS, Inc.
4040 Sorrento Valley Blvd.
San Dr.ego, California 92121
Tel: 714-279-5200
Anthem Electronics, Inc.
2661 Dow Avenue
Tustin, California 92680
Tel: 714-730-8000
Wyle Electronics
124 Maryland Street
-el SegundO, California 90245
Tel: 213-322-8100 TWX: 910-348-7111
Wyle Distributor Group
17872 Cowan Avenue
Irvine, California 92714
Tel: 714-641-1600
Telex: 610-595-1572
"Sertech Laboratories
2120 Main Street Suite 190
Huntington Beach, California 92647
Tel: 714-960-1403

Colorado
Bell Industries
8155 West 48th Avenue
Wheat ridge. Colorado 80033
Tel: 303-424-1985 TWX: 910-938-0393
Arrow Electronics
2121 South Hudson
Denver, Colorado 80222
Tel: 303·758·2100
Wyle Distribution Group
6777 E. 50th Avenue
Commerce City, Colorado 80022
Tel: 303-287-9611 TWX: 910-936-0770
Hamilton/Avnet Electronics
8765 E. Orchard Rd., Suite 708
EngleWOOd. Colorado 80111
Tel: 303-740-1000 TWX: 910-935-0787

Connecticut
Arrow Electronics, Inc
12 Beaumont Road
Wallingford, Connecticut 06492
Tel: 203-265-7741 TWX: 203-265-7741
Hamilton/Avnet Electronics
Commerce Drive, Commerce Park
Danbury. Connecticut 06810
Tel: 203-797-2800
TWX: None - use 710-897-1405
(Regional Hq. in Mt Laurel. N.J.I
Harvey Electronics
112 Main Street
Norwalk, Connecticut 06851
Tel: 203-853-1515
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, Connecticut 06810
Tel: 203-792-3500

Florida
Arrow Electronics
1001 Northwest 62nd Street
Suite 402
Ft. Lauderdale, Florida 33309
Tel: 305-776-7790
Arrow Electronics
115 Palm Bay Road N.W
Suite 10 Bldg. #200
Palm Bay, Florida 32905
Tel: 305-725-1408
Hallmark Electronics
1671 W. McNab Road
Ft. Lauderdale, Florida 33309
Tel: 305-971-9280 TWX; 510-956-3092
Hallmark Electronics
7233 Lake Ellenor Drive
Orlando, Florida 32809
Tel: 305-855-4020 TWX; 810-850-0183
Hamilton/Avnet Electronics
6800 N.w. 20th Avenue
Ft. Lauderdale, Florida 33309
Tel: 305-971-2900 TWX: 510-954-9808
Hamilton/Avnet Electronics
3197 Tech Drive, North
51. Petersburg, Florida 33702
Tel: 813-576-3930
Schweber Electronics
2830 North 28th Terrace
Hollywood, Florida 33020
Tel: 305-927-0511 TWX: 510-954-0304

Georgia
Arrow Electronics
2979 Pacific Drive
Norcross, Georgia 30071
Tel: 404-449-8252
Telex: 810-766-0439

"This distributor carries Fairchild die products only.

9-3

Tel: 404-448-0800
Telex: None - use HAMAVLECB DAL 73-0511
(Regional HQ. In Dallas, Texasl
illinois
Hallmark Electronics, Inc
1177 Industnal Drive
Bensenville, Illinois 60106
Tel: 312-860-3800
Hamilton/Avnet Electronics
3901 N. 25th Avenue
Schiller Park, Illinois 60176
Tel: 312·678·6310 TWX: 910-227-0060
Kierulff Electronics
1536 Landmeier Road
Elk Grove Village, Illinois 60007
Tel: 312-640-0200 TWX: 910-227-3166
Schweber Electronics, Inc.
1275 Brummel Avenue
Elk Grove Village, Illinois 60007
Tel: 312-593-2740 TWX: 910-222-3453
Semiconductor Specialists, Inc.
(mailing address)
O'Hare International Airport
P.O. Box 66125
Chicago, Hlinois 60666
(shipping address)
195 Spangler Avenue
Elmhurst Industrial Park
Elmhurst, illinoiS 60126
Tel: 312-279-1000 TWX: 910-254-0169

Indiana
Graham Electronics Supply, Inc.
133 S. Pennsylvania SI
Indianapolis, Indiana 46204
Tel: 317·634-8486 TWX: 810-341-3481
Pioneer Indiana Electronics, Inc.
6408 Castle Place Drive
Indianapolis, Indiana 46250
Tel: 317-849-7300 TWX: 810-260-1794

Kansas
Hallmark Electronics, Inc.
11870 W. 91st Street
Shawnee Mission. Kansas 66214
Tel: 913-888-4746
Hamilton/Avnel Electronics
9219 Guivira Road
Overland Park, Kansas 66215
Tel: 913-888-8900
Telex: None - use HAMAVLECB DAL 73-0511
(Regional Hq. in Dallas, Texas)

louisiana
Sterling Electronics Corp.
4613 Fairfield
Metairie, Louisiana 70002
Tel: 504-887-7610
Telex: STERLE LEC MRIE 58-328

Maryland
Hallmark ElectroniCS, Inc.
6655 Amberton Drive
Baltimore, Maryland 21227
Tel: 301·796-9300
Hamilton/Avnet Electronics
(mailing address)
Friendship International Airport
P.O. Box 8647
Baltimore, Maryland 21240
(shIpping address)
7235 Standard Drive
Hanover, Maryland 21076
Tel: 301-796-5000 TWX: 710-862-1861
Telex: HAMAVLECA HNVE 87-968
Pioneer Washington Electronics, Inc.
9100 Gaither Road
Gaithersburg, Maryland 20760
Tel: 301-948-0710 TWX: 710-828-9784
Schweber Electronics
9218 Gaither Road
Gaithersburg, Maryland 20760
Tel: 301-840-5900 TWX: 710-828-0536

II

Fairchild
Semiconductor

Franchised
Distributors

United States and
Canada

Massachusetts
Arrow Electronics. Inc
960 Commerce Way
Woburn, Massachusetts 01801
Tel: 617~933-8130 TWX: 710-393-6770

New Jersey

Harvey ElectroniCS
Imaliing addressl
P
Box 1208
Bmghampton. New York 13902
IShlPPlng address'
1911 Vestal Parkway East
Vestal. New York 13850
Tel 607-748-821'

Hallmark Electronics. Inc
Springdale Busmess Center
2091 Springdale Road
Cherry HilL New Jersey 08003

Tel 609-424-0880
Arrow Electronics
85 Wells Avenue
Newlon Centre, Massachusetts 02159
Tel: 617-964-4000

Gerber Electronics
128 Carnegie Row
Norwood, Massachusetts 02026
Tel: 617-329-2400
Hamilton/Avnet Electronics
50 Tower .Office Park
Woburn, Massachusetts 01801
Tel: 617-273-7500 TWX: 710-393-0382
Harvey Electronics
44 Hartwell Avenue
Lexington, Massachusetts 02173
Tel: 617-861-9200 TWX: 710-326-6617
Schweber Electron)cs
25 Wiggins Avenue
Bedford, Massachusetts 01730
Tel: 617-275-5100
**Sertech Laboratories
1 Peabody Street
Salem, Massachusetts 01970
Tel: 617-745-2450
Michigan
Hamilton/Avnet Electronics
32487 Schoolcraft
Livonia, Michigan 48150
Tel: 313-522-4700 TWX: 810-242-8775
Pioneer/Detroit
13485 Stamford
Livonia, Michigan 48150
Tel: 313-525-1800
R-M Electronics
4310 Roger B. Chaffee
Wyoming, Michigan 49508
Tel: 616-531-9300
Schweber Electronics
33540·Schoolcraft
Livonia. Michigan 48150
Tel: 313-525-8100
Arrow Electronics
3921 Varsity Drive
Ann Arbor, Michigan 48104
Tel: 313-971-8220
Minnesota
Arrow Electronics
5230 West 73rd Street
Edina, Minnesota 55435
Tel: 612-830-1800
Hamilton/Avnet Electronics
7449 Cahill Road
Edina, Minnesota 55435
Tel: 612-941-3801
TWX: None- use 910-227-0060
(Regional Hq. in Chicago, III.)
Schweber Electronics
7402 Washington Avenue S.
Eden Prairie, Minnesota 55344
Tel: 612-941-5280
Missouri
Hallmark Electronics, Inc
13789 Rider Trail
Earth City, Missouri 63045
Tel: 314-291-5350
Hamilton/Avnet Electronics
13743 Shoreline Ct., East
Earth City, Missouri 63045
Tel: 314-344-1200 TWX: 910-762-0684

*Minority Distributor
··Tl,iS

Hamilton/Avnet ElectroniCS
10 Industnal Road
Fairfield, New Jersey 07006
Tel: 201-575-3390 TWX: 710-994-5787

Hamllton/Avnet ElectroniCS
#1 Keystone Avenue
Cherry HLII, New Jersey 08003
Tel: 609-424-0100 TWX: 710-940-0262
Schweber Electronics
18 Madison Road
Fairfield, New Jersey 07006
Tel: 201-227-7880 TWX- 710-480-4733
Sterling Electronics
774 Pfeiffer Blvd
Perth Amboy, N.J. 08861
Tel: 201-442-8000 Telex 138-679
Wilshire Electronics
102 Gaither Drive
Mt Laurel, N.J. 08057
Tel: 215-627-1920
Wilshire Electronics
1111 Paulison Avenue
Clifton, N.J. 07015
Tel: 201-365-2600 TWX: 710-989-7052
New Mexico
Bell Industries
11728 Linn Avenue N.E.
Albuquerque, New Mexico 87123
Tel: 505-292-2700 TWX: 910-989-0625
Hamilton/Avnet Electronics
2450 Byalor Drive S.E
Albuquerque, New Mexico 87119
Tel: 505-765-1500
TWX: None - use 910-379-6486
(Regional Hq. in Mt. View, Ca.l

a

Rochester Radio Supply Co Inc
140 W Main Street
fP 0 Box 19711 Rochester, New York 14603
Tel: 716-454-7800

Schweber ElectroniCS
Jericho Turnpike
Westbury, LI. New York 11590
Tel' 516-334-7474 TWX 510-222-3660
Jaco Electronics. Inc
145 Oser Avenue
Hauppauge. LI .. New York 11781
Tel: 516-273-1234 TWX: 510-227-6232
Summit Distributors, Inc
916 Main Street
Buffalo, New York 14202
Tel: 716-884-3450 TWX: 710-522-1692
North Carolina
Arrow Electronics
938 Burke Street
Winston Salem, North Carolina 27102
Tel: 919-725-8711 TWX: 510-922,-4765
Hamiiton/Avnet
2803 Industrial Drive
Raleigh, North Carolina 27609
Tel: 919-829-8030
Hallmark ElectroniCs
1208 Front Street, Bldg. K
Raleigh, North Carolina 27609
Tel: 919-823-4465 TWX: 510-928-1831
Resco
Highway 70 West
Rural Route 8, P.O. 80x 116-8
Raleigh, North Carolina 27612
Tel: 919-781-5700

New York
Arrow Electronics
900 Broadhollow Road
Farmingdale, New York 11735
Tel: 516-694-6800

Pioneer/Carolina Electronics
103 Industrial Drive
Greensboro. North Carolina 27406
Tel: 919-273-4441

Arrow Electronics
20 Qser Avenue
Hauppauge, New York 11787
Tel: 516-231-1000

Ohio
Arrow Electronics
7620 McEwen Road
CenterVille. Ohio 45459
Tel, 513-435-5563

*Cadence Electronics
40-17 Oser Avenue
Hauppauge, New York 11787
Tel: 516-231-6722
Arrow Electronics
P.O. Box 370
7705 Maltlage Drive
liverpool, New York 13088
Tel: 315-652-1000
TWX: 710-545-0230
Components Plus, Inc.
40 Oser Avenue
Hauppauge, L.I., New York 11787
Tel: 516-231-9200 TWX: 510-227-9869
Hamilton/Avnet Electronics
167 Clay Road
Rochester, New York 14623
Tel: 716-442-7820
TWX: None- use 710-332-1201
(Regional Hq. in Burlington, MaJ
Hamilton/Avnet Electronics
16 Corporate Circle
E. Syracuse, New York 13057
Tel: 315-437-2642 TWX: 710-541-0959
Hamilton/Avnet Electronics
5 Hub Drive
Melville, New York 11746
Tel: 516-454-6000 TWX: 510-224-6166

distributor carries Fairchild die products only.

9-4

Hamilton/Avnet Electronics
4588 Emery Industrial Parkway
Cleveland, Ohio 44128
Tel: 216-831-3500
TWX: None - use 910-227-00M
(Regional Hq, in Chicago, IIi.)
Hamilton/Avnet Electronics
954 Senate Drive
Dayton, Ohio 45459
Tel: 513-433-0610 TWX: 810-450-2531
Pioneer/Cleveland
4800 E. 131st Street
Cleveland, Ohio 44105
Tel: 216-587-3600
Pioneer/Dayton
1900 Troy Street
Dayton. Ohio 45404
Tel' 513-236-9900 TWX: 810-459-1622
Schweber ElectroniCS
23880 Commerce Park Road
Beachwood, Ohio 44122
Tel: 216-464-2970 TWX: 810-427-9441
Arrow Electronics
6238 Cochran Road
Solon, Ohio 44139
Tel: 216-248-3990 TWX: 810-427-9409

Fairchild
Semiconductor

Franchised
Distributors

United States and
Canada

Ohio
Arrow Electronics
(mailing addressl

Hamllton/Avnet ElectroniCS
3939 Ann Arbor
Houston, Texas 77042
Tel. 713-780-1771
Telex' HAMAVLECB HOU 76-2589

Cam Gard Supply ltd.
15 Mount Royal Blvd
Moncton, New Brunswick, E1C 8N6, Canada
Tel 506-855-2200

P.O. Box 37826
CincinnatI. Ohio 45222
(shipping addressl

10 Knolicrest DrIVe
Reading, Ohio 45237
Tel: 513-761-5432 TWX 810-461-2670
Hallmark Electronics
6969 Worthington-Galena Road
Worthington. uhlo 43085
Oklahoma
Hallmark ElectroniCS
5460 S. 103rd East Avenue
Tulsa, Oklahoma 74145
Tel: 918-835-8458 TWX: 910-845-2290
Radio Inc. Industnal ElectronIcs
1000 S. MaIn
Tulsa, Oklahoma 74119
Tel: 918-587-9123
Pennsylvania
Pioneer/Delaware Valley Electronics
261 Gibraltar Road
Horsham, Pennsylvania 19044
Tel: 215-674-4000 TWX: 510-665-6778
Pioneer Electronics, Inc.
560 Alpha Drive
Pittsburgh, Pennsylvania 15238
Tel: 412-782-2300 TWX: 710-795-3122
Schweber Electronics
101 Rock Road
Horsham, Pennsylvania 19044
Tel: 215-441-0600
Arrow Electronics
4297 Greensburgh Pike
Suite 3114
Pittsburgh, Pennsylvania 15221
Tel; 412-351-4000
South Carolina
Oixie Electronics, Inc.
P.O. Box 408 (Zip Code 29202)
1900 Barnwell Street
Columbia, South Carolina 29201
Tel: 803-779-5332

Tex ..
Allied Electronics
401 E. 8th Street
Fort Worth, Texas 76102
Tel: 817-336-5401
Arrow Electronics
13715 Gamma Road
Dallas, Texas 75234
Tel: 2~4-386-7500 TWX: 910-860-5377
Hallmark Electronics Corp.
10109 McKalla Place Suite F
Austin, Texas 78758
Tel: 512-837-2814
Hallmark Electronics
11333 Pagemill Drive
Dallas, Texas 75243
Tel: 214-234-7300 TWX; 910-867-4721
Hallmark Electronics, Inc.
8000 West glen
Houston, Texas 77063
Tel: 713-781-6100
Hamilton/Avnet ElectronICS
10508A Boyer Boulevard
Austin, Texas 78758
Tel: 512-837-8911
Hamilton/Avnet Electronics
4445 Sigma Road
Dallas, Texas 75240
Tel: 214-661-8661
Telex: HAMAVLECB DAL 73-0511

Schweber Electronics, Inc
14177 Proton Road
Dallas, Texas 75240
Tel: 214-661-5010 TWX: 910-860-5493
Schweber ElectrOniCS, Inc.
7420 HarWln Dnve
Houston, Texas 77036
Tel: 713-784-3600 TWX. 910-8S'-1109
Slerllng Electronics
4201 Southwest Freeway
Houston, Texas 77027
Tel: 713-627-9800 TWX: 901-881-5042
Telex: STELECO HOUA 77-5299
Utah
Century Electronics
3639 W 2150 South
Sail lake City. Utah 84120
Tel 801-972-6969 TWX. 910-925-5686
Hamilton/Avnet ElectronICS
1585 W. 2100 South
Salt lake City, Utah 84119
Tel: 801-972-2800
TWX: None- use 910-379-6486
(Regional Hq. in Mt. View, CaJ
Washington
Hamilton/Avnet Electronics
14212 N.E. 21st Street
Bellevue, WashIngton 98005
Tel: 206-746-8750 TWX: 910-443-2449
Wyle Distribution Group
1750 132nd Avenue N.E.
Bellevue, WaShington 98005
Tel: 206-453-8300 TWX: 910-444-1379
Radar ElectronIc Co., Inc.
168 Western Avenue W.
Seattle, Washington 98119
Tel: 206-282-2511 TWX: 910-444-2052
Wisconsin
Hamilton/Avnet ElectroniCs
2975 Moorland Road
New Berlin, Wisconsin 53151
Tel: 414-784-4510 TWX: 910-262-1182
Marsh Electronics, Inc
1563 South 100th Street
Milwaukee, Wisconsin 53214
Tel: 414-475-6000 TWX: 910-262-3321
Canada
Cam Gard Supply ltd.
640 42nd Avenue S.E.
Calgary, Alberta, T2G lY6, Canada
Tel: 403-287-0520 Telex: 03-822811
Cam Gard Supply Ltd.
16236 116th Avenue
Edmonton, Alberta T5M 3V4, Canada
Tel: 403-453-6691 Telex: 03-72960
Cam Gard Supply ltd.
4910 52nd Street
Red Deer, Alberta, T4N 2C8, Canada
Tel: 403-346-2088
Cam Gard Supply Ltd
825 Notre Dame Drive
Kamloops, British Columbia, V2C 5N8, Canada
Tel: 604-372-3338
Cam Gard Supply Ltd.
1777 Ellice Avenue
Winnepeg, Manitoba, R3H OW5, Canada
Tel: 204-786-8401 Telex: 07-57622
Cam Gard Supply Ltd.
Rookwood Avenue
Fredericton, New Brunswick, E3B 4Y9, Canada
Tel: 506-455-8891

9-5

Cam Gard Supply ltd
3065 Roble Street
Halifax, Nova Scotia, B3K 4P6. Canada
Tel: 902-454-8581 Telex: 01-921528
Cam Gard Supply ltd
1303 Scarth Street
Regina, Saskatchewan, S4R 2E7, Canada
Tel: 306-525-1317 Telex: 07-12667
Cam Gard Supply Ltd.
1501 Ontario Avenue
Saskatoon, Saskatchewan, S7K 1S7, Canada
Tel: 306~652~6424 Telex: 07-42825
Electro SonIc Industrial Sales
(Torontoi ltd
1100 Gordon Baker Rd.
Willowdale, Ontario, M2H 3B3, Canada
Tel: 416-494-1666
Telex: ESSCO TOR 06-22030
Future Electronics Inc.
Baxter Center
1050 Baxter Road
Ottawa, Ontario, K2C 3P2, Canada
Tel: 613-820-9471
Future Electronics Inc.
4800 Ouffenn Street
Downsview, Ontano, M3H 5S8, Canada
Tel: 416-663-5563
Future Electronics Corporation
5647 Ferrier Street
Montreal, Quebec, H4P 2K5, Canada
Tel: 514-731-7441
Hamilton/Avnet International
(CanadaJ Ltd.
3688 Nashua Drive, Units 6 & H
Mississauga, Ontario, L4V 1M5, Canada
Tel: 416-677-7432 TWX: 610-492-8867
Hamllton/Avnet International
(Canada) ltd.
1735 Courtwood Crescent
Ottawa, Ontario, K1 Z 5l9, Canada
Tel: 613-226-1700
Hamilton/Avnet International
(Canada) ltd
2670 Sabourin Street
SI. Laurent, Quebec, H4S 1M2, Canada
Tel: 514-331-6443 TWX: 610-421-3731
A.A.E. Industrial ElectroniCS, Ltd.
3455 Gardner Court
Burnaby, British Columbia Z5G 4J7
Tel: 604-291-8866 TWX: 610-929-3065
Telex: RAE-VCR 04-54550
Semad Electronics Ltd
620 Meloche Avenue
Dorval, Quebec, H9P 2P4, Canada
Tel: 604-2998-866 TWX: 610-422-3048
Semad Electronics ltd.
105 Brisbane Avenue
Downsview, Ontario, M3J 2K6, Canada
Tel: 416-663-5670 TWX: 610-492-2510
Semad Electronics ltd.
1485 Laperriere Avenue
Ottawa, Ontario, K1Z 7$8, Canada
Tel: 613-722-6571 TWX: 610-562-8966

II

Fairchild
Semiconductor

Sales
Representatives

United States and
Canada

Alabama

Texa.

Tel: 205-533-3509

Nevada
Magna Sales
4560 Wagon Wheel Road
Carson City, Nevada 89701
Tel: 702-883-1471

California
Celtee Company
18009 Sky Park Circle Suite B
Irvine, California 92705
Tel: 714-557-5021 TWX: 910-595-2512

New Jersey
BGR Associates
3001 Greentree Executive Campus
Marlton, New Jersey 08053
Tel: 609-428-2440

Technical Marketing, Inc.
9027 North Gate Blvd.
Suite 140
Austin, Texas 78758

Celtee Company
7867 Convoy Court, Suite 312
San Diego, California 92111
Tel: 714-279-7961 TWX: 910-335-1512

Lorac Sales, Inc.
1200 Route 23 North
Butler, New Jersey 07405
Tel: 201-492-1050 TWX: 710-988-5846

Technical Marketing
6430 Hillcroft, Suite 104
Houston, Texas 77036
Tel: 713-777-9228

Magna Sales, Inc.
3333 Bowers Avenue
Suite 295
Santa Clara, California 95051
Tel: 408-727-8753 TWX: 910-338-0241

New York
Lorac Sales, Inc.
550 Old Country Road, Room 410
Hicksville, New York 11801
Tel: 516-681-8746 TWX: 510-224-6480

Utah
Simpson Associates, Inc.
7324 South 1300 East, Suite 350
Midvale, Utah 84047
Tel: 801-566-3691
TWX: 910-925-4031

Colorado
Simpson Associates, Inc
2552 Ridge Road
Littleton, Colorado 80120
Tel: 303-794-8381 TWX: 910-935-0719

Tri-Tech Electronics, Inc.
3215 E. Main Street
Endwell, New York 13760
Tel: 607-754-1094 TWX: 510-252-0891

Cartwright & Bean, Inc.
2400 Bob Wallace Ave., Suite 201
Huntsville, Alabama 35805

Connecticut
Phoenix Sales Company
389 Main Street
Ridgefield, Connecticut 06877
Tel: 203-438-9644 TWX: 710-467-0662
Florida
Lectromech, Inc.
399 Whooping Loop
Altamonte Springs, Florida 32701
Tel: 305-831-1577 TWX: 510-959-6063

Lectromech, Inc.
2280 U.S. Highway 19 North
Suite 155, Building K
Clearwater, Florida 33515
Tel: 813-797-1212
TWX: 510-959-6030
Lectromech, Inc.
17 East Hibiscus Blvd.
Suite A-2
Melbourne, Florida 32901
Tel: 305-725-1950
TWX: 510-959-6063
Lectromech, Inc.
1350 S. Powerline Road, Suite 104
Pompano Beach, Florida 33060
Tel: 305-974-6780 TWX: 510-954-9793
Georgia
Cartwright & Bean, Inc.
P.O. Box 528461Zip Code 303551
319S Cain's Hill Place, NW.
Attanta, Georgia 30305
Tel: 404-233-2939 TWX: 810-751-3220
illinois
Micro Sales, Inc.
2258-B Landmeir Road
Elk Grove Village, Illinois 60007
Tel: 312-956-1000 TWX: 910-222-1833
Maryland
Delta III Associates
1000 Century Plaza Suite 224
Columbia, Maryland 21044
Tel: 301-730-4700 TWX: 710-826-9654
Massachusetts
Spectrum Associates, Inc.
109 Highland Avenue
Needham, Massachusetts 02192
Tel: 617-444-8600 TWX: 710-325-6665
Minnesota
PSI Company
5315 W. 74th Street
Edina, Minnesota 55435
Tel: 612-835-1777 TWX: 910-576-3483
MiSSissippi
Cartwright & Bean, Inc.
P.O. Box 16728
5150 Keele Street
Jackson, Mississippi 39206
Tel: 601-981-1368
TWX: 810-751~3220

Tri-Tech Electronics, Inc.
590 Perinton Hills Office Park
Fairport, New York 14450
Tel: 716-223-5720
TWX, 510-253-6356
Tri-Tech Electronics, Inc.
6836 E. Genesee Street
Fayetteville, New York 13066
Tel: 315-446-2881 TWX: 710-541-0604
Tri-Tech Electronics, Inc.
19 Davis Avenue
Poughkeepsie, New York 12603
Tel: 914-473-3880
TWX: 510-253-6356
North Carolina
Cartwright & Bean, Inc.
1165 Commercial Ave.
Charlotte, North Carolina 28205
Tel: 704-377-5673

Cartwright & Bean, Inc.
P.O. Box 18465
3948 Browning Place
Raleigh, North Carolina 27619
Tel: 919-781-6560
Ohio
The Lyons Corporation
4812 Frederick Road, Suite 101
Dayton, Ohio 45414
Tel: 513-278-0714
TWX: 810-459-1803

The Lyons Corporation
6151 Wilson Mills Road, Suite 101
Highland Heights, Ohio 44143
Tel: 216-461-8288
TWX, 810-459-1803
Oklahoma
Technical Marketing
9717 E. 42nd Street, Suite 221
Tulsa, Oklahoma 74145
Tel: 918-622-5984
Oregon
Magna Sales, Inc.
8285 S.w. Nimbus Ave., Suite 138
Beaverton, Oregon 97005
Tel: 503-641-7045
TWX: 910-467-8742
Tennessee
Cartwright & Bean, Inc.
P.O. Box 4760
560 S. Cooper Street
Memphis, Tennessee 38104
Tel: 901-276-4442
TWX: 810-751-3220

Cartwright & Bean, Inc.
8705 Unicorn Drive
Suite B120
Knoxville, Tennessee 37923
Tel: 615-693-7450
TWX: 810-751-3220

9-6

Technical Marketing
3320 Wiley Post Road
Carrollton, Texas 75006
Tel: 214-387-3601 TWX: 910-860-5158

Tel: 512-·835-0064

Washington
Magna Sales, Inc.
Benaroya Business Park
Building 3, Suite 115
300-120th Avenue, N.E.
Bellevue, Washington 98004
Tel: 206-455-3190
Wisconsin
Larsen Associates
10855 West Potter Road
Wauwatosa, Wisconsin 53226
Tel: 414-258-0529 TWX: 910-262-3160
Canada
R.N. Longman Sales, Inc. (L.$.1.l
1715 Meyerside Drive
Suite 1
Mississauga, Ontario, L5T 1C5 Canada
Tel: 416-677-8100 TWX: 610-492-8976

R.N. Longman Sales, Inc. (L.S.U
16891 Hymus Blvd.
Kirkland, Quebec
H9H 3L4 Canada
Tel: 514-694-3911
TWX: 610-422-3028

Fairchild
Semiconductor
AI,bam,
Huntsville Office
500 Wynn Drive
Suite 511
Huntsville. Alabama 35805
Tel: 205-837-8960

Arlzon.
Phoenix Office
4414 N. 19th Avenue. Suite G
Phoenix 85015
Tel: 602-264-4948 TWX: 910-951-1544

e,lIfornla
Los Angeles Office'

Crocker Bank Bldg.
15760 Ventura Blvd., Suite 1027
Encino 91436

United States and
Canada

Sales
Offices
Minnesota
Minneapolis Office'
4570 West 77th Street Room 356
Minneapolis 55435
Tel 612-835-3322 TWX 910-576-2944

New Jersey
Wayne Office'
580 Valley Road, Suite 1
Wayne 07490
Tel: 201-696-7070 TWX: 710-988-5046
New Mexico
Alburquerque Office
North Building
2900 louisiana N.E. South G2
Alburquerque 87110
Tel: 505-884-5601 TWX: 910-379-6435

Tel: 213-990-9800 TWX: 910-495-1776
Santa Ana Office'
1570 Brookhollow Drive
Suite 206
Santa Ana 92705
Tel: 714-557-7350 TWX: 910-595-1109
Santa Clara Office'
3333 Bowers Avenue, Suite 299
Santa Clara 95051
Tel: 408-987-9530 TWX: 910-338-0241
Florida
Ft. Lauderdale Office
Executive Plaza, Suite 300-8
1001 Northwest 62nd Street
Ft. Lauderdale 33309
Tel: 305-771-0320 TWX: 510-955-4098
Orlando Oftice'
Crane's Roost Office Park
399 Whooping Loop
Altamonte Springs 32701
Tel: 305-834-7000 TWX: 810-850-0152
illinois
Chicago Office
60 Gould Center
The East Tower, Suite 710
Rolling Meadows 60008
Tel: 312-640-1000

Indiana
Ft. Wayne Office
2118 Inwood Drive, Suite 111
Ft. Wayne 46815
Tel: 219-483-6453 TWX: 810-332-1507
Indianapolis Office
7202 N. Shadeland Castle Point
Room 205
Indianapolis 46250
Tel: 317-849-5412 TWX: 810-260-1793

Kans.
Kansas City Office
860Q West 110th Street, Suite 209
Overland Park 66210
Tel: 913-649-3974

Maryland
Columbia Office"
1000 Century Plaza, Suite 225
Columbia 21044
Tel: 301-730-1510 TWX: 710-826-9654
M.sachuaetts
80ston Office'
888 Worcester Street
Wellesley Hills 02181
Tel: 617-237·3400 TWX: 710-348-0424

Michigan

New York
Melville Office
275 8roadhollow Road, Suite 219
Melville 11747
Tel: 516-293-2900 TWX: 510-224-6480
Poughkeepsie Office
19 Davis Avenue
Poughkeepsie 12603
Tel: 914-473-5730 TWX: 510-248-0030
Fairport Office
260 Perinton Hills Office Park
F ai rport 14450
Tel: 716-223-7700
North Carolina
Raleigh Office
3301 Execullve Dnve. SUite 204
Raleigh 27609
Tel: 919-876-0096
Ohio
Dayton Office
4812 Frederick Road, Suite 105
Dayton 45414
Tel: 513-278-8278 TWX: 810-459-1803
Oregon
Fairchild Semiconductor
8285 S.W. Nimbus Avenue, Suite 138
Beaverton, Oregon 97005
Tel: 503-641-7871 TWX: 910-467-7842
Pennsylvania
Philadelphia Office2500 Office Center
2500 Maryland Road
Willow Grove 19090
Tel: 215-657-2711

Texas
Austin Office
9027 North Gate Blvd .. Suite 124
Austin 78758
Tel: 512-837-8931
Dallas Office
13771 N. Central Expressway, Suite 809
Dallas 75243 '
Tel: 214-234-3391 TWX: 910-867-4757
Houston Otfice
6430 Hillcroft, Suite 102
Houston 77081
Tel: 713-771-3547 TWX: 910-881-8278
Canada
Toronto Regional Office
Fairchild Semiconductor
1590 Matheson Blvd., Unit 26
Mississauga, Ontario L4W 1J1, Canada
Tel: 416-625-7070 TWX: 610-492-4311

Detroit Office·
21999 Farmington Road
Farmington Hills 48024
Tel: 313·478-7400 TWX: 810-242-2973

·Field Application Engineer

9-7

II

International

Fairchild
Semiconductor

Sales
Offices

Australia
FaIrchild Australia Ply Ltd
Branch Office Third Floor
F.A.I. Insurance Building
619 PaCific Highway
5t. Leonards 2065
New South Wales, Australia

Mexico
Fairchild Mexlcana S A
Blvd. Adalafo"Lopez Maleos No 163
MexIco 19, D.F.
Tel. 905-563-5411 Telex 017-71-038

Tel: W2l·439-5911
Telex: AA20053
Austria and eastern Europe
Fairchild ElectrOniCS
A-lOla Wi en
SChwedenplalz 2
Tel: 0222635821 Telex: 75096
Benelux
Fairchild Semiconductor
Paradijslaan 39
Eindhoven, Holland
Tel: 00-31-40-446909 Telex: 00-1451024

Brazil
Fairchild Semicondutores Uda
Caixa Postal 30407
Rua Alagoas, 663
01242 Sao Paulo, Brazil
Tel: 66-9092 Telex: 011-23831
Cable: FAIRLEC

Franc.
Fairchild Camera & Instrument S.A.
121, Avenue d'italie
75013 Paris, France
Tel: 331-584-55 66
Telex: 0042 200614 or 260937
Germany
Fairchild Camera and Instrument IDeutschland}
Daimlerstr 15
8046 Garching Hochbruck
Munich, Germany
Tel: (089) 320031 Telex: 52 4831 fair d

Fairchild Camera and instrument
IDeutschland) GmBH
Oeltzenstrasse 15
3000 Hannover
W. Germany
Tel: 0511 17844 Telex: 09 22922

Scandinavia
Fairchild Semiconductor AS
Svartengsgatan 6
5-' 1620 Stockholm
Sweden
Tel. 8-449255 Telex 17759
Singapore
Fairchild Semiconductor Ply Ltd.
No. , 1, Lorang 3
Toa Payoh
SIngapore 12
Tel: 531-066 Telex: FAIRSIN-RS 21376
Taiwan
Fairchild SemIconductor (Taiwan) Ltd.
HSletsu Bldg., Room 502
47 Chung Shan North Road
Sec. 3 Taipei, Taiwan
Tel: 573205 thru 573207
United Kingdom
Fairchild Camera and Instrument (UK) Ltd
Semiconductor Division
230 High Street
Potters Bar
Hertfordshlre EN6 5BU
England
Tel: 0707 51111 Telex: 262835

FairChild SemIconductor Ltd.
17 Victoria Street
CraigshiU
Livingston
West Lothian, Scotland - EHS4 SBG
Tel: Livingston 0506 32891 Telex: 72629
GEC-Fairchlld Ltd
Chester High Road
Neston
South Wlrral L64 3UE
Cheshire. England
Tel 051-336-3975 Telex. 629701

Fairchild Camera and Instrument (Deutschland)
Postrstrasse 37
7251 Leonberg
W. Germany
Tel: 07152 41026 Telex: 07 245711

Hong Kong
Fairchild Semiconductor (HK) Ltd.
135 Hoi Bun Road
Kwun Tong
Kowloon, Hong Kong
Tel: K-890271 Telex: HKG-531
Italy
Fairchild Semiconduttori, S.P.A.
Via Flamenia Vecchia 653
00191 Roma, Italy
Tel: 06 327 4006 Telex: 63046 (FAIR ROM)

Fairchild Semlconduttori S.P.A.
Via Rosellini, 12
20124 Milano, Italy
Tel: 02 6 88 74 51 Telex: 36522
Japan
Fairchild Japan Corporation
Pola Bldg.
1-15-21, Shibuya
Shibuya-Ku, Tokyo 150
Japan
Tel: 03 400 8351 Telex: 242173

Fairchild Japan Corporation
Yotsubashi Chuo Bldg.
1-4-26, Shinmachi,
Nishi-Ku, Osaka 550, Japan
Tel: 06-541-6138/9

Kor.a
Fairchild Semikor Ltd.
K2 219-6 Gari Bong Dong
Young Dung Po-Ku
Seoul 150-06, Korea
Tel: 85-0067 Telex: FAIRKOR 22705
(mailing address)
Central P.O. Box 2806

9-8

~AIRCHIL.C

Fairchild cannet assume responsibility for use of any circuitry described other than circuitry
bodied in a Fairchild product.
Manufactured under one or the following U.S. Patents: 2981877 , 3015048 , 3064167 , 3108359, 'l 17260; other patents pending .
No other circuit patent licenses are implied .
Fairchild reserves the right to make changes In the circu;try or specifications at any time without notice.
Printed in USA / 292-12-0001-048/ 1SM Aprtl 1979



---

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