1979_Intel_Component_Data_Catalog 1979 Intel Component Data Catalog
User Manual: 1979_Intel_Component_Data_Catalog
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Intel was organized in 1968 to utilize the rapidly expanding technology of Integrated Electronics. During its 10-year
history, Intel has become the world's largest supplier of MOS circuits, and is in the top five of the world's producers of
all semiconductor devices.
This Component Data Catalog provides complete specifications on most of Intel standard memory, microprocessor,
peripheral and telecommunication components. Industrial grade products are detailed in Sec·
tion 13, military products in Section 14. Margin tabs provide quick guides to major
product categories; indexes located in Section 1 and at the beginning of
each section allow location of specific circuit types. Ordering,
packaging, product flow information and available literature
may be found in Section 2.
The following are trademarks of Intel Corporation
and may be used only to describe Intel products: Intel, ICE, INSITE, Intellec, iSBC,
Library Manager, MCS, Megachassis,
MICROMAP, MULTIBUS, PROMPT,
RM, UPI, "Scope, PROMWARE,
iCS and the combination of
MCS, RMX, ICE, iSBC or
iCS with a numerical
suffix.
intel®
Component Data Catalog
1979
©Intel Corporation 1976, 1977, 1978, 1979
Intel Corporation
3065 Bowers Avenue' Santa Clara CA 95051
Telephone: (408) 987-8080
TWX: 910-338-0026' Telex: 34-6372
intel®
Component
Data
Catalog
1979
Numerical and
Functional Indexes
1
General Information
2
Random Access
Memory
3
Read Only Memory
4
Memory Support
5
Telecom
6
MCS-4/40™
Microprocessors
7
MCS-48™
Microcomputers
8
MCS-SO/S5™
Microprocessors
9
MCS-86™
Microprocessor
10
Microprocessor
Peripherals
11
Microcomputer
Development Systems
12
Industrial Grade
Products
Military Products
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIEO IN AN INTEL PftOOUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIEO.
131
141
I
I
I
I
I
I
Numerical and
Functionallndexes 1
FUNCTIONAL INDEX
3207A-l
3222
3232
GENERAL INFORMATION
Table of Contents
Ordering Information
Packaging Information
Standard Product Flow
Intel Technical library
Sales Offices
Distributors
2-2
2-3
2-4
2-12
2-14
2-17
2-19
3242
3245
3404
3101/3101A
5101 Family
256 x 4-8it Static RAM
3-8
3-12
3-20
3-28
3-33
3-45
3-49
3-54
High Speed lK x I-Bit Static RAM
3-58
High Speed 1K x 1-8it Static RAM
16,384 x 1-8it Dynamic RAM
16,384 x I-Bit Dynamic RAM
16,384 x 1-8it Dynamic RAM
4096 x I-Bit Static RAM
1024 x 4-8it Static RAM
4096 x I-Bit Static RAM
High Speed 4096 x I-Bit Static RAM
1024 x 4-Bit Static RAM
16 x 4-Blt High Speed RAM
256 x 4-Bit Static CMOS RAM
2910
2911
2912
3-2
3-4
1K x I-Bit Static RAM
4096 x I-Bit Dynamic RAM
4096 x 1-8it Dyanmic RAM
4096-Bit Dynamic RAM
8,912 x I-Bit Dynamic RAM
256 x 4-Bit Static RAM
256 x 4-8it Static RAM
1024 x 4-8it Static RAM
4040
4004
4003
4265
4269
4201A
4289
4002
4001
3-63
3-64
3-76
3-88
3-89
3-95
3-99
3-105
3-106
3-107
3-111
4308
1 of 8 Binary Decoder
Quad Bipolar to MOS Level Shifter and Driver
6-3
6-15
6-26
Single Chip 4-8it P-Channel Microprocessor
Single Chip 4-8it P-Channel Microprocessor
10-Bit Shift Register 10utput Expander
Programmable General Purpose 1/0 Device
Programmable Keyboard Display Device
Clock Generator
Standard Memory Interface
320-8it RAM and 4-Bit Output Port
256 x 8 Mask Programmable ROM and 4-Bit
1/0 Port
1024 x 8 Mask Programmable ROM and
4-Bit 1/0 Ports
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-13
MCS-4STM MICROCOMPUTERS
SINGLE COMPONENT 8-BIT MICROCOMPUTERS
8021
Single Component 8-Blt Microcomputer
8022
Single Component 8-8it Microcomputer
with AID
8048/86481
8748/8035
8049/80391
8039-6
INPUT 10UTPUT
8243
4-2
4-4
4-5
4-9
4-12
4-15
4-16
4-17
4-20
4-23
4-28
4-31
8-4
8-10
Single Component 8-8it Microcomputer
8-22
Single Component 8-8it Microcomputer
8-31
MCS-48™ Input/Output Expander
8-36
MCS-SO!S5™ MICROPROCESSORS
Recommended Products for New 8085A Applications
8-Bit Microprocessor
8080Al8080A-l I
8080A-2
8-8it N-Channel Microprocessor
8224
Clock Generator and Driver for 808DA CPU
8801
Clock Generator Crystal for 8224/8080A
8228/8238
System Controller and Bus Driver for
8080A CPU
8205
High Speed lout of 8 Binary Decoder
8212
8-8it Input/Output Port
Priority Interrupt Control Unit
8214
821618226
4-Bit Parallel Bidirectional Bus Driver
8085A18085A-2
Single Chip 8-Bit N-Channel
Microprocessors
8008/8008-1
4-36
4-39
4-42
4-45
4-48
8155/81561
8155-2/8156-2
MEMORY SUPPORT
SELECTOR GUIDE
3205
3207A
PCM CODEC - '" Law
PCM CODEC - A Law
PCM line Filters
MCS-4!4oTM MICROPROCESSOR
PROGRAMMABLE READ ONLY MEMORIES!
READ ONLY MEMORIES
SELECTOR GUIDE
BIPOLAR CROSS REFERENCE
1702A
2K (256 x 8) UV Erasable PROM
1702ALI 1702AL-2 2K (256 x 8) UV Erasable Low Power PROM
2316E
16K (2K x 8) ROM
2332A
32K (4K x 8) ROM
2364A
64K (8K x 8) 8it ROM
2608
8K (1 K x 8) Factory Programmable PROM
2708/8708
8K and 4K UV Erasable PROM
2716
16K (2K x 8) UV Erasable PROM
2732
32K (4K x 8) UV Erasable PROM
2758
8K (1 K x 8) UV Erasable Low Power PROM
3604A13624A
Family
4K (512 x 8) High-Speed PROM
3605A/3625A
4K (IK x 4) PROM
3628
8K (IK x 8) Bipolar PROM
3636
16K (2K x 8) Bipolar PROM
PROM AND ROM PROGRAMMING INSTRUCTIONS
5-23
5-27
5-3
5-19
TELCoM
RANDOM ACCESS MEMORIES
SELECTOR GUIDE
21 01A181 0IA-4'
21 02A/21 02ALI
8102A-4'
2104A Family
2104A Family
2107C Family
2109 Family
2111A/8111A-4'
2112A
2114
2115A/2125A
Family
2115H, 2125H
Family
2117 Family
2117-5
2118 Family
2141
2142
2147
2147H
2148
5-11
5-13
Quad Bipolar to MOS Level Shifter and Driver
4K Dynamic RAM Refresh Controller
4K Dynamic RAM Address Multiplexer and
Refresh Counter
16K Dynamic RAM Address Multiplexer and
Refresh Counter
Quad TTL to MOS Driver to 4K RAMs
High Speed 6-Bit Latch
5-2
5-3
5-7
8185/8185-2
8218/8219
*For specIfIcations contacllntel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
1-2
2048-Bit Static MOS RAM with 1/0 Ports
and Timer
1024 x 8-Bit Static RAM for MCS-85
Bipolar Microcomputer Bus Controllers for
MCS-80 and MCS-85
9-4
9-5
9-11
9-19
9-23
9-25
9-29
9-35
9-45
9-49
9-54
9-70
9-77
9-81
FUNCTIONAL INDEX
8257/8257 -5
8259A
8355/8355-2
8755A
Programmable DMA Controller
Programmable Interrupt Controller
16,384-Bit ROM with 1/0
16,384-Bit EPROM with 1/0
9-92
9-109
9-127
9-132
SDK-86 MCS-86 System Design Kit
SDK-C86 MCS-86 System Design Kit Software and Cable Interface
to Intellec® Development System
Insite User's Program Library
10-4
10-23
10-27
10-33
10-37
I'Scope 820 Microprocessor System Console
I'Scope Probe 8080A
I'Scope Probe 8085
12-103
12-103
12-110
MICROCOMPUTER TRAINING PROGRAMS
12-112
MCS-86 MICROPROCESSOR
8086/8086-4
8282/8283
8284
8286/8287
8288
16-Bit HMOS Microprocessor
Octal Latch
Clock Generator and Drive for 8086 CPU
Octal Bus Transceiver
Bus Controller for the 8086 CPU
8202
8251A
8253/8253-5
8255A/8255A-5
8271
8273
8275
8278
8279/8279-5
8291
8292
8294
8295
Universal Peripheral Interface 8-Bit
Microcomputer
Dynamic RAM Controller
Programmable Communication Interface
Programmable Intrerval Timer
Programmable Peripheral Interface
Programmable Floppy Disk Controller
Programmable HDLC/SDLC Protocol
Controller
Programmable CRT Controller
Programmable Keyboard Interface
Programmable Keyboard/Display Interface
GPIB Talker/Listener
GPIB Controller
Data Encryption Unit
Dot Matrix Printer Controller
INDUSTRIAL GRADE PRODUCTS
12114
12708/18708
12716
18048/18648/
18748/18035
18155/18156
11-3
11-14
11-24
11-32
11-43
11-64
18212
18216/8226
18243
18251
18255A
18259
18279
18355
18755A-8
11-93
11-118
11-142
11-152
11-164
11-188
11-190
11-201
MICROCOMPUTER DEVELOPMENT SYSTEMS
1024 x 4-81t Static RAM
8K UV Erasable PROM
16K 12K x 8) UV Erasable PROM
13-3
13-4
13-5
Single Component 8-Bit Microcomputer
2048-Bit Static MOS RAM With I/O Ports
and Timer
8-Bit Input/Output Port
4-Bit Parallel Bidirectional Bus Driver
MCS-48 Input/Output Expander
Programmable Communication Interface
Programmable Peripheral Interface
Programmable Interrupt Controller
Programmable Keyboard/Display Interface
16,384-8it ROM With I/O
16,384-8it EPROM With I/O
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
MILITARY PRODUCTS
MICROCOMPUTER DEVELOPMENT SYSTEMS
Model 210 Intellec® Series II Microcomputer Development System
Model 220 Intellec® Series II Microcomputer Development System
Model 230 Intellec® Series II Microcomputer Development System
Expansion Chassis Intellec® Series II Microcomputer
Development System
Model 770 Printer Intellec® Series II Microcomputer
Development System
Intellec Printer
MCS-48 Diskette-Based Software Support Package
PL/M-80 High Level Programming Language Intellec®
Resident Compiler
MDS-311 8086 Software Development Package
FORTRAN-80 8080/8085 ANS FORTRAN 77 Intellec
Resident Compiler
Basic-80 Extended ANS 1978 Basic Intellec® Resident Interpreter
Intellec® Single/Double Density Flexible Disk System
ISIS-II Diskette Operating System Microcomputer
Development System
Intellec Prompt 48 MCS-48 Microcomputer Design Aid
ICE-49 MCS-48 In-Circuit Emulator
ICE-80 8080 In-Circuit Emulator
ICE-85 MCS-85 In-Circuit Emulator
ICE-86 8086 In-Circuit Emulator
EMI 8021 Emulation Board
EM2 8022 Emulation Board
UPP-l03 Universal PROM Programmer
SDK-85 MCS-85 System Design Kit
12-97
12-99
TEST AND INSTRUMENTATION SYSTEMS
MICROPROCESSOR PERIPHERALS
8041A/8741A
12-91
M1702A
M2114
M2115A1M2125A
Family
M2147
M2708
M2716
M3604A1M3624A
M3625A
M3636
M510H/
M5101L-4
M8080A
M8212
M8214
M8216/M8226
M8224
M8228
12-3
12-6
12-10
12-14
12-16
12-18
12-20
12-22
12-25
12-36
12-40
12-43
12-47
12-50
12-56
12-61
12-67
12-71
12-77
12-80
12-83
12-85
M8251
M8255A
M8085A
M8155
M8257
M8259
M8048/M8748/
M8035
*For specifications contact Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
1-3
2K 1256 x 8) UV Erasable PROM
1024 x 4-Bit Static RAM
14-4
14-6
High Speed 1K x 1-8it Static RAM
4096 x I-Bit Static RAM
8K and 4K UV Erasable PROM
16K 12K x 8) UV Erasable PROM
4K 1512 x 8) High Speed PROM
4K 11K x 4) PROM
16K 12K x 8) Bipolar PROM
14-10
14-15
14-21
14-27
14-32
14-34
14-37
256 x 4-Bit Static CMOS RAM
8-Bit N-Channel Microprocessor
8-Bit Input/Output Port
Priority Interrupt Control Unit
4-Bit Parallel Bidirectional Bus Driver
Clock Generator and Driver for 8080A CPU
System Control,ler and Bus Driver for
8080A CPU
Programmable Communication Interface
Programmable Peripheral Interface
Single Chip 8-Bit N-Channel Microprocessor
2048-8it Static MOS RAM With I/O Ports
and Timer
Programmable DMA Cont~oller
Programmable Interrupt Controller
14-40
14-43
14-48
14-53
14-56
14-59
14-87
14-98
14-105
Single Component 8-Bit Microcomputer
14-110
14-63
14-68
14-71
14-74
NUMERICAL INDEX
1702A
M1702A
1702AL-21
1702AL-2
2101A/8101A-4·
2102A/2102ALI
8102A-4·
2104A Family
2104A Family
2107C Family
2109 Family
2111A/8111A-4·
2112A
2114
12114
M2114
2115A/2125A
Family
M2115A/M2125A
Family
2115H,2125H
Family
2117 Family
2117-5
2118 Family
2141
2142
2147
M&147
21.wH
2Ji:48
'"
2316E
2332A
2364A
2608
2708/8708
12708/18708
M2708
2716
12716
M2716
2732
2758
2910
2911
2912
3101/3101A
3205
3207A
3207A-l
3222
3232
3242
3245
3404
3604A/3624A
Family
M3604AI M3624A
3605A/3625A
M3625A
3628
2K (256 x 8) UV Erasable PROM
2K (256 x 8) UV Erasable PROM
2K (256 x 8) UV Erasable Low Power PROM
256 x 4-Bit Static RAM
1K x I-Bit Static RAM
4096 x I-Bit Dynamic RAM
4096 x I-Bit Dynamic RAM
4096 x I-Bit Dynamic RAM
8,192 x I-Bit Dynamic RAM
256 x 4-Bit Static RAM
256 x 4-Bit Static RAM
1024 x 4-Bit Static RAM
1024 x 4-Bit Static RAM
1024 x 4-Bit Static RAM
4-5
14-4
4-9
3-4
4002
4003
4004
4040
4201A
4265
4269
4289
4308
3-8
3-12
3-20
3-28
3-33
3-45
3-49
3-54
13-3
14-16
High Speed 1K x I-Bit Static RAM
3-58
High Speed 1K x I-Bit Static RAM
14-10
High Speed 1K x 1-Bit Static RAM
16,384 x I-Bit Dynamic RAM
16,384 x I-Bit Dynamic RAM
16,384 x I-Bit Dynamic RAM
4096 x I-Bit Static RAM
1024 x 4-Bit Static RAM
4096 x 1-Bit Static RAM
4096 x 1-Bit Static RAM
High Speed 4096 x I-Bit Static RAM
1024 x 4-Bil Static RAM
16K (2K x 8) ROM
32K (4K x 8) ROM
64K (8K x 8) Bit ROM
8K (lK x 8) Factory Programmable PROM
8K and 4K UV Erasable PROM
8K UV Erasable PROM
8K and 4K UV Erasable PROM
16K (2K x 8) UV Erasable PROM
16K (2K x 8) UV Erasable PROM
16K (2K x 8) UV Erasable PROM
32K (4K x 8) UV Erasable PROM
8K (1 K x 8) UV Erasable Low Power PROM
PCM CODEC - I' Law
PCM CO DEC - A Law
PCM Line Filters
16 x 4-Bit High Speed RAM
1 of 8 Binary Decode~
Quad Bipolar to MOS Level Shifter and Driver
Quad Bipolar to MOS Level Shifter and Driver
4K Dynamic RAM Refresh Controller
4K Dynamic RAM Address Multiplexer
and Refresh Counter
16K Dynamic RAM Address Multiplexer
and Refresh Counter
Quad TTL to MOS Driver for 4K RAMs
High Speed 6-Bit Latch
3-63
3-64
3-76
3-88
3-89
3-95
3-99
14-14
3-105
3-106
4-12
4-15
4-16
4-17
4-20
13-4
14-27
4-23
13-5
14-17
4-28
4-31
6-3
6-15
6-26
3-107
5-3
5-7
5-11
5-13
4K
4K
4K
4K
8K
4-36
14-32
4-39
14-34
4-42
(512 x 8) High Speed PROM
(512 x 8) High Speed PROM
(lK x 4) PROM
(IK x 4) PROM
(1 K x 8) Bipolar PROM
3636
M3636
4001
5101 Family
M5101-41
M5101L-4
800818008-1
8021
8022
8041A/8741A
8048/86481
8748/8035
18048/186481
18748/18035
M8048/M87481
M8035
8049/8039-6
8080A/80aOA-ll
80aOA-2
M8080A
8085A/8085A-2
M8085A
8086/8086-4
8155181561
8155-2/8156-2
18155/18156
M8155
8185/8185-2
8202
8205
8212
18212
M8212
8214
M8214
8216/8226
18216/8226
M8216/M8226
821818219
5-19
5-23
5-27
5-3
8224
M8224
822818238
M8228/M8238
8243
14
16K (2K x 8) Bipolar PROM
16K (2K x 8) Bipolar PROM
256 x 8 Mask Programmable ROM and 4-Blt
1/0 Port
320-Bit RAM and 4-Bit Output Port
10-Bit Shift Register 10utput Expander
Single Chip 4-Bit P-Channel Microprocessor
Single Chip 4-Bit P-Channel Microprocessor
Clock Generator
Programmable General Purpose 1/0 Device
Programmable Keyboard Display Device
Standard Memory Interface
1024 x 8 Mask Programmable ROM and
4-Bit 1/0 Ports
256 x 4-Bit Static CMOS RAM
4-45
14-37
7-11
7-10
7-5
7-4
7-3
7-8
7-6
7-7
7-9
7-13
3-111
256 x 4-Bit Static CMOS RAM
8-Bit Microprocessor
Single Component 8-Bit Microcomputer
Single Component 8-Bit Microcomputer
with AID
Universal Peripheral Interface 8-Bit
Microcomputer
14-40
9-5
8-4
Single Component 8-Bit Microcomputer
8-22
Single Component 8-Bit Microcomputer
13-16
Single Component 8-Bit Microcomputer
Single Component 8-Bit Microcomputer
14-110
8-31
8-Bit N-Channel Microprocessor
8-Bil N-Channel Microprocessor
Single Chip 8-Bit N-Channel Microprocessor
Single Chip 8-Bit N-Channel Microprocessor
16-Bit HMOS Microprocessor
2048-Bit Static MOS RAM With 1/0 Ports
and Timer
2048-Blt Static MOS RAM With 1/0 Porls
and Timer
2048-Bit Static MOS RAM Wilh 1/0 Ports
and Timer
1024 x 8-Bit Static RAM for MCS-85
Dynamic RAM Controller
High Speed l-oul-of-8 Binary Decoder
8-Bit Input/Output Port
8-Bit InputlOutput Port
8-Bit InputlOutput Port
Priority Interrupt Control Unit
Priority Interrupt Control Unit
4-Bit Parallel Bidirectional Bus Driver
4-Bit Parallel Bidirectional 8us Driver
4-Bit Parallel Bidirectional Bus Driver
Bipolar Microcomputer Bus Controllers for
MCS-80 and MCS-85
Clock Generator and Driver for 8080A CPU
Clock Generator and Driver for 8080A CPU
System Controller and Bus Driver for
8080A CPU
System Controller and Bus Driver for
8080A CPU
MCS-48 ™Input/Output Expander
8-10
11-3
9-11
14-43
9-54
14-74
10-4
9-70
13-7
14-87
9-77
11-14
9-29
9-35
13-6
14-48
9-45
14-53
9-49
13-9
14-56
9-81
9-19
14-59
9-25
14-63
8-36
NUMERICAL INDEX
18243
8251A
18251A
M8251A
8253/8253-5
8255A/8255A-5
18255A
M8255A
8257/8257-5
M8257
8259A
18259
M8259
8271
8273
MCS-48 ™Input/Output Expander
Programmable Communication Interface
Programmable Communication Interface
Programmable Communication Interface
Programmable Interval Timer
Programmable Peripheral Interface
Programmable Peripheral Interface
Programmable Peripheral Interface
Programmable DMA Controller
Programmable DMA Controller
Programmable Interrupt Controller
Programmable Interrupt Controller
Programmable Interrupt Controller
Prog rammable Floppy Disk Controller
Programmable HDLCISDLC Protocol
Controller
Programmable CRT Controller
Programmable Keyboard Interface
Programmable KeyboardlDisplay Interface
Programmable KeyboardlDisplay Interface
Octal Latch
Clock Generator and Drive for 8086 CPU
Octal Bus Tranceiver
Bus Controller for the 8086 CPU
GPIB TalkerlLlstener
GPIB Controller
Data Encryption Unit
Dot Matrix Printer Controller
16,384-Bit ROM With 1/0
16,384-Bit ROM With 1/0
16,384-Bit EPROM With 1/0
16,384-Bit EPROM With 1/0
Clock Generator Crystal for 8224/8080A
8275
8278
8279/8279-5
18279
8282/8283
8284
8286/8287
8288
8291
8292
8294
8295
8355/8355-2
18355
8755A
18755A-8
8801
Available Literature
Basic-80 Extended ANS 1978 Basic Intellec® Resident Interpreter
Bipolar Cross Reference
Development Systems
Distributors
EM 1 Emulation Board
EM2 Emulation Board
13-10
11-24
13-11
14-68
11-32
11-43
13-12
14-71
9-92
14-98
9-109
13-13
14-105
11-64
Expansion Chassis Intellec® Series II
FORTRAN-80 Intellec® Resident Compiler
ICE-49 MCS-48 In-Circuit Emulator
ICE-80 8080 In-Circuit Emulator
ICE-85 MCS-85 In-Circuit Emulator
ICE-86 8086 In-Circuit Emulator
Insite Users Library
Intel Technical Library
Intellec® Printer
Intellec® SinglelDouble Density Flexible Disk System
Intellec® Prompt 48 MCS-48 Design Aid
ISIS-II Diskette Operating System
MCS-48 Diskette-Based Software Support Package
MDS-311 8086 Software Development Package
Memory Support Circuits
Microcomputer Training Programs
Military Products
Model 210 Intellec® Series II
Model 220 Intellec® Serres II
Model 230 Intellec® Series II
Model 770 Printer Intellec® Series II
Ordering Information
Packaging Inlormation
Peripherals
PLlM-80 High Level Programming Language Intellec®
Resident Compiler
PROMIROM Programming Instructions
Sales Offices
SDK-85 MCS-85 System Design Kit
SDK-86 MCS-86 System Design Kit
SDK-C86 MCS-86 System Design Kit Software and Cable
Interface to Intellec® Development System
Standard Product Flow
Technical Library
f'Scope 820 Microprocessor System Console
f'Scope Probe 8080A
f'Scope Probe 8085
UPP-l03 Universal PROM Programmer
Users Library
11-93
11-118
11-142
11-152
13-14
10-23
10-27
10-33
10-37
11-164
11-188
11-190
11-201
9-127
13-15
9-132
13-18
9-23
2-14
12-40
4-4
12-2
2-19
12-77
12-80
/ 0
'}
(~/
1-5
12-14
12-36
12-56
12-61
12-67
12-71
12-99
2-14
12-18
12-43
12-50
12-47
12-20
12-25
5-2
12-112
14-2
12-3
12-6
12-10
12-16
2-3
2-4
11-2
12-22
4-48
2-17
12-85
12-91
12-97
2-12
2-14
12-103
12-108
12-110
12-83
12-99
Generallnformation
2
GENERAL INFORMATION
TABLE OF CONTENTS
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
Packaging Information............................................................................. 2-4
Standard Product Flow ............................................................................. 2-12
Intel Technical library .............................................................................. 2-14
Sales and Marketing Offices ......................................................................... 2-17
Distributors ...................................................................................... 2-19
2-2
ORDERING INFORMATION
Semiconductor components are identified as follows:
Example:
M
C
5
o
1
L -_ _ _ _ _ _ _ _ _ _ _ _
1
L
4
~------------~I ~I-------r------~
L
Four
five characters
per device type
Up to three character
modifier for power,
speed, processing, etc.
Package Type
B - Hermetic Package, Type B
C - Hermetic Package, Type C
o - Hermetic Package, Type D
M - Metal Can Package
P - Plastic Package
X - Unpackaged Device
M - Indicates Military Operating
Temperature Range
I - Indicates Industrial Grade
Examples:
P5101 L
CMOS 256 X 4 RAM, low power selection, plastic package, commercial temperature range.
C8080A2
8080A Microprocessor with 1.5 f..lS cycle time, hermetic package Type C, commercial
temperature range.
MD3604/C
512 X 8 PROM, hermetic package Type D, military temperature range, MI L-STD-883 Level
C processing. *
MC8080A/B
8080A Microprocessor, hermetic package Type C, military temperature range, MI L-STD-883
Level B processing. *
Kits, boards and systems may be ordered using the part number designations in this catalog.
The latest Intel OEM price book should be consulted for availability of various options. These may be
obtained from your local Intel representative or by writing directly to Intel Corporation, 3065 Bowers
Avenue, Santa Clara, California 95051.
*On military temperature devices, B suffix indicates MIL-STO-883 Level B processing. Suffix C indicates MIL-STO-883 Level
C processing. "S" number suffixes must be specified when entering any order for military temperature devices. All orders
requesting source inspection will be rejected by Intel.
2-3
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
PLASTIC DUAL IN-LINE PACKAGE TYPE P
l6-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
.835 121.2091
r - . 8 2 5 120.9551
C
~
I- - - - __ -3PINo11'255It'4771
.20015.0801
MAX.
SEATING
PLANE
.
125J~r251
.245 (G.223)
~
---
.140 13.5561
====
.13013.303
mrrm: ____~nrtJ1iJT1
~.015MIN .
r-I L::....i i - JI-.02010i~~811
J~ (2.7941
.060 TYP
.090 12.2861
11.5241
c
.032 TYP
.905 122.9871
r - .895122.7331---
l8-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
l----
o .255 (6.467)
.245 16.2231
125~~~~751
r-I
~
ff'l
---
".,,~ ." mmn:
nrtJ1iJT1-..
.
J
---3PIN11
.20015.0801
PLANE
.016 (Q.406)
10.8131
L::....i ~
I_-M":~';!
18.255~1
.140 13.5561
~ .015 MIN .
-.II- .020
.110 (2.7941
.060 TYP
.032 TVP
.090 12.2861
11.5241
10.8131
10.5:~811
.D1om
10.2541
-J t ~L
L
""Cii6 (0 406)
.
o·
!
is·
!
.350
I
18.8901--1
REF .
.
1.035126.2891 ~
r-1.025126.0351
C ---3
20-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
1__ _ _
PIN1
1
.25516.4671
.245 16.2231
~
---
.325
-MAX,;!
.20015.0801
MAX.
SEATING
PLANE
.12513.1751
MIN.
.130 13.3021
====
Fa
[
13.0461]
~
Ir I - --~~
L::....i
I
,...J
~ 12.7941
.090 12.2861
II
.015 MIN.
10.3811
.D10m-J
(0.254)
.080 TVP
11.5241
.032 TVP
10.8131
t l~
, 5'
-.:
I
L
-.J~ .020 (0.508)
1
(8.255~1
.016 10.4061
I
.350
I
18.8901--1
REF.
'·'05(28.067)~
C 1.095 (27.813)
22-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
C
- _ - 3 P I N o l .35510171
.34518.7631
~
---
.200 15.0BOI
M4~,
=~
~
[
.145 13.6831]
S;t-R.N~EG,----+--mrrm:~
nrtJ1iJT~ ~
I
~.015MIN.
125131751
MIN.
i
,J L
1
.110 (2.794)
,060TYP
.032TYP
.090 12.2861
11.5241
10.8131
2-4
-.II- .020
J
-A
.425
.155 13.9371
10.~~~11
.016 (OAD6)
.010 TYP
(0.254)
MAX.
110.7951
,
-.:
I
I
I
I
.450
1"'-111.4301--1
REF .
0°
;So
PACKAGING INFORMATION
All dimensions
In
Inches and (millimeters)
PLASTIC DUAL IN-LINE PACKAGE TYPE P
r----
24-LEAD PLASTIC DUAL IN·LlNE
PACKAGE TYPE P
, .245 (31.623)
1.235 (31.369) - r
C
I
-
-
PIN
__ - 3
; 1.545 t.843}
-
.625
.160 (4.064)
[
mJ~~ ~~"50
13.8~0}1
MAX.
PLANE
12!) (3.175)
MIN.
-.J
__
.200 (5.080)
SEATING
.535 (13.589)
___
I'
JI
L
J
.
-
.:.!!Q. (2.794)
.090 (2.286)
-)
.060 TYP
(1.524)
--.-'.015 MIN.
IL
-1
-
[
I
.650
I
(16.510)-.)
REF .
.535 (13.665)
-.J
.625
.160 (4.064)
MAX.
_"___
I
,.I
~ (2.794)
.090 (2.286)
.060 TYP
(1.524)
[
.150 13.810} ]
S:~:'~:~3175}~~L~~===1WY
(i~li8~"N
~
[
t -..J;5~O.
_l'IN~11'545t'843}
.200 (5.080)
40·LEAD PLASTIC DUAL IN·LlNE
PACKAGE TYPE P
L
.016 (0.406)
I
1.455 (36.S57)
---1.445(36.703)--[
___
MIN.
I
-.020 (D.50B)
.032 TYP
(0.813)
C ---3-
28·LEAD PLASTIC DUAL IN·LINE
PACKAGE TYPE P
O1OTYP-t
1O.254}
(0.3811
MAX. --I
115.875}
.032 TYP
(0.813)
010 TYP
{O.254J
-t
MAX.]
115.875}
t ~~.
~
150
I
L
--..JI-- .020 (0.508)
.016 (0.406)
I
I
.650
(16.510)~
REF .
2.055 (52.197)
- - - 2.045 { 5 1 . 9 4 3 ) - r
C
---3'_PIN~I_1
I
.545 (13.843)
___
~~3.5891
[
ClOTYP
(0.254)
-t
.625
MAX.
115.875}
1I
t l~
15
--.l
I
I
'L 116.510}.....I
.650
I
REF.
2·5
PACKAGING INFORMATION
CERAMIC DUAL IN-LINE PACKAGE TYPE D
.790 (20.066)
16-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
.750
---------------
C
1
All dimensions in inches and (millimeters)
-
(19.050)~
---~~NJI
.310 (7.874)
.265 (6.731)
~
--.200(5.0aO)
M~
SEATING
--PLANE
.140 13.5 561
1
t-~V~--~.
~ IVI ~
~ (2.794) j
MIN.
L
.060 TVP
(1.524)
.090 12.286)
.032 TYP.
(0.813)
l.015MIN .
~880 {22352} ~
C
---~--"-'NJII
~!~-(~~
.265 (6.731)
~
--.200 (5.080)
M~
10.3811
.......11 __ .020 (0.508)
:016 (0.406)
-
.920 (23.000)
--------1
18-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
1
.165 (4.1911
=_
l= i:J 1_
-
. ,2513.1751 ___
_ _ _~
__
--_~
~4(j i3~56j
_
SEAT~___~ _ _ _ ~.
PLANE
12513.1751
MIN.
INi U
J-----~Vi VU
I
l
~
II
.060 TVP
.090 (2".286)
(1.524)
-l·015 MIN.
10_3_8 11
-. __
~
I
. 110 (2.794)
:92~
,325
1
.165 (4.191)
r- 18.2551. ]
1
MAX
010 TVP
(O.254)
I::
I
j_193~,s51_1
(Q..508J
.016 (0.406)
.032 TVP
(0.813)
REF .
-
.990 (25.146)
~ fi.
;
--.., I
------------- ,950 (24.130) ~
1
20-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
C
---~--"-'NJI-1
.~(7.8~)
.26516_7311
~
---
.325
.200 (5.080)
SEATINGM~X.,
-
.165 (4.191)
=_~
-
3
.140 1 .:561
1
~J
~ IVI~---~'l'015MIN'
~
PLANE
]
,J t
.125 (3.175)
MIN.
_11 __
.110 (2.7941
.060 TYP
.032 TYP
.090 (2.286)
(1.524)
(0.813)
1.095 (27.813)
, - - - 1.060 (26.924)
1
22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
C
-
---~.
~NJI
.400~
.370 (9.398)
_=~=_
MAX.
.016 (O.406)
~
--.20015_0801
10.3811
02010.5081
~
.18014.5721
_15013.81;IJ
SEATING
t~==---~l·015MIN.
.'25(3.'75)~=V VIVI11~V
J
PLANE
M IN
.
.110 (2.794Jj
.090 (2.286)
t
(O.381)
.060 TYP
11.524)
.032 TYP
10.8131
2--6
-J1---..020
(D.S08)
:016
(O.4DS)
-MAX.]
18.2551
I
010 TVP
(a.254)
I::
I
~ fi,
;
-.., I
1-19':b~1-1
REF .
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
CERAMIC DUAL IN-LINE PACKAGE TYPE C
C
,
IT
16-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
.820 120.820}---::J
.790 120.066}
===
J
r:
.300 17.620}
L
.280 (7.112)
~~-
C ·
PIN 1 MARK
PIN 1
~
.920 120.8201
880 119.8121--:;J
18-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
IT
-~---
.300 (7.620)
[
.280 17.112}
~~-
~
.200 15.0BOI
MAX
PIN 1 MARK
PIN11
.095 12.413}
'L--- JLJI ~
I
mR-_-W
W
q
-- 0701,m
~
S~t~~~G
125 (3 175)
050 TVP
MIN
1'2701
110 (2794)
032 TVP
.090 12.286}
10.8131
C
.970 (24.638)
---
(0635)
'-.:$'fio
0'0 TYP
(0.2541
I
"
I
325
I
1--(82551---1
REF
n
.990 125. '461
MAX
025MIN
022 10 558}
0"1'S (0 381)
--
--:J
[1---
20-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
~
,
,30
(3.3021
PIN 1
PIN'MARK
I
.300 17.6201
.280 17.112}
-~-
~
4
.20015.0BO}
MAX.
.'2013.048}
.'00
S~t~~~G ~L:-~nt1flfjJ
L¥l 1--lL.'-02-5..L!'N~~~4~9':"010 -+-~
fio
¥M
'
'-.~
JI
,.
10.635}
.125 (3.175)
MIN.
.060 TVP
(1.270)
.110 (2.794),
.090 12.2861
22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
TYP
10254}
l--(l3~22:5)---J
.022 (0.5581
.....015 (0.381)
.D32 TYP.
REF .
10.813)
, [ J!,
IT
C
'.095 127.8'3}
-:J
1.060 126.9241
PIN 1
===
I
PIN 1 MARK
.400 110.'601
..J
L'
~~-
.380 (9.652)
~
102541
I
.425
I
f--Il0.7951--<
REF.
2-7
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
CERAMIC DUAL IN-LINE PACKAGE TYPE D
C
---~PIN11
C
24-LEAD HFRMETIC DUAL IN-LINE
PACKAGE TYPE D
,.285 (32.S39)-=-:)
1.235 (31.369)
.600 115.2401
.515 (13.081)
~
---
C
.625
22015.5881
':::'~:=
125M(~N~75J
m · ~L~~}MIN
MAX.;!
175 144451
145
I!J ~
~
.110 (2.794)
I
060 TYP
I--
11.5241
(0381)
1:: l
1
.010 TYP.
(0.254)
_ _ 020 105081
.032 TYP
.090 12.2861
I
.
1.285 (32.639)
1.235 (31.369)
.......... I
'
.675
~o
1--117.1451--1
.016 (0.406)
REF .
10.8131
C
---"1
[Jo-O-':o
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
(15.875~1
PIN 1
/".2401
.515 (13.081)
~
-
~
.232 (5.893)
MAX.
_
:=:=:-:;'::.:=0: _
l!Z.2.Q.!
r-~--~
~~ l lU! U
t
I
I
'L
r.t t:
-..I
SEATING
PLANE
. 12513.,751J--r
MIN.
,
.145 13.6831
a.15M/N .
U.060TYP.
(1.S24)
.110 (2.794)
.090 (2.286)
.032 TYP.
(0.813)
1
10.3811
.010 TYP.
(0.254)
.020 (0.508)
o·
~ ...-";so
,,
,
lI1;;:51
.016 (0.406)
REF .
.J
1.485 (37.719)
1
28-LEAD HERMETIC DUAL IN·LINE
PACKAGE TYPE D
1.435
C
.220(5.588)
MAX.
SEATING
PLANE -
_
(36.449)~
._~~I
---~l
.600 115.2401
.515 (13.081)
~
---
-===- ~ ==="
.625
MAX .::--1
.145
~'tll
MIN.
--
I
-.060 TYP.
(1.524)
.010 TYP.
10.2541
.032 TYP
.090 12.2861
10.8131
1.485 (37.719)
1.435 (36.449)
I
-,
i.-ll;;:51~
- - - - .020 (0.508)
.110 (2.794)
C
MIN
.01653811.
I
1 : lf
115.8751
~~~6~3)_]_
E~=----~:I.J
~V V1U11f
t
.12513.1751
C
.175 (4.445)
.016 /0.406)
REF .
---'1
[J9-O-t:1
28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
PIN 1
.600 (15.240)
30811
.232 (5.893)
SEATING
PLANE
_
MIN.
:=:=:-:;'::.:=0: _
.145 13.6831
r-~-~
+
~l ~ ~I U
t
jI
'L
. ,2513.1751J--r
r+-l
.110 (2.194)
.090 (2.286)
1
.187 (4.750) •
MAX.
t:.
2-8
U.060TYP.
-.l
(1.524)
.032 TYP.
(0.813)
O.15MIN .
10.3811
.020 (0.508)
.016 (0.406)
.010 TYP.
(0.254)
I
lI176;:51
REF .
I
.J
fio
PACKAGING INFORMATION
All dimensions In Inches and (millimeters)
CERAMIC DUAL IN-LINE PACKAGE TYPE D
C
C---~r
~
40·LEAD HERMETIC DUAL IN·LlNE
PACKAGE TYPE D
2008D (52.B32)~
2.030 (51.S62)
PIN 1
.600 {15.240}
.515 {13.0Bl}
---
.625
.220 {5.5SB}
_-==--====_
MAX.
MAX·01
il
1~15.875~1
.175 (4.445)
~~1
.145
r-~=---~=r=I
SEATING
PLANE
.'25J~N175)L
U~.060TYP.
I-
(1.524)
.110 (2.794)
.090 (2.286)
.032 TYP
(O.B13)
C
40·LEAD HERMETIC DUAL IN·LlNE
PACKAGE TYPE D
l015MIN.
'L
--l
2.080 (52.832)
2.030 (51.562)
(0.381)
.020 (O.50B)
.016 (O.406)
-----I
[Jo-OPlN'
-
.6001,5.2401
.515 (13.0Bl)
~
.625
.232 (5.893)
_--= :c "-=L _
MAX.
. '45
(3.6B:ii]
S~t:~~G [~~II---~-{0.'5MIN.
I
JL
.125 (3.175)
MIN.
r+l
~ .060 TYP.
(0.381)
{1.524}
.110 (2.794)
.090 (2.286)
.020 (0.508)
.032 TVP.
(0.813)
2·9
~
AX.J
(15.875)
.187 (4.750)
.016 (0.406)
(O.2S4)
0"
~ .......-,,-so
.010 TYP.
I
L
I
1176~~51
REF .
.J
PACKAGING INFORMATION
All dimensions in Inches and (millimeters)
CERAMIC DUAL IN-LINE PACKAGE TYPE C
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
I
----------~ (3D.a61) _______ 1
1.185 (30.099)
PIN 1 MARK
PIN 1
D[~ =l-
.600 ),..2401
.570 (14.478)
_~~
_I
.14SMAX
J)~ (2.4131
.200 15.0801
(3.6831
S~t;~~G--r---MLAr-~-l~~.= 1m~'N
.125 {3.175J
MIN.
.050 TYP
..... (1.270)
JI
.010 TYP
(0.254)
(0.5081
H
.015 (0.3811
-I
D[- el
1
1.415 (35.941)
- ------,·385
(35.'i79)
=~..
.570 (14.4781
_I
M-jl:-X_'
.125 (3.175)
MIN.
1fflV2:.
JI
.095 (2.413)
S~~;~~G __ -ITi~
~~
.145 MAX
.050 TYP
r-
_
PIN 1 MARK
.600 t(15.2401
'Nl
_=_
.200 (5.0ao)
't
.625
I
(15.875)---J
REF .
. 110(2.794)
.090 (2.286)
2a-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
1
!
L
...... ,022 (O.S58)
,--
O"
\t".: I'W
(1.270)
.010 TVP
10.2541
..... :6~~
+~ #'&
''....~
!
(0.508)
II
:6:~:~:
.110 (2.794)
.090 (2.286)
4O-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
DC-=J-el
_ 2 . 0 2 0 (51.308'----::1
,
1.980 (50.29 21
PIN 1
MARK
PIN 1 :1,5.2401
.570 (14.478)
---.l
_= _
.095 (2.413)
·
.070 ( 1 . n 8 I L L
~-=1m
__ _
JL
f
.145
(3.683)
MAX.
t.020 MIN.
.050 TVP
(1.270)
(0.5081
.022 (0.558)
.015 (O.38l)
.110(2.794)
.090 (2.2861
2-10
.010 TYP
(0.254)
~0
I
.
I'
"-..f
,
~'
.625
-(1~.:~~)
10
PACKAGING INFORMATION
All dimensions
In
Inches and (millimeters)
CERAMIC DUAL IN-LINE PACKAGE TYPE B
C
22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
-
1.095 (27.813) ~
1.060 (26.924)
B~-==-=~D
PIN'-.J,0.'601
.370 I 9.3981
,=~~
200 {5 080)
MAX.
~
~~~~~~m'25
13'~
1.
~
SEATING
r---
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
190 (4.826)
M('O'795)~1
I
1.235 (31.369)
.J ~,
.0'0 TVP
LI':~~5Ij
102541
(0.813)
1.285 (32.B39)
1
MAX,
_ .160 (4.064)
IIII-----j Il t==iF-0-'5-M~'N
'25MI~N1751 :~~~ :~:~:::j L~O~TYPO~TYPjL .~~~ :gi::
=;P"'LA;;';N"'E=---+--
(1,524)
.425
I
150 (3810)
REF.
------J
I---~-=-B-_~N_.ll!
EI
_
.600 (15.240)
.515 (l3.0Sl)
~
----.220(5.558)
MAX
b'MAX.g
.625
M
.150 (3.Sl0)
(3 17~
125
(15.875)
ffi1TIf1~=~~TInTInlt t ~:~ :~:~~:
j1nrflft ~~53~~~ ~~02~:r
L~ h L, -t.02010~081
SEATING
.'OO;;;~~~:C;C:~:I=--+~~~rrnl
MIN.
.11012.794Ij
.090 (2.286)
.060 TYP.
.032 TYP
(1.524)
(0.813)
r---
28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
1.485 (37.719)
1.435 (36.449)
L
016 (0 406)
.
.675
(17.145)
.
-i
J
*.
REF.
------J
I---~--=E-_~N_.ll!
EI
.~
_
(15.240)
.570 (13.0811
--~-
.220(5.558)
MAX
~ ;::c~c;-mmj
SEATING
'~PL7CAN:;:-E--+--
.125 (3.175)
MIN.
h-----j ~
~
-~
:~:.:: :~:~::: j L
t
.060 TVP.
.032 TVP
(1.524)
(0.813)
C
40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
~
2.080 (52.832)
2.030 (51.562)
EI~
MIN.
-~
.110 (2.794)
.090 (2.286)
j
L
2-11
~,
1'76i~51
020 10 5081
REF.
.600 (15.240)
.570 (13.081)
~
~:::-~~~m"25
13,'4
~
L J'J
.016 (0.406)
.150 (3.810)
P;;CL7;AN~E=---t---
(02541
MI'5~75~1
B-PIN'!
.220(5.558)
MAX.
O,OTVP.
(0381)
j ' MAK 0l
~
--~-
SEATING
I:: ::::
0,5MIN
_IL
_
.125(3.175)
.625
.150 (3.810)
h-----j ~
.060 TVP.
,032 TVP
(1.524)
to.813)
~
!
.'90 148261
MAX
(0.381)
.020 (0.5081
,016 (0.406)
O'OTVP
(0254)
01
M"5875~1
_ .155 (3937)
t=!o--.~0'~5M~,.LN.
__I'L
.625
I
,
L
~ ;'i;
.675
jl
(17.145)-REF.
STANDARD PRODUCT FLOW
Wafer
Fabrication
Hermeticity Testing to
eliminate devices which
show insufficient
hermeticity. (Monitored
byQA)
Fine leak C OIPs.CERDIPs.and
Metal cans (MIL-STD-883
Method 1014.28),' Gross Leak
C DIPs and Cerdips only (Method
1014.2C. vacuum omitted and 1 hour pressurozatlon>.
1st Optical Inspection
For Fab Defects
Electrical Wafer Sort
.. ~I
1st Optical Inspection
for Sort Defects
Optical inspection criteria based on
MIL-STO-883 Method 2010.3B to
insure that all devices are free
from internal defects which could
lead to failure in normal applications.
(Monitored by QA)
Temp Cy
Seal
Scribe or Saw & Break
HERMETIC
2nd Optical Inspection
2nd Optical Inspection QA Gate
Die Attach
Die Attach Inspection
QA Die Attach Gate
Lead Bond
Lead Band Inspection
Lead Bond Gate
2-12
Precap Visual
Inspection criteria
based on MIL-STO-883
Method 2010.3B to insure
that after assembly all devices are free
from defects which could lead to failure
in normal applications. (Each lot must
pass a QA acceptance.)
STANDARD PRODUCT FLOW
Final Visual
Lead Trim
late
QA Outgoing Acceptance
"Fine leak limits: All
devices 1 x 10-7 cc-atm/sec
Electrical Testing to test
conditions and limits which guarantee
AC, DC and functional performance over
full
temperature
range.
Solder Dip
Deilash, Trim & Form
Temp Cycle
Mold
PLASTIC
Electrical 1% AQL
Functional Tests to guarantee
performance over full specified
temperature range
Visual/Mechanical LTPD 7/2
Solderability LTPD 5010
Hermeticity LTPD 7/1
Plant Clearance
2·13
IN II:L t"I1UUU\,; I LIII:.HA I U HI:.
The accelerating rate of new developments in microprocessors and memories has created the need for concise, up-tothe-minute design information. To assist customers in maintaining expertise in state of the art systems, Intel provides
a variety of sales and technical literature including brochures, data sheets, application notes, handbooks, and
technical manuals containing comprehensive information on microprocessors, microcomputers, memories, development systems, and software.
If you wish to receive Intel literature, contact your local Intel sales office, representative, distributor or Intel Corporation, Literature Department. International locations also provide selected literature in Japanese, French or German.
To order literature by mail, please enclose check or money order payable to Intel Corporation. Purchase Orders are
accepted for amounts of $100.00 or more. You can also order Intel documentation with your Master Charge or
BankAmericardlVisa credit card. Include your card number, expiration date and signature on the order form. Volume
and educational discounts are available. A maximum of five complimentary (N/C) items may be ordered. Mail to:
Intel Corporation
Literature Department
3065 Bowers Avenue
Santa Clara, California 95051
SALES LITERATURE
Product Descriptions
Catalogs
9800365
9800600
9800606
610200
1978 System Data Catalog
$2.00
Brochures
Microcomputer Product Line
Brochure
Microcomputer Components
Brochure
Memory Components Brochure
Growing Static RAM Family Album
MOS RAMs Brochure
f'Scope 820 Brochure
1979 Intel Microcomputer Workshops Brochure
9800615
N/C
9800723
N/C
N/C
N/C
N/C
N/C
MCS-85 Product Description
Peripherals Product Description
Intellec Series II Microcomputer
Development Systems Functional
Description and Specifications
MCS-48 Single Chip Family of
Microcomputers Product
Description
MCS-86 Product Description
N/C
N/C
N/C
N/C
N/C
Reference Guides
9800774
9800749
N/C
BASIC 80 Reference Guide
MCS-86 Assembly Language
Reference Guide
N/C
N/C
Application Notes
AP-4
AP-12
AP-15
AP-16
AP17
AP-22
AP-23
AP-24
AP-26
AP-27
AP-28
AP-29
AP-30
AP-31
AP-33
AP-35
AP-36
AP-40
AP-42
AP-43
AP-45
2107A Application Note
5101 Application Note
8255 Programmable Peripheral
Interface
Using the 8251 Application Note
2709 8K Erasable PROM Application Note
Which Way for 16K
2104A 4K RAM
MCS-48 Family-9800413B
iSBC 80/10 & System 80/10
Control With UPI-41
Multibus Interfacing-9800587A
Using The Intel 8085 Serial
I/O Lines
Applications of 5 Volt EPROM and
ROM Family for Microprocessor
Systems
Using the 8259-9800658A
RMX/80-9800577 A
CRYSTALS: Specifications9800652A
Using the 8273-9800667A
Keyboard/Display Scanning With
Intel's MCS-48 Microcomputers
Writing Diagnostics for the f'Scope
Using the iSBC™ 957 ... 9800816
Using the 8202 ... 9800809
N/C
N/C
Reference Cards
9800404
9800438
N/C
N/C
9800547
9800582
N/C
N/C
N/C
N/C
N/C
N/C
N/C
9800653
9800412
PROMPT 48 Reference Card let
$1.50
8085/8080 Assembly Language
Reference Card
FORTRAN-80 Reference Card
f'Scope 820 8080A Operator's
Reference Card
MCS-48 In-Circuit Emulator
Reference Card
MCS-48 Assembly Language
Reference Card
UPI-41 Assembly Language
Reference Card
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Reliability Reports
N/C
N/C
N/C
RR 7
RR 8
RR 9
RR 10
RR 11
RR 12
RR 14
RR 15
RR 16
RR 17
RR 18
N/C
N/C
N/C
N/C
N/C
N/C
2-14
2107A/2107B 4K Dynamic RAM
Polysilicon Fuse Bipolar PROM
MOS Static RAMs
8080/8080A Microcomputer
2416 16K CCD Memory
2708 8K Erasable PROM
2115/2125 MOS Static RAMs
2104A 4K Dynamic RAM
2116 16K Dynamic RAM
iSBC 80/10 Single Board Computer
HMOS Reliability
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
PRODUCT LITERATURE
9800220
TECHNICAL LITERATURE
User's Guides
9800016
9800203
9800223
9800298
9800306
9800338
9800350
9800508
9800522
9800557
9800558
9800698
9800743
9800826
High Speed Paper Tape Reader
Installation and Operation Guide
MCS-80 System Design Kit User's
Guide
iSBC 80P and iSBC 80P10 Proto·
typing Package User's Guide
iSBC 635 Power Supply User's
Guide
ISIS-II User's Guide
SBC 80P20 User's Guide
iSBC 915 Go/No Go Diskette
Diagnostic and Monitor Program
User's Guide
iSBC 80P05 User's Guide
RMX/80 User's Guide
Intellec Series II Model 210
User's Guide
A Guide to Intellec Microcomputer Development Systems, by
Daniel D. McCracken
A Guide to PLiM Programming for
Microcomputer Applications, by
Daniel D. McCracken
MCS-86 System Design Kit User's
Guide
iSBC 957-lntellec iSBC 86/12 ...
User's Guide
f-IScope 820 Microcomputer Console
Key Sequence Guide
9800221
9800230
$2.50
$5.00
9800255
$5.00
9800265
$5.00
$30.00
$5.00
9800268
9800270
$5.00
$5.00
$15.00
9800277
9800278
$15.00
9800279
$2.00
9800292
9800294
$9.95
$7.50
9800297
$5.00
9800300
$2.00
9800301
Manuals
9800017
9800019
9800025
9800042
9800129
9800132
9800133
9800153
9800167
9800172
9800185
9800206
9800210
9800212
9800307
MCS-8 User's Manual
8008 Assembly Language Programming Manual
4004/4040 Assembly Language Programming Manual
MCS-40 User's Manual
Intellec 800 Microcomputer Development System Operator's Manual
Intellec Microcomputer Development System Reference Manual
Universal PROM Programmer Reference Manual
MCS-80 User's Manual
In-Circuit Emulator/80 Microcomputer Development System Hardware Reference Manual
ROM Simulator Microcomputer
Development System ROM SIM
Reference Manual
In/Circuit Emulator/80 Operator's
Manual
ISIS-I Diskette Operating System
Operator's Manual
Series 3000 Microprogramming
Manual
Diskette Operating System Microcomputer Development System
MDS DOS Hardware Reference
Manual
$2.50
9800316
$5.00
9800317
$5.00
$5.00
9800349
$15.00
$40.00
9800366
9800385
$40.00
$7.50
9800386
$35.00
9800388
$25.00
9800402
$15.00
9800410
$15.00
9800420
$5.00
9800422
$35.00
2-15
In-Circuit Emulator/30 Microcomputer Development System
ICE·30 Hardware Reference
Manual
Series 3000 Reference Manual
iSBC 80/10 and iSBC 80/10A Single
Board Computer Hardware Reference Manual
MCS-48 and UPI-41 Assembly
Language Programming Manual
iSBC 416 16K PROM/RPM Expan·
sion Board Hardware Reference
Manual
PLiM Programming Manual
MCS-48 Family of Single Chip
Microcomputers User's Manual
iSBC 104/108/116 Combination
Memory and I/O Expansion Boards
Hardware Reference Manual
iSBC 508 I/O Expansion Board
Hardware Reference Manual
iSBC 016 16K RAM Expansion
80ard Hardware Reference Manual
ISIS-II 8080/8085 Macro Assembler
Operator's Manual
iSBC 501 Direct Memory Access
Controller Hardware Reference
Manual
iSBC 630 Power Supply User's
Manual
ISIS-II PL /M-80 Compiler Operator's
Manual
8080/8085 Assembly Language
Programming Manual
Intellec PROMPT 80/85 User's
Manual
System 80/10 Microcomputer
Hardware Reference Manual
iSBC 80/20 and iSBC 80/20-4 Single
Board Computer Hardware
Reference Manual
iSBC 211/212 Diskette Harcjware
System Hardware Reference
Manual
MCS-85 User's Manual
iSBC 519 Programmable I/O Expansion Board Hardware Reference
Manual
Intellec Mirocomputer Development
System Diagnostic Confidence Test
Operator's Manual
iSBC 517 Combination I/O Expansion Board Hardware Reference
Manual
PROMPT 48 Microcomputer User's
Manual
iSBC 310 High-Speed Mathematics
Unit Hardware Reference Manual
iSBC 202 Double Density Diskette
Controller Hardware Reference
Manual
Intellec Double Density Diskette
Operating System Hardware
Reference Manual
$25.00
$5.00
$10.00
$10.00
$5.00
$10.00
$7.50
$5.00
$5.00
$5.00
$10.00
$5.00
$5.00
$15.00
$10.00
$5.00
$15.00
$10.00
$5.00
$5.00
$7.50
$5.00
$7.50
$7.50
$5.00
$5.00
$35.00
PRODUCT LITERATURE
9800449
9800450
9800451
9800452
9800463
9800464
9800465
9800466
9800467
9800478
9800480
9800481
9800482
9800483
9800484
9800485
9800486
9800487
9800488
9800489
9800504
9800505
9800556
iSBC 094 4K Byte CMOS RAMI
Battery Backup Board Hardware
Reference Manual
iSBC 534 Four Channel Communications Expansion Board Hardware
Reference Manual
SDK·85 User's Manual
8080/8085 Floating Point Arithmetic
Library User's Manual
ICE 85 In·Circuit Emulator Operat·
ing Instructions for ISIS-II Users
ICE-48 Operator's Manual
In-Circuit Emulator/41 Operator's
Manual
PUM-86 Programming Manual
PROMPT-SPP Specialized PROM
Programming User's Manual
ISIS-II PUM-86 Compiler Operator's
Manual
ISIS-II FORTRAN-80 Compiler
Operator's Manual
FORTRAN 80 Programming Manual
iSBC 80104 Single Board Computer
Hardware Reference Manual
iSBC 80105 Single Board Computer
Hardware Reference Manual
System 80/20-4 Microcomputer
Hardware Reference Manual
iSBC 711 Analog Input Board Hard·
ware Reference Manual
iSBC 724 Analog Output Board
Hardware Reference Manual
iSBC 732 Combination Analog
InputlOutput Board Hardware
Reference Manual
iSBC 032/048/064 Random Access
Memory Boards Hardware
Reference Manual
iSBC 556 Optically Isolated Programmable 1/0 Board Hardware
Reference Manual
UPI-41 User's Manual
iSBC 660 System Chassis Hardware
Reference Manual
Intellec Series II Hardware
Reference Manual
9800559
9800592
$5.00
9800593
$5.00
$5.00
9800611
$5.00
9800616
$25.00
$20.00
9800639
$15.00
$10.00
9800641
9800642
$5.00
$15.00
9800643
$20.00
$10.00
9800645
$15.00
9800697
9800698
9800722
9800728
9800758
9800819
$5.00
9800707
$7.50
$7.50
$5.00
Intellec Series II Installation and
Service Manual
flScope 8080A Probe Service
Manual
flScope 820 Microprocessor System
Console Service Manual
iSBC 80/30 Single Board Computer
Hardware Reference Manual
iSBC 544 Hardware Reference
Manual
MCS-86 Software Development
Utilities Operating Instructions for
ISIS-II Users
MCS-86 Assembler Operating
Instructions for ISIS-II Users
MCS-86 Assembly Language Converter Operating Instructions for
ISIS-II Users
iSBC 464 PROMIROM Board Hard·
ware Reference Manual
iSBC 86/12 Hardware Reference
Manual
SDK-86 Assembly Manual
SDK-86 User's Guide
MCS-86 User's Manual
flScope 8085 Probe Service Manual
BASIC 80 Reference Manual
Universal PROM Programmer User's
Manual
System 80/30 Documentation
Package
$15.00
$15.00
$15.00
$10.00
$7.50
$20.00
$15.00
$15.00
$5.00
$10.00
$5.00
$7.50
$5.00
$15.00
$15.00
$15.00
$25.00
Handbooks
9800526
$5.00
9800676
111100
$5.00
flScope 820 Microprocessor System
Console Operator's Handbook
$15.00
Peripheral Design Handbook - 1979 $7.50
Memory Design Handbook
$5.00
Specifications
9800199
$5.00
$5.00
9800222
$5.00
9800606
$25.00
2-16
External Reference Specification
ROM Simulator
External Reference Specification
ICE-30 Software Driver
Intellec Series II Microcomputer
Development Systems Functional
Description and Specifications
$2.50
$2.50
N/C
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987~8080
TWX. 910-338-0026
TELEX: 34~6372
ALABAMA
Intel Corp.
3322 S. Parkway, Ste. 71
Holiday Office Center
Huntsville 35802
Tel: (205) 883-2430
Glen White Associates
3502 9th Avenue
HUntsville 35805
Tel: (205) 883-9394
tPen-Tech Associates, Inc.
Holiday Office Center
3322 S. Memorial Pkwy.
Huntsville 35801
Tel: (205) 533-0090
ARIZONA
Intel Corp.
8650 N. 35th Avenue, Suite 101
Phoenix 85021
Tel. (602) 242-7205
tBFA
4426 North Saddle Bag Trail
Scottsdale 85251
Tel: (602)994-5400
CALIFORNIA
Intel Corp.
7670 Opportunity Rd.
Suite 135
San Diego 92111
Tel: (714) 268-3563
Intel Corp.·
1651 East 4th Street
Suite 105
Santa Ana 92701
Tel: (714) 835-9642
TWX: 910-595-1114
Intel Corp. *
15335 Morrison
Suite 345
Sherman Oaks 91403
(213) 986-9510
TWX: 910-495-2045
Intel Corp.·
3375 Scott Blvd.
Santa Clara 95051
Tel: (408)987-8086
TWX: 910-339-9279
TWX: 910-338-0255
Earle Associates, Inc.
4805 Mercury Street
Suite L
San Diego 92111
Tel: (714)287-5441
Mac-!
2576 Shattuck Ave.
Suite 4B
Berkeley 94704
Tel: (415) 843-7625
Mac-I
P.O. Box 1420
Cupertino 95014
Tel: (408) 257-9880
Mac-I
P.O. Box 8763
Fountain Valley 92708
Tel: (714) 839-3341
Mac-I
20121 Ventura B[vd., Suite 240E
Woodland Hills 91364
Tel: (213)347-5900
COLORADO
Intel Corp. *
6000 East Evans Ave.
Bldg. 1, SUite 260
Denver 80222
Tel: (303) 758-8086
TWX: 910-931-2289
tWestex
27972 Meadow Drive
P.O. Box 1355
E.... ergreen 80439
Tel: (303) 674-5255
CONNECTICUT
[ntel Corp.
Peacock Alley
1 Padanaram Road, Suite 146
Danbury 06810
Tel: (203) 792-8366
TWX: 710-456-1199
FLORIDA
Intel Corp.
1001 N.W. 62nd Street. Suite 406
Ft. Lauderdale 33309
Tel. (305) 771-0600
TWX: 510-956-9407
Intel Corp.
5151 Adanson Street, Suite 203
Orlando 32804
Tel: (305) 628-2393
TWX: 810-853-9219
tPen-Tech Associates, Inc.
201 S.E. 15th Terrace. Suite F
Deerfield Beach 33441
Tel: (305) 421-4989
u.s.
AND CANADIAN SALES OFFICES
MISSOURI
'Technica[ Representatives, Inc.
320 Brookes Drive, SUite 104
Hazelwood 63042
Tel: (314)731-5200
TWX: 910-762-0618
I Pen-Tech Associates, Inc.
111 So. Maitland Ave., Suite 202
Maitland 32751
Tel: (305) 645-3444
GEORGIA
tPen-Tech Associates, Inc.
Suite 305 C
2101 Powers Ferry Road
Atlanta 30339
Tel: (404) 955-0293
NEW JERSEY
Intel Corp.
1 Metroplaza Office Bldg.
505 Thornell SI.
Edison 08817
Tel: (201) 494-5040
TWX: 710-480-6238
ILLINOIS
Intel Corp.900 Jorie Bou[evard
Suite 220
Oakbrook 60521
Tel. (312) 325-9510
TWX: 910-651-5881
tDytek-Centra[, Inc.
121 So. Wilke Road
Suite 304
Arlington Heights 60005
Tel. (312) 394-3380
TWX: 910-687-2267
NEW MEXICO
BFA Corporation
P.O. Box 1237
Las Cruces 88001
Tel: (505)523-0601
TWX: 910-983-0543
BFA Corporation
3705 Westerfield, N.E.
Albuquerque 87111
Tel: (505)292-1212
TWX: 910-989-1157
NEW YORK
Intel Corp. *
350 Vanderbilt Motor Pkwy.
Suite 402
Hauppauge 11787
Tel: (516)231-3300
TWX: 510-227-6236
Intel Corp.
80 Washington St.
Poughkeepsie 12601
Tel: (914) 473-2303
TWX: 510-248-0060
Intel Corp.
474 Thurston Road
Rochester 14619
Tel: (716) 328-7340
TWX: 510-253-3841
tMeasurement Technology, Inc.
159 Northern Boulevard
Great Neck 11021
Tel' (516) 482-3500
T-Squared
4054 Newcourt Avenue
Syracuse 13206
Tel: (315) 463~8592
TWX: 710-541-0554
:T-Squared
2 E. Main
Victor 14564
Tel: (716) 924-9101
TELEX: 97-8289
INDIANA
E[ectro Reps Inc.
941 E. 86th Street, Suite 101
Indianapolis 46240
Tel: (317) 255-4147
TWX. 810-341-3217
IOWA
Technical Representatives, Inc.
St. Andrews Building
1930 SI. Andlews Drive N.E.
Cedar Rapids 52405
Tel. (319) 393-5510
KANSAS
Technical Representatives, Inc.
8245 Nieman Road, Suite #100
Lenexa 66214
Tel: (913) 888-0212, 3, & 4
TWX: 910-749-6412
KENTUCKY
tLowry & Associates, Inc.
3351 Commodore
Lexington 40502
Tel: (606) 269-6329
MARYLAND
Intel Corp.7257 Parkway Drive
Hanover 21076
Tel: (301) 796-7500
TWX: 710-862-1944
Glen White Associates
57 W. Timonium Road, Suite 307
Timonium 21093
Tel: (301) 252-6360
tMesa Inc.
11900 Parklawn Drive
Rockville 20852
Tel: Wash. (301) 881-8430
Balto. (301) 792-0021
NORTH CAROLINA
tPen-Tech Associates, Inc.
P.O. Box 5382
Highpoint 27262
Tel: (919) 883-9125
Glen White Associates
3700 Computer Drive
Suite 330
Raleigh 27609
Tel: (919) 787-7016
MASSACHUSETTS
Intel Corp.·
187 Billerica Road, Suite 14A
Chelmsford 01824
Tel: (617)667-8126
TWX: 710-343-6333
tComputer Marketing, Inc.
257 Crescent Street
Waltham 02154
Tel: (617) 894-7000
OHIO
Inte[ Corp. *
8312 North Main Street
Dayton 45415
Tel: (513) 890-5350
TWX: 810-450-2528
Intel Corp,·
Chagrin-Brainard B[dg. #201
28001 Chagrin Blvd.
Cleveland 44122
Tel, (216) 464-2736
Lowry & Associates, Inc.
24200 Chagrin Blvd.
Suite 320
Cle....eland 44122
Tel. (216)464-8113
tLowry & Associates, Inc.
1524 Marsella Drive
Dayton 45432
Tel: (513) 429-9040
tLowry & Associates, Inc.
1050 Freeway Or., N.
Suite 209
Columbus 43229
Tel: (614) 436-2051
MICHIGAN
Intel Corp.
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Tel: (313)353-0920
TWX: 910-420-1212
TELEX: 2 31143
tLowry & Associates, Inc.
135 W. North Street
Suite 4
Brighton 48116
Tel: (313) 227-7067
MINNESOTA
Intel Corp.
8200 Normandale Avenue
Suite 422
Bloomington 55437
Te[: (612) 835-6722
TWX: 910-576-2867
tDytek North
1821 University Ave.
Room 163N
St. Paul 55104
Te[: (612) 645-5816
OREGON
ESIChase Company
4095 SW 144th St.
Bea....erton 97005
Tel: (503)641-4111
PENNSYLVANIA
Inte[ Corp. *
275 Commerce Dr.
200 Office Center
Suite 212
Fort Washington 19034
Tel' (215) 542-9444
TWX 510-661-2077
tLowry & ASSOCiates, Inc.
Seven Parkway Center
SUite 455
Pittsburgh 15520
Tel: (412) 922-5110
to.E.D. Electronics
300 N. York Road
Hatboro 19040
Tel· (215) 874-9600
TENNESSEE
Glen White Associates
Rt. #12, Norwood SID
Jonesboro 37659
Tel: (615) 477-8850
Glen White Associates
2523 Howard Road
Germantown 38138
Tel: (901) 754-0483
Glen White ASSOCiates
6446 Ridge Lake Road
Hixon 37343
Tel: (615) 842-7799
TEXAS
Intel Corp.·
2925 L.B.J. Freeway
Suite 175
Dallas 75234
Tel: (214) 241-9521
TWX: 910-860-5487
Inte[ Corp. *
6776 S.W. Freeway
Suite 550
Houston 77074
Tel: (713) 784-3400
Mycrosystems Marketing Inc.
13777 N. Central Expresswav
Suite 405
Dallas 75243
Tel: (214) 238-7157
TWX: 910-867-4763
Mycrosystems Marketing Inc.
6610 Harwin Avenue, Suite 125
Houston 77036
Tel: (713) 783-2900
UTAH
lWestek
3788 Brockbank Drive
Salt Lake City 84117
Tel: (801) 278-6920
VIRGINIA
Glen White ASSOCiates
P.O. Box 1104
Lynchburg 24505
Tel: (804) 384-6920
Glen White Associates
Rt. #1, Box 322
Colonial Beach 22443
Tel. (804) 224-4871
WASHINGTON
Intel Corp.
300 120th Avenue N.E.
Bldg. 2, Suite 202
Bellevue 98005
Tel: (206) 453-8086
E.S./Chase Co.
P.O. Box 80903
Seattle 98198
Tel: (206) 762-4824
TWX· 910-444-2298
WISCONSIN
Intel Corp.
4369 S. Howell Ave.
Milwaukee 53207
Tel: (414) 747-0789
CANADA
Intel Corp.
Suite 233, Bell Mews
39 Highway 7, Bell Corners
Ottawa, Ontario K2H 8R2
Tel. (613) 829-9714
TELEX: 053-4419
Multllek, Inc.·
15 Grenfell Crescent
Ottawa, Ontario K2G OG3
Tel: (613) 226-2365
TELEX: 053-4585
*Field application location
~These representati .... es do not offer Intel Components,
only boa~ds and systems.
2-17
INTERNATIONAL SALES AND MARKETING OFFICES
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8080
TWX: 910-338-0026
TELEX: 34-6372
EUROPEAN MARKETING OFFICES
BELGIUM
Intel International·
Rue du Moulin It Pepler
51-Bolte 1
B-1160 Brussels
Tel. (02) 660 30 10
TELEX: 24814
FRANCE
Intei Corporation. S.A.R.L.·
5 Place de la Balance
$ili0223
94528 Rungis Cedex
Tel: (01) 687 22 21
TELEX: 270475
ORIENT MARKETING OFFICE
JAPAN
Intei Japan Corporation *
Flower Hill-Shinmachl East Bldg.
1·2:J..9, Shin machi, Setagaya-ku
Tokyo 154
Tel: (03) 426-9261
TELEX: 781-28426
ISRAEL
SCANDINAVIA (conllnuec:l)
Intel Semiconductor Ltd.
P.O. Box 1659
Haifa
Tel: 972/4524261
TELEX: 92248511
Intel Scandinavia
P.O, Box 158
ITALY
Intel Corporation lIalla, S.P.A.
Corso 5empJone 39
1-20145 Milano
Tel: 39 2/34 90 176
TEL.EX: 311271
AlS
N~2040
Klofta, Norway
Tel. 47 2/981068
TELEX: 18018
Intel Scandinavia AlS
P.O. Box 17
SenlnerlkuJa, 3
SF..(I04QO
Helsinki, Finland
Tel: 358 0/55 85 31
TELEX: 123332
NETHERLANDS
Intel Semiconductor Nederland B.V.
Cometongebouw
Westblaak 106
3012 Km Rotterdam
Tel: (10) 149122
TELEX: 22283
SCANDINAVIA
GERMANY
ENGLAND
Intel Denmark A/S·
Lyngbyvej 32 2nd Floor
CK-2100 Copenhagen Easl
Tel: (01) 18 2000
TELEX: 19567
Intel Sweden AB·
Box 20092
Enlghetsvagen,5
5-16120 Bromma
Sweden
Tel: (08) 98 53 90
TELEX: 12281
Intel Corporation (U.K'., Ltd.·
Broadfield House
4 Between Towns Aoad
Cowley. Oxford OX4 3NB
Tei: (0865) 77 14 31
TELEX' 637203
Intel Corporation (U.K.) Ltd
46·50 Beam Street
Nantwich, Cheshire CW5 5LJ
Tel' (0270) 62 65 60
TELEX: 36620
Intel Semiconductor GmbH·
Seidlstrasse 27
8000 Muenchen 2
Tel: (089) 55 8141
TELEX: 523177
Intel Semiconductor GmbH
Abraham Lincoln Strasse 30
6200 Wlesbaden 1
Tel: (06121) 74855
TElEX: 04186183
Intel Semiconductor GmbH
Wernerstrasse 67
P.O. Box 1460
7012 Fellbach
Tel: (0711) 580082
TELEX: 7254826
Intel Semiconductor GmbH
Hlndenburger Strasse 28/29
3000 Hannover
Tel: (0511) 852051
TELEX: 923625
INTERNATIONAL DISTRIBUTORS
ARGENTINA
S I.E SA
Av. Pie. Rogue Saenz Pens 114298
1035 Buenos Aires
Tel 35-6784
AUSTRALIA
A.J.F. Systems & Components
PTY. LTD.
44 Prospect Rd.
Prospect 5082
South Australia 17005
Tel: 269-1244
TELEX: 82535
AJ.F. Systems & Components
PTY. LTD.
29 Devlin St.
Ayde, N.S.W. 2112
Tel. (02) 807..e878
TELEG: 24906
A.J.F. Systems & Components
PTY. LTD.
310 Queen St. Melbourne,
Vlctorta 3000
Tel: (03) 679~702
TELEX: 30270
Warburton·Frankl (Sydney) Pty. Ltd.
199 Parramatta Aoad
Auburn, N.S.W. 2114
Tel. 648-1711, 648-1381
TELEX: WhAFAAN AA 22265
Warburton-Frankl Industries
(Melbourne) Ply, ltd.
220 Park Street
South Melbourne, Victoria 3205
Tel: 699-4999
TELEX: WARFRAN AA 31370
Warburton Frankl, Ply, Ltd.
322 Grange Road, Kidman Perk
South Australia 5025
Tel: 35&-7333
TELEX: WARFRAN AA 92908
Warburton Franki (Perth) Ply, Ltd,
98·102 Belgravla SI., Belmont
Western Australia 6104
Tel. 35S-7000
TELEX: WARFRAN AA 92908
Warburton Frankt (Brisbane) Ply. ltd.
13 Chester 5t" Fortitude Valley
Queensland 400S
'
TELEX.. WARFAAN AA 41052
COLOMBIA
ISRAEL
SINGAPORE
Video National
Dtagonal 34, No. 5-62
Apartado Aereo 27599
Bogota
Tel. 36--37
TELEX: 43439 VINAT
Eastronlcs Lld.11 Aozenis Street
P.O. Box 39330
DENMARK
ITALY
General Engtneers Associates
Blk 3, 1003~1008
P.S.A. Mullt·Story Complex
Telok Blangah/Pasir Panjang
Singapore 5
Tel: 271--31(,3
CABLE: GENEERCORP
Lyngso Komponent A/S
Ostmarken 4
DK-2860 Soborg
Tel' (01) 67 00 77
TELEX. 22990
ScandinaVian Semiconductor
Supply AlS
Nannasgade 18
DK~2200 Copenhagen N
Tel. (01) 83 50 90
TELEX' 19037
FINLAND
Oy Fmtrontc AB
L.oennrolinkalu 350
SF 00180
Helsinki 18
Tel (BO) 601155
TELEX: 123107
Oy Softplan AB
Skillnadsgatan 9A
SF-00130 Helsinki, 13
Tel: 80-644306
TELEX: 12579
Celdis
53, Rue Charles Frerot
94250 Gentlily
Tel: 581 0020-591 0469
TELEX. 200,485 F
Metrologie
La Tour d'Asni~res
4, Avenue Laurent Cely
9260S~Asniere8
Tel: 791 4444
TELEX: 611448 F
Tekelec Airtrontc'
Cite des Bruyeres
Rue Carle Vernet
92310Sevres
Tel' 0) 027 75 35
TELEX: 204552
GERMANY
Bacher Elektronlsche Geraete GmbH
Rote-nmulgasse 2S
A-1120 Vienna
Tel: (0222) 83 63 96
TELEX' (01) 1532
Reklrsch Elektronik Geraete GmbH
Gotlfrted·Keller-Gassa,29
Al030 Vienna
Tel: (222) 734394
TELEX' 74759
Alfred Neye Enatechntk GmbH
Schillerstrasse 14
BELGIUM
BRAZIL
Jeotron S.A
05110-Av. Mulinga 3650
SAndar
Plrituba-Sao Paulo
Tel. 261-0211
TELEX; (011) 2221CO BR
CHILE
Intetlec
P.O. Box 13317
Dr Sotero Del Rio 326
Oficina 903
Santiaqo 1
Tel. 723740
Eledra 3S S.P .A. Vlale Elvezla, 18
20154 Milan,
Tel' (02)3493041
TELEX: 39332
Eledra 3S S.P .A.Via Paolo Gaidano, 141 0
10137 Torino
!
TEL: (011) 30 97 097 ~ 30 ~7114
TELEX: 210632
~::~~u~:p~: ¢a;marana, \)a
~1.3(~~o;;e2it~~~ _ 81 27'324
TELEX. 612051
JAPAN
Tokyo Electron Labs, Inc.
No 1 Higashikata-Machi
Midori·Ku, Yokohama 226
Tel: (045) 471..s811
TELEX: 781-4773
Ryoyo Electric Corp.
Konwa Bldg,
1·12~22, Tsukiji, l-Chome
Chuo-Ku, Tokyo 104
Tal: (03) 543-7711
Nippon Micro Computer Co. Ltd.
Mutsumi Bldg. 4-5~21 Kojimachi
Chlyoda-ku, Tokyo 102
Tel' (03) 230..(1041
FRANCE
AUSTRIA
Inelco Belgium S.A.
Avenue Val Duchesse, 3
B-116O Brussels
Tel' (02) 660 00 12
TELEX: 25441
Tel~Aviv61390
Tel: 475151
TELEX: 33638
D~2065 Qulckborn~Hamburg
KOREA
Korem Digital
Room 411 Ahil Bldg.
49-4 2·GA Hoehyun·Dong
Chung·Ku Seoul
Tel: 23~8123
CABLE: CHEJU 26364
Leewood International, Inc.
C.P.O. Box 4046
112~25, Sokong·Dong
Chung~Ku, Seoul 100
Tel: 26·5927
CABLE: "LEEWOOD" Seoul
NETHERLANDS
Tel' (04106) 6121
TELEX: 02·13590
Electronic 2000 Vertriebs GmbH
Neumarkter Strasse 75
0·8000 Muenchen 80
Tel: (089) 434061
TELEX 522561
Jermyn GmbH
Postfach 1146
0-6277 Kamberg
Tel (06434) 6005
TELEX' 484426
C.N. Rood BV
CorlVender
Lindenstraat,13
Postbus 42
RiiswiJk 2280 AA
Tel 070-996360
TELEX: 31238
Inelco Nederland
AFO Elektronlc
Joan Muyskenweg 22
NL~1006 Amsterdam
Tel' (020) 934824
TELEX: 14622
HONG KONG
NEW ZEALAND
China Electronics
Sea Bird House, 9th Floor
22-28 Wyndham Street
Hong Kong
Tel: 520687
W. K. McLean Ltd.
103-5 Felton Matthew Avenue
Glenn Innes, Auckland, 6
Tel: 587..(137
TELEX. NZ2783 KOSFY
INDIA
NORWAY
Micro Electronics International
10~2~289/114A
Shantlnager
Hyderabad 500028
CABLE: MELECTRO·HYDERBAD
Norclisk Elektronik (Norge)
MustadsVell
N·Oslo 2
Tel' (02) 55 38 93
TELEX: 16963
AlS
SOUTH AFRICA
Electronic Building Elements
P.O. Box 4609
Pretoria
Tel: 789221
TELEX: 30161
SPAIN
Interlace·
Ronda San Pedro 22
Barcelona 10
Tel 3017851
TELEX: 51508 IFCE E
iTT SESA
Miguel Angel 16
Madrid 10
Tel: (1) 410 2354
TELEX: 27707
SWEDEN
Nordlsk Elactronik Ad
Sandhamnsgalan 71
S-102 54 Stockholm
Tel: (08) 635040
TELEX. 10547
SWITZERLAND
Industrade AG
Gemsenstrasse 2
Postcheck 80·21190
CH-8021 Zurich
Tel. (01) 602230
TELEX: 56788
TAIWAN
Taiwan Automation Co.·
2nd Floor, 224
Nanking East Road
Section 3
Taipei
Tel: (02) 7710940-3
TELEX: 11942 TAIAUTO
UNITED KINGDOM
G.E.C. SemicondUctors Ltd
East Lane
NorthWembly
Middlesex HAg 7PP
Tei: (01) 904-9303
TELEX: 923429
Jermyn Industries
Vestry Estate
Seven oaks. Kent
Tel: (0732) 51174
TELEX: 95142
Stntrom Electronics Ltd.Arkwrl9ht Road
Reading, BerkShire RG2 OLS
Tel' (0734) 85464
TELEX: 847395
Rapid Recall, Ltd.
8 Soho Mills Ind. Park
Woburn Green
Bucks, England
Tel: Boumd End 24961
TELEX. 849439
VENEZUELA
Componentes y Clrcultos
Electronicas TTLCA C.A.
Apartado 3223
Caracas 101
Tel: 35-5591
TELEX: TAMER 24157
PORTUGAL
Ditram
Componentes E Electronlca LOA
A.v. Migual Bombarda, 133
Llsboa 1
Tel: 11945313
2-18
·Field Application Location
inter
U.S. AND CANADIAN DISTRIBUTORS
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8080
TWX: 910-338-0026
TELEX: 34-6372
ALABAMA
tHamiiton/ Avnet Electronics
805 Oser Drive NW
Huntsville 35805
Tel: (205) 837-7210
Pioneer
1207 Putman Drive NW
Huntsville 35805
Tel: (205) 837-9300
ARIZONA
tHamilton/ Avnet Electronics
2615 South 21 st Street
Phoenix 85034
Tel: (602) 275-7851
tLiberty/ Arizona
8155 N. 24th Avenue
Phoenix 85021
Tel: (602) 249-2232
TELEX: 910-951-4282
CALIFORNIA
tAvnet Electronics
350 McCormick Avenue
Costa Mesa 92626
Tel: (714) 754-6111
tHamilton/ Avnet Electronics
575 E. Middlefield Road
Mountain View 94040
Tel: (415) 961-8600
tHamilton/ Avnet Electronics
8917 Complex Drive
San Diego 92123
Tel: (714) 279-2421
tHamiiton Electro Sales
10912 W. Washington Boulevard
Culver City 90230
Tel: (213) 558-2121
tLiberty Electronics
124 Maryland Street
EI Segundo 90245
Tel: (213) 322-5059
TWX: 910-348-7140
tLiberty/San Diego
8284 Mercury Court
San Diego 92111
Tel: (714) 565-9171
TELEX: 910-335-1590
tEl mar Electronics
2288 Charleston Road
Mountain View 94040
Tel: (415) 961-3611
TELEX: 910-379-6437
COLORADO
tElmar/Denver
6777 E. 50th Avenue
Commerce City 80022
Tel: (303) 287-9611
TWX: 910-936-0770
tHamilton/ Avnet Electronics
5921 No. Broadway
Denver 80216
Tel: (303) 534-1212
CONNECTICUT
tCramer/Connecticut
12 Beaumont Road
Wallingford 06492
Tel: (203)265-7741
tHamiiton/ Avnet Electronics
643 Danbury Road
Georgetown 06829
Tel: (203) 762-0361
tHarvey Electronics
112 Main Street
Norwalk 06851
Tel: (203) 853-1515
FLORIDA
Arrow Electronics
1001 N.W. 62nd Street
Suite 402
Ft. Lauderdale 33309
Tel: (305) 776-7790
Arrow Electronics
115 Palm Bay Road, NW
Suite 10
Palm Bay 32905
Tel: (305) 725-1480
tHamiiton/ Avnet Electronics
6800 Northwest 20th Ave.
Ft. Lauderdale 33309
Tel: (305) 971-2900
jPioneer
6220 S. Orange Blossom Trail
Suite 412
Orlando 32809
Tel: (305) 859-3600
Hamilton/Avnet
3197 Tech. Drive N.
St. Petersburg 33702
Tel: (813) 576-3930
GEORGIA
Arrow Electronics
3406 Oak Cliff Road
Doraville 30340
Tel: (404) 455-4054
tHamiiton/ Avnet Electronics
6700 I 85, Access Road, #11
Norcross 30071
Tel: (404) 448-0800
ILLINOIS
tCramer/Chicago
1911 So. Busse Rd.
Mt. Prospect 60056
Tel: (312) 593-8230
tHamiiton/ Avnet Electronics
3901 No. 25th Ave.
Schiller Park 60176
Tel: (317) 849-7300
Pioneer/Chicago
1551 Carmen Drive
Elk Grove Village 60006
Tel: (312) 437-9680
INDIANA
tPioneer /1 ndiana
6408 Caslleplace Drive
Indianapolis 46250
Tel: (317) 849-7300
Sheridan Sales
8790 Purdue Road
Indianapolis 46268
Tel: (317) 297-3146
KANSAS
tHamilton/ Avnet Electronics
9219 Quivira Road
Overland Park 66215
Tel: (913) 888-8900
MARYLAND
tHamilton Avnet
7235 Standard Drive
Hanover 21076
Tel: (301) 796-5684
tPioneer/Washington
9100 Gaither Road
Gaithersburg 20760
Tel: (301) 948-0710
TWX: 710-828-0545
MASSACHUSETTS
ICramer Electronics Inc.
85 Wells Avenue
Newton 02159
Tel: (617) 969-7700
MASSACHUSETTS (continued)
tHamilton/ Avnet Electronics
100 E. Commerce Way
Woburn 01801
Tel: (617) 933-8000
MICHIGAN
tSheridan Sales Co.
24543 Indoplex Circle
Farmington Hills 48024
Tel: (313) 477-3800
IPioneer/Michlgan
13485 Stamford
Livonia 48150
Tel: (313) 525-1800
tHamilton/ Avnet Electronics
32487 Schoolcraft Road
Livonia 48150
Tel: (313) 522-4700
TWX: 810-242-8775
MINNESOTA
Iindustrial Components
5280 West 74th Street
Minneapolis 55435
Tel: (612) 831-2666
tCramer/Bonn
5424 Edina Industrial Blvd.
Edina 55435
Tel: (612) 835-7811
tHamilton/ Avnet Electronics
7683 Washington Avenue So.
Edina 55435
Tel: (612) 941-3801
MISSOURI
tHamilton/ Avnet Electronics
364 Brookes Drive
Hazelwood 63042
Tel: (314) 731-1144
Sheridan Sales
220 S. Hwy 67, Suite 10
Florissant 63031
Tel: (314) 837-5200
NEW JERSEY
Arrow Electronics
Pleasant Valley Avenue
Moorestown 08057
Tel: (215) 928-1800
Arrow Electronics
285 Midland Avenue
Saddlebrook 07662
Tel: (201) 797-5800
tHamilton/ Avnet Electronics
218 Little Falls Road
Cedar Grove 07009
Tel: (201) 239-0800
TWX: 710-994-5787
tHarvey Electrooics
389 Passaic Avenue
Fai rfield 07006
Tel: (201) 227-1262
tHamiiton/ Avnet Electronics
113 Gaither Drive
East Gate Industrial Park
Mt. Laurel 08057
Tel: (609) 234-1233
TWX: 710-897-1405
NEW MEXICO
Alliance Electronics Inc.
11728 Linn Ave., N.E.
Albuquerque 87123
Tel: (505) 292-3360
tHamilton/ Avnet Electronics
2524 Baylor Drive, S.E.
Albuquerque 87119
Tel: (505) 765-1500
tMicrocomputer System Technical Demonstrator Centers
'Microcomputer Systems Spares Order Point
2-19
U.S. AND CANADIAN DISTRIBUTORS
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8080
TWX: 910-338-0026
TELEX: 34-6372
NEW YORK
Harvey Electronics
P.O. Box 1208
Binghampton 13902
Tel: (607) 748-8211
Arrow Electronics
900 Broad Hollow Road
Farmingdale 11735
Tel: (516) 694-6800
tCramer/Rochester
3000 South Winton Road
Rochester 14623
Tel: (716) 275-0300
tHamiiton/Avnet Electronics
167 Clay Road
Rochester 14623
Tel: (716) 442-7820
tCramer/Syracuse
6716 Joy Road
East Syracuse 13057
Tel: (315) 437-6671
tHamilton/ Avnet Electronics
6500 Joy Road
E. Syracuse 13057
Tel: (315) 437-2641
tHamilton/Avnet Electronics
70 State Street
Westbury, L.I.11590
Tel: (516) 333-5800
TWX: 510-222-8237
tHarvey Electronics
60 Crossways Park West
Woodbury 11797
Tel: (516) 921-8700
NORTH CAROLINA
Pioneer/Carolina
2906 Baltic Avenue
Greensboro 27406
Tel: (919) 273-4441
TWX: 510-925-1114
tHamilton/Avnet Electronics
2803 Industrial Drive
Raleigh 27609
Tel: (919) 829-8030
Arrow Electronics
1377-G S. Park Drive
Kernersville 27284
Tel: (919) 996-2039
OHIO
tSheridan Sales Co.
2501 Neff Road
Dayton 45414
Tel: (513) 223-3332
Sheridan Sales Co.
23224 Commerce Park Road
Beachwood 44122
Tel: (216) 831-0130
tHamiiton/Avnet Electronics
954 Senate Drive
Dayton 45459
Tel: (513) 433-0610
TWX: 810-450-2531
tPloneer/Dayton
1900 Troy Street
Dayton 45404
Tel: (513) 236-9900
!Sherldan Sales Co.
P.O. Box 37856
Cincinnati 45222
Tel: (513) 761-5432
TWX: 810-461-2670
!Pioneer/Cleveland
4800 E. 131st Street
Cleveland 44105
Tel: (216) 587-3600
tHamiiton/ Avnet Electronics
761 Beta Drive, Suite E
Cleveland 44143
Tel: (216) 461-1400
OHIO (continued)
tSheridan Sales Co.
701 Beta Drive
Mayfieldville 44143
Tel: (216) 461-3300
WASHINGTON (continued)
tLiberty Electronics
1750 132nd Avenue NE
Bellevue 98005
Tel: (206) 763-8300
OKLAHOMA
tComponents Specialties, Inc.
7920 E. 40th Street
Tulsa 74145
Tel: (918) 664-2820
OREGON
tAlmac/Stroum Electronics
4475 S.W. Scholls Ferry Rd.
Portland 97225
Tel: (503) 292-3534
WISCONSIN
Arrow Electronics
434 W. Rawson Avenue
Oak Creek 53154
Tel: (414) 764-6600
tHamiiton/ Avnet
2975 Moorland Road
New Berlin 53151
Tel: (414) 784-4510
PENNSYLVANIA
tSheridan Sales Co.
4297 Greensburgh Pike, Suite 3114
Pittsburgh 15221
Tel: (412) 351-4000
Pioneer/Pittsburgh
560 Alpha Drive
Pittsburgh 15238
Tel: (412) 782-2300
Pioneer/Delaware Valley
141 Gibraltar Road
Horsham 19044
Tel: (215) 674-4000
TWX: 510-665-6778
TENNESSEE
tSheridan Sales Co.
6900 Office Park Circle
Knoxville 37919
Tel: (615) 588-5836
TEXAS
Component Specialties Inc.
8330 Burnett Road, Suite 101
Austin 78758
Tel: (512) 459-3308
tCramer Electronics
13740 Midway Road
Dallas 75240
Tel: (214) 661-9300
tHamilton/ Avnet Electronics
4445 Sigma Road
Dallas 75240
Tel: (214) 661-9300
tHamilton/Avnet Electronics
3939 Ann Arbor
Houston 77063
Tel: (713) 780-1771
tComponent Specialties, Inc.
10907 Shady Trail, Suite 101
Dallas 75220
Tel: (214) 357-6511
tComponent Specialties, Inc.
8585 Commerce Park Drive, Suite 590
Houston 77036
Tel: (713) 771-7237
UTAH
tHamiiton/ Avnet Electronics
1585 West 2100 South
Salt Lake City, 84119
Tel: (801) 972-2800
WASHINGTON
tHamliton/Avnet Electronics
14212 N.E. 21st
Bellevue 98005
Tel: (206) 746-8750
!Almac/Stroum Electronics
5811 Sixth Ave. South
Seattle 98108
Tel: (206) 763-2300
2-20
CANADA
ALBERTA
tL. A. Varah Ltd.
4742 14th Street N.E.
Calgary T2E 6L7
Tel: (403) 276-8818
Telex: 138258977
BRITISH COLUMBIA
! L.A. Varah Ltd.
2077 Alberta Street
Vancouver V5Y lC4
Tel: (604) 873-321/
TWX: 610-929-1068
Telex: 04 53167
Zentronics
8325 Fraser Street
Vancouver V5X 3X8
Tel: (604) 325-3292
Telex: 04-5077-89
MANITOBA
L. A. Varah
1-1832 King Edward Street
Winnipeg R2R ONI
Tel: (204) 633-6190
ONTARIO
tL.A. Varah, Ltd.
505 Kenora Avenue
Hamilton L8E-3P2
Tel: (416) 561-9311
TELEX: 061-8349
tHamilton/Avnet Electronics
3688 Nashua Drive, Units G & H
Mississauga L4V IM5
Tel: (416) 677-7432
TWX: 610-492-8867
tHamiiton/Avnet Electronics
1735 Courtwood Cresco
Ottawa K2C 3J2
Tel: (613) 226-1700
TWX: 610 562-1906
tZentronics
141 Catherine Street
Ottawa, Ontario K2P lC3
Tel: (613) 238-6411
tZentronics
99 Norfinch Dr.
Downsview, Ontario M3N lW8
Tel: (416) 635-2822
Telex: 02-021694
QUEBEC
tHamilton/ Avnet Electronics
2670 Paulus Street
St. Laurent H4S lG2.
Tel: (514) 331-6443
TWX: 610-421-3731
Zentronics
8146 Montview Road
Town of Mt. Royal
Montreal H4P 2L7
tMicrocomputer System Technical Demonstrator Centers
"Microcomputer System Spares Order Point
Random Access
Memory
3
RANDOM ACCESS MEMORIES
Electrical Characteristics Over Temperature
Power
Type
No.
of
Bits
No.
Description
Organl-
01
zatio"
Pins
Access
Time
Cycle
Time
Dissipation
Max,!'1
Max.
(ns)
Min.
(ns)
Operalingl
Standby (mW)
Supplies (V)
Page
No.
DYNAMIC RAMS
4096
16-Pin Dynamic
4096xl
16
350
350
441/25
+12. +5,-5
2104A-l
4096
16·Pin Dynamic
4096xl
16
150
320
462/26
+12, +5, -5
2104A-2
4096
16-Pin Dynamic
4096xl
16
200
375
422/26
+12, +5,-5
2104A-3
4096
16-Pin Dynamic
4096xl
16
250
375
396/26
+12, +5,-5
2104A
2104A-4
4096
16-Pin Dynamic
4096xl
16
300
425
396/26
+12, +5.-5
4096
22-Pin Dynamic
4096xl
22
250
430
396/2.6
+12, +5,-5
2107C-l
4096
22-Pin Dynamic
4096xl
22
150
380
462/2.6
+12, +5,-5
2107C-2
4096
22-Pin Dynamic
4096xl
22
200
400
436/2.6
+12, +5,-5
2107C
2107C-4
2109-3
2109-4
22-Pin Dynamic
4096xl
22
300
470
396/2.6
+12, +5, -5
16-Pin Dynamic
8192xl
16
200
375
462/20
+12, +5,-5
8192
16-Pin Dynamic
8192xl
16
250
410
436/20
+12, +5,-5
16,384
16-Pin Dynamic
16,384xl
16
150
320
462/20
+12, +5, -5
2117-3
16,384
16-Pin Dynamic
16,384xl
16
200
375
462/20
+12, +5,-5
2117-4
16,384
16-Pin Dynamic
16,384xl
16
250
410
436/20
+12, +5,-5
2117-2
2117-5
16,384
16-Pin Dynamic
16,384xl
16
300
490
462/20
+12, +5, -5
16,384
16-Pin Dynamic
16,384xl
16
80
200
160/16.5
+5
2118-3
16,384
16-Pin Dynamic
16,384xl
16
100
235
138/16.5
+5
2118-4
16,384
16-Pin Dynamic
16,384xl
16
120
270
121/16.5
+5
2118-7
16,384
16-Pin Dynamic
16,384xl
16
150
320
121/16.5
+5
2118-2
Cf.I
4096
8192
c:>
21 01A18101A
1024
Static, Separate liD
256x4
22
350
350
300
+5
CD
2101A-2
1024
Static, Separate 110
256x4
22
250
250
350
+5
z
2101A-4
1024
Static, Separate liD
256x4
22
450
450
300
+5
+5
~
C
c:>
3-28
3-33
3-64
3-88
STATIC RAMS
IE
...z
3-12
3-4
(.)
:::::i
c;,;
1024
Static
1024xl
16
350
350
275
2102A-2
1024
Static
1024xl
16
250
250
325
+5
2102A-4
1024
Static
1024xl
16
450
450
275
+5
2102AL
1024
Low Standby Power Static
1024xl
16
350
350
165/35
+5
+5
21 02A181 02A
2102AL-2
1024
Low Standby Power Static
1024xl
16
250
250
325/42
2102AL-4
1024
Low Standby Power Static
1024xl
1~
450
450
165/35
+5
1024
Static, Common 110 with
256x4
18
350
350
300
+5
2111A-2
1024
Static, Common I/O
256x4
18
250
250
350
+5
2111A-4
1024
Static, Common I/O
256x4
18
450
450
300
+5
1024
Static, Common liD without
Output Deselect
256x4
16
350
350
300
+5
2112A-2
1024
Static, Common 110 without
Output Deselect
256x4
16
250
250
350
+5
2112A-4
1024
Static, Common liD without
Output Deselect
256x4
16
450
450
300
+5
+5
2111A18111A
3-8
Output Deselect
2112A
4096
Static, Common liD
1024x4
18
450
450
525
2114-2
4096
Static, Common I/O
1024x4
18
200
200
525
+5
2114-3
4096
Static, Common 110
1024x4
18
30'0
300
525
+5
2114L
4096
Static, Common I/O
1024x4
18
450
450
370
+5
2114L2
4096
Static, Common liD
1024x4
18
200
200
370
+5
2114L3
4096
Static, Common liD
1024x4
18
300
300
370
+5
2114
3-2
3-45
3-49
3-54
RANDOM ACCESS MEMORIES (Cont.)
Electrical Characteristics Over Temperature
Access
Type
No.
01
Blls
Organl-
zallon
Description
No.
01
Pins
Power
Dissipation
Cycle
Time
Min.
(ns)
Operatingl
Standby (mW)
Supplies (V)
Page
No.
450
450
550
+5
14-7
Time
Ma•.
(ns)
Ma •• ll1
STATIC RAMS (Continued)
M2114
4096
Static. Common 1/0 TA
-55'C to +125'C
2115A
High Speed Static. Open Collector
1024x1
16
45
45
655
+5
1024
High Speed Static. Open Collector
1024x1
16
70
70
655
+5
2115AL
1024
High Speed Static. Open Collector
1024x1
16
45
45
395
+5
2115AL-2
1024
High Speed Static. Open Collector
1024x1
16
70
70
395
+5
1024
High Speed Static. Three State
1024x1
16
45
45
655
+5
2125A-2
1024
High Speed Static. Three State
1024x1
16
70
70
655
+5
2125AL
1024
High Speed Static. Three State
1024x1
16
45
45
395
+5
2125AL-2
1024
High Speed Static, Three State
1024x1
16
70
70
395
+5
1024
High Speed Static. Open Collector
1024x1
16
55
55
690
+5
1024
High Speed Static. Open Collector
1024x1
16
75
75
415
+5
1024
High Speed Static, Three State
1024x1
16
55
55
690
+5
1024
High Speed Static, Three State
(-55'C to 125'CI
1024x1
16
75
75
415
+5
14-11
M2115AL
M2125A
M2125AL
,..
~
18
1024
M2115A
m
::E
:z
1024x4
2115A-2
2125A
CI
=
1024
High Speed Static, Open Collector
1024x1
16
25-35
25-35
655
+5
3-63
1024
High Speed Static, Three State
1024x1
16
25-35
25-35
655
+5
3-63
2141-2
4096
Static
4096x1
18
120
120
385/110
+5
2141-3
4096
Static
4096x1
18
150
150
385/110
+5
:z
2141-4
4096
Static
4096x1
18
200
200
303/66
+5
2141-5
4096
Static
4096x1
18
250
250
303/66
+5
2141L-3
4096
Static
4096x1
18
150
150
220/28
+5
2141L-4
4096
Static
4096x1
18
200
200
220/28
+5
2141L-5
4096
Static
4096x1
18
250
250
220/28
+5
4096
Static, with Output Enable
1024x4
20
450
450
525
+5
2142-2
4096
Static, with Output Enable
1024x4
20
200
200
525
+5
2142-3
4096
Static, with Output Enable
1024x4
20
300
300
525
+5
2142L
4096
Static, with Output Enable
1024x4
20
450
450
375
+5
2142L-2
4096
Static, with Output Enable
1024x4
20
200
200
375
+5
2142L-3
4096
Static, with Output Enable
1024x4
20
300
300
375
+5
4096
High Speed Static
,
4096x1
18
70
70
880/110
+5
2147-3
4096
High Speed Static
4096x1
18
55
55
990/165
+5
2147L
4096
High Speed Static
4096x1
18
70
70
770/55
+5
(.)
2142
2147
1>=
..:a:::
~e
~
.....
High Speed Static
4096xl
18
35-45
35-45
990/165
+5
3-105
4096
High Speed Static(-55°C to 125°CI
4096xl
18
85
85
990/165
+5
14-15
2148
4096
High Speed Static
1024x4
18
60
60
825/165
+5
3-106
3101
64
Fully Decoded
16x4
16
60
60
525
+5
64
High Speed Fully Decoded
16x4
16
35
35
525
+5
3-107
3101A
Static CMOS RAM
256x4
22
800
800
150/2.5
+5
1024
Static CMOS RAM
256x4
22
650
650
135/20"W
+5
5101L-l
1024
Static CMOS RAM
256x4
22
450
450
135/20"W
+5
CI::E
5101L-3
1024
Static CMOS RAM
256x4
22 .
650
650
135/1
+5
:::::;,..
M5101-4
1024
Static CMOS RAM
(-55°C to 125°C)
256x4
22
800
800
168/1
+5
1024
Static CMOS RAM
(-55°C to 125°C)
256x4
22
800
800
168/400"W
+5
(.)(.)
-~
me
3-99
4096
1024
:zCl
3-95
2147H
5101L
m
3-89
M2147
CICI
z ...
~iii
I---'
14-11
2115H
CD
CI
3-58
2125H
e
:::::;
0
3-58
5101
CD
M5101L-4
3-111
14-41
3-3
2101A/8101A-4*
256 X 4 BIT STATIC RAM
2101A-2
2101A
2101A-4
250 ns Max.
350 ns Max.
450 ns Max.
• 256 x 4 Organization to Meet Needs for
Small Syst,m Memories
• Single +5V Supply Voltage
• Directly TTL Compatible: All Inputs and
Output
• Statis MOS: No Clocks or Refreshing
Required
• Simple Memory Expansion: Chip Enable
Input
• Inputs Protected: All Inputs Have Protection Against Static Charge
• Low Cost Packaging: 22 Pin Plastic Dual
In-Line Configuration
• Low Power: Typically 150 mW
• Three-State Output: OR-Tie Capability
• Output Disable Provided for Ease of Use
in Common Data Bus Systems
The Intel@ 2101A is a 256 word by 4-bit static random access memory element using N-channel MOS devices integrated on a
monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is
read out nondestructively and has the same polarity as the input data.
The 2101 A is designed for memory applications where high performance, low cost, large bit storage, .and simple interfacing are
important design objectives.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. Two chip-enables allow easy selection of
an individual package when outputs are OR-tied. An output disable is provided so that data inputs and outputs can be tied for
common I/O systems. The output disable function eliminates the need for bi-directional logic in a common I/O system.
The Intel@ 2101A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.
Intel's silicon gate technology also provides el(cellent protection against contamination. This permits the use of low cost
plastic packaging.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
Ao
vee
22
A,
21
A2
A.
A,
A2
A,
20
WE
Ao
19
CE,
As
As
18
00
A,
17
CE2
As
A7
16
D0.
GND
15
DI.
01,
14
DO,
DO,
10
13
01,
01 2
11
12
0°2
.,
Ao
A,
DO,
'2
.
0°2
A3
A.
A7
DO,
D0.
01,
01,
01 2
00
012
01,
01,
01.
01.
®
®
~vcc
®
----0
®
CD
ROW
SELECT
MEMORY ARRAY
32 ROWS
32 COLUMNS
@
®
@
®
INPUT
DATA
CONTROL
@!
PIN NAMES
01,-01 4
Y,.
DATA INPUT
ADDRESS INPUTS·
WE
WRITE ENABLE
CE,
CHIP ENABLE 1
CE 2
00
CHIP ENABLE 2
o
OUTPUT DISABLE
00,-0°4 DATA OUTPUT
Vee
POWER 1+5VI
*AII 8101A-4 specs are identical to the 2101A-4 specs.
3-4
= PIN NUMBERS
GNO
2101A FAMILY
'COMMENT:
ABSOLUTE MAXIMUM RATINGS*
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Under Bias ..... _lOoC to BO°C
Storage Temperature . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground. . . . . . . ..
-0.5V to +7V
Power Dissipation .. . . . . . . . . . . . . . . . . ..
1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A ~ O°C to 70°C, Vee ~ 5V ±5% unless otherwise specified.
Symbol
Parameter
Min.
Typ.[ll
Max.
Unit
Test Conditions
~
0 to 5.25V
III
I nput Current
1
10
fJA
VIN
ILOH
Data Output Leakage Current
1
10
fJA
Output Disabled, VOUT~4.0V
ILOL
Data Output Leakage Current
-1
-10
fJA
Output Disabled, VouT~0.45 V
lec1
Power Supply
Current
2101A.2101A-4
2101A-2
55
mA
Power Supply
2101A,2101A-4
2101A-2
lec2
Current
35
45
65
60
VIN
~
5.25V, 10
mA
70
V IL
Input "Low" Voltage
-0.5
+O.B
V
VIH
Input "High" Voltage
2.0
V
VOL
Output "Low" Voltage
Vcc
+0.45
VO H
Output "High"
Voltage
-
V
10L ~ 2.0mA
2.4
V
10H - -200fJA
2101A-4
2.4
V
10H ~ -150fJA
TYPICAL D.C. CHARACTERISTICS
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
AMBI~NT TE MPER1TURE
1
-15
«
.°
-10
E
5
0
\~
,----
25°C
70°C
\~
1\\
'\
vee'" 4.75V
'\..iUTPUi "H1Gr" TY!ICAL
~
VOH (VOL lS)
VOL (VOL lS)
NOTES: 1. Typical values are for T A = 25° e and nominal supply voltage.
3-5
OmA
VIN ~ 5.25V, 10 ~ OmA
TA ~ O°C
2101A,2101A-2
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
~
TA~25°C
2101A FAMILY
A.C. CHARACTERISTICS FOR 2101A-2 (250 ns ACCESS TIME)
READ CYCLE
T A = O°C to 70°C, VCC = 5V ±5%, unless otherwise specified.
Symbol
Parameter
T
Min.
[1]
yp.
Max.
Unit
Test Conditions
tRC
Read Cycle
tA
Access Time
250
ns
tco
Chip Enable To Output
180
ns
Input Levels = 0.8V or 2.0V
too
tOF[3]
Output Disable To Output
130
ns
Timing Reference = 1.5V
180
ns
Load = 1 TTL Gate
and CL = 100pF.
tOH
250
Data Output to High Z State
0
Previous Read Data Valid
after change of Address
40
ns
ns
t r , tf = 20ns
WRITE CYCLE
Symbol
Parameter
twc
Write Cycle
T yp.[1]
Min.
Max.
Unit
170
ns
Test Conditions
tAW
Write Delay
20
ns
tcw
Chip Enable To Write
150
ns
t r , tf = 20ns
Input Levels = 0.8V or 2.0V
tow
Data Setup
150
ns
Timing Reference = 1.5V
tOH
twp
Data Hold
0
ns
Load = 1 TTL Gate
Write Pulse
150
ns
tWR
tos
Write Recovery
Output Disable Setup
0
20
ns
ns
CAPACITANCE
Symbol
CIN
GoUT
and CL = 100pF.
[21
TA = 25°C, f = 1 MHz
Limits (pF)
Test
Typ)11
Max.
Input Capacitance
(All Input Pins) VIN = OV
4
8
Output Capacitance VO UT = OV
8
12
WAVEFORMS
WRITE CYCLE
READ CYCLE
1------
t RC
I.-------twc------~I
-------1
ADDRESS
ADDRESS
I.----tcw----I
--tco
eEl
IT;
eE'
eE'
t co - _
I----tcw----l
OD------'
(COMMON I/O} (4)
aD
t OH -
--
(COMMON I/O) [41
'os
DATA
DATA
OUT
IN
---,-~
NOTES:
1. Typical values are for TA = 25° C and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3. tOF is with respect to the trailing edge of CEl. CE2.
or 00, whichever occurs first.
3·6
-tDH--
----twp---_I
,.""";';;';"'_1-_
4. 00 should be tied low for separate I/O operation.
2101A FAMILY
2101A (350 ns ACCESS TIME)
A.C. CHARACTERISTICS
READ CYCLE
Symbol
TA ~ O°C to 70°C. VCC ~ 5V ±5%. unless otherwise specified.
tco
Parameter
Read Cycle
Access Time
Chip Enable To Output
too
tOF [2)
Output 0 isable To Output
Data Output to High Z State
tOH
Previous Read Data Valid
after change of Address
tRC
tA
Min.
Typ.[11
Max.
350
ns
ns
Test Conditions
ns
t r • tf ~ 20ns
Input Levels = O.BV or 2.0V
180
ns
Timing Reference
150
ns
Load
350
240
0
Unit
~
~
1.5V
1 TTL Gate
and CL
~
100pF.
ns
40
WRITE CYCLE
Symbol
twc
tAW
tcw
tow
tOH
twp
Parameter
Write Cycle
Write Delay
Min.
Typ.[11
Max.
Unit
220
ns
20
Test Conditions
t r • tf
Chip Enable To Write
Data Setup
200
ns
ns
200
ns
Input Levels = O.BV or 2.0V
Timing Reference ~ 1.5V
Data Hold
0
200
ns
Load
tWR
Write Pulse
Write Recovery
tos
Output Disable Setup
0
ns
ns
20
ns
~
~
20ns
1 TTL Gate
and C L ~ 100pF.
2101A-4 (450 ns ACCESS TIME)
A.C. CHARACTERISTICS
READ CYCLE
Symbol
TA ~ O°C to 70°C. Vcc ~ 5V ±5%. unless otherwise specified.
Parameter
Read Cycle
tRC
tA
Access Time
tco
too
tOF [2)
Chip Enable To Output
Output Disable To Output
Data Output to High Z State
tOH
Previous Read Data Valid
after change of Address
Min.
T yp.[11
Max.
450
450
310
250
200
0
Unit
Test Conditions
ns
ns
t r • tf·~ 20ns
ns
ns
ns
Input Levels ~ O.BV or 2.0V
Timing Reference ~ 1.5V
Load ~ 1 TTL Gate
and C L ~ 100pF.
ns
40
WRITE CYCLE
Symbol
Parameter
Min.
Typ.[11
Max.
Unit
Test Conditions
twc
Write Cycle
270
ns
20
250
ns
t r • tf
ns
ns
Input Levels = O.BV or 2.0 V
Timing Reference ~ 1.5V
ns
Load
tAW
Write Delay
tcw
tow
Chip Enable To Write
Data Setup
tOH
twp
Data Hold
Write Pulse
tWR
Write Recovery
tos
Output Disable Setup
250
0
250
0
ns
ns
20
ns
NOTES: 1. Typical values are for TA = 25° C and nominal supply voltage.
2. tOF i. with respect to the trailing edga of CE1. CE2. or 00. whichever occurs first.
3-7
~
~
20ns
1 TTL Gate
and CL
~
100pF.
inter
2102A, 2102AL/8102A-4*
1K x 1 BIT STATIC RAM
PIN
2102AL-4
2102AL
2102AL-2
2102A-2
2102A
2102A-4
Operating Pwr.
(mW)
174
174
342
342
289
289
Standby Pwr.
(mW)
35
35
42
--
---
Access
(ns)
450
350
250
250
350
450
• Inputs Protected: All Inputs
Have Protection Against Static
Charge
• Low Cost Packaging: 16 Pin
Dual-In-Line Configuration
• Single +5 Volts Supply Voltage
• Directly TTL Compatible: All
Inputs and Output
• Standby Power Mode (2102AL)
• Three-State Output: OR-Tie
Capability
)
The Intel® 2102A is a high speed 1024 word by one bit static random access memory element using N-channel MOS devices
integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to
operate. The data is read out nondestructively and has the same polarity as the input data.
The 2102A is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing are
important design objectives. A low standby power version (2102AL) is also available. It has al/ the same operating
characteristics of the 21 02A with the added feature of 35m W maximum power dissipation in standby and 174m W in operations.
It is directly TTL compatible in all respects: inputs, output, and a single +5 volt supply. A separate chip enable (CE) lead allows
easy selection of an individual package when outputs are OR-tied.
The Intel® 2102A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance easy to use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.
PIN
CONFIGURATION
LOGIC SYMBOL
A,
A,
Au
A5
A,
R/W
A,
A,
CE
A,
A,
A3
A,
A,
DATA OUT
Ao
A3
DATA IN
A,
Vee
Au
GND
r
H
L
PIN NAMES
D'N
A,
A, DOUT
A,
A,
R/W
BLOCK DIAGRAM
D'N
DATA INPUT
Ao·A g
ADDRESS INPUTS
R/W
REAO/WRITE INPUT
CE
CHIP ENABLE
DOUT
DATA OUTPUT
Vee
POWER (+5V)
CELL
ARRAY
3/~OR~uW':NS
CE
OATA
0"'
TRUTH TABLE
,.-O'N
X
X
L
L
L
H
L
H
X
L
MODE
HIGH Z
L
NOT SELECTED
WRITE "0"
WRITE "1"
0= PIN NUMBERS
~OUT_---"R::cEAc:cD_ _-,
• All 8102A-4 specifications are Identical to the 21 02A-4 specifications.
3-8
2102A FAMILY
Absolute Maximum Ratings*
Ambient Temperature Under Bias -1Oo
Storage Temperature
Voltage On Any Pin
With Respect To Ground
Power Dissipation
e to 80 e
0
-6SoC to +lS0oC
-O.SV to + 7V
1 Watt
·COMMENT:
Stresses above those listed under "Absolute Maximum Rating"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliabil ity.
D. C. and Operating Characteristics
TA = o°c to 70°C, Vcc = 5V ±5% unless otherwise specified.
2102A, 2102A-4
2102AL,2102AL-4
Limits
Min. Typ.(1( Max.
2102A-2, 21 02A L-2
Limits
Min_ Typ.l1] Max.
III
Input Load Current
1
10
1
10
pA
VIN = 0 to 5.25V
ILDH
Output Leakage Current
1
5
1
5
pA
CE = 2.0V,
VOL1T = VO H
ILOL
Output Leakage Current
-1
-10
-1
-10
pA
CE = 2.0V,
VOUT= 0.4V
Icc
Power Supply Current
33
Note 2
45
65
mA
All Inputs = 5.25V,
Data Out Open,
TA = OoC
VIL
Input Low Voltage
-0.5
0.8
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vcc
2.0
Vcc
V
VOL
Output Low Vo ltage
0.4
V
IOL = 2.1mA
VOH
Output High Voltage
V
IOH = -100pA
Symbol
Parameter
0.4
2.4
2.4
Unit Test Conditions
Notes: 1. Typical values are for TA = 25° C and nominal supply voltage.
2. The maximum ICC value is 55mA for the 2102A and 2102A-4, and 33mA for the 2102AL and 2102AL-4.
Standby Characteristics
2102AL, 2102AL-2, and 2102AL-4 (Available only in the Plastic Package)
TA = O°c to 70°C
Symbol
Parameter
VPD
Vcc in Standby
VCES(2]
CE Bias in Standby
2102AL,2102AL-4
Limits
Typ.(1]
Min.
Max.
2102AL-2
Limits
Typ.(1]
Min.
1.5
1.5
V
2.0
2.0
VPD
VPD
V
V
2.0V';;;VPD ';;;Vcc Max.
1.5V';;;Vpo< 2.0V
Max.
Unit
Test Conditions
IpDl
Standby Current
15
23
20
28
mA
Allinputs= VPDl = 1.5V
IpD2
Standby Current
20
30
25
38
mA
Allinputs= VPD2= 2.0V
tcp
tR(3]
Chip Deselect to Standby Time
Standby Recovery Time
0
tRC
0
ns
tRC
ns
STANDBY WAVEFORMS
NOTES:
1. Typical values are for TA = 25"C.
2. Consider the test conditions as shown: If the standby voltage (VPD) is between 5.25V (VCC Max.) and
2.0V, then CE must be held at 2.0V Min. (VI H). If
the standby voltage is less than 2.0V but greater than
1.5V (VPD Min,), then CE and standby voltage
must be at least the same value or, if they are different, CE must be the more positive of the two.
3. tR = tRC (READ CYCLE TIME).
I-----STANDBV M O D E - - - . I
vcc-----,.
OV - - - - - - - - - - -
----- ----- -- -
---
3-9
2102A FAMILY
A. C. Characteristics
= O°C to
TA
70°C, Vcc
= 5V ±5% unless otherwise specified
READ CYCLE
Symbol
2102A-4,2102AL-4
2102A,2102AL
2102A-2,2102AL-2
Limits (ns)
limits (ns)
limits (ns)
Max_
Min_
Max_ Min_
Max_ Min_
Parameter
tRe
Read Cycle
tA
Access Time
250
350
teo
Chip Enable to Output Time
130
180
tOHl
Previous Read Data Valid with
Respect to Address
40
40
40
tOH2
Previous Read Data Valid with
Respect to Chip Enable
0
0
0
250
350
450
20
20
20
180
250
300
250
350
450
450
230
WRITE CYCLE
twe
Write Cycle
tAW
Address to Write Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Setup Time
tDH
Data Hold Time
tcw
Chip Enable to Write Setup
Time
0
0
0
180
250
300
0
0
0
180
250
300
r---.
A _C _ CONDITIONS OF TEST
SYMBOL
LIMITS (pF)
Typ.ll] MAX.
TEST
0.8 Volt to 2.0 Volt
I nput Pulse Levels:
Input Rise and Fall Times:
10nsec
Timing Measurement
Inputs:
Reference Levels
Output Load:
Output:
0.8 and 2.0 Volts
I TTL Gate and CL = 100pF
C IN
1.5 Volts
C OUT
INPUT CAPACITANCE
(ALL INPUT PINS) VIN
~
OUTPUT CAPACITANCE
VOUT ~ OV
OV
3
5
7
10
Waveforms
READ CYCLE
WRITE CYCLE
~------------twc------------~
CHIP
ENABLE
~----tcw-----------I
-1]+-----twP----------t
DATA
READ/
OUT
WRITE
tow
20 VOLTS
3'
08 VOL TS
DATA
IN
NOTES: 1. Typical values are for TA = 25° e and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3-10
DATA STABLE
2102A FAMILY
Typical D. C. and A. C. Characteristics
POWER SUPPLY CURRENT VS.
AMBIENT TEMPERATURE
POWER SUPPLY CURRENT VS.
SUPPLY VOLTAGE
45
35
- - f----
40
I
I
30
Vee M A X . -
35
-~
TA
=1 25oC
/""
25
--r-- r--
30
25
:t
S
/"
20
-~
TYPICAL
I---
15
20
15
-
/
/
~PICAL
/
10
o
5
10
1
Vee (VOLTS)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
VIN LIMITS VS. TEMPERATURE
1.8
-n----
1.6
g
0
2:
1.4
z
>1.2
V,l
(MAX)
I
I
o
10
20
30
J.
40
25
20
:t
.5
-
-T
I _
VIC
1.0
30
+YPICA~
I I
50
60
15
10
/
/
V
/
~
/"
-+
TYPICAL
TA '" 25°C
Vee MIN.
I
70
VOL (VOLTS)
ACCESS TIME VS.
AMBIENT TEMPERATURE
350
ACCESS TIME VS.
LOAD CAPACITANCE
350
.i.,
TA=25°C
Vee MIN.
1 TTL LOAD
-
250
TYPICAL
,..-
f.--
- --
1 TTL LOAD
f..--
250
,,/
~YPICAL
150
150
our
OUTPf REFrENCEILEVELr VVOLOH 10.8V
~ 2.0V
50
o
10
20
30
40
50
60
-- Vee MIN.
C l '" 100pF
100
70
200
T RTRENCEj LEVEL 1,.5V
300
C l (pF)
3-11
400
500
600
inter
2104A
4096 x 1 BIT DYNAMIC RAM
2104A
Max. Access Time (ns)
350
Read, Write Cycle (ns)
500
35
Max. 100 (mA)
Period: 2 ms
• Refresh
On-Chip Latches for Addresses, Chip
• Select
and Data In
Simple
Expansion: Chip Select
• Output Memory
is
Three-State,
• Data is Latched and ValidTTLintoCompatible;
Next Cycle
• Compatible with Intel® 2116 16K RAM
Highest Density 4K RAM Industry Stan• dard
16 Pin Package
Low Power 4K RAM
• All
Inputs Including Clocks TTL
• Compatible
Standard Power Supplies:
• +12V,
+5V, -5V
The Intel® 21 04A is a 4096 word by 1 bit MOS RAM fabricated with N-channel silicon gate technology for high performance
and high functional density.
The efficient design of the 2104A allows it to be packaged in the industry standard 16 pin dual-in-line package. The 16 pin
package provides the highest system bit densities and is compatible with widely available automated handling equipment.
The use of the 16 pin package is made possible by multiplexing the 12 address bits (required to address 1 of 4096 bits) into
the 21 04A on 6 address input pins. The two 6 bit address words are latched into the 21 04A by the two TTL clocks, Row
Address Strobe (RAS) and Column Address Strobe (CAS). Non-critical clock timing requirements allow use of the
multiplexing technique while maintaining high performance.
A new unique dynamic storage cell provides high speed along with low power dissipation and wide voltage margins. The
memory cell requires refreshing for data retention. Refreshing is easily accomplished by performing any RAS/CAS cycle
with CS at VIH for each of the 64 row addresses every 2 milliseconds.
The 2104A is designed for CAS-only deselect and is compatible with Intel® 2116, 16K RAM.
PIN CONFIGURATION
LOGIC DIAGRAM
BLOCK DIAGRAM
D'N
"oUT
PIN NAMES
WRITE ENABLE
",,·As
ADDRESS INPUTS
WE
CAS
COLUMN ADDRESS STROBE
POWER {-5Vl
os
v••
CHIP SELECT
Vee
Voo
Vss
POWER (+5V)
o,N
~UT
DATA IN
OATAQUr
lIAS
ROW ADDRESS STROBE
4096 BIT
STORAGE ARRAY
-Vss
- voo
-Vee
_GNO
POWER {+12Vl
GROUND
CLOCK
GENERATOR NO.1
3-12
2104A
ABSOLUTE MAXIMUM RATINGS*
*COMMENT: Stresses above those listed under "Absolute Maxi~
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
Ambient Temperature Under Bias ..... -10DC to +80DC
Storage Temperature . . . . . . . . . . . . . -65 DC to +150DC
Voltage on any Pin Relative to VBB
(Vss - VBB ;;;. 4.5V) . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation . . . . . . . . . . . . . • . . . . . . . . . 1.0W
Data Out Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
reliability.
D.C. AND OPERATING CHARACTERISTICS[1]
TA = o°c to 70 DC, Voo = +12V ±5%, Vcc = +5V ±10%, Vss = -5V ±10%,
Symbol
Parameter
Min.
III
Input Load Current (Any Input)
IILOI
Output Leakage Current for
High I mpedance State
1001 [3]
Voo Standby Current
IBB1
VBS Standby Current
1002[3]
Limits
Typ)2]
Vss = OV, unless otherwise hoted.
Unit
Max.
10
Conditions
/lA
VIN = VIL MIN to VIH MAX
10
/lA
Chip Deselected: RAS and CAS at VIH
VOUT = 0 to 5.5V
0.7
2
mA
Voo = 12.6V, CAS and RAS at VIH.
5
50
/lA
Chip Deselected Prior to Measurement. See Note 5.
Operating V 00 Current
25
35
mA
tCYC = 500 ns
IBB2
Operating Vss Current
130
400
/lA
tRC
= 500ns,
ICC1[4]
V cc Supply Current When
Deselected
10
/lA
= 2.0mA
VIL
Input Low Voltage (Any Input)
-1.0
0.8
V
VIH
Input High Voltage
2.4
7.0
V
VOL
Output Low Voltage
0.0
0.4
V
IOL
VOH
Output High Voltage
2.4
VCC
V
IOH=-5mA
CAPACITANCE [6]
Symbol
TA
= 25
D
TA
C
Test
Typ.
Max.
Unit
Conditions
CI1
Input Capacitance (Ao-A5), DIN, CS
3
7
pF
VIN = Vss
CI2
Input Capacitance RAS, WR ITE
3
7
pF
VIN = Vss
Co
Output Capacitance (DOUT)
4
7
pF
VOUT = OV
CI3
Input Capacitance CAS
7
pF
VIN = Vss
Notes:
= oDe
6
1. All voltages referenced to VSS. The only requirement for the sequence of applying voltages to the device is that VOO. VCC, and
VSS should never be O.3V or more negative than VBB. After the application of supply voltages or after extended periods of operation without clocks, the device must perform a minimum of one initialization cycle (any valid memory cycles containing both RAS
and CAS) prior to normal operation.
2. Typical val'ues are for T A = 25° C and nominal power supply voltages.
3. The 100 current flows to VSS.
4. When chip is selected
Vec supply current is dependent on output loading~c
is connected to output buffer on!y':
5. The chip is deselected; i.e., output is brought to high impedance state by CAS-only cycle or by a read cycle with CS at VIH.
6. Capacitance measured with Boonton Meter.
3-13
2104A
A.C.CHARACTERISTICS[1]
T A= oOe to 7o o e, VDD = 12V ±5%, VCC =
5V ±10%, V BB = -5V ±10%, VSS = OV, unless otherwise noted.
READ, WRITE, AND READ MODIFY WRITE CYCLES
2104A
Parameter
Symbol
Min.
Max.
2
Unit
tREF
Time Between Refresh
tRP
RAS Precharge Time
150
ns
tcp
CAS Precharge Time
150
ns
tRCL [2]
RAS to CAS Leading Edge Lead Time
100
tCRP
CAS to RAS Precharge Time
tRSH
RAS Hold Time
200
ns
tCSH
CAS Hold Time
350
ns
tAR
RAS to Address or CS Hold Time
250
ns
tASR
Row Address Set-Up Time
0
ns
tASC
Column Address or CS Set-Up Time
0
ns
tRAH
Row Address Hold Time
100
ns
tCAH
Column Address or CS Hold Time
100
tT
Rise or Fall Time
3
50
ns
tOFF
Output Buffer Turn-Off Delay
0
100
ns
tCAC[3]
Access Time From CAS
200
ns
tRAC[3]
Access Time from RAS
350
ns
150
ms
ns
ns
0
ns
READ CYCLE
Symbol
2104A
Parameter
Min.
Max.
Unit
tRC
Random Read or Write Cycle Time
500
tRAS
RAS Pulse Width
350
ns
tCAS
CAS Pulse Width
200
ns
tRCS
Read Command Set·Up Time
0
ns
tRCH
Read Command Time
0
ns
tDOH
Data Out Hold Time
32
p.s
32000
ns
WRITE CYCLE[4]
Symbol
Notes:
2104A
Parameter
Min.
Max.
Unit
tRC
Random Read or Write Cycle Time
500
tRAS
RAS Pulse Width
350
tCAS
CAS Pulse Width
200
ns
twcs
Write Command Set-Up Time
0
ns
tWCH
Write Command Hold Time
100
ns
tWCR
Write Command Hold Time Referenced to RAS
250
ns
twp
Write Command Pulse Width
100
ns
tRWL
Write Command to RAS Lead Time
200
ns
tCWL
Write Command to CAS Lead Time
200
ns
tDS
Data-In Set-Up Time
0
ns
tDH
Data-In Hold Time
100
ns
tDHR
Data·ln Hold Time Referenced to RAS
250
ns
ns
32000
ns
1. All voltages referenced to VSS. Minimum timings do not allow for tT or skews.
2. CAS mus.!...!:!'main at VIH a minimum of tRCL MIN after RAS switches to VIL. To achiev~ the minimum guaranteed access time
(tRAC), CAS must switch to VIL at or before tRCL of tRAC - tT - tCAC as described in the Applications Information section.
tRCL MAX is given for reference only as tRAC _ tCAC·
3. Load = 2 TTL and 100 pF. See Applications Information.
4. In a write cycle DOUT latch will contain data written into cell. In a read-modify-write cycle DOUT latch will contain data read
from cell. If WE goes low after CAS and prior to tCAC, DOUT is indeterminate.
3-14
2104A
WAVEFORMS
READ CYCLE
t Re
,
;'AS
V'H
CiJ r'\l@
i'fAS
.
V"
!----tRel----,---.
V'H
CD
V'l
liH
ADDRESSES
V"
r
~ I-;'AH~I
~
ROW
ADDRESS
;'SH
II/II
1\\\\l0.
-tcp-
teAs
1-·~'cAH~
tAse
){
)(
_tCRP-fL.
.
tCSH
CAS
t ASR
l~tRP~
If
~
COLUMN
ADDRESS
tAR
y,(
V'H
CS
~·'cAH~
tAse
V
V"
r---
V'H
WE
,=t ~
Jff
.
V'l
1----1 tRCH
t RCS
tRAC
t eAc
t OFF -+
VOH
OOH _
1-
~®
DOUT
HIGH IMPEDANCE
VALID
DATA OUT
~
70
VOL
~
WRITE CYCLE
- - - . ;,e
.
V'H
i'fAS
;'AS
•
r:---=;R:==:1
If
CD r\(2)
_ _ t eRP -----+-
V'l
.
/, II,
'cSH
-;,el~
v,H
CAS
v,l
tASRI ..........
V'H
ADDRESSES
t ASH
CD \\\\ (3)
){CD(3)
tAse
-;'AH-1
ROW ) (
ADDRESS
)<
-
.
'cAS
-'cAH-
-'cP~
)(
COLUMN
ADDRESS
v,l
\-
v,H
'weR
tAR
-'tcAH-----...
tAse
12'
CS
V'l
/
;'Wl
tCWl
v,H
WE
\.
-'wes-
Hi)
'wp
I--- ' w e H -
1
/
V'l
tDHR
®'os-jV'H
D'N
v,l
-'oH~
XCD®
K
tRAC
VOH
DouT
tOFF
~
'11:0
$0
VOL
(See next page for notes)
3-15
tCAe
HIGH IMPEDANCE
tDOH_1
®
VALID
DATA OUT
F-
2104A
A.C.CHARACTERISTICS[1]
TA = O°C to 70°C, Voo = 12V ±5%, VCC = 5V ±10%, VBB = -5V ±10%, VSS = OV, unless otherwise noted.
READ-MODIFY-WRITE CYCLE
Symbol
2104A
Parameter
Min.
Unit
Max.
tRWC
Read Modify Write Cycle Time[2]
700
ns
tCRW
RMW Cycle CAS Width
400
ns
tRRw
RMW Cycle RAS Width
550
ns
tRWL
RMW Cycle RAS Lead Time
200
ns
tCWH
RMW Cycle CAS Hold Time
550
ns
tCWL
Write Command to CAS Lead Time
200
ns
twp
Write Command Pulse Width
100
ns
tRCS
Read Command Set-Up Time
tMOO
Modify Time
tos
Data·ln Set-Up Time
tOH
Data-In Hold Time
a
a
a
ns
10
J.l.s
ns
100
ns
Notes: 1. All voltages referenced to Vss.
2. The minimum cycle timing does not allow for tT or skews.
WAVEFORMS
READ-MODIFY-WRITE CYCLE
,"we
1'1'
- r--
tRRW
CD 0
cA.s
I '
i - - tRCL -
II
0
II~I'RAH
V 1l
'CWH
,
V,H
Vil
V,H
CS
V'L
\
-tcRP-----------..
tCRW
II
\\\\ 0
I-----'RWL~
tASR~
i tAscr
I~
COLUMN
X0 AD~~~SS J( X ADDRESS
K
CD
'AR
-tCAH
ADDRESSES
'RP-----+
/
II
V,H
.
~tcP-
- - tcwL - - - -
.
IV
CD~
H
tRCSj-----------
V,H
_twP-j;
0 0/
WE
V'L
t MOD
'-,-
,- -'DS@
V,H
~
D,N
V'L
VOH
DOUT
VOL
,
t RAC
,
toFF---1
~®
.
teAc
HIGH
IMPEDANCE
¥0)
0 DATA
IN
VALID
CD
tDH@
K
tOOH
®
VALID
DATA OUT
Notes: 1,2. VIHMIN and VILMAX are reference levels for measuring timing of input signals.
3,4. VOHMIN and VOLMAX are reference levels for measuring timing of 00UT.
5.
6.
Referenced to CAS or WE, whichever occurs last.
In a write cycle 00UT latch will contain data written into cell. In a read-modify-write cycle 00UT latch will contain
data read from cell. If WE goes low after CAS and prior to tCAC, DOUT is indeterm inate.
3-16
2104A
TYPICAL CHARACTERISTICS
TYPICAL IBB2 AND 1002
VS. CYCLE TIME
TYPICAL IBB2 AND 1002
VS. TEMPERATURE
800
40
12.0V
-5.0V
500 ns
100 ns
150 ns
Voo
VBB
'RC
tRCL
'RP
30
20
'0
o
r--- ~
o
25
600
400
200
~
j
20
~
o
'00
~2
'0
....
75
350
r-..
IBB2
400
TEMPERATURE ("C)
--......
o
200
'" -s.ov
'" 25 c C
teAs = 200 ns
tRCL '" 100 ns_ 600
30
r-
50
800
VOD '" 12.0V
-
IDOl
VS. TEMPERATURE
40
VBB
TA
145 ns.
3-17
'00
2104A
Note that if 100 nsec ~ tRCL ~ 145 nsec, device access
time is determined by equation 3 and is equal to tRAC. If
tRCL> 145 nsec, access time is determined by equation 4.
This 45 ns interval (shown in the tRCL inequality in equation 3) in which the failing edge of CAS can occur without
affecting access time is provided to allow for system timing
skew in the generation of CAS. This allowance for a tRCL
skew is designed in at the device level to allow minimum
access times to be achieved in practical designs.
WRITE CYCLE
A Write Cycle is generally performed by bringing Write
Enable (WE) low before CAS. DOUTwili bethe data written
into the cell addressed. If WE goes low after CAS and prior
to tCAC, DouT will be indeterminate.
READ-MODIFY-WRITE CYCLE
A Read-Modify-Write Cycle is performed by bringing
Write Enable (WE) low after access time, tRAC, with RAS
and CAS low. Data in must be valid at or before the falling
edge of WE. In a read-modify-writecycle DouTis data read
and does not change during the mOdify-write portion of
the cycle.
CAS ONLY (DESELECT) CYCLE
In some applications, it is desirable to be able to deselect
all memory devices without running a regular memory
cycle. This may be accomplished with the 2104A by performing a CAS-Only Cycle. Receipt of a CAS without RAS
deselects the 2104A and forces the Data Output to the
high-impedance state. This places the 2104A in its lowest
power, standby condition. 100 will be about twice 1001 for
the first cycle of CAS-only deselection and 1001 for any
additional CAS-only cycles. The cycle timing and CAS
timing should be just as if a normal RAS/CAS cycle was
being performed.
RASJCAS CYCLE
RAS
CAS
'BB
(rnA)
v," ---,
V"
V," - V"
-t
+2:
-20
I
CAS ONLY CYCLE
I
100 200 300400 SOD 600 700 800 9001000(ns)
VI
I
tI- l
1.l-iJ
-
~.
-4.
+100
+80
....
'DD
(rnA)
""r
+40
+20
•-
II
~ ruItw~
TYPICAL SUPPLY CURRENTS VS. TIME
I
CHIP SELECTION/DESELECTION
The 2104A is selected by driving CS low during a Read,
Write, or Read-Modify-Write cycle. A device is deselected
by 1) driving CS high during a Read, Write, or ReadModify-Write cycle or 2) performing a CAS Only cycle
independent of the state of CS.
REFRESH CYCLES
Each of the 64 rows internal to the 2104A must be
refreshed every 2 msec to maintain data. Any data cycle
(Read, Write, Read-Modify-Write) refreshes the entire
selected row (defined by the low order row addresses).
The refresh operation is independent of the state of chip
select. It is evident, of course, that if a Write or ReadModify-Write cycle is used to refresh a row, the device
should be deselected (CS high) if it is desired not to
change the state of the selected cell.
RAS/CAS TIMING
The device clocks, RAS and CAS, control operation of the
2104A. The timing of each clock and the timing
relationships of the two clocks must be understood by the
user in order to obtain maximum performance in a
memory system.
The RAS and CAS have minimum pulse widths as defined
by tRAS and teAS respectively. These minimum pulse
widths must· be maintained for proper device operation
and data integrity. A cycle, once begun by driving RAS
and/or CAS low must not be ended or aborted prior to
fulfilling the minimum clock signal pulse width(s). A new
cycle must not begin until the minimum precharge time,
tRP, has been met.
POWER SUPPLY
Typical power supply current waveforms versus time are
shown below for both a RAS/CAS cycle and a CAS only
cycle. 100 and IBB current surges at RAS and CAS edges
make adequate decoupling of these supplies important. Due
to the high frequency noise component content of the current waveforms, the decoupling capacitors should be low
inductance, ceramic units selected for their high frequency
performance.
It is recommended that a 0.1 f..lF ceramic capacitor be connected between Voo and Vss at every other device in the
memory array. A 0.1 f..lF ceramic capacitor should also be
connected between V BB and V ss at every other device
(preferably the alternate devices to the Voo decoupling).
For each 16 devices, a 10 f..lF tantalum or equivalent capacitor should be connected between Voo and VSS near the
array. An equal or slightly smaller bulk capacitor is also
recommended between VBB and Vss for every 32 devices .
A 0.01 f..lF ceramic capacitor is recommended between Vce
and Vss at every eighth device to prevent noise coupling to
the VCC line which may affect the TTL peripheral logic in
the system.
3·18
2104A
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution
system on the array board should be minimized. It is
recommended that the Vo o , VBB, and Vss supply lines be
gridded both horizontally and vertically at each device in
the array. This technique allows use of double-sided circuit
boards with noise performance equal to or better than
multi-layered circuit boards.
~$§~~~VCC
VBBJ.J.
DIN
DOUT
DECOUPLING CAPACITORS
D ~ 0.1 "F to VDD TO Vss
B ~ 0.1 "F VBB TO Vss
C ~ 0.01 "F Vce TO Vss
3-19
2104A FAMILY
4096 x 1 BIT DYNAMIC RAM
2104A-3
2104A-4
2104A-1
2104A-2
Max. Access Time (ns)
150
200
250
300
Read, Write Cycle (n5)
320
375
375
425
35
32
30
30
Max. 100 (mA)
• Highest Density 4K RAM Industry Standard 16 Pin Package
• Refresh Period: 2 ms
• On-Chip Latches for Addresses, Chip
Select and Data In
• Simple Memory Expansion: Chip Select
• Output is Three-State, TTL Compatible;
Data is Latched and Valid into Next Cycle
• Low Power 4K RAM: 462mW Operating
27mW Standby
• All Inputs Including Clocks TTL
Compatible
• :t10% Tolerance on All Power Supplies
+12V, +5V, -5V
• RAS-Only Refresh Operation
The Intel® 2104A is a 4096 word by 1 bit MOS RAM fabricated with N-channel silicon gate technology for high performance
and high functional density.
The efficient design of the 2104A allows it to be packaged in the industry standard 16 pin dual-in-line package. The 16 pin
package provides the highest system bit densities and is compatible with widely available automated handling equipment.
The use of the 16 pin package is made possible by multiplexing the 12 address bits (required to address 1 of 4096 bits) into
the 2104A on 6 address input pins. The two 6 bit address words are latched into the 21 04A by the two TTL clocks, Row
Address Strobe (RAS) and Column Address Strobe (CAS). Non-critical clock timing requirements allow use of the
multiplexing technique while maintaining high performance.
A new unique dynamic storage cell provides high speed along with low power dissipation and wide voltage margins. The
memory cell requires refreshing for data retention. Refreshing is most easily accomplished by performing a RAS-only
refresh cycle or read cycle at each of the 64 row addresses every 2 milliseconds.
The 2104A is designed for page mode operation, RAS-only refresh, and CAS-only deselect.
PIN CONFIGURATION
LOGIC DIAGRAM
Vss
Ao
0,.
CAS
A,
WE
Dour
v••
A,
BLOCK DIAG RAM
WE ---J--=-'-'="'-I
0,.
A)
"AS
CS
""A,
A)
A,
As
A,
As
DOUT
A,
Vee
Voo
Dour
~-
...
PIN NAMES
ADDRESS INPUTS
WE
WRITE ENABLE
CAS
COLUMN ADDRESS STROBE
POWER (-5Vl
CS
CHiP SelECT
V"
Vee
Voo
Vss
o,N
DATA IN
CoUT
DATA OUT
lIAS
ROW ADDRESS STROBE
4096 BIT
STORAGE ARRAY
_-V"
--VOD
--Vee
POWER (+5Vl
_-GND
POWER (+12V!
GROUND
CLOCK
'R AS)
3-20
_--1...:G:.:,E;,;;NE;,;;",;;,AT;,:;O;,;;".;,,:N.::,O..:'....
2104A FAMILY
ABSOLUTE MAXIMUM RATINGS·
·COMMENT.
Ambient Temperature Under Bias ..... _10°C to +80°C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Voltage on any Pin Relative to VBB
(Vss - VBB ;;. 4.5V) . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation .... . . . . . . . . . . . . . . . . . .. 1.0W
Data Out Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1]
TA ~ 0° to 70°C. Voo ~ +12V ±10%. VCC ~ +5V ±10%. VBB ~ -5V ±10%. Vss ~ OV. unless otherwise noted.
Limits
Symbol
Parameter
Min.
Typ.12)
Unit
Max.
Conditions
III
Input Load Current (any input)
10
/J. A
VIN = Vss to VIH MAX
IILOI
Output Leakage Current for
High Impedance State
10
/J.A
Chip deselected: RAS and CAS at V IH
VOUT ~ 0 to 5.5V
1001 [3J
VOD Standby Current
0.7
2
mA
Voo ~ 13.2V
0.7
1.5
mA
Voo ~ 12.6V
IBB1
VBB Standby Current
5
50
/J.A
V DO = 13.2V
1002[3J
Operating V DO Current
24
35
mA
2104A-l
tRC = tRC MIN
22
32
mA
2104A-2
tRC = tRC MIN
20
30
mA
130
325
/J.A
10
/J. A
25
mA
2104A-l,2104A-2
tRC = tRC MIN
22
mA
2104A·3,2104A-4
tRC = tRC MIN
IBB2
Operating VBB Current
Icc,[4 J
VCC Supply Current when
Deselected
1003
Operating Voo Current
(RAS-only cycle)
12
10
Min cycle time. T A = O°C
Input Low Voltage (any input)
-1.0
0.8
V
VIH
Input High Voltage (any input)
2.4
7.0
V
VOL
Output Low Voltage
0.0
0.4
V
IOL ~ 3.2 mA
VOH
Output High Voltage
2.4
Vcc
V
IOH
Symbol
TA
tRC = tRC MIN
2104A-3,2104A-4
VIL
CAPACITANCE [6]
CAS and RAS at V IH .
Chip deselected prior
to measurement.
See Note 5.
~
-5 mA
= 25°C
Typ.
Max.
Unit
Conditions
CI1
Input Capacitance (Ao-A5, DIN. CS)
Test
3
7
pF
VIN ~ VSS
Cl2
Input Capacitance (RAS, WRITE)
3
7
pF
VIN ~ Vss
VOUT ~ OV
VIN = Vss
Co
Output Capacitance (DOUT)
4
7
pF
CI3
Input Capacitance (CAS)
6
7
pF
Notes: 1. All voltages referenced to VSS. The only requirement for the sequence of applying voltages to the device
IS
that VOO. VCC. and
VSS should never be O.3V or more negatIve than VaB' After the application of supply voltages or after extended periods of operation without clocks, the device must perform a minimum of one initialization cycle (any valid memory cycles containing both FfAS
and CAS) prior to normal operation.
2. Typical values are for TA = 2SoC and nommal power supply voltages.
3. The 100 current flows to VSS.
IS
5. The chip
deselected; I.e .• output
IS
selected
Vee supply current
4. When chip
IS
IS
dependent on output loadlng~c
IS
connected to output buffer on~
brought to high Impedance state by CAS-only cycle or by a read cycle with CS at VIH.
6. Capacitance measured with Boonton Meter.
3-21
2104A FAMILY
A.C.CHARACTERISTICS[1.2)
TA=O°C to 70°C,VDD= 12V ±10%, Vcc=5V ±10%,VBB=-5V ±10%, VSS=OV,unless otherwise noted.
READ, WRITE, AND READ MODIFY WRITE CYCLES
Symbol
2104A-1
Min.
Max.
Parameter
tREF
Time Between Refresh
tRP
RAS Precharge Time
tcp
CAS
2104A-2
Min.
Max.
2104A-3
Min.
Max.
2
2
2104A-4
Min.
Max.
2
2
Unit
ms
ns
100
120
120
125
Precharge Time
60
80
110
110
tRCD[3]
RAS to CAS Delay Time
20
tCRP
CAS to RAS Precharge Time
tRSH
RAS Hold Time
tAR
RAS to Address or
tASR
Row Address Set-Up Time
tASC
Column Address or
tRAH
Row Address Hold Time
tCAH
Column Address or
tT
Rise or Fall Time
3
50
3
50
3
50
3
50
ns
tOFF
tCAcl 4 •5 ]
Output Buffer Turn-Off Delay
0
50
0
60
0
60
0
80
ns
Access Time F rom CAS
100
135
165
165
ns
tRAcl 4]
Access Time From R AS
150
200
250
300
ns
CS
Hold Time
CS Set-Up Time
CS
50
65
35
85
80
ns
135
ns
0
0
0
0
ns
100
165
160
165
ns
95
135
120
215
ns
0
0
0
0
ns
-10
20
-10
25
-10
35
-10
ns
80
ns
45
Hold Time
25
ns
80
75
55
READ CYCLE
2104A-1
Symbol
Parameter
Min.
Max.
2104A-2
Min.
Max.
375
2104A-3
Min.
Max.
Max.
Unit
ns
tRC
Random Read or Write Cycle Time
320
tRAS
RAS Pulse Width
150
tCAS
CAS Pulse Width
100
135
165
165
ns
tRCS
Read Command Set·Up Time
0
0
0
0
ns
tRCH
tDOH
Read Command Hold Time
0
0
0
0
ns
10
10
10
10
",
Data Out Hold Time
10000
200
375
2104A-4
Min.
10000
250
425
10000
300
10000
ns
WRITE CYCLE
2104A-1
Symbol
Parameter
Min.
Max.
2104A-2
Min.
Max.
375
2104A-3
Min.
Max.
2104A-4
Min.
Max.
Random Read or Write Cycle Time
320
tRAS
RAS Pulse Width
150
tCAS
CAS Pulse Width
100
135
165
165
ns
twCS(6]
Write Command Set-Up Time
0
0
0
0
ns
twCH
Write Command Hold Time
45
55
75
80
ns
tWCR
Write Command Hold Time Referenced to
95
120
160
215
ns
twp
Write Command Pulse Width
45
55
75
80
ns
tRWL
Write Command to RAS Lead Time
50
70
85
130
ns
tCWL
Write Command to CAS Lead Time
50
70
85
130
ns
RAS
10000
200
425
Unit
tRC
375
10000
250
10000
300
ns
10000
ns
tDS
Data-I n Set-Up Time
0
0
0
0
ns
tDH
Data·ln Hold Time
55
65
75
80
ns
tDHR
Data-In Hold Time Referenced to RAS
95
120
160
215
ns
NOTES:
1. All voltages referenced to VSS.
2. A.C. Characteristics assume tT = 5ns.
3. tRCD(MAXI is specified as a reference point only; if tRCD .. tRCD(MAX) acce.. time is tRAC, if tRCD
> tRCD(MAX)
access time is tRCD + tCAC.
4. Load = 2TTL loads and 100pF.
5. Assumes tRCD ." tRCD(MAX).
6. In a write cycle with tWCS'" twCS(M IN) the cycle is an early write cycle and DOUT will be data written into the selected cell
(DOUT = DIN). If tCWD ." tCWD(MIN) and tRWD ." tRWD(MIN) the cycle isa read-modify-write cycle and
DOUT will be data from the selected address read. If neither of the above conditions are satisfied, DOUT
is indeterminate.
3-22
2104A FAMILY
WAVEFORMS
READ CYCLE
'RC
f--'RP---j
t RAS
V'H
(if
RAS
v"
0
... -tcRP
V'H
CD,,\\\ l®
CAS
V"
~H
ADDRESSES
V"
'A.RI--
~
~AH
1-
..:
ROW
ADDRESS
X
1
t CAS
){
V"
ADDRESS
r--
VIH
I
X
COLUMN
~
V"
I111 --~p~
--~H--
t Ase
'AR
CS
.1
"SH
tRCD
--.
t Ase
~H-
/
!""t
tRes
V"
t RAe
I·
t CAC
1-
t OFF -
VOH
~0
DOUl
CAll
VIH
CD
v"
.
"e
CD \.\\ \ /J)
-"AH---j
'ASC
V,H
){CD0
)
ROW 1 ) (
ADDRESS
-
/
~A'
V,H
\
-
VIH
V"
'AR
'ASC
""'"
-~.-
f2\
D'N
\\,
I--;,cs-
'CWL
'wp
-;'C'-I/
!I.®
®'osr-
-toH~
K
XCi®
t RAe
'oFF ......,
v"H
'Ixn-
v"L
RAS-ONLY REFRESH CYCLE
V
t RWL
tOHR
V,H
'IJ ~~P---1'-
K
V"
WE
-tcRP-
-~COLUMN
ADDRESS
V"
es
}-
t RSH
tRCD
t ASR : -
I
VALID
DATA OUT
7
0
~,
t DOH
• I-'RP----I
"AS
VIH
ADDRESSES
X
'i.
HIGH IMPEDANCE
$0
VO,
WRITE CYCLE
RCH
j\
rJif
WE
1<.0
.Jt0
'CAe
HIGH IMPEDANCE
t DOH _ ]
~® O::i:,oUT
}--
2104A FAMILY
A.C.CHARACTERISTICS (7,8]
TA = 0 0 to lO0C, VDD =12V ±10%, Vcc=5V ±10%, Vss=-5V ± 10%, VsS=OV,unless otherwise noted.
READ-MODIFY-WRITE CYCLE
Symbol
Parameter
2104A·l
Min.
Max.
2104A·2
Min.
Max.
2104A·3
Min.
Max.
2104A·4
Min.
Max.
Unit
tRWC
Read Modify Write Cycle Time[2]
330
420
480
575
tCRW
RMW Cycle CAS Width
115
155
180
250
tRRW
RMW Cycle RAS Width
165
tRWL
RMW Cycle RAS Lead Time
50
70
85
130
ns
tCWL
Write Command to CAS Lead Time
50
70
85
130
ns
twp
Write Command Pulse Width
45
55
75
80
ns
tRCS
Read Command Set·Up Time
0
0
0
0
ns
tRWDI6J
RAS to WE Delay
110
145
175
250
ns
tCWD [6J
CAS to WE Delay
60
80
90
115
ns
tDS
Data·ln Set·Up Time
0
0
0
0
ns
tDH
Data·ln Hold Time
55
65
75
80
ns
10,000
220
265
10,000
10,000
385
ns
ns
10,000
ns
WAVEFORMS
READ-MODIFY-WRITE CYCLE
'Rwe
r--'""-
'RRW
I
CD} 0
'7
!
i _ - - tRco-----j
V"
ADDRESSES
V"
~__+
I -1'RAH I
I tAscM
I-----------1
-'RWC~
J(
I
'AA
I
I
WE
Iv
CD~
cs
~tcP-------------
--tCWl
-teAH
XCD AD~~~SS X X ~g~~~~
0
I·
-tcRP----"
'vI;
CD},\\"J.0
'.
t ASR
J
tCflW
H
t RWD
--i
tRcsl...
t cwo -
-
--_
-~'--l
y
o CD/
"I t:-@)''j'DH®
I
tDS 5
)qeD DATA
IN
VALID
0
tRAC
t CAC
tOFF
"----j
0
7.
8.
tOOH~
HIGH
IMPEDANCE
-"0
Notes: 1,2.
3,4,
5.
6.
K
®
VALID
DATA OUT
VIHMIN or VIHCMIN and VILMAX are reference levels for measuring timing of input signals.
VOHMIN and VOLMAX are reference levels for measuring timing of DOUT.
Referenced to CAS or WE, whichever occurs last.
In a write cycle with tWCS;;' tWCSIMIN] the cycle is an early write cycle and DOUT will be data written into the selected cell
1DOUT = DIN)· If tCWD;;' tCWDIMIN) and tRWD;;' tRWD(MIN) the cycle is a read-modify-write cycle and DOUT will be
data from the selected address read. If neither of the above conditions are satisfied, DOUT is indeterminate.
All voltages referenced to VSS.
A.C. Characteristics assume tT:: 5ns.
3·24
2104A
FAMILY
TYPICAL CHARACTERISTICS
TYPICAL IBB2 AND 1002
VS. TEMPERATURE
40
800
120V
-50V
50005
100 ns
150n5_ 600
Voo
VBB
'Re
tRCo
'R"
30
10
o
-
1002
i--
TYPICAL IBB2 AND 1002
VS. CYCLE TIME
400
r-- ~:-o
200
25
50
40
800
75
100
260 . . . - - - - . . . - - - - , - - - - , - - - - - ,
VOD ., 12.0V
VBB = -50V
TA
= 25 C
""j
VOD = 10,BV
Vas = -5.6V
teAs'" 200 os
tACO'" 100 ns _
30
20
~
~O2
10
't-o
TYPICAL ACCESS TIME
VS. TEMPERATURE
o
200
400
TEMPERATURE ( C}
IB82
600
--800
600
2OOr---r---t=~--r--~
400
""~ ];150
200
100
o
1000
.
60~--~--~--~-~
o
25
TCYCLE (ns)
75
100
TEMPERATURE fOCI
APPLICATIONS
ADDRESSING
Two externally applied negative going TTL clocks, Row
Address Strobe (RAS), and Column Address Strobe
(C"AS), are used to strobe the two sets of 6 addresses into
internal address buffer registers. The first clock, RAS,
strobes in the six low order addresses (Ao-A,) which
selects one of 64 rows and begins the timing which
enables the column sense amplifiers. The second clock,
CAS, strobes in the six high order addresses (Ao-A I d to
select one of 64 column sense amplifiers and Chip Select
(CS) which enables the data out buffer.
system access time since the decode time for chip select
does not enter into the calculation for access time.
Both the RAS and CAS clocks are TTL compatible and do
not require level shifting and driving at high voltage MaS
levels. Buffers internal to the 2104A convert the TTL level
signals to MaS levels inside the device. Therefore, the
delay associated with external TTL-MaS level converters
is not added to the 2104A system access time.
An address map of the 21 04A is shown below. Address "0'"
corresponds to all addresses at VII. All addresses are
sequentially located on the chip.
READ CYCLE
A Read cycle is performed by maintaining Write Enable
(WE) high during CAS. The oufput pin of a selected device
will unconditionally go to a high impedance state
immediately following the leading edge of CAS and
remain in this state until valid data appears at the output at
access time. The selected output data is internally latched
and will remain valid for at least tOOH MAX. A subsequent
CAS must be given to the device either by a Read, Write,
Read-Modify-Write, CAS-only or RAS/CAS refresh cycle.
2104A Address Map
0
4032
ffi
0
0
ARRAY
(DATA IN)
frl
0
;:
0
a:
4095
Device access time, tACC, is the longer of two calculated
intervals:
63
SENSE AMPLIFIER
COLUMN DECODER
1. tACC = tRAC OR 2. tACC = tRCO
DATA CYCLES/TIMING
A memory cycle begins with addresses stable and a
negative transition of RAS. See the waveforms on page 4.
It is not necessary to know whether a Read or Write cycle
is to be performed until CAS becomes valid.
+ tCAC
Access time from RAS, tRAC, and access time from CAS,
tCAC, are device parameters. RAS to CAS delay time, tRCO,
is a system dependent timing parameter. For example,
substituting the device parameters to the 2104A-4 yields:
3. tACC = tRAC = 300ns for 80nsec ::; tRCO ::; 135nsec
OR
4. tACC = tRCD + tCAC = tRCD + 165ns for tRCD > 135ns.
Note that Chip Select (CS) does not have to be valid until
the second clock, CAS. It is, therefore, possible to start a
memory cycle before it is known which device must be
selected. This can result in a significant improvement in
3·25
2104A FAMILY
Note that if 80nsec S tRCD S 135nsec, device access time is
determined by equation 3 and is equal to tRAC. If tRCD >
135ns, access time is determined by equation 4. This 55ns
interval (shown in the tRCD inequality in equation 3) in
which the falling edge of CAS can occur without affecting
access time is provided to allow for system timing skew in
the generation of CAS. This allowance for a tRCD skew is
designed in at the device level to allow minimum access
times to be achieved in practical system designs.
Write, or Read-Modify-Write cycle. A device is deselected
by 1) driving CS high during a Read, Write, or ReadModify-Write cycle or 2) performing a CAS Only cycle
independent of the state of CS.
REFRESH CYCLES
Each of the 64 rows internal to the 2104A must be
refreshed every 2 msec to maintain data. Any cycle (Read,
Write, Read-Modify-Write, RAS-only refresh) refreshes
the entire selected row (defined by the low order row
addresses). The refresh operation is independent of the
state of chip select. It is evident, of course, that if a Write or
Read-Modify-Write cycle is used to refresh a row, the device should be deselected (CS high) if it is desired not to
change the state of the selected cell.
WRITE CYCLE
A Write Cycle is generally performed by bringing Write
Enable (WE) low before CAS. DOlI will be the data written
into the cell addressed. If WE goes low after CAS buttCWD
< tCWD MIN and tRWD < tRWD MIN, Dour will be
indeterminate.
RAS/CAS TIMING
READ-MODIFY-WRITE CYCLE
The device clocks, RAS and CAS, control operation of the
2104A. The timing of each clock and the timing
relationships of the two clocks must be understood by the
user in order to obtain maximum performance in a
memory system.
A Read-Modify-Write Cycle is performed by bringing
Write Enable (WE) low during a selected RAS/CAS cycle
with tRWD 2: tRWD MIN and tewD 2: tCWD MIN. Data in must be
valid at or before the falling edge of WE. In a read-modifywrite cycle Dour is data read from the selected cell and
does not change during the modify-write portion of the
cycle.
The RAS and CAS have minimum pulse widths as defined
by tRAS and tCAS respectively. These minimum pulse
widths must be maintained for proper device operation
and data integrity. A cycle, once begun by driving RAS
and/or CAS low must not be ended or aborted prior to
fulfilling the minimum clock signal pulse width(s). A new
cycle must not begin until the minimum precharge time,
tRP, has been met.
CAS ONLY (DESELECT) CYCLE
In some applications, it is desirable to be able to deselect
all memory devices without running a regular memory
cycle. This may be accomplished with the 2104A by per·
forming a CAS·Only Cycle. Receipt of a CAS without RAs
deselects the 2104A and forces the Data Output to the
high·impedance state. This places the 2104A in its lowest
power, standby condition. I DO will be about twice 1001 for
the first cycle of CAS'only deselection and 1001 for any
additional CAS'only cycles. The cyc~imJ.!:!J1 and CAS
timing should be just as if a normal RAS/CAS cycle was
being performed.
PAGE MODE OPERATION
The 2104A is deSigned for page mode operation. Product
tested to page mode operating specifications are available
upon request.
POWER SUPPLY
CHIP SELECTION/DESELECTION
Typical power supply current waveforms versus time are
shown below for both a RAS/CAS cycle and a CAS only
cycle. I DO and I BB current surges at RAS and CAS edges
make adequate decoupling of these supplies important. Due
to the high frequency noise component content of the cur·
rent waveforms, the decoupling capacitors should be low
inductance, ceramic units selected for their high frequency
performance.
The 2104A is selected by driving CS low during a Read,
RASlCAS CYCLE
RAS
V'H
V"
CAS
~,
V'H
-
- r--
v"
+2:
(rnA)
"t
.
!
CP3 ONL Y CYCLE
I
I
ILt-+J
It-
~
t-
~
It is recommended that a 0.1 I-'F ceramic capacitor be con·
nected between VDO and Vss at every other device in the
memory array. A 0.1 I-'F ceramic capacitor should also be
connected between VBB and Vss at every other device
(preferably the alternate devices to the VDO decoupling) .
For each 16 devices, a 10 I-' F tan tal um or equ ivalent capaci·
tor should be connected between VOO and VSS near the
array, An equal or slightly smaller bulk capacitor is also
recommended between VBB and Vss for every 32 devices .
~ ru I~r-"l
A 0.01 I-'F ceramic capacitor is recommended between VCC
and V ss at every eighth device to prevent noise coupl ing to
theVCC line which may affect the TTL peripheral logic in
the system,
,A
VI
.",
I
100 200 JOO 400 SOO 600 700 800 900 1ooo(ns)
""
~'20
+100
·80
• 60
'DO
ImAI
••0
.'0
-
TYPICAL SUPPL Y CURRENTS VS TIME
3·26
2104A FAMILY
gridded both horizontally and vertically at each device in
the array. This technique allows use of double·sided circuit
boards with noise performance equal to or better than
multi·layered circuit boards.
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution
system on the array board should be minimized. It is
recommended that the V DD , Vss. and Vss supply lines be
~~~~~VCC
VBB~
DIN
OOUT
OECOUPLING CAPACITORS
o
0.1 "F to VOO TO Vss
B
C
0.1 "F VSB TO VSS
0.01 "F VCC TO VSS
•
3·27
2107C FAMILY
4096·BIT DYNAMIC RAM
Access Time (ns)
Read, Write Cycle (ns)
RMW Cycle (ns)
Max 100 AV (mA)
•
•
•
•
•
2107C·1
150
380
450
35
2107C·2
200
400
500
33
2107C
250
430
550
30
2107C·4
300
470
590
30
Direct Replacement for Industry
Standard 22·Pin 4K RAMs
•
± 10% Tolerance on all Power
Supplies
Low Operating Power
•
Output is Three·State and TTL
Compatible
•
TTL Compatible - All Address, Data,
Write Enable, Chip Select Inputs
•
Refresh Period 2 ms
Low Standby Power
Only One High Voltage Input SignalChip Enable
150 ns Access Time
The Intel® 2107C is a 4096-word by l-bit dynamic n-channel MOS RAM_ It was designed for memory applications where
very low cost and large bit storage are important design objectives. A new unique dynamic storage cell provides high speed
and wide operating margins. The 2107C uses dynamic circuitry which reduces the standby power dissipation.
Reading information from the memory is non-destructive. Refreshing is most easily accomplished by performing one read
cycle on each of the 64 row addresses. Each row address must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic one or a logic zero.
The 2107C is fabricated with n-channel silicon gate technology. This technology allows the design and production of high
performance, easy to use MOS circuits and provides a higher functional density on a monolithic chip than other MOS technologies. The 2107C is a replacement for the 2107A, 2107B and other industry standard 22-pin 4K RAMs.
PIN CONFIGURATION
2107C
VBB
LOGIC SYMBOL
2107C
AD
AD
A,
...
...
DIN
...
A1
DoUT
Vss
As
A,
All
A1
A,.
A11
A2
All
cs
NC
AS
AD
A,_
A,
A4
All
A,.
WE
CS
...
A2
Vee
CE
A11
CE WE
PIN NAMES
Ao-A11 ADDRESS INPUTS·
CE
ell
DIN
llQUT
NC
CHIP ENABLE
CHIP SELECT
DATA INPUT
DATA OUTPUT
NOT CONNECTED
ROW DECODE
AND BUFFER
REGISTER
"'~"L-_---,~_~
AS
CE
6OOi'
A2
A4
A4
VDD
DIN
BLOCK DIAGRAM
VBB
Vee
Voo
POWER (-5VI
POWER (+6VI
POWER (+12V)
Vss
GROUND
WE
WRITE ENABLE
3-28
84
MEMORY
ARRAY
84X84
VDD
VCC
Vss
VBB
2107C FAMILY
Absolute Maximum Ratings·
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ._10°C to BO°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to +150°C
Voltage on any Pin Relative to VBB (Vss - VBB ~4.51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.00W
'COMMENT:
Stresses above those listed under "Absoluta Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. and Operating Characteristics
TA = O°C to 70°C, Voo = +12V ±10%, VCC = +5V ±10%, VBB[ll = -5V ±10%, VSS= OV, unless otherwise noted.
Symbol
Limits
Parameter
Unit
Min.
Typ.[21
Conditions
Max.
III
Input Load Current (all inputs except CEI
10
j.LA
VIN = OV to VIH MAX
CE = VILC or VIHC
ILC
Input Load Current, CE
2
j.LA
VIN = OV to VIHC MAX
IILol
Output Leakage Current for high
impedance state
10
j.LA
CE = VILC or CS = VIH
Vo = OV to 5.5V
1001[31
Voo Supply Current - standby [31
20
200
j.LA
CE = -1 V to +0.6V
24
35
mA
2107C-l, tCYC = 380
100AV
Average V DO Current - operating
22
33
mA
2107C-2, tCYC = 400
20
30
mA
2107C,
20
30
mA
2107C·4, tCYC = 470
10
j.LA
CE = VILC or CS = VIH
5
50
j.LA
CE = -1 V to +O.6V
100
Min. cycle time, Min. tCE
tCYC = 430
ICCl [3,41
V cc Supply Current - standby
IBBl
VBB Supply Current - standby
IBB AV
Average VBB Current - operating
400
j.LA
VIL
Input Low Voltage
-1.0
0.8
V
VIH
Input High Voltage
2.4
Vcc+l
V
VILC
CE Input Low Voltage
-1.0
+1.0
V
VIHC
CE Input High Voltage
Voo-l
Voo+l
V
VOL
Output Low Voltage
0.0
0.40
V
IOL = 3.2 mA
VOH
Output High Voltage
2.4
Vcc
V
IOH = -2.0 mA
NOTES:
1. ~he only requirement for the sequence of applying voltage to the device is that Voo, VCC, and VSS should never be O.3V or more nega.
tove than VBB.
2. Typical values are for TA = 25°C and nominal power supply voltages.
3. The 100 and ICC currents flow to VSS.
4. During CE on VCC supply current is dependent on output loading. VCC is connected to output buffer only.
3·29
2107C FAMILY
A.C. Characteristics 11]
TA = O°C to 70°C. VDD = 12V ±10%. VCC = 5V ±10%. VBB = -5V f10%. Vss = OV. unless otherwise noted.
READ. WRITE. AND READ MODIFY/WRITE CYCLE
2107C·1
Symbol
2107C
2107C-2
2107C-4
Units
Parameter
Min.
tREF
Time Between Refresh
tAC
Address to CE Set-Up Time
tAH
Address Hold Time
tcc
tT
CE Off Time
tCD
CE Off to Output Disable Time
Max
Min.
Max.
2
Min.
Max.
2
Min.
2
2
ms
0
0
0
0
ns
50
50
100
100
ns
130
CE Transition Time
130
40
30
30
2107C-1
2107C-2
40
40
30
2
ns
130
130
40
Note
Max.
30
ns
ns
3
Units
Note
ns
3
READ CYCLE
Symbol
2107C
2107C-4
Parameter
Min.
tCY
Cycle Time
380
tCE
CE On Time
210
Max.
Min.
Max.
400
4000
4000
CE Output Delay
130
180
tACC
tWL
twc
Address to 0 utput Access
CE toWE
150
200
0
0
Max.
430
230
tco
WE toCEOn
Min.
260
Min.
Max.
470
4000
300
4000
ns
280
ns
4
300
5
230
250
0
0
0
ns
ns
0
0
0
ns
WRITE CYCLE
2107C-1
Symbol
2107C-2
2107C
2107C-4
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Units
Note
ns
3
Max.
tCY
Cycle Time
380
tCE
CE On Time
210
tw
WE to CE Off
CE toWE
125
125
125
175
ns
tcw
150
150
150
200
ns
tDW
DIN to WE Set-Up
0
0
0
0
ns
tDH
twp
DIN Hold Time
0
0
0
0
ns
WE Pulse Width
50
50
50
100
ns
tWD
WE to Output Disable Time
15
15
15
15
Symbol
Test
400
4000
430
4000
230
Plastic and
Ceramic Package
Typ.
260
470
4000
Unit
300
4000
ns
6
Conditions
Max.'
CAD
Address Capacitance. CS. DIN
5
7
pF
VIN = Vss
CCE
CE Capacitance
10
15
pF
COUT
Data Output Capacitance
5
7
pF
VIN = Vss
VOUT= OV
CWE
WE Capacitance
6
8
pF
VIN = Vss
NOTES:
1. After the application of supply voltages or after extended
6. If WE is low before CE goes high then DIN must be valid
periods of operation without CEo the device must perform a
minimum of one initialization cycle (any valid memory cycle
or refresh cycle) prior to normal operation.
2. tAC is measured from end of address transition.
3. ty = 20 ns.
4. CLOAD = 50 pF. Load = One TTL Gate. Ref = 2.0V.
5. tACC = tAC + tco + 1ty.
when CE goes high.
7. Capacitance measured with Boonton Meter or effective capa-
citance calculated from the equation:
C = ~ with the current equal to a constant 20 mAo
6V
3-30
2107C FAMILY
Read and Refresh Cycle
VIH)1-0
ADDRESS
ANDes
ADDRESS STABLE
K
CD
~=-__+-____________JI
V,L
_
[1J
ADD~ESS
ADDRESS CAN CHANGE
~------------------------------------------'
tT-_
tAH~
VIHC-----t------r-~~------------------------------------------------,
®
I
CE
I
\
1------- tcc ~
-1
V,H
WE CAN
CHANGE
WE
I
I--twc
'\
WECAN
CHANGE
V,L
--
~-----------------~O-------------------·I
- - - - - - - - . tCY - - - - - - - - -
V,H
ADDRESS
ANDes
ADDRESS CAN CHANGE
V,L
"-li-®--s
~--~~--tCE------------
A
V,HC - t
CE
j
o
r---~tw--------,
I
~---------- tcw-----~---- -~
~
I
WE
i
WE CAN CHANGE
---1
I
I
DIN CAN CHANGE
-- -twP-
i, - - - tcc -
-'i
I
N V
I
I
I
WE CAN CHANGE
I
--I ~tDH
_______ tow
)<
1
K
DIN STABLE
D,N
CAN CHANGE
L
--two--HtGH
IMPEDANCE
NOTES: 1. For Refresh cycle, row and column addresses must be stable before tAC and remain stable for entire tAH period.
2. VIL MAX is the reference level for measuring timing of the addresses,
3.
4.
5.
6.
CS, WE, and
DIN-
VIN MIN is the reference level for measuring timing of the addresses, C$, WE, and DIN.
VSS +2.0V is the reference level for measuring timing of CEo
VDD -2V is the reference level for measuring timing of CEo
VSS +2.0V is the reference level for measuring the timing of DOUT.
3-31
STABLE
2107C FAMILY
Read Modify Write Cycle
2107C-1
Symbol
2107C-2
Min_
tRWC
Read Modify Write (RMW) Cycle
tCRW
CE Width During RMW
twc
WE toCE On
tw
WE to CE Off
twp
WE Pulse Width
tow
DIN to WE Setup
tOH
DIN Hold Time
tco
CE to Output Delay
Max.
450
280
0
125
50
0
0
4000
Min.
Access Time
two
WE to Output Disable Time
VIL
2107C-4
Units
Note
~
550
380
0
125
Max_
4000
50
0
0
15
15
230
250
15
Min.
ns
1
Max.
590
420 4000
0
175
100
0
0
280
300
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC-Q)
~ 3
1'\
4000
Min.
180
200
I
ADDRESSES
ANDCS
Max.
500
330
0
125
50
0
0
130
150
tACC
VIH
2107C
Parameter
ADDRESS STABLE
2
i--tAC
K
ADDRESS CAN CHANGE
-
tAH
tCRW
tT~
I--tT
r-
®
II
CE
twc- ~
J
~. r0)
~
DIN CAN CHANGE
j
I
NOTES: 1.
2.
3.
4.
5.
6.
7.
~~
V
~
mCAN
CHANGE
-I--
I--tDW
)
tco
HIGH
t-----tcc~
I---twp-
~
IMPEDAiCE,
1\
tw
~
I--
I--tDH
K
DINCAN
DIN STABLE
CHANGE
!-tWD-->
CD
) j.--
VI\UD
~11
f-
HIGH
IMPEDANCE
tAce
tt of 20 ns.
__
VIL MAX is the reference level for measuring timing of the addresses, CS, WE, and DIN.
VIH MIN is the refarence level for measuring timing of the addresses, CS, WE. and DIN.
VSS +2.0V is the reference level for measuring timing of CEo
VOO -2V is the reference level for measuring timing of CEo
VSS +2.0V is the reference level for measuring the timing of 00UT. CLOAO = 50 pF. Load
WE must be at VIH until end of tCO.
3-32
=
One TTL Gate.
,[L
.J
inter
2109 FAMILY
8,192 x 1 BIT DYNAMIC RAM
2109-3
2109-4
56000,56001 56002,56003
200
250
410
375
475
375
Maximum Access Time (ns)
Read, Write Cycle (ns)
Read-Modify-Write Cycle (ns)
_
_ 8K RAM, Industry Std. 16-Pin Package
_ ±10% Tolerance on All Power Supplies:
_
+12V, +SV, -SV
_
_ Low Power: 462mW Max. Operating,
20mW Max. Standby
_
- Low 100 Current Transients
_
_ All Inputs, Including Clocks, TTL Compatible
Non-Latched Output is Three-State,
TTL Compatible
RAS Only Refresh
64 Refresh Cycles Required Every 2ms
Page Mode Capability
CAS Controlled Output
Allows Hidden Refresh
The Intel® 2109 is a 8,192 word by 1-bit Dynamic MOS RAM which is pin compatible with the industry standard 16K
dynamic RAMs. The 2109 is manufactured with the same masks as the Intel® 2117 and is fabricated with Intel's standard
two layer polysilicon NMOS technology - a production proven process for high reliability, high performance, and high
storage density. As is shown in the block diagram below, the device is organized as two 8K arrays separated by sense
amplifiers and column decoders. The selected 8K array is tested for all of the A.C. and D.C. characteristics necessary to
permit the 2109 to be considered a functionally compatible 8K vilrsion of the 16K device.
The 2109 uses a single transistor dynamic storage cell and advanced dynamic circuitry to aChieve high speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients and ±10% tolerance on all power supplies contribute to the high noise immunity of the 2109 in a system
environment.
The 2109 is available as either an "upper" or "lower" half of the 2117. Row Address 6 (As) selects the operating half, and is
VIH for S6000, S6002, S6064 and S6066 specifications and As is VIL for S6001, S6003, S6065 and S6067 specifications.
The 2109 three-state output is controlled by Column Address Strobe (CAS) independent of Row Address Strobe (RASl.
After a valid read or read-modify-write cycle, data is latched on the output by holding CAS low. The data out pin is returned
to the high impedance state by returning CAS to a high state. The 2109 hidden refresh feature allows CAS to be held lowto
maintain latched data while RAS is used to execute RAS-Only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RASOnly refresh cycles, hidden refresh cycles, or normal read or write cycles on the 64 row address combinations of Ao
through As. As must be at its proper state (VIH or VIL depending on the device specification) for 64 cycle refresh. A write
cycle will refresh stored data on all bits of the selected row except the bit which is addressed.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGBAM
AO
A,
A,
D'N
A,
COUT
A,
A,
As
RAS
DOUT
CAS
WE
NOTE 1: 56000,56002: As ATVIH DURING ROW ADDRESS VALID
S6001, S6003: A6 AT VIL DURING ROW ADDRESS VALID
PIN NAMES
Ao-As
ADDRESS INPUTS
WE
WRITE ENABLE
CAS
COLUMN ADDRESS STROBE
v••
POWER (-5V)
D'N
DATA IN
Vee
POWER (+5V)
DOUT
DATA OUT
Voo
POWER (+12V)
RAS
ROW ADDRESS STROBE
V"
GROUND
3-33
2109 FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT:
AmbientTemperatureUnderBias ... -1O°Cto+80°C
Storage Temperature ............. -65°Cto+150°C
Voltage on Any Pin Relative to Vss
IVss - Vss 24V) ..................... -0.3V to +20V
Data Out Current ............................ 50mA
Power Dissipation ........................... 1.0W
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the de·
vice at these or at any other condition above those indio
cated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1.2j
TA
=
ooe
Symbol
to
7o o e.
Voo = 12V ±10%. VCC = 5V ±10%. Vss = -5V ±10%. VSS = OV. unless otherwise noted.
Parameter
Limits
Min. TypPJ Max. Unit Test Conditions
IILlI
Input Load Current (any input)
0.1
10
J.1.A VIN=VSS to 7.0V. Vss=-5.0V
IILOI
Output Leakage Current for
High Impedance State
0.1
10
Chip Deselected: CAS at VIH.
J.1.A VOUT = 0 to 5.5V
Notes
4
1001
Voo Supply Current. Standby
1.5
mA CAS and RAS at VIH
Iss1
Vss Supply Current. Standby
1.0
50
fJ.A
ICC1
VCC Supply Current. Output
Deselected
0.1
10
1002
Voo Supply Current. Operating
35
fJ.A CAS at VIH
mA 2109-3. tRC = 375ns. tRAS = 200ns
4
33
mA 2109-4. tRC = 410ns. tRAS = 250ns
4
ISS2
Vss Supply Current. Operating.
RAS-Only Refresh. Page Mode
1003
Voo Supply Current. RAS-Only
Refresh
150
1.5
300
5
fJ.A TA = O°C
27
mA 2109-3. tRC = 375ns, tRAS = 200ns
4
26
mA 2109-4. tRC = 410ns, tRAS = 250ns
4
1005
Voo Supply Current. Standby.
Output Enabled
VIL
Input Low Voltage (all inputs)
-1.0
0.8
V
VIH
Input High Voltage (all inputs)
2.4
6.0
V
VOL
Output Low Voltage
0.4
V
10L = 4.2mA
4
VOH
Output High Voltage
V
10H = -5mA
4
2.4
3
mA CAS at VIL. RAS at VIH
NOTES:
1. All voltages referenced to Vss.
2. No power supply sequencing is required. However. Voo, Vee and Vss should never be more negative than -O.3V with respect to Vee as
required by the absolute maximum ratings.
3. Typical values are for Til = 25°C and nominal supply voltages.
4. See the Typical Characteristics Section for values of this parameter under alternate conditions.
5. Icc is dependent on output loading when the device output is selected. Vee is connected to the output buffer only. Vee may be reduced
to Vss without affecting refresh operation or maintenance of internal device data.
3-34
2109 FAMILY
TYPICAL SUPPLY CURRENT WAVEFORMS
=1=
LONG iiAS"ICAll
t
J I i 11111
I J I
RAS ONLY REFRESH
II Ell f
J
r
I
125
Ilam
100
100
(rnA!
75
50
25
J
rt/\
'"
1\
\~~
J
A
~
\....
I~
I
1'10..
75
,"
50
1\
25
IBB
(rnA)
A
0
~
·25
·50
r
It.
'J
It.
1J
IL,
...
1.
"
'V
A
A
I'
.
...t
A.
~\
,
1
·75
125
100
Iss
(rnA)
~
50
lW \
25
o
IItiE I
1\
75
o
J
V
11
r-- fI
~
TIME(ns)
~
T1ME(ns)
Typical power supply current waveforms vs. time are
shown for the RAS/CAS timings of Read/Write, Read/
Write (Long RAS/CAS), and RAS-only refresh cycles. 100
and IBB current transients at the RAS and CAS edges
require adequate decoupling of these supplies. Decoupling recommendations are provided in the Applications
section.
,
III
J IV
100
...
i-200
V\\
300
500
The effects of cycle time, Voo supply voltage and ambient
temperature on the 100 current are shown in graphs
included in the Typical Characteristics Section. Each
family of curves for 1001, 1002, and 1003 is related by a
common point at Voo = 12.0V and T A = 25° C for two given
tRAS pulse widths. The typical 100 current for a given
condition of cycle time, Voo and TA can be determined by
combining the effects of the appropriate family of curves.
CAPACITANCE [1J
TA = 25°C, VOO = 12V±100f0, VCC = 5V±100f0, VBB = -5V±100f0, Vss = OV, unless otherwise specified.
Symbol
400
TIME(ns)
Typ.
Max.
Unit
CI1
Address. Data In
Parameter
3
5
pF
CI2
RAS Capacitance, WE Capacitance
4
7
pF
CI3
CAS Capacitance
6
10
pF
Co
Data Output Capacitance
4
7
pF
NOTES:
1. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation:
C = !..::ll with .J.V equal to 3 volts and power supplies at nominal levels .
.J.V
3·35
2109 FAMILY
A.C. CHARACTERISTICS[1,2,3]
TA = Doe to 7Doe, VDD = 12V ±1D%, Vcc = 5V ±1D%, Vss = -5V ±1D%, Vss = DV, unless otherwise noted.
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
5ymbol
2109-3
56000,56001
Max.
Min.
Parameter
tRAC
Access Time From RAS
tCAC
Access Time From CAS
tREF
Time Between Refresh
tRP
RAS Precharge Time
tcPN
tCRP
CAS Precharge Timelnon-pagecycles)
CAS to RAS Precharge Time
2109-4
56002,56003
Min.
Max.
200
135
2
250
165
2
150
25
-20
35
165
250
0
35
Unil
Notes
ns
4,5
4,5,6
ns
ms
tCSI-I
CAS Hold Time
tASR
Row Address Set-Up Time
tRAH
Row Address Hold Time
120
25
-20
25
135
200
0
25
tASC
Column Address Set-Up Time
-10
-10
ns
tCAH
Column Address Hold Time
55
120
3
0
75
160
3
0
ns
tRCO
RAS to CAS Delay Time
tRSH
RAS Hold Time
tAR
Column Address Hold Time, to RAS
tT
Transition Time (Rise and Fall)
tOFF
Output Buffer Turn Off Delay
65
50
60
ns
ns
ns
85
ns
7
ns
ns
ns
ns
ns
50
70
ns
8
ns
READ AND REFRESH CYCLES
tRC
Random Read Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
tRCS
Read Command Set-Up Time
tRCH
Read Command Hold Time
375
200
135
0
0
10000
10000
410
250
165
0
0
ns
10000
10000
ns
ns
ns
ns
WRITE CYCLE
tRC
Random Write Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
twcs
Write Command Set-Up Time
tWCH
Write Command Hold Time
tWCR
Write Command Hold Time, to RAS
twp
Write Command Pulse Width
tRWL
Write Command to RAS Lead Time
tCWL
Write Command to CAS Lead Time
tos
Data-In Set-Up Time
tOH
Data-In Hold Time
tOHR
Data-In Hold Time, to RAS
375
200
135
10000
10000
410
250
165
ns
10000
10000
ns
ns
-20
75
160
75
100
100
0
75
160
-20
55
120
55
80
80
0
55
120
ns
9
ns
ns
ns
ns
ns
ns
ns
ns
READ-MODIFY-WRITE CYCLE
tRwe
Read-Modify-Write Cycle Time
tRRW
RMW Cycle RAS Pulse Width
tCRW
RMW Cycle CAS Pulse Width
tRWO
RAS to WE Delay
375
245
180
160
tcwo
CAS to WE Delay
95
Notes: See following page for A.C. Characteristics Notes.
3-36
10000
10000
475
305
230
200
125
ns
10000
10000
ns
ns
ns
9
ns
9
2109 FAMILY
WAVEFORMS
READ CY CLE
V,H
RAS
CD
Vil
®tcRP-1
V,H
CAS
tRe
l®
r;-
CD
1----
t ASR
'1H
_ t RAH
~
ADDRESSES
Vil
-
tRCO
I
Vil
ADDRESS
x.. ){r
tAR-----
tAse
. t RSH
teAs
'I
l::itReH0
L-teAe
1----------.--~.-----tRAC ---.---.--~,--" -----"-
HIGH
VOH
DOUT
VOL
~1----------------tRe
I.
CD i'l (2)
V,H
V,L
eDteRP
=
V,H
'1L
--1
I------ tOFF ---I
r-V-A-U-O------.L®
J
ADDRESSES
VIL
----------~-~---------..,
l-tRP~
tRAS
~
1--------------~tesH·---------------
t:-
t RCO
~~I'
){CD(2)
t RSH
CD
II
tASR--
V,H
--
'---tRAH--!
ROW:
ADDRESS
tAse-
l(
r-
X
r\\\
-tAR--
lit
I
t------~
f.------- t e A H - -
K
COLUMN
ADDRESS
--··---~tcWl--
~
V,H
~
V'L
r-- 1--tePN~~1
teAs
i'(3)
t RWL
WE
-0
\
----------------~IM~P~E~O~A~N~C~E-------------------------------------------~~ DATA OUT
~~-----4
WRITE CYCLE
RAS
---tcPN_1
J!
I
!#
_
X
COLUMN
ADDRESS
I
V'L
RP
I
t---~-------l
1-----teAH --.-
,j_t RCS
t
Ir
tCSH
\\\\ l®
--"!
ROW
V,H
WE
--I -
tRAS
-~
-.--.-----
~tweH----:jI
. - - tWGS ~
'weR
r--®tDS~
~tDH®-
XCD(3)
V,H
O'N
V'L
K
tOHR
Dour
NOTES;
VOH
VOL
HIGH
IMPEDANCE
1,2. V 1H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT"
5, tOFF IS MEASURED TO lOUT" IILO I·
6. tos AND tOH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
7. tRCH IS REFERENCED TO THE TRAILING EOGE OF CAs OR RAS, WHICHEVER OCCURS FIRST.
S.
;;~r :~~~~~~~e~,~Td~ ~~~;E~~P~~t:EL~:i~ARt~6Ct:ECE~C~~~6~~gE~~~DRBAYS~ CAS-
A.C. CHARACTERISTICS NOTES (From Previous Page)
1. All voltages referenced to Vss.
2. Eight cycles are required after power-up or prolonged periods
(greater than 2msl of RAS inactivity before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
3. A.C. Characteristics assume tT = 5ns.
4. Assume that tRCD S tRCD (max.l. If tRCD is greater than tRCD
(max.1 then tRAC will increase by the amount that tRCD exceeds
tRCD (max.l.
5. Load = 2 TTL loads and 100pF.
6. Assumes tRCD ? tRCD (max.1.
7. tRCD (max.1 is specified as a reference point only; if tRCD is less
than tRCD (max.1 access time is tRAC, iftRCD is greater than tRCD
(max. I access time is tRCD + tCAC.
8. tT is measured between V,H (min.l and V,L (max.l.
9. twcs, tCWD and tRWO are specified as reference pOints only. If
twcs 2" twcs (min.1 the cycle is an early write cycle and the data
out pin will remain high impedance throughout the entire
cycle. If tCWD? tcwD (min.1 and tRwD 2" tRwD (min.l, the cycle is
a read-modify-write cycle and the data out will contain the data
read from the selected address. If neither of the above
conditions is satisfied, the condition of the data out is
indeterminate.
3-37
2109 FAMILY
WAVEFORMS
READ-MODIFY-WRITE CYCLE
IRwe
1-,,,--1
tRRW
I
JJ
;'-~
,8 tcRP __ 1
- ' HtRAIi
:i)
---'Ae
tAs~t·
tASRr--
ADDRESSES
"'"
IRCD
~:: _}{~I AO~~~SS
(iJ
X
\\\
~
_ - t c P N -__1
tRSH
tcRW-
®
'RWL-
1-
- . - - tCWL - - -
ICAH
~ ;g6~~s~
I-'' --y
'RWO
1RCsi"--
lewD
(2)(iY
'I - I--'OH®
0'"
){(1)
-
~tCAC----1
tRAC
,
(iJ I
DATA IN
VALID
~
HIGH
VALID
IMPEDANCE
DATA OUT
0
K
@
.I-'
oe.
,0
RAS-ONL Y REFRESH CYCLE
r--,,,-I
I---------------,,'---------------~
I------------,,"~--------I
V'H
RAS
----,,.,-L
CD
v"
---l
IJ.
JlI
0
~
t CRP
~
''\~___
®
»:
CD AO'h~~SS ) (
V"-~~0~~~~-~~-----------------------------
ADDRESSES V!H
VOH
DOUT
HIGH
VOL--------------------,~M~PE~D~AN~C~E--------------------
HIDDEN REFRESH CYCLE
f-1·-----tRc~---~
ADDRESSES
tRCH
CD
v" - - - + - ' \
1
0
I
~-'·,l<".~.,.."-----------VA-L.,~I"'"~A-T-A------------.:..1-,19.;;0;,."_'
.
____
VaH
DOUT
VOL
NOTES:
1,2.
3,4.
5.
6.
7.
8.
CD
,H
V MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT '
tOFF IS MEASURED TO tOUT";; IILO I.
tos AND tOH ARE REFERENCED TO CAS OR WE. WHICHEVER OCCURS LAST.
tRCH IS REFERENCED TO THE TRAllIr.JG EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST.
teAP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CAS~
ONL Y CYCLE (I.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
3-38
2109 FAMILY
TYPICAL CHARACTERISTICS [1 J
GRAPH 1
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS. VOO
GRAPH 2
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS. VBB
1.2
1.2
~
1.1
g
.
~
....
~
~
I'-........
1.0
"
.
CD
~
~
Vee
0.7
10
I"
11
~
12
13
TA = 70 C
Voo'" 12.0V-
0.8
-4.5
"..sffi
1.0
~
O.S
:::>
u
/'"
Ii!
"1 4 .5V
0
E
40
0.6
so
60
~
;;
12
13
O.S
r--o
a:
:::>
20
I
S
10
E
10
-
a:
30
~
20
~375m
:::>
u
~"500n'
Ii!
~
--'
"..s....
40
ffia:
tRAS = 200ns
30
'"I
I
I
tRAS - 200ns
tRG '" 375ns
1
I
S
E
tRI " 750n,
tRAS '" 500ns
10
tRel "7500.
tRAS '" 200ns
0
200
400
600
SOO
tRC - CYCLE TIME (ns)
1000
o
10
so
Voo '" 12.0V
Vas'" -S.OV
40
~
it:
20
60
50
:::>
u
Ii!
40
r--
GRAPH 9
TYPICAL OPERATING CURRENT
1002 VS. AMBIENT TEMp·ERATURE
50
ffia:
30
20
--
TA - AMBIENT TEMPERATURE ('C)
TA '" 2S"C
:::>
--
0.6
0.4
14
GRAPH 8
TYPICAL OPERATING CURRENT
"..s....
6.0
Voo'" 13.2V
Vas == -4.5V
1.0
'"I
Vas == -s.OV
....
;0
E
.....
1002 VS. VOO
~----~~--_4----~~~:-~O~
5.5
1.2
Voo - SUPPL Y VOL T AGE (VOLTS)
TA '" 25 C
~
a:
a:
:::>
u
E
1002 VS. tRC
it:
"..s....ffi
:::>
10
50r-----,------,------,------,
5.0
GRAPH 6
TYPICAL STANDBY CURRENT
1001 VS. AMBIENT TEMPERATURE
0.4
20
4.5
Vee - SUPPL Y VOL T AGE (VOL TS)
... /
I
=lO.BV
Vas =-S.5V-
GRAPH 7
TYPICAL OPERATING CURRENT
a:
a:
u
0.7
4.0
-6.0
TA '" O"C
Vas = -4.5V
TA - AMBIENT TEMPERATURE ( C)
"..sffi
-5.5
1.2
a:
a:
T A = 70 C
Voo'" 12.0VV66i-5.5V
1.4
....
Vee
~
1001 VS. VOO
V
/"
Voo
O.S
u
1.4
V
40
-5.0
GRAPH 5
TYPICAL STANDBY CURRENT
O.S
.
"1 5 .OV
GRAPH 4
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS.
AMBIENT TEMPERATURE
/'
0.9
?
Vas - SUPPl Y VOL TAGE (VOL IS)
V
:S
u
0.7
-4.0
14
1.0
~
0.9
Voo - SUPPL Y VOL T AGE (VOLTS)
1.0
o
u
1.1
u
Vee
1. 1
0.7
?
4.5V
1.2
0.9
1.0
u
TA '" 70 C
r-- Vas = -5.5V
O.S
~
~
.t::
0.9
~
~
1. 1
u
............... t'-
~
0
0
1.2
~
u
:S
GRAPH 3
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS. VCC
11
12
13
Voo - SUPPL Y VOL T AGE (VOL TS)
NOTES: See following page for Typical Characteristics Notes.
3-39
14
o
o
20
40
60,
TA - AMBIENT TEMPERATURE ( C)
so
2109 FAMILY
TYPICAL CHARACTERISTICS
[1]
GRAPH 11
TYPICAL RAS ONLY
REFRESH CURRENT
1003 VS. VOO
GRAPH 10
TYPICAL RAS ONLY
REFRESH CURRENT
1003 VS. tRC
50
!
iiia:
30
...
a:
u
;;
!
...
iiia:
a:
:J
:J
~
~
'-...........
M
C
;;
40
!
...
i:'a:i
30
a:
10
iil
r-...
8
51
200
600
400
800
!
a:
c
10
=
!
...
12.0V
iiia:
Vae '" -S.OV
a:
:J
u
30
13
14
~
~ ~=~50n5
~
:J
~
teAS -
51
'rns
20
40
80
60
GRAPH 15
TYPICAL PAGE MODE CURRENT
1004 VS. AMBIENT TEMPERATURE
50
Voo"" 12,DV
V BB = -5.0V
1=
:J
0
I
20
:z:
.P
...
80
a:
:J
u
60
_
i:'a:i
'z"
in
...............
5
~
~
//
-.......
o
0
51
20
=1
=
T A 25"C
VOO=12.0V
V BB -5,5V
Vcc =4,5V
/
40
:J
I
/
VOH - OUTPUTVQLTAGE (VOLTS)
•
1001 @VOO= 13.2V, TA = O°C
•
1002 or 1003 @ tRAS = 200ns, tRC =
375ns, VOO = 12.0V, TA = 25°C
•
1002 or 1003 @ tRAS = 500ns, tRC =
750ns, VOO = 12.0V, TA = 25°C
o
1004 @ tCAS = 135ns, tpc = 225ns,
VOO = 12.0V, TA = 25°C
t:.
1004 @ tCAS = 350ns, tpc = 500ns,
VOO = 12.0V, TA = 25°C
The typical 100 current for a given combination of cycle time, V 00 supply
o
o
o
ambient temperature dependence of 1001,
1002,1003 and 1004 is shown in related
graphs. Common points of related curves
are indicated:
100
100
1. The cycle time, VOd'supply voltage, and
voltage and ambient temperature may be
VOL - OUTPUT VOL T AGE (VOLTS)
3·40
determined by combining the effects of
the appropriate family of curves.
2109 FAMILY
D.C. AND A.C. CHARACTERISTICS, PAGE MODE[7.8.11]
TA
= O°C
to 70°C, VDD
= 12V±10%, Vee = 5V±100f0,
VBB
= -5V±10%,
Vss
= OV,
unless otherwise noted.
For Page Mode Operation order: 2109-3* 56064,56065 or 2109-4* 56066, 56067.
I
Symbol
tpc
Parameter
2109-3
86064,86065
Min.
Max.
2109-4
86066,56067
Min_
Max_
Unit
Page Mode Read or Write Cycle
225
275
ns
tpCM
Page Mode Read Modify Write
270
340
ns
tcp
CAS Precharge Time, Page Cycle
80
100
tRPM
RAS Pulse Width, Page Mode
200
10,000
250
10,000
tCAS
CAS Pulse Width
135
10,000
165
10,000
ns
1004
Voo Supply Current Page Mode,
Minimum tpc, Minimum tCAS
26
mA
30
Notes
ns
ns
9
'56064, 56066: A6 at VIH during Row Address Valid.
56065, 56067: A6 at VIL during Row Address Valid.
WAVEFORMS
PAGE MODE READ CYCLE
~----------------------------tRPM------------------------------~1~~
_V1HC
RAS
~~--------+-----------------------------~(I~f---!-.-----------------~tRP~
ADDRESSES V
V'H
!L--~~~~~~~~~--------t--'~~~~~----~f~~~~~~--~-------------------
WE
V 1HC
+-__.1
V,L ______
V OH
Dour VOL ---------------------....;~
NOTES:
1,2. V 1H MIN AND V 1L MAX ARE REFERENCE lEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. VOH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF Dour5. tOFF IS MEASURED TO lOUT";; IILO I6. tRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST.
7. ALL VOL TAGES REFERENCED TO Vss.
8. AC CHARACTERISTIC ASSUME tr = 5ns.
9. SEE THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNDER AL TERNATE CONDITIONS.
10. tcRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (i.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
11. ALL PREVIOUSLY SPECIFIED A.C. AND D.C. CHARACTERISTICS ARE APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE (i.e., 2109-3, S6064 OR 56065 WILL OPERATE AS A 2109-3).
3-41
2109 FAMILY
PAGE MODE WRITE CYCLE
_
V 1HC
RAS V,L
WE
V 1HC
V,L------r-----~~--~~----------~~----~~--------~r---_f~------~----~~-----------
PAGE MODE READ-MODIFY-WRITE CYCLE
_
V 1H
RAS
V 1L
ADDRESSES
V 1H
V"
NOTES:
1.2.
3,4.
5.
6.
7.
V 1H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
VOH MIN AND VOL MAX ARE REFERENCE lEVELS FOR MEASURING TIMING OF DOUT '
tOFF IS MEASURED TO lOUT";; ['lO I.
tDS AND tOH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
tcRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (I ,e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
3-42
2109 FAMILY
APPLICATIONS
The 2109 is packaged in a standard 16-pin DIP by
multiplexing 14 address bits onto 7 input pins (Ao-A6). The
7 bit address words are latched into the 2109 by two TTL
clocks, Row Address Strobe (RAS) and Column Address
Strobe (CAS). Since the 2109 is an 8K memory device, only
13 of the 14 address bits are required and the 14th address
bit must be at VIH (for S6000, S6002, S6064 or S6066) or VIL
(for S6001, S6003, S6065 or S6067) during Row Address
Valid. This means it is not possible to simply tie input pin
A6 high or low, since it supplies two system addresses to
the memory array. Input pin A6 must be at the appropriate
level (determined by the "S"-specification) during the row
address valid period and then changed to the proper high
order address during the column address valid period.
RAS/CAS TIMING
RAS and CAS have minimum pulse widths as defined by
tRAS and tCAS respectively. These minimum pulse widths
must be maintained for proper device operation and data
integrity. A cycle, once begun by driving RAS and/or CAS
low must not be ended or aborted prior to fulfilling the
minimum clock signal pulse width(s). A new cycle can not
begin until the minimum precharge time, tRP, has been
met.
DATA OUTPUT OPERATION
The 2109 Data Output (DOUT), which has three-state
capability, is controlled by CAS. During CAS high state
(CAS at VIH) the output is in the high impedance state. The
following table summarizes the DOUT state for various
types of cycles.
READ CYCLE
A Read cycle is performed by maintaining Write Enable
(WE) high during a RAS/CAS operation. The output pin of
a selected device will remain in a high impedance state
until valid data appears at the output at access time.
Intel 2109 Data Output Operation
for Various Types of Cycles
Device access time, tACC, is the longer of the two
calculated intervals:
1. tACC = tRAC OR 2. tACC = tRCD
+ tCAC
Type of Cycle
DOUT State
Read Cycle
Data From Addressed
Memory Cell
HI-Z
HI-Z
HI-Z
Data From Addressed
Memory Cell
Indeterminate
Fast Write Cycle
RAS-Only Refresh Cycle
CAS-Only Cycle
Read/Modify/Write Cycle
Access time from RAS, tRAC, and access time from CAS,
tCAC, are device parameters. Row to column address
strobe delay time, tRCD, are system dependent timing
parameters. For example, substituting the device parameters of the 2109-3 yields:
Delayed Write Cycle
HIDDEN REFRESH
3. tACC = tRAC = 200nsec for 25nsec :StRCD :S65nsec
OR
4. tACC = tRCD + tCAC = tRCD + 135 for tRCD > 65nsec
A feature of the 2109 is that refresh cycles may be
performed while maintaining valid data at the output pin.
This feature is referred to as Hidden Refresh. Hidden
Refresh is performed by holding CAS at VIL and taking
RAS high and after a specified precharge period (tRP),
executing a "RAS-Only" refresh cycle, but with CAS held
low (see Figure below).
Note that if 25nsec :StRCD :S65nsec device access time is
determined by equation 3 and is equal to tRAC. If tRCL
>65nsec, access time is determined by equation 4. This
40nsec interval (shown in the tRCD inequality in equation 3)
in which the falling edge of CAS can occur without
affecting access time is provided to allow for system
timing skew in the generation of CAS.
REFRESH CYCLES
Each of the 64 rows of the 2109 must be refreshed every 2
milliseconds to maintain data. Any memory cycle:
RAS
1. Read Cycle
2. Write Cycle (Early Write, Delayed Write or ReadModify-Write)
3. RAS-only Cycle
refreshes the selected row as defined by the low order
(RAS) addresses. As must be held at the proper level (VIH
or VIL depending on specification) to perform 64 cycle
refresh operation, but may be driven high and low for 128
cycle RAS-only refresh without affecting device data
retention. Any Write cycle, of course, may change the
state of the selected cell. Using a Read, Write, or ReadModify-Write cycle for refresh is not recommended for
systems which utilize "wire-OR" outputs Since output bus
contention will occur.
-{
MEMORY
CYCLE
/
CAS
HIGH Z
DOUT
<
DATA
)---
This feature allows a refresh cycle to be "hidden" among
data cycles without affecting the data availability.
POWER ON
The 2109 requires no power on sequence providing
absolute maximum ratings are not exceeded. After the
application of supply voltages or after extended periods of
bias (greater than 2 milliseconds) without clocks, the
device must perform a minimum of eight initialization
cycles (any combination of cycles containing a RAS clock,
such as RAS-Only refresh) prior to normal operation.
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A RASonly refresh cycle maintains the DOUT in the high
impedance state with a typical power reduction of 20%
over a Read or Write cycle.
3-43
2109 FAMILY
POWER SUPPLY DECOUPLING/DISTRIBUTION
8K UPGRADE FOR 4K SYSTEMS
It is recommended that a O.lI'F ceramic capacitor be
connected between Voo and Vss at every other device in
the memory array. A O.lI'F ceramic capacitor should also
be connected between Vss and Vss at every other device
(preferably the alternate devices to the Voo decouplingl.
For each 16 devices, a lOI'F tantalum or equivalent
capacitor should be connected between Voo and Vss near
the array. An equal or slightly smaller bulk capacitor is
also recommended between Vss and Vss for every 32
devices.
The 2109 can be used to upgrade existing 4K (Intel21 04A)
memory systems with minimal redesign. The 2109
maintains many of the features of the 4K RAMs. For
example, the latched data output of the 4Ks can be
emulated by holding CAS low to maintain data out valid.
Hidden refresh capability for the 4Ks is also maintained
with the 2109. The 64 cycle refresh operation of the 2109
m"kes it compatible with 4K systems.
To upgrade a 4K system to accept the 2109, an extra
memory address multiplexer must be implemented to
replace the Chip Select (CS) input of the 4Ks. The
replacement circuitry is shown in the figure below, and
involves some gating to control the output of the
multiplexer during row and column address valid periods
and also some control to handle the multiplexer during
refresh operation.
The Vee supply is connected only to the 2109 output
buffer and is not used internally. The load current from the
Vee supply is dependent only upon the output loading and
is associated with the input high level current to a TTL gate
and the output leakage currents of any OR-tied 2109's
(typically lOOI'A or less total). Intel recommends that a 0.1
or O.OlI'F ceramic capacitor be connected between Vee
and Vss for every eight memory devices.
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution system on the array board should be minimized. It is
recommended that the Voo, Vss, and Vss supply lines be
gridded both horizontally and vertically at each device in
the array. This technique allows use of double sided
circuit boards with noise performance equal to or better
than multi-layered circuit boards.
COLUMN
ENABLE
A6 '" VIH
~:gg
Vee
?6..
-:
S6064
86066
X>--+---i_"
I~\
A6 '" VIL
86001
86003
S6065
56067
ADOR 12
DECOUPLING CAPACITORS
o ~ O.lIlF TO VOD TO VSS
S ~ O.lIlF Vss TO Vss
e ~ O.OlIlF Vce TO Vss
SAMPLE P.C. BOARD LAYOUT EMPLOYING VERTICAL
AND HORIZONTAL GRIDDING ON ALL POWER SUPPLIES.
3-44
A61C'S)
TO MEMORY
ARRAY
2111A/8111A-4*
256 x 4 BIT STATIC RAM
2111A-2
2111A
2111A-4
250 ns Max.
350 ns Max.
450 ns Max.
Decoded: On Chip Address
• Fully
Decode
Inputs Protected: All Inputs Have Pro• tection
Against Static Charge
Low Cost Packaging: 18 Pin Plastic Dual
• In-Line
Configuration
Low Power: Typically 150 mW
• Three-State
Output: OR-Tie Capability
•
Data Input and Output
• Common
Single
+5V
Voltage
• Directly TTLSupply
Compatible:
All Inputs and
• Output
Static MOS: No Clocks or Refreshing
• Required
Simple Memory Expansion: Chip Enable
• Input
The Intel® 2111A is a 256 word by 4-bit static random access memory element using N-channel MOS devices integrated on a
monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is
read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2111A is designed for memory applications in small systems where high performance, low cost, large bit storage, and
simple interfacing are important design objectives.
It is directly TTL compatible in all respects: inputs, outputs. and a single +5V supply. Separate chip enable (CE) leads allow
easy selection of an individual package when outputs are OR-tied.
The Intel® 2111A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.
Intel's silicon gate technology also provides excellent protection against contamination. This permits the use of low cost
plastic packaging.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
AD
0
~~-r--'
@
----------0
(3)
A3
vee
AD
A,
A,
A,
I/O,
A,
A,
1/°2
A3
®
A1
A,
R/W
AD
eE,
A3
1/°3
A,
1/04
A,
1/°4
A6
1/0 3
A,
A,
1/0 2
A6
GND
110,
A,
00
tE2
(2)
-------0 GND
ROW
SELECT
CD
MEMORY ARRAY
32 ROWS
32 COLUMNS
@
A4
@
1/01
00
1/02
INPUT
DATA
CONTROL
1/03
1/04
PIN NAMES
AO-A7
ADDRESS INPUTS
00
OUTPUT DISABLE
RAV
REAO/WR1TE INPUT
eEl
CHIP ENABLE 1
tE2
CHIP ENABLE 2
1/0,- 1/04
DATA INPUT/OUTPUT
o '"
"All 8111A-4 specifications are identical to the 2111A-4 specifications.
3-45
Vee
PIN NUMBERS
2111A FAMILY
'COMMENT:
ABSOLUTE MAXIMUM RATINGS*
Stresses above those listed under ''Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Under Bias ..... _lOoC to SO°C
Storage Temperature ........... _65°C to +150°C
Voltage On Any Pin
With Respect to Ground ....... "
-0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A = O°C to 70°C, Vcc = 5V ±5% , unless otherwise specified.
TypJ1J
Max.
Unit
III
Input Load Current
1
10
pA
VIN = 0 to 5.25V
ILOH
1(0 Leakage Current
1
10
pA
Output Disabled, VI/O = 4.0V
ILOL
1(0 Leakage Current
-1
-10
pA
Output Disabled, VI/0=0.45V
ICCl
Power Supply
Current
2111A,2111A-4
2111A-2
35
45
55
65
mA
ICC2
Power Supply
2111A,2111A-4
60
2111A-2
70
Symbol
Parameter
Current
Min.
mA
VIL
V IH
Input Low Voltage
-0.5
O.S
V
Input High Voltage
2.0
Output Low Voltage
Vcc
0.45
V
VOL
Output High
VOH
V
Test Conditions
VIN = 5.25V
11/0 = OmA, TA = 25°C
V IN = 5.25V
11/0=OmA, TA = O°C
10L = 2.0mA
2111A,2111A-2
2.4
V
IOH = -200pA
2111A-4
2.4
V
10H = -150pA
Voltage
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
AMBI~NT TE1MPER1TuRE
-15
\~ --:::::
70°C
\\
\\
-10
'\
-5
o
O'C
25°C
1
,
!
Vcc"'4.75V __ ~
'\. iUTPUi "HIGH" TYPi'CAL
~
VOH (VOLTS)
NOTE: 1. Typical values are for TA
=
VOL (VOLTS)
2SoC and nominal supply voltage.
3-46
2111A FAMILY
A.C. CHARACTERISTICS FOR 2111A-2 (250 ns ACCESS TIME)
READ CYCLE T A = O°C to 70°C. VCC = 5V ±5%. unless otherwise specified.
Symbol
Parameter
T yp.[1]
Min.
Max.
Unit
Test Condit,ons
tRC
tA
Access Time
250
ns
ns
tco
Chip Enable To Output
180
ns
t r • tf = 20ns
Input Levels
too
tOF [3)
Output Disable To Output
130
ns
Timing Reference
180
ns
Load
Read Cycle
tOH
250
Data Output to High Z State
0
Previous Read Data Valid
after change of Address
40
ns
= 0.8V or 2.0V
= 1.5V
= 1 TTL Gate
and CL = 100pF.
WRITE CYCLE
Symbol
Typ.[1)
Min.
Parameter
Max.
Unit
170
ns
twc
tAW
Write Cycle
20
ns
tcw
Chip Enable To Write
150
ns
Write Delay
tow
Data Setup
150
ns
tOH
twp
Data Hold
ns
Write Pulse
0
150
tWR
Write Recovery
0
ns
ns
tos
Output Disable Setup
20
ns
CAPACITANCE
CIN
ClIO
t r • tf = 20ns
Input Levels = 0.8V or 2.0V
Timing Reference = 1.5V
Load = 1 TTL Gate
and CL = 100pF.
[2)
TA = 25°C. f = 1 MHz
Test
Symbol
Test Conditions
Input Capacitance
(All Input Pins) VIN
= OV
I/O Capacitance VI/O = OV
Limits (pF)
Typ.[l) Max.
4
8
10
15
WAVEFORMS
READ CYCLE
WRITE CYCLE
------- tRc-----~1
I--------~c-------I
ADDRESS
ADDRESS
CHIP
ENABLES
(CEi, CE21
ENABLES
CHIP
___-"""'I----tcw - - - -I
iCE1 ·CE2 )
_-+___"I-too--I
~:~ :~t-~-~-~~~~j---D-~"'TA-AL-~DU-T---+
OUTPUT
DISABLE
DATA I/O
READ!
WRITE
--tAw-II"- - - - - - ' 1
NOTES: 1. Typical values are for TA = 25°C and nominal supply voltage.
2, This parameter is periodically sampled and is not 100% tested.
3, tOF is with respect to the trailing edge of CE1. CE2. or 00, whichever occurs first.
3-47
2111A FAMilY
2111A (350 ns ACCESS TIME)
A.C. CHARACTERISTICS
READ CYCLE T A = O°C to 70°C. Vee = 5V ±5%. unless otherwise specified.
Symbol
Parameter
Min.
Read Cycle
tRe
T [1]
yp.
Max.
350
Unit
Test Conditions
ns
Access Time
350
ns
t r • tf = 20ns
teo
Chip Enable To Output
240
ns
too
tOF [2J
Output Disable To Output
180
ns
Input Levels = 0.8V or 2.0V
Timing Reference = 1.5V
150
ns
Load = 1 TTL Gate
tA
-----
f----
.~-
tOH
Data Output to High Z State
0
and CL = 100pF.
Previous Read Data Valid
after change of Address
40
ns
WRITE CYCLE
Symbol
Min.
Parameter
[1]
Typ.
Max.
Unit
twe
Write Cycle
220
ns
tAW
Write Delay
20
ns
200
ns
200
ns
tew
Chip Enable To Write
tow
Data Setup
tOH
twp
Data Hold
- - f.....
._----_. ._--.
----~--.-
Write Pulse
tWR
Write Recovery
tos
Output Disable Setup
0
~. 20()- t - - - - t - -..
ns
ns
0
ns
20
ns
Test Conditions
t r • tf = 20ns
Input Levels = 0.8V or 2.0V
Timing Reference = 1.5V
Load = 1 TTL Gate
and CL = 100pF.
2111A-4 (450 ns ACCESS TIME)
A.C. CHARACTERISTICS
READ CYCLE T A = O°C to 70°C. Vee = 5V ±5%. unless otherwise specified.
Symbol
tRC
Parameter
Read Cycle
Min.
T yp.[1J
Max.
Unit
tA
Access Time
450
ns
teo
Chip Enable To Output
310
ns
too
tOF [2J
Output Disable To Output
250
ns
200
ns
tOH
Data Output to High Z State
Previous Read Data Valid
after change of Address
Test Conditions
ns
450
0
t r • tf = 20ns
Input Levels = 0.8V or 2.0V
Timing Reference = 1.5V
Load = 1 TTL Gate
and CL = 100pF.
ns
40
WRITE CYCLE
Symbol
Parameter
twe
Write Cycle
tAW
tew
Min.
Typ.[1]
Max.
Unit
Test Conditions
270
ns
Write Delay
20
ns
t r • tf = 20ns
Chip Enable To Write
250
ns
Input Levels = 0.8V or 2.0V
Timing Reference = 1.5V
tow
Data Setup
250
ns
tOH
Data Hold
0
ns
twp
Write Pulse
250
ns
tWR
Write Recovery
0
ns
t DS
Output Disable Setup
20
ns
NOTES: 1. Typical values are for TA = 25° C and nominal supply voltage.
2. tOF is with respect to the trailing edge of CEI. eE2. or 00. whichever occurs first.
3-48
Load = 1 TTL Gate
and CL = 100pF.
intel"
2112A
256 X 4 BIT STATIC RAM
2112A-2
2112A
2112A-4
250 ns Max.
350 ns Max.
450 ns Max.
• Fully Decoded: On Chip Address
Decode
• Inputs Protected: All Inputs Have Protection Against Static Charge
• Low Cost Packaging: 16 Pin Plastic Dual
In-Line Configuration
• Single +5V Supply Voltage
• Directly TTL Compatible: All Inputs and
Outputs
• Static MOS: No Clocks or Refreshing
Required
• Simple Memory Expansion: Chip Enable
Input
• Low Power: Typically 150 mW
• Three-State Output: OR-Tie Capability
The Intel® 2112A is a 256 word by 4-bit static random access memory element using N-channel MaS devices integrated on a
monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is
read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2112A is designed for memory applications in small systems where high performance, low cost, large bit storage, and
simple interfacing are important design objectives.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate chip enable (CE) lead allows
easy selection of an individual package when outputs are OR-tied.
The Intel® 2112A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance, easy-to-use MaS circuits and provides a higher functional density on a monolithic chip than either
conventional MaG technology or P-channel silicon gate technology.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
AD
·3
Vee
Ao
A,
®
----0
0
®
----0
liD,
A4
A,
A,
WE
A,
1/°2
A3
1/°3
A3
Ao
CE
A4
1/°4
A4
A5
1/04
A,
®
A, 0
ROW
SELECT
CD
®
MEMORY ARRAY
32 ROWS
32 COLUMNS
A5
A.
1(03
A,
1/02
GND
I/O,
A.
A,
1/01
®
@
WE
1/02
eE
@
1/03
INPUT
DATA
CONTROL
® ®
A5
1/04
PIN NAMES
-@
WE
3-49
A6
(7)
A7
Vee
GND
2112A FAMILY
'COMMENT:
ABSOLUTE MAXIMUM RATINGS*
Stresses above those listed under 'Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Under Bias ..... -lOoC to 80°C
Storage Temperature . . . . . . . . . . . _65°C to +150°C
Voltage On Any Pin
With Respect to Ground . . . . . . . ..
-0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . .. 1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A = O°C to 70°C, Vcc = 5V ±5% unless otherwise specified.
Symbol
Parameter
Typ.!lJ
Min.
Max.
Unit
Test Conditions
III
Input Cu rrent
1
10
fJ.A
ILOH
I/O Leakage Current
1
10
fJ.A
VIN = 0 to 5.25V
Output Disabled, VI/0=4.0V
ILOL
I/O Leakage Current
-1
-10
fJ.A
Output Disabled, VI/0=0.45V
ICCl
Power Supply
Current
2112A, 2112A-4
2112A-2
55
65
mA
VIN = 5.25V, 1110 = OmA
TA =25°C
ICC2
Power Supply
Current
2112A, 2112A-4
2112A-2
mA
VIN = 5.25V, 11/0 = OmA
TA = O°C
VIL
V1H
Input "Low" Voltage
-0.5.
60
70
0.8
Input "High" Voltage
2.0
V
VOL
VO H
Output "Low" Voltage
VCC
+0.45
Output "High"
35
45
V
V
10L = 2.0 mA
2112A, 2112A-2
2.4
V
10H = -200fJ.A
2112A-4
2.4
V
10H = -150fJ.A
Voltage
A.C. CHARACTERISTICS FOR 2112A-2
READ CYCLE
Symbol
TA = O°C to 70°C, Vcc = 5V ±5% unless otherwise specified.
Parameter
Typ.!lJ
Min.
Max.
250
Unit
ns
Test Conditions
tRC
Read Cycle
tA
Access Time
250
ns
tco
Chip Enable To Output Time
180
ns
Timing Reference = 1.5V
tCD
Chip Enable To Output Disable Time
120
ns
Load = 1 TTL Gate
tOH
Previous Read Data Valid After
Change of Address
0
ns
40
t r , tl = 20ns
and CL = 100pF.
READ CYCLE WAVEFORMS
CAPACITANCE
Symbol
[2J
TA = 25°C, f = 1 MHz
Test
Limits (pF)
Typ.[lJ Max.
CIN
I nput Capacitance
(All Input Pins) VIN = OV
4
8
ClIO
I/O Capacitance VI/a = OV
10
15
NOTES:
1. Typical values are for TA = 25° C and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3-50
2112A FAMILY
A.C. CHARACTERISTICS FOR 2112A-2 (Continued)
WRITE CYCLE #1
TA = O°C to 70°C. Vcc = 5V ±5%
Symbol
Typ.[l]
Min.
Parameter
Write Cycle
Max.
Unit
200
ns
Test Conditions
tAWl
Address To Write Setup Time
20
ns
t r • tf = 20ns
Input Levels = 0.8V or 2.0V
tOWl
Write Setup Time
180
ns
Timing Reference = 1.5V
tWPl
Write Pulse Width
180
ns
Load = 1 TTL Gate
tCSl
Chip Enable Setup Time
0
ns
tCHl
Chip Enable Hold Time
0
ns
tWRl
Write Recovery Time
0
ns
tOHl
Data Hold Time
0
ns
tCWl
Chip Enable To Write Setup Time
180
ns
tWCl
WRITE CYCLE #2 TA
Symbol
= O°C to
70°C. Vcc
and CL = 100pF.
= 5V ±5%
Typ.[ll
Min.
Parameter
Max.
Unit
Test Conditions
Write Cycle
320
ns
tAw2
Address To Write Setup Time
ns
tOW2
Write Setup Time
20
180
t r • tf = 20ns
Input Levels = 0.8V or 2.0V
ns
Timing Reference = 1.5V
tW02
Write To Output Disable Time
120
ns
Load = 1 TTL Gate
tCS2
Chip Enable Setup Time
0
ns
tCH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
ns
tOH2
Data Hold Time
0
ns
tWC2
WRITE CYCLE WAVEFORMS
WRITE CYCLE #2
WRITE CYCLE #1
NOTE: 1. Typical values are for TA =
25' C and
nominal supply voltage.
3-51
and CL = 100pF.
2112A FAMILY
A.C. CHARACTERISTICS FOR 2112A
READ CYCLE
Symbol
TA ~ O°C to 70°C, VCC ~ 5V ±5% unless otherwise specified.
Parameter
Min.
tRC
Read Cycle
tA
Access Time
tco
Chip Enable To Output Time
tco
Chip Enable To Output Disable Time
tOH
Previous Read Data Valid After
Change of Address
Symbol
Typ.l11
Max.
350
Parameter
0
Unit
Test Conditions
ns
t r , tf = 20ns
350
240
ns
Input Levels = O.BV or 2.0V
ns
Timing Reference
200
ns
Load = 1 TTL Gate
ns
40
Typ.[l1
Min.
Max.
Unit
and CL
~
~
1.5V
100pF.
Test Conditions
270
ns
t r , tf
20
ns
Input Levels
Write Setup Time
250
ns
Timing Reference = 1.5V
tWP1
Write Pu Ise Width
250
ns
Load
tCS1
Chip Enable Setup Time
0
ns
tCH1
Chip Enable Hold Time
0
ns
tWR1
Write Recovery Time
0
ns
tOH1
Data Hold Time
0
ns
tCW1
Chip Enable to Write Setup Time
250
ns
tWC1
tAW1
Write Cycle
tOW1
Address To Write Setup Time
~
~
20ns
~
O.BV or 2.0V
1 TTL Gate
and CL
~
100pF.
WRITE CYCLE #2 TA = ODC to 70 DC, Vce ~ 5V ±5%
Symbol
NOTE:
Min.
Parameter
tWC2
tAW2
Write Cycle
Typ.[11
Max.
Unit
Test Conditions
470
ns
Address To Write Setup Time
20
ns
Input Levels = O.BV or 2.0V
tOW2
Write Setup Time
250
ns
Timing Reference
tW02
Write To Output Disable Time
200
ns
Load = 1 TTL Gate
tCS2
Chip Enable Setup Time
0
ns
tCH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
ns
tOH2
Data Hold Time
0
ns
1. Typical values are for TA
= 25°C and
nominal supply voltage.
3-52
t r , tf = 20ns
=
1.5V
and CL = 100pF.
2112A FAMILY
A.C. CHARACTERISTICS FOR 2112A-4
READ CYCLE
Symbol
tRe
tA
teo
teo
tOH
TA ~ O°C to 70°C, Vee ~ 5V ±5% unless otherwise specified.
Parameter
Read Cycle
Typ .llJ
Chip Enable To Output Disable Time
Previous Read Data Valid After
Change of Address
Max.
a
Unit
Test Conditions
ns
t r , tf
450
310
ns
Input Levels
ns
Timing Reference
260
ns
ns
Load
450
Access Time
Chip Enable To Output Time
WRITE CYCLE #1
Symbol
Min.
40
~
20ns
~
~
0.8V or 2.0V
~
1.5V
1 TTL Gate
and CL
~
100pF.
TA ~ O°C to 70°C, Vee ~ 5V ±5%
Parameter
tWCl
tAWl
tdWl
Write Cycle
tWPl
Write Pulse Width
tesl
Address To Write Setup Time
Write Setup Time
Min.
Typ.[ll
Max.
320
20
300
Unit
Test Conditions
ns
t r , tf
ns
ns
Input Levels ~ 0.8V or 2.0V
Timing Reference ~ 1.5V
ns
Load
Chip Enable Setup Time
300
a
ns
tCH1
Chip Enable Hold Time
a
ns
tWR1
Write Recovery Time
0
ns
tOH1
Data Hold Time
0
ns
tewl
Chip Enable to Write Setup Time
300
ns
~
~
20n5
1 TTL Gate
~
and CL
10apF.
WRITE CYCLE #2 TA ~ aOc to 7aoc, Vee ~ 5V ±5%
Symbol
twe2
tAW2
tow2
Address To Write Setup Time
Write Setup Time
Min.
Typ.!lJ
Max.
Unit
ns
t r , tf
ns
Input Levels
ns
Timing Reference
ns
Load
ns
tes2
Chip Enable Setup Time
teH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
tOH2
Data Hold Time
0
ns
ns
Write To Output Disable Time
1. Typical values are for TA ~
Test Conditions
580
20
300
260
a
tW02
NOTE:
Parameter
Write Cycle
25°C and nominal supply voltage.
3-53
~
~
20ns
~
0.8V or 2.0V
~
1.5V
1 TTL Gate
and CL
~
100pF.
inter
2114
1024 X 4 BIT STATIC RAM
I
I
2114-2
200
525
Max. Access Time (ns)
Max. Power Dissipation (mw)
2114-3
300
525
2114
450
525
2114L2
200
370
2114L3
300
370
2114L
450
370
Directly TTL Compatible: All Inputs
• and
Outputs
Common
Input and Output Using
• Three-StateDataOutputs
Compatible with 3605 and 3625
• Pin-Out
Bipolar PROMs
• High Density 18 Pin Package
• Identical Cycle and Access Times
• Single +5V Supply
• No Clock or Timing Strobe Required
• Completely Static Memory
The Intel® 2114 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel Silicon-Gate
MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and therefore
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2114 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing are
important design objectives. The 2114 is placed in an is-pin package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an individual package when outputs are or-tied.
The 2114 is fabricated with Intel's N-channel Silicon-Gate technology - a technology providing excellent protection against
contamination permitting the use of low cost plastic packaging.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
A, 0
""
As
A.
Vee
A,
A.
A,
liD,
A,
A,
""
A.
I/0,
A,
1/0,
A,
1/0,
A,
1/°4
As
WE
A.
Ag
A
4
A,
110,
A4
As
As
CS
GND
®
CD
A.
As
A,
@)
..-..=-Vcc
®
~GND
ROW
SELECT
MEMORY ARRAY
64 ROWS
64 COLUMNS
@
@
liD,
A.
I/O,@
1/°4
I/O,@
1/0,@
WE
CS
PIN NAMES
AO-Ag
WE
ADDRESS INPUTS
Vee POWER (+5V)
WRITE ENABLE
GND GROUND
CS
CHIP SELECT
o:
1/0,-1/°4 DATA INPUT/OUTPUT
3·54
PIN NUMBERS
2114 FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias . . . . . . . . . . . . -10°Cto 80°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1.0W
D.C. Output Current
. . . . . . . . . . . . . . . . . . . . . 5mA
D.C. AND OPERATING CHARACTERISTICS
TA = o°c to 70 o e, Vcc = 5V ± 5%, unless otherwise noted.
SYMBOL
PARAMETER
2114-2,2114·3,2114
Min. Typ.(1) Max.
2114L2, 2114L3, 2114L
Min. Typ.(1) Max. UNIT
CONDITIONS
III
I nput Load Current
(All Input Pins)
10
10
JlA
VIN = 0 to 5.25V
IILOI
I/O Leakage Current
10
10
JlA
CS = 2.4V,
Vila = O.4V to Vcc
ICCl
Power Supply Current
95
65
mA
VIN = 5.25V, lifO = 0 mA,
TA=25°C
ICC2
Power Supply Current
100
70
mA
VIN = 5.25V, lifO = 0 mA,
TA = O°C
80
VIL
Input Low Voltage
-0.5
0.8
-0.5
0.8
V
VIH
Input High Voltage
.2.0
6.0
2.0
6.0
V
10L
Output Low Current
2.1
6.0
10H
Output High Current
-1.0
-1.4
105!2)
Output Short Circu it
Current
NOTE: 1. Typical values are for T A = 25" C and Vee
2. Duration not to exceed 30 seconds.
2.1
6.0
-1.0
-1.4
40
40
mA
VOL = O.4V
mA
VOH = 2.4V
mA
= 5.0V.
CAPACITANCE
TA = 25°C, f = 1.0 MHz
SYMBOL
TEST
MAX
UNIT
CONDITIONS
CliO
Input/Output Capacitance
5
pF
VI/a = OV
CIN
Input Capacitance
5
pF
VIN = OV
NOTE: This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.8 Volt to 2.4 Volt
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 nsec
Input and Output Timing Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Volts
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL
3·55
= 100 pF
TEST NOTE: This circuit
employs a self starting
oscillator and a charge
pump which require a
certain amount of time
after POWER ON to start
functioning properly. This
2314 circuit is conservatively specified as requiring 500 flsec after Vcc
reaches its specified
limits (4.75V).
2114 FAMILY
A.C. CHARACTERISTICS
TA
= o°c to 70°C, Vee = 5V ± 5%, unless otherwise noted.
READ CYCLE [1]
SYMBOL
2114-2,2114L2 2114-3, 2114L3
Max.
Min.
Max.
Min.
PARAMETER
tRe
Read Cycle Time
tA
Access Time
teo
Chip Selection to Output Valid
200
tex
Chip Selection to Output Active
tOTO
Output 3-state from Deselection
tOHA
Output Hold from Address Change
2;14,2114L
Min.
Max.
450
300
UNIT
ns
200
300
450
ns
70
100
120
ns
20
20
20
60
ns
80
50
100
ns
50
50
ns
WRITE CYCLE [2]
SYMBOL
2114-2,2114L2 2114-3,2114L3
Max.
Max.
Min.
Min.
PARAMETER
2114,2114L
Max.
Min.
UNIT
twe
Write Cycle Time
200
300
450
ns
tw
Write Time
120
150
200
ns
tWR
Write Release Time
tOTW
Output 3-state from Write
tow
Data to Write Time Overlap
120
150
200
ns
tOH
Data Hold From Write Time
0
0
0
ns
0
0
0
60
os
100
80
ns
NOTES:
1. A Read Docur. during the overlap of a low
CS and a high WE.
2. A Write occurs during the overlap of a low CS and a low WE.
WAVEFORMS
READ CYCLE@
WRITE CYCLE
-------'RC--------I
I~'-----'A---
ADDAE~ --~----------------------r_~~-----
\\\\\\\\\\t
os \\\\\\\\\
'-twR
,\\' .\\'\
'// '/ / / / / /
_tCQ _ _
-------torD _~I
-tex
tOHA~
/ / / / / / / / / / /,
'w
.1
®
~\\\k
-tOT=!
DOUT
NOTES:
@ WE is high for a Read Cycle.
@)
~/ /
DOUT
t'DW
If the CS low transition occurs simultaneously with the WE low
transition, the output buffers remain in a high impedance state.
D'N
® WE must be high during all address transitions.
3-56
!
tDH
2114 FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
1.2
1.2
1. 1
1. 1
-
...............
1.0
;!-
S
N
..
::;
iii
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
O.g
-
r--
1.0
;!-
S
N
..
::;
~
o
z
0.8
~
0.7
0.7
0.6
0.5
4.50
0.5
4.75
5.00
5.25
1. 2
i,..--
,,-
V
1. 1
1.0
II
0.9
~
0.8
::;
~
a:
0.8
z
0.7
0.9
~
N
~ r-
o
0.7
0.6
-
0.6
0.5
100
200
300
400
500
20
600
40
60
CL (pF)
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
40
40
30
30
20
80
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
N
~
60
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
;!-
a:
40
TA reI
1.1
~
20
0
5.50
Vee (V)
1.2
::;
~
-------
0.8
0.6
1.0
f.---
O.9
~
10
o
o
V-
./
20
"~
10
"~
/
/'
V
o
o
VOL (VI
VOH (V)
3-57
80
inter
2115A, 2125A FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
2115AL
2125AL
I Max. TAA(ns)
I Max. 'cc(mA)
2115A
2125A
2115AL-2
2125AL-2
45
45
70
70
75
125
75
125
2115A-2
2125A-2
• HMOS Technology
• Pin Compatible To 93415A
(2115A) And 93425A (2125A)
• TTL Inputs And Outputs
• Fan-Out Of 10 TTL (2115A Family)
-- 16mA Output Sink Current
• Uncommitted Collector (2115A)
And Three-State (2125A) Output
• Single +5V Supply
• Standard 16-Pin Dual In-Line
• Low Operating Power Dissipation
--Max. 0.39mW/Bit (2115AL, 2125AL) Package
The Intel® 2115A and 2125A families are high·speed, 1024 words by 1 bit random access memories. Both open collector
(2115A) and three-state output (2125A} are available. The 2115A and 2125A use fully DC stable (static) circuitry throughout - in both the array and the decoding and, therefore, require no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data.
The 2115AL!2125AL at 45 ns maximum access time and the 2115AL-2/2125AL-2 at 70 ns maximum access time are fully
compatible with the industry-produced 1 K bipolar RAMs, yet offer a 50% reduction in power of their bipolar equivalents.
The power dissipation of the 2115AL/2125AL and 2115AL-2/2125AL-2 is 394 mW maximum as compared to 814 mW
maximum of their bipolar equivalents. For systems already designed for 1 K bipolar RAMs, the 2115A/2125A and the
2115A-2/2125A-2 at 45 ns and 70 ns maximum access times, respectively, offer complete compatibility with a 20% reduction
in maximum power dissipation.
The devices are directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate select (CS) lead
allows easy selection of an individual package when outputs are OR-tied.
The 2115A and 2125A families are fabricated with HMOS, Intel's High Speed N-channel MOS Silicon Gate Technology.
PIN CONFIGURATION
LOGIC SYMBOL
CS
cs
Vee
'0
D'N
'."
"
"
"
"
"
As
'.
"
"
GND
As
15
,.
BLOCK DIAGRAM
WORD
DRIVER
Vee
.
PlN 16
GND
=
PIN 8
1 I
SENSE AMPS
AND
WRITE
DRIVERS
10
13
I~
I----
ADDRESS
DECODER
!l.DDRESS
DECODER
DOUT
00000
PIN NAMES
111 JJ
~
6
7
8
's
9
®@@@@
WE
DIN
CD @ @
TRUTH TABLE
CHiPSELE~
ADDRESS INPUTS
WRITE ENABLE
DoUT
CONTROL
LOGIC
ISEE TRUTH
TABLE)
1
12
I II t I
_DATA
r------
11
Ao A, Az A7 A~
DiN
32 X 32
ARRAY
~
"
"
"
°OUT
WE
Ao
WE
"
"
"
DIN
OUTPUT
OUTPUT
2115A FAMILY 2125A FAMILY
INPUTS
INP~~
DATAOUT~
3-58
CS WE o.N
H
X
X
OoU7
L
L
L
HIGH Z
HIGH Z
HIGH Z
L
L
H
HIGH Z
HIGH Z
L
H
X
OoU7
OoU7
HIGH Z
MODE
OoU7
NOT SELECTED
WRITE "0"
WRITE "1"
REAO
2115A, 2125A FAMILY
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . . . _1O°C to +85°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
All Output or Supply Voltages . . . . . . . . . . -0.5V to + 7V
All Input Voltages . . . . . . . . . . . . . . . . . -0.5V to +5.5V
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . 20 mA
'COMMENT: Stresses above those listed under "Absolute Maxi·
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
at any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTICS[1,21
VCC = 5V ±5%, TA = o°c to 75°C
Symbol
Test
Min.
Typ.
Max.
Unit
VOL1
2115A Family Output Low Voltage
0.45
V
10L= 16mA
VOL2
2125A Family Output Low Voltage
0.45
V
10L = 7 mA
VIH
Input High Voltage
VIL
Input Low Voltage
IlL
Input Low Current
2.1
Conditions
V
-0.1
0.8
V
-40
j.lA
Vcc = Max., VIN = O.4V
IIH
Input High Current
0.1
40
j.lA
VCC = Max., VIN = 4.5V
ICEX
2115A Family Output Leakage Current
0.1
100
j.lA
VCC = Max., VOUT = 4.5V
IIOFFI
2125A Family Output Current (High Z)
0.1
50
j.lA
Vcc = Max., VOUT = 0.5V/2.4V
los[3]
2125A Family Current Short Circuit
to Ground
-100
mA
VCC= Max.
VOH
Family Output High Voltage
Icc
Power Supply Current:
ICC1: 2115AL, 2115AL·2, 2125AL,
2125AL-2
2.4
ICC2: 2115A, 2115A-2, 2125A, 2125A-2
V
60
75
mA
100
125
mA
10H = -3.2 mA
All Inputs Grounded, Output
Open
NOTES:
1. The operating ambient temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute. Typical thermal
resistance values of the package at maximum temperature are:
400 fpM air flow) = 45° C/W
BJA (still air) = 60°C/W
BJC = 25°C/W
2. Typical limits are at VCC = 5V. TA = +25°C, and maximum loading.
3. Duration of short circuit current should not exceed 1 second.
B JA (@
3-59
2115A, 2125A FAMILY
2115A FAMILY A.C. CHARACTERISTlCS[1,21 Vee = 5V ±5%, T A = o°c to 75°C
READ CYCLE
Symbol
2115AL Limits
2115A Limits 2115AL-2 Limits 2115A-2 Limits
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
15
30
15
30
15
30
15
40
ns
Chip Select Recovery Time
10
30
10
30
10
30
10
40
ns
tAA
Address Access Time
30
45
30
45
40
70
40
70
ns
tOH
Previous Read Data Valid After
Change of Address
tAcs
t RCS
Chip Select Time
5
5
10
5
10
5
10
10
ns
WRITE CYCLE
Symbol
Test
tws
Write Enable Time
tWR
Write Recovery Time
tw
Write Pulse Width
tWSD
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
10
25
10
25
0
10
30
30
0
25
10
25
0
40
45
0
ns
30
20
30
10
30
15
50
15
ns
Data Set-Up Time Prior to Write
0
-5
5
-5
0
-5
5
-5
ns
tWHD
Data Hold Time After Write
5
5
15
tWHA
Address Hold Time
5
5
twses
Chip Select Set-Up Time
5
5
0
5
tWHes
Chip Select Hold Time
5
5
0
5
0
0
0
0
0
ns
5
0
0
0
5
Address Set-Up Time
0
0
0
0
0
5
tWSA
0
0
0
0
0
5
5
5
5
A.C. TEST CONDITIONS
5
5
ns
ns
ns
ns
All INPUT PULSES
90%
Vee
\
,--_';.;;.0,";;..,_ __
30Dn
GNO --::-
2115A
....
10n5
..
10n5
"oUT-.....- - -4
600Il
JOpF
(INCLUDING
SCOPE AND
JIG)
-==-\.'---------'.I
--r
GND
READ CYCLE
-=-
-I
,"
'Om
10m
WRITE CYCLE
.J)K. . ______________
l<-
AO A9 _ _ _
Ao Ag
l - tAA
f-
~
-If-
---
",?
-J(-
Dour
10%
90%
__ tw-----..
DATA VALID
-f\
I twso_
7 '-
!
PROPAGATION DELAY FROM CHIP SELECT
I-t:j
----- twscs
Dour
DATA
UNDEFINED
{All ABOVE MEASUREMENTS REFERENCED TO 1.5V)
3-60
-rJ
I--lt
_twHA_1,
WHO
'ws
~t,tWHCS
'wR
~
-----.
2115A, 2125A FAMILY
2125A FAMILY A.C. CHARACTERISTICS[1.2J
vee; 5V ±5%, T A ; O°c to 75°C
READ CYCLE
2125AL Limits
2125A Limits 2125AL-2 Limits 2125A-2 Limits
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
Symbol
tACS
Chip Select Time
15
30
15
30
15
30
15
40
ns
tZRCS
Chip Select to HIGH Z
10
30
10
30
10
30
10
40
ns
tAA
Address Access Time
30
45
30
45
40
70
40
70
ns
tOH
Previous Read Data Val id After
Change of Address
5
5
5
10
10
5
10
10
ns
WRITE CYCLE
Symbol
Min. Typ. Max. Min. Typ_ Max. Min. Typ. Max_ Min. Typ. Max. Units
Test
tzws
Write Enable to HIGH Z
tWR
Write Recovery Time
tw
Write Pulse Width
tWSD
10
0
25
30
10
25
10
30
0
25
10
25
0
0
40
ns
45
ns
30
20
30
10
30
10
50
15
ns
Data Set-Up Time Prior to Write
0
-5
5
-5
0
-5
5
-5
ns
tWHD
Data Hold Time After Write
5
0
5
0
5
0
5
0
ns
tWSA
Address Set-Up Time
5
0
5
0
5
0
15
0
ns
tWHA
Address Hold Time
5
0
5
0
5
0
5
0
ns
twses
Chip Select Set-Up Time
5
0
5
0
5
0
5
0
ns
tWHes
Chip Select Hold Time
5
0
5
0
5
0
5
0
ns
A.C. TEST CONDITIONS
All INPUT PULSES
'1--1
51 on
GNO
300n
"1---------\ -
3-r"- - :-- "
-- "-
-= ___ :_ --lOns
-"'*1
90%
1,;_;.;"_';.;;,0%;;...._ _
:_10n5
JOpF
(INCLUDING
SCOPE AND
JIG)
READ CYCLE
WRITE CYCLE
~\,,_ _ _ _ _ _ _ _ _ _ __
r-
.--
Ao-Ag _ _ _
---If--
---If--
DouT
-'~
D,N
-f
_IW----.
~
WE
PROPAGATION DELAY FROM CHIP SELECT
tWSD
t~::=-I
I-
f+--o-
DoUT"~~===
(All ABOVE MEASUREMENTS REFERENCED TO 1.5V)
3-61
tWHO
_tWHA_
_tWSA_
~twscs_
F--
~~fc!.(f/;,
'wR-
twHCS______..
2115A, 2125A FAMILY
2125A FAMILY WRITE ENABLE TO HIGH Z DELAY
5V
WE
WRITE ENABLE
750U
2125A
DOUT
"0" LEVel
DATA OUTPUT _ _
t=
tzws
r---;';;H-;"
..::..;;.:;.:=__~=} a.5V
5 of
DOUT _ _..;"'..;".;;l';.:V.;;'l=-_ _~--}
a.sv
, - _ _ ~I~':'
DATA OUTPUT
LOAD 1
2125A FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z
cs
CHIP SELECT
_ _ _.1'1
DOUT
r--~I~;
tZRCS
DATA OUTPUT _ _..;"O:,.."..;,l':,;V..;,';;,.L_ _~_ } a.sv
"1" lEVEL
DOUT
-------""'\I--}
DATA OUTPUT
0.5V
\-. _ _
!!'!!! ~
(ALL tzxxx PARAMETERS ARE MEASURED AT A DELTA
OF a.sv FROM THE LOGIC LEVEL AND USING LOAD 1.)
2115A/2125A FAMILY CAPACITANCE* vee; SV, f; 1 MHz, T A
TEST
SYMBOL
Input Capacitance
CI
Output Capacitance
Co
2115A Family
LIMITS
;
2SoC
2125A Family
LIMITS
TEST CONDITIONS
UNITS
MAX.
TYP.
TYP.
MAX.
3
S
3
S
pF
All Inputs;
8
S
8
pF
CS; SV, All Other Inputs;
Output Open
S
av, Output Open
av,
"This parameter is periodically sampled and is not 100% tested.
TYPICAL CHARACTERISTICS
ICC VS. TEMPERATURE
110
100
J'15A-~
211'5A.
t--!125A, 2125A·2 -
t-- t--
ACCESS TIME VS. TEMPERATURE
ICC VS. VCC
110
~
100
r-r-r-
70
60
V2115A,2115A.2
2125A,2125A·2
90
90
80
:<
80
!
"
70
:-
E
9
70
60
50
r--r-.
r--
"
2115AL,2115AL·2
~
60
50
o
TEMPERATURE (OC)
V
/'"
I
I
I
50
f-- ~ ~g;:t:~: ~g~::~
40
I--- f0o-
./'
L--I.-'"
30
20
roo
i.-- l-
j....- L--~
2115AL, 21 lSA
21rAl'r25AI
2115AL, 2115AL-2
2125AL,2125AL-2
J....-
V
~
10
TA",125oe
o
Vee = 5V
o
OW.
Vee (V)
3·62
E
~
60
TEMPERATURE (DC)
60
ro
00
inter
,\,
2115H, 2125H FAMILY
HIGH SPEED 1K x 1 BIT STATIC RAM
• HMOS n Technology
• 25-35ns Maximum Access Time
• TTL Inputs and Outputs
• Single +5V Supply
• Uncommitted Collector (2115H) and
Three-State (2125H) Output
• 125mA Maximum Icc
• Pin Compatible to 93415A (2115H) and
93425A (2125H)
• Standard 16-Pin Dual In-Line Package
The Intel@ 2115H and 2125H families are high-speed, 1024 words by 1 bit random access memories. Both open collector
(2115H), and three-state output (2125H) are available. The 2115H and 2125H use fully DC stable (static) circuitry
throughout - in both the array and thedecoding and, therefore, require no clocks or refreshing to operate. The data is read
out non-destructively and has the same polarity as the input data.
The 2115H and 2125H families are fully compatible with 1 K Bipolar Static RAMs yet offer significant reductions in power
The devices are directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate select (CS)
lead allows easy selection of an individual package when outputs are OR-tied.
The 2115H and 2125H families are fabricated with Intel's N-channel HMOS n Silicon Gate Technology.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
cs
-
WORD
os
vee
Au
0,.
DRIVER
Au
A,
....
..
A,
A,
A,
...
WE
A,
A,
...
... ,
A,
A,
A,
DOUT
OND
32 X32
ARRAY
Vee =
GND =
.
A,
11
As
12
A.
13
PIN 16
PIN8
1 )
t-------
SENSE AMPS
CONTROL
lOGIC
AND
WRITE
DRIVERS
1-
(SEE TRUTH
TABLE)
I-
1
ADDRESS
DECODER
ADDRESS
DECODER
"oUT
III! 1
t t tIt
AS A6 A7 AS A9
CS
WE
o,N
®00®®
®@@@@
CD
@
@
Ao
A, A2 A] A4
TRUTH TABLE
PIN NAMES
Ao TOAo
WE
CHIP SELECT
ADDRESS INPUTS
WRITE ENABLE
DATA INPUT
OnUT
DATA OUTPUT
"'.
INPUTS
CS WE
H
X
L
L
L
L
L
H
3-63
o.t.
OUTPUT
2115H FAMilY 2125H FAMILY
OUTPUT
MODE
DoUT
DoUT
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
NOT SELECTED
L
H
X
DoUT
DoUT
READ
X
WRITE "0"
WRITE'T'
o
inter
2117 FAMILY
16,384 x 1 BIT DYNAMIC RAM
2117-2
150
320
330
Maximum Access Time (ns)
Read, Write Cycle (ns)
Read-Modify-Write Cycle (ns)
• Industry Standard 16-Pin Configuration
• ±10% Tolerance on All Power Supplies:
+12V, +5V, -5V
• Low Power: 462mW Max. Operating,
20mW Max. Standby
• Low 100 Current Transients
• All Inputs, Including Clocks,
TTL Compatible
2117-3
200
375
375
2117-4
250
410
475
• Non-Latched Output is Three-State,
TTL Compatible
• RAS Only Refresh
• 128 Refresh Cycles
Required Every 2ms
• Page Mode Capability
• CAS Controlled Output
Allows Hidden Refresh
The Intel@ 2117 is a 16,384 word by 1-bit DynamiC MOS RAM fabricated with Intel's standard two layer polysilicon NMOS
technology - a production proven process for high performance, high reliability, and high storage density.
The 2117 uses a single transistor dynamiC storage cell and advanced dynamic circuitry to achieve high speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients and ±10% tolerance on all power supplies contribute to the high noise immunity of the 2117 in a system
environment.
Multiplexing the 14 address bits into the 7 address input pins allows the 2117 to be packaged in the industry standard 16-pin
DIP. The two 7-bit address words are latched into the 2117 by the two TTL clocks, Row Address Strobe (RAS) and Column
Address Strobe (CAS). Non-critical timing requirements for RAS and CAS allow use of the address multiplexing technique
while maintaining high performance.
The 2117 three-state output is controlled by CAS, independent of RAS. After a valid read or read-modify-write cycle, data is
latched on the output by holding CAS low. The data out pin is returned to the high impedance state by returning CAS to
a high state. The 2117 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to
execute RAS-only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RASonly refresh cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of Ao through A6
during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is addressed.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
64 x 128 CELL
MEMORY ARRAY
AO
A,
A,
D'N
A3
A,
A5
As
DOUT
DOUT
RAS
CAS
WE
PIN NAMES
-Ao-A6
ADDRESS INPUTS
WE
WRITE ENABLE
CAS
COLUMN ADDRESS STROBE
VBB
POWER (-5Vl
D'N
DATA IN
Vee
POWER {+5V}
DOUT
DATA OUT
VDO
POWER (+12V)
RAS
ROW ADDRESS STROBE
Vss
GROUND
.-~
CAS-====..1
~===============~----~
D'N
3·64
2117 FAMILY
ABSOLUTE MAXIMUM RATINGS*
'COMMENT:
AmbientTemperatureUnderBias ... -10°Cto+80°C
Storage Temperature ............. -65°Cto+150°C
Voltage on Any Pin Relative to Vss
(Vss-Vss~4V)
..................... -0.3Vto+20V
Data Out Current ............................ 50mA
Power Dissipation .... . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1,2]
TA
= ooe
Symbol
to
7ooe,
VDD
= 12V ±10%,
Vee
Parameter
Ilul
Input Load Current (any input)
IILOI
Output Leakage Current for
High Impedance State
1001
Voo Supply Current, Standby
ISS1
Vss Supply Current, Standby
ICC1
Vcc Supply Current, Output
Deselected
1002
Voo Supply Current, Operating
ISS2
Vss Supply Current, Operating,
RAS-Only Refresh, Page Mode
1003
Voo Supply Current, RAS-Only
Refresh
= 5V ±10%,
Vss
= -5V ±10%,
Vss
= OV,
unless otherwise noted.
Limits
Min. Typ,l31 Max. Unit Test Conditions
0.1
10
J1.A VIN=VSS to 7.0V, Vss=-5.0V
10
Chip Deselected: CAS at VIH,
J1.A VOUT = 0 to 5.5V
1.5
mA CAS and RAS at VIH
1.0
50
J1.A
0.1
10
J1.A CAS at VIH
35
mA 2117-2, tRC
35
mA 2117-3, tRC
33
mA 2117-4, tRC
0.1
150
300
J1.A TA
mA 2117-2, tRC
27
mA 2117-3, tRC
26
mA 2117-4, tRC
Voo Supply Current, Standby,
Output Enabled
VIL
Input Low Voltage (all inputs)
-1.0
0.8
VIH
Input High Voltage (all inputs)
2.4
6.0
V
VOL
Output Low Voltage
0.4
V
10L
VOH
Output High Voltage
V
10H
1.5
2.4
3
4
5
= 375ns, tRAS = 150ns
= 375ns, tRAS = 200ns
= 410ns, tRAS = 250ns
4,6
= 375ns, tRAS = 150ns
= 375ns, tRAS = 200ns
= 410ns, tRAS = 250ns
4,6
4
4
= O°C
27
1005
Notes
4
4
mA CAS at VIL, RAS at VIH
V
= 4.2mA
= -5mA
4
4
NOTES:
1. All voltages referenced to Vss.
2. No power supply sequencing is required. However. Voo, Vce and Vss should never be more negative than -0.3V with respect to Vee as
required by the absolute maximum ratings.
3. Typical values are for 1A = 25° e and nominal supply voltages.
4. See the Typical Characteristics Section for values of this parameter under alternate conditions.
5. Icc is dependent on output loading when the device output is selected. Vee is connected to the output buffer only. Vee may be reduced
to Vss without affecting refresh operation or maintenance of internal device data.
6. For the 2117-2 at tRe = 320ns, tRAS = 150ns, 1002 max. is 45mA and 1003 max. is 31mA.
3-65
2117 FAMILY
TYPICAL SUPPLY CURRENT WAVEFORMS
LONG ~m
IIJIS/OO
RASONLY REFRESH
PI I I I I
J I 1 I I I 1 I t I J I 'I I I
125
lima
100
100
(mAl
75
1\
50
,\
~\
J \~~
25
75
1\
25
(rnA)
1
J~
I\..
.
50
IBB
J
A
~
\...
A
0
~1
- 25
AA
'II
"V
\I,
- 50
·V
1
A
...,l
.&
/'
(
...,
,,
A
n
"
-75
125
100
IsS
(rnA)
25
o
moo
1\
75
50
j
III
J\
II
I-- II ~
V
o
TIME(ns)
100
TIME(ns)
Typical power supply current waveforms vs. time are
shown for the RAS/CAS timings of Read/Write, Read/
Write (Long RAS/CAS), and RAS-only refresh cycles. 100
and Iss current transients at the RAS and CAS edges
require adequate decoupling of these supplies. Decoupling recommendations are provided in the Applications
section.
...
\I
jV
I
L-200
Vl\
300
= 25°C,
Symbol
VDD
= 12V±100f0, Vcc = 5V±100f0,
VBB
500
The effects of cycle time, Voo supply voltage and ambient
temperature on the 100 current are shown in graphs
included in the Typical Characteristics Section. Each
family of curves for 1001, 1002, and 1003 is related by a
common point at Voo = 12.0V and TA =25°C fortwogiven
tRAS pulse widths. The typical 100 current for a given
condition of cycle time, Voo and TA can be determined by
combining the effects of the appropriate family of curves.
CAPACITANCE [1J
TA
400
TlME(ns)
= -5V±100f0,
Parameter
Vss
= OV,
unless otherwise specified.
Typ.
Max.
Unit
C(1
Address, Data In
3
5
pF
CI2
RAS Capacitance, WE Capacitance
4
7
pF
CI3
CAS Capacitance
6
10
pF
Co
Data Output Capacitance
4
7
pF
NOTES:
1. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation:
C = It-t with t-V equal to 3 volts and power supplies at nominal levels.
t-V
3·66
2117 FAMILY
A.C. CHARACTERISTICS[1,2,3]
TA = O°C to 70°C, VOO = 12V ±10%, Vee = 5V ±10%, Vee = -5V ±10%, Vss = OV, unless otherwise noted.
R£AJa, WRITE, JltEAD-MODIFY-WJltITE AND REFRESH CYCLES
2117-2
Symbol
Parameter
Min.
Access Time From RAS
tCAC
Access Time From CAS
tREF
Time Between Refresh
tRP
tRAH
100
CAS Precharge Timelnon-pagecycles) 25
CAS to RAS Precharge Time
-20
RAS to CAS Delay Time
20
100
RAS Hold Time
CAS Hold Time
150
Row Address Set-Up Time
0
Row Address Hold Time
20
tASC
Column Address Set-Up Time
tCAH
Column Address Hold Time
tAR
Column Address Hold Time, to RAS
IT
Transition Time (Rise and Fal/)
tOFF
Output Buffer Turn Off Delay
tRCO
tRSH
tCSH
tASR
2117-3
Min.
RAS Precharge Time
50
Mu.
2117-4
Min.
200
135
2
150
100
2
tRAC
tCPN
tCRP
Max.
120
25
-20
25
135
200
0
25
65
150
25
-20
35
165
250
0
35
-10
-10
-10
45
95
3
0
55
120
3
0
75
160
3
0
50
50
50
60
Max.
Unit
Notes
250
165
2
ns
4,5
4,5,6
ns
ms
ns
ns
ns
85
ns
7
ns
ns
ns
ns
ns
ns
ns
50
70
ns
8
ns
READ AND REFRESH CYCLES
tRC
Random Read Cycle Time
tRAs
RAS Pulse Width
tCAS
CAS Pulse Width
tRCS
Read Command Set-Up Time
tRCH
Read Command Hold Time
320
150
100
0
0
10000
10000
375
200
135
0
0
10000
10000
410
250
165
0
0
ns
10000
10000
ns
ns
ns
ns
WRITE CYCLE
320
150
100
tRC
Random Write Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
twcs
-20
45
Write Command Hold Time
Write Command Hold Time, to RAS 95
Write Command Pulse Width
45
Write Command to RAS lead Time
60
Write Command to CAS lead Time
60
Data-In Set-Up Time
0
45
Data-In Hold Time
Data-In Hold Time, to RAS
95
tWCH
twCR
twp
tRWL
tCWL
tos
tOH
tOHR
10000
10000
Write Command Set-Up Time
375
200
135
10000
10000
-20
55
120
55
80
80
0
55
120
410
250
165
ns
10000
10000
ns
ns
ns
-20
75
160
75
100
100
0
75
160
9
ns
ns
ns
ns
ns
ns
ns
ns
READ-MODIFY-WRITE CYCLE
tRWC
Read-Modify-Write Cycle Time
tRRW
RMW Cycle RAS Pulse Width
tCRW
RMW Cycle CAS Pulse Width
tRwo
RAS to
tcwo
CAS to WE Delay
WE Delay
330
185
135
120
70
10000
10000
Notes: See following page for A.C. Characteristics Notes.
3-67
375
245
180
160
95
10000
10000
475
305
230
200
125
ns
10000
10000
ns
ns
ns
9
ns
9
2117 FAMILY
WAVEFORMS
tRC
READCY CLE
~tRd
tRAS
CD
®tCRP -1
/I
l®
V,H
0J
i-+---
ROW
V"
1\\\\0
~
-
!---tCAH~
tASC
K)
ADDRESS
teAs
tAR
r--tRAH~
~
ADDRESSES
tRSH
tRCO
/I
tASR
~tcPN~1
tCSH
~
X
COLUMN
ADDRESS
_I ......
~tRCH0
tRCS
~
teAC
.
\
---_________>o_
tRAC
0
~tOFF---
VOH
HIGH
r-VA-L-,-D-----""\I
VOL--------~IM~P~E~D~A~NC~E~---------------------~~4~~I_D_AT_A_D_UT_ _ _ _ _1
®
~1·r-----------------tRC ------------------~
WRITE CYCLE
1-.r-----------~tRAs--------------~ l~tRP~
0~~®~________________~~
1'--
___®:8~tC=R~P_--1~'~~r-::::::::::::t~R~C~D;;;:;:~~~rt-cs-H~=======-tR-S-H===========~t--~~ l~teP~
~:_---JJ
01\\ \~I--®--~teAs---f--.Hfi-:-------"i:
---------+tAR--+t-------~
tASR-j-
-+-tRAH--l
~H-------~~~(G)~l~~-R-O-W-~l(~~)~r-~-CO-L-U-M-N~r------~K~~--------t--~------------f2\
ADDRESSES
ADDRESS
ADDRESS
~L-------~~~~~-----~~~~~_4-----~r_----------~~---------_+--~------------------~---~--+-~-tRWL--------'------'
1~---r---+-r------~L::::=:~~:::::::::::1
" I-- twcs - -
V,H
WE
0'
v"
-------- t WCH twp
''1
________________...
\
~---~~----~CR--~-------~
t--®t DS -
V,H
D'N
......--.-t oH
@-
) 0o
VIL
K
~-----------tDHR------------·
DOUT
NOTES:
VOH
VOL
1,2.
3,4.
5.
6.
7.
8.
HIGH
IMPEDANCE
V 1H MIN AND V 1l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DoUT ·
tOFF IS MEASURED TO lOUT";; IILO I·
tos AND tOH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
tRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCUR.§.£.!RST.
tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (I.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
A.C. CHARACTERISTICS NOTES (From Previous Page)
1. All voltages referenced to Vss.
2. Eight cycles are required after power-up or prolonged periods
(greater than 2ms) of RAS inactivity before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
3. A.C. Characteristics assume tT = 5ns.
4. Assume that tRCD ,; tRCD (max.), If tRCD is greater than tRCD
(max,) then tRAC will increase by the amount that tRcD exceeds
tRCD (max,).
5. Load = 2 TTL loads and 100pF.
6. Assumes tRCD ~ tRCD (max,).
7. tRCD (max,) is specified as a reference point only; if tRcD is less
than tRCD (max,) access time is tRAC, iftRCD is greater than tRCD
(max,) access time is tRCD + tCAC.
8. tT is measured between V,H (min.1 and V,L (max,).
9. twcs, tCWD and tRWD are specified as reference points only. If
twcs ~ twcs (min,) the cycle is an early write cycle and the data
out pin will remain high impedance throughout the entire
cycle. IftcWD ~tcwD (min,) and tRWD~tRWD (min,), the cycle is
a read-modify-write cycle and the data out will contain the data
read from the selected address. If neither of the above
conditions is satisfied, the condition of the data out is
indeterminate.
3-68
2117 FAMILY
WAVEFORMS
READ-MODI FY-WRITE CYCLE
tRWC
r------- ,,,----1
tRRW~--
(i)
0
tCRP
IT
0
I
-j
---~---'c
'~
itRAH
(i) t\\\\ 0
---------;--:--tAR
tASR
ADDRESSES
~::
r------
){ CD
'c'"---'-RS;·~= _~= I---
~tACD
tA~r
AD~~~SS
0
1<
--
.. - - - - - - - I.-
-teAH
tRWO
0(i)/
tcwo---_I f--twp--I
}
V
0'''-1
U '0"0
){CD
~'c"------i
,
t RWl - -
- - - tCWl - - -
)c! ;:g~~~sNs
tRcsi--
HIGH
'--tCPN-------1
DATA IN
VALID
0
K
0 1
""
IMPEDANCE
(4)
VALID
DATA OUT
-
tOFf
0
RAS-ONL Y REFRESH CYCLE
If.·-------------'"c---------------~
1-------------tRAS----------~
v,"
CAS
v"
ADDRESSES
v,"
V"
DOUT VOH __________________________________~H~IG~H~-----------------------------------VOL
IMPEDANCE
HIDDEN REFRESH CYCLE
_
V 1H
CAS
ADDRESSES
v,"
V"
V,"
DO"' :::_____-
t
20
::l
10
30
~
..
t
::l
iil
.9
20
I
N
...
>
.t
11
0
.9
400
600
800
tRe -CYCLE TIME (n5)
O.S
::l
I
Q
12
13
10
1000
o
10
'---
-
0.6
20
14
5.5
6.0
-40
rso
60
TA - AMBIENT TEMPERATURE rC)
GRAPH 9
TYPICAL OPERATING CURRENT
1002 VS. AMBIENT TEMPERATURE
50'---'---r---~--'
TA "26l C
VOO=12.0V
vaa ;;; -5.0V
40~----+-----~-----+----~
.......-d
tRAS" 200ns
375n
30r---r---t--~'~RA~S~"~200~n.~
tRe '" 376ns
•
20r---r---t---+--~
~"50On'
-
_8
'RI" 750n.
tRAS '" 200ns
0
200
1.0
::l
U
40
::l
U
::l
U
5.0
Voo'" 13.2V
\/sa =-4.5V
Vea '" -S.OV
..t
Voo" 12.OVV•• i-5.5V
GRAPH 6
TYPICAL STANDBY CURRENT
1001 VS. AMBIENT TEMPERATURE
1.2
::l
U
V
TA =70"C
O.S
1.4
zW
II:
II:
0.9
Vee -SUPPLY VOLTAGE IVOLTS)
1.4
,/
1.0
0.7
4.0
-6.0
GRAPH 5
TYPICAL STANDBY CURRENT
1001 VS. VOO
1.0
~
a:
a:
50r-----._----~------._-----,
5or-----r-----r-----~----,
TA '" 25°C
Vas:=: -S.OV
TAJ250C
"
GRAPH 12
TYPICAL RAS ON L Y
REFRESH CURRENT
1003 VS. AMBIENT TEMPERATURE
vol"
40 _Voo=12.0V
Vas'" -S.OV
40r------r-----4------4_-----1
40
30
30r------r-----4------4_-----1
30~----4_-----+------4_-----1
20
20 r------r-----4---- ~ 375n5 -
12.0V -+------1-------1
r - - V ss =-50V
::>
<.J
~
::>
tRAS :: 200ns
'-............
'"I
8
E
10
tRC '" 375ns
........
tRAS '" 500ns
c
E
tRis
o
=
10r---~t___~._--.e~~--i
tRAC - 500ns
0, :-0-------:-,:-,------:',2:-----:',3:-----,='4
Voo - SUPPLY VOL TAGE (VOLTS)
TA - AMBIENT TEMPERATURE fOC)
GRAPH 13
TYPICAL PAGE MODE CURRENT
1004 VS.tpc
GRAPH 14
TYPICAL PAGE MODE CURRENT
1000
800
600
40
"
S
T A -25°C
Voo = 12.0V
>~
a:
a:
Vas'" -S.OV
30
::>
20
c
it
i~ ~=_3?OnS
'"I
E
v DO
40
10
teAS
o
200
400
iil
30
<.J
~
tpc = 225n5
-
20
~ r-
I
r'
a:
::>
teAS = 135n5
~
c
E
"
>~
a:
30
10
1
teAS
tpc
~ 12.0V
vss '" -s.ov
40
S
~
~
::>
50
! 25'C
Vas = -s.ov
<.J
<.J
GRAPH 15
TYPICAL PAGE MODE CURRENT
1004 VS. AMBIENT TEMPERATURE
1004 VS. VOO
50
::>
it
tRAS '" 500ns
tRC = 750ns
tRC - CYCLE TIME (ns)
400
TA
>~
a:
a:
1°r--~---=1~=~;;;:;-1
tRC 1= 750n5
200ns
50
S
c
E
°0L-----~20------~40------~60----~80
200
"
20~----4------+----~t~R~AS--~200VLns-1
it
::>
tCAS'" 135ns
tpc 225ns
20
'"I
~
c
350ns
10
E
I 500n,
tCAS '" 35On5
t PC 500ns
j'"
0
600
10
1000
800
12
11
13
Voo - SUPPLY VOLTAGE (VOLTS)
GRAPH 16
TYPICAL OUTPUT SOURCE CURRENT
JOH VS. OUTPUT VOLTAGE VOH
GRAPH 17
TYPICAL OUTPUT SINK CURRENT
IOL VS. OUTPUT VOLTAGE VOL
20
0
14
tpc - CYCLE TIME (ns)
40
60
80
TA - AMBIENT TEMPERATURE eC)
NOTES:
"s
>~
a:
a:
80
5l....
40
::>
l!:::>
0
I
"
::>
60
>~
a:
a:
Von'" 12.0V
20
-
<.J
"Z
;;;
...............
>-
40
::>
0
I
20
~
...............
...............
~
.9
=1
TA 25oC
_Voo"'12.0V
80
Vss = -S.5V
VCC '" 4.5V
S
TA=25°C
::>
""'a:
are indicated:
100
100
o
~
E
/
.IV
/
o
o
o
V OH - OUTPUT VOLTAGE (VOLTS)
1. The cycle time, VDD supply voltage, and
ambient temperature dependence of IDD1,
IDD2, IDD3 and IDD4 is shown in related
graphs. Common points of related curves
VOL - OUTPUT VOL TAGE (VOLTS)
3·71
•
IDDl @VDD= 13.2V, TA = O°C
•
IDD2 or I DD3 @ tRAS = 200ns, tRC =
375ns, VDD = 12.0V, T A = 25"C
'"
I DD2 or I DD3 @ tRAS = 500ns, tRC =
75005, VDD = 12.0V, TA = 25°C
o
I DD4 @ tCAS = 13505, tpc = 225ns,
VDD= 12.0V, TA=25"C
6.
I DD4 @ tCAS = 350ns, tpc = 500ns,
VDD = 12.0V, TA = 25°C
The typical I DD current for a given combination of cycle time, VDD supply
voltage and ambient temperature may be
determined by combining the effects of
the appropriate family of curves.
2117 FAMILY
D.C. AND A.C. CHARACTERISTICS, PAGE MODE[7,8,11]
TA = ooe to 7ooe,
VDD
= 12V±100f0, Vee = 5V±100f0,
VBB
= -5V±100f0,
Vss
= OV,
unless otherwise noted.
For Page Mode Operation order 2117-286053,2117-386054, or 2117-4 86055.
2117-2
86053
8ymbol
Parameter
Min.
Max.
2117-3
86054
Min.
Max.
2117-4
86055
Min.
Max.
Unit
Page Mode Read or Write Cycle
170
225
275
ns
tpCM
Page Mode Read Modify Write
205
270
CAS Precharge Time, Page Cycle
tRPM
RAS Pulse Width, Page Mode
60
150
80
200
340
100
ns
tcp
tCAS
CAS Pulse Width
100
1004
Voo Supply Current Page Mode,
Minimum tpc, Minimum tCAS
tpc
10,000
10,000
38
135
10,000
10,000
30
250
165
Notes
ns
10,000
10,000
ns
26
mA
ns
9
WAVEFORMS
PAGE MODE READ CYCLE
~----------------------------tRPM-------------------------------~1~
_
VIHC
RAS
t====-;;.:;t:===::j----------.....-j:,.:::::::-t-RS-H----~tRP~
_ V 1HC
CAS
WE
V1L.
V 1HC
+-_J
V" _ _ _
V OH
DOUT VOL------------~~
NOTES:
1,2. VIH MIN AND V/ L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF Dour.
5. tOFF IS MEASURED TO lOUT;;;; IlLO l.
ti, tRCH IS REFERENCeD TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST.
7. ALL VOLTAGES REFERENceD TO Vss.
8. AC CHARACTERISTIC ASSUME tT '" 5n5.
9.
THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNDER ALTERNATE CONDITIONS.
10. tcRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (i.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
11. ALL PREVIOUSLY SPECIFIED A.C. AND D.C. CHARACTERISTICS ARE APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE (i.e., 2117-3, S6054 WILL OPERATE AS A 2117-3).
see
3-72
2117 FAMILY
PAGE MODE WRITE CYCLE
ADDRESSES V ,H
VIL--~~~~~~~~~------t---~~~~~----~----~;---L~~~~~-----H------------
WE
V1HC
V,L------,-----~~~--~r_----------tf~------~----------~l~--_H~------~------~------------
PAGE MODE READ-MODI FY-WRITE CYCLE
i--------tCSH------i
CAS
~~RP_~~::~;;:r~--- 'cR. ----~
VIH
V"
ADDRESSES
~::
HIGH
IMPEDANCE
NOTES:
1,2.
3,4.
5,
6.
7.
V1H MIN AND V1l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF D OUT '
tOFF IS MEASURED TO lOUT';;; IILO I.
tos AND tOH ARE REFERENCED TO CAS OR 'WE, WHICHEVER OCCURS LAST.
tcRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (J.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
3-73
2117 FAMILY
APPLICATIONS
READ CYCLE
DATA OUTPUT OPERATION
A Read cycle is performed by maintaining Write Enable
(WE) high during a RAS/CAS operation. The output pin of
a selected device will remain in a high impedance state
until valid data appears at the output at access time.
The 2117 Data Output (DOUT), which has three-state
capability, is controlled by CAS. During CAS high state
(CAS at VIH) the output is in the high impedance state. The
following table summarizes the DOUT state for various
types of cycles.
Oevice access time, tACC, is the longer of the two
calculated intervals:
1. tACC = tRAC OR 2. tACC = tRCD
Intel 2117 Data Output Operation
for Various Types of Cycles
+ tCAC
Access time from RAS, tRAC, and access time from CAS,
tCAC, are device parameters. Row to column address
strobe delay time, tRCD, are system dependent timing
parameters. For example, substituting the device parameters of the 2117-3 yields:
Type of Cycle
DOUT State
Read Cycle
Data From Addressed
Memory Cell
HI-Z
HI-Z
HI-Z
Data From Addressed
Memory Cell
Indeterminate
Early Write Cycle
RAS-Only Refresh 'Cycle
CAS-Only Cycle
Read/Modify/Write Cycle
3. tACC = tRAC ;= 200nsec for 25nsec :StRCD :S65nsec
OR
4. tACC = tRCD + tCAC = tRCD + 135 for tRCD > 65nsec
Note that if 25nsec :StRCD :S65nsec device access time is
determined by equation 3 and is equal to tRAC. If tRCL
>65nsec, access time is determined by equation 4. This
40nsec interval (shown in the tRCD inequality in equation 3)
in which the falling edge of CAS can occur without
affecting access time is provided to allow for system
timing skew in the generation of CAS.
Delayed Write Cycle
HIDDEN REFRESH
A feature of the 2117 is that refresh cycles may be
performed while maintaining valid data at the output pin.
This feature is referred to as Hidden Refresh. Hidden
Refresh is performed by holding CAS at VIL and taking
RAS high and after a specified precharge period (tRP),
executing a "RAS-Only" refresh cycle, but with CAS held
low (see Figure below).
REFRESH CYCLES
Each of the 128 rows of the 2117 must be refreshed every 2
milliseconds to maintain data. Any memory cycle:
1. Read Cycle
2. Write Cycle (Early Write, Delayed Write or ReadModify-Write)
3. RAS-only Cycle
RAS
refreshes the selected row as defined by the low order
(RAS) addresses. Any Write cycle, of course, may change
the state of the selected cell. Using a Read, Write, or ReadModify-Write cycle for refresh is not recommended for
systems which utilize "wire-OR" outputs since output bus
contention will occur.
-{
MEMORY
CYCLE
"";~.=1
/ r---t'--_C..JYi
\
CAS
HIGHZ
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A RASonly refresh cycle maintains the DOUT in the high
impedance state with a typical power reduction of 20%
over a Read or Write cycle.
DOUT
(
DATA _ _- J
)'---_ _
This feature allows a refresh cycle to be "hidden" among
data cycles without affecting the data availability.
RAS/CAS TIMING
POWER ON
RAS and CAS have minimum pulse widths as defined by
tRAS and tCAS respectively. These minimum pulse widths
must be maintained for proper device operation and data
integrity. A cycle, once begun by driving RAS and/or CAS
low must not be ended or aborted prior to fulfilling the
minimum clock signal pulse width(s). A new cycle can not
begin until the minimum precharge time, tRP, has been
met.
The 2117 requires no power on sequence providing
absolute maximum ratings are not exceeded. After the
application of supply voltages or after extended periods of
bias (greater than 2 milliseconds) without clocks, the
device must perform a minimum of eight initialization
cycles (any combination of cycles containing a RAS clock,
such as RAS-Only refresh) prior to normal operation.
3·74
2117 FAMILY
POWER SUPPLY OECOUPLING/OISTRIBUTION
It is recommended that a 0.1/LF ceramic capacitor be
connected between VDD and Vss at every other device in
the memory array. A 0.1 /LF ceramic capacitor should also
be connected between VBB and Vss at every other device
(preferably the alternate devices to the VDD decouplingl.
For each 16 devices, a 10/LF tantalum or equivalent
capacitor should be connected between VDD and Vss near
the array. An equal or slightly smaller bulk capacitor is
also recommended between VBB and Vss for every 32
devices.
The Vcc supply is connected only to the 2117 output
buffer and is not used internally. The load current from the
Vcc supply is dependent only upon the output loading and
is associated with the input high level current to a TTL gate
and the output leakage currents of any OR-tied 2117's
(typically 1OO/LA or less total>. Intel recommends that a 0.1
or 0.01/LF ceramic capacitor be connected between Vcc
and Vss for every eight memory devices.
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution system on the array board should be minimized. It is
recommended that the VDD, VBB, and Vss supply lines be
gridded both horizontally and verticaily at each device in
the array. This technique allows use of double sided
circuit boards with noise performance equal to or better
than multi-layered circuit boards.
CASCD
A6CD
A5CD
A4CD
A3CD
A2CD
A1CD
AOCD
RASD
RASC
WECD
WEAB
RASB
RASA
CASAB
A6AB
A5AB
A4AB
A3AB
A2AB
A1AB
AOAB
!
,0'
DECOUPLING CAPACITORS
D = O.1/LF TO VDD TO VSS
B = O.1/LF VBB TO VSS
C = O.01/LF VCC TO Vss
.0
,
•
60
SAMPLE P.C. BOARD LAYOUT EMPLOYING VERTICAL
AND HORIZONTAL GRIDDING ON ALL POWER SUPPLIES.
BOARD ORGANIZATION: 64K WORDS BY 8-BITS.
64K BYTE STORAGE ARRAY LAYOUT
3-75
inter
2117-5
16,384 x 1 BIT DYNAMIC RAM
21,17-5
Maximum Access Time (ns)
3do
Read, Write Cycle (ns)
490
Read-Modify-Write Cycle (ns)
580
• Industry Standard 16-Pin Configuration
• Low Power: 462mW Max. Operating,
20mW Max. Standby
• Low 100 Current Transients
• All Inputs, Including Clocks,
TTL Compatible
• RAS Only Refresh
)
I
• Non-Latched Output is Three-State,
TTL Compatible
• 128 Refresh Cycles
Required Every 2ms
• Page Mode Capability
• CAS Controlled Output
Allows Hidden Refresh
The Intel® 2117 is a 16,384 word by 1-bit Dynamic MOS RAM fabricated with Intel's standard two layer polysilicon NMOS
technology - a production proven process for high performance, high reliability, and high storage density.
The 2117 uses a single transistor dynamic storage cell and advanced dynamic circuitry to achieve high speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients contribute to the high noise immunity of the 2117 in a system environment.
Multiplexing the 14 address bits into the 7 address input pins allows the 2117 to be packaged in the industry standard 16-pin
DIP. The two 7-bit address words are latched into the 2117 by the two TTL clocks, Row Address Strobe (RAS) and Column
Address Strobe (CAS), Non-critical timing requirements for RAS and CAS allow use olthe address multiplexing technique
while maintaining high performance.
The 2117 three-state output is controlled by CAS, independent of RAS. After a valid read or read-modify-write cycle, data is
latched on the output by holding CAS low. The data out pin is returned to the high impedance state by returning CAS to
a high state. The 2117 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to
execute RAS-only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RASonly refresh cycles, hidden refresh cycles, or normal read orwrite cycles on the 128 address combinations of Ao through A6
during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is addressed.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
AOAO
A,
A,
CAS
64)( 128 CELL
MEMORY ARRAY
D,N
A3
A,
A,
DOUT
As
RAS
CAS
DOUT
WE
PIN NAMES
AO~A6
ADDRESS INPUTS
WE
WRITE ENABLE
CAS
COLUMN ADDRESS STROBe
v••
POWER (-5V)
D,N
DATA IN
Vee
POwER (+5V)
DOUT
DATA OUT
VDD
POWER (+12V)
RAS
ROW ADDRESS STROBE
V"
GROUND
CAS-===~
~===============~----~
D,N
3-76
2117-5
ABSOLUTE MAXIMUM RATINGS*
'COMMENT:
Ambient Temperature Under Bias ... -10° Cto +80°C
Storage Temperature ............. -6So C to +1S00 C
Voltage on Any Pin Relative to Vss
(Vss - Vss 2: 4V) ............ . . . . . . . .. -0.3V to +20V
Data Out Current ............................ SOmA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the de·
vice at these or at any other condition above those indio
cated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating can·
ditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1,21
TA
= ooe to 70 oe,
Symbol
Voo
= 12V ±5%, Vcc = 5V
Parameter
±10%, VBB
= -5V ±10%,
Vss
= OV,
unless otherwise noted.
Limits
Min. TypPJ Max. Unit Test Conditions
Notes
JIll I
Input Load Current (any input)
0.1
10
!J.A VIN=VSS to VIHMAX, Vss=-S.OV
IILOI
Output Leakage Current for
High Impedance State
0.1
10
Chip Deselected: CAS at VIH,
!J.A VOUT = 0 to S.SV
4
1001
Voo Supply Current, Standby
1.S
mA CAS and RAS at VIH
ISS1
Vss Supply Current, Standby
1.0
SO
!J.A
ICC1
Vcc Supply Current, Output
Deselected
0.1
10
!J.A CAS at VIH
1002
Voo Supply Current, Operating
3S
mA 2117, tRC
ISS2
Vss Supply Current, Operating,
RAS-Only Refresh, Page Mode
1003
Voo Supply Current, RAS-Only
Refresh
1005
Voo Supply Current, Standby,
Output Enabled
VIL
Input Low Voltage (all inputs)
-1.0
0.8
VIH
Input High Voltage (all inputs)
2.4
6.0
V
VOL
Output Low Voltage
0.4
V
IOL = 4.2mA
4
VOH
Output High Voltage
V
IOH = -SmA
4
1S0
1.S
2.4
5
= 490ns,
tRAS
= 300ns
4
= 490ns,
tRAS = 300ns
4
400
!J.A TA = O°C
27
mA 2117, tRC
3
mA CAS at VIL, RAS at VIH
V
NOTES:
1. All voltages referenced to Vss.
2. No power supply sequencing is required. However, Voo, Vee and Vss should never be more negative than -O.3V with respect to VBB as
required by the absolute maximum ratings.
3. Typical values are for T1.\ = 25° C and nominal supply voltages.
4. See the Typical Characteristics Section for values of this parameter under alternate conditions.
5. Icc is dependent on output loading when the device output is selected. Vee is connected to the output buffer only. Vee may be reduced
to Vss without affecting refresh operation or maintenance of internal device data.
3-77
2117-5
TYPICAL SUPPLY CURRENT WAVEFORMS
: : ~f 1 11
I I I 1 I I 'TT I 1 I I CI"T T"" I I
125
IlruR
100
100
(mA)
75
50
25
J
1'1
~
I
rtf \
\~f1
J
l
A
I
I...
"'"
75
50
(rnA)
0
A
- 25
U
- 50
n
1\
I '\
25
IsS
r
II,
A
1I.
'oJ
_.
A
'V
A
I'
AV
,j
(
A
~\
!
"
-"
,
II .
- 75
125
100
Iss
(rnA)
rt
50
J\
/111 \
25
o
IIAlB I
1\
75
o
J I Y \ r- 1,1
100
200
300
\'\
400
500
100
TIME(ns)
200
300
400
500
600
700
800
900
~
J
II /'
J IV \Jo-V"
TIME(ns)
100
200
300
CAPACITANCE 11]
= 25°C,
Symbol
VDD
= 12V±5%, Vcc = 5V±10%,
VBB
500
The effects of cycle time, Voo supply voltage and ambient
temperature on the 100 current are shown in graphs
included in the Typical Characteristics Section. Each
family of curves for 1001, 1002, and 1003 is related by a
common pOint at Voo = 12.0V and TA = 25°C for two given
tRAS pulse widths. The typical 100 current for a given
condition of cycle time, Voo and TA can be determined by
combining the effects of the appropriate family of curves.
Typical power supply current waveforms vs. time are
shown for the RAS/CAS timings of Read/Write, Readl
Write (Long RAS/CAS). and RAS-only refresh cycles. 100
and IBB current transients at the RAS and CAS edges
require adequate decoupling of these supplies. Decoupling recommendations are provided in the Applications
section.
TA
400
TlME(ns)
= -5V±10%,
Parameter
Vss
= OV,
unless otherwise specified.
Typ.
Max.
Unit
CI1
Address, Data In
3
5
pF
CI2
RAS Capacitance, WE Capacitance
4
7
pF
CI3
CAS Capacitance
6
10
pF
Co
Data Output Capacitance
4
7
pF
NOTES:
1. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation:
C = I..l.t with ..l.V equal to 3 volts and power supplies at nominal levels .
..l.V
3-78
2117-5
A.C. CHARACTERISTICS [1,2,3]
TA = O°C to 70°C, VOO = 12V ±5%, Vee = 5V ±10%, Vee = -5V ±10%, Vss = OV, unless otherwise noted,
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
2117
Parameter
Symbol
Min.
Max.
Unit
Notes
tRAC
Access Time From RAS
300
ns
tCAC
Access Time From CAS
ns
4,5
4,5,6
tREF
Time Between Refresh
180
2
tRP
RAS Precharge Time
tCPN
tCRP
CAS Precharge Time1non-pagecycles)
CAS to RAS Precharge Time
tRCO
RAS to CAS Delay Time
tRSH
RAS Hold Time
tCSH
CAS Hold Time
tASR
Row Address Set-Up Time
tRAH
Row Address Hold Time
tASC
Column Address Set-Up Time
tCAH
Column Address Hold Time
tAR
Column Address Hold Time, to RAS
tT
Transition Time (Rise and Fall>
tOFF
Output Buffer Turn Off Delay
180
80
-20
80
180
300
0
80
ms
ns
ns
ns
120
ns
7
ns
ns
ns
ns
0
ns
80
215
3
0
ns
50
80
490
300
180
10000
10000
ns
ns
8
ns
READ AND REFRESH CYCLES
tRC
Random Read Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
tRCS
Read Command Set-Up Time
tRCH
Read Command Hold Time
ns
0
0
ns
ns
ns
ns
WRITE CYCLE
tRC
Random Write Cycle Time
tRAS
RAS Pulse Width
tCAS
CAS Pulse Width
twcs
Write Command Set-Up Time
tWCH
Write Command Hold Time
tWCR
Write Command Hold Time, to RAS
twp
Write Command Pulse Width
tRWL
Write Command to RAS Lead Time
tCWL
Write Command to CAS Lead Time
tos
Data-In Set-Up Time
tOH
Data-In Hold Time
tOHR
Data-In Hold Time, to RAS
490
300
180
0
100
215
100
130
130
0
80
215
ns
10000
10000
ns
ns
ns
9
ns
ns
ns
ns
ns
ns
ns
ns
READ-MODIFY-WRITE CYCLE
tRWC
Read-Modify-Write Cycle Time
tRRW
RMW Cycle RAS Pulse Width
tCRW
RMW Cycle CAS Pulse Width
tRwO
RAS to WE Delay
tcwo
CAS to WE Delay
580
390
275
260
140
Notes: See following page for A.C. Characteristics Notes.
3·79
ns
10000
10000
ns
ns
ns
ns
9
9
2117-5
WAVEFORMS
'i
'RC
READCY CLE
i~- tRP------i
tAAS
V,H
ill
C0 ~@
v"
CAs
C0
I----
tASR
'lH
V,L
K
ROW
ADDRESS
\\\\ @
I--
I--tRAH----+
~
ADDRESSES
t ASH -
tRCO
f
V,L
~'c-==1
'CSH
~~
®teRP-j
V,H
fi
'AR
'ASC
)(
'I
teAS
1I
~teAH--
x:
COLUMN
ADDRESS
_~tRCS
We
V,H
V,L
H'Rc/V
&
\
.
teAC
tRAC
~toFF-
CD
Dour
HIGH
r-V-A-L-ID----""""\l
VOH
VOL --------------~IM~P~E~D~AN~C~E~--------------------------------------~~~~ID-A-T-A_O_U_T________-1
WRITE CY CLE
'RC
I-'R~
tRAS
G)
®teRP - j
~.
I'®
tRCo
/I
tASR-r---ADDRESSES
V'L
)(D®
l:---tePN~1
tCSH
~t-
V,H
®
tRSH
G)
--tRAH------j
tASC-
IF
teAS
1\\'\1'O
'AR
I-
!---teAH-
ROW·X ~
~
COLUMN
ADDRESS
ADDRESS
.
t RwL
'<:wL
&.
-+--twcs--
_ t WCH twP
II
"
'wCR
I-®'OS- i - - - - · O H @ -
)
D'N
G)
K
®
tOHR
~~~-·--------------~IM~P~~~~~:N~C~E~--------------------------------------------------------------NOTES:
1,2.
3,4.
5.
6.
7.
VIH MIN AND V 1L MAX ARE REFERENCE lEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DoUT tOFF IS MEASURED TO lOUT';;; IILO (.
tos AND tOH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
tRcH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCUR.!£..!RST.
8. ~~L :~~~~~E(~e~.N;~~ ~~;;E~~~~E':EL~:~~ARs~6;~ECE~c~~~~~~ge;~~DRBA~t CAS-
A.C. CHARACTERISTICS NOTES (From Previous Page)
1. All voltages referenced to Vss.
2. Eight cycles are requirec!!!!!er power-up or prolonged periods
(greater than 2ms) of RAS inactivity before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
3. A.C. Characteristics assume tT = 5ns.
4. Assume that tRCD :5 tRCD (max.l. If tRCD is greater than tRCD
(max.l then tRAC will increase by the amount that tRCD exceeds
tRCD (max.l.
5. Load = 2 TTL loads and 100pF.
6. Assumes tRCD 2: tRCD (max.l.
7. tRCD (max.l is specified as a reference point only; if tRCD is less
than tRCD (max.l access time is tRAC, if tRCD is greater than tRCD
(max.l access time is tRCD + tCAC.
8. tT is measured between VIH (min.l and VIL (max.l.
9. twcs, tcwD and tRwD are specified as reference points only. If
twcs 2: twcs (min.l the cycle is an early write cycle and the data
out pin will remain high impedance throughout the entire
cycle. If tCWD 2: tcwD (min.l and tRWD 2: tRwD (min.l, the cycle is
a read-modify-write cycle and the data out will contain the data
read from the selected address. If neither of the above
conditions is satisfied, the condition of the data out is
indeterminate.
3-80
2117-5
WAVEFORMS
READ-MODI FY-WRITE CYCLE
tRwe
-1--,,,--1
tRRW
G\ ®
1/
0'cR'-j
'cSH
tRCD
~'''N-I
tRSH
(D K.\\\ ®
'~
tcRW·
~-"'R
tRAH
tA.SR-ADDRESSES
~::
tASC-"
XCD AO~~SS X
®
~Wl~
X ;g~~~
tRcsi~
~tCWL---
-teAH
K
tRWO
~~'-V
tCWD
0(0/
"I -'-"0"®
®'o,
XCI)
DATA
IN
VALID
I 0
f-:---'cAC~
tRAe
HIGH
,
IMPEDANCE
-
(~,
®
K
VALID
DATA OUT
-
tOFF
®
RAS-ONL Y REFRESH CYCLE
~-------------'R'---------------~
'RAS------ir'R'---t
'----
I
r- tCRP ®
X CD AD'6~ss ] (
V"--~f0~2~~~~--~-----------------------------------------------------------
ADDRESSES V'H
DOUT
VOH
HIGH
VOL----------------------------------~,M~P~ED~A~N~CE~-----------------------------------
HIDDEN REFRESH CYCLE
ADDRESSES
0'
NOTES:
V"
V,"
V"
m
Do '"
v,"
VVOO~----------------I"""'-----------------VALI~OATA_
.....,;,.....----------------------~@FF
•
12. V 1H MIN AND V IL MAX ARE REFERENCE LEVELS fOR MEASURING TIMING OF INPUT SIGNALS.
3,4. VOH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DO UT '
5. toFF IS MEASURED TO lOUT <: IILO I.
6. tos AND tOH ARE REFERENCED TO CAS OR m, WHICtfEVER OCCURS LAST.
~: ~~~ ~~~~~~;~~~~~:OO~~~ ~~~~~6~i~~~~~~~~~~; cRv'6SL~H~~~~~i~E~~~~SC~-ST.
ONLY CYCLE
Ii.e.• FOR SYSTEMS WHERE CAS HAS NOT BEEN OECOOED WITH RASI,
3-81
2117-5
TYPICAL CHARACTERISTICS [1 J
GRAPH 1
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS. VOO
1.2
1.2
~
~
1.1
::!
"cc
"~
.
I!:
=>
~
I
'a.. I"--..
~
Q
E
Vaa '" -S.OV
401---+--~--~---i
I-
I-
iiia:
10
30~----~------~----~----~
20~----~----__~----~----~
_
I
tRAS = SOOns
_8
+ __......
tRAS '" 300ns
- - tR~ = 490nl
200
400
600
800
'Rl
1000
.
Q
t
iil
20
~
tRAS "" 300ns
tRC; - 490n5
I
~
10
-750..
tRAS = 500ns
tRC = 750ns
20
40
60
80
TA - AMBIENT TEMPERATURE I'C)
GRAPH 13
TYPICAL PAGE MODE CURRENT
1004 VS.tpc
GRAPH 14
TYPICAL PAGE MODE CURRENT
GRAPH 15
TYPICAL PAGE MODE CURRENT
1004 VS. AMBIENT TEMPERATURE
1004 VS. VOO
50
50
0....
~"350ns
iiia:
a:
E
teAS - 1 BOn.
30
=>
u
~
I!:
teAS"" 180ns
20
.
~ :;--'" tpc t = 310n5
-
I
Q
10
40
I-
30
">....
20
Vas = -s.OV
Voo ~ 12.0V
=25°C
Vas'" -S.OV
l-
w
a:
a:
30
>
....
E
30
Voo -SUPPLY VOLTAGE IVOLTS)
zI-
t
iil
~
a
TRC - CYCLE TIME (n$)
TA
w
a:
a:
=>
u
V Bs""-5.0V
iii
~·~0----~17,----~12~----~13~----~,4
50
.s
_yJ-,2.0V
40
~
~~_ tAAC = 500ns
10 ' -____
r
o
1
I-
tRis '" 300';'""
u
w
u
a:
~
l-
20
'"
E
...............
=>
60
I-
40
z"
"
in
=>
~
=I25"C
•
10D1@VOO=12.6V,TA=0°C
Voo=12.DV
Vas'" -5.5V
Vee =4.5V
•
1002 or 1003 @tRAS= 300ns, tRC =
490n., VOO = 12.0V, TA = 25°C
•
1002 or 1003 @ tRAS = 500ns, tRC =
750ns, VOO = 12.0V, TA = 25°C
o
1004@tCAS= 180ns, tpc = 310n.,
VOO = 12.0V, TA = 25°C
t:.
1004 @ tCAS = 350ns, tpc = 500ns,
VOO = 12.0V, TA = 25°C
TA
BO
_
iiia:
VOO -12.0V
=>
0
I
I-
TA=25°C
/
~
.IV
=>
0
I
.............
o
o
4
VOH -OUTPUTVOLTAGE IVOLTS)
~
E
20
1. The cycle time, V 00 supply voltage, and
ambient temperature dependence of 1001,
1002, 1003 and 1004 is shown in related
graphs. Common pOints of related curves
are indicated:
V
o
o
VOL - OUTPUT VOLTAGE IVOL TS)
3-83
The typical 100 current for a given combination of cycle time, VOO supply
voltage and ambient temperature may be
determined by combining .the effects of
the appropriate family of.diJrves.
2117-5
D.C. AND A.C. CHARACTER,ISTICS, PAGE MODE[7.B.lll
TA
= O°C to 70°C,
Voo
= 12V ±5%, Vee = 5V ±10%, VBB = -5V ±10%, Vss = OV,
For Page Mode Operation order 2117 S6117.
2117-5
S6117
Symbol
Parameter
Min.
Max.
Unit
tpc
Page Mode Read or Write Cycle
310
ns
tpCM
Page Mode Read Modify Write
405
ns
tcp
CAS
tRPM
RAS Pulse Width. Page Mode
300
10,0.00
tCAS
CAS Pulse Width
180
10.000
ns
1004
Voo Supply Current Page Mode,
Minimum tpc. Minimum tCAS
26
mA
P~echarge
Time. Page Cycle
120
Notes
ns
ns
9
WAVEFORMS
PAGE MODE READ CYCLE
_V1HC
RAS
WE
+-_",
V1HC
V,L _ _ _
V OH
Dour VOL-----------~~
NOTES:
1.2. V1H MIN AND V 1l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT '
5. tOFF IS MEASURED TO lOUT';;; IIlO I.
6. tRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR W, WHICHEVER OCCURS FIRST.
7. ALL VOLTAGES REFERENCED TO Vss.
8. AC CHARACTERISTIC ASSUME tT = 5ns.
g. see THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNOER ALTERNATE CONDITIONS.
10. tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE 0 .•.• FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
11. ALL PREVIOUSLY SPECIFIED A.C. AND O.C. CHARACTERISTICS ARI: APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE 0 .... 2117·5. 86117 WILL OPERATE AS A 2117·5).
3-84
unless otherwise noted.
2117-5
PAGE MODE WRITE CYCLE
WE
V1HC
VIL ____
~----_+~~--_+----------~~----_+----------~~--~~------~----_f-----------
PAGE MODE READ-MODIFY-WRITE CYCLE
ADDRESSES
WE
NOTES:
~:: _~~~Io.L~;:::~I-_ _+ ____+....L~~Clo.__-I____-+__ ......L~i='p.---I-----I--V 1H
v" _ _-+-.::~
1.2. V 1H MIN AND V 1L MAX ARE REFERENCE lEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE lEVELS FOR MEASURING TIMING OF Dour.
5. tOFF IS MEASURED TO lOUT';;;; IILO I.
6. tos AND tOH ARE REFERENCeD TO CAS OR~. WHICHEVER OCCURS LAST.
7. tCRP REQUIREMENt IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE h.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
3-85
2117·5
APPLICATIONS
READ CYCLE
DATA OUTPUT OPERATION
A Read cycle is performed by maintaining Write Enable
(WE) high during a RAS/CAS operation. The output pin of
a selected device will remain in a high impedance state
until valid data appears at the output at access time.
The 2117 Data Output (DOUT). which has three-state
capability. is controlled by CAS. During CAS high state
(CAS at VIH) the output is in the high impedancestate. The
following table summarizes the DouT state for various
types of cycles.
Device access time. tACC. is the longer of the two
calculated intervals:
1. tACC = tAAC OR 2. tAcc = tACO
Intel 2117 Data Output Operation
for Various Types of Cycles
+ tCAC
Access time from RAS. tAAC. and access time from CAS.
tCAC. are device parameters. Row to column address
strobe delay time. tACO. are system dependent timing
parameters. For example. substituting the device parameters of the 2117 yields:
Type of Cycle
COUT State
Read Cycle
Data From Addressed
Memory Cell
fo:Il-Z
HI.-Z
HI-Z
Data From Addressed
Memory Cell
Indeterminate
Early Write Cycle
RAS-Only Refresh Cycle
CAS-Only Cycle
Read/Modify/Write Cycle
3. tAcc = tAAC = 300nsec for 80nsec :5tACO :5120nsec
OR
. 4. tAcc = tACO + tCAC = tRco + 180 for tACO> 120nsec
Note that if 80nsec :5tACO :5120nsec device access time is
determined by equation 3 and is equal to tAAC. If tACO
>120nsec. access time is determined by equation 4. This
40nsec interval (shown in the tACO inequality in equation 3)
in which the falling edge of CAS can occur without
affecting access time is provided to allow for system
timing skew in the generation of CAS.
gelayed Write Cycle
HIDDEN REFRESH
A feature of the 2117 is that refresh cycles may be
performed while maintaining valid data at the output pin.
This feature is referred to as Hidden Refresh. Hidden
Refresh is performed by holding CAS at VIL and taking
RAS high and after a specified precharge period (tAP).
executing a "RAS-Only" refresh cycle. but with CAS held
low (see Figure below),
REFRESH CYCLES
Each of the 128 rows ofthe 2117 must be refreshed every 2
milliseconds to maintain data. Any memory cycle:
1. Read Cycle
2. Write Cycle (Early Write. Delayed Write or ReadModify-Write)
3. RAS-only Cycle
iiAs
refreshes the selected row as defined by the low order
(RAS) addresses. Any Write cycle. of course. may change
the state of the selected cell. Using a Read. Write. or ReadModify-Write cycle for refresh is not recommended for
systems which utilize "wire-OR" outputs since output bus
contention will occur.
-{
MEMORV
CYCLE
---"*--""~~::=J
. \
/ ,----t\--._C.vi
CAS
HIGHZ
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A RASonly refresh cycle maintains the DouT in the high
impedance state with a typical power reduction of 20%
over a Read or Write cycle.
DOUT
(' - - - - - - - - - '
DATA
)-
This feature allows a refresh cycle to be "hidden" among
data cycles without affecting the data availability.
miCAS TIMING
RAS and CAS have minimum pulse widths as defined by
POWER ON
tRAS and tCAS respectively. These minimum pulse widths
must be maintained for proper device operation and data
integrity. A cycle. once begun by driving RAS andlor CAS
low must not be ended or aborted prior to fulfilling the
minimum clock signal pulse width(s), A new cycle can not
begin until the minimum precharge time. tAP. has been
met.
The 2117 requires no power on sequence providing
absolute maximum ratings are not exceeded. After the
application of supply voltages or after extended periods of
bias (greater than 2 milliseconds) without clocks. the
device must perform a minimum of eight initialization
cycles (any combination of cycles containing a RAS clock.
such as RAS-Only refresh) prior to normal operation.
3-86
2117-5
POWER SUPPLY DECOUPLING/DISTRIBUTION
is associated with the input high level current to a TTL gate
and the output leakage currents of any OR-tied 2117's
(typically 100J.LA or less total). I ntel recommends that a 0.1
or 0.01J.LF ceramic capacitor be connected between Vee
and Vss for every eight memory devices.
It is recommended that a 0.1 J.LF ceramic capacitor be
connected between Voo and Vss at every other device in
the memory array. A 0.1 J.LF ceramic capacitor should also
be connected between VBB and Vss at every other device
(preferably the alternate devices to the Voo decouplingl.
For each 16 devices, a 10J.LF tantalum or equivalent
capacitor should be connected between Voo and Vss near
the array. An equal or slightly smaller bulk capacitor is
also recommended between VBB and Vss for every 32
devices.
Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution system on the array board should be minimized. It is
recommended that the Voo, VBB, and Vss supply lines be
gridded both horizontally and vertically at each device in
the array. This technique allows use of double sided
circuit boards with noise performance equal to or better
than multi-layered circuit boards.
The Vee supply is connected only to the 2117 output
buffer and is not used internally. The load current from the
Vee supply is dependent only upon the output loading and
-~
•
•
DIN DOUT
DECOUPLING CAPACITORS
D = O.1J.LF TO VDD TO VSS
B - O.1"F VBB TO Vss
C = O.01"F VCC TO Vss
SAMPLE P.C. BOARD LAYOUT EMPLOYING VERTICAL
AND HORIZONTAL GRIDDING ON ALL POWER SUPPLIES.
BOARD ORGANIZATION: 64K WORDS BY 8-BITS.
64K BYTE STORAGE ARRAY LAYOUT
3-87
'''-Iv
2118 FAMILY
16,384 x 1 BIT DYNAMIC RAM
2118-2
80
200
250
Maximum Access Time (ns)
Read, Write Cycle (ns)
Read-Modlfy-Wrlte Cycle (ns)
• Single +5V SuP,ply, ±10% Tolerance
2118-4
120
270
345
'~k, l~ ~
,
"', 'r ,;::: ,{r. . .
.y}4.~~
.j
2118-7
150
320
410
• Non-Latched Output is Three-State,
TTL Compatible
• HMOS Technology
• RAS Only Refresh
• 128 Refresh Cycles Required
Every 2ms
• Low Power: 160mW !"lax. Operating
16mW Max. Standby
•
2118-3
100
235
295
\
Low Voo Current Transients
• Page Mode Capability
• CAS Controlled Outp~t Allows
Hidden Refresh
• All Inputs, Including Clocks,
TTL Compatible
The Intell!!> 2118 is a 16,384 word by l-bit Dynamic MOS RAM designed to operate from a single +5V power supply. The 2118
is fabricated using HMOS - a production proven process for high performance, high reliability, and high storage density.
The 2118 uses a single transistor dynamic storage cell and advanced dynamic circuitry to achieve ~igh speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients contribute to the high noise immunity of the 2118 in a system environment.
Multiplexing the 14address bits into the 7 address input pins allows the 2118 to be packaged in the industry standard 16-pin
DIP. The two 7-bit address words are latched into the 2118 by the two TTL clocks, Row Address Strobe (RA~) and Column
Address Strobe (CAS). Non-critical timing requirements for ~and CAS allow use of the address multiplElxing technique
while maintaining high performance.
The 2118 three-state output is controlled by CAS, independent of RAS. After a valid read or read-modify-write cycle, data is
latched on the output by holding CASlow. The data out pin is returned to the high impedance state by returning CAS to a
high state. The 2118 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to execute
RAS-only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RASonly refresh cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of f1:.o through A6
during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is addressed.
PIN
CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
-Voo
64 II; 128 CELL
MEMORY ARRAX
128 SENSE
AMPLIFIERS
OUTPUT
1 OF 64 COLUMN
BUFFER
DECODERS
64x 128 CELL
MEMORY ARRAY
AO-As
ADDRESS INPUTS
CAS
COLUMN ADDRESS STROBE
D,N
DATA IN
DOUT
DATA OUT
WE
WAITE ENABLE
RAS
ROW ADDRESS STROBE
Voo
POWER (+5V)
Vss
GROUND
o,N
3-88
_VSS
DouT
,
inter
2141
4096 X 1 BIT STATIC RAM
2141-2
2141-3
2141-4
2141-5
2141L-3
Max. Access Time (ns)
120
150
200
250
Max. Active Current (mA)
70
20
70
55
20
12
55
12
150
40
Max. Standby Current (mA)
• HMOS Technology
• Industry Standard 2147 Pinout
• Completely Static Memory or Timing Strobe Required
2141L-4
200
5
40
250
40
5
5
• Automatic Power-Down
• Directly TTL Compatible and Output
No Clock
2141L-5
All Inputs
• Separate Data Input and Output
• Three-State Output
• High Density 18-Pin Package
• Equal Access and Cycle Times
• Single +5V Supply
The Intel® 2141 is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using HMOS, a highperformance MOS technology. It uses a uniquely innovative design approach which provides the ease-of-use features
associated with non-clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high - deselecting the 2141 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as CS remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are deselected.
The 2141 is placed in an 18-pin package configured with the industry standard pinout, the same as the 2147. It is directly TTL
compatible in all respects: inputs, output, and a single +5V supply. The data is read out nondestructivelyand has the same
polarity as the input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
LOGIC SYMBOL
Ao
AD
vee
A,
A6
A,
A,
A3
A,
A,
A,
A,
AlO
DOUT
A"
D,N
A,
As Dour
A,
A,
A,
A'D
Cs
DIN WE CS
WE
GND
BLOCK DIAGRAM
@
A,
A,
A3
-Vee
®
-GND
A.
MEMORY ARRA Y
64 ROWS
64 COLUMNS
A"
D,N
PIN NAMES
AD-A" ADDRESS INPUTS
WRITE ENABLE
WE
CHIP SELECT
DATA INPUT
D,N
DATA
OUTPUT
Dour
@
-=-----1
Vee POWER (+5V)
GND GROUND
cs
TRUTH TABLE
CS
WE
H
L
L
X
L
H
MODE
NOT SE LECTEO
WRITE
READ
CS
OUTPUT
POWER
HIGH Z
HIGH Z
STANDBY
ACTIVE
ACTIVE
DOUT
WE
®
3-89
DOUT
2141
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias ............... -1O·C to 85·C
Storage Temperature ............... -65·Cto+150·C
Voltage on Any Pin With
RespecttoGround .................... -1.5V to +7V
Power Dissipation •............................ 1.2W
D.C. Output Current ....•..................... 20mA
D.C. AND OPERATING CHARACTERISTICS
= o·c to 70·C, Vee = +5V±10% unless otherwise noted.
TA
Symbol
Parameter
2141-4/-5
2141 L-3/L-4/L-5
2141·2/-3
Min, Typ.l1j Max. Min. Typ.l1j Max. Min. Typ.[1j Max.
Unit
Conditions
III
Input Load Current
(All Input Pins)
0.01
10
0.01
10
0.01
10
p.A
Vee~Max., VIN~
IILOI
Output Leakage
Current
0.1
10
0.1
10
0.1
10
p.A
lee
Operating Current
45
ISB
Standby Current
20
Ipol2,
Peak Power-On
Current
40
GND to Vee
~~VIH, Vee~Max.,
Vour~GND
70
40
to 4.5V
40
rnA
Vee~Max., CS~Vll,
12
5
rnA
Outputs Open
Vee~Min. to Max.,
30
18
rnA
55
30
CS~VIH
Vee~GND
CS~Lower
to Vee Min.
of Vee or
-
VIH Min.
Vil
Input Low Voltage
-1.0
2.0
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
IOS[3 1
Output Short Circuit
Current
-120
0.8
-1.0
6.0
2.0
0.4
0.8
-1.0
0.8
6.0
2.0
6.0
V
0.4
V
10l =8.0mA
II
10H = -4.0mA
0.4
2.4
120
2.4
120
-120
-120
120
V
rnA
Vour=GND to Vee
Notes: 1. Typical limits are at Vee ~ 5V, TA ~ +25·C, and specified loading.
2. lee exceeds ISB maximum during power-on, as shown in Graph 7. A pull-up resistor to Vee on the
keep the device deselected; otherwise, power-on current approaches lee active.
3. Duration not to exceed one minute.
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference
Levels
Output Load
GND to 3.5 Volts
10 nsec
1.5 Volts
1 TTL Load plus 100pF
CAPACITANCE [41
TA
= 25·C, f = 1.0MHz
Symbol
Parameter
Max. Unit
Conditions
CIN
Input Capacitance
5
pF
VIN
COUT
Output Capacitance
6
pF
VOUT ~ OV
~OV
Note 4. This parameter is sampled and not 100% tested.
3·90
CS
input is required to
2141
A.C. CHARACTERISTICS
TA
= O·C to 70·C, Vee = +5V±10Dfo, unless otherwise noted.
READ CYCLE
Symbol
Parameter
2141-2
Mex.
Min.
2141-3/L-3
Min.
Max.
2141-4/L-4
Min.
Max.
2141-S/L-S
Min.
Max.
Unit
120
150
200
250
ns
IRc
Read Cycle Time
t ......
Address Access Time
120
150
200
250
ns
t... CS1[1]
Chip Select Access Time
120
150
200
250
ns
t...cs212]
Chip Select Access Time
130
160
200
250
ns
tOH
Output Hold from Address Change
10
10
10
10
ILz 131
Chip Selection to Output in Low Z
30
30
30
30
tHz '31
Chip Deselection to Output in High Z
0
tpu
Chip Selection to Power Up Time
0
tpo
Chip Deselection to Power Down Time
60
0
60
60
0
0
0
60
0
60
ns
ns
60
60
ns
ns
0
60
ns
WAVEFORMS
READ CYCLE NO.1
[4,51
tRC -
ADDRESS
-t.A---Il
---'\(-
--.J
.-
1----1:
-'F-
tOH----~i
OATAOUT-------PR-E-V-'O-U-S-DA-T-A-V-A-lI-D----~~~.Y-)(~-T)(~ ------------------O-A-T-A-VA-L-'O------------------------
READ CYCLE NO.2
[4.6J
tRe
co ---"'\
K
'ACS
-'HZ-
tlZ
DATA OUT
HIGH IMPEDANCE
~X
X~
Vee
IMPEDANCE
::------1-50%---==L
I---- t.u
SUPPL V
CURRENT
HIGH
OATA VALID
I--t,o
Notes:
1. Chip deselected for greater than 55ns prior to selection.
2. Chip deselected for a finite time that is less than 55ns prior to selection. (If the deselect time is Ons, the chip is by definition
selected and access o.ccurs according to Read Cycle No.1,)
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device.
4. WE is high for Read Cycles.
5. Device is continuously selected, CS = V,L.
6. Addresses valid prior to or coincident with CS transition low.
3-91
2141
A.C. CHARACTERISTICS
TA
= o'e to 70'e,
Vee
= +5V±10%, unless otherwise noted.
WRITE CYCLE
2141-2
Symbol
Parameter
Min.
twe
Write Cycle Time
120
tew
Chip Selection to End of Write
lAw
Address Valid to End of Write
tAS
2141-3/L-3
Max.
Min.
2141-4/L-4
Max.
Min.
Max.
2141-S/L-S
Min.
Max.
Unit
200
250
ns
110
150
135
180
230
ns
110
135
180
230
ns
Address Setup Time
0
0
0
0
ns
twp
Write Pulse Width
60
60
60
75
ns
tWR
Write Recovery Time
10
15
20
20
ns
tow
Data Valid to End of Write
50
60
60
75
ns
tDH
Data Hold Time
twz
Write Enabled to Output in High Z
tow
Output Active from End of Write
5
5
10
70
10
5
5
80
10
5
5
ns
5
80
10
80
5
WAVEFORMS
WRITE CYCLE #1 (WE CONTROLLED)
'we
~
ADDRESS
--'
tew
(:SIt
1\
IL
tAW
tAS
'wP
I
LiLI
-'wR-
\\
tow
DATA IN
tOH_
DATA IN VALID
_________________=1
IMPEDANCE~------==>It--..;.;.;====-~--i.'"---~-I---twz
-'ow
HIGH
DATA OUT
DATA UNDEFINED
WRITE CYCLE #2 (CS CONTROLLED)
'we
ADDRESS
~
----
tAS
'cw
h
tAW
'wP
-'wR-
11111111
\\\\\\\\\\
t
'ow
DATA IN
OH
_
DATA IN VALID
i+-- 'wz
DATA OUT
-----------------=-1
HIGH IMPEDANCE
:)
.._ _ _ _ _ _ _ _ _ _ _ _ _ __
DATA UNDEFINED
Note: 1. If CS goes high simultaneously with
WE
high, the output remains in a high impedance state.
3-92
ns
ns
2141
TYPICAL D.C. AND A.C. CHARACTERISTICS
GRAPH 1
SUPPLY CURRENT VS.
SUPPL Y VOLTAGE
GRAPH 3
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
GRAPH 2
SUPPLY CURRENT VS.
AMBIENT TEMPERATURE
100
40
40
r--- ~ r--
ICC
30
30
T5.0V
f--- vee"
80
TA
25 C
==
_60
«
!
TA '25'C
4.S0
4.75
""
20
ISB
o
a
5.S0
5.25
5.00
.!? 40
10
I
IS8
:r
Vee "S.OV -
L-
10
o
-
a
20
60
80
a
1.0
2.0
V aUT (VI
Vee (VI
GRAPH 4
NORMALIZEO ACCESS TIME
VS. SUPPLY VOLTAGE
~ 1.0
I:=:...
t'l
1.0
'AA
-<
-<
_
:!-
60
~ .9~--+---4--.~~--~
«
«
240
a;
a:
T A "25'C -
.9
:::;
::E
:IE
~
.8
.8
4.75
S.OO
Vee (VI
S.25
5.50
20
GRAPH 7
TYPICAL POWER-ON CURRENT
VS. POWER SUPPLY VOLTAGE
Ipo
-- - -
1.6
/
Jl
1.2
ISB
.8
.4
20
a
.7
4.50
2.0
I----h,.,£,.,.,£.+-
f--i
II
7\
--
80
\
o
~
/
- 10
TA
V
/
" 70"C
eel " 5.0V
CS PULL-UP RESISTOR TO Vee
Vee (VI
2.0
V OUT IVI
~
~
3.0
4.0
5.0
"125 C
TA
1.0
.,:!-
2.0
vee' 5.0V _
:;"
-- ~
TA "2S"C
1.0
/
1.0
2.0
V ,N (VI
3-93
3.0
4.0
3.0
20
I
1 K!2
/
/
GRAPH 9
ACCESS TIME CHANGE VS.
OUTPUT LOADING
GRAPH 8
ACCESS TIME CHANGE VS.
INPUT VOLTAGE
20
--
/
V
60
/
if
"
!
~
/
I---+---+---+--;r---I
~~
:!:!~
N
:::;
100
80
tACS
4.0
GRAPH 6
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
GRAPH 5
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
1.1 r - - - , - - - - , . - - - - - r - - - - - ,
1.1
~
3.0
4.0
~
V
V
V
TA
== 70"C
Vee
MIIN
I
100
200
c,
300
(pFI
400
500
2141
DEVICE DESCRIPTION
There is no functional constraint on the amount of time the
2141 is deselected. However. there is a relationship
between deselect time and Chip Select access tim,e. With
no compensation. the automatic power switch' would
cause an increase in Chip Select access time. since some
time is lost in repowering the device upon selection. A
feature of the 2141 design is its ability to compensate for
this loss. The amount of compensation is a function of
deselect time. as shown in Figure 3. For short deselect
times. Chip Select access time becomes slower than
address access time. since full compensation typically
requires 60ns. For longer deselect times. Chip Select
access ti me actually becomes faster than address access
ti me because the compensation more than offsets the ti me
lost in powering up. The spec accounts for this
characteristic by specifying two Chip Select access times.
tACS1 and tACS2.
The 2141 is produced with HMOS. a new highperformance MOS technology which incorporates onchip substrate bias generation to achieve high- performance. This process. combined with new design ideas.
gives the 2141 its unique features. Both low power and
ease-of-use have been obtained in a single part. The lowpower feature is controlled with the Chip Select input.
which is not a clock and does not have to be cycled.
Multiple read or write operations are possible during a
single select period. Access times are equal to cycle times.
resulting in data rates up to 8.3 MHz for the 2141-2. This is
considerably higher performance than for clocked static
designs.
Whenever the 2141 is deselected. it automatically reduces
its power requirements to a fraction of the active power. as
shown in Figure 1. This is achieved by switching off the
power to unnecessary portions of the internal peripheral
circuitry. This feature adds up to significant system power
savings. The average power per device declines as system
size grows because a continually higher portion of the
memory is deselected. Device power dissipation asymptotically approaches the standby power level. as shown in
Figure 2.
___
~
~'0n'
11:~~§2
...
o
60
-I11+8n'
80
DESELECT TIME (n5)
FIGURE 3. tACS VS. DESELECT TIME.
~
~
V- I--
\
V,L
- - j-"-'
ICC-
-- !r-
J
ice
\
)
ISB
The power switching characteristic of the 2141 requires
more careful decoupling than would be required of a
constant power device. It is recommended that a O.1IlF
ceramic capacitor be used on every other device. with a
221lF to 471lF bulk electrolytic decoupler every 32 devices.
The actual values to be used will depend on board layout.
trace widths and duty cycle. Power supply gridding is
recommended for PC board layout. A very satisfactory
grid can be developed on a two-layer board with vertical
traces on one side and horizontal traces on the other. as
shown in Figure 4.
\..
FIGURE 1. icc WAVEFORM.
ICC
a:
w
;:
..
0
w
U
;;
W
Cl
w
"
<
::;
w
...
2142 FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
1.2
1.2
----
1.1
..............
1.0
0.9
0.8
1. 1
-
1.0
~
~
i
0.7
0.6
0.8
0.5
4.75
5.00
5.25
6.50
80
1. 2
L--
1.1
1.
o.i
80
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
1.
.!l
fa
~
~
40
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
J.. . . . . V
O.9
20
TA (·C)
1.1
fa
N
o
---
Vee (V)
1.2
o~
O.9
~ t--..
!:!
:::;
i
0.8
0.7
0.54.50
~
0.9
....
~
O.8
i
o. 7
0:
o.7
o.6
-r-
o.6
O.5
100
200
300
400
600
• O. 5 0
800
20
80
80
CL (oF)
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
40
40
30
30
""
"\
0
0
""''"
IIoH
/
o
/
V--
/
oV
o
4
3
VOL (VI
(V)
3·98
4
inter
2147
4096 X 1 BIT STATIC RAM
2147-3
55
180
30
Max. Access Time (ns)
Max. Active Current (mA)
Max. Standby Current (mA)
• HMOS Technology
Static Memory • Completely
or Timing Strobe Required
2147
70
160
20
2147L
70
140
10
Power-Down
• Automatic
High Density l8-Pin Package
• Directly TTL Compatible - All Inputs
• and Output
Separate Data Input and Output
• Three-State
Output
•
No Clock
• Equal Access and Cycle Times
• Single +5V Supply
The Intel® 2147 is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using HMOS, a highperformance MOS technology. It uses a uniquely innovative design approach which provides the ease-of-use features
associated with non-clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
es controls the
power-down feature. In less than a cycle time after es goes high - deselecting the 2147 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as es remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are deselected.
The 2147 is placed in an 18-pin package configured with the industry standard pinout. It is directly TTL compatible in all
respects: inputs, output, and a single +5V supply. The data is read out nondestructively and has the same polarity as the
input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
A.
Vee
A,
As
A2
A,
A3
A.
A4
Ag
A.
A,.
Dour
A11
WE
GNO
LOG IC SYMBO L
A.
A,
A2
A3
A4
As
A6
A,
A.
Ag
BLOCK DIAGRAM
@
-Vee
®
_GND
Dour
MEMORY ARRAY
64 ROWS
64 COLUMNS
D,N
A,.
Cs
DIN WE CS
A11
@
D,N
PIN NAMES
A.-A11 ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT
DATA OUTPUT
DOUT
WE
CS
D,N
-=-----1
Vee POWER (+5V)
GND GROUND
TRUTH TABLE
Ics
WE
I~
X
L
H
MODE
NOT SELECTED
WRITE
READ
OUTPUT
POWER
HIGH Z
HIGH Z
STANDBY
ACTIVE
ACTIVE
Dour
WE
®
------------_ _ _- t R e '_ _ _ _ _--------l~
-.~
~- - - * -
*
~t=~~-H-t_AA~i-!x-x~}~_____________
DATA OUT
PREV'OUS DATA VALID
! __
DATA VALID
READ CYCLE NO.2
toe
~
f-
tLZ tACS
DATA OUT
HIGH IMPEDANCE
!--tHZ_
XX ~
3-101
DATA VALID
HIGH
IMPEDANCE
2147
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
2147-3
Symbol
Parameter
Min.
twe
Write Cycle Time
tew
Chip Selection to End of Write
tAW
Address Valid to End of Write
tAS
Address Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End of Write
tOH
Data Hold Time
twz
Write Enabled to Output in High Z
tow
Output Active from End of Write
2147,2147L
Max.
55
45
45
0
35
10
25
10
0
0
30
Min.
Max.
70
55
55
0
40
15
30
10
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
ns
WAVEFORMS
WRITE CYCLE #1 (WE CONTROLLED)
twe
ADDRESS~
~
'ew
OSI'
II
1\
'AW
'AS
'WP
I
IIII
i+--twR-
\\
'ow
'oH-
~
DATA IN
DATA IN VALID
r--________________=1
==:)I..-"""';;.;;;;..-.;~=-__{-~.-----twz
tow
HIGH I M P E D A N C E " j - - - - -
DATA OUT
DATA UNDEFINED
WRITE CYCLE #2 (CS CONTROLLED)
ADDRESS
--
'we
--'
-h
'ow
'AS
-
'AW
twP
-twR-
IIIIIIII
\\\\\\\\\\
tow
OATA IN
'OH -
DATA IN VALID
I--________________
=1
~).-....;~;.;;;;;.;;;;;.=------twz
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
Note: 1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
3·102
Test
Conditions
2147
TYPICAL D.C. AND A.C. CHARACTERISTICS
GRAPH 1
SUPPL Y CURRENT VS.
SUPPLY VOLTAGE
GRAPH 2
SUPPL Y CURRENT VS.
AMBIENT TEMPERATURE
GRAPH 3
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
100
40
40
r-- ~
ICC
30
30
TA"25"C
-
--
J
5.0V
Vee
80 f--TA " 25"C
_
'"
J:
Vee "5.0V -
10
60
!
.2 40
10
IS8
o
4.50
4.75
5.00
Vee IV)
5.50
5.25
20
GRAPH 4
NORMALIZED ACCESS TIME
VS. SUPPLY VOLTAGE
1.1
~
1.0
$
<
$
S
N
60
80
1.0
,---,---.,------r-----,
'AA
_
/
60
'"
!
..940
::;
'a:"
:;;
~
.8
20
.7
4.50
4.75
5.00
Vee IV)
5.25
o
5.50
--
/
1.6
1/
Jl
1.2
IS8
.8
.4
--
-i
/
20
"
2.0
3.0
Vee IV)
o
~~e: ~5~~1.0
I
2.0
3.0
20
/
.d: 10
..,$
/
TA " 70°C
V " 5.0V
eel
TA "25°C
lK!l CSPUll·UP RESISTOR TO Vee
1.0
/
/
..,~
-- r-- ~
/
/
/
4.0
GRAPH 9
ACCESS TIME CHANGE VS.
OUTPUT LOADING
GRAPH 8
ACCESS TIME CHANGE VS.
INPUT VOLTAGE
P\
--
4.0
V OUT (V)
GRAPH 7
TYPICAL POWER-ON CURRENT
VS. POWER SUPPLY VOLTAGE
2.0
Ipo
~
3.0
100
80
TA " 25"C -
2.0
Vour IV)
GRAPH 6
OUTPUT SINK CURRENT VS.
OUTPUT VOL TAGE
tACS
.9
o
GRAPH 5
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
1.1
--
'"
20
IS8
4.0
5.0
1.0
2.0
VIN IV)
3.0
4.0
V
/
TA "70°C
Vee
TN
I
100
200
300
C L IpF)
Note 1. The supply current curves shown in Graphs 1 and 2 are for the 2147.
The supply current curves for the 2147L and 2147-3 can be calculated by scaling proportionately.
3-103
V
/
400
500
2147
DEVICE DESCRIPTION
The 2147 is produced with HMOS, a new highperformance MOS technology which incorporates onchip substrate bias generation" combined with device
scaling to achieve high-performance. The speed-power
product of this process has been measured at 1pj,
approximately four times better than previous MOS
processes.
This process, combined with new design ideas, gives the
2147 its unique features. High speed, low power and easeof-use have been obtained in a single part. The low-power
feature is controlled with the Chip Select input, which is
not a clock and does not have to be cycled. Multiple read
or write operations are possible during a single select
period. Access times are equal to cycle times, resulting in
data rates of 14.3 MHz and 18 MHz forthe 2147 and 2147-3,
respectively. This is considerably l;Iigher performance
than for clocked static designs.
Whenever the 2147 is deselected, it aut0matically reduces
its power requirements to a fraction of the active power, as
shown in Figure 1. This is achieved by switching off the
power to unnecessary portions of the internal peripheral
circuitry. This feature adds up to significant system power
savings. The average power per device declines as system
size grows because a continually higher portion of the
memory is deselected. Device power dissipation asymptotically approaches the standby power level, as shown in
Figure 2.
There is no functional constraint on the amount of timet he
2147 is deselected. However, there is a relationship
between deselect time and Chip Select access time. With
no compensation, the automatic power switch would
cause an increase in Chip Select access time, since some
time is lost in repowering the device upon selection. A
feature of the 2147 design is its ability to compensate for
this loss. The amount of compensation is a function of
deselect time, as shown in Figure 3. For short deselect
times, Chip Select access time becomes slower than
address access time, since full compensation typically
requires 40ns. For longer deselect times, Chip Select
access time actually becomes faster than address access
ti me because the compensation more than offsets the time
lost in powering up. The spec accounts for this
characteristic by specifying two Chip Select access times,
tACS1 and tACS2.
II:=~----II[
a
~
~
~
~
100
DESELECT TIME (os)
FIGURE 3. tACS VS. DESELECT TIME.
The power switching characteristic of the 2147 requires
more careful decoupling than would be required of a
constant power device. It is recommended that a O.lI'F to
0.31'F ceramic capacitor be used on every other device,
with a 221'F to 471'F bulk electrolytic decoupler every 16
devices. The actual values to be used will depend on board
layout, trace widths and duty cycle. Power supply
gridding is recommended for PC board layout. A very
satisfactory grid can be developed on a tWO-layer board
with vertical traces on one side and horizontal traces on
the other, as shown in Figure 4.
FIGURE 1. icc WAVEFORM.
ICC
a:
w
s:
:t
w
u
~
0
w
<.!l
'a:w"
'"
~
FIGURE 4. PC LAYOUT.
>
I-
'"
i;;
ISB
4K 8K 16K
32K
64K
MEMORY SIZE IN WORDS
FIGURE 2. AVERAGE DEVICE DISSIPATION VS.
MEMORY SIZE.
Terminations are recommended on input signal lines to
the 2147 devices. In high speed systems, fast drivers can
cause significant reflections when driving the high
impedance inputs of the 2147. Terminations may be
required to match the impedance of the line to the driver.
The type of termination used. depends on designer
preference and may be parallel resistive or resistivecapacitive. The latter reduces terminator power dissipation.
3·104
2147H
HIGH SPEED 4096 x 1 BIT STATIC RAM
• HMOS II Technology
• 35-45ns Maximum Access Time
• Fully Compatible with Industry
Standard 2147
• 180mA Maximum Icc
• Automatic Power-Down
• High Density 18-Pln Package
• 30mA Maximum ISB
• Completely Static Memory or Timing Strobe Required
• Directly TTL Compatible - All Inputs
and Output
No Clock
• Separate Data Input and Output
• Equal Access and Cycle Times
• Three-State Output
• Single +5V Supply
The Intel® 2147H is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using HMOS II, Intel's new
high-performance MOS technology. It uses a uniquely innovative design approach which provides the ease-of-use
features associated with non-clocked static memories and the reduced standby power dissipation associated with clocked
static memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high - deselecting the 2147H - the part
automatically reduces its power requirements and remains in this low power standby mode as long as CS remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are
deselected.
The 2147H is placed in an 18-pin package configured with the industry standard pinout. It is directly TTL compatible in all
respects: inputs, output, and a single +5V supply. The data is read out nondestructively and has the same polarity as the
input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
A.
vee
Al
A6
A2
A,
A3
As
A.
A.
As
A,.
Dour
All
LOGIC SYMBOL
BLOCK DIAGRAM
A.
A,
A2
A3
A.
As
As
@
-Vee
~GND
Dour
ROW
A,
As
A.
WE
D,N
A,.
GNII
Cs
DIN ~E
SELECT
MEMORY ARRAY
64 ROWS
64 COLUMNS
A"
cs
2147H
@
D,N
PIN NAMES
AD-A"
WE
CS
D,N
Dour
ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT
DATA OUTPUT
-=------1
Vee POWER I+5V)
GND
GROUND
TRUTH TABLE
WE
X
L
H
MODE
NOT SELECTED
WRITE
READ
3-105
Dour
inter
2148
1024 X 4 BIT STATIC RAM
Max. Access Time (ns)
Max. Active Current (mA)
Max. Standby Current (mA)
• HMOS Technology
Static Memory
• Completely
- No Clock or Timing Strobe
60
150
30
• Automatic Power· Down
• High Density 18·Pin Package
TTL Compatible
• Directly
- All Inputs and Outputs
• Common Data Input and Output
• Three·State Output
Required
• Equal Access and Cycle Times
• Single +5V Supply
The Intel® 2148 is a 4096·bit static Random Access Memory organized as 1024 words by 4 bits using HMOS, a high·
performance MOS technology. It uses a uniquely innovative design approach which provides the ease·of·use features
associated with non·clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
CE controls the power-down feature. In less than a cycle time after CE goes high - deselecting the 2148 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as CE remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are
deselected.
The 2148 is placed in an 18·pin package configured with the industry standard 1K x 4 pinout. It is directly TTL compatible
In all respects: inputs, outputs, and a single +5V supply. The data is read out nondestructively and has the same
polarity as the input data. Common input and output pins are provided.
PIN CONFIGURATION
A.
Vee
As
A7
A4
AS
A3
A,
BLOCK DIAGRAM
LOGIC SYMBOL
~vee
AO
A1
~GND
1/01
A,
A3
ROW
1/02
SELECT
A4
AO
1101
A1
1102
A,
1103
IT
1104
GND
WE
As
AS
1103
A.
A,
1/04
AS
1101
1/03
PIN NAMES
Ag-Ag
CE
1/01-1104
Vee
GND
54 ROWS
64 COLUMNS
@
@
o=
A7
1102
WE
MEMORY ARRAY
ADDRESS INPUTS
WRITE ENABLE
CHIP ENABLE
DATA INPUT/OUTPUT
POWER (+SV)
GROUND
PIN NUMBERS
@
COLUMN 110 CIRCUITS
@
@
1/04
WE~1~=t-'--------------------------------~
TRUTH TABLE
CE
WE
MODE
I/O
POWER
H
L
L
X
L
H
NOT ENABLED
WRITE
READ
HIGH·Z
HIGH·Z
STANDBY
ACTIVE
ACTIVE
DOUT
3·106
inter
3101, 3101A
16 x 4 BIT HIGH SPEED RAM
• Fast Access Time - 35 nsec max
over 0·75°C Temperature Range
(3101A)
• OR· Tie Capability - Open Collector
Outputs
• Fully Decoded - on Chip Address
Decode and Buffer
• Simple Memory Expansion through
Chip Select Input - 17 nsec max over
0·75°C Temperature Range (3101A)
• Minimum Line Reflection - Low
Voltage Diode Input Clamp
• DTL and TTL Compatible - Low Input
Load Current: 0.25 mA max
• Ceramic and Plastic Package Dual In·JLine Configuration
16 Pin
The Intel 3101 and 3101A are high speed fully decoded 64 bit random access memories, organized 16 words
by 4 bits. Their high speed makes them ideal in scratch pad applications. An unselected chip will not generate
noise at its output during writing of a selected chip. The output is held high on an unselected chip regardless
of the state of the read/write signal.
The use of Schottky barrier diode clamped transistors to obtain fast switching speeds results in higher performance than equivalent devices with gold diffusion processes.
The Intel 3101 and 3101A are packaged in either hermetically sealed 16 pin ceramic packages, or in low cost
silicone packages, and their performance is specified over a temperature range from O°C to 7SoC.
The storage cells are addressed through an on chip 1 of 16 binary decoder using four input address leads.
A separate Chip Select lead allows easy selection of an individual package when outputs are OR-tied.
In addition to the address leads and the Chip Select lead, there is a write input which allows data presented at
the data leads to be entered at the addressed storage cells.
PIN CONFIGURATION
ADDRESS INPUT Ao
A, ADDRESS INPUT
WE
Az ADDRESS INPUT
DATA INPUT D,
A3 ADDRESS INPUT
DATA OUTPUT
0,
DATA INPUT 02
DATA OUTPUT
'02
GN.
.,
.. CD
.,., .,
., @
Vee
CHIPSELECT CS
WRITE ENABLE
04 DATA INPUT
04
BLOCK DIAGRAM
LOGIC SYMBOL
.,
.,., .,
DATA OUTPUT
03 DATA INPUT
'03 ImTA OUTPUT
., ®
.. @
@Vcc
@GNO
.. ----.,...,....,....,,...,...,-rl
Q-PmNumbarl
TRUTH TABLE
PIN NAMES
I 0,-04
DATA INPUTS
I AO-A3
ADDRESS INPUTS
I WE
WRITE ENABLE
CHIP
II
CS
CHIP SELECT INPUT
II
II
0,-04
Vee
DATA OUTPUTS
POWER (+5V)
3-107
SELECT
WRITE
ENABLE
OPERATION
OUTPUT
LOW
LOW
LOW
HIGH
WRITE
READ
HIGH
COMPLEMENT OF
WRITTEN DATA
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
3101, 3101A
Absolute Maximum Ratings *
'COMMENT:
Temperature Under Bias:
Ceramic
Plastic
-65°C to +125°C
-65°C to +75°C
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex·
tended periods may affect device reliability.
-65°C to +160o C
Storage Temperature
All Output or Supply Voltages
-0.5 to +7 Volts
All Input Voltages
-1.0 to +5.5 Volts
Output Currents
100 mA
D.C. Characteristics
SYMBOL
= O°C
TA
= 5.0V
±5%
MIN.
to +75°C, Vee
MAX.
UNIT
IFA
ADDRESS INPUT LOAD CURRENT
-0.25
mA
Vee
~5.25V.
lFO
DATA INPUT LOAD CURRENT
-0.25
mA
Vee
~5.25V.
VD ~0.45V
I FW
WRITE INPUT LOAD CURRENT
-0.25
mA
Vee
~5.25V,
Vw ~0.45V
IFS
CHIP SELECT INPUT LOAD CUR RENT
mA
Vee ~5.25V, Vs =0.45V
IRA
ADDRESS INPUT LEAKAGE CURRENT
10
>J A
Vee
~5.25V,
VA ~5_25V
IRD
DATA INPUT LEAKAGE CURRENT
10
~A
Vee
~5.25V,
VD ~5.25V
I RW
WRITE INPUT LEAKAGE CURRENT
10
>J A
Vee
~5.25V.
Vw ~5.25V
IRS
CHIP SELECT INPUT LEAKAGE CURRENT
10
fJA
Vee
~5.25V, Vs~5.25V
V eA
ADDRESS INPUT CLAMP VOLTAGE
-1.0
V
Vee
~4.75V,
VeD
DATA INPUT CLAMP VOLTAGE
-1.0
V
Vee
~4.75V. ID~-5.0
mA
Vew
WRITE INPUT CLAMP VOLTAGE
-1.0
V
Vee =4.75V,
Iw~-5.0
mA
Ves
CHIP SELECT INPUT CLAMP VOLTAGE
-1.0
V
Vee =4.75V, Is ~-5.0 mA
VOL
OUTPUT "LOW" VOLTAGE
PARAMETER
_ . - r-------
-0.25
0.45
TEST CONDITIONS
V A ~0.45V
IA =-5.0 mA
Vee =4.75V, 10L ~ 15 mA
V
Memory Stores "Low"
leEX
OUTPUT LEAKAGE CURRENT
100
fJA
lee
POWER SUPPLY CURRENT
105
mA
V ,L
INPUT "LOW" VOLTAGE
V ,H
INPUT "HIGH" VOLTAGE
Vee ~5.25V, VeEX ~5.25V
Vs~2.5V
0.85
2.0
Vee =5.25V, V A ~Vs
V
Vee
~5.0V
V
Vee
~5.0V
~VD ~OV
Typical Characteristics
OUTPUT CURRENT
VS. OUTPUT "LOW" VOLTAGE
40
III
Vee:: 5.0V
30
75°C ........ ,
20
Jh
VII-
25"C_
10
25'C"-.1
-25
/II
'IL
<'
-50
1
75'C_
~
INPUT THRESHOLD VOLTAGE
VS. AMBIENT TEMPERATURE
2.5
II
w
~ 2.0
I
o
>.
;- -75
I
~
~-100
I
::>
-DoC
'5" 1.5
--- -
~
"
t-- 125
a:
,..J:
~
!::-150
1///
~ 1.0
-200
0.4
0.6
OUTPUT VOLTAGE (V)
0.8
---
r---
~
-175
IV;
I
vee'" s.ov
~ ~ f"e """"olc
"-
1,./.,'(/
0.2
INPUT CURRENT
VS. INPUT VOLTAGE
0.5
1.0
INPUT VOLTAGE (V)
3·108
2.0
3.0
0
25
50
AMBIENT TEMPERATURE (OC)
75
3101,3101A
Switching Characteristics
Conditions of Test:
15 rnA T." lood
Input Pulse amplitudes:
~IT~,
2.5V
"'Wo.,
I nput Pulse rise and fall times of
5 nanoseconds between 1 volt
and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 15mA and 30 pF
WRITE CYCLE
READ CYCLE
Address to Output Delay
~r------x
-!!'I'
~
---.--
CHIP SELECT INPUT
-'----.
:S,18ns
I-'Vl ''}~
CHIP SELECT INPUT
-+-------- t OW -----+-
--
---~
Data may'
e I , __________ _
_+C_h_an_9_
Chip Select to Output Delay
=x---------~
WRITE INPUT
..-~18ns
0 1, O 2, 0 3 , 0 4
(Selected Chips) ~
CHIP SELECT INPUT
,,
,,
_I
------..1
tSR - (See Note 1)
*Outputs of unselected chips remam high dUring write cycle.
NOTE l'
tSR is associated with a read cycle following a write cycle and does not affect the access time.
A.C. Characteristics
TA
= O°C to +75°C, VCC = 5.0V ±5%
READ CYCLE
SYMBOL
tS+' t5_
PARAMETER
Chip Select to Output
WRITE CYCLE
3101A
3101
LIMITS (n.1
LIMITS (nsl
MIN. MAX.
MIN. MAX.
5
17
5
SYMBOL
42
'SR
Delay
tA_' t A
+
10
35
10
60
MIN. MAX.
MIN. MAX.
Sense Amplifier
50
35
twp
Write Pulse Width
25
40
Data-Write Overlap
25
40
0
5
Time
TA
= 25°C
INPUT CAPACITANCE
(All Plnsl
COUT
3101
LIMITS (nsl
tow
'WA
CIN
3101A
LIMITS (nsl
Recovery Time
Address to Output
Delay
CAPACITANCE (2)
TEST
OUTPUT CAPACITANCE
Write Recovery Time
10 pF
maximum
NOTE 2:
12 pF
maximum
3-109
This parameter is periodically sampled and is not 100%
tested. Condition of measurement is f = 1 MHz, Vbias
= 2V. VCC = OV. and TA = 25°C.
3101,3101A
Typical A.C. Characteristics
ADDRESS TO OUTPUT DELAY
VS.
AMBIENT TEMPERATURE
CHIP SE LECT TO OUTPUT 1)£ LA Y
VS.
AMBIENT TEMPERATURE
40
40
.l.ov
.l.ov ±
Vee
± 5%
C l '" 30pF
Vee
C l "'30pF
30
30
,.
_.
~
o
.-
'A'
r-
'A-
>-
~
~
o
20
20
i'!
~
a:
is
'"
5%
's10
10
- - - - ----'s.
~----
o
o
25
o
15
50
o
ADDRESS & CHIP SELECT TO OUTPUT DELAY
VS.
LOAD CAPACITANCE
45
Vee '"
5.~V
.±5%
D.C. LOAD'" 15 rnA
TA '" 25°C
tA:"""-
35
15
50
........- ....-
WRITE PULSE WIDTH & SENSE
AMPLIFIER RECOVERY nM£
VS. AMBIENT TEMPERATURE
40
....- ....-
I
vee "5.0V
C l =30pF
30
....--{/'
'SR
...- ....---~ ~
---
25
I
,
I
-
15
I / /'s .......... --r-~
;..-
's-
//
//
5
26
AMBIENT TEMPERATURE (tlCI
AMBIENT TEMPERATURE (OC)
o
50
100
....-
20
-....----
I
150
.....-
-
w,
10
o
200
o
25
50
AMBIENT TEMPERATURE I 'C)
LOAD CAPACITANCE (pFJ
3·110
15
inter
5101 FAMILY
256 x 4 BIT STATIC CMOS RAM
PIN
Typ. Current @ 2V Typ. Current @ 5V
5101L
5101L-1
5101L-3
(j,lA)
(j,lA)
Max Access
(ns)
0.14
0.14
0.70
0.2
0.2
1.0
650
450
650
• Single +5V Power Supply
• Directly TTL Compatible:
All Inputs and Outputs
• Three-State Output
• Ideal for Battery
Operation (5101 L)
The Intel® 5101 is an ultra-low power 1024-bit (256 words X 4 bits) static RAM fabricated with an advanced ion-implanted
silicon gate CMOS technology. The device has two chip enable inputs. Minimum standby current is drawn by this device when
CE2 is at a low level. When deselected the 5101 draws from the single 5-volt supply only 10 microamps. This device is ideally
suited for low power applications where battery operation or battery backup for non-volatility are required.
The 5101 uses fully DC stable (static) circuitry; it is not necessary to pulse chip select for each address transition. The data is read
out non-destructively and has the same polarity as the input data. All inputs and outputs are directly TTL compatible. The 5101
has separate data input and data output terminals. An output disable function is provided so that the data inputs and outputs may
be wire OR-ed for use in common data I/O systems.
The 5101 L has the additional feature of guaranteed data retention at a power supply voltage as low as 2.0 volts.
A pin compatible N-channel static RAM, the Intel® 2101A, is also available for low cost applications where a 256 X 4 organization is needed.
The Intel ion-implanted, silicon gate, Complementary MOS (CMOS) process allows the design and production of ultra-low power,
high performance memories.
BLOCK DIAGRAM
ROW
DECODERS
CELL ARRAY
32 ROWS
32 COLUMNS
......----L_--"~DO,
o
3-111
='
PIN NUMBERS
5101 FAMILY
Absolute Maximum Ratings *
'COMMENT:
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Under Bias . . . . . _lO°C to ao°c
Storage Temperature . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground .... -0.3V to Vcc +0.3V
Maximum Power Supply Voltage . . . . . . . . , +7.0V
Power Dissipation . . . . . . . . . . . . . . . . . . , 1 Watt
D. C. and Operating Characteristics
TA = O°C to 70°C, Vcc = 5V ±5% unless otherwise specified.
Symbol
Il2!2]
Parameter
5101 Land 5101 L-1
5101L-3
Limits
Limits
Min. Typ.!l] Max. Min. Typ.ll] Max. Units
Input Current
5
IlLOI!2] Output Leakage Current
1
Test Conditions
nA
5
1
fJ.A
CE1=2.2V, VOUT=
Oto VCC
ICCl
Operating Current
9
22
9
22
mA
VIN=VCC, Except
CEl .,:;; 0.65V,
Outputs Open
ICC2
Operating Current
13
27
13
27
mA
VIN=2.2V, Except
CEl ":;;0.65V,
Outputs Open
200
fJ.A
CE2":;;0.2V, TA=
70'C
IC Cl!2] Standby Current
10
Vil
Input Low Voltage
-0.3
0.65 -0.3
0.65
V
VIH
Input High Voltage
2.2
VCC
2.2
VCC
V
VOL
Output Low Voltage
0.4
V
IOl =2.0 mA
VOH
Output High Voltage
V
IOH= -1.0 mA
0.4
2.4
2.4
Low Vcc Data Retention Characteristics (For 5101L, 5101L-1 and 5101L-3) TA = O'Cto 70'C
Symbol
Parameter
Min.
Typ.!l]
VDR
VCC for Data Retention
ICCDR1
5101 L or 5101 L·l Data Retention
Current
0.14
5101 L-3 Data Retention Current
0.70
ICCDR2
tCDR
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
Max.
2.0
Units
Test Conditions
V
10
fJ.A
CE2":;;0.2V
200
fJ.A
0
ns
tRC[3]
ns
NOTES:
1. Typical values are TA = 25'C and nominal supply voltage.
2. Current through all inputs and outputs included in ICCl measurement.
3. tRC = Read Cycle Time.
3-112
VDR=2.0V,
TA=70'C
VDR=2.0V,
TA=70'C
5101 FAMILY
Low VCC Data Retention Waveform
Typical ICCDR Vs. Temperature
I
1.00
SUPPLY
CD
®
VOLTAGE (Vee)
I
r--
4.7SV
VO.
L/
® V,"
CHIP ENABLE ICE21
OV -
@)
@)
-
V
Vee = 2V
eE2 = O.2V
VIN = 2V
0.2V
0.10
-"""---------------------,,- -
0.0
,V
o
V
,/
/
10
20
30
40
50
60
70
TEMPERATURE lOCI
A.C. Characteristics
TA; o°c to 70°C, Vee; 5V ±5%, unless otherwise specified.
READ CYCLE
Symbol
Parameter
5101 L·1
Limits (ns)
Min.
Max.
5101 Land
5101 L·3
Limits (ns)
Min.
Max.
450
650
tRe
Read Cycle
tA
Access Time
450
650
teol
Chip Enable (CE 1) to Output
400
600
tC02
Chip Enable (CE 2) to Output
500
700
too
Output Disable to Output
250
tOF
Data Output to High Z State
0
tOHl
Previous Read Data Valid with
Respect to Address Change
0
0
tOH2
Previous Read Data Valid with
Respect to Chip Enable
0
0
450
650
130
350
0
150
WRITE CYCLE
twe
Write Cycle
tAW
Write Delay
130
150
tewl
Chip Enable (CE 1) to Write
350
550
tew2
Chip Enable (CE 2) to Write
350
550
tow
Data Setup
250
400
tOH
Data Hold
50
100
twp
Write Pulse
250
400
tWR
Wr ite Recovery
50
50
tos
Output Disable Setup
130
150
Ca paci°ta nce[2]T A
A. C. CONDITIONS OF TEST
Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Measurement Reference Level:
Output Load:
1 TTL Gate and CL
20 nsec
1.5 Volt
=
Symbol
C'N
100pF
<::OUT
NOTES:
~ 25°C. f
= 1 MHz
+0.65 Volt to 2.2 Volt
1. Typical values are for T A ~ 25" e and nominal supply voltage.
2. This parameter is periodically sampled and is not 100% tested.
3·113
Limits (pF)
Typ.
Max.
Test
Input Capacitance
(All Input Pins) V,N
~
OV
Output Capacitance VOUT
~
OV
4
8
8
12
5101 FAMILY
Waveforms
READ CYCLE
WRITE CYCLE
I.--------------'we--------------~
1--+-------- 'eW2 -----------1
DATA IN
STABLE
1________ 'we ______--1- t WR - - RW
NOTES:
1. OD may be tied low for separate I/O operation.
2. During the write cycle, OD is "high" for common I/O and
"don't care" for separate I/O operation.
3-114
Read Only Memory
4
MOS EPROM AND ROM FAMILY
Type
.'"
.
0
8
~~2
fig:
,,",0
No.
01
Bits
No.
01
Organization
16384
2048 x 8
Maximum
Operating
Maximum
Power
Temperature
Access
Range
(OC)
Pins
Output l1 ]
(ns)
Dissipation
(mW)
24
T.S.
450
630
Power
Supply
(V)
Page No.
5V± 10%
4·12
--
2332A
32768
4096 x 8
24
T.S.
TBD
TBD
2364A
65536
8192 x 8
28
T.S.
TBD
TBD
o to 70
o to 70
o to 70
2608
8192
1024 x 8
24
T.S.
450
800
o to 70
1702A
2048
256 x 8
24
T.S.
1 ~s
885
o to 70
1702A·2
2048
256 x 8
24
T.S.
650
959
o to 70
1702A·6
2048
256 x 8
24
T.S.
885
o to 70
M1702A
2048
256 x B
24
T.S.
850
960
- 55 to 100
1702AL
2048
256 x B
24
T.S.
1 ~s
221
o to 70
5V± 5%
-9V± 5%
2048
256 x 8
24
T.S.
650
221
o to 70
-9V±5%
2704
4096
512 x 8
24
T.S.
450
800
o to 70
2708
8192
1024 x 8
24
T.S.
450
800
o to 70
5V±5%
12V±5%
-5V±5%
2708L
8192
1024 x 8
24
T.S.
450
425
010 70
5V±5%
12V±5%
-5V±5%
2708·1
8192
1024 x 8
24
T.S.
350
800
o to 70
5V±5%
12V±5%
-5V±5%
12708
8192
1024 x 8
24
T.S.
450
800
- 40 to 85
2316E
1702AL·2
1.5
~s
5V±10%
4-15
5V± 10%
4-16
--
5V±5%
12V±5%
-5V± 5%
4-17
5V±5%
-9V± 5%
5V±5%
-9V±5%
5V±5%
4·5
-9V±5%
5V± 10%
- 9V± 10%
5V±5%
14·5
4·9
5V±5%
'~"
ill
8
'"
12V±5%
-5V±5%
12V±5%
4-20
4·21
13-4
-5V±5%
M2708
8192
1024 x 8
24
T.S.
450
750
-55tol00
12V±10%
-5V±10%
2716
2716·1
2716-2
16384
16384
16384
2048 x 8
2048 x 8
2048 x 8
24
24
24
T.S.
T.S.
T.S.
450
350
390
525/132 12J
550/138 12J
5251132 12J
o to 70
o to 70
o to 70
5V±5%
5V± 10%
12716
16384
2048 x 8
24
T.S.
450
603/165 12J
-40 to 85
5V±5%
13·5
M2716
16384
2048 x 8
24
T.S.
450
603/165 12J
-55tol00
5V±10%
14-28
2732
32768
4096 x 8
T.S.
450
788/158 12J
4-28
525/132 12J
o to 70
o to 70
5V±5%
450
5V±5%
4-31
24
-----""-
2758
8192
1024 x 8
24
---~
T.S.
Notes: 1. T.S. is a three state output.
2. Static standby mode feature.
14·22
4-23
5V±5%
ROM and PROM Programming Instructions 4-48
Disk L 1, file 819·1
4-2
BIPOLAR PROM FAMILY
Type
3604A
3604A·2
3604AL
3624A
3624A-2
M3604A
M3624A
3605A
3605A-1
3625A
3625A-l
M3625A
3628
3628-4
3636
3636-1
M3636
Notes:
No.
of
Bits
Organization
No.
of
Pins
4096
4096
4096
4096
4096
512x8
512x8
512x8
512x8
512x8
24
24
24
24
24
O.C.
4096
4096
512x8
512x8
O.C.
4096
4096
4096
4096
1024x4
1024x4
1024x4
1024x4
1024x4
T.S.
4096
8192
8192
1024x8
1024x8
24
24
18
18
18
18
18
24
24
16384
16384
16384
2048x8
2048x8
2048x8
24
24
24
Output(1)
Maximum
Access
(ns)
70
60
90
70
60
O.C.
O.C.
T.S.
T.S.
90
90
T.S.
60
50
60
50
60
O.C.
O.C.
T.S.
T.S.
T.S.
T.S.
T.S.
Maximum
Power
Dissipation
(mW)
Operating
Temperature
Range
(0C)
Power
Supply
Page
No.
895
895
o to 75
o to 75
o to 75
o to 75
o to 75
5V±5%
5V±5%
5V±5%
5V±5%
5V±5%
4·36
-55t0125
- 55 to 125
o to 75
o to 75
o to 75
o to 75
o to 75
5V± 10%
5V± 10%
14-33
5V±5%
5V±5%
5V±5%
5V±5%
4-39
685/135(2)
895
895
1045
1045
735
735
735
735
998
80
100
998
998
80
65
80
998
998
998
T.S.
T.S.
1. D.C. and T.S. are open collector and three-state
output respectively.
2. The 3604Al has a low power dissipation feature.
o to 75
o to 75
o to 75
o to 75
- 50 to 125
5V±5%
5V±5%
5V±5%
5V± 10%
5V± 10%
5V±5%
ROM and PROM Programming Instructions
4-3
14-35
4-42
4-45
14-38
BIPOLAR PROM CROSS REFERENCE
Part
Prefix and
Number Manufacturer
Organization
Intel Part Number
For New
Replacement
Designs
Direct
5340-1
5341-1
MMI
MMI
512 x 8
512 x 8
M3624A
M3624A
5604C
5605C
5624C
5625C
IM-Intersil
IM-Intersil
IM-Intersil
IM-Intersil
512
512
512
512
x
x
x
x
4
8
4
8
3602A
3604A
3622A
3624A
6305-1
6306-1
6340-1
6341-1
6352-1
6353-1
6380-1
6381-1
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
512
512
512
512
1024
1024
1024
1024
x
x
x
x
x
x
x
x
4
4
8
8
4
4
8
8
74S472
74S473
74S474
74S475
74S570
74S571
TI
TI
TI
TI
512
512
512
512
512
512
x
x
x
x
x
x
8
8
8
8
4
4
7620-5
7621-5
7640-2
7640-5
7641-2
7641-5
7642-5
7643-5
7644-5
7680-5
7681-5
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
512
512
512
512
512
512
1024
1024
1024
1024
1024
x
x
x
x
x
x
x
x
x
x
x
4
4
8
8
8
8
4
4
4
8
8
82S115
82S115
82S130
82S131
82S140
82S141
825136
82S137
825137
82S180
82S181
825182
825183
82S191
825191
N-Signetics
S-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
S-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
N-Signetics
S-Signetics
512
512
512
512
512
512
1024
1024
1024
1024
1024
1024
1024
2048
2048
x8
x 8
x 4
x 4
x8
x 8
x4
x4
x4
x 8
x 8
x 8
x8
x 8
x 8
87S295
87S296
National
National
93436C
93438C
93438M
93446C
93448C
93448M
93452C
93453C
93453M
Fairchild
Fairchild
Fairchild
National
National
HM~Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
HM-Harris
Fairchild
Fairchild
Fairchild
Fairchild
Fairchild
Fairchild
512 x 8
512 x 8
512
512
512
512
512
512
1024
1024
1024
x4
x 8
x 8
x4
x8
x8
x4
x4
x4
4-4
3604A
3625A
3604A
3624A
3625A
3625A
3628
3628
3624A
3604A
3624A
3604A
3604A
3625A
3604A
M3604A
3604A
M3624A
3624A
3605A
3625A
3625A
3628
3628
3624A
M3624A
3604A
3625A
3604A-2
3624A-2
3625A-1
3625A-1
M3625A
3628
3628
3628-1
3636
M3636
3604A
3624A
3604A
3604A-2
M3604A
3625A-1
3624A-2
M3624A
3625A-1
3625A-1
M3625A
inter
1702A
2K (256 x 8) UV ERASABLE PROM
1702A-2
1702A
1702A-6
0.65 us Max.
1.0 us Max.
1.5 us Max.
• Fast Access Time: Max. 650 ns
(1702A-2)
• Fast Programming: 2 Minutes
for all 2048 Bits
• All 2048 Bits Guaranteed*
Programmable: 100% Factory
Tested
• Static MOS: No Clocks Required
• Inputs and Outputs DTL and
TTL Compatible
• Three-State Output: OR-tie
Capability
The 1702A is a 256 word by 8-bit electrically programmable ROM ideally suited for uses where fast turnaround and pattern experimentation are important. The 1702A undergoes complete programming and functional testing prior to shipment, thus insuring 100% programmability.
Initially all 2048 bits of the 1702A are in the "0" state (output low). Information is introduced by selectively
programming "1"s (output high) in the proper bit location. The 1702A is packaged in a 24 pin dual in-line
package with a transparent lid. The transparent lid allows the user to expose the 1702A to ultraviolet light to
erase the bit pattern. A new pattern can then be written into the device.
The circuitry of the 1702A is completely static. No clocks are required. Access times from 650ns to 1.5~s are
available. A 1702AL family is available (see 1702AL data sheets for specifications) for those systems requiring
lower power dissipation than the 1702A.
The 1702A is fabricated with silicon gate technology. This low threshold technology allows the design and production of higher performance MaS circuits and provides a higher functional density on a monolithic chip than
conventional MaS technologies.
*Intel's liability shall be limited to replacing any unit which fails to program as desired.
PIN CONFIGURATION
PIN NAMES
BLOCK DIAGRAM
DATA OUT 1
AO-A7
3
22
Vcr
"DATA OUT 1
AD
4 {LSBI
21
A3
-DATA OUT 2
5
20
A4
"DATA OUl 3
6
AS
"DATA OUT 4
7
18
·DATA OUT 5
8
17
A7
"OATA OUT 6
9
16
VGG
-DATA OUT 7
10
15
Vetl
'"DATA OUT B
"
Vee
12
(MSB)
14
CS
13
PROGRAM
CS
°OUTl-OOUTB
DATA OUT 8
Address Inputs
Chip Select Input
Data Outputs
"THIS PIN IS THE DATA INPUT LEAD DURING PROGRAMMING
NOTE: In the read mode a logic 1 at the address inputs
and data outputs is a high and logic 0 is a low.
U.S. Patent No. 3660819
4-5
1702A
PIN CONNECTIONS
The external lead connections to the 1702A differ, depending on whether the device is being programmed or used in read mode
(see following table). In the programming mode, the data inputs 1-8 are pins 4-11 respectively. The programming voltages and tim-
ing are shown in the Data Catalog ROM and PROM Programming Instructions section.
~
MODE
12
(Vee)
13
(Program)
14
(CS)
15
(Vaa)
22
16
(VGG)
(Vee!
23
(Vee)
24
(Voo)
Read
Vee
Vee
GND
Vee
VGG
Vee
Vee
Voo
Programming
GND
Program Pulse
GND
VBB
Pulsed VGG
GND
GND
Pulsed V DO
Absolute Maximum Ratings*
'COMMENT
Ambient Temperature Under Bias . . . . . . . -10°C to +80°C
Storage Temperature
. . . . . . . . . . . . . -65°C to + 125 °c
Soldering Temperature of Leads (10 sec) . . . . . . . . +300 o C
. . . . . . . . . . . . . . . . . . . . . . . 2 Watts
Power Dissipation
Read Operation: Input Voltages and Supply
Stresses above those listed under "Absolute Maximum Rat·
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for ex·
tended periods may affect device reliability.
Voltages with respect to Vee . . . . . . . . . . +0.5V to -20V
Program Operation: I nput Voltages and Supply
Voltages with respect to Vee . . . . . . . . . . . . . . . . -48V
D.C. and Operating Characteristics
TA
READ OPERATION
unless otherwise noted.
Symbol
Test
= oOe to 70°C, Vee = +5V ±5%, Voo = -9V ±5%, VGG = -9V ±5%,
17U2A, 17U2A-6 Limits
Typ.[l]
Max.
Min.
Min.
17U2A-2 Limits
Typ.!l]
Max.
Unit
Conditions
= O.OV
III
Address and Chip Select
Input Load Current
1
1
pA
VIN
ILO
Output Leakage Current
1
1
pA
VOUT = O.OV, CS = VIH2
1001 [1]
Power Supply Current
35
50
40
60
rnA
CS = VIH2, IOl = O.OmA,
TA = 25°C, Continuous
1002
Power Supply Current
32
46
37
55
mA
CS = O.OV, IOl = O.OmA,
T A = 25°C, Continuous
1003
Power Supply Current
38
60
43
65
mA
CS =VIH2,lol = O.OmA,
T A = O°C, Continuous
ICFl
Output Clamp Current
8
14
7
13
mA
VOUT= -1.0V,
T A = O°C, Continuous
leF2
Output Clamp Current
7
13
6
12
mA
VO UT = -1.0V,
T A = 25°C, Continuous
IGG
Gate Supply Current
1
pA
VILl
Input Low Voltage
for TT L I nlerface
-1
0.65
-1
0.65
V
VIl2
Input Low Voltage
for MOS Interface
Voo
Vce-6
Voo
Vec-6
V
VIHl
Addr. Input High Voltage
Vee-2
Vee+0.3
Vee-2
Vee+ O•3
V
VIH2
ChipSel.lnput High Volt.
Vee-2
Vee+0. 3
Vee-1.5
Vee+0.3
V
1
IOl
Output Sink Current
1.6
IOH
Output Source Current
-2.0
Val
Output Low Voltage
VOH
Output High Voltage
4
-3
3.5
1.6
4
-2.0
-3
0.45
3.5
4.5
Note 1: Typical valuesareat nominal voltages and TA
= 25°C.
4-6
4.5
0.45
mA
VOUT= 0.45V
mA
VOUT= O.OV
V
IOl = 1.6mA
V
IOH = -200pA
1702A
A.C. Characteristics
T A = r:J' e to + 70 o e, Vee = +5V ±5%, VDD = -9V ±5%, VGG = -9V ±5% unless otherwise noted
Symbol
1702A
Limits
Min.
Max.
Test
1702A·2
Limits
Min.
Max.
1702A·6
Limits
Min.
Max.
Unit
MHz
Freq.
Repetition Rate
1
1.6
0.66
tOH
Previous Read Data Valid
0.1
0.1
0.1
IlS
tAee
Address to Output Delay
1
0.65
1.5
Ils
tes
Chip Select Delay
0.1
0.3
0.6
IlS
teo
Output Delay From CS
0.9
0.35
0.9
Ils
taD
Output Deselect
0.3
0.3
0.3
IlS
Capacitance"
SYMBOL
TA = 25°e
TEST
TYPICAL
MAXIMUM
UNIT
CIN
Input Capacitance
8
15
pF
COUT
Output Capacitance
10
15
pF
CONDITIONS
V,,' V"
CS = Vee
VOUT
VGG
} All
unused pins
= Vee
= Vee
are at A.C.
ground
"This parameter is periodically sampled and is not 100% tested.
Switching Characteristics
Conditions of Test:
Input pulse amplitudes: to 4V; t R , tF <50 ns
Output load is 1 TTL gate; measurements made
at output of TTL gate (tPD';;15 ns), CL = 15pF
°
A) READ OPERATION
~-CYCLE
TIME
B) DESELECTION OF DATA OUTPUT IN OR·TIE
OPERATION
l/FREO ______
V
V'H -:\;10%
.JA'--___
ADDRES"J'\..:.9::.;0%:..-._ _ _ _ _ _ _
V 1L
1-
os
V'H
V1L
I
Ti
--I tes
I
i'OH-!
I
I
I
DATAOH
OUTV
VOL
l
1
, ,
-
I
'o'.A:T'A OUT
INV,,?-LlD
j.I
I
C.'I'..·
r + - - - - t A C C - - - - l ·[
4·7
1702A
Typical Characteristics
OUTPUT CURRENT VS.
VDD SUPPLY VOLTAGE
OUTPUT CURRENT VS.
TEMPERATURE
"ill
~
TA
= 2SoC
i3
"z
"
Vee
-9
.g
0
w
"
!j
-3
.,iil
I
5
I
%
1
0
0
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
20
30
40
50
60
70
80
90
~
Vee = '5V
Voo= -9V
i3
'-i.
10
j AMIBIENT TEMPERATURE fOe)
i
'" +5V
'" 2SoC
TA
Tor I'-- r--
"
-10
I
f--
VOl=+4SV
~r--...~
0
VGG ,. -9V
V OH '" O.OV
5
VaG'" -9V
~
iT:
I
"-
:2
-8
-6
-7
V oo SUPPLY VOL lAGE {V~
I
Voo'" -9V
~
Specliu:ld
Operaung Range_r-
-5
f--
~
r;;
r
1
Ivcc
~
+A5V/
VOL
--
lJ
.g
'" t5V
Vee
vGG '" -9V
-4
f---
I
I
VaG'" -9V
+R-
r-r
f- f-1:-::'
100 CURRENT VS. TEMPERATURE
39
38
37
"
f----f--+-- E
f----f---+--
1
Vee = +5V
-
Voo" -9V
Vee
12.0
=
"
VGG - -9V
~ 10.0
~
3.
+5V
Voo " -9V
ffi
=
i3
.
1
1\
E
2SoC
~
8.0
"
35
i\
VGG= -9V
'\
34
z
33
~
~
32
i3
31
'\
OUTPUTS ARE: OPEN
I"
"
1
~S=Vcc
1"- I"
Q
0
INPUTS = Vee
'\
3.
"l..
29
'--
-
CS = O.DV
28
1
27
--11+
I
+2
+3
+4
OUTPUT VOLT A.GE (VOLTS)
BOO
1702A
700
Vee'" +5V
Voo '" -9V
120
_
VGG '" -9V
400
TA
=
25-C -
1702A-2
1 TTL LOAD - 20 pF
~
600
Vee =+5V- -
-
'>="
500
VDD '" -9V _
-
~
400
<[
300
u
u
300
~
VGG '" -9V
-
I--
1702A-2
200
200
-+--1
17bzA
700
1 TTL LOAO-
.sw 600
'>=" 500
100
100
o
100
900
BOO
<[
80
ACCESS TI ME VS.
TEMPERATURE
900
""
60
AMBIENT TEMPERATURE (oC)
ACCESS TIME VS.
LOAD CAPACITANCE
~
40
20
o
10
m
30 40
W 60
m
M
o
00 100
10
~
30
~
50 00
m
AMBIENT TEMPERATURE (OC)
LOAD CAPACITANCE (pFl
4·8
00
00
inter
1702AL, 1702AL·2
2K (256 x 8) UV ERASABLE LOW POWER PROM
MAXIMUM
ACCESS (tJs)
1702AL
1.0
1702AL-2
0.65
Part No.
tOVGG (tJs)
0.4
0.3
• Inputs and Outputs DTL and TTL
Compatible
• Three-State Output: OR-tie
Capability
• Clocked VGG Mode for Low
Power Dissipation
• Fast Programming: 2 Minutes
for all 2048 Bits
• All 2048 Bits Guaranteed*
Programmable: 100% Factory
Tested
The 1702AL is a 256 word by 8 bit electrically programmable ROM and is the same chip as the industry standard 1702A. The
programming and erasing specifications are identical to the 1702A. The 1702AL operates with the VGG clocked to reduce the
power dissipation.
Initially all 2048 bits of the 1702AL are in the "0" state (output low). Information is introduced by selectively programming
"1"s (output high) in the proper bit location. The 1702AL is packaged in a 24 pin dual in-line package with a transparent lid. The
transparent lid allows the user to expose the 1702AL to ultraviolet light to erase the bit pattern. A new pattern can then be
written into the device.
The 1702AL is fabricated with silicon gate technology. This low threshold technology allows the design and production of high
performance MOS circuits and provides a higher functional density on a monolithic chip than conventional MOS technologies.
*Intel's liability shaU be limited to replacing anv unit which fails to program as desired.
PIN CONFIGURATION
PIN NAMES
BLOCK DIAGRAM
DATA OUT 1
AO-A7
CS
3
22
Vee
°OATAOUT 1
AO
4 (lSB)
21
A3
-DATA OUT 2
5
°DATA OUT 3
6
16
VGG
°DATA OUT 4
7
°DATA OUT 5
8
"DATA OUT 6
9
-DATA OUT 7
10
"DATA OUT 8
Vee
11 (MSB)
14
.....,_,_ _ _' ....
3
DOUT1-DOUTB
DATA OUT 8
Address Inputs
Chip Select Input
Data Outputs
CS
AO A,
PROGRAM
"'7
NOTE: In the read mode a logic 1 at the address inputs
and data outputs is a high and logic 0 is a low.
'THIS PIN IS THE DATA INPUT LEAO DURING PROGRAMMING
U.S. Patent No. 3660819
4-9
1702AL, 1702AL·2
PIN CONNECTIONS
The external lead connections to the 1702AL differ, depending on whether the device is being programmed or used in read mode
(see following table). In the programming mode, the data inputs 1-8 are pins 4-11 respectively. The programmil1g voltages and timing are shown in the Data Catalog ROM and PROM Programming Instructions section.
~
MODE
12
(Vee)
13
(Program)
14
(CS)
15
(VBB)
Read
Vee
Vee
GND
Vee
Program Pulse
GND
Programming
GND
VBB
16
(VGG )
22
(Vee)
23
(Ved
24
(Voo)
Clocked VGG
Vee
Vee
Voo
Pulsed VGG
GND
GND
Pulsed Voo
Absolute Maximum Ratings*
'COMMENT
Ambient Temperature Under Bias ....... -10°C to +80°C
Storage Temperature . . . . . . . . . . . . . -65°C to +125 0 C
Soldering Temperature of Leads (10 sec) ........ +300 0 C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 2 Watts
Read Operation: Input Voltages and Supply
Voltages with respect to Vee . . . . . . . . . . +0.5V to -20V
Program Operation: Input Voltages and Supply
-48V
Voltages with respect to Vee . . . . . . . . . . . . .
D.C. and Operating Characteristics
R EAD OPERATION
Symbol
Test
III
Address and Chip Select
Input load Current
IlO
10001 [1]
Output leakage Current
Min.
Stresses above those listed under "Absolute Maximum Rat·
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for ex·
tended periods may affect device reliability.
TA = oDe t6 70De, Vee = +5V ±5%, Voo = -9V ±5%, VGG [1] = -9V ±5%,
unless otherwise noted.
1702A l limits
Typ.[2]
Max.
Min.
1702Al-2 limits
Typ.l2]
Max.
1
1
Unit
pA
Conditions
VIN = O.OV
1
pA
VOUT = O.OV, CS = Vee-2
7
10
rnA
15
mA
TA=25°C CS=V IH , VGG=VCC'
TA=O°C IOl=O.OmA
50
35
50
rnA
CS = Vee -2,lol = O.OmA,
TA = 25°C, Continuous
32
46
32
46
rnA
CS = O.OV,IOl = O.OmA,
TA = 25°C, Continuous
Power Supply Current
38
60
38
60
rnA
CS = Vee -2,IOl = O.OmA,
TA = O°C, Continuous
leFl
Output Clamp Current
8
14
5.5
8
rnA
VOUT=-1.0V,
TA = O°C, Continuous
leF2
Output Clamp Current
7
13
5
7
rnA
VOUT = -1.0V,
TA = 25°C, Continuous
IGG
Gate Supply Current
1
pA
VIL1
Input low Voltage
for TT II nterface
-1
0.65
-1
0.65
V
VIl2
Input low Voltage
for MOS Interface
VOO
Vee- 6
VOO
Vee-6
V
VIH
Address and Chip Select
Input High Voltage
Vcc-2
Vce+O•3
Vcc-2
Vcc+0.3
V
1
7
10
10002
Power Supply Current
Power Supply Current
10Dl [1]
Power Supply Current
35
1002
Power Supply Current
1003
15
....
1
IOl
Output Sink Current
1.6
IOH
Output Source Current
-2.0
VOL
Output Low Voltage
VOH
Output High Voltage
4
-2.0
-3
3.5
1.6
4
-3
0.45
3.5
4.5
4.5
0.45
rnA
VOUT= 0.45V
rnA
VOUT= O.OV
V
IOl = 1.6mA
V
IOH = -200pA
NOTES: 1. The 1702Al is operated with the VGG clocked to obtain low power dissipation. The average 100 will vary between 1000 and 1001 (at
25DC) depending on the VGG duty cycle (see curve opposite). 2. Typical values are at nominal voltage and TA = 25°C.
4-10
1702AL, 1702AL·2
TYPICAL CHARACTERISTICS
AVERAGE CURRENT VS. DUTY
CYCLE FOR CLOCKED VGG
..
1000
elJeJE~ J••I J-Jv I
40
36
C!
= V 1H
TA
= 25G C
~
700
~
I
2.
!-"
600
I
0
0
-
900
30
1---------------x-------I
l----toH-1
\ _______--Jif
----------~----~
CSIWE
______
DATA
OUT
~~~~D_A_T~A_O_UT_'_NV_A_L_'D
I~--+I----------
t
ns
ns
A.C. TEST CONDITIONS:
I nput Capacitance
ADDRESS
Units
I---teo _ I
I
Aee
I
I
I-to,-II
:><:~-------------------------,I-• ·.·--·~-t~6:-T-~~-6~~
_____________
4-19
2708/8708*
8K AND 4K UV ERASABLE PROM
Max. Power
Max. Access
Organization
800 mW
450 ns
1K x 8
2708l
425 mW
450 ns
1K x 8
2708·1
800mW
350 ns
1K x 8
2704
800 mW
450 ns
512 x 8
2708
•
Low Power Dissipation Max. (2708L)
•
Fast Access Time - 350 ns Max.
(2708·1)
•
Static -
425 mW
No Clocks Required
•
Data Inputs and Outputs TTL
Compatible during both Read and
Program Modes
•
Three·State Outputs - OR·Tie
Capability
The Intel® 2708 is a 8192-bit ultraviolet light erasable and electrically reprogram mabie EPROM, ideally suited where
fast turnaround and pattern experimentation are important requirements. All data inputs and outputs are TTL compatible during both the read and program modes. The outputs are three-state, allowing direct interface with common
system bus structures.
The 2708L at 425 mW is available for systems requiring lower power dissipation than from the 2708. A power
dissipation savings of over 50%, without any sacrifice in speed, is obtained with the 2708L. The 2708L has high input
noise immunity and is specified at 10% power supply tolerance. A high-speed 2708-1 is also available at 350 ns for
microprocessors requiring fast access times. For smaller size systems there is the 4096-bit 2704 which is organized as
512 words by 8 bits. All these devices have the same programming and erasing specifications of the 2708. The 2704
electrical specifications are the same as the 2708.
The 2708 family is fabricated with the N-channel silicon gate FAMOS technology and is available in a 24-pin dual in-line
package.
PIN CONFIGURATION
BLOCK DIAGRAM
DATA OUTPUT
VO-07
A,
I
A.
As
A,
CHIP SELECT
A,
lOGIC
A2
2708/2704
y
DECODER
Y GATING
X
DECODER
64 X 128
ROM ARRAY
A2 - A,----r-______
~____~
(LSB) Ao
(LSB) 00
ADDRESS
0,
'0
02
"
\.\;,
f
A:==:
A,
OUTPUT BUFFERS
INPUTS
~'
As---A. ____
A,----
AB- - - t-,,--
'2
NOTE 1; PIN 22 MUST BE CONNECTED
TO Vss FOR THE 2704.
PIN NAMES
PIN CONNECTION DURING READ OR PROGRAM
Ao . A 9
ADDRESS INPUTS
01-0 8
DATA OUTPUTS/INPUTS
CHIP SElECT/WR!TE ENABLE INPUT
(;StWE
PIN NUMBER
I
,
DATA I/O
INPUTS
1-8,
9-11,
MODE
.
13-17
ADDRESS
I
22,23
READ
Dour
A'N
DESELECT
HIGH IMPEDANCE
DON'T CARE
PROGRAM
D,N
All 8708 speCIficatIons are IdentIcal to the 2708 specIficatIons.
lAIN
I
v,s
PROGRAM
'2
GND
GND
GND
GND
GND
,"
PULSED
26V
4-20
,.
Voo
+12
+,2
' +12
cstWE
20
V"
V,H
VIHW
VB.
Vee
2'
-5
-5
-5
2'
+5
+5
+5
2708 FAMILY
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.
Absolute Maximum Ratings*
_25°C to +85°C
-65°C to +125°C
+20V to -0.3V
+15V to -0.3V
Temperature Under Bias ..
Storage Temperature . . . . . . . . .
V DD With Respect to Vss ..... .
VCC and Vss With Respect to Vss
All Input or Output Voltages With Respect
to Vss During Read . . . . . . . .
CSIWE Input With Respect to Vss
During Programming ...... .
Program Input With Respect to Vss
Power Dissipation . . . . . . . . . . . .
'COMMENT
Stresses above those listed under Absolute Maximum
Ratings" may cause permanent damage to the device.
This IS a stress rating only and functional operation
of the device at these-or any other conditions above
those indicated in the operational sections of this
II
+15V to -0.3V
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
+20V to -0.3V
+35V to -0 3V
1.5W
I
DC and AC Operating Conditions During Read
2708
2708·'
2708L
Temperature Range
O°C _ 70°C
O°C _ 70°C
O°C _ 70°C
Vee Power Supply
5V ± 5%
5V ± 5%
5V ± 10%
VDD Power Supply
12V ± 5%
12V ± 5%
12V ± 10%
VSS Power Supply
-5V ± 5%
-5V ± 5%
-5V ± 10%
READ OPERATION
D.C. and Operating Characteristics
2708L Limits
2708, 2708·1 Limits
Symbol
Parameter
Units
Typ. [2]
Min.
Min.
Max.
Typ.[2]
Max.
Test Conditions
'll
Adctress and Chip Select Input Sink Current
1
10
1
10
.A
VIN
'LO
Output Leakage Current
1
10
1
10
VOUT '" S.SV, CS/WE "" SV
IDD[3]
VOO Supply Current
50
65
21
28
.A
rnA
ICC[3]
VCC Supply Current
6
10
2
4
rnA
All Inputs High;
CS/WE
30
'aa[3]
VBB Supply Current
V,L
Input Low Voltage
V,H
Input High Voltage
VOL
Output Low Voltage
VOHl
Output High Voltage
3.7
VOH2
Output High Voltage
2.4
45
VSS
3.0
14
rnA
0.65
VSS
0.65
V
Vce+ 1
2.2
VCC+1
V
0.4
V
10
0=
S.2SV or VIN
=
VIL
Worst Case Supply Currents[41
=
SV; TA
=
O°C
IOL""" 1.6mA (2708, 2708·1)
0.45
3.7
2.4
800
PD
Power Dissipation
IOL - 2mA (2708Ll
V
IOH - -100 f,lA
V
325
rnW
IOH --1 rnA
T A -700e
425
rnW
TA =ooe
NOTES: 1. VBS must be applied prior to Vee and VOO. VSB must also be the last power supply switched off
2. Typical values are for T A == 25° C and nominal supply voltages.
3. The total power disiipation is not calculated by summing the various currents (100, ICC, and ISB} multiplied by their respective voltages since current paths exist between the various power supplies and VSS. The 100, ICC, and ISB currents should be used to determine power supply capacity only
4. IBB for the 2708L is specified in the programmed state and is 18 mA maximum in the unprogrammed state.
2708L
2708 AND 2708-1
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE
ACCESS TIME VS. TEMPERATURE
~r-----r----'-----'-----r----,
ALL POSSIBLE OPERATING
CONDITIoNs
Vee = 5.25V
Voo
"
1 TTL
~OAD 1~F
+
12.6V
V88 = -5.25V
........
300
!g
10.
~.
200
_~B
-
f.--
f.-- V
100
2'
. .
TAfe)
8'
o~:::t~:t~~~~~~}~~Jc
o
20
40
60
TAI"C)
4-21
80
100
•
-20
20
4.
TA I"C)
60
2708 FAMILY
A. C. Characteristics
Symbol
Parameter
Min.
tACC
Address to Output Delay
tco
Chip Select to Output Delay
tDF
Chip Deselect to Output Float
0
tOH
Address to Output Hold
0
2708-1 Limits
Typ_
Max_
2708, 2708L, Limits
Typ_
Min_
Max_
280
350
280
450
ns
60
120
60
120
ns
120
ns
120
0
0
Units
ns
A.C. TEST CONDITIONS:
Parameter
Typ.
C'N
Input Capacitance
COUT
Output Capacitance
Symbol
Max.
Unit.
Conditions
4
6
pF
V,N = OV
8
12
pF
VOUT = OV
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ';;20 ns
Timing Measurement Reference Levels: O.BV and
2.BV for inputs; O.BV and 2.4V for outputs.
Input Pulse Levels: 0.65V to 3.0V
Note: 1. This parameter is periodically sampled and is not 100% tested.
Waveforms
ADDRESS
_x___x__
I
l-toH_1
\ _ _------.J),...----+I
1-·----IAcc---_.1
ERASURE CHARACTERISTICS
form Intel which should be placed over the 270B window
to prevent unintentional erasure.
The erasure characteristics of the 2708 family are such that
erasure begins to occur when exposed to Iight with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range.
Data show that constant exposure to room level fluorescent lighting could erase the typical device in approximately 3 years, while it would take approximately 1 week
to cause erasure when exposed to direct sunlight. If the
2708 is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels are available
The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instructions Section) for the
2708 family is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity X exposure time) for erasure
should be a minimum of 15 W-sec/cm 2 . The erasure time
with this dosage is approximately 15 to 20 minutes using an
ultraviolet lamp with a 12000 /lW/cm2 power rating. The
device should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes
which should be removed before erasure.
4-22
2716
16K (2K x 8) UV ERASABLE PROM
• Pin Compatible to Intel® 5V ROMs
(2316E, 2332A, and 2364A) and 2732
EPROM
• Fast Access Time
- 350 ns Max. 2716·1
- 390 ns Max. 2716·2
- 450 ns Max. 2716
• Single
• Simple Programming Requirements
Single Location Programming
Programs with One 50 ms Pulse
+ 5V Power Supply
• Inputs and Outputs TTL Compatible
during Read and Program
• Low Power Dissipation
- 525 mW Max. Active Power
- 132 mW Max. Standby Power
• Completely Static
The Intel® 2716 is a 16,384·bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2716
operates from a single 5-volt power supply, has a static standby mode, and features fast single address location programming. It makes designing with EPROMs faster, easier and more economical. For production quantities, the 2716 user can
convert rapidly to Intel's pin-for-pin compatible 16K ROM (the 2316E) or the new 32K and 64K ROMs (the 2332A and
2364A respectively).
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with the newer high performance
+5V microprocessors such as Intel's 8085 and 8086. The 2716 is also the first EPROM with a static standby mode which
reduces the power dissipation without increasing access time. The maximum active power dissipation is 525 mW while the
maximum standby power dissipation is only 132 mW, a 75% savings.
The 2716 has the simplest and fastest method yet devised for programming EPROMs - single pulse TTL level program min\!.
No need for high voltage pulsing because all programming controls are handled by TTL signals. Program any location at any
time-either individually, sequentially or at random, with the 2716's single address location programming. Total programming
time for all 16,384 bits is only 100 seconds.
PIN CONFIGURATION
.
A,
Vee
A,
A,
A,
MODE SELECTION
2732 t
2716
Vpp
DE
A,
A6
A,
A,
CE/PGM
(lSI
DE
V ..
Vee
OUTPUTS
120)
(21)
124)
(9-1'.13-11)
MODE
A"
OElVpp
A1
AD
A1
AD
~
Vee
A,
0,
o.
Read
V,L
+5
Dour
V,H
V'L
Don't Care
+5
Standby
+5
+5
HIgh Z
Program
Pulsed VIL 10 VIH
V,H
+25
+5
D,N
Program Verify
V,L
V,L
+25
+5
Dour
Program Inhibit
V,L
V,H
+25
+5
High Z
f--:----
0,
0,
OND
BLOCK DIAGRAM
t Refer to 2732
OATAoufPU1S
Vee 0 - - -
data sheet for
speci fi cati ons
PIN NAMES
AO- A l0
ADDRESSES
CE/PGM
CHIP ENABLE/PROGRAM
DE
0-°1
OUTPUT ENABLE
Ao-AlO
ADDRESS
INPUTS
OUTPUTS
4-23
u,
---Do
2716
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . . . . . -l~oC to +80:C
Storage Temperature . . . . . . . . . . . . . . -65 C to +125 C
All Input or Output Voltages with
Respect to Ground . . . . . . . . . . . . . . . +6V to -0.3V
Vpp Supply Voltage with Respect
to Ground During Program . . . . . . . . +26.5V to -0.3V
'COMMENT: Stresses above those listed under "Absolute Maxi·
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
DC and AC Operating Conditions During Read
2716
2716-1
2716·2
O°C -70°C
O°C _ 70°C
O°C _ 70°C
V CC Power Supply [1,2]
5V ±5%
5V± 10%
5V ± 5%
Vpp Power Supply [2]
VCC
VCC
VCC
Temperature Range
READ OPERATION
D.C. and Operating Characteristics
Limits
Parameter
Symbol
Typ.[31
Min.
Max.
Unit
Conditions
III
Input Load Cu rrent
10
fJ.A
VIN = 5.25V
ILO
Output Leakage Current
10
fJ.A
VOUT= 5.25V
Ipp,l2I
Vpp Current
5
rnA
Vpp = 5.25V
I CC1 [2]
Vcc Current (Standby)
10
25
rnA
CE = VIH. DE = VIL
lee2[2]
Vee Current (Active)
57
100
rnA
C5E=cr=VIL
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
VcC+l
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.45
2.4
V
IOL = 2.1 rnA
V
IOH = -400 fJ.A
NOTES: 1. Vce must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to VCC except during programming. The supply current would then be the sum of ICC and IPP1.
3. Typical values are for T A = 25°C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
Typical Characteristics
ICC CURRENT
vs.
TEMPERATURE
70
60
-- --
'-
r--
50
ACCESS TIME
r--
ICC2 ACTIVE CURRENT
ICCl STANDBY CURRENT
C"E=VIH
Vee 5V----,.--.-
T
,
o
o
w
w
~
~
TEMPERATURE
700
700
600
600
500
500
1400
~
u
10
VS.
CAPACITANCE
C'E=VIL
Vcc'5V _ _
!:} 30
20
ACCESS TIME
v••
50
TEMPERATURE ( C)
60
ro
60
-
300
200
-
f.--
I--
-
Vec = 5V
200
100
o
I--
100
o
o
100
200
300
400
el (pF)
4-24
SOO
600
700
800
o
w
w
~
~
50
TEMPERATURE 1°C)
60
ro
60
2716
A.C. Characteristics
2716 Limits
Symbol
Parameter
Min
Typ[31
2716-1 Limits
Max Min Typ[31
Max
2716-2 Limits
Min Typ[31
Test
Unit
Conditions
Max
BE = OE = VIL
tACC
Address to Output Delay
450
350
390
ns
tCE
CE to Output Delay
450
350
390
ns
OE = VIL
tOE
Output Enable to Output Delay
120
120
120
ns
CE = VIL
tDF
Output Enable High to Output Float
0
100
ns
CE = VIL
tOH
Output Hold from Addresses, CE or
0
ns
CE = OE = VIL
100
0
100
0
0
0
OE Whichever Occurred First
Capacitance [4] TA; 25°C, f ; 1 MHz
Symbol
Parameter
Typ.
A.C. Test Conditions:
Max_
Unit
Conditions
Output Load: 1 TTL gate and CL; 100 pF
CIN
Input Capacitance
4
6
pF
VIN; OV
Input Rise and Fall Times: <20 ns
Input Pulse Levels: O.BV to 2_2V
COUT
Output Capacitance
8
12
pF
V OUT ; OV
Timing Measurement Reference Level:
Inputs
1 V and 2V
Outputs
O.BV and 2V
A. C. Waveforms [1]
r - - - - - - - - - - - - - - - · . . ------'""-1
ADDRESSES
VALID
ADDRESSES
CE----------------+_~
teE
OE---------------+--------~
[5]
[61
l - - - - - l toF
rrrrrri--· . . . . . •
HIGH Z
OUTPUT--------------------------------i-~._._~~
HIGH Z
'\,..Jio..Jio..Jio..Jio..Jio.+_ _ • • • • • •
NOTE: 1.
2.
3.
4.
VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
Vpp may be connected directly to VCC except during programming. The supply current would then be the sum of ICC and IpP1.
Typical values are for T A = 25'C and nominal supply voltages.
This parameter is only sampled and is not 100% tested.
5. OE may be delayed up to tACC -- tOE after the falling edge of CE without impact on tACC'
6. tDF'is specified from OE or CE, whichever occurs first.
4-25
2716
TYPICAL 16K EPROM SYSTEM
A8·15
ADO·7
8212
ADDRESS
LATCH
ALE
I
8085
~
~
~
~ A14
~
I
~"-A"
AO-A7
2716
D0-7
1
....... OE
A8
~
~
101M
~
~~
-!-'
RD
VCC
CEO
512 X 8
O.C.
PROM
3604A
~N
!3!3
.J'J,.
-
M..,
">el)
uu
II
L--..j CE 1
0hfl'
~U
r-
...
I-
~~I~-
... ... ,,....
r-~I-
CE2
CE3
CE4
CE5
CE6
CE7
... ~~
• This scheme accomplished by using CE (PD) as the primary decode. OE (CS) is now controlled by previously unused
signal. RD now controls data on and off the bus by way of OE.
• A selected 2716 is available for systems which require CE access of less than 450 ns for decode network operation.
• The use of a PROM as a decoder allows for:
a) Compatibility with upward (and downward) memory expansion.
b) Easy assignment of ROM memory modules, compatible with PUM modular software concepts.
SK, 16K, 32K, 64K 5V EPROM/ROM FAMILY
PRINTED CIRCUIT BOARD LAYOl!T
4·26
2716
ERASURE CHARACTERISTICS
OUTPUT OR-TIEING
The erasure characteristics of the 2716 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2716 in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the 2716 is to
be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from
Intel which should be placed over the 2716 window to
prevent unintentional erasure.
Because 2716's are usually used in larger memory arrays,
Intel has provided a 2 line control function that accomodates this use of multiple memory connections. The two
line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will
not occur.
To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the
primary device selecting function, while OE (pin 20) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their
low power standby mode and that the output pins are only
active when data is desired from a particular memory
device.
PROGRAMM!NG
The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instruction Section) for the
2716 is exposure to shortwave ultraviolet light which has
a wavelength of 2537 Angstroms (A). The integrated dose
(Le., UV intensity X exposure time) for erasure should be
a minimum of 15 W-sec/cm 2 • The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 JlW/cm2 power rating. The 2716
should be placed within 1 inch of the lamp tubes during
erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
Initially, and after each erasure, all bits of the 2716 are in
the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "l's" and "O's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
DEVICE OPERATION
The 2716 is in the programming mode when the Vpp power
supply is at 25V and OE is at V IH. The data to be programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.
The five modesof operation of the 2716 are listed in Table
I. It should be noted that all inputs for the five modes are at
TTL levels. The power supplies required are a +5V VCC and
a Vpp. The Vpp power supply must be at 25V during the
three programming modes, and must be at 5V in the other
two modes.
When the address and data are stable, a 50 msec, active
high, TTL program pulse is applied to the CE/PGM input.
A program pulse must be applied at each address location
to be programmed. You can program any location at any
time - either individually, sequentially, or at random.
The program pulse has a maximum width of 55 msec. The
2716 must not be programmed with a DC signal applied to
the CE/PGM input.
TABLE I. MODE SELECTION
~
CE/PGM
DE
V,,
Vee
OUTPUTS
1181
1201
1211
1241
19-11,13.17)
MODE
R..d
VIL
VIL
+5
+5
DOUT
V'H
Pulsed VIL to VIH
Don'teare
+5
+5
High Z
V'H
+25
+5
D'N
Program Verify
VIL
V'L
+25
+5
DOUT
Program Inhibit
V'L
V'H
+25
+5
High Z
Standby
Program
Programming of multiple 2716s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the paralleled 2716s may be connected together when they are programmed with the same data. A high level TTL pulse
applied to the cr/PGM input programs the paralleled
2716s.
PROGRAM INHIBIT
READ MODE
The 2716 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. OUtput Enable (OE) is the output
control and should be used to gate data to the output
pins, independent of device selection. Assuming that
addresses are stable, address access time (tACC) is equal to
the delay from CE to output (tCE). Data is available at
the outputs 120 ns (tOE) after the falling edge of OE,
assuming that CE has been low and addresses have been
stable for at least tACC - tOE,
STANDBY MODE
Programming of multiple 2716s in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel 2716s may be
common. A TTL level program pulse applied to a 2716's
CE/PGM input with Vpp at 25V will program that 2716.
A low level CE/PGM input inhibits the other 2716 from
being programmed.
PROGRAM VERIFY
The 2716 has a standby mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW. The
2716 is placed in the standby mode by applying a TTL high
signal to the CE input. When in standby mode, the outputs
are in a high impedence state, independent of the OE input.
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify
may be performed wth Vpp at 25V. Except during programming and program verify, Vpp must be at 5V.
4-27
2732
32K (4K x 8) UV ERASABLE PROM
• Single +SV
± 5%
Power Supply
• Pin Compatible to Intel® 2716 EPROM
and 2332/2364 ROMs
• Output Enable for MCS-8S™ and
MCS-86™ Compatibility
• Completely Static
• Simple Programming Requirements
- Single Location Programming
- Programs with One SOms Pulse
• Fast Access Time: 4S0ns Max.
• Low Power Dissipation:
lS0mA Max. Active Current
30mA Max. Standby Current
• Three-State Output for Direct Bus
Interface
The Intel® 2732 is a 32,768-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2732
operates from a single 5-volt power supply, has a standby mode, and features an output enable control. For production, the
pin compatible 2332 and 2364 ROMs are available. The total programming time for all bits is three and a half minutes. All
these features make designing with the 2732 in microcomputer systems faster, easier, and more economical.
An important 2732 feature is the separate output control, Output Enable (OEI, from the Chip Enable control (CEI. The OE
control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-30 describes the
microprocessor system implementation of the OE and CE controls on Intel's 2716 and 2732 EPROMs. AP-30 is available
from Intel's Literature Department.
The 2732 has a standby mode which reduces the power dissipation without increasing access time. The maximum active
current is 150mA, while the maximum standby current is only 30mA, an 80% savings. The standby mode is achieved by
applying a TTL-high signal to the CE input.
PIN CONFIGURATION
MODE SELECTION
~
Vee
A7
A.
As
Ag
A_
A"
A2
AlO
A,
CE
Ao
07
00
D.
0,
Os
DEIVpp
CE
MODE
(181
OE/Vpp
1201
Vcc
(24)
OUTPUTS
(9-11,13-17)
Read
VIL
VIL
+5
DOUT
Standby
V IH
Don't Care
+5
High Z
Program
VIL
Vpp
+5
DIN
Program Verify
V IL
V IL
+5
DOUT
Program Inhibit
V IH
Vpp
+5
High Z
0_
BLOCK DIAGRAM
03
Vcc<>-----
DATA OUTPUTS
00-07
GNOO---
PIN NAMES
AO-A11
ADDRESSES
CE
CHIP ENABLE
DE
OUTPUT ENABLE
Oo-~
OUTPUTS
Y·GATING
32.768·8IT
CELL MATRIX
4-28
2732
PROG RAM M I NG;";:~;::~!\:-.""~::"Z,l
The programming specifications are described in the Data Catalog PROM/ROM Programming Instlii!.r;rti9'1S..'
ABSOLUTE MAXIMUM RATINGS*
·COMMENT
0,'
,
'\';I~:~~>~\
\'
Stresses above those listed under "Absolute Maximum RatingS,,~~~~'aa~,
permanent damage to the device. This is a stress rating only and functi~~1
operation of the device at these or any other conditions above those
Temperature Under Bias ..... , ...... -1O·C to +80·C
Storage Temperature .............. -65·C to +125·C
All Input or Output Voltages with
Respect to Ground ................... +6V to -O.3V
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA
= O·C to 70·C. Vcc = +5V ± 5%
READ OPERATION
Limits
Symbol
Parameter
Typ.l11
Max.
Unit
ILl1
Input Load Current (except OElVpp)
10
p.A
1L12
OElVpp Input Load Current
300
p.A
ILO
Output Leakage Current
ICC1
Vcc Current (Standby)
Min.
10
p.A
15
30
mA
85
150
mA
Conditions
= 5.25V
VIN = 5.25V
Your = 5.25V
CE = VIH. OE = VIL
OE = CE = VIL
VIN
ICC2
Vee Current (Active)
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
Vcc+1
V
VOL
Output Low Voltage
0.45
V
IOL
VOH
Output High Voltage
V
IOH
2.4
= 2.1mA
= -400p.A
Note: 1. Typical values are for TA = 25·C and nominal supply voltages.
TYPICAL CHARACTERISTICS
Icc CURRENT
VS.TEMPERATURE
'00
90
....
80
70 f-;{
E
60
f-
CE TO OUTPUT DELAY (t CE )
VS. CAPACITANCE
~2 (lcTlv~ CU~R;:;t- J-....
400
I-
CE=V1l
Vcc '5V
I
I
....
l - t-
400
!
~
20
Vee'"' 5V
'0
'0
20
I I I
30
40
50
TEMPERATURE (OC)
t- f- l-
t--
300
200
30
I
~ t-
~
~Cl
(STANDBY CURRENT)
e'E'=VIH
0
~
~ 300
I
I I I
ll40
500
500
I I I
f-..l....J I
50
CE TO OUTPUT DELAY (t CE )
VS.TEMPERATURE
I
60
200
I
70
'00
y25;C
80
'000
'00
200
300 400
C L (pFI
4·29
500
600
700
Vcc"'5V
800
0
'0
20
30
40
50
TEMPERATURE 1°C)
I
I
60
70
80
2732
A.C. CHARACTERISTICS
± 5%
TA = O°C to 70°C, VCC = +5V
Limits
Symbol
Parameter
Typ.i11
Max.
Unit
tACC
Address to Output Delay
450
ns
CE = OE = VIL
tCE
CE to Output Delay
450
ns
OE = VIL
tOE
Output Enable to Output Delay
120
ns
CE = VIL
tOF
Output Enable High to Output Float
0
100
ns
CE = VIL
tOH
Address to Output Hold
0
ns
CE = OE = VIL
CAPACITANCE
Symbol
Min.
A.C. TEST CONDITIONS
[21 TA = 25°C, f = 1MHz
Parameter
CIN1
Input Capacitance
Except OE/Vpp
CIN2
OE/Vpp Input
Capacitance
COUT
Output Capacitance
A.C. WAVEFORMS
Test Conditions
Typ.
Max.
4
6
Unit Conditions
pF
VIN = OV
20
pF
VIN = OV
12
pF
VOUT = OV
Output Load: 1 TTL gate and CL = 100pF
Input Rise and Fall Times: ::; 20ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1V and 2V
Outputs 0.8V and 2V
[31
~-------A-D~-:-C-~D-SE-S---
ADDRESSES _ _ _ _ _ _ _
-.tcETi
1450MAX.J
------------+-----~
DE
tOF
~---ot- 1100 MAX.)
151
HIGHZ
OUTPUT --------,;...,.:..-------H~_++<
NOTES:
1. TYPICAL VALUES ARE FOR TA = 25°C AND NOMINAL SUPPLY VOLTAGES
2. THIS PARAMETER IS ONLY SAMPLED AND IS NOT 100% TESTED.
3. ALL TIMES SHOWN IN PARENTHESES ARE MINIMUM TIMES AND ARE NSEC UNLESS OTHERWISE SPECIFIED.
4. DE MAY BE DELAYED u~o 33~s AFTER THE FALLING EDGE OF CE WITHOUT IMPACT ON tAce5, tOF IS SPECIFIED FROM DE OR CE, WHICHEVER OCCURS FIRST.
4-30
HIGHZ
2758
8K (1 K x 8) UV ERASABLE LOW POWER PROM
•
•
Single
•
+ 5V Power Supply
•
Fast Access Time: 450 ns Max. in
Active and Standby Power Modes
Simple Programming Requirements
Single Location Programming
Programs with One 50 ms Pulse
•
Inputs and Outputs TTL Compatible
during Read and Program
Low Power Dissipation
525 mW Max. Active Power
132 mW Max. Standby Power
•
•
Completely Static
Three·State Outputs for OR·Ties
The Intel® 2758 is a 8192-bit ultraviolet erasable and electrically programmable read-only memory (EPROM)_ The 2758
operates from a single 5-volt power supply, has a static standby mode, and features fast single address location programming_ It makes designing with EPROMs faster, easier and more economical. The total programming time for all 8192 bits
is 50 seconds_
The 2758 has a static standby mode which reduces the power dissipation without increasing access time_ The maximum
active power dissipation is 525 mW, while the maximum standby power dissipation is only 132 mW, a 75% savings_ Powerdown is achieved by applying a TTL-high signal to the CE input_
A 2758 system may be designed for total upwards compatibility with Intel's 16K 2716 EPROM (see Applications Note
30). The 2758 maintains the simplest and fastest method yet devised for programming EPROMs - single pulse TTLlevel programming. There is no need for high voltage pulsing because all programming controls are handled by TTL
signals. Program any location at any time - either individually, sequentially, or at random, with the sing I" address
location programming.
MODE SELECTION
PIN CONFIGURATION
~
Vee
AS
CE/PGM
AR
GE
vpp
Vee
OUTPUTS
118)
119)
120)
121)
124)
19-11,13·17)
MODe
0,
GNO
'-----'
Read
V,L
V,L
V,L
+5
+5
DOUT
Standby
V,H
V,L
Don't
Care
+5
+5
High Z
Program
Pulsed V IL to V IH
V,L
V,H
+25
+5
D,N
Program Verify
V,L
V,L
\IlL
+25
+5
DOUT
Program Inhibit
V,L
V,L
\'IH
+25
+5
High Z
BLOCK DIAGRAM
PIN NAMES
1
--
Ao- A9
ADDRESSES
CEiPGM
CHIP ENABLEIPROClRAM
OE
OUTPUT ENABLE
0 0 °1
OUTPUTS
A,
SELECT REFERENCE
Vee 0 - - -
INPUT LEVEL
AO~A9
ADDRESS
INPUTS
4-31
DATA OUTPUTS
00-07
2758
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions section.
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . .
· .. -10°C to +80°C
· . _65°C to +125°C
Storage Temperature . . . . . . . . .
All Input or Output Voltages with
Respect to Ground . . . . . . . .
· ... +6V to -0.3V
Vpp Supply Voltage with Respect
to Ground During Programming ..... +26.5V to -0.3V
*COMMENT: Stresses above those listed under "Absolute Maxi·
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec·
tions of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
READ OPERATION
D.C. and Operating Characteristics
TA=0°Ct070°C, VCC[1,2] =+5V±5%, Vpp[2] =vcc
Symbol
Limits
Parameter
Unit
Typ,l31
Min.
Conditions
Max.
III
Input Load Current
10
(J.A
VIN = 5.25V
I LO
Output Leakage Current
10
(J.A
VOUT = 5.25V
IpPl [2J
Vpp Current
5
mA
Vpp= 5.25V
ICCl [2J
VCC Current (Standby)
10
25
mA
CE = VIH, OE = VIL
57
100
mA
OE=CE=VIL
ICC2[2]
V CC Current (Active)
A R[4]
Select Reference Input Level
-0.1
0.8
V
VIL
Input Low Voltage
-0.1
0.8
V
2.0
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
NOTES:
1.
2.
3.
4.
liN = 10(J.A
Vcc + 1
V
0.45
V
IOL - 2.1 mA
V
IOH - -400(J.A
2.4
Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of ICC and IpP1
Typical values are for TA = 25 'C and nominal supply voltages.
AR is a reference voltage level which requires an input current of only 10 JiA. The 2758 S1865 is also available which has a reference
voltage level of VIH instead of VIL.
Typical Characteristics
ICC CURRENT
ACCESS TIME
v•.
v••
TEMPERATURE
70
60
-
---
50
1
ICC2
CAPACITANCE
r-
CliVE CURRENT
CE= Vil
Vce" SV
40
S!30
lec1
10
o
!
~
....
u
20
o
ro
w
30
~
CURR NT
CE-=VIH
Vec = 5V
50
60
lro
700
700
600
600
500
500
400
300
200
ST~BY
TEMPERATURE (Oc)
ACCESS TIME
vs.
TEMPERATURE
100
--
-
!
100
200
r----
400
~ 300
200
- r-
,..-
100
o
50
5V
8
~
f--
Vee
t
300
400
CL (pF)
4-32
500
600
700
800
o
10
~
30
~
M
TEMPERATURE (OC)
W
M
M
2758
A.C. Characteristics
T A = O°C to 70°C. VCC[1J = +5V ±5%. Vpp[2J = VCC
Limits
Symbol
Parameter
Min.
TypPI
Max.
Unit
Test Conditions
Address to Output Delay
250
450
ns
tCE
CE to Output Delay
280
450
ns
OE = VIL
tOE
Output Enable to Output Delay
120
ns
CE = VIL
tDF
Output Enable High to Output Float
0
100
ns
CE = VIL
tOH
Output Hold From Addresses, CE
or OE Whichever Occurred First
0
ns
CE=OE=VIL
tACC
A.C. Test Conditions:
CapacitanceI4JTA=25°C, f= 1 MHz
Symbol
Parameter
CE=OE=VIL
Typ.
Max.
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
lV and 2V
Outputs 0.8V and 2V
Unit Conditions
CIN
Input Capacitance
4
6
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT= OV
NOTE: Please refer to page 2 for notes.
A.C. Waveforms l5]
ADDRESSES
ADDRESSES
VALID
CE--------+-'"
teE
.....--(4,50 MAX.)
6E---------+------~
!"-------+--. . . • . • . • • .
[7J
tOF
(100 MAX.)
....- ...... .
tOH_
(0)
~.,....,....,....,...,...
OUTPUT _ _ _ _ _ _ _ _~H~IG~H~Z_ _ _ _ __4~~_f_f~~
HIGH Z
'-..Io...Io...Io...Io...a.....II-_ • • • • • • •
NOTES: 1. VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp
2. Vpp may be connected dlreclly to VCC except dUring programming. The supply current would then be the sum of ICC and IpP1
3. Typical values are for TA = 25'C and nominal supply voltages.
4. This parameter IS only sampled and is not 100% tested.
5 All times shown in parentheses are minimum times and are nsec unless otherWise speCified.
6 DE may be delayed up to 330 ns after the falling edge of CE without impact on tACC
7. tOF IS speCified from 5E or GE, whichever occurs first
4-33
2758
ERASURE CHARACTERISTICS
the outputs 120 ns (tOE) after the falling edge of OE,
assuming that CE has been low and addresses have been
stable for at least tACC - tOE'
The erasure characteristics of the 2758 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2758 in approximately 3
years, while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the 2758 is to
be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from
Intel which should be placed over the 2758 window to
prevent unintentional erasure.
STANDBY MODE
The 2758 has a standby mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW. The
2758 is placed in the standby mode by applying a TTL high
signal to cr input. When in standby mode, the outputs
are in a high impedence state, independent of the OE input.
OUTPUT OR·TIEING
Because EPROMs are usually used in larger memory arrays,
Intel has provided a 2 line control function that accommodates this use of multiple memory connections. The two line
control function allows for:
The recommended erasure procedure (see Data Catalog
Programming Section) for the 2758 is exposure to shortwave ultraviolet light which has a wavelength of 2537
Angstroms (1\). The integrated does (i.e., UV intensity X
exposure time) for erasure should be a minimum of 15
W-sec/cm 2 . The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with
12,000 pW/cm 2 power rating. The 2758 should be placed
within 1 inch of the lamp tubes during erasure. Some lamps
have a filter on their tubes which should be removed before
erasure.
a) the lowest possible memory Power dissipation, and
b) complete assurance that output bus contention will
not occur.
To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the
primary device selecting function, while OE (pin 20) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their
low power standby mode and that the output pins are only
active when data is desired from a particular memory device.
DEVICE OPERATION
The five modes of operation of the 2758 are listed in Table
1. It should be noted that all inputs for the five modes are
at TTL levels. The power supplied required are a +5V VCC
and a Vpp. The Vpp power supply must be at 25V during
the two programming modes, and must be at 5V in the
other th ree modes. In all operational modes, AR must be
at VIL (except for the 2758 S1865 which has AR at VIH).
PROGRAMMING
Initially, and after each erasure, all bits of the 2758 are in
the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "O's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
TABLE I. MODE SELECTION
0::
CE/PGM
AR
fiE
Vpp
Vee
OUTPUTS
(181
1191
(201
(21)
(241
(9·11,13-111
The 2758 is in the programming mode when the Vpp
power supply is at 25V and OE is at V IH. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.
MODE
Read
V,L
V,L
V,L
+5
+5
DOUT
Standby
V,H
V,L
Don't
Care
+5
+5
High Z
Program
Pulsed V tL to V IH
V,L
V,H
+25
+5
D,N
Program Verify
V,L
V,L
V,L
+25
+5
DOUT
Program Inhibit
V,L
V,L
V,H
+25
+5
High Z
When the address and data are stable, a 50 msec,
active high, TTL program pulse is applied to the CE/PGM
input. A program pulse must be applied at each address
location to be programmed. You can program any location
at any time - either individually, sequentially, or at random. The program pulse has a maximum width of 55 msec.
READ MODE
The 2758 must be programmed with a DC signal applied
to the CE/PGM input.
The 2758 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output
pins, independent of device selection. Assuming that
addresses are stable, address access time (tACC) is equal to
the delay from CE to output (tCE)' Data is available at
Programming of multiple 275Bs in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the parallelled 2758s may be connected together when they are
programmed with the same data. A high level TTL pulse
applied to the CE/PGM input programs the paralleled
2758s.
4-34
2758
PROGRAM INHIBIT
PROGRAM VERIFY
Programming of multiple 2758s in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel 2758s may be
common. A TTL level program pulse applied to a 2758's
CE/PGM input with Vpp at 25V will program that 2758.
A low level CE/PGM input inhibits the other 2758 from
being programmed.
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify
may be performed with Vpp at 25V. Except during programming and program verify, Vpp must be at 5V.
4-35
3604A, 3624A FAM I LY
4K (512 x 8) HIGH·SPEED PROM
3604A-2
3624A-2
3604A
3624A
3604AL
Max. T A(ns)
60
70
90
Max. ICC(mA)
170
170
130/25*
*Standby Current When The Chip is Deselected.
• Four Chip Select Inputs
For Easy Memory
Expansion
• Fast Access Time
--60ns Max (3604A-2, 3624A-2)
• Low Standby Power Dissipation
(3604AL) --32}-LW/Bit Max
• Polycrystalline Silicon Fuse
For Higher Reliability
• Open Collector (3604A)
or Three State (3624A)
Outputs
• Hermetic 24 Pin DIP
The Intel® 3604A/3624A are 4096·bit bipolar PROMs organized as 512 words by 8 bits. The fast second generation
3604A/3624A replaces its Intel predecessor, the 360413624. Higher speed PROMs, the 3604A·2/3624A·2, are now avail·
able at 60 ns. All 3604A/3624A specifications, except programming, are the same as or better than the 360413624. Once
programmed, the 3604A/3624A are interchangeable with the 360413624
The PROMs are manufactured with all outputs initially logically high. Logic low levels can be electrically programmed
in selected bit locations. Both open collector and three·state outputs are available. Low standby power dissipation can
be achieved with the 3604AL. The standby power dissipation is approximately 20% of the active power dissipation.
The 3604A/3624A are available in a hermetic 24'pin dual in·line package. These PROMs are manufactured with the
time·proven polycrystalline silicon fuse technology.
h
Mode/Pin Connection
~~~::' ~~~:~:~
I READ,
I
r·
ln22
I
I No Connect or 5V i
P,"2~
5V
_J
3-60-4-'AL------+!--+5-V--+M-,-;t-b'-Left Open
PROGRAM
I
3604A.3604A-2
PIN NAMES
AO-AS
ADDRESS INPUTS
CS1-CS2 }
CS3-CS4
CHIP SELECT INPUTS
01-0S
DATA OUTPUTS
III
[1] To select the PROM CSl
and CS3
PIN CONFIGURATION
BLOCK DIAGRAM
= CS4
~
CS2
LOGIC SYMBOL
",
",
",
".
0,
0,
0,
.
",
o.
o.
o•
"
'
o.
'0
..
....,
4·36
~
1.
0,
~
0
3604A, 3624A FAMILY
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions
Absolute Maximum Ratings*
'COMMENT
Temperature Under Bias ........... -65°C to +125°.(;
Storage Temperature . . . . . . . . . . . . . _65°C to +160°C
Output or Supply Voltages ......... -O.5V to 7 Volts
All Input Voltages. . . . . . . . . . . . . . . . .. -1.6 to 5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . 100mA
D. C. Characteristics:
All Limits Apply for Vcc= -+;5.DV ±5%, T A = DOC to +75°C
Limits
Typ)l]
Max.
Unit
Test Conditions
Address Input Load Current
-0.05
-0.25
mA
Vee = 5.25V, V A = 0.45V
-0.05
Symbol
IFA
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Parameter
Min.
IFS
Chip Select Input Load Current
-0.25
mA
Vee = 5.25V, Vs = 0.45V
IRA
Address Input Leakage Current
40
jJ.A
Vee = 5.25V, V A = 5.25V
IRS
Chip Select Input Leakage
Current
40
jJ.A
Vee - 5.25V, Vs = 5.25V
VCA
Address Input Clamp Voltage
-0.9
-1.5
V
Vee = 4.75V,IA = -10 mA
Ves
Chip Select Input Clamp
Voltage
-0.9
-1.5
V
Vee = 4.75V, Is = -10 mA
VOL
Output Low Voltage
0.3
0.45
V
Vee = 4.75V, 10L = 15 mA
leEX
Output Leakage Current
100
jJ.A
Vee = 5.25V, VeE = 5.25V
Icc,
Power Supply Current (3604A,
3604A-2, 3624A, and 3624A·2)
170
mA
Vec, = 5.25V, V AO-+V AS = OV,
CS, = CS2 = OV, CS3 = CS4 = 5.25V
lee2
Power Supply Current (3604AL)
Active
130
--
Standby
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
100
130
mA
Vee2 = 5.25V, Vee, = Open
CS, = CS2 = 0.45V, CS3 = CS4 = 2.4V
15
25
mA
CS, = CS2 = 2.5V
0.85
V
Vee = 5.0V
V
Vee = 5.0V
2.0
3624A FAMILY ONLY
Symbol
Parameter
Min.
1101
Output Leakage for High
Impedance Stage
Ise!2]
Output Short Circu it Current
-20
VO H
Output High Voltage
2.4
Typ.!'1
-25
Max.
Unit
Test Conditio ns
100
jJ.A
VO=5.25V or 0.45V,
Vee=5.25V,CS, =CS2=2.4V
-70
mA
V
NOTES: ,. Typical values are at 25° e and at nominal voltage.
2. Unmeasured outputs are open during this test.
4-37
Vo = OV, Vee = 4.75V
10H =-2.4mA, Vee = 4.75V
3604A, 3624A FAMILY
A. C. Characteristics
SYMBOL
Vee
~ +5V ±5%, TA ~ o°c to +75°C
MAXIMUM LIMITS (ns)
PARAMETER
UNIT
TEST CONDITIONS
90
ns
30
30
CS 1 = CS 2 = V IL
and CS 3 = CS 4 = V IH
to Select the PROM
ns
30
120
ns
3604A·2
3624A·2
3604A
3624A
3604AL
Address to Output Delay
60
70
ts++
Chip Select to Output Delay
30
ts--
Chip Select to Output Delay
30
tA++. tA-tA+-. t A-+
Capacitance 111 TA
~
25°C, f
= 1 MHz
LIMITS
SYMBOL
C INA
PARAMETER
Address I nput Capacitance
UNIT
TYP.
MAX.
4
10
CINS
Ch ip·Select Input Cap2citance
6
10
COUT
Output Capacitance
7
15
I
TEST CONDITIONS
pF
Vee ~ 5V
V IN
~
2.5V
pF
Vee ~ 5V
V IN
~
2.5V
pF
Vee ~ 5V
VOUT
~
NOTE ,- This parameter is only perrodica:ly samp:ed and IS not 100% tested.
Switching Characteristics
Conditions of Test:
Input pulse amplitudes· 2.5V
Input pulse rise and fall times of
5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels
Output" loading is 15 mA and 30 pF
Frequency of test· 2.5 MHz
15 rnA TEST LOAD
~',oo"
~
~600n
Waveforms
ADDRESS TO OUTPUT DELAY
CHIP SELECT TO OUTPUT DELAY
ADDRESS
INPUT
OUTPUT
t A ++
"--~
OUTPUT
4·38
2.5V
360SA, 362SA
4K (1K x 4) PROM
3605A·1,3625A·1
SOns Max.
3605A, 3625A
60 ns Max.
• Open Collector (3605A) and Three·State
(3625A) Outputs
• :t 10% Power Supply Tolerance
• Fast Access Time: 40 ns Typically
• Lower Power Dissipation: 0.14 mW/Bit
Typically
• Polycrystalline Silicon Fuse for Higher
Reliability
• Simple Memory Expansion Two Chip
Select Inputs
• Hermetic 18·Pin DIP
The Intel@ 3605A and 3625A families are high density, 4096·bit bipolar PROMs organized as 1024 words by 4 bits. The
1024 by 4 organization gives ideal word or bit modularity for memory array expansion. The 3605A has open collector
outputs and the 3625A has three·state outputs. The 3605A and 3625A are fully specified over the o·e to 75·e
temperature range with ± 10% power supply variation. Maximum access times of 50 ns (3605A·1/3625A·1) and 60 ns
(3605A/3625A) are available at a typical power dissipation of 0.14 mW/bit.
The 3605A/3625A are packaged in an 18·pin dual in·line hermetic package with 300 milli·inch centers. Thus, twice the
bit density can be achieved with the 3605A13625A in the same memory board areas as 512 by 8·bit PROMs in 24·pin
packages.
The highly reliable polycrystalline silicon fuse technology is used in the manufacturing of the 3605A and 3625A
families. All outputs are initially a logical high and logic low levels can be electrically programmed in selected bit loca·
tions.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
CS1
CS2
A,
Ci1
0.
GND
CS2
r-
Ao
A.
A,
A,
A,
A.
0,
-
0,
0,
-
As
0.
-
A.
A,
A,
-
JIg
-
-
W
0
§0
~
-
.-
-
PIN NAMES
Ao - JIg
0,
.°4
ADDRESS INPUTS
-
CHIP SELECT INPUT
OUTPUTS
64 X64 ARRAY
W
0
§c
5
-
I
I
I
I
ffi
...OW;e
~X
!!5::>
~
OUTPUT
BUFFER
I
4·39
I
0,
I
°2
I
0,
I
3605A, 3625A FAMILIES
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions.
Absolute Maximum Ratings·
'COMMENT
Temperature Under Bias ........... -65°C to +125°C
Storage Temperature ............. _65°C to +160°C
Output or Supply Voltages . . .. . . . . .. -O.5V to 7 Volts
All Input Voltages. . . . . . . . . . . . . . . . .. -lV to 5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . lOOmA
D. C. Characteristics:
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
All Limits Apply for Vee = +5.0V ±10%, T A = ODC to +75°C
limits
Typ.ll1
Max.
Unit
Test Conditions
Address Input Load Current
-0.05
-0.25
mA
Vee=5.5V, VA=0.45V
IFS
Chip Select Input Load Current
-0.05
-0.25
mA
Vee=5.5V, VS=0.45V
IRA'
Address Input Leakage Current
40
J.l.A
Vee=5.5V, V A = 5.5V
IRS
Chip Select Input Leakage
Current
40
J.l.A
Vee=5.5V, Vs = 5.5V
Symbol
IFA
Parameter
Min.
VeA
Address Input Clamp Voltage
-0.9
-1.5
V
Vee=4.5V, IA=-10mA
Ves
Chip Select Input Clamp
Voltage
-0.9
-1.5
V
Vee=4.5V,ls=-10mA
VOL
Output Low Voltage
0.3
0.45
V
Vee=4.5V, 10L =15mA
leEx
3605A Output Leakage Current
Power Supply Current
110
J.l.A
mA
Vee=5.5V, VeE=5.5V
ICC
40
140
VIL
VIH
Input "Low" Voltage
Input "High" Voltage
0.85
V
Vee=5.5V, VAO-,v A9=OV,
CS 1=CS2=VIH
V
2.0
3625,3625-1 ONLY
Symbol
Parameter
Min.
1101
Output Leakage for High
Impedance Stage
Ise[1]
Output Short Circu it Current
-20
VOH
Output High Voltage
2.4
Typ.[1]
-35
Unit
40
J.l.A
VO=5.5V or 0.45V,
Vee=5.5V, CS1=CS2=2.4V
-80
mA
Vo = OV
V
NOTES: 1. Unmeasured outputs are open during this test.
4-40
Test Conditions
Max.
10H = -2.4mA, Vee = 4.5V
3605A, 3625A FAMILIES
A. C. Characteristics
Vcc = +5V ±10%, T A = DoC to +75°C
Limits
3605A
3625A
Unit
50
60
ns
Max.
3605A·'
3625A·'
Symbol
Parameter
tA++, tA··
tA+-, tA_+
Address to Output Delay
ts++
Chip Select to Output Delay
30
30
ns
Chip Select to Output Delay
30
30
ns
ts--
Conditions
CS", =CS2=VIL
to select the
PROM.
Capacitance 111 TA = 25°C, f = 1 MHz
LIMITS
SYMBOL
PARAMETER
UNIT
TYP.
MAX.
TEST CONDITIONS
C INA
Address I nput Capacitance
3
8
pF
Vee = 5V
V IN =2.5V
C INS
Chip·Select Input Capacitance
4
8
pF
Vee = 5V
VIN = 2.5V
COUT
Output Capacitance
5
19
pF
Vee = 5V
VOUT = 2.5V
NOTE 1: This parameter
IS
only pertodically sampled and is not 100% tested.
Switching Characteristics
Conditions of Test:
Input pulse amplitudes - 2.5V
Input pulse rise and fall times of
5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 15 mA and 30 pF
Frequency of test - 2.5 MHz
15mA TEST
LOAD~VCC
300n
30pF
Waveforms
ADDRESS TO OUTPUT DELAY
CHIP SELECT TO OUTPUT DELAY
ADDRESS
INPUT
OUTPUT
OUTPUT
.-
OUTPUT
ts __
4·41
Goon
inter
3628
8K (1 K X 8) BIPOLAR PROM
3628
3628·4
80ns Max.
100 ns Max.
• Fast Access Time: 65 ns Typically
• Low Power Dissipation: O.09mW/Bit
Typically
• Four Chip Select Inputs for Easy Memory
Expansion
• Three·State Outputs
• Hermetic 24·Pin DIP
• Polycrystalline Silicon Fuses for Higher
Fuse Reliability
The Intel$ 3628 is a fully decoded 8192·bit PROM organized as 1024 words by 8 bits. The worst case access time of 80
ns is specified over the O·C to 75·C temperatue range and 5% Vee power supply tolerances. There are four chip
selects provided to facilitate expansion into larger PROM arrays. It uses Schottky clamped TTL technology with polycrystalline silicon fuses. All outputs are initially high and logic low levels can be electrically programmed in selected
bit locations.
Prior to the 8192 bit 3628, the highest density bipolar PROM available was 4096 bits. The high density of the 3628 now
easily doubles the capacity without an increase in area on existing designs currently using 512 words by 8 bit PROMs.
There is also little, if any, penalty in power since the 3628 power/bit is approximately one·half that of 4K PROMs. The
3628 is packaged in a hermetic 24-pin dual in·line package.
PIN CONFIGURATION
BLOCK DIAGRAM
DATA OUT 1
DATA OUT 8
Vee
A.
A. (MSB)
CS.
17
0. (MSB)
~
0.
00
GND ' -_ _ _.....11_°.
·PROGRAMMING PIN
PIN NAMES
ADDRESS INPUTS
A.-""
CS, - cs,}CHIP SELECT INPUTS(1I
CS 3 - CS._
OATA OUTPUTS
0, -08
-
[1 J To select the PROM CSt = CS 2 .. V1L
and CS3 "" CS 4 = V 1H
4·42
LOGIC SYMBOL
3628
PROGRAMMING
The programming specifications are described in the PROM programming section of the Data Catalog.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ........... -65°C to +125°C
Storage Temperatu re . . . . . . . . . . . .. -65°C to + 1600 C
Output or Supply Voltages . . . . . . . .. -0.5V to 7 Volts
All Input Voltages .................. -lV to 5.5V
Output Currents ....................... 100mA
D.C. CHARACTERISTICS:
'COMMENT
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
All Limits Apply for Vee= +5.0V±5%, TA=O°C to + 75°C
Limits
Typ.11 J
Max.
Unit
Test Conditions
IFA
Address Input Load Current
-0.05
-0.25
mA
Vee=5.25V, V A =0.45V
I FS
Chip Select Input Load Current
-0.05
-0.25
mA
Vee=5.25V, Vs =0.45V
IRA
Address Input Leakage Current
40
i-,,,"',"''''''.'
""'"""",,"
Data
Column
,'f,'" ;.,
Punch a T
Blank
Customer Company Name
Blank
Customer's Company Division or location
Blank
Customer Part Number
Blank
Punch the Intel 4-digit basic part number and
in ( ) the number of output bits; e.g., 2708
(81. 2316(8), or 3605(4)
Blank
Chip number for ROMs with programmable
chip select inputs. If not applicable, leave
blank.
Blank
Punch a 2-digit decimal number to indicate
truth table number. The first truth table
will be 00, second 01, third 02, etc.
Title Card Format.
For a N words X 4·bit organization only, cards 2 and
those following should be punched as shown. Each card
specifies the 4·bit output of 14 words.
LSBDECIMAL WORD
ADDRESS BEGINNING
EACH CARD
JIIISBi
14 DATA FIELDS
,.-L-,
/J,IOOiJ
F'ttPt"i
Ntif~ti
I
Column
1-5
DECIMAL NUMBER
INDICATING THE
TRUTH TABLE NUMBER
,l,
f'f'F'P f1t11'fF' PF'tilf Nt"iPP F'F'PI'f Pf'tPff f'PNl1 ItH'P Pltltlt H'PF' NNPP
Pftl~P
00
1111 III. III' 1111 '11' III' .11' .111 1111 1111 1111 1111 III' .11.
~ ~~~~ ~ ~ ~ ~ ~ ~ I~'~ ~,~ I~ ~ I~ ~ ~I~I ~1~ ~ ~! ~ !~!! ~I!! ~I: ~! ~!! ~l~ ~HOI!~ ~I~!!~ ~ ~l ~ ~~ ~!~ !~I ~I~~' ~\~ ~I~I~I ~I ~~! ~l~' ~s ~I ~I ~I~!
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2222222221112
n
22 2 2222 2 2 i2 12
n
12 22 2 Z2 2 2 2 2 2 2 2 2 12 2 2 2 222 2 2 222 2 n 2 2 12 2 22 2 2 2 2 2 2 2 2 2 lZ 2
lJ1J3133J1JJ333JJlJJJ3ll1l1331J333331131J3J3JJ3111J311]1]1311111Jl]311JlllJ1J31J
4 ~ 4 44
~4
4 4 44 U 4 44 U 44 '4 U (4'
111 ~ IU
4 H 4 4 4 44 44 4 4 4 4 44 4 44 44 44 4 4 4444 44 4 4 444 44 44 4 44 U 4
55555 S 5'5 IS 11115 5 5 5 S 51115 5 ~ "Ill II) 5 5 5 S51 551515551151555 S 51115 :i 5 5 5 5115 5 5 511 ~ 5 5 5 5 5
; 6 6 6£ 6 666666666 t 6 H 6 6 6611 E5 6 H 56 6 65 6 i 6 6 5 6 6 6 6 6 6 6 6 6 0 ~ 6 6 6 6 06 56 6 i 6066 S 6 60 6 S& 6 6 6 6 G~ 6 ti 6
11"""";; '" 1111111' "'11""'11'111""1"11,,"111"""1111"'11"""'" 1
e8 8 ~ 8 8 8 aa8 8 BB 8 Bi 8 8 8 8 8 8 8 8 a8 8 B8 B&8 6 e8 8 Ba8 8 B8 a888888888 B8 8 8 8 888888 B8 8 8 B8 8 8 8 8 8 8 B8 8 a8
4·54
6
7-10
11
12·15
16
17·20
21
22·25
26
27-30
31
32-35
36
3740
41
4245
46
47-50
51
52-55
56
57-60
61
62-65
66
67·70
71
72-75
76-78
79-80
Data
Punch the 5 digit decimal equivalent of the
binary coded location which begins each
card. The address is right justified, i.e.,
00(100, 00~14, 00028, etc.
Blank
Data Field
81ank
Data Field
Blank
Data Field
·Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Data Field
Blank
Punch same 2 digit decimal number as In
title card.
For a N words X 8-bit organization only, cards 2 and
those following should be punched as shown. Each card
specifies the 8-bit output of 8 words.
Column
1-5
MSB _LSBDECIMAL WORD
ADDRESS BEGINNING
EACH CARD
8 DATA FIELDS
6
7-14
15
16-23
24
25-32
33
34-41
42
43-50
51
52-59
60
61-68
69
70-77
78
79-80
DECIMAL NUMBER
INDICATING THE
TRUTH TABLE NUMBER
n
,-L,
11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111
11111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000000000000000000000000000000000000000000000000 0 00"
1 ) ) " I ' '1"""';""';""'ll',,"),""I'''''l1lO)'11111')1313Il1 11""'I"".,'''I''''\'\L\1\)I'\\\'lillll&OilI1IJI--...-II...>--top ~ I
· I - - - - - tCYC
I
r---(NOTE 2)
(SEE FIG. 2 FOR DETAILS)
veel::::JUL~~~JL
'==10V
OUTPUT 1
o.45V
(MAX)
"5V
r1
~
I-----..n~-----
nL,
2Z
tPROGRAMMED 0 {NOTE 11
OUTPUT2 '::~-~'~2-~'~2-~
II
l~
L
PROGRAMMEO 0(NOTE 1)
OU~U4::(~::~-------~2J1""'-------~2)l,
2JLJL
l
O.45V (MAX)
LPROGRAMMEO 0 (NOTE 1 I
Figure 1. Programming Cycles.
NOTES: 1. ~:~;:~~::~::~g~T0~~u~~~~~~~':v~~~E~~~8~::N~E~~OA:T~:~ ~~~:~ ~~~~ AND PRIOR TO Vee RISING TO 12.SV.
2. AFTER THE LAST BIT HAS BEEN PROGRAMMED, 128 ADDITIONAL VERIFICATIONS ARE REQUIRED FOR EACH OUTPUT TO
BE CORRECTLY PROGRAMMED.
3. AFTER THE 128 PROGRAM VERIFICATIONS. A FINAL 2.5 ms Vee AND CS PULSE SHOULD BE APPLIED WHILE SIMULTANEOUSLY
ENABLING THE CURRENT SOURCES TO ALL OUTPUTS WHICH ARE TO BE PROGRAMMED.
12.5V
Vee
5V
5V
4.SV
'D
;,..V
\
os
OV
.. ,ov
OUTPUT 1
-5V
I\.
I \
---.I
/
'--
. . ----------.1
'----------------4;~
UNPROGRAMMED BIT
~10V
OUTPUT 2
!\
-~---------------------.I
~------~l~l--------------------------------
J\
"'10V
OUTPUT N
_5V
----------------------------------------------~l
Figure 2. Programming Cycle Details.
4-77
~--------------------------------
{al RAMP TIME IN PROGRAMMING 8 OUTPUTS
(bl RAMP TIME IN PROGRAMMING 4 OUTPUTS
tpw
tpw
0.2
0.2
100
200
300
400
500
600
700
BOO
100
PROGRAMMING ELAPSED TIME (msl
Figure 3.
200
300
400
500
600
PROGRAMMING ELAPSED TIME (ms}
Vee Pulse Width vs. Programming Time.
4·78
700
800
Memory Support
5
MEMORY SUPPORT CIRCUITS
Electrical Characteristics
Over Temperature
Type
Description
No.
of
Pins
Input
to
Output
Delay Max.
Power
Dissipation[1 J
Maximum
Supplies, V
Page
No.
3205
1 of 8 Binary Decoder
16
18 ns
350 mW
+5
5·3
3207A
Quad Bipolar to MOS Level
Shifter and Driver
16
25 ns
900 mW
+ 5,+ 16,+ 19
5-7
3207A-1
Quad Bipolar to MOS Level
Shifter and Driver
16
25 ns
1040 mW
+5,+ 19,+22
5-11
3222
4K Dynamic RAM Refresh Controller
22
-
600 mW
+5
5-13
3232
4K Dynamic RAM Address
. Multiplexer and Refresh Counter
24
20 ns
750 mW
+5
5·19
3242
16K Dynamic RAM Address
Multiplexer and Refresh Counter
28
20 ns
825 mW
+5
5·23
3245
Quad TIL to MOS Driver for
4K RAMs
16
32 ns
388 mW
+ 12,+5
5-27
3404
High Speed 6-Bit Latch
16
12 ns
375 mW
+5
5-3
Note 1. Power Dissipation calculated with maximum power supply current and nominal supply voltages.
5-2
inter
3205,3404
3205 HIGH SPEED 1 OUT OF 8 BINARY DECODER
3404 HIGH SPEED 6-BIT LATCH
Max. Delay Over O°C to 75°C
• 18ns
Temperature: 3205
Max. Data to Output Delay
• 12ns
Over 0° C to 75° C
• Low Input Load Current: .25mA Max.,
1/6 Standard TTL input Load
Line Reflection: Low
• Minimum
Voltage Diode Input Clamp
Outputs Sink 10mA Min.
• 16-Pin
Dual In-Line Package
•
• Simple Expansion: Enable Inputs
Temperature: 3404
Compatible With DTL and
• Directly
TTL Logic Circuits
• Totem-Pole Output
3205
The 3205 decoder can be used for expansion of systems which utilize memory components with active low
chip select input. When the 3205 is enabled, one of its eight outputs goes "low", thus a single row of a memory
system is selected. The 3 chip enable inputs on the 3205 allow easy memory expansion. For very large memory
systems, 3205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory expansions.
3404
The Intel 3404 contains six high speed latches organized as independent 4-bit and 2-bit latches. They are
designed for use as memory data registers, address registers, or other storage elements. The latches act as high
speed inverters when the "Write" input is "low".
The Intel 3404 is packaged in a standard 16-pin dual-in-line package; and its performance is specified over the
temperature range of O°C to +75°C, ambient. The use of Schottky barrier diode clamped transistors to obtain
fast switching speeds results in higher performance than equivalent devices made with a gold diffusion process.
PIN CONFIGURATION
3205
.,
'.
3404
Vee
D,
"
"
"
Vee
0,
D,
D6
0,
1/8 BINARY
DECODER
D,
D,
0,
E,
0,
W,
GRD
GRD
5-3
D.
3205, 3404
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias:
Ceramic
Plastic
'COMMENT
-65°C to +125°C
-65°C to +75 0 C
Stresses above those listed under "Absolute Maximum Rat·
ing" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at
any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
-65°C to +160o C
Storage Temperature
All Output or Supply Voltages
-0.5 to + 7 Volts
All Input Voltages
-1.0 to +5.5 Volts
Output Currents
125 mA
D.C. CHARACTERISTICS
3205,3404
SYMBOL
PARAMETER
MIN.
LIMIT
MAX.
-0.25
UNIT
TEST CONDITIONS
IF
INPUT LOAD CURRENT
IR
INPUT LEAKAGE CURRENT
10
fJA
Vee = 5.25V, VR = 5.25V
Vc
INPUT FORWARD CLAMP VOLTAGE
-1.0
V
Vee - 4.75V, Ie - -5.0 mA
VOL
OUTPUT "LOW" VOLTAGE
VOH
OUTPUT HIGH VOLTAGE
V1L
INPUT "LOW" VOLTAGE
V 1H
INPUT "HIGH" VOLTAGE
Isc
OUTPUT HIGH SHORT
CIRCUIT CURRENT
Vox
OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT
mA
0.45
2.4
0.85
2.0
-40
-120
0.8
Vee = 5.25V, V F = 0.45V
= 4.75V, 10L - 10.0 mA
V
Vee
V
Vee = 4.75V, 10H- -1.5 mA
V
Vee = 5.0V
V
Vee = 5.0V
mA
Vee = 5.0V, VOUT = OV
V
Vee = 5.0V, lox
= 40 mA
Vee = 5.25V, Outputs Open
POWER SUPPLY CURRENT
3404 ONLY
Ice
POWER SUPPLY CURRENT
75
mA
Vee = 5,25V, Outputs Open
Irwl
WRITE ENABLE LOAD CURRENT
PIN 7
-1.00
mA
Vee =5.25V, Vw =0.45V
IFW2
WRITE ENABLE LOAD CURRENT
PIN 15
-0.50
mA
Vee =5.25V, Vw =0.45V
IRW
WRITE ENABLE LEAKAGE CURRENT
10
fJA
VR 5.25V
TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
100
TA '" 25"C __
80
~
Vee" 5.0V
~
TA=OoC~
TA '" DOC
1#
60
!.11
VJj. 1';;" 25"C
I
-10
DATA TRANSFER FUNCTION
5.0
r- ~cc J50~
J....."
TA '" 75°C
~U
TA " 75"C~
20
~
/.~
'"
.M r--.2
TA '"
I
-30
~~
aoc
OUTPUT "LOW' VOLTAGE (V)
Mf.-\
1--1
A
1.0
\
-.1
1
1.0
I
-50
1.0
TA "'75°C
J
TA =25"C
.4
TA '" 25"C
2.0
I
-40
r-rT A '" DOC
3.0
J
40
1
= 5 0V
TA '" 75"C
/I
-20
Vc~
4.0
\.. ~ ~
2.0
3.0
4.0
OUTPUT "HIGH" VOLTAGE (V)
5-4
5.0
o
.2
.4
.6
.8
1.0
1.2 1.4 1.6 1.8 2.0
INPUT VOL TAGE (V)
3205, 3404
3205 HIGH SPEED 1 OUT OF 8 BINARY DECODER
SWITCHING CHARACTERISTICS
CONDITIONS OF TEST:
TEST LOAD:
39011
Input pulse amplitudes: 2.5V
Input rise and fall times: 5 nsec
between 1V and 2V
Measurements are made at 1.5V
All Transistors 2N2369 or Equivalent. CL ::: 30 pF
TEST WAVEFORMS
ADDRESS OR ENABLE
INPUT PULSE
~1-"HI~_____---______l:~:f."---
______________ J~'. \~ _______________ _
OUTPUT
A.C. CHARACTERISTICS
TA = OOC to +75°C, Vcc = 5.0V ±5% unless otherwise specified.
PARAMETER
SYMBOL
MAX. LIMIT
UNIT
18
ns
18
ns
18
ns
t++
ADDRESS OR ENABLE TO
OUTPUT DELAY
C+
4
18
C_
INPUT CAPACITANCE
<1N (11
1. This parameter
IS
4(typ.)
5(typ.)
P3205
C3205
TEST CONDITIONS
ns
pF
pF
f = 1 MHz. Vcc = OV
VBIAS = 2.0V. TA = 25°C
penodlcally sampled and IS not 100% tested.
TYPICAL CHARACTERISTICS
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE
20,-----,----,---,----,
20 ,-----,----..,1-.---,
Vee;; 5.0V
TA ;; 2SOC
g
......
w
15
a:
0
vee" S.ov
c L ;; 30 pF
15
15r---~~--_+---~
'-.
10
10~==t===~===1
'
..
Ii!
w
a:
..
0
0
50
100
1S0
oL---~---~---~
o
200
25
50
AMBIENT TEMPERATURE {OCI
LOAD CAPACITANCE (pFI
5-5
75
3205,3404
3404 6-BIT LATCH
SWITCHING CHARACTERISTICS
Vcc
TEST LOAD:
CONDITIONS OF TEST:
390(2
Input pulse amplitudes: 2.5V
Input rise and fall times: 5 nsec
between lV and 2V
:rF
Measurements are made at 1.5V
'":
MEASUREMENT FOR OATA OELAY
OATA
INPUT
":'" All Transistors 2N2369 or Equivalent. CL == 30pF
TEST WAVEFORMS
\
---~I"------------------~
WRITE
ENABLE
OUT
OUT
NOTE 1: Output Data
IS
SYMBOL
~
________________________ .1"
-1-'WI"O"~
~~~~~;:~;-------------
----------"
NOTE 2' Output Data
valid after t+_. t_+
A.C. CHARACTERISTICS
MEASUREMENT FOR WRITE ENABLE DELAY
DATA
INPUT
WRITE
ENABLE
IS
PARAMETER
MIN.
LIMITS
TYP.
UNIT
MAX.
t+_,t_+
DATA TO OUTPUT DELAY
12
ns
WRITE ENABLE TO OUTPUT DELAY
17
ns
'SET UP
TIME DATA MUST BE PRESENT BEFORE
RISING EDGE OF WRITE ENABLE
'HOLD
TIME DATA MUST REMAIN AFTER
RISING EDGE OF WRITE ENABLE
C'NW {31
valid after t __ , t_+
TA = OOC to +75°C, VCC= 5.0V ±5%; unless otherwise specified.
t __ .t_+
'WP
C ,ND {31
":"
12
ns
8
ns
i
WRITE ENABLE PULSE WIDTH
15
DATA INPUT CAPACITANCE
WRITE ENABLE CAPACITANCE
TEST CONDITIONS
ns
P3404
4
pF
C3404
5
pF
VBIAS = 2.0V. TA =250 C
P3404
7
pF
f - 1 MHz. VCC = OV
C3404
8
pF
VBIAS = 2.0V. TA = 25°C
f - 1 MHz. VCC = OV
NOTE 3: This parameter is periodically sampled and is not 100% tested.
TYPICAL CHARACTERISTICS
DATA INPUT, WRITE ENABLE
TO OUTPUT DELA Y VS.
AMBIENT TEMPERATURE
DATA INPUT, WRITE ENABLE
TO OUTPUT DELAY VS.
LOAD CAPACITANCE
WRITE ENABLE PULSE WIDTH
VS. LOAD CAPACITANCE
20
20r-----,-----,-----,---~,
20
J
..
.
w
w
~
<
15
<
.....
15
WRITE ENABLE t -
- --
w
....
~
15
15
w
i<
TA "'25"C
I
~
15
Vee:: S.ov
Vee S.OV
Ct"'JOpF
....
i<
~
10
.....
~
~
<
....
<
Q
<
....
<
Q
10
DATAJR WRITE
~
~
DATA t+_
o
100
200
300
LOAD CAPACITANCE (pFI
400
10
ENA~LE c+
o
o
25
50
AMBIENT TEMPERATURE lae)
5-6
75
o
100
~
200
V
300
LOAD CAPACITANCE (pFI
400
infer
3207A
QUAD BIPOLAR-TO-MOS
LEVEL SHIFTER AND DRIVER
• High Speed, 45 nsec Max. - Delay
+ Transition Time Over Temperature
with 200 pF Load
• TTL and DTL Compatible Inputs
• 1103 and 1103A Memory Compatible
at Output
• Simplifies Design - Replaces
Discrete Components
• Easy to Use - Operates from Standard
Bipolar and MOS Supplies
• Minimum Line Reflection - Input and
Output Clamp Diodes
• High Input Breakdown Voltage 19 Volts
• CerDIP Package - 16 Pin DIP
The 3207A is a Quad Bipolar-to-MOS level shifter and driver which accepts TTL and DTL input signals, and
provides high output current and voltage suitable for driving MOS circuits. It is particularly suitable for driving
the 1103 and 1103A memory chips. The circuit operates from a 5 volt TTL power supply, and Vss .and Vas
power supplies from the 1103 and 11 03A.
The device features two common enable inputs per pair of devices which permits some logic to be done at their
inputs, such as cenable and precharge decoding for the 1103 and 11 03A.
For the TTL inputs a logic "1" is VIH and a logic "0" is VIL. The 3207A outputs correspond to a logic "1" as
VOL and a logic "0" as VOH for driving MOS inputs.
The 3207A is packaged in a hermetically sealed 16 pin ceramic dual-in-line package. The device performance
is specified over the same temperature range as the 1103 and 11 03A, i.e. from OOC to +70°C.
PIN CONFIGURATION
LOGIC SYMBOL
01
vee
OUTPUT
OATAINPUT
ENABLE INPUT
ENABLE INPUT
OATAINPUT
OUTPUT
°1
E1
OUTPUT
E2
OATAINPUT
O2
°2
ENABLE INPUT
ENABLE INPUT
03
OATAINPUT
03
E3
OUTPUT
E4
04
5-7
°4
3207A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ......... oDe to +70 o C
Storage Temperature ........... -65°C to +160 o C
All Input Voltages and VSS' ......... -1.0 to +21V
Supply Voltage Vcc ............... -1.0 to + 7V
All Outputs and Supply Voltage
Vss with respect to GND . . . . . . . .. -1.0 to +25V
Power Dissipation at 25°C ............ 2 Watts III
'COMMENT
Stresses above those listed under"Absolute Maximum Ratings"may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(1) Refer to the graph of Junction Temperature versus Total Power Dissipation on page 5-10 for other temperatures.
D.C. CHARACTERISTICS TA ~ ooe to 70°C, Vcc~ 5V ± 5%, Vss = 16V ± 5%, Vss - Vss= 3.0V to 4.0V
LIMIT
UNIT
CONDITIONS
-·0.25
mA
V o " .45V. Vee" 5.25V. All Other Inputs
at 5.25V. Vss " 16V. Vee" 19V
-0.50
mA
VE " .45V, Vee" 5.25V, All Other Inputs
at 5.25V, V ss " 16V, Vee" 19V
SYMBOL
TEST
I FO
DATAINPUTLOADCURRENT
IFE
ENASLE INPUT LOAD CURRENT
IRD
DATA INPUT LEAKAGE
CURRENT
20
ENASLE INPUT LEAKAGE
CURRENT
20
I-
MIN.
MAX.
-:0
IRE
VOL
I
OUTPUT "LOW" VOLTAGE
OUTPUT "HIGH" VOLTAGE
Vo
=:
19V, Vee= 5.0V, AI! Other Inputs
Grounded, Vss " 16V. Vee" 19V
Il A
.8
VlOoCI
IOL "500IlA, Vee" 4.75V
VI250CI
V{70oCI
Vss" 16V. Vee" 19V
Vss '- .7
Vss -.6
VlOoCI
Vss -.5
V{70oCI
V OH {MAX.!
V E " 19V, Vee" 5.0V. All Other Inputs
Grounded, V ss " 16V, Vee" 19V
.7
.6
V OH IMIN.!
~A
V{25OCI
VSS + 1.0
V
IOL
OUTPUT SINK CURRENT
100
mA
IOH
OUTPUT SOURCE CURRENT
-100
mA
V'L
INPUT "LOW" VOLTAGE
V,H
INPUT "HIGH" VOLTAGE
All Inputs at 2.0V
IOH" -500jJA. Vee" 5.0V
Vss" 16V. Vee" 19V
All Inputs at 0.85V
IOH" 5mA, VCC" 5.0V
VSS" 16V, VSS ~ 19V
Va "4V, Vee" 5.0V,V ss " 16V,
Vee" 19V, VE~ Vo" 2.0V
Va" Vss -4V, Vee" 5.0V, Vss " 16V
Ves" 19V, VE Vo " 0.85V
0
C'N
I
1.0
2.0
INPUT CAPACITANCE
8{Typicall
V
Vee" 5.0V, Vss " 16V, Vee" 19V
V
Vee" 5.0V, V ss " 16V, Ves" 19V
pF
V SIAS " 2.0V, Vee" OV
POWER SUPPLY CURRENT DRAIN:
All Outputs "Low"
Symbol
ICC
Min,
Parameter
Current trom
Max.
Unit
Vee
83
mA
Conditions
VCC" 5.25V, VSS" 16.8V, VSS" 20.8V
ISS
Current from VSS
250
J1A
ISB
Current from V BB
21
mA
PTOTAL
Total Power Dissipation
900
mW
All I nputs Open
All Outputs "High"
ICC
Current from
Vee
33
mA
ISS
Current from V S5
250
Il A
ISS
Current from V BB
3
mA
PTOTAL
Total Power Dissipation
250
mW
Standby CondItion with VCC
=:
OV, VSS
ICC
0
mA
ISS
Current from V SS
250
Il A
Current from V BB
250
Il A
ISB
0
20.8V
All Inputs Grounded
=- V aB
Current from V CC
PTOTAL
VCC" 5.25V, VSS" 16.8V, VSS
Total Power Dissipation
10
5-8
VCC" OV, VSS" 16.8V, V SB "16.8V
mW
3207A
SWITCHING CHARACTERISTICS
A.C. CHARACTERISTICS
= O°C to 70°C, Vcc = 5V ±5%, Vss = 16V ±5%,
TA
Vss
= Vss +3 to 4V, f = 2 MHz, 50% Duty Cycle
LIMITS (ns)
SYMBOL
DELAY DIFFERENTlALlll
TEST
C L =100pF
MIN.
MAX.
(1)
CL = 200 pF
MIN.
MAX.
C L = 200 pF
MAX.
t+_
INPUT TO OUTPUT DELAY
5
15
5
15
5
t_+
INPUT TO OUTPUT DELAY
5
25
5
25
10
10
tr
OUTPUT RISE TIME
5
20
5
30
tf
OUTPUT FALL TIME
5
20
10
30
10
to
DELAY + RISE OR FALL TIME
10
35
20
45
10
This is defined as the maximum skew between any output in the same package, eg., all the input to output delays for the
t_+ parameter are within a maximum of 10 nsec of each other in the same package.
WAVEFORMS
OUT
~""'--+tr
IN
GND
TYPICAL CHARACTERISTICS
SWITCHING TIME VS.
AMBIENT TEMPERATURE
SWITCHING TIME VS.
LOAD CAPACITANCE
40
40r---r---~--.----'
I.
vee""
Vee =5.0V
5.0V
vss '"
16V
30 - v ss " 19V
cL
= 200 pF
20
10
o
Vss "16V
Vss "19V
30
-
-
TA
---t----t----/
=25°C
t,
-
20 f----t---+-:"....~
..-t_+
I,
-t+_
oL-_ _L -_ _
o
20
40
.,.P---"'---j
1,
60
o
80
AMBIENT TEMPERATURE (Oel
100
~
200
__
~
300
LOAD CAPACITANCE (pF)
5·9
_ _- '
400
3207A
POWER AND SWITCHING CHARACTERISTICS
POWER CONSUMED IN CHARGING AND
DISCHARGING LOAD CAPACITANCE
OVER OV TO 16V INTERVAL
NO LOAD D.C. POWER DISSIPATION VS.
OPERATING DUTY CYCLE
1.0 r---------,.--------~--------....,..------__,
.2r-----------------~----~----~--~~
Vee -5V
Vss =16V± 6%
.1
g
.06
"'z
:;:
.04
f:?
§
U
a::
.75
~
z
0
;::
«
!w
...
u
'"~ zi:!
0
w
:; ~
::> «
'"0z
V•• =VSS +3to4V
.08
0
«
u
iii
.02
15
.50
a::
w
~
.01
...
.008
0
0
t.i
w
3:
...0
.004
.2
.4
.6.8
6
1
8 10
oL-------~--------~------~--------j
o
60
75
SWITCHING DUTY CYCLE (%)
FREQUENCY OF SWITCHING (MHz)
POWER =CV 2 f
WORST CASE LOAD CAPACITANCE
ON EACH OUTPUT VS.
FREQUENCY OF SWITCHING
JUNCTION TEMPERATURE VS. TOTAL
POWER DISSIPATION OF THE CIRCUIT
~0r--------'--------~----~--....,..--------'
OPERATING IN THIS REGION IS NOT
RECOMMENDED
50~----~~----~~-+--------~--------1
0.6
1.0
1.5
2.0
TOTAL POWER DISSIPATION OF THE CIRCUIT (W)
TOTAL POWER = D.C. POWER + POWER CONSUMED IN
CHARGING AND DISCHARGING LOAD CAPACITANCE.
FREQUENCY OF SWITCHING (MHz)
5·10
100
inter
3207A-1
QUAD BIPOLAR-TO-MOS
LEVEL SHIFTER AND DRIVER
• Power Supply Voltage Compatible
with the High Voltage 1103-1
• 1103-1 Memory Compatible
at Output
The Intel 3207 A-1 is the high voltage version of the standard 3207 A, and is compatible with the 1103-1. The
3207A-1 has all the same features as the standard 3207A. The absolute maximum ratings and pin configuration
are repeated below for convenience, while the DC and AC characteristics appear below and on the next page.
PIN CONFIGURATION
OUTPUT
DATA INPUT
ENABLE INPUT
ENABLE INPUT
DATA INPUT
ABSOLUTE MAXIMUM RATINGS*
LOGIC SYMBOL
Temperature Under Bias . . . . . . . . . . oOe to +55°e
Storage Temperature . . . . . . . . . . . -65o e to +160 o e
All Input Voltages . . . . . . . . . . . . -1.0 to +21 Volts
Supply Voltage Vcc . . . . . . . . . . . -1.0 to +7.0 Volts
All Outputs and Supply Voltages VBB and Vss
with respect to GND . . . . . . . . . . . -1.0 to +25 Volts
Power Dissipation at 25°C . . . . . . . . . . . . . . . 2 Watts
OUTPUT
DATA INPUT
ENABLE INPUT
ENABLE INPUT
DATA INPUT
COMMENT:
OUTPUT
OUTPUT
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of this specification is not implied, Exposure to absolute maxi·
mum rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTICS
SYMBOL
TA = oOC to 55°C, Vee = 5V ± 5%,Vss =19V ± 5%, VsB -VSS = 3.0V to4.0V
TEST
LIMIT
MIN.
MAX.
UNIT
CONOITIONS
IFD
DATA INPUT LOAD CURRENT
-0.25
mA
V D .45V, Vee~ 5.25V, All Other Inputs
at 5.25V. VSs~ 19V,VBB~ 23V
IFE
ENABLE INPUT LOAD CURRENT
-0.50
mA
VE ~ .45V. Vee~ 5.25V. All Other Inputs
at 5.25V, VSSo 19V, VBB~ 23V
IRD
DATA INPUT LEAKAGE
CURRENT
20
I"A
V D ~ 19V, Vee~ 5.0V, All Other Inputs
Grounded, VSS = 19V, VBB ~ 23V
IRE
ENABLE INPUT LEAKAGE
CURRENT
20
pA
V E = 19V, Vee= 5.0V, All Other Inputs
Grounded, VSS ~ 19V, VBB~ 23V
VOL
OUTPUT "'LOW·· VOLTAGE
0.8
VlOoCI
IOL ~ 500/lA, Vee~ 4.75V
0.7
0.6
V(25OCI
VSS~ 19V, VBB~ 23V
V OH (MIN.J
OUTPUT ··HIGH·· VOLTAGE
V(550CI
Vss -0.7
Vss -0.6
VlOoCI
Vss -0.5
V(550CI
V OH (MAX.J
V(25OCI
VSS + 1.0
V
0
All Inputs at 2.0V
IOH~ -500~A, Vee" 5.0V
Vss ~ 19V. VBB~ 23V
All Inputs at O.85V
IOH 5mA, VCC ~ 5.0V
VSS ~ 19V, V BB
23V
0
0
IOL
OUTPUT SINK CURRENT
100
mA
Vo ~ 4V. Vee~ 5.0V.V ss " 19V.
VBB~23V, VE~ Vo~ 2.0V
IOH
OUTPUT SOURCE CURRENT
-100
mA
Vo ~ Vss -4V, Vee - 5.0V, Vss ~ 19V
V,L
INPUT ··LOW'· VOLTAGE
V,H
INPUT ·'HIGH·· VOLTAGE
C'N
INPUT CAPACITANCE
VBB~
1.0
2.0
8(Typical)
5-11
23V. V E ~ Vo ~ 0.85V
V
Vee~ 5.0V, Vss~ 19V. VBB~ 23V
V
Vee - 5.0V. VSS~ 19V, VBB~ 23V
pF
V B1AS
2.0V,
Vee~
OV
._-
3207A-1
D.C. CHARACTERISTICS (Cant'd)
TA
~ DOC to +55°C, Vee ~ 5V ± 5%, Vss ~ 19V ± 5%, V88 -Vss ~ 3.0V to 4.0V
POWER SUPPLY CURRENT DRAIN:
All Outputs "low"
Symbol
Max.
Unit
ICC
Current from
Vee
83
mA
ISS
Current from VSS
250
/lA
25
mA
1040
mW
Parameter
Min.
'88
Current from V SS
PTOTAL
Total Power Dissipation
Conditions
Vee 0 5.25V. Vss
= 20V. VS8 = 24V
All I nputs Open
All Outputs "High"
ICC
Current from
Vee
33
mA
ISS
Current from VSS
250
/lA
'B8
Current from V aB
5
mA
PTOTAL
Total Power Dissipation
297
mW
Standby Condition with
Vee:O;
OV,
Vss
=0
V BS
'ee
Current from
Vee
0
mA
ISS
Current from VSS
500
/lA
Vas
500
/lA
Current from
'SS
15
Total Power Dissipation
PTOTAL
Vee 0 5.25V. Vss 0 20V. V880 24V
All Inputs Grounded
Vee 0 OV. VSS
=
20V. VSS 0 20V
mW
A.C. CHARACTERISTICS
TA = DOC to 55°C, Vee = 5V ±5%, Vss
19V ±5%, VS8 = Vss +3 to 4V, f = 2 MHz, 50% Duty Cycle
LIMITS (ns)
SYMBOL
TEST
C L = 100 pF
MIN.
(1)
MAX.
CL = 200 pF
MIN.
DELAY DIFFERENTlAL I1 )
C L = 200 pF
MAX.
MAX.
t+~
INPUT TO OUTPUT DELAY
5
15
5
15
t~+
INPUT TO OUTPUT DELAY
5
5
25
5
10
tr
OUTPUT RISE TIME
5
25
20
5
30
10
tf
OUTPUT FALL TIME
5
DELAY + RISE OR FALL TIME
10
20
35
45
10
tD
25
35
10
10
This is defined as the maximum skew between any output in the same package, eg., all the input to output delays for the
t ..+ parameter are within a maximum of 10 nsec of each other in the same package.
WAVEFORMS
OUT
IN
GND
5·12
inter
3222
REFRESH CONTROLLER FOR 4K DYNAMIC
RANDOM ACCESS MEMORIES
• Ideal for use in 2107A, 2107C Systems
• Adjustable Refresh Timing Oscillator
• Simplifies System Design
• 6-Bit Address Multiplexer
• Reduces Package Count
• 6-Bit Refresh Address Counter
• Standard 22-Pin DIP
• Refresh Cycle Controller
The Intel® 3222 is a refresh controller for dynamic RAMs requiring refresh of up to 6 input addresses (or 4K bits for 64 x 64
organization). The device contains an accurate refresh timer (whose frequency can be set by an external resistor and
capacitor), plus all necessary control and 1/0 circuitry to provide for the refresh requirements of dynamic RAMs. The chip's
high performance makes it especially suitable for use with high speed N-channel RAMs like the Intel® 2107e. The 3222 is well
suited for asynchronous dynamic memory systems.
The 3222 operates from a single +5 volt power supply and is specified for operation over a ooe to 75°e ambient temperature
range. It is fabricated by means of Intel's highly reliable Schottky bipolar process.
BLOCK DIAGRAM
PIN CONFIGURATION
VCC
Rx/ex
ACK
ADDRESS
INPUTS
6
lAo As I
REFON
~:X
BUSY
A3
A.
~
A5
n
XI
C
2 INPUT
6 CHANNEL
ADDRESS
MULTIPLEXER
6BlT
REFRESH
COUNTER
-=-
05
04
TIMER
CONTROL
...._ _ _ _r 0 3
~
=0 (° .°
ADDRESS
OUTPUTS
0
5)
IClOCK
SELECT
:
I
PIN NAMES
REFREQ
Ao-AS
ACK
ADDRESS INPUTS
ACKNOWLEDGE
00 . Os
ADDRESS OUTPUTS
a
OUTPUT
BUSY INPUT
INTERNAL REFRESH
REQUEST LATCH OUTPUT
BUSY
REFON
CVREO CYCLE REQUEST
INPUT
AHREQ
REFRESH ON OUTPUT
REFRESH REQUEST INPUT
RxCx
STARTCY
Ae TIE POINt
STARTCVCLE OUTPUT
Vee
+5V SUPPLY
,-
STARTCY
CONTROL
ACK
5-13
3222
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Temperature Under Bias .•.•.•.•.... _65° to +125°C
Storage Temperature •..•••••..•••• _65° to +160°C
All Input, Output or Supply Voltages .••. -O.5V to +7V
All Input Voltages ...•••••••.••..• -1.0V to +5.5V
Output Currents . . . • • . • . . . . . . . . . • . . • .. 100 mA
Power Dissipation . . . • . . . . . . . . . . . . . . . . . . . . 1 W
D.C. CHARACTERISTICS All Limits Apply for VCC = +5.DV ±5%, TA = DOC to +75°C.
Limits
Symbol
Parameter
Min.
Typ.[l]
Max.
Unit
Test Conditions
IFB
Input Load Current BUSY
0.40
1
mA
VIN = 0.45V
IFO
Input Load Current All Other Inputs
0.05
0.25
mA
VIN = 0.45V
IRB
Input Leakage Current BUSY
<1
50
/lA
VIN = Vee
IRO
Input Leakage Current All Other Inputs
<1
20
/lA
VIN = 5.25V
VeLAMP
Input Clamp Voltage
-0.76
-1
V
Ie = -5.0mA
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
0.8
2.0
V
V
Icc
Power Supply Current
91
120
mA
Vee = 5.25V
Isc
Output High Short Circuit Current
-48
-70
mA
VOUT = OV
Vee = 5.25V
VOL
Output Low Voltage
0.32
0.45
V
IOL = 5mA
VOH
Output High Voltage (00-05)
2.6
3.1
V
IOH=-lmA
Vee = 4.75V
VOHI
Output High Voltage (All Other Outputs)
2.4
3.0
V
IOH = -lmA
Vee = 4.75V
Note 1:
Typical values are for TA
= 2Soe and nominal power supply voltages.
Limits (pF)
Typ.
Max.
Symbol
Test
CIN (Address)
Input Capacitance
5
10
CIN (CYREQ)
Input Capacitance
6
10
Vee = OV
CIN (BUSY)
Input Capacitance
20
30
f = 1 MHz
Note 2:
This parameter is periodically sampled and is not 100% tested.
5-14
Conditions
Vbia. = 2.0V
3222
A.C. Characteristics
All Limits Apply for Vee = +5.0V ±5%, TA = o°c to +75°C. Load = 1 TTL, CL = 15pF.
Conditions of Test: Input pulse amplitude: 3V, Input rise and fall times: 5ns between 1 V and 2V. Measurements are made at 1.5V.
Symbol
Parameter
Min.
Typ.'
Max.
Unit
tAA
Address In to Address Out
7
12
ns
tBAM
BUSY In to Address Out
21
28
ns
tBAR
BUSY In to Counter Out
18
27
ns
Conditions
BUSY = VIH
tBK
BUSY In to ACK Out
14
20
ns
tBR
BUSY In to REFON Out
15
24
ns
tBS
BUSY In to STARTCY Out
4
7
14
ns
CYREO= VIL
tHOLD
BUSY Hold Time
50
ns
External Delay between STARTCY and
BUSY
tRH
CYREOor REFREO Hold Time
0
tRR
REFREO to REFON
tRRe
REFREO to REFON
tRS
CYREOor REFREO In to
STARTCY Out
tSetup
BUSY Setup Time
Note 1: Typical values are for TA
9
REFREO = VIH, CYREO = VIL
ns
External Delay after BUSY
18
26
ns
CYR EO and BUSY = VIH, No priority
contention between REFREO and
CYREO
33
45
ns
BUSY = VIH
14
21
ns
BUSY = VIH
ns
BUSY = VIL During Refresh
120
= 25°e and nominal power supply voltages.
A. SYSTEM MEMORY CYCLE
WITH MEMORY NOT BUSY
B. SYSTEM MEMORY CYCLE WITH MEMORY
BUSY (FOLLOWING REFRESH CYCLE)
(Numbers in parentheses are minimum values in ns unless otherwise specified.)
"-
V'H
'RH
(01----
V'H
CYREQ
(IN)
CYREQ
(IN)
VIL
VIL
v,"
V'H
REFREQ
REFREO.
(IN)
(IN)
V'H
STAFfTCY
(OUT)
STARTCY
lOUT)
VIL
VIL
v,"
V'H
BUSY
(IN)
BUSY
VIL
(IN)
V'H
V'H
REFON
(OUT)
REFON
(OUT)
V'l-
V'H
ACt(
ACK
-- - - -
V 1L -
Ao·A s
'"=;§
V1l
VIL
V'H
(OUT)
(IN)
VIL
(OUT)
V'H
A,· ...
(IN)
t"A ;
VIL
112 MAX)
°
0 .05
(OUT)
V'H
V'H
ADDRESS
ADORESS
°o.()s
(OUT)
V'L
5-15
ADDRESS
V'L
3222
D. REFRESH MEMORY CYCLE WITH MEMORY
BUSY (FOLLOWING SYSTEM CYCLE)
C. REFRESH MEMORY CYCLE WITH
MEMORY NOT BUSY
(Numbers in parentheses are minimum values in ns unless otherwise specified;)
CYREO
(IN)
V'H'--------------------V'L- -
CYREO
(IN)
-- --
v,.
V1l -
-
---
V'H'------"\
REFREO
(IN)
V'H--""-~i
STARTCY
(OUT)
ffiRTCV
V'l
V'H--------..
(OUT)
V'l- _ _
BUSY
(IN)
V'l ____...J
V'H
BUSY
(IN)
V'H---------------------
V'H
V'H
V'H------.'!"\
REFON
fQUT)
REFON
(OUT)
V1l -
V'H
ACK
(OUT)
ACK
(OUT)
V'H
"o-As
(IN)
V'H-----------4I------.l-I--_
"o-As
(IN)
V'l
V'H
°0-05
(OUT)
V'l------.1
0;0.
V'l
(OUT)
V'l ___________-+.....;;.;..........._----I-+__
V,H--------....:::::...:............- ...... I,---,I ......AODRESS
V,l-------------...JI'-;..;.......~'I'---
NOTE 1: tRR (26m MAX) IF PRIORITY CONTENTION IS ELIMINATED; tARe
F. USE OF 3222 FOR REFRESH TIMING AND
CONTROL IN A 2104A SYSTEM
E. TYPICAL APPLICATION OF 3222 REFRESH
CONTROLLER IN A 2107C SYSTEM
2104A
MEMORY
DEVICES
L
ADDRESS
INPUTS
TO 21078
ARRAY
_ _ _ _..... ~~~~ TIMING
~--- RAS ENABLE
LATCH
.......J..._.l...JL-_--. ONL V ONE 3222 IS REaUIRED PER SYSTEM.
ADEQUATE BUFFERING SHOULD BE PROVIDED
BETWEEN THE 3222 ADDReSSES (00-0 5 1
THE MEMORY INPUTS.
...._ _ _ _ _---1 OUTPUTS AND
5-16
3222
PIN NAMES AND FUNCTIONS
Pin
No.
Pin
Name
Q
2
3
4
5-7
15-17
8-10
REFREQ
CYREQ
STARTCY
Ao-A5
0 0-05
Function
Output of the internal Refresh Request latch. This pin may be connected to the Refresh Request input
(REFREQ) directly for asynchronous sequential mode refresh or
indirectly through control logic for
burst mode or synchronous mode
refresh (see text).
An externally generated signal
which the 3222 monitors to determine memory system status. If BUSY
is high the memory is not busy and a
system or refresh cycle may begin.
If BUSY is low the memory is being
accessed for a data 1/0 or refresh
cycle and no other cycle may begin.
19
REFON
The 3222 output which when low indicates the memory system is either
ready to begin or is in a refresh cycle
(Refresh On).
20
ACK
The 3222 output which when low indicates the memory system is
either ready to begin or is in a
system cycle (system cycle request
accepted and acknowledged).
22
Vee
+5 volt supply.
The block diagram shows the four main circuit categories of
the 3222. An explanation of the workings of each of these
categories is given in the Device Operation section from a
users point of view.
DEVICE OPERATION
Operation of the Intel® 3222 Refresh Controller is most
easily explained by considering five conditions presented
by the three input control lines Cycle Request (CYREQ),
Refresh Request (REFREQ), and System Busy (BUSY).
These conditions are:
Low order memory address outputs.
During a system cycle these outputs
give the low order (Ao-A5) address
of a memory access. During a
refresh cycle these outputs give the
refresh address (generated internal
to the 3222).
BUSY
Connection point for the RC network which determines the refresh
period for sequential refresh mode.
(See Refresh Control section).
Function
As shown in the pin configuration figure, the 3222 has as
inputs the six low order (Ao-A5) system addresses. These
addresses are internally multiplexed with six internally
generated refresh addresses. The output of these
multiplexers provide the six low order addresses to the
memory array.
Low order system address inputs.
These add resses are multi plexed to
the address output pins (00-05)
during a system cycle.
18
RX/CX
1. Providing a refresh timing oscillator.
2. Generating six bit refresh addresses.
3. Multiplexing refresh and system addresses to the six
low order address inputs (00-05)'
4. Providing control signals for both refresh and memory cycle accesses.
Output signal indicating to external
circuitry that a memory cycle
(system or refresh) is to begin. See
text for timing considerations for a
refresh cycle.
Ground.
21
The Intel® 3222 performs the four basic functions of a
refresh controller by:
System Memory Cycle Request input (active when low). The request
is honored only if the memory is not
presently executing a cycle (BUSY
high) and if a refresh request did not
occur first.
GROUND
Pili
Name
FUNCTIONAL DESCRIPTION
Refresh Request input (active when
low). The request is honored only if
the memory is not presently executing a cycle (BUSY high) and if a
system cycle request did not occur
first.
11
Pin
No.
1. System memory cycle request - memory not busy
(BUSY = High)
2. System memory cycle request - memory busy
(BUSY =Low)
3. Refresh cycle request - memory not busy
(BUSY = High)
4. Refresh cycle request - memory busy
(BUSY =Low)
5. Simultaneous system memory cycle and refresh cycle
requests.
Condition 5 is actually a subset of the four previous
conditions and is included for completeness.
As is implied in the five conditions, the response of the3222
to both refresh and memory cycles is dependent on the
state of the BUSY input. The BUSY signal is generated
externally to the 3222 and, when low, defines the time when
the memory is performing a cycle (refresh or memory
access). It is important to assure that BUSY is low for the
entire memory cycle time. Interference may occur in
asynchronous memory systems if the BUSY input goes
high prematurely. (An asynchronous memory system is
one in which the refresh and memory cycle requests occur
independent of each other.)
5-17
3222
System Memory Cycle Request -
Memory Not Busy
This section details operation of the 3222 when the memory
is not busy and a request for a system memory cycle is
made (See Figure A for timing sequences). The request for
a memory cycle is made by the CYREQ input going low. The
Start Cycle output STARTCY goes low at tRS after CYREQ.
STARTCY is used for two purposes:
and tRRG (or tRR) time respectively. The low gOing edge of
STARTCY is used to set the external BUSY latch low. As in
the previous two cases, the BUSY input must remain low for
the entire cycle required by the memory. As in the previous
two cases, the low going BUSY drives the STARTCYoutput
high.
Refresh Cycle - Memory Busy
For this condition, it is assumed that the previous cycle was
a system access cycle. Timing conditions forthis operation
are shown in Figure D. Here, the STARTCY input goes low
tss after BUSY returns high from the previous cycle. As
before, REFON goes low tSR after BUSY goes high. After
tHOLD, relative to STARTCY, BUSY again goes low and
places the low order refresh addresses on the address
outputs (0 0-05) after tSAR time. Internal refresh timing is
performed in a manner identical to that described in
Refresh Cycle-Memory Not Busy section.
1. To set the external BUSY latch. (See Figure E.)
2. To initiate memory system timing (after appropriate
delay).
The required delay time depends on system configuration
and associated delay paths for both Chip Enable (2107B
input signal) and system addresses.
The low going BUSY input causes the internally generated
Start Cycle output to go high and the Acknowledge output
ACK to go low (after tSK time). The Acknowledge output
confirms that the requested system memory cycle has been
accepted by the 3222. Note that the cycle request input may
be returned to the high state when the BUSY input goes low.
However, at the designer's discretion, the cycle request line
may remain low until "just prior"to BUSYreturning high. (If
BUSY goes high before CYREQ goes high, another
memory access may inadvertently be started.)
Simultaneous Refresh and Memory System Cycle Request
The simultaneous request for a refresh and memory system
access is almost a certainty in asynchronous systems. It is,
therefore, necessary to have circuitry in any refresh
controller capable of resolving the attendent ambiguity with
minimum additional delay. The Intel® 3222 Refresh
Controller has just such a circuit. (All timing parameters
specified for asynchronous operation assume that a refresh
and memory system request can occur at the same time.) A
latch internal to the 3222 decides which signal (CYREQ or
REFREQ) it will accept if both occur simultaneously, and
conditions the other control circuits appropriately. If a
refresh cycle was accepted, REFON will go low at the
appropriate time. If a memory system access was accepted
then ACK will go low at the appropriate time.
When the memory is not busy and a cycle request has been
made, the low order systllm address delay through the 3222
is tAA nsec. When the 3222 is not busy, the low order system
addresses (Ao-As) are gated through to the output (00-05)
independent of any other input.
System Memory Cycle Request -
Memory Busy
The major differences between a system memory cycle
request when the system is busy and when it is not busy (as
previously described) are:
Refresh Control
The 3222 controls both burst and distributed refresh modes.
The burst refresh mode requires that REFREQ be generated
externally to the 3222 since refresh is completed in 64
consecutive cycles every 2ms. A system requiring distributed refresh timing, however can be controlled either by the
3222 or by external circuitry. If refresh timing is to be
controlled by the 3222 the output IT is tied to the REFREQ
input. Timing is controlled by an oscillator internal to the
3222. The desired refresh timing interval is determined by:
1. The Start Cycle outputS
;:;:T::::A-;-;:;-R::::T"'C"'y does not go low until
tss after the rising edge of the BUSY input. (Even
though the CYREQ input is low.)
2. Output addresses 00-05 change at or before tAA time if
the previous cycle was a system cycle request and
change at or before tSAM if the previous cycle was a
Refresh Cycle request. (Note that the longer delay is
after a refresh cycle.) See Figure B for definition of
terms.
Note that for a system memory cycle following a refresh
cycle, the refresh on output REFON goes high at or before
tSR relative to BUSY going high. Since the Acknowledge
output ACK can not go low until after tHOLD there is no
ambiguity between REFON and ACK. The memory is
always defined as being in a refresh cycle, system cycle or'
no cycle.
1. tREF = .63 RxCx
r
Where:
tREF = the total time between refreshes (e.g. 2m sec) in
msec.
r =the number of rows to be refreshed on the memory
device (for the 2107C r = 64),
Rx = external timing resistance in KG (3K to 10K)
c, = external timing capacitance in Ilf. (0.005Ilf to
0.02Ilf)
Refresh Cycle -
Memory Not Busy
Operation of the 3222 for a refresh request with the memory
not busy (see Figure C) is similar to a system cycle request
under the same condition. A refresh cycle is initiated
by the Refresh Request input (REFREQ) going low.
This low going input causes both the Start Cycle output,
STARTCY, and Refresh On output, REFON, to go low at t RS
The 3222's oscillator stability is guaranteed to be ±2% for a
given part and ±6% from part to part, both over the ranges
O"C,;;; TA';;; 75°C and Vee = 5.0V ±5%.
Figure F shows how the 3222 may be used to control
refresh ina 2104A system.
5-18
inter
3232
ADDRESS MULTIPLEXER AND REFRESH
COUNTER FOR 4K DYNAMIC RAMs
Input to Output Delay:
• Address
9ns Maximum Driving 15pF,
• Ideal for 2104A
• Simplifies System Design
• Reduces Package Count
• Standard 24-Pin DIP
•
•
25ns Maximum Driving 250pF
Suitable for Either Distributed or
Burst Refresh
Single Power Supply: +5 Volts ±10%
The Intel@3232contains an address multiplexer and refresh counter for multiplexed address dynamic RAMs requiring refresh
of up to 6 input addresses (or 4K bits for 64 x 640rganization). It multiplexes twelve bits of system supplied address to six output
address pins. The device also contains a 6 bit refresh counter which is externally controlled so that either distributed or burst
refresh may be used. The high performance of the 3232 makes it especially suitable for use with high speed N-channel RAMs
like the 2104A.
The 3232 operates from a single +5 volt power supply and is specified for operation over a 0 to +75°C ambient temperature
range.
PIN CONFIGURATION
COUNT
LOGIC DIAGRAM
Vee
A"<>---r==~======[J
ROW ENABLE
REFRESH ENABLE
A,
"-
A,
A"
A,
A.
Aa
A,.
A.
A3
A.
A.
0;,
03
0,
O.
0;
0.
~~--~=*========[J
I
I
I
GND
NOTE,
12
I
I
I
TOTAL I
!
8
I TOTAL
I
!
!
ZERO DETECT
Ao THROUGH',,"
ARE ROW ADDRESSES.
AI THROUGH Al1 ARE COLUMN ADDRESSES.
REFRESH
ENABLE
TRUTH TABLE AND DEFINITIONS:
REFRESH
ENABLE
ROW
ENABLE
H
X
l
H
l
l
ROW
ENABLE
OUTPUT
REFRESH ADDRESS
IFROM INTERNAL COUNTER!
ROWADORESS
lAo THROUGH Asl
COLUMN ADDRESS
lAo THROUGH A" I
COU~<>------~
COUiiiT -
ADVANCES INTERNAL REFRESH COUNTER.
ZERO DETECT INDICATES A ZERO IN THE REFRESH ADDRESS
IUSED IN BURST REFRESH MODEl.
5-19
8 TOTAL
8 TOTAL
8
TOTAL
II
3232
ABSOLUTE MAXIMUM RATINGS·
·COMMENT:
Temperature Under Bias ....•• ,....... -65° to +125°C
Storage Temperature .•...••..•••.••.. _65° to +160"C
All Input, Output, or
Supply Voltages .•..............•.•. -0.5V to +7 Volts
Output Currents ••••......•...••.••..••.....•. 100mA
Power Dissipation .•••.•........•.......••........ 1W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
All Limits Apply for Vee = 5.0V ±10%, TA = O"C to
SYMBOL
PARAMETER
IF
Input Load Current
IR
VIH
Input Leakage Current
VIL
VOL
VOH
Input High Voltage
+ 75°C
LIMITS
MIN.
UNIT
TEST CONDITIONS
TYP.(1)
MAX.
-0.04
-0.25
rnA
VIN - 0.45V
0
10
p.A
VIN
5.5V
V
V
10L
5mA
1mA
2.0
V
0.8
Input Low Voltage
Output Low Voltage
0.25
0.40
Output High Voltage (0,,0,)
2.8
4.0
V
10H
VOHI
Output High Voltage
(zero Detect)
2.4
3.3
V
10H =-lmA
Icc
Power Supply Current
rnA
Vee - 5.5V
Note 1.
100
Typical values are for T A = 25° e and Vee = 5.0V.
5-20
150
3232
A.C. CHARACTERISTICS
All Limits Apply for Vee
= +5.0V ±10%. TA = O"C to 75°C.
Load
= 1 TTL.
CL
Typ~11
= 250pf. Unless Otherwise Specified.
SYMBOL
PARAMETER
MAX.
UNIT
CONDITIONS
tAO
t AO(
Address Input to Output Delay
6
9
ns
Refresh Enable
Address Input to Output Delay
16
25
ns
Refresh Enable
MIN.
too
Row Enable to Output Delay
7
12
27
ns
Refresh Enable
tOOl
Row Enable to Output Delay
12
28
41
ns
Refresh Enable
ho
Refresh Enable to Output Delay
7
14
27
ns
Note 1. 2
tEOI
Refresh Enable to Output Delay
12
30
45
ns
teo
Count to Output
15
40
60
ns
Refresh Enable
teol
Count to Output
20
55
80
ns
Refresh Enable
fe
Counting Frequency
5
tepw
Count Pulse Width
35
tez
Count to Zero Detect
15
= LOWIlI (li
= Low
= Low (II (21
= Low
= Highlll (21
= High
MHz
ns
70
ns
Note 2
Note 1: Vee = 5.0V. T A = 25°e
2: eL = 15pF
A.C. TIMING WAVEFORMS (Typically used with 2104A)
NORMAL CYCLE
VIH
ROW ENABLE
V,L
1.5V
V,H
Ao·Al1
V,L
VOH
1l•.Il.
ROIV ADDRESS
COLUMN AODRESS
VOL
REFRESH
ENABLE
~---------------------------
V,L
REFRESH CYCLE
V,H
REFRESH
ENABLE
1.5V
V,L
V,H
ClIUfIT
VIL - - - -
VOH
Il•.o"
VOL
2.4V
O.BV
REFRESH ADDRESS
~H'----------------------------------~~
~----------------------
5·21
REFRESH ADDRESS
3232
PIN NAMES AND FUNCTIONS
Pin
Pin.
Name
Function
No.
.
I
-:•
inputs. The truth table on page 1 shows the levels required
to multiplex to the output:
Count Input
Active low input increments
internal six bit counter by
one for each count pulse in.
2
Refresh Enable
Input
Active high input which
determines whether the
3232 is in refresh mode (H)
or address enable (L).
7,3,5,18,
20,22
Ao-A, Inputs
Row Address inputs.
8.4,6,17,
19,21
A,-A II Inputs
Column address inputs.
9,11,10,
16,15,14
0 0-0 5 Outputs
Address outputs to memories. Inverted with respect
to address inputs.
12
GND
Power supply ground.
13
Zero Detect
Output
Active low output which
senses that all six bits of
refresh address in the counter are zero. Can be used in
the burst mode to sense
refresh completion.
23
Row Enable
Input
High input selects row, low
input selects column addresses of the driven memories.
24
Vee
+5V power supply input.
1. Refresh addresses (from internal counter)
2. Row addresses (Ao through A,)
3. Column addresses (A6 through All)
Burst Refresh Mode
When refresh is requested, the refresh enable input is high.
This input is ANDed with the 6 outputs of the internal 6 bit
counter. At each Count pulse the counter increments by
one, sequencing the outputs (0 0-0 5) through all 64 row
addresses. When the counter sequences to all zeros, the
Zero Detect output goes low signaling the end of the refresh
sequence. Due to counter decoding spikes, the Zero Detect
output is va'lid only after lez following the low going edge of
Count.
Distributed Refresh Mode
In the distributed refresh mode, one row is selected for
refresh each (tREFRESH/n) time where n ~ number of rows in
the device and tREFRESH is the specified refresh rate for the
device. For the 2104A tREFRESH ~ 2msec and n ~ 64, there·
fore one row is refreshed each 31 Ilsec. Following the refresh
cycle at row n x , the Count input is pulsed, advancing the
refresh address by one row so that the next refresh cycle will
be performed on row nx +1' The Count input may be pulsed
following each refresh cycle or within the refresh cycle after
the specified memory device address hold time.
Rowand Column Address
All twelve system address lines are applied to the inputs of
the 3232. When Refresh Enable is low and Row Enable is
high, input addresses Ao-A5 are gated to the outputs and
applied to the driven memories. Conversely, when Row
Enable is low (with Refresh Enable still low), input
addresses A6-A" are gated to the outputs and applied to the
driven memories.
DEVICE OPERATION
The Intel® 3232 Address Multiplexer/Refresh Counter
performs the following functions:
Figure 1 shows a typical connection between the 3232 and
the 2104A 4K dynamic RAM. When the memory devices are
driven directly by the 3232, the address applied to the
memory devices is the inverse of the address at the 3232
inputs due to the inverted outputs of the 3232. This should
be remembered when checking out the memory system.
1. Row, Column and Refresh Address multiplexing
2. Address counting for burst or distributed refresh.
These functions are controlled by two signals: Refresh
Enable and Row Enable, both of which are active high TTL
All
I
A,
0,.
>-----
I
I
I
I
3232
0.
>----ZERO
REFRESH
ENABLE
I
I
As
A,
A,
~
~
I
2104A
I
I
~
A,
2104A
~
~ETECT
ROW
ENABLE
)
Figure 1. Typical Connection of 3232 and 2104 Memories.
5-22
I
I
2104A
i-
inter
3242
ADDRESS MULTIPLEXER AND REFRESH
COUNTER FOR 16K DYNAMIC RAMs
• Single Power Supply:
• Ideal For 2116
• Simplifies System Design
+5 Volts ±10%
• Address Input to Output Delay:
• Reduces Package Count
• Standard 28-Pin DIP
9ns Driving 15 pF,
25ns Driving 250pF
• Suitable For Either Distributed
Or Burst Refresh
The Intel® 3242 is an address multiplexer and refresh counter for multiplexed address dynamic RAMs requiring refresh of 64 or
128 cycles. It multiplexes 14 bits of system supplied address to 7 output address pins. The device also contains a 7 bit refresh
counter which is externally controlled so that either distributed or burst refresh may be used. The high performance of the 3242
makes it especially suitable for use with high speed N-channel RAMs like the 2116.
The 3242 operates from a single +5 volt power supply and is specified for operation over a 0 to +75°C ambient temperature
range. It is fabricated by means of Intel's highly reliable Schottky bipolar process and is packaged in a hermetically sealed 28
pin Type D package.
LOGIC DIAGRAM
PIN CONFIGURATION
COUNT
Vee
REFRESH ENABLE
As
ROW ENABLE
A"
N.C.
As
A,
A"
As
A,
A,
A"
A13D-----
AS
AS
I
I
I
I
I
TO~~L I
I
I
I
I
I
I
As
A,
I
I
7
I TOTAL
7
TOTAL
I
I
I
An
A"
I
I
I
A,
0.
0;,
0;
I
I
I
I
I
I
I
0,
0;
0,
0,
GND
I
A7
AO
00
ZERO DETECT
NOTE: Ao THROUGH A6 ARE ROW ADDRESSES.
A7 THROUGH A13 ARE COLUMN ADDRESSES.
TRUTH TABLE AND DEFINITIONS:
REFRESH
ENABLE ~-''''''~<""1"''''''''-
7 TOTAL
6 TOTAL
REFRESH
ENABLE
ROW
ENABLE
H
X
L
H
L
L
OUTPUT
REFRESH ADDRESS
(FROM INTERNAL COUNTER)
AOWADDAESS
fAo THROUGH As)
COLUMN ADDRESS
fA7 THROUGH All)
COCJN'F
COiJj\j'f ~ ADVANCES INTERNAL REFRESH COUNTER.
ZERO DETECT INDICATES ZERO IN THE FIRST 6
SIGNIFICANT REFRESH COUNTER
BITS (USED IN BURST REFRESH MODE)
5-23
O~------
3242
A.C. Characteristics
= +5.0V ±1 0%,
All Limits Apply for Vee
TA
= 0° C to
75° C, Load
= 1 TTL,
MIN.
CL
= 250pF,
TYP.(1) ,MAX.
Unless Otherwise Specified.
SYMBOL
PARAMETER
tAO
Address Input to Output Delay
6
9
UNIT
ns
Refresh Enable
tAO!
Address Input to Output Delay
16
25
ns
Refresh Enable
CONDITIONS
= Low(2)(3)
= Low
= Low(2)(3)
= Low
too
Row Enable to Output Delay
7
12
27
ns
Refresh Enable
tOOl
Row Enable to Output Delay
12
28
41
ns
Refresh Enable
Notes 2, 3
tEO
Refresh Enable to Output Delay
7
14
27
ns
hot
Refresh Enable to Output Delay
12
30
45
ns
leo
Count to Output
15
40
60
ns
Refresh Enable
teO!
Count to Output
20
55
80
ns
Refresh Enable
5
MHz
Ie
Counting Frequency
tcpw
Count Pulse Width
35
tcz
Count to Zero Detect
15
Notes: 1. Typical values are for T A
= 25°e and
Vee
= Hig)1(2) (3)
= High
ns
70
Note 3
ns
= 5.0V.
= 25°e, Vee = 5.0V.
eL = 15pF.
2. TA
3.
A.C. TIMING WAVEFORMS (Typically used with 2116)
NORMAL CYCLE
ROW ENABLE
1.5V
\
II
1\ 1.5V
-
:---
tAO
-too~
-'oo~
~H------DD-N-'T-C-A-RE-------r~2~.4~V-------R-O-W-AD-D-R-E~--------~~----CO-l-U-MN--AD-D-R-E~-----~L
REFRESH
___________________
~~O~.8~V
______________________
~~
_________________
~---------------------------
ENABLE
VIl - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
REFRESH CYCLE
\\....---
REFRESH
ENABLE
Vil
l
----
VOH
0-06
ADDRESS
VOL
.
I
V,H
COUNT
~tcpw_
"~c
---------------_
t
oo
)
_ t CQ
_
~
2.4V
O.8V
}
REFRESH ADDRESS
REFRESH ADDRESS
!.-- t e l _
VOH1
zrnllM'm:'f
VOL - - - - - - - - - - - - - - - - - - - - - - -
5-24
---
1\ 1.5V
X
3242
Absolute Maximum Ratings*
·COMMENT:
Temperature Under Bias ..............
-10· to +85·C
Storage Temperature ................. -65· to +150·C
All Input, Output, or
Supply Voltages .................... -0.5V to +7 Volts
Output Currents .............................. 100mA
Power Dissipation ................................ 1W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. and Operating Characteristics
All Limits Apply for Vee = 5.0V ±10%, TA = O"C to
SYMBOL
IF
+ 75·C
PARAMETER
MIN.
LIMITS
TYP.(H
MAX.
-0.04
-0.25
mA
VIN - 0.45V, Note 2
0.01
10
p.A
VIN
5.5V
SmA
Input Load Current
IR
Input Leakage Current
VIH
Input High Voltage
TEST CONDITIONS
UNIT
V
2.0
VIL
Input Low Voltage
VOL
Output Low Voltage
VOH
Output High Voltage (00-06)
3.0
4.0
VOHI
Output High Voltage
(zero Detect)
2.4
3.3
lec
Power Supply Current
0.25
105
0.8
V
0.40
V
10L
V
IOH
V
IOH = -1mA
165
mA
Vee
Notes: 1. Typical values are for TA = 25°e and Vee = 5.0V.
2. Inputs are high impedance, TTL compatible, and suitable for bus operation.
Packaging Information
28 LEAD HERMETIC DUAL IN-LINE PACKAGE
TYPE D
-__
C
C
~ (37.338)~
1.430 (36.322)
~PINll
~ (13.462)
.510 (12.954)
___
--.l
CJ
.625
=-__I5?JV
-=i'
1-1
I--
-,--PM ~=
~.140 (3.556)
~.065 (1.016~032
(1.651)
.040
MAX.
(15.875)
TVP
(0.831)
5-25
IL
--I
l 0 1 6 MIN.
(0381)
.023 '(0.584)
.014 (0.356)
;0'381~
1.015:
.008 (0~.203)
~ .700
.600
(17.78)
(15.24)
1mA
5.5V
3242
PIN NAMES AND FUNCTIONS
Pin
No.
Pin
Name
2. Row addresses (Ao through AS)'
3_ Column addresses (A 7 through A13).
Function
Count
Input*
Active low input increments internal 7bit counter by one for each count pulse
in.
2
Refresh
Enable
Input*
Active high input which determines
whether the 3242 is in refresh mode (H)
or address enable (L).
9,5,7,21,
23,25,27
AO-As
Inputs*
Row address inputs.
10,6,8,20, A7-A13
22,24,26
Inputs*
Column address inputs.
11 ,13,12,
18,17,16,
19
Do-Os
Outputs
Address outputs to memories. Inverted
with respect to address inputs.
14
GND
Power supply ground.
15
Zero
Detect
Output
Active low output wh ich senses that the
six low order bits of refresh address in
the counter are zero. Can be used in the
burst mode to sense refresh completion.
3
Row
Enable
Input*
High input selects row, low input selects
column addresses of the driven memories.
28
Vee
+5V power supply input.
Burst Refresh Mode
When refresh is requested, the refresh enable input is high.
This input is ANDed with the seven outputs of the internal
7-bit counter. At each Count pulse the counter increments by
one, sequencing the outputs (Do-Os) through 128 row addresses. When the first six significant bits of the counter
sequence to all zeros, the Zero Detect output goes low,
signaling the end of the refresh sequence. Due to counter decoding spikes, the Zero Detect output is valid only after tez
following the low-going edge of Count. The Zero Detect output used in this manner signals the completion of 64 refresh
cycles. To use the 128-cycle burst refresh mode, an external
flip-flop must be driven by the Zero Detect_
Distributed Refresh Mode
"The inputs are high impedance, TTL compatible, and suitable for bus
In the distributed refresh mode, one row is selected for refresh
each (tREFRESH/n) time where n = number of refresh cycles
required for the device and tREFRESH is the specified refresh
rate for the device. For the 2116 tREFRESH = 2 msec and n =
128 or 64, therefore, one row is refreshed each 15.5 or 31
f.1.sec, respectively. Following the refresh cycle at row n x, the
Count input is pulsed, advancing the refresh address by one
row so that the next refresh cycle will be performed on row
n x +1' The Count input may be pulsed following each refresh
cycle or within the refresh cycle after the specified memory
device address hold time.
operation.
Rowand Column Address
DEVICE OPERATION
The Intel® 3242 Address Multiplexer/Refresh Counter performs the following functions:
1. Row, Column and Refresh Address multiplexing.
2_ Address Counting for burst or distributed refresh.
These functions are controlled by two signals: Refresh Enable
and Row Enable, both of which are active high TTL inputs.
The truth table on page 1 shows the levels required to multiplex to the output:
1. Refresh addresses (from internal counter).
3242
Ao
>---
00
A
A,
0,
>---
All 14 system address lines are applied to the inputs of the
3242. When Refresh Enable is low and Row Enable is high,
input addresses Ao-As are gated to the outputs and applied to
the driven memories. Conversely, when Row Enable is low
(with Refresh Enable still low), input addresses A7-A13 are
gated to the outputs and applied to the driven memories.
Figure 1 shows a typical connection between the 3242 and the
2116 16K dynamic RAM. When the memory devices are
driven directly by the 3242, the address applied to the memory devices is the inverse of the address at the 3242 inputs due
to the inverted outputs of the 3242. This should be remembered when checking out the memory system.
I
I
I
I
A,
-r-
f---J2116
Ao
I
I
I
2116
Ao
I----
_J~
REFRESH
ENABLE
ZERO DETECT
ROW
ENABLE
Figure 1. Typical Connection of 3242 and 2116 Memories.
5-26
I
I
I
2116
Ao
~
3245
QUAD TTL-TO-MOS DRIVER
FOR 4K N-CHANNEL MOS RAMs
• High Density One Package
• Fully Compatible with 4K RAMs
Without Requiring Extra Supply
or External Devices
• High Speed, 32 nsec Max. Delay + Transition Time
• Low Power - 75mW Typical
Per Channel
Four Drivers in
• TTL and DTL Compatible Inputs
• CerDIP Package -
16 Pin DIP
• Only +5 and +12 Volt Supplies
Required
The Intel® 3245 is a Quad Bipolar-to-MOS driver which accepts TTL and DTL input signals. It provides
high output current and voltage suitable for driving the clock inputs of N-channel MOS memories such as
the 21 07B. The circuit operates from two power supplies which are 5 and 12 volts. I nput and output clamp
diodes minimize line reflections.
The device features two common enable inputs, a refresh select input, and a clock control input for
simplified system designs. The internal gating structure of the 3245 eliminates gating delays and minimizes package count.
The 3245 is fabricated by means of Intel's highly reliable Schottky bipolar process and is specified for
operation over a 0 to +75 0 C ambient temperature range.
LOGIC DIAGRAM
PIN CONFIGURATION
e,-------,
V OD
vee
0,
E,-------,
0,
0,
~
e,
c
0,
E,
;;
r;
0,
0,
GNO
NC
0,
0,
PIN NAMES
1,-1 4
SELECT INPUTS
0,.°4
DRIVER OUTPUTS
E,.E 2
ENABLE INPUTS
Vee
+5V POWE R SUPPLY
R
REFRESH SELECT INPUT
V DD
+12V POWER SUPPLY
C
CLOCK CONTROL INPUT
NC
NOT CONNECTED
5-27
3245
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ••.••••.••• -10°C to 85°C
Storage Temperature ••.••.•••.•. _65°C to +l50°C
Supply Voltage, Vee ••••••••.••••• -0.5 to +7V
Supply Voltage, Voo •••..••••••••. -0.5 to +14V
All Input Voltages. . . • . • • . . • . • . • •. -1.0 to Voo
Outputs for Clock Driver. . . . . • . . • -1.0 to Voo +1 V
Power Dissipation at 25°C. • • • . • . • • . . . • . . .. 'lW
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operation'al sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS
TA =o°c to 75°C, Vcc=5.0V ±5%. Voo = 12V ±5%
Symbol
Min.
Parameter
,13.T4
Max.
Unit
-0.25
mA
Test Conditions
VF = 0.45V
IFO
Input Load Current,T,,1 2
IFE
Input Load Current,R,C,E1,E2
-1.0
mA
VF = 0.45V
IRO
Data Input Leakage Current
10
IlA
V R = 5.0V
IRE
Enable Input Leakage Current
40
IlA
V R = 5.0V
VOL
Output Low Voltage
0.45
V
V
IOL = 5mA, VIH = 2V
IOL --5mA
VOH
Output High Voltage
Voo+1.0
V
V
IOH = -lmA, VIL = 0.8V
IOH - 5mA
VIL
Input Low Voltage, All Inputs
0.8
V
VIH
Input High Voltage, All Inputs
-1.0
Voo-O.50
2
V
POWER SUPPLY CURRENT DRAIN AND POWER DISSIPATION
Symbol
Parameter
Typ.
Max.
Unit
mA
Icc
Current from Vcc
23
30
100
Current from Voo
19
26
mA
POl
Power Dissipation
365
485
mW
Test Conditions - I nput states to
ensure the following output states:
Additional Test
Conditions
High
Power Per Channel
91
121
mW
Vcc = 5.25V
Icc
Current from Vcc
29
39
mA
Voo = 12.6V
100
Current from Voo
12
15
mA
P02
Power Dissipation
300
388
mW
Power Per Channel
75
97
mW
Low
5·28
3245
A.C. CHARACTERISTICS
TA
= 0° to
75°C, VCC
= 5.0V ±5%, VOO = 12V ±5%
Parameter
MinJ11
L+
Input to Output Delay
5
tOR
Delay Plus Rise Time
t+_
Input to Output Delay
tOF
Delay Plus Fall Time
tT
Output Transition Time
tOR
Delay Plus Rise Time
tOF
Delay Plus Fall Time
Symbol
NOTES: 1.
2.
3.
4.
Typ.f2.41 Max.l31
11
20
Symbol
*
10
Typ. Max.
=0
=0
RSE;RIES = 0
RSERIES = 0
RSERIES = 20Q
RSERIES = 20Q
RSERIES = 20Q
ns
RSERIES
ns
RSERIES
32
ns
17
25
ns
27
38
ns
25
38
ns
A.C. CONDITIONS OF TEST
Input Pulse Amplitudes: 3.0V
Input Pulse Rise and Fall Times: 5 ns between
1 volt and 2 volts
Measurement Points: See Waveforms
Unit
CIN
Input Capacitance, I, ,12,13,14
5
8
pF
CIN
I nput Capacitance, R,C,E 1 ,E2
8
12
pF
I!VV~
R!E."~ES_~ ~
'--_.....
:;t
*This parameter is periodically sampled and is not 100% tested.
Condition of measurement is f = 1 MHz, Vbias = 2V, VCC=OV,
3245
L
and TA = 25'C.
WAVEFORMS
Test Conditions
ns
18
TA = 25°C
Test
32
7
3
CL = 150pF }
These values represent a range of
CL = 200pF
total stray plus clock capacitance
CL = 250pF
for nine 4K RAMs.
Typical values are measured at 25' c.
CAPACITANCE
Unit
~----------l---------------------2.0V
INPUT _ _ _"""""
TYPICAL CHARACTERISTICS
DELAY PLUS TRANSITION TIME
INPUT TO OUTPUT DELAY
VS. LOAD CAPACITANCE
VS. LOAD CAPACITANCE
40
40
30
30
20
20
-----
10
100
200
300
...-:":j
400
10
'+500
600
~
~
~
::::: ~
100
LOAD CAPACITA~CE (pF)
~
'OR
200
300
400
LOAD CAPACITANCE (pF)
5·29
500
3245
Typical System
Below is an example of a 64K x 18 bit memory system (each card is 16K x 18) employing the 3245 quad high voltage
driver for the chip enable inputs. A single 3245 package drives 16K x 9 bits. Ao through All are 2107B addresses.
CARD 0
CARD C
CARD B
-
(9 21078'5)-------+
(ROW 4LI
CARD A
CHIP ENABLE
(ROW JL)
(ROW JRI
CHIP ENABLE
CHIP ENABLE
(ROW 2LI
(ROW 2R)
CHIP ENABLE
CHIP ENABLE
(ROW 1LI
(ROW1RI
'CHIP ENABLE
n
CHIP E N A B L e U
SEETABlEl~_________________E~-,~~
SEETABLE1~----------------~E,~
DRIVER 1 RS("
DRIVER 2 (RS(J"
R
~----T-'-dr""">-__-+++~L....."J---'l/V'or-~
DRIVER 1 RSl2i ~..,...++.!.Qr......
DRIVER 2 (RS(411
CHIP ENAOLE
(ROW 2LI
TABLE 1.
)---'l/VI.,-~ CHIP ENABLE
(ROW 1LI
>----t-++--'lL....J
. .___-4===~L.JI--'V""---s
REFRESH;)
ENABLE ~---4-~"---j--------
:X -.: .: : : : : : : : : : : : .: :.: : : : : : : : : : :
=====2 : :
t
=~;= =:x:::::::==;==t=====tJ==
=::::::::: .: : : : =: : : : ==
On the decoding side, when the FSR pulse is widened, the
8th bit of the PGM word is detected and transmitted on the
SIGR lead. That output is latched until the next receiving
signaling frame.
r---
TS1 R
~---j
I•
The remaining 7-bits are decoded according to the value
given in the GGITT G733 recommendation. The SIGR lead
is reset to a TTL low level whenever the Godec is in the
power-down state.
"I
TSn R
192
r
~---- TSnR ----
TSI R
---4
CLKR~\~\JlSU1U'~
192
REC. SIGNAL FRAME
FSR
..JI
DR
:~~~~~~~=~==~==========~=====~~===~======:=~~::~:==~~~:=~~~=:=~::=:~~=_-~
\~\
_____________
SIGR
------------------------------------------"-"---
SIG R - - - - - - - - - - - -
----------- ----
D3 Framing
with the same bit clock distributed to all Godec's, whether
the microcomputer control mode or the direct control
mode is employed.
The number of clock pulses (GLKx, GLKR I delivered to the
Godec per frame must be a multiple of 8. In the case of the
03 framing format (193 bits/framel, one clock pulse per
frame must be suppressed (blanked) from the 1.544 Mb/s
bit clocks GLKx and GLKR. It is generally easiest to blank
the framing (193rdl bit in both cases. This pulse
suppression may be performed once at the system level,
Standby Mode -
?:I
XC
The framing pulse widths are always defined relative to
Godec bit clock transitions; whenever a pulse is blanked in
a Godec bit clock, any framing pulse which spans that
blanked bit clock interval must be extended beyond the
next bit clock transition.
Power Down
exception of the interface to the De and GLKe leads, to
allow the Godec to be reactivated.
The power consumption in the standby mode is typically
110mW.
To minimize power consumption and dissipation in large
systems, a standby mode is provided by loading a control
word (De I with a "1" in bits 1 and 2 locations. Most of the
Godec functions thereby become disabled, with the
Power-On Clear
(Voo or Vee) are removed or applied. The Godec thus
assumes'the power-down state upon application of the
positive power supplies and must be initialized in the
normal way for operation.
Whether the device is used in the direct or microcomputer
mode, an internal reset (power-on clear) is generated
whenever either of the two positive device power supplies
Precision Voltage Reference for the
D/A Converter
A gain setting op amp, programmed during manufacturing, "trims" the reference voltage source to the final
precision voltage reference value provided to the 0/ A
converter. The precision voltage reference determines the
initial gain and dynamic range characteristics described
in the A.G. Transmission Specification Section.
The voltage reference is generated on the chip and is
calibrated during the manufacturing process, The
technique uses the difference in sub-surface charge
density between two suitably implanted MaS devices to
derive a temperature stable and bias stable reference
voltage.
6-8
2910
APPLICATIONS
Circuit Interface
Auto Zero
~-~--~:=~--~~--~~~----,
The auto zero output (most significant bit or sign bit of the
AID conversion) integrated over a long time constant will
compensate for the DC offset inside the Codec I voltage
difference between the bottom of the DAC and GRDA,.
The above drawing shows a possible connection between
the VFx and Auto leads. The recommended values of the
auto zero components are:
~
VFX
8KHz
CO DEC
500i!
C,
'"F
CAP X
2000pF
R,
47KS2
DX
R3
R,
330n
470K~2
-DR
CAP1 R
C1 of 11'F, R1 of 47kO, R2 of 3300, and R3 of 470kfl.
CAP R
470pF
~I __~__V_F~R-+~
I
Filters Interface
The filters may be interfaced as shown in the circuit
interface diagram. Note that the output pulse stream is of
the non-return to zero type.
c,
100 PF
Ox Buffering
Holding Capacitors
For optimum idle channel noise performance it is
recommended that the Dx output of each Co dec be
buffered from the system PCM bus with an external threestate or open collector buffer. Each buffer can be enabled
with the appropriate Codec generated TSx signal. The
TSx signal may be used to activate zero code suppression
logic on the PCM bus.
For an 8KHz sampling system the transmit holding
capacitor CAPx should be 2000pF, 20%. The receive
holding capacitor CAPR should be 470pF, 20% for 32 timeslots and 8KHz sample rate or 560pF, 20% for 24 time-slots
and 8KHz sample rate. An additional capacitor C2 of
100pF, is required from the CAP2R lead to GRDA.
Grounding and Oecoupling Recommendations
VFx
1$~
ANALOG CKTS.
DIGITAL
CKTS.
To minimize the injection of digital logic noise into the
analog signal path the GRDA and GRDD external
connection should be made as close as practical to the
system supply ground .
+12V
+5V
. 1pF
Oecoupling
A 0.11'F bypassing capacitor from each power supply to
digital ground is generally recommended at each device.
This decoupling may be reduced based on actual board
design and performance.
-5V
Sufficient board level decoupling must be provided to
guarantee that power supply transients (including turn
on and off) do not exceed the absolute maximum ratings
of thedevice. A minimum of 11'F is recommended once per
board for each power supply. A pair of small switching
diodes (i n opposite di rections) between analog and digital
ground on a once-per-board basis is recommended to
maintain the two ground levels near the same value during
board insertion and removal.
CODEC
Grounding
Analog grounding is connected to the GRDA lead. The
GRDA and GRDD leads are not connected inside the 291 O.
An external connection is thus necessary outside the
Codec to tie all the analog ground lines to the common
return of the system GRDD.
6-9
2910
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............ -10°C to +80°C
Storage Temperature .............. -65°C to +150°C
All Input or Output Voltages
with Respect to VBB .................. -0.3 to +20V
Vee, Voo and Vss with
Respect to VBB ........................ -0.3 to +20V
Power Dissipation ........................... 1.35W
""COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
D.C. AND OPERATING CHARACTERISTICS
TA = O°C to +70°C, Voo = +12V
± 5%,
Vee = 5V
± 5%,
VBB = -5V ± 5%, GRDA = OV, GRDD = OV, unless otherwise specified.
DIGITAL INTERFACE
Limits
Symbol
Parameter
IlL
Low Level Input Current
IIH
High Level Input Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
Min. Typ.[11
Max.
Unit
10
p.A
VIN < VIL
VIN > VIH
10
p.A
+0.6
V
0.4
V
Test Conditions
V
+2.2
Dx, 10L=3.2mA
SIGR,IOL=0.5mA
TSx, 10L=1.6mA, open drain
PDN, 10L=0.5mA,open drain
VOH
Output High Voltage
2.4
V
Dx, IOH=30mA
SIGR, IOH=0.6mA
ANALOG INTERFACE
AIZ
Input Impedance when Sampling, VFx
125
Aoz
Output Impedance, VFR
100
VOL
Output Low Voltage, Auto
VOH
Output High Voltage, Auto
Vee
500
fl
In Series with CAPx to
GRDA, -3.1V < VIN < 3.1V
180
300
fl
-3.1V < Your < 3.1V
VBB
VBB
V
400kfl to GRDA
300
V
Vee
R1
Auto Zero Component
42
47
52
kfl
R2
Auto Zero Component
290
330
360
fl
330fl Recommended[2[
R3
Auto Zero Component
420
470
520
kfl
470kfl Recommended[2[
C1
Auto Zero Component
CAPx
Holding Capacitor, Transmit
1600
2000
2400
pF
8kHz Sampling, 2000pF
CAPR
Holding Capacitor, Receive
390
470
560
pF
8kHz Sampling, 32 TimeSlots, 470pF Recommended[2[
450
560
670
pF
120
pF
8kHz Sampling, 24 TimeSlots, 560pF Recommended [21
100pF Recommendedl 21
1.0
47kfl Recommended[21
p.F
R~commended[2[
C2
Bypass Capacitor
80
POWER DISSIPATION
1000
Standby Current
6
9
mA
leeo
Standby Current
5
8
mA
IBBO
Standby Current
2
4
mA
1001
Operating Current
11
16
mA
leel
Operating Current
13
21
mA
IBBI
Operating Current
4
6
mA
NOTES:
1. Typical Values are for TA = 25' C and nominal power supply values.
2. See Applications Circuit Interface for component connections.
6·10
Voo = 12.6V
Vee = 5.25V
VBB = -4.75V
Clock Frequency 2.048MHz
2910
A.C. CHARACTERISTICS
TA = O°C to +70° C, Voo = +12V± 5%, VCC =+5V± 5%, VBB=-5V± 5%, GRDA=OV, GRDD=OV, unless otherwise specified.
TRANSMISSION (Any two 2910 Codec's, end-to-end)
Limits
Symbol
Min. Typ.l1l
Parameter
SID
Signal/Total Distortion Ratio, C-message
Weighted (See Figure 1)
AG
Gain Tracking Error
(See Figure 2)
Max.
Fig. 1 Fig. 1
Unit
Test Conditions
dB
VFx=1.02KHz, Sinusoid
VFx=1.02KHz Sinusoid
-0.3
0.3
dB
-37dBmO::::VFx80
dB
Note 8
CT
NOTES:
1. Typical Values are for TA = 2SoC and nominal power supply values.
2. DR of Device Under Test (D.U.T.) driven with repetitive digital word sequence specified in CCITT recommendation G.711.
Measurement made at VFR output.
3. D.U.T. acts as both encoder and decoder (Dx=DR) in a digital loop-back configuration. Specified gain is in addition to normal (Sinx)/x
insertion loss.
4. Any 2910 as encoder; any other 2910 as decoder; both D.U.T.'s with separate supplies and at independent temperatures. Specified gain is in
addition to normal (Sinx)/x insertion loss.
S. (Sinx)/x with x = Measurement Frequency If! x ..
Sampling Frequency
6. D.U.T. Encoder; impose 200mV p-p, 1.02KHz on appropriate supply; measurement made at remote decoder output; encoder in idle
channel conditions.
7. D.U.T. acts as encoder and decoder; impose 200mV P-P. 1.02KHz on appropriate supply; measurement made at co-located decoder
output; encoder in idle channel conditions.
8. VFX of D.U.T. encoder = 1.02KHz. OdBmO. Co-located D.U.T. decoder under quiet channel conditions; measurement made at colocated decoder output.
6-12
2910
A.C. CHARACTERISTICS
TA = O°C to +70 e C, VOO = +12V ± 5%, Vcc
unless otherwise specified.
= +5V ± 5%,
= -5V ± 5%,
VBB
GRDA
= OV,
GRDD
= OV,
TIMING SPECIFICATION
CLOCK SECTION
Limits
Symbol
Parameter
tCY
Clock Period
Min.
Max.
485
tr, tf
Clo(;k Rise and Fall Time
tClK
Clock Pulse Width
215
5
tcoc
Clock Duty Cycle (tClK -;- tCY)
45
30
55
Units
Comments
ns
CLKx, CLKA (2.048MHz systems),
CLKc
ns
CLKx, CLKA, CLKc
ns
CLKx, CLKA, CLKc
%
CLKx, CLKA
TRANSMIT SECTION
Time Slot From Leading Edge of Transmit
Time Slot l1 )
tVFX
Analog Input Conversion
20
tozx
Data Enabled on TS Entry
Data Hold Time
50
80
180
230
ns
ns
tHzx
Data Float on TS Exit
75
205
ns
ClOAO
tSON
Time Slot X to Enable
30
220
ns
o < ClOAO < 100pF
tSOFF
Time Slot X to Disable
70
185
ns
tss
Signal Setup Time
0
ClOAO = 0
Relative to Bit-7 Falling Edge
tSH
Signal Hold Time
100
tFSO
Frame Sync Delay
15
100
6
6
tOHX
ns
0< CLOAO < 100pF
o < ClOAO > 100pF
=0
ns
Relative to Bit-8 Falling Edge
ns
FSx
RECEIVE AND CONTROL SECTIONS
tVFA
Analog Output Update
Time Slot From the Leading Edge of the
Channel Time Slot
ns
tOSA
Receive Data Setup
20
tOHA
Receive Data Hold
50
tSIGR
SIGA Update
tFSO
Frame Sync Delay
15
tosc
Control Data Setup
100
ns
tOHC
Control Data Hold
100
ns
ns
300
ns
100
ns
From the Trailing Edge of the
Channel Time Slot
NOTE:
1. The 20 time slot minimum insures that the complete AID conversion will take place under any combination of receive interrupt or
asynchronous operation of the Codec. Ifthe transmit channel Q!:l.!y is operated the AID conversion can be completed in a minimum of 11
time slots. Refer to the Codec Control General Requirement section for instructions on selting a channel in an idle condition.
6-13
2910
TIMING WAVEFORMS[1]
TRANSMIT TIMING
CLKx
FSX
FRAMESj=
"I
NON·SIGNALING
SIGNAL~N~
t FSD
--------.......,
FRAMES
RECEIVE TIMING
FSR~---.....,
tFSD
NON-SIGNALING
FRAMESj=
"I
SIGNAL;:~
--------t FSO
FRAMES
CONTROL TIMING
Notes: 1. All timing parameters referenced to 2.0V, except tHzx and tSOFF which reference a high impedance state.
6-14
inter
2911
PCM CODEC -
A LAW
8-BIT COMPANDED AID AND OfA CONVERTER
• Per Channel, Single Chip Codec
• ±5% Power Supplies: +12V, +5V, -5V
• CCITT G711 and G732 Compatible.
Even Order Bits Inversion Included
• Precision On-Chip Voltage Reference
• Low Power Consumption: 230mW Typ.
Standby Power: 110mW Typ.
• All Digital Inputs and Outputs TTL
Compatible
• Fabricated with Reliable N-Channel
MOS Process
• Microcomputer Interface with On-Chip
Time-Slot Computation
• 66dB Dynamic Range, with Resolution
Equivalent to 11-Bit Linear Conversion
Around Zero
The Intel® 2911 is a fully integrated PCM (Pulse Code Modulation) Codec (Coder-Decoder). fabricated with N-channel
silicon gate technology. The high density of integration allows the sample and hold circuits. the digital-to-analog
converter. the comparator and the successive approximation register to be integrated on the same chip. along with the
logic necessary to interface a full duplex PCM link.
The primary applications are in telephone systems:
• Transmission
• Switching
• Concentration
- 30/32 Channel Systems at 2.048 Mbps
- Digital PBX's and Central Office Switching Systems
- Subscriber Carrier/Concentrators
The wide dynamic range of the 2911 (66 dB) and the minimal conversion time (80 I'sec minimum) make itan ideal product
for other applications. like:
• Data Acquisition
• Telemetry
• Secure Communications Systems
• Signal Processing Systems
BLOCK DIAGRAM
PIN CONFIGURATION
TRANSMIT SECTION AID
®
r------l----t-.. TSx
VFx-......- - - i
® AUTO
SAM:LE
CD CAP 'Ix
HOLD
®CAP 2x--+----1
1--_ _ _-1
@
SUCCESSIVE
1--+_ Ox @l
APPROXIMATION
1--+_CLKx @
L-r-.----r-J--t-- FSx
r-'--,--I--Dc
@)
@
1--+_CL"c@
L ........---l-T~. PDN ®
@CAP1._-+_ _-I
@CAP2.--+---I
®
VF._-+--<
OPINNU'.lBER
6·15
r-l....-l--+--o.CLK• (J)
I--i-_
@
I--+_FS. @
2911
\'{,,,
': . . :,>,:'F:!d~;;'!,):
.
PIN DESCRIPTION
Pin No. Symbol
1
CAPlx
2
CAP2x
3
VFx
4
AUTO
Function
Description
Hold
Connections for the transmit holding capacitor. Refer to Applications Section.
Input
Analog input to be encoded
into a PCM word. The signal on this lead is sampled
at the same rate as the
transmit frame synchronization pulse FSx, and the
sample value is held in the
external capacitor connected to the CAPlx and
CAP2x leads until the encoding process is completed.
Output
Most significant bit of the
encoded PCM word (+5V
for negative, -5V for positive value). Refer to the
Codec Applications Section.
5
GRDA
Ground
Analog return common to
the transmit and receive
analog circuits. Not connected to GRDD internally.
6
VDD
Power
+12V, ±5%, referenced to
GRDD or GRDA, depending upon system grounding
considerations.
7
DR
Pin No. Symbol
Input
Receive PCM highway (serial bus) interface. The Codec serially receives a PCM
word (8-bits) through this
lead at the proper time
defined by FSR, CLKR, Dc,
and CLKc.
8
PDN
Output
Active high when the Codec is in the power down
mode. TTL interface. Open
drain output.
9
VFR
Output
Analog output. The voltage
present on VFR is the decoded value of the PCM
word received on lead DR.
This value is held constant
between two conversions.
6-16
Function
····.·i."\I-:~
'~
.... ,.
.
,'
De:.cr,PCI~
.'1.
Connections for.'tfl~, :~;'fl~f!
ceive holding cail'aC:if6F.i ..
Refer to the Applications"
Section.
10
CAP1R
11
CAP2R
12
GRDD
Ground
Ground return common to
the DC power supplies;
VBB. Vee. and VOD.
13
Ox
Output
Output of the transmit side
onto the send PCM highway (serial bus). The 8-bit
PCM word is serially sent
out on this pin at the proper
time defined by FSx. CLKx.
Dc. and CLKe. TTL threestate output.
14
TSx
Output
Normally high. this signal
goes low while the Codec is
transmitting an 8-bit PCM
word on the Ox lead. (Timeslot information used for
diagnostic purposes and
also to gate the data on the
Ox lead,) TTL interface.
open drain output.
15
Vee
Power
+5V. ±5%. referenced to
GRDD.
16
CLKR
Input
Master receive clock defining the bit rate on the receive PCM highway. Typically 2.048 Mbps for a carrier system. Maximum rate
2.1 Mbps, 50% duty cycle.
TTL compatible.
17
FSR
Input
Frame synchronization pulse
for the receive PCM highway. Resets the on-chip
time-slot counter for the
receive side.
Maximum
repetition rate 12 kHz.
TTL interface.
18
CLKx
Input
Master transmit clock defining the bit rate on the
transmit PCM highway. Typically 2.048 Mbps for a carrier system. Maximum rate
2.1 Mbps. 50% duty cycle.
TTL interface.
Hold
2911
Pin No. Symbol
19
20
Function
Description
Input
FSx
Frame synchronization pulse
for the transmit PGM highway. Resets the on-chip
time-slot counter for the
transmit side. Maximum
repetition rate 12 kHz. TTL
interface.
Function
21
Dc
Input
22
GLKc
Input
Data in~ul t6'pr6~!{a:i·A~he
Godec for the c.!;!.q~en,mdd~ VIH
+0.6
V
+2.2
Test Conditions
V
0.4
V
Dx,IOl=3.2mA
TSx, 10l=1.6mA, open drain
PDN, 10l =0.5mA,open drain
VOH
Output High Voltage
2.4
V
Dx, IOH=30mA
ANALOG INTERFACE
AIZ
Input Impedance when Sampling, VFx
125
100
300
500
0
In Series with CAPx to
GRDA, -3.1V < VIN < 3.1 V
180
300
Aoz
Output Impedance, VFR
0
-3.1V < VOUT < 3.1V
Val
Output Low Voltage, Auto
Vss
V
400kf1 to GRDA
VOH
Output High Voltage, Auto
V
R1
Auto Zero Component
42
Vcc
47
52
kO
47kO Recommended!2\
R2
Auto Zero Component
290
330
616
f1
470
520
kO
3300 Recommended i2 ]
470kO Recommended l21
R3
Auto Zero Component
420
C1
Auto Zero Component
1.0
CAPx
Holding Capacitor, Transmit
1600
2000
2400
pF
8kHz Sampling, 2000pF
Recommendedl 2!
CAPR
Holding Capacitor, Receive
390
470
560
pF
8kHz Sampling, 32 TimeSlots, 470pF Recommended i 21
450
560
670
pF
8kHz Sampling, 24 TimeSlots, 560pF Recommended 21
80
100
120
pF
100pF Recommended!21
C2
Bypass Capacitor
J.l.F
POWER DISSIPATION
1000
Standby Current
6
9
mA
leeo
Standby Current
5
8
mA
Isso
1001
Standby Current
Operating Current
2
4
mA
11
16
mA
leci
Operating Current
13
21
mA
Issl
Operating Current
4
6
mA
NOTES:
1. Typical Values are for T A = 25° C and nominal power supply values.
2. See Applications Circuit Interface for component connections.
6-23
Voo = 12.6V
Vce = 5.25V
Vss = -4.75V
Clock Frequency 2.048MHz
2911
.
,
A.C. CHARACTERISTICS
TA = O°C to +70°C, Voo = +12V ± 5%, Vcc = +5V ± 5%, 'veB .5V'±'Sb#,~"
GRDA = OV, GRDD = OV, unless otherwise specified,
""
';,
=
TRANSMISSION, GAIN AND DYNAMIC RANGE
"
,
"
"
""
Limits
Symbol
SID
Min,
Parameter
Signal to Total Distortion Ratio. See
Figure 2. CCITT G.712 Method 2
(Sinusoidal method),
Typ.[1)
NIC
Idle Channel Noise
AOR
Output Dynamic Range, VFR
AORT
AOR Variation with Temperature
:
Max.
Unit
35
dB
29
24
dB
dB
Gain Tracking Deviation from Gain at
OdBmO. See Figure 1. CCITT G.712
Method 2 (Sinusoidal method).
aG
2.14
2.16
'{,~:.'
"
±0.3
dB
±0.7
dB
±2.1
dB
-73
dBmOp
2.18
-.22
VRMS
" ,
Test Conditions
Signal Level OdBmO to
-30dBmO
Signal Level -40dBmO
Signal Level -45dBmO
Signal Level +3dBmO to
-40dBmO
SignaJ Level -40dBmO to
-50dBmO
Signal Level -50dBmO to
-55dBmO
With Auto Zerol 2 )
23° C, Nominal Supplies
mVRMs/oC Relative to 23° C
AORS
AOR Variation with Supplies
±18
mVRMS
GSL
Self Loop Gain
-.24
-,20
-.16
dB
VFx=-dBmO, 1.02KHz13)
GEE
End-to-End Codec Gain
-.4
-.3
-.2
dB
23°C, Nominal Supplies[41
GEET
GEE Variation with Temperature
.0010
.0018
dBrC
GEES
GEE Variation with Supplies
±.07
±,13
dB
Supplies ±5%14)
GFR
Decoder Frequency Response Departure
from Ideal (Sinx)/x, VFR
dB
300 Hz 80
'"
Supplies ±5%
Relative to 23° C[4)
NOTES:
1, Typical Values are for TA = 25°C and nominal power supply values.
2. If all Auto-Zero components are removed and VFx is direct coupled, the encoder tends to bias itself away from a decision level
(hysteresis), The idle channel noise is then typically -85dBmOp, but will be dependent on the D.C. offset of the PCM transmit
filter output provided to VFx.
3, D,U, T, acts as both encoder and decoder (Dx=DR) in a digital loop-back configuration. Specified gain is in addition to normal (Sinx Ilx
insertion loss.
4, Any 2911 as encoder; any other 2911 as decoder; both D.U,T.'s with separate supplies and at independenttemperatures. Specified gain
is in addition to normal (Sinx)/x insertion loss.
5, (Sinx)/x with x = Measurement Frequency ((I x 7r
Sampling Frequency
6, VFX of D,U.T, encoder = 1.02KHz, OdBmO. Co-located D.U.T. decoder under quiet channel conditions; measurement made at colocated decoder output.
aG
(dB)
+3
+11---+--1""~
celT
RECOMMENDATION
G.712
INPUT
LEVEL
r~t,;--:in---+';---:;';--dBmo
-20
-10
INPUT lEVEL (dBmO)
-3
LEGEND
~~~'l.:CCITTG.712
- - - 2911
Figure 2. -Signal/Total Distortion Ratio
Figure 1, Gain Variation (aG) vs. Signal Level
Reference Level OdBmO
6-24
,
",;
2911
A.C. CHARACTERISTICS
TA = O°C to +70°C, VDD
GRDA = OV, GRDD = OV, unless otherwise specified.
= +12V ±
5%, Vcc
= +5V ±
5%, VBB~ .5V'± 5%,
TIMING SPECIFICATIONS AND WAVEFORMS[l]
CLOCK AND TRANSMIT SECTION
Limits
Symbol
Parameter
Min.
Max.
485
Units
Comments
ns
CLKx, CLKR (2.048MHz systems),
CLKc
ns
CLKx, CLKR, CLKc
tCY
Clock Period
tr, tf
Clock Rise and Fall Time
tClK
Clock Pulse Width
215
tCDC
Clock Duty Cycle (tClK -;- tCyl
45
tVFX
Analog Input Conversion
20
tDZX
tDHX
Data Enabled on TS Entry
Data Hold Time
50
80
180
230
ns
ns
tHZX
Data Float on TS Exit
75
205
ns
CLOAD = 0
tSON
Time Slot X to Enable
30
220
ns
0< CLOAD < 100pF
185
ns
ns
ClOAD = 0
Relative to Bit-7 Falling Edge
ns
Relative to Bit-8 Falling Edge
ns
FSx
5
tSOFF
Time Slot X to Disable
70
tss
Signal Setup Time
0
tSH
Signal Hold Time
100
tFSD
Frame Sync Delay
15
30
55
ns
CLKx, CLKR, CLKc
%
CLKx, CLKR
Time Slot From Leading Edge of Transmit
Time Slot 121
100
o < ClOAD < 100pF
0< CLOAD > 100pF
Notes'
1. All timing parameters referenced to 2.0V. except tHZX and tSOFF which reference a high Impedance state
2. The 20 time slot minimum insures that the complete AID conversion will take place under any combination of receive interrupt or
asynchronous operation of the Codee. If the transmit channel ~ is operated the AID conversion can be completed in a minimum of 11
time slots. Refer to the Codec Control General Requirement section for instructions on setting a channel in an idle condition.
6-25
2911
";i
A.C. CHARACTERISTICS
TA = O°C to +70°C, Voo
GRDA = OV, GRDD = OV, unless otherwise specified.
= +12V ±
5%, Vee
= +5V ± 5'Oio:Vai1'5~~;:~9..
' ",:' ,
'/,;:-.,----1
VFxlGSx
VFxO
--t-----'
Vee
0
PWRO+
CD
PWRO--i""'f""-"III'v--;
PDWN@
PIN NAMES
eLK
VFX 1+. VFx 1GSx
VFxD
VFRI
VFRO
PWRI
@
ANALOG INPUTS
GAIN CONTROL
ANALOG OUTPUT
ANALOG INPUT
ANALOG OUTPUT
DRIVER INPUT
PWRO+, PWRO- DRIVER OUTPUT
ClK
ClKO
PWDN
Vee
V••
GRDD
GRDA
CLOCK INPUT
CLOCK SELECTION
POWER DOWN
POWER (+5V)
POWER (-5V1
DIGITAL GROUND
ANALOG GROUND
@
CLKO@
Vaa
OPIN NUMBER
Vee
GRDD GRDA
00@@
AT & T is a registered trademark of American Telephone and Telegraph Corporation.
6-27
2912
PIN DESCRIPTION
Pin
No.
Symbol
Function
Description
VFxl+
Input
Analog input of the transmit
filter. The VFxl+ signal comes
from the 2 to 4 wire hybrid in
the case of a 2 wire line and
goes through the 50/60Hz
notch and the antialiasing
filter before being sent to the
Codec for encoding.
2
VFxl"
Input
Inverting input of the gain adjustment operational amplifier
on the transmit filter.
3
GSx
Output
Output of the gain adjustment
operational amplifier on the
transmit filter. Used for gain
setting of the transmit filter.
Output
4
5
PWRI
Input
6
PWRO+
Output
7
PWRO-
Output
Pin
No.
Symbol
Function
Description
10
VFRI
Input
Analog input of the receili&
filter, interface to the Codec
analog output for PCM applications. The receive filter provides the
,.~
Si~X
correction
needed for sample and hold
type Codec outputs to give
unity gain. The input voltage
range is directly compatible
with the Intel® 2910 and 2911
Codecs.
11
GRDD
Ground
Digital ground return for internal clock generator.
12
ClKl 1 1
Input
Clock input. Three clock frequencies can be used:
1.536MHz, 1.544MHz or
2.048MHz; pin 14, ClKO, has
to be strapped accordingly.
High impedance input, TTL
voltage levels.
13
PDWN
Input
Control input for the stand-by
power down mode. An internal pull up to +5V is provided for interface to the
Intel® 2910 and 2911 PDWN
outputs. TTL voltage levels.
14
ClKO[ll
Input
Non-inverti ng side of the power amplifiers. Power driver
output capable of directly
driving transformer hybrids.
Clock (pin 12, ClK) frequency
selection. If tied to VSB, ClK
should be 1.536MHz. If tied to
Ground, ClK should be 1.544
MHz. If tied to Vee, ClK
should be 2.048MHz.
15
GRDA
Ground
Inverting side of the power
amplifiers. Power driver output capable of directly driving
transformer hybrids.
Analog return common to the
transmit and receive analog
circuits. Not connected to
GRDD internally.
16
VFxO
Output
Analog output of the transmit
filter.
The output voltage
range is directly compatible
with the Intel® 2910 and 2911
Codecs.
Analog output of the receive
filter. This output provides a
direct interface to electronic
hybrids. For a transformer hybrid application, VFRO is tied
to PRWI and a dual balanced
output is provided on pins
PWRO+ and PWRO-.
Input to the power driver
amplifiers on the receive side
for interface to transformer
hybrids. High impedance input. When tied to Vss, the
power amplifiers are powered
down.
8
Vss
Power
-5V ± 5% referenced to
GRDA
9
Vee
Power
+5V ± 5% referenced to
GRDA
NOTE:
1. The three clock frequencies are directly compatible with the Intel® 2910 and 2911 Codecs. The
following table should be observed in selecting the clock frequency.
Codec Clock
Clock Bits/Frame
2912 ClK, Pin 12
2912 ClKO, Pin 14
1.536 MHz
1.544 MHz
2.048 MHz
192
193
256
1.536 MHz
1.544 MHz
2.048 MHz
VBB (-5V)
6-28
GRDD
VCC (+5V)
2912
FUNCTIONAL DESCRIPTION
\,%:'!:I', ",\,~
A stand-by, power down mode is incl~dedih th~\~~l;!;anct
can be directly controlled by the 2910/291 H;;?decs::' .•\ii';:l.,!~:\·
The 2912 provides the transmit and receive filters found on
the termination of a PCM line or trunk. The transmit filter
performs the anti-aliasing function needed for an 8KHz
sampling system, and the 50/60Hz rejection. The receive
filter has a low pass transfer characteristic and also
provides the Sinx/x correction necessary to interface the
Intel 2910 (I' Law) and 2911 (A Law) Codecs which have a
non-return-to-zero output of the digital to analog
conversion. Gain adjustment is provided in the receive
and transmit directions.
r
The 2912 can interface directly with a transfor~~i'hybri~' '0;"
(2 to 4 wire conversion) or with electronic hybrids; in the .'
latter case the power dissipation i!l.-significantly reduced
by powering down the output amplifier provided on the
2912.
PABX I
I
I
I
c.o,
SWITCHING SYSTEM I CHANNEL BANK
--,
SUPERVISION
PROTECTION
L-':=~r--------r-1
8ATTERY
TELEPHONE SET
I
I
I
L
TYPICAL LINE TERMINATION
FILTER OPERATION
Transmit Filter Input Stage
load impedance connected to the amplifier output must be
greater than 10KO in parallel with 20pF. The input signal
on lead VFxl+ can be either AC or DC coupled. The input
Op Amp can also be used in the inverting mode or
differential amplifier mode. The remaining portion of the
transmit filter provides a gain of +3dB in the pass band.
The input stage provides gain adjustment in the passband.
The input operational amplifier has a common mode
range of ±2.2 volts, a DC offset of less than 25mV, a voltage
gain greater than 2000 and a unity gain bandwidth of
2M Hz. It can be connected to provide a gain of 20dB
without degrading the noise performance of the filter. The
2912
.....
VFx l +
t.....
VFxl-
GSx
R2
R,
TRANSMIT FILTER GAIN ADJUSTMENT
6-29
R2
GAIN'" 1 + R,
2912
.,'\
,'.
iP',: :~,:r.." ',,~
Transmit Filter Transfer Characteristics
50Hz/60Hz Notch -
Tran.~( Fi'I'ttr-<;'~'i,''' .
.
The transmit filter has a notc~ secti~~ to.~~~(~~9..
60Hz components of the ,"put signaL ~ A· t.nInl~l If ~.
attenuation of. 26dB is provided at 60Hz. A(50Hl':'~he i!'~~
minimum attenuation is 20dB. The gain at 200Hz,)s 'c W .,
between -.125dB and -l.adB. (All gain figures are relative"'··
to the gain at 1kHz).
The transmit section of the filter provides a passband
flatness and stopband attenuation which exceeds the
ATT~ D3 and D4 specification and is compatible with the
CCITT G712 recommendation. The 2912 specification
meets the digital class 5 central office switching systems
requirements. The transmit filter transfer characteristics
and specifications are shown in the diagram below.
+.125dB
+.125dB
3000Hz
300Hz
+.OJdB
3300Hz
~~~;;~$~~~~~;:;~~~'t',-·lOdB
.,
3400Hz
EXPANDED
SCALE
-1
-1
-10
-20
-40
FREQUENCY {Hzl
TRANSMIT FILTER TRANSFER CHARACTERISTICS
Transmit Filter Output Stage
The voltage range of the output signal on the VFxO lead is
±3.2 volts. The DC offset is less than 200mV. It is
recommended that the VFxO output be capacltively
coupled to the VFx input of the Intel®2910 and 2911
Codecs.
6-30
2912
~";i'
'~:'i'>i:.L'h·",
'., ... ,
~f~
Receive Filter Transfer Characteristics
"'/~
"
The receive section of the filter provides a passband
flatness and stopband rejection which exceeds the ATT@
03/04 specification and is compatible with the CCITT
G712 recommendation when used with a decoder which
contains a sample/hold amplifier at its output. The filter
contains the required compensation forthe Sinx response
'~
'
,
istics and specifications.
the decoder. as shown in the diagram below,
x
+2
/
;~:B
:s
~
i!:
..:
I
I
I
I
/
+.125dB
300Hz
//
+2
/1
+1
I
+.125dB
3000Hz
~
I
I
EXPANDED
SCALE
+.03dB
3300Hz
-'5dB~
iii
~
/
TYPICALFILTER"1
;1
TRANSFER FUNCTION - - - . "
+1
200Hz
~
300 Hz
J
-1
-1
"
0
0W
>
;::
~
w
a:
z
;;:
"
-10
,~,
filte~"t(a?$fef:", ~~"
including the SI;"; t;e~:~~~J:;~~i
of such decoders, The receive
TYPICAL FILTER TRANSFER
FUNCTION''' WHEN MULTIPLIED
-10
-20
-20
WHICH IS THE Si:x OUTPUT RESPONSE
OF THE INTEL 2910 AND 2911 CODECS
-30
.............~-30
-40
-40
FREQUENCY (Hz)
NOTES:
" TYPICAL TRANSFER FUNCTION OF THE RECEIVE FILTER AS A SEPARATE COMPONENT,
2. TYPICAL TRANSFER FUNCTION OF THE RECEIVE FILTEA DRIVEN BY THE SAMPLE AND
HOLD OUTPUT OF THE INTEL 2910 AND 2911 CODECS, THE COMBINED FILTERICODEC
RESPONSE MEETS THE STATED SPECIFICATIONS,
RECEIVE FILTER TRANSFER CHARACTERISTICS
6-31
"
,J,'.
.',,'"
2912
Receive Filter Output
The VFRO lead is capable of driving high impedance
electronic hybrids. The gain of the receive section from
VFRI to VFRO is:
2912
SinH ( 8600 )
which when multiplied by the output response of the Intel
2910 and 2911 Codecs results in a OdB gain in the
pass band. The filter gain can be adjusted downward by a
resistor voltage divider connected as shown. The total
resistive load RT on VFRO should not be less than 10kn.
Z == LOAD
RECEIVE FILTER OUTPUT GAIN ADJUSTMENT
Receive Filter Output Driver Amplifier Stage
VFRO
A balanced power amplifier is provided in order to drive
low-impedance loads in a bridged configuration. The
receive filter output VFRO is connected through gain
setting resistors Rl and R2 to the amplifier input PWRI.
The input voltage range on PWRI is±3.2volts and the gain
is 6dB for a bridged output. With a 20kn load connected
between PWRO+ and PWRO-, the maximum voltage swing
across the load is ±6.4 volts. With a 600.0 load connected
between PWRO+ and PWRO-, the maximum voltage swing
across the load is ±5.0 volts. The series combination of Rs
and the hybrid transformer must present a minimum A.C.
load resistance of 600.0 to the amplifier in the bridged
configuration. A typical connection of the output driver
amplifiers is shown below. These amplifiers can also be
used with loads connected to ground.
2912
R,
PWRI
R2
Rs
-=-
PWRO+
PWRO-
R" R2 GAIN SETTING RESISTORS
Rs SERIES LOAD RESISTOR
The power amplifier should be deactivated when not
utilized to save power. This is accomplished by tying the
PWRI pin to VBB.
TYPICAL CONNECTION OF OUTPUT
DRIVER AMPLIFIER
Power Down Mode
When power is restored, the settling time of the 2912 is
typically 15ms.
Pin 13, PDWN, provides the power down control. When
the signal on this lead is brought high, the 2912 goes into a
standby, power down mode. Power dissipation is reduced
to 55mW. In the stand-by mode, all outputs go into a high
impedance state. This features allows multiple 2912's to
drive the same analog bus on a time-shared basis.
The PDWN interface is directly compatible with the Intel
2910 and 2911 PDWN outputs. Only one command from
the common control is then necessary to power down
both the Codec and the Filters of the line or trunk
interface.
6-32
2912
APPLICATIONS
Circuit Interface
(Example 1)
2910
SIGx - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
SIG. - - - - - - - - - - - - - - - - - - - - - , . - - - - - - - t - - V D D
NG
i-----,
~
L
-,
I
I
I
-=-
DIGITAL
INTERFACE
I
I
I
...J
TIP
~----------------~---~c
~----------------------GRDD
~------------------------~B
~--------------------------------GRDA
TYPICAL liNE INTERFACE USING A 2910 CODEC AND 2912 FilTER AND TRANSFORMER-RESISTOR HYBRID.
Codec Interface
Transformer Interface (Example 1)
The 2912 PCM Filter is designed to directly interface to the
2910 and 2911 Codecs as shown above. The transmit path
is completed by connecting the VFxO output ofthe 2912 to
the coupling capacitor of the auto zero circuit associated
with the 2910 and 2911 codecs. The receive path is
completed by directly connecting the codec output VFR to
the receive input of the 2912 VFRI. The PWDN input of the
2912 should be connected to the PWDN output of the
codec to allow the filter to be put in the power-down
standby mode under control of the codec.
The diagram above shows a typical interface of the 2912
Filter to a transformer. This connection can provide
+8dBm into a 600n line. The functions of the resistors in
example 1 are as follows:
Clock Interface
Rs is a resistor which injects the balance network signal
into the transmit path to perform the 214 wire conversion.
R,. R2 are gain setting resistors for the transmit filter input
stage. Transmit gain equals - R2/R,. The transmit filter
provides an additional 3.0dB of gain.
R3. R4 are attenuation setting resistors for the receive
filter. Receive gain equals R3/(R3+R4).
To assure proper operation. the ClK input of the 2912
should be connected to the same clock provided to the
receive bit clock. ClKR of 2910 or 2911 Codec as shown
above. The ClKO input of the 2912 should be set to the
proper voltage depending on the standard clock
frequency chosen for the codec and filter. See the clock
selection table in the Pin Description section.
RL is a 600n load resistor through which the balanced
driver amplifier stage drives the transformer winding.
6-33
2912
Grounding and Decoupling
Recommendations
Analog grounding is connected to the GRDA leads. The
GRDA and GRDD leads are not connected inside the 2912.
An external connection is thus necessary outside the
Filter to tie all the analog ground lines to the common
return of the system GRDD. To minimize the injection of
digital logic noise into the analog Signal path the GRDA
and GRDD external connection should be made as close
as practical to the system supply ground.
vee
.05JlF
The GRDA of the 2912 Filtershould betied tothe GRDAof
the 2910 or 2911 Codec as shown above. Likewise, the
GRDD pins of the Codec and Filter should be connected.
Analog gain setting or 2/4 wire circuits associated with the
filter should have a ground path to GRDA.
GRDD
GRDA
.05,uF
A 0.05J.lF bypassing capacitor from each power supply to
analog ground GRDA is generally recommended at each
2912 device. This decoupling may be reduced based on
actual board design and performance. Sufficient board
level decoupling must be provided to guarantee that
power supply transients (including turn on and turn off)
do not exceed absolute maximum ratings of the device. A
minimum of 1J.lF is recommended once per board for each
power supply.
v••
FILTER
2912
Transformer Interface (Example 2)
,...-----,
TRANSFORMER
The diagram shows an alternative interface of the 2912
Filter to a transformer. This connection can provide
+5.75dSm into a 600n line. The functions of the resistors
in example 2 are as follows:
I
I
I
I
I
RING~i
R1 = R2. The matching maintains hybrid balance.
R3 = R4. The gain setting for the transmit filter input stage
is performed by R2 and R4. Transmit gain equals - R4/R2.
The transmit filter provides an additional 3.0dS of gain.
L
-
~
-=-
Rs = R7 = 2Rs. Each power amplifier drives a load equal to
Rs.
-
_,
,...
I
I
:
I
..J
I
Ra, Rs are attenuation setting resistors for the receive
filter. Receive gain equals Rs/(Ra+Rs).
TIP
:
I
IL ____ _
6-34
2912
ABSOLUTE MAXIMUM RATINGS*
'COMMENT:
Temperature Under Bias ............ -10°C to +80°C
Storage Temperature .............. -65° C to +150° C
Supply Voltage with Respect to Vss .. -0.3V to +14.0V
All Input and Output Voltages with
Respect to Vss .................... -0.3V to +14.0V
All Output Currents ......................... ±50mA
Power Dissipation ........................... 1 Watt
Stresses above those listed under "Absolute M~x,{rrium
Rating" may cause permanent damage to the dl/vice. This
is a stress rating only and functional operation oft/Je: device at these or at any other condition above those iria;·
cated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA = O°C to +70°C, Vcc = +5V ± 5%, Vss = -5V ± 5%, GRDA = OV, GRDD = OV, unless otherwise specified.
DIGITAL INTERFACE
Limits
Symbol
Parameter
Typ.!1!
Min.
Max.
Unit
Ilic
Input Load Current
(except PDWNi
Test Conditions
10
JJ.A
VIN = VIL MIN to VIH MAX
Ilia
Input Load Current, CLKO
10
JJ.A
VIN = Vss to VIH MAX
IliP
Input Load Current, PDWN
-100
JJ.A
VIN = VIL MIN to VIH MAX
VIL
Input Low Voltage (except CLKOl
0.8
V
VIH
Input High Voltage (except CLKOl
2.2
VILa
Input Low Voltage, CLKO
Vss
Vila
VIHO
V
VSS+O.5
V
Input Intermediate Voltage, CLKO GRDD-o.5
0.8
V
Input High Voltage, CLKO
Vcc
V
Typ.!1!
Vcc-O.5
POWER DISSIPATION
Limits
Max.
Unit
Icco
Vcc Standby Current
6
9
mA
PDWN = VIH MIN
Isso
Vss Standby Current
5
8
mA
PDWN = VIH MIN
Icc1
'Icc Operating Current, Power
Amplifiers Inactive
21
33
mA
PWRI = Vss
ISS1
Vss Operating Current, Power
Amplifiers Inactive
21
33
mA
PWRI = Vss
ICC2
Vcc Operating Current
28
44
mA
ISS2
Vss operating Current
28
44
mA
Symbol
Parameter
Min.
NOTE: 1. Typical values are for TA = 25° C and nominal power supply values.
6-35
Test Conditions
2912
,
D.C. AND OPERATING CHARACTERISTICS
TA
= O°C to +70°C, Vee = +5V ±
5%, VBB
= -5V ± 5%,
GRDA
= OV,
GRDD
= OV,
..
unless otherwi~e'sp~cif,jed.
"
1':',1
ANALOG INTERFACE, TRANSMIT FILTER INPUT STAGE
"ft)~:h
"d'
Symbol
Parameter
IBXI
Input Le,akage Current, VFxl+, VFxl-
Rixi
Input Resistance, VFxl+, VFxl-
VOSXI
Input Offset Voltage, VFxl+, VFxl-
Min.
Typ.l1]
"
Max.
100
10
Unit
nA
Test Conditions
-2.2V < VIN < 2.2V
MO
25
mV -2,2V < VIN < 2.2V
PSRR1
Power Supply Rejection, GSx
45
dB
CMRR
Common Mode Rejection, VFxl+, VFxl-
45
dB
AVOL
DC Open Loop Voltage Gain, GSx
fe
Open Loop Unity Gain Bandwidth, GSx
VOXI
Output Voltage Swing, GSx
CLXI
Load Capacitance, GSx
RLXI
Minimum Load Resistance, GSx
-2.2V < VIN < 2.2V
2000
2
MHz
±2.5
V
20
pF
kO
10
RL;:: 10kO
Minimum RL
ANALOG INTERFACE, TRANSMIT FILTER
Symbol
Parameter
Typ.l1]
Max.
Unit
Rox
Output Resistance, VFxO
400
0
Vosx
Output DC Offset, VFxO
200
PSRR2
Power Supply Rejection of Vee at
1kHz, VFxO
30
35
PSRR3
Power Supply Rejection of VBB at
1kHz, VFxO
25
30
CLX
Load Capacitance, VFxO
RLX
Minimum Load Resistance, VFxO
Vox
Output Voltage Swing, 1kHz, VFxO
Min.
Test Conditions
mV VFxl+ Connected to GRDA,
Input Op Amp at Unity Gain
dB
dB
20
10
pF
kO
Minimum RL
±3.2
V
RL ;:: 1OkO or with 2910 or 2911
Max,
Unit
1
p.A
ANALOG INTERFACE, RECEIVE FILTER
Symbol
IBR
Parameter
Min.
Typ.l1]
Input Leakage Current, VFRI
RIR
Input Resistance, VFRI
ROR
Output Resistance, VFRO
1
100
VOSR
Output DC Offset, VFRO
200
PSRR4
Power Supply Rejection of Vee at
1kHz, VFRO
30
35
PSRRs
Power Supply Rejection of VBB at
1kHz, VFRO
25
30
CLR
Load Capacitance, VFRO
RLR
Minimum Load Resistance, VFRO
VOR
Output Voltage Swing, VFRO
MO
dB
10
pF
kO
±3.2
6·36
0
mV VFRI Connected to GRDA
dB
20
NOTE:
1. Typical values for TA = 25° C and nominal power supply values,
Test Conditions
-3.2V < VIN < 3.2V
V
Minimum RL
RL = 10kO
2912
D.C. AND OPERATING CHARACTERISTICS
TA = O°C to +70°C, Vee = +5V ± 5%, VBB = -5V ± 5%, GRDA = OV, GRDD = OV, unless otherwise specified.
ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE
Symbol
Parameter
IBRA
I nput leakage Current, PWR I
Typ.i 11
Min.
Max.
Unit
3
I'A
RIRA
Input Resistance, PWRI
RORA
Output Resistance, PWRO+, PWRO-
VOSRA
Output DC Offset, PWRO+, PWRO-
75
mV
CLRA
load Capacitance, PWRO+, PWRO-
100
pF
Output Voltage Swing Across RL,
±3.2
V
RL = 10kO
PWRO+, PWRO- Single Ended
Connection
±2.9
V
RL = 6000
±2.5
V
RL = 300kO
Output Voltage Swing, PWRO+, PWROBalanced Output Connection
±6.4
±5.8
V
V
RL = 20kO
RL = 12000
±5.0
V
RL = 6000
VORA1
VORA2
10
Test Conditions
-3.2V < VIN < 3.2V
MO
1
0
IloUTI <10mA
-3.0V < VOUT < 3.0V
PWRI Connected to GRDA
RL Connected
to GRDA
RL Connected
Between PWRO+
and PWRO-
A.C. CHARACTERISTICS
TA = O°C to +70°C, Vee = +5V
Clock Input Frequency: ClK =
ClK =
ClK =
± 5%, VBB
1.536MHz
1.544MHz
2.048MHz
= -5V ± 5%, GRDA = OV, GRDD = OV, unless otherwise specified.
± 0.1%, ClKO = VILO (Tied to VBB)
± 0.1%, ClKO = VIIO (Tied to GRDD)
± 0.1%, ClKO = VIHO (Tied to Vee)
TRANSMIT FILTER TRANSFER CHARACTERISTICS
Symbol
GRX
Parameter
Gain Relative to Gain at 1 kHz
Below 50Hz
50Hz
60Hz
200Hz
300Hz to 3000Hz
3300Hz
3400Hz
4000Hz
4600Hz and Above
(See Transmit Filter Transfer Characteristics description section
for graph)
Min.
Typ.l11
-1.8
-0.125
-0.65
-1.4
2.9
3.0
Max.
Units
-10
-20
-26
-0.125
0.125
0.03
-0.1
-14
-32
dB
dB
dB
dB
dB
dB
dB
dB
dB
3.1
dB
Test Conditions
OdBmO Input Signal
Gain Setting Op Amp at
Unity Gain
OdBmO Signal'" 1.1 VRMS
I nput at VFxlOdBmO Signal'" 1.6 VRMS
Output at VFxO
GAX
Absolute Passband Gain at 1kHz, VFxO
GAXT
Gain Variation with Temperature
at 1 kHz
GAXS
Gain Variation with Supplies at 1 kHz
CTRT
Cross Talk, Receive to Transmit,
Measured at VFxO
Nex1
Total C Message Noise at Output, VFxO
9
12
dBrncO Gain Setting Op Amp at
Nex2
Total C Message Noise at Output, VFxO
10
13
dBrncO Gain Setting Op Amp at
DDX
Differential Envelope Delay, VFxO
1 kHz to 2.6kHz
80
I'S
DAX
Absolute Delay at 1 kHz, VFxO
130
I'S
DPX1
Single Frequency Distortion Products
-48
dB
OdBm Input Signal at 1 kHz
DPX2
Single Frequency Distortion Products
at Maximum Signal level of
+3dBmO at VFxO
-45
dB
0.16 VRMS 1kHz Input Signal at
VFxl-, Gain Setting Op Amp at
20dB Gain. The +3dBmO signal
at VFxO is 2.24 VRMS.
dB/oC OdBmO Signal level
.0005
dBIV OdBmO Signal level,
Supplies ±5%
.05
-60
dB
[21
121
See next page for NOTES.
6-37
VFRI = 1.6 VRMS, 1 kHz Input
VFxl+, VFxl- Connected
to GSx, GSx Connected through
10kO to GRDA
Unity Gain
20dB Gain
2912
A.C. CHARACTERISTICS
TA = O°C to +70°C, Vee = +5V ± 5%, VBB = -5V ± 5%, GRDA = OV, GRDD = OV, unless otherwise speclftoo. '
",,,'
'
Clock Input Frequency: CLK = 1.536MHz ± 0.1%, CLKO = VILO (Tied to V B B ) " "
CLK = 1.544MHz ± 0.1%, CLKO = Vila (Tied to GRDD)
CLK = 2.048MHz ± 0.1%, CLKO = VIHO (Tied to Vee)
RECEIVE FILTER TRANSFER CHARACTERISTICS (See Receive Filter Transfer Characteristics description section
for graph)
Symbol
GRR
Parameter
Gain Relative to Gain at 1 kHz with
Sinx/x Correction of 2910 or 2911
Below 200Hz
200Hz
300Hz to 3000Hz
3300Hz
3400Hz
4000Hz
4600Hz and Above
Min.
Typ.l11
Max.
Units
Test Conditions
OdBmO Input Signal
-0.5
-0.125
-0.65
-1.4
-0.1
0.125
0.125
0.125
0.03
-0.1
-14
-30
dB
dB
dB
dB
dB
dB
dB
+0.1
dB
GAR
Absolute Passband Gain at 1kHz, VFRO
GART
Gain Variation with Temperature
at 1kHz
GARS
Gain Variation with Supplies at 1 kHz
CTTR
Cross Talk, Transmit to Receive,
Measured at VFRO
NeR
Total C Message Noise at Output, VFRO
DOR
Differential Envelope Delay, VFRO,
1 kHz to 2.6kHz
100
DAR
Absolute Delay at 1 kHz, VFRO
130
",s
DPR1
DPR2
Single Frequency Distortion Products
Single Frequency Distortion Products
at Maximum Signal Level of
+3dBmO at VFRO
-48
-45
dB
dB
0
.0005
(Sin
Input at VFR I
OdBmO Signal'" 1.6 VRMS
Output at VFRO
dBIV OdBmO Signal Level, Supplies
±5%
-60
12
dB
VFxO = 2.2 VRMS, 1 kHz Output.
VFRI Connected to GRDA.
dBrncO VFRO Output or PWRO+ and
[21 PWRO- Connected with Unity
Gain
",s
OdBm Input Signal at 1 kHz
+3dBmO Signal Level of
2.24 VRMS, 1 kHz Input at VFRO
NOTES:
1. Typical values are for TA = 25° C and nominal power supply values.
2. A noise measurement of 18dBrnc into a 600n load at the 2912 device is equivalent to 12dBrncO.
6-38
If)
f
211"(8000) 211"(8000)
dBfOC dB/oC OdBmO Signal Level
.05
9
OdBmO Signal'" 1.6 VRMS x
MCS-4/40TM
Microprocessor
7
TABLE OF CONTENTS·
Central Processing Unit
4040 Single Chip 4-Bit P·Channel Microprocessor ............................................... " 7-3
4004 Single Chip 4-Bit P·Channel Microprocessor ................................................. 7-4
Input/Output
4003 10·Bit Shift Register/Output Expander ...................................................... 7-5
4265 Programmable General Purpose I/O Device .................................................. 7-6
4269 Programmable Keyboard Display Device ....................... , ............................ 7-7
Peripherals
4201 A Clock Generator ....................................................................... 7-8
4289 Standard Memory Interface ............................................................... 7-9
RAMs
4002 320·Bit RAM and 4-Bit Output Port. ......................................................... 7-10
ROMs
4001256 x 8 Mask Programmable ROM and 4-Bit I/O Port. .......................................... 7-11
43081024 x 8 Mask Programmable ROM and Four 4-Bit I/O Ports ..................................... 7-13
4316A/2316A 2048 x 8 ROM .................................................................... 4-12
PROMs
1702A/4702A 2K (256 x 8) UV Erasable PROM ..................................................... 4-5
*Partial data sheets are shown here. For complete specifications, contact Intel Literature Department, Intel Corporation, 3065 Bowers
Avenue, Santa Clara, California 95051.
7-2
inter
4040
SINGLE CHIP 4-BIT
P-CHANNEL MICROPROCESSOR
• 8K Byte Memory Addressing
Capability
• FunctionalJy and Electrically
Upward Compatible to 4004 CPU
• 14 Additional Instructions
(60 total) Including Logical
Operations and Read Program
Memory
• 24 Index Registers
• Subroutine Nesting to 7 Levels
• Standard Operating
Temperature Range of
OOto 70°C
• Interrupt Capability
• Single Step Operation
• Also Available With -40°
to +85° C Operating Range
The Intel® 4040 is a complete 4-bit parallel central processing unit (CPU). The CPU can directly address 4K eight bit instruction
words or 8K with a bank switch. Seven levels of subroutine nesting, including interrupt, and 24 randomly accessable index
registers (24x4) are provided as convenient facilities for the designer. The index registers may be used for addressing or for
scratch pad memory for storing computation results. The interrupt feature permits a normal program sequence to be
interrupted, with normal program execution continuing after the interrupt service routine is completed. Provisions have also
been made to permit single-stepping the CPU using the STOP and ACKNOWLEDGE signals.
The 4040 is an enhanced version of the 4004 and as such retains all the functional capability of that device. It will execute all the
4004 instructions, and is also electrically compatible with all components used with a 4004 CPU.
BLOCK DIAGRAM
0 0 .°3
BI·DIRECTIONAL
DATA BUS
1.1
DATABUS
BUFFER
(4 BIT)
INTERNAL DATA BUS
IACCUMUlAT~~~ I I
INSTRUCTION
REGISTER 18)
LOGIC
UNIT
(ALU)
j
t
·10V
CARRY
ROM
OUT
CONTROL
RAM
CONTROL
TEST
~
CYCLE
ENCODING
1 JJ 1~#:NT;;:11 st i~:
CM ROM
'I'"
t
TCt~
SYNC 01
INT ACK
7-3
2
3
LEVEL NO.2
4
5
6
7
LEVEL NO.3
02
RESET
r-
LEVEL NO.4
8
9
LEVEL NO.5
10
11
12
13
14
15
lEVE-.l NO.
AND
1
lEVEL NO.1
~
LEVEL NO.7
TIMING
0-1
z>-
t;
CONTROL
ST
~
~
Y
SINGLE
STEP
CONTROL
MPX
'"
0
(12)
MACHINE'
-
~
I
PROGRAM COUNTER
AND
=-
I
J
I
MUlS;I~~~XER
INSTRUCTION
DECODER
LD:gj~~l r--
+5V
IT
1_
J
ARITHMETIC
_
.-
j
I[
TEMP. REG"{411
~"'I
~~
(4 BITI
INTERNAL DATA BUS
t
FLlP-F~OPS
POWER
SUPPLIES
1j
ADDRESS
-
o 141
1
2
3
4
5
6
7
STACK
SCRATCH
PAD
inter
4004
SINGLE CHIP 4-BIT
P-CHANNEL MICROPROCESSOR
• CPU Directly Compatible
With MCS-40 ROMs and
RAMs
• 4-Bit Parallel CPU With 46
Instructions
• Instruction Set Includes
Conditional Branching,
Jump to Subroutine and
Indirect Fetching
• Easy Expansion - One CPU
can Directly Drive up to
32,768 Bits of ROM and up
to 5120 Bits of RAM
• Standard Operating
Temperature Range of
0° to 70°C
• Also Available With -40°
to +85° C Operating Range
• Binary and Decimal
Arithmetic Modes
• 10.8 Microsecond
Instruction Cycle
The Intel® 4004 is a complete 4-bit parallel central processing unit (CPU). The 4004 easily interfaces with keyboards,
switches, displays, A-D converters, printers and other peripheral equipment.
The CPU can directly address 4K 8-bit instruction words of program memory and 5120 bits of data storage RAM. Sixteen
index registers are provided for temporary data storage. Up to 16 4-bit input ports and 16 4-bit output ports may also be
directly addressed.
The 4004 is fabricated with P-channel silicon gate MOS technology.
DATABUS
BUFFER
(4 BIT)
INTERNAL DATA BUS
IACCUMUlAT~~ I I
TEMP. REG .. )
141
J,
DATA BUS
ft
li
1
I
INSTRUCTION
II
I
STACK
REGISTER (8)
l
I I
LEVEL NO.1
AND
MACHINE
CYCLE
ENCODING
-
14,1-
I t
I O:gJ~~L 1"'-
Y
I
I
ROM
CONTROL
RAM
CONTROL
I
,j j j j
CM ROM
~
TIMING
AND
CONTROL
TEST
1
TEST
REGISTER
lEVEL NO.3
MPX
0
141
1
141
2 (4)
3 (4)
4
(4)
5 (4)
6 (4)
7 (4 )
(12)
(12)
(12)
ADDRESS
8 (41
9 (4)
10 141
1114f
12(41
13(41
14(41
15(41
STACK
I
POWER { _ - 1 0 V
_
+5V
SU PPLIES
LEVEL NO.2
1I
I
(121
DECODER
~
I
PROGRAM COUNTER
INSTRUCTION
_~AR~T~G~~TIC
UNIT
IALUI
MULTIPLEXER
J
FLAG
FLIP-FLOPS
14 BITI
INTERNAL DATA BUS
sVIC TCl"
SYNC
CM RAM
0-3
7-4
¢1
¢2
l
RESET
f
SCRATCH
PAD
4003
10-BIT SHIFT REGISTER/OUTPUT EXPANDER
• Easy Expansion of I/O Output
Capability
• Enable Output Control
• Standard Operating Temperature
Range of 0° to 70° C
• 10 Bit Serial-In/Parallel Out
• Serial-Out Capability for
Additional I/O Expansion
• 16 Pin Dual-In-Line Package
The 4003 is a 10 bit serial-in, parallel-out, serial-out shift register with enable logic. The 4003 is used to expand the number of
ROM and RAM 1/0 ports to communicate with peripheral devices such as keyboards, printers, displays, readers,
teletypewriters, etc.
The 4003 is a single phase static shift register; however, the clock pulse (CP) maximum width is limited to 10 msec. Data-in and
CP can be simultaneous. To avoid race conditions, CP is internally delayed.
PIN CONFIGURATION
CLOCK}
PULSE INPUT CP
OAT A IN
PARALLELfO
OUTPUTS
!!
E ENABLE INPUT
SERIAL OUT
Voo
0,
09
Vss
Os
r
BLOCK DIAGRAM
°7
PARALLEL °
OUTPUTS 3
°6
°4
°s
PARALLEL
OUTPUTS
I
I
I
I
10 BIT PARALLEL
OUTPUT BUFFER
I
7-5
'
I
I
4265
PROGRAMMABLE GENERAL PURPOSE I/O DEVICE
• TTL Interface
• Up to Eight 4265s Per System
• Interface to Standard RAMs
• 28 Pin Dual-In-Line Package
• Interface to Standard RAMs
28 Pin Dual-In-Line Package
• Standard
Temperature
• Range of Operating
0 to 70 C
Available with -40 to
• Also
+85 C Operating Range
14 Operating Modes
• Multi-Mode
16 Lines of 1/0 Capability
• Bit
Set/Reset
• Multiplexable
Outputs
•
Eight
Bit
Transfer
• Interfaces to 8080 Mode
Peripherals
• Synchronous and Asynchronous
• Interface
• Strobed Buffer Inputs and Outputs
0
0
0
0
The 4265 is a general purpose 1/0 device designed to interface with the MCS-40'· microcomputer family. This device provides
four software programmable 4-bit 1/0 ports which can be configured to allow anyone of fourteen unique operating modes for
interfacing to data memory or a variety of user peripheral devices.
A single MCS-40 system can accomodate up to four 4265s (one per CM-RAM) without external logic or up to eight 4265s with
one external decoder.
The 4265 resides on the MCS-40 data bus and uses the same selection procedure as 4002 RAM device. A valid compare selects
the 4265 for MCS-40 1/0 commands. As in the case of the 4002 or any MCS-40 peripheral circuit, selecti:m occurs only when the
proper SRC code and the CM signal are present simultaneously.
The 4265 provides an extremely flexible, general purpose 1/0 system capable of handling 4- or 8-bit input or output data. One of
fourteen basic operating modes can be selected (software programmable) as described below.
Port Z is TTL compatible with any TTL device. Ports W, X, and Yare low-power TTL compatible.
PIN CONFIGURATION
V DD
Vss
Do
Wo
0,
W,
0,
W,
03
W3
RESET
Xo
eM·RAM
x,
SYNC
X,
':'1
X3
('2
Vo
Z3
V,
Z,
V,
Z,
V3
Zo
V ODl
7·6
inter
4269
PROGRAMMABLE KEYBOARD DiSpLAY DEVICE
Keyboard Features:
Display Features:
•
Programmable to Interface to Encoded
Keyboard (8-bit code), 64-Key Scanned
Keyboard (expandable to 128 keys) or
Sensor Matrix (64 sensors)
•
Programmable to Interface to
Individually Scanned Displays or
Burrough's Self-Scan* Drive (16, 18, or
20 Characters)
•
8 Character FIFO Character Buffer (or
RAM in Sensor Mode)
•
•
2 Key Rollover and Key Debounce
•
External Interrupt Line to Indicate
When a Character Has Been Entered in
Character Buffer
Two 16 x 4 Display Registers
Recirculated Synchronously with
Keyboard Scan Lines to Give Automatic
Display Refresh
•
Display Registers Loadable and
Readable Selectively or Sequentially
•
40 Pin Dual In-Line Package
•
Standard Operating Temperature
Range of 0 0 to 70 0 C
Also Available with -40 0 C to +85 0 C
Operating Range
•
The 4269 has two separate and distinct sections: the keyboard section and the display section. The keyboard section can
interface to a range of devices from a matrix of toggle or thumb switches such as found on an instrument panel up to a full
typewriter style keyboard. The display section can interface to a range of devices from an array of individual LED indicators up
to a gas discharge alphanumeric display.
The 4269 Programmable Keyboard Display (PKD) relieves the 4004 or 4040 CPU from continuously scanning aswitch array or
refreshing a display under software control. This greatly expands the CPU throughput. The 4269 can scan up to an 8 x 8
keyboard or sensor matrix (or a 2 x 8 x 8 keyboard with the use of the shift or control key input). The display portion can
continuously refreSh either a single 16 x 8 alphanumeric display; a single 8 x 8 alphanumeric display; a dual16 x 4 digit display; a
Single 32 x 4 digit display; a 16 x 6,18 x 6 or 20 x 6 alphanumeric gas discharge display such as the Burroughs Self-Scan'; or an
array of 128 indicators.
*Self-Scan
IS
a registered trademark of the Burroughs Corporation
PIN CONFIGURATION
7·7
inter
4201A
CLOCK GENERATOR
• Complete Clock Requirements for
MCS-40TM Systems
• Provides MCS-40 Reset Function
Signal
• Crystal Controlled Oscillator
(XT AL External)
• Standard Operating Temperature Range
of 0° to 70°C
• MOS and TTL Level Clock Outputs
• Also Available with -40° to +85° C
Operating Range
The 4201A is a CMOS integrated circuit designed to fill the clock requirements of the MCS-40 microcomputer family. The
4201A contains a crystal controlled oscillator (XTAL external), clock generation circuitry, and both MOS and TTL level
clock driver circuits.
The 4201A also performs the power on reset function required by MCS-40components and provides the logic necessary to
implement the single-step function of the 4040 central processor unit.
PIN CONFIGURATION
4201A
BLOCK DIAGRAM
me
~
=
B-:
1--------. '
1_------1'-;-1-r"""
91 DRIVER
92 DRIVER
MODE 0>--_ _ _ _ _ _ _ _ _
0-----.....1
N,O,O>-----S""T"'EP,..-I
N.C. 0
I
SINGLE
STEP F/F
I·
MaS
~
DRIVER
P
DRIVER
~
RESET IN
RESET OUT
~}
}m
gSTOP
ACK
111
Vss VOD GROUND
7-8
inter
4289
STANDARD MEMORY INTERFACE
• Direct Interface to all Standard
Memories
• 40 Pin Dual In-Line Package
• Standard Operating
Temperature Range of
0° to 70°C
• Also Available With
-40° to +85° C Operating
Range
• Allows Read and Write Program
Memory
• Single Package Equivalent of
4008/4009
• TTL Compatible Address, Chip
Select, Program Memory Data
Lines
The 4289 standard memory interface and I/O interface enables the CPU devices to utilize standard memory components as
program data memory. Notably, PROMs (4702A), RAMs (2102) and ROMs can be arranged in a memory array to facilitate
system development. Programs generated using the 4289 interface can be committed to MCS-40'· ROMs (4308 and 4001) with
no change to software.
The 4289 also contains a 4 bit bi-directional I/O port and necessary steering logic to multiplex a host of I/O sources to the CPU.
The Read and Write Program Memory instruction allows the user to store data and modify program memory. The device directly
addresses 4K of program memory. The address is obtained sequentially during A 1-A3 states of an instruction cycle. The eight
bit instruction is presented to the CPU during M1 and M2 states of the instruction cycle via the four bit data bus.
The 4289 stores the SRC instruction operand as an I/O address and responds to the ROM I/O instructions (WRR and RDR) by
reading or writing data to and from the processor and 4289 I/O bus.
7-9
4002
320-BIT RAM AND 4-BIT OUTPUT PORT
• 16 Pin Dual In-Line Package
• Four Registers of 20 4 Bit
Characters
• Direct Interface to MCS-40TM
4 Bit Bus
• Output Port Low-Power TTL
Compatible
• Standard Operating
Temperature Range of
0° to 70°C
• Also Available With -40°
to +85° C Operating Range
The 4002 performs two distinct functions. As a RAM it stores 320 bits arranged in 4 registers of twenty 4 bit characters each (16
main memory characters and 4 status characters). As a vehicle of communication with peripheral devices. it is provided with 4
output lines and associated control logic to perform output operations. The 4002 is a PMOS device and is compatible with all
MCS-40'· components.
The 4002 is available in two options. the 4002-1 and 4002-2. Along with an external pin connected to either VD D or Vss. a two bit
chip selection address is provided allowing a maximum of 1280 bits of 4002 RAM on a single MCS-40 CM-RAM line. Thus. the
four CM-RAM lines give a maximum of 5120 bits of 4002 RAM in an MCS-40 system.
PIN CONFIGURATION
BLOCK DIAGRAM
:: :>-------IO:~II~-~T:,M~,N:G:--....,I. . .>---------------Ir:=
___-:-"1
ROM TIMING
> - - - - - - - -.....IL,......,.."T"""r...:-rJ
:1
tP 20
DATA
r
BUS
I/O
")
02
lID, INPUTI
OUTPUT
1/02 LINES
OJ
IIO J
"s.
Voo
{ MEMORY
D,
ClOCK}_
PHASE 1 1
ClOCK}~
PHASE Z
I~~~~ } SYNC
-f-:::-l
~nnn
,
I-
: SYNC
-•
OVeo
oeM
RST
00 ()--oOI..........
eM CONTROL
INPUT
o Vss
O,O--O.....-.,~
0 2 0--0""'-"-'
{CLEAR INPUT
CL fDA I/O LINES
o,O--O""'-"-1_..,.........J
RESET
MEMORY
DATA
MUX
CLEAR
ADDRESS
I/O
INTERFACE
REGISTER
AND
DECODER
7-11
1-----"..1
ROM
256 X 8
inter
MCS®
4001
ROM
CUSTOM ROM
ORDER FORM
CUSTOMER
P.O. NUMBER
DATE
For Intel use only
s#
PPPP
STD
ZZ
DD
APP
DATE
All custom 4001 ROM orders must be submitted on this form. Programming information should be sent in the form of computer
punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel.
MARKING
INTEL PATTERN NUMBER
The marking as shown at the right must contain the I ntel logo, the
product type (P4001), the 4·digit Intel pattern number (PPPP), a date
code (XXXX), and the 2·digit chip number (00). An optional customer
identification number may be substituted for the chip number (ZZ).
Optional Customer Number (maximum 6 characters or spaces).
•
I
CUSTOMER NUMBER _ _ _ _ _ _ _ _ _ _ _ _ _ __
P4001
PPPP
xxxx
zz
CHIP NUMBER OR
CUSTOMER NUMBER
MASK OPTION SPECIFICATIONS
A. CHIP NUMBER _ _ _ _ __
(Must be specified-any number from
through 15-00).
o
B. I/O OPTION - Specify the connec·
tion numbers for each I/O pin (next
page). Examples of some of the pas·
sible I/O options are shown below:
EXAMPLES - DESIRED OPTION/CON·
NECTIONS REQUIRED
1. Non-inverting output -
1 and 3 are
connected.
2. Inverting output -
1 and 4 are con-
nected.
3. Non-inverting input (no Input resistor) - only 5 is connected.
6.
If inputs and outputs are mixed on
the same port, the pins used as the
outputs must have the internal resistor connected to either VDO or
VSS 18 and 9 or 8 and 10 must be
connected). This is necessary for testing purposes. For example, if there
are two inverting inputs (With no in~
put resistor) and two non-Inverting
outputs, the connection would be
made as follows:
Inputs - 2 and 6 are connected
Outputs - 1, 3, 8, and 9 are connected or
1, 3, 8, and 10 are connected
If the pins on a port are all inputs or
all outputs, the inte·rnal resistors do
not have to be connected.
4. Inverting input (input resistor to VSS)
5.
2, 6, 7, and 9 are connected.
Non-inverting Input (Input resistor to
VDD) nected.
2, 7, 8, and 10 are can·
C. 4001 CUSTOM ROM PATTERN Programming information should be
sent in the form of computer punched
7-12
cards or punched paper tape. In either
case, a printout of the truth table
must accompany the order. In the
BPNF format, the characters should
be written as a "P" for a high level
output ~ VSS (negative logic "0") or
an "N" for a low level output ~ V DD
(negative logic "1").
Hex input tapes for the 4001 and
4308 may also be generated by
Intellec®
Development
Systems.
These tapes are assumed to be negative
logic. This means that a NOP instruction operation code (00000000), for
example, would be coded as 00 in the
HEX format. This would automatically result in the VIH levels on the
MCS4/40 data bus. When the BPNF
format is used, all logic representations must be inverted. Thus, a NOP
would be represented as BPPPPPPPPF.
inter
4308
1024 x 8 MASK PROGRAMMABLE ROM
AND FOUR 4-BIT 1/0 PORTS
• Direct Interface to MCS-40TM
4-Bit Data Bus
• I/O Ports Low-Power TTL
Compatible
• 28 Pin Dual In-Line Package
• Equivalent to Four 4001 ROMs
• Four Independent 4-Bit I/O
Ports
• Standard Operating
Temperature Range of
OOto 70°C
• Input I/O Buffer Storage with
an Optional Strobe
• Also Available With -40°
to +85° C Operating Range
The 4308 is a 1024 x 8 bit word ROM memory with four 1/0 ports. It is designed for the MCS-40" system and is operationally
compatible with all existing MCS-40 elements. The 4308 is functionally identical to four 4001 chips. The 4308 has 161/0 lines
arranged in four groups of four lines.
BLOCK DIAGRAM
SYNC
eM ROM
0
0
11
TIMING
"l
d
12
0 ____
6
00
0..........'....
0,
RESET
8
00 _9_
13
CLRILD 0 - -
--
DATA BUS
CONTROL
IN OUT
BUFFER
LOGIC
<>
I[
22
~ ~ ~ ~ ~
•
[
•....
~
t
DECODER
110 03
...,-0
~
~
4 BITS
t '''./
HH
1/01 3
PIN CONFIGURATION
7-13
AND MUX
10248
Ii
[
=r:JC
LJl
ROM ARRAY
I---------v:'
·0
tt,,)"
1/010
0
28
_---.J [
[
1
1+1+
~
23
ADDRESS
REGISTER
AND
I'OPORT
1/000
..
~}
[
t
I/O PORT
2
I" ,,1+
If02a
1/023
~tl
I/O PORT
3
H+I"
1/030
1/033
0,
0,
MCSa!>
CUSTOM ROM
ORDER FORM
Intet
4308
ROM
CUSTOMER
P.O. NUMBER
DATE
For Inlel use only
S#
PPPP
STD
ZZ
DD
APP
DATE
All custom 4308 ROM orders must be submitted on this form. Programming information should be sent in the form of computer
punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel.
MARKING
INTEL PATTERN NUMBER
•
The marking as shown at the right must contain the Intel logo,
the product type (P4308), the 4-digit Intel pattern number
(PPPP), a date code (XXXX), and the 2-digit chip number
(DO). An optional customer identification number may be
substituted for the chip number (ZZ). Optional Customer
Number (maximum 6 characters or spaces).
P4308
I
xxxx
zz
CHIP NUMBER OR
CUSTOMER NUMBER
DATE CODE
CUSTOMER NUMBER
MASK OPTION SPECIFICATION
A. CHIP NUMBER _ _ _ _ _ _ _ (Must be specified).
Hex input tapes for the 4001 and 4308 may also be generated by I ntellec® Development Systems. These tapes
are assumed to be negative logic. This means that a NOP
instruction operation code (00000000), for example, would
be coded as 00 in the HEX format. This would automatically result in the VIH levels on the MCS4/40 data bus.
When the BPNF format is used, all logic representations
must be inverted. Thus, a NOP would be represented as
BPPPPPPPPF.
B. I/O OPTION - Specify the connection numbers for each
I/O pin. See table below.
C. 4308 CUSTOM ROM PATTERN - Programming information should be sent in the form of computer punched cards
or punched paper tape. In either case, a printout of the truth
table must accompany the order. In the BPNF format, the
characters should be written as a "P" for a high level output
= Vss (negative logic "0") or an "N" for a low level output
= VDD (negative logic "1").
PIN
OPTION
11000
27
1100,
26
1
2
2
11002
25
24
5
4
1
1
1
1
2
2
2
2
3
2
17
16
15
1
1
1
1
1
2
2
2
14
21
1
1
2
2
20
19
1
1
2
2
18
1
2
11003
1/0 10
1101,
1101 2
1/01 3
1/020
1/02,
1/022
11023
1/030
1/03,
11032
1/033
1
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
6
5
5
6
6
6
6
6
6
5
5
5
5
4
4
4
4
4
5
5
5
4
4
5
3
4
5
4
4
5
5 6
5
c:J--~--G
.,
ROM
MUX
PATTERN
5
6
6
6
6
6
6
6
6
7
8
9
10
11
7
8
8
8
8
8
8
9
9
9
9
9
10
10
10
10
10
10
11
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
9
9
9
9
9
8
8
9
9
8
9
9
8
8
9
10
10
10
10
10
10
10
11
11
11
11
11
11
11
"-
a
CLR
LD
I"
11
11
5
~
I eLK
2
INPUT
11
11
j
F F
-
71
"6
11
10
11
10
11
ON
~~~t
~-c>-c'
L f
RESET
LOGIC
0---
BUS
OUTPUT
liD PORT LINE OPTION
NOTE: Options 10 and 11 cannot both be specified.
7-14
slC>----OVoO
Y
X v"
MCS-48™
Microcomputers
8
MCS-48™ MICROCOMPUTERS
TABLE OF CONTENTS
Single Component 8·Bit Microcomputers
8021 Single Component 8-Bit Microcomputer. ...................................................... 8-4
8022 Single Component 8-Bit Microcomputer with AID . ........................................... _ .. 8-10
8048/8648/8748/8035 Single Component 8-Bit Microcomputer .......................................... 8-22
8049/8039/8039-6 Single Component 8-Bit Microcomputer ............................................. 8-31
Input/Output
8243 MCS-48™ InputlOutput Expander ............................................................ 8-36
INTRODUCTION
Recent advances in NMOS technology have allowed Intel for the first time to place enough capability on a single
silicon die to create a true Single chip microcomputer containing all the functions required in a digital processing
system. This microcomputer, its variations, and its optional peripherals are collectively called the MCS-48 microcomputer family and are fully described in this manual.
The head of the family is the 8048 microcomputer which contains the following functions in a single 40-pin package:
8-Bit CPU
1 K x 8 ROM program memory
64 x 8 RAM data memory
27110 lines
8-bit timerlevent counter
A 2.5 or 5.0 microsecond cycle time and a repertOire of over 90 instructions each consisting of either one or two cycles
makes the single chip 8048 the equal in performance of most presently available multi-chip NMOS microprocessors,
yet the 8048 is a true "low-cost" microcomputer. A single 5V supply requirement for all MCS-48 components assures
that "low cost" also applies to the power supply in your system.
Even with low component costs, however, a project may be jeopardized by high development and rework costs
resulting from an inflexible production design. Intel has solved this problem by creating two pin-compatible versions
of the 8048 microcomputer: the 8048 with mask programmable ROM program memory for low cost production and the
8748 with user programmable and erasable EPROM program memory for prototype development. The 8478 is essentiallya single chip microcomputer "breadboard" which can be modified over and over again during development and
pre-production, then simply replaced by the low cost 8048 ROM for volume production. The 8748 provides a very easy
transition from development to production and also provides an easy vehicle for temporary field updates while new
ROMs are being made.
8-2
To allow the MCSA8 to solve a wide range of problems and to provide for future expansion, all 8048 functions have
been made externally expandable using either special expanders or standard memories and peripherals. An efficient
low cost means of I/O expansion is provided by the 8243 Input/Output Expander which provides 16 I/O lines in a 24·pin
package. For systems with large I/O requirements, multiple 8243s can be used.
For such applications as keyboards, displays, serial communication lines, etc., standard MCS·80™ (8080) and
MCS·85™ (8085) peripheral circuits may be added. Program and data memory may be expanded using standard
memories or the 8355 and 8155 memories that also include programmable I/O lines and timing functions.
The 8035 is an 8048 without internal program memory that allows the user to match his program memory requirements
exactly by using a wide variety of external memories. The 8035 allows the user to select a minimum cost system no
matter what his program memory requirements.
The 8048 was designed to be an efficient control processor as well as an arithmetic processor with an instruction set
which allows the user to directly set and reset individual lines within its I/O ports as well as test individual bits within
the accumulator. A large variety of branch and table look·up instructions make the 8048 very efficient in implementing
standard logic functions. Special attention was also given to code efficiency with over 70% of the instructions being
single byte and all others being only two bytes. This means many functions requiring 1.5K to 2.0K bytes in other
processors may very well be compressed into the 1K words resident in the 8048.
8 BIT cPU
1 K WORDS OF PROGRAM MEMORY
64 WORDS OF DATA MEMORY
OSCILLATOR AND CLOCK DRIVER
RESET CIRCUIT
INTERRUPT CIRCUIT
Figure 1. On Chip Features
SPECIAL FEATURES
• Single SV Supply
• 8·Level Stack
• 40·Pin DIP
• Pin Compatible ROM and EPROM
• 2 Working Register Banks
• RC, XT AL, or External Frequency
Source
• 2.5 and 5.0 I1sec Cycle Versions
• All Instructions 1 or 2 Cycles
• Clock per Cycle and Optional Clock
per State Output
• Single Step
8·3
8021
SINGLE COMPONENT 8-BIT MICROCOMPUTER
• 8·Bit CPU, ROM, RAM, I/O in Single
28·Pin Package
• 1K x 8 ROM
64 x 8 RAM
21 I/O Lines
• Single SV Supply ( + 4.SV to 6.SV)
• Interval Timer/Event Counter
• 8.38 j.lsec Cycle With 3.S8 MHz XTAL;
All Instructions 1 or 2 Cycles
• Clock Generated With Single Resistor
or Inductor
• Instructions -8748 Subset
• Zero-Cross Detection Capability
• High Current Drive Capability-2 Pins
• Easily Expandable I/O
The Intel® 8021 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's N-channel
silicon gate MOS process. The features of the 8021 include a subset of the 8048 optimized for low cost, high volume applications, plus additional I/O flexibility and power.
The 8021 contains a 1 K X 8 program memory, a 64 X 8 data memory, 21 I/O lines, and an 8-bit timer/event counter, in addition to on-board oscillator and clock circuits. For systems that require extra I/O capabi lity, the 8021 can be expanded using
the 8243 or discrete logic.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8021 has bit handling
capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results from an instruction set consisting mostly of single byte instructions and no instructions over two bytes in length.
To minimize development problems and maximize flexibility, an 8021 system can be easily designed using the 8021 emulation board, EMB-21. The EMB-21 contains a 40-pin socket which can accommodate either the 8748 shipped with the board
or an ICE-48 plug. Also, the necessary discrete logic to reproduce the 8021 's additional I/O features is included.
PIN CONFIGURATION
P22
P23
PROG
POO
POl
P02
POl
P04
P05
P06
P07
ALE
T1
Vss
Vee
XTAL{
P20
P17
"3
"2
P11
"0
RESET
XTAL 2
XTAL 1
PORT
#fJ
PORT
#1
Pl.
""
",
BLOCK DIAGRAM
LOGIC SYMBOL
RESET
PORT
#2
TEST
ADDRESS
LATCH
ENABLE
PORT
EXPANDER
STROBE
8-4
8021
ABSOLUTE MAXIMUM RATINGS*
'.'
,
".
"
'COMMENT: Stresses above those listed under ;, Ab;.dfU.te M~~j~:y"'::;i .
mum Ratings" may cause permanent damage to the device.1J'ls."i~"_a'\'.:~:I;,',0%\\:'",\,}
stress rating only and functional operation of the device at th~~ '01( . " "' "
Ambient Temperature Under Bias......... O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . .• 1 W
any other conditions above those indicated in the operational sec~, i}
tions of this specification is not implied. Exposure to absolut~'
maximum rating conditions for extended periods may affect device
reliability.
D.C. AND OPERATING CHARACTERISTICS
T A = O°C to 70°C, Vee = 5.5V ±1V, Vss = OV
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
VfL
Input Low Voltage (All except XTAL 1, XTAL2)
-0.5
0.8
V
VfH
Input High Voltage (All except XTAL 1, XTAL2)
2.0
Vee
V
Vee = 5.0V ±10%
VfH,
Input High Voltage (All except XTAL 1, XTAL2)
3.0
Vee
V
Vee = 5.5V ±1V
VOL
Output Low Voltage
0.45
V
IOL = 1.6 mA
V
IOL = 7 mA
V
IOH - 50 JlA
VOL,
Output Low Voltage (P10, P11)
VOH
Output High Voltage (All unless Open Drain)
IOL
Output Leakage Current (Open Drain Option Port 0)
±10
JlA
lee
Vee Supply Current
100
mA
2.5
2.4
Vss + 0.45 ~ V fN ~ Vee
A.C. CHARACTERISTICS
T A = o°c to 70°C, Vee = 5.5V ±1V, Vss = OV
Symbol
Parameter
Min.
Max.
Unit
tey
Cycle Time
8.38
50.0
Jlsec
~F
Oscillator Frequency Variation -Resistor Mode
-20
+20
%
A.C. TEST CONDITIONS
Control Outputs: CL = 80 pF
8-5
Test Conditions
3 MHz XTAL = 10 Jlsec tey
F = 2.5 MHz
8021
PIN DESCRIPTION
DesijJnation
Pin #
Function
Designation
Vss
14
Circuit GND potential
Vcc
28
+5V power supply
PROG
POO-P07
Port 0
4-11
8-bit quasi-bidirectional port
P10-P17
Port 1
18-25
8-bit quasi-bidirectional port
P20-P23
Port 2
26-27
1-2
4-bit quasi-bidirectional port
P20-P23 also serve as a 4-bit I/O
expander bus for 8243
T1
I nput pin testable using the JT1
and JNT1 instructions_ Can be
designated the timer/event counter input using the STRT CNT
instruction. Also allows zero-
13
Function
crossover sensing of slowly' mov-' - . ,,:
ing AC inputs.
RESET
17
Input used to initialize the processor by clearing status flip-flops
and setting program counters to
zero.
ALE
12
Address Latch Enable. Signal occuring once every 30 input clocks,
used as an output clock.
XTAL1
15
One side of crystal, inductor, or
resistor input for internal oscillator. Also input for external source.
(Not TTL compatible.)
XTAL2
16
Other side
element.
Output strobe for 8243 I/O Expander
3
Pin#
of timing
control
INSTRUCTION SET*
Mnemonic
Description
ADD
ADD
ADD
ADDC
ADDC
ADDC
ANL
ANL
ANL
ORL
ORL
ORL
XRL
XRL
XRL
INC
DEC
CLR
CPL
DA
SWAP
RL
RLC
RR
RRC
A,R
A,@R
A,#data
A,R
A,@R
A,#data
A,R
A,@R
A,#data
A,R
A,@R
A,#data
A,R
A,@R
A,#data
A
A
A
A
A
A
A
A
A
A
Add
Add
Add
Add
Add
Add
IN
OUTL
MOVD
MOVD
ANLD
ORLD
A,P
P,A
A,P
P,A
P,A
P,A
Input port to A
Output A to port
I npu t Expander port to A
Output A to Expander port
And A to Expander port
Or A to Expander port
..
INC
INC
R
@R
Increment register
Increment data memory
..:
u
c
JMP
JMPP
DJNZ
addr
@A
R,addr
Jump unconditional
Jump indirect
Decrement register and Jump
on R not zero
S
..
:;
E
~
Swap nibbles of A
Rotate A left
Bytes
JC
JNC
JZ
JNZ
JT1
JNTl
JTF
..:
u
c
=
Clear A
Complement A
Decimal Adjust A
Description
Mnemonic
.!c
~
0
~e
i=
NOP
addr
addr
addr
addr
a
Jump on T1 = 0
Jump on timer flag
Jump to subroutine
Return
No Operation
a:
e
III
2
1
2
2
2
2
'See July, 1978 MCS-48 User's Manual for opcodes.
8-6
8021
FUNCTIONAL SPECIFICATIONS
The following is a functional description of the major elements of the 8021.
Loe 24-63
Program Memory
INDIRECTLY
ADDRESSABLE
The 8021 contains 1 K X 8 of mask programmable ROM.
No external ROM expansion capability is provided.
BY
IRARO OR 1
Loe 8-23
I
CAN BE USED FDA
ADDRESS STACK
7
6
Data Memory
5
4
3
2
IRAR 1
IRAR 0
A 64 X 8 dynamic RAM is located on chip for data storage.
All locations are indirectly addressable and eight designated
locations are directly addressable. Also, included in the
memory is the address stack, addressed by a 3-bit stack
pointer.
DIRECTLY
1
ADDRESSABLE
Figure 1. Internal RAM Organization
Memory is organized as shown in Figure 1. The least significant 8 addresses, 0-7, are directly addressable by any of
the 11 direct register instructions. The locations are readily
accessible for a variety of operations with the least number
of instruction bytes required for their manipulation.
Oscillator and Clock
The 8021 contains its own onboard oscillator and clock
circuit, requiring only an external timing control element.
This control element can be a crystal, inductor, resistor, or
clock in. The capacitor normally required in resistor or
inductor timing control operation is integrated onto the
8021. All internal time slots are derived from the external
element, and all outputs are a function of the oscillator
frequency. Pins Xl and X2 are used to input the particular
control element. An instruction cycle consists of 10 states,
and each state is a time slot of 3 oscillator periods. Therefore, to obtain a 10 Ilsec instruction cycle, a 3 MHz crystal
should be used.
Registers 0 and 1 have yet another function, in that they
can be used to indirectly address all locations in memory,
using the indirect register instructions. These indirect RAM
address registers, I RAR's, are especially useful for repetitive-type operations on adjacent memory locations. The
indirect register instruction specifies which IRAR to use,
and the contents of the IRAR is used to address a location
in RAM. The contents of the addressed location is used
during the execution of the instruction, and may be modified. A value larger than 63 should not be preset in the
IRAR when selected by an indirect register instruction.
I RAR's may point to addresses 0-7, if desired.
.
Timer/Event Counter
An interval timer is available to enable the user to keep
track of time elapsed or number of events occurred, during
normal program execution and flow.
Locations 8-23 may be used as the address stack. The
address stack enables the processor to keep track of the
return addresses generated from CALL instructions. A 3-bit
stack pointer (SP) supplies the address of the locations to
be loaded with the next return address generated. The SP to
this pushdown stack is incremented by one after a return
address is stored, and decremented by one before an
address is fetched during a RET. A total of 8 levels of
nesting is possible. The SP is initialized to location 8 upon
RESET. Since each address is 10 bits long, two bytes must
be used to store a single address. The SP is incremented
and decremented by one, but each increment or decrement
moves the address pointed to by two. Therefore, only even
numbered addresses are pointed to.
By a MOV T,A instruction, the contents of the accumulator
are loaded to the timer. At the STRT T command an internal prescaler is zeroed and thereafter increments once each
30 input clocks (once each single cycle instruction, twice
each double cycle instruction). The prescaler is a divide by
32. At the (11111) to (00000) transition the timer is incremented. The timer is 8 bits and an overflow (FFH) to
(OOH) timer flag is set. A conditional branch is available for
testing this flag, the flag being reset each test. Total count
capacity for the timer is 2 8 X 2 5 = 8192 or 81.9 msec at a
10 Ilsec cycle time. Contents of the timer are moved to the
accumulator by the MOV A,T instruction without disturbing the counting process.
If a particular application does not require 8 levels of nesting, the unused portion of the stack may be used as any
other indirectly addressable scratchpad location. For
example, if only 3 levels of subroutine nesting are used,
then only locations 8-15 need be reserved for the address
stack, and locations 16-63 can be used for data storage.
The actual program counter address is not stored in the
address stack. A separate register retains its value.
The timer may also be used as an event counter. After a
STRT CNT command, the chip will respond to a high to
low transition on the Test 1 pin by incrementing the timer.
Transitions can occur no faster than one each three instruction cycles.
The timer and event functions are exclusive. Counting or
timing may be started or stopped (STOP TCNT) at will.
8-7
8021
Input/Output Capabilities
The 8021 I/O configurations are highlY flexible. A number
of different configurations are possible, tailoring an 8021 to
a given task. Other than the power supply and dedicated
pins, all other pins (20) can be used for input, output, or
both, depending on the configuration.
INTERNAL
BUS
WRI~~!~ -l--l----l~r---'
INPUT BUFFER
P20-P23 and Pl0-P17 are quasi-bidirectional, and Test 1
is directly testable through program control. A simplified
schematic of the quasi-bidirectional interface is shown in
Figure 2. This configuration allows buffered outputs, and
also allows external input. When writing a "0" or low value
to these ports, the large pulldown device sinks an external
TTL load. When writing a "1", a large current is supplied
through the large pullup device to allow a fast data transfer.
After a short time (less than one instruction cycle), the
large device is shut off and the small pullup maintains the
"1" level indefinitely. However, in this situtation, an input
device capable of overriding the small amount of sustaining
current supplied by the pullup device can be read. (Alternatively, the data written can be read). So, by writing a "1"
to any particular pin, that pin can serve either as a true
high-level latched output pin, or as just a pullup resistor on
an input. This allows maximum user flexibility in selecting
his input or latched output pins, with a minimum of
external components.
Figure 2. Quasi-Bidirectional Port Structure
Port 00-07 is also quasi-bidirectional, except there is no
large pullup device. As outputs, this port is essentially
open drain.
Figure 3. I/O Expander Interface
By mask option the small pullup devices on POO-P07 may
be deleted on any pin providing a true open drain output.
This is useful in driving analog circuits and certain loads,
such as keyboards.
fa) ZERO CROSS DETECT
Also available is the 8243 I/O expander chip, which provides additional I/O capability with a limited number of
overhead pins. This chip has 4 directly addressable 4-bit
ports. It connects to the PROG pin, which provides a clock,
and pins P20-P23, which provide address and data. These
ports can be written with a MOVO P,A; ANlO P,A; and
ORlO P,A for Ports 4-7. A high to low transitiori on
PROG signifies that address and control are available on
P20-P23. The previous data on P20-P23 before an output
expander instruction is lost. Therefore, when using an
output expander P20-P23 are not useful for general
input/output. Reading is via the MOVO A,P. This circuit
configuration is shown in Figure 3.
fb) OPTIONAL PULLUP RESISTOR
The Test 1 pin has a special bias input that allows zerocrossover sensing of slowly moving inputs. This is especially
useful in SCR control of 60 Hz power and in developing
time of day routines. As a ROM mask option there is a
pullup resistor that is useful for switch contact input or
standard TTL. See Figure 4.
Figure 4. Test 1 Pin
8-8
8021
CPU
1. Pin Out - As the 8021 is a. 28·Pinbll?:<,/AOQJe form
The 8021 CPU has arithmetic and logical capability. A wide
variety of arithmetic and logic instructions may be exer·
cised, which affect the contents of the accumulator, and/or
direct or indirect scratchpad locations. Provisions have been
made for simplified BCD arithmetic capability through the
use of the DAA, SWAP A, and XCHD instructions. In
addition, MOVP A,@A allows table lookup for display
formating and constants. Jump conditions such as zero,
not zero refer to the accumulator contents at the time of
the condition.
2. Instruction Time - The 8021 instruction cycle is 30
of adapter must be used to Interfacem~ . &021
socket to ICE-48. An emulation board, EM:(.hiIA
been designed to perform this functiorL The E1'JVfi;',;;.:;::,:.
also accounts for the increased flexibility'bfsdme' '
8021 I/O lines.
clock cycles long, the 8748 instruction cycle is 15
clocks long. Where exact timing is important the
8748 breadboard part should be operated at half the
8021 cI ock rate.
3, Test 1 - To facilitate developing time of day rou·
tines from 60 Hz, and for SCR control, the Test 1
pin without the pullup resistor option will detect
zero crossing of a capacitively coupled AC input.
Reset
The 8021 may see poorly regulated and noisy power sup·
plies. A useful feature is to sense when the power supply
dips and do a reset to prevent continued operation with
incorrect data. This feature may be implemented on the
8021 by connecting a diode between the RESET node and
ground. See Figure 5.
4. Quasi·Bidirectional Ports - All 8021 ports are quasi·
bidirectional to facilitate stand·alone use. Port 0 has
open drain outputs and by mask option it mayor
may not have pullup resistors.
5. Oscillator - The 8021 has on-chip oscillator that is
optimized for the single resistor mode, External
connection will differ from the 8748.
A reset will then be forced if the supply drops approxi·
mately 1.5 volts and rapidly recovers. One instruction
cycle will reset the 8021 to the initialized state.
6. Dynamic RAM and Logic -
The 8021 utilizes
dynamic RAM and some dynamic logic. Input
clocking must be maintained above the minimum
rate or improper operation may result,
By removing the diode and using only the capacitor, voltage
drops in Vee will not cause a RESET.
7. f/igh Current Outputs - Very high current drive is
desirable for minimizing external parts required to
do high power control. P10 and P11 have been
designated high drive outputs capable of sinking
7 rnA at Vss +2.5 yolts. (For clarity, this is 7 'rnA to
Vss with a 2.5 volt drop across the buffer.) These
pins may, of course, be paralleled for 14 rnA drive if
the output logic states are always the same.
10 V
8. Reset - Reset has been modified on the 8021, as
+----..., RESET
previously noted, A reset will be forced if the power
supply drops approximately 1.5 volts and rapidly
recovers, if a diode is used in the reset circuit. This
prevents continued operation with incorrect data
caused by a poorly regulated and/or noisy power
supply.
9. Instruction Set - The following instructions, which
are found in the 8748, have been deleted from the
8021 instruction set.
FIGURE 5. POWER ON RESET
Data Moves
Registers
Branch
JTO
A,PSW DEC R
PSW,A ~ JNTO
A,@R
Flags
JFO
MQVX @R,A
JFl
MQVP3 A,@A
JNI
CPL FO
JBb
CLR F1
MOV
MOV
MOVX
Differences Between the 8021 and the 8748
~
CPL F1
Although the 8021 is basically an electrical and functional
subset of the 8748, there are some differences:
Timer
addr
EN TeNTI
DIS TeNTI
addr
addr
Subroutine
addr
addr
addr
RETR
Control
EN
DIS
SEL
SEL
SEL
SEL
ENTO
I
I
RBO
RBl
MBO
MB1
elK
Input/Output
ANL
ORL
INS
P,#data
P,#data
A,BUS *
OUTL BUS,A
ANL
ORL
*
BUS.#data
BUS,#data
*Thest! Instructions have been replaced in the 8021 by
IN A,PO and OUTL PO,A respectivelv.
INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara, CA 95051 • (408) 246-7501
Printed in U,S,A,1T38/1078IBUBA
8-9
tnt~'''''''''';:;:;1'(,,'
.-r
8022
'/",y'i-/i' ,: "
SINGLE COMPONENT 8·BIT MICROCOMPUT'~_;2:~':,
WITH ON·CHIP AID CONVERTER
," ,/,~'~z~,~~~~,
,~'
• 8.38 I-tsec Cycle; All Instructions 1
or 2 Cycles
• On·Chip 8·Bit A/D Converter; Two Input
Channels
• Instructions -
• 8 Comparator Inputs (Port 0)
II
• Single 5V Supply (4.5V to 6.5V)
• Two Interrupts -
8048 Subset
• Interval Timer/Event Counter
Zero,Cross Detection Capability
• High Current Drive Capability -
"
• Clock Generated with Single Resistor,
Inductor, or Crystal
2 Pins
External and Timer
• Easily Expandable I/O
The Intel@ 8022 is the newest member of the MCS-48™ family of single chip 8-bit microcomputers. It is designed to
satisfy the requirements of low cost, high volume applications which involve analog signals, capacitive touch panel
keyboards, and/or large ROM space. The 8022 addresses these applications by Integrating many new functions onchip, such as AID conversion, comparator inputs and zero-cross detection.
The features of the 8022 include 2K bytes of program memory (ROM), 64 bytes of data memory (RAM), 28 I/O lines, an
on-Chip 8-bit AID converter with two input channels, an 8-bit port with comparator inputs for interfacing to low voltage
capacitive touchpanels or other non-TTL interfaces, external and til)1er interrupts, and zero-cross detection capability.
In addition, it contains the 8-bit interval timer/event counter, on-board oscillator and clock circuitry, single 5V power
supply reqUirement, and easily expandable I/O structure common to all members of the MCS-48 family.
The 8022 is designed to be an efficient controller as well as an arithmetic processor. It has bit handling capability plus
facilities for both binary and BCD arithmetic. Efficient use of program memory results from using the MCS-48 instruction set which consists mostly of single byte instructions and has extensive conditional jump and direct table lookup
capability. Program memory usage is further reduced via the 8022's hardware implementation of the A/D converter
which simplifies interfacing to analog signals.
PIN CONFIGURATION
LOGIC SYMBOL
Vee
Vee
AVec
VAREF
AN'
P2'
P2.
PROG
XTAL
BLOCK DIAGRAM
Vss
r
RESET _
P23
P2'
P20
P17
POO
P'6
P15
PORT 2
P'.
P03
P13
P04
P12
P11
RESET
ALE
T1
ANO
ADDRESS
LATCH
ENABLE
AN'
PORT
XTAl2
XTAL 1
SUBST
EXPANDER
STROBE
I I
AID
AID SUBSTRATE
Vee
Vss
i'
• 2K)( 8 ROM, 64)( 8 RAM, 28 I/O Lines ',~ ~,¥,.
• 8·Bit CPU, ROM, RAM, 110 in Single
40·Pin Package
8-10
,!,j,'
8022
Designation
PIN DESCRIPTION
Designation
Pin #
Function
Vss
20
Vcc
PROG
40
+ 5V circuit power supply.
37
Output strobe for Intel® 8243 110
expander.
10-17
8·bit open·drain port with com·
parator inputs. The switching
threshold is set externally byV TH .
Optional pull·up resistors may be
added via ROM mask selection.
POO-P07
Port 0
VTH
9
Port 0 threshold reference pin.
25-32
8·bit quasi·bidirectional port.
P20-P27
Port 2
33-36
38-39
1-2
8·bit quasi·bidirectional port.
P20-23 also serve as a 4·bit 110
expander for Intel® 8243.
8
Interrupt input and input pin test·
able using the conditional transfer instructions JTO and J NTO. Initiates an interrupt following a
low level input if interrupt is enabled. Interrupt is disabled after
a reset.
T1
19
Input pin testable using the JT1
and JNT1 conditional transfer instructions. Can be designated
the timer/event counter input
using the STRT CNT instruction.
Also serves as the zero-cross
detection input to allow zerocrossover sensing of slowly moving AC inputs. Optional pull-up
resistor may be added via ROM
mask selection.
8-11
Function
Input used tOjnltialit~th~ wocessor by clearing staf\.ls lIrp~tl6'p~\.
and setting the prograr('lcountet
to zero.
24
AVss
7
AID converter G N D Potential.
Also establishes the lower limit
of the conversion range.
Circuit GND potential.
P10-P17
Port 1
TO
Pin #
RESET
+ 5V power supply.
AVcc
3
AID
SUBST
21
Substrate pin used with a bypass
capacitor to stabilize the substrate voltage and improve AID
accuracy.
V AREF
4
AID converter reference voltage.
Establishes the upper limit of the
conversion range.
ANO, AN1
6,5
Analog inputs to AID converter.
Software selectable on-chip via
SEL ANO and SEL AN1 instructions.
ALE
18
Address Latch Enable. Signal
occurring once every 30 input
clocks (once every cycle), used as
an output clock.
XTAL 1
22
One side of crystal, inductor, or
resistor input for internal oscillator. Also input for external frequency source. (Not TTL compatible.)
XTAL 2
23
Other side of timing control element. This pin is not connected
when an external frequency
source is used.
8022
ABSOLUTE MAXIMUM RATINGS·
:'
'Ie
,'>'"~,<~~~
\, '..' ."
'COMMENT: Stresses above those listed under""Aoso:lt.lte M~~m
Ratings" may cause permenent damage to the device', T{'liS" t~\ a 'st~i:./
rating only and functional operation of the device at these <1(' any o,\hel,,"
conditions above those indicated in the operational section's' of tkt~
specification is not implied. Exposure to absolute maximum rating ci:1n·
ditions for extended periods may affect device reliability.
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature .............. -65·C to + 180·C
Voltage on Any Pin with
Respect to Ground .................. -0.5V to + 7V
Power Dissipation .......................... 1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A=0·Ct070·C, Vee =5.5V ±1V, Vss=OV
Parameter
Symbol
Min.
Limits
Typ.
Max.
Unit
Test Conditions
Vil
Input Low Voltage (All except XTAL 1,
XTAL 2, Port 0)
-0.5
0.8
V
Vill
Input Low Voltage (Port 0)
-0.5
VTH -0.1
V
VIH
Input High Voltage (All except XTAL 1,
XTAL 2, RESET, Port 0)
2.0
Vee
V
Vee= 5.0V ± 10%
VIHl
Input High Voltage (All except XTAL 1,
XTAL 2, RESET, Port 0)
2.4
Vee
V
Vee = 6.0V ± 0.5V
VIH2
Input High Voltage (Port 0)
VTH+0.1
Vee
V
VIH3
Input High Voltage (RESET, XTAL 1)
3.0
Vee
V
VTH
Port 0 Threshold Reference Voltage
0
Vecl2
V
Val
Output Low Voltage
0.45
V
III = 1.6 rnA
Vall
Output Low Voltage (P10, P11)
2.5
V
IOl=7 rnA
VOH
Output High Voltage (All unless Open Drain
Option-Port 0)
V
IOH=50"A
2.4
III
Input Leakage Current (T1)
± 10
~
VIN=Vee
ILO
Output Leakage Current (Open Drain
Option-Port 0)
±10
"A
Vee;;'VIN;;'V SS + 0.45V
Icc
Vee Supply Current
VTl
Zero-Cross Detection Input (T1)
100
1
3
rnA
VACpp
Input through a
capaCitor
A.C. CHARACTERISTICS
TA=O·C to 70·C, Vee =5.5V ± 1V, Vss=OV
Symbol
Parameter
Min_
Max.
Unit
Test Conditions
tcv
Cycle Time
8.38
50.0
"s
3 MHz XTAL= 10 "s te v
tll
ALE Pulse Width
4.6
23.0
"s
tev= 10 "s
F=2.5MHz,R=15kQ
AF
Oscillator Frequency Variation- Resistor Mode
-20
+20
%
FTl
Zero-Cross Detection Input Frequency (T1)
0.03
1
kHz
A.C. TEST CONDITIONS
Control Outputs: C l = 80 pF
8-12
---
8022
~!I\
C";":!" "
A.C. CHARACTERISTICS
Expander
Operation
Normal
Operation
\I
'
"
tJ'".",
T A =0·Ct070·C, Vc c=5,5V ±1V, vss=ov
Symbol
>Ii __ , .
~"'!
Parameter
Min.
tcp
Port Control Setup Before Falling Edge of PROG
110
ns
tpc
Port Control Hold After Falling Edge of PROG
140
ns
tpR
PROG to Time P2 Input Must Be Valid
top
Output Data Setup Time
220
tpo
Output Data Hold Time
65
tPF
Input Data Hold Time
Max.
810
Unit
ns
ns
ns
0
150
ns
t pp
PROG Pulse Width
t pRL
ALE to Time P2 Input Must Be Valid
t pL
Output Data Setup Time
400
ns
tLP
Output Data Hold Time
150
ns
tpFL
Input Data Hold Time
0
ns
ns
1510
810
PORT 2 TIMING
1--------ICy---------1
ALE
_tLL_
EXPANDER
PORT
OUTPUT
!-----TpRL----I
EXPANDER
PORT
INPUT
tcp
PROO
8-13
tpc
ns
',~;;.:"4~
,,'
f,;",,'
Note'~. ',:, ':::" ,/".:
f'\,.
I
,"
8022
"..( .,~
,'
AID CONVERTER CHARACTERISTICS
T A =0·Cto70·C, Vcc=5.5V ±1V, Vss=OV, AV cc =5.5V ±1V, AVss=OV
Parameter
Resolution
Min.
Typ.
Max.
Unit
Comments: ..
Bits
8
± V2
LSB
(Note 1)
Zero Error
0
LSB
(Note2) T A =25·C
Full Scale Error
0
LSB
(Note3) T A =25·C
Non·Linearity
Absolute Accuracy
%
±1
Conversion Range
V AREF
AVss
V AREF
AVccl2
Input Capacitance (ANO, AN1)
Conversion Time
AVcc
1
V
pF
4
4
(Note 4)
V
tCY
Sample Hold Time (tAS)
0.07
tCY
(Note 5)
Sample Hold Time (tAH)
0.23
tCY
(Note 5)
Sample Setup Before Falling Edge of ALE (tss)
0.20
tCY
Sample Hold After Falling Edge of ALE (tSH)
0.10
tCY
ANALOG INPUT TIMING
I
ALE
ANALOG
INPUT
NOTES:
1. Non-linearity error is the maximum deviation from a straight line through the end pOints of the AID transfer characteristics.
2. Zero error is the difference between the output of an ideal and the actual AID for zero input voltage.
3. Full-scale error is the difference between the output of an ideal and the actual AID for full-scale input voltage.
4. Absolute accuracy describes the difference between the actual Input voltage and the full-scale weighted equivalent of the binary output.
Included are quantizing and all other errors.
5. The analog input must be maintained at a constant voltage during the sampling time (tAS) and the sample hold time (tAH).
8·14
8022
INSTRUCTION SET
He.adeclmal
Byte. Cycle
Opcode
De.crlptlon
Mnemonic
Add ,egiste, to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with
ca,ry
AD DC A,fdata Add immediate with
ca,ry
And ,egiste, to A
ANL A,A,
ANL A,@A
And data memo,y to A
And immediate to A
ANL A,fdata
Or register to A
ORL A,R,
0, data memo,y to A
ORL A,@A
0, immediate to A
OAL A,fdata
XAL A,A,
Exclusive Or register
to A
XRL A,@A
Exclusive 0, data
memory to A
Exclusive Or immediate
XAL A,*data
to A
INC A
Increment A
Decrement A
DEC A
Clea, A
CLR A
Complement A
CPL A
DAA
Decimal adjust A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Rotate A le,t th,ough
carry
AA A
Rotate A right
Rotate A right through
RRC A
carry
ADD A,A,
ADD A,@A
ADD A,fdata
AOOC A,A,
AOOC A,@A
.
.!!
:;
E
c
"
"
C
2
Output A to port
Input expander port
toA
Output A to expander
port
And A to expander port
Or A to expander port
S-
MOVD Pp.A
ANLD Pp.A
ORLD Pp.A
..
.5
.."e
!i
2
Input port to A
IN A, Pp
OUTL PpA
!i MOVD A,P p
g"
"D.
.5
68-6F
60-61
03
78-7F
70-71
t
2
13
.!
~
u::
Jump
Jump
Jump
Jump
Jump
CALL
Jump to subroutine
AET
Return
CLR C
CPLC
Clear carry
Complement carry
00-01
.
03
17
07
27
37
57
47
E7
F7
MOV
MOV
MOV
MOV
MOV
MOV
A,R,
A,@R
A,*data
R"A
@R,A
R"fdata
l;
C MOV A,T
0 MOV T,A
0 STRT T
STRT CNT
E
;:: STOP TCNT
"
'""
OS,09,OA
90,39,3A
OC-OF
JMP addr
Jump unconditional
JMPP @A
DJNZ R,addr
Jump indirect
Decrement register and
jump on A not zero
Jump on carry 1
Jump on carry 0
Jump on A zero
Jump on A not zero
04,24,33,64,
S4,A4,C4,E4
93
ES-EF
l;
t: RAD
">c0
SEL ANO
:( SEL AN1
EN I
=
=
16
14,34,54,74,
94,B4,04,F4
83
1k
97
A7
FS-FF
FO-F1
23
A8-AF
AO-A1
BS-BF
1
2
2
BO-B1
28-2F
20-21
30-'31
2
A3
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timerfcounter
42
62
55
45
65
Move conversion result
register to A
Select analog Input
zero
Select analog input one
80
3C-3F
9C-9F
SC-8F
1S-1F
10-"
JC addr
JNC addr
JZ addr
JNZ addr
TO= 1
TO=O
T1 = 1
T1 =0
time' flag
.
77
67
Increment register
Increment data memory
.
on
on
on
on
on
Move register to A
Move data memo,y to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to
register
II
> MOV @R,#data Move immediate to
0
:IE
data memory
S XCH A,R,
Exchange A and
c
register
XCH A,@R
Exchange A and data
memory
XCHO A,@R
Exchange nibble of A
and register
Move to A from current
MOVPA,@A
page
II:
"i!c
JTO
JNTO
JT1 add'
JNT1 add,
JTF add,
c
INC Rr
,ij.INC@R
ID
Description
'"
58-5F
50-51
53
4S-4F
40-41
43
08-0F
0
.s:;
Mnemonic
-E.
95
05
RET I
Enable external
interrupt
Disable external
interrupt
Enable timer/counter
interrupt
Disable timer/counter
interrupt
Return from interrupt
NOP
No operation
00
DIS I
2
l; EN TCNTI
:5
DIS TCNTI
F6
E6
C6
96
85
15
2,
35
93
SYMBOLS AND ABBREVIATIONS USED
A
addr
ANO, AN1
CNT
data
I
P
Pp
Rr
T
TO, T1
#
Accumulator
11·Bit Program Memory Address
Analog Input 0, Analog Input 1
Event Counter
8-Bit Number or Expression
Interrupt
@
8·15
Mnemonic for "in-page" Operation
Port Designator (p = 1, 2,or 4-7)
Register DeSignator (r = 0-7)
Timer
Test 0, Test 1
Immediate Data Prefix
Indirect Address Prefix
8022
struction makes very efficient use of fhe working regis·
ters as program loop counters by aHowing'the program·
mer to decrement and test the register in a s'lngle in·
struction.
.
FUNCTIONAL DESCRIPTION
PROGRAM MEMORY
The 8022 program memory consists of 2048 words 8 bits
wide which are addressed by the program counter. The
memory is ROM which is mask programmable at the fac·
tory. No external ROM expansion capability is provided.
There are three locations in program memory of special
importance.
Registers 0 and 1 have yet another function in that they
can be used to indirectly address all locations in the
data memory using the indirect register instructions.
These two RAM pointer registers are especially useful
for repetitive type operations on adjacent memory loca·
tions. The indirect register instruction specifies which
pOinter register to use and the content of the pointer
register is used to address a location in RAM. The con·
tents of the addressed location are used during the exe·
cution of the instruction and may be modified. The
pOinter registers may also point to registers 0-7, if
desired.
Location 0: Activating the RESET line of the proces·
sor causes the first instruction to be
fetched from location O.
Location 3: Activating the interrupt input line of the
processor (if interrupt is enabled) causes
a jump to subroutine.
Locations 8-23 serve a dual role in that they contain the
8-level program counter stack, two RAM locations per
level. The program counter stack enables the processor
to keep track of the return addresses generated by inter·
rupts or CALL instructions by storing the contents of
the program counter prior to servicing the subroutine. A
3-bit stack pOinter determines which of the program
counter stack's eight register pairs will be loaded with
the next return address generated. The stack pointer,
when initialized to 000 by RESET, points to RAM loca·
tions 8 and 9. The first subroutine jump or interrupt
results in the program counter contents being trans·
ferred to locations 8 and 9. The stack pOinter is then in·
cremented by one and pOints to locations 10 and 11 in
anticipation of another CALL. The end of a subroutine,
which is signaled by a return instruction (RET or RETI),
causes the stack pointer to be decremented and the
contents of the resulting register pair to be transferred
to the program counter.
Location 7: A timer/event counter interrupt resulting
from a timer/counter overflow causes a
jump to subroutine (if timer/counter inter·
rupt is enabled).
Therefore, the first instruction to be executed after in·
itialization is stored in location 0, the first word of an ex·
ternal interrupt service routine is stored in location 3,
and the first word of a timer/event counter interrupt ser·
vice routine is stored in location 7.
2047 r - - - - - ,
1------
LOCATION 7- TIMER/COUNTER INTERRUPT
VECTORS PROGRAM HERE
Since the program counter's addresses are 11 bits long,
two bytes or registers must be used to store a single ad·
dress. Thus, the 16-byte program counter stack permits
up to a total of 8 levels of subroutine nesting without
overflowing the stack. If overflow does occur, the
deepest address stored (locations 8 and 9) will be over·
written and lost since the stack pOinter overflows from
111 to 000. It also underflows from 000 to 111. If a parti·
cular application does not require 8 levels of nesting,
tthe unused portion of the program counter stack may
be used as any other indirectly addressable RAM loca·
tion. For example, if only 3 levels of subroutine nesting
are used, then only locations 8-13 need be reserved for
the program counter stack, and locations 14-23 can be
used for data storage.
LOCATION 3-EXTERNAlINTERRUPT
VECTORS PROGRAM HERE
7 6 5 4 3 2 1 0
RESET VECTORS PROGRAM HERE
PROGRAM MEMORY MAP
Program memory can be used to store constants as well
as program instructions. The MOVP instruction allows
easy table lookup for constants and display formatting.
DATA MEMORY
On·chip data memory is organized as 64 words eight bits
wide. All locations are indirectly addressable and eight
designated locations are directly addressable. Also in·
cluded in the data memory is the program counter stack,
addressed by a 3-bit stack pOinter.
I'
24
23 8 LEVEL STACK
OR
USER RAM
16)( 8
The first eight locations (0-7) of the array are designated
as working registers and are directly addressable by any
of the 11 direct register instructions. These locations
are readily accessible for a variety of operations with a
minimum number of instruction bytes required for their
manipulation. Thus, they are usually used to store fre·
quently accessed intermediate results. The DJNZ in·
WORKING
REGISTERS
8.8
Rl
RO
DATA MEMORY MAP
8-16
ADDRE SSED
INDIRECTLY
THROU GH
ROORR 1
DIRECTLy
ADDREiSABLE
8022
,I,
INPUT/OUTPUT
i.e., inputs must be present until react"by an input in·
struction. Inputs are fully TTL c6mpatible"'anO-a.l1 out·
puts will drive at least one standard TTL 10ad,'TWo /tIies
of port 1 (P10 and P11) are designated as high currertt:: ....
drive lines and have the ability to sink 7 mA. lri'addltion;' .,.
these pins may be paralleled for 14 mA output if the·out·
put iogic states are always the same. The high current
output lines eliminate the need for discrete transisiors
in many applications.
The 8022 has 26 lines which can be used for digital input
or output functions. These lines are organized as 3 ports
of 8 lines, each of which serve as either inputs, outputs,
or bidirectional ports, and 2 test inputs which can alter
program sequences when tested by conditional jump in·
structions.
Ports 1 and 2 have identical operating characteristics
and are both quasi·bidirectional. That is, each line may
serve as an input, an output, or both. Data written to
these ports is statically latched and remains unchanged
until rewritten. As inputs, these lines are non·latching;
The lines of ports 1 and 2 are quasi·bidirectional
because of their output structure which allows them to
be used as inputs, outputs, or both, even though as out·
puts they are statically latched.
+5V
+5V
Q
INTERNAL
BUS
=50KQ
0
0
110 PIN
PORTS 1
AND2
FLIp·
FLOP
eLK
is
WRITE
PULSE
QUASI-BIDIRECTIONAL PORT STRUCTURE
Each line is continuously pulled up to + 5V through a
relatively high impedance device ("'50 kQ). This pullup is
sufficient to provide the source current for a TTL high
level, yet can be pulled low by a standard TTL gate, thus
allowing the same pin to be used both as an input and
output. When writing a "0" or low value to these ports, a
low impedance device ("'300Q) overcomes the high
pullup and provides TTL current sinking capability.
When writing a "1", a large current is momentarily supplied through a relatively low impedance device ("'5kQ)
to allow a fast data transfer. After a short time (less than
one instruction cycle) the low impedance device is shut
off and the small pullup maintains the "1" level indefinitely. In this Situation, an input device capable of overriding the small amount of sustaining current supplied
by the pullup device can be read. (Alternatively, the data
written cn be read.) So, by writing a "1" to any particular
pin that pin can serve either as a true high-level latched
output pin, or as just a pullup resistor on an input. This
allows maximum user flexibility in selecting his input or
latched output lines, with a minimum of external
components.
PORT 0 COMPARATOR INPUTS
Port 0 has been modified from the standard quasibidirectional structure to allow an optional open drain
configuration with comparator inputs. The low impedance pullup device has been eliminated and the high impedance pullup is optional. Thus, the user can choose
via a mask programmable seiection each line of port 0 to
be either quasi-bidirectional with a high impedance or
true open·drain. The open drain configuration allows the
line to sink current through the low impedance pulldown
device or to float in the high output state. More impor·
tantly, the open drain configuration makes port 0 very
easy to drive when it is used as inputs. The input cir·
cuitry for each line of port 0 includes a voltage com·
parator which amplifies the voltage difference between
the "input port line and the port 0 threshold reference pin
(VTH). The voltage gain of the comparator is sufficient to
sense a 100 mV input differential within the range Vss to
Vcc/2.
8·17
8022
+5V
INTERNAL
BUS
Q
0
~50KQr-----'
0
1/0 PIN
PORTO
FLIp·
FLOP
i:i
elK
WRITE
PULSE
VTH
PORT 0 1/0 STRUCTURE
If VTH is allowed to float, it will bias itself to the digital
switch point of the other ports, and port 0 behaves as a
set of normal digital inputs. However, by biasing VTH ,
the switch point can be both tightly controlled and adjusted. Common uses for this would include high noise
margin inputs (Vccf2), unusual logic level inputs as from
a diode isolated keyboard, analog channel expansion,
and direct capacitive touchpanel interface. The comparator action is automatic and the port is read just as any
other port.
A 4-bit transfer from a port to the lower half of the accumulator sets the most significant four bits to zero.
Each transfer consists of two 4-bit nibbles. The first
contains the "opcodes" and port address, and the second contains the actual 4 bits of data. A high-to-Iow transition of the PROG line indicates that address is present
while a low-to-high transition indicates the presence of
data.
In addition to the 26 digital 1/0 lines contained on-board
the 8022, a user can obtain additional 1/0 lines by utilizing the Intel® 8243 1/0 expander chip or standard TTL
The 8243 interfaces to 4 port lines of the 8022 (lower half
of port 2) and is strobed by the PROG line of the 8022.
In addition to the 24 general purpose 1/0 lines which
comprise ports 0, 1, and 2, the 8022 has two inputs
which are testable via conditional jump instructions, TO
and T1. These pins allow inputs to cause program
branches without the necessity to load an input port into the accumulator. TO and T1 have other functions as
well.
4
TEST AND INTERRUPT INPUTS
The Test 0 pin serves as an external interrupt input as
well as a testable input. An interrupt sequence is initiated by applying a low "0" level input to the TO pin when
external interrupt is enabled. Interrupt is level triggered
and active low to allow "WIRE ORING" of several interrupt sources at the input pin. When an interrupt is
detected, it causes a "jump to subroutine" at location 3
in program memory as soon as all other cycles of the
current instruction are complete. At this time, the program counter contents are saved in the program counter
stack, but the remaining status of the processor is not.
Unlike the 8048, the 8022 does not contain a program
status word. Thus, when appropriate, the carry and auxiliary carry flags are saved in software, as the accumulator is. The routine shown below saves the accumulator
and the carry flags in only four bytes.
)
4
8022
8243
v
"
4
P20-3
4
PROG
I
4
P20-3
PROG
1
1/0 EXPANDER INTERFACE
Instructions
The 8243 contains four 4-bit 1/0 ports which serve as extensions of the on-chip 1/0 and are addressed as ports
4-7. The following operations may be performed on
these ports:
1.
2.
3.
4.
MOV R6,A
CLR A
DAA
MOV R7,A
Transfer Accumulator to Port
Transfer Port to Accumulator
And Accumulator to Port
Or Accumulator to Port
Bytes
Comments
;save accumulator
;clear accumulator
;convert carry flags into sixes
;save status of carry flags
The end of an interrupt service subroutine is marked by
the execution of a Return from Interrupt instruction
(RETI). Prior to returning from the interrupt subrouti.ne
8-18
8022
however, the status of the accumulator and the carry
flags are restored in software. The following routine
restores the status of the accumulator and the carry
flags, which was previously saved, in five bytes.
Instructions
Bytes
MOV A,R7
The internal digital state is sensed as a zero.:until the rising edge crosses the DC average level, wtiem.it):re<;;omes
a one. This is accomplished by the self-biasing high
gain amplifier which is included in the T1 input, This ci.r.cuit biases the T1 input exactly at its switching pOint,
such that a small change will cause a digital transition
to occur. This digital transition takes place within 5
degrees of the zero pOint. The digital value of T1 remains
a one until the falling edge of the AC input drops approximately 100 mV below the switching point of the rising
edge (100 mV below the zero pOint, if the digital transition occurred exactly at the zero point). The 100 mV offset is created by hysteresis and eliminates chattering of
the internal signal caused by the external noise.
Comments
;restore carry flags status to
;accumulator and set/clear carry flags
;restore accumul3tor
;return
Add A.#OAAH
MOV A,R6
RET!
The interrupt system is single level in that once an interrupt is detected, all further interrupt requests are ignored until execution of a RETI re-enables the interrupt
input logic. This sequence holds true also for an internal
interrupt generated by timer overflow. If an external interrupt and an internal timer/counter generated interrupt
are detected at the same time, the external source will
be recognized. If needed, a second external interrupt
can be created by enabling the timer/counter interrupt,
loading FFH in the counter (one less than terminal
count) and enabling the event counter mode. A low-tohigh transition on the T1 input will then cause an interru pt vector to location 7.
The zero cross detection capability allows the user to
make the 60 Hz power signal the basis for this system
timing. All timing routines, including time-of-day, can be
implemented using the zero cross detection capability
of T1 and its conditional jump instructions. In addition,
the zero cross detection feature can be used in conjunction with the timer interrupt to interrupt processing at
the zero voltage point. This enables the user to control
voltage phase sensitive devices such as triacs and
SCRs, and to use the 8022 in applications such as shaft
speed and angle measurement.
The Test 1 pin, in addition to being a testable input,
serves two other important functions. It can be used as
an input pin to the external event counter, as previously
mentioned, and it can be used to detect the zero crossing point of slow moving AC signals. Execution of the
STRT CNT instruction puts the T1 pin in the counter input mode by connecting T1 to the counter and enabling
the counter. Subsequent low-to-high transitions on T1
will cause the counter to increment. Note that this
operation differs from the rest of the MCS-48 devices,
which increment the counter on high-to-Iow transitions.
This change was made on the 8022 to take advantage of
the accuracy of the rising edge detection on the zero
cross circuitry. The maximum rate at which the counter
may be incremented is once per three instruction cycles
(every 30 I-'s when using a 3 MHz crystal) - there is no
minimum frequency.
ANALOG TO DIGITAL CONVERTER
The 8022 contains on-chip a complete hardware implementation of an 8-bit analog to digital (AID) converter
with two multiplexed analog inputs. The AID converter
utilizes a successive approximation technique to provide an updated conversion once every four instruction
cycles (i.e., once every 40 I-'s) with a minimum of required
software.
The AID converter consists of four main parts, the input
circuitry, a series string of resistors, a voltage comparator, and the successive approximation logic. The two
analog inputs are multiplexed on-Chip and selected via
software by the SEL ANO and SEL AN1 instructions. Besides selecting one of the analog inputs, these instructions restart the conversion sequence which operates
continuously. Restarting a conversion sequence deletes
the conversion in progress but does not effect the resu It
of the previous conversion which is stored in the conversion result register. The continuous operation of the AID
converter saves program space and time by allowing the
user obtain multiple readings from a given input with
only one select instruction. To obtain a valid conversion
reading, the user must provide the analog input Signal
no later than the beginning of the select instruction
cycle. The analog input is then sampled by the AID converter and maintained internally. This voltage becomes
one input to the voltage comparator which amplifies the
difference between the analog input and the voltage tap
on the series resistor string.
In addition to serving as a testable input and as the
counter input, the T1 pin has special circuitry to detect
when an AC signal crosses its average DC level. When
driven directly, this pin responds as a normal digital input. To utilize the zero cross detection mode, an AC
signal of approximately 1-3 VAC pop magnitude and a
maximum frequency of 1 kHz is coupled through an external capacitor (1 I-'F) to the T1 pin.
T
f'
-+----*';-1----,1'----1-3 VAC
8022
~
INTERPRETATION
I
T11
AC SOURCE---j
'-----Ir-
P
The series resistor string is connected between the AID
reference pin (V AREF) and ground (AVss). It is comprised
of 256 identical resistors which divide the voltage between these two pins into 256 identical voltage steps.
This configuration gives the converter its inherent
monotonicity. The range of VAREF in which full 8-bit
resolution can be provided is between Ve cl2 and Vee.
~
r~;-TO TlIEVENT COUNTER
I
1 MF
I
I
ZERO-CROSS DETECTION
8-19
8022
To insure maximum accuracy fr6rht'~e ~/O.converter,
separate power supply pins (AVcc and Ay~s)·~b:~\~ ~ub
strate pin (SUBST) have been provided.SUpptYifi.g';.!.ne,
power supply pins with a well filtered and'f~g'ulat8(;l:;:'
voltage supply minimizes the effect of powElr.$Opply"
variance and system noise. The substrate pin should tie.
bypassed to ground through a 500 pF to 0.001 flF capacitor.
Thus, the user is given a minimum voltage range from
ground to VCcl2 and a maximum range from ground to
Vcc over which 8-bit resolution is insured.
The voltage tap on the series resistor string is selected
by the resistor ladder decoder. This decoder is driven by
the 8-bit successive approximation register (SAR). Each
bit of the SAR is set in succession MSB to LSB and a
voltage comparison between the selected resistor ladder voltage and the analog input voltage is performed
after the setting of each bit. The result of each comparison determines whether the particular bit will remain set or be reset. All comparisons are performed
automatically by the on-chip AID hardware. At the end of
8 comparisons the SAR contains a valid digital result
which is then latched into the conversion result register
(CRR). The RAD instruction (read AID) loads the conversion result from the CRR to the accumulator of the 8022.
ANALOG MULTIPLEXER
r---~
I
I
As mentioned previously, the software and time required to perform an AID conversion is optimized by the
8022's on-chip AID converter configuration. Typical software for reading two sequential AID conversions and
storing them in data memory is shown below:
I
RESISTIVE
LADDER
--'-'---,
I
I
Rl2
First
SEL ANO
;Starts conversion of ANO input
Conversion
MOV RO,#24
RAD
;Set up memory pointer
;First conversion value to accumulator
Second
MOV@RO.A
;Store first conversion value
Conversion
INC RO
;Increment memory location
RAD
;Second conversion value to accumulator
50 ~s
4 bytes
40 ~s
3 bytes
R
I
ffi
I
~
1~8
I l
8-W
I
i
Rl2
L _ _ L..J
Note that the second conversion occurs without a second select instruction being used. Rather, the continuous operation of the AID converter provides an updated digital value 4 instruction cycles after the first.
INTERNAL BUS
AID CONVERTER BLOCK DIAGRAM
r----...---.. XTAL 1
r---"XTAL1
OPTIONAL C
RECOMMENDED
R
'----<>----.. XTAL 2
'---"XTAL2
INDUCTOR
RESISTOR
+5V
1K
,---.._---1 XTAL 1
CJ
lo-.....-*'---..... XTAL 1
1 MEGQ
'----*'---.. XTAL 2
NC
.6-3 MHz
EXTERNAL
CRYSTAL
FREQUENCY REFERENCE OPTIONS
8-20
XTAL 2
8022
OSCILLATOR AND CLOCK
CPU
The 8022 contains its own on-board oscillator and clock
circuit, requiring only an external timing control element This control element can be a crystal, inductor,
resistor, or clock in_ The capacitor normally required in
resistor or inductor timing control operation is integrated onto the 8022. All internal time slots are derived
from the external element, and all outputs are a function
of the oscillator frequency. Pins X1 and X2 are used to
input the particular control element An instruction
cycle consists of 10 states, and each state is a time slot
of 3 oscillator periods. Therefore, to obtain a 10 fls
instruction cycle, a 3 MHz crystal should be used.
The 8022 CPU has arithmetic and logiyal ca~i,n\¥·.,A
wide variety of arithmetic and logic instructions mal/:"'~~;il
exercised, which affect the contents of the. C!CCj.I,niU",i
lator, and/or direct or indirect scratch pad 10catioM. Pi'()o.
visions have been made for simplified BCD arithmetic
capability through the use of the DAA, SWAP A, and
XCHD instructions. In addition, MOVP A,@A allows
table lookup for display formatting and constants. Jump
conditions such as zero, not zero refer to the accumulator contents at the time of the condition.
TIMER/COUNTER
The 8022 may be used in systems with poorly regulated
and noisy power supplies. A useful feature is to sense
when the power supply dips and quickly recovers, and
do a reset to prevent continued operation with incorrect
data. This feature may be implemented on the 8022 by
connecting a diode between the RESET node and
ground.
RESET
An interval timer/counter is available to enable the user
to keep track of time elapsed or number of events occurred during normal program execution and flow.
By a MOV T,A instruction, the contents of the accumulator are loaded to the timer. At the STRT T command an
internal prescaler is zeroed and thereafter increments
once each 30 input clocks (once each single cycle instruction, twice each double cycle instruction). The prescaler is a divide by 32. At the (11111) to (00000) transition the timer is incremented. The timer is 8 bits and an
overflow (FFH) to (OOH) timer flag is set along with the
timer interrupt, if enabled. A conditional branch instruction (JTF) is available for testing this flag, the flag being
reset each test This instruction must also be used to initialize the timer overflow flag after a RESET instruction,
as RESET does not perform this function. Total count
capacity for the timer is 28 X 25=8192 or 81.9 ms at a 10
fls cycle time. Contents of the timer are moved to the accumulator by the MOV A,T instruction without disturbing the counting process.
Including the diode in the reset circuitry forces a reset
to occur if the power supply experiences a very sudden
voltage glitch. Specifically, if the power supply drops
approximately 1.5V and recovers after at least a few
nanoseconds, a reset will occur. Without the diode, a
power supply interruption of less than 1 ms will not
cause a power-on reset
Vee
l"Fl
10V
8022
24
t------j
The timer may also be used as an event counter. After a
STRT CNT command, the 8022 will respond to a low-tohigh transition on the Test 1 pin by incrementing the
timer. Transitions can occur no faster than once each
three instruction cycles.
OPT~~~~~
~
The timer and event functions are exclusive. Counting
or timing may be started or stopped (STOP TCNT) at will.
POWER ON RESET
INTEL CORPORATION. 3065 Bowers Avenue. Santa Clara, CA 95051 • (408) 987·8080
Printed in U.S.A./T-244/I078/15K BL
8-21
RESET
inter
8048/8648/8748/8035
SINGLE COMPONENT 8-BIT MICROCOMPUTER
•
•
•
•
8048 Mask Programmable ROM
8648 One-Time Factory Programmable EPROM
8748 User Programmable/Erasable EPROM
8035/8035L External ROM or EPROM
8-Bit CPU, ROM, RAM, 1/0 in
• Single
Package
Interchangeable
ROM and EPROM
• Versions
SV Supply
• Single
2.5
",sec
and 5.0 ",sec Cycle Versions
• All Instructions
1 or 2 Cycles.
• Over 90 Instructions: 70% Single Byte
ROMIEPROM
• 641K xx 88 RAM
27110 Lines
Interval TimerlEvent Counter
Easily Expandable Memory and 1/0
Compatible with 808018085 Series
Peripherals
•
•
•
• Single Level Interrupt
The Intel'" 8048/86481874818035 Is a totally self-sufficient, 8-bit parallel computer fabricated on a single silicon chip
using Intel's N-channel silicon gate MOS process.
The 8048 contains a 1K x 8 program memory, a 64 x 8 RAM data memory, 27 I/O lines, and an 8-bit timer/counter in addition to on-board oscillator and clock circuits. For systems that require extra capability, the 8048 can be expanded
using standard memories and MCS-80™/MCS-85TM peripherals. The 8035 is the equivalent of an 8048 without program
memory. The 8035L has the RAM power-down mode of the 8048 while the 8035 does not. The 8648 is a one-time programmable (at the factory) 8748 which can be ordered as the first 25 pieces of a new 8048 RAM order. The substitution
of 8648's for 8048's allows for very fast turnaround for initial code verification and evaluation units. To reduce development problems to a minimum and provide maximum flexibility, three interchangeable pin-compatible versions of this
single component microcomputer exist: the 8748 with user-programmable and erasable EPROM program memory for
prototype and preproduction systems, the 8048 with factory-programmed mask ROM program memory for low cost,
high volume production, and the 8035 without program memory for use with external program memories.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8048 has extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory
results from an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
8048
8-22
8048/8648/8748/8035
PiN DESCRIPTION
#
Function
Designation
20
Circuit GND potential
RD
26
Programming power supply; +25V
during program, +5V during operation for both ROM and PROM.
low power standby pin in 8048
and 8035l.
Designation
Pin
VSS
V DD
Vee
40
Main power supply; +5V during
operation and programming.
PROG
25
Program pulse (+23V) input pin
during 8748 programming.
DBa-DB7
BUS
RESET
4
Input which is used to initialize the
processor. Also used during PROM
programming verification, and
power down. (Active low)
(Non TTL VIH )
WR
10
8-bit quasi-bidirectional port.
Output strobe during a bus write.
(Active low)
21-24
35-38
8-bit quasi-bidirectional port.
Used as write strobe to external
data memory.
12-19
TO
INT
Output strobe activated during a
BUS read. Can be used to enable
data onto the bus from an external
device.
27-34
P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit I/O expander
bus for 8243.
ALE
True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Input pin testable using the conditional transfer instructions JTO
and JNTO. TO can be designated as
a clock output using ENTO ClK
instruction. TO is also used during
programming.
39
6
11
Address latch enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives
the addressed instruction under the
control of PSEN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
T1
8
Function
Used as a read strobe to external
data memory. (Active low)
Output strobe for 8243 I/O
expander.
P10-P17
Port 1
P20-P27
Port 2
Pin #
Input pin testable using the JT1,
and JNT1 instructions. Can be designated the timer/counter input using
the STRT CNT instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
8·23
PSEN
9
Program store enable. Th is output
occurs only during a fetch to external program memory. (Active low)
SS
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction. (Active low)
EA
7
External access input which forces
all program memory fetches to reference external memory. Useful
for emulation and debug, and
essential for testing and program
verification_ (Active high)
XTAL1
2
One side of crystal input for internal oscillator. Also input for external source. (Non TTL V IH )
XTAl2
3
Other side of crysta I input_
8048/8648/8748/8035
INSTRUCTION SET
Description
ADD A, R
ADD A,@R
ADD A, tidata
ADDC A, R
ADDC A,@R
ADDC A, #data
ANL A, R
ANL A,@R
Ado register to A
Add data memory to A
ANL A, "data
ORL A, R
ORL A, @R
3
OR L A, #data
E XRL A, R
u XRL A, @R
u
oCt
XR L A, #data
INCA
DEC A
CLR A
CPLA
DAA
SWAP A
RLA
RLC A
RR A
RRCA
e
"
"
IN A, P
OUTL P, A
ANL P, #data
;; ORL P, #data
B- INS A, BUS
0
." OUTL BUS, A
Q. ANL BUS, #data
OR L BUS, #data
MOVD A, P
MOVD P, A
ANLD P, A
ORLD P, A
"
.:"
;'"
1;1
i
a:
..c
.
u
~
di
Bytes
Mnemonic
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Cycle
1
2
1
2
1
2
1
2
1
2
2
2
2
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right through carry
2
2
I nput port to A
Output A to port
And immediate to port
Or immediate to port
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
2
2
2
2
I nput expander port to A
Output A to expander port
And A to expander port
Or A to expander port
INCR
INC@R
DEC R
Increment register
Increment data memory
Decrement register
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
J Z addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF 1 addr
JTF addr
JNI addr
JBb addr
Jump unconditional
Jump indirect
Decrement register and skip
Jump on carry -= 1
Jump on carry = 0
Jump on A zero
Jump on A not zero
~
~
~
~
1
0
1
0
1
1
Jump on timer flag
Jump on INT
~
0
Jump on accumulator bit
2
2
2
2
2
2
2
2
2
2
2
2
2
Move immediate to A
Move A to register
Move A to data memory
2
2
Move immediate to register
2
2
Return and restore status
Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
MOV A, T
MOVT, A
STRTT
0
~ STRT CNT
~ STOP TCNT
E
i= EN TCNTI
DIS TCNTI
Read timer/counter
Load timer/counter
Start timer
Start counter
2l~
"
E
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Cycles
1
Move data memory to A
Move immediate to data memory
1
2
2
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
1
Move external data memory to A
2
2
2
2
Move A to external data memory
Move to A from current page
Move to A from page 3
2
u
1
Bytes
Jump to subroutine
Return
Move register to A
0
2
Description
MOV A, R
MOV A,@R
MOV A, #data
MOV R,A
MOV@R,A
MOV R, #data
'"
> MOV@R,"'data
0
:;; MOV A, PSW
~ MOV PSW, A
C XCH A, R
XCHA,@R
XCHD A,@R
MOVX A,@R
MOVX@R,A
MOVPA,@A
MOVP3 A,@A
.
Rotate Aright
~
C
C
FO
FO
F1
F1
"
Decimal adjust A
~
CALL addr
RET
RETR
CLR
CPL
'" CLR
3'"
u. CPL
CLR
CPL
1
2
Clear A
Complement A
TO
TO
T1
T1
FO
F1
.="
l!"
.c
en
"
1
2
Increment A
Decrement A
Jump on
Jump on
Jump on
Jump on
Jump on
Jump on
Mnemonic
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Stop timer/cou nter
Enable timer/counter interrupt
Disable timer/counter interrupt
EN I
DIS I
SEL RBO
SEL RB1
SEL MBO
SEL MB1
ENTO ClK
Select register bank 0
Select register bank 1
Select memory bank 0
NOP
No operation
Enable external interrupt
Disable external interrupt
Select memory bank 1
Enable clock output on TO
Mnemonics copyright Intel Corporation 1976
8·24
1.
1
8048/8648/8748/8035
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ........... O°C to 70°C
Storage Temperature ................... -65°C to +150°C
Voltage On Any Pin With Respect
to Ground ............................. -0.5V to +7V
Power Dissipation .............................. 1.5 Watt
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied.
D.C.AND OPERATING CHARACTERISTICS TA=O·C to 70·C, Vee=Voo=
Symbol
+5V ± 10%, VSS=OV
Parameter
Unit
V1L
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.8
V
V1L1
Input Low Voltage
(RESET, X1, X2)
-.5
.6
V
V1H
Input High Voltage
(All Except XTAL 1, XTAL 2, RESET)
2.0
Vec
V
VO L1
Output Low Voltage
(RD, WR, PSEN, ALE)
VOL3
Output Low Voltage
(All Other Outputs)
VOH1
Output High Voltage
(RD, WR, PSEN, ALE)
2.4
VOH2
Output High Voltage
(All Other Outputs)
2.4
ILl1
Input Leakage Current
(P10·P17, P20·P27, EA, SS)
-500
I LO
Output Leakage Current (BUS, TO)
(High Impedance State)
±10
BUS
Vss+ .45<:VIN~Vee
P1, P2
BUS, P1, P2
-500,...
-50 rnA
SOmA
30mA
-300 ",A
:I:
g
:I:
5}
5}
-100,...
4V
VOH
Test Conditions
10mA
OV
OV
VOH
8·25
Ci2V
4V
VOL
8048/8648/8748/8035
WAVEFORMS
Instruction Fetch From External Program Memory
Read From External Data Memory
-.-LL--j------
\'------J/
-- -<,,__A_~D_E~_~_S_S
ADDRESS
(0-7) VAllO
_______-J)<:,,_____
\'----_~_~_~_TV_~_~T_'~...J>-
_...JX....
-
-
-
-
-
-
-
)<:. . ______
A_D_D_R_ES_S_I_8-_9_IV_A_L_'_D_ _ _ _ _ _ _
N_E_X_T_A_D_D_RE_S_S_V_A_L_'D_ _ _ _ _ _ ___
NOTES:
1. PROG MUST FLOAT IF EA IS LOW {;.e" io23VI, OR IF TO" 5V FOR THE 8748, FOR THE
8048 PROG MUST ALWAYS FLOAT,
2, Xl AND X2 DRIVEN BY 3 MHz CLOCK WILL GIVE 5",ec 'CY, THIS IS ACCEPTABLE FOR
,8 PARTS AS WELL AS STANDARD PARTS,
The 8748 EPROM can be programmed by either of two
Intel products:
1, PROMPT -48 Microcomputer Design Aid. or
2, Universal PROM Programmer (UPP series) peripheral
of the Intellec@ Development System with a UPP-848
Personality Card.
8-30
Note: See the ROM/PROM section tor 8048 ROM ordering procedures.
To minimize turnaround tIme on the first 25 pieces 8648 may be
specified on the ROM order.
NEW HIGH PERFORMANCE
'''''''',\
8049/8039/8039·6
SINGLE COMPONENT 8·BIT MICROCOMPUTER
*8049 Mask Programmable ROM
*8039 External ROM or EPROM
*New 11 MHz Operation
• 8·Bit CPU, ROM, RAM, 1/0 in
Single Package
• 2K)( 8 ROM
128)( 8 RAM
27110 Lines
• Single 5V ± 10% Supply
• Interval TimerlEvent Counter
• 1.36 iLSec Cycle; All Instructions
1 or 2 Cycles
• Easily Expandable Memory and 1/0
• Compatible with MCS Memory and 1/0
• Single Level Interrupt
• Over 90 Instructions: 70% Single Byte
• Pin Compatible with 8048/8748
The Intell!> 8049/8039/8039-6 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using
Intel's N-channel silicon gate MOS process.
The 8049 contains a 2Kx 8 program memory, a 128 x 8 RAM data memory, 27 I/O lines, and an 8-bit timer/counter in
addition to on board oscillator and clock circuits. For systems that require extra capability, the 8049 can be expanded
using standard memories and MCS-80™/MCS_85TM peripherals. The 8039 is the equivalent to an 8049 without program
memory. The 8039-6 is a lower speed (6MHz) version of the 8039.
To reduce development problems to a minimum and provide maximum flexibility, two interchangeable pin-compatible
versions of this single component microcomputer exist: the 8049 with factory-programmed mask ROM program
memory for low-cost high volume production, and the 8039 without program memory for use with external program
memories in prototype and preproduction systems.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8049 has extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory
results from an instruction set consisting mostly of single byte instructions and no instructions over two bytes in
length.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
PORT
=i
PORT
.2
READ
8049
WAITE
PROGRAM
STOAE
ENABLE
ADDRESS
LATCH
ENABLE
PORT
EXPANDER
STROBE
8-31
UU".'OU~.'OU"'1:J·U
"
PIN DESCRIPTION
"
#
Function
Designation
20
Circuit GND potential
RD
Voo
26
+5V during operation. low power
standby pin.
Vee
40
Main power supply; +5V during
operation.
25
Output strobe for 8243 1/0
expander.
B-bit quasi-bidirectional port.
Designation
Pin
Vss
PROG
P10-P17
Port 1
P20-P27
Port 2
00-07
BUS
27-34
21-24
35-38
12-19
T1
INT
6
Function
" ,
~
,I, .t
"
' , ",,, "·i
P2Q-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit 1/0 expander
bus for 8243
4
Input which is used to initialize the
processor. Also used during verification, and power down. (Active
low) (Non TTL VIH)
WR
10
Output strobe during a BUS write.
(Active low)
Used as write strobe to External
Data Memory.
ALE
11
True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Input pin testable using the JT1,
and JNT1 instructions. Can be designated the timer lcounter input using
the STRT CNT instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
8-32
~'"
Output strobe activated during a., "":'::'
BUS read. Can be used to enable
data onto the BUS from an external
device.
RESET
B-bit quasi-bidirectional port.
Input pin teStable using the conditional transfer instructions JTO
and JNTO. TO can be designated as
a clock output using ENTO ClK
instruction.
39
8
#
Used as a Read Strobe to External
Data Memory. (Active low)
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives
the addressed instruction under the
control of PSEN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
TO
Pin
Address Latch Enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
PSEN
9
Program Store Enable. This output
occurs only during a fetch to external program memory. (Active low)
SS
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruc;tion. (Active low)
EA
7
External Access input which forces
all program memory fetches to reference external memory. Useful
for emulation and debug, and
esse nt ia I for test ing and progra m
verification. (Active high)
XTAL1
2
One side of crystal in put for internal oscillator. Also input for external source. (Not TTL Compatible)
XTAl2
3
Other side of crystal input.
8049/8039/8039·6
INSTRUCTION SET
Mnemonic
ADDA, R
ADD A,@R
ADD A, #data
ADDC A, R
ADDC A,@R
AD DC A, #data
ANL A, R
ANL A, @R
ANL A, #data
ORLA, R
ORL A, @R
.!l!
ORL A, #data
E XRLA, R
XRLA,@R
~
XRL A, #data
INCA
DECA
CLR A
CPLA
DAA
SWAP A
RLA
RLCA
RR A
RRCA
B
"
""
"
~
"
S-
g"
.:"
Q.
..
~
t;
';;,
"
IX
~
"~
Iii
IN A, P
OUTL P, A
ANL P, #data
ORL P, #data
INS A, BUS
OUTL BUS, A
AN L BUS, #data
ORL BUS,#data
MOVD A, P
MOVD P, A
ANLD P, A
ORLD P, A
INCR
INC@R
DECR
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
J Z addr
JNZ addr
JTO addr
JNTO addr
JTl addr
JNTl addr
JFO addr
JF 1 addr
JTF addr
JNI addr
JBb addr
Description
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
Bytes
Cycle
.
'E
:J
1
e
.a
'""
2
1
1
1
1
2
2
~
E
And data memory to A
2
And immediate to A
2
Or register to A
Or data memory to A
1
1
Or immediate to A
2
2
1
1
2
2
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
.
1:
"0
~
~
E
j::
Increment register
Increment data memory
e1:
Decrement register
0
U
Jump unconditional
Jump indirect
Decrement register and skip
Ju mp on Carry = 1
Jump on Carry = 0
Ju mp on A Zero
Jump on A not Zero
Jump on TO = 1
Jump on TO = 0
Jump on Tl = 1
Jump on T1 = 0
Jump on FO = 1
Jump
Jump
Jump
Jump
on
on
on
on
Fl = 1
timer flag
INT = 0
Accumulator Bit
C
C
FO
FO
Fl
Fl
MOV A, R
MOV A,@R
MOV A, #data
MOV R,A
MOV@R,A
MOV R, #data
~
> MOV @R, #data
0
:;; Move A, PSW
~ MOV PSW, A
XCH A, R
XCHA,@R
Decrement A
I nput port to A
Output A to port
And immediate to port
Or immed iate to port
Input BUS to A
Output A to BUS
And immediate to BUS
Or immed iate to BUS
Input Expander port to A
Output A to Expander port
And A to Expander port
Or A to Expa nder port
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Description
CALL
RET
RETR
CLR
CPL
CLR
u. CPL
CLR
CPL
And register to A
Exclusive Or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Mnemonic
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Bytes'
Jump to subroutine
2
2
2
2
2
2
1
1
2
2
2
2
Return
Return and restore status
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear Flag 1
Complement Flag 1
Move register to A
Move Jata memory to A
Move immediate to A
Move
Move
Move
Move
Move
A to register
A to data memory
immediate to register
immediate to data memory
PSW to A
Move A to PSW
Exchange A a nd register
Exchange A and data memory
XCHD A,@R
MOVX A,@R
MOVX@R,A
MOVPA,@A
MOVP3 A,@A
Exchange nibble of A and register
Move external data memory to A
Move A to externa I data memory
Move to A from cu rrent page
Move to A from Page 3
MOV A, T
MOVT, A
STRTT
STRT CNT
STOP TCNT
EN TCNT!
DIS TCNTI
Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer ICounter
Enable Timer/Counter Interrupt
Disable Timer/Counter Interrupt
EN I
DIS I
SEL RBO
SEL RBl
SEL MBO
SEL MBl
ENTO CLK
Enable external interrupt
Disable external interrupt
Select register bank 0
Select register bank 1
NOP
No Operation
Select memory ba n k 0
Select memory ban k 1
Enable Clock output Of'l TO
Mnemonics copyright Intel Corporation 1976, 1977, 1978
8-33
Cyel ••
1
2
2
2
2
8049/8039/8039·6
Storage Temperature ............... -65°C to +150° C
Voltage on Any Pin With
RespecttoGround ...................... -O.5Vto+7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 Watt
'COMMENT: Stresses above th'ose.listiJd dl1<;flit.tA,bsolute
Maximum Ratings" may cause permanent.darrr8,{fe.:t,ptf1e
device, This is a stress rating only f!n,di.funofipnfll;\:
operation of the device at these or any othe, condlti6h"lii,'
above those indicated in the operational sections. of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA = O°Cto 70°C, Vcc = Voo = +5V ±10%, Vss = OV
ABSOLUTE MAXIMUM RATINGS·
AmbientTemperature Under Bias
........ O°C to 70°C
Limits
Symbol
Min.
Parameter
Typ.
Max.
Unit
-0.5
0.8
V
Input High Voltage
(All Except XTAL1, XTAL2, RESET)
2.0
VCC
V
VIHl
Input High Voltage (RESET, Xl, X2)
3.8
Vcc
V
VOL
Output Low Voltage
(BUS, RD, WR, PSEN, ALE)
0.45
V
IOL = 2.0mA
VOLl
Output Low Voltage
(All Other Outputs Except PROG)
0.45
V
IOL = 1.6mA
VO L2
Output Low Voltage (PROG)
0.45
V
IOL = 1.0mA
VO H
Output High Voltage
(BUS, RD, WR, PSEN, ALE)
2.4
V
IOH = -100J..!A
VOHl
Output High Voltage
(All Other Outputs)
2.4
V
IOH =-50J..!A
IlL
Input Leakage Current
(Tl, INT)
IOL
Output Leakage Current (Bus, TO)
(High Impedance State)
100
Power Down Supply Current
VIL
Input Low Voltage
VIH
±10
loo+lcc Tota I Su pply Current
A.C. CHARACTERISTICS
Symbol
J..!A
Test Conditions
VSS~VIN~VCC
±10
J..!A
VSS + 0.45 ~ VIN ~ Vc c
25
50
mA
TA = 25°C
100
170
mA
TA = 25°C
TA = o°c to 70°C, VCC = VOO = +5V ±10%, Vss = OV
Parameter
tLL.
ALE Pulse Width
tAL
tLA
Icc
tow
two
Data Hold After WR
tCY
Cycle Time
tOR
Data Hold
t RO
PSEN, RD to Data In
tAW
Address Setup to WR
tAD
Address Setup to Data In
t AFC
Address Float to RD, PSEN
8049/8039
(Note 1)
Min.
Max.
8039·6
Min.
Max.
Unit
Conditions (Note 2)
150
400
Address Setup to ALE
70
150
ns
Address Hold from ALE
50
80
ns
Control Pulse Width (PSEN, RD, WR)
300
700
ns
Data Set·Up Before WR
250
500
ns
40
120
ns
C L =20pF
I's
l1MHz XTAL
(6MHz XTAL for ·6)
1.36
0
15.0
2.5
100
0
200
400
-10
2. Control Outputs: C L = 80pF
BUS Outputs:
C L = 150pF
8·34
15.0
200
ns
500
ns
950
ns
2~0
200
Noles: 1. 8039-6 specifications are also valid for 8049/8039 operating a16MHz.
ns
0
ns
ns
80491803918039·6
WAVEFORMS
INSTRUCTION FETCH FROM EXTERNAL PROGRAM MEMORY
-tcY-----1
-tLL---1
1_-"
ALE
J
IL..-_ _----II--I---'L
- tAFCI---tcc--1
----------+--+--~
~-------------
PSEN
BUS
INSTRUCTION
READ FROM EXTERNAL DATA MEMORY
ALE
J
L
r--tcc--l
RD
--------~I
I~--------
'ml r"o"'NG~l ~""
BUS
FLOATING~
I
..
tAD
--F-LO-A-T-I-N-G---
l.tRD-1
II'
WRITE TO EXTERNAL DATA MEMORY
ALE
J
L
BUS
FLOATING
8-35
Inter
8243
MCS-48™ INPUT/OUTPUT EXPANDER
Low Cost
• Simple
Interface to MCS-4S™ Micro• computers
Four 4-Bit I/O Ports
• AND
• and OR Directly to Ports
24-Pin DIP
• Single
5V Supply
• High Output
Drive
• Direct Extension
of Resident S048 I/O
• Ports
The Intel@> 8243 is an input/output expander designed specifically to provide a low cost means of I/O expansion for the
MCS-48'· family of single chip microcomputers. Fabricated in 5 volts NMOS, the 8243 combines low cost, single supply
voltage and high drive current capability.
The 8243 consists of four 4-bit bidirectional static I/O ports and one 4-bit port which serves as an interface to the MCS-48
microcomputers. The 4-bit interface requires that only 4 I/O lines of the 8048 be used for I/O expansion, and also allows
multiple 8243's to be added to the same bus.
The I/O ports of the 8243 serve as a direct extension of the resident I/O facilities of the MCS-48 microcomputers and are
accessed by their own MOV, ANL, and ORL instructions.
BLOCK DIAGRAM
PIN CONFIGURATION
PORT 4
P50
vee
P,JAR~6'~~TIC
UNIT
(ALUI
STACK
MULTIPLEXER
~
,-
It
POW
SU PPLIES
It
1
,I
(8!
I FL ~pl:~PS I'-
1j
H
SCRATCH
PAD
'"
'"
IS'
'"
'"
'"
8008/8008·1
PIN DESCRIPTION
INTERRUPT
READY
<.',
"2
DATA
BUS
10
Figure 1. Pin Configuration
00.0 7
SYNC
BI-DIRECTIONAL DATA BUS. All address and
data communication between the processor and the
program memory, data memory, and I/O devices
occurs on these 8 lines. Cycle control information
is also available.
SYNC output. Synchronization signal generated by
the processor. It indicates the beginning of a machine cycle.
¢1'¢2
Two phase clock inputs.
INT
SO,S"S2
MACHINE STATE OUTPUTS. The processor controls the use of the data bus and determines whether
it will be sending or receiving data. State signals
SO, S" and S2, along with SYNC inform the peripheral circuitry of the state of the processor.
INTERRUPT input. A logic "1" level at this input
causes the processor to enter the I NTE R RUPT
mode.
READY
READY input. This command line is used to synchronize the 8008 to the memory cycle allowing
any speed memory to be used.
VCC +5V ±5%
Voo -9V ±5%
9-6
8008/8008·1
INSTRUCTION SET
Data and Instruction Formats
Data in the 800S is stored in the form of 8-bit binary integers. All data transfers to the system data bus will be
in the same format.
I
0 7 0 6 05 0 4 0 3 O 2 0, DO
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particlilar operation
executed.
One Bvte
TYPICAL INSTRUCTIONS
'n~IIUClIon,
I
°7 06 05 0 .. D3 02 0, DO
I
Re9'~H!f I() '1!9'~It:f. memory ''''''f~''C!'.
OP CODE
110 "",hmel,e 01 109,eoll, lataH! O'
,elu.n ,n$'ruct,ons
Two Bvte InSlIvetlons
Imrnl'O,ale Vlode
'''~I'lJC110''S
Tn,ee Bvte InS1IuChOnS
JUMP Of CALL
MNEMONIC
(1IMOV '1,'2
,.t'MOV r, M
MOV M,'
(3IMVI,
MVIM
INA r
OCR r
MINIMUM
STATES
REOUIRED
151
181
171
181
191
151
151
"HI'uClI0"~
INSTRUCTION CODE
~D6
05 04 03
D D D
0 0
5
0
8
0
8
0
0
5
5
0
5
0
8
0
8
0
0
DESCRIPTION OF OPERATION
0 2 0, DO
,,
,,
,,,
,, ,,,
,,
,,, ,,
0 0 0
8 8 8
8
8 8 8
0 0 0
0 0 0
8
0
0
S
0
8 8
0
8 8
0 0
0
5
,
Load Inde)( register r1 wIth the content of Index regIster '2.
Load mdex register I with the content of memory regIster M.
Load memory register M with the content of Index register r.
Load mdex register r with data B . . . 8.
Load memory register M with data B .
.8.
Increment the content of Index register r Ir I AI.
Decrement the content of mdex register r Ir I AI.
Accumulator Group Instructions
The rpslIl, of the ALU instructions affect all of the flag flip.flops. The ro'a'e instruclions affect only ,he carry flip-flop.
ADOr
ADD M
ADI
151
181
181
ADCr
151
ADC M
ACI
IBI
IBI
SUB r
SUB M
SUI
see r
SBB M
5BI
151
181
181
(51
181
181
,
,
0
0
0 0
8 8
0
0
0 0
8 8
0
0
0 0
8 8
0
0
0 0
8 8
,
,
,
,
,
,
0
0
0
0 0
0 0
0 0
B 8 8
0
0
0 0
0 0
8 8 B
0
0
0
0
0
0
8 8 8
,,,
5
,
5
5
0 0
,
, ,,,
8
5
, ,
0
0
0
B 8
5 5
0 0
8 8
,
,
,,,
, ,
,, ,,
,, ,
, ,
flip·flop.
Add the content of Ind'x register r, memory register M, or data
8 ... B from the accumulator with carry. An overflow (carry)
sets the carry fllp-Ilop.
8
S S
5
0
8 8
0
8
sets the carry flip-flop.
5
5
S
Subtract the content of Index register r, memory register M. or data
data B ... B from the accumulator with borrow. An underflow
8
0 0
8 8
1
B 8 8
Add the content 01 Index register r, memory register M, or data
B ... B to the accumulatOr. An overflow (carry) sets the carry
Subtract the content of Index register r. memory register M, or
data B .. . B from the accumulator. An underflow (borrow)
(borrow) sets the carry flip-flop.
9·7
8008/8008·1
INSTRUCTION CODE
MINIMUM
MNEMONIC
07 06
Os 0 4 0 3
151
181
181
a
a
a a
1
1
1
151
8
1
1
STATES
!7 D1 ~
DESCRIPTION OF OPERATION
REOUIRED
ANAr
ANAM
ANI
XAA r
XAA M
181
181
XAI
ORAr
151
181
181
OAA M
OAI
CMP r
CMPM
151
181
181
CPI
ALC
151
151
151
151
AAC
AAL
AAA
1
1
a a
a a
a a
8
8
B 8
1 a
1 a
1 a
B 8
1 1
1 1
1 1
B 8
1 1
1 1
1 1
B B
a
a
a
a
a
a
a
a
a a
a a 1
a 1 a
a 1 1
B
a
a
a a
8 8
1 a
1 a
0
a
8
8
a
a
a a
1
1
8
1
1
1
8
0
a
a
8
1
1
1
B
0
S S S
1 1 1
1 a a
B 8
Compute Ihl' loq!(,cli AND of the content of Index regIster r,
mt!rnory reglSIf'r M, or dald B .
B with the accumulator
8
S S 5
Compute the EXCLUSIVE OR of the content of index register
1
1
r. memory regIster M, or data B .
1 1
B with tht accumulator.
a a
8 8 8
S S S
1 1 1
1 a a
B 8 8
Compute the INCLUSIVE OR of the content of lOde)! regIster
r, memory regIster m, or data B
. B wIth the accumulator.
S S S
1 1 1
1 a a
B 8 8
Compare the content of index register r. memory register M.
a
a
a
a
Rotate
Rotate
Rotate
Rotate
1
1
1
1
a
a
a
a
or data B ... B wIth the accumulator. The content of the
accumulator IS unchanged.
the
the
the
the
content
content
content
content
of
of
of
of
the
the
the
the
accumulator
accumulator
accumulator
accumulator
left.
right.
left through the carry.
right through the carry.
Program Counter and Stack Control Instructions
141 JMP
1111
151 JNC, JNZ,
JP, JPO
190r 111
a
1
82 B2
X X
x X X
8262 B2
83 6 3 8 3
a
a
1
82 B2
X X
190r 111
JC,JZ
JM, JPE
1111
CALL
0
1
62 B2
X X
a
1
B:1
eNe, CNZ,
CP, cpO
19 or 111
ce, ez,
19 or 111
C4
B2
83
C3
82
83
C4 C3
B2
8 3 83
X X
B:1
B2
X X
B2 82 82
B3 B3 B3
a
82
X X
a C4
B2 B2
B3 63
1 C4
62 B2
83B3
1
B:1
B2
X X
eM, CPE
B2
83
1
B2
83
X
0
1
B:1
C3
B2
B3
C3
62
B3
1 a a UncondItionallY Jump to memory address 83 ... BJB2 ... 82.
B2 B2 B
B3 B3 83
a a a
B2 82 B
B3 63 B
a a a
B2
B3
1
B2
B3
B2
83
1
62
B3
1
Jump to memory address 83 ... 8382 .. . 82 if the condItion
flip~flop is false, Otherwise, execute the next in":1 \letion In sequence.
Jump to memory address 83 ... 8382 . .. 82
If t~,e
col"dition
B2 flip-flop is true. Otherwise, execute the next instructiLn in sequence.
83
a
Unconditionally call the subroutine at memory address 83 ...
B2 8382 ... 82. Save the current address (up one level in the stack).
83
0
a Call the subroutme at memory address 83 ... 8362 . " . 82 if the
B2 B2 82 condition flip-flop is false, and save the current address (up one
83 83 83 level 10 the stack J Otherwise. execute the next instruction in sequence.
0 1 a Call the subroutine at memory address B3 ... B3B2 ' .. 82 If the
82 B2 B2 condition flip·flop is true. and save the current address (up one
B3 B3 B3 level In the stack). Otherwise, execute the next instruction in sequence.
1
1
1
Unconditionally return (down one level in the stack).
13 or 51
a a
a a
X X X
RNC, ANZ,
RP, RPO
a
C4 C3
a
1
1
Return (down one level In the stack) If the condition flip.flop is
AC,RZ
RM, RPE
13 or 51
a
1 C4 C3
a
1
1
Return (down one level
151
RET
false. OtherWise, execute the next Instruction in sequence.
0
10
the stack) if the condition flip.flop is
true. OtherWise, execute the next instructIOn tn sequence.
AST
151
a a
A A A
1
a
1
Call the subroutine at memory address AAAOOO (up one level in the stackL
InputlOutput Instructions
IN
181
a
1
a a
M
M M 1
OUT
161
a
1
A A M
M M 1
a a
o
a a
1
1
0
0
X
1
1
Read the content of the selected Input port (MMMI into the
accumulator.
Wnte the content of the accumulator toto the selected output
por' IAAMMM, AA 1001
Enter the STOPPED state ard remain there until Interrupted.
NOTES
SSS:o Source Inde.x Register
} These registers, rt• are deSignated Alaccumulator-OOOI,
DOD
Destination Index Reg",er
B1001l, C10101, 010111, Ell001, Hll0ll, Llll01.
(2)
Memory registers are addressed by the contents of regISters H &. L.
(3)
Additional bvtes of instruction are designated by BBBBSSBS.
(41
X" "Don't Care".
(5)
Flag flip.flops are defined by C4C3 carry (OO·overflow or underflow), zero IOl·result IS zero), sign (10-MSB of result
parety (11-parity IS even).
(1)
0
9-8
IS
"1"),
8008/8008·1
ABSOLUTE MAXIMUM RATINGS·
AmUlelll I emperalurt::
'COMMENT
O°C to +lO°C
Under Bias
Storage Temperature
Stresses above those listed under" Absolute Max·
-55°C to +150°C
Input Voltages and Supply
Voltage With Respect
to Vee
+0.5 to -20V
Powpr Oissipation
1.0 W @l 25°C
imum Ratings" may cause permanent damage to
the device. This is a stress rating only and func·
tional operation of the device at these or any other
condition above those indicated in the operational
sections of this specification is not implied.
D.C. AND OPERATING CHARACTERISTICS
TA = o'e to lo'e, Vee = + 5V ± 5%, Voo= - 9V ± 5% unless otherwise specified. Logic "1" is defined
as the more positive level (VIH, VOH). "0" is defined as the more negative level (VIL, YoU.
SYMBOL
PARAMETER
MIN.
LIMITS
TYP.
MAX.
30
60
rnA
TA = 25°C
10
~A
V,N = OV
UNIT
100
AVERAGE SUPPLY CURRENTOUTPUTS LOADED'
III
INPUT LEAKAGE CURRENT
V'L
INPUT LOW VOLTAGE
(INCLUDING CLOCK,»)
Voo
Vce -4.2
V
V,H
INPUT HIGH VOLTAGE
(INCLUDING CLOCKS)
Vee-1.5
Vee +0.3
V
VOL
OUTPUT LOW VOLTAGE
VOH
OUTPUT HIGH VOLTAGE
0.4
Vee- l .S
TEST
CONDITIONS
* Measurements are made while
V
10L = 0.44mA
CL = 200 pF
V
10H = 0.2mA
the 800S is executing a typical
sequence of instructions. The
test load is selected such that
at VOL = OAV. I OL= O.44mA
on each output.
A.C. CHARACTERISTICS
T A =O·C to 70 ·C; Vee = + 5V ± 5%, VDO = - 9V ± 5%. All measurements are referenced to 1.5V levels.
8008
SYMBOL
8008-1
LIMITS
PARAMETER
MIN.
MAX.
2
LIMITS
MIN.
tCY
CLOCK PERIOD
t A.t F
CLOCK RISE AND FALL TIMES
t¢l
PULSE WIDTH OF ¢,
.70
.35
t¢2
PULSE IJI/IDTH OF ¢2
.55
.35
tOl
CLOCK DELAY FROM FALLING
EDGE OF ¢, TO FALLING EDGE
OF ¢2
.90
t02
CLOCK DELAY FROM ¢2 TO ¢,
.40
.35
.20
.20
3
1.25
50
MAX.
3
Jl.S
50
ns
TEST CONDITIONS
tA.t F = 50ns
Jl.S
I1S
1.1
1.1
UNIT
I1S
I1S
t03
CLOCK DELAY FROM ¢1 TO ¢2
too
DATA OUT DELAY
tOH
HOLD TIME FOR DATA BUS OUT
.10
tlH
HOLD TIME FOR DATA IN
111
tso
SYNC OUT DELAY
.70
.70
/.IS
C L = 100pF
tS1
STATE OUT DELAY (ALL STATES
EXCEPT T 1 AND T11) 121
1.1
1.1
/.IS
C L- 1QOpF
tS2
STATE OUT DELAY (STATES
T1 AND T11)
1.0
1.0
/.IS
C L= 100pF
tRW
PULSE WIDTH OF READY DURING
1.0
Jl.S
1.0
.10
111
I1S
/.IS
.35
.35
/.IS
.20
.20
/.IS
¢22 TO ENTER T3 STATE
tRO
READY DELAY TO ENTER WAIT
STATE
l211t the INTERRUPT is not used, all
stafP~ h;lVe the same outnut delay, t S1 '
9-9
C L =100pF
I1S
8008/8008-1
TIMING DIAGRAM
____
-.-tcy~
i-- to,
,..-.:;
"'11
~
-+
t(Jl
I-
Q-
~
- -
"
P
I-
t02
DATA
BUS
LINES
10, . . Dol
P
R
\
I
_to,~fo-tso_1
____--:1.J
i ------ -----------J
-----------~
I
,.-~,-
_1
-------- ~~IADDRESS OUT
_~--.-tDD~~!
(l21
°22
~:-o }:tIH~1
---
1.
--~
DATA IN
----- ..I
DATA OUT
~tDD~~---------
"_
5,
1---
~-----...;~
So
STATE
LINES
121
0"
...... tso ___ 1
I
t02
SYNC
If"":'\
6t2
r-------
---
~--_.I
tOH ..--
_tS2_
i--- t S l -
~
~
52
f-!t RW
-
~
1'1
-
----~
.
1
T,
Notes:
1-'----
t--
tRD
I
..
T2
I
T,
T,
-----1
1. READY line must be at "0" prior to <1>22 of T2 to guarantee entry into the WAIT state.
2. INTERRUPT line must not change levels within 200ns (max.! of falling edge of <1>1.
TYPICAL D.C. CHARACTERISTICS
POWER SUPPLY CURRENT
OUTPUT SINKING CURRENT
VS. TEMPERATURE
VS. TEMPERATURE
·
·
---- ~
I--
~c- ...
•
' '\1
~
~~-:-;n\l
00
on
,
'v'~
'-9V
Vee'S"
'.
<
-
1O"C
,
.~
.......
.........
·
,
10
VS. OUTPUT VOLTAGE
,
,
0
OUTPUT SOURCE CURRENT
,
2
,
.
--
~-VOD ·14\1
.,'+:-
I--
.
"'-
,
,
2
,
1
0
2
I'-..
"" "
.
OUTPUT VOLTAO£ 11,11. VON
I'\.
"
TYPICAL A.C. CHARACTERISTICS
DATA OUT DELAY VS.
OUTPUT LOAD CAPACITANCE
0
·
·,
,/
CAPACITANCE f
V
SYMBOL
/
·
"
L
"
".
'"
'"
DATA IUSU'ACITAt4CE IpF) C P1
'"
= 1MHz; TA = 25°C; Unmeasured Pins Grounded
TEST
LIMIT IpF)
TYP.
MAX.
CON
INPUT CAPACITANCE
5
10
COB
OATA BUS 1/0 CAPACITANCE
5
10
COUT
OUTPUT CAPACITANCE
5
10
..
9·10
8080Al8080A·1/8080A·2
8·BIT N·CHANNEL MICROPROCESSOR
The 8080A is functionally and electrically compatible with the Intef® 8080.
• TTL Drive Capability
• 2 JJs ( - 1:1.3 JJs, - 2:1.5 JJs) Instruction
Cycle
• 16·Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
Switching of the Program Environment
• Powerful Problem Solving Instruction
Set
• Decimal, Binary, and Double Precision
Arithmetic
• 6 General Purpose Registers and an
Accumulator
• Ability to Provide Priority Vectored
Interrupts
• 16·Bit Program Counter for Directly
Addressing up to 64K Bytes of
Memory
• 512 Directly Addressed 1/0 Ports
The Intel® 8080A is a complete 8·bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using
Intel's n·channel silicon gate MOS process. This offers the user a high performance solution to control and processing
appl ications.
The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose registers
may be addressed individually or in pairs providing both Single and double precision operators. Arithmetic and logical
instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic operation.
The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out stack to
store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general purpose registers. The
16-bit stack pointer controls the addressing of this external stack. This stack gives the 8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited
subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bidirectional
data busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O
are provided directly by the 8080A. Ultimate control of the address and data busses resides with the HOLD Signal. It
provides the ability to suspend processor operation and force the address and data busses into a high impedance
state. This permits OR-tying these busses with other controlling devices for (DMA) direct memory access or multiprocessor operation.
8080A CPU FUNCTIONAL BLOCK DIAG.RAM
°
7 .00
81DIRECTIONAL
DATA BUS
D
DATA BUS ~
BUFFE[iLATCH
BIT I
(8
{8 BIT!
INTERNAL DATA BUS
INTERNAL DATA BUS
It
IACCUMULAT~~ I I
lL
I
TEMP REG
II
lSI
l
ACCUMUlATO~1
(s:
FLlp·FLOPS
FLAG
r-- -
~ ---""JARITHMETIC
r-
POWER
1_
.,2V
+5V
_-5V
_GND
DECODER
AND
UNIT
(AlU)
181_
=-
DECIMAL
ADJUST
su PPLIES
INSTRUCTION
LOGIC
I +t
MACHINE
CYCLE
ENCODING
DATA BUS INTERRUPT
WAITE CONTROL
l
I
ORIN
...
HOLD
~
-
TIMING
AND
CONTROL
f5
t;
~
a:
-
~
I
I
I,
t
JJ
~t
LATCH 18!
1
INSTRUCTION
REGISTER (811
f-
CONTAOl CONTROL CONTROL SYNC CLOCKS
1sL ), 12
9-11
w
J
lSI
lSI
B
RESET
-
C
IS\
R~G.
REG.
D
REG.
H
(8)
Z
TEMP REG.
TEMP REG.
181
E
181
REG.
181
L
REG.
181
REG.
STACK POINTER
PROGRAM COUNTER
1161
(161
INCREMENTER/OECREMENTER
ADDRESS LATCH
(l6)
~1
1161
ADDRESS BUFFER
WAIT
I L INt HL HLwL
ACK
READY
I MULTIPLEXER
"'~
.
.."
ADDRESS BUS
r- REGISTER
ARRAY
8080Al8080A·1/8080A·2
PIN DESCRIPTION
The following describes the function of all of the aOaOA I/O pins.
Several of the descriptions refer to internal timing periods.
RESET
HOLD
INT
12
29
A"
A'4
A'3
A,z
A,s
Ag
As
A7
A6
As
A4
A3
13
28
+12V
14
27
¢z
15
26
16
25
40
2
39
3
38
A'S.Ao (output three·state)
ADDRESS BUS; the address bus provides the address to memory
(up to 64K 8-bit words) or denotes the I/O device number for up
to 256 input and 256 output devices. Ao is the least significant
address bit.
4
5
37
6
7
35
DrDo (input/output three·state)
8
DATA BUS; the data bus provides bi-directional communication
between the CPU, memory, and I/O devices for instructions and
data transfers. Also, during the first clock cycle of each machine
cycle, the aOaOA outputs a status word on the data bus that describes the current machine cycle. Do is the least significant bit.
SYNC (output)
SYNCHRONIZ!NG SIGNAL; the SYNC pin provides a signal to
indicate the beginning of each machine cycle.
DBIN (output)
DATA BUS I N; the DBI N signal indicates to external circuits that
the data bus is in the input mode. This signal should be used to
enable the gati ng of data onto the aOaOA data bus from memory
or I/O.
READY (input)
READY; the READY signal indicates to the aOaOA that valid
memory or input data is available on the aOaOA data bus. This
signal is used to synchronize the CPU with slower memory or I/O
devices. If after sending an address out the aOaOA does not receive a READY input, the aOaOA will enter a WAIT state for as
long as the READY line is low. READY can also be used to single
step the CPU.
WAIT (output)
WAIT; the WAIT signal acknowledges that the CPU is in a WAIT
state.
WR (output)
WRITE; the WR signal is used for memory WRITE or I/O output
control. The data on the data bus is stable while the WR signal is
active low (WR ; 0).
HOLD (input)
HO LD; the HO LD signal requests the CPU to enter the HO LD
state. The HO LD state allows an external device to gain control
of the aOaOA address and data bus as soon as the aOaOA has completed its use of these buses for the current machine cycle. It is
recognized under the following conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READY signal is active.
As a result of entering the HOLD state the CPU ADDRESS BUS
(A ,5 -A o ) and DATA BUS (DrDo) will be in their high impedance
state. The CPU acknowledges its state with the HO LD ACKNOWLEDGE (HLDA) pin.
HLDA (output)
HOLD ACKNOWLEDGE; the HLDA signal appears in response
to the HOLD signal and indicates that the data and address bus
9·12
9
10
11
36
INTE~
8080A
o
o
34
33
o
32
31
30
o
17
24
WR
SYNC
18
23
Az
A,
Ao
WAIT
READY
19
22
¢,
+5V
20
21
HLDA
INTE 0
Figure 1. Pin Configuration
will go to the high impedance state. The HLDA signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WR ITE memory or OUTPUT operation.
In either case, the H LDA signal appears after the rising edge of
u
1.0
~
iii
0.5
NOTES:
1. The RESET signal must be active for a minimum of 3 clock cycles.
2. When DBIN is high and VIN > VIH an internal active pull up will
be switched onto the Data Bus.
3. Jl.I supply I Jl. T A = -0.45%f c.
0
+25
+50
AMBIENT TEMPERATURE (OC)
Figure 2. Typical Supply Current vs.
Temperature, Normalized[J]
Figure 3. Data Bus Characteristic
During DBIN
9-13
+75
8080Al8080A·1/8080A·2
A.C. CHARACTERISTICS (8080A)
TA ~ o°c to 70°C. VOO = +12V
± 5%. VCC = +5V ± 5%. V BB ~ -5V ± 5%. VSS = OV. Unless Otherwise Noted
Parameter
Symbol
·2
·2
Max.
·1
Min.
·1
Min.
Max.
Min.
Max.
Unit
0.48
2.0
0.32
2.0
0.38
2.0
~sec
50
0
25
0
50
tCy[3J
Clock Period
tr,lf
Clock Rise and Fall Time
0
t",l
"'1 Pulse Widlh
60
50
60
nsec
t",2
"'2 Pulse Widlh
220
145
175
nsec
tOl
Delay "'1 to "'2
0
0
0
nsec
t02
Delay "'2 10 "'1
70
60
70
nsec
103
Delay "'1 10 "'2 Leading Edges
80
60
70
IOA[2]
Address Oulput Delay From "'2
200
150
175
nsec
tOO[2J
Oala Oulpul Delay From "'2
220
180
200
nsec
lod2J
Signal Oulput Delay From "'2 or"'2 (SYNC, WR, WAIT, HLOA)
120
nsec
tOF[2J
OBIN Delay From "'2
140
nsec
tOI[lJ
Delay for Inpul Bus 10 Enler Input Mode
tOSl
Oala Selup Time During "'1 and OBIN
120
25
WAVEFORMS
110
25
140
10F
130
25
10F
10
30
Test Condition
nsec
nsec
10F
20
}
CL=100 pF
}
CL=50 pF
nsec
nsec
(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 8.0V
"0" = 1.0V; INPUTS "1" = 3.3V. "0" = 0.8V; OUTPUTS "1" = 2.0V. "0" = 0.8V.)
i:'1
_______
..J~JF'Cy
~
r
'I
-t01-
~~--~r~-r--~/\~__~/\~____
------.
..--t¢2----:J
~
I
--t 03 ....1
-- I
-~I'...LL-~--+---~--+-- -~--++----+--~-I
A'S"AO ----------+-.....I·~I-----'oA~1
-too-I
0,.0
0
+_J7I
oalN
;,1
-
-l-_.__~.I-_---
__________
SYNC _ _ _ _ _ _ _ _ _ _
f--I
I
1
---- to: 1-
tOI
1--
---
tAW·
--I'
'I
---t oo -
-4
Ji
-~~-+-+-*--~~
--~::: -:'g~t-'~
--- to 51 1-
~ ~___
f-'ow ~
_
DA~A_O~T
-I
-'DS2~
-\.-
--- toe 1---l-i""----+-""\!'
---------------------+~-'o-FJ~II
_'oF-l.I~---l------+~-+-+~----l+-~
1
- ,j~
READY
WAIT
-----------------------------'H-~-,-'-O--c--+....11-
-;:,f~~I-:1
_ ':_1 J'-
HOlD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I~*I~-~~
-I ~H;P2
HLDA
- --.rc.""'U'"
,1~t
INT
tH _ _ __
INTE
9-14
SOSOA/SOS(}A·1/S0S0A·2
A.C. CHARACTERISTICS (SOSOA)
TA = oDe to 7o o e, VDD = +12V ± 5%, Vee = +5V ± 5%, V BB = -5V ± 5%, Vss = OV, Unless Otherwise Noted
Parameter
Symbol
Min.
Max.
·1
·1
·2
·2
Min.
Max.
Min.
Max.
120
Unit
150
tDH[1J
Data Holt time From "'2 During DBIN
[1J
tIE[2J
INTE Output Delay From "'2
130
tRS
READY Setup Time During "'2
120
90
90
nsec
tHS
HOLD Setup Time to "'2
140
120
120
nsec
tiS
INT Setup Time During "'2
120
100
100
tH
Hold Time From "'2 (READY, INT, HOLD)
0
0
0
tFO
Delay to Float During Hold (Address and Data Bus)
tAW[2J
Address Stable Prior to WR
tDW[2J
tWD[2J
[1J
200
120
nsec
[1J
200
200
Test Condition
nsec
Data Setup Time to "'2 During DBIN
tDS2
CL = 50 pF
nsec
nsec
- f-nsec
120
120
nsec
-
nsec
[5J
[5J
[5J
Output Data Stable Prior to WR
[6J
[6J
[6J
nsec.
Output Data Stable From WR
[7J
[7J
[7J
nsec
tWA[2J
Address Stable From WR
[7J
[7J
[7J
nsec
tHF[2J
HLDA to Float Delay
[8J
[8J
[8J
nsec
tWF[2J
WR to Float Delay
tAH[2J
Address Hold Time After DBIN During HLDA
[9J
[9J
[9J
nsec
-20
-20
-20
nsec
CL = 100 pF: Address, Data
CL = 50 pF: WR,HLDA,DBIN
1-
NOTES: (Parenthesis gives ·1, ·2 speCifications, respectively)
1. Data input should be enabled with D81N status. No bus conflict can then occur and data hold time is assured.
tDH '" 50 ns or tOF, whichever is less .
2. Load Circuit.
.,t\_ _
+5V
8080A
OUTPUT
I
, +',-f--.II
I-ti
:
SYNC
+--.---+-~
--
i.-
'wo
=
tD3 + trt2 + tt2 + tft2 + tD2 + trt1 ;. 480 ns (-1:320 ns, - 2:380 ns).
TYPICAL Ll. OUTPUT DELAY VS. Ll. CAPACITANCE
+20
c
I
1
>-
~
i
I I
081N
3. ICY
\
~
1_'"
~
>-
::>
i
r-f-1
f--
I
'DC
0
--
Jr-'wF+100
-" CAPACITANCE {pf)
i
-
I
WAIT
~
--
'DC
~
I
.NT
i
(CACTUAL - C SPEC )
F-
1
HlDA
INTE
-'0
<1
READY
HOLD
+'0
D
1-:1_-________
4. The following are relevant when interfacing the 8080A to devices having VIH = 3.3V:
a) Maximum output rise time from .8V to 3.3V = 1DOns @ CL == SPEC.
b) Output delay when measured to 3.0V =:: SPEC +60ns @ CL '" SPEC.
d If CL '* SPEC, add .6ns/pF if CL> CSPEC. subtract .3ns/pF (from modified delay> if CL < CSPEC.
5. tAW = 2 ICY - tD3 - trt2 -140 ns (-1:110 ns, -2:130 ns).
6. tDW = tCY - ID3 - Irt2 - 170 ns (-1:150 ns, - 2:170 ns).
7. If not HLDA. tWD= tWA"" t03 + tr1>2 +10ns. If HLOA. tWD '" twA = tWF·
8. tHF == tD3 + tr1>2 -50ns.
9. twF '" t03 + tr1>2 -10ns
10. Data in must be stable for this period during DBIN ·T3. Both tOS1 and tDS2 must be satisfied.
11. Ready signal must be stable for this period during T2 or TW' (Must be externally synchronized.)
12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and durIng T3. T 4. T5
and TWH when in hold mode. (External synchronization is not required.)
13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be
recognized on the following instruction. (External synchronization is not required.;
14. This timing diagram shows timing relationships only; it does not represent any specific machine cycle.
9·15
8080Al8080A·1/8080A·2
INSTRUCTION SET
The accumulator group instructions include arithmetic and
logical operators with direct, indirect, and immediate addressing modes.
increment and decrement memory, the six general registers
and the accumulator is provided as well as extended increment and decrement instructions to operate on the register
pairs and stack pointer. Further capability is provided by
the ability to rotate the accumulator l!lft or right through
or around the carry bit.
Move, load, and store instruction groups provide the ability
to move either 8 or 16 bits of data between memory, the
six working registers and the accumulator using direct, indirect, and immediate addressing modes.
Input and output may be accomplished using memory addresses as I/O ports or the directly addressed I/O provided
for in the 8080A instruction set.
The ability to branch to different portions of the program
is provided with jump, jump conditional, and computed
jumps. Also the ability to call to and return from subroutines is provided both conditionally and unconditionally.
The RESTART (or single byte call instruction) is useful for
interrupt vector operation.
The following special instruction group completes the 8080A
instruction set: the NOP instruction, HALT to stop processor execution and the DAA instructions provide decimal
arithmetic capability. STC allows the carry flag to be directly set, and the CMC instruction allows it to be complemented. CMA complements the contents of the accumulator
and XCHG exchanges the contents of two 16-bit register
pairs directly.
Double precision operators such as stack manipulation and
double add instructions extend both the arithmetic and
interrupt handling capability of the 8080A. The ability to
Data and I nstruction Formats
Data in the 8080A is stored in the form of 8-bit binary integers. All data transfers to the system data bus will be in the
same format.
ID7
D6 D5 D4 D3 D2 D1 Dol
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particular operation
executed.
One Byte Instructions
1
TYPICAL INSTRUCTIONS
Register to register, memory reference, arithmetic or logical, rotate,
return, push, pop, enable or disable
Interrupt instructions
D7 D6 D5 D4 0 3 D2 D0?QJ OP CODE
Two Byte Instructions
I D7
I D7
0 6 0 5 D4 D3 D2 0 1 DO
OP CODE
D6 D5 D4 D3 D2 D1 DO
OPERAND
Immediate mode or I/O instructions
OP CODE
Jump, call or direct load and store
instructions
Three Byte Instructions
107 D6 D5 D4 D3 D2 D1 Do
I D7
10
D6 D5 D4 D3 D2 D1 Do
7 D6 D5 D4 D3 D2 D1 Do
I LOW ADDRESSOR OPERAND 1
I HIGH ADDRESSOR OPERAND 2
For the 8080A a logic "1" is defined as a high level and a logic "0" is defined as a low level.
9-16
8080Al8080A·1/8080A·2
8080 INSTRUCTION SET
Summary of Processor Instructions
Mnemonic
Description
Instruction Codelll
Clockl2;
D/ D5 D5 D4 03 D1 01 Do Cycles Mnemonic
Instruction Codelll
Clockl21
D/ D5 D5 04 03 02 01 Do Cycles
Description
MOVE. LOAD. AND STORE
MOVrl.r2
Move ·reglster to register
MOV M.r
Move register to memory
MOV r.M
MVI r
Move Immediate register
JPO
PCHL
S
Move memory to register
MVI M
LXI B
Load Immediate register
Pair B & C
Load Immediate register
Pair 0 & E
Load Immediate reglstel
Pair H & L
Store A Indirect
Store A Indirect
Load A IOdllect
Load A Indirect
Store A direct
Load A direct
LXI H
STAX B
STAX 0
LDAX B
LDAX 0
STA
LOA
SHLD
LHLD
XCHG
to
to
CALL
10
CZ
CNZ
CP
CM
10
CC
eNC
CPE
CPO
13
13
Store H & L direct
Load H & L direct
Exchange 0 & E H & L
Registers
16
16
11
RESTART
RST
E on stack
SPHL
LXI SP
INX SP
DCX SP
JZ
JNZ
JP
JM
JPE
NOTES.
Restart
INR r
OCR r
INR M
Pop regrstel Pair 8 &
C off stack
Pop register Parr 0 &
E off stack
Pop register Pair H &
L off stack
Pop A and Flags
off stack
Exchange top of
stack H & L
H & L to stack pOinter
Load Immediate stack
pOinter
10
Jump
Jump
Jump
Jump
Jump
Jump
on
on
on
on
on
on
10
INX H
Illcrement 0 & E
registers
Increment H & L
18
DCX 8
DCX 0
DCX H
Decrement 8 & C
Decrement 0 & E
Decrement H & L
0
0
10
10
10
10
10
11
0
0
10
10
5
5
5
ADO
ADD r
ADC r
10
10
10
A A A
registers
ADD M
ADC M
no carry
zelo
no zero
positive
mIOUS
panty even
Increment 8 & C
registers
INX 0
Increment stack pOinter
Decrement stack
Jump unconditional
Jump on carry
Increment register
Decrement register
Increment memory
Decrement memory
10
10
5111
5111
5111
Return all panty odd
11
pOinter
JMP
no zelo
POSitive
mHlus
panty even
INCREMENT AND DECREMENT
to
5111
5111
5111
Return on zero
11
OCR M
INX 8
5111
5111
Return on cany
Push regrster Pall H &
L on stack
Push A and Flags
on stack
JUMP
JC
JNC
11117
10
Retur n on
Retul n on
Retur 11 on
Return on
Push register Pair 0 &
XTHL
11117
II! 17
11117
positive
minus
parity even
parity odd
RNZ
RP
RM
PUSH 0
POP PSW
Call on
Calion
Call all
Call on
Return on no carry
11
POP H
11117
11117
RNC
RZ
Push register Pair B &
C on stack
POP 0
Call on zero
Calion no zero
Return
PUSH B
POP B
t7
t 1117
111 t 7
RET
RC
RPE
RPO
PUSH PSW
Call unconditional
Callan carry
Calion no carry
RETURN
STACK OPS
PUSH H
10
5
CALL
Move immediate memory
LXI 0
Jump on parity odd
H & L to plogram
counter
ADI
ACI
DAD B
DAD 0
DAD H
DAD SP
Add register to A
Add register to A
With carry
Add memory to A
Add memory to A
With carry
Add Immediate to A
Add Immediate to A
With carry
Add B & C to H & L
Add 0 & E to H & L
Add H & L to H & L
Add stack pOinter to
H& L
DOD or SSS 8 000. COOl 0 010. E 011. H 100. L 101. Memory 110. A 111
Two possible cycle limes 16112) IOdlCate IOstructlon cycles dependent on condition flags
9-17
10
10
10
10
• All mnemoniCs copynght
e I ntel Corporation 1977
8080AJ8080A·1/8080A·2
Summary of Processor Instructions (Cont.)
Mnemonic
Description
Instruclion Codelll
Clockl21
07 06 05 04 03 02 0, DO Cycles
SUBTRACT
SUB r
SBB r
SUB M
SBB M
SUI
SBI
Subtract register
from A
Subtract register from
A with borrow
Subtract memory
from A
Subtracl memory from
A with borrow
Subtract immediate
from A
Subtract Immediate
from A with borrow
S S
And reg Isler with A
Exclusive Or reg Isler
Wllh A
Or reg 1St" with A
Compare register with A
And memory Wllh A
Exclusive Or memory
with A
Or memory with A
Compare memory with A
And Immediate with A
Exclusive Or Immediate
with A
Or Immediate with A
Compare Immediate
with A
S S
S S
S
S
lOGICAL
ANA r
XRA r
ORA I
CMPr
ANA M
XRA M
ORA M
CMP M
ANI
XRI
ORI
CPI
S
S
S
S
0
ROTATE
RLC
RRC
RAL
RAR
Rolate
Rotate
ROlale
carry
Rolale
carry
A left
A fight
A left through
A fight Ihrough
SPECIALS
CMA
STC
CMC
DAA
Complement A
Set carry
Complement carry
Decimal adJusl A
INPUT /OUTPUT
IN
OUT
Input
Oulput
10
10
CONTROL
EI
01
NOP
HLT
Enable Interrupts
Disable Interrupl
No-operallon
Halt
NOTES 1 DOD or SSS B=Ooo. C=OOI 0=010. E=OII. H=100. L=101. Memory=110 A=111
2. Two possible cycle times (6/12) indicate Instruclion cycles dependent on condition flags
9-18
• All mnemonics copYright
c
Intel Corporation 1977
inter
8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
Single Chip Clock Generator/Driver for
• 8080A
CPU
Oscillator Output for External System
• Timing
• Power-Up Reset for CPU
• Ready Synchronizing Flip-Flop
• Advanced Status Strobe
Controlled for Stable System
• Crystal
Operation
• Reduces System Package Count
The Intel@ 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected by the
designer to meet a variety of system speed requirements.
Also included are circuits to provide power·up reset, advance status strobe, and synchronization of ready.
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing for 8080A.
BLOCK DIAGRAM
PIN CONFIGURATION
RESET
Vee
RESIN
XTAl1
RDVIN
XTAL 2
READY
SYNC
.,ITTLI
STSTB
@>
XTALl
§>
XTAL2
1!1>
TANK
ose
.,
.,
TANK
lIt>
l!9
1!2>
.,ITTU[y
.,
OS<:
.,
[B>
SYNC
[D
RESIN
STSTB
II>
RESET
IT>
Voo
@>
RDVIN
PIN NAMES
XTAL 1
!
RESIN
RESET INPUT
RESET
RESET OUTPUT
XTAL2
RDYIN
READY
READY INPUT
READY OUTPUT
TANK
osc
ascI LLATOR OUTPUT
SYNC
SYNC INPUT
.,ITTL)
8224
ABSOLUTE MAXIMUM RATINGS*
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
relillbility.
Temperature Under Bias ............... O°C to 70°C
Storage Temperature .............. _65°C to 150°C
Supply Voltage, Vee ................ -0.5V to +7V
Supply Voltage, Voo .............. -0.5V to +13.5V
Input Voltage ..................... -1.5V to +7V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
D.C. CHARACTERISTICS
TA = O°C to 70°C; Vee = +5.0V ±5%; Voo = +12V ±5%.
Symbol
IF
IR
Ve
Parameter
Min.
Input Current Loading
Input Leakage Current
... Input ForwardClaITt-Voltage
V 1L
Input "Low" Voltage
V 1H
Input "High" Voltage
2.6
2.0
V1WV1L
RESIN Input Hysteresis
.25
VOL
Output "Low" Voltage
VOH
Limits
Typ.
Test Conditions
Max.
Units
-.25
mA
VF = .45V
VR = 5.25V
10
IJ.A
1.0
V
Ie = -5mA
.8
V
Vee = 5.0V
V
Reset Input
All Other Inputs
V
Vee = 5.0V
.45
V
(r/Jl,r/J2)' Ready, Reset, STSTB
.45
V
IOL =2.5mA
All Other Outputs
IOL = 15mA
V
V
V
IOH = -1001J.A
IOH = -1001J.A
IOH = -lmA
-60
mA
Vo =OV
Vee = 5.0V
Output "High" Voltage
r/J1
' r/J2
READY, RESET
All Other Outputs
9.4
3.6
2.4
Ise[ll
Output Short Circuit Current
(All Low Voltage Outputs Only)
-10
Icc
Power Supply Current
115
mA
100
Power Supply Current
12
mA
Note: 1. Caution, <1>1 and <1>2 output drivers do not have short circuit protection
Crystal Requirements
Tolerance: 0.005% at 0·C-70·C
Resonance: Series (Fundamental)'
Load Capacitance: 20-35 pF
Equivalent Resistance: 75-20 ohms
Power Dissipation (Min): 4 mW
'With tank circuit use 3rd overtone mode.
9-20
8224
A.C. CHARACTERISTICS
Vcc = +5.0V ± 5%; Voo = +12.0V ± 5%; TA = DoC to 70 D C
Symbol
Parameter
Limits
Typ.
Min.
~,
rfJ, Pulse Width
2tcy _ 20ns
t2
rfJ2 Pulse Width
5tcy _ 35ns
to,
rfJ, to rfJ2 Delay
0
t02
rfJ2 to rfJ, Delay
2tcy _ 14ns
t03
rfJ, to rfJ2 Delay
tR
rfJ, and rfJ2 Rise Time
tF
rfJ, and rfJ2 Fall Time
to2
rfJ2 to rfJ2 (TTL) Delay
toss
Max.
Test
Conditions
Units
9
9
ns
CL = 20pF to 50pF
9
2tcy
2tcy + 20ns
9
9
20
20
-5
+15
ns
rfJ2 to STSTB Delay
6tcy _ 30ns
6tcy
tpw
STSTB Pulse Width
tcy _ 15ns
tORS
RDYIN Setup Time to
Status Strobe
50ns _ 4tcy
tORH
RDYIN Hold Time
After STSTB
tOR
RDYIN or RESIN to
rfJ2 Delay
tCLK
ClK Period
f max
Maximum Oscillating
Frequency
27
MHz
Cin
Input Capacitance
8
pF
rfJ2TTl,Cl=30
R,=300n
R2=600n
9
9
STSTB, Cl=15pF
9
R, = 2K
R2 = 4K
9
4tcy
9
Ready & Reset
Cl=10pF
R,=2K
R2=4K
4tcy _ 25ns
9
tcy
9
Vcc=+5.0V
Voo=+12V
VSIAs=2.5V
f=l MHz
TEST
CIRCUIT
INPUT >---~----1
GNO
9·21
8224
WAVEFORMS
I---------------'cv------------_
.,
I-------~-----~
SYNC
(FROM 808OA)
I--·--------·oss-----------J.-·PW
I-------·OOH-----+I
RDYIN OR RESIN
"\ir---------""\ir - - - - - - - - -
- - - - - - - - - - - - - - - - - - -
-- - -- - --- - -- ------ - '\..\:------1--------------
READvour
RESET OUT
VOLTAGE MEASUREMENT POINTS: 4J1. 4J2 logic "0"
=
1.0V. logic "1" = a.ov. All other signals measured at 1.5V.
EXAMPLE:
A.C. CHARACTERISTICS (For tCY = 488.28 ns)
TA
=
O°C to 70°C; VOO
=
+5V ±5%; Voo
=
+12V ±5%.
Limits
Typ.
Units
Test Conditions
t4Jl
1/>1 Pulse Width
89
ns
tcy=488.28ns
t4J2
1/>2 Pulse Width
236
ns
ns
Symbol
Parameter
Min.
tOl
Delay 1/>1 to 1/>2
0
t02
Delay 1/>2 to 1/>1
95
109
Max.
_ 1/>1 & 1/>2 Loaded to
CL = 20 to 50pF
ns
129
ns
t03
Delay 1/>1 to 1/>2 Leading Edges
tr
Output Rise Time
20
ns
tl
Output Fall Time
20
ns
toss
1/>2 to STSTB Delay
296
326
ns
t04J2
tpw
1/>2 to 1/>2 (TTL) Delay
-5
+15
ns
Status Strobe Pulse Width
40
ns
tORS
RDYIN SetupTimetoSTSTB
-167
ns
tORH
RDYIN Hold Time after STSTB
217
ns
tOR
READY or RESET
to 1/>2 Delay
192
ns
fMAX
Oscillator Frequency
18.432
9-22
MHz
-
Ready & Reset Loaded
to 2mA/l0pF
All measurements
referenced to 1.5V
unless specified
otherwise.
inter
8801
CLOCK GENERATOR CRYSTAL
FOR 8224/8080A
• Specifically Selected for Intel® 8224
• 18.432 MHz for 1.95 lAS 8080A Cycle
• Simple Generation of all Standard
Communication Baud Rates
• Frequency Deviation ± 0.005%
• Fundamental Frequency Mode
• OOC to 70°C Operating Temperature
The Intel@ 8801 is a quartz crystal specifically selected to operate with the 8224 clock generator and the 8080A CPU. It
resonates in the fundamental frequency mode at 18.432 MHz. This frequency allows the 8080A at full speed (T Cy = 488
ns) to have a cycle of 1.95 IlS and also simplifies the generation of all standard communication baud rates. The 8801
crystal is exactly matched to the requirements of the 8080A/8224 and provides both high performance and system
flexibility for the microcomputer designer.
8801 INTERFACE
PACKAGING INFORMATION
8801
1-400~
~~1~~
I
I
-r
_J
.510
;8801
14
_1
11
12
OSC
10
0, (TTL)
3
RDYIN
-
Vee
~IJ-,
GND
T
8224
CLOCK
GENERATOR
1.500
RESIN
GND
1_. 192_1
STSTB (TO 8228 PI N 1)
9·23
8801
r-- -
APPLICATIONS
I
The selection of 18.432 MHz provides the 8080A with clocks
whose period is 488ns. This allows the 8080A to 9perate at
very close to its maximum specified speed (480 ns). The
8224. when used with the 8801. outputs a signal on its OSC
pin that is an approximately symetrical square wave at a
frequency of 18.432 MHz. This frequency signal can be
easily divided down to generate an accurate. stable baud
rate clock that can be connected directly to the transmitter
or receiver clocks of the 8251 USART. This feature allows
the designer to support most standard communication
interfaces with a minimum of extra hardware.
--.,
8801
Vl}
'.~2
TO HOSOA
(,'2(TTL)
8224
TO 8251
2.048 MHz
18.432 MHz
The chart below (Fig. 1) shows the equivalent baud rates
that are generated with the corresponding dividers.
BASIC DIVIDER
30
9600 BAUO
(64XI
I
OTHER
TRIM
DIVIDER
BAUD
RATES
Figure 1. Block Diagram
BAUD RATE
64x
BAUD RATE
16x
FREQUENCY
BASIC
DIVIDER
PLUS TRIM
DIVIDER
614.4 KH
730
-
4800
19.2K
307.2 KH
730
72
2400
9600
153.6 KH
730
74
1200
4800
76.8 KH
';·30
78
600
2400
38.4 KH
730
716
300
1200
19.2 KH
730
';'32
600
9.6 KH
';'30
';'64
300
4.8 KH
';'30
';'128
6.982 KH
';'30
';'88
9600
*109.1
*For 109.1 (64x) Baud rate divide 1200 8aud Frequency (76.8 KH) by 11.
Figure 2. Baud Rate Chart
ELECTRICAL CHARACTERISTICS
Recommended Drive Level ................
SmW
Type of Resonance . . . . . . . . . . . . . . . . . . . . .. Series
Equivalent Resistance .................. 200h'ms
Maximum Shunt Capacity
...... . . . . . . . . . .. 7pF
Maximum Frequency Deviation
0° - 70°C
..................
-SSo - 12SoC . . . . . . . . . . . . . . . . ..
± .OOS%
± .002%
9·24
8228/8238
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU
• Single Chip System Control for
MCS·80™ Systems
• User Selected Single Level Interrupt
Vector (RST 7)
• Built·ln Bidirectional Bus Driver for
Data Bus Isolation
• 28·Pln Dual In· Line Package
• Reduces System Package Count
• Allows the Use of Multiple Byte
Instructions (e.g. CALL) for Interrupt
Acknowledge
• *8238 Has Advanced IOW/MEMW for
Large System Timing Control
The Intel!!> 8228 is a single chip system controller and bus driver for MCS·80. It generates all signals required to
directly interface MCS·80 family RAM, ROM, and 110 components.
A bidirectional bus driver is included to provide high system TTL fan·out. It also provides isolation of the 8080 data bus
from memory and 110. This allows for the optimization of control signals, enabling the systems designer to use slower
memory and 110. The isolation of the bus driver also provides for enhanced system noise immunity.
A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small system
requirements. The 8228 also generates the correct control signals to allow the use of multiple byte instructions (e.g.,
CALL) in response to an interrupt acknowledge by the 8080A. This feature permits large, interrupt driven systems to
have an unlimited number of interrupt levels.
The 8228 is designed to support a wide variety of system bus structures and also reduce system package count for
cost effective, reliable design of the MCS·80 systems.
PIN CONFIGURATION
STsTB
BLOCK DIAGRAM
0,_
°°2 3- °0,0,00-
Vee
27
HLDA
I/ow
M'EMw
WR
DBIN
CPU {
DATA
BUS
-DB,
_DBO;
:= g:!
-
4-
1I0R
07 -
BUSEN
8228/8238
06
07
DB6
DB3
02
DRIVER CONTROL
INTA
D.
DB7
DB2
SYSTEM DATA BUS
- - DBs
DBa
DB7
MEMA
DB4
03
DB2
10
05
"
DB5
12
01
13
DBl
,.
GATING
ARRAY
~STB------------------~
DBIN
---------------------------1
~--------------------------~
HLDA
__________________________
-1
D'
PIN NAMES
07-00
DB7-DBO
170R
DATA BUS (8080 SIDE)
DATA BUS (SYSTEM SIDE)
I/O READ
INTA
HlOA
WR
INTERRUPT ACKNOWLEDGE
HlDA (FROM 8080)
WR (FROM 8080)
flOW
I/O WRITE
BUSEN
BUS ENABLE INPUT
MEMR
MEMORY REAO
STSTS
STATUS STROBE (FROM 8224)
MEMW
MEMORY WRITE
Vee
+5V
OBIN
DBIN (FROM 80BO)
GND
oVOLTS
9·25
8228/8238
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . . . _O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . _65°C to 150°C
Supply Voltage, Vee . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage . . . . . . . . . . . . . . . . . . . . . -1.5V to +7V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
D.C. CHARACTERISTICS
Symbol
TA = o°c to 70°C; Vee = 5V ±5%.
Parameter
Ve
Input Clamp Voltage, All Inputs
IF
Input Load Current,
STSTB
Limits
Min. Typ.!1] Max.
Unit
.75
V
Vee=4.75V; le=-5mA
500
(JA
VCC=5.25V
750
(JA
VF=0.45V
O2 & 06
250
All Other Inputs
Input Leakage Current
STSTB
OB o ·OB 7
A II Other I n puts
VTH
Input Threshold Voltage, All Inputs
Icc
Power Supply Current
VOL
VOH
(JA
100
(JA
VcC=5.25V
20
(JA
VR =5.25V
100
(JA
V
Vcc=5V
190
mA
VCC=5.25V
Output Low Voltage,
00. 0 7
.45
V
V c c=4.75V; 10L =2mA
All Other Outputs
.45
V
10L = 10mA
V
VcC=4.75V; IOW-1O(JA
0.8
140
Output High Voltage,
0 0 .0 7
3.6
All Other Outputs
2.4
Short Circuit Current, All Outputs
10 (oft)
Off State Output Current,
All Control Outputs
Note1:
250
2.0
lOS
liNT
Test Conditions
(JA
0 0 ,0 1 ,0 4 ,05 ,
&07
IR
-1.0
3.B
15
I NT A Current
V
10H = -lmA
90
mA
Vcc=5V
100
(JA
VcC=5.25V; Vo=5.25
-100
(JA
VO=.45V
mA
(See Figure below)
5
Typical values are for T A = 25 0 C and nominal supply voltages.
9·26
8228/8238
.,
WAVEFORMS
·2---~
STATUS STROBE
.O~DATABUS
______
-/~~-+_-J~
+-r__
DBIN _ _ _ _ _ _'ss
__
______________________
~
HLDA ______________~-+------+_----~
MA. iDA, MEMR ---------------+.
~------+_------f_"
DURING HlDA
----j-'I.I-- - - - - - - - - - - - - -
SYSTEM BUS DURING READ
8080 BUS DURING READ· -
-
-
-
-
-
-
'wR
IOWORMEMW--------------~rt------------------~
'wR
8080 BUS DURING WRITE
SYSTEM BU8DURINGWRITE -
-
-
-
-
-
-
-
j -
- - - - - - - - - - - - --
VOLTAGE MEASUREMENT POINTS: 00-07 (when outputs) Logic "0" = 0_8V, Logic "1" = 3.0V. All other signals measured
at 1.5V.
'ADVANCED IOW/MEMW FOR 8238 ONLY.
A.C. CHARACTERISTICS
Symbol
two
TA = o°c to 70"C; Vee = 5V ±5%.
Parameter
Delay from 8080 Bus Do-D7 to System Bus
DBO-DB7 during Write
9-27
8228/8238
CAPACITANCE
This parameter is periodically sampled and not 100% tested.
Limits
Parameter
Symbol
Min.
Typ.ll1
Max.
Unit
CIN
Input Capacitance
8
12
pF
COUT
Output Capacitance
Control Signals
7
15
pF
I/O
I/O Capacitance
(D or DB)
8
15
pF
+12V
1Kr2 ,10%
8228
Test Conditions: NS: VBIAS = 2.5V, Vcc=5.0V, TA = 25°C, f= 1MHz.
I
Note 2: For DO·D7: Rl = 4Kn., R2 = ~U,
CL = 2SpF. For all other outputs:
Rl = SOOn., R2 = 1 Kn., CL = 100pF.
23
INTA
1:)---------'
Figure 1. INTA Test Circuit (for RST 7)
2
Ao
GNO.-
20
<5V
A,
11
·5V
A,
28
+12V~
A,
A.
A,
25
Ao
26
A,
27
A,
29
A,
30
~
31
As
Ao
32
8080A
CPU
13
SYSTEM DMA R E O . - HOLD
A.
A,
A,
A,
A"
14
16
INT. ENABLE
INT
A,
1
A,.
40
A"
37
A12
3B
A13
39
A,.
36
A,. 18
A,.
A15
WR
OBIN
~D1TAL
TANK
OSC
.,(TTL)
RDYIN
RESIN
+12V
<5V
GND
---
14
HDLA
~
2
-~
21
2141
11
22
10
15
6,
D.
0,
D,
--!.
3
17
15
13
8224
4
~
23
1
12
CLOCK
GENERATOR
DRIVER
16
5
8
r
WAIT
READY
D,
D.
RESET
I.
0,
0,
D.
SYNC
0,
J
10
15
9
17
16
8
12
11
7
10
DB
13
8228/8238
9
BI-DIRECTIONAL
BUS DRIVER
5
3
6
4
19
5
21
20
6
8
7
23
28
<5V-
GND~1
STATUS STROBE
ADDRESS BUS .
Ao
A12
A13
INTE
A,
34
35
A,.
SYSTEM INT. REO.
33
22
BUSEN
0
Figure 2. CPU Standard Interface
9·28
18
-----
24
SYSTEM
CONTROL
..
..
..
.
0
0110
DB,
DB,
DB,
DB.
DATA BUS
DBs
DB.
DB,
IIIITA}
MEMR
26
MEM W
25
27
IIOR
IIOW
CONTROL BUS
inter
8205
HIGH SPEED 1 OUT OF 8 BINARY DECODER
• 1/0 Port or Memory Selector
• Simple Expansion -
• Low Input Load Current - .25 mA
max., 1/6 Standard TTL Input Load
• Minimum Line Reflection - Low
Voltage Diode Input Clamp
Enable Inputs
• High Speed Schottky Bipolar
Technology - 18ns Max. Delay
• Outputs Sink 10 mA min.
• 16-Pin Dual-In-Line Ceramic or
Plastic Package
• Directly Compatible with TTL Logic
Circuits
The 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory components with active low chip select input. When the 8205 is enabled, one of its eight outputs goes
"low", thus a single row of a memory system is selected. The 3 chip enable inputs on the 8205 allow easy
system expansion. For very large systems, 8205 decoders can be cascaded such that each decoder can drive
eight other decoders for arbitrary memory expansions.
The I ntel@8205 is packaged in a standard 16 pin dual-in-line package; and its performance is specified over
the temperature range of O°C to +75°C, ambient. The use of Schottky barrier diode clamped transistors to
obtain fast switching speeds results in higher performance than equivalent devices made with a gold diffusion process.
PIN CONFIGURATION
LOGIC SYMBOL
Ao
16
V.cc
Ao
A,
15
00
A,
Az
14
0,
A2
13
°z
4
E,
8205
8205
Ez
5
12
03
E3
6
11
0.
E,
10
05
E2
9
06
E3
°7
GRD
8
ADDRESS
"'0
PIN NAMES
AO· A2
E,· E3
00· 0,
ADDRESS INPUTS
ENABLE INPUTS
DECODED OUTPUTS
9-29
A,
A,
L
Ii
L
Ii
L
Ii
L
Ii
L
L
Ii
Ii
L
L
Ii
Ii
L
L
L
L
Ii
Ii
Ii
Ii
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ENABLE
" " "
L
L
L
L
L
L
L
L
L
Ii
L
Ii
Ii
L
Ii
L
L
L
L
L
L
L
L
L
L
Ii
Ii
L
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
L
L
L
L
Ii
H
Ii
0
L
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
H
,
Ii
L
Ii
Ii
Ii
Ii
"
Ii
Ii
Ii
Ii
Ii
Ii
H
Ii
OUTPUTS
2
3
4
5
6
7
Ii
Ii
L
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
H
Ii
Ii
Ii
Ii
L
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
H
Ii
Ii
Ii
Ii
Ii
L
Ii
Ii
Ii
H
Ii
Ii
Ii
Ii
H
Ii
Ii
H
Ii
H
Ii
L
Ii
Ii
Ii
Ii
Ii
Ii
Ii
L
H
Ii
Ii
Ii
H
H
Ii
Ii
Ii
Ii
Ii
Ii
H
L
Ii
Ii
Ii
Ii
Ii
H
H
H
Ii
Ii
Ii
Ii
Ii
H
H
H
H
8205
FUNCTIONAL OESCR IPTION
Decoder
The 8205 contains a one out of eight binary decOder. It accepts a three bit binary code and by gating this input, creates
an exclusive output that represents the value of the input
code.
Ao
~
A,
0;
A,
0,
For example, if a binary code of 101 was present on the AO,
A 1 and A2 address input lines, and the device was enabled,
an active low signal would appear on the 05 output line.
Note that all of the other output pins are sitting at a logic
high, thus the decoded output is said to be exclusive. The
decoders outputs will follow the truth table shown below in
the same manner for all other input variations.
0,
DECODER
0.
0;
0.
Enable Gate
0,
When using a decoder it is often necessary to gate the outputs with timing or enabling signals so that the exclusive
output of the decoded value is synchronous with the overall
system.
ENABLE GATE
E,
IEH2·03)
E,
0,
The 8205 has a built-in function for such gating. The three
enable inputs (Ei, E2, E3) are ANDed together and create
a single enable signal for the decoder. The combination of
both active "high" and active "low" device enable inputs
provides the designer with a powerfully flexible gating function to help reduce package count in his system.
ADDRESS
OUTPUTS
A,
A,
E,
E,
E3
0
1
2
3
4
5
6
7
L
H
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
fl
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
L
H
H
l
9-30
ENABLE
Ao
H
L
H
H
L
H
L
L
L
H
H
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
8205
ray of 8205s can be used to create a simple interface to a
24K memory system.
APPLICATIONS OF THE 8205
The 8205 can be used in a wide variety of applications in
microcomputer systems. I/O ports can be decoded from the
address bus, chip select signals can be generated to select
memory devices and the type of machine state such as in
8008 systems can be derived from a simple decoding of the
state lines (SO, Sl, S2) of the 8008 CPU.
The memory devices used can be either ROM or RAM and
are 1K in storage capacity. 8308s and 8102s are the devices
typically used for this application. This type of memory device has ten (10) address inputs and an active "low" chip
select (CS). The lower order address bits AO-A9 which come
from the microprocessor are "bussed" to all memory elements and the chip select to enable a specific device or group
of devices comes from the array of 8205s. The output of
the 8205 is active low so it is directly compatible with the
memory components.
I/O Port Decoder
Shown in the figure below is a typical application of the
8205. Address input lines are decoded by a group of 8205s
(3). Each input has a binary weight. For example, AO is assigned a value of 1 and is the LSB; A4 is assigned a value of
16 and is the MSB. By connecting them to the decoders as
shown, an active low signal that is exclusive in nature and
represents the value of the input address lines, is available at
the outputs of the 8205s_
Basic operation is that the CPU issues an address to identify
a specific memory location in which it wishes to "write" or
"read" data. The most significant address bits A 1O-A 14 are
decoded by the array of 8205s and an exclusive, active low,
chip select is generated that enables a specific memory device. The least significant address bits AO-A9 identify a
specific location within the selected device. Thus, all ad'
dresses throughout the entire memory array are exclusive
in nature and are non-redundant.
This circuit can be used to generate enable signals for I/O
ports or any other decoder related application.
Note that no external gating is required to decode up to 24
exclusive devices and that a simple addition of an inverter
or two will allow expansion to even larger decoder networks.
This technique can be expanded almost indefinitely to support even larger systems with the addition of a few inverters
and an extra decoder (8205).
Chip Select Decoder
Using a very similar circuit to the I/O port decoder, an ar-
Ao
A,
A,
A,
A,
8205
E,
A,
e;
EN
E,
_Ao
>----A,
f - - A,
E,
0,1:>-- '5
E,
EN
E;
E,
o,p--- CS
g
A,
0;1:>-- cs,o
8205
PORT
NUMBERS
-
E,
'----- Ao
-A,
Oop--0, I:>-o,p--- 18
o,p--o,p--- 2.
o,p--- 2'
o,p--- 22
0, I:>-- 23
~A,
,.
8205
E,
E,
E,
24K Memory Interface
I/O Port Decoder
9-31
o,p--- CS;;
o.p-- cs;;
o,p--o.p--0, I:>--
CS13
E,
E,
GND
17
8205
0;;1:>-- CS,
~A,
16
'---- A,
A,
~Ao
E,
E,
'---
E,
o,p--- CS,
o,p--- CS,
o;p--- CS,
0; I:>-- CS,
0; I:>-- Cs,
o;p--- CS,
o,p--- CS,
E;
13
...
0;,1:>-- CSo
8205
10
E,
'---
AO
A,
A,
°op--o,p--o,P--o,p--0, I:>-o,p--O,P--0, I:>-oop--o,p--0, I:>-o,p--- ,-,
o,p--- '2
0, I:>-o,p--- ,.
8205
EN
..... 11.._ _ _ _ _ _ _ _--,) ~~MORIES
o,p--0, p--o,p--o,p--o.p-o,p--o.P--o,p---
CHIP
SELECTS
8205
Logic Element Example
Probably the most overlooked application of the 8205 is
that of a general purpose logic element. Using the "on-chip"
enabling gate, the 8205 can be configured to gate its decoded outputs with system timing signals and generate
strobes that can be directly connected to latches, flip-flops
and one-shots that are used throughout the system.
and T2 decoded strobes can connect directly to devices like
8212s for latching the address information. The other decoded strobes can be used to generate signals to control the
system data bus, memory timing functions and interrupt
structure. RESET is connected to the enable gate so that
strobes are not generated during system reset, eliminating
accidental loading.
An excellent example of such an application is the "state
decoder" in an 8008 CPU based system. The 8008 CPU issues three bits of information (SO, S 1, S2) that indicate the
nature of the data on the Data Bus during each machine
state. Decoding of these signals is vital to generate strobes
that can load the addrllss latches, control bus discipline and
general machine functions.
The power of such a circuit becomes evident when a single
decoded strobe is logically broken down. Consider fi output, the boolean equation for it would be:
T1
13
4"
11
,.
14
5
10
(SO·S1·S2HSYNC·Phase 2·Reset)
A six input NAND gate plus a few inverters would be needed to implement this function. The seven remaining outputs
would need a similar circuit to duplicate their function,
obviously a substantial savings in components can be
achieved when using such a technique.
In the figure below a circuit is shown using the 8205 as the
"state decoder" for an 800B CPU that not only decodes the
SO, S1, S2 outputs but gates these signals with the clock
(phase 2) and the SYNC output of the 8008 CPU. The T1
2
=
TI
s,
S,
8008
CPU
WAIT
T2
8205
o
+---t--IE,
I
I
T4
T3
I
I
I
TS
I
OUTPUTS~~~_: r~ ~IJ "'!r- _-_- t+-i~ ~ !i_i- - - -+_i - - - -. .
T5
15
12
i___
__
F~
w_:
t-
1---------,~r--~I--i-l--t-
3------------.~r-~:--~:
~--------------ur---r-l-~Jr
SYSTEM RESET
State Control Coding
50
0
0
0
0
1
1
1
1
$,
1
1
0
0
0
1
1
0
S, STATE
0
Tl
1
1
T2
0
0
0
1
1
TIl
WAIT
T3
STOP
T4
T5
9-32
8205
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias:
'COMMENT
-65°C to .1250 C
-65°C to + 75°C
Ceramic
Plastic
Stresses above those listed under "Absolute Maximum Rat·
ing" may cause permanent damage to the device. T:,is is a stress
rating only and functional operation of the device at these or at
any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
-65°C to +160o C
Storage Temperature
-0.5 to + 7 Volts
All Output or Supply Voltages
-1.0 to +5.5 Volts
All Input Voltages
125 mA
Output Currents
D.C. CHARACTERISTICS TA
= DoC to +75°C, Vee = 5.0V ±5%
8205
PARAMETER
SYMBOL
-
MIN.
LIMIT
MAX.
-0.25
UNIT
TEST CONDITIONS
= 5.25V, V F = 0.45V
IF
INPUT LOAD CURRENT
mA
Vee
IA
INPUT LEAKAGE CURRENT
10
fJA
Vee
Ve
INPUT FORWARD CLAMP VOLTAGE
-1.0
V
= 5.25V, VA = 5.25V
Vee = 4.75V, Ie = -5.0 mA
VOL
OUTPUT "LOW" VOLTAGE
V
Vee
VOH
OUTPUT HIGH VOLTAGE
V
Vee
V 1l
INPUT "LOW" VOLTAGE
V
Vee
V 1H
INPUT "HIGH" VOL TAGE
V
Vee
Ise
OUTPUT HIGH SHORT
CIRCUIT CURRENT
Vox
OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT
Icc
POWER SUPPLY CURRENT
0.45
2.4
0.85
2.0
-40
-120
0.8
70
= 4.75V, IOl = 10.0 mA
= 4.75V, IOH = -1.5 mA
mA
= 5.0V
= 5.0V
Vee = 5.0V, VOUT
V
Vee
= 5.0V, lox
mA
Vee
= 5.25V
=
=
OV
40 mA
TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
DATA TRANSFER FUNCTION
50
100
~
25"C
~
80
Vee'" 5 OV
~
60
-. ~
~
T.
~
75"C_
20
~
AI' l .2
.4
~
TA - O"C
w
-20
1-1-1-Hf--ifI#-1H--+--+-I
~ 3,0
-30
I--I--+-+---+'II+--+---+--I--+--l
~
I--+-+-.....
/H---+--+---+---+-~
o
c:>
-40
TA " DOC
.6
~:>
TA " 2S"C
2.0
T A " 75"C
1.0
i\ I\:<
f-t f.\
H
.8
OUTPUT "lOW" VOL TAGE IV)
1.0
1.0
2.0
3.0
40
OUTPUT "HIGH" VOLTAGE (V)
9·33
5.0
\
\
1\ 1\
_~~L-wA~-L-L-L~~~
TA," 25"C
-
40
-10
TA." Dec
II
/ b'4
-
Vee" S.OV
j
40
T T
V
TA " 75"<: -...
T.
.2
.4
.6
.8
1.0
"- _\ l'-
1.2 1.4
INPUT VOL T AGE (V)
1.6
1.B 2.0
8205
8205 SWITCHING CHARACTERISTICS
CONDITIONS OF TEST:
Input pulse amplitudes:
TEST LOAD:
3901"2
2.5V
Input rise and fall times: 5 nsec
between 1 V and 2V
Measurements are made at 1.5V
All TransIstors 2N2369 or EqUIvalent.
CL
=
30 pF
TEST WAVEFORMS
ADDRESS OR ENABLE
INPUT PULSE
---------------~--------------------~,----------------
OUTPUT
A.C. CHARACTERISTICS TA
I
SYMBOL
= O°C
to +75°C, Vce
I
PARAMETER
MAX. LIMIT
t++
ADDRESS OR ENABLE TO
OUTPUT DELAY
t_+
t+
t -C'N
= 5.0V ±5% unless otherwise specified.
UNIT
18
ns
18
ns
18
ns
ns
18
(1)
INPUT CAPACITANCE
1, This parameter (s periodically sampled and
IS
4(typ.1
5(typ.1
P8205
C8205
TEST CONDITIONS
pF
pF
f " 1 MHz, Vce " OV
VSIAS " 2.0V, T A" 250 e
0
not lOOro
tested.
TYPICAL CHARACTERISTICS
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE
20r-----,------,-----,------,
g
15
20r------.-------r-1.----~
Vee" 50V
vee"
TA "25"C
CL
g
f-----+------f
w
-'
a>
w
5.0V
"'30pF
15~-------r------~------~
-'
«
'"
«
~
~
'"o
'o"
MD ---+H_~
[I>
STB ~-----1LJ
IT> D', --------+-+1
DATA LATCH
[I>D', - - - - - - - - = l - - H
PIN NAMES
DI,·D~
OATA IN
DOt·DOt
lIIj.os.
DATA OUT
MD
STB
IN'F
CLR
MODE
STROBE
INTERRUPT (ACTIVE LOW)
CLEAR (ACTIVE LOW)
DEVICE SELECT
12]> D '6 - - - - - - - - - - , - - H
~ DI,
~
--------+-H
D'8---------L-H
IE> CLR-----~
9-35
FUNCTIONAL DESCRIPTION
Service Request Flip-Flop
Data Latch
The (8R) flip-flop is used to generate and control
interrupts in microcomputer systems. It is asynchronously set by the CLR input (active low). When the (8R) flipflop is set it is in the non-interrupting state.
The 8 flip-flops that make up the data latch are of a "0"
type design. The output (Q) of the flip-flop will follow the
data input (0) while the clock input (C) is high. Latching
will occur when the clock (C) returns low.
The output of the (8R) flip-flop (Q) is connected to an
inverting input of a "NOR" gate. The other input to the
"NOR" gate is non-inverting and is connected to the
device selection logic (081 • 082). The output of the
"NOR" gate (INT) is active low (interrupting state) for
connection to active low input priority generating circuits.
The latched data is cleared by an asynchronous reset
input (CLR). (Note: Clock (C) Overrides Reset (CLR).)
Output Buffer
The outputs of the data latch (Q) are connected to 3-state,
non-inverting output buffers. These buffers have a
common control line (EN); this control line either enables
the buffer to transmit the data from the outputs of the data
latch (Q) or disables the buffer, forcing the output into a
high impedance state. (3-state)
SERVICE REQUEST FF
IT> DS'
lIT> OS,
The high-impedance state allows the designer to connect
the 8212 directly onto the microprocessor bi-directional
data bus.
[I>
MO
[IT>
STB
INT@
OUTPUT
BUFFER
Control Logic
The 8212 has control inputs 081, 082, MO and 8TB.
These inputs are used to control device selection, data
latching, output buffer state and service request flip-flop.
DS1, DS2 (Device Select)
These 2 inputs are used for device selection. When 081 is
low and 082 is high (081 • 082) the device is selected. In
the selected state the output buffer is enabled and the
service request flip-flop (8R) is asynchronously set.
rI>
II> 01,
DO,
[DD12
DO, ~
II> 0 '3
003[i>
[[>0'4
0°4
[2]>
!!DOlo
0°5
G3>
MD (Mode)
I!:E> 0 '6
0°6
[iI>
This input is used to control the state of the output buffer
and to determine the source of the clock input (C) to the
data latch.
~Ol,
DO,
!I2>
When MO is high (output mode) the output buffers are
enabled and the source of clock (C) to the data latch is
from the device selection logic (081 ·082).
§>O'B
DOBIE>
~CLA
When MO is low (input mode) the output buffer state is
determined by the device selection logic (081 • 082) and
the source of clock (C) to the data latch is the 8TB
(8trobe) input.
ST.
0
1
0
1
0
1
0
1
STB (Strobe)
This input is used as the clock (C) to the data latch forthe
input mode MO = 0) and to synchronously reset the
service request flip-flop (8R).
MO
(DS1- DS 2)
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
DATA OUT EQUALS
3STATE
3· TATE
DATA LATCH
DATA LATCH
DATA LATCH
DATA IN
DATA IN
DATA IN
eLA - RESETS OAT A LATCH
SETS SA FLIP-FLOP
(NO EFFECT ON OUTPUT BUFFER)
Note that the 8R flip-flop is negative edge triggered.
9-36
CLR
0
0
1
1
1
1
(oS,-052)
0
1
1
1
0
1
ST.
0
0
'-0
0
~
'SR
'NT
1
1
0
1
1
1
1
0
0
0
1
0
-INTERNAL SA FLIP-FLOP
8212
Applications of the 8212 - For
Microcomputer Systems
II
III
IV
Basic Schematic Symbol
Gated Buffer
Bi-Directional Bus Driver
Interrupting Input Port
V
VI
VII
VIII
Interrupt Instruction Port
Output Port
8080A Status Latch
8085A Address Latch
1. Basic Schematic Symbols
showing the system input or output as a system bus (buS
containing 8 parallel lines). The output to the data bus is
symbolic in referencing 8 parallel lines.
Two examples of ways to draw the 8212 on system
schematics - (1) the top being the detailed view showing
pin numbers, and (2) the bottom being the symbolic view
BASIC SCHEMATIC SYMBOLS
OUTPUT DEVICE
INPUT DEVICE
"
11
STB
01
DO
4
6
01
STB
DO
7
9
16
18
20
8212
10
15
17
19
16
18
20
22
23
(DETAILED}
B212
INT
GND
INPUT
STROBE
CLR
10
15
17
19
21
14
Vee
----;::=L-,
SYSTEM
INPUT
OUTPUT
FLAG
SYSTEM
OUTPUT
(SYMBOLIC}
GND
DATA BUS
GATED BUFFER
II. Gated Buffer (3-State)
The simplest use of the 8212 is that of a gated buffer. By
tying the mode signal low and the strobe input high, the
data latch is acting as a straight through gate. The output
buffers are then enabled from the device selection logic
DS1 and DS2.
Vcc--~------~-------,
STB
INPUT
DATA
1250 "A}
When the device selection logic is false, the outputs are 3state.
8212
~----------~CLR
When the device selection logic is true, the input data from
the system is directly transferred to the output. The input
data load is 250 micro amps. The output data can sink 15
milli amps. The minimum high output is 3.65 volts.
GATING {
CONTROL
(DS1.DS2}
9·37
- - -__________- '
OUTPUT
DATA
(15mA}
13.65V MIN}
8212
BI-DIRECTIONAL BUS DRIVER
III. BI-Dlrectlonal Bus Driver
A pair of 8212's wired (back-to-back) can be used as a
symmetrical drive, bi-directional bus driver. The devices
are controlled by the data bus input control which is
connected to DS1 on the first 8212 and to DS2 on the
second. One device is active, and acting as a straight
through buffer the other is in 3-state mode. This is a very
useful circuit in small system design.
DATA
BUS
,
j
~
~
~
8212
v
--c
DATA BUS
CONTROL
(0= L -R)
(I = R- L)
STB
DATA
BUS
CLR
-
G~O L-...
STB
8212
L
/'--
"-r
CLR
----I
~
GNO
IV. Interrupting Input Port
INTERRUPTING INPUT PORT
This use of an 8212 is that of a system input port that
accepts a strobe from the system input source, which in
turn clears the service request flip-flop and interrupts the
processor. The processor then goes through a service
routine, identifies the port, and causes the device
selection logic to go true - enabling the system input data
onto the data bus.
DATA
BUS
INPUT
STROBE
STB
SYSTEM
INPUT
SYSTEM
RESET
PORT
{
SELECTION
(OS1.0S2)
_ _ _ _ _...J
......_ _ _
~~C~~~~R~~~)CKT
OR
TO CPU
INTERRUPT INPUT
V. Interrupt Instruction Port
INTERRUPT INSTRUCTION PORT
The 8212 can be used to gate the interrupt instruction,
normally RESTART instructions, onto the data bus. The
device is enabled from the interrupt acknowledge signal
from the microprocessor and from a port selection signal.
This Signal is normally tied to ground. (OS1 could be used
to multiplex a variety of interrupt instruction ports onto a
common bus).
DATA
BUS
STB
RESTART
INSTRUCTION
(RST O-RST 7)
(OSI) PORT SELECTION
---...J
INTERRUPT ACKNOWLEDGE _ _
9·38
8212
VI. Output Port (WIth HIInd·....ldng)
OUTPUT PORT (WITH HAND-SHAKING)
DATA
BUS
The 8212 can be used to transmit data from the data bus to
a system output. The output strobe could be a handshaking signal such as "reception of data" from the device
that the system Is outputting to. It In turn, can Interrupt the
system signifying the reception of data. The selection of
the port comes from the device selection logic.(OS1 • OS2)
, . . - - _......-
OUTPUT STROBE
STB
SYSTEM OUTPUT
SYSTEM RESET
SYSTEM
INTERRUPT
L -_ _ _> _ _ -
PORT SELECTION
} (LATCH CONTROLI
(!m.DS21
VII. _OA 'tatUI LIItch
Here the 8212 is used as the status latch for an 8080A
microcomputer system. The input to the 8212 latch Is
directly from the 8080A data bus. Timing shows that when
the SYNC signal is true, which Is connected to the DS2
input and the phase 1 signal Is true, which is a TTL level
coming from the clock generator; then, the status data will
be latched into the 8212.
/:
0,
O2
03
04
05
0,
07
8080A
SYNC
DBIN
Ql
It is shown that the two areas of concern are the bidirectional data bus of the microprocessor and the control
bus.
10
9
8
7
DATA BUS
3
4
5
6
19
1L-
02
22
12V
Note: The mode signal is tied high so that the output on the
latch is active and enabled all the time.
STATUS
LATCH
15
'---4
1"'\
~7
ovJ \.,~ r-------,
CLOCK GEN.
• DRIVER
0,
~
~
8212
r,g
20
rz,-
22
~
~ INTA
~ Wo
~
9
16
18
-~TLI
Do
F-
CLR
STACK
HLTA
OUT
Ml
INP
MEMR
T1
01
BASIC
92
CONTROL
BUS
SYNC
DS~ MD OS,
13 12
DATA
'1'1
DBIN
STATUS
9-39
T2
8212
VIII. 808SA Low-Order Address Latch
The 8085A microprocessor uses a multiplexed address/
data bus that contains the low order 8-bits of address
information during the first part of a machine cycle. The
same bus contains data at a later time in the cycle. An
address latch enable (ALE) signal is provided by the
8085A to be used by the 8212 to latch the address so that it
may be available through the whole machine cycle. Note:
In this configuration, the MODE input is tied high, keeping
the 8212's output buffers turned on at all times.
8085A
ADo
ADl
AD2
AD3
AD4
ADs
AD6
AD7
ALE
12
13
14
15
16
17
18
19
DATA BUS
II
•
r1LVee
11T
3
Dll STB 001
'----S
7
~ A4
I#- As
8212
18
~
20
22
CLR
DS 2 MD
13 12
J
Vee
9·40
~~IJ
A2
r,o A3
9
16
f
~
~
8
A6
If,- A7
t=-
r
5s,
_
LOW ORDER
ADDRESS BUS
8212
ABSOLUTE MAXIMUM RATINGS·
'eOMMENT
Temperature Under Bias Plastic ....... O°C to +70°C
Storage Temperature .............. -65°C to +160°C
All Output or Supply Voltages ........ -0.5 to +7 Volts
All Input Voltages .................. -1.0 to 5.5 Volts
Output Currents ............................. 100mA
D.C. CHARACTERISTICS
Symbol
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functIOnal
operation of the device at these or any other conditions above those
indicated In the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended penods
may affect device reliability.
TA = O°C to +75°C, Vee = +5V ±5%
Parameter
Limits
Min.
Typ.
Max.
Unit
Test Conditions
IF
Input Load Current, ACK, OS2, CR,
01,-018 Inputs
-.25
mA
VF
IF
Input Load Current MO Input
-.75
mA
VF
IF
Input Load Current OS, Input
-1.0
mA
VF
= .45V
= .45V
= .45V
IR
Input Leakage Current, ACK, OS, CR,
01,-018 Inputs
10
p.A
VR
~
Vee
IR
Input Leakage Current MO Input
30
p.A
VR
~
Vee
IR
Input Leakage Current OS, Input
40
p.A
VR
~
Vee
Ve
Input Forward Voltage Clamp
-1
V
Ie
= -5mA
VIL
Input "Low" Voltage
.85
V
VIH
Input "High" Voltage
VOL
Output "Low" Voltage
.45
V
IOL
VOH
Output "High" Voltage
3.65
V
IOH
Ise
Short Circuit Output Current
-15
mA
Vo
= 15mA
= -1mA
= OV, Vee = 5V
1101
Output Leakage Current High
Impedance State
20
p.A
Vo
= .45V/5.25V
lee
Power Supply Current
130
mA
V
2.0
4.0
-75
90
9-41
8212
TYPICAL CHARACTERISTICS
INPUT CURRENT VS. INPUT VOLTAGE
-50
1....
100
TA "0' C
15
/'
l00r------,-------,-------,-------,
~
a
v
Vee'" l5.0V
OUTPUT CURRENT VS. OUTPUT "LOW" VOLTAGE
Vee'" +5.0V
80r_----~~----_+------_+------~
/T A "25"C
/ /T A "75"C
60~----_1------_+------_+~~~~
~ -150
"u....
~
~
40r-------~--~_4--~~~------_1
-200
~r_----~--~~~~----_+------~
-250
-300
-3
-,
-2
'2
"
°0~--~~~----~-------.76------~.8
'3
INPUT VOLTAGE (V)
OUTPUT "LOW" VOLTAGE (V)
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE
50
Vee'" l5.QV
TA = 25"C
40
30
20
10
---;;:.
50
-----
100
-- --
\-\-;.-t":"-
150
250
200
300
LOAD CAPACITANCE (pF)
OUTPUT "HIGH' VOLTAGE (V)
WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE
DATA TO OUTPUT DELAY
VS. TEMPERATURE
22r-----r-----~----,_-----,----,
Vee'" +s.ov
35~----+-----t-----f_----~----~
20r-----+-----~----~----~----_i
/
/
'8r_----+-----+-----~~~~----~
>
)~
....
.....
30~----+-----t-----f_----~----~
1--/
25j-----t-----f_=-q:---,-'. . .r------j
16r_----+-.....
-.....- .....
~~--~------r_--__i
'"
..... t+_
141---t----t---t-----------""t-------1
--
'2r-----+-----~----~----~----_i
15+-----+-----~----~-----+----_i
1~·~5----~----~25~--~~~--~7~5----~,00
1~2·~5----~----~25~-----;:I50~--~7~5----~,00
t--
-
TEMPERATURE C'C)
TEMPERATURE (oG)
9-42
8212
A.C. CHARACTERISTICS
Symbol
TA
= O°C to +70°C,
Vcc
= +5V ± 5%
Limits
Parameter
Min.
Typ.
Unit
Max,
Test Conditions
tpw
Pulse Width
tpo
Data to Output Delay
30
ns
ns
Note 1
tWE
Write Enable to Output Delay
40
ns
Note 1
tSET
Data Set Up Time
15
20
30
ns
ns
tH
Data Hold Time
tR
Reset to Output Delay
40
ns
Note 1
ts
Set to Output Delay
30
ns
Note 1
tE
Output Enable/Disable Time
45
ns
Note 1
tc
Clear to Output Delay
55
ns
Note 1
CAPACITANCE*
Symbol
F
= 1MHz, VBIAS = 2.5V,
Vcc
= +5V, TA = 25°C
Limits
Test
Typ. Max.
CIN
051 MD Input Capacitance
CIN
052, CK, ACK, Db-Ole
Input CapaCitance
9pF 12pF
5pF 9pF
COUT
001-008 Output CapaCitance
8pF 12pF
'This parameter is sampled and not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test
Input Pulse Amplitude = 2.5V
Input Rise and Fall Times 5ns
Between 1V and 2V Measurements made at 1.5V
with 15mA and 30pF Test Load
Test Load
15mA & 30pF
VCC
Note 1:
Test
CL"
R1
R2
tpD, tWE, tR. ts, tc
30pF
300n
600n
tEo ENABLEI
30pF
10Kn
1Kn
tEo ENABLE)
30pF
300n
600n
tE, DISABLEI
5pF
300n
600n
tE, DISABLE)
5pF
10Kn
1Kn
TO
D.U.T.
'INCLUDING JIG & PROBE CAPACITANCE
'Includes probe and jig capaCitance.
9·43
8212
TIMING DIAGRAM
15V)("" -
DATA
-
•
DS2
-
-
-
-
1 5V!
-'I:
-
'1' 'H
I;=='PW
_____ -1.
STB", OS,
-
5V
=--1'-----
\ \ . . '_5V_ _ _ _ _ _ __
I--'WE----....!
OUTPUT
OS,.
______ ~ _____ J~:-------
DS2
15Vj
\1.5V
x
--------~--'E-:J r _ ~E~~~W~ _ ~-'-D-__j-,---OUTPUT
_______
~~=-==--.-
r-'PWi
15V~
CLR
~15V
________~14~~tC==~r ____ _
DO
_ _ _ _ _ _ _ _ _ _ _ _ _ _ .J\\..1_5V
_ _ _ _ _ __
, 5V X - - - - - - - - - - y ' 5 V
DATA
~'-----
_ _ _ _ _ .../1 .
STB or
OS, •
OUTPUT
r 'SET 1:\
DS2
'H
-
i- 'PD-1
_ _ _ _ _ _ _ J~5;-----------
STS
_ _ _ _- - - ' t \ 1 5 V
' .
~'pw=i
DSl' DS2 -------~ -------~:--
~-- tPw:+; 's
I
- - + - - - - - :\
NOTE: ALTERNATIVE TEST LOAD
I-- tR
.-1
Vee
OUT
~
CL
'0K
'::' 1K
9-44
F
infel~
8214
PRIORITY INTERRUPT CONTROL UNIT
• 8 Priority Levels
• Fully Expandable
• Current Statu8 Aeglster
• High Performance (50 n8)
• Priority Comparator
• 24-Pln Dual In· Line Package
The Intel- 8214 Is an 8-level priority Interrupt control unit (PICU) designed to simplify Interrupt·driven microcomputer
systems.
The PICU can accept 8 requesting levels; determine the highest priority, compare this priority to a software controlled
current status register and Issue an Interrupt to the system along with vector Information to identify the service
routine.
The 8214 Is fully expandable by the use of open collector Interrupt output vector Information. Control signals are also
provided to simplify this function.
The PICU Is designed to support a wide variety of vectored interrupt structures and reduce package count In interrupt·
driven microcomputer systems.
·Not.: The specifications for the 3214 are Identical with tho•• for th. 8214.
PIN CONFIGURATION
LOGIC DIAGRAM
[jDECR
a;;
.,
Vee
II!>ETLC.-
ECS
i;
l!!> R.
R,
REQUEST ACTIVITY
R.
R.
SG8
iNT
CLK
R.
8214
A,
INTE
A;
A,
A;
R,
R,
Ro
ELR
ENLG
GND
ETLG
PIN NAMES
INPUTS
II;:Ii
RIOUIS' LEVELlIR) HIGHEIT PRIORITY)
~
_
CURReNT STATUI
Ri
ENABLE CURRENT ITA"UI
INTERRUPT ENAILI
CLOCK liNT ,.f)
.NTI
o
[!!>
[IT>
[!!>
[i!>
~
~
I!D
"-CD
A,[D
if.
Rs
As
A, UI>
R,
[!>
S;;
ED
B,
B,
CD
§GI
Ili>
ECs
ID
(OPEN COLLECTOR)
R,
R,
R,
PRIORITY
COMPARATOR
IT>
INTE - - - - - - - - - - - - '
DC>
~-----------------~
ITATUI GROUP "LECT
lUi
ENMLE LIVEL RIAD
ETLG
INAILI TMI' LEVlL GROUP
OUTPUTS:
i;.ij
ilf
RIOf.MIT LEVELl
}
INTERR ..... CACT. LOWI
INLG
ENAILI NEXT LEVEL GROUP
OHN
COLLECTOR
9·45
8214
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 7SoC
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6SoC to +160°C
All Output and Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -O.SV to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +S.SV
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 100 mA
'COMMENT: Stresses abo.e those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating
only and functional oparation of the device at these or at any other condition above those indicated in the operational sections of this specifi·
cations is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA = o°c to +70°C. VCC = 5V ±5%.
Symbol
-_.
Parameter
Vc
Input Clamp Voltage (all inputs)
IF
Input Forward Current:
ETlG input
all other inputs
IR
Input Reverse Current:
ETlG input
all other inputs
Vil
Input lOW Voltage:
all inputs
VIH
Input HIGH Voltage:
all inputs
Icc
Power Supply Current
VOL
Output LOW Voltage:
all outputs
VOH
Output HIGH Voltage:
ENLG output
los
Short Ci.cuit Output Current: ENLG output
ICEX
Output Leakage Current: INT and Ao ·A2
Min.
limits
Typ,!l1
-.15
-.08
Max.
V
Ic=-5mA
-0.5
-0.25
mA
mA
VF=0.45V
80
40
IJ.A
IJ.A
VR=5.25V
0.8
V
VCC=5.0V
V
Vcc=5.0V
90
130
mA
See Note 2.
.3
.45
V
10l =15mA
V
IOH=-1mA
-55
mA
VOs=OV, VCc=5.0V
100
IJ.A
VC Ex=5.25V
2.4
3.0
-20
-35
9·46
Conditions
-1.0
2.0
NOTES:
1. Typical values are for TA = 25"C, VCC= 5.0V.
2. 80.82, SGS, ClK, Ro·R4 grounded, all other inputs and all outputs open.
Unit
8214
A.C. CHARACTERISTICS
Symbol
TA = o°c to +70°C, VCC
=+5V ±5%
Parameter
Min.
limits
Typ.111
50
Max.
Unit
tCY
ClK Cycle Time
80
tpw
ClK, ECS, INT Pulse Width
25
15
ns
tlSS
INTE Setup Time to ClK
16
12
ns
ns
tlSH
INTE Hold Time after ClK
20
10
ns
tETCS[2]
ETlG Setup Time to ClK
25
12
ns
tETCH[2]
ETlG Hold Time After ClK
20
10
ns
tECCS[2]
ECS Setup Time to ClK
80
25
ns
tECCH[3]
ECS Hold Time After ClK
0
tECRS[3]
ECS Setup Time to ClK
tECRH[3]
ECS Hold Time After ClK
0
tECSS[2]
ECS Setup Time to ClK
75
tECSH[2]
ECS Hold Time After ClK
toCS[2]
SGS and 80-82 Setup Time to ClK
tOCH[2]
SGS and 80.82 Hold Time After ClK
0
tRCS[3]
Ro-R7 Setup Time to ClK
90
tRCH[3]
Ro-R7 Hold Time After ClK
0
tiCS
INT Setup Time to ClK
55
tCI
ClK to INT Propagation Delay
tRIS[4]
Ro-R7 Setup Time to INT
10
0
ns
tRIH[4]
Ro-R7 Hold Time After INT
35
20
ns
110
ns
70
ns
70
ns
0
70
ns
50
ns
ns
55
ns
ns
35
15
ns
25
ns
tRA
Ro-R7 to Ao-A2 Propagation Delay
80
100
ns
tELA
ElR to Ao-A2 Propagation Delay
40
55
ns
tECA
ECS to Ao-A2 Propagation Delay
100
120
ns
tETA
ETlG to Ao-A2 Propagation Delay
35
70
ns
tOECS[4]
SGS and 80-82 Setup Time to ECS
15
10
tOECH[4]
SGS and 8 0 -82 Hold Time After ECS
15
10
tREN
Ro-R7 to ENlG Propagation Delay
45
70
ns
tETEN
ETlG to ENLG Propagation Delay
20
25
ns
tECRN
ECS to ENlG Propagation Delay
85
90
ns
tECSN
ECS to EN lG Propagation Delay
35
55
ns
ns
ns
CAPACITANCE[5)
limits
Typ.l1]
Max
Unit
CIN
Input Capac itance
5
10
pF
COUT
Output Capacitance
7
12
pF
Symbol
Parameter
Test Conditions:
VSIAS = 2.5V, vcc
Min.
= 5V, TA = 25°C, f = 1 MHz
NOTE 5. This parameter is periodically sampled and not 100% tested.
9-47
8214
WAVEFORMS
iiii-o,
';<:-----------------'1.
•______ 1
'1\. _____
-RCS
tACH.
tRIS
)(------.1"'_
___
tRIK
------- --"\
,------_!._------
-------1----
--------'\rnJ--------------I
_
J"" __________ _ .1'(1"---+-------
ETLG
1
lUes
INTE
I
tETCH
~.
~'____~-~------J·,I~-/II~--~------~--tlSS
I
tlSH
,..---- l)··r-I---""v-'r~
iGs.iiO-ii
~~8.~~'---~----1'"'
+:.J (" '1 teeRH
EeRS
'PW
•
-----------
teecH
tcy
I~ ~~~~---~~I~--~__t~I~~~
iNT -+----1---+-------+----------~lr-----
----------.1
--I-----~-fiR
"1"---
- ---- --- -----~~::~~~~tR~A~~~~~~~~~~~·il
,-~-------,=-=--=t.-='\~r------------'\~_1-----------~ __
~~
;;.0;
.~
__
I~~
J..
~,
~---_---~---I'_+----------_+-J
tREN
tETEN
..-------
tecsN
ENLG
-----------------'\,---------------------~____________________ _
NOTES:
(1) Typical values are for T A = 25°e, Vee = 5.0V.
(2) Required for proper operation if ISE is enabled during next clock pulse.
(3) These times are nOI required for pr"per "peralion bUI for desired change in interrupt flip·flop.
(4) Required for new requesl or slatus 10 be properly loaded.
Test Conditions
Test Load Circuit
Input pulse amplitude: 2,5 volts.
Input rise and fall times: 5 ns between 1 and 2 volts.
300!l
Output loading of 15 mA and 30 pf.
OUT
Speed measurements taken at the 1.5V levels.
0--..,..------1
lOp'
9·48
600n
inter
8216/8226
4·BIT PARALLEL BIDIRECTIONAL BUS DRIVER
• Data Bus Buffer Driver for 8080 CPU
• 3.65V Output High Voltage for Direct
Interface to 8080 CPU
• Low Input Load Current - 0.25 mA
Maximum
• 3·State Outputs
• High Output Drive Capability for
Driving System Bus
• Reduces System Package Count
The 8216/8226 is a 4-bit bidirectional bus driver/receiver. All inputs are low power TIL compatible. For driving MOS, the
DO outputs provide a high 3.65V VOH , and for high capacitance terminated bus structures, the DB outputs provide a
high 50 rnA IOL capability. A non-inverting (8216) and an inverting (8226) are available to meet a wide variety of applications for buffering in microcomputer systems .
• Note: The specifications for the 3216/3226 are identical with those for the 8216/8226.
PIN CONFIGURATION
cs
LOGIC DIAGRAM
LOGIC DIAGRAM
8216
8226
Vee
00,
OlEN
08,
DO,
01,
08,
DO,
01,
08,
DO,
01, <>------0---+-..,
01,
oO,o---+-----+-- Cs
OlEN 0 - -......- - - - - '
OlEN 0 - -......- - - - - '
9-49
DB,
DO,
C>----+--< t--+--'
DB,
080 ·oB3
DB,
DO,
DO,o---+-- DO
} HIGH IMPEDANCE
Figure 1. 8216/8226 Logic Diagrams
9-50
8216/8226
WAVEFORMS
INPUTS
OUTPUT
ENABLE
~tDj Y
,.5V"',..-----..~
.
~H
.5V
OUTPUTS
t~L
A.C. CHARACTERISTICS
TA = O°C to +70°C, Vcc = +~" ±5%
Limits
Typ.ll]
Max.
Unit
TpOl
Input to Output Delay DO Outputs
15
25
ns
CL=30pF,Rl=300S!
R2=600S!
Tp02
Input to Output Delay DB Outputs
8216
19
30
ns
CL =300pF, Rl=90S!
8226
16
25
ns
R2 = 180S!
8216
42
65
ns
(Note 2)
36
54
ns
(Note 3)
16
35
ns
(Note 4)
Symbol
TE
Min.
Parameter
Output Enable Time
8226
To
Conditions
Output Disable Time
Test Load Circuit
Te.t Condition.:
Input pulse amplitude of 2.5V.
I nput rise and fall times of 5 ns between 1 and 2 volts.
Output loading is 5 mA and 10 pF.
Speed measurements are made at 1.5 volt levels.
OUT o--..-----~
CAPACITANCEIS)
Symbol
Min.
Parameter
Limits
Typ.!1]
Max.
Unit
CIN
Input Capacitance
4
8
pF
CO UTl
Output Capacitance
6
10
pF
CO UT2
Output Capacitance
13
18
pF
Test Conditions
NOTES:
1. Typical values are for TA = 25°C, VCC = 5.0V.
2. DO Outputs, CL = 30pF, Rl = 300/10 K!l, R2 = 180/1K!l; DB Outputs, CL = 30OpF, Rl = 90/10 K!l, R2 = 180/1 K!l.
3. DO Outputs, CL = 30pF, Rl = 300/10K!l, R2 = 600/1K; DB Outputs, CL =30OpF, RI =90/10 K!l, R2 = 180/1 K!l.
4. DO Outputs, CL = 5pF, Rl = 300/10K!l, R2 = 600/1 K!l; DB Outputs, CL = 5pF, Rl = 90/10 K!l, R2 = lBOll K!l.
5. This parameter is periodically sampled and not 100% tested.
9·51
8216/8226
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . . . . O°C to 70°C
Storage Temperature ............ -65°C to +150°C
All Output and Supply Voltages. . . . . ..
-0.5V to +7V
All I nput Voltages. . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . .. 125 rnA
D.C. AND OPERATING CHARACTERISTICS
Symbol
Limits
Typ.
Max.
Unit
IF1
Input Load Current OlEN, CS
-0.15
-.5
rnA
VF =0.45
IF2
Input Load Current All Other Inputs
-0.08
-.25
rnA
VF =0.45
IR1
Input Leakage Current 0 I EN, CS
80
fJ.A
VR =5.25V
IR2
Input Leakage Current 01 Inputs
40
fJ.A
VR =5.25V
Vc
Input Forward Voltage Clamp
-1
V
Ic= -5mA
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
1101
Output Leakage Current
(3-State)
Icc
Power Supply Current
VO L1
Output "Low" Voltage
VOL2
Output "Low" Voltage
VOH1
Output "High" Voltage
3.65
4.0
V
DO Outputs 10H = -lmA
VOH2
Output "High" Voltage
2.4
3.0
V
DB Outputs 10H = -10mA
los
Output Short Circuit Current
-15
-30
-35
-75
Parameter
Min.
.95
Conditions
V
V
2.0
DO
DB
20
100
fJ.A
Vo = 0.45V/5.25V
8216
95
130
rnA
8226
85
120
mA
0.3
.45
V
DO Outputs IOL=15mA
DB Outputs 10L =25mA
8216
0.5
.6
V
DB Outputs 10L =55mA
8226
0.5
.6
V
DB Outputs 10L =50mA
NOTE: Typical values are for TA = 25°C, VCC=5.0V.
9-52
-65
-120
mA
mA
DO Outputs VO~OV,
DB Outputs VcC=5.0V
8216/8226
APPLICATIONS OF THE 8216/8226
8080 Data Bus Buffer
The 8080 CPU Data Bus is capable of driving a single TTL
load and is more than adequate for small, single board systems_ When expanding such a system to more than one board
to increase I/O or Memory size, it is necessary to provide a
buffer_ The 8216/8226 is a device that is exactly fitted to
this application.
The 8216/8226 can be used in a wide variety of other buffering functions in microcomputer systems such as Address
Bus Drivers, Drivers to peripheral devices such as printers,
and as Drivers for long length cables to other peripherals or
systems.
Shown in Figure 2 are a pair of 8216/8226 connected directly to the 8080 Data Bus and associated control signals.
The buffer is bi-directional in nature and serves to isolate the
CPU data bus.
On the system side, the DB lines interface with standard
semiconductor I/O and Memory components and are completely TTL compatible. The DB lines also provide a high
drive capability (50mA) so that an extremely large system
can be dirven along with possible bus termination networks.
Do
•
,.
01 OlEN
DB
DO
DBo
DB,
0,
8216
8228
0,
'0
"
,.
'2
0,
On the 8080 side the 01 and DO lines are tied together and
are directly connected to the 8080 Data Bus for bi-directional
operation. The DO outputs of the 8216/8226 have a high
voltage output capability of 3.65 volts which allows direct
connection to the 8080 whose minimum input voltage is
3.3 volts. It also gives a very adequate noise margin of
350mV (worst case).
DB,
'3
DB,
cs
SYSTEM
DATA
8US
,.
8080
01 OlEN
0,
DB
DO
DB,
Os.
0,
8216
8226
The OlEN inputs to 8216/8226 is connected directly to the
8080. OlEN is tied to DBIN so that proper bus flow is
maintained, and CS is tied to BUSEN so that the system
side Data Bus will be 3-stated when a Hold request has been
acknowledged during a DMA activity.
0,
"
,.
'2
0,
'0
DB,
'3
DB,
cs
Memory and 1/0 Interface to a Bidirectional Bus
In large microcomputer systems it is often necessary to provide Memory and I/O with their own buffers and at the same
time maintain a direct, common interface to a bi-directional
Data Bus. The 8216/8226 has separated data in and data
out lines on one side and a common bi-directional set on the
other to accomodate such a function.
Figure 2. 8080 Data Bu. Buffer
Shown in Figure 3 is an example of how the 8216/8226 is
used in this type of appl ication.
MEMORY
The interface to Memory is simple and direct. The memories
used are typically Intel® 8102,81 02A, 8101 or 8107B-4 and
have separate data inputs and outputs. The 01 and DO lines
of the 8216/8226 tie to them directly and under control of
the MEMR signal, which is connected to the 01 EN input,
an interface to the bi-directional Data Bus is maintained.
The interface to I/O is similar to Memory. The I/O devices
used are typically Intel® 8255s, and can be used for both
input and output ports. The I/O R signal is connected directly to the 0 IEN input so that proper data flow from the
I/O device to the Data Bus is maintained_
Figure 3. Memory and 1/0 Intarface
to a Bidirectional Bu.
9·53
I/O
808SA/808SA-2
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSORS
• Four Vectored Interrupt Inputs (One is
non-Maskable) Plus an SOSOAcompatible interrupt
• Single +5V Power Supply
• 100% Software Compatible with SOSOA
• 1.3 J.lS Instruction Cycle (SOS5A);
O.S J.lS (SOS5A-2)
• On-Chip Clock Generator (with External
Crystal, LC or RC Network)
• Serial In/Serial Out Port
• Decimal, Binary and Double Precision
Arithmetic
• On-Chip System Controller; Advanced
Cycle Status Information Available for
Large System Control
• Direct Addressing Capability to 64k
Bytes of Memory
The Intel® 8085A is a complete 8 bit parallel Central Processing Unit (CPU). Its instruction set is 1000/0 software compatible
with the 8080A microprocessor, and it is designed to improve the present 8080A's performance by higher system speed.
Its high level of system integration allows a minimum system of three IC's [8085A (CPU), 8156 (RAM/IO) and 8355/8755A
(ROM/PROM/IO)] while maintaining total system expandability. The 8085A-2 is a faster version of the 8085A.
The 8085A incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) provided for the
8080A, thereby offering a high level of system integration.
The 8085A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The
on-chip address latches of 8155/8156/8355/8755A memory products allow a direct interface with the 8085A.
RST6.5
'T
I
TRAP
I "T'S 1 "TS1
f
IACCUMULAT~~I I
~
TEMP. REG.
III
4'"
I
SERIAL 1/0 CONTROL
8-BIT INTERNAL DATA BUS
J
IN:!~~S;~I~N(8)1
181
l
FLIp· FLOPS
t t
8
'"
REG.
INSTRUCTION
ARITHMETIC
0
REG.
H
REG.
DECODER
LOGIC
AND
UNIT
IAlUI
St 1
0
I
I
INTERRUPT CONTROL
MACHINE
CYCLE
ENCODING
t:::=..
lSi
C
,
{~,.v
l
~~EGISTER
ARRAY
(16)
STACK POINTER
ADDRESS LATCH
(16)
elK
GEN
eLK
~OUT
CONTROL
I
READY
k~
STATUS
AtE
DMA
U I
IJIM
HOLD
(161
LL
TIMING AND CONTROL
X2~
lSi
REG.
INCREMENTER/OECREMENTER
-GND
X,~
181
REG.
lSi
PROGRAM COUNTER
POWER
SUPPLY
(S)I-
REG.
181
H1A
RESET
,---L---,
~
"'SJOUT
I
ADDRESS BUFFER
~
15 •
ADDRESS BUS
RESET IN
Figure 1. 808SA CPU Functional Block Diagram
9·54
_u
181
DATA/ADDRESS BUFFER 1011
~
AD7 ADo
ADDRESS/DATA BUS
8085A18085A-2
vcc
X1
X2
RESET OUT
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
ADo
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
Symbol
HOLD
HLDA
CLK (OUT)
RESET IN
READY
S, can be used as an advanced R/Vii
status. 10/iiii,So and S, become valid
at the beginning of a machine cycle
and remain stable throughout the
cycle. The falling edge of ALE may be
used to latch the state of these lines.
101M
S1
RD
WR
ALE
So
A15
A14
A13
A12
A"
A10
Ag
RD
(Output, 3-state)
READ control: A low level on RD indicates the selected memory or 1/0
device is to be read and that the Data
Bus is available for the data transfer,
3-stated during Hold and Halt modes
and during RESET.
WR
(Output, 3-state)
WRITE control: A low level on WR indicates the data on the Data Bus is to
be written into the selected memory
or 1/0 location. Data is set up at the
trailing edge of WR. 3-stated during
Hold and Halt modes and during
RESET.
READY
(Input)
If READY is high during a read orwrite
cycle, it indicates that the memory or
peripheral is ready to send or receive
data. If READY is low, the cpu will
wait an integral number of clock
cycles for READY to go high before
completing the read or write cycle.
HOLD
(Input)
HOLD indicates that another master
is requesting the use of the address
and data buses. The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as
the completion of the current bus
transfer. Internal processing can continue. The processor can regain the
bus only after the HOLD is removed.
When the HOLD is acknowledged, the
Address, Data, RD, WR, and 101M
lines are 3-stated.
HLDA
(Output)
HOLD ACKNOWLEDGE: Indicates
that the cpu has received the HOLD
request and that it will relinquish the
bus in the next clock cycle. HLDA
goes low after the Hold request is
removed. The cpu takes the bus one
half clock cycle after HLDA goes low.
INTR
(Input)
INTERRUPT REQUEST: is used as a
general purpose interrupt. It is sampled only during the next to the last
clock cycle of an instruction and during Hold and Halt states. If it is active,
the Program Counter (PC) will be inhibited from incrementing and an
INTA will be issued. During this cycle
a RESTART or CALL instruction can
be inserted to jump to the interrupt
service routine. The INTR is enabled
and disabled by software. It is disabled by Reset and immediately after
an interrupt is accepted.
AS
Figure 2. 808SA Pinout Diagram
8085A FUNCTIONAL PIN DEFINITION
The following describes the function of each pin:
Symbol
Function
As-A15
Address Bus: The most significant 8
bits of the memory address or the 8
bits of the 1/0 address, 3-stated during Hold and Halt modes and during
RESET.
(Output, 3-state)
ADo-7
(Input/Output,
3-state)
Multiplexed AddresslData Bus: Lower 8 bits of the memory address (or
1/0 address) appear on the bus during the first clock cycle (T state) of a
machine cycle. It then becomes the
data bus during the second and third
clock cycles.
ALE
(Output)
Address Latch Enable: It occurs during the first clock state of a machine
cycle and enables the address to get
latched into the on-chip latch of peripherals. The falling edge of ALE is
set to guarantee setup and hold times
for the address information. The failing edge of ALE can also be used to
strobe the status information. ALE is
never 3-stated.
So, Sl, and 101M
(Output)
Function
Machine cycle status:
101M S, So Status
-0- "0 T Memory write
o 1 0 Memory read
0 1 1/0 write
1
1
1 0 I/O read
o 1 1 Opcode fetch
1
1 1 Interrupt Acknowledge
o 0 Halt
X X Hold
X X Reset
* = 3-state (high impedance)
X = unspecified
9·55
8085A/8085A,.2
8085A FUNCTIONAL PIN DESCRIPTION (Continued)
Symbol
Function
INTA
(Output)
iNTERRUPT ACKNOWLEDGE: is
used instead of (and has the same
timing as) RD during the Instruction
cycle after an INTR is accepted. It can
be used to activate the 8259 Interrupt
chip or some other interrupt port.
RST 5.5
RST 6.5
RST 7.5
(Inputs)
RESTART INTERRUPTS: These three
inputs have the same timing as INTR
except they cause an internal RESTART to be automatically inserted.
Function
Schmitt-triggered input, allowing
connection to an R-C network for
power-on RESET delay. The cpu is
held in the reset condition as long as
. RESET IN is applied.
The priority of these interrupts is
ordered as shown in Table 1. These
interrupts have a higher priority than
INTR. In addition, they may be individually masked out using the SIM
instruction.
TRAP
(Input)
RESET IN
(Input)
RESET OUT
(Output)
Indicates cpu is being reset. Can be
used as a system reset. The signal is
synchronized to the processor clock
and lasts an integral number of clock
periods.
X1, X2
X1 and X2 are connected to a crystal,
(Input)
lC, or RC network to drive the internal
clock generator. X 1 can also be an
external clock input from a logic gate.
The input frequency is divided by 2 to
give the processor's internal operating frequency.
elK
Clock Output for use as a system
clock. The period of ClK is twice the
X1, X2 input period.
Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at
the same time as INTR or RST 5.5-7.5.
It is unaffected by any mask or Interrupt Enable. It has the highest priority
of any interrupt. (See Table 1.)
(Output)
Sets the Program Counter to zero and
resets the Interrupt Enable and HlDA
flip-flops. The data and address buses
and the control lines are 3-stated during RESET and because of the asynchronous nature of RESET, the processor's internal registers and flags
may be altered by RESET with unpredictable results. RESET IN is a
SID
(Input)
Serial input data line. The data on this
line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
SOD
(Output)
Serial output data line. The output
SOD is set or reset as specified by the
SIM instruction.
Vee
Vss
+5 volt supply.
Ground Reference.
TABLE 1. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY
Name
Priority
Address Branched To (1)
When Interrupt Occurs
Type Trigger
Rising edge AND high level until sampled.
1
24H
RST 7.5
2
3CH
Rising edge (latched).
RST 6.5
3
34H
High level until sampled.
TRAP
RST 5.5
4
2CH
High level until sampled.
INTR
5
See Note (2).
High level until sampled.
NOTES:
(1) The processor pushes the PC on the stack before branching to the indicated address.
(2) The address branched to depends on the instruction provided to the cpu when the interrupt is
acknowledged.
9·56
808SA/808SA-2
set until the request is serviced. Then it is reset automatically. This flip-flop may also be reset by using the
SIM instruction or by issuing a RESET IN to the 8085A.
The RST 7.5 internal flip-flop will be set by a pulse on the
RST 7.5 pin even when the RST 7.5 interrupt is masked out.
FUNCTIONAL DESCRIPTION
The 8085A is a complete 8-bit parallel central processor.
It is designed with N-channel depletion loads and requires
a single +5 volt supply. Its basic clock speed is 3 MHz
(8085A) or 5 MHz (8085A-2), thus improving on the present
8080A's performance with higher system speed. Also it is
designed to fit into a minimum system of three IC's: The
cpu (8085A), a RAM/IO (8156), and a ROM or EPROM/IO
chip (8355 or 8755A).
The status of the three RST interrupt masks can only be
affected by the SIM instruction and RESET IN. (See SIM,
Chapter 4.)
The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than
one is pending as follows: TRAP - highest priority,
RST 7.5, RST 6.5, RST 5.5, INTR - lowest priority. This
priority scheme does not take into account the priority
of a routine that was started by a higher priority interrupt.
RST 5.5 can interrupt an RST 7.5 routine if the interrupts
are re-enabled before the end of the RST 7.5 routine.
The 8085A has twelve addressable 8-bit registers. Four of
them can function only as two 16-bit register pairs. Six
others can be used interchangeably as 8-bit registers or
as 16-bit register pairs. The 8085A register set isas follows:
Mnemonic
Register
Contents
ACCorA
Accumulator
8 bits
PC
Program Counter
16-bit address
BC,DE,HL
General-Purpose
Registers; data
pointer (HL)
8 bits x 6 or
16 bits x 3
SP
Stack Pointer
16-bit address
Flags or F
Flag Register
5 flags (8-bit space)
The TRAP interrupt is useful for catastrophic events such
as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest
priority. It is not affected by any flag or mask. The TRAP
input is both edge and level sensitive. The TRAP input
must go high and remain high until it is acknowledged.
It will not be recognized again until it goes low, then high
again. This avoids any false triggering due to noise or
logic glitches. Figure 3 illustrates the TRAP interrupt
request circuitry within the 8085A. Note that the servicing
of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR)
disables all future interrupts (except TRAPs) until an EI
instruction is executed.
The 8085A uses a multiplexed Data Bus. The address is
split between the higher 8-bit Address Bus and the lower
8-bit Address/Data Bus. During the first T state (clock
cycle) of a machine cycle the low order address is sent
out on the Address/Data bus. These lower 8 bits may be
latched externally by the Address Latch Enable signal
(ALE). During the rest of the machine cycle the data bus is
used for memory or I/O data.
The 8085A provides RD, WR, So, S1, and 10iM signals for
bus control. An Interrupt Acknowledge signal (INTA) is
also provided. HOLD, READY, and all Interrupts are synchronized with the processor's internal clock. The 8085A
also provides Serial Input Data (SID) and Serial Output
Data (SOD) lines for simple serial interface.
EXTERNAL
TRAP
INTERRUPT
REQUEST
INSIDE THE
BOS5A
TRAP
,,-,RE:::S~ET-.::'N~-I--l SCHMITT
TRIGGER
In addition to these features, the 8085A has three maskable, vector interrupt pins and one nonmaskable TRAP
interrupt.
+5V
0
elK
D
INTERRUPT AND SERIAL I/O
FIF
The 8085A has 5 interrupt inputs: INTR, RST 5.5, RST6.5,
RST 7.5, and TRAP. INTR is identical in function to the
8080A INT. Each of the three RESTART inputs, 5.5, 6.5,
and 7.5, has a programmable mask. TRAP is also a
RESTART interrupt but it is nonmaskable.
INTERNAL
TRAP
ACKNOWLEDGE
TRAP F.F.
Figure 3. TRAP and RESET IN Circuit
The three maskable interrupts cause the internal execution of RESTART (saving the program counter in the stack
and branching to the RESTART address) if the interrupts
are enabled and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a
RESTART vector independent of the state of the interrupt enable or masks. (See Table 1.)
There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are high level-sensitive like
INTR (and INT on the 8080) and are recognized with the
same timing as INTR. RST 7.5 is rising edge-sensitive.
The TRAP interrupt is special in that it disables interrupts,
but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were
enabled or disabled prior to the TRAP. All subsequent
RIM instructions provide current interrupt enable status.
Performing a RIM instruction following INTR, or RST
5.5-7.5 will provide current Interrupt Enable status,
revealing that Interrupts are disabled. See the description of the RIM instruction in Chapter 4.
For RST 7.5, only a pulse is required to set an internal
flip-flop which generates the internal interrupt request.
(See Section 2.2.7.) The RST 7.5 request flip-flop remains
The serial I/O system is also controlled by the RIM and
SIM instructions. SID is read by RIM, and SIM sets the
SOD data.
9-57
8085A/8085A-2
To minimize variations in frequency. it is recommended
that you choose a value for C ex! that is at least twice that
of Cint. or 30 pF. The use of an LC circuit is not recommended for frequencies higher than approximately5 MHz.
DRIVING THE X1 AND X21NPUTS
You may drive the clock inputs of the 8085A or 8085A-2
with a crystal. an LC tuned circuit. an RC network. or an
external clock source. The driving frequency must be at
least 1 MHz. and must be twice the desired internal clock
frequency; hence. the 8085A is operated with Ii 6 MHz
crystal (for 3 MHz clock). and the 8085A-2can be operated
with a 10 MHz crystal (for5 MHz clock). If a crystal is used.
it must have the following characteristics:
An RC circuit may be used as the frequency-determining
network for the 8085A if maintaining a precise clock frequency is of no importance. Variations in the on-chip
timing generation can cause a wide variation in frequency
when using the RC mode. Its advantage is its low component cost. The driving frequency generated by the
circuit shown is approximately 3 MHz. It is not recommended that frequencies greatly higher or lower than this
be attempted.
Parallel resonance at twice the clock frequency desired
CL (load capacitance) s; 30 pf
Cs (shunt capacitance) S; 7 pf
Rs (equivalent shunt resistance) S; 75 Ohms
Drive level: 10 mW
Frequency tolerance: ±.005% (suggested)
Figure 4 shows the recommended clock driver circuits.
Note in D and E that pullup resistors are required to assure
that the high level voltage of the input is at least 4 V.
Note the use of the 20 pf capacitors between Xl. X2 and
ground. These capacitors are required with crystal frequencies below 4 MHz to assure oscillator startup at the
correct frequency. A parallel-resonant LC circuit may be
used as the frequency-determining network forthe8085A.
providing that its frequency tolerance of approximately
±10% is acceptable. The components are chosen from
the formula:
x,
For driving frequencies up to and including 6 MHz you
may supply the driving signal to Xl and leave X2 opencircuited (Figue4D).lfthe driving frequency is from 6 MHz
to 10 MHz. stability of the clock generator will be improved
by driving both Xl and X2 with a push-pull source (Figure
4E). To prevent self-oscillation of the 8085A. be sure that
X2 is not coupled back to Xl through the driving circuit.
808SA
----,
+5V
I
I
..,..
2
Low time> 60 ns
47011
TO
C 1NT
.J.. ~'SpF
lKI1
I
I
/
X,
x, _ _ _ ....JI
*20 pF CAPACITORS REQUIRED FOR
CRYSTAL FREQUENCY,.; 4 MHz ONLY.
A. Quartz Crystal Clock Driver
x,
----,
808SA
'X2lEFT FLOATING
D. 1-6 MHz Input Frequency External Clock Driver
Circuit
I
I C 1NT
.......
-L.. ""15pF
ceXT
I
X,_ _ _
.-II
+5V
Low time> 40 ns
B. LC Tuned Circuit Clock Driver
47011 /
»-+---'---1 X,
.....-_....-_ _ _-1' x,
I
1-::-20pF
808SA
'1
-'OK
~
47011
'------II- X,
E. 1-10 MHz Input Frequency External Clock Driver
Circuit
C. RC Circuit Clock Driver
Figure 4. Clock Driver Circuits
9·58
8085A/8085A-2
GENERATING AN 8085A WAIT STATE
The 8085A cpu can also interface with the standard
memory that does not have the multiplexed address/data
bus. It will require a simple 8212 (8-bit latch) as shown in
Figure 8.
If your system requirements are such that slow memories
or peripheral devices are being used, the circuit shown in
Figure 5 may be used to insert one WAIT state in each
8085A machine cycle
The 0 flip-flops should be chosen so that
• ClK is rising edge-triggered
• CLEAR is low-level active.
----
SOS5A
CLEAR
A l E - ClK
TO
ClK OUTPUT --. ClK
SOS5A
"0"
"0"
FfF
FfF
+5V-D
1-°'"-------10
-
nD~
TRAP
X,
r! !
RESET IN
HOLD
RST7,S
HLDA
RST6,S
SOD
8085A
RST5,5
ADDR
I-
r-
ISID
S,I-
I-
INTR
lIiITA
s.r-
RESET
OUT
ADDA/
DATA ALE AD WA 101M
ROY elK
181
READY
INPUT
~o-.
X,
Vss Vee
181
VI'
T
~ POR~W
:h-
WR
PORT
ALE
PORT
R0 8l56 8
DATAl
C
ADDR
Figure 5. Generation of a Wait State for 808SA CPU
IN
101M
As in the 8080, the READY line is used to extend the read
and write pulse lengths sothatthe 8085A can be used with
slow memory. HOLD causes the cpu to relinquish the bus
when it is through with it by floating the Address and Data
Buses.
TIMER
OUT
RESET
W
8
II
W
(6)
--
r-
lOW
RO
ALE
Itt-
SYSTEM INTERFACE
I
The 8085A family includes memory components, which
are directly compatible to the 8085A cpu. For example, a
system consisting of the three chips, 8085A, 8156, and
8355 will have the following features:
PORT
A
CE
"- %10
~;:::
fN
8355/
8755A
V
DATAl
ADDR
p-.
• 2K Bytes ROM
• 256 Bytes RAM
• 1 Timer/Counter
.
101M
~
elK
PORT
B
RESET
iOR
s!v!c vto
V
• 4 8-bit I/O Ports
~
Vee
- - ROY
---1
tROG
Vee
Vee
• 1 6-bit I/O Port
Vee
• 4 Interrupt levels
• Serial In/Serial Out Ports
V
V
*NQTE: OPTIONAL CONNECTION
This minimum system, using the standard I/O technique
is as shown in Figure 6.
Figure 6. 808SA
Technique)
In addition to standard I/O, the memory mapped I/O
offers an efficient I/O addressing technique. With this
technique, an area of memory address space is assigned
for I/O address, thereby, using the memory address for
I/O manipulation. Figure 7 shows the system configuration of Memory Mapped I/O using 8085A.
9-59
Minimum
System
(Standard
I/O
808SA/808SA-2
8OS5A MINIMUM SYSTEM CONFIGURATION
:)
A8-16
~
A
ADO-7
~).
~
ALE
8085A
RD
-
elK
-
RESET OUT
READY
i
I
I.
iTIMER
RESET
T6~~R
-
-
WR
101M
I
WARD
IN
AD
ALE
eE ' (
O~7
:~~V~-~
101M
_10/
CE
M
I
I·
I
ALE
FfDlrow elK RSTIRDY
_
8355 [ROM + I/0j
OR
8755A [PROM + I/0j
8156
[RAM + I/O + COUNTERITIMER]
*NOTE: OPTIONAL CONNECTION
BBtt
88
Figure 7. MCS-85'· Minimum System (Memory Mapped I/O)
----
TRAP
X,
X,
RESET IN
HOLD
RST7
HLDA
ASrG
SOD
808SA
RST5
SID
---
s,_
INTR
RESET
INTA
SOOUT
OAT A ALE RO WR 101M
ROY eLK
ADDA/
AODR
(.(
(.(
101M (es)
WR
8212
I-
RO
DATA
~
I
STANDARD
MEMORY
ADDR (es)
V
(16)
......
elK
RESET
10/M (es)
I/O POR TS,
WR
RO
DATA
STANDARD
~
I/O
ADDR
~~I
II
T
Vee
vee
Vee
Figure 8. MCS-85'· System (Using Standard Memories)
9·60
lS
Vee
Vee
Vee
SOS5A/S085A-2
BASIC SYSTEM TIMING
TABLE 2. SOS5A MACHINE CYCLE CHART
The BOB5A has a multiplexed Data Bus. ALE is used as a
strobe to sample the lower B-bits of address on the Data
Bus. Figure 9 shows an instruction fetch, memory read
and 1/0 write cycle (as would occur during processing of
the OUT instruction). Note that during the I/O write and
read cycle that the 1/0 port address is copied on both the
upper and lower half of the address.
I
MACHINE CYCLE
OPCODE FETCH
MEMORY READ
MEMORY WR ITE
I/O READ
I/O WRITE
CONTROL
5T':.TU5
IO/M 51
(OFI
(MRI
(MWI
(IORI
(IOWI
0
0
0
1
1
1
1
0
1
0
(INAI
(SII
DAD
ACK OF
RST,TRAP
HALT
1
0
1
1
1
1
T5
a
50
RD
WR
INTA
1
0
0
0
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
TS
T5
1
1
ACKNOWLEDGE
OF lNTR
BUS IDLE
There are seven possible types of machine cycles. Which
of these seven takes place is defined by the status of the
three status lines (101M, S1, So) and the three control
signals (RD, WR, and INTA). (See Table 2.) The status
lines can be used as advanced controls (for device selection, for example), since they become active at the T1
state, at the outset of each machine cycle. Control lines
RD and WR become active later, at the time when the
transfer of data is to take place, so are used as command
lines.
a
1
0
TABLE 3. SOS5A MACHINE STATE CHART
Status & Buses
Machine
State
51,50 10/M
Control
IA8-A'~~~o-AD7 Ri),Wii INTA ALE
A machine cycle normally consists of three T states, with
the exception of OPCODE FETCH, which normally has
either four or six T states (unless WAIT or HOLD states
are forced by the receipt of READY or HOLD inputs). Any
T state must be one of ten possible states, shown in
Table 3.
T,
X
X
T2
X
X
TWAIT
T3
T4
X
X
I
1
I
X
1
1
l'
X
i
X
X
X
X
I
! x I
I x
at I X
X
X
X
a
a
X
X
X
X
0
1
1
0
I
I
I
TS
1
a
1
0
TS
TS
1
0
TS
TS
TS
TS
0' I
X
TS
I
1
0'
i
X
TS
!
X
TS
TS
0
TS
TS
I
THALT
I
THOLD
I
X
I
!
TS
TS
I
I
i
1
I 1
T6
0'" LogiC "0"
1 = LogiC "1"
~
I
I
X
!
Ts
T RESET
I
1
I
0
: i
TS'" High Impedance
X '" Unspecified
ALE not generated during 2nd and 3rd machme cycles of DAD Instruction
t IO!M '" 1 dUring T4 - T6 of INA machine cycle.
M,
M,
elK
As -A'5
ADo_7
M3
T,
PC H (HIGH ORDER ADDRESS)
PC L
{pC
+ 1}H
~----
(LQWORDER
ADDRESS)
DATA FROM
MEMORY
(INSTRUCTION)
ALE
RD
WR
101M
STATUS
1
10 (READ)
5,50 (FETCH)
Figure 9. SOS5A Basic System Timing
9·61
01 WRITE
11
0
i~
8085A/8085A-2
TABLE 4. ABSOLUTE MAXIMUM RATINGS·
'COMMENT
Ambient Temperature Under Bias ......... o°c to 70°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
Voltage on Any Pin
With Respect to Ground ............ -0.5V to +7V
Power Dissipation. . . . . . . . . . . . . . . . . .
1.5 Watt
Stresses above thoselisted,under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
TABLE 5. D.C. CHARACTERISTICS
(TA
;
O°C to 70°C; Vce ; 5V ±5%; VSS ; OV; unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Max.
Units
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vec-+O· 5
V
VOL
Output Low Voltage
0.45
V
IOL; 2mA
VOH
Output High Voltage
V
IOH ; -400JlA
V IL
2.4
lee
Power Supply Current
170
mA
IlL
Input Leakage
±10
JlA
Vin = Vee
ILO
Output Leakage
±10
JLA
0.45V .;; V out .;; Vee
VILR
Input Low Level, RESET
-0.5
+0.8
V
2.4
Vee +0.5
V
V IHR
Input High Level, RESET
VHY
Hysteresis, RESET
V
0.25
9·62
808SA/808SA-2
TABLE 6. A.C. CHARACTERISTICS
TA=0·Ct070·C; Vcc=5V ±5%; Vss=OV
8085A·2[21
(Preliminary)
8085A[21
Symbol
Parameter
Min.
Max.
Min.
Max.
320
2000
200
2000
Units
tCYC
CLK Cycle Period
f1
ClK low Time -
Standard 150 pF loading
Lightly loaded[S]
80
100
40
ns
ns
t2
ClK High Time -
Standard 150 pF loading
Lightly loaded[S]
120
150
70
ns
ns
t r , tf
ClK Rise and Fall Time
30
ns
tXKR
X1 Rising to ClK Rising
30
120
30
100
ns
tXKF
X1 Rising to ClK Falling
30
150
30
110
ns
tAC
AS- 15 Valid to leading Edge of Control[1]
270
115
tACL
AO_7 Valid to leading of Control
240
115
tAO
AO- 15 Valid to Valid Data In
30
575
ns
ns
ns
350
ns
0
ns
tAFR
Address Float after leading Edge of READ (INTA)
tAL
AS- 15 Valid before Trailing Edge of AlE[1]
tALL
AO-7 Valid before Trailing Edge of ALE
tARY
READY Valid from Address Valid
tCA
Address (As-A15) Valid after Control
120
60
ns
tcc
Width of Control low (RD, WR, INTA) Edge of ALE
400
230
ns
tCL
Trailing Edge of Control to leading Edge of ALE
50
25
ns
tow
Data Valid to Trailing Edge of WRITE
420
230
tHABE
HlDA to Bus Enable
210
150
ns
tHABF
Bus Float after HlDA
210
150
ns
tHACK
HlDA Valid to Trailing Edge of ClK
tHOH
HOLD Hold Time
tHOS
HOLD Setup Time to Trailing Edge of ClK
tlNH
INTR Hold Time
tiNS
INTR, RST, and TRAP Setup Time to Falling Edge of ClK
tLA
Address Hold Time after ALE
100
50
tLC
Trailing Edge of ALE to leading Edge of Control
130
60
tLCK
ALE low during ClK High
100
50
tLOR
ALE to Valid Data during Read
460
270
ns
tLow
ALE to Valid Data during Write
200
120
ns
tLL
ALE Width
tLRY
ALE to READY Stable
0
115
50
90
50
220
ns
100
ns
ns
110
40
0
0
ns
170
120
ns
0
0
ns
160
150
ns
140
ns
ns
I
ns
ns
80
110
9·63
ns
ns
30
ns
808SA/808SA-2
TABLE 6. A.C. CHARACTERISTICS (Cont.)
Symbol
8085A-2[2)
(Preliminary)
8085A[2):
Parameter
Min.
tRAE
Trailing Edge of READ to Re-Enabling
of Address
tRD
READ (or INTA) to Valid Data
tRY
Control Trailing Edge to leading Edge
of Next Control
tRDH
Data Hold Time After READ INTA
tRYH
READY Hold Time
tRYS
Max.
150
Min.
90
300
Units
Max.
ns
150
ns
400
220
0
0
ns
0
0
ns
READY Setup Time to leading Edge
of ClK
110
100
ns
tWD
Data Valid After Trailing Edge of WRITE
100
tWDL
lEADING Edge of WRITE to Data Valid
[7)
ns
60
40
ns
20
ns
Notes:
_
1. Aa-A15 address Specs apply to 101M, SQ, and S1 except Aa-A15 are undefined during T4-T6 of OF cycle whereas 101M, SQ, and
S1 are stable.
2. Test conditions: tCYC = 320ns (B085A)/200ns (BOB5A-2); CL = 150pF.
3. For all output timing where CL = 150pF use the following correction factors:
25pF oS CL '" 150pF: -0.10 ns/pF
150pF < CL oS 300pF: +0.30 ns/pF
4. Output timings are measured with purely capacitive load.
5. All timings are measured at output voltage VL = O.BV, VH = 2.0V, and 1.5V with 20ns rise and fall time on inputs.
6. To calculate timing specifications at other values of tCYC use Table 7.
7. Data hold time is guaranteed under all loading conditions.
8. Loading equivalent to 50 pF + 1 TTL input.
9-64
808SA/808SA-2
TABLE 7. BUS TIMING SPECIFICATION AS A TCYC DEPENDENT
8085A-2 (Preliminary)
8085A
tRO
-
tRAE
-
tAL
tLA
tLL
t LCK
t LC
tAO
-
tCA
tow
two
tcc
tCL
t ARy
t HACK
tHABF
tHABE
tAC
(1/2) T -45
MIN
tAL
(1/2) T - 60
MIN
tLA
(1/2) T - 20
MIN
tLL
(1/2) T - 60
MIN
t LCK
-
t LC
-
(1/2) T - 40
MIN
MAX
tAO
-
MAX
(3/2+N)T-180
(1/2) T -10
MAX
tRO
-
(5/2 + N) T -150
(3/2+N)T-150
MIN
tRAE
-
(1/2) T -10
MIN
(112) T - 40
MIN
tCA
-
(112) T - 40
MIN
(312 + N) T - 60
MIN
tow
MIN
MIN
two
(1/2) T - 40
MIN
(3/2 + N) T - 80
MIN
tcc
(312 + N) T - 70
MIN
(112) T - 110
MIN
tCL
(1/2) T -75
MIN
(3/2) T - 260
MAX
t ARy
(3/2) T - 200
MAX
(1/2) T - 50
MIN
t HACK
(1/2) T - 60
MIN
(1/2) T + 50
MAX
tHABF
(1/2) T + 50
MAX
(1/2) T + 50
MAX
tHABE
(2/2) T - 50
MIN
tAC
tl
-
(3/2 + N) T - 70
(1/2) T - 60
MIN
t2
MIN
tRY
-
(3/2) T - 80
MIN
t LOR
-
(4/2) T - 180
MAX
t2
tRY
t LOR
N is equal to the total WAIT states.
~
MIN
MIN
MIN
(1/2) T - 80
T
MIN
(112) T - 20
(1/2) T - 50
(1/2) T - 30
(1/2) T - 40
NOTE:
MIN
(5/2 + N) T - 225
-
tl
(1/2) T - 50
(1/2) T - 50
NOTE:
~
(1/2)T + 50
MAX
(2/2) T - 85
MIN
(1/2) T - 60
MIN
(1/2) T - 30
MIN
(3/2) T - 80
MIN
(4/2) T - 130
MAX
N is equal to the total WAIT states.
T ~ tCYC.
tCYC.
X,INPUT
elK
OUTPUT
I_-----tcvc
Figure 10. Clock Timing Waveform
9-65
MAX
------_1
808SA/808SA-2
Read Operation
T,
ClK \
__
TZ
1
1
_J/r---}_----If-~\. . . ._
_J/
~'LeK5
)l
\ ......._
_JJ
_teA_
ADDRESS
tAD~
<1!!!
ADDRESS
>-
r r-
I---'LA-
t l l ---.
t AFR -------
ALE
.-- t AL ----..
RDilNTA
-
'Ae
Write Operation
}
.
.1
,'t
I
T2
}
,.,.
.if£
I
tRO
'ee
/
/t+--tLCK~
T-'RAE-
~'eL-y
J:
I
T,
ClK\
DATA IN
tlDR
.
~tLC--·
$ff)i
tRDH ......
\
I
T3
\
/
,'eA--i
!---'LOWADDRESS
r
J
J{.
ADDRESS
)
T,
~
DATAQUT
!-- t l l ---.. -'LA~
______ t wo ---'-
'ow
--- I--'WOL
ALE
1/
I--'AL'ee
~'L=1
. - - t el --.
t AC - - - - + -
Read operation with Walt Cycle (Typical) -
same READY timing applies to WRITE operation.
T,
T2
eLK
/ -'LCK
)
J
\
ADDRESS
)
.
~
f--tu-
- t lA tAFR_
_tAL_
RD/INTA
-
#//J)!
.
tAo
tce
'i
_I
,Y-
-
tRYS
~,
I
I
Figure 11. 808SA Bus Timing, With and Without Walt
9·66
r--
""
DATA IN
- teL
~tlRY -'---0tAC _____________
tARY
] ___ t RAE tRDH -..
tLOR
I
_tlC-:-~
READY
il
ADDRESS
ALE
j
_tCA_
tAO
ADo-AD,
T,
T3
TWAtT
1'---
-1
808SA/808SA-2
Hold Operation
T,
T,
:\
\
elK
t
HOLD
t HDS ...
T HOLD
/
1
~tHDH
(ADDRESS, CONTROLS)
T,
/
:~
r-tHACK ....
t
HLDA
BUS
T HOLD
'\
tHABF-fo-
l=HABE-
>--\
Figure 12. 808SA Hold Timing.
T,
A8_15=]========:====~--------------f
A°0-7
---'..>.--~
BUS FLOATING*
-------1
~,-----------1-----~--------------~~--Jr---------
HOLD
HlDA
-<-101M IS ALSO FLOATING DURING THIS TIME.
Figure 13. 808SA Interrupt and Hold Timing
9·67
8085A/8085A-2
TABLE 8. INSTRUCTION SET SUMMARY
Mnemonic
Deseriplion
MOVE. LOAD. AND STORE
MOVrl r2
Move register to register
MOV M.r
Move register to memory
MOV r.M
Move memory to register
MVI r
Move Immediate register
MVI M
Move lmmed,ate memory
LXI B
load Immediate register
LXIO
LXI H
LXI SP
Pair B & C
Load Immediate register
Pair 0 & E
Load Immediate register
Pair H & L
Load Immedlale Slack
InSlruelion Codelll
Cloekl21
07 06 05 04 03 oz 01 00 Cycles
CPE
CPO
D D D
1
10
10
RNC
RZ
RNZ
RP
RM
RPE
RPO
10
10
10
STAX
STAX
LOAX
LOAX
STA
LOA
SHLO
LHLO
XCHG
B
0
B
0
STACK OPS
PUSH B
PUSH 0
PUSH H
PUSH PSW
POP B
POP 0
POP H
POP PSW
XTHL
SPHL
JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
PCHL
CALL
CALL
CC
CNC
CZ
CNZ
CP
CM
Store A mdlrect
Store A Indirect
Load A Indlrecl
Load A Indlrecl
Siore A dlrecl
Load A dlrecl
Siore H & L direct
Load H & L direci
Exchange 0 & E H & L
Registers
Push reg ISler Pair B &
C on Slack
Push reg Isler Pair 0 &
E on slack
Push reglsler Pair H &
L on slack
Push A and Flags
on stack
Pop register Pair B &
C 011 slack
Pop reg Isler Pair 0 &
E 011 Slack
Pop reglSIer Pair H &
L 011 Slack
Pop A and Flags
011 Slack
Exchange lop of
slack. H & L
H & L 10 slack pOIOIer
07 06
Inslruelion Codl(ll
lis 04 03 OZ 01
I
0
Do
Relu,"
Return on ca fry
Return on no carry
Return on zero
10
6112
6112
6112
6112
6112
6112
6112
6112
Return on panty even
Relu," on panly odd
1 0
Reslarl
A
IN PUT/OUTPUT
Inpul
IN
Oulpul
OUT
12
A
0
0
10
10
1
INCREMENT AND DECREMENT
INR r
Increment register
OCR r
Decrement register
INR M
Increment memory
DCA M
Decrement memory
INX B
Incremenl B & C
registers
INX D
Incremenl D & E
registers
INX H
Incremenl H & L
registers
13
13
16
16
12
12
12
INX SP
OCX B
OCX 0
OCX H
OCX SP
12
10
10
CloeklZI
Cyel ..
9118
9118
0
Return on no zero
Return on posItive
Return on minus
RESTART
RST
pOinter
oeseriplion
Call on panly even
Calion panly odd
RETURN
RET
RC
D
0
1 0
Mnemor.ic
10
10
6
Increment stack pomter
Decrement B & C
Decrement 0 & E
Decremenl H & L
Decrement stack
pOinter
ADO
ADD r
AOC r
10
10
ADD M
ADC M
16
AOI
ACI
Jump uncondil,onal
Jump on carry
Jump on no carry
Jump on zero
Jump on no zero
Jump on pos;llve
Jump on minus
Jump on panly even
Jump aD panty odd
H & L 10 program
counter
10
71tO
7110
7110
DAD
DAD
DAD
DAD
7110
7110
7110
7110
SUBTRACT
SUB r
Call uncondilional
Call on carry
Call on no carry
Call on zero
Call on no zero
Call on positive
Callan minus
t8
9118
9118
9118
9118
9118
9118
B
0
H
SP
SBB r
7110
6
SUB M
SBB M
SUI
SBI
LOGICAL
ANA I
9·68
Add reglsler 10 A
Add register to A
with carry
Add memory to A
Add memory 10 A
with carry
Add Immediate to A
Add Immediate 10 A
with carry
Add B & C 10 H & L
Add 0 & E 10 H & L
Add H & L 10 H & L
Add slack pOlnler 10
H&L
Sublract reg Isler
from A·
Sublracl reg Isler from
A wllh borrow
Sublracl memory
from A
Subtract memory from
A with borrow
Subtract Immediate
from A
Sublract 1m media Ie
from A with borrow
And reglsler wllh A
1
0
10
10
10
10
1 0
1 0
1 0
0 S S S
808SA/808SA-2
TABLE 8. INSTRUCTION SET SUMMARY (Continued)
Inslruclion Codelll
Clockl11
D) D6 D5 D4 D3 D1 DI Do Cycles
Mnemonic
Description
XRA r
Exclusive Or leglster
with A
Or register with A
Compare regISter with A
And memory with A
ORA r
CMPr
ANA M
XRA M
ORA M
CMP M
ANI
XRI
ORI
CPI
ROTATE
RLC
RRC
NOTES
I
Mnemonic
Description
Inslruction Codell J
D) D6 D5 D4 D3 D1 DI
RAL
Rolate A left through
0
RAR
1
Rotate A IIqht througll
carry
Exclusive Or memory
with A
Or memory with A
Compare memory with A
And Immediate with A
ExclusIve Or Immediate
with A
Or Immediate with A
Compare Immediate
with A
SPECIALS
CMA
STC
CMC
DAA
Complement A
Set carry
Complement carry
Decimal adjust A
CONTROL
EI
01
NOP
HLT
Enable Interrupts
Disable Interrupt
No-operation
Halt
NEW 8085A INSTRUCTIONS
RIM
Read Interrupt Mask
SIM
Set Interrupt Mask
Rotate A left
Rotate A light
DOD or SSS B 000. C 001.0 010. E 011. H 100 L 101 Memory 110 A 111
Two possible cycle times. (6/12) indicate Instruction cycles dependent on condition flags
*AII mnemonics copynght
1
carry
©Intel Corporation 1977
9·69
0
1
Do
Ciockl1J
Cycles
inter
8155/8156/8155-2/8156-2
2048 BIT STATIC MOS RAM WITH I/O PORTS AND TIMER
8085A
8085A-2
8155
8156
8155-2
8156-2
~
CPU
Chip
Enable
ACTIVE LOW
ACTIVE HIGH
• 256 Word x 8 Bits
•
1 Programmable 6-Bit 1/0 Port
•
•
Programmable 14-Bit Binary Counterl
Timer
Single +5V Power Supply
• Completely Static Operation
• Multiplexed Address and Data Bus
• Internal Address Latch
• 2 Programmable 8 Bit 1/0 Ports
• 40 Pin DIP
The 8155 and 8156are RAM and I/O chips to be used in the MCS-85'" microcomputer system. The RAM portion is designed
with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit use with no wait states
in 8085A CPU. The 8155-2 and 8156-2 have maximum access times of 330 ns for use with the 8085A-2.
The 1/0 portion consists of three general purpose 1/0 ports. One of the three ports can be programmed to be status pins,
thus allowing the other two ports to operate in handshake mode.
A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse for
the CPU system depending on timer mode.
PIN CONFIGURATION
PC,
vee
pc.
pc,
TIMER IN
pel
RESET
pC s
PC.
PB,
TIMERolit
PBs
101M
PBs
BLOCK DIAGRAM
101M
256 X 8
ADo 1
CE OR ce-
PB.
AD
PB,
STATIC
RAM
*
G
pa., .,
G
ALE
VIR
PB,
ALE
PB,
RD
AD.
PB.
W"R--
AD,
PA,
AD,
PAs
AD,
PAs
AD.
PA.
ADs
PA,
AD.
PA,
AD,
PA,
v"
PA.
RESET
TIMER
TIMER CLK
TIMER OUT
*: 8155/8155-2 =
9-70
PAo' 7
CE, 8156/8156·2 = CE
PC o- s
G
Lvcc
/+SV)
Vss IOVI
8155/8156/8155-2/8156-2
8155/8156 PIN FUNCTIONS
.$y~
RESET
(input)
ADo-7
(input)
~
Pulse provided by the 8085A to initialize the system (connect to 8085A
RESET OUT). Input high on this line
resets the chip and initializes the
three I/O ports to input mode. The
width of RESET pulse should typically
be two 8085A clock cycle times.
3-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The 8-bit address is
latched into the address latch inside
the 8155/56 on the fall i ng edge of
ALE. The address can be either for
the memory section or the 110 section
depending on the 10/M input. The
8-bit data is either written into the
chip or read from the chip, depending
on the WR or RD input signal.
CE or CE
(input)
Chip Enable: On the 8155, this pin is
CE and is ACTIVE LOW. On the 8156,
this pin is CE and is ACTIVE HIGH.
RD
(input)
Read control: Input low on this line
with the Chip Enable active enables
and ADo-7 buffers. If 10/M pin is low,
the RAM content will be read out to
the AD bus. Otherwise the content
of the selected I/O port or command/
status registers will be read to the
AD bus.
WR
(input)
Write control: Input low on this line
with the Chip Enable active causes
the data on the Address/Data bus to
be written to the RAM or I/O ports and
command/status register depending
on 101M'.
9-71
l!y.!!!l!2!
Function
ALE
(input)
Address Latch Enable: This control
signal latches both the address on the
ADo-7 lines and the state of the Chip
Enable and 10/M into the chip at the
falling edge of ALE.
10/M
(input)
Selects memory if low and 110 and
commandlstatus registers if high.
PAO-7(8)
(input/output)
These 8 pins are general purpose I/O
pins. The in/out direction is selected
by programming the command
register.
PBo-7(8)
(input/output)
These 8 pins are general purpose 110
pins. The inlout direction is selected
by programming the command
register.
peo-5(6)
(input/output)
These 6 pins can function as either
input port, output port, or as control
signals for PA and PB. Programming
is done through the command register. When PCO-5 are used as control
Signals, they will provide the following:
PCo - A INTR (Port A Interrupt)
PC1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupti
PC4 - B BF (Port B Buffer Full I
PC5 - B STB (Port B Strobe I
TIMER IN
(input)
Input to the counter-timer.
TIMER OUT
(output)
Timer output. This output can be
either a square wave or a pulse depending on the timer mode.
Vce
+5 volt supply.
Vss
Ground Reference.
8155/8156/8155-2/8156-2
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TemperatureUnderBias ................ O°Cto+70°C
Storage Temperature ............... -65°Cto+150°C
Voltage on Any Pin
With Respect to Ground ............... -O.5V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
(TA = o°c to 70°C; Vee = 5V ± 5%)
MAX.
UNITS
-0.5
0.8
V
2.0
Vee+O· 5
V
0.45
V
SYMBOL
PARAMETER
MIN.
V'L
Input Low Voltage
V'H
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
TEST CONDITIONS
I,L
Input Leakage
±10
p.A
= 2mA
IoH = -400j.tA
V'N = Vee to OV
ILO
Output Leakage Current
±10
p.A
0.45V .;;; VOUT .;;; Vee
Icc
Vee Supply Current
180
mA
"L(CE)
Chip Enable Leakage
8155
8156
+100
-100
!J.A
!J.A
V
2.4
9·72
ioL
V'N
= Vee to OV
8155/8156/8155-2/8156-2
A.C. CHARACTERISTICS
(TA = o°c to 70°C; VCC = 5V ± 5%1
8155/8156
SYMBOL
PARAMETER
MIN.
MAX.
8155-2/8156-2
(Preliminary)
MIN.
MAX.
UNITS
tAL
Address to Latch Set Up Time
50
30
ns
tlA
Address Hold Time after Latch
80
30
ns
tlC
Latch to R EAD/WR ITE Control
100
40
tRO
Valid Data Out Delay from READ Control
170
tAD
Address Stable to Data Out Valid
400
tll
Latch Enable Width
tROF
Data Bus Float After READ
0
tCl
R EAD/WR ITE Control to Latch Enable
20
10
ns
ns
100
ns
140
ns
330
ns
ns
70
100
0
80
ns
tcc
READ/WRITE Control Width
250
200
tow
Data In to WRITE Set Up Time
150
100
ns
two
Data In Hold Time After WR ITE
0
0
ns
tRV
Recovery Time Between Controls
300
twp
WR ITE to Port Output
tpR
Port Input Setup Time
70
50
ns
tRP
Port Input Hold Time
50
10
ns
tSBF
Strobe to Buffer Full
tss
Strobe Width
tRBE
READ to Buffer Empty
400
300
tSI
Strobe to INTR On
400
300
ns
tROI
READ to INTR Off
400
300
ns
ns
200
400
300
400
200
300
ns
ns
ns
150
ns
tpss
Port Setup Time to Strobe Strobe
50
0
ns
tPHS
Port Hold Time After Strobe
120
100
ns
tSBE
Strobe to Buffer Empty
400
300
ns
tWBF
WR ITE to Buffer Full
400
300
ns
tWI
WR ITE to INTR Off
400
300
ns
tTL
TIMER-IN to TIMER-OUT Low
400
300
ns
tTH
TIMER-IN to TIMER-OUT High
300
ns
tROE
Data Bus Enable from READ Control
10
10
ns
t1
TIMER-IN Low Time
80
40
ns
t2
TIMER-IN High Time
120
70
ns
400
9-73
8155/8156/8155-2/8156-2
WAVEFORMS
8.
Read Cycle
(
\
"
/
\~
CE 18155 I
DR
If-
CE 18156 I
I
V
\
101M
\
'AD
X
7
__
AL E
,
ADDRESS
t
AL
_
)< I.-
r
DATA VALID
~
~tlA-
If-
/
\
r-------
1- t RDE ..
t lL- - -
-
'ROF-
.1
~tRD_
-'le-I~
/
tcc~
--'el
- t RV
U
b. Write Cycle
\
CE 18155I
\
-,
OR
I
CE 18156I
\
101M
X
AD...7
I
/
,v
\
ADDRESS
I--ALE
~\.
'Al-
I---
'lA--
K X
-4------
tow - - - -
~\
---
t lL -
J(
DATA VALID
~'el-
-,V
- - t LC
-----...1
-two~
-,1
(.....-- t cc
Figure 1. 8155/8156 Read/Write Timing Diagrams
9·74
-
I---'RV-
"--
8155/8156/8155-2/8156-2
e. Strobed Input Mode
/
BF
tSBF
'~,,_-21__ ~
tRBE
\ \-;3 /
INTA
\
I--'pss
INPUT DATA
FAOMPOAT
X
/
j
t pHS
~
b. Strobed Output Mode
BF
INTA
'WP
OUTPUT
DATA ________________________________
TOPOAT
~~
Figure 2. Strobed 1/0 Timing
9·75
______________________________________________________
8155/8156/8155-2/8156-2
a. Basic Input Mode
DATA BUS'
===== ___________
~
~
b. Basic Output Mode
WR
DATA BUS*
OUTPUT
"DATA BUS TIMING IS SHOWN IN FIGURE 7.
Figure 3. Basic 1/0 Timing Waveform
I
LOAD COUNTER FROM CLR
2
I
1
---1
RElOAD COUNTER FROM CLR
I
2
I
1
1
TIMER IN
TIMER OUT
(PULSE)
TIMER OUT
(SQUARE WAVE)
\
\\
1) J "
...... (NOTE
___
(NOTE 11
'- _ _ _ _ _ _ _ _ J
I
I
NOTE 1: THE TIMER OUTPUT ISPERIQDIC IF IN AN AUTOMATIC
RELOAD MODE (M 1 MODE BIT '" 1)
Figure 4. Timer Output Waveform Countdown from 5 to 1
9-76
_I
inter
*Compatible with SOS5A
"'*Compatible with 8OS5A-2
• Multiplexed Address and Data Bus
• Low Standby Power Dissipation
• Directly Compatible with 808SA
Microprocessor
• Single +SV Supply
• Low Operating Power Dissipation
• High Density 18-Pln Package
The Intel@ 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using N-channel
Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface directly to the 8085A
microprocessor to provide a maximum level of system integration
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185.
PIN CONFIGURATION
ADO
Vee
AD,
RD
AD,
W-
BLOCK DIAGRAM
cs
AD,
ALE
AD,
cs
CE,
AD,
CE,
ADs
CE,
AD
W-
AD,
A.
Vss
AS
CE,
R/W
LOGIC
ALE
J
~
V
DATA
BUS
BUFFER
1K x 8
RAM
MEMvRY
ARRAY
x·y DECODE
PIN NAMES
t..
ADDRESS/DATA LINES
ADDRESS LINES
CHIP SELECT
CHIP ENABLE (101M)
CHIP ENABLE
ADDRESS LATCH ENABLE
As.
A.
ALE
READ ENABLE
WAITE ENABLE
9-77
1:'
ADDRESS
LATCH
~T
8185/8185-2
OPERATIONAL DESCRIPTION
The 8185 has been designed to provide for direct interface
to the multiplexed bus structure and bus timing of the
8085A microprocessor.
----
At the beginning of an 8185 memory access cycle, the 8bit address on ADo-7, As and A9, and thestatusofCEl and
CE2 are all latched internally in the 8185 by the falling edge
of ALE. If the latched status of both CEl and CE2 are
active, the 8185 powers itself up, but no action occurs until
the CS Iine goes low and the appropriate R 0 or WR control
signal input is activated.
TRAP
x,
III
x,
RESET IN
R8T7,5
HOLD
HlDA
RST6,5
SOD
8085A
RST5,5
INTR
lNTA
ADDR
ADDRI
DATA ALE i!D
(8)
The Cs input is not latched by the 8185 in order to allow
the maximum amount of time for address decoding in
selecting the 8185 chip. Maximum power consumption
savings will occur, however, only when CEl and CE2 are
activated selectively to power down the 8185 when it is not
in use. A possible connection would be to wire the 8085A's
10iM' line to the 8185's CEl input, thereby keeping the
8185 powered down during liD and interrupt cycles.
.. "
Vss Vee
r1D~
WIi
--
CE 2
CS
(CS·)12)
1
X
X
0
i
,',
"
,f,~,<':
" ,,\I
\':
."
"."
SID '-S,_
S. ___
RESET
OUT
101M
ROY elK
vi' vr
(8)
~ POR~¢y
~-
WR
PORT ¢8)y
(
i!D 8156 B
ALE
PORT
DATAl
c
ADOR
IN
101M TIMeR
RESET
OUT
~
(6)
:::
lOW
TABLE 1.
TRUTH TABLE FOR
POWER DOWN AND FUNCTION ENABLE
CE l
' ,',
"
AD
ALE
~-
8185 Status
~=
Power Down and
Function Disable[l)
CE
-"
PORT
A
W
A e.10
8355/
8755A
V
DATAl
ADDR
X
X
0
0
Power Down and
Function Disable[l)
101M
\
PORT
RESET
0
1
1
0
Powered Up and
Function Disablell)
0
1
0
1
Powered Up and
Enabled
~
elK
WR
AD
eE, 8185
ALE
/-f-
es, CE 2
H-
As .A9
TABLE 2.
TRUTH TABLE FOR
CONTROL AND DATA BUS PIN STATUS
A°0-7
v!s v!c
Vee
During Data
-WR ADo-7
Portion of Cycle' 8185 Function
RD
0
X
X Hi-Impedance
1
0
1
Data from Memory Read
1
1
0
Data to Memory
Write
1
1
1
Hi-Impedance
Reading, but not
Driving Data Bus
~
vs! v!c vto tROG
Notes:
X: Don't Care.
1: Function Disable implies Data Bus in high impedance state
and not writing.
2: CS' = (CEl = 0) • (CE2 = 1) • (CS = 0)
CS· = 1 signifies all chip enables and chip select active
(CS·)
B
ROY
Vee
No Function
Figure 1. 8185 In an MCS-85 System.
4 Chips:
2K Bytes ROM
1 .25K Bytes RAM
38 I/O Lines
1 Counter/Timer
2 Serial I/O Lines
5 I nterrupt Inputs
Note:
X: Don't Care.
9·78
8185/8185-2
ABSOLUTE MAXIMUM RATINGS*
·COMMEI.,
Temperature Under Bias .............. O°C to +70°C
Storage Temperature .............. -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .............. -0.5V to +7V
Power Dissipation .....•....................... 1.5W
D.C. CHARACTERISTICS
Stresses above those listed under "Absolute Maximum>"
permanent damage to the device. This is a stress rating 0
operation of the device at these or any other conditio
indicated in the operational sections of this specification
Exposure to absolute maximum rating conditions for extende!bp
may affect device reliability.
':'~ .
DLYADJ (Input)
Delay-Adjust is used for connection of an external
capacitor and resistor to ground to adjust the required
set~up and hold time of address to control signal.
__
,:
',.'
'1~
I': ~:/:...
BREQ is used for requesting the bus ~n"priority"~
decided by a parallel priority resolver circuit', ..... '.: .' "'"
the
BPRO is used to allow lower priority devices to gain·
bus when a serial priority resolving structure is used.
BPRO would go to '!WAN of the next lower priority Master.
8218/8219 FUNCTIONAL DESCRIPTION
When priority is granted to the Master (a low on BPRN and
a high on BUSY) the Master outputs a BUSY signal on the
next falling edge of BCLK. The BUSY signal locks the
master onto the bus and prohibits the enable of any other
masters onto the bus.
The 8218/8219 is a bipolar Bus Control Chip which
reduces component count in the interface between a
master device and the system Bus. (Master device: 8080,
8085, 8257 (oMAU
At the same time BUSY goes active, Address and Data
Enable (ADEN) goes active signifying that the Master has
control of the bus. ADEN is often used to enable the bus
drivers.
The 8218 and 8219 serve three major functions:
1. Resolve bus contention.
2. Guarantee set-up and hold time of address/data lines
to I/O and Memory read/write control signals
(adjustable by external capacitor).
3. Provide sufficient drive on all bus command lines.
The Bus will be released only ifthe master loses priority; is
not in the middle of a transfer, and Override is not active
or, if the Master stops requesting the bus, is not in the
middle of a data transfer, and Override is not active. ADEN
then goes inactive.
Bus Arbitration Logic
Provision has been made in the 8218 to allow bussynchronous requests. This mode is activated when
BCR1, BCR2 and RSTB are all low. This action
asynchronously sets the synchronization flip flop (FF2) in
Figure 1a.
J:jus Arbitration Logic activity begins when the Master
makes a request for use of the bus on BCR1 or BCR2. The
request is strobed in by RSTB. Following the next two
falling edges of the bus clock (BCLK) the 8218/8219
OVRIDE
BCRI
BCR2
-
I/
'
-
.=u-
11
I J~
.J
SET
.....
.....
Q
~
ASYNCH.
REQUEST
SET
Q
D
SYNCH.
REQUEST
PRIORITY
ANO
REQUEST
lOGIC
FFI
FF2
elK
ClR
I~)
I
ClR
~
FIGURE 11. 8218 BUS ARBITRATION LOGIC
9·83
8218/8219
OVRIDE
BCR1
BeR2
J-
1
SET
./
Q
D
ASYNCH,
REQUEST
Q
D
SYNCH.
REQUEST
PRIORITY
AND
REQUEST
LOGIC
FF2
FFl
,-----c
CLK
CLK
CLR
CLR
1
FIGURE lb. 8219 BUS ARBITRATION LOGIC
Timing Logic
Timing Logic activity begins with the rising edge of XSTR
(Transfer Start Request) or with ADEN going active,
whichever occurs second. This action causes XCV
(Transfer Cycle) to go active. 50-200ns later (depending on
resistance and capacitance at DL YADJ) the appropriate
Control Outputs will go active if the control input is active.
MADe
MRDR
i'OlfR
OUTPUT
CONTROL
LOGIC
iiiiWfR
lowe
IOWR
XSTR can be raised after the command goes active in the
current transfer cycle so that a new transfer can be
initiated immediately after the current transfer is
complete.
IORC
MWTC
ANYR
A negative going edge on XCP (Transfer Complete) will
cause the Control Outputs (MRDC, etc') to go inactive.
50-200ns later (depending on capacitance at DL YADJ)
XCV will go inactive indicating the transfer cycle is
completed.
CONTROL
OUTPUT
INACTIVE
SET
Additional logic within the 8218/8219 guarantees that if a
transfer cycle is started (XCY is active), but the bus is not
requested microcomputer systems.
After being initialized by software, the 8257 can transfer a
block of data, containing up to 16,384 bytes, between
memory and a peripheral device directly, without further
intervention required of the CPU. Upon receiving a DMA
transfer request from an enabled peripheral, the 8257:
1. DMA Channels
1. Acquires control of the system bus.
2. Acknowledges that requesting peripheral which is
connected to the highest priority channel.
3. Outputs the least significant eight bits of the memory
address onto system address lines Ao-A7, outputs
the most significant eight bits ofthe memory address
to the 8212 1/0 port via the data bus (the 8212
places these address bits on lines As·A,s), and
The 8257 provides four separate DMA channels (labeled
CH-O to CH-3). Each channel includes two sixteen-bit
registers: (1) a DMA address register, and (2) a terminal count register. Both registers must be initialized
before a channel is enabled. The DMA address register is
loaded with the address of the first memory location to be
accessed. The value loaded into the low-order 14-bits of
the terminal count register specifies the number of DMA
cycles minus one before the Terminal Count (TC) output
is activated. For instance, a terminal count of 0 would
cause the TC output to be active in the first DMA cycle for
that channel. In general, if N = the number of desired DMA
cycles, load the value N-1 into the low-order 14-bits of the
terminal count register. The most significant two bits of the
terminal count register specify the type of DMA operation
for that channel.
4. Generates the appropriate memory and I/O read/
write control signals that cause the peripheral to
receive or deposit a data byte directly from or to the
addressed location in memory.
The 8251 will retain control of the system bus and repeat
the transfer sequence, as long as a peripheral maintains its
DMA request. Thus, the 8257 can transfer a block of data
to/from a high speed peripheral (e.g., a sector of data on a
floppy disk) in a single "burst". When the specified
number of data bytes have been transferred, the 8257
activates its Terminal Count (TC) output, informing the
CPU that the operation is complete.
The 8257 offers three different modes of operation:
(1) DMA read, which causes data to be transferred from
memory to a peripheral; (2) DMA write, which causes
data to be transferred from a peripheral to memory;
and (3) DMA verify, which does not actually involve the
transfer of data. When an 8257 channel is in the DMA verify
mode, it will respond the same as described for transfer
operations, except that no memory or I/O read/write
control signals will be generated, thus preventing the
transfer of data. The 8257, however, will gain control of the
system bus and will acknowledge the peripheral's DMA
request for each DMA cycle. The peripheral can use these
acknowledge signals to enable an internal access of each
byte of a data block in order to execute some verification
procedure, such as the accumulation of a CRC (Cyclic
Redundancy Code) checkword. For example, a block of
DMA verify cycles might follow a block of DMA read cycles
(memory to peripheral) to allow the peripheral to verify its
newly acquired data.
Figure 1. 8257 Block Diagram Showing DMA
Channels
9·93
U2571U257·5
These two bits are not modified during a DMA cycle, but
can be changed between DMA blocks.
BIT 15
BIT 14
TYPE OF DMA OPERATION
Each channel accepts a DMA Request (DROn) input and
provides a DMA Acknowledge (DACKn) output.
0
0
0
1
0
1
Verily DMA Cycle
Write DMA Cycle
Read DMA Cycle
(Illegal)
(ORO O-ORO 3)
DMA Request: These are individual asynchronous channel request inputs used by the peripherals to obtain a DMA
cycle. If not in the rotating priority mode then ORO 0 has
the highest priority and ORO 3 has the lowest. A request
can be generated by raising the request line and holding it
high until DMA acknowledge. For multiple DMA cycles
(Burst Mode) the request line is held high until the DMA
acknowledge of the last cycle arrives.
(OACK 0 - OACK 3)
DMA Acknowledge: An active low level on ,the acknowl·
edge output informs the peripheral connected to that
channel that it has been selected for a DMA cycle. The
DACK output acts as a "chip select" for the peripheral
device requesting service. This line goes active (low)
and inactive (high) once for each byte transferred even if
a burst of data is being transferred.
2, Data BUB Butler
This three-state, bi-directional, eight bit buffer interfaces
the 8257 to the system data bus.
(0 0-0 7)
Data Bus Lines: These are bi-directional three-state lines.
When the 8257 is being programmed by the CPU, eightbits of data for a DMA address register, a terminal count
register or the Mode Set register are received on the data
bus. When the CPU reads a DMA address register, a
terminal count register or the Status register, the data is
sent to the CPU over the data bus. During DMA cycles
(when the 8257 is the bus master), the 8257 will output the
most significant eight-bits of the memory address (from
one of the DMA address registers) to the 82121atch via the
data bus. These address bits will be transferred at the
beginning of the DMA cycle; the bus will then be released
to handle the memory data transfer during the balance of
the DMA cycle.
Figure 2. 8257 Block Diagram Showing Data Bus
Buffer
9·94
825718257·5
3. ReadIWrlte logic
(Ao-A31
When the CPU is programming or reading one of the
8251's registers (i.e., when the 8257 is a "slave" device on
the system bus), the ReadlWrite logic accepts the I/O
Read (mm) or I/O Write (l7OW) signal, decodes the least
significant four address bits, (Ao·A3), and either writes
the contents of the data bus into the addressed register
(if I/OW is true) or places the contents of the addressed
register onto the data bus (if iiOR is true).
Address Lines: These least significant four address lines
are bi-directional. In the "slave" mode they are inputs
which select one of the registers to be read or
programmed. In the "master" mode, they are outputs
which constitute the least significant four bits of the 16-bit
memory address generated by the 8257.
During DMA cycles (i.e., when the 8257 is the bus
"master"), the Read/Write logic generates the I/O read
and memory write (DMA write cycle) or I/O Write and
memory read (DMA read cycle) signals which control the
data link with the peripheral that has been granted the
DMA cycle.
Chip Select: An active-low Input which enables the I/O
Read or I/O Write input when the 8257 is being read or
programmed in the "slave" mode. In the "master" mode,
CS is automatically disabled to prevent the chip from
selecting itself while performing the DMA function.
Note that during DMA transfers Non-DMA I/O devices
should be de-selected (disabled) using "AEN" signal to
inhibit I/O device decoding of the memory address as an
erroneous device address.
I/O Read: An active-low, bi-directional three-state line. In
the "slave" mode, it is an input which allows the 8-bit
status register or the upper/lower byte of a 16-bit DMA
address register or terminal count register to be read. In
the "master" mode, I/OR is a control output which is used
to access data from a peripheral during the DMA write
cycle.
(1I0W)
I/O Write: An active-low, bi-directional three-state line. In
the "slave" mode, it is an input which allows the contents
of the data bus to be loaded into the 8-bit mode set register
or the upper/lower byte of a 16-bit DMA address register
or terminal count register. In the "master" mode, I/OW is a
control output which allows data to be output to a
peripheral during a DMA read cycle.
(elK)
Clock Input: Generally from an Intel@ 8224 Clock Gen·
erator device. (c/l2 TTL) or Intel@ 8085A ClK output.
(RESET)
Reset: An asynchronous input (generally from an 8224
or 8085 device) which disables all DMA channels by
clearing the mode register and 3·states all control lines.
Figure;,. 8257 Block Diagram Showing
Read/Write Logic Function
9·95
8257/8257·5
4. Control Logic
(TC)
This block controls the sequence of operations during all
DMA cycles by generating the appropriate control signals
and the 16-bit address that specifies the memory location
to be accessed.
Terminal Count: This output notifies the currently
selected peripheral that the present DMA cycle should be
the last cycle for this data block. If the TC STOP bit in the
Mode Set register is set, the selected channel will be
automatically disabled at the end of that DMA cycle. TC is
activated when the 14-bit value in the selected channel's
terminal count register equals zero. Recall that the loworder 14-bits of the terminal count register should be
loaded with the values (n-1), where n =thedesired number
of the DMA cycles.
(A4-A7)
Address Lines: These four address lines are three-state
outputs which constitute bits 4 through 7 of the 16-bit
memory address generated by the 8257 during all DMA
cycles.
(READy)
(MARK)
Ready: This asynchronous input is used to elongate the
memory read and write cycles in the 8257 with wait states
if the selected memory requires longer cycles.
Modulo 128 Mark: This output notifies the selected
peripheral that the current DMA cycle is the 128th cycle
since the previous MARK output. MARK always occurs at
128 (and all multiples of 128) cycles from the end of the
data block. Only if the total number of DMA cycles (n) is
evenly divisable by 128 (and the terminal count register
was loaded with n-1), will MARK occur at 128 (and each
succeeding multiple of 128) cycles from the beginning of
the data block.
(HRQ)
Hold Request: This output requests control of the system
bus. In systems with only one 8257, HRQ will normally be
applied to the HOLD input on the CPU.
(HLDA)
Hold Acknowledge: This input from the CPU indicates
that the 8257 has acquired control of the system bus.
(MEMR)
Memory Read: This active-low three-state output is used
to read data from the addressed memory location during
DMA Read cycles.
Memory Write: This active-low three-state output is used
to write data into the addressed memory location during
DMA Write cycles.
(ADSTB)
Address Strobe: This output strobes the most significant
byte of the memory address into the 8212 device from the
data bus.
(AEN)
Address Enable: This output is used to disable (float) the
System Data Bus and the System Control Bus. It may also
be used to disable (float) the System Address Bus by use
of an enable on the Address Bus drivers in systems to
inhibit non-DMA devices from responding during DMA
cycles. It may be further used to isolate the 8257 data bus
from the System Data Bus to facilitate the transfer of the 8
most significant DMA address bits over the 8257 data 1/0
pins without subjecting the System Data Bus to any
timing constraints for the transfer. When the 8257 is used
in an 1/0 device structure (as opposed to memory
mapped), this AEN output should be used to disable the
selection of an 1/0 device when the DMA address is on the
address bus. The 1/0 device selection should be
determined by the DMA acknowledge outputs for the 4
channels.
Figure 4. 8257 Block Diagram Showing Control Logic
and Mode Set Register
9-96
8257/8257·5
5. Mode Set Register
Note that rotating priority will prevent anyone channel
from monopolizing the DMA mode; consecutive DMA
cycles will service different channels if more than one
channel is enabled and requesting service. There is no
overhead penalty associated with this mode of opera·
tion. All DMA operations began with Channel 0 initially
assigned to the highest priority for the first DMA cycle.
When set, the various bits in the Mode Set register enable
each of the four DMA channels, and allow four different
options for the 8257:
16543210
~"ffl
Enable. A U T O L O A D ' n a b l e . DMA Channel 0
Enables TC STOP
Enables DMA Channel 1
Enables EXTENDED WRITE
Enables DMA Channel 2
En,bles ROTATING PRIORITY
Enables DMA Channel 3
Extended Write Bit 5
r
If the EXTENDED WRITE bit is set, the duration of both the
MEMW and IIOW signals is extended by activating them
earlier in the DMA cycle. Data transfers within microcomputer systems proceed asynchronously to allow
use of various types of memory and 1/0 devices with
different access times. If a device cannot be accessed
within a specific amount of time it returns a "not ready"
indication to the 8257 that causes the 8257 to insert one or
more wait states in its internal sequencing. Some devices
are fast enough to be accessed without the use of wait
states, but if they generate their READY response with the
leading edge of the I/OW or MEMW signal (which
generally occurs late in the transfer sequence), they
would normally cause the 8257 to enter a wait state
because it does not receive READY in time. For systems
with these types of devices, the Extended Write option
provides alternative timing for the 1/0 and memory write
signals which allows the devices to return an early READY
and prevents the unnecessary occurrence of wait states in
the 8257, thus increasing system throughput.
The Mode Set register is normally programmed by the
CPU after the DMA address register(s) and terminal
count register(s) are initialized. The Mode Set Register is
cleared by the RESET input, thus disabling all options,
inhibiting all channels, and preventing bus conflicts on
power-up. A channel should not be left enabled unless its
DMA address and terminal count registers contain valid
values; otherwise, an inadvertent DMA request (DROn)
from a peripheral could initiate a DMA cycle that would
destroy memory data.
The various options which can be enabled by bits in the
Mode Set register are explained below:
Rotating Priority Bit 4
In the Rotating Priority Mode, the priority of the channels
has a circular sequence. After each DMA cycle, the
priority of each channel changes. The channel which had
just been serviced will have the lowest priority.
TC Stop Bit 6
If the TC STOP bit is set, a channel is disabled (i.e., its
enable bit is reset) after the Terminal Count (TC) output
goes true, thus automatically preventing further DMA
operation on that channel. The enable bit for that channel
must be re-programmed to continue or begin another
DMA operation. If the TC STOP bit is not set, the
occurrence of the TC output has no effect on the channel
enable bits. In this case, it is generally the responsibility of
the peripheral to cease DMA requests in order to terminate
a DMA operation.
If the ROTATING PRIORITY bit is not set (set to a zero),
each DMA channel has a fixed priority. In the fixed priority
mode,.Channel 0 has the highest priority and Channel 3
has the lowest priority. If the ROTATING PRIORITY bit is
set to a one, the priority of each channel changes after
each DMA cycle (not each DMA request). Each channel
moves up to the next highest priority assignment, while
the channel which has just been serviced moves to the
lowest priority assignment:
CHANNEL--' CH-O CH-1 CH-2 CH-3
JUST SERVICED
Priority _
As.lgnments
Highest
t
Lowest
CH-1
CH-2
CH-3
CH-O
CH-2
CH-3
CH-O
CH-1
CH-3
CH-O
CH-1
CH-2
CH-O
CH-1
CH-2
CH-3
Auto Load Bit 7
The Auto Load mode permits Channel 2 to be used for
repeat block or block chaining operations, without
immediate software intervention between blocks. Channel 2 registers are initialized as usual for the first data
block; Channel 3 registers, however, are used to store the
block re-initialization parameters (DMA starting address,
terminal count and DMA transfer mode). After the first
block of DMA cycles is executed by Channel 2 (i.e., after
the TC output goes true), the parameters stored in the
Channel 3 registers are transferred to Channel 2 during an
"update" cycle. Note that the TC STOP feature, described
above, has no effect on Channel 2 when the Auto Load bit
is set.
9·97
8257/8257·5
If the Auto Load bit is set, the initial parameters for
Channel 2 are automatically duplicated in the Channel 3
registers when Channel 2 is programmed. This permits
repeat block operations to be set up with the programming
of a single channel. Repeat block operations can be used
in applications such as CRT refreshing. Channels 2 and 3
can still be loaded with separate values if Channel 2 is
loaded before loading Channel 3. Note that in the Auto
Load mode, Channel 3 is still available to the user if the
Channel 3 enable bit is set, but use of this channel will
change the values to be auto loaded into Channel 2 at
update time. All that is necessary to use the Auto Load
feature for chaining operations is to reload Channel 3
registers at the conclusion of each update cycle with the
new parameters for the next data block transfer.
TC STATUS FOR CHANNEL 0
iC STATUS FOR CHANNEL 1
' - - - - - ' T C STATUS FOR CHANNEL 2
' - - - - - - ' T C STATUS FOR CHANNEL 3
The TC status bits are set when the Terminal Count (TCI
output is activated for that channel. These bits remain set
until the status register is read or the 8257 is reset. The
UPDATE FLAG, however, is not affected by a status
register read operation. The UPDATE FLAG can be
cleared by resetting the 8257, by changing to the non-auto
load mode (i.e., by reseUing the AUTO LOAD bit in the
Mode Set register) or it can be left to clear itself at the
completion of the update cycle. The purpose of the
UPDATE FLAG is to prevent the CPU from inadvertently
skipping a data block by overwriting a starting address or
terminal count in the Channel 3 registers before those
parameters are properly auto-loaded into Channel 2.
Each time that the 8257 enters an update cycle, the update
flag in the status register is set and parameters in Channel
3 are transferred to Channel 2, non-destructively for
Channel 3. The actual re-initialization of Channel 2 occurs
at the beginning of the next channel 2 DMA cycle after the
TC cycle. This will be the first DMA cycle of the new data
block for Channel 2. The update flag is cleared at the
conclusion of this DMA cycle. For chaining operations,
the update flag in the status register can be monitored by
the CPU to determine when the re-initialization process
has been completed so that the next block parameters can
be safely loaded into Channel 3.
The user is cautioned against reading the TC status
register and using this information to reenable chan·
nels that have not completed operation. Unless the
DMA channels are inhibited a channel could reach ter·
minal count (TCI between the status read and the mode
write. DMA can be inhibited by a hardware gate on the
HRQ line or by disabling channels with a mode word
before reading the TC status.
6. Status Register
The eight-bit status register indicates which channels
have reached a terminal count condition and includes the
update flag described previously.
I;
..
'"
_I PARAMETERS
FOR BLOCK 1
(CH 2)
i-I
PARAMETERS
FOR BLOCK 3
(CH 3)
I
1-
-IETC----CHANNEL 2 UPDATE
OCCURS HERE
110 WRITE
DRQ2
•
n n n n __
_
_ _ _ _ _.UUUL
J.--OATA BLOCK
'-I
TC
UPDATE FLAG
Figure 5. Autoload Timing
9·98
8257/8257·5
OPERATIONAL SUMMARY
CONTROL INPUT
CS
IIOW
IIOR
A3
Program Half 01 a
Channel Register
0
0
1
0
Read Hall of a
Channel Register
0
1
0
0
Program Mode Set
Register
0
0
1
1
Read Status Register
0
1
0
1
Programming and Reading the 8257 Registers
There are four pairs of "channel registers": each pair
consisting of a 16-bit DMA address register and a 16-bit
terminal count register (one pair for each channel). The
8257 also includes two "general registers": one 8-bit
Mode Set register and one 8-bit Status register. The
registers are loaded or read when the CPU executes a
write or read instruction that addresses the 8257 device
and the appropriate register within the 8257. The 8228
generates the appropriate read or write control signal
(generally IIOR or IIOW while the CPU places a 16-bit
address on the system address bus. and either outputs the
data to be written onto the system data bus or accepts the
data being read from the data bus. All or some of the most
significant 12 address bits A4-A 15 (depending on the
systems memory. 1/0 configuration) are usually decoded
to produce the chip select (CS) input to the 8257. An 1/0
Write input (or Memory Write in memory mapped 1/0
configurations. described below) specifies that the
addressed register is to be programmed. while an 1/0
Read input (or Memory Read) specifies that the addressed
register is to be read. Address bit 3 specifies whether a
"channel register" (AJ = 0) or the Mode Set (program
only)/Status (read only) register (A3 = 1) is to be accessed.
The least significant three address bits. Ao-A2. indicate the
specific register to be accessed. When accessing the
Mode Set or Status register. Ao-A2 are all zero. When
accessing a channel register bit Ao differentiates between
the DMA address register (Ao = 0) and the terminal count
register (Ao = 1). while bits AI and Az specify one of the
four channels. Because the "channel registers" are 16bits. two program instruction cycles are required to load
or read an entire register. The 8257 contains a first/last
(F/L) flip flop which toggles at the completion of each
channel program or read operation. The F/L flip flop
determines whether the upper or lower byte of the register
is to be accessed. The F/L flip flop is reset by the RESET
input and whenever the Mode Set register is loaded. To
maintain proper synchronization when accessing the
"channel registers" all channel command instruction
operations should occur in pairs. with the lower byte of a
register always being accessed first. Do not allow CS to
clock while either IIOR or IIOW is active. as this will cause
an erroneous F/L flip flop state. In systems utilizing an
interrupt structure. interrupts should be disabled prior to
any paired programming operations to prevent an
interrupt from splitting them. The result of such a split
would leave the F/L F/F in the wrong state. This problem is
particularly obvious when other DMA channels are
programmed by an interrupt structure.
8257 Register Selection
-BI-DIRECTIONAL DATA BUS
ADDRESS INPUTS
REGISTER
BYTE
CH-O DMA Address
FIL
0,
06
Os
04
03
O2
0
A7
A6
A"
A,
A15
AD
A,
A\2
A]
All
A,
Alo
Al
A,
A"
As
C,
Rd
C6
Wr
CD
C,
CI2
C]
CII
C,
CiO
CI
C,
Co
Cs
EW
RP
EN3
EN2
ENl
ENO
0
UP
TC3
TC2
TCl
TCO
A3
A2
Al
Ao
LSB
MSB
0
0
0
0
0
0
0
0
0
1
LSB
MSB
0
0
0
0
0
0
1
1
0
LSB
MSB
0
0
0
0
1
1
0
0
0
1
CH-1 Terminal Count
LSB
MSB
0
0
0
0
1
1
1
1
0
1
CH-2 DMA Addr•••
LSB
MSB
0
0
1
1
0
0
0
0
0
1
CH-2 Termlna' Count
LSB
MSB
0
0
1
1
0
0
1
1
0
1
CH-3 DMA Addr•••
LSB
MSB
0
0
1
1
1
1
0
0
0
1
CH-3 Terminal Count
LSB
MSB
0
0
1
1
1
1
1
1
0
1
-
1
0
0
0
0
Al
TCS
1
0
0
0
0
0
0
CH-O Terminal Count
CH-1 DMA Addre••
MODE SET (Program only)
STATUS (Read only)
1
C,
1
Do
Same as Channel 0
I I I
Same •• Channel 0
I I I
Same •• Channel 0
-Ao-A15: DMA Starting Address. Co-C,,: Terminal Count value (N-1), Rd and Wr: DMA Verify (00). Write (01) or Read (10) cycle selection.
AL: Auto Load. TCS: TC STOP. EW: EXTENDED WRITE, RP: ROTATING PRIORITY. EN3-ENO: CHANNEL ENABLE MASK. UP: UPDATE
FLAG. TC3-TCO: TERMINAL COUNT STATUS BITS.
9-99
8257/8257·5
read and write commands and byte transfer occurs between the selected I/O device and memory. After the
transfer is complete, the DACR" line is set HIGH and the
HRO line is set LOW to indicate to the CPU that the bus
is now free for use. ORO must remain HIGH untii DACK
is issued to be recognized and must go LOW before 54
of the transfer sequence to prevent another transfer
from occuring. (See timing diagram.)
RESET
J
SI
Di!Q,;
SAMPLE ORon LINES
SET HAQ IF OROn = 1
,-
iDRon
I
n
SO
SAMPLE HLDA
SAMPLE OROn LINES
Consecutive Transfers
If more than one channel requests service simultaneously, the transfer will occur in the same way a burst does.
No overhead is incurred by switching from one channel
to another. In each 54 the DRO lines are sampled and
the highest priority request is recognized during the
next transfer. A burst mode transfer in a lower priority
channel will be overridden by a higher priority request.
Once the high priority transfer has completed control
wiil return to the lower priority channel if its ORO is still
active. No extra cycles are needed to execute this sequence and the HRO line remains active untii all ORO
lines go'LOW.
I..HiDA
RESOLVE OROn PRIORITIES
l
--
HLDA· ORQ"
S1
PRESENT AND LATCH
UPPER ADDRESS
PRESENT LOWER ADDRESS
~
Control Override
S2
ACTIVATE READ COMMAND
ADVANCED WRITE COMMAND
AND DACKn
~.
.....-
S3
ACTIVATE WRITE COMMAND
ACTIVATE MARK AND Te
READY .
I VERIF~
IF APPROPR 11\ rE
~ READY + VERIFY
SW
SAMPLE
READY
~
LINE
"-r-LREADY
S4
RESET ENABLE FOR CHANNel N IF
Te STOP AND Te ARE ACTIVE.
DEACTIVATE COMMANDS.
~ DEACTIVATE OACKn, MARK AND Te.
SAMPLE OROn AND HLOA.
DROn· HLOA
RESOLVE OROn PRIORITIES.
RESET HAG IF HLDA
l
The continuous DMA transfer mode described above
can be Interrupted by an external device by lowering the
HLOA line. After each OMA transfer the 8257 samples
the HLOA line to Insure that it is still active. if it is not
active, the 8257 completes the current transfer, releases
the HRO line (LOW) and returns to the idle state. If ORO
lines are stiil active the 8257 will raise the HRO line in
the third cycle and proceed normally. (See timing
diagram.)
=0 OR ORO = O.
Not Ready
The 8257 has a Ready input similar to the 8080A and the
8085A. The Ready line is sampled in State 3. If Ready is
LOW the 8257 enters a wait state. Ready is sampled during every wait state. When Ready returns HIGH the 8257
proceeds to State 4 to complete the transfer. Ready is
used to interface memory or I/O devices that cannot
meet the bus set up times required by the 8257.
HlDA + OROn
1 DRQn refers to any ORO line on an enabled DMA channel.
Figure 6. DMA Operation State Diagram
Speed
The 8257 uses four clock cycles to transfer a byte of
data. No cycles are lost in the master to master transfer
maximizing bus efficiency. A 2MHz clock input will
allow the 8257 to transfer at a rate of 500K bytes/second.
Memory Mapped I/O Configurations
DMA OPERATION
Single Byte Transfers
A single byte transfer is initiated by the I/O device rais·
ing the ORO line of one channel of the 8257. If the channel is enabled, the 8257 will output a HRO to the CPU.
The 8257 now waits until a HLOA is received insuring
that the system bus is free for its use. Once HLOA is
received the ~ line for the requesting channel is activated (LOW). The OACK line acts as a chip select for
the requesting I/O device. The 8257 then generates the
The 8257 can be connected to the system bus as a memory
device instead of as an I/O device for memory mapped I/O
configurations by connecting the system memory control
lines to the 8257's i/O control lines and the system I/O
control lines to the 8257's memory control lines.
This configuration permits use of the 8080's considerably
larger repertOire of memory instructions when reading or
loading the 8257's registers. Note that with this
connection. the programming of the Read (bit 15) and
Write (bit 14) bits in the terminal count register will have a
different meaning:
9-100
8257/8257 ·5
A"
I
I
A.
r--
ALE
r---!.!
STB
DO,
00,
OS2
8212
f-
Ci:R
MD
0s1
01 8 --01,
13
V"
~
,
AD,
I
f--
AD,
f--
,
AD
WR
{
-2
-2
-2
t---!
8,
0,
A,
I
I
I
82
,
---rn
A,
~BJ
•
•
7
'2
MEMA
f-f-f-f--
lOR
/;IDiIW
lOW
O.
~'"
13 8
CHIP
SElECT
-
DE
SEL jB}
1
101M
L
~
HLDA
-,/
eLK (OUT)
_
RESET OUT
-
AEADY
READY
CS
0,
I
I
A,
'----
"',.
0,
--Lc MeMR
---'--c iOO
~
OROo
BAcKI)
MEMW
ORal
~ iOW
DACK 1
DAa t
--22...
IiRO
--..!...
HLDA
DACK 2
DROl
DACK J
~
~
ClK
TC
RESET
MARK
AEN
ADSTB
•
•
13
DS2
-=>
,J"
CLR
01,
I
I
01,
MD
STB
DO,
I
I
8212
00,
5S1
l' l'
Figure 11. Detailed System Interface Schematic
9·101
lOW
,....-
I
8257-5
-
lOR
~1~
RESET
-
MEhTR
I·
"1
HOLD
iN
DATA BUS
A,
4
RESET
0,
0,
V"
8085
~
ADDRESS
BUS
,.
25
'8
2.
,.
,.
17
'5
3.
,
ORa..
DACK o
ORO,
OACK,
DRQ2
DACK 2
ORQl
DACK 3
TC
MARK
CONTROL
BUS
6~5716257·5
MEMRO
IIORO
MEMWR
IIOWR
IIORO
MEMRO
iiOWA
MEMWR
8257
BIT 15
READ
BIT 14
WRITE
0
0
1
1
0
1
0
1
DMA Verily Cycle
DMA Read Cycle
DMA Write Cycle
Illegal
Figure 8. TC Register for Memory Mapped 1/0 Only
Figure 7. System Interface for Memory Mapped 1/0
SYSTEM APPLICATION EXAMPLES
l
\
\
\
ADDRESS BUS
~r
CONTROL BUS
II
~I
fi
U D U
11 D 1
DRaa
DISK 1
-------
DACK 0
ORO 1
8257
AND
8212
ImlR
DATA BUS
I
I
DISK 2
DACK 1
II
II
II~
UD U
SYSTEM
RAM
MEMORY
------
ORQ2
DISK 3
OACK 2
DR03
-------
OACK 3
DISK 4
OMA CONTROLLER
Figure 9.
Floppy Disk Controller (4 Drives)
ORO
8257
AND
8212
8251
DACK
USART
MODEM
TELEPHONE
LINES
Figure 10. Hlgh·Speed Communication Controller
9-102
SYSTEM
RAM
MEMORY
\
8257/8257·5
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O°C to 70°C
Storage Temperature .............. _65°C to +150°C
Voltage on Any Pin
With Respect to Ground ............ -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS
TA - o°c to 70°C, Vee - +5V ± 5%, GND - OV
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Low Voltage
-0.5
0.8
Volts
VIH
Input High Voltage
2.0
Vee+· 5
Volts
VOL
Output Low Voltage
0.45
Volts
IOL - 1.6 mA
VOH
Output High Voltage
2.4
Vee
Volts
IoH--150IlA for AB,
DB and AEN
IOH --80IlA for others
VHH
HRQ Output High Voltage
3.3
Vee
Volts
IOH - -801lA
lee
Vee Current Drain
120
mA
VIL
TEST CONDITIONS
IlL
Input Leakage
±10
/.LA
VIN - Vee to OV
IoFL
Output Leakage During Float
±10
IlA
VOUT - Vee to OV
CAPACITANCE
TA - 25°C; Vee - GND SYMBOL
ov
PARAMETER
TEST CONDITIONS
MAX.
UNIT
CIN
Input Capacitance
10
pF
fc - 1 MHz
CI/O
I/O Capacitance
20
pF
Unmeasured pins
returned to GND
MIN.
9-103
TYP.
8257/8257·5
A.C. CHARACTERISTICS: PERIPHERAL (SLAVE) MODE
TA = o°c to 70°C, Vee
= 5.0V ±5%; GNO = OV (Note 1).
8080 Bus Parameters
Read Cycle:
8257
Parameter
Symbol
Min.
8257·5
Max.
Min.
Max.
Unit
TAR
Adr or CSt Setup to R O.J,
0
0
ns
TRA
Adr or cst Hold from ROt
0
0
ns
T RO
Data Access from ROt
0
300
0
200
ns
TOF
OB-+Float Delay from ROt
20
150
20
100
ns
TRR
RD Width
250
250
Test Conditions
(Note 2)
ns
Write Cycle:
8257
Symbol
Parameter
Min.
8257-5
Max.
Min.
Max.
Unit
TAW
Adr Setup to WR.J,
20
20
ns
TWA
Adr Hold from WRt
0
0
ns
Tow
Data Setup to WRf
200
200
ns
Two
Data Hold from WRt
0
0
ns
Tww
WR Width
200
200
ns
Test Conditions
Other Timing:
8257
Symbol
I;
..
Parameter
Min.
8257-5
Max.
Min.
Max.
Unit
TRSTW
Reset Pulse Width
300
TRSTD
Power Supplyt (Vee) Setup to Reset.),
500
Tr
Signal Rise Time
20
20
ns
Tf
Signal Fall Time
20
20
ns
Reset to First I/OWR
TRSTS
Notes:
500
2
Test Conditions
ns
300
!J.S
2
tCY
1. All timing measurements are made at the following reference voltages unless specified otherwise:
2. 8257: CL = 100pF. 8257·5: eL = lSOpF.
Input "1" at 2.0V, "0" at 0.8V
Output "1" at 2.0V, "0" at 0.8V
8257 PERIPHERAL MODE TIMING DIAGRAMS
Write Timing:
Read Timing:
Et_T'~-
ADDRESS BUS
ADDRESS B U s = : J t
-
DATA BUS
I
----l ~ TRA
..,:~-_-_-_-_-_-_-_-_-_-_-_-T~-.!f:-~--~-D~-_-_-_-_
----------J1--~--+_--~~----
Reset Timing:
TAR -
IdR.
y-'--~==
Input Waveform for A.C. Tests:
:: =======:X :~:;;
RESET
9·104
TEST POINTS : : :::
x. .____
8257/8257·5
A.C. CHARACTERISTICS: DMA (MASTER) MODE
TA = O°C to 70°C, Vcc
= + 5V
:l:
5%, GND
=OV.
Timing Requirements
8257
SYMBOL
PARAMETER
MIN.
8257-5
MAX.
MIN.
MAX.
UNIT
Tcy
Cycle Time (Period)
0.320
4
0.320
4
/.IS
TO
Clock Active (High)
120
.BTcy
BO
.BTcy
ns
TQS
DROt Setup to Ot (SI, S4)
120
30
ns
TQH
DROt Hold from HLDAt[4]
0
0
ns
THS
HLDAt or tSetup to Ot(SI, S4)
100
100
ns
TRS
READY Setup Time to ot (S3, Sw)
30
30
ns
TRH
READY Hold Time from ot (S3, Sw)
20
20
ns
Note:
4. Tracking Parameter.
Tracking Parameters
Signals labeled as Tracking Parameters (footnotes 4-7 under A.C. Specifications) are signals that follow similar paths
through the silicon die. The propagation speed of these signals varies in the manufacturing process but the relationship between all these parameters is constant. The variation is less than or equal to 50 ns.
Suppose the following timing equation is being evaluated,
TA(MIN) + T B(MAX) :$150 ns
and only minimum specifications exist for T A and TB. If T A(MIN) is used, and if TA and TB are tracking parameters,
TB(MAX) can be taken as T B(MIN) + 50 ns.
T A(MIN) + (T B(MIN)· + 50 ns) :$ 150 ns
• if TA and T B are tracking parameters
9-105
8257/8257·5
A.C. CHARACTERISTICS: DMA (MASTER) MODE
TA=O·C to 70·C, Vee= +5V ±5%, GND=OV
Timing Re.pon.e.
82157·5
8257
MAX.
UNIT
Too
HROt or ~Delay from Ot(SI,S4)
(measured at 2.0V)[1 1
160
160
ns
TOOt
HROt or .J.Delay from OtISI.S4)
(measured at 3.3V)[31
250
250
ns
TAEL
AENt Delay from 0 ~(Sl)[ 1 1
300
300
ns
TAET
AEN./. Delay from Ot(S!)I!]
200
200
ns
TAEA
Adr(AB)(Active) Delay from AENt(Sll[41
TFAAB
Adr(AB)(Active) Delay from ot(Sl)[21
250
250
TAFAB
Adr(AB)(Float) Delay from Ot(SI)[21
150
150
ns
TASM
Adr(AB)(Stable) Delay from Ot(Sll[2]
250
250
ns
TAH
Adr(AB)(Stable) Hold from Ot(Sl )[21
TAHR
Adr(AB)(Valid) Hold from Rdt(Sl,SI)[41
TAHW
Adr(AB)(Valid) Hold from Wrt(Sl,SI)(41
TFAOB
Adr(DB)(Active) Delay from Ot(Sl)1 21
TAFOB
Adr(DB)(Float) Delay from Ot(S2)1 21
TSTT+20
TASS
Adr(DB) Setup to AdrStbHS1·S2)1 41
100
100
TAtiS
Adr(DB)(Valid) Hold from AdrStbHS2)(41
50
50
TSTL
AdrStbt Delay from IIt(S1I[11
200
200
ns
TSTT
AdrStb,j, Delay from 0 t (S2)( 11
140
140
ns
Tsw
AdrStb Width (Sl·S2)1 41
TCy-l00
Tcy-l00
ns
TASC
Rd.!- or Wr(Ext),j, Delay from AdrStb.j,(S2)14J
70
70
ns
TOBC
Rd.J, or Wr(ExtH Delay from Adr(DB)
(Float)(S2)(4J
20
20
ns
TAK
DACKt or .J.Delay from 0+(S2.S1) and
TC!Markt Delay from Ot(S3) and
TC!Mark,j, Delay from 0 t (S4)( 1,5J
250
250
ns
TOCL
Rd,J. or Wr(ExtH Delay from Ot(S2) and
Wrt Delay from Ot(S3)12,6J
200
200
ns
TOCT
Rdt Delay from OHS1,SI) and
wrt Delay from 8t(S4)12,71
200
200
ns
TFAC
Rd or Wr (Active) from Ot(SI )(2J
300
300
ns
TAFC
Rd or Wr ,(Float) from et(SI)[2]
150
150
ns
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
20
ns
20
ns
TASM-50
ns
60
60
ns
300
300
TASM-50
300
250
TSTT+20
ns
300
ns
170
ns
ns
ns
TRWM
Rd Width (S2·S1 or SI)14J
TWWM
Wr Width (S3-S4)1 41
TCy-50
Tcy-50
ns
TWWME
Wr(Ext) Width (S2-S4)141
2TCy-50
2TCy-50
ns
Notes:
2TCY + To-50
1. Load = 1 TTL. 2. Load = 1 TTL + 50pF. 3. Load = 1 TTL + (R L "' 3.3KI, VOH
5. ATAK<50ns. 6. ATOCL<50ns. 7. ATDCT<50ns.
9-106
2TCY + To-50
=
3.3V.
4. Tracking Parameter.
ns
-
825718257-5
DMA MODE WAVEFORMS
CONSECUTIVE CYCLES AND BURST MODE SEQUENCE
~
I
~
I
00
I
~
I
a
I
a
I
~
I
~
S2
I
~
S3
I
SI
SI
SI
CLOCK
DRaO.3 __~__~+-
______~-+____~____~~______~~__________~__4-____r-___________
TOO
HRQ _ _ _ _ _ _"
- \._----
HLDA ___________..../1
AEN _________~-~
ADA 0·7 (LOWER AQR)_
-
-
DATAO·7 (UPPER ADR1-
-
_
ADA STS
----fI
TWWME--
READY
CLOCK
NOTE: Ttw c;IDdt ww.form is
duplicated fOf clarity.
The 8257 requir.. onlv
SI
so
S1
S2
S1
S3
one clock input.
Figure 12. Consecutive Cycles and Burst Mode Sequence
9·107
S2
S3
~
SI
SI
SI
8257/8257·5
I
51
I
52
I
53
I
54
I
51
I
51
I
SO
51
I
I
52
CLOCK
ORO 0-3
HRQ
HLDA
t--
TAn AEN
J
\
T
Figure 13. Control Override Sequence
so
I
~
I
52
I
I
53
~
I
~
I
54
I
51
I
51
CLOCK
DRQO·3
~/~-----
~
READY
_ _ _ _ _ _ _....:;~----'...J
Te/MARK
I
\. .______
- TRS
\
Figure 14. Not Ready Sequence
9·108
I
51
8259A
PROGRAMMABLE INTERRUPT CONTROLLER
• MCS·86™ Compatible
• Programmable Interrupt Modes
• MCS·80185™ Compatible
• Individual Request Mask Capability
• Eight·Level Priority Controller
• Single
• Expandable to 64 Levels
• 28·Pin Dual·ln·Line Package
+ 5V Supply (No Clocks)
The Intel" 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intel@ 8259. Software originally written for the 8259 will operate the
8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).
BLOCK DIAGRAM
PIN CONFIGURATION
vee
WR
Au
AD
INTA
0,
IR7
D.
IR6
DATA
BUS
0,.
IR5
BUFFER
D.
IR4
0,
IR3
0,
IR2
0,
!R'
0"
IRO
CAS 0
INT
RD
CAS'
SP/Eiii
WR
GND
CAS2
PIN NAMES
0 7 -0.
DATA BUS (BI·DIRECTIDNAL)
RD
WR
READ INPUT
WRITE INPUT
Ao
CDMMAND SELECT ADDRESS
CS
CAS2·CASO
INT
INTA
cs
SP!El11
CHIP SELECT
CASCADE LINES
SLAVE PROGRAM INPUT/ENABLE
INT
INTA
IRO-IR7
INTERRUPT OUTPUT
INTERRUPT ACKNOWLEDGE INPUT
INTERRUPT REQUEST INPUTS
CONTROL LOGIC
IRO
IR'
IR2
es------'
'--r_~-IR7
CASO
CAS 1
eAS2
SPJEN---~
9-109
~INTERNAl
BUS
8259A
INTERRUPTS IN MICROCOMPUTER
SYSTEMS
Microcomputer system design requires that 110 devices
such as keyboards, displays, sensors and other components receive servicing in an efficient manner so that
large amounts of the total system tasks can be assumed
by the microcomputer with little or no effect on throughput.
match his system requirements. The priority modes can
be changed or reconfigured dynamically at any time during the main program. This means that the complete
interrupt structure can be defined as required, based on
the total system environment.
The most common method of servicing such devices Is
the Polled approach. This is where the processor must
test each device in sequence and In effect "ask" each
one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would
have a serious, detrimental effect on system throughput, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost effectiveness
of using such devices.
CPU·ORIVEN
MULTIPLEXOR
CPU
\
RAM
A more desirable method would be one that would allow
the microprocessor to be executing its main program
and only stop to service peripheral devices when it Is
told to do so by the device itself. In effect, the method
would provide an external asynchronous input that
would inform the processor that it should complete
whatever instruction that is currently being executed
and fetch a new routine that will service the requesting
device. Once this servicing is complete, however, the
processor would resume exactly where it left off.
This me~hod is called Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.
ROM
-h
v
"'V
I'-----"
V
'V
----'\,
~
"'V
['v---V
1/0111
,..--
1/0(21
r--
r---,
A.
-h
I
~
I
IIO(NI
IL ___ ..JI
V'
Polled Method
The Programmable Interrupt Controller (PIC) functions
as an overall manager in an Interrupt-Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the incoming requests
is of the highest importance (priority), ascertains
whether the incoming request has a higher priority value
than the level currently being serviced, and issues an
interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or "routine" that is associated with its specific
functional or operational requirements; this is referred
to as a "service routine". The PIC, after issuing an Interrupt to the CPU, must somehow input information into
the CPU that can "point" the Program Counter to the
service routine associated with the requesting device.
This "pointer" is an address In a vectoring table and will
often be referred to, In this document, as vectoring data.
RAM
ROM
8259A BASIC FUNCTIONAL DESCRIPTION
GENERAL
The 8259A is a device specifically designed for use in
real time, interrupt driven microcomputer systems. It
manages eight levels or requests and has built-in features for expandability to other 8259A's (up to 64 levels).
It is programmed by the system's software as an 110
peripheral. A selection of priority modes Is available to
the programmer so that the manner In which the requests are processed by the 8259A can be configured to
--)j
----
Interrupt Method
9-110
'0
8259A
INTERRUPT REQUEST REGISTER (lRR) AND
IN-SERVICE REGISTER (lSR)
The interrupts at the IR input lines are handled by two
registers in cascade, the Interrupt Request Register
(IRR) and the In-Service Register (ISR). The IRR is used
to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels
which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set
in the IRR. The highest priority is selected and strobed
into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt lines
to be masked. The IMR operates on the IRR. Masking of
a higher priority input will not affect the interrupt
request lines of lower priority.
INT (INTERRUpn
This output goes directly to the CPU interrupt input. The
VOH level on thialine is designed to be fully compatible
with the 8080A, 8085A and 8086 input levels.
8259A Block Diagram
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring
information onto the data bus. The format of this data
depends on the system mode (IlPM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8·bit buffer is used to interface the 8259A to the system Data Bus. Control words
and status information are transferred through the Data
Bus Buffer.
READIWRITE CONTROL LOGIC
The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command
Word (OCW) registers which store the various control
formats for device operation. This function block also
allows the status of the 8259A to be transferred onto the
Data Bus.
CS (CHIP SELECn
A LOW on this input enables the 8259A. No reading or
writing of the chip will occur unless the device is
selected.
WR(WRITE)
8259A Block Diagram
A LOW on this input enables the CPU to write control
words (ICWs and OCWs) to the 8259A.
AO
RD (READ)
A LOW on this input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In Service
Register (ISR), the Interrupt Mask Register (IMRl, or the
Interrupt level onto the Data Bus.
9·111
This input signal is used in conjunction with WR and RD
signals to write commands into the various command
registers, as well as reading the various status registers
of the Chip. This line can be tied directly to one of the address lines.
8259A
THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of all
8259A's used in the system. The associated three 110
pins (CASO-2) are outputs when the 8259A is used as a
master and are inputs when the 8259A is used as a
slave. As a master, the 8259A sends the 10 of the inter·
rupting slave device onto the CASO-2 lines. The slave
thus selected will send its preprogrammed subroutine
address onto the Data Bus during the next one or two
consecutive INTA pulses. (See section "Cascading the
8259A".)
If no interrupt request is present at step 4 of either
sequence (i.e., the request was too short in duration) the
8259A will issue an interrupt level 7. Both the vectoring
bytes and the CAS lines will look like an interrupt level 7
was requested.
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specific interrupt routine requested
without any polling of the interrupting devices. The nor·
mal sequence of events during an interrupt depends on
the type of CPU being used.
The events occur as follows in an MCS·80/85 system:
1. One or more of the INTERRUPT REQUEST lines
(IR7-0) are raised high, setting the corresponding IRR
bit(s).
2. The 8259A evaluates these requests, and sends an
INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an
INTA pulse.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259A will also release a CALL in·
struction code (11001101) onto the 8·bit Data Bus
through its 07-0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259A from the CPU group.
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data
Bus. The lower 8·bit address is released at the first
INTA pulse and and the higher 8·bit address is reo
leased at the second INTA pulse.
7. This completes the 3·byte CALL instruction released
by the 8259A. In the AEOI mode the ISR bit is reset at
the end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appropriate EOI command is
issued at the end of the interrupt sequence.
8259A Block Diagram
The events occurring in an MCS·86 system are the same
until step 4.
WIi
lID
4. Upon receiving an INTA from the CPU group, the high·
est priority ISR bit is set and the corresponding IRR
bit is reset. The 8259A does not drive the Data Bus
during this cycle.
5. The MCS-86 CPU will initiate a second INTA pulse.
During this pulse, the 8259A releases an 8·bit pOinter
onto the Data Bus where it is read by the CPU.
i
INTERRUPT
REQUESTS
6. This completes the interrupt cycle. In the AEOI mode
the ISR bit is reset at the end of the second INT A
pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the
interrupt subroutine.
8259A Interface to Standard System Bus
9·112
INT
INT A
8259A
INTERRUPT SEQUENCE OUTPUTS
MCS-80/85 SYSTEM
This sequence is timed by three INTA pulses. During the
first iiiifA pulse the CALL opcode is enabled onto the
data bus.
During the third INTA pulse the higher address of the
appropriate service routine, which was programmed as
byte 2 of the initialization sequence (As - Ad, is
enabled onto the bus.
Content 01 Third Interrupt
Vector Byte
Content of First Interrupt
Vector Byte
D7
D6
D5
D4
D3
D2
Dl
DO
07
D6
D5
D4
D3
D2
D1
DO
A15
A14
A13
,0.12
A11
,0.10
A9
AS
CALLCODE~
L_l_________
0____0_________________1~1
MCS·86 SYSTEM
During the second INTA pulse the lower address of the
appropriate service routine is enabled onto the data bus.
When Interval = 4 bits A5-A7 are programmed, while AoA. are automatically inserted by the 8259A. When Interval = 8 only A6 and A7 are programmed, while Ao-A5 are
automatically inserted.
Content of Second Interrupt
Vector Byte
Inl....al.,4
III
--
07
D6
D5
04
D3
02
D1
7
A7
A6
A5
1
1
1
0
0
6
A7
A6
A5
1
1
0
0
0
5
A7
A6
A5
1
0
1
0
0
4
A7
AS
AS
1
0
0
0
0
3
A7
A6
A5
0
1
1
0
0
2
A7
A6
A5
0
1
0
0
0
1
A7
A6
A5
0
0
1
0
0
0
A7
AS
A5
0
0
0
0
0
D7
06
D5
D4
D3
D2
D1
DO
7
A7
,0.6
1
1
1
0
0
0
6
A7
AS
1
1
0
0
0
0
5
A7
,0.6
1
0
1
0
0
0
4
,0.7
A6
1
0
0
0
0
0
3
A7
A6
0
1
1
0
0
0
2
A7
AS
0
1
0
0
0
0
1
,0.7
AS
0
0
1
0
0
0
0
A7
AS
0
0
0
0
0
0
III
DO
MCS-86 mode is similar to MCS-80 mode except that
only two Interrupt Acknowledge cycles are issued by
the processor and no CALL opcode is sent to the processor. The first interrupt acknowledge cycle is similar to
that of MCS-80/85 systems in that the 8259A uses it to
internally freeze the state of the interrupts for priority
resolution and as a master it issues the interrupt code
on the cascade lines at the end of the INTA pulse. On
this first cycle it does not issue any data to the proc·
essor and leaves its data bus buffers disabled. On the
second interrupt acknowledge cycle in MCS-86 mode
the master (or slave if so programmed) will send a byte
of data to the processor with the acknowledged interrupt code composed as follows (note the state of the
ADI mode control is ignored and A5-A'l are unused in
MCS-86 mode):
Content of Interrupt Vector Byte
lor MCS-86 System Mode
Inl.",.1=8
9-113
DO
D7
06
D5
04
D3
D2
01
IR7
A15
A14
,0.13
A12
,0.11
1
1
1
IR6
,0.15
A14
A13
,0.12
,0.11
1
1
0
IR5
,0.15
,0.14
A13
,0.12
,0.11
1
0
1
IR4
A15
,0.14
,0.13
,0.12
A11
1
0
0
IR3
0.15
A14
,0.13
,0.12
,0.11
0
1
IR2
,0.15
A14
A13
,0.12
A11
0
IRl
A15
,0.14
,0.13
A12
A11
0
0
1
IRO
,0.15
A14
A13
,0.12
A.11
0
0
0
,
1
0
8259A
PROGRAMMING THE 8259A
INITIALIZATION
The 8259A accepts two types of command words generated by the CPU:
GENERAL
Whenever a command is issued with AO = 0 and D4 = 1,
this is interpreted as Initialization Command Word 1
(ICW1). ICW1 starts the initialization seQuence during
which the following automatically occur.
1. Initialization Command Words (lC Ws): Before normal
operation can begin, each 8259A in the system must
be brought to a starting point - by a seQuence of 2 to
4 bytes timed by WR pulses. This seQuence is
described in Figure 1.
a. The Interrupt Mask Register is cleared.
b. IR 7 input is assigned priority 7.
c. The slave mode address is set to 7.
2. Operation Command Words (OCWs): These are the
command words which command the 8259A to operate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
d. Special Mask Mode is cleared and Status Read is set to
IRR.
e. If IC4 = 0, then all functions selected in ICW4 are set to
zero. (Non-Buffered mode', no Auto-EOI, MCS-80/85
system, non SFNMI.
The OCWs can be written into the 8259A anytime after
initialization.
Ao
04
03
0
1
'Not.: Master/Slave In ICW4 is only used in the buffered mode.
RD
WR
CS
0
0
1
0
0
1
INPUT OPERATION (READ)
IRR, ISR or Interrupting Level_DATA BUS (Note 1)
IMR -.DATA BUS
OUTPUT OPERATION (WRITE)
0
0
0
1
0
0
0
1
1
0
1
1
X
X
X
1
1
0
0
0
0
0
0
0
DATA
DATA
DATA
DATA
BUS -OCW2
BUS-OCW3
BUS--ICW1
BUS __ OCW1, ICW2, ICW3, ICW4 (Note 2)
DISABLE FUNCTION
X
X
X
X
X
X
1
X
1
X
0
DATA BUS - 3-STATE (NO OPERATION)
DATA BUS - 3-STATE (NO OPERATION)
1
Not••: t. Selection of IAA. ISA or Interrupting Level is based on the content of OCW3 written before the AEAD operation.
2. On-chip sequencer logic queues these commands into proper sequence.
8259A Basic Operation
9-114
8259A
INITIALIZATION COMMAND WORDS 1 AND 2
(lCW1, ICW2)
INITIALIZATION COMMAND WORD 3 (ICW3)
A5-A 15: Page starting address of service routines. In an
MCS 80/85 system, the 8 request levels will generate
CALLs to 8 locations equally spaced in memory. These
can be programmed to be spaced at intervals of 4 or 8
memory locations, thus the 8 routines will occupy a
page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (Ao-A 15l. When the
routine interval is 4, Ao-A4 are automatically Inserted by
the 8259A, while A5-A 15 are programmed externally.
When the routine interval Is 8, Ao-A5 are automatically
inserted by the 8259A, while Ae-A15 are programmed
externally.
The 8-byte Interval will maintain compatibility with current software, while the 4-byte Interval is best for a compact jump table.
In an MCS-86 system A15-A 11 are inserted in the five
most significant bits of the vectoring byte and the
8259A sets the three least significant bits according to
the interrupt level. A10-A 5 are ignored and ADI (Address
interval) has no effect.
LTIM:
If LTIM = 1, then the 8259A will operate in the
level interrupt mode. Edge detect logic on the
Interrupt inputs will be disabled.
ADI:
CALL address interval. ADI = 1 then Interval = 4;
ADI = 0 then interval = 8.
SNGL: Single. Means that this Is the only 8259A in the
system. If SNGL= 1 no ICW3 will be issued.
IC4:
If this bit is set - ICW4 has to be read. If ICW4
Is not needed, set IC4 = O.
AO
05
07
A7
AI
A15
A14
04
AS
This word is read only when there is more than one
8259A in the system and cascading is used, in which
case SNGL = O. It will load the 8-bit slave register. The
functions of this register are:
a. In the master mode (either when SP = 1, or in buffered
mode when MIS = 1 in ICW4) a "1" is set for each
slave in the system. The master then will release byte
1 of the call sequence (for MCS-80/85 system) and
will enable the corresponding slave to release bytes 2
and 3 (for MCS-86 only byte 2) through the cascade
lines.
b. In the slave mode (either when SP = 0, or If BUF = 1
and MIS = 0 In ICW4) bits 2-0 identify the slave. The
slave compares its cascade Input with these bits and,
If they are equal, bytes 2 and 3 of the call sequence (or
just byte 2 for MCS-86) are released by it on the Data
Bus.
INITIALIZATION COMMAND WORD 4 (lCW4)
SFNM: If SFNM = 1 the special fully nested mode Is
programmed.
BUF: If BUF = 1 the buffered mode is programmed. In
buffered mode SP/EN becomes an enable output
and the masterlslave determination Is by MIS.
MIS: If buffered mode is selected: MIS 1 means the
8259A Is programmed to be a master, MIS 0
means the 8259A is programmed to be a slave. If
BUF = 0, MIS has no function.
AEOI: If AEOI = 1 the automatic end of interrupt mode
is programmed.
I'PM: Microprocessor mode: I'PM = 0 sets the 8259A
for MCS-80/85 system operation, I'PM 1 sets
the 8259A for MCS-86 system operation.
=
=
D3
02
01
LTIM
AOI
5NOL
A11
A10
At
53
52
S1
MIS
AEOI
DO
.------------YE5
57
I_I
58
,.::~.~."
_ 1 _ _ ---lSFNM
aUF
READY TO ACCEPT REQUESTS
IN THE FULLY NESTED MODE
Figure 1_ Inltlanzatlon Sequence
9-115
=
so
ICW3
8259A
,CW,
A.
0,
0,
0,
0,
, . ICW4 NEEDED
0'" NO ICW4 NEEDED
1" SINGLE
0" NOT SINGLE
CALL ADDRESS INTERVAL
1 .. INTERVAL OF 4
0'" INTERVALOF8
1 = lEVEl TRIGGERED INPUT
0= EDGE TRIGGERED INPUT
A7 - AS OF LOWER
ROUTINE ADDRESS
(MCS·SO/8S MODE ONl V)
'CW2
A.
0,
D.
UPPER ROUTINE
ADDRESS
ICW3 IMASTER DEVICE,
1 .. IA INPUT HAS A SLAVE
0-' IR INPUT DOES NOT HAVE
A SLAVE
I-
ICW3 (SLAVE DEVICE)
~
0,
~
~
~
I I I I I I
1
0
0
0
0
0,
0
~
0,
lID, lID,
~
I,D.'
~
SLAVE 10111
'"
o
o
o
0
o
0
1
2
3
4
5
•
7
1
o
1
o
1
o
1
1
1
0
o
1
,
0
0
1
1
1
1
1 = MCS-86 MODE
o "- MeS-SO/BS MODE
1" AUTO EOI
o = NORMAl.
Efffi
,.
0
- NON BUFFERED MODE
- BUFFERED MODE/SLAVE
1
x
1
- BUFFERED MODE/MASTER
EOI
NOTE 1: SLAVED 10 IS EQUAL TO THE CORRESPONDING MASTER IR INPUT.
NOTE 2: X INDICATED "DON'T CARE".
Initialization Command Word Format
9-116
8259A
OPERATION COMMAND WORDS (OCWs)
OPERATION CONTROL WORD 1 (OCW1)
After the Initialization Command Words (leWs) are pro·
grammed Into the 8259A, the chip Is ready to accept
Interrupt requests at Its Input lines. However, during the
8259A operation, a selection of algorithms can com·
mand the 8259A to operate In vanous modes through
the Operation Command Words (OCWs).
OCW1 sets and clears the mask bits in the interrupt
Mask Register (IMR). M7- Mo represent the eight mask
bits. M 1 Indicates the channel is masked
(inhibited), M = 0 indicates the channel is enabled.
=
OPERATION CONTROL WORD 2 (OCW2)
R, SEOI, EOI - These three bits control the Rotate and
End of Interrupt modes and combinations of the two. A
chart of these combinations can be found on the Opera·
tion Command Word Format.
OPERATION CONTROL WORDS (OCWI)
M
~
OCW1
D7D1D5D4D3D2
IM7
Me
M5
M4
M3
M2
L2, L1, Lo - These bits determine the interrupt level
acted upon when the SEOI bit is active.
D1
M1
OPERATION CONTROL WORD 3 (OCW3)
OCW2
0
I R
SEOI
EOI
0
0
L2
L1
ESMM - Enable Special Mask Mode. When this bit is
set to 1 it enables the SMM bit to set or reset the Special
Mask Mode. When ESMM 0 the SMM bit becomes a
"don't care".
LOI
=
=
ocwa
0
I 0
SSMM SMM
0
P
SRIS
RIS I
9·117
=
=
SMM - Special Mask Mode. If ESMM 1 and SMM 1
the 8259A will enter Special Mask Mode. If ESMM 1
and SMM 0 the 8259A will revert to normal mask mode.
When ESMM 0, SMM has no effect.
=
=
8259A
oew'
~
~
~
~
06
Os
~
~
~
~
~
oew,
"0
07
1
1
5£01.1
R
0
Dz
03
o.J
01 L,l L,J L, J
EOI.I
0,
Do
0"
I
BCD LEVel TO BE RESET
OR PUT INTO LOWEST PRIORITV
0
0
, , ,
, ,
, ,
0
0
0
0
0
0
0
4
,• • ,
7
0
0
0 0 , ,
, , , ,
l I
J rt
rf~r+
r,.r-;-
r,--:;-r,-
r;-.r,
1-;;-717
r,--:;-17
tt2:t3:
NON.SPECIFIC EOI
SPECIFIC EOI, LO-L2CODE OF IS FF TO BE RESET
ROTATE AT EOI AUTOMATICALLY (MODE AI
ROTATE AT EOI (MODE BJ. (L(l.L2 DEFINES NEW LOWEST PRIORITY)
SET ROTATE A FF
CLEAR ROTATE A FF
ROTATE PRIORITY (MODE B) INDEPENDENTLY OF EOI (L.O-U CODE OF LINE)
NO OPERATION
oew,
Ao
01
1 l0
0,
Ds
/'SMM/SMM/
colT
CARE
0"
0
03
/
1
~
01
Do
I IHUSI I
p
RIS
Lr-
READ IN SERVICE REGISTER
0
0
I ,
I
0
NO ACTION
0
,
READ
IR REG
,
,
READ
IS REG
ONNEKT
ROPULSE RDPULSE
ONNE,(T
POLLING
A HIGH ENABLES THE NEXT AD PULSE
TO READ THE BCD CODE OF THE HIGH
EST UVEL REQUESTING INTERRUPT
SPECIAL MASK MODE
0
0
I ,
I
0
NO ACTION
Operation Command Word Format
9-118
0
,
,
,
RESET
SPECIAL
MAlI<
SfT
SPECIAL
MAS'
8259A
INTERRUPT MASKS
Each Interrupt Request input can be masked indivIdually by the Interrupt Mask Register (IMR) programmed
through OCW1_ Each bit in the IMR masks one interrupt
channel if it is set (1)_ Bit 0 masks IRO, Bit 1 masks IR1
and so forth. Masking an IR channel does not affect the
other channels operation.
SPECIAL MASK MODE
Some applications may require an interrupt service
routine to dynamically alter the system priority structure during its execution under software control. For
example, the routine may wish to Inhibit lower priority
requests for a portion of its execution but enable some
of them for another portion.
The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (I.e., while executing a service routine),
the 8259A would have inhibited all lower priority
requests with no easy way for the routine to enable
them
That is where the Special Mask Mode comes in. In the
special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that
are not masked.
Thus, any interrupts may be selectively enabled by
loading the mask register.
The special Mask Mode is set by OCW3 where:
SSMM = 1, SMM = 1, and cleared where SSMM = 1,
SMM=O.
BUFFERED MODE
When the 8259A is used In a large system where bus
driving buffers are required on the data bus and the cascading mode is used, there exists the problem of enablIng buffers.
The buffered mode will structure the 8259A to send an
enable signal on SP/EN to enable the buffers. In this
mode, whenever the 8259A's data bus outputs are enabled, the SP/EN output becomes active.
This modification forces the use of software programming to determine whether the 8259A is a master or a
slave. Bit 3 in ICW4 programs the buffered mode, and bit
2 in ICW4 determines whether it is a master or a slave.
9-119
FULLY NESTED MODE
This mode is entered after initialization unless another
mode is programmed. The interrupt requests are
ordered in priority form 0 through 7 (0 highest). When an
interrupt is acknowledged the highest priority request is
determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an
End of Interrupt (EOI) command immediately before
returning from the service routine, or if AEOI (Automatic
End of Interrupt) bit is set, until the trailing edge of the
last INTA. While the IS bit is set, all further interrupts of
the same or lower priority are inhibited, while higher
levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal Interrupt enable flip-flop has been re-enabled through software).
After the Initialization sequence, IRO has the highest
priority and IR7 the lowest. Priorities can be changed, as
will be explained, in the rotating priority mode.
THE SPECIAL FULLY NESTED MODE
This mode will be used in the case of a big system
where cascading is used, and the priority has to be conserved within each slave. In this case the fully nested
mode will be programmed to the master (using ICW4).
This mode is similar to the normal nested mode with the
following exceptions:
a. When an interrupt request from a certain slave is in
service this slave is not locked out from the master's
priority logic and further interrupt requests from
higher priority IR's within the slave will be recognized
by the master and will initiate interrupts to the processor. (In the normal nested mode a slave is masked
out when its request is in service and no nigher
requests from the same slave can be serviced.)
b. When exiting the Interrupt Service routine the software has to check whether the interrupt serviced was
the only one from that slave. This is done by sending
a non-specific End of Interrupt (EOI) command to the
slave and then reading its In-Service register and
checking for zero. If it Is empty, a non-specific EOI
can be sent to the master too. If not, no EOI should be
sent.
8259A
POLL
In this mode the microprocessor internal Interrupt
Enable flip-flop is reset, disabling its interrupt input.
Service to devices is achieved by programmer initiative
using aPoll command.
The Poll command is issued by setting P= "1" in OCW3.
The 8259A treats the next AD pulse to the 8259A (i.e.,
RD = 0, ~ = 0) as an interrupt acknowledge, sets the
appropriate IS bit if there is a request, and reads the
priority level. Interrupt is frozen from WR to RD.
The word enabled onto the data bus during
D7
1
De
D5
D4
I
D3
m5 is:
D2
D1
DO
W2
W1
wol
WO-W2: Binary code of the highest priority level
requesting service.
I: Equal to a "1" if there is an interrupt.
second in MCS-86). Note that from a system standpoint,
this mode should be used only when a nested multilevel
interrupt structure is not required within a single 8259A.
To achieve automatic rotation (Rotate Mode A) within
AEOI, there is a special rotate flip-flop. It is set by OCW2
with R = 1, SEOI = 0, EOI = 0, and cleared with R = 0,
SEOI = 0, EOI = O.
ROTATING PRIORITY MODE A (AUTOMATIC
ROTATION) FOR EQUAL PRIORITY DEVICES
In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after
being serviced, receives the lowest priority, so a device
requesting an interrupt will have to wait, in the worst
case until each of 7 other devices are serviced at most
once. For example, if the priority and "in service" status
is:
Be'ore Rotate (IR4 the highest priority requiring service)
This mode is useful if there is a routine command common to several levels so that the INTA sequence is not
needed (saves ROM space). Another application is to
use the poll mode to expand the number of priority
levels to more than 64.
IS7 ISf IS5 154 IS3
"IS" Status
Low••1 Prlorlly
The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when "EOI bit in ICW1 is set) or by a command
word that must be issued to the 8259A before returning
from a service routine (EOI command). An EOI command
must be issued twice, once for the master and once for
the corresponding slave if slaves are in use.
There are two forms of EOI command: Specific and NonSpecific. When the 8259A is operated in modes which
preserve the fully nested structure, it can determine
which IS bit to reset on EOI. When a Non-Specific EOI
command is issued the 8259A will automatically reset
the highest IS bit of those that are set, since in the
nested mode the highest IS level was necessarily the
last level acknowledged and serviced.
However, when a mode is used which may disturb the
fully nested structure, the 8259A may no longer be able
to determine the last level acknowledged. In this case a
Specific End of Interrupt (SEOI) must be issued which
includes as part of the command the IS level to be reset.
EOI is issued whenever EOI = 1, in OCW2, where LO-L2 is
the binary level of the IS bit to be reset. Note that although
the Rotate command can be issued together with an EOI
where EOI = 1, it is not necessarily tied to it.
It should be noted that an IS bit that is masked by an
IMR bit will not be cleared by a non-specific EOI if the
8259A is in the Special Mask Mode.
716
Priority Status
END OF INTERRUPT (EOI)
IS2
151
ISO
10111011101010101
5
High... Prlorlly
I • I 3 I 2 I i"to I
After Rotate (lR4 was serviced, all other priorities
rotated correspondingly)
IS7
HIS" Status
ISf 155 154 153
Hlgh••1 Prlorlly
Priority Status
IS2
IS1
ISO
10111010101010101
I
2
I
Low ••1 Prlorlly
ho I 7F rG
4
I3 1
The Rotate command mode A is issued in OCW2 where:
R = 1, EOI = 1, SEOI = O. Internal status is updated by an
End of Interrupt (EOI or AEOI) command. If R = 1, EOI = 0,
SEOI = 0, a "Rotate-A" flip-flOp is set. This is useful in
AEOI, and described under Automatic End of Interrupt.
ROTATING PRIORITY MODE B (ROTATION BY
SOFTWARE)
The programmer can change priorities by programming
the bottom priority and thus fixing all other priorities;
i.e., if IR5 is programmed as the bottom priority device,
then IR6 will have the highest one.
AUTOMATIC END OF INTERRUPT (AEOI) MODE
The Rotate command is issued in OCW2 where: R = 1,
SEOI = 1; LO-L2 is the binary priority level code of the
bottom priority device.
If AEOI = 1 in ICW4, then the 8259A will operate in AEOI
mode continuously until reprogrammed by ICW4. In this
mode the 8259A will automatically perform a nonspeCific EOI operation at the trailing edge of the last
interrupt acknowledge pulse (third pulse in MCS-80/85,
Observe that in this mode internal status is updated by
software control during OCW2. However, it is independent of the End of Interrupt (EOI) command (also executed by OCW2). Priority changes can be executed during an EOI command or independently.
9-120
8259A
lTiM BIT
TO OTHER PRIORTY CEllS
O. EDGE
1 = L.EVEl
eLR IIR
eLR Q
EDGE
IS.. lIT
SET
SENSE
,,.,DRITY
FLA~T~C~H---1f-_ _+-_--+--t----(~·L:::ttt--::~;;;;:;;-'H SET ISR
RESOLVER
CONTROL
L.OGIC
REQUEST
LATCH
o
O'P-+---+--~~-44-r-~--'
NQN·
MASKED
"EQ
Q
I~
NOTES
1. MAlTER CLEAR ACTIVE ONLY DURING ICW'
2. FREEZE/IS ACTIVE DURING 1NTi'1 AND POLL SEQUENCES ONLY
3. TRUTH TABLE FOR D·L-ATCH
OPERATION
FOLLOW
HOLD
Priority Cell - Simplified Logic Diagram
LEVEL TRIGGERED MODE
In· Service Register (lSR): 8·bit register which contains
the priority levels that are being serviced. The ISR is
updated when an End of Interrupt command is issued.
This mode is programmed using bit 3 in ICW1.
If LTIM ='1', an interrupt request will be recognized by a
'high' level on IR Input, and there is no need for an edge
detection. The interrupt request must be removed
before the EOI command is issued or the CPU interrupt
is enabled to prevent a second interrupt from occurring.
The above figure shows a concev~al circuit to give the
reader an understanding of the level sensitive and edge
sensitive input circuitry of the 8259A. Be sure to note
that the request latch is a transparent D type latch.
READING THE 8259A STATUS
The Input status of several internal registers can be read
to update the user information on the system. The
following registers can be read by issuing a suitable
OCW3 and reading with RD.
Interrupt Mask Register: B·bit register whose content
specifies the interrupt request lines being masked.
acknowledged. The highest request level is reset from
the IRR when an interrupt Is acknowledged. (Not
affected by IMR.)
Interrupt Mask Register: 8·bit register which contains
the interrupt request lines which are masked.
The IRR can be read when, prior to the RD pulse, a WR
pulse is issued with OCW3 (ERIS 1, RIS 0.)
=
=
The ISR can be read in a similar mode when ERIS = 1,
RIS = 1 in the OCW3.
There is no need to write an OCW3 before every status
read operation, as long as the status read corresponds
with the previous one; i.e., the 8259A "remembers"
whether the IRR or ISR has been previously selected by
the OCW3. This is not true when poll is used.
After initialization the 8259A is set to IRR.
For reading the IMR, no OCW3 is needed. The output
data bus will contain the IMR whenever RD is active and
AO= 1.
Polling overrides status read when P
OCW3.
9·121
=1,
ERIS
=1
in
8259A
SUMMARY OF 8258A INSTRUCTION SET
In.t, •
1
2
3
4
5
8
7
8
Mnemonic
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
12
13
14
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
15
18
ICWI
ICWI
17
ICW2
18
19
20
21
ICW3
ICW3
ICW4
ICW4
ICW4
ICW4
9
10
11
22
23
24
25
28
27
28
29
30
31
32
33
34
35
38
37
38
39
40
41
42
43
44
45
48
47
48
49
50
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
leW4
ICW4
leW4
P
0
0
o
A5
0
0
o
o
A7
AS
A5
o
1
o
o
A7
A7
A7
A7
A7
A7
A7
AS
AS
AS
AS
AS
AS
AS
A5
A5
A5
0
0
0
0
1
1
o
o
o
o
o
o
o
1
1
o
0
1
0
1
o
000
0
o
o
o
o
1
0
No ICW4 Required
000
0
A9
SI
~
0
0
H
o
0
0
000
J
K
L
M
N
0
0
0
000
001
0
0
o
000
o
o
000
000
o
o
o
1
o
1
o
0
NB
NC
NO
NE
NF
NG
NH
NI
NJ
ICW4
ICW4
ICW4
NK
NL
NM
ICW4
ICW4
NN
NO
NP
0
o
o
o
o
o
o
o
o
o
o
ICW4 Required
Format = 4,
Format = 8,
Format = 8,
Format = 8,
1
o
0
o
1
1
1
0
1
o
0
1
o
1
1
o
o
0
not alngle, level triggered
81ngle, edge triggered
81ngle, level triggered
not alngle, edge Irlggered
=8, not alngle, level triggered
Non,buffered mode, AEOI. MCS.a6
No action, redundant
Non,buffered mode, no AEOI, MCS.a6
Non-biJilered mode, AEOI, MCS-8OI85
Non-buffered mode, AEOI, MCS-86
Buffered mode. sl~ve, no A~OI, MCS-8OI85
Buffered mode, slave, no AEOI, MCS-86
Buffered mode, slave, AEOI, MCS-80185
Buffered mode, slave, AEOI, MCS-86
0
1
o
Byte 1 Initialization
Format 4, alngle, edge triggered
Format = 4, alngle, level triggered
Format. 4, not alngle, edge triggered
Format
0
0
0
0
0
1
1
0000000
o 0 0 0 0
0
1
00000110
o 0 0 ·0 0 1 1 1
F
G
Format = 4, not Single, level triggered
Format = 8, single, edge triggered
Format = 8, single, level triggered
Format 8, not alngle, edge triggered
Format =8, not alngle, level triggered
Byte 2 InltlallZlltion
Byte 3 Inillalization - master
Byte 3 Initialization - 81ave
No action, redundant
Non,buffered mode, no AEOI, MCS.a6
Non,buffered mode, AEOI, MCS-8OI8~
AS
SO
SO
0
o
0
E
Format = 4, single, level triggered
Format = 4, not Single, edge triggered
=
}
0
001
1
0
1
o
Byte 1 InltiallZlltlon
=
0
1
Format = 4, Single, edge triggered
o
0
A15 A14 A13 A12 All Al0
S7 58 S5 54 S3 S2
o 0 0 0 0 ~
000
0
0 0
000
0
0
0
o 0 0 0 0 0
M
S
A
B
C
E
SE
RE
RSE
R
CR
RS
P
RIS
o
AS
AS
AS
AS
AS
ICW4
ICW4
leW4
leW4
leW4
ICW4
leW4
leW4
leW4
OCW2
OCW2
OCW2
OCW2
OCW2
OCW2
OCW2
OCW3
OCW3
1
A7
A7
A7
A7
A7
o b
53
60
61
0
1
o
o
o
A5
A5
A5
000
000
000
000
000
000
000
ICW4
59
K
L
M
N
1
AS
AS
AS
P
NA
OCWI
56
57
58
F
G
H
o
A7
A7
A7
0
51
54
0
E
O...rltlon DeHripllon
o
o
o
o
o
ICW4
leW4
ICW4
52
55
A
B
C
Buffered mode, master, no AEOI, MCS-80185
Buffered mode, master, no AEOI. MCS.a6
Buffered mode, master, AEOI, MCS-8OI85
Buffered mode, master. AEOI, MCS.a6
Fully nested mode, MCS-80, non-buffered. no AEOI
}
ICW4 NB through ICW4 NO are Identical to
ICW4 B through ICW4 0 with the addition of
Fully Nested Mode
Fully Nested Mode, MCS-80185. non-buffered, no AEOI
1
o
000
o
000
o 1 1 1
000
000
00000
1
00000
00001
1
ICW4 NF through ICW4 NP are idenllcal to
ICW4 F through ICW4 P with the addition of
Fully Nested Mode
00000
o 0 0
0
1
o 0 0
0
o
0
0
1
1
1
I
1
M7
M6
o
o
o
0
0
1
o
o
M5
o
M4
o
o
1
1
o
1
000
o
1
0
00000
1
100
00000
o 0 0 0 0
o
M3
M2
Ml
MO
0
0
0
0
0
L2 Ll
LO
0
000
OL2L1LO
o
o
0
0
0
0
0
0
uL2L1LO
100
o
9-122
Load mask register, read mask register
Non-specific EOI
Specific EOI. LO-L2 code of IS FF to be resel
Rotate at EOI Automatically (Mode A)
Rotate at EOI (mode B). LO-L2 code of line
Set Rotate A FF
Clear Rotate A FF
Rotate priority (mode B) independentiy of EOI
Poll mode
Read IS register
8259A
SUMMARY OF 8259A INSTRUCTION SeT (Cont.)
62
OCW3 RR
63
OCW3 SM
OCW3 RSM
64
Ope...llon O.... rlpllon
AU 07 De 05 04 03 02 01 DO
MMmonlc
In••••
0
0
0
Nole: 1. In the master mode
0
0
0
0
SP pin =1. in
0
1
0
0
0
0
slave mode
1
0
0
0
0
0
Read request register
0
0
0
Set special mask mode
Reset special mask mode
SP =0
not be connected to a slave 8259A unless IR1-IR7 also
have slaves attached.
Clscldlng
The 8259A can be easily interconnected in a system of
one master with up to eight slaves to handle up to 64
priority levels.
The cascade bus lines are normally low and will contain
the slave address code from the trailing edge of the first
INTA pulse to the trailing edge of the third pulse. It is
obvious that each 8259A in the system must follOW a
separate initialization sequence and can be pro·
grammed to work in a different mode. An EOI command
must be issued twice: once for the master and once for
the corresponding slave. An address decoder is required
to activate the Chip Select (C'S) input of each 8259A.
A typical MCS-80/85 system is shown in Figure 2. The
master controls, through the 3 line cascade bus, which
one of the slaves will release the corresponding
address.
As shown in Figure 2, the slave interrupt outputs are
connected to the master interrupt request inputs. When
a slave request line is activated and afterwards acknowl·
edged, the master will enable the corresponding slave
to release the device routine address during bytes 2 and 3
of INTA. (Byte 2 only for MCS-861. The IRO input should
The cascade lines of the Master 8259A are activated for
any interrupt input, even if no slave is connected to that
input.
\
AOOR ESS BUS 1161
\
CONTROL BUS
1
1
INT REO
~
\
1
DATA BUS 181
"-
--
--
-- -
--
---
---
~
- --
--- - - --
f--f---
--
-
INT
G!O
6
5
4
3
2
CAS 1
,-
CAS2
1-
1
0
1
0
IIII I I
t
f
7
6
5
4
3
2
f
I
;.
...
CS
CASO
8'259A
SLAVE A
SPIEN7
!
r--
...
cs
-
r
IN'
8259A
SLAVE B
SPIEN7
8
5
4
J
8
5
4
3
2
1
CAS 0
CAS 1
CAS'
CAS2
CAS 2
0
II I I I ![!!
I
INTERRUPT REQUESTS
Figure 2. Clscldlng the 8259A
9·123
CS
CASO
...
INT
8259A
MASTER
SP/81 ..,1<...
9·126
8355*/8355-2**
16,384-8IT ROM WITH 1/0
*Directly Compatible with 808SA CPU
**Directly Compatible with 808SA-2
• Each 1/0 Port Line Individually
Programmable as Input or Output
• 2048 Words x 8 Bits
• Single
+ 5V
Power Supply
• Multiplexed Address and Data Bus
• Internal Address Latch
• 2 General Purpose 8·Bit 1/0 Ports
• 40·Pin DIP
The Intel@ 8355 is a ROM and I/O chip to be used in the MCS-85~ microcomputer system. The ROM portion is organized as
2048 words by 8 bits. It has a maximum access time of 400 ns to permit use with no wait states in the 8085A CPU.
The 1/0 portion consists of 2 general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line is indivdually programmable as input or output.
The 8355-2 has a 300ns access time for compatibility with the 8085A-2 microprocessor.
PIN CONFIGURATION
BLOCK DIAGRAM
CLK
N.C. (NOT CONNECTED)
REAOV
5
ADO-7
PB2
PB,
AD
lOW
PORTA
AIt"-10
Pa.
PA,
CE2
EE,
101M
ALE
AD
lOW
RESET
BB
ROM
G
8
lOR
~Vcc(+5V)
A,.
As
Vss (OV)
9-127
PAo-,
PBa. . .,
8355/8355-2
Symbol
Function
Symbol
Function
ALE
(Input)
When ALE (Address latch Enable is
high, ADo-7, 101M, A8-10, CE, and CE
enter address latched. The signals
(AD, 101M, A8-10, CE, CE) are latched
in at the trailing edge of ALE.
ClK
(Input)
The ClK is used to force the READY
into its high impedance state after it
has been forced low by CE low, CE
high and ALE high.
ADo-7
(Input)
Bidirectional AddresslData bus. The
lower 8-bits of the ROM or 1/0 address
are applied to the bus lines when ALE
is high.
READY
(Output)
Ready is a 3-state output controlled by
CE1, CE2, ALE and ClK. READY is
forced low when the Chip Enables are
active during the time ALE is high, and
remains low until the rising edge of the
next ClK (see Figure 6).
PAO-7
(Input!
Output)
These are general purpose 1/0 pins.
Their inputloutput direction is determined by the contents of Data Direction
Register (DDR). Port A is selected for
write operations wtlen the Chip Enables
are active and lOW is low and a 0 was
previously latched from ADo.
During an 1/0 cycle, Port A or Bare
selected based on the latched value of
ADo. If RD or lOR is low when the latched
chip enables are active, the output
buffers present data on the bus.
A8-10
(Input)
These are the high order bits olthe ROM
address. They do not affect 1/0 operations.
CE1
CE2
(Input)
Chip Enable Inputs: CE1 is active low
and CE2 is active~. The 8355 can be
accessed only when BOTH Chip Enables are active at the time the ALE
signal latches them up. If either Chip
Enable input is not active, the ADo-7
and READY outputs will be in a high
impedance state.
10iM
(Input)
If the latched 10iM is high when RD is
low, the output data comes from an
1/0 port. If it is low the output data
comes from the ROM.
RD
(Input)
If the latched Chip Enables are active
when RD goes low, the ADo-7 output
buffers are enabled and output either
the selected ROM location or I/O port.
When both RD and lOR are high, the
ADa-7 output buffers are 3-state.
lOW
(Input)
If the latched Chip Enables are active,
a Iowan lOW causes the output port
pointed to by the latched value of ADo
to be written with the data on ADo-7.
The state of 101M is ignored.
9-128
Read operation is selected by either
lOR low and active Chip Enables and
ADo low, Q[ 101M high, RD low, active
chip enables, and ADo low.
PBO-7
(Input!
Output)
This general purpose 1/0 port is
identical to Port A except that it is
selected by a 1 latched from ADo.
RESET
(Input)
An input high on RESET causes all pins
in Port A and B to assume input mode.
lOR
(Input)
When the Chip Enables are active, a low
on lOR will output the selected 1/0 port
onto the AD bus. lOR low performs the
same function as the combination 101M
high and RD low. When lOR is not used
in a system, lOR should be tied to Vee
Vee
+5 volt supply.
Vss
Ground Reference.
("1") .
8355/8355-2
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TemperatureUnderBias ................ 0·Cto+70·C
Storage Temperature ............... -65·Cto+150·C
Voltage on Any Pin
With Respect to Ground ............... -0.5V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
ITA = o·e to 70·e; Vee = 5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee-+{)·5
V
TEST CONDITIONS
VOL
Output Low Voltage
VOH
Output High Voltage
IlL
Input Lea kage
10
!-LA
= 5.0V
= 5.0V
IoL = 2mA
IoH = -400!-LA
VIN = Vee to OV
ILO
Output Leakage Current
±10
IJA
0.45V ..;vOUT ';;;'Vee
lee
Vee Supply Current
180
mA
A.C. CHARACTERISTICS
0.45
V
V
2.4
ITA
= oOe to 70 o e; Vee = 5V ± 5%)
8355
Symbol
Vee
Vee
Parameter
Min.
Max.
8~5~-2
(Prel m nary)
Min.
Max.
Units
tcye
Clock Cycle Time
320
320
ns
TI
ClK Pulse Width
80
80
ns
T2
ClK Pulse Width
120
120
tf.t,
ClK Rise and Fall Time
30
ns
30
ns
tAL
Address to latch Set Up Time
50
30
ns
tlA
Address Hold Time after latch
80
30
ns
tle
latch to READIWRITE Control
100
40
tRO
Valid Data Out Delay from READ Control
170
140
ns
tAD
Address Stable to Data Out Valid
400
330
ns
tll
latch Enable Width
tROF
Data Bus Float after READ
0
tCl
READIWRITE Control to latch Enable
20
10
tee
READIWRITE Control Width
250
200
ns
tow
Data In to Write Set Up Time
150
150
ns
two
Data In Hold Time After WRITE
10
twp
WRITE to Port Output
tPR
Port Input Set Up Time
50
50
tRP
Port Input Hold Time
50
50
tRYH
READY HO!-D Time
0
tARY
ADDRESS (CE) to READY
tRV
Recovery Time Between Controls
300
200
ns
tROE
READ Control to Data Bus Enable
10
10
ns
100
70
100
0
160
0
ns
ns
ns
400
160
9·129
ns
85
10
400
Note: CLOAD = 150pF
ns
ns
ns
ns
160
ns
160
ns
8355/8355-2
Figure 1. Clock Specification for 8355
elK
A8-10
101M
~
ADDRESS
'AD
A00-7
(eE,-a
~
)
ADDRESS
DATA
• eE2·1)
~
1\
'LL~
r-'LA--0/
ALE
f.- 'AL ....
r-
I+-'RDE~
'RDF·
!----'RD---
J
i+--'LC~
f+--j-'RV
'ow
I----'cc
J-- 'WD~
I---'CL~
Figure 2. ROM Read and 110 Read and Write
9·130
8355/8355-2
a. Input Mode
tJ~
ROOR
lOR
PORT~
INPUT
DATA· BUS
-
-
-
-
-
-)(
- - - - -- -
----------
b. Output Mode
twp
GLITCH FREE
/OUTPUT
PORT
OUTPUT
X"'____
...I\______...J
DATA· - '"
BUS
_____
·DATA BUS TIMING IS SHOWN IN FIGURE 4.
Figure 3. 1/0 Port Timing
Figure 4. Walt State Timing (READY
=0)
9·131
8755A
16,384-8IT EPROM WITH 1/0
•
Directly Compatible with 8085A CPU
• 2048 Words )( 8 Bits
• 2 General Purpose 8·Bit 1/0 Jlorts
• Single +5V Power Supply (Vee>
• Each 1/0 Port Line Individually
Programmable as Input or Output
• U.V. Erasable and Electrically
Reprogrammable
• Multiplexed Address and Data Bus
• Internal Address Latch
• 40·Pln DIP
The Intell!!> 87SSA is an erasable and electrically reprogram mabie ROM (EPROM I and I/O chip to be used in the MCS-8S'"
microcomputer system. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum access time of4S0 ns
to permit use with no wait states in an 808SA CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and each I/O port line is individually programmable as input or output.
BLOCK DIAGRAM
PIN CONFIGURATION
CLK
READY
A~,
PORTA
PB,
lOW
PA,
Aa-l0
CE,
2K x 8
EPROM
101M
ALE
iffi
lOW
G
G
8
RESET
lOR
PROG/eEl
Voo
9-132
Vee (+5V)
V" COV)
PA O- 7
PBo--7
675:»A
8755A FUNCTIONAL PIN DEFINITION
Symbol
Function
Symbol
Function
ALE
(input)
When Address Latch Enable goes
high, ADo-7, 101M, AS-l0, CE2, and
CEl enter the address latches. The
signals (AD, 101M, AS-l0, CE) are
latched in at the trailing edge of ALE.
READY
(output)
ADo-7
(input/output)
Bidirectional AddresslData bus. The
lower 8-bits of the PROM or 1/0
address are applied to the bus lines
when ALE is high.
READY is a 3-state output controlled
by CE2, CEl. ALE and ClK. READY
is forced low when the Chip Enables
are active during the time ALE is high,
and remains low until the rising edge
of the next ClK. (See Figure 6.)
PAO-7
(input/output)
These are general purpose I/O pins.
Their inputloutput direction is determined by the contents of Data Direction Register (DDR). PortAisselected
for write operations when the Chip
Enables are active and lOW is low
and a 0 was previously latched from
ADo, AD1.
AS-l0
(input)
PROG/CEl
CE2
(input)
During an 1/0 cycle, Port A or Bare
selected based on the latched value.of
ADo. If RD or lOR is low when the
latched Chip Enables are active, the
output buffers present data on the
bus.
These are the high order bits of the
PROM address. They do not affect
1/0 operations.
Chip Enable Inputs: CEl is active low
and CE2 is active high. The 8755A
can be accessed only when BOTH
Chip Enables are active at the time
the ALE signal latches them up. If
either Chip Enable input is not active,
the ADo-7 and READY outputs will
be in a high impedance state. CEl is
also used as a programming pin. (See
section on programming.)
101M
(input)
If the latched 101M is high when RD
is low, the output data comes from
an 1/0 port. If it is low the output data
comes from the PROM.
RD
(input)
If the latched Chip Enables are active
when RD goes low, the ADo-7 output
buffers are enabled and output either
the selected PROM location or 1/0
port. When both RDand lOR are high,
the ADo-7 output buffers are 3-stated.
lOW
(input)
If the latched Chip Enables are active,
a low on lOW causes the output port
pointed to by the latched value of
ADo to be written with the data on
ADo-7. The state of 101M is ignored.
ClK
(input)
The ClK is used to force the READY
into its high impedance state after it
has been forced low by CE110w, CE2
high, and ALE high.
Read operation is selected by either
lOR low and active Chip Enables and
ADo and ADl low, or 101M high, RD
low, active Chip Enables, and ADo
and ADllow.
PBO-7
(input/output)
This general purpose 1/0 port is
identical to Port A except that it is
selected by a 1 latched from ADo and
a 0 from AD1.
RESET
(input)
In normal operation, an input high on
RESET causes all pillS in Ports A and
B to assume input mode (clear DDR
register).
lOR
(input)
When the Chip Enables are active, a
low on lOR will output the selected
I/O port onto the AD bus. lOR low
performs the same function as the
combination of 101M high and RD
low. When lOR is not used in a system,
lOR should be tied to Vee ("1").
Vee
+5 volt supply.
Vss
Ground Reference.
Voo
Voo is a programming voltage, and
must be tied to +5V when the 8755A
is being read.
For programming, a high voltage is
supplied with Voo= 25V, typical. (See
section on programming.)
9·133
O'~~A
ERASURE CHARACTERISTICS
SYSTEM APPLICATIONS
The erasure characteristics of the 8755A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 8755A in
approximately 3 years while it would take approximately 1
week to cause erasure when exposed to direct sunlight.
If the 8755A is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels
are available from Intel which should be placed over the
8755 window to prevent unintentional erasure.
System Interface with 808SA
The recommended erasure procedure for the 8755A is
exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e.,
UV intenSity X exposure time) for erasure should be a
minimum of 15W-sec/cm2. The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000!-'W/cm2 power rating. The
8755A should be placed within one inch from the lamp
tubes during erasure. Some lamps have a filter on their
tubes and this filter should be removed before erasure.
If a memory mapped I/O approach is used the 8755A will be
selected by the combination of both the Chip Enables and
10lM using the ADs-15 address lines. See Figure 1.
A system using the 8755A can use either one of the two I/O
Interface techniques:
• Standard I/O
• Memory Mapped I/O
If a standard I/O technique is used, the system can use the
feature of both CE2 and CEI. By using a combination of
unused address lines AII-15 and the Chip Enable inputs, the
8085A system can use up to 5 each 8755A's without requiring
a CE decoder.
PROGRAMMING
Initially, and after each erasure, all bits of the EPROM
portions of the 8755A are in the "1" state. Information is
introduced by selectively programming "0" into the
desired bit locations. A programmed "0" can only be
changed to a "1" by UV erasure.
The 8755A can be programmed on the Intel® Universal
PROM Programmer (UPP), and the PROMPrM 80/85 and
PROMPT-48'· design aids. The appropriate programming
modules and adapters for use in programming both
8755A's and 8755's are shown in Table 1.
...
A
(;8-1.
8085A
?
(ADo.,
v
'I
ALE
The program mode itself consists of programming a
single address at a time, giving a single 50 msec pulse
for every address. Generally, it is desirable to have a
verify cycle after a program cycle for the same address
as shown in the attached timing diagram. In the verify
cycle (Le., normal memory read cycle) 'VDD' should
be at +5V.
I--
RD
WR
elK (~2)
READY
I-I-I--
I--
101M
Vee
*1
I--
I
rvJ
Preliminary timing diagrams and parameter values per·
taining to the 8755A programming operation are con·
tained in Figure 6.
AID ••,
iiiii
A8-10
RD elK
101M
ALE i1!W READY CE
8755A
TABLE 1. 8755A PROGRAMMING MODULE CROSS
REFERENCE
"NOTE: Optional connection.
1.
2.
3.
4.
MODULE NAME
USE WITH
UPP 955
UPP UP2(2)
PROMPT 975
PROMPT 475
UPP(4)
UPP 855
PROMPT 80/85(3)
PROMPT 48(1)
"JOTES:
Described on p. 11·9 of 1978 System Data Catalog.
Special adaptor socket.
Described on p. 11-3 of 1978 System Data Catalog.
Described on p. 10-85 of 1978 System Data Catalog.
Figure 1. 8755A in 8085A System (Memory-Mapped I/O)
9·134
8755A
ABSOLUTE MAXIMUM RATINGS*
TemperatureUnderBias .............. -10·e to +70·e
Storage Temperature ............... -65·e to +150·e
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . . . .. -0.5 to +7V'
Power Dissipation ............................. 1.5W
'COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
'Except for programming voltage.
D.C. CHARACTERISTICS
(TA = oOe to 70°C; VCC = 5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vcc tO.5
V
VOL
Output Low Voltage
VOH
Output High Voltage
TEST CONDITIONS
IlL
Input leakage
10
/lA
= 2mA
= -400/lA ,l
VIN = Vcc to OV
ILO
Output leakage Current
±10
p.A
0.45V ";;VOUT ..;;vcc
ICC
VCC Supply Current
180
mA
A.C. CHARACTERISTICS
SYMBOL
V
0.45
ITA
IOL
V
2.4
IoH
= o°c to 70°C; VCC = 5V ± 5%)
PARAMETER
MIN.
MAX.
UNITS
tCYC
Clock Cycle Time
320
T1
ClK Pulse Width
80
ns
T2
ClK Pulse Width
120
ns
ns
tf.tr
ClK Rise and Fall Time
tAL
Address to Latch Set Up Time
50
ns
tLA
Address Hold Time after Latch
80
ns
tLC
Latch to R EADIWR ITE Control
100
ns
30
Valid Data Out Delay from READ Control
170
ns
tAD
Address Stable to Data Out Valid
450
ns
tLL
Latch Enable Width
tRDF
Data Bus Float after READ
100
150 pF Load
ns
100
ns
tCL
READ/WRITE Control to Latch Enable
20
ns
tcc
READ/WRITE Control Width
250
ns
tow
Data In to WR ITE Set Up Time
150
ns
two
Data In Hold Time After WR ITE
30
twp
WR ITE to Port Output
tpR
Port Input Set Up Time
50
ns
tRP
Port Input Hold Time
50
ns
tRYH
READY HOLD TIME
0
tARY
ADDRESS (CE) to READY
tRV
Recovery Time between Controls
tROE
Data Out Delay from READ Control
tLO
ALE to Data Out Valid
ns
400
ns
160
ns
160
ns
300
ns
10
ns
350
9-135
CLOAO = 150 pF
(See Figure 3)
ns
tRD
0
TEST CONDITIONS
ns
Preliminary
8755A
WAVEFORMS
Figure 2. Clock Specification for 8755A
AS-l0
)
ADDRESS
l(
ADDRESS
tAD
ADQ.-7
)
ADDRESS
~--~
,.....-----.
)
>----~
DATA
1-
r-
tLL_
_
\
/
>-
I
ALE
(PROG)/CE,
ADDRESS
tAL_
!+---tLA _
,
tLD
\.
-----
\
-----
_tRDE
tRDF
I--
r-----
rtwD
I
~tLe_
I--- tRP
tDW
~
~
tee
I--teL-
Please note that CE1 must remain low for the entire cycle.
tRV
Figure 3. PROM Read, 1/0 Read and Write Timing
9·136
8755A
A. INPUT MODE
RDOR
lOR
PORT
INPUT
DATA' BUS
-
-
-
-
-
-
)<
------- --------------------
B. OUTPUT MODE
_ _ _ _ _ _ _ _ _ _ ~-_--t.-.j /
GLITCH FREE
OUTPUT
PORT
OUTPUT
X\,_______
-A_______..J
DATA' - '"
BUS
_____
'DATA BUS TIMING IS SHOWN IN FIGURE 4.
Figure 4. 1/0 Port Timing
Figure 5. Wait State Timing (READY
=0)
9-137
8755A
D.C. SPECIFICATION PROGRAMMING
(TA = aoe to 7aoe; Vee = 5V
± 5%;
Symbol
Vss = aV)
Parameter
Voo
Programming Voltage (during Write
to EPROM)
100
Prog Supply Current
Min.
Typ.
Max.
Unit
24
25
15
26
30
mA
Typ.
Max.
Unit
V
A.C. SPECIFICATION FOR PROGRAMMING
(TA = aoe to 7aoe; Vee = 5V
± 5%;
Symbol
Vss = aV)
Parameter
IpS
Data Setup Time
tpo
Data Hold Time
ts
Prog Pulse Setup Time
tH
Prog Pulse Hold Time
tPR
Prog Pulse Rise Time
tPF
Prog Pulse Fall Time
tpRG
Prog Pulse Width
Min.
10
0
2
2
0.01
0.01
45
9-138
ns
ns
JlS
Jls
2
2
50
Jls
Jls
msec
8755A
WAVEFORMS
FUNCTION
1....." " " " " - - - - - - - PROGRAM CYCLE - - - - - - -....-11....< - - - - - VERIFY CYCLE'
----l-
ALE
DATA TO BE
PROGRAMMED
A/DO·7
tpo
AB·10
PROG/CE,
tps
+25
VDD
+5---------------------------(
\J-"VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE (WITH VOO '" +5V FOR 8755Aj
Figure 6. 8755A Program Mode Timing Diagram
9·139
PROGRAM CYCLE
MCS-86™
Microprocessor 10
MCS-S6 MICROPROCESSOR
TABLE OF CONTENTS
8086/8086-4
828218283
8284
8286/8287
8288
16-Bit HMOS Mic~oprocessor ............................................................. 10-4
Octal Latch ........................................................................... 10-23
Clock Generator and Drive for 8086 CPU .................................................. 10-27
Octal Bus Transceiver ................................................................. 10-33
Bus Controller for the 8086 CPU ......................................................... 10-37
10-2
operations, and improved bit manipulation. Significantly, they also include mechanisms for such minicomputer·type operations as reentrant code, positionindependent code, and dynamically relocatable pro·
grams. In addition, the processor may directly address
up to 1 megabyte of memory and has been designed to
support multiple-processor configurations.
THE MCS·86 MICROPROCESSOR
FAMILY
INTRODUCTION
The Intel@ 8086, a new microcomputer, extends the midrange 8080 family into the 16-bit arena. The chip has at·
tributes of both 8- and 16-bit processors. By executing
the full set of 8080A/8085 8-bit instructions plus a
powerful new set of 16-bit instructions, it enables a sys·
tem designer familiar with existing 8080 devices to
boost performance by a factor of as much as 10 while
using essentially the same 8080 software package and
development tools.
Support for the 8086 is provided by offering a complete
line of bipolar components: clock generator, octal
latches, octal transceivers, and a bus controller. Exist·
ing 8-bit peripherals and memories can be used to build
your complete system. A configuration option in the
8086 allows a complete 16·bit system to be built with as
little as 11 components (including memory and I/O).
The goals of the 8086 architectural design were to extend existing 8080 features symmetrically, across the
board, and to add processing capabilities not to be
found in the 8080. The added features include 16-bit
arithmetic, signed 8- and 16-bit arithmetic (including
multiply and divide), efficient interruptible byte-string
FURTHER INFORMATION
For more detailed information on the MCS-86 microcomputer family please consult the following Intel publica·
tion: MCS-86 User's Manual (order number 9800722A).
RECOMMENDED PRODUCTS FOR MCS-86 MICROCOMPUTER APPLICATIONS
Function
Part
No.
Description
Page No.
RAMs (Static)
2114
2141
2142
2148
3-54
3-89
3·95
3-106
1Kx 4
4Kx 1
1Kx4
1K x 4 High Speed
RAMs (Dynamic)
2117
2118
3·64
3-88
16K x 1
16Kx 1
RAM Support
8202
11·14
Dynamic RAM Controller
ROMs
2316E
4·12
2Kx8
EPROMs
2716
2732
4·23
4·28
2Kx8
4Kx8
Microprocessor Support
8205
8257·5
8259A
E282
8283
8284
8286
8287
8288
9-29
9·92
9-109
10·23
10·23
10·27
10·33
10·33
10·37
1·of·8 Decoder
DMA Controller
Interrupt Controller
8-Bit Non-Inverting Latch
8-Bit Inverting Latch
Clock Generator
8·Bit Non·lnverting Transceiver
8·Bit Inverting Transceiver
Bus Controller
Peripherals
8251A
8253·5
8255A·5
8271
8273
8275
8278
8279·5
8291
8292
8294
8295
8041/8741
11·24
11·32
11-43
11-64
11·93
11·118
11·142
11-152
11-164
11·188
11·190
11·201
11·3
USART
Counter/Timer
Programmable Peripheral Interface
Floppy Disk Controller
Communications Controller
CRT Controller
KeyboardlDisplay Controller
KeyboardlDisplay Controller
GPIB Talker/listener
GPIB Controller
Data Encrypter
Dot Matrix Printer Controller
Universal Peripheral Interface
10·3
8086/8086·4
16·811 HMOS MICROPROCESSOR
Direct Addressing Capability to 1
• MByte
of Memory
• Bit, Byte, Word, and Block Operations
16·Bit Signed and Unsigned
• 8·and
Arithmetic in Binary or Decimal
Assembly Language Compatible with
• 8080/8085
Including Multiply and Divide
14 Word, By 16·Bit Register Set with
• Symmetrical
Operations
• 5 MHz Clock Rate (4 MHz for 8086·4)
System Compatible
• MULTIBUS™
Interface
• 24 Operand Addressing Modes
The Intel@ 8086 is a new generation, high performance microprocessor implemented in N-channel, depletion load,
silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributes of both 8- and
16-bit microprocessors. It addresses memory as a sequence of 8-bit bytes, but has a 16-bit wide physical path to memory for high performance.
EXECUTION UNIT
BUS INTERFACE UNIT
REGISTER FilE
I R~~\~i't~'~~E I
DATA,
POINTER, AND
INDEX REGS
(8 WORDS)
r--"'"'<--O-_BHEIS7
A1!'SS
Al6tS3
6·BYTE
INSTRUCTION
QUEUE
GND
VCC
AD14
AD15
AD13
A161S3
AD12
A171S4
AD11
A18/S5
AD10
A191S6
AD9
BHEIS7
AD8
MNIMX
AD7
Rli
AD6
Rellm (HOLD)
AD5
ROIGT1 (HlDA)
AD4
lOCK
(WR)
AD3
52
(MliO)
AD2
51
(DTlR)
AD1
So
(DEN)
ADO
aso
(ALE)
NMI
aS1
(INTA)
INTR
TEST~_r-----"'""-----,
INT~_
NMI~-
TEST
ClK
READY
GND
RESET
CONTROL & TIMING
RCfGTO":1W
HOLD~
40 LEAD
HLDA----L-r_-r_-r--_-.-----:~
eLK
RESET
READY
GND
Vee
Figure 2. 8086 Pin Diagram
Figure 1. 8086 CPU Functional Block Diagram
10-4
8086/8086·4
FUNCTIONAL DESCRIPTION
GENERAL OPERATION
The internal functions of the 8086 processor are partitioned logically into two processing units_ The first is
the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of Figure
1.
A 19- A1. Byte data with even addressh:!s}r.~nsferred
on the DrDo bus lines while odd a~tffesse(f:~~~ata
(Ao HIGH) Is transferred on the D15-O'ebllS, hl'l-.,kltoe "
processor provides two enable signals, BHE,~nQ, Ad:,'
selectively allow reading from or writing into 'either,an" j."~"
odd byte location, even byte location, or both'. T~,e ,,,
instruction stream is fetched from memory as wards ""
and is addressed internally by the processor to the byte
level as necessary.
4 ,;, ":
These units can interact directly but for the most part
perform as separate asynchronous operational proces·
sors. The bus interface unit provides the functions
related to instruction fetching and queuing, operand
fetch and store, and address relocation. This unit also
provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase
processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream
can be queued while waiting for decoding and execution.
The instruction stream queuing mechanism allows the
BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the
BIU will attempt a word fetch memory cycle. This greatly
reduces "dead time" on the memory bus. The queue
acts as a Flrst·ln-First-Out (FIFO) buffer, from which the
EU extracts instruction bytes aSJequired. If the queue is
empty (following a branch instruction, for example), the
first byte into the queue immediately becomes avaiiable
to the EU.
..r----:J- FFFFFH
T
r---'
l
XXXXOH
~
+01
SEGMENT
REGISTER FILE
CS
SS
OS
ES
v--
-
} STACK SEGMENT
SET
I
I
tr
~
The execution unit receives pre-fetched instructions
from the BIU queue and provides un-relocated operand
addresses to the BIU. Memory operands are passed
through the BIU for processing by the EU, which passes
results to the BIU for storage. See the Instruction Set
description for further register set and architectural
descriptions.
I
CODE SEGMENT
6 KB
DATA SEGMENT
EXTRA DATA SEGMENT
"'C-.--:I""OOOOOH
MEMORY ORGANIZATION
The processor provides a 20-bit address to memory
which locates the byte being referenced. The memory is
logically organized as a linear array of 1 million bytes,
addressed as OOOOO(H) to FFFFF(H). The memory can be
further logically divided Into code, data, alternate data,
and stack segments of up to 64K bytes each, with each
segment failing on 16-byte boundaries. (See Figure 3a.)
Word (16-blt) operands can be located on even or odd
address boundaries and are thus not constrained to
even boundaries as is the case in many 16·bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued
address location and the most significant byte in the
next higher address location. The BIU automatically per·
forms the proper number of memory accesses, one if
the word operand is on an even byte boundary and two if
it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the
software. This performance penalty does not occur for
instruction fetches, only word operands.
Physically, the memory is organized as a high bank
(D 15-Da) and a low bank (DrOol of 512K 8-blt bytes
addressed in parallel by the processor's address lines
10-5
Figure 38. Memory Organization
In referencing word data the BIU requires one or two
memory cycles depending on whether or not the starting byte of the word is on an even or odd address,
respectively. Consequently, in referencing word operands performance can be optimized by locating data on
even address boundaries. This is an especially useful
technique for using the stack, since odd address references to the stack may adversely affect the context
switching time for interrupt processing or task multiplexing.
Certain locations in memory are reserved for specific
CPU operations (see Figure 3b.) Locations from address
FFFFOH through FFFFFH are reserved for operations
including a jump to the initial program loading routine.
Following RESET, the CPU will always begin execution
at location FFFFOH where the Jump must be. Locations
OOOOOH through 003FFH are reserved for interrupt
operations. Each of the 256 possible interrupt types has
its service routine pointed to by a 4-byte pointer element
consisting of a 16·bit segment address and a 16·bit offset address. The pointer elements are assumed to have
been stored at the respective places in reserved memory
prior to occurrence of interrupts.
8086/8086·4
MINIMUM AND MAXIMUM'MODES
FFFFFH
RESET BOOTSTRAP
PROGRAM JUMP
The requirements for supporting minimum ~~ .IT1aximum 8086 systems are sufficiently differeNt tJ'laf'they
cannot be done efficiently with 40 uniquely defined: .'.'.'.,
pins, Consequently, the 8086 is equipped with a ,strap , ':,
pin (MN/MX) which defines the system configuration.
The definition of a certain subset of the pins changes
dependent on the condition of the strap pin. When
MN/MX pin is strapped to GND, the 8086 treats pins 24
through 31 in maximum mode. An 8288 bus controller
interprets status information coded into 80,8 1,82 to generate bus timina and control siQ!!!!ls compatible with
the MULTIBUST . When the MN/MX pin is strapped to
Vee, the 8086 generates bus control signals itself on'
pins 24 through 31, as shown in parentheses in Figure 2.
Examples of minimum mode and maximum mode
systems are shown in Figure 4.
FFFFOH
3FFH
INTERRUPT POINTER
FOR TYPE 255
.
3FCH
~------------'7H
INTERRUPT POINTER
FOR TYPE 1
~-IN-TE-R-RU-P-T-PO-IN-T-E-R~ ~~
~
FOR TYPE 0
____________
~OH
Figure 3b. Reserved Memory Locations
D
lUi
Vee
8284 CLOCK
GENERATOR
IlE!
f-
I
GND
-----
MNIMX
ClK
MilO
READY
iNTA
Rii
c- RESET
ROY
r-l--,
I
I
WAIT
STATE
I
I
I GENERATOR I
L ___ ...l
-Vee
'l
1
WI!
DTIA
I
I
I
I
I
I
I
,-----,
-DEN '- - - , I
r-----,
I I
I I
8086 CPU
ALE
GND
I I
I I
I
oe
~
ADo-A D15 I~DDRIDATA
A16-A19
ii'HE r--
I I
I I
I L
I
STB
I
I
6262
lATCH
2 OR 3
ADDR
t
I
I
I
I
I
J!=---:l
T----' I
L-....I oe
II
TRAN8:~IVER I
:
(2)
L ___
f
: IBHE
OPTIONAL
FOR INCREASED
DATA BUS DRIVE
lli 11
CSOH
CSOL
Figure 4a. Minimum Mode 8086 Typical System Configuration
WEOD
2142 RAM (4)
(2)
1Kx8
10-6
I
DATA
I
(2)
1KxS
11 1fl 11
CE
OE
2716·2 PROM (2)
2Kx8
I
2KxS
CS
RDWR
MCS.ao
PERIPHERAL
8086/8086·4
I
I
GND
D
ill,
8284
CLOCK
GENERATOR
liES
I
MNIMX
.... CLK
_
READY
RESET
I
I WAIT
I STATE I
I GENERATOR I
L ___ -l
MRDC
So
So
MWTC
S,
S,
-
AMWC f--N.C.
DTIA
AIOWC f--N.C.
52
8288
10RC
SUS _
DEN CTRLR 10WC
S,
,---
RDY
r- 1 -.,
CLK
t-GND
-
8086
CPU
-
ALE
-
GND
ADo-AD15
A16- A 19
IffiE
INTA
r---:l
LOCK I--N.C.
I~DDRIDATA
I
I
STS
OE
V
I
8282
LATCH
(2 OR 3)
~DDR
~~
r---
Lt;:
T
OE
8286
TRANSCEIVER
(2)
.J\
DATA
SHE
CSOH
11f 11
h'11
CSO,
WE OD
CE
2142 RAM (4)
(2)
1Kx8
I
OE
2716·2 PROM (2)
(2)
1Kx8
2Kx8
I
CS
liD WI!
MCS·80
PERIPHERAL
2Kx8
Figure 4b. Maximum Mode 8086 Typical System Configuration
Status bits So, S1, and S2 are used, in maximum mode,
by the bus controller to identify the type of bus transac·
tion according to the following table:
BUS OPERATION
The 8086 has a combined address and data bus com·
monly referred to as a time multiplexed bus. This tech·
nique provides the most efficient use of pins on the
processor while permitting the use of a standard 40·lead
package. This "local bus" can be buffered directly and
used throughout the system with address latching pro·
vided on memory and 1/0 modules. In addition, the bus
can also be demultiplexed at the processor with a single
set of address latches if a standard non·multiplexed bus
is desired for the system.
S2
S;
So
o (lOW)
0
0
0
1
0
1
0
1
0
1
0
0
0
1 (HIGH)
1
1
1
Each processor bus cycle consists of at least four ClK
cycles. These are referred to as T 1, T 2, T3 and T 4 (see
Figure 5). The address is emitted from the processor
during T 1 and data transfer occurs on the bus during T3
and T4' T2 is used primarily for changing the direction of
the bus during read operations. In the event that a "NOT
READY" indication is given by the addressed device,
"Wait" states (Tw) are inserted between T3 and T 4' Each
inserted "Wait" state is of the same duration as a ClK
cycle. Periods can occur between 8086 driven bus
cycles. These are referred to as "Idle" states (T,) or inac·
tive ClK cycles. The processor uses these cycles for
internal housekeeping.
1
0
0
1
1
1
Interrupt Acknowledge
Read I/O
WriteI/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
Status bits S3 through S7 are multiplexed with high·
order address bits and the BHE signal, and are therefore
valid during T 2 through T 4. S3 and S4 indicate which
segment register (see Instruction Set description) was
used for this bus cycle in forming the address, accord·
ing to the following table:
o (lOW)
o
During T1 of any bus cycle the ALE (Address latch
Enable) signal is emitted (by either the processor or the
8288 bus controller, depending on the MN/MX strap). At
the trailing edge of this pulse, a valid address and cer·
tain status information for the cycle may be latched.
1 (HIGH)
1
o
1
o
1
Alternate Data (extra segment)
Stack
Code or None
Data
S5 is a reflection of the PSW interrupt enable bit. S6
and S7 is a spare status bit.
10·7
=0
8086/8086·4
.,:
'
'::"1; ,':
~
- :'
1-------f4+NwAITl=rCy-------l'I-'------14+NwAITJ=rov-----T,
T2
T3
TWAIT
T4
T,
T2
T3
TWAIT!
T4
elK
GOES INACTIVE IN THE STATE
':::~'-----L.J../~~YU/ffff~ ~'.
AOOAISTATUS
-----E)('--__
ADORIOATA
DA_T_A_OU_T_(D_,,_-D_,)_ _
~>--~
READY
DllR
DEN
- - MEMORY ACCESS TIME
\L--_--I/
WP
Figure 5, Basic System Timing
07-00 bus lines and odd addressed bytes on 0 15-08'
Care must be taken to assure that each register within
an 8-bit peripheral located on the lower portion of the
bus be addressed as even.
1/0 ADDRESSING
In the 8086, I/O operations can address up to a maximum of 64K I/O byte registers or 32K I/O word registers.
The I/O address appears in the same format as the
memory address on bus lines A15-A o. The address lines
A 19-A 16 are zero in I/O operations. The variable I/O instructions which use register OX as a pOinter have full
address capability while the direct I/O instructions
directly address one or two of the 256 I/O byte locations
in page 0 of the I/O address space.
EXTERNAL INTERFACE
PROCESSOR RESET AND INITIALIZATION
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8086 RESET is
required to be HIGH for greater than 4 ClK cycles. The
I/O ports are addressed in the same manner as memory
locations. Even addressed bytes are transferred on the
10-8
808618086·4
8086 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is
HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 10 ClK cycles.
After this interval the 8086 operates normally beginning
with the instruction In absolute location FFFFOH (see
Figure 3b). The details of this operation are specified in
the Instruction Set description of the MCS-86 Users'
Manual. The RESET input is internally synchronized to
the processor clock. At initialization the HIGH-to-lOW
transition of RESET must occur no sooner than 50 I-IS
after power-up, to allow complete initialization of the
8086.
NON·MASKABLE
INTERRUPT OPERATIONS
Interrupt operations fall into two classes; software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in
the Instruction Set description. Hardware interrupts can
be classified as non-maskable or maskable.
MASKABLE INTERRUPT (INTR)
The 8086 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable FLAG status bit. The
interrupt request Signal Is level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of ClK. To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a
block-type instruction. During the interrupt response
sequence further interrupts are disabled. The enable bit
is reset as part of the response to any interrupt (INTR,
NMI, software interrupt or single-step), although the
Interrupts result in a transfer of control to a new program location. A 256-element table containing address
pOinters to the interrupt service program locations
resides in absolute locations 0 through 3FFH (see
Figure 3b), which are reserved for this purpose. Each
element in the table is 4 bytes in size and corresponds
to an interrupt "type". An interrupting device supplies
an 8-bit type number, during the interrupt acknowledge
sequence, which is used to "vector" through the appropriate element to the new interrupt service program
location.
ALE
T,
I
T.
T.
T.
T,
I
T.
T.
Jl'-----_----In_____
\'---_---..../
ADo-AD,.
,,,
NMI Is required to have a duration in the HIGH state of
greater than two ClK cycles, but is not required to be
synchronized to the clock. Any high-going transition of
NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves of a
block-type instruction. Worst case 'response to NMI
would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the
low-going edge; it may occur before, during, or after the
servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure. The signal must be free of logical spikes in
general and be free of bounces on the lo:.v:going edge to
avoid triggering extraneous responses.
If INTR is asserted sooner than 9 ClK cycles after the
end of RESET, the processor may execute one instruction before responding to the interrupt. NMI may not be
asserted prior to the 2nd ClK cycle following the end of
RESET.
I
INTERRb~ti
The processor provides a single n~~~,sk:
pin (NMI) which has higher priority than 't~,
terrupt request pin (INTR). A typical use wotr~,
tivate a power failure routine. The NMI is edge-iriflg~~"
on a lOW·to-HIGH transition. The activation of this Pm '
causes a type 2 interrupt. (See Instruction Set description.)
FLOAT
Figure 8. Interrupt Acknowledge Sequence
10-9
T.
8086/8086·4
FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the
interrupt. Until the old FLAGS register Is restored the
enable bit will be zero unless specifically set by an
instruction.
During the response sequence (figure 6) the processor
executes two successive (back-to-back) interrupt
acknowledge cycles. The 8086 emits the LOCK signal
from T2 of the first bus cycle until T2 of the second. A
local bus "hold" request will not be honored until the
end of the second bus cycle. In the second bus cycle a
byte is fetched from the external interrupt system (e.g.,
8259A PIC) which identifies the source (type) of the
interrupt. This byte is multiplied by four and used as a
pOinter into the interrupt vector lookup table. An INTR
signal left HIGH will be continually responded to within
the limitations of the enable bit and sample period. The
INTERRUPT RETURN instruction includes a FLAGS pop
which returns the status of the original interrupt enable
bit when it restores the FLAGS.
HALT
When a software "HALT" instruction is executed the
processor indicates that it is entering the "HALT" state
in one of two ways depending upon which mode is
strapped. In minimum mode, the processor issues one
ALE with no qualifying bus control signals. In Maximum
Mode, the processor issues appropriate HALT status on
5251So and the 8288 bus controller issues one ALE. The
8086 will not leave the "HALT" state when a local bus
"hold" is entered while in "HALT". In this case, the
processor reissues the HALT indicator. An interrupt
request or RESET will force the 8086 out of the "HALT"
state.
READ/MODIFYIWRITE (SEMAPHORE)
OPERATIONS VIA LOCK
The LOCK status information is provided by the processor when directly consecutive bus cycles are required
during the execution of an instruction. This provides the
processor with the capability of performing read/modify/
write operations on memory (via the Exchange Register
With Memory instruction, for example) without the
possibility of another system bus master receiving
intervening memory cycles. This is useful in multip~ocessor system configurations to accomplish "test
and set lock" operations. The LOCK signal is activated
(forced LOW) in the clock cycle following the one in
which the software "LOCK" prefix instruction is
decoded by the EU. It is deactivated at the end of the
last bus cycle of the instruction following the "LOCK"
prefix instruction. While LOCK is active all interrupts
are masked and a request on a RQ/GT pin will be
recorded and then honored at the end of the LOCK.
rElin~11 ~t'~t.~.f1'.
to become active. It must
CLK cycles. The WAIT instructloir .ill '
repeatedly until that time. This acti\irty'.~,d0,,»
- ,
sume bus cycles. The processor remains InaJ"Jo,Il~ s
~h
while waiting. All 8086 drivers go to 3-state O'f\fil.lf'o,u.,~ '4")r'a
"Hold"is entered. If Interrupts are enabled, they' m,~Y' S", .,
occur while the processor Is waiting. When this occu'rs t".;
the processor fetches the WAIT Instruction one extra
time, processes the interrupt, and then re-fetches and
re-executes the WAIT Instruction upon returning from
the interrupt.
8086 COMPARED WITH 8080/8085
While the 8086 has new instruction coding patterns to
allow for the greatly expanded capabilities, all functions
of the 8080/8085 may be performed by the 8086 with
identical program semantics to their 8080/8085 versions. For every 8080/8085 Instruction there is a corresponding 8086 instruction (or, in rare cases, a short
sequence of instructions). Virtually all 8086 data manipulation instructions may be specified to operate on
either the full set of 16-bit registers or on an 8-bit subset
of them which corresponds to the 8080 register set. This
relationship is shown in Figure 7 where the shaded
registers (names in parentheses) represent the 8080
register set.
BASIC SYSTEM TIMING
Typical system configurations for the processor
operating in minimum mode and in maximum mode are
shown in Figures 4a and 4b, respectively. In minimum
mode, the MN/MX pin is strapped to Vee and the processor emits bus control signals in a manner similar to
the 8085. In maximum mode, the MN/MX pin is strapped
to Vss and the processor emits coded status information which the 8288 bus controller uses to generate
MULTIBUSTM compatible bus control Signals. Figure 5
illustrates the signal timing relationships.
ACCUMULATOR
BASE
COUNT
DATA
~
p
SI
SOURCE INDEX
DI
DESTINATION INDEX
~~I~~(PC)
EXTERNAL SYNCHRONIZATION VIA TEST
STACK POINTER
BASE POINTER
FLAGS"
As an alternative to the Interrupts and general I/O
capabilities, the 8086 provides a single softwaretestable input known as the TEST signal. At any time the
program may execute a WAIT instruction. If at that time
the TEST signal is inactive (HIGH), program execution
becomes suspended while the processor waits for TEST
(SP)
BP
FLAGSL
INSTRUCTION POINTER
(PSW) STATUS FLAGS
CS
CODE SEGMENT
DS
DATA SEGMENT
SS
STACK SEGMENT
ES
EXTRA SEGMENT
Figure 7. 8086 Register Model; (8080 Registers Shaded)
10-10
8086/8086·4
..',.,
/.
,
SYSTEM TIMING - MINIMUM SYSTEM
The read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low·
going) edge of this signal is used to latch the address
Information, which Is valid on the local bus at this time,
into the 828218283 latch. The ~ and Ao signals
address the low, high, or both bytes. From T1 to T4 the
M/iO signal Indicates a memory or flO operation. At T2
the address is removed from the local bus and the bus
goes to a high Impedance state. The read control signal
Is also asserted at T2. The read (RD) signal causes the
addressed device to enable its data bus drivers to the
local bus. Some time later valid data will be available on
the bus and the addressed device will drive the READY
line HIGH. When the processor returns the read signal
to a HIGH level, the addressed device will again 3-state
Its bus drivers. If a transceiver (8286/8287) is required to
buffer the 8086 local bus, signals DTiFf and DEN are pro·
vlded by the 8086.
The BHE and Ao signals are used to select the proper
byte(s) of the memoryliO word to be read or written
according to the following table:
AD
0
0
0
0
";'1
.'
,I
"':':"~ ",,'I.'
flO ports are addressed In the'~mei,1'i,"~r,~,memory
location. Even addressed bytes "lire ,transfer ""
the
0 7-0 0 bus lines and odd addressed D'Y~~'o~"
The basic difference between the inte('::up.t,;;,'"
edge cycle and a read cycle is that the 'in~(fll~~,
acknowledge signal (INTA) is asserted in place oh~'
. read (Fro) signal and the address bus is floated. (See
Figure 6.) In the second of two successive INTA cycles,
a byte of information is read from bus lines 0 7-0 0 as
supplied by the interrupt system logic (i.e., 8259A Priority Interrupt Controller). This byte identifies the source
(type) of the interrupt. It is multiplied by four and used
as a pOinter Into an interrupt vector lookup table, as
described earlier.
A write cycle also begins with the assertion of ALE and
the emission of the address. The M/iO signal is again
asserted to indicate a memory or I/O write operation. In
the T2 immediately following the address emission the
processor emits the data to be written into the
addressed location. This data remains valid until the
middle of T4' During T2, T3, and Tw the processor asserts
the write control signal. The write (WR) signal becomes
active at the beginning of T2 as opposed to the read
which is delayed somewhat into T2 to provide time for
the bus to float.
BHE
..'
BUS TIMING -
MEDIUM COMPLEXITY SYSTEMS
For medium complexity systems the MN/MX pin is connected to Vss and the 8288 Bus Controller is added to
the system as well as an 8282/8283 latch for latching the
system address, and a 8286/8287 transceiver to allow for
bus loading greater than the 8086 is capable of handling.
Signals ALE, DEN, and DT/R are generated by the 8288
instead of the processor in this configuration although
their timing remains relatively the same. The 8086 status
outputs (S'2, 8" and So) provide type-of-cycle information
and become 8288 inputs. This bus cycle information
specifies read (code, data, or I/O), write (data or flO),
interrupt acknowledge, or software halt. The 8288 thus
issues control signals specifying memory read or write,
flO read or write, or interrupt acknowledge. The 8288
provides two types of write strobes, normal and
advanced, to be applied as required. The normal write
strobes have data valid at the leading edge of write. The
advanced write strobes have the same timing as read
strobes, and hence data isn't valid at the leading edge of
write. The 8286/8287 transceiver receives the usual T
and OE Inputs from the 8288's DTiFi and DEN.
The pointer into the interrupt vector table, which is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8259A Priority Interrupt Controller is
positioned on the local bus, a TTL gate is required to
disable the 8286/8287 transceiver when reading from the
master 8259A during the interrupt acknowledge
sequence and software "poll".
Whole word
Upper byte froml
to odd address
Lower byte froml
to even address
None
10-11
808618086·4
8086 FUNCTIONAL PIN DEFINITION
The following pin function descriptions are for 8086
systems In either minimum or maximum mode. The
"Local Bus" In these descriptions Is the direct multi·
plexed bus Interface connection to the 8086 (without
regard to additional bus buffers).
AD1S-ADo (INPUT/OUTPUT 3-STATE)
These lines constitute the time muUiplexed memoryllO
address (T 1) and data (T2, T3, Tw, T4) bus. Ao is analogous
to SHE for the lower byte of the data bus, pins D,Do. It
is LOW during T1 when a byte is to be transferred on the
lower portion of the bus in memory or 110 operations.
Eight-bit oriented devices tied to the lower half would
normally use Ao to condition chip select functions. (See
table on page 8.) These lines are active HIGH and float to
3-state OFF during interrupt acknowledge and local bus
"hold acknowledge".
Alg1Se, Ale/Ss, A 11/S4 , A1e/S3 (OUTPUT 3-STATE)
During T1 these are the four most significant address
lines for memory operations. During 110 operations
these lines are LOW. During memory and 110 operations,
status information is available on these lines during T2,
T3, Tw, and T4. The status of the interrupt enable FLAG
bit (Ss) is updated at the beginning of each CLK cycle.
A17/S4 and A1f1S3 are encoded as follows:
A1~S4
o (LOW)
o
1 (HIGH)
1
Ss Is 0 (LOW"
Alternate Data
Stack
Code or None
Data
This information indicates which relocation register is
presently being used for data accessing.
These lines float to 3-state OFF during local bus "hold
acknowledge".
BlfEIS7 (OUTPUT 3-STATE)
During T1 the bus high enable signal (SHE) should be
used to enable data onto the most significant half of the
data bus, pins 0 15-0 8 . Eight-bit oriented devices tied to
the upper half of the bus would normally use SHE to
condition chip select functions. SHE is LOW during T1
for read, write, and interrupt acknowledge cycles when a
byte is to be transferred on the high portion of the bus.
(See table on page 8.) The S7 status Information is available during T2, T3, and T4. The signal is active LOW, and
floats to 3-state OFF in "hold". It is LOW during T1 for
the first interrupt acknowledge cycle.
READY (INPUn
READY is the acknowledgem.ent from the addressed
memory or 110 device that It will complete the data
transfer. The ROY signal from memoryllO is synchronized by the 8284 Clock Generator to form READY. This
signal is active HIGH.
INTR (IN PUn .
Interrupt request Is a level triggered input which is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt
acknowledge operation. A subroutine is vectored to via
an interrupt vector lookup table located in system
memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.
TEST (INPUn
The TEST input is examined by the "Wait For Test"
instruction. If the TEST input is LOW execution continues, otherwise the processor waits in an "Idle" state.
This Input Is synchronized ipternally during each clock
cycle on the leading edge frf eLK.
NMI(INPUn
Non-maskable interrupt Is an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via
an interrupt vector lookup table located in system
memory. NMI is not maskable internally by software. A
transition from a LOW to HIGH initiates the interrupt at
the end of the current instruction. This input is internally synchronized.
RESET (IN PUn
RESET causes the processor to Immediately terminate
its present activity. The signal must be active HIGH for
at least four clock cycles. It restarts execution, as
described in the Instruction Set description, when
RESET returns LOW. RESET is internally synchronized.
elK (lNPUn
The clock provides the basic timing for the processor
and bus controller. It Is asymmetric with a 33% duty
cycle to provide optimized internal timing.
Vee
RD (OUTPUT 3-STATE)
Vce is the
Read strobe indicates that the processor is performing a
memory or 110 read cycle, depending on the state of the
52 pin. This signal is used to read devices which reside
GND
+ 5V ± 10% power supply pin.
GND are the ground pins
10-12
8086/8086·4
The following pin function descriptions are for the 8086
minimum mode (i.e., MN/MX=Vcc). Only the pin func·
tions which are unique to minimum mode are described;
all other pin functions are as described above.
MilO (OUTPUT 3·STATE)
This status line is logically equivalent to S2 in the max·
imum mode. It is used to distinguish a memory access
from an I/O access. M/iO becomes valid in the T4
preceding a bus cycle and remains valid until the final T4
of the cycle (M = HIGH, 10 = LOW). M/iO floats to 3·state
OFF in local bus "hold acknowledge".
WR (OUTPUT 3·STATE)
Write strobe indicates that the processor is performing
a write memory or write 110 cycle, depending on the
state of the M/j() signal. WR is active for T2, T3 and Tw of
any write cycle. It is active LOW, and floats to 3-state
OFF in local bus "hold acknowledge".
DTfR (OUTPUT 3·STATE)
"
Data transmit/receive is needed in rriiniiPu~.~Y~~'""at
desires to use an 8286/8287 data bus transceiver'. lM~.:.
used to control the direction of data flow thr~ugn· th~""
transceiver. Logically DT/A is equivalent to
In· the...
maximum mode, and its timing is the same as for.
MIIO.(T= HIGH, R= LOW.) This signal floats to 3-state
OFF in local bus "hold acknowledge".
57
DEN (OUTPUT 3·STATE)
Data enable is provided as an output enable for the
8286/8287 in a minimum system which uses the
transceiver. DEN is active LOW during each memory and
1/0 access and for INTA cycles. For a read or INTA cycle
it is active from the middle of T2 until the middle of T 4,
while for a write cycle it is active from the beginning of
T2 until the middle of T4. DEN floats to 3·state OFF in
local bus "hold acknowledge".
INTA (OUTPUT 3·STATE)
HOLD (INPUT), HLDA (OUTPUT)
INTA is used as a read strobe for interrupt acknowledge
cycles. It is active LOW during T2, T3 and Tw of each
interrupt acknowledge cycle. INTA floats to 3-state OFF
in "hold acknowledge".
HOLD indicates that another master is requesting a
local bus "hold". To be acknowledged, HOLD must be
active HIGH. The processor receiving the "hold"
request will issue HLDA (HIGH) as an acknowledgement
in the middle of T 4 or T,. Simultaneous with the
issuance of HLDA the processor will float the local bus
and control lines. After HOLD is detected as being LOW,
the processor will LOWer HLDA, and when the processor needs to run another cycle, it will again drive the
local bus and control lines. (See Figure 13.)
ALE (OUTPUT)
Address latch enable is provided by the processor to
latch the address into the 8282/8283 address latch. It is
a HIGH pulse active during T1 of any bus cycle. Note
that ALE is never floated.
10-13
2. During the CPU's next T.. or T.J a'pulse1 ClK wide
The following pin function descriptions are .for-.!he
808818288 system In maximum mode (I.e., MN/MX
Vss). Only the pin functions which are unique to max·
Imum mode are described; all other pin functions are as
described above.
=
from the 8086 to the requesting mastei' '~~~t--i
::::: ~1r+I-,_,:_~O_:1-J-+-'
___
_____H __-I_A_"_.A;_"'I-"'_'-I_ffC,1
'lOA'
_
I
~ rJ~
r:..lr--tr---t----\'---t-+-t----+Jr-
_____H __-I_'C_'"_'+--.II
.".O",,"TS "",CO,""'"
SEE NOTES
'TL--t-..-{I~'CLAL
--++'CH__
DT/R
5.61
'c,.,_ ~
'"
/
--++---+---+---f-/"
WRITE - (RD,MRDC,IORC,iNTA,DTIR""Volil
ADwADn
TCLMH--
I-
relAV
-
r=
1\
TCVNX-
r-
TCHDZ---
TCLDVC
JOAT
---+-+X'r-+--+-~X-+--L--OA-'A--f--+-,l ,m
'-+'c-'-.'-+-IJ_/__+ __-+_______-+_,_c,_._,+,~I;OTE 3}
\.r---
TCLMH _
-----1--+---1----hi-rCLMl
~ITCLML
_
......
---+~+-1-~-~\1
'---f-/
I\
I
MC"
,...
DT/R
-=:::=
'C'MCH_
e- -
,~'COA{(Ty
(SEE NOTE 4)
I
FLOAT I'
/
~-t--r~-------I--4--+--+~~==
\ 'CHOT'
1/
\-
~-~~----~-~~
,",00"""",,,
SEE NOTES 5,6
I
iCLMCL
TCLM'-
INTA
-{/\
\
---I_.../f
'---l----I,r,.:.:--'C'--.,
SOFTWARE HALT -
(DEN=VOl;Ro,MRDC,IORC,MWTC,AMWC.IOW~,AIOWC,iNTA.,DTlR= JOH;TI'S FOLLOW T, •
IMH
TCVNX"""
THEN NMI OR INTR-BEGIN NEW T j .)
AD'5,AOO
----+_____ r-----+---------
NorES: 1, ALL SIGNALS SWITCH BETWEEN VOH AND VOL UNLESS OTHERWISE SPECIFIEO,
2, ROY IS SAMPLED NEAR THE END OF T2, T3' Tw TO DETERMINE IF Tw MACHINES STATE!'; ARE TO BE INSERTED
3 FOLLOWING A WRITE CYCLE THE LOCAL BUS IS:FLOATED BY THE 8086 ONLY WHEN THE 8086 ENTE-riS A "HOLD ACKNOWLEDGE" STATE
TWO INTA CYCLES RUN BACK·TO·BACK. "fHE 8086 LOCAL ADDRIDATA BUS IS FLOATING DURING THE SECOND INTA CYCLE
SIGNALSAT82840R8288ARESHOWNFQRREFERENCEONLY
______ _
THE ISSUANCE OF THE 6288 COMMAND AND CONTROL SIGNALS (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INT A AND DEN) LAGS THE ACTIVE HIGH 8286 CEN
ALL TIMING MEASUREMENTS ARE MADE AT j 5V UNLESS OTHERWISE NOTED.
8 STATUS INACTiVE IN STATE JUST PRIOR TO T4
Figure 9. 8086 Bus Timing -
Maximum Mode System (Using 8288)
10·19
~
8086/8086·4
\\~l"
NM'
INTR
TEST
"H:, '\~\)\
eLK
1-:
NOTE:
1. SETUP REQUIREMENTS FOR ASYNCHRONOUS SIGNALS ONLY TO GUARANTEE RECOGNITION AT NEXT CLK
Figure 10. Asynchronous Signal Recognition
Any eLK
cYCle--j
Any eLK
cycle--I
eLK
Figure 11. Bus Lock Signal Timing (Maximum Mode Only)
eLK
(see note 3)
~
MASTER
Previous grant
(see note
Master request is sampled by 8086
1)
NOTES:
1. THE 8086 FLOATS S2,Sl'SO FROM 1.1.1 STATE ON THIS EDGE
2. THE 8086 FLOATS AxDx BUS RD AND LOCK ON THIS EDGE
3. THE OTHER MASTER FLOATS
52, 51, SO FROM 1.1.1 STATE ON THIS EDGE
4. THE OTHER MASTER FLOATS AxDx BUS, BHE, AND
LOCK ON THIS EDGE
Figure 12. Request/Grant Sequence Timing (Maximum Mode Only)
"CLKeyeL'_
eLK
~~
Gr
Master grant is sampled by 8086
~OR2cyeL'S
~
i , ",
~'--"
-1~(LHAV
-'p\-:'"-AV----I"I-,'__
r-_ _ _ _ _-----;,J\-"
___
NOTE:
1. BUS FLOATS ON THIS EDGE (SEE TCHDZ)
Figure 13. Hold/Hold Acknowledge Timing (Minimum Mode Only)
10·20
8086
INSTRUCTION SET SUMMARY
IANSFER
!evI:
3210
78543210
memory tolfrom register
1 Od w Imod reg
rim
e to register/memory
o 1 1 w I miiiJ 0 0 0
rIm
e to register
w reg
I
o0 0 w I
o0 1 w
to accumulator
Ilor to memory
76543210
data
78543210
datalfw~1
data
addr-Iow
addr-hlgh
addr-Iow
addr-hlgh
I
DEC", Decrement:
Register Imemory
tIll 1 1 1 1 w
Register
10 1 0 0 1 "9
NEO:Change sign
tIl 1 1 0 1 1 w mod 0 1 1 rim
76543/10
!mod 001
1
I
eMP " Compare:
Jl110
a reg
rIm
Register/memory and register
00 1 1 1 0 d w mod feg
register to reglsterfmemory
J1100)modOreg
rim
Immediate With register/memory
1 00000 s w mod 1 1 1 rIm
mod
Immediate With accumulator
Push:
AAS=ASCII adjust for subtract
mod 1 1 0 rIm
register
DP:
Imemory
J01111
Imod 000
rIm
~
~
register
Exchangl:
Imemory with register
[
with accumulator
[~
It
00011'11 Imod reg
rim
765'32'0
rIm
memory to segment reglste
Imemory
001 1 1 lOw
rim
data
100 1 1 1 1 1 1 1
DAS=DeClmal adjust lor subtract
00 1 0 1 1 1 1
MUl=Muitiply (unsigned)
1 1 1 101 1 w mod 100 rim
IMUl"lnleger multiply (signed)
1 1 1 101 1 w mod 101 <1m
AAM=ASCII adjust for multiply
1 1 0 1 0 1 00
OIV=Dlvide (unsigned)
1 1 1 101 1 w mod 1 10 rim
IOIV"dnteger divide (signed)
1 1 1 101 1 w mod 1 1 1 <1m
AAO=ASCIl adjust lor divide
110 1010 1
CBW=Convert byte 10 word
10011000
CWO "'Convert word 10 double word
1 00 1 1 00 1
00001010
00001010
I
from:
If'
i
765<32'0
[
~
10010_1
[ JID:E]
port
LOGIC
)utputto:
".
l
[J[!,'
port
ranslate byte to AL
ad EA to register
ad pointer to OS
ad pointer to ES
oad AH with flags
.tore AH into flags
Push Ilags
'op flags
TIJim
port
101 1 1 w
G~
[2 0011011mod
[2 0001011.mod
D
reg
=r7mJ
reg
rIm
000100 "!TI od reg
rIm
I
I
1 1 1 1 0 11 w modO 1 0 <1m
SHl/SAl",Shiftloglcal/arithmelic left
11.0100vw mod 100 rim
SHR=Shitt logical fight
110100vw mod 101 rim
SAR"Shilt anthmetic right
110100vw mod 1 1 1 rim
RDl=Rotate left
1 101 a a
ROR=Rotate right
11010avw modOO! rim
RCl~Rotate
G~(
[j~
through carry flag left
RCR=Rotate through carry nght
[i~
IJ~
V
w modaOO rim
110100vw mod 01 a rim
110100vw modO 1 1 rim
AND, And:
Reg {memory and register to either
o 0 1 000 d w mod reg
Immediate to register/memory
1 0 0 0 0 0 0 w mod 10 0 rfm
immediate to accumulator
0010010w
rim
data
data
data iI w-l
data If w-l
TEST" Aniliunction to filial. nD raul rt:,-:--:-:--:-c-:--r-:---,-Reglsterlmemory and register
METIC
Add:
emory with register to either
[I
COOOdw mod
ate to register/memory
0:
OOOOsw modOaO rim
ate to accumulator
NOT=invert
[I ooo1owl
reo
Immediate data and registerfmemory
Immediate data ard accumulator
rim
data
data
F.;;=;';;=;'~=c'F===::::===i=7.:7.':::=;=t----~
data If s.w=OI
OR, Or:
data It w=1
Reg./memory and register to either
Add wllh CI"y:
Immediate to register/memory
emory with register to eitner
[I
ate to.register/memory
0:
iate to accumulator
[£:
0100dw mod reo
rim
OOOOsw modO 1 0 rim
01010 w
data
Immediate to accumulator
data
data If
data if s:w",OI
XOR '" Exclusive or:
w~ 1
Incrlment:
Reg./memory and register to either
Immediate to register/memory
Ir/memory
Immediate to accumulator
=:--,_=:7.='
FO~O~'~'~O~O~d,,;w~m;.;o~d,.:r~eo~r~/m~_ _
1 000 0 0 0 w mod 11 0 rIm
data
a 0 1 1 0 lOw
SCII adjust for add
Beirnal adjust for add
SUbtroot:
~emory
and register to either
[11010dW
mod reO
rim
liate from register/memory
[IIOOOOSW modi 0 1 rim
liate from accumulator
1:£:)10110w
SUbtract wHh "'""'
~emory
and register to either
Ilate from registerfmemory
llate from accumulator
~'O ; 1 Od
data
rim
1 Ij 0 0 0 0 sw modill 1 rim
data
data if s:w=OI
w mod reg
[I001110w
data
da..
data if '11=1
STRING MANIPULATION
REP=Repeat
data if w=1
data if s:w=OI
1111100" 1
MOVS=Move byte/word
1010010w
CMPS=Compare byte/word
101001 1 w
SCAS=Scan byte/word
10101 1 1 'II
lODS=load byte/wd to AUAX
10101 lOW
STDS=Stor byte/wd from AUA
11010101wl
,monics ©Intel, 1978
10-21
data
data if '11,,1
data if w=1
CONTROL TRANSFER
CAll, Call,
76543210
76543210
Oirect intersegment
11 1 1 0 1 0 0 0 I disp-Iow
11 1 1 1 1 1 1 1 Imod 0 1 0 rIm
11 0 0 1 1 0 1 0 I offset-low
Indirect intersegmenl
11
Direct within segment
Indirect
wllnm segment
1
76 5432 10
76543210
seg-Iow
JHB/JAE",Jump on not below/above
oraqual
JHBE/JA~Jump on not below or
equal/above
JHP/JPO."Jump on not par/par odd
disp-hlgh
offset-high
seg-hlgh
JHO~Jump
I
1 1 1 1 1 1 1 mod 0 1 1 rim
LOOP=Loop CX times
JMP " Unconditional Jump:
Direct Intersegment
I disp-Iow
[1 1 1 0 1 0 1 1 I
dlsp
[iii 1 l I t 1 Imod 1 0 0 rIm
\1 1 1a10 10 I
offset-low
Indirect mtersegment
11
11
Direct within segment
Direct within segment-short
Indirect within segment
on not overflow
JNS"'Jump on not Sign
1 101 001
I
I
seg-Iow
dlsp-hrgh
I
offset-high
seg-high
t i l l 1 1 1 mod 101 rIm
LOOPZllOOPE~Loop while zero/equal
LOOPNZlLOOPNE=loop while not
zero/equal
JCXZ~Jump on ex zero
INT
=
Within segment
Within seg. adding immed to SP
Inlersegment
Intersegment. adding Immediate to SP
IF'~'~O~O~O~O~',;,,,{-I--c----,---,--,--,-~
Type 3
IRET=lnterrupt return
Fll:""~O~O;";'O~'';"0{-I-~~--r---'--'--'--'
data-high
data-low
I
(
J
dIS,
dIS,
diS,
dIS,
I
I
I
1
I
1 00 110 1
1,10011001
1"00" 10 1
1"00""1
type
PROCESSOR CONTROL
1:.;0~1:",1:",1;,,1~1;,1;;.0oFl~~~~9
dlsp
dlsp
1:.;0~1:",1:",1~0~0~1;;.0oFl~~~~9
ClD=Clear direction
JBE/JNA~~¥~go~~ below
dlsp
1:.;0~1:",1;,,1~0~1;,,;;.0oFl~~~~9
STD=Set direction
p;1
CLl=Clear Interrupt
dlsp
I:';O:"":"":"";'~";;'0~O ~~~~9
dlsp
oFl
dlsp
O:",':",'~'~'~O~';,0 ==~==i
disp
:.;Lo:",1:",1;,,1;,,0~0;,;,O;;.0 ~~~~9
dlsp
JS=Jump on sign
:.;1O:",':",';,,'~'0;;;;,0;;.0 ~~~~9
disp
~:~~~:~:j~~~ ~~ ~~; ~e~~~~~~~:rero :.;O:",1:",1;,,1::0~1~O,;,,,F~"';;;;h=i
on overflow
or equal
JNlE/JG;~~~~ron not less or equal/
dis,
data-high
data-lOW
Fll~1~O~0~0~0~1~O+-1_--"="'---'-_=="'-~
JlE/JNG;~~~~ron less or equal/not
JB/JNAE~~Ue~~a~n below/not above
JP/JPE=Jump on panty/parity even
dIS,
111001011\
10 1 1 1 0 1 00
JO~Jump
l'
\
I
I
di50
I
J
I
I
l'
Type speCified
JE/JZ",Jump on equal/zero
Jl/JNGE~~Ue~ea~n less/not greater
or equal!
dlSP
dis,
Interrupt
INTO=lnterrupt on overflow
RET " Return from CALL:
765 43210
10 1 1 1 00 1 1 I
1011101111
10 1 1 1 1 0 1 1 (
1011100011
10111 1001
l' 1 1 0 0 0 1 0
1 1 00 0 0 1
111 1 00000
l' 1 1 0 0 0 1 1 I
*,1
111111000
ClC=Clear carry
CMC~Complement
STC",Sel carry
oF
l
STI=Set Interrupt
l
oF
HLT=Hall
0 1 11 1 10 1
101 1 1 1 1 1 1 I
carry
1 " " 0101
111111001
111111 00
1 " " " 01
11 1110 1 0
11111011
!
1""0100
110011011
WAIT=Wait
disp
ESC=Escape (to external device)
dlsp
lOCK~Bus
I
I
1" 01 1 x x x!
1 " " 0000
mod x
,
x rIm
I
I
lock prefiX
Foot.ot.. ,
AL ' B-bit accumulator
AX ' 16-bit accumulator
CX ' Count regISter
OS ' Data segment
ES = Extra segment
Above/below refers to unsigned value.
Greater =: more positive;
Less less positive (more negative) signed values
=:
if d =: 1 then "to" reg; if d=:O then "from" reg
if w
if
if
if
if
=:
if s:w = 01 then 16 bits of immediate data form the operand.
if s:w = 11 then an immediate data byte is sign extended to
form the t6-bit operand.
if v = 0 then "count" = 1; if v = 1 then "count" in (CL)
x::: don't care
z is used for string primitives for comparison with ZIF FLAG.
SEGMENT OVERRIDE PREFIX
10 0 1
1 then word instruction; if w == 0 then byte instruction
mod = 11 then
mod, 00 then
mod = 01 then
mod = 10 then
if rim' 000 then
if rim' 001 then
if rim = 010 then
if rim = 011 then
if rim = 100 then
if rim = 101 then
if rim = 110 then
if rim' 111 then
OISP follows 2nd
rim is treated as a REG field
olSP , 0', disp-Iow and disp-high are absent
olSP = disp-Iow sign-extended to 16-bits, disp-high is absent
DlSP = disp-high: 'disp-Iow
EA = (aX) + (SI) + olSP
EA = (aX) + (01) + DlSP
EA = (ap) + (SI) + olSP
EA ' (ap) + (01) + olSP
EA = (SI) + DlSP
EA = (01) + DlSP
EA = (BP) + DlSP'
EA = (BX) + OISP
byte of instruction (before data jf required)
'except if mod, 00 and rim' 110 then EA = disp-high: disp-Iow.
reg
t 1 01
REG is aSSigned according to the following table:
IS-Bit Iw ' 1)
000 AX
001 ex
010 OX
011 BX
100 SP
101 BP
110 SI
111 01
8-BIt (w = 0)
000 AL
001 CL
010 OL
011 BL
100 AH
101 CH
110 oH
111 BH
Segment
00 ES
01 es
10 SS
11 OS
Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to
represent the file:
FLAGS ' X:X:X:X:(OF):(oF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
Mnemonics©lntel,1978
10-22
8282/8283
OCTAL LATCH
•
Fully Parallel 8·Bit Data Register and
Buffer
•
Transparent during Active Strobe
•
Supports 8080, 8085, 8048, and 8086
Systems
• High Output Drive Capability for
Driving System Data Bus
•
3·State Outputs
•
20·Pln Package with 0.3" Center
•
No Output Low NO,lse when Entering
or Leaving High Impedance State
The 8282 and 8283 are 8-bit bipolar latches with 3-state output buffers. They can be used to implement latches, buffers,
or multiplexers. The 8283 inverts the input data at its outputs while the 8282 does not. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with these devices.
PIN CONFIGURATIONS
LOGIC DIAGRAMS
I
I
I
I
I
I
L ______ _
I
L
______ _
vee
000
001
01 4
003
004
01 5
DOs
DOs
ii07
L______ _
STB
PIN NAMES
'010-017
DOg-OCr
OE
STB
DATA IN
DATA OUT
OUTPUT ENABLE
STROBE
10-23
I
I
I
I
I
8282/8283
00 0-00 7
PIN DEFINITIONS
Pin
STB
(8282)
Description
00 0-007
(8283)
STROBE (Input). STB is an input control
pulse used to strobe data at the data input
pins (A o-e.7) into the data latches. This
signal is active HIGH to admit input data.
The data is latched at the HIGH to LOW
transition of STB.
"
OPERATIONAL DESCRIPTION
The 8282 and 8283 octal latches are 8·bit latches with
3·state output buffers. Data having satisfied the setup
time requirements is latched into the data latches by
strobing the STB line HIGH to LOW. Holding the STB
line in its active HIGH state r:nakes the latches appear
transparent. Data is presented to the data output pins by
activating the OE input line. When OE is inactive HIGH
the output buffers are in their high impedance state.
Enabling or disabling the output buffers will not cause
negative·going transients to appear on the data output
bus.
OUTPUT ENABLE (Input). OE is an input
control signal which when active LOW
enables the contents of the data latches
onto the data output pin (Bo-B7)' OE being
inactive HIGH forces the output buffers to
their high impedance state.
01 0- 01 7
PI~~::t
DATA OUTPUT
true, the data in the;"da~a' Ie
sented as Inverted (8283ro,f no;n~
(8282) data onto the data outPt..t.P.~~~
DATA INPUT PINS (Input). Data presented
at these pins satisfying setup time reo
quirements when STB is strobed and
latched into the data input latches.
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................. O·C to 70'C
Storage Temperature ............. - 65'C to + 150'C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + 5.5V
Power Dissipation .......................... 1 Watt
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device, This Is a stress
rating only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating con'·
dltions for extended periods may affect device reliability.
D.C. CHARACTERISTICS FOR 828218283
Conditions: Vee = 5V± 5%, TA= O'C to 70'C
Symbol
Max
Units
Ve
Input Clamp Voltage
Parameter
-1
V
Icc
Power Supply Current
160
mA
IF
Forward Input Current
-0.2
mA
VF = 0.45V
IR
Reverse Input Current
50
jAA.
V R = 5.25V
VOL
Output Low Voltage
0.50
V
10l = 32 mA
VOH
Output High Voltage
V
10H = -5 mA
± 50
jAA.
VOFF = 0.45 to 5.25V
0.8
V
Vcc =5.0V
See Note 1
V
Vcc =5.0V
See Note
10FF
Output Off Current
Vil
Input Low Voltage
VIH
Input High Voltage
C IN
Min
2.4
2.0
Input Capacitance
=
Nol••: 1. Output loading 10l 32 mAo 10H
=- 5 mAo
12
Cl =300 pF
10-24
pF
rest Conditions
Ic = -5 mA
1
F= 1 MHz
VSIAS =2.5V, Vcc=5V
TA =25'C
828218283
A.C. CHARACTERISTICS FOR 828218283
Conditions: vee= 5V± 5%, TA=O·C to 70·C
Loading: Outputs -
10L = 32 rnA, 10H = - 5 rnA, C L = 300 pF
Max
Units
Input to Output Delay
-Inverting
-Non-Inverting
25
35
ns
ns
STB to Output Delay
-Inverting
-Non-Inverting
45
55
ns
ns
Output Disable Time
25
ns
50
ns
Symbol
TIVOV
TSHOV
TEHOZ
Min
Parameter
Test Conditions
(See Note 1)
TELOV
Output Enable Time
10
TIVSL
Input to STB Setup Time
0
ns
TSLIX
Input to STB Hold Time
25
ns
TSHSL
STB High Time
15
ns
NOTE: 1. See waveforms and test load circuit on following page.
828218283 TIMING
INPUTS
\V
\V
11\
11\
! - - - T I V S L _ .TSLIX·
STB
--.-I
\
\
TSHSL
/
1
_
!-TIVOV.
OUTPUTS
\/
.,<\
\
- mM_C=
\
TEHOZ
>-_~o.!.'..:"~~_
SEE NOTE 1
I--TSHOV-
NOTE: 1.8283 ONLY -
OUTPUT MAY BE MOMENTARILY INVALID FOLLOWING THE HIGH GOING STB TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED
10-25
'-
8282/8283
OUTPUT DELAY VS. CAPACITANCE
50
50
8283
8282
40
frl
,.'"z
:5w
c
10
600
pF LOAD
800
1000
pF LOAD
OUTPUT TEST LOAD CIRCUITS
1.5V
1.SV
33Q
2.14V
180Q
OUT
52.7Q
OUT
1300
PF
3-STATE TO VOL
OUT
1300
pF
1300
3·STATE TO YOH
SWITCHING
10·26
pF
8284
CLOCK GENERATOR AND DRIVER
FOR 8086 CPU
• Generates the System Clock for the
8086
• Generates System Reset Output from
Schmitt Trigger Input
• Uses a Crystal or a TTL Signal for Fre·
quency Source
• Provides Local Ready and MULTIBUS™
Ready Synchronization
• Single
+ 5V Power Supply
• Capable of Clock Synchronization with
other 8284's
• 18·Pin Package
The 8284 is a bipolar clock generator/driver designed to provide clock signals for the 8086 CPU and peripherals. It also
contains READY logic for operation with two MULTIBUSTM systems and provides the 8086's required READY synchronization and timing. Reset logic with hysteresis and synchronization is also provided.
8284 PIN CONFIGURATION
8284 BLOCK DIAGRAM
RES--;:===::;----,.Cl>----l
X1
CYSNC
VCC
XTAL
OSCIL·
LATOR
X2
PCLK
Xl
AEN1
X2
RDYl
TNK
EFI
RDY2
FIC
AEN2
OSC
CLK
RES
GND
RESET
RESET
h - - - - - t ; > o - - t - - - o sC
TANK
READY
a
CK
t - - - - CLK
FiC-.-[>O-----L.I~
EFI~======Cy
PCLK
CSyNC-------------'--t--
RDY1
AEN1
=====l>;;:::::::[J
READY
AEN2====j2~==LJ
RDY2
8284 PIN NAMES
~~
I
CONNECTIONS FOR CRYSTAL
TANK
FIC
EFI
CSYNC
~~~~
i
USED WITH OVERTONE CRYSTAL
CLOCK SOURCE SELECT
EXTERNAL CLOCK INPUT
CLOCK SYNCHRONIZATION INPUT
READY SIGNAL FROM TWO MULTIBUS" SYSTEMS
ADDRESS ENABLED QUALIFIERS FOR RDY1.2
RESET
OSC
CLK
PCLK
READY
VCC
GND
RESET INPUT
SYNCHRONIZED RESET OUTPUT
OSCILLATOR OUTPUT
MOS CLOCK FOR 8086
TTL CLOCK FOR PERIPHERALS
SYNCHRONIZED READY OUTPUT
+5 VOLTS
0 VOLTS
10-27
8284
".
PIN DEFINITIONS
Pin
Pin
110
Definition
AEN1,
AEN2
I
ADDRESS ENABLE. AEN is an active
lOW signal. AEN serves to qualify its
respective Bus Ready Signal (RDY1 or
RDY2). AEN1 validates RDY1 while AEN2
validates RDY2. Two AEN signal inputs
are useful in system configurations
which permit the processor to access
two Multi-Master System Busses. In non
Multi-Master configurations the AEN
signal inputs are tied true (lOW).
BUS READY (Transfer Complete). ROY is
an active HIGH signal which is an indication from a device located on the system
data bus that data has been received, or
is available. RDY1 is qualified by AEN1
while RDY2 is qualified by AEN2.
RDY1,
RDY2
READY
o
READY. READY is an active HIGH signal
which is the synchronized ROY signal input. Since ROY occurs asynchronously
with respect to the processor's clock
(ClK) it is necessary for them to be synchronized before being presented to the
processor. READY is cleared after the
guaranteed hold time to the processor
has been met.
X1, X2,
TNK
CRYSTAL IN. X1 and X2 are the pins to
which a crystal is attached with TNK
(TANK) serving as the overtone input.
The crystal frequency is 3 times the
desired processor clock frequency.
F/C
FREQUENCY/CRYSTAl SELECT. FIC is
a strapping option. When strapped lOW,
FIC permits the processor's clock to be
generated by the crystal. When FIC is
strapped HIGH, ClK is generated from
the EFI input.
EXTERNAL FREQUENCY IN. When FIC
is strapped HIGH, ClK is generated from
the input frequency appearing on this
pin. The input signal is a square wave 3
times the frequency of the desired ClK
output.
EFI
ClK
PClK
o
o
PROCESSOR CLOCK. ClK is the clock
output used by the processor and all
devices which directly connect to the
processor's local bus (i.e., the bipolar
support chips and other MOS devices).
ClK has an output frequency which is
1/3 of the crystal or EFI input frequency
and a 1/3 duty cycle. An output HIGH of
4.5 volts (V cc = 5V) is provided on this
pin to drive MOS devices.
110
OSC
o
RES
RESET
.;:,:'
"'f
Definition
OSCillATOR OUTPlJT: OSCI$J~.TTl
level output of the internal oscjJiatrir:'oirc"
cuitry. Its frequency is equaito' that6f'
the crystal.
. '
RESET IN. RES is an active lOW signal
which is used to generate RESET. The
8284 provides a Schmit! trigger input so
that an RC connection can be used to
establish the power-up reset of proper
duration.
0
RESET. Reset is an active HIGH signal
which is used to reset the 8086 family
processors. Its timing characteristics
are determined by RES.
CSYNC
CLOCK SYNCHRONIZATION. CSYNC is
an active HIGH signal which allows multiple 8284's to be synchronized to provide clocks that are in phase. When
CSYNC is HIGH the internal counters are
reset. When CSYNC goes lOW the internal counters are allowed to resume
counting. CSYNC needs to be externally
synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to ground.
GND
Ground
Vee
+ 5V supply
FUNCTIONAL DESCRIPTION
GENERAL
The 8284 is a single chip clock generatorldriver for the
8086 CPU. The chip contains a crystal controlled
oscillator, a "divide by three" counter, complete MUlTIBUSTM "Ready" synchronization and reset logic.
OSCILLATOR
The oscillator circuit of the 8284 is designed primarily
for use with an external series resonant, fundamental
mode, crystal from which the basic operating frequency
is derived. However, overtone mode crystals can be
used with a tank circuit as shown in Figure 1.
The crystal frequency should be selected at three times
the required CPU clock. X 1 and X2 are the two crystal
input crystal connections.
PERIPHERAL CLOCK. PClK is a TTL
level peripheral clock signal whose output frequency is 1/2 that of ClK and has
a 50% duty cycle.
The output of the oscillator is buffered and brought out
on OSC so that other system timing signals can be
derived from this stable, crystal-controlled source.
10-28
8284
osc
o
ClK
~
X2
PCLK
3 TO 10 pF
Q
8284
Vcc
EFI
>1
I
r
o-+-..---cliiES
RESET
TANK
(TO OTHER 8284.)
Figure 2. CSYNC Synchronization
,----------- -I
I
I
:
>-'-I>o-+'-I >1
1=
:
I
I
2.k,
I USED WITH OVERTONE
C BP
r r
CT
L ______ .:___-=___
CLOCK OUTPUTS
:
CRYSTALS ONLY
The ClK output is a 33% duty cycle MOS clock driver
designed to drive the 8086 processor directly. PClK is a
TIL level peripheral clock signal whose output frequency is 1/2 that of ClK. PClK has a 50% duty cycle.
~
The tank input to the oscillator allows the use of ovenone mode crys·
tals. The tank circuit shunts the crystal's fundamental and high ovenone
frequencies and allows the third harmonic to oscillate. The external LC
network is connected to the TANK input and is AC coupled to ground.
RESET LOGIC
The reset logic provides a Schmitt trigger input (RES)
and a synchronizing flip-flop to generate the reset timing. The reset Signal is synchronized to the falling edge
of ClK. A simple RC network can be used to provide
power on reset by utilizing this function of the 8284.
Figure 1
CLOCK GENERATOR
READY SYNCHRONIZATION
The clock generator consists of a synchronous divideby-three counter with a special clear input that inhibits
the counting. This clear input (CSYNC) allows the output clock to be synchronized with an external event
(such as another 8284 clock). It is necessary to synchro·
nize the CSYNC input to the EFI clock external to the
8284. This is accomplished with two Schottky flip-flops.
(See Figure 2.) The counter output is a 33% duty cycle
clock at one-third the input frequency.
Two READY inputs (RDY1, RDY2) are provided to
accomomodate two Multi-Master system busses. Each
input has a qualifier (AEN1 and AEN2, respectively). The
AEN signals validate their respective ROY signals. If a
Multi·Master system is not being used the AEN pin
should be tied lOW.
The READY output is an active HIGH signal which is the
synchronized RDY1 or RDY2 input. Since RDY1 and
RDY2 occur asynchronously with respect to the processor's clock (ClK), it is necessary to synchronize them
before presenting them to the processor to insure they
meet the required set·up time. The READY logic does
this job and also guarantees the required hold time
before clearing the READY signal.
The FIG input is a strapping pin that selects either the
crystal oscillator or the EFI input as the clock for the -;- 3
counter. If the EFI input is selected as the ClOCK source,
the oscillator section can be used independently for
another clock source. Output is taken from OSC.
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................. O'C to 70'C
Storage Temperature ............. - 65'C to + 150'C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. -1.0V to + 5.5V
Power Dissipation .......................... 1 Watt
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.
10·29
8284
D.C. CHARACTERISTICS FOR 8284
Conditions: T A = O'C to 70 'C; V CC = 5V ± 10%
Symbol
Parameter
Min
Forward Input Current
IF
IR
Reverse Input Current
Vc
Input Forward Clamp Voltage
Icc
Power Supply Current
V il
Input lOW Voltage
V IH
Input HIGH Voltage
2.0
V IHR
Reset Input HIGH Voltage
2.6
VOL
Output lOW Voltage
V OH
Output HIGH Voltage ClK
Other Outputs
VIHR-VllR
RES Input Hysteresis
Max
Units
Test Conditions
-0.5
mA
V F =0.45V
VR=5.25V
50
,..A
-1.0
V
140
mA
0.8
V
V cc =5.0V
V
Vcc= 5.0V
Ic= -5 mA
V
V cc =5.0V
V
5 mA
4
2.4
V
V
-1 mA
-1 mA
0.25
V
Vcc= 5.0V
0.45
"
A.C. CHARACTERISTICS FOR 8284
Conditions: TA = O'C to 70 'C; Vee = 5V ± 10%
TIMING REQUIREMENTS
Symbol
TEHEL
TElEH
TElEl
Parameter
External Frequency High Time
-
External Frequency low Time
EFI Period
Min
Max
Units
20
ns
20
ns
TEHEl+ TElEH+ 0
XTAl Frequency
12
ns
25
Test Conditions
(Note 1)
MHz
TR1VCl
RDY1, RDY2 Set·Up to ClK
35
ns
TClR1X
RDY1, RDY2 Hold to ClK
0
ns
TA1VR1V
AEN1, AEN2 Set·Up to RDY1, RDY2
15
ns
TClA1X
AEN1, AEN2 Hold to ClK
0
ns
TYHEH
CSYNC Set·Up to EFI
20
ns
TEHYl
CSYNC Hold to EFI
20
ns
TYHYl
CSYNC Width
2·TElEl
ns
TI1HCl
RES Set·Up to ClK
65
ns
(Note 2)
TCLl1H
RES Hold to ClK
20
ns
(Note 2)
TIMING RESPONSES
Symbol
Parameter
Min
TClCl
ClK Cycle Period
TCHCl
TClCH
TCH1CH2
TCl2CL1
ClK Rise and Fall Time
TPHPl
PClK High Time
TClCl- 20
TPlPH
PClK low Time
TClCl-20
TRYlCl
Ready Inactive to ClK (See Note 4)
Max
Units
Test Conditions
125
ns
ClK High Time
(V, TClCl) + 2.0
ns
Fig. 3 & Fig. 4
ClK low Time
(2hTClCL)-15.0
ns
Fig. 3 & Fig. 4
ns
1.0V to 3.5V
10
ns
ns
-8
ns
Fig. 5 & Fig. 6
(2/,TClCl)-15.0
ns
Fig. 5 & Fig. 6
40
ns
~.
TRYHCH
Ready Active to ClK (See Note 3)
TCLIl
ClK to Reset Delay
Notes: 1. o=EFI rise + EFI fall.
2. Set up and hold only necessary to guarantee recognition at next clock.
3. Applies only to T3 and TW states.
4. Applies only to T2 states.
10-30
eLK
0
PCLK
0
ADY,2
1-4---
AEN1,2
I --/----
-·l_-i---;;;:. .
CSYNe
:.:::l-i=t-_ _ _ _
--J~---t--.....,\",----+_----+_-_TeLI1"-I_TI1HeL_
I
\
I
RESET 0
AI.L TIMING MEASUREMENTS ARE MADE AT 1.5 VOLTS, UNLESS OTHERWISE NOTED
A.C. TEST CIRCUITS
Vee
Fie
CLK
t-----jEFI
CLKt-----j
5pF
...r-I
X,
24MHz=
X.
CSYNC
Figure 3. Clock High and Low Time
Figure 4. Clock High and Low Time
10·31
8284
Vee
Vee
Fie
ClK
liENl
AENI
I - - - r - - / EFI
ClK t - - - - - 1
5 pF
.-r::-I
X,
READY
24 MHz c:::J
X,
OSC
RDY2
1 - - - - - / RDY2
AEN2
A£iii2
Fie
CSYNC
CSYNC READYt------1
-=
Figure 5. Ready to Clock
Figure 6. Ready to Clock
lOAD
TEST
POINT
Vee
ALL DIODES 1N3064
OR EQUIVALENT
FROM OUTPUT
UNDER TEST
I
CL
(SEE NOTE 3)
NOTES: 1. CL ~ 100 pF
2. CL~30 pF
3. CL INCLUDES PROBE AND JIG CAPACITANGE
10·32
inter
8286/8287
OCTAL BUS TRANSCEIVER
• Data Bus Buffer Driver for MCS-86™,
MCS·80™, MCS·8S™, and MCS-48™
Families
•
High Output Drive Capability for
Driving System Data Bus
•
Fully Parallel 8-Bit Transceivers
•
3-State Outputs
•
20-Pin Package with 0.3" Center
•
No Output Low Noise when Entering
or Leaving High Impedance State
The 8286 and 8287 are 8-bit bipolar transceivers with 3-state outputs. The 8287 inverts the Input data at its outputs
while the 8286 does not. Thus, a wide variety of applications for buffering in microcomputer systems can be met.
PIN CONFIGURATIONS
LOGIC DIAGRAMS
.2841
r-------l
I
e--+I
I
PIN NAMES
AfJ- A7
IIo-B7
SYSTEM BUS DATA
OE
T
OUTPUT ENABLE
TRANSMIT
LOCAL BUS DATA
10-33
I
I
I
8286/8287
PIN DEFINITIONS
Pin
TRANSMIT (Input). T is an input control
signal used to control the direction of the
transceivers. When HIGH, it configures the
transceiver's Bo-B7 as outputs with Ao-A7
as inputs. T LOW configures Ao-A7 as the
outputs with Bo-B7 serving as the inputs.
T
SYSTEM BUS DATA PINS (Input/Output).
These pins serve to either present data to
or accept data from the system bus de·
pending upon the state of the T pin.. .
Bo-B7
(8286)
Bo-B7
(8287)
Description
OPERATIONAL DESCRIPTION
OUTPUT ENABLE (Input). OE is an input
control signal used to enable the appropri·
ate output driver (as. selected by T) onto its
respective bus. This signal is active LOW.
The 8286 and 8287 transceivers are 8·bit transceivers
with high impedance outputs. With T active HIGH and
OE active LOW, data at the Ao-A7 pins is driven onto the
Bo-B7 pins. With T inactive LOW and OE active LOW,
data at the Bo-B7 pins is driven onto the Ao-A7 pins. No
output low glitching will occur whenever the trans·
ceivers are entering or leaving the high impedance
state.
LOCAL BUS DATA PINS (Input/Output).
These pins serve to either present data to
or accept data from the processor's local
bus depending upon the state of the T pin.
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
·COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.
Temperature Under Bias ................. O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + 5.5V
Power Dissipation .......................... 1 Watt
D.C. CHARACTERISTICS FOR 8286/8287
Conditions: vee = 5V ±5%, TA = O·C to 70·C
Max
Units
Vc
Input Clamp Voltage
-1
V
Icc
Power Supply Current-8287
-8286
130
160
mA
rnA
IF
Forward Input Current
-0.2
rnA
VF =0.45V
IR
Reverse Input Current
50
!J.A
VR=5.25V
VOL
Output Low Voltage -B Outputs
-A Outputs
0.5
0.5
V
V
IOL=32 rnA
IOL=10mA
VOH
Outpu1 High Voltage -B Outputs
-A Outputs
V
V
IOH=-5 rnA
10H= -1 rnA
10FF
10FF
Output Off Current
Output Off Current
VIL
Input Low Voltage
VIH
Input High Voltage
C IN
Input Capacitance
Symbol
---
Nole: 1. B Outputs
Parameter
Min
2.4
2.4
VOFF =0.45V
VOFF= 5.25V
IF
IR
-A Side
-B Side
0.8
0.9
2.0
12
Test Conditions
le=-5 rnA
V
V
Vee = 5.0V, See Note 1
Vee= 5.0V, See Note 1
V
Vee = 5.0V, See Note 1
pF
F= 1 MHz
VBIAS =2.5V, Vee=5V
TA=2S·C
- 10L = 32 mAo 10H = -5 mAo eL = 300 pF A Outputs - 10L = 10 mAo 10H = -1 rnA, eL = 100 pF
10·34
828618287
A.C. CHARACTERISTICS FOR 828618287
"
Conditions: Vee = 5V ± 5%, T A = O·C to 70·C
Loading: B Outputs - 10L = 32 rnA, 10H = - 5 rnA, C L = 300 pF
A Outputs - 10L = 10 rnA, 10H = -1 rnA, C L = 100 pF
Symbol
Parameter
TIVOV
Min
Input to Output Delay
Inverting
Non-Inverting
TEHTV
Transmit/Receive Hold Time
TTVEl
Transmit/Receive Setup
TEHOZ
Output Disable Time
TElOV
Output Enable Time
.'.'
Max
Units
Test Conditions
25
35
ns
ns
(See Note 1)
TEHOZ
ns
30
ns
10
25
ns
50
ns
Not.: 1. See waveforms and test load circuit on following page.
828618287 TIMING
INPUTS
______
\/
-J/\~
___________________________________________
-
TEHOZ:--
\V
OUTPUTS
TELOV-
VOH-O.5V
~- - - -
__________-J/~~______________~~I
C
--
~ -~1'___1--_1TTV_E_L_____
T
NOTE: 1. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED.
10-35
OUTPUT DELAY VS. CAPACITANCE
50
50
8287
10
800
200
pF LOAD
pF LOAD
TEST LOAD CIRCUITS
1.5V
OUT
~-
2.14V
1.5V
~."
SSQ
OUT
OUT
I~PF
r300 pF
3·STATE TO VOL
3·STATE TO VOL
SWITCHING
B OUTPUT
A OUTPUT
B OUTPUT
1.5V
1.5V
2.28V
180Q
OUT
OUT
r~PF
114Q
900Q
OUT
rl00PF
100PF
a·STATE TO VOH
3·STATE TO VOH
r
SWITCHING
B OUTPUT
A OUTPUT
A OUTPUT
10-36
1000
inter
8288
BUS CONTROLLER FOR THE 8086 CPU
•
Bipolar Drive Capability
•
3·State Command Output Drivers
•
Provides Advanced Commands
•
Configurable for Use with an 1/0 Bus
•
Provides Wide Flexibility in System
Configurations
•
Facilitates Interface to One or Two
Multi·Master Busses
The Intel@ 8288 Bus Controller is a 20-pin bipolar component for use with medium-to-Iarge 8086 processing systems.
The bus controller provides command and control timing generation as well as bipolar bus drive capability while
optimizing system performance.
A strapping option on the bus controller configures it for use with a multi-master system bus and separate I/O bus.
PIN CONFIGURATION
lOB
VCC
CLK
So
52
S1
BLOCK DIAGRAM
80S6
STATUS
I so--
I
{
5
~---
STATUS
DECODER
52~--
DT/R
---*,"
COM·
MAND
SIGNAL
GENER·
AlDR
MRDC
MWTC
AMWC
lORC
lowe
l
MULTIBUSTM
MCE/PDEN
ALE
DEN
AEN
CEN
MRDC
INTA
AMWC
10RC
MWTC
J SIGNALS
COMMAND
AIOWC
10WC
GND
AIOWC
INTA
FUNCTIONAL PIN-OUT
CONTROL
INPUT
{
oriA"
CLK~
CONTROL
AEN - CEN--
CONTROL
lOGIC
SIGNAL
GENER·
ATOR
106--
GND
'
) ADDRESS LATCH, DATA
DEN
TRANSCEIVER, AND
MCE/PDEN INTERRUPT CONTROL
SIGNALS
ALE
It
PROCESSOR
STATUS
+5V
{
~
VCC
So
51
52
AIOWC
AMWC
10WC
COMMAND
BUS
MWTC
GNO
MRDC
CONTROL
INPUT
(
~
AEN
CLK
lOB
CEN
8288
10RC
INTA
DTIR
ALE
MCE/PDEN
DEN
10-37
:J
-.
~
CONTROL
OUTPUT
8288
PIN DEFINITIONS
Name
1/0
Name
Function
Vee
+5V supply.
GND
Ground.
So, S1, S2
Status Input Pins: These pins are the
status input pins from the 8086 proc·
essor. The 8288 decodes these in·
puts to generate command and control signals at the appropriate time.
When these pins are not in use (passive) they are all HIGH. (See chart
under Command and Control Logic.)
Clock: This is a clock signal from the
CLK
1/0
Advanced I/O Write Commanct:The
AIOWC issues an I/O Write Com~\
mand earlier in the machine cycle to.
give I/O devices an early indication
of a write instruction. Its timing is
the same as a read command signal.
AIOWC is active LOW.
I/O Write Command: This command
line instructs an I/O device to read
the data on the data bus. This signal
is active LOW.
iORC
0
I/O Read Command: This command
line instructs an I/O device to drive
its data onto the data bus. This
signal is active LOW.
AMWC
a
Advanced Memory Write Command:
The AMWC issues a memory write
command earlier in the machine cycle to give memory devices an early
indication of a write instruction. Its
timing is the same as a read command signal. AMiiiiC is active LOW.
MW'fC
a
Memory Write Command: This command line instructs the memory to
record the data present on the data
bus. This signal is active LOW.
MRDC
a
Memory Read Command: This command line instructs the memory to
drive its data onto the data bus. This
signal is active LOW.
INTA
a
Interrupt Acknowledge: This command line tells an interrupting device
that its interrupt has been acknowledged and that it should drive vectoring information onto the data bus.
This signal is active LOW.
MCE/PDEN
0
This is a dual function pin.
MCE (lOB is tied LOW): Master Cascade Enable occurs during an interrupt sequence and serves to read a
Cascade Address from a master PIC
(Priority Interrupt Controller) onto
the data bus. The MCE signal is active HIGH.
PDEN (lOB is tied HIGH): Peripheral
Data Enable enables the data bus
transceiver for the I/O bus during 110
instructions. It performs the same
function for the 1/0 bus that DEN performs for the system bus. P5Eiii is
active LOW.
8284 clock generator and serves to
establish when command and control signals are generated.
Address Latch Enable: This signal
serves to strobe an address into the
address latches. This signal is active
HIGH and latching occurs on the failing (HIGH to LOW) transition. ALE is
intended for use with transparent 0
type latches.
ALE
a
DEN
a
Data Enable: This signal serves to
enable data transceivers onto either
the local or system data bus. This
signal is active HIGH.
DTiR
a
Data Transmit/Receive: This signal
establishes the direction of data
flow through the transceivers. A
HIGH on this line indicates Transmit
(write to I/O or memory) and a LOW
indicates Receive (Read).
Address Enable: AEN enables command outputs of the 8288 Bus Controller at least 85 ns after it becomes
active (LOW). AEN going inactive immediately 3-states the command output drivers. AEN does not affect the
110 command lines if the 8288 is in
the I/O Bus mode (lOB tied HIGH).
CEN
i
lOB
Function
Command Enable: When this signal
is LaWall 8288 command outputs
and the DEN and PDEN control outputs are forced to their inactive
state. When this signal is HIGH,
these same outputs are enabled.
Input/Output Bus Mode: When the
lOB is strapped HIGH the 8288 functions in the I/O Bus mode. When it is
strapped LOW, the 8288 functions in
the System Bus mode. (See sections
on I/O Bus and System Bus modes).
10-38
.
o~oo
INTA (Interrupt Acknowledge) acts asah ,1/0 r.ead during
an interrupt cycle. Its purpose is to iMerman.interrupting device that its interrupt is beingack;'owhi!l;lg~d
and that it should place vectoring informationonto'~tle·:
data bus.
.
COMMAND AND CONTROL LOGIC
The command logic decodes the three 8086 CPU status
lines (So, 51,
to determine what command is to be
issued.
S2l
This chart shows the meaning of each status "word".
s;
S;
So
8086 State
8288Command
Control Outputs
0
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Interrupt Acknowledge
Read 1/0 Port
Write 1/0 Port
Halt
Code Access
Read Memory
Write Memory
Passive
INTA
10RC
10WC,AIOWC
None
MRDC
MRDC
MWTC,AMWC
None
The control outputs of the 8288 are Data Enable (DEN),
Data Transmit/Receive (DTlR) and Master Cascade
Enable/Peripheral Data Enable (MCE/PDEN). The DEN
signal determines when the external bus should be
enabled onto the local bus and the DTiR' determines the
direction of data transfer. These two signals usually go
to the chip select and direction pins of a transceiver.
The MCE/PDEN pin changes function with the two
modes of the 8288. When the 8288 is in the lOB mode
(lOB HIGH) the PDEN Signal serves as a dedicated data
enable Signal for the 1/0 or Peripheral System bus.
The command is issued in one of two ways dependent
on the mode of the 8288 Bus Controller.
1/0 Bus Mode - The 8288 is in the 1/0 Bus mode if the
lOB pin is strapped HIGH. In the 1/0 Bus mode all 1/0
command lines (IORC, 10WC, AIOWC, INTA) are always
enabled (I.e., not dependent on AEN). When an 1/0 command is initiated by the processor, the 8288 immediately
activates the command lines using PDEN and DT/R to
control the 110 bus transceiver. The 1/0 command lines
should not be used to control the system bus in this
configuration because no arbitration is present. This
mode allows one 8288 Bus Controller to handle two external busses. No waiting is involved when the CPU
wants to gain access to the 1/0 bus. Normal memory access requires a "Bus Ready" signal (AEN LOW) before it
will proceed. It is advantageous to use the lOB mode if
1/0 or peripherals dedicated to one processor exist in a
multi-processor system.
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge cycle if the 8288 is in the System Bus mode (lOB
LOW). During any interrupt sequence there are two interrupt acknowledge cycles that occur back to back. During the first interrupt cycle no data or address transfers
take place. Logic should be provided to mask off MCE
during this cycle. Just before the second cycle begins
the MCE signal gates a master Priority Interrupt Controller's (PIC) cascade address onto the processor's
local bus where ALE (Address Latch Enable) strobes it
into the address latches. On the leading edge of the
second interrupt cycle the addressed slavePIC gates an
interrupt vector onto the system data bus where it is
read by the processor.
System Bus Mode - The 8288 is in the System Bus
mode if the lOB pin is strapped LOW. In this mode no
command is issued until 85 ns after the AEN Line is activated (LOW). This mode assumes bus arbitration logic
will inform the bus controller (on the AEN line) when the
bus is free for use. Both memory and 1/0 commands
wait for bus arbitration. This mode is used when only
one bus exists. Here, both 1/0 and memory are shared by
more than one processor.
If the system contains only one PIC, the MCE signal is
not used. In this case the second Interrupt Acknowledge
signal gates the interrupt vector onto the processor bus.
Address Latch Enable and Halt
Command Outputs
The advanced write commands are made available to initiate write procedures early in the machine cycle. This
signal can be used to prevent the 8086 CPU from entering an unnecessary wait state.
Command Enable
The command outputs are:
MRDC
MWTC
10RC
10WC
AMWC
AIOWC
INTA
-
Address Latch Enable (ALE) occurs during each
machine cycle and serves to strobe data into the address latches. ALE also serves to strobe the status (So,
51, 5;) into a latch within the 8288. For this reason an
ALE occurs when entering a halt state.
Memory Read Command
Memory Write Command
1/0 Read Command
1/0 Write Command
Advanced Memory Write Command
Advanced 1/0 Write Command
Interrupt Acknowledge
The Command Enable (CEN) input acts as a command
qualifier for the 8288. If the CEN pin is high the 8288
functions normally. If the CEN pin is pulled LOW, all
command lines are held in their inactive state (not
3-state). This feature can be used to implement memory
partitioning and to eliminate address conflicts between
system bus devices and resident bus devices.
10-39
0"'00
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias.
Storage Temperature.
All Output and Supply Voltages.
All Input Voltages.
Power Dissipation.
.O°C to 70°C
. . - 65°C to + 150°C
. . - 0.5V to + 7V
. ... - 1.0V to + 5.5V
. ......................... . 1.5 Watt
·COMMENT: Stresses above those listed under "Absolute Mpxirr.rUJ!1
Ratings" may cause permanent damage to the device. This is a sUes's'"
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS FOR THE 8288
Conditions: Vcc= 5V ± 10%, TA = ooe to lOoe
Max
Unit
-1
V
Power Supply Current
230
mA
Forward Input Current
-0.7
mA
'R
Reverse Input Current
50
~A
VOL
Output low Voltage-Command Outputs
0.5
0.5
V
V
IOl~32
V
V
IOH~
Symbol
Min
Parameter
Vc
Input Clamp Voltage
ICC
'F
Control Outputs
VOH
Output High Voltage- Command Outputs
Control Outputs
V,l
Input low Voltage
V,H
Input High Voltage
IOFF
Output Off Current
2.4
2.4
0.8
V
100
~A
2.0
Test Conditions
IC- -5 mA
VF ~ 0.45V
VR~VCC
10l~
IOH~
mA
16 mA
-5 mA
-1 mA
V
VOFF~
0.4 to 5.25V
A.C. CHARACTERISTICS FOR THE 8288
Conditions: Vcc = 5V ± 10%, TA = ooe to lOoe
TIMING REQUIREMENTS
Symbol
TClCl
Parameter
ClK Cycle Period
Max
Min
loading
Unit
125
ns
TClCH
ClK low Time
66
ns
TCHCl
ClK High Time
40
ns
TSVCH
Status Active Setup Time
65
ns
TCHSV
Status Active Hold Time
10
ns
TSHCl
Status Inactive Setup Time
55
ns
TClSH
Status Inactive Hold Time
10
ns
TIMING RESPONSES
Symbol
Parameter
TCVNV
Control Active Delay
Min
Max
Unit
5
45
ns
10
TCVNX
Control Inactive Delay
45
ns
TCllH, TClMCH
ALE MCE Active Delay (from ClK)
15
ns
TSVlH, TSVMCH
ALE MCE Active Delay (from Status)
15
ns
TCHll
ALE Inactive Delay
15
ns
TClMl
Command Active Delay
10
35
ns
TClMH
Command Inactive Delay
10
35
ns
TCHDTl
Direction Control Active Delay
50
ns
TCHDTH
Direction Control Inactive Delay
30
ns
TAElCH
Command Enable Time
40
ns
TAEHCZ
Command Disable Time
40
ns
TAElCV
Enable Delay Time
275
ns
TAEVNV
AEN to DEN
20
ns
TCEVNV
CEN to DEN, PDEN
TCElRH
CEN to Command
85
10-40
20
ns
TClMl
ns
loading
"'OC }
IORC
MWTC
IOWC
INTA
AMWC
AIOWC
IOl~32 mA
IOH~ -2 mA
Cl~300 pF
IOl~16mA
Other
{
IOH~ -1 mA
Cl~80 pF
.":
D"DD
8288 TIMING DIAGRAM
STATE
_T4~ ~Tl
-TCLCL
CLK
I
V\
\
f-
TCHSV-
-
n
/
T2
-TCLCH-h
'\
-
TSVCH
1\
/
- "Y
TCHCL-
1\
r\
ADDR
VALID
ADDRESSJDATA
~
TCLLH_
r
WRITE
DATA VALID
-
I
-
V\
r\
/
G)
HSVL;-TCHLL
! ®¥
ALE
1\
TSHCL
TCLS~
\
\
T4~
T3
j
-
r-TCLMH
V
\
1\
-
/
-
-TClMl
_TCLML
\
V
/
\
-
-TCVNV
/
)
)
\
/
1\
l+-
TCVNX-
\
)
)
V
~
j
'--
TCVNV-
I
DEN (WRITE)
\
I
-
/
\
PiiEiii (WRITE)
I
\
---- _.t::
\
-TCVNX
TCHDTH-
DTIR(READ)
---MCE
J
\
-
If1--- I I®
TCLMCH-
1/
/
1\
I-- TCHOTL
\
TCHDTH~
-TCVNX
r-TSVMC-;;-
NOta
1. AODRES8IOATA BUS IS SHOWN ONLY FOR REFERENCE PURPOSES.
2. lEADING EDGE OF. ALE AND MeE IS DETERMINED BY THE FALLING EDGE Of elK OR STATUS GOING ACTIVE, WHICHEVER OCCURS LAST
3. AlL TIMING MEASUREMENTS ARE MADE AT 1.!5V UNLESS SPECIFIED OTHERWISE.
10·41
-
0'"'00
DEN, PDEN QUALIFICATION TIMING
CEN
TAEVNV~
DEN
8288 ADDRESS ENABLE (AEN) TIMING (a·STATE ENABLE/DISABLE)
\~--TAELCV~
1\5v
TAELCH}__
1.SV
1--~--~----------~,_--iT-A-E-HxC~lz~--~
I
VOH
OUTPUT _ _ _ _ _ _ _ _ _ _...... ,
COMMAND
j\\' ___
O.5V
_
VOH
1-.C~....::f~----
.../11
·TCELRH ...
I
CEN------------------------------T=C~E~LR~H~---'I
\
~~---------------------
NOTE: CEN MUST BE lOW OR VALID PRIOR TO T2 TO PREVENT THE COMMAND FROM BEING GENERATED.
TEST LOAD CIRCUITS
1.5V
133Q
180Q
OUT
152.7Q
OUTi
1300
2.28V
2.14V
1.SV
OUT
OUTi
1300
pF
114Q
pF
1
80PF
3·STATE TO HIGH
COMMAND OUTPUT
TEST LOAD
3·STATE TO LOW
3·STATE COMMAND OUTPUT
TEST LOAD
10-42
CONTROL OUTPUT
TEST LOAD
Microprocessor
Peripherals
11
MICROPROCESSOR PERIPHERALS
INTRODUCTION
Intel peripherals greatly enhance the 8080, the 8085, and many other microcomputers. These peripherals can significantly reduce development time, operating software, package count, board space, and parts costs while improving
performance and increasing throughput in microcomputer systems. This section contains the most up-to-date data
about Intel peripherals now available.
TABLE OF CONTENTS
8041 A/8741 A
8202
8251A
825318253-5
8255A/8255A-5
8271
8273
8275
8278
827918279-5
8291
8292
8294
8295
Universal Peripheral Interface 8-Bit Microcomputer..................................... 11-3
Dynamic RAM Controller ........................................................... 11-14
Programmable Communication Interface ............................................. 11-24
Programmable Interval Timer ........................................................ 11-32
Programmable Peripheral Interface..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-43
Programmable Floppy Disk Controller ................................................ 11-64
Programmable HDLCISDLC Protocol Controller ........................................ 11-93
Programmable CRT Controller ...................................................... 11-118
Programmable Keyboard Interface ................................................... 11-142
Programmable KeyboardlDisplay Interface ............................................ 11-152
GPIB Talker/Listener ............................................................... 11-164
GPIB Controller ................................................................... 11-188
Data Encryption Unit. ............................................................. 11-190
Dot Matrix Printer Controller ........................................................ 11-201
11-2
inter
8041A/8741A
UNIVERSAL PERIPHERAL INTERFACE
8·BIT MICROCOMPUTER
• Fully Compatible with MCS·48™,
MCS·80™, MCS·8S™, and MCS·86™
Microprocessor Families
• 8·Bit CPU plus ROM, RAM, 110, Timer
and Clock in a Single Package
• One 8·Bit Status and Two Data Regis·
ters for Asynchronous Slave·to·Master
Interface
• Expandable 1/0
• DMA, Interrupt, or Polled Operation
Supported
• ROM Power· Down Capability
• 1024 x 8 ROM/EPROM, 64 x 8 RAM,
8·Bit Timer/Counter, 18 Programmable
I/O Pins
• Single SV Supply
The Intel'" 8041A/8741A is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, 1/0
ports, timer/counter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to
function as a peripheral controller in MCS-48™, MCS-80™, MCS-85™, MCS-86™, and other 8-bit systems.
The UPI_41A™ has 1K words of program memory and 64 words of data memory on-chip. To allow full user flexibility the
program memory is available as ROM in the 8041A version or as UV-erasable EPROM in the 8741A version. The 8741A
and the 8041A are fully pin compatible for easy transition from prototype to production level designs.
The device has two 8-bit, TTL compatible 1/0 ports and two test inputs. Individual port lines can function as either inputs or outputs under software control. I/O can be expanded with the 8243 device which is directly compatible and has
16 I/O lines. An 8-bit programmable timer/counter is included in the UPI device for generating timing sequences or
counting external inputs. Additional UPI features include: single 5V supply, low power standby mode (in the 8041 A),
single-step mode for debug (in the 8741A), and dual working register banks.
Because it's a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI interface devices. It is designed to be an efficient controller as well as an arithmetic processor. Applications include keyboard scanning, printer control, display multiplexing and similar functions which involve interfacing peripheral
devices to microprocessor systems.
PIN CONFIGURATION
BLOCK DIAGRAM
["...
V':=======:~
36
P2410eF
P17
P,.
r
~·
P25iiifF
MASTER
SYSTEM
INTERFACE
PORT
,,0 1
DATA
P"
p'"1
MEMORY
r-:c=-:'c.ccc-1 RESIDENT
1---'''-.:::''::c--c-1 R:~~gM
r-:=-:=:-i :;~~~~
(8
Wff-_
",,--
"'--
PERIPHERAL
Ao--
INTERFACE
..--
SYNC
EA-_
SYNC
PROG
FiESE'f--
C"",TAC{"-B
Le, OR
CLOCK
To
TIMING
X2--
8BIT
TlMERI
EVENT COUNTER
11-3
UU41 A/U141 A
PIN DESCRIPTION
UPI INSTRUCTION SET
Description
Mnemonic
ACCUMULATOR
Signal
0 0-0 7
Description
Three-state, bidirectional DATA BUS BUFFER lines
used to interface the UPI-41A to an 8-bit master
system data bus.
P 10- P 17
8-bit, PORT 1 quasi-bidirectional I/O lines.
P20 -P 27
8-bit, PORT 2 quasi-bidirectional I/O lines. The lower
4 bits (P20-P 23) interface directly to the 8243 I/O expander device and contain address and data information during PORT 4-7 access. The upper 4 bits
(P 24 -P27) can be programmed to provide Interrupt
Request and DMA Handshake capability. Software
control can configure P24 as OBF (Output Buffer
Full), P25 as IBF (Input Buffer Full), P26 as ORO
(OM A Request), and P 27 as DACK (OM A
ACKnowledge).
WR
I/O write input which enables the master CPU to
write data and command words to the UPI-41A INPUT DATA .BUS BUFFER.
RD
I/O read input which enables the master CPU to
read data and status words from the OUTPUT DATA
BUS BUFFER or status register.
CS
Chip select input used to select one UPI-41A out of
several connected to a common data bus.
ADD A,Rr
ADD A,@Rr
ADD A,Hdata
AD DC A,Rr
ADDC A,@Rr
ADDC A,Hdata
ANL A,Rr
ANL A,@Rr
ANL A.Hdata
DRL A,Rr
ORL A.@Rr
ORL A,Hdata
XRL A,Rr
XRL A,@Rr
XRL A,Hdata
INC A
DEC A
CLR A
CPL A
DA A
SWAP A
RL A
RLC A
RR A
RRC A
IN A,Pp
OUTL Pp.A
ANL Pp,#data
ORL Pp,#data
IN A.DBB
OUT DBB,A
MOVD A,Pp
MOVD Pp.A
ANLD Pp,A
ORLD Pp.A
Input pins which can be directly tested using conditional branch instructions.
T1 also functions as the event timer input (under
software control). To is used during PROM programming and verification in the 8741A.
Inputs for a crystal, LC or an external timing signal
to determine the internal oscillator frequency.
EA
PROG
Output signal which occurs once per UPI-41A instruction cycle. SYNC can be used as a strobe for
external circuitry; it is also used to synchronize
single step operation.
RESET is also used during PROM programming and
verification.
Single step input used in the 8741A in conjunction
with the SYNC output to step the program through
each instruction.
TIMER/COUNTER
Multifunction pin used as the program pulse input
during PROM programming.
Input used to reset status flip-flops and to set the
program counter to zero.
+ 5V during normal operation. Programming supply
pin during PROM programming. Low power standby
pin in ROM version.
Circuit ground potential.
1
,1
2
2
1
1
2
1
1
2
1
1
1
2
1
1
2
1
1
1
2
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
Input port to A
Output A to port
AND immediate to port
OR immediate to port
Input DBB to A. clear IBF
Output A to DBB, set OBF
Input Expander port to A
Output A to Expander port
AND A to Expander port
OR A to Expander port
MOV A.Rr
MOV A.@Rr
MOV A.Hdata
MOV Rr.A
MOV @Rr.A
MOV Rr.#data
MOV @Rr,#data
MOV A.PSW
MOV PSW.A
XCH A.Rr
XCH A.@Rr
XCHD A,@Rr
MOVP A,@A
MOVP3, A,@A
External access input which allows emulation,
testing and PROM/ROM verification.
+ 5V power supply pin.
1
1
1
2
2
2
2
DATA MOVES
During I/O expander access the PROG pin acts as
an address/data strobe to the 8243.
RESET
1
INPUT /OUTPUT
Address input used by the master processor to indicate whether byte transfer is data or command.
SYNC
Add register to A
Add data memory to A
Add immediate to A
Add immed. to A with carry
Add immed. to A with carry
Add immed. to A with carry
AND register to A
AND data memory to A
AND immediate to A
OR register to A
OR data memory to A
OR immediate to A
Exclusive OR register to A
Exclusive OR data memory to A
Exclusive OR immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap digits of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right th rough carry
MOV A,T
MOV T,A
STRT T
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
11-4
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange digit of A and register
Move to A from current page
Move to A from page 3
Read Timer /Counter
Load Timer ICounter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer ICounter Interrupt
Disable Timer ICounter Interrupt
1
1
1
1
2
2
1
1
1
1
2
2
2
2
1
1
1
1
1
1
t
1
1
2
2
1
1
1
8041A18741A
FEATURES AND ENHANCEMENTS
UPI-41
UPI-41A
,'"
1. Single Data Bus Buffer
DO-~
D7~
,
1. Two Data Bus Buffers, one for input and one for 6(jt-'
put. This allows a much cleaner Master/Slave protocol.
DATA
BUS
BUFFER
(8)
DO-D7
df
INTERNAL
DATA BUS
INPUT
DATA
BUS
BUFFER
(8)
'-----'
OUTPUT
DATA
BUS
BUFFER
(8)
2. 8 Bits of Status
2. 4 Bits of Status
:
UNDE~INED
:
FO
IBF
I I
OBF
FO
I
IBF
OBF
I
ST 4-ST 7 are user defi nable status bits. These bits are
defined by the "MOV STS, A" single byte, single
cycle instruction. Bits 4-7 of the accumulator are
moved to bits 4-7 of the status register. Bits 0-3 of
the status register are not affected.
MOV STS, A
3. RD and WR are level triggered. IBF, OBF, F1 and INT
change internally when RD or WR are low.
Op Code: 90H
3. RD and WR are edge triggered. IBF, OBF, F1 and INT
change internally after the trailing edge of RD or WR.
FLAGS AFFECTED
FLAGS AFFECTED
AD orWR
RDorWR
4. P24 and P25 are port pins only.
4. P24 and P25 are port pins or Buffer Flag pins which
can be used to interrupt a master processor. These
pins default to port pins on Reset.
If the "EN FLAGS" instruction has been executed,
P24 becomes the OBF (Output Buffer Full) pin. A "1"
written to P24 enables the OBF pin (the pin outputs
the OBF Status Bit). A "0" written to P24 disables the
OBF pin (the pin remains low). This pin can be used
to indicate that valid data is available from the UPI41A (in Output Data Bus Buffer).
11-5
8041A18741A
UPI·41A·
UPI·41
If "EN FLAGS" has been executed, P25'beCQm~th'e
IBF (Input Buffer Full) pin. A "1" written .~ P25 .,.
enables the IBF pin (the pin outputs the inverse ot the
IBF Status Bit). A "0" written to P25 disables the IEi'F "
pin (the pin remains low). This pin can be used to indio
cate that the UPI·41 is ready for data.
OBF (INTERRUPT REQUEST)
iBF (INTERRUPT REQUEST)
DATA BUS BUFFER INTERRUPT CAPABILITY
EN FLAGS
5. P26 and P27 are port pins only.
Op Code: OF5H
5. P26 and P27 are port pins or DMA handshake pins for
use with a DMA controller. These pins default to port
pins on Reset.
If the "EN DMA" instruction has been executed, P26
becomes the DRQ (DMA ReQuest) pin. A "1" written
to P26 causes a DMA request (DRQ is activated). DRQ
is deactivated by DACK· RD, DACK ·WR, or execution
of the "EN DMA" instruction.
If "EN DMA" has been executed, P27 becomes the
DACK (DMA ACKnowledge) pin. This pin acts as a
chip select input for the Data Bus Buffer registers
during DMA transfers.
8041A!
8741A
DRQ~
DROn
DACK~
DACK
8257
DMA HANDSHAKE CAPABILITY
EN DMA
11-6
,.
Op Code: OE5H
8041 Al8741 A
'COMMENT: Stresses above those'llsted under '''l\I)solute Maximum
Ratings" may cause permanent damage to till; device. Thill;s a stress
rating only and functional operation of the deVice at''these Otllny other
conditions above those indicated in the operational ,sections 01 tills"
specification is not implied. Exposure to absolute maximum rating ~,
ditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O~C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin With Respect
to Ground .......................... 0.5V to + 7V
Power Dissipation ......................... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
TA =0·Ct070·C. Vss=OV, 8041 A: Vee= +5V ±10%,8741A: Vee= +5V ±5%
Symbol
Min.
Max.
Unit
V 1L
Input Low Voltage (All Except X" X2l
Parameter
-0.5
0.8
V
Test Conditions
VIHI
Input High Voltage (All Except X,. X2• RESEn
2.2
Vee
V 1H2
Input High Voltage (X" X2, RESEn
3.0
Vee
V
VOLI
Output Low Voltage (0 2-0 7• Sync)
0.45
V
IOL=2.0 rnA
VO L2
Output Low Voltage (All Other Outputs Except Prog)
0.45
V
10L= 1.6 rnA
VOL3
Output Low Voltage (Prog)
0.45
V
10L= 1.0 rnA
VOHI
Output High Voltage (0 0-0 7)
2.4
V
10H= -400,..A
VOH2
Output High Voltage (All Other Outputs)
2.4
V
10H= -50,..A
VSS"VIN"Vee
IlL
Input Leakage Current (To. T, • RD, WR. CS. Ao. EA)
±10
,..A
loz
Output Leakage Current (0 0-0 7, High Z State)
±10
,..A
Vss + 0.45"V1N"Vee
lUI
Low Input Load Current (P 'O P17, P2O P27
Low Input Load Current (RESET, SS)
0.5
rnA
V IL =0.8V
0.2
rnA
V 1L =0.8V
IU2
100
Voo Supply Current
1.5
rnA
lee+ 100
Total Supply Current
125
rnA
A.C. CHARACTERISTICS
TA= o·c to 70·C, Vss=OV, 8041A:
Vee= Voo= + 5V ± 10%, 8741A: Vee= Voo= + 5V ± 5%
DBB READ
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
tAR
CS, Ao Setup to RD+
0
ns
tRA
CS, Ao Hold After ROt
0
ns
tRR
RD Pulse Width
250
ns
tey= 2.5,..s
tAD
CS, Ao to Data Out Delay
225
ns
C L=150pF
t RO
RD~
225
ns
CL=150pF
tROF
ROt to Data Float Delay
100
ns
tRV
Recovery Time Between Reads AndlOr Write
300
tey
Cycle Time
2.5
15
,..S
Min.
Max.
Unit
to Data Out Delay
ns
DBB WRITE
Symbol
Parameter
WR~
0
ns
0
ns
WR Pulse Width
250
ns
tow
Data Setup to WRt
150
ns
two
Data Hold Aftert WRt
0
ns
tAW
CS, Ao Setup to
tWA
CS, Ao Hold After WRt
tww
11-7
Test Conditions
OU41AlUf41A
A.C. TEST CONDITIONS
DrDo Outputs
RL; 2.2kto VSS
4.3k to vee
Cl,f; 100 pF
WAVEFORMS
1. READ OPERATION-DATA BUS BUFFER REGISTER.
CS OR AO
~
......-.-tAR
'RV
\---'RR~--1 ~'RA-
x:
(SYSTEM'S
ADDRESS BUS)
\
-----~tRD-
DF
-.
----.AO---
(READ CONTROL)
l
2. WRITE OPERATION-DATA BUS BUFFER REGISTER.
~OR AO
-WR
=4-.Awl"-----I··~'w_W~.~-,..--r
..A~-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
L-
(WRITE CONTROLI
--'DW--': ~ 'wo
DATA BUS
DATA
IINPUTl _ _ _ _
M_Ay_C_H_AN_G_'_ _
\,t
-.J/I
(SYSTEM'S
' -_ _ _ _ _ _ _ _ _ ADDRESSBUSI
-DATA VALlD_V
DATA
It\'-___-:.;;M.;,AY;,...C;,...H;,...AN.;,:G.;,'_ _ _ __
11·8
8041 Al8741 A
A.C. CHARACTERISTICS-PORT 2
TA =
o·c to 70·C, 8041A:
vcc= + 5V ± 10%, 8741A: Vcc= + 5V ± 5%
Symbol
tcp
Parameter
Min.
Port Control Setup Before Falling Edge of PROG
Max.
110
Unit
Test Conditions
ns
tpc
Port Control Hold After Falling Edge of PROG
140
ns
tDP
Output Data Setup Time
220
ns
tpF
Input Data Hold Time
110
ns
t pp
PROG Pulse Width
1400
ns
tps
Input Data Setup Time
700
ns
WAVEFORMS-PORT 2
SYNC
EXPANDER
PCH
PORT
OUTPUT
EXPANDER
PORT
PCH
INPUT
PROG
A.C. CHARACTERISTICS-DMA
T A=0·Ct070·C, Vcc=5V ±10%
Symbol
t ACC
Parameter
Min.
Max.
Unit
0
tCAC
RD or WR to DACK
0
tACD
DACK to Data Valid
225
ns
t CRO
RD or WR to DRO Cleared
200
ns
ns
WAVEFORMS- DMA
- tAce
-..tCAC
-
tAce
,--------.
DATA BUS
- -tcAe
VALID
VALID
---tACDORO
-
-l,t
11·9
Test Conditions
ns
DAC to WR or RD
ICRa-
C L =150pF
8041 A/8741 A
Mnemonic
Description
Bytes
Mnemonic
Cycles
CONTROL
EN DMA
EN I
DIS I
EN FLAGS
SEL RBO
SEL RB1
NOP
CLR Fl
CPL Fl
MOV STS, A
Enable DMA Handshake Lines
Enable IBF Interrupt
Disable IBF Interrupt
Enable Master Interrupts
Select register bank 0
Select register bank 1
No Operation
Increment register
Increment data memory
Decrement register
SUBROUTINE
CALL addr
RET
RETR
2
2
2
Jump to subroutine
Return
Return and restore status
FLAGS
CLR
CPL
CLR
CPL
C
C
FO
FO
.' ,,' ,,;\ B)'Ie$"
Cycles
r
Clear Fl Flag
Complement Fl Flag
A4-A7 to Bits 4-7 of Status
,1, '
Jump unconditional
Jump indirect
2
1
Decrement register and skip
Jump on Carry = 1
Jump on Carry = 0
Jump on A Zero
Jump on A not Zero
Jump on TO= 1
Jump on TO=O
Jump on T1 = 1
Jump on T1 =0
Jump on FO Flag = 1
Jump on F1 Flag = 1
Jump on Timer Flag = 1, Clear Flag
Jump on ISF Flag = 0
Jump on OBF Flag = 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BRANCH
JMP addr
JMPP @A
DJNZ R,addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNISF addr
JOBF addr
JBb addr
REGISTERS
INC Rr
INC@Rr
DEC Rr
Descrlptiol'l\"
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Jump on Accumulator Bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
APPLICATIONS
DATA 1\'---"-"'0-=,11
8085A
TO
PERIPHERAL
DEVICES
ADDR 1-----.--\
8048
CONTROLI-_ _ _-r~1
Figure 1. 808SA-8041A Interlace
RJj
RJj
WR
WR 8041A!
8741A
cs
~
~
Ao
-TO
DBB
-Tl
PORT
CONTROL
2
BUS
DATA BUS
8
Figure 2. 8048-8041A Interlace
KEYBOARD
MATRIX
8243
EXPANDER
8041A!8741A
DATA BUS
CONTROL BUS
Figure 3. 8041A-8243 Keyboad Scanner
CONTROL BUS
Figure 4. 8041A Matrix Printer Interlace
11·10
TO
PERIPHERAL
DEVICES
8041 Al8741 A
~'
,
"
The program/verify sequence'is;,..
PROGRAMMING, VERIFYING, AND
ERASING THE 8741A EPROM
, ",
1. Voo = 5V, clock applied
i~t'~~i' ~if~,or
operating, RESET
OV, TEST o=:' 5V,~A"';';~; "BUS and PROG floating.
"'\ "',:,,'\,{":1,/l'
2. Insert 8741A in programming socket.
,', ,/"
' ;):
6;
=
ProgrammlnglVerlflcatlon
= OV (select program mode).
= 25V (activate program mode).
3. TEST 0
4. EA
In brief, the programming process consists of: activat·
ing the program mode, applying an address, latching the
address, applying data, and applying a programming
pulse. Each word is programmed completely before
moving on to the next and is followed by a verification
step. The following is a list of the pins used for program·
ming and a description of their functions:
""
5. Address applied to BUS and P20·1.
6. RESET
= 5V (latch address).
7. Data applied to BUS.
8. Vo
= 25V (programming power).
9. PROG = OV followed by one 50 ms pulse to 25V.
=
10. Voo
5V.
11. TEST 0 = 5V (verify mode).
12. Read and verify data on BUS.
Pin
XTAL 1
13. TEST 0 = OV.
Function
Clock input (1 to 6 MHz)
14. RESET = OV and repeat from step 5.
15. Programmer should be at conditions of step 1 when
8741A is removed from socket.
RESET
Initialization and address latching
TEST 0
Selection of program or verify mode
EA
Activation of program/verify modes
Programming Options
BUS
Address and data input data output during
verify
The 8741A EPROM can be programmed by either of two
Intei products:
P20·1
Address input
1. PROMPT·48 Microcomputer Design Aid.
Voo
Programming power supply
PROG
Program pulse input
2. Universal PROM Programmer (UPP·101 or UPP·102)
Peripheral of the Intellec Development System with
a UPP·848 Personality Card.
+5V
RESET
o----------------~
- - - - BUS ANO PROG CAN BE DRIVEN ONLY DURING THIS TIME
+5V
TEST 0
-I
r-------
o
+25V
EA
+5V - - - - - - - - '
BUS
<
ADDRESS AO·A7
P20·21
<
ADDRESS Aa-Ag
X
DATA
)
<
DATA OUT
>
+25V
VDD
+5V-------------------------------------J
PROG +5V _______
+OV
~
+25V
____________________________ 1
~
'
Lt.-----
WARNING: An attempt to program a mlssocketed 8741A will result In severe damage to the part. An Indication of a properly socketed part is the
appearance of the SYNC output. The lack of this clock may be used to disable the programmer.
Figure 5. ProgrammlngIVerlflcatlon Sequence
11·11
'
.
OSCILLATOR
8202
PIN DESCRIPTIONS
."
Pin Name
ALo
AL1
AL2
AL3
AL4
ALs
AL6/0P3
#
1/0
Pin Description
6
8
10
12
14
16
18
Low-o"rder Address. These Address
inputs are used to generate the Row
Address for the Multiplexer. If the
ALs/OP3 input is pulled to +12V
through a 5Kfl resistor, the 8202
configures itself for 4K RAMs. If
AL6/0P3 is driven with TTL levels,
the 8202 configures itself for 16K
RAMs.
5
4
High-Order Address. These Address inputs are used to generate
the Column Address for the Multiplexer. If the 8202 is configured for
4K RAMs, AH6 can be used as an
active high Chip select for the memory controlled by 8202. For 16K
RAM operation, AH6 becomes the
most significant column address bit.
AHo
AH1
AH2
AH3
AH4
AHs
AH6
2
1
39
38
OUTo
OUT1
OUT2
OUT3
OUT4
OUTs
OUT6
7
9
11
13
15
17
19
o
o
WE
28
o
Write Enable. This output is designed to drive the Write Enable inputs of the Dynamic RAM array.
CAS
27
o
Column Address Strobe. This output is used to latch the Column
Address into the Dynamic RAM
array.
3
21
22
23
26
24
25
Output of the Multiplexer. These
outputs are desig ned to drive the adO dresses of the Dynamic RAM array.
o For 4K RAM operation, OUT6 is deo signed to drive the 2104A CS input.
o (Note that the OUTO-6 pins do not
o require inverters or drivers for
proper operation.
0
0
0
0
Pin Name
#
RD/S1
32
Read/S1 input. This input is use(l to,
request a read cycle. In normal
operation, a low on this input informs the arbiter that a read cycle is
requested. In the Advanced Read
Mode, this input is designed to
accept the S1 status Signal from the
8085A (fully decoded for a read), The
trailing edge of ALE informs the
arbiter that a read cycle is requested by latching S1.
31
Write Input. This input is used to request a write cycle. A low on this input informs the arbiter that a write
cycle is desired.
33
Protected Chip Select. A low on this
input enables the WR and RD/S1 inputs. PCS is protected against terminating a cycle in progress.
341
Refresh Requestl Address Latch Enable. During normal operation, a
high on this input indicates to the
arbiter that a refresh cycle is being
requested. In the Advanced Read
Mode, this input is used to latch the
state of the 8085 S1 signal into the
RD/S1 input. If S1 is high at this
time, a Read Cycle is requested. In
this mode, transparent refresh is not
possible.
29
0 Transfer acknowledge. This output
is a strobe indicating valid data
during a read cycle or data written
during a write cycle. XACK can be
used to latch valid data from the
RAM array.
30
0 System Acknowledge. This output
indicates the beginning of a memory
access cycle. It can be used as an
advanced transfer acknowledge to
eliminate wait states. (Note: If a
memory access request is made
during a refresh cycle, SACK is delayed until XACK in the memory
access cycle).
XO/OP2
X1/CLK
36
37
Crystal Inputs. These inputs are designed for a quartz crystal to control
the frequency of the oscillator. If
XO/OP2 is pulled to +12V through a
1Kfl resistor, X1/CLK becomes a
TTL input for an external clock.
TNK
35
Tank. This pin is used for a tank
circuit connection.
Vee
40
+ 5V
Vss
20
Ground.
REFRQI
ALE
Row Address Strobe. These outputs
are used to latch the Row Address
into the bank of dynamic RAMs,
selected by the 8202 Bank Address
pins (80, B1/0P1)
Bank Address. These inputs are
used to select one of four banks of
dynamic RAM via the RASo-3 outputs. If the B1/0P1 input is pulled to
+12V through a 5K!1 resistor, the
8202 configures itself to the Advanced Read mode. This mode
changes the function of the 8202
RD/S1 and REFRQ/ALE inputs and
disables the RASo and RAS1 outputs.
11-15
Pin Description,./,
1/0
± 10%
8202
BASIC FUNCTIONAL DESCRIPTION
The 8202 consists of six basic blocks; the oscillator, the
arbiter, the refresh timer, the refresh counter, the
multiplexer, and the timing and control block.
Oscillator
The oscillator provides the .basic timing for all 8202
operations. The oscillator circuit is designed primarily
for use with an external series resonant fundamental
mode crystal. Overtone crystals may be used with the
tank circuit shown in Figure 1. A small capacitor (3-5) pF
should be placed in series with any crystal to block D.C.
stress and assure oscillation at the proper frequency.
WE
XO/OP2
+12v~~ro,l:I~ra
If the B,/0P , input is pulled to .
5KQ
resistor (Advanced Read mode), ROf5, bet~!\i~ .. an
input for the S, status signal of the 8085A(fully dE!ft.,~,d
for read). REFRQ/ALE becomes an inpuf fw \ t~~' At.,lfi7
signal of the 8085 (used to latch S" If 5, is "high'.:af the""
falling edge of ALE, a read cycle will be reques:ted:
Transparent refresh is not possible in this mode.
"
Refresh Timer
The refresh timer is a simple timer that indicates to the
arbiter that it is time for a refresh cycle. The refresh timer
is reset when a refresh cycle is requested.
Refresh Counter
The refresh counter contains the address of the row to be
refreshed. This counter is incremented after every refresh
cycle.
CAS
c::::=J
~
X,/ClK
RASO
RAS,
3 TO 5 pF
8202
RAS2
RAS3
XACK
SACK
TANK
Multiplexer
The multiplexer is deSigned to provide the dynamic RAM
array with row addresses, column addresses and refresh
addresses at the proper times. Its inputs consist of ALo-5,
AL6/0P3, AHo-6, and the refresh counter.
If AL6/0P3 is pulled to +12V through a 5Kn resistor, the
8202 configures itself for 4K RAMs. In this mode, ALo-5
provides the multiplexer with the six bit row address. AHo5 provides the multiplexer with the six bit column address.
r----------- --,
I
I
I
I
I
I
I USED WITH OVERTONE
I CRYSTALS ONLY
1
f = 2'VlCT
:
ALo.,
r-=-_ __r __ :
CBP
L _______
AL,;/OP,
CT
~
---------v1
AH=,:----~I RESET REFRESH COUNTER.
SET DELAYED SACK MODE.
Inputs Bo and B1/0P1 are used to select one of four banks
of dynamic RAM via the RASo-3 outputs.
START WRITE
CYCLE
If B1/0P1 is pulled to +12V through a SKU resistor, the
8202 configures itself to the Advanced Read Mode. This
mode changes the function of the RD/S1 and REFRQ/ ALE
inputs and disables the RASo and RAS1 outputs.
START READ
CYCLE
SYSTEM OPERATION
1. START REFRESH CYCLE.
The 8202 is always in one of the following states:
1. Idle.
2. Performing
3. Performing
4. Performing
5. Performing
>-=-t----1 ~: ~NE;:~::~:~~~ TIMER.
ADDRESS COUNTER.
a
a
a
a
Test Cycle.
Write Cycle.
Read Cycle.
Refresh Cycle.
IDLE LOOP
Idle
When the 8202 is idle, no cycle is in progress, the arbiter
monitors internal and external cycle requests, and the
refresh timer counts towards an internal refresh cycle
request. (Fig. X.1)
While the 8202 is idle, the arbiter samples access cycle
requests and refresh cycle requests, internal or exter·
nal, on the rising edge of clock. If both Read and Write
cycle requests are active when sampled, a test cycle is
started. If a write·cycle request is active when sampled,
a write cycle is started. If a read cycle request is active
when sampled, a read cycle is started. If a refresh cycle
request was previously pulsed or is active when
sampled, a refresh cycle is started. Due to internal
delays, if an access cycle request and a refresh cycle
request occur simultaneously, the access cycle will be
executed before the refresh cycle is executed.
Test Cycle
When a test cycle is started, (Read and Write Cycle
Requests both active when sampled) the refresh counter
is set to zero and the delayed SACK mode is reset, while
the 8202 executes a write cycle. This cycle is used for
testing only and is not recommended for normal system
operation.
Write Cycle (Fig. X.2)
When a write cycle is started, (Write·Cycle Request
active when sampled) the Multiplexer drives the
OUT 0-6 pins with the low order address. Then, if the
delayed SACK Mode is not set, SACK is activated. The
row address is strobed into the selected bank of RAMs.
The multiplexer then drives the OUT 0-6 pins with the
high order address and the write enable (WE) pin is actio
vated. The column address is then strobed into the RAM
array.
Near the end of the cycle, the XACK output is activated.
If the Delayed SACK Mode is set, SACK had the same
timing as XACK. At the end of the cycle, all signals are
deactivated, the Delayed SACK Mode is exited, and the
precharge time begins. After the precharge time, the
8202 re·enters the idle state. The refresh timer con·
ti~ues to count during access cycles.
If the REFRQ pin is pulsed or held active while a write
cycle is in progress, a refresh cycle will occur immedi·
ately following the write cycle, if the Advanced Read
Mode is not selected.
Read Cycle (Fig. X.3)
Read cycle operation is the same as write cycle opera·
tion, except the write enable (WE) signal is not activated.
11·17
8202
ately following the read cycle, if the Advanced Read
Mode is not selected.
If the REFRQ pin is pulsed or held active while a read
cycle is in progress, a refresh cycle will occur immedi-
NOTE 1
OUTO·6
~
ROW ADDRESS
X. . .____
-'X. . .___
CO_L_U_M_N_A_DD_R_E_SS_ _ _ _
RO_W_AD_D_R_ __
DELAYED SACK MODE
\--------------~
SACK
7
\
RASO·3
/
\
WE
C
/
/
\
CAS
PRECHARGE
J
t
\
XACK
/
NOTE 1
OUTO.s
~
ROW ADDRESS
X'-____
..JX'--__
C_O_L_U_MN_AD_D_R_ES_S_ _ _ _
R_O_W_A_D_DR_ __
\ ---------------\
DELAYED SACK MODE
/
\'---_ _-----17
PRECHARGE
\
/
\
/
Refresh Counter. The 8202 then activates the Row
Address Strobe (RAS 0-3) signals. At the end of the
refresh cycle, all signals are deactivated, the refresh
counter is incremented, and the precharge time begins.
A fter the precharge time, the 8202 re-enters the Id Ie
State.
'
Refresh Cycle (Fig. X.4)
When a refresh cycle is started, (refresh-cycle request
previously pulsed or active when sampled) the 8202
resets the Refresh Timer. The Multiplexer drives the
OUT 0-6 pins with the refresh address cqntained in the
11-18
8202
NEXT REFRESH ADDRESS
\---------/
ROW ADD!!,
L
PRECHARGE
Hidden Refresh Cycle
Distributed hidden refresh operation is most efficient if
REFRQ is strobed during a command cycle such as
fetch, where it is intended for the refresh cycle to follow.
This is illustrated for 8085 in the following diagram.
REFRQ
8085
8202
System Configurations
Currently, there exists a wide range of processor bus
structures, processor speeds, and memory speeds. As a
result, the 8202 offers many possible system configura·
tions with equally many cost·performance tradeoffs.
WIi - - - - - - - - - - - - - - - - WIi
The following system block diagram illustrates just one
of the possible system configurations supported by the
8202:
2117
DYNAMIC RAM ARRAY
~o~
~D~
_ _~~~1i1l~1
~-~1_--~------~A~~,~~~----~--Aa_15
~Ao_15
ALE
~~-8
8Ta 8212
8202
(16K MODE)
808SA ADo-,
GND-
iIii
WR
101M
~
L-_ _
REA_DY..JI
'--1111
rv
CUTO_II
r-,-. !!Q1S,
r-r- WR
r-i-- m
n
4
WE!~=~] I-
r---
~FRQ/ALE ~
"MOO
~r--
1Wit-__§m<_A_=--1 RAs3
WE
DIM DOUT
Jj
en
r--- I
"gn""N"'D;,.O""UTcs---I
~
U
[V
r--
OTHER
SYSTEM
ACKNOWLEDQE
LINES
.1
BA'NKO
r
"0-8
!---<
r---
Ao.,
We
CAS
RAS
DIN DoUT
uTI
+
BAL
Ao.,
r--
'--
11-19
I
I--
8202
Other system configurations are described in the Intel,
Application Note AP45, "Using the 8202 Dynamic RAM
Controller." Other related documents are:
• AR-1, "Simplify Your Dynamic RAMlMfcroprocessor
Interface."
. .
.. , ,
• "Intel Memory Design Handbook" (Dynamic Ram sections).
• AP-38, "Application Techniques for the Intel
Bus."
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
.,"'
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature .............. -65·C to + 150·C
Voltage On Any Pin
With Respect to Ground ............. -0.5V to + 7V
Power Dissipation ........................ 1.4 Watts
D.C. CHARACTERISTICS
TA=O·C to 70·C; Vee =5.0V ± 10%; GND= OV
Symbol
Parameter
Min
Test Conditions
Max
Units
Ve
Input Clamp Voltage
-1.0
V
Icc
Power Supply Current
250
mA
IF
Forward Input Current
Xl /ClK
All Other Inputs
-2.0
-320
mA
,.A
VF=0.45V
VF=0.45V
IR
Reverse Input Current
40
IJ.A
VR=Vce
VOL
Output low Voltage
0.45
0.45
V
V
IOL=5 mA
IOL=3 mA
V
V
IOH= -1 mA
IOH= -1 mA
Mrn<, XArn<
All Other Outputs
VOH
Output High Voltage
SACK,XACK
All Other Outputs
V,L
Input low Voltage
V,H
Input High Voltage
2.4
2.6
I,
0.8
2.0
le= -5 mA
V
Vec=5.0V
V
Vee=5.0V
CAPACITANCE
Symbol
C'N
Parameter
,
'\'
8OS5A,
Min
Input Capacitance
Max
30
11-20
Units
Test Conditions
pF
F= 1 MHz
VSIAS = 2.5V, Vee = 5V
TA = 25·C
8202
Measurements made with respec~ to RAs1l"T;Xf;)','
output will be held in the marking state upon Reset.'
'
Programming the 8251A
Prior to starting data transmission or reception, the 8251A
must be loaded with a set of control words generated by
the CPU. These control signals define the complete functional definition of the 8251A and must immediately folIowa Reset operation (internal or external).
The control words are split into two formats:
1. Mode Instruction
2. Command Instruction
Mode Instruction
ADDRESS BUS
-T]
\
CONTROL BUS>
I/O R
9,
I/O W RESET
(TTL)
c=
J
DATA BUS
8
7
cs
Command Instruction
Th is format defines a status word that is used to control the
actual operation of the 8251 A.
L
c/o
This format defines the general operational characteristics
of the 8251A. It must follow a Reset operation (internal or
external). Once the Mode Instruction has been written into
the 8251A by the CPU, SYNC characters or Command Instructions may be inserted.
D7-DO
RD
WR
RESET
eLK
8251A
Figure 4_ 8251A Interface to 8080 Standard
System Bus
DETAILED OPERATION DESCRIPTION
General
The complete functional definition of the 8251 A is programmed by the system's software. A set of control words
must be sent out by the CPU to initialize the 8251A to
support the'desired communications format. These control
words will program the: BAUD RATE, CHARACTER
LENGTH, NUMBER OF STOP BITS, SYNCHRONOUS or
ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc. In the Synchronous Mode, options are also provided to select either internal or external character synchronization.
Once programmed, the 8251A is ready to perform its communication functions. The TxRDY output is raised "high"
to signal the CPU that the 8251A is ready to receive a data
character from the CPU. This output (TxRDY) is reset
automaticallv when the CPU writes a character into the
8251A. On the other hand, the 8251A receives serial data
from the MODEM or I/O device. Upon receiving an entire
character, the RxRDY output is raised "high" to signal the
CPU that the 8251 A has a complete character ready for the
CPU to fetch_ RxRDY is reset automatically upon the CPU
data read operation.
Both the Mode and Command Instructions must conform
to a specified sequence for proper device operation. The
Mode Instruction must be inserted immediately following a
Reset operation, prior to using the 8251A for data communication.
All control words written into the 8251A after the Mode Instruction will load the Command Instruction. Command
Instructions can be written into the 8251A at any time in
the data block during the operation of the 8251 A. To return to the Mode Instruction format, the master Reset bit
in thp. Command Instruction word can be set to initiate an
internal Reset operation which automatically places the
8251A back into the Mode Instruction format. Command
Instructions must follow the Mode Instructions or Sync
characters.
*
eiD '" 1
MODE INSTRUCTION
C/O
eo,
SYNC CHARACTER 1
CID
~
SYNC CHARACTER 2
,
}
C/D'" 1
COMMAND INSTRUCTION
c/o'" 0
DATA
C/D'" 1
COMMAND INSTRUCTION
CID " 0
DATA
C/O'" 1
COMMAND Il\lSTRUCTtON
The second SYNC character is skipped if MODE instruction
has programmed the 8251A to single character Internal SYNC
Mode. Both SYNC characters are skipped if MODE instruction
has programmed the 8251A to ASYNC mode.
Figure 5_ Typical Data Block
11-26
SYNC MODE
ONLY *
8251A
Synchronous Mode (Transmission)
the SYNDET F IF is reset at each StqtU5 RelKj, r1l9/
'1,"',
'COMMENT: Stresses above tho$e"/isteP,tlhli/i!ff"t~solute
Maximum Ratings" may cause perrii~lr~ht;d~rf1' . q . . .,e
device. This is a stress rating only and fUrlc..{fOt1i/.{
tion of the device at these or any other cond/tli7~.~~'bl)·
those indicated in the operational sections of this %pe~;ii,'
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... oOe to 70°C
Storage Temperature . . . . . . . . . . . . . . -65°e to +150 o e
Voltage On Any Pin
With Respect to Ground . . . . . . . . . . . . -O.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS
T A ~ DoC to 70°C; Vee ~ 5.0V ±5%; GND ~ OV
Symbol
Min.
Max.
Unit
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.2
VOL
Output Low Voltage
VOH
Output High Voltage
IOFL
VIL
Parameter
Test Conditions
Vee
V
0.45
V
Output Float Leakage
±10
!LA
IlL
I nput Leakage
±10
!LA
VIN ~ Vee TO 0.45V
Icc
Power Supply Current
100
mA
All Outputs
2.4
V
IOL
~
2.2 mA
IOH
~
-400 !LA
VOUT ~ Vee TO 0.45V
~
High
CAPACITANCE
TA ~ 25°C; Vee ~ GND ~ OV
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
CIN
Input Capacitance
10
pF
fc
ClIO
I/O Capacitance
20
pF
Unmeasured pins returned to GND
~
lMHz
+20
L
+10
"
>-
..,....
2V
~
0
420n
I-
:s~ lN914
8251A
0
/
~
I-
"0..,
I----t---<> OUT
·1 0
6K
·20
-100
/
/
"
SPEC.
V
·50
+50
J. CAPACITANCE (pF)
Figure 16. Test Load Circuit
Figure 17. Typical A Output Delay vs. A
Capacitance (pF)
11·28
+100
8251A
A.C. CHARACTERISTICS
TA = DOC to 70°C; VCC = 5.0V ±5%; GND = OV
Bus Parameters (Note 1)
Read Cycle:
PARAMETER
SYMBOL
MIN.
MAX.
TEST CONDITIONS
UNIT
tAR
Address Stable Before READ (CS, C/D)
50
ns
Note 2
tRA
Address Hold Time for READ (CS, C/D)
50
ns
Note 2
tRR
READ Pulse Width
250
ns
tRO
Data Delay from READ
tOF
READ to Data Floating
10
250
ns
100
ns
MAX.
UNIT
3, CL = 150 pF
Write Cycle:
SYMBOL
PARAMETER
MIN.
tAW
Address Stable Before WR ITE
50
ns
tWA
Address Hold Time for WR ITE
50
ns
tww
WR ITE Pulse Width
250
ns
tow
Data Set Up Time for WR ITE
150
ns
two
Data Hold Time for WRITE
30
ns
tRV
Recovery Time Between WRITES
6
tCY
TEST CONDITIONS
Note 4
NOTES: 1. AC timings measured VOH = 2.0, VOL = 0.8, and with load circuit of Figure 1.
2. Chip Select ICS) and Command/Data IC/D) are considered as Addresses.
3. Assumes that Address is valid before RD •.
4. This recovery time is for Mode Initialization only. Write Data is allowed only when TxROY = 1.
Recovery Time between Writes for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY.
Input Waveforms for AC Tests
2.4---~X
0.45
_ _ _ _-J
:::
TEST
POINTS
11-29
:::x. .____
8251A
Other Timings:
SYMBOL
tCY
t
t¢
tR, tF
tOTx
tSRx
tHRx
fTx
tTPW
tTPO
fRx
tRPW
tRPO
tTxROY
tTxROY CLEAR
tRxROY
tRxROY CLEAR
tiS
I
PARAMETER
Clock Period
Clock High Pulse Width
Clock Low Pulse Width
Clock Rise and Fall Time
TxD Delay from Falling Edge of TxC
Rx Data Set-Up Time to Sampling Pulse
Rx Data Hold Time to Sampling Pulse
Transmitter Input Clock Frequency
lx Baud Rate
16x Baud Rate
64x Baud Rate
Transmitter Input Clock Pulse Width
lx Baud Rate
16x and 64x Baud Rate
Transmitter Input Clock Pulse Delay
lx Baud Rate
16x and 64x Baud Rate
Receiver Input Clock Frequency
lx Baud Rate
16x Baud Rate
64x Baud Rate
Receiver Input Clock Pulse Width
lx Baud Rate
l6x and 64x Baud Rate
Receiver Input Clock Pulse Delay
lx Baud Rate
16x and 64x Baud Rate
TxRDY Pin Delay from Center of last Bit
TxRDY .j, from Leading Edge of WR
RxRDY Pin Delay from Center of last Bit
RxRDY .j, from Leading Edge of RD
Internal SYNDET Delay from Rising
Edge of RxC
MIN.
320
MAX.
1350
UNIT
ns
140
90
5
tcy-eo
ns
ns
ns
20
1
2
2
DC
DC
DC
{J.s
{J.s
{J.s
64
310
615
kHz
kHz
kHz
12
1
tCY
tCY
15
3
tCY
tCY
DC
DC
DC
TEST CONDITIONS:,
Notes 5, 6
64
310
615
kHz
kHz
kHz
12
1
tCY
tCY
15
3
tCY
tCY
tCY
ns
8
180
24
150
tCY
ns
Note
Note
Note
Note
7
7
7
7
24
tCY
Note 7
16
tCY
Note 7
tES
External SYNDET Set-Up Time Before
Falling Edge of RxC
tTxEMPTY
twc
TxEMPTY Delay from Center of Last Bit
Control Delay from Rising Edge of
WRITE (TxEn, DTR, RTS)
20
8
tCY
tCY
Note 7
Note 7
tCR
Control to READ Set-Up Time (DSR, CTS)
20
tCY
Note 7
5.
The TxC and RxC frequencies have the following limitations with respect to ClK.
For 1x Baud Rate, fTx or fRx ..;; 1/(30 tCY)
For 16x and 64x Baud Rate, fTx or fRx ..;; 1/(4.5 tCY)
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
11-30
8251A
Receiver Control & Flag Timing (ASYNC Mode)
FRA~~NI\~~~:7:
----------------------1"---1--1------1------
Transmitter Control & Flag Timing (SYNC Mode)
-----..
Tx READY
IPIN)
'1
~''----<
Tx READY
{STATUS BITl
WrDATA
MARKING STATE
\"I,OATA
EXAMPLE FORMAT
23.
...
o
\
~
3
CHAR 1
•
...
0'
wrCOMMA~
Wr DATA
CHAR4
SYN~\
DATA
CHAR 2
CHAR 1
0\
W,COMMAND
SBRK,
Wr DATA
CHAR 3
~
IL
~
,r-
t
{\
I~
r---'
I
- , , - - W- ' L -
CID
~
CH~f~
SYNC CHAR 2
0'
23'
7
'"
J'
...
J.
0"
...
WrOATA
MARKI~~
;;~'
C~~TRA~
"'
II
MARKING
STATE
SPACING
STATE
DATA
CHAR S
STATE
o.
Z 3'
'"
"
....
SYNC
CHAR
0'
ETC
23.
H,
0"
5 BIT CHARACTER WITH PARITY, 2. SYNC CHARACTERS
Receiver Control & Flag Timing (SYNC Mode)
115_
tES~
II--
SYNDET IS,B)
~
'L-~
I
,--
~
OVERRUN
ERROR (S,BI
LOST
ct;:iM "tr(t:
Rx ROY (PINI
CIO
n
~OTEuf
SYNDET
(PIN) NOTE "1
---1~'EH
1
R.En I
CHAR 3
--V
DON'T
SYNC
SYNC
CARE
CHAR 1
CHAR 2
• "'}.,
0
,
',>},' ,
0
,
,
,
•
DATA
CHAR 1
~
CHAR 2
>--DATA
CHAR 3
.. 0' 2"' .. 0 " " ' .. 0 ' , 3'
, I I I I I I I I I I I II ~lJAJASs~lEL~/
JlJ1IUlJ
~k=
CHAR 1
• loX' , , •
I - -I -
'-
+
",""
3'
<[
DATA
CHAR 1
DON'T CARE
~
~
~
x x x x xo'
/
EXIT HUNT MODE
SET S'/N DET (STATUS BIT)
11-31
Rd DATA
hv
SYNC CHAR 2
ftf
I
J1Jl
IN1ERNAL SYNC, 2 SYNC CHARACTERS, 5 BITS, WITH PARITY
E',TERNAL SYNC, 5 sns, WITI-I PARITY
, r---
Rd STATUS
CHAR 1
TTfI T
LEXIT HUNT MODE
SET SYNC DET
NOTE "1
NOTE "'2
--
Ild:;::~S
RdDATA
CHAR 1
., ,
I, -
234
DATA
L
CHAR 2
,,01"34<[
CHAR;~
BEGINS
r-ETC,
Inter
8253/8253·5
PROGRAMMABLE INTERVAL TIMER
• MCS-85™ Compatible 8253.5
• Count Binary or BCD
• 3 Independent 16·Blt Counters
• Single
+ 5V Supply
• DC to 2 MHz
• 24·Pln Dual In·Llne Package
• Programmable Counter Modes
The Intel@ 8253 is a programmable counter/timer chip designed for use as an Intel microcomputer peripheral. It uses
nMOS technology with a single +5V supply and is packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with a count rate of up to 2 MHz. All modes of operation are software programmable.
PIN CONFIGURATION
0,
Vee
0,
WR
AD
BLOCK DIAGRAM
eLK 0
GATEa
OUT
03
A,
D,
Ao
elK 2
0,
a
eLK 1
GATE 2
elK 1
aUTO
GATE 1
GATE 0
GND
GATE 1
AO --~-I
OUT 1
OUT 1
A,---o-J
'--.....--'
cs-------'
PIN NAMES
ClK 2
°7- DO
DATA BUS {8-Bln
CONTROL
eLK N
COUNTER CLOCK INPUTS
REGISTER
GATE N
COUNTER GATE INPUTS
OUT N
COUNTER OUTPUTS
AD
READ COUNTER
WR
WRITE COMMAND OR DATA
CS
CHIP SELECT
Ao·A
V
COUNTER SELECT
GND
GROUND
WORD
COUNTER
=2
GATE 2
OUT2
+5 VOLTS
INTERNAL BUS /
11-32
825318253·5
FUNCTIONAL DESCRIPTION
AO,A1
General
These inputs are normally connected to the address bus.
Their function is to select one of the three counters to be
operated on and to address the control word register for
mode selection.
The 8253 is a programmable interval timer/counter
specifically designed for use with the Intel'· Microcomputer systems. Its function is that of a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
CS (Chip Select)
A "low" on this input enables the 8253. No reading or
writing will occur unless the device is selected. The CS
input has no effect upon the actual operation of the
counters.
The 8253 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in systems software, the programmer configures the
8253 to match his requirements, initializes one of the
counters of the 8253 with the desired quantity, then upon
command the 8253 will count out the delay and interrupt
the CPU when it has completed its tasks. It is easy to see
that the software overhead is minimal and that multiple
delays can easily be maintained by assignment of priority
levels.
Other counter/timer functions that are non-delay in
nature but also common to most microcomputers can be
implemented with the 8253.
• Programmable Rate Generator
• Event Counter
• Binary Rate Multiplier
• Real Time Clock
• Digital One-Shot
• Complex Motor Controller
::,
Q--Iiod
.--.,..-d
Data Bus Buffer
This 3-state, bi-directional, 8-bit buffer is used to interface
the 8253 to the system data bus. Data is transmitted or
received by the buffer upon execution of INput or OUTput
CPU instructions. The Data Bus Buffer has three basic
functions.
1. Programming the MODES of the 8253.
2. Loading the count registers.
3. Reading the count values.
ReadlWrite Logic
The ReadlWrite Logic accepts inputs from the system bus
and in turn generates control signals for overall device
operation. It is enabled or disabled by CS so that no
operation can occur to change the function unless the
device has been selected by the system logic.
Figure 1. Block Diagram Showing Data Bus Buffer and
Read/Write Logic Functions
RD (Read)
A "low" on this input informs the 8253 that the CPU is
inputting data in the form of a counters value.
WR (Write)
A "low" on this input informs the 8253 that the CPU is
outputting data in the form of mode information or loading
counters.
11-33
CS
RD
WR
A1
Ao
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Load Counter No. 0
0
1
Load Counter No.1
1
0
Load Counter No.2
1
1
Write Mode Word
1
0
0
0
Read Counter No. 0
1
1
Read Counter No.1
1
1
1
0
Read Counter No.2
1
1
No-Operation 3-State
1
1
1
1
0
0
0
0
X
X
X
X
Disable 3-State
0
1
1
X
X
No-Operation 3-State
8253/8253·5
Control Word Register
The Control Word Register is selected when AD, A 1 are 11.
It then accepts information from the data bus buffer and
stores it in a register. The information stored in this
register controls the operational MODE of each counter,
selection of binary or BCD counting and the loading of
each count register.
The Control Word Register can only be written into; no
read operation of its contents is available.
Counter #0, Counter #1, Counter #2
These three functional blocks are identical in operation so
only a single Counter will be described. Each Counter
consists of a single, l6-bit, pre-settable, DOWN counter.
The counter can operate in either binary or BCD and its
input, gate and output are configured by the selection of
MODES stored in the Control Word Register.
The counters are fully independent and each can have
separate Mode configuration and counting operation,
binary or BCD. Also, there are special features in the
control word that handle the loading of the count value so
that software overhead can be minimized for these
functions.
The reading of the contents of each counter is available to
the programmer with simple READ operations for event
counting applications and special commands and logic
are included in the 8253 so that the contents of each
counter can be read "on the fly" without having to inhibit
the clock input.
8253 SYSTEM INTERFACE
Figure 2. Block DIagram ShowIng Control Word
RegIster and Counter Functions
The 8253 is a component of the Intel'" Microcomputer
Systems and interfaces in the same manner as all other
peripherals of the family. It is treated by the systems
software as an array of peripheral 1/0 ports; three are
counters and the fourth is a control register for MODE
programming.
ADDRESS BUS (16)
CONTRDLBUS
Basically, the select inputs AD, A 1 connect to the AD, A 1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method.
Or it can be connected to the output of a decoder, such as
an Intel@ 82D5 for larger systems.
RD
FIgure 3. 8253 System Intertace
11·34
WR
8253/8253·5
M -
OPERATIONAL DESCRIPTION
M2
Ml
MO
0
0
0
General
The complete functional definition of the 8253 is
programmed by the systems sof!ware. A set of control
words must be sent out by the CPU to initialize each
counter of the 8253 with the desired MODE and quantity
information. These control words program the MODE,
Loading sequence and selection of binary or BCD
counting.
Once programmed, the 8253 is ready to perform whatever
timing tasks it is assigned to accomplish.
MODE:
Mode 0
0
0
1
Mode 1
X
1
0
Mode 2
X
1
1
Mode 3
1
0
0
Mode 4
1
0
1
Mode 5
BCD:
The actual counting operation of each counter is
completely independent and additional logic is provided
on-chip so that the usual problems associated with
efficient monitoring and management of external,
asynchronous events or rates to the microcomputer
system have been eliminated.
o
Binary Counter 16-bits
Binary Coded Decimal (BCD) Counter
(4 Decades)
Programming the 8253
All of the MODES for each counter are programmed by the
systems software by simple liD operations.
Each counter of the 8253 is individually programmed by
writing a control word into the Control Word Register.
(AD, Al = 11)
Counter Loading
The count register is not loaded until the count value is
written (one or two bytes, depending on the mode
selected by the RL bits), followed by a rising edge and a
falling edge of the clock. Any read of the counter prior to
that falling clock edge may yield invalid data.
Control Word Format
MODE Definition
SCl
SCD
RL1
RLD
I M21
Ml
01
Do
MD
BCD
Definition of Control
SC -
RL -
Select Counter:
SCl
seo
0
0
1
0
1
Select Counter 0
0
Select Counter 2
1
1
Illegal
Select Counter 1
MODE 0: Interrupt on Terminal Count. The output will
be initially low after the mode set operation. After the
count is loaded into the selected count register, the output will remain low and the counter will count. When terminal count is reached the output will go high and remain high until the selected count register is reloaded
with the mode or a new count is loaded. The counter
continues to decrement after terminal count has been
reached.
Rewriting a counter register during counting results in
the following:
(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
MODE 1: Programmable One-Shot. The output will go
Iowan the count following the rising edge of the gate input.
Read/Load:
RLl
RLO
0
0
Counter Latching operation (see
R EAD/WR ITE Procedure Section)
1
0
Read/Load most significant byte only.
0
1
Read/Load least significant byte only.
1
1
Read/Load least significant byte first,
then most significant byte.
The output will go high on the terminal count. If a new
count value is loaded while the output is low it will not
affect the duration of the one-shot pulse until the succeeding trigger. The current count can be read at any
time without affecting the one·shot pulse.
The one-shot is retriggerable, hence the output will remain low for the full count after any rising edge of the
gate input.
11-35
8253/8253·5
MODE 2: Rate Generator. Divide by N counter. The out·
put will be low for one period of the input clock. The
period from one output pulse to the next equals the
number of. input counts in the count register. If the
count register is reloaded between output pulses the
present period will not be affected, but the subsequent
period will reflect the new value.
If the count register is reloaded between output pulses
the present period will not be affected, but the subse·
quent period will reflect the new value. The count will be
inhibited while the gate input is low. Reloading the
counter register will restart counting beginning with the
new number.
The gate input, when low, will force the output high.
When the gate input goes high, the counter will start
from the initial count. Thus, the gate input can be used
to synchronize the counter.
MODE 5: Hardware Triggered Strobe. The counter will
start counting after the rising edge of the trigger input
and will go low for one clock period when the terminal
count is reached. The counter is retriggerable. The out·
put will not go low until the full count after the rising
edge of any trigger.
When this mode is set, the output will remain high until
after the count register is loaded. The output then can
also be synchronized by software.
MODE 3: Square Wave Rate Generator.Similar to MODE
2 except that the output will remain high until one half
the count has been completed (for even numbers) and
go low for the other half of the count. This is accom·
plished by decrementing the counter by two on the fall·
ing edge of each clock pulse. When the counter reaches
terminal count, the state of the output is changed and
the counter is reloaded with the full count and the whole
process is repeated.
~
Status
Modes
0
Low
Disables
Rising
--
counting
1
--
1) Initiates
High
Enables
counting
--
counting
2) Resets output
after next clock
If the count is odd and the output is high, the first clock
pulse (after the count is loaded) decrements the count
by 1. Subsequent clock pulses decrement the clock by
2. After timeout, the output goes low and the full count
is reloaded. The first clock pulse (following the reload)
decrements the counter by 3. Subsequent clock pulses
decrement the count by 2 until timeout. Then the whole
process is repeated. In this way, if the count is odd, the
output will be high for (N + 1)/2 counts and low for
(N - 1)/2 counts.
MODE 4: Software Triggered Strobe. After the mode is
set, the output will be high. When the count is loaded,
the counter will begin counting. On terminal count, the
output will go low for one input clock period, then will
go high again.
Low
Or Going
2
1) Disables
counting
2) Sets output
Initiates
counting
Enables
counting
Immediately
high
1) Disables
counting
2) Sets output
Immediately
high
Initiates
Enables
counting
counting
4
Disables
counting
, --
Enables
5
--
Initiates
--
3
counting
Figure 4. Gate Pin Operations Summary
11·36
counting
825318253·5
MODE 0: Interrupt on Terminal Count
MODE 3: Square Wave Generator
CLOCK
CLOCK
I
WFrn~
I
~
4
OUTPUT (INTERRUPT)
(n-4)
OUTPUT (n=4)
I
2
1
i
OUTPUT (n., 5)
I-t-n----{
I
I
I
I
WRm~
I
I
GATE-----....l,:L....J.....I..:- - - -
5
OUTPUT (iNTERRUPT)
(m-5)
4
3
2
1
0
~
A
MODE 1: Programmable One·Shot
MODE 4: Software Triggered Strobe
CLOCK
CLOCK
WIIn~
TRIGGER
4
OUTPUT
_ _____..;4~.::3~2'__~1_0
~
3
2
~
OUTPUT
1
~L~~~~j----------
LOADn~~----------------
TRIGGER~
OUTPUT
GATE
- - . ,4i.~3_2~~4~3~:2~1~r------
--------~~~--------_
______4'--____~4~3'--~2~1~0
U-
OUTPUT
MODE" 2: Rate Generator
MODE 5: Hardware Triggered Strobe
CLOCK
GATE
---JI"------4
OUTPUT (n - 4)
3
2
1
0
Wl"--------
GATE~
4343210
OUTPUT (n = 41
Figure 5. 8253 Timing Diagrams
11·37
LJ
6253/8253·5
8253 READ/WRITE PROCEDURE
Write Operations
MODE Control Word
Counter n
The systems software must program each counter of the
8253 with the mode and quantity desired. The programmer must write out to the 8253 a MODE control word and
the programmed number of count register bytes (lor 2)
prior to actually using the selected counter.
The actual order of the programming is quite flexible.
Writing out of the MODE control word can be in any
sequence of counter selection, e.g., counter #0 does not
have to be first or counter #2 last. Each counter's MODE
control word register has a separate address so that its
loading is completely sequence independent. (SCO, SCll
The loading of the Count Register with the actual count
value, however, must be done in exactly the sequence
programmed in the MODE control word (RLO, RL 1). This
loading of the counter's count register is still sequence
independent like the MODE control word loading, but
when a selected count register is to be loaded it must be
loaded with the number of bytes programmed in the
MODE control word (RLO, RL 1). The one or two bytes to
be loaded in the count register do not have to follow the
associated MODE control word. They can be programmed
at any time following the MODE control word loading as
long as the correct number of bytes is loaded in order.
All counters are down counters. Thus, the value loaded
into the count register will actually be decremented.
Loading all zeroes into a count register will result in the
maximum count (2 16 for Binary or 104 for BCD). In MODE
the new count will not restart until the load has been
completed. It will accept one of two bytes depending on
how the MODE control words (RLO, RL 1) are programmed. Then proceed with the restart operation.
°
LSB
Count Register byte
Counter n
MSB
Count Register byte
Counter n
Note: Format shown is a simple example of loading the 8253 and
does not imply that it is the only format that can be used.
Figure 6. Programming Format
MODE Control Word
No.1
Counter
°
Al
AO
1
1
No. 2
MODE Control Word
Counter 1
1
1
No.3
MODE Control Word
Counter 2
1
1
Count Register Byte
Counter 1
0
1
Count Register Byte
Counter 1
0
1
No. 4
LSB
No. 5
MSB
No.6
LSB
Count Register Byte
Counter 2
1
0
No.7
MSB
Count Register Byte
Counter 2
1
0
No.8
LSB
0
0
No. 9
MSB
0
0
Count Register Byte
Counter 0
Count Register Byte
Counter 0
Note: The exclusive addresses of each counter's count register make
the task of programming the 8253 a very simple matter, and
maximum effective use of the device will result if this feature
is fully utilized.
Figure 7. Alternate Programming Formats
11-38
825318253·5
Read Operation Chart
Read Operations'
In most counter applications it becomes necessary to read
the value of the count in progress and make a
computational decision based on this quantity. Event
counters are probably the most common application that
uses this function. The 8253 contains logic that will allow
the programmer to easily· read the contents of any of the
three counters without disturbing the actual count in
progress.
There are two methods that the programmer can use to
read the value of the counters. The first method involves
the use of simple I/O read operations of the selected
counter. By controlling the AD, A 1 inputs to the 8253 the
programmer can select the counter to be read (remember
that no read operation of the mode register is allowed AD,
Al-11). The only requirement with this method is that In
order to assure a stable count reading the actual operation
of the selected counter must ~ inhibited either by
controlling the Gate input or by external logic that inhibits
the clock input. The contents of the counter selected will
be available as follows:
A1
AO
0
0
RO
0
Read Counter No. 0
0
1
0
Read Counter No.1
1
0
0
Read Counter No.2
1
1
0
Illegal
Reading While Counting
first I/O Read contains the least significant byte (LSB).
In order for the programmer to read the contents of any
counter without effecting or disturbing the counting
operation the 8253 has special internal logiC that can be
accessed uSing simple WR commands to the MODE
register. BaSically, when the programmer wishes to read
the con.!ents of a selected counter "on the fly" he loads the
MODE register with a special code which latches the
present count value into a storage register so that its
contents contain an accurate, stable quantity. The
programmer then issues a normal read command to the
selected counter and the contents of the latched register is
available.
second I/O Read contains the most significant byte
(MSB).
MODE Register for Latching Count
"
Due to the internal 'lOgic of the 8253 it is absolutely
necessary to complete the entire reading procedure. If two
bytes are programmed to be read then two bytes must be
read before any loading WR command can be sent to the
same counter.
AO, A1
11
DO
x
SC1,SCO- specify counter to be latched.
05,04
00 designates counter latching operation
X
don't care.
The same limitation applies to this mode of reading the
counter as the previous method. That is, it is mandatory
to complete the entire read operation as programmed.
This command has no effect on the counter's mode.
ClK
3MHz
~2
8085
·1.5MHz
ClK
8253-5
'If an 8085 clock output is to drive an 8253·5 clock input, it must be reduced to 2 MHz or less.
Figure 8. MCS-85™ Clock Interface"
11-39
8253/8253·5
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for ex tended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias
Storage Temperature
Voltage On Any Pin
With Respect to Ground
Power Dissipation ........... .
...
D.C. CHARACTERISTICS
DOC to 7DOC
-65°Cto+1500C
-D.5Vto+7V
1 Watt
(TA ~ o°c to 70°C; Vee ~ 5V ±5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.2
Vee+· 5V
V
VOL
Output low Voltage
0.45
V
Note 1
VOH
Output High Voltage
V
Note 2
2.4
IlL
I nput load Current
±10
IOFL
Output Float Lea kage
±10
/lA
140
mA
Vee Supply Current
lee
Note 1: 8253, IOL ~ 1.6 mA; 8253-5, IOL = 2.2 mAo
Note 2: 8253, IOH ~ -150 /lA; 8253-5, IOH ~ -400 /lA.
CAPACITANCE
/lA
TEST CONDITIONS
= Vee to OV
VOUT = Vee to OV
VIN
TA = 25°C; Vee = GND = ov
Symbol
Parameter
Max.
Unit
CIN
I nput Capacitance
10
pF
fc = 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to Vss
Min.
Typ.
11-40
Test Conditions
8253/8253·5
A.C. CHARACTERISTICS
TA = o°c to 70°C; Vee = 5.0V ±5%; GND = OV
Bus Parameters (Note 1)
Read Cycle:
8253
SYMBOL
PARAMETER
MIN.
8253-5
MAX.
MIN.
MAX.
UNIT
tAR
Address Stable Before READ
50
30
tRA
Address Hold Time for READ
5
5
ns
tRR
READ Pulse Width
400
300
ns
tRD
Data Delay From R EADI21
tDF
READ to Data Floating
25
tRV
Recovery Time Between READ
and Any Other Control Signal
1
ns
300
125
25
200
ns
100
ns
1
!.IS
Write Cycle:
8253-5
8253
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
MAX.
UNIT
tAW
Address Stable Before WR ITE
50
30
ns
tWA
Address Hold Ti me for WR IT E
30
30
ns
tww
WR ITE Pulse Width
400
300
ns
tDW
Data Set Up Time for WR ITE
300
250
ns
tWD
Data Hold Time for WR ITE
40
30
ns
1
1
!.Is
tRv
Recovery Time Between WRITE
and Any Other Control Signal
Notes: 1. AC timings measured at VOH = 2.2. VOL = 0.8
2. Test Conditions: 8253. CL = 1 OOpF; 8253-5: CL = 150pF.
Write Timing:
Read Timing:
+"'f'____
"0-1. CS_ _J1~_ _ _ _ _ _ _
DATA BUS
Input Waveforms for A.C. Tests:
2.4---"""X
•
2,.28
_0
>
TEST POINTS
0.45 _ _ _..I
11·41
<::x___
6253/8253·5
Clock and Gate Timing:
8253
Note 1:
8253-5
MIN.
MAX.
MIN.
tCLK
Clock Period
380
de
380
tPWH
High Pulse Width
230
230
ns
tpwL
low Pulse Width
150
150
ns
tGW
Gate Width High
150
150
ns
tGL
Gate Width low
100
100
ns
tGS
Gate Set Up Time to CLKt
100
100
ns
tGH
Gate Hold Time After CLKt
50
50
too
Output Delay From CLK.J,[1]
400
400
ns
tDDG
Output Delay From Gate4- 11 ]
300
300
ns
SYMBOL
PARAMETER
Test Conditions: 8253: CL = 1 OOpF; 8253-5: CL = 150pF.
elK
11-42
..
MAX.
UNIT
de
ns
ns
8255A/8255A·5
PROGRAMMABLE PERIPHERAL INTERFACE
• MCS·85™ Compatible 8255A·5
• Direct Bit Set/Reset Capability Easing
Control Application Interface
• 24 Programmable I/O Pins
• Completely TTL Compatible
• 40·Pin Dual In· Line Package
• Fully Compatible with Intel® Micro·
processor Families
• Reduces System Package Count
• Improved Timing Characteristics
• Improved DC Driving Capability
The Intel® 8255A is a general purpose programmable 1/0 device designed for use with Intel® microprocessors. It has
241/0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first
mode (MODE 0), each group of 121/0 pins may be programmed in sets of 4 to be input or output. In MODE 1, the second
mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8
lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking.
PIN CONFIGURATION
8255A BLOCK DIAGRAM
...
PIN NAMES
~~-
'.---
CONTROl
lOGIC
'"~~--I
°7-0 0
RESET
DATA BUS (BI·DIRECTIONAl)
RESET INPUT
CHIP SELECT
RD
READ INPUT
WR
WRITE INPUT
AO.A1
PA7-PAO
PORT ADDRESS
PORT A (BIT)
P87·PBO
PORTB (BIT)
PC7-I'CO
PORT C (BIT)
Vee
GND
'VOLTS
+5 VOLTS
11-43
8255A18255A·5
8255A FUNCTIONAL DESCRIPTION
General
The 8255A is a programmable peripheral interface (PPI)
device designed for use in Intel® microcomputer
systems. Its function is that of a general purpose 110
component to interface peripheral equipment to the
microcomputer system bus. The functional configuration of the 8255A is programmed by the system software
so that normally no external logic is necessary to inter·
face peripheral devices or structures.
(RD)
Read. A "low" on this input pin enables the 8255A to
send the data or status information to the CPU on the
data bus. In essence, it allows the CPU to "read from"
the 8255A.
(WR)
Write. A "low" on this input pin enables the CPU to write
data or control words into the 8255A.
(Ao and A 1)
Port Select 0 and Port Select 1. These input signals, in
conjunction with the RD and WR inputs, control the
selection of one of the three ports or the control word
registers. They are normally connected to the least
significant bits of the address bus (Ao and A 1).
Data Bus Buffer
This 3-state bidirectional 8·bit buffer is used to interface
the 8255A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU~ Control words and status infor·
mation are also transferred through the data bus buffer.
8255A BASIC OPERATION
INPUT OPERATION (READ)
AO
RD
WR
CS
0
1
0
0
0
0
1
1
1
0
0
0
PORT A = DATA BUS
PORT B = DATA BUS
PORT C= DATA BUS
OUTPUT OPERATION
(WRITE)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
DATA
DATA
DATA
DATA
(CS)
X
X
X
X
1
Chip Select. A "low" on this input pin enables the communiction between the 8255A and the CPU.
1
1
0
1
0
DATA BUS = 3-STATE
ILLEGAL CONDITION
X
X
1
1
0
DATA BUS=3-STATE
Al
Read/Write and Control Logic
The function of this block is to manage all of the internal
and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Can·
trol busses and in turn, issues commands to both of the
Control Groups.
0
0
1
BUS=
BUS =
BUS =
BUS =
PORT A
PORT B
PORT C
CONTROL
DISABLE FUNCTION
Figure 1. 8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions
11-44
8255A18255A·5
(RESET)
Ports A, B, and C
Reset. A "high on this input clears the control register
and all ports (A, C, C) are set to the input mode.
The 8255A contains three 8-bit ports (A, B, and C). All
can be configured in a wide variety of functional characteristics by the system software but each has its own
special features or "personality" to further enhance the
power and flexibility of the 8255A.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255A_ The control word contains information such as "mode", "bit set", "bit reset",
etc., that initializes the functional configuration of the
8255.
Each of the Control blocks (Group A and Group 8) accepts
"commands" from the Read/Write Control Logic, receives
"control words" from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7-C4)
Control Group B - Port B and Port Clower (C3-CO)
Port A. One 8-bit data output latch/buffer and one 8-bit
data input latch.
Port B. One 8-bit data input/output latch/buffer and one
8-bit data input buffer.
Port C. One 8-bit data output latch/buffer and one 8-bit
data input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control.
Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signal inputs in
conjunction with ports A and B.
The Control Word Register can Only be written into. No
Read operation of the Control Word Register is allowed.
PIN CONFIGURATION
'A4
PA,
WR
RESET
1C=::::>.o:;.,..
0,
0,
0,
0,
0,
81.0UWCl'toIIfAi, DAfA 9IJS.
.,o,,<:::=~~
l1li---",
ft _ _ _...
PIN NAMES
:~
....,---ooj "='
° ,.°
1
....,----1
0
RESET INPUT
CHIP SELECT
READ INPUT
WRITE INPUT
PORT ADDAESS
PORT A (BIT)
PORT B (BITI
RD
WR
"'----.....
Figure 2. 8225A Block Diagram Showing Group A and
Group B Control Functions
11-45
DATe BUS (B)·DIRECTIONAL)
RESET
CS
AD,A'
PA7·PAD
PB7·PBO
PC7·PCO
PORT C (BIT)
Vee
GND
eVOLTS
+5 VOLTS
8255A18255A·5
8255A OPERATIONAL DESCRIPTION
CONTROL WORD
Mode Selection
There are three basic modes of operation that can be selected by the system software:
I
r
07 1 0, 05 1 04 1 03 1 0, 0,1
Dol
L,J
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-Directional Bus
/
When the reset input goes "high" all ports will be set to
the input mode (Le., all 24 lines will be in the high impedance state). After the reset is removed the 8255A can
remain in the input mode with no additional initialization
required. During the execution of the system program
any of the other modes may be selected using a single
output instruction. This allows a single 8255A to service
a variety of peripheral devices with a simple software
maintenance routine.
GROUP B
\
PORT C (LOWER)
L-..
1'" INPUT
0= OUTPUT
PORTS
1 = INPUT
0'" OUTPUT
MODE SELECTION
0= MODE 0
1 = MODE 1
llllt:.
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be "tailored" to almost any I/O
structure. For instance; Group B can be programmed in
Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1
to monitor a keyboard or tape reader on an interrupt-driven
basis.
/
GROUP A
PORT C (UPPER)
1 = INPUT
0= OUTPUT
PORTA
1 = INPUT
0= OUTPUT
MODE SELECTION
OO=MODEO
01 = MODE 1
1X = MODE 2
_I
MODE SET FLAG
1 = ACTIVE
1
ADDRESS BUS
CONTROL BUS
Figure 4_ Mode Definition Format
MOOED
The mode definitions and possible mode combinations
may seem confusing at first but after a cursory review of
the complete device operation a simple, logical 110 approach will surface. The design of the 8255A has taken
into account things such as efficient PC board layout,
control signal definition vs PC layout and complete
functional flexibility to support almost any peripheral
device with no external logic. Such design represents
the maximum use of the available pins.
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a
single OUTput instruction. This feature reduces software
requirements in Control-based applications.
Figure 3. Basic Mode Definitions and Bus Interface
11·46
8255A18255A·5
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports.
CONTROL WORD
Interrupt Control Functions
When the 8255A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt reo
quest signals, generated from port C, can be inhibited or
enabled by setting or resetting the associated INTE flipflop, using the bit set/reset function of port C.
BIT SET/RESET
1'" SET
0= RESET
BIT SELECT
01234567
"---1-0101010180
001100118,
-+_o 0
L - - - -_ _
This function allows the Programmer to disallow or allow a
specific I/O device to interrupt the CPU without affecting
any other device in the interrupt structure.
0 0 1111 B2
I NTE flip-flop definition:
BIT SET/RESET FLAG
0= ACTIVE
(BIT-SET) - INTE is SET - Interrupt enable
(BIT-RESET) - INTE is RESET - Interrupt disable
Note: All Mask flip-flops are automatically reset during
mode selection and device Reset.
Figure 5. Bit Set/Reset Format
Operating Modes
Mode 0 Basic Functional Definitions:
MODE 0 (Basic Input/Output). This functional configuration provides simple input and output operations for
each of the three ports. No "handshaking" is required,
data is simply written to or read from a specified port.
• Two 8-bit ports and two 4-bit ports.
• Any port can be input or output.
• Outputs are latched.
• I nputs are not latched.
• 16 different Input/Output configurations are possible
in this Mode.
.
tRR
~ r-
AD
C
IR
-;
~
I'--tHR -
-------
INPUT
t':==:=.t
---tRA------:1
AR - - -
CS. Al, AD
----------
<
tRD
1 I.
tDF
r---
.
MODE 0 (Basic Input)
'wW---~
~ .-
]
r--tow
tAW
~
'wD~
twA
-
Eli. A1. AO
~."d-
OUTPUT
MODE 0 (Basic Output)
11-47
8255A18255A·5
MODE 0 Port Definition
A
B
GROUP B
GROUPA
PORTC
PORTC
#
PORTB
0
1
2
3
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
4
5
OUTPUT
INPUT
INPUT
6
INPUT
OUTPUT
04
03
01
DO
PORTA
0
0
0
0
0
0
0
1
OUTPUT
OUTPUT
OUTPUT
OUTPUT
0
0
0
0
1
1
1
0
1
OUTPUT
OUTPUT
OUTPUT
OUTPUT
0
OUTPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
7
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
0
0
0
0
1
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
(UPPER)
(LOWER)
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
1
INPUT
OUTPUT
8
9
0
1
INPUT
OUTPUT
10
INPUT
OUTPUT
11
INPUT
INPUT
0
1
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
12
13
OUTPUT
INPUT
0
INPUT
INPUT
14
INPUT
OUTPUT
1
INPUT
INPUT
15
INPUT
INPUT
MODE 0 Configurations
CONTROL WORD #2
CONTROL WORD #0
0,
I
D.
D,
D,
D3
D,
D2
D,
Do
I I I0 I
1 0 0 0 0 0
I I I I
8
,
8255A
c{
D,
D2
D,
I II I I I I
4
8
8
A
,
8255A
PC7·PC4
c{
4
Pel-peO
8
pa,.pao
o
D,
Do
I
11
8
A
.
c{ .
a
D,
D.
D,
D3
D2
D,
•
)
/8
PA,'PAo
PC 7 ·PC 4
PC3 -PC O
PB"PBo
Do
I
1110101010101 1 11
,
8255A
7 -00 •
Do
CONTROL WORD #3
D3
1 0 0 0 0 0
°
D,
PA"PAo
CONTROL WORD #1
D,
D2
°7- 0 0
a
D,
D3
II
A
D,
D,
1,10101010101 1 0
o
°7-0 0 •
D,
D.
)
/'
8
8
A
PA,·pAo
PA"PAo
8255A
.
pe3 -peO
c{ .
pa,.PSo
S
PC7 ·PC4
°
7 ,00
11-48
•
4
I
/'
8
PC 7 -PC4
PC3 -Pe O
PB,'PSO
8255AJ8255A·5
CONTROL WORD #4
0,
I
D.
,
Os
0,
CONTROL WORD #8
03
,
0,
0,
0,
DO
0
0
0
Os
0,
o
0
0
/8
A
0,
03
0,
0
0
J
°7-0 0 •
,
Os
0,
0
0
c{
~-PC1-PC4
° -°
7
4
--7~
,
0,
0,
0,
,
8
,
0
0
0
0,
,
03
0,
0
0
4
PC7-PC4
4
8
,
0,
0,
PC3 -PCO
0
,I
0
0,
Os
0
0
0,
0,
0,
0
0
I, I I I, I I
I
B
B
0
0
03
,
0,
0,
I
/'
° -°
I, I
J/
0
'
PA,~PA,
PC7 -PC 4
PC3 -PC O
PS 7 -PSo
I
I
8
°7-°0--
4
PC 3-PC O
B
PS7 -PSo
/ B
,
c{
PC 7 -PC 4
,
0,
D.
Os
0
0
I, I I
I I I 1'1
0
8
0,
03
0,
I, I I
0
0
0,
.
/8
I
PA7 -PAO
PC 7 -PC4
PC 3 -pCO
P~-PBO
DO
I , I,
I
A
PA,.PA,
8
PA,.PA,
8255A
8255A
0
,
8
A
DO
A
7
IB
CONTROL WORD #11
0,
III I
0
PS 7 -PSo
Do
0,
PA7 "PAO
CONTROL WORD #7
,
I
8255A
c{ .
.
Os
PC 3 -PCO
o
B
0,
4
D.
PC 7 -PC 4
DO
P.,.PSo
DO
A
0,
0,
°7-0 0 ..
8255A
°7-0 0 ..
PA7 -PAc,
CONTROL WORD #10
°3
II I I I I I
0
Os
0
A
PA 7 -PAo
CONTROL WORD #6
0,
D.
8255A
c{
-
Os
B
I I I I I I I I, I
.
. c{ .
I I I, ]
0
0
B
0,
,
B
PS 7 ,PB O
8255A
0,
,
c{
0- -
PC 3 -PC O
DO
A
°7-0 0 ..
IB
J
CONTROL WORD #9
03
II I I I
0
0
A
CONTROL WOAD #5
D.
o
8255A
B
0,
DO
• PArPAo
8255A
.
0,
I, I I I ' I I I I I
I I I I I Io I I
0
c{
B
4
PC7-PC4
°7- 0 0
4
8
c{
PC3 -PC O
B
PS7 -PSO
11·49
4
4
8
PC7 -PC 4
PC3 -PCO
p.,.pe,
8255A18255A·5
CONTROL WORD #14
CONTROL WORD ""12
07
06
05
I, 1 0 1 0
'
A
8255A
.
.
c{
7
.
04
03
02
01
I, I, 1 I, 1
0
.
1
0
A
.
,.
7
8255A
.
"
7
•
B
CONTROL WORD #13
'
c{
0
B
DO
7
.
I
'
.
•
.
CONTROL WORD #15
A
.
,.
8255A
.
•
I
•
8255A
•
c{
B
A
7
..
,
.
c{
B
4
4
•
Mode 1 Basic Functional Definitions:
Operating Modes
•
•
MODE 1 (Strobed Inputlputput). This functional con·
figuration provides a means for transferring 1/0 data to
or from a specified port in conjunction with strobes or
"handshaking" signals. In mode 1, port A and Port B use
the lines on port C to generate or accept these "hand·
shaking" signals.
•
•
11·50
Two Groups (Group A and Group B)
Each group contains one a·bit data port and one 4·bit
control/data port.
The a·bit data port can be either input or output.
Both inputs and outputs are latched.
The 4·bit port is used for control and status of the
a·bit data port.
8255A18255A·5
Input Control Signal Definition
MODE 1 (PORT AI
STB (Strobe Input). A "low" on this input loads data into
the input latch.
CONTROL WORD
07 06 06 04 03 02 0, Do
IBF (Input Buffer Full F/F)
11 I 01 111 11IoNXN
A "high" on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgement
IBF is set by STB input being low and is reset by the rising
edge of the RDin put.
L~'I~PUT
0= OUTPUT
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the STB is a "one", IBF is a "one" and INTE is a "one".
It is reset by the falling edge of RD. This procedure allows
an input device to request service from the CPU by simply
strobing its data into the port.
MODE 1 (PORT B)
INTE A
Controlled by bit set/reset of PC 4.
INTE B
Controlled by bit set/reset of PC2.
Figure 6. MODE 1 Input
,- t s T - +-'
IBF
SlB
l
J
1
tSlT
'I
INTR
INPUT FROM PERIPHERAL
I--j
-
-
i
______.r·PH-~
-+__
•_ _ _ _ _ _ _ _ _ _
.~----
Figure 7. MODE 1 (Strobed Input)
11·51
~7
l-tRIB~l
JL
1
.J
8255A18255A·5
Output Control Signal Definition
MODE 1 (PORT Al
OBF (Output Buffer Full F/F). The OBF output will go
"low" to indicate that the CPU has written data out to
the specified port. The OBF F/F will be set by the rising
edge of the WR input and reset by ACK Input being low.
PA,·P"o
CONTROL WORD
ACK (Acknowledge Input). A "low" on this input informs
the 8255A that the data from port A or port B has been ac·
cepted. In essence, a response from the peripheral
device indicating that it has received the data output by
the CPU.
MODE 1 (PORT B)
INTR (Interrupt Request). A "high" on this output can be
used to interrupt the CPU when an output device has ac·
cepted data transmitted by the CPU. INTR is set when
ACK is a "one", OBF is a "one" and INTE is a "one". It is
reset by the falling edge of WR.
CONTROL WORD
INTEA
Controlled by bit set/reset of PC 6.
WR-
INTE B
Controlled by bit set/reset of PC 2 .
Figure 8. MODE 1 Output
\
\
INTR
~,~
_two}
I
~t'0=1
j1/)
~-J/
--tAK
OUTPUT
~-'wB
Figure 9. Mode 1 (Strobed Output)
11·52
--tAIT~
8
8255A18255A·5
Combinations of MODE 1
Port A and Port B can be individually defined as input or
output in Mode 1 to support a wide variety of strobed I/O
applications.
PArPAo
PC,
rnA
PC,
IBFA
PC,
INTRA
PC,
2
PC.,7
---f-- I/O
PC,
PC,
INTRa
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
Figure 10. Combinations of MODE 1
Operating Modes
Output Operations
MODE 2 (Strobed Bidirectional Bus 110). This functional
configuration provides a means for communicating with
a peripheral device or structure on a single 8·bit bus for
both transmitting and receiving data (bidirectional bus
110). "Handshaking" signals are provided to maintain
proper bus flow discipline in a similar manner to MODE
1. Interrupt generation and enable/disable functions are
also available.
OBF (Output Buffer Ful). The OBF output will go "low"
to indicate that the CPU has written data out to port A.
MODE 2 Basic Functional Definitions:
• Used in Group A only.
• One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C).
• Both inputs and outputs are latched.
• The 5-bit control port (Port C) is used for control
and status for the 8-bit, bi-directional bus port (Port
INTE 1 (The INTE Flip-Flop Associated with OBF)_ Controlled by bit set/reset of PCs.
A).
ACK (Acknowledge). A "low" on this input enables the
tri-state output buffer of port A to send out the data.
Otherwise, the output buffer will be in the high impedance state.
Input Operations
STB (Strobe Input)
STB (Strobe Input)_ A "low" on this input loads data into
the input latch.
Bidirectional Bus 110 Control Signal Definition
IBF (Input Buffer Full F/F). A "high" on this output indicates that data has been loaded into the input latch.
INTR (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
INTE 2 (The INTE Flip·Flop Associated with IBF). Controlled by bit set/reset of PC 4 •
11-53
8255A18255A·5
CONTROL WORD
-INTRA
PC 2.{l
1 = INPUT
o = OUTPUT
' - - - - - PORT B
1"" INPUT
0= OUTPUT
WR_
L-_ _ _ _ _ GROUP B MODE
0= MODE 0
, ""MODE 1
RD-
Figure 11. MODE Control Word
Figure 12. MODE 2
A
DATA FROM
CPU TO 8255A
WR
"\
OBF
INTR
~
I
______ t AOB
~I
1
I_two._~
/
\
\
"
~
------t AK -
r-./'
/
~tST-------"'"
II
sfB
\
tSl.~JI
IBF
PERIPHERAL
BUS
.
\
-tADI~
tpg~~-------
----------
~-
/
J
-ltpH
--
tl<$<1><1
OBF
GROUP A
i
___________ GROUP B
(DEFINED BY MODE 0 OR MODE 1 SELECTION)
Figure 16. MODE 2 Status Word Format
11-56
!
8255A/8255A·5
INTERRUPT
REQUE
APPLICATIONS OF THE 8255A
STi
PC,
The 8255A is a very powerful tool for interfacing
peripheral equipment to the microcomputer system. It
represents the optimum use of available pins and is flex·
ible enough to interface almost any I/O device without
the need for additional external logic.
8255A
MODEl
(INPUT)
Each peripheral device in a microcomputer system
usually has a "service routine" associated with it. The
routine manages the software interface between the
device and the CPU. The functional definition of the
8255A is programmed by the I/O service routine and
becomes an extension of the system software. By examining the I/O devices interface characteristics for
both data transfer and timing, and matching this information to the examples and tables in the detailed operational description, a control word can easily be developed to initialize the 8255A to exactly "fit" the application. Figures 17 through 23 present a few examples of
typical applications of the 8255A.
-
Ro
PA,
R,
PA 2
R2
PA,
R,
PA,
R,
PAs
PAs
R5
PA,
CONTROL
PC,
STROBE
PC,
ACK
Bo
PB,
B,
PB 2
B2
PB,
B,
PB,
B,
PB,
B,
MODE 1
INTERRUPT
REaUEST
FUllY
DECODED
KEYBOARD
SHIFT
PBo
(OUTPUT)
PC o
PAo
BURROUGHS
SELF-SCAN
DISPLAY
PBs
BACKSPACE
PB,
CLEAR
PC,
DATA READY
PC 2
ACK
PC,
BLANKING
--.f C7
CANCEL WORD
UPT~
PAc
PA,
INTERR
REQUEST
PA 2
HIGH-SPEED
PA,
PRINTER
PA,
Figure 18. Keyboard and Display Interface
PA,
MODE 1
(OUTPUT)
PAs
PA,
INTERRUPT
REQU
HAMMER
ESTi
RELAYS
PC,
PC,
PC,
PC,
PC,
8255A
~~~~T;
PB o
PB,
PB 2
PB,
8255A
PB,
MODEl
(OUTPUT)
-
PAo
Ro
PA,
R,
PA 2
R2
PA,
R,
PA,
R,
FULLY
DECODED
KEYBOARD
PAs
R,
PAs
SHIFT
PA,
CONTROL
PC,
STROBE
PB,
PBs
PB,
PC,
PC 2
ACK
PC,
ACKNOWLEDGE
PC,
BUSY IT
PC,
TEST LT
------PB o
PCo
CONTROL LOGIC AND DRIVERS
PB,
INTERRUPT
REQUEST
PB 2
Figure 17. Printer Interface
MODE 0
PB,
(INPUT)
PB,
PB,
PBs
PB,
- "'0- "'0- -- ' 0 - -- "'0- ..--- ' 0 -
--
.---
TERMINAL
ADDRESS
-
~
---U-
--'b'--
Figure 19. Keyboard and Terminal Address Interface
11-57
8255A18255A·5
.:-J
INTERRUPT
REQUE
r--
ST
LSB
PC,
PAD
PA,
PA,
PA,
PA,
PA,
PA.
MODE 0
PA5
,,=~> I'~
PA,
PC.
--
12-BIT
D-A
CONVERTER
(DAC)
-
MODE 2
ANALOG OUTPUT
.
.
PC.
MSB
PC,
l~
STS DATA
BIT
SET/RESET
PC,
SAMPLE EN
PC,
STB
PB.
LSB
PB,
PB,
~~~~T~
PB,
-
--
D.
PA,
0,
PAs
0,
PA,
0,
PC.
DATA STB
A-D
CONVERTER
(ADC)
-
ANALOG INPUT
MODE 0
(OUTPUT)
PB,
PBS
MSB
Figure 20. Digital to Analog, Analog to Digital
INTERRUPT
REQU
EST
I
PC,
ACK (IN)
PC,
DATA READY
PC.
ACK (OUT)
PC,
TRACK "0" SENSOR
PC.
SYNC READY
PC,
INDEX
r
FORWARD/REV.
PB,
READ ENABLE
PB3
WRITE ENABLE
PB4
DISC SELECT
PB,
ENABLE CRe
PBs
TEST
PB,
BUSY IT
Figure 22. Basic Floppy Disc Interface
INTERRUPT
RECUES
TJ
PC,
PAD
(OUTPUT)
-
CRT CONTROLLER
PA,
PA,
R,
• CHARACTER GEN.
PA2 •
R,
PA,
R,
• REFRESH BUFFER
PA,
R,
PA.
R.
• CURSOR CONTROL
PA.
R.
PA,
R,
R,
MODE 1
SHIFT
(INPUT)
PAD
R.
R,
PAs
R,
PA,
R,
8 lEVEL
PAPER
TAPE
READER
PA,
CONTROL
PC,
DATA READY
ACK
PC.
PC5
STB
PC.
PC,
BLANKED
PC,
STOP/GO
PC.
BLACK/WHITE
ACK
8255A
MACHINE TOOL
START/STOP
PC,
ROWSTB
PC,
COLUMN STB
PC.
CURSOR H/V STS
PB.
a
MODE
(OUTPUT)
--
R.
R,
- PAS
8255A
PC,
PA,
PA,
MODE 1
I
AND DRIVE
ENGAGE HEAD
8·BIT
PB.
PB,
FLOPPY DISK
CONTROLLER
0,
PA.
8255A
OUTPUT EN
PC,
0,
PA,
PC,
8255A
D.
0,
MODE 0 f C
PC.
(INPUT)
LIMIT SENSOR (HNi
,
PC,
OUT OF FLUID
1-
PB,
PB,
CURSOR/ROW/COLUMN
PB,
PB.
H&V
CHANGE TOOL
PB ,
LEFT/RIGHT
PB,
UP/DOWN
a
PB,
HOR. STEP STROBE
(OUTPUT)
PB.
VERT. STEP STROBE
MODE
- ADDRESS
PB.
PB,
PB,
SLEW/STEP
PBs
PBs
FLUID ENABLE
PB,
PB,
-
Figure 21. Basic CRT Controller Interface
r--------'
EMERGENCY STOP
Figure 23. Machine Tool Controller Interface
11-58
8255A18255A·5
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for ex tended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias . . . . . . . . . oOe to 70°C
Storage Temperature . . . . . . . . . . . . . . _65°e to +150o e
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS
TA = o°c to 70°C. Vee = +5V ±5%; GND = OV
PARAMETER
SYMBOL
MIN.
Vil
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
TEST CONDITIONS
MAX. UNIT
0.8
V
Vee
V
VOL (DB) Output Low Voltage (Data Bus)
0.45
V
IOl = 2.5mA
VOdPER) Output Low Voltage (Peripheral Port)
0.45
V
IOl = 1.7mA
V
IOH = -4001lA
VOH(DB)
Output High Voltage (Data Bus)
2.4
VOH(PER) Output High Voltage (Peripheral Port)
120
rnA
Input Load Current
±10
IlA
VIN = Vcc to OV
Output Float Leakage
±10
IlA
VOUT = Vec to OV
III
IOFl
IOH = -2001lA
Power Supply Current
Icc
-1.0
V
mA
Darlington Drive Current
Note 1:
2.4
-4.0
IDAR[l]
R EXT = 750D; VEXT= 1.5V
Available on any 8 pins from Port Band C.
CAPACITANCE
TA = 25°C; Vee = GND = OV
SYMBOL
MAX.
UNIT
CIN
Input Capacitance
PARAMETER
MIN.
TYP.
10
pF
fc = lMHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to G N D
___ ~
TEST CONDITIONS
~:O~'
L:~~:_J---I~=vY--V
I
VEXT*
100pF
·VEXT is set at various voltages during testing to guarantee the specification.
Figure 24. Test Load Circuit (for dB)
11·59
8255A/8255A·5
A.C. CHARACTERISTICS
TA
= o°c to 70°C; VCC = +5V ±5%; GND = OV
Bus Parameters
Read:
Write:
Other Timings:
I
Notes: 1. Test Conditions: 8255A: CL = 1 OOpF; 8255A-5: CL = 150pF.
2. Period of Reset pulse must be at least 50-"s during or after power on.
Subsequent Reset pulse can be 500 ns min.
11-60
8255A18255A·5
Figure 25. Input Waveforms for A.C. Tests
...
.
~r
RD
.
-,
r--
~
-'HR-I
tIR - - -
INPUT
r--'AR-
~tRA--:-1
CS.A1.AO
- - - - - - - - - -r(
'Ro
'OF
.
---
Figure 26. MODE 0 (Basic Input)
'wW
.) l-
r--'ow
J I'w~
twA
'AW
-
C8.A1.AO
OUTPUT
'wB---J
Figure 27. MODE 0 (Basic Output)
11-61
8255A18255A·5
,
"
~tST------+
1
1
Sl8
-'
IOF
'f
J
tSIT
INTR
-----
\
1__ 'Rlo_I'
)
~7
J
v
/
/
~'PH--:I
INPUT FROM
PERIPHERAL
---
.
---------------------
..•
...
Figure 28. MODE 1 (Strobed Inut)
,
\
\
INTR
I
~.wo}
~'WIT)
OUTPUT
~~o
Figure 29. MODE 1 (Strobed Output)
11-62
tAOS
~/)
L/
'-..d-..,,~
8255A18255A·5
INTR
ISF
PERI:~iRAL
_-_-___
- __
-_
- _ - __
-_
-_-_....,'-_ _ _ _ _ _ _
-_"'-tP_H:...._....._ _
~~;;:~~~~~~:_...... -
-
-=t:,~
DATA FROM
PERIPHERAL TO 8255
DATA FROM
8255 TO 8080
Figure 30. MODE 2 (Bidirectional)
NOTE:
Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(lNTR = IBF • MASK' STB • RD + OBF • MASK· ACK • WR )
11·63
• Internal CRC Generation and Checking
Step Rate, Settle-Time, Head
• Programmable
Load Time, Head Unload Index Count
• IBM 3740 Soft Sectored Format Compatible
• Programmable Record Lengths
• Multi-Sector Capability
Maintain Dual Drives with Minimum Software
• Overhead
Expandable to 4 Drives
• Fully MCS-80 and MCS-85 Compatible
• Single + 5V Supply
Automatic Read/Write Head POSitioning and
• Verification
• 40-Pln Package
The Intel~ 8271 Programmable Floppy Disk Controller (FOC) Is an LSI component designed to interface one to 4 floppy
disk drives to an B-blt microcomputer system. Its powerful control functions minimize both hardware and software
overhead normally associated with floppy disk controllers.
BLOCK DIAGRAM
PIN CONFIGURATION
FAULT RESETIOPO
Vee
SELECT 0
LOW CURRENT
4 MHzCLK
LOAD HEAD
ReSET
DIRECTION
READY 1
SEEK/STEP
SELECT 1
WR ENBLE
DACK
INDEX
ORO
WA PROTECT
iii5
READY 0
WR
TRKO
INT
COUNT/OPI
OBO
WR DATA
OBI
FAULT
OB2
UNSEPDATA
OB3
DATA WINDOW
DB.
PlOtSS
OBS
CS
OB6
INSVNC
OB7
A,
GNO
"0
:r
SELECT 1,0
FAULT RUETfOPO
.....
"Q
OAT" BUS lal DIRECTIONAL.
CLOCIC INPUT ITTLI
SlLECT1.0
FAULT RElnlOPTlONAL OUTPUT
RUET
...
."
IImIV'I.•
~~;:NC
l!r
""'"
L..-c=~_____
ORO
DlllAREOUEST
CI'UREo\OlNPUT
PlO/SS
OACK
'NT
iW
ViR
DRIVE
INTERFACE
CONTROLLER
SELECT 0
SELECT 1
WR ENABLE
LOAD HEAD
SEEK/STEP
DIRECTION
LOWCURAENT
FAULT RESETIOPO
RESET
UNSEPAAATEDOATA
FAuLT
CS - - - - - - '
......
WAIlATA
IIl"D'I' 1,0
lIMA ACKMOWLEDCE
WR DATA
'NSVNC
- - - - DATA WINDOW
w.mnoom;;
UNSEPDATA
1-----_
~--------- ~
PIN NAMES
Dao
SERIAL
INTERFACE
CONTROLLER
~
INTERNAL
DATA SUS
WRPROTfCT
;;mr
CPU WRITE tNPUT
WRENABLE
lEEIC/STI;'
WRITEENASLE
REGI'TERSELleT
READ DATA INIVMC
DIAECnQN
DIRECTION
LOAOHEAO
LOWCUJlRIiNT
HEKISTEI'
CPU INTERFACE
11-64
DISK INTERFACE
8271
8271 BASIC FUNCTIONAL DESCRIPTION
General
The 8271 Floppy Disk Controller (FOC) interfaces either
two single or one dual floppy drive to an eight bit
microprocessor and is fully compatible with Intel's
new high performance MCS-85 microcomputer system.
With minimum external circuitry, this innovative controller
supports most standard, commonly-available flexible disk
drives including the mini-floppy.
Pin
Name
A,-A.
Pin
No.
122-21) I
ORO
(8)
0
(6)
(2)
0
These lines are used to specify the
selected drive. These lines are set
by the command byte.
Fault Reset! (1)
OPO
a
The optional fault reset output line
Is used to reset an error condition
which is latched by the drive. If
this line is not used for a fault
reset it can be used as an optional
output line. This line is set with
the write special register command.
Write Enable (35)
a
This signal enables the drive write
logic.
Seek/Step
(36)
0
This multi-function line is used during drive seeks.
Direction
(37)
0
The direction line specifies the
seek direction. A high level on
this pin steps the R/W head
toward the spindle (step-in), a
low level steps the head away
from the spindle (step-out).
Load Head
(38)
a
The load head line causes the
drive to load the Read/Write head
against the diskette.
Low Current
(39)
0
This line notifies the drive that track
43 or greater is selected.
Ready 1,
Ready 0
(5)
(32)
These two lines indicate that the
specified drive is ready.
Fault
(28)
This line is used by the drive to
specify a file unsafe condition.
Count/OPI
(30)
If the optional seek/direction/
count seek mode is selected, the
count pin receives pulses to step
the R1W head to the desired track.
Otherwise, this line can be used
as an optional Input.
Write Protect (33)
The Write signal is used to signal
the control logic that a transfer of
data from the data bus to the 8271
is required.
This signal specifies that the
diskette inserted is write protected.
TRKO
(31)
This signal indicates when the RIW
head is pOSitioned over track zero.
The Read signal is used to signal
the control logic that a transfer of
data from the 8271 to the data bus
is required.
Index
(34)
The index signal gives an indication
of the relative position of the diskette.
PLO/SS
(25)
This pin is used to specify the type
of data separator used. PhaseLocked Oscillator/Single Shot.
Write Data
(29)
In addition to the standard read/write commands, a scan
command is supported. The scan command allows the
user program to specify a data pattern and instructs the
FOC to search for that pattern on a track. Any application
that is required to search the disk for information (such as
point of sale price lookup, disk directory search, etc.>, may
use the scan command to reduce the CPU overhead. Once
the scan operation is initiated, no CPU intervention is
required.
Hardware Description
Select 1Select 0
The 8271 is packaged in a 40 pin DIP. The following is a
functional description of each pin.
Pin
Name
Vee
Pin
No.
(40)
Clock
(20)
(3)
Reset
(4)
GND
I/O
Description
+5V supply
Ground
A square wave clock
A high signal on the reset input
forces the 8271 to an idle state.
The 8271 remains idle until a command is issued by the CPU. The
output signals of the drive interface are forced inactive (LOW).
Reset must be active for 10 or
more clock cycles.
(24)
The I/O Read and 1/0 Write inputs
are enabled by the chip select signal.
DBTDBo (19-12) 1/0 The Data Bus lines are bidirectional, three-state lines (8080 data
bus compatible).
WR
RD
INT
(10)
(9)
(11)
0
ia ., .
The DMA acknowledge signal
notifies the 8271 that a DMA cycle
has been granted. For non-DMA
transfers, this signal should be
driven in the manner of a "Chip
Select".
(7)
The 8271 FOC supports a comprehensive soft sectored
format which is IBM 3740 compatible and includes
provision for the designating and handling of bad tracks. It
is a high level controller that relieves the CPU (and user) of
many of the control tasks associated with implementing a
floppy disk interface. The FOC supports a variety of high
level instructions which allow the user to store and retrieve
data on a floppy disk without dealing with the low level
details of disk operation.
These two lines areCPM:
face Register select lines:»"> ':"
The DMA request signal is used"
request a transfer of data between
the 8271 and memory.
The interrupt signal indicates that
the 8271 requires service.
11-65
a
CompoSite write data.
.'i~.
8271
Pin
Name
Pin
No.
I/O
Description
Unseparated (27)
Data
This input is the unseparated data
and clocks.
Data Window (26)
This is a data window established
by a single-shot or phase-locked
oscillator data separator.
Result R e g i s t e r . " " . , ..... "•..... f'."'Pl- (....
The Result Register is used to supply"t~ out~o~PG
command execution (such as a good/badccirnplet'l~lQ. ~
the CPU. The standard Result byte format is! ". '. '.. t<"
1 1 I
I0 I
l'rrL~~m".
COMPLETION CODe
INSYNC
(23)
0
This line is high when 8271 has
attained input data synchronization. by detecting 2 bytes of
zeros followed by an expected
Address Mark. It will stay high
until the end of the 10 or data
field.
COMPLETION TYPE
DELETED DATA FOUND
L-_ _ _ _ _ _ _ _ _ NOT USED =00
CPU Interface Description
This interface minimizes CPU involvement by supporting
a set of high level commands and both OMA and non-OMA
type data transfers and by providing hierarchical status
information regarding the result of command execution.
The CPU utilizes the control interface (see the Block
diagram) to specify the FOC commands and to determine
the result of an executed command. This interface is
supported by five Registers which are addressed by the
CPU via the At, Ao, RO and WR signals. lfan 8080 based
system is used, the RO and WR signals can be driven by
the 8228's i70R and iiOW signals. The registers are
defined as follows:
Command Register
The CPU loads an appropriate command into the
Command Register which has the following format:
Figure 1. 8271 Block Diagram Showing CPU
Interface Functions
Status Register
Reflects the state of the FOC.
A,
I0
A.()
I0 I
07
06 05 04 03
1
I
02 0,
Do
1
I
0
10 I
I I I I I0 I0 I
IIII
~----- COMMAND OPCOOE
SURFACE!DRIVE
.
(SELECT 0, 1 J
'"_~M"""~
1 = INTERRUPT REQUEST
, .. RESULT REGISTER FULL
1'" PARAMETER REGISTER FULL
~--------1"
Parameter Register
COMMAND REGISTER FULL
' - - - - - - - - - - - 1 = COMMAND BUSY
Accepts parameters of commands that require further
description; up to five parameters may be required,
example:
Reset Register
Allows the 8271 to be reset by the program. Reset must
be active for 11 or more chip clocks .
•NT (Interrupt Line)
I 0 I, 1 I 1
Another element of the control interface is the Interrupt
line (tNT). This line is used to signal the CPU that an FDC
operation has been completed. It remains active until the
result register is read.
1 1
~------
EXPECTED PARAMETER
11·66
8271
DMA Operation
The 8271 can transfer data in either DMA or non DMA
mode. The data transfer rate of a floppy disk drive is high
enough (one byte every 32 usec) to justify DMA transfer.
In DMA mode the elements of the DMA interface are:
ORO: DMA Request:
The DMA request signal is used to request a transfer of
data between the 8271 and memory.
DACK: DMA Acknowledge:
The DMA acknowledge signal notifies the 8271 that a DMA
cycle has been granted.
Disk D~"lnl.~.C.r~!4:<,
The 8271 disk drive interface supj:Yorts ,~e
command structure described in the Comr,riahl;l
tion section. The 8271 maintains the location'of 9}iil1r
and the current track location for two drives.H6we(ler,
with minor software support, this interface can suPPorf"
four drives by expanding the two drive select lines (select
0, select 1) with the addition of minimal support hardware.
The FOC Disk Drive Interface has the following major
functions.
READ FUNCTIONS
RD, WR: Read, Write
The read and write signals are used to specify the
direction of the data transfer.
Utilize the user supplied data window to obtain the clock
and data patterns from the unseparated read data.
DMA transfers require the use of a DMA controller such as
the Intel®8257. The function of the DMA controller is to
provide sequential addresses and timing for the transfer
at a starting address determined by the CPU. Counting of
data block lengths is performed by the FOC.
Compute and verify the 10 and data field CRCs.
To request a OMA transfer, the FOC raises ORQ. OACK
and RD enable OMA data onto the bus (independently of
CHIP SELECT). OACK and WR transfer DMA data to the
FOC. If a data transfer request (read or write) is not
serviced within 31 f.Lsec, the command is cancelled, a late
OMA status is set, and an interrupt is generated. In OMA
mode, an interrupt is generated at the completion of the
data block transfer.
Establish byte synchronization.
WRITE FUNCTIONS
Encode composite write data.
Compute the 10 and data field GRCs and append them to
their respective fields.
CONTROL FUNCTIONS
Generate the programmed step rate, head load time, head
settling time, head unload delay, and monitor drive
functions.
When configured to transfer data in non-DMA mode, the
CPU must pass data to the FOC in response to the nonDMA data requests indicated by the status word. The
data is passed to and from the chip by asserting the
DACK and the RD or WR signals. Chip select should be
inactive (HIGH).
DATA
SEPARATOR
1----
DATA WINDOW
UNSEPARATED DATA
...
~
~
:....
.......
8271
WRITE DATA
WRITE ENABLE
SEEK/STEP
DIRECTION
CDUNT/OPI
LOAD HEAD
INDEX
TRACK 0
FDC
DRIVE
....
:.
SELECT 0
~
...
LOW CURRENT
SELECTl
WR ITE PROTECT
WRITE FAUCT
.....
WRITE FAULT RESET/OPO
AEADYO
READY 1
NOTE:
Figure 2_ 8271 Block Diagram Showing Disk Interface
Functions
INPUTS TO CHIP MAY REQUIRE RECEIVERS
(AT LEAST PULL UP/DOWN PAIRS).
Figure 3_ 8271 Disk Drive Interface
11-67
DUAL
FLOPPY
DISK
I
8271
,
:(;4;;A;~ c)~l:~,
Data Separation
Insync Pin
The 8271 needs only a data window to separate the data
from the composite read data as well as to detect missing
clocks in the Address Marks.
This pin gives an indication of wheHre~ tt\~!J
synchronized with the serial data stream'duri~g'
operations. This pin can be used with a ptl!iseclb.ck
oscillator for soft and hard locking.
"
The window generation logic may be implemented using
either a single-shot separator or a phase-locked oscillator.
Single-Shot Separator
FOUND SYNC & 10 MARK
READ 10 FielD BUT
The single-shot separator approach is the lowest cost
solution.
The FOe samples the value of Data Window on the leading
edge of Unseparated Data and determines whether the
delay from the previous pulse was a half or full bit-cell
(high input = full bit-cell, low input = half bit-ceID.
PlO/SS should be tied to Ground.
FOUND SYNC & 10 MARK
10 FIELD CORRECT
TRACK OR SECTOR
INCORRECT
IN SYNC
/
\
/
/
FOUND SYNC & DATA MARK
NOT AN 10 MARK
FOUND SYNC & DATA MARK
READ DATA SECTOR
Figure 4. Insync Waveform
DATA WINDOW
UNSEPARATED
DATA
RETRIGGERABLE
SINGLE·SHOT
2.851'5 WINDOW*
8271 FOG
I
}LO/SS
*FOR MINI-FLOPPY DATA WINDOW = 5.7l'sec
Figure 5. Slngle·Shot Data Separator Block Diagram
UNSEPARATEO
DATA
tos;;; lOOns
I
Figure 6. Slngle·Shot Data Window Timing
11·68
8271
Phase-Locked Oscillator Separator
.•
The FDC samples the value of Data Window on the leading
edge of Unseparated Data and determines whether the
pulse represents a Clock or Data Pulse.
',f';r(
Insync may be used to provide s~t~dy,p.
control for the phase-locked oscillator. . j •
PLO/SS should be tied to Vee (+5Vl.
- - - - - - - DATA WINDOW
UNSEPARATED --1---t.~('
DATA
__
PLO
r
I
I
8271 FOe
-"':-lI"'p-L-O-/S"S
I
L _____________________ l
IN SYNC*
+5V
*OPTIONAL
F;igure 7_ PLO Data Separator Block Diagram
UNSEPARATED
DATA
*DATA WINDOW MAY BE 1800 OUT OF PHASE IN PLO DATA SEPARATION MODE.
Figure 8. PLO Data Window Timing
Disk Drive Control Interface
Write Enable
The disk drive control interface performs the high level
and programmable flexible disk drive operations. It
custom tailors many varied drive performance parameters
such as the step rate, settling time, head load time, and
head unload index count. The following is the description
of the control interface.
The Write Enable controls the read and write functions of a
flexible disk drive. When Write Enable is a logical one, it
enables the drive write electronics to pass current through
the Read/Write head. When Write Enable is a logical zero,
the drive Write circuitry is disabled and the Read/Write
head detects the magnetic flux transitions recorded on a
diskette. The write current turn-on is as follows.
WRITEDAT~
--I
WRITE ENABLE
I
____
I-tWE
Figura 9_ Write Enable Timing
11-69
~
8271
"
The Direction pin is a control (~:Th '~
in which the RIW head is stepped, A'io~~e' ,I,Q
line moves the head toward the spindljHsf~
low level moves the head away from the spiMtue
Seek Control
Seek Control is accomplished by SeekiStep, Direction,
and Count pins and can be implemented two ways to
provide maximum flexibility in the subsystem design, One
instance is when the programmed step rate is not equal to
zero, In this case, the 8271 uses the Seek/Step and
Direction pins (the Seek/Step pin becomes a Step pinJ.
Programmable Step timing parameters are shown,
Another instance is when the programmable step rate is
equal to zero, in which case the 8271 holds the seek line
high until the appropriate number of user-supplied step
pulses have been counted on the count input pin,
DIRECTION
SEEK/STEP
~
~."
n
~
I---tos
--l
~tps
tps=tos =tso =lOllS
STANDARD: 1ms.;;ts.;;255ms
MINI· FLOPPY: 2ms';; ts';; 510ms
Figure 10. Seek Timing
DIREcnD~
SEEK/STEP
I
I
---J
...
-
COUNT
--
.....~.....
LAST COUNT
tos =tso =tcs =lOlls
tsc ;;'llls
tpC;;.201lS
tc;;'lms
Figure 11. Seek/Step/Count Timing
11-70
8271
Head Seek Settling Time
if
The 8271 allows the head settling time to be programmed
from 0 to 255ms, in increments of 1ms.
i'
The head settling time is defined as the interval of time
from completion of the last step to the time when reading
or writing on the diskette is possible (R/W Enable). The
R/W head is assumed loaded.
r
SEEK OR LAST STEP
LAST STEP COMPLETE
I~
r____--'1---.,~
WRITE/READ ENABLE
STANDARD: 0';;;*tsw';;;255ms
*R/W HEAD IS ASSUMED LOADED.
MINI· FLOPPY: 0 ,;;;*tsw';; 510ms
Figure 12. Head Load Settling Timing
Load Head
When active, load head output pin causes the drive's
read/write head to be loaded on the diskette. When the
head is initially loaded, there is a programmed delay (Q to
60ms in 4ms increments) prior to any read or write
operation. Provision is also made to unload the head
following an operation within a programmed number of
diskette revolutions.
LOAD HEAD
,..------- ------------""
tLw-1
r
I
EARLIEST WRITE ENABLE
OR INTERNAL READ DATA
STANDARD: 0,;;; tLW';;; 60ms
MINI·FLOPPY: 0,;;; tLW';;; 120ms
Figure 13. Head Load to Read/Write Timing
11·71
8271
Index
The Index input is used to determine "Sector not found"
status and to initiate format track/read 10 commands and
head unload Index and Count operations.
Figure 14. Index Timing
Track 0
This input pin indicates that the diskette is at track O.
During any seek operation, the stepping out of the
actuator ceases when the track 0 pin becomes active.
Select 1, 0
Only one drive may be selected at a time. The
Input/Output pins that must be externally qualified with
Select 0 and Select 1 are:
Unseparated Data
Data Window
Write Enable
Seek/Step
Count/Optional Input
Load Head
Track 0
Low Current
Write Protect
Write Fault
Fault Reset/Optional Output
Index
I
When a new set of select bits is specified by a new command or the FDC finishes the index count before head
unload, the following pins will be set to the 0 state:
Write Enable (35)
Seek/Step (36)
Direction (37)
Load Head (38)
Low Head Current (39)
The select pins will be set to the state specified by the
command or both are set to zero following the index
count before head unload.
Low Current
This output pin is active whenever the physical track
location of the selected drive is greater than 43. Generally
this signal is used to enable compensation for the lower
velocities encountered while recording on the inner
tracks.
Write Protect
The 8271 will not write to a disk when this input pin is
active and will interrupt the CPU if a Write attempt is made.
Operations which check Write Protect are aborted if the
Write Protect line is active.
This signal normally originates from a sensor which
detects the presence or absence of the Write Protect
hole in the diskette jacket.
Write Fault and Write Fault Reset
The Write Fault input is normally latched by the drive
and indicates any condition which could endanger data
integrity. The 8271 interrupts the CPU anytime Write
Fault is detected during an operation and immediately
resets the Write Enable, Seek/Step, Direction, and Low
Current signals. The write fault condition can be cleared
by using the write fault reset pin.'1f the drive being used
does not support write fault, then this pin should be
connected to Vee through a pull-up resistor.
Ready 1, 0
These two pins indicate the functional status of the disk
drives. Whenever an operation is attempted on a drive
which is not ready, an interrupt is generated. The interface continually monitors this input during an operation
and if a Not Ready condition occurs, immediately terminates the operation. Note that the 8271 latches the
Not Ready condition and it can only be reset by the execution of a Read Drive Status command. For drives that
do not support a ready signal, either one can be derived
with a one shot and the index pulse, or the ready inputs
can be grounded and Ready determined through some
software means.
11-72
8271
PRINCIPLES OF OPERATION
The Command Phase
As an 8080 peripheral device, the 8271 accepts commands
from the CPU, executes them and provides a RESULT
back to the 8080 CPU at the end of command execution.
The communication with the CPU is established by the
activation of CS and RD or WR. The Al, Ao inputs select
the appropriate registers on the chip:
The software writes a command to the comman'dt~tar.
As a function of the command issued, from zero to 1fve"'
parameters are written to the parameter register,' Ref.er t6 "
diagram showing a flow chart of the comman1 phase.
Note that the flow chart shows that a command may not be
issued if the FDC status register indicates that the device
is busy. Issuing a command while another command is in
progress is illegal. The flow chart also shows a parameter
buffer full check, The FDC status indicates the state of the
parameter buffer. If a parameter is issued while the
parameter buffer is full, the previous parameter is over
written and lost.
DACK
1
1
1
1
1
a
a
0
CS
0
a
a
a
a
1
1
a
A1
0
a
a
0
1
x
x
x
Ao
RD
WR
Operation
0
0
1
0
1
0
Read Status
Write Command
Read Result
Write Parameter
Write Reset Reg.
Write Data
Read Data
Not Allowed
a
1
1
a
X
X
x
1
1
1
0
x
1
0
a
a
1
X
START
The FDC operation is composed of the foilowing
sequence of events.
STANDARD
RESULT
RETURNED
NO
?
YES
8080 WRITES THE COMMAND AND PARAMETERS INTO
THE 8271 COMMAND AND PARAMETER REGISTERS.
IMMEDIATE
RESULT
RETURNED
?
THE 8271 IS ON ITS OWN TO CARRY OUT THE COMMANDS.
THE 8271 SIGNALS THE CPU THAT THE EXECUTION HAS
FINISHED. THE CPU MUST PERFORM A READ OPERATION
OF ONE OR MORE OF THE REGISTERS TO DETERMINE
THE OUTCOME OF lHE OPERATION.
COMMAND
BUSY BIT SET
NOTE:
NO
STANDARD RESULT RETURNED CAN BE
DETERMINED BY MASKING OUT THE
DRIVE SELECT BITS OF THE COMMAND
BYTE (BITS 7 AND 6) AND CHf'CKING
FOR A VALUE OF LESS; THAN 2Ci6 (IF
tESS THAN 2C16, STANDARD RESULT
IS RETURNED).
->1
IMMEDIATE RESULT RETURNED CAN
BE DETERMINED BY ADDITIONALLY
MASKING OUT BITS 5 AND 4 OF THE
COMMAND BYTE AND CHECKING FOR
A VALUE OF C16 Of!. GREATER (IF Ci6
OR GREATER, IMMEDIATE RESULT
RETURNED).
(MORE)
PARAMETERS
REQUIRED
?
I
Figure 16. Checking for Result Type Following 8271
Command and Parameters
The Execution Phase
PARAMETER
FULL BIT SET
During the execution phase the operation specified
during the command phase is performed. During this
phase, there is no CPU involvement if the system utilizes
DMA for the data transfers. The execution phase of each
command is discussed within the detailed command
descriptions. The following table summarizes many ofthe
basic execution phase characteristics.
Figure 15. Passing the Command and Parameters to the
8271
11-i"3
8271
EXECUTION PHASE BASIC CHARACTERISTICS
The following table summarizes the various commands
with corresponding execution phase characteristics.
3
4
5
6
7
Head
Ready
Writel
Protect
Seek
Seek
Check
Result
2
COMMANDS
Deleted
Data
Completion
Interrupt
SCAN DATA
SKIP
LOAD
j
x
YES
YES
YES
YES
SCAN DATA AND
DEL DATA
WRITE DATA
XFER
LOAD
j
x
YES
YES
YES
YES
x
LOAD
j
j
YES
YES
YES
YES
WRITE DEL DATA
x
LOAD
j
j
YES
YES
YES
YES
READ DATA
SKIP
LOAD
j
x
YES
YES
YES
YES
READ DATA AND
DEL DATA
XFER
LOAD
j
x
YES
YES
YES
YES
x
LOAD
YES
NO
YES
YES
LOAD
j
j
x
XFER
x
YES
YES
YES
YES
READ 10
VERIFY DATA AND
DEL DATA
FORMAT TRACK
x
LOAD
j
j
YES
NO
YES
YES
SEEK
x
LOAD
Y
x
YES
NO
YES
YES
READ DRIVE STATUS
SPECIFY
x
x
x
NO
NOTE 5
NO
NO
NO
NO
NO
NO
RESET
UNLOAD
x
NO
NO
NO
NO
R SP REGISTERS
x
x
x
x
x
x
x
NO
NO
NOTE 6
NO
W SP REGISTERS
x
x
x
NO
NO
NO
NO
x
Note: 1. "x" ~ DON'T CARE 2. "j" -
check 3. "-" -
No change 4. "y" ~ Check at end of operation 5. See "READ DRIVE STATUS" command.
S. See "READ SPECIAL REGISTER" command.
Table 1. Execution Phase Basic Characteristics
Explanation of the execution phase characteristics table.
4. Write Protect
1. Deleted Data Processing
The operations that are marked check Write Protect are
immediately aborted if Write Protect line is active at the
beginning of an operation.
If deleted data is encountered during an operation that
is marked skip in the table, the deleted data record is
not transferred into memory, butthe record is counted.
For example, if the command and parameters specify a
read of five records and one of the records was written
with a deleted data mark, four records are transferred
to memory. The deleted data flag is set in the result
byte. However, if the operation is marked transfer, all
data is transferred to memory regardless of the type of
data mark.
5. Seek
Many of the 8271 commands cause a seek to the
desired track. A current track register is maintained for
each drive or surface.
6. Seek Check
Operations that perform Seek Check verify that
selected data in the 10 field is correct before the 8271
accesses the data field.
2. Head
The Head column in the table specifies whether the
Read/Write head will be loaded or not. If the table
,specifies load, the head is loaded after it is positioned
over the track. The head loaded by a command remains
loaded until the user specified number of index pulses
have occurred.
3. Ready
The Ready column indicates if the ready line (Ready
1, Ready 0) associated with the selected drive is
checked. A not ready state is latched by the 8271 until the user executes a read status command.
11-74
8271
C
POLLED INTERRUPT
CPU INTERRUPT
)
START
--1
(
START
~-I
!f
Bit 4: Result Full
)
'I
This bit indicates the state of the result buffer"ltis valid
only after Command Busy bit is low. This bit is set when
the FDC finishes a command and is reset after the result'
byte is read by the CPU. The data in the result buffer is
valid only after the FDC has completed a command.
Reading the result buffer while a command is in progress
yields no useful information.
Bit 3: Interrupt Request
This bit reflects the state of the FDC INT pin. It is set
when FDC requests attention as a result of the completion of an operation or failure to complele an intended
operation. This bit is cleared by reading the result
register.
c
Bit 2: Non-DMA Data Request
)
END
When the FDC is utilized without a DMA controlier, this bit
is used to indicate FDC data requests. Note that in the
non-DMA mode, an interrupt is generated (interrupt
request bit is set) with each data byte written to or read
from the diskette.
Figure 17. Getting the Result
The Result Phase
Bits 1 and 0:
During the Result Phase, the FDC notifies the CPU of the
outcome of the command execution. This phase may be
initiated by:
1. The successful completion of an operation.
2. An error detected during an operation.
Not used (zero returned).
After reading the Status Register, the CPU then reads the
Result Register for more information.
THE RESULT REGISTER
This byte format facilitates the use of an address table
to look up error routines and messages. The standard
result byte format is:
PROGRAMMING
07
Al
Ao
CS RD
0
0
1
1
0
1
0
1
Status Reg
Result Reg
-
CS
WR
Os
I 0 I0
Command Re g
Parameter Re g
Reset Reg
-
Ds
t
04
03
02
D1
Do
I0 I
!
[UT_L
.
NOTUSED"O
COMPLETION CODE
- - - - - COMPLETION TYPE
- - - - DELETED DATA FOUND
STATUS REGISTER
L...._ _ _ _ _ _ _ _ _ _ _ NOT USED
FDC Status
0
00
Bits 7 and 6:
Not used (zero returned).
COMMAND BUSY
COMMAND REG FULL
PARAMETER REG FULL -
Bit 5:
Deleted Data Found: This bit is set when deleted data is
encountered during a transaction.
Bit 7: Command Busy
Bits 4 and 3: Completion Type
The command busy bit is set on writing to the command
register. Whenever the FDC is busy processing a
command, the command busy bit is set to a one. This bit is
set to zero after the command is completed.
The completion type field provides general information
regarding the outcome of an operation.
The completion type field provides general information
regarding the outcome of an operation.
Bit 6: Command Full
Completion
Type
The command full bit is set on writing to the command
buffer and cleared when the FDC begins processing the
command.
Bit 5: Parameter Full
00
01
10
This bit indicates the state of the parameter buffer. This bit
is set when a parameter is written to the FDC and reset
after the FDC has accepted the parameter.
11
11-75
Event
Good Completion - No Error
System Error - recoverable errors;
operator intervention probably required
for recovery.
Command/Drive Error - either a program
error or drive hardware failure.
I'
!!
i
Ii
I
8271
Bits 2 and 1: Completion Code
The completion code field provides more detailed
information about the completion type (See Table).
Completion
Completion
Type
Code
Event
00
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Good Completionl
Scan Not Met
Scan Met Equal
Scan Met Not Equal
Clock Error
Late DMA
10 CRC Error
Data CRC Error
Drive Not Ready
Write Protect
Track 0 Not Found
Write Fault
Sector Not Found
It is important to note the hllf,
result byte. In very simple systems
GO result is required. the user may si
zero result (a zero result is a good completl
level of complexity is at the completion type int
completion type supplies enough information so th'ap,tJ:j.~.,
software may distinguish between fatal and non-fat"tl
errors. If a completion type 01 occurs. ten retries should
be performed before the error is considered unrecoverable.
The Completion TypelCompletion Code interface supplies the greatest detail about each type of completion.
This interface is used when detailed information about the
transaction completion is required.
Bit 0:
Not used (zero returned).
interpretation
Definition
Successful Completion/
Scan Not Met
The diskette operation specified was completed without error. If scan operation
was specified, the pattern scanned was not found on the track addressed.
Scan Met Equal
The data pattern specified with the scan command was found on the track
addressed with the specified comparison, and the equality was met.
Scan Met Not Equal
The data pattern specified with the scan command was found with the
specified comparison on the track addressed, but the equality was not met.
Clock Error
During a diskette read operation, a clock bit was missing (dropped). Note that this
function is disabled when reading any of the ID address marks (which contain
missing clock pulses). If this error occurs, the operation is terminated immediately and an interrupt is generated.
Late DMA
During either a diskette read or write operation, the data channel did not respond
within the allotted time interval to prevent data from being overwritten or lost. This
error immediately terminates the operation and generates an interrupt.
ID Field CRC Error
The CRC word Itwo bytes) derived from the data read in an ID field did not match
the CRC word written in the ID field when the track was formatted. If this error
occurs, the associated diskette operation is prevented and no data is transferred.
Data Field CRC Error
During a diskette read operation, the CRC word derived from the data field read
did not match the data field CRC word previously written. If this error occurs, the
data read from the sector should be considered invalid.
Drive Not Ready
The drive addressed was not ready. This ,"dication is caused by any of the
following conditions:
1. Drive not powered up
2. Diskette not loaded
3. Non-existent drive addressed
4. Drive went not ready during an operation
Note that this completion code is cleared only through an FDG read drive
status command.
Write Protect
A diskette write operation was specified on a write protected diskette. The
intended write operation is prevented and no data is written on the diskette.
Track 00 Not Found
During a seek to track 00 operation, the drive failed to provide a track 00
indication after being stepped 255 times.
Write Fault
This error is dependent on the drive supported and indicates that the fault Input to
the FDG has been activated by the drive.
Sector Not Found
Either the sector addressed could not be found within one complete revolution of
the diskette Itwo index marks encountered) or the track address specified did not
match the track address contained in the ID field. Note that when the track
address specified and the track address read do not match, the FDG automatically
increments its track address register Istepping the drive to the next trackl and
again compares the track addresses. If the track addresses still do not match, the
track address register is incremented a second time and another comparison is
made before the sector not found completion code is set,
Table 2. Completion Code Interpretation
11-76
8271
Load Bad Tracks
INITIALIZATION
Reset Command
CMO:
::::.1 : I I I I I I I I I ' I
0
0
0
0
0
0
0
PAR;
0
PAR:
Function: The Reset command emulates the action of
the reset pin. It is issued by outputting a one followed
by a zero to the Reset register.
1.
2.
3.
4.
The drive control signals are forced low.
An in-progress command is aborted.
The FOC status register flags are cleared.
The FOC enters an idle state until the next command is
issued.
Reset must be active for 10 or more clock cycles.
Many of the interface characteristics of the FOC are
specified by the systems software. Prior to initiating any
drive operation command, the software must execute
the three specify commands. There are two types of
specify commands selectable by the first parameter
issued.
First Parameter
Specify Type
OOH
10H
.18H
Initialization
Load bad Tracks Surface '0'
Load bad Tracks Surface '1'
The Specify command is used prior to performing any
diskette operation (including formatting of a diskette) to
define the drive's inherent operating characteristics and
also is used following a formatting operation or
installation of another diskette to define the locations of
bad tracks. Since the Specify command only loads
internal registers within the 8271 and does not involve an
actual diskette operation, command processing is limited
to only Command Phase. Note that once the operating
characteristics and bad tracks have been specified for
a given drive and diskette, redefining these values need
only be done if a diskette with unique bad tracks is to be
used or if the system is powered down.
Initialization:
DO
0
PAR
0
0
,
,
PAR
0
PAR :
0
,
PAR :
0
1
o
o
I
I
~~--+-----------------------4
BAD TRACK NO. 2
____________________
~
CURRENT
TRACK
PAR: L-~__~
Parameter 0: 10H = Load Su~face zero bad tracks
18H = Load Surface one bad track
Parameter· 1:
Bad track address number 1 (Physical Address).
It is recommended to program both bad tracks and current track to FFH during initialization.
SPECIFY COMMAND
CMD :
PAR.
~~--+--+--+--+--+--+--+-~~~~
1--_t-_t-_..L_..L_..L_..L_..L_..L_-.1..:oe,,:..~
0
0
I ' I ' I
0
I ' I
I Io I ' I' I
0
o
o
I'
I'
STEP RATE'"'
HEAD SETTLING TIME'""
INDEX CNT BEFORE
HEAD UNLOAD*
I
HEAD LOAD TIME*
SEEK COMMAND
The seek command moves the head to the specified track
without loading the head or verifying the track.
The seek operation uses the specified bad tracks to
compute the physical track address. This feature insures
that the seek operation positions the head over the correct
track.
When a seek to track zero is specified, the FOC steps
the head until the track 00 signal is detected.
If the track 00 signal is not detected within (FF)H steps, a
track 0 not found error status is returned.
A seek to track zero is used to position the read/write head
when the current head position is unknown (such as after
a power up>.
Seek operations are not verified. A subsequent read or
write operation must be performed to determine if the
correct track is located.
READ DRIVE STATUS COMMAND
This command is used to interrogate the drive status.
Upon completion the result register wi" hold the final
drive status.
"Note: Mini-floppy parameters are doubled.
Parameter 0 - OOH = Select Specify Initialization.
Parameter 1 - 07-00 = Step Rate (0-255ms in 1ms steps).
Parameter 2 - 07-00 = Head Settling Time (0-255ms in 1
ms stees). {O - 510ms in 2ms steps} () = standard,
{}= mini
Parameter 3 - 07-04 = Index Count - Specifies the
number of Revolutions (0-14) which are to occur before
the FOC automatically unloads the R/W head. If 15 is
specified, the head remains loaded.
03-00 = Head Load Time (0-60ms in steps of 4ms).
{0-120ms in 8ms steps} () = standard, U= mini
CMO:
A1
Ao
0
0
07
06
Os
I I IS~L I I,
SgL
04
0
03
02
I ' I,
0,
0
Do
I I
0
IF A DRIVE NOT READY RESULT IS RETURNED. THE READ STATUS MUST
BE ISSUED TO CLEAR THE CONDITION.
"Note the two ready bits are zero latching. Therefore, to clear the drive
not ready condition. assuming the drive is ready, and to detect it via software, one must issue this command twice.
11-77
8271
NON·DMA
, -_ _ _-'Y"'ES'-':::
(
J
START
SI~~LE
ACTUATOR?
SET NON·DMA
ANDIOR
SINGLE ACTUATOR
NO
POWER·UP
ALL DRIVES
seEK TO
TRACK 0
ON DRIVE 0
RESET
seEK TO
TRACK 0
ON DRIVE 1
INTERFACE
RESET
FoC
SPECIFY
DRIVE
CHARACTERISTICS
SPECIFY
BAD TRACKS
DRIVE 0
YES
SPECIFY
BAD TRACKS
DRIVE 1
NO
Figure 18. Initialization of the 8271 by the User
Mode Register Write Parameter Format
ReadlWrite Special Registers
This command is used to access special registers within
the 8271.
'" 0 DMA MODE, = 1 NON DMA
Do
00 DOUBLE, 0 1 SINGLE ACTUATOR
CMD:
Bits 6 & 7
PAR:
Must be one.
Command code:
3DH Read Special Register
3AH Write Special Register
Bits 5-2
For both commands, the first parameter is the register
address; for Write commands a second parameter
specifies data to be written. Only the Read Special
Register command supplies a result.
I
Register Address
in Hex
Comment
Scan Sector Number
06
See Scan Description
Description
Scan MSB of Count
14
See Scan Description
Scan LSB of Count
13
See Scan Description
Surface 0 Current Track
12
Surface 1 Current Track
1A
Mode Register
17
See Mode Register
Description
Drive Control Output Port
23
See Drive Output
Port Description
Drive Control Input Port
22
See Drive Input
Port Description
Surface 0 Bad Track 1
10
Surface 0 Bad Track 2
11
Surface 1 Bad Track 1
18
Surface 1 Bad Track 2
19
(Not used), Must be set to zero.
-Bit 1
Double/Single Actuator: Selects Single or double actuator
mode. If the single actuator mode is selected, the FOG
assumes that the physical track location of both disks is
always the same. This mode facilitates control of a drive
which has a Single actuator mechanism to move two
heads.
-Bit 0
Data Transfer Mode: This bit selects the data transfer
mode. If this bit is a zero, the FDC operates in the DMA
mode (DMA RequestiACKl. If this bit is a one, the FDC
operates in non-DMA mode. When the FDC is operating in
DMA mode, interrupts are generated at the completion of
commands. If the non-DMA mode is selected, the FDC
generates an interrupt for every data byte transferred.
Table 3. Special Registers
• Bits 0 and 1 are initialized to zero.
11·78
8271
Non·DMA Transfers in DMA Mode
Track Format
If the user desires, he may retain the use of interrupts
generated upon command completions. This mode is
accomplished by selecting the DMA capability, but
using the DMA REQ/ACK pins as effective INT and CS
signals, respectively.
Each Diskette Surface is divided into 77 tracks with each
track divided into fixed length sectors. A sector can hold a
whole record or a part of a record. If the record is shorter
than the sector length, the unused bytes are filled with
binary zeros. If a record is longer than the sector length,
the record is written over as many sectors as its length
requires. The sector size that provides the most efficient
use of diskette space can be chosen depending upon the
record length required.
Tracks are numbered from 00 (outer-most' to 76 (innermost) and are used as follows:
TRACK 00 reserved as System Label Track
TRACKS 01 through 74 used for data
TRACKS 75 and 76 used as alternates.
Drive Control Input Port
Reading this port will give the CPU exactly the data that
the FDC sees at the corresponding pins. Reading this
port will update the drive not ready status, but will not
clear the status. (See Read Drive Status Command for
Bit locations.)
Each sector consists of an ID field (which holds a unique
address for the sector) and a data field.
Drive Control Output Port Format
I
I
I
I I
I
I
I
I
L=
WRITE ENABLE
SEEK/STEP
DIRECTION
LOAD HEAD
LOW HEAD CURRENT
WRITE FAULT RESET /
OPTIONAL OUTPUT
SELECT 0
SELECT 1
Each of these signals correspond to the chip pin of the
same name. On standard·sized drives with write fault
detection logic, bit 5 is set to generate the write fault
reset signal. This signal is used to clear a write fault
indication within the drive. On mini·sized drives, this bit
can be used to turn on or off the drive motor prior to initio
ating a drive operation. A time delay after turn on may be
necessary for the drive to come up to speed. The regis·
ter must be read prior to writing the register in order to
save the states of the remaining bits. When the register
is subsequently written to modify bit 5, the remaining
bits must be restored to thei r previous states.
IBM DISKETTE GENERAL FORMAT
INFORMATION
The IBM Flexible Diskette used for data storage and
retrieval is organized into concentric circular paths or
TRACKS. There are 77 tracks on either One or both sides
(surfaces) of the diskette. On double-sided diskettes, the
corresponding top and bottom tracks are referred to as a
CYLINDER. Each track is further divided into fixed length
sections or SECTORS. The number of sectors pertrack26,15 or 8 - is determined when a track is formatted and is
dependent on the sector length - 128, 256 or 512 bytes
respectively - specified.
All tracks on the diskette are referenced to a physical
index mark (a small hole in the diskette). Each time the
hole passes a photodetector cell (one revolution of the
diskette), an Index pulse is generated to indicate the
logical beginning of a track. This index pulse is used to
initiate a track formatting operation.
The ID field is seven bytes long and is written for each
sector when the track is formatted. Each ID field consists
of an IDfield Address Mark, a Cylinder Number byte which
identifies the track number, a Head Number byte which
specifies the head used (top or bottom) to access the
sector, a Record Number byte identifying the sector
number (1 through 26 for 128 byte sectors), an N-byte
specifying the byte length of the sector and two CRC
(Cyclic Redundancy Check) bytes.
The Gaps separating the index mark and the ID and data
fields are written on a track when it is formatted. These
gaps provide both an interval for switching the drive electronics from reading or writing and compensation for rotational speed and other diskette-to-diskette and drive-todrive manufacturing tolerances to ensure that data written
on a diskette by one system can be read by another
(diskette interchangeability>.
IBM Format Implementation Summary
Track Format
The disk has 77 tracks, numbered physically from 00 to 76,
with track 00 being the outermost track. There are
logically 75 data tracks and two alternate tracks. Any two
tracks may be initialized as bad tracks. The data tracks are
numbered logically in sequence from 00 to 74, skipping
over bad tracks (alternate tracks replace bad tracks).
Note: In IBM format track 00 cannot be a bad track.
Sector Format
Each track is divided into 26,15, or 8 sectors of 128, 256,
or 512 bytes length respectively. The first sector is
numbered 01, and is physically the first sector after the
physical index mark. The logical sequence of the
remaining sectors may be nonsequential physically. The
location of these is determined at initialization by CPU
software.
Each sector consists of an I D field and a data field. All
fields are separated by gaps. The beginning of each field
is indicated by 6 bytes of (OOlH followed by a one byte
address mark.
Address Marks
Address Marks are unique bit patterns one byte in length
which are used to identify the beginning of ID and Data
fields. Address Mark bytes are unique from all other data
11-79
8271
Index
II
G.p
Last Sector
Sector 03
Sector 02
Sector 01
I
G.p
10 Field
Data Field
A
A
128, 256, or 512 Bytes
AM2: Data: hex FB or F8
F8 '" data field
F8 = contra I field
(The control field can
begin with a 0 or an F:
0'" deleted rElcord
F '" defective record
0)
Clock: hex C7J
CD
Post-index gap.
0)
6 bytes of zeroes
o
Hex 00 for 128 byte per sector for mat
Hex 01 for 256 byte per sector format
Hex 02 for 512 byte per sector for mat
Cyclic redundancy check.
The check bytes are
generated during a write
operation. They are used
Hex 01 through lA for 128 byte per sector format diskette
Hex 01 through OF for 256 byte per sector format diskette
Hex 01 through 08 for 512 byte per sector format diskotte
during a read operation
to verify that data is
read correctly.
®
Hex 00 for one-sided diskettes and side 0 of two-sided diskettes
Hex 01 for side 1 of two-sided diskettes
L
Pre-index gap.
o
Hex 00 through 4A (Decimal 1 through 74. Cylinders 75 and 76
are used as a Iternate cylinder s.l
Post· 10 gap.
Post-data gap.
AM1: identifies Infield
Data: hex FE
Clock: hex C7
Figure 19. Track Format
bytes in that certain bit cells do not contain a clock bit (all
other data bytes have clock bits in every bit cell.) There are
four different types of Address Marks used. Each of these
is used to identify different types of fields.
10 Field
Index Address Mark
ID Address Mark
C
Cylinder (Track) Address, 00-74
H = Head Address
R = Record (Sector) Address, 01-26
N = Record (Sector) Length, 00-02
Note: Sector Length = 128 x 2N bytes
CRC = 16 Bit CRC Character (See Below)
The 10 Address Mark byte is located at the beginning of
each 10 field on the diskette.
Data Field
The Index Address Mark is located at the beginning of
each track and is a fixed number of bytes in front of the
first record.
MARK
Data Address Mark
The Data Address Mark byte is located at the beginning of
each non-deleted Data Field on the diskette.
Deleted Data Address Mark
The Deleted Data Address Mark byte is located at the
beginning of each deleted Data Field on the diskette.
Address Mark Summary
Index Address Mark
10 Address Mark
Data Address Mark
Deleted Data Address Mark
Bad Track 10 Address Mark
Clock
Pattern
Data
Pattern
07
C7
C7
C7
C7
FC
FE
FB
F8
FE
MARK
C
I
H
R
N
DATA
CRC
CRC
CRC
CRC
Data is 128, 256, or 512 bytes long.
Note:
All marks, data, ID characters and CRC
characters are recorded and read most
significant bit first.
CRC Character
The 16-bit CRC character is generated using the
gener.ator polynominal X16 + X12 + X5 + 1, normally
initialized to (FF)H. It is generated from all characters
(except the CRC in the 10 or data field), including the data
(not the clocks) in the address mark. It is recorded and
read most significant bit first.
11-80
8271
Data is written (general case) in the following manner:
MISSING
CLOCK
CLOCK
DATA "0"
CLOCK
DATA "1"
CLOCK
DATA "1"
DATA "1"
Mini·Floppy Disk Format
TF=FUlL BIT TIME= NOMINALLY 4,..a*
TH
iheForf!1af'if!ln~d specify
record length, the bits are coded the same'~')!:a$ jn the
Read Data commands.
. .'. ". ··"·F'· ..
2 . The programmable gap sizes (gap 3, gap 5,ahd gap 1f rtl'u.st:
be programmed such that the 6 bytes of zero (s~oo)aresub)
tracted from the intended gap size i.e., if gap 1 is irrlendE!d
to be 16 bytes long, programmed length must be 16 - 6 ~'10
bytes (of FF H'S).
1. The parameter 2 (0 7 - 0 5) of
Data Format
=HALF BIT TIME= NOMINALLY 2,...*
The mini-floppy disk format differs from the standard
disk format in the following ways:
Figure 20. Data Format
References
"The IBM Diskette for Standard Data Interchange," IBM
Document GA21-9182-0. "System 32," Chapter 8, IBM
Document GA21-9176-0.
1. Gap 5 and the Index Address mark have been eliminated.
2. There are fewer sectors/tracks.
GAPS
Bad Track Format
The following is the gap size and description summary:
The Bad Track Format is the same as the good track
format except that the bad track 10 field is initialized as
follows:
C
Gap
Gap
Gap
Gap
Gap
= H = R = N = (FFiH
When formatting, bad track registers should be set to
FFH for the drive during the formatting, thus specifying
no bad tracks. Thus, all tracks are left available for formatting.
Upon completion of the format the bad tracks should be
set up using the write special register command. The
8271 will then generate an extra step pulse to cross the
bad track, locating a new track that now happens to be
an extra track out.
This gap separates the index adGap 1:
dress mark of the index pulse from
N bytes FF's
6 bytes a's for sync the first 10 mark. It is used to protect the first ID field from a write on
the last physical sector of the current track.
Format Track
Format Command
0
PAR:
0
PAR:
0
PAR:
0
PAR:
0
PAR:
0
0
,
,
,
,
,
S~l
I S~l I
1
!
o
I
0
I I ' I,
This gap separates the ID field from
Gap 2:
the data mark and field such that
11 bytes FF's
6 bytes a's for sync during a write only the data field
will be changed even if the write
gate turns on early, due to drive
speed changes.
0
TRACK ADDRESS
GAP 3 SIZE MINUS 6
RECORD LENGTH
1
Programmable
17 Bytes
Programmable
Variable
Programmable
The last six bytes of gaps 1.2,3 and 5 are 1001H, all other
bytes in the gaps are (FFIH. The Gap 1,3 and 5 count
specified by the user are the number of bytes of IFFIH. Gap
4 is written until the leading edge of the index pulse. If a
Gap 5 size of zero is specified, the Index Mark is not
written.
The track following the bad track(s) should be one
higher in number than track before the bad track(s).
CMO:
1
2
3
4
5
NO. OF SECTORS/TRACK
GAP5SIZEMINUS6
This gap separates a data area from
Gap 3:
the next ID field. It is used so that
N bytes FF's
6 bytes a's for sync during drive speed changes the
next ID mark will not be overwritten,
thus causing loss of data.
GAP 1 SIZE MINUS 6
The format command can be used to initialize a disk track
compatible with the IBM 3740 format. A Shugart "IBM
Type" mini-floppy format may also be gef1llrated.
Gap 4:
FF's only
The Format command can be used to initialize a diskette, one track at a time. When format command is used,
the program must supply 10 fields for each sector on the
track. During command execution, the supplied 10 fields
(track head sector addresses and the sector length) are
written sequentially on the diskette. The 10 address
marks originate from the 8271 and are written automatically as the first byte of each 10 field. The CRC character is written in the last two bytes of the 10 field and is
derived from the data written in the first five bytes. During the formatting operation, the data field of each sector is filled with data pattern (E5)H' The CRC, derived
from the data pattern is also appended to the last byte.
This gap fills out the rest of the disk
and is used for slack during formatting. During drive speed variations
this gap will shrink or grow if the
disk is re-formatted.
This gap separates the last sector
Gap 5:
from the Index Address mark and
N bytes FF's
6 bytes a's for sync is used to assure that the index address mark is not destroyed by
writing on the last physical data
sector on the track.
The number of FF bytes is programmable for gaps 1, 3
and 5.
11-81
8271
INDEX
GATA
FIELD
INDEX ADDRESS MARK
GAPS
GAP 1:
POST INDEX GAP
"I
I"
SYNC
GAP 2:
I
POST ID FIELD GAP
I"
"I
SYNC
I
' - - - - - - WRITE GATE TURN-ON FOR UPDATE OF NEXT
DATA FIELD.
NOTE: THE WRITE GATE TURN-ON SHOULD BE TIMED
TO WITHIN ± '" 1 BIT BY COUNTING THE BYTES
IN THE GAP UNTlll BYTE BEFORE THE
TURN-ON.
GAP 3:
POST DATA FIELD GAP
I"
L
WRITE GATE TURN-OFF FROM UPDATE OF PREVIOUS DATA FIELD.
NOTE:
IBM FORMAT REQUiRES AT LEAST 2 BINARY "1" BITS AS A DATA FIELD POSTAMBLE.
2-BITS
GAP 4:
FINAL GAP
I"
GAP 5:
~I
INITIAL GAP
"I
I"
SYNC
Figure 21. Track Format
11·82
I
8271
n
PHYSICAL
________
INDEX
~
~M~A~RK~
__________________________________________________________________________________
HEX FF
I (~::~) I
40 BYTES
6 BYTES
11 BYTES
6 BYTES
(TYPICAL)
NUMBER OF BYTES
NUMBER
OF SECTORS
26
15
8
4
2
1
GAP 1
GAP 3
GAP 2
ID FIELD
'ONES
SYNC
26
26
26
26
26
26
6
6
6
6
6
6
GAP 5
DATA FIELD
ONES
SYNC
11
11
11
11
11
11
6
6
6
6
6
6
7
7
7
7
7
7
131
259
515
1027
2051
4099
'ONES
SYNC
27
48
90
224
255
0
6
6
6
6
6
0
GAP 4
'ONES
SYNC
40
40
40
40
40
40
6
6
6
6
6
6
275
129
146
236
719
1007
'Program Specified
5208 Bytes Per Track
Figure 22. Standard Diskette Track Format
n
PHYSICAL
INDEX
MARK
SECTOR 2
DATA FIELD
HEX FF
I (:::;0) I
11 BYTES
6 BYTES
HEX FF
I (:::~) I
6 BYTES
NUMBER OF BYTES
NUMBER
OF SECTORS
18
10
5
2
1
GAP 1
GAP 3
GAP 2
SYNC
16
16
16
16
16
6
6
6
6
6
7
7
7
7
7
GAP 4
DATA FIELD
ID FIELD
'ONES
ONES
SYNC
11
11
11
11
11
6
6
6
6
6
'Program Specified
131
259
515
1027
2051
'ONES
SYNC
11
21
74
255
0
6
6
6
6
0
24
30
88
740
1028
3125 Bytes Per Track
Figure 23. Mini·Diskette Track Format
11·83
8271
C
_____S_TTAR_T_ _....J)
NO
!~~{ ' - - - - - r - - - - '
Te STOP
DMA ENABLE BITS
~---r-----'
}
~~~O
LOAD AND
DMA ENABLE BITS
Figure 23. User DMA Channel Initialization Flowchart
Read ID Command
CMD:
0
0
si ! S~L I
PAR:
0
1
TRACK ADDR ESS
PAR:
0
1
PAR:
0
1
l
o
I
0
I
0
0
I
1
I
1
I
0
I
1
I
1
I
0
I
o
I
0
I
o
I
0
NUMBER OF 10 FIELDS
The Read ID command transfers the specified number of
I D fields into memory (beginning with the first ID field after
I ndex), The CRC character is checked but not transferred.
These fields are entered into memory in the order in
which they are physically located on the disk, with the
first field being the one starting at the index pulse.
Full power of the multisector read/write commands can be
realized by doing DMA transfer using Intel® 8257 DMA
Controller, For example, in a 128 byte per sector
multisector write command, the entire data block
(containing 128 bytes times the number of sectors) can be
located in a disk memory buffer. Upon completion of the
command phase, the 8271 begins execution by accessing
the desired track, verifying the ID field, and locating the
data field of the first record to be written. The 8271 then
DMA-accesses the first sector and starts counting and
writing one byte at a time until all 128 bytes are written. It
then locates the data field of the next sector and repeats
the procedure until all the specified sectors have been
written. Upon com pletion of the execution phase the 8271
enters into the result phase and interrupts the CPU for
availability of status and completion results. Note that all
read/write commands, single or multisector are executed
without CPU intervention.
Data Processing Commands
All the routine Read/Write commands examine specific
drive status lines before beginning execution, perform
an implicit seek to the track address and load the drive's
read/write head. Regardless of the type of command
(Le., read, write or verify), the 8271 first reads the ID
field(s) to verify that the correct track has been located
(see sector not found completion code) and also to
locate the addressed sector. When a transfer is complete (or cannot be completed), the 8271 sets the interrupt request bit in the status register and provides an indication of the outcome of the operation in the result
register.
Note, execution of multi-sector operations are faster if
the sectors are not interleaved.
128 Byte Single Record Format
! S~L I
CMD:
0
0
sil
PAR:
0
1
TRACK ADDR 0·255
COMMAND DPCODE
PAR:
0
1
SECTOR 0255
Commands
If a CRC error is detected during a multisector transfer,
processing is terminated with the sector in error. The
address of the failing sector number can be determined by
examining the Scan Sector Number register using the
Read Special Register command.
READ DATA
READ DATA AND DELETED DATA
WRITE DATA
WRiTE DELETED DATA
VERIFY DATA AND DELETED DATA
11-84
Opcode
12
16
OA
OE
1E
8271
':.
;'
y' ;.:'
":.:'
Scan Commands
Variable Length/Multi-Record Format
D,
CMD,
0
PAR,
0
PAR,
0
PAR,
0
0
,
,
,
siL
I S~L I
DO
CDMMAND OPCODE
0
TRACK ADDR 0·255
PAR.
0
SECTOR 0·255
PAR.
0
PAR
0
PAR
0
,
,
,
PAR,
0
,
LENGTH
I
NO. OF SECTORS
07-05 of Parameter 2 determine the length of the disk
record.
000
o0 1
010
011
1 0 0
o1
1 0
1 1 1
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
8192 Bytes
16,384 Bytes
Commands
READ DATA
READ DATA AND DELETED DATA
WRITE DATA
WRITE DELETED DATA
VERIFY DATA AND DELETED DATA
SCAN DATA
SCAN DATA AND DELETED DATA
Command
0
,
S;L
"
/
D4
D5
D6
CMD,
,
"\,
"Ol
I S~L I J o 1
0
0
'02
:'.:
""
'Pl'"
lSOAT~
o
SDElO
'Oa
lli
TRACK AODR 0 255
SECTOR
a 255
LENGTH
SCAN TYPE
I
I
NO OF SECTORS
STEP SIZE
FIELD LENGTH (KEY)
O2 = 0
O2 = 1
Scan Data
Scan Data and Deleted Data
. Scan Commands, Scan Data and Scan Data and Deleted
Data, are used to search a specific data pattern or "key"
from memory. The 8271 FDC operation during a scan is
unique in that data is read from memory and from the
diskette simultaneously.
Opcode
13
17
OB
OF
1F
00
04
Read Commands
Read Data, Read Data and Deleted Data.
Function
The read command transfers data from a specified disk
record or group of records to memory. The operation of
this command is outlined in execution phase table.
Write Commands
Write Data, Write Deleted Data.
Function
The write command transfers data from memory to a
specified disk record or group of records.
Verify Command
Verify Data and Deleted Data.
Function
The verify command is identical to the read data and
deleted data command except that the data is not
transferred to memory. This command is used to check
that a record or a group of records has been written
correctly by verifying the CRe character.
During the scan operation, the key is compared
repetitively (using the 8257 DMA Controlier in auto load
mode) with the data read from the diskette (e.g., an eight
byte key would be compared with the first eight bytes (1-8)
read from the diskette, the second eight bytes (9-16), the
third eight bytes (17-24), etc.). The scan operation is
concluded when the key is located or when the specified
number of sectors have been searched without locating
the key. When concluded, the 8271 FOe requests an
interrupt. The program must then read the result register
to determine if the scan was successful (if the key was
located). If successful, several of the FOe's special
registers can be examined (read special registers
command) to determine more specific information
relating to the scan (I.e., the sector number in which the
key was located, and the number of bytes within the sector
that were not compared when the key was located),
The 8271 does not do a sliding scan, it does a fixed
block linear search. This means the key in memory is
compared to an equal length block in a sector; when
these blocks meet the scan conditions the scan will
stop. Otherwise, the scan continues until all the sectors
specified have been searched.
The following factors regarding key length must be
considered when establishing a key in memory.
1. When searching multiple sectors, the length of the key
must be evenly divisible into the sector length to
prevent the key from being split at subsequent sector
boundaries. Since the character FFH is not compared,
the key in memory can be padded to the required length
using this character. For example, if the actual pattern
compared on the diskette is twelve characters in length,
the field length should be sixteen and four bytes of FFH
11-85
8271
would be appended. to the key. Consequently, the last
block of sixteen bytes compared within the first sector would end at the sector boundary and the first
byte of the next sector would be compared with the
first byte 01 the key. Splitting data over sector boundarys will not work properly since the FDC expects the
start of key at each sector boundary.
2. Since the first byte of the key is compared with the first
byte of the sector. when the pattern does not begin with
the first byte of the sector, the key must be offset using
the character FF16. For example, if the first byte of a
nine byte pattern begins on the fifth byte of the sector,
four bytes of FF16 are prefixed to the key (and three
bytes of FF16 are appended to the key to meet the
length requirement) so that the first actual comparison
begins on the fifth byte.
The Scan Commands require five parameters;
10-LEQ
0 5-00:
Scan for each chaYacfervv
tor less than or equa(to;!he
character within the field leQgth•. (
scan stops after the first less thah,ore
condition is met.
'., •.;"..>,
Step Size: The Step Size field specifies the
offset to the next sector in a multisector
scan. In this case, the next sector address is
generated by adding the Step Size to the
current sector address.
Parameter 4, Field Length
Specifies the number of bytes to be compared (length of
key). While the range of legal values is from 1 to 255, the
field length specified should be evenly divisible into the
sector length to prevent the key from being split at sector
boundaries, if the multisector scan commands are used.
Parameter 0, Track Address
Specifies the track number containing the sectors to be
scanned. Legal values range from OOH to 4C H (0 to 76) for
a standard diskette and from OOH to 22H (0 to 34) for a
mini-sized diskette.
Scan Command Results
More detailed information about the completion of Scan
Commands may be obtained by executing Read Special
Register commands.
Parameter 1, Sector Address
Specifies the first sector to be scanned. The number of
sectors scanned is specified in parameter 2, and the order
in which sectors are scanned is specified in parameter 3.
Parameter 2, Sector Length/Number of Sectors
The sector length field (bits 7-51 specifies the number of
data bytes allocated to each sector (see parameter 2,
routine read and write commands for field interpretationl.
The number of sectors field (bils 4-01 specifies the number
of sectors to be scanned. The number specified ranges
from one sector to the physical number of sectors on the
track.
Read Special Register
Parameter
Results
(Hexl
06
The sector number of the sector in which the
specified scan data pattern was located.
Parameter 3
0 7-06:
Indicate scan type
OO-EO
Scan for each character within the field
length (key) equal to the corresponding character within the disk sector. The scan stops
after the first equal condition is met.
01-GEO
Scan for each character within the disk sector greater than or equal to the corresponding character within the field length (key).
The scan stops after the first greater than or
equal condition is met.
14
MSB Count - The number of 128 byte blocks
remaining to be compared in the current sector
when the scan data pattern was located. This
register is decremented with each 128 byte block
read.
13
LSB Count - The number of bytes remaining to
be compared in the current sector when the scan
data pattern is located. This register is initialized
to 128 and is decremented with each byte
compared.
Upon a scan met condition, the equation below can be
used to determine the last byte in the located pattern.
Pointer = sector length - ((Register
11-86
14HI -128 + (Register 13H))
8271
8271 Scan Command Example
Assume there are only 2 records on track 0 with the
following data:
Record 01: 01 02 03 04 05 06 07 08 000 .... 00
Record 02: 01 02 AA 55 00 00 00 00 ........ 00
··c· ...
Command
·
·
·
·
·
·
Field [11 Starting
Length Sector #
Special Registers [4J
# of
Sectors
Completion
Code l31
R06
Key[2 J
R14
R13
Comment
SCAN EO
2
1
1
01,02
SME
01
0
1270
SCAN
SCAN
SCAN
SCAN
SCAN
SCAN
2
2
2
2
2
4
1
1
1
1
2
1
1
1
1
2
1
1
02,03
FF[5 J,05
FF!5 1,06
AA,55
01,02
05,06,07,08
SNM
SNM
SME
SME
SME
SME
X
X
X
X
X
X
01
02
02
01
0
0
0
0
1230
1250
1270
1210
SCAN GEO
SCAN GEO
SCAN GEO
4
4
4
1
1
1
1
1
2
05,06,07,08
05,04,07,08
00,03,AA,44 [6J
SME
SMNE
SNM
01
01
0
0
1210
1210
X
X
X
GEO-SME
GEO-SMNE
GEO-SNM
SCAN LEO
SCAN LEO
4
4
1
1
01,03,FF,04
01,02,FF,04
SMNE
SME
01
01
0
0
1250
1250
LEO-SMNE
LEO-SME
EO
EO
EO
EO
EO
EO
1
1
Met in fi rst field
Not met
Not met with don't care
Met with don't care
Met in Record 02
Starti ng sector'" 1
Field, Key length = 4
NOTES:
1. Field Length - Each record is partitioned into a number offields equal to the record size divided by the field length.
Note that the record size should be evenly divisable by the field length to insure proper operation of multi record
scan. Also, maximum field length = 256 bytes.
2. Key - The key is a string of bytes located in the user system memory. The key length should equal the field length.
By programming the 8257 DMA Controller into the auto load mode. the key will be recursively read in by the chip
(once per field).
3. Completion Code - Shows how Scan command was met or not met.
SNM - SCAN Not Met - 0 0 (also Good CompJete)
SME - SCAN Met Equal - 0 1
SMNE - SCAN Met Not Equal - 1 0
4. Special Registers
R06 - This register contains the record number where the scan was met.
R14 - This register contains the MSB count and is decremented every 128 characters.
Record Size
1
R14 =
(Initialize at
Beginning of Record)
000
001
010
011
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
0
1
3
7
••
•
R13 -
21 -
Length (R l
(07-05 of PAR 2)
•
••
•
••
This register contains a modulo 128 LSB count which is initialized to 128 at beginning of each record. This
count is decremented after each character is compared except for the last character in a pattern match
situation.
5. The OFFH character in the key is treated as a don't care character position.
6. The Scan comparison is done on a byte by byte basis. That is, byte 1 of each field is compared to byte 1 of the key,
byte 2 of each field is compared to byte 2 of the key, etc.
11-87
8271
N';<::;~~·;t'!,.{2· ~
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin with
Respect to Ground ................. - 0.5V to + 7V
Power Dissipation .......................... 1 Watt
·COMMENT: Stresses above those listed u;'~:;:r.·
Ratings" may cause permanent damage to the deViQ!!
rating only and functional operation of the device at tliellf,orA\llY
conditions above those indicated In the operational seclfO'I'I~:jjfi ...
specification Is not implied. Exposure to absolute maximum ratYn'9'I.I:ilfY<; ,
ditlons for extended periods may affect device reliability.
"~" ""0,.
D.C. CHARACTERISTICS
TA
=O·C to 70·C,
Vcc =
Symbol
+ 5.0V ± 5%
Parameter
Test Conditions
Min.
Max.
Unit
V,L
Input Low Voltage
-0.5
0.8
V
V,H
Input High Voltage
2.0
(Vee + 0.5)
V
VOL
Output Low Voltage
0.45
V
10L = 2.0 mA for Data Bus Pins
10L = 1.7 mA for All Other Pins
VOH
Output High Voltage
V
10H= -2201JA
I,L
Input Load Current
± 10
IJA
V,N = Vee to OV
loz
Off-State Output Current
±10
~
VOUT= Vee to OV
Icc
Vee Supply Current
180
mA
2.4
CAPACITANCE
TA =25·C, Vee=GND=OV
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
C'N
Input Capacitance
10
pF
tc= 1 MHz
C,IO
110 Capacitance
20
pF
Unmeasured Pins Returned to GND
11-88
8271
A.C. CHARACTERISTICS
T A =0·Ct070·C, Vcc= +5.0V ±5%
Read Cycle
Symbol
Min.
Parameter
Max.
Unit
tAc
Select Setup to RD
0
ns
tCA
Select Hold from RD
0
ns
tAA
RD Pulse Width
250
ns
tAD
Data Delay from Address
250
ns
tAD
Data Delay from RD
150
ns
C l = 150 pF, Note 2
tDF
Output Float Delay
20
100
ns
C l = 20 pF for Minimum;
150 pF for Maximum
tDc
DACK Setup to RD
25
tCD
DACK Hold from RD
25
tKO
Data Delay from DACK
Note 2
Note 2
ns
ns
250
ns
Max.
Unit
Write Cycle
Symbol
Parameter
Min.
tAc
Select Setup to WR
0
ns
tCA
Select Hold from WR
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup to WR
150
ns
two
Data Hold from WR
0
ns
toc
DACK Setup to WR
25
ns
tco
DACK Hold from WR
25
ns
Test Conditions
DMA
Symbol
tca
Test Conditions
Parameter
Request Hold from WR or RD (for Non·Burst Mode)
Other Timing
Symbol
Parameter
Min.
Max.
10
Unit
t ASTW
Reset Pulse Width
tr
Input Signal Rise Time
20
tf
Input Signal Fall Time
20
tASTS
Reset to First IOWR
tCY
Clock Period
250
tCl
Clock Low Period
110
tCH
Clock High Period
122
ns
tos
Data Window Setup to Unseparated Clock and Data
50
ns
tOH
Data Window Hold from Unseparated Clock and Data
0
ns
2
Test Conditions
tCY
ns
ns
tCY
Note 3
ns
NOTES:
1. All timing measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "0" at O.BV
Output "1" at 2.0V, "0" at O.BV
2. tAD, tAD, tAC, and tCA are not concurrent specs.
3. Standard Floppy: tCy=250 ns ±0.4%
Mini·Floppy: tCY = 500 ns ±0.4%
11·89
8271
WAVEFORMS
Read Wavaforms
DACK
}
- t o c -I
)
.
IRR
IRD
--tAC---
DATA BUS
f
--- ------------
.
tAO
IKD
](
I---tcD~1
)(
I--tcA-1
i---IDF-~ _ _ _ _ _ _ _
Write Waveforms
DACK
--toc-----'--'
--Y;
I-----IAC
){
I
DATA BUS
-+------tcD-
](
r
IWW
-~
f-o- leA---l
}(
loW
IWO--=l
DMA Waveforms
ORQ
__-II
[-,~=t
\~--~I----------------------------ROOR WR
----------~~~--------------------------
CHIP CLOCK
11·90
8271
WRITE DATA
PW
~F-~I
PULSE WIDTH PW = tCY % 30 ns
H (HALF BIT CELL) = 8 tCY
F (FULL BIT CELL) = 16 tCY
*tCY
= 250 ns
%0.4"10
250 ns %30 ns
2.0 lAs % 8 ns
4.0 lAs % 16 ns
**tCY = 500 ns %0.4"10
500 ns %30 ns
4.0 lAs % 16 ns
8.0 lAS % 32 ns
Figure 24. Write Data
READ DATA
*tCY = 250 ns
**tCY = 500 ns
F = 16 tCY
H
8 tCY
=
% 8 tCY
% 4 tCY
Figure 25. Read Data
*STANDARD FLEXIBLE DISK DRIVE TIMING
**MINI·FLOPPY TIMING
11·91
8271
UNSEPARATED
DATA
DATA
WINDOW
tDH~O
Figure 26. Single·Shot Data Separator
UNSEPARATED
DATA
"DATA
WINDOW
"DATA WINDOW MAY BE 180 0 OUT OF PHASE
IN PLO DATA SEPARATION MODE.
Figure 27. PLO Data Separator
11·92
ns -----
8273
PROGRAMMABLE HDLC/SDLC PROTOCOL ,',
CONTROLLER
• HDLC/SDLC Compatible
• Programmable NRZI Encode/Decode
• Frame Level Commands
• N·Blt Reception Capability
• Full Duplex, Half Duplex, or Loop
SDLC Operation
• Digital Phase Locked Loop Clock
Recovery
• Up to 64K Baud Transfers
• Minimum CPU Overhead
• Two User Programmable Modem
Control Ports
• Fully Compatible with 6080/6085 CPUs
+ 5V Supply
• Single
• Automatic FCS (CRC) Generation and
Checking
• 4O·Pln Package
The Intel- 8273 Programmable HOLCISOLC Protocol Controller is a dedicated device designed to support the ISOICCITrs HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high performance
microcomputer systems such as the MC8-85™. A frame level command set is achieved by a unique microprogrammed
dual processor chip architecture. The processing capability supported by the 8273 relieves the system CPU of the low
level real-time tasks normally associated with controllers.
BLOCK DIAGRAM
PIN CONFIGURATION
REGISTERS
FIAG1iET
Vee
T.tNT
PH;
elK
Pi3
PI2
TIIIINT RESULT
..,
RESET
TxDACK
COMMAND
RIIIINT RESULT
TEST MOOE
STATUS
RESULT
m
lxDRO
RiDACK
PA,
RltDRO
i'A,
Ro
!SA;
WR
Rx tNT
eD
cr!
000
TxD
DB'
Txe
DB.
RiC
DB3
RxD
084
32xCLK
085
os
086
DPLl
DB7
A,
GND
Ao
080-7
T,D
;:;c
TxDRQ
T;i5ACi(
RItDRQ
Rx'DA"CK
TxlNY
RxlNT
AD
WR
i5PiI
32x'CLK
RTs
;;,-.
ffi
CD
PAZ_4
Ao
A,
PIN NAMES
RESET
RxD
iW:
D80-D87
es
CHIP SELECT
mI1!1IlT
DATA SUS (8 BITS)
FLAG DETECT
TxtNT
TRANSMITTER INTERRUPT
elK
RESET
CLOCK INPUT
RESET
Ax C
TxC
RECEIVER CLOCK
TRANSMITTER CLOCK
TRANSMITTER DMA ACKNOWLEDGE
Tx 0
TRANSMITTER DATA
CLEAR TO SEND
TiUifi
TxORQ
TRANSMITTER DMA REQUEST
\Wi
READ INPUT
WRITE INPUT
RECEIVER DMA ACKNOWLEDGE
1m
~
Rx ORO
RECEIVER OMA REOUEST
Rx INT
AtJ-A 1
RECEIVER INTERRUPT
COMMAND REGISTER SELECT ADDRESS
DIGITAL PHASE LOCKED LOOP
i5Pil.
~
Rx 0
CTI
cs
32 TIMES CLOCK
RECEIVER DATA
elK
CPU INTERFACE
CD
CARRIER DETeCT
;2-::4 GP INPUT PORTS
Rif • ~:g:::~~~~~~
Vee
GND
+SVOLTSUPPLY
GROUND
11-93
FLAG'DET
MODEM INTERFACE
types of frames; an Informati~iiFra.me'is·'~~ansfer
data, a Supervisory Frame is used fOt90ntr,o~~s~s,
and a Non-sequenced Frame is used for i'litral.il.
Receive Interrupt Result
Contains the outcome of 8273 receive operation (good/
bad completion), followed by additional results which detail the reason for interrupt.
Status
The status register reflects the state of the 8273 CPU
Interface.
REGISTERS
DMA Data Transfers
The 8273 CPU interface supports two independent data
interfaces: receive data and transmit data. At high data
transmission speeds the data transfer rate of the 8273 is
great enough to justify the use of direct memory access
(DMA) for the data transfers. When the 8273 is configured
in DMA mode, the elements of the DMA interfaces are:
DPLL
32X elK
RTs
PBl _ 4
TxDRQ: Transmit DMARequest
Requests a transfer of data between memory and the
8273 for a transmit operation.
TxDACK: Transmit DMA Acknowledge
The TxDACK signal notifies the 8273 that a transmit
DMA cycle has been granted. It is also used with WR to
transfer data to the 8273 in non·DMA mode.
CPU INTERFACE
RxDRQ: Receive DMA Request
MODEM INTERFACE
Requests a transfer of data between the 8273 and memo
ory for a receive operation.
Figure 2. 8273 Block Diagram Showing CPU Interface
Functions
11·96
8273
RxDACK: Receive DMA Acknowledge
The RxDACK signal notifies the 8273 that a receive DMA
cycle has been granted. It is also used with RD to read
data from the 8273 in non-DMA mode.
REGISTERS
RD, WR: Read, Write
The RD and WR signals are used to specify the direction of
the data transfer.
DMA transfers require the use of a DMA controller such as
the Intel 8257. The function of the DMA controller is to
provide sequential addresses and timing for the transfer,
at a starting address determined by the CPU. Counting of
data block lengths is performed by the 8273.
To request a DMA transfer the 8273 raises the appropriate
DMA REQUEST. DMA ACKNOWLEDGE and READ enables DMA data onto the bus (independently of CHIP
SELECT). DMA ACKNOWLEDGE and WRITE transfers
DMA data to the 8273 (independent of CHIP SELECT).
32X eLK
RxDRQ
RxDACK
TxlNT
It is also possible to configure the 8273 in the non-DMA
data transfer mode. In this mode the CPU module must
pass data to the 8273 in response to non-DMA data requests indicated by the status word.
RI(INT
RD
We
A,
Modem Interface
,......----.......-
RESET
R,D
R,C
The 8273 Modem interface provides both dedicated and
user defined modem control functions. All the control
signals are active low so that EIA RS-232C inverting
drivers (Me 1488) and inverting receivers (MC 1489) may
be used to interface to standard modems. For asynchronous operation, this interface supports programmable
NRZI data encode/decode, a digital phase locked loop
for efficient clock extraction from NRZI data, and
modem control ports with automatic CTS, CD monitoring and RTS generation. This interface also allows the
8273 to operate in PRE-FRAME SYNC mode in which the
8273 prefixes 16 transitions to a frame to synchronize
idle lines before transmission of the first flag.
It should be noted that all the 8273 port operations deal
with logical values, for instance, bit DO of Port A will be a
one when CTS (Pin 30) is a physical zero (logical one),
Port A - Input Port
During operation, the 8273 interrogates input pins CTS
(Clear to Send) and CD (Carrier Detect). CTS is used to
condition the start of a transmission. If during transmission CTS is lost the 8273 generates an interrupt. During
reception, if CD is lost, the 8273 generates an interrupt.
0.,
0,
----...-l
i
D,
I
CPU INTERFACE
Port B - Output Port
During normal operation, if the CPU sets RTS active, the
8273 will not change this pin; however, if the CPU sets RTS
inactive, the 8273 will activate it before each transmission
and deactivate it one byte time after transmission. While
the receiver is active the flag detect pin is pulsed each time
a flag sequence is detected in the receive data stream.
Following an 8273 reset, all pins of Port B are set to a high,
inactive level.
D,
I
CLEAR TO SEND
MODEM INTERFACE
Figure 3. 8273 Block Diagram Showing Control logic
Functions
0,
"0
L<::r.s -
FLAG DET
INTERNAL DATA BUS -
II]
I
t
I
~-
REQUEST TO SEND
IUSER DE!.INED OUTPUT PB4, PB3, PB2. PB,
~ - CARRIER DETECT
I FLAG DETECT
~SER DEFINED INPUT PA4, PA3, PA2
The user defined input bits correspond to the 8273 PA 4 ,
PA 3 and PA, pins. The 8273 does not interrogate or manipulate these bits.
11·97
The user defined output bits correspond to the state of
PB4-PB, pins. The 8273 does not interrogate or manipulate these bits.
8273
Serial Data Logic
The Serial data is synchronized by the user transmit (TxC)
and receive (RxC) clocks. The leading edge of TxC
generates new transmit data and the trailing edge of RxC
is used to capture receive data. The NRZI encoding/
decoding of the receive and transmit data is programmable.
circuitry in place of the RxD pin,
send a message to itself to verify
TxO
RxC
RxO
\
/
X
\
X
operation'0t~~,
~h~~;tlfi1>
In the selectable clock diagnostic feature, when
looped back, the receiver may be presented incorreqt
sample timing by the external circuitry. The user may
select to sUbstitute the TxC pin for the RxC input on-chip
so that the clock used to generate the loop back data is
used to sample it. Since TxD is generated off the leading
edge of TxC and RxD is sampled on the trailing edge, the
selected clock allows bit synchronism.
The diagnostic features included in the Serial Data logic
are programmable loop back of data and selectable clock
for the receiver. In the loop-back mode, the data presented
to the TxD pin is internally routed to the receive data input
TxC
thU~.,/1
SOLC Loop
4 ';,
The OPLL simplifies the SOLe loop station implementation. In this application, each secondary station on a loop
data link is a repeater set in one-bit delay mode. The
signals sent out on the loop by the loop controller (primary
station) are relayed from station to station then, back to
the controller. Any secondary station finding its address in
the A field captures the frame for action at that station. All
received frames are relayed to the next station on the loop.
Loop stations are required to derive bit timing from the
incoming NRZI data stream. The OPLL generates sample
Rx clock timing for reception and uses the same clock to
implement Tx clock timing.
8273
LOOP
CONTROLLER
RxO 1 - - - - - - - ,
.------tTxO
"fXC
R.xD RxC
TxD
8273
8273
LOOP
LOOP
TERMINAL
TERMINAL
TxO~----~----------~--~~RxO
Figure 6. SOLC Loop Application
11·101
'~/':~":&~~0~
8273
PRINCIPLES OF OPERATION
The 8273 is an intelligent peripheral controller which
relieves the CPU of many of the rote tasks associated with
constructing and receiving frames. It is fully compatible
with the MCS-80/85'· system bus. As a peripheral device,
it accepts commands from a CPU, executes these
commands and provides an Interrupt and Result back to
the CPU at the end of the execution. The communication
with the CPU is done by activation of CS, RD, WR pins,
while the A1, Ao select the appropriate registers on the
chip as described in the Hardware Description Section.
VES
The 8273 operation is composed of the following
sequence of events:
CPU WRllES COMMAND AND PARAMETERS INTO THE
8273 COMMAND AND PARAMETER REGISTERS.
NO
THE 8273 IS ON ITS OWN TO CARRY OUT THE COMMAND.
THE 8273 SIGNALS THE CPU THAT THE EXECUTION
HAS FINISHED. THE CPU MUST PERFORM A REAP
OPERATION OF ONE OR MORE OF THE REGISTERS.
END OF COMMAND PHASE
The Command Phase
During the command phase, the software writes a command to the command register. The command bytes provide a general description of the type of operation requested. Many commands require more detailed information about the command. In such a case up to four
parameters are written into the parameter register. The
flowchart of the command phase indicates that a command may not be issued if the Status Register indicates
that the device is busy. Similarly if a parameter is issued
when the Parameter Buffer shows full, incorrect operation
will occur.
The 8273 is a duplex device and both transmitter and
receiver may each be executing a command or passing
results at any given time. For this reason separate
interrupt pins are provided. However, the command register must be used for one command sequence at a time.
Status Register
The status register contains the status of the 8273 activity.
The description is as follows.
0,
OtiC\;
04
03
0,
0,
Do
!CBSVI CBF I CPBF IC"BF I "XINTI TxlNT I"XIR6] TxlRA]
VES
Figure 7. Command Phase Flowchart
Bit 6 CBF (Command Buffer Full)
Indicates that the command register is full, it is reset when
the 8273 accepts the command byte but does not imply
that execution has begun.
Bit 5 CPBF (Command Parameter Buffer Full)
CPBF is set when the parameter buffer is full, and is reset
by the 8273 when it accepts the parameter. The CPU may
poll CPBF to determine when additional parameters may
be written.
Bit 7 CBSY (Command Busy)
Indicates in-progress command, set for CPU poll when
Command Register is full, reset upon command phase
completion. It is improper to write a command when CBSY
is set; it results in incorrect operation.
Bit 4 CRBF (Command Result Buffer Full)
Indicates that an executed command immediate result is
present in the Result Register. It is set by 8273 and reset
when CPU reads the result.
11-102
8273
Bit 3 RxlNT (Receiver Interrupt)
Th. Ex.cutlon Phas.'-· i"r), r;!/, . .-
RxlNT indicates that the receiver requires CPU attention.
It is identical to RxlNT (pin 11) and is set by the 8273 either
upon good/bad completion of a specified command or by
Non-DMA data transfer. It is reset only after the CPU has
read the result byte or has received a data byte from the
8273 in a Non-DMA data transfer.
Upon accepting the last parameter, th~{82i3'ent
the Execution Phase. The execution phase 'ifla~<'&Of,!lll
of a DMA or other activity, and mayor may not fe.qi))'re.
CPU intervention. The CPU intervention is eliminatecl"t"
this phase if the system utilizes DMA for the data transfers, otherwise, for non-DMA data transfers, the CPU is
interrupted by the 8273 via TxlNT and RxlNT pins, for
each data byte request.
I()," {(~: >
Bit 2 TxlNT (Transmitter Interrupt)
The TxlNT indicates that the transmitter requires CPU
attention. It is identical to TxlNT (pin 21. It is set by 8273
either upon good/bad completion of a specified command
or by Non-DMA data transfer. It is reset only after the CPU
has read the result byte or has transferred transmit data
byte to the 8273 in a Non-DMA transfer.
Th. R.sult Phas.
During the result phase. the 8273 notifies the CPU of the
execution outcome of a command. This phase is initiated
by:
Bit 1 RxlRA (Receiver Interrupt Result Available)
The RxlRA is set by the 8273 when an interrupt result
byte is placed in the RxlNT register. It is reset after the
CPU has read the RxlNT register.
1. The successful completion of an operation
2. An error detected during an operation.
Bit 0 TxlRA (Transmitter Interrupt Result Available)
To facilitate quick network software decisions. two types
of execution results are provided:
The TxlRA is set by the 8273 when an interrupt result
byte is placed in the TxlNT register. It is reset when the
CPU has read the TxlNT register.
1. An Immediate Result
2. A Non-Immediate Result
0,
I,
I
{
.
Y
,
I
~
07 Os 05 04 03
AilS bits recelved
00 received
o
01-00 received
o
02-00 received
03-00 received
04-DO received
0,
o
•
0
0
0
°5-00 received
06-00 received
R...._
Inlerrupt R••utl Code Ax Sillus Aft.r INT
A1 match or general receive
A2 match
CRe error
o
o
Abort detected
o
o
Idle detect
06
05
0
0
0
O.
Active
Active
Active
Disabled
0
EOP detected
Frame les8 than 32 bits
Disabled
Active
0
OMA overrun detected
Disabled
o
Memory buffer overflow
Disabled
carrier detect failure
Disabled
Disabled
Receive Interrupt overrun
Figure B. Rx Interrupt Result Byte Format
Dr
Active
0
o
* Partial Byte Received
110
03
0,
02
DO
I
I,
,
D.
D,
1
02
0,
0
Do
0
Early transmit Interrupt
Frame tnmsmit complete
DMA underrun
Clear to Send ICTS) error
Abort complete
Figure 10. Tx Interrupt Result Byte Format
11-103
8273
,;t,,;:,,~#(i§:;
Immediate result is provided by the 8273 for commands
such as Read Port A and Read Port B which have
information (CTS, CO, RTS, etd that the network
software needs to make quick operational decisions.
A command which cannot provide an immediate result will
generate an interrupt to signal the beginning of the Result
phase. The immediate results are provided in the Result
Register; all non-immediate results are available upon
device interrupt, through Tx Interrupt Result Register
Txl/R or Rx Interrupt Result Register RxI/R. The result
may consist of a one-byte interrupt code indicating the
condition for the interrupt and,ito,ictuir.elt:tbytes which detail the condition.
""J,/",
Tx and Rx Interrupt Result Registers
The Result Registers have a result code, the th:~e';~\1h
order bits 07-05 of which are set to zero for all but me
receive command. This command result contains a count
that indicates the number of bits received in the last byte. If
a partial byte is received, the high order bits of the last data
byte are indeterminate.
All results indicated in the command summary must be
read during the result phase.
11-104
8273
'li'
,},c~:3'tcJ;'>
c,<,
,-----
N~"cig~AI
I
I
I DMA
I MODE
READ STATUS
REGISTER
I
I
I
I
I
r -______Y~E~S_<
I
~N~D~----------~,
READ STATUS
REGISTER
DATA REQUEST
NQN·DMA MODE
USE BACK of AD OR
WR TO READ OR
WRITE DATA
( END)
YES
READ IIR
REGISTER
RESULT PHASE FLOWCHART -
11-105
INTERRUPT RESULTS
!~,"'~~:.k l':.
8273
.~··./ ..... i
---....
AFTER COMMAND PHASE COMPLETION (READ PORT A. PORT B)
READ STATUS
REGISTER
READ RESULT
REGISTER
RESULT PHASE FLOWCHART -
Figure 9. Rx Interrupt Service
11·106
IMMEDIATE RESULTS
8273
DETAILED COMMAND DESCRIPTION
Initialization SeUReset Commanda
General
These commands are used to manipulate data withlhthe "
8273 registers. The Set commands have a single param.~~: •
eter which is a mask that corresponds to the bits to ~ 5et.'(·,:
(They perform a logical-OR of the specified register with
the mask provided as a parameter). The Register
commands have a single parameter which is a mask that
has a zero in the bit positions that are to be reset. (They
perform a logical-AND of the specified register with the
mask).
The 8273 HDLC/SDLC controller supports a comprehensive set of high level commands which allows the 8273 to
be readily used in full-duplex, half-duplex, synchronous,
asynchronous and SDLC loop configuration, with or
without modems. These frame-level commands minimize
CPU and software overhead. The 8273 has address and
control byte buffers which allow the receive and transmit
commands to be used in buffered or non-buffered modes.
In buffered transmit mode, the 8273 transmits a flag
automatically, reads the Address and Control buffer
registers and transmits the fields, then via DMA, it fetches
the information field. The 8273, having transmitted the
information field, automatically appends the Frame Check
Sequence (FCS) and the end flag. Correspondingly, in
buffered read mode, the Address and Control fields are
stored in their respective buffer registers and only
Information Field is transferred to memory.
In non-buffered transmit mode, the 8273 transmits the
beginning flag automatically, then fetches and transmits
the Address, Control and Information fields from the
memory, appends the FCS character and an end flag. In
the non-buffered receive mode the entire contents of a
frame are sent to memory with the exception of the flags
and FCS.
HOLC Implementation
HDLC Address and Control field are extendable. The
extension is selected by setting the low order bit of the
field to be extended to a one, a zero in the low order bit
indicates the last byte of the respective field.
Since Address/Control field extension is normally done
with software to maximize extension flexibility, the 8273
does not create or operate upon contents of the extended
HDLC Address/Control fields. Extended fields are
transparently passed by the 8273 to user as either
interrupt results or data transfer requests. Software must
assemble the fields for transmission and interrogate them
upon reception.
However, the user can take advantage of the powerful
8273 commands to minimize CPU/Software overhead and
simplify buffer management in handling extended fields.
For instance buffered mode can be used to separate the
first two bytes, then interrogate the others from buffer.
Buffered mode is perfect for a two byte address field.
The 8273 when programmed, recognizes protocol
characters unique to HDLC such as Abort, which is a
string of seven or more ones (01111111). Since Abort
character is the same as the GA (EOP) character used in
SDLC Loop applications, Loop Transmit and Receive
commands are not recommended to be used in HDLC.
HDLC does not support Loop mode.
Set One-Bit Delay (CMD Code A4)
When one bit delay is set, 8273 retransmits the received
data stream one bit delayed. This mode is entered at a
receiver character boundary, and should only be used by
Loop Stations.
Reset One-Bit Delay (CMD Code 64)
The 8273 stops the one bit delayed retransmission mode.
Set Data Transfer Mode (CMD Code 97)
~
~
~
~
~
~
~
~
~
~
:::·1 : 1~ 1: 1: 1: I' 1: 1: 1: I' 1
When the data transfer mode is set, the 8273 will interrupt
when data bytes are required for transmission or are
available from a receive. If a transmit interrupt occurs and
the status indicates that there is no Transmit Result
(TxIRA = 0), the interrupt is a transmit data request. If a
receive interrupt occurs and the status indicates that there
is no receive result (RxIRA = 0), the interrupt is a receive
data request.
Reset Data Transfer Mode (CMD Code 57)
If the Data Transfer Mode is reset, the 8273 data transfers
are performed through the DMA requests without interrupt·
ing the CPU.
11-107
8273
(~O)
Set Operating Mode (CMO Code 91)
Flag Stream Mode
If this bit is set to a one, the foliowing'::!~!'e;(;lU
operation of the transmitter.
"'J; 11 >/ •• ,
(,e,"..,.c
~
)
..
.";/,\; ;;;
I-T_R_A_N_S_M_IT_T_E_R_S_T_A_T_E-+-_ _ _ _ _ _ _ _--I
1 = BUfFERED MODE
1 :: EARLY INTERRUPT MODE
Idle
Transmit or Transmit.}
Transparent Active
Send Flags immediately.
Send Flags after the
transmission complete
Loop Transmit Active
1 Bit Delay Active
Ignore command.
Ignore command.
t'S:"1f}8
1 :: EOP INTERRUPT MODE
If this bit is reset to zero the following table outlines the
operation of the transmitter.
I 1 = HOLe MODE
Reset Operating Mode (CMO Code 51)
TRANSMITTER STATE
IDLE
Transmit or Transmit·
Transparent Active
Loop Transmit Active
1 Bit Delay Active
Any mode switches set in eMD code 91 can be reset using
this command by placing zeros in the appropriate
positions.
(OS) HOLC Mode
I n HOLe mode, a bit sequence of seven ones (01111111) is
interpreted as an abort character. Otherwise, eight ones
(011111111) signal an abort.
}
ACTION
Send Idles on next character
boundary.
Send Idles after the transmission
is complete.
Ignore command.
Ignore 00 mmand.
Set Serial 1/0 Mode (CMO Code AO)
(04) EOP Interrupt Mode
In EOP interrupt mode, an interrupt is generated
whenever an EOP character (01111111) is detected by an
active receiver. This mode is useful forthe implementation
of an SOLe loop controller in detecting the end of a
message stream after a loop poll.
\ 1 = NAZl MODE
1 '" TxC .... RxC
1 = LOOP BACK TxD ___ RxD
Reset Serial I/O Mode (CMD Code 60)
(03) Transmitter Early Interrupt Mode (Tx)
The early interrupt mode is specified to indicate when the
8273 should generate an end of frame interrupt. When set,
an early interrupt is generated when the last data
character has been passed to the 8273. If the user software
responds with another transmit command before the final
flag is sent, the final flag interrupt will not be generated
and a new frame will immediately begin when the current
frame is complete. This permits frames to be separated by
a single flag. If no additional Tx commands are provided, a
final interrupt will follow.
If this bit is zero, the interrupt will be generated only after
the final flag has been transmitted.
(02) Buffered Mode
If the buffered mode bit is set to a one, the first two bytes
(normally the address (A) and control (e) fields) of a frame
are buffered by the 8273. If this bit is a zero the address and
control fields are passed to and from memory.
This command allows bits set in eMD code AO to be reset
by placing zeros in the appropriate positions.
(02) Loop Back
If this bit is set to a one, the transmit data is internally routed
to the receive data circuitry.
(01) TxC __ Rxe
If this bit is set to a one, the transmit clock is internally
routed to the receive clock circuitry. It is normally used
with the loop back bit (02),
(DO) NRZI Mode
(01) Preframe Sync Mode
If this bit is set to a one ,the 8273 will transmit two characters before the first flag of a frame.
To guarantee sixteen line transitions, the 8273 sends two
bytes of data (OO)H if NRZI is set or data (55)H if NRZI is not
set.
If this bit is set to a one, NRZI encoding and decoding of
transmit and receive data is provided. If this bit is a zero, the
transmit and receive data is treated as a normal positive logic
bit stream.
NRZI encoding specifies that a zero causes a change in the
polarity of the transmitted signal and a one causes no polarity
change. NRZI is used in all asynchronous operations.
Refer to IBM document GA27-3093 for details.
11-108
8273
il
Selective Receive (CMD Code C1).
Reset Device Command
:1
r
CMD
PAR
An 8273 reset command is executed by outputing a (01)H
followed by (OO)H to the reset register (TMR). See 8273
AC timing characteristics for Reset pulse specifications.
PAR
PAR
PAR
The reset command emulates the action of the reset pin.
1. The modem control signals are forced high (inactive
level).
2. The 8273 status register flags are cleared.
3. Any commands in progress are terminated immediately.
4. The 8273 enters an idle state until the next command is
issued.
5. The Serial 110 and Operating Mode registers are set
to zero and OMA data register transfer mode is
selected.
6. The device assumes a non-loop SOLC terminal role.
° °
° 1
° 1
° 1
° 1
1
'10101°1°1°1'
LEAST SIGNIFICANT BYTE OF THE
RECEIVE BUFFER LENGTH (80)
MOST SIGNIFICANT BYTE OF RECEIVE
BUFFER LENGTH (Sl)
RECEIVE FRAME ADDRESS MATCH
FIELD ONE (Al)
RECEIVE FRAME ADDRESS MATCH
FIELD TWO (A2)
Selective receive is a receive mode in which frames are
ignored unless the address field matches anyone of two
address fields given to the 8273 as parameters.
When selective receive is used in HOLe the 8273 looks at
the first character, if extended, software must then decide
if the message is for this unit.
Receive Commands
Selective Loop Receive (CMD Code C2)
The 8273 supports three receive commands: General
Receive, Selective Receive, and Selective Loop Receive.
General Receive (CMD Code CO)
General receive is a receive mode in which frames are
received regardless of the contents of the address field.
CMD
PAR
PAR
CMD: ° ° '1'101010[01010
, LEAST SIGNIFICANT BYTE OF THE
PAR:
°
RECEIVE BUFFER LENGTH (80)
, MOST SIGNIFICANT BYTE OF RECEIVE
PAR:
°
BUFFER LENGTH (Bl)
PAR
PAR
NOTES:
1. "buffered mode is specified, the RO: R1 receive frame length
(result) is the number of data bytes received.
2. If non-buffered mode is specified, the RO, R1 receive frame
length (result) is the number of data bytes received plus two
(the count includes the address and control bytes).
3. The frame check sequence (FCS) is not transferred to
memory.
4. Frames with less than 32 bits between flags are ignored (no
interrupt generated) if the buffered mode is specified.
5. In the non-buffered mode an interrupt is generated when a
less than 32 bit frame is received, since data transfer requests
have occurred.
6. The 8273 receiver is always disabled when an Idle is received
after a valid frame. The CPU module must issue a receive
command to re-enable the receiver.
7. The intervening ABORT character between a final flag and an
IDLE does not generate an interrupt.
8. If an ABORT Character is not preceded by a flag and is followed by an IDLE, an interrupt will be generated for the ABORT
followed by an IDLE interrupt one character time later. The
reception of an ABORT will disable the receiver.
° 0 '1'1°1°1°1°1'1°
LEAST SIGNIFICANT BYTE OF THE
° ° RECEIVE
BUFFER LENGTH (BO)
1
MOST SIGNIFICANT BYTE OF RECEIVE
°
BUFFER LENGTH (B1)
FRAME ADDRESS MATCH
° 1 RECEIVE
FIELD ONE (All
,
RECEIVE FRAME ADDRESS MATCH
°
FIELD TWO (A2)
Selective loop receive operates like selective receive except that the transmitter is placed in flag stream mode
automatically after detecting an EOP (01111111) following
a valid received frame. The one bit delay mode is also
reset at the end of a selective loop receive.
Receive Disable (CMD Code C5)
Terminates an active receive command immediately.
11-109
A,
Ao
D7
CMDI ° I ° I 1 I
PAR:
NONE
D6
'1
D5
D4
03
D2
0,
° I ° I ° I' I ° I
Do
1
8273
Transmit Commands
The 8273 supports three transmit commands: Transmit
Frame, Loop Transmit, Transmit Transparent.
CMD,
0
0
PAR,
Transmit Frame (CMD Code C8)
MOST SIGNIFICANT BYTE OF
PAR,
CMD
PAR
,
,
PAR
PAR
0
0
0
1
I
J
01
oj
J
1
1
1J 0
01 0
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH ILOI
0
1
MOST SIGNifiCANT BYTE OF
0
1
ADDRESS FIELD Of TRANSMIT FRAME IAI
0
1
CONTROL FIELD OF TRANSMIT FRAME IC)
FRAME LENGTH ILl I
The 8273 will transmit a block of raw data without
protocol, i.e., no zero bit insertion, flags, or frame check
sequences.
FRAME LENGTH ILlI
,
PAR
Transmits one frame including: initial flag, frame check
sequence, and the final flag.
11 the buffered mode is specified, the LO, L1, frame length
provided as a parameter is the length of the information
field and the address and control fields must be input.
I n unbuffered mode the frame length provided must be the
length of the information field plus two and the address
and control fields must be the first two bytes of data. Thus
only the frame length bytes are required as parameters.
Loop Transmit (CMD Code CAl
Abort Transmit Commands
An abort command is supported for each type of transmit
command. The abort commands are ignored if a transmit
command is not in progress.
Abort Transmit Frame (CMD Code CC)
Al
CMO,
PAR:
Ao
D7
06
Os
04
D3
02
01
00
I 0 I 0 I 1 I 1I0 I0 I1 I 1 I0 I0
NONE
After an abort character (eight contiguous ones) is transmitted, the transmitter reverts to sending flags or idles as a
function of the flag stream mode specified.
Abort Loop Transmit (CMD Code CE)
CMD
,
PAR
I 1 I 0 I 0 I 1I 0 I 1 I 0
0
0
1
0
1
LEAST SIGNIFICANT BYTE Of
FRAME LENGTH (LO)
PAR
0
1
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (U)
PAR
0
1
ADDRESS FIELD OF TRANSMIT FRAME IA)
PAR
0
1
CONTROL FIELD OF TRANSMIT FRAME (c)
~
CMD
PAR;
~
~
~
~
~
~
~
~
~
0
1
1
0
0
1
1
1
0
co- I I I I I I I I I
NONE
After a flag is transmitted the transmitter reverts to one bit
delay mode.
Abort Transmit Transparent (CMD Code CD)
Transmits one frame in the same manner as the transmit
frame command except:
1. This command should be given only in one-bit delay
mode.
2. If the flag stream mode is not active transmission will
begin after a received EOP has been converted to a
flag.
3. If the flag stream mode is active transmission will
begin atthe next flag boundary for buffered mode or at
the third flag boundary for non-buffered mode.
4. At the end of a loop transmit the one-bit delay mode is
entered and the flag stream mode is reset.
Al
CMD,
PAR:
Ao
D7
06
05
04
03
02
D1
Do
I 0 I 0 I 1 I 1 I0 I 0 I1 I 1 I 0 I 1
NONE
The transmitter reverts to sending flags or idles as a function of the flag stream mode specified.
11·110
8273
Modem Control Commands
(05) Flag Detect
The modem control commands are used to manipulate the
modem control ports.
This bit can be used to set the flag deteot~Jfu lj
will be reset when the next flag is detected~ ~!,
When read Port A or Port B commands are executed the
result of the command is returned in the result register.
The Bit Set Port B command requires a parameter that is a
mask that corresponds to the bits to be set. The Bit Reset
Port B command requires a mask that has a zero in the bit
positions that are to be reset.
These bits correspond to the state of the PB4-PB, outpJr
pins.
',C,'
(04-01) User Defined Outputs
(Do) Request to Send
This is a dedicated 8273 modem control signal, and
reflects the same logical state of RTS pin.
Read Port A (CMO Code 22)
CMD
PAR,
~
~
~
~
lot
0
tot
0
~
~
~
I ' tot
0
~
~
~
Reset Port B Bits (CMD Code 63)
tot ' t 0
This command allows Port B user defined bits to be reset.
NONE
Read Port B (CMO Code 23)
A,
CMD:
PAR:
I
0
AO
07
Os
Ds
0,
I Io I I, I I
0
0
0
03
O2
0
0
0,
~:~ I
DO
I , I,
0
I I I I I I I I' I I
l
NONE
I I:I:I' I I I I' I' I
0
0
0
I
0
t RTS - REQUEST TO SEND
USER DEFINED
FLAG DETECT
This command allows user defined Port B pins to be set.
0
0
L-
Set Port B Bits (CMO Code A3)
~:~'I
1:,_
This command allows Port B (04-0,) user defined bits to
be reset. These bits correspond to Output Port pins (PB4PB,).
0
~ t RTS -
REQUEST TO SEND
~-"IN-"E:.=D_ _ _ _ __
FLAG DeTECT
8273 Command Summary
Command Description
Command
(HEX)
Parameter
Result
Port
Results
Completion
Interrupt
Set One Bit Delay
A4
Set Mask
None
-
No
Reset One Bit Delay
64
Reset Mask
None
-
No
Set Data Transfer Mode
97
Set Mask
None
No
Reset Data Transfer Mode
57
Reset Mask
None
-
Set Operating Mode
91
Set Mask
None
-
No
Reset Operating Mode
51
Reset Mask
None
No
Set Serial 1/0 Mode
AO
Set Mask
None
Reset Serial 1/0 Mode
60
Reset Mask
None
-
No
No
No
General Receive
CO
BO,Bl
RIC,RO,RI,(A,C)(2)
RXI/R
Yes
Selective Receive
C1
BO,B1,A1,A2
RIC,RO,R1,(A,C)(2)
RXI/R
Yes
Selective Loop Receive
C2
BO,B1,A1,A2
RIC,RO,R1,(A,C)(2)
RXI/R
Yes
Receive Disable
C5
None
None
-
No
Transmit Frame
CB
LO,L 1,(A,C)(')
TIC
TXI/R
Yes
Loop Transmit
CA
LO,L1,(A,C)(')
TIC
Transmit Transparent
C9
LO,L1
TIC
Abort Transmit Frame
CC
None
Abort Loop Transmit
CE
None
Abort Transmit Transparent
CD
None
Read Port A
22
None
Read Port B
23
None
Set Port B Bit
A3
Set Mask
Reset Port B Bit
63
Reset Mask
Notes: 1. Issued only when in buffered mode.
TXI/R
Yes
TXI/R
Yes
TIC
TXI/R
Yes
TIC
TXI/R
Yes
TIC
TXI/R
Yes
Port Value
Result
No
Port Value
Result
No
None
-
No
None
-
No
2. Read as results only in buffered mode,
11·111
I
8273
8273 Command Summary Key
80
- Least significant byte of the receive buffer
length.
- Most significant byte of the receive buffer
length.
LO
- Least significant byte of the Tx frame length.
L1
- Most significant byte of the Tx frame length.
A1
- Receive frame address match field one.
A2
- Receive frame address match field two.
A
- Address field of received frame. If non-buffered
mode is specified, this result is not provided.
C
- Control field of received frame. If non-buffered
mode is specified this result is not provided.
RXI/R - Receive interrupt result register.
TXI/R - Transmit interrupt result register.
RO
- Least significant byte of the length of the frame
received.
R1
- Most significant byte of the length of the frame
received.
RIC
- Receiver interrupt result code.
TIC
- Transmitter interrupt result code.
81
COMMAND
I
t
GENERAL
RECEIVE
(Ro. R,I
DATA IN
DMA REQUESTS
DATA
I~~ERRUPTS
t
t
t
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....I_A
_ _...I._C_ _.I.__,- - - - - - - - - -
I
i
NON·BUFFERED MODE
CPU INTERRUPTS
Figure 12. Typical Frame Reception
11-112
t
FRAME
COMPLETE
t
POSSIBLE
IDLE INTERRUPT
,fro,.
8273
(''':'';;''''
t"
iff-,lit
.:~~ ,t!;'-'.~'i
'?v
"'
~~,;" .. j
TRANSMIT
FRAME
COMMAND
~.,
;~
Tx DATA
RTS
CTS
--1
DATA INTERRUPTS
L
-----'
t t t t t
DATA REQUESTS
OR
A
C
I,
12
13
------------~----~-----~-----~----~--------------------------------,
t
NON-BUFFERED MODE
CPU INTERRUPTS
~ EARLYTx
TRANSM ISSION
COMPLETE
!NTERRUP~
t
INTERRUPT
Figure 13. Typical Frame Transmission
MEMORIES
}
~
~
SYSTEM BUS
/~
/'?o,DB0-7
MEMR
lOW
MEMW
lOR
CS
HRO
AO,A,
DB0-7
RD
WR
CS
TXINT
RXINT
~7HACK
'\v7
RXC
RXD
TXC
TXD
TxDRO
8257
DMA
CONTROLLER
.
, ..
TxDACK
8273
RxDRO
MODEM
j.
RxDACK
A
"'-r
Figure 14. 8273 System Diagram
11-113
MODEM CONTROLS
I'
8273
ABSOLUTE MAXIMUM RATINGS*
AmbientTemperature Under Bias ", ... ,' O°C to 70°C
Storage Temperature ............... -65° C to +150°C
Voltage on Any Pin With
RespecttoGround ..................... -0,5Vto+7V
Power Dissipation ... , ................ , .. , , ., 1 Watt
'COMMENT: Stresses above those listed urrdflrJ:Ab
Maximum Ratings" may cause permanent da/hlli/eta
device, This is a stress rating only and fuiictiQHal
operation of the device at these or any other condit/dns'
above those indicated in the operational sections of this
specification is not implied, Exposure ,to absolute
maximum rating conditions for extended periods may
affect device reliability,
D.C. CHARACTERISTICS
T A = 0° C to 70° C, Vee = +5.0V ±5%
Symbol
Parameter
VIL
Input Low Voltage
V IH
Input High Voltage
Min.
Max.
Unit
-0.5
0.8
V
2.0
Vcc+ 0.5
Test Conditions
V
V
10L = 2.0 mA for Data Bus pins
10L = 1.7 mA for all other pins
VOL
Output Low Voltage
VOH
Output High Voltage
V
10H= -200 j.tA
IlL
Input Load Current
±10
j.tA
VIN=VCC toOV
loz
Off·State Output Current
±10
j.tA
VOUT= Vee to OV
lee
Vee Supply Current
180
mA
0.45
2.4
CAPACITANCE
TA
= 25°C;
Vee
= GND = OV
Max.
Unit
CIN
Input Capacitance
10
pF
te = 1MHz
CliO
I/O Capacitance
20
pF
Unmeasured Pins
Returned to GND
Symbol
Parameter
Min.
Typ.
Test Conditions
8273
A.C. CHARACTERISTICS
TA
=o·c to 70·C,
Vcc
= + 5.0V
± 5%
Read Cycle
:~~
··.·;.: •.···'it}.
Symbol
Parameter
Min.
Max.
Unit
Test CofwJut~
Note 3 ' ....W.
tAc
Select Setup to RD
0
ns
tCA
Select Hold from RD
0
ns
tRR
RD Pulse Width
0
ns
tAD
t RO
Data Delay from Address
250
ns
Note 3
Data Delay from RD
150
ns
tOF
Output Float Delay
20
100
ns
=150 pF, Note 3
Cl =20 pF for Minimum;
toc
DACK Setup to RD
25
tco
DACK Hold from RD
25
tKO
Data Delay from DACK
Note 3
Cl
150 pF for Maximum
ns
ns
250
ns
Max.
Unit
Write Cycle
Symbol
tAC
Parameter
Min.
Select Setup to WR
0
ns
tCA
Select Hold from WR
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup to WR
150
ns
two
Data Hold from WR
0
ns
toc
DACK Setup to WR
25
ns
tco
DACK Hold from WR
25
ns
Test Conditions
DMA
Symbol
tco
Parameter
Test Conditions
Request Hold from WR or RD (for Non·Burst Mode)
Other Timing
Symbol
Parameter
t RSTW
Reset Pulse Width
tr
Input Signal Rise Time
tf
t RSTS
Input Signal Fall Time
Min.
Max.
Unit
20
tCY
ns
10
20
Reset to First IOWR
2
ns
tCY
Clock
250
tCY
ns
tCl
Clock Low
110
ns
tCH
Clock High
122
ns
tOCl
Data Clock Low
200
ns
tOCH
Data Clock High
200
ns
tOCY
Data Clock
tTD
Transmit Data Delay
los
Data Setup Time
100
ns
tOH
Data Hold Time
0
ns
tOPlL
t FlO
DPLL Output Low
200
ns
8·tcy±50
ns
ns
15625
100
FLAG DET Output Low
Test Conditions
ns
NOTES:
1. All timing measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "a" at 0.8V
Outpul "1" at 2.0V, "a" at 0.8V
2. 64K baud maximum operating rate.
3. tAD, tRO, tAC, and tCA are not concurrent specs.
11·115
Note 2
Note 2
;
,
~,
WAVEFORMS
Read Waveforms
OACK
Ao, A" CS
-
'DC
'CD
:x
)
'RR ------"IJ..~_'_CA_--I_ _ _ __
~~--____- - -__-~J,
AD
~':~~_-~-Ao---'Ro--yJ<---l-,D-F~...-Ii- ______ _
DATA BUS
I----------'KO-----~--i
Write Waveforms
iD_
~'
~f----'AC-
](
'ww
1
'1-'cA-I
~
X
DATA BUS
'ow
1(
two-~
DMA Waveforms
DRO
®OR~
__
--oJ/
'CQ=.1
r
\~--~----------------------------
__I
XL______________________________________
CHIP CLOCK
11-116
8273
;. :",;,~t:l£:~:~".!'~:;r?
Transmit Data Waveforms
'~ ,
:;..
j
.1
teCt
tocy
\
tacH
.
~
TxD
~tTD--
Receive Data Waveforms
11---
-_tl~tocH-n--
--tOC-L-
RXD-~t~JE~J-DPLL Output Waveform
Flag Detect Output Waveform
11-117
."
., .
. :'1/:"' ,\\
'1 \ , '
8275
PROGRAMMABLE CRT CONTROLLER
• Programmable Screen and Character
Format
• Fully MC8-S0™ and MCS·SS™
Compatible
• 6 Independent Visual Field Attributes
• Dual Row Buffers
• 11 Visual Character Attributes
(Graphic Capability)
• Programmable DMA Burst Mode
• Cursor Control (4 Types)
• Single
• Light Pen Detection and Registers
• 40·Pln Package
+ 5V Supply
The Intell!!> 8275 Programmable CRT Controller is a single chip device to interface CRT raster scan displays with
Intell!!> microcomputer systems. Its primary function Is to refresh the display by buffering the Information from main
memory and keeping track of the display position of the screen. The flexibility designed into the 8275 will allow simple
Interface to almost any raster scan CRT display with a minimum of external hardware and software overhead.
PIN CONFIGURATION
BLOCK DIAGRAM
vcc
LC3
LC2
LCl
LCo
DRO
DACK
HRTC
VRTC
LAO
LAl
LTEN
RVV
VSP
GPAl
GPAo
HLGT
IRa
CCLK
CCe
CCs
CC4
CC3
CC2
CCl
CCo
Ri5
WR
LPEN
DBO
DBl
DB2
DB3
DB4
DBS
DB6
DB7
GIIID
CCLK
DBo-7
CCo-6
DRQ_----,
LCO-3
DACK
IRQ
cs
AO
LAo_l
HRTe
VRTe
HLGT
RVV
PIN NAMES
LTEN
vsp
......----oor"~
GPAO_1
lPEN
11·118
:\
.' .
,'.;.
8275
PIN DESCRIPTIONS
Pin # Pin Name 1/0
o
1
Pin Description
Line count. Output from the line count-
2
er which is used to address the character
3
4
generator for the line positions on the
screen.
o
5
6
7
o
Horizontal retrace. Output signal which
is active during the pro~rammed horizonta' retrace interval. During this peri-
od the VSP output is high and the
LTEN output is low.
8
VRTC
o
VCC
39
38
LAO
LAI
o
put is low.
9
Read input. A control signal to read
10
Write input. A control signal to write
commands into the control registers or
write data into the row buffers during a
horizontal and vertical line combinations
character attribute codes.
37
LTEN
o
12
13
14
15
16
17
18
19
DBO
D81
DB2
DB3
DB4
DB5
DB6
DB7
36
RVV
o
35
VSP
o
20
Ground
Reverse video. Output signal used to
indicate the CRT circuitry to reverse the
video signal. This output is active at the
cursor position if a reverse video block
cursor is programmed or at the positions
specified by the field attribute codes.
Video suppression. Output signal used to
blank the video signal to the CRT. This
output is active:
during the horizontal and vertical retrace intervals.
at the top and bottom lines of rows if
underline is programmed to be number
8 or greater.
when an end of row or end of screen
code is detected.
When a DMA underrun occurs.
Light pen. Input signal from the CRT
system signifying that a light pen signal
has been detected.
I/O
Light enable. Output signal used to
enable the video signal to the CRT. This
output is active at the programmed
u nderli ne cu rsar position, and at positions specified by attribute codes.
DMA cycle.
LPEN
attribute codes. These attribute
for the graphic displays specified by the
registers.
11
Line
codes have to be decoded externaily by
the dot/timing logic to generate the
Vertical retrace. Output signal which is
active during the programmed vertical
retrace interval. During this period the
VSP output is high and the LTEN out-
Pin Description
+5V power supply
DMA request. Output signal to the 8257
DMA controiler requesting a DMA cycle.
DMA acknowledge. Input signal from
the 8257 DMA controiler acknowledging
that the requested DMA cycle has been
granted.
HRTC
Pin # Pin Name 1/0
40
at regular intervals (1/16 frame frequency for cursor, 1/32 frame fre-
Bi-directional three-state data bus lines.
1 he outputs are enabled during a read of
the C or P ports.
quency for character and field attri-
butesl - to create blinking displays
as specified by cursor, character attribute, or field attribute programming.
34
33
GPAI
GPAO
o
32
HLGT
o
General purpose attribute codes. Out-
puts which are enabled by the general
purpose field attribute codes.
Ground
Highlight. Output signal used to intensify the display at particular positions on
the screen as specified by the character
attribute codes or field attribute codes.
31
IRQ
o
Interrupt request.
30
CCLK
I
Character clock (from dot/timing logicl.
29
28
27
26
25
24
23
CC6
CC5
CC4
CC3
CC2
CCI
o
Character codes. Output from the row
buffers used for character selection in
the character generator.
CCo
22
cs
21
AO
Chip select. The read and write are en-
abled by
11-119
CS.
Port address. A high input on AO selects
the "e" port or command registers and a
low input selects the "P" port or parameter registers.
8275
FUNCTIONAL DESCRIPTION
Data Bus Buffer
This 3-state, bidirectional, B-bit buffer is used to interface
the 8275 to the system Data Bus.
This functional block accepts inputs from the System Control Bus and generates control signals for overall device
operation. It contains the Command, Parameter, and Status
Registers that store the various control formats for the
device functional definition.
AO
OPERATION
REGISTER
ORa _ _ _- - ,
0
Read
PREG
DACK
0
Write
PREG
IRa
1
Read
SREG
1
Write
CREG
RD (Read)
A "low" on this input informs the 8275 that the CPU is
reading data or status information from the 8275.
WR (Write)
A "low" on this input informs the 8275 that the CPU is
writing data or control words to the 8275.
Figure 1_ 8275 Block Diagram Showing Data Bus Buffer
and ReadIWrlte Functions
CS (Chip Select)
A "low" on this input selects the 8275. No reading or writ·
ing will occur unless the device is selected. When CS is high,
the Data Bus in the float state and RD and WR will have no
effect on the chip.
Ao
RD
WR
CS
0
0
0
1
0
0
0
0
0
DRQ (DMA Request)
1
X
X
A "high" on this output informs the DMA Controller that
the 8275 desires a DMA transfer.
DACK (DMA Acknowledge)
A "low" on this input informs the 8275 that a DMA cycle
is in progress.
IRQ (Interrupt Request)
A "high" on this output informs the CPU that the 8275
desires interrupt service.
11-120
0
0
1
1
1
X
0
X
Write 8275 Parameter
Read 8275 Parameter
Write 8275 Command
Read 8275 Status
Three·State
Three·state
8275
Character Counter
The Character Counter is a programmable counter that is
used to determine the number of characters to be displayed
per row and the length of the horizontal retrace interval. It
is driven by the CCLK (Character Clock) input, which
should be a derivative of the external dot clock.
DATA
D80_7
BUS
CCO_6
BUFFEA
Line Counter
The Line Counter is a programmable counter that is used to
determine the number of horizontal lines (Sweeps) per
character row. Its outputs are used to address the external
character generator ROM.
DRO_---,
LCO_3
DACK
IRO
Row Counter
The Row Counter is a programmable counter that is used to
determine the number of character rows to be displayed per
frame and length of the vertical retrace interval.
READI
WRITEi
CO~~~OL d
AO--
LOGIC
HRTe
VRTC
. HLGT
RVV
LTEN
Light Pen Registers
cs---
The Light Pen Registers are two registers that store the can·
tents of the character counter and the row counter when·
ever there is a rising edge on the LPEN (Light Pen) input.
VSP
GPAO_l
lPEN
Note: Software correction is required.
Figure 2. 8275 Block Diagram Showing Counter and
Register Functions
Raster Timing and Video Controls
The Raster Timing circuitry controls the timing of the
HRTC (Horizontal Retrace) and VRTC (Vertical Retrace)
outputs. The Video Control circuitry controls the generation of LAo_l (Line Attribute), HGL T (Highlight), RVV
(Reverse Video), l.TEN (Light Enable), VSP (Video Suppress), and GPAO-l (General Purpose Attribute) outputs.
FIFOs
There are two 16 character F I FOs in the 8275. They are
used to provide extra row buffer length in the Transparent
Attribute Mode (see Detailed Operation section).
Buffer Input/Output Controllers
Row Buffers
The Row Buffers are two 80 character
filled from the microcomputer system
character codes to be displayed. While
displaying a row of characters, the other
the next row of characters.
buffers. They are
memory with the
one row buffer is
is being filled with
The Buffer Input/Output Controllers decode the characters
being placed in the row buffers. If the character is a character attribute, field attribute or special code, these controllers control the appropriate action. (Examples: An
"End of Screen-Stop DMA" special code will cause the
Buffer Input Controller to stop further DMA requests. A
"Highlight" field attribute will cause the Buffer Output
Controller to activate the HGL T output.)
11-121
8275
SYSTEM OPERATION
The 8275 is programmable to a large number of different
display formats. It provides raster timing, display row buf·
fering, visual attribute decoding, cursor timing, and light
pen detection.
8~~;i'~j(')G0!1
It is designed to interface with the
and standard character generator ROMs fo/~~'finlilP
decoding. Dot level timing must be provided by e'h~H~t:
circuitry.
<"
MEMORIES
U
(
SYSTEM BUS
DBO_7
MNIIl'!
AO
DBO_7
lOW
MEMW
lOR
WR
CS
CS
HRO
HACK
IRO
RD
LCO_3
ORO
8257
DMA
CONTROLLER
VIDEO SIGNAL
CHARACTER
GENERATOR
DACK
8275
CRT
CONTROLLER
HORIZONTAL SYNC
CCO-6
CCLK
DOT
TIMING
AND
INTERFACE
VERTICAL SYNC
INTENSITY
VIDEO CONTROLS
Figure 3. 8275 Systems Block Diagram Showing Systems Operation
11·122
,
','
8275
General Systems Operational Description
The 8275 provides a "window" into the microcomputer
system memory.
Display characters are retrieved from memory and displayed on a row by row basis. The 8275 has two row buffers. While one row buffer is being used for display, the
other is being filled with the next row of characters to be
displayed. The number of display characters per row and
the number of character rows per frame are software programmable, providing easy interface to most CRT displays.
(See Programming Section.)
The 8275 requests DMA to fill the row buffer that is not
being used for display. DMA burst length and spacing is
programmable. (See Programming Section.)
The 8275 displays character rows one line at a time.
The number of lines per chara~tlit'J;dW, t
tion, and blanking of top and bottort}.lines
mabie. (See Programming Section.)
• ':..,
The 8275 provides special Control Codes whic~';ea~ bli;:us
to minimize DMA or software overhead. It also pl'0J([lres ~
Visual Attribute Codes to cause special action or symbtl1s ··j'i.
on the screen without the use of the character generator
(see Visual Attributes Section).
The 8275 also controls raster timing. This is done by generating Horizontal Retrace (H RTC) and Vertical Retrace
(V RTC) signals. The timing of these signals is programmable.
The 8275 can generate a cursor. Cursor location and format
are programmable. (See Programming Section.)
The 8275 has a light pen input and registers. The light pen
input is used to load the registers. Light pen registers can be
read on command. (See Programming Section.)
---------------------------------------1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00•••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
First Line of a Character Row
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000.00.0000000000000.000.008000.00.000.0
Second Line of a Character Row
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000.00.0000000000000.000.008000800.000.0
0.0000.0080000.00.0000000000000.000800.000.00.000.0
Third Line of a Character Row
---------------1 st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
080000.00 •• 000.00.0000000000000.000.00.000.008000.0
0.0000.00.0.00.0080000000000000.000.00.000.008000.0
O.OOOO.OO.OOOO.OO • • • • OOOOODOOOO • • • • ODO.OOO.OO.D.O.O
0.0000.00.00.0.00.000000000 DODD. 08 DO DO. DO O. DO. O. O. 0
O.OODO.OO.OOO • • CO. DOD DOD 0000 0008 00. 00 O. DO O. 00_0. 0.0
00 • • • • 000.0000.00 • • • • • 00000 DOD O. 00. 0000 • • • 0000.0.00
Seventh Line of a Character Row
Figure 4. Display 01 a Character Row
11-123
8275
Display Row Buffering
Before the start of a frame, the 8275 requests DMA and
one row buffer is filled with characters.
After all the lines of the chaPa~i::
roles of the two row buffers are<'~~he,c;f
procedure is followed for the next row. ,"t,
CCLK
celK
CCO_6
080_7
ORQ
CCO_6
LCO_3
DACK
ORQ
IRQ
DACK
LCO_3
IRQ
RD
WR
Ao
LAO_l
RD
HRTC
VAle
WR
HLGT
RVV
LTEN
lAO_l
AO
HRTe
VRTe
HLGT
RVV
os
GPAO_l
VSP
os
LTEN
GPAO_l
VSP
'T----r' '
LPEN
LPEN
Figure 5. First Row Buffer Filled
When the first horizontal sweep is started, character codes
are output to the character generator from the row buffer
just filled, Simultaneously, DMA begins filling the other
row buffer with. the next row of characters.
Figure 7. First Buffer Filled with Third Row,
Second Row Displayed
This is repeated until all of the character rows are displayed.
ceLK
060_7
DATA
BUS
BUFFER
ORQ _ _ _ _,
lCO_3
lAO_l
HRTe
AO--
VRTe
HlGT
RVV
LTEN
vsp
GPAO_l
LPEN
Figure 6. Second Buffer Filled, First Row Displayed
11·124
8275
Display Format
Row Format
Screen Format
The 8275 is designed to hold the line count stabl~·whHe.
outputting the appropriate character codes during ~ach
horizontal sweep. The line count is incrementeddutlng
horizontal retrace and the whole row of character codes are
output again during the next sweep. This is continued until
the whole character row is displayed.
The 8275 can be programmed to generate from 1 to 80
characters per row, and from 1 to 64 rows per frame.
The number of lines (horizontal sweeps) per character row
is programmable from 1 to 16.
The output of the line counter can be programmed to be in
one of two modes.
123456789 . . . . . . . . . . . . . . 80
2
3
4
5
6
7
8
9
In mode 0, the output of the line counter is the same as the
line number.
In mode 1, the line counter is offset by one from the line
number.
Note: In mode 1, while the first line (line number 01 is being dis·
played, the last count is output by the line counter (see
examples).
Line
Number
64
0
1
2
3
4
5
Figure 8. Screen Format
The 8275 can also be programmed to blank alternate rows.
In this mode, the first row is displayed, the second blanked,
the third displayed, etc. DMA is not requested for the
blanked rows.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•
• • •••••
•
•
•
•
0
0
0
0
0
0
0
0
0
II
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
7
0
8
9
0
10
11
12
13
14
15
0
0
•
0
0
0
0
0
0
Line
Line
Counter
Counter
Mode 0
Mode 1
0000
0001
0010
001 1
0100
0101
o1 1 0
0111
1000
1001
1010
1 01 1
1 100
1 10 1
1110
111
1111
0000
0001
0010
001 1
0100
0101
0110
01 1 1
1000
1001
1010
1011
1 100
1 101
1 1 10
Figure 10. Example of a 16·Line Format
123456789.
.. . . . . . . . .
.
.
Line
Number
. 80
2
0
1
2
3
4
5
3
4
5
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
7
0
8
0
9
0
• •
•
•
•
•
•• •• •
•
•
•
•
0
0
0
0
0
Line
Counter
Mode 0
Counter
0000
0001
0010
001 1
0100
0101
110
1 11
1000
1001
1001
0000
0001
0010
0011
0100
0101
0110
01 1 1
1000
o
o
Line
Mode 1
64
Figure 11. Example of a 10-Line Format
Figure 9. Blank Alternate Rows Mode
Mode 0 is useful for character generators that leave address
zero blank and start at address 1. Mode 1 is useful for char·
acter generators which start at address zero.
11·125
8275
~/'
/I«t";;~:('~: !:
Underline placement is also programmable (from line num·
ber 0 to 15). This is independent of the line counter mode.
If the line number of the underline is greater than 7 (line
number MSB = 1), then the top and bottom lines will be
blanked.
Line
Number
a
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
•
•
0
•
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o •
0
•
0
0
0
•
•
0
0
•
•••••••
•
•
•
••
•
•••••••••
0
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mod4tO
Line
Counter
Mode'
0000
0001
0010
00 11
0100
a 10 1
a 11 a
0111
1000
100 1
10 1 a
1011
1011
0000
0001
0010
00 11
0100
a1a1
a 11 a
0111
1000
1001
1010
Top and 80ttom
Lines are Blanked
-/$1'",.
'.tf".
."t.,;, 1;/~~.tfJ/,~.
Dot Format
Dot width and character width are
external timing and control circuitry.
dep~~~~';
{"'f/r; • r"'i
("!l/J/ltt:"I.Jt
Dot level timing circuitry should be designed to accept th'G·
parallel output of the character generator and shift it out
serially at the rate required by the CRT display.
8275
cc
VIDEO
VS.
SYNCHRONIZER
Figure 14. Typical Dot Level Block Diagram
Figure 12. Underline In Line Number 10
If the line number of the underline is less than or equal to 7
(line number MSB = 0), then the top and bottom lines will
not be blanked.
Dot width is a function of dot clock frequency.
Character width is a function of the character generator
width.
Horizontal character spacing is a function of the shift
register length.
Note: Video control and timing signals must be synchronized with
the video signal due to the character generator access delav.
Line
Number
a
0
0
1
2
0
0
o • DOD
o 0
0
•o•
•
o • 0
0
o • o DO.
0
0
4
0
0
5
6
7
o • DOD
o • o 0 0
3
•••••
•
•
0
0
•••••••
Line
Counter
Mode 0
Line
Counter
Mode 1
0000
0001
0010
0011
0100
a 10 1
a 11 a
0111
0111
0000
0001
0010
00 11
0100
a 10 1
a 11 a
,A
~l
Top and Bottom
Lines are not Blanked
Figure 13. Underline In Line Number 7
If the line number of the underline is greater than the maxi·
mum number of lines, the underline will not appear.
Blanking is accomplished by the VSP (Video Suppression)
Signal. Underline is· accomplished by the LTEN (Light
Enable) signal.
11·126
"~It,>
4
8275'
".,""',j,,,
""
"
~;
~.
.
Rastar Timing
The character counter is driven by the character clock input
(CCLK). It counts out the characters being displayed
(programmable from 1 to 80). It then causes the line
counter to increment, and it 'Starts counting out the hori·
zontal retrace interval (programmable from 2 to 32). This
is constantly repeated.
".",".j,'
".
1";
if'~'
The row counter is an internal counter drivel'(~,,n,e line
counter. It controls the functions of thlt row buffers; and
counts the number of character rows displayed.
''', ': ~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,' ,,0
ONE CHARACTER ROW
r
•
,
HRTC~U-U-LCo- a
INTERNAL
eeLK
ROW COUNTER
•
PROGRAMMABLE 1 TO 16
LINE COUNTS
Figure 16. Row Timing
HRTe
PROGRAMMABLE 1 TO 80 CCLKS
LeQ..
PRESENT LINE COUNT
----------------~
NEXT
LINE COUNT
After the row counter counts all of the rows in a frame
(programmable from 1 to 64), it starts counting out the
vertical retrace interval (programmable from 1 to 4).
Figure 15. line Timing
,
ONE FRAME
r
\
ROW'~~~~~~~ X:/'/X.XX:iY:f.:XFIRST
The line counter is driven by the character counter. It is
used to generate the line address outputs (LC O_J ) for the
character generator. After it counts all of the lines in a
character row (programmable from 1 to 16), it increments
the row counter, and starts over again. (See Character For·
mat Section for detailed description of Line Counter
functions.)
DISPLAY
ROW
VRTe
LAST
DISPLAY
ROW
FIRST
LAST
RETRACE RETRACE
ROW
ROW
~~'---L
."
PROGRAMMABLE
1 TO 64 ROW COUNTS
...
.
I
PROGRAMMABLE
1 TO 4 ROW COUNTS
Figure 17. Frame Timing
The Video Suppression Output (VSP) is active during
horizontal and vertical retrace intervals.
Dot level timing circuitry must synchronize
with the vioeo signal to the CRT Disp!ay.
11·127
~hese
outputs
8275
Interrupt Timing
DMATlmlng
."".,,; .
(I."
The 8275 can be programmed to request burst DMA transfers of 1 to 8 characters. The interval between bursts is also
programmable (from 0 to 55 character clock periods ±1).
This allows the user to tailor his DMA overhead to fit his
system needs.
7J
The first DMA request of the frame occurs one row time
before the end of vertical retrace. DMA requests continue
as programmed, until the row buffer is filled. If the row
buffer is filled in the middle of a burst, the 8275 terminates
the burst and resets the burst counter. No more DMA
requests will occur until the beginning of the next row.
At that time, DMA requests are activated as programmed
until the other buffer is filled.
INTERNAL~
ROW
COUNTER
LA
DISPLAY RETRACE
ROW
ROW
VRTe
~I-_ _~_J
IRQ
If, for any reason, there is a DMA underrun, a flag in the
status word will be set.
;j: .~ /:«
The 8275 can be programmed to generate llq)iltIjf, . . ~
request at the end of each frame. This can be" U$jid·'.tq
reinitialize the DMA controller. If the 8275 inte~~;';~,,:,
enable flag is set, an interrupt request will occur at the
'i.
beginning of the last display row.
)
Figure 19. Beginning of Interrupt Request
I RQ will go inactive after the status register is read.
INTERNAL
ROW
COUNTER
VRTC
IRQ
_~BUR~/
r
RD~~r-
NEXT
ROW BUFFER
FILLED
Figure 20_ End of Interrupt Request
Figure 18. DMA Timing
A reset command will also cause IRQ to go inactive, but
th is is not recommended during normal service.
Another method of reinitializing the DMA controller is to
have the DMA controller itself interrupt on terminal count.
With this method, the 8275 interrupt enable flag should not
be set.
The DMA controller is typically initialized for the next
frame at the end of the current frame.
Note: Upon power-up, the 8275 Interrupt Enable Flag may be set.
As a result, the user's cold start routine should write a reset
command to the 8275 before system interrupts are enabled.
11-128
8275
Character Attribute Codes
Character attribute codes are codes that can be u,sed"tQ"'!pI'l-"
erate graphics symbols without the use of' ·a., chjjract.r'
generator. This is accomplished by selectively acti~ati)1g'the'
Line Attribute outputs (LAO_1), the Video SuppresslQn'
output (VSP). and the Light Enable output. The dot level
timing circuitry can use these signals to generate the proper
symbols.
VISUAL ATTRIBUTES AND SPECIAL
CODES
The characters processed by the 8275 are 8-bit quantities.
The character code outputs provide the character generator
with 7 bits of address. The Most Significant Bit is the extra
bit and it is used to determine if it is a normal display
character (MSB ~ 0), or if it is a Visual Attribute or Special
Code (MSB = 1).
Character attributes can be programmed to blink or be
highlighted individually. Blinking is accomplished with the
Video Suppression output (VSP). Blink frequency is equal
to the screen refresh frequency divided by 32. Highlighting
is accomplished by activating the Highlight output (HGLT).
There are two types of Visual Attribute Codes. They are
Character Attributes and Field Attributes.
Character Attributes
MSB
LSB
11CCCCBH
I
IL
HIGHLIGHT
BLINK
L _ _ _ _ _ CHARACTER ATTRIBUTE CODE
HORIZ, RIGHT
HALF
O°r--=CH~A~R.~G~EN-,----r~~~~---------l~
Olr-------"'"=-t=D-t=====D
ENABLE
02~--------i===r=~--~==========l-.)
I
t===[}--+==f=F~[)
CHARACTER
GENERATORI-________
;~~ 0 3 ,
8275
SHIFT
REGISTER
06i-----t=r)--jf-+-i----.lU
HORtZ. LEFT HALF
LAl t---------~-------4+_--------<+-t-+--'
VIDEO
L~~--------~--------~--------~--~~
vsp~---------------------------------------------------------I
LTEN
r---------------------------------------------------------I
HGLTr--------------------------------------------------------_1
Figure 21. Typical Character Attribute Logic
11-129
1---------------- HIGHLIGHT
cI
8275
'j"w'c
~,.<:;.,
<\
. .• <'. ;,~\,t;;;t1(*f'f:! .
Character attributes were designed to produce the following graphics:
,
CHARACTER ATTRIBUTE
CODE "CCCC"
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underl ine
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
Above Underline
Underline
Below Underline
lA,
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUTPUTS
VSP
lAO
0
0
1
0
1
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
lTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
SYMBOL
I
~"-
"
DESCRIPTION
Top left Corner
Top Right Corner
I
L
~
~
-1
~
Bottom left Corner
Bottom Right Corner
Top Intersect
Right Intersect
left Intersect
~
Bottom Intersect
---
Horizontal Line
I
+
Vertical Line
Crossed Lines
Not Recommended'
Special Codes
Undefined
Illegal
1
I
Illegal
Undefined
I
I
Illegal
Undefined
I
'Character Attribute Code 1011 is not recommended for
normal operation. Since none of the attribute outputs are
active, the character Generator will not be disabled, and
an indeterminate character will be generated.
Character Attribute Codes 1101, 1110, and 1111 are illegal.
Blinking is active when B ; 1.
Highlight is active when H ; 1.
11·130
~ '"
8275
Special Codes
Field Attributes
Four special codes are available to help reduce memory,
software, or DMA overhead.
The field attributes are control codes which affect' the
visual characteristics for a field of characters, starting at the
character following the code up to, and inciudil'l!J, the
character which precedes the next field attribute code, or
up to the end of the frame. The field attributes are reset
during the vertical retrace interval.
Special Control Character
MSB
1 1
1
1
o
LSB
0 S S
~ SPECIAL CONTROL CODE
There are six field attributes:
Characters following the code are caused
to blink by activating the Video Suppression output (VSP). The blink frequency is equal to the
screen refresh frequency divided by 32.
1.
Blink -
2.
Highlight -
The End of Row Code (00) activates VSP and holds it to
the end of the line.
3.
The End of Row-Stop DMA Code (01) causes the DMA
Control Logic to stop DMA for the rest of the row when it
is written into the Row Buffer. It affects the display in the
same way as the End of Row Code (00).
Reverse Video - Characters following the code are
caused to appear with reverse video by activating
the Reverse Video output (RVV).
4.
Underline -
The End of Screen Code (10) activates VSP and holds it to
the end of the frame.
5,6.
S S
0 0
0 1
0
FUNCTION
End of Row
End of Row-Stop DMA
End of Screen
End of Screen-Stop DMA
The End of Screen-Stop DMA Code (11) causes the DMA
Control Logic to stop DMA for the rest of the frame when
it is written into the Row Buffer. It affects the display in
the same way as the End of Screen Code (10).
If the Stop DMA feature is not used, all characters after an
End of Row character are ignored, except for the End of
Screen character, which operates normally. All characters
after an End of Screen character are ignored.
Characters following the code are
caused to be highlighted by activating the Highlight output (HGLT).
Characters following the code are
caused to be underlined by activating the Light
Enable output (LTEN).
General Purpose - There are two additional 8275
outputs which act as general purpose, independently programmable field attributes. GPAO-1 are
active high outputs.
Field Attribute Code
MSB
LSB
10URGGBH
II
T IL-
HIGHLIGHT
~·---BLINK
GENERAL PURPOSE
REVERSE VIDEO
'---------UNDERLINE
L _____
~.- - - - - - -
H = 1 FOR HIGHLIGHTING
B = 1 FOR BLINKING
R = 1 FOR REVERSE VIDEO
U = 1 FOR UNDERLINE
GG = GPA1, GPAo
Note: If a Stop DMA character is not the last character in a burst or
row, DMA is not stopped until after the next character is
read. In this situation, a dummy character must be placed in
memory after the Stop DMA character.
11-131
8275
The 8275 can be programmed to provide visible or invisible
field attribute characters.
If the 8275 is programmed in the visible field attribute
mode, all field attributes will occupy a position on the
screen. They will appear as blanks caused by activation of
the Video Suppression output (VSP). The chosen visual
attributes are activated after this blanked character.
Each row buffer has a correspon;j'IIl~oF+F
are 16 characters by 7 bits in size.
N".
,.
'-'';:;-
When a field attribute is placed in the row h't\t( p.p
DMA, the buffer input controller recognizes it and; pX~;
the next character in the proper F IFa.
"'i'e
When a field attribute is placed in the Buffer Output Con·
troller during display, it causes the controller to immediately put a character from the FIFO on the Character Code
outputs (CCo..s). The chosen Visual Attributes are also
activated.
Since the FIFO is 16 characters long, no more than 16 field
attribute characters may be used per line in this mode.
If more are used, a bit in the status word is set and the first
characters in the F IFa are written over and lost.
ABC D E
F G H
J K L M
Nap 0 R S T~U7-:-V-;------
Note: Since the FIFO is 7 bits wide, the MSB of any characters put
1 234 5
in it are stripped off. Therefore, a Visual Attribute or Special
Code must not immediately follow a field attribute code. If
this situation does occur, the Visual Attribute or Special
Code will be treated as a normal display character.
6 7 8 9
Figure 22. Example of the Visible Field Attribute Mode
(Underline Attribute)
If the 8275 is programmed in the invisible field attribute
mode, the 8275 F IFa is activated.
ABC D E F G H I J K L M
NOPORSTUV
CCLK
1 234 5 6 7 8 9
DBO_7
CCO_6
Figure 24. Example of the Invisible Field Attribute
Mode (Underline Attribute)
DRQ _ _ _ _,
LCO_3
ill
ViR
AO
LAO_l
HRTe
VRle
HLGT
RVV
LTEN
cs
VSP
GPAO_l
lPEN
Figure 23. Block Diagram Showing FIFO Activation
Field and Character Attribute Interaction
Character Attribute Symbols are affected by the Reverse
Video (RRV) and General Purpose (GPAO-1) field attributes. They are not affected by Underline, Blink or Highlight field attributes; however, these characteristics can be
programmed individually for Character Attribute Symbols.
11-132
8275
Cursor Timing
Device Programming
The cursor location is determined by a cursor row register
and a character position register wh ich are loaded by command to the controller. The cursor can be programmed to
appear on the display as:
The 8275 has two programming register's, theG6rh.lfflulti
Register (GREG) and the Parameter Register (PREG). 'It,
also has a Status Register (SREG). The Command Register
can only be written into and the Status Registers can only
be read from. They are addressed as follows:
1.
2.
3.
4.
a
a
a
a
blinking underline
blinking reverse video block
non-blinking underline
non-blinking reverse video block
AO
The cursor blinking frequency is equal to the screen refresh
frequency divided by 16.
If a non-blinking reverse video cursor appears in a nonblinking reverse video field, the cursor will appear as a
normal video block.
If a non·blinking underline cursor appears in a non-blinking
underline field, the cursor will not be visible.
Light Pen Detection
A light pen consists of a micro switch and a tiny light
sensor. When the light pen is pressed against the CRT screen,
the micro switch enables the light sensor. When the raster
sweep reaches the Iight sensor, it triggers the light pen
output.
This has to be corrected in software.
REGISTER
Read
PREG
0
Write
PREG
1
Read
SREG
1
Write
CREG
The 8275 expects to receive a command and a sequence
of 0 to 4 parameters, depending on the command. If the
proper number of parameter bytes are not received before
another command is given, a status flag is set, indicating an
improper command.
Instruction Set
The 8275 instruction set consists of 8 commands.
COMMAND
If the output of the light pen is presented to the 8275
LPEN input, the row and character position coordinates are
stored in a pair of registers. These registers can be read on
command. A bit in the status word is set, indicating that
the light pen signal was detected. The LPEN input must be
a 0 to 1 transition for proper operation.
Note: Due to internal and external delays, the character position
coordinate will be off by at least three character positions.
OPERATION
0
NO. OF PARAMETER BYTES
Reset
Start Display
Stop Display
Read Light Pen
load Cursor
4
Enable Interrupt
Disable Interrupt
o
o
Preset Counters
o
o
o
2
2
In addition, the status of the 8275 (SREG) can be read by
the CPU at any time.
11-133
8275
'c.jl,'
1.
Reset Command:
Parameter - UUUU
DATA BUS
OPERATION AO
Command
DESCRIPTION
Reset Command
MSB
0
0
0
0
LSB
U U U U
0
a 0 a a
a a a 1
a a
a
0
Write
1
Write
0
Write
0
Screen Camp
Byte 2
V V R R R R R R
Write
0
Screen Camp
Byte 3
U U
U
M F
C C Z
Screen Camp
Byte 1
Parameters
Screen Camp
0
Write
Byte 4
0
0
S H H H H H H H
U
'"
",;
1
2
3
16
Parameter L
LLLL
L
l
L
Number of Lines per Character Row
NO. OF LINES/ROW
a a a a
a a a
a a
a
2
3
Spaced Rows
16
FUNCTIONS
a
i/j
Z Z Z
As parameters are written, the screen composition is
defined.
S
NUM~~il'Q~"
LINE
UNDERLINE
L L L L
Action - After the reset command is written, DMA requests stop, 8275 interrupts are disabled, and the VSP
output is used to blank the screen. HRTC and VRTC can·
tinue to run. HRTC and VRTC timing are random on
power·up.
Parameter - S
UnderlinEf'P!~9~.
Normal Rows
Spaced Rows
Parameter - M
M
Parameter - HHHHHHH
Horizontal Characters/Row
H H H H H H H
a
Mode 0 (Non·Offset)
NO. OF CHARACTERS
PER ROW
a a a a a a a
a 0 a a a a 1
a 0 a a a
a
1
2
3
Line Counter Mode
LINE COUNTER MODE
Mode 1 (Offset by 1 Count)
Parameter - F
Field Attribute Mode
F
FIELD ATTRIBUTE MODE
a
a
a
1
Transparent
Non-Transparent
0
1
a
80
1
0
a a
Undefined
1
Parameter - VV
Undefined
Parameter - CC
C C
o
a
Vertical Retrace Row Count
V V
NO. OF ROW COUNTS PER VRTC
a a
a
a
2
Parameter - RRRRRR
Cursor Format
CURSOR FORMAT
0
Blinking reverse video block
a
Blinking underline
Nonblinking reverse video block
Nonblinking underling
1
3
4
Parameter - ZZZZ
Horizontal Retrace Count
Z
NO. OF CHARACTER
COUNTS PER HRTC
NO. OF ROWS/FRAME
a 0 a 0 a a
a a a a 0 1
a 0 a 0
0
2
3
Z
Z
a a a a
a a a 1
a 0
a
Vertical Rows/Frame
R R R R R R
Z
2
4
6
1
32
1
1
64
Note: uuuu MSB determines blanking of top and bottom lines
(1 = blanked, = not blanked).
a
11·134
8275
2.
Start Display Command:
5.
Load Cursor Position:
DATA BUS
OPERATION AO
Command
Write
DESCRIPTION
MSB
Start Display
o
0
LSB
1
S
S S B
B
No parameters
0 0
0 0
0
0 1
0
0
Write
Write
Parameters
SSS
BURST SPACE COOE
0
1
0
1
0
0
7
15
23
31
39
47
55
0
Write
o
o
DESCRIPTION
Load Cursor
1
Char. Number
Row Number
(Char. Position in RoW'~c
{Row Numbed
0
Action - The 8275 is conditioned to place the next two
parameter bytes into the cursor position registers. Status
flags not affected.
NO. OF CHARACTER CLOCKS
BETWEEN DMA REQUESTS
S S S
OPERATION AO
Command
6.
Enable Interrupt Command:
DATA BUS
Command
IOPERATION AO
DESCRIPTION
MSB
I
Enable Interrupt
1
Write
1
0
LSB
1
0
0
0
0
0
No parameters
BB
B B
BURST COUNT CODE
Action - The interrupt enable status flag is set and inter·
rupts are enabled.
NO. OF DMA CYCLES PER
BURST
1
2
4
8
0 0
0
0
7.
Action - 8275 interrupts are enabled, DMA requests begin,
video is enabled, Interrupt Enable and Video Enable status
fl ags are set.
3.
I
OPERATION AO
Command
Stop Display Command:
OPERATION AO
I
I
Write
1
DESCRIPTION
DATA BUS
I
MSB
Disable Interrupt 1
1
LSB
0
0
0
0
0
0
No parameters
DATA BUS
I
Command
Disable Interrupt Command:
Wnte
1
DESCRIPTION
Stop Display
MSB
0
1
LSB
0
0
0
0
0
0
Action - Interrupts are disabled and the interrupt enable
status flag is reset.
No parameters
Action - Disables video, interrupts remain enabled, HRTC
and VRTC continue to run, Video Enable status flag is
reset, and the "Start Display" command must be given to
re·enable the display.
8.
Preset Counters Command:
DATA BUS
4.
Read Light Pen Command
DATA BUS
OPERATION Ao
DESCRIPTION
MSB
LSB
Command
Wnte
1
Read Light Pen
0
Parameters
Read
Read
0
Char. Number
Row Number
(Char. Position in Row)
0
1
1
0
0
0
0
Action - The 8275 is conditioned to supply the contents
of the light pen position registers in the next two read
cycles of the parameter register. Status flags are not af·
fected.
DESCRIPTION
MSB
L
Preset Counters
1
Write
1
1
LSB
1
0
0
0
0
0
No parameters
0
(Row Numbed
Note: Software correction of 1ight pen position is required.
Command
I OPERATION AO
Action - The internal timing counters are preset, corresponding to a screen display position at the top left corner.
Two character clocks are required for this operation. The
counters will remain in this state until any other command
is given.
This command is useful for system debug and synchroniza·
tion of clustered CRT displays on a single CPU.
11-135
8275
Status Flags
IC
DATA BUS
MSB
OlE IR LPICVEOU FO
Command
IE
-
LSB
-
(I nterrupt Enable) Set or reset by command. It
enables vertical retrace interrupt. It is automatically set by a "Start Display" command
and reset with the "Reset" command.
VE -
IR -
(Interrupt Request) This flag is set at the beginning of display of the last row of the frame if
the interrupt enable flag is set. It is reset after
a status read operation.
DU -
(Improper Command) ThiS: ffag, is
'\!:I'l a
command parameter string i~ 'tooIOOOOt-i~PQ:'j
short. The flag is automatically r~&~:;afte~ ,:)
status read.
'
(Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
(DMA Underrun) This flag is set whenever a
data underrun occurs during DMA transfers.
Upon detection of DU, the DMA operation is
stopped and the screen is blanked until after
the vertical retrace interval. This flag is reset
after a status read.
FO - (FIFO Overrun) This flag is set whenever the
FIFO is overrun. It is reset on a status read.
LP - This flag is set when the light pen input (LPEN)
is activated and the light pen registers have been
loaded. This flag is automatically reset after a
status read.
11-136
8275
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias . . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
'COMMENT: Stresses above those listed under "Absoll!te Maxi·
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at thes~ or '
any other conditions above those indicated in the operational sections of this specification is not implied.
D.C. CHARACTERISTICS
T A = O°C to 70°C; Vee = 5V ±5%
MIN.
MAX.
UNITS
VIL
SYMBOL
Input Low Voltage
PARAMETER
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+0.5V
V
VOL
Output Low Voltage
VOH
Output High Voltage
IlL
Input Load Current
±10
IOFL
Output Float Leakage
Icc
Vee Supply Current
0.45
V
V
2.4
TEST CONDITIONS
IOL = 2.2 mA
IOH = -400fJ.A
fJ.A
VIN = Vee to OV
±10
fJ.A
VOUT = Vee to OV
160
mA
CAPACITANCE
TA=25°C; Vee=GND=OV
SYMBOL
MAX.
UNITS
CIN
Input Capacitance
PARAMETER
MIN.
10
pF
fc=lMHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to Vss.
11·137
TEST CONDITIONS
T"'TPOINTS <"0X::==
CCLK
tKF
0.45
11-141
0.8
0.8
8278
PROGRAMMABLE KEYBOARD INTERFACE
• Simultaneous Keyboard and Display
Operations
• N·Key Rollover with Programmable
Error Mode on Multiple New Closures
• Interface Signals for Contact and
Capacitive Coupled Keyboards
• 16·Character 7·Segment Display
Interface
• 128·Key Scanning Logic
• Right or Left Entry Display RAM
• 10.7 msec Matrix Scan Time for 128
Keys and 6 MHz Clock
• Depress/Release Mode Programmable
• 8·Character Keyboard FJFO
• Interrupt Output on Key Entry
The Intel@ 8278 is a general purpose programmable keyboard and display interface device designed for use with 8-bit
microprocessors such the MDS-80 ™and MCS-85™_The keyboard portion can provide a scanned interface to
128-key contact or capacitive-coupled keyboards_ The keys are fully debounced with N-key rollover and
programmable error generation on multiple new key closures. Keyboard entries are stored in an
8-character FIFO with overrun status indication when more than 8 characters are entered. Key entries set
an interrupt request output to the master CPU.
The display portion of the 8278 provides a scanned display interface for LED, incandescent, and other
popular display technologies. Both numeric displays and simple indicators may be used. The 8278 has a
16X4 display RAM which can be loaded or interrogated by the CPU. Both right entry calculator and left entry typewriter display formats are possible. Both read and write of the display RAM can be done with autoincrement of the display RAM address.
PIN CONFIGURATION
RL
Vee
Xl
CLR
X2
B3
RESET
B2
NC
B,
cs
Bo
PIN NAMES
BLOCK DIAGRAM
DATA BUS
READ, WRITE STROBES
CHIP SELECT
CONTROL/DATA SELECT
OUTPUTS
RL
CLR
KCL
FREQ. REFERENCE INPUT
HIGH FREQUENCY OUTPUT
CLOCK
KEYBOARD RETURN LINE
CLEAR ERROR
KEY CLOCK
M.
M6-MO
83- BO
MATRIX SCAN LINES
DISPLAY OUTPUTS
M,
ERROR
IRQ
HVS
SYNC
M3
BP
ERROR SIGNAL
INTERRUPT REQUEST
HYSTERESIS
TONE ENABLE
Do
M2
D,
M,
KCL
iVA
02
Mo
03
Voo
0,
NC
0,
ERROR
D.
IRQ
0,
HYS
SCAN
RESET INPUT
,.-L-,
M.
DATA
BUS
x,
GND
TO
DISPLAY
DIGITS
X2
+5
-
PWR_
GNO-
11-142
INTERNAL
BUS
8278
PIN DESCRIPTION
>'.',"
The 8278 is packaged in a 40-pin DIP. The following is a
brief functional description of each pin.
Signal
Description
Signal
Pin No.
00-07
12-19
Three-state. bi-directional data bus
lines used to transfer data and commands between the CPU and the
8278.
10
Write strobe which enables the master CPU to write data and commands between the CPU and the
8278.
8
Read strobe which enables the master CPU to read data and status from
the 8278 internal registers.
6
Chip select input used to enable
reading and writing to the 8278.
9
Address input used by the CPU to
indicate control or data.
Ao
IRQ
Mo-Ms
HYS
KCL
SYNC
Bo-B3
24
Error signal. This line is high whenever two new key closures are detected during a single scan or when
too many characters are entered
into the keyboard FIFO. It is reset by
a system RESET pulse or by a "1"
input on the CLR pin or by the
CLEAR ERROR command.
CLR
39
Input used to clear an ERROR condition in the 8278.
BP
21
Tone enable output. This line is high
for 10ms following a valid key
closure; it is set high and remains
high during an ERROR condition.
Vcc,Voo
40,26
+5 volt power input: +5V
20,7
Signal ground.
4
A low signal on this pin resets the
8278.
GND
2,3
Inputs for crystal, L-C or external
timing signal to determine internal
oscillator frequency.
PRINCIPLES OF OPERATION
23
Interrupt Request Output to the
master CPU. In the keyboard mode
the IRQ line goes low with each
FIFO read and returns high if there
is still information in the FIFO or an
ERROR has occurred.
27-33
Matrix scan outputs. These outputs control a decoder which scans
the key matrix columns and the 16
display digits. Also, the Matrix scan
outputs are used to multiplex the
return lines from the key matrix.
Input from the multiplexer which indicates whether the key currently
being scanned is closed.
RL
-L-
Description
Pin No.
ERROR
22
34
11
35-38
Hysteresis output to the analog detector. (Capacitive keyboard configuration>. A "0" means the key currently being scanned has already
been recorded.
± 10%.
The following is a description of the major elements of the
Programmable Keyboard/Display interface device. Refer
to the block diagram in Figure 1.
110 Control and Data Buffers
The I/O control section uses the CS, Ao, RD, and WR lines
to control data flow to and from the various internal
registers and buffers (see Table 1>' All data flow to and
from the 8278 is enabled by CS. The 8-bits of information
being transferred by the CPU is identified by Ao. A logic
one means information is command or status. A logic zero
means the information is data. RD and WR determine the
direction of data flow through the Data Bus Buffer 8279 is a general purpose programmable keyboard and display 1/0 interface device desi.gned for use with
Intel@> microprocessors. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The
keyboard portion will also interface to an array of sensors or a strobed interface keyboard, such as the hall effect and
ferrite variety. Key depressions can be 2-key lockout or N-key rollover. Keyboard entries are debounced and strobed in
an 8-character FIFO. If more than 8 characters are entered, overrun status is set. Key entries set the interrupt output
line to the CPU.
The display portion provides a scanned display interface for LED, incandescent, and other popular display
technologies. 80th numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279
has 16X8 display RAM which can be organized into dual 16X4. The RAM can be loaded or interrogated by the CPU. 80th
right entry, calculator and left entry typewriter disp~ay formats are possible. 80th read and write of the display RAM
can be done with auto-increment of the display RAM address.
PIN CONFIGURATION
lOGIC SYMBOL
PIN NAMES
IRQ
RLo 7
DATA
SHIFT
SlJ
RL,
DB!} I
elK
(,'0
SL,
CHIP SELECT
I
READ INPUT
WRITE INPUT
BUFFER ADDRESS
INTERRUPT REaUEST 'OUTPUT
SCAN liNES
A.
IRO
WR
OUT 81
DBo
OUT 82
OUT 83
DB,
our
A1
SL03
Alo1
SHIFT
SHIFT
I
RETURN LINES
I
SHIFT INPUT
I
0
CONTROL/STROBE INPUT
DlSf>LAY IAI 'OUTPUTS
'OUT 8(13
0
DISPLAY IBI 'OUTPUTS
0
BLANK DISPLAY 'OUTPUT
CNTLISTB
viR
INTERFACE
SLO-J
SCAN
AD
--
OUT A3
iiil
DB,
~ KEY DATA
CPU
CS
CNTlISTB
OUT A01
OUT A2
DB,
1----
RD
I
I
SLo
BUS
RESE r INPUT
RESET
SC,
OAT A 6US (BI DIRECTIONAL)
CLOCK INPUT
OUT AO_3
RESET
DISPLAY
Os
CLK
Vss
11-152
OUT 80-.1
DATA
827918279-5
HARDWARE DESCRIPTION
SHIFT
The 8279 is packaged in a 40 pin DIP. The following is
a functional description of each pin.
No. Of
Pins
Designation
Function
8
DBo-DB7
ClK
RESET
CS
Ao
2
RD, WR
IRQ
2
4
8
V ss, Vee
Slo-Sl3
Rlo-Rl7
No. Of
Pins
Bi-directional data bus. All data
and commands between the
CPU and the 8279 are transmitted on these lines.
Clock from system used to generate internal timing.
A high signal on ihis pin resets
the 8279, After being reset the
8279 is placed in the following
mode:
1) 16 8-bit character display
-left entry,
2) Encoded scan keyboard-2
key lockout.
Along with this the program
clock prescaler is set to 31.
Chip Select. A low on this pin
enables the interface functions
to receive or transmit.
Buffer Address. A high on this
line indicates the signals in or
out are interpreted as a command or status. A low indicates
that they are data.
Input/Output read and write.
These signals enable the data
buffers to either send data to
the external bus or receive it
from the external bus.
Interrupt Request. I n a keyboard
mode, the interrupt line is high
when there is data in the FI FO/
Sensor RAM. The interrupt line
goes low with each FIFO/
Sensor RAM read and retu rns
high if there is still information in the RAM. In a sensor
mode, the interrupt line goes
high whenever a change in a
sensor is detected.
Ground and power supply pins.
Scan lines which are used to
scan the key switch or sensor
matrix and the display digits.
These lines can be either encoded (1 of 16) or decoded (1 of
4).
Return line inputs which are
connected to the scan lines
through the keys or sensor
switches. They have active internal pullups to keep them
high until a switch closure pulls
one low. They also serve as an
8-bit input in the Strobed Input
mode.
The shift input status is stored
along with the key position on
key closure in the Scanned
Designation Function
Keyboard modes. It has an
active internal pullup to keep it
high until a switch closure pulls
it low.
CNTLlSTB
For keyboard modes this line is
used as a control input and
stored like status on a key closure. The line is also the strobe
line that enters the data into the
FIFO in the Strobed Input mode.
(Rising Edge). It has an active
internal pullup to keep it high
until a switch closure pulls it
low.
4
4
OUT Ao-OUT A3 These two ports are the outputs
OUT Bo-OUT B3 for the 16 x 4 display refresh
registers. The data from these
outputs is synchronized to the
scan lines (Slo-Sl3) for multiplexed digit displays. The two 4
bit ports may be blanked independently. Thesetwo ports may
also be considered as one 8 bit
port.
BD
Blank Display. This output is
used to blank the display during
digit switching or by a display
blanking command.
PRINCIPLES OF OPERATION
The following is a description of the major elements of the
8279 Programmable Keyboard/Display interface device.
Refer to the block diagram in Figure 1.
110 Control and Data Buffers
The I/O control section uses the CS, Ao, RD and WR lines
to control data flow to and from the various internal
registers and buffers. All data flow to and from the 8279 is
enabled by CS. The character of the information, given or
desired by the CPU, is identified by Ao. A logic one
means the information is a command or status. A logic
zero means the information is data. RD and WR determine
the direction of data flow through the Data Buffers. The
Data Buffers are bi-directional buffers that connect the
internal bus to the external bus. When the chip is not
selected (CS ~ 1), the device~e i!l.a high impedance
state. The drivers input during WR. CS and output during
RD .CS.
Control and Timing Registers and Timing Control
These registers store the keyboard and display modes and
other operating conditions programmed by the CPU. The
modes are programmed by presenting the 'proper
command on the data lines with Ao = 1 and then sending
a WR. The command is latched on the rising edge of WR.
11-153
U2f9/U279·5
FUNCTIONAL DESCRIPTION
Since data input and display are an integral part of many
microprocessor designs, the system designer needs an
interface that can control these functions without placing
a large load on the CPU. The 8279 provides this function
for 8-bit microprocessors.
The 8279 has two sections: keyboard and display. The
keyboard section can interface to regular typewriter style
keyboards or random toggle or thumb switches. The
display section drives alphanumeric displays or a bank of
indicator lights. Thus the CPU is relieved from scanning
the keyboard or refreshing the display.
The 8279 is designed to directly connect to the
microprocessor bus. The CPU can program all operating
modes for the 8279. These modes include:
• Scanned Sensor Matrix - with encoded (8 x8
switches) or decoded (4 x 8 matrix switches) scan fines.
Key status (open or closed) stored in RAM addressable
by CPU.
• Strobed Input -- Data on return lines during control
line strobe is transferred to' FIFO.
Output Modes
• 8 or 16 character multiplexed displays that can be
organized as dual 4-b'it or single 8-bit.
• Right entry or left entry display formats.
Other features of the 8279 include:
• Mode programming from the CPU.
Input Modes
• Clock Prescaler
• Scanned Keyboard with encoded (8 x 8 key
keyboard) or decoded (4 x 8 key keyboard) scan lines.
A key depression generates a 6·bit encoding of key
position. Position and shift and control status are
stored in the FIFO. Keys are automatically debounced
with 2·key lockout or N·key rollover.
• Interrupt output to signal CPU when there is keyboard
or sensor data available.
elK
DISPLAY
ADDRESS
REGISTERS
• An 8 byte FIFO to store keyboard information.
• 16 byte internal Display RAM for display refresh. This
RAM can also be read by the CPU.
IRO
DBO·7
RESET
KEYBOARD
oeBOUNCE
AND
16 x 8
DISPLAY
RAM
CONTROL
TIMING
AND
CONTROL
OUT AO.3
OUT BG.3
SlO·3
11·154
RLO-7
CNT LlSTB
8279/8279·5
The command is then decoded and the appropriate
function is set. The timing control contains the basic
timing counter chain. The first counter is a + N prescaler
that can be programmed to yield an internal frequency
of 100 kHz which gives a 5.1 ms keyboard scan time and
a 10.3 ms debounce time. The other counters divide
down the basic internal frequency to provide the proper
key scan, row scan, keyboard matrix scan, and display
scan times.
". ;~
."'"
SOFTWARE OPERATION
8279 commands
.',
Keyboard/Display Mode Set
MSB
Scan Counter
The scan counter has two modes. In the encoded mode,
the counter provides a binary count that must be
externally decoded to provide the scan lines for the
keyboard and display. In the decoded mode, the scan
counter decodes the least significant 2 bits and provides a
decoded 1 of 4 scan. Note than when the keyboard is in
decoded scan, so is the display. This means that only the
first 4 characters in the Display RAM are displayed.
In the encoded mode, the scan lines are active high
outputs. In the decoded mode, the scan lines are active
low outputs.
Code:
The 8 return lines are buffered and latched by the Return
Buffers. In the keyboard mode, these lines are scanned,
looking for key closures in that row. If the debounce
circuit detects a closed switch, it waits about 10 msec to
check if the switch remains closed. If it does, the address
of the switch in the matrix plus the status of SHIFT and
CONTROL are transferred to the FIFO. In the scanned
Sensor Matrix modes, the contents of the return lines is
directly transferred to the corresponding row of the
Sensor RAM (FIFO) each key scan time. In Strobed Input
mode, the contents of the return lines are transferred to
the FIFO on the rising edge of the CNTLlSTB line pulse.
Where DD is the Display Mode and KKK is the Keyboard
Mode.
DO
o
0
8 8-bit character display 16 8-bit character display -
o
o
8 8-bit character display -
Display Address Registers and Display RAM
The Display Address Registers hold the address of the
word currently being written or read by the CPU and the
two 4-bit nibbles being displayed. The read/write
addresses are programmed by CPU command. They also
can be set to auto increment after each read or write. The
Display RAM can be directly read by the CPU after the
correct mode and address is set. The addresses for the A
and B nibbles are automatically updated by the 8279 to
match data entry by the CPU. The A and B nibbles can be
entered independently or as one word, according to the
mode that is set by the CPU. Data entry to the display can
be set to either left or right entry. See Interface
Considerations for details.
Left entry
Left entry'
Right entry
Right entry
For description of right and left entry, see Interface
Considerations. Note that when decoded scan is set in
keyboard mode, the display is reduced to 4 characters
independent of display mode set.
KKK
0 0
0
Encoded Scan Keyboard -
0 0
1
Decoded Scan Keyboard - 2-Key Lockout
0
0
Encoded Scan Keyboard -
N-Key Rollover
0
1 1
Decoded Scan Keyboard -
N-Key ROllover
0 0
Encoded Scan Sensor Matrix
0
Decoded Scan Sensor Matrix
FIFO/Sensor RAM and Status
This block is a dual function 8 x 8 RAM. In Keyboard or
Strobed Input modes, it is a FIFO. Each new entry is
written into successive RAM positions and each is then
read in order of entry. FIFO status keeps track of the
number of characters in the FIFO and whether it is full or
empty. Too many reads or writes will be recognized as an
error. The status can be read by an RD with CS low and
Ao high. The status logic also provides an IRQ signal
when the FIFO is not empty. In Scanned Sensor Matrix
mode, the memory is a Sensor RAM. Each row of the
Sensor RAM is loaded with the status of the corresponding row of sensor in the sensor matrix. In this mode, IRQ is
high if a change in a sensor is detected.
LSB
101010iDIDIKIKIKI
16 8-bit character display -
Return Buffers and Keyboard Debounce
and Control
-","
The following commands program the 8279 operating"{
modes. The commands are sent on the Data Bus with Cs
low and Ao high and are loaded to the 8279 on the rising
edge of WR.
0
2 Key Lockout·
Strobed Input, Encoded Display Scan
Strobed Input, Decoded Display Scan
Program Clock
All timing and multiplexing Signals for the 8279 are
generated by an internal prescaler. This prescaler
divides the external clock (pin 3) by a programmable
integer. Bits PPPPP determine the value of this integer
which ranges from 2 to 31. ChOOSing a divisor that yields
100 kHz will give the specified scan and debounce
times. For instance, if Pin 3 of the 8279 is being clocked
by a 2 MHz Signal, PPPPP should be set to 10100 to
divide the clock by 20 to yield the proper 100 kHz operating frequency.
Read FIFO/Sensor RAM
Code:
I 011 I0 I All X IA IA IA I
X= Don't Care
The CPU sets up the 8279 for a read of the FIFO/Sensor
RAM by first writing this command. In the Scan Key'Default after reset.
11-155
8279/8279·5
board Mode, the Auto-Increment flag (AI) and the RAM
address bits (AAA) are irrelevant. The 8279 will automatically drive the data bus for each subsequent read (Ao= 0)
in the same sequence in which the data first entered the
FIFO. All subsequent reads will be from the FIFO until
another command is issued.
Clear
The Co bits are available in this commaRd t<>.
rows of the Display RAM to a selectable bl8fj,l
DECODER
16
BLANK
t~ISPlAY
3 lSB'
~
ADDRESSES
(DECODED)
DISPLAY
4
/
CHARACTERS
DATA
DISPLAY
• Do not drive the keyboard decoder with the MSB of the scan lines.
11-159
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature ...•.•....•••. O°C to 70°C
Storage Temperature ••.•....•..•• -65°C to 125°C
Voltage on any Pin with
Respect to Ground ••..•.•••••..• -0.5V to +7V
Power Dissipation •••...•••••••....•...• 1 Watt
D.C. CHARACTERISTICS
TA
= o·c to 70·C, Vss = OV, Note 1
Symbol
Parameter
Min.
Max.
Unit
VIL1
Input Low Voltage for
Return Lines
-0.5
1.4
V
VIl2
Input Low Voltage for All Others
-0.5
0.8
V
Test Conditions
V
Input High Voltage for
Return Lines
2.2
VIH2
Input High Voltage for All Others
2.0
VOL
Output Low Voltage
VOH
Output High Voltage on Interrupt
Line
Illl
Input Current on Shift, Control and
Return Lines
+10
-100
jJ.A
jJ.A
VIN = Vee
VIN = OV
IIl2
Input Leakage Current on All Others
±10
jJ.A
VIN = Vee to OV
IOFl
Output Float Leakage
±10
jJ.A
VOUT = Vee to OV
Icc
Power Supply Current
120
rnA
VIHI
V
0.45
3.5
V
Note 2
V
Note 3
Notes:
1. 8279, Vee = +5V ±5%; 8279·5, Vee = +5V ±10%.
2. 8279, IOl = 1.6mA; 8279·5, IOl = 2.2mA.
3. 8279, IOH = -100jlA; 8279-5, IOH = -400jlA.
CAPACITANCE
SYMBOL
TEST
Cin
Input Capacitance
Cout
Output Capacitance
MAX.
UNIT
5
10
pF
Vin=Vee
20
pF
Vout=Vee
10
11-160
TEST CONDITIONS
TYP.
8219/ts;U~·~
A.C. CHARACTERISTICS
TA = O°C to 70°C, Vss = OV, (Note 1)
Bus Parameters
Read Cycle·
8279-5
8279
Symbol
Parameter
Max.
Min.
tAR
Address Stable Before READ
tRA
Address Hold Time for READ
tRR
READ Pulse Width
Min.
Max.
Unit
ns
0
50
5
0
ns
420
250
ns
tRDI21
Data Delay from READ
300
150
ns
tADI21
Address to Data Valid
450
250
ns
tDF
READ to Data Floating
tRCY
Read Cycle Ti me
100
10
10
1
ns
100
1
J.l.s
Write Cycle:
8279
Symbol
Parameter
Min.
8279-5
Max.
Min.
Max.
Unit
tAW
Address Stable Before WR IT E
50
0
ns
tWA
Address Hold Time for WR ITE
20
0
ns
tww
WR ITE Pulse Width
400
250
ns
tDW
Data Set Up Time for WR ITE
300
150
ns
tWD
Data Hold Time for WR ITE
40
0
ns
Notes:
1. 8279, VCC = +5V ±5%; 8279-5, VCC = +5V ±10%.
2. 8279, CL = 100pF; 8279-5, CL = 150pF.
Other Timings:
8279
Symbol
8279·5
Min.
tcPW
Clock Pulse Width
230
120
nsec
tCY
Clock Period
500
320
nsec
Keyboard Scan Time;
Keyboard Debounce Time:
Key Scan Time:
Display Scan Time:
Max.
Min.
Digit·on Time:
Blanking Time:
Internal Clock Cycle:
5.1 msec
10.::: msec
80 J.l.sec
10.3 msec
Input Waveforms For A.C. Tests
.'=X >
2.0
2.0
TEST POINT, /-::::
0.8
0.8
0.45
t1-161
)c
Max.
I
Parameter
Unit
480 J.l.sec
160 J.l.sec
10 J.l.sec
WAVEFORMS
Read Operation
AO.
(SYSTEM'S
CS
ADDR ESS BUS)
---tAR ----+-1~·~----------tRCy
~--------------------
---+-------_1
1~----tRR-----'1
(READ CONTROL)
1~----tAD
- - - -...1
Write Operation
(SYSTEM'S
ADDRESS BUS)
o - - - - - tww- - - -....
(WRITE CONTROL)
DATA BUS
DATA
(INPUTl _ _ _ _ _
M_A_Y_C_H_A_N_G_E_ _ _
~ ----DATA VALlD---iXJ
....,JI
-
Clock Input
11·162
DATA
:,,"-_____M_A_Y_CH_A_N_G_E_ _ _ _ ___
8279 SCAN TIMING
SCAN WAVEFORMS
So
S,
ENCODED
SCAN
I
S,
I
\
'-'--
I
S,
s0---V
S,
DECODED
SCAN
S,
S,
V
V
V
V
V
V
V
V
V
V
VV
V
V
V
DISPLAY WAVEFORMS
1 - - - - - - - 640 ",s= 64 t c v - - - - - - - i
Ao-A,
ACTIVE HIGH
A(O)
BLANK
CODE-
ASSUME INTERNAL FREQUENCY=100 kHz
SOtcv=1~
A(1)
·BLANK CODe IS EITHER ALL
D's OR ALL 1'. OR 20 HEX
80-B3
ACTIVE HIGH
B(1)
490 ...
BD
NOTE: SHOWN IS ENCODED SCAN LEFT ENTRY
8,rS3 ARE NOT SHOWN BUT THEY ARE SIMPLY 81 DIVIDED BY 2 AND 4
11-163
BLANK
CODE·
8291
GPIB TALKER/LISTENER
• Designed to Interface Microprocessors
(e.g., 8080, 8085, 8086, 8048) to an
IEEE Standard 488 Digital Interface
Bus
• 1 - 8 MHz Clock Range
• 16 Registers (8 Read, 8 Write), 2 for
Data Transfer, the Rest for Interface
Function Control, Status, etc.
• Programmable Data Transfer Rate
• Complete Source and Acceptor
Handshake
• Directly Interfaces to External NonInverting Transceivers for Connection
to the GPIB
• Complete Talker and Listener
Functions with Extended Addressing
• Provides Three Addressing Modes,
Allowing the Chip to be Addressed
Either as a Major or a Minor Talker/
Listener with Primary or Secondary
Addressing
• Service Request, Parallel Poll, Device
Clear, Device Trigger, Remote/Local
Functions
• DMA Handshake Provision Allows for
Bus Transfers without CPU Intervention
• Selectable Interrupts
• On-Chip Primary and Secondary
Address Recognition
• Automatic Handling of AddreSSing and
Handshake Protocol
• Provision for Software Implementation
of Additional Features
• Trigger Output Pin
• On-Chip EOS (End of Sequence)
Message Recognition Facilitates
Handling of Multi-Byte Transfers
The 8291 GPIB Talker/Listener is a microprocessor-controlled chip designed to interface microprocessors (e.g., 8048,
8080,8085,8086) to an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface
functions except for the controller.
BLOCK DIAGRAM
PIN CONFIGURATION
18291
I
I
GPIBOATA
INTERFACE
FUNCTIONS ~="=~
SH
GPIB CONTROL
I
AH
TE
LE
SR
RL
11-164
I
I
I
TiRCONTROL
TO NON.INVERTING
BUS TRANSCEIVERS
8291
..'·n
PIN DESCRIPTION
Symbol
1/0
Pin No.
00-07
1/0
12-19
Oata bus port, to be connected
to microprocessor data bus.
21-23
Register select inputs, to be connected to three non-multiplexed
microprocessor address bus
lines. Select which of the 8 internal read (write) registers will
be read from (written into) with
the execution of RO (WR).
RSo-RS2
8
9
WR
INT (INT)
OMA REO
0
0
OMA ACK
Function
24
Interface clear; GPIB command
line. Places the interface functions in a known quiescent state.
27
Service request; GPIB command
line. Indicates the need for
attention and requests an interruption of the current sequence
of events on the GPIB.
25
Remote enable; GPIB command
line. Selects (in conjunction with
other messages) remote or local
control of the device.
39
End or identify; GPIB command
line. Indicates the end of a
multiple byte transfer sequence
or, in conjunction with ATN,
addresses the device during a
polling sequence.
11
Interrupt request to the microprocessor, set high for request
and cleared when the appropriate register is accessed by the
CPU. May be software configured to be active low.
3
External clock input, used for
internal time delays generator.
May be any speed in 1·8 MHz
range.
RESET
4
Reset input. When high, forces
the device into an "Idle" (initialization) mode. The device wi II remain at "Idle" until released by
the microprocessor.
110
36
1/0
o
OMA request, normally low, set
high to indicate byte output or
byte input, in OMA mode; reset
by OMA ACK.
CLOCK
OAV
Not ready for data; GPtij hand- •
shake control line. Indicates the'"
condition of readiness of de~
vice(s) connected to the bus to
accept data.
Read strobe. When low, selected
register contents are read by the
CPU.
Write strobe. When low, data is
written into the selected register.
28-35
37
':;JR,:
Attention; GPIB command line.
Specifies how data on DIO lines
are to be interpreted.
Trigger output, normally low;
generates a triggering pulse corresponding to the GET command.
110
1/0
.
26
5
i5i0,-i5i0a
NRFO
;i
Function'
Chip select. When low, enables
reading from or writing into the
register selected by RSo-RS2.
OMA acknowledge. When low,
resets DMA REO and selects
data inldata out register for
DMA data transfer (actual transfer done by RO/WR pulse).
0
Pin No.
Not data accepted; GPIB handshake control line. Indicates the
condition of acceptance of data
by the device(s) connected to
the bus.
&
TRIG
1/0
38
10
6
Symbol
1/0
8-bit GPIB data port, used for
bidirectional data byte transfer
between 8291 and GPIB via noninverting external line transceivers.
T/R1
o
T/R2
o
2
Vee
P.S.
40
External transceivers control
line. Set high to indicate output
datalsignals on the OIO,-OIOa
and OAV lines and input signals
on the NRFO and NOAC lines
(active source handshake). Set
low to indicate input datal
signals on the OIO,-OIOa and
DAV lines and output signals on
the NRFO and NOAC lines (active acceptor handshake).
External transceivers control
line. Set high to indicate output
signals on the EOI line. Set low
to indicate expected input signal
on the EOI line during parallel
poll.
Positive power supply (5V ±
10%).
GND
P.S.
20
Potential ground circuit.
Oata valid; GPIB handshake
control line. Indicates the availability and validity of information on the 010 lines.
Note: all signals on the 8291 pins are specified with positive logiC.
However, IEEE 488 specifies negative logic on ils 16 signal lines.
11-165
.">
.
8291
8291 SYSTEM DIAGRAM
r- - -
I
8251
ORO
r--~'---.., T/R2
1---"'=----1
8291
t--'...:;...--.,
- -•
I CON.:'RMO~LER I
L ~02~N~L)_ ..
OACK
GPIB
INTERFACE
T/R1
THE GENERAL PURPOSE INTERFACE
BUS (GPIB)
The General Purpose Interface Bus (GPIB) is defined in
the IEEE Standard 488-1975 "Digital Interface for
Programmable Instrumentation." Although a knowledge
of this standard is assumed, Figure 1 provides the bus
structure for quick reference. Also, Tables 1 and 2
reference the interface state mnemonics and the interface'
messages respectively. Modified state diagrams for the
8291 are presented in Appendix A.
ABLE TO
TALK, LISTEN,
AND
CONTROL
r--
I
f-
LISTEN
(e.g. digital
mloltlmeterl
(r-t-
The 8291 architecture includes 16 registers. Eight of these
registers may be written into by the microprocessor. The
other eight registers may be read by the microprocessor.
One each of these read and write registers is for direct data
transfers. The rest of the write registers control the various
features of the chip, while the rest of the read registers
provide the microprocessor with a monitor of GPI B states,
various bus conditions, and device conditions.
DATA BYTE
TRANSFER
CONTROL
DEVICE C
ONLY ABLE
TO LISTEN
I
l-
(e.g. signal
GENERAL
INTERFACE
generator)
The 8291 handles communication between a microprocessor controlled device and the GPIB. Its capabilities include data transfer, handshake protocol, talkerllistener
addressing procedures, device clearing and triggering,
service request, and both serial and parallel polling
schemes. In most procedures, it does not disturb the
microprocessor unless a byte Is waiting On input or a
byte sent On output (output buffer empty).
DATA BUS
DEVICE B
TALK AND
The 8291 is a microprocessor controlled device designed to interface microprocessors e.g., 8048, 8080,
8085,8086 to the GPIB. It implements all of the interface
functions defined in the IEEE 488 Standard. If an implementation of the Standard's Controller function is
desired, it can be connected with an Intel@ 8292 to form
a complete interface.
I
tllf
(e.g. calculator)
ABLE TO
GENERAL DESCRIPTION
fffff
OEVICE A
MANAGEMENT
(
DEVICE D
ONLY ABLE
TO TALK
I
l-
(e.g. counter)
.....=}DI01. .. 8
DAV
NRFD
NDAC
IFC
ATN
SRO
REN
EOI
Figure 1. Interface Capabilities and Bus Structure_
11-166
8291
GPIB Addressing
Each device connected to the GPI B must have at least one
address whereby the controller device in charge of the bus
can configure it to talk, listen, or send status. An 8291
implementation of the GPIB offers the user three
addressing modes from which the device can be initialized
for each application. The first of these modes allows for
the device to have two separate primary addresses. The
second mode allows the user to implement a single
talker/listener with a two byte address (primary address +
secondary address). The third mode again allows fortwo
distinct addresses but in this instance, they can each have
a two-byte address. However, this mode requires that the
secondary addresses be passed to the microprocessorfor·
verification. These three addressing schemes are described in more detail in the discussion of the Address
registers.
TABLE 1.
IEEE 488 INTERFACE STATE MNEMONICS
Mnemonic
State Represented
Mnemonic
State Represented
ACDS
ACRS
AIDS
ANRS
APRS
AWNS
Accept Data State
Acceptor Ready State
Acceptor Idle State
Acceptor Not Ready State
Affirmative Poll Response State
Acceptor Wait for New Cycle State
PACS
PPAS
PPIS
PPSS
PUCS
Parallel
Parallel
Parallel
Parallel
Parallel
REMS
RWLS
Remote State
Remote With Lockout State
CADS
CAWS
CIDS
CPPS
CPWS
CSBS
CSNS
CSRS
CSWS
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
SACS
SDYS
SGNS
SIAS
SIDS
SIIS
SINS
SIWS
SNAS
SPAS
SPIS
SPMS
SRAS
SRIS
SRNS
SRQS
STRS
SWNS
System Control Active State
Source Delay State
Source Generate State
System Control Interface Clear Active State
Source Idle State
System Control Interface Clear Idle State
System Control Interface Clear Not Active State
Source Idle Wait State
System Control Not Active State
Serial Poll Active State
Serial Poll Idle State
Serial Poll Mode State
System Control Remote Enable Active State
System Control Remote Enable Idle State
System Control Remote Enable Not Active State
Service Req uest State
Source Transfer State
Source Wait for New Cycle State
TACS
TADS
TIDS
TPIS
Talker
Talker
Talker
Talker
------------------------,
CACS
Controller Active State
I
:
I
I
I
I
I
I
:
I
I
~ ~T~~ _
Addressed State
Active Wait State
Idle State
Parallel Poll State
Parallel Poll Wait State
Standby State
Service Not Requested State
Service Requested State
Synchronous Wait State
~~tl~.o~r:...T~.::.s~r~t~t~ ______
DCAS
DCIS
DTAS
DTIS
Device
Device
Device
Device
LACS
LADS
LIDS
LOCS
LPAS
LPIS
LWLS
Listener Active State
Listener Addressed State
Listener Idle State
Local State
Listener Primary Addressed State
Listener Primary Idle State
Local With Lockout State
NPRS
Negative Poll Response State
I
I
I
I
I
I
:
I
I
J
Clear Active State
Clear Idle State
Trigger Active State
Trigger Idle State
- - - - - - The Controller function is implemented on the Intel® 8292.
11·167
Poll
Poll
Poll
Poll
Poll
Addressed to Configure State
Active State
Idle State
Standby State
Unaddressed to Configure State
Active State
Addressed State
Idle State
Primary Idle State
8291
TABLE 2.
IEEE 488 INTERFACE MESSAGE REFERENCE LIST
Mnemonic
Message
Interface Function(s)
LOCAL MESSAGES RECEIVED (By Interface Functions)
• gts
ist
Ion
Ipe
nba
go to standby
individual status
listen only
local poll enable
new byte available
C
PP
L, LE
PP
SH
pon
rdy
• rpp
* rse
rsv
power on
ready
request parallel poll
request system control
request service
SH,AH,T,TE,L,LE,SR,RL,PP,C
AH
C
C
SR
rtl
sic
• sre
·tca
·tcs
ton
retu rn to local
send interface clear
send remote enable
take control asynchronously
take control synchronously
talk only
RL
C
C
C
AH,C
T, TE
*
REMOTE MESSAGES RECEIVED
ATN
DAB
DAC
DAV
DCL
Attention
Data Byte
Data Accepted
Data Valid
Device Clear
SH,AH,T,TE,L,LE,PP,C
(Via L, LE)
SH
AH
DC
END
GET
GTL
lOY
IFC
End
Group Execute Trigger
Go to Local
Identify
I nterface Clear
(via L, LE)
DT
RL
L,LE,PP
T,TE,L,LE,C
LLO
MLA
MSA
MTA
OSA
Local Lockout
My Listen Address
My Secondary Address
My Talk Address
Other Secondary Address
RL
L,LE,RL,T,TE
TE.LE.RL
T,TE,L,LE
TE
OTA
PCG
tPPc
t [PPD)
t[PPE]
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Disable
Parallel Poll Enable
T, TE
TE,LE,PP
PP
PP
PP
• PPRN
tPPu
REN
RFD
RQS
Parallel Poll Response N
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service
(via C)
PP
RL
SH
(via L, LE)
[SOC]
SPD
SPE
'SQR
STB
Select Device Clear
Serial Poll Disable
Serial Poll Enable
Service Request
Status Byte
DC
T, TE
T, TE
(via C)
(via L, LE)
• TCT or [TCT]
UNL
Take Control
Unlisten
C
L, LE
'These messages are handled only by Intel's 8292.
tUndefined commands which may be passed to the microprocessor.
11·168
Mnemonic
REMOTE MESSAGES SENT
ATN
DAB
DAC
DAV
DCl
Attention
Data Byte
Data Accepted
Data Valid
Device Clear
C
(via T, TE)
AH
SH
(via C)
END
GET
GTl
lOY
IFC
End
Group Execute Trigger
Go to local
Identify
Interface Clear
(via T)
(via C)
(via C)
C
C
llO
MlA or [MlA]
MSA or [MSA]
MTA or [MTA]
OSA
local lockout
My Listen Address
My Secondary Address
My Talk Address
Other Secondary Address
(via
(via
(via
(via
(via
C)
C)
C)
C)
C)
OTA
PCG
PPC
[PPD]
[PPE]
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Disable
Parallel Poll Enable
(via
(via
(via
(via
(via
C)
C)
C)
C)
C)
PPRN
PPU
REN
RFD
ROS
Parallel Poll Response N
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service
PP
(via C)
C
AH
T, TE
[SOC]
SPD
SPE
SRO
STB
Selected Device Clear
Serial Poll Disable
Serial Poll Enable
Service Request
Status Byte
(via
(via
(via
SR
(via
TCT
UNl
Take Control
Unlisten
(via C)
(via C)
""All Controller messages must be sent via Intel's 8292.
11·169
C)
C)
C)
T, TE)
8291
8291 Registers
A bit-by-bit map of the 16 registers on the 8291 is
presented in Table 3. A more detailed explanation of each
of these registers and their functions follows. The access
of these registers by the microprocessor is accomplished
by using the es, RD, WR, and RSo-RS2 pins.
CS
RD
WR
RSo-RS2
All Read Registers
Resister
0
0
1
All Write Registers
0
1
0
eee
eee
X
X
XXX
Don't Care
TABLE 3. 8291 REGISTERS
READ REGISTERS
RS2
DI7
Dl6
DI5
DI4
DI3
WRITE REGISTERS
REGISTER SELECT
CODE
Dl2
Dll
DIO
RSl
RSO
0
0
~07
I D06 I D05 I D04 I D03 I D02
CPT I APT
GET I END I DEC I ERR I BO
BI
0
0
1
CPT
I
I
APT
GET I END I DEC I ERR
INTERRUPT STATUS 1
0
0
li:=
I 0
I
S6
S5
I S4
INTERRUPT MASK 2
S2
I S3
Sl
1
I
S8
I rsv
56
SERIAL POLL STATUS
ton
Ion
EOI I LPAS
I
0
MJMNI
I
TO
LO
I 0
I
1
I
I
I x
DTl
DLl
I 51
I 0
I 0
I 0
ADMll ADMOI
AUX MODE
0
AD5,01 AD4,01 AD3.01 AD2.01 AD1.01
ADDRESS
52
CNT21 CNTlI CNTOI COM41 COM31 COM21 COMll COMol
COMMAND PASS THROUGH
DLO
I S3
ADDRESS MODE
CPT71 CPTGI CPT51 CPT41 CPT31 CPT2 I CPTlI CPTO
DTO
I S4
SERIAL POLL MODE
TA
TPA5 I LA
I S5
ADDRESS STATUS
I X
I BI
DMAOI DMAII SPAScl LLOC I REMCI ADSC I
INTERRUPT STATUS 2
SRGS!
BO
INTERRUPT MASK 1
INT I SPAS I LLO I REM I SPAScl LLOC I REMCI ADScl
S8
DOl I DOO
DATA OUT
DATA IN
a
I
AR5
DT
DL
I I I
AD5
AD4
AD3
AD2 I ADl
EC2
Eel
ADDRESS 011
1
AD5.11 AD4.11 AD3.11 AD2.11 AD1.ll
ADDRESS 1
I
EC7 [ ECG
EC5
EC4
I EC3
I
[ ECO
EOS
Data Registers
DI7
I DIG
Dl5
DI4
DI3
DI2
Dll
DIO
DATA·IN REGISTER (OR)
D07 I D06
D05 I D04 I D031 D02 [DOl
DOO I
DATA·OUT REGISTER (OW)
The data-in register is used to move data from the GPIB to
the microprocessor or to memory when the 8291 is
addressed to listen. Incoming information is separately
latched by this register, and its contents are not destroyed
by a write to the data-out register. The RFD (Ready for
Data) message is held false until the byte is removed from
the data in register, either by the microprocessor or by
DMA. The 8291 then completes the handshake automatically. In RFD/OAV holdoff mode (see Auxiliary Register
A), the handshake is not finished until a command is sent
telling the 8291 to release the holdoff. In this way, the same
byte may be read several times, or an over anxious talker
may be held off until all available data has been processed.
11-170
8291
RFD/DAV holdoff mode is in effect,·datd.~h.~,until the
release command is issued. Also, a readotfl1.~'.rt:tata-in
register does not destroy the information in the dat~O\ilt
register.
" Mi
When the 8291 is addressed to talk, it uses the data-out
register to move data onto the GPIB. Upon a write to this
register, the 8291 initiates and completes the handshake
while sending the byte out over the bus. When the
Interrupt Registers
I CPT I APT
GET I END
DEC
I
ERR
BO
BI
CPT I APT
INTERRUPT STATUS 1 (1 R)
liNT
GET I END I DEC I ERR
BO
BI
I
INTERRUPT MASK 1 (1W)
I SPAS I LLO I REM I SPAScl LLOC I REMCI ADSC I
DMAOI DMAI I SPASCII.LOC I REMCI ADScl
INTERRUPT STATUS 2 (2R)
INTERRUPT MASK 2 (2W)
The 8291 can be configured to generate an interrupt to the
microprocessor upon the occurrence of any of 12
conditions or events on the GPIB. Upon receipt of an
interrupt, the microprocessor must read the Interrupt
Status registers to determine which event has occurred,
and then execute the appropriate service routine (if
necessary). Each of the 12 interrupt status bits has a
matching mask bit in the interrupt mask registers. These
mask bits are used to select the events that will cause the
INT pin to be asserted. Writing a logic "1" into any of these
bits enables the corresponding interrupt status bits to
generate an interrupt. Bits in the Interrupt Status registers
are set regardless of the states of the mask bits. The
I nterrupt Status registers are then cleared upon being
read or when a local pon (power-on) message is executed.
If an event occurs while one of the Interrupt Status
registers is being read, the event is typically held until after
its register is cleared and then placed in the register.
The mnemonics for each of the bits in these registers and a
brief description of their respective functions appears in
Table 4. This table also indicates how each of the interrupt
bits is set.
TABLE 4. Interrupt Bits
Indicates Undefined Commands
CPT
An undefined command has been received.
Set by (TPAS + LPAS)oSCGoACDS.MODE 3
APT
A secondary address must be passed through
to the microprocessor for recognition.
Set by DTAS
GET
A group execute trigger has occurred.
Set by (EOS + EOI)oLACS
END
An EOS or EOI message has been received.
Set by DCAS
DEC
Device Clear Active State has occurred.
Set by TACS.nbaoDAC.RFD
ERR
Interface error has occurred; no listeners
are active.
TACSo(SWNS + SGNS)
80
A byte has been output.
BI
A byte has been input.
Set by LACS.ACDS
Shows status of the INT pin
The device has been enabled for a serial poll
INT
SPAS
The device is in local lock out state.
(LWLS+RWLS)
LLO
The device is in a remote state.
(REMS+RWLS)
REM
---
SPAS-SPAS
These are status only. They will not generate
- interrupts, nor do they have corresponding
mask bits.
SPASC
Serial Poll Active State change interrupt
LLq:::NO LLO
LLOC
Local lock out change interrupt.
RemotQocal
RLC
Remote/Local change interrupt.
AddresseCUnaddressed
ADSC
Address status change interrupt!
"In ton (talk-only) and Ion (listen-only) modes, no ADSC interrupt is generated.
11·171
8291
;
The BO and BI interrupts enable the user to perform data
transfer cycles. BO indicates that a byte has been sent to
the GPIB and a new data byte may be written into the Data
Out register. It is set by the occurrence of TACS • (SWNS
+ SGNS). Hence, it is reset when a data byte is written into
the Data Out register, when ATN is asserted on the
GPIB, or when the device stops being addressed to talk.
Similarly, BI is set when an input byte is accepted into the
8291 and reset when the microprocessor reads the Data In
register. BO and BI are also reset by pon (power-on local
message) and by a read of the Interrupt Status 1 register.
However, if it is so desired, data transfer cycles may be
performed without reading the Interrupt Status 1 register
if all interrupts except for BO or BI are masked; BO and BI
will automatically reset after each byte is transferred.
If the 8291 is used without DMA, the BO and BI interrupts
may be enabled through the DMA REO pin. The DMAO
and DMAI bits in the Interrupt Mask 2 register would be the
corresponding mask bits for this feature. Thus, implementing this feature, with BO and BI masked from the INT
pin, allows for servicing of these interrupts without
reading the Interrupt Status registers.
The ERR bit is set to indicate the bus error condition where
the 8291 is an active talker, tries sending a byte to the
GPIB, but there are no active listeners (e.g., all devices on
the GPIB are in AIDS). The logical equivalent of (nba •
TACS • DAC • RFD) will set this bit.
The DEC bit is set whenever DCAS has occurred. The user
must define a known state to which all device functions
will return in DCAS. Typically this state will be a power-on
state. However, the state of the device functions at DCAS
is at the deSigner's discretion. It should be noted that
DCAS has no effect on the interface functions which are
returned to a known state by the I FC (interface clear)
message or the pon local message.
The End Interrupt bit may be used by the microprocessor
to detect that a multi-byte transfer has been completed.
The bit will be set when the 8291 is an active listener
(LACS) and either EOS or EOI is received. EOS will
generate an interrupt when the byte in the Data In register matches the byte in the EOS register. Otherwise the
interrupt will be generated when a true input is detected at
the EOI pin of the 8291.
The GET interrupt bit is used by the microprocessor to
detect that DTAS has occurred. It is set by the 8291 when
the GET message is received while it is addressed to listen. The TRIG output pin of the 8291 is also asserted
when the GET message is received. Thus, the basic
operation of the device may be started without involving
the microprocessor.
The APT interrupt bit indicates to the processor that a
secondary address is available in the CPT register for
validation. This interrupt will only occur if Mode 3
addressing is in effect. (Refer to the section on
addreSSing.) In Mode 2, secondary addresses will be
recognized on the 8291. They will be ignored in Mode 1.
The CPT interrupt bit flags thEi>ac i
fined command and of all secondar~;'CQ'ffr!j1
ing an undefined command. The COlJ)man
through feature is enabled by the BO bit'2>hl'(u?.:
4.The 8291 sends DAVtrue on the GPIB and proceeqSwi,lh ..,
the Source Handshake protocol.
It should be noted that each time the device is addressed.
the Address Status Register should be read. and the 8257
should be initialized accordingly. (Refer to the 8257 data
sheet available in Intel's Peripheral Design Handbook.)
System Configuration
Microprocessor Bus Connection
The 8291 is 8080. 8048. 8085 and 8086 compatible. The
three address pins (RSo. RS,. RS21 should be connected to
the non-multiplexed address bus (for example: As. Ag.
A101. In case of 8080. any address lines may be used.
External Transceivers Connection
8291 IEEE bus pins are TTL compatible. For IEEE Std. bus
connection. external transceivers are required. 8291
supplies Transmit/Receive control pins: T IR1 controls
010,-8, NRFD, NADC and DAV transceivers,T/R2
controls EOI transceiver. I FC, A TN, REN are always inputs
and SRO is always an output.
Logically. TR1 = TACS + SPAS + PPAS;
TR2 = TACS + SPAS.
Refer to 8292
configuration.
Data
Sheet
for
8291/8292 system
8291
DEVICE ELECTRICAL CHARACTERISTICS
D.C. CHARACTERISTICS
TA = O°C to 70°C; Vee = 5V ± 10%
Symbol
Parameter
Min.
Max.
Unit
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2
Vee+0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
2.4
V
IOH = -400,..A (-150,..A for SRQ pin)
VOH-INT
Interrupt Output High Voltage
2.4
V
IOH=-400,..A
IlL
Input Leakage
10
ILOL
Output Leakage Current
ILOH
Output Leakage Current
lee
Vee Supply Current
3.5
A.C. CHARACTERISTICS
± 10%, Commercial: TA =
Vee = 5V
V
Symbol
Parameter
Address Stable Before READ
Min.
-10
I'A
VouT=0.45V
10
I'A
VOUT=Vce
180
mA
TA=O°C
Max.
Unit
nseel 11
tRA
Address Hold After READ
tRR
READ width
0
nsec l1 1
250
nsec l21
tAO
Address Stable to Data Valid
250
nsec l11
tRO
READ to Data Valid
100
nsec l21
Data Float After READ
0
tAW
Address Stable Before WRITE
0
60 121
nsec
nsecl 11
tWA
Address Hold After WRITE
tww
WRITE Width
250
tow
Data Set Up Time to the Trailing
Edge of WRITE
150
nsec l11
two
Data Hold Time After WRITE
0
nsecl 11
0
nsec l11
tAKRQ
DACKI to DREQI
130
nsec
tOKOA6
DACKI to Up Data Valid
200
nsec
Notes:
1. 8080 System CLmax = 100pF: CLmin = 15pF; 3 MHz clock.
2. 8085 System CL = 150pF; 4 MHz clock.
11-179
IOH=-50,..A
VIN=OV to Vee
0
tROF
IOL=2mA (4mA for TR1 pin)
I'A
O°C to 70°C
tAR
Test Conditions
8291
TIMING WAVEFORMS
CSIRSi
~
K
I"
"-'RA-
'RR
'AO
II
i\
~
./
DATA BUS
(DATA DUT)
"
~'RV["--
-+
--'RO-
I--'AR--
I\--
I--'ROF
VALID DATA
WRITE
CSIRSi
~
I<
'ww
I--'WA-J
_'ow __
WRITE
\
_'RV[,I_ _
--.
I--'AW-DATA BUS
(DATA IN)
~
DATA MAY CHANGE
VALID DATA
K
DATA MAY CHANGE
NOTES: 1. 'Rv'S THE TIME BETWEEN READ OR WRITE OPERATIONS WITH
THE CHIP SELECTED (CHIP .!lECOYERY TIME).
DMA
DREQ _ _- - - J/
I
b,,,",
--------~,~---------
11-180
I\--
'WO--
8291
GPIB TIMINGSl 1
1
>;>':;;V:'
Symbol
Parameter
Max.
Unit
Test Conditions
90
nsec
PPSS,ATN=OA5V
PPSS,ATN=OA5V
-,
TEOT13
EOI! to TR11
TEODI6
EOII to 010 Valid
130
nsec
TEOT12
EOIltoTR11
130
nsec
PPSS,ATN=OA5V
TATND4
ATN! to NDAGI
130
nsec
TAGS, AIDS
TATT14
ATNI to TR11
130
nsec
TAGS, AIDS
TATT24
ATNI to TR21
130
nsec
TAGS, AIDS
TDNVD3-G
DAVI to NDAGI
350
nsec
AH,GAGS
TNDDV1
NDACI to DAVI
300
nsec
SH,STRS
TNRDV2
NRFDI to DAVI
300
nsec
SH, T1 True
TNDDR1
NDAGI to DREQI
350
nsec
SH
TDVDR3
DAVI to DREQI
350
nsec
AH, LACS, ATN=2AV
TDVND2-G
DAVI to NDACI
350
nsec
AH,LACS
TDVNR1-G
DAVI to NRFDI
350
nsec
AH, LACS, rdy=True
;;!.J~4f
>
';
TRDNR3
RD~
500
nsec
AH, LACS
TWRDI5
WR to 010 Valid
200
nsec
SH, TAGS, RS=OAV
TWRDV2
WRt to DAV+
760
nsec
NRFD = 2AV, RS = OAV, SH,
TACS, High Speed Transfers
Enabled, NF = fe = 8 MHz
to NRFDt
Notes;
L All GPIB timings are at the pins of the 8291,
11-181
;
8291
Appendix A
MODIFIED STATE DIAGRAMS
Figure A.1 presents the interface function state diagrams.
It is derived from IEEE Std. state diagrams, with the
following changes:
E. The symbol
A. Controller function omitted.
B. Addressing modes included in T,L state diagrams.
Note that in Mode 3, MSA, OSA are generated only after
secondary address validity check by the microprocessor
(APT interrupt).
indicates:
x--0
1. When event X occurs, the function will return to
state S.
2. X overrides any other transition condition in the
function.
C. All remote messages sent true in each state are
indicated.
D. All remote multiline messages decoded are conditioned by ACDS. The multiplication by ACDS is not
drawn to simplify the diagrams.
Statement 2 simplifies the diagram, avoiding the explicit
use of X to condition all transitions from S to other states.
r----l
I
I
I
L
I
I
I
____ J
SH
pon
OAC
ATN + Fi
(WITHIN t2)
Fl:: TACS + SPAS
r----...,
I
I
I
AH
I
I
I
L ____ J
"THIS TRANSITION WILL NEVER
OCCUR UNOER NORMAL OPERATION.
pon--_"",
F3=ATN+rdy
T3' "" T3 • CPT· APT
F3 + T3'· ATN
Figure A.1. 8291 State Diagrams (Continued next page)
11-182
TOELAY ·DAV
8291
pon-----..j
IFC
(WITHIN t4)
F4:= OTA + (OSA' TPAS + MSA· LPAS)'
MODE 1 + MLA· MODE 1
END IF DAB:= EOS
rI
I
IL
SRO
____ J
pon---_-I
SPAS
pon - - - _...
IFC
(WITHIN t4)
r----,
I
I
LE'
I
L ____
pon
J
r----l
1
1
---_-I
pon
pon-----..j
F5
Figure A.1. 8291 State Diagrams (Continued next page)
11·183
=
----00-1
(MLA· MODE 1 + LPAS • MSA· MODE 11
1
RL
1
1L
____
J1
8291
r----,
I
J
PP2
I
L __ _ _
I
I
I
J
pon
F6'" DeL + SOC, LADS
r----..,
I
I
I
I
DT
L ____
I
I
....J
Figure A.1. 8291 State Diagrams
Appendix B
IEEE 488 TIME VALUES
Time Value
Identifier-
Function (Applies to)
Tl
SH
Description
Value
Settling Time for Multiline Messages
2' 21'st
Response to A TN
-S 200ns
t2
LC,iC,SH,AH,T,L
T3
AH
Interface Message Accept Time
14
T,TE,L,LE,C,CE
Response to IFC or REN False
< 1001's
ts
PP
Response to ATN+EOI
-S 200ns
T6
C
Parallel Poll Execution Time
2' 21's
T7
C
Controlier Delay to Allow Current Talker
to see ATN Message
2' 500ns
Ts
C
Length of IFC or REN False
> 1001's
Tg
C
Delay for EOI"
2' 1.51'stt
t
> 00
Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified by an
upper case T indicate the minimum time that a function must remain in a state before exiting.
If three-state drivers are used on the 010, DAV, and EOI lines, Tl may be:
1. '2: 1100ns
2. Or '2: 700ns if it is known that within the controller ATN is driven by a three-state driver.
3. Or '2: SOOns for all subsequent bytes following the first sent alter each false transition of ATN (the first byte must be sent in
accordance with (1) or (2).
4. Or '2: 350ns for all subsequent bytes following the first sent after each false transition of ATN under conditions specified in
Section 5.2.3 and warning note. See IEEE Standard 488.
t
Time required for interface functions to accept, not necessarily respond to interface messages.
o Implementation independent.
•• Delay required for EOI, NDAC, and NRFD signal lines to indicate valid states.
tt
'2: 600ns for three-state drivers.
11-184
8291
:it"···
~
f ~~V,t.
Appendix C
THE THREE WIRE HANDSHAKE
DATA
J ___________-JX___
VALID
DAV
NONE READY
NRFD
IllilillDV
ALL READY
SOME
READV
LU 4JL
NDAC
ACC
I ACC
I
I
I
I
DATA TRANSFER
BEGINS
TRANSFER
ENDS
Figure C.1. 3-Wire Handshake Timing.
11-185
8291
SOURCE
ACCEPTOR
YES
YES
OATA IS VAllO ANO MAY
NOW BE ACCEPTEO
NDAC SIGNAL LINE STAYS LOW UNTIL
ALL ACCEPTORS HAVE ACCEPTED IT
DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME
NO
FLOW DIAGRAM OUTLINES SE~UENCE OF EVENTS DURING TRANSFER OF
DATA BYTE. MORE THAN ONE LISTENER AT A TIME CAN ACCEPT DATA
BECAUSE OF LOGICAL AND CONNECTION OF NRFD AND NDAC LINES.
Figure C.2. Handshake Flowchart.
11·186
Appendix 0
FUNCTIONAL PARTITIONS
B
I
1
A
L
~I
DEVICE (APPARATUS)
INTERFACE
FUNCTIONS
J~~
W
LL
E
DEVICE
FUNCTIONS
/E
~~(C
\ r---v
\
::::C3~
J:.3):
C
(8292 ONLY)
1\
\
\
DT
\
\
\
DC
\
\
\
\
PP
\
\
\
IT
L -_ _ _ _ _ _. -_ _ _ _ _ _~I~I
:;¢(2:¢
MESSAGE
CODING
¢0=
I
SR
I
DRIVERS
AND
RECEIVERS
-------------
~FACE
l"i"I~S
I
I
L
OR -----r---r--- --------- LE -----
:B
LL;
\
RL
I
T
OR TE
/
/
I
AH
I
I
I
SH
I
/
/
________________-,______________~
MCS'·
SYSTEM
1
8291
A B 12 34 5 --
CAPABILlTV DEFINED BV THE 488·1975 STANDARD.
CAPABILITY DEFINED BV THE DESIGNER.
INTERFACE BUS SIGNAL LINES.
REMOTE INTERFACE MESSAGES TO AND FROM INTERFACE FUNCTIONS.
DEVICE DEPENDENT MESSAGES TO AND FROM DEVICE FUNCTIONS.
STATE LINKAGES BETWEEN INTERFACE FUNCTIONS.
LOCAL MESSAGES BETWEEN DEVICE FUNCTIONS AND INTERFACE
FUNCTIONS (MESSAGES TO INTERFACE FUNCTIONS ARE DEFINED.
MESSAGES FROM INTERFACE FUNCTIONS EXIST ACCORDING TO THE
DESIGNER'S CHOICE).
6 - CONTROL MESSAGES (8292 ONL V).
Figure 0.1. Functional Partition Within a Device.
INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara, California 95051 (408) 987-8080
11-187
Printed in U.S.A./0978-T-203-CG
Intel
8292
GPIB CONTROLLER
FEATURES:
• Complete IEEE Standard 488 Controller
Function.
• Complete Implementation of Transfer
• Interface Clear (IFC) Sending Capability
Allows for Seizure of Control and/or
Initialization of the Bus.
• Synchronous Control Seizure Prevents
the Destruction of any Data
Transmission in Progress.
Control Protocol.
• Responds to Service Requests (SRQ).
• Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker/Listener/Controller.
• Sends (REN), Allowing Instruments to
Switch to Remote Control.
The 8292 GPIB CONTROLLER is a microprocessor·controlled chip designed to connect with the 8291
GPIB TALKER/LISTENER to implement the full IEEE Standard 488 controller function, including transfer
control protocol. The 8292 is a pre-programmed UPI-41A: M
PIN CONFIGURATION
IFCR
X1
VCC
COUNT
X2
REN
RESET
OAV
NC
IBFI
Cs
OBFI
GND
EOI
RD
SPI
AD
TCI
WR
CIC
SYNC
DO
8291,8292 SYSTEM DIAGRAM
:I cONfl-brllEfl :I
L _____ J
IOPTIONAl)
8291
GPIB
TALKERI
LISTENER
8292
GPI8
CONTROLLER
NC
ATNO
01
NC
02
ClTH
03
Ne
04
NC
05
SYC
06
IFC
07
IITN'
VSS
SRQ
GENERAL PURPOSE INTERFACE BUS
11-188
8292
PIN DESCRIPTION
Symbol 1/0 Pin No.
0 0-0 7
Ao
CS
RD
WR
RESET
DAV
1/0
ATNI
CIC
EOI
IFC
0
1/0
1/0
SYC
OBFI
IBFI
Function
1/0 12-19 8 bidirectional lines used for com·
munication between the central
processor and the 8292'5 data bus
buffers and status register.
Address Line-Used to select be·
9
tween the data bus and the status
register during read operations
and to distinguish between data
and commands written into the
8292 during write operations.
6
Chip Select Input-Used to select
the 8292 from other devices on the
common data bus.
8
1/0 write input which allows the
master CPU to write to the 8292.
10
1/0 read input which allows the
master CPU to read from the 8292.
0
0
4
Used to initialize the chip to a
known state during power on.
37
DAV Handshake Line-Used only
during parallel poll, configures to
force the 8291 to accept the parallel poll status bits.
22
Attention In-Used by the 8292 to
monitor the GPIB ATN control line.
It is used during "take control synchronously" execution and during
the transfer control procedure.
31
34
Controller In Charge-Controls
the SIR input of the SRQ bus transceiver. It can also be used to indicate that the 8292 is in charge of
the bus.
End Or Identify-One of the GPIB
management lines, as defined by
IEEE Std. 488-1975. Used with ATN
as Identify Message during parallel poll.
23
Interface Clear-One of the GPIB
management lines, as defined by
IEEE Std. 488-1975, places all devices in a known quiescent state.
24
System Controller-Monitors the
system controller switch.
35
Output Buffer Full-Used as an interrupt to the central processor
while the output buffer of the 8292
is full. The feature can be enabled
and disabled by the interrupt mask
register.
36
Input Buffer Not Full-Used to in·
terrupt the central processor while
the input buffer of the 8292 is
empty. This feature is enabled and
disabled by the interrupt mask
register.
Symbol 1/0 Pin No.
Function
0
Attention Out-ControlstheATN;;
control line of the bus through external logic for tcs (take control
synchronously) purpose. (ATN is a
GPIB control line, as defined by
IEEE Std. 488-1975.)
Service Request-One of the IEEE
control lines. Sampled by the 8292
when it is controller in charge, if
true-SPI interrupt to the monitor
will be generated.
The Remote Enable bus signal
selects remote or local control of
the device on the bus. A GPIB bus
management line, as defined by
IEEE Std. 488-1975.
Task Complete Interrupt-Interrupt to the control processor used
to indicate that the task requested
was completed by the 8292 and the
information requested is ready in
the data bus.
Special Interrupt-Used as an interrupt on events not initiated by
the central processor.
CLEAR LATCH Output-Used to
clear the IFCR after recognized by
the 8292. Usually low (except after
hardware Reset), will be pulsed
low when IFCR is recognized by
the 8292.
IFC Received (Iatched)- The 8292
monitors the IFC Line (when not
system controller) through this
pin.
Count Input-When enabled by
the proper command the internal
counter will count external events
through this pin. High to low transition will increment the internal
counter by one. The pin is sampled
once per three internal instruction
cycles (7.5 flsec when using 6 MHz
XT AL). It can be used for byte
counting when connected to
NDAC line, or for block counting
when connected to the EOI line.
Inputs for a crystal, LC or an external timing signal to determine the internal oscillator frequency.
ATNO
29
21
REN
0
38
TCI
0
32
SPI
0
33
CLTH
0
27
I
39
IFCR
COUNT
X1,X2
SYNC
Vee
Vss
11-189
2,3
0
11
P.S.
40
P.S.
7,20
8041A instruction cycle synchronization signal; it is an output clock with a frequency of
XTAL+ 15.
+ 5V supply input.
Circuit ground potential.
8294
DATA ENCRYPTION UNIT
• 7·Bit User Output Port
• Single 5V ± 10% Power Supply
Certified by National Bureau of
• Standards
• 80 Byte/Sec Data Conversion Rate
Data Encryption Using 56·Bit
• 64·Bit
Key
to MCS·86""', MCS.as™,
• Peripheral
MC&IOlM and MCs.48 Processors
JM
Implements Federal Information
• Processing
Data Encryption Standard
• DMA Interface
3 Interrupt Outputs to Aid in Loading
• and
Unloading Data
• Encrypt and Decrypt Modes Available
DESCRIPTION
The Intel@ 8294 Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and decrypt
64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard.
The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64·bit cipher words. The operation
is reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the 8294; however, the 56-bit key is user-defined and may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294 in 8-bit bytes by way of the system data
bus. A DMA interface and three interrupt outputs are available to minimize software overhead associated with data
transfer. Also, by using the DMA interface two or more DEUs may be operated in parallel to achieve effective system
conversion rates which are virtually any multiple of 80 bytes/second. The 8294 also has a l·bit TTL compatible output
port for user-specified functions.
Because the 8294 implements the NBS encryption algorithm it can be used in a variety of Electronic Funds Transfer
applications as well as other electronic banking and data handling applications where data must be encrypted.
PIN
CONFIGURATION
NC
X1
VCC
NC
DACK
ORO
SRO
OAV
NC
WR
PIN NAMES
PIN NAME
BLOCK DIAGRAM
FUNCTION
DATA
07"00
RD,WR
cs
Ao
RESET
X1,X2
DATA BUS
REAO,WRITE STROBES
CHIP SELECT
CONTROUDAT A SELECT
RESET INPUT
BUS
P6
SYNC
DRQ,DACK
SRQ,OAV,CCMP
P'
P6'PO
VCC,VOQ,GND
FREQUENCY REFERENCE INPUT
HIGH FREQUENCY OUTPUT
DMA ReOUEST,DMA ACKNOWLEDGE
INTERRUPT REQUEST OUTPUTS
OUTPUT PORT LINES
+ 5V POWER,GND
NC
NO CONNECTION
SYNC
DO
P1
PO
VOO
NC
ceMP
PO·P6
RESET~
SYNC
ceMP
X,
NC
NC
X2
TIMING
GNO
+5V-POWER-_
GNO--
11-190
INTERNAL
BUS
8294
Pin If
Pin Name
Pin If
Pin Name
1
NC
No connection.
40
Vee
+ 5 volt pow~r inpci'l~,i -r5V
2
X1
3
X2
Inputs for crystal, L-C or external timing signal to determine
internal oscillator frequency.
39
NC
No connection.
38
OACK
4
RESET
37
ORO
0
OMA request. Output signal to
the 8257 OMA Controller
requesting a OMA cycle.
38
SRO
0
Service Request. Interrupt to
the CPU indicating that the
8294 is awaiting data or commands at the input buffer.
SRO= 1 implies IBF=O.
35
OAV
0
Output Available. Interrupt to
the CPU indicating that the
8294 has data or status available in its output buffer.
OAV=1 impliesOBF=1.
34
NC
33
o
30
29
28
27
P6
P5
P4
P3
P2
P1
PO
User output port lines. Output
lines available to the user via a
CPU command which can assert selected port lines. These
lines have nothing to do with
the encryption function. At
power-on, each line is in a 1
state.
26
Voo
110
Pin Description
5
NC
No connection.
CS
A low signal to this pin enables
reading and writing to the 8294.
7
GNO
This pin must be tied to ground.
8
RO
An active low read strobe at
this pin enables the CPU to
read data and status from the
internal OEU registers.
9
Ao
Address input used by the CPU
to select OEU registers during
read and write operations.
WR
11
SYNC
12
00
13
01
14
15
16
17
18
19
O2
20
An active low write strobe at
this pin enables the CPU to
send data and commands to
the OEU.
o
I/O
High frequency (Clock ... 15)
output. Can be used as a strobe
for external circuitry.
Three-state, bi-directional data
bus lines used to transfer data
between the CPU and the 8294.
03
04
05
06
07
GNO
± 10%.
OMA acknowledge. Input
signal from the 8257 OMA Controller acknowledging that the
requested OMA cycle has been
granted.
A low signal to this pin resets
the 8294.
6
10
110
This pin must be tied to ground.
32
31
25
NC
24
CCMP
23
NC
NC
NC
22
21
11 -191
No connection.
+ 5V power input. (+ 5V ± 10%)
Low power standby pin.
No connection.
o
Conversion Complete. Interrupt
to the CPU indicating that the
encryption/decryption of an
8-byte block is complete.
No connection.
No connection.
No connection.
8294
,~
BASIC FUNCTIONAL DESCRIPTION
DEC
Decrypt; indicates whether the DEU is in an
crypt or a decrypt mode. DEC = 1 implies the
decrypt mode. DEC = 0 Implies the encrypt
mode.
CF
Completion Flag; This flag may be used to indicate any or all of three events in the data transfer
protocol.
The data conversion sequence is as follows:
en-'
After this, data conversions are made by writing 8 data
bytes and then reading back 8 converted data bytes. Any
of the above commands may be issued between data
conversions to change the basic operation of the DEU;
e.g., a Decrypt Data command could be issued to
change the DEU from encrypt mode to decrypt mode
without changing either the key or the interrupt outputs
enabled.
INTERNAL DEU REGISTERS
Four internal registers are addressable by the master
processor: 2 for input, and 2 for output. The following
table describes how these registers are accessed.
RD
WR
CS
Ao
1
0
0
0
0
0
1
o
o
o
1
o
X
X
o
1. It may be used in lieu of a counter in the
processor routine to flag the end of an 8byte transfer.
2. It must be used to indicate the validity of
the KPE flag.
3. It may be used in lieu of the CCMP interrupt
to indicate the completion of a DMA operation.
KPE
Key Parity Error; After a new key has been
entered, the DEU uses this flag in conjunction
with the CF flag to indicate correct or incorrect
parity.
Register
Data input buffer
Data output buffer
Command Input buffer
Status output buffer
Don't care
X
COMMAND SUMMARY
1-
Data Output Buffer - Data read from this register is the
output of the encryption/decryption operation.
Command Input Buffer - Commands to the DEU are
written into this register. (See command summary
below.)
Status Output Buffer - DEU status is available in this
register at all times. It is used by the processor for polldriven command and data transfer operations.
6
5
4
3
2
FUNCTION:
x
X
KPE
CF
DEC
1'-0"1-'11-0"1""'011'-0""'1""'011'-0""'1-'01
MSB
Data Input Buffer - Data written to this register is interpreted in one of three ways, depending on the preceding
command sequence.
1. Part of a key.
2. Data to be encrypted or decrypted.
3. A DMA block count.
STATUS BIT:
Enter New Key
OP CODE:
The functions of each of these registers are described
below.
OBF
,
Input Buffer Full; A write to the Data Input Buffer
or to the Command Inpui 'Suffer sets 18F''''''1. The
DEU resets this flag when It !'las acce'ptl!d: the
Input byte. Nothing should be written whciit ,(,'
IBF= 1.
'~"':..:",
OPERATION
1. A Set Mode command is given, enabling the desired
interrupt outputs.
2. An Enter New Key command is issued, followed by 8
data inputs which are retained by the DEU for encryption/decryption. Each byte must have odd parity.
3. An Encrypt Data or Decrypt Data command sets the
DEU in the desired mode.
,
IBF
LSB
This command is followed by 8 data byte inputs which
are retained in the key buffer (RAM) to be used in
encrypting and decrypting data. These data bytes must
have odd parity represented by the LSB.
2-
Encrypt Data
OP CODE:
0-'-1-0'-11-'-11 1'-0-'-1-0'-10-'-1-'01
r-I
MSB
LSB
This command puts the 8294 into the encrypt mode.
3-
Decrypt Data
OP CODE:
1'"""0"10-'1-1 0"""'1""'01'"""0'-10-'1-'0
'"""I
MSB
I
LSB
This command puts the 8294 into the decrypt mode.
4 - Set Mode
OPCODE:
10 10 10 10 1AlB 1C 1DI
MSB
LSB
where:
Output Buffer Full; OBF= 1 indicates that output
from the encryption/decryption function is
available in the Data Output Buffer. It is reset
when the data is read.
11-192
A is the OAV (Output Available) interrupt enable
B is the SRQ (Service Request) interrupt enable
C is the DMA (Direct Memory Access) transfer enable
D is the CCM P (Conversion Complete) interrupt enable
8294
This command determines which interrupt outputs will
be enabled. A "1" in bits A, B, or 0 will enable the OAV,
SRO, or CCMP interrupts respectively. A "1" in bit C will
allow DMA transfers. When bit C is set the OAV and
SRO interrupts should also be enabled (bits A,B= 1).
Following the command in which bit C, the DMA bit, is
set, the 8294 will expect one data byte to specify the
number· of 8·byte blocks to be converted using DMA.
5 - Write to Output Port
OP CODE:
rll'l'p-6'1p-5'I-P4'I-p-3 'Ip-2'I-P1'I-p-'o1
LSB
MSB
This command causes the 7 least significant bits of the
command byte to be latched as output data on the 8294
output port. The initial output data is 1111111. Use of
this port is independent of the encryption/decryption
function.
After the Enter New Key conimand i:S":i~SJ,i$d, 8 data
bytes representing the new key areW!1t.~E!if't6~~~.gata
input buffer (most significant byte first).:After tH'9~h.
byte is accepted by the DEU, CF goes true'{q~''IIIJ1. 'i"ht¥,e :' ,
CF bit goes false again when KPE is valid. The tl?U'CjiIfI,d",,:' .'"
then check the KPE flag. If KPE = 1, a parity erro'r:'ha~' .: , '
been detected and the DEU has not accepted the key. '
Each byte is checked for odd parity, where the parity bit
is the LSB of each byte.
Since the CF bit is used in this protocol to indicate the
validity of the KPE flag, it may not be used to flag the
end of the 8 byte key entry. CF = 1 only as long as KPE is
invalid. Therefore, the CPU might not detect that CF = 1
and the key entry is complete before KPE becomes
valid. Thus, a counter should be used, as in Figure 2, to
flag the end of the new key entry. Then, CF is used to
indicate a valid KPE flag.
PROCESSOR/DEU INTERFACE PROTOCOL
ENTERING A NEW KEY
The timing sequence for entering a new key is shown in
Figure 1. A flowchart showing the CPU software to
accommodate this sequence is given in Figure 2.
DATA REGISTER
CF~
1 BYTE OF KEY
L
KPE ____________
'N_VA_L_'D________~~
AD
_n... -l.J"" -""l.J - - - -u ------ I L
CHECKLf
KPE
ViR
---1J KEY
KEY
~
DATA
DATA
KEY
DATA
NEW
KEY
COMMAND
Figure 1. Entering a New Key
Figure 2. Flowchart for Entering a New Key
11·193
8294
ENCRYPTING OR DECRYPTING DATA
USING SOFTWARE CO\lllTEII
Figure 3 shows the timing sequence for encrypting or
decrypting data. The CPU writes a data bytes to the
DEU's data input buffer for encryption/decryption. CF
then goes true (CF = 1) to indicate that the DEU has
accepted the a·byte block. Thus, the CPU may test for
IBF => G and CF = t to terminate the' input mode, or it
may use a software counter. When the encryption/·
decryption is complete, the CCMP and OAV Interrupts
are asserted and the OBF flag is set true (OBF= 1). OAV
and OBF are set false again after each of the converted
data bytes is read back by the CPU. The CCMP interrupt
is set false, and remains false, after the first read. After
a bytes have been read back by the CPU, CF goes false
(CF = 0). Thus, the CPU may test for CF = 0 to terminate
the read mode. Also, the CCMP Interrupt may be used to
initiate a service routine which performs the next series
of a data reads and a data writes.
,
---'Ir----111.-_ _ __
CCMP
(IF ENABLED) _ _ _ _---'_ _ _ _
n
sRalL-J
(IF ENABLED)
L_
Jl'--__________
DAY
I11LJ11L_Jr lL
oaF
_ _ _ _11
I LJr lLJI lL
(IF ENABLEO) _ _ _ _ _ _ _ _ _ _ _
CF]
USING CF FLAG
I
l.JLJ-lJ
WRUlJ-LJ
8 DATA WRITES
8 DATA READS
~------------
100 ms - MAXIMUM
Figure 3. Encrypting/Decrypting Data
Figure 4 offers two flowcharts outlining the alternative
means of implementing the data conversion protocol.
Either the CF flag or a software counter may be used to
end the read and write modes.
SRQ= 1 implies IBF=O, OAV= 1 implies OBF= 1. This
allows interrupt routines to do data transfers without
checking status first. However, the OAV service routine
must detect and flag the end of a data conversion.
Figure 4. Data Conversion Flowcharts
11·194
'I"
8294
USING DMA
The timing sequence for data conversions using DMA is
shown in Figure 5. This sequence can be better
understood when considered in conjunction with the
hardware DMA interface in Figure 6. Note that the use of
the DMA feature requires 3 external AND gates and 2
DMA channels (one for input, one for output). Since the
DEU has only one DMA request pin, the SRO and OAV
outputs are used in conjunction with two of the AND
gates to create separate DMA request outputs for the 2
DMA channels. The third AND gate combines the two
active-low DACK inputs.
CCMP
(IF ENABLED)
CF
SRO
=::::==:::;-_____________-:::'r
OOJ
, - - I_
_
_
_
--.JI
_
LflJ1f--l'--_ _ __
RD
Il_JL
~-Lrl __ ~
--U-lJU--UlJ--U-
WR
1JlJLJ--lJ
OAV
DMAR
DACK
To initiate a DMA transfer, the CPU mu!ll'first.initialize
the two DMA channels as showri.!n the. f'foWI1./1!·art in
Figure 7. It must then issue a Set ModecQr:nmantl,'t'~:fRe
DEU enabling the OAV, SRO, and DMA butpu'ts. The,
CCMP interrupt may be enabled or disabled, dependIng
on whether that output is desired. Following the'Set'
Mode command, there must be a data byte giving the
number of 8-byte blocks of data (n<256) to be converted.
The DEU then generates the required number of DMA
requests to the 2 DMA channels with no further CPU
intervention. When the requested number of blocks
has been converted, the DEU will set CF and assert the
CCMP interrupt (if enabled). CCMP then goes false
again with the next write to the DEU (command or data).
Upon completion of the conversion, the DMA mode is
disabled and the DEU returns to the encrypt/decrypt
mode. The enabled interrupt outputs, however, will
remain enabled until another Set Mode command is
issued.
USING DMA
INITIALIZE OMA READ CHANNEL POINTER
INITIALIZE OMA WRITE CHANNEL POINTER
SET
DMA
--..DMA
BLOCK
8 OMA READS
MODE COUNT (n)
8 OMA WRITES
REPEATED n TIMES
Figure 5. DMA Sequence
00- 0 ,
~r)
YES
8257
8
Figure 7. DMA Flowchart
SINGLE BYTE COMMANDS
INT-----::~.
,2 X,
r -__.-,.....-__
8257
8294
20 PF
I
INT------<
?
11-202
A
8
C
0
E
F
G
H
I
J
K
L
M
N
0
Print Char.
P
Q
R
S
T
U
V
W
X
Y
Z
[
\
1
t
8295
" 'J""",
PIN DESCRIPTION
Pin #
Description
12-19
Three-state bidirectional data
bus buffer lines used to interface the 8295 to the host processor in the parallel mode. In
the serial mode Do-D2 sets up
the baud rate.
10
Pln#
o
35
GP1,GP2
o
o
23,24
General purpose output piils:"
51-57
27-33
Solenoid drive outputs; active
low.
STB
o
34
Solenoid strobe output. Used
to determine duration of solenoids activation.
22
Top of form input, used to
sense top of form signal for
type T printer, active low.
Write input which enables the
master CPU to write data and
commands to the 8295. In the
serial mode this pin must be
tied to ground.
Description
Main motor drive,
,
aetivel~.i:;>:,;, "
Read input which enables the
master CPU to read data and
status. In the serial mode this
pin must be tied to Vee.
IRQ/SER
I/O
36
In parallel mode it is an interrupt request input to the
master CPU; in serial mode it
should be strapped to ground.
6
Chip select input used to
enable the RD and WR inputs
except during DMA, active low.
DRQ/CTS
0
37
4
Reset input, active low. After
reset the 8295 will be set for 12
characterslinch single width
printing, solenoid strobe at 320
msec.
In the parallel mode used as
DMA request output pin to indicate to the 8257 that a DMA
transfer is requested; in the
serial mode used as clear·tosend signal.
DACKI
SIN
1/0
38
In the parallel mode used as
DMA acknowledgement; in the
serial mode, used as input for
data.
SYNC
o
11
Output signal which occurs
once per instruction cycle (2.5
,..sec wittJ 6 MHz crystal); can
be used as a reference clock.
Vee
9,40
Voo
26
+ 5V power supply.
+ 5V low power standby sup-
GND
20
Circuit and supply ground.
PFEED
1
39
2,3
o
1/0
MOT
8
HOME
PFM
Name
110
1/0
21
Paper feed input switch.
Home Input switch, used by
the 8295 to detect that the print
head is in the home position.
Inputs for a crystal to set in·
ternal oscillator frequency. For
proper operation use 6 MHz
crystal.
Paper feed motor drive, active
low.
11-203
ply.
Microcomputer
Development Systems
12
MICROCOMPUTER DEVELOPMENT SYSTEMS
TABLE OF CONTENTS
MICROCOMPUTER DEVELOPMENT SYSTEMS
Model 210 Intellec® Series II Microcomputer Development System.................................... 12-3
Model 220 Intellec® Series II Microcomputer Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12·6
Model 230 Intellec® Series II Microcomputer Development System .................................... 12-10
Expansion Chassis Intellec® Series II Microcomputer Development System ............................. 12·14
Model 770 Printer Intellec® Series II Microcomputer Development System .............................. 12·16
Intellec Printer ................................................................................ 12·18
MCS-48 Diskette·Based Software Support Package ........... " .................................... 12·20
PUM-80 High Level Programming Language Intellec® Resident Compiler ............................... 12·22
MDS-311 8086 Software Development Package ..................................................... 12·25
FORTRAN-80 8080/8085 ANS FORTRAN 77 Intellec Resident Compiler ................................ , 12·36
Basic-80 Extended ANS 1978 Basic Intellec® Resident Interpreter ..................................... 12-40
Intellec® Single/Double Density Flexible Disk System ............................................... 12·43
ISIS-II Diskette Operating System Microcomputer Development System ................................ 12-47
Intellec Prompt 48 MCS-48 Microcomputer Design Aid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-50
ICE-49 MCS-48In-Circuit Emulator ................................................................ 12·56
ICE-80 8080 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-61
ICE-85 MCS·85 In-Circuit Emulator ................................................................ 12-67
ICE-86 8086 In-Circuit Emulator. ................................................................. 12-71
EM1 8021 Emulation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-77
EM2 8022 Emulation Board ...................................................................... 12-80
UPP-103 Universal PROM Programmer ............................................................ 12-83
SDK-85 MCS-85 System Design Kit. .............................................................. 12-85
SDK-86 MCS-86 System Design Kit ............................................................... 12-91
SDK-C86 MCS·86 System Design Kit Software and Cable Interface to Intellec® Development System. . . . . . .. 12·97
Insite User's Program Library .................................................................... 12-99
TEST AND INSTRUMENTATION SYSTEMS
I'Scope 820 Microprocessor System Console ...................................................... 12-103
"Scope Probe 8080A ........................................................................... 12·108
"Scope Probe 8085 ............................................................................. 12-110
MICROCOMPUTER TRAINING PROGRAMS ......................................................... . 12·112
12·2
inter
MODEL 210
INTELLEC SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Low cost development system for
MCS·80, MCS·85, and MCS·48 microproc·
essor families
Built·in interfaces for TTY, CRT, printer,
high speed paper tape reader/punch and
universal PROM programmer
Compact four·slot chassis
Standard MULTIBUS with multiproc·
essor and DMA capabilities
Single LSI electronics board with CPU,
32K bytes RAM memory, and 4K bytes
ROM memory
ROM·based monitor, assembler, and
editor
Self·test diagnostic capability
Compatible with standard Inteliec/iSBC
expansion modules
Eight·level nested, maskable priority
interrupt system
Software compatible with previous
Intellec systems
The Model 210 Intellec Series II Microcomputer Development System is a low cost, fully supported development system providing basic hardware and software support for development of products based around Intel's MCS-80 or
MCS-85 microprocessor families. Through optional software, this development capability can be extended to products
based on the MCS-48 family of microprocessors. Using the user supplied system console (TTY or equivalent), the pro·
duct designer may enter and correct a program source code, assemble, and begin execution, all using the Model 210
ROM·resident editor/assembler. MCS·80 and MCS·85 debugging is accomplished by means of system monitor debug
commands. Completed programs may be punched to paper tape for loading into the user's system or programmed into
PROM using the optional Intellec UPP-103 Universal PROM Programmer.
12·3
MODEL 210
FUNCTIONAL DESCRIPTION
interrupt controller, operating in a polled mode, nested
to the primary 8259.
Hardware Components
The Intellec Series II Model 210 is a compact, 4·inch
table·top chassis with a 4·slot cardcage, power supply,
and two printed circuit cards. The CPU, interrupt, 1/0,
and bus interface circuitry are all fashioned from Intel's
high technology LSI components and located on one PC
board. Known as the integrated processor board (lPB), it
occupies the first slot in the cardcage. A second PC
board (the parallel 1/0 board - PIO) containing addi·
tional 1/0 interface logic is mounted on the rear panel.
The remaining 3 slots in the cardcage are available for
system expansion. A simplified block diagram of the
IPB is shown in Figure 1.
PIO Interface Logic - The second part of the 110 sub·
system consists of the interface logic provided on the
PIO board itself. Utilizing Intel's UPI·41 programmable
peripheral controller, the PIO board provides device
interfaces for standard Intellec peripherals, including a
printer, high speed paper tape reader, high speed paper
tape punch, and Universal PROM programmer. Com·
munication between the IPB and PIO is maintained over
a separate 8·bit bidirectional data bus. Connectors for
the four devices specified above, as well as the two
serial channels, are mounted directly on the PIO.
Control
System Components
User control is maintained through a front panel con·
sisting of a power switch and indicator, reset/boot
switch, runlhalt light, and eight interrupt switches and
indicators. The front·panel circuit board is attached
directly to the IPB, allowing the eight interrupt switches
to connect to the primary 8259, as well as to the Intellec
Series II bus.
The heart of the IPB is an Intel NMOS 8·bit microproces·
sor, the 8080A·2, running at 2.6 MHz. 32K bytes of RAM
memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with sys·
tem bootstrap "self·test" diagnostics, and the Intellec
Series II System Monitor. The eight·level vectored prior·
ity interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259 interrupt controller,
the interrupt system may be user programmed to
respond to individual needs.
MUL TIBUS Capability
All Intellec Series II models implement the industry·
standard MULTIBUS. MULTIBUS enables several bus
masters, such as CPU and DMA devices, to share the
bus and memory by operating at different priority levels.
Resolution of bus exchanges is synchronized by a bus
clock signal derived independently from processor
clocks. Readlwrite transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microprocessor family.
Input/Output
IPB Serial Channels - The 110 subsystem in the Model
210 consists of two parts. Two serial channels are pro·
vided directly on the IPB itself. Each channel is RS232
compatible and is capable of running asynchronously
from 110 to 9600 baud or synchronously from 150 to 56K
baud. One channel contains current loop adapters for
teletype compatibility. Both channels are implemented
using Intel's 8251 USART. They can be programmatic·
ally selected to perform a variety of 110 functions. Baud
rate selection is accomplished programmatically
through an Intel 8253 interval timer. The 8253 also
serves as the real·time clock for the entire system. 110
activity is signaled to the system through a second 8259
Software
All standard Model 210 software is ROM·based to elimi·
nate costly delays of loading paper tape. The capabili·
ties of the system monitor with its "self·test" diagnos·
tics, text editor, and MCS·80/MCS·85 or MCS·48 ROM
assemblers are described on pages 10·22 to 10·25 of this
catalog.
Figure 1. Simplified Integrated Processor Board (lPB) Block Diagram for the Model 210 Intellec Series II
Microcomputer Development System
12·4
MODEL 210
Electrical Characteristics
SPECIFICATIONS
DC Power Supply
Host Processor (IPB)
8080A-2 based, operating at 2.600 MHz.
RAM - 32K, expandable to 64K with iSBC 032 RAM
board (system monitor occupies 62K through 64K)
ROM - 4K (2K in monitor, 2K in boot/diagnostic),
expandable with addition of 20K auxiliary ROM board
containing text editor and assembler
Bus - MULTIBUS, maximum transfer rate of 5 MHz
Clocks - Host processor, crystal controlled at 2.6 MHz,
bus clock, crystal controlled at 9.8304 MHz
Volts
Supplied
Amps
Supplied
Typical
System Requirements
+ 5±5%
+12±5%
-12±5%
-10±5%
24
2.0
0.3
1.0
3.5
0.1
0.05
0.1
AC Requirements
50-60 Hz, 115/230V AC
Environmental Characteristics
Operating Temperature -
O'C to 35'C (95 'F)
Memory Access Time
Equipment Supplied
RAM - 585 ns max
PROM - 450 ns max
Model 210 chassis
Integrated processor board (IPB)
Parallel 1/0 board (Pia)
ROM-resident system monitor
Auxiliary ROM board with MCS-80/MCS-85 assembler
and text editor
PROM programming software (paper tape)
Assembler cross reference program (paper tape)
1/0 Interfaces
2 serial 1/0 channels, RS232C, at 110-9600 baud (asynchronous) or 150-56K baud (synchronous). Baud rates
and serial format fully programmable using Intel 8251
USARTs. Serial channel 1 additionally provided with 20
mA current loop. Parallel 1/0 interfaces provided for
paper tape punch, paper tape reader, printer, and
UPP-103 Universal PROM Programmer.
Reference Manuals
9800558 - A Guide to Microcomputer Development
Systems (SUPPLIED)
9800557 - Intellec Series II Model 210 User's Guide
(SUPPLIED)
9800555 - Intellec Series II Hardware Interface Manual
(SUPPLIED)
9800301 -8080/8085 Assembly Language Programming Manual (SUPPLIED)
9800605 - Intellec Series II System Monitor Source
Listing (SUPPLIED)
9800554 - Intellec Series II Schematic Drawings
(SUPPLIED)
Interrupts
8-level, maskable, nested priority interrupt network initiated from front panel or user selected devices.
Direct Memory Access (DMA)
Standard capability on MULTIBUS; implemented for
user selected DMA devices through optional DMA
module - maximum transfer rate of 2 MHz.
Physical Characteristics
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Width - 17.37 in. (44.12 cm)
Height - 4.81 in. (12.22 cm)
Depth - 19.13 in. (48.59 cm)
Weight - 45 Ib (20.5 kg)
ORDERING INFORMATION
Part Number
Description
MDS-210
Intellec Series II Model 210
microcomputer development system
12-5
InT~I
~
MUDEL 220
INTELLEC SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Complete microcomputer development
system in one package for MCS·aO,
MCS·aS, and MCS·4a microprocessor
families
Integral CRT with detachable upperl
lower case typewriter·style full ASCII
keyboard
Integral 2S0K·byte floppy disk with total
storage capacity expandable to over 2M
bytes
Single LSI electronics board with CPU,
32K bytes RAM memory, and 4K bytes
ROM memory
Powerful ISIS·II Diskette Operating
System with relocating macroassembler,
linker, and locater
Self·test diagnostic capability
Standard MULTIBUS with multi·
processor and DMA capability
Eight·level nested, maskable priority
interrupt system
Compatible with standard InteliecliSBC
expansion modules
Built·in interfaces for high speed paper
tape reader/punch, printer, and universal
PROM programmer
Software compatible with previous
Intellec systems
The Model 220 Intellec Series II Microcomputer Development System is a complete microcomputer development
system integrated into one compact package. It includes a CPU with 32K bytes of RAM memory, 4K bytes of ROM
memory, a 2000-character CRT, detachable full ASCII keyboard with cursor controls and upperllower case capability,
and a 250K-byte floppy diskette drive. Powerful ISIS-II Diskette Operating System software allows the Model 220 to be
used quickly and efficiently for assembling and debugging programs for Intel's MCS-80, MCS-85, or MCS-48 microprocessor families without the need for paper tape handling. ISIS-II performs all file handling operations for the user,
leaving him free to concentrate on the details of his own application. When used in conjunction with an optional incircuit emulator (ICE) module, the Model 220 provides all the hardware and software development tools necessary for
the rapid development of a microcomputer-based product.
12-6
MODEL 220
Input/Output
FUNCTIONAL DESCRIPTION
IBP Serial Channels - The 110 subsystem in the Model
220 consists of two parts: the 10C card and two serial
channels on the IPB itself. Each serial channel is RS232
compatible and is capable of running asynchronously
from 110 to 9600 baud or synchronously from 150 to 56K
baud. Both may be connected to a user defined data set
or data terminal. One channel contains current loop
adapters. Both channels are implemented using Intel's
8251 USART. They can be programmatically selected to
perform a variety of 110 functions. Baud rate selection is
accomplished programmatically through an Intel 8253
interval timer. The 8253 also serves as a real-time clock
for the entire system. I/O activity through both serial
channels is signaled to the system through a second
8259 interrupt controller, operating in a polled mode,
nested to the primary 8259.
Hardware Components
The Intellec Series II Model 220 is a packaged, highly
integrated microcomputer development system consisting of a CRT chassis with a 6-slot cardcage, power supply, fans, cables, single floppy diskette drive, and two
printed circuit cards. A separate, full ASCII keyboard is
connected with a cable.
CPU Cards - The master CPU card contains its own
microprocessor, memory, 110, interrupt, and bus interface circuitry, fashioned from Intel's high-technology
LSI components. Known as the integrated processor
board (IPB), it occupies the first slot in the cardcage. A
second, slave CPU card, is responsible for all remaining
110 control, including the CRT and keyboard interface
and floppy disk control. This card, mounted on the rear
panel, also contains its own microprocessor, RAM and
ROM memory, and 110 interface, thus in effect creating a
dual processor environment. Known as the 110 controller (IOC), the slave CPU card communicates with the
IPB over an 8-bit bidirectional data bus, thus leaving the
remaining 5 slots in the cardcage available for system
expansion. A block diagram of the 10C is shown in
Figure 1.
10C Interface - The remainder of system I/O activity
takes place in the 10C. The 10C provides interfaces for
the CRT, keyboard, integral floppy disk and standard
Intellec peripherals, including a printer, high speed
paper tape reader/punch, and universal PROM programmer. The 10C contains its own independent microprocessor, also an 8080A-2. This CPU controls all I/O operations, as well as supervising communications with the
IPB. 8K bytes of ROM contain all I/O control firmware.
8K bytes of ROM are used for CRT screen refresh storage and the floppy disk buffer. These do not occupy any
space in Intellec Series II main memory since the 10C is
a totally independent microcomputer subsystem.
System Components
The heart of the IPB is an Intel NMOS 8-bit microprocessor, the 8080A-2, running at 2.6 MHz. 32K bytes of RAM
memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with system bootstrap "self-test" diagnostics and the Intellec
Series II System Monitor. The eight-level vectored priority interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259 interrupt controller,
the interrupt system may be user programmed to
respond to individual needs.
Integral CRT Display - The CRT is a 12-inch raster
scan-type monitor with a 50/60 Hz vertical scan rate and
15.5 kHz horizontal scan rate. Controls are provided for
brightness and contrast adjustments. The interface to
the CRT is provided through an Intel 8275 single chip,
programmable CRT controller. The master processor on
CABLE BUS TO IPS
Figure 1. 110 Controller (lOC) Block Diagram for the Model 220 Intellec Series II Microcomputer Development System
12-7
MODEL 220
the IPB transfers a character for display to the 10C,
where it is stored in RAM. The CRT controller reads a
line at a time into its line buffer through an Intel 8257
DMA controller and then feeds one character at a time
to the character generator to produce the video signal.
Timing for the CRT control is provided by an Intel 8253
interval timer. The screen display is formatted as 25
rows of 80 characters. The full set of ASCII characters
are displayed, including lower·case alphas.
standard Intellec peripherals, including a printer, high
speed paper tape reader, high speed paper tape punch,
and universal PROM programmer. Communication
between the IPB and 10C is maintained over a separate,
8·bit bidirectional data bus. Connectors for the devices
named above, as well as the two serial channels, are
mounted directly on the 10C itself.
Control
Keyboard - The keyboard interfaces directly to the 10C
processor via an 8·bit data bus. The keyboard contains
an Intel UPI-41 Universal Peripheral Interface, which
scans the keyboard, encodes the characters, and buffers the characters to provide N·key rollover. The key·
board itself is a high quality typewriter-style keyboard
containing the full ASCII character set. An upperllower
case switch allows the system to be used for document
preparation. Cursor control keys are also provided.
User control is maintained through a front panel con·
sisting of a power switch and indicator, reset/boot
switch, run/halt light, and eight interrupt switches and
indicators. the front·panel circuit board is attached
directly to the IPS, allowing the eight interrupt switches
to connect to the primary 8259, as well as to the Intellec
Series II bus.
Floppy Disk Drive
All Intellec Series II models implement the industry·
standard MULTIBUS. MULTIBUS enables several bus
masters, such as CPU and DMA devices, to share the
bus and memory by operating at different priority levels.
Resolution of bus exchanges is synchronized by a bus
clock signal derived independently from processor
clocks. Read/write transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microcomputer family.
MULTIBUS Capability
The floppy disk drive is controlled by an Intel 8271
single chip, programmable floppy disk controller. It
transfers data via an Intel 8257 DMA controller between
an 10C RAM buffer and the diskette. The 8271 handles
reading and writing of data, formatting diskettes, and
reading status, all upon appropriate commands from the
10C microprocessor.
Peripheral Interface
Expansion
A UPI-41 Universal Peripheral Interface on the 10C board
performs similar functions to the UPI-41 on the PIO
board in the Model 210. It provides interface for other
The Model 220 may be expanded to 64K of RAM and up
to 2.25M bytes of on-line diskette storage.
SPECIFICATIONS
Direct Memory Access (DMA)
Host Processor (IPB)
Standard capability on MULTISUS; implemented for
user selected DMA devices through optional DMA
module - maximum transfer rate of 2 MHz.
8080A·2 based, operating at 2.600 MHz.
RAM - 32K, expandable to 64K with iSBC 032 RAM
boards (system monitor occupies 62K through 64K)
ROM - 4K (2K in monitor, 2K in boot/diagnostic)
Bus - MULTISUS, maximum transfer rate of 5 MHz
Clocks - Host processor, crystal controlled at 2.6 MHz,
bus clock, crystal controlled at 9.8304 MHz
Memory Access Time
RAM - 585 ns max
PROM - 450 ns max
Diskette
Diskette System Capacity - 250K bytes (formatted)
Diskette System Transfer Rate - 160K bits/sec
I/O Interfaces
Diskette System Access Time
Track·to-Track: 10 ms max
Average Random Positioning: 260 ms max
Rotational Speed: 360 rpm
Average Rotational Latency: 83 ms max
Recording Mode: FM
2 Serial I/O Channels, RS232C, at 110-9600 baud (asynchronous) or 150-56K baud (synchronous). Baud rates
and serial format fully programmable using Intel 8251
USARTs. Serial Channel 1 additionally provided with 20
mA current loop. Parallel I/O interfaces provided for
paper tape punch, paper tape reader, printer, and
UPP·103 Universal PROM Programmer.
Physical Characteristics
Interrupts
Width - 17.37 in. (44.12 cm)
Height - 15.81 in. (40.16 cm)
8·level, maskable, nested priority interrupt network initiated from front panel or user selected devices.
Depth - 19.13 in. (48.59 cm)
Weight - 86 Ib (39 kg)
12-8
MODEL 220
Reference Manuals
Keyboard
Width - 17.37 in. (44.12 cm)
Height - 3.0 in. (7.62 cm)
Depth - 9.0 in. (22.0 cm)
Weight - 6 Ib (3 kg)
A Guide to Microcomputer Development
Systems (SUPPLIED)
9800558 -
Intellec Series II Installation and Service
Manual (SUPPLIED)
9800559 -
Electrical Characteristics
9800306 -
ISIS·II System User's Guide (SUPPLIED)
DC Power Supply
Volts
Supplied
Amps
Supplied
Typical
System Requirements
+ 5±5%
+ 12±5%
30.0
2.5
0.3
1.5
1.5
1.7
7.5
0.2
0.05
0.15
1.3"
1.2"
-12±5%
-10±5%
+15±5%
+ 24±5%
Intellec Series II Hardware Reference Man·
ual (SUPPLIED)
9800556 -
9800555 -
Intellec Series II Hardware Interface Manual
(SUPPLIED)
8080/8085 Assembly Language Program·
ming Manual (SUPPLIED)
9800301 -
*Not available on bus.
AC Requirements
Intellec Series II System Monitor Source
Listing (SUPPLIED)
9800605 -
50-60 Hz. 115/230V AC
Equipment Supplied
9800554 -
Model 220 chassis
Integrated processor board (IPB)
I/O controller board (IOC)
CRT and keyboard
250K·byte floppy disk drive
ROM resident system monitor
ISIS·II system diskette with MCS·80/MCS·85
macroassembler
Intellec Series II Schematic Drawing
(SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
Description
MDS·220
Intellec Series II Model 220
microcomputer development system
(110V/60 Hz)
MDS·221
Intellec Series II Model 220
microcomputer development system
(220V/50 Hz)
12·9
MODEL 230
INTELLEC SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Complete microcomputer development
center for Intel MCS·80, MCS·85, and
MCS·48 microprocessor families
LSI electronics board with CPU, RAM,
ROM, I/O, and interrupt circuitry
Powerful ISIS·II Diskette Operating
System software with relocating
macroassembler, linker, and locater
1 million bytes (expandable to 2.5M
bytes) of diskette storage
64K bytes RAM memory
Self·test diagnostic capability
Eight·level nested, maskable priority
interrupt system
Supports PLIM and FORTRAN high level
languages
Standard MULTIBUS with multiprocessor
and DMA capability
Built·in interfaces for high speed paper
tape reader/punch, printer, and universal
PROM programmer
Compatible with standard Inteliec/iSBC
expansion modules
Integral CRT with detachable upper/
lower case typewriter·style full ASCII
keyboard
Software compatible with previous
Intellec systems
The Model 230 Intellec Series II Microcomputer Development System is a complete center for the development of
microcomputer-based products. It includes a CPU, 64K bytes of RAM, 4K bytes of ROM memory, a 2000-character CRT,
a detachable full ASCII keyboard, and dual double density diskette drives providing over 1 million bytes of on-line data
storage. Powerful ISIS-II Diskette Operating System software allows the Model 230 to be used quickly and efficiently
for assembling and/or compiling and debugging programs for Intel's MCS-80, MCS-85, or MCS-48 microprocessor
families without the need "for handling paper tape. ISIS-II performs all file handling operations, leaving the user free to
concentrate on the details of his own application. When used in conjunction with an optional in-circuit emulator (ICE)
module, the Model 230 provides all the hardware and software development tools necessary for the rapid development
of a microc0rT!puter-based product.
12-10
MODEL 230
FUNCTIONAL DESCRIPTION
card communicates with the IPS over an 8-bit bidirectional data bus.
Hardware Components
Memory and Control Cards - In addition, 32K bytes of
RAM (bringing the total to 64K bytes) is located on a
separate card in the main cardcage. Fabricated from
Intel's 16K RAMs, the board also contains all necessary
address decoding and refresh logic. Two additional
boards in the cardcage are used to control the two
double-density floppy disk drives.
The Intellec Series II Model 230 is a packaged, highly
integrated microcomputer development system consisting of a CRT chassis with a 6-slot cardcage, power supply, fans, cables, and five printed circuit cards. A
separate, full ASCII keyboard is connected with a cable.
A second chassis contains two floppy disk drives capable of double-density operation along with a separate
power supply, fans, and cables for connection to the
main chassis. A block diagram of the Model 230 is
shown in Figure 1.
CPU Cards - The master CPU card contains its own
microprocessor, memory, 110, interrupt and bus interface circuitry fashioned from Intel's high technology LSI
components. Known as the integrated processor board
(IPS), it occupies the first slot in the cardcage. A second
slave CPU card is responsible for all remaining 110 control including the CRT and keyboard interface. This card,
mounted on the rear panel, also contains its own microprocessor, RAM and ROM memory, and 110 interface
logic, thus, in effect, creating a dual processor environment. Known as the 110 controller (10C), the slave CPU
Expansion - Two remaining slots in the cardcage are
available for system expansion. Additional expansion of
4 slots can be achieved through the addition of an Intellec Series II expansion chassis.
System Components
The heart of the IPS is an Intel NMOS 8-bit microprocessor, the 8080A-2, running at 2.6 MHz. 32K bytes of RAM
memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with system bootstrap "self-test" diagnostics and the Intellec
Series II System Monitor. The eight-level vectored prior·
ity interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259 interrupt controller,
the interrupt system may be user programmed to
respond to individual needs.
Figure 1_ Intellec Series II Model 230 Microcomputer Development System Block Diagram
12-11
MUDEL 230
Input/Output
IPB Serial Channels - The I/O subsystem in the Model
230 consists of two parts: the 10C card and two serial
channels on the IPB itself. Each serial channel is RS232
compatible and is capable of running asynchronously
from 110 to 9600 baud or synchronously from 150 to 56K
baud. Both may be connected to a user defined data set
or terminal. One channel contains current loop
adapters. Both channels are implemented using Intel's
8251 USART. They can be programmatically selected to
perform a variety of I/O functions. Baud rate selection is
accomplished progammatically through an Intel 8253
interval timer. The 8253 also serves as a real·time clock
for the entire system. I/O activity through both serial
channels is signaled to the system through a second
8259 interrupt controller, operating in a polled mode
nested to the primary 8259.
and universal PROM programmer. Communication
between the IPB and 10C is maintained over a separate
8·bit bidirectional data bus. Connectors for the four
devices named above, as well as the two serial chan·
nels, are mounted directly on the 10C itself.
Control
User control is maintained through a front panel, con·
sisting of a power switch and indicator, reset/boot
switch, run/halt light, and eight interrupt switches and
indicators. The front panel circuit board is attached
directly to the IPB, allowing the eight interrupt switches
to connect to the primary 8259, as well as to the Intellec
Series II bus.
Diskette System
The Intellec Series II double density diskette system
provides direct access bulk storage, intelligent control·
ler, and two diskette drives. Each drive provides 1/2 mil·
lion bytes of storage with a data transfer rate of 500,000
bits/second. The controller is implemented with Intel's
powerful Series 3000 Bipolar Microcomputer Set. The
controller provides an interface to the Intellec Series II
system bus, as well as supporting up to four diskette
drives. The diskette system records all data in soft sec·
tor format. The diskette system is capable of performing
seven different operations: recalibrate, seek, format
track, write data, write deleted data, read data, and verify
CRC.
IOC Interface - The remainder of system I/O activity
takes place in the 10C. The 10C provides interface for
the CRT, keyboard, and standard Intellec peripherals
including printer, high speed paper tape reader/punch,
and universal PROM programmer. The 10C contains its
own independent microprocessor, also an 8080A·2. The
CPU controls all I/O operations as well as supervising
communications with the IPB. 8K bytes of ROM contain
all I/O control firmware. 8K bytes of RAM are used for
CRT screen refresh storage. These do not occupy space
in Intellec Series II main memory since the 10C is a
totally independent microcomputer subsystem.
Integral CRT
Diskette Controller Boards - The diskette controller
consists of two boards, the channel board and the inter·
face board. These two PC boards reside in the Intellec
Series II system chassis and constitute the diskette
controller. The channel board receives, decodes and
responds to channel commands from the 8080A·2 CPU
in the Model 230. The interface board provides the
diskette controller with a means of communication with
the diskette drives and with the Intellec system bus. The
interface board validates data during reads using a
cyclic redundancy check (CRC) polynomial and gener·
ates CRC data during write operations. When the disk·
ette controller requires access to Intellec system memo
ory, the interface board requests and maintains DMA
master control of the system bus, and generates the
appropriate memory command. The interface board also
acknowledges I/O commands as required by the Intellec
bus. In addition to supporting a second set of double
density drives, the diskette controller may co·reside
with the Intel single density controller to allow up to 2.5
million bytes of on·line storage.
Display - The CRT is a 12·inch raster scan type monitor
with a 50/60 Hz vertical scan rate and 15.5 kHz horizontal
scan rate. Controls are provided for brightness and con·
trast adjustments. The interface to the CRT is provided
through an Intel 8275 single chip programmable CRT
controller. The master processor on the IPB transfers a
character for display to the 10C, where it is stored in
RAM. The CRT controller reads a line at a time into its
line buffer through an Intel 8257 DMA controller and
then feeds one character at a time to the character gen·
erator to produce the video Signal. Timing for the CRT
control is provided by an Intel 8253 interval timer. The
screen display is formatted as 25 rows of 80 characters.
The full set of ASCII characters are displayed, including
lower case alphas.
Keyboard - The keyboard interfaces directly to the 10C
processor via an 8·bit data bus. The keyboard contains
an Intel UPI·41 Universal Peripheral Interface, which
scans the keyboard, encodes the characters, and buf·
fers the characters to provide N·key rollover. The key·
board itself is a high quality typewriter style keyboard
containing the full ASCII character set. An upperllower
case switch allows the system to be used for document
preparation. Cursor control keys are also provided.
MUL TlBUS Capability
All Intellec Series II models implement the industry
standard MULTIBUS. MULTIBUS enables several bus
masters, such as CPU and DMA devices, to share the
bus and memory by operating at different priority levels.
Resolution of bus exchanges is synchronized by a bus
clock Signal derived independently from processor
clocks. Read/write transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microcomputer family.
Peripheral Interface
A UPI·41 Universal Peripheral Interface on the 10C board
performs similar functions to the UPI·41 on the PIO
board in the Model 210. It provides interface for other
standard Intellec peripherals including a printer, high
speed paper tape reader, high speed paper tape punch,
12·12
MODEL 230
AC Requirements -
SPECIFICATIONS
50/60 Hz, 115/230V AC
Host Processor (IPB)
RAM - 64K (system monitor occupies 62K through 64K)
ROM - 4K (2K in monitor, 2K in boot/diagnostic)
Environmental Characteristics
Diskette System Capacity (Basic Two Drives)
Operating Temperature -
Unformatted
Per Disk: 6.2 megabits
Per Track: 82.0 ki lobits
Formatted
Per Disk: 4.1 megabits
Per Track: 53.2 kilobits
Equipment Supplied
Diskette Performance
Diskette System Transfer Rate - 500 kilobits/sec
Diskette System Access Time
Track·to·Track: 10 ms
Head Settling Time: 10 ms
Average Random Positioning Time - 260 ms
Rotational Speed - 360 rpm
Average Rotational Latency - 83 ms
Recording Mode - M2FM
0° to 35°C (95°F)
Model 230 chassis
Integrated processor board (IPB)
1/0 controller board (laC)
32K RAM board
CRT and keyboard
Double density floppy disk controller (2 boards)
Dual drive floppy disk chassis and cables
2 floppy disk drives (512K byte capacity each)
ROM·resident system monitor
ISIS·II system diskette with MCS·80/MCS·85
macroassembler
Physical Characteristics
Width - 17.37 in. (44.12 cm)
Height - 15.81 in. (40.16 cm)
Depth - 19.13 in. (48.59 cm)
Weight - 73 Ib (33 kg)
Reference Manuals
9800558 -
Keyboard
Width - 17.37 in. (44.12 cm)
Height - 3.0 in. (7.62 cm)
Depth - 9.0 in. (22.86 cm)
Weight - 6 Ib (3 kg)
Guide (SUPPLIED)
9800306 - ISIS·II System User's Guide (SUPPLIED)
9800556 - Intellec Series II Hardware Reference Man·
ual (SUPPLIED)
9800555 - Intellec Series II Hardware Reference Man·
ual (SUPPLIED)
Dual Drive Chassis
Width - 16.88 in. (42.88 cm)
Height - 12.08 in. (30.68 cm)
Depth - 19.0 in. (48.26 cm)
Weight - 64 Ib (29 kg)
9800301 - 8080/8085 Assembly Language Program·
ming Manual (SUPPLIED)
9800292 - ISIS·II 8080/8085 Assembler Operator's Man·
ual (SUPPLIED)
Electrical Characteristics
9800605 - Intellec Series II Systems Monitor Source
Listing (SUPPLIED)
DC Power Supply
Volts
Supplied
+ 5±5%
+12±5%
-12±5%
-10±5%
+15±5%
+24±5%
A Guide to Microcomputer Development
Systems (SUPPLIED)
98005:50 - Intellec Series II Installation and Service
Amps
Supplied
Typical
System Requirements
30
2.5
0.3
1.5
1.5
1.7
14.25
0.2
0.05
15
1.3
9800554 - Intellec Series II Schematic Drawings
(SUPPLIED)
Reference manuals are shipped with each product only
if deSignated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051 .
• Not available on bus.
ORDERING INFORMATION
Part Number
Description
MDS·230
Intellec Series II Model 230
microcomputer development system
(110V/60 Hz)
MDS·231
Intellec Series II Model 230
microcomputer development system
(220V/50 Hz)
12·13
EXPANSION CHASSIS
INTELLEC SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Four expansion slots for Intellec Series
II systems
Cable connectable to main Intellec bus
Internal power supply
Standard Intellec MULTIBUS with multi·
processor and DMA capability
Snug fit beneath all Intellec Series II
units
Compatible with standard Intellec/iSBC
expansion modules
The Intellec Series II Expansion Chassis provides four expansion slots for use with Intellec Series II microcomputer
development systems. With its own separate power supply, the expansion chassis may be fully loaded with any
boards needed to expand a user's Intellec Series II system. With the addition of the expansion chassiS, Intellec Series
II Models 220 and 230 contain a total of ten slots, sufficient for any configuration Intellec Series II system. The Intellec
Series II Expansion Chassis is a compact chassis with a four slot cardcage, power supply, fans, and cable assemblies.
It is designed to fit under any Intellec Series II system, connect directly to the system bus through an opening in the
top of the chaSSiS, and provide additional slots for the system users. The power supply is linked directly to the main
chassis power supply, allowing power to flow to both chassis when the main power is turned on.
I
12·14
EXPANSION CHASSIS
SPECI FICATIONS
Environmental Characteristics
Physical Characteristics
Operating Temperature -
Width - 17.37 in. (44.12 cm)
Height - 4.81 in. (17.22 cm)
Depth - 19.13 in. (48.59 cm)
Weight - 42 lb. (19 kg)
0° to 35°C (95°F)
Equipment Supplied
Expansion chassis
Cables
Reference Manuals
9800550 -
Intellec Series II Installation and Service
Guide (SUPPLIED)
9800554 - Intellec Series II Schematic Drawings
(SUPPLIED)
Electrical Characteristics
DC Power Supply
Volts
Supplied
+ 5±5%
+12:t:5%
-12±5%
-10±5%
AC Requirements -
Amps
Supplied
System
Requirements
24
2.0
0.3
1.0
None
None
None
None
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Depa~tment, 3065 Bowers
Avenue, Santa Clara, California 95051.
50-60 Hz, 115/230V AC
ORDERING INFORMATION
Part Number
Description
MDS-201
Intellec Series II
expansion chassis
12-15
Intel·
MODEL 770 PRINTER
INTELLEC SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Provides low cost, hard copy printer for
CRT·based systems
Prints original plus four copies
Prints 60 characters per seconds (21-90
lines per minute)
Offers 5 x 7 dot matrix character format
Provides for rear or bottom tractor feed
Provides adjustable line width from 80
to 132 columns on 81/2 inch line
The Intellec Series II Microcomputer Development System Model 770 Printer is a low cost, hard copy printer designed
for use with CRT·based Intellec Series II and Intellec microcomputer development systems. Unidirectional printing at
60 characters per second makes the Model 770 an ideal printer for microcomputer·based system designers with small
to medium printing requirements. The 8V2·inch line width may be filled with 80 to 132 characters by varying the
character size. The printer uses standard fanfold paper through a tractor·feed mechanism to produce an original and
up to four copies. Paper can be fed from either the bottom or the rear of the printer for versatility in any lab environment.
12·16
MODEL 770 PRINTER
SPECIFICATIONS
Printing Method
Paper Feed
Impact, character-by-character printing, one line character buffer.
Tractor Feed -
Printing Rate
Characters Full Lines ters/line
5.5 ips slew
Paper
60 cps
21 @ 80 characters/line, 90 @ 20 charac-
Standard sprocketed paper, BV2 in. to 9V2 in. paper width
Number of Copies
Transmission Rate
Parallel -
Original plus up to four carbon copies
Up to 75,000 cps
Character Structure
Physical Characteristics
5 x 7 dot matrix, 10 point type equivalent
Width - 24.5 in. (62.2 cm)
Height - 7.0 in. (17.8 cm)
Depth - 18.0 in. (45.7 cm)
Weight - 60 Ib (27 kg)
Code
USASCII -
64 characters printed
Switch Controls
On-Off
Electrical Characteristics
50-60 Hz, 110/230V AC ± 10%
Indicators
Paper Out
Environmental Characteristics
Format
80 to 132 characters per line, variable.
10 to 165 characters per inch, operator adjustable.
6 lines per inch.
Temperature - Operating: - 40' to 100'F (5' to 40'C),
Storage: _40' to 160'F (_40' to 50'C)
Humidity - Operating: 5% to 90% (no condensation),
Storage: 0% to 95% (no condensation)
ORDERING INFORMATION
Part Number
Description
MDS-770
60 CPS printer (110V/60 Hz)
MDS-771
60 CPS printer (220V/50 Hz)
12-17
INTEllEC PRINTER
Provides listing of hard copy output at
55 lines per minute
8112 ·inch fanfold paper
Prints up to four copies on standard
Switch selectable to 80 or 132
characters per 8112 -inch line
Provides automatic on-off motor switch
for quiet operation
Employs 5 x 7 dot matrix with standard
2-channel, vertical control format
Provides optional finished metal stand
and paper takeup tray
The Intellec Printer provides hard copy listings at 10 to 16 times the speed of a teleprinter. The automatic on-off motor
control allows the user to maintain a low noise environment and yet send information to the printer from the Intellec
system console without additional manipulation of line printer switches. The user may select a column width of 80
characters per line (10 characters per inch) or 132 characters per line (16.5 characters per inch) either manually or
under program control. Top of page spacing capability is available under user programmable format control. The
printer uses standard 81f2-inch fanfold paper and can produce up to four carbon copies along with the original. Paper
may be fed either from the bottom or from the rear of the printer for versatility in any lab environment.
12·18
INTELLEC PRINTER
Format
SPECIFICATIONS
80 or 132 characters maximum per line, 6 lines per inch
Printing Method
Paper Feed
Impact, character-by-character printing, one line character buffer
Sprocket fed, 4 I.P_S. slew, adjustable to 9V2-in. width
Printing Rate
Paper
Characters - 100 or 165 cps
Full Lines - 55 lines per minute (80- or 132-character
line)
Standard sprocketed paper
Number of Copies
Original and up to four carbon copies
Transmission Rate
Parallel -
Up to 75,000 characters per second
Data Input
Parallel
Warranty
The MDS-PRN is warranted against defects in materials
and workmanship for a period of one (1) year on mechanical parts, 90 days on electrical parts, and 45 days on
labor.
Character Structure
Physical Characteristics
5 x 7 dot matrix, 10-point type equivalent
Width - 23.25 in. (59.1 cm)
Height - 12.75 in. (32.4 cm)
Depth - 18.75 in. (47.6 cm)
Weight - 66 Ib (30.2 kg)
Code
USASCII -
64 characters printed
Switch Controls
On/off
Select
Forms override
Normal/condensed top of form
Electrical Characteristics
115V AC± 10%, 60 Hz (or 230V AC± 10%, 50 Hz as
option)
Environmental Characteristics
Indicators
Temperature - 40° to 100°F, operating; - 40° to 160°F,
storage
Humidity -5% to 90% (no condensation) operating;
0% to 95% (no condensation) storage
Paper out
Select
Manual Controls
Form thickness
Paper advance knob
Optional Equipment
MDS-STD finished metal stand and paper tray
Buffer
Reference Manuals
One line character buffer
None
ORDERING INFORMATION
Part No.
Description
MDS-PRN
Printer unit
MDS-STD
Stand and paper tray
12-19
MCS·48
DISKETTE·BASED SOFTWARE
SUPPORT PACKAGE
Extends Intellec microcomputer develop·
ment system to support MCS·48
development
Takes advantage of powerful ISIS·II file
handling and storage capabilities
MCS·48 assembler provides conditional
assembly and macro capability
Provides assembler output in standard
Intel hex format
The MCS-48 Diskette-Based Software Support Package is provided with the Intel ISIS-II system diskette and contains
both the MCS-48 assembler and the diskette version of the universal PROM mapper. The assembler translates symbolic 8048 assembly language instructions into the appropriate machine operation codes, and provides both conditional and macroassembler programming. Output may be loaded either to an ICE-48 module for debugging or into an
Intellec microcomputer development system for 8748 PROM programming using the universal PROM programmer.
12-20
MCS·48 DISKETTE·BASED SOFTWARE SUPPORT PACKAGE
FUNCTIONAL DESCRIPTION
ISIS·II 6048 t.1ACROA$SEMBLEFt, Vl 0
SEQ
SOURCE STATEMENT
The MCS-48, a software support assembler package, is
provided with the ISIS-II system diskette and contains
both the MCS-48 assembler and the diskette version of
the universal PROM mapper. The MCS-48 assembler
8048
assembly
language
translates
symbolic
instructions into the appropriate machine operation
codes. The ability to refer to program addresses with
symbolic names eliminates the errors of hand translation and makes it easier to modify programs when
adding or deleting instructions. Conditional assembly
permits the programmer to specify which portions of
the master source document should be included or
deleted in variations on a basic system design, such as
the code required to handle optional external devices.
Macro capability allows the programmer use of a single
label to define a routine. The MCS-48 assembler will
assemble the code required by the reserved routine
whenever the macro label is inserted in the text. Output
from the assembler is in standard Intel hex format. It
may be either loaded directly to an in-circuit emulator
(ICE-48) module for integrated hardware/software debugging, or loaded into an Intellec development system
for 8748 PROM programming using the universal PROM
programmer. A sample assembly listing is shown in
Table 1.
Table 1. Sample MCS·48 Diskette-Based
Assembly Listing
SPECIFICATIONS
Reference Manuals
Operating Environment
.DECIMAL ADDITION ROUTINE ADO BCD NUMBER
,AT LOCATION 'BETA' TO BCD NUMBER AT 'ALPHA' WITH
RESULT IN 'ALPHA' LENGTH OF NUMBER IS 'COUNT' DIGIT
4
5
,PAIRS (ASSUME BOTH BETA AND ALPHA ARE SAME LlNGTH
,AND HAVE EVEN NUMBER OF DIGITS OR MSD IS 0 IF
6
7
,0001
INIT
8
9
L1
"'"
"28
""
"'''
"'''
0102
0104
"'06
0107
0106
0109
010A
0108
Cloe
"""
""
8928
8,1.,32
97
ALPHA
EQU
30
BETA
EQU
EQU
ORG
40
5
100H
COUNT
" "
""
22
"
.,"
57
25
26
""
""
0100 EA07
USER SYMBOLS
ALPHA
000"
AUGND,ADDND,CNT
RO, 'AUGND
At, ItADONO
R2 .•eNT
"
".
SatE
MACRO
MOV
MOV
Mev
ENDM
10
11
IN IT
ALPHA, BETA. COUNT
MOV
RO,IIALPHA
MOV
MOV
ClR
MOV
At,II8ETA
R2. /lCOUNT
C
A, @RO
ADDG
A, @R1
DA
MOV
INC
INC
A
@RO,A
RO
DJNZ
R1
R2, lP
COUNT 0005
ASSEMBLY COMPLETE, NO ERRORS
ISIS·II ASSEMBLER SYMBOL CROSS REFERENCE, Vl 0
ALPHA
BETA
COUNT
INIT
L1
LP
138
14/1
15/1
7/1
19/1
22/1
17
17
17
17
28
9800255 - MCS-48/UPI-41 Assembly Language Programming Manual (SUPPLIED)
9800236 - Universal PROM Mapper Operator's Manual
(SUPPLIED)
9800306 - ISIS-II User's Guide (SUPPLIED)
Required Hardware
Intellec microcomputer development system
System console
Inteliec diskette operating system
32K RAM (absoluteassembler)
48K RAM (macroassembler)
Optional Hardware
Universal PROM programmer
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Shipping Media
Diskette
ORDERING INFORMATION
Product Code
Description
MDS-D48
Diskette-based assembler for MCS-48
family of microprocessors
12-21
PL/M·80
HIGH LEVEL PROGRAMMING LANGUAGE
INTELLEC RESIDENT COMPILER
Provides resident operation on Intellec
Microcomputer Development System
and Intellec Series II microcomputer
development systems
Speeds project completion with
increased programmer productivity
Produces relocatable and linkable object
code
Improves product reliability with
simplified language and consequent
error reduction
Sophisticated code optimization reduces
application memory requirements
Eases enhancement as system
capabilities expand
Cuts software development and
maintenance costs
The PUM-80 High Level Programming Language Intellec Resident Compiler is an advanced, high level programming
language for Intel 8080 and 8085 microprocessors, iSBC-80 OEM computer systems, and Intellec microcomputer
development systems. PUM has been substantially enhanced since its introduction in 1973 and has become one of
the most effective and powerful microprocessor systems implementation tools available. It is easy to learn, facilitates
rapid program development and debugging, and significantly reduces maintenance costs. PUM is an algorithmic
language in which program statements naturally express the algorithm to be programmed, thus freeing programmers
to concentrate on system development rather than assembly language details (such as register allocation, meanings
of assembler mnemonics, etc.). The PUM compiler efficiently converts free-form PUM programs into equivalent 80801
8085 instructions. Substantially fewer PUM statements are necessary for a given application than would be using
assembly language or machine code. Since PUM programs are problem oriented and thus more compact, programming in PUM results in a high degree of productivity during development efforts, resulting in significant cost reduction in software development and maintenance for the user.
12-22
PL/M·80
FUNCTIONAL DESCRIPTION
Block Structure - aids in utilization of structured programming techniques.
The PUM compiler is an efficient multi phase compiler
that accepts source programs, translates them into
object code, and produces requested listings. After
compilation, the object program may be first linked to
other modules, then located to a specific area of memory, and finally executed. The diagram shown in Figure 1
illustrates a program development cycle where the program consists of three modules: PUM, FORTRAN, and
assembly language. A typical PUM compiler procedure
is shown in Table 1.
Access - provided by high level PUM statements to
hardware resources (interrupt systems, absolute
addresses, CPU input/output ports).
Data Definition - enables complex data structures to
be defined at a high level.
Re-entrant Procedures option.
may be specified as a user
Benefits
PUM is designed to be an efficient, cost-effective solution to the special requirements of microcomputer software development as illustrated by the following benefits of PUM use:
Features
Major features of the Intel PUM-80 compiler and programming language include:
Low Learning Effort - even for the novice programmer,
because PUM is easy to learn.
Resident Operation - on Intellec microcomputer development systems eliminates the need for a large inhouse computer or costly timesharing system.
Earlier Project Completion - on critical projects,
because PUM substantially increases programmmer
productivity while reducing program development time.
Object Code Generation - of relocatable and linkable
object codes permits PUM program development and
debugging in small modules, which may be easily linked
with other modules and/or library routines to form a
complete application.
Lower Development Cost - because increased programmer productivity requiring less programming
resources for a given function translates into lower software development costs.
Extensive Code Optimization - including compile time
arithmetic, constant subscript resolution, and common
subexpression elimination, results in generation of
short, efficient CPU instruction sequences.
Increased Reliability - because of PUM's use of simple
statements in the program algorithm, which are easier
to correct and thus substantially reduce the risk of
costly errors in systems that have already reached full
production status.
Symbolic Debugging - fully supported in the PUM
compiler and ICE-85 in-circuit emulators.
Easier Enhancement and Maintenance - because programs written in PUM are easier to read and easier to
understand than assembly language, and thus are easier to enhance and maintain as system capabilities
expand and future products are developed.
Compile Time Options - includes general listing format commands, symbol table listing, cross reference
listing, and "innerlist" of generated assembly language
instructions.
Figure 1_ Program Development Cycle Block Diagram
12-23
PUM·80
ging software for 8080 and 8085 microcomputers, and
the use of expensive (and remote) timesharing or large
computers is consequently not required.
Simpler Project Development - because the Intellec
microcomputer development system with resident
PUM·80 is all that is needed for developing and debug·
$OBJECT(:F1:FACT.OB2)
$DEBUG
$XREF
$TITLE('FACTORIAL GENERATOR $PAGEWIDTH(80)
PROCEDURE')
FACT:
DO;
DECLARE NUMCH BYTE PUBLIC;
2
3
4
5
6
1
2
2
2
FACTORIAL: PROCEDURE (NUM,PTR) PUBLIC;
DECLARE NUM BYTE, PTR ADDRESS;
DECLARE DIGITS BASED PTR (161) BYTE;
DECLARE (I,C,M) BYTE;
7
9
10
11
12
13
14
15
2
2
3
3
4
4
4
4
NUMCH=1; DIGITS(1) = 1;
DO M= 1 TO NUM;
C=O;
DO 1=1 TO NUMCH;
DIGITS(I) = DIGITS(I)* M + C;
C= DIGITS(I)/10;
DIGITS(I)= DIGITS(I) - 10*C;
END;
16
17
18
20
21
22
3
3
4
4
4
4
IF C<>O THEN
DO;
NUMCH = NUMCH + 1; DIGITS(NUMCH) = C;
C= DIGITS(NUMCH)/10;
DIGITS(NUMCH)= DIGITS(NUMCH) - 10*C;
END
END;
24
2
END FACTORIAL;
25
END;
Table 1. PLlM·80 Compiler Sample Factorial Generator Procedure
Shipping Media
SPECI FICATIONS
Diskette
Operating Environment
Required Hardware
Intellec microcomputer development system
65K bytes of memory
Dual diskette drives
System console - teletype
Optional Hardware
CRT as system console
Line printer
Required Software - ISIS·II diskette operating system
Reference Manuals
980026 - PUM·80 Programming Manual (SUPPLIED)
9800300 - ISIS·II PUM·80 Compiler Operator's Manual
(SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Product Code
Description
MDS·PLM
High level language compiler
12·24
MDS·311
8086 SOFTWARE DEVELOPMENT PACKAGE
Pl/M-86 high level programming language
LlNK86, lOC86 and QRl86 link and
relocation utilities
ASM86 assembler for 8086 assembly
language programming
CONV86 converter for conversion of
8080/8085 assembly language source
code to 8086 assembly language source
code
OH86 object-to-hexadecimal converter
LlB86 library manager
The 8086 software development package provides a set of software development tools for the 8086 microprocessor
and iSBC 86/12 single board computer. The package operates under the ISIS·II operating system on Intellec®
Microcomputer Development Systems-Model 800 or Series II-thus minimizing requirements for additional hardware
or training for Intel Microcomputer Development System users.
The package permits 8080/8085 users to efficiently convert existing programs into 8086 object code from either
8080/8085 assembly language source code or PUM·80 source code.
For the new Intel Microcomputer Development System user, the package operating on an Intellec Model 230
Microcomputer Development System provides total 8086 software development capability.
12-25
MDS·311
PL/Iv1·S6 HIGH LEVEL PROGRAMMING LANGUAGE
Produces relocatable and linkable object
code
Sophisticated new compiler design
allows user to achieve maximum
benefits of 8086 capabilities
Supports full extended addressing
features of the 8086 microprocessor
Language is upward compatible from
PLlM·80, assuring MCS™·80185 design
portability
Sophisticated code optimization assures
efficient code generation and minimum
application memory utilization
Supports 16·bit signed integer and 32·bit
floating point arithmetic
Like its counterpart for MCS TM_80/85 program development, PUM-86 is an advanced structured high level programming language. PUM-86 is a new compiler created specifically for performing software development for the
Intel® 8086 Microprocessor.
PUM-86 has significant new capabilities over PUM-80 that take advantage of the new facilities provided by the 8086
microprocessor, yet the PUM-86 language remains downward compatible with PUM-80.
With the exception of interrupts, hardware flags, and time-critical code sequences, PUM-80 programs may be recompiled under PUM-86 with little or no conversion required. PUM-86, like PUM-80, is easy to learn, facilitates rapid program development, and reduces program maintenance costs.
PLiM is a powerful, structured high level algorithmic language in which program statements can naturally express the
program algorithm. This frees the programmer to concentrate on the system implementation without concern for burdensome details of assembly language programming (such as register allocation, meanings of assembler mnemonics,
etc.).
The PLlM-86 compiler efficiently converts free-form PUM language statements into equivalent 8086 machine instructions. Substantially fewer PUM statements are necessary for a given application that if it were programmed at the
assembly language or machine code level.
Since PUM programs are implementation problem oriented and more compact, use of PLiM results in a high degree of
engineering productivity during project development. This translates into significant reductions in initial software
development and follow-on maintenance costs for the user.
FEATURES
Major features of the Intel PLlM-86 compiler and programming language include:
• Supports Five Data Types
Byte: 8-bit unsigned number
Word: 16-bit unsigned number
Integer: 16-bit Signed number
Real: 32-bit floating point number
Pointer: 16-bit or 32-bit memory address indicator
• Two Data Structuring Facilities
-
Array: Indexed list of same type data elements
Structure: Named collection of same or different type data elements
Combinations of Each: Arrays of structures or structures of arrays
• Block Structure
-
Permits use of structured programming techniques
• Relocatable and Linkable Object Code
Permits PLlM-86 programs to be developed and debugged in small modules. These modules can be easily linked
with other modules andlor library routines to form a complete application system.
12-26
MDS·311
• Built·ln String Handling Facilities
-
Operates on byte strings or word strings
Six Functions: MOVE, COMPARE, TRANSLATE, SEARCH, SKIP, and SET
• Automatic Support for 8086 Extended Addressing
Three compiler options offer a separate model of computation for programs from 128K bytes to 1-Megabyte in
size
Language transparency for extended addressing
• Support for ICE·86™ and Symbolic Debugging
-
Debug option for inclusion of symbol table in object modules for In-Circuit Emulation with symbolic debugging
• Numerous Compiler Options
A host of 26 compiler options including:
•
•
•
•
•
Conditional compilation
Included file or copy facility
Two levels of optimization
Intra-module and inter-module cross reference
Arbitrary placement of compiler and user files on any available combination of disk drives
• Reentrant and Interrupt Procedures
-
May be specified as user options
BENEFITS
PUM-86 is designed to be an efficient, cost-effective solution to the special requirements of 8086 Microcomputer Software Development, as illustrated by the following benefits of PUM-86 use:
• Low Learning Effort -
PUM-86 is easy to learn and to use, even for the novice programmer.
• Earlier Project Completion - Critical projects are completed much earlier than otherwise possible because
PUM-86, a structured high-level language, increases programmer productivity_
• Lower Development Cost - Increases in programmer productivity translate immediately into lower software development costs because less programming resources are required for a given programmed function.
• Increased Reliability - PUM-86 is designed to aid in the development of reliable software (PUM-86 programs are
simple statements of the program algorithm). This substantially reduces the risk of costly correction of errors in
systems that have already reached full production status, as the more simply stated the program is, the more likely
it is to perform its intended function.
• Easier Enhancements and Maintenance - Programs written in PUM tend to be self-documenting, thus easier to
read and understand. This means it is easier to enhance and maintain PUM programs as the system capabilities expand and future products are developed.
• Simpler Project Development - The Intellec® Development Systems offer a cost-effective hardware base for the
development of 8086 designs. PUM-86 and other elements of ISIS-II and the 8086 Software Development Package
are all that is needed for development of software for the 8086 microcomputer and iSBC 86/12 single board computer. This further reduces development time and costs because-expensive (and remote) time sharing of large computers is not required. Present users of Intel Intellec® Development Systems can begin to develop 8086 designs
without expensive hardware reinvestment or costly retraining.
12-27
MDS·311
SAMPLE PROGRAM
STATISTICS: DO;
I*The procedure in this module computes the mean and variance of an array of data, X, of length N + 1, according to
the method of Kahan and Parlett (University of California, Berkeley, Memo no. UCB/ERL M77/21. *1
STAT: PROCEDURE(X$PTR,N,MEAN$PTR,VARIANCE$PTR) PUBLIC;
DECLARE (X$PTR,MEAN$PTR,VARIANCE$PTR) POINTER,
X BASED X$PTR (1) REAL,
N INTEGER,
MEAN BASED MEAN$PTR REAL,
VARIANCE BASED VARIANCE$PTR REAL,
(M,O,DIFF) REAL,
I INTEGER;
M=X(O);
0=0.0;
DO 1= 1 TO N;
DIFF = X(I) - M;
M = M + DIFF/FLOAT(I + 1);
0= + DIFF*DIFF*FLOAT(I)/FLOAT(I
END;
a
+ 1);
MEAN= M;
VARIANCE = O/FLOA T(N);
END STAT;
END STATISTICS;
12·28
MDS·311
ASM86 ASSEMBLER
A new assembler that encourages well·
designed and well·structured programs
Powerful "EQU" (equate) facility allows
complex expressions to be represented
as a single symbol
ASM86 is highly mnemonic and
compact, with most mnemonics
representing several distinct machine
instructions
Enhanced data handling capabilities
ASM86 will generate optimal code
Fully detailed set of error messages
The 8086 assembly language is "strongly typed". This means it performs extensive checks on the usage of variables
and labels. The assembler uses the attributes which are derived explicitly when a variable or label is first declared,
then makes sure that each use of a symbol in later instructions conforms to the usage defined for that symbol when It
was declared.
Compared to earlier assemblers, ASM86 supports substantially improved flexibility in data definition and manipulation:
-RECORDS
·PROCEDURES
·ARRAYS
Its capabilities allow very sophisticated goals and significantly simplified codin.g to be achieved with a straightforward use of the language.
For example a data RECORD smaller than a word may be defined as a collection of named bit-fields and operators for
manipulating these subfields are automatically defined when the rec9rd is declared. Bit-fields within a record may be
referenced directly by name.
Powerful string manipulation instructions permit direct transfers to or from memory or the accumulator. They can be
prefixed with a repeat operator for repetitive execution with a count-down and a condition test. These operations automatically decrement or increment the relevant indexes to memory, depending on the direction flag.
The assembler fully supports the 8086 addressing modes by providing for complex address expressions involving
base and index registers and field offsets. A powerful EQU facility allows the use of simplified synonyms for complicated expressions which may occur throughout a module.
The 8086 assembly language includes approximately 100 instruction mnemonics. From these few mnemonics, the
assembler can generate over 3,800 distinct machine instructions. These instructions are differentiated by the
assembler's ability to evaluate the "TYPE" of the operands to the instruction and then generate the proper machine instruction. ASM86 will generate the shortest machine instruction possible given no forward referencing or given explicit information as to the characteristics of the forward referenced symbol.
ASM86 provides a detailed set of error messages which may appear both in the regular list file and the error print file.
As a debugging feature, the list file may include a detailed listing of the user symbol table.
ASM86 allows the user power and flexibility, and is fully compatible with LlNK86, LOC86, QRL86 and LlB86.The
ASM86 operator's manual includes details on linking ASM86 programs with programs written in PUM-86.
ASM86 implements directives which reflect the high level orientation of the 8086 architecture.
ASM86 assembles code Significantly faster than ASM80 V2.0.
12-29
MDS·311
CONV 86
MCS-80/8S to MCS-86 ASSEMBLY LANGUAGE
CONVERTER UTILITY PROGRAM
Translates 8080/8085 Assembly
Language Source Code to 8086
Assembly Language Source Code
Provides a fast and accurate means to
convert 8080/8085 programs to the 8086,
facilitating program portability.
Automatically generates proper ASM·86
directives to set up a "virtual 8080"
environment that is compatible with
PLlM·86.
In support of Intel's commitment to software portability, CONV86 is offered as a tool to move 808018085 programs to
the 8086. A comprehensive manual, "MCS-86 Assembly Language Converter Operating Instructions for
ISIS-II Users" (9800642), covers the entire conversion process. Detailed methodology of the conversion process is fully
described therein.
CONV86 will accept as input an error-free 808018085 assembly-language source file and optional controls, and produce
as output, optional PRINT and OUTPUT files.
The PRINT file is a formatted copy of the 808018085 source and 8086 source file with embedded caution messages.
The OUTPUT file is an 8086 source file.
CONV86 issues a caution message when it detects a potential problem in the converted 8086 code.
A transliteration of the 8080/8085 programs occurs, with each 8080/8085 construct mapped to its exact 8086 counterpart:
-Registers
-Condition flags
-Instructions
-Operands
-Assembler directives
-Assembler control lines
Because CONV86 is a transliteration process, there is the possibility of as much as a 15%-20% code expansion over
the 8080/8085 code. For compactness and efficiency it is recommended that critical portions of programs be re-coded
in 8086 assembly language.
Also, as a consequence of the transliteration, some manual editing may be required for converting instruction sequences dependent on:
-instruction length, timing, or encoding
-interrupt processing
}
-PUM parameter passing conventions
mechanical editing procedures
for these are suggested in the converter manual.
The set directive, macro definitions, macro calls, and conditional assembly directives are not supported by Version
V1.0 of the 8086 Assembler. Appendix F of the MCS-86 Assembly Language Converter Operating Instructions for ISISII Users contains instructions for converting 8080/8085 programs containing these features, by using the macro expansion printed in the 808018085 assembler listing.
The accompanying diagram illustrates the flow of the conversion process. Initially, the abstract program may be
represented in 8080/8085 or 8086 assembly language to execute on that respective target machine. The conversion
process is porting a source destined for the 8080/8085 to the 8086 via CONV86.
12-30
MDS·311
ABSTRACT PROGRAM
SOURCE CODE
IN 808018085
ASSEMBLY LANG
-~~i
CONV86
808018085
EXECUTE
ON
808018085
SOURCE CODE
IN 8086
ASSEMBLY LANG
-ALGORITHM
,-------
r------
EQUIVALENT
FUNCTION
I
r-----r------
PORTING 8080/8085 SOURCE CODE TO THE 8086
12·31
ASSEMBLE
FOR
8086
EXECUTE
ON
8088
MDS·311
LINK86
Automatic combination of separately
complied or assembled 8086 programs
into a relocatable module
Automatic generation of a summary map
giving results of the LI N K86 process
Automatic selection of required modules
from specified libraries to satisfy
symbolic references
Extensive debug symbol manipulation;
the user is allowed the choices of line
number and local symbol deletion and
may selectively purge definitions of
public symbols
Abbreviated control syntax
Relocatable modules may be merged
into a single module suitable for
inclusion in a library
Supports "incremental" linking
LlNK86 combines object modules specified in the LlNK86 input list into a single output module. LlNK86 combines
segments from the input modules according to the order in which the modules are listed.
Support for incremental linking is provided since an output module produced by LlNK86 can be an input to another
link. At each stage in the incremental linking process, unneeded public symbols may be purged.
LlNK86 will link any valid set of input modules without any controls. However, controls are available to control the
output of diagnostic information in the LlNK86 process and to control the content of the output module.
LlNK86 allows the user to create a large program as the combination of several smaller, separately compiled modules.
After development and debugging of these component modules the user can link them together, locate them using
LOC86, and enter final testing with much of the work accomplished.
LOC86
Automatic and independent relocation
of segments. Segments may be
relocated to best match users memory
configuration
Automatic generation of a summary map
giving starting address, segment
addresses and lengths, and debug
symbols and their addresses
Extensive debug symbol manipulation,
allowing line numbers, local symbols,
and public symbols to be purged and
listed selectively
Extensive capability to manipulate the
order and placement of segments in
8086 memory
Abbreviated control syntax
Relocatability allows the programmer to code programs or sections of programs without having to know the final
arrangement of the object code in memory.
LOC86 converts relative addresses in an input module to absolute addresses. LOC86 orders the segments in the input
module and assigns absolute addresses to the segments. The sequence in which the segments in the input module
are assigned absolute addresses is determined by their order in the input module and the controls supplied with the
command.
LOC86 will relocate any valid input module without any controls. However, controls are available to control the output
of diagnostic information in the LOC86 process, to control the content of the output module, or both.
The program you are developing will almost certainly use some mix of random access memory (RAM), read-only
memory (ROM), and/or programmable read-only memory (PROM). Therefore, the location of your program affects both
cost and performance in your application. The relocation feature allows you to develop your program on the Intellec
development system and then simply relocate the object code to suit your application.
12-32
MDS·311
QRL86
Combination linkage and relocation tool
Combines object modules and converts
relative addresses to absolute addresses
in a single step
QRL86 can be used for quick turnaround
during development, whereas the extra
capabilities of LI N K86 and LOC86 may
be needed to finalize the product at the
end of development
QRL86 purges unsatisfied externals
while LlNK86 and LOC86 allow them to
be kept for future processing
QRL86 provides 25% faster turnaround
than LINK86 and LOC86, but does not
have as wide a range of controls:
Incremental linking
- Selective purge of publics
QRL86 controls give the capability of
changing the order and placement of
segments in memory
ORL86 combines object modules and converts relative addresses to absolute addresses in a single step. The segment
is the fundamental unit with which linkage and relocation functions work. First, segments are combined, then
absolute addresses are assigned to segments. Addresses that are referenced relative to the beginning of a segment
are translated to absolute memory address references.
The modules to be combined are specified in a list in the ORL86 command. In general, ORL86 will link and locate any
set of valid input modules without any controls. However, controls are available for you to modify the manner in which
ORL86 links and locates and to control the output of information in the process.
OH86
OH86 command converts an 8086
absolute object module to symbolic
hexadecimal format
Converts an absolute module to a more
readable format that can be displayed
on a CRT or printed for debugging
Facilitates preparing a file for later
loading by a symbolic hexadecimal
loader, such as the iSBC Monitor or
Universal PROM Mapper
The OH86 command converts an 8086 absolute object module to the hexadecimal format. This conversion may be
necessary to format a module for later loading by a hexadecimal loader such as the iSBC 86/12 monitor or Univeral
Prom Mapper. The conversion may also be made to put the module in a more readable format that can be displayed or
printed.
The module to be converted must be in absolute format; the output from the ORL86 and LOC86 is in absolute format.
12·33
MDS·311
LIB86
UB86 is a library manager program
which allows you to:
Create specially formatted files to
contain libraries of object modules
Maintain these libraries by adding or
deleting modules
Libraries can be used as input to QRL86
or UNK86 which will automatically
link modules from the library that
satisfy external references in the
modules being linked
Print a listing of the modules and
public symbols in a library file
Libraries aid in the job of building programs. The library manager program, LlB86, creates and maintains files containing object modules. The operation of LlB86 is controlled by commands to indicate which operation LlB86 is to perform. The commands are:
CREATE - creates an empty library file
ADD - adds object modules to a library file
DELETE - deletes modules from a library file
LIST - lists the module directory of library files
EXIT - terminates the LlB86 program and returns control to ISIS-II
1515·11
TEXT EDITOR
PLlM·86
SOURCE
RELOCATABLE
OBJECT MODULE
ORL86
USER
SYSTEM
SDK·88
OH86
ISBC86/12
or
1515·11
TEXT EDITOR
ASM86
SOURCE
RELOCATABLE
OBJECT MODULE
ASM80/85
SOURCE
12-34
LlNK86
AND
LOC86
r-------,
I
I
I
ICE.86
(TBA)
I
I
I
!... ______ l
UPM
MDS·311
SPECIFICATIONS
Operating Environment
Required Hardware
Documentation Package
Intellec® Microcomputer Development System
PUM-86 Programming Manual (9800466)
ISIS-II PUM-86 Compiler Operator's Manual (9800478)
MCS™_86 User's Manual (9800694)
MCS-86 Software Development Utilities Operating
Instructions for ISIS-II Users (9800639)
MCS-86 Assembly Language Reference Manual (9800640)
MCS-86 Assembler Operating Instructions for ISIS-II
Users (9800641)
MCS-86 Assembly Language Converter Operating
Instructions for ISIS-II Users (9800642)
MCS-86 Absolute Object File Formats (9800821)
Universal PROM Programmer User's Manual (9800819A)
- M DS-800, M DS-888
- Series II
64K Bytes of RAM Memory
Dual Diskette Drives
-
Single or Double- Density
System Console
-
CRT or Hardcopy Interactive Device
Optional Hardware
Universal PROM Programmer
Line PrinterICE-86™Required Software
ISIS-II Diskette Operating System
Flexible Diskettes
-
-
Single or Double- Density
* Recommended
12-35
Single and Double- Density
FORTRAN·80
8080/8085 ANS FORTRAN 77
INTELLEC® RESIDENT COMPILER
Meets and exceeds ANS FORTRAN 77
Subset Language Specification
Produces relocatable and linkable object
code compatible with resident PLlM·80
and 8080/8085 Macro Assembler
Supports Intel Floating Point Standard
with either the floating point support
library or the iSBC·310 High Speed
Mathematics Board
Full FORTRAN 77 language 1/0 support or
optional RMX·80 run·time library
Resident operation on Intellec®
Microcomputer Development System
and Intellec® Series II Microcomputer
Development System
Well defined 1/0 interface for configu·
ration with user·supplied drivers
Supports full symbolic debugging with
ICE·80™ and ICE·85™
Sophisticated code optimization insures
efficient program implementation
FORTRAN-80 is a computer industry-standard, high-level programming language and compiler that translates FORTRAN statements into relocatable object modules_ When the object modules are linked together and located into absolute program modules, they are suitable for execution on Intel® 8080/8085 Microprocessors, iSBC-80 OEM Computer
Systems, and Intellec® Microcomputer Development Systems. FORTRAN-80 meets and exceeds the ANS FORTRAN
77 Language Subset Specification 1. The compiler operates on the Intellec Microcomputer Development System under
the ISIS-II Disk Operating Systems and produces efficient relocatable object modules that are compatible for linkage
with PUM-80 and 8080/8085 Macro Assembler modules.
The ANS FORTRAN 77 language specification offers many powerful extensions to the FORTRAN language that are
especially well suited to Intel® 8080/8085 Microprocessor software development. Because FORTRAN-80 conforms to
the ANS FORTRAN 77 standard, the user is assured of compatibility with existing FORTRAN software that meets the
standard as well as a guarantee of upward compatibility to other computer systems supporting an ANS FORTRAN 77
Compiler.
1ANSI X3J3/90
12-36
FORTRAN·80
• The INCLUDE control permits specified source
files to be combined into a compilation unit at com·
pile time.
FORTRAN·SO LANGUAGE FEATURES
Major ANS FORTRAN 77 features supported by the
Intel® FORTRAN-80 Programming Language include:
o
Structured Programming is supported with the IF ...
THEN ... ELSE IF ... ELSE ... END IF constructs.
o
CHARACTER data type permits alphanumeric data
to be handled as strings rather than characters
stored in array elements.
o
Full 1/0 capabilities include:
Sequential and Direct Access files
Error handling facilities
Formatted, Free·formatted, and Unformatted
data representation
Internal (in·memory) file units provide capa·
bility to format and reformat data in internal
memory buffers
List Directed Formatting
• Supports arrays of up to seven dimensions.
o
o
FORTRAN·SO BENEFITS
FORTRAN-80 provides a means of developing applica·
tion software for Intel@ MCS-80/85 products in a
familiar, widely accepted, and computer industry·
standardized programming language. FORTRAN·80 will
greatly enhance the user's ability to provide cost·
effective solutions to software development for Intel
microprocessors as illustrated by the following:
Supports logical operators
.EQV.
- Logical equivalence
.NEQV.
- Logical nonequivalence
Major extensions to FORTRAN 77 in Intel FORTRAN-80
include:
o Direct 8080/8085 port 1/0 supported by intrinsic
subroutines.
o
Binary and Hexadecimal integer constants.
o
Well defined interface to FORTRAN-80 1/0 state·
ments (READ, OPEN, etc.), allowing easy use of
user·supplied 1/0 drivers.
o
User·defined INTEGER storage lengths of 1, 2 or 4
bytes.
o
User·defined LOGICAL storage lengths of 1, 2 or 4
bytes.
o
REAL STORAGE lengths of 4 bytes.
o
Bitwise Boolean operations using logical operators
on integer values.
o
Hollerith data constants.
o
Implicit extension of the length of an integer or
logical expression to the length of the left·hand
side in an assignment statement.
o
A format descriptor to suppress carriage return on
a terminal output device at the end of the record.
FORTRAN·SO COMPILER FEATURES
o
Optional Assembly Language code listing.
o
Comprehensive cross·reference, symbol attribute
and error listing.
Compiler controls and directives are compatible
with other Intel language translators.
o
o
Completely Complementary to Existing Intel Soft·
ware Design Tools - Object modules are linkable
with new or existing Assembly Language and PLiM
Modules.
o
Incremental Runtime Library Support - Runtime
overhead is limited only to facilities required by the
program.
o
Low Learning Effort - FORTRAN·80, like PLlM, is
easy to learn and use. Existing FORTRAN software
can be ported to FORTRAN-80, and programs
developed in FORTRAN·80 can be run on any other
computer with ANS FORTRAN 77.
o
Earlier Project Completion - Critical projects are
completed earlier than otherwise possible because
FORTRAN-80 will substantially increase program·
mer productivity, and is complementary to PLiM
Modules by providing comprehensive arithmetic,
1/0 formatting, and data management support in
the language.
o
Lower Development Cost - Increases in program·
mer productivity translates into lower software
development costs because less programming
resources are required for a given function.
o
Increased Reliability - The nature of high·level
languages, including FORTAN-80, is that they lend
themselves to simple statements of the program
algorithm. This substantially reduces the risk of
costly errors in systems that have already reached
production status.
o
Easier Enhancements and Maintenance - Like
PLlM, program modules written in FORTRAN-80 are
easier to read and understand than assembly
language. This means it is easier to enhance and
maintain FORTRAN-80 programs as system
capabilities expand and future products are
developed.
o
Comprehensive, Yet Simple Project Development
- The Intellec Microcomputer Development Sys·
tem, with the 8080/8085 Macro Assembler, PLlM-80
and FORTRAN-80 is the most comprehensive soft·
ware design facility available for the Intel
MCS-80/85 Microprocessor family. This reduces
development time and cost because expensive (and
remote) timesharing or large computers are not reo
quired.
Supports multiple compilation units in Single
source file.
o
o
Optional Reentrancy.
o
User·defined default storage lengths.
o
Optional FORTRAN 66 Do Loop semantics.
o
Source files may be prepared in free format.
Transparent interface for software and hardware
floating pOint support, allowing either to be chosen
at time of linking.
12-37
FORTRAN·BO
SAMPLE FORTRAN·80 SOURCE PROGRAM
LISTING
•
*
** TBIS PROGRA~ IS AN EXAMPLE OF ISIS-II FORTRAN-80 THAT
** CONVERTS TEMPERATURE BETWEEN CELSIUS AND FARENHEIT
PROGRAM CONVRT
CHARACTER*l CHOICE, SCALE
PRINT 100
** ENTER CONVERSION SCALE (C OR F)
PRINT 200
READ (5,300) SCALE
*
10
IF (SCALE .EO. 'C')
THEN
PRINT 400
** ENTER THE NUMBER OF DEGREES FARENHEIT
READ (5,*) DEGF
DEGC = 5./9.*(DEGF-32)
** PRINT THE ANSWER
WRITE (6,500) DEGF,DEGC
** RUN AGAIN?
PRINT 600
READ (5,300) CHOICE
IF (CHOICE .EQ. 'Y')
+
THEN
GOTO 10
ELSE IF (CHOICE .EQ. 'N')
+
THEN
CALL EXIT
ELSE
GO TO 20
END IF
ELSE IF (SCALE .EQ. 'F')
+
TBEN
** CONVERT FROM FARENHEIT TO CELSIUS
PRINT 100
READ (5,*) DEGC
DEGF = 9./5.*DEGC+32.
*. PRINT THE ANSWER
WRITE (6,800) DEGC,DEGF
GO TO 20
ELSE
** NOT A VALID ENTRY FOR THE SCALE
WRITE (6,900) SCALE
GOTO 10
END IF
FORMAT(' TEMPERATURE CONVERSION PROGRAM' ,11,
+' TYPE C FOR FARENHEIT TO CELSIUS OR' ,1,
+' TYPE F FOR CELSIUS TO FARENHEIT' ,11)
FORMAT(/,' CONVERSION? ',$)
FORMAT (A 1)
FORMAT(/,'ENTER DEGREES FARENHEIT: ',$)
FORMAT(/,F1.2,· DEGREES FARENHEIT = ',F1.2,' DEGREES CELSIUS-)
FORMAT(/,' AGAIN (Y OR N)? ',$)
FORMAT(/,' ENTER DEGREES CELSIUS: ',$)
FORMAT(/,F1.2,' DEGREES CELSIUS = ',F1.2,' DEGREES FARENHEIT',/)
FORMAT (/ , lH , A1 " NOT A VALID CHOICE - TRY AGAIN I ' , I)
END
+
*
*
*
20
*
*
*
100
200
300
400
500
600
100
BOO
900·
12·38
FORTRAN·ao
The FORTRAN-80 Compiler is an efficient, multiphase compiler that accepts source programs, translates them into
relocatable object code, and produces requested listings_ After compilation, the object program may be linked to other
modules, located to a specific area of memory, then executed_ The diagram shown below illustrates a program development cycle where the program consists of modules created by FORTRAN-80, PLlM-80 and the 8080/8085 Macro
Assembler_
ISIS-II
LOADER
:--
ISIS-II
TEXT
EDITOR
FORTRAN-80
SOURCE
ISIS-II
TEXT
EDITOR
ISIS-II
TEXT
EDITOR
PLIM-80
SOURCE
ASSEMBLY
LANGUAGE
SOURCE
RELOCATABLE
OBJECT
MODULE
-
DEBUG
VIA
MONITOR
-
OPTIONAL
ICE-BOTM
ICE_BSTM
IN-CIRCUIT
EMULATOR
-
PROM
PROGRAMMER
RELOCATABLE
OBJECT
MODULE
RELOCATABLE
OBJECT
MODULE
Required Software:
ISIS-II Diskette Operating System
- Single or Double Density
SPECIFICATIONS
OPERATING ENVIRONMENT
Optional Software:
iSBC-801 FORTRAN-80 Run-Time Software Package
for RMX-80
Required Hardware:
Intellec® Microcomputer Development System
- MDS-800, MDS-888
- Series II Model 220, Model 230
DOCUMENTATION PACKAGE
64K bytes of RAM memory
FORTRAN-80 Programming Manual (9800481)
Dual diskette drives
- Single or Double Density
ISIS-II FORTRAN-80 Compiler Operator's Manual
(9800480)
System console
- CRT or hardcopy interactive device
FORTRAN-80 Programming Reference Card (9800547)
SHIPPING MEDIA
Optional Hardware:
Li ne Pri nter
ICE-80™,ICE-85TM
Flexible Diskettes
- Single and Double Density
ORDERING INFORMATION
PRODUCT CODE
DESCRIPTION
MDS-301
FORTRAN-80 Compiler for Intellec
Microcomputer Development
Systems
12-39
BASIC-80
EXTENDED ANS 1978 BASIC
INTELLEC® RESIDENT INTERPRETER
Meets ANS 1978 standard for minimal
BASIC and adds many powerful
extensions
Supports the Intel floating point standard
and provides integer and string data types
Operates under the ISIS-II operating
system on Intellec and Intellec Series-II
Microcomputer Development Systems
Can call user subroutines written in
FORTRAN-80, PLlM-80, and 8080/85
macro assembler that are resident in the
Intellec memory
Full sequential and random disk file 1/0
with ISIS-II
Applications range from prototyping
microcomputer software to inexpensive
engineering and management problem
solving on the Intellec systems
Easily learned language and interactive
environment combine to provide a flexible and powerful facility for developing
programs to run on the Intellec Microcomputer Development Systems
BASIC is an industry standard, high·level programming language which is designed to be easily learned and used by
novices and experienced programmers alike. The interpreter provides an interactive environment which allows fast
and easy program development, testing, and debugging. BASIC is widely used for problem solving in engineering and
management; extensive software exists for business applications such as order entry, accounts receivable, accounts
payable, and inventory control, and engineering applications such as numeric and statistical analysis.
Intel's BASIC·80 meets the standards of ANS 1978 BASIC and extends them to take advantage of the software deve.'·
opment capabilities of the Intellec Microcomputer Development Systems. The matching of these resources with the
ease of programming in BASIC·80 provides a very effective tool for both microprocessor systems development and
inexpensive applications programming and problem solving on the Intellec systems .
..
..
..
..
..
12·40
BASIC·80
• Formatted print statement with the PRINT USING
function.
BASIC·80 LANGUAGE FEATURES
Standard ANS 78 BASIC features, all supported by
BASIC·80, include:
• ELSE clause for IF ... THEN statements.
• Matrices with up to 110 dimensions.
• String and numeric constants, variables, and arrays.
• Extensive string manipulation functions.
• FOR ... TO ... STEP ... NEXT statements for loop
execution.
• Boolean operators.
• Type conversion functions-integer, floating point,
and character.
• IF ... THEN statements for conditional execution.
• ON ... GOTO statements for computed branching.
• GOSUB/RETURN subroutine calls and returns.
• Built in scientific functions:
ABS
EXP
INT
LOG
RND
SGN
SQR
ATN
BENEFITS OF BASIC·SO
TAN
COS
SIN
• Added Value to the Intellec Systems-with BASIC-80
the Intellec Microcomputer Development Systems
can be effectively used in many engineering and
management applications.
• User defined single statement functions.
• Inexpensive and Accessible Computational Facilitythe ease of use and flexibility inherent in BASIC·80
and its interpretive environment fit well with the "at
hand" computational resources of the Intellec sys·
tems. The combination is a particularly useful tool for
obtaining fast and accurate results.
Major extensions to ANS 78 BASIC which BASIC·80 pro·
vides include:
• Support for the Intel single and double precision
floating pOint standard.
• Easy to Learn-the language is designed to be easily
understood and learned. Results are obtained faster
and people who may benefit from using the system
can do so easily.
• Disk file 1/0, supporting both random access and
sequential access files.
• Direct read and write to CPU 1/0 ports through the INP
and OUT functions.
• Aid in Microcomputer Software Design-microcom·
puter software can be prototyped in BASIC·80 to inex·
pensively develop and test program logiC.
• Direct memory read and write through the PEEK and
POKE functions.
• Calls to user·supplied external subroutines, which
may have been written in FORTRAN·80, PUM·80, or
8080/8085 Assembly Language and have been located
at absolute memory locations using the ISIS·II
facilities.
• Complemented by Existing Software-subroutines
written in PUM-80, FORTRAN-80, and ASM 8080/85
can be called from BASIC·80 programs.
• Program execution trace command.
• Easy to Enhance and Maintain-BASIC-80, being
straightforward and easi Iy understood, provides for
programs that are easy to maintain and modify in the
future.
SPECIFICATIONS
Optional Hardware:
• User directed error trapping and handling functions.
Line printer
Additional diskette drive
Operating Environment
Required Software:
ISIS·II Diskette Operating System
- Single or double density
Required Hardware:
Intellec Microcomputer Development System
- MDS-800, MDS-888
- Series-II Model 220, Model 230
Documentation Package:
Basic·80 Reference Manual (9800758A)
Basic-80 Programming Reference Card (9800774)
48K bytes of RAM memory
Diskette drive
- Single or double density
Shipping Media:
System console
- CRT or hard copy interactive device
Flexible diskettes
- Single and double density
12-41
BASIC·BO
EXAMPLE BASIC·BO PROGRAM
list
10 PRINT "THIS PROGRAM CALCULATES THE MEAN AND STANDARD"
20 PRINT " DEVIATION OF INPUT DATA"
30 S=0:V=0
40 INPUT "NUMBER OF VALUES";N
50 FOR 1=1 TO N
60 INPUT A(I)
70 S=S+A(I)
80 NEXT
90 S=S/N
100 REM CALCULATION OF VARIANCE
110 FOR 1=1 TO N
120 V=V+(A(I)-S) "2/N
130 NEXT
140 SD=SQR (V)
150 PRINT "MEAN=";S
160 PRINT "STANDARD DEVIATION IS=";SD
Ok
run
THIS PROGRAM CALCULATES THE MEAN AND STANDARD
DEVIATION OF INPUT DATA
NUMBER OF VALUES? 6
? 34.7
? 32.9
? 38.2
? 35
? 37.6
? 40.9
MEAN= 36.55
STANDARD DEVIATION IS= 2.642442
Ok
ORDERING INFORMATION
Product Code
Description
MDS·320
1515·11 BASIC·80
Disk·Based Interpreter
12·42
INTELLEC® SINGLE/DOUBLE DENSITY
FLEXIBLE DISK SYSTEM
Flexible Disk system providing high
speed Input/Output and data storage
for Intellec Microcomputer Development
Systems
Data recorded on double density
flexible disk is in soft·sectored format
which allows 112 million byte data
capacity with up to 200 files per flexi·
ble.disk
Available in both single density and
double density systems
Associated software supports up to
four double density drives and two
single density drives, providing up to
2.5 Megabytes of storage in one
system
Data recorded on single density flexi·
ble disk is in IBM soft· sectored format
which allows 1/4 million byte data
capacity with up to 200 files per flexi·
ble disk
Dynamic allocation and deallocation
of flexible disk sectors for variable
length files
The .Intellec® Flexible Disk System is a sophisticated, general purpose, bulk storage peripheral for use with the
Intellec Microcomputer Development System. The use of a flexible disk operating system significantly reduces program development time. The software system known as ISIS-II (Intel System Implementation Supervisor), provides the
ability to edit, assemble, compile, link, relocate, execute and debug programs, and performs all file management tasks
for the user.
FLEXIBLE DISK SYSTEM
12-43
FLEXIBLE DISK SYSTEM
puter Set. This a-bit processor includes four 3002 Central Processing Elements (2-bit slice per CPE), a 3001
Microprogram Control Unit, and 512 x 32 bits of 3604
programmable-read-only-memory (PROM) which stores
the microprogram. It is the execution of the microprogram by the microcomputer set which actually
effects the control capability of the Channel Board.
HARDWARE
The Intellec® flexible disk system provides direct
access bulk storage, intelligent controller, and two flexible disk drives_ Each single density drive provides 1/4
mi Ilion bytes of storage with a data transfer rate of
250,000 bits/second. The double density drive provides
V2 million bytes of storage with a data transfer rate of
500,000 bits/second. The controllers are implemented
with Intel's powerful Series 3000 Bipolar Microcomputer
Set. The controllers provide i nterfa'ce to the Intellec
System bus. Each single density controller will support
two drives. Each double density controlier will support
up to four drives. The flexible disk system records all
data in soft sector format.
The single/double density flexible disk controllers each
consists of two boards, the Channel Board and the Interface Board. These two printed circuit boards reside in
the Intellec System chassis. The boards are shown in
the photograph, and are described in more detail in the
following paragraphs.
This board is the same for either single or double density drives, except that the Series 3000 microcode is different.
INTERFACE BOARD
The Interface Board provides the flexible disk controller
with a means of communication with the flexible disk
drives, as well as with the Intellec system bus. Under
control of the microprogram being executed on the
Channel Board, the Interface Board generates those
signals which cause the read/write head on the selected
drive to be loaded (i.e., to come in contact with the flexible disk platter), cause the head to move to the proper
track and verify successful operation. The Interface
Board accepts the data being read off the flexible disk,
interprets synchronizing bit patterns, checks the validity of the data using a cyclic redundancy check (CRG)
polynomial, and then transfers the data to the Channel
Board.
During write operations, the Interface Board outputs the
data and clock bits to the selected drive at the proper
times, and generates the CRC characters which are then
appended to the data.
When the flexible disk controller requires access to
Intellec system memory, the Interface Board requests
the DMA master control of the system bus, and generates the appropriate memory command. The Interface
Board also acknowledges I/O commands as required by
the Intellec bus.
SINGLE/DOUBLE DENSITY CHANNEL BOARD
The Flexible Disk System is capable of performing
seven different operations: recalibrate, seek, format
track, write data, write deleted data, read data, and verify
CRC.
The channel board is different for single and double density drives, due to the different recording techniques
used. The single density controller boards support one
set of dual single density drives. The double density
controller boards support up to two sets of dual double
density drives (four drives total).
DOUBLE DENSITY INTERFACE BOARD
(SINGLE DENSITY INTERFACE BOARD
IS SIMILAR TO THE ONE SHOWN ABOVE)
The double density controller may co-reside with the
Intel single density controller to allow conversion of
single density flexible disk to double density format,
and provide up to 2.5M bytes of storage.
CHANNEL BOARD
The Channel Board is the primary control module within
the flexible disk system. The Channel Board receives,
decodes, and responds to channel commands from the
Central Processor Unit (CPU) in the Intellec system. The
Channel Board can access a block of Intellec system
memory to determine the particular flexible disk operations to be performed and fetch the parameters required
for the successful completion of the specified operation.
FLEXIBLE DISK DRIVE MODULES
Each flexible disk drive consists of read/write and control electronics, drive mechanisms, read/write head,
track positioning mechanism, and the removable flexible disk platter. These components interact to perform
the following functions:
• Interpret and generate control signals
• Move read/write head to selected track
• Read and write data
The control functions of the Channel Board have been
achieved with an B-bit microprogrammed processor,
designed with Intel's Series 3000 Bipolar Microcom12-44
FLEXIBLE DISK SYSTEM
library management, run-time supports, and utility
management.
ASSOCIATED SOFTWARE - INTEL
SYSTEMS IMPLEMENTATION
SUPERVISOR (lSIS·II)
ISIS-II provides automatic implementation of random access disk files. Up to 200 files may be stored on each 114
million byte flexible disk for single density system or on
each Y2 million byte flexible disk for double density
system. For more information, see the ISIS-II data specification sheet.
The Flexible Disk Drive System is to be used in conjunction with the ISIS-II Operating System. ISIS-II provides total file management capabilities, file editing,
ISIS·II OPERATIONAL ENVIRONMENTAL
FLEXIBLE DISK DRIVE PERFORMANCE
SPECIFICA TlON
ISIS-II
32K bytes RAM memory
48K bytes when using Assembler Macro feature
64K bytes when using PUM or Fortran
System Console
Single or Double density Flexible Disk Drive
Single
Density
Capacity (Unformatted):
Per Disk
Per Track
Capacity (Formatted):
Per Disk
Per Track
Data Transfer Rate
HARDWARE SPECIFICATIONS
MEDIA
Single Density
Flexible Disk
One Recording Surface
IBM Soft Sector Format
77 TrackslDiskette
26 Sectors/Track
128 Bytes/Sector
Double Density
Double Density Specified
Flexible Disk
One Recording Surface
Soft Sector Format
77 TrackslDiskette
52 SectorslTrack
128 Bytes/Sector
Access Time:
Track-to-Track
Head Settling Time
Average Random
Positioning Time
Rotational Speed
Average Latency
Recording Mode
PHYSICAL CHARACTERISTICS
CHASSIS AND DRIVES
Mounting:
Height:
Width:
Depth:
Weight:
Table-Top or Standard 19" Retma Cabinet
12.08 in. (30.68 cm)
16.88 in. (42.88 cm)
19.00 in. (48.26 cm)
64.0 Ib (29.0 kg)
MEDIA
CHASSIS
DC Power Supplies
Supplied Internal to the Cabinet
AC Power Requirements
3-wire input with center conductor (earth ground) tied
to chassis
Single-phase, 115 VAC; 60 Hz; 1.2 Amp Maximum (For
a Typical Unit)
230 VAC; 50 Hz; 0.7 Amp Maximum (For
a Typical Unit)
Temperature:
Operating:
Non-Operating:
Humidity:
Operating:
Non-Operating:
FLEXIBLE DISK OPERATING SYSTEM CONTROLLER
DC Power Requirements (All power supplied by Intellec
Development System)
5V @ 3.75A (typ), 5A (max)
INTERFACE BOARD
Single Density
5V @ 1.5A (typ), 2.5A (max)
3.1 megabits
41 kilobits
6.2 megabits
82 kilobits
2.05M bits
26.6K bits
250 kilobits/
sec
4.10 megabits
53.2 kilobits
500 kilobits/
sec
10 ms
10 ms
10 ms
10 ms
260 ms
360 rpm
83 ms
Frequency
Modulation
260 ms
360 rpm
83 ms
M2FM
ENVIRONMENTAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
CHANNEL BOARD
Single Density
Double
Density
15.6°C to 51.7"C
5°C to 55°C
8 to 80% (Wet bulb 29.4 0c)
8 to 90%
DRIVES AND CHASSIS
Temperature:
Operating:
10°C to 38°C
Non-Operating: - 35°C to 65°C
Humidity:
Operating:
20% to 80% (Wet bulb 26.7"C)
Non-Operating: 5% to 95%
CONTROLLER BOARDS
Temperature:
Operating:
Oto55°C
Non-Operating: - 55°C to 85°C
Humidity:
Up to 95% relative humidity without
Operating:
condensation
Non-Operating: All conditions without condensation of water or frost
Double Density
5V @ 3.75A (typ), 5A (max)
Double Density
5V @ 1.5A (typ), 2.5A (max)
-10V @ O.lA (typ),
0.2A (max)
12-45
FLEXIBLE DISK SYSTEM
EQUIPMENT SUPPLIED
DOUBLE DENSITY
Cabinet, Power Supplies, Line Cord, Two Drives
Double Density FDC Channel Board
Double Density FDC Interface Board
Dual Auxiliary Board Connector
Flexible Disk Controller Cable
Flexible Disk Peripheral Cable
Hardware Reference Manual
Reference Schematics
ISIS-II Double Density System Disk
ISIS-II System User's Guide
SINGLE DENSITY
Cabinet, Power Supplies, Line Cord, Two Drives
Single Density FDC Channel Board
Single Density FDC Interface Board
Dual Auxiliary Board Connector
Flexible Disk Controller Cable
Flexible Disk Peripheral Cable
Hardware Reference Manual
Reference Schematics
ISIS-II Single Density System Disk
ISIS-II System User's Guide
OPTIONAL EQUIPMENT
MDS-640
MDS-BLD
MDS-DDR
Rack Mount Kit
10 Blank Flexible Disks
Second Drive Cabinet with two additional
drives
ORDERING INFORMATION
Part Number
MDS-2DS/110V
2DS/220V
MDS-DDS/110V
DDS/220V
MDS-DDR/110V
DDR/220V
Description
Flexible Disk drive unit with
drives, single density drive
troller, software, and cables_
Flexible Disk drive unit with
drives, double density drive
troller, software, and cables.
two
contwo
con-
Add-on drive unit with two drives
and double density cable, without
controller and software. Can be
used with double density controller.
12-46
1515·11
DISKETTE OPERATING SYSTEM
MICROCOMPUTER DEVELOPMENT SYSTEM
Supports resident, high level program·
ming languages, PLIM and FORTRAN
Supports up to four double density drives
and two single density drives, providing
up to 2.5 megabytes of storage in one
system with up to 200 files per diskette
Provides dynamic allocation and de·
allocation of diskette sectors for
variable length files
Relocating MCS·80/MCS·85 macro·
assembler contains extended macro and
conditional assembly capability
Linker automatically combines
separately assembled or compiled pro·
grams into single relocatable module
Command file facility allows console
commands to be submitted from
diskette file
Library manager creates and updates
program libraries
Diskette operating system functions
callable from user programs
Supports all standard Intellec
peripherals
Diskette system text editor provides
string search, substitution, insertions,
and deletion commands
Provides access to all Intellec monitor
facilities
The 1515·11 Microcomputer Development System Diskette Operating System is a sophisticated, general purpose, high
speed data handler and file manipulation system. It provides the ability to edit, assemble, compile, link, relocate,
execute, and debug programs, and performs all user file management tasks. The 1515·11 operating system resides on
the system diskette and supports a broad range of user oriented design aid software. Total file management and input
editing features greatly reduce software development time. The 1515·11 relocating macroassembler, linker, object
locator, and library manager may be loaded from the diskette in seconds. All passes of the assembler may be executed
without the need for user intervention. Object code and listings may be directed to any output device, or stored as
diskette files. Powerful system console commands are provided in an easy to use context. Monitor mode may be
entered by a special prefix to any sytem command or program call.
12·47
ISIS·II
Call Capability - The delete, rename, and attribute
assignment commands, along with a set of file 1/0
routines, are callable from user written programs. This
allows the user to open, close, read, and write diskette
files, access standard peripheral devices, write error
messages, and load other programs via simple program
call statements.
FUNCTIONAL DESCRIPTION
The ISIS-II operating system resides on the system diskette and supports a broad range of user oriented design
aid software_ Total file management and input editing
features greatly reduce software development time. The
ISIS-II relocating macroassembler, linker, object locator,
and library manager may be loaded from the diskette in
seconds. All passes of the assembler may be executed
without the need for user intervention. Object code and
listings may be directed to any output device, or stored
as diskette files. A diagram of the ISIS-II system program development flow is shown in Figure 1.
ISIS·II Files
A file is a user defined collection of information of
variable length. ISIS-II also treats 'each of the standard
Intellec system peripherals as files through preassignment of unique file names to each device. In this manner
data may be copied from one device to another (i.e., tape
reader to tape punch) using the same command required
to copy one diskette data file to another. ISIS-II provides
automatic implementation of random access disk files.
Each file is identified by a user chosen name unique on
its diskette. Up to 200 files may be stored on each
diskette.
Command
Initialize
disk
Operation
Initializes a diskette for use by the system. Requires only one disk drive.
Attribute
assignment
Assigns specified attributes to a file,
such as write-protect.
Copy
Creates copies of existing diskette
files or transfers files from one device
to another.
Delete
Removes a file from the diskette,
thereby freeing space for allocation of
other files.
Directory
Lists name, size, and attributes of files
from a specified diskette directory.
Rename
Allows diskette files to be renamed.
Format
Initializes a diskette for use by the system. (Use with two or more drives.)
Debug
Loads a specified program from a diskette into memory and then transfers
control to the Intellec monitor for execution and or debugging.
Submit
Provides capability for executing a
series of ISIS-II commands previously
written to a diskette file.
ISIS·II System Commands
ISIS-II system commands are designed to provide the
user with a powerful, easy to use program and file manipulation capability. Several commands have the capability of operating on several files at once via the wildcard
file naming convention. As an example, the command
DELETE .OBJ deletes all files in the diskette directory
with the suffix .OBJ. A summary of ISIS-II system commands is presented in Table 1.
*
Table 1. ISIS·II System Commands
Figure 1_ Program Development Flow USing ISIS-II Disk Operating System
12-48
ISIS·II
ISIS·II Text Editor
The ISIS-II text editor is a comprehensive tool for
assembly language, PUM, and FORTRAN program entry
and correction for Intel microcomputers_ Its command
set allows either entire lines of text or individual characters to be manipulated within a line.
Program Entry - Programs may be entered from the
console keyboard or may be loaded directly. Text is
stored internally in the editor's workspace, and may be
edited with the following commands:
• string insertion or deletion
• string search
• string substitution
Utility Commands - To facilitate the use of these
editing commands, utility commands are used to
change positions in the workspace. These include:
• move pointer by line or by character
• move pointer to start of workspace
• move pointer to end of workspace
Storage - The contents of the workspace are stored on
diskette and can be immediately accessed by ISIS-II
commands or other programs, such as the ISIS-II MCS80/MCS-85 macroassembler.
ISIS·II MCS·80/MCS·85 Relocating
Macroassembler
Address Translation - The ISIS-II MCS-80/MCS-85
macroassembler translates assembly language mnemonics into relocatable and/or absolute object code
modules. In addition to eliminating the errors of hand
translation, the ability to refer to program addresses
with symbolic names makes it easy to modify programs
by adding or deleting instructions. Extended macro
capability eliminates the need to rewrite similar sections of code repeatedly, and thus simplifies program
documentation. Conditional assembly permits the
assembler to include or delete sections of code that
may vary from system to system, such as the code required to handle optional external devices. Additionally,
the user is allowed complete freedom in aSSigning the
location of code, data, and stack segments.
List File - The ISIS-II Assembler accepts diskette file
input and produces a relocatable object file with corresponding symbol table and assembly listing file, including any error messages. A cross reference listing is also
ORDERING INFORMATION
Part Number
Description
MDS-2DS or
MDS-DDS 220
Diskette operating
system
12-49
optionally produced. The list file may then be examined
from the system console or copied to a specified list
device.
Object File - The relocatable object file generated by
the assembler may be combined with other object programs residing on the diskette to form a single relocatable object module or it can be converted to an absolute
form for subsequent loading and execution.
ISIS·II Linker
The ISIS-II linker provides the capability to combine the
outputs of several independently compiled or assembled object modules (files) into a single relocatable
object module. The linker automatically resolves all
external program and data references during the linking
process. Object modules produced from previous link
operations may be easily linked to a new module. ISIS-II
also provides facilities to ease the generation of overlays. An optional link map showing the contents and
lengths of each segment in the output module can be
requested. All unsatisfied external references are also
listed. If requested by the user, the ISIS-II linker can
search a specified set of program libraries for routines
to be included in the output module.
ISIS·II Object Locator
The ISIS-II locate program takes output from either the
resident FORTRAN or PUM compilers, the macroassembler, or the linker and transforms that output from
relocatable format to an absolute format which may
then be loaded via the standard ISIS-II loader, or loaded
into an appropriate in-circuit emulator (ICE) module.
During the locate process, code, data, and stack segments may be separately relocated, allowing code to be
put in areas to be subsequently specified as ROM, while
data and the stack are directed to RAM addresses. A
locate map showing absolute addresses for each code
and data segment and a symbol table dump listing symbols, attributes, and absolute address may also be
requested.
ISIS·II Library Manager
The ISIS-II Library Manager program provides for the
creation and maintenance of a program library containing Intel-provided and user-written programs and subroutines. These library routines may be linked to a program using the ISIS-II linker. Several libraries, each containing its own set of routines, may be created.
INTELLEC PROMPT 48
MCS·48 MICROCOMPUTER DESIGN AID
-256 bytes expandable RAM data memory
in PROMPT system
Complete low cost design aid and
EPROM programmer for revolutionary
MCS-48 single component computers
Simplifies microcomputing, allowing user
to enter, run, debug, and save machine
language programs with calculator-like
ease
Utilizes two removable 8-bit MCS-48
CPUs
8748 CPU with erasable, reprogrammabie on-chip program memory
8035 CPU with off-chip program
memory
1K-byte erasable, reprogram mabie onchip (8748), expandable program memory, 1K-byte RAM in PROMPT system
64 bytes RAM on-chip, expandable
register memory
27 on-chip TTL compatible expandable
110 lines
On-chip clock, internal timer/event
counter, two vectored interrupts, eight
level stack control
Single + 5V DC system power
requirement
Integral keyboard and displays (no teletypewriter or CRT terminal required)
Extensive PROMPT 48 monitor, allowing
system 110, bus, and memory expansion
Includes comprehensive design library
The Intel lee Prompt 48 MCS·48 Microcomputer Design Aid is a low cost, fully·assembled design aid for the revolu·
tlonary 8748 single component microcomputer. PROMPT 48 simplifies the programming of MCS·48 systems - pro·
grams may be entered and debugged with calculator·like ease on the large, informative display and keyboard panel.
The comprehensive design library with tutorial manual is ideal for newcomers to microcomputing. PROMPT 48's
panel connector allows easy access to 110 ports and system bus. Thus users can expand program memory beyond the
1K bytes provided internally.
12·50
INTELLEC PROMPT 48
FUNCTIONAL DESCRIPTION
"PROMPT" stands for PROgraMming Tool. It is a programmer for 8748 EPROMs, and a versatile aid for
debugging MCS-48 programs. Programs can be entered
via its Integral panel keyboard, programming socket, or
serial channel. Almost any terminal can be Interfaced to
the serial channel, including a teletypewriter, CRT, or an
Intellec microcomputer development system. Intellec
PROMPT 48 simplifies the programming of MCS·48
systems. Like the 8748 it is radically new, highly integrated, and expandable. Like the MCS·48 family, it is
low cost, and ideal for small applications and programs.
It is a deSign aid, not a development system with
sophisticated software and peripherals.
MCS·48 Processors
PROMPT 48 comes complete with two of Intel's revolutionary MCS-48 processors: an 8748·4 Single Component 8-Bit Microcomputer and and 8035-4 Single Component 8-Bit Microcomputer. Advances in n-channel MOS
technology allow Intel, for the first time to integrate into
one 40'pin component all computer functions:
8-bit CPU
1K x 8-bit EPROM/ROM program memory
64 x 8-bit RAM data memory
27 input/output lines
8·bit timer/event counter
Performance - More than 90 instructions - each one
or two cycles - make the single chip MCS-48 equal in
performance to most multi-chip microprocessors. The
MCS-48 is an efficient controller and arithmetic processor, with extensive bit handling, binary, and BCD
arithmetic instructions. These are encoded for
minimum program length; 70% are Single byte operation codes, and none is more than two bytes.
Flexibility - Three interchangeable, pin-compatible
devices offer flexibility and low cost in development and
production, as follows:
8748 - with user-programmable and erasable EPROM
program memory for prototype and pre-productions
systems.
8048 - with factory-programmed mask ROM memory
for low-cost, high volume production.
8035 - without program memory, for use with external
program memories.
Circuitry - Each MCS-48 processor operates on a
single + 5V supply, with internal oscillator and clock
driver, and circuitry for Interrupts and resets. Extra circuitry Is In the 8048 ROM processor to allow low power
standby operation. The 64 x 8 RAM data memory can be
independently powered.
Compatibility - For systems requiring additional compatibility, the MCS-48 can be expanded with the new
8243 I/O expander, 8155 I/O and 256-byte RAM, 8755 I/O
and 2K-byte EPROM, or 8355 I/O and 2K ROM devices.
MCS-48 processors readily interface to MCS-80/85
peripherals and standard memories.
Memory Capacity
PROMPT 48 is a complete, fully assembled and powered
microcomputer system including program memory, data
memory, I/O, and system monitor beyond that available
on MCS-48 single component computers. 1K bytes of
PROMPT system RAM serve as "writable program memory" - a ROM simulator for the program memory on
each MCS-48 computer. 256 bytes of PROMPT system
RAM serve as "external data memory," beyond the 64
register bytes on each MCS·48 computer. Users may fur·
ther expand program or data memory via the panel I/O
ports and bus connector.
Programming
Programs written first in assembly language, are
entered in machine language and debugged with
calculator-like ease on the large, informative display
and keyboard panel. Most MCS-48 operations can be
specified with only two keystrokes. Once entered,
routines can be exercised one instruction (single step)
or many instructions at a time. The principal MCS-48
register - the accumulator - is displayed while single
stepping. Programs can be executed in real time (GO
NO BREAK) or with as many as eight different breakpoints (GO WITH BREAK).
Control
PROMPT 48 can be fully controlled either by the panel
keyboard and displays, or remotely by a serial channel.
Thus a teletypewriter or CRT can be used but neither Is
required.
Access
The PROMPT panel I/O ports and bus connector allow
easy access to all MCS-48 pins except those reserved
for control by the PROMPT system, namely EA external
access, SS single step, and X1, X2 clock inputs.
Optional Expansion
PROMPT 48 may be expanded beyond the resources on
both the MCS-48 single component computer and the
PROMPT system. External program and data memory
may be interfaced and input/out ports added with the
8243 I/O expander.
12-51
INTELLEC PROMPT 48
FEATURES
Single Component Computer
The 8748 is the first microcomputer fully integrated on
one component. All elements of a computing system are
provided, including CPU, RAM, I/O, timer, interrupts, and
erasable, reprogram mabie nonvolatile program memory.
Programming Socket
PROMPT's programming socket programs this revolutionary "smart PROM"-the 8748-in a highly reliable,
convenient manner. A fail-safe interlock ensures the
device is properly inserted before applying programming pulses. Each location may be individually programmed, one byte at a time. A read-before-write
programming algorithm prevents device damage by
inadvertently programming unerased memory.
real time - after each instruction the MCS-48 program
counter is compared against pending breakpoints. If no
break is encountered, execution resumes. The go single
step (GO SINGLE STEP) mode exercises one instruction
at a time. Commands are like sentences, with parameters separated by [!] NEXT. Each command ends with
[!] EXECUTE/END. In addition to the PROMPT basic
commands, thirteen functions simplify programming.
Each is started merely by pressing a hex datalfunction
key and entering parameters as required, as shown in
Table 1.
MCS·48 Processors
The execution socket accepts either an 8035 or an 8748
MCS-48 processor. Both are supplied with each
PROMPT 48, and either can serve as heart of .the
PROMPT system. There are no processors within the
PROMPT 48 mainframe, which instead contains monitor
ROM and RAM, user RAM, peripherals, drivers, and
sophisticated control circuitry. Once a processor is
seated in the execution socket and power is applied, the
PROMPT system comes to life. Various access modes
may be selected such as program execution from
PROMPT system RAM, or from on-chip PROM. Thus programs may first be executed from PROMPT RAM with
the 8035 processor. When debugging is complete, the
8035 (execution socket) processor can program the 8748
(programming socket) processor. Finally, a programmed
8748 processor may be exercised by itself from the
execution socket. The execution socket processor runs
either monitor or user programs.
System Monitor
The system reset command initializes the PROMPT
system and enters the monitor. The monitor interrupt
command exits a user program gracefully, preserving
system status and entering the monitor. The user interrupt command causes an interrupt only if the PROMPT
system is running a user program. A comprehensive
system monitor resides in four 1K-byte read only
memories. It drives the PROMPT keyboard and displays
and responds to commands and functions. The top 16
bytes of on-chip program memory must be used by the
PROMPT system to switch between monitor and user
programs. It requires one level of the MCS-48 eight-level
stack.
Commands
PROMPT 48's commands are grouped and color-coded
to simplify access to the 8748'5 separate program and
data memory. Registers, data memory, or program memory, may be examined and modified with the examine
and modify commands. Then either the next or previous
register and memory locations may be accessed with
one keystroke. Programs may be exercised in three
modes. The go no break (GO NO BREAK) runs in real
time. The go with break (GO WITH BREAK) mode is not
12-52
INTELLEC PROMPT 48
Cable Interface
Key
An optional cable, PROMPT-SER, directly connects the
PROMPT system to virtually any terminal via a rear
access slot.
Function
Operation
[}]
Port 2 map
Allows specification of direction of each pin
on port 2. Port 2 is multiplexed to address
external program memory and expand 110.
Thus it must be buffered; the P2 map command establishes the direction of buffering.
[]
Program EPROM
Byte search
(with optional
mask)
Programs 8748 EPROMs.
Sweeps through register, data, or program
memory searching for byte matches. Starting and ending memory addresses are spe·
cified.
[}]
Word search
(with optional
mask)
Sweeps through register, data, or program
memory searching for word matches. Start·
ing and ending memory addresses are spe·
cified.
[}]
Hex calculator
Computes hexadecimal sums and differ·
ences.
[]
8748 program
Similar to program EPROM, but ensures that
the top of program memory contains monitor re-entry code for debugging.
~
for debug
[!]
Compare
Verifies any portions of EPROM program
memory against PROMPT memory.
[}]
Move memory
Allows blocks of register, data, or program
memory to be moved.
[!J
Access
Specifies one of six access modes for PROMPT 48. For example EPROM, PROMPT
RAM, or external program memory, and a
variety of inputloutput options may be
selected.
[]I
Breakpoint
Allows any or all of the eight breakpoints to
be set and cleared.
@]
Clear
Clears portions of register, data, or program
memory.
[QJ
Dump
Dumps register, data, or program memory to
PROMPT's serial channel: for example, a
teletypewriter paper tape punch.
[!]
Enter
Enters (reads) register, data, or program
memory from PROMPT's serial channel.
[£J
Fetch
Fetches programs from EPROM to PROMPT
RAM.
Table 1. PROMPT 48 Commands and Functions
Access
Easy access to the pins of the executing processor is
provided via the 1/0 ports and bus connector. Only the
EA external access, SS single step, and X1, X2 clock
inputs are reserved for the PROMPT system.
Expansion
Program or data memory may be expanded beyond that
provided on-Chip or in the PROMPT system. 1/0 ports
may be expanded, as with the 8243, or peripheral controllers may be memory-mapped. The 1/0 ports and Bus
connector allows the execution socket processor to be
directly interfaced to prototype systems, yet be controlled from the PROMPT panel.
Control
The commandlfunction group panel keyboard and displays completely control PROMPT 48-a teletypewriter
or CRT terminal is not needed. A hyphen prompting
character appears whenever a command or function can
be entered. Addresses and data are shown whenever
examining registers and memory. Parameters for commands and functions are also shown.
12-53
INTELLEC PROMPT 48
concepts. PROMPT's handy, pocket·sized reference
card let can be affixed to the mainframe. Programming
pads aid In the organization and documentation of programs. These features, plus a comprehensive design
library of manuals, articles, and application notes,
make the Intellec PROMPT 48 Ideal for the newcomer to
mlcrocomputlng.
Documentation
The PROMPT 48 manual Includes chapters for the
reader with little or no programming experience. Topics
treated range from number systems to microcomputer
hardware design. A novel, unifying set of tutorial
diagrams - MICROMAPS - simplify microcomputer
User Interrupt - causes an interrupt only if the
PROMPT system is running a user program.
SPECI FICATIONS
Timing
The processor traps to location 316. The MCS·48 timer/event counter is not used by the PROMPT system and is
available to the user. Either timer flag or interrupt will
signal when overflow has occurred. The timer interrupt
can be used only in the go-no·break (real time) mode.
BasiC Instruction - 2.5 ,.,s
Cycle Time - tCY = 2.5,.,s
Clock - 6 MHz ± 0.1%
Memory Bytes
The 8748 contains 64 bytes of register memory, no external data memory, and 1024 bytes of RAM program
memory. The PROMPT system provides 256 bytes of external data memory, and 1024 bytes of RAM program
memory. PROMPT RAM program memory can be used
In place of the on-chip EPROM program memory; thus
programs less than 1024 bytes may be designed. For
larger programs additional memory can be directly Interfaced to the MCS-48 bus via the PROMPT panel I/O
ports and bus connector.
EPROM Programming
PROMPT 48 provides a programming socket to directiy
program 8748s. Programs are loaded into the PROMPT
RAM program memory via keyboard. EPROM, teletypewriter, or other serial interface. A fail-safe interlock
ensures programming pulses are applied only if the
device is properly inserted. Inadvertant reprogramming
is prevented by a read·before-write programming algo·
rithm. Each location may be Individually programmed,
one byte at a time.
Memory Configuration
Memory
Register
Data
Program
Maximum
On Chip
In PROMPT 48
64
3328
4096
64
0
1024 EPROM
0
256
Panel I/O Ports and Bus Connectors
All MCS-48 pins, except five, are accessible on the I/O
ports and bus connector. The five reserved for PROMPT
system control are EA external access, SS single step,
X1, X2 crystal inputs, and 5V. Due to internal buffering
of the MCS-48 bus, access times will be negligibly
degraded by the PROMPT system. Since MCS-48 processors do not communicate internal address gate
status, bus data must be driven out if neither PSEN nor
RD is asserted.
1024 RAM
I/O Ports
All MCS-48 I/O ports are accessible on the PROMPT
panel connector.
Bus - A true bidirectional 8·blt port with associated
strobes. If the bidirectional feature is not needed, bus
can serve as either a statically latched output port or a
non·latching input port. Input and output lines cannot
be mixed.
Ports 1 and 2 - Data written to these 8-bit ports Is
latched and remains unchanged until written. As inputs
these lines are not latching. The lines of ports 1 and 2
are called quasi bidirectional. A special output structure
allows each line of port 1 and half of port 2 to serve as an
input, an output, or both. Any mix of input, output, and
both lines is allowed.
System Devices
Both user programs and the PROMPT monitor enjoy access to system devices: serial 110, panel displays, and
keyboard. These are memory-mapped to program
memory addresses beyond 2K.
Serial 110 - The serial I/O port (data 82016, control 821 16 )
is defined by software and jumpers for 110 baud, 20 mA
current loop, btl! can easily be jumpered for other baud
rates and RS232C levels. Asynchronous or synchronous
transmisSion, data format, control characters, and parity can be programmed.
TO, T1, and INT - Three pins that can serve as inputs. TO
can be deSignated as a clock output. Input/output can
be expanded via the PROMPT panel connector with a
special I/O expander (8243) or standard peripherals.
Panel Displays - Eight display ports (data 810-817 1el
allow each of the panel displays to be written from user
programs. Data written on a display device will time out
after a fixed interval. Displays must be refreshed on a
polled or interrupt-driven basis. User programs can call
software drivers which provide this capability.
Reset and Interrupts
Reset - Initializes the PROMPT system and enters the
monitor.
Monitor Interrupt - exits a user program gracefully,
preserving system status and entering the monitor.
12-54
INTELLEC PROMPT 48
Panel 1/0 Ports and Bus Connector - 3M 3425 Flat
Crimp. A complete cable set including wlrewrap header
for prototyplng Is included with each PROMPT.
Keyboard - Software Is used to debounce the panel
keyboard (data 810 16 ), The monitor's input routines (see
Software Drivers) provide this debouncing and can be
called from user programs.
Equipment Supplied
Commands
Single step}
With break
No break
PROMPT 48 mainframe with two MCS-48 processors
(8748, 8035), display/keyboard, EPROM programmer,
power supply, cabinet, and ROM-based monitor.
110 V AC power cable
110 or 220 V AC
Fuse
Panel I/O ports
Bus connector cable set
Go
Register}
{ Data
Memory
Program
Open previous/clear/entry El Next D Execute/End
Examine/modify
Functions
~
~
I!l
~
lliJ
III
lliJ
IU
IAl
[[]
~
lID
[]
IE;
Physical Characteristics
Port 2 map
Program EPROM (8748)
Search (R, 0 or P)* memory for 1 byte, optional
mask
Search (R, 0 or P) memory for 2 bytes, optional
mask
Hexadecimal calculator + ,8748 program EPROM for debug
Compare EPROM with memory
Move memory (R, 0 or P)
Access
Breakpoi nt
Clear memory (R, 0 or P)
Dump memory (R, 0 or P)
Enter (read) memory (R, 0 or P)
Fetch EPROM program memory
Height - 5.3 in. (13.5 cm) max
Width - 17 in. (43.2 cm)
Depth - 17 in. (43.2 cm) max
Weight - 21 lb. (9.6 kg)
Electrical Characteristics
Pc- 'er Requirements - either 115 or 230V AC (± 10%)
may be switch selected on the mainframe. 1.8 amps
max current (at 125 V AC).
Frequency - 47-63 Hz
Environmental Characteristics
Operating Temperature - O·C to + 40·C
Non-Operating Temperature - 20·C to + 65·C
Reference Manuals
Note
"A, D, or P is register, data, or program.
9800402 Intellec PROMPT 48 User's Manual
(SUPPLIED)
9800270 - MCS·48 User's Manual (SUPPLIED)
9800255 - MCS-48 and UPI·41 Assembly language
Programming Manual (SUPPLIED)
Software Drivers
Panel Keyboard In - KBIN, KDBIN
Panel Display Out - DGS6, DGOUT, HXOUT, BlK,
REFS, ENREF
Serial Channel - CI, CO, RI, PO, CSTS
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Connectors
Serial 1/0 - 3M 3462-0001 Flat Crimp/AMP 88106-1 Flat
Crimp/ TI H312113 Solder/AMP 1-583485-5 Solder.
ORDERING INFORMATION
Part Number
Description
PROMPT-48 or
PROMPT·48·220V
Intellec PROMPT 48 MCS-48 microcomputer design aid. Complete with
two MCS-48 processors (8748 and
8305), EPROM programmer, integral
keyboard, displays, and system
monitor in ROM.
PROMPT·SER
Serial cable for connecting PROMPT
to TTY, CRT
12·55
ICE·49
MCS·48 IN·CIRCUIT EMULATOR
Emulates 8049, 8048, 8748, 8039, 8035, and 8021* Microcomputers
Extends Intellec microcomputer develop·
ment system debug power to user con·
figured system via external cable and
40·pin plug, replacing system MCS·48
device
Emulates user system MCS·48 device in
real time
Eliminates need for extraneous debug·
ging tools residing in user system
Collects bus,register, and MCS·48
status information on instructions
emulated
Shares static RAM memory with user
system for program debug
Provides capability to examine and alter
MCS·48 registers, memory, and flag
values, and to examine pin and port
values
Provides hardware comparators for user
designated break conditions
Integrates hardware and software efforts
early to save development time
The ICE-49 MCS-48 In-Circuit Emulator module is an Intellec-resident module that interfaces with any MCS-48 system.
The MCS-48 family consists of the 8049, 8048, 8748, 8039, 8035, and 8021 microcomputers. The ICE-49 module interfaces with an MCS-48 system through a cable terminating in an MCS-48 pin-compatible plug which replaces the
MCS-48 device in the sytem. With the ICE-49 plug in place, the designer has the capability to execute the system in
real time while collecting up to 255 instruction cycles of real-time trace data. In addition, he can Single step the system
program to monitor more closely the program logic during execution. Static RAM memory is available through the
ICE-49 module to emulate MCS-48 program and data memory. The designer can display and alter the contents of data
and replacement RAM control memory, internal MCS-48 registers and flags and I/O ports. Powerful debug capability is
extended into the MCS-48 system while ICE-49 debug hardware and software remain inside the Intellec system. Symbolic reference capabil ity allows the designer to use meaningful symbols rather than absolute values when examining
and modifying memory, registers, flags, and I/O ports in this system.
*EM1 emulator board is also required.
12-56
ICE·49
FUNCTIONAL DESCRIPTION
Integrated Hardware/Softw81ei:r&";IPJ.Pllent
Debug Capability Inside User System
Real· Time Trace
The ICE-49 module captures trace information while the
designer is executing programs in real time. The instruc·
tions executed, program counter, port values for bus 0,
port 1 and port 2, and the values of selected MCS-48
status lines are stored for the last 255 instruction cycles
executed. When retrieved for display, code is disassem·
bled for user convenience. This provides data for deter·
mining how the user system was reacting prior to emu·
lation break, and is available whether the break was user
initiated or the result of an error condition. For more
detailed information on the actions of internal registers,
flags, or other system operations, the user may operate
in single or multiple step sequences tailored to system
debug needs.
Batch Testing
In conjunction with the 1515-11 diskette operating
system, the ICE-49 module can run extensive system
diagnostics without operator intervention. The designer
or test engineer can define a complete diagnostic exer·
cise, which is stored in a file on the diskette. When actio
vated with an 1515-11 submit command, this file can
instruct the ICE-49 module to execute the diagnostic
routine and store the results in another file on the
diskette. Results are available to the designer at his con·
venience. In this way, routine diagnostics and long term
testing may be done without tying up valuable man·
power.
-------, r------------,
EMULATOR BOARO
I
I
SYNC 0
CONTROL PROCESSOR BOARD
I
I
II
r-'--'-,-.l.1-------1
II
II
CABLE
BUFFER
SYNC 1
'--:; ::"~,;;:;~
The user prototype need consistof,np m9r~;\f1an,an
MCS-48 socket and timing logic to begininteg,ratldn'cOfll
software and hardware development efforts: .Through~if:h
the ICE-49 module mapping capabilities, Intellec system "
resources can be accessed to replace prototype me'mory. Hardware designs can be tested using the system
software to drive the final product. Thus, the system in·
tegration phase, which can be costly when attempting
to mesh completed hardware and software products,
becomes a convenient two·way debug tool when begun
early in the design cycle.
The ICE-49 module provides the user with the ability to
debug a full prototype or production system without
introducing extraneous hardware or software test tools.
The module connects to the user system through the
socket provided for the MCS-48 device in the user
system. Intellec memory is used for the execution of the
ICE-49 software. The Intellec console and file handling
capabilities provide the designer with the ability to com·
municate with the ICE-49 module and display informa·
tion on the operation of the prototype system. The
ICE-49 module block diagram is shown in Figure 1.
USER SOCKET
_0_"";,
INTERNAL
TIMER
II
II
II
I
I
I
I
I
I
II
II
II
f---,-".:::o:.:c:,'
I I
P1
P2A
CONTROL
PROGRAM
8080
CONTROL
PROCESSOR
8049 OR 8048
W/INTERNAL
MONITOR P~~I---------:'-:-::c:---'
I
CONTROL
SCRATCH
PAD
I
I
I
I
I
I
~ I
~ I
~ I
~ I
w
~>- I
:!: I
I
I
LU
~
I
II
I
L ____________ ~ L____________ ~
Figure 1. ICE·49 Module Block Diagram
12-57
ICE·49
'\\I1l~)tt~/
Memory Mapping
Intel 8080 to communicate
cessor via a common memory spade;:,,6,?
trois an internallCE-49 bus for intramod41Ef '"
tion. ICE-49 hardware consists of two p6,~~f:
Reference Manuals
9800632 -
For Bus:
VOL = 0.5V (max), IOL = 25 mA
VOH = 3.65V (min), IOH = -1 mA
Part Number
t~·'4Ci~c.c
Operating Humidity without condensation
Output Impedance - @ ICE·49 user socket pins:
P1, P2:
VOL = 0.5V (max), IOL = 16 mA
VOH = Vee (10K pullup)
=
O°C
Assembled kit to upgrade ICE·48 to
ICE-49 capability. ICE·49 emulator
board, 8049/8048 CPU components
with internal monitor program,
ICE·49 firmware and diskette soft·
ware included.
12·60
ICE·80
8080 IN·CIRCUIT EMULATOR
Connects Intellec system to user con·
figured system via an external cable and
40·pin plug, replacing the user system
8080
Eliminates need for extraneous debug·
ging tools residing in user system
Provides address, data, and 8080 status
information on last 44 machine cycles
emulated
Allows real·time (2 MHz) emulation of
user system 8080
Provides capability to examine and alter
CPU registers, main memory, pin, and
flag values
Shares Intellec RAM, ROM, and PROM
memory and Intellec I/O facilities with
user system
Checks for up to three hardware and four
software break conditions
Integrates hardware and software
development efforts
Offers full symbolic debugging
capabilities
Available in diskette or paper tape
versions
The Intellec ICE-80 8080 In-Circuit Emulator is an Intellec resident module designed to interface with any user configured 8080 system. With ICE-80 as a replacement for a prototype system 8080, the designer may emulate the
system's 8080 in real time, single step the system's program, and substitute Intellec memory and I/O for user system
equivalents. Powerfullntellec debug functions are extended into the user system. For the first time the designer may
examine and modify his system with symbolic references instead of absolute values.
12-61
ICE·80
during system debugging. By referring to symbolic
memory addresses, the user may be assured of examining, changing, or breaking at the intended location.
FUNCTIONAL DESCRIPTION
Integrated Hardware/Software Development
Use of the ICE-80 module enables the system integration phase, which can be so costly and frustrating when
attempting to mesh completed hardware and software
products, to become a convenient two-way debug tool
when begun early in the design cycle. The user prototype need consist of no more than an 8080 CPU socket
and a user bus to begin integration of software and hardware development efforts. With the ICE-80 mapping
capabilities, system resources may be accessed for
missing prototype hardware. Hardware designs may be
tested using system software to drive the final product.
A functional block diagram of the ICE-80 module is
shown in Figure 1.
Symbolic Debugging Capability
ICE-80 provides for user-defined symbolic references to
program memory addresses and data. Symbols may be
substituted for numeric values in any of the ICE-80 commands. The user is thus relieved from looking up
addresses of variables or program subroutines.
Symbol Table - The user symbol table generated along
with the object file during a PUM compilation or a
MAC80 or resident assembly, is loaded to memory along
with the user program to be emulated. The user may add
to this symbol table any additional symbolic values for
memory addresses, constants, or variables found useful
Symbolic Reference - ICE-80 provides symbolic definition of all 8080 registers, flags, and selected pins. The
following symbolic references are also provided for user
convenience: TIMER, a 16-bit register containing the
number of '1'2 clock pulses elapsed during emulation;
ADDRESS, the address of the last instruction emulated;
INTERRUPTENABLED, the user 8080 interrupt mechanism status; and UPPERLIMIT, the highest RAM address
occupied by user memory.
Debug Capability Inside User System
ICE-80 provides for user debugging of full prototype or
production systems without introducing extraneous
hardware or software test tools. ICE-80 connects to the
user system through the socket provided for the user
8080 in the user system (See Figure 2). Intellec memory
is used for the execution of the ICE-80 software, while
I/O provides the user with the ability to communicate
with ICE-80 and receive information on the generation of
the user system. A sample ICE-80 debug session is
shown in Figure 3.
I/O Mapping and Memory
Memory and I/O for the user system may be resident in
the user system or "borrowed" from the Intellec system
through ICE-80's mapping capability.
16 ADDRESS
8 DATA OUT
8 DATA IN
CONTROL
r-----------------l
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
8-,2
I
I
I
I
l __ _
I
ICE·ao TRACE BOARD
PROCESSOR
BOARD
_ ICE·SO
__
___
_ _ _ _ _ _ ---J
CONTROL}
BOAT A 'BITS
INTELLEC BUS
16 ADDRESS BITS
Figure 1. Functional Block Diagram of ICE-80 Module
12-62
ICE·SO
ICE-80 trace board. ICE-80 and the system also communicate through a control block resident in the Intellec
main memory, which contains detailed configuration
and status information transmitted at an emulation
break. ICE-80 hardware consists of two PC boards - the
processor and trace boards residing in the Intellec chassis - and a 6-foot cable interfacing to the user system.
The trace and processor boards communicate with the
system on the bus, and also with each other on a separate ICE-80 bus. ICE-80 connects to the user system
through a cable that plugs directly into the socket
provided for the user's 8080.
Trace Board
The trace board talks to the system as a peripheral
device. It receives commands to ICE-80 and returns
ICE-80. responses. While ICE·80 is executing the user
program, the trace board collects data for each machine
cycle emulated (snap data). The information is continuously stored in high-speed bipolar memory.
Breakpoint - The trace board also contains two 24-bit
hardware breakpoint registers which can be loaded by
the user. While in emulation mode, a hardware com paritor is constantly monitoring address and status lines for
a match to terminate an emulation. A user protS'e is also
available for attachment to any user signal. When this
signal goes true a break condition is recognized.
Figure 2. ICE·SO Module Installed in User System
Memory Blocking - ICE·80 separates user memory into
16 4K blocks. User I/O is divided into 16 16·port blocks.
Each block of memory or I/O may be defined independ·
ently. The user may assign system equivalents to take
the place of devices not yet designed for the user sys·
tem during prototyping. In addition, memory or I/O may
be accessed in place of user system devices during prototype or production checkout.
Interrogation - The trace board signals the processor
board when a command to ICE-80 or break condition has
been detected. The ICE-80 CPU then sends data stored
on the trace board to the control block in memory. Snap
data, along with information on 8080 registers and pin
status and the reason for the emulation break, are then
available for access during interrogation mode. Error
conditions, if present, are transmitted and automatically
displayed for the user.
Error Messages - The user may also designate a block
of memory or I/O as nonexistent. ICE-80 issues error
messages when memory or I/O designated as nonexisting is accessed by the user program.
Processor Board
An 8080 CPU resides on the processor board. During
emulation it executes instructions from the user's program. At all other times it executes instructions from
the control program in the trace module's ROM.
Real·Time Trace
Timing - The processor board contains an internal
clock generator to provide clocks to the user emulation
CPU at 2 MHz. The CPU can alternately be driven by a
clock derived from user system signal lines. The clock
source is selected by a jumper option on the board. A
timer on the trace board counts the <1>2 clock pulses during emulation and can provide the user with the exact
timing of the emulation.
ICE-80 captures valuable trace information while the
user is executing programs in real time. The 8080 status,
the user memory or port addressed, and the data read or
written (snap data), is stored for the last 44 machine
cycles executed. This provides ample data for determining how the user system was reacting prior to emulation
break. It is available whether the break was user initiated or the result of an error condition. For detailed
information on the actions of CPU registers, flags, or
other system operations, the user may operate in single
or multiple step sequences tailored to system debug
needs.
On/Off Control - The processor board turns on an emulation when ICE-BO has received a run command from
the system. It terminates emulation when a break condition is detected on the trace board, or the user's program attempts to access memory or I/O ports
deSignated as nonexistent in the user system, or the
user 8080 is inactive for a quarter of a second.
Hardware
The heart of the ICE-80 is a microcomputer system utilizing Intel's 8080 microprocessor as its nucleus. This
system communicates with the Intellec host processor
via I/O commands. Host processor commands and
ICE-80 status are interchanged through registers on the
Status Storage - The address map located on the processor board stores the assigned location of each user
memory or I/O block. During emulation the processor
board determines whether to send/receive information
12-63
ICE·SO
ISIS 8080 MACROASSEMBLER, V1.0
PAGE 1
;USER PROGRAM TO OUTPUT A SERIES OF
;CHARACTERS TO SDK·80 CONSOLE DEVICE
1320
01E3
CO
13200801
13223A3613
1354F
1326 CDE301
132979
132A 93
132B 323713
132E FE40
1330 C22513
1333 C32013
START:
1336 SA
1337
0000
DAT1:
RSLT:
LOOP:
ORG
EQU
1320H
1E3H
MVI
LOA
MDV
CALL
MOV
SBB
STA
CPI
JNZ
JMP
B,1
DAn
C,A
CO
A,C
B
RSLT
40H
LOOP
START
DB
OS
END
SAH
;SDK·80 CONSOLE OUT DRIVER
;SET UP B VALUE
;LOAD A WITH DAT1 VALUE
;SEND C VALUE TO CONSOLE
;RESTORE A
;SUBTRACT B FROM A
;STORE RESULT IN RSLT
;LAST VALUE TO PRINT
;LOOP AGAIN IF A>40H
;ELSE RESTART WHOLE PROCEDURE
ISIS, V1.0
INITIAL ICE·80 SESSION
-ICE80
(Note: The SDK·BO Monitor has already been used to inltialize the SDK·BO Board)
ISIS ICE·80, V1.0
"XFORM MEMORY 0 TO 1 U
'XFORM 10 OFH U
CD
@
@
@)
®
®
(j)
®
'LOAD PROG. HEX
ERR =067
STAT = 11H TYPE=06H CMND=07H ADDR= 1320H GOOD=06H BAD =04H
'CHANGE MEMORY 1321H=FFH
ERR=067
STAT = 11H TYPE=06H CMND=07H ADDR= 1321H GOOD= FFH BAD= FDH
'LOAD PROG. HEX
'GO FROM START UNTIL RSLT WRITTEN
EMULATION BEGUN
ERR=067
STAT=11H TYPE=07H CMND=~2H
'DISPLAY CYCLES 5
STAT=A2H ADDR=1326H DATA=ClDH
STAT=82H ADDR = 1327H DATA= E!i.H
STAT=82H ADDR=1328H DATA=01"1
STAT=04H ADDR=FFFF/t DATA = 13"1
STAT=04H ADDR=FFFEH DATA = 29H,
'CHANGE DOUBLE REGISTER SP= 13F"~
'BASE HEX
'EQUATE STOP=1333H
'GO FROM START UNTIL STOP EXECUTED 'THEN DUMP
EMULATION BEGUN
'
B=01H C =41H D=OOH E=OOH H =OOH L=OOH F= 56H A=40H P= 1320H '= 1333H 5= 13FFH
EMULATION TERMINATED AT 1333H
'
'EXIT
'FFFF
Notes
1. Set up user memory and 110. The program is set u~ to execute in block 1 (1000H-1FFFH) of user memory, and requires access to the SDK·80
monitor (block 0) and 110 ports in block OFH. Both ports and memory are defined as available to the user system. All other memory and 110 is initial·
ized by ICE·80 as nonexistent (guarded).
2. A load command generates an error. The type and command numbers indicate that a data mismatch occurred on a write to memory command.
The data to be written to address 1320H should have been 06H. When ICE·80 read the data after writing it, a 04H was detected. A change command
to a different memory address hints that bit 1 does not go to 1 anywhere in this memory block. Examination indicates that a pin was shorted on the
RAM located at 1300H-13FFH in the prototype system. The problem is fixed and a subsequent load succeeds.
3. A real·time emulation is begun. The program is executed from 'START' (1320H) and continues until 'RSl T' is written [in location 1328H, the con·
tents of the accumulator is stored in (written into) 'RSlT'j.
4. An error condition results: TYPE 07, CMND 02 indicate the program accessed is a guarded area.
5. The last 5 machine cycles executed are displayed. The last instruction executed was a call (CDH). The fourth and fifth cycles are a push opera·
tion (designated by status 04H) to store the program counter before executing the call. The stack pOinter was not initialized in the program and is ac·
cessing memory location FFFFH.
6. After making a note to initialize the stack pOinter in the next assembly., a temporary fix is effected by setting the stack pOinter to the top of user
available memory.
7. After setting the base for displays to hex and adding the symbol 'STOP' to the symbol table, emulation is started which will terminate when the
instruction at 1333H ('STOP') is executed. When emulation terminates, a dump of the contents of user 8080 registers is requested. One can see that
the value of the accumulator is set at 40H, the stack pOinter is set at 13FFH, the last address executed (') is 1333H, and the program counter has
been set to 1320H.
8. Exit returns control to the MDS monitor.
Figure 3. Sample ICE·aO Debug Session
12-64
ICE·80
on the Intellec or user bus by consulting the address
map. The processor board allows the ICE-80 CPU to gain
access to the bus as a master to "borrow" Intellec facilities. At an emulation break, the processor board stores
the status of specified 8080 input and output Signals,
disables all interaction with the user bus, and commands the trace board to send stored information to a
control block in Intellec memory for access during interrogation mode.
figured with a broad range of modifiers to provide the
user with maximum flexibility in describing the operation to be performed. Listings of emulation commands,
interrogation commands, and utility commands are provided in Table 1, Table 2, and Table 3, respectively.
Cable Card
Base
Establishes mode of display for output
data.
Display
Prints contents of memory, 8080 registers, input ports, 8080 flags, 8080 pins,
snap data, symbol table, or other diagnostic data on list device. May also be
used for base-to-base conversion, or for
addition or subtraction in any base.
Change
Alters contents of memory, register, output port, or 8080 flag.
XFORM
Defines memory and I/O status.
Search
Looks through memory range for specified value.
The cable card is included for cable driving. It transmits
address and data bus information to the user system
through a 40-pin connector that plugs into the user system in the socket designed for the 8080 when enabled
by the processor module's user bus control logic.
Software
The ICE-80 software driver (ICE80SD) is a RAM-based
program providing easy to use English language commands for defining breakpoints, initiating emulation,
and interrogating and altering the user system status
recorded during emulation. ICE-80 commands are con-
Step
Table 2_ ICE-80 Interrogation Commands
Operation
Command
Go
Load
Fetches user symbol table and object
code from input device.
Save
Sends user symbol table and object code
to output device.
Equate
Enters symbol name and value to user
symbol table.
Fill
Fills memory range with specified value.
Move
Moves block of memory data to another
area of memory.
Timeout
Enables/disables user CPU 1/4 second
wait state timeout.
List
Defines list device (diskette-based version only).
Exit
Returns program control to monitor.
Initiates emulation in single or multiple
instruction increments. User may specify
register dump or tailor diagnostic activity to his needs following each step, and
define conditions under which stepping
should continue.
Delimits blocks of instructions for which
register dump or tailored diagnostics are
to occur.
Continue
Resumes real-time emulation.
Call
Emulates user system interrupt.
Operation
Command
Initiates real-time emulation and allows
user to specify breakpoints, data retrieval,
and conditions under which emulation
should be reinitiated.
Range
Operation
Command
Table 1. ICE-80 Emulation Commands
Table 3. ICE-80 Utility Commands
SPECIFICATIONS
Diskette-Based ICE80SD
Paper Tape·Based ICE80SD
Operating Environment
Required Hardware
Intellec system
System console
Reader device
Punch device
ICE-80
Required Software
System monitor
Operating Environment
Required Hardware
Intellec system
32K bytes RAM memory
System console
ISIS MOS floppy disk drive
ICE-80
Required Software
System monitor
ISIS-II Diskette Operating System
12-65
ICE·80
System Clock
Environmental Characteristics
Crystal controlled 2.1S5 MHz±0.01%. May be replaced
by user clock through jumper selection.
Operating Temperature Operating Humidity -
O·C to 40·C
Up to 95% relative humidity
without condensation
Connectors
Edge Connector -
Equipment Supplied
CDC VPB01 E32AOOA 1
Printed circuit modules (2)
Interface cables and buffer board
ICE-SO software driver, paper tape version
(ICE-SO software driver, diskette-based version is supplied with diskette operating systems)
Physical Characteristics
Width -
12.00 in. (30.4S cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 8.00 Ib (3.64 kg)
Reference Manuals
9800185 - ICE-SO Operator's Manual (SUPPLIED)
9800556 - Intellec Series II Hardware Reference Manual (SUPPLIED)
9800554 - Intellec Series II Schematic Drawings
(SUPPLIED)
Electrical Characteristics
DC Power Requirements
Vee= +5V, ±5%
lee=9.S1A max; 6.90A typ
Voo= + 12V, ± 5%
100 = 79 mA max; 45 mA typ
Vss= -9V, ±5%
Iss= 1 mA max; 1!IA typ
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
Description
MDS-80-ICE
SOSO CPU In-circuit emulator, cable
assembly and Interactive software
included
12-66
ICE·8S
MCS·8S IN·CIRCUIT EMULATOR
Connects the Intellec system resources
to the user configured system via a
40-pin adaptor plug
Displays trace data from user's 8085 in
assembler mnemonics and allows personality groupings of data sampled by external 18-channel trace module
Executes user system software in real
time
Shares Intellec memory and 1/0 facilities
with user system
Extends ICE capabilities to prototype
system peripheral circuitry by allowing
user to execute peripheral chip analysis
routines
Provides 1023 states of 8085 trace data
plus 18 additional logic signals via external trace module
Offers full symbolic debugging capability
for both assembly language and Intel's
high level compiler language, PL/M-80
Provides ability to examine and alter
MCS-85 registers, memory, flag values,
interrupt bits, and 1/0 ports
The ICE-85 MCS-85 'In-Circuit Emulator is an Intellec resident module designed to interface with any user configured
8085 system. In addition, an external trace module provides access to user system peripheral circuitry via a user configured DIP clip for peripherallCs or may be attached to as many as 18 separate prototype signal nodes via individual
probe clips. Using the ICE-85 module, the designer may execute prototype software in real time or single step mode
and may substitute Intellec system memory and 1/0 for their user system equivalents. ICE capability may be extended
to the remaining user system peripheral circuitry by allowing the user to create and execute a library of user defined
peripheral chip analyzer routines. All user access to the prototype system software may be done symbolically by
assigning names to program locations and data, 1/0 ports, and groups of external trace Signals. For the first time, inciruit emulation extends beyond a user prototype CPU to the entire user system, allowing in-system emulation.
12-67
MCS-85™ IN-CIRCUIT EMULATOR
SYMBOLIC DEBUGGING CAPABILITY
ICE-85 allows the user to make symbolic references to I/O
ports, memory addresses and data in his program. Symbols
and PL/M statement number may be substituted for numeric values in any of the ICE-85 commands. The user is relieved from looking up addresses of variables or program
subroutines.
The user symbol table generated along with the object file
during a PUM-80 compilation or by the ISIS-II 8080/8085
Macro Assembler is loaded into the I ntellec® System memory along with the user program which is to be emulated.
The user may add to this symbol table any additional
symbolic values for memory addresses, constants, or variables that are found useful during system debugging. By
referring to symbol memory addresses, the user can examine, change or break at the intended location.
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
The user prototype need consist of no more than an 8085
CPU socket and a user bus to begin integration of software
and hardware development efforts. Through ICE-85 mapping capabilities, Intellec® System equivalents can be
accessed for missing prototype hardware. Hardware designs
can be tested using the system software which will drive the
final product.
The system integration phase, which can be so costly when
attempting to mesh completed hardware and software
products, becomes a convenient two-way debug tool when
begun early in the design cycle.
ICE-85 provides symbolic definition of all 8085 registers,
interrupt bits and flags. The following symbolic references
are also provided for user convenience: TIMER, the loworder 16 bits of a register containing the number of 2 MHz
clock pulses elapsed during emulation; HTIMER, the highorder 16 bits of the timer counter; PPC, the address of the
last instruction emulated; BUFFERSIZE, the number of
frames of valid trace data (between 0 and 1022).
PERSONALITY GROUPED DISPLAYS
Trace data in the 1023 by 42-channel real-time trace memory buffer is displayed in easy to read format. The user has
the option to specify trace data displays in actual 8085
assembler instruction mnemonics. The data collected from
the External Trace Module can be grouped and symbolically named according to user specifications and displayed in
the appropriate number base designation. Simple ICE-85
commands allow the user to select any portion of the 42Kbit trace buffer for immediate display.
TYPICAL ICE INTERROGATION AND
UTILITY COMMANDS
MEMORY AND I/O MAPPING
Memory and I/O for the user system can be resident in the
user system or "borrowed" from the Intellec® System
through ICE-85's mapping capability.
ICE-85 separates user memory into 32 2K blocks. Each
block of memory can be defined independently. The user
may assign Intellec® System equivalents to take the place
of devices not yet designed for the user system during prototyping. In addition, Intellec® System memory or I/O can
be accessed in place of suspect user system devices during
prototyping or production checkout.
The user can also designate a block of memory or I/O as
nonexistent. ICE-85 issues error messages when memory
or I/O designated as nonexistent is accessed by the user
program.
DISPLAY/
CHANGE
Display/Changes the values of symbols and
the contents of 8085 registers, pseudoregisters, status flags, interrupt bits, I/O ports
and memory.
EVALUATE
Displays the value of an expression in the
binary, octal, decimal or hexadecimal.
SEARCH
Searches user memory between locations in a
user program for specified contents.
CALL
Emulates a procedure starting at a specified
ICALL
Executes a user-supplied procedure starting at
memory address in user memory.
a specified memory address in the Intellec®
System memory.
EXECUTE
12-68
Saves emulated program registers and emulates a user-supplied subroutine to access
peripheral chips in the user's system.
MCS-85™ IN-CIRCUIT EMULATOR
REAL TIME TRACE
EXTERNAL TRACE MODULE
ICE-85 captures valuable trace information from the emulating CPU and the External Trace Module while the user is
executing programs in real time. The 8085 status, the user
memory or port addressed, the data read or written, the
serial data Iines and data from 18 external signals, is stored
for the last 1023 machine states executed (511 machine
cycles). This provides ample data for determining how the
user system was reacting prior to emulation break. It is
available whether the break was user-initiated or the result
of an error condition.
TTL level signals from 18 points in the user system may be
synchronously sampled by the External Trace Module and
collected in ICE-85's trace buffer. The signals can be collected from a single peripheral chip via the supplied 40-pin
DIP clip or may be placed by the user on up to 18 separate
signal nodes using the supplied 18 individual probe clips.
These signals are included in the 42-channel breakpoint
comparisons and clock qualifiers. Also, data from these
18 channels may be displayed in each to read, user-defined
groupings.
For detailed information on the actions of CPU registers,
flags, or other system operations, the user may operate in
single or multi-step sequences tailored to system debug
needs.
SYNCHRONOUS OPERATION WITH OTHER DESIGN
AIDS
ICE-85 can be synchronized with other Intellec® design
aids by means of two external synchronization lines. These
lines are used to enable and disable ICE-85 trace data
collection and to cause break conditions based on an
external signal which may not be included in the ICE-85
breakpoint registers. In addition, ICE-85 can generate signals on these lines which may be used to control other
design aids.
BREAK REGISTERS/TRACE MEMORY
EMULATION CONTROLS AND COMMANDS
GROUP
Defines into a symbolically named group, a
channel or combination of channels from the
8085 Microcprocessor and/or the External
Trace Module.
GO
Initiates real-time emulation and controls
emulation break conditions.
STEP
Initiates emulation in single instruction steps.
User may specify the type and amount of
information displayed following each step,
and define conditions under which stepping
should continue.
PRINT
Prints the user-specified portion of the trace
memory to the selected list device_
ICE-85 has two breakpoint registers which are used to
break emulation, and two trace qualifier registers which are
used to control the collection of trace data during emulation. Each register is 42 entries wide, one entry for each
channel and each entry can take anyone of the three values
0, 1 or "don't care".
The trace buffer, also 42 entries wide, collects data sampled
from 24 8085 processor channels and 18 external channels
sampled by the External Trace Module. The signals collected from the 8085 include address lines, data lines, status
lines and serial input and output lines. The 18 channels
extending from the External Trace Module synchronously
sample and collect into the trace buffer any user-specified
TTL compatible signal from the rest of the prototype
system. "Break" and "trace qualification" may therefore
occur as a result of a match of any combination of up to 42
channels of CPU and external circuitry signals.
12-69
ICE·8S
r -- -- -- -- -- --..----_---,
ICE·85 CONTROL BOARD
I
L _________ _
I
r----------
SYNC 0
I
I
CHIP DATA f
TRACE DATA
I
CONTROL
I
ADDRESS
I
I
J
L ___________________t=~=i========:b=;::;::::-=~-----~I
L ____________________
I
I
L -_ _ _ _ _ _-'-'FO=Rc=E~T=RA=CE~.
TIME CLOCK
_ _ ___j
I
~
ICE·a5 TRACE BOARD
~
TO USER'S
SOCKET
SYNC 1
8085 CHIP CONTROLLER
,.----------1
I
SIGNAL BUFFERS
tf------l18 USER TRACE
!'r----.----J
PROBES
IL __________ ..JI
18 EXTERNAL TRACE BUFFER
Figure 1_ Functiona-I Block Diagram of ICE-85 Module
SPECI FICATIONS
ICE·85 Operating Environment
Required Hardware
Intellec microcomputer development system
System console
Intellec diskette operating system
ICE-85 module
Required Software
System monitor
ISIS-II
lee = 12A max; 10A typ
Voo=+12V±5%
100 = 80 mA max; 60 rnA typ
V BB = -10V±5%
188=30 mA max; 10!1A typ
Environmental Characteristics
Operating Temperature - 0° to 40°C
Operating Humidity - Up to 95% relative humidity without condensation.
Emulation Clock
Equipment Supplied
User's system clock or ICE-85 adaptor socket (6.144
MHz crystal)
18-channel external trace module
Printed circuit boards (2)
Interface cable and emulation buffer module
ICE-85 software, diskette-based version
Physical Characteristics
Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Packaged Weight - 6.00 Ib (2.73 kg)
Electrical Characteristics
DC Power Requirements
Vee= +5V±5%
Reference Manuals
9800463 -
ORDERING INFORMATION
Part Number
Description
MDS-85-ICE
8085 CPU in-circuit emulator and
18-channel external trace module
ICE-85 Operator's Manual (SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
12-70
ICE·86™
8086 IN·CIRCUIT EMULATOR
Hardware in-circuit emulation
2K bytes of high speed ICE-86 mapped
memory
Full symbolic debugging
Software debugging with or without user
system
Breakpoints to halt emulation on a wide
variety of conditions
Handles full 1 megabyte addressability of
8086
Comprehensive trace of program execution, both conditional and unconditional
Compound commands
Disassembly of trace or memory from
object code into assembler mnemonics
Command macros
The ICE-86 module provides In-Circuit Emulation for the 8086 microprocessor and the iSBC 86/12 Single Board Computer. It includes three circuit boards which reside in Intellec Microcomputer Development Systems_ A cable and buffer box connect the Intellec system to the user system by replacing the user's 8086_ Powerfullntellec debug functions
are thus extended into the user system. Using the ICE·86 module, the designer can execute prototype software in continuous or single-step mode and can substitute blocks of Intellec system memory for user equivalents. Breakpoints
allow the user to stop emulation on user·specified conditions, and the trace capability gives a detailed history of the
program execution prior to the break. All user access to the prototype system software may be done symbolically by
referring to the source program variables and labels.
12-71
ICE·86
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
SYMBOLIC
DEBUGGttl~.-., ,(~,"~",:
Symbols and PLiM statement -:numqei~'~ .pe
substituted for numeric values in any ofth~.IOE-86'iS~ •
mands. This allows the user to make syirfuc)l!c le~~~;"~
ences to 110 ports, memory addresses, and dat!!. in tI,a. " .;JI
user program. Thus the user need not remember thlad-~ "', '
dresses of variables or program subroutines.
The ICE-86 emulator allows hardware and software
development to proceed interactively. This is more effective than the traditional method of independent hardware and software development followed by system integration. With the ICE-86 module, prototype hardware
can be added to the system as it is designed. Software
and hardware testing occurs while the product is being
developed.
Symbols can be used to reference variables, procedures, program labels, and source statements. A variable can be displayed or changed by referring to it by
name rather than by its absolute location in memory.
Using symbols for statement labels, program labels, and
procedure names simplifies both tracing and breakpoint
setting. Disassembly of a section of code from either
trace or program memory into its assembly mnemonics
is readily accomplished.
Conceptually, the ICE-86 emulator assists three stages
of development:
1. It can be operated without being connected to the
user's system, so ICE-86 debugging capabilities can
be used to facilitate program development before any
of the user's hardware is available.
Furthermore, each symbol may have associated with it
one of the data types BYTE, WORD, INTEGER,
SINTEGER (for short, 8-bit integer) or POINTER. Thus
the user need not remember the type of a source program variable when examining or modifying it. For
example, the command "!VAR" displays the value in
memory of variable VAR in a format appropriate to its
type, while the command "IVAR= IVAR+ 1" increments
the value of the variable.
2. Integration of software and hardware can begin when
any functional element of the user system hardware
is connected to the 8086 socket. Through ICE-86
mapping capabilities, Intellec memory, ICE memory,
or diskette memory can be substituted for missing
prototype memory. Time-critical program modules
are debugged before hardware implementation by using the 2K-bytes of high-speed ICE-resident memory.
As each section of the user's hardware is completed,
it is added to the prototype. Thus each section of the
hardware and software is "system" tested as it
becomes available.
The user symbol table generated along with the object
file during a PUM-86 compilation or an ASM-86
assembly is loaded into memory along with the user program which is to be emulated. The user may add to this
symbol table any additional symbolic values for memory
addresses, constants, or variables that are found useful
during system debugging.
3. When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-86 module is then used for real time emulation of the 8086 to debug the system as a completed
unit.
The ICE-86 module provides access through symbolic
definition to all of the 8086 registers and flags. The
READY, NMI, TEST, HOLD, RESET, INTR, and MNiMX
pins of the 8086 can also be read. Symbolic references
to key ICE-86 emulation information are also provided.
Thus the ICE-86 module provides the user with the ability to debug a prototype or production system at any
stage in its dev-elopment without introducing
extraneous hardware or software test tools.
r-
PLUG INTO
BUFFER BOX
~,USER
BOB6 SOCKET
Y·CABLE
CABLE
r------ -------- ------------------------ I
I
I
I
I
I
r----..,I
T·CABLE
I
I
I
I
I
I INTELLEC I
HOST
I
I
I
IA
I I
I ____ -.Jh
II L
FIRMWARE
CONTROLLER
BOARD
i
MULTI.Bus
I
TRACE BOARD
j
I
AUXILLIARY CONNECTOR
1
B8-CONTROLLER
BOARD
I
L ______________________________
Figure 1. ICE·86 Block Diagram
12-72
~
I
I
I
I
I
I
I
I
II
...!N~L~C.J
ICE·86
A typicallCE·B6 development configuration. It is based on an MDS·230 Development System, which also includes an
MDS·DDS Double Density Diskette Operating System and an MDS·201 Expansion Chassis (which holds the ICE·B6
emulator). The ICE·B6 module is shown connected to a user prototype system, in this case, an SDK·B6.
MACROS AND COMPOUND COMMANDS
GO
A macro is a set of ICE·86 commands which is given a
single name. Thus, a sequence of commands which is
executed frequently may be invoked simply by typing in
a single command. The user first defines the macro by
entering the entire sequence of commands which he
wants to execute. He then names the macro and stores
it for future use. He executes the macro by typing its
name and passing up to ten parameters to the com·
mands in the macro. Macros may be saved on a disk file
for use in subsequent debugging sessions.
Compound commands provide conditional execution of
commands(IF), and execution of commands until a con·
dition is met or until they have been executed a
specified number of times (COUNT, REPEAT).
Compound commands and macros may be nested any
number of times.
MEMORY MAPPING
Memory for the user system can be resident in the user
system or "borrowed" from the Intellec System through
ICE·86's mapping capability.
The ICE·86 emulator allows the memory which is ad·
dressed by the 8086 to be mapped in 1K·byte blocks to:
1. Physical memory in the user's system,
2. Either of two 1K·byte blocks of ICE·86 high speed
memory,
3. Intellec memory,
4. A random·access diskette file.
The user can also designate a block of memory as non·
existent. The ICE·86 module issues an error message
when any such "guarded" memory is addressed by the
user program.
Description
Command
The ICE·86 module provides a programmable diagnostic
facility which allows the user to tailor its operation us·
ing macro commands and compound commands.
Initializes emulation and allows the
user to specify the starting point
and breakpoints. Example:
GO FROM .START TILL .DELAY
EXECUTED
where START and DELAY are state·
ment labels.
STEP
Allows the user to
through the program.
single·step
Table 1. Summary of ICE·B6 Emulation Commands
OPERATION MODES
The ICE·86 software is a RAM·based program that pro·
vides the user with easy·to·use commands for initiating
emulation, defining breakpoints, controlling trace data
collection, and displaying and controlling system
parameters. ICE·86 commands are configured with a
broad range of modifiers which provide the user with
maximum flexibility in describing the operation to be
performed.
Emulation
Emulation commands to the ICE·86 emulator control the
process of setting up, running and halting an emulation
of the user's 8086. Breakpoints and tracepoints enable
ICE·86 to halt emulation and provide a detailed trace of
execution in any part of the user's program. A summary
of the emulation commands is shown in Table 1.
Breakpoints - The ICE·86 module has two breakpoint
registers that allow the user to halt emulation when a
specified condition is met. The breakpoint registers may
be set up for execution or non·execution breaking. An
execution breakpoint consists of a single address
which causes a break whenever the 8086 executes from
its queue an instruction byte which was obtained from
12·73
ICE·86
the address. A non-execution breakpoint causes an
emulation break when a specified condition other than
an instruction execution occurs. A non-execution breakpOint condition, using one or both breakpoint registers,
may be specified by anyone of or a combination of:
Memory/Register Commands
Display or change the contents of:
• Memory
• 8086 Registers
• 8086 Status flags
• 8086 Input pins
• 8086 I/O ports
• ICE-86 Pseudo·Registers (e.g. emulation timer)
1. A set of address values. Break on a set of address
values has three valuable features:
a. Break on a single address.
Memory Mapping Commands
b. The ability to set any number of breakpoints within
a limited range (1024 bytes maximum) of memory.
Display, declare, set, or reset the ICE-86 memory mapping.
Symbol Manipulation Commands
c. The ability to break in an unlimited range. Execution is halted on any memory access -to an address
greater than (or less than) any 20-bit breakpoint address.
Display any or all symbols, program modules, and program
line numbers and their associated values (locations in
memory).
Set the domain (choose the particular program module) for
the line numbers.
2. A particular status of the 8086 bus (one or more of:
memory or I/O read or write, instruction fetch, halt, or
interrupt acknowledge).
Define new symbols as they are needed in debugging.
Remove any or all
statements.
3. A set of data values (features comparable to break on
a set of address values, explained in point one).
modules,
and
program
Change the value of any symbol.
TYPE
4. A segment f(~gister (break occurs when the register is
used in an effective address calculation).
Assign or change the type of any symbol in the symbol table.
ASM
An external breakpoint match output for user access is
provided oli the buffer box. This allows synchronization
of other test equipment when a break occurs.
Disassemble user program memory into ASM·s6 Assembler
mnemonics.
PRINT
Tracepoints - The ICE·86 module has two tracepoint
registers which establish match conditions to conditionally start and stop trace collection. The trace information is gathered at least twice per bus cycle, first
when the address signals are valid and second when the
data signals are valid. If the 8086 execution queue is
otherwise active, additional frames of trace are collected.
Display the specified portion of the trace memory.
LOAD
Fetch user symbol table and object code from the input file.
SAVE
Send user symbol table and object code to the output file.
LIST
Send a copy of all output (including prompts, input line
echos, and error messages) to the chosen output device (e.g.,
disk, printer) as well as the console.
Each trace frame contains the 20 address/data lines and
detailed information on the status of the 8086. The trace
memory can store 1,023 frames, or an average of about
300 bus cycles, providing ample data for determining
how the 8086 was reacting prior to emulation break. The
trace memory contains the last 1,023 frames of trace
data collected, even if this spans several separate
emulations. The user has the option of displaying each
frame of the trace data or displaying by instruction in actual ASM-86 Assembler mnemonics. Unless the user
chooses to disable trace, the trace information is
always available after an emulation.
EVALUATE
Display the value of an expression In binary, octal, decimal,
hexadecimal, and ASCII.
SUFFIX/BASE
Establish the default base for numeric values in input
text/output display (binary, octal, decimal, or hexadecimal).
CLOCK
Select the internal (ICE·86 provided, for stand·alone mode
only) or an external (user.provided) system clock.
RWTIMEOUT
Allows the user to time out READIWRITE command signals
based on the time taken by the 8086 to access Intellec
memory or diskette memory.
Interrogation and Utility
Interrogation and utility commands give the user convenient access to detailed information about the user
program and the state of the 8086 that is useful in
debugging hardware and software_ Changes can be
made in both memory and the 8086 registers, flags, input pins, and I/O ports. Commands are also provided for
various utility operations such as loading and saving
program files, defining symbols and macros, displaying
trace data, setting up the memory map, and returning
control to ISIS-II. A summary of the basic interrogation
and utility commands is shown in Table 2.
symbols,
ENABLE/DISABLE ROY
Enable or disable logical AND of ICE·86 Ready with the user
Ready signal for accessing Intellec memory, ICE memory, or
diskette memory.
Table 2. Summary of Basic ICE·86 Interrogation and
Utility Commands
12-74
ICE·86
DIFFERENCES BETWEEN ICE·86
EMULATION AND THE 8086
MICROPROCESSOR
DC CHARACTERISTIOs::
USER CABLE
"~i.
1_ Output Low Voltages [VodMax) = O.4VJ' ... "
loLlMint,;,
The ICE-B6 module emulates the actual operation of the
BOB6 microprocessor with the following exceptions:
The ICE-86 module will not respond to a user system
NMI or RESET signal when it is out of emulation_
A16/S3-A19/S7, BHE/S7, RD,
B mA
(16 mA @ 0.5V)
HLDA
• The MINIMAX line, which chooses the "minimum" or
"maximum" configuration of the BOB6, must not
change dynamically in the user system.
• In the "minimum" mode, the user HOLD signal must
remain active until HLDA is output by the ICE-B6
emulator.
12 mA "t, 'f
(24 mA @ 0.5V)
LOCK, OSO, OS1, SO, S1, S2,
WR, M/iO, DT/R, DEN, ALE,
INTA
• Trap is ignored in single step mode and on the first instruction step of an emulation.
-f,t
ADO-AD15
7mA
MATCHO OR MATCH1 (on
buffer box)
16 mA
2. Output High Voltages [VOH (Min)=2.4V]
IOH(Min)
The RO/GT lines in the "maximum" configuration are
not supported.
ADO-AD15
-
A16/S3-A19/S7, BHE/S7, RD,
-2.6 mA
3mA
LOCK, OSO, OS1, SO, S1, S2,
WR, M/iO, DT/R, DEN, ALE,
INTA
The speed of run emulation by the ICE-B6 module
depends on where the user has mapped his memory. As
the user prototype progresses to include memory,
emulation becomes real time.
HLDA
-3.0 mA
MATCHO OR MATCH1 (on
buffer box)
- O.B mA.
3. Input Low Voltages [VldMax) = O-BV]
IlL (Max)
Memory
Mapped To
Estimated Speed
User System
100% of real time., up to 4 MHz
clock
ICE
2 wait states per BOB6-controlled
bus cycle
Intellec
Approximately 0.02% of real time
at .4 MHz clock
Diskette
ADO-AD15
NMI, CLK
READY
INTR,HOLD,TEST,RESET
MN/MX (0.1 ,..f to GND)
mA
mA
mA
mA
mA
4_ Input High Voltages [VIH(Mln) = 2.0V]
IIH(Max)
ADO-AD15
NMI, CLK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1 ,..F to GND)
..
of real time is emulation at the user system clock rate with
no wait states.
""The emulation speed from diskette is comparable to Intellec
memory, but emulation must walt when a new page is accessed
on the diskette.
-0.2
-0.4
-O.B
-1.4
-3.3
"100%
BO,..A
20,..A
40,..A
-0.4 mA
-1.1 mA
5_ RO/GTO, RO/Gn are pulled up to + 5V through a 5.6K
ohm resistor. No current is taken from user circuit at
Vee pin.
12-75
ICE·86
':'·t.~Vl'!
SPECIFICATIONS
Emulation Clock
ICE·86 Operating Environment
User system clock up to 4 MHzor :f~,t.q :
clock in stand-alone m o d e "
(I)."
Physical Characteristics
DC Power
Vcc = +5V +5%-4%
Icc = 15A maximum; llA typical
Voo
+12V ±50.10
100
120 mA maximum; SO mAtypical
VBB = -10V ± 5% or -12V ± 5% (optional)
IBB = 15 mA maximum; 12 mA typical
=
=
Environmental Characteristics
Operating Temperature: o· to 40·C
Operating Humidity: Up to 95% relative humidity with·
out condensation.
ORDERING INFORMATION
Description
SOS6 CPU in-circuit emulator
"'./
Electrical Characteristics
Equipment Supplied
MDS-S6-ICE
' '<';;~>j/'C"t
Printed Circuit Boards
Width: 12.00 in (30.4S cm)
Height: 6.75 in (17.15 em)
Depth: 0.50 in (1.27 cm)
Packaged Weight: 9.00 Ib (4.10 kg)
Required Software
System monitor
ISIS-II, version 3.4 or subsequent
ICE-S6 software
Part Number
,
<$'
h,
Required Hardware
Intellec microcomputer development system with:
1. Three adjacent slots for the ICE-S6 module. (Series II
requires MDS-201 Expansion Chassis).
2. 64K bytes of Intellec memory. If user prototype program memory is desired, additional memory above
the basic 64K is required.
System console
Intellec diskette operating system
ICE-86 module
Printed circuit boards (3)
Interface cable and emulation buffer module
Operator's manual
ICE-S6 software, diskette·based
>;<~i
12-76
EM1
8021 EMULATION BOARD
EPROM functional equivalent of 8021 single component 8·bit microcomputer
Connects to prototype system through
8021 pin compatible plug
Based on 8748 - user programmablel
erasable EPROM 8·bit computer
On·card 3.0 MHz or external TTL driven
clock
Operates with ICE·49™ to provide full
in·circuit debugging of 8021 prototype
system
Portable 4" x 7" microcomputer circuit
assembly
The MDS-EM1 emulator board is a ready-to-use 4" x 7" microcomputer circuit assembly that emulates the Intel 8021
microcomputer. A 12-inch flat-cable assembly connects the board to the 8021 socket in a prototype system_ The board
is designed so that it can be mounted either as a stand-alone unit or within the prototype assembly_
The 8021 microcomputer has 1K x 8 mask programmable ROM program memory and 64 x 8 RAM data memory_ The
EM1 is controlled by an Intel 8748, with 1K of EPROM program memory and a 64-byte data memory_ The EPROM can be
programmed and erased repeatedly during hardware and software development The EM1 has several ancillary circuits
that perform the following functions which are specific to the 8021:
Zero crossing detector
Crystal controlled clock/buffer
Port 0 simulator
For prototype debugging, the 8748 can be removed from its socket and replaced with a cable to an InteIICE-49_ When
used with the EM1, ICE-49 emulates the 8021 in real time, or Single steps the 8021 program at the user's command_ A
full range of capabilities for examining and modifying 8021 memory and status are supplied through ICE-49.
12-77
EM1
HARDWARE
Zero Cross Detection Simulator
The EM1 emulation board uses the 8748 to perform the
emulation.
The zero cross detection simulator enables the 8748's
T1 input to detect zero·crossings. The circuitry provides
a high level signal on a positive crossing and a low level
signal on a negative crossing of zero to the T1 input of
the 8748.
PO Simulator
Port 0 of the 8021 is a quasi·bidirectional' port. The PO
simulator converts the data bus of the 8748 into a quasibidirectional port.
Reset Buffer
The 8021 resets on a logic HIGH level signal. However,
the 8748 resets on a logic LOW level, thus an inverter is
provided on the MDS-EM1 to make the two chips compatible.
Crystal Control Clock Buffer
The EM1 allows the user to select an on·board oscillator
or a TTL clock driven from the 8021 user's prototype
system via a Cambion Suitcase jumper.
Jumper
Position
State
W1
A-B
C-D
On·Board
External
TTL Clock
Optional Pull Ups
Resistors are provided to simulate the optional pull·up
resistors on T1 input and port 0 of the 8021. A removable
resistor pack is used on port O. The T1 input pull up can
be installed by soldering in a 50K resistor.
SOFTWARE
When emulating the 8021 with EM1 the user must
observe the 8021 instruction set.
• A bidirectional port which serves as an input port, output port, or both,
even though outputs are statically latched.
r---'
I OPTIONAL I
PULL UP I
L
.J
I
~ SIMULATOR
PORTO
I
K
DBO-OB7
~
<=
1\
POO-P07
y
~
I)
40
LINES
-- --
\
P10-P17
P20-P28
1\
I
ALE
8748
OR
4O·PIN
PLUG
8021
CABLE
PLUG
PROG
CABLE TO
ICE·49
I
I
Tl
RESET
I
I
I
I
CRYSTAL
Cg~6~~L
S
I
FLAT CAB LE
XTAL1
I
I g:T~~~I~~ I
I SIMULATORS I
:
I
I
I
i
I
I
I
RESET BUFFER
iI
T1
RESET
r-ON~ARiil
_-_1_--1
L_~.!!~N_J
PULL UP J:
_______
CLOCK
~
28
LINES
OPTIONAL I
I
EM1 FUNCTION DIAGRAM
12·78
28·PIN
SOCKET
EM1
SPECIFICATIONS
Physical Characteristics
Stand-Alone Required Hardware
EM1 emulation board
Width: 7.0 in. (17.78 cm)
Height: 4.0 in. (10.16 cm)
Depth: 0.75 in. (1.91 cm)
Weight: <1.0 Ib (0.45 kg)
In-Circuit Emulation Required Hardware
EM1 emulation board
Intellec Microcomputer Development System configured to support ICE-49
Electrical Characteristics
Operating Environment
Equipment Supplied
EM1 printed circuit board
12" long flat cable terminating in 28-pin plug, pin compatible with 8021
EM1 Operator's Manual
System Clock
Crystal controlled 3.0 MHz on board or user supplied
TTL external clock: hardware jumper selectable
DC Power
Vcc=5V ±5%
Icc = 300 mA (max)
Environmental Characteristics
Operating Temperature-O°C to 55°C
Operating Humidity-Up to 95% relative humidity without condensation
ORDERING INFORMATION
Part Number
Description
MDS-EM1
8021 Emulation Board
12-79
EM2
8022 EMULATION BOARD
Portable 4.25" x 2.75" microcomputer
circuit assembly
Provides Intel® 8755A -
2K x 8 EPROM
Connects directly into prototype system
through Intel® 8022* pin compatible
socket
EPROM functional and electrical
equivalent of Intel® 8022 - single
component 8·bit computer
The EM2 emulator board is a ready-lo-use 4.25" x 2.75" microcomputer circuit assembly that emulates the Intel® 8022
single chip microcomputer. The emulator board is designed to plug directly into the 8022 socket. No interfacing and
interconnection cables are necessary. Power is obtained from the user's system.
The EM2 emulator board provides the user a full EPROM functional and electrical equivalent of the 8022 single component 8-bit microcomputer.
The EM2 emulator board consists of an Intel® 8022 emulator chip and an Intel® 8755A, providing the EM2 emulator
board with a 2K x 8 EPROM program memory which can be programmed and erased repeatedly during hardware and
software development.
The 8022E emulator chip is a modified version of the 8022 intended for use in design support systems. Instead of
using resident ROM memory as the 8022, the 8022E uses an external 2K EPROM 8755A memory for program storage,
allowing easy program modification.
-See Intel® 8022 Data Sheet.
12-80
EM2
EM2 BLOCK DIAGRAM
40-PIN SOCKET CONFIGURATION
P26
Vee
P27
P25
P24
AVec
PROG
VAREF
AN1
P23
AND
P22
AVss
P21
TO
P20
VTH
P17
POD
P16
P01
P15
P02
P14
P03
P13
P04
P12
P05
P11
P06
P10
P07
RESET
ALE
XTAL2
T1
XTAL1
vss
SUBST
,..-........,rl
8755A
40·PIN
SOCKET
8022 EMULATOR CHIP
PIN 1
SQUARE SOLDER PAD
PIN DESCRIPTION
Designation
Vss
Pin #
20
Designation
Function
24
Input used to initialize the processor
by clearing status flip-flops and setting
the program counter to zero.
AVss
7
AID converter GND potential. Also
establishes the lower limit of the conversion range.
AVcc
3
AID + 5V power supply.
Circuit GND potential.
40
+ 5V circuit
PROG
37
Output strobe for I ntel® 8243 I/O expander.
power supply.
POO-P07 10-17 8-bit open-drain port with comparator
Port 0
inputs. The switching threshold is set
externally by VTH . Optional pull-up resistors may be added via ROM mask
selection. (The emulator board has
switch selection of this option.)
9
Pin #
RESET
Function
Vcc
VTH
2048
EPROM
MEMORY
SUBST
21
Substrate pin used with a bypass capacitor to stabil ize the substrate voltage
and improve AID accuracy.
VAREF
4
AID converter reference voltage. Establishes the ~pper limit of the conversion
range.
ANO,
AN1
6,5
Analog inputs to AID converter. Software selectable on-chip via SEL AND
and SEL AN1 instructions.
ALE
18
Address Latch Enable. Signal occurring once every 30 input input clocks
(once every single cycle instruction),
used as an output clock.
XTAL1
22
One side of crystal, inductor, or resistor input for internal oscillator. Also
input for external frequency source.
(Not TTL compatible.)
XTAL2
23
Other side of timing control element.
This pin is not connected when an external frequency source is used.
Port 0 threshold reference pin.
P10-P17 25-32 8-bit quasi-bidirectional port.
Port 1
P20-P27 33-36 8-bit quasi-bidirectional port.
Port 2
TO
T1
38-39 P20-P23 also serve as a 4-bit I/O ex1-2 pander for I ntel® 8243.
8
19
Interrupt input and input pin testable
using the conditional transfer instructions JTO and JNTO. Initiates an interrupt following a low level input if interrupt is enabled. Interrupt is disabled
after a reset.
Input pin testable using the JT1 and
JNT1 conditional transfer instructions.
Can be designated the timer/event
counter input using the STRT CNT instruction. Also serves as the zero-cross
detection input to allow zero-crossover
sensing of slowly moving AC inputs.
Optional pull-up resistor may be added
via ROM mask selection.
12-81
EM2
:...-.
The Intel® 8755A EPROM can be programmed using any
of the modules listed in Table 1.
Module
Description
UPP·103
Universal PROM Programmer.
Requires UPP·955, which in·
cludes 8755A Personality Card
with 40·pin adapter socket.
PROMPT·48
Intellec® MCS·48 Microcom·
puter Design Aid. Requires
PROMPT·475 Programming
Adapter.
PROMPT·80/85
~',,'
The 8755A EPROM is erasedwheri e~~t;~d
wavelengths shorter than apptoximatily'
stroms (A). Sunlight and certain fluoresq~erit Iarl)P$W~l1IiVEL
wavelengths in the 3000A to 4000A range.lf
for extended periods, then opaque labels shouldb,e .
placed over the window to prevent unintentional
erasure.
On the EM2 Board:
The recommended erasure procedure is exposure to
ultraviolet light which has a wavelength of 2537 A. The
integrated dose (UV intensity multiplied by exposure
time) for erasure should be a minimum of 15W·sec/cm.
The erasure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with a 12,0001'
W/em 2 power rating. Place the 8755A within one inch of
the lamp during erasure. Some lamps include a filter
which should be removed before erasure.
Intellec® 8080/8085 Microcom·
puter Design Aid. Requires
PROMPT·975 Programming
Adapter.
Table 1. 8755A Proramming Module
Physical Characteristics
SPECIFICATIONS
Width: 2.75 in. (6.98 cm)
Height: 4.25 in. (10.79 cm)
Depth: 1.5 in. (3.81 cm)
Weight: 0.5 Ib (0.23 kg)
Operating Environment
Intel® 8755A EPROM Programming
UPP·103
PROMPT·48
PROMPT·80/85
Electrical Characteristics
DC Power
Intellec Microcomputer Development System
Vcc=5V ±5%
Icc = 300 mA (maximum)
Software
8048 Assembler
ISIS·II Diskette Operating System
Environmental Characteristics
Equipment Supplied
Operating Temperature -
EM2 Printed Circuit Board
EM2 Reference Manual
Operating Humidity without condensation
ORDERING INFORMATION
Part Number
Description
MDS·EM2
8022 Emulation Board
12·82
0 to 55·C
Up to 95% relative humidity
UPP-103*
UNIVERSAL PROM PROGRAMMER
*Replaces UPP·101, UPP·102 Universal PROM Programmers
Intellec development system peripheral
for PROM programming and verification
Universal PROM mapper software provides powerful data manipulation and
programming commands
Provides flexible power source for
system logic and programming pulse
generation
Provides personality cards for programming all Intel PROM families
Provides zero insertion force sockets for
both 16-pin and 24-pin PROMs
Holds two personality cards to facilitate
programming operations using several
PROM types
The UPP·103 Universal PROM Programmer is an Intellec system peripheral capable of programming and verifying the
following Intel programmable ROMs (PROMs): 1702A, 2704, 2708, 2716, 3601, 8702A, 8704, and 8708. In addition, the
UPP·103 programs the PROM memory portions of the 8748 microcomputer and the 8755 PROM and 1/0 chip. Program·
ming and verification operations are initiated from the Intellec development system console and are controlled by the
universal PROM mapper (UPM) program.
12·83
U~~·'03
or diskette files and a PROM plugged into the Universal
PROM Programmer. It uses Intellec system memory for
intermediate storage. The UPM transfers data in 8-bit
HEX, BNPF, or binary object format between paper tape
or diskette files and the Intellec system memory. While
the data is in Intellec system memory, it can be displayed and changed. In addition, word length, bit position, and data sense can be adjusted as required for the
PROM to be programmed. PROMs may also be duplicated or altered by copying the PROM contents into the
Intellec system memory. Easy to use program and compare commands give the user complete control over programming and verification operations. The UPM eliminates the need for a variety of personalized PROM programming routines because it contains the programming algorithms for all Intel PROM families.
FUNCTIONAL DESCRIPTION
Universal PROM Programmer
The basic Universal PROM Programmer (UPP) consists
of a controller module, two personality card sockets, a
front panel, power supplies, a chassis, and an Intellec
development system interconnection cable. An Intel
4040-based intelligent controller monitors the commands from the Intellec System and controls the data
transfer Interface between the selected PROM persona·
lity card and the Intellecmemory. A unique personality
card contains the appropriate pulse generation func·
tions for each Intel PROM family. Programming and veri·
fying any Intel PROM may be accomplished by selecting
and plugging in the appropriate personality card. The
front panel contains a power·on switch and indicator, a
reset switch, and two zero-force insertion sockets (one
16-pin and one 24-pin or two 24-pin). A central power
supply provides power for system logic and for PROM
programming pulse generation. The Universal PROM
Programmer may be used as a table top unit or mounted
in a standard 19-inch RETMA cabinet.
Optional Versions
There are two versions of the UPM: one that runs under
the Intellec system monitor (paper tape system), and
one that runs under ISIS-II, the Intellec diskette operat·
ing system (diskette-based system). The paper tape version is included with the Universal PROM Programmer.
The diskette-based version of the UPM is available on all
ISIS-II system diskettes.
Universal PROM Mapper
The Universal PROM Mapper (UPM) is the software pro·
gram used to control data transfer between paper tape
SPECIFICATIONS
3604A, 3624A, 3604AL, 36046-6, 3605, 3625, 3608, 3628
UPP-872: 8702A/1702A personality card
UPP-878: 8708/8704/2708/2704 personality card
Hardware Interface
Data - Two 8-bit unidirectional buses
Commands - 3 write commands, 2 read commands,
one initiate command
PROM Programming Sockets
UPP-501: 16-pin/24-pin socket pair
UPP-502: 24-pin/24·pin socket pair
UPP-562: Socket adaptor for 3621, 3602, 3622, 3602A,
3622A
UPP-555: Socket adaptor for 3604AL, 36046-6, 3608, 3628
UPP·566: Socket adaptor for 3605, 3625
PhYSical Characteristics
Width - 6 in. (14.7 cm)
Height - 7 in. (17.2 cm)
Depth - 17 in. (41.7 cm)
Weight - 18 Ib (8.2 kg)
Equipment Supplied
Electrical Characteristics
AC Power Requirements - 50-60 Hz; 115/230V AC: 80W
Environmental Characteristics
Operating Temperature - O°C to 55°C
Optional Equipment
Personality Cards
UPP-361: 3601 personality card
UPP-816: 2716 personality card
UPP-832: 2732 personality card
UPP-848: 8748 personality card with 40-pin adaptor
socket
UPP-855: 8755 personality card with 40-pin adaptor
socket
UPP-865: 3602, 3622, 3602A, 3622A, 3621, 3604, 3624,
Cabinet
Power supplies
4040 intelligent controller module
Specified zero insertion force socket pair
Intellec development system interface cable
Universal PROM Mapper program (paper tape version disk-based version available on "ISIS-II diskettes)
ORDERING INFORMATION
Part Number
Description
UPP-103
Universal PROM programmer with
16-pin/24-pin socket pair and
24-pin/24-pln socket pair
12-84
Reference Manuals
9800133 - Universal PROM Programmer Hardware
Reference Manual (SUPPLIED)
9800554 - Intellec Series II Schematics Drawings
(SUPPLIED)
9800819 - Universal PROM Programmer User's Manual
(SUPPLIED)
SDK·8S
MeS·8S SYSTEM DESIGN KIT
Complete single board microcomputer
system including CPU, memory, and 110
Large wire·wrap area for custom
interfaces
Popular 8080A instruction set
Easy to assemble, low cost, kit form
Interfaces directly with TTY
Extensive system monitor software in
ROM
High performance 3 MHz 808SA CPU
(1.3 /As instruction cycle)
Interactive LED display and keyboard
Comprehensive design library included
The SDK-85 MCS-85 System Design Kit is a complete single board microcomputer system in kit form_ It contains all
components required to complete construction of the kit, including LED display, keyboard, reSistors, caps, crystal,
and miscellaneous hardware_ Included is a preprogrammed ROM containing a system monitor for general software
utilities and system diagnostics. The complete kit includes a 6-digit LED display and a 24-key keyboard for a direct insertion, examination, and execution of a user's program. In addition, it can be directly interfaced with a teletype terminal. The SDK-85 is an inexpensive, high performance prototype system that has deSigned-in flexibility for simple interface to the user's application.
12-85
SDK·8S
FUNCTIONAL DESCRIPTION
The SDK-85 is a complete 8085A microcomputer system
on a single board, in kit form. It contains all necessary
components to build a useful, functional system. Such
items as resistors, capacitors, and sockets are included.
Assembly time varies from three to five hours, depending on the skill of the user. The SDK-85 functional block
diagram is shown in Figure 1.
808SA Processor
The SDK-85 is designed around Intel's 8085A microprocessor. The Intel 8085A is a new generation, complete
8-bit parallel central processing unit (CPU). Its instruction set is 100% software upward compatible with the
8080A microprocessor, and it is designed to Improve the
present 8080A's performance by higher system speed.
Its high level of system integration allows a minimum
system of three IC's: 8085A (CPU), 8156 (RAM), and
8355/8755 (ROM/PROM). A block diagram of the 8085A
microprocessor is shown In Figure 2.
Addressing - The 8085A uses a multiplexed data bus.
The 16-bit address is split between the 8-bit address bus
and the 8-bit address/data bus. The on-chip address
latches of 8155/8156/8355/8755 memory products allows
a direct interface with the 8085A.
System Monitor
A compact but powerful system monitor is supplied
with the SDK-85 to provide general software utilities and
system diagnostics. It comes in a pre-programmed
ROM.
Communications Interface
The SDK-85 communicates with the outside world
through either the on-board LED display/keyboard combination, or the user's TTY terminal (jumper selectable).
ROM/IO (8355)
EPROM/IO (8755)
ADDRESS
CPU
System Integration - The 8085A incorporates all of the
features that the 8224 (clock generator) and 8228 (system controller) provided for the 80MA, thereby offering
a high level of system integration.
DECODER
KEYBOARD/DISPL~Y
DATA
FIELD
FIELD
I ~CI
C./.
I
I
I
I ~
I -v
~
I
8'
:1
INTERRUPT
INPUTS
SDK·8S KEYBOARD LAYOUT
RESET
S~~~~E
~~TC~
GO
J
OPTIONAL
NEXT
EXEC
9
~:~:6~EI~~~~~~~~~g~~DED ON THE PC BOARD FOR THE DEVICE BUT THE
Figure 1. SDK·aS System Design Kit Functional Block Diagram
12·86
C
0
~ ~
E
F
A
B
SUBST EXAM 4
5
6
7
MEM
REG SPH SPL PCH peL
8279
[~ ~
P,. ',C,'o
'-
C' C/..
,-,
c",
L:::I.:=-'='-_..L:..I.-'
i'i'n '~
:0-.,.5" I ,
FOR BUS EXPANSION
ADDRESS
0
1
2
~
I
I
I
I
I
I
~-----'ff
: .--':~-;
I
I
I
•
r----'
~ _:~6__
J
~~~A
SDK·85
Rsr S.5
INSIDE THE 8085:
RSr 7.5
SID
SOD
181
REG
MACHINE
CYCLE
ENCODINO
181
REG
0
REG.
181
E
REG.
181
H
REG
lSI
L
181
REGISTER
REG
STACK POINTER
PROGRAM COUNTER
(l61
(16)
POWER{_t5V
SUPPLY
_
GND
INCREMENTER DECREMENTER
1161
TIMING AND CONTROL
•
•
SEVEN 8-BIT REGISTERS. SIX OF THEM CAN BE LINKED
IN REGISTER PAIRS FOR CERTAIN OPERATIONS.
8-BIT ALU.
•
•
A1S,AS
A07'AD o
ADDRESS BUS
ADDRESSIDATA BUS
16-BIT STACK POINTER (STACK IS MAINTAINED
OFFBOARD IN SYSTEM RAM MEMORY).
16-BIT PROGRAM COUNTER.
Figure 2. 808SA Microprocessor Block Diagram
Both memory and I/O can be easily expanded by simply
soldering in additional devices in locations provided for
this purpose. A large area of the board (45 sq. in.) is laid
out as general purpose wire-wrap for the user's custom
interfaces.
Commands - Keyboard monitor commands and teletype monitor commands are provided in Table 1 and
Table 2, respectively.
Command
Display memory
Assembly
Only a few simple tools are required for assembly;
soldering iron, cutters, screwdriver, etc. The SDK-85
user's manual contains step-by-step instructions for
easy assembly without mistakes. Once construction is
complete, the user connects his kit to a power supply
and the SDK-85 is ready to go. The monitor starts immediately upon power·on or reset.
Command
Reset
Go
Operation
Starts monitor.
Allows user to execute user program.
Single step
Allows user to execute user program one instruction at a tlmeuseful for debugging.
Substitute memory Allows user to examine and
modify memory locations.
Examine register
Allows user to examine and
modify 8085A's register contents.
Vector interrupt
Serves as user interrupt button.
Substitute memory
Insert instructions
Move memory
Examine register
Go
Operation
Displays multiple memory locations.
Allows user to examine and
modify memory locations one
at a time.
Allows user to store multiple
bytes in memory.
Allows user to move blocks of
data in memory.
Allows user to examine and
modify the 8085A's register
contents.
Allows user to execute user
programs.
Table 2. Teletype Monitor Commands
Documentation
In addition to detailed information on using the
monitors, the SDK-85 user's manual provides circuit diagrams, a monitor listing, and a description of how the
system works. The complete design library for the
SDK-85 is shown in Figure 3 and listed in the Specifications section under Reference Manuals.
Table 1. Keyboard Monitor Commands·
12-87
SDK·8S
Figure 3. SDK·a5 Design Library
808SA INSTRUCTION SET
Table 3 contains a summary of processor instructions
used for the 8085A microprocessor.
Mnemonic
I
Description
I
I~IOCk3
Instruction Code2
I
07 06 05 04 03 02 01 DO Cycles
MOVE, LOAD, AND STORE
MOVr1r2
Move register to register
0
1
MOVM,r
Move register to memory
0
1
1
MOVr.M
Move memory to register
0
1
0
MVI r
Move immediate register
0
0
0
0
MVI M
Move immediate memory
0
0
1
1
0
LXI B
Load immediate register
PalrB&C
0
0
0
0
0
LXI 0
Load immediate register
Pair 0 & E
0
0
0
1
0
LXI H
Load Immediate register
Pair H & L
0
0
1
0
0
STAX B
Store A Indirect
0
0
0
0
Mnemonic1
I
Description
I
Instruction Code2
3
oiCIOCk
07 06 05 04 03 02 01 DO Cycle.
LXI SP
Load immediate stack
pOinter
0
0
1
1
0
0
0
1
10
7
INX SP
Increment stack pOinter
0
0
1
1
0
0
1
1
6
7
OCX SP
Decrement stack
pOinter
0
0
1
1
1
0
1
1
6
1
0
0
0
0
1
1
10
1
0
1
1
0
1
0
7110
0
S
S
S
4
1
0
S
S
S
0
0
1
1
0
0
1
1
0
7
1
1
0
10
JUMP
0
0
1
10
JMP
Jump unconditional
1
JC
Jump on carry
1
0
0
1
10
0
0
1
10
0
0
0
0
JNC
Jump on no carry
1
1
0
1
0
0
1
0
7110
JZ
Jump on zero
1
1
0
0
1
0
1
0
7110
JNZ
Jump on no zero
1
1
0
0
0
0
1
0
7110
1
0
0
1
0
7110
7110
1
0
7
JP
Jump on positive
1
1
1
STAX 0
Store A Indirect
0
0
0
1
0
0
1
0
7
JM
Jump on minus
1
1
1
1
1
0
1
0
LOAX B
Load A indirect
0
0
0
0
1
0
1
0
7
JPE
Jump on parity even
1
1
1
0
1
0
1
0
7110
LOAX 0
Load A Indirect
0
0
0
1
1
0
1
0
7
JPO
Jump on parity odd
1
1
1
0
0
0
1
0
7110
STA
Store A direct
0
0
1
1
0
0
1
0
13
PCHL
1
1
0
1
0
0
1
6
Load A direct
0
0
1
1
1
0
1
0
13
H & L to program
counter
1
LOA
SHLO
Store H & L direct
0
0
1
0
0
0
1
0
16
LHLO
Load H & L direct
0
0
1
0
1
0
1
0
16
CALL
Call unconditional
1
1
0
0
1
1
0
1
18
XCHG
Exchange 0 & E, H & L
registers
1
1
1
0
1
0
1
1
4
CC
Call on carry
1
1
0
1
1
1
0
0
9118
CNC
Call on no carry
1
1
0
1
0
1
0
0
9118
Push register pair B & C
on stack
1
1
0
0
0
1
0
1
12
CZ
Call on zero
1
1
0
0
1
1
0
0
9118
CNZ
Call on no zero
1
1
0
0
0
1
0
0
9118
PUSH 0
Push register paIr 0 & E
on stack
1
1
0
1
0
1
0
1
12
CP
Calion positive
1
1
1
1
0
1
0
0
9118
CM
Call on minus
1
1
1
1
1
1
0
0
9118
PUSH H
Push register pair H & L
on stack
1
1
1
0
0
1
0
1
12
CPE
Calion parity even
1
1
1
0
1
1
0
0
9118
PUSH PSW
CPO
Calion parity odd
1
1
1
0
0
1
0
0
9/18
Push A and flags on
stack
1
1
1
1
0
1
0
1
12
POP B
Pop register pair B & C
off stack
1
1
0
0
0
0
0
1
10
Return
1
1
0
0
1
0
0
1
10
Return on carry
1
1
0
1
1
0
0
0
6112
POP 0
Pop register pair 0 & E
off stack
1
1
0
1
0
0
0
1
10
ANC
Return on no carry
1
1
0
1
0
0
0
0
6112
Pop register pair H & L
off stack
AZ
Return on zero
1
1
0
0
1
0
0
0
6112
POP H
1
1
1
0
0
0
0
1
10
POP PSW
Pop A and flags off
stack
1
1
1
1
0
0
0
1
10
XTHL
Exchange top of stack
H&L
1
1
1
0
0
0
1
1
16
SPHL
H & L to stack pOinter
1
1
1
1
1
0
0
1
6
STACK OPS
PUSH B
CALL
RETURN
RET
RC
ANZ
Return on no zero
1
1
0
0
0
0
0
0
6112
AP
Return on POSitive
1
1
1
1
0
0
0
0
6112
AM
Return on minus
1
1
1
1
1
0
0
0
6112
continued'
12·88
SDK·8S
Mnemonlc '
I
Description
I Instrucllon Code2
I 07 08 05 0 4 0 3 O2 0 ,
I Clock3
I Cycles
DO
Mnemonic 1
I~
Description
I
I Clock3
Instruction Code2
10 7 06 05 0 4 03 O2 0 , Dol Cycles
RPE
Return on parity even
1
1
1
0
1
0
0
0
6112
LOGICAL
RPO
Return on parity odd
1
1
1
0
0
0
0
0
6112
ANA r
And register with A
1
0
1
0
0
S
S
S
4
XAA r
Exclusive Or register
with A
I
0
1
0
1
S
S
S
4
ORA r
Or register with A
1
0
1
1
0
S
S
S
4
CMPr
Compare register with A
1
0
1
1
1
S
S
S
4
4
ANA M
And memory with A
1
0
1
0
0
1
1
0
7
XRA M
Exclusive Or memory
with A
1
0
1
0
1
1
1
0
7
RESTART
RST
1
Aestart
1
A
A
A
1
1
1
12
INCREMENT AND DECREMENT
INA r
Increment register
0
0
0
0
0
1
0
0
DCA r
Decrement register
0
0
0
0
0
1
0
1
4
INR M
Increment memory
0
0
1
1
0
1
0
0
10
OCR M
Decrement memory
0
0
1
1
0
1
0
1
10
ORA M
Or memory with A
1
0
1
1
0
1
1
0
7
INX B
Increment B & C
registers
0
0
0
0
0
0
1
1
6
CMP M
Compare memory with A
1
0
1
1
1
1
1
0
7
INX 0
Increment 0 & E
registers
0
0
0
1
0
0
1
1
6
INX H
Increment H & L
registers
0
0
1
0
0
0
1
1
6
OCX B
Decrement B & C
0
0
0
0
1
0
1
1
6
OCX 0
Oecrement 0 & E
0
0
0
1
1
0
1
1
6
OCX H
Decrement H & L
0
0
1
0
1
0
1
1
6
Add register to A
1
0
0
0
0
S
S
S
And immediate with A
1
1
1
0
0
1
1
0
7
Exclusive Or immediate
with A
1
1
1
0
1
1
1
0
7
ORI
Or immediate with A
1
1
1
1
0
1
1
0
7
CPI
Compare immediate
with A
1
1
1
1
1
1
1
0
7
RLC
Rotate A left
0
0
0
0
0
1
1
1
4
RRC
Rotate A right
0
0
0
0
1
1
1
1
4
RAL
Rotate A left through
carry
0
0
0
1
0
1
1
1
4
RAR
Rotate A right through
carry
0
0
0
1
1
1
1
1
4
ROTATE
ADD
ADDr
ANI
XRI
4
ADC r
Add register to A with
carry
1
0
0
0
1
S
S
S
4
ADD M
Add memory to A
1
0
0
0
0
1
1
0
7
AOC M
Add memory to A with
carry
1
0
0
0
1
1
1
0
7
AOI
Add immediate to A
1
1
0
0
0
1
1
0
7
CMA
Complement A
0
0
1
0
1
1
1
1
4
ACI
Add immediate to A
with carry
1
1
0
0
1
1
1
0
7
STC
Set carry
0
0
1
1
0
1
1
1
4
DAD B
AddB&Cl0H&L
0
0
0
0
1
0
0
1
10
CMC
Complement carry
0
0
1
1
1
1
1
1
4
DAD 0
Add 0 & E to H & L
0
0
0
1
1
0
0
1
10
OM
Decimal adjust A
0
0
1
0
0
1
1
1
4
DAD H
AddH&LloH&L
0
0
1
0
1
0
0
1
10
DAD SP
Add stack painter to
H&L
0
0
1
1
1
0
0
1
10
SPECIALS
INPUT/OUTPUT
IN
Input
1
1
0
1
1
0
1
1
10
OUT
Output
1
1
0
1
0
0
1
1
10
EI
Enable interrupts
1
1
1
1
1
0
1
1
4
01
Disable interrupts
1
1
1
1
0
0
1
1
4
NOP
No-operation
0
0
0
0
0
0
0
0
4
HLT
Halt
0
1
1
1
0
1
1
0
5
SUBTRACT
SUB r
Subtract register from A
1
0
0
1
0
S
S
S
4
SBB r
Subtract register from A
with borrow
1
0
0
1
1
S
S
S
4
SUB M
Subtract memory from A
1
0
0
1
0
1
1
0
7
SSB M
Subtract memory from
A with borrow
1
0
0
1
1
1
1
0
7
SUI
Subtract immediate
from A
1
1
0
1
0
1
1
0
7
SBI
Subtract immediate
from A with borrow
1
1
0
1
1
1
1
0
7
CONTROL
NEW 8085 INSTRUCTIONS
RIM
Read interrupt mask
0
0
1
0
0
0
0
0
4
SIM
Set interrupt mask
0
0
1
1
0
0
0
0
4
Notes
1. All mnemonics copyright © Intel Corporation 1977.
2. DDDorSSS: B=OOO, C=001, 0=010, E=01"
H=100, L=101, Memory = 110, A=111~
3. Two possible cycle times. (6/12) indicates instruction cycles dependent on condition flags.
Table 3. Summary of 808SA Processor Instructions
SPECIFICATIONS
Addressing
Central Processor
ROM - 0000-07FF (expendable to OFFF with an addi·
tional 8355/8755A)
RAM - 2000-20FF (2800-28FF available with an additional8155)
CPU - 8085A
Instruction Cycle Tcy - 330 ns
1.3 ,..s
Memory
Note
The wire·wrap area of the SDK-a5 PC board may be used for additional
custom memory expansion up to the 64K-byte addressing limit of the
ROM - 2K bytes (expandable to 4K bytes) 8355/8755A
RAM - 256 bytes (expandable to 512 bytes) 8155
80a5A~
12-89
SDK·85
Input/Output
Physical Characteristics
Parallel - 38 lines (expandable to 76 lines)
Serial - Through SID/SOD ports of 8085A. Software
generated baud rate.
Baud Rate - 110
Width - 12.0 in. (30.5 cm)
Height - 10 in. (25.4 cm)
Depth - 0.50 in. (1.27 cm)
Weight - approx. 12 oz
Interfaces
DC Power Requirement (power supply not included in
kit)
Electrical Characteristics
Bus - All signals TTL compatible
Parallel 1/0 - All signals TTL compatible
Serial 1/0 - 20 mA current loop TTY
Voltage
Note
By populating the buffer area of the board, the user has access to all bus
Current
Vee 5V ±5'10
1.3A
VTTy-l0V ± 10%
0.3A
signals that enable him to design custom system expansions into the
kit's wire-wrap area.
(VTTY required only if teletype
is connected)
Interrupts
Environmental Characteristics
Three Levels
(RST 7.5) - Keyboard interrupt
(RST 6.5) - TTL input
(INTR) - TTL input
Operating Temperature -
DMA
Hold Request input.
Jumper selectable. TTL compatible
Software
System Monitor - Pre-programmed 8755A or 8355 ROM
Addresses - 0000-07FF
Monitor 1/0 - Keyboard/display or TTY (serial I/O)
Reference Manuals
9800451 - SDK-85 User's Manual (SUPPLIED)
9800366 - MCS-85 User's Manual (SUPPLIED)
9800301 - 8080/8085 Assembly Language Programming Manual (SUPPLIED)
8085/8080 Assembly Language Reference Card (SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
Description
SDK-85
MCS-85 system design kit
0-55°C
12-90
SDK·86
MeS·86 SYSTEM DESIGN KIT
Complete single board microcomputer
system including CPU, memory, and 1/0
Interactive LED display and keyboard
Wire wrap area for custom interfaces
Easy to assemble kit form
High performance 8086 16·bit CPU
Extensive system monitor software in
ROM
Interfaces directly with TTY or CRT
Comprehensive design library included
The SDK-86 MCS-86 System Design Kit is a complete single board 8086 microcomputer system in kit form. It contains
all necessary components to complete construction of the kit, including LED display, keyboard, resistors, caps, crystal, and miscellaneous hardware. Included are preprogrammed ROMs containing a system monitor for general software utilities and system diagnostics. The complete kit includes an 8-digit LED display and a mnemonic 24-key keyboard for direct insertion, examination, and execution of a user's program. In addition, it can be directly interfaced
with a teletype terminal, CRT terminal, or the serial port of an Intellec system. The SDK-86 is a high performance prototype system with designed-in flexibility for simple interface to the user's application.
12-91
SDK·as
FUNCTIONAL DESCRIPTION
A block diagram of the 8086 microprocessor is shown in
Figure 2.
The SDK-86 is a complete MCS-86 microcomputer system on a single board, in kit form. It contains all necessary components to build a useful, functional system.
Such items as resistors, caps, and sockets are included.
Assembly time varies from 4 to 10 hours, depending on
the skill of the user. The SDK-86 functional block diagram is shown in Figure 1.
System Monitor
8086 Processor
The SDK-86 communicates with the outside world
through either the on-board light emitting diode (LED)
display/keyboard combination or the user's TTY or CRT
terminal (jumper selectable), or by means of a special
mode in which an Intellec development system
transports finished programs to and from the SDK-86.
Memory may be easily expanded by simply soldering in
additional devices in locations provided for this purpose. A large area of the board (22 square inches) is laid
out as general purpose wire-wrap for the user's custom
interfaces.
The SDK-86 is designed around Intel's 8086 microprocessor. The Intel 8086 is a new generation, high performance microprocessor implemented in N-channel, depletion load, silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor
features attributes of both 8-bit and 16-bit microprocessors in that it addresses memory as a sequence
of 8-bit bytes, but has a 16-bit wide physical path to
memory for high performance. Additional features of
the 8086 include the following:
• Direct addressing capability to one megabyte of
memory
• Assembly language compatibility with 8080/8085
• 14 word x 16-bit register set with symmetrical operations
• 24 operand addressing modes
• Bit, byte, word, and block operations
• 8 and 16-byte signed and unsigned arithmetic in
binary or decimal mode, including multiply and divide
• 5 MHz clock rate
• MULTlBUS compatible system interface
A compact but powerful system monitor is supplied
with the SDK-86 to provide general software utilities and
system diagnostics. It comes in preprogrammed read
only memories (ROMs).
Communications Interface
Assembly
Only a few simple tools are required for assembly: soldering iron, cutters, screwdriver, etc. The SDK-86
assembly manual contains step-by-step instructions for
easy assembly with a minimum of mistakes. Once construction is complete, the user connects his kit to a
power supply and the SDK-86 is ready to go. The monitor
starts immediately upon power-on or reset.
Commands - Keyboard mode commands, serial port
commands, and Intellec slave mode commands are
summarized in Table 1, Table 2, and Table 3, respectively. The SDK-86 keyboard is shown in Figure 3.
CONTROL
LINES
CONNECTOR
ADDRESS
BUS EXPANSION
CONNECTOR
I
BAUD RATE ~----~I
GENERATOR
1....,-"::::::":':':"..,.--'
LEO DISPLAY
Figure 1. SDK·86 System Design Kit Functional Block Diagram
12-92
SDK·86
EXECUTION UNIT
BUS INTERFACE UNIT
)
REGISTER FilE
R~~~~;::I~~E I
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5 WORDS)
DATA.
POINTER. AND
INDEX REGS
(8 WORDS)
,.-....::.'----.--iH"lIS7
A1~Se
A,itS,
Figure 4. SDK·86 Design Library
FLAGS
3
DT/R.DEN.AlE
Command
Operation
Reset
Go
6·BYTE
INSTRUCTION
QUEUE
Single step
T~--_r--------~~------,
INT--_
NMI---
Substitute
memory
HOLD
HlDA--;.-,-__- , -__- r__--r__"?'~
elK
RESET
READY
Examine
register
Block move
Vee
GND
Figure 2. 8086 Microprocessor Block Diagram
Input or output
Starts monitor.
Allows user to execute user pro·
gram, and causes it to halt at prede·
termined program stop. Useful for
debugging.
Allows user to execute user pro·
gram one instruction at a time. Use·
ful for debugging.
Allows user to examine and modify
memory locations in byte or word
mode.
Allows user to examine and modify
8086 register contents.
Allows user to relocate program
and data portions in memory.
Allows direct control of SDK·86 I/O
facilities in byte or mode.
Table 1. Keyboard Mode Commands
SYSTM
RESET
INTR
C
0
liP
IFL
+
-
8
9
A
B
IW/CS
OW/DS
IISS
IES
:
REG
,
E
F
4
5
6
7
IB/SP
OB/BP
MV/SI
EW/DI
0
1
2
3
EB/AX
ER/BX
GO/CX
ST/DX
Command
Operation
Dump memory
Allows user to print or display large
blocks of memory information in
hex format than amount visible on
terminal's CRT display.
Allows user to display blocks of
memory information larger than
amount visible on terminal's CRT
display.
Allows user to transmit finished
programs into and out of SDK·86 via
TTY paper tape punch.
Start/continue
display
Punch/read
paper tape
Table 2. Serial Mode Commands
Figure 3. SDK·86 Keyboard
Documentation
In addition to detailed information on using the moni·
tors, the SDK·86 user's manual provides circuit dia·
grams, a monitor listing, and a description of how the
system works. The complete design library for the
SDK·86 is shown in Figure 4 and listed in the Specifica·
tions section under Reference Manuals.
Command
Operation
Up/download
Allows user to transport finished pro·
grams between Intellec and SDK·86,
using special Intellec utility program.
Note
The Intellec slave mode utilizes all the keyboard mode commands
and serial mode commands (listed in Tables 1 and 2, respectively), as
well as the up/download slave mode command, via the console of
the Intellect development system, using the SDK·CB6 product.
Table 3. Intellec Slave Mode Commands
12·93
SDK·86
8086 INSTRUCTION SET
Table 4 contains a summary of processor instructions
used for the 8086 microprocessor.
Mnemonic and
Description
Mnemonic and
Description
Instruction Code
Instruction Code
DATA TRAISFER
78543210
Register/memory lolllom register
Immediate to reglsler/memory
Immediate to register
11543210
711543210
11543210
CMP
f;ll~O~O~O=:,~o~'.;;w"fI'im'~',::,'~..!;='-'/~m-+_-;::;:---'_=="7"l
f;ll~'~O~O,.;;o";;,~,,,;;w"fI;;;",,,=o;;.o,:;;o,.;;'/;;;m~=c~"~"~'f--"""",,,,,,,,-,,w-,o'-,I
1 0 1 1 w reg
data
data If
w~ 1
=
Compln:
Reglsterlmemory and register
:::~ ::~I~:~:;:~ory
:::::::::
18543Z10
11543Z10
10 10 0 0 0 w
addr-Iow
addr-hlgh
11 {} 1 0 0 0 1 w I
AAS~ASCII adjust for subtract
10 0 1 1 1 1 1 1 I
Accumulator to memory
addr-Iow
addr-hlgh
OAS-Declmal adlust lor subtract
10010/111
Ii
Imod 0 reg
Imod 0 reg
0 0 0 1 1 10
Segment register to register/memory ) 1 0 0 0 1 1 0 0
rim
MUL~Multlply
rim
IMUL=lntegermulllply {Signed)
(unSigned)
AAM:ASCII adjusl lor mulliply
PUSH .. Palh:
Register/memory
Register
1 1 t I l l 1 1 mod 110 rim
I)
Segment register
!I)
1 I) 1 0 reg
I)
0 reg 1 1 0
I
11
Register
II) 1 I)
Segmentregtster
10
I)
Register/memory with register
11
I) I)
Reglsterwllh accumulator
1,0010 reg
I)
11
0 0 1 1 W Imod re!)
rim
I
port
10010 W I
111 10110 w I
NOT-Invert
1 1 1 1 0 1 1 w mod 0 1 0 rim
SHL/SAL-Shllllogical/anlhmetic left
1 1. 01 00 v w mod 1 00 rim
logical flghl
1110011 W
1 10100 v w mod 1 1 1
1I0l-Rotate left
1 10100 v w modO 0 0 rim
1110100vwlmodOOI rim
IICL=Rotale Ihrough carry flag lett
110100 v w modO 1 0 rim
RCR=Rotate through carry fight
110100 v w modO 1 1 rim
1110111 w
Vanable port
ruT~Translate
port
1 1 0 1 0 0 v w mod 1 0 ,
SAII-ShlftarrlhmellC right
1I01l=Rotale nghl
OUT", OU.,UI
Fixed port
0 0 00 10 10
I
lOGIC
I
SHII~Shllt
CD
1 10 10 10 1
1001 1000
\1001 1001
I
III", Inpul
Vaflable port
I
I
ICHG .. Etchlngl:
Fixed port
0 0 0 0 , 0 10
11 1 1 1 0 1 1 w mod 1 1 1 rim
1
11 feg
0 reg 1
11010100
11 1 1 , 0 1 1 w Imod 110 rim
CaW'Convert byte 10 word
0 0111 1 ImodO 0 0 rim
I
1 1 1011 w Imod 100 rim
t i l l 0 1 1 W mod 101
IOIV-Integerdlvlde (Signed)
CWO=Converl word to double word
Register/memory
11
OIV=Dlvlde (unSI!)ned)
AAO=ASCII adlust lor diVide
pop,Pto,
71543Z10
f::;-::":::":;:":;:":;:':':.;;,:+m~,:::.,,:,.,,:,.'d:':"".:.:";;;m4...".",,::::'~;;:aw__,.,+-"""""-",-,''",w",'0e.J'
Memory to accumulator
Register/memory to segment register
71543Z10
F.10=,0",:,",:,",:,~O.::.',:;w,.1m::;;,;:;":":.l":=""/;;,m-+--.,.,-----,C-,,--,---::-1
byte to Al
It 1 0 1 0 l I t
1
mod reg
rim
mod reg
rim
Reg Imemory and register to either
Immediate to register/memory
0 1 I) 0
mod reg
rim
Immediate 10 accumulator
10001 t
I)
LOI-load pomter to OS
11
LEI-Load pomterto ES
1 10
UHF-Load AH With lIags
10011111
IAIIF-Store AH Into flags
AND - Ami.
0 0101
LEA",Load EA to register
I)
I
I)
10011110
TEST
I
'UIMF",Push flags
110011 100
'O'F-Pop flags
1,0011 101 I
=
data II w-l
~(1~0~0~0;;0.:,,;;0;:w41;;;m'~''';'~''b.:.:'';;;m~_--c_---,_~~----,
Or:
Immediate to register/memory
Immediate 10 accumulator
ADD", Add:
~o]o]o]oIoIoI'~w~m~'~':::,j1.,~'/~m+_ _ _- ,_ _c--:co
1 00000 s W mod 000 rim
0 0 0 0 lOw I
dala
I
~
Reg Imemory and register 10 either
II)
0 0 1 0 0 lOw
And luncUon to flagl, no ruu1ic"--c-:~--:--c--,----:------,
Reglslerlmemory and register
ARITHMETIC
Immediate to accumulator
~
Immediate data and reglsler/memory F,ll~,c;,=,;,~o=,;'~'''':."1I;;;m';;';"o,,:0~o:"'/,;;m"'t=c::o:''''i'''~'f--"""="",,,,,,w-,-'-,I
Immediate data and accumulator
11 0 1 0 1 0 0 w
data
data 11 w 1
OR
Reg Imemory With register 10 either
Immediate 10 reglsterlmemory
0jO~'jOjOjo!d~w~l~m'~'r'f"£j"~m::t=~~=+=~~~
0 0 0 0 0 0 w mod 1 00 rim
data
data II W 1
F,I
data
data
data II s w-Ol
data If w-I
XOR
=
F.Io=,o=,o=,o",:,=,o="';;."fl;;;m'::::',.'~"'c""/,;;m-+_----::-;:-----,_=-.-c...,....,
~11GoQo~0~0~ojo~wjl=m'='=0~O~'='/=mj::J~"~"~J---""",,,,",,,-,,w.:c-'-,1
liTIiii
0 w I
data
data If w ,
helu.lv. or:
Aeglmemory and reglsler to either
:::::::::::
::~I~:~:;:~ory
\F.o~o=:,=:,=,o=,o="';;."fI;;,;m'§'",',:""!;='-'/::,,m-+_--:::;:;---'_==:T1
F.;~:~:~:=,:~:~:,:;:~m';;',;;'":',o;;",,,;,;'/;;;m~=c,C',,;;;;:~~:aw~_7,'f---="="="=w-,"-'
ADC '" Add wllh em,:
~;~:::o;: :~tl:I::~~~:~:yelthar F.:";:";:~;';:':';:':~:"'::,.:;;;;:~:;:'o,~~gO~:;::":-+---;;;":;:;,,--,-c:,c:,,,:c,:;:;,,C:wC:;.O;c-"
Immediate to accumulator
I0 0 0 lOt 0 W I
dala
data If w 1
IIIC '" Incl1mlnl:
Register/memory
1 1 1 1 1 , 1 W mod 000 rim
Register
01000 reg
AM-ASCII adjust for add
00110111
DAA.. Decimal adlust for add
0010011'
STRING MANIPULATION
REP-Aepeat
11 1 1 1 001
z [
MOYS =: Move byte/word
1 0 1 0 0 lOw
CMPS =: Compare bytelword
10 100 11 W
SCAS =:. Scan bytelword
10 10 1 1 1W
IU., .._
LODS =: load bytelwd to AUAX
1 0 1 0 1 lOw
=~~:::O;r::n~~:::::::;:er F.:~:=:;~:=:;";:~:';;:=I"'::§:""'~;',;:,='~;~:==f----;;;":;:,,c-,.-,,;::..;:-,"-",".CC."O"
STOS =: Stor bytelwd Irm AUA
1 I) 1 0 lOt w
Immedllte from accumulator
... =
0010110 W
data
Reg.fmemory and register to 'Ither
000110 d w mod reg
Immediate from reols1erlmemory
100000sw modOl1 rIm
Immediate from accumulator
0001 t lOw
OEC
=
datalfw-l
IIMnclwlllt1llrrlw
rIm
data
IIIcl1mlnl:
Reglsterlmemory
Register
Hi-Changesilin
l I l t 1 1 1 W modO 0 1 rim
data
data If w-l
data If sw..Ql
CONTROL TRANSfER
CALL
~
ClII:
Dlrecl Within segment
11101000
Indirect Within segment
1 1 1 1 1 1 1 1 mod 010 rim
Dlreclmtersegment
0'1001 reg
1,111011 w ImodO 11 rim
Indlfectlntersegment
10011 010
dlsp·low
oflset-Iow
offsel-hlgh
seg-Iow
seg·hlgh
(11 1 1 , 1 1 1 [mOd 0 t 1
continued
12·94
SDK·8S
Mnemonic and
Description
JMP
=
I
Uncondttlon.t Jump:
78543210
16543210
Dllecl wl\tlln segment
\1 1 101001 \
dlsp-Iow
OHee1 wl!Illfl segment-short
111101011\
dlsp
Indirect within segment
, 1 1 1 1 1 1 1 1 Imod 100
Dlfectlntersegment
11
Indirect mlersegment
RET
=
Mnemonic and
Description
Instruction Code
1 101010
I
I
78543210
rim
offset-high
seg-Iow
sll9-I\'gh
Instruction Code
78&43210
dISp-hlgh!
o!!set-Iow
I
78543210
JNS-Jump on not Sign
1011110011
LOOP loop ex times
lOOPZllOOPE=loop whllelero/equal
lOOPIIZllOOPIIE~loop .... hile not
zero/eQual
JCIl-Jump on CX lero
1111000101
111100001
I
R.lurn trom CAll·
dlsp
11100011
dlsp
I.T Interrupt
\11000011\
FI,"c,c!oc!o""o""o":"'""o+1~-d;:c.,CC';-C'OW:-'----:-d'C:"-;:.hC:;ILJc-1
Within seg adding Immed to SP
lolersegment
\1 100101 1 \
Inlersegment adding Immediate 10 SP
J£/JZoJumpon equal/zero
JL/JNIlE'Jump on less/not greater
or equal
JLf/JIIG-Jump on less or equal/not
greater
JI/JNAE=Jump on belo ..... /not above
or equal
1F.,",,",0",0~,"'0':""'0!-I~-CdC7",CCIC-ow~'------CCd';-C"C-h,"gh-'1
01110100
dlsp
01111100
dlsp
1011111101
dlsp
!011100101
dlsp
I
I
I
Typespecilled
111001101
Type 3
1110011001
111m-Interrupt on overllol'<
Q 1 00 111
IRET ~ Inler ru pI return
111001111
I
PROCESSOR CONTROL
101110110!
ClC-Clearcarry
JP/JPE=Jumpon parlty/parlly
101111010!
CMC-Complementcarry
~ID
STC-Set carry
111111001 )
ClO-Clear direction
111111100 )
e~en
o~erl!o.....
1F.0~,~,~,~0~0~0~0,p1~~d~'''~~1
1F.0~,~,;",:.,~0;;0;;0,p1~~d~"p~~1
JS-Jump on sign
JIIE/JIIZ-Jump on not equat/not zero F.0~'~';"~o,:.';;o.;.,'~~~~~
JIIl/JGE~1ue~~a~n nolless/greater
0 1 I I 1 1 0 1
1F,;0":",":",":",~,~,~,'C,+1~~~9
STj-Sel Interrupt
JIIB/JAE~~u~~a~n not below/above
1F.0~'~'~'~0~0,:.'':''+1~~;;b9
HlT-Halt
JIIBE/JA;~~~I~aob~~~t
IF,;0":"'~''':"'~0";C''C''C'+1~~~9
IF,;0",'~'~'";C'~0";C''C'+1~~~9
below or
111111000 )
STD-Set direction
CLI-Clearlnterrupl
not less or equal/
JIIP/JPO-Jump on not par/par odd
JIIO-Jump on not overflow
type
01
JI£jJIIA~~~~goo~~ belo ..... or equal!
JllLE/JGg1~~~rOn
dlsp
11100000
111111111 tmod 101
Wlthlnsegmenl
JO-Jump on
dlsp
dlsp
11111101
11111010
1111110111
)111101001
WAIT 'Wall
ESC~Escape
Ic:0--,'--,'--,'-".O-".o-".o-,-'J-I~--''''---"
(10 ex1ernal deVice)
lOCK-Buslockprellx
11 0011011 I
1110tlxxxlmodx~
111110000
I
Notes
Al '" 8-bit accumulator
AX '" 16-blt accumulator
ex '" Count register
OS '" Oata segment
ES " Extra segment
Abovelbelow refers to unstgned value
Greater'" more POSitive,
less'" less POSitive (more negative) Signed values
ild=l then "to" reg; if d""O then "from" reg
if w '" 1 then word instructIOn, If w '" 0 then byte instruction
=
=
If s w 01 then 16 bits of Immediate data form the operand
If s w 11 then an Immediate data byte IS sign extended to
form the 16-blt operand
If v=:O then "count" =: I, If v=:O then "count" In (el)
x =: don't care
If v=:O then "count" "" 1, If v = 1 then "count" In (Cll register
Z IS used for string primitives for comparison With ZF FLAG
SEGMENT OVERRIDE PREFIX
Qi~
reg 110
REG IS aSSigned accordmg to the follOWing table
if mod"" 11 then
If mod'" 00 then
if mod = 01 then
If mod'" 10 then
rIm IS treated as a REG field
DlSP '" 0·, dlsp-Iow and dlsp-hlgh are absent
DlSP = disp-Iow sign-extended to 16-bits, dlsp-hlgh IS absent
OISP = dlsp-high: dlsp-Iow
if rIm'" 000 then
if rim" 001 then
if rim" 010 then
if rIm"' 011 then
if rIm"" 100 then
if rIm" 101 then
if rim" 110 then
if rIm'" 111 then
OISP follows 2nd
EA '" (BX)
+
(51)
+
lfi.BIt Iw 11
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 SI
111 01
0
OISP
EA" IBXI • 1011 ·OISP
EA" IBPI • ISII • OISP
EA '" (BP) + (01) + OISP
EA '" (SI) + OISP
EA '" (01) + OISP
EA" IBPI • OISP'
EA '" (BX) + OlSP
byte of instruction (before data If reqUired)
=
110 then EA '" dlsp-hlgh- dlsp-Iow
0
SegmBnt
00
01
10
11
ES
CS
SS
OS
InstructIOns which reference the flag register file as a 16-bll object use the symbol FLAGS to
represent the file
FLAGS
·except if mod'" 00 and rIm
i>BIt (W 01
000 Al
001 Cl
010 Ol
011 Bl
100 AH
101 CH
110 OH
111 BH
0
X X X X10FI (OFIIiFI (TFIISFlllFI XIAFIX (PFI XICFI
Mnemonics
(c)
Intel, 1978
Table 4. 8086 Instruction Set Summary
SPECIFICATIONS
Addressing
Central Processor
ROM - FEOOO-FFFFF
RAM 0-7FF (800-FFF available with additional
2142's)
CPU -
8086-4
Note
Note
May be operated at 2.5 MHz or 5 MHz, jumper selectable, for use with
8086.
The wire-wrap area of the SDK·86 PC board may be used for additional
custom memory expansion.
Input/Output
Memory
Parallel - 48 lines (two 8255A's)
Serial - RS232 or current loop {8251A)
Baud Rate - selectable from 110 to 4800 baud
ROM - 8K bytes 2316/2716
RAM - 2K bytes (expandable to 4K bytes) 2142
12-95
SDK·8S
Interfaces
Electrical Characteristics
Bus - All signals TTL compatible
Parallel I/O - All signals TTL compatible
Serial I/O - 20 mA current loop TTY or RS232
DC Power Requirement
(Power supply not included in kit)
Note
The user has access to all bus signals which enable him to design cus·
tom system expansions into the kit's wire-wrap area.
Voltage
Interrupts (256 vectored)
Maskable
Non·maskable
TRAP
Current
VCC5V ±5%
3.5A
VTTY -12V ± 10%
0.3A
(VTTY required only if teletype is connected)
Environmental Characteristics
Operating Temperature - 0-50·C
DMA
Hold Request - Jumper selectable. TTL compatible
input.
Software
System Monitor - Preprogrammed 2716 or 2316 ROMs
Addresses - FEOOO-FFFFF
Monitor 1/0 - Keyboard/display or TTY or CRT (serial
110)
Physical Characteristics
Width - 13.5 in. (34.3 cm)
Height - 12 in. (30.5 cm)
Depth - 1.75 in. (4.45 cm)
Weight - approx. 24 oz. (3.3 kg)
Reference Manuals
9800697A SDK·B6 MCS·B6 System Design Kit
Assembly Manual
9800722 - MCS·B6 User's Manual
9800640A - BOB6 Assembly Language Programming
Manual
BOB6 Assembly Language Reference Card
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
Description
SDK·B6
MCS·B6 system design kit
12·96
inter
SDK-C86
MCS-86'· SYSTEM DESIGN KIT
SOFTWARE AND CABLE INTERFACE TO
INTELLEC@ DEVELOPMENT SYSTEM
• Provides the Software and Hardware
Communications Link Between an
Intellec® Development System and the
SDK-86
• Enhances and Extends the Power and
Usefulness of the SDK-86
• Intellec® System Files can be Accessed
and Down loaded to the SDK-8S
Resident Memory
• Allows the SDK-86 to Become an
Execution Vehicle for ISIS-II
Developed 8086 Object Code Using
the MDS-311 Software Cross
Development Package
• Data in SDK-86 Memory can be
Uploaded and Saved in Intellec®
System Files
• All SDK-86 Serial Port Mode
Commands Become Available at
Console of the Intellec® System
The SDK-C86 product provides the software and hardware link for using the SDK-86 monitor in conjunction with an
Intellec® Development System while adding features of data transfer between SDK-86 memory and Intellec® System files.
The user may enter programs and data into the SDK-86 and then save them on a diskette. Also, programs and data may be
created on the Inteliec® System using the MDS-311 cross development software package, then loaded into the SDK-86 for
testing and checkout. This provides a real time execution environment of the SDK-86 as a peripheral to the Inteliec@
System.
12-97
SDK-C86
HARDWARE
There are two serial ports on the Intellec® System back
panel, TTY and CRT. Assuming that one of the ports is
used for the Intellec® console, the SDK-C86 cable can
plug into the unused port. The SDK-86 is jumper
selectable to accept either the CRT (RS232) orTTY (20mA
current loop) signals.
The edge connector on the SDK-86 has the MUL TIBUS··
form factor. No signals are connected to the fingers
except the power supply traces. Therefore, the SDK-86
can plug directly into the Intellec® motherboard to obtain
power while using the SDK-C86 cable as the communication link.
SOFTWARE
Two programs must be invoked to operate in the SDK-86
slave mode. One program runs on the SDK-86, and
another runs in any ISIS-II environment that includes a
diskette drive.
The serial 1/0 monitor is installed on the SDK-86 and
operates as though it was talking to a terminal. The
software in the Intellec® allows the Intellec®, with a
console device, to behave as if it were a terminal to the
SDK-86.
The SDK-C86 software program in the I ntellec reads the
console input device, then passes the character to the
SDK-86 through the serial port. It also receives the
characters from the SDK-86 and displays them at the
console output device. Besides the basic transfer
function, this program also recognizes and performs the
Upload and Download functions.
COMMAND MODES
• Transparent: In this mode, the SDK-C86 software
passes all characters through without any processing.
All the commands of the SDK-86 monitor (except paper
tape commands) are available and will function in
exactly the same manner as if the terminal were
attached directly to the serial port of the SDK-86.
• Upload/Download: In this mode the SDK-C86 software,
in the Intellec®, recognizes the mnemonic for Upload or
Download from the terminal. It "translates" the
Download command to an R (Read hexadecimal tape)
command and the Upload command to a W (Write
hexadecimal tape). The Rand W commands are then
passed on to the SDK-86 monitor. Using these paper
tape commands allows for a checksummed transfer of
data between the Intellec® and the SDK-86 memory.
COMMAND SUMMARY
• Reset - starts the SDK-86 monitor.
• Execute with Breakpoint (G) Allows you to execute a user program and cause it to halt at a predetermined program step - useful for debugging.
• Single Step (N) - allows you toexecute a user program
one instruction at a time - useful for debugging.
• Substitute Memory (S, SW) - allows you to examine
and modify memory locations in byte or word mode.
• Examine Register (X) - allows you to examine and
modify the 8086's register contents.
• Block Move (M) - allows you to relocate program and
data portions in memory.
• Input OJ Output (I, IW, 0, OW) - allowsdirectcontrol of
the SDK-86's 110 facilities in byte or word mode.
• Display Memory (D) - allows you to print or display
large blocks of memory information in HEX format.
• Load (L) - allows you to load hex format object files
into SDK-86 memory from an Intellec.
• Transfer (T) - allows you to save contents of SDK-86
memory in a hex format object file in the Intellec.
SERIAL~
PORTS
CABLE
~
,........~========::::::====~..
INTELLEC®
DEVELOPMENT
SYSTEM
CRTOR TTY
[~}
SDK-S6
...m
SDK-86/1ntellec® Slave Mode Configuration
12-98
-
SERIAL
PORT
______~~
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2. A source listing of the program must be included.
This must be the output listing of a compile or assembly. All accepted programs must be capable of
compilation or assembly by Intel standard compilers or assemblers. No consideration will be given
to partial programs or duplication of existing programs.
3. A test program which assures the validity of the
contributed program must be included. This must
show the correct operation of the program.
4. A source paper tape or diskette of the contributed
program is required. This will be used for the reproduction of tapes for other members.
Complete the Submittal Form as follows: (please type or
print)
PROGRAM LIBRARY SERVICES
PAPER TAPES, DISKETTES OR SOURCE LISTINGS are
available for every program in Insite TM. Diskettes are
available on single or double density.
1. Processor (check appropriate box).
2. Program Title: Name and brief description of program function.
3. Function: Detailed description of operations performed by the program. Attach additional pages if
necessary.
MEMBERSHIP
Membership in InsiteTM is available on an annual basis.
Intel customers may become members through an accepted program contribution or membership fee. New
members should use the membership form on the back
of this data sheet.
4. Required Hardware:
For example: TTY or Ports 0 and 1
Interrupt Circuitry
I/O Interface
Machine line and configuration for
cross products
5. Required Software:
For example: TTY Driver
Floating Point Package
Support software required for cross
products
PROGRAM SUBMITTAL
Programs submitted for our review must follow the
guidelines listed below:
6. Input Parameters: Description of register values,
memory areas or values accepted from input ports.
1. Programs must be written in a standard Intel
Assembly Language or PUM-80. These languages
are documented in the following manuals:
a. 8008/MCS-8 Assembly Programming Manual #980198
b. 8080/8085 Assembly Language Programming
Manual #98-301C
c. 8080/8085 Floating-Point
User's Manual #98-4528
Arithmetic
7. Output Results: Values to be expected in registers,
memory areas or on output ports.
8. Program Details: (for resident products only)
a. Register modified
Library
b. RAM required (bytes)
c. ROM required (bytes)
d. PUM-80 Programming Manual #98-2688
d. Maximum subroutine nesting level
e. MCS-48 and UPI-41 Assembly Language Manual
#98-255C
9. Assembler/Compiler Used:
f. FORTRAN-80 Programming Manual #98-481A
g. 8086 Assembly Language Reference Manual #98640A
h. PUM-86 Programming Manual #98-466A
For example: PUM-80
Intellec® MDS Macro Assembler
FORTRAN-80
10. Programmer, Company and Address_
12-100
INSITETM USER'S PROGRAM LIBRARY
INSITETM USER'S LIBRARY PARTIAL INDEX
3-Byle Positive Fractional Multiply
5 Leyel (BARDOr) to 8 Level (ASCii) Paper Tape
Conversion
8·Bit Multiply and Divide
8·Blt Random Number Generator
12 x 12 Multiply
16-8il CAG for Polynomial X16+ X12+ X5+ 1
16·Bit Division - 16·Bil Result
16·Bit Division - 16-Bit Result
16·BII Multiply - 16-8il Result
16-BLt Multiply - 16-BII Result
16·Bil Multiply - 32-811 Result
16·Bit Random Number Generator
16-8il Square Root Routine
32-8il Binary to BCD Conversion, leading Zero
Blanking
32-8ij Divide Subroutine
2706 PROM Programmer for Intellee SIMOD 80
4040 Cross Assembler for Intel lee SIMOD 80 and
MDS-80Q
B008 Cross Assembler for BOSS·MACRO Definition - M800B.SRC
8008 Cross Inverse Assembler for HP 2100
8008 Disassembler
8008 MACRO Assembler Version 2.0
8008 MACRO Definition Set for Assembly on
PDp·ll
8048 BCD Multiply
8048-DIV - DiVision Routine
8048 - Seven Segment Display Interface Subroutines - SCAN
8048 TUNE GENERATOR
8080 CPU Exercise Routine
8080 Cross Assembler for Tektronix 4051
8080 Disassembler
8080 Disassembler
8080 Double Precision ARC Tangent
8080 Floating Point Ab
8080 Floating Point Extended Math Package
8080 Floating Point with BCD Conversion
Routine
8080 Idle Analyzer for Approxlmateng CPU
Utilization
8080 1/0 System Status Display
8080 Least Squares Quadratic Fitting Routine
8080 MACRO Assembler 4.1
8080 RAM Memory Test
8080 Symbol Table Dump
8085 Cross Assembler for the DEC PDP8 and
PDP11
9600 Initialize CRT and UART for Baud
Absorbance Calculation
AID Converter Routine
ADCCP Remainder Routine
Adaptive Game Program
Algebraic Compare Subroutine
Align Program - Intermediate Pass Between
PLMIPass 1 & 2
AnaloglDigital Polling Routene
AP29 "USING THE 8065 SERIAL 110 LINES"
APL Graphic Display on a 5 x 7 Dot Matrix
Approximating Routine
Arctan 2 Subroutine
ARRAY ADDRESSING SUBROUTINE AND
CALLING MACRO
ASCII Display
ASCii to EBCDIC and EBCDIC to ASCII Converters
ASCIl String to Intel Floating Point
Assembler Oriented Centronics 306 Une Printer
Handler and Error Only Assembler
Bandit Static Display
Banner Print and Punch
BASIC CPU State Vector Maintenance
Basic Digital Panel Meter Call
BASIC Interpreter
BASICIM Translator and
Interpreter
BCD to BIN ConverSion Routine
BCD tolfrom Binary Conversion
BCD Input and Direct Conversion to Binary
Routme
BCD Multiplication
BCD Sum for 8008
BCD Up/Down Counter
BIN to BCD Conversion Routme
Binary to BCD Subroutine
Binary to HEX Routine
Binary Loader for MDS
Binary Multiplication - 24-Bit
Binary Search
Binary Search Routine
Binary Tape Program
BINDECBIN - Binary to/from BCD
BINLB - 8080 System Loader
Bl0RIM
Blackjack
$BLPT
BOOT - Bootstrap Loading and Program Patch-
ong
Calculate a Calendar
Calendar Subroutine
Card Reader Driver, Hollenth to ASCII ConverSion
Character Interpreted Memory Dump
eLi
Clock Subroutine
Compare
COMPARE Files
Compare Object Code Tape with Memory
Control Data Output
Controller for Hewlett-Packard 9871A Printer
Conversion of Scientific to Easily Readable
Notation
Crap's
CRECH - CycliC Redundancy Check
Cross Assembler ASM08
Cross Assembler for NOVA 1200
Cross Assembler for NOVA 1220, IBM 360/40
and CDC 3000
Cross Assembler for PDP-1l
Cross Assembler for PDP-1l
Cross Assembler for Varian Data Machine
Cross Reference for PAseo PASCAL Programs
- XREF80
CRTBZ - GET
Cut and Paste Editor (PUM)
Cyclic Redundancy Character Generator
Cyclic Redundancy Check
Cyclic Redundancy Check for Data String of 2 16
Bytes
Data Array Move
Data General to InteUec MDS Diskette Trans·
port Package
Data 110 PROM Processor
"DATCON 81" Analog to Digital Conversion
Program
Decrement Hand L Regsiters
Delete Comments
Diagnostic 1003 - Memory Validity Check
Digital to Analog Conversion for Eight OutputS
Disable Hold - Screen Mode
Disassembler
Disk Dump Routine for ICOM F DOS-l1/MOD 80
Floppy DOS
Diskette Recovery Program, Recovery 1
Display
Double Precision Integer Arithmetic Package
Double Precision Multiply
Driver for Tektronix 4010 Grafic Screen
DTMHEX
Elementary Function Package
Enable Hold - Screen Mode
ERLIST
Examin
EXEC
Factorial of a Decirnal Number
Fast Floating Point Square Root Routine
FAST & SLOW
FDUMP
Field
Fixed and Floating POInt Arithmetic Routines
Fixed POint CHEBYSHEV Sine and Cosine for
PUM Users
Flag Processing Routine
Floating Point Conversion Routine
Floating Point Decimal and HEX Format Conversion
Floating Point Format Conversion Package
Floating Point Interpreter
Fioating Point Math Package
Floating Point Package for Intel 8008 and 8080
Microprocessors
Floating Point Procedures
Floating Point Square Root
Floating Point Utility Programs for Use with
FPALLIB
Fly Reader Driver
Format
12-101
Format Intel Data
Gambol
Game of Ufe
Gamma Function Subroutine
Generalized Stepper Motor Drive Program
GLANCE
GRAPH
Gray to Binary Conversion
Handler for Tally PTP
Hang
Hazeltine 2000 CRT Function Driver
Hewlett·Packard Calculator to MDS800 110 Control Program - HPIO
HEX Convert - Convert Intel HEX to Prolog
HEX File Converter
Hex to ASCII Conversion
HEX to Decimal Conversion
HEX Format Paper Tape Dump for SDK
HEX Tape Loader for SDK
High Speed Paper Tape Reader with Stepper
Motor Control
Histogram
18080 Cross Assembler for 1ntel 806018085
Microprocessors
IBM Selectric Input Program
IBM Selectric Output Program
ICE-80 Disassembler
I-Command - Insert Data in HEX Form from
TTY into RAM
Input/Output Commands for MDS
Insert Tab Characters for Spaces
Intel Format HEX Data File LoadlRead
Intellec 8 MOD 80 Monitor
Intellec 8/MOD 80 - Silent 700 Interface
Inteliec MDS Diagnostic Confidence Test Version 1.1
Intellec MDS Monitor VerSion 2.0
Intellec B Text Editor
Interfacing the MDS and HP 2644
Interrupt Driven Clock Routine
Interrupt Handler (Re-Entrant)
Interrupt Service Routine
INVERT Data in RAM
110 Routine for TI Silent 700 Terminal
110 Simulation MACROS
110 Test Program for SSC 80/20 - 10TEST
Join
Julian Data Routine
K, Program Trap and Dump Routine
Kalah
Keyboard Scanner
Kill the Rotating Bit
Lander
Lerr
Legible Paper Tape
Lewthwaite's Game
Linear System (Gauss Elimination) - LlSY
LISP INTERPRETER
List
List Device Program
List SCR
List 1 - High Speed List Propram for Inlellec 8
ListlPrintlType "List SAC" on Diskette
LLUChernack Basic Interpreter
LOAD
Log Base 2
LSORT
MACRO Assembler for DG NOVA
Main Routine DDUMP(Diskette DUMP Routines)
Mastermind
Mastermind 8080
"Mastermind 8080" for SSC BOI10
Match
Match Game
Maze
Maze
MBCo N1 x N2 Bytes Decimal Multiply Subroutine
MDS Back to Back Data Transfer
Memory Compare
Memory Diagnostic Program
Memory Dump
Memory Test for the 8080
Memory Test Program
~Scope 820 Test Instrument, iSBC 80/10 Diagnostic Program
MINITH-RMX Minimal Terminal Handler
Model 101 Centronics Printer Handler
Mon256 - 256-Syte PROM Monitor
INSITETM USER'S PROGRAM LIBRARY
INSITETM USER'S LIBRARY PARTIAL PROGRAM INDEX (Continued)
Monitor for iSeC 80/05 or 80104 - MON805
Monitor for iSaC 80110 or BO/10A - MON8l0
Monitor for iSeC 80/20 or 80120-4 -
RANDOM$BITS
React
Read and Interrupt Modifications for InleHec 81
MOD 80
ReadlWrite Routines for Interchange Tapes
Reader Test
Real Time Clock Service Routine
Real Time Executive
Real Time Monitor
MON820
Morse Code Generator
MSAVEIMLOAO Utilities for MOS-800 with DOS
MULJDIV Multi-Precision Pack for 8080
Natural Logarithm
N·Syte Binary Multlplicaiton and leading Zero
Blanking
Nim
Nlm
Non-Encoded Keyboard Subroutine
Nova Cross Assembler - Intel 8080
Numbers
Octal Code Conversion for PDp·11
Octal Debugging Program (COn for the Mes-eo
Computer
Octal PROM Programming
OCTHEX
Onlins, Upload, Download
Optimized Ultra Fast Floating Point Package
Output Message Generator
P2708 PROM Programming Routine
Page Break for Tektronix 4010 1/0 Graphics Terminal
Statement Counter
STEP
String Manipulation Package
Structured Assembler for 8080
Subroutine DMULT (Decimal Multiplication)
Subroutine Log - Common Logarithms
Subroutine SORT
Symbol Cross-Reference
Symbol Table
Symbol Table Dump for Intellec SlMOD '0
Symbol Table List Routine
Tabs
Tally - Use Tally 2200 Une Printer in Assembly
Stage of Programming
Tally R2050 HSPTR Driver
Tape Duplicator
Tape Labeler for MDS
Teleprocessing Buffer Routine
Terminal Editor
Terminet 300
Termlnel1200
Text Editor, Enhanced
Text Storage Program
Thermocouple linearization (Type J)
Thumbwheel
80/10 Test Program
Tlc-Tae-Toe
Tic-Tae·Toe - 3 Dimensional
Time Sharing Communications
TIMIT - Interrupt Driven Real Time Clock Routine
T.!. Silent 700 Interface - Inlellec MDS
T.1. Silent 700 SBC 80 Monitor Interface
TRACE - Program TracR and Debugger
Trace & Register Print Out
Trace Routine
TRACE Version 7.0
ny Binary Dump Routine
ny Binary Load Routine
TTY Diagnostic
Type
Type
Type K.T.C. Linearizer
Utility Macros for 8080
VDU Darts
Video Driver
Wipe
Word Game, The
WAM!N·RMX Minimal Terminal Output
RECOVA
Relative Jump Routine
Relocatable FMath and XMath, 8085 Floating
Point Package
AIABO
RMSTF - Integration Routine
RMXJ80·based Keyboard Input Handler Subroutine
Run 0
Sample Automatic Test Equipment
Save/Restore CPU State on an Interrupt
Communicator
80P Real Time Clock
SSC 80/10 8255 Test
SSC 80110 Interactfve Monitor
SSC 80110 Port 1/0 Exerciser
SBC 310 Floating Point System for Use with
sec
sse
Page Listing Program
Paper Tape Leader 1.0
Paper Tape AeformaUer for SOK
Pass - Parameter Passing Routine
PDP·11 Binary FHe to Intel HEX File Converter
POp·l1 Program Load to HEX, Dump, & Verify
PILOT·80 ISIS·II Version 2.0
PUM 80 Pass 3
PUM Floating Point Interface
PUM Histogram Procedure and Random Number Generator
Print
Print Program for G.E. Termlnet-1200 Printer
Print Out Source File on Floppy Disk
Print Text for SSC 80110
Program
Test
Load
PROM Programmer tor Intellec 8
Prompt Pong
Proportional Power Control Image Builder
Punch Binary Tape
Punch Test or lTV ReaderlPunch Test
Quicksort Procedures
RAM Check
RAM Test Program
Random Number Generator - RINGEN
sec
SBC 80120
SCAN
SCAN - 8048 - Seven Segment Display interface Subroutines
SOK-80 Keyboard Monitor
SDK-SO Paper Tape Punch Routine
SOK80 TRAP
SDK PROM Programmer
Sequential Pascal Compiler
Serial PROM Programmer
Sets Horizontal Tabs on Terminet
Shellsorting Routine
SinX, CosX Subroutine
Slot Machine
SMAL:Symbolic Microcontrolier Assembly
Language
SMPY16: 16-Sit 2'8 Complement Signed Multiplication
Snap Dump 8080
Software Stack Routines for 8008
Source Paper Tape to Magnetic Cassette
SQRTF - Calculates 8·BIt Root of 18-Bit Number
Stage2
insiteM'USER'S LIBRARY MEMBERSHIP FORM
I am interested in becoming a member of InsiteTM
Enclosed is
0 Check
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0 Program Submittal
NAME:
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Intel Corporation
User's Library 6-321
Microcomputer Systems
3065 Bowers Avenue
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95051
Ph. 408-987-8080
Intel International Corp. SA
User's library
Rue du Moulin a Papier 51
Boite 1
B-1160 Brussels, Belgium
Ph. 02-660-301.0
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User's Library
Flowerhill-Shinmachi, East Bldg.
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813-426-9267 (CS & Fin.)
'Please refer to Intel OEM Price List for membership fee.
12-102
inter
JASCOPE 820
MICROPROCESSOR SYSTEM CONSOLE
Gives complete control over microprocessor, including single step, run-withdisplay, or run-real-time capability
Executes instrument resident software
patch routines even when microcomputer system is ROM-based
Provides a 32-bit hardware breakpoint
with bit masking and a 256-word trace
memory
Is a stand-alone, self-contained, rugged
portable unit
Executes diagnostic routines from
jAScope 820 console overlay memory
Provides an interface to microcomputer
systems for troubleshooting system
problems
Monitors, displays, and alters register,
memory, and I/O values for system
under test
Human engineered with easy to read
g-segment hexadecimal displays and
extensive operator prompting
Designed to support many different
microprocessors
Has built-in, self-test operation
Intel's new ,..SCOPE 820 Microprocessor System Console provides equipment manufacturers with a portable microcomputer system deSigned to expedite troubleshooting and maintenance of other microcomputer systems. The unit
can control and examine system operations. Diagnostics can be automated by EPROM (erasable, programmable read
only memories) or ROMs into the socket at the upper left of the keyboard display panel. The ,..Scope 820 is a portable,
self-contained instrument designed to provide the control, monitoring, and interaction necessary to effectively and
quickly evaluate and debug 8·bit microcomputer·based systems in the lab, on the production line, or in the field. Con·
nection to the user's system is through a personality probe plugged into the microprocessor socket. Each personality
probe is unique to each microprocessor type. The instrument features many different operating and controi modes,
allowing the operator to carry out a number of functional checks on the microcomputer system under test (SUT).
Although the unit has been specifically deSigned to ease the task of microcomputer system checkout for the lab, production line, and field technician, it also provides the more powerful analytical capabilities necessary to troubleshoot
difficult problems by the more experienced, sophisticated user. Preprogrammed test routines resident in front panel
PROMs, dedicated high level commands keys, visual prompting, and simplified data entry sequences all ease the
checkout of microcomputer hardware. For more rigorous diagnostic tasks, the unit provides a 32·bit maskable hard·
ware breakpoint with optional course of action after a breakpoint match, a 256 x 32-bit trace memory, and a 128 x 8
overlay RAM that allows real-time entry of test routines via the ,..Scope 820 keyboard.
12-103
I-LSCOPE 820
FEATURES
Address Display/Select
CPU Control
A dedicated, 4·digit hexadecimal address display allows
the following address information to be displayed:
The instrument provides complete control over the
• The address of any memory location.
operation of the microprocessor in the system under
• The 110 port number of any I/O port.
test (SUT). The user CPU can be forced to halt, single
step, reset, run real time, or run with display. All of the
• The address of any overlay memory location.
• The address of the overlaymemory origin assignment.
above CPU commands may be issued without impacting
other operational parameters or diagnostic sequences
• The address at which the breakpoint is to occur.
previously established.
~. The address portion of the breakpoint mask.
• The address of the given trace record element.
Reset/Self·Test
An additional feature of the address display/select logic
is that once the operator has initiated a given memory,
trace, or 110 examination, it is possible to continue the
examination in a sequential fashion either in an ascend·
ing address value.
The reset and self·test features of the unit allow the
operator to either initialize the instrument to a known
state or quickly verify that the instrument is operating
correctly. When the console is reset, the breakpoint and
overlay memory are disabled, the display registers are
cleared and the specific examine modes are aborted.
When the operator initiates the self·test of the unit, a se·
quence of operations take place which serve to confirm
proper operation of a majority of the instrument.
Breakpoint Control
The hardware breakpoint of the instrument allows the
operator to alter the normal program flow of the SUT.
Breakpoint logic is implemented in hardware, thereby
eliminating any throughput degradation of the SUT. All
32 bits of the breakpoint condition word are maskable in
order to allow the breakpoint condition to be as specific
or as general as may be desired. The occurrence of a
breakpoint match can cause an unconditional halt,
incrementing of the pass counter, calling of a subrclu··-----------.....:.
tine, or the recording of a single cycle of trace data. All
of these options are selectable via the exam action key
prior to enabling the breakpoint.
Trace Memory
The console has a full 32·bit word trace memory that
records 256 cycles of SUT operation without causing
any delays. The trace memory provides information
about CPU operation just prior to a CPU halt or just prior
to the initiation of a panel freeze via the trace display
key. The operator can alternatively elect to have data
recorded on all SUT microprocessor cycles or only when
program execution of the SUT microprocessor gener·
ates a breakpoint match. Once the data is recorded,
sequential examination of the data may be accom·
plished simply by depressing the exam next or exam
last keys.
Overlay Memory
A unique feature of the unit is the ability to map its
memory onto the SUT memory space. Using the overlay
memory allows the operator to insert patch, exercise, or
diagnostic subroutines at any location or. point of execution in the SUT program. The subroutine may either be
entered via the front panel· hexadecimal keypad or via
the front panel's ROM/PROM socket. By using the unit's
overlay memory, the operator may quickly set up the
sur to execute special maintenance or troubleshooting
programs to permit rapid evaluation of system operation.
The address, data, and control variable entry into the
instrument is accomplished via the conveniently located
hexadecimal keypad. For selection of the information to
be displayed or modified the operator enters the hexa·
decimal value of the desired address, 110 port number,
or label assigned to each of the registers. Once this
entry is made, the operator can then elect to either con·
tinue data entry if modification is desired or press the
end execute key if examination only is desired. For all
data entry sequences potentially requiring multiple
value entry, the "Scope 820 Microprocessor System
Console provides operator prompting to indicate the
specific information expected.
12·104
IlSCOPE 820
Value Display/Select
The value displays provide clear and easy to use information. Together with the address display, they provide
simultaneous readout of trace vectors, breakpoint conditions and breakpoint mask values, memory contents,
and I/O port contents. In addition, the display allows
readout of all single and double byte register values, the
state of CPU pins and flags, and information regarding
the course of action following the occurrence of a breakpOint, as well as information regarding the breakpoint
pass count. The information displayed by the 4-digit
hexadecimal value readouts is selected via the hexadecimal keypad in conjunction with any of the instrument's eleven dedicated examine keys. Further, the
information is either displayed statically or is continually updated 10 times/sec if the unit is in the runwith-display mode.
durable as well as easy to use and understand. A plastic
overlay employing membrane switch contacts provides
long lasting durability as well as protection from
accidental spills. Audio and tactile feedback for the
membrane switches is provided for operator convenience. Ease of use of the front panel has been further
enhanced by human engineering with functional grouping of switches as well as LEDs that prompt the
operator during data entry sequences. Graphics have
also been added to reinforce the functional switch
groupings as well as data entry procedures.
PROM/ROM Socket
A front panel socket is provided for mounting 2K PROMs
or ROMs that serve as storage for preprogrammed test
subroutines. The actual useable program space of the
PROM/ROM is 1920 bytes. The remaining 128 bytes of
storage, shadowed by RAM, are used by the unit to identify up to 16 separate subroutines in the PROM/ROM
and to define the specific instrument states and conditions under which the subroutine will be called. Each of
the separate subroutines is uniquely enabled by the
subroutine select (SUBR SELECT) key and the hex
keypad.
_ _- - - - - - - Power Supply
The system console is complete with its own fully regulated DC power supply that provides all the DC power
required by the unit itself, as well as that which is
required by the associated microprocessor probe. The
supply is completely self-contained, including its own
AC on/off switch, line fuse, line filter, and power cord.
An additional feature of the power supply is that it has
been designed to permit line voltage selection in the
field to facilitate operation with a wide range of AC line
voltages and frequencies.
Breakpoint Action
Binary Data Display/Modification
All 8-bit values can be displayed in binary format on the
instrument. The binary display operates in parallel with
the hexadecimal display and is provided for those instances where operator recognition is enhanced by binary
presentation. The selection procedure for the binary
data display is identical to that for the hexadecimal
value display. Once the selection has been made, the
operator may alter the value by means of further hex
keypad entries or by changing the binary state of any of
the data bits via the eight binary data switches.
Front Panel
The front panel of the "Scope 820 Microprocessor System Console has been designed to be rugged and
Following the occurrence of a breakpoint match, the
operator has the flexibility to execute a number of different diagnostic operations. The selection of these
alternate courses of action is accomplished by pushing
the exam action key and then entering the assigned
value of the specific action desired via the hex keypad.
Further keypad entries specify the parametric value of
the action selected such as the number of breakpoint
pass counts or the start address of a subroutine call
following a breakpoint.
Probe Connection
The instrument is intended to work with many of the
microprocessors available today. This is accomplished
by standardized interface logic which transmits and
receives various address, data, and control signals
between the system console and the circuitry of the particular probe. The interconnect circuitry between the
instrument and probe has been designed to drive a
4-foot cable that permits convenient positioning of the
panel and the SUT. In addition, a board edge connector
has been provided for a personality ROM that provides
front panel definition and interpretation of specific control signals for different types of microprocessors. This
personality ROM is supplied with each probe kit.
12-105
f.tSCOPE 820
FUNCTIONAL DESCRIPTION
CPU Control
User selectable commands permit one of four possible
CPU operating modes:
Run Real Time - User's CPU runs at full speed set by
user clock. No wait states or cycle stealing are required.
Run with Display - User's CPU runs at full speed,
except that 10 times/sec the instrument halts user's
CPU temporarily to acquire display data. Worse case
throughput is 95% of real time operation.
Halt - User CPU halted at next opcode fetch. DMA
activity is permitted during halt.
Single Step halts.
of previously recorded data without halting the user
CPU.
Overlay Memory
The !-,Scope 820 Microprocessor System Console allows
memory read/writes of the user CPU in any assigned 1K
or 2K block to be made to the instrument's overlay
memory. For 1K block aSSignments, the first 128 bytes
reside in the instrument's RAM memory while the
remaining 896 bytes reside in the interchangeable front
panel ROM/EPROM (either Intel's 2716 EPROM or Intel's
2316E ROM). For 2K block aSSignments, again the first
128 bytes are from RAM and the remaining 1920 bytes
are from the front panel 2716/2316E.
User CPU executes one instruction then
Breakpoint Control
The breakpoint condition is set by a 32-bit word (16-bit
address, 8-bit data, 8-bit status). The breakpoint mask is
also set by a 32-bit word which is bit selectable. There
are three courses of action following a breakpoint
match:
1. Halt on first opcode fetch following breakpoint
match_
2. Halt on first opcode fetch following Nth breakpoint
match 1';;N';;256.
3. Execute subroutine beginning at first opcode fetch
following breakpoint match.
All breakpoint actions following a match are controlled
by the breakpoint enable/disable switch except for trace
recording and the sync trigger output. The sync output
is a negative true TTL output occurring whenever a
breakpoint match occurs.
Trace Memory
The trace memory is a 256-word memory with each word
consisting of 16 address bits, 8 data bits, and 8 status
bits. The memory is a circular buffer which records the
last 256 cycles (words) prior to a user CPU halt or display trace command. Trace data can be recorded on all
CPU cycles or only when breakpoint matches occur
(independent of breakpoint enable/disable status). In
addition, the operator may initiate a panel freeze to temporarily stop all trace data recording, and allow display
SPECIFICATIONS
Commands
Reset
Self test
CPU reset
Run real time
Run with display
Halt
Single step
Enable/disable breakpoint
Enable/disable overlay
Data Entry
All single and double byte items may be entered via the
front panel hexadecimal keypad. In addition, all single
byte items may be optionally entered via eight binary
input keys.
Data Display
Eight hexadecimal 0.5 in. LEDs are provided for the
simultaneous display of 4 bytes of information. The displays are physically separated into two groups. The first
group displays 2 bytes of address, while the second
group displays CPU data, status, single and double byte
register values, or single and double byte breakpoint
values. In addition, eight binary displays are used to provide quick recognition of single byte binary data
patterns.
Self Test
The necessary hardware and software have been incorporated into the instrument to facilitate the selfchecking of the majority of its operations. Included in
these self tests are:
o Bit tests of all breakpoint condition and mask latches.
o Bit tests of all RAM.
o Verifies checksum on all operating system ROMs.
o Clears trace memory and performs bit test on trace
RAM.
o Checks miscellaneous I/O ports and peripheral components
o Lights all front panel displays for user verification.
Enable trace all cycles
Enable trace at breakpoi nt
Examine/modify value
Single registers
Double registers
CPU states
Breakpoint pass count
Examine/modify memory
Examine/modify 110
Examine/modify overlay memory
Examine/modify next location
Examine/modify last location
12-106
",SCOPE 820
Examine/modify breakpoint condition
Examine/modify breakpoint mask
Examine/modify breakpoint action
Examine/modify overlay origin
Display trace data
Clear entry
Continue
End/execute
Subroutine select
Height (top closed) - 6-5/8 in. (168 mm)
Height (top removed) - 4-518 in. (117 mm)
Weight - 20 Ib (9.1 kg)
Electrical Characteristics
Voltage -100,120,220,240 -10%
Frequency - 48-63 Hz
+ 5%, 110V AC max
Environmental Characteristics
Connection
Four external connections to the "Scope 820 Microproc·
essor System Console are provided:
1.2m (4 ft), 50 conductor flat cable - for connection to
the microprocessor probe
20·pin board edge connector - for the probe personal·
ity PROM
24·pln zero force Insertion sockets - for overlay
EPROM/ROM
Recessed pin - for breakpoint sync output
Operating Temperature - O°C to 55°C (32°F to 130°F)
Storage Temperature - - 40°C to 75°C (- 40°F to
167°F)
Humidity - 95% RH, 15°C to 40°C (59°F to 104 OF) noncondensing
Accessories Supplied
Two keys
One fuse for 220/240V operation
One 2.3m (7.5 ft) power cord
Reference Manuals
Breakpoint
Pulse Width - 180 ns typ
Output High - 2.5V min, -1.2 rnA
Output Low - 0.5V max, 24.0 rnA
Physical Characteristics
Width - 18·7/8 in. (479 mm)
Length - 15·1/2 in. (394 mm)
9800526A (SUPPLIED)
Part Number
Description
Microprocessor system console
820
Operator's
Handbook
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
USC-820
"Scope
12·107
J.tSCOPE PROBE 8080A
Provides interconnection for 8o.8o.A
microprocessor·based systems to
/lScope 820. Microprocessor System
Console
Provides complete control over system
under test (SUn, yet causes minimal
interference with SUT operation
Comes complete with cable, buffer box,
personality ROM, and /lScope 820.
system console overlay
Fits securely in console carrying case
during transit
Provides complete protection for plug
pins during transit
Connects via 4·loot cable to /lScope 820.
console
Has user system interconnect cable
with integral ground plane for low noise
operation
Operates over broad range of environ·
mental conditions
The I'Scope Probe 8080A provides the I'Scope Microprocessor System Console with the ability to interact with 8080A
microcomputer-based systems_ The purpose of the probe is to interface the I'Scope 820 console to the CPU of the
system under test (SUT). All of the interface signals and the associated circuitry have been designed to be effectively
transparent to the SUT. CPU data, address, and clock lines are sensed by the probe 8080A, with only the CPU ground
lines being switched. In addition, all SUT loading and timing degradations have been minimized by specially designed
buffer circuitry. The mechanical design of the probe is compact, rugged, and allows proper operation of the probe and
the console over the full ambient range specified. The buffer circuitry and the ground plane design of the interconnect
cable provide low noise electrical signals while allowing the SUT to be four feet from the system console.
12-108
!-,SCOPE PROBE 8080A
SPECI FICATIONS
",Scope 820 Console Configuration
Several features of the console are directly determined
by the probe being used with it. The instrument features
that are determined by the aOaOA interface probe are:
Single Registers - A, B, C, D, E, H, L
Double Registers - BC, DE, HL, PC, SP
CPU States - Flags, CPU pins (SYNC, RESET, HLDA,
HOLD, READY, INT, INTE)
Trace/Breakpoint Word Size - 32 bits with 16 bits of
address, a bits of data, and a bits of CPU status.
User System Interconnect Cable
Width: 21/4 in. (57 mm)
Length: 16 in. (406 mm) flat cable
!-,Scope 820 Console Personality ROM PC Card
Height: 3f4 in. (19 mm)
Width: 21/.1 in. (57 mm)
Length: 3114 in. (83 mm)
Electrical Characteristics
All DC specifications are in addition to user system
parameters. All capacitance values include cables and
connectors.
Non-Intercepted Signals
",Scope 820 Console Interconnect
The probe interconnection to the !-,Scope a20 console is
accomplished via a 4-foot (1.2m) flat cable. 50-pin mating connectors plug into a board edge conector in the
power cord compartment of the instrument and into a
flat cable connector on the buffer box.
01,02
± 10!-,A max; 55 pF typ
+ 12V Supply
WAIT
- 0.25 mA max @ 0.45V; 30 !-'A max
5.25V; 49 pF typ
15!-,A max
35 pF typ (capacitance loading only)
@
Intercepted Signals
Outputs to User System
System Under Test (SUT) Interconnect
SYNC
Interconnection from the buffer box to the SUT is
accomplished with a 16-inch (406 mm) flat cable, complete with an integral ground plane, which is terminated
with a low profile 40-pin DIP connector. The DIP connector is inserted into the SUT 8080A socket and the 8080A
itself is plugged into the 40-pin socket provided on the
probe buffer box.
HOLDA,INTE,
DBIN, and Vim
Inputs from User System
INT, READY,
RESET
HOLD
Connections
Three external connections to the probe are provided:
50-pin flat cable connector on buffer box
40-pin zero insertion socket for the 8080A
40-pin low profile replaceable IC DIP connector for connection to SUT
Accessories Supplied
One !-,Scope 820 system console overlay
One personality ROM
One hardware reference manual
Probe Buffer Box
Height: 0.75 in. (19 mm)
Length: 7.25 in. (184 mm)
Width: 3.75 in. (95 mm)
Environmental Characteristics
Operating Temperature - O°C to 55'C (32°F to 130°F)
Storage Temperature - - 40 'C to 75 'C (- 40 OF to
167'F)
Humidity - 95% RH, 15'C to 40°C (59°F to 104 'F) noncondensing
Reference Manuals
!-,Scope 820 Operator's Manual (SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number Description
PRB-80
40!-,A max @ 2.7V; - 0.72 mA max @
O.4V; 50 pF typ
60!-,A max @ 2.7V; -1.08 mA max @
O.4V; 50 pF typ
Power Requirements - Power supplied by !-,Scope 820
Microprocessor System Console.
9800526 -
Physical Characteristics
20 mA min @ 0.5V; -1 mA min @
2.7V; 40 pF typ
4 mA min @ 0.4V; - 0.2 mA min @
2.7V; 40 pF typ
a080A interface probe
12-109
Jl SCOPE™ PROBE 8085
Provides interconnection for both 8085 and 8085A
Microprocessor-based Systems to the /lScope™
Microprocessor System Console
Operates over a broad range of environmental
conditions
Comes complete with cable, buffer box, personality
ROM, and /lScope system console overlay
Provides complete control over the system under
test, yet causes minimal interference with system
under test operation
Has user system interconnect cable with integral
ground plane for low noise operation
Fits securely in the console carrying case during
transit
Increases diagnostic capability via
positioned external inputs
Provides complete protection for plug pins during
transit
four
user
The probe 8085 provides the I'Scope Console with the ability to interact with 8085 and 8085A Microcomputer-based
systems. The purpose of the probe is to interface the I'Scope Console to the CPU of the system under test (SUT). All ofthe
interface signals and the associated circuitry have been designed to be effectively transparent to the SUT. CPU data,
address, and clock lines are sensed by the probe 8085, with only the CPU control lines being switched. In addition, all SUT
loading and timing degradations have been minimized by specially designed buffer circuitry.
The mechanical design of the probe is compact, rugged, and allows proper operation of the probe and the console overthe
full ambient range specified. The buffer circuitry and the ground plane design of the interconnect cable provide low noise
electrical signals while allowing the SUT to be 4 feet from the system console.
The probe can be reconfigured to test either 8085 or 8085A microprocessor-based systems. The user can operate the
microprocessor from either the system under test crystal or one adjacent to the probe 8085 CPU socket. User control of the
probe interaction with CPU control signals insures maximum compatibility with the system under test. Test and diagnostic
capability is increased by integrating four external inputs into the probe 8085.
12·110
INTA
GENERAL
I'SCOPE CONSOLE INTERCONNECT
The probe interconnection to the I'Scope Console is
accomplished via a 1.2m (4 ft.) flat cable. 50-pin mating
connectors plug into a board edge connector in the power
cord compartment of the instrument and into a flat cable
connector on the buffer box.
21 mA max @ 0.5 volt; -3.6 mA max@
2.4 volt
6 mA max @ 0.5 volt; -350 I'A max @
HlDA
2.7 volt
All Output Signals have capacitance of 20pF typical.
Inputs from user system:
1
RESET IN,
-O.S mA @ O.4V; 40 ,..A max @ 2.7V;
READY, HOLD,
RST 6.5, RST 5.5, 20 pF typical
INTR, TRAP
-O.SS mA @ O.4V; -0.25 mA max @
RST 7.5
2.7V; 20 pF typical
SYSTEM UNDER TEST (SUT) INTERCONNECT
Interconnection from the buffer box to the SUT is
accomplished with a 200mm (S in.) flat cable, complete
with an integral ground plane, which is terminated with a
low profile 40-pin DIP connector. The DIP connector is
inserted into the SUT SOS5 socket and the SOS5 itself is
plugged into the 40-pin socket provided on the probe
buffer box.
,..SCOPE CONSOLE CONFIGURATION
Several features of the I'Scope Console are directly determined by the probe being used with it. The features that
are determined by the SOS5 interface probe are:
• Single Registers: A, B, C, 0, E, H, L
• Double Registers: BC, DE, Hl, PC, SP
• CPU States: Flags, CPU pins, Interrupt Masks, and
Interrupt States
• TracelBreakpoint Word Size: 32 bits with 16 bits of
address, S bits of data and S bits of CPU status
• 4 external inputs included in the S bits of CPU status for
examining, recording in trace memory. and transferring control
External I n puts:
XIO, X11, X12, XI3 -0.25 mA max @ 0.45V; 10 I'A max @
5.25V; 2.4V min Input High Voltage;
0.S5V max Input Low Voltage
CONNECTIONS
Three external connections to the probe are provided:
• 50-pin flat cable connector on buffer box
• 40-pin zero insertion force socket for the SOS5 SUT
CPU
• 40-pin low profile replaceable IC DIP connector for
connection to SUT
CHARACTERISTICS
PHYSICAL CHARACTERISTICS
Probe Buffer Box:
Height:
length:
Width:
ELECTRICAL SPECIFICATIONS
22mm (7/S in.)
20Smm (S-1/4 in.)
116mm (4-5/S in.)
All DC specifications are in addition to user system
parameters. All capacitance values include cables and
connectors.
User System Interconnect Cable:
Non-Intercepted Signals
I'Scope Console Personality ROM PC Card:
x1, x2, reset out
16pF typical
ADo-AD7, As-A15
-0.25 mA max @ 0.45V; 10 I'A max
@ 5.25V; 26 pF typical
SID
40 ,..A max @ 2.7V; -0.6 mA max
@ 0.4V; 20 pF typical
SOD
20 I'A max @ 2.7V; -0.4 mA max @
O.4V; 20 pF typical
Intercepted Signals
Output to user system:
Width:
Length:
Height
Width:
length:
57mm (2-1/4 in.)
200mm (S in.) flat cable
19mm (3/4 in.)
57mm (2-1/4 in.)
S6mm (3-1/4 in.)
POWER REQUIREMENTS
Power supplied by I'Scope Microprocessor System
Console.
ENVIRONMENTAL CONDITIONS
Operating Temperature: 0° to 50°C (32° to 122°F)
-40° to 75°C (-40° to 167"F)
Storage Temperature:
Humidity:
95% RH, 15° to 40°C (59° to
104° F) noncondensing
ALE
19 mA max @ 0.5 volt; -900 I'A max@
2.7 volt
ClK
2 mA max @ 0.64 volt; -400 I'A max @
2.6 volt
ACCESSORIES SUPPLIED
SSO, SSI
S mA max @ 0.5 volt; -400 I'A max @
2.7 volt
One Personality ROM
RD, WR, 101M
24 mA max @ 0.5 volt; -2.6 mA max @
2.4 volt
One Probe SOS5 overlay for the I'Scope System Console
One Operator's Manual
Four Test Probes for the External Inputs
ORDERING INFORMATION
Part Number
Description
PRB-S5
SOS5 Interface Probe
12-111
MICROCOMPUTER TRAINING PROGRAMS
INTRODUCTION
Intel provides complete training for all its system related products. Courses are given regularly at Intel's training
centers located in Santa Clara, California; Boston, Massachusetts; and Chicago, Illinois. These training centers are
staffed by highly trained and experienced instructors. This section describes the overall program for microcomputer
training and provides outlines for the following courses offered by Intel.
TABLE OF CONTENTS
Microcomputer Training Programs ........................................................................... 14·3
INTRODUCTORY LEVEL
Introduction to Microcomputers ............................................... '" ......................... 14·4
Microcomputer Concepts (2 days) ......................................................................... 14·5
Development System Operations (3 days) ................................... " ............................. 14·5
INTERMEDIATE LEVEL
MCS·80/85 System ............................................ , ................................. '" ....... 14·6
PLlM·80 Language/Software Design .............................. " ....................................... 14·7
MCS·86 System .......................................................................................... 14·8
PLlM·86 Language/Software Design .... , '" .. , ............................................................ 14·9
MCS·48 System .......................................................................................... 14·10
ADVANCED LEVEL
RMX/80 System .......................................................................................... 14·11
Advanced MCS·86 Assembly Language .................................................................... 14·12
iSBC Design Project. ..................................................................................... 14·12
12·112
intel~
MICROCOMPUTER TRAINING PROGRAMS
Courses presented at training centers
and customer facilities
On-site courses tuned to customer
requirements
System demonstration
Training center locations
Boston
Chicago
Santa Clara
Hands-on laboratory sessions reinforce
lecture
Training center classes limited to 15
attendees
Scheduled on a continuing basis
throughout the year
Intellec microcomputer development
systems with in-circuit emulators used
in laboratory
Evening workshops
Microcomputers are being used in hundreds of applications from simple controllers to complex data processing
systems. To enable users to bring microcomputers into their applications, Intel offers a selection of workshops
designed to provide users with the tools for making optimum use of Intel microcomputers in system development.
12·113
MICROCOMPUTER TRAINING PROGRAMS
INTRODUCTION TO MICROCOMPUTERS
This workshop offers five days of lectures, questions and answers, practical learning, and hands·on training with your
own microcomputer. You'll learn the fundamentals and general uses of microprocessors, and the basics of
microcomputer·based design. The best learning will come from using and programming an operating SDK·85 System
Design Kit (described below). When the training session is completed, an SDK·85 kit is yours to keep.
Attendees: One who has limited programming and design experience, and does not need to learn about development
systems. A background in electronics is helpful but not necessary. (Maximum attendance is 20.)
SPECIAL OFFER!
Day 1
Introduction to Microcomputers
Computer Ogranization
Instruction Execution
Lab-Using Microcomputers
Day 2
Elementary Programming
Microcomputer Interfacing
Lab-Audio Oscillator Using
Digital Techniques
Day 3
Computer Arithmetic
Conditional Jumps
Stacks and Subroutines
Push/Pop
Lab-Using Monitor Routine
Day 4
Interrupts
Computer Kit Hardware
Memory Systems
Decimal Arithmetic
Lab-A Digital Clock
Day 5
Introduction to
Single Chip Microcomputers
Introduction to High
Level Langnuages
Introduction to 16·8it
Microcomputers
Survey of Programming Aids
Included in the price of the course is
an SDK·85 kit which includes:
3 MHz CPU (enhanced 8080)
Keyboard-24 keys
Display-6 digits
Monitor ROM 2048 bytes
RAM Memory 256 bytes
38110 lines
Teletype interface
Complete documentation
Table 1. Introduction to Microcomputers Course Outline
12·114
MICROCOMPUTER TRAINING PROGRAMS
Microcomputer Concepts Workshop
The student will learn microcomputer terminology, run a microcomputer program, and gain insight in the development
process and selecting the most appropriate microcomputer for an application.
Attendees: Project leaders, managers, administrative staff, or non·technical personnel who need a better understanding
of microcomputer fundamental concepts.
Day 2
Review
Single Chip Design Example
iSBC Design Example
Hardware/Software Tradeoffs
Day 1
Introduction
Terminology
SDK·85- Microcomputer Experiment
iSBC Demonstration
Development System Laboratory
Table 2. Microcomputer Concepts Workshop Course Outline
Development System Operations Workshop
This lab-intensive workshop teaches the student how to operate the Intellec Microcomputer Development System and
the ISIS (Intel Systems Implementation Supervisor) disk operating system. Laboratory operations include editing data
files, assembling and compiling programs, using relocation and linkage facilities, and identifying the correct documentation. This is not a programming course.
Attendees: A programmer who will be using the Intellec MOS. In addition, the technician, programmer-aid, or clerk who
needs to operate the Intellec MDS can benefit from this course.
Day 3
Review
Link/Locate
Diagnostic Programs
BASIC·80
Identify Manuals
Day 1
Introduction
System Installation,
Interconnections, Power·Up
Utility Commands-COPY,
DELETE, RENAME,
DIR, ATTRIB
Day 2
Review
Edit-Build and Modify a File
Compile
Assemble
Table 3. Development System Operations Workshop Course Outline
12-115
MICROCOMPUTER TRAINING PROGRAMS
COURSE DESCRIPTIONS
MeS·80/85 System Workshop
puter Development System and an in-circuit emulator.
The course outline for this workshop is presented in
Table 4.
This workshop will prepare the student to design and
develop a system using Intel 8080/8085 microprocessors by means of lectures, demonstrations, and laboratory "hands-on" experience with the Intellec Microcom-
Prerequisites: A knowledge of binary and hexadecimal
number systems and basic logic functions is recommended.
8085 Timing
a. Ready/Wait
b. DMA/Hold
8085 Interrupts
a. RST 5.5, 6.5, 7.5
b. Trap
c. RIM, SIM
8080 vs. 8085
a. 8080 Chip Set
1. 8228/8238 System Controller
2. 8224 Clock Generator
b. 8080 Bus Structure
c. 8080 Instruction Timing
Memory Interfacing
a. RAM/ROM/PROM Address
Decoding
b. 8708 PROM/8185 RAM
Laboratory
a. Program Design Using
Development System
b. Program DEBUG Under Disk
Operating System
Day 1
Introduction
a. Microprocessor System
,. Function
2. Organization
3. Programming
b. Central Processor Overview
1. Functional Sections
2. Programming Model
3. Execution Sequence
Assembly Language Instructions
a. Input/Output
b. Register/Memory Reference
c. Arithmetic, Logical. Rotates
Input/Output Techniques
a. Programmed I/O
b. I nterrupt I/O
c. Direct Memory Access
Programmed Input/Output
a. Status Request
b. Command
c. Data Transfer
Deyelopment System
a. Function
b. System Monitor
c. Disk Operating System
Debugging With the System Monitor
a. Break Points
b. Examine Registers
Laboratory
a. Using the System Monitor
b. Program Instruction Sequences
c. Debugging and Break Points
Day 4
8085 CPU Set
a. 8085 Bus Structure
b. 8355/8755 ROM/EPROM
and I/O
c. 8155 RAM/Timer and I/O
I/O Design
a. Memory-mapped
b. 8255 Parallel Interface
c. 8251 Serial Interface
In-Circuit Emulator
a. Prototype Development
b. Resource Sharing
c. Mapping Commands
d. Utility Commands
e. Debug Commands
f. Emulation Syntax
Laboratory
a. Use of the In-Circuit
Emulator for System
Debugging
Day 2
Basic CPU Timing
a. Instruction Fetch
b. Bus Structure
c. Read/Write Timing
Subroutines
a. Invocation
b. Stack Memory
c. Parameters
Interrupt System
a. Description
b. RST Instruction
c. Service Subroutines
Disk Operating System Modules
a. Macro Assembler
b. Text Editor
c. File Utility Commands
Laboratory
a. Using the Disk Operating System
b. Program Assembly and Execution
Day 3
Programming Techniques
a. Branch Tables
b. Direct Load/Store Instructions
c. Special Purpose Instructions
Day 5
Relocation and Linkage
a. ISIS-II LINK and LOCATE
Commands
b. Relocatable Libraries
c. Parameter Passing
d. System Design
Macros
Single Board Computer.
a. Use as a System
Component
b. Parallel I/O Options
c. Serial I/O Options
d. Interrupt System
e. Family Boards
Table 4. MCS-BO/aS System Workshop Course Outline
12-116
MICROCOMPUTER TRAINING PROGRAMS
PLlM·80 Language/Software Design
Workshop
Development System and an in·circuit emulator. The
course outline for this workshop is presented in Table 5.
This workshop will prepare the student for designing,
developing, and debugging modular PUM·80 programs,
by means of lectures, demonstrations, and laboratory
"hands-on" experience with the Intellec Microcomputer
Prerequisites: A knowledge of binary and hexadecimal
number systems and basic logic functions is required.
To attain maximum benefit from course presentation,
some background in logic design and computer programming is recommended.
Day 1
Introduction
a. Preview of Course
b. Overview of PUM, Linking and
Relocation
c. Why use a High Level Language
Definitions
Symbols, Identifiers, Reserved
Words, Comments, Data Elements,
Expressions, Statements,
Declarations
Data Elements
Variables, Subscripted Variables,
Data Type, Constants
Operators, Operations and Priorities
Arithmetic and Boolean
Evaluating Expressions
Statements
Redefine, Basic, Conditional
Assignment
a. Implement a Given Algorithm in
PLiM
Day 2
1515·11 Disc Operating System
a. Components of System
ISIS· II File Structure
a. System Files
b. User Files
c. Device Files
d. Directory and File Attributes
1515·11 Commands
a. CUSPS-Commonly Used
System Programs
b. Directory and Attribute
Commands
c. Rename and Delete Commands
d. Creating System and
User Discs
1515·11 Editor
a. Definition 01 Terminology
b. Invoking the Editor
c. Editor Commands
d. Editing Existing Files
1515·11 PL/M 80 Compiler
a. Invoking PUM
b. Compiler Options
1515·11 Locate
a. Invoking Locate
Laboratory
a. Introduction to ISIS·II Disc
Operating System
b. Creating a PUM Source File
c. Compiling a PLIM Program
d. Locating and Executing a PUM
Program
c. Program Construction
Data References
a. Based Variables
b. Variable Equivalencing
Blocks
a. Concept and Use
b. Scope of Declarations
Predeclared Procedures
a. TIME, MOVE, LENGTH, LAST and
SIZE Procedures
b. Type Transfers
c. Shifts and Rotates
The Memory Array and STACKPTR
variables
Laboratory
a. Compile and Locate Program
b. Execute Program
Day 4
Review
Modular Implementation
a. Compilation Modules
b. Modular Programming
ISIS·II Link
a. Invoking Link
b. Link Options
c. Assembly Object Modules
In·Circuit Emulator
a. Definition
b. System Overview
1. Memory and 110 Mapping
2. BreakpOint Capability
3. Dynamic Tracing
4. Control Block
In·Circuit Emulator Software Driver
a. Modes
b. Commands
System Debugging Examples
System Demonstration
Laboratory
a. Locate
b. Load and Emulate Using
In·Circuit Emulator
Day 5
Review
Interrupt Procedures
Reentrant Procedures
1515·11 Librarian
a. Creating a Library
b. Managing a Library
1. Adding Modules
2. Deleting Modules
1515·11 System Interfaces
a. System Library
Discussion of Selected Programs
Laboratory
a. Create a Library
b. Link Object to a Library
Day 3
Review
Procedures
a. Declaration
b. Invocation
Table 5. PL/M·80 Language/Software Design Workshop Course Outline
12·117
MICROCOMPUTER TRAINING PROGRAMS
MeS·S6 System Workshop
ence with the SDK-86 and the Intellec Microcomputer
Development System. The course outline for this workshop is presented in Table 6.
This workshop will prepare the student to develop assembly language programs and design systems based
on the Intel 8086 microprocessor through the use of lecture, demonstration, and laboratory "hands-on" experi-
Prerequisites: The student has programmed a computer in assembly language and, preferably, is familiar
with the 8080/8085 microprocessor.
Day 1
8259A - Priority Interrupt Control Unit
Development System
a. ISIS
b. Editor
c. Demonstration
Introduction
a. Microcomputer system
1. Function
2. Memory organization
3. Interfacing
b. Central processor overview
I. Programming
2. Instruction format
Laboratory
a. Using the development system
Day4
Review
Programming for Large Systems
a. Segmentation registers
b. Assembler
c. Linkage
d. Locate
Assembly Language Instruction
a. Register and data operations
I. 8·bit
2. 16·bit
b. I/O ooerations
System Design Kit (SDK·86)
a. Demonstration
b. Debugging
Laboratory
a. Assembler programming techniques
Programming
a. Arithmetic
b. String operators
Laboratory
a. Using the SDK·86
Day 2
Day 5
Review
CPU Architecture
a. Addressing modes
CPU Timing
a. Read cycle
b. Memory access time
c. Write cycle
Procedures
a. Invocation
b. Stack management
c. Parameters
Day 3
Review
8086 CPU
a. Block diagram
b. Signal description
8284 -
Clock Generator
8288 -
Bus Controller
828213 -
Octal Latch
8286/7 -
Octal Transceiver
Single Board Computer
a. Design example
Other 8086 Configurations
Interrupt System
a. Description
b. Signal pins
Introduction to PL/M-86
Application Techniques
Table 6. MCS-86 System Workshop Course Outline
12-118
MICROCOMPUTER TRAINING PROGRAMS
PLlM·86 Language/Software Design
Workshop
opment System. The course outline for this workshop is
presented in Table 7.
This workshop will prepare the student for designing,
developing, and debugging modular PUM-86 programs
using lecture, demonstration, and laboratory "handson" experience with the Intellec Microcomputer Devel-
Prerequisites: A knowledge of binary and hexadecimal
number systems and basic logic functions is required.
To attain maximum benefit from course presentation,
some background in logic design and computer programming is recommended.
Day 1
Procedures
a. Declaration
b. Invocation
c. Program construction
Introduction
a. Preview of course
b. Overview of PUM, linking and
relocation
c. Why use a high level language
Data References
a. Based variables
b. Variable equivalencing
c. Pointer type
Definitions
a. Symbols, identifiers, reserved
words, comments, data ele·
ments, expressions, statements,
declarations
Statement Labels
Unconditional Transfers
Blocks
a. Concept and use
b. Scope of declarations
c. Modular compilation
d. Modular program
Data Elements
a. Variables, subscripted variables,
constants
Data Types
a. Logical, integer, real
1515·11 LINK·S6
a. Invoking LlNK·BS
b. Link options
c. Assembly object modules
Operators, Operations and Priorities
a. Arithmetic and boolean
Evaluating Expressions
Laboratory
a. Compile program modules
b. Link and locate modules
c. Execute program
Statements
a. Redefine, basic, conditional
Assignment
a. Implement a given algorithm in
PUM
Day 4
Day 2
Review
1515-11 LIB·S6
a. Creating a library
b. Managing a library
1. Adding modules
2. Deleting modules
1515·11 Disk Operating System
a. Components of system
1515·11 File Structure
a. System fi les
b. User files
c. Device files
d. Directory and file attributes
String Operations
a. Move bytes or words
b. Compare bytes or words
c. Find bytes or words
d. Skip bytes or words
ISIS· II Commands
a. CUSPS - Commonly Used Sys·
tern Programs
b. Directory and attribute commands
c. Rename and delete commands
The LOCKSET Procedure
a. Excluding mutual access
Laboratory
a. Create a library
b. Link object to a library
c. Locate
d. Creating system and user disks
1515·11 Editor
a. Definition of terminology
b. Invoking the editor
c. Editor commands
d. Editing existing files
Day 5
1515·11 PUM-S6 Compiler
a. Invoking PUM
b. Compiler options
Review
Interrupt Procedures
1515·11 LOC-S6
a. Invoking LOC·BS
Predeclared Procedues
a. TIME, MOVE, LENGTH, LAST and
SIZE procedures
b. Type transfers
c. Shifts and rotates
Reentrant Procedures
Laboratory
a. Introduction to ISIS·II disk operating system
b. Creating a PUM source file
c. Compiling a PUM program
d. Locating and executing a PUM
program
The Memory Array and STACKPTR
Variables
Discussion of Selected Programs
Laboratory
a. Execution and debugging of selected programs
Day 3
Review
Table 7. PL/M-86 Language/Software Design Workshop Course Outline
12-119
MICROCOMPUTER TRAINING PROGRAMS
MCS·48 System Workshop
emulator. The course outline for this workshop is pre·
sented in Table 8.
This workshop will prepare the student to design and
develop a system using the Intel 8049 microprocessor,
by means of lectures, demonstrations, and laboratory
"hands-on" experience with the Intellec Microcomputer
Development System, the PROMPT-48, and an in-circuit
Prerequisites: A knowledge of binary and hexadecimal
number systems and basic logic functions is required.
To attain maximum benefit from course presentation,
some background in logic design or computer programming is recommended.
Day 1
Orientation
Introduction
a. Microprocessor System
1. Function
2. Organization
3. Programming
b. 8048 Overview
1. Functional Sections
2. Programming Model
3. Execution Sequence
Assembly Language Instructions
a. 1/0 Instructions
b. Data Move Instructions
c. Increment/Decrement Instructions
d. Branch Instructions
e. Worksession No.1
f. Accumulator Group Instructions
1. ADDIADDC
2. Logicals
PROMPT·48
a. Function
b. Operation
Laboratory Exercise
a. Program Entry and Execution
Using PROMPT·48
Day 2
Assembly Language Instructions
a. Accumulator Group Instructions
1. Flags
2. Rotates
b. Specials (XCH, DA, SWAP)
c. Worksession No.2
d. Subroutines
1. Invocation
2. Stack Operation
e. Interrupt System
1. Description
2. Service Subroutines
3. Multiple Source Systems
Development System
a. Function
b. Disk Operating System
Text Editor and Macro Assembler
a. Function
b. Operation
Laboratory Exercise
a. Bootstrap Procedures
b. Create, Edit, and Assemble
Source Program
c. Execute Program
Day 3
System Timing
a. Basic Timing and Timer
b. Bus Timing for Peripheral Devices
Peripherals and Design
a. Expanding Memory
1. Program Memory (1, 2K ROMs)
2. Data Memory (RAMs)
b. Expanding Ports (8243)
1. Device Characteristics
2. Software Control of Ports
c. Combination Chips
1. 8155 RAM and 1/0 Chip
2. 8355, 8755 ROM and 1/0 Chip
d. Peripheral InterfaCing (Parallel)
1. 8255 Parallel I/O
2. 8279 Keyboard and Display
Interface
-Keyboard Scanning
Techniques
-Display Refresh
Laboratory Exercise
a. Edit and Assemble Using DOS
b. Execute Using PROMPT·48
Day 4
Industrial Grade I2708 is a 8192-bit ultraviolet light erasable and electrically reprogrammable EPROM, ideally suited where fast turnaround and pattern experimentation are important requirements_ All data inputs and outputs
are TIL compatible during both the read and program modes. The outputs are three-state, allowing direct interface
with common system bus structures. The 12708 is fabricated' with the N-channel silicon gate FAMOS technology and
is available in a 24-pin dual in-line package.
BLOCK DIAGRAM
PIN CONFIGURATION
DATA OUTPUT
UO-07
A,
lice
A.
A.
As
AD
A.
lis.
A3
CS/WE
A,
12708
I
OUTPUT BUFFERS
y
DECODER
V GATING
Itoo
PROGRAM
A,
07 (MSS)
(LSSI A.
(LSS) 00
00
01
o.
O.
04
"'".
ADDRESS
INPUTS
A,
AsA,_
A,A.--
Ao-A9
ADDRESS INPUTS
O'.()8
DATA OUTPUTS/INPUTS
x
64 X 128
ROM ARRAY
DECODER
!.\9-
03
PIN NAMES
/WE
CHIP SELECT
LOGIC
PIN CONNECTION DURING READ OR PROGRAM
PIN NUMBER
ADDRESS
CHIPSELECTIWRITE ENABLE INPUT
DATA I/O
9·11.
13-17
MODE
READ
DOUT
DESELECT
HIGH IMPEDANCE
PROGRAM
D,N
INPUTS
1·8.
22.23
A'N
DON'TeARE
A,.
Vss
PROGRA\f1
VOD
12
GND
GND
GND
18
GND
GND
PULSED
19
+12
+12
+12
26V
13-4
CS/WE
20
V"
V,H
VIHW
V ••
Vee
21
-5
-5
-5
24
+5
+5
+5
12716
INDUSTRIAL GRADE
16K (2K x 8) UV ERASABLE PROM
•
Fast Access Time: 450 ns Max
•
Industrial Grade Temperature
Range: - 40°C to + 85°C
•
Single + 5V Power Supply
• Low Power Dissipation
- 603 mW Max. Active Power
- 165 mW Max. Standby Power
• Simple Programming Requirements
Single Location Programming
Programs with One 50 ms Pulse
• Inputs and Outputs TTL Compatible
during Read and Program
• Completely Static
The Intel@ Industrial Grade 12716 is a 16,384-bit ultraviolet erasable and electrically programmable read-only memory
(EPROM). The 12716 operates from a single 5-volt power supply, has a static standby mode, and features fast single address location programming. It makes designing with EPROMs faster, easier and more economical.
The 12716, with its single 5-volt supply and with an access time of 450 ns max, is ideal for use with the newer high performance industrial grade + 5V microprocessors such as Intel's 18085 and 18086. The 12716 is also the first EPROM
with a static standby mode which reduces the power dissipation without increasing access time. The maximum active
power dissipation is 603 mW while the maximum standby power dissipation is only 165 mW, a 75% savings.
The 12716 has the simplest and fastest method yet devised for programming EPROMs-single pulse TTL level programming. No need for high voltage pulsing because all programming controls are handled by TTL signals. Program
any location at any time-either individually, sequentially or at random, with the 12716's single address location programming. Total programming time for all 16,384 bits is only 100 seconds.
PIN CONFIGURATION
12716
MODE SELECTION
~
CE/PGM
DE
V,,
Vee
(18)
(201
(2H
(24)
OUTPUTS
(9·11,13-17)
MODE
Read
V'L
V'L
'5
+5
DOUT
Standby
V'H
Don't Care
+5
+5
High Z
Program
Pulsed V1L to VIH
V'H
+25
+5
D'N
V'L
V'L
.25
+5
DOUl
V'L
V'H
+25
+5
High Z
Program Verify
r-:----:-,
Program Inhibit
BLOCK DIAGRAM
Vcc<>---
PIN NAMES
ADDRESSES
CHIP ENABLE/PROGRAM
1\0" AlO
ADDRESS
INPUTS
OUTPUT ENABLE
0-0
OUTPUTS
13-5
OATA()lITPU1~
---00 0/
18048118648118748118035
INDUST.RIAL TEMPERATURE RANGE
SINGLE COMPONENT 8·BIT MICROCOMPUTER
•
•
•
•
•
8048 Mask Programmable ROM
8648 One·Time Factory Programmable EPROM
8748 User Programmable/Erasable EPROM
8035/8035L External ROM or EPROM
- 40°C to + 85°C Operation
• 8·Bit cPu, ROM, RAM, 1/0 In Single
Package
• 1K x 8 ROMIEPROM
64x8 RAM
271/0 LINES
• Interchangeable ROM and EPROM
Versions
• Interval TimerlEvent Counter
• Single 5V Supply
• 2.5 ",sec and 5.0 ",sec Cycle Versions:
All instructions 1 or 2 Cycles
• Easily Expandable Memory and 1/0
• Over 90 Instructions: 70% Single Byte
• Single Level Interrupt
• Compatible with 808018085 Series
Peripherals
The Intell!> 8048/8648/8748/8035 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip
using Intel's N-channel silicon gate MOS process.
The 8048 contains a 1K x 8 program memory, a 64 x 8 RAM data memory, 271/0 lines, and an 8-bit timerlcounter in addition to on-board oscillator and clock circuits. For systems that require extra capability, the 8048 can be expanded
using standard memories and MCS-80™IMCS-85TM peripherals. The 8035 is the equivalent of an 8048 without program
memory. The 8035L has the RAM power-down mode of the 8048 while the 8035 does not. The 8648 is a one-time programmable (at the factory) 8748 which can be ordered as the first 25 pieces of a new 8048 ROM order. The substitution
of 8648's for 8048's allows for very fast turnaround for initial code verification and evaluation units.
To reduce development problems to a minimum and provide maximum flexibility, three interchangeable pin-compatible versions of this single component microcomputer exist: the 8748 with user-programmable and erasable EPROM
program memory for prototype and preproduction systems, the 8048 with factory-programmed mask ROM program
memory for low cost, high volume production, and the 8035 without program memory for use with external program
memories.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8048 has exten·
slve bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory
results from an instruction set conSisting mostly of single byte instructions and no instructions over 2 bytes in length.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
RESET
.,,
Pl •
'"
SINGLE
STEP
EXTERNAL_
MEM,
18048
"3
TEST {
INTERRUPT-
BUS
13-6
I815SH8156
2048 BIT STATIC MOS RAM WITH I/O PORTS AND TIMER
• Industrial Temperature Range
( - 40°C to + 85°C)
• 2 Programmable 8 Bit I/O Ports
•
• 256 Word x 8 Bits
1 Programmable 6-Bit I/O Port
• Single +5V Power Supply
• Programmable 14-Bit Binary Counter/
Timer
• Completely Static Operation
• Multiplexed Address and Data Bus
• Internal Address Latch
• 40 Pin DIP
The 18155 and 18156 are RAM and 1/0 chips to be used in the MCS·85™ microcomputer system. The RAM portion is
designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit use with no
wait states in 18085A CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status pins,
thus allowing the other two ports to operate in handshake mode.
A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse for
the CPU system depending on timer mode.
PIN CONFIGURATION
pC 3
vee
PC.
pc,
TIMER IN
PC,
RESET
PCo
PC s
PB,
BLOCK DIAGRAM
101M
256 X 8
ADo 7
oliT
PBs
STATIC
101M
PBs
RAM
CE OR CEo
PB.
AD
PB 3
TIMER
WR
PB,
ALE
PB,
ADo
PB o
AD,
PA,
AD,
PAs
AD3
PAs
AD.
PA.
ADs
PA,
AD.
PA,
AD,
PA,
vss
PAo
*
ALE
RD
G
PAo~ 7
G
PB" _,
G
PCo - s
WR-RESET
TIMER
TIMER eLK
Lvcc
(+5V)
Vss (OV)
*:18155 = CE,I8156
13·7
==
CE
18212
8-BIT INPUT/OUTPUT PORT
• Fully Parallel 8-Bit Data Register and Buffer
• Service Request Flip-Flop for
Interrupt Generation
• 3.6SV Output High Voltage for
Direct Interface to 8008, 8080A, or
808SA CPU
• Low Input Load Current -
• Asynchronous Register Clear
.2SmA Max.
• Replaces Buffers, Latches and
Multiplexers in Microcomputer Systems
• Three State Outputs
• Outputs Sink 1SmA
• - 40°C to
+ 8SoC Temp Range
The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection
logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.
The device is multi mode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the
principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
Note: The specifications for the 3212 are identical with those for the 8212.
PIN CONFIGURATION
LOGIC DIAGRAM
SERVICE REOUEST FF
os,
vee
MD
INT
01,
01 8
DO,
00 8
01 2
01,
00 2
DO,
01 3
01 6
00 3
00 6
01,
Dis
DO,
DOs
STa
CLR
GND
DS 2
'\
@>D52
U>
Ml)
----t- SfB ~----iLJ
OUTPUT
BUFFER
IT> [lI, -----....;~--_+-+-t
DATA LATCH
[I> [JI.
-------~-+1
PIN NAMES
01, Dla
00,·00,
flI;.OS2
MO
STa
12]> [) I, - - - - - - - _ + - + 1
DATA IN
DATA OUT
DEVICE SELECT
MODE
iN'!'
STROBE
INTERRUPT (ACTIVE LOW)
eLR
CLEAR (ACTIVE LOW)
~
DI,-------_+-H
§> 0'8 - - - - - - - - - ' - - + 1
~CLR-----<1
13-8
008
IE>
inter
18216/8226
4 BIT PARALLEL BIDIRECTIONAL BUS DRIVER
• 3.65V Output High Voltage for Direct
Interface to 8080 CPU
• Data Bus Buffer Driver for 8080 CPU
• Low Input Load Current Maximum
.25 mA
• Three State Outputs
• Reduces System Package Count
• - 40°C to + 85°C Temp Range
• High Output Drive Capability for
Driving System Data Bus
The 8216/8226 is a 4-bit bi-directional bus driver/receiver.
All inputs are low power TTL compatible. For driving MOS, the DO outputs provide a high 3.65V VOH, and for high capaci·
tance terminated bus structures, the DB outputs provide a high 50mA IOL capability.
A non-inverting (8216) and an inverting (8226) are available to meet a wide variety of applications for buffering in micro·
computer systems.
PIN CONFIGURATION
cs
LOGIC DIAGRAM
8216
LOGIC DIAGRAM
8226
Vee
DO.
OlEN
DB.
DO,
01.
0'0
DB.
DO.
01.
DB,
DO,
01,
DB,
DO,
01,
01, .
01,
De,
D~
DB,
DB,
DO,
GNO
DBo
DO.
DO,
01,
01,
DB,
DO,
PIN NAMES
DB,
DO,
01,
01,
DB,
DB,
O8o-OB,
DATA BUS
BI·DIRECTIONAL
0'0-0"
DATA INPUT
DOo·D0 3
DATA OUTPUT
OlEN
OATA IN ENABLE
DIRECTION CONTROL
cs
CHIP SELECT
..
DO, ~--i---C::t- -+---..J
DO,
L-------I-........----UPPll'"
_1."'1'
OATA
(},O"
BUS
""--PIN NAMES
0,-"0
RESET
cs
iilI
iili
Nl.AI
PA7"Nl
-P87'PC7.f'CO
Vee
lIND
DATA BUS ,BI·DIRECTIDNAL)
RESET INPUT
CHIP SELECT
READ INPUT
WRITE INPUT
cs-_ _.....J
PORT ADDRESS
PORTA,BIT)
PORTB,BIT)
PORTC,BIT)
+6 VOLTS
'VOLTS
13-12
110
1',,",.1'''0
18259
PROGRAMMABLE INTERRUPT CONTROLLER
• MCS·86™ Compatible
• MCS·80185™ Compatible
• Eight·Level Priority Controller
• Expandable to 64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
+ 5V Supply (No Clocks)
• - 40°C to + 85°C Temp_ Range
• Single
The Intel'" 8259 Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input.
The 8259 is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements.
BLOCK DIAGRAM
PIN CONFIGURATION
cs
WA
vee
An
AD
INTA
0,
IA7
D.
IA6
DATA
0,.
IA5
BUFFER
0,
IA4
03
IA3
O2
IA2
0,
IRI
CONTROL lOGIC
BUS
D.
IRO
CASO
INT
CAS 1
Sf/EN
GND
CAS2
RO
WR
CS------'
PIN NAMES
DrDo
DATA BUS IBI-DIRECTIDNAL!
RD
READ INPUT
WR
WRITE INPUT
A.
COMMAND SELECT ADDRESS
CS
CHIP SELECT
CAS2-CASO
CASCADE LINES
SLAVE PROGRAM INPUT/ENABLE
SI'/Elli
INT
INTA
IRO-IR7
CASO
CAS 1
CAS 2
SP/Eiii - - - - '
INTERRUPT OUTPUT
INTERRUPT ACKNOWLEDGE INPUT
INTERRUPT REOUEST INPUTS
13-13
~INTERNAl
BUS
inter
18279
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
Temperature Range
• (Extended
- 40°C to + 85°C)
Simultaneous Keyboard Display
• Operations
• Dual 8· or 16·Numerical Display
• Single 16·Character Display
or Left Entry 16·Byte Display
• Right
RAM
• Scanned Keyboard Mode
• Scanned Sensor Mode
• Mode Programmable from CPU
• Programmable Scan Timing
• Interrupt Output on Key Entry
• Strobed Input Entry Mode
• 8·Character Keyboard FIFO
Lockout or N·Key Rollover with
• 2·Key
Contact Debounce
The Intel'!> 8279 is a general purpose programmable keyboard and display I/O interface device designed for use with
Intel'!> microprocessors. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The
keyboard portion will also interface to an array of sensors or a strobed interface keyboard, such as the hall effect and
ferrite variety. Key depressions can be 2-key lockout or N-key rollover. Keyboard entries are debounced and strobed in
an 8-character FIFO. If more than 8 characters are entered, overrun status is set. Key entries set the interrupt output
line to the CPU.
The display portion provides a scanned display interface for LED, incandescent, and other popular display
technologies. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279
has 16X8 display RAM which can be organized into dual 16X4. The RAM can be loaded or interrogated by the CPU. Both
right entry, calculator and left entry typewriter display formats are possible. Both read and write of the display RAM
can be done with auto·increment of the display RAM address.
LOGIC SYMBOL
PIN CONFIGURATION
Rl,
PIN NAMES
IRQ
08 01
1;0
eLK
I
RESET
I
RESET INPUT
I
CHIPSELECT
OAT A 8US (BI DIRECTIONAL)
.
CLOCK INPUT
READ INPUT
SHIFT
AD
WRITE INPUT
iVA
A,
I
IRa
a
BUffER ADDRESS
INTERRUPT REOUEST OUTPUT
SL03
0
SCAN LINES
RL07
SHIFT
I
RETURN LINES
DB,
CNTl/STB
~~~;~~:~S~ROBE iN~
OUTA(l.)
DISPLAY (AI OUTPUTS
DB,
OUT 803
DB,
DB,
OUT A,
DB,
qUT
I
0
DISPLAY (8)OUTPUT$
a
BLANK DISPLAY OUTPUT
08,
l!I5
C!'
OS
CNTLlSTB
SlOol
SCAN
AO
.
A2
OUT A3
DB,
iVA
CPU
INTERFACE
OUT AO.3
RESET
DISPLAY
ClK
V..
13-14
OUT 80-3
DATA
inter
18355*
16,384-8IT ROM WITH 1/0
* Directly Compatible with 18085A CPU
• Industrial Temperature Range
( - 40°C to + 85°C)
• 2048 Words x 8 Bits
• Single
+ 5V Power Supply
• Internal Address Latch
• 2 General Purpose 8-Bit 110 Ports
• Each 110 Port Line Individually
Programmable as Input or Output
• Multiplexed Address and Data Bus
• 40-Pin DIP
The Intel@ 8355 is a ROM and I/O chip to be used in the MCS-85" microcomputer system. The ROM portion is organized as
2048 words by 8 bits. It has a maximum access time of 400 ns to permit use with no wait states in the I8085A CPU.
The 110 portion consists of 2 general purpose 110 ports. Each 110 port has 8 port lines, and each 110 port line is indlvdually programmable as input or output.
PIN CONFIGURATION
BLOCK DIAGRAM
13-15
18755A-8
16,384-8IT EPROM WITH 1/0
• Directly Compatible with 1808SA CPU
• Industrial Temperature Range
( - 40°C to + 85°C)
• 2 General Purpose 8·Bit 110 Ports
• 2048 Words x 8 Bits
• Each 110 Port Line Individually
Programmable as Input or Output
• Single
+ 5V Power Supply (Vee>
• U.V. Erasable and Electrically
Reprogrammable
• Multiplexed Address and Data Bus
• Internal Address Latch
• 40·Pin DIP
The Intel® 8755A is an erasable and electrically reprogram mabie ROM (EPROM I and I/O chip to be used in the MCS-85'·
microcomputer system. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum access time of
750 ns to permit use with one wait state in a 3 MHz 8085A system.
The 110 portion consists of 2 general purpose 110 ports. Each 110 port has 8 port lines, and each 110 port line is individually programmable as input or output.
BLOCK DIAGRAM
PIN CONFIGURATION
eLK
READY
ADo_7
101M
7
A a- 10
AD
CE,
lOW
ALE
2K)( 8
EPROM
101M
"
ALE
AD
lOW
G
G
RESET
lOR
PROG/CE 1
Voo
13-16
Vee (+5V)
Vss (OVI
PAO-7
PBO-7
Military
Products 14
INTEL MILITARY PRODUCTS
In 1977, Intel qualified the first military microprocessor to MIL·M·38510. The JAN version of the industry standard
8080A is listed in OPL, Part I as M3851 0/42001 BOB.
Intel also offers an extensive family of selected microprocessor and memory components for military/hi·rel applica·
tions. All standard military products are screened to full Level B requirements of MIL·STD·883B, Method 5004. Addi·
tionally, complete lot conformance testing is performed in accordance with MIL·STD·883B, Method 5005.
TABLE OF CONTENTS
M1702A. .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14·4
M2114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14·6
M2115A, M2125A .... , ........................................................................... 14·10
M2147 . . .. . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. 14·15
M2708 ............................................................ , . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·21
M2716 ...........................................". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·27
M3604A, M3624A ................................................................................ 14·32
M3625A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·34
M3636 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·37
M5101·4, M5101 L·4 ............................................................................... 14·40
M8080A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·43
M8212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·48
M8214 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·53
M8216/M8226. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·56
M8224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·59
M8228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·63
M8251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·68
M~~A ........................................................................................ 1~1
M8085A ........................................................................................ 14·74
M8155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·87
M8257. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14·98
M8259 ......................................................................................... 14·105
M8048/M8748/M8035 ............................................................................. 14·110
14·2
MILITARY PRODUCT REQUIREMENTS
MIL·M·38510
Requirements
JAN
(Level B)
883
(Level B)
Para. 3.4.1.2
X
N/A
Para. 3.4.1.2.1
X
N/A
DEVICE QUALIFICATION
Para. 4.4
X
N/A
TRACEABILITY
Para. 3.4.6
X
N/A
COUNTRY OF MANUFACTURE
Para. 3.2.1
X
N/A
General Requirements
CERTIFICATION
A. Product Assurance
Program Plan
B. Manufacturer's
Certification
Screening Test
Requirements
Screening Per Method
5004 of MIL·STD·883
INTERNAL VISUAL
2010, Condo B
100%
100%
STABILIZATION BAKE
1008, Condo C
(24 Hrs. @ 150°C)
100%
100%
TEMPERATURE CYCLING
1010, Condo C (10 cycles
-65°Cto + 150°C)
100%
100%
CONSTANT ACCELERATION
2001, Condo D or E
As Applicable
100%
100%
SEAL (HERMETICITY)
A. Fine
B. Gross
1014
Condo B (5 x 10 atm·cc/sec)
Cond.C
100%
100%
PRE BURN·IN ELECTRICAL
Per Applicable Device
Specification
100%
100%
BURN·IN
1015, Condo C or F
(160 Hrs. @ 125°C)
100%
100%
FINAL ELECTRICAL TESTS
A. Static (@ 25°C, Min and
Max Rated Temp)
B. Dynamic and Functional
(@ 25°C)
Per Applicable Device
Specification
Per Applicable Device
Specification
100%
100%
100%
100%
EXTERNAL VISUAL
2009
100%
100%
JAN
(Level B)
883
(Level B)
Quality Conformance
Inspection Tests
Per MIL·STD·883,
Method 5005
GROUP A
Electrical Tests
Per Applicable Device
Specification. Table I,
Subgroups as Required
Every
Inspection
Lot
Every
Inspection
Lot
GROUP B
Package Function and
Mechanical Tests
Per Table lib,
Subgroups 1·3
Every 6
Weeks
Every 6
Weeks
GROUP C
Die Related Tests
Per Table III,
Subgroups 1 and 2
Every 12
Weeks
Every 12
Weeks
GROUP D
Package Related Tests
Per Table IV,
Subgroups 1·5
Every 6
Months
Every 6
Months
14·3
M1702A
2K (256 x 8) UV ERASABLE PROM
-55°C to +100°C OPERATION
• All 2048 Bits Factory Tested Prior
to Shipment
• Fast Access Time: Max. 850ns
• Completely Static
• Inputs and Outputs DTL and
TTL Compatible
• Three-State Output
• 24 Pin Dip
The Intel® M1702A is a 256-word by 8-bit ultraviolet light erasable and electrically reprogrammable EPROM which is specified over the _55°C to +100°C temperature range_ The M1702A has a transparent lid which allows the user to expose the
M 1702A to UV light to erase the bit pattern, A new pattern can then be written into the device,
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Ambient Temperature Under Bias
Storage Temperature
.. -65°C to 110°C
_65°C to + 125 °c
Soldering Temperature of Leads (10 sec)
+300 oC
.2 Watts
Power Dissipation
Read OperatIon: Input Voltages and Supply
Voltages with respect to Vee
. +O.5V to -20\/
Program Operation: Input Voltages and Supply
, , , , , -48V
Voltages with respect to Vee
"COMMENT
Stresses above those listed under "Absolute Maximum Rat·
ings" may cause permanent damage to the device. This is a
stress ratIng only and functIOnal operation of the device at
these or at any other condition above those indicated in
the operational sections of this speCIfication is not Implied.
Exposure to Absolute MaXimum Rating conditions for ex
tended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA = -55°C to 100°C, Vee = +5V ±10%, Voo = -9V ±10%,
READ OPERATION
VGG = -9V ±10% unless otherwise noted,
Symbol
Test
III
Address and Chip Select Input Load Current
Min,
Typ,Cl]
Max,
Unit
10
/lA
VIN = O,OV
Conditions
IlO
Output Leakage Current
10
/lA
VOUT = O,OV,CS~ VIH2
1001 [1]
Power Supply Current
35
50
mA
CS=VIH2, IOl =O,OmA,
TA = 25°C, Continuous
1002
Power Supply Current
32
46
mA
CS =O,OV, IOl =O,OmA,
TA = 25°C, Continuous
1003
Power Supply Current
38
65
mA
CS=VIH2, IOl =O,OmA,
TA = -55°C, Continuous
leF
Output Clamp Current
8
11
mA
VOUT = -1.0V,
TA = -55°C, Continuous
IGG
Gate Supply Current
10
/lA
Vill
Input Low Voltage for TTL Interface
-1
0,65
V
VIl2
Input Low Voltage for MOS Interface
Voo
Vee-6
V
VIHl
Address Input High Voltage
Vce- 2
Vee+O,3
V
Vee -1.5
Vee+O,3
VIH2
Chip Select Input High Voltage
IOl
Output Sink Current
IOH
Output Source Current
VOL
Output Low Voltage
VO H
Output High Voltage
Note 1.
1.6
4
-2,0
-3
3,5
Typical values are at nominal voltages and T A "" 25° C.
14-4
4,5
0,45
V
mA
VOUT = 0,45V
mA
VOUT = O,OV
V
IOl = 1.6mA
V
IOH = -200/lA
M1702A
A.C. CHARACTERISTICS
TA = -55°C to 100°C, Vee = +5V ±1 0%, VDD = -9V ±10%, vGG = -9V ±10% unless otherwise noted.
,,:,
Limits
Symbol
Test
Freq.
Min.
Repetition Rate
:'; ",f\
Max.
Unit, ,
1.2
MHz
tcH
I'revious Read Data Valid
0.1
Jls
tAce
Address to Output Delay
0.85
JlS
tes
Chip Select Delay
0.5
JlS
teo
Output Delay From CS
0.35
Jls
taD
Output Deselect
0.3
JlS
CAPACITANCE" TA
SYMBOL
CIN
=
25°C
TEST
TYPICAL
MAXIMUM
UNIT
Input Capacitance
8
15
pF
Output Capacitance
COUT
10
15
pF
CONDITIONS
V 'N ' V"
}
All
CS = Vee
unused pins
VOUT = Vee
are at A.C.
VGG = Vee
ground
*This parameter is sampled and is not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test:
I nput pulse amplitudes: 0 to 4V; tR ,t F S 50 ns
Output load is 1 TTL gate; measurements made
at output of TTL gate (tPD';;15 ns), C L = 15pF
A) READ OPERATION
- - - C Y C U : TI".,1E
B) DESELECTION OF DATA OUTPUT IN OR-TIE
OPERATION
l!FHfO-~
,
v,"
yw;
X
ADDRESk'--_ _ _ _ _ _ _....J'
VtL
I
-I ICS
-
I
~
(5 v," ~
V1l
I
g~~:aH -;---~-NA-}-:-L-~-T----,,\
'-----
I
I-
'0"-:
r
:
~L--+------------~~----'4-----~--1-1
• - - - 'Ace - - - - - - - - t
ERASING AND PROGRAMMING PROCEDURE
The erasing and programming procedure of the M1702A
is the same as the O'C to 70'C 1702A. The procedure is
described in the Data Catalog PROM/ROM Programming Instructions section.
14-5
" ",
inter
M2114
1024 x 4 BIT STATIC RAM
I Max. Access Time (ns)
I
Max. Power Dissipation (mw)
2114-3
300
575
2114
450
575
2114L3
300
410
2114L
450
410
• Directly TTL Compatible: All Inputs
and Outputs
• High Density 18 Pin Package
• Identical Cycle and Access Times
• Common Data Input and Output Using
Three-State Outputs
• Single +5V Supply
• No Clock or Timing Strobe Required
• Military Temperature Range
-55°C to +125°C
• Completely Static Memory
The Intel® M2114 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits LJSlng N-channel SiliconGate MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The M2114 is designed for memory applications where high performance. low cost. large bit storage. and simple
interfacing are important design objectives. The M2114 is placed in an 18-pin package for the highest possible density.
It is directly TTL compatible in all respects: Inputs. outputs. and a single "1"5V supply. A separate Chip Select rCS) lead
allows easy selection of an individual package when outputs are OR-tied.
PIN CONFIGURATION
LOGIC SYMBOL
A3
'\
vee
Ao
As
A,
A,
A,
As
A3
As
Ao
tlO,
A,
1/0,
A,
1/03
A,
I/O,
A,
A,
1/°2
As
CS
As
@
~vcc
(:D
Q)
A,
CD
A
~
(17'
~GND
ROW
SELECT
MEMORY ARRAY
64 ROWS
64 COLUMNS
'@
As
A,
GNO
BLOCK DIAGRAM
(4)
1/° 3
A,
1/0,8
A,
1/°4
As
WE
A.
1/°4
I/O,@
110,@
WE
CS
PIN NAMES
AO-A9
WE
ADDR ESS INPUTS
Vee POWER 1+5VI
WRITE ENABLE
GND GROUND
CS
CHIP SELECT
1/0, -110.
DATA INPUT/OUTPUT
WE~-'L....~
14-6
o
0
PIN NUMBERS
M2114 FAMILY
'COMMENT: Stresses abo~~'ih~/
Maximum Ratings" may cause p~;~~""~,,
device. This is a stress rating only and fur/!;tio,fJ.
tion of the device at these or any other col/fJrtic{lnl,fJ
those indicated in the operational sections of thj~ Shijplfi;"
cation is not implied. Exposure to absolute maximum "
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . -65°C to +150°C
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . -0.5V to +7V
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . 1.0W
D.C. Output Current
. . . . . . . . . . . . . . . . . . . . . 5mA
D.C. AND OPERATING CHARACTERISTICS
TA ; -55°C to +125°C, Vcc ; 5V ± 10%, unless otherwise noted.
SYMBOL
PARAMETER
M2114, M2114-3
Typ.l1] Max.
Min.
M2114L3, M2114L3
Typ.!1] Max.
Min.
UNIT
CONDITIONS
III
I nput Load Current
(All Input Pins)
10
10
JlA
VIN ; 0 to 5.5V
llLOI
I/O Leakage Cu rrent
10
10
JlA
CS; 2.4V,
Vila; O.4V to Vcc
ICCl
Power Supply Current
ICC2
Power Supply Current
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
10L
Output Low Current
2.1
6.0
2.1
6.0
mA
VOL; O.4V
10H
Output High Current
-1.0
-1.4
-1.0
-1.4
mA
VOH ; 2.4V
IOS[2]
Output Short Circuit
Current
80
95
65
mA
V IN ; 5.5V,
TA;25°C
105
75
mA
VIN ; 5.5V 1110; OmA,
TA; _55°C
0.8
V
0.8
-0.5
6.0
2.0
6.0
40
40
1110; 0 mA,
V
mA
NOTE: 1. Typical values are for T A = 25° C and Vee = 5.0V.
2. Duration not to exceed 30 seconds.
CAPACITANCE
TA ; 25°C, f ; 1.0 MHz
SYMBOL
TEST
CI/O
Input/Output Capacitance
CIN
Input Capacitance
CONDITIONS
MAX
UNIT
5
pF
Vila ;OV
5
pF
VIN ; OV
NOTE: This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . 0.8 Volt to 2.0 Volt
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . 10 nsec
Input and Output Timing Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Volts
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF
14-7
TEST NOTE: This circuit
employs a self starting
oscillator and a charge
pump which require a
certain amount of time
after POWER ON to start
functioning properly. This
M2114 circuit is conservatively specified as requir·
ing 500 !-,sec after Vee
reaches its specified
limits (4.50V).
M2114 FAMILY
A.C. CHARACTERISTICS
= -55°C to +125°C, Vcc = 5V ±10%, unless otherwise noted.
TA
READ CYCLE [1]
M2114, M2114L
PARAMETER
SYMBOL
Min.
Max.
450
M2114-3, M2114L3
Min.
UNIT
Max.
ns
300
t RC
Read Cycle Time
tA
Access Time
450
300
ns
teo
Chip Selection to Output Valid
120
100
ns
tex
Chip Selection to Output Active
toTO
Output 3·state from Deselection
tOHA
Output Hold from Address Change
50
PARAMETER
Min.
20
20
ns
80
100
ns
ns
50
WRITE CYCLE [2]
M2114, M2114L
SYMBOL
Max.
M2114·3, M2114L3
Min.
UNIT
Max.
twc
Write Cycle Time
450
300
ns
tw
Write Time
200
150
ns
tWR
Write Release Time
0
0
toTW
Output 3-state from Write
tDW
Data to Write Time Overlap
200
150
ns
tDH
Data Hold From Write Time
0
0
ns
ns
100
80
ns
NOTES:
1. A Read occurs during the overlap of a low
CS
and a high WE.
2. A Write occurs during the overlap of a low CS and a low WE.
WAVEFORMS
READ CYCLE@
WRITE CYCLE
.
I------'Re-------I
'we
r------'A-------i
ADDRESS
+_'1'-___
ADDRESS _Jj\._ _ _ _ _ _ _ _ _ _
i--twR-
:'\\' 1\\\'
rT1771T1711177
tw
Dour
® k\\'\
------------*¢==~
-toT~1
NOTES:
@
@)
Dour
i'DW
WE is high for a Read Cycle.
If the
CS low transition
occurs simultaneously with the WE low
transition, the output buffers remain in a high impedance state.
D,N
® WE must be high during all address transitions.
14·8
rt:
1
tOH
M2114 FAMilY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
1.2
1.2
1. 1
1.1
1.0
~
$
o
~
..
:;
~
o
z
0.9
0.8
----
1.0
$
r----
0
w
..
N
0.9
.,;/
:;
:E
a:
0
0.8
0.7
0.6
0.6
0.5
4.50
4.75
5.00
5.25
V
0.5
-55
5.50
V
.,;V
z
0.7
Vs..,
-10
35
80
125
Vee (V)
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
1.7
1.2
.,.....
1. 1
~
1.0
~
1.1
1.0
u
u
$
~
0.9
~
a:
~
rilN
0.9
:E
a:
0
0.8
..
N
..............
~ r--...
:;
:;
0.8
z
0.7
0.7
0.6
0.6
0.5
100
200
300
400
500
0.5
-55
600
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
30
30
'"
./
"~
o
o
80
TA I"C)
40
10
35
~
CL IpF)
40
20
-10
...........
10
"~
/
/
V
"
VOL (V)
14-9
125
~
o
o
VOH IV)
--
M2115A, M2125A FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
M2115Al, M2125Al
M2115A, M2125A
Max. T AA (ns)
75
55
Max. ICC (mA)
75
125
HMOS Technology
• low
Operating Power Dissipation
• 413mW
(M2115Al, M2125Al)
Inputs and Output
• TTL
Collector (M2115A,
• Uncommitted
M2115Al) and Three State (M2125A,
M2125Al) Output
Access Time Over -55°C to 125°C
• Fast
- 55ns Maximum (M2115A, M2125A)
Non-Inverting
Data Output
•
• Single 5V Supply with ±10% Tolerance • Hermetic 16 Pin Dual In-line Package
The Intel® M2115A and M2125A families are fully static, random access memories (RAMs) organized as 1024 words by 1
bit, which operate over a -55°C to +125°C ambient temperature range. Both open collector (M2115A) and three-state
(M2125A) outputs are available. The M2115A and M2125A use fully DC stable (static) circuitry throughout in both the array
and the decoding, and, therefore, require no clocks or refreshing to operate. The data is read out nondestructively and has
the same polarity as the input data.
The M2115AL and M2125AL are ideal for high-performance systems where speed and power dissipation are significant
design considerations. They have a maximum access time of 75 ns, while power dissipation is only413 mW maximum. The
M2115A and M2125A at 55 ns maximum should be considered for applications in which speed is a primary design
objective.
The devices are directly TTL compatible in all respects: inputs, outputs and a single+5V supply. A separate chip select lead
allows easy selection of an individual package when outputs are OR-tied.
PIN CONFIGURATION
LOGIC SYMBOL
CS
BLOCK DIAGRAM
DIN WE
WORD
os
Vee
Ao
DON
A,
A,
WE
A,
's
Ao
t-----
DRIVER
14
32 X 32
ARRAY
t
1
AT
A,
A,
A,
."
AT
A,
A,
DOUT
A,
GND
A,
SENSE AMPS
AND
WRITE
A,
A,
DRIVERS
10
A,
11
A,
12
A,
'3
J
ADDRESS
Vee
PIN 16
GND =
PIN 8
~
t t t } !,
'S
As A6 A) As A
@@@@@
PIN NAMES
W£
"'_
DoT
TABLE)
CD
ADDRESS
DECODER
DECODER
tIt t 1
.~ TOAg
,..........
lOGIC
--
°OUT
Ao Al At A3 A4
C!l
CONTROL
(SEE TRUTH
WE
0,
,
0.:: @ @
TRUTH TABLE
CHIP SELECT - -
ADD";~
INPUTS
WRITE ENABLE
CS
DATA INPUT
DATA OUTPUT
DoUT
H
X
L
L
l
H
HIGH Z
HIGH Z
H
X
DoUT
L
L
14·10
WE o.N
OUTPUT
OUTPUT
2115A FAMilY 2125A FAMll Y
X
L
HIGH Z
MODE
DoUT
HIGH Z
HIGH Z
WRITE "0"
HIGH Z
WRITE "1"
DoUT
READ
NOT SELECTED
M2115AL, M2115A, M2125AL, M2125A
ABSOLUTE MAXIMUM RATlNGS*
u~d'~';\
'COMMENT: Stresses above those listed
".(X1i>solute Maximum Ratings" may cause permanent damage to the ,de'l1'ic&. This is
Temperature Under Bias. . . . . . . . . .. -65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
All Output or Supply Voltages . . . . . . . . . . -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . -0.5V to +6V
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . 20 mA
a stress rating only and functional operation of the devlce
at'these
or at any other condition above those indicated in the operaiional., ,
sections of this specification is not implied. Exposure to absolute \,::',~
maximum rating conditions for extended periods may affect device' ,
reliability.
D.C. CHARACTERISTICS[1.21
Vcc=5V±10%. TA=-55°Cto+125°C
Symbol
Test
Max.
Unit
VOL1
M2115A, M2115ALOutput Low
Voltage
Min.
Typ.
0.45
V
IOL=10mA
VO L2
M2125A, M2125AL Output Low
Voltage
0.45
V
10L = 5 mA
VIH
Input High Voltage
V IL
Input Low Voltage
IlL
Input Low Current
IIH
2.1
Conditions
V
0.8
V
-0.1
-40
/lA
VCC= Max., V IN = 0.4V
Input High Current
0.1
40
/lA
VCC = Max., VIN = 4.5V
I CEX
M2115A, M2115AL Output Leakage
Current
0.1
100
/lA
Vcc = Max., VOUT = 4.5V
ilOFFI
M2125A, M2125AL Output Leakage
Current (High Z)
0.1
50
/lA
VCC = Max., VOUT = 0.5V/2.4V
IOS[31
M2125A, M2125AL Current Short
Circuit to Ground
mA
Vcc = Max.
VO H
M2115A, M2115AL Output High
Voltage
ICC1
M2115AL, M2125AL Power Supply
Current
ICC2
M2115A, M2125A Power Supply
Current
-100
2.4
V
10H = -3.2 mA
60
75
mA
All Inputs Grounded, Output
Open
100
125
mA
All Inputs Grounded, Output
Open
NOTES:
1. The operating ambient temperature ranges are guaranteed with transverse air flow exceeding 400 linear feet per minute.
Typical thermal resistance values of the package at maximum temperature are:
8JA (@400fPM air flow)
8JA (still air) ~ 60°C/W
8JC = 25°C/W
~
45°C/W
2. Typical limits are at Vee = 5V, TA:O: +25°e and maximum loading.
3. Duration of short circuit current should not exceed 1 second.
14·11
M2115AL,M2115AA.C.CHARACTERISTICS[1,21
VCC=5V±10%, TA=-55°Cto+125°C
Th'
·,t",
READ CYCLE
Symbol
tACS
tRCS
tAA
tOH
M2115AL Limits
Typ.
Min.
Max.
Test
Chip Select Time
Chip Select Recovery Time
Address Access Time
Previous Read Data Valid After Change of
Address
45
50
75
5
40
5
U/\'itSi"",
\\"~"
45
35
55
35
ns
ns
ns
10
10
,'(
,\m1~'!"'\\l'~1i'"
M2115A Limits
Typ.
Min.
Max.
ns
WRITE CYCLE
Symbol
tws
tWR
tw
tWSD
tWHD
tWSA
tWHA
twSCS
tWHCS
Typ.
Min.
Test
Write Enable Time
Write Recovery Time
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Typ.
0
40
5
5
5
5
5
5
10
-5
0
0
0
0
0
Max.
Units
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
-5
0
0
0
0
0
r--------,
ALL INPUT PULSES
I
4.5V
-,
3.5to.P
/-,
- -
i· '
30an
GND
\
90%
-- -.. --';.;."';;..'---
-=- _.. . ..
-10ns
:_---10n5
-::J\ - -- -- ---!
lOpF
(INCLUDING
SCOPE AND
JIG)
3.5VP·~ _ ~
-r
'
-=- ..;:_
_ __. __
GND
READ CYCLE
AO·A.
Min.
45
50
0
55
5
5
15
5
5
5
A.C. TEST CONDITIONS
600n
Max.
~
_ _ _ _ _ _ _ __ _
10ns
--:
10%
~
,
__ 90%
;___ --lOos
WRITE CYCLE
---..I~"'--------------
r
AO·A9
.'-
~f-
"",I-
~r
--.'{_ t w __
DATA VALID
WE
.
----tr
PROPAGATION DELAY FROM CHIP SELECT
tWSD
~_t:j
twscs
14·12
1------1
tWHO
_tWHA_
-r--
i·.·iC~~::'~
(ALL ABOVE MEASUREMENTS REFERENCED TO 1.5V)
r-
lws
q~':;Hcs-1
~
I;;~\~~~
M2115AL, M2115A, M2125AL, M2125A
M2125AL, M2125A A.C. CHARACTERISTICS[1.2]
,,'111,\1
'''I
,
READ CYCLE
Symbol
M2125AL Limits
Typ.
Min.
Max.
Test
Chip Select Time
Chip Select to HIGH Z
Address Access Time
Previous Read Data Valid After Change of
Address
tACS
tZRCS
tAA
tOH
5
M2125A Limits
Typ.
Min.
Max.
45
50
75
40
5
10
ns
ns
ns
45
35
55
25
,,'
Units '
10
ns
WRITE CYCLE
Symbol
Test
Min.
Write Enable to HIGH Z
Write Recovery Time
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time
Address Hold Time
Chip Select Setup Time
tzws
tWR
tw
tWSD
tWHD
tWSA
tWHA
WSCS
tWHCS
Max.
0
0
0
A.C. TEST CONDITIONS
r-r--l- --
M2125A
DOUl -~r----+
"'tND
30pF
(INCLUDING
SCOPE AND
JIG)
Ao.Ag _ _
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
,
,
I
I
:-;':---90%
,
I
-=- _..: :__ 10ns
I
READ CYCLE
35
35
_; _____________ : _\1,;_;.;;__';;;;0%:=-_ _
~~~
GND
Units
0
0
0
5
3.±5VP'P_ _
610n
Max.
10
-5
0
0
ALL INPUT PULSES
4.5V
300n
0
40
5
5
5
5
5
10
-5
0
0
5
Typ.
Min.
45
50
0
55
5
5
15
5
5
Chip Select Hold Time
Typ.
-= --I
I
I
--l :____ 10ns
- - - - ~ ~ ~ ~--~ ~! -~::
I
---1
f--1Ons
I
:---1Ons
WRITE CYCLE
--J~~------------
,C--
~
-:~
-ll-
AO Ag
l - tAA -
-cr
D'N
-if-
DATA VALID
.-t\l\l~
WE
...:~
PROPAGATION DELAY FROM CHIP SELECT
twso
---
7 <-
~ltw"O
_tWHA __
~IWSA---'
I---'wscs~
(ALL ABOVE MEASUREMENTS REFERENCED TO 1.5V)
14·13
~
~tWHCS~
M2115AL, M2115A, M2125AL, M2125A
'.
~' \'
./
M2125AL. M2125A WRITE ENABLE TO HIGH Z DELAY
5V
\
.'
r-
~'TEENABLE~1.5V
~
r-----
HIGHZ
DOUT
M2125Al,
DATA OUTPUT _ _..,;;,,0·..,;·L;;;E,;;"VE;;.;L,,-_-'I
5pF
M2125A
}0.5V
"," LEVEL
}0.5V
DOUT
'-- -.!!!~!
DATA OUTPUT
LOAD 1
M2125AL. M2125A PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z
CHIP SELECT
os
{
1.5V
- - _......
t
zRCS
....
r--Hi
I-
-'----=====:::::j
~._._J_ _ _L __ _
20
40
60
80
'·15%
100
DESFLECT TIME (ns)
FIGURE 3. tACS VS. DESELECT TIME.
The power switching characteristic of the M2147 requires
more careful decoupling than would be required of a
constant power deVice. It is recommended that a O. 1J1F to
0.3J1F ceramic capacitor be used on every other device,
with a 22J1F to 47J1F bulk electrolytic decoupler every 16
devices. The actual values to be used will depend on board
layout, trace widths and duty cycle. Power supply
gridding is recommended for PC board layout. A very
satisfactory grid can be developed on a two-layer board
with vertical traces on one side and horizo'ltal traces on
the other, as shown in Figure 4.
VCC---;~S-_-i
FIGURE 1. icc WAVEFORM.
ICC 0:
W
;:;
0
Co
W
U
:;
w
"w
'«w"
FIGURE 4. PC LAYOUT.
0:
>
«
Terminations are recommended on input signal lines to
the M2147 devices. In high speed systems, fast drivers can
cause significant reflections when driving the high
impedance inputs of the M2147. Terminations may be
required to match the impedance of the line to the driver.
The type of termination used depends on designer
preference and may be parallel resistive or resistivecapacitive. The latter reduces terminator power dissipation.
::;:
w
lV>
>
V>
ISB
I
4K 8K 16K
32K
64K
MEMORY SIZE IN WORDS
FIGURE 2. AVERAGE DEVICE DISSIPATION VS.
iMEMORY SIZE.
14-20
inter
M2708
8K (1 K x 8) UV ERASABLE PROM
• Extended Temperature Range:
- 55°C to 100°C
• Static: No Clocks Required
• Fast Programming: Typ. 100 sec. For All
8K Bits
• Inputs and Outputs TTL Compatible
During Both Read and Program Modes
• Low Power During Programming
• Access Time: 450 ns Max.
• Three·State Output: OR·Tie Capability
• Standard Power Supplies:
+12V, +5V, -5V
• Hermetic Package: 24 Pin DIP
The Intel M2708 is a high speed 8192 bit erasable and electrically reprogrammable ROM (EPROM) ideally suited where fast
turn around and pattern experimentation are important requirements.
The M2708 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows the user to expose the
chip to ultraviolet light to erase the bit pattern. A new pattern c;;an then be written into the devices.
The M2708 is fabricated with the time proven N-channel silicon gate technology.
PIN CONFIGURATION
BLOCK DIAGRAM
A,
Vee
A6
A,
A.
Ag (MSB)
A.
~.
A,
CS/WE
A,
I
CHIP SELECT
CsfWE-
LOGIC
OUTPUT BUfFERS
Ik>o
M2708
06
ADDRESS{~~Jr-------iDEC6DERF:
. t---------tYGATING
O.
INPUTS
PROGRAM
A,
(LSSI Ao
07 (MSS)
0,
02~"
'.~
\ts
13
12
DATA OUTPUT
00-07
A._
A4
" " ,"
A.__
L~-I
V4
03
R4X 178
~'"-I
"_UMAKHA'----'
PIN NAMES
PIN CONNECTION DURING READ OR PROGRAM
Ao-Ag
ADDRESS INPUTS
o,-os
DATA OUTPUTS
C!WE
CHIP SELECT!WRITE ENABLE INPUT
PIN NU~~BER
DATA I/O
9·11.
MODE
13-17
READ
DOUT
DEslli'CT
PROGRAM
HIGH IMPEDANCE
--;::--------
D'N
ADDRESS
INPUTS
1·8,
,
'~
vJ
22,23
12
A'N
DON'TeARE
GND
~~
GND
GND
PROGRAM
1.
GND
GND
PULSED
VIHP
14-21
Voo
19
+12
CS/WE
v••
20
21
Vee
24
+12
+12
V,"
-5
+5
+.
-5
+5
V'L
VIHW
-.
M2708
Absolute Maximum Ratings'f
Temperature Under Bias. . . . . . . . . . . . . . . . . . . . . ..
'eOMMENT
-65°C to 110°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
Voo With Respect to VBB . . . . . . . . . . . . . . . . . . . . . .. +20V to -O.3V
Vee and Vss With Respect to V BB . . . . . . . . . . . . . . . . . +15V to -0.3V
All Input or Output Voltages With Respect
Stresses above those Iisted under" Absolute Maximum
Ratings" may cause permanent damag'e t.0: the device.
This is a stress rating only and functional qpe-ratiofl:
of the device at these or any other conditions abqve
to VBB During Read. . . . . . . . . . . . . . . . . . . . . . . ..
CS/WE Input With Respect to VBB
During Programming . . . . . . . . . . . . . . . . . . . . . . . .
Program Input With Respect to V BB . . . . . . . . . . . . . . ..
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+15V to -0.3V
specification is not implied. Exposure to absolute
+20V to -0.3V
+35V to -0 3V
. . . ..
1.8W
affect device reliability.
those indicated in the operational sections of this
maximum rating conditions for extended periods may
READ OPERATION
D.C. and Operating Characteristics
TA = _55°C to 100°C, Vee = +5V ±10%, Voo = +12V ±10%, VBB[1J = -5V ±10%, Vss =
Symbol
Typ.[2J
Min.
Parameter
III
Address and Chip Select Input Sink Current
1
ov, unless otherwise noted.
Max.
Unit
10
jJ.A
Conditions
VIN = 5.5 V or VIN = VIL
ILO
Output Leakage Current
1
10
jJ.A
VOUT = 5.5 V, CSIWE= 5V
100[3J
Voo Supply Current
50
80
rnA
Worst Case Supply Currents:
i ee [3]
Vee Supply Current
6
15
rnA
All Inputs High
60
rnA
CSIWE = 5V; TA = -55°C
I BB [3J
V BB Supply Current
V IL
Input Low Voltage
Vss
0.65
V
V IH
Input High Voltage
3.0
Vee +l
V
VOL
Output Low Voltage
0.45
V
IOL = 1.6rnA
VOH1
Output High Voltage
3.7
V
IOH
VO H2
Output High Voltage
2.4
V
IOH=-lmA
Po
Power Dissipation
mW
TA = 100°C
30
750
= -100jJ.A
NOTES: 1. VBB must be applied prior to Vee and VOO. VBB must also be the last power supply switched off.
2. Typical values are for TA = 25°C and nominal supply voltages.
3. The total power dissipation of the 2704/2708 is specified at 750mW. It is not calculated by summing the various currents (100,
ICC. and ISS) multiplied by their respective voltages since current paths exist between the various power supplies and VSS. The
100, ICC, and IBB currents should be used to determine power supply capacity only.
Typical D.C. Characteristics
1....
60
zUJ
a
80
80
...........
a:
a:
40
~
it
::l
VI
_g5 20
ICC CURRENT VS. TEMPERATURE
100 CURRENT VS. TEMPERATURE
IBB CURRENT VS. TEMPERATURE
so
-
., "- r"- ..........
~E"HIGH
t
I
I
CSiE"r W
o-60
-40
-20
0
20
40
60
-
I
I
r--- ..........
1
-r-
K/WE" HIGH
....................
1--_ _ ......
-
60
....
~
a:
a:
~
I
40
~
it
CSIWE" LO.J;--
- r-- -
::l
VI
_t?
20
r80
0
100 120
~~
~
0
~
40
TA I" el
14·22
M
so
100
1~
M2708
,-' :,~
,'~, -'
,
A.C. Characteristics/~i'A"i'~' •.\' • ',!is·' .......
TA = _55°C to 100°C, Vee = +5V ±10%, Voo = +12V ±10%, VBB = -5V ±10%, Vss = OV,
Un\e~5'Otherwise'I'l~~,l:C:\
.':
_I,'
Symbol
Parameter
Min.
tAee
Address to Output Delay
teo
Chip Select to Output Delay
tOF
Chip De-Select to Output Float
0
tOH
Address to Output Hold
0
~.
>',:
,~(
Typ.
Max.
~P"Uh·:tt'
t:'
~,\-\ :~
2BO
450
ns
120
ns
120
ns
60
• -I,· ,",
-,' ~'
ns
A.C. TEST CONDITIONS:
Symbol
Parameter
Typ. Max. Unit Conditions
CIN
Input Capacitance
4
6
pF
VIN=OV
CO UT
Output Capacitance
B
12
pF
VOUT=OV
Note 1.
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ';;;20 ns
Timing Measurement Reference Levels: O.BVand
2.BV for inputs; O.BV and 2.4V for outputs
Input Pulse Levels: 0.65V to 3.0V
This parameter is sampled and not 100% tested.
Waveforms
ADDRESS
_X~_--JX,---I
,_toH_1
CSIWE
~'---_ _---J)
:___ toF_1
f-.tCO_1
1~.----tACC
I
I
DoAuTTAr;~;;~JJI~~:~,~······ . ·.·. . .···.·.......jiK______________..LI"".•••••'"• • •"'.~"'t" ~A" ~T"'~N"'~6"'•>"••'•"•.·.w·. . . ·.
ERASURE CHARACTERISTICS
The erasure characteristics of the IVILIUti are suell LlldL
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range.
Data show that constant exposure to room level fluorescent
lighting could erase the typical M270B in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the M270B is to
be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from
Intel which should be placed over the M270B window to
prevent unintentional erasure.
PROM/ROM Programming Instructions section) for the
M270B is exposure to shortwave ultraviolet light which has
a wavelength of 2537 Angstroms (A). The integrated dose
(i.e., UV intensity X exposure time) for erasure should be
a minimum of 15 W-sec/cm 2 . The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 1200 /lW/cm 2 power rating. The M270B
should be placed within 1 inch of the lamp tubes during
erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
14-23
M2708
I.
ERASING P R O C E D U R E " , . ' ; i
, fi, If"
~, .\' ,'.
" '"
'l"
.,,,
The M2708 is erased by exposure to high intensity short wave ultraviolet light at a wavelength of 2537 A.'t.ti,~,;'ecomm~~.,' .
grated dose (i.e., UV intensity x exposure time) is 10W-sec/cm 2 . An example of an ultraviolet source which can era~~ .~h~r "
,,:'\\\
in 30 minutes is the Model S52 short wave ultraviolet lamp. The lamp should be used without short wave filters and~!t~'~i(jM\f,'",i
should be placed about on,e inch away from the lamp tubes.
I' .,{ ;)")'Y''''~I
Two manufacturers of the S52 are Ultra-Violet Products, Inc. (San Gabriel, Calif.) and Product Specialities, Inc. (lssaq·~<&.~" '~:'"
Washington).
"
l(;.,,,"
To prevent damage to the device, it is recommended that no more ultraviolet light exposure be used than that necessary to erase
the M2708.
II.
PROGRAMMING INSTRUCTIONS
Initially, and after each erasure, all bits of the M2708 are in the "1" state (Output High). Information is introduced by selectively
programming "0" into the desired bit locations. A programmed "0" can only be changed to a "1" by UV erasure.
The circuit is set up for programming operation by raising the CS/WE input (Pin 20) to +12V. The word address is selected in the
same manner as in the read mode. Data to be programmed are presented, 8-bits in parallel, to the data output lines (Ol'OS)'
Logic levels for address and data lines and the supply voltages are the same as for the read mode. After address and data set up
one program pulse per address is applied to the program input (Pin 18). One pass through all addresses is defined as a program
loop. The number of loops (N) required is a function of the program pulse width (tpw) according to N x tpw ;;'100 ms.
The width of the program pulse is from 0.1 to 1 ms. The number of loops (N) is from a minimum of 100 (tpw = 1 ms) to greater
than 1000 (tpw = 0.1 ms). There must be N successive loops through all 1024 addresses. It is not permitted to apply N program
pulses to an address and then change to the next address to be programmed. Caution should be observed regarding the end of a
program sequence. The CS/WE falling edge transition must occur before the first address transition when changing from a program
to a read cycle. The program pin should also be pulled down to VILP with an active instead of a passive device. This pin will source
a small amount of current (II PL) when CS/WE is at VI HW (12V) and the program pulse is at V ILP .
Programming Examples (Using N x tpw ;;. 100 ms)
Example 1:
All 8096 bits are to be programmep with a 0.5 ms program pulse width.
The minimum number of program loops is 200. One program loop consists of words 0 to 1023.
Example 2:
Words 0 to 100 and 500 to 600 are to be programmed. All other bits are "don't care". The program pulse width
is 0.75 ms.
The minimum number of program loops is 133. One program loop consists of words 0 to 1023. The data entered
into the "don't care" bits shou Id be all l's.
Example 3:
Same requirements as example 2 but the PROM is now to be updated to include data for words 750 to 770.
The minimum number of program loops is 133. One program loop consists of words a to 1023. The data entered
into the "don't care" bits should be all 1 'so Addresses a to 100 and 500 to 600 must be re-programmed with their
original data pattern.
I
14-24
M2708
PROGRAM CHARACTERISTICS
TA = 25°C, Vee = 5V ±5%, V DD = +12V ±5%, VBB = -5V ±5%, Vss = OV, Unless Otherwise Noted.
D.C. Programming Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
III
Address and CS/WE Input Sink Current
10
J.i.A
IIPL
Program Pulse Source Current
3
rnA
IIPH
Program Pulse Sink Curre·nt
45
20
mA
55
mA
Test Conditions
VIN = 5.25V
Worst Case Supply Currents:
IDD
VDD Supply Current
lee
Vee Supply Current
5
8
mA
All Inputs High
IBB
VBB Supply Current
30
35
mA
CS/WE = 5V; TA = 25°C
VIL
Input Low Level (except Program)
Vss
0.65
V
VIH
Input High Level for all Addresses and Data
3.0
Ve e +1
V
V1HW
CS/WE Input High Level
11.4
12.6
V
Referenced to Vss
V1HP
Program Pulse High Level
25
27
V
Referenced to Vss
VILP
Program Pulse Low Level
Vss
1
V
V1HP - VILP = 25V min.
A.C. Programming Characteristics
Min.
Typ.
Max.
Units
Symbol
Parameter
tAS
Address Setup Time
10
J.i.S
tess
CS/WE Setup Time
10
J.i.S
tDS
Data Setup Time
10
J.i.S
tAH
Address Hold Time
1
J.i.S
J.i.S
--
teH
CS/WE Hold Time
.5
tDH
Data Hold Time
1
tDF
Chip Deselect to Output Float Delay
0
J.i.S
120
ns
10
MS
ms
tDPR
Program To Read Delay
tpw
Program Pulse Width
.1
1.0
tpR
Program Pu Ise Rise Time
.5
2.0
J.i.s
tpF
Program Pulse Fall Time
.5
2.0
MS
NOTE: Intel5 standard product warranty applies only to devices programmed to specifications described herein.
14·25
M2708
Programming Waveforms
1 - - - - - - - - - - - - 1 OF N PROGRAM lOOPS----------.f-~-READ
(AFTER N
PROG. LOOPS)
ADDRESS 0
ADDRESS 0
(.lmSMIN)
tpw
i'1.OnlSMAXJ--
PROGRAM
PULSE
vlL------"i
NOTE 1. THE CS/WE TRANSITION MUST OCCUR AFTER THE PROGRAM PULSE TRANSITION
AND BEFORE THE ADDRESS TRANSITION.
NOTE 2. NUMBERS IN ( ) INDICATE MINIMUM TIMING IN
~S
UNLESS OTHERWISE SPECIFIED.
Packaging Information
24 LEAD HERMETIC DUAL IN-LINE PACKAGE
1.220 (30.988)
I~--1.180
(29.g72)~
j
D[O
~ -=-)-
PIN 1 MARK
PIN 1
~
--1
.600 (15.24Q)
.560 (14.224)
_-.1
_~_
·
W
L-
I
-tt=
~~=--W?V --~
0.195 (4.953)
.100 {2.54J
1).140 ~
MAX.
.070 (1.7781
0.100 (2.541
t
S:~:~~G --:1OOf12540~
~~
M'N'--~l ! ~~I~
""='._
.0."."" .Lo" ••"
- -- -
.065 (1.6511
.090 (2.286)
t 0 1 5 MIN
I
(0.3811
.014 (O.356)
Printed in U.S.A.
MMC-061 10476
14-26
M2716
16K (2K x 8) UV ERASABLE PROM
Temperature Range
• Extended
- 55°C to + 100°C Operation
• Single
•
• Static Standby Mode
Low Power Dissipation of 165 mW
• max.
standby power
+ 5V Power Supply
• Fast Access Time; 450 ns max.
Inputs and Outputs TTL Compatible
• during
Read and Program
Single Programming Requirements
Single Location Programming
- Programs with One 50 ms Pulse
The Intel® M2716 is a 16,384-bit ultraviolet erasable and electrically programmable read only memory (EPROM)
specified over the - 55°C to + 100°C temperature range_ The M2716 operates from a single + 5V power supply, has a
static power-down mode, and features fast, single-address location programming_ It makes designing with EPROMs
faster, easier and more economical.
The M2716 has a static standby mode which reduces the power dissipation without increasing access time. The active
power dissipation is reduced by over 60% in the standby power mode.
The M2716 has the simplest and fastest method devised yet for programming EPROMs - single pulse TTL level programming. No need for high voltage pulsing because all programming controls are handled by TTL signals. Program
any location at any time - either individually, sequentially or at random, with the M2716's single-address location programming. Total programming time for all 16,384 bits is only 100 seconds.
MODE SELECTION
PIN CONFIGURATION
~
CE/PGM
(181
OE
(20)
Vpp
(211
Vee
OUTPUTS
(241
19-11,13-17)
MODE
07
O.
Read
V'L
V'L
+5
+5
DOUT
Standby
V,H
Don't Care
+5
+5
High Z
Program
Pulsed Vil to VIH
V,H
+25
+5
D,N
V'L
.,
V,L
+25
+5
DOUT
\1., .
+"
+,
HIQh Z
Program Verify
G~~~\.,;;:;;..'__~~~~~~
,
I
-
BLOCK DIAGRAM
Vee 0 - - - -
~
__~~~~~L-~~~~~~~
CEJPGM
PIN NAMES
ADDRESSES
CHIP ENABLE/PROGRAM
OUTPUT ENABLE
OUTPUTS
AO-AlO
ADDRESS
INPUTS
14-27
I
M2716
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section
Absolute Maximum Ratings·
TemperatureUnderBias ................ -65'Cto +110'C
'COMMENT: Stresses above those listed under "Absolute Maximl/m
Ratings" may cause permanent damage to the device. This is a stress
Storage Temperature ................... -65'C to + 125'C
All Input or Output Voltages with
Respect to Ground ....................... + 6V to - O.3V
rating only and functional operation of the device at these or any other·
conditions above those indicated in the operational sections of -this
specification is not implied. Exposure to absolute maximum rating con-
Vpp Supply Voltage with Respect
to Ground During Program .............. + 26.5V to - O.3V
READ OPERATION
D.C. and Operating Characteristics
TA = - 55 'c to + 100·C, v ee [1.2] = + 5V ±
Symbol
Parameter
ditions for extended periods may affect device reliability.
10%. Vpp[2]= VCC
Limits
Typ1I3]
Min.
Max.
Unit
Conditions
III
Input Load Current
10
ILO
I pP1 [2]
Output Leakage Current
10
JJA
JJA
Vpp Current
5
rnA
Vpp= 5.50V
lee1[2]
Vee Current (Standby)
10
30
rnA
CE = V IH • OE = V IL
lee2[2]
Vee Current (Active)
57
115
rnA
OE=CE= V IL
VIL
Input Low Voltage
0.8
V
V ee + 1
V
0.45
V
IOL = 2.1 rnA
V
IOH = -400 fJA
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
-0.1
2.0
2.4
V IN =5.50V
V ouT =5.50V
NOTES: 1. vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum ollee and IpP1 .
3. Typical values are for TA = 25'e and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
Typical Characteristics
.
..
ICC CURRENT
ACCESS TIME
ACCESS TIME
TEMPERATURE
CAPACITANCE
TEMPERATURE
,
80
70
60
r-- 1"--
50
'g"
700
500
r-- r--
30
Icc, dTANbBY
-
20
I -I - t--
-60 -40 -20
I--I -
6URR~NT
CE=VIH
Vee =5V
600
200
300
200
100
100
--r-l
0
20
40 60
TEMPERATURE (OC)
80
100
120
Vcc=5V-
f - I--
~~NT
ICC2 ACTIVE
CE"=Vll
Vee = 5V
40
u
u
10
"
800
600
o
100
200
300
400
500
C,IPFl
14·28
800
700 800
-60 -40 -20
--0
20 40 60
TEMPERATURE ('C)
",....
80
100 120
M2716
A.C. Characteristics
T A = - 55·C to + 100·C, V cc [1,21= + 5V ±
10%, V pp[21= Vcc
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test
Conditions
tACC
Address to Output Delay
450
ns
CE=OE=VIL
tCE
CE to Output Delay
450
ns
OE=V IL
tOE
Output Enable to Output Delay
150
ns
tDF
Output Enable High to Output Float
0
130
ns
eE= VIL
CE= VIL
tOH
Output Hold From Addresses, CE or
OE Whichever Occurred First
0
ns
CE=OE=V IL
Capacitance[4] T A = 25 ·C, f = 1 MHz
Symbol
Parameter
A.C. Test Conditions:
Typ.
Max.
Unit
CIN
Input Capacitance
4
6
pF
VIN=OV
Conditions
COUT
Output Capacitance
8
12
pF
VOUT= OV
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: <:;20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
Outputs
1V and 2V
0.8V and 2V
A.C. Waveforms[Sl
ADDRESSES
VALID
ADDRESSES
CE----------------4---~
tCE
(450 MAK)
5E----------------4-----------~
'-------+-. . . . . . . . . .
1----_1
tDF
(130 MAK)
[7)
OUTPUT
NOTES: 1.
........
.......
HIGH Z
3.
4.
5.
Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
'
Vpp may be connected directly to Vee except during programming. The
supply currenl would then be the sum of Icc and IpP1.
Typical values are for TA 25°C and nominal supply voltages.
This parameter is only sampled and is not 100% tested.
All times shown in parentheses are minimum and are nsec unless other-
6.
5E
2.
=
wise specified.
7.
may be delayed up 10 lAce - tOE after the falling edge of
impacl on tACC.
tOF is specified from DE or CE, whichever occurs first.
CE:
without
14·29
HIGH Z
M2716
TYPICAL 16K EPROM SYSTEM
A8_1S
AOO_7 H---''--~
ALEH----I
M8085A
RD~~
I ~
101M
• This scheme accomplished by using CE as the primary decode. OE Is now controlled by previously
unused signal. RD now controls data on and 011 the bus by way of OE.
• The use 01 a PROM as a decoder allows lor.
a) Compatibility with upward (and downward) memory expansion.
b) Easy assignment 01 ROM memory modules, compatible with PUM modular software concepts.
8K, 16K, 32K, 64K 5V EPROM/ROM FAMILY
PRINTED CIRCUIT BOARD LAYOUT
ERASURE CHARACTERISTICS
The erasure characteristics of the M2716 are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure
to room level fluorescent lighting could erase the
typical device in approximately 3 years, while it would
take approximately 1 week to cause erasure when exposed to direct sunlight. If the M2716 is to be exposed
to these types of lighting conditions for extended
periods of time, opaque labels are available from Intel
which should be placed over the M2716 window to prevent unintentional erasure.
The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instruction Section) for the
M2716 is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (I.e., UV intenSity x exposure time) for erasure
should be a minimum of 15 W-sec/CM2. The erasure time
with this dosage is approximately 15 to 20 minutes
using an ultraviolet lamp with a 12000 '"' W/cm 2 power
rating. The device should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on
their tubes which should be removed before erasure.
14-30
M2716
DEVICE OPERATION
PROGRAMMING
The five modes of operation of the M2716 are listed in
Table 1. It should be noted that all inputs for the five
modes are at TTL levels. The power supplies required
are a + 5V Vcc and a V pp. The V pp power supply must be
at 25V during the three programming modes, and must
be at 5V in the other two modes.
Initially, and after each erasure, all ·tiitsot th~M2*iliare
in the "1" state. Data is introduced by sele"'tlvely'pror.· ...·
gramming "O's" into the desired bit 10catiOn$.'A!,t~pl1,~H
only "O's" wil be programmed, both "1's" and "O'S<':.tllll.,.
be presented in the data word. The only way to change'a:.,
"0" to a "1" is by ultraviolet light erasure.
MODE SELECTION
~
CE/PGM
fiE
Vpp
Vee
(18)
(20)
(21)
(24)
The M2716 is in the programming mode when the V pp
power supply is at 25V and OE is at V1H . The data to be
programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data
inputs are TTL.
OUTPUTS
(9·11,13·17)
MODE
Read
VIL
Standby
V,H
V'L
Don't Care
Program
'5
'5
DOUT
'5
'5
HIgh Z
Pulsed VIL to VIH
V,H
+25
+5
D,N
Program Verify
V'L
V,L
+25
+5
°OUT
Program InhIbit
V'L
V,H
.25
'5
High Z
When the address and data are stable, a 50 msec, active
high, TTL program pulse is applied to the CE input. A
program pulse must be applied at each address location
to be programmed. You can progam any location at any
time - either individually, sequentially, or at random.
The program pulse has a maximum wit)dth of 55 msec.
The M2716 must not be programmed with a DC signal
applied to the CE input.
READ MODE
The M2716 has two control functions, both of which
must be logically satisfied in order to obtain dat at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable (OEl
is the output control and should be used to gate data to
the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tAccl is equal to the delay from CE to output (t cE ).
Data is available at the outputs 150 ns (tOE) after the fall·
ing edge of or, assuming that cr has been low and
addresses have been stable for at least tAcc-tOE.
Programming of multiple M2716's in parallel with the
same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of
the paralleled M2716's may be connected together when
they are programmed with the same data. A high level
TTL pulse applied to the CE input programs the paralleled M2716's.
STANDBY MODE
PROGRAM INHIBIT
The M2716 has a standby mode which reduces the active power dissipation by 75%, from 633 mW to 165 mW.
The M2716 is placed in the standby mode by applying a
TTL high special to the CE input. When in standby
mode, the outputs are in a high impedance state, inde·
pendent of the OE input.
Programming of multiple M2716's in parallel with different data is also easily accomplished. Except for CE,
all like units (including OE) of the parallel M2716's may
be common. A TTL level program pulse applied to a
M2716's CE input with V pp at 25V will program that
M2716. A low level CE input inhibits the other M2716
from being programmed.
OUTPUT OR-TIEING
PROGRAM VERIFY
Because M2716's are usually used in larger memory
arrays, Intel has provided a 2 line control function that
accommodates this use of multiple memory connections. The two line co~trol function allows for
A verify should be performed on the programmed bits to
determine that they were correctly programmed_ The
verify may be performed with V pp at 25V. Except during
programming and program verify, V pp must be at'5V.
a) the lowest possible memory power dissipation, and,
b) complete assurance that output bus contention will
not occur.
To most efficiently use these two control lines, it is recommended that cr (pin 18) be decoded and used as the
primary device selecting function, while OE (pin 20) be
made a common connection to all devices in the array
and connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low power standby mode and that the output
pins are only active when data is desired from a particular memory device.
DEVICE RELIABILITY
The M2716 is built on a proven 2 layer polysilicon NMOS
technology. Extensive testing and monitoring has allowed us to achieve failure rates equal to other memory
devices. For detailed failure rate predictions and
reliability data, request Intel 2716 Reliability Report.
14-31
inter
•
M3604A, M3624A
4K (512 x 8) HIGH·SPEED PROM
,'01 •
. t'"
, '.
•
Silicon Fuse for
• Polycrystalline
Higher Reliability
Military Temperature Range:
_55 0 C to +125 0 C
.,'
Four Chip Select Inputs for Easy
Memory Expansion
•
Collector (M3604A) or
• Open
Three-State (M3624A) Outputs
Fast Access Time -
I •••
90nsec Maximum
,
, '"
".
Packaging - 24 Pin Hermetic
• Standard
Dual In-Line Lead Configuration
The M3604A and M3624A are military temperature range PROMs organized as 512 words by 8 bits. They are manufactured with all outputs high and logic output low levels can be electrically programmed in selected bit locations. The
M3604A and M3624A, except for programming, have the same electrical specifications and are direct replacements to
their predecessors, the M3604 and M3624.
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS·
LOGIC SYMBOL
Temperature Under Bias ........... _65°C to +135 C
Storage Temperature . . . . . . . . . . . . . -65°C to +160°C
Output or Supply Voltages .. . . . . . .. -O.5V to 7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . -1.6V to 5.6V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . IOOmA
",
"',
a,
a,
..
0,
0,
"
0,
A,
0,
....
.."
Symbol
0,
0,
A,
A,
D.C. CHARACTERISTICS
0,
·COMMENT
Stresses above those listed IInder "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
0,
Vee = +5.0V ±10%, T A = -55°C to +125°C
Parameter
Min.
limits
Typ,[,l
Max.
Unit
IFA
Address Input Load Current
-0.05
-0.25
mA
IFS
Chip Select Input Load Current
-0.05
-0.25
mA
IRA
Address Input Leakage Current
40
IRS
Chip Select Input Leakage
Current
40
fJ.A
fJ.A
Test Conditions
Vee = Max, VA=0.45V
Vee= Max, Vs =0.45V
Vee- Max, VA- Max
Vee= Max, Vs= Max
VeA
Address Input Clamp Voltage
-0.9
-1.5
V
Ves
Chip Select Input Clamp
Voltage
-0.9
-1.5
V
VOL
Output Low Voltage
0.3
0.45
V
leEx
Output Leakage Cu rrent
100
leel
Power Supply Current (M3604A)
190
fJ.A
mA
VIL
Input "Low" Voltage
0.8
V
Vee= 5.0V, TA=25°C
VIH
Input "High" Voltage
V
Vee= 5.0V, TA=25°C
2.0
Vee = Min, IA=-lOmA
Vee = Min, 15= -lOmA
Vee = Min, 10L = 10mA
Vee= Max, VeE = Max
Veel = Max, VAO-+VAS=OV,
CS, =CS2=OV,CS3=CS4= 5.5V
M3624AONLY
Symbol
Parameter
1101
Output Leakage for High
Impedance Stage
Ise[21
Output Short Circuit Current
VO H
Output High Voltage
Min.
-20
Typ.[ll
-25
Max.
Unit
Test Conditions
100
fJ.A
VO= Max or 0.45V,
Vee= Max, CS, = CS 2 = 2.4V
-80
mA
V
2.4
NOTES: I. Tvpical values are at 25° e and at nominal voltage.
2. Unmeasured outputs are open during this test.
14-32
Vo =OV
10H =-2.4mA, Vee = 5V
)': '~
M3604A, M3624A
A.C. CHARACTERISTICS
Vee ~ +5.0V ±10%. T A ~ -55°C to +125°C
LIMITS
SYMBOL
PARAMETER
UNIT
Typ.[1]
MAX.
Address to Output Delay
60
90
ns
t5++
Ch ip Select to Output Delay
20
45
ns
t5 __
Chip Select to Output Delay
20
45
ns
tA++. tA __
tA+_. tA_+
CAPACITANCE [2] TA = 25°C. f ~
CONDITIONS
CS1
= CS2 = VIL and
CS3 = CS4 = VIH to
Select the PROM
1 MHz
LIMITS
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
TEST CONDITIONS
C INA
Address Input Capacitance
4
10
pF
Vee ~ 5V
C INS
Chip·Select I nput Capacitance
6
10
pF
Vee
NOTES:
7
Output Capacitance
COUT
pF
15
Vee
~
~
VIN~2.5V
~
5V
VIN
5V
VOUT
2.5V
~
2.5V
1. Typical values are at 2SoC and nominal voltage.
2. This parameter is only periodically sampled and is not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test:
Input pulse amplitudes - 2.5V
Input pulse rise and fall times of
5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 10 mA and 30 pF
Frequency of test - 2.5 MHz
10 rnA TEST LOAD
td':::
WAVEFORMS
CHIP SELECT TO OUTPUT DELAY
ADDRESS TO OUTPUT DELAY
ADDRESS
I
i~v
15~
ro
\
f,.5V
\
I
es 3 • es.
OUTPUT
t A++
15~
tA __
OUTPUT
OUTPUT
ts __
t A+_
tA~+
14·33
ts++
M3625A
4K (1Kx4) PROM
•
• Three·State Outputs
:t 10% Power Supply Tolerance
• Polycrystalline Silicon Fuse for Higher
Reliability
• Fast Access Time: 60 ns Maximum
• Lower Power Dissipation: 0.14mW/Bit
Typically
• Hermetic 18·Pin DIP
• Simple Memory Expansion Two Chip
Select Inputs
The Intel® M3625A is a high density, 4096-bit bipolar PROM organized as 1024 words by 4 bits. The 1024 by 4 organization gives ideal word or bit modularity for memory array expansion. The M3625A is fully specified over the -55°C to
125 'C temperature range with ± 10% power supply variation.
The M3625A is packaged in an 18-pin dual-in-line hermetic package with 300 milli-inch centers. Thus, twice the bit
density can be achieved in the same memory board areas as 512 by 8-bit PROMs in 24-pin packages.
The highly reliable polycrystalline silicon fuse technology is used in the manufacturing of the M3625A. All outputs are
initially a logical high and logic low levels can be electrically programmed in selected bit locations.
PIN CONFIGURATION
BLOCK DIAGRAM
~
~
W
~
~
0
0
~-
64 X 64 ARRAY
1!
~-
~
~
~
LOGIC SYMBOL
W
0
~
0
~-
CS,
CS2
Ao
A,
A,
A,
A,
A,
A,
A,
A,
As
~o
:!!
~;:,
.....
0,
I
_xffi
~5
:.
"
OUTPUT
BUFFER
I
0,
ADDRESS INPUTS
CHIP SELECT INPUT
OUTPUTS
14-34
I
>-~
0,
PIN NAMES
I
OW
0,
0,
I
I
0,
I
0,
I
0,
M3625A
PROGRAMMING
The programming' specifications are described in the Data Catalog PROM/ROM Programming InstructIOns.
Absolute Maximum Ratings·
'COMMENT
Temperature Under Bias ................ -65·Cto +135·C
StorageTemperature ................... -65·Cto + 160·C
Output or Supply Voltages .................... - 0.5 V to 7V
All Input Voltages .......................... -1V to 5.5 V
Output Currents ................................ 100mA
D.C. Characteristics:
Stresses above those listed under "Absolute MaximUm
Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in the
operational sections of this specification is not implied.
All limits apply for Vee = +5.0V±10%, TA = -55·C to +125·C, unless otherwise
specified.
Limits
Symbol
Parameter
Typ.l']
Max.
Unit
Test Conditions
IFA
IFS
Address Input Load Current
-0.05
-0.25
mA
Vee = 5.5V, VA = 0.45V
Chip Select Input Load Current
-0.05
-0.25
mA
IRA
Address Input Leakage Current
40
Jl.A
Vee =5.5V, Vs=0.45V
Vec = 5.5V, VA = 5.5V
IRS
Chip Select Input Leakage
Current
40
Jl.A
Vee =5.5V, Vs =5.5V
\10\
Output Leakage for High
Impedance Stage
40
Jl.A
Vo=5.5Vor~5V_,_
Vec =5.5V, CS1 = CS 2 =2.4V
Isc'''
VeA
Output Short Circuit Current
-35
-80
mA
Vo=OV
Address Input Clamp Voltage
-0.9
-1.5
V
Ves
Chip Select Input Clamp
Voltage
-0.9
-1.5
V
VOH
Output High Voltage
VOL
Output Low Voltage
0.3
0.45
V
Icc
Power Supply Current
110
140
mA
VIL
VIH
Input "Low" Voltage
0.85
V
TA =25·C
V
TA =25·C
Input "High" Voltage
Min.
-20
2.4
V
2.0
NOTES:
1. Typical values are for TA =25"C and nominal supply vOltages.
2. Unmeasured outputs are open during this test.
14·35
Vec =4.5V, IA= -10mA
Vee =4.5V, Is= -10mA
10H= -2.4mA, Vee =4.5V
Vec =4.5V,l oL =10mA
Vec =5.5V, VAO '" VA9=OV,
CS 1 = CS 2 = VIH
M3625A
A.C. Characteristics:
Symbol
Vee = +5.0V±10%, TA = -55·Cto +125·C.
Parameter
Max.
Limits
Unit
tA++, tA __
tA+_, tA-+
Address to Output Delay
60
ns
ts++
Chip Select to Output Delay
35
ns
ts-_
Chip Select to Output Delay
35
ns
.
Capacitance
1
Conditions
CS1 = CS2 = VIL
to select the
PROM.
TA = 25 ·C, f = 1 MHz.
Limits
Symbol
Parameter
Typ.
Max.
Unit
3
8
pF
Vee=5V
VIN =2.5V
Test Conditions
CINA
Address Input Capacitance
CINS
Chip Select Input Capacitance
4
8
pF
Vee=5V
VIN =2.5V
COUT
Output Capacitance
5
10
pF
Vee=5V
VOUT=2.5V
NOTES:
1. This parameter is only periodically sampled and Is not 100% tested.
Switching Characteristic,s
Conditions of Test:
Input pulse amplitudes - 2.5V
Input pulse rise and fall times of
5 nanoseconds between 1 V and 2V
Speed measurements are made at 1.5V levels
Output loading - 10mA and 30pF
Frequency of test - 2.5 MHz
10mATEST LOAD
vee
~470Q
~
~lkQ
Waveforms
ADDRESS TO OUTPUT DELAY
CHIP SELECT TO OUTPUT DELAY
ADDRESS
CSl.~
INPUT
1.SV
OUTPUT
OUTPUT
OUTPUT
ts __
14-36
M3636
16K (2K x 8) BIPOLAR PROM
• - 55°C to + 125°C Operation
• Fast Access Time: 80 ns Maximum
• Low Power Dissipation: 0.05 mW/Bit
Typically
• Hermetic 24·Pin DIP
• Three Chips Select Input for Easy
Memory Expansion
• Polycrystalline Silicon Fuses for
Higher Fuse Reliability
• Pin Compatible to 8K PROMs
• Three·State Outputs
The Intel® M3636 is a fully decoded 16,384 bit PROM organized as 2048 words by 8 bits. The worst case access time of
80 ns is specified over the - 55°C to + 125°C temperature range and 5% Vcc power supply tolerances. There are three
chip selects provided to facilitate expansion into larger PROM arrays. The PROMs use the Schottky clamped TTL technology with polycrystalline silicon fuses. All outputs are initially high and logic low levels can be electrically programmed in selected bit locations.
Prior to the 16,384 bit M3636, the highest density bipolar PROM available was 8196 bits. The high density of the M3636
now easily doubles the capacity without an increase in area on existing designs currently using 1024 by 8-bit PROMs.
There is also little, if any, penalty in power since the power/bit is approximately one-half that of 8K PROMs. The M3636
is packaged in a hermetic 24-pin dual in-line package.
BLOCK DIAGRAM
PIN CONFIGURATION
DATA OUT 1
Vee
es,
es,
e",
Ao
°3
0,
es,
es,
A,
0"
A,
0,
eS3
'"
~
A8
cs,-
A,
CS2eS3 -1"--_-;--_-'
Al0 (MSB)
17
LOGIC SYMBOL
DATA OUT 8
0 8 (MSB)
PIN NAMES
AO
ADDRESS
AlO
cst. CSz, CS3
01
[11
INPUT~
CHIP SELECT INPUTS!l]
-os
DATA OUTPUTS
--
To select the PROM CS, '" V1L
and CS2 = CS3 '" VIH
14-37
0,
0,
M3636
PROGRAMMING
The programmIng specifications are described in the PROM/ROM Programming section of the Data Catalogue.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ........... - 65°C to + 125°C
Storage Temperature ............. - 65°C to + 160°C
Output or Supply Voltages ........... - 0.5V to 7 Volts
All Input Voltages ...................... -1V to 5.5V
Output Currents ........................... 100 mA
'Comment: Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at any other
condition above those indicated In the operational sections of this
specification Is not implied.
D.C. CHARACTERISTICS
All Limits Apply for Vee =
+ 5.0V ± 5%, TA = - 55°C to 125°C unless otherwise specified
limits
Typ.l11
Max.
Unit
IFA
Address Input Load Current
-0.05
-0.25
mA
Vee = 5.25V, VA = 0.45V
IFS
Chip Select Input Load Current
-0.05
-0.25
mA
Vee = 5.25V, Vs = 0.45V
Symbol
Parameter
Min.
Test Conditions
IRA
Address Input Leakage Current
40
/AA
Vee = 5.25V, VA = 5.25V
IRS
Chip Select Input Leakage
Current
40
/AA
Vee=5.25V, Vs=5.25V
1101
Output Leakage for High
Impedance State
100
/AA
Vo = 5.25V or 0,45V,
Vee = 5.25V, CSt = 2.4V
Isell ]
Output Short Circuit Current
-35
-80
mA
Vo=OV
VeA
Address Input Clamp Voltage
-0.9
-1.5
V
Vee = 4.75V, IA= -10 mA
Ves
Chip Select Input Clamp
Voltage
-0.9
-1.5
V
Vee = 4.75V, Is= -10 mA
-20
2,4
VOH
Output High Voltage
VOL
Output Low Voltage
0.3
150
Icc
Power Supply Current
Vil
Input "Low" Voltage
VIH
Input "High" Voltage
3.0
2.0
Notes:
1. Typical values are for TA = 25'e and nominal supply voltages.
2. Unmeasured outputs are open during this test.
14·38
V
10H= -2.4 mA, Vee=4.75V
0.45
V
Vee = 4.75V, 10l = 10 mA
185
mA
0.85
V
Vee = 5.0V± 5%, TA = 25°C
V
Vee= 5.0V± 5%, TA = 25°C
Vee=5.25V
A.C. CHARACTERISTICS
Vee= ± 5 ± 5%, TA = -55°C to 125°C
···L.~,
SYMBOL
PARAMETER
MAX. LIMITS
UNIT
CONDITIONS
TA
Address to Output Delay
80
ns
tEN
Output Enable Time
50
ns
tOIS
Output Disable Time
50
ns
CS 1 =V IL
and CS 2 = CS 3 = V IH
to select the PROM,
CAPACITANCE (11 TA ~ 25°C, f ~
1 MHz
PARAMETER
SYMBOL
TYP. LIMITS
TYP.
MAX.
UNIT
TEST CONDITIONS
CINA
Address I nput Capacitance
4
10
pF
Vce = 5V
V IN = 2.5V
CINS
Chip·Select Input Capacitance
6
10
pF
Vee = 5V
VIN
CO UT
Output Capacitance
7
12
pF
Vee = 5V
VOUT
NOTE1: This parameter
IS
":"i
~
2,5V
~
2,5V
only periodically sampled and ;s not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test:
Input pulse amplitudes· 2,5V
Input pulse rise and fall times of
5 nanoseconds between 1 volt and 2 volts
Speed measurements are made at 1.5 volt levels
Output loading is 10 mA and 30 pF
Frequency of test - 2,5 MHz
10 rnA TEST
LOA~D
Vcc
470n
30pF
1K
n
WAVEFORMS
CHIP SELECT TO OUTPUT DELAY
ADDRESS TO OUTPUT DELAY
cs, - - -......
ADDRESS
INPUT
cs, ,cs,, _ _ _...J
OUTPUT
OUTPUT
tA
tEN
OUTPUT
t
tA
A
_
14-39
' -_ _ _ _ _ _....J ' -_ _
.:1
Intel
M5101-4, M5101L-4
256 x 4 BIT STATIC CMOS RAM
Temperature Range:
• Military
-55°C to +125°C
•
• Fast Access Time -
• Single +5V Power Supply
Controls Unconditional
• CE2
Standby Mode
Ultra Low Standby Current: 200nA/Bit
• Three-State Output
800ns
The Intel® M5101 is an ultra-low power 256 X 4 CMOS RAM specified over the _55°C to +125°C temperature range. The RAM
uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. When deselected with CE2 low, the
M5101 draws from the single 5-volt supply only 200 microamps at 125°C.
The Intel® M5101 is fabricated with an ion-implanted, silicon gate, Complementary MOS (CMOS) process. This technology allows
the design and production of ultra-low power, high performance memories.
PIN CONFIGURATION
lOGIC SYMBOL
5101
5101
A,
'cc
A,
A,
ABSOLUTE MAXIMUM RATINGS*
A"
A,
Ambient Temperature Under Bias.
. _65°C to 135°C
Storage Temperature
-65 Q C to +150°C
A,
A,
Voltage On Any Pin
With Respect to Ground.
A,
'"
A,
-O.3V to Vee +O.3V
A,
A,
A.
A,
DO,
A,
Maximum Power Supply Voltage
+7.0V
Power Dissipation
1 Watt
00,
D',
DI!
D',
DD,
c.,
DO,
D',
"'.
D',
DO,
ce, -
·COMMENT.
DO,
ce,
Stresses above those listed under "Absolute Maximum
Ratlng l l may cause permanent damage to the deVice. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN NAMES
01,
A,
01.
_,...,
AIW
OA,TA,INPUT
A,DDAtSS INPUTS
00,- 004 DATA OUTPUT
,HAQ . WAITE 'NPUT
D.C. AND OPERATING CHARACTERISTICS FOR M5101-4, M5101L-4
TA = -55°C to 125°C, VCC = 5V ±5% unless otherwise specified.
Symbol
Parameter
Typ.[1)
Max.
Unit
nA
VIN = 0 to 5.25V
Output High Leakage
2
I1A
CE 1 = 2.2V, VOUT = Vcc
I l o l [2)
Ou tpu t Low Leakage
2
I1A
CE 1 = 2.2V, VOUT=O.OV
ICCl
Operating Current
11
25
mA
VIN = Vcc Except CE 1 «0.01 V
Outputs Open
ICC2
Operating Current
20
32
mA
VIN =2.2V Except CE 1 «0.5V
Outputs Open
ICCl [2)
Standby Current
2
200
I1A
VIN =0 to Vcc, Except
CE2 « 0.2V
V il
Input "Low" Voltage
-0.3
0.5
V
V IH
Input "High" Voltage
Vcc-2.O
Vce
V
VOL
Output "Low" Voltage
VO H
Output "H igh" Voltage
I U[2)
Input Current
ILOH I2 )
Min.
8
0.4
Vcc- 2.O
NOTES: 1. Typical values are T A = 25°C and nominal supply voltage.
14-40
Test Conditions
V
IOl = 2.0mA
V
IOH = 1.0mA
2. Current through all inputs and outputs included in ICCl-
M5101-4, M5101L-4
Low VCC Data Retention Characteristics (For M5101L-4) TA = -55°C to 125°C
Symbol
Parameter
Vcc for Data Retention
VO R
Typ. [11
Min.
Max.
Unit
'.'"
Test Conditions
V
2.0
"
.....
2
ICCOR
Data Retention Current
tCOR
Chip Deselect to Data Retention
Time
tR
Operation Recovery Time
NOTES:
200
I1A
VOR =2.0V.
ns
0
tRC[21
ns
1. Typical values are T A = 25°C and nominal supply voltage.
2. tRC = Read Cycle Time.
A.C. CHARACTERISTICS FOR M5101-4, M5101L-4
READ CYCLE
TA = -55°C to 125°C, VCC = 5V ±5%, unless otherwise specified.
Symbol
Parameter
Min.
Read Cycle
Typ.
Max.
Unit
Test Conditions
ns
tRC
tA
Access Time
800
tCOl
Chip Enable (CE1) to Output
700
ns
tC02
Chip Enable (CE2) to Output
850
ns
too
Output Disable To Output
tOF
Data Output to High Z State
0
350
150
ns
tOHl
Previous Read Data Valid with
Respect to Add ress Change
0
ns
tOH2
Previous Read Data Valid with
Respect to Chip Enable
0
ns
800
ns
(See below)
ns
WRITE CYCLE
Symbol
L
Parameter
Typ.
Min.
twc
Write Cycle
800
Max.
Unit
tAW
Write Delay
150
nS
Chip Enable (CE1) To Write
550
ns
tCW2
Chip Enable (CE2) To Write
550
ns
tow
Data Setup
400
ns
tOH
Data Hold
100
ns
twp
Write Pulse
400
:>u
tWR
tos
I Write Recovery
1
Output Disable Setup
Input Pulse Levels:
1
I
I
\I>
I
[31
TA = 25°C, f = 1 MHz
0.5 Volt to Vcc-2.0 Volt
20 nsec
Timing Measurement Reference Level:
1 TTL Gate and CL
1.5 Volt
=
Symbol
CIN
CcUT
NOTE: 3. This parameter is periodically sampled and is not 100% tested.
14-41
Limits (pF)
Test
I nput Capacitance
(All Input Pins) V IN
100pF
I
ns
CAPACITANCE
Input Pulse Rise and Fall Times:
Output Load:
(See below)
ns
150
A. C. CONDITIONS OF TEST
Test Conditions
ns
tCWl
= OV
Output Capacitance VOUT = OV
Typ.
Max.
4
8
8
12
':'....
..
CE2 '::0.2V
'
1:\\
M5101-4, M5101L-4
WAVEFORMS
WRITE CYCLE
~----------_IRC-------------I
I-------------WC------------~
ADDRESS
ADDRESS
CE2
CE2
oo---'f---.,.
00
(COMMON 1/0) [,]
(COMMON 1/01 [2]
lOS
DATA
DATA
OUT
IN
DATA-IN
STABLE
- - - . - , I~-------Iwp------..j
R·W
NOTES: 1. 00 may be tied low for separate I/O operation.
2. During the write cycle, 00 is "high" for common I/O and
"don't care" for separate I/O operation.
Low Vcc Data Retention
SUPPLY VOLTAGE (Vee)
G)
4.75V
®
VOR
@
O.2V
®
CHIP ENABLE (CE2)
w--~-------------
14-42
VIH
,._;;.;;.._+-_
intel®
M8080A
8·BIT N·CHANNEL MIRCOPROCESSOR"
.
The M8080A is functionally compatible with the Inteflll8080.
• Fully Military Temperature Range
- 55°C to + 125°C
• :t 10% Power Supply Tolerance
• 2 /As Instruction Cycle
• Powerful Problem Solving Instruction
Set
• 6 General Purpose Registers and an
Accumulator
• 16·Bit Program Counter for Directly
Addressing up to 64K Bytes of
Memory
'"."
• 16·Bit Stack Pointer and Stack
"
Manipulation Instructions for Rapid
, (:'
Switching of the Program Environment
• Decimal, Binary, and Double Precision
Arithmetic
• Ability to Provide Priority Vectored
Interrupts
• 512 Directly Addressed 1/0 Ports
• TTL Drive Capability
The Intel® M8080A is a com·plete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using
Intel's n·channel silicon gate MOS process. This offers the user a high performance solution to control arid processing
applications.
The M8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose registers
may be addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical
instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic operation.
The M8080A has an external stack feature wherein any portion of memory may be used as a last inlfirst out stack to
store Iretrieve the contents of the accumulator, flags, program counter and all of the 6 general purpose registers. The
16-bit stack pointer controls the addressing of this external stack. This stack gives the M8080A the ability to easily
handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost
unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8·line bidirectional
data busses are used to facilitate easy interface to memory and 1/0. Signals to control the interface to memory and 1/0
are provided directly by the M8080A. Ultimate control of the address and data busses resides with the hold signal. It
provides the ability to suspend processor operation and force the address and data busses into a high impedance
state. This permits OR·tying these busses with other controlling device for (OMA) direct memory access or multiprocessor operation.
BLOCK DIAGRAM
°7- DO
BI-DIRECTIONAL
DATA BUS
(8 BIT)
INTERNAL DATA BUS
REGISTER
ARRAY
(16)
PROGRAM COUNTER
TIMING
AND
POWER1-
SUPPLIES
_
CONTROL
+12V
+5V
_-5V
_GND
11,5 - "0
ADDRESS BUS
14-43
M8080A
INSTRUCTION SET
The accumulator group instructions include arithmetic and
logical operators with direct, indirect, and immediate addressing modes.
increment and decrement memory, the six general registers
and the accumulator is provided as well as extended increment and decrement instructions to operate on the register
pairs and stack pointer. Further capability is provided by
the ability to rotate the accumulator I!!ft or right through
or around the carry bit.
Move, load, and store instruction groups provide the ability
to move either 8 or 16 bits of data between memory, the
six working registers and the accumulator using direct, indirect, and immediate addressing modes.
Input and output may be accomplished using memory addresses as I/O ports or the directly addressed I/O provided
for in the M8080A instruction set.
The ability to branch to different portions of the program
is provided with jump, jump conditional, and computed
jumps. Also the ability to call to and return from sub·
routines is provided both conditionally and unconditionally.
The RESTART (or single byte call instruction) is useful for
interrupt vector operation.
The following special instruction group completes the
M8080A instruction set: the NOP instruction, HALT to stop
processor execution and the DAA instructions provide decimal arithmetic capability. STC allows the carry flag to be directly set, and the CMC instruction allows it to be complemented. CMA complements the contents of the accumulator
and XCHG exchanges the contents of two 16·bit register
pairs directly.
Double precision operators such as stack manipulation and
double add instructions extend both the arithmetic and
interrupt handling capability of the M8080A. The ability to
Data and Instruction Formats
Data in the M8080A is stored in the form of 8-bit binary integers. All data transfers to the system data bus will be in the
same format.
ID7
D6 D5 D4 D3 D2 D, Dol
DATA WORD
The program instructions may be one, two, or three bytes in length. MUltiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particular operation
executed.
One Byte Instructions
TYPICAL INSTRUCTIONS
I D7
Register to register, memory reference, arithmetic or logical, rotate,
return, push, pop, enable or disable
Interrupt instructions
D6 D5 D4 D3 D2 DlYOJ OPCODE
Two Byte Instru·ctions
ID7
ID7
I OP CODE
Do I OPERAND
D6 D5 D4 D3 D2 D, Do
D6 D5 D4 D3 D2 D,
Immediate mode or I/O instructions
Three Byte Instructions
I D7
I D7
I D7
06 D5 D4 D3 D2 D, Do
OP CODE
D6 D5 D4 D3 D2 D, Do
LOW ADDRESSOR OPERAND 1
D6 D5 D4 D3 D2 D, DO
I HIGH ADDRESSOR OPERAND 2
Jump, call or direct load and store
instructions
For the M8080A a logic "1" is defined as a high level and a logic "0" is defined as a low level.
14-44
M8080A
ABSOLUTE MAXIMUM RATINGS·
,\1
.',,'1"
,
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the' device.
This is a stress rating onlv and functional operation of the' qevice at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Temperature Under Bias . . . . . . . . . . . .. -55°C to +125°C
Storage Temperature. . . . . . . . . .
-65°C to +150°C
All Input or Output Voltages
With Respect to Vss . . . . . . . . . . . . . . -0.3V to +20V
Vcc, V DD and Vss With Respect to Vss
-0.3V to +20V
Power Dissipation ....
. . . . . . . . . . . .. 1.7W
D.C. CHARACTERISTICS
TA = _55°C to +125°C, VDD = +12V ±10%, Vcc = +5V ±10%, Vss = -5V ±10%, Vss = OV, Unless Otherwise Noted.
Symbol
Parameter
Typ.
Min.
Max.
Unit
Vss+0.8
V
VILC
Clock Input Low Voltage
VIHC
Clock Input High Voltage
8.5
V DD +1
V
V IL
Input Low Voltage
Vss-1
Vss+0.8
V
V IH
Input High Voltage
3.0
Vcc+1
V
VOL
Output Low Voltage
0.45
V
V OH
Output High Voltage
Vss-1
3.7
Test Condition
} IOL
IOH
V
IDD IAV)
Avg. Power Supply Current (V DD )
50
80
mA
ICCIAV)
Avg. Power Supply Current (VccI
60
100
mA
Iss IAV)
Avg. Power Supply Current (V ss )
.01
1
mA
= 1.9mA on all outputs,
= 1501lA.
} 0 PO'" '00
T Cy
=
.48 Ilsec
IlL
Input Leakage
±10
Il A
Vss ,;;: VIN ,;;: VCC
ICL
Clock Leakage
±10
Il A
Vss ,;;: VCLOCK ,;;: VDD
IDL [21
Data Bus Leakage in Input Mode
-100
-2.0
Il A
mA
VSS';;:VIN ';;:VSS +0.8V
+10
-100
Il A
I
IFL
Address and Data Bus Leakage
During HOLD
Vss +0.8V';;:VIN ';;:VCC
VADDR/DATA
V ADDR/DATA
= VCC
= VSS + 0.45V
CAPACITANCE
VCC
= VDD = VSS = OV, Vss = -5V
t-
~
Symbol
Parameter
Typ.
Max.
Unit
Test Condition
a:
a:
::>
u
C",
Clock Capacitance
17
25
pf
fc
CIN
I nput Capacitance
6
10
pf
Unmeasured Pins
COUT
Output Capacitance
10
20
pf
Returned to Vss
= 1 MHz
~
~
0.51-------+-------"\
ill
+1?1'>
NOTES:
AMBIENT TEMPERATURE (OC}
1. The RESET signal must be active for a minimum of 3 clock cycles.
2. When DSIN is high and VIN > VIH an internal active pull up will
be switched onto the Data Bus.
3. ill supply lilT A = -0.45%f c.
Figure 1. Typical Supply Current vs.
Temperature, Normalized[3)
Figure 2. Data Bus Characteristic During
DBIN
14·45
M8080A
A.C. CHARACTERISTICS
TA
~ _55°C to +125°C, Voo ~ +12V ±1 0%, VCC ~ +5V ±10%, VBB ~ -5V ±1 0%, VSS ~ OV, Unless OtherWise1'~~t;;d.
Symbol
Parameter
Min.
Max.
Unit
O.4B
2.0
j1sec
0
50
nsec
tCy[31
Clock Period
t r , tf
Clock Rise and Fall Time
t1
1>1 Pulse Width
60
nsec
t2
¢2 Pulse Width
220
nsec
t01
Delay 1>1 to 1>2
0
n sec
nsec
t02
Delay 1>2 to 1>1
BO
t03
Delay 1>1 to 1>2 Lead ing Edges
BO
tOA [21
Address Output Delay From 1>2
200
nsec
too [21
Data Output Delay From 1>2
220
nsec
toc [21
Signal Output Delay From 1>1, or 1>2 (SYNC, WR,WAIT, HLOAI
140
nsec
tOF [21
DBIN Delay From 1>2
150
nsec
tOF
nsec
Delay for Input Bus to Enter Input Mode
tOS1
Data Setup Time During ¢1 and DB IN
WAVEFORMS[14]
,
"-"'in
~ \,, l
.U,.,
"t,~, \';~\~ ,:,
.,
nsec
25
tOI[1]
Test ConditiBri''''."",
l~ ~50pf
nsec
30
(Note: Timing measurements are made at the following reference voltages: CLOCK "1" ~ 7.0V,
"0" = 1.0V; INPUTS "1" ~ 3.0V, "0" = O.BV; OUTPUTS "1" = 2.0V, "0" = O.BV.)
,'--_---Jl\\--__
r---\,1'-1-+~
~-+--...J'I
11
-A1S"A O
---lOA
I
1.
-too'--I
°7"°0
SYNC
DBIN
READY
-
-
I
1---
tOI
--.~~-----+--~
I
I -~:
- - - - - - --"t"-
..r-----_t--"'\
-r
_ tocrl_
Iii
I
---:1'
-t -- -- __ J! ---1+f---+----,f.-·tAW --1+-4--1
t OH \ -
I
-'F"'-+-- --1DATA IN
~
-\-
-..- toe
,
-
_~
tOSl 1-
~tDD~~--+-~~---*~
~
-"1 1---- I- tow ~
,I
DATA OUT
---
-1
-.-10S2 -
1---
t~---+----'.\.'
------------------t_-to-,-J:II
_to,-~ll~--t-----~--r-+-il----~~
~"~
- .l@
.r
toe I~_l
---------------------------~lH:..~--.:..lt.:.o~-+.J1_~ t:__ .1:-tRsl~
WAIT
II
1
tRS
~I
HOLD ______________________________________________________________________JtI,,@*~I--~~
~r~H; -HLDA
----------------------------------------------------------~~
-
INT
-..1.--
I ....
Jt@ ~
-----------------------------------------------tl~sl:
-
tH - - .
INTE
14-46
...
M8080A
A.C. CHARACTERISTICS (Continued)
TA = -55°C to +125°C, voo = +12V ±10%, Vee =+5V
Symbol
'I"~
;,\,(' 1\\\:<'
±10%, VBB
= -5V ±10%, vss = OV, Unless Otherwise Not~J~
Min.
Parameter
tOS2
Data Setup Time to 4>2 During DBIN
tOH [1J
Data Hold Time From 4>2 During DBIN
Max.
Unit
130
nsec
[1]
nsec
tiE [2J
INTE Output Delay From 4>2
tRS
READY Setup Time During 4>2
120
nsec
tHS
HOLD Setup Time to 4>2
140
nsec
tiS
INT Setup Time During 4>2
120
nsec
tH
Hold Time From 4>2 (READY, INT, HOLD)
0
nsec
tFD
Delay to Float During Hold (Address and Data Bus)
tAW[2J
Address Stable Prior to WR
[5J
tDW[2J
Output Data Stable Prior to WR
[6J
nsec
tWD[2J
Output Data Stable From WR
[7J
nsec
tWA[2J
Address Stable From WR
[7J
nsec
tHF[2J
HLDA to Float Delay
[8J
nsec
tWF [2J
WR to Float Delay
[9J
nsec
tAH [2J
Address Hold Time After DBIN During HLDA
-20
nsec
200
Test Condition
L~"
\i""ii:!~,:;~;:~;
nsec
CL = 50pf
nsec
130
nsec
-
_ CL =50pf
-
NOTES,
1. Data Input should be enabled with D81N status. No bus conflict can then occur and data hold time IS assured.
tOH == 50 ns or tOF, whichever IS less,
2. Load Circuit.
+5V
2.1K
M8080A
OUTPUT
--
*---+-----+--'
--
.*"--4-----!-'-
3. tCY:: t03 + trcp2 + tct>2 + tfcP2 + t02 + treP1 ;. 480ns.
TYPICAL
CBIN
-- ~".,-
~tol
-20.........
-100
UADY
'
+50
-50
I
+100
4. The following are relevant when interfacing the M8080A to devices having VIH == 3.3V:
....
~
HLOA
toc
-
....
.... t
INTE
CAPACITANCE
(CACTUAL - C SPEC )
-tHF-
.NT
~
..:> CAPACITANCE (pf)
WAIT
HOLD
OUTPUT DELAY VS.
I:~I~
SYNC
WR
~
IE
_
l_-___
J--__
al Maximum output rise time from .BV to 3.3V "" 100ns@ CL "" SPEC .
bl Output delay when measured to 3.0V '" SPEC +60ns @ CL "" SPEC.
cl If CL oF SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL
5. tAW = 2 tCY -t03 -t r 4J2 -140nsec.
6. tow'" tCY -t03 -t r4J2 -1 70nsec.
7. If not HLDA, two"" tWA == t03 + tr4J2 +10ns If HLoA, two == tWA == tWF.
< CSPEC.
B. tHF == t03 + trrJ>2 -50ns .
9. tWF == t03 + trlJl2 -10ns
10. Data in must be stable for this period during DBIN ·T3. Both tOS1 and t052 must be satisfied.
11. Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)
12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and dUring T3, T 4, T 5
and TWH when in hold mode. (External synchronization IS not required,)
13. Interrupt signal must be stable during thiS period of the last clock cycle of any instruction 10 order to be
recognized on the following instruction. (External synchrOnization is not reqUired.)
14. This timing diagram shows timing relationships only; It does not represent any specific machine cycle.
14·47
M8212
8-BIT INPUT/OUTPUT PORT
• Fully Parallel 8-Bit Data Register and
Buffer
• 3.4V Output High Voltage for Direct
Interface to M8080A CPU
• Service Request Flip-Flop for Interrupt
Generation
• Asynchronous Register Clear
• Replaces Buffers, Latches, and Multiplexers in Microcomputer Systems
• Low Input Load Current 0.25mA Max
• Reduces System Package Count
• 3-State Outputs
• Full Military Temperature Range
-55°C to +125°C
• ±10% Power Supply Tolerance
• 24-Pin Dual In-Line Package
The Intel@ M8212/M3212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and
device selection logic. Also included is a service request flip-flop for the generation and control of interrupts to the
microprocessor.
The device is multi mode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the
principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
• Note: The specifications for the M3212 are identical with those for the M8212.
LOGIC DIAGRAM
PIN CONFIGURATION
SERVICE REQUEST FF
'\
os,
MD
01,
Dis
DO,
DOs
01 2
01,
00 2
DO,
Oi,
01 6
00 3
00 6
01.
01.
DO.
DO.
STa
CLR
GND
05 2
---+1H_~
[I)
MO
[IT>
STS ~--+---f._J
BUFFER
DO,@>
~lJl4
--------'-H
PIN NAMES
Oll- ola
DATA IN
00,·00,
DATA OUT
os,·OS2
DEVICE SELECT
MO
MODe
STB
INT
CLR
STROBE
OUTPUT
[§> 0 's - - - - - - - + - H
129 0 '6 - - - - - - - - , - - H
INTERRUPT (ACTIVE LOW)
CLEAR (ACTIVE LOW)
~
0', - - - - - - - + - H
§> D'a - - - - - - - . . L - H
14-48
M8212
'COMMENT: Stresses above those ji~tIId,UlJder "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions 1ib0'fll!
those indicated in the operational sections of this specifi- '"
cation is not implied. Exposure to absolute maximum
rating conditions for ex tended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ........ -55°C to +125°C
Storage Temperature
.......... -65°C to +160P C
All Output or Supply Voltages .... -0.5 to +7 Volts
All Input Voltages ............ -1.0 to 5.5 Volts
Output Currents ...................... 100 mA
D.C. CHARACTERISTICS
T A = -55°C to +125°C
Symbol
Vee = +5V ±10%
Parameter
Limits
Min.
Typ.
Unit
Test Conditions
Max.
IF
Input Load Current
STB, OS2, CR, 011-018 Inputs
-.25
mA
VF
=
IF
Input Load Current
MO Input
-.75
mA
VF
= .45V
IF
Input Load Current
OS, Input
-1.0
mA
VF
=
.45V
IR
Input Leakage Current
STB, OS, CR, 011-018 Inputs
10
p..A
V.
=
Vee
IR
Input Leakage Current
MO Input
30
p..A
V.
=
Vee
IR
Input Leakage Current
OS, Input
40
p..A
V.
=
Vee
Ie
=
-5mA
V
IOL
V
IOH
=
=
-75
mA
Vee
20
p..A
Vo
145
mA
Ve
Input Forward Voltage Clamp
-1.2
V
VIL
Input "Low" Voltage
.BO
V
VIH
Input "High" Voltage
VOL
Output "Low" Voltage
VOH
Output "High" Voltage
los
Short Circuit Output Current
1101
Output Leakage Current
High Impedance State
Icc
Power Supply Current
2.0
V
.45
3.5
.45V
4.0
-15
90
14-49
=
10mA
-.5mA
5.0V
= .45V to vee
M8212
A.C. CHARACTERISTICS
T A =- 55°Cto+125°C
Symbol
V cc -+5V+l0o/c
0
-
"" :t<'
Limits
Parameter
Min.
Unit
Test Conditions
Max.
ns
tpw
Pulse Width
tpD
Data To Output Delay
30
ns
NOTE 1
tWE
Write Enable To Output Delay
50
ns
NOTE 1
tSET
Data Setup Time
20
ns
tH
Data Hold Time
30
ns
tR
Reset To Output Delay
55
ns
NOTE 1
ts
Set To Output Delay
35
ns
NOTE 1
tE
Output Enable/Disable Time
50
ns
NOTE 1 C L = 30 pF
tc
Clear To Output Delay
55
ns
NOTE 1
CAPACITANCE
40
F = 1 MHz, VelAs =2.5V, Vcc
Symbol
=
+5V, TA
= 25°C
LIMITS
Test
Typ.
Max.
CIN
OS, MD Input Capacitance
9 pF
15 pF
CIN
DS"CLR, STBI, 01,-01,
Input Capacitance
5 pF
10 pF
COUT
00,-00, Output Capacitance
8 pF
15 pF
SWITCHING CHARACTERISTICS
Conditions of Test
Input Pulse Amplitude = 2.5V
Input Rise and Fall Times: 5 ns between 1V and 2V
Test Load
Vee
R,
TO
D,U,T,
rCl
-=-
NOTE 1:
TEST
tpD. tWE. tA.
Cl
Is. to
30pF
R,
R2
300n
600n
tEo ENABLEt
30pF
10Kn
lKn
tEo ENABLE.
30pF
300n
600n
tE~ DISABLEt
5pF
JOon
600n
tEo DISABLE.
5pF
10Kn
lKn
14-50
R2
-=-
M8212
TIMING DIAGRAM
'5vA--------*'5v
'5vl
\~5V______
Oall
Ir='PW--I--'H~~---
________ -1.
ST80'
Os,.
os,
_________L__,WE----,I, _______ _
OUTPUT
________________
JX~15_V
,-',j
DS,.DS,+_MD_ _ _ _ _ _ _ _ _
_______
\ 15_V____
~-'E1 r - - - - - - - L='=1::---L-
-
-
-
-
-
-
-
-
-
________
~'_5V
-
__'ft=f:'==-L:-
OUTPUT
-
cTA
----15V\1---'PWi1;--15V- ~
I.
DO
_________________
'5V
DATA
I
Os, • OS,
~\'_15_V_____
~--------*1bV
--------~~'SET-'svjST8 0'
~I r - - - - - -
'"
~'----
\
_ _ _ _ _ _ _ _ _ _ _~_'P_O~/----------OUTPUT
ST8
__ _ _ _ _ _ _ _ _ _
15VI
~X"-15_V____________
\'S'------------V
-----~ ~'pW-1
15V
15V
1.5V
-'R-1 '--_______
---J
14·51
M8212
TYPICAL CHARACTERISTICS
INPUT CURRENT VS. INPUT VOLTAGE
Vee
=
OUTPUT CURRENT VS. OUTPUT "LOW" VOLTAGE
loor------,-------,-------,--------,
~~
15,ov
-50
80
1
"'"
-100
>-
TA = 0 C
~
~ -150
V
~
!
VTA '25 C
VTA ·,5C
::>
u
>-
ii'
!: -200
~
a:
a:
>-
60
::>
u
>-
~::>
40
0
20
-250
-300
-3
-2
.,
-1
.,
.3
INPUT VOL TAGE IVI
OUTPUT "LOW" VOLTAGE (V)
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE
50
Vee
~f+50V
TA - 25 C
40
0
//
\I~..:._20
/-
-~I--
/
10
0
50
100
_/
J,..--- I--
"
150
200
250
OUTPUT "HIGH' VOL T AGE (V)
LOAD CAPACITANCE (pF)
DATA TO OUTPUT DELAY
VS. TEMPERATURE
WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE
300
2
Vee
0
=
tSlov
I
35~----r-----+-----~----~----~
,/
8
30t-----+----+---~--___t_------I
/
;;... .....
6
.,-/
.,-
/
1-
4
-........
2
10
-25
25
50
'5
------:!.,00
1?2'':-5-----!------:':25:-----:':50;;-------::''::-5
100
TEMPERATURE ( C)
TEMPERATURE 1 C}
14·52
inter
M8214
PRIORITY INTERRUPT CONTROL UNIT
• 8 Priority Levels
• 24-Pin Dual In-Line Package
• Fully Expandable
• Full Military Temperature Range
- 55°C to + 125°C
• Current Status Register
• + 10%
• Priority Comparator
Power Supply Tolerance
The Intel ill M8214 is an 8·level priority interrupt control unit (PICU) designed to simplify interrupt·driven microcom·
puter systems.
The PICU can accept 8 requesting levels; determine the highest priority, compare this priority to a software controlled
current status register and issue and interrupt to the system along with vector information to identify the service
routine.
The M8214 is fully expandable by the. use of open collector interrupt output vector information. Control signals are
also provided to simplify this function.
The PICU is designed to support a wide variety of vectored interrupt structures and reduce package count in interrupt·
driven microcomputer systems.
LOGIC DIAGRAM
PIN CONFIGURATION
iIi>
.,
24
Vee
23
EeS
22
A,
SGS
2'
A6
INT
20
"5
elK
,g
A,
80
El"
[1I>ETLG
REQUEST ACTIVITY
.,
M8214
"3
'8
INTE
..,
",
A,
A,
A,
'0
ElA
~"
GNO
12
liD
Ao
",
@> ",
IiI> "3
QD
IiI>
IE>
['2>
[E>
[0
CD
"'
(OPEN COLLECTOR)
Ao
AND
PRIORITY
A, CD
ENCODER
",
80
I
f8
B,
Ao
CD
SGS
'.~
elK
INTERRUPT ENABLE
CLOCK liNT F-FI
ENABLE LEVEL READ
ENABLE THIS lEVEL GROUP
OUTPUTS
l
"0-"'2
iNT
REQUEST LEVELS
ENLG
ENABLE NEXT LEVEL GROUP
INTERRUPT (ACT LOW)
J
D So
INT
DIS
FF
~~
II>
OPEN
COLLECTOR
14·53
~
r-__~=t~~---------ENLG~
"6
B,
INPUTS
",
R;,
II>
II>
REQUEST
LATCH
I
M8214
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . -65°C to +160°C
All Output and Supply Voltages ........ -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . ,-1.0V to +5.5 V
Output Currents . . . . . . . . . . . . . . . . . . . . .. 100 rnA
'COMMENT: Stresses above those listed under ,"Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and 'functional opera-'
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
D.C. AND OPERATING CHARACTERISTICS
TA
= 55°C to 125°C ~CC = 5V ±10%
Symbol
Parameter
Min.
Vc
Input Clamp Voltage (all inputs)
IF
Input Forward Current:
ETLG input
all other inputs
IR
Input Reverse Current:
ETLG input
all other inputs
VIL
Input LOW Voltage:
all inputs
VIH
Input HIGH Voltage:
all inputs
lee
Power Supply Current
VOL
Output LOW Voltage:
all outputs
VO H
Output HIGH Voltage:
ENLG output
los
Short Circuit Output Current: EN LG output
ICEX
Output Leakage Current: INT, Ao, A"
Limits
Typ.!l]
-.15
-.08
Max.
V
le=-5mA
-0.5
-0.25
mA
mA
VF=0.45V
80
40
pA
pA
VR=5.5V
0.8
V
Vee=5.0V
V
Vee=5.0V
90
130
mA
See Note 2.
.3
.45
V
IOL =10mA
V
IOH=-lmA
-55
mA
Vee=5.0V
100
pA
VCEX=5.5V
2.4
3.0
-15
-35
NOTES:
1. Typical values are for T A = 250 e, Vee = 5.0V.
2. 80-82, SGS, eLK, R(j-R;i grounded, all other inputs and all outputs open.
14-54
Conditions
-1.2
2.0
A2
Unit
M8214
..
A C CHARACTERISTICS
T A; _55°C to +125°C VCC; +5V -+10%
,\" \'\~~\:,~1_"~~\,:
1
",
Symbol
Min.
Parameter
Limits
Typ.l11
Max.
,;X;_
.:i;"\:"
U"'~',:~l;\"
ns
tCY
ClK Cycle Time
85
tpw
ClK, ECS, INT Pulse Width
25
15
tlSS
INTE Setup Time to ClK
16
12
ns
tlSH
lNTE Hold Time after ClK
20
10
ns
tETCS[2]
ETlG Setup Time to ClK
25
12
ns
tETCH[2]
ETlG Hold Time After ClK
20
10
ns
tECCS[2]
ECS Setup Time to ClK
85
25
ns
tECCH[3]
ECS Hold Time After ClK
tECRS[3]
ECS Setup Time to ClK
tECRH[3]
ECS Hold Time After ClK
0
tECSs[2]
ECS Setup Time to ClK
85
tECSH[2]
ECS Hold Time After ClK
tOCS[2]
SGS and BO-B2 Setup Time to ClK
90
tOCH[2]
SGS and Bo·B 2 Hold Time After ClK
0
tRCS[3]
Ro ·R 7 Setup Time to ClK
tRCH[3]
Ro·R 7 Hold Time After ClK
0
tiCS
INT Setup Time to ClK
55
tCI
ClK to INT Propagation Delay
tRIS[4]
Ro-R7 Setup Time to INT
10
0
ns
tRIH[4]
RO-R7 Hold Time After INT
35
20
ns
ns
0
110
ns
70
ns
70
ns
ns
0
100
50
ns
ns
55
ns
ns
35
15
ns
30
ns
tRA
Ro·R 7 to Ao-A2 Propagation Delay
80
100
ns
tELA
ElR to Ao-A2 Propagation Delay
40
55
ns
tecA
ECS to AO·A2 Propagation Delay
100
130
ns
tETA
ETlG to Ao·A2 Propagation Delay
35
70
ns
tOECS[4]
SGS and Bo-B2 Setup Time to ECS
20
10
tOECH[4]
SGS and Bo ·B2 Hold Time After ECS
20
10
tREN
RO-R7 to ENlG Propagation Delay
45
70
ns
tETEN
ETLG to ENLG Propagation Delay
20
30
ns
tECRN
-----,
ECS to ENlG Propagation Delay
85
110
ns
tECSN
ECS to ENLG Propagation Delay
--
ns
ns
--
--
CAPACITANCE
Limits
Typ.l1]
Max
Unit
CIN
Input Capac itance
5
10
pF
COUT
Output Capacitance Except ENlG (Pin 14)
7
12
pF
Symbol
Min.
Parameter
Test Conditions:
VSIAS = 2.5V, vcc = 5V, TA
= 25°C, f;
1 MHz
14-55
'\~\t\\\\\:'
M8216/M8226
4-BIT PARALLEL BIDIRECTIONAL BUS DRIVER
3.40V Output High Voltage for Direct
• Data Bus Buffer Driver for 8080 CPU • Interface
to 8080 CPU
Low Input Load Current: 0.25mA
• Maximum
• 3-State Outputs
Output Drive Capability for
Military Temperature Range
• Full
• High
Driving System Data Bus
-55°C to +125°C
• ±10% Power Supply Tolerance
• 16-Pin Dual In-Line Package
The M8216/M8226 is a 4-bit bidirectional bus driver/receiver. All inputs are low power TTL compatible. For driving MOS,
the DO outputs provide a high 3.40V VOH, and for high capacitance terminated bus structures, the DB outputs provide a
high 50 mA IOL capability. A non-inverting (M8216) and an inverting (M8226) are available to meet a wide variety of
applications for buffering in microcomputer systems.
PIN CONFIGURATION
cs
LOGIC DIAGRAM
LOGIC DIAGRAM
M8216
M8226
Vee
OlEN
DO,
D',
D',
DB.
DB,
DB,
DO,
D0.
DO,
D••
DB,
DO,
D',
DB,
Dl1 ,
D',
DO,
DO,
DO,
01,
DB,
3ND
01,
DB,
DB,
D',
D',
DB,
DB,
DO,
DO,
PIN NAMES
D',
D',
DB,
DB,
D8 0-DB)
DATA BUS
BI-OIRE"CTIONAl
01 0 .01 3
DATA INPUT
000-D0 3
DATA OUTPUT
OlEN
cs
DO,
DO,
DATA IN ENABLE
DIRECTION CONTROL
'-----+-+------<>cs
CHIP SelECT
OlEN
e>--_-----'
'-----+.....- - - - 0 CS
D'EN c>--......- - - - - '
14-56
M8216/M8226
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............ -55°C to +125°C
Storage Temperature ............. - 6S·C to
+ 160·C
All Output and Supply Voltages ......... -O.5V to +7V
All Input Voltages ................. -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . 125 mA
·COMMENT: Stresses above those listed under "Abs!?lute
Maximum Ratings" may cause permanent damage'''tO''the
device. This is a stress rating only and functional o~~r;':' ,':'
tion of the device at these or any other conditions abov~ , "
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
D.C. AND OPERATING CHARACTERISTICS
T A = _55°C to +125°C, VCC = +5V ±10%
Limits
Symbol
Parameter
Typ.
Max.
Unit
IFl
Input Load Current OlEN, CS
-0.15
-.5
mA
VF = 0.45
-0.08
Min.
Conditions
IF2
Input Load Current All Other Inputs
-.25
mA
VF = 0.45
IRl
Input Leakage Current OlEN, CS
20
IJ.A
VR
IR2
Input Leakage Current 01 Inputs
10
IJ.A
VR
= 5.5V
= 5.5V
Ie = -5mA
Ve
Input Forward Voltage Clamp
-1.2
V
VIL
Input "Low" Voltage M8216
.95
V
Vee = 5V
VIL
Input "Low" Voltage M8226
.90
V
Vee = 5V
20
100
IJ.A
VIH
Input "High" Voltage
1101
Output Leakage Current
(3-State)
lee
Power Supply Current M8216
95
130
mA
lee
Power Supply Current M8226
85
120
mA
VaLl
Output "Low" Voltage
0.3
.45
V
DO Outputs IOL = 15mA
DB Outputs IOL = 25mA
VOL2
Output "Low" Voltage
0.5
.6
V
DB Outputs IOL = 45mA
VOH
Output "High" Voltage
3.4
3.8
V
DO Outputs IOH = -.5mA
VOH2
Output "High" Voltage
2.4
3.0
V
DO Outputs IOH = -2mA
DB Outputs IOH = -5.0mA
los
Output Short Circuit Current
-15
-35
NOTE: Typical values are for TA
V
2.0
DO
DB
- -
= 25°C. VCC =5.0V.
14·57
--
-65
• nn
.
mA
-
Vee = 5V
Vo
= .45V to Vee
DO Outputs Vee
no
nll+nll+~
\/,...,..
= 5.0V
=
~
nv
M8216/M8226
WAVEFORMS
INPUTS
OUTPUT
ENABLE
~tDj
Y
'.5VX,.-----"'~ ~H
OUTPUTS
f
_ _ _ _ _ _ _ _ _- J
~L
.SV
A.C. CHARACTERISTICS
TA = _55°C to +125°C,
vcc =+5V ±10%
Limits
Symbol
Parameter
Min.
Typ.[l]
Max.
Unit
TpOl
Input to Output Delay DO Outputs
15
25
ns
Tp02
Input to Output Delay DB Outputs
M8216
19
33
ns
Tp02
Input to Output Delay DB Outputs
M8226
16
25
ns
(NOTE 2)
TE
Output Enable Time M8216
42
75
ns
(NOTE 2)
TE
Output Enable Time M8226
36
62
ns
(NOTE 2)
To
Output Disable Time M8216
16
40
ns
(NOTE 2)
To
Output Disable Time M8226
16
38
ns
(NOTE 2)
Conditions
(NOTE 2)
(NOTE 2)
Test Conditions
Test Load Circuit
Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
OUT~----~------~
CAPACITANCE
Symbol
Parameter
Min.
Limits
Typ.(1]
Max.
4
6
pF
Unit
CIN
(nput Capacitance
COUTI
Output Capacitance
DO Outputs
6
10
pF
COUT2
Output Capacitance
DB Outputs
13
18
pF
Test Conditions:
NOTES:
VSIAS = 2.5V, vee = 5.0V, TA = 25°C, f = 1 MHz.
1. Typical values are for TA
2.
TEST
= 25°e, Vee = 5.0V.
CL
R,
R2
JOpF
JOOl!
6OOl!
Tp02
TE. (DO. ENABLEti
JOOpF
JOpF
90l!
10Kl!
lSO!l
lKl!
TE. (DO. ENABLE.)
T E. (DB. ENABLEti
JOpF
JOOpF
JOOl!
10Kl!
600n
lKl!
TE• (DB. ENABLE.i
JOOpF
90n
1SOl!
5pF
JOOl!
To. (DB. DISABLEti
5pF
5pF
tOKl!
90l!
6OOl!
tKl!
To. (DB. DISABLE.)
5pF
10Kl!
TpDl
To. (DO. DISABLEti
To. (DO. DISABLE.)
1SOl!
lKl!
14·58
M8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
• Single Chip Clock Generator/Driver for
M8080A CPU
';"," c';, '
• Oscillator Output for External System
Timing
• Power-Up Reset for CPU
• Crystal Controlled for Stable System
Operation
• Ready Synchronizing Flip-Flop
• Advanced Status Strobe
• Reduces System Package Count
• Fully Military Temperature Range
-55°C to +125°C
• :t 10% Power Supply Tolerance
The Intel@ M8224 is a single chip clock generator/driver for the M8080A CPU. It is controlled by a crystal, selected by
the designer to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status trobe, and synchronization of ready.
The M8224 provides the designer with a significant reduction of packages used to generate clocks and timing for
M8080A.
PIN CONFIGURATION
RESET
Vee
RESIN
XTAll
ROVIN
XTAl2
READY
SYNC
¢l 2 (TTl)
STSTB
GNOqS
BLOCK DIAGRAM
~
XTALl
IE>
XTAL'
1!1>
TANK
h---O---OSC
t - - D - - - ' '1
@>
[!:!>
TANK
OSC
"
!D
SYNC
"
12>
RESIN
----f--~-'
STSTB
[Z>
HSO--'I}-......- - - RESET
U>
9PVOD
fL>
RDYIN
- - - - H i 5 C i } - - - - - READY!!>
PIN NAMES
/
Fi'm"N
RESET INPUT
RESET
ROVIN
RESET OUTPUT
XTAL 1
XTAl2
REAOY INPUT
TANK
USED WITH OVERTONE Xl AL
\
CONNECTIONS
FOR CRYSTAL
READY
READY OUTPUT
asc
OSCILLATOR OUTPUT
SYNC
SYNC INPUT
"2 (TTL)
Q2 elK (TTL LEVEL)
STSTB
STATUSSTB
Vee
+SV
Voo
+12V
GND
OV
.,
(ACTIVE LOW)
8080
~1
\ CLOCKS
14-59
M8224
*COMMENT: Stresses above those li$~'ynder "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functil!Jnal ope(ation of the device at these or any other conditionS"abf,!tIe :,
those indicated in the operational sections of this specifi.;, ,,:', :l'
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias. ',' • • • • • •• -55°C to 125°C
Storage Temperature .••.•••••••. -65°C to 150°C
Supply Voltage, Vee ..•••••••.. • •
-0.5V to +7V
Supply Voltage, Voo •••.•.••.•.. -0.5V to +13.5V
Input Voltage. • . • • • • . • . • • . . • . • •
-1.0V to +7V
Output Current. • • • • • • • • • • • . • • • . • • • •• 100mA
D.C. CHARACTERISTICS
TA =-66°Cto 126°C; Vee = +5.0V ±10%;Voo = +12V ±10%.
Symbol
Parameter
Min.
Limits
Typ.
Max.
Units
Test Conditions
IF
Input Current Loading
-.25
mA
VF = .45V
IR
Input Leakage Current
10
IlA
VR = 5.5V
Vc
Input Forward Clamp Voltage
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
RESIN
All Other Inputs
2.6
2.0
VIWVIL
R ESI N Input Hysteresis
.25
VOL
Output "Low" Voltage
VOH
Output "High" Voltage
I/Jl ,I/J2
READY, RESET
OSC,I/J2 (TTL), STSTB
-1.2
V
Ie = -5mA
.8
V
Vee = 5.0V
V
OSC,
rp2 (TTL)
All Other Outputs
V
Vee = 5.0V
.45
V
IOL = 10mA
.45
V
IOL = 2.5mA
9.0
3.3
2.4
V
V
V
IOH = -1001lA
IOH = -100IlA
IOH = -lmA
-60
mA
Vo =OV
Vee =5.0V
Ios[l]
Output Short Circuit Current
(All Low Voltage Outputs Only)
lee
Power Supply Current
115
mA
100
Power Supply Current
12
mA
-10
Note: 1. Caution, <1>1 and <1>2 output drivers do not have short circuit protection
Crystal Requirements
Tolerance: .005% at _55°C to 125°C
Resonance: Series (Fundamental)*
Load Capacitance: 20-35pF
Equivalent Resistance: 75-20 ohms
Power Dissipation (Min): 4mW
·With tank circuit use 3rd overtone mode.
14-60
,
M8224
A.C. CHARACTERISTICS
Vcc = +5.0 ±10%; Voo = +12.0V ±10%; TA = -55°C to +125°C
Symbol
Parameter
Limits
Typ.
Min.
1>1 Pulse Width
2tcy _ 20ns
t2
1>2 Pulse Width
5tcy _ 45n5
t01
1>1 to 1>2 Delay
0
t02
1>2 to 1> 1 Delay
2tcy _ 25n5
t03
1>1 to 1>2 Delay
t1
tR
1>1 and 1>2 Rise Time
tF
1>1 and 1>2 Fall Time
to2
1>2 to 1>2 (TTL) Delay
Max.
Test
Conditions'::' '
Units
',,}
9
9
ns
CL = 20pF to 50pF
9
~tcy + 40n5
9
2tcy
9
25
25
-5
ns
+15
1>2TTl ,Cl=30pF
R1~300n
R2=600n
toss
1>2 to STSTB Delay
6tcy _ 30ns
tpw
STSTB Pulse Width
tcy _ 23n5
tORS
RDYIN Setup Time to
Status Strobe
50ns _ 4tcy
tORH
RDYIN Hold Time
After STSTB
tOR
READY or RESET to
1>2 Delay
tCLK
ClK Period
f max
Maximum Oscillating
Frequency
Cin
Input Capacitance
6tcy
9
9
STSTB, Cl=15pF
9
R1 = 2K
R2 = 4K
9
4tcy
9
4tcy _ 25n5
9
Cl=10pF
R1=2K
R2=4K
tcy
9
MHz
27
pF
8
Vcc =+5.0V
\I~~"",+ 1?\I
Vs1As =2.5V
f=l MHz
Vee
TEST
CIRCUIT
R,
INPUT
>
Icc
1ND
14-61
R,
GND
M8224
WAVEFORMS
I---------------'Cy
'F
l~ .
- C
1---'03
·t
tljJ2
i
t o"i2--'
tO \i2
f
I
'02
/
SYNC
(FROM 8080A J
_-,,,,--I
'",-
toss
1------tORH-----1
"'\ir---------,ir - - - - - - - - -
- - - - - - - - - - - - - - - - - - -
RDYIN OR RESIN
- - - - - - - - - - - - - - - - - - - '\p-------j-------------------------,~ - - - - - - - - - - - - - - - - - - - - - - - - - _.
READVOUT
- - - - - - - t OR - -
RESET OUT
VOLTAGE MEASUREMENT POINTS: 1, 2 logic "0" = 1.0V, logic "1" = 7.0V. READY, RESET logic "0" = 0.8V, logic "1" = 3.0V.
All other signals measured at 1.5V.
Example:
A.C. CHARACTERISTICS
(For tCY = 488.28 ns.)
TA = -55°C to 125°C; Voo = +5V ±10%; Voo = +12V ±10%.
Symbol
Parameter
Min.
Limits
Typ.
Max.
Units
t,pl
2.4 - - -....
0.45 _ _ _J
,00."
14·107
<:: X'-___
Unit
M8259
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ... - 55°C to + 125°C
Storage Temperature ............. - 65°C to + 150°C
Voltage On Any Pin With Respect
to Ground ........................ - 0.5V to + 7V
Power Dissipation .......................... 1 Watt
D.C. CHARACTERISTICS
TA = - 55°C to + 125°C; Vee= 5V ± 10%
Parameter
Symbol
~~XiA!ujll ~."
·COMMENT: Stresses above those listed under "AbsPhi6!
.'.,
Ratings" may cause permanent damage to the device. This is a stress' ,'" ,
rating only and functional operation of the device at these or any other
conditions above those Indicated In the operational sections of this
specification Is not Implied.
Min.
Max.
Unit
Test Conditions
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+ 0.5
V
VOL
Output Low Voltage
0.45
V
IOL=2 mA
VOH
Output High Voltage
2.4
V
IOH = - 400 ".A
VOH-INT
Interrupt Output High Voltage
2.4
3.5
V
V
IOH = - 400 ".A
IOH= -50/AA
11l(IRO_7)
Input Leakage Current
for IRo_7
-300
10
IlL
Input Leakage Current for Other Inputs
IOFL
Output Float Leakage
± 10
".A
".A
".A
".A
Icc
Vee Supply Current
100
mA
CAPACITANCE
10
VIN=OV
VIN=Vee
V IN = Vee to OV
VOUT = 0.45V to Vee
T A =25°C; Vee=GND=OV
Symbol
Parameter
Max.
Unit
C IN
Input Capacitance
Min.
Typ.
10
pF
fc= 1 MHz
CliO
1/0 Capacitance
20
pF
Unmeasured pins returned to Vss
14-108
Test Conditions
i·,
M8259
Read Status/Poll Mode
\'-______1
iVR-----.. ~
I
""~~W~'-d+--OC--JW3 rzmzZZZZZT~
14-109
DATA
I VmvVW7l/1
M8048/M8748/M8035
SINGLE COMPONENT 8-BIT MICROCOMPUTER
*8048 Mask Programmable ROM
*8748 User Programmable/Erasable EPROM
*8035 External ROM or EPROM
to +125°C Operation
• -55°C
(MS04S/MS035L)
• -55°C to +100°C Operation
(MS74S/MS035)
S-Bit CPU, ROM, RAM, I/O in
Single Package
•
Interchangeable ROM and EPROM
• Versions
• Single 5V Supply
2.5 ... sec and 5.0 ... sec Cycle Versions
• All
Instructions 1 or 2 Cycles.
• Over 90 Instructions: 70% Single Byte
ROM/EPROM
• 641K xx SS RAM
27 I/O Lines
• Interval Timer/Event Counter
• Easily Expandable Memory and I/O
with SOSO/SOS5 Series
• Compatible
Peripherals
• Single Level Interrupt
The Intel® M8048/M8748/M8035/M8035L is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon
chip using Intel's N-channel silicon gate MOS process.
The M8048 contains a 1 K x 8 program memory, a 64 x 8 RAM data memory, 27 I/O lines, and an 8-bit timer/counter in
addition to on-board oscillator and clock circuits. For systems that require extra capability, the M8048 can be expanded
using standard memories and MCS-80'"/MCS-85'" peripherals. The M8035 is the equivalent of an M8048 without program
memory. The M8035L has the RAM power down mode of the M8048 while the M8035 does not. To reduce development
problems to a minimum and provide maximum flexibility, three interchangeable pin-compatible" versions of this single
component microcomputer exist: the M8748 with user-programmable and erasable EPROM program memory for
prototype and preproduction systems, the M8048 with factory-programmed mask ROM program memory for low cost,
high volume production, and the M8035 without program memory for use with external program memories.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The M8048 has extensive
bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results
from an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
BLOCK DIAGRAM
LOGIC SYMBOL
PIN CONFIGURATION
RESET_
SINGLE
STEP
EXTERNAL_
MEM
M8048
INTERAUPT-
BUS
14-110
M8048/M8748/M8035
DRIVING FROM EXTERNAL SQ:PllCE
CRYSTAL OSCILLATOR MODE
+ 5V
, - - - - - - , - - . . , XTAL1
4709
1·6 mHz
0- 15 pF
(INCLUDES XTAL,
)0--+-------=-1 XTAL 1
SOCKET, STRAY)
+ 5V
'--_--i_-...:3'1
15-25pF
(INCLUDES SOCKET.
STRAY)
XTAL2
4709
I-=-'
'------+---1 XTAL2
CRYSTAL SERIES RESISTANCE SHOULD BE <7SU AT 6 MHz, <180.11 AT 3.6 MHz.
BOTH Xl AND X2 SHOULD BE DRIVEN.
RESISTORS TO Vee ARE NEEDED TO ENSURE VIH '" 3.8V IF TTL CIRCUITRY IS
USED. THE MINIMUM HIGH AND THE MINIMUM LOW TIMES ARE 45%.
LC OSCILLATOR MODE
~
~
45 JJH
120 f.lH
20 pF
20 pF
NOMINALf
5.2 MHz
3.2 MHz
.-----.---"1 XTAL1
L---+--"IXTAL2
Cpp:::: 5-10 pF PIN·TO·PIN
CAPACITANCE
EACH C SHOULD BE APPROXIMATELY 20pF, INCLUDING STRAY CAPACITANCE.
PROGRAMMING, VERIFYING, AND
ERASING THE 8748 EPROM
WARNING:
An attempt to program a rnlssocketed 8748 will result in severe
damage to the part, An indication of a properly socketed part is the
appearance of the ALE clock output. The lack of th is clock may
Programming Verification
In brief, the programming process consists of: activating
the program mode, applying an address, latching the
address, applying data, and applying a programming pulse.
Each word is programmed completely before moving on to
the next and is followed by a verification step. The followtion of their functions:
Pin
Function
XTAL 1
Clock Input (1 to 6MHz)
Reset
Initialization and Address Latching
Test 0
Selection of Program or Verify Mode
EA
Activation of Program/Verify Modes
BUS
Address and Data Input
Data Output During Verify
be used to disable the prQgrammer.
The Program !Verify sequence is:
1.
~ 5v,
2.
Insert 8748 in programming socket
Clock applied or internal oscillator operating,
RESET = Ov, TEST 0 = 5v, EA = 5v, BUS and PROG
floating.
J.
I
4.
EA
t:;:)
uv
I U=
(select program mooel
= 23V (activate program mode)
5.
Address applied to BUS and P2()'1
6.
RESET
7.
Data applied to BUS
8.
V DO = 25v (programming power)
9.
PROG
10.
V DD =5v
=
5v (latch address)
= Ov followed by one 50ms pulse to
= 5v (verify
11.
TEST 0
12.
Read and verify data on BUS
= Ov
= Ov and
23V
mode)
P20-1
Address Input
13.
TEST 0
VDD
Programming Power Supply
14.
RESET
PROG
Program Pulse Input
15.
Programmer should be at conditions of step 1 when 8748
repeat from step 5
is removed from socket.
14-111
MS04S/MS74S/MS035
/'
'1",
AC TIMING SPECIFICATION FOR PROGRAMMING
TA
= 25°C ± 5°C, Vee = 5V ± 5%, Voo = 25V ± 1V
...
'l.
Min.
Parameter
Symbol
tAW
Address Setup Time to RESET t
4tcy
tWA
Address Hold Time After RESET I
4tcy
tow
Data in Setup Time to PROG I
4tcy
two
Data in Hold Time After PROG I
4tcy
tpH
RESET Hold Time to Verify
4tcy
tvoow
Voo
4tcy
tVOOH
Voo Hold Time After PROG I
0
tpw
Program Pulse Width
50
tTW
Test 0 Setup Time for Program Mode
4tcy
4tcy
tWT
Test 0 Hold Time After Program Mode
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
tr. tf
Voo and PROG Rise and Fall Times
0.5
CPU Operation Cycle Time
5.0
tRE
RESET Setup Time Before EA
IS
Unit
60
mS
4tcy
tCY
Note: If Test 0
Max.
t.
high too can be triggered by RESET
2.0
J.LS
J.LS
4tcy
t.
DC SPECIFICATION FOR PROGRAMMING
TA = 25°C ± 5°C. Vee = 5V ± 5%. VOD = 25V ± 1V
Symbol
Parameter
VOOH
Voo Program Voltage High Level
VOOL
Voo Voltage Low Level
VPH
PROG Program Voltage High Level
VPL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
V EAH1
EA1 Verify Voltage High Level
Min.
Max.
Unit
24.0
26.0
V
4.75
5.25
V
21.5
24.5
V
V
21.5
24.5
V
8748
11.4
12.6
V
8048
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
mA
IPROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
14-112
Test Conditions
0.2
VEAL
I~ ..
Test Conditions .... ,
M8048/M8748/M8035
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAM/VERIFY MODE lEPROM'S ONLYI
EA
:: __________.JJ'
1 - - - - - - - - - - PROGRAM ---------t-~- VERIFY--'~I~'----PROGRAM - - - ~---~
TO
DBo-DB,
J--
---<
DATA TO BE
PROGRAMMED VALID
NEXT ADDR
VALID
LAST
ADDRESS
x==
NEXT
ADDRESS
~~-~_~_:____________________________________________
voo+:
+23----------PROG +5 _
_ _ _ _ _ _ _ _
,,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ""\
___ -'
,,",_ _ _ _ _ __
+0
VERIFY MODE (ROM/EPROMI
TD.RESET
080-0B7
-JJ'
\ \ .______________
=>---
\'"-_____J'
\""----
- - -<\.____A_~_~_~~_S_S _'X\._N_O~_~_TV_~_~_i~_'>-
ADDRESS
10-71 VALID
__
-
-
-
-
-
-
-
\J
V
---------~I\\.----------~----.-.-----.-----.------------~/'\.--------------_________________________
NOTES,
1. PROG MUST FLOAT IF EA IS LOW (i.e., ",23VI, OR IF TO' 5V FOR THE 8748. FOR THE
8048 PROG MUST ALWAYS FLOAT.
2. X, AND X, DRIVEN BY 3 MHz CLOCK WILL GIVE 5",ec fey. THIS IS ACCEPTABLE FOR ALL PARTS.
The 8748 EPROM can be programmed by either of two
Intel products:
1, PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP Series)
peripheral of the Intellec@ Development System with a
UPP-848 Personality Card.
14-113
M8048/M8748/M8035
INSTRUCTION SET
Mnemonic
Sj!
"E
"<><>
ct
...
5
5
0
:::.
..."
.5
I!
!
..
'0
~
.c
c<>
..
I!
Description
Bytes Cycle
ADD A, R
ADD A,@R
ADD A, #data
ADDCA, R
ADDCA,@R
AD DC A, #data
ANL A, R
ANLA,@R
ANL A, #data
ORL A, R
ORLA,@R
ORL A. #data
XRL A, R
XRLA,@R
XRL A. #data
INCA
DECA
CLR A
CPLA
DAA
SWAP A
RLA
RLC A
RR A
RRCA
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register to A
And data memory to A
And immediate to A
Or register to A
INA, P
OUTL P, A
ANL p, #data
ORL p, #data
INS A, BUS
OUTL BUS, A
ANL BUS, #data
ORL BUS, #data
MOVD A, P
MOVD P, A
ANLD P, A
ORLD P, A
Input port to A
Output A to port
INCR
INC@R
DEC R
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNI addr
JBb addr
Or data memory to A
Or immediate to A
Exclusive or register to A
Exclusive or data memory to A
Exclusive or immediate to A
c
'S
l!
.Q
"
0
::Ii
J!!
C
1
2
2
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
Input expander port to A
Output A to expander port
And A to expander port
Or A to expander port
2
2
2
2
2
2
=a
Jump on A zero
Jump on A not zero
Jump
Jump
Jump
Jump
Jump
Jump
on
on
on
on
on
on
TO
TO
T1
T1
FO
F1
=1
=0
=1
=0
=1
=1
Jump on timer flag
Jump on INT
=0
Jump on accumulator bit
(J
.
-;:
E
2
2
2
Increment data memory
Decrement register
Jump on carry
~
"0
j::
Increment register
Jump unconditional
Jump indirect
Decrement register and skip
Jump on carry = 1
.
g
c
8
1
2
Mnemonic
Description
CALL
RET
RETR
Jump to subroutine
Return
CLR
CPL
CLR
CPL
CLR
CPL
Clear carry
",'"
C
C
FO
FO
F1
F1
MOVA, R
MOVA,@R
MOV A, #data
MOV R, A
MOV@R,A
MOV R, #data
MOV @R, #data
MOV A, PSW
MOV PSW, A
XCH A, R
XCHA,@R
XCHD A,@R
MOVXA,@R
MOVX@R,A
MOVPA,@A
MOVP3 A,@A
MOVA, T
MOVT, A
STRTT
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
Return and restore status
2
2
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
Move register to A
Move data memory to a
1
1
Move immediate to A
2
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
1
2
2
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
Move external data memory to A
Move A to external data memory
Move to A from current page
Move to A from page 3
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter interrupt
Disable timer/counter interrupt
EN I
DIS I
SEL RBO
SEL RB1
SEL MBO
SEL MB1
ENTO CLK
Enable external interrupt
Disable external interrupt
NOP
No operation
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output on TO
2
2
2
2
2
2
2
2
Mnemonics copyright Intel Corporation 1978
14-114
2
Complement carry
2
2
2
2
2
Bytes'C~
1
2
2
2
2
M8048/M8748/M8035
PIN DESCRIPTION
Designation
Pin #
Designation
Function
Vss
20
Circuit GND potential
INT
Vee
26
Programming power supply; +25V
during program, +5V during operation for both ROM and PROM.
Low power standby pin in 8048
and 8035L.
Vee
40
Main power supply; +5V during
operation and programming.
PROG
25
Program pulse (+23V) input pin
during 8748 programming.
DBc-DB7
BUS
21-24 8-bit quasi-bidirectional port.
35-38 P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit·I/0 expander
bus for 8243.
TO
Input pin testable using the conditional transfer instructions JTO
and JNTO. TO can be designated as
a clock output using ENTO CLK
instruction. TO is also used during
programming.
39
Input pin testable using the JT1,
... .-....
,,,,.,..'"
: ............ , ..... +i ....... ,..
r" .......
h~
deSignated the timer/counter input using the STRT CNT instruction.
,
Output strobe activated during a
BUS read. Can be used to enable
data onto the bus from an external
device.
4
Input which is used to initialize the
processor.
Also used during
PROM programming verification,
and power down. (Active low)
(Non TTL VIH)
10
Output strobe during a bus write.
(Active low)
27-34 8-bit quasi-bidirectional port.
12-19 True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Function
Interrupt input. Initiates an i~ter.>:J':):"
rupt if interrupt is enabled. Inter- {,'\"
rupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
Used as a read strobe to external
data memory. (Active low)
Used as write strobe to external
data memory.
ALE
11
Address latch enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives the addressed instruction
under the control of PSEN. Also
contains the address and data
during an external RAM data store
instruction, under control of ALE
RD, and WR.
'
T1
6
8
Output strobe for 8243 I/O expander.
P10-P17
Port 1
P20-P27
Port 2
Pln#
9
Program store enable. This output
occurs only during a fetch to external program memory. (Active low)
5
Single step input can be used in
junction with ALE to "single step"
the processor through each instruction. (Active low)
EA
7
External access input which forces
all program memory fetches to reference external memory. Useful
for emulation and debug, and
essential for testing and program
verification. (Active high)
XTAL1
2
One side of crystal input for internal oscillator. AlSO InpUt Tor external source. (Non TTL VIH)
XTAL2
3
Other side of crystal input.
14·115
M8048/M8748/M8035
A.C. CHARACTERISTICS (PORT 2 TIMING)
TA
= -55°C to
(100°C 8748/8035/125°C 8048/8035L), VCC
Symbol
= +5V ± 10%, VSS = OV
Parameter
Min.
tcp
Port Control Setup Before Falling
Edge of PROG
115
tpc
Port Control Hold After Falling
Edge of PROG
65
tPA
PROG to Time P2 Input Must Be Valid
Max.
Unit
ns
ns
860
ns
160
ns
tPF
Input Data Hold Time
top
tpo
Output Data Setup Time
230
ns
Output Data Hold Time
25
ns
tpp
PROG Pulse Width
920
ns
tPL
Port 2 1/0 Data Setup
300
ns
tLP
Port 2 1/0 Data Hold
120
ns
0
PORT 2 TIMING
ALE
EXPANDER
PORT
OUTPUT
PCH
EXPANDER
PORT
INPUT
PCH
PROG
14-116
Test Conditions
M8048/M8748/M8035
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias
8748/8035 .............•......... -55·C to +100·C
8048/8035L ...................... -55·C to +125·C
Storage Temperature .....•.....•.. -65·C to +150·C
Voltage On Any Pin With Respect
to Ground ...............•............. -0.5 to +7V
Power Dissipation ...................•....• 1.5 Watt
'COMMENT:
Stresses above those fisted under "Absolute Maximum Ratirlfll'''
may cause permanent damage to the device. This Is a stress rsting
only and functional operation of the device at these or _ny other
conditions above those indicated in the operational sections of this
specification is not implied.
D.C.AND OPERATING CHARACTERISTICS
TA
= -55·C to
(100·C 8748/8035/125·C 8048/8035Li, Vee
Symbol
= Voo = +5V ± 10%, Vss = OV
limits
Parameter
Min.
Typ.
Unit
Test Conditions
Max.
V1l
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.7
V
V1ll
Input Low Voltage
(RESET, X1, X2)
-.5
.5
V
V1H
Input High Voltage
(All Except XTAL1, XTAL 2, RESET)
2.3
Vee
V
V1Hl
Input High Voltage (~X1, X2)
3.8
Vee
V
VOL
Output Low Voltage
(BUS, RD, WR, PSEN, ALE)
.45
V
IOl
= 1.2mA
V Oll
Output Low Voltage
(All Other Outputs)
.45
V
IOl
= 0.8mA
VOH
Output High Voltage (BUS)
2.4
V
IOH= -24OILA
VOHl
Output High Voltage
(RD, WR, PSEN, ALE)
2.4
V
IOH
= -5OILA
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH
= -3OILA
III
Input Leakage Current (T1, INT)
±10
Illl
Input Leakage Current
(P10-P17, P20-P27, EA, SS)
-700
!LA
!LA
Vss+.45 :5VIN -:;;Vee
ILO
Output Leakage Current (BUS, TO)
(High Impedance State)
± 10
ILA
Vss + .45-"V1N-"Vee
100
Voo Supply Current
10
25
mA
100+ lee
Total Supply Current
80
155
mA
BUS
VSS-"VIN-"Vee
P1, P2
BUS, P1, P2
-500""
70mA
50mA
-300""
%
%
9
0
9
30mA
-100""
4Y
YaH
10mA
G
OV
OY
2V
4V
VOH
VOL
14·117
M8048/M8748/M8035
WAVEFORMS
Instruction Fetch From External Program Memory
Read From External Data Memory
1~-----'cY-------~1
:---- tLL
ALE
I
--..1
J I l - - l----'L
-i
teA
I
PSEN
ALE
r-
J
I~- tcc-I
RD
------11
t AFC ________
---I 1--tOR
~--"'"
BUS
BUS
I
I
1__ --
i i
-'
FLOATING
I
r-
teA
f---t
i
L
OR
~--FL-O-AT-'N-G--
1---t
l... t RO - ]
AD - - - - :
Input and Output Waveforms for A.C. Tests
Write to External Data Memory
ALE
J
L
"=X
WR
BUS
2.0
>
TEST POINTS
0.8
<
2.0
0.8
0.45
x=
A.C. CHARACTERISTICS
TA
= -55°C
to (100°C 8748/8035/125°C 8048/8035Lj, Vee
= VDD = +5V ± 10%,
8048
8648 (Note 2)
Symbol
Parameter
8748/8035/8035l
Min.
Note
Max.
Vss
8748
8035
Min. Max.
= OV
Unit
Conditions (Note 1)
tll
ALE Pulse Width
200
300
ns
tAL
Address Setup to ALE
120
120
ns
tLA
Address Hold from ALE
SO
SO
ns
tcc
Control Pulse Width (PSEN, RD, WR)
400
600
ns
tDw
Data Setup before WR
420
600
ns
tWD
Data Hold After WR
SO
120
ns
Cl = 20pF
tCY
Cycle Time
2.5
4.17 15.0
/1S
(3.6 MHz
XTAL 8748/8035)
tDR
Data Hold
tRD
PSEN, RD to Data In
tAW
Address Setup to WR
0
tAD
Address Setup to Data In
Address Float to RD, PSEN
tCA
Control Pulse to ALE
Control outputs: CL =80 pF
BUS Outputs:
CL = 150 pF
tCY
200
0 200
ns
400
600
ns
230
tAFC
1:
15.0
=
260
600
ns
900
ns
-40
-60
ns
10
10
ns
2.5/1s for 804S/8035L
4. 17/1s for 8748/8035
14·118
INTEL CORPORATION , 3065 Bowers Avenue , Santa Clara, CA 95051 • (408) 987·8080
Printed in USA / B·158 /0379 / 125K / CP
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