1979_Mostek_Microcomputer_Products_Data_Book 1979 Mostek Microcomputer Products Data Book
User Manual: 1979_Mostek_Microcomputer_Products_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 848
| Download | |
| Open PDF In Browser | View PDF |
1979
Microcomputer Products
Data Book
Copyright © 1979 Mostek Corporation (All rights reserved)
Trade Marks Registered ®
Mostek reserves the right to make changes in specifications at any time and without notice. The information
furnished by Mostek in this publication is believed to be accurate and reliable. However, no responsibility is assumed
by Mostek for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No
license is granted under any patents or patent rights of Mostek.
The "PRELIMINARY" designation on a Mostek data sheet indicates that the product is not characterized. The
specifications are subject to change, are based on design goals or preliminary part evaluation, and are not
guaranteed. Mostek Corporation or an authorized sales representative should be consulted for current information
before using this product. No responsibility is assumed by Mostek for its use; nor for any infringements of patents
and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent
rights, or trademarks of Mostek. Mostek reserves the right to make changes in specifications at any time and without
notice.
PRINTED IN USA June 1979
Publication Number MK79707
1979 MICROCOMPUTER DATA BOOK
Functional Index
of Contents
General
Information
Micro Design Series
~vl""'r'n"'ble
Micro Design Series
Single Board
Z80 Micro
Device Fam
3870 Micro
Device Family
F8 Micro
Device Family
SOlE Series
OEM Modules
SO Series
OEM Modules
Militaryl
Hi-Rei
Micro Development
Systems (U.S.)
Micro Development
Systems (
Micro Development
Aids
1979 MICROCOMPUTER DATA BOOK
Functional Index
of Contents
1979 MICROCOMPUTER DATA BOOK
FUNCTIONAL INDEX
General Information ................................................................. i
Introduction .................................................. " ............... iii
Order Information ............................................................... v
Package Descriptions ........................................................... vii
U.S. and Canadian Sales Offices ................................................. ix
U.S. and Canadian Representatives ................................................ x
U.S. and Canadian Distributors .................................................. xi
International Sales and Marketing Offices ......................................... xii
Micro Design Series-Expandable ................................................
1
Product Specifications
Central Processor Module (MDX-CPU1) ........................................... 3
Dynamic RAM Module (MDX-DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7
EPROM/UART Module (MDX-EPROM/UART) ..................................... 11
Programmable Input/Output Unit (MDX-PIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15
Serial Input/Output Module (MDX-SIO) .......................................... 21
Z80 Debug Module (MDX-DEBUG) .............................................. 27
Z80 Single Step Module (MDX-SST) .......................................... 35
Prototyping Package (MDX-PROTO) ........................................... 37
Universal Memory Card (MDX-UMC) .......................................... 45
EPROM Module (MDX-EPROM) ............................................... 47
Static RAM Module (MDX-SRAM) ............................................ 51
MD Accessories (MD-ACC) ................................................... 55
Analog to Digital Conversion Module (MDX A/D) .............................. 59
Application Note
STD ZOO Bus Description and Electrical Specifications .............................. 63
Micro Design Series - Single Board ............................................
67
Product Specifications
ZOO Single Board Computer (MD-SBC1) .......................................... 69
Z80 Microcomputer Family ......................... ................. , ..........
73
Device Specifications
Central Processing Unit (MK3880) ............................................... 75
Parallel I/O Controller (MK3881) ............................................ 165
Counter Timer Circuit (MK3882) ............ , ....... , .................. , ..... 203
Direct Memory Access (MK3883) ............................................ 239
Serial I/O Controller (MK3884/3885/3887) ................................. 259
Z80 Combo Circuit (MK3886) ................................................ 307
Application Note
Z80 Dynamic RAM Interfacing Technique ....................................... 309
3870 Microcomputer Family ........ ........................................... 325
Device Specifications
2K ROM Single-Chip Microcomputer (MK3870)' .................................. 327
4K ROM Single-Chip Microcomputer (MK3872) ............................... 361
SIO Single-Chip Microcomputer (MK3873) ................................... 395
P-PROM Microcomputer (MK3874) .......................................... 397
Single-Chip Microcomputer (MK3876) ....................................... 401
Fa Microcomputer Family ...................................................... 439
Device Specifications
Central Processing Unit (MK3850) .............................................. 441
Program Storage Unit (MK3851) ............................................. 467
Dynamic Memory Interface (MK3852) ........................................ 485
Static Memory Interface (MK3853) .......................................... 503
Static Memory Interface (MK3854) .......................................... 521
Peripheral Input/Output (MK3861) .......................................... 529
Peripheral Input/Output (MK3871) .......................................... 545
Application Notes
F8 Keyboard Scanning ....................................................... 567
F8 Display Multiplexing ..................................................... 573
F8 External Interrupt Expansion ........................... , ................. 581
F8 Subroutine Interrupt Nesting ............................................. 587
European Software Development (SO/E) Series OEM Modules ....... 597
Product Specifications
Software Development Board (SDB-80E) ........................................ 599
Random Access Memory (RAM-80E) ......................................... 605
Flexible Disk Drive Controller (FLP-80-E) ..................................... 609
SYS·80F Flexible Disk Operating System (FLP-80-DOS) ....................... 613
Software Oevelopoment (SD) Series OEM Modules ...................... 617
Product Specifications
Software Development Board (SDB-80) ......................................... 61 9
Random Access Memory (RAM-80) .......................................... 623
Flexible Disk Drive Controller (FLP-80) ....................................... 627
Flexible Disk Operating System (FLP-80DOS) ................................. 631
Analog/Digital Converter (A/D-80) .......................................... 637
Video Adapter Board (VAB-2) ................................................ 643
Military/Hi-Reliability ............................................................ 647
Product Specifications
Reference Guide ............................................................ 649
Z80 Central Processing Unit (MKB3880-P) ................................... 653
Z80 Parallel I/O Controller (MKB3881-P) ..................................... 657
Z80 Counter Timing Circuit (MKB3882-P) .................................... 661
Quality Specification ........................................................ 665
MIL-M38510 Sampling Plan ................................................ 679
U.S. Disk-Based Development Systems ..................................... 681
Product Specifications
Floppy Disk-Based Computer (AID-80F) .......................................... 683
Z80 Application Interface Module (AIM-80) ................................... 691
3870 Application Interface Module (AIM-72) ................................. 695
PROM Programmer (PPG-08) ................................................ 701
PROM Programmer (PPG-8/16) ............................................. 703
Keyboard Display Unit (CRT) ................................................. 707
Line Printer ................................................................ 711
AID-80F Cross Assembler 3870/F8 (FZCASM) ................................ 715
BASIC Software Interpreter ................................................. 719
FORTRAN IV Compiler ...................................................... 723
FLP-80-DOS Software Library (UB-80-Vl) .................................... 725
European Disk-Based Development Systems . .............................. 727
Product Specification
Microcomputer Development System (SYS-OOFT) ................................. 729
l80 Application Interface Module (AIM-80E) .................................. 737
3870 Application Interface Module (AIM-72E) ................................ 741
PROM Programmer (PPG-08) ................................................ 747
PROM Programmer (PPG-8/16) ............................................. 749
Line Printer ................................................................ 753
AID-80F Cross Assembler 3870/F8 (FlCASM) ................................ 757
BASIC Software Interpreter ................................................. 761
FORTRAN IV Compiler ...................................................... 765
FLP-80-DOS Software Library (LlB-80-V1) .................................... 767
Microcomputer Development Aids ............................................ 769
FORTRAN Cross Software
FORTRAN IV Cross Assembler (XFOR-50170) .................................... 771
FORTRAN IV Cross Assembler (XFOR-80) .................................... 773
Single-Chip Microcomputer Emulators
3870 Emulator (EMU-70) ..................................................... 775
3870 Series Emulator (EMU-72) ............................................. 777
P-PROM Microcomputer (MK3874) .......................................... 779
Miscellaneous Development Equipment
Evaluation Kit (MCK50/70) .................................................... 783
3870/F8 Software Development Board (SDB-50170) .......................... 785
Application Interface Module (AIM-70) ....................................... 791
F8 PSU Emulator (EMU-51) ................................................. 795
Video Adapter Board (VAB-2) ................................................ 799
l80 Software Development Board (SDB-80) .................................. 803
l80 Software Development Board-E (SDB-80E) ............................... 807
l80 Operating System (DDT -80) ............................................. 813
AssemblerIEditorILoader (ASMB-80) ....................•................... 81 7
Video Display Interface (VOl) ................................................. 823
1979 MICROCOMPUTER DATA BOOK
General
Information
ii
MOSTEK 1969-1979
Ten Years of Technology Leadership
Mostek Technology. Technology links the past,
present. and fUlure of Mostek. Innovations In both
circuit and system design, and wafer processing have
accounted for our rapid growth and for the strong
acceptance of Mostek as a technology leader.
Mostek's Z80 IS the most powerful 8-blt microcomputer available. It IS software compatible with the
8080A yet has some significant system advantagesan Increased Instruction set. reduced dynamic
memory interfacing costs, reduced 1/0 costs and
reduced support circuitry costs.
Mostek's 3870 Family of single-chip microcomputers allow system fleXibility and expansion while
retaining the deSign and economic advantages of
single-chip construction. Software compatible with
the F8, Mostek's 3870 family IS the answer to a wide
range of low-cost microcomputer applications.
Microcomputer Systems. Mostek's microcomputer
line IS supported by a wide array of development aids.
These Include software development boards that may
be used as software development aids or as standalone microcomputers. Add-on memory boards,
application Interface modules, and emulators assist In
system deSign, debugging, and field testing.
The proven process technology In the semiconductor Industry IS N-Channel silicon-gate MOS.
Mostek IS recognized as an Important Innovator in this
process because of the continuing development of
new techniques and enhancements which allow
significant performance breakthroughs In our
products. Competing technologies have not yet been
able to approach either the performance or
producibility of N-Channel MOS. Therefore, It appears
that NMOS silicon-gate will continue to lead Industry
developments for several years to come.
Microcomputer Components. Mostek's microcomputer products cover the full spectrum of
microprocessor applications worldWide.
Mostek's microcomputer line Includes Mostek's MD
Serles™ of OEM microcomputer boards. The MD
Series features both stand-alone boards (deSignated
MD) and expandable boards (deSignated MDX) that
are STD-Z80 BUS compatible. These powerful Z80based boards are Simple and economical to use.
Also available IS Mostek's AID-80FTM, a dual floppydisk development system that develops and debugs
software for Mostek's entire microcomputer line.
Mostek provides a complete base of powerful
software and software aids, complete documentatIOn,
and factory and field-application engineers.
Mostek smgle-chlp microcomputer famllv
iii
iv
ORDERING INFORMATION
Factory orders for parts described in this book should include a four-part number as explained below:
Example:
Dash Number
Package
" - - - - - - - - - 3 . Device Number
" - - - - - - - - - - - 4 . Mostek Prefix
1.
Dash Number
One or two numerical characters defining spacific device performance characteristic.
2.
Package
P - Gold side-brazed ceramic DIP
J - CER-DIP
N
K
T
E
3.
-
Epoxy DIP (plastic)
Tin side-brazed ceramic DIP
Ceramic DIP with transparent lid
Ceramic leadless chip carrier
Device Number
1XXX
2XXX
3XXX
38XX
4XXX
5XXX
7XXX
4.
or 1XXXX - Shift Register, ROM
or 2XXXX - ROM, EPROM
or 3XXXX - ROM, EPROM
- Microcomputer Components
or 4XXXX
RAM
or 5XXXX
Counters, Telecommunication and Industrial
or 7XXXX Microcomputer Systems
Mostek Prefix
MK-Standard Prefix
MKB-100% 883B screening, with final electrical test at low, room and high-rated temperatures.
v
vi
MOSTEI(.
MICROCOMPUTER DEVICES
Package Descriptions
PLASTIC DUAL-IN LINE PACKAGING (N)
28 PIN
40 PIN
~
~ ~=~
&-
T
"ONOMj
¥M~"'~ ~~
1 I
''''.0 I I
'"
I =t
'"
PIN SPACING (SEE NOTE 1)
'"
000'
'"
I
626
.
~\
~rOl0
0025
NOTES:
1. The true·poaition pin spacing ia 0.100 between centerline•. Each pin centerline
ia 10000ted within t 0.010 of its true longitudinal po$ition relative to pins 1 and 40.
vii
CERAMIC DUAL-IN-LiNE HERM ETIC PACKAGING (P)
28 PIN
"f]. []ITT
J1 r
'"
.010
".00"''''.0'''' i
Of f'I" 1
800
_
FORID£NTIFICATION
40 PIN
1-"""'·
I'''·"
1=""'' =:1
~mw~~-I=-l
JL
±'
'"''
viii
.
'"'.,""""'"
-i~l~
,~~
"'~I-'"
u.s. AND
CANADIAN SALES OFFICES
CORPORATE HEADQUARTERS
Mostek Corporation
1215 W. Crosby Rd.
P. O. Box 169
Carrollton, Texas 75006
REGIONAL OFFICES
Mostek (Eastern U.S.lCanada)
34 W. Putnam. 2nd Floor
Greenwich, Conn. 06830
Mostek (North Central U.S.)
6125 Blue Circle Drive, Suite A
Minnetonka, Mn. 55343
203/622-0955
612/935-4020
TWX 710-579-2928
TWX 910-576·2802
Mostek (Northeast U.S.)
29 Cummings Park, Suite #426
Woburn, Mass. 01801
Mostek (South Central U.S.)
228 Byers Road
Suite 105
Miamisburg, Ohio 45342
513/866·3405
TWX 810·473·2976
617/935-0635
TWX (Temp.) 710-332-0435
Mostek (Mid-Atlantic U.S.)
East Gate Business Center
125 Gaither Drive, Suite D
Mt. Laurel, New Jersey 08054
609/235-4112
TWX 710-897-0723
Mostek (Southeast U.S.)
Exchange Bank Bldg.
1111 N. Westshore Blvd.
Suite 414
Tampa, Florida 33607
613/676-1304
TWX 810-876-4611
Mostek (Central U.S.)
701 E. Irving Park Road
Suite 206
Roselle, III. 60172
312/529-3993
TWX 91(}-291·1207
Mostek (Michigan)
Livonia Pavillion East
29200 Vassar, Suite 815
livonia, Mich. 48152
313/478·1470
TWX 810·242·2978
Mostek (Southwest U.S.)
4100 McEwen Road
Suite 237
Dallas. Texas 75234
214/386·9141
TWX 910·860·5437
Mostek (Northern California)
202S-Gateway Place
Suite 268
San Jose, Calif. 95011
408/287·5081
TWX 910-336-7336
ix
Mostek (Southern California)
17870 Skypark Circle
Suite 107
Irvine, Calif. 92714
714/549·0397
TWX 910·595·2513
Mostek (Rocky M.ountiJins)
8686 N. Central Ave.
Suite 126
Phoenix, Ariz. 85020
602/997·7573
TWX 910-957·4581
Mostek (NorthY'est)
1107 North East 45th Street
Suite 411
Seattle, Wa. 98105
206/632·0245
U.S. AND CANADIAN REPRESENTATIVES
ALABAMA
Beacon Elect. Assoc., Inc.
11309 S. Memorial Pkw,/.
Suite G
Huntsville, AL 35803
2051881·5031
TWX 810-726-2136
ARIZONA
Summit Sales
7336 E. Shoernan lane
Suite 116E
Scottsdale. AZ 85251
8021994-4587
TWX 910-950-1283
CALIFORNIA
Harvey King. Inc.
8124 Miramar Road
San Diego, CA 92126
7141566-5252
TWX 910-335-1231
COLORADO
Waugaman Associates
4800 Van Gordon
Wheat Ridge, CO 80033
3031423-1020
TWX 910-938-0750
CONNECTICUT
New England Technical Sales
33 Trotwood Drive
W. Hartford. CT 06117
2031236-4705
FLORIDA
Beacon Elect. Assoc .• Inc.
6842 N.W. 20th Ave.
Ft Lauderdale, FL 33309
305/971-7320
TWX 510-955-9834
Beacon Elect. Assoc., Inc.
P. O. Box 125
Ft. Walton Beach, FL 32548
9041244-1550 .
Beacon Elect. Assoc., Inc.
235 Maitland Ave.
P. O. Box 1278
Maitland, FL 32751
3051647-3498
TWX 810.-853-5038
Beacon Elect. Assoc., Inc.
316 Laurie
Melbourne, FL 32901
3051259-0648
TWX 810-853-5038
GEORGIA
Beacon Elect. Assoc., Inc.'
6135 Barfield Rd.
Suite 112
Atlanta, GA 30328
4041256-9640
TWX 810-751·3165
ILLINOIS
Carlson Electronic Sales'
600 East Higgins Road
Elk Grove Village, IL 60007
3121956-8240
TWX 910-222·1819
INDIANA
Rich Electronic Marketing'
599 Industrial Drive
Carmel, IN 46032
317/844-8462
TWX 810-280-2631
Rich Electronic Marketing
3448 West Taylor St.
Fort Wayne, IN 46804
2191432-5553
TWX 810·332-1404
IOWA
Cahill Associates
226 Sussex Or. N.E.
Cedar Rapids, IA 52402
3191377-4018
PENNSYLVANIA
CMS Marketing
121A Lorraine Avenue
P.O. Box 300
Oreland, PA 19075
2151885·5108
TWX 510-665-0161
Carlson Electronic Sales
204 Collins Rd. N.E.
Cedar Rapids, IA 52402
3191377-6341
TENNESSEE
Beacon Elect. Assoc., Inc.
100 Tulsa Road
Oak Ridge, TN 37830
6151482·2409
TWX 810-572.1077
KANSAS
Rush & West Associates'
107 N. Chester Street
Ol~the. KN 68061
9131764-2700
TWX 910-749-6404
Rich Electronic Marketing
1128 Tusculum Blvd.
Suite D
Greenville, TN 37743
6151639-3139
KENTUCKY
Rich Electronic Marketing
5910 Bardstown Road
P. O. Box 91147
Louisville, KY 40291
5021239-2747
MASSACHUSETTS
New England Technical Sales'
135 Cambridge Street
Burlington. MA 01803
617/272-0434
TWX 710-332-0435
MICHIGAN
A.P.J. Associates, Inc.
496 Ann Arbor Trail
Plymouth, MI 48170
3131459·1200
TWX 810·242-6970
TEXAS
West & Associates, Inc.
8403 Shoal Creek Road
Austin, TX 78758
512/451-2456
West & Associates, Inc.'
4300 Alpha Road, Suite 106
Dallas, TX 75234
2141661-9400
TWX 910-860-5433
West & Associates, Inc.
9730 Town Park #101
Houston, TX 77036
7131777-4108
UTAH
Waugaman Associates
445 East 2nd South
Suite 304
Salt Lake City, UT 84111
8011363-0275
TWX 9101925·5607
MINNESOTA
Cahill Associates·
315 N. Pierce
St. PaUl, MN 55104
6121646-7217
TWX 910-563-3737
MISSOURI
Rush & West Associates
481 Melanie Meadows Lane
Ballwin, MO 63011
3141394-7271
NEW MEXICO
Waugaman Associates
9004 Menaul N.E.
Suile 7
P. O. Box 14894
Albuquerque, NM 87111
WISCONSIN
Carlson Electronic Sales
Northbrook Executive Ctr.
10701 West North Ave.
Suite 209
Milwaukee, WI 53226
4141476-2790
TWX 910-222-1819
CANADA
Cantec Representatives Inc.'
17 Bentley Avenue
Ottawa, Ontario
Canada K2E 6T7·
6131225·0363
TWX 610-562·8967
NORTH CAROLINA
Beacon Elect. Assoc., Inc.
1207 West Bessemer Ave.
Suite 112
Greensboro, NC 27408
919/275-9997
TWX 510-925-1119
NEW YORK
ERA (Engrg. Rep. Assoc.)
One DuPont Street
Plainview. NY 11803
5161822-9890
TWX 510-221-1849
Precision Sales Corp.
5 Arbuslus Ln., MR-97
Binghamton, NY 13901
0071648-3686
Precision Sales Corp.·
1 Commerce Blvd.
Liverpool, NY 13088
3151451-3480
TWX 710-541-0463
Cantec Representatives Inc.
15737 Rue Pierrefonds
5te. Genevieve, P.O.
Canada H9H 1G3
5141694·404a
TELEX 05-822790
eantec Representat.wes Inc.
83 Galaxy Blvd., Unit 1A
(Rexdale)
Toronlo, Canada M9W 5X6
4161675-2480
TWX 610-492·2655
'Home Office
Precision Sales Corp.
3594 Monroe Avenue
Rochester, NY 14534
716/381-2820
x
u.s. AND
OKlAHOMA
Sterling Electronics
9810 E. 42nd Street
SUite 229
Tulsa. OK 74145
CANADIAN DISTRIBUTORS
ARIZONA
Klerulff ElectroniCS
4134 E. Wood 5t.
Phoenix, AZ 85040
GEORGIA
Arrow Electronics
3406 Oakchff Road
Doraville, GA 30340
6021243·4104
TWX 910/951·1550
404/455·4054
TWX 8101757·4213
CAUFORNIA
Bell Industries
1161 N. Fair Oaks Avenue
Sunnyvale. CA 94086
4081734·8570
TWX 910/339·9378
Arrow Electronics
720 Palomar Avenue
Sunnyvale, CA 94086
4081739·3011
TWX 9101339·9371
Intermark Electronics
1802 E. Carnegie Avenue
Santa Ana, CA 92705
714/540·1322
TWX 910/595·1583
Intermark Electronics
4125 Sorrento Valley Blvd.
San Diego. CA 92121
71412 79·5200
TWX 910/335·1515
Intermark ElectrOnics
TWX 910/771-2114
ILLINOIS
Arrow Electronics
492 Lunt Avenue
P. O. Box 94248
Schaumburg, IL 60193
NEW JERSEY
Arrow ElectroniCS
Pleasant Valley Avenue
Morrestown. NJ 08057
TWX 810/281·2233
312/893·9420
609/235·1900
TWX 710/897·0892
Bell Industnes
3422 W. Touhy Avenue
Chicago, IL 60645
Arrow Electronics
285 Midland Avenue
Saddlebrook. NJ 07662
312/982·9210
312/640·0200
2131725·0325
219/423·3422
TWX 910/580·3106
Klerulff Electronics
TWX 810/332·1562
Graham Electronics
133 S. Pennsylvania St.
Indianapolis. IN 46204
415/968·6292
317/634·8202
TWX 810/379·6430
Kierulff ElectrOnics
8797 Balboa Avenue
San Diego. CA 92123
TWX 810/341·3481
714/556·3880
TWX 910/595·1720
COLORADO
Bell Industries
8155 W. 48th Avenue
Wheatndge. CO 80033
303/424·1985
TWX 910/938·0393
Klerulff Electronics
10890 E. 47th Avenue
Denver. CO 80239
303/371·6500
TWX 910/932·0169
CONNECTICUT
Arrow Electronics
295 Treadwell
Hamden, CT 06514
2031248·3801
TWX 710/465·0780
Schweber ElectrOnics
Finance Drive
Commerce Industrial Park
Danbury. CT 06810
2031792·3500
TWX 710/456-9405
FLORIDA
Arrow ElectroniCS
1001 N.W. 62nd St.
'
Suite 108
Ft. lauderdale. Fl 33309
305/776·7790
TWX 510/955·9456
Arrow ElectrOnics
115 Palm Bay Road. N.W.
SUite 10 Bldg. 200
Palm Bay. Fl 32905
3051725·1480
TWX 510/959·6337
Diplomat Southland
2120 Calumet
Clearwater. Fl 33515
813/443·4514
TWX 810/866·0436
Klerulff Electronics
3247 Tech Drive
St. Petersburg. Fl 33702
813/576·1966
TWX 810/863·5625
TWX 710/988·2206
Klerulff Electronics
3 Edison Place
Fairfield. NJ 07006
201/575·6750
TWX 9101222·0351
Ft. Wayne ElectroniCS
3606 E. Maumee
Ft. Wayne. IN 46803
Schweber Electronics
17811 Gillette Avenue
Irvine, CA 92714
201/797·5800
TWX 910/223/4519
Klerulff Electronics
1536 Lanmeler
Elk Grove Village, IL 60007
Klerulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
7141731·5711
TWX 910/595·2599
215/441·0600
404/449·9170
317/297·4910
TWX 810/341·3228
7141278·2112
PENNSYLVANIA
Schweber ElectroniCS
101 Rock Road
Horsham. PA 19044
SOUTH CAROLINA
Hammond Electrontcs
1035 lawn Des HIli Rd.
GreenVIlle. SC 29602
4081738·1111
TWX 910/339·9312
TWX 910/335·1182
Klerulff Electronics
14101 Franklin Avenue
Tustm, CA 92680
918/663·2410
Telex 49-9440
816/452·3900
INDIANA
Advent ElectroniCS
8505 ZionSVille Road
Indianapolis. IN 46268
3969 E. Bayshore Road
Palo Alto, CA 94303
314/426·4500
TWX 9101763·0710
Semiconductor Spec
3805 N. Oak Trafficway
Kansas City. MO 64116
Schweber Electronics
4126 Pleasantdale Road
Atlanta. GA 30340
Sunnyvale. CA 94086
1020 Stewart Dnve
MISSOURI
Olive Electronics
9910 Page Blvd.
St. lOUIS. MO 63 I 32
TWX 7101734·4372
Schweber ElectrOnics
18 Madison Road
FaIrfIeld. NJ 07006
201/227·7880
TWX 7101734·3405
NEW MEXICO
Bell Industnes
11728 linn N.E.
Albuquerque. NM 87123
505/292·2700
TWX 910/989·0625
NEW YORK
Arrow Electronics
900 Broad Hollow Rd.
Farmingdale. l.I .. NY 11735
IOWA
Advent ElectroniCS
682 58th Avenue
Court South West
Cedar Rapids. IA 52404
516/694·6800
TWX 510/224·6494
Cramer Electronics
7705 Maltage Drive
P. O. Box 370
Liverpool. NY 13088
319/363·0221
315/652·1000
TWX 710/545·0230
Cramer Electronics
3000 S. Winton Road
Rochester. NY 14623
LOUISIANA
Sterlmg Electronics
4613 Fairfield Avenue
Metairie. LA 70005
803/233·4121
TEXAS
Arrow ElectroniCS
13740 Midway Road
P.O. Box 401068
Dallas. TX 75240
214/661·9300
TWX 910/861·5495
Quality Components
10201 McKalla
SUite D
Austin. TX 78758
512/838-0551
Ouahty Components
4303 Alpha Road
Dallas. TX 75240
214/387·4949
TWX 910/860·5459
Quality Components
6126 Westline
Houston. TX 77036
7131772·7100
Schweber ElectronIcs
7420 Harwin Drive
Houston, TX 77036
7131784·3600
TWX 910/881·1109
Sterling Electronics
2800 longhorn Blvd.
SUite 101
Austin. TX 78759
512/836·1341
Telex - 776-407
Sterling ElectrOniCS
2875 Merrell Road
P.O. Box 29317
Dallas. TX 75229
214/357·9131
Telex - 025
Sterling Electronics
4201 Southwest Freeway
Houston. TX 77027
713/627·9800
504/887·7610
716/275·0300
TWX 910/881·5042
Telex 58-328
TWX 510/253·4766
llonex Corporation
415 Crossway Park Drive
Woodbury. NY 11797
UTAH
Bell Industnes
MASSACHUSETTES
Klerulff Electronics
13 Fortune Drive
Billenca. MA 01821
516/921·4414
TWX 510/221·2196
Schweber Electronrcs
2 TWin line Circle
Rochester. NY 14623
617/667·8331
TWX 710/390·1449
llonex Corporation
1 North Avenue
8urllngton, MA 01803
716/424·2222
Schweber ElectrOnics
Jericho Turnpike
Westbury. NY 11590
617/272·9400
TWX 710/332·1387
516/334·7474
Schweber Electronics
25 Wiggins Avenue
Bedford. MA 01730
617/275-5100
TWX 7101326·0268
Arrow ElectroniCs
960 Cammer Way
Woburn. MA 01801
TWX 510/222·3660
2258 S. 2700 W.
Salt lake City. UT 84119
801/972·6969
TWX 910/925-5686
Klerulff Electronics
3695 W. 1987 South SI.
Salt lake City. UT 84104
801/973·6913
WASHINGTON
Klerulff ElectrOniCS
1005 Andover Park East
Seattle. WA 98188
206/575·4420
NORTH CAROUNA
Arrow Electronics
1369G South Park Dflve
KernerSVille. NC 27282
919/996·2039
Hammond Electronics
2923 Pactftc Avenue
Greensboro. NC 27406
MARYlAND
Arrow ElectrOnics
4801 Benson Avenue
Baltimore. MD 21227
301/247-5200
TWX 710/236·9005
Cramer Electronics
16021 Industnal Dnve
Gaithersburg. MD 20760
919/275·6391
TWX 510/925·1094
OHIO
Arrow ElectrOnics
3100 Plainfield Road
Kettering. OH 45432
301/948·011 0
TWX 710/828·0082
513/253·9176
TWX 810/459·1611
Arrow ElectrOniCs
10 Knoll Crest Dnve
Readtng. OH 44139
MICHIGAN
Arrow ElectroniCS
3921 Varsity Drive
Ann Arbor. MI 48104
5131761·5432
TWX 810/461-2670
Arrow ElectrOnics
6238 Cochran Road
Solon. OH 44139
313/971·8220
TWX 810/223·6020
Schweber ElectrOniCS
33540 Schoolcraft Road
livonia. MI 48150
216/248·3990
TWX 810/427·9409
313/525·8100
Schweber ElectrOnics
23880 Commerce Park Road
Beachwood. OH 44122
MINNESOTA
Arrow ElectroniCS
5251 W. 73rd Street
Edina. MN 55435
216/464·2970
TWX 810/427·9441
TWX 910/444-2034
WISCONSIN
Arrow ElectrOnics
434 Rawson Avenue
Oak Creek. WI 53154
4141764·6600
TWX 910/262·1192
CANADA
Prelco ElectroniCS
2767 Thames Gate Dflve
~~~~~st~at~~· ,oGJano
416/678·0401
TWX 610/492·8974
Prelco Electrontcs
480 Port Royal St. W.
Montreal 357 P.Q. H3l 2B9
514/389·8051
TWX 610/421·3616
Prelco ElectrOnics
1 770 Woodward Drave
Ottowa. Ontano K2C OP8
6131226·3491
TWX 610/562·8724
RAE. Industrial
3455 Gardner Court
Burnaby. B.C. V5G 4J7
604/291·8866
TWX·604/291·8866
W.E.S.lId.
15 15 King Edward St.
Winnipeg. Manitoba R3H OR8
204/632·1260
612/830·1800
Telex - 07-57347
TWX 910/576·3125
xi
INTERNATIONAL MARKETING OFFICES
EUROPEAN HEAD OFFICE
Mostek International
150 Chausee de Ja Hulpe
B·l1 70 Brussels
Belgium
322-660.69.24
Germanv
Mostek GmbH
Talstrasse 172
0-7024 Fllderstadt 1
The Netherlands
United Kingdom
Nljkerk Elektronlka BV
Drentestraat 7
1083 HK Amsterdam
49711-70.10.45
020.428.933
Telex - 7255792
Telex - 11625
Mostek U.K. -ltd.
Masons House
1-3 Valley Dnve
Kingsbury Road.
London, N.W. 9
Mostek GmbH
Fnedlandstrasse 1
d-2085 QUickborn
494106-2077178
Telex - 213685
Norway
Telex - 25940
Telex - 62011
Austria
TranSlstor-Vertnebs GmbH
Auhofstrasse 41 A
A-1130 Vienna
43 222-829.45.12
Telex-13738
47 2-38.02 86
Celdls Limited
37-39 Love rock Road
Reading
Berks RG 31 ED
Telex - 16205
44734-58.51.71
Belgium
Neye Enatechnlk GmbH
Schllierslrasse 14
0-2085 QUickborn
Solfonlc
49 4106-61.22.95
14. Rue Pere de Oeken
8-1040 Brussels
Telex - 213.590
Mostek Scandmavla AS
Magnusvagen 1, 8 tr.
5-17531 Jarfalla
322-736.10.07
Dr Oohrenberg
Bayreuther 5trasse 3
0-1 Berlin 30
Telex - 12997
Telex - 25141
44 1-204.93.22
Hefro Teknlska A/S
Postboks 6596
Rodelkka
Oslo 5
T~lex
Olstronic Limited
50-51 Burnt Mill
Elizabeth Way,
Harlow
Essex CM 202 HU
46 758-343.38
44279-32.497/39.701
Denmark
49 30-213.80.43
Semi cap APS
Gammel KongeveJ 184.5
DK-1850 Copenhagen
Telex - 184860
Interelko AB
5trandbergsg. 47
S-11251 Stockholm
Telex - 10689
Telex - 15987
Raffel-Electronic GmbH
Lochnerstrasse 1
0-4030 Ratlngen
Finland
Telex - 8585180
451-22.15.10
468-13.21.60
492102-280.24
S.W. Instruments
KarstuJantle 48
SF-00550 HelslOkl 55
Siegfried Ecker
Konlgsberger Strasse 2
0-6120 Mlchelstadt
358-0-73.82.65
Telex - 122411
496061-2233
SIUC 505
F-94623 Rungls Cedex
49 7071-24.43.31
331-687.34.14
4461-652.04.31
Telex - 669971
441-599.30.41
Telex - 24507
Yugoslavia
Chemcolor
Inozemma Zastupstva
Proletersklh brlgada 37-a
41001 Zagreb
Memotec AG
CH-4932 Lotzwll
4163-28.11.22
Telex - 726.28.79
Telex - 68636
Dema-ElectronlC GmbH
Blutenstrasse 21
0-8 Munchen 40
49 89-288018
Telex - 28345
113. Rue Artlstlde Bfland
F-91400 Orsay
3310-19.27
Pronto Electronic Systems ltd.
645 High Road,
Seven Kings.
liford,
Essex IG 38 RA
Switzerland
Telex - 204049
I.P.C.
A.M. Lock co., Ltd.
Neville Street.
Chadderton,
Oldham, LancashIre
Spain
Telex - 51934
Matronlc GmbH
Lichtenberger Weg 3
0-7400 Tublngen
Telex - 81387
Comelta S.A
Cia EJectrlnlca Tecnlcas
Apllcadas
Consejo de Clento. 204
Entlo 3A.
Barcelona 11
34 3-254.66.07/08
Telex - 4191630
France
Mostek France s.8.r.1
30 Rue de Morvan
- 84B370
Sweden
41-513.911
Telex - 21236
Telex - 691451
Italy
PEP.
4. Rue Barthelemy
F-92120 Montrouge
Mostek Italla S.p.A
Via G. da Procida. 10
1-20149 Milano
331-73533.20
39 2-349.26.96
Telex - 204534
Telex - 333601
SCAIS
80. Rue d'Arcuil
SIUC 137
Comprel S.r.L.
Vlale Romagna, 1
1-20092 Cmlsello Balsamo
F-94150 Rungls Cedex
39 2-928.08.09/928.03.45
331-687.23.12
Telex - 332484
Telex - 204674
Argentina
Israel
Rayo Electronics. S.R.L
Belgrano 990, PIS os 6y2
1092 Buenos Aires
Telsys limited
54 Jabotlnsky Road
Ramal-Gan 52462
38-1779.37-9476
Telex-122153
972 73.98.65
72.23.62
Telex - 32392
Australia
Amtron Tyree Pty. Ltd
176 Botany Street
Waterloo, N.5.W. 2017
61 69-89.666
Telex - 25643
Brasil
Cosele. Ltda.
Rua da Consolacao. 867
ConJ.31
01301 Sao Paulo
Korea
Vine Overseas Trading Corp.
Room 303-1ae Sung Bldg.
199-1 Jangsa-Oong
Jongro-Ku
Seoul
Taiwan
26-1663.25-9875
5418251
Telex - 24154
Telex - 11064
Japan
Systems Marketing. Inc.
4th Floor, 5hmdo Bldg.
3-12-5 Uchlkanda,
Chlyoda-Ku.
Tokyo. 100
E.C.S. Oiv. of Alrspares
P.O. Box 1048
Airport Palmerston North
81 3-254.27.51
Telex - 3766
New Zealand
77-047
Telex - 25761
South Africa
Radlokom
P.O. Box 56310
Plnegowne
Telex - 1130869
TelJln Advanced Products Corp.
'-1 Uchlsalwal-Cho
2-Chome Chlyoda-Ku
Tokyo, 100
81 3-506.46.73
Transvaal
Hong Kong
Telex - 23548
5511-257.35.35/25843.25
2123.
789-1400
Cet Limited
1402 Tung Wah ManSion
199-203 Hennessy Road
Wanchal. Hong Kong
.
Telex· 8-0838 SA
5-72.93.76
Telex - 85148
xii
Dynamar Taiwan Limited
P.O. Box 67-445
2nd Floor, No. 14, Lane 164
Sung-Chiang Road
Taipei
1979 MICROCOMPUTER DATA BOOK
1
2
MOSTEI(@
MD SERIES MICROCOMPUTER MODULES
zao Central Processor Module (MDX-CPU1)
FEATURES
o Z80 CPU
o 4K x 8 EPROM (two 2i'lt;is, customer provided)
o 256 x 8 Static RAM (compatible with DDT-80
o
o
o
o
o
o
o
o
debugger).
Flexible Memory decoding for EPROM and RAM
Four counter/timer channels
Restart to OOOOH or EOOOH (strapping option)
Debug compatible for single step in DDT-80
4MHz version available
+5Vonly
Fully buffered signals for system expandability
STD-Z80 BUS compatible
DESCRIPTION
The MD Series and the STD-Z80 BUS were designed
to satisfy the need for low cost OEM microcomputer
modules. The STD-Z80 BUS uses a motherboard
interconnect system concept and is designed to handle any MD Series Card type in any slot. The modules
for the STD-Z80 BUS are a compact 4.5 x 6.5 inches
which provide for system partitioning by function
(RAM, EPROM, I/O). This smaller module size makes
system packaging easier while increasing MOS~LSI
densities provide high functionality per module.
addition, an MK3882 Counter Timer Circuit is
included on the MDX-CPU1 to provide counting and
timing functions for the Z80. Either 2716 EPROM
can be located at any 2K boundary within any given
16K block in the Z80 memory map via a jumper
arrangement.
The MDX-CPU1 can be used in conjunction with the
MDX-DEBUG and MDX-DRAM modules to utilize
DDT-80 and ASMB-80 in system development. This is
accomplished by strapping the scratch pad RAM to reside at location F FOO so that it will act as the Operating System RAM for DDT-80.
The MDX-CPU1 is also available in 4MHz version
(MD~-CPU1-4). In this version, one wait cycle is
automatically inserted each time on-board memory is
accessed by a read or write cycle. This is necessary to
make the access times of the 2716 PROMs and the
3539 scratch pad RAM compatible with the MK38804 MHz Z80-CPU.
ELECTRICAL SPECIFICATIONS
WORD SIZE
Instruction:
Data:
8, 16,24, or 32 bits
8 bits
CYCLE TIME
The MD Series of OEM microcomputer boards and
the STD-Z80 BUS offer the most cost effective
system configuration available to the OEM system
designer.
Clock period or T state = 0.4 microsecond @ 2.5MHz
or = 0.25 microsecond @
4.00MHz
Instructions require from 4 to 23 T states
MDX-CPU1 DESCRIPTION
MEMORY ADDRESSING
The MOSTEK MDX-CPU1 is the heart of an MD
Series Z80 system. Based on the powerful Z80 mi.croprocessor, the MDX-CPU1 can be used with great versatility in an OEM microcomputer system application. This is done simply by inserting custom ROM or
EPROM memories into the sockets provided on the
board and configuring them virtually anywhere
within the Z80 memory map.
On-Board EPROM: jumper selectable for any 2K
boundary within a 16K block of Z80 memory map.
On-Board RAM: F FOO-F F F F
On board memory is provided in the form of sockets
for 4K of EPROM (2-2716's) and 256 bytes of
scratch pad RAM as pictured in the block diagram. In
MEMORY CAPACITY
On-Board EPROM - 4K bytes (sockets only)
On-Board RAM - 256 bytes
Off-board Expansion - Up to 65,536 byte, with userspecified combinations of RAM, ROM, PROM.
3
MDX-CPUl BOARD WITH OVERLAY
4
MDX-CPU1 BLOCK DIAGRAM
....
CTC
CE
MK3882
4'
~
PORT
SELECT
CONTROL
I
~}
L
;1
CPU
MK3880
~
/).
CLoe\<
GfNERATO;'
~
~
g
BUFFER CONTROL
TRI
STATE
r- BUFFER
DATA
C.S.
W~
'----8
SCRATCHPAD RAM
(f)
en
w
a::
5
a::
Iz
)
BUFFER
ENABLE
16
~
~~ONTRO~?
BUFFER
..J
0
2
-
~
7ADDRESS~
BUFFER
.,r
8
v
I
AND
USER
PRbM
2
2716's
)
12
MEM.", .,,"'"
CRYSTAl
CQNTROLlto
8
DATA
I
0
(J
BUFFER
ENA
0
0
I
LJONTROL
256 BYTES
~
ENA
<{
....,...
16
BI- DIRECTIONAL
DATA BUFFER
+ltND
~
V
~----------------~v~----------------------~
STO-Z8D 8US INTERFACE
MEMORY SPEED REQUIRED
INTERRUPTS
MEMORY
ACCESS TIME
CYCLE TIME
2716*
450nS
450nS
* Single 5 volt type required
Multi-level with three vectoring mode (Mode 0, 1,2).
Interrupt requests may originate from user-specified
I/O or from the on-board MK3882 CTC.
PARALLEL BUS INTERFACE - STD-Z80 SUS
COMPATIBLE
I/O ADDRESSING
Input
One 74LS load max
Bus Outputs IOH = -15 rnA min at 2.4 volts
IOL = 24 rnA min at 0.5 volts
On-Board Programmable Timer
PORT
ADDRESS (HEX)
MK3882
CHANNEL
7C
7D
7E
7F
o
SYSTEM CLOCK
MIN
MAX
1
2
3
MDX-CPU1 500 KHz
MDX-CPU1-4500 KHz
2.500 MHz
4.000 MHz
I/O CAPACITY
POWER SUPPLY REQUI REMENTS
Up to 252 port addresses can be decoded off board.
Four port addresses are on board. 252 + 4 = 256 total
I/O ports.
5V ± 5% at 1.1 A maximum
5
OPERATING TEMPERATURE
CONNECTORS
FUNCTION
CONFIGURATION
MATING
CONNECTOR
STD-Z80
BUS
56 pin dual read out
Printed Circuit
Viking 3VH28/
ICE5
0.125 in. centers
Wire Wrap
Viking 3VH28/
1CND5
MECHANICAL SPECIFICATIONS
CARD DIMt:NSIONS
4.5 in (11.43cm) high by 6.50 in. (16.51cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
I Solder Lug
I
Viking 3VH28/
1CN5
ORDERING INFORMATION
DESIGNATOR
DESCR IPTION
PART NO.
MDX-CPU1
Module with Operation Manual
less EPROMs and mating connectors.
2.5MHz version.
MK77850
MDX-CPU1-4
Module with Operations Manual less
EPROMs and mating connectors.
4.0 MHz version.
MK77850-4
MDX-CPU1 and -4 Operations Manual
MK79612
MDX-PROTO
data sheet
MD Series Protyping
package
MK79605
AID-80F
data sheet
Disk based development system for
MD Series
MK78568
AIM-80
data sheet
Z80 In-circuit Emulation module
(2.5 MHz only)
MK78537
,
6
MOSTEI(.
MD SERIES MICROCOMPUTER MODULES
Dynamic Ram Module (MDX-DRAM)
FEATURES
o Three memory sizes
o
o
o
SK x S (MDX-DRAMS)
16K x S (MDX-DRAM16)
32K x S (MDX-DRAM32)
Selectable addressing on 4K boundaries.
4MHz version available (MDX-DRAM-4)
STD BUS compatible
DESCRIPTION
The MD Series and the STD-ZSO BUS were designed
to satisfy the need for low cost OEM microcomputer
modules. The STD-ZSO BUS uses a motherboard
interconnect system concept and is designed to handle any MD Series card type in any slot. The modules
for the STD-ZSO BUS are a compact 4.5 x 6.5 inches
which provides for system partitioning by function
(RAM, EPROM, I/O). This smaller module size makes
system packaging easier while increasing MOS-LSI
densities provide high functionality per module.
The MD Series of OEM microcomputer boards and
the STD-ZSO BUS offer the most cost effective
system configuration available to the OEM system
designer.
MDX-DRAM DESCRIPTION
The MDX-D RAM is designed to be a RAM memory
expansion board for the MOSTEK MD SERIES of
ZSO based microcomputers. It is available in three
memory capacities: SK bytes (MDX-DRAMSl, 16K
bytes (MDX-DRAM161, and 32K bytes (MDXDRAM32). Additionally, the MDX-DRAM16 and the
MDX-DRAM32 are available in a 4MHz version. Thus,
the designer can choose from the various options to
tailor his add-on dynamic RAM directly to his system
requirements.
The MDX-DRAMS is designed using MOSTEK's
MK410S, S,192-bit dynamic RAM. The MDXDRAM16 and MDX-DRAM32 utilize high-performance MK4116, 16,3S4-bit dynamic RAMs which
allow 4MHz versions of these boards to be offered.
No wait-state insertion circuitry is required on any of
the RAM cards.
to start on any 4K boundary.
ELECTRICAL SPECIFICATIONS
WORD SIZE
S bits
MEMORY SIZE
MDX-DRAMS - S,192 bytes
MDX-DRAM16 - 16,3S4 bytes
MDX-DRAM32 - 32,76S bytes
ACCESS TIMES
MEMORY
ACCESS
TIMES
SYSTEM
CLOCK
MDX-DRAM
2.5 MHz 350ns max.
MDX-DRAM-4 4.0 MHz 200ns max.
MEMORY
CYCLE
TIMES
465ns min.
325ns min.
ADDRESS SELECTION
Selection of SK, 16K, or 32K contiguous memory
blocks to reside at any 4K boundary
PARALLEL BUS INTERFACE-STD BUS
COMPATIBLE
Inputs
Bus Outputs
One 74LS load max
IOH = -15mA min. at 2.4 volts
IOL = 24mA min. at 0.5 volts
SYSTEM CLOCK
Min
MDX-DRAM
1.25MHz
MDX-DRAM-4 1.25MHz
Max
2.5MHz
4.0MHz
POWER SUPPLY REQUIREMENTS
+5V ± 5% at 0.6A max.
+12V ± 5% at 0.25A max.
-12V ± 5% at 0.03A max.
OPERATING TEMPERATURE
Address selection is provided on all MDX-DRAM
cards for positioning the SK, 16K, or 32K of memory
7
MDX-ORAM BOARD
8
MDX-DRAM BLOCK DIAGRAM
MEMORY ARRAY
.>
--.....
MEMORY DECODE
a
....
BUFFER CONTROL
1\
4
2.5MHz
RAS
8KxB
CAS
4.QMHz
8-MK4108
16KX8 8-MK4116
16KXB
16-MK410B
32KXB I6-MK4116
32KXB
16-MK4116
WRITE
~
4
DIN
A
/\
8
7
BUFFER
DOUT
1
8
1\
.......
I. 4
MUX
~
BUFFER
(4
j\
I. 8
ADDRESS
CONTROL
DATA
BUFFER
j-5V
0
."
c-...
~
CONTROL
LINES
REGULATOR
I i i I
~
DATA
BUS
ADDRESS
BUS
GND +5 +12 -12
MECHANICAL SPECIFICATIONS
CARD DIMENSION
4.5 in. (11.43cm) high by 6.50 in. (16.51 em) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
CONNECTORS
FUNCTION
CONFIGURATION
MATING
CONNECTOR
STD-Z80
BUS
56 pin dual read out
Printed Circuit
Viking 3VH281
ICE5
0.125 in centers
Wire wrap
Viking 3VH281
1CND5
Solder Lug
Viking 3VH281
1CN5
9
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
Module with Operation Manual
less mating connectors in the
following memory capacities,
2.5MHz versions.
MDX-DRAM8
8K Bytes (4108's)
MK77750
MDX-DRAM16
16K Bytes (4108's)
MK77751
(4116's)
MK77754
32K Bytes (4116's)
MK77752
MDX-DRAM32
Module with Operations Manual less
mating connectors in the following
memory capacities, 4.0 MHz version:
MDX-DRAM16-4
16K Bytes (4116's)
MK77754-4
MDX-DRAM32-4
32K Bytes (4116'5)
MK77752-4
MDX-PROTO
Data Sheet
MD Series prototyping
package
MK79605
AID-80F
Data Sheet
Disk based development
system for M D Series
MK78568
AIM-80
Data Sheet
Z80 In-circuit emulation module
(2.5MHz only)
MK78537
10
MD SERIES MICROCOMPUTER MODULES
EPROM/UART Module (MDX-EPROM/UART)
FEATURES
D
D
10K x 8 EPROM/ROM (2716's not included)
Serial I/O channel
RS - 232 and 20 mA interface
Reader step control for Teletypes
Baud rate generator 110-19200 Baud
D 4MHz version available (MDX-EPROM/UART-4)
D STD BUS compatible.
DESCRIPTION
The MD Series and the STD-Z80 BUS were designed
to satisfy the need for low cost OEM microcomputer
modules. The STD-Z80 BUS uses a motherboard
interconnect system concept and is designed to handle any MD Series card type in any slot. The modules
for the STD-Z80 BUS are a compact 4.5 x 6.5 inches
which provides for system partitioning by function
(RAM, EPROM, I/O). This smaller module size makes
system packaging easier while increasing MOS-LSI
densities provide high functionality per module.
The MD Series of OEM microcomputer boards and
the STD-Z80 BUS offer the rnost cost effective
system configuration available to the OEM system
designer.
the unit has been programmed, no further changes are
necessary unless there is a modification of the serial
data format. Features of the UART include:
Full duplex operation
Start bit verification
Data word size variable from 5 to 8 bits
One or two stop bit selection
Odd,even, or no parity option
One word buffering on both transmit and receive
The MDX-EPROM/UART is also available in a 4MHz
version. Circuitry is provided to force one wait state
each time on board EPROMs or the UART are
accessed.
ELECTRICAL SPECIFICATIONS
WORD SIZE
8 bits for PROM
5 to 8 bits for Serial I/O.
MEMORY ADDRESSING
ROM/EPROM
2K blocks jumper selectable for any 2K boundary
within a given 16K boundary of Z80 memory map.
MDX-EPROM/UART DESCRIPTION
MEMORY CAPACITY
The MDX-EPROM/UART is one of MOSTEK's complete line of STD-Z80 BUS compatible Z80 microcomputer modules.
10K bytes of 2716 memory.
(2716's not included)
Designed as a universal EPROM add-on module for
the STD-Zf;JO BUS, the MDX-EPROM/UART provides the system designer with sockets to contain up
to 10K x 8 of EPROM memory (5·2716's) as shown
in the Block Diagram.
MEMORY SPEED REQUIRED
The EPROM memories can be positioned to start on
any 2K boundary within a 16K block of memory via
a strapping option provided on the MDX-EPROM/
UART.
* Single 5 Volt type required
Included on-board the MDX-EPROM/UART is a fully
buffered asynchronous I/O port with a Teletype
reader step control. A full duplex UART is used to receive and tran~mit data at the serial port. Operation
and UART options are under software control. Once
On-board Serial I/O Port
Control Port DDH
DCH
Data Port
Modem and Reader Step Control DEH
MEMORY
ACCESS TIME
CYCLE TIME
2716*
450ns
450ns
I/O ADDRESSING
11
BOARD PHOTO
12
MDX-EPROM/UART BLOCK DIAGRAM
ADDRESS
AND
CONTROL
BUS
~
V
(/)
r---
::J
'"o
00
N
6
f-
~
BUS
MEMORY
INTERFACE
IsELECTION
LOGIC
LOGIC
~
PORT
SELECTION
EPROM/ROM
SOCKETS (5)
LOGIC
~
Vt---II
UART
~
----
(/)
DATA
RS232
AND
20 MA
BUFFERS
~
¢=>
-
20 MA INPUT
OUTPUT t..NO
READER STEP
RS-232
INPUT, OUTPUT
AND
MODEM CONTROL
BUS
L 99625
SERIAL COMMUNICATIONS INTERFACE
I/O TRANSFER RATE
X16 BAUD RATE CLOCK
BAUD RATE (Hz)
1760
4800
9600
19200
38400
76800
153600
317200
110
300
600
1200
2400
4800
9600
19200
SIGNAL
Transmitted data
Received data
Reader Step Relay (RS R)
SERIAL COMMUNICATIONS CHARACTERISTICS
Asynchronous
Full duplex operation
Start bit verification
Data word size variable from 5 to 8 bits.
One or two stop bits
Odd, even, or no parity
One word buffering on both transmit and receive.
Output
Input
Output
(40mA)
Data Terminal Ready (DTR)
Request to Send (RTS)
Carrier Detect (CDET)
Clear to Send (CTS)
Data Set Ready (DSR)
Output
Input
Input
Input
Output
Output
Output
PARALLEL BUS INTERFACE - STD-Z80 BUS
COMPATIBLE
Inputs
Bus Outputs
One 74LS Load Max
IOH = -15mA min at 2.4 Volts
IOL = 24mA min at 0.5 Volts
MECHANICAL SPECIFICATIONS
SYSTEM CLOCK
MDX-EPROM/UART
MDX-EPROM/UART-4
BUFFERED
FOR
20mA Cu rrent
Loop
RS-232
MIN.
MAX.
CARD DIMENSIONS
250 KHz
250 KHz
2.5 MHz
4.0 MHz
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
13
CONNECTORS
CONNECTORS (Contd.)
MATING
CONNECTOR
FUNCTION
CONFIGURATION
STD-Z80
BUS
56 pin dual
Printed Circuit
Viking 3VH28/
1CE5
0.125 in. centers
Wire Wrap
Viking 3VH28/
1CND5
Solder Lug
Viking 3VH28/
1CN5
Serial I/O
26 pin dual
0.100 in. grid
Flat Ribbon
Ansley 6092600M
Discrete Wires
Winchester
PGB26A
(housing)
Winchester
100-70020S
(contacts)
POWER SUPPLY REQUIREMENTS
+12 Volts ± 5% at 50 mA max.
-12 Volts ± 5% at 35 mA max.
+5 Volts ± 5% at 1.2 A max.
OPERATING TEMPERATURE RANGE
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MDX-EPROM/UART
Module with Operation
Manual Less EPROMs and
mating connectors.
2.5MHz version.
MK77753
MDX-EPROM/UART-4
Module with Operation
Manual less EPROMs and Mating
connectors. 4.0 MHz version.
MK77753-4
MDX-EPROM/UART
Operations Manual only
MK79604
MDX-PROTO
Data Sheet
MD Series Prototyping
Package
MK79605
AID-80F
Data Sheet
Data Sheet of disk based
development system for MD
Series
MK78568
AIM-80
Data Sheet
Z80 In-Circuit Emulation
Module (2.5 MHz only)
MK78537
14
MOSTEI(.
MD SERIES MICROCOMPUTER MODULES
Programmable Input/Output Unit (MDX-PIO)
FEATURES:
D
D
D
D
D
D
D
D
D
D
D
D
Four 8-bit I/O ports with 2 handshake lines per
port
A" I/O lines fully buffered
I/O lines TTL compatible with provision for
termination resistor networks
Jumper options for inverted or non-inverted
handshake
Two 8-bit ports capable of true bidirectional I/O
Programmable In only, Out only, or Bidirectional
Output data buffers selectable to provide inverted
or non-inverted drive capability
Interrupt driven programmability
Address strap selectable
STD-Z80 BUS Compatible
4 MHz Option
Fu"y buffered for MD Series expandability
DESCRIPTION
The MD Series and the STD-Z80 BUS were designed
to satisfy the need for low cost OEM microcomputer
modules. The STD-Z80 BUS uses a motherboard
interconnect system concept and is designed to handle any MD Series card type in any slot. The modules
for the STD-Z80 BUS are a compact 4.5 x 6.5 inches
which provides for system partitioning by function
(RAM, EPROM, I/O). This smaller module size makes
system packaging easier while increasing MOS-LSI
densities providingihighfunctionality per module.
The MD Series of OEM microcomputer boards and
the STD-Z80 BUS offer the most cost effective
system configuration available to the OEM system
designer.
MDX-PIO DESCRIPTION
The para"el I/O controller (MDX-PIO) is a highly versatile unit designed to provide a variety of methods
for inputting and outputting data from the MD Series
microcomputer system. The system is designed
around two Mostek MK3881 Z80-P10 para"el I/O
controllers which give four independent 8-bit I/O
ports with two handshake (data transfer) control lines
per port. The Z80-PI0's are designated PIOl and P102.
Each has an I/O port pair designated A and B. Each
port pair of each PIO have similar output circuitry.
A" I/O lines are buffered and have provisions for
termination resistors on board. A" port lines are
brought to two 26 pin connectors; two ports per
connector.
Figure 1 illustrates in block diagram from the major
functional elements of port pair A and B of PIO 1.
These elements can be defined as the resistor termination networks, data buffers, port configuration control, MK3881 PIO, and address decode and data bus
buffers. Input and output from the ports are provided
through J1, a 26 pin connector. This connector provides data paths for the two ports and their respective
handshake signals.
One 14-pin socket is provided per port for resistor
dual inline packages so that terminations may be
placed on the data lines. A para"el termination is provided for each 8-bit port data line plus the input
strobe (STB) handshake line. The MDX-PIO is normarry shipped with 1K pu"up terminators. In addition to the para"el termination resistors, the ready
(RDY) handshake output line is series terminated
with a 47 .n resistor. This is used to damp and reduce
reflections on this output line.
Port A and B data bus lines are buffered using quadruple non-inverting transceivors. The buffers can be
configured using port configuration jumpers to provide fixed Input, fixed Output or Bidirectional
(Port A only) signals. Further the transceivers are
configured such that port direction can be selected in
4-bit sections. The transceivers are mounted in
sockets so that they can be easily replaced with their
complements in order to achieve a polarity change if
desired.
The handshake lines are also fully buffered. The port
configuration control provides jumper options to
independently control the polarity or "sense" of each
handshake line so as to further ease the interfacing
between the MDX-PIO and peripheral devices.
The MK3881, PIO para"el I/O controller is the heart
of the module. This circuit is a fully programmable
two port device which provides a wide range of configuration options. Anyone of four distinct modes of
operation can be selected for a port. They are byte
output, byte input, byte bidirectional (Port A only)
and bit control mode. The PIO also automatically generates a" handshaking signals in a" the above modes.
15
MDX-PIO BOARD
16
47n
MDX-PIO BLOCK DIAGRAM FOR
PI01 (PI02 IS IDENTICAL)
ROY
DATA BUFFER
1
(4)
PORT
A
(4)
UJ
i5
o
ADDRESS
DECODE
MK3B81
CXl
AND
6
DATA BUS
N
I-
UJ
PIO I
BUFFERS
CONTROL(9)
(4)
PORT B
(4)
ROY
The Pia permits total interrupt control so that full
usage of the MDX-CPU 1 interrupt capabilities can be
utilized durinq I/O transfers. Also the Pia can be programmed to interrupt the CPU on the occurrence of a
specified status condition in a specific periph-eral
device. The Pia circuit will provide vectored interrupts and maintain the daisy chain priority interrupt
logic compatible with the STD BUS.
The address decoding, interface and bus management
for the board are performed by the address decode
and data bus circuit. Each MDX-PIO port has two addresses, one for Control and one for Data. A total of
eight addresses are utilized per board. These addresses
are defined in the table below.
The circuitry for the other two ports provided by Pia
#2 is identical to Pia #1. The port configuration
logic, buffers, termination and pin out on connector
J-2 is duplicated for Pia #2. These two ports share the
address decode and data bus buffer circuitry with Pia
#1. The only differences are in the address decoding
as given in the port address table, and Pia #2 is lower
priority in the daisy chain interrupt structure.
ELECTRICAL SPECIFICATIONS
WORD SIZE:
Data: 8-bits
I/O Addressing: 8-bits
TABLE 1
I/O ADDRESSING:
Pia 1
PORT A
PORT B
Data
Control
XX08
XX18
XX28
XX38
Pia 2
PORT A
PORT B
XX48
XX58
XX68
XX78
The XX symbols stand for the upper 5 bits of the I/O
channel address. These bits are jumper selectable on
the MDX-PIO board in order to provide address
selectable,fully decoded ports.
On-board programmable - See Table 1
I/O CAPACITY:
Four parallel 8-bit ports. On board jumper, selectable
in 4 bit bytes as either In only, Out only, or Bidirectional. (Port 1A or 2A only) Automatic handshake
provided with each port.
17
SYSTEM CLOCK
INTERRUPTS
Vectored interrupts generated. Interrupt vector programmable upon initialization. Daisy chained interrupt priority. Selected bit channels can be masked
out under program control.
MDX-PIO
MDX-PIO-4
MIN
MAX
250KHz
250KHz
2.5 MHz
4.0 MHz
I/O DRIVERS
The following line drivers and terminations are all compatible with the I/O driver sockets on the MDX-PIO.
SIGNALS
TYPE
OUTPUT
SINK CURRENT (mA)
Address, Data
Bus & Control
74LS245
NI
Tri-State
Bidirectional
24
I/O Ports 1A
and 2A
*74LS244
NI
Tri-State
Bidirectional
24
74LS241
I
Tri-State
Bidirectional
24
*74LS243
NI
Tri-State
Bidirectional
24
74LS242
NI
Tri-State
Bidirectional
24
74L586
I/NI (strap
selectable)
8
I/O Ports 1B
and 2B
Handshake:
RDY
Note: I = inverting
N I = non-inverting
* These chips are supplied with the board. They may be exchanged with the other unit listed to provide the
alternate signal polarity.
TERMINATORS:
POWER SUPPLY REQUIREMENTS
1K ohm resistors on all I/O port lines.
+5
I
OPERATING TEMPERATURE RANGE
IKA.
~-------~~-------O
74LS8G
PARALLEL BUS INTERFACE-STD-Z80 BUS
COMPATIBLE
18
O°C to 50°C
MECHANICAL SPECIFICATIONS
47J\.
~[)~--~~------~~-RDY
Inputs
Bus Outputs
+5 volts ± 5% at 1.1 A max.
One 74LS Load Max.
IOH = -15mA min. at 2.4 volts
IOL = 24mA min. at 0.5 volts
CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
CONNECTORS
FUNCTION
CONFIGUI;{ATION
MATING CONNECTOR
STD-Z80 BUS
56 pin dual
Printed Circuit
Viking 3VH28/1 CE5
0.125 in. centers
Wire Wrap
Viking 3VH28/1CND5
Solder Lug
Viking 3VH28/1CN5
Parallel I/O
26 pin dual
0.100 in. center
Flat Ribbon
Ansley 609-2600M
Discrete Wires
Winchester PGB26A (housing)
Winchester 100-70020S (contacts)
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MDX-PIO
Module with Operation
Manual less mating
connectors. 2.5MHz version
MK77650
MDX-PIO-4
Module with Operation
Manual less mating connectors.
4.0 MHz version
MK77650-4
MDX-PIO Operations
Manual only
MK79606
MDX-PROTO
Data Sheet
MD Series prototyping
package data sheet
MK79605
AID-80F
Data Sheet
Data Sheet of disk based
development system for MD Series
MK78568
AIM-80
Data Sheet
Z80 In-circuit Emulation
module (2.5 MHz only)
MK78537
19
20
MOSTEI(.
MD SERIES MICROCOMPUTER MODULES
Seriallnput/Output Module (MDX-SIO)
FEATURES
o Two independent full-duplex channels
o Independent programmable Baud rate clocks
o Asynchronous data rates - 110 to 19.2K bits per
o
o
o
o
o
o
o
o
o
o
o
o
o
o
second
Receiver data registers quadruply buffered
Transmitter data registers double buffered
Asynchronous operation
Binary synchronous operation
HDLC or IBM SDLC operation
Both CRC-16 and CRC-CCITT (-0 and -1) hardware implemented
Modem control
Operates as DTE or DCE
Serial input and output as either RS-232 or 20mA
current loop
Current loop optically isolated
Current loop selectable for either active or passive
mode
Address programmable
4 MHz option
Compatible with STD-Z80 BUS
DESCRIPTION
The MD Series and the STD-Z80 BUS were designed
to satisfy the need for low cost OEM microcomputer
modules. The STD-Z80 BUS uses a motherboard
interconnect system concept and is designed to handie any MD Series card type in any slot. The modules
for the STD-Z80 BUS are a compact 4.5 x 6.5 inches
which provides for system partitioning by function
(RAM, EPROM, I/O). This smaller module size makes
system packaging easier while increasing MOS- LSI
densities providing high functional ity per modu Ie.
The MD Series of OEM microcomputer boards and
the STD-Z80 BUS offer the most cost effective
system configuration available to the OEM system
designer.
MDX-SIO DESCRIPTION
The Serial Input/Output Module, MDX-SIO, is
designed to be a multiprotocol asynchronous or synchronous I/O module for the STD-Z80 Bus. The
module is designed around the Mostek MK3884 Z80SIO which provides two full duplex, serial data channels. Each channel has an independent programmable
baud rate clock generator to increase module flexibility. The MOX-SIO is capable of handling asynchronous, synchronous, and synchronous bit oriented protocols such as IBM BiSync, IBM SDLC, HDLC and
virtually any other serial protocol. It can generate CRC
codes in any synchronous mode and can be programmed by the CPU for any traditional asynchronous
format. The serial input and output data are fully
buffered and are provided at the connector as either a
20m A current loop or RS-232-C levels. A modem
control section is also provided for handshaking and
status. The MDX-SIO module can be jumper configured as a data terminal (DTE) orasa modem (DCE) in
order to facilitate a variety of interface configurations.
Figure 1 is a block diagram of the MDX-SIO module.
It consists of five main elements. They are the
channel configuration headers, line drivers and receivers, MK3884 Z80-SI0, programmable Baud rate
generators, and address decode and data bus buffers.
Input and output to the board is provided via two 26
pin connectors. One connector is dedicated for each
channel.
Several features are available as options that are
selected via the channel configuration header. The
headers are used to select the orientation of the data
communication interface and the mode of the 20m A
current loop. The MDX-SIO can be selected to act as
either a terminal or processor (Data Terminal Equipment DTE) or as the modem (Data Communications
Equipment - DCE). The header allows reconfiguration
of both data interchange and modem control signals.
This allows increased flexibility necessary to link different hardware elements in OEM data link systems
and networks. The module is shipped from the
factory wired as a DTE interface.
The MDX-SIO has different selectable options for the
20mA current loop. The receiver and transmitter
functions can be reconfigured on the module to
allow for reorientation of these signals. Also the
receive and transmit circuits can be selected to
function in either an active or passive mode. In the
active mode, the MDX-SIO module provides the
20mA current source. In the passive mode, the
module requires that the loop current be provided.
The latter is the same mode as that of a Teletype.
21
MDX-SIO BOARD
22
MDX-SIO BLOCK DIAGRAM
FIGURE 1
CHANNEL A
RS 232 DATA
AND
MODEM CONTROL
20 MA SERIAL
INPUT/OUTPUT
ADDRESS
STD-Z80
BUS
DECODE
AND
CHANNEL B
DATA BUS
BUFFERS
20 MA SERIAL
INPUT /OUTPUT
RS232 DATA
AND
An E IA and 20mA current loop interface circuit is
used to provide the necessary level shifting and signal
conditioning between the MK3884 Z80-S10 and the
connector. These line drivers and receivers provide
the correct electrical signal levels, slew rate and impedance for interfacing RS-232C and 20mA current
loop peripherals. Additionally, optical isolation is
provided for both transmit and receive circuits in the
20mA current loop mode.
The Mostek MK3884 Z80-S10 is the central element
of this module. This device is a multifunction component designed to satisfy a wide variety of serial data
communications requirements in microcomputer systems. Its basic role is that of a serial to parallel,
parallel to serial converter/controller but within that
role it is configured by software programming so that
its function can be optimized for a given serial data
communications application. The MK3884 provides
two independent full duplex channels; A and B.
•
•
Asynchronous operation (Channel A and B)
- 5, 6, 7, or 8 bits/character
- 1, 1 Y, or 2 stop bits
- Even, odd or no parity
- x1, x16, x32 and x64 clock modes
- Break generation and detection
- Parity, Overrun and Framing error detection
Binary Synchronous operation (Channel A only)
- One or two Sync characters in separate registers
- Automatic Sync character insertion
- CRC generation and checking
•
HDLC or IBM SDLC operation (Channel A only)
- Automatic Zero insertion and deletion
- Automatic Flag Insertion
- Address field recognition
- I-Field residue handling
- Valid receive messages protected from overrun
- CRC generation and checking
The MK3884 also provides modem control inputs and
outputs as well as daisy chain priority interrupt logic.
Eight different interrupt vectors are generated by the
SID in response to various conditions affecting the
data communications channel transmission and reception.
Address decoding, STD-Z80 BUS interface and bus
management for the module are performed by the
Address Decode and Data Bus circuit. The MDX-SIO
contains command registers that are programmed to
select the desired operational mode. The addressing
scheme is as follows:
XXXXX 00
XXXXX 01
Channel A Data'
Channel A Control Status
XXXXX 10
XXXXX 11
Channel B Data
Channel B Control Status
The X indicates the binary code necessary to represent which of the 64 port addresses is selected by on
board strapping.
Each channel has an individual programmable' Baud
rate generator. The X 1 multiplier on the Z80-S10
23
must be used in the synchronous mode. The X16,
X32, or X64 Z80-S10 clock rate can be specified for
the asynchronous mode. Table 1 indicates the possible Baud rates available for both operation modes
with the Z80-S10 Data Rate multipliers.
SYSTEM'CLOCK
MDX-SIO
MDX-SI0-4
MIN
MAX
250KHz
250KHz
2.5 MHz
4.0 MHz
Figure 1
BAUD RATE (HZ)
SYNCHRONOUS
ASYNCHRONOUS
Xl
800
1200
1760
2152
2400
4800
9600
19200
28800
32000
38400
57600
76800
115200
153600
307200
X16
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
SERIAL COMMUNICATION INTERFACE
X32
X64
25
37.5
55
67.25
75
150
300
600
900
1000
1200
1800
2400
3600
4800
9600
12.5
18.75
27.50
33.63
37.50
75
150
300
450
500
600
900
1200
1800
2400
4800
20m A
LOOP
SIGNAL
Transmitted data Output
Received data
Input
Data Terminal
Ready (DTR)
Request to Send
(RTS)
Clear to Send (CTS)
Carrier Detect
(CDET)
RS-232-C
Output
Input
Input/Output
Input/Output
Output/Input
Output/Input
PARALLEL BUS INTERFACE - STD-Z80 BUS
COMPATIBLE
Inputs
Bus Outputs
One 74LS load max.
10H = -15mA min at 2.4 Volts
10L = 24mA min at 0.5Volts
ELECTRICAL SPECIFICATIONS
WORD SIZE
POWER SUPPLY REQUIREMENTS
Data: 8-bits
I/O addressing: 8-bits
+12 volts ± 5% at 72 mA max.
-12 volts ± 5% at 46 mA max.
+5 volts ± 5% at 650 mA max.
I/O ADDRESSING
On board upper six bits programmable
I/O CAPACITY
OPERATING TEMPERATURE
O°C to 50°C
MECHANICAL SPECIFICATIONS
Serial - Two full duplex serial ports. Channel A is
capable of synchronous and asynchronous operation.
Channel B is asynchronous only. Special control registers and 'circuitry to permit implementation of
SO LC, BiSync, MonoSync, H 0 LC. Other formats can
be programmed on Channel A only.
CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
SERIAL BAtJD RATES
CONNECTORS
See Table 1
FUNCTION
CONFIGURATION
INTERRUPTS
Generates vectored interrupts to 8 different locations
corresponding to conditions within both channels.
Interrupt vector location programmable. Daisy
chained priority hardware interrupt circuitry.
24
STD-Z80
BUS
56 pin
0.125 in. centers
MATING
CONNECTOR
Printed Circuit
Viking 3VH28/
1CE5
Wire Wrap
Viking 3VH28/
lCND5
Solder Lug
Viking 3VH28/
1CN5
CONNECTORS Cont'd.
SERIAL I/O
26 pin
0.100 in. center
Flat Ribbon
Ansley 6092600M
Discrete Wires;
WINCHESTER
PGB26A
(housing)
WINCHESTER
100-70020S
(contacts)
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MDX-SIO
Dual channel, Full-Duplex Serial
I/O Module less mating connectors with
Operations Manual. 2.5MHz version.
MK77651
MDX-SI0-4
Module with Operations
Manual less mating connectors.
4.0MHz version
MK77651-4
MDX-SIO Operations Manual
MK79608
MDX-PROTO
Data Sheet
MD Series Prototyping
Package
MK79605
AID-80F
Data Sheet
Disk based development
system for M D series
MK78568
AIM-80
Data Sheet
Z80 In-circuit Emulation
module (2.5 MHz only)
MK78537
25
26
MOSTEI(.
MD SERIES MICROCOMPUTER MODULES
Z80 Microcomputer Debug Module (MDX-DEBUG)
HARDWARE FEATURES
MD SERIES GENERAL DESCRIPTION
o
o
o
o
The MD Series and the STD-Z80 BUS were designed
to satisfy the need for low cost OEM microcomputer
modules. The STD-Z80 BUS uses a motherboard
interconnect system concept and is designed to handle any MD Series card type in any slot. The modules
for the STD-Z80 BUS are a compact 4.5 x 6.5 inches
which provides for system partitioning by function
(RAM, EPROM, I/O). This smaller module size makes
system packaging easier while increasing MOS-LSI
densities provide high functionality per module.
STD-Z80 BUS compatible
4 MHz version available
Serial I/O Channel
10K bytes of ROiVI contain the following firmware: DDT-80, ASMB-80
DEBUGGER FEATURES
o
o
o
o
Z80 Operating System with debug capability
Channelized I/O for versatility
I/O peripheral drivers supplied
ROM based
TEXT EDITOR FEATURES
o Input and modification of ASCI I Text
o
o
o
Line and character editing
Alternate command buffers for pseudo-macro
command capability
ROM based
ASSEMBLER FEATURES
o Assembles all Z80 mnemonics
o
o
o
o
Object output in industry standard hexadecimal
format extended for Relocatable and Linkable
Programs
Over fifteen pseudo-ops
Two-pass assembly
ROM based
LINKING LOADER FEATURES
o Loads into memory both relocatable and nonrelocatable object output of the assembler
o Loads Relocatable modules anywhere in memory
o Automatically provides linkage of global symbols
between object modules as they are loaded
o Prints system load map
o ROM based
The MD Series of OEM microcomputer boards and
the STD-Z80 BUS offer the most cost effective
system configuration available to the OEM system
designer.
HARDWARE DESCRIPTION
The MDX-DEBUG module has sockets for 10K bytes
of masked ROM that are filled with a Z80 firmware
package (DDT-80/ASMB-80). This module has a STDZ80 BUS interface and is available in both 2.5MHz
and 4.0MHz versions. Included on-board is a fully
buffered asynchronous I/O port capable of 110-19200
Baud rates. Serial data interfaces are available for
20mA current loop (with reader step control) and
RS-232. The on-board Baud Rate Generator is selectable to all common Baud rates from 110 to 19,200
Baud.
FIRMWARE DESCRIPTION
DEBUGGER DESCRIPTION
DDT-80 is the Operating System for the MDXDEBUG Module. It resides in a 2K ROM (MK34000
series) resident on the MDX-DEBUG Module. It provides the necessary tools and techniques to operate
the system, i.e., to efficiently and conveniently perform the tasks necessary to develop microcomputer
software. DDT-80 is designed to support the user
from initial design through production testing. It
allows the user to display and update memory, registers, and ports, load and dump object files, set breakpoints, copy blocks of memory, and execute programs.
27
MDX-DEBUG BLOCK DIAGRAM
ADDRESS
J
\/
\=)
BUS
INTERFACE
MEMORY
~ELECTION
LOGIC
LOGIC
AND CONTROL
-.
BUS
V
ROM FIRMWARE
DDT·BO AND ASM&8C
PORT
SELECTION
LOGIC
~
UART
~
RS-232
AND
20 MA
BUFFERS
-
V
DATA
¢:J
¢=/
20MA INPUT
OUTPUT AND
READER STEP
RS·232
INPUT. OUTPUT
AND
MODEM CONTROL
BUS
L99627
DDT-80 COMMAND SUMMARY
Display and/or update the contents of
memory location s.
Tabulate the contents to memory locaM s, f
tions s through f.
Display and/or update the content of
Ps
I/O port s.
D s, f
Dump the contents of memory locations s through f in a format suitable to
be read by the L command.
Load, into memory, data which is in
L
the appropriate format.
Es
Transfer control from DDT-80 to a
user's program starting at location s.
H
Perform 16 bit hexadecimal addition
and/or subtraction.
C s, f, d
Copy the contents of memory locations
s through f to another location in memo
ory starting at location d.
Insert a breakpoint in the user's proBs
gram (must be in RAM) at location s
which transfers control back to DDT80. This allows the user to intercept his
program at a specific point (location s)
and examine memory and CPU registers
to determine if this program is working
correctly.
R
Display the contents of the user registers.
The s, f, and d represent start, finish, and destination
operands required for each command.
MEMORY, PORT AND REGISTER COMMANDS
(M, P, R)
Ms
28
The M, P, and R commands provide the means for
displaying the contents of specified memory locations, port addresses, or CPU registers. The M and P
commands sequentially access memory locations or
ports and display their contents. The user has the
option of updating the content of the memory location or port. (Note some ports are output only and
their contents cannot be displayed). The M command
also gives the user access to the CPU registers through
an area in RAM called the Register Map (discussed in
the Execute, Breakpoint section below).
The M and R commands are used to tabulate blocks
of memory locations (M) or the CPU registers (R).
The M command will accept two operands, the starting and ending address of the memory block to be
tabulated. The R command will accept either no
operand or one. If no operand is specified, the CPU
registers will be displayed without a heading. If an
operand is specified then a heading which labels the
registers contents will be displayed as well.
EXECUTE AND BREAKPOINT (E, B)
The E command is used to execute all programs,
including aids such as the Assembler. The B command
is used to set a breakpoint to exit from a program at
some predetermined location for debugging purposes.
At the instant of a breakpoint exit, the contents of all
CPU register are saved in a designated area of MDXDEBUG RAM called the Register Map. In the Register Map, the register contents may be examined or
modified using the M command and a predefined
mnemonic (or absolute address) of the storage location for that register (example :PC, :A, ... , :SP). The
Register Map is also used to initialize the CPU registers whenever execution is initiated or resumed. Thus
the E and B commands can be used together to initialize, execute, and examine the results of individual
program segments.
The B command gives the user the option of having
all CPU registers displayed when the breakpoint is encountered. This is done by entering a second operand
to the B command. Otherwise DDT-80 defaults to
displaying the PC and AF registers. When all CPU registers are displayed, the format is the same as for the
R command previously discussed.
LOAD, DUMP, AND COPY (L, D, C)
The Land D commands load and dump object files
through the object I/O channel in standard Intel Hex
format. Checksums are used for error detection, and
the addresses of questionable blocks are typed automatically while loading.
The C command will copy the contents of the memory block specified to another block of memory.
There are no restrictions on the direction of the copy
or on whether the blocks overlap.
HEXADECIMAL ARITHMETIC (H)
The H command is a dummy command used to allow
hexadecimal addition and subtraction for expression
evaluation without performing any other operation.
DDT-80 I/O CAPABILITIES
DDT-80 specifies I/O channels, designated 'Console',
'Object', and 'Source', to which any suitable devices
may be assigned. The Channel Assignment Table is
located in MDX-DRAM where it maybe examined or
modified using the M command. The table addresses
correspond to the I/O channels and the table contents
correspond to the addresses of the peripheral driver
routines. A channel which has a device assignment
may have that device assignment changed using the M
command. This is accomplished by merely modifying
the table contents of that channel's table address to
correspond to the new peripheral driver routine. A set
of peripheral driver routines is supplied and listed below. This scheme also allows the user to write a driver
routine for his own peripheral, load it into memory,
and easily configure that peripheral into the system.
DDT-SO I/O PERIPHERAL DRIVERS
1. A serial input driver (usually a keyboard).
2. A serial output driver (usually a CRT or teletype
typehead).
3. A serial input driver wh ich sends out a reader step
signal (usually a teletype reader).
4. A serial output driver which forces a delay after a
carriage return (usually a Silent 700 typehead).
5. A parallel input driver (usually for high speed
paper tape input).
6. A parallel output driver (usually for high speed
paper tape output).
7. A parallel output driver (usually for a line
printer).
TEXT EDITOR DESCRIPTION
The Text Editor permits random access editing of
ASCII character strings. It can be used as a line or
character oriented editor. Individual characters may
be located by position or context. The Editor works
on blocks of characters which are typically read into
memory from magnetic tape or paper tape. Each
edited block can be output to magnetic tape or paper
tape after editing is completed. While the primary
application for the Text Editor is in editing assembly
language source statements, it may be applied to any
ASCII text delimited by "carriage returns".
The Editor has a macro command processing option.
Up to two sets of commands may be stored and processed at any time during the editing process.
All I/O is done via the DDT-80 channels. The Editor
can be used with the MOSTEK ASMB-80 Assembler
and Loader to edit, assemble, and load programs in
memory without the need for external media for
intermediate storage.
The following
Editor:
AnBn Cn dS1dS2dDnE-
1Ln Mn N-
Pn -
RSn dS1d-
commands are recognized by the Text
Advance record pointer n records
Backup record pointer n records
Change string S1 to string S2 for n
occurrences
Delete next n records
Exchange current record with records
to be inserted
I nsert records
Go to line number n
Enter command buffers (pseudomacro)
Print top, bottom, and current line
number
Punch n records from buffer
Read source records into buffer
Search for nth occurrence of string S1
29
ASSEMBLER DESCRIPTION
The Assembler reads Z80 source mnemonics and
pseudo-ops and outputs an assembly listirig and
object code. The assembly listing shows address,
machine code, statement number, and source statement. The object code is in industry standard hexadecimal format modified for relocatable, linkable
assemblies.
The Assembler supports conditional assemblies,
global symbols, relocatable programs, and a printed
symbol table. It can assemble any length program,
limited only by a symbol table size which is user
selectable. Expressions involving addition and subtraction are allowed. A global symbol is categorized
as "internal" if it appears as a label in the program;
otherwise it is an "external" symbol. The printed
symbol table shows which symbols are internal and
which are external. The Assembler allows the user to
select relocatable or non-relocatable assembly via the
"PSECT" pseudo-op. Relocation records are placed in
the object output for relocatable assemblies (the
MOSTEK object format is defined below). The
Assembler can be run as a single pass assembler or as a
learning tool. (In this mode, global symbols and forward references are not allowed).
The following pseudo-ops are recognized by the
Assembler:
ORG program origin
EQU equate label
DEFL define label
DEFM define message
DEFB define byte
DEFW define word
DEFS defi ne storage
END end statement
NAME program name definition
PSECT program section definition
GLOBAL
global symbol definition Supports the
following assembler pseudo-ops
EJECT eject a page of listing
TITLE place heading at top of each page
LIST turn listing on
NLiST turn listing off
RELOCATING LINKING LOADER DESCRIPTION
The MOSTEK Relocating Linking Loader provides
state-of-the-art capability for loading programs into
memory by allowing loading and linking of any number of relocatable and non-relocatable object
modules. Non-relocatable modules are always loaded
at their starting address as defined by the ORG
pseudo-op during assembly. Relocatable object
modules can be positioned anywhere in memory at an
offset add ress.
30
The Loader automatically links and relocates global
symbols which are used to provide communication or
linkage between program modules. As object programs are loaded, a table containing global symbol
references and definitions is built up. At the end of
each module, the loader resolves all references to global Symbols which are defined by the current or a
previously loaded module. It also prints on the console device the number of defined global symbols that
have been referenced. The symbol table can be
printed to list all global symbols and their load address. The number of object modules which can be
loaded by the Loader is limited only by the amount
of MDX-RAM available for the modules and the symbol table .. Space for the symbol table is allocated
dynamically downward in memory from either the
top of memory or from a specified address entered as
an operand of the load command.
All I/O is done via the DDT-80 channels. Assemblies
can be done from source statements stored in memory (by the Editor). The object output can be
directed to a memory buffer rather than to an external device. Thus, assembly and loading can be done
without external storage media.
The Loader prints the beginning and ending address
of each module as it is loaded. The transfer address as
defined by the END pseudo-ops is printed for the
first module loaded. The Loader execute command
(E) can be used to automatically start execution at
the transfer address.
The Loader Commands are the following:
L offset load object module at address "offset" plus program origin address
E
execute loaded program at transfer
address of first module
T
print global symbol table
MOSTEK OBJECT OUTPUT DEFINITION
Each record of an object module begins with a delimiter (colon or dollar sign) and ends with carriage
return and line feed. A colon (:) is used for data records and the end-of-file record. A dollar sign ($) is
used for records containing relocation information
and linkirig information. All information is in ASCII.
Each record is identified by "type". The type is determined by the 8th and 9th bytes of the record
which can take the following values:
00
01
02
03
04
05
- data
- end-of-file
- internal symbol
- external symbol
- relocation information
- module definition
rOW"'' "
1
··
2
#
of
BINARY
3
RECORD TYPE
4
5
6
7
II
8
9
0
START ADDRESS
OF DATA
DATA BYTES
0
0
CHECK
SUMG)
..• DATA•.•
I
··
0
TRANSFER ADDRESS
OF MODULE
0
0
I
....I..
0
•
0
0
0
MODULE NAME
I
CHECK
SUMG)
LINK
AD~RESS0
I
4
0
.
I
$
3
0
I
G)
ADDRESS
I
I
of
BINARY
BYTES
.
CHECK
SUMG)
I
EXTERNAL
SYMBOL NAME
#
2
0
,
CHECK
SUMG)
I
INTERNAL
SYMBOL NAME
$
1
·
I
I
I
$
$
10
I
ADDRESSES WHICH
.•. REQUIRE RELOCATION •.•
CHECK
SUMG)
•
5
0
L
....I..
.. 1.
FLAGS
0
CHECK
SUMG)
•
NOTES:
1. Check Sum is negative of the binary sum of all bytes except delimiter and carriage return/line feed.
2. Link Address points to last address in the data which uses the external symbol. This starts a backward link list through the data records for that
external symbol. The list terminates at OFFFFH.
3. The flags are one binary byte. Bit 0 is defined as:
o -absolute module
1 - relocatable module
4. Maximum of 64 ASCII bytes.
ELECTRICAL SPECIFICATIONS
SERIAL COMMUNICATIONS INTERFACE
I/O TRANSFER RATE
SIGNAL
BUFFERED FOR:
20mA Current Loop
RS-232
Transmitted data
Received data
Data Terminal Ready (DTR)
Request to Send (RTS)
Carrier Detect (CDET)
Clear to Send (CTS)
Data Set Ready (DSR)
Reader Step relay (RS)
Output
Input
X16 Baud Rate Clock
1,760
4,800
9,600
19,200
38,400
76,800
153,600
307,200
Baud Rate (Hz)
110
300
600
1,200
2,400
4,800
9,600
19,200
Output
Input
Input
Input
Output
Output
Output
Output
(40mA)
SERIAL COMMUNICATIONS CHARACTERISTICS
PARALLEL BUS INTERFACE-STD-Z80 BUS
COMPATIBLE
Asynchronous
Full duplex operation
Start bit verification
Data word size variable from 5 to 8
bits.
One or two stop bits
Odd, even, or no parity
One word buffering on both transmit
and on receive.
Inputs
Bus Outputs
One 74LS load Max
IOH = -15mA min at
2.4 Volts
IOL = 24mA min at
0.5 Volts
31
CONNECTORS
I/O ADDRESSING
On-board Serial I/O Port
Control Port DDH·
Data Port
DCH
Module and Reader Step Control Port DEH
FUNCTION
CONFIGURATION
STD BUS
56 pin dual read out
SYSTEM CLOCK
0.125 in. centers
MDX-DEBUG
MDX-DEBUG-4
1.25MHz
1.25MHz
2.5MHz
4.0MHz
POWER SUPPLY REQUIREMENT
+12 Volts ± 5% at 50 rnA max.
-12 Volts ± 5% at 35 rnA max.
+5 Volts ± 5% at 1.2 A max.
Serial I/O
26 pin dual readout
0.100 in. grid
OPERATING TEMPERATURE
MECHANICAL SPECIFICATIONS
CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MDX-DEBUG
Module with 10K bytes of firmware
and Operations Manual. No mating
connectors. 2.5MHz version.
MK77950
MDX-DEBUG-4
Module with 10K bytes of firmware
and Operations Manual. No mating
connectors. 4.0MHz version
MK77950-4
MDX-DEBUG Operations
Manual only
MK79611
Program Source Listing
of 10K byte firmware package
(DDT/ASMB-80) including comments
and flow charts. (Available free with
purchase of either MDX-DEBUG
Module).
MK78536
and
MK78534
MDX-PROTO
Data Sheet
MD Series Prototyping package
MK79605
AID-80F
Data Sheet
Disk based development system
for MD Series
MK78568
AIM-80
Data Sheet
Z80 In-circuit emulation module
12.5MHz onlvl
MK78537
32
MATING
CONNECTOR
Printed Circuit
Viking 3VH28/
lCE5
Wire Wrap
Viking 3VH28/
lCND5
Solder Lug
Viking 3VH28/
lCN5
Flat Ribbon
Ansley 6092600M
Discrete Wires
Winchester
PGB26A
(housing)
Winchester
100-70020S
(contacts)
* The DDT-80 and ASMB-80 listings are available directly from MOSTEK by filling out a copy of the
Software Licensing Agreement printed on the opposite page of this data sheet and returning it with
the appropriate payment of Customer Purchase Order
to:
MOSTEK CORPORATION
Microcomputer Systems Div.
1215 West Crosby Road
Carrollton, Texas 75006
33
1.
2.
3.
4.
5.
6.
STANDARD SOFTWARE LICENSE AGREEMENT
All Mostek Corporation products are sold
on condition that the Purchaser agrees to
the following terms:
The Purchaser agrees not to sell, provide, give alivay, or otherwise make available to any unauthorized
persons, all or any part of, the Mostek software products listed below; including, but not restricted
to: object code, source code and program listings.
The Purchaser may at any time demonstrate the normal operation of the Mostek software product
to any person.
All software designed, developed and generated independently of, and not based on, Mostek's software by purchaser shall become the sole property of purchaser and shall be excluded from the
provisions of this Agreement. Mostek's software which is modified with the written permission of
Mostek and which is modified to such an extent that Mostek agrees that it is not recognizable as
Mostek's software shall become the sole property of purchaser.
Purchaser shall be notified by Mostek of all updates and modifications made by Mostek for a oneyear period after purchase of said Mostek software product. Updated and/or modified software and
manuals will be supplied at the current cataloged prices.
In no event will Mostek be held liable for any loss, expense or damage, of any kind whatsoever,
direct or indirect, regardless of whether such arises out of the law of torts or contracts, or Mostek's
negligence, including incidental damages, consequential damages and lost profits, arising out of or
connected in any manner with any of Mostek's software products described below.
MOSTEK MAKES NO WARRANTIES OF ANY KIND, WHETHER STATUTORY, WRITTEN,
ORAL, EXPRESSED OR IMPLIED (INCLUDING WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY AND WARRANTIES ARISING FROM COURSE
OF DEALING OR USAGE OF TRADE) WITH RESPECT TO THE SOFTWARE DESCRIBED
BELOW.
The Following Software Products Subject to this Agreement:
Order Number
Description
Ship To:
Price*
Bill To:
--------------------------------------------------------------
Method of Shipment:
Customer P.O. Number
Agreed To:
----------------------PURCHASER
MOSTEK CORPORATION
By:
By:
Titl-e-:- - - - - - - - - - - - - - - - - Titl-e-:- - - - - - - - - - - - - - - - - - Date:
• Prices Subject to Change Without Notice
34
Date:
MOSTEJ(.
MD SERIES MICROCOMPUTER MODULES
zao Single Step Module (MDX-SST)
FEATURES
o Hardware single-step capability
o Compatible with DDT-80 Operating System
STD-Z80 BUS compatible
o
DESCRIPTION
The MD Series andtheSTD BUS were designed for lowcost OEM microcomputer modules. The STD BUS uses a
motherboard interconnect system concept and is
designed to handle any MD Series Card type in any slot.
The modules for the STD BUS are a compact 4.5 x 6.5
inches which provide for system partitioning byfunction
(RAM, EPROM, 1/0). This smaller module size makes
system packaging easier, while increasing MOS-LSI
densities provide high functionality per module.
The MD Series of OEM microcomputer boards and the
STD BUS offer the most cost-effective system
configuration available to the OEM system designer.
MDX-SST DESCRIPTION
The MOSTEK MDX-SST was designed to enhance the
hardware and software debug capability for MD Series
systems. The use of the MDX-SSTwith the MDX-CPU1
and MDX-DEBUG boards allows the user to single-step
instructions through RAM andlor EPROM/ROM with
the capability of displaying all of the MDX-CPU 1
registers on each instruction execution.
The MDX-SST board is implemented using the MDXCPU1 's nonmaskable interrupt and is controlled by
firmware from the keyboard. When the command to
single step an instruction is given, the sequence of
events is the same as executing a program except that a
"1" is output to the single step control port (DFH)
instead of a "0". The circuit decodes the double M 1
instructions (CBH, DDH, EDH, or FDH) and M 1 is used to
clock a shift register circuit which (if a "1" is output to
port DFH) generates a nonmaskable interrupt at the
start of the instruction to be single stepped. The
nonmaskable interrupt saves the address of execution
on the stack and causes the next instruction to be
fetched from address E066H. The shift register is
clocked twice after the nonmaskable interrupt, causing
the signal DEBUG to go low, forcing "E" on the most
significant address lines, and causing the instruction to
be fetched from the E066H in the operating system
DDT -80. The operating system then jumps to E069H,
clears the debug flip-flop by reading PORT DFH, saves
the MDX-CPU1 registers in the MDX-CPU1 scratch
RAM, and waits for the next command.
The single-step command is implemented in DDT-80
which resides on the MDX-DEBUG board and has the
following format:
S COMMAND, Single-step
This command allows the user to start single-stepping
from a given location for a given number of instructions
and to display the CPU registers after each step.
Format:
.S aaaa,nn,b(cr)
.S aaaa,nn (cr)
.S aaaa (cr)
.S (cr)
start single-stepping at location aaaa
for nn steps or instructions. If b=O,
display only the PC and AF registers,
if b#O, display all the CPU registers.
the same as above with b = 0
assumed.
the same as above with nn= 1 and
b=O assumed .
the same as above with nn= 1 and
b=O assumed; aaaa is set equal tothe
contents of the user's PC.
The use of the MDX-SST board requires the MDX-CPU1
and the MDX-DEBUG.
ELECTRICAL SPECIFICATIONS
PORT ADDRESS (HEX)
DF
35
MDX-SST BLOCK DIAGRAM
I
DATA BUS
Do-D7
"
~
PORT
DECOt>E
~
CONTROL BUS ...
IIORQ.WR.RD.M I ~
SYSTEM CLOCK
MIN
500KHz
Pin
46
I
DEBUG
Pin
38
INSTRUCTION
DETECTOR
~
DOUBLE
OP CODE
DETECT
ADDRESS BUS-"
I
Ao-A7
.)
~
IRQ
NM
t
I
CONNECTOR CONTINUED
MAX
4.00MHz
PARALLEL BUS INTERFACE
STO-Z80 BUS COMPATIBLE
Wire Wrap
Viking
3VH281
1CND5
Solder Lug
Viking
3VH281
1CN5
POWER SUPPLY REQUIREMENTS
+5Vdc @ 85mA
OPERATING TEMPERATURE
ORDERING INFORMATION
MECHANICAL SPECIFICATIONS
DESIGNATOR
DESCRIPTION
PART NO.
CARD DIMENSIONS
MDX-SST
Single Step
Module
MK77958
4.5 in (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
MDX-SST
Operations
Manual
MK79638
MDX-PROTO
data sheet
MD Series Protyping package
MK79605
AIM-80
data sheet
Z80 In-circuit
Emulation module
(2.5 MHz only)
MK78537
CONNECTORS
FUNCTION
CONFIGURATION MATING
CONNECTOR
STO BUS
56 pin
0.125 in. centers
36
Printed Circuit Viking
3VH28/1CE5
MOSTEI(.
MD SERIES MICROCOMPUTER MODULES
Prototyping Package (MDX-PROTO)
FEATURES
o 8-slot card cage with mother board (MK77954)
o MDX-CPU1 module (MK77850)
o MDX-DRAM8 module (MK77750)
o MDX-DEBUG module (MK77950)
o MD-WW2 Wire wrap board (MK77952)
o MD-EXT Extender board (MK77593)
o Cables for RS232 device (MK77955)
or TIY (MK77956)
o 4MHz option available (MDX-PROTO-4)
o STD BUS compatible
DESCRIPTION
The MD Series and the STD BUS were designed to
satisfy the need for low-cost OEM microcomputer
modules. The STD BUS uses a mother board
interconnect system concept and is designed to handle
any MD Series Card type in any slot. The modules forthe
STD BUS are a compact 4.5 x 6.5 inches which provide
for system partitioning by function (RAM, EPROM, 1/0).
This smaller module size makes system packaging
easier while increasing MOS-LSI densities provide high
functionality per module.
The MD Series of OEM microcomputer boards and the
STD BUS offer the most cost-effective system
configuration available to the OEM system designer.
On-board memory is provided in the form of 4K of
EPROM (2-2716's) and 256 bytes of scratchpad RAM as
pictured in the block diagram. In addition, a MK3882
Counter Time Circuit is included on the MDX-CPU1 to
provide counting and timing functions for the Z80.
Either 2716 EPROM can be located at any 2K boundary
within any given 16K block intheZ80 memory map via a
jumper arrangement.
The MDX-CPU1 can be used in conjunction with the
MDX-DEBUG and MDX-DRAM modules to utilize DDT80 and ASMB-80 in system development. This is
accomplished by strapping the scratchpad RAM to
reside at location FFOO so that it will act as the
Operating System RAM for DDT -80.
MDX-PROTO DESCRIPTION
HARDWARE DESCRIPTION
MDX-CPU1 DESCRIPTION
The MOSTEK MDX-CPU1 is the heart of an MD Series
Z80 system. Based on the powerful Z80
microprocessor, the MDX-CPU1 can be used with great
versatility in an OEM microcomputer system
application. This is done simply by inserting custom
ROM or EPROM memories into the sockets provided on
the board and configuring them virtually anywhere
within the Z80 memory map.
The MDX-CPU1 is also available in 4MHzversion (MDXCPU 1 -4). In this version, one wait cycle is automatically
inserted each time on-board memory is accessed by a
read or write cycle. This is necessary to make the access
times of the 2716 PROMs and the 3539 scratchpad
RAM compatible with MK3880-4 4MHz ZSO-CPU.
MDX-DRAM DESCRIPTION
The MDX-DRAM is designed to be a RAM memory
expansion board for the MOSTEK MD SERIES of ZSO
based microcomputers. It is available in three memory
capacities: SK bytes (MDX-DRAMS), 16K bytes (MDX-
37
BLOCK DIAGRAM MDX-PROTO
STD
zeo
BUS
161("16-_I08·~ZK.'16·1,II(411
,uMoSI6-f111(4116:
L:=::::::>f iW
MDX-CPU I
DRAM 16), and 32K bytes (MDX-DRAM32).
Additionally, the MDX-DRAM16 and the .MDXDRAM32 are available in a 4MHz version. Thus, the
designer can choose from the various options to tailor
his add-on dynamic RAM directly to his system
requirements.
The MDX-DRAMS is designed using MOSTEK's
MK410S S,192-bit dynamic RAM. The MDX-DRAM32
utilizes high-performance MK4116, 16K-bit dynamic
RAMs wh ich allow 4M Hz versions of these boards to be
offered. No wait-state insertion circuitry is required on
'
any of the RAM cards.
Address selection is provided on all MDX-DRAM cards
for positioning the SK, 16K, or 32K of memory to starton
any 4K boundary.
MDX-DRAM
20MA INPUT,
OUTPUT 'ANO
READER STEP
RS-232
INPUT,OUTPUT
AND MODEM
CONTROL
MDX-DEBUG
FIRMWARE DESCRIPTION
DEBUGGER DESCRIPTION
DDT-SO is the Operating System for the MDX-DEBUG
Module. It resides in a 2K ROM (MK34000 series)
resident on the MDX-DEBUG Module. It provides the
necessary tools and techniques to operate the system,
i.e" to efficiency and conveniently develop microcomputer software. DDT-SO is designed to support the
user from initial design through production testing. It
allows the user to display and update memory,
registers, and ports, load and dump object files, set
breakpoints, copy blocks of memory, and execute
programs.
DDT-SO COMMAND SUMMARY
MDX-DEBUG DESCRIPTION
M s
The MDX-DEBUG Module has sockets for 10K bytes of
masked ROM that are populated with a ZSO firmware
package (DDT-SO/ASMB-SO). This module has a STD
BUS interface and is available in both 2.5MHz and
4.0MHz versions. Included on board is a fully buffered
asynchronous 1/0 port capable of 110-19200 Baud
Rates. Serial Data interfaces are available for 20mA
current loop (with reader step control) and RS-232. The
on-board Baud Rate Generator is selectable to all
common Baud Rates from 110 to 19,200 Baud.
M s, f
38
'
Ps
D s,f
L
Es
- Display andlor update the contents of
memory location s.
- Tabu late the contents of memory locations s
through f.
- Display andlor update the contents of 1/0
port s.
- Dump the contents of memory locations s
through f in a format suitable to read by the
L command.
- Load, into memory, data which is in the
appropriate format.
- Transfer control from DDT-SO to a user's
program starting at location s.
H
C s,f,d
B
R
s
- Perform 16-bit hexadecimal addition and/or
subtraction.
- Copy the contents of memory locations s
through f to another location in memory
starting at location d.
- Insert a breakpoint in the user's program
(must be in RAM) at location s which
transfers control back to DDT-80. This
allows the user to intercept his program at a
specific point (location s) and examine
memory and CPU registers to determine if
this program is working correctly.
- Display the contents of user registers.
The s,f, and d represent start, finish, and destination
operands required for each command.
registers are displayed, the format is the same as for the
R command previously discussed.
LOAD, DUMP, AND COPY, (L,D,C)
The Land D commands load and dump object files
through the object I/O channel in standard Intel Hex
format. Checksums are used for error detection, and the
addresses of questionable blocks are typed
automatically while loading.
The C command will copy the contents of the memory
block specified to another block of memory. There are no
restrictions on the direction of the copy or on whether
the blocks overlap.
HEXADECIMAL ARITHMETIC (H)
MEMORY, PORT AND REGISTER COMMANDS
(M,P,R)
The M, p, and R commands provide the means for
displaying the contents of specified memory location,
port addresses, or CPU registers. The M and P
commands sequentially access memory locations or
ports and display their contents. The user has the option
of updating the content of the memory location or port.
(Note some ports are output only and their contents
cannot be read or displayed). The M command also gives
the user access to the CPU registers through an area in
RAM called the Register Map (discussed in the Execute,
Breakpoint section below).
The M and R commands are used to tabulate blocks of
memory locations (M) or the CPU registers (R). The M
command will accept two operands, the starting and
ending addresses of the memory block to tabulated. The
R command will accept either no operand or one. If no
operand is specified, the CPU registers will be displayed
without a heading. If an operand is specified then a
heading which labels the register contents will be
displayed as well.
The H command is a dummy command used to allow
hexadecimal addition and subtraction for expression
evaluation without performing any other operation.
DDT-SO I/O CAPABILITIES
DDT-80 specifies I/O channels, designated 'Console',
'Object', and 'Source', to which any suitable devices
may be assigned. The Channel Assignment Table .is
located in MDX-RAM where it may be examinec1 or
modified using the M command. The table addresses
correspond to the I/O channels and the table contents
correspond to the addresses of the peripheral driver
routines. A channel which has a device assignment may
have that device assignment changed using the M
command. This is accomplished by merely modifying
the table contents of that channel's table address to
correspond to the new peripheral driver routine. A set of
peripheral driver routines is supplied and listed below.
This scheme also allows the user to write a. driver
routine for his own peripheral, load it into memory, and
easily configure that peripheral into the system.
DDT-80 I/O PERIPHERAL DRIVERS
EXECUTE AND BREAKPOINT (E,B).
The E command is used to execute all programs,
including aids such as the Assembler. The B command
is used to set a breakpoint to exit from a program at
some predetermined location for debugging purposes.
At the instant of a breakpoint exit, the contents of all
CPU registers are saved in a designated area of MDXDEBUG RAM called the Register Map. In the Register
Map, the register contents may be examined or modified
using the M command and a predefined mnemonic (or
absolute address) of the storage location for that
register (Example: PC, :A. ... ,:SP). The Register Map is
also used to initialized the CPU registers whenever
execution is initiated or resumed. Thus the E and B
commands can be used together to initialize, execute,
and examine the results of individual program
segments.
The B command gives the user the option of having all
CPU registers displayed when the breakpoint is
encountered. This is done by entering a second operand
to the B command. Otherwise DDT-80 defaults to
displaying the PC and AF registers. When all CPU
1. A serial input driver (usually a keyboard).
2. A serial output driver (usually a CRT or teletype
typehead).
3. A serial input driver which sends out a reader step
signal (usually a teletype reader).
4. A serial output driver which forces a delay after a
carriage return (usually a Silent 700 typehead).
5. A parallel input driver (usually for high-speed paper
tape input).
6. A parallel output driver (usually for high-speed paper
tape output).
7. A parallel output driver (usually for a line printer).
TEXT EDITOR DESCRIPTION
The Text Editor permits random access editing of ASCII
character strings. It can be used as a line or characteroriented editor. Individual characters may be located by
position or context. The Editor works on blocks of
characters which are typically read into memory from
magnetic tape or paper tape. Each edited block can be
output to magnetic tape or paper tape after editing is
completed. While the primary application for the Text
39
Editor is in editing assembly language source
statements, it may be applied to any ASCII text delimited
by "carriage returns".
The Editor has a macro command processing option. Up
to two sets of commands may be stored and processed
at any time during the editing process. All I/O is done
via the DDT-80 channels. The Editor can be used with
the MOSTEK ASMB-80 Assembler and Loader to edit,
assemble, and load programs in memory without the
need for external media for intermediate storage.
The following
Editor:
An
Bn
Cn dS1dS2D
On
E
Ln
Mn
N
Pn
R
5n dS1d
commands are recognized by the Text
- Advance record pointer n seconds
- Backup record pointer n seconds
- Change string S1 to string 52 for n
occurences
- Delete n records
- Exchange current record with records
to be inserted
- Insert records
- Go to line number n
- Enter command buffers (pseudomacro)
- Print top, bottom and current line
number
- Punch n records from buffer
- Read source records into buffer
- Search for nth occurrence of signal S1
ASSEMBLER DESCRIPTION
The Assembler reads Z80 source mnemonics and
pseudo-ops and outputs an assembly listing and object
code. The assembly listing shows address, machine code,
statement number, and source statement. The object
code is in industry-standard hexadecimal format modified for relocatable, linkable assemblies.
The Assembler supports conditional assemblies, global
symbols, relocatable programs and a printed symbol
table. It can assemble any length program, limited only
by a symbol table size which is user selectable.
Expressions involving addition and subtraction are
allowed. A global symbol is catagorized as "internal" if it
appears as a label in the program; otherwise it is an
"external" symbol. The printed symbol table shows
which symbols are internal and which are external. The
assembler allows the user to select relocatable or nonrelocatable assembly via the "PSECT" pseudo-op.
Relocation records are placed in the object ciutput for
relocatable assemblies. (The MOSTEK object format is
defined below.) The Assembler can be run as a singlepass assembler or as a learning tool. (In this mode,
global symbols and forward references are not allowed.)
The following pseudo-ops are recognized by the
Assembler:
EQU
- equate label
DEFL
- define label
DEFM
- define message
DEFB
- define byte
DEFW
- define word
DEFS
- define storage
END
- end statement
40
NAME
PSECT
EJECT
TITLE
LIST
NLiST
- program name definition
- global symbol definition Supports the
following assembler psuedo-ops
- eject a page of listing
- place heading at top of each page
- turn listing on
- turn listing off
RELOCATING LINKING LOADER DESCRIPTION
The MOSTEK Relocating Linking Loader provides stateof-the-art capability for loading programs into memory
by allowing loading and linking of any number of
relocatable and non-relocatable object modules. Nonrelocatable modules are always loaded at their starting
address as defined by the ORG pseudo-op during
assembly. Relocatable object modules can be
positioned anywhere in memory at an offset address.
The Loader automatically links and relocates global
symbols which are used to provide communication or
linkage betweeen program modules. As object
programs are loaded a table containir,tg global symbol
references and definitions is built up. At the end of each
module, the loader resolves all references to global
symbols which are defined by the current or a previously
loaded module. It also prints on the console device the
number of defined global symbols that have been
referenced. The symbol table can be printed in order to
list all global symbols and their load address. The
number of object modules which can be loaded by the
Loader is limited only by the amount of MDX-RAM
available for the modules and the symbol table. Space
for the symbol table is allocated dynamically downward
in memory from either the top of memory or from a
specified address entered as an operand of the load
command.
All I/O is done via the DDT -80 chanhels. Assemblies
can be done from source statements stored in memory
(by the Editor). The object output can be directed to a
memory buffer rather than to an external device. Thus,
assembly and loading can be done without external
storage media.
The Loader prints the beginning and ending address of
each module as it is loaded. The transfer address as
defined by the END pseudo-op is printed for the first
module loaded. The Loader execute command (E) can be
used to automatically start execution at the transfer
address.
The spader Commands are the following:
L offset - load object module at address "offset" plus
program origin address
E
- execute loaded program at transfer address
of first module
T
- print global symbol table
MOSTEK OBJECT OUTPUT DEFINITION
Each record of an object module begins with a delimiter
(colon or dollar sign) and ends with carriage return and
line feed. A colon (:) is used for data records and end-offile record. A dollar sign ($) is used for records
containing relocation information and linking
information. All information is in ASCII. Each record is
identified by "type". The type is determined by the 8th
and 9th bytes of the record which can take the following
values:
00 - data
01 - end-of-file
02 - internal symbol
03 - external symbol
04 - relocation information
05 - module definition
rOW"""
1
··
2
#
of
BINARY
3
5
4
0
6
7
~
8
START ADDRESS
OF DATA
DATA BYTES
9
0
•.• DATA••.
0
1
0
2
CHECK
SUMG)
•
$
INTERNAL
SYMBOL NAME
$
EXTERNAL
SYMBOL NAME
.
·•
·
--'0
3
#
of
BINARY
BYTES
G)
0
$
0
0
0
4
MODULE NAME
I
I
0
0
5
CHECK
SUMG)
ADDRESS
.
--'-
CHECK
SUMG)
LINK
AD~RESS0
I
$
CHECK
SUMG)
I
TRANSFER ADDRESS
OF MODULE
0
,
0
0
I
··
10
•
ADDRESSES WHICH
... REOUIRE RELOCATION .
FLAGS
0
..
.
CHECK
SUMG)
CHECK
SUMG)
I
NOTES:
1. Check Sum is negative of the binary sum of all bytes except delimiter and carriage return/line feed.
2. Link Address points to last address in the data which uses the external symbol. This starts a backward link list through the data records for the external symbol. The list terminates at OFFFFH.
3. The flags are one binary byte. Bit 0 is defined as:
0- absolute module
1 - relocatable module
4. Maximum of 64 ASCII bytes.
ELECTRICAL SPECIFICATIONS
MEMORY CAPACITY
MDX-CPU1
Instruction: 8, 16, 24, or 32 bits
Data: 8 bits
On-Board EPROM - 4K bytes (sockets only)
On-Board RAM-256 bytes
Off-board Expansion - Up to 65,536 bytes with userspecified combinations of RAM,
ROM, PROM.
CYCLE TIME
MEMORY SPEED REQUIRED
WORD SIZE
Clock period or T state = 0.4 microsecond @ 2.5MHz
0.25 microsecond @ 4.00 MHz
Instructions require from 4 to 23 T states
MEMORY ADDRESSING
jumper selectable for any 2K
boundary within a 16K block of
Z80 memory map.
On-Board RAM: FFOO-FFFF
MEMORY
ACCESS TIME
2716*
450ns
CYCLE TIME
450ns
*Single 5 volt type required
On-Board EPROM:
I/O ADDRESSING
On-Board Programmable Timer
41
PORT
ADDRESS (HEX)
7C
7D
7E
7F
MK3882
CHANNEL
PARALLEL BUS INTERFACE-STD BUS
COMPATIBLE
1
Inputs
One 74LS load max
2
3
Bus Outputs
10H =-15mA min. at 2.4 volts
10L = 24mA min at 0.5 volts
o
1/0 CAPACITY
Up to 252 port address can be decoded off board. Four
port addresses are on board. 252 + 4V = 256 total I/O
ports.
INTERRUPTS
POWER SUPPLY REQUIREMENTS
+5V ± 5% at 0.6A max.
+ 12V ± 5% at 0.25A max.
-12V ± 5% at 0.03A max.
OPERATING TEMPERATURE
Multi-level with three vectoring modes (Mode 0,1,2).
Interrupt requests may originate from user-specified
I/O or from the on-board MK3882 CTC.
MDX-DEBUG
PARALLEL BUS INTERFACE STD BUS COMPATIBLE
1/0 TRANSFER RATE
Inputs
Bus Outputs
One 74LS load max
10H = -3mA min at 2.4 volts
10L = 24mA min at 0.5 volts
SYSTEM CLOCK
MDX-CPUl
MDX-CPU-4
MIN
MAX
500 KHz
500 KHz
2.500MHz
4.000MHz
POWER SUPPLY REQUIREMENTS
5V :!: 5% at 1.lA maximum
O°C to 50°C
X 16 Baud Rate Clock
1,760
4,800
9,600
19,200
38.400
76,800
153,600
307,200
Baud Rate (Hz)
110
300
600
1,200
2.400
4,800
9,600
19,200
SERIAL COMMUNICATIONS CHARACTERISTICS
Asynchronous
Full duplex operation
Start bit verification
Data word size variable from 5 to 8 bits
One or two stops bits
Odd, even, or no parity
One word buffering on both transmit
and on receive.
OPERATING TEMPERATURE
ODC to 50 C
G
MDX-DRAM
WORD SIZE
SERIAL COMMUNICATIONS INTERFACE
8 bits
SIGNAL
MEMORY SIZE
MDX-DRAM8
MDX-DRAM16
MDX-DRAM32
- 8,192 bytes
- 16,384 bytes
- 32,768 bytes
ACCESS TIME
SYSTEM
CLOCK
MDX-DRAM
MDX-DRAM-4
2.5MHz
40MHz
MEMORY
ACCESS
TIMES
MEMORY
CYCLE
TIMES
350ns max. 465ns min.
200ns max. 325ns mih.
ADDRESS SELECTION
Selection of 8K, 16K, or 32K contiguous memory blocks
to reside at any 4K boundary.
SYSTEM CLOCK
MDX-DRAM
MDX-DRAM-4
42
MIN
1.25MHz
1.25MHz
MAX
2.5MHz
4.0MHz
BUFFERED FOR:
20mA Current Loop
RS-232
Transmitted data
Output
Received data
Input
Data Terminal
Ready (DTR)
Request to Send (RTS)
Carrier Detect
(COET)
Clear to Send (CTS)
Data Set Ready (DSR)
Reader Step relay (RS) Output
(20mA)
Output
Input
Input
Input
Output
Output
Output
PARALLEL BUS INTERFACE-STD BUS
COMPATIBLE
Inputs
One 74LS load max
Bus Outputs
10H = -3mA min. at 2.4 volts
10L = 24mAmin. at 0.5 volts
I/O ADDRESSING
CONNECTORS
On-Board Serial 1/0 Port
Control Port DDH
Data Port DCH
Module and Reader Step Control Port DEH
FUNCTION
Printed Circuit
Viking 3VH281
1CE5
Wire Wrap
0.125 in.
Viking 3VH281
centers
1CND5
Solder Lug
Viking 3VH281
1CN5
MD-CC8 STD BUSSED 1I~ rack (MK77954) bussed
motherboard with eight connectors on 0.5 in. centers.
STD BUS
SYSTEM CLOCK
MDX-DEBUG
MDX-DEBUG-4
1.25MHz
1.25MHz
MATING
CONNECTOR
CONFIGURATION
2.5MHz
4.0MHz
POWER SUPPLY REQUIREMENT
+12 Volts ± 5% at 50 mA max.
-12 Volts ± 5% at 35 mA max.
+5 Volts ± 5% at 1.2 mA max.
56 pin dual
STD BUS Organization
MECHANICAL SPECIFICATIONS
RS232 Cable MD-RS232 26 pin socket connector
ANSLEY #609-2061 M 5
feet of 26 wire flatcable
ANSLEY #171-26
25-pin standard EIA
ANSLEY #609-25S
CARD DIMENSIONS
TTY Cable MD-TTY
OPERATING TEMPERATURE
26 pin socket connector
ANSLEY #609-2061 M
5 feet of 26 wire flatcable
ANSLEY #171-26
TIY connector Molex 15 Pin
Molex #03-09-2151
4.5 in. (11.43cm) high by 6.50 in (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (.016 cm) printed circuit board thickness
STD BUS
COMPONENT SIDE
PIN
LOGIC
P OWE R
BUS
DATA
BUS
1
3
5
7
9
11
13
ADDRESS
BUS
CONTROL
BUS
POWER
BUS
15
17
19
21
23
25
27
29
MNEMONIC SIGNAL
FLOW
+5V
IN
GND
IN
-5V
IN
CIRCUIT SIDE
DESCRI PTION
PIN
+5 Volts DC (Bussed)
Digital Ground (Bussed)
-5 Volts DC
03
02
01
00
In/au t
In/Out
In/Out
In/Out
Low
Low
Low
Low
Order
Order
Order
Order
Data
Data
Data
Data
A7
A6
A5
Out
Out
Out
Out
Out
Out
Out
Out
Low
low
Low
low
Low
low
Low
low
Order
Order
Order
Order
Order
Order
Order
Order
Address
Address
Address
Address
Address
Address
Address
Address
A4
A3
A2
Al
AO
Bu s
Bus
Bus
Bus
Bus
Bu s
Bu s
Bus
Bu s
Bu s
Bu s
Bu s
SIGNAL
FLOW
In
In
In
DESCRIPTION
+5V
GND
- 5V
8
10
12
14
07
06
05
04
In/Out
In/Out
In/au t
In/au t
High
High
High
High
Order
Order
Order
Order
Data
Data
Data
Data
16
18
20
22
24
26
28
30
A15
A14
A13
A12
All
Ala
A9
A8
High
High
High
High
High
High
High
High
Order
a rde r
Order
Order
Order
Order
Order
Order
Address
Addres s
Address
Addres s
Address
Address
Address
Address
2
4
6
MNEMONIC
31
33
35
37
39
41
43
45
47
49
51
WR
IORQ
IOEXP
REFRESH
STATUS 1
BUSAK
INTAK
WAITRQ
SYSRESET
CLOCK
PCO
Out
Out
Out
Out
Out
Out
Out
In
Out
Out
Out
Write to Memory or I/O
I/O Address Select
I/O Expansion
Refresh Timi ng
**
Bus Acknowl edge
Interrupt Acknowledge
Wait Request
System Reset
Clock from Processor
Priority Chain Out
32
34
36
38
40
42
44
46
48
50
52
RD
MEMRQ
MEMEX
MC SY NCU
STATUS a
BUSRQ
INTRQ
NMI RQ
PBRESEl
CNTRL
PCI
53
55
AUXGND
AUX+V
In
In
AUX Ground (Bussed)
+12 Volts DC}
54
56
AUXGND
AUX-V
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In/Out
**
Out
In
In
In
In
In
In
In
In
!
+5VDC
Bussed).
Digital Ground (Bussed)
-5 Volts DC
Bus
Bus
Bus
Bus
Bus
Bu s
Bus
Bus
Bus
Bu s
Bus
Bus
Read to Memory or I/O
Memory Address Sel ect
Memory Expansion
**
CPU Statu s
Bus Request
Interrupt Request
Non-Maskable interrupt
Push Button Reset
AUX Timing
Priority Chain In
AUX Ground (Bussed)
-12 Volts DC
**Refer to a STD-ZaO BUS Description
43
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MDX-PROTO
Prototyping package with Operations
Manuals. 2.5 MHz version.
MK77951
Note: 2.5 MHz version includes SK
dynamic RAM board MDX-DRAMS
only.
MDX-PROTO-4
PrototYPlng package with
Operations Manuals. 4.0 MHz version.
MK77951-4
NOTE: 4.0 MHz version includes 16K
dynamic RAM board MDX-DRAM 16-4.
AID-SOF data sheet
Disk-based development system for
system for MD series.
MK7S56S
AIM-SO data sheet
Z80 In-Circuit Emulation
module (2.5 MHz only),
MK78537
44
MOSTEI(.
MD SERIES MICROCOMPUTER MODULES
Universal Memory Card (MDX-UMC)
FEATURES
MECHANICAL SPECIFICATIONS
o Can be strapped to accept the following industrystandard memory devices:
CARD DIMENSION
STATIC RAM
EPROM
2758 (lK x 8) MK4118 (1 K x 8)
2716 (2K x 8) MK4802 (2K x 8)
2732 (4K x 8)
ROM
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
MK34000 (2K x 8)
CONNECTORS
o Memories can be mixed to form a combination
memory board
FUNCTION
MATING
CONFIGURATION CONNECTOR
o Wait state generator for 4MHz operation
STO-Z80
BUS
56 pin dual read
out
o STO-Z80 BUS compatible
0.125 in. centers
o +5 Volt only
DESCRIPTION
The MO Series and the STO-Z80 BUS were designed to
satisfy the need for low cost OEM microcomputer
modules. The STO-Z80 BUS uses a motherboard
interconnect system concept and is designed to handle
any MO Series card type inanyslot. The modulesforthe
STO-Z80 BUS are a compact 4.5 x 6.5 inches which
provides for system partitioning by function (RAM,
EPROM, 110). This smaller module size makes system
packaging easier while increasing MOS-LSI densities
provide high functionality per module.
The MO Series of OEM microcomputer boards and the
STO-Z80 BUS offer the most cost effective system
configuration available to the OEM system designer.
MDX-UMC DESCRIPTION
The MOX-UMC is one of MOSTEK's complete line of
STO-Z80 BUS compatible microcomputer modules.
Designed as a universal memory card for the STO-Z80
BUS, the MOX-UMC provides the user with the
capability of configuring the board to meet the system
requirement of ROM/EPROM and/or RAM. By the use
of strapping options, the user is able to configure pairs
of sockets for ROM/EPROM/RAM to form a
combination memory board.
Other MOX-UMC features include 4K boundary
addressing and an optional wait-state generator to
accomodate slower memories for 4MHz operations.
Printed Circuit
Viking 3VH28/
lCE5
Wire Wrap
Viking 3VH28/
lCN05
Solder Lug
Viking 3VH28/
1eNS-
ELECTRICAL SPECIFICATIONS
WORD SIZE
8 bits
MEMORY ADDRESSING
4K boundaries
MEMORY CAPACITY
8 sockets
Sockets are strapped in pairs to accomodate the
following memories:
EPROM
2758
2716
2732
STATIC RAM
MK4118
MK4802
ROM
MK34000
PARALLEL BUS INTERFACE - STO-Z80 BUS
COMPATIBLE
One 74LS load max.
Inputs:
BUS Outputs:
10H = -15mA min at 2.4 Volts
10L = 24mA min at 0.5 Volts
POWER SUPPLY REQUIREMENTS*
+5V ± 5% at 0.450 A max
*Ooes not include power for memories
OPERATING TEMPERATURE
O°C to 50°C
45
MDX-UMC BLOCK DIAGRAM
8
MEMORY
DECODE
)
CS
OE
Ii
CONTROL
LOGIC
/\
WRITE
MEMORY ARRAY
DEVICES
*
EPROM
2758
2716
2732
BAM
MK4118
MK4802
ROM
MK34000
<-
*MEMORY DEVICES CAN BE MIXED TO
FORM A COMBINATION MEMORY BOARD
1\
/\
10
4
OE
8
6
V
/\
RQ,RD
,CLOCK
DATA BUS
BUFFER
ADDRESS BUS
BUFFER
CONTROL BUS
BUFFER
/\
/
+5V
4
WAITRQ
?
16
GND
I I
STD-zao BUS
\I
I)
I
1
MDX-UMC BLOCK DIAGRAM
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO_
MDX-UMC
Module with operation manual less mating connectors
MK77759
MDX-PROTO
MD Series prototyping package
MK77951
AID-80F
MD Series development system
MK78125
AIM-80
Z80 In-Circuit Emulation module (2.5MHz only)
MK78132
46
8
MOSTEl(.
MD SERIES MICROCOMPUTER MODULES
EPROM Module (MDX-EPROM)
FEATURES
ELECTRICAL SPECIFICATIONS
o Accepts the following industry standard EPROMS:
2758 (1K x 8)
2716 (2K x 8)
2732 (4K x 8)
WORD SIZE
8 bits
MEMORY CAPACITY
8K x 8 using eight 2758's
16K x 8 using eight 2716's*
32K x 8 using eight 2732's
*EPROMS included
REQUIRED ACCESS TIME
MIN ACCESS
MEMORY
TIME
TIME
o
Eight EPROM sockets for maximum storage of:
8K x 8 using 2758's
16K x 8 using 2716's
32K
x8
using 2732's
.
,.
o
Wait state generator for 4MHz operation
o
STD-Z80 BUS compatible
o
+5 Volt only
CYCLE TIME
2758,2716,
2732
450ns*
450ns
*One walt state must be added for 4MHz operation.
Description
The MD series and the STD-Z80 BUS were designed to
satisfy the need for low cost OEM microcomputer
modules. The STD-Z80 BUS uses a motherboard
interconnect system concept and is designed to handle
any MD Series card type inanyslot. The modulesforthe
STD-Z80 BUS are a compact 4.5 x 6.5 inches which
provides for system partitioning by function (RAM,
EPROM, 1/0). This smaller module size makes system
packaging easier while increasing MOS-LSI densities
provide high functionality per module.
ADDRESS SELECTION
4K boundaries
BUS INTERFACE
STD-Z80 BUS compatible
Inputs:
One 74LS load max.
10H = -15mA min at 2.4 Volts
Bus Outputs:
10H = 24mA min at 0.5 Volts
The MD Series of OEM microcomputer boards and the
STD-Z80 BUS offer t!1e most cost effective system
configuration available to the OEM system designer.
CONNECTORS
MDX-EPROM DESCRIPTION
FUNCTION
MATING
CONFIGURATION CONNECTOR
The MDX-EPROM is designed to be an EPROM memory
expansion board for the MOSTEK MD SERIESTM of Z80based microcomputers. The MDX-EPROM accepts the
following EPROMS; 2758 (1 K x 8), 2716 (2K x 8) and
2732 (4K x 8) which giv~s a maximum storage capacity
of 8K,i 6K, or 32K bytes respectively.
STO-Z80
BUS
56 Pin dual
0.125 in centers
Starting address selection is provided for positioning
the MDX-EPROM on any 4K boundary. A wait-state
generator is also provided for optional4MHz operation.
Printed Circuit
Viking 3VH281
1CE5
Wire Wrap
Viking 3VH281
1CND5
Solder Lug
Viking 3VH281
1CN5
47
MECHANICAL SPECIFICATIONS
CARD DIMENSION
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm)long
0.48 in. (1 .22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
POWER SUPPLY REQUIREMENTS*
+5 Volts ± 5% at 0.45A
*Does not include EPROMs. Add 100 mA for each
EPROM.
OPERATING TEMPERATURE
O°C to 50°C
ORDERING INFORMATION
48
DESIGNATOR
DESCRIPTION
PART NO.
MDX-EPROM
Module with Operation Manual less mating
connectors (does not include EPROMS).
MK77758
MDX-EPROM Operations Manual only
MK796n
MDX-PROTO
MD Series prototyping package
MK77951
AID-80F
Disk-based development system for MD series
MK78125
AIM-80
Z80 In-Circuit-Emulation module (2.5 MHz only)
MK78132
MDX·EPROM BLOCK DIAGRAM
B
MEMORY
DECODE
MEMORY ARRAY
....,
-
OE
a.
CONTROL
LOGIC
8Kx8
16Kx8
32Kx8
8- 2758
8- 2716
8- 2732
'\
I'
/\
10
4
OE
8
6
J
ADDRESS BUS
BUFFER
CONTROL BUS
BUFFER
I'
MRO,RD
,CLOCK
4
~
/\
-WAITRO
+5V
16
I
DATA BUS
BUFFER
GND
f
B
J
STD-80 BUS
49
50
MOSTEI<.
MD SERIES MICROCOMPUTER MODULES
Static RAM Module (MDX-SRAM)
FEATURES
ADDRESS SELECTION
o Three memory sizes
4K x S (MDX-SRAM4)
SK x S (MDX-SRAMS)
16K x S (MDX-SRAM16)
Selection of 4K, SK, or 16K contiguous memory blocks
to begin on any 4K boundary.
o
Selectable starting adddress on 4K boundaries
o
2.5 MHz and 4.0 MHz compatible
o
STD-ZSO BUS compatible
Inputs: One 74LS load max
Bus Outputs: 10H:= -15mA min at 2.4 Volts
10L := 24mA min at 0.5 Volts
STD-ZSO BUS compatible
o
+5 Volt only
DESCRIPTION
The MD Series™ and the STD-ZSO BUS were designed
to satisfy the need for low-cost OEM microcomputer
modules. The STD-ZSO uses a motherboard interconnect system concept and is designed to handle any
MD Series card type in any slot. The modules for the
STD-ZSO BUS are a compact 4.5 x 6.5 inches which
provides for system partitioning by function (RAM,
EPROM, 1/0). This smaller module size makes system
packaging easier while increasing MOS-LSI densities
provide high functionality per module.
The MD Series of OEM microcomputer boards and the
STD-ZSO BUS offer the most cost-effective system
configuration available to the OEM system designer.
MDX-SRAM DESCRIPTION
The MDX-SRAM is designed to be a static RAM Memory
expansion board for the MOSTEK MD SERIES of ZSO
based microcomputers. It is available in three memory
capacities; 4K bytes (MDX-SRAM4), SK bytes (MDXSRAMS), and 16K bytes (MDX-SRAM 16). Additionally,
all MDX-SRAM boards are 2.5MHz and 4.0MHz
compatible. Thus, the designer can choose from three
options available and tailor the add-on static RAM
directly to the system requirements.
The MDX-SRAM is designed using the state of the art
MK411S (1 KxS) static RAM and MK4S02(2KxS) static
BUS INTERFACE
POWER SUPPLY REQUIREMENTS
BOARDS
+5V ± 5%
MDX-SRAM4
MDX-SRAMS
MDX-SRAM16
O.S A max
1.2 A max
1.2 A max
RAM memory devices. Because of the high speed ofthe
MK411S and MK4S02, no wait states are necessary for
operating the MDX-SRAM at 2.5MHz or 4.0MHz.
Address selection is provided on all MDX-SRAM cards
for positioning the 4K, SK, or 16K of memory to start on
any 4K boundary.
ELECTRICAL SPECIFICATIONS
WORD SIZE
S bits
MEMORY SIZE
MDX-SRAM4 - 4,096 bytes
MDX-SRAMS -S,192 bytes
MDX-SRAM16 - 16,3S4 bytes
TIMING
MDX-SRAM
MEMORY
ACCESS
MEMORY
CYCLE
250ns max.
250ns min.
51
MECHANICAL SPECIFICATIONS
OPERATING TEMPERATURE
CARD DIMENSION
4.5 in. (11.43 em) high by 6.50 in. (16.51 em) long
0.48 in. (1.22 em) maximum profile thickness
0.062 in. (0.16 em) printed circuit board thickness
MDX-SRAM BLOCK DIAGRAM
MEMORY ARRAY
8
MEMORY
DECODE
a.
)
....
CS
OE
CONTROL
LOGIC
WRITE
4Kx8
8KX8
16KX8
4-MK4118
8-MK4118
8-MK4802
V"'-
f--
')
/\
4
6
<~
8
I
CONTROL
BUS
BUFFER
ADDRESS
BUS
BUFFER
f\
1\
MEMRQ
RD
;
52
\/
~
4
16
WAITRQ
S:rD-Z80 BUS
OE
DATA
BUS
BUFFER
/\
+5\
*\
8
V
~
CONNECTORS
FUNCTION
CONFIGURATION
MATING
CONNECTOR
Printed Circuit
STD-Z80
BUS
56 pin dual
read out
Viking 3VH281
1CE5
Wire Wrap
0.125 in centers
Viking 3VH281
1CND5
Solder Lug
Viking 3VH281
1CN5
II·:
.
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MDX-SRAM4
4K Bytes (4118's) module
with operation manual
less mating connectors
MK77755
MDX-SRAM8
8K Bytes (4118's) module
with operation manual
less mating connectors
MK77756
MDX-SRAM16
16K Bytes (4802's) module
with operation man!Jal
less mating connectors
MK77757
MDX-PROTO
Data Sheet
MD Series prototyping
package
MK79605
AID-80F
Data Sheet
Disk based development
system for MD Series
MK78568
AIM-80
Data Sheet
Z80 In-circuit emulation
module (2.5 MHz only)
MK78537
53
.
54
MOSTEI(@
MD SERIES ACCESSORIES
MD-ACC
The following items are available as accessories to
support design, development, and production of
products designed around the MOSTEK MD Series Z80
microcomputer modules:
• WW1 wire wrap card with bussed power and ground
• WW2 wire wrap card without bussed power and
ground
• MD-CC8 8-slot card cage
• MD-CC14 14-slot card cage
• MD-CC28 28-slot card cage
• MD-EXT Extender card.
Description
The STD BUS concept is a joint design between Mostek
and Pro-Log to satisfy the need for cost-effective OEM
Microcomputer Systems. The definition of the STD BUS
and the MD Series of OEM microcomputer modules are
a result of years of microcomputer component and
module manufacturing experience. The STD BUS uses a
motherboard interconnect system concept and is
designed to handle any MD Series card in any card slot.
Modules for the STD BUS range from CPU, RAM and
EPROM Modules to Input, Output, AID, and TRIAC
control modules. A ROM-based DEBUG module
provides users of the STD BUS with Edit, Assembly, and
Debug capability using only an ASCII terminal.
Printed circuit modules for the STD BUS are a compact
4.5 x 6.5 inches providing for system partitioning by
function (RAM, PROM, 1/0). This smaller module size
makes system packaging easier while increasing MOSLSI densities provide high functionality per module.
MECHANICAL SPECIFICATIONS
CARD DIMENSIONS
4.5 in (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
CONNECTORS
FUNCTION
CONFIGURATION
MATING
CONNECTOR
STD-Z80 BUS
56 pin dual read out
Printed Circuit
Viking 3VH28/1CE5
0.125 in. centers
Wire Wrap
Viking 3VH28/1 CND5
Solder Lug
Viking 3VH28/1 CN5
ORDER INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MD-WW1
MD Series wire wrap card with
bussed power and ground
MK77959
MD-WW2
MD Series wire wrap card without bussed power and ground
MK77952
MD-EXT
MD Series extender card
MK77953
MD-CC8
MD Series 8-slot card cage
with STD BUS motherboard
MK77954
MD-CC14
MD Series 14-slot card cage
with STD BUS motherboard.
MK77960
MD-CC28
MD Series 28-slot card cage
with STD BUS motherboard
MK77961
55
WW1 PHOTO MK77969
WW2 PHOTO MK77962
MD - EXT PHOTO MK77963
56
MD-CC 8 Drawing with Dimensions
MD-CC 14 Drawing with Dimensions
MD-CC 28 Drawing with Dimensions
57
MD-CC8 8-Slot Card Cage
MD-CC14 14-Slot Card Cage
58
MOSTEI(.
MD SERIES MICROCOMPUTER MODULES
Analog to Digital Conversion Module (MDX-A/D)
FEATURES
o 8-Bit AID converter with 16 single-ended analog
inputs
o 3
•
•
•
full-scale input ranges
0 to +1 Volts
0 to +2 Volts
0 to +5 Volts
o Total unadjusted error
o Linearity error
< ± 112 LSB
< ± 112 LSB
o No missing codes
o Guaranteed monotonicity
for the STD-Z80 BUS. The module is designed around
the MOSTEK MK5160 8-bit AID converter/16 channel
analog multiplexer. Additional provisions have been
included to allow further analog expansion if desired.
Also, an optional Sample and Hold module (AD582) may
be added to increase system performance. Figure 1 is a
block diagram of the MDX-A/D showing the major
elements of the module.
The first element of this board is the multiplexer. This
16-channel mUltiplexer can directly access anyone of
16 single-ended analog channels and provides logic for
additional channel expansion. All analog input lines
contain a diodelresistor protection circuit to reduce
damage potential from overvoltage and transient
inputs.
o No zero adjust required
o No full scale adjust required
o Provisions for additional channel expansion
o Optional sample and hold
o Address programmable
o 4MHz option
o Compatible with STD-Z80 BUS
DESCRIPTION
The MD Series and the STD-Z80 BUS were designed to
satisfy the need for low-cost OEM microcomputer
modules. The STD-Z80 BUS uses a motherboard
interconnect system concept and is designed to handle
any MD Series card type in any slot. The modules for the
STD-Z80 BUS are a compact 4.5 x 6.5 inches which
provides for system partitioning by function (RAM,
EPROM, 1/0). This smaller module size makes system
packaging easier while increasing MOS-LSI densities
providing high functionality per module.
The MD Series of OEM microcomputer boards and the
STD-Z80 BUS offer the most cost effective system
configuration available to the OEM system designer.
MDX-A/D DESCRIPTION
The Analog to Digital Converter Module, MDX-A/D, is
designed to be a 16 channel single-ended AID module
The output of the multiplexer can either drive the AID
converter directly or a Sample and Hold (S/H) module
version is available. The board is shipped normally
without a Sample and Hold.
If an SIH function is required, an Analog Devices
AD582 needs to be inserted and one jumper removed.
This circuitry allow sampling of signals up to 5KHz with
a nominal 150nsec aperture time.
The other half of the MK5160 is the AID converter. The
8-bit AID consists of 256 series resistors with an
analog switch tree, a chopper stabilized comparator and
a sucessive approximation register. The series resistor
approach guarantees monotonicity and no missing
codes. The need for external zero and full-scale
adjustments has been eliminated and an absolute
accuracy of :;;;; 1 LSB including quantizing error is
provided. A start convert signal initiates the conversion
process and can be jumper selected from either an
external source or under program control. Upon
completion, a DONE signal is generated to indicate end
of conversion. This signal is used to flag the program as
well as any external device.
The Data Bus Buffer and Interface Logic allows the
MDX-A/D module to interface with the STD-Z80 BUS. It
provides buffering for all signals as well as address
decoding and AID port control. A total of 4 port address
locations a're required and can start on any four-word
boundary.
59
ELECTRICAL SPECIFICATIONS
SYSTEM CLOCK
WORD SIZE
Data: 8 bits
I/O Addressing: 8 bits
MDX-A/D
MDX-A/D-4
MIN
250 KHz
250 KHz
MAX
2.5 MHz
4.0 MHz
ELECTRICAL SPECIFICATIONS
I/O ADDRESSING
On board programmable on 4-word boundaries
X X X X X X 0 0 A/D Port Configuration Data
X X X X X X 0 1 A/D Port Configuration Control
X X X X X X 1 0 A/D Data Input/Output Port
X X X X X X 1 1 Data Control Port
POWER SUPPLY REQUIREMENTS
+12 Volts ±5% at 30 rnA max
-12 Volts ±5% at 15 rnA max
+5 Volts ± 5% at 0.6 A max
I/O CAPACITY
Eight bit analog to digital converter with up to sixteen
single ended analog input channels. Channel expansion
available. Start conversion and done handshake signals
available at the edge connector.
Three full scale input ranges: 0 to +1 Volt, 0 to +2 Volts
and 0 to +5 Volts.
SAMPLE/HOLD OPTION DATA
DROOP RATE: 100mV at 25°C
APERTURE TIME: 150nsec
MAX INPUT FREQUENCY: 5KHz
APERTURE JITIER: 15 nsec
CONVERSION TIME
138 microseconds max
OPERATING TEMPERATURE RANGE
0° to +50°C
INTERRUPTS
MECHANICAL SPECIFICATIONS
Vectored interrupts generated. Interrupt vector
programmable upon initialization. Daisy-chained
interrupt priority. Interrupts are controlled by a
MOSTEK MK3881 Parallel I/O controller chip.
CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
MDX-A/D BLOCK DIAGRAM
Figure 1
DONE
MK 5160
MUX
DATA BUS
STD
zao
BUS
BUFFER
SAMPLE
AND
HOLD
AND
ADDITIONAL
ANALOG
CHANNEL
EXPANSION
----1
IN
I
I
I
I
I
INTERFACE
LOGIC
CONVERT
CONTROL
1
I
1
AID:
16 ANALOG
S.E. INPUTS
DATA
60
CONNECTORS
MATING
FUNCTIONS CONFIGURATION CONNECTOR
STD-Z80 BUS 56 pin dual
0.125 centers
Printed Circuit
Viking
3VH28/1CE5
Wire Wrap
Viking
3VH28/1CND5
Solder Lug
Viking
3VH28/1CN5
Analog 1/0
40 pin dual
0.100 centers
Ansley 609-4000
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MDX-A/D
Module with Operation Manual less mating connector:
2.5 MHz version
MK77653
MDX-AlD-4
Module with Operation Manual less mating connector:
4.0 MHz version
MK77653-4
MDX-A/D Operations Manual only
MK79632
61
STANDARD LICENSE AGREEMENT AND REGISTRATION FORM
All Mostek Corporation software products are sold
on condition that the Purchaser agreeS to
the following terms:
1.
2.
3.
4.
The Purchaser agrees not to sell, provide, give away, or otherwise make available to any unauthorized persons,
all or any part of, the Mostek software products listed below, including, but not restricted to: object code, source
code and program listings.
The Purchaser may at any time demonstrate the normal operation of the Mostek software product to any person.
All software designed, developed and generated independently of, and not based on, Mostek's software by
purchaser shall become the sole property of purchaser and shall be excluded from the provisions of this
Agreement. Mostek's software which is modified to such an extent that Mostek agrees that it is not recognizable
as Mostek's software shall become the sole property of purchaser.
Mostek's sole obligation shall be to make available all published modifications of updates made by Mostek to
licensed software products which are published within one (1) year from date of purchase, provided Purchaser
has completed and returned the Software License Agreement and Registration Form.
5.
In no event will Mostek be held liable for any loss, expense or damage, of any kind whatsoever, direct or indirect,
regardless of whether such arises out of the law of torts or contracts, or Mostek's negligence including
incidental damages, consequential damages and lost profits, arising out of or connected in any manner with any
of Mostek's software products described below.
6.
MOSTEK MAKES NO WARRANTIES OF ANY KIND, WHETHER STATUTORY, WRITTEN, ORAL, EXPRESSED OR
IMPLIED (INCLUDING WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY
AND WARRANTIES ARISING FROM COURSE OF DEALING OR USAGE OF TRADE) wl'rn RESPECT TO THE
SOFTWARE DESCRIBED BELOW.
To be eligible for software product updates this form must be completed and returned to:
Mostek Corporation
Microcomputer Department
Software Librarian
MS503
P.O. Box 169
1215 W. Crosby Road
Carrollton, TX 75006
The following software products are subject to this agreement:
Part Number
Description
Ship to: _________________________________________________________________________________
Customer
P.O. Number: _____________________________
Purchase Date:
System Serial Number:
PURCHASER
MOSTEK CORPORATION
By: _____________________________________
By: _______________________________________
Title: _____________________________________
Title: _______________________________________
Company: _________________________________
Date: _______________________________________
Date: _____________________________________
62
MOSTEI(®
STD-zao BUS DESCRIPTION AND ELECTRICAL SPECIFICATIONS
Application Note
DESCRIPTION
The purpose of this application note is to provide the
O.E.M. system designer with more information about
the STO-Z80 BUS. The information presented is a
bus description of the STO-Z80 BUS, the pin out,
and the recommended BUS loading specifications.
In April of 1978, several meetings were held between
MOSTEK CORP. and PROLOG CORP. to discuss the
possibility of defining a new O.E.M. microcomputer
board BUS. The goals for the new BUS were that it be
simple to interface to, be well defined, and be able to use
a standard 56 pin edge card connector. The results of
these meetings were successful, and the STD BUS was
defined.
The STD BUS was defined as a general purpose microprocessor bus which is capable of supporting the
following processors: Z80, 8080, 8085, 6800, and
6809. It is possible to design simple function cards
which will work with each of the processors, however it
may be difficult or impossible to design an add on card
which used one of the many peripheral chips and then
have the card work with all of the STD BUS processors.
It was for this reason that MOSTEK defined the
STD-Z80 BUS. The STD-Z80 is a subset of the general
purpose STD BUS and is defined exclusively forthe Z80.
By specifying the STD-Z80 bus, exact functional pin
descriptions and bus timing can be given. Therefore, a
STD-Z80 system will be guaranteed to work with all
STD-Z80 designed boards.
The STD-Z80 backplane pin assignments are listed and
described in Table 1. A table showing the BUS pins
versus BUS signals is shown in Table 2.
7
8
9
10
11
12
13
14
03
07
02
06
01
05
DO
04
Data Bus (Tri -state,
input/output, active high).
DO-D7 constitute an 8-bit
bi-directional data bus. The
data bus is used for data
exchange with memory and
I/O devices.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A7
A15
A6
A14
A5
A13
A4
A12
A3
All
A2
Al0
Al
A9
AD
A8
Address Bus (Tri-state,
output, active high). AO-A 15
make up a 16-bit address
bus. The address bus provides the address for memory
(up to 65K bytes) data exchanges and for I/O device
data exchanges. I/O addressing uses the lower 8
address bits to allow the user
to directly select up to 256
input or 256 output ports. AD
is the least significant address bit. During refresh
time, the lower 7 bits
contain a valid refresh
refresh address for dynamic
memories.
31
/WR
Write (Tri-state,output,
active low) /WR indicates
that the CPU data bus holds
valid data to be stored in the
addressed memory or I/O
device.
32
/RD
Read (Tri-state, output,
active low). RD indicates that
the CPU wants to read data
from memory or an I/O
device. The addressed I/O
device or memory should use
this signal to gate data onto
the CPU data bus.
33
/IORO
Input/Output Request (Tristate, output, active low). The
/IORO signal indicates that
the lower half of the address
bus holds a valid I/O address
for an I/O read or write
operation. An /IORO signal is
also generated with a /M 1
signal when an interrupt is
being acknowledged to
indicate that an interrupt
STD-Z80 BUS DESCRIPTION
Table 1
BUS
PIN
MNEMONIC DESCRIPTION
1
2
+5V
+5V
+5Vdc system power
+5Vdc system power
3
GND
4
GND
Ground-System signal
ground and DC return
Ground-System signal
ground and DC return
5
6
-5V
-5V
-5Vdc system power
-5Vdc system power
63
response vector can be
placed on the data bus.
Interrupt Acknowledge
operations occur during 1M 1
time, while 1/0 operations
never occur during 1M 1
time.
34
IMEMRO
Memory Request (Tri-state,
output, active low). The
IMEMRO signal indicates
that the address bus holds a
valid address for a memory
read or memory write
operation.
35
IIOEXP
1/0 Expansion, not used on
MDX cards. (Normally strapped to ground on the
MOSTEK motherboard)
36
IMEMEX
Memory Expansion, not used
on Mostek MDX cards.(Normally strapped to ground on
the MOSTEK motherboard)
37
IREFRESH
REFRESH (Tri-state, output,
active low). IREFRESH indicates that the lower 7 bits
of the address bus contain a
refresh address for dynamic
memories and the IMEMRO
signal should be used to
perform a refresh cycle for all
dynamic RAMs in the
system. During the refresh
cycle A7 is a logic 0 and the
upper 8 bits of the address
bus contains the I register.
38
64
IMCSYNC
Not generated on the
MOSTEK MDX-CPU1. Can
be generated by gating the
following signals:/RD+ IWR
+ IINTAK. By connecting a
jumper on the MDX-CPU1,
this line becomes IDEBUG
(Input). IDEBUG is used in
conjunction with the DDT -80
operating system on the
MDX-DEBUG card, and the
MDX-SST card for implementing a hardware single
step function. When pulled
low, the IDEBUG line will set
an address modification
latch which will force the
upper three address lines
A15, A14, and A13 to a logic
1. These address lines will
remain at a logic 1 until reset
by performing any 1/0 operation.
39
ISTATUS 1
Machine Cycle One (Tristate, output, active low).
IM1 indicates that the
current machine cycle is in
the op code fetch cycle of an
instruction. Note that during
the execution of two-byte opcodes IM1 will be generated
as each op-code is fetched.
These two-byte op-codes
always begin with a CBh,
DDh, EDh, or FDh. IM1 also
occurs with 10RO to indicate
an interrupt acknowledge
cycle.
40
ISTATUS 0
Not used on Mostek MDX
cards.
41
IBUSAK
Bus Acknowledge (Output,
active low). Bus acknowledge
is used to indicate to the
requesting device that the
CPU address bus, data bus,
and control bus signals have
been set to their high impedance state and the external device can now
control the bus.
42
IBUSRO
Bus Request (Input. active
low). The IBUSRO signal is
used to request the CPU
address bus, data bus, and
control signal bus to go to a
high impedance state so that
other devices ca n control
those buses. When IBUSRO
is activated, the CPU will
set these buses to a high
impedance state as soon as
the current CPU machine
cycle is terminated and the
IBUSAK signal is activated.
43
IINTAK
Interrupt Acknowledge (Tristate, output, active low). The
IINTAK signal indicates that
an interrupt acknowledge
cycle is in progress, and the
interrupting device should
place its response vector on
the data bus. The liNT AK
signal is equivalent to an
10RO during an IM1.
44
IINTRO
Interrupt Request (Input,
active low). The Interrupt
Request signal is generated
by 1/0 devices. A request will
be honored at the end of the
current instruction if the
internal software controlled
interrupt enable flip flop (IFF)
is enabled and if the BUSRQ
signal is not active. When the
CPU accepts the interrupt.
an interrupt acknowledge
signal IINTAK (IORQ during
an M 1) is sent out at the
beginning of the next
instruction.
45
46
47
IWAITRQ
INMIRQ
ISYSRESET
Wait Request (Input, active
low). Wait Request indicates
to the CPU that the
addressed memory or 1/0
device is not ready for a data
transfer. The CPU continues
to enter wait states for as
long as this signal is active.
This signal allows memory or
1/0 devices of any speed to
be synchronized to the CPU.
Use of this signal postpones
refresh as long as it
held active.
Non-Maskable Interrupt
Request (Input, negative
edge triggered). The NonMaskable Interrupt Request
line has a higher priority than
the IINTRQ line and is always
recognized at the end of the
current instruction, independent of the status
of the interrupt enable
flip-flop. INMIRQ automatically forces the CPU to
restart to location 0066h.
The program counter is automatically saved in the
external stack so that the
user can return to the program that was interrupted.
Note that continuous WAIT
cycles can prevent the current instruction from ending
and that a IBUSRQ will override a INMIRQ.
System Reset (Output,
active low). The System
Reset line indicates that
a reset has been generated
either from an external reset
or the power on reset
circuit. The system reset will
occur only once per reset and
will be approximately 2
microseconds in duration.
A system reset will also force
the CPU program counter to
zero, disable interrupts, set
the I register to OOh, set the
R register to OOh, and set
Interrupt Mode O.
48
IPBRESET
Push Button Reset (Input.
active low). The Push Button
Reset will generate a debounced system reset.
49
ICLOCK
Processor Clock (Output,
active low).
Single phase system clock.
50
ICNTRL
Not used on MOSTEK MDX
cards.
* 51
PCO
Priority Chain Output (Output, active high). The signal is
used to form a priorityinterrupt daisy chain when
more than one interruptdriven device is being used.
A high level on this pin indicates that no other devices
of higher priority are being
serviced by a CPU interrupt
service routine.
* 52
PCI
Priority Chain In (Input.
active high). This signal is
used to form a priorityinterrupt daisy chain when
more than one interruptdriven device is being used. A
high level on this pin indicates that no other devices
of higher priority are being
serviced by a CPU interrupt
service routine.
53
54
AUX GND
AUX GND
Auxiliary Ground (Bussed)
Auxiliary Ground (Bussed)
55
+12V
+12Vdc system power
56
-12V
-12Vdc system power
NOTES:
1.
Input/Output
2
The following signals have pull-up resistors; /WR, IRO, fIORQ, IMEMRQ,
references
of each signal
are made with
respect to
MDX-CPU 1 module.
IREFRESH, IOEBUG, IMl, IBUSRQ, IINTAK, IINTRQ, IWAITRQ,
INMIRQ, ISYSRESET, IPBRESET, and ICLOCK. The value of the pull-up
resistors are 1K except for /WAITRQ which IS 500 ohms and /PBRESET
which is 10K ohms. These resistors are located on the MDX-CPUl module.
*The Mostek card cage is prioritized from left to right as viewed from
the top with component side of boards to the left.
STD-Z80
ELECTRICAL BUS SPECIFICATIONS
BUS RECEIVERS
Logical Low: 0.8V maximum at -0.36mA
Logical High: 2.0V minimum at 20j.1A
BUS DRIVERS
Logical Low: 0.5V maximum at 24mA
Logical High: 2.4V minimum at -15mA
Off State Output Current (tri-state): ±100(.1A
65
RECOMMENDED BUS DRIVERS
AND RECEIVERS
Bus Drivers: 74LS240, 74LS241, 74LS373,
74LS374, and 74LS244.
Bus Receivers: 74LS240, 74LS241, and
74LS244.
Bus Transceivers: 74LS245, 74LS242,
and 74LS243.
66.
STD-Z80 BUS PIN-OUT
Table 2
Component
Side
Mnemonic Pin
Circuit
Side
Mnemonic
+5V
2
+5V
3
GND
4
GND
5
-5V
6
-5V
7
9
11
13
03
D2
D1
DO
8
10
12
14
D7
D6
D5
D4
15
17
19
21
23
25
27
29
A7
A6
A5
A4
A3
A2
A1
AO
16
18
20
22
24
26
28
30
A15
A14
A13
A12
A11
A10
A9
A8
31
IWR
32
IRD
33
IIORQ
34
IMEMRQ
35
IIOEXP
36
IMEMEX
37
IREFRESH
38
IMCSYNC
39
ISTATUS 1
40
ISTATUS 0
41
IBUSAK
42
IBUSRQ
43
IINTAK
44
IINTRQ
45
IWAITRQ
46
INMIRQ
47
ISYSRESET
48
IPBRESET
49
ICLOCK
50
ICNTRL
51
PCO
52
PCI
53
AUX GND
54
AUX GND
55
+12V
56
-12V
Pin
1979 MICROCOMPUTER DATA BOOK
67
68
MOSTEI{.
MD SERIES MICROCOMPUTER MODULES
zao Single Board Computer (MD-SBC1)
FEATURES
o
o
o
o
o
Sockets for 8K bytes 2716 EPROM
o
Two TTL buffered 8-bit INPUT ports
o
o
Two Interrupt Inputs
Z80 Microprocessor
2K byte RAM capacity with 1 K included
the board. Power on reset circuitry is included on the
CPU's RESET input. Provision is made to expand the
I/O capability through the use of on-board connectors.
MD-SBC1 BLOCK DIAGRAM
Figure 1
Crystal Clock - 2.5 MHz
Three TTL buffered 8-bit OUTPUT ports
Single +5 volt power supply
DESCRIPTION
The MD-SBC1 is a complete Z80 based microcomputer on 4 % in. by 6 % in. circuit module. All I/O is
fully TTL buffered and is brought to a 56 pin edge
connector.
The smaller card size and the single power supply
makes the MD-SBC1 easier to package and easier to
use than most other modules. While the module size
is small no compromises have been made in computing power due to increasing MOS- LSI densities and
the use of the Z80 microcomputer. The 40 buffered
TTL I/O lines and the 8K bytes of EPROM provide
the capability to solve many control problems encountered by the OEM microcomputer user. The expandable MD Series (MDX) has the same form factor
allowing easy expansion to a multi-board system with
increased capability.
Figure 1 is a block diagram of the MD-SBC1. The
basic module comes with 1 K bytes of RAM expandable to 2K bytes by the addition of two 2114 type
RAMs. Four 2716 sockets are provided for up to 8K
bytes of EPROM, and are decoded in 2K blocks starting at address zero. The output ports are 74LS244
latches which are brought to the card cage connector.
The input ports are 74LS240 Octal Buffers with 4.7K
OHM pull-up resistors on the inputs. These input lines
are also brought to the edge connector. The Z80-CPU
is driven by a crystal clock at 2.5MHz (400nsec
T-State) .
Both the NMI and INT interrupt inputs to the Z80CPU are terminated with 4.7K Ohm pull ups and
brought to the card edge connector. An external
clock can be used by changing strapping options on
ELECTRICAL SPECIFICATIONS
WORD SIZE
INSTRUCTION 8,16, 24 or 32 bits
DATA 8 bits
CYCLE TIME
T-STATE = 400nSec, fastest instruction is 1.6 microsecond.
MEMORY ADDRESSING
EPROM
NUMBER
2
3
HEX
ADDRESS
0000-07FF
0800-0FFF
1000-17FF
1800-1 FFF
RAM
NUMBER
STANDARD
OPTIONAL
2400-27FF
o
69
MD-SBC 1 BOARD PHOTO
70
MEMORY CAPACITY
SYSTEM CLOCK
8 K bytes of 2716 memory (none included)
2 K bytes of 2114 memory (1 K bytes included)
flilD-SBC1
MEMORY SPEED REQUIRED
POWER SUPPLY REQUIREMENTS
Memory
2716*
2114
Access Time
Re uired
450nSec
450nSec
Cycle Time
Re uired
450nSec
450nSec
MIN
250KHz
MAX
2.5MHz
+5 volts ± 5% at 1.2A max (fully loaded)
(100mA per RAM, 100mA per EPROM)
OPERATING TEMPERATURE RANGE
* Single 5 volt type required
MECHANICAL SPECIFICATIONS
I/O ADDRESSING AND CAPACITY
PORT TYPE
Input
Output
HEX
ADDRESS
00 and 01
00,01,02
DATA
CAPACITY
16 lines
24 lines
CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51cm) long
048 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed circuit board thickness
INTERRUPTS
CONNECTORS
Two active low; NMI and INT. See Z80-CPU
(MK3880) Technical Manual for a full description of
Z80 interrupts.
FUNCTION
I/O INTERFACES
Paralled I/O
Inputs - One 74LS load plus a 4.7K Ohm pull up resistor
Outputs - 10H = -15mA at VOH = 2.4 volts
10L = 24mA at VOL = 0.5 volts
CONFIGURATION MATING
CONNECTOR
Printed Circuit
56 pin (28 position) VIKING 3VH28/1CE5
0.125 in centers
Wire Wrap
VIKING 3VH28/1CND5
Solder Lug
VIKING 3VH28/1CN5
I
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MD-SBC1
Complete Z80 Single Board
Computer with Operations
Manual less EPROMs and mating
connector.
MK77851
MD-SBC1 Operations
Manual only.
MK79609
MDX-PROTO
Data Sheet
MD Series prototyping
package
MK78605
AID-80F
Data Sheet
Disk based development
system for MD Series
MK78568
AIM-80
Data Sheet
Z80 In-Circuit Emulation
Module for AID-80F
MK78537
71
72
1979 MICROCOMPUTER DATA BOOK
73
74
MOSTEI(.
Z80 MICROCOMPUTER DEVICES
Technical Manual
MI(3880
CENTRAL
PROCESSING
UNIT
75
76
TABLE OF CONTENTS
Chapter
Page
1.0
Introduction .......................................................5
2.0
Z80-CPU Architecture ................................................7
3.0
Z80-CPU Pin Description ............................................ 11
4.0
CPU Timing ....... _.............. _................................ 15
5.0
Z8D-CPU Instruction Set ............ _............................... 23
6.0
Flags ........................................................... 43
7.0
Summary of OP Codes and Execution Times ............................ 47
8.0
Interrupt Response ................................................ 59
9.0
Hardware Implementation Examples ................................... 65
10.0
Software Implementation Examples ................................... 71
11.0
Electrical Specifications ............................................ 77
12.0
Z80 Instruction Breakdown by Machine Cycle ........................... 83
13.0
Package Description and Ordering Information ........................... 90
77
78
1.0 INTRODUCTION
The term "microcomputer" has been used to describe virtually every type of small
computing device designed within the last few years. This term has been applied to
everything from simple "microprogrammed" controllers constructed out of TTL MSI up
to low end minicomputers with a portion of the CPU constructed out of TTL LSI "bit
slices." However, the major impact of the LSI technology within the last few years has been
with MOS LSI. With this technology, it is possible to fabricate complete and very powerful
computer systems with only a few MOS LSI components.
The Mostek Z80 family of components is a significant advancement in the state-of-art of
microcomputers. These components can be configured with any type of standard semiconductor memory to generate computer systems with an extremely wide range of
capabilities. For example, as few as two LSI circuits and three standard TTL M$I packages
can be combined to form a simple controller. With additional memory and I/O devices a
computer can be constructed with capabilities that only a minicomputer could previously
deliver. This wide range of computational power allows standard modules to be constructed
by a user that can satisfy the requirements of an extremely wide range of applications.
The major reason for MOS LSI domination of the microcomputer market is the low cost of
these few LSI components. For example, MOS LSI microcomputers have already replaced
TTL logic in such applications as terminal controllers, peripheral device controllers, traffic
signal controllers, point of sale terminals, intelligent terminals and test systems. In fact the
MOS LSI microcomputer is finding its way into almost every product that now uses
electronics and it is even replacing many mechanical systems such as weight scales and
automobile controls.
The MOS LSI microcomputer market is already well established and new products using
them are being developed at an extraordinary rate. The Mostek Z80 component set has been
designed to fit into this market through the following factors:
1. The Z80 is fully software compatible with the popular 8080A CPU offered from
several sources. Existing designs can be easily converted to include the Z80 as a
superior alternative.
2. The Z80 component set is superior in both software and hardware capabilities to
any other 8-bit microcomputer system on the market. These capabilities provide the
user with significantly lower hardware and software development costs while also
allowing him to offer additional features in his system.
3. A complete development and OEM system product line including full software
support is available to enable the user to easily develop new products.
Microcomputer systems are extremely simple to construct using Z80 components. Any such
system consists of three parts:
1. CPU (Central Processing Unit)
2.
Memory
3.
Interface circuits to peripheral devices
79
The CPU is the heart of the system. Its function is to obtain instructions from the memory
and perform the desired operations. The memory is used to contain instructions and in most
cases data that is to be processed. For example, a typical instruction sequence may be to
read data from a specific peripheral device, store it in a location in memory, check the
parity and write it out to another peripheral device. Note that the Mostek component set
includes the CPU and various general purpose I/O device controllers, as well as a wide range
of memory devices. Thus, all required components can be connected together in a very
simple manner with virtually no other external logic. The user's effort then becomes
primarily one of software development. That is, the user can concentrate on describing his
problem and translating it into a series of instructions that can be loaded into the microcomputer memory. Mostek is dedicated to making this step of software generation as simple
as possible. A good example of this is our assembly language in which a simple mnemonic
is used to represent every instruction that the CPU can perform. This language is self documenting in such a way that from the mnemonic the user can understand exactly what the
instruction is doing without constantly checking back to a complex cross listing.
80
2.0 Z80·CPU ARCHITECHURE
A block diagram of the internal architecture of the Z80-CPU is shown in Figure 2.0-1
The diagram shows all of the major elements in the CPU and it should be referred to
throughout the following description.
ZSO'CPU BLOCK DIAGRAM
ALU
13
CPU AND
SYSTEM
CONTROL
SIGNALS
INSTRUCTION
DECODE
&
CPU
CONTROL
CPU
CONTROL
iii
+5V GND
(I)
FIGURE 2.0-1
2.1 CPU REGISTERS
The Z80-CPU contains 208 bits of R/W memory that are accessible to the programmer.
Figure 2.0-2 illustrates how this memory is configured into eighteen 8-bit registers and
four 16-bit registers. All Z80 registers are implemented using static RAM. The registers
include two sets of six general purpose registers that may be used individually as 8-bit
registers or in pairs as 16-bit registers. There are also two sets of accumulator and flag
registers.
Special Purpose Registers
1. Program Counter (PC). The program counter holds the 16-bit address of the current
instruction being fetched from memory. The PC is automatically incremented after
its contents have been transferred to the address lines. When a program jump occurs
the new value is automatically placed in the PC, overriding the incrementer.
2. Stack Pointer (SP). The stack pointer holds the 16-bit address of the current top of
a stack located anywhere in external system RAM memory. The external stack
memory is organized as a last-in first-out (LI Fa) file. Data can be pushed onto the
stack from specific CPU registers or popped off of the stack into specific CPU registers through the execution of PUSH and POP instructions. The data popped from the
stack is always the last data pushed onto it. The stack allows simple implementation
of multiple level interrupts, unlimited subroutine nesting and simplification of many
types of data manipulation.
81
ZSO-CPU REGISTER CONFIGURATION
MAIN REG SET
AL TERNATE REG SET
A
'v'
ACCUMULATOR
FLAGS
A
F
ACCUMULATOR
A'
FLAGS
F'
C
B'
C'
D
D'
E'
H
H'
L'
INTERRUPT
VECTOR
I
I
}
""""
PURPOSE
REGISTERS
MEMORY
REFRESH
R
INDEX REGISTER IX
INDEX REGISTER IY
SPECIAL
PURPOSE
REGISTERS
>
STACK POINTER SP
PROGRAM COUNTER PC
FIGURE 2,0-2
3. Two Index Registers (IX & IV). The two independent index registers hold a 16-bit
base address that is used in indexed addressing modes, In this mode, an index register
is used as a base to point to a region in memory from which data is to be stored or
retrieved. An additional byte is included in indexed instructions to specify a displacement from this base. This displacement is specified as a two's complement
signed integer, This mode of addressing greatly simplifies many types of programs,
especially where tables of data are used.
4. Interrupt Page Address Register (I). The Z80-CPU can be operated in a mode where
an indirect call to any memory location can be achieved in response to an interrupt.
The I Register is used for this purpose to store the high order 8-bits of the indirect
address while the interrupting device provides the lower 8-bits of the address, This
feature allows interrupt routines to be dynamically located anywhere in memory with
absolute minimal access time to the routine,
5. Memory Refresh Register (R). The Z80-CPU contains a memory refresh counter to
enable dynamic memories to be used with the same ease as static memories. This 7-bit
register is automatically incremented after each instruction fetch. The data in the
refresh counter is sent out on the lower portion of the address bus along with a
refresh control signal while the CPU is decoding and executing the fetched instruction, This mode of refresh is totally transparent to the programmer and does not
slow down the CPU operation. The programmer can load the R register for testing
purposes, but this register is normally not used by the programmer.
Accumulator and Flag Registers
The CPU includes two independent 8-bit accumulators and associated 8-bit flag registers.
The accumulator holds the results of 8-bit arithmetic or logical operations while the flag
register indicates specific conditions for 8 or 16-bit operations, such as indicating whether
or not the result of an operation is equal to zero. The programmer selects the accumulator
and flag pair that he wishes to work with with a single exchange instruction so that he may
easily work with either pair.
82
General Purpose Registers
There are two matched sets of general purpose registers, each set containing six 8-bit registers that may be used individually as 8-bit registers or as 16-bit register pairs by the programmer. One set is called BC, DE, and HL while the complementary set is called BD', DE'
and HL'. At ar1Y one time the programmer can select either set of registers to work with
through a single exchange command for the entire set. In systems where fast interrupt
response is required, one set of general purpose registers and an accumulator/flag register
may be reserved for handl ing this very fast routine. Only a simple exchange command need
be executed to go between the routines. This greatly reduces interrupt service time by
eliminating the requirement for saving and retrieving register contents in the external
stack during interrupt or subroutine processing. These general purpose registers are used for
a wide range of applications by the programmer. They also simplify programming, especially
in ROM based systems where little external read/write memory is available.
2.2 ARITHMETIC & LOGIC UNIT (ALU)
The 8-bit arithmetic and logical instructions of the CPU are executed in the ALU. Internally
the ALU communicates with the registers and the external data bus on the internal data bus.
The type of functions performed by the ALU include:
Add
Left or right shifts or rotates (arithmetic and logical)
Subtract
Increment
Logical AND
Decrement
Logical OR
Set bit
Logical Exclusive OR
Reset bit
Compare
Test bit
2.3 INSTRUCTION REGISTER AND CPU CONTROL
As each instruction is fetched from memory, it is placed in the instruction register and
decoded. The control section performs this function and then generates and supplies all of
the control signals necessary to read or write data from or to the registers, controls the
ALU and provides all required external control signals.
83
84
3.0 Z80-CPU PIN DESCRIPTION
The Z80-CPU is packaged in an industry standard 40 pin Dual In-Line Package. The I/O
pins are shown in Figure 3.0-1 and the function of each is described below.
Z80 PIN CONFIGURATION
30
AO
A,
A2
A3
A4
A5
A6
A7
AS
ADDRESS
BU5
Ag
AlO
A"
Z80 CPU
MK 3880
MK 38804
A'2
A13
A'4
A'5
14
DO
0,
O2
03
D4
DATA
BUS
D5
06
07
FIGURE 3.0-1
AO-A15
(Address Bus)
Tri-state output, active high. AO-A15 constitute a 16-bit address
bus. The address bus provides the address for memory (up to 64K
bytes) data exchanges and for I/O device data exchanges. I/O
addressing uses the 8 lower address bits to allow the user to
directly select up to 256 input or 256 output ports. AO is the
least significant address bit. During refresh time, the lower 7 bits
contain a valid refresh address.
00- 0 7
(Data Bus)
Tri-state input/output, active high. 00-07 constitute an 8-bit
bidirectional data bus. The data bus is used for data exchanges
with memory and I/O devices.
M1
(Machine Cycle one)
Output, active low. M 1 indicates that the current machine cycle
is the OP code fetch cycle of an instruction execution. Note that
during execution of 2-byte op-codes, M 1 is generated as each op
code byte is fetched. These two byte op-codes always begin with
CBH, DOH, EDH, or FDH. M 1 also occurs with IORO to indicate
an interrupt acknowledge cycle.
MREO
(Memory Request)
Tri-state output, active low. The memory request signal indicates
that the address bus holds a valid address for a memory read or
memory write operation.
85
10RO
Tri-state output, active low. The 10RO signal indicates that the
(I nput/Output Request) lower half of the address bus holds a valid I/O address for a I/O
read or write operation. An 10RO signal is also generated with
an M 1 signal when an interrupt is being acknowledged to indicate
that an interrupt response vector can be placed on the data bus.
Interrupt Acknowledge operations occur during M 1 time while
I/O operations never occur during M 1 time.
RD
(Memory Read)
Tri-state output, active low. RD indicates that the CPU wants to
read data from memory or an I/O device. The addressed I/O device
or memory should use this signal to gate data onto the CPU data
bus.
WR
(Memory Write)
Tri-state output, active low. WR indicates that the CPU data bus
holds valid data to be stored in the addressed memory or I/O
device.
RFSH
(Refresh)
Output, active low. RFSH indicates that the lower 7 bits of the
address bus contain a refresh address for dynamic memories and
current MREO signal should be used to do a refresh read to all
dynamic memories. A7 is a logic zero and the upper 8 bits of the
Address Bus contains the I Register.
HALT
(Halt state)
Output, active low. HALT indicates that the CPU has executed a
HALT software instruction and is awaiting either a non maskable
or a maskable interrupt (with the mask enabled) before operation
can resume. While halted, the CPU executes NOP's to maintain
memory refresh activity.
WAIT*
(Wait)
Input, active low. WAIT indicates to the Z80-CPU that the addressed memory or I/O devices are not ready for a data transfer.
The CPU continues to enter wait states for as long as this signal is
active. This signal allows memory or I/O devices of any speed to
be synchronized to the CPU.
INT
(I nterrupt Request)
Input, active low. The Interrupt Request signal is generated by
I/O devices. A request will be honored at the end of the current
instruction if the internal software controlled interrupt enable
flip-flop (IFF) is enabled and if the BUSRO signal is not active.
When the CPU accepts the interrupt, an acknowledge signal
(lORd during M1 time) is sent out at the beginning of the next
instruction cycle. The CPU can respond to an interrupt in three
different modes that are described in detail in section 8.
Input, negative edge triggered. The non maskable interrupt request
line has a higher priority than INT and is always recognized at the
end of the current instruction, independent of the status of the
interrupt enable flip-flop. NM I automatically forces the Z80-CPU
to restart to location 0066H. The program counter is automatically saved in the external stack so that the user can return to the
program that was interrupted. Note that continuous WAIT cycles
can prevent the current instruction from ending, and that a
BUSRQ will override a NMI.
86
Input, active low. RESET forces the program counter to zero and
initializes the CPU. The CPU initialization includes:
1)
2)
3)
4)
Disable the interrupt enable flip-flop
Set Register I = DOH
Set Register R = DOH
Set Interrupt Mode 0
During reset time, the address bus and data bus go to a high
impedance state and all control output signals go to the inactive
state. No refresh occurs.
BUSRQ
(Bus Request)
Input, active low. The bus request signal is used to request the
CPU address bus, data bus and tri-state output control signals to
go to a high impedance state so that other devices can control
these buses. When BUSRQ is activated, the CPU will set these
buses to a high impedance state as soon as the current CPU
machine cycle is terminated.
BUSAK*
(Bus Acknowledge)
Output, active low. Bus acknowledge is used to indicate to the
requesting device that the CPU address bus, data bus and tristate control bus signals have been set to their high impedance
state and the external device can now control these signals.
Single phase system clock.
*While the Z80-CPU is in either a WAIT state or a Bus Acknowledge condition, Dynamic Memory Refresh
will not occur.
87
88
4.0 CPU TIMING
The Z80-CPU executes instructions by stepping through a very precise set of a few basic
operations. These include:
Memory read or write
I/O device read or write
I nterrupt acknowledge
All instructions are merely a series of these basic operations. Each of these basic operations
can take from three to six clock periods to complete or they can be lengthened to synchronize the CPU to the speed of external devices. The basic clock periods are referred to as
T states and the basic operations are referred to as M (for machine) cycles. Figure 4.0-0
illustrates how a typical instruction will be merely a series of specific M and T cycles. Notice
that this instruction consists of three machine cycles (M1, M2 and M3). The first machine
cycle of any instruction is a fetch cycle which is four, five or six T states long (unless
lengthened by the wait signal which will be fully described in the next section). The fetch
cycle (M 1) is used to fetch the OP code of the next instruction to be executed. Subsequent
machine cycles move data between the CPU and memory or I/O devices and they may have
anywhere from three to five T cycles (again they may be lengthened by wait states to
synchronize the external devices to the CPU). The following paragraphs describe the timing
which occurs within any of the basic machine cycles. In section 7, the exact timing for
each instruction is specified.
BASIC CPU TIMING EXAMPLE
T State
Machine Cycle
M1
(OP Code Fetch)
M2
M3
(Memory Read}
(Memory Write)
Instruction Cycle
FIGURE 4.0-0
All CPU timing can be broken down into a few very simple timing diagrams as shown in
Figure 4.0-1 through 4.0-7. These diagrams show the following basic operations with and
without wait states (wait states are added to synchronize the CPU to slow memory or
I/O devices).
4.0-1.
Instruction OP code fetch (M 1 cycle)
4.0-2.
Memory data read or write cycles
4.0-3.
I/O read or write cycles
4.0-4.
Bus Request/Acknowledge Cycle
4.0-5.
I nterrupt Request/Acknowledge Cycle
4.0-6.
Non maskable Interrupt Request/Acknowledge Cycle
4.0-7.
Exit from a HALT instruction
89
INSTRUCTION FETCH
Figure 4.0·1 shows the timing during an M1 cycle (OP code fetch). Notice that the PC is
placed on the address bus at the beginning of the M 1 cycle. One half clock time later the
MREO signal goes active. At this time the address to the memory has had time to stabilize
so that the falli~ edge of MR EO can be used directly as a chip enable clock to dynamic
memories. The RD line also goes active to indicate that the memory read data should be
enabled onto the CPU data bus. The CPU samples the data from the memory on the data
bus with the rising edge of the clock of state T3 and this same edge is used by the CPU
to turn off the RD and MREQ signals. Thus the data has already been sampled by the CPU
before the RD signal becomes inactive. Clock state T3 and T4 of a fetch cycle are used to
refresh dynamic memories. (The CPU uses this time to decode and execute the fetched
instruction so that no other operation could be performed at this time). Durin~nd T4
the lower 7 bits of the address bus contain a memory refresh address and the R FSH signal
becomes active to indicate that a refresh read of all dynamic memories should be accomplished. Notice that a RD signal is not generated during refresh time to prevent data from
different memory segments from being gated onto the data bus. The MREO signal during
refresh time should be used to perform a refresh read of all memory elements. The refresh
signal can not be used by itself since the refresh address is only guaranteed to be stable
during MREO time.
INSTRUCTION OP CODE FETCH
Ml Cycle
T1
T3
T2
T4
T,
I
--'~ ~ ~ ~ ~fAO
~
A15
,
,
MREO
RD
I
r
'-- f-
I
I
-
r
-i
MI
AFSH
REFRESH ADDR
- ----- ---.r-L"_ ----- ------t------ --------- ------ - - - - - --
WAIT
DO -
I
PC
D7
\._-----
-
'""j'N'
L::.::.
,
Ir
FIGURE 4.0-1
Figure 4.0-1A illustrates how the fetch cycle is delayed if the memory activates the WAIT
line. During T2 and every subsequent Tw, the CPU samples the WAIT line with the falling
edge of <1>. If the WAIT line is active at this time, another wait state will be entered during
the following cycle. Using this technique the read cycle can be lengthened to match the
access time of any type of memory device.
90
INSTRUCTION OP CODE FETCH WITH WAIT STATES
MI Cycle
T1
I
T2
Tw
Tw
T4
T3
-'~ ~ ~I l -~
AD - A15
J
J
PC
~f-
,.- t--
MAEQ
00 -
MI
I
\
AD
07
I
REFRESH AD DR
f'"'iN
-,
L..:.:.:
I
J
- ----- -l.J_~
- -----
=lJ_-_
_____
~JL--+~_-_-
L
----- ----- -
I\
I
FIGURE 4.0-1A
MEMORY READ OR WRITE
Figure 4.0-2 illustrates the timing of memory read or write cycles other than an OP code
fetch (M 1 cycle). These cycles are generally three clock periods long unless wait states are
requested by the memory via the WAIT signal. The MREQ signal and the RD signal are used
the same as in the fetch cycle. In the case of a memory write cycle, the MREQ also becomes
active when the address bus is stable so that it can be used directly as a chip enable for
dynamic memories. The WR line is active when data on the data bus is stable so that it can
be used directly as a R/W pulse to virtually any type of semiconductor memory. Furthermore the WR signal goes inactive one half T state before the address and data bus contents
are changed so that the overlap requirements for virtually any type of semiconductor
memory type will be met.
MEMORY READ OR WRITE CYCLES
MI~nlOry
I
T1
~I·
Read Cycle
T2
~.--,-.-
Memory Write Cycle - -_ _ _
T1
T3
T2
I
T3
- ~ ~ ~I l -~ ~
AO - A15
I
.I
MEMORY)"DDR
\
I
l
I
(00·-07)
I
\
J
DATA OUT
IN
- ---- ----
I
MEMORY AOOR
\
DATA BUS
r--
r--l-_-= r---f-----r-L-~------t---- -f----
- - - - f-.
FIGURE 4.0-2
91
Figure 4.0-2A illustrates how a WAIT request signal will lengthen any memory read or
write operation. This operation is identical to that previously described for a fetch cycle.
Notice in this figure that a separate read and a separate write cycle are shown in the same
figure although read and write cycles can never occur simultaneously.
MEMORY READ OR WRITE CYCLES WITH WAIT STATES
I
T,
T2
Tw
T
I
w
T,
T3
- h -h - h -h - h -h I
AO -.. A15
II
MEMOR Y ADDA.
1
MREQ
I--
(
\
}
DATA BUS
(00-07)
READ
CYCLE
IN
I
I
WR
}
DATA BUS
(00-07)
WAIT
WRITE
CYCLE
DATA OUT
-
-------- t-lJ_-_- lI~ ~.JL=_ -----
f----
---- --
---1--
FIGURE 4.0-2A
INPUT OR OUTPUT CYCLES
Figure 4.0-3 illustrates an I/O read or I/O write operation. Notice that during I/O operations
a single wait state is automatically inserted. The reason for this is that during I/O operations,
the time from when the 10RQ signal goes active until the CPU must sample the WAIT line
is very short and without this extra state sufficient time does not exist for an I/O port to
decode its address and activate the WAIT line if a wait is required. Also, without this wait
state it is difficult to design MOS I/O devices that can operate at full CPU speed. During
this wait state time the WAIT request signal is sampled. During a read I/O operation, the
RD line is used to enable the addressed port onto the data bus just as in the case of a
memory read. For I/O write operations, the WR line is used as a clock to the I/O port, again
with sufficient overlap timing automatically provided so that the rising edge may be used as
a data clock.
Figure 4.0-3A illustrates how additional wait states may be added with the WAIT line.
The operation is identical to that previously described.
BUS REQUEST/ACKNOWLEDGE CYCLE
Figure 4.0-4 illustrates the timing for a Bus Request/Acknowledge cycle. The BUSRQ
signal is sampled by the CPU with the rising edge of the last clock period of any machine
cycle. If the BUSRQ signal is active, the CPU will set its address, data and tri-state control
signals to the high impedance state with the rising edge of the next clock pulse. At that
time any exterhal device can control the buses to transfer data between memory and I/O
devices. (This is generally known as Direct Memory Access [DMA] Llsing cycle stealing).
The maximum time for the CPU to respond to a bus request is the length of a machine
cycle and the external controller can maintain control of the bus for as many clock cycles
as is desired. Note, however, that if very long DMA cycles are used, and dynamic memories
are being used, the external controller must also perform the refresh function. This situation
only occurs if very large blocks of data are transferred under DMA control. Also note that
during a bus request cycle, the CPU cannot be interrupted by either a NMI or an INT signal.
92
INPUT OR OUTPUT CYCLES
T,
T2
Tw'
T,
T3
ne or 2 bytes
Ollerand
d7
dO
Examples of this type of instruction would be to load the accumulator with a constant,
where the constant is the byte immediately following the OP code.
Immediate Extended. This mode is merely an extension of immediate addressing in that the
two bytes following the op codes are the operand.
OP Code
one or 2 bytes
Operand
low order
Operand
high order
Examples of this type of instruction would be to load the HL register pair (16-bit register)
with 16 bits (2 bytes) of data.
98
Modified Page Zero Addressing. The Z80 has a special single byte call instruction to any of
8 locations in page zero of memory. This instruction (which is referred to as a restart) sets
the PC to an effective address in page zero. The value of this instruction is that it allQws a
single byte to specify a complete 16-bit address where commonly called subroutines are
located, thus saving memory space.
lop Code I
bO
one byte
Effective address is (00b5b4b3000)
Relative Addressing. Relative addressing uses one byte of data following the OP code to
specify a displacement from the existing program to which a program jump can occur.
This displacement is a signed two's complement number that is added to the address of the
OP code of the following instruction.
OP Code }
Jump relative (one byte OP code)
Operand
8-bit two's complement
Address (A+2)
displacement added
to
The value of relative addressing is that it allows jumps to nearby locations while only
requiring two bytes of memory space. For most programs, relative jumps are by far the
most prevalent type of jump due to the proximity of related program segments. Thus,
these instructions can significantly reduce memory space requirements. The signed displacement can range between +127 and -128 from A + 2. This allows for a total displacement of +129 to -126 from the jump relative OP code address. Another major advantage
is that it allows for relocatable code.
Extended Addressing. Extended Addressing provides for two bytes (16 bits) of address to
be included in the instruction. This data can be an address to which a program can jump or
it can be an address where an operand is located.
}
OP Code
one or two bytes
~---------------------------------~
Low Order Address or Low order operand
High Order Address or High order operand
Extended addressing is required for a program to jump from any location in memory to any
other location, or load and store data in any memory location.
When extended addressing is used to specify the source or destination address of an operand,
the notation (nn) will be used to indicate the content of memory at nn, where nn is the
16-bit address specified in the instruction. This means that the two bytes of address nn are
used as a pointer to a memory location. The use of the parentheses always means that the
value enclosed within them is used as a pointer to a memory location. For example, (1200)
refers to the contents of memory at location 1200.
Indexed Addressing. In this type of addressing, the byte of data following the OP code
contains a displacement which is added to one of the two index registers (the OP code
specifies which index register is used) to form a pointer to memory. The contents of the
index register are not altered by this operation.
OP Code
f-------!
}
two byte OP code
OP Code
Displacement Operand added to index register to form a pointer
to memory.
99
An example of an indexed instruction would be to load the contents of the memory location (Index Register + Displacement) into the accumulator. The displacement is a signed
two's complement number. Indexed addressing greatly simplifies programs using tables of
data since the index register can point to the start of any table. Two index registers are
provided since very often operations require two or more tables. Indexed addressing also
allows for relocatable code.
The two index registers in the Z80 are referred to as IX and IY. To indicate indexed addressing the notation:
(IX+d) or (lY+d)
is used. here d is the displacement specified after the OP code. The parentheses indicate that
this value is used as a pointer to external memory.
Register Addressing. Many of the Z80 OP codes contain bits of information that specify
which CPU register is to be used for an operation. An example of register addressing would
be to load the data in register B into register C.
Implied Addressing. Implied addressing refers to operations where the OP code automatically implies one or more CPU registers as containing the operands. An example is the set of
arithmetic operations where the accumulator is always implied to be the destination of the
results.
Register Indirect Addressing. This type of addressing specifies a 16-bit CPU register pair
(such as H L) to be used as a pointer to any location in memory. This type of instruction is
very powerful and it is used in a wide range of applications.
I
OP Code
I}
one or two bytes
An example of this type of instruction would be to load the accumulator with the data in
the memory location pointed to by the H L register contents. Indexed addressing is actually
a form of register indirect addressing except that a displacement is added with indexed
addressing. Register indirect addressing allows for very powerful but simple to implement
memory accesses. The block move and search commands in the Z80 are extensions of this
type of addressing where automatic register incrementing, decrementing and comparing
has been added. The notation for indicating register indirect addressing is to put parentheses around the name of the register that is to be used as the pointer. For example, the
symbol
(HL)
specifies that the contents of the H L register are to be used as a pointer to a memory
location. Often register indirect addressing is used to specify 16-bit operands. In this case,
the register contents point to the lower order portion of the operand while the register
contents are automatically incremented to obtain the upper portion of the operand.
Bit Addressing. The Z80 contains a large number of bit set, reset and test instructions.
These instructions allow any memory location or CPU register to be specified for a bit
operation through one of three previous addressing modes (register, register indirect and
indexed) while three bits in the OP code specify which of the eight bits is to be manipulated.
ADDRESSING MODE COMBINATIONS
Many instructions include more than one operand (such as arithmetic instructions or loads).
In these cases, two types of addressing may be employed. For example, load can use immediate addressing to specify the source and register indirect or indexed addressing to
specify the source and register indirect or indexed addressing to specify the destination.
100
5.3 INSTRUCTION OP CODES
This section describes each of the l80 instructions and provides tables listing the OP codes
for every instruction. In each of these tables the shaded OP codes are identical to those
offered in the 8080A CPU. Also shown is the assembly language mnemonic that is used for
each instruction. All instruction OP codes are listed in hexadecimal notation. Single byte
OP codes require two hex characters while double byte OP codes require four hex characters.
The conversion from hex to binary is repeated here for convenience.
Hex
Binary
Decimal
Hex
Binary
Decimal
0
0000
0
8
1000
1
0001
1
9
1001
8
9
2
0010
2
A
1010
10
3
0011
3
B
1011
11
4
0100
4
C
1100
12
5
0101
5
D
1101
13
6
0110
6
E
1110
14
7
0111
7
F
1111
15
l80 instruction mnemonics consist of an OP code and
zero, one or two operands.
Instructions in which the operand is implied have no operand. Instructions which have
only one logical operand or those in which one operand is invariant (such as the Logical OR
instruction) are represented by a one operand mnemonic. Instructions which may have
two varying operands are represented by two operand mnemonics.
LOAD AND EXCHANGE
Table 5.3-1 defines the OP code for all of the 8-bit load instructions implemented in the
l80-CPU. Also shown in this table is the type of addressing used for each instruction. The
source of the data is found on the top horizontal row while the destination is specified by
the left hand column. For example, load register C from register B uses the OP code 48H.
In all of the tables the OP code is specified in hexadecimal notation and the 48H (=0100
1000 binary) code is fetched by the CPU from the external memory during Ml time,
decoded and then the register transfer is automatically performed by the CPU.
The assembly language mnemonic for this entire group is LD, followed by the destination
followed by the source (LD DEST., SOURCE). Note that several combinations of addressing
modes are possible. For example, the source may use register addressing and the destination
may be register indirect; such as load the memory location pointed to by register H L with
the contents of register D. The OP code for this operation would be 72. The mnemonic for
this load instruction would be as follows: LD (HL), D
The parentheses around the H L means that the contents of H L are used as a pointer to a
memory location. In all l80 load instruction mnemonics the destination is always listed
first, with the source following. The l80 assembly language has been defined for ease of
programming. Every instruction is self documenting and programs written in l80 language
are easy to maintain.
Note in Table 5.3-1 that some load OP codes that are available in the l80 use two bytes.
This is an efficient method of memory utilization since 8, 16, 24 or 32 bit instructions
are implemented in the l80. Thus often utilized instructions such as arithmetic or logical
operations are only 8-bits which results in better memory utilization than is achieved with
fixed instruction sizes such as 16-bits.
All load
actually
example
written:
instructions using indexed addressing for either the source or destination location
use three bytes of memory with the third byte being the displacement d. For
a load register E with the operand pointed to by IX with an offset of +8 would be
LD E, (IX + 8)
101
The instruction sequence for this in memory would be:
Address A
~D1
OP Code
A+1
5F
A+2
08
Displacement operand
The two extended addressing instructions are also three byte instructions. For example
the instruction to load the accumulator with the operand in memory location 6F32H would
be written:
LD A, (6F 32H)
and its instruction sequence would be:
Address A
A+1
A+2
A
~
OPCode
32
low order address
6F
high order address
Notice that the low order portion of the address is always the first operand.
The load immediate instructions for the general purpose 8-bit registers are two-byte instructions. The instruction load register H with the value 36H would be written:
LD H, 36H
and its sequence would be:
Address A
A+1
~
OPCode
~
Operand
Loading a memory location using indexed addressing for the destination and immediate
addressing for the source requires four bytes. For example:
LD{IX-151.21H
would appear as:
Address A
DD
OP Code
A+1
36
A+2
F1
A+3
21
displacement (-15 in
signed two's complement)
operand to load
Notice that with any indexed addressing the displacement always follows directly after the
OP code.
Table 5.3-2 specifies the 16-bit load operations. This table is very similar to the previous one.
Notice that the extended addressing capability covers all register pairs. Also notice that
register indirect operations specifying the stack pointer are the PUSH and POP instructions.
The mnemonic for these instructions is "PUSH" and "POP". These differ from other 16-bit
loads in that the stack pointer is automatically decremented and incremented as each byte
is pushed onto or popped from the stack respectively. For example the instruction:
102
PUSH AF
is a single byte instruction with the OP code of F5H. When this instruction is executed the
following sequence is generated:
Decrement SP
LD (SP), A
Decrement SP
LD (SP), F
Thus the external stack now appears as follows:
(SP)
F
(SP+1)
A
Top of stack
II
8 BIT LOAD GROUP
SOURCE
EXT.
IMPLIED
A
B
c
REGISTER
R
ED
57
ED
SF
B
A
I}~' ;;'1~
.: .•.
~:4r t 4ci [41
[4F 1:'4~: 4~
·5~
f:.~~·
~t
17
FD
(lY+d)
17
d
(nn)
(BC)
(DE)
INDEXED
UX+d)OV+dl
Fa
AODA. IMME.
(nn)
li~.
"
!?E
DO
46
d
46
d
··4A: I~B I·.··.·. ..•.~.~ .. [4:
DO
4E
d
FO
4E
d
Isa '~i V~~ l!l~
DO
56
d
FD
56
d
)6
DO
5E
d
FD
5E
d
bE
DO
66
d
FD
66
d
'26
DO
6E
d
FD
6E
d
~~i
L~:!
14~. I;~t~: 1 46: t~.6
["c.
[
16·bit value in range <0, 65535>
TABLE 6.0-1
119
120
7.0 SUMMARY OF OP CODES AND EXECUTION TIMES
The following section gives a summary of the zao instruction set. The instructions are
logically arranged into groups as shown on Tables 7.0-1 through 7.0-11. Each table shows
the assembly language mnemonic OP code, the actual OP code, the symbolic operation,
the content of the flag register following the execution of each instruction, the number
of bytes required for each instruction as well as the number of memory cycles and the
total number of T states (external clock periods) required for the fetching and execution
of each instruction. Care has been taken to make each table self-explanatory without
requiring any cross reference with the text or other tables.
121
a-BIT LOAD GROUP
Mnemonic
~
LD r, n
Symbolic
Operation
r- s
r-n
LDr,IHLI
LD r, IIX+d)
r -IHLI
r -IIX+d)
LD r, IIY+d)
r -IIY+d)
LDIHLI,r
LD IIX+d), r
IHLI-r
IIX+d)-r
LD IIY+d), r
IiY+d)-r
LDIHLI,n
IHLI-n
LD IiX+d), n
IiX+d)-n
LD IiY+d), n
IiY+d)-n
Flags
S
P!V
H
N
Op·Code
C 76 543 210
Hex
s
01 r
00 r 110
n
01 r 110
11 011 101
DO
01 r 110
d
FD
11 111 101
01 r 110
- d
01 110 r
11 011 101
DO
01 110 r
_ d
·• •• •• ·•
- •
•
•
·• ·• ·• · · •
·· • ··•• •
•
• · ·
• •
· •••
• •
· •••
·• · · • • · · · • ··
• ·
•
·•• • •
• •
• •
•
•
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
•
•
•
X
X
X
X
X
X
•
•
•
X
X
X
I
X
0
I
I
X
·
•
• •
LD A, IBC)
LD A, IDE)
LD A, Innl
A-IBC)
A-IDE)
A -Inn)
LD IBC), A
LD IDE), A
LD Inn), A
IBC)-A
IDE)-A
Inn)-A
LD A, I
A-I
I
LD A, R
A-R
LD I, A
I-A
LD R, A
R-A
Notes:
Z
··
·• ·••
·
• • •
•
• •
···
• • ·
• • •
•
0
0
X IFF
0
0
0
X IFF
0
0
X
0
X
• • •
X
0
X
• • •
11 111 101
01 110 r
- d
00 110110
- n
11 011 101
00 110110
- d
- n
11 111 101
00 110110
- d
- n
00 001010
00 011 010
00 111 010
- n
- n
00 000010
00 010010
00110010
n
n
11 101101
01 010111
11 101101
01 011111
11 101101
01 000111
11 101 101
01 001111
-
-
-- --
0=
flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
Table 7.0-1
122
No. of M
Cycles
1
2
No. of T
States
Comments
r, s
Reg.
4
7
000
B
001
C
010
0
7
E
19
011
H
100
101
L
19
111
A
1
3
2
5
3
5
1
3
2
5
7
19
FD
3
5
19
36
2
3
10
DO
36
4
5
19
FD
36
4
5
19
OA
lA
3A
1
1
3
2
2
4
7
7
13
02
12
32
1
1
3
2
2
4
7
7
13
ED
57
ED
5F
ED
47
ED
4F
2
2
9
2
2
9
2
2
9
2
2
9
r, s means any of the registers A, B, C, 0, E, H, L
IFF the cOAtent of the interrupt enable flip·flop (IFF) is copied into the PIV flag
Flag Notation:
No. of
Bytes
1
2
16-BIT LOAD GROUP
Mnemonic
LD dd, nn
Symbolic
Operation
dd ~ nn
S
•
X
•
LD IX, nn
IX
• •
X
·
LD IV, nn
IV - nn
LD HL, (nn)
H ~ (nn+1)
L - (nn)
LD dd, (nn)
ddH ~(nn+1)
dd L ~(nn)
LD IX, (nn)
IXH- (nn+l)
IXL ~(nn)
LD IV, (nn)
IVH~(nn+1)
~
nn
IVL -(nn)
LD (nn), HL
(nn+1) - H
(nn)-L
LD (nn), dd
(nn+1) - ddH
(nn)-ddL
LD (nn), IX
(nn+l) - IXH
(nn)-IXL
LD (nn), IV
(nn+l) ~ IVH
(nn)-IVL
LD SP, HL
LD SP, IX
SP - HL
SP - IX
LD SP, IV
SP - IV
PUSH qq
(Sp·2) - qqL
(Sp·l) - qqH
(SP·2) - IXL
(SP-1) -IXH
(SP·2) - IVL
(SP·1) -IVH
qqH- (SP+1)
qqL -(SP)
IXH-(SP+l)
IXL -(SP)
IVH-(SP+l)
IVL -(SP)
PUSH IX
PUSH IV
PDP qq
POP IX
POP IV
Notes:
·
Z
FI ns
H
PIV
X
N
• •
X
•
..
·· · ··
• •
•
··
·• · • •
• •
•
··
• •
•
• ·
• ·
•
• •
• •
· ••
• •
•
··
• •
· ••
• ·
•
• •
• •
• •
·
• •
•
•
·
• ·
•
• •
• •
·• •• ••
·• ·• • •
·
• ·
•
·• ·•
• •
·
C
•
Op·Cilde
76 543 210
00 ddO 001
n
n
11 011 101
00 100 001
n
n
11 111 101
00 100 001
n
n
00 101 010
n
n
11 101 101
01 ddl 011
n
n
11 011 101
00 101 010
n
n
11111 101
00 101 010
n
n
00 100 010
n
n
11 101 101
01 ddO 011
n
n
11 011 101
00 100 010
n
n
11 111 101
00 100 010
n
n
11 111 001
11 011 101
11 111 001
11 111 101
11 111 001
11 qqO 101
- -- --
•
X
X
X
X
X
·· ---
X
X
•
X
X
•
X
X
•
X
X
•
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No. of
Bytes
3
No. of M No. ofT
Cycles States
10
3
~
X
X
Hex
•
-
4
4
14
FD
21
4
4
14
2A
3
5
16
ED
4
6
20
DO
2A
4
6
20
FD
2A
4
6
20
22
3
5
16
ED
4
6
20
DO
22
4
6
20
FD
22
4
6
20
F9
DO
F9
FD
F9
1
2
1
2
6
10
2
2
10
1
3
11
2
4
15
2
4
15
1
3
10
2
4
14
2
4
14
~
--
--
---
---
-~
-
--
-
·
· -~
--
~
•
•
•
•
•
•
•
•
•
DO
21
Comments
dd
Pair
00
BC
DE
01
HL
10
11
SP
--
-
11
11
11
11
11
011
100
111
100
qqO
101
101
101
101
001
DO
E5
FD
E5
11
11
11
11
011 101
100 001
111 101
100001
DO
El
FD
El
qq
00
01
10
11
Pair
BC
DE
HL
AF
dd is any of the register pairs BC, DE, HL, SP
qq is any of the register pairs AF, BC, DE, HL
(PAIR)H, (PAl R) L refer to high order and low order eight bits of the register pair respectively.
e.g. BCL = C, AFH =A
Flag Notation:
=flag not affected, 0 =flag reset, 1 =flag set, X =flag is unknown,
I flag is affected according to the result of the operation.
•
Table 7.0-2
123
EXCHANGE GROUP AND BLOCK TRANSFER AND SEARCH GROUP
Mnemonic
EXDE,HL
EX AF, AF'
EXX
Symbolic
Operation
DE-HL
AF-AF'
S
Z
• •
•
•
X
X
X
FI s
H
P/V
• X
N
• •
Hex
EB
08
D9
No. 01
Bytes
1
1
1
No.oIM
Cycles
1
1
1
11 100 011
E3
1
5
No.ol T
States Comments
4
4
4
Register bank and
auxiliary register
bank exchange
19
11
11
11
11
101
011
101
011
DD
E3
FD
E3
2
6
23
2
6
23
C 76
• 11
00
• 11
Op·Code
543 210
101 011
001 000
011 001
(BC --BC')
DE-DE'
HL-HL'
EX (SP), HL H -(SP+1)
L -(SP)
EX (SP), IX IXH--(SP+l)
IXL --(SP)
EX (SP), IY IYH -(SP+1)
IYL -(SP)
· · ·•
• ·
·
• •
·•
• ·
X
X
X
X
X
X
• • •
• • •
• •
LDI
(DEHHU
DE - DE+l
HL - HL+l
BC - BC·l
• •
X
0
X
CD
I
0
•
11 101 101
10 100 000
ED
AO
2
4
16
LDI R
(DEHHU
DE - DE+l
HL - HL+l
BC -BC·l
Repeat until
BC = 0
• •
X
0
X
0
0
•
11 101 101
10110000
ED
BO
2
2
5
4
21
16
11 101 101
10 101 000
ED
A8
2
4
16
ED
2
2
5
4
21
16
LDD
(DEHHU
DE - DE·l
HL - HL·l
BC - BC·l
LDDR
(DEHHU
DE - DE·l
HL - HL·l
BC -BC·l
Repeat until
BC = 0
X
X
X
0
X
CD
\
0
·
• •
X
0
X
0
0
•
11 101 101
10 111 000
B8
1
•
11 101 101
10 100 001
ED
Al
2
4
16
1
•
11 101 101
10 110 001
ED
Bl
2
2
5
4
21
16
1
•
11 101 101
10 101 001
ED
A9
2
4
16
1
•
11 101 101
10 111 001
ED
B9
2
2
5
4
21
16
·
CIl
A- (HL!
HL-HL+l
BC - BC·l
I
CPIR
A- (HU
HL-HL+l
BC - Be·l
Repeat until
A=(HLlor
BC= 0
\
CPD
A - (H Ll
HL - HL·l
BC - BC·l
I
CIl
I
X
\
X
CPDR
A - (H Ll
HL - HL·l
BC - BC·l
Repeat until
A= (HLl or
BC = 0
I
CIl
I
X
I
X
CD
CIl
·
011
100
111
100
•
CPI
Notes:
··
•
• •
I
X
I
X
X
\
X
CIl
\
CD
\
CD
\
CD
I
CD
I
P/V Ilag is 0 if the result of BC·l = 0, otherwise PIV = 1
Z flag is 1 if A = (H Ll, otherwise Z = D.
Flag Notation: • = Ilag not affected, 0 = Ilag reset, 1 = flag set, X = flag is unknown,
I =flag is affected according to the result 01 the operation.
Table 7.0·3
124
Load (H Uinta
(DE), increment the
pointers and
decrement the byte
counter (BC)
If BC "I' 0
If BC = 0
If BC "I' 0
If BC = 0
If BC"I' OandA"I'(HU
If BC = 0 or A = (H U
IfBC10andA1(HLl
IIBC=OorA=(HLl
8-BIT ARITHMETIC AND LOGICAL GROUP
Mnemonic
ADD A, r
ADD A, n
Symbo lie
Operati on
S
Z
A - A+ r
A - A+ n
I
I
I
I
Fl. s
H
X
X
I
I
ADD A, (HLi
ADD A, (lX+dl
A - A+ (HLI
A-A+(I X+d.1
I
I
I
I
X
X
I
ADD A, (lY+dl
A-A+(I Y+di
I
I
X
ADC A, s
SUB s
SBC A, s
AND s
ORs
XOR s
CP s
INC r
INC(HLi
INC (lx+dl
A-A+s+ CY
A-A·s
A-A·s ·CY
A-A A
A-A v s
A-A (j) s
A· s
r - r+ 1
(HlHH Li+l
(lx+dl (lX+d 1+1
I
I
I
I
I
I
I
I
I
0
0
I
I
I
X
X
X
X
X
X
X
X
X
X
INC (lY+dl
(lY+dl (lY+d 1+1
I
I
I
I
Notes:
,
I
I
I
I
I
I
I
I
X
X
P/V
N
Op·Code
C 76 543 210 Hex
V
V
0
0
I 10 lQQQ] r
I 11lQQQ]110
-
\
X
X
V
V
0
0
I
I
I
X
V
0
I
V
V
V
P
P
P
V
V
V
V
0
1
1
0
0
0
1
0
0
0
I
I
I
X
X
X
X
X
X
X
X
X
X
•
•
•
X
I
X
V
0
•
X
I
X
V
1
•
.•
t
I
1
I
I
I
I
0
0
0
I
n
No.of No.ofM No.ofT
Bytes Cycles States Comments
1
2
1
2
4
7
DD
1
3
2
5
7
19
FD
3
5
19
-
10 lQQQ]110
11 011 101
10lQQQ]110
d
11 111 101
10 1QQQ]110
d
- -
[QIDJ
lQTI]
Jl][J
[IT[]
TIIDJ
[ill]
- - [j]]-
Reg.
B
C
D
E
H
l
A
s is any of r, n,
(HLi, (lX+dl,
(I Y+dl as shown lor
AD D instruction.
The indicated bits
replace the [llJ!]!] in
the AD D set above.
IIDQJ
00 r [j]QJ
00 11 0 [j]QJ
11 011 101
00 110 [j]QJ
d
11 111 101
00 11 0 [j]QJ
d
r
000
001
010
011
100
101
111
,
DD
1
1
3
1
3
6
4
11
23
FD
3
6
23
sisanyolr,(HLI,
(lX+dl, (lY+dl as
shown lor INC.
DEC same lormat
and states as INC.
Replace IT®] with
[Q] in OP Code.
The V symbol in the P/V flag column indicates that the PIV Ilag contains the overflow 01 the result of the
operation. Similarly the P symbol indicates parity. V = 1 means overflow, V = 0 means not overflow, P = 1
means parity of the result is even, P = 0 means parity of the result is odd.
Flag Notation: • =flag not affected, 0 = Ilag reset, 1 =flag set, X =flag is unknown.
I =flag is affected according to the result of the operation.
Table 7,0-4
125
GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
Svmbolic
Mnemonic Operation
S
DAA
Converts acc, I
content into
packed BCD
following add
or subtract
with packed
BCD operands
CPL
A- A
Z
j
FI gs
H
X
I
X
Op-Code
PIV N C 76 543 210
P
•
j
•
·
X
1
X
·
1
•
I
X
I
X
V
1
I
X
X
X
•
0
0
• •
• •
• •
•
• •
2F
1
1
4
11 101 101
01 000 100
I 00 111 111
ED
44
3F
2
2
8
1
1
4
1 00
00
01
11
11
11
01
11
01
11
01
37
00
76
F3
FB
ED
46
ED
56
ED
5E
1
1
1
1
1
2
1
1
1
1
1
2
4
4
4
4
4
8
2
2
8
2
2
8
I
CCF
CY-CY
•
SCF
NOP
HALT
01"
EI"
1M 0
CY-l
No operation
CPU halted
IFF - 0
IFF - 1
Set interrupt
mode 0
Set interrupt
mode 1
Set interrupt
mode 2
I
•
• •
•
• •
• •
• •
·
X
X
X
X
X
X
•
•
•
•
•
X
X
X
X
X
X
•
•
•
•
•
•
• •
X
•
X
• • •
• •
X
•
X
• • •
Notes:
·•
0
·
110
000
110
110
111
101
000
101
010
101
011
111
000
110
011
011
101
110
101
110
101
110
IFF indicates the interrupt enable flip-flop
CY indicates the carry flip-flop.
Flag Notation: • =flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
"Interrupts are not sampled at the end of EI or DI
Table 7.0-5
126
No.ofM No.of T
Cvcles States
1
4
00 101 111
A - A+l
1M 2
No. of
Bvtes
1
Comments
Decimal adjust
accumulator
NEG
1M 1
00 100 111
Hex
27
Complement
accumulator
lOne's complement}
Negate acc, (two's
complement)
Campi ement carry
flag
Set carry flag
16-BIT ARITHMETIC GROUP
Symbolic
Operation
-HL+ss
Mnemonic
ADD HL,ss
H~
ADC HL, 55
HL -HL+ss+CY
S
··
I
PlY
X
FI gs
H
X X
•
N
0
Op·Code
C 76 543 210 Hex
I 00 ssl 001
X
X
X
V
0
I 11 101 101
Z
I
EO
No.of No.ofM NII.ofT
Bytes Cycles States Comments
Reg.
1
3
11
ss
BC
00
15
01
DE
4
2
10
HL
11
SP
14
2
15
DO
2
4
15
FD
2
4
15
1
2
1
2
6
10
2
2
10
1
2
1
2
6
10
2
2
10
ED
01 ssl 010
SBC HL,ss
HL - HL·ss·CY
ADD IX, pp
ADD IY, rr
I
I
X
X
X
V
1
!
IX-IX+pp
• •
X
X
X
•
0
I
IY-IY+rr
··
X
X
X
•
0
I 11 111 101
INC ss
INC IX
ss-ss+l
IX - IX+ 1
• •
• •
X
X
•
•
X
X
• • •
• • •
INC IY
IY - IY+l
• •
X
•
X
• • •
DECss
DEC IX
ss_ss·l
IX - IX· 1
• •
• •
X
X
•
•
X
X
• • •
DECIY
IY -IY·'
• •
X
•
X
• • •
Notes:
• • •
11
01
11
00
101
ssO
011
ppl
101
010
101
001
00 rrl
001
00 ssO
11 011
00 100
11 111
00 100
00 ssl
11 011
00 101
11111
00 101
011
101
011
101
011
DO
23
FD
23
all
101
011
101
011
DO
2B
FO
2B
pp
00
01
10
11
rr
00
01
10
11
Reg.
BC
DE
IX
SP
Reg.
BC
DE
IY
SP
I
ss is any of the register pairs BC, DE, HL, SP
pp is any of the register pairs BC, DE, IX, SP
rr is any of the register pairs BC, DE, IY, SP.
Flag Notation: •
!
flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown.
= flag is affected according to the result of the operation.
=
Table 7.0-6
127
ROTATE AND SHIFT GROUP
Symbolic
FI gs
Op·Code
PI
Operation
V
N C 76543210
• •
X
0
X
•
0
\
00 000 111
07
1
1
4
Rotate left circular
accumulator
• •
X
0
X
•
0
\ 00 010 111
17
1
1
4
Rotate left
accu mu lator
~
··
X
0
X
0
I 00 001 111
OF 11
1
4
Rotate right circular
accumulator
~J
• •
X
0
X
0
j 00 011 111
1 F jl
1
4
Rotate right
accumulator
j 11
00
I 11
00
CB 12
2
8
CB ,2
,4
15
[4
6
23
6
123
Mnemonic
5
[ITlLEQ}J
RLCA
No.of No.of No.of
M T
Hex Bytes Cycles States Comments
H
Z
A
LIITJ~1..
RLA
A
RRCA
A
RRA
A
·
·
RLC r
j
j
X
0
X
p
0
RLC (HU
I
j
X
0
X
p
0
I
I X 0 X
P
0
rm-LtE[jJ
RLC (IX+d)
r.(H U.(iX+d),(iY+d)
RLC (iY+d)
II
j 11 011 101
11 001 011
d
00 [QQQjll0
DO
CB
I 11 111 101
FD
CB
-
Ij I
/
001 011
[QQQj r
001 011
[QQQjll 0
X
0
X
P
0
-
11 001 011
d
00 IQ@ 110
- -
RLs
4fu-[EQJJ
\ \
X
0
X
P
0
\
IDill
I
j
X
0
X
p
0
\
[QIDJ
\ I
X
0
X
P
0
j
IQIjJ
I I
X
0
X
P
0
\
[QID
I
RRGs
LjGJltrn
Instruction format and
states are as shown for
RLC's. To form new
Dp· Code replace lQQQl
of RLC's with shown
code
!
s =r,(HU,(iX+d),(iY+d)
s =r,(HU,(iX+d),(iY+d)
RRs
W-ol-lillJ
s =r,(HU,(iX+d),(iY+d)
SLAs
0-17-01-0
s =r,(HL),(iX+d),(iY+d)
cj -
0 l---Jill
s =r,(HU,(iX+d),(iY+d)
j
\
X
0
X
P
0
I
[QIJ
SRLs
0-17 0 I-Jill
s =r,(HU,(iX+d),(lY+d)
I
j
X
0
X
p
0
I
[ill
RLO
A 17.413iOI
1~-lliOI(HL I I
X
0
X
P
0
• 11 101 101
01 101 111
6F
• 11 101 101
01 100 111
ED
67
SRAs
RRD
A tJ-413iOI
1}-§OI(HL)
\ \
X
0
X
p
0
Flag Notation; • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
Table 7.0-7
128
Rotate left circular
register r
Reg.
r
B
000
C
1001
0
010
011
E
1
H
100
101
L
111
A
ED 12
2
15
11
15
1
Rotate digit left and
right between the
accumulator
and location (H U.
The content of the
upper half of the
accumulator is
unaffected
BIT SET, RESET AND TEST GROUP
X
Flags
H
PlY
1 X X
N
0
I
X
1
X
X
0
I
X
1
X
X
0
Mnemonic
BIT b, r
Symbolic
Operation
Z - rb
S Z
X I
BITb, (HU
Z -ffiDb
X
BIT b, (lX+d1b
Z - (lX+d1b
X
No. 01 No.oIM No.ofT
Bytes Cycles States
2
8
2
CB
2
3
12
DO
CB
4
5
20
11 111 101
11 001 011
d
01 b 110
FD
CB
4
5
20
11 001 011
r
IDJb
11 001 011
[IDJ b 110
11 011 101
11 001 011
d
[jJb 110
11 111 101
11 001 011
d
IDJ b 110
CB
2
2
8
CB
2
4
15
•
•
•
-
01
BIT b, (IY+d1b
Z - (IY+d1b
SET b, r
rb - 1
SET b, (HU
(HUb - 1
SET b, (lX+dl
(lX+dlb - 1
SET b, (lY+dl
RES b, s
(lY+d1b - 1
sb - 0
s=r,(HU,
(lX+d),
(lY+dl
X
I
• •
X
1
•
X
·• • •
· ·
X
X
• •
• •
•
X
X
0
X
X
0
X
• •
X
• •
X
·
·•
• • •
-
-
X
X
•
0
··0
Op·Code
543 210
001 011
b r
001 011
b 110
011 101
001 011
Hex
CB
C 76
11
01
11
01
11
11
d
-
b 110
-
-
-
oil]]
I
Notes:
The notation sb indicates bit b (0 to
Flag Notation: •
7)
Comments
Reg.
r
B
000
001
C
0
010
E
011
H
100
101
L
111
A
Bit Tested
b
000
0
001
1
010
2
3
011
4
100
101
5
110
6
111
7
,
DO
CB
4
6
23
FD
CB
4
6
23
To form new Ow
Code replace []]
of SET b, s with
[Q]. Flags and time
states for SET
instruction
or location s.
=flag not affected, 0 =flag reset, 1 =flag set, X =flag is unknown,
1= flag is affected according to the result of the operation.
Table 7.0-8
129
JUMP GROUP
Mnemonic
JP nn
Symbolic
Operation
PC· nn
S
Z
• •
X
Flags
H
X
•
PlY
N
Op-Code
C 76 543 210 Hex
11 000 011
C3
n
n
11 cc 010
n
n
• • •
JP CC, nn
If condition cc
is true PC • nn,
otherwise
continue
• •
X
•
X
JR e
PC - PC + e
• •
X
•
X
• • •
JR C, e
• •
X
•
X
• • •
JP (HU
If C = 0,
continue
If C = I,
PC -. PC+e
If C = I,
continue
If C = 0,
PC· PC+e
If Z = 0
continue
If Z = I,
PC· PC+e
If Z = I,
continue
If Z = 0,
PC· PC+e
PC - Hl
• •
X
•
X
JP(lX)
PC - IX
• •
X
•
X
JR NC, e
JR Z, e
JR NZ, e
• •
• •
• •
X
X
X
•
•
•
X
X
X
.
·
·
• • •
·
-
• • •
• • •
• • •
JP(IV)
PC· IV
• •
X
•
X
• • •
• • •
• • •
DJNZ, e
B - 8-1
If B = 0,
continue
• •
X
•
X
• • •
011 000
e-2
111 000
e-2
-
00 110 000
- e-2
2
3
12
38
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is met
-
28
00 100 000
• e-2
-
20
11 101 001
E9
1
1
4
11
11
11
11
101
001
101
001
00
2
2
8
E9
FO
E9
2
2
8
00 010 000
- e-2
10
2
2
8
If B = 0
2
3
13
If 8 .; 0
011
101
111
101
-
e-2 in the op-code provides an effective address of pc+e as PC is
incremented by 2 prior to the addition of e.
=flag not affected, 0 =flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
130
18
000
001
010
011
100
101
110
111
00 101 000
- e-2
e is a signed two's complement number in the range <:;126,129>
Table 7.0-9
10
30
e represents the extension in the relative addressing mode.
Flag Notation: •
Condition
NZ non zero
Z zero
NC non carry
C carry
PO parity odd
PE parity even
P sign positive
M sign negative
3
-
If B'; 0,
PC - PC+e
Notes:
cc
3
- --
00
00
-
No.of No.ofM No.ofT
Bytes Cycles States Comments
3
3
10
CALLAND RETURN GROUP
Symbolic
Ope,ation
S
(Sp·ll - PCH
(SP·2) - PCl
PC - nn
Mnemonic
CAll nn
CAllcc, nn If condition
cc is false
continue,
Flags
H
Z
P/V
• •
X
•
X
•
• •
X
•
X
•
N
Op·Code
C 76 543 210 Hex
11 001 101 CO
n
n
·•·•-
--
11 cc 100
n
n
-.•
-
otherwise
same as
No. of NonfM No.of T
Bytes Cycles States Comments
3
17
5
3
3
10
If cc is false
3
5
17
If cc is t,ue
1
3
10
1
1
5
If cc is false
1
3
11
2
4
14
2
4
14
If cc
cc
000
001
010
all
100
101
110
111
1
3
11
CALL nn
RET
PCl - (SP)
PCH - (SP+1)
• •
X
•
X
• • •
11 001 001
RET cc
If condition
cc is false
• •
X
•
X
·•
11 cc 000
•
C9
continue,
otherwise
same as
RET
RET!
Return from
interrupt
Return from
RETNI
non maskable
• •
X
•
X
• •
·•
X
•
X
•
• •
X
• 11
101
111
101
101
001
101
000
101
101
101
101
• 111
t
111
·•
ED
40
ED
45
interrupt
RST p
(Sp·l) (SP·2) PCH PCl -
PCH
PCl
0
P
•
X
• •
I
I
t
000
001
010
all
100
101
110
111
is true
Condition
NZ non zero
Z
zero
NC non carry
carry
C
PO
parity odd
PE
parity even
P
sign positive
M
sign negative
P
DOH
08H
10H
18H
20H
28H
30H
38H
1 RETN loads IFF2 - IFFI
Flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I =flag is affected according to the result of the operation.
Table 7.0-10
131
INPUT AND OUTPUT GROUP
Mnemonic
IN A, (n)
Symbolic
Operation
A - (n)
S
Z
FI gs
H
X
'X
·
p
0
•
X X
X
1
X 11 101 1011
10 100 010
X
X
I
X
r - (C)
if r = 110 only
the flags will
be affected
I
INI
(HL) - (C)
8 - 6·1
HL-HL+l
(HL) • (C)
6 - 8·1
HL-HL+l
Repeat until
8=0
X
j
Op-Code
C 76 543 210 Hex
11 011 011
08
•
• •
IN r, (C)
P!V N
•
•
- -
INIR
X
1
No.ofM No.of T
Cycles States
3
11
ED
2
3
12
ED
2
4
16
C to AO - A7
6to AS - A15
2
21
5
(If 810)
4
16
018=0)
C to AO - A7
8 to AS - A15
n
11 101 101
01 r 000
Comments
n to AO - A7
Ace to AS - A15
C to AO - A7
B to AS - A15
I
CD
I
No.of
Bytes
2
X
X
X
X
1
X 11 101 101
10 110 010
A2
ED
82
2
CD
INO
OUT (nl. A
(HL) - (C)
8 - 8·1
HL-HL·'
(HL) • (C)
6 - 8·1
HL- HL·l
Repeat until
8=0
(n)-A
• •
X
•
X
• • •
11 010 011
03
OUT (C), r
(C) - r
• •
X
•
X
• • •
11 101 101
01 r 001
OUTI
(C) - (HL)
8 - 6·1
HL-HL+l
(C) - (HLl
6 - 8·1
HL-HL+l
Repeat until
8=0
X
CD
t
X
X
X
X
(e) - (HLl
X
INOR
OTIR
OUTO
OTOR
Notes:
CD
8 - 8·1
HL-HL·l
(C) • (HLl
8 - 6·1
HL-HL·l
Repeat until
6=0
X
j
X
X X
X
1
X 11 101 101
10 101 010
ED
AA
X
1
X
X
X
1
X 11 101 101
10 111 010
8A
X
X
1
X
X
X
X
1
16
C to AO - A7
8 to AS - A15
2
5
21
(If 610)
4
16
(If 8 = 0)
C to AD - A7
8 to AS - A15
2
3
11
ED
2
3
12
n to AD - A7
Ace to AS - A15
C to AO - A7
8 to AS - A15
ED
2
4
116
Cto AO - A7
8 to AS - A15
2
5
21
(If 810)
4
16
(If 8 = 0)
Cto AO - A7
6 to AS - A15
16
Cto AO - A7
8to AS - A15
5
21
(If 810)
4
16
(If 8 = 0)
Cto AO - A7
Bto AS - A15
ED
1
X 11 101 101
10 100 011
A3
X 11 101 101
10 110 011
83
I
ED
2
X
CD
t
1
X
X
X
X
X
X
X
X
1
1
X 11 101 101
10 101 011
A8
X 11 101 101
10111011
88
flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
132
4
2
If the result of 8· 1 is zero the Z flag is set, otherwise it is reset.
Table 7.0-11
2
ED
ED
12
2
2
4
8.0 INTERRUPT RESPONSE
The prupose of an interrupt is to allow peripheral devices to suspend CPU operation in an
orderly manner and force the CPU to start a peripheral service routine. Usually this service
routine is involved with the exchange of data, or status and control information, between
the CPU and the peripheral. Once the service routine is completed, the CPU returns to the
operation from wnich it was interrupted.
INTERRUPT ENABLE - DISABLE
The Z80-CPU has two interrupt inputs, a software maskable interrupt and a non-maskable
interrupt. The non...maskable interrupt (~) can not be disabled by the programmer and
it will be accepted whenever a peripheral device requests it. This interrupt is generally
reserved for very important functions that must be serviced whenever they occur, such as
an impending power failure. The maskable interrupt (iNT) Can be selectively enabled or
disabled by the programmer. This allows the programmer to disable the interrupt during
periods where his program has timing constraints that do not allow.it to be interrupted.
In the Z8(}-CPU there is an enable flip flop (called IFF) that is set or reset by the programmer using the Enable Interrupt (EI) and Disable Interrupt (01) instructions. When the
IFF is reset, an interrupt can not be accepted by the CPU.
Actually, for purposes that will be subsequently explained, there are two enable flip flops,
called IFF, and IFF2'
IIFF11
Actually disables interrupts
from being accepted.
Temporary storage location
for IFF 1.
The state of IFF1 is used to actually inhibit interrupts while IFF2 is used as a temporary
storage location for IFF1' The purpose of storing the IFF1 will be subsequently explained.
A reset to the CPU will force both IFF1 and IFF2 to the reset state so that interrupts are
disabled. They can then be enabled by an EI instruction at any time by the programmer.
When an EI instruction is executed, any pending interrupt request will not be accepted until
after the instruction following EI has been executed. This single instruction delay is necessary for cases when the following instruction is a return instruction and interrupts must not
be allowed until the return has been completed. The EI instructions sets both IFF 1 and
IFF2 to the enable state. When an interrupt is accepted by the CPU, both IFF1 and IFF2
are automatically reset, inhibiting further interrupts until the programmer wishes to issue a
new EI instruction. Note that for all ofthe previous cases, IFF 1 and IF F2 are always equal.
The purpose of IFF2 is to save the status of IFF1 when a non-maskable interrupt occurs.
When a non-maskable interrupt is accepted, IFF 1 is reset to prevent further interrupts
until reenabled by the programmer. Thus, after a non-maskable interrupt has been accepted
maskable interrupts are disabled but the previous state of IFF 1 has been saved so that the
complete state of the CPU just prior to the non-maskable interrupt can be restored at any
time. When a Load Register A with Register I (LD A, I) instruction or a Load Register A
with Register R (LD A, R) instruction is executed, the state of I FF2 is copied into the
parity flag where it can be tested or stored.
A second method of restoring the status of IFF 1 is thru the execution of a Return From
Non-Maskable Interrupt (RETN) instruction. Since this instruction indicates that the non
maskable interrupt service routine is complete, the contents of I FF2 are now copied back
into IFF 1, so that the status of IFF 1 just prior to the acceptance of thenon-maskable
interrupt will be restored automatically.
133
Figure B.0-1 is a summary of the effect of different instructions on the two enable flip flops.
INTERRUPT ENABLE/DISABLE FLIP FLOPS
Action
IFF I IFF2
o
o
o
o
LDA,R
•
•
•
•
Accept NMI
o
•
IFF2
•
o
0
•
•
CPU Reset
DI
EI
LD A,I
RETN
Accept INT
RETI
FIGURE 8.0-1
IFF 2 -+ Parity flag
IFF 2 -+ Parity flag
"." indicates no change
CPU RESPONSE
Non-Maskable
A non-maskable interrupt will be accepted at all times by the CPU. When this occurs, the
CPU ignores the next instruction that it fetches and instead does a restart to location
0066H. Thus, it behaves exactly as if it had received a restart instruction but, it is to a
location that is not one of the B software restart locations. A restart is merely a call to a
specific address in page 0 memory.
Maskable
The CPU can be programmed to respond to the maskable interrupt in anyone of three
possible modes.
Mode 0
This mode is identical to the BOBOA interrupt response mode. With this mode, the interrupting device can place any instruction on the data bus and the CPU will execute it. Thus, the
interrupting device provides the next instruction to be executed instead of the memory.
Often this will be a restart instruction since the interrupting device only need supply a
single byte instruction. Alternatively, any .other instruction such as a 3 byte call t.o any 1.0cation in mem.ory could be executed.
The number .of clock cycles necessary to execute this instructi.on is 2 more than the n.ormal
number for the instruction. This occurs since the CPU automatically adds 2 wait states t.o an
interrupt response cycle t.o allow sufficient time t.o implement an external daisy chain f.or
pri.ority c.ontrol. Section 4.0 illustrates the detailed timing f.or an interrupt resp.onse. After
the application .of RESET the CPU will aut.omatically enter interrupt M.ode O.
M.ode 1
When this m.ode has been selected by the pr.ogrammer, the CPU will resp.ond t.o an interrupt
by executing a restart t.o locati.on 003BH. Thus the response is identical to that for a n.on
maskable interrupt except that the call l.ocation is 003BH instead .of 0066H. Another
difference is that the number of cycles required to c.omplete the restart instructi.on is 2
m.ore than normal due t.o the tw.o added wait states.
134
Mode 2
This mode is the most powerful interrupt response mode. With a single 8-bit byte from the
user an indirect call can be made to any memory location.
With this mode the programmer maintains a table of 16 bit starting addresses for every interrupt service routine. This table may be located anywhere in memory. When an interrupt
is accepted, a 16 bit pointer must be formed to obtain the desired interrupt service routine
starting address from the table. The upper 8 bits of this pointer is formed from the contents
of the I register. The I register must have been previously loaded with the desired value by
the programmer, i.e. LD I, A. Note that a CPU reset clears the I register so that it is initialized to zero. The lower eight bits of the pointer must be supplied by the interrupting
device. Actually, only 7. bits are required from the interrupting device as the least
bit must be a zero. This is required since the pointer is used to get two adjacent bytes to
from a complete 16 bit service routine starting address and the addresses must always start
in even locations.
Interrupt
Service
Routine
Starting
Address
Table
desired starting address
pointed to by:
low order }
high order
I REG
CONTENTS
The first byte in the table is the least significant (low order) portion of the address. The
programmer must obviously fill this table in with the desired addresses before any interrupts
are to be accepted.
Note that this table can be changed at any time by the programmer (if it is stored in Read/
Write Memory) to allow different peripherals to be serviced by different service routines.
Once the interrupting device supplies the lower portion of the pointer, the CPU automatcally pushes the program counter onto the stack, obtains the starting address from the table
and does a jump to this address. This mode of response requires 19 clock periods to complete (7 to fetch the lower 8 bits from the interrupting device, 6 to save the program
counter, and 6 to obtain the jump address.)
Note that the Z80 peripheral devices all include a daisy chain priority interrupt structure
that automatically supplies the programmed vector to the CPU during interrupt acknowledge. Refer to the Z80-PIO, Z80-SIO and Z80-CTC manuals for details.
135
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
LastM Cvcle
MI
of Instruction
~n-~ ~~
-------
INT
AD-A15
X
MI
I
I
I
:
laRa
I
I
I
DATA BUS
I
\
I
~I.I
--'"'-----._- ------- ------1------- f-----I-----,..-7\.-------1"------ --------- ------I
,-----I
~------
RD
'](REFRESH
PC
\
MREO
WAIT
r--Lr-L ~
------- ~------ ___ ~L v:.------ ------- ------- ------------------- ------ ------- -------
I
I
I
I
I
I
Daisey Chain
Priority Frozen
:
i
I
Vector Placed
onto Data Bus
zao INTERRUPT ACKNOWLEDGE SUMMARY
1) PERIPHERAL DEVICE REQUESTS INTERRUPT. Any device requesting and interrupt
can pull the wired-or line INT low.
2) CPU ACKNOWLEDGES INTERRUPT. Priority status is frozen when M1 goes low
during the Interrupt Acknowledge sequence. Propagation delays down the lEI/lEO
daisy chain must be settled out when IORQ goes low. If lEI is HIGH, an active Peri·
pheral Device will place its Interrupt Vector on the Data Bus when iOFiQ goes low.
That Peripheral then releases its hold on INT allowing interrupts from a higher
priority device. Lower priority devices are inhibited from placing their Vector on
the Data Bus or Interrupting because lEO is low on the active device.
3) INTERRUPT IS CLEARED. An active Peripheral device (lEI=1, I EO=O) monitors
OP Code fetches for an RETI (ED 40) instruction which tells the peripheral that its
Interrupt Service Routine is over. The peripheral device then re-activates its internal
Inlerrupt structure as well as raising its I EO line to enable lower priority devices.
136
INTERRELATIONSHIP OF 00, NMi, AND BUSRQ
The following flow chart details the relationship of three control inputs to the Z80-CPU. Note
the following from the flow chart.
1. I NT and NM I are always acted on at the end of an instruction.
2. BUSRQ is acted on at the end of a machine cycle.
3. While the CPU is in the DMA MODE, it will not respond to active inputs on INT or NMI.
4. These three inputs are acted on in the following order of priority: a)BUSRQ b)NMI c)INT
Z80-CPU INTERRUPT SEQUENCE
NO
YES
YES
NO
SET NMI F/F
SET INT. F/F
RESET
BUSRQ F/F
NO
J
YES
NON
MASKABLE
INTERRUPT
YES
MASKABLE]
INTERRUPT
MODE
>---+f
137
138
9.0 HARDWARE IMPLEMENTATION EXAMPLES
This chapter is intended to serve as a basic introduction to implementing systems with the
zao-cpu.
MINIMUM SYSTEM
Figure 9.0-1 is a diagram of a very simple
following five elements:
1)
2)
3)
4)
5)
zao system.
Any
zao system must include the
Five volt power supply
Oscillator
Memory devices
I/O circuits
CPU
MINIMUM Z80 COMPUTER SYSTEM
AO-A,O
+5V
GND
MREO
AD
+5V
RESET
J
MK 3880
Z80
CPU
DATA BUS
10RO
AO
M1
A,
OUTPUT
DATA
INPUT
DATA
FIGURE 9.0-1
zao-cpu
Since the
only requires a single 5 volt supply, most small systems can be implemented using only this single supply.
The oscillator can be very simple since the only requirement is that it be a 5 volt square
wave. For systems not running at full speed, a simple RC oscillator can be used. When the
CPU is operated near the highest possible frequency, a crystal oscillator is generally required
because the system timing will not tolerate the drift or jitter that an RC network will
generate. A crystal oscillator can be made from inverters and a few discrete components
or monolithic circuits are widely available.
The external memory can be any mixture of standard RAM, ROM, or PROM. In this simple
example we have shown a single 16K bit ROM (2K bytes) being utilized as the entire memory
system. For this example we have assumed that the Z80 internal register configuration
contains sufficient ReadlWrite storage so that external RAM memory is not required.
139
Every computer system requires I/O circuits to allow it to interface to the "real world."
In this simple example it is assumed that the output is an 8 bit control vector and the input
is an 8 bit status word. The input data could be gated onto the data bus using any standard
tri-state driver while the output data could be latched with any type of standard TTL latch.
For this example we have used a Z80-P10 for the I/O circuit. This single circuit attaches to
the data bus as shown and provides the required 16 bits of TTL compatible I/O. (Refer to
the zao-Plo manual for details on the operation of this circuit.) Notice in this example that
with only three LSI circuits, a simple oscillator and a single 5 volt power supply, a powerful
computer has been implemented.
ADDING RAM
Most computer systems require some amount of external Read/Write memory for data
storage and to implement a "stack". Figure 9.0-2 illustrates how 256 bytes of static memory
can be added to the previous example. In this example the memory space is assumed to be
organized as follows:
ROM & RAM IMPLEMENTATION EXAMPLE
ADDRESS
r - - - - , OOOOH
2 K bytes
t-_R_O_M_-i 07FFH
256 bytes 0800H
RAM
~
08 FFH
Ao-A7
AO-AtO
!>-
-
~
All
~
(
ADDRESS BUS
CEI
~2
CE3
MK 34000
2Kx8
-.BQ
00
~ R/W
ROM
256 x 8
RAM
GEl ~
All
CE2 r - ' - -
'>
00 -0 7
\
'"
Do -0 7
;-
".
DATA BUS
(
FIGURE 9.0-2
In this diagram the address space is described in hexidecimal notation. For this example,
address bit A 11 separates the ROM space from the RAM space so that it can be used for the
chip select function. For larger amounts of external ROM or RAM, a simple TT L decoder
will be required to form the chip selects.
MEMORY SPEED CONTROL
For many applications, it may be desirable to use slow memories to reduce costs. The
WAIT line on the CPU allows the zao to operate with any speed memory. By referring
back to section 4 you will notice that the memory access time requirements are most
severe during the M1 cycle instruction fetch. All other memory accesses have an additional
one half of a clock cycle to be completed. For this reason it may be desirable in some
applications to add one wait state to the Ml cycle so that slower memories can be used.
Figure 9.0-3 is an example of a simple circuit that will accomplish this task. This circuit can
be changed to add a single wait state to any memory access as shown in F,gure 9.0-4.
140
ADDING ONE WAIT STATE TO AN Ml CYCLE
+5V
141"---Ml---~"1
I Tl I
Ml
<1>,
0
0
7474
c
0
T2
I
Tw
I
T3
I
T4
I
J\.JLJLJ\.JLJ
0
7474
a
a
c
R
R
+5V
+5V
FIGURE 9.0-3
ADDING ONE WAIT STATE TO ANY MEMORY CYCLE
+5V
o
o
o
0
C
7474
C
7474
MREO
--"1...._____
0
R
R
+5V
+5V
FIGURE 9.0-4
INTERFACING DYNAMIC MEMORIES
This section is intended only to serve as a brief introduction to interfacing dynamic
memories. Each individual dynamic RAM has varying specifications that will require minor
modifications to the description given here and no attempt will be made in this document
to give details for any particular RAM.
Figure 9.0-5 illustrates the logic necessary to interface 8K bytes of dynamic RAM using
l6-pin 4K dynamic memories. This Figure assumes that the RAM's are the only memory in
the system so that A12 is used to select between the two pages of memory. During refresh
time, all memories in the system must be read. The CPU provides the proper refresh address
on lines AO through A6. To add additional memory to the system it is necessary to only
replace the two gates that operate on A12 with a decoder that operates on all required
address bits. For larger systems, buffering for the address and data bus is also generally
required.
An application note entitled "Z80 Interfacing Techniques for Dynamic RAM" is available from your MOSTEK representative which describes dynamic RAM design techniques.
141
INTERFACING DYNAMIC RAMS
DELAY
I--~
DELAY
CAS
R!W
.~
i
]'-..-J
RAS
f
ACTA"
00-07
AO-AS
1
1'~
ADDRESS
MULTIPLEXER
DATA
BUS
CAS
MUX
CONTROL
ADDRESS
BUS
4Kx8 DYNAMIC PAGE
RAM MEMORY (10001o IFFFl
ARRAY
R!W
-
'---
RAS
4Kx8 DYNAMIC PAGE o
RAM MEMORY (00001o OFFF)
ARRAY
• NO REFRESH ADDRESS MULTIPLEXER REQUIRED
• MREQ INITIATES MEMORY CYCLE
• ~ SELECTS REFRESH CYCLE
FIGURE 9.0-5
Z80-CPU DESIGN CONSIDERATIONS: CLOCK CIRCUITRY
When using the Z80-CPU at less than its rated speed, the Clock Input (cI» can be driven by a
7400 TTL gate with a resistor pull up (typically 330 ohms) to +5 Volts. Because of dynamic
currents flowing into the Clock Input Pin, the rise time of the Clock Input waveform will
be typically 60-80 nanoseconds. The resistor will eventually pull the clock input up to Vcc
but with a slow rise time which will limit the maximum frequency of operation. Figure
9.0-6 shows a Clock Input driver which has an active pull-up and which will allow maximum
frequency operation. The circuit is recommended for all but the most cost sensitive Z80
applications.
Z80 CPU CLOCK BUFFER CIRCUI7RY
33pf
22
2N3906
FROM
OSCILLATOR
FIGURE 9.0~6
142
or Equivalent
CLOCK
INPUT
RESET CIRCUITRY
The ZBO-CPU has the characteristic that if the RESET input goes low during T2 or T4 of a
cycle that the MREQ signal will go to an indeterminate state for one T-State approximately
3 T-States later. If there are dynamic memories in the system this action could cause an
aborted or short access of the dynamic RAM which could cause destruction of data within
the RAM. If the contents of RAM are of no concern after RESET, then this characteristic
is no problem as the CPU always resets properly. If RAM contents must be preserved,
then the falling edge of the RESET input must be synchronized by the falling edge of I'iifi'.
The circuitry of Figure 9.0-7 does this synchronization as well as providing a one-shot
to limit the duration of the CPU RESET pulse. The CPU RESET signal must be a pulse
even though the EXTERNAL RESET button is held closed to avoid suspending the CPU
refresh of dynamic RAM for a time long enough to destroy data in the RAM.
MANUAL AND POWER-ON RESET CIRCUIT
+5
+5
10K
+5
o
EXTERNAL
RESET
S
a~---4
220n
7414
FIGURE 9.0-7
ADDRESS LATCHING
In order to guarantee proper operation of the ZBO-CPU with dynamic RAMs the upper
4 bits of the address should ,be latched as shown in Figure 9.O-B. This action is required
because the ZBO-CPU does not guarantee that the Address Bus will hold valid before the
rising edge of MREQ on an OP Code Fetch.
This action does not directly affect dynamic memories because they latch addresses internally. The problem comes from the address decoder which generates RAS. If the address
lines which drive the decoder are .allowed to change while MREQ is low, then a "glitch"
can occur on the RAS line or lines, which may have the effect of destroying one row of
data within the dynamic RAM.
143
ADDRESS LATCH
74LS75
A12
10
10
A12
A13
2D
20
A13
A14
3D
30
A14
A15
4D
40
A15
zao-cpu
G
DYNAMIC
RAM
DECODING
CIRCUITRY
G
LJ
T o RAS DECODE
FIGURE 9.0-8
RAs TIMING WITH AND WITHOUT ADDRESS LATCH.
\~
________O_P_C_O_D_E_F_E_T_C_H______
~/
VALID MEMORY ADDRESS
FIGURE 9.0-9
144
\
REFRESH ADDRESS
VALID REFRESH ADDRESS
LATC~
AJ
\
WITHOUT ADDRESS
\~
____
W_IT_H__
A_D_D_R_ES_S_L_A_T_C_H____
--J/
/
10.0 SOFTWARE IMPLEMENTATION EXAMPLES
10.1 Methods of Software Implementation
Several different approaches are possible in developing software for the l80 (Figure 10.1)
First of all, Assembly Language or a high level language may be used as the source language.
These languages may then be translated into machine language on a commercial time sharing
facility using a cross-assembler or cross-compiler or, in the case of assembly language, the
translation can be accomplished on a l80 Development System using a resident assembler.
Finally, the resulting machine code can be debugged either on a time-sharing facility using
a l80 simulator or on a l80 Development System which uses a l80-CPU directly.
SOFTWARE GENERATION TECHNIQUES
SOURCE
LANGUAGE
TRANSLATION
DEBUGGING
RESIDENT ASSEMBLER
CROSS ASSEMBLER
CROSS COMPI LE R
FIGURE 10.1
In selecting a source language, the primary factors to be considered are clarity and ease of
programming vs. code efficiency. A high level language with its machine independent constraints is typically better for formulating and maintaining algorithms, but the resulting
machine code is usually somewhat less efficient than what can be written directly in assembly language. These tradeoffs can often be balanced by combining high level language and
assembly language routines, identifying those portions of a task which must be optimized
and writing them as assembly language subroutines.
Deciding whether to use a resident or cross assembler is a matter of availability and shortterm vs. long-term expense. While the initial expenditure for a development system is higher
than that for a time-sharing terminal, the cost of an individual assembly using a resident
assembler is negligible while the same operation on a time-sharing system is relatively
expensive and in a short time this cost can equal the total cost of a development system.
Debugging on a development system vs. a simulator is also a matter of availability and expense combined with operational fidelity and flexibility. As with the assembly process,
debugging is less expensive on a development system than on a simulator available through
time-sharing. In addition, the fidelity of the operating environment is preserved through
real-time execution on a l80-CPU and by connecting the I/O and memory components
which will actually be used in the production system. The only advantage to the use of a
simulator is the range of criteria which may be selected for such debugging procedures
as tracing and setting breakpoints. This flexibility exists because a software simulation can
achieve any degree of complexity in its interpretation of machine instructions while development system procedures have hardware limitations such as the capacity of the real-time
storage module, the number of breakpoint registers and the pin configuration of the CPU.
Despite such hardware limitations, debugging on a development system is typically more
productive than on a simulator because of the direct interaction that is possible between
the programmer and the authentic execution of his program.
145
10.2 Software Features Offered by the
zao-cpu
The zao instruction set provides the user with a large and flexible repetoire of operations
with which to formulate control of the zao-cpu.
The primary, auxiliary and index registers can be used to hold the arguments of arithmetic
and logical operations, or to form memory addresses, or as fast-access storage for frequently
used data.
Information can be moved directly from register to register; from memory to memory;
from memory to registers; or from registers to memory. In addition, register contents and
register/memory contents can be exchanged without using temporary storage. In particular,
the contents of primary and auxiliary registers can be completely exchanged by executing
only two instructions. EX and EXX. This register exchange procedure can be used to
separate the set of working registers between different logical procedures or to expand the
set of available registers in a single procedure.
Storage and retrieval of data between pairs of registers and memory can be controlled on
a last-in first-out basis through PUSH and POP instructions which utilize a special stack
pointer register, SP. This stack register is available both to manipulate data and to automatically store and retrieve addresses for subroutine linkage. When a subroutine is called,
for example, the address following the CALL instruction is placed on the top of the pushdown stack pointed to by SP. When a subroutine returns to the calling routine, the address
on the top of the stack is used to set the program counter for the address of the next
instruction. The stack pointer is adjusted automatically to reflect the current "top" stack
position during PUSH, POP, CALL and RET instructions. This stack mechanism allows
pushdown data stacks and subroutine calls to be nested to any practical depth becaust) the
stack area can potentially be as large as memory space.
The sequence of instruction execution can be controlled by six different flags (carry, zero,
sign, parity/overflow, add-subtract, half-carry) which reflect the results of arithmetic, logical,
shift and compare instructions. After the execution of an instruction which sets a flag,
that flag can be used to control a conditional jump or return instruction. These instructions
provide logical control following the manipulation of single bit, eight-bit byte (or) sixteenbit data quantities.
A full set of logical operations, including AND, OR, XOR (exclusive -OR), CPL (NOR) and
NEG (two's complement) are available for Boolean operations between the accumulator and
1) all other eight-bit registers, 2) memory locations or 3) immediate operands.
In addition, a full set of arithmetic and logical shifts in both directions are available which
operate on the contents of all eight-bit primary registers or di rectly on any memory location.
The carry flag can be included or simply set by these shift instructions to provide both the
testing of shift results and to link register/register or register/memory shift operations.
10.3 Examples of Use of Special
A.
Let us assume that a string of data in memory starting at location "DATA" is to be
moved into another area of memory starting at location "BUFFER" and that the
string length is 737 bytes. This operation can be accomplished as follows:
LD
LD
LD
LDIR
146
zao Instructions
HL,DATA
DE,BUFFER
BC,737
;START ADDRESS OF DATA STRING
;START ADDRESS OF TARGET BUFFER
;LENGTH OF DATA STRING
TRANSFER MEMORY
;MOVE STRING
;POINTED TO BY HL INTO MEMORY
;LOCATION POINTED TO BY DE INCREMENT
;HL AND DE, DECREMENT BC PROCESS
;UNTI L BC=O.
11 bytes are required for this operation and each byte of data is moved in 21 clock cycles.
B.
Let's assume that a string in memory starting at location "DATA" is to be moved
into another area of memory starting at location "BUFFER" until an ASCII $ char·
acter (used as string delimiter) is found. Let's also assume that the maximum string
length is 132 characters. The operation can be performed as follows:
LD
LD
LD
LD
LOOP:CP
HL,DATA
DE,BUFFER
BC,132
A,'$'
(HL)
JR
LDI
Z, END-$
JP
PE,LOOP
END:
;STARTING ADDRESS OF DATA STRING
;STARTING ADDRESS OF TARGET BUFFER
;MAXIMUM STRING LENGTH
;STRING DELIMITER CODE
;COMPARE MEMORY CONTENTS WITH DE·
;LlMITER
;GO TO END IF CHARACTERS EQUAL
;MOVE CHARACTER (HL) TO (DE)
;INCREMENT HL AND DE, DECREMENT BC
;GO TO "LOOP"
IF MORE CHARACTERS
;OTHERWISE, FALL THROUGH
;NOTE: P/V FLAG IS USED
;TO INDICATE THAT REGISTER BC WAS
;DECREMENTED TO ZERO.
19 bytes are required for this operation.
C.
Let us assume that a 16-digit decimal number represented in packed BCD format (two
BCD digits/byte) has to be shifted as shown in the Figure 10.2 in order to mechanize
BCD multiplication or division. The operation can be accomplished as follows:
LD
LD
XOR
ROTAT:RLD
INC
DJNZ
HL,DATA
B, COUNT
A
HL
ROTAT-$
;ADDRESS OF FIRST BYTE
;SHIFT COUNT
;CLEAR ACCUMULATOR
;ROTATE LEFT LOW ORDER DIGIT IN ACC
;WITH DIGITS IN (HL)
;ADVANCE MEMORY POINTER
;DECREMENT B AND GO TO ROTAT IF
;B IS NOT ZERO, OTHERWISE FALL THROUGH
BCD DATA SHIFTING
11 bytes are required for this operation.
.,,;r
L
/r
""""'-1-...-
~
/r
./"
/r
./"
~
...-
........., ~
~.
---
o
I
FIGURE 10.2
147
11 bytes are requ ired for th is operation.
D.
Let us assume that one number is to be subtracted from another and a) that they are
both in packed BCD format, b) that they are of equal but varying length, and c) that
the result is to be stored in the location of the minuend. The operation can be accomplished as follows:
LD
LD
LD
AND
SUBDEC:LD
SBC
HL, ARG1
DE, ARG2
B, LENGTH
A
A, (DE)
A, (HL)
bAA
LD
INC
INC
DJNZ
(HL),A
HL
DE
SUBDEC-$
;ADDRESS OF MINUEND
;ADDRESS OF SUBTRAHEND
;LENGTH OF TWO ARGUMENTS
;CLEAR CARRY FLAG
;SUBTRAHEND TO ACC
;SUBTRACT (HL) FROM ACC
;ADJUST RESULTTO DECIMAL CODED VALUE
;STORE RESULT
;ADVANCE MEMORY POINTERS
;DECREMENT B AND GO TO "SUBDEC" IF B
;NOT ZERO, OTHERWISE FALL THROUGH
17 bytes are required for this operation.
10.4 Examples of Programming Tasks
A.
The following program sorts an array of numbers each in the range <0,255> into
ascending order using a standard exchange sorting algorithm.
01/22/76
11:14:37
BUBBLE LISTING
LOC
OBJ CODE STMT SOURCE STATEMENT
1
*** STANDARD EXCHANGE (BUBBLE) SORT ROUTINE***
2
3
4
5
AT ENTRY: HL CONTAINS ADDRESS OF DATA
C CONTAINS NUMBER OF ELEMENTS TO BE SORTED
(1 SECOND, NO JUMP
;EXCHANGE ARRAY ELEMENTS
~ECORDEXCHANGEOCCURRED
;POINT TO NEXT DATA ELEMENT
;COUNT NUMBER OF COMPARISONS
;REPEAT IF MORE DATA PAIRS
;DETERMINE IF EXCHANGE OCCURRED
;CONTINUE IF DATA UNSORTED
;OTHERWISE, EXIT
;DESIGNATION OF FLAG BIT
;STORAGE FOR DATA ADDRESS
The following program multiplies two unsigned 16-bit integers and leaves the result
in the H L register pair.
01/22/76
11 :32:36
LOC
OBJ CODE
STMT
0000
MULTIPLY LISTING
SOURCE STATEMENT
MULT:;
0000
0002
0003
0004
0005
0008
OOOA
0610
4A
7B
EB
210000
CB39
lF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OOOB
3001
26
UNSIGNED SIXTEEN BIT INTEGER MUL TIPL Y.
ON ENTRANCE: MULTIPLIER IN HL.
MULTIPLICAND IN DE.
ON EXIT: RESULT IN HL.
REGISTERS USES:
MLOOP:
H
L
D
E
B
C
A
HIGH ORDER PARTIAL RESULT
LOW ORDER PARTIAL RESULT
HIGH ORDER MULTIPLICAND
LOW ORDER MULTIPLICAND
COUNTER FOR NUMBER OF SHIFTS
HIGH ORDER BITS OF MULTIPLIER
LOW ORDER BITS OF MULTIPLIER
LD
LD
LD
EX
LD
SRL
RR
B,16;
C,D;
A,E;
DE,HL;
HL,O;
C;
A;
JR
NC, NOADD·$
NUMBER OF BITS-INITIALIZE
MOVE MULTIPLIER
MOVE MULTIPLICAND
CLEAR PARTIAL RESULT
SHIFT MULTIPLIER RIGHT
LEAST SIGNI FICANT BIT IS
IN CARRY.
IF NO CARRY' SKIP THE ADD.
149
------
----
._,,"----
--"
01/22/76
150
11 :32:36
MULTIPLY LISTING (Cant'd.)
LOC
OBJ CODE
STMT SOURCE STATMENT
OOOD
19
27
OOOE
OOOF
0010
0011
0013
EB
29
EB
10F5
C9
29
30
31
32
33
34
ADD HL, DE;
NOADD:
EX DE,HL;
ADD HL,HL;
EX DE,HL;
DJNZ MLOOP·$;
RET;
END;
ELSE ADD MULTIPLICAND TO
PARTIAL RESULT.
SHIFT MULTIPLICANT LEFT
BY MULTIPLYING IT BY TWO.
REPEAT UNTIL NO MORE BITS.
11.0 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ....................................... Specified Operating Range
Storage Temperature ......... '" .....................................-65°C to +150°C
Voltage on Any Pin with Respect to Ground
............................... -0.3V to +7V
Power Dissipation ............................................................. 1.5W
D.C. CHARACTERISTICS
T A = O°C to 70°C, VCC = 5V ± 5% unless otherwise specified
MIN.
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
TEST CONDITION
V
VILC
Clock Input Low Voltage
-0.3
0.8
VIHC
Clock Input High Voltage
Vcc·.6
Vcc+.~
V
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCC
V
VOL
Output low Voltage
0.4
V
tOl = 1.8mA
VOH
Output High Voltage
V
IOH = -250 JlA
ICC
Power Supply Current
150*
mA
III
Input leakage Current
10
JlA
VIN
IlOH
Tri·State Output leakage Current in Float
10
JlA
VOUT = 2.4 to VCC
IlOl
Tri-State Output leakage Current in Float
-10
JlA
VOUT
ILD
Data Bus leakage Current in Input Mode
±10
JlA
~VIN~VCC
2.4
= 0 to VCC
= O.4V
*200mA for -4, -10 or -20 devices
CAPACITANCE
T A = 25° C, f = 1MHz unmeasured pins returned to ground
SYMBOL
PARAMETER
MAX. UNIT
C
Clock Capacitance
35
pF
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
10
pF
*Comment
Stresses above those listed under" Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect devic'e reliability.
151
MK 3880, MK 3880-10, MK 3880-20 Z80-CPU
A C CHARACTERISTICS
TA
= oOe to 7oo e,
Vee
= +5V ± 5%,
Unless Otherwise Noted
SIGNAL
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tc
tw(H)
tw(L)
tr,f
Clock
Clock
Clock
Clock
.4
[ 12]
(D)
2000
30
JlSec
tD(AD)
tF(AD)
tacm
Address Output Delay
Delay to Float
[1]
Address Stable Prior to 1iiiFlE5
(Memory Cycle)
[2]
Address Stable Prior to 10RO, Ro
or WR (I/O Cycle) _ _
__
Address Stable From RD, WR, 10RO or MREO [3]
[4]
Address Stable From Ri5 or WR
During Float
145
110
nsee
nsee
nsee
Data Output Del ay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During Ml Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Input Hold Time
230
90
AO·15
taci
tca
tcaf
tD(D)
tF(D)
tS(D)
DO·7
tS(RD)
tDL~(RD)
tDH(RD)
tDH;j;(BD)
tDL(WR)
tDL;j;(WR)
tDH(WR)
tw(WRi:.)
[8]
[9]
nsec
110
nsee
100
nsee
110
nsee
115 Delay
100
nsec
Falling Edge of Clock,
130
nsee
Rising Edge of Clock,
100
nsee
Falling Edge of Clock,
110
nsee
80
nsec
90
nsec
100
nsec
WFU2.elay From Rising Edge of Clock,
WR Low
WR Delay From Falling Edge of Clock
WR Low
WR Delay From Falling Edge of Clock,
WR High_
Pulse Width, WR Low
[10]
= 50pF
CL
= 50 pF
CL
= 50 pF
CL
= 50pF
CL
= 50pF
nsec
90
Rising Edge of Clock,
CL
nsee
10RO Delay From Rising Edge of
Clock, 10RO Low
10RO Delay From Falling Edge of
~ck, 10RO Low
10RO Delay From Rising Edge of
Clock, 10RO High
i5R'5 Delay From Falling Edge of
Clock, 10RO High
From
RD Low
RD..Q.elay From
RD Low
Ro Delay From
_Ro High
RD..Q.elay From
RD High
Except T3·Ml
nsee
tDH(MR)
tDL(i;(lR)
= 50pF
nsee
nsee
tDHi(MR)
CL
nsee
100
tDH(lR)
WR
nsee
MREO De2L.E!:.om Falling Edge of
Clock, MREO Low
tDL(lR)
RD
180
180
tDL
Ao-15
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tc
tw(H)
tw(L)
t r, f
Clock
Clock
Clock
Clock
.25
[12]
(D)
2000
30
/lSec
nsec
nsec
nsec
tD(AD)
tF(AD)
tacm
Address Output Delay
Delay to Float
Address Stable Prior to ~
(Memory Cycle)
Address Stable Prior to "j'('j"RQ, RD
or WR (I/O Cycle) _ _
__
Address Stable From RD, WR, 10RO or iiAi'fEQ
Address Stable From Ri5 or WR
During Float
110
90
[ 1]
nsec
nsec
nsec
[2]
nsee
[3]
[4]
nsee
nsec
taci
tea
tcaf
.J
tdci
tcdf
tH
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During Ml Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Input Hold Time
tDL(MR)
IIifR"Ea Delay From Falling Edge of
tD(D)
tF(D)
tS(MR)
tDH(RD)
tDL~(RD)
tDH(RD)
tDH-;j;(RD)
tDL(WR)
WR
Clock, MREO Low
MREO Delay From Rising Edge of
Clock, fimEQ High
MREO Delay From Falling Edge of
Clock, MREO High
Pulse Width, MREO Low
Pulse Width, fimEQ High
tDL(lR)
RD
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
tDL~(WR)
tDH(WR)
tw(WRL)
110
110
150
90
50
nsec
nsec
nsec
60
nsec
[5]
nsec
[6]
[7]
0
nsec
nsec
nsec
20
85
nsec
85
nsec
85
nsec
[8]
[9]
nsec
10RO Delay From Falling Edge of
Clock, 10RO Low
I01'fQ Delay From Rising Edge of
Clock, 10RO High
I01'fQ Delay From Falling Edge of
Clock, 10RO High
85
nsec
85
nsec
85
nsee
RD Delay From
RD Low
RD.Q.elay From
RD Low
RD..Q.elay From
RD High
RD.Q.elay From
RD High
Rising Edge of Clock,
85
nsec
Falling Edge of Clock,
95
nsec
Rising Edge of Clock,
85
nsec
Falling Edge of Clock,
85
nsee
Rising Edge of Clock,
65
nsec
Falling Edge of Clock,
80
nsec
Falling Edge of Clock,
80
nsec
WR..J2.!llay From
WR Low
WR Delay From
WR Low
WR Delay From
WR High _
Pulse Width, WR
Low
[10]
CL" 50pF
Except T3.M 1
CL" 50pF
CL" 50pF
nsec
nsec
75
Edge of
TEST CONDITIONS
CL "50pF
CL "50pF
CL" 50pF
nsec
NOTES:
A Data should be enabled onto the CPU data bus when RD is active. During interrupt acknowledge data should be enabled when M1
and lORa are both active.
S The RESEi' signal must be active for a minimum of 3 clock cycles.
(Cont'd. on page 83)
154
~IIK
3880-4 Z80A-CPU
SIGNAL
Ml
UNIT
Ml..Q!llay From Rising Edge of Clock
Ml Low
M'i.Qelay From Rising Edge of Clock,
Ml High
100
nsec
100
nsec
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock
RFSH High
130
nsec
120
nsec
PARAMETER
tDL(Ml)
tDH(Ml)
RFSH
MAX.
SYMBOL
tDL(RF)
tDH(RF)
MIN.
WAIT
tS(WT)
WAIT Setup Time to Falling Edge of
Clock
HALT
tD(HT)
HALT Delay Time From Falling Edge
of Clock
INT
ts(IT)
INT Setup Time to Rising Edge of Clock
80
nsec
NMI
tw(NML)
Pulse Width, NMI Low
80
nsec
BUSRO
ts(BO)
BUSRO Setup Time to Rising Edge of
Clock
50
nsec
BUSAK
tDL(BA)
300
BUSAK Delay From Rising Edge of
BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
ts(RS)
RESET Setup Time to Rising Edge of
Clock
tF(C)
De!ll to/Fr:Q!!I Float (MREO, lORa,
RD and WR)
tmr
iiii1 Stable Prior to
nsec
100
nsec
100
nsec
60
[11 J
= 50pF
CL
= 50pF
CL
= 50pF
CL
= 50pF
II
nsec
80
lORa (Interrupt Ack.)
CL
nsec
~k,
tDH(BA)
RESET
70
TEST CONDITION
nsec
nsec
LOAD CIRCUIT FOR OUTPUT
TEST POINT
= tw
[1 J tacm
( DATA OR CONTROL
I---i>}
DATA
CPU
INTERFACE {
B~S
HANDSHAKE
CPU
BUS
I/O
6
PERIPHERAL
INTERFACE
II
PIO CONTROL
LINES
8 '--i>OATA OR CONTROL
t:r-'7
1-_-i>}HANDSHAKE
INTERRUPT CONTROL LINES
The Port I/O logic is composed of 6 registers with "handshake" control logic as shown in
figure 2.0-2. The registers include: an 8 bit data input register, an 8 bit data output register,
a 2 bit mode control register, an 8 bit mask register, an 8 bit input/output select register,
and a 2 bit mask control register.
PORT I/O BLOCK DIAGRAM
Figure 2.0-2
8BIT
PERIPHERAL
DATA OR
CONTROL BUS
MASK
CONTROL
REG
12 BITS)
t-::==Si
t-
MASK
REG
(8 BITS)
1.......- - - - - 1
DATA
INPUT
I/'-,-;;==c:-I ~E~TS)
INTERRUPT
REQUESTS
173
The 2-bit mode control register is loaded by the CPU to select the desired operating mode
(byte output, byte input, byte bidirectional bus, or bit control mode). All data transfer
between the peripheral device and the CPU is achieved through the data input and data
output registers. Data may be written into the output register by the CPU or read back to
the CPU from the input register at any time. The handshake lines associated with each port
are used to control the data transfer between the Pia and the peripheral device.
The 8-bit mask register and the 8-bit input/output select register are used only in the bit
control mode. In this mode any of the 8 peripheral data or control bus pins can be programmed to be an input or an output as specified by the select register. The mask register
is used in this mode in conjunction with a special interrupt feature. This feature allows an
interrupt to be generated when any or all of the unmasked pins reach a specified state
(either high or low). The 2-bit mask control register specifies the active state desired (high
or low) and if the interrupt should be generated when all unmasked pins are active (AND
condition) or when any unmasked pin is active (OR condition). This feature reduces the
requirement for CPU status checking of the peripheral by allowing an interrupt to be automatically generated on specific peripheral status conditions. For example, in a system with
3 alarm conditions, an interrupt may be generated if anyone occurs or if all three occur.
The interrupt control logic section handles all CPU interrupt protocol for nested priority
interrupt structures. The priority of any device is determined by its physical location in a
daisy chain configuration. Two lines are provided in each Pia to form this daisy chain. The
device closest to the CPU has the highest priority. Within a Pia, Port A interrupts have
higher priority than those of Port B. In the byte input, byte output or bidirectional modes,
an interrupt can be generated whenever a new byte transfer is requested by the peripheral.
In the bit control mode an interrupt can be generated when the peripheral status matches a
programmed value. The Pia provides for complete control of nested interrupts. That is,
lower priority devices may not interrupt higher priority devices that have not had their
interrupt service routine completed by the CPU. Higher priority devices may interrupt the
servicing of lower priority devices.
When an interrupt is accepted by the CPU in mode 2, the interrupting device must provide
an 8-bit interrupt vector for the CPU. This vector is used to form a pointer to a location
in the computer memory where the address of the interrupt service routine is located.
The 8-bit vector from the interrupting device forms the least significant 8 bits of the indirect
pointer while the I Register in the CPU provides the most significant 8 bits of the pointer.
Each port (A and B) has an independent interrupt vector. The least significant bit of the
vector is automatically set to a 0 within the Pia since the pointer must point to two adjacent memory locations for a complete 16-bit address.
The Pia decodes the RETI (Return from interrupt) instruction directly from the CPU data
bus so that each Pia in the system knows at all times whether it is being serviced by the
CPU interrupt service routine without any other communication with the CPU.
174
3.0 PIN DESCRIPTION
A diagram of the Z80-P10 pin configuration is shown in figure 3.0-1. This section describes
the function of each pin.
Z80-CPU Data Bus (bidirectional, tristate)
This bus is used to transfer all data and commands between the Z80CPU and the Z80-PI0. DO is the least significant bit of the bus.
B/A Sel
Port B or A Select (input, active high)
This pin defines which port will be accessed during a data transfer between the Z80-CPU and the Z80-P10. A low level on this pin selects
Port A while a high level selects Port B. Often Address bit AO from the
CPU will be used for this selection function.
C/D Sel
Control or Data Select (input, active high)
This pin defines the type of data transfer to be performed bwtween the
CPU and the PIO. A high level on this pin during a CPU write to the
PIO causes the Z80 data bus to be interpreted as a command for the
port selected by the B/ A Select line. A low level on this pin means that
the Z80 data bus is being used to transfer data between the CPU and
the PIO. Often Address bit A1 from the CPU will be used for this function.
CE
Chip Enable (input, active low)
A low level on this pin enables the PIO to accept command or data
inputs from the CPU during a write cycle or to transmit data to the
CPU during a read cycle. This signal is generally a decode of four
I/O port numbers that encompass port A and B, data and control.
System Clock(input)
The Z80-PI0 uses the standard Z80 system clock to synchronize certain
signals internally. This is a single phase clock.
Machine Cycle One Signal from CPU (input, active low)
This signal from the CPU is used as a sync pulse to control several
internal PIO operations. When M1 is active and the R D signal is active,
the Z80-CPU is fetching an instruction from memory. Conversely,
when M1 is active and IORO is active, the CPU is acknowledging an
interrupt. In addition, the M1 signal has two other functions within the
Z80-PIO.
1.
M1 synchronizes the PIO interrupt logic.
2.
When M1 occurs without an active RD or IORO signal the
PIO logic enters a reset state.
Input/Output Request from Z80-CPU (input, active low)
The IORO signal is used in conjunction with the B/A Select, C/D
Select, CE, and RD signals to transfer commands and data between
the Z80-CPU and the Z80-PIO. When CE, RD and IORO are active,
the port addressed by B/A will transfer data to the CPU ( a read operation). Conversely, when CE and IORO are active but RD is not active,
then the port addressed by B/ A will be written into from the CPU with
either data or control information as specified by the C/D Select signal.
Also, if IORO and M1 are active simultaneously, the CPU is acknowledging an interrupt and the interrupting port will automatically place
its interrupt vector on the CPU data bus if it is the highest device requesting an interrupt.
175
Read Cycle Status from the ZSO-CPU (input, active low)
If RD is active a MEMORY READ or I/O READ operation is in progress. The RD signal is used with B/A Select, C/D Select, CE and 10RQ
signals to transfer data from the ZSO-PIO to the ZSO-CPU.
lEI
Interrupt Enable In (input, active high)
This signal is used to form a priority interrupt daisy chain when more
than one interrupt driven device is being used. A high level on this pin
indicates that no other devices Cif higher priority are being serviced
by a CPU interrupt service routine.
lEO
Interrupt Enable Out (output, active high)
The I EO signal is the other signal required to form a daisy chain priority scheme. It is high only if I EI is high and the CPU is not servicing
an interrupt from this PIO. Thus this signal blocks lower priority devices from interrupting while a higher priority device is being serviced
by its CPU interrupt service routine.
Interrupt Request (output, open drain, active low)
When I NT is active the ZSO-PIO is requesting an interrupt from the
ZSO-CPU.
AO-A7
Port A Bus (bidi rectional, tri-state)
This S bit bus is used to transfer data and/or status or control information between Port A of the ZSO-PIO and a peripheral device. AO
is the least significant bit of the Port A data bus.
ASTB
Port A Strobe Pulse from Peripheral Device (input, active low)
The meaning of this signal depends on the mode of operation selected
for Port A as follows:
A RDY
176
1}
Output mode: The positive edge of this strobe is issued by the
peripheral to acknowledge the receipt of data made available by
the PIO.
2}
Input mode: The strobe is issued by the peripheral to load data
from the peripheral into the Port A input register. Data is loaded into the PIO when this signal is active.
3}
Bidirectional mode: When this signal is active, data from the
Port A output register is gated onto Port A bidirectional data
bus. The positive edge of the strobe acknowledges the receipt
of the data.
4}
Control mode: The strobe is inhibited internally.
Register A Ready (output, active high)
The meaning of this signal depends on the mode of operation selected
for Port A as follows:
1)
Output mode: This signal goes active to indicate that the Port
A output register has been loaded and the peripheral data bus
is stable and ready for transfer to the peripheral device.
2}
Input mode: This signal is active when the Port A input register
is empty and is ready to accept data from the peripheral device.
3}
Bidirectional mode: This signal is active when data is available
in Port A output register for transfer to the peripheral device.
In this mode data is not placed on the Port A data bus unless
A STB is active.
4)
Control mode: This signal is disabled and forced to a low state.
Port B Bus (bidirectional, tristate)
This 8 bit bus is used to transfer data and/or status or control information between Port B of the PIO and a peripheral device. The Port B
data bus is capable of supplying 1.5ma@ 1.5V to drive Darlington
transistors. BO is the least significant bit of the bus.
B STB
Port B Strobe Pulse from Peripheral Device (input, active low)
The meaning of this signal is similar to that of A STB with the following exception:
In the Port A bidirectional mode this signal strobes data from the
peripheral device into the Port A input register.
B RDY
Register B Ready (output, active high)
The meaning of this signal is similar to that of A Ready with the following exception:
In the Port A bidirectional mode this signal is high when the Port A
input register is empty and ready to accept data from the peripheral
device.
PIO PIN CONFIGURATION
Figure 3.0-1
15
19
14
--~
1
CPU
DATA
BUS
SEL
PIO
CONTROL
40
12
39
10
38
9
3
8
2
7
18
6
PORT B/A SEL
CONTROL/DATA
13
---~
4
CHIP ENABLE
M1
10RO
RD
+5V
GND
Z80-PIO
16
27
28
35
29
30
26
31
11
32
33
25
INT
INTERRUPT {
CONTROL
INT ENABLE IN
INT ENABLE OUT
A1
A2
A3
A4
A5
PORT A
I/O
A6
A7
ARDY
'A'S'i'B
MK3881
37
36
AO
34
BO
B1
B2
B3
B4
B5
PORT B
I/O
B6
B7
23
24
21
22
17
BRDY
BSi"B
177
178
4.0 PROGRAMMING THE PIO
4.1 RESET
The Z80-PIO automatically enters a reset state when power is applied. The reset state performs the following functions:
1)
Both port mask registers are reset to inhibit all port data bits.
2)
Port data bus lines are set to a high impedance state and the Ready "handshake"
signals are inactive (low). Mode 1 is automatically selected.
3)
The vector address registers are not reset.
4)
Both port interrupt enable flip flops are reset.
5)
Both port output registers are reset.
In addition to the automatic power on reset, the PIO can be reset by applying an M1 signal
without the presence of a RD or TORTI signal. If no RD or TORCl is detected during M1
the PIO will enter the reset state immediately after the M1 signal goes inactive. The purpose
of this reset is to allow a single external gate to generate a reset without a power down
sequence. This approach was required due to the 40 pin packaging limitation. It is recommended that in breadboard systems and final systems with a "Reset" push button that a
M1 reset be implemented for the PIO.
D
7408
CPU RESET
_ ___
- - - PIO M1
CPU M1
A software RESET is possible as described in Section 4.4, however, use of this method
during early system debug may not be desirable because of non-functional system hardware
(bus buffers or memory for example).
Once the PIO has entered the internal reset state it is held there until the PIO receives a
control word from the CPU.
4.2 LOADING THE INTERRUPT VECTOR
The PIO has been designed to operate with the Z80-CPU using the mode 2 interrupt response. This mode requires that an interrupt vector be supplied by the interrupting device.
This vector is used by the CPU to form the address for the interrupt service routine of that
port. This vector is placed on the Z80 data bus during an interrupt acknowledge cycle by
the highest priority device requesting service at that time. (Refer to the Z80-CPU Technical
Manual for details on how an interrupt is serviced by the CPU). The desired interrupt
vector is loaded into the PIO by writing a control word to the desired port of the PIO with
the following format:
07
06
05
04
03
02
01
V7
V6
V5
V4
V3
V2
V1
DO
Z:m.~ ~rn
to indicate that
data is available for the peripheral device. In most systems, the rising edge of the READY
signal can be used as a latchin~ si~nal in the peripheral device. The READY signal will
remain active until a positive edge is received from the STROBE line indicating that the
peripheral has taken the data shown in Figure 5.0-1a. If already active, READY will be
forced low 1% cycles after the falling edge of 10RQ if the port's output register is written
into. READY will return high on the first falling edge of after the rising edge of 10RQ
as shown in figure 5.0-1b. This action guarantees that READY is low while port data is
changing and that a positive edge is generated on READY whenever an Output instruction
is executed.
MODE 0 (OUTPUT)TIMING
MODE 0 (OUTPUT) TIMING
Figure 5.0-1a
Figure 5.0-1b
T2
TW
T3
T1
WR*
WR*
PORT OUTPUT
---_,,....:JL--+----4-----''-<----
18 BITS)
READY
----\--1r-----+-------
READY
STRciiIE "1" - - - - - - - - - - - - - - - -
STROBE
iiiiT"1"
INT
-
PORT OUTPUT
(8 BITS)
-c/o-. -
WR* "" RD • CE •
lORa
By connecting READY to STROBE a positive pulse with a duration of one clock period
can be created as shown in Figure 5.0-1c. The positive edge of READY/STROBE will not
generate an interrupt because the positive portion of STROBE is less than the width of M1
and as such will not generate an interrupt due to the internal logic configuration of the
PIO.
If the PIO is not in a reset status (i.e. a control mode has been selected), the output register
may be loaded before Mode 0 is selected. This allows port output lines to become active
in a user defined state. For example, assume the outputs are desired to become active in
a logic one state, the following would be the initialization sequence:
a) PIO RESET
b) Load Interrupt Vector
c) Select Mode 1 (input) (automatic due ro RESET)
d) Write FF to Data Port
e) Select Mode 0 (Outputs go to "1's")
f) Enable Interrupt if desired
183
MODE 0 (OUTPUT) TIMING - READY TIED TO STROBE
Figure 5.0-1c
T2
TW
T3
T1
T2
,p
PORT OUTPUT
(8 BITSi
-----".-l---f--t-------
''-_--'I
Ml
INT
WR*= RD·
''1'' _ _ _ _ _ _ _ _ _ _ _ _ _ __
CEo CiD· iORQ
5.2 INPUT MODE (MODE 1)
Figure 5.0-2 illustrates the timing of an input cycle. The peripheral initiates this cycle using
The STROBE line after the CPU has performed a data read. A low level on this line loads
data into the port input register and the rising edge of the STROBE line activates the
interrupt request line (INT) if the interrupt enable is set and this is the highest priority
requesting device. The next falling edge of the clock line (q,) will then reset the READY
line to an inactive state signifying that the input register is full and further loading must be
inhibited until the CPU reads the data. The CPU will in the course of its interrupt service
routine, read the data from the interrupting port, When this occurs, the positive edge from
the CPU RD signal will raise the READY line with the next low going transition of q"
indicating that new data can be loaded into the Pia,
Since RESET causes READY to go Iowa dummy Input instruction may be needed in some
systems to cause READY to go high the first time in order to start "handshaking".
MODE 1 (INPUT) TIMING
MODE 1 (INPUT) TIMING (NO STROBE INPUT)
Figure 5.0-2a
Figure 5,0-2b
RO'
PORT INPUT
----\--.3-----'r----.-------
(8 BITS)
= " 0 " _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
!NT
''1'' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MODE 1 (INPUT) TIMING (NO
Si'ROiE INPUT)
If already active, READY will be forced low one and one-half q, periods following the
falling edge of IORO during a read of a Pia port as shown in Figure 5,0-2b. If the user
strobes data into the Pia only when READY is high, the forced state of READY will
prevent input register data from changing while the CPU is reading the Pia. Ready will
go high again after the rising edge of the IORO as previously described.
184
5.3 BIDIRECTIONAL MODE (MODE 2)
This mode is merely a combination of Mode 0 and Mode 1 using all four handshake lines.
Since it requires all four lines, it is available only on Port A. When this mode is used on
Port A, Port B must be set to the Bit Control Mode. The same interrupt vector will be
returned for a Mode 3 interrupt on Port B and an input transfer interrupt during Mode 2
operation of Port A. Ambiguity is avoided if Port B is operated in a polled mode and the
Port B mask register is set to inhibit all bits.
Figure 5.0-3 illustrates the timing for this mode. It is almost identical to that previously
described for Mode 0 and Mode 1 with the Port A handshake lines used for output control
and the Port B lines used for input control. The difference between the two modes is that,
in Mode 2, data is allowed out onto the bus only when the A STROBE is low. The rising
edge of this strobe can be used to latch the data into the peripheral since the data will
remain stable until after this edge. The input portion of Mode 2 operates identically to
Mode 1. Note that both Port A and Port B must have their interrupts enabled to achieve an
interrupt driven bidirectional transfer.
PORT A, MODE 2 (BIDIRECTIONAL) TIMING
Figure 5.()'3
WR*
ARDY
ASTB
~RTA -----------------------~~~~i_--------1
DATA BUS
INT
B STB
B RDY
RD
The peripheral must not gate data onto a port data bus while A STB is active. Bus contention is avoided if the peripheral uses B STB to gate input data onto the bus. The PIO uses
the B STB low level to sample this data. The PIO has been designed witlia zero hold time
requirement for the data when latching in this mode so that this simple gating structure can
be used by the peripheral. That is, the data can be disabled from the bus immediately after
the strobe rising edge. Note that if A STB is low during a read operation of Port A (in response to a B STB interrupt) the data in the output register will be read by the CPU instead
of the correct data in the data input register. The correct data is latched in the input register
it just cannot be read by the CPU while A STB is low. If the A STB signal could go low
during a CPU Read, it should be blocked from reaching the A STB input of the PIO while
BRDY is low (the CPU read will occur while BRDY is low as the RD signal returns BRDY
high).
185
5.4 CONTROL MODE (MODE 3)
The control mode does not utilize the handshake signals and a normal port write or port
read can be executed at any time. When writing, the data wiJl be latched into output registers with the same timing as Mode O. A RDY will be forced low whenever Port A is operated in Mode 3. B RDY will be held low whenever Port B is operated in Mode 3 unless
Port A is in Mode 2. In the latter case, the state of B RDY will not be affected.
When reading the PIO, the data returned to the CPU will be composed of output register
data from those port data lines assigned as outputs and input register data from those port
data lines assigned as inputs. The input register will contain data which was present immediately prior to the falling edge of RD. See Figure 5.0-4.
MODE 3 TIMING
Figure 5.0-4a
X
~T
X
DATABUS
_____________J~---D-AT-A--W-O-R-D-1--r_I\---D-A-T-A-W-O-R-D-2
__~~____________________________
f
INT
DATA MATCH OCCURS JERE
\'--------+-4~5
~'--
_ __JJ
DATA IN
'Timing Diagram Refers to Bit Mode Read
L
}~------------------------------
DATA WORD 1 PLACED ON BUS
An interrupt will be generated if interrupts from the port are enabled and the data on the
port data lines satisfies the. logical equation defined by the 8-bit mask control registers.
Another interrupt will not be generated until a change occurs in the status of the logical
equation. A Mode 3 interrupt will be generated only if the result of a Mode 3 logical oper,
ation changes from false to true. For example, assume that the Mode 3 logical equation is
an "OR" function. An unmasked port data line becomes active and an interrupt is requested.
If a second unmasked port data line becomes active concurrently with the first, a new
interrupt will not be requested since a change in the result of the Mode 3 logical operation
has not occurred. Note that port pins defined as outputs can contribute to the logical
equation if their bit positions are unmasked.
If the result of a logical operation becomes true immediately prior to or during M1, an
interrupt will be requested after the trailing edge of MT, provided the logical equation remains true after M1 returns high.
186
Figure 5.0-4b is an example of Mode 3 interrupts. The port has been placed in Mode 3
and 0 R logic selected and signals are defined to be high. All but bits AO and A 1 are masked
out and are not monitored thereby creating a two input positive logic OR gate. In the
timing diagram AD is shown going high and creating an interrupt (INT goes low) and the
CPU responds with an Interrupt Acknowledge cycle (lNTA). The PIO port with its interrupt
pending sends in its Vector and the CPU goes off into the Interrupt Service Routine. AD is
shown going inactive either by itself or perhaps as a result of action taken in the Interrupt
Service Routine (making the logical equation false). An arrow is shown at the point in time
where the Service Routine issues the RETI instruction which clears the PIO interrupt
structure. A 1 is next shown going high making the logical equation·true and generating
another interrupt. Two important points need to be made from this example:
1)
A 1 must not go high before AO goes low or else the logical equation will not go
false - a requirement fo' A 1 to be able to generate an interrupt.
2)
In order for A1 to generate an interrupt it must be high after the RETI issued
by AD's Service Routine clears the PIO's Interrupt structure. In other words, if
A 1 were a positive pulse that occurred after AD went low (to make the equation
false) and went low before the RETI had cleared the Interrupt Structure it would
have been missed. The logic equation must become false after the I NT A for
AD's service and then must be true or go true after RETI clears the previous
interrupt for another interrupt to occur.
MODE 3 EXAMPLE
Figure 5.()'4b
EQUATION TRUE
AO
A1
INT
~~==D-INTERRUPT
INTA
187
188
6.0 INTERRUPT SERVICING
Some time after an interrupt is requested by the Pia, the CPU will send out an interrupt
acknowledge (M1 and IORQ). During this time the interrupt logic of the Pia will determine
the highest priority port which is requesting an interrupt. (This is simply the device with
its Interrupt Enable Input high and its Interrupt Enable Output low). To insure that the
daisy chain enable lines stabilize, devices are inhibited from changing their interrupt request
status when M1 is active. The highest priority device places the contents of its interrupt
vector register onto the Z80 data bus during interrupt acknowledge.
Figure 6.0-1 illustrates the timing associated with interrupt requests. During M 1 time, no
new interrupt requests can be generated. This gives time for the Int Enable signals to ripple
through up to four Pia circuits. The Pia with lEI high and lEO low during INTA will place
the 8-bit interrupt vector of the appropriate port on the data bus at this time.
If an interrupt requested by the Pia is acknowledged, the requesting port is 'under service'.
lEO of this port will remain low until a return from interrupt instruction (RETI) is executed
while lEI of the port is high. If an interrupt request is not acknowledged, lEO will be forced
high for one M1 cycle after the Pia decodes the opcode 'ED'~ This action guarantees that
the two byte RETI instruction is decoded by the proper Pia port. See Figure 6.()'2.
INTERRUPT ACKNOWLEDGE TIMING
Figure 6.0-1
LASTT
STATE
INT
lORa
}
r-------
'ORQANDiiiii
INDICATE
INTERRUPT
~NOWLEDGE
IINTA)
Ml
lEO
lEI " 1 · · - - - - - - - - - - - - - - - - - - - - - - -
RETURN FROM INTERRUPT CYCLE
Figure 6.0-2
Tl
T2
4>
\
I
\
I
\
\
I
I
DO-D7-----;~~----------;G
Ml
RD
r-----------~
lEI
lEO
lEO of higher priority PIO going high to
allow lower priority device to decode RETI.
Higher priority device is not under service.
---- ----189
DAISY CHAIN INTERRUPT SERVICING
Figure 6.0-3
HIGHEST PRIORITY PORT
1. PRIORITY INTERRUPT DAISY CHAIN BEFORE ANY INTERRUPT OCCURS.
2. PORT 2A REQUESTS AN INTERRUPT AND IS ACKNOWLEDGED.
UNDER SERVICE
SERVICE SUSPENDED
3. PORT 1B INTERRUPTS, SUSPENDS SERVICING OF PORT 2A.
SERVICE COMPLETE
~-"';"""I
SERVICE RESUMED
HI
4. PORT 1B SERVICE ROUTINE COMPLETE, "RETI" ISSUED, PORT 2A SERVICE RESUMED.
5. SECOND "RETI" INSTRUCTION ISSUED ON COMPLETION OF PORT 2A SERVICE ROUTINE.
Figure 6.0-3 illustrates a typical nested interrupt sequence that could occur with four ports
connected in the daisy chain. In this sequence Port 2A requests and is granted an interrupt.
While this port is being serviced, a higher priority port (1 B) requests and is granted an
interrupt. The service routine for the higher priority port is completed and a RETI instruction is executed to indicate to the port that its routine is complete. At this time the
service routine of the lower priority port is completed.
190
7.0 APPLICATIONS
7.1 EXTENDING THE INTERRUPT DAISY CHAIN
Without any external logic, a maximum of four ZBO-PIO devices may be daisy chained
into a priority interrupt structure. This limitation is required so that the interrupt enable
status (I EO) ripples through the entire chain between the beginning of M 1, and the beginning of fORtI during an interrupt acknowledge cycle. Since the interrupt enable status cannot
change during iiiIT, the vector address returned to the CPU is assured to be from the highest
priority device which requested an interrupt.
If more than four Pia devices must be accommodated, a "look-ahead" structure may be
used as shown in figure 7.0-1. With this technique more than thirty Pia's may be chained
together using standard TTL logic.
A METHOD OF EXTENDING THE INTERRUPT PRIORITY DAISY CHAIN
Figure 7.0-1
zao-
CPU ~~--~--~--~~--~------------~----~--~~--~----~
DATA
BUS
7.2 I/O DEVICE INTERFACE
In this example, the ZBO-PIO is connected to an I/O terminal device which communicates
over an B bit parallel bidirectional data bus as illustrated in figure 7.0-2. Mode 2 operation
(bidirectional) is selected by sending the following control word to Port A:
EXAMPLE I/O INTERFACE
Figure 7.0-2
D7
D6
D5
D4
o
x
x
D3
D2
D1
DO
~------~v~-------MODE CONTROL
191
EXAMPLE I/O INTERFACE
Fig ure 7.0·2
ARDY
ASTB
B ROY
-BSTB
-"-
I
,f"
0
S
T
B
DATA BUS
lORa
Z80·CPU
M1
MK3880
-INT
....
~
ADDRESS
,.
Z80·P10
",
MK3881
r0
R
a
B/A
C/O
CE
I'
)!'
I'
I/O
TERMINAL
-
DECODER
Next, the proper interrupt vector is loaded (refer to CPU Manual for details on the operation of the interrupt).
V5
V4
V3
V2
V1
o
Interrupts are then enabled by the rising edge of the first M1 after the interrupt mode
word is set unless that M1 defines an interrupt acknowledge cycle. If a masUoliows the
interrupt mode word, interrupts are enabled by the rising edge of the first M1 following
the setting of the mask.
Data can now be transferred between the peripheral and the CPU. The timing for this
transfer is as described in Section 5.0.
7.3 CONTROL INTERFACE
A typical control mode application is illustrated in figure 7.0-3. Suppose an industrial
process is to be monitored. The occurrence of any abnormal operating condition is to be
reported to a Z80-CPU based control system. The process control and status word has
the following format:
192
v
0
BUS
V6
0
R
c
PORT DATA BUS
ADDRESS BUS
V7
,W"
0
A
v
07
06
05
04
03
02
00
01
CONTROL MODE APPLICATION
Figure 7.0-3
PORTA
BUS
-
~SPEC.
A7
-
As
TEST
""
TURN ON PWR •
.
..,As
07·00
Z80·CPU
MK3880
Z8()'PIO
MK3881
PWR. FAILALM.
A.J
HALT
A3
TEMP. ALM.
-
A2
HTRS. ON
~
Al
PRESS. SYS.
~-
AO
B/A
C/O
'"
INDUSTRIAL
PROCESSING
SYSTEM
...,.
~
,.
PRESS. ALM.
-CE
t
A()'A15
ADDRESS
DECODER
The PIO may be used as follows. First Port A is set for Mode 3 operation by writing the
following control word to Port A.
07
06
05
04
x
X
03
02
01
00
Whenever Mode 3 is selected, the next control word sent to the port must be an I/O select
word. In this example we wish to select port data lines A5, A3, and AD as inputs and so the
following control word is written:
07
06
o
o
05
04
o
03
02
01
o
o
00
193
Next the desired interrupt vector must be loaded (refer to the CPU manual for details);
07
06
05
04
03
02
01
00
V7
V6·
V5
V4
V3
V2
V1
VO
An interrupt control word is next sent to the port:
D7
D6
D5
0
Enable
OR
Interrupts
Logic
Active
High
D4
D3
I I
D2
D1
DO
0
.,
,
Mask
Follows
Interrupt Control
The mask word following the interrupt mode word is:
D7
D6
D5
D4
o
D3
D2
D1
DO
o
Selects A5, A3 and AO to be monitored
Now, if a sensor puts a high level on line A5, A3, or AO, an interrupt request will be generated. The mask word may select any combination of inputs or outputs to cause an interrupt. For example, if the mask word above had been:
D7
o
D6
D5
o
D4
D3
D2
o
D1
DO
o
then an interrupt request would also occur if bit A7 (special Test) of the output register
was set.
Assume that the following port assignments are to be used:
EOH=
E1W
E2H=
E3H=
Port A Data
Port B Data
Port A Control
Port B Control
All port numbers are in hexadecimal notation. This particular assignment of port numbers
is convenient since AO of the address bus can be used as the Port B/A Select and A1 of the
address bus can be used as the Control/Data Select. The Chip Enable would be the decode
of CPU address bits A7 thru A2 (111000). Note that if only a few peripheral devices are
being used, a Chip Enable decode may not be required since a higher order address bit
could be used directly.
194
8.0 PROGRAMMING SUMMARY
8.1 LOAD INTERRUPT VECTOR
V6
V7
V5
V4
x
x
V3
V2
V1
o
8.2 SET MODE
M1
MO
MODE NUMBER
0
M1
MO
0
0
0
1
0
2
3
MODE
Output
Input
Bidirectional
Bit Control
When selecting Mode 3, the next word to the PIO must set the 1/0 Register:
11/0711/0611/0511/0411/0311/0211/01 1 1/00
110
= 1 Sets bit to
1/0
=
I
Input
0 Sets bit to Output
8.3 SET INTERRUPT CONTROL
USED IN MODE 3 ONLY
195
If the "mask follows" bit is high, the next control word written to the PIO must be the
mask:
MB = 0, Monitor bit
MB = 1, Mask bit from being monitored
Also, the interrupt enable flip flop of a port may be set or reset without modifying the
rest of the interrupt control word by using the following command:
x
196
x
o
o
9.0 ELECTRICAL SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RAfINGS*
Temperature Under Bias
Storage Temperature
Voltage On Any Pin With
Respect To Ground
Power Dissipation
Specified operating range.
-65°C to +150°C
-O.3V to +7V
.6W
9.2 D. C. CHARACTERISTICS
Table 9.2-1
T A = O°C to 70°C, VCC = 5 V ± 5% unless otherwise specified
Symbol
Parameter
Min
Max
Unit
VILC
Clock Input Low Voltage
-0.3
0.45
V
VIHC
Clock Input High Voltage
VIL
Input Low Voltage
VCC-·6
-0.3
VCC+·3
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VCC
0.4
VOH
Output High Voltage
ICC
III
Power Supply Current
70'
rnA
Input Leakage Current
10
ILOH
ILO L
II n
Tri-State Output Leakage Current in Float
Tri-State Output Leakage Current in Float
10
-10
Data Bus Leakage Current in Input Mode
±10
JLA
JLA
JLA
JLA
IOHD
Darlington Drive Current
2.4
Test Condition
V
V
V
IOL = 2.0mA
V
IOH = -250J,!A
VIN=OtoVCC
VOUT=2.4 to VCC
VOUT= 0.4 V
Q<;;;VIN
Unmeasured Pins
*Comment
Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
197
9.4A A.C. CHARACTERISTICS MK3880, MK3880·10, MK3880·20, Z80-PIO
T A= ooe to 70oe, Vee = +5V ± 5%, unless otherwise noted
Table 9.4-1A
MAX
UNIT
400
[1]
170
170
2000
2000
nsec
nsec
MIN
SIGNAL
SYMBOL
tc
Clock Period
tw (H)
tw (L)
t r , tf
Clock Pulse Width, Clock High
Clock Pulse Width, Clock Low
Clock Rise and Fall Times
th
Any Hold Time for Specified Set-Up Time
0
ts~CS)
Control Signal Set-up Time to Rising Edge of 'PDuring Read
280
C/D SEL
tDR(D)
tS~D)
nsec
nsec
nsec
nsec
Data Output Delay from Falling Edge of RD
Data Set-Up Time to Rising Edge of During Write or MT
430
nsec
nsec
50
Cycle
DO-D7
lEO
30
COMMENTS
or Write Cycle
CE ETC.
lEI
PARAMETER
tDI(D)
Data Output Delay from Falling Edge of 10RO During INTA
Cycle
340
nsec
tF(D)
Delay to Floating 8us (Output Buffer Disable Time)
160
nsec
ts (lEI)
lEI Set-Up Time to Falling Edge of 10RO During INTA Cycle
tDH (10)
lEO Delay Time from Rising Edge of lEI
lEO Delay Time from Falling Edge of lEI
tDL (10)
tDM (10)
10RO
tS~IR)
-Ml
ts (Ml)
C L = 50pF
[3]
nsec
140
lEO Delay from Falling Edge of Ml (Interrupt Occurring Just
Prior to M 1) See Note A.
[2]
210
nsec
190
300
nsec
nsec
10RO Set-Up Time to Rising Edge of During Read or Write
Cycle
250
nsec
iiii1 Set-Up Time to Rising Edge of During ii\iTA or M1
210
nsec
240
nsec
[5]
[5] CL = 50pF
[5]
Cycle. See Note B_
RD
ts (RD)
RD Set-Up Time to Rising Edge of During Read or
M1
Cycle
ts (PD)
tDS (PD)
AO-A7
BO-B7
tF (PD)
Port Data Set-Up Time to Rising Edge of STR01!"E" (Mode 1)
Port Data Output Delay from Falling Edge of STROBE
(Mode 2)
230
nsec
nsec
[5]
200
nsec
C L = 50pF
200
nsec
[5]
260
Delay to Floating Port Data Bus from Rising Edge of
STROBE (Mode 2)
tDI (PD)
Port Data Stable from Rising Edge of 10RO During WR
Cycle (Mode 0)
ASTB
tw (ST)
Pulse Width, STROBE
INT
tD (IT)
INT Delay Time from Rising Edge of
INT Delay Time from Data Match During Mode 3 Operation
490
nsec
tD (lT3)
650
nsec
ARDY
BRDY
tDH (RY)
Ready Response Time from Rising Edge of 10RO
t c+
460
nsec
[5]
t c+
400
nsec
C L = 50pF
[5]
tDL (RY)
STROBE
Ready Response Time from Rising Edge of STROBE
A. 2.5tc »(N-2ltDL(l0)+ tDM (10) +tS(lEI) + TTL Buffer Delay, if any
B.
M1 must be active for a minimum of 2 clock
periods to reset the PIO.
[1] tc=tw (H) +tW(L) +tr+tf
[2] Increase tDR(D) by 10 nsec for each 50pF increase in loading up to 200pF max.
[3]
Increase tDi (D) by 10 nsec for each 50pF increase in loading up to 200pF max.
[4]
For Mode 2: tw [ST):>tS(PD)
[5]
Increase these values by·2 nsec for each 10pF increase ·in loading up to 100pF max.
198
nsec
nsec
150
[4]
BSTB
9.4B A.C. CHARACTERISTICS MK3881-4, Z80A-PIO
Table 9.4-1B T A=O°C to 70°C, Vee = +5V :l; 5%, unless otherwise noted
SIGNAL
(N-2ltDL(10)+ tOM (10) + tS(1 Ell + TTL Buffer Delay, if any
B. M1 must be active for a minimum of 2 clock periods to reset the PIO.
[1]
tc ~ tw (
I
System Clock (input)
This single-phase clock is used by the CTC to synchronize certain signals internally.
M1
Machine Cycle One Signal from CPU (input, active low)
When Ml is active and the RD signal is active, the CPU is fetching an instruction from memory. When M 1
is active and the lORa signal is active, the CPU is acknowledging an interrupt, alerting the CTC to place an
Interrupt Vector on the Z80 Data Bus if it has daisy chain priority and one of its channels has requested
an interrupt.
lORa
Input/Output Request from CPU (input, active low)
The lORa signal is used in conjunction with the CE and RD signals to transfer data and Channel Control
Words between the Z80-CPU and the CTC. During a CTC Write Cycle, lORa and CE must be true and
RD false. The CTC does not receive a specific write signal, instead generating its own internally from the
inverse of a valid RD signal. In a CTC Read Cycle, lORa, CE and RD must be active to place the contents
of the Down Counter on the Z80 Data Bus. If lORa and M 1 are both true, the CPU is acknowledging an
interrupt request, and the highest-priority interrupting channel will place its Interrupt Vector on the Z80
Data Bus.
213
3.0 CTC PIN DESCRIPTION (CONT'D)
RD
Read Cycle Status from the CPU (input, active low)
The RD signal is used in conjunction with the IORO and CE signals to transfer data and Channel Control
Words between the Z80-CPU and the CTC. During a CTC Write Cycle, IORO and CE must be true and
RD false. The CTC does not receive a specific write signal, instead generating its own internally from the
inverse of a valid RD signal. In a CTC Read Cycle, IORO, CE and RD must be active to place the contents
of the Down Counter on the Z80 Data Bus.
lEI
Interrupt Enable In (input, active high)
This signal is used to help form a system-wide interrupt daisy chain which establishes priorities when more
than one peripheral device in the system has interrupting capability. A high level on this pin indicates that
no other interrupting devices of higher priority in the daisy chain are being serviced by the Z80-CPU.
lEO
Interrupt Enable Out (output, active high)
The I EO signal, in conjunction with I E I, is used to form a system-wide interrupt priority daisy chain. I EO
is high only if I E I is high and the CPU is not servicing an interrupt from any CTC channel. Thus this signal blocks lower priority devices from interrupting while a higher priority interrupting device is being
serviced by the CPU.
Interrupt Request (output, open drain, active low)
This signal goes true when any CTC channel which has been programmed to enable interrupts has a zerocount condition in its Down Counter.
Reset (input, active low)
This signal stops all channels from counting and resets channel interrupt enable bits in all control registers,
thereby disabling CTC-generated interrupts. The ZC/TO and INT outputs go to their inactive states, lEO
reflects I EI, and the CTC's data bus output drivers go to the high impedance state.
CLK/TRG3-CLK/TRGO
External Clock/Timer Trigger (input, user-selectable active high or low)
There are four CLK/TRG pins, corresponding to the four independent CTC channels. In the Counter
Mode, every active edge on this pin decrements the Down Counter. In the Timer Mode, an active edge on
this pin initiates the timing function. The user may select the active edge to be either rising or falling.
ZC/T02-ZC/TOO
Zero Count!Timeout (output, active high)
There are three ZC/TO pins, corresponding to CTC channels 2 through O. (Due to package pin limita:
tions channel 3 has no ZC/TO pin.) In either Counter Mode or Timer Mode, when the Down Counter
decrements to zero an active high going pulse appears at this pin.
214
Z80-CTC PIN CONFIGURATION
Figure 3.0-1
DO
23
25
Cl T/TRGO
ZC/TO O
D1
D2
CPU
DATA BUS
D3
ClK/TRG 1
D4
ZC!T01
D5
D6
CHANNEL
SIGNALS
ClK!TRG2
ZC/T02
CSO
MK3882
Z80-CTC
CS1
CTC
CONTROL
CHIP
ENABLE
M1
IORQ
RD
MK3882-4
Z80A-CTC
+5V
GND
ENA~~:
INTERRUPT {INT
CONTROL
IN 11
INT ENABLE
OUT
215
216
4.0 CTC OPERATING MODES
At power-on, the Z80-CTC state is undefined. Asserting RESET puts the CTC in a known state. Before
any channel can begin counting or timing, a Channel Control Word and a time constant data word must be
written to the appropriate registers of that channel. Further, if any channel has been programmed to
enable interrupts, an Interrupt Vector word must be written to the CTC's Interrupt Control logic. (For
further details, refer to section 5.0: "CTC Programming. ") When the CPU has written all of these words to
the CTC, all active channels will be programmed for immediate operation in either the Counter Mode or
the Timer Mode.
4.1
CTC COUNTER MODE
In this mode the CTC counts edges of the ClK/TRG input. The Counter Mode is programmed for a
channel when its Channel Control Word is written with bit 6 set. The Channel's External Clock (ClK/
TRG) input is monitored for a series of triggering edges; after each, in synchronization with the next rising edge of (the System Clock), the Down Counter (which was initialized with the time constant data
word at the start of any sequence of down-counting) is decremented. Although there is no set-up time
requirement between the triggering edge of the External Clock and the rising edge of , (Clock), the
Down Counter will not be decremented until the following pulse. (See the parameter ts(CK) in section
8.3: "A.C. Characteristics.") A channels's External Clock input is pre-programmed by bit 4 of the Channel Control Word to trigger the decrementing sequence with either a high or a low going edge.
In any of Channels 0, 1, or 2, when the Down Counter is successively decremented from the original time
constant until finally it reaches zero, the Zero Count (ZCITO) output pin for that channel will be pulsed
active (high). (However, due to package pin limitations, channel 3 does not have this pin and so may
only be used in applications where this output pulse is not required.) Further, if the channel has been so
pre-programmed by bit 7 of the Channel Control Word, an interrupt request sequence will be generated.
(For more details, see section 7.0: "CTC Interrupt Servicing.")
As the above sequence is proceeding, the zero count condition also results in the automatic reload of the
Down Counter with the original time constant data word in the Time Constant Register. There is no
interruption in the sequence of continued down-counting. If the Time Constant Register is written to
with a new time constant data word while the Down Counter is decrementing, the present count will be
completed before the new time constant will be loaded into the Down Counter.
CHANNEL - COUNTER MODE
Figure 4.1-0
CHANNEL
CONTROL
REGISTER
AND LOGIC
(8 BITS)
.
TIME
CONSTANT
REGISTER
(8 BITS)
INTERNAL BUS
DOWN
COUNTER
(8 BITS)
ZERO COUNT/
TIMEOUT
EXTERNAL CLOCK/TIMER TRIGGER
217
4.2
CTC TIMER MODE
In this mode the CTC generates timing intervals that are an integer value of the system clock period. The
Timer Mode is programmed for a channel when its Channel Control Word is written with bit 6 reset. The
channel then may be used to measure intervals of time based on the System Clock period. The System
Clock is fed through two successive counters, the Prescaler and the Down Counter. Depending on the
pre-programmed bit 5 in the Channel Control Word, the Prescaler divides the System Clock by a factor of
either 16 or 256. The output of the Prescaler is then used as a clock to decrement the Down Counter,
which may be pre-programmed with any time constant integer between 1 and 256. As in the Counter
Mode, the time constant is automatically reloaded into the Down Counter at each zero-count condition,
and counting continues. Also at zero-count, the channel's Time Out (ZC/TO) output (which is the output of the Down Counter) is pulsed, resulting in a uniform pulse train of precise period given by the product.
tc * P * TC
where tc is the System Clock period, P is the Prescaler factor of 16 or 256 and TC is the pre-programmed time constant.
Bit 3 of the Channel Control Word is pre-programmed to select whether timing will be automatically
initiated, or whether it will be initiated with a triggering edge at the channel's Timer Trigger (CLK/TRG)
input. If bit 3 is reset the timer automatically begins operation at the start of the CPU cycle following
the I/O Write machine cycle that loads the time constant data word to the channel. If bit 3 is set the
timer begins operation on the second succeeding rising edge of after the Timer Trigger edge following
the loading of the time constant data word. If no time constant data word is to follow then the timer
begins operation on the second succeeding rising edge of after the Timer Trigger edge following the
control word write cycle. Bit 4 of the Channel Control Word is pre-programmed to select whether the
Timer Trigger will be sensitive to a rising or falling edge. Although there is no set-up requirement between the active edge of the Timer Trigger and the next rising edge of <1>. If the Timer Trigger edge
occurs closer than a specified minimum set-up time to the rising edge of <1>, the Down Counter will not
begin decrementing until the following rising edge of <1>. (See parameter ts(TR) in section 8.3: "A.C.
Characteristics". )
If bit 7 in the Channel Control Word is set, the zero-count condition in the Down Counter, besides
causing a pulse at the channel's Time Out pin, will be used to initiate an interrupt request sequence, (For
more details, see section 7.0: "CTC Interrupt Servicing.")
CHANNEL - TIMER MODE
Figure 4.2-0
CHANNEL
CONTROL
REGISTER
AND LOGIC
(8 BITS)
TIME
CONSTANT
REGISTER
(8 BITS)
INTERNAL BUS
, and the output of the Prescaler in
turn clocks the Down Counter. The output of the Down Counter (the channel's ZC/TO output) is a
uniform pulse train of period given by the product.
tc * P * TC
where tc is the period of System Clock <1>, P is the Prescaler factor of 16 or 256, and TC is the time
constant data word.
Sit 5 = 1
(Defined for Timer Mode only.) Prescaler factor is 256.
Bit 5 = 0
(Defined for Timer Mode only.) Prescaler factor is 16.
DO
RESET
USED IN TIMER
MODE ONLY
Bit 4 = 1
TI ME R MODE - positive edge trigger starts timer operation.
COUNTE R MODE - positive edge decrements the down counter.
Bit 4 = 0
TIMER MODE - negative edge trigger starts timer operation.
COUNTER MODE - negative edge decrements the down counter.
220
5.1
LOADING THE CHANNEL CONTROL REGISTER (CONT'D)
Bit 3 = 1
Timer Mode Only - External trigger is valid for starting timer operation after rising edge of T2 of the
machine cycle following the one that loads the time constant. The Prescaler is decremented 2 clock
cycles later if the setup time is met, otherwise 3 clock cycles. Once timer has been started it will free run
at the rate determined by the Time Constant register.
Bit 3 = 0
Timer Mode Only - Timer begins operation on the rising edge of T2 of the machine cycle following the
one that loads the time constant.
Bit 2 = 1
The time constant data word for the Time Constant Register will be the next word written to this channel. If an updated Channel Control Word and time constant data word are written to a channel while it
is already in operation, the Down Counter will continue decrementing to zero before the new time constant is loaded into it.
Bit 2 = 0
No time constant data word for the Time Constant Register should be expected to follow. To program
bit 2 to this state implies that this Channel Control Word is intended to update the status of a channel already in operation, since a channel will not operate without a correctly programmed data word in the
Time Constant Register, and a set bit 2 in this Channel Control Word provides the only way of writing to
the Time Constant Register.
Bit 1 = 1
Reset channel. Channel stops counting or timing. This is not a stored condition. Upon writing into this
bit a reset pulse discontinues current channel operation, however, none of the bits in the channel control
register are changed. If both bit 2 = 1 and bit 1 = 1 the channel will resume operation upon loading a
time constant.
Bit 1 = 0
Channel continues current operation.
5.2
DISABLING THE CTC'S INTERRUPT STRUCTURE
If an external Asynchronous interrupt could occur while the processor is writing the disable word to the
CTC (01 H); a system problem may occur. If interrupts are enabled in the processor it is possible that the
Asynchronous interrupt will occur while the processor is writing the disable word to the CTC. The CTC
will generate an I NT and the CPU will acknowledge it, however, by this time, the CTC will have received
the disable word and de-activated its interrupt structure. The result is that the CTC will not send in its
interrupt vector during the interrupt acknowledge cycle because it is disabled and the CPU will fetch an
erroneous vector resulting in a program fault. The cure for this problem is to disable interrupts within
the CPU with the D I instruction just before the CTC is disabled and then re-enable interrupts with the E I
instruction. This action causes the CPU to ignore any interrupts produced by the CTC while it is being
disabled. The code sequence would be:
LD A, 01 H
DI
OUT (CTC), A
EI
; DISABLE CPU
; DISABLE CTC
; ENABLE CPU
221
II
S.3
LOADING THE TIME CONSTANT REGISTER
A channel may not begin operation in either Timer Mode or Counter Mode unless a time constant data
word is written into the Time Constant Register by the CPU. This data word will be expected on the
next I/O Write to this channel following the I/O Write of the Channel Control Word, provided that bit 2
of the Channel Control Word is set. The time constant data word may be an integer value in the range 1256. If all eight bits in this word are zero, it is interpreted as 256. If a time constant data word is loaded
to a channel already in operation, the Down Counter will continue decrementing to zero before the new
time constant is loaded from the Time Constant Register to the Down Counter.
TIME CONSTANT REGISTER
TCs
DS
DO
TCS
TCO
MSB
CHANNEL BLOCK DIAGRAM
LSB
Figure 5.3-0
CHANNEL
CONTROL
REGISTER
AND LOGIC
(8 BITS)
TIME
CONSTANT
REGISTER
(8 BITS)
INTERNAL BUS
ZERO COUNT/
DOWN
COUNTER
(8 BITS)
PRESCALER
(8 BITS)
<\>
I
EXTERNAL CLOCK/TIMER TRIGGER
S.4
TIMEOUT
LOADING THE INTERRUPT VECTOR REGISTER
The Z80-CTC has been designed to operate with the Z80-CPU programmed for mode 2 interrupt response. Under the requirements of this mode, when a CTC channel requests an interrupt and is acknowledged, a 16-bit pointer must be formed to obtain a corresponding interrupt service routine starting address from a table in memory. The upper 8 bits of this pointer are provided by the CPU's I register, and
the lower 8 bits of the pointer are provided by the CTC in the form of an Interrupt Vector unique to the
particular channel that requested the interrupt. (For further details, see section 7.0: "CTC Interrupt
Serv ic i ng".)
MODE 2 INTERRUPT OPERATION
Desired starting address pointed to by:
INTERRUPT
SERVICE
ROUTINE
STARTING
ADDRESS
TABLE
222
<
LbwORDER }
HIGH ORDER
5.4 LOADING THE INTERRUPT VECTOR REGISTER (Cont'd)
The high order 5 bits of this Interrupt Vector must be written to the CTC in advance as part of the initial
programming sequence. To do so, the CPU must write to the I/O port address corresponding to the CTC
channel 0, just as it would if a Channel Control Word were being written to that channel, except that bit
o of the word being written must contain a O. (As explained above in section 5.1, if bit 0 of a word
written to a channel were set to 1, the word would be interpreted as a Channel Control Word, so a 0 in
bit 0 signals the CTC to load the incoming word into the Interrupt Vector Register.) Bits 1 and 2, however are not used when loading this vector. At the time when the interrupting channel must place the
Interrupt Vector on the Z80 Data Bus, the Interrupt Control Logic of the CTC automatically supplies a
binary code in bits 1 and 2 indentifying which of the four CTC channels is to be serviced.
INTERRUPT VECTOR REGISTER
I
,
D7
D6
D5
D4
D3
V7
V6
V5
V4
V3
V
SUPPLIED BY USER
,
I
D2
D1
DO
X
X
0
I
0
0
1
1
,
I
o CHANNEL
1 CHANNEL
o CHANNEL
0
1
2
1 CHANNEL 3
V
(Highest Priority)
(Lowest Priority)
I
AUTOMATICALLY INSERTED BY ZaO-CTC
223
224
6.0
CTC TIMING
This section illustrates the timing relationships of the relevant CTC pins for the following types of operation: writing a word to the CTC, reading a word from the CTC, counting, and timing. Elsewhere in this
manual may be found timing diagrams relating to interrupt servicing (section 7.0) and an A.C. Timing
Diagram which quantitatively specifies the timing relationships (section a.4).
6.1
CTC WRITE CYCLE
Figure 6.1-0 illustrates the timing associated with the CTC Write Cycle. This sequence is applicable to
loading either a Channel Control Word, an Interrupt Vector, or a time constant data word.
zao-cpu
I n the sequence shown, during clock cycle T 1, the
prepares for the Write Cycle with a false
(high) signal at CTC input pin RD (Read). Since the CTC has no separate Write signal input, it generates
initiates the Write
its own internally form the false RD input. Later, during clock cycle T2, the
Cycle with true (low) signals at CTC input pins 10RO (I/O Request) and CE (Chip Enable). (Note: MT
must be false to distinguish the cycle form an interrupt acknowledge.) Also at this time a 2-bit binary
code appears at CTC inputs CS1 and CSO (Channel Select 1 and 0), specifying which of the four CTC
Data Bus_ Now everything is
channels is being written to, and the word being written appears on the
ready for the word to be latched into the appropriate CTC internal register in synchronization with the
rising edge beginning clock cycle T3. No additional wait states are allowed_
zao-cpu
zao
CTC WRITE CYCLE
Figure 6.1-0
CSO-1, CE
________
~)(~____C_H_A_N_N__E_L_A_D_D_R_E_S_S____~)(~_________
\----_----'1
M1
DATA
"1"
__________~X~_____
IN
____
~)(~___ _
'AUTOMATICALLY INSERTED BY ZBO-CPU
6.2
CTC READ CYCLE
Figure 6.2-0 illustrates the timing associated with the CTC Read Cycle. This sequence is used any time
the CPU reads the current contents of the Down Counter. During clock cycle T2, the
initiates
the Read Cycle with true signals at input pins RD (Read), 10RO (I/O Request), and CE (Chip Enable).
also at this time a 2-bit binary code appears at CTC inputs CS1 and CSO (Channel Select 1 and 0), specifying which of the four CTC channels is being read from. (Note: M1 must be false to distinguish the
cycle form an interrupt acknowledge.) On the rising edge of the cycle T3 the valid contents of the Down
Counter as of the rising edge of cycle T2 will be available on the
Data Bus. No additional wait states
are allowed.
zao-cpu
zao
225
CTC READ CYCLE
Figure 6.2·0
CSO-1. CE ________
~)(~_____C_H_A_N_N_E_l_A_D_D__R_ES_S______J)(~_________
lORa
\I--_ _-,---J/
RD
\'--_ _----JI
"1" - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
M1
DATA
-----------«
OUT
)~---
*AUTOMATICALL Y INSERTED BY Z80·CPU
6.3
CTC COUNTING AND TIMING
Figure 6.3-0 illustrates the timing diagram for the CTC Counting and Timing Modes.
CTC COUNTING AND TIMING
Figure 6.3·0
226
ClK
__....JI
INTERNAL
COUNTER
________..JI
ZC/TO
_ _-.II
TRG
_--....J/
INTERNAL
TIMER
___---II
\~--
\~---JI
ZERO COUNT
\~___________
\ ________
\"-------START TIMING
6.3 CTC COUNTING AND TIMING (Cont'd)
In the Counter Mode, the edge (rising edge is active in this example) form the external hardware connected to pin C LK/TRG decrements the Down Counter in synchronization with the System Clock ----229
7.2
RETURN FROM INTERRUPT CYCLE
Figure 7.2-0 illustrates the timing associated with the RETI Instruction. This instruction is used at the
end of an interrupt service routine to initialize the daisy chain enable lines for proper control of nested
priority interrupt handling. The CTC decodes the two-byte RETI code internally and determines whether it is intended for a channel being serviced.
When several Z80 peripheral chips are in the daisy chain lEI will become active on the chip currently
under service when an EDH opcode is decoded. If the following opcode is 4DH, the peripheral being serviced will be re-initialized and its I EO will become active. Additional wait states are allowed.
RETURN FROM INTERRUPT CYCLE
Figure 7.2-0
Ml
\
/
RD
~
!
00- 0 7
lEI
\
0
I
--------1
lEO
7.3
/
\
@)
--------
/
/
DAISY CHAIN INTERRUPT SERVICING
Figure 7.3-0 illustrates a typical nested interrupt sequence which may occur in the CTC. In this example,
channel 2 interrupts and is granted service. While this channel is being serviced, higher priority channell
interrupts and is granted service. The service routine for the higher priority channel is completed, and a
RETI instruction (see section 7.2 for further details) is executed to signal the channel that its routine is
complete. At this time, the service routine of the lower priority channel 2 is resumed and completed.
DAISY CHAIN INTERRUPT SERVICING
Figure 7.3-0
230
7.4
USING THE CTC AS AN INTERRUPT CONTROLLER
All of the Z80 family parts contain circuitry for prioritizing interrupts and supplying the vector to the
CPU. However, in many Z80 based systems interrupts must be processed from devices which do not contain this interrupt circuitry. To handle this requirement the MK3882 CTC can be used, providing prioritized, independently vectored, maskable, edge selectable, count programmable external interrupt inputs.
The MK3882 parts may be cascaded, expanding the system to as many as 256 interrupt inputs.
Each MK3882 contains 4 channels with counter inputs able to interrupt upon one or more (up to 256)
edge transitions. The active transition may be programmed to be positive or negative. Each of the 4
channels has a programmable vector which is used in powerful Z80 mode 2 interrupt processing. When
an interrupt is processed the vector is combined with the CPU I register to determine where the interrupt
service routine start address is located. Additionally, priority resolution is handled within the MK3882
when more than one interrupt request is made simultaneously. When more than one MK3882 is used,
the prioritizing is done, with the lEI/lEO chain resolving inter-chip priorities. Each channel can be independently "masked" by disabling that channel's local interrupt.
When programming the MK3882 to handle an input as a general purpose interrupt line, the channel is put
in the counter mode, with the count set to 1, the active edge specified and the vector is loaded. When
the programmed edge occurs a mode 2 interrupt will be generated by the CTC and the Z80-CPU can
vector directly to the service routine for the non-Z80 peripheral device. Note that after the interrupt,
the CTC down counter is automatically reloaded with a count of one and the eTC begins looking for
another active edge. The second interrupt will not be passed on to the CPU until after the RETI of the
first interrupts service routine.
CTC AS AN INTERRUPT CONTROLLER
Figure 7.4-0
HV
TO
CPU
DATA
HIGHEST
,u,
PRIORITY
18
A,
19 CSI
i'OiiQ
iii
iiD
iNT
10
INTERRUPT
0
INTERRUPT
!I
INTERftUPT
,
eso
Ao
TRG I
iORo
14iiii
"
TRG2 21
'liD
TRGS 2.0
To
.Z80-CPU
LOWEST
PRIORITY
TO AOOITIONAL
MIC 3882'S
231
232
8.0
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .......................................... Specified Operating Range
Storage Temperature .................................................... _65° C to +150° C
Voltage on Any Pin with Respect to Ground .................................... -0.3V to +7V
Power Dissipation ................................................................ 0.8V
8.1 D. C. CHARACTERISTICS
TA = 0° C to 70° C, Vcc = 5V ± 5% unless otherwise specified
SYMBOL
VILC
VIHC
VIL
VIH
VOL
VOH
ICC
III
ILOH
'LOL
IOHD
PARAMETER
Clock Input Low Voltage
Clock Input High Voltage (1)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Power Supply Current
Input Leakage Current
Tri-State Output Leakage Current In Float
Tri-State Output Leakage Current In Float
Darlington Drive Current
MIN
-0.3
MAX
.45
VCc-·6 VCC +.3
-0.3
0.8
2.0
VCC
0.4
2.4
120
10
10
-10
-1.5
UNIT TEST CONDITION
V
V
V
V
V
V
mA
IOL=2mA
IOH = -250J.lA
TC = 400 nsec**
J.lA
J.lA
JlA
mA
VIN = 0 to VCC
VOUT = 2.4 to VCC
VOUT = O.4V
VOH=1.5V
* *T C = 250 nsec for M K 3882-4
8.2 CAPACITANCE
TA=25°C,f=1 MHz
SYMBOL
PARAMETER
MAX
Cq,
CIN
Clock Capacitance
Input Capacitance
COUT
Output Capacitance
20
5
10
UNIT TEST CONDITION
pF
Unmeasured Pins
pF
Returned to Ground
pF
'COMMENT
Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
233
8.3 A.C. CHARACTERISTICS MK 3882, MK 3882-10, Z80-CTC
TA
= 0°
C to 70° C, Vcc
Signal
Symbol
'I>
tc
tW('I>H)
tW('I>L)
tr, tf
tH
ts'I>(CS)
CS,
cr, etc.
tDR(D)
tS"'(D)
tD 1(0)
DO-D7
tF(D)
lEI
tS(lEI)
lEO
tDH(IO)
tDL(IO)
tDM(IO)
10RO
= +5
V ± 5%, unless otherwise noted
Parameter
Clock Period
Clock Pulse Width, Clock High
Clock Pulse Width, Clock Low
Clock Rise and Fall Times
Any Hold Time for Specified Setup Time
Control Signal Setup Time to Rising
Ed(le of 'I> Durin9_ Read or Write Cycle
Data Output Delay from Rising Edge of
RD During Read Cycle
Data Setup Time to Rising Edge of 'I>
During Write or M 1 Cycle
Data Output Delay from Falling Edge
of 10 RO During I NT A Cycle
Delay to Floating Bus (Output Buffer
Disable Timel
lEI Setup Time to Falling Edge of 10RO
During I NT A Cycle
lEO Delay Time from Rising Edge of lEI
I EO Delay Time from Falling Edge of I E I
lEO Delay from Falling Edge of M1
( Interrupt Occurring just Prior to M 1)
10RO Setup Time to Rising Edge of ,',
During Read or Write Cycle
tS'I'(M1) 1'i7r1 Setup Time to R ising Edge of '\'
During I NT A or M 1 Cycle
tS'I'(RD) RD Setup Time to Rising Edge of 'I>
During Read or M 1 Cycle
tDCK( IT) I NT Delay Time from Rising Edge of
CLK!TRG
I NT Delay Time from Rising Edge of
for Immediate Count
tS(TR)
Trigger Setup Time to R ising Edge of 'I)
for Enabling of Prescaler on Following
Rising Edge of 'I)
tS"'(IR)
1'i7r1
RD
fi\JT
Min
Max
Unit
400
170
170
(1 )
2000
2000
30
ns
ns
ns
ns
ns
ns
480
ns
0
160
Comments
(2)
ns
50
340
ns
230
ns
(2)
ns
200
220
190
300
ns
ns
ns
250
ns
210
ns
240
ns
(3)
(3)
(3)
2tc(
CS,
cr, etc
DO-D7
lEI
lEO
IURTI
Ml
RD
INT
Parameter
Min
Clock Period
250
Clock Pulse Width, Clock High
105
Clock Pulse Width, Clock Low
105
Clock Rise and Fall Times
Any Hold Time for Specified Setup Time 0
Control Signal Setup Time to Rising Edge 145
of During Read or Write Cycle
Data Output Delay from Falling Edge of
tDR(D)
RD During Read Cycle
tS(D)
Data Setup Time to Rising Edge of
50
During Write or Ml Cycle
Data Output Delay form Falling Edge
tD I(D)
of IOAG During INTA Cycle
Delay to Floating Bus (Output Buffer
tF(D)
Disable Time)
tS(IEI)
lEI Setup Time to Falling Edge of IORQ 140
During INTA Cycle
I EO Delay Time from Rising Edge of I E I
tDH(IO)
lEO Delay Time from Falling Edge of lEI
tDL(10)
I EO Delay from Falling Edge ofMl
tDM(10)
(Interrupt Occurring just Prior to M 1)
tS(IR)
IORU Setup Time to Rising Edge of
115
During Read or Write Cycle
tS(Ml) Ml Setup Time to Rising Edge of
90
During I NTA or M 1 Cycle
tS( RD) liD Setup Time to Rising Edge of
115
During Read or M 1 Cycle
tDCK(IT) INT Delay Time from Rising Edge of
CLK/TRG
tD( IT)
INT Delay Time from Rising Edge of
tC(CK)
Clock Period
2tC(
130
for Immediate Count
tS(TR)
Trigger Setup Time to Rising Edge of 130
for enabling of Prescaler on Following
Rising Edge of
tc
tW(H)
tW(L)
tr, tf
tH
tS(CS)
Max
Unit Comments
(1 )
2000
2000
30
ns
ns
ns
ns
ns
ns
380
ns
(2)
ns
160
ns
110
ns
(2)
ns
160
130
190
ns
ns
ns
(3)
(3)
(3)
ns
ns
ns
2tC(, ZC/TO High
ZC/TO Delay Time from Rising Edge
of <1>, ZC/TO Low
NOTES:
(1.)
(2.1
(3.1
(4.1
tc = tw(WI + tw( during T3
and is then held into the Write cycle. During an I/O
Write, data is held from the previous Read cycle until
the end of the Write cycle.
NOTE:
If WAIT is low during the negative transition of TW*, then TW* will be extended
another T-cycle and WATT will again be
sampled. The duration of a peripheral
transaction cycle may thus be indefinitely
extended.
Figure 3
CE
~---'I------IORO
I'-----...JI·- - - - - - RD
DATA
\
~---'
-----{L~_~OU~T~_+r-----
STD MEMORY TIMING
This timing is exactly the same as used by the Z80CPU to access system main memory, either in a Read
or Write operation. The DMA will default to this timing after a power-on reset, or when a Reset or Reset
Timing command is written to it; and unless otherwise programmed, will used this timing during all
Transfer or Search operations involving system main
memory. During the memory Read portion of a transfer cycle, data is latched in the DMA on the negative
edge of during T3 and held into the following Write
cycle. During the memory Write portion of a transfer
cycle, data is held form the previous Read cycle and
released at the end of the present cycle.
The DMA is normally programmed for a
NOTE:
3 T-cycle duration in memory transactions. But WATT is sampled during the negative transistion of T2, and if it is low,
T2 will be extended another T-cycle, after
which WAIT will again be sampled. The
duration of a memory transaction cycle
may thus be indefinitely extended.
STD MEMORY TIMING
I
Figure 4
T,
I
STD PERIPHERAL TIMING
Figure 5
'I·
ADD-~
'---~------~----~4J
\
,/
\
!I
HELD UNTIL
READ DATA-
$TARTOF
READ
----------~-_fll- NeXT
~-+-- f~:~~~E~
t'I}---
WRITE DATA- _ _ _"_E_LD_'_RO_M_p_RE_v_'O_us_R_EA_D+_ _ _ _
WAIT
T,
\~_-+-_-+,!I
IORQ
-----------rr,------ --_ _ _ _ _ _ _ _ _ _ -1
'-- _ _ _ _ _ _ _ _
·LATCHED BY DMA ON BUS DURING A TRANSFER
VARIABLE CYCLE
I}---
ADD
1\
I
1\
If
~II
WR
---- - - - j r.---- ---,
' - - - -- ------_ _ -1
READ DATA-
HELD UNTIL
START OF
NEXT READ
DURING A
TRANSFER
WRITe DATA"
HElD FROM PREVIOUS READ
I
I
"LATCHED BY DMA ON BUS DURING A TRANSFER
}---
The Variable feature of the DMA allows the user to
program the DMA's memory or peripheral transaction
timing to values different than given above in the
standard default diagrams. This permits the designer
to tailor his timing to the particular requirements of
his system components, and maximizes the data
transfer rate while eliminating external signal conditioning logic. Cycle length can be one to four T-cycles
(more if WAIT is used). Signal timing can be varied as
shown. During a transfer, data will be latched by the
DMA on the clock edge causing the rising edge of RD
and will be held on the data lines until the end of the
following Write cycle.
(See Timing Control Byte, page 9.)
243
DMA BUS RELEASE WITH 'READY'
FOR BURST AND CONTINUOUS MODE
DMA TIMING WAVEFORMS (CONT'D)
VARIABLE CYCLE
Figure 6
~PROGRAMMED FOR' CVCLES
VARIABLE LENGTH
T,
I
T2
I
I
T3
T,
,',
X
AO - A15
X
r
iORo
I
MREQ
\
Ri5
\
FA
\
/
,r I
,r /
The DMA will relinquish the bus after RDY has gone
inactive (Burst mode) or after an End of Block or a
Match is found (Continuous mode). With RDY inactive, the DMA in Continuous mode is inactive but
maintains control of the bus (BUSRQ low) until the
cycle is resumed when RDY goes active. See Figure 9.
BUS RELEASE WITH 'READY'
FOR BURST AND CONTINOUS MODE
Figure 9
,',
)--,---!--I_ _
WAiT (MEM)
r
I
/
8USRQ
--rr--;---t--------L.. _ _ _ _ _ _ _ _ _
__ _
_ _ _ _ _ _ _ _ _ _ ..J
~
_______ _
DMA BUS REQUEST AND ACCEPTANCE FOR
BYTE-AT-A-TIME, BURST,
AND CONTINUOUS MODE
Ready is sampled on every rising edge of <1>. When it is
found to be active, the following rising edge of generates BUSRQ. After receiving BUSRQ the CPU will
grant a BUSAK which will be connected to BAI
either directly or through the Bus Acknowledge Daisy
Chain. When a low is detected on BAI (sampled on
every rising edge of <1», the next rising edge of will
start an active DMA cycle. See Figure 7.
BUS REQUEST AND ACCEPTANCE FOR BYTEAT-A-TIME, BURST, AND CONTINOUS MODE
I
}
CONTINUOUS
;:--MODE
----~I;--DM-A---;1--'
oMA ACTlVE ........ ..--'NACTIVE -----...j_OMA ACTIVE
- _ ....J
_____
WAiTUo,-----------r h , - - - - - - - - -
~/
I P'"_L::~~~~_M_O.:'~___
DMA BUS
MODE
RELEASE
FOR
BYTE-AT-A-TIME
In the Byte mode the DMA will release BUSRQ on
the rising edge of prior to the end of each Read cycle in Search Only or each Write cycle in a Transfer,
regardless of the state of RDY. The next bus request
will come after both BUSRQ and BAI have returned
high. See Figure 10.
BUS RELEASE FOR BYTE-AT-A-TIME MODE
Figure 10
RDV~A~CT~_ _ _ _~).~)---------
DMA ACTIVE .......
I__ OMA INACTIVE
DMA BUS RELEASE WITH MATCH FOR
BURST OR CONTINUOUS MODES
1
DMA INACTlVE ...... r+-- DMA ACTIVE
DMA BUS RELEASE AT END OF BLOCK
FOR BURST OR CONTINUOUS MODE
Timing for End of Block and DMA not programmed
for Auto-restart. See Figure 8.
BUS RELEASE AT END OF BLOCK
Figure 8",
nnf
BUSRQ
ROY
INACT
__
..,-_-\~)
~
LAST BYTE
!
"'--IN BlOCK-------!
1
DMA'ACTlVE-+-I-+-DMA INACTIVE
244
Figure 11
,', JLr4nnJu-u---u-u-uL
ACT
RDV
When a Match is found and the DMA is programmed
to stop on Compare, the DMA performs an operation
on the next byte and then releases bus. See Figure 11.
BUS RELEASE WITH MATCH FOR
BURST OR CONTINOUS MODES
BUSRQ
-----I»
"
Ir---
,--~\)
I
\~
INACT
, ___________ _
.
/
~ ~ BYTE N+l __1
MATCH FOUND IN
1- - -
BYTE N
THIS BYTe
DMA ACTIVE - . ..... OMA INACTIVE
READING FROM THE DMA INTERNAL
REGISTERS
Seven registers are available in the DMA for reading.
They are: 8 bits of the status register, the upper and
lower 8 bits of the block length register, and two port
address registers.
These are available to be read sequentially: status,
B LK Lower, B LK Upper, Port A Address lower, Port
A Address Upper, Port B Address lower, Port B Address upper. An internal pointer points to each register in turn as each READ is accomplished. If a register is not to be read, it may be excluded by programming a 0 in the Read Byte. The internal pointer
will skip any register not programmed with a 1 in the
Read Byte. After a Reset or a Load, Reset RD must
be given to set the internal pointer pointing to the
first register programmed to be read by the Read
Byte. After RD Status, the pointer will be pointing to
the status register regardless of the mask and the next
read will be from the status register. The following
read will be from the register pointed to before R D
Status.
The following diagrams and charts give the function
of each bit in the six different command bytes. Two
of these are defined as being from Group 1, and are
termed command bytes lA and lB. These Group 1
commands contain the most basic DMA set-up information. The other four are categorized as Group 2,
and are termed commands 2A, 2B, 2C, and 2D.
Group 2 words specify more detailed set-up information.
COMMAND BYTE 1A
Figure 12
-.Specifies Group 1
o
Co
Function
o
Not allowed. (Command Byte 1 B)
o
o
Search Only.
Search and Transfer.
Previous sections of this specification have indicated
the various functions and modes of the DMA. The
diagrams and charts below will show how the DMA is
programmed to select among these functions and
modes and to adapt itself to the requirements of the
user system. More detailed programming information
is available in the Z80-DMA Technical Manual.
The command bytes contain information to be loaded into the DMA's control and other registers and/or
information to alter the state of the chip, such as an
Enable Interrupt command. The command structure
is designed so that certain bits in some commands can
be set to alert the DMA to expect the next byte
written to it to be for a particular internal register.
II
Transfer Only.
PROGRAMMING THE DMA
The Z80-DMA chip may be in an "enable"state, in
which it can gain control of the system buses and
direct the transfer of data between its ports, or in a
"disable" state, when it cannot gain control of the
bus. Program commands can be written to it in either
state, but writing a command to it automatically puts
it in the disable state, which is maintained until an enable command is issued to the DMA. The CPU must
program it in advance of any data search or transfer
by addressing it as an I/O port and sending it a sequence of 8 bit command bytes via the system data
bus using Output instructions. When the DMA is
powered up or reset by any means, the DMA will
automatically be placed into a disable state, in which
it can initiate neither bus requests nor data transfers
nor interrupts.
Byte lA
cannot be 00
Port A is read from, Port B is written to
(unless the Search Only Mode has been
selected, in which case Port B is never
addressed).
Port B is read from, Port A is written to
(unless the Search Only Mode has been
selected, in which case Port A is never
addressed).
COMMAND BYTE 1B
Figure 13
-..--
Specifies Group 1
Specifies B'/te 1 B
Address for this port increments after
each byte.
Address for this port decrements after
each byte.
D3 = 1
This port addresses an I/O peripheral.
D3= 0
This port addresses main memory.
=1
This word programs Port A.
D2= 0
This word programs Port B.
D2
245
COMMAND BYTE 2D (CONT'D)
COMMAND BYTE 2A
Figure 14
Hex
--.-Specifies Byte 2A
Specifies Group 2
COMMAND BYTE 2B
Figure 15
--.-Specifies Group 2
M1
Specifies Byte 2B
MO
o
o
Mode
Byte
Continuous
Burst
Transparent
o
1
o
1
1
1
C3
C7
CB
CF
D3
AB
AF
A3
87
83
BB
A7
BF
B3
J3L
8B
f4
f3
f2
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1__
1
0
0
0
0
1
0
0
0
0
0
1
0
2f--
CIN
COUT
Clock Capacitance
I nput Capacitance
Output Capacitance
35
5
10
pF
pF
pF
Unmeasured Pins
Returned to Ground
TEST
250llA
249
A.C. TIMING DIAGRAMS
PRELIMINARY
Z80 and Z80A as a Peripheral Device (Inactive State)
Timing measurements are made at the following voltages, unless otherwise specified:
CLOCK
OUTPUT
INPUT
FLOAT
-I
--------------------~
.....-tD1(D) .....
------------+------ tS(lR)i--
lEI
lEO
-
INT
CONDITION
250
tDL(lO)
-
"1"
"0"
4.2V
2.0V
2.0V
!1V
O.8V
O.8V
O.8V
+O.5V
PRELIMINARY
A.C. CHARACTERISTICS MK3883 Z80-0MA
Z80-DMA as a Peripheral Device (Inactive State).
T A =0° C to 70° C, Vcc = +5V± 5%," Unless Otherwise Noted
SIGNAL
SYMBOL
PARAMETER
MIN
MAX
UNIT
(I)
tc
tw(I)H)
tw(I)L)
tr, f
Clock
Clock
Clock
Clock
400
170
170
(1)
2000
2000
30
nsec
nsec
nsec
nsec
tH
Any Hold Time for Specified Setup Time
0
nsec
tS(I)(CS)
Control Signal Setup Time to Rising Edge
of (I) During Write Cycle
280
nsec
tDR(D)
Data Output Delay from Falling Edge of
RD
Data Setup Time to Rising Edge of 'I)
During Write orM1 Cycle
Data Output Delay from Falling Edge of
IORO During INTA Cycle
Delay to Floating Bus (Output Buffer
Disable Time)
CE
tS'I)(D)
DO-7
tDI(D)
tF(D)
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Times
lEI
tS(IEI)
lEI Setup Time to Falling Edge of IORO
During I NT A Cycle
lEO
tDH(IO)
tDL(IO)
tDM(IO)
I EO Delay Time from R ising Edge of I E I
lEO Delay Time from Falling Edge of lEI
lEO Delay from Falling Edge of M1
(I nterrupt Occurring Just Prior to Ml) See
Note A.
IORO
tS'I)(IR)
IORO Setup Time to Rising Edge of 'I)
During Write Cycle
M1
tS(I)(M1)
M 1 Setup Time to R ising Edge of IN·21 tDLiIOI + tDMllOI + tS(lEl1 + TTL Buffer Delay. If any
11 I te
t w l'l+1 I +twl'l'Ll +tr +tf
(2) Increase tOR{Ol by 10 nsec for each 50pF Increase In loadmg up to 200pF max.
(3) Increase to(O) by 10 nsec for each 50pF increase
In
loading up to 200pF max.
251
PRELIMINARY
A.C. CHARACTERISTICS MK3883·4 Z80A·DMA
Z80A DMA as a Peripheral Device (Inactive State)
T A = O°C to 70°C, Vcc = +5V±5%, Unless Otherwise Noted
SIGNAL
'I>
CE
SYMBOL
PARAMETER
MIN
MAX
tc
tw('I'H)
tw('I>L)
t r, f
Clock
Clock
Clock
Clock
250
10,5
105
( 1)
nsec
2000. fl·sec
2000 /nsec
nsec
30
tH
Any Hold Time for Specified Setup Time
0
nsec
tS'I'(CS)
Control Signal Setup Time to Rising Edge
of 'I> During Write Cycle
145
nsec
tDR(D)
Data Output Delay from Falling Edge of
RD
Data Setup Time to Rising Edge of 'I'
During Write or MT Cycle
Data Output Delay from Falling Edge
of IORO During INTA Cycle
Delay to Floating Bus (Output Buffer
Disable Time)
tS'I>(D)
DO-7
tDI(D)
tF(D)
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Times
380
UNIT
nsec
250
nsec
110
nsec
tS(IEI)
lEI Setup Time to Falling Edge of IORO
During I NT A Cycle
lEO
tDH(IO)
tDL(IO)
tDM(IO)
lEO Delay Time from Rising Edge of lEI
lEO Delay Time from Falling Edge of lEI
lEO Delay from Falling Edge of M.L
(I nterrupt Occurri ng Just Prior to M 1)
See Note A.
IORO
tS'I'(IR)
IORO Setup Time to Rising Edge of 'I'
During Write Cycle
115
nsec
M1
tS'I'(M1)
M1 Setup Time to Rising Edge of 'I'
During I NT A or MT Cycle. See Note B.
90
nsec
RD
tS'I'(RD)
RD Setup Time to Rising Edge of 'I'
During M 1 Cycle
115
nsec
INT
tD(IT)
INT Delay Time from Condition Causing
INT. INT generated only when DMA is
inactive.
BAO
tDH(BO)
tDL(BO)
BAO Delay from Rising Edge of BAI
BAO Delay from Falling Edge of BAI
NOTES:
111 Ie
2.5I c
> IN-21 IDLIIOI +lS(iEII + TTL Buffer Delay, If any
Iwl(IR)
tDH¢(IR)
tDL(RD)
10RO
10RO
IORO
10RO
10RO
10RO
10RO
10RO
RO
RO
RO
RO
-RD
RO
RO
RD
Delay
Low
Delay
Low
Delay
High
Delay
High
Delay
Low
Delay
Low
Delay
High
Delay
High
lS0
90
nsec
nsec
nsec
Data Output Delay
Delay to Float Ourinq Write Cycle
Data Setup Time to Risinq Edqe of Clock 35
Durinq Read When Risinq Edge Ends RO
Data Setup Time to Falling Edge of Clock 50
During Read When Falling Edge Ends RD
Data Stable Prior to WR (Memory Cycle) (5)
tOlD)
tF(O)
tS'I)(O)
007
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
nSf~C
nsec
nsec
CL
200pF
nsec
nsec
nsec
nsec
(6)
(7)
from Rising Edge of Clock,
75
nsec
from Falling Edge of Clock,
SO
nsec
from Rising Edge of Clock,
80
nsec
from Falling Edge of Clock,
80
nsec
from Rising Edge of Clock,
75
nsec
from Falling Edge of Clock,
95
nsec
from Rising Edge of Clock,
75
nsec
from Falling Edge of Clock,
80
nsec
D
0
0
CL =50pF
CL =50pF
255
II
A.C. CHARACTERISTICS MK3880-4 Z80A-DMA (CONT'D)
SIGNAL
SYMBOL
PARAMETER
tDL(WR)
WR Delay from Rising Edge of Clock,
WR Low
Wli Delay from Falling Edge of Clock,
WR Low
Wli Delay from Falling Edge of Clock,
WR High
WR Delay from Rising Edge of Clock,
iiiTR High
Pulse Width, iiiTR Low
tDL(WR)
WR
tDH(l>(WR)
tDH(WR)
tw(WRL)
PRELIMINARY
MIN
MAX
UNIT
60
nsec
80
nsec
80
nsec
80
nsec
(10)
nsec
WAIT
ts(WT)
WAIT Setup Time to Falling Edge of
Clock
70
nsec
BUSRO
tD(BO)
BUSRQ Delay Time from Rising Edge
of Clock
100
nsec
tF(C)
Delay to Float (MREO, IORO, RD and
WR)
80
NOTES:
A. Data should be enable onto the DMA data bus when RD is active.
B. All control signals are internally synchronized, so they may be totally asynchronous with respect to the clock.
C. Output ~elay vs. Loaded Capacitance
TA = 70 C Vee +5V ± 5%
(1) "'CL +100pF (A1>-A15 and
D. During Standard CPU Timing.
;=
0
1.
2.
3.
4.
5.
6.
7.
8.
Control Signals), add 30 nsec to timing shown.
tacm tw(H) +tf -30 Variable 1 Cycle.
10.tw(WR) tc -40Std. CPU Timing
tw(WR) tw( HI +tw(
--- ---
lacm
',~
R5
___r -
WR
iC5"R6
Rri
"~--~
WR
WAil'
BuSi'iQ
---~',
-------------------------------------------------------------~
257
'PACKAGE DESCRIPTION
40 Pin Dual-In-Line Ceramic Package
PACKAGE DESCRIPTION
40-Pin Dual-In-Line Plastic Package
ORDERING INFORMATION
PART NO.
PACKAGE TYPE
MAX CLOCK FREQ.
TEMPERATURE RANGE
MK3883N Z80-DMA
MK3883P Z80-DMA
MK3883N-4 Z80A-DMA
MK3883P-4 Z80A-DMA
PLASTIC
CERAMIC
PLASTIC
CERAMIC
2.5
2.5
4.0
4.0
O°C to
O°C to
O°C to
O°C to
258
MHz
MHz
MHz
MHz
70°C
70°C
70°C
70°C
MOSTEI(.
zaD MICROCOMPUTER DEVICES
Technical Manual
II
MI(3884/5/7
SERIAL I/O
CONTROLLER
259
260
TABLE OF CONTENTS
Page
1.0
Introduction .................................................... 1
1.1
Structure .......................................................1
1.2
Features ....................................................... 1
2.0
Architecture ....................................................3
2.2
Note on Bonding Option ...........................................5
3.0
Operation ......................................................7
3.1
Asynchronous Modes .............................................7
3.2
Synchronous Modes ..............................................S
4.0
SIO Programming ............................................... 15
4.1
General .......................................................15
4.2
Write Registers ................................................. 15
4.3
Read Registers .................................................. 17
4.4
Register Description ............................................. 17
4.5
ZSO SIO Command Structure ......................................26
4.6
Programming Example ...........................................27
5.0
Timing Waveforms .............................................. .29
6.0
Daisy Chain Interrupt Servicing .....................................31
7.0
Absolute Maximum Ratings .......................................33
7.1
D.C. Characteristics ..............................................33
7.2
Capacitance ....................................................33
7.3
Load Circuit for Output ..........................................34
7.4
A.C. Timing Diagram· Preliminary ..................................35
7.5
A.C. Characteristics - Preliminary ...................................37
S.O
Package Configuration ............................................39
9.0
Ordering Information ........................................... .41
261
262
LIST OF TABLES & FIGURES
Figure
Page
TITLE
1.0
SIO Block Diagram ...............................................2
2.0
Channel Block Diagram ............................................3
2.1
2.2
SIO PIN OUT ...................................................3
Bonding Option ..................................................5
3.0
Asynchronous Format.............................................7
3.1
Synchronous Formats .............................................9
3.2
Transmission SDLC/HDLC Message Format ........................... 12
3.3
Reception SDLC/HDLC Message Format ............................. 13
I
Write Registers ................................................. 15
Read Registers .................................................. 17
4.5
Z80-S10 Command Structure ......................................26
Write Cycle ....................................................29
Read Cycle ....................................................29
Interrupt Acknowledge Cycle ......................................30
Return from Interrupt Cycle .......................................30
Daisy Chain Interrupt Servicing .....................................31
7.1
D.C. Characteristics ..............................................33
7.2
Capacitance ....................................................33
7.3
Load Circuit for Output ..........................................34
7.4
A.C. Timing Diagram - Preliminary ..................................35
7.5
A.C. Characteristics - Preliminary ...................................37
8.0
Package Configuration ............................................39
263
264
1.0 INTRODUCTION
The MOSTEK Z80 product line is a complete set of microcomputer components, development systems and support software. The Z80 microcomputer component set includes all
of the circuits necessary to build high-performance microcomputer systems with virtually
no other logic and a minimum number of low cost standard memory elements.
The Z80-S10 (Serial Input/Output) circuit is a programmable, dual-channel device which
provides formatting of data for serial data communication. It is capable of handling asynch ronous, synchronous and synchronous bit oriented protocols such as I BM BiSync, H DLC,
SO LC and virtually any other serial protocol. It can generate CRC codes in any synchronous
mode and can be programmed by the CPU for any traditional asynchronous format.
1.1 STRUCTURE
ON-channel Silicon Gate Depletion Load Technology
o Forty Pin DIP
o Single 5 volt power supply
o Single phase 5 volt clock
o Two Full Duplex channels
1.2 FEATURES
o
o
o
o
o
o
o
o
o
o
Two independent full duplex channels
Data rates - 0 to 550K bits/second
Receiver data registers quadruply buffered; transmitter double buffered.
Asynchronous operation
- 5, 6, 7 or 8 bits/character
- 1, 1% or 2 stop bits
- Even, odd or no parity
- x 1, x 16, x32 and x64 clock modes
- Break generation and detection
- Parity, Overrun and Framing error detection
Binary Synchronous operation
- Internal or external character synchronization
- One or two Sync characters in separate registers
- Automatic Sync character insertion
- CRC generation and checking
HDLC or IBM SDLC operation
- Automatic Zero insertion and deletion
- Automatic Flag insertion
- Address field recognition
- I-Field residue hand I ing
- Valid receive messages protected from overrun
- CRC generation and checking
Eight modem control inputs and outputs
Both CRC-16 and CRC-CCITT are implemented
Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external logic.
All inputs and outputs fully TTL compatible.
265
SIO BLOCK DIAGRAM
Figure 1.0
~
INTERNAL
CONTROL
LOGIC
+5V GND
CHANNEL A
SERIAL
DATA
CHANNEL
CLOCK
SYNC
~'
""'""
WAIT/ROY
. As a Ready function, it is actively driven high and occurs from the positive edge of <1>.
WAIT/READY ENABL (07)
The Wait/Ready pin will remain high (Ready mode) or floating (Wait mode) until this bit
is programmed to one.
WRITE REGISTER 2 (Channel B only)
Write Register 2 is the interrupt vector register and it exists only in Channel B. V4-V7
and Vo are always returned exactly as written. V ,-V3 are returned as written if the "Status
Affects Vector", Control bit is "0".
WRITE REGISTER 3
Write register 3 contains control bits for some of the receiver logic.
D7
D6
D5
D4
D3
D2
D1
DO
RCVR
Bits!
CharO
RCVR
Bits!
Char 1
Enter
Hunt
Mode
RECVR
CRC
Enable
Address
Auto
Enables
Sync Char
Load
Inhibit
Receiver
Enable
Search
Mode
RECEIVER ENABLE (DO)
A "1" programmed here allows receiver operations to begin.
284
SYNC CHAR LOAD INHIBIT (01)
Sync characters preceding a message will not be loaded into the receiver buffers if this
option is selected. The CRC calculation is not stopped by the sync character being stripped.
ADDRESS SEARCH MODE (02)
If the SOLC mode is selected, this mode will cause messages with addresses not matching
the programmed address or the global (11111111) address to be rejected, i.e., no interrupts
occur unless an address match occurs if this mode is selected.
RECVR CRC ENABLE (03)
Receiver CRC Enable. If this bit is set, a calculation of CRC begins (or restarts) at the start
of the last character transferred from the receive register to the buffer stack regardless of
the number of characters in the stack.
ENTER HUNT MODE (04)
If character synchronization is lost for any reason, or if in SDLC mode, it is determined
that the contents of an incoming message are not needed, Hunt mode may be reentered by
writing a "1" to this bit.
AUTO ENABLES (05)
If this mode is selected, the DCD and CTS inputs are receiver and transmitter enables,
respectively. If the mode is not selected, DCD and CTS are only inputs to their corresponding bits in Read Register O.
RCVR BITS/CHAR 1 (06), RCVR BITS/CHAR 0 (07)
These bits together determine the number of serial receive bits that will be assembled to
form a character.
These bits may be changed during the time that a character is being assembled, if it is done
before the number of bits currently programmed is reached.
D7
D6
Receiver BitslCharacter 1
0
0
1
1
Receiver BitslCharacter 0
0
1
0
1
BitslCharacter
S
7
6
8
WRITE REGISTER 4
Write Register 4 contains control bits affecting both the receiver and transmitter.
D7
D6
DS
D4
D3
D2
Dl
DO
Clock
Rate
1
Clock
Rate
0
Sync
Modes
1
Sync
Modes
0
Stop
Stop
Bits
0
Parity
Evenl
Parity
Bits
1
Odd
PARITY (DO)
If this bit is set, an additional bit position (in addition to those specified in the bits/character control) is added to transmitted data and is expected in receive data.
285
PARITY EVEN/ODD (0,)
If parity is specified, this bit determines whether it is sent or checked as even or odd parity.
STOP BITS 0 (02), STOP BITS' (03)
These bits determine the number of stop bits added to each asynchronous character sent.
The receiver always checks for one stop bit.
The special (00) mode is used to signify that a synchronous mode is to be selected.
03
Stop Bits 1
O2
Stop Bits
a
a
a
1
1
a
a
Sync Modes
1 Stop Bit Per Character
111, Stop Bits Per Character
2 Stop Bits Per Character
1
1
SYNC MODES 0 (04), SYNC MODES (05)
These select the various options for character synchronization:
Sync Mode 1
Sync Mode
a
a
a
a
8~bit
1
16·bit programmed sync
1
1
a
SDLC Mode (01111110 sync pattern)
External Sync Mode
1
programmed sync
CLOCK RATE 0 (06), CLOCK RATE 1 (07)
Specifies the multiplier between clock and data rates. For synchronous modes X1 must be
specified. Any rate may be specified for the asynchronous modes. The same multiplier is
used for both the receiver and transmitter.
In all modes, the system clock (q,) must be at least 5 X the data rate. If the X1 clock rate
is selected, bit synchronization must be accomplished externally.
Clock Rate 1
Clock Rate
a
a
a
1
1
a
a
1
1
Data
Data
Data
Data
Rate
Rate
Rate
Rate
X1
X16
X32
X64
~
~
~
~
Clock
Clock
Clock
Clock
Rate
Rate
Rate
Rate
WRITE REGISTER 5
Write Register 5 contains mostly control bits affecting the transmitter.
07
06
05
DTR
Transmit
Bits/
CharO
Transmit
Bits/
Char 1
04
Send
Break
03
Transmit
Enable
O2
SDLC/
CRC16
01
DO
RTS
Transmit
CRC
Enable
TRANSMIT CRC ENABLE (DO)
This bit determines whether CRC is to be calculated on any particular send character.
If set at the time of loading the character from the transmit buffer to the transmit shift
register, CRC will be calculated on the character. CRC will not be automatically sent unless
this bit is set when the transmitter is completely empty.
286
Request to Send is the control bit for the RTS pin. When the RTS bit is set, the RTS
goes active (low). When the bit is reset (to 0), the RTS pin will go inactive (high) only
after the transmitter is empty.
SOlC/CRC16 (02)
This bit selects the CRC code used by both the transmitter and the receiver. When reset, the
SDLC polynomial X 16 + X12 + X5 1 is used. (In SDLC mode, the registers are preset to
"all 1's" and a special check sequence is used.) When set, the CRC-16 polynomial X16 +
X15 + X2 + 1 is used, and the CRC registers are reset to "all O's".
+
TRANSMIT ENABLE (03)
Data will not be transmitted and the TxD pin will be held marking (high) until this bit is
set. Data or Sync characters in the process of being transmitted will be completely sent if
the transmit enable bit is reset after transmission has started. CRC characters will not be
completely sent if the transmitter is disabled during the sending of a CRC character.
SEND BREAK (04)
When set, this bit directly forces the TxD pin spacing, regardless of any data being transmitted. When reset, the TxD pin is released.
TRANSMIT BITS/CHAR 0 (05), TRANSMIT BITS/CHAR 1 (06)
These bits together control the number of bits that will be sent from each byte transferred
to the transmit buffer.
05
06
Transmit Bits!
Characte 1
0
0
1
1
~~:~!~~r ~tsl
Bits/Character
5 or less
7
6
8
0
1
0
1
Bits to be sent are assumed to be right justified. Low order bits (DO) are sent first. The
"5 or less" mode allows transmission of 1 to 5 bits in a character.
06
05
04
03
O2
01
DO
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
Sends one bit
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
Sends three bits
Sends four bits
0
0
0
0
0
0
0
0
Sends five bits
07
Sends two bits
O=OATA BIT
OTR (07)
Data Terminal Ready is the control bit for the DTR pin. When set, DTR is active (low).
When reset (0) DTR is inactive (high).
287
----~----------
WRITE REGISTER 6
This register contains the first 8 bits of a BiSync sequence. It must be programmed with
the check address (if used) in SDLC mode, and must contain the sync character in the 8-bit
sync mode. It is not used in the external sync mode.
07
06
Os
04
02
01
DO
SYN7
SYN6
SYNS
SYN4
SYN3
SYN2
SYN1
SYNO
A07
A06
ADS
A04
A03
A02
A01
ADO
03
MONO OR BI SYNC MODE
SDLC MODE
WRITE REGISTER 7
This register contains the second byte of a 16-bit synchronization sequence, or the 8-bit
sync character. For SDLC mode, it must be programmed to 01111110 . It is not used in
the external sync mode.
07
06
Os
SYN1S
SYN14
SYN13
0
1
1
03
O2
01
DO
SYN11
SYN10
SYN9
SYN8
1
1
1
0
04
SYN12
1
BI SYNC MODE
SOLC MODE
READ REGISTER 0
This is the register read if the register pointers are (000).
07
06
Break/
Abort
Tx
UNOERRUN/
EOM
Os
04
CTS
Sync/
Hunt
03
O2
01
Do
DCO
Transmit
Buffer
Empty
Interrupt
Pending
Receive
Character
Available
RECEIVE CHARACTER AVAILABLE (DO)
This bit is set when at least one character is available in the receive buffers.
INTERRUPT PENDING (D,) (Channel A only)
Any interrupt condition present in the entire SIO will cause this bit to be set, but it is
present only in Channel A and is always in Channel B.
a
TRANSMIT BUFFER EMPTY (D2)
The Transmit Buffer Empty bit is set whenever the transmit buffer is empty, except when
a CRC character is ~eing sent in a synchronous mode.
Shows the state of the DCD pin at the time of the last change of any of the five External/
Status bits. (DCD, CTS, SYNC/HUNT, BREAK/ABORT or Tx UNDERRUN/EOM.) To get
the current state of the DCD pin, this bit must be read immediately following a RESET
EXTERNAL/STATUS INTERRUPT command. (Command 2.)
SYNC/HUNT (D4)
In asynchronous modes, this bit is similar to the DCD and the CTS bits, except that it
shows the state of the SYNC pin. I n synchronous modes, this bit is reset when character
synchronization is achieved and is set by writing the ENTER HUNT MODE bit. Unlike the
external pin, the bit remains reset until set by the ENTER HUNT MODE bit.
CTS (D5)
This bit is similar to the DCD bit, except that it shows the state of the CTS pin.
288
BREAK/ABORT (07)
In asynchronous modes, this bit is set when a "break" is detected. After the inputs have
been re-enabled (by the RESET EXTERNAL/STATUS INTERRUPTS command, Command
2), the bit will be reset when the break stops. If EXTERNAL STATUS interrupts are
enabled, these changes of state cause interrupts. I n SO LC mode, this bit is set by the detection of an abort sequence (7 or more 1's). It is not used in other synchronous modes.
TRANSMIT UNDER RUN/END OF MESSAGE (EOM)
In synchronous modes, CRC is automatically sent when the transmitter is empty for the
first time in a message. Interrupts are generated (if enabled) when this bit is set, but not
when reset. If this bit is set and the TRANSMIT BUFFER EMPTY bit is not set, then the
CRC character is being sent. TRANSMIT BUFFER EMPTY and Tx UNOERRUN/EOM
both set imply that SYNC characters are being sent.
READ REGISTER'
This register is read when the register pointers are (001). The pointers automatically reset
to (000) after a read from this register.
D7
D6
D5
End Of
Frame
(SDLC)
CRC!
Framing
Receiver
Overrun
Error
Error
D4
D3
D2
Dl
DO
Parity
Error
Residue
Code 2
Residue
Code 1
Residue
Code 0
All Sent
ALL SENT (DO)
In asynchronous modes, this bit is set when all characters have completely cleared the
transmitter. Transitions of this bit do not cause interrupts. It is always set in synchronous
modes.
RESIDUE CODE
a (0,) -
RESIDUE CODE 2 (03)
These three bits indicate the. length of the l-fie·1d in the.SOLC mode in those cases where
the I-field is not an integral multiple of the character length used. Only on the transfer on
which the END OF FRAME (SOLC) bit ·is set do these codes have meaning.
For a receiver setting of eight bits per character, the codes signify the following:
Residue Code 2
1
0
1
0
1
0
1
0
Residue Code 1
Residue Code 0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
I-Field
In Previous
Byte
0
0
0
0
0
0
1
2
I-Field
In Second
Previous Byte
3
4
5
6
7
B
8
8
I-field bits are right-justified in all cases.
If a receive character length different from eight bits is used for the I-field, a table similar
to the above may be constructed for each different character length. For no residue, i.e.,
the last character boundary coincides with the boundary of the I-Field and CRC Field,
the Residue Code will always be:
Residue Code 2
o
Residue Code 1
Residue Code 0
289
PARITY ERROR (04)
When'parity is enabled, this bit is set for those characters whose parity does not match
the sense programmed. The bit is latched so that once an error occurs, the bit remains set
until the ERROR RESET COMMAND, Command 6, is given.
RECEIVER OVERRUN ERROR (05)
This indicates that more than four characters have been received without a read from the
CPU. Only the character that has been written over is flagged with this error, but when this
character is read, the error condition is latched until reset by the ERROR RESET
COMMAND, Command 6. If STATUS AFFECTS VECTOR bit is enabled, the character
that has been overrun will interrupt with the SPECIAL RECEIVE CONDITION vector.
CRC/FRAMING ERROR (06)
If a framing error occurs (in asynchronous modes), this bit is set (and not latched) only
for the character on which it occurred. Detection of a framing error adds an additional
Y:. bit time to the character time so that the framing error will not also be interpreted as
a new start bit. In synchronous modes, this bit indicates the result of comparing the CRC
checker to the appropriate check value.
END OF FRAME (SOLC) (07)
In SDLC mode, this bit indicates that a valid ending flag has been received and that the
CRC error and residue codes are valid.
READ REGISTER 2 (Channel B Only)
This register contains the interrupt vector as written into Write Register 2 if the STATUS
AFFECTS VECTOR control bit is not set. If that control bit is set, it contains the interrupt
vector as it would be returned were an interrupt from the SIO to be processed exactly
at the time of the read. If no interrupts are pending, V3 = 0, V2 = 1, V 1 = 1 and other
bits are as programmed. The register may be read only through Channel B.
Os
°7
v7
Vs
°5
°4
v5
v4
v3
0,
°2
°3
*
*
V2
v,
°0
"
Vo
*V,. V2. and V3 are varible if STATUS AFFECTS VECTOR mode is enabled
4.5 Z80-810 COMMAND STRUCTURE
OATABITS
101
rl
1
1
0
CRC 1
1
1
0
CRC 1
CM02
CM01
CMOO
CRCO
CM02
CM01
CMOO
1
0
1
Break/Abort
Tx
UNOERRUNI
EOM
1
1
0
CRC1
CRCO
1
1
290
CRCO
1
0
0
Wait/ROY EN
1
End of Frame
SOLC
0
0
0
0
TxBuffer
EMPTY
INT Pending
(CH A Onlyl
RxChar Avail
CTS
SYNC/HUNT
OCO
CM02
CM01
CMOO
0
0
1
RxINTmod~O
Status Effects V
(CH BOnlyl
TxlNT EN
EXT INT EN
Res. Code 2
Res. Code 1
Res. Code 0
All Sent
WaitFN/ROYFN Wait/ROYonRIT RxlNTMode 1
eRe FrameError
0
0
RxOVRN Error
Parity Error
4.5 Z80-S10 COMMAND STRUCTURE (Cont'd.)
CHB-ONLY
n
~
8
1
1
0
CRC 1
CRCO
CMD 2
CMD 1
CMDO
0
1
0
1
1
0
V7
V6
V5
V4
V3
V2
V1
VO
1
0
1
V7
V6
V5
V4
V3
V2
V1
VO
1
1
0
CRC 1
CRC 0
CMD 2
CMD1
CMDO
0
1
1
1
1
0
RxBits/Char 1
RxBits/Char 0
Auto Enables
EntetHuntMode
RxCRC EN
1
1
0
CRC 1
CRC 0
CMD 2
CMD 1
CMDO
AddrssSearchMd
1
SyncChar
RxEN
LD INH
0
0
-
Sync Mode 1
Sync Mode 0
Stop Bits 1
Stop Bits 0
Parity Even/Odd
Parity
CRC 0
CMD 2
CMO 1
CMO 0
1
0
1
OTR
TxBits/Char 1
TxBits/Char 0
Send BREAK
TxEN
SOLC/CRC 16
RTS
TxCRC EN
0
CRC 1
CRC 0
CMO 2
CM01
CMOO
1
1
0
1
0
SYNC/SOLC 7
SYNC/SOLC 6
SYNC/SOLC 5
SYNC/SOLC 4
SYNC/SOLC 3
SYNC/SOLe 2
SYNC/SOLC 1
SYNC/SDLC 0
rl1
1
0
CRC 1
CRCO
CM02
CMO 1
CMOO
1
1
1
1
1
0
SYNC/SOLC 10
SYNC/SOLC 9
SYNC/SOLC8
1
1
0
Clock Rate 1
~1
1
0
CRC 1
1
1
0
1
1
1
8
Clock Rate 0
SYNC/SOLC 15 SYNC/SOLC 14 SYNC/SOLC 13 SYNC/SOLC 12 SYNC/SOLC 11
4.6 PROGRAMMING EXAMPLE
A typical start-up routine following an internal or external reset, would be as follows:
B/A
C/O
RO
07
D6
D5
D4
D3
D2
0
0
0
0
0
0
D1
1
V2
1
V1
Vo
0
0
V7
V6
V5
V4
V3
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DO
0
0
0
0
0
0
0
0
0
1
COMMENTS
Pointer set to Register 2B
Interrupt Vector loaded
~ointer set to Write Register 4B
Even parity, 1 stop bit, X16 clock asynchronous mode selected
Pointer set to Write Register 5B
7 bits/tr?nsmit character, transmitter
Pointer set to Write Register 3B
7 bits/receive character, OCD and CTS
enable Receiver and Transmitter, Receiver
enabled
Pointer set to Register 1 B
Interrupt on every character, status affects
Vector external/status interrupts enabled
Channel B is now setup to send and receive asynchronous data.
Setup for Channel A follows:
a
a
0
0
a
a
a
1
a
a
a
a
1
0
a
a
a
0
Pointer set to Write Register 4A
SDLC mode and XI clock selected, no parity
291
-------------
II
Programming Example
B/A C/D
RD
0
D7
0
D6
1
D5
0
D4
0
D3
0
D2
1
D1
1
0
0
AD7
1
AD6
0
AD5
0
AD4
0
AD3
0
AD2
1
AD1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
D
D
0
D
D
0
COMMENTS
Pointer set to Write Register 6A, Reset
Receive CRC Checker
ADO SD LC message address entered
1
Pointer set to Write Register 7A, Reset
mit CRC generator
0
SDLC Flag entered
Pointer set to Register 1 A
Interrupt every character, status affects
vector, external/status interrupts enabled
Pointer set, to Write Register 5A, Reset
External/Status Interrupts
0
SDLC CRC Code selected, 8 bits/transmit
character, CRC and transmitter enabled
Pointer set to Write Register 3A
8 bits/receive character, DCD and CTS
enable receiver and transmitter, receiver is
enabled, SIO searches for programmed
address.
DO
0
Channel A is now programmed for SDLC transfers.
0
0
0
292
0
0
D
D
D
D
D
D
D
D
0
D
D
0
D
D
0
Address byte to be sent by Ch. A
Address or control byte to be sent by Ch. A
Reset Tx UNDERRUN/EOM
pointer to register 0, so CRC can be auto·
matically sent at end of message.
5.0 TIMING WAVEFORMS
WRITE CYCLE
Illustrated here is the timing associated with a data or control byte being written into the
SIO. Z80 output instructions satisfy this timing.
T1
T2
TW
T3
T1
/
/
\
Ml
\
IORO
RD
-:.;
lEI
\:
(
DATA·
VECTOR )
RETURN FROM INTERRUPT CYCLE
If a Z80 peripheral device has no interrupt pending and is not under service, then its I EO=
I E I. If it has an interrupt under service (i.e. it has already interrupted and received an
interrupt acknowledge) then its I EO is always low, inhibiting lower priority chips from
interrupting. If it has an interrupt pending which has not yet been acknowledged, I EO
will be low unless an "ED" is decoded as the first byte of a two byte opcode. In this case,
lEO will go high until the next opcode byte is decoded, whereupon it will again go low.
If the second byte of the opcode was a "40" then the opcode was an RETI instruction.
After an "ED" opcode is decoded, only the peripheral device which has interrupted and is
currently under service will have its I E I high and its I EO low. This device is the highest
priority device in the daisy chain which has received an interrupt acknowledge. All other
peripherals h,3ve IEI=IEO. If the next opcode byte decoded is "40", this peripheral device
will reset its" interrupt under service" condition.
Wait cycles are allowed in the M 1 cycles.
\
RD
/
\'------/
'---I
\'-----.oJ/
DO-D7'----------~~~----------------~~~--------~----------lEI
lEO
294
- - - - - - - -,r-----------------------______
...JI
/
6.0 DAISY CHAIN INTERRUPT SERVICING
The following illustration is a typical nested interrupt sequence which may occur in the SIO.
In a system with several peripheral chips, the other chips may be included in the daisy chain
with either higher or lower priority than the SIO channels.
In this sequence, the transmitter of Channel B interrupts and is granted service. While it is
being serviced, an external/status interrupt from Channel A occurs and is granted service.
The service routine for the Channel A interrupt is completed and either the RETI instruction is executed or the RETI command is written into the SIO to indicated to Channel
A that the external/status interrupt routine is complete. At this time, the service routine for
the Channel B transmitter is resumed. When this routine is completed, another RETI instruction is executed to complete the service.
CHANNELA
RECEIVER
CHANNELA
CHANNELA
TRANSMITTER EXTERNAL!
STATUS
CHANNELS
RECEIVER
CHANNELS
CHANNELS
TRANSMITTER EXTERNAL!
STATUS
1. Priority Interrupt Daisy Chain before any interrupt occurs.
UNDER SERVICE
2. Channel S's transmitter interrupts and is acknowledged.
UNDER SERVICE
SERVICE SUSPENDED
3. External/Status of Channel A interrupts suspending service of Channel S transmitter
SERVICE COMPLETE
SERVICE RESUMED
4. Channel A External/Status routine complete. RET! issued, Channel S transmitter service resumed.
SERVICE COMPLETE
5. Channel B transmitter's service routine complete, second RETI issued.
295
296
7.0 ABSOLUTE MAXIMUM RATINGS*
PRELIMINARY
Voltage on any pin relative to GND ................................ -a.3V to +7V
Operating Temperature (Ambient) T A ................................ aoc to 7aoC
Storage Temperature - Ceramic (Ambient) .........................-65°C to +15aoC
Storage Temperature - Plastic (Ambient) .........................._55° C to +125°C
Power Dissipation .................................................... 1.5W
""Comment
Stresses above those Iisted under "Absolute Maximum Rating" may cause permanent damage to the device. This is a
stress rating only and fUnctional operation of the device at these or any other condition above those indicateq in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for e~ltended
periods may affect device reliabil lty.
7.1 D.C. CHARACTER ISTICS
TA = aoc to 7aoC, VCC = 5V ± 5% unless otherwise specified.
Symbol
Parameter
Min.
VILC
Clock Input Low Voltage
VIHC
VIL
Clock Input High Voltage
Typ.
Max.
Unit
-0.3
.40
V
Input Low Voltage
VCC-·2
-0.3
VCC
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VCC
0.4
V
IOL - 1.8 mA
VOH
Output High Voltage
V
VCC
III
Power Supply Current
140
mA
IOH - 250JlA
tc - 400 nsec
Input Leakage Current
10
ILOH
Tri-State Output Leakage Current in Float
10
ILOL
Tri-State Output Leakage Current in Float
-10
ILD
Data Bus Leakage Current in Input Mode
±10
JlA
JlA
JlA
JlA
2.4
Test Condition
V
V
= 0 to VCC
= 2.4 to VCC
VOUT = O.4V
VIN
VOUT
O during Read Cycle
Data Setup Time to Rising Edge of . By using these timing diagrams,
a set of equations can be derived to show the worst
case access times needed for dynamic memories with
the l80 operating at 2.5MHz.
The access time needed for the op code fetch cycle
and the memory read cycle can be computed by
equations 1 and 2.
tDL(D)
= Data setup time to rising edge of clock
during op code fetch cycle.
let: tc = 400ns; tDL= 50ns
(2) tACCESS MEMORY READ = 4(tc/2) .tDL(MR)
·tS(D)
where: tc = Clock period
tDL(D)
OP CODE FETCH TIMING
Figure la.
T4
VALID REFRESH
ADDRESS AO-A6
AO-A 15
iiiiEQ - f - - - -......
RFSH -r---~------~---;
'---_____--"r
RD -+-----,1
00-07
310
151 (Ol
MEMORY READ TIMING
Figure lb.
1------
400ns
Ie
/
AO-AI5
VALID MEMO RY ADDRESS AO-AI5
100 ns_
MREQ
RO
\
tOLT(MR)
1\
Isf
00-07
(0)_ 60ns
-
MEMORY WRITE TIMING
Figure le.
T2
AO-AI5
ADDRESS
90ns -
-
tDl
T
AO-AI5
(WR)
tW(WRL)
200ns
'D(D)
-360n5--_'"
00-07
DATA OUT
311
zao REFRESH CONTROL AND TIMING
One of the most important features provided by the
Z80 for interfacing to dynamic memories is the
execution of a refresh cycle every time an op code
fetch cycle is performed. By placing the refresh cycle
in the op code fetch, the Z80 does not have to allocate time in the form of "wait states" or by
"stretching" the clock to perform the refresh cycle.
In other words, the refresh cycle is "totally transparent" to the CPU and does not decrease the system
throughput (see Figure la). The refresh cycle is
transparent to the CPU because, once the op code
has been fetched from memory during states T 1
and T 2, the memory would normally be idle during
states T 3 and T 4.
Therefore, by placing the refresh in the T 3 and T 4
states of the op code fetch, no time is lost for refreshing dynamic memory. The critical timing parameters
involving the Z80 and dynamic memories during
the refresh cycle are: tw(MRH) and tw(MRL). The
parameter known as tW(MRH) refers to the time that
MREQ is high during the op code fetch between the
fetch of the op code and the refresh cycle. This time
is known as "precharge" for dynamic memories and is
necessary to allow certain internal nodes of the RAM
to be charged-up for another memory cycle. The
equation for the minimum tW(MRH) time period is:
(1)
(2)
(3)
(4)
Prolonged reset> 1ms
Prolonged wait state operation> 1ms
Prolonged bus acknowledge (OMA) > 1ms
8T28
A tW(MRH) of 160ns is more than adequate to meet
the worst case precharge times for most dynamic
RAMs. For example, the MK4027-4 and the
MK4116-4 require a 120ns precharge.The other
refresh cycle parameter of importance to dynamic
RAMs is tw(MRL), (the time that MREQ
is low during the refresh cycle). This time is important
because MREQ is used to directly generate RAS. The
equation for the minimum time period is:
(4)
where:
let:
then:
tW(MRL)=t c -40
tc is the clock period
tc = 400ns
tw(MRL) = 360ns
A 360ns tW( M R L) exceeds the 250ns min RAS time
required for the MK4027-4 and the MK4116-4.
By controlling the -refresh internally with the Z80,
the designer must be aware of one limitation. The
limitation is that to refresh memory properly, the
Z80 CPU must be able to execute op codes since the
refresh cycle occurs during the op code fetch. The
following conditions cause the execution of op codes
to be inhibited, and will destroy the contents of
dynamic memory.
312
17ns
'ii'"
'"~
~
8T28
SUPPORT CIRCUITS FOR DYNAMIC MEMORY
INTERFACE
Two support circuits are necessary to ensure reliable
operation of dynamic memory with the Z80.
The first of these circuits is an address latch shown in
Figure 3. The latch is used to hold addresses Al Z"
A15 while MREQ is active. This action is necessary
because the Z80 does not ensure the validity of the
address bus at the end of the op code fetch (see
Figure 4). This action does not directly affect dynamic memories because they latch addresses internally. The problem comes from the address decoder
which generates RAS. If the address lines which drive
the decoder are allowed to change while MREQ is
low, then a "glitch" can occur on the RAS line or
lines (if more than one row of RAMs are used)
which may have the effect of destroying one row of
data.
The second support circuit is used to generate a
power on and short manual reset pulse. Recall from
the discussion under Z80 Timing and Memory Con-
ADDRESS LATCH
Figure 3.
7475
AI2
10
IQ
LI2
AI3
20
2Q
AI3
AI4
3D
3Q
AI4
AI5
40
4Q
AI5
G
G
I
I
T
RAS TIMING WITH AND WITHOUT ADDRESS LATCH
Figure 4.
\
OP CODE FETCH
/
\
VALID MEMORY ADDRESS
RAS
RAS
REFRESH ADDRE.SS/
'-----_---I
\
\
WITHOUT ADDRESS
LATCH
WITH ADDRESS
LATCH
VALID REFRESH ADDRESS
·u
/
\
\
/
/
313
trol Signals that one of the conditions that will
cause dynamic memory to be destroyed is a reset
pulse of duration greater than 1ms. The circuit shown
in Figure 5a can be used to generate a short reset
pulse from either a push button or an external
source. Additionally the manual reset is synchronized
to the start of an M1 cycle so that the reset will not
fall during the middle of a memory cycle. Along with
the manual reset, the circuit will also generate a
power on reset.
If it is not necessary that the contents of the dynamic
memory be preserved, then the reset circuit shown in
Figure 5b may be used to generate a manual or
power on reset.
MANUAL AND POWER·ON RESET CIRCUIT
+5
Figure 5a.
+5
10K
10K
IOOOpf
68
+
~f
I.
CPU RESET
10K
74132
7404
EXTERNAL
220 n
>RESET:__~~~~"__' -__-Qrr>-____~
~14
+
168~f
+5
MANUAL AND POWER·ON RESET CIRCUIT
Figure 5b.
10K
~
+
68~fl
10K
EXTERNAL
RESET
314
>____~------~2V2VO~--~~--_.--------J
74132
7404
CPU RESET
~c
cEo
m
C(I)
~C5
!"z
m
X
WR
A1
AI
A8
A2
AS
A:
AI
j.
748157
IA
I.
8
2A
C
0
28
3A
38
4A
48
G
S
AO
,
,6,J4
-
AI
A2
A3
M
AS
CSorA6
-
.' "
=
-
f--
f---
£M
.AS
J51J6
1
DIN
.,
~
IA
A.
AI
f8
2A
28
3A
38
+5V
4A
A
AI
A
~--~
4B
::-
A
I-I--
f-f--
=
I--
f-f-f----
C::
C::
~
~
r-f--
-
r-
f---
=
-f==
-
MK 4116-4
(8)
-=
:s:""C
li
I--
f-l-
-
-
r
m
Z
I--
-
0
-
(I)
-
r
(")
r~
8 f - i----BILS97
C
S°,-
m
~
L
-=
~
AI
AI3
AI
AI
I---
MK4027-4
.".
AI
I
llf-)J
-L
1
):>
I
.117
AI
I~
2~
3.12
~~dEI
JI5
9JI6
4~
~~;
J7 0
J9 0
.III
o
.......18
JIO
;:::'J12
AO
.2
5
E2
6~
+5V~ E3
7
J24
L-J25
7404
'-1
7400
....r----..
~
-.::J
7432
~~
-=
MREQ
+5V
See Tables 1 and 2 for jumper options.
o
S
7404
CK
74374
CAl
.....
U1
R'F'SH
Rif
T
Q
MUX
:::t
m
OA TA
8l s
0
I
2
3
4
5
6
:s:):>
-I
n
C
j;;
Gl
JJ
):>
:s:
DESIGN EXAMPLES FOR INTERFACING THE
Z80 TO DYNAMIC MEMORY
To illustrate the interface between the Z80 and
dynamic memory, two design examples are presented.
Example number 1 is for a 4K/16Kx8 memory and
the example number 2 is a 16K/64Kx8 memory.
Design Example Number 1: 4K/16Kx8 Memory
This design example describes a 4K/16Kx8 memory
that is best suited for a small single board Z80 based
microcomputer system. The memory devices used in
the example are the MK4027 (4,096x1 MOS Dynamic RAM) and the MK4116 (16,384x1 MaS Dynamic RAM). A very important feature of this design
is the ease in which the memory can be expanded
from a 4Kx8 to a 16Kx8 memory. This is made
possible by the use of jumper options which configure the memory for either the MK4027 or the
MK4116. See Table 1 and 2 for jumper options.
Figure 6 shows the schematic diagram for the
4K/16Kx8 memory. A timing diagram for the Z80
control signals and memory control signals is shown
in Figure 7. The operation of the circuit may be
described as follows: RAS is generated by NANDing
MREQ with RFSH + ADDRESS DECODE. RFSH
is generated directly from the Z80 while address
decode comes from the 74LSI38 decoder. Address
decode indicates that the address on the bus falls
within the memory boundaries of the memory.
If an op code fetch or memory read is being executed
the 81 LS97 output buffer will be enabled at approximately the same time as RAS is generated for the
memory array. The output buffer is enabled only
DESIGN EXAMPLE NO.1 MEMORY TIMING
Figure 7.
MREQ_--~,
MUX-------t--~
52n5
CAS------+--,
DATA BUS
316
during an op code fetch or memory read when
ADDRESS DECODE, MREQ, and RD are all low.
The switch multiplexer signal (MUX) is generated on
the rising edge of after MR EQ has gone low during
an op code fetch, memory read or memory write.
After MUX is generated and the address multiplexers
switch from the row address to column address,
CAS will be generated. CAS comes from one of the
outputs of the multiplexer and is delayed by two
gate delays to ensure that the proper column address
set-up time will be achieved. Once RAS and CAS
have been generated for the memory array, the
memory will then access the desired location for a
read or write operation.
7404
7400
22ns}
Generate RAS from MREQ
15ns
63ns
RAS to rising edge of
10ns
to MUX
7404
15ns)
22ns
Generate CAS from MUX
7404
15ns
tCAC
165ns
CAS access time
81 LS97
22ns
Output buffer delay
349ns
Worst case access
74S74
74S157
The worst case access time required by the CPU
for the op code fetch is 450ns (from equation 1);
therefore, the circuit exceeds the required access time
by 101 ns (worst case).
The circuit shown in Figure 6 provides excellent
performance when used as a small on board memory.
The memory size should be held at eight devices
because there is not sufficient timing margin to allow
the interface circuit to drive a larger memory array.
Design Example Number 2: 16Kx8 Memory
This design example describes a 16K/64Kx8 memory
which is best suited for a Z80 based microcomputer
system where a large amount of RAM is desired.
The memory devices used in this example are the
same as for the first example, the MK4027 and the
MK4116. Again as with the first example, the
memory may be expanded from a 16Kx8 to a 64Kx8
by reconfiguring jumpers. See Table 3 and 4 for
jumper options.
Figure 8. shows the schematic diagram for the 16K/
64K memory. A timing diagram is shown in Figure 9.
The operation of the circuit can be described as
follows: RAS is generated by NANDing MREQ with
ADDRESS DECODE (from the two 74LS138s) +
RFSH. Only one row of RAMs will receive a RAS
during an op code fetch, memory read or memory
write. However, a RAS will be generated for all rows
within the array during a refresh cycle. MREQ is
inverted and fed into a TTL compatible delay line to
generate MUX and CAS. (This particular approach
differs from the method used in example number 1
in that all memory timing is referenced to MREQ,
whereas the circuit in example number 1 bases its
memory timing from both MREQ and the clock.
Both methods offer good results, however, the TTL
delay line approach offers the best control over the
memory timing.) MUX is generated 65ns later and is
used to switch the 74157 multiplexers from the
row to the column address. The 65ns delay was
chosen to allow adequate margin for the row address
hold time tRAH. At 110ns, CAS is generated from
the delay line and NANDed with RFSH, which
inhibits a CAS during refresh cycle. After CAS is
applied to the memory, the desired location is then
accessed. A worst case access timing analysis for the
circuit shown in Figure 8 can be computed as follows:
74LS14
74LSOO
delay line
delay line
7400
tCAC
8833
""
15ns
50ns
}
""}
20ns
165ns
30ns
Generate RAS from MREQ
MUX from RAS
CAS delay from MUX
Access time from CAS
Output buffer delay
347ns
The required access time from the CPU is 450ns
(from equation 1). This leaves 103ns of margin for
additional CPU buffers on the control and address
lines.This particular circuit offers excellent results for
an application which requires a large amount of RAM
memory. As mentioned earlier, the memory timing
used in this example offers the best control over the
memory timing and would be ideally suited for an
application which required direct memory access
(DMA).
4K x 8 CONFIGURATION(MK4027) JUMPER
Table 1
Connect: J2 to J3
CONNECT: J13toJ14
J4 to J6
ADDRESS
CONNECT
J7 to J8
OOOO-OFFF
J17toJ25
J9toJ10
1000-1FFF
J18toJ25
Jl1toJ12
2000-2FFF
J19 to J25
3000-3FFF
J20 to J25
4000-4FFF
J21 toJ25
500D-5FFF
J22 to J25
6000-6FFF
J23 to J25
7000-7FFF
J24 to J25
16K x 8 CONFIGURATION (MK4116) JUMPER CONNECTIONS
CONNECT: J14 toJ15
ADDRESS
CONNECT
J17toJ25
8000-8FFF
J18 to J25
9000-9FFF
AOOO-AFFF
J19toJ25
BOOO-BFFF
J20 to J25
J21 to J25
COOO-CFFF
J22 to J25
DOOO-DFFF
J23 to J25
EOOO-EFFF
J24 to J25
FOOO-FFFF
Table 2
CONNECT:
J1 to J2
J4 to J5
J8 to J 11
J 10 to J13
J12 to J 16
J14 to J 16
ADDRESS
CONNECT
0-3FFF
4000-7FFF
8000-BFFF
COOO-FFFF
J17 toJ25
J18toJ25
J19toJ25
J20 to J25
317
16K x 8 CONFIGURATION (MK4027)
Table 3
CONNECT:
J 1 to J3
J5 to J6
J7 to J8
J9toJl0
JlltoJ12
J13toJ14
ADDRESS:
CONNECT:
0-3FFF
J24 to J25
J26 to J27
J28 to J29
J30 to J31
ADDRESS:
CONNECT:
4000-7FFF
J16 to J17
J18 to J19
J20 to J21
J22 to J23
ADDRESS:
CONNECT:
8000-BFFF
J40 to J41
J42 to J43
J44 to J43
J46 to J47
ADDRESS:
CONNECT:
64K x 8 CONFIGURATION(MK4116)
Table 4
CONNECT:
J1 to J2
J4 to J5
J8 to J 11
J1QtoJ13
J 12 to J 15
J14 to J15
ADDRESS: Q·FFFF
CONNECT: J32 to J33
J34 to J35
J36 to J37
J38 to J39
SYSTEM PERFORMANCE CHARACTERISTICS
Table 5
The system characteristics for the preceeding design
examples are shown in Table 5.
EXAMPLE
2
#
MEMORY CAPACITY
MEMORY ACCESS
POWER REQUIREMENTS
4K/16Kx8
349ns max.
16K/64Kx8
347ns max.
+12V @ 0.0250 A max.
+5V @ 0.422 A max.'
-5V @ 0.030 A max.
+12V @ 0.600 A max.
+5V @ 0.550 A max. '
-5V @ 0.030 A max.
'All power requirements are max.; operating temperature O°C
to 70°C ambient, max +12V current computed with Z80
executing continuous op code fetch cycles from RAM at
1.6 Jl s intervals.
318
COOO-FFFF
J32 to J33
J34 to J35
J36 to J37
J38 to J39
DESIGN EXAMPLE NO.2 SCHEMATIC DIAGRAM
Figure 8.
74LSI4
R5
RFSH
74LSI4
MREQ
RAS
DID
DOD
D11
DOl
D12
D02
013
D03
WRiTE
WR
MEMORY ARRAY
32 DEVICES
16k.8 (MK 4027-4)
64k ,8(MK4116-4)
CAs
AD
AI
A4
A2 A3
A5
OOVR RCV B
1
0
B
1
8833
0
B
1
0
1
014
D04
D15
005
DIG
DOS
DI7
D07
B
DO
DI
D2
D3
B
04
B
D5
8833
D6
D7
CS(A6)
IY
2Y
3Y
4Y
.------Ai2
~~~~~L.-U,"'-r~L~ L~.~~L~~~L~.L,~~~M'''~
74LSI4
AD
A7
AI
A8
A2
A9
A3
AID
A4
All
A5
AI2
AG
AI3
AI4
AI5
FOR JUMPER OPTIONS SEE TABLES 3 AND 4
319
II
DESIGN EXAMPLE NO.2 MEMORY TIMING
Figure 9.
~----400ns----~
MREQ - - - - - _.....
OP CODE FETCH
37ns
RAS------------~~
160 ns
MUX------------4----~
65 ns
CAS---------+------~
~
195ns ..
DATA BUS
3470s----1
PRINTED CIRCUIT LAYOUT
One of the most important parts of a dynamic
memory design is the printed circuit layout. Figure
10 illustrates a recommended layout for 32 devices.
A very important factor in the P.C. layout is the
power distribution. Proper power distribution on
the VOO and VBB supply lines is necessary because
of the transient current characteristics which dynamic
memories exhibit. To achieve proper power distribution, VOO, VBB, VCC and ground should be laid
out in a grid to help minimize the power distribution
impedance. Along with good power distribution,
adequate capacitive bypassing for each device in the
memory array is necessary. I n addition to the individual by-passing capacitors, it is recommended that
each supply (VBB, Vee and VOO) be bypassed with
an electrolytic capacitor 20.uF.
By using good power distribution techniques and
using the recommended number of bypassing capacitors, the designer can minimize the amount of noise
in the memory array. Other layout considerations
320
are the placement of signal lines. Lines such as
address, chip select, column address strobe, and
write should be bussed together as rows; then, bus
all rows together at one end of the array. Interconnection between rows should be avoided. Row
address strobe lines should be bussed together as al
row, then connected to the appropriate RAS driver.
TTL drivers for the memory array signals should be
located as close as possible to the array to help
minimize signal noise.
For a large memory array such as the one shown in
design example number 2, series terminating resistors
should be used to minimize the amount of negative
undershoot. These resistors should be used on the
address lines, CAS and WRITE, and have values
between 20 n to a 33 n .
The layout for a 32 device array can be put in a 5" x
5" area on a two sided printed circuit board.
SUGGESTED P. C. LAYOUT FOR MK4027 or MK4116
Figure 10.
321
4MHz Z80 DYNAMIC
CONSIDERATIONS
MEMORY
INTERFACE
A 4MHz Z80 is available for the microcomputer designer who needs higher system throughput. Considerations which must be faced by the designer when
interfacing the 4MHz Z80 to dynamic memory are
the need for memories with faster access times
and for providing minimum RAM precharge time.
The access times required for dynamic memory interfaced to a 4MHz Z80 can be computed from equations 1 and 2 under Z80 Timing and Memory Control
Signals.
Access time for op code fetch for 4MHz
zao,
let: tc = 250ns; tDLi (MR) = 75ns; tS (D) = 35ns
then: tACCE55 OP CODE = 265ns
Access time for memory read for 4MHz
zao,
let: tc
= 250ns; tDL;f;(MR) = 75ns; t5¢ (D) = 50ns
A tW(MRH) of 95ns will not meet the minimum precharge time of the MK4027-2 or MK4116-2 which is
100ns. The MK4027-3 and MK4116-3 require a
120ns precharge. Figure 11 shows a circuit that will
lengthen the tW(MRH) pulse from 95ns to a minimum of 126ns while only inserting one gate deldY
into the access timing chain. Figure 12 shows the
timing for the circuit of Figure 11. The operation of
the circuit in Figure 11 can be explained as follows:
The D flip flops are held in a reset condition until
MREO goes to its active state. After MREO goes
active, on the next positive clock edge, the D input of
U1 and U2 will be transferred to the outputs of the
flip flops. Output OA will go high if M1 was high
when clocked U 1. Output 08 will go low on the
next positive going clock edge, which will cause
the output of U3 to go low and force the output of
U4, which is RAS, high. He flip flops will be reset
when MREO goes inactive.
then: tACCE55 MEMORY READ = 375ns
The problem of faster access times can be solved by
using 200ns memories such as the MK4027-3 or
MK4116-3. Depending on the number of buffer
delays in the system, the designer may have to use
150ns memories such as the MK4027-2 or MK4116-2.
The most critical problem that exists when interfacing dynamic memory to the 4MHz Z80 is the
RAM precharge time (trp). This parameter is called
tW(MRH) on the Z80 and can be computed by the
following equation.
The circuit shown in Figure 11 will give a minimum
of 126ns precharge for dynamic memories, with the
Z80 operating at 4MHz. The 126ns tW(MRH) is computed as follows.
110ns
5ns
20ns
-9ns
126ns
(4) tW( R H) = tW(H) + tf-20ns
let: tW(H) = 110ns; tf = 5ns
then: tW(MRH) = 95ns
tW( H) - clock pulse width high (min)
tF - clock full time (min)/
tDLitMR) - MREQdeiay (min)
74574 delay (min)
tW(MRH) modified (min)
4MHz Z80 PRECHARGE EXTENDER FOR DYNAMIC MEMORIES
Figure 11.
+5
MI
+5
>---;D 5a~_a_A________~D 5
74574
aB
MREa
h-----
ADDRESS DECODE
322
+
RFSH
RA5
TIMING DIAGRAM FOR 4MHz Z80 PRECHARGE EXTENDER
Figure 12
MREQ
------+---..
QA --------~
9ns
QB
-----------------------------1
APPENDIX
passes, which will execute in less than 4 minutes
for a 16Kx8 memory. If an error occurs, the program
will store the pattern in location '2C'H and the
address of the error at locations '2D'H and '2E'H.
MEMORY TEST ROUTINE
This section is intended to give the microcomputer
designer a memory diagnostic suitable for testing
memory systems such as the ones shown in Section
VI.
The routine is a modified address storage test with an
incrementing pattern. A complete test requires 25610
LOC
OBJ CJDE
The program is set up to test memory starting at location '2F'H up to the end of the block of memory
defined by the bytes located at 'OC'H and 'OD'H.
The test may be set up to start at any location by
modifying locations '03'H - '04'H and '11 'H - '12'H
with the starting address that is desired.
IIXRTS LISTING
STMT SOURCE STATEMENT
PAGE
0001
0001 ;TRANSLATED FROM DEC 1976 INTERFACE MAGAZINE
0002 ;
0003 ;THIS IS A MO~IFIED ADDRESS STORAGE TEST WITH AN
0004 ;INCREKENTI!G ?ATTERN
0005 ,
0006 ;256 PASSZS MUST BE EXECUTED BEFORE THE MEMCRY IS
0007 ;COMPLETELY TESTED.
0008 ;
0009 ;IF AN ERROR OCCURS, THE PATTERN WILL BE STORED
0010 ;AT LOCATION '002C'H AND THE ADDRESS OF THE
0011 ;ERROR LOCATION WILL BE STORED AT '002D'H AND
0012 ; '002E'H.
0013
323
MEMORY TEST ROUTINE (Cont'd.)
0014
0015
0016
0017
0018
0019
0020
0021
;THE CONTENTS OF LOCATIONS 'OOOC'H AND '001D'H
;SHOULD BE SELECTED ACCORDING TO THE FOLLOWING
;MEMORY SIZE TO BE TESTED
,
;TOP OF MEMORY TO
;BE TESTED
0022
0000
0000
0600
0002
0005
0006
0007
0008
0009
OOOA
OOOB
0000
212FOO
70
AC
A8
77
23
7C
FE10
C20500
0010
0013
212FOO
7D
AC
A8
BE
C22500
23
7C
FE10
C21300
04
0014
0015
0016
0017
001A
001B
001C
001E
0021
LOC
0022
0025
0028
002B
002C
002D
002F
324
OBJ CODE
C30200
222DOO
322COO
76
2FOO
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
,
;TEST TIME FOR A 16K X 8 MEMORY IS APPROX. 4 MIN
;LOAD
LOOP:
FILL:
;READ
0049 TEST:
0050
0054
0055
0056
0057
0058
, 10' H
'20'H
'40 'H
'80'H
'CO'H
'FF'H
4K
8K
16 K
32K
48K
64K
;THE PROGRAM IS SET UP TO START TESTING AT
;LOCATION '002F'H. THE STARTING ADDRESS FOR THE
;TEST CAN BE MODIFIED BY CHANGI~G LOCATIONS
;'0003-0004'H F.ND '0011-0012'H.
0048
0051
0052
0053
ORG
OOOOH
LD
B,O
;CLEAR B PATRN MODIFIER
UP MEMORY
LD
HL,START ;GET STF.RTING ADDt!
A,l.
;LOII BYTE TO ACeI'!
LD
XOR
;XOR filTH HIGH 3ITE
H
;XOR WITH PATTERN
XOS
B
(HL) ,A
LD
;STORE IN ADDR
INC
;INCRBMENT ADDR
HL
A,H
;10AD HIGH BYTE OF ADDR
1D
;:;OMPARE "ITH STOP ADDR
CP
EPAGE
NZ,FI1L
;NOT DONE,GO BACK
JP
AND CHECK TEST DATE
HL,START ;GET STARTING ADDR
LD
'\,L
LD
; LO.~D LOW BYTE
XOR
H
;XOR WITH HIGH BYTE
;XOR WITH MODIFIER
XOR
B
(
HL)
;::OMPARE
CP
WITH MDIORY LOC
;ERROR EXIT
NZ,FXIT
JP
;UPDATE MEMORY ADDRESS
INC
HL
;LOAD HIGH BYTE
A,H
LD
;COMPARE WITH STOP ADDR
EPAGE
CP
;LOOP BACK
NZ,TEST
JP
; UPDATE MODIFIER
INC
B
!'JXRTS LISTING
STMT SOURCE STATEMENT
0059
0060
0061
0062
0063
0064
0065
0066
0068
0069
VALUE OF EPAGE
JP
;ERROR EXIT
HIT:
LD
LD
HALT
PATRN:
DEFS
BYTE:
DEFS
START:
DEFli
EPAGE:
EQU
END
LOOP
PAGE
; RST WITH NEW MODIFIER
(BYTE), HL ;SAVE ERROP ADDRESS
(PATEN),A ;SAVE BAD PATTERN
;FLAG OHRATOR
1
2
$
10H
0002
;SE! UP FOR 4K TEST
1979 MICROCOMPUTER DATA BOOK
325
326
MOSTEI(@
F8 MICROCOMPUTER DEVICES
Single-Chip Microcomputer MK 3870
FEATURES
SINGLE CHIP 3870 MICROCOMPUTER FAMI L Y
o Software compatible with 3870/F8 family
o 2048 X 8 mask programmable ROM
o
o
I/O<=>E<=>
<=>
<=>
MK3870
1/0
64 byte scratch pad RAM
32 bits (4 ports) TTL compatible I/O
I nterval timer mode
<=>
I/O<=>
1/0
Pulse width measurement mode
Event counter mode
External interrupt
a(:::::)
MK3873
SERIAL 1/0
(:::::) 1/0
0110
1/00BOI/o
MK3876
I/O 0
<=> 1/0
Crystal, LC, RC, or external time base
Low power (275 mW typ.)
1/0
1/0°8°1/0
MK3872
1/00
<=:> 1/0
o Programmable binary timer
o
o
o
o
1/0
F8 FAMILY
Single +5 volt ± 10% power supply
o Pinout compatible with 3870 family
P
E
GENERAL DESCRIPTION
R
I
P
H
The MK3870 is a complete 8-bit microcomputer
on a single MOS integrated circuit. The 3870 can
execute the F8 instruction set of more than 70 commands, allowing expansion into multi-chip configurations with software compatibility. The device
features 2048 bytes of ROM, 64 bytes of scratchpad RAM, a programmable binary timer, 32 bits of
I/O, and a single +5 volt power supply requirement.
Utilizing ion-implanted, N-channel silicon-gate technology and· advanced circuit design techniques, the
single-chip 3870 offers maximum cost effectiveness in a wide range of control and logic replacement applications.
FUNCTIONAL PIN DESCRIPTION
PO-0-PO-7, P1-0-P1-7, P4-0-P4-7, and P5-0-P5-7
are 32 lines which can be individually used as either
TTL compatible inputs or as latch outputs.
STROBE is a ready strobe associated with I/O Port 4.
This pin which is normally high provides a single low
pulse after valid data is present on the P4-0-P4-7 pins
during an output instruction.
E
R
A
L
S
I/OW
I/OW
I/OW
I/OW
<
I/OW
PIN CONNECTIONS
XTL1
•
1
40
'4-------
Vee
XTL2
.. 2
39
<1----
RESET
PO-o . . . 3
PO-1 . . . 4
1'0-2" .. 5
PO-3" • 6
STROBE...
3 8 _ EXTINT
37 . . . . I'i:o
36 . . "
Pf-l
35 .___
. . . PI-2
34
pj:3
7
P4-0 - - 8
P4-1"" 9
P4-2" .. 10
P4-3" •
P4-4" •
11
12
l'4-5 .... 13
33 ...... ps-o
32 ..... P5-1
31 ..... P5-2
30 ..... i'!r.3
29 .. -- P5-4
28 _
..
i'5-5
PO-7" •
16
27 .... P5-6
26 . . . . P5-7
25 _ .. PI-7
PO-5" •
1B
23 . . . .
P4-6" .. 14
P4-7" .. 15
24 . . . .
GNO
PHI
Pr:!i
22 . . . . I'f-4
21..
TEST
RESET may be used to externally reset the 3870.
When pulled low the 3870 will reset. When then
327
PIN NAME
DESCR IPTION
TYPE
PO-O - PO~7
I/O Port 0
Bidirectional
I/O Port 1
I/O Port 4
I/O Port 5
Ready Strobe
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Input
Input
P1-0 - P1-7
P4-0 - P4-7
P5-0 - P5-7
---STROBE
EXTINT
RESET
TEST
XTL 1, XTL 2
VCC, GND
External Interrupt
External Reset
Test Line
Time Base
Power Supply Lines
allowed to go high the 3870 will begin program
execution at program location H '000'.
Counter is used to address instructions or immediate
operands. P is used to save the contents of PO during
an interrupt or subroutine call. Thus P contains the
return address at which processing is to resume upon
completion of the subroutine or the interrupt routine.
The Data Counter (DC) is used to address data
tables. This register is auto-incrementing. Of the
two data counters only DC can access the ROM.
However, the XDC instruction allows DC and DC1
to be exchanged.
Associated with the address registers is an 11 bit
Adder/lncrementer. This logic element is used to
increment PO or DC when required and is also used
to add displacements to PO on relative branches or
to add the data bus contents to DC in the ADC
(Add Data Counter) instruction.
2048 X 8 ROM
EXT INT is the external interrupt input. Its active
state is software programmable. This input is also
used in conjunction with the timer for pulse width
measurement and event counting.
XTL 1 and XTL 2 are the time base inputs to which
a crystal (1 to 4 MHz), LC network, RC network, or
an external single-phase clock may be connected.
The microcomputer program and data constants
are stored in the program ROM. When a ROM access
is required, the appropriate address register (PO or
DC) is gated onto the ROM address bus and the ROM
output is gated onto the main data bus. The first byte
in the ROM is location zero.
Scratch pad and IS
TEST is an input, used only in testing the 3870.
For normal circuit functionality this pin is left
unconnected or may be grounded.
VCC is the power supply input (+5V ± 10%).
3870 ARCHITECTURE
This section describes the basic functional elements
of the 3870 as shown in the block diagram of
Figure 1. A programming model is shown in Figure 2.
Main Control Logic
The Instruction Register (IR) receives the operation
code (OP code) of the instruction to be executed
from the program ROM via the data bus. During
all OP code fetches eight bits are latched into the I R.
Some instructions are completely specified by the
upper 4 bits of the OP code. In those instructions
the lower 4 bits are an immediate register address or
an immediate 4 bit operand. Once latched into the
I R the main control logic decodes the instruction
and provides the necessary control gating signals to
all circuit elements.
ROM Address Registers
There are four 11 bit registers associated with the
2K x 8 ROM. These are the Program Counter (PO),
the Stack Register (P), the Data Counter (DC) and
the Auxiliary Data Counter (DC1). The Program
328
The scratch pad provides 64 8-bit registers which
may be used as general purpose RAM memory.
The Indirect Scratchpad Address Register (IS) is a
6 bit register used to address the 64 registers. All 64
registers may be accessed using IS. In addition the
lower order 12 registers may also be directly addressed.
IS can be visualized as holding two octal digits. This
division of IS is important since a number of instructions increment or decrement only the least significant 3 bits of IS when referencing scratch pad bytes
via IS. This makes it easy to reference a buffer consisting of contiguous scratchpad bytes. For example,
when the low order octal digit is incremented or decremented IS is incremented from octal 27 (0 '27') to
'20) or is decremented from 0 '20' to 0 '27'. This
feature of the IS is very useful in many program
sequences. All six bits of IS may be loaded at one
time or either half may be loaded independently.
o
Scratch pad registers 9 through 15 (decimal) are given
mnemonic names (J, H, K, and Q) because of special
linkages between these registers and other registers
such as the Stack Register. These special linkages
facilitate the implementation of multi-level interrupts
and subroutine nesting. For example, the instruction
LR K,P stores the lower eight bits of the Stack
Register into register 13 (K lower or KL) and stores
the upper three bits of P into register 12 (K upper
or KU).
Arithmetic and Logic Unit (ALU)
After receiving commands from the main control
logic, the ALU performs the required arithmetic or
logic operations (using the data presented on the
two input busses) and provides the result on the
result bus. The arithmetic operations that can be
performed in the ALU are binary add, decimal
adjust, add with carry, decrement, and increment.
The logic operations that can be performed are
AND, OR, EXCLUSIVE OR, 1's complement,
shift right, and shift left. Besides providing the
result on the result bus, the ALU also provides four
signals representing the status of the result. These
signals, stored in the Status Register (W), represent
CARRY, OVERFLOW, SIGN, and ZERO condition
of the result of the operation.
3
o
2
_BIT NO.
STATUS REGISTER (W)
SIGN
CARRY
ZERO
OVERFLOW
INTERRUPT CONTROL
BIT
Summary of Status Bits
Accumulator(A)
OVERFLOW = CARRY 7\i)CARRY 6
The Accumulator (A) is the principal register for
data manipulation within the 3870. The A serves
as one input to the ALU for arithmetic or logical
operations. The result of ALU operations are stored
in the A.
ZERO
ALU7 AALU6 A ALU5 A ALU4 /\
ALU3 A ALU2 A ALUl /\ ALUO
CARRY
CARRY7
SIGN
ALU7
MK3870 BLOCK DIAGRAM
Figure 1
XTL1
EXTINT
XTL2
~
MEMORY ADDRESS BUS
:
2048 X 8
~':.
ROM
MEMORY
ADDRESS
M
A
I
N
PO;P
DC, DCl
M
E
M
MAIN
R
CONTROL
o
Y
LOGIC
~<;.:
~L;,::.::;,: .\'.'
TEST
RESULT BUS
1/0
I/o
I/O
I/O
329
II
3870 PROGRAMMABLE REGISTERS, PORTS AND MEMORY MAP
Figure 2
INDIRECT
SCRATCHPAD
ADDRESS REGISTER
ACCUMULATOR
J
A
I
I
ISL
32
0
PROGRAM
COUNTER
(W)
1~IOlzlclSI
z
I
0
N
T
R
V E A I
ERR G
R 0 R N
C S
C
F
..
Y
0
O{
~
STACK
REGISTER
..
I
..
0
11 bits
0
0
1
0
J
9
9
11
HU
10
A
12
HL
11
B
13
KU
12
C
14
KL
13
o
15
OU
14
E
16
OL
15
F
17
ill
3D
75
62
3E
76
63
3F
77
§
PL
87
7_8bits_0
PORT 7
DATA
COUNTER
7_8bits_0
I
INTERRUPT
CONTROL PORT
MAIN MEMORY
MEMORY
DC
DCU
..
10
I
0
~
PORT 6
7_8bits_0
R
0
M
AUX DATA
COUNTER
DCl
I/O PORTS
PORT 5
PORT4
PORT 1
PORTO
330
DCI U
.
10
I
~
DCL
87
11 bits
DCI L
87
11 bits
OCl
I
P
PU
10
BINARY
TIMER
K{
POL
87
11 bits
10
N L
T 0
R W
L
4 _ 5bits_0
H{
PO
POU
HEX
I
-6bits-
STATUS
REGISTER
DEC
~
IS
ISU
5
7-8bits-0
SCRATCHPAD
0
~
~
DEC
HEX
0
0
2046
7FE
2047
7FF
The Status Register(W)
Interrupt Control Port (Port 6)
The Status Register (also called the W register)
holds five status flags as follows:
Bit 0 - External Interrupt Enable
Bit 1 - Timer Interrupt Enable
Bit 2 - EXT INT Active Level
Bit 3 - Start/Stop Timer
Bit 4 - Pulse Width/Interval Timer
Bit 5 - 7 2 Prescale
Bit 6 - 7 5 Prescale
Bit 7 - 7 20 Prescale
Interrupt Control Bit (ICB)
The ICB may be used to allow or disallow interrupts
in the 3870. This bit is not the same as the two
interrupt enable bits in the Interrupt Control Port
(ICP). If the ICB is set and the 3870 interrupt logic
communicates an interrupt request to the CPU
section, the interrupt will be acknowledged and
processed upon completion of the first non-privileged instruction. If the ICB is cleared an interrupt request will not be acknowledged or processed
until the ICB is set.
I/O Ports
The 3870 provides four complete bidirectional
Input/Output ports. These are ports 0, 1, 4, and 5.
In addition, the Interrupt Control Port is addressed
as port 6 and the binary timer is addressed as port 7.
An output instruction (OUT or OUTS) causes the
contents of A to be latched into the addressed port.
An input instruction (I N or I NS) transfers the contents of the port to A (port 6 is an exception which
is described later). The schematic of an I/O pin and
available output drive options are shown in Figure 3.
An output ready strobe is associated with port 4. This
flag may be used to signal a peripheral device that
the 3870 has just completed an output of new
data to port 4. The strobe provides a single low pulse
shortly after the output operation is completely
finished, so either edge may be used to signal the
peripheral. STROBE may also be used as an input
strobe simply by doing a dummy output of H '00'
strobe to port 4 after completing the input operation.
Timer and Interrupt Control Port
The Timer is an 8-bit binary down counter wh ich is
software programmable to operate in one of three
modes: the Interval Timer Mode, the Pulse Width
Measurement Mode, or the Event Counter Mode.
As shown in Figure 4, associated with the Timer
are an 8-bit register called the Interrupt Control
Port, a programmable prescaler, and an 8-bit modulo-N register. A functional logic diagram is shown
in Figure 5.
The desired timer mode, prescale value, starting and
stopping the timer, active level of the EXT INT pin,
and local enabling or disabling of interrupts are selected by outputting the proper bit configuration from
the Accumulator to the Interrupt Control Port (port
6) with an OUT or OUTS instruction. Bits within the
Interrupt Control Port are defined as follows:
A special situation exists when reading the Interrupt
Control Port (with an I N or I NS instruction). The
Accumulator is llill loaded with the content of the
ICP; instead, Accumulator bits 0 through 6 are loaded
with O's while bit 7 is loaded with the logic level
being applied to the EXT I NT pin, thus allowing the
status of EXT I NT to be determined without the
necessity of servicing an external interrupt request.
When reading the Interrupt Control Port (Port 6)
bit 7 of the Accumulator is loaded with the actual
logic level being applied to the EXT INT pin, regardless of the status of I CP bit 2 (the EXT I NT Active
Level bit); that is, if EXT I NT is at +5V bit 7 of the
Accumulator is set to a logic 1, but if EXT INT is at
GND then Accumulator bit 7 is reset to logic O.
This capability is useful in establishing a high speed
polled handshake procedure or for using EXT I NT
as an extra input pin if external interrupts are not
required and the Timer is used only in the Interval
Timer Mode. However, if it is desirable to read the
contents of the ICP then one of the 64 scratch pad
registers or one byte of RAM may be used to save
a copy of whatever is written to the ICP.
The rate at which the timer is clocked in the Interval
Timer Mode is determined by the frequency of an
internal
G)
MODULO-N REGISTER
:Il
»
s
8-bits
INT
CO
PO
(po
I
WPT
OL
Event Counter Mode
2 Prescale
+20
~5
7
6
0
,2
-5
0
~
0
0
0
1
5 Prescale
~
0
1
0
10 Prescale
~
0
1
~
20 Prescale
~
0
0
40 Prescale
100 Prescale
~
0
1
200 Prescale
~
~
0
4
_---- __J .3
2
L:
0
Bit No.
Ext"'" 'ot"'Ppt E"b'e
Timer Interrupt Enable
~
EXT INT Active Level
•
Start/Stop Timer
Pulse Width/Interval Timer
Note: See Fiqure 5for a more detailed functional diagram.
w
w
w
EXTERNAL
INTERRUPT
REQUEST
LATCH
FROM
w
INTERRUPT
CONTROL
.s w
PORT
::!!3:
~
.,..w
co CO
u. ......
83
82 I B4
85
86
C
SO lSI
87
....
'INS 7'
3:
m
~
:xl
:::
....zm
:xl
:xl
-
~
C
TIMER INTERRUPT*
*LOADS INTERRUPT VECTOR
~~Oi~~ U~~~~O~6~TION
PRIVILEGED
~
."
INSTRUCTION.
C
Z
(")
::!
o
Z
~
•
III
C
~f~~RWLEDGE
INTERRUPT
»
I'
o
~
:xl
»
3:
'I', PULSE WIDTH MODE
'I'SELECTS
JL
EXTERNAL
INTERRUPT
INPUT
JL
EXTERNAL INTERRUPT t
t LOADS INTERRUPT VECTOR
H 'OAO' UPON COMPLETION
OF THE FIRST NONPRIVILEGED INSTRUCTION
IDII
~
___________________________________________CC ACKNOWLEDGE
~~i~~~~~T
clear any previously stored timer interrupt request.
As previously noted, the Timer is an 8-bit down
counter which is clocked by the prescaler in the
Interval Timer Mode and in the Pulse Width Measurement Mode. The prescaler is not used in the Event
Counter Mode. The Modulo-N register is a buffer
whose function is to save the value which was most
recently outputted to Port 7. The modulo-N register
is used in all three timer modes.
Interval Timer Mode
When ICP bit 4 is cleared (logic 0) and at least one
prescale bit is set the Timer operates in the Interval
Timer Mode. When bit 3 of the ICP is set the Timer
will start counting down from the modulo-N value.
After counting down to H'01', the Timer returns to
the modulo-N value at the next count. On the transition from H'01' to H 'N' the Timer sets a timer
interrupt request latch. Note that the interrupt request latch is set by the transition to H 'N' and not
be the presence of H 'N' in the Timer, thus allowing
a full 256 counts if the modulo-N register is preset
to H '00'., If bit 1 of the ICP is set, the interrupt request is passed on to the CPU section of the 3870.
However, if bit 1 of the ICP is a logic 0 the interrupt
request is not passed on to the CPU section but the
interrupt request latch remains set. If ICP bit 1 is
subsequently set, the interrupt request will then be
passed on to the CPU section. (Recall from the discussion of the Status Register's Interrupt Control Bit
that the interrupt request will be ackoowledged by
the CPU section only if ICB is set). Only two events
can reset the timer interrupt request latch; when the
timer interrupt request latch is acknowledged by the
CPU section, or when a new load of the modulo-N
register is performed.
Consider an example in which the modulo-N register
is loaded with H '64' (decimal 100). The timer
interrupt request latch will be set at the 100th
count following the timer start and the timer interrupt request latch will repeatedly be set on precise
100 count intervals. If the prescaler is set at -;-40
the timer interrupt request latch will be set every
4000 clock (4MHz
time base frequency) this will produce 2 millisecond
intervals.
The range of possible intervals is from 2 to 51,200
cJ> clock periods (1~s to 25.6ms for a 2MHzcJ> clock).
However, approximately 50 cJ> periods is a practical
minimum because the time between setting the
interrupt request latch and the execution of the first
instruction of the interrupt service routine is at least
29 cJ> periods (the response time is dependent upon
how many privileged instructions are encountered
when the request occurs); 29 is based on the timer
interrupt occuring at the beginning of a non-priviledged short instruction. To establish time intervals
greater than 51,200 'I> clock periods is a simple
matter of using the timer interrupt service routine to
count the number of interrupts, saving the result in
one or more of the scratch pad registers until the
desired interval is achieved. With this technique
virtually any time interval, or several time intervals,
may be generated.
The Timer may be read at any time and in any mode
using an input instruction (IN 7 or INS 7) and may
take place "on the fly" without interfering with
normal timer operation. Also, the Timer may be
stopped at any time by clearing bit 3 of the ICP.
The Timer will hold its current contents indefinitely
and will resume counting when bit 3 is again set.
Recall however that the prescaler is reset whenever
the Timer is stopped; thus a series of starting and
stopping will result in a cumulative truncation error.
A summary of other timer errors is given in the
timing section of this specification. For a free
running timer in the Interval Timer Mode the time
interval between any two interrupt requests may be
in error by ± 6 cJ> clock periods although the cumulative error over many intervals is zero. The prescaler
and Timer generate precise intervals for setting the
timer interrupt request latch but the time out may
occur at any time withi n a machine cycle. (There
are two types of machine cycles; short cycles which
consist of 4 cJ> clock periods and long cycles wh ich
consist of 6 cJ> clock periods. In the mUlti-chip F8
family there is a signal called the WRITE clock which
corresponds to a machine cycle). Interrupt requests
are synchronized with the internal WRITE clock
thus giving rise to the possible ± 6 cJ> error. Additional
errors may arise due to the interrupt request occuring
while a privileged instruction or multicycle instruction is being executed. Nevertheless, for most applications all of the above errors are negligible, especially if the desired time interval is greater than
1 ms.
Pulse Width Measurement Mode
When ICP bit 4 is set (logic 1) and at least one prescale bit is set the Timer operates in the Pulse Width
Measurement Mode. This mode is used for accurately
measuring the duration of a pulse applied to the
EXT INT pin. The Timer is stopped and the prescaler is reset whenever EXT I NT is at its inactive
level. The active level of EXT I NT is defined by
ICP bit 2; if cleared, EXT INT is active low; if set,
EXT INT is active high. If ICP bit 3 is set, the
prescaler and Timer will start counting when EXT
INT transitions to the active level. When EXT INT
returns to the inactive level the Timer then stops,
the prescaler resets, and if lCf l2l1 Q is set an external interrupt request latch is set. (Unlike timer
interrupts, external interrupts are not latched if
the ICP Interrupt Enable bit is not set).
335
As in the Interval Timer Mode, the Timer may be
read at any time, may be stopped at any time by
clearing ICP bit 3, the prescaler and ICP bit 1 function as previously described, and the :imer still
functions as an 8-bit binary down counter with the
timer interrupt request latch being set on the Timer's
transition from H '01' to H 'N'. Note that the EXT
INT pin has nothing to do with loading the Timer;
its action is that of automatically starting and stopping the Timer and of generating external interrupts.
Pulse widths longer than the prescale value times the
modulo-N value are easily measured by using the
timer interrupt service routine to store the number of
timer interrupts in one or more scratch pad registers.
As for accuracy, the actual pulse duration is typically
slightly longer than the measured value because the
status of the prescaler is not readable and is reset
when the Timer is stopped. Thus for maximum
accuracy it is advisable to use a small division setting
for the prescaler.
Event Counter Mode
II
..
When ICP bit 4 is cleared and all prescale bits (I CP
bits 5, 6, and 7) are cleared the Timer operates in
the Event Counter Mode. This mode is used for
counting pulses applied to the EXT INT pin. If
ICP bit 3 is set the Timer will decrement on each
transition from the inactive level to the active level
of the EXT I NT pin. The prescaler is not used in
this mode; but as in the other two timer modes, the
Timer may be read at any time, may be stopped at
any time by clearing ICP bit 3, ICP bit 1 functions
previously described, and the timer interrupt request
latch is set on the Timer's transition from H '01'
to H 'N'.
Normally ICP bit 0 should be kept cleared in the
Event Counter Mode; otherwise, external interrupts
will be generated on the transition from the inactive
level to the active level of the EXT INT pin.
For the Event Counter Mode the
width required on EXT INT is 2
and the minimum inactive time is 2
therefore, the maximum repetition
minimum pulse
clock periods)
in all cases except where B is the Decrement Scratchpad instruction, in which case the freeze cycle is a
long cycle (6 clock periods).
I NT R EO goes low on the next negative edge of
WRITE if both PRI IN is low and the appropriate interrupt enable bit of the I nterrupt Control Part is set.
Both INT REO and WRITE are internal signals.
Event C
A NO-OP long cycle to allow time for the internal priority chain to settle.
Event D
The program counter (PO) is pushed to the stack
register (P) in order to save the return address. The
interrupt circuitry places the lower 8 bits of the interrupt vector address onto the data bus. This is always a
long cycle.
Event E
A long cycle in which the interrupt circuitry places
the upper 8 bits of the interrupt vector address onto
the data bus.
A short cycle in which the interrupting interrupt request latch is cleared. Also, the CPU's Interrupt Control Bit is cleared, thus disabling interrupts until an EI
instruction is performed. The fetch of the next instruction from the interrupt address.
Event G
Begin execution of the first instruction of the interrupt service routine.
Summary Of Interrupt Sequence
For the MK3870 the interrupt response time is defined as the time elapsed between the occurence of
EXT I NT going active (or the Timer transitioning to
H'N') and the beginning of execution of the first instruction of the interrupt service routine. The interrupt response time is a variable depedent upon what
the microprocessor is doing when the interrupt request occurs. As shown in Figure 5, the minimum
interrupt response time is 3 long cycles plus 2 short
cycles plus one WR ITE clock pulse width plus a setup
time of EXT I NT prior to the leading edge of the
WR ITE pulse - a total of 27 clock periods plus the
setup time. At a 2 MHz this is 14.25 /-lS. Although
the maximum could theoretically be infinite, a practical maximum is 35 /-lS (based on the interrupt request occurring near the beginning of a PI and LR K,
P sequence).
Power-On Clear
The intent of the Power-an-Reset circuitry on the
3870 is to automatically reset the device following
a typical power-up situation, thus saving external
reset circuitry in many applications. This circuitry is
not guaranteed to sense a "Brown Out" (low voltage)
condition nor is it guaranteed to operate under all
possible power-on situations.
Three conditions are required before the 3870 will
leave the reset state and begin operation. Refer to
Figure 7 as an aid to the following descriptions. The
On-Chip Vcc detector senses a minimum value of Vcc
before it will allow the 3870 to operate. The threshold of this detector is set by analog circuitry because
a stable voltage reference is not available with
n-channel MaS processing. Processing variations will
cause this threshold to vary from a low of 3.0 volts to
a high of 4.3 volts with 3.5 volts .being typical.
337
The 3870 uses a substrate bias as a technique to provide improved performance verses power consumption relative to conventional grounded substrate approaches. This bias generator may start operating as
low as Vcc = 3 volts on some devices while others
may require Vcc = 4 volts in order to get adequate
substrate bias. Until the substrate reaches the proper
bias, the 3870 will not be released from the reset
state. The final condition required is that the clocks
of the 3870 must be functioning. Typically the clocks
will start to function at Vcc equal to 3 to 3.5 volts
but since the part is tested at 4.5 volts MOSTEK cannot guarantee any operation below 4.5 volts. The
output of the delay circuit in Figure 7 will stay low
until the clocks start to function. If the input to the
delay circuit is high, typically after 100 cycles of the
WR ITE clock (800 cycles of the external clock)
the output of the delay circuit will go high allowing
the 3870 to begin execution.
If Vcc falls to ground for at least a few hundred nanoseconds the output of the delay circuit will go low
immediately and the 3870 will reset.
The internal logic may detect a valid Vcc, bias and
clocks at Vcc = 3.5 volts and allow the 3870 to start
executing after the time delay. With a slowly rising
power supply the part may start running before Vcc
is above 4.5 volts which is below the guaranteed
voltage range. When power-on-clear is required with a
slowly rising power supply, an external capacitor
must be used on the RESET pin to hold it below 0.8
volts until Vcc is stable above 4.5 volts. (Note: The
option to disconnect the internal pull-up resistor on
RESET is available which allows the use of a larger
external pull-up resistor and a small capacitor on
RESET.)
In many applications, it is desirable if the unit does
an automatic power-on-clear, but not mandatory. The
unit will have a RESET push button and if the unit
does not power-up correctly or malfuctions because
of some disturbance on the Vcc line, the operator will
simply press RESET and restore normal operation. It
is for these applications that the internal power-onclear circuitry was designed.
In some applications it is required that the microcomputer continue to run properly without operator
intervention after brown-outs, power line disturbances, electrical noise, computer malfunction
due to a programming bug or any other disturbance
except a catastrophic failure of some component.
Once concept used to keep computers running is that
of the "WATCHDOG TIMER". The computer is programmed to periodically reset the watchdog timer
during the normal execution of its program (this is
easily done in the 3870 as its normal application is in
338
some control function which is typically periodic).
As long as the computer continues to execute its
program the watchdog timer is continually reset and
never times out. Should the computer stop executing
its program for whatever reason, the watchdog timer
will time out producing a RESET pulse to the CPU
re-starting execution. This is a very positive way to
assure that the computer is doing its job, i.e., executing the program. It is important that the software
driving the watchdog timer test as many functional
blocks (timer, ALU, scratchpad RAM, and Ports) of
the 3870 as possible before reseting the watchdog
timer. This is because operation of the 3870 with an
out of spec power supply may allow some of the
functions to operate correctly while other functions
are not operable.
MOSTEK can guarantee co~rect operation of the
3870 only while the Vcc voltage remains within its
specified limits. If proper ?~eration of the 3870 must
be guaranteed after a disturbance on the Vcc line,
then an external circuit must be used to monitor the
Vcc line and produce a "F'fESEf" to the 3870 whenever
Vcc is out of the specified limits.
A related characteristic to power-on-clear is the
Startup time of the basic timing element. The LC,
and RC, oscillators begin to function almost
immediately once Vcc is high enough to allow the onboard oscillator to operate (Vcc = 3.5). Operation
with a crystal is partly mechanical and some start
time is required to get the mass of the crystal into
vibrational motion. This time is basically dependent
on the frequency (mass) of the crystal. 4 MHz crystals typically require about 2-3 mSec to start while 1
MHz crystals require 60-70 mSec to start oscillating.
Of course, this time may vary greatly from crystal to
crystal and is also a function of the power supply rise
time characteristic, however, the high frequency crystals start faster and are definately recommended
(i.e., 3-4 MHz).
The condition of the port pins during the power-onclear sequence is often asked. The port pins or the
STROBE line cannot be specified until Vcc reaches
4.5V and the 3870 enters the RESET state. Before
this, the port pins may stay at Vss, may track Vcc as
it rises, or they may track Vcc part way up then
return to Vss (Ports 4 & 5 will go to Vcc once the
clocks are running and the 3870 has sufficient Vcc to
properly operate the internal control logic and I/O
ports).
External Reset
When RESET is taken low the content of the Program Counter is pushed to the Stack Register and
then the Program Counter and the ICB bit of the
W Status Register are cleared. The original Stack
Register content is lost. Ports 4, 5, 6 and 7 are loaded
INTERRUPT SEQUENCE
Figure 6
FREEZE CYCLE
,---J"-.,
I--I~- - B - - - + t - - I - o - - C + O + E - j - F - r G
WRITE
EXT INT OR
~1-lA
1-1
I I
TIMER INTERRUPT
INT REQ
(INTERNAL)
iff---I
I .- - - - -iJ- .J
I
I [,; ---l
POWER ON CLEAR BLOCK DIAGRAM
Figure 7
SCHMITT
TRIGGER
WRITE
WRITE
FORCE
RESET
WRITE
TO INTERNAL
3870 LOGIC
RESET STATE=1
339
with H '00'. The contents of all other registers and
ports are unchanged or undefined. When RESET is
taken high the first program instruction is fetched
from ROM location WOOO'. When an external reset
of the 3870 occurs, PO is pushed into P and the old
contents of P are lost. It must be noted that an
external reset is recognized at the start of a machine
cycle and not necessarily at the end of an
instruction. Thus if the 3870 is executing a multicycle instruction, that instruction is not completed and
the contents of P upon reset may not necessarily be
the address of the instruction that would have been executed next. It may, for example, point to an immediate operand if the reset occurred during the
second cycle of a LI or CI instruction. Additionally,
several instructions (JMP, PI, PK, LR PO, 0) as well
as the interrupt acknowledge sequence modify PO
in parts. That is, they alter PO by first loading one
part then the other and the entire operation takes
more than one cycle. Should reset occur during this
modification process the value pushed into P will
be part of the old PO (the as yet unmodified part)
and part of the new PO (already modified part). Thus
care should be taken (perhaps by external gating) to
insure that reset does not occur at an undesirable
time if any significance is to be given to the contents
of P after a reset occu rs.
program ROM is prevented from driving the data bus.
In this mode operands and instructions may be
forced externally through port 5 instead of being
accessed from the program ROM. When TEST is
in either the TTL state or the high state, STROBE
ceases its normal function and becomes a machine
cycle clock (identical to the F8 multi-chip system
WR ITE clock except inverted).
Timing complexities render the capabilities associated with the TEST pin impractical for use in a
user's application, but these capabilities are thoroughly sufficient to provide a rapid method for thoroughly testing the 3870.
3870 Clocks
The time base for the 3870 may originate from one
of four sources.
The four configurations are shown in Figure 8. There
is an internal 26pF capacitor between XTL 1 and
GND and an internal 26pF capacitor between XTL 2
and G N D. Thus external capacitors are not neccesarily required. In all external clock modes the external time base frequently is divided by two to form
the internal q, clock.
Crystal Selection
Vcc Decoupling
The 3870 family devices have dynamic circuitry internally which requires a good high frequency decoupling capacitor to surpress noise on the Vcc line.
A .01 J.lF or .1 J.lF ceramic capacitor should be placed
between Vcc and ground, located physically close to
the 3870 device. This will reduce noise generated by
the 3870 to about 70-100mVolts on the Vcc line.
The use of a crystal as the time base is highly recommended as the frequency stability and reproducability from system to system is unsurpassed. The
3870 has an internal divide by two to allow the user
of inexpensive and widely available TV Color Burst
Crystals (3.58MHz). The following crystal parameters
and vendors are suggested for 3870 applications:
Parameters
Test Logic
Special test logic is implemented to allow access
to the internal main data bus for test purposes.
In normal operation the TEST pin is unconnected
or is connected to GND. When TEST is placed at a
TTL level (2.0V to 2.6V) port 4 becomes an output
of the internal data bus and port 5 becomes a
wired-OR input to the internal data bus. The data
appearing on the port 4 pins is logically true whereas
input data forced on port 5 must be logically false.
When TEST is placed at a high level (6.0V to 7.0Vl.
the ports act as above and additionally the 2K x 8
a) Parallel Resonance, Fundamental Mode AT-CUT
b) Frequency Tolerance measured with 18pF load
(0.1% accuracy). Drive level10mW.
c) Shunt Capacitance (Co) = 7pF max.
d) Series Resistance (Rs)
f
f
f
f
f
= 1MHz
= 2MHz
= 3M Hz
= 3.58MHz
= 4MHz
Rs = 550 ohms max.
Rs = 300 ohms max.
Rs = 150 ohms max. *
Rs = 150 ohms max.
Rs = 150 ohms max.
Holder
HC-6
HC-33
HC-6
HC-18
HC-25
HC-33
*HC-18 or HC-25 may not be available at 3MHz.
340
CLOCK CONFIGURATION
Figure 8
VCC
RC Mode
~ E2JR
~
-
Cextemal
--:-- (optional I
± 2.6pF
C = 26.5 pF
External Mode
Crystal Mode
Open
External
Clock
ATCutl-4MHz
+ Cextemal
FREOUENCY VRS RC
LC Mode
XTL 1
I\.
XTL 2
L
3~rt~-+~~.r~~-~~~r+4-~4-~~~~
'"
~--1~-- ~
Cexternal (optional)
MHz
Minimum L = 0.1 mH
Minimum Q = 40
1
MAXIMUM (4.5. 5.5V, O°C .70'C))Y''-t--¥H-++-
I/ - + + - H I- TYPICAL ITYP'IClL ~N'IT In ~C~ ~ 5J. T~ =' 25'C)i';:'--I--7H
HH-++-I-+
I I
I
Maximum Cexternal
=
30pF
-+-+-+-I--I--++-
MINIMjUM 14.5V ·5.5V, O°C· 70°C),/
I'll I
I I I I ' I I ' I
C = 13pF ± 1.3pF + Cexternal
IR) ICINTERNAL + CEXTERNALl
UNIT TO UNIT VARIATION
VARIATION FROM
= ± 12%
4.5 to 5.5V
REFERENCED TO 5V = +7% A%
VARIATION FROM O"C TO 70°C
REFERENCED TO 25°C = +6% ·9%
TOTAL VARIATION NOT CONSIDERING
VARIATION IN EXTERNAL COMPONENTS = ± 25%
Suggested Crystal Vendors
a) Electro·Dynamics
5625 Foxridge Drive
Mission, Kansas 66201
913·262·2500
b) CRYSTEK
1000 Crystal Drive
Ft. Myers, Florida 33901
813·936·2109
c) W.T. Liggett Corp.
1500 Worcester Rd.
Section 30
Framingham, MA 01701
617·620·1150
e) Electronic Crystals Corp.
1153 Southwest Blvd.
Kansas City, Kansas 66103
913·262-1274
d) Erie Frequency Control
453 Lincoln Street
Carlisle, Penn 17013
717·249-2232
f) M-TRON Industries
P.O. Box 630
100 Pouglas Avenue
Yankton, South Dakota
605-665-9321
341
w
.j::Io
N
::!'!s
co
"
~ W
co 00
CC'-.j
o
OUTS
r-----------------------~·~IADC
"'C
7
::0
oG')
INS"?
::0
)
I
i
"
"ILNK
~
OUTS 6
w
S
"
INS 6
z
G')
S
o
PO)
OU TS
INS*0,1,4,5
LISU
~
SCRATCHPAD
REGISTERS
a
AS
NS
XS
--, 0 C II
Ie.
1', ,011...
1+-
-LR
PORTS
(4 )
INVERTING
ASD
LR
o
I/O
-{>o-
ROM
MEM
2048 x 8
0,1,4,5
ACCUMULATOR
I~
:;("~ ..
I
T."
",,~(PO
*
COM
I C
r,
I~-±---+-- 05*
5L I
SL4
5 RI
SR4
ROM
MEM
FROM
76
I~
TIMERI
The value of the exterrliJl Interrupt mput IS loaded to
Bit 7 of the ilCClJmulLltor (with Bits 0 through 6 loaded
with leros) when the instruction 'INS 6' IS executed. This
InStfuctlon <.llso sets Sfi.ltuS.
H'OAO'
RESET
Reset T r ilnsfers PO to P and
II PO, P, DC, and DCl are 12 bit regISters
then clears PO, ICB Bit of W,
f
EXTERNAL
eM*
These IIlstr uctlOns set status
H'020'
H '000'
2048
7
OCTAL
INTERRUPT
and Ports 4,5,6 and 7.
Note
The instructions PI
~md
PK Jre shown
(Pll, PI2 I
Add Carry
LNK
A-IA) + CRy
19
1/0
1/0
1/0
1/0
Add Immediate
AI
A-(A) + H
2411
1/0
1/0
110
1/0
And ImmedIate
NI
A __ (AlI\H'II'
2111
Clear
CLR
A--H'OO'
70
'II'
1/0
1/0
Compare Immediate
CI
H'p't (A) + 1
2511
Complement
COM
A.tA). H'FF'
18
1/0
ExclUSive or ImmedIate
XI
A .. (A) , H'II'
2311
1/0
Increment
INC
A_(A) + 1
1F
Load Immediate
LI
A_H'!I'
2011
110
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
7,
load Immerhate Shori
LIS
A_H' 01'
OR Immediate
01
A_(A) V H
Shift Left One
SL
Shift lldt 1
Shift left Four
SI
ShIfT Right One
SR
Shift Right Four
SR
Shift Rlqh! 4
2211
1/0
1/0
13
1/0
1/0
Shift Left 4
15
1/0
1/0
ShIft RighI 1
12
1/0
14
1/0
'II'
BRANCH INSTRUCTIONS In all conditional branches PO-( PO) + 2 if the test condition is not met. Execution is complete
in 3 short cycles.
MACHINE
COOE
MNEMONIC
OPERATION
OP COOE
Branch on Carrv
BC
Branch on POSITIve
BP
OPERAND
FUNCTION
PO~POI 111 H'aa' "CRY
Zero
t TEST CONDITION
Iz~~ol
(RY \
S~~N I
Te~t
SIGN
B2aa
If
BNC
Staa
91aa
PO. (POI + l' H'aa'
92aa
a
98aa
BNO
BNZ
84aa
0
a
PO+(POI+1+ H'aa'
If ZERO
Branch If False
H'aa'
8M
.IOVR
Branch If Not Zero
I
1 + H'aa '
-+
II CARRY
Branch If No Overflow
STATI.,IS 81TS
CRY
ZERO
d any test ,s true
If SIGN
Branch If No Carr V
OVR
1
PO-(POI
BT
Branch If Negative
JJS
(2MHl 1111
1
PO-{POl + 1
BZ
Branch on True
CYCLES
SHOflT
LONG
8laa
SIGN
Branch on Zero
1
BYTES
94<1a
0
9taa
BF
If all false teSt hIlS
PO_(POI+l+ H'aa' II
Branch If ISAR (LoW€d 11
8Faa
ISARLn
,
PO_(POH2JI ISARL..:
Branch Relative
BR
PO. (PO)+l+ H'aa'
90aa
Jump
JMP
PO_H'aaaa'
29a
t
I nternal Clock Period
2tO
WRITE
tw
Internal WR ITE Clock Period
4t
6t
I/O
tdl/O
Output delay from
internal WR ITE Clock
tsl/O
Input Setup time
to WR ITE Clock
1000
tl/O-s
Output valid to STROBE
Delay
3t
-1000
3t<»
+250
tsl
STROBE Low Time
8t
-250
12t'»
+250
to(lNT)
XTL 1
XTL 2
to(EX)
tEX(H)
0
UNJT
NOTES
Short Cycle
Long Cycle
1000
ns
50pF plus
one TTL load
ns
I/O load =
50pF + 1 TTL
STROBE Load=
50pF + 3 TTL
STROBE
RESET
EXTINT
tRH
tEH
RESET Hold Time, Low
EXT I NT Hold Time,
Active and I nactive State
346
6t<»
+750
6t<» +
750
2t<»
ns
ns
ns
To trigger
interrupt
To trigger
timer
CAPACITANCE
T A = 25°C, f=2MHz
SYMBOL
PARAMETER
MIN
MAX
7
Input Capacitance: I/O Ports, RESET,
CIN
UNIT
pF
EXTINT, RAMPRT, TEST
Unmeasured
Pins
Grounded
20.5
Input Capacitance: XTL 1, XTL2
CXTL
NOTES
32.5
pF
DC CHARACTERISTICS - See Figures 12-17 for typical curves.
TA = O°C to 70°C, VCC = +5V' 10%, I/O POWER DISSIPATION.;; 100mW
SYMBOL
PARAMETER
ICC
Power Supply Current
MIN
TEST CONDITIONS
MAX
UNIT
85
rnA
Outputs Open
400
rnW
Outputs Open
2.4
5.8
V
-0.3
0.6
V
PD
Power Dissipation
VI HEX
External Clock
Input High Level
VILHEX
External Clock
Input Low Current
IIHEX
External Clock
Input High Current
100
!1A
VIHEX = VCC
IILEX
External Clock
I nput Low Cu rrent
·100
!1A
VILEX = VSS
2.0
5.8
V
2.0
13.2
V
-·0.3
0.8
V
VIH
VIHOD
Input High Level
PortS,RESET', EXT INT'
Open Drain Input
High Level
VIL
I nput Low Level
Ports, RESET', EXT INT 1
IlL
Input Low Current
Ports, RESET2, EXT INT2
Leakage Current
IL
Open dram ports, RAMPRT
RESET3. EXT INT3
10H
Standard po,ts, REID2
EXT INT2
Output High Current
rnA
VI L =O.4V
+10
-5
!1A
VIW13.2V
VIN=O.OV
-8.5
!1A
!1A
rnA
rnA
rnA
-1.6
-100
-30
-0.1
10HDD
OUTPUT High Current
Direct Drive Ports
10L
Output Low Current
10 ports
-1.5
VOW2.4V
VOW3.9V
VOH = 2.4V
VOW1.5V
VO H .7V
1.8
rnA
VOL =O.4V
10HS
STROBE Output High Current
-300
!1A
VOW2.4V
10LS
STROBE Output Low Current
5.0
rnA
VOL = O.4V
* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1.
2.
3.
4.
RESET and EXT INT have internal Schmit triggers giving minimum .2V hysteresis.
RESET or EXT INT programmed with standard pull·up
RESET or EXT INT programmed without standard pull·up
Power dissipation for 1/0 pins is calculated by~(Vcc . Vill !I IlL! I +~(VcC . VOHI
II 10H II +~(VOlI
(lOll
347
TIMER AC CHARACTERISTICS
Definitions:
Error = I ndicated time value - actual time value
tpsc
= tx Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±6t
Cumulative interval error, free running (Note 3) ..................................... 0
Error between two Timer reads (Note 2) ................................... ±(tpsc + t to -(tpsc +t to -(tpsc + 7t to -8t
Load Timer to stop Timer error (Note 1) ........................... +t to -(tpsc + 2t to -(tpsc + 8t to -9t
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) ..................................+t to -(tpsc +2t
Event Counter Mode:
Minimum active time of EXT INT pin ............................................2t
Minimum inactive time of EXT INT pin .......................................... 2t
Notes:
1. All times which entail loading, starting, or stopping the Timer are referenced from the end
of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the last machine
cycle of the IN or INS instruction.
3. All times which entail the generation of an interrupt request are referenced from the start
of the machine cycle in which the appropriate interrupt request latch is set. Additional
time may elapse if the interrupt request occurs during a privileged or multicycle instruction.
4.
348
Error may be cumulative if operation is repetitively performed.
External Clock
Internal 'I' Clock
I/O Port Output
,['"''
t=
STROBE
tSL
---:1
RESET
EXTINT
=__ ' "
rcp
BITJ'O
rcp
BIT 2' I
r\Jote: All measurements are referenr.ed to VIL max., VIH min., VOL max., or VOH min.
349
INPUT/OUTPUT AC TIMING
Figure 11
INTERNAL
WRITE
CLOCK
* CYCLE TIM ING
SHOWN FOR
4MHz EXTER NAL
CLOCK
CYCLE TIMING
DEPENDS ON INSTRUCTION
n
2/J.S*
1
IN OR
INS
OP CODE
FETCHED
3fJS*
I
PORT ADDR.
PLACED ON
DATA BUS
PORT PINS
J
3fJS*
PORT DATA
DRIVEN ON TO
DATA BUS
X
~
1
11"-
NEXT
OPCODE
FETCHED
D<
1fJS
SET UP
MAX.
tSIO
A. INPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
CYCLE TIMING
14------;*I------+OO~------~---~--.. DEPENDS ON INSTRUCTION
3fJS*
OUTOR
OUTS
OP CODE
FETCHED
PORT ADDR.
ON DATA
BUS
ACCUMULATOR
CONTENTS
ON DATA BUS
NEXT
OP CODE
FETCHED
PORT PINS
STAYS LOW
STROBE
(ACTIVE FOR PORT 4 ON L Y)
FOR TWO WRITE
CYCLES
500n,* MIN.
tl/O-S
B. OUTPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
OUTS 0,1
FETCHED
ACC DATA
ON BUS
PORT PINS
1fJS
MAX
C. INPUT ON PORT 0 OR 1
350
D. OUTPUT ON PORT 0, 1
STROBE SOURCE CAPABILITY
(TYPICAL AT VCC = 5V, TA = 25°C)
Figure 12
-15
S
0
U
R
C
E
C
U
R
R
E
N
T
-10
I'
"- .........
~
.......
-5
M
A
~
.......
I
"- .......
.......... !Io..
.......... ~
r-..... ""2
3
r"o ~
4
5
4
5
OUTPUT VOLTAGE
STROBE SINK CAPABILITY
(TYPICAL AT VCC = 5V, TA
= 25°C)
Figure 13
S
I
N
K
C
U
R
R
E
N
T
+100
I
+50
M
A
./
-'-
l/
/
~
1
~
~~
~
2
3
OUTPUT VOLTAGE
351
STANDARD I/O PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V, T A = 25° C)
Figure 14
-1.5
S
0
U
R
C
E
-
I' ......
-1.0
C
U
R
R
E
N
T
M
A
~
c----
~
'-
"- ......
,
~
"-
-.5
I'
"""""'"
~
~
~ .....
"",
4
3
2
~
"5
OUTPUT VOLTAGE
DIRECT DRIVE I/O PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V, TA = 25°C)
Figure 15
S
0
U
R
C
E
C
U
R
R
E
N
T
-10
- .. -...r-..
~
-5
r--
........
.........
~
.....
,
.....
M
A
,
i '!III...
"~
1
2
3
OUTPUT VOLTAGE
352
4
5
I/O PORT SINK CAPABILITY
(TYPICAL AT VCC = 5V, TA = 25°C)
Figure 16
+60
S
I
N
K
C
U
R
R
E
N
+50
+40
+30
l,,,,o000o ~
T
M
+20
......
A
+10
~
~
~
".
i..o-""
~~
~~
~ ~
2
4
3
5
OUTPUT VOL TAGE
MAXIMUM OPERATING TEMPERATURE VS. I/O POWER OISIPATION
Figure 17
100
--~"'"
50
""""
~
~F
Ie J""""oo
to--. ....
100
200
300
400
500
CERAfVt"ic
r--.
600
~
r--
.......
1000
POI/O MW
353
PACKAGE DESCRIPTION: 40-Pin Dual In-Line Ceramic Package
I
I
2000 , 020
=fr=~~
~/L D---~Im [1
Symbolization Area For
L-
Identification of Pin 1
~
raiD
! 001
PACKAGE DESCRIPTION 40-Pin Dual-in-Line Plastic Package
r
---------Z.D40
------------10'
~
ymbolization Area for Identification of Pin 1.
1~
~w-w-w-~~~~-W-W-L~~~~~~W-W-WL~,~11~
-~-T
180
21
40
B
J~l
L
I ..jf.-018
--l I_PIN
~ ~:06():000Z
SAIICING (SEE NOTE I)
-tZ5MIN
10-- 6Z5±=002S---\1
~_010
ORDERING INFORMATION
PART NO.
MK3870N/14XXX
M K3870P /14XXX
354
PACKAGE TYPE
Plastic
Ceramic
TEMPERATURE RANGE
O°C to +70°C
O°C to +70°C
APPENDIX A
ORDERING INFORMATION
355
Custom M K3870 Option Specifications
Paper Tape
The custom MK3870 program may be transmitted to
Mostek in any of the following media, listed in order
of preference:
1)
PROMs from the EMU-70
2)
Punched paper tape
3)
AID-80F Flexible Disk
Card Deck (IBM 80 column cards)
4)
Punched paper tapes (1" wide, 8 level ASCII) will be
accepted. The tape must contain the absolute object
output from the above mentioned F8 assemblers. Paper
object tapes in absolute format generated by the "D"
(dump) command of DDT-2 or the dump command of
the AI D-80F (F8 debug option) are also acceptable if
the entire memory space is dumped continuously.
Tapes may also be punched using the DATA DECK
FORMAT. They must contain 80 characters per record
with a CR (carriage return) and LF (line feed) separating each record. The tape must be clearly labeled with
customer name, and format used. Fan fold tape is preferred. Tape transparency should be limited to 60%
transmissivity (40% opaque). Specifically, thin yellow
or white tape is error prone on photo-electric readers
and must not be used.
The program may be specified in the following forms:
PROMS with correct object code in each location
OBJECT CODE produced by one of Mostek's assemblers.
XFOR-50/70 Fortran IV Cross Assembler, SDB50/70 resident assembler (ASMB-50/70), AI D80F F8 Cross-Assembler (FZCASM)
OBJECT CODE produced by the dump command
from any of Mostek's F8 development hardware
(SDB-50/70, AID-80F).
DATA DECK FORMAT as described in the Data
Deck section
A completed cover letter (See Fig. A-l) must be attached. The information should be properly packed
and mailed prepaid and insured to:
MOSTEK Corporation
Microcomputer Product Marketing
1215 West Crosby Road
Carrollton, Texas 75006
A second copy of the cover letter should be mailed
separately to the above address.
FLEXIBLE DISKS
FLEXIBLE DISKS (Floppy Disks) produced on the
Mostek AI D-80F development station may be submitted. The format must be the absolute object output
from the assemblers, or an object dump using the
memory dump command (F8 Debug Option). The disk
must be clearly labeled with the format of the data
(object, or object dump) and the customer's name.
Punched Card Deck
Standard 80 column punched cards must be used.
They must be punched in IBM 029 code. The deck
must contain two type of cards:
COMMENT CARDS
DATA CARDS
PROMS
Comment Cards
2708 type PROMs, programmed with the customer
program (positive logic sense for addresses and data)
may be submitted. The PROMs must be clearly marked
to indicate which PROM corresponds to address space
000 7FF and which PROM corresponds to address
space 800 FFF. See Fig. A-2 for marking. Include a
three-letter customer ID on each PROM. After the
PROMs are removed from the EMU-70, they must be
placed in a conductive IC carriers and securely packed.
Comment Cards must have an asterisk (*) in column 1.
The remaining 79 columns may be any character. Comment Cards may be placed anywhere throughout the
data deck.
Figure A-2
~
~
000
800
xxx
356
xxx
XXX
~
Customer ID
Data Cards
These cards specify the actural ROM data. All fields
are right justified.
COLUMN 1:
C (the letter C)
COLUMN 2-9:
ADDR
BYTE
COLUMN 10-12:
COLUMN 14-16:
DATA 1
COLUMN 17-19:
DATA 2
COLUMN 20-22:
DATA 3
3870 ORDERING INFORMATION
DATE~
_______________________
CUSTOM E R PO NUMB ER _____________________
CUSTOMERNAME _________________________________
ADDRESS ______________________________________
CITY __________________
STATE ________________
ZIP ________________
COUNTRY ______________________________________
PHONE ____________________________ EXTENSION _________________________
CONTACT ____________________________________________________________
CUSTOMERPARTNUMBE~R
________________________________________________
OPTIONS:
EXTERNAL INTERRUPT:
Pull-Up 0
No Pull-Up 0
RESET:
Pull-Up 0
No Pull-Up 0
OPEN DRAIN
DRIVER PULL-UP
PORT OPTIONS:
STANDARD TTL
P4-0
P4-1
0
D
P4-2
CJ
P4-3
CJ
0
0
D
0
CJ
CJ
0
CJ
P4-4
0
0
0
P4-5
CJ
P4-6
CJ
CJ
D
D
D
P4-7
CJ
D
P5-0
CJ
CJ
D
P5-1
0
D
P5-2
0
P5-5
D
D
CJ
CJ
P5-6
D
0
0
0
P5-7
0
CJ
P5-3
P5-4
D
CJ
CJ
0
0
D
D
D
D
PATTERN MEDIA
DPROMS
(Customer can send in two extra PROM's,
MOSTEK will program the customer's
code on these PROM's for code verification
in the Emulator-70.)
CJPAPER TAPE (DATA DECK)
0
PAPER TAPE (OBJECT)
0
CARD DECK (DATA DECK)
D
DISKETTE (OBJECT)
357
THESE ITEMS MAY AFFECT COST
BRANDING REQUIREMENT (If any, 10 Alpha-numeric digits allowed)
PROTOTYPE QUANTITY (10 pieces at no charge - higher quantity extra charge)
WAIVE PROTOTYPES (Customer accepts liability for all work in process)
Yes
SIGNATURE
TITLE
358
No
COLUMN 76-78:
COLUMN 77-79:
DATA 21
DATA 22 or
SEQUENCE NUMBER
ADDR is the address of the first byte of data (DATA
1) contained on that card. Successive data bytes read
from that card will be placed in successively greater address locations. BYTE is the number of data bytes to
be read from that card (1 to 22). I f sequence numbers
are used, the maximum number of bytes per card is 21.
The base for ADDR and BYTE may be either decimal
or hex but both must be the same. Data may be either
in decimal or hex regardless of the base used for
ADDR and BYTE. The base for sequence numbers (if
they are used) is always decimal. The bases must be
consistent throughout the deck. Data cards need not
occur in order of increasing or decreasing addresses.
Any unspecified address will be filled with zero. Any
unpunched field will be read as a zero. If two data
cards specify data for the same address, the one encountered second in the deck will override the first.
Verification Media
All original pattern media (PROMs, paper tape, etc.)
are filed for contractural purposes and are not returned. Two copies of computer listings printed during the
creation of the custom mask pattern are returned. One
copy may be kept by the customer. The other copy
should be checked thoroughly, signed, and returned to
Mostek. The signed I isting constitutes the contractual
agreement for creation of the customer mask. Though
the computer I isting serves as the actual verification
media, Mostek will program 2708 PROMs programmed
from the data file used to create the custom mask to
aid in the verification process. If programmed PROMs
are desired, two blank 2708 type PROMs must be provided by the customer.
A portion of an example deck is shown.
*
3870 DATA DECK
*
MOSTEK CORP, EXAMPLE APPLICATION
*
ADDR/BYTE ARE IN DECIMAL
*
DATA IS IN HEX
C 0 8 20
C 8 8
OB
1B 28 03
C 16 8 04
*
FF
29 01
54 34 56
71
B6
F3 4C 25
2E
94
00
START OF SUBROUTINE ALPHA
C 1096 4
20 32 7C 53
C 1100 4
52 47
C 1104
07
29 06
359
360
Fa MICROCOMPUTER DEVICES
Single-Chip Microcomputer MK3872
FEATURES
o
o
Software compatible with F8 family
4032 x 8 mask programmable ROM
o
o
64 byte scratchpad RAM
o
Standby option for executable RAM including:
-Low standby power, less than 8.2mW
-Minimum 2.2V standby supply voltage
-No external components required to trickle
charge battery
o
o
o
o
o
o
o
SINGLE CHIP 3870 MICROCOMPUTER FAMILY
64 additional bytes of executable RAM addressable by program counter or data counter
1/0<=:>8<=:>1/0
MK 3870
1/9<=:>
WI/O
F8 FAMILY \
110<=:>
110<=:> '--_ _-'
32 bits (4 ports) TTL Compatible I/O
Programmable binary timer
-Internal timer mode
-Pulse width measurement mode
-Event counter mode
I/OW
P
E
R
External interrupt
I
Crystal, LC, RC, external, or internal time base
P
H
Low power (285mW typ.)
Single +5 volt ± 10% power supply
Same pinout as MK3870
SERIAL I/O
E
IIOW
M
E
11O<=:)
<=)~
11O<=)
1 -_ _-J
R
L
S
R
Y
A
>
<
r - - - -_ _
GENERAL DESCRIPTION
I/OW
The MK3872 is a complete 8-bit microcomputer
on a single MOS integrated circuit. The 3872 can
execute the F8 instruction set of more than 70
commands, allowing expansion into multi-chip
configurations with software compatibility. The
device features 4032 bytes of ROM, 64 bytes of
scratchpad RAM, 64 bytes of executable RAM,
a programmable binary timer, 32 bits of I/O, and a
single +5 volt power supply requirement. Utilizing
ion-implanted, N-channel silicon gate technology
and advanced circuit design techniques the singlechip 3872 offers maximum cost-effectiveness in a
wide range of control and logic replacement applications. The 3872 is an expanded memory version of
the 3870 single chip microcomputer. The 3872 is
identical to the 3870 in the following areas: instruction set, architecture, AC and DC characteristics, and
pinout. The only change is in the memory expansion
along with the appropriate memory address registers.
110<=)
PIN CONNECTIONS
'veB
i>O=Q"______ 3
'vsoIPO=l'_4
PO=2_5
m ___ 6
ffiQB1: _ _ 7
P4,o_e
23 __
m
22_~
'PROGRAMMABLE PIN FUNCTION DEPENDS ON DEVICE
OPTION (STANDBY MODE DEVICE OR STANDARD DEVICE).
361
PIN NAME
po-o - J5O-7
P1-0 - 'P'f:f
P4-0 - P4-7
P5-0 - P5-7
STROBE
EXTINT
RESET RAMPRT
TEST
XTL 1, XTL 2
Vee, GND
VSB
VBB
DESCRIPTION
I/O Port 0
I/O Port 1
I/O Port 4
I/O Port 5
Ready Strobe
External Interrupt
External Reset, RAM
Protect
Test Line
Time Base
Power Supply Lines
Standby Power
Substrate Decoupling
TYPE
Bid irectional
Bid irectional
Bid irectional
Bidirectional
Output
Input
Input
Input
Input
Input
Input
Input
FUNCTIONAL PIN DESCRIPTION
PO-O-P0-7, Pl-0-Pl-7, P4-0-P4-7, and P5-0-P5-7
are 32 lines which can be individually used as either
TTL compatible inputs or as latched outputs.
STROBE is a ready strobe associated with I/O Port 4.
This pin which is normally high provides a single low
pulse after valid data is present on the P4-0-P4-7
pins during an output instruction.
RESET - RAMPRT may be used to externally reset
the 3872. When pulled low the 3872 will reset. When
allowed to go high the 3872 will begin program execution at program location H '000'. Additionally
when RESET - RAMPRT is brought low all accesses
of the executable RAM are prevented and the RAM is
placed in a protected state for powering down VCC
without loss of data when the STANDBY option is
selected.
EXT I NT is the external interrupt input. Its active
state is software programmable. This input is also
used in conjunction with the timer for pulse width
measurement and event counting.
XTL 1 and XTL 2 are the time base inputs to which
a crystal (1 to 4MHz), LC network, RC network, or
an external single-phase clock may be connected.
TEST is an input, used only in testing the 3872. For
normal circuit functionality this pin is left unconnected or may be grounded.
VCC is the power supply input (+5V± 10%).
VSB is the RAM standby power supply input if the
standby option is selected (+5.5V to +2.2V).
3870 ARCHITECTURE
This section describes the basic functional elements
of the 3872 as shown in the block diagram of Figure
1. A programming model is shown in Figure 2.
Main Control Logic
The I nstruction Register (I R) receives the operation
code (OP code) of the instruction to be executed
from the program ROM via the data bus. During all
OP code fetches eight bits are latched into the I R.
Some instructions are completely specified by the
upper 4 bits of the OP code. In those instructions
the lower 4 bits are an immediate register address
or an immediate 4 bit operand. Once latched into the
I R the main control logic decodes the instruction
and provides the necessary control gating signals to
all circuit elements.
ROM Address Registers
There are four 12 bit registers associated with the
4K x 8 ROM and 64 x 8 RAM. These are the Program
Counter (PO), the Stack Register (Pl, the Data Counter (DC) and the Auxiliary Data Counter (DC1). The
Program Counter is used to address instructions or
immediate operands. P is used to save the contents of
PO during an interrupt or subroutine call. Thus, P
contains the return address at which processing is
to resume upon completion of the subroutine or the
interrupt routine.
The Data Counter (DC) is used to address data tables.
This register is auto-incrementing, Of the two data
counters only DC can access the memory. However,
the XDC instruction allows DC and DCl to be
exchanged.
Associated with the address registers is a 12 bit
Adder/lncrementer. This logic element is used to
increment PO or DC when required and is also used to
add displacements to PO on relative branches or to
add the data bus contents to DC in the ADC (add
data counter) instruction.
4032 x 8 ROM
The microcomputer program and data constants
are stored in the program ROM. When a ROM access
is required, the appropriate address register (PO or
DC) is gated onto the ROM address bus and the ROM
output is gated onto the main data bus. The first
byte in ROM is location zero.
64 x 8 Executable RAM
VBB is the substrate decoupling pin. A .01 microFarad capacitor is required to provide substrate
decoupling. It is only used when standby option is
selected.
362
The upper 64 bytes of the total 4096 byte memory
of the 3872 is RAM memory, The first byte is at address 4032 decimal (FCO hex). As with the ROM
memory the RAM memory may be accessed by the
PO and DC address registers. It may be written via
the STORE (Sn instruction. It may be read via the
LOAD (LM) instruction. Additionally instructions
may be executed from the RAM. A mask programmable standby power option is available whereby the
64x8 RAM remains powered and protected so that
its contents are saved during a loss of the normal
circuit power supply.
via IS. This makes it easy to reference a buffer consisting of contiguous scratchpad bytes. For example,
When the low order octal digit is incremented or
decremented IS is incremented from octal 27 (0 '27')
to 0 '20' or is decremented from 0 '20' to 0 '27'.
This feature of the IS is very useful in many program
sequences. All six bits of IS may be loaded at one
time or either half may be loaded independently.
Scratchpad and IS
Scratchpad registers 9 through 15 (decimal) are
given mnemonic names (J, H, K, and Q) because of
special linkages between these registers and other
registers such as the Stack Register. These special
linkages facilitate the implementation of multi-level
interrupts and subroutine nesting. For example,
the instruction LR K, P stores the lower eight bits of
the Stack Register into register 13 (K lower or K L)
and stores the upper three bits of P into register 12
(K upper or KU) The scratchpad is not protected
with the standby power option.
The scratchpad provides 64 8-bit registers which may
be used as general purpose RAM memory. The
Indirect Scratchpad Address Register (IS) is a 6 bit
register used to address the 64 registers. All 64
registers may be accessed using IS. In addition the
lower order 12 registers may also be directly addressed.
IS can be visualized as holding two octal digits. This
division of IS is important since a number of instructions increment or decrement only the least significant 3 bits of IS when referencing scratchpad bytes
Arithmetic and Logic Unit (ALU)
After receiving commands from the main control
MK 3872 BLOCK DIAGRAM
Figure 1
XTL 1
VSR
XTL2
~
EXTINT
RAMPRT
INTERRUPT
64X 8 RAM
4032 X 8
ROM
MEMORY
ADDRESS
M
A
I
N
PO; P
M
E
M.
0
R
y
DC,DCI
\!
:'[1'
1~
:.\':
?{::
f,",
"
MAIN
CONTROL
LOGIC
~~~
,.
-:;';,
:'}~
::;
.'
"
,.
B
U
S
~.~I:
':"',
,,~~~.
RESULT BUS
~i:;~~~. ·~\: :~.< . ~,~. :~~: :;~" >:.~:': :;: ~~~~,:::.'::;~:<.; '~'.
TEST
LOGIC
TEST
PORT 0
PORT 1
I/O
I/O
PORT4
PORT5
RESET &
POWER ON
CLEAR
363
3872 PROGRAMMABLE REGISTERS, PORTS AND MEMORY MAP
Figure 2
INDIRECT
SCRATCHPAD
ADDRESS REGISTER
ACCUMULATOR
I
A
I
ISL
32
0
~6bits-
STATUS
REGISTER
PROGRAM
COUNTER
(WI
:{
PO
POU
z
I
0
N
T
R
V E A I
ERR G
R 0 R N
C F
C S
11
..
Y
BINARY
TIMER
..
87
12 bits
0
a{
11
PL
1
87
..
0
12 bits
0
1
J
9
9
11
HU
10
A
HL
11
B
12
13
KU
12
C
14
KL
13
o
15
au
aL
14
E
16
15
F
17
...
61
3D
3E
75
76
63
3F
77
DEC
0
HEX
0
4030
FBE
7_8bits_0
DATA
COUNTER
MAIN MEMORY
MEMORY
DC
DCU
INTERRUPT
CONTROL PORT
..
11
I
~
DCL
87
12 bits
..
0
PORT 6
R
0
M
AUXDATA
COUNTER
I/O PORiS
PORT 5
PORT4
I
DCI U
.
11
DCl
I
DCI L
87
12 bits
0
...
7 _ 8 bits"" 0
364
4031
FBF
4032
4033
FCO
FCI
4094
FFE
4095
FFF
R
A
M
PORT 1
PORTO
0
62
PORT 7
7_8bits-...0
OC1
0
§
P
PU
HEX
I
STACK
REGISTER
N L
T 0
R W
L
~5bits_0
POL
I
DEC
H
IS
ISU
5
7-8bits-0
SCRATCHPAD
logic, the ALU performs the required arithmetic or
logic operations (using the data presented on the two
input busses) and provides the result on the result
bus. The arithmetic operations that can be performed
in the ALU are binary add, decimal adjust, add with
carry, decrement, and increment. The logic operations that can be performed are AND, OR, EXCLUSIVE OR, "s complement, shift right, and shift
left. Besides providing the result on the result bus, the
ALU also provides four signals representing the status
of the result. These signals, stored in the Status
Register (W), represent CARRY, OVERFLOW,
SIGN, and ZERO condition of the result of the
operation.
Accumulator (A)
The Accumulator (A) is the prinicpal register for
data manipulation within the 3872. A serves as one
input to the ALU for arithmetic or logical operations.
The result of ALU operations are stored in A.
The Status Register (W)
The Status Register (also called the W register)
holds five status flags as follows:
"--BITNO.
STATUS REGISTER (WI
cessed upon completion of the first non-privileged
instruction. If the ICB is cleared an interrupt request
will not be acknowledged or processed until the
ICB is set.
I/O Ports
The 3872 provides four complete bidirectional
Input/Output ports. (When standby option is used,
Port 0, bit a and 1 are not available). These are
Ports 0, 1, 4, and 5. In addition, the Interrupt
Control Port is addressed as Port 6 and the binary
timer is addressed as Port 7. An output instruction
(OUT or OUTS) causes the contents of A to be
latched into the addressed port. An input instruction
(I N or INS) transfers the contents of the port to A
(port 6 is an exception which is described later).
The I/O pins on the 3872 are logically inverted.
The schematic of an I/O pin and available output
drive options are shown in Figure 3.
An output ready strobe is associated with Port 4.
This flag may be used to signal a peripheral device
that the 3872 has just completed an output of new
data to Port 4. The strobe provides a single low pulse
shortly after the output operation is completely
finished, so either edge may be used to signal the
peripheral. STROBE may also be used as an input
strobe simply by doing a dummy output of H '00'
to Port 4 after completing the input operation.
Timer and Interrupt Control Port
SIGN
L-._ _
L-._ _ _ _
CARRY
ZERO
~----- OVERFLOW
INTERRUPT CONTROL
BIT
Summary of Status Bits
The Timer is an 8-bit binary down counter which is
software programmable to operate in one of three
modes: the Interval Timer Mode, the Pulse Width
Measurement Mode, or the Event Counter Mode.
As shown in Figure 4, associated with the Timer
are an 8-bit register called the Interrupt Control Port,
a programmable prescaler, and an 8-bit modulo-N
register. A functional logic diagram is shown in
Figure 5.
The desired timer mode, prescale value, starting and
stopping the timer, active level of the EXT INT pin,
~ ALU7/\ALU6 /\ ALU5 /\ ALU4 /\ and local enabling or disabling of interrupts are
ALU3/\ ALU2 /\ ALU, /\ ALUO
selected by outputting the proper bit configuration
from the Accumulator to the Interrupt Control
= CA RRY7
Port (Port 6) with an OUT or OUTS instruction.
Bits within the Interrupt Control Port are defined
= ALU7
as follows:
OVERFLOW = CARRY 7(E)CARRY 6
ZERO
CARRY
SIGN
Interrupt Control Bit (rCB)
Interrupt Control Port (Port 6)
The ICB may be used to allow or disallow interrupts
in the 3872. This bit is not the same as the two
interrupt enable bits in the Interrupt Control Port
(rCP). If the ICB is set and the 3872 interrupt logic
communicates an interrupt request to the CPU
section, the interrupt will be acknowledged and pro-
Bit a - External Interrupt Enable Bit 5 - -;- 2 Prescale
Bit 1 - Timer Interrupt Enable
Bit 6 - -;- 5 Prescale
Bit 2 - EXT INT Active Level
Bit 7 - -;- 20 Prescale
Bit 3 - Start/Stop Timer
Bit 4 - Pulse Width/Interval Timer
365
I/O PIN CONCEPTUAL DIAGRAM WITH OUTPUT BUFFER OPTIONS
Figure 3
Vee
Output
Buffer
PORT
I/O
PIN
Q
C
0
'';:;
~
l-
I-
a:
0
a.
a:
0
a.
0
0
0
a:
0
LU
:::l
Cl
~
c
()
-a
<{
a:
0
<{
0
...J
...
Q)
'~
(j)
:::J
co
«
«0
I-
OUTPUT BUFFER OPTIONS
Vee
Vee
6 K
n
typ,
Standard
Output
1K
Open Drain
Output
n
Direct Drive
Output
Ports 0 and 1 are Standard Output type only,
Ports 4 and 5 may both be any of the three output options (programmable bit by bit).
The STROBE output is always configured similar to a Direct Drive Output except that it is capable of
driving 3 TTL loads.
RESET and EXT I NT may have standard 6Kn (typical) pull-up or may have no pull·up.
366
typ,
"TI-l
TIMER & CONTROL PORT BLOCK DIAGRAM
.g' ~
Figure 4
(;m
.... :::0
rc.o
(")
o2
-l
:::0
o
External
Time
Base
.;.2
PRESCALER
cp
Clock
7'
-..
TIMER
8-bit down counter
(port 7)
.;-2,5,10,20,40,100, or 200
r~
o
:::0
-l
OJ
r-
o
(")
II
I~
J
..
TIMER
INTERRUPT
REQUEST
LATCH
o'"
»
MODULO-N REGISTER
C)
:::0
»
S
8-bits
INT
CO
PO
(po
IUPT
OL
Event Counter Mode
2 Prescale
5 Prescale
10 Prescale
20 Prescale
40 Prescale
100 Prescale
200 Prescale
~
~
~
~
~
~
~
~
+20
.;-5
.;-2
7
6
5
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
4
3
2
L:
0.-
Bit No.
Ex"",' I""",pt Eoobl,
Timer Interrupt Enable
~
EXT INT Active Level
. . Start/Stop Timer
Pulse Width/Interval Timer
Note: See Fi!jure 5for a more detailed functional diagram.
CAl
0)
'-I
EXTERNAL
INTERRUPT
REQUEST
LATCH
w
m
FROM
INTERRUPT
CONTROL
:::!!s
PORT
~A
co
~W
"'co
83
82184
85
86
UI ......
B7
N
BO IBI
-t
'INS 7'
~
~
m
::JJ
::::
Z
-t
m
-
SET
iP
TIMER
::JJ
::JJ
INTERRU~T* ~
"T1
*LOADS INTERRUPT VECTOR
~~O~~~ U~?~~O~6~TION
J'L-
+
~
(')
PRIVILEGED
INSTRUCTION.::!
C
~?~~~WLEDGE r-
o
z
~
I I I
INTERRUPT
S!
~
::JJ
~
S
'I'=PULSE WIDTH MODE
JL
EXTERNAL
INTERRUPT
INPUT
JL
"XTERNAL INTERRUPT T
MK3872 TIMER/INTERRUPT FUNCTIONAL DIAGRAM
t LOADS INTERRUPT VECTOR
H 'OAO' UPON COMPLETION
OF THE FIRST NONPRIVILEGED INSTRUCTION
Figure 5.
1011
L-----------------------------------------CC
ACKNOWLEDGE
EXTERNAL
INTERRUPT
A special situation exists when reading the Interrupt
Control Port (with an IN or INS instruction). The
Accumulator is DQ!; loaded with the content of the
ICP; instead, Accumulator bits 0 through 6 are loaded
with O's while bit 7 is loaded with the logic level
being applied to the EXT I NT pin, thus allowing the
status of EXT INT to be determined without the
necessity of servicing an external interrupt request.
When reading the Interrupt Control Port (Port 6)
bit 7 of the Accumulator is loaded with the actual
logic level being applied to the EXT INT pin, regardless of the status of ICP bit 2 (the EXT INT Active
Level bit); that is, if EXT I NT is at +5V bit 7 of the
Accumulator is set to a logic 1, but if EXT INT is at
GND then Accumulator bit 7 is reset to logic O.
This capability is useful in establishing a high speed
polled handshake procedure or for using EXT I NT
as an extra input pin if external interrupts are not
required and the Timer is used only in the Interval
Timer Mode. However, if it is desirable to read the
contents of the I CP then one of the 64 scratch pad
registers or one byte of RAM may be used to save
a copy of whatever is written to the ICP.
The rate at which the timer is clocked in the Interval
Timer Mode is determined by the frequency of an
internal clock and by the division value selected for
the prescaler. (The internal clock operates at onehalf the external time base frequency). If ICP bit 5 is
set and bits 6 and 7 are cleared, the prescaler divides
by 2. Likewise, if bit 6 or 7 is individually set the
prescaler divides by 5 or 20 respectively. Combinations of bits 5, 6 and 7 may also be selected.
For example, if bits 5 and 7 are set while 6 is cleared
the prescaler will divide by 40. Thus possible prescaler values are 72, 75. 710, 720, 74J, 7100, and
7200.
Any of three conditions will cause the prescaler to be
reset: whenever the timer is stopped by clearing lCP
bit 3, execution of an output instruction to Port 7,
(the timer is assigned port address 7), or on the
trailing edge transition of the EXT I NT pin when
in the Pulse Width Measurement Mode. These last
two conditions are explained in more detail below.
An OUT or OUTS instruction to Port 7 will load the
content of the Accumulator to both the Timer and
the 8-bit modulo-N register, reset the prescaler, and
clear any previously stored timer interrupt request.
As previously noted, the Timer is an 8-bit down
counter which is clocked by the prescaler in the
Interval Timer Mode and in the Pulse Width Measurement Mode. The prescaler is not used in the Event
Counter Mode. The Modulo-N register is a buffer
whose function is to save the value which was most
recently outputted to Port 7. The modulo-N register
is used in all three timer modes.
Interval Timer Mode
When I CP bit 4 is cleared (logic 0) and at least one
prescale bit is set the Timer operates in the Interval
Timer Mode. When bit 3 of the ICP is set the Timer
will start counting down from the modulo-N value.
After counting down to H'01', the Timer returns to
the modulo-N value at the next count. On the transition from H'01' to H 'N' the Timer sets a timer
interrupt request latch. Note that the interrupt request latch is set by the transition to H 'N' and not
be the presence of H 'N' in the Timer, thus allowing
a full 256 counts if the modulo-N register is preset
to H '00'. If bit 1 of the I CP is set, the interrupt request is passed on to the CPU section of the 3872.
However, if bit 1 of the ICP is a logic 0 the interrupt
request is not passed on to the CPU section but the
interrupt request latch remains set. If ICP bit 1 is
subsequently set, the interrupt request will then be
passed on to the CPU section. (Recall from the discussion of the Status Register's I nterrupt Control Bit
that the interrupt request will be acknowledged by
the CPU section only if I CB is set). Only two events
can reset the timer interrupt request latch; when the
timer interrupt request latch is acknowledged by the
CPU section, or when a new load of the modulo-N
register is performed.
Consider an example in which the modulo-N registe
is loaded with H '64' (decimal 100). The time
interrupt request latch will be set at the 100th
count following the timer start and the timer interrupt request latch will repeatedly be set on precise
100 count intervals. If the prescaler is set at 740
the timer interrupt request latch will be set every
4000 clock periods. For a 2MHz clock (4MHz
time base frequency) this will produce 2 millisecond
intervals.
The range of possible intervals is from 2 to 51,200
clock periods (1~s to 25.6ms for a 2MHz clock).
However, approximately 50 periods is a practical
minimum because the time between setting the
interrupt request latch and the execution of the first
instruction of the interrupt service routine is at least
29 periods (the response time is dependent upon
how many privileged instructions are encountered
when the request occurs). To establish time int&rvals
greater than 51,200 clock periods is a simple
matter of using the timer interrupt service routine to
count the number of interrupts, saving the result in
one or more of the scratchpad registers until the
desired interval is achieved. With this technique
virtually any time interval, or several time intervals,
may be generated.
The Timer may be read at any time and in any mode
using an input instruction (I N 7 or INS 7) and may
369
take place "on the fly" without interferring with
normal timer operation. Also, the Timer may be
stopped at any time by clearing bit 3 of the ICP.
The timer will hold its current contents indefinitely
and will resume counting when bit 3 is again set.
Recall however that the prescaler is reset whenever
the Timer is stopped; thus a series of starting and
stopping will result in a cumulative truncation
error.
A summary of other timer errors is given in the
timing section of this specification. For a free running
timer in the Interval Timer Mode the time interval
between any two interrupt requests may be in error
by ± 6 clock period:; although the cumulative
error over many intervals is zero. The prescaler and
Timer generate precise intervals for setting the timer
interrupt request latch but the time out may occur
at any time within a machine cycle. (There are two
types of machine cycles: short cycles which consist
of 4 clock periods and long cycles which consist
of 6 clock periods. In the multi-chip F8 family
there is a signal called the WRITE clock which corresponds to a machine cycle). Interrupt requests are
synchronized with the internal WR ITE clock thus
giving rise to the possible ± 6 error. Additional
errors may arise due to the interrupt request
occurring while a privileged instruction or multicycle
instruction is being executed. Nevertheless, for most
applications all of the above errors are negligible,
especially if the desired time intervall is greater than
lms.
Pulse Width Measurement Mode
When ICP bit 4 is set (logic 1) and at least one prescale bit is set the Timer operates in the Pulse Width
Measurement Mode. This mode is used for accurately
measuring the duration of a pulse applied to the
EXT I NT pin. The Timer is 5topped and the prescaler
is reset whenever EXT INT is at its inactive level.
The active level of EXT INT is defined by ICP bit 2;
if cleared, EXT INT is active low; if set, EXT INT is
active high. If ICP bit 3 is set, the prescaler and
Timer will start counting when EXT INT transitions
to the active level. When EXT INT returns to the
inactive level the Timer then stops, the prescaler
resets and if ICP bit 0 is set an external interrupt
reque~t latchisSet.Turiiike timer interrupts, external
interrupts are not latched if the ICP Interrupt Enable
bit is not set).
As in the Interval Timer Mode, the Timer may be
read at any time, may be stopped at any time by
clearing ICP bit 3, the prescaler and ICP bit 1 function as previously described, and the Timer still
functions as an 8-bit binary down counter with the
timer interrupt request latch being set on the Timer's
transition from H '01' to H 'N'. Note that the EXT
INT pin has nothing to do with loading the Timer;
370
its action is that of automatically starting and stopping the Timer and of generating external interrupts.
Pulse widths longer than the prescale value times the
modulo-N value are easily measured by using the
timer interrupt service routine to store the number of
timer interrupts in one or more scratchpad registers.
As for accuracy, the actual pulse duration is typically
slightly longer than the measured value because the
status of the prescaler is not readable and is reset
when the Timer is stopped. Thus for maximum
accuracy it is advisable to use a small division setting
for the presca1er.
Event Counter Mode
When ICP bit 4 is cleared and all prescale bits (I CP
bits 5, 6, and 7) are cleared the Timer operates in the
Event Counter Mode. This mode is used for counting
pulses applied to the EXT INT pin. If ICP bit 3 is set
the Timer will decrement on each transition from the
inactive level to the active level or the EXT I NT pin.
The prescaler is not used in this mode, but as in the
other two timer modes, the timer may be read at any
time, may be stopped at any time by clearing ICP
bit 3, ICP bit 1 functions as previously described,
and the timer interrupt request latch is set on the
Timer's transition from H '01' to H 'N '.
Normally ICP bit 0 should be kept cleared in the
Event Counter Mode; otherwise, external interrupts
will be generated on the transition from the inactive
level to the active level of the EXT INT pin.
For the Event Counter Mode the minimum pulse
width required on EXT INT is 2 clock periods and
the minimum inactive time is 2 clock periods;
therefore, the maximum repetition rate is 500KHz.
Timer Emulation
For total software compatibility when expanding
into a multi-chip configuration the MK3871 Peripheral Input/Output circuit should be used rather
than the older MK3861 PIO. The MK3871 has the
same improved Timer (binary count, readable, and
three modes of operation rather than one) and ready
strobe output as are on the MK3872.
External Interrupts
When the timer is in the Interval Timer Mode the
EXT INT pin is available for non-timer related
interrupts. If ICP bit 0 is set an external interrupt
request latch is set when there is a transition from the
inactive level to the active level of EXT INT.
(EXT INT is an edge-triggered input). The interrupt
request is latched until either acknowledged by the
CPU section or until ICP bit 0 is cleared (unlike
timer interrupt requests which remain latched even
when ICP bit 1 is cleared). External interrupts are
handled in the same fashion when the Timer is in
the Pulse Width Measurement Mode or in the Event
Counter Mode, except that only in the Pulse Width
Measurement Mode the external interrupt request
latch is set on the trailing edge of EXT INT, that is,
on the transition from the active level to the inactive
level.
Interrupt Handling
When either a timer or an external interrupt request
is communicated to the CPU section of the 3872,
it will be acknowledged and processed at the completion of the first non-privileged instruction if the
Interrupt Control Bit of the Status Register is set.
If the Interrupt Control Bit is not set, the interrupt
request will continue until either the Interrupt
Control Bit is set and the CPU section acknowledges
the interrupt or until the interrupt request is cleared
as previously described.
If there is both a timer interrupt request and an
external interrupt request when the CPU section
starts to process the requests, the timer interrupt
is handled first.
When an interrupt is allowed the CPU section will
request that the interrupting element pass its interrupt vector address to the Program Counter via
the data bus. The vector address for a timer interrupt
is H '020'. The vector address for external interrupts
is H 'OAO'. After the vector address is passed to the
Program Counter, the CPU section sends an acknowledge signal to the appropriate interrupt request
latch which clears that latch. The execution of the
interrupt service routine will then commence.' The
return address of the original program is automatically saved in the Stack Register, P.
The Interrupt Control Bit of W (Status Register) is
automatically reset when an interrupt request is
acknowledged. It is then the programmer's responsibility to determine when ICB will again be set
(by executing an EI instruction). This action prevents an interrupt service routine from being interrupted unless the programmer so desires.
External Reset
When RESET is taken low the content of the Program Counter is pushed to the Stack Register and
then the Program Counter and the ICB bit of the
W Status Register are cleared. The original Stack
Register content is lost. Ports 4, 5, 6 and 7 are loaded
with H'OO'. The contents of all other registers and
ports are unchanged. When power is first applied all
ports and registers are undefined until a reset is performed. When RESET is taken high the first program
instruction is fetched from ROM location H '000'.
When an external reset of the 3872 occurs, PO is
pushed into P and the old contents of P are lost. It
must be noted that an external reset is recognized at
the start of a machine cycle and not necessarily at
the end of an instruction. Thus if the 3872 is executing a multi-cycle instruction, that instruction is
not completed and the contents of P upon reset
may not necessarily be the address of the instruction
that would have been executed next. It may, for
example, point to an immediate operand if the reset
occurred during the second cycle ofa LI or CI
instruction. Additionally, several instructions (JMP,
PI, PK, LR PO, Q) as well as the interrupt acknowledge sequence modify PO in parts. That is, they
alter PO by first loading one part then the other
and the entire operation takes more than one cycle.
Should reset occur during this modification process
the value pushed into P will be part of the old PO
(the as yet unmodified part) and part of the new
PO (already modified part). Thus care should be taken
(perhaps by external gating) to insure that reset
does not occur at an undesirable time if any significance is to be given to the contents of P after a reset
occurs.
Test Logic
Special test logic is implemented to allow access to
the internal main data bus for test purposes.
In normal operation the rEST pin is unconnected
or is connected to GND. When TEST is placed at a
TTL level (2.0V to 2.6V) Port 4 becomes an output
of the internal data bus and Port 5 becomes a wiredOR input to the internal data bus. The data appearing
on the Port 4 pins is logically true whereas input data
forced on Port 5 must be logically false. When TEST
is placed at high level (6.0V to iovl. the ports act
as above and additionally the 2K x 8 program ROM
is prevented from driving the data bus. In this mode
operands and instructions may be forced externally
through Port 5 instead of being accessed from the
program ROM. When TEST is in either the TTL
state or the high state, STROBE ceases its normal
function and becomes a machine cycle clock
(identical to the F8 multi-chip system WR ITE clock
except inverted).
371
~---
'
--------
SAVE ROUTINE REQUIRED, VSB;;;' 2.2 VOLTS
Figure 6a.
VCC SUSTAINED BY CAPACITOR OR
BATTERY UNTIL RAMPRT BROUGHT LOW
~
VCC
Mru,
~'''"W" -{
FAILURE DETECTED
~
EXT INT
I
I
~
I
--RESET/RAMPRT
I
-1
I
I
~-fr---/I
I
L
DATA SAVE
MUST
BE
DONE
HERE
;1
fy
I
~
I
ACCESS TO
RAM INHIBITED
..
~
EXECUTION
BEGINS AGAIN
I
NO SAVE ROUTINE REQUIRED, VSB;;;' 2.2 VOL TS
Figure 6b.
VCC----_~
MAIN POWER
FAILURE DETECTED
1
/
( )
~--~)
r--------
\'-------I( --------~/
}
372
)r(
Timing complexities render the capabilities associated with the TEST pin impractical for use in a user's
application, but these capabilities are thoroughly
sufficient to enable a rapid method for thoroughly
testing the 3872.
STANDBY POWER OPTION
If the standby power option has not been selected
Port O-bit 0 and 1 are readable and writeable.
If the standby power option is selected PortO-Bit 1
is readable only. Port O-Bit 0 remains readable and
writable although it is not connected to a package
pin. The standby power source (VSB) is connected
to Pin 4.
A .01 ~F capacitor must be connected to Pin 3. The
purpose of the capacitor is to decouple noise coupled
to the substrate of the circuit when VCC is switched
off and on. It is recommended that Nickel-Cadmium
batteries (typical voltage of 3 series cells = 3.6V) be
used for standby power, since the M K3872 can automatically trickle charge the three Ni-Cad's. If more
than three cells in series are used, the charging circuit
must be provided outside the MK3872. Whenever
RESET-RAMPRT is brought low, the standby RAM
(64x8 bit words in PO/DC address space, 4032 to
409510 or FCO to FFF16) is placed in a protected
state. Also the RAM itself is switched from VCC
power to the VSB power. Two modes of powering
down are recommended. In the first mode, the processor must be interrupted early enough to save all
necessary data before the VCC falls below the minimum level. After the save is done, RESET can fall.
This prevents any further access of the RAM; Vf,..C
may now fall. As the power comes up, th«: RESE /
RAMPRT signal should be held low until VCC IS
above the minimum level.
Now execution may terminate at any time, even
during the update of a variable or flag word, causing
that byte in RAM to be bad data. There is always a
good data byte which contains either the most
recent or next most recent value of the variable.
Any copy of the variable where the flag word is
"set" is a good data byte. While this method significantly encumbers the data storage process, it eliminates the need for a power fail interrupt which both
reduces external circuitry and leaves the external
interrupt pin completely free for other use.
3872 Clocks
The time base for the 3872 may originate from one
of five sources. There are four external modes and
one internal mode.
If both XTL 1 and XTL 2 are grounded, the 3872
will activate its internal oscillator.
The four external configurations are shown in Figure
7. There is an internal 20pF capacitor between XTL 1
and GND and an internal 20pF capacitor between
XTL 2 and GND. Thus external capacitors are not
neccessarily required. In all external clock modes the
external time base frequently is divided by two to
form the internal II> clock.
Crystal Selection
The use of a crystal as the time base is highly recommended as the frequency stability and reproducability from system to system is unsurpassed. The
3872 has an internal divide by two to allow the user
of inexpensive and widely available TV Color Burst
Cyrstals (3.58MHz). The following crystal parameters
and vendors are suggested for 3872 applications:
The second mode may be used if a special save data
routine is not needed. The EXT INTERRUPT need
not be used and the only reguirement to save the
RAM data is that RESET-RAMPRT be low before
VCC drops below 4.5V. For examl'lle if a few key
variables are to be stored in RAM and it is desired
that these be saved during a loss of power, two copies
of each variable are kept with an associated flag, thus
no interrupt and save routine is necessary. The
method of updating a variable is as follows:
a) Parallel Resonance, Fundamental Mode AT-Cut
b) Frequency Tolerance measured with 18pF load
(0.1 % accuracy). Drive level 10mW.
c) Shunt Capacitance (Co) = 7pF max.
d) Series Resistance (Rs)
- Clear Flag Word 1
- Update Variable (Copy 1)
- Set Flag Word 1
- Clear Flag Word 2
- Update Variable (Copy 2)
- Set Flag Word 2
f= 1MHz
f 2MHz
f - 3MHz
f= 3.58MHz
f = 4MHz
Parameters
Holder
Rs = 550 ohms
Rs - 300 ohms
Rs - 150 ohms
Rs - 150 ohms
Rs = 150 ohms
max.
max.
max. *
max.
max.
HC-6
HC-33
HC-6
HC-18
HC-25
HC-33
*HC-18 or HC-25 holder may not be available at
3MHz.
373
CLOCK CONFIGURATIONS
Figure 7
VCC
RC Mode
~
EDR
~Cexternal
--:- (optional)
---L-
Minimum R = 4K
Crystal Mode
External Mode
~D§
99
Open
ATCutl-4MHz
n
External
Clock
C = 26.5 pF ±2.6pF + Cexternal
FREQUENCY VRS RC
LC Mode
4
XTL 1
XTL 2
L
3
r...
I
L
MH,
2
1
Cexternal (optional)
l'
I
Minimum L = 0.1 mH
Minimum Q = 40
I
MAXIMUM (4.5 - 5.5V, DOC -7o el
,
,
TYPICAL (TYPICAL UNIT AT Vee = 5V, T A = 25°C)
,
D
Maximum Cexternal =30pF
MINIMUM (4.5V ·5.5V. O'C· 70°CI:
0
1 X 10-7
3 X 10-7
2 X 10-7
I
--1~---'
4 X 10-7
5 X 10-7
(Rl (CINTERNAL + CEXTERNALl
UNIT TO UNIT VARIATION = ± 12%
VARIATION FROM 4.5 to 5.5V
REFERENCED TO 5V.=o +7% -4%
VARIATION FROM o"e TO 70°C
REFERENCED TO 25 C = +6% -9%
6 X 10-7
C = 10pF ± 1.3pF + Cexternal
1
f~21TVTC
Q
TOTAL VARIATION NOT CONSIDERING
VARIATION IN EXTERNAL COMPONENTS'" ±. 25%
NOTE: The stray capacitance across the inductor
must be included as Cexternal in all calculations.
Suggested Crystal Vendors
a) Electro-Dynamics
5625 Foxridge Drive
Mission, Kansas 66201
913-262-2500
b) CRYSTEK
1000 Crystal Drive
Ft. Myers, Florida 33901
813-936-2109
374
c) W.T. Liggett Corp.
1500 Worcester Rd.
Section 30
Framingham, MA 01701
617-620-1150
e) Electronic Crystals Corp.
1153 Southwest Blvd.
Kansas City, Kansas 66103
913-262-1274
d) Erie Frequency Control
453 Lincoln Street
Carlisle, Penn 17013
717-249-2232
f) M-TRON Industries
P.O. Box 630
100 Douglas Avenue
Yankton, South Dakota
605-665-9321
:!)s:
MK3872 PROGRAMMING MODEL
~~
CD CO
Figure 8
OO-.,j
N
OUTS
r-----------------------~IADC
7
"g
:II
o
INS*7
G')
),
:II
,I,
·ILNK
»
OUTS 6
w
INS*6
4
LlSL
PO)
t
OUTS 0,1,4.5
I III S*,O,I,4,5
.)<
LlSU
AS'
ASD
o
°
(4 )
1>-
NS
XS
SC RATC H PA D
REGISTERS
1/
PORTS
INVERTING
T
ROM
MEM
LR
4032X8
I"''''
.1 D C
~i
~
tt
J
.. '~I
!J
fIr
I......
pott
FROM
I ~ ...
' 'PO)
1_ •
LR
. . ACCUMULATOR
0;"
OS*
PK 2
LR
~"'I
COM*
INC
SL I
SL4
SRI
SR4
f t " "et
lPO
*
AM
AMD
PROGRAM
COUNTER
HEX
OCTAL
NM
OM
XM
ROM
MEM
40
4KX8
eM*
* These instructions set status
H'020'
t The value of the external interrupt input is loaded to
Bit 7 of the accumulator (with Bits 0 through 6 loaded
with zeros) when the instruction 'INS 6' is executed. This
H'OAO'
H'OOO'
RESET
t
EXTERNAL INTERRUPT
Co)
-..I
UI
instruction also sets status.
Reset Transfers PO to P and
then clears PO, ICB Bit of W,
and Ports 4,5,6 and 7.
tt PO, P, DC, and DCl are 12 bit registers
Note: The instructions PI and PK are shown in two sequential parts.
(PI1, PI2 and PK1, PK2),
LM
RAM
ST IDC)
64X8
s:
s:
z
G')
s:
o
C
m
r-
INSTRUCTION EXECUTION
This section details the timing and execution of the 3872 instruction set. The 3872 executes the entire
F8 instruction set with exact F8 timing.
F8 INSTRUCTION SET
ACCUMULATOR GROUP INSTRUCTIONS
MNEMONIC
OPCODE
OPERATION
MACHINE
OPERAND
FUNCTION
CODE
BYTES
CYCLES
LONG
SHORT
OVR
STATUS BITS
ZERO CRY
J.S
(2MH,I
11
OVR
ZERO
CRY
SIGN
MEMORY REFERENCE INSTRUCTIONS In all Memory Reference Instructions, the Data Counter is incremented
MNEMONIC
OPERATION
QPCODE
MACHINE
OPERAND
FUNCTION
CODE
Add Binary
AM
_IAI + IIDCII
88
Add Decimal
AMD
A.. (A) + [IDCI]-
89
AND
NM
A4IAI A [{DCII
8A
Compare
CM
{(DC)! + ('AI + 1
80
Exclusive OR
XM
A4IAI01IDCII
8C
Load
LM
A"[(DCII
16
Logical OR
OM
A... (A) V"f(DC1J
8B
Store
ST
A_HDCI]
17
BYTES
CYCLES
SHORT
LONG
J.S
12MHzI
STATUS BITS
OVR
ZERO
CRY
SIGN·
1/0
1/0
1/0
1/0
1/0
BCD Adjust
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
ADDRESS REGISTER GROUP INSTRUCTIONS
MACHINE
CODE
Add to Data Counter
MNEMONIC
OPCODE
ADC
DC-IDC) + (A)
8E
Call to Subroutine+
PK
POU ...(r121; POL-.(r131, P4(POI
DC
Call to Subroutine Immediate·
PI
p..(PO), PO.H'aaaa
Exchange DC
XDC
tDCJ~(DC1)
Load Data Counter
LR
DC,O
DCU-4(r14); DCL4(rlS1
Load Data Counter
LR
DC'H
DCU~rl0);
Load DC Immediate
DCI
Load Program Counter
LR
pO,a
POU--lr14); POL.,(r15)
00
P,K
PU~r12J;
09
OPERATION
Load Stack Register
LR
Return from Subroutine*
POP
Store Data Counter
LR
OPERAND
FUNCTION
DC
CYCLES
BYTES
SHORT
LONG
iJS
I2MHzI
OVR
STATUS BITS
CRY SIGN
ZERO
13
28aaaa
2C
DCl..(r11)
H'aaas'
Pl.(r13)
OF
10
PO"'(P)
lC
a,DC
rl44-(DCU); r15 ...(DCL)
DE
Store Data Counter
LR
H,DC
rlQ4(DCU); r1,..(DCL)
11
Store Stack Registf:!r
LR
K,P
r12~PU);
08
r13 ...(PL)
12
2Aaaaa
SCRATCHPAD REGISTER INSTRUCTIONS (Refer to Scratchpad Addressing Modes)
MNEMONIC
OPERATION
OPCDDE
Add Binary
Add Decimal
Decrement
OS
load
LR
Load
Load
MACHINE
OPERAND
FUNCTION
CODE
AS
A-+{A)+(r)
C,
ASD
A-.....(A)+(r)
0,
r... (r) + H'FF'
3,
A,'
A-(f)
4,
LR
A, KU
A ... (r12)
00
LR
A, KL
A"-(r13)
01
Load
LR
A,QU
A·(r14)
02
Load
LR
A,QL
A.(r15)
03
Load
LR
',A
r..-{A)
5,
04
Load
LR
KU,A
r12+iAJ
Load
LR
KL, A
r13-(A)
as
load
LR
QU,A
r14..-(A)
06
OL,A
r15..-(A)
07
CYCLES
BYTES
SHORT
LONG
STATUS BITS
;IS
I2MHz"'I
OVR
ZERO
CRY
SIGN
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Load
LR
And
NS
A_(A)/\(r)
F,
1/0
1/0
Exclusive Or
XS
A+(A) + (r)
E,
1/0
1/0
*Privileged instruction, Accumulator contents altered during execution of PI instruction.
377
- --.-
-"-
-
------- -- ---
MISCELLANEOUS INSTRUCTIONS
MNEMONIC
OPCODE
OPERATION
Disable Interrupt
OPERAND
MACHINE
CODE
FUNCTION
01
RESET ICB
CYCLES
SHORT
LONG
lA
Enable Interrupt *
EI
SETICB
lB
Input
IN
04,05,06,07
A_(lnput Port aa)
26aa
Input Short
INS
0,1
A<-(lnput Port 0 or 1) AO,A 1
Input Short
INS
4,5,6,7
A.-(Input Port a)
Aa
Load ISAR
LR
IS,A
IS....(A)
OB
Load ISAR Lower
LlSL
bbb
ISI:"-bbb
6(1bbb)**
Load ISAR Upper
LlSU
bbb
ISU·bbb
6(Obbb)**
Load Status Register*
LR
W,J
W_(r9)
No Operation
NOP
Output *
OUT
04,05,06,07
Output Short
OUTS
0,1
PO ... (PO)
BYTES
OVR
STATUS BITS
ZERO
CRY
SIGN
8
0
1/0
0
1/0
4
0
1/0
0
1/0
8
0
1/0
0
1/0
1/0
1/0
1/0
1/0
2
2
2
2
2
2
2
2
10
+1
j.IS
(2MHz
~
I nternal Clock Period
WRITE
tw
Internal WR ITE Clock Period
to (I NT)
XTL 1
XTL2
to(EX)
tEX(H)
UNIT
MIN
MAX
250
1000
ns
4MHz - 1.0MHz
250
1000
ns
4MHz-1MHz
90
100
700
700
ns
ns
2tO
4t
Short Cycle
Long Cycle
6t
I/O
NOTES
tdl/O
Output delay from
internal WR ITE Clock
0
1000
tsl/O
Input Setup time
to WR ITE Clock
1000
tl/O-s
Output valid to STROBE
Delay
3t
-1000
3t
+250
tsl
STROBE Low Time
8t
-250
12t
+250
ns
50pF plus
one TTL load
ns
I/O load =
50pF + 1 TTL
STROBE Load=
50pF + 3 TTL
STROBE
FfESET
EXTINT
tRH
tEH
RESET Hold Time, Low
EXT I NT Hold Time,
Active and I nactive State
6t
+750
6t +
750
2t
ns
ns
ns
To trigger
interrupt
To trigger
timer
379
CAPACITANCE
T A = 25°C, f=2MHz
MIN
SYMBOL
PARAMETER
CIN
Input Capacitance: I/O Ports, RESET RAMPRT, EXTINT, TEST
CXTL
Input Capacitance: XTL 1, XTL2
23.5
MAX
UNIT
7
pF
29.5
pF
NOTES
Unmeasured
Pins
Grounded
DC CHARACTERISTICS
T A = O°C to 70°C, VCC = +5V ± 10%, I/O POWER DISSIPATION.;; 100mW
SYMBOL
PARAMETER
ICC
Power Supply Current
TEST CONDITIONS
MAX
UNIT
100
rnA
Outputs Open
500
rnW
Outputs Open
2.4
5.8
V
-0.3
0.6
V
Po
Power Dissipation
VIHE:'
External Clock
I nput High Level
VILHEX
External Clock
Input Low Current
IIHEX
External Clock
Input High Current
100
JlA
VIHEX = VCC
IILEX
External Clock
Input Low Current
·100
JlA
VILEX
2.0
5.8
V
2.0
13.2
V
-0.3
0.8
VIH
VIHOD
VIL
IlL
IL
10H
IOHDD
10L
Input High Level
Ports,RESET1, EXT INTl
Open Drain Input
High Level
I nput Low Level
Ports, RESET1, EXT INT 1
Input Low Current
Ports, RESET2, EXT INT2
Leakage Current
+10
-5
Open drain ports, ~-
RESET3, EXT INT3
Output High Current
Standard ports, RESET2
EXT INT2
OUTPUT High Current
Direct Drive Ports
Output Low Current
10 ports
rnA
·1.6
JlA
=
VSS
VIL=Oo4V
VIN=13.2V
VIWO.OV
JlA
JlA
VOW204V
VOW3.9V
-0.1
rnA
VOH = 204V
-1.5
rnA
rnA
Vnl-l=1.5V
VOW· 7V
-100
-30
-8.5
1.8
rnA
VOL=O.4V
IOHS
STROBE Output High Current
-300
JlA
VOW204V
10LS
STROBE Output Low Current
5.0
rnA
VOL=Oo4V
VIHRPR
VILRPR
380
MIN
Input High Level
For RAM Protect Function
To be effective.
Input High Level
For RAM Protect Function
To be effective
1.9
5.8
V
Guaranteed .1 V less
thanVIHforRESET
-0.3
004
V
Guaranteed .1 V less
than V I L for RESET
..
DC CHARACTERISTICS (Cont'd)
PARAMETER
MIN
MAX
UNIT
VS B
Standby Vee
for RAM
3.2
5.5
V
IS8
Standby current
leHARGE
Trickle charge
available on VSB
with Vee=4.5 to 5.5
SYMBOL
POlO
rnA
rnA
Vsa= 5.5
VSB= 3.2
rnA
VSB=3.8V
·15
rnA
VSB=3.2V
600
60
rnW
rnW
All Pins
anyone pin
6
3.7
·.8
Power dissipated
by I/O Pins4
NOTES
* Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. RESET and EXT INT have internal Schmit triggers giving minimum .2V hysteresis.
2. RESE'f or EXT INT programmed with standard pull·up
3. RESEi' or EXT INT programmed without standard pull-up
4. Power dissipation for 1/0 pins is calculated by~(Vcc - VIL) q IILI) +~(VCc - VOH)
q 10H II +~(VOL)
(lOL)
TIMER AC CHARACTERISTICS
Definitions:
Error
= Indicated time value - actual time value
tpsc
= t X Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±6t
Cumulative interval error, free running (Note 3) ..................................... 0
Error between two Timer reads (Note 2) ................................... ±(tpsc + t to -(tpsc +t to -(tpsc + 7tell)
Start Timer to interrupt request error (Notes 1,3) .......................... -2tell to -8tell
Load Timer to stop Timer error (Note 1) ........................... +tell to -(tpsc + 2tell)
Load Timer to read Timer error (Notes 1,2) ........................ -5tell to -(tpsc + 8tell)
Load Timer to interrupt request error (Notes 1,3) ........................ -2t ell to -9tell
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) ................................. .+t eIlto -(tpsc +2t ell)
Minimum pulse width of EXT INT pin ..........................................2tell
Event Counter Mode:
Minimum active time of EXT INT pin ............................................2t<1>
Minimum inactive time of EXT INT pin ..........................................2tell
Notes:
1. All times which entail loading, starting, or stopping the Timer are referenced from the end
of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the last machine
cycle of the IN or INS instruction.
3. All times which entail the generation of an interrupt request are referenced from the start
of the machine cycle in which the appropriate interrupt request latch is set. Additional
time may elapse if the interrupt request occurs during a privileged or multicycle instruction.
4. Error may be cumulative if operation is repetitively performed.
381
AC TIMING DIAGRAM
Figure 9
External Clock
Internal Clock
I/O Port Output
r'~-'
STROBE
RESET
ICPBIT]="
EXTINT
_
tEH
BIT 2=1
Note: All measurements are referenced to VI L max., VIH min., VOL max., or VOH min.
382
INPUT/OUTPUT AC TIMING
Figure 10
INTERNAL
WRITE
CLOCK
n
* CYCLE TIM ING
SHOWN FOR
4MHz EXTER NAL
CLOCK
2jJS* ,
INOR
INS
OPCODE
FETCHED
3jJS*
,
PORTADDR.
PLACED ON
DATA BUS
,
3jJS*
PORT DATA
DRIVEN ON TO
DATA BUS
2J.!S*1
I~
11'--
NEXT
OPCODE
FETCHED
X
X
PORT PINS
,
CYCLE TIMING
DEPENDS ON INSTRUCTION
1jJS
SETUP
MAX.
tSIO
I
A. INPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
,
2J.!S*'
OUTOR
OUTS
OPCODE
FETCHED
3jJS*
,
PORTADDR.
ON DATA
BUS
CYCLE TIMING
DEPENDS ON INSTRUCTION
3jJS*
r
ACCUMULATOR
CONTENTS
ON DATA BUS
PORT PINS
STROBE
(ACTIVE FOR PORT 4 ON L YI
2J.!S*j
NEXT
OPCODE
FETCHED
X
tdl/O
STAYS LOW
I+1jJS
FOR TWO WRITE
CYCLES
MAX.
B. OUTPUT ON PORT 4 OR 5
-
I-r- 500n.* MIN.
INTERNAL
WRITE
CLOCK
OUTS 0,1
FETCHED
ACC DATA
ON BUS
PORT PINS
1jJS
MAX
C. INPUT ON PORT 0 OR 1
D. OUTPUT ON PORT 0, 1
383
STROBE SOURCE CAPABILITY
(TYPICAL AT VCC = 5V, TA = 25°C)
Figure 11
-15
S
0
U
R
C
E
C
U
R
R
E
N
T
-10
"""""'- ~
"""""'-5
"
..........
~
.....
M
A
~
..... -......
.....
"-
" i'-
~
r"
2
3
""'"
/
4
OUTPUT VOLTAGE
STROBE SINK CAPABILITY
(TYPICAL AT VCC = 5V, TA
= 25°C)
Figure 12
S
I
N
K
C
U
R
R
E
N
T
+100
+50
~ 10-"'"
,
M
A
~
/
/
./
."
1
~ """"
2
3
OUTPUT VOLTAGE
384
4
5
STANDARD I/O PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V, T A = 25°C)
Figure 13
-1.5
S
0
U
R
C
E
f' ~
-1.0
~
C
U
R
R
E
N
T
M
A
"'""
""
~~
'-.
"'"""-.5
""- "......
~
"'"" ~
,,~
......
2
"
'5
4
3
"""'III
OUTPUT VOLTAGE
DIRECT DRIVE I/O PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V, T A = 25°C)
Figure 14
S
0
U
R
C
E
C
U
R
R
E
N
T
-10
-r--5
~
...... r--. ......
.......
, ,
....
~
M
A
~
""'~
~
2
3
""
4
5
OUTPUT VOLTAGE
385
I/O PORT SINK CAPABILITY
(TYPICAL AT VCC = 5V, TA = 25°C)
Figure 15
+60
S
I
N
K
+50
C
U
+40
R
R
E
N
T
+30
M
A
+20
~",
~
+10
~
~
~
~
--
...-~
",.,.,.
",
",
~
2
4
3
5
OUTPUT VOL TAGE
MAXIMUM OPERATING TEMPERATURE VS. I/O POWER DISIPATION
Figure 16
100
--
°C
~
"""
50
I000o..
.......
~4s7-C:Ie ........
....... .... CER~Mi'C
........
100
200
300
400
500
600
PDI/O MW
386
...... ......
~
1000
TRICKLE CHARGE CURRENT
Figure 17
9.0mA
ITC VS. VSB
,
ITC
VCC= 5.5V
"
8.0mA
'"
..... ~
'-.....
""
..........
7.0mA
~
r........
~
3.5V
3.2V
4.0mA
3.8V
I~
'"
ITC
3.0mA
VCC= 4.5V
~
"""" ""
'"
~
2.0mA
3.2V
3.5V
"
.....
"'-
"-
""'t
3.8V
387
----------
PACKAGE DESCRIPTION: 40-Pin Dual In-Line Ceramic Package
I- --j I-II
I .04TYP
.05TYP-l
025 TYP
I
010
I~
~=rtr
II
I --II.018 002
•
TYP
._ _
'9 EQ~~~~:_'00~1.9_00- - - - - I
PACKAGE DESCRIPTION 40-Pin Dual-in-Line Plastic Package
r~
2~---I,L
~~~~~~~~~~~~~~~~UCUC~~'~I~
-
2048X 8 mask programmable ROM
Programmable binary timer
-Internal timer mode
-Pulse width measurement mode
-Event counter mode
Crystal, LC, RC, or external time base
Low power (285mW typ.)
I/O
I/O
0
1/
0
l I o o B o S E R I A L I/O
MK3873 O l i O
c-=>
I/O
°
I/O
I/OW
. W I/O
MK3876
I/OW
<=>1/0
F8 FAMILY
p
E
R
I
External interrupt
MK3870
I/OO
Bol/o
MK3872
1/00
64 additional bytes of executable RAM addressable by program counter or data counter
32 bits (4 ports) TTL Compatible I/O
8<:::::>c-.:)
P
H
E
R
A
L
S
I/O<=>
I/O<=>
I/OW
I/O<=>
<
Single +5 volt ± 10% power supply
Same pinout as MK3870
PIN CONNECTIONS
XTL I -------. I
GENERAL DESCRIPTION
XTL2 _ 2
~VBB po-o'~
The MK3876 is a complete 8-bit microcomputer
on a single MOS integrated circu it. The 3876 can
execute the F8 instruction set of more than 70
commands, allowing expansion into multi-chip
configurations with software compatibility. The
device features 2048 bytes of ROM, 64 bytes of
scratchpad RAM, 64 bytes of executable RAM,
a programmable binary timer, 32 bits of I/O, and a
single +5 volt power supply requirement. Utilizing
ion-implanted, N-channel silicon gate technology
and advanced circuit design techniques the singlechip 3876 offers maximum cost-effectiveness in a
wide range of control and logic replacement applications. The 3876 is an expanded memory version of
the 3870 single chip microcomputer. The 3876 is
identical to the 3870 in the following areas: instruction set, architecture, AC and DC characteristics, and
pinout. The only change is in the memory expansion
along with the appropriate memory address registers.
3
·Vsa' PO-i*_ 4
PO~
~5
PO-3
___ 6
STROBE - - -
7
P"4-=o
~8
j54:I
___ 9
P4-2 ___
10
P4-3
-II
P4-4
-12
29 ___ PS _
4
P4-5 - - 1 3
28_P5-5
p"4=-s
_14
27_i:i"5-6
P4=7
--15
26_P5-""7
25_Pl="7'
24_~
23 ___ ~5
Pcf4
--_19
21_TEST
'PROGRAMMABLE (PORT PINS BECOME VSB AND PIN FUNCTION DEPENDS ON DEVICE OPTION (STANDBY DEVICE OR
STANDARD DEVICE)
401
PIN NAME
PO-O - J5O-7
P1-Q - PH
P4-0 - P4-7
P5-0 - P5-7
STROBE
EXTINT
RESET RAMPRT
TEST
XTL 1, XTL 2
Vee, GND
VSB
VBB
I
DESCRIPTION
I/O Port 0
I/O Port 1
I/O Port 4
I/O Port 5
Ready Strobe
External Interrupt
External Reset, RAM
Protect
Test Line
Time Base
Power Supply Lines
Standby Power
Substrate Decoupling
TYPE
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
-
Input
Input
Input
Input
Input
FUNCTIONAL PIN DESCRIPTION
PO-O-PO-7, P1-0-P1-7, P4-0-P4-7, and P5-0-P5-7
are 32 lines which can be individually used as either
TTL compatible inputs or as latched outputs.
STROBE is a ready strobe associated with I/O Port 4.
This pin which is normally high provides a single low
pulse after valid data is present on the P4-0-P4-7
pins during an output instruction.
RESET - RAMPRT may be used to externally reset
the 3876. When pulled low the 38713 will reset. When
allowed to go high the 38713 will begin program execution ~ogram. location H '000'. Additionally
when RESET - RAMPRT is brought low all accesses
of the executable RAM are prevented and the RAM is
placed in a protected state for powering down VCC
without loss of data when the STANDBY option is
selected.
EXT INT is the external interrupt input. Its active
state is software programmable. This input is also
used in conjunction with the timer for pulse width
measurement and event counting.
XTL 1 and XTL 2 are the time base inputs to which
a crystal (1 to 4MHz), LC network, RC network, or
an external single-phase clock may be connected.
3870 ARCHITECTURE
This section describes the basic funccional elements
of the 3876 as shown in the block diagram of Figure
1. A programming model is shown in Figure 2.
Main Control Logic
The Instruction Register (IR) receives the operation
code (OP code) of the instruction to be executed
from the program ROM via the data bus. During ali
OP code ,fetches eight bits are latched into the I R.
Some instructions are completely specified by the
upper 4 bits of the OP code. In those instructions
the lower 4 bits are an immediate register address
or an immediate 4 bit operand. Once latched into the
I R the main control logic decodes the instruction
and provides the necessary control gating signals to
all circuit elements.
ROM Address Registers
There are four 12 bit registers associated with the
4K x 8 ROM and 64 x 8 RAM. These are the Program
Counter (PO), the Stack Register (P), the Data Counter (DC) and the Auxiliary Data Counter (DC1). The
Program Counter is used to address instructions or
immediate operands. P is used to save the contents of
PO during an interrupt or subroutine call. Thus, P
contains the return address at which processing is
to resume upon completion of the subroutine or the
interrupt routine.
The Data Counter (DC) is used to address data tables.
This register is auto-incrementing. Of the two data
counters only DC can access the memory. However,
the XDC instruction allows DC and DC1 to be
exchanged.
Associated with the address registers is a 12 bit
Adder/lncrementer. This logic element is used to
increment PO or DC when required and is also used to
add displacements to PO on relative branches or to
add the data bus contents to DC in the ADC (add
data counter) instruction.
4032 x 8 ROM
TEST is an input, used only in testing the 3876. For
normal circuit fu_nctionality this pin is left unconnected or may be grounded.
VCC is the power supply input (+5V± 10%).
VSB is the RAM standby power supply input if the
standby option is selected (+5.5V to +2.2V).
VBB is the substrate decoupling pin. A .01 microFarad capacitor is required to provide substrate
decoupling. It is only used when standby option is
selected.
402
The microcomputer program and data constants
are stored in the program ROM. When a ROM access
is required, the appropriate address register (PO or
DC) is gated onto the ROM address bus and the ROM
output is gated onto the main data bus. The first
byte in ROM is location zero.
64 x 8 Executable RAM
The upper 64 bytes of the total 4096 byte memory
of the 3876 is RAM memory. The first byte is at address 4032 decimal (FCO hex). As with the ROM
memory the RAM memory may be accessed by the
PO and DC address registers. It may be written via
the STO R E (ST) instruction. It may be read via the
LOAD (LM) instruction. Additionally instructions
may be executed from the RAM. A mask programmable standby power option is available whereby the
64x8 RAM remains powered and protected so that
its contents are saved during a loss of the normal
circuit power supply.
via IS. This makes it easy to reference a buffer consisting of contiguous scratchpad bytes. For example,
When the low order octal digit is incremented or
decremented IS is incremented from octal 27 (0 '27')
to 0 '20' or is decremented from 0 '20' to 0 '27'.
This feature of the IS is very useful in many program
sequences. All six bits of IS may be loaded at one
time or either half may be loaded independently.
Scratch pad and IS
Scratchpad registers 9 through 15 (decimal) are
given mnemonic names (J, H, K, and 0) because of
special linkages between these registers and other
registers such as the Stack Register. These special
linkages facilitate the implementation of multi-level
interrupts and subroutine nesting. For example,
the instruction LR K, P stores the lower eight bits of
the Stack Register into register 13 (K lower or KL)
and stores the upper three bits of P into register 12
(K upper or K LJ) The scratch pad is not protected
with the standby power option.
The scratch pad provides 64 8-bit registers which may
be used as general purpose RAM memory. The
Indirect Scratchpad Address Register (IS) is a 6 bit
register used to address the 64 registers. All 64
registers may be accessed using IS. In addition the
lower order 12 registers may also be directly addressed.
IS can be visualized as holding two octal digits. This
division of IS is important since a number of instructions increment or decrement only the least significant 3 bits of IS when referencing scratchpad bytes
Arithmetic and Logic Unit (ALU)
After receiving commands from the main control
MK 3876 BLOCK DIAGRAM
Figure 1
XTLl
XTL2
~
VSR
EXTINT
RAMPRT
INTERRUPT
LOGIC
64X 8 RAM
MEMORY ADDRESS BUS
2048 X 8
ROM
MEMORY
ADDRESS
M
A
I
N
POoP
"
.".,(
D'
A
T
A
M
DC, DCI
E
M
MAIN
R
CONTROL
o
Y
LOGIC
RESULT BUS
TEST
LOGIC
TEST
PORT 0
PORT 1
I/O
I/O
PORT4
PORT5
RESET &
POWER ON
CLEAR
403
3876 PROGRAMMABLE REGISTERS, PORTS AND MEMORY MAP
Figure 2
INDIRECT
SCRATCHPAD
ADDRESS REGISTER
ACCUMULATOR
I
A
I
ISL
32
0
4--6 bits-
STATUS
REGISTER
PROGRAM
COUNTER
(W)
:{
PO
POU
..
11
S
I
G
N
..
0
a{
STACK
REGISTER
PU
11
12 bits
HEX
OCl
o
o
o
I
J
9
9
11
HU
10
A
HL
11
B
12
13
KU
12
13
C
D
14
KL
au
14
E
16
QL
15
F
17
a
PL
I
87
DEC
..
0
61
3D
62
3E
75
76
63
3F
77
DEC
0
0
4030
FBE
7_8bits_0
PORT ")
DATA
COUNTER
7_8bits _ _ 0
G:
..
11
INTERRUPT
CONTROL PORT
MAIN MEMORY
MEMORY
DC
I DCL
87
12 bits
~
..
0
PORT 6
HEX
R
0
7_8bits_0
M
AUX DATA
COUNTER
DCl
I/O PORTS
DCIU
..
11
PORT5
PORT4
]
I
DCI L
87
12 bits
.
0
7 _ 8 bits-' 0
404
4031
FBF
4032
4033
FCO
FCI
4094
FFE
4095
FFF
R
A
M
PORT 1
PORTO
15
I
P
.
BINARY
TIMER
POL
87
12 bits
N L
T 0
R W
L
4 _ 5bits_0
R
IS
ISU
5
7..-8bits-0
I 0 Z C
N V E A
T ERR
R R 0 R
C F
Y
SCRATCHPAD
logic, the ALU performs the required arithmetic or
logic operations (using the data presented on the two
input busses) and provides the result on the result
bus. The arithmetic operations that can be performed
in the ALU are binary add, decimal adjust, add with
carry, decrement, and increment. The logic operations that can be perfor)11ed are AND, OR, EXCLUSIVE OR, 1's complement, shift right, and shift
left. Besides providing the result on the result bus, the
ALU also provides four signals representing the status
of the result. These signals, stored in the Status
Register (W), represent CARRY, OVERFLOW,
SIG N, and ZE RO condition of the result of the
operation.
Accumulator (A)
The Accumulator (A) is the prinicpal register for
data manipulation within the 387.6. A serves as one
input to the A LU for arithmetic or logical operations.
The result of A LU operations are stored in A.
The Status Register (W)
The Status Register (also called the IN register)
holds five status flags as follows:
4
3
2
"'-BITNO.
STATUS REGISTER (W)
cessed upon completio.n of the first non-privileged
instruction. If the ICB is cleared an interrupt request
will not be acknowledged or processed until the
ICB is set.
I/O Ports
The 3876 provides four complete bidirectional
Input/Output ports. (When standby option is used,
Port 0, bit 0 and 1 are not available). These are
Ports 0, 1, 4, and 5. I n addition, the Interrupt
Control Port is addressed as Port 6 and the binary
timer is addressed as Port 7. An output instruction
(OUT or OUTS) causes the contents of A to be
latched into the addressed port. An input instruction
(I N or I NS) transfers the contents of the port to A
(port 6 is an exception which is described later).
The I/O pins on the 3876 are logically inverted.
The schematic of an I/O pin and available output
drive options are shown in Figure 3.
An output ready strobe is associated with Port 4.
This flag may be used to signal a peripheral device
that the 3876 has just completed an output of new
data to Port 4. The strobe provides a single low pulse
shortly after the output operation is completely
finished, so either edge may be used to signal the
peripheral. STROBE may also be used as an input
strobe simply by doing a dummy output of H '00'
to Port 4 after completing the input operation.
Timer and Interrupt Control Port
SIGN
CARRY
ZERO
~-----------
OVERFLOW
INTERRUPT CONTROL
BIT
The Timer is an 8-bit binary down counter which is
software programmable to operate in one of three
modes: the Interval Timer Mode, the Pulse Width
Measurement Mode, or the Event Counter Mode.
As shown in Figure 4, associated with the Timer
are an 8-bit register called the I nterrupt Control Port,
a programmable prescaler, and an 8-bit modulo-N
register. A functional logic diagram is shown in
Figure 5.
Summary of Status Bits
The desired timer mode, prescale value, starting and
stopping the timer, active level of the EXT I NT pin,
~ ALU7 !\ALU6 !\ ALU5 !\ ALU4 t\ and local enabling or disabling of interrupts are
ALU3!\ ALU2!\ ALU1 !\ ALUO
selected by outputting the proper bit configuration
from the Accumulator to the Interrupt Control
CARR Y 7
Port (Port 6) with an OUT or OUTS instruction.
Bits within the Interrupt Control Port are defined
ALU7
as follows:
OVERFLOW = CARRY 7(BCARRY 6
ZERO
CARRY
SIGN
Interrupt Control Bit (lCB)
Interrupt Control Port (Port 6)
The ICB may be used to allow or disallow interrupts
in the 3876. This bit is not the same as the two
interrupt enable bits in the Interrupt Control Port
(ICP). If the ICB is set and the 3876 interrupt logic
communicates an interrupt request to the CPU
section, the interrupt will be acknowledged and pro-
Bit 0 - External I nterrupt Enable Bit 5 - -0- 2 Prescale
Bit 1 - Timer Interrupt Enable
Bit 6 - -0- 5 Prescale
Bit 2 - EXT INT Active Level
Bit 7 - -0- 20 Prescale
Bit 3 - Start/Stop Timer
Bit 4 - Pulse Width/Interval Timer
405
I/O PIN CONCEPTUAL DIAGRAM WITH OUTPUT BUFFER OPTIONS
Figure 3
Vee
Output
Buffer
PORT
1(0
PIN
c
0
';:J
f-
~
::l
01
-.=
c
0
(,)
c:c:
q
6
f-
c:c:
c:c:
0
a...
0
a...
0
0
:O
12"
(")
o
Z
-i
:0
Externa
Time
Base
PRESCALER
• .:. 2
Clock
clock periods although the cumulative
error over many intervals is zero. The prescaler and
Timer generate precise intervals for setting the timer
interrupt request latch but the time out may occur
at any time within a machine cycle. (There are two
types of machine cycles: short cycles which consist
of 4 clock periods and long cycles which consist
of 6 clock periods. In the multi-chip F8 family
there is a signal called the WRITE clock which corresponds to a machine cycle). Interrupt requests are
synchronized with the internal WR ITE clock thus
giving rise to the possible ± 6 error. Additional
errors may arise due to the interrupt request
occurring while a privileged instruction or multicycle
instruction is being executed. Nevertheless, for most
applications all of the above errors are negligible,
especially if the desired time intervall is greater than
1ms.
II
~.
.
Pulse Width Measurement Mode
When I CP bit 4 is set (logic 1) and at least one prescale bit is set the Timer operates in the Pulse Width
Measurement Mode. This mode is used for accurately
measuring the duration of a pulse applied to the
EXT I NT pin. The Timer is stopped and the prescaler
is reset whenever EXT I NT is at its inactive level.
The active level of EXT INT is defined by ICP bit 2;
if cleared, EXT INT is active low; if set, EXT INT is
active high. If ICP bit 3 is set, the prescaler and
Timer will start counting when EXT I NT transitions
to the active level. When EXT I I NT returns to the
inactive level the Timer then stops, the prescaler
resets and if I CP bit 0 is set an external interrupt
reque~t latchis7et.Tunlike timer interrupts, external
interrupts are not latched if the ICP Interrupt Enable
bit is not set).
As in the Interval Timer Mode, the Timer may be
read at any time, may be stopped at any time by
clearing ICP bit 3, the prescaler and ICP bit 1 function as previously described, and the Timer stili
functions as an 8-bit binary down counter with the
timer interrupt request latch being set on the Timer's
transition from H '01' to H 'N '. Note that the EXT
INT pin has nothing to do with loading the Timer;
410
its action is that of automatically starting and stopping the Timer and of generating external interrupts.
Pulse widths longer than the prescale value times the
modulo-N value are easily measured by using the
timer interrupt service routine to store the number of
timer interrupts in one or more scratchpad registers.
As for accuracy, the actual pulse duration is typically
slightly longer than the measured value because the
status of the prescaler is not readable and is reset
when the Timer is stopped. Thus for maximum
accuracy it is advisable to use a small division setting
for the presca1er.
Event Counter Mode
When I CP bit 4 is cleared and all prescale bits (I CP
bits 5, 6, and 7) are cleared the Timer operates in the
Event Counter Mode. This mode is used for counting
pulses applied to the EXT INT pin. If ICP bit 3 is set
the Timer will decrement on each transition from the
inactive level to the active level or the EXT I NT pin.
The prescaler is not used in this mode, but as in the
other two timer modes, the timer may be read at any
time, may be stopped at any time by clearing ICP
bit 3, ICP bit 1 functions as previously described,
and the timer interrupt request latch is set on the
Timer's transition from H '01' to H 'N'.
Normally I CP bit 0 should be kept cleared in the
Event Counter Mode; otherwise, external interrupts.•
will be generated on the transition from the inactive
level to the active level of the EXT I NT pin.
For the Event Counter Mode the minimum pulse
width required on EXT INT is 2 clock periods and
the minimum inactive time is 2 clock periods;
therefore, the maximum repetition rate is 500KHz.
Timer Emulation
For total software compatibility when expanding
into a multi-chip configuration the MK3871 Peripheral Input/Output circuit should be used rather
than the older MK3861 PIO. The MK3871 has the
same improved Timer (binary count, readable, and
three modes of operation rather than one) and ready
strobe output as are on the MK3876.
External Interrupts
When the timer is in the Interval Timer Mode the
EXT I NT pin is available for non-timer related
interrupts. If ICP bit 0 is set an external interrupt
request latch is set when there is a transition from the
inactive level to 'the active level of EXT I NT.
(EXT I NT is an edge-triggered input). The interrupt
request is latched until either acknowledged by the
CPU section or until lep bit 0 is cleared (unlike
timer interrupt requests which remain latched even
when ICP bit 1 is cleared). External interrupts are
handled in the same fashion when the Timer is in
the Pulse Width Measurement Mode or in the Event
Counter Mode, except that only in the Pulse Width
Measurement Mode the external interrupt request
latch is set on the trailing edge of EXT INT, that is,
6n the transition from the active level to the inactive
level.
Interrupt Handling
When either a timer or an external interrupt request
is communicated to the CPU section of the 3876,
it will be acknowledged and processed at the com·
pletion of the first non-privileged instruction if the
Interrupt Control .Bit of the Status Register is set.
If the Interrupt Control Bit is not set, the interrupt
request will continue until either the Interrupt
Control Bit is set and the CPU section acknowledges
the interrupt or until the interrupt request is cleared
as previously described.
If there is both a timer interrupt request and an
external interrupt request when the CPU section
starts to process the requests, the timer interrupt
is handled first.
When an interrupt is allowed the CPU section will
request that the interrupting element pass its interrupt vector address to the Program Counter via
the data bus. The vector address for a timer interrupt
is H '020'. The vector address for external interrupts
is H 'DAD'. After the vector address is passed to the
Program Counter, the CPU section sends an acknowledge signal to the appropriate interrupt request
latch which clears that latch. The execution of the
interrupt service routine will then commence. The
return address of the original program is automatically saved in the Stack Register, P.
The Interrupt Control Bit of W (Status Register) is
automatically reset when an interrupt request is
acknowledged. It is then the programmer's responsibility to determine when ICB will again be set
(by executing an EI instruction). This action prevents an interrupt service routine from being inter.
rupted unless the programmer so desires.
Event B
Event B represents the instruction being executed
when the interrupt occurs. The last cycle of B is normally the instruction fetch for the next cycle. However, if B is not a privileged instruction and the CPU's
Interrupt Contr.ol Bit is set, then the last cycle be-.
comes a "freeze" cycle rather than a fetch. At the
end of the freeze cycle the interrupt request latches
are inhibited from altering the interrupt daisy-chain
so that sufficient time will be allowed for the daisychain to settle. (If B is a privileged instruciton, the instruction fetch is not replaced by a freeze cycle; instead, the fetch is performed and the next instruction
is executed. Although unlikely to be encountered, a
series of privileged instructions will be sequentially
executed without interrupt. One more instruction,
called a 'protected' instruction, will always be executed after the last privileged instruction. The last
cycle of the protected instruction then performs the
freeze.)
The dashed lines on EXT INT illustrate the last opportunity for EXT INT to cause the last cycle .of a
non-protected instruction to become a freeze cycle.
The freeze cycle is a short cycle (4 --------I~
TO INTERNAL
3870 LOGIC
RESET STATE~1
413
Power-On Clear (Cont'd)
oscillator to operate (Vcc = 3.5V). Operation with a
crystal is partly mechanical and some start time is required to get the mass of the crystal into vibrational
motion. This time is basically dependent on the frequency (mass) of the crystal. 4 MHz crystals typically
require about 2-3 mSec to start while 1 MHz crystals
require 60-70 mSect to start oscillating. Of course,
this time may vary greatly from crystal to crystal and
is also a function of the power supply rise time characteristic, however, the higher freq\lency crystals start
faster and are definitely recommended (i.e., 3-4
MHz).
The condition of the port pins during the power-onclear sequence is often asked, The port pins or the
STROBE line cannot be specified until Vcc reaches
4.5V and the 3876 enters the RESET state. Before
this, the port pins may stay at Vss, may track Vcc as
it rises, or they may track Vcc part way up then return to Vss (Ports 4 and 5 will go to Vce once the
clocks are running and the 3870 has sufficient Vcc to
properly operate the internal control logic and I/O
ports, Ports 0 and 1 must be controlled by the program).
External Reset
When RESET is taken low the content of the Program Counter is pushed to \ the Stack Register and
then the Program Counter and the ICB bit of the
W Status Register are cleared. The original Stack
Register content is lost. Ports 4, 5, 6, and 7 are
loaded with H '00'. The contents of all other registers
and ports are unchanged. When power is first applied
all ports and registers are undefined until a reset is performed. When RESET is taken high the first program
instruction is fetched from ROM location H '000'.
When an external reset of the 3876 occurs, PO is
pushed into P and the old contents of P are lost. It
must be noted that an external reset is recognized at
the start of a machine cycle and not necessarily at
the end of an instruction. Thus if the 3876 is executing a multi-cycle instruction, that instruction is
not completed and the contents of P upon reset
may not necessarily be the address of the instruction
that would have been executed next. It may, for
example, point to an immediate operand if the reset
occurred during the second cycle of a LI or CI
instruction. Additionally, several instructions (JMP,
PI, PK, LR PO, Q) as well as the interrupt acknowledge sequence modify PO in parts. That is, they
alter PO by first loading one part then the other
and the entire operation takes more than one cyc.le.
Should reset occur during this modification process
the value pushed into P will be part of the old PO
(the as yet unmodified part) and part of the new
PO (already modified part). Thus care should be taken
(perhaps by external gating) to insure that reset
does not occur at an undesirable time if any signifi414
cance is to be given to the contents of P after a reset
occurs.
VCC Decoupling
The 3870 family devices have dynamic circuitry internally which requires a good high frequency decoupling capacitor to surpress noise on the Vcc line. A
.01 J1F or .1 J1F ceramic capacitor should be placed
between Vcc and ground, located physically close to
the 3870 device. This will reduce noise generated by
the 3870 to about 70-100 mVolts on the Vcc line.
Test Logic
Special test logic is implemented to allow access to
the internal main data bus for test purposes.
In normal operation the TEST pin is unconnected
or is connected to G N D. When TEST is placed at a
TTL level (2.0V to 2.6V) Port 4 becomes an output
of the internal data bus and Port 5 becomes a wiredOR input to the internal data bus. The data appearing
on the Port 4 pins is logically true whereas input data
forced on Port 5 must be logically false. When TEST
is placed at high level (6.0V to 7.0Vl. the ports act
as above and additionally the 2K x 8 program ROM
is prevented from driving the data bus. I n this mode
operands and instructions may be forced externally
through Port 5 instead of being accessed from the
program ROM. When TEST is in either the TTL
state or the high state, STROBE ceases its normal
function and becomes a machine cycle clock
(identical to the F8 multi-chip system WR ITE clock
except inverted).
Timing complexities render the capabilities associated with the TEST pin impractical for use in a user's
application, but these capabilities are thoroughly
sufficient to provide a rapid method for thoroughly
testing the 3876.
STANDBY POWER OPTION
If the standby power option has no.t been selected
Port O-bit 0 and 1 are readable and writeable.
If the standby power option is selected Port O-Bit 1
is readable only. Port O-Bit 0 remains readable and
writable although it is not connected to a package
pin. The standby power source (VSB) is connected
to Pin 4.
A .00l-lF capacitor must be connected to Pin 3. The
purpose of the capacitor is to decouple noise coupled
to the substrate of the circuit when VCC is switched
off and on. It IS recommended that Nickei-Cadmium
batteries (typical voltage of 3 series cells = 3.6V) be
used for standby power, since the MK3876 can automatically trickle charge the three Ni-Cad's. If more
than three cells in series are used, the charging circuit
must be provided outside the MK3876. Whenever
RESET-RAMPRT is brought low, the standby RAM
STAN BY POWER OPTION (Cont'd)
(64x8 bit words in PO/DC address space, 4032 to
409510 or FCO to FFF16) is placed in a protected
state. Also the RAM itself is switched from VCC
power to the VSB power. Two modes of powering
down are recommended. In the first mode, the processor must be interrupted early enough to save all
necessary data before the VCC falls below the minimum level. After the save is done, RESET can fall.
This prevents any further access of the RAM; VCC
may now fall. As the power comes up, the RESET/
RAMPRT signal should be held low until VCC is
above the minimum level.
The second mode may be used if a special save data
routine is not needed. The EXT INTERRUPT need
not be used and the only requirement to save the
RAM data is that RESET-RAMPRT be low before
VCC drops below 4.5V. For example if a few key
variables are to be stored in RAM and it is desired
that these be saved during a loss of power, two copies
of each variable are kept with an associated flag, thus
no interrupt and save routine is necessary. The
method of updating a variable is as follows:
- Clear Flag Word 1
- Update Variable (Copy 1)
- Set Flag Word 1
- Clear Flag Word 2
. Update Variable (Copy 2)
- Set Flag Word 2
Now execution may terminate at any time, even
during the update of a variable or flag word, causing
that byte in RAM to be bad data. There is always a
good data byte which contains either the most
recent or next most recent value of the variable.
Any copy of the variable where the flag word is
"set" is a good data byte. While this method significantly encumbers the data storage process, it eliminates the need for a power fail interrupt which both
reduces external circuitry and leaves the external
interrupt pin completely free for other use.
Figure 9 represents the internal circuitry which can
be connected to pins 3, 4, and 39 to provide this
Standby Mode. If the Standby Mode is selected,
switches A 1 and A2 are masked in the position
shown, thereby disconnecting the normal port circuitry from pins 3 and 4. Switches B1 and B2 are
masked in the position shown to allow pin 39 to become the control (RAMPRT) and pin 4 the power
(VSB) for the Standby Mode. If the Standby Mode is
not selected all switches are masked opposite of the
positions shown and pins 3 and 4 become normal
3870 type ports.
RAMPRT is an input signal used to control access to
the Standby RAM. If RAMPRT is high, access to the
64 Byte Standby RAM is permitted by the CPU via
the Program Counter (PO) of the Data Counter (DC).
The Standby RAM current is supplied by the series
pass transistor and a 4 to 12 mA current can be supplied out of pin 4 (Vsb) to trickle charge two Ni-Cad
cells (nominal 2.5 Volts). The resistors shown simulate device impedances that limit the current available at pin 4 so that the battery is not overcharged. If
RAMPRT is low, the Control Logic turns off the pass
transistor and the Standby RAM is maintained by a
current supplied by the battery connected to pin 4.
When RAMPRT is low, the CPU cannot access the
Standby RAM thereby protecting its contents as Vcc
fails.
The Standby RAM can be maintained by a capacitor,
however, a resistor and a diode will be required in
order to charge the capacitor to Vcc. Internal voltage
drops will not allow Vsb to go above 3 volts (typically) without this external resistor.
3876 Clocks
The time base for the 3876 may originate from one
of four sources.
The four configurations are shown in Figure 10.
There is an internal 26pF capacitor between XTL 1
and GND and an internal 26pF capacitor between
XTL 2 and GND, thus external capacitors are not
neccessarily required. In all external clock modes the
external time base frequently is divided by two to
form the internal (I) clock.
Crystal Selection
The use of a crystal as the time base is highly recommended as the frequency stability and reproducability from system to system is unsurpassed. The
3876 has an internal divide by two to allow the user
of inexpensive and widely available TV Color Burst
Cyrstals (3.58MYz). The following crystal parameters
and vendors are suggested for 3876 applications:
Parameters
a) Parallel Resonance, Fundamental Mode AT-Cut
b) Frequency Tolerance measured with 18pF load
(0.1% accuracy). Drive level10mW.
c) Shunt Capacitance (Co) = 7pF max.
d) Series Resistance (Rs)
Holder
f = 1MHz
f - 2MHz
f = 3MHz
f - 3.58MHz
f - 4MHz
Rs = 550 ohms max.
Rs - 300 ohms max.
Rs = 150 ohms max. *
Rs - 150 ohms max.
Rs = 150 ohms max.
HC-6
HC-33
HC-6
HC-18
HC-25
HC-33
*HC-18 or HC-25 holder may not be available at
3MHz.
415
SAVE ROUTINE REQUIRED, VSB;;;' 2.2 VOLTS
Figure 8a
VCC SUSTAINED BY CAPACITOR OR
BATTERY UNTIL RAMPRT BROUGHT LOW
r----'---I-~ ---J ~ I
I
I
~'----~f ~f_--t---J;1
I
I----I-
I
ACCESS TO
RAM INHIBITED
I ~ EXECUTION
- - - + - -....~~ BEGINS AGAIN
I
NO SAVE ROUTINE REQUIRED, VSB;;;' 2.2 VOLTS
Figure 8b
VCC----_~
MAIN POWER
FAILURE DETECTED
1
/ '
( )
~---;)
....
1-----
\-------11) )\-1_ _ _ _ _ _
416
~/
CLOCK CONFIGURATIONS
Figure 10
RC Mode
VCC
EiJ E2JR
-;-
~§3S39
o
--L Cexternal
i
External Mode
Crystal Mode
Open
(optional)
External
Clock
ATCutl-4MHz
~
Minimum R = 4KU
C = 26.5pF ± 2.6pF + CEXTERNAL
FREOUENCY VRS RC
LC Mode
4
I'
3
XTL 1
""
I'
I'
2
...... ,...
......
I'
......
:--.
"
I
L __ ~t_-
, r;-
t--..L
Cexternal (optional)
I"'-
Minimum L =0.1 mH
Minimum Q = 40
MINIMUM (4.5V ·5.5V, O°C _70°C)/
, X 10-7
I I
I
I I I
I '
J.
I
I
...J
P"-
M~XIMUM (4.~ - S.5Y, ~oC ;70:oCI:L
TYPICAL (TYPICAL UNIT AT VCC =5V. TA =25°C)
/
I
II
XTL 2
Maximum Cexternal = 30pF
I
L
2 X 10-1
3 X 10-7
4 X 10·7
(R) (CINTERNAL + CEXTERNALl
5 X 10-7
UNIT TO UNIT VARIATION = ± 12%
VARIATION FROM 4.5 to 5.5V
REFERENCED TO 5V = +7%-4%
VARIATION FROM O°C TO 70°C
REFERENCED TO 25°C = +6% ·9%
TOTAL VARIATION NOT CONSIDERING
VARIATION IN EXTERNAL COMPONENTS = ± 25%
6 X 10-7
C = 13pF ± 1.3pF + Cexternal
f~ 21TVIC
NOTE: The stray capacitance across the inductor
must be included as Cexternal in all calculations.
Suggested Crystal Vendors
418
a) Electro-Dynamics
5625 Foxridge Drive
Mission, Kansas 66201
913-262-2500
d) Erie Frequency Control
453 Lincoln Street
Carlisle, Penn 17013
717-249-2232
b) CRYSTEK
1000 Crystal Drive
Ft, Myers, Florida 33901
813-936-2109
e) Electronic Crystals Corp,
1153 Southwest Blvd,
Kansas City, Kansas 66103
913-262-1274
c) W.T. Liggett Corp.
1500 Worcester Rd.
Section 30
Framingham, MA 01701
617-620-1150
f) M-TRON Industries
P.O, Box 630
100 Douglas Avenue
Yankton, South Dakota
605-665-9321
"TIs
MK3876 PROGRAMMING MODEL
cE' "
~W
"CO
Figure 11
"'''-1
"'0)
OUT S
,-----------------------~4~IADC
'"C
:lJ
7
o
G')
INS*7
:lJ
EI
l DI
J,
I,
·ILNK
~
s
OUTS 6
w
"
2
INS 6
4 3 2 I
LIS L
G')
s
o
PO)
OUTS 0,1,4,5
11\15*0,1,4,5
lISU
AS
NS
XS
ASD
SCRATCHPAD
REGISTERS
o
I/O
PORTS
(4 )
-C»INVERTING
3
4
ROM
MEM
"5
2048X8
~
--IDC II
T+I~ 1... •
LR
ACCUMULATOR
I.~
LR:;'"
~~
IT, "
"C'~(PO
*
DS*
COM
It, C
SL I
PO tf
I..
FROM
TIMER 1 RAM
SL4
SRI
5R4
PK 2
LR
PROGRAM
COLJNTER
2KX8
HEX
OCTAL
H'020'
These Instructions set status
H'OAO'
The value of the external Interrupt input IS loaded to
Bit 7 of the ilcr.umulator (wIth Bits 0 through 6 IOdded
with zeros) when the instruction 'INS 6' is executed. This
Instruction also sets status.
H'OOO'
RESET
f
EXTERNAL INTERRUPT
Reset Tr<'Jnsfers PO to P and
then clears PO, leB Bit of W,
and Ports 4,5,6 and 7.
tt PO, P, DC, and DC 1 are 12 bit registers
Note
The instructions PI and PK are shown In two sequential parts.
(P11, PI2 and PK 1, PK21.
...
~
CD
ROM
MEM
LM
ST (DCl
RAM
64X8
o
m
r
INSTRUCTION EXECUTION
This section details the timing and execution. of the 3876 instruciton set. The 3876 executes the entire F8
instruction set with exact F8 timing. Refer to Figure 11 for a 3876 Programming Model.
F8 INSTRUCTION SET
ACCUMULATOR GROUP INSTRUCTIONS
MACHINE
MNEMONIC
OPCQDE
OPERATION
OPERAND
FUNCTION
CODE
BYTES
CYCLES
LONG
SHORT
/.S
12MHzl
OVR
STATUS BITS
ZERO CRY
SIGN
Add Carry
LNK
A_(A) +CRY
19
1/0
I/O
I/O
I/O
Add 1rnmed iate
AI
A-(Al + H 'ii'
24ii
I/O
1/0
I/O
I/O
And Immediate
NI
A-(AIAH'II'
21ii
Clear
CLA
A .. H'OO'
70
+1
1/0
1/0
Compare Immediate
CI
H'!I'-f (A)
Complement
COM
A+(A) + H'FF'
18
I/O
Exclusive or Immediate
XI
A_(Aj + H'ii'
23ii
I/O
Increment
INC
A-fA) + 1
IF
Load Immediate
LI
A_H'II'
2011
Load Immediate Short
LIS
A_H'Oi'
7,
25ii
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OR Immediate
01
A ... (A) VH 'ij'
22ii
I/O
I/O
Shift Left One
SL
Shift Left 1
13
I/O
I/O
Shift left Four
SL
Shift Left 4
15
I/O
I/O
Shift Right One
SR
Shift Right 1
12
I/O
Shift Right Four
SA
Shift Right 4
14
I/O
BRANCH INSTRUCTIONS In all conditional branches PO-( PO) + 2 if the test condition is not met. Execution is complete
in 3 short cycles.
OPERAND
OPCODE
CODE
FUNCTION
Branch on Carry
Be
P04iPOl-l-1+ H'aa' If CRY
Branch on Positi'le
BP
PO-(POl
S'IGN
Branch on Zero
~
Zero
~
1- TEST CONDITION
Iz~~ol IS~~N I
SHORT
LONG
82aa
-I-
1
-I-
H'aa' If
81aa
-I-
1
-I-
H'as' if
84aa
-I-
1 + H'aa'
8taa
If any test IS true
JRY
Branch If Negative
91aa
PO... (POI +1 + H'aa'
8M
If SIGN =0
Branch if No Carry
PO ... (PO) +1+ H'aa'
BNC
92aa
If CARRY" 0
Branch jf No Overflow
98aa
PO"'{PO) +l+H'aa'
BNO
If OVA = 0
Branch if Not Zero
PO.(POI+l+ H'aa'
BNZ
94"
If ZERO" 0
Branch If False Tesl
BF
PO"(PQ) -1-1+ H'aa'
! TEST CONDITION
jf all false test bits
I ""~ I
Branch If tSAR (Lower)
n
..,; I
""I
BA7
9taa
I ,.., I
10~F IZE~O IC~y ISI~N:
PO_(POl+1+ H'aa' If
87aa
tSARLO
PO,,(PO)+2If ISARL
=.
Branch Relative
BA
PO" (POl+1+ H'aa'
90aa
Jump·
JMP
PO ... H'aaaa'
29aaaa
*Privileged instruction, Accumulator contents altered during execution JMP instruction.
420
STATUS BITS
!.IS
(2MHz
t",
PARAMETER
Time base period, all
external modes
External Clock Pulse Width
High
External Clock Pulse Width Low
MIN
MAX
250
1000
ns
90
100
700
700
ns
ns
Internal Clock Period
2tO
4t
6t
NOTES
4MHz-1MHz
Short Cycle
Long Cycle
WRITE
tw
Internal WR ITE Clock Period
I/O
tdl/O
Output delay from
internal WR ITE Clock
tsl/O
Input Setup time
to WR ITE Clock
1000
tl/O-s
Output valid to STROBE
Delay
3t
-1000
3t
+250
tsl
STROBE Low Time
8t
-250
12t
+250
0
UNIT
1000
ns
50pF plus
one TTL load
ns
I/O load =
50pF + 1 TTL
STROBE Load=
50pF + 3 TTL
STROBE
RESET
EXTINT
tRH
tEH
RESET Hold Time, Low .•
EXT I NT Hold Time,
Active and I nactive State
6t
+750
6t +
750
2t,\>
ns
ns
ns
To trigger
interrupt
To trigger
timer
423
TIMER AC CHARACTERISTICS
Definitions:
Error = Indicated time value - actual time value
tpsc
= tx Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±6t
Cumulative interval error, free running (Note 3) ............... , ..................... 0
Error between two Timer reads (Note 2) ................................... ±(tpsc + t to -(tpsc +t to -(tpsc + 7t to -8t
Load Timer to stop Timer error (Note 1) ........................... +t to -(tpsc + 2t to -(tpsc + 8t to -9t
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) ..................................+t to -(tpsc +2t <1»
Minimum pulse width of EXT INT pin ..........................................2t
Event Counter Mode:
Minimum active time of EXT INT pin ............................................2t<1>
Mir:limum inactive time of EXT INT pin ......................................... ·2t<1>
1. All times wh ich entail loading, starting, or stopping the Timer are referenced from the end
of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the last machine
cycle of the I N or I NS instruction.
3. All times which entail the generation of an interrupt request are referenced from the start
of the machine cycle in which the appropriate interrupt request latch is set. Additional
time may elapse if the interrupt request occurs during a privileged or multicycle instruction.
4. Error may be cumulative if operation is repetitively performed.
CAPACITANCE
TA = 25°C, f=2MHz
MIN
SYMBOL
PARAMETER
CIN
Input Capacitance: I/O Ports, RESET/
RAMPRT, EXTINT, TEST
CXTL
Input Capacitance: XTL1, XTL2
20.5
MAX
UNIT
7
pF
32.5
pF
NOTES
Unmeasured
Pins
Grounded
DC CHARACTERISTICS
TA
= O°C to 70°C, VCC =+5V ± 10%, I/O POWER DISSIPATION..; 100mW
SYMBOL
PARAMETER
ICC
Power Supply Current
Po
424
Power Dissipation
MIN
TEST CONDITIONS
MAX
UNIT
93
.mA
Outputs Open
440
mW
Outputs Open
DC CHARACTERISTICS (Cont'd)
PARAMETER
MIN
MAX
UNIT
VIHEX
External Clock
Input High Level
2.4
5.8
V
VILHEX
External Clock
I nput Low Current
-0.3
0.6
V
IIHEX
External Clock
Input High Current
100
!lA
VIHEX = VCC
IILEX
External Clock
I nput Low Cu rrent
-100
!lA
VILEX = VSS
2.0
5.8
V
2.0
13.2
V
-0.3
0.8
SYMBOL
VIH
VIHOD
VIL
IlL
IL
10H
10HDD
10L
Input High Level
Ports,RESET1, EXT INTI
Open Drain Input
High Level
Input Low Level
Ports, RESET1, EXT I NT 1
Input Low Current
Ports, RESET2, EXT INT2
Leakage Current
Open drain ports,
'R"E'SE'T 3, EXT INT3
Output High Current
Standard ports, R ESET2
EXT INT2
OUTPUT High Current
Direct Drive Ports
Output Low Current
10 ports
IOHS
STROBE Output High Current
IOLS
STROBE Output Low Current _
VIHRPR
VILRPR
Input High Level
For RAM Protect Function
To be effective.
lnput High Level
For RAM Protect Function
To be effective.
VSB
Standby VCC
for RAM
ISB
Standby current
ICHARGE
Trickle charge
available on VSB
with V CC=4.5 to 5.5
-1.6
+10
-5
NOTES
mA
VIL=O.4V
!lA
VIW 13. 2V
VIN=O.OV
!lA
!lA
VOW2.4V
VOH=3.9V
-0.1
mA
VOH = 2.4V
-1.5
mA
mA
VOW1.5V
VO W ·7V
-100
-30
-8.5
1.8
mA
VOL=O.4V
-300
!lA
VOW2.4V
5.0
mA
VOL = O.4V
1.9
5.8
V
Guaranteed .1 V less
thanVIHforRESET
-0.3
0.4
V
Guaranteed .1 V less
than V I L for RESET
3.2
5.5
V
6
3.7
mA
mA
VSB =5.5V
VSB = 2.2\1
-.8
-12
mA
-4.5
-15
mA
VS B= 3.8VR'ESE'f1
RAMPRT high
VSB= 3.2V
* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. RESET and EXT INT have internal Schmit triggers giving minimum .2V hysteresis.
2. RESEi' or EXT INT programmed with standard pull-up
3. RESET or EXT I NT programmed without standard pull-up
4. Power dissipation for 1/0 pins is calculated by~(Vcc - VIL) q IILI) +k(VCC - VOH ) II 10H I) +~(VOL) (lOL)
425
AC TIMING DIAGRAM
Figure 12
External Clock
Internal ERATING TEMPERATURE VS. I/O POWER DISIPATION
Figure 19
100
-
~
50
...
i'ooo..
~~
'U
100
200
300
...... ......
,
~
IC
....... ..........
400
CE ~A
........
II I
500
600
PDI/O MW
430
~
100.....
r-
I"--
l. I
1000
TRICKLE CHARGE CURRENT
Figure 20
ITC VS. VSI3
VCC= 5.5V
9.0mA
f'....
ITC
8.0mA
"
"
7.0mA
........
'" "
...........
.......
""
3.5V
3.2V
4.0mA
......
...............
3.8V
4",
"'- ~
ITC
VCC= 4.5V
"'" ......."'-
3.0mA
"'- .........
"-
2.0mA
3.2V
3.5V
"- ~
3.8V
431
PACKAGE DESCRIPTION: 40-Pin Dual In-Line Ceramic Package
1-------1- - 2000'
=m=
I
020
~~
,::::~r==f\~D~J~'=11m []
I
I/O<=>
B<==>
MK 3870
I/O
to
.....
01/0
----------------------------------------.....
F8 FAMILY
0
64 byte RAM on the CPU chip
0
Two bi-directional, 8-bit I/O ports
I/O<=:>
0
8-bit arithmetic and logic unit, supporting both
binary and decimal arithmetic
I/O<=:>
0
Interrupt control logic
0
Both external and crystal clock generating modes
I/O<=:>
0
Over 70 instructions
0
Low power dissipation-typically less than
330mW
p
E
R
I
P
H
E
R
A
L
<=:>
I/O<=:>
M
E
I/O<=:>
<=:)
I/O<=:)
s
<
>
M
0
R
Y
<=:>
I/O<=:)
GENERAL DESCRIPTION
I/O
The MK3850 is the Central Processing Unit (CPU)
for the F8 Microprocessor family.
It is used in
conjunction with other F8 family devices to configure the optimal microprocessor system for the
amount of RAM, ROM/PROM, and I/O required in
the users application. A minimum system may be
configured with as few as two devices (CPU & PSU),
while larger systems may have up to 64K bytes of
memory, 128 I/O ports, direct memory acccess,
and even multiple processors. Single chip microcomputer systems are also possible using the
MK3870
PIN NAME
DESCRIPTION
TYPE
DBO-OB7
'--__---'
PIN CONNECTIONS
~
I
40
WRITE
2
39
XTLX
VOO
3
38
XTLY
EXT RES
RC
VGG
4
37
f7003
5
36
110 04
DB3
6
35
DB4
I/O 13
7
34
lIO 14
lIO 12
8
33
I/O 15
DB2
D002
9
10
MK3850
32
DB5
31
Di505
lI001
II
30
I/O 06
DB I
12
29
DB 6
II
13
28 110 16
lIO 10
14
27
110 17
DB0
15
26
DB7
I/O 00
16
25 I/O 07
ROMC0
17
24
VSS
ROMC I
18
23
iN'FliEQ
ROMC 2
19
22
ICB
ROMC 3
20
21
ROMC 4
I/O
441
FUNCTIONAL PIN DEFINITION
and WRITE are clock outputs which drive all
other devices in the F8 family.
XTLX and XTL Yare used when generating the
system clock in the Crystal mode. The XTL Y pin
is also used for operating in the External clock
mode.
ROMCO through ROMC4 are control outputs which
control logic operations for other devices in the F8
ROMCO through ROMC4 assume a state
family.
early in each machine cycle and hold that state for
the duration of the cycle.
DBa through DB7 are bi-directional data bus lines
which link the 3850 CPU with all other F8 chips in
the system. These are multiplexed lines, used to
transfer data and addresses.
170 00 through I/O 07 and I/O 10 through I/O 17
are Input/Output port bits through which the CPU
communicates with logic external to the microprocessor system.
EXT RES may be used to externally reset the
system. When this line is pulled low, the program
,counter is set to address H '0000'.
INT REO is used to signal the CPU that an interrupt
is being requested. The 3851 PSU and 3853 SMI
devices contain logic to initiate interrupt requests
~y pulling INT REO low. The CPU acknowledges
I~terrupt requests by outputting appropriate ROMC
signal sequences.
!CB !ndicates whether or not thLCPU is currently
Ignonng the INT REO line. If ICB is low the CPU
will respond to interrupt requests, if itJ3 is high
'
the CPU will ignore interrupt requests.
RC is not use~ and should be connected to VSS for
normal operation.
VSS = OV
VDD = +5V ± 5% @ 80m A max.
VGG = +12V ± 5% @ 25mA max.
CPU ORGANIZATION
This section describes the basic functional elements
of the MK3850 CPU. These elements are shown on
the Functional Block Diagram of the CPU in Figure 3.
Instruction Register (I R)
The. Instruction ~egister s~ores t~e instruction operation code dUring the instructIOn execution sequence. The OP Code is loaded into the Instruction
Register from the data bus at the end of the execution sequence for the previous instruction. The last
operation associated with each instruction is therefore the fetch of the OP code for the next instruction
to be executed (unless an interrupt initiates the
interrupt service sequence). The newly fetched OP
code is latched into the Instruction Register at the
start of the next machine cycle (as defined by the 1-0
transistion of the WRITE clock).
Most OP codes are either 4 or 8 bits long. For those
instructions where the OP code may be completely
442
specified using the upper 4 bits of the machine
instruction, the lower 4 bits are used to specify an
operand. This operand may specify a Scratch Pad
Register, Port, or a 4-bit Immediate Constant. For
this reason, the lower 4 bits of the instruction register
are bussed to both the Scratch Pad Register Select
logic and the Right Multiplexer Bus.
,
Control Unit
The Control Unit for the CPU consists of the Control
ROM (CROM) and the State Counter. The CROM is
responsible for generating all system timing and
control signals required for controlling data flow
within the F8 CPU and other F8 circuits.
The inputs to the CROM logic are the 8 bits from
the instruction register, 4 bits from the State
Counter, three internal status signals (" ALU
RESULT = 0", "ISARL = 7", and the status of the
Interrupt Control Bit (lCB) and two external conditions (INT REO and Reset).
The I R inputs to the control logic identify which
instruction is being executed, while the State Counter
inputs define the machine cycle within the instruction execution sequence. The status of the ICB
together with INT REO are used to determine
whether the interrupt sequence is to be initiated in
!i~u. of fetching a new instruction. The reset input
initiates the restart sequence. The remaining two
internal signals are used to make branching decisions.
The outputs generated by the control logic fall into
th ree groups.
External Commands
• Next State Outputs
I nternal Commands
External ~ommands are coded into the 5 system
control lines (ROMCO - ROMC4). Descriptions of
these commands are shown in Table 2.
The next state outputs are 4 signals representing the
next state of the State Counter. These signals are
decoded during the present machine cycle and are
strobed into the State Counter at the start of the
next cycle. At that time these signals become the
present state inputs to the CROM from the State
Counter and new next State Outputs are generated.
The internal commands control data flow within
the F8 CPU circuit. These commands include
selecting the .ALU operation to be performed, gating
the proper Input onto the Left and Right Multiplexer Busses, gating the Result Bus into the proper
register or onto the Data Bus, selecting the proper
Scratch pad Address input (either the ISAR or the
lower 4 bits of the I R), and providing a signal to the
timing circuits to force either a long or a short cycle.
Arithmetic And Logic Unit (ALU)
The 8-bit parallel ALU is the heart of the CPU.
After receiving commands from the control circuits
on the CPU circuit, the ALU performs the required
arithmetic or logic operations (using the data
presented on the two input busses) and provides
the result on the Result Bus. The arithmetic operations that can be performed in the ALU are binary
add, decimal adjust, add with carry, decrement, and
increment. The logic operations that can be performed are "AND", "OR", "EXCLUSIVE OR",
and "1's COMPLEMENT". Associated with the left
input port to the ALU is a shifter, a complementer,
and a low order carry (CO). The shifter can shift
the left Multiplexer Bus to the left or to the right by
1 or 4 bits. The complementer can perform the 1 's
complement of the left Multiplexer Bus before
providing it as an input to the ALU. Co participates
whenever the ALU performs the add with carry
operation. Normally it is a zero, but may be forced
to a 1 or may take the state of thf! carry bit in the W
register. Besides providing the result on the Result
Bus, the ALU also provides four signals representing
the status of the result. These signals, stored in the
Status (W) register, represent carry, overflow, sign
and zero condition of the result of the operation.
The Zero condition is also used by the control circuits during execution of the branch instructions.
In addition to performing arithmetic or logic operations, the ALU sometimes acts simply as a passage
way to allow the contents of the various internal
registers to be placed on the Result Bus so that they
may be transferred to another register. For example,
when the W register is stored in the Scratchpad, it
first passes unaltered through the ALU on to the
Result Bus, then into the Scratchpad register.
The Accumulator
The Accumulator is the principle register for data
manipulations within the CPU. Using the ALU, the
8-bit contents of the Accumulator may be complemented, incremented, or shifted left or right. Its
contents may also be logically or
arithmetically
combined with the contents of the Scratch pad or
memory locations, with the result replacing the
original contents of the Accumulator.
FIGURE 1 - THE ISAR REGISTER
5
r---I
4
3
~I~I
NOT INCREMENTEDJ
OR DECREMENTED
o
2
.-BITNO.
I""'--'I""-'IISAR
"""""""1
llNCREMENTED AND
DECREMENTED
Additional saving may be further achieved by utilizing
another key feature of the Scratchpad which permits
the direct access of registers H'O' through H'B'.
These registers shou Id be reserved by the programmer
for those variables most frequently accessed.
Scratch pad registers H'9' through H'F' (0 11' through
0'17') have special significance since they have
linkages directly with the status word (W), the Data
Counter (DC), Stack Register (P) and Program
Counter (PO) as shown in the F8 Programming Model
(Figure 7). These linkages are implemented using
single byte F8 instructions such as:
LR K,P
wh ich transfers the 16-bit contents of the Stack
Register (P) into the 'K' register pair (Scratchpad
registers H'C' and H'D'). The contents of the accumulator are undisturbed by the execution by these
instructions.
The Status Register
The status register (also called the W register) hoi
five status flags as shown in figure 2.
FIGURE 2 - THE STATUS REGISTER
The Scratch pad And ISAR
3
The Scratch pad consists of 64 8-bit RAM data
registers (H'OO' thru H'3F') which are available to
the programmer for the high speed access and manipulation of data. For most control/logic replacement
this will provide all the data storage required.
'-BITNO.
STATUS REGISTER (WI
SIGN
All of the 64 Scratch pad registers are indirectly
accessable through the use of the 6-bit Scratchpad
address register, ISAR. In this way, any scratchpad
register may be loaded to/from or added to the
accumulator (binary or BCD); logically 'ANDED'
or 'exclusive OR'ED' with the Accumulator; or
decremented directly without disturbing the Accumulator. The contents of the least significant 3-bits of
ISAR may be selectively auto-incremented, autodecremented, or left unchanged (at the programmer's
option) whenever the Scratch pad is accessed .using
ISAR(see Figure 1).
ISAR itself may be loaded either to/from the lower
6-bits of the accumulator, or loaded in 3-bit halves
using the single byte immediate instructions LlSU n
and LISL n. The ability to independently modify the
upper and lower halves of ISAR plus the autoincrement/auto-decrement options, can be used
very effectively by the programmer to minimize the
size of his programs.
CARRY
ZERO
1--_ _ _ _ _ OVERFLOW
INTERRUPT MASTER
ENABLE
Note that status flags are selectively modified following execution of different instructions. Table 4
defines the way in which individual F8 instructions
modify status flags.
Sign (S BIT)
When the results of an ALU operation are being
interpreted as a signed binary number, the high
order bit (bit 7) represents the sign of the number.
443
At the conclusion of instructions that may modify
the accumulator bit 7, the S bit is set to the complement of the accumulator bit 7.
Carry (C BIT)
The C bit may be visualized as an extension of an
8-bit data unit, i.e., the ninth of a 9-bit data unit.
When two bytes are added, and the sum is greater
than 255, then the carry out of the high order bit
appears in the C bit. Here are some examples:
C 76 543 2 1 0 _Bit Number
Accumulator contents:
0 1100 10 1
Value added:
0 1 1 1 01 1 0
Sum: 0 1 1 01101 1
There is no carry, so C is reset to O.
C 765432 1 0 _ B i t Number
Accumulator contents:
1001110 1
Value added:
1 1 0 1 00 0 1
Sum: 1 01 101 1 1 0
TABLE 1 - SUMMARY OF STATUS BITS
OVERFLOW
CARRY7 @ CARRY 6
ZERO
ALU7 A ALU6 A ALU5 A ALU4 A ALU3 A
CARRY
CARRY7
SIGN
ALU7
ALU2
A
ALUl
A
ALUO
External Reset
When the EXT RES (External Reset) signal is pulled
low and then returned high, the Program Counter
(PO) is set to 0, causing the program origined at
memory location 0 to be executed. The Interrupt
Control status bit is also set low, inhibiting interrupt
acknowledgement. The system is locked in an idle
state while EXT RES is held low.
There is a carry. so C is set to 1.
Zero (Z BIT)
Timing Circuit
The Z bit is set whenever an arithmetic or logical
operation generates a zero result. The Z bit is reset
to 0 when an arithmetic or logical operation could
have generated a zero result, but did not.
Overflow (0 BIT)
When the results of an ALU operation are being
interpreted as a signed binary number, since the
high order bit (bit 7) represents the sign of the
number, some method must be provided for indicatinQ carries ouf of the highest numeric bit (bit 6).
This IS done using the 0 bit. After arithmetic operations, the 0 bit is set to the Exclusive-OR of
carries out of bits 6 and bits 7. This simplifies signed
binary arithmetic and is described in the Guide to
Programming the F8. Here are some examples:
Accumulator contents:
Value Added:
765432 1 O_Bit Number
1 01 1 001 1
01110001
Sum :.......----~ 1 00 1 00
1
There is a carry out of bit 6 and out of bit 7, so the 0
bit is reset to 0 (1@1 = 0). The C bit is set to 1.
76 543 2 1 0
Accumulator contents:
Value Added:
Sum:
~Bit
Number
01100111
00100100
10001011
A machine cycle is either 4 or 6 periods long, with
all instructions requiring between 1 and 5 machine
cycles to complete their execution sequence.
The Data Bus
The Data Bus is used for transfering all address and
data information between F8 System components.
Th is includes Port Addresses, Memory Addresses,
Read/ Write Memory Data, and Input/Output Port
Data. Memory Address transfers are accomplished
using two successive 8 bit transfers to complete the
16-bit Memory Address.
The three conditions
requiring Memory Address transfers are:
1. When a three-byte instruction specifies a memory
address in the second and third bytes.
2. When data is being moved between DC or PO
registers and associated scratchpad registerS.
3. During the interrupt acknowledge sequence, when
the interrupt vector is loaded into PO.
"...
There is a carry out of bit 6, but no carry out of bit
7; the 0 bit is set to 1 (1@0 = 1). The C bit is reset
to O.
Interrupts (lCB BIT)
External logic can alter program execution sequence
within the CPU by interrupting ongoing operations,
however interrupts are allowed only when the ICB
bit is set to 1.
444
The timing circuit generates all the timing signals
for the entire microcomputer. The two primary
timing signals are and WRITE. The Instruction
Execution Sequence for each instruction is timed
with these signals. The falling edge of WR ITE marks
the beginning of a new machine cycle, while is
used to time the length of the individual machine
cycles.
I/O Ports
The 16 address pins which most
reauire are used bv the 3850 for
Data may be transferred, via these
between the 3850 CPU and logic
microprocessor system.
microprocessors
two I/O ports.
two I/O ports,
external to the
While other F8 devices provide additional I/O ports,
the two I/O ports on the 3850 CPU execute data
transfers twice as fast, since they do not use the
external Data Bus.
Observe that the data path between the accumulator
and the two CPU I/O ports is entirely within the
3850 CPU chip.
FIGURE 3 - MK 3850 CPU FUNCTIONAL DIAGRAM
8 BIT
ALU
LEFT
MULTIPLEXER
BUS
ALU RESET=O
ISARL=7
CONTROL
AND
GND
+5
ROM
LOGIC
+12
ttl
POWER
LINES
INSTRUCTION EXECUTION SEQUENCE
All instructions are composed of long machine
cycles (six periods) and/or short machine cycles
(four periods). The long cycle is sometimes referred
to as 1.5 cycles. Figure 8 illustrates the short cycle
(PWS) and the long cycle (PWU. Observe that
WRITE high appears at the end of each machine
cycle.
The simplest instructions of the F8 instruction set
execute in one short cycle while the most complex
instruction (PI) requires two short cycles plus three
long cycles. Every instruction's execution sequence
ends with the next instruction OP code being fetched
from memory. The OP code is loaded into the CPU's
instruction register where it is decoded by the CPU's
Control Unit.
The only instructions which may be executed in a
single cycle are those which do not require the use
of the Data Bus. This permits the Data Bus to be used
ROMeo
THRU
ROMC4
DBD-DB7
I/O DO-I/O 07
I/O 10-1/0
17
to fetch the next instruction OP code simultaneously
with the performance of the operation indicated
by the current OP code. ROMC state 0 is used to
specify the machine cycle during which a fetch is
occurring, and therefore is used for all one cycle
instructions.
Other instructions require more than one cycle to
execute and use different ROMC states to specify
the operation to be performed during each of the
required cycles. The last cycle of each instruction,
however, will always be the ROMC state 0 in order
that the next OP code may be fetched.
The ROMC control signals are brought externally
to the CPU itself in order to coordinate those operations which affect the memory referencing registers
located on F8 devices other than CPU. Among these
registers are the Program Counter, Stack Register
and Data Counter. Most of the ROMC control states
indicate those operations involving the contents of
these registers, as shown in Table 2.
445
During this time, the high and low bytes of the
Vector address from the interrupting device are
transferred (via the Data Bus) into the Program
Counter(s) and the Interrupt Control Bit (Bit 4
of the Status Register) is cleared to zero.
There are four different devices in the F8 Microprocessor family which contain the set of previously
mentioned system registers (Program Counter, Stack
Register, and Data Counter). These are the MK3853
SMI, MK3852 DMI, MK3851 PSU, and MK3871
PIO. Every F8 microprocessor system must contain
at least one of these devices in addition to the
MK3850 CPU. For those systems incorporating more
than one of these devices, the resultant duplication
of the Program Counter, Stack Register, and Data
Counter is completely transparent to the user. This
is accomplished since each device in the system receives the ROMC signals from the CPU and thus
remains synchronized with all other devices.
The response time for acknowledging an interrupt
request can vary from 26 to 29 output
drive the slave XTL Y input.
447
FIGURE 6 - EXTERNAL CLOCK
a long (6 clock period) cycle. Thus the entry:
S
VSS
_~R=C_-r--I
XTLY
represents an instruction that executes in one short
cycle. The entry:
S
3850
CPU
L
S
XTLX
EXTERNAL
CLOCK
represents an instruction that executes in three
cycles; the first is a short cycle, the second is a long
cycle, the third is a short cycle.
ROMC STATE
This is the state, as identified in Table 2 which is
output by the 3850 CPU in the early stages of the
instruction cycle.
Figure 8 illustrates the AC characteristics of the
clock signal needed for external mode clock g~nera
tion, plus the AC characteristics of the
«DC));
DC ~(DC) + 1
Set status flags on basis
of «DC)) + (A) + 1;
DC~(DC) + 1
DC~(DC) +A
3S
4
3S
4
3S
4
3S
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1/0
-
0
1/0
0
-
-
-
-
0
1/0
0
1/0
-
-
-
-
-
-
-
-
-
-
FUNCTION
S
PO+-(PO) + 2
because (ISAR L) = 7
PO <- (PO) + H'ii' + 1
because (ISARL) =1= 7
Test t /\ W. reg ister
Res =1= 0 so PO = (PO)
+ H'ii' + 1
Test t 1\ W. register
Res f. 0 so PO = (PO)
+2
A <- (I/O Port 0 or 1)
DB +- Port address (2
through 15)
A ~ (Port 2 through 15)
I/O Port 0 or 1 ~ (A)
-
-
-
x
1/0
?
1/0
1/0
1/0
?
-
-
-
-
0
0
1/0
1/0
0
0
1/0
1/0
-
-
-
-
-
2
-
-
-
-
y
3S
0
1
3S
-
-
-
-
-
x
-
y
-
-
-
-
x
DB ~ Port address (2
through 15)
Port (2 through 15) <(A)
A <- (A) + (r) Binary
A <- (A) + (r) Decimal
A+- \A) 0 (r)
A +- (A) /\ (r)
IDLE
POL ~ Int. address
(lower byte); PCl +-PO
POU <-Int. address
(upper byte)
IDLE
P~PO,
PO<-O
PROGRAMMING MODEL
Figure 7 shows a Programming Model of the F8
Microcomputer system. This diagram is intended to
depict the various data transfers and manipulations
which are facilitated by the instruction set of the
F8. Every F8 "system configuration will contain
the basic functional elements shown in this diagram,
with the exception of the Auxiliary Data Counter
(DC1). The Auxiliary Data Counter is available
only in those systems incorporating the MK3852
Dynamic Memory I nterface, the M K3853 Static
Memory Interface, or the
MK3870 single chip
F8 Microcomputer.
FIGURE 7 - F8 PROGRAMMING MODEL
CPU - - - - - - - \
/
, - - - - - - - - - - . . - 1 ADC
).,......-,..r:;:::::;--~ LN K
OUTS P, OUT P P
OUTS P, OUT P P
LlSL
(PO)
ISAR
LlSU
SCRATCHPAD
REGISTERS
AUX DATA
COUNTER
OUTS P, OUT PP
• AS
NS
XS
ASD
INS' P. IN' PP
10
PORTS
(128)
MEM
(64K)
MEM
(64K)
PO
PROGRAM
COUNTER
INT. VECTOR
INTERRUPT
LM
DC
'THESE INSTRUCTIONS SET STATUS
H'OOOO' RESET
NOTE: The instructions PI and PK are
shown in two sequential parts
(PI" PI2 and PK1, PK2).
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Above which useful life may be impaired)
VGG ... , . , , , , , , , , , ... , ; .... , ..... , ....... , . , , . , ... , .. , , ... , . , ... , . , , , .. +15V to -0,3V
VDD ............ , . , .... , , , , , .. , . , . , . , . , , , . , ............ , . , ... , ..... , .... +7V to -0.3V
RC, XTLX, and XTL Y , . , . , , . , , , , ........ , , ..... , ... +15V to -0.3V (RC with 5Kr2 series resistor)
All other inputs, , , .. , , , , , , , .. , .. , ...... , ............... , .. , . , .... , .. , , . , . , , +7V to -0,3V
Storage temperature .... , ........ , . , . , .. , .. , , , .. , .... , ... , ... " , ......... ,-55°C to +150°C
Operating temperature ... , , , . , , , ..... , . , ....... , , , .. , , . , . , ........... , .... , .. 0° C to +70° C
NOTE: All voltages with respect to VSS,
455
SUPPLY CURRENTS
TYP.
MAX.
UNITS
TEST CONDITIONS
VDD Current
30
80
mA
f" 2 M Hz, Outputs
unloaded f· 2 MHz
VGG Current
15
25
mA
Outputs unloaded
MAX.
UNITS
TEST CONDITIONS
250
225
MS
ns
ns
MS
MS
ns
ns
ns
P
<
::j
--~
I
~"'4~
l::td5
I
/
i
I
ICB (1)
~I
{
tsx
I
I
I
~I
(1)
I CB wi II go from a 1 to a 0 foil owi ng the execution of the Eli nstruction and wi II go from a 0 to 1
following either the execution of the 01 instruction or the CPU's acknowledgement of an interrupt.
(2)
This is an input ot the CPU chip and is generated by a PSU or 3853 MI chip. The open drain outputs of these chips are all wire "AN Oed" together on this line with the pull-up being located on the
CPU chip. For a 0 to 1 transition the delay is measured to 2.0V.
Symbols are defined in Table 5
459
FIGURE 12 - A SHORT CYCLE INSTRUCTION FETCH
pW x __
XTLY
IC-1
I_I
~PW1
J--p\
OP CODE FOR NEXT INSTRUCTION
I
-,
NEXT
INSTRUCTION
Symbols are defined in Table 5
FIGURE 13 - A LONG CYCLE INSTRUCTION FETCH (DURING DS ONLY)
ROMC---------------I----~)(~___________T~R~U~E_R~O~M~C~S~TA~T~E~O~______~~---I-td 3
-1
\
______________
460
-l :
I
~---------------------------------J~OPCODEFORNEXT
ONE CYCLE OF THE SINGLE, LONG
CYCLE DS INSTRUCTION
(DECREMENT SCRATCHPAD)
Symbols are defined in Table 5
I-tdb 3
I INSTRUCTION
I
NEXT
!NSTRLJCTlON
FIGURE 14 - MEMORY REFERENCE TIMING
(WRITE)
__L_-~_-~~~_-~~_~I------------------~·I
I:::~~~~~~~~~~~~~~~~~-P-W-S-_-_-_-_-_~_PW
________________
"
J
~I
I
I
~----------tdb1----------~
I
STABLE
~I'-_....JL""'_-_-_-_""""_~
I I
1
I
1
I
I
DATA BUS (1)
tdbO-.j
(HIGH IMPEDANCE)
__ ____________________________
-J><
DATA BUS
---.l
_I
--------------------------------------~)(
DATA BUS
1.
tdb4
tdb5
114--I-
DATA STABLE
________________________________________--J)(
- - - - I I..
~I
DATA BUS
STABLE
DATA STABLE
tdb6
1""'.1-----
Timing for CPU outputting data onto the data bus.
Delay tdb1 is the delay when data is coming from the accumulator.
Delay tdb2 is the delay when data is coming from the scratch pad (or from a memory device).
Delay tdbO is the delay for the CPU to stop driving the data bus.
2.
There are four possible cases when imputting data to the CPU, via the data bus lines: they oepend on the data path and
the destination in the CPU, as follows:
tdb3;
tdb4;
tdb5;
tdb6;
Destination
Destination
Destination
Destination
-
IR (instruction Fetch) - See Figure 2-10 for details.
Accumulator (with ALU operation - AM)
Scratch pad (LR K,P etc.)
Accumulator (no ALU operation - LM)
In each case a stable data hold time of 50 nS from the WRITE reference point is required.
Symbols are defined in Table 5
461
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Above which useful life may be impaired)
VGG ................................................................... +15V to -0.3V
VDD .................................................................... +7V to -0.3V
RC, XTLX, and XTL Y .............................. +15V to -0.3V (RC with 5Kn series resistor)
All other inputs ............................................................ +7V to -0.3V
Storage temperatu re ......................................................-55° C to + 150° C
Operating temperature ....................................................... O°C to +70°C
NOTE: All voltages with respect to VSS.
SUPPLY CURRENTS (MK3850N-3, MK3850P-3)
SYMBOL
PARAMETER
TYP.
MAX.
UNITS
TEST CONDITIONS
100
VOO Current
30
80
mA
f = 2 MHz,
Outputs unloaded
IGG
VGG Current
15
25
mA
Outputs unloaded
TEST CONDITIONS
MIN.
SUPPLY CURRENTS (MK3850N-13 , MK3850P-13)
SYMBOL
PARAMETER
TYP.
MAX.
UNITS
100
VOO Current
MIN.
35
90
mA
IGG
VGG Current
20
33
mA
Outputs unloaded
TYP.
MAX.
= 2 MHz, Outputs
unloaded
f
SUPPLY CURRENTS (MK3850P-23)
SYMBOL
PARAMETER
100
VOO Current
IGG
VGG Current
MIN.
UNITS
TEST CONDITIONS
40
100
mA
f = 2 MHz, Outputs
unloaded
25
40
mA
Outputs un loaded
ORDER INFORMATION
PART NO.
462
PACKAGE TYPE
TEMPERATURE RANGE (TA)
MK3850N-3
Plastic
O°C to +70°C
MK3850P-3
Ceramic
O°C to +70°C
MK3850N-13
Plastic
_40°C to +85°C
MK3850P-13
Ceramic
_40° C to +85° C
MK3850P-23
Ceramic
-55°C to +125°C
COMMENTS
I
PACKAGE DESCRIPTION - 40-Pin Dual-In-Line Ceramic Package
Symbolization Area for
Identification of Pin 1
.05TYP ~~
I I -I j-- .04 TYP
008
008 I
II
I
.=~
I
I
I .010
-.025I 0,0 ,t1 f
25
t'{-!
-1~0:: :::ALT::ACES
100~1900-------I.1.1
2000RE'
I.
~-----I-'
}o--------
PACKAGE DESCRIPTION - 40-Pin Dual-in-Line Plastic Package
+a~
I~.
I
,-""
'"-L
[:::::::::::::::::-J~:
21
40
i7-~raa5 50TYP1t:=-- -l f.~~~
. 075 REF
-L'
a2:I
1--l~OI8!.OO2
--1
~. 100:t: .010
~ ~.055±.007
~
~25!.005
540 NOM
~
fa
~.62S,!:= .025---.\1
I
NOM
+
~OIO_.OO2
463
INSTRUCTIONS FOR COMPLETION OF MASK PROGRAMMED PART FORM:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
464
List customer name.
List customer address.
List customer city, state, and zip code.
List customer phone number and extension.
List a contact within the customer's company that can be called for reply to engineering questions.
List the responsible Disbributor should the order be placed through a Distributor.
List the ROM/PSU/3870 part number for example 3851/12XXX, 34XXX, or MK 3870/
141XXX.
List the package type (plastic or ceramic) required by the customer for the production
order (NOTE - prototypes will be Dallas assembled in ceramic).
List the customer part number.
List any special branding requirements desired by the customer (NOTE - usually the
MOSTEK exclusive part will suffice for customer branding requirements).
List the customer specification number and indicate whether the customer intends to
send a specification to MOSTEK for file. Should you circle NO this denotes that
parts will be tested to the standard MOSTEK data sheet.
Should the customer request his specification to be on file with MOSTEK, please
indicate the date that the customer spec was sent to MOSTEK.
Circle the pattern media that the customer wishes to use to transmit code to MOSTEK.
Indicate the verification media requested by the customer from MOSTEK. (NOTE the listing is usually sufficient).
Check the port option requested by the customer (make reference to note # 1).
Indicate the date that the customer's pattern was sent to MOSTEK.
Indicate whether the customer requires prototypes (NOTE - standard quantity of
prototype Dallas assembled in ceramic is 10).
Indicate whether the customer requires pattern verification. Check YES or WAIVER.
Indicate whether the customer requires prototype verification. Indicate by checking
YES or WAIVER.
Make any comments concerning waivers if stated above.
The customer purchase order to MOSTEK direct or to his Distributor.
List the date of the customer order.
List the Distributor purchase order number to MOSTEK should the order be placed
through a Distributor.
Indicate the production quantity and price.
Indicate the delivery dates requested or committed to the customer; both prototypes
and production. (NOTE - standard commitment is six weeks to prototype after verification of listing and twelve weeks from prototype verification to production).
Date this form was completed and forwarded to MOSTEK.
Name of Representative compieting this form.
Customer Name _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Address __________________________________________________
City __________________________ State _ _ _ _ _ _ _ _ _ Zip _ _ _ _ _ _ _ ___
Phone (_ _ ) ___________________ Extension _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Contact __________________________________________________________
Distributor _____________________________________________________
ROM Generic Type _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Package Type _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Customer Part Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Brandi ng Requ irement _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Specification: _ _ _ _ _ _ _ _ _ _ _ __
DYes
o
No
Parts to be tested to standard Data Sheet
Date customer spec sent to MOSTE K _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
PATTERN MEDIA
VERIFICATION MEDIA
PORT OPTION (Note 1)
o
o
o
o
o
o
o
o
o
o
o
EMU-70
PROM
Paper Object Tape
Silent 700 Cassette
Card Deck
Tape of Card Deck
Listing
Other
Standard TTL
Open Drain
Driver Pullup
(Note 2) _________________________________________
Date Pattern Data Sent to MOSTEK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Does Customer Require Prototypes
0 Yes
o
No
Pattern Verification Required by Customer
DYes
Prototype Verification Required by Customer
0 Yes
o
o
Waived
Waived
CO MME NTS: (Waiver Explanation) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Customer Order Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Date of Customer Order _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Distributor Order Number to MOSTEK _ _ _ _ _ _ _ _ _ _ _ _ _ __
Order Quantity and Price _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Delivery Requested/Committed
Prototypes
Production _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Date Form Completed _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Name of Representative Completing Form _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
465
466
MOSTEl(.
Fa MICROPROCESSOR DEVICES
Program Storage Unit MK3851
FEATURES
Fa FAMILY
D 1024 x 8 ROM storage
I/O<=:>
D Two 8-bit I/O Ports
I/O<=) '--_ _-'
D Programmable timer
D External/timer interrupt circuitry
D Low power dissipation
< 275mW typical
GENERAL DESCRIPTION
The MK 3851 program storage unit (PSU) provides
1024 bytes of read only memory (ROM) for the F8
system. Additionally each PSU provides two 8-bit
I/O ports, a programmable timer and vectored timer
and external interrupts. The PSU contains three
16-bit address registers and a 16-bit incrementer/adder.
On command from the F8 CPU the MK 3851 accesses
its internal memory using one of these three registers and increments or adds displacement to the
register if required.
P
E
R
M
I
P
H
E
M
I/OW
E
R
A
I/O
L
<==> '--__-'
o
R
y
<,----->
S
The MK 3851 PSU is manufactured using N-channel
Power dissipation is
Isoplanar MOS technology.
very low, typically less than 275mW.
PIN NAME
DESCRIPTION
I/O AO·I/O A7
I/O Port A
B i-di recti onal
I/O BO·I/O B7
I/O Port B
Bi-directional
TYPE
DBO·DB7
Data Bus
Bi-directional, tri-state
ROMCO·ROMC4
Control Lines
Input
<1\ WRITE
Clock Lines
Input
EXTINT
External Interrupt
Input
PRTii\i
Priority In
Input
Pi'ITOOT
Priority Out
Output
PIN CONNECTIONS
I/OB7 _
I
40 _
I/O A7 _
2
39 _
DBS
VGG-
3
38 _
1/086
Vee _
4
37 _
i7OA6
EXTINT _
5
36
I5RiOD'i' ___
6
DB7
_11OA5
35 _
I/OB5
7
34 _
DB5
(>_8
33 _
___
32 _
DB4
j'j'Qgli
WRITE _
~
PRilliI _
9
10
~_II
MK 3B51
30 _
i7Ol\4
i7Ci"li3
31
_
iNTRE'Ci
Interrupt Request
Output
110 B3
Data Bus Drive
Output
USED - - 12
ROMC4 _
13
29 _
DBDR
28 _
DB3
vSS. VDD. VGG
Power Supply Lines
Input
ROMC3 _
14
27 _
082
ROMC2 _
15
26_~
NOT
ROMCI _
16
25 _IIOA2
ROMCO _
17
24 _ I I O A I
VSS _
18
23 _
110 81
110 AO _
19
22 _
DBI
i701iO _
20
21
DBO
_
467
FUNCTIONAL DIAGRAM
6BITPQRT
INTERRUPT ADDRESS
ADDRESS SELECT
(MASKED OPTION)
PORT SELECT
LOGIC
ROMe DeCODe
AND
CONTROL
ROMeo - ROMC4
LOGIC
TIMING
L __JI---16
.....--
WRITE
VSS
..---
VOO
+-----
VGG
Figure 1
FUNCTIONAL PIN DESCRIPTION
and WR ITE are clock inputs generated by the
MK 3850 CPU.
MK 3851 PSU low, and the MK 3851 PSU is not
requesting an interrupt.
ROMCO through ROMC4 are control inputs generated by the MK 3850 CPU.
I/O AO through I/O A7 and I/O BO through i7OB7
are two Input/Output bi-directional ports through
which the MK 3851 PSU communicates with logic
external to the microprocessor system.
OBO through OB7 are bi-directional data bus lines
which link the MK 3851 PSU with all other devices
in the F8 system.
OBDR is low when the MK 3851 PSU is outputting
data on the data bus (OBO-OB7). DBDR is an open
drain signal.
INT REQ. This signal is connected to the INT REQ
input on the 3850 CPU. INT REO is output low to
interrupt the MK 3850 CPU. This occurs only if
PRI IN is low, and MK 3851 PSU interrupt control
logic is requesting an interrupt.
DEVICE ORGANIZATION
EXT INT. A high to low transition on this signal is
recogniled by the iviK 385i as an interrupt request
from an external device.
PRI IN. This input must be low to allow theMK 3851
PSU to set INT REQ low in response to an interrupt.
PR lOUT. This signal is connected to ~ on the
next device in the interrupt p~ori~ daisy chain.
PR lOUT is output high unless P I I is entering the
468
This section describes the operation of the basic
functional elements of the MK 3851 PSU. These
elements are shown on the PSU functional block
diagram. (Fig.1)
ROM STORAGE
The MK 3851 PSU has 1024 bytes of read-only
memory.
This ROM array may contain object
program code and/or tables of non-varying data.
Every MK 3851 PSU is implemented using a custom
mask which specifies the state of every ROM bit,
as well as certain address mask options which are
external to the ROM array.
THE PROGRAM
COUNTER (DC)
COUNTER
(PO) AND DATA
The MK 3851 PSU addressing logic consists
primarily of two 16-bit registers: the program counter (PO) and the data counter (DC).
The program counter will at all times address the
memory word from which the next object program
code must be fetched. The data counter addresses
memory words containing individual data bytes or
bytes within data tables to be used as operands.
The mechanism whereby an address is decoded by
the MK 3851 PSU logic is identical, whether the
address originated in PO or in DC.
enable signal will be generated which causes PSU
logic to respond to a memory access request. If the
high order 6-bits of the address do not match the
page select, no enabling signal is generated and the
PSU will not respond to memory access requests.
The 6-bit page select register may be looked upon
as identifying the memory addressing space of the
individual MK 3851 PSU device. Each of the 64
page select options allowed by the 6-bit page select
register identifies a single address space consisting
of 1024 contiguous memory addresses. Following
are two examples:
Page Select Mask:
o0 0 0 0 0
Recall that PO always addresses the memory location out of which the next object program instruction byte will be read. If the instruction requires
data (an operand) other than an immediate operand
to be accessed, DC must address memory. PO cannot be used to address a non-immediate operand
since PO is saving the address of the next instruction
code.
PSU Address Space:
o 0 0 0 0 0 0 0 0 0 0 0 0 0 DOH '0000'
0 0 0 0 0 1 1 1 1 1 1 1 1 11th rough.
H'03FF'
Page Select Mask:
001011
THE STACK REGISTER
PSU Address Space:
0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 H'2COO'
.10 0 1 0 1 11!1 1 1 1 1 1 1 1 1 11 through
H'2FFF'
The MK 3851 PSU addressing logic contains a third
16-bit register, called the stack register. The stack
register is labeled P on Figure 1. The stack register
is a buffer for the program counter PO. The contents of the stack register are never used directly
to address memory.
The following instructions access P:
LR K,P
MOVE THE CONTENTS OF P TO THE
CPU SCRATCHPAD K REGISTERS
LR P,K
MOVE THE CONTENTS OF THE CPU
K SCRATCHPAD REGISTERS TO P
PK
SAVE THE CONTENTS OF PO IN P
THEN MOVE THE CONTENTS OF CPU
SCRATCHPAD REGISTERS 12 AND 13
TO PO
PI H'aaaa' MOVE THE CONTENTS OF PO TO P
THEN LOAD THE HEXADECIMAL
VALUE INTO PO
POP
MOVE THE CONTENTS OF P TO PO
o
o
I
I
Six high order
address bits
Ten low order address bits
INCREMENTER ADDER LOGIC
There are only two arithmetic operations that
memory devices need to perform on the contents
of memory address registers:
1. I ncrement by 1 the 16-bit value stored in an
address register.
2. Add an 8-bit value, treated as a signed binary
number (subject to twos complement arithmetic)
to the 16-bit value stored in an address register.
The incrementer adder logic performs these two
functions in the MK 3851 PSU.
INTERRUPT LOGIC
In addition, when an interrupt is acknowledged, the
contents of PO are saved in P.
This logic responds to an interrupt request signal
which may originate internally from timer logic,
or be input by an external device. Based on priority
considerations, the interrupt request is passed on
to the MK 3851 CPU.
PAGE SELECT LOGIC
TIMER LOGIC
All memory addresses are 16-bits wide, whether the
memory address originates in the program counter or
the data counter. Addressing logic within the MK3851
PSU separates the 16-bit address into two portions.
The low-order 10 bits address one of the PSU's
1024 bytes of ROM storage. The high order 6-bits
constitute a page select.
Every MK 3851 PSU has a polynomial shift register
which may be used in conjunction with interrupt
logic to generate real-time intervals.
Every MK 3851 PSU has a 6-bit page select register,
which is a mask option that must be specified when
the PSU ROM chip is ordered. If the high order six
bits of the address match the page select mask, an
Upon counting down to zero, the timer uses interrupt
logic to signal that it has timed out.
The timer is programmable and is handled as though
it were an I/O port. Using an OUT or OUTS instruction, a value may be loaded into the timer in order
to determine the real-time period at the end of which
a time-out interrupt will be generated.
469
THE DATA BUS
The 8-bit data bus is the main path for transfer of
information between the MK 3850 CPU and other
devices in the F8 microprocessor system. It is identified in Figure 1 by data lines DBO-DB7.
I/O PORTS
Every MK 3851 PSU has four, 8-bit I/O ports.
Associated with the I/O ports is an I/O port address
select register. This is a 6-bit register, the contents of
which is a PSU mask option. that must be specified at the time the MK 3851 PSU is ordered.
Two of the four I/O ports, identified as I/O ports A
and B in Figure 1, are used to transfer data to or
from external devices. A third I/O port is assigned
to the programmable timer while the fourth port
is the Interrupt Control Port.
The four I/O ports of any MK 3851 PSU are addressed
by an 8-bit I/O port address. The high order 6 bits
are specified by the I/O port address select code with
the remaining 2 bits identifying the particular I/O
port as following:
XXXXXXOO
XXXXXXOl
XXXXXX10
XXXXXXll
I/O Port A
I/O Port B
Interrupt control
Programmable Timer
XXX XXX represents a six bit PSU mask option. For
example, if the six are 000010, the four I/O port
addresses are H'08', H'09', H'OA' and H'OB'.
When a logic "1" is output to I/O port A or B, it
places a 0 volt level on the output pin. This same
negative true logic also applies to input. The I/O
ports, timer, and interrupt control ports are not
initialized during the power on reset.
MASK OPTIONS
The following mask options must be specified for
every M K 3851 PSU:
1. The 1024 bytes of ROM storage. This will reflect
programs and permanent data tables stored in the
PSU memory.
2. The 6-bit page select. This defines the PSU address
space
3. The 6-bit I/O port address select. This defines the
four PSU I/O port addresses.
4. The 16-bit interrupt address vector, excluding
bit 7.
.
5. The I/O port output option. The choices are
the standard Pull-up (Option A), the Open-Drain
(Option B) and the Driver Pull-up (Option C)
The clock drives sequencing logic .to precharge the
ROM matrix. The clock also drives the programmable timer.
INSTRUCTION EXECUTION
The MK 3851 PSU responds to signals which are
output by the MK 3850 CPU in the course of executing Instruction cycles.
Table 1 summarizes the response of the MK 3851
PSU to the ROMC states.
MEMORY ADDRESSING
Those ROMC states which specify a memory access
call for only one memory device to respond to the
memory access operation. However, every memory
device responds to ROMC states that call for modification of proQram counter or data counter register
contents. Consider two examples:
1. ROMC state 5 specifies that the data counter
(DC) register contents must be incremented.
Every memory device will simultaneously receive this ROMC state, and will simultaneously
increment the contents of its DC register.
2. ROMC state 0 is the standard instruction fetch.
Only the memory device whose address space
includes the current contents of the program
counter (PO) registers will respond to this ROMC
state by accessing memory and placing the contents of the addressed memory word on the 8-bit
data bus.
However, every memory device will
increment the contents of its PO register, whether
or not the PO register contents are within the
memory space of the device.
When all memory devices connected to the 8-bit
data bus of a MK 3850 CPU are also connected to
the ROMC control lines ofthe same CPU, the memory
devices simultaneously receive the same ROMC state
signals from the CPU and respond to ROMC states
by identically modifying the contents of memory
address registers. Therefore the PO repister on all
memory devices contain identical Information.
The same holds true for DC and P registers.
Only the memory device whose address space includes the specified memory address, will respond to
any memory access request. To avoid addressing
conflicts, it is necessary to insure that the following
three conditions exist:
OPERATIONAL DESCRIPTION
1. Memory devices must receive the ROMC state
sig!lals from one CPU.
2. Page select masks must not be duplicated. (More
than one memory device cannot have the same
memory space).
3. The memory address contained in the specified
register (PO or DC) must be within the memory
space of a memory device.
CLOCK TIMING
DATA OUTPUT BY THE PSU
All timing within the MK 3851 PSU is controlled by
and WRITE, which are input from the MK 3850
CPU.
Figure 10 shows the timing when the MK 3851 PSU
outputs data on the data bus. This timing applies
whenever a MK 3B51 PSU is the data source. The
MK 3851 PSU always places data on the data bus in
time for the set-up required by an MK 3850 CPU
destination.
The WRITE clock refreshes and updates MK 3851
PSU address registers, which are dynamic.
470
ROMC STATES
ROMC
(Hexadecimal)
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
Definitions
DB PO
DC P
pp
p
OPERATION PERFORMED
COMMENT
DB.- ((PO)) ; PO+PO +1
OP CODE, FETCH
DB'- ((PO)) ; PO.-PO +DB
BRANCH OFFSET FETCH
DB "-((DC)); DC+DC+1
DB..-((PO)) ;P()+PO+1
IMMEDIATE OPERAND FETCH
PO ..-p
((DC))..-DB; DC.-DC+1
MK3851:DC-DC+10NLY
DB+DCU
DB"-PU
P..-PO; DB..-H'OO'; POL, POH"- DB EXTERNAL RESET
DB '-DCL
DC'-DC+DB
DB'-PL
DB.-((PO)) ; DCL+DB
P+PO+1
DB.-((PO)) ; DCL+DB
P+PO; DB.-IAL; POL--DB
LOWER BYTE OF ADDRESS VECTOR
FREEZE INTERRUPT STATUS
PREVENT ADDRESS VECTOR CONFLICTS
DB.-((PO)) ; DCU-DB
POL--DB ; P--PO
DB..-IAU; POU-DB
UPPER BYTE OF ADDRESS VECTOR
POlJ..-DB
PU..-DB
DCU..-DB
POL..-DB
PL"-DB
DCL"-DB
((pp))..-DB or ((p))"-DB
DB..-( pp)) or DB..-((p))
NO OPERATION
DC ~DC1
MK 3851: NO OPERATION
DB..-POL
DB+POU
Data Bus
Program Counter
Data Counter
Stack Register
Two hex digits (long I/O port address)
One hex digit (short I/O port address)
IA
L
U
()
..-
~
Interrupt address vector
Lower byte suffix
Upper byte suffix
Contents of
transfer to
exchange
Table 1
Observe that DBDR is low while data output by the
MK 3851 PSU is stable on the data bus. Thus DBDR
low indicates that the data bus currently contains
data flowing from a MK 3851 PSU. For systems with
more than one MK 3851 PSU the DBDR outputs
may be wire-ORed and the result.JTI£Y... be used as a
bus data flow direction indicator. DBDR may remain
low until td8 into the instruction cycle following the
one in which DBDR was set low.
added to a 16 bit number within the PSU's Incrementer Adder. This worst case corresponds to data
coming from the accumulator in the CPU for an ADC
instruction or from a memory device for a B R instruction. For this worst case, arriving data must
allow sufficient time for 16-bit Adder logic. td4 in
Figure 10 identifies this worst case timing.
DATA INPUT TO THE PSU
The two PSU I/O ports with addresses xxxxxxOO
and xxxxxx01 (xxxxxx is the 6-bit I/O port address
select) may be used to transmit data between the
PSU and external devices. I N and I NS instructions
The worst case timing forthe MK 3851 PSU receiving
data from the data bus is when the data must be
INPUT/OUTPUT INTERFACING
471
STANDARD PULL-UP CONFIGURATION
r ----- ---- - - ---
----- - -- - - - - - - - -,
I
I
Voo
J
J
voo
1/0 PORT
J
TTL INPUT
J
J
I
I
I
L
I
--<)
J
I
J
:L
_____H~~~~~I~~R~~I:'~
TTL OUTPUT
_____________ _
Figure 2
OPEN DRAIN CONFIGURATION
---------------~
Voo
TTL INPUT
110 PORT
y
I
I
I
x--/
J
I
I
_____H!~T5~E~~ _~~U~TJ
I
I
:L
TTL OUTPUT
______________ _
Figure 3
DRIVER PULL-UP CONFIGURATION
-------
------------,
~,.(a-)--+---~~R~------~
x
•
I~)
---------------~---j
Figure 4
472
Voo
voo
1/0 PORT
LED
~-
cause data at the I/O ports to be transmitted to the
CPU. OUT and OUTS instructions cause data in the
CPU's accumulator to be loaded into an I/O port
latch.
Data bus timing associated with the execution of
I/O instructions does not differ from data bus timing
associated with any other data transfer to or from
the PSU. However, timin!j at the I/O port depends
on which port option is bemg used. Figures 2,3 and
4 illustrate the three port options. Figure 11 illustrates timing for the three cases. Figure 2 illustrates
the standard pull-up configuration.
When the I/O port is configured as shown in Figure 3
the drain connection of FET (a) is "open", (not
connected to VOO through a pull-up transistor).
This option is most useful in aJ)plications where
several signals (possibly several I/O port lines) are
to be wire-ORed together. A common external
pull-up, R L is used to establish the 2 high output
levels. Another advantage of this option is that
the output (point Y) may be tied through a pull-up
resistor to a voltage higher than VOO (up to VGG)
for, interfacing to external circuits requiring a higher
level than VOO would provide. The process of
inputting and outputting with this configuration
can be described as follows:
If a high level is present at point X( (this would be
coming from the port latch), FET a) will conduct
and pull point Y to a low level by current flow
through R L- This low level at Y will cause transistor (b) to turn on and present a low level to the
input TTL circuit. If a low level is present at X,
FET (a) will turn off and point Y will be pulled
toward VOO by RL. This causes transistor (b) to
turn off and present a high level to the internal
TTL circuits.
When data is input, a high level at the base of transistor (c) causes it to conduct and pull point Y low.
This transfers a high level to the internal I/O port
logic through the inverting hysteresis circuit. If a
low level is present at the base of (c), conduction
stops and point Y is pulled toward VOO by R L.
This is then transferred as a low level to the internal
I/O port logic through the hysteresis circuit.
Figure 4 shows the I/O port driver pull-up option
shown driving a LED indicator. This application is
typical of a front-panel address or data display,
where a row of LED indicators shows the logic state
of an I/O port. In this case, a high level at X turns
FET (b) on and (a) off, providing a path for current
through resistor R from the base of transistor (c).
This stops (c) from conducting and the LED does
not light. However, if a low level is present at X,
(b) turns off and (a) turns on! providing a path for
current from VDO through (a/ to R. This current
through R turns on (c), causing the LED to conduct
and be lit.
The three options for I/O port output configurations
described above are provided to aid the designer in
optimizing (minimizing) the system hardware for
hiS particular application. The option is specified
as a mask option by the designer.
----~
THE PROGRAMMABLE TIMER
The MK 3851 PSU has an 8-bit shift register, addressable as I/O port xxxxxx 11, which may be used as a
programmable timer. (xxxxxx is the 6-bit I/O port
address select, a PSU mask option.) Figure 5 illustrates the shift register logic and the exclusive-OR
feedback path.
CONVERSION OF TIMER COUNTS
INTO TIMER CONTENTS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
3
4
0
7F BF 5F 2F 97
OE 87 43 A1 DO
OF 07 03 01 00
EC F6 7B BO 5E
00 06 83 41 AO
2A 15 8A C5 E2
CF E7 73 B9 5C
65 32 99 CC 66
05 02 81 40 20
30 98 4C 26 13
C4 62 B1 58 AC
5A AD 06 EB 75
20 96 4B A5 02
67 33 19 8C C6
C3 E1 70 38 9C
F2 79 BC DE EF
8B 45 A2 51 28
90 48 24 12 09
78 3C 9E 4F A7
A6 53 29 94 4A
A9 04 EA F5 FA
1B 80 46 23 91
B6 DB 60 36 9B
7E 3F 1F 8F 47
ED 76 3B
8E
EE F7 FB FO FE
Each timer count = 15.5
to
5
7
6
CB E5 72
E8 F4 7A
80 CO 60
AF 07 6B
50 A8 54
F1 F8 7C
AE 57 2B
B3 59 2C
10 08 84
89 44 22
56 AB 05
BA DO 6E
E9 74 3A
63 31 18
4E 27 93
77 BB 50
14 OA 85
04 82 C1
03 69 34
25 92 49
70 BE OF
C8 64 B2
CD E6 F3
A3 01 68
C7 E3 71
F F halts timer
JJS at 2MHz
8
39
3D
BO
35
AA
3E
95
16
C2
11
6A
B7
90
OC
C9
2E
42
EO
9A
A4
6F
09
F9
B4
B8
9
1C
1E
08
1A
55
9F
CA
OB
61
88
B5
5B
CE
86
E4
17
21
FO
40
52
37
6C
FC
OA
DC
Table 2
Based on the logic illustrated in Figure 5 binary
values in the range 0 through 254 when loaded into
the timer, are converted into "timer counts", as shown
in table 2. Table 2 contains the actual (HEX) value
loaded into the timer, and the column/row is the
corresponding decimal number of time intervals the
timer will take to time out. Data cannot be read out
of the programmable timer I/O port.
Either the OUT or OUTS instruction is used to
"timer counts" into the programmable timer.
contents of the programmable timer can not be
using an IN or INS instruction. The timer will
out after a time interval given by the product:
(period of clock <1» X (timer counts) X 31
load
The
read
time
For example, a value of H 'C8' loaded into the programmable timer becomes 215 timer counts. The
timer will therefore time out in 3.33 milliseconds,
if the period of clock signal is 500 nanoseconds.
A value of H'FF' loaded into the programmable timer
will stop the timer. This is because the timer shift
473
TIMER LOGIC DIAGRAM
lOAD
TIMER
CLEARED WHENEVER
TIMER IS lOADED
r-----_--+
JAM 8 BITS
PARAllEL
WHEN lOAOEO
u
.;- 31 PRESCAlER
TIMER ClK
r--+---jD
Q
TO
D
Q
TI
D
T3
D
DECODE TIMER STATE
'FE' AS TIMEOUT
\
--I
Q'I---<~T4'----jD
Q
T5
o
C
C
lSB
MSB
O
T5
~T~6
_ _ _ _ _ _ _ _ _ _ _ _ _~
Figure 5
register feedback gates will always present a logic 1
to the D input of the LSB flip-flop (fig. 5). Therefore
the timer will retain a value to H'FF' and a H'FE'
will never be decoded to cause a time out.
Figure 6 illustrates a possible sequence for a timer
which is initially loaded with H'C8' then allowed
to run continuously.
INTERRUPT LOGIC ORGANIZATION
The timer runs continuously unless it has been
stopped by loading H'FF' into it. Upon timing out,
the timer transmits an - interrupt request to the
interrupt logic. If proper interrupt logic conditions
exist, the timer interrupt request is passed on to the
CPU via INT REO.
After the programmable timer has timed out it will
again time out after 255 time counts. Therefore if
the programmable timer is simply left running, it
will time out every 7905 clock periods, or every
3.9525 milliseconds for a 500 nanosecond clock.
Whenever the timer and timer interrupt are being
set to time a new interval, the timer should be loaded
before enabling the timer interrupt. The act of
loading the timer clears any pending timer interrupts.
When the timer interrupt is enabled, any pending
timer interrupt will be acknowledged and forwarded
to the CPU. Since the timer runs continuously
(unless stopped under program control) enabling the
timer before loading a time count can cause a spurious interrupt. Time outs of the timer are latched in
the interrupt logic of the PSU, even while timer interrupts are disabled. When the timer is enabied, an
immediate interrupt acknowledge will occur if the
continuous running timer timed out while timer
interrupts were disabled.
If the timer is loaded just prior to enabling timer
interrupts a spurious interrupt request will not exist
when the timer interrupt is enabled.
474
The I nterrupt Control Port has the I/O port address
xxxxxx10, where xxxxxx is the 6-bit I/O port
address select.
Data is loaded into this register
(I/O port) using an OUT or OUTS instruction. Data
cannot be read from this port. The contents of the
Interrupt Control Port are interpreted as follows:
CONTENTS OF
INTERRUPT
CONTROL PORT
FUNCTION
B'xxxxxxOO'
B'xxxxxx01 '
B'xxxxxx 10'
B'xxxxxx 11'
Disable all interrupts
Enable external interrupt,
disable timer interrupt
Disable all interrupts
Disable external interrupt,
enable timer interrupt
In the above I/O port contents definitions x represents "don't care" bits.
Depending on the contents of the Interrupt Control
Port, a MK 3851 PSU's interrupt control logic can be
accepting timer ~nterrupts, or external interrupts,
or neither, but never both.
Figure 7 is a conceptual logic diagram of the PSU's
interrupt logic. Between the EXT I NT input or the
time-out input and the output INT REO, there are
4 flip-flops. EXT INT and the time-out interrupt
input each have 2 synchronizing flip-flops to detect
the active edge.
TIME OUT AND INTERRUPT REQUEST
~3.3
m s - -...I......---3.953 m s - - - - - I......_--3.953
-
A
II
I--
---
D
13
I--
c
c
B
ms---_~~I
D
D
Figure 6
Each edge detect circuit is followed by its own
INTERRUPT flip-flop which latches the true
condition.
The outputs of the TIMER INTERRUPT flip-flop
and the EXTERNAL INTERRUPT flip-flop are
ORed to set the SERVICE REQUEST flip-flop,
providing that an interrupt from some other PSU
is not being acknowledged by the CPU.
INT REQ is the NAND of PRI IN and SERVICE
REQUEST.
INT REQ is an open drain signal. The INT REO
signal of several PSU's may be tied together so that
anyone can force the line to OV if it is requesting
interrupt service. A ~II-u~ to VDD is provided by
the MK 3850 CPU to I T R Q input pin.
PRI IN is part of the interrupt priority chain. The
chain begins ~ap to VSS. Each device in the
chain has a PRI IN input and PRI OUT outPu~
PRI OOT:of the PSU will be true (OV) only if PRI I
is true (OV) and SERVICE REQUEST is false. This
means that when PRI IN is true (OVl, PRI OUT and
INT REQ are always at opposite levels. PRI OUr
is connected to PRI IN on the next device in the
interrupt priority daisy chain, if there is one. The
function of the priority daisy chain is to insure that
just one device at a time be requesting interrupt
service.
The SERVICE REQUEST flip-flop cannot be set
if another interrupt request is in the process of being
acknowledged anywhere in the system. If an interrupt
request has been latched into the TIMER INTERRUPT
flip-flop, or the EXTERNAL INTERRUPT flip-flop,
the PSU logic waits until after the process .of ack-
nowledging the other interrupt has been completed
before setting SERVICE REQUEST. This precaution is necessary to insure that the priority chain is
not altered during acknowledgement. Chaos would
result if half of the interrupt vector came from one
device and the second half from some other device.
The SERVICE REQUEST flip-flop is cleared after
an interrupt from the PSU has been acknowledged.
It is also cleared whenever the PSU's interrupt control
register is accessed by an output instruction.
The conditions for setting the TIMER INTERRUPT
flip-flop and the EXTERNAL INTERRUPT flip-flop
differ slightly. External interrupts must be enabled
before the EXTERNAL INTERRUPT flip-flop can
be set by a negative going transition of EXT INT.
However, TIMER INTERRUPT will be set by a
timer TIME OUT independent of Interrupt Control
Port bit 1. This means that the PSU can detect a
time out interrupt that occurred while the external
interrupt was enabled in the PSU.
The TIMER INTERRUPT flip-flop is cleared whenever the PSU's timer is loaded or when its timer
interrupt has been acknowledged. The EXTERNAL
INTERRUPT flip-flop is cleared whenever the PSU's
interrupt control register is accessed by an output
instruction, or when its external interrupt has been
acknowledged.
INTERRUPT ACKNOWLEDGE SEQUENCE
Upon receiving an interrupt request, whether from
an external sou rce via EXT I NT or from the internal
timer, the PSU and CPU go through an interrupt
475
INTERRUPT LOGIC
INTR A C K * * : : : . - - - - - - - - - - - - 1 ,
*(lCP BtT OJ-{tCP BIT Il
TIME OUT
.--------c~
SYNC
fF
CUt, "
EXT tNT
INTR
FF
CLKY
WRITE ........~---+---_t_-__t-------------------l
(ICP'SIT 0)· {lCP BIT
Ii
• ICP~lnterrupt Control Port
'" "'1 During Event G in Fig 8
Figure 7
sequence which results in the execution of an interrupt service routine located at the memory address
pointed to by the Interrupt Address Vector. Figures
8 and 9 illustrate the interrupt sequence for the two
cases. Events occuring in these sequences are .Iabeled
with the letters A through H. Events are described
as follows.
EVENT A
The initial interrupt request arrives. The falling edge
of EXT I NT pin identifies an external interrupt. The
rising edge of interval timer output indicates a timeout.
The system is not already into Event F due to servicing some other interrupt.
EVENT E
The CPU now begins its response to the INT REO,
line by outputting the unique ROMC state H'10'
inhibiting modification of interrupt priority logic.
This will only occur when the following conditions
are satisfied:
The CPU is executing the last cycle of an instruction
(beginning an instruction fetch).
The ICB is enabled (ICB = 0).
EVENT B
The synchronizing flip-flop in the PSU control logic
changes state.
EVENTC
The timer interrupt, or external interrupt flip-flop
goes true, indicating the local interrupt logic's acknowledgement of the interrupt. The timer interrupt
flip-flop will always respond and save the time-out
occurrence, whereas the external interrupt flip-flop
will only be set at this time if the external interrupt
mode is enabled within the local control logic.
The current instruction fetch is not protected (not
a privileged instruction).
EVENT F
The CPU generates the interrupt acknowledge sequence of ROMC states as follows:
ROMC STATE
10
IC
EVENT D
OF
The INT REO line is pulled low by the PSU, passing
the request for servicing on to the CPU. The conditions that must be present for this to occur are:
13
The PRI IN pin must be low.
00
The proper enable state must exist in the local
control logic for the type of interrupt (timer or
external).
476
Inhibit modification of interrupt
priority logic.
No function
Put lower byte of interrupt
addi6ss
vactoi on
data
bus
Put upper byte of interrupt
address vector on data bus
Fetch instruction from memory
(first instruction of interrupt
service routine)
EVENT G
At this point the CPU begins fetching the first instruction of the interrupt service routine. In the
~SU interrupt logic, the SERVICE REQUEST flipflop and the appropriate INTERRUPT REQUEST
flip-flop are cleared.
EVENT H
The CPU begins executing the first instruction of
the interrupt service routine.
INTERRUPT ADDRESS VECTOR
program execution can branch to the routine that
handles this particular interrupt.
Fifteen bits of
the interrupt vector are specified as a mask option.
Bit 7 cannot be masked. It is set by the interrupt
control logic to 0 if the timer interrupt is enabled
or to a 1 if external interrupt is enabled. The interrupt vector is ofthe form:
WWWW, XXXX, OYYY, ZZZZ for timer interrupt
and WWWW, XXXX, 1YYY, ZZZZ for external
interrupt where W,X Y and Z are the mask specified bits.
INTERRUPT SIGNALS TIMING
During the interrupt acknowledge, the interrupting
PSU provides a 16-bit interrupt address vector. The
CPU causes this vector to be loaded into PO, so that
Timing for signals associated with the MK 3B51
interrupt logic is shown in Figure 12.
TIMER INTERRUPT SEQUENCE
t
WRITE
B
c
D
i I
I
I
F
A
~~ ~ ~
I
I
I
I
I
TIME OUT
TIMER REQ
TIMER INTR F. F.
!NT REO (TO CPU)
ROMC STATE
(FROM CPU)
@
IL-
I
- - - --
__
--
--
I
I
ss
I
~~
I
10
IC
OF
13
00
Figure 8
477
EXTERNAL INTERRUPT SEQUENCE
A
B
I
I
C
o
I
I
i (I
F
A~---:G:-I-----:-H:':"'I\
~JJ~
WRITE
I
I
I
I
I
,- -,I
- --
iN'f REO (TO CPU)
L.'F-'--:-_---:--._--'-_-:'1
ROMC STATE
IC
10
OF
00
13
(FROM CPU)
Figure 9
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Above which useful life may be impaired)
VGG ...................................................... , +15V to -O.3V
VDD ............................•................. , ......•.. +7V to -O.3V
I/O Port Open Drain Option ..................................... +15V to -O.3V
External Interrupt Input ...........................•.......... -lmA to +225 pA
All other inputs & outputs ............•.. " ..•. ~ .................. + 7V to -O.3V
Storage Temperature .......................................... -50C to +150°C
Operating Temperature ......•.....................................ot to +70'C
Note: All voltages with respect to
vss.
DC CHARACTERISTICS
VSS = OV, VDD = +5V ±5%; VGG = +12V±5%, TA = O°C to + 70°C
SUPPLY CURRENTS
SYMBOL
PARAMETER
iDD
IGG
478
MIN
TYP
MAX
UNITS
VDD Current
30
70
rnA
VGG Current
10
18
rnA
TEST
CONDITIONS
= 2MHz, Outputs Unloaded
f = 2MHz, Outputs Unbaded
f
DC SIGNAL CHARACTERISTICS
VDD = +5V ± 5%, VGG = + 12V±5%, VSS = OV TA = 0-70°C
SIGNAL
SYMBOL
PARAMETER
MIN
MAX
OATA BUS (OBO-OB7)
VIH
VIL
VOH
VOL
IIH
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
3.5
VOO
0.8
CLOCK LINES (tP,WRITE) VIH
VIL
IL
Input High Voltage
Input Low Voltage
Leakage Current
3.5
PRIORITY IN AND
VIH
CONTROL LINES
(PRI IN, ROMCO-ROMC4) VIL
IL
Input High Voltage
Input Low Voltage
Leakage Current
3.5
PRIORITY OUT
(PRIOUT)
VOH
VOL
Output High Voltage
Output Low Voltage
3.9
INTERRUPT REQUEST
(lNT REQ)
VOH
VOL
IL
Output High Voltage
Output Low Voltage
Leakage Current
VSS
VOH
VOL
IL
Output High Voltage
Output Low Voltage
Leakage Current
VSS
Input High Voltage
IlL
Input Low Voltage
Input Clamp Voltage
Input High Current
Input Low Current
VOH
Output High Voltage
VOH
VOL
VIH
VIL
IL
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Low Current
VOH
VOL
VIH
VIL
IlL
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
VOH
VOL
Output High Voltage
Output Low Voltage
10L
DATA BUS DRIVE
(DBDR)
EXTERNAL INTERRUPT VIH
(EXT INT)
VIL
VIC
IIH
I/O PORT OPTION A
(STANDARD PULL-UP)
I/O PORT OPTION B
(OPEN DRAIN)
I/O PORT OPTION
(ORIVER PULL-UP)
UNITS
TEST CONOITIONS
Volts
Volts
Volts
Volts
10H = -100 p.A
10L = 1.6mA
p.A
p.A
VIN = VDD, tri-state mode
VIN = VSS, tri-state mode
VDD
0.8
1
Volts
Volts
p.A
VIN =VOD
VDD
0.8
1
Volts
Volts
p.A
VIN = VDD
VDD
0.4
Volts
Volts
10H = -100p.A
10L = 100p.A
Volts
Volts
p.A
Open Orain Output [ 1 ]
0.4
1
0.4
1
Volts
p.A
3.5
15
Volts
-VSS
Volts
Volts
p.A
-250
1.2
15
10
-750
3.9
VSS
3.9
VSS
VSS
VSS
VSS
VDD
0.4
1
-1
10L = 1mA
VIN =VDD
Open Orain Output
2.9
VSS
2.9
VSS
VSS
2.9
VSS
Leakage Current
3.9
VSS
10L = 1.6mA
VIN = VDD
IIH = 185 p.A
p.A
VIN = VOD
VIN =VSS
VDD
Volts
10H = -30 p.A
VOD
0.4
Volts
Volts
Volts
10H = -100 p.A
10L = 1.6mA
Internal Pull-up to VDD [ 3 ]
Volts
mA
VIN=0.4V[4]
VDD
0.8
-1.6
0.4
VOO
0.8
2
VDD
0.4
Volts
Volts
Volts
Open Orain Output
10L = 1.6m.A
[3]
p.A
VIN =VDD
Volts
Volts
10H = -850 pA
10L = 1.6mA
Notes:
1.
Pull-up resistor to V DD on CPU.
2.
Positive current is defined as conventional current flowing into
the pin referenced.
3.
Hysteresis input circuit typically provides additional O.3V noise
immunity while internal/external pull-up provides TTL compatibility.
4.
Measured while I/O port is outputting a high level.
479
AC CHARACTERISTICS
VSS = QV, VOO = +5V ± 5%, VGG
= +12V± 5%, TA = QOC to + 7CfC
Symbols in this table are used by all timing diagrams.
Typ
Max.
Units
Test Conditions/
Comments
Symbol
Parameters
Min
pcI>
Pulse Width
180
P to WR ITE + Delay
0
250
td2
cI>to WRITE - Delay
0
225
ns
td4
WRITE to DB Input Delay
2PcI>+1.0
/.IS
PW2
WR ITE Pulse Width
PcI>
ns
PWs
WRITE Period; Short
4P cI>
6P cI>
500
ns
P cI>-100
tr.tf = 50 ns typo
PWL
WRITE Period; Long
td3
WRITE to ROMC Delay
td6
WRITE to DB Output Delay
2PcI>+100-td 2
2PcI>+200
2PcI>+800-td2
ns
CL = 100pF
td7
WRITE to DBDR -Delay
2PcI>+100-td2
2PcI>+200
2PcI>+800-td2
ns
CL = 100pF
td8
WRITE to DBDR + Delay
ns
Open Drain
tr,
WRITE to INT REO - Delay
430
ns
CL=100pF [1]
tr2
WRITE to INT REO + Delay
430
ns
CL = 100pF [3]
tpr,
PRI IN to i'f\i'i'l':iEQ - Delay
240
ns
CL = 100pF [2]
tp r2
PRI IN to ~ + Delay
430
ns
CL = 100pF
tpd l
PRI IN to PRI OUT -Delay
300
ns
CL = 50pF
tpd2
PRI IN to PRI OUT + Delay
365
ns
CL = 50pF
tpd3
WRITE to
PRiOOT + Delay
700
ns
CL = 50pF
tpd4
WRITE to PRI OUT - Delay
640
ns
CL = 50pF
tsp
WRITE to Output Stable
1.7
/-Is
CL = 50pF.
Standard Pull·up
tod
WRITE to Output Stable
1.7
/-Is
CL = 50pF
RL = 12.5K
Open Drain
tdp
WRITE to Output Stable
400
ns
CL = 50pF. Driver
Pull-up
tsu
I/O Setup Time
1.3
/-Is
th
I/O Hold Time
0
/-Is
tex
EXT INT Setup Time
400
ns
200
200
Table 4
Notes:
Assume Priority In was enabled (PAl IN~ 0) in previous F8 cycle before interrupt is detected in the PSU.
PSU has interrupt pending before priority in is enabled.
Assume pin tied to ~ input of the 3850 CPU.
The parameters which are shaded in the table above represent those which are most frequently of importance when interfacing to an
F8 system. Unshaded parameters are typically those that are relevant only between F8 chips and not normally of concern to the user.
5. Input and output capacitance is 3 to 5pF typical on all pins except VDD. VGG. and VSS.
1.
2.
3.
4.
480
n.
PSU DATA BUS TIMING
WRITE
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J _ _ _ _ _ _ _ _ _
~
____
SHORT CYCLE
,------,
,I _ _ _ _ _ _ \ \ _ _ _ __
~
~
LONG CYCLE
Id3==,~_________________________________________
J
ROMC
STABLE
I~
IdS
MTABUS------------------~I- - - - - - - - - - - - - - - - - - - - - - - OUTPUT
X
STABLE
i
~".=7---14
DBDR
(START OF DATA OUT)
DBDR
(END OF DATA OUT IN
SUBSEQUENT
CYCLE)
Id 7
1~.~----------ld4--------------~1~~-------------------------
X
DATA BUS
INPUT
STABLE
Figure 10
TIMING AT PSU I/O PORTS
WRITE
INPUT (I)
OUTPUT(2)
(STANDARD
PULLUP)
OUTPUT(2)
(OPEN DRAIN)
OUTPUT(2)
(DRIVER
PULLUP)
/
~J
DATA
DATA MAY CHANGE
: tS P=X29V
i 'Od =X29V
~ldP--y
tlh
Isu=f
2.9V
STABLE
DATA MAY CHANGE
STABLE
STABLE
STABLE
1. The set-up and hold times specified are with respect to the end of the second long cycle during execution of the three
cycle IN or INS instruction.
2. All delay times are specified with respect to the end of the second long-cycle during execution of the three cycle OUT
or OUTS instruction.
Figure 11
481
INTERRUPT LOGIC SIGNALS TIMING
WRITE
_______I
}~, 1~---S1:-A8-L-E--__I_____ ~~~~~~...t.LONI_r_G_-~C- _Y-:_L~ - _-" \_-'\:_-_-_-_~_
r:--1
__
ROMe
INTREO
=----1
~
~lr =1"'------_ _ _ _~_t_r2
rL =!
I
~lPd 4 = 1
t Pd 3
----PRI IN
INT REO
PRIOUT
EXT INT
NOTE: Timing measurements are made at valid logic level of the signals referenced unless otherwise noted.
Figure 12
Column
ORDER INFORMATION
1·20
26-30
36-36
User
SL
ROM
40-42
10
PACKAGE SPECI FICATION
MK 3851N/12XXX
Plastic
User
SL
MK 3851P/12XXX
Ceramic
ROM
The 12XXX number is assigned by MOSTEK when an
MK 3851 is ordered. All mask options must also be
specified as described in the next section.
OPTION SPECIFICATION
CARD FORMAT USED TO DEFINE MK 3851
PSU MASK OPTIONS
Mask options are specified using a card file which
may inClude the following types of card:
Option card,
Comment cards,
'X, cards itext format commands). and
'C' cards (ROM truth table data).
10
Port
Timer
45
50-53
58-60
Port
Timer
HEX
63-65
HEX
DEC
DEC
is the customer name
is a 5-digit SL number for the device
assigned by MOSTEK (Leave Blank)
is the ROM number (0-63 decimal) Specifies
ROM page
is the decimal number (n) of the lowest of
the four I/O port addresses selected where:
n:; 4a, 1..;; a ..;; 63
is 1 for Standard I/O
2 for Open Drain
3 for Driver Pull-up (Output Only)
is the Timer/External I nterrupt Address
Vector (4 Hexadecimal digits)
Columns 58-60 specify the desired number base for
the address field on the output listing.
Columns 63-65 specify the desired number base for
the data fields on the output listing. Each defaults
to DECIMAL when not specified. All other fields
on the option caid must be sPecified.
COMMENT CARD FORMAT
OPTION CARD FORMAT
The option card must always be the first card in
the input data file. The format of the option card
follows:
482
Each comment card must have an asterisk (*) in
column 1. All other columns are ignored. Acomment
card may occur any time after the option card in
the input file. Comment cards are optional.
TEXT FORMAT CARD FORMAT
The text format commands are used to describe
the format of the ROM· data cards which follow.
Text format commands should have the character
'X' in column 1 and should precede all ROM data
cards. The valid text format commands are:
X SEQUENCE
indicates that the ROM has sequence numbers in
columns 77-79. This command causes F8 ROM
to do sequence checking.
X BASE
HEX HEX
DEC DEC
specifies the number base of the ROM address input
and the ROM data input respectively: If no X BASE
card occurs, all fields are assumed to be decimal.
DATA CARD FORMAT
The data cards for F8 PSUs must have the character
'C' in column 1. The ROM truth table data card
format is as follows:
Column
2-9
Add
C
10-12
Bytes
14-16
Data 1
17-19
Data 2
20-22.....
Data 3..
77-79
Data 22
Add
is the ROM address of the first data field
on the card
is the number of bytes of data on the card
Bytes
( < 23) Same number base as address.
Data n specifies the data to be coded at ROM
address (Add + n - 1) for 0< n < = Bytes
Data 22 is a sequence number if an X SEQUENCE
card has occurred
NOTE: All numeric fields must be right justified.
OTHER INPUT METHODS
For information concerning other methods of input
contact a MOSTEK representative.
PACKAGE DESCRIPTION
40-Pin Dual In-line Ceramic
1---1- - 2.000 ~ 020-------11
~Fr~:
o:::~[r===~D~=====i"IHJ[J
"
1100
1/0
D Interfaces with MK3854 for DMA channel
1/0<=:>[:3(:::::)1/0
D Provides automatic refresh for dynamic RAMs.
1/0
D Low Power Dissipation Typically Less Than
335mW
<=:> .
MK 3870
(:::::)
1/0
F8 FAMILY
I/O<=>
GENERAL DESCRIPTION
I/O<=>
The 3852 DMI provides all interface logic needed to
include up to 64K bytes of dynamic or static RAM
memory in an F8 microcomputer system. In response
to control signals output by the 3850 CPU, the 3852
DMI generates address and control signals needed by
standard static and dynamic RAM devices. The
MK3852 DMI is manufactured using N-channel
Isoplanar MOS technology.
FUNCTIONAL PIN DESCRIPTION
1/0 (::::)
P
E
I/O<=:>
R
M
I
P
E
M
I/O<=>
H
E
R
A
L
S
o
I/O<=>
R
y
>
<
during all ROMC states except ROMC state 05
(store in memory); it can be used to generate the
clock signals required by many dynamic RAMs.
CPU SLOT high identifies portions of an instruction
execution cycle during which the 3850 CPU is
reading data out of RAM, or writing data into RAM.
CPU SLOT is a bi-directional signal. If held low
by external logic, it causes the address line drivers
and RAM WRITE driver to be held in a high impedance state.
BLOCK DIAGRAM
Figure 1
DATA BUS
CONTROL
SIGNALS TO
ALL ELEMENTS
DBO-DB7
ROMC DECODE
AND CONTROL
LOGIC
ROMCO-ROMC 4
16
TIMING
ADDRESS BUS
<
16*
ADDRO-ADDR 15
486
MEMORY
CONTROL
WRITE
REGDR
CPU READ
R"AMWiiiTE
AND
REFRESH
MIM IDLE
CYCLE
CYCLE
REO
CONTROL
CPU SLOT
DMA
DEVICE ORGANIZATION
This section describes the basic functional elements
of the MK3852 DMI. These elements are shown in
the DMI functional block diagram (figure 1).
PROGRAM COUNTER (PO) AND DATA
COUNTER (DC AND DC1)
The MK3852 DMI addressing logic consists of 3
16-bit registers, the Program Counter (PO) and the
Data Counters (DC and DC1).
The Program Counter will at all times address the
memory word from which the next object program
code must be fetched. The Data Counter (DC)
addresses memory words containing individual data
bytes or bytes within data tables to be used as
operands.
It is important to note that the 3852 DMI has an
auxiliary Data Counter (DC1). The contents of DC
can be saved in DC1 by using the instruction XDC
(exchange data counters). This instruction puts the
contents of DC into DC1 and the contents of DC1
into DC. DC~DC1.
PO will always address the memory location out
of which the next object program instruction byte
will be read. If the instruction requires data (an
operand) other than an immediate to be accessed
DC must address memory. PO cannot be used to
address a NON-immediate operand since PO is saving
the address of the next instruction code.
THE STACK REGISTER P
The MK3852 OM I addressing logic contains a fourth
16-bit register called the stack register (PI. The stack
register is a buffer for the program counter PO. The
contents of the stack register are never used directly
to address memory.
The following instructions access P
LR K, P
Move the contents of P to the CPU
scratch pad K registers
LR P,K
Move the contents of the CPU K
scratch pad registers to P
PK
Save the contents of PO in P then
move the contents of CPU scratchpad registers 12 and 13 to PO
PI H'aaaa'
Move the contents of PO to P then
load the hexadecimal value into PO
In addition, when an interrupt is acknowledged, the
contents of PO are saved in P.
MEMORY CONTROLS
Memory Control logic generates appropriate timing
and control signals needed by RAM to input or
output data. Timing and control signals are generated in response to ROMC states, as decoded by
the Control Unit.
INCREMENTER ADDER LOGIC
There are only two arithmetic operations that memory devices need to perform on the contents of
memory address registers:
1. Increment by 1 the 16-bit value stored in an
address register.
2. Add an 8-bit value, treated as a signed binary
number (subject to twos complemented arithmetic) to the 16-bit value stored in address register.
The incrementer adder logic performs these two
functions in the MK3852 DMI.
THE DATA BUS
The 8-bit data bus is the main path for transfer of
information between the MK3850 CPU and other
devices in the F8 microprocessor system.
ADDRESSABLE I/O PORTS
The 3852 DMI has four I/O port addresses reserved
for its use. There are two versions of the 3852 DMI;
one has I/O port addresses OC, 00, OE and OF for
its four I/O ports; since these addresses are also used
by the 3853 SMI, another version of the 3852 DMI
uses I/O port address EC, ED, EE and EF. This
allows an F8 microcomputer system to include
. both a 3852 OM I and a 3853 SM I.
I/O port addresses OE and OF (or EE andEFl, though
reserved for the 3852 OM I, are not used. Port OC
(or EC) is a general purpose, 8-bit data storage
buffer which can be loaded with the OUT or OUTS
instruction and read using the I N or I NS instruction.
Port 00 (or ED) is a control register which controls
memory refresh and DMA operations.
DMA AND REFRESH CONTROL
POP
Move the contents of P to PO
Because of the organization of the F8 microcomputer
system, there is a period within every instruction
execution cycle when the CPU is not accessing
memory.
487
DMA and Refresh Control logic generates timing and
control signals that identify time periods when the
CPU is not accessing memory; during these time
periods memory is refreshed, or DMA data accesses
occur.
The WRITE clock refreshes and updates the MK3852
DMI. A machine cycle begins with the fall of the
WR ITE clock and the system control lines become
stable shortly after the start of the cycle.
OPERATIONAL DESCRIPTION
CLOCK TIMING
All timing within the MK3852 DMI is controlled by
and WRITE, which are input from the MK3850
CPU. Each machine cycle will contain either 4
clock periods (short cycle) or 6 clock periods
(long cycle).
INSTRUCTION EXECUTION
The MK3852 DMI responds to signals which are
output by the MK3850 CPU in the course of executing instruction cycles.
Table 1 summarizes the response of the MK3852
DMI to the ROMC states.
Table 1
ROMCSTATES
ROMC
(Hexadecimal)
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
488
OPERATION PERFORMED
COMMENT
DB-( (PO)); PO-PO + 1
DB-«PO)); PO-PO + DB
DB-«DC)); DC-DC + 1
DB-«PO)); PO-PO + 1
PO-P
«DC))-DB; DC-DC + 1
DB-DCU
DB-PU
P-PO; DB+-H'OO'; POL, POH-DB
DB-DCL
DC-DC + DB
DB-PL
DB-«PO)); DCL-DB
P-PO+ 1
DB-«PO)); DCL-DB
NO OPERATION
NO OPERATION
DB-«PO)); DCU-DB
POL-DB; P-PO
NO OPERATION
POU-DB
PU-DB
DCU-DB
POL-DB
PL-DB
DCL-DB
«pp))-DB or ((p))-DB
DB-( pp ) or DB-((p))
NO OPERATION
DC!:;DC1
DB-POL
DB-POU
OP CODE, FETCH
BRANCH OFFSET FETCH
IMMEDIATE OPERAND FETCH
EXTERNAL RESET
Definitions:
DB
PO
DC
DCl
P
pp
p
lA
L
u
()
....
.
•
•
.
·
·
·
•
·
·
·
Data Bus
Program Counter
Data Cou nter
Aux Data Counter
Stack Register
Two hex digits (long 1/0 port address)
One hex digit (short 1/0 port address)
Interrupt address vector
Lower byte suffix
Upper byte suffix
Contents of
- transfer to
~ - exchange
MEMORY ADDRESSING
Any dynamic RAM which is controlled by the
3852 DMI will have a PAGE SELECT input, which
must be true if the memory is to respond to read
or write control signal sequences.
PAG E SE LECT true is created by logic external to
the 3852 DMI, and defines the dynamic RAM address
space. PAGE SELECT true can be generated in any
way; there are no special rules.
For example, consider an F8 system with 1 K bytes
of ROM on a 3851 PSU and 4K bytes of dynamic
RAM controlled by a 3852 DM I; address ranges
will be as follows:
1K bytes of ROM
4K bytes of RAM
000016 to 03FF16
040016 to 13FF16
In binary format, the dynamic RAM address space
is defined by:
~
NMO
o
a:
a:
Cl
Cl
«
Minimum: 0 0 0
Maximum:O 0 0
Cl
Cl
«
o0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
PAGE SELECT may be the OR of ADDR 12,
ADDR11 and ADDR10, which are shown above.
Depending on the way in which dynamic RAM is
being used, PAGE SELECT may be a simple memory
enable signal, or it may be ANDed with CPU READ
and RAM WRITE, to generate local versions of
these two signals which are locally true only.
3852 DMI
SPACE
ADDRESS
REGISTERS'
ADDRESS
As described in Table 1, certain ROMC states require
the contents of the high order, or low order half of
PO, P, or DC to be placed on the data bus. If there
is more than one memory device in an F8 system,
only one device must respond to these ROMC states.
The 3851 PSU uses its address
mine if it is to place address
the data bus; for the 3851
memory and address registers'
be identical.
select mask to deterregister contents on
PSU, therefore, the
address spaces must
The 3852 DMI address registers' address space is
identified by the REGDR signal; if this signal is not
clamped low, the 3852 will place data on the data
bus in response to ROMC states that require data
from PO, P or DC to be placed on the data bus.
If REGDR is derived from the PAGE SELECT
signal, then the RAM memory and the 3852 DMI
address registers' address spaces will coincide.
On the other hand, it is a good idea to make the
3852 DM I address registers' address space cover all
addresses that are not part of another memory
device's address registers' address space. For
example, the following address spaces would be
desirable:
ADDRESS SPACES
3851 PSU
3852 DMI
MEMORY
ADDRESS
REGISTERS
000016-03FF 16
040016-13F F 16
000016-03F F 16*
040016-FFFF16
*For the 3851 PSU, the two address spaces must be
identical.
If the address space for the address registers covers
all possible memory addresses, then instructions
that read data out of address registers will always
generate a valid response.
In the above illustration, if memory and address
registers' address spaces coincided for the 3852,
then in response to instructions that require data
to be output from PO, P, or DC, no device would
respond when the selected address register contains
a value in excess of 13F F 16; as a result, invalid values
would be received by the 3850 CPU.
ADDRESS CONTENTIONS
When a 3852 DM I is present in an F8 system, memory addressing contentions are resolved as described
in Memory Addressing, with one exception: the
3852 DMI has a DC1 register and the 3851 PSU does
not.
The XDC instruction (ROMC state 1D) causes the
contents of the DCO and DC1 registers to be exchanged; having no DC1 register, the 3851 PSU does
not respond to this ROMC state, therefore 3851 PSU
and 3852 DM I devices can have different values in
their DC registers, and each value can be within the
different address spaces of the two memory devices.
An instruction that requires data to be output from
DC may now cause two devices to simultaneously
place different data on the data bus. This may be
illustrated as follows:
PSU
Before XDC: DC =XXXX
DC1=
After XDC: DC =XXXX
DC1
DMI
XXXX
YYYY
YYYY
XXXX
If XXXX happens to be in a PSU's address space
while YYYY is in the DMI address space, then
address contentions will arise.
489
Even if XXXX is not in the PSU's address space,
address contentions may arise due to the fact that
memory reference instructions will increment
different DC contents. Suppose two memory reference instructions are executed following one XDC,
then another XDC is executed; this is what happens:
PSUAfter first XDC:
DC = XXXX
DC1=
After two memory
DC = XXXX+2
reference instructions: DC1 =
After second XDC:
DC = XXXX+2
DC1 =
DMI
YYYY
XXX X
YYYY+2
XXXX
XXXX
YYYY+2
An address contention may arise if DC contents
approaches the boundary of the PSU address space.
For example, if the address space boundary occurs
at XXXX+1, the PSU and the DMI will both consider
themselves selected.
The following coding instruction sequence shows
how to use the DC instruction without encountering address contentions. The example allows use of
a second address value YYYY, which is held in DC1,
while using the H register' to temporarily hold the
first address value, XXXX. Address YYYY, which
at the beginning of the example is held in DC1,
must be in the DM I address space. The address
XXXX may be in any address space.
INSTRUCTION PSU
DCO
LR H,DC
DCIZZZZ
XDC
DMI
DCO
DC1
XXXX
XXX X
YYYY
ZZZZ
ZZZZ
ZZZZ
YYYY
YYYY
ZZZZ
tion is used to load DC1. Consider the following
instruction sequence:
INSTRUCTION
DCI
XDC
DCI
YYYY
ZZZZ
PSU
DC
DMI
DC
XXXX
YYYY
YYYY
ZZZZ
XXXX
YYYY
WWWW
ZZZZ
P
WWWW
YYYY
YYYY
YYYY lies in the address space of the DMI, ZZZZ
lies anywhere, XXXX and WWWW are arbirtary
initial values. The DCI instructions could just as
well be LR DC, H or LR DC, O.
The exchange of DC and DC1 becomes most powerful when a series of swaps are used to add two blocks
of memory, or to move data from one block to a
second. The XDC instruction can be used to do this
so long as neither block is in a PSU's address space.
Notice that the DC of the PSU is out of step throughout the example.
INSTRUCTION
psu
PO
DCI
ZZZZ
LM
XDC
ST
XDC
DMI
DC
DC1
xxxx
xxxx
ZZZZ
ZZZZ+1
ZZZZ+1
ZZZZ+2
ZZZZ+2
ZZZZ
ZZZZ+1
YYYY
YYYY+1
ZZZZ+ 1
YYYY
YYYY
YYYY
ZZZZ+1
ZZZZ+l
YYYY+1
ZZZZ+L'>Z+LW·1
ZZZZ+L'>Z+t:.Y-l
ZZZZ+L'>Z+t:.Y
YYYY+t:.Y
ZZZZ+L'>Z
YYYY+t:.Y-1 ZZZZ+L'>Z
yyyy+t:.y ZZZZ+L'>Z
wwww
ZZZZ+L'>Z
Other Instructions
LM
XDC
ST
DCI
WWWW
WWWW
In the above example ZZZZ and YYYYboth lie in
the address of a DMI. The space spanned by ZZZZ
to ZZZZ + t:.Z + t:. Y must be outside of any PSU's
address space.
Other Instructions
TIMING SIGNALS OUTPUT BY A
XDC
LR DC,H
ZZZZ+N YYYY+N ZZZZ
YYYY+N
ZZZZ+N ZZZZ
XXXX
XXXX
YYYY+N
For the above scheme to work, it is only necessary
for ZZZZ through ZZZZ+N to be outside any PSU's
address space.
If the value XXXX through XXXX+N is outside of
any PSU's address space, then the DCI ZZZZ instruction may be omitted.
In many cases, it will not be necessary to restore
the XXXX value; then the LR H,DC and LR DC, H
instructions can also be omitted-letting a subsequent
,?C loading instruction synchronize the DC's.
Before a value held in DC1 can be used, it must
first have been loaded into DC1. The XDC instruc-
490
3852 DMI
Within an instruction cycle, there may be either two
or three memory acces:. periods, depending on
whether the instruction cycle is long or short. A
memory access period is equivalent to two clock
periods, and is identified by CYCLE REO, which is
a divide-by-two of <1>. Whether the instruction cycle
is short, or long, depends on the source and destination of the data being transmitted during instruction
execution.
During the first memory access period, the 3852
DMI outputs the contents of PO on the address
lines of ADDRO-ADDR15.
In effect, 3852 DMI logic beings by assuming that
a memory read is to occur, with the memory address
provided by PO.
While the contents of PO are being output on the
address lines, the 3852 DMI control unit, in parallel,
decodes the ROMC state which has been received
from the 3850 CPU.
If the assumed logic proves to be correct, or if no
memory access is to occur, then the second access
period can be used for memory refresh or DMA.
If the instruction, once decoded by the CPU, specifies
a memory read with another memory address, then
the 3852 DMI wastes the first access period. The
instruction cycle will always be long in this case.
During the second access period, the required
memory access is performed, while memory refresh
occurs, or DMA is implemented in the third access
period.
If a memory write instruction is decoded, then no
access periods are available for memory refresh
or DMA.
Four variations of the in~truction cycle result. The
timing diagrams illustrating the four variations
represent worst cases, and assume td 2 = 150ns.
These are the four variations:
3852 DMI TIMING SIGNALS OUTPUT DURING A SHORT CYCLE MEMORY READ WITH ADDRESS
FROM PO
Figure 2
~------------------~Op5------------------~
WRITE
500n5=1
ADDRESS LINES _ _ _ _ _ _ _X ' " - - - - - - - - S T - A - B - L - E - - - - - - - - -
DATA BUS
__
I
~
=i
____________________
i=noM±1
00ns
X"---D-A-T-A-,S-TA--SL-E-F-R-O-M--R-A-M---
-JI~----~------------_
~14~-------_'_.2_5_PS_-~~~~~~~~~~!II~------------______
CPU READ - - - - - - - - _
~
~ ~,. on_S_~__'_.2_7_IlS____________
~ ~~~
CPU SLOT
~
::1=
.....- - - - 1 . 0
------/
PS--------..f
1. The instruction fetch. The memory address originates in PO and the instruction cycle is short. Timing is
shown in Figure 2.
491
3852 DMI TIMING SIGNALS OUTPUT DURING A LONG CYCLE MEMORY READ, WITH ADDRESS
OUT OF PROGRAM COUNTER
Figure 3
~"'I.·~~~~~~=========_3._0_I'S~~~~~-=/-,...:.-=--=----_-~~'..
WRITE..../j·
r--450nS~
_ __
.1
r--500ns~
I
ADDRESS LINES
X,...-------ST-A-B-LE--------
I
!==770nS±100nS--j
~
I
DATA BUS
I.
·11
1.251'S
....J/r.",---------
CPU READ,
"'-..... _ _ _ _ _
t:'" ~-1 ,~"'
CPU SLOT
/
[
DATA STABLE FROM RAM
j
'J... . . ______-J~
~~
- i 170
I nS
MEMIDLE "
CYCLE REO
~750nS~/r----__'"
I
'"
-1 ~~O
I_
/ r - - -....."'--
·I'-----J
1001'S
2. An immediate operand fetch. The memory address originates in PO, and the instruction cycle is long. Timing is shown in Figure 3.
3852 DMI TIMING SIGNALS OUTPUT DURING A LONG CYCLE MEMORY READ, WITH ADDRESS
OUT OF DATA COUNTER
Figure 4
WRITE
_-_-_--:--_-_3_.0_I1_S~~~~~~~~~~~~~~-I---"'iL
-'i
,1"""4:_-_-_-_-_-_-_-_-_-_-_-_-_-_-
I
r-450nS-l....>--_ _ 1.25I1S-----..~1
ADDRESS LINES
I
X,...------:S=T:-::A-=S:-:-L-==E-------:--
~900nS~
I
I
I
><,...-DA-T-A-S-TA-B-L-E~F-RO-M~R-A-M--
I
DATA BUS
1·>-----1-.2-5-I1S--2.15I1S-·-I------+l·,
...
CPU READ
\~_ _ _ _-JI,...------~------~I---
I
~cii~~_ns_-j_
CPU SLOT
MEMIDLE
-.J ~~0l--
,~-----------------------------~'-_ _ _ _-_-_I~r
_
T.·--------2.27I1S--------~·11
InS
~~--------------------------------:~g0l--,
~750nS-.J
I
\
-l ~~O I·
1r---~\,-
1.0 I1
_ _oJ/
\,-_ _oJ/
S----]
3. A data fetch. A data byte is output from an address register, or the memory address originates in DC, therefore the instruction cycle is long. Timing is shown in Figure 4.
492
3852 DMI TIMING SIGNALS OUTPUT DURING A WRITE TO MEMORY
Figure 5
WRITE
~:!.===============~_3_.0_~S_-_-_-_-_-_-_-_-__-_-_-_--J--/~--------~~
~450 nS /""".---1.25 ~S ----+I-I
j.--1.3 ~S
-I
--Ii
ADDRESS liNES __________7-________________--J)(r------------~S~T7A~Bl~E~------------
DATA BUS
)(r-------=D7A=TA~ST=A~B~l~E~F~R~07M~C~P~U~------
I
I.
1.85~S-_____+l-1350ns
MIN
I.
...1
RAM WRITE ---------------------------------------~
II
CPU READ
CPU SLOT
MEMIDlE
.
2.3
~~O 1-
MINr----
L-J_'I'-----"
~S
MAX
-.
-----~I--~\~----------------------------------
r450nS~
~~AI
\~_________________________________________
-!?~I·750ns---1
CYCLE REO --------~I--~\
---J ~~ I.
Ir----~\~____~I
1.0~S--1
4. A memory write. Data is written into the RAM memory location addressed by DC. Timing is shown in Figure 5.
CPU SLOT and MEM IDLE identify the way in
which a memory access period is being used. Figures
6 and 7 illustrate the relationship.
When the 3852 DMI is refreshing dynamic memory
CPU SLOT and MEM IDLE are both low.
When the 3850 CPU is accessing memory, CPU
SLOT is high; RAM WR ITE and the address lines
are driven at this time.
3852 DMI logic is able to achieve two memory
accesses with in one instruction cycle by pursuing
the logic sequence summarized in Table 2. Buffer/
latches are placed on the F8 data bus lines between
the RAM and the F8 system to hold the data fetcher.!
during the first access.
When memory is available for DMA access, CPU
SLOT is low, and MEM IDLE is high.
493
TIMING FOR MEMORY REFRESH AND DMA DURING A SHORT CYCLE MEMORY READ, WITH ADDRESS OUT OF PROGRAM COUNTER
Figure 6
I\
WRITE--.I:
~
450nS
~
/
I..
r- ±X
500 nS
ADDRESS LINES
FOR REFRESH
~I
2.0~S
770 nS ± 100 nS
I
CPU AD DR
+ !~O X
::1:==500 ns--1
I
REFRESH ADDR
I
J
100
I. :I. D::::~
400nS
f--500 "'--+-770
ADDRESS LINES
FOR DMA
X
I
,S<
oS
OR
";:
I
CPU ADDR
HIGH IMPEDANCE
1----770 nS ± 100 ns:::-I
DATA BUS
CPU READ
I
X'--D-A-T-A-S-T-A-B-LE-FR-O-M-R-A-M-
~--------------------I~-----------------
I"
1.25~S
I
-1 . /if-1.27~S
---1 \
450nS
CPU SLOT
MEMIDLE
FOR REFRESH
~II
-':yr---------~I
, ' -_ _ _ _ _ _ _
,-
,'-_______..Jr-
I
--.I
I
170
nS
~O
I......
t---
._
I
1.25~S;------I~~
~2n~~
MEMIDLE
FOR DMA
CYCLE REQ
I ,'-_________f
I
.....t-----------2.2~S;-----------..~
\~ _ _ _--I/ ~~'-___,.JI
~
250
nS
494
~
I"
1.0J.lS
TIMING FOR MEMORY REFRESH AND DMA DURING A LONG CYCLE MEMORY READ WITH ADDRESS OUT OF PROGRAM COUNTER
'
Figure 7
r-----'\1~-:===========~~_-_-_-_3.0_~_S==============_-r===\L----I~I
:=l
I-I
I
±
WRITE
450 nS
~500 nS
770 nS + 100 nS
X
ADDRESS LINES
FOR REFRESH
_ _ _ _...J
ADDRESS LINES
FOR DMA
_ _ _ _...J
DATA BUS
400nS
.. ..
X'-__---'-'R"'EF..:;A:::;D:::,:DR.!..-_ __
CPU ADDR
400nS
~500nS
1~ ~SO ~ tif~:d
±=770nS±
CPU ADDR
X
~
770 nS ± 100 nS
~450ns~'
1.25~S
HIGH IMPEDANCE
I
:1,..-___________
_____________X
I_
CPU READ
....
STABLE DATA FROM RAM
·1
,r------------
1.27~S---I
CPU SLOT
.~''''
FOR REFRESH
----I.~----------~~-----------
-j ~SO I--
r:;fnS
~:
f--
MEMIDLE
----:--\1
FOR DMA
._
1.25~SI
/ r - - - - -_____
. /\,\.. _ _ _ __
I
22~S----------l-.
\\..__--JrTable 2
OPERATION PERFORMED DURING
INSTRUCTION CYCLE
FIRST ACCESS
SECOND ACCESS
THIRD ACCESS
No memory access, or read from
memory addressed by PO. (See Figure
2.)
[PO]--+AO - A 15
Latch data on F8 data
bus. Second memory
access for DMA or
refresh.
None
No memory access, or read from
memory addressed by PO. (See Figure
3.)
[PO]-AO- A15
Latch data on F8 data Th i rd memo ry access
not used.
bus. Second memory
access for DMA or
refresh.
Read data from memory addressed by
register other than PO, or read data
from address register. (See Figure 4.)
[PO]-AD- A15
[Other register]- AD Latch data on Fa
data bus. Third
-15
memory access for
DMA or refresh
Write data to memory. (See Figure
5.)
[PO]-AO-A15
[DC]-AD - A 15
[
Access memory to
write data. No DMA
or refresh.
] means "contents of register identified within square brackets.
495
MEMORY
ACCESS
REFRESH
AND
DIRECT MEMORY
These two topics are covered together, since in
terms of 3852 DMI logic, they are similar operations.
CYCLE REQ identified 2 or 3 memory access periods
witnin an instruction cycle.
Either the first or the second access period, as summarized in Table 2, is reserved for the instruction
cycle being decoded. Let us refer to this as the
"reserved" access period. If the ROMC state for the
instruction cycle requires data to be read out of
RAM, then the read occurs during the reserved
access period. If the ROMC state for the instruction
cycle requires data to be input to an address register,
or if no data movement occurs on the data bus, then
the reserved access period is not used for any memory
access-it is, in effect, wasted.
One more memory access may occur within the
instruction cycle; this occurs during either the second
or third access period, as summarized in Table 2,
while the data bus latches hold data accessed during
the first period. We will refer to this 1S the "free"
access period.
Some available free access periods must be used to
refresh dynamic RAM. A refresh uses logic within
the 3852 DMI. Therefore a refresh occurs in parallel
to anything else that is going on.
If the free access period is not used to refresh dynamic RAM, it may be used by a 3854 OMA device
to perform direct memory accesses. The OMA uses
a separate data channel to access memory, so OMA
can occur in parallel with anything else that is going
on within the F8 system.
If a ROMC state received by the 3852 OMI requires
data to be output from an address register, then
the 3852 OMI will become the selected data source
if REGOR is allowed to go high.
DATA INPUT TO RAM
Figure 5 provides worst case timing when data is
written into RAM. Data is transferred through tristate buffers on the data bus and into RAM.
RAM WRITE is pulsed low by the 3852 OMI to
enable the transfer of data off the data bus, into
RAM. The tri-state buffers or multiplexers between
data bus and RAM WRITE data lines are necessary
if OMA sources are also allowed to write into RAM.
DATA INPUT TO THE 3852 DMI
Problems of addressing contention are posed by
having duplicated address registers; one step in resolving this possible problem is to force every memory device to read onto its address registers whenever
a ROMC state specifies any such operation. Address
space concepts therefore do not apply when data is
read into 3852 OMI address registers.
INPUT/OUTPUT
There are two versions of the 3852 OM I; each has
four reserved I/O port addresses, implemented as
follows:
PORT ADDRESSES
STANDARD
OPTION
OC
00
DATA OUTPUT BY RAM
Figures 2, 3, and 4 provide worst case timing when
RAM, controlled by the 3852 OMI, outputs data
onto the data bus. In these figures it is assumed that
CPU SLOT is used to strobe the RAM data into
the data bus latches.
CPU READ is output high by the 3852 OMI to
enable transfer of data from the data bus buffers to
the data bus. Recall that dynamic RAM have its own
connection to the data bus via buffer/latches; data
is not transferred via the 3852 OM I.
Observe that CPU READ high is similar to D8DR
low-each is active when its respective data bus
drivers are turned on.
OE
OF
EC
ED
EE
EF
FUNCTION
General purpose latch
Memory IDMA control
Not implemented
Not implemented
Option port addresses are used in F8 systems that
include both a 3852 OMI and a 3853 SMI.
The implemented I/O ports are accessed via IN,
INS, OUT and OUTS instructions, just like any
other I/O port. However, the 3852 OMI I/O ports
are internal latches, having no connection to I/O
pins or external interface. REG DR, if not clamped
low by an external device, will go high during IN or
I NS instructions that select either of the OM I ports.
However, clamping REGOR low does not inhibit
data bus driving during I/O as it did during the
output of address registers.
DATA OUTPUT BY THE 3852 DMI
I/O port OC (or EC) is used as a general purpose,
8-bit data storage location.
REGOR defines the address space of the address
registers within the 3852 OMI.
I/O port 00 (or ED) controls memory refresh and
OMA as follows:
49.6
11s/sH 1+lo
7
3
I NOT 'uSED '
ut
SYSTEM INITIALIZATION
I _ B I T NUMBER
An FB system is initialized by power on, or EXT
RESET being pulsed low at the CPU.
OMA """'"",
When an FB system is initialized, DMA is turned off
and memory refresh is on, with refresh every fourth
cycle selected.
0= DMA enabled.
1= Refresh memory.
0= No memory refresh.
1= Refresh every fourth instruction cycle.
Contents of all other registers are indeterminate;
reading the control port OD (or ED) also gives indeterminate results, although the DMA/refresh
state of the DMI has been initialized.
0= Refresh every eighth instruction cycle.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATING (All voltages with respect to VSS)*
VGG······················································ . +15V to -0.3V
VDD ........................................................ +7V to -0.3V
All other inputs and outputs ..................................... +7V to -0.3V
Operating temperature, T A (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
Storage temperature - Ambient (Ceramic) ... , ......................-65°C to +150°C
Storage temperature - Ambient (Plastic) ...........................-55°C to +125°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
II
RECOMMENDED DC OPERATING CONDITIONS
(O°C"';;TA"';;70°C)
SYMBOL
PARAMETER
MIN
VDD
VGG
VSS
Supply
Voltage
4.75
11.4
0
TYP
5.0
12.0
0
MAX
UNITS
5.25
12.6
0
Volts
Volts
Volts
TEST CONDITIONS
DC ELECTRICAL CHARACTERISTICS
(O°C ",;;TA"';; 70°C) VDD = +5V ± 5%; VGG = +12V ± 5%; VSS = OV
SYMBOL
PARAMETER
IDD
IGG
VDD Current
IGG Current
MIN
DATA BUS (DBO-DB7)
PARAMETER
SYMBOL
VIH
VIL
VOH
VOL
IIH
IlL
CI
I nput High Voltage
I nput Low Voltage
Output High ~oltage
Output Low Voltage
Input High Current
Input Low Current
Capacitance
TYP
MAX
UNITS
35
13
70
30
rnA
rnA
MIN
MAX
UNITS
3.5
VSS
3.9
VSS
VDD
.B
VDD
.4
1
-1
10
Volts
Volts
Volts
Volts
~A
~A
pF
TEST CONDITIONS
f=2MHz, Outputs unloaded
f=2MHz, Outputs unloaded
TEST CONDITIONS
IOH = -100~A
IOL = 1.6mA
VIN = VDD, three-state mode
VIN = VSS, three-state mode
Three-state mode
497
CONTROL LINES (ROMCO-ROMC4), AND CLOCK LINES (, WRITE)
SYMBOL
PARAMETER
MIN
MAX
UNITS
3.5
VOO
VSS
.8
Volts
Volts
JJ.A
pF
TEST CONDITIONS
,--
VIH
VIL
IL
CI
Input High Voltage
Input Low Voltage
Leakage Current
Capacitance
1
10
VIN = VOO
ADDRESS LINES (ADDRO-ADDR15) AND RAM WRITE
SYMBOL
PARAMETER
MIN
MAX
UNITS
VOH
VOL
IL
Output High Voltage
Output Low Voltage
Leakage Current
4.0
VOO
.4
1
Volts
Volts
JJ.A
TEST CONDITIONS
IOH = -1mA
IOL = 3.2mA
VIN = VOO
REGDR AND CPU SLOT
SYMBOL
PARAMETER
MIN
MAX
UNITS
VOH
VOL
VIH
VIL
IlL
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Low Current
3.9
VOO
.4
Volts
Volts
Volts
Volts
mA
IL
Leakage Current
VSS
3.5
VSS
-3.5
VOO
.8
-14.0
1
JJ.A
TEST CONDITIONS
IOH = -300JJ.A
IOL = 2mA
Internal Pull-up to VOO
VIN =.4V and device outputting a logic "1"
VIN = VOO
CPU READ, MEMIDLE, AND CYCLE REO
SYMBOL
PARAMETER
MIN
MAX
UNITS
VOH
VOL
IL
Output High Voltage
Output Low Voltage
Leakage Current
3.9
VOO
.4
1
Volts
Volts
JJ.A
498
VSS
TEST CONDITIONS
loW-1mA
IOL = 2mA
VIN = VOO
AC ELECTRICAL CHARACTERISTICS
(DoC';;; TA';;; 70°C) (VDD = +5V ± 5%; VGG
SYMBOL
= +12V ± 5%; VSS = OV)
PARAMETER
MIN
TYP MAX
TEST
COND
UNIT
P
-lBO
ns
tdl
+5Q-td 2
2P+SQ-td 2
2P+400-td 2
ns
1
tcsl
CPU SLOT + Delay
BO-td 2
320-td 2
ns
1
tcs2
CPU SLOT - Delay (PCO access)
2P+400-td 2
ns
1
tm4
MEMIDLE - Delay (DC access)
6P+400-td2
ns
1,4
tCY3
CYCLE R EQ + to + Edge Delay
2P
twr2
twr3
RAM WRITE - Delay
300
2S0
1,4
1,4
4P+SO-td 2
SP
S
<
E
I/O<=:>
L...._---'
W~
R
Y
>
PIN CONNECTIONS
ADDRO-ADDR 15 - The address bus provides the
location of a memory read or write cycle.
DBO-DB7 - The Data Bus provides bi-directional
communication between the 3850 F8 CPU and the
3853 SMI and all other F8 peripheral devices.
VGG ---- I
~
-
2
WRITE -
3
INT REQ -
4
PRfTN _
404-- Voo
39 _
ROMC 4
38 37 _
ROMC 2
ROMC 3
ROMC I
5
36 -
RAM WRITE -
6
35 _
ROMC III
EXT INT -
7
34 -
CPU READ
AD DR 7 ADDR 6 _
8
33 - - REGDR
32 _
ADDR 15
TYPE
ADDR 5 -
10
Bi-directional,
tri-state
Output
Input
Output
Input
Output
Input
Input/Output
Output
Input
Input
ADDR 4 - I I
30 _
ADDR 13
ADDR 3 -
12
29 _
ADDR 12
ADDR 2 -
13
28 -
ADDR II
ADDR I -
14
27 -
ADDR 10
ADDR Ii'J -
15
26 -
ADDR 9
DB 0 -
16
25 _
ADDR 8
ROMCO-ROMC4 - These lines provide the 3853 SMI
with control information from the 3850 F8 CPU.
Address Lines
Clock Lines
Interrupt Request
Priority In Line
Write Line
External Interrupt Line
Register Drive Line
CPU Read Line
Control Lines
Power Supply Lines
I/O<=>
I/O<=:>
FUNCTIONAL PIN DESCRIPTION
ADDRO-ADDR15
The MK 3853 Static Memory Interface (SMI) provides
all necessary address lines and control signals to
interface up to 65,536 bytes of Static RAM, ROM
or PROM to an F8 microcomputer system. When
quantities do not justify the mask charges for the
MK 3851 PSU, or a fast turn around is of high
importance, the MK 3853 SMI can be used to
interface the F8 to EPROM or fusible-link bipolar
PROMs. The 3853 SMI along with standard PROM
can emulate the memory function of the 3851 PSU,
while the 3861 provides the I/O ports, interrupt and
timer features of the 3851 PSU. The 3853 is a high
performance MOS/LSI circuit using N-channel
Isoplanar technology.
DESCRIPTION
Data Bus Li nes
MK 3870
F8 FAMILY
Less Than
GENERAL DESCRIPTION
PIN NAME
DBO-DB7
B (: : :)
I/O <=>
9
MK 3853
DB I ....... 17
DB 2 __ 18
_20
_
ADDR 14
24 ..... DB 7
23 __ DB 6
DB 3 - - 19
vss
31
22 - - DB 5
L _ _ _ _ _- - ' I
21 - - DB 4
503
BLOCK DIAGRAM
INTERRUPT
C~~~rcOl
14-----,
PORT SELECT
LOGIC
16
ADORO - ADOR15
Figure 1
<1>- This is the system clock generated by the 3850
F8 CPU.
data from the data bus is to be written into a RAM
location specified by the address bus.
WRITE -
CPU READ - This signal when high, specifies that
data is to be read from the memory array interfaced
to the SMI.
This clock defines the machine cycle.
EXT INT - When an external circuit pulls this
input "low", an external interrupt will be latched
into the SMI if its interrupt control register has
been set up to allow external interrupts. The SMI
will then communicate this interrupt request to the
CPU via INT REO line.
PRI IN - This input signals the SMI that a higher
priority peripheral has an interrupt request pending
on the CPU. If the SMI has already requested an
interrupt, the interrupt request will be maintained,
but will not be serviced by the CPU until PRI IN is
in the "low" state.
INT REO - This is an open drain output that is
wire ORed with the corresponding INT REO outputs of all other peripherals to form the interrunt
.
request input to the CPU.
RAM WRITE - This signal, when low, specifies that
504
REGDR (OUTPUT/INPUT) - This signal functions
both as an input and an output, to gate PO, DC, and
I/O ports '~C' and 'OD' onto the data bus at the
proper time.
DEVICE ORGANIZATION
This section describes the basic functional elements
ofthe MK 3853 SMI. These elements are shown in
the SMI functional block diagram (figure 1).
PROGRAM COUNTER (PO) AND DATA
COUNTERS (DC AND DC1)
The MK 3853 SMI addressing logic consists of 3
16-bit registers, the Program Counter (PO) and the
Data Counters (DC and DC1)
The Program Counter will at all times address the
memory word from which the next object program
code must be fetched. The Data Counter (DC)
. addresses memory words containing individual data
bytes or bytes within data tables to be used as
operands.
It is important to note that the 3853 SMI has an
auxiliary Data Counter (DCl). The contents of DC
can be saved in DCl by using the instruction XDC
(exchange data counters). This instruction puts the
contents of,..~ into DCl and the contents of DCl
into DC. D~DC 1.
PO will always address the memory location out
of which the next object propram instruction byte
will be read. If the instruction requires data (an
operand) other than an immediate operand to be
accessed, DC must address memory. PO cannot be
used to address a NON·immediate operand since PO
. is saving the address of the next instruction code.
THE STACK REGISTER P
The MK 3853 SMI addressing logic contains a fourth
16-bit register called the stack register (P). The stack
register is a buffer for the program counter PO. The
contents of the stack register are never used directly
to address memory.
The following instructions access P
LR K, P
Move the contents of P to the CPU
scratch pad K registers
and I/O ports ('OC'H and 'OD'H) onto the data bus
at the proper time. If the 3851 PSU or 3852 DMI
are not used in the system, then REGDR may be left
open. If one or more 3851 PSU's are used in a
system without the 3852 DMI, then the signal DBDR
from all PSU's in the system should be tied together
and gated through an open collector AND gate and
tied to REGDR of the SMI. If the 3852 DMI and
the 3853 SMI are used in a system without the
3851 PSU, then .REGDR of the SMI should be left
open and REGDR of the 3852 DMI should be tied
low to prevent a data bus conflict when the PO and
DC registers are output onto the data bus.
INCREMENTER ADDER LOGIC
There are only two arithmetic operations that memory devices need to perform on the contents of
memory address registers:
1. I ncrement by 1 the 16-bit value stored in an
address register.
2. Add an 8-bit value, treated as a signed binary
number
(subject to twos complemented
arithmetic) to the 16-bit value stored in address
register.
The incrementer adder logic performs these two
functions in the MK 3853 SMI.
INTERRUPT LOGIC
This logic responds to an interrupt request signal
which may originate internally from timer logic, or
be input by an external device. Based on priority
considerations, the interrupt request is passed on to
the MK 3850 CPU.
LR P,K
Move the contents of the CPU K
scratch pad registers to P
PK
Save the contents of PO in P then
move the contents of CPU scratchpad registers 12 and 13 to PO
TIMER LOGIC
PI H'aaaa'
Move the contents of PO to P then
load the hexadecimal value into PO
Every MK 3853 SMI has a polynomial shift register
which may be used in conjunction with interrupt
logic to generate real-time intervals.
POP
Move the contents of P to PO
Upon counting down to zero, the timer uses
interrupt logic to signal that it has timed out.
In addition, when an interrupt is acknowledged, the
contents of PO are saved in P.
MEMORY CONTROLS
The timer is programmable and is handled as though
it were an I/O port. Using an OUT or OUTS instruction, a value may be loaded into the timer in order to
determine the real-time period at the end of which a
time-out interrupt will be generated.
The 3853 SMI provides three memory control outputs: RAM WRITE, CPU READ and REGDR.
THE DATA BUS
RAM WRITE is used to control the read/write cycle
,of a static memory. RAM WRITE should be tied
directly to the R/W line of the static memory.
The 8-bit data bus is the main path for transfer of
information between the MK 3850 CPU and other
devices in the F8 microprocessor system.
CPU READ is a control signal that signifies that data
is to be read out 6f a memory location. CPU READ
and an externally generated address page select signal
can be gated together to form a signal to enable the
output of the memory array onto the F8 data bus.
REGDR is both an input and an output that is used
to gate the program counter PO, data counter (DC).
ADDRESSABLE I/O PORTS
Every MK 3853 SMI has four, 8-bit I/O ports. Two
of the I/O ports are used to store a proQrammable
interrupt vector address. A third I/O port IS assigned
to a programmable timer while a fourth port is the
Interrupt Control Port.
505
ROMC STATES
ROMC
(Hexadecimal)
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Definitions
DB PO
DC -
OPERATION PERFORMED
. DB + ((PO)) ; PO.PO +1
DB + ((PO)) ; PO.PO +DB
DB +-((DC)); DC+DC+1
DB+-((PO)) ;PO+-P0+1
PO .... p
((DC))"" DB ; DC .. DC+1
DB+DCU
DB+-PU
p ....PO ; DB+-H'OO'; POL, POH+ DB
DB+DCL
DC+DC+DB
DB+PL
DB+((PO)) ; DCL.-.DB
P+P0+1
DB.-.((PO)) ; DCL.-.DB
P+PO; DB+IAL; POL_DB
FREEZE INTERRUPT STATUS
DB+((PO)) ; DCU-DB
POL-DB; P-PO
DB+-IAU; POU-DB
POU+-DB
PU .... DB
DCU+-DB
POL .... DB
PL+-DB
DCL+-DB
((pp))+-DB or ((p))+-DB
DB+-( pp)) or DB+((p))
NO OPERATION
DC ~DC1
DB+-POL
DB+POU
Data Bus
Program Counter
Data Counter
DC1 - Aux Data Counter
p.
Stack Register
pp
Two hex digits (long I/O port address)
p
One hex digit (short I/O port address)
IA
L
U
()
+-
?
COMMENT
OP CODE, FETCH
BRANCH OFFSET FETCH
IMMEDIATE OPERAND FETCH
EXTERNAL RESET
LOWER BYTE OF ADDRESS VECTOR
PREVENT ADDRESS VECTOR CONFLICTS
UPPER BYTE OF ADDRESS VECTOR
Interrupt address vector
Lower byte suffix
Upper byte suffix
Contents of
transfer to
exchange
Table 1
T-he four I/O ports of the MK 3853 SMI have the
following port addresses:
Programmable Interrupt Vector
(upper byte) .
H'OD' Programmable Interrupt Vector
(lower byte)
H'OE' Interrupt Control Port
H'OF' Programmable Timer
H'OC'
506
OPERATIONAL DESCRIPTION
CLOCK TIMING
All timing within the MK 3853 SMI is controlled by
and WRITE, which are input from the MK 3850
CPU.
Each
machine .cycle will
contain
either
4 cl.ock periods (short cycle) or 6 clock periods
(long cycle).
The WRITE clock refreshes and updates the MK3853
SMI. A machine cycle begins with the fall of the
WRITE clock and the system control lines become
stable shortly after the start of the cycle.
state by accessing memory and placing the
contents of the addressed memory word on the
8-bit data bus. However, every memory device
will increment the contents of its PO register,
whether or not the PO register contents are
within the memory space of the device.
INSTRUCTION EXECUTION
The MK 385;3 SMI responds to signals which are
output by the MK 3850 CPU in the course of
executing instruction cycles.
Table 1 summarizes the response of the MK 3853
SM I to the ROMC states.
MEMORY ADDRESSING
Those ROMC states which specify a memory access
call for only one memory device to respond to the
memory access operation. However, every memory
device responds to ROMC states that call for modi·
fication of program counter or data counter register
contents. Consider two examples:
1. ROMC state 5 specifies that the data counter
DC re!lister
contents must be incremented.
Every memory device will simultaneously receive
this ROMC state, and will simultaneously increment the contents of its DC register.
2.
ROMC state 0 is the standard instruction fetch.
Only the memory device whose address space
includes the current contents of the program
counter PO re!li~ters will resp.ond to this ROMC
When all memory devices are connected to the 8-bit
data bus of a MK 3850 CPU and are also connected
to the ROMC control lines of the same CPU, the
memory devices simultaneously receive the same
ROMC state signals from the CPU and respond to
ROMC states by identically modifying the contents of memory address registers. Therefore the PO
register on all memory devices contains identical
information. The same holds true for DC and P
reg.isters.
Only the memory device whose address space includes the specified memory address, will respond to
any memory access request. To avoid addressing
conflicts, it is necessary to insure that the following
three conditions exist:
1. Memory devices must receive the ROMC state
signals from one CPU.
2. Memory array decoding must not overlap. (More
than one memory device cannot have the same
memory space).
3. The memory address contained in the specified
register (PO or DC) must be within the memory
space of memory device.
TIMER LOGIC DIAGRAM
CLEARED WHENEVER
TIMER IS,L_OA_O_E_D_ _ _ _ _-
LOAD
TIMER
.....
JAM 8 BITS
PARALLEL
WHEN LOADED
+ 31 PRESCALER
DECODE TIMER STATE
'FE' AS TIMEOUT
r---j---ID
Q
TO
\
-~(
TIMER CLK
D
QI--..T..,3L.._-lD
QI--~lt::!4'---ID
QI--~T.S!5_-IID
C
C
C
Q
T6
D
Q T7
o
C
LSB
C
C
C
~
C
MSB
• T3
{T4
•
Figure 2
L-------~<==].~~U5L..----------------~
507
DATA INPUT TO THE SMI
The worst case timing for the MK 3853 SMI receiving data from the data bus is when the data must
be added to a 16-bitnumber within the SMI's Incrementer Adder. This worst case corresponds to data
coming from the accumulator in the CPU for an
ADC instruction or from a memory device for a BR
instruction. For this worst case, arriving data must
allow sufficient time for 16-bit Adder logic.
THE PROGRAMMABLE TIMER
The MK 3853 SMI has an 8-bit shift register,
addressable as an I/O port, of which may be used as
a programmable timer. Figure 2 illustrates the shift
register logic and the exclusive OR feedback path.
Based on the logic illustrated in Figure 2, binary
values in the range 0 through 254, when loaded into
the timer, are converted into "timer counts", as
shown in Table 2. Table 2 contains the actual (HEX)
value loaded into the timer, and the column/row is
the corresponding decimal number of time intervals
the timer will take to time out. Data cannot be read
out of the programmable timer I/O port.
Either the OUT or OUTS instruction is used to
"timer counts" into the programmable timer.
contents of the programmable timer cannot be
using an IN or INS instruction. The timer will
out after a time interval given by the product:
interrupts are disabled. When the timer is enabled,
an immediate interrupt acknowledge will occur if
the continuous running timer timed out while timer
interrupts were disabled.
If the timer is loaded just prior to enabling timer
interrupts a spurious interrupt request will not exist
when the timer interrupt is enabled.
Figure 3 illu~trates a possible sequence for a timer
which is initially loaded with H'C8' then allowed to
run continuously.
CONVERSION OF TIMER COUNTS
INTO TIMER CONTENTS
o
1
2
3
4
5
6
7
load
The
read
time
9
10
For example, a value of H'C8' loaded into the programmable timer becomes 215 timer counts. The
timer will therefore time out in 3.33 milliseconds,
if the period of clock signal is 500 nanoseconds.
12
13
14
15
16
17
18
19
(period of clock clock periods or every
3.9525 milliseconds for a 500 nanosecond clock.
Whenever the timer and timer interrupt are being set
to time a new arrival, the timer should be loaded
before enabling the timer interrupt. The act of
loading the timer clears any pending timer interrupts.
When the timer interrupt is enabled, any pending
timer interrupt will be acknowledged and forwarded
to the CPU. Since the timer runs continuously
(unless stopped under program control) enabling
the timer before loading a time count can cause a
spurious interrupt. Time outs of the timer are latched
in the interrupt logic of the SMI, even while timer
508
8
11
20
21
22
23
24
25
o
2
3
7F BF 5F 2F
OE 87 43 A1
OF 07 03 01
EC F6 7B BD
OD 06 83 41
2A 15 8A C5
CF E7 73 B9
65 32 99 CC
05 02 81 40
30 98 4C 26
C4 62 B1 58
5A AD D6 EB
2D 96 4B A5
67 33 19 8C
C3 E1 70 38
F2 79 BC DE
8B 45 A2 51
90 48 24 12
78 3C 9E 4F
A6 53 29 94
A9 D4 EA F5
1B 8D 46 23
B6 DB 6D 36
7E 3F 1F 8F
ED 76 3B 10
EE F7 FB FD
Each timer count -
4
5
6
7
97 CB E5 72
DO E8 F4 7A
00 80 CO 60
5E AF D7 6B
AO 50 A8 54
E2 F1 F8 7C
5C AE 57 2B
66 B3 59 2C
20 10 08 84
13 89 44 22
AC .56 AB ·D5
75 BA DD 6E
D2 E9 74 3A
C6 63 31 18
9C 4E 27 93
EF 77 BB 5D
28 14 OA 85
09 04 82 C1
A7 D3 69 34
4A 25 92 49
FA 7D BE DF
91 C8 64 B2
9B CD E6 F3
47 A3 D1 68
8E C7 E3 71
FE I FF halts timer
15.5 JJS at 2MHz
8
39
3D
BO
35
AA
3E
95
16
C2
11
6A
B7
9D
OC
C9
2E
42
EO
9A
A4
6F
D9
F9
B4
B8
9
1C
1E
D8
1A
55
9F
CA
OB
61
88
B5
5B
CE
86
E4
17
21
FO
4D
52
37
6C
FC
DA
DC
Table 2
INTERRUPT LOGIC ORGANIZATION
The interrupt Control Port has the I/O port address
'OE'H. Data is loaded into this register (I/O port)
using an OUT or OUTS instruction. Data cannot be
read from this port. The contents of the Interrupt
Control Port are interpreted as follows:
CONTENTS OF
INTERRUPT
CONTROL PORT
FUNCTION
B'xxxxxxOO'
Disable all interrupts
B'xxxxxx01 '
Enable external interrupt,
disable timer interrupt
B'xxxxxx10'
Disable all interrupts
B'xxxxxx 11 '
Disable external interrupt
Enable timer interrupt
TIME OUT AND INTERRUPT REQUEST
- 3 . 3 ms--...f.oIf----3.953 m s - - - -..../.----3.953
-
11
A
ms-------I.~I
I--
c
B
c
A
H'C8' loaded into timer.
B
First time out.
C
Second, and subsequent time outs. 0
0
0
D
Interrupt Service Routines being entered by CPU.
11,12,13 - Intervals between time out interrupt request reaching interrupt logic and service routines being entered by CPU.
These time intervals depend on the number of privileged instructions encountered from the time INT REO goes
Figure 3
low. If none are encountered, 34P 4>is the minimum interval (17 /IS for P 4> = 500ns)
In the preceding I/O port contents definitions x represents "don't care" bits.
Depending on the contents of the Interrupt Control
Port, a. M K ;3853 $MI's interrupt control Iqgic can be
accepting timer Interrupts, or external Interrupts,
or neither, but never both.
Figure 4 is a conceptual logic diagram of the SMI's
interrupt logic. Between the EXT INT input or the
time-out input and the output INT REQ, there are
4 flip-flops. EXT INT and the time-out interrupt
input each have 2 synchronizing flip-flops to detect
the active edge.
Each edge detect circuit is followed by its own
INTERRUPT flip-flop which latches the true
condition.
The outputs of the TIMER INTERRUPT flip-flop
and the EXTERNAL INTERRUPT flip-flop are
ORed to set the SERVICE REQUEST flip-flop,
provided that an interrupt from some other device
is not being acknowledged by the CPU.
INT REQ is an open drain signal that is the NAND of
PRI IN and SERVICE REQUEST. The INT REQ
signal of several devices may be tied together so that
anyone can force the line to OV if it is requesting
INTERRUPT LOGIC
INTR
ACI(**:.::....---------~,....
OUTPUT TO ICP
*(lCP BIT OHICP BIT I)
TIME OUT
. - - - - - - - -.... fiiiiIN
SYNC
FF
eLK' 0"
el.K'
INTR
FF
CLKY
WRITE
-...O------+-----+--+------~--
_____________'
(rep'BIT 0)· (ICP BIT I)
'ICP-INTERRUPT CONTROL PORT
" , OURING EVENT G IN FIG 6
Figure 4
509
INTERRUPT flip-flop is cleared whenever the SMI's
interrupt control register is accessed by an output
instruction, or when its external interrupt has been
acknowledged.
interrupt service. An internal pull-up to VI)~ is
provided by the MK 3850 CPU to the INT EQ
input pin.
PRI IN is part of the interrupt priority chain. Each
SM I has a P"RTTf\f input but, it is imBortant to note
that the SMI does not have a PRI 0 T. This means
that the SMI will be the last device in the daisy chain
interrupt rietwork. In a small system where only a
CPU and a SMI are used, thenPRI IN should be
tied low. See Figure 5.
INTERRUPT ACKNOWLEDGE SEQUENCE
Upon receiving an interrupt reguest, whether from an
external source via EXT I NT or from the internal
timer, the SMI and CPU go through an interrupt
sequence which results in the execution of an
interrupt service routine located at the memory
address pointed to by the Interrupt Address Vector.
Figures 6 and 7 illustrate the interrupt sequence for
the two cases. Events occurring in these sequences
are labeled with the letters A through H. Events are
described as follows.
The SERVICE REQUEST flip-flop cannot be set if
another interrupt request is in the process of being
acknowledged anywhere in the system. If an interrupt
request has been latched into the TIMER INTERRUPT flip-flop, or the EXTERNAL INTERRUPT
flip-flop, the SMI logic waits until after the process
of acknowledging the other interrupt before setting
SERVICE REQUEST. This precaution is necessary
to insure that the priority chain is not altered during
acknowledgment. Chaos would result if half of the
interrupt vector came from one device and the
second half from some other device.
EVENT A
The initial interrupt request arrives. The falling edge
of EXT I NT pin identified an external interrupt. The
rising edge of interval timer output indicates a
timeout.
THE SERVICE REQUEST flip-flop is cleared after
an interrupt from the SMI has been acknowledged.
It is also cleared whenever the SMI interrupt control
register is accessed by an output instruction.
EVENT B
The synchronizing flip-flop in the SMI control logic
changes state.
The conditions for setting the TIMER INTERRUPT
flip-flop and the EXTERNAL INTERRUPT flip-flop
differ slightly. External interrupts must be enabled
before the EXTERNAL INTERRUPT flip-flop
can be set by a negative going transition of EXT INT.
However, TIMER INTERRUPT will be set by a timer
TIME OUT independent of Interrupt Control Port
bit 1. This means that the SM I can detect a time out
interrupt that occurred while the external interrupt
was enabled in the SMI.
EVENT C
The timer interrupt, or external interrupt flip-flop
goes true, indicating the local interrupt logic's
acknowledgment of the interrupt. The timer interrupt flip-flop will always respond and save the timeout occurrence, whereas the external interrupt
flip-flop will only be set at this time if the external
interrupt mode is enabled within the local control
logic.
EVENT D
The TIMER INTERRUPT flip-flop is cleared
whenever the SM I's timer is loaded or when its timer
interrupt has been acknowledged. The EXTERNAL
The INT REQ line is pulled low by the SMI, passing
INTERRUPT INTERCONNECTION
CONTROL
J
psu
PRIORITY
~
U
PIO
OUT
IN
PIO
PRIORITY
PRIORITY
MK 3851
MK 3861
J
ROMC" - ROMC4
D
CPU
MK 3850
LINES (5)
OUT
IN
SMI
PRIORITY
MK 3861
OUT
IN
MK 3853
,
1
INTERRUPT REQUEST
BUS
,'-----Figure 5
510
EXTERNAL
INTERRUPT
---'1
LINES - - - -_ _ _ _
the request for servicing on to the CPU. The conditions that must be present for this to occur are:
OF
Put lower byte of interrupt address vector on
data bus
The PRI IN pin must be low.
13
Put upper byte of interrupt address vector on
data bus
00
Fetch instruction from memory (first instruction of interrupt service routine)
The proper enable state must exist in the local
control logic for the type of interrupt (time or
external). The system is not already into Event F due
to servicing some other interrupt.
EVENT G
EVENT E
At this point the CPU begins fetching the first instruction of the interrupt service routine. In the SMI
interrupt logic, the SERVICE REQUEST flip-flop
and the appropriate INTERRUPT REQUEST flipflop are cleared.
The CPU now begins its response to the INT REQ,
line by outputting the unique ROMC state H'10'
inhibiting modification of interrupt priority logic.
This will only occur when the follOWing conditions
are satisfied:
EVENT H
The CPU is executing the last cycle of an instruction
(beginning an instruction fetch).
The CPU begins executing the first instruction of the
interrupt service routine.
The ICB is enabled (lCB = 0).
INTERRUPT ADDRESS VECTOR
The current instruction fetch is not protected (not a
privileged instruction).
During the interrupt acknowledge, the interrupting
SMI provides a 16-bit interrupt address vector. The
CPU causes this vector to be loaded into PO,. so that
program execution can branch to the routine that
handles this particular interrupt. Fifteen bits of the
interrupt vector are programmable from I/O ports
'OC'H and 'DD'H. Bit 7 cannot be programmed. It is
set by the interrupt control logic to 0 if the timer
interrupt is enabled or to a 1 if external interrupt
is enabled. The interrupt vector is of the form:
WWWW, XXXX, OYYY, ZZZZ for timer interrupt and
WWWW, XXXX, 1YYY, ZZZZ for external interrupt
EVENT F
The CPU generates the interrupt acknowledge sequence of ROMC states as follows:
ROMC STATE
10
Inhibit modification of interrupt priority logic.
IC
No function
TIMER INTERRUPT SEQUENCE
~
i I
WRITE
I
I
I
I
I
I
I
TIME OUT
TIMER REQ
TIMER INTR F. F.
fNT REO (TO CPUI
ROMC STATE
(FROM CPU)
Figure 6
LIS
f%i
I
,
IL...
I
F
o
C
B
r r~I------------~A~----G~I------~H~I)
I
I
LIS
n
~I
LIS,.
"
L
L
LI
I
S
- - - - -__
--
--
I
I
I
ss
I
I
l-s~
10
I
Ie
I
OF
I
13
I
I
I
00
511
INTERRUPT SIGNALS TIMING
where W, X, Y and Z are the bits programmed by
I/O ports 'QC'H and 'OD'H.
Timing for sipnals associated with the MK 3853
interrupt logic IS shown in Figure 9.
EXTERNAL INTERRUPT SEQUENCE
A
I
I
I
WRITE
D
C
B
EI
I
I
____________
F
-JA~
______________
I
~
HI '
GI
I
I~L/~.
LIS
r
I
I
I
I
~
I
L
S
L
S
L
I
I
I
I
I
I
~
EXTINT
1- - -
I
I
- --
I
EXT REO
I
.,#{
I
~,
I
I
EXT INTF.F.
INT REQ (TOC PU)
ROMCSTATE
(FROM CPU)
I
10
I
IC
OF
I
13
I
00
Figure 7
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATING (All voltages with respect to VSS)
..
VGG ..................................................... +15V to -0.3V
VDD ...................................................... +7V to -0.3V
All other inputs and outputs .................................... + 7V to -0.3V
Operating temperature, T A (Ambient) ............................. O°C to +70°C
Storage temperature" Ambient (Ceramic) ........................-65°C to +150°C
Storage temperature" Ambient (Plastic) .........................-55°C to +125°C
*Stresses "above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating· conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(O°C"; TA"; 70°C)
I
SYMBOL
I
I
I
I
I
PARAMETER
MIN
TYP
MAX
UNITS
VDD
Supply
4.75
5.0
5.25
Volts
VGG
Voltage
11.4
12.0
12.6
Volts
0
0
0
Volts
VSS
512
TEST CONDITIONS
DC ELECTRICAL CHARACTERISTICS
(O°C';;; TA';;; 70°C) (VDO = +5V ± 5%; VGG = +12V ± 5%; VSS
TYP
MAX
SYMBOL
PARAMETER
MIN
.-.
35
70
VOO Current
100
13
30
IGG Current
IGG
= OV)
UNITS
rnA
rnA
TEST CONDITIONS
f = 2 MHz, Outputs unloaded
f = 2 MHz, Outputs unloaded
DATA BUS (DBO -DB7)
SYMBOL
VIH
VIL
VOH
VOL
IIH
IlL
CI
PARAMETER
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
Capacitance
MAX
MIN
3.5
VOD
.8
VSS
3.9
VOO
.4
VSS
1
-1
10
UNITS
Volts
Volts
Volts
Volts
J,lA
J,lA
pF
TEST CONDITIONS
IOH = -100J,lA
IOL = 1.6mA
VIN = VOO, three-state mode
VIN = VSS, three-state mode
Th ree-state mode
PRIORITY IN (PRIIN), CONTROL LINES (ROMCO-ROMC4) AND CLOCK LINES (
PW1
td 1
td2
PW2
PWS
PWL
td3
td4
td6
tad1
tad2
tcq
tcr2
tW1
tw2
twp
=+ 12V ± 5%; VSS = OV)
MAX
0.5
180
10
P-180
to write + delay
to write - delay
Write Pulse Width
Write Period;
Short
Write Period;
Long
Write to ROMC
Delay
0
0
P-100
300
250
P
Write to DB
Input Delay
Write to DB
Output Delay
Address delay if
PO (Instruction by
immediate data)
Address delay if DC
(Operand fetch)
or WRITE cycle
CPU READ - Delay
CPU READ + Delay
RAI'iil WRITE - Delay
RAM WRITE + Delay
RAM WR ITE Pulse
Width
UNITS TEST COND
4 P
MS
nS
nS
nS
nS
nS
6 P
nS
750
nS
2P+1.0
MS
CL = 100pF
CL = 100pF
2P+100-td2
2P+200
2P+80D-td2
nS
CL = 100pF
50
300
500
nS
CL = 500pF
2P+620-td2
nS
CL = 500pF
450
2P+400-td2
4P+450-td2
5P+300-td2
P
nS
nS
nS
nS
nS
50pF
50pF
500pF
500pF
500pP
500
nS
50pF
2P+500-td2
nS
50pF
2+50-td2
50
250
2P+50-td2
4P+50-td2
5P+50-td2
350
trg1
WRITE to REGDR
-Delay
70
trg2
WRITE to REGDR
+ Delay
2P+80-td2
514
TYP
CLOCK Period
Pulse Width
300
AC ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
TYP
MIN
SYMBOL
WRITE to INT REO
- Delay
WRITE to INT REO
+ Delay
PRI IN to INT REO
- Delay
PRI IN to INT REO
+ Delay
EXT I NT Setup
Time
tq
tr2
tpq
tpr2
tex
NOTES:
MAX
UNITS
430
nS
CL - 100 pF [1]
1.65
p.s
CL = 100 pF [3]
240
nS
CL = 100 pF [2]
1.5
p.s
CL=100pF
nS
400
(PATiN = 0)
TEST CONDITIONS
1.
Assume PRIORITY IN was enabled
2.
SM I has interrupt pending before PR lOR ITY I N is enabled.
in previous F8 cycle before interrupt is detected in the SMI.
3.
Assume pin tied to
i'NTR'Eci input of 3850 cpu.
TIMING DIAGRAM
WRITE
ROMC
ADDRESS
STABLE
STABLE
STABLE
1+-------- IA02-------+I
CPU READ
RAM WRITE
REGDR
Figure 8
515
TIMING DIAGRAM
WRITE
STABLE
ROMC
INT REQ
::=i
INT REQ
~--------------+------------
-----c'''~
Figure 9
TIMING DIAGRAM
~----------------------PWs------------------------~
WRITE
ADDRESS
STABLE
DATA BUS
INPUT
DATA STABLE FROM RAM
~-----t_CR_2~~~~~~;>~____________________________________
CPU READ
MK 3853 SMI TIMING SIGNALS OUTPUT DURING A SHORT CYCLE
MEMORY READ USING PO
Figure 10
*NOTE: This is the time at which the CPU will strobe data in from the memory.
CPU data sheet for further information.
516
(<1>=
2 MHz) Refer to MK3850
TIMING DIAGRAM
~-------------------------PWL
__________________________
~
WRITE
ADDRESS
STABLE
DATA BUS
INPUT
DATA STABLE FROM RAM
~------t_cR_2~~~~~~~~~~-------------------------------------
CPU READ
MK 3853 SMI TIMING SIGNALS OUTPUT DURING A LONG CYCLE MEMORY READ,
WITH ADDRESS OUT OF PROGRAM COUNTER
Figure 11
TIMING DIAGRAM
~-------------------------PWL--------------------------~
WRITE
t-------- tAD2 ------~
STABLE
ADDRESS
DATA BUS
INPUT
DATA STABLE FROM RAM
t-------- t CR2------~
CPU READ
j
MK 3853 SMI TIMING SIGNALS OUTPUT DURING A LONG CYCLE MEMORY READ,
WITH ADDRESS OUT OF DATA COUNTER
Figure 12
*NOTE: This is the time at which the CPU will strobe data in from the memory.
CPU data sheet for further information.
(<1>= 2 MHz) Refer to MK3850
517
TIMING DIAGRAM
WRITE
ADDRESS
STABLE
DATA BUS
OUTPUT
DATA STABLE FROM CPU
RAM WRITE
i------------ t
W2
CPU READ
MK 3853 SMI TIMING SIGNALS OUTPUT DURING A WRITE TO MEMORY
Figure 13
*NOTE: This is the time at which the CPU will output data to memory.
sheet for further information.
(<1>= 2 MHz) Refer to MK3850 CPU data
M K 3853 APPLICATION
Figure 9 shows a typical application for interfacir19
the MK 3853 SMI to static memories. This particular
example shows a memory system using the MK 2708
1K x 8 EPROM and the MK 4102 1K x 1 Static
RAM. Decoding is provided in 1K boundaries for
up to 8K of memory. This should be more than
adequate for most systems. However, if memory
518
expansion is desired, decoders can be added to
provide additional decoding.
The input to the memory array is isolated from the
F8 data bus to avoid capacitive loading of the data
bus and the output of the memory array is buffered
with C/MOS drivers to meet the 3.5 VIH requirement
for the MK 3850 CPU.
MK 3853 APPLICATiON
Boe97
rOSG-DB1
< X8
F8 DATA BUS
I
FROM
F8
CPU
I
eoce7
X8
OBO-OB7
<
DATA OUT 00.07
J4o)Y
I
>
OAT~
--' "-MK3853
SMt
ROMCO~
.----
MK4102
MK270B
ADDRESS AO·A15
AO·A9
ADDRESS
WRITE~
RAM
WRITE
'--",---
740X;-
-
Note'
DATA c l b T A IN
81To
BlTo
81TO·81T1
CPUREAD
~---'--,!
~r--.REGDR
t
OATAIN DO-07
~
REGDR may be left open
when the 3851 PSU artha
3B52 DMI are not used m
<
I~"
tliesystem.
All B
AU C
A13 D
,
,
,
,
,
,
.
~
7430
AO·Ag
=-=J
ADDRESS
IT
---{
/
}._""," ---"."-
M
20aOH
MEMORY MAP
lK
lCOOH
lK
1800H
RECOMMENDED MOSTEK MEMORIES:
Device
Organization
Type
Access
MK 2708
lK x 8
STATIC
EPROM
450nS
MK 4102·1
lK x 1
STATIC RAM
450nS
MK4102-11
lK xl
STATIC RAM
450nS
(Low Powerl
1400H
lK
CODED FOR ADDITIONAL
>- PRDEOM
OR RAM
loaOH
lK
OCOOH
lK
0800H
I------j
MOOH
I------j
lK RAM
lK PROM
OOOOH L-_ _ _ _--'
Figure 14
519
PACKAGE DESCRIPTION
40-lead plastic package
~,
I
+010
.. --L
'.0 -'"
I
[:::::::::::::::::]$:'
21
40
40-lead side-braze ceramic package
I'----
=trt=~:
2.000! 0 2 0 - - - - - - - - . , ' 1
11
lr=======;II~~I~I~m
OM3::/'~1
'\ =~~~nl
'SYMBOLIZATION AREA FOR
IDENTIFICATION OF PIN 1
05TYP4
.
f--
I I
-j
r-
025 TYP
I
04TYP
520
O°C To 70 D C
O°C To 70°C
-40°C To +85°C
-40°C To +85°C
_55° C To +125° C
-55°C To +125°C
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
I
040
1
~I
~,I .010
.0015
ORDERING INFORMATION
MK3853P
MK3853N
MK3853P-10
MK3853N-10
MK3853P-20
MK3853N-20
r-
1010
!'(XlI
MOSTEI{.
Fa MICROCOMPUTER DEVICES
F8 Direct Memory Access MK3854
FEATURES
F8 FAMILY
I/O<=>
0
2 )lsec cycle time
0
Provides strobe for timing peripherals
0
16-bit address
0
12-bit byte count
0
Control registers
I/O<=>
p
E
R
0
Port address selection
I
P
H
E
0
+5V and +12V power supplies
R
0
Low power dissipation-280mW
M
E
I/O<=>
M
o
I/OW
R
y
A
L
S
<
>
GENERAL DESCRIPTION
The MK 3854 Direct Memory Access (DMA) chip
facilitates high speed data transfer between the main
memory of an F8 system and peripherals. This
transfer occurs without suspending normal operation
of the processor, allowing DMA with no reduction
of program execution speed. The MK 3854 DMA is
manufactured using N-channel, Isoplanar MOS
technology. Power dissipation is low, typically less
than 280mW.
I/OW
I/O
W '---__-'
PIN CONNECTIONS
40 ___ DWS
DIRECTION _ _ I
ENABLE _ _ 2
PIN NAME
DESCRIPTION
TYPE
DBO-DB7
Data bus lines
ADDRO-ADDR15
Address lines
<1>, WRITE
Clock lines
Registers load/
read line
Port address
select
Memory idle line
Transfer request
line
Control status
lines
DMA Write slot,
transfer
Output strobe
line
Power lines
Bidirectional
three state
Output
three state
Input
Input
LOAD REG/
READ REG
Pl, P2
MEM IDLE
XFER REQ
ENABLE,
DIRECTION
DWS, XFER
STROBE
VSS, VDD, VGG
XFER _ _ 3
Input
Input
Output
38 _
XFER REQ _ _ 4
LOAD REG
37 ___ MEM IDLE
t
VGG- 5
36_
VOO_6
3 5 _ Vss
ADDR8 ___ 7
34 ___ ADDRO
ADDR9 ___ 8
33 ___ ADDRI
32 ___ ADDR2
ADDRIO ___ 9
ADDRII _ _ 10
Input
39 ___ STROBE
MK 3854
31 ___
ADOR3
ADDRI2 ___ II
30 ___ ADDR4
ADDRI3 ___ 12
29 ___ ADDR5
ADDRI4 ___ 13
28 ___ ADDR6
ADDRI5 ___ 14
27 ___ ADDR7
PI_IS
P2_16
2 6 _ READ REG
25 ___ WRITE
Output
DB7"-- 17
2 4 _ DBO
066..-- 18
2 3 _ DBl
Output
DB5..-- 19
2 2 _ DB2
DB4 ___ 20
2 1 _ 063
Input
521
MK 3854 DMA FUNCTIONAL DIAGRAM
LOAD
REG
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _---,
P1 ~--------------;
P2 ....- - - - - - - - - 1
WRITE ....- - - - - - - - - - 1
I/O PORT
SELECT
APORT
8
8
PORT 0
16-BIT
INCREMENTER
16
ADDRESS
ADDRa
ADDR15
8
PORT 1
1------'
VGG~
VDD~
VSS
•
12-BIT
DECREMENTER
APORT
PORT2
READ
REG
~_ _ _ _ _ _ _--.
r-~-------.XFERREQ
r - - - - - - - C MEM IDLE
.---------c: cp
PORT3
~
r-------J~
_ _ _ _ _ _ _J\ DATA BUS
DBO-DB7
DATA BUS (8)
BUFFERS
8
\r------,/
PORT 3 BIT 4
5
6
DWS
.-----+- XFER
STROBE
DIRECTION
.L-------17J--====!==i=======~__~ENABLE
Figure 1
FUNCTIONAL PIN DESCRIPTION
c):>and WRITE are clocks provided by the MK 3850
CP"U_ c):> is only used in the generation of STROBE_
WRITE is only used for loading I/O ports and data
bus monitoring for I/O match.
READ REG and LOAD REG are control signals
that must be input to the MK 3854 DMA device in
lieu of the five ROMe state signais. Since the
MK 3854 DMA device only responds to ROMC
states 1A and 1B, external logic must generate
READ REG true for ROMC state 18 and LOAD
REG true for ROMC state lA, as follows:
READ
LOAD
522
REG
REG
;
ROMCO-ROMC1-ROMC2-ROMC3-ROMC4
ROMCO-ROMC1-ROMC2-ROMC3-ROMC4
ADDRO through ADDR 15 are the 16 address lines
which address the memory I()cation to be accessed
during the current DMA operation. This memory
address originates in I/O ports 0 and 1 as illustrated
in Figure 1. These lines are in a high impedance
state when no DMA operation is taking place
(XFER = 0).
MEM IDLE is a timing signal input to the MK 3854
DiviA device from the MK 3852 DMI device. This
signal is output high to' identify time slots when
memory is available for DMA access.
XFER REQ is a control signal which must be input
to the MK 3854 DMA device by an external device
which is controlling the DMA transfer rate (I/O
port 3, bit 4 must be set to zero in this case)_ When
low, this signal causes a byte of data to be transferred to or from memory during the next available
DMA time slot. This signal is latched while MEM
IDLE = 1. Changes during a DMA time slot are
therefore ignored.
DMA controller and become bits 2 and 3 of the I/O
port address. This may be illustrated as follows:
7 6 5 4 3 2 1 0
1, 1, 1, 1, I I /xl I
tt
DBO through DB7 are the bidirectional data bus lines
which link the MK 3850 CPU with all other devices
in the F8 system. Note that only data being transferred to or from one of the four MK 3854 I/O
ports uses the data bus pins. Data being transferred
to or from memory under DMA control completely
bypasses the MK 3854 DMA device.
P1 and P2 must be strapped externally to determine
the addresses of the four MK 3854 DMA device I/O
ports as illustrated in the section titled 'I/O ports'.
XFER is a control output which identifies the time
slots when a DMA data transfer is occurring. XFER
is high whenever, MEM IDLE is high and other conditions specify that a DMA data transfer is to occur
during the next available time slot. These conditions are that a DMA transfer is specified either b
bit 4 of I/O port 3 being set to 1, or by XFER RE
being low while DMA has been enabled and the
currently executed instruction is not attempting to
access the DMA device's I/O ports. ENABLE is
provided by I/O port 3 bit 7. DMA data transfers
are inhibited while an instruction is accessing the
I/O ports of the MK 3854 DMA device since these
instructions may be in the process of modifying
the parameters that control the DMA operation.
This inhibit is generated by ANDing the LOAD
REG input with an internal I/O port selected signal.
O
DIRECTION is a control output which reflects the
contents of I/O port 3, bit 6. When high, data is
being written into memory. When low, data is being
read from memory.
ENABLE is a eontrol output which reflects the
contents of I/O port 3, bit 7. When high, DMA
data transfers may occur. When low, DMA is disabled.
DWS is a DMA write slot signal. It is the logical
AND of XFER and DIRECTION, thus it is true
during any DMA write to memory.
STROBE is a DMA transfer signal output that is
used for strobing data and for generating RAM
WRITE. STROBE is high only during the second
occurrence of clock high after MEM IDLE goes
true, provided that XFER is also true.
P2 P1
x
BIT NUMBER
~~~g::;~~::S~LLER
~ THESE
TWO ADDRESS BITS
ARE VARIABLE AND DEFINE
ONE OF FOUR
110 PORTS:
00 SPECIFIES
01 SPECIFIES
10 SPECIFIES
11 SPECIFIES
1/0
1/0
1/0
1/0
PORT a
PORT 1
PORT 2
PORT 3
MK 3854 DMA I/O PORT ADDRESSES
FUNCTION OF
1/0 PORT
FIRST
3854
SECOND
3854
THIRD
3854
FOURTH
3854
Address, L.O. Byte
(PORTal
Fa
F4
Fa
FC
Address, H.O. Byte
(PORT!)
Fl
F5
F9
FD
Count, L.O. Byte
(PORT21
F2
F6
FA
FE
Count, H.O. Four bits.
and Control (PORT31
F3
F7
FB
FF
Table 1
The four I/O ports are not initialized during the
power on reset.
DMA CONTROL LOGIC
This logic provides the control signals required to
implement DMA data transfers.
Figure 2 shows
the detailed logic that generates these control signals.
LOAD REG/READ REG
The LOAD REG and READ REG signal inputs to the
DMA require special mention.
Most F8 support devices have a control unit which
decodes the five ROMC signals output by the
MK 3850 CPU. However, the MK 3854 DMA controller will only respond to ROMC states 1A and 1B,
which are "write to I/O port" and "read from I/O
port" controls, respectively. All other states constitute "No Operations".
Therefore, instead of
having a control unit, external logic is used to decode
these ROMC state signals, creating READ REG in
response to state 1B, and LOAD REG in response
to state 1A.
DEVICE ORGANIZATION
This section describes the operation of the basic
functional elements of the MK 3854 DMA. These
elements are shown on the DMA block diagram ·(fig. 1).
I/O PORTS
The MK 3854 DMA controller has four 8-bit registers
which are addressed as I/O ports.
Since there may be up to four DMA controllers in
anF8 system, 16 I/O port addresses are reserved for
the exclusive use of DMA controllers, as shown in
Table 1.
The four I/O port address used by a DMA are defined
by the two signals (P1 and P2) which are input to the
INCREMENT AND DECREMENT LOGIC
This logic is used to increment the address in ports
o and 1 and to decrement the byte count in ports
2 and 3.
THE DATA AND ADDRESS BUSSES
Note carefully that whereas the address bus is used
to output the address of the memory location wh ich
will be accessed during the next DMA operation,
MK 3854 DMA controller's connection to the data
bus is used only to transfer data between MK 3854
DMA device I/O ports and the CPU. The data bus
is not used to transfer data bytes during a DMA
operation.
523
DMA CONTROL SIGNALS
>---i'- DIRECTION
XFER REQ
......._ - DWS
~---..._"
>---i'- XFER
LOAD REG
APORT*---,..._,
>---i.- STROBE
>----1.-
MEM IDLE
ENABLE
t--------r-----+-----------~
110 PORT 3 BI.:..:T:....7-=----_ _ _......._ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
Figure 2
*AN
1/0 PORT WAS BEING SELECTED
OPERATIONAL DESCRIPTION
The MK 3854 DMA device makes use of time slots
during which the CPU is not accessing memory.
During these time slots, the MK 3854 DMA device
generates data transfer control signals which enable
data to be read out of memory, or to be written into
memory. The MK 3852 DMI device outputs the
MEM IDLE signal to identify time slots available for
DMA access.
In addition to providing data transfer control signals,
the MK 3854 DMA controller outputs the address
of the memory location which is to be accessed.
The four I/O ports of a DMA device must be loaded
with appropriate data to control the DMA operation.
I/O ports are loaded using OUT instructions. The
contents of I/O ports may be read at any time using
IN'instructions.
Before a DMA operation starts the beginning address
,of the memory buffer from which data will be read,
or to which data will be written, must be loaded into
I/O ports 0 and 1. I/O ports 2 and 3 are used to
define the length of the memory buffer which is to
be accessed plus various DMA options and controls,
as illustrated in Figure 3.
With reference to Figure 3, observe that 12 bits are
set aside to define the memory buffer length (byte
count), therefore memory buffers up to 4096 bytes
in length may be written into or read via DMA. A
byte count of 01 transfers one byte; a count of 00
transfers 4096 bytes.
Bit 7 of I/O port 3 may be used at any time to start
or stop DMA operations. During normal initiation
sequence this bit wi!! be zero while !/O ports D, 1
and 2 are loaded with appropriate data. Then in
order to initiate the DMA operations, I/O port 3
will be loaded with a data byte that includes a 1 in
the high order bit. However, in the case of repeated
block transfers, it may only be necessary to reload
port 3, and port 2 will hold zero and the contents
of port 0 and 1 will be the address of the last byte
previously transferred plus 1.
524
The direction of the DMA data transfer is determined by bit 6 of I/O port 3. If this bit is, zero,
data will be read out of memory by the external
device. If this bit is one, data will be written into
memory by the external device.
The rate of DMA data transfer is determined by bit
4 of I/O port 3. If this bit is zero, then the external
device must provide a transfer request (XFER REO)
signal whenever it is ready for a DMA data transfer.
The actual data transfer will then occur during the
next DMA slot, as identified by MEM IDLE high.
The external device controls DMA transfer rate in
this mode. If bit 4 of I/O port 3 is 1, the MK 3854
DMA controller assumes that external logic is ready
for a DMA transfer whenever MEM I DLE high
identifies a DMA slot. In this mode, the F8 system
controls DMA transfer rate.
Each time a DMA data transfer occurs, logic within
the MK 3854 DMA controller that is clocked by
XFER increments the memory address in I/O ports
o and 1 and decrements the byte counter in I/O
ports 2 and 3. If bit 5 of I/O port 3 is zero, then
DMA transfer will automatically halt and clear
bit 7-the enable bit-as soon as the byte counter
is decremented to zero. If bit 5 of I/O port 3 is 1,
however, the byte count is ignored and DMA data
transfer will continue until halted by an OUT instruction setting bit 7 of I/O port 3 to zero. If
continuous DMA data transfer is specified by bit
5 of I/O port 3 being set to 1, then the memory
address in I/O port 0 and 1 will still be incremented
and the byte counter decremented after each DMA
access even though the byte counter is ignored.
DMA registers are loaded and read when the MK 3850
CPU executes I/O instructions that access the D~,,~.A.
registers; The I/O instructions use the DATA BUS
to ,transmit the I/O address in one instruction cycle
and to transfer data during the following instruction
cycle. The appropriate control signal, LOAD REG
or READ REG, will become active durin\{ this second
cycle. The DMA will load one of its registers during
a cycle with LOAD REG high if the I/O address,
which had been on the data bus during the previous
will drive the contents of a selected register onto the
DATA BUS only while READ REG is high if there
was a similar address match dUring the prior cycle.
I/O address assignment is made using pins P1 and P2.
cycle, matched a DMA port address. The register is
loaded and the address comparator is up·dated by
the WR ITE clock. These are the only functions of
WRITE in the MK 3854 DMA. Likewise a DMA chip
USE OF PORT 2 AND PORT 3 AS DMA CONTROLS
I/O PORT3
7
I
654
I
I
I
3
I/O PORT 2
2
IMSBI
1
I
0
I
o
65432
BIT NUMBER
ILSB I
I
BUFFER LENGTH
(BYTE COUNT)
' - - - 0 - EXTERNAL DEVICE CONTROLS DATA TRANSFER RATE
1 - A BYTE OF DATA WILL BE TRANSFERRED EVERY AVAILABLE DMA SLOT
' - - - - - 0 - DATA TRANSFER HALTS WHEN THE BYTE COUNT REGISTER DECREMENTS
TOO
1 - DATA TRANSFER CONTINUES UNTIL BIT 7 IS RESET TO 0 UNDER PROGRAM
CONTROL
' - - - - - - - 0 - DATA IS TRANSFERRED FROM MEMORY TO AN EXTERNAL DEVICE
1 - DATA IS TRANSFERRED FROM AN EXTERNAL DEVICE TO MEMORY
~------
Figure 3
0 - HALTDMAOPERATION
1 - ENABLE DMA OPERATION
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Above which useful life may be impaired)
VGG ........................................................... +15V to -O.3V
VDD ..............................................................+7 to -O.3V
All other Inputs and Outputs ......................................... +7V to -O.3V
Storage Temperature .............................................. -55°C to + 150°C
Operating Temperature ............................................... O'C to + 7acC
Note: All voltages with respect to VSS.
DC CHARACTERISTICS: VSS
SUPPLY CURRENTS
SYMBOL
PARAMETER
100
IGG
VOO Current
VGG Current
= OV, VDD = +5V±5%, VGG = +12V± 5%, TA = 0 to + 70°C
MIN
TYP
MAX
20
15
40
28
UNITS
TEST CONDITIONS
mA
mA
f = 2M Hz, Outputs Unloaded
f = 2M Hz, Outputs Unloaded
DC SIGNAL CHARACTERISTICS
SIGNAL
DATA BUS (OBO-OB7)
ADDRESS LINES
(AOORO-AOOR15)
ENABLE, DIRECTION
Table 2
SYMBOL
PARAMETER
MIN
MAX
UNITS
Volts
TEST CONDITIONS
VIH
Input High Voltage
3.5
VOO
Vll
Input low Voltage
VSS
0.8
Volts
VOH
Output High Voltage
3.9
VOO
Volts
VOL
Output low Voltage
VSS
0.4
Volts
IIH
Input High Current
1
J.IA
VIN = 6V, three-state mode
III
Input low Current
-1
MA
VIN = VSS three-state mode
VOH
Output High Voltage
3.9
VOO
Volts
IOH = -1 mA
VOL
Output low Voltage
VSS
0.4
Volts
IOl = 3.2 mA
Il
leakage Current
VOH
Output High Voltage
1
3.9
VOO
J.IA
Volts
IOH = -100MA
IOl = 1.6mA
VIN = 6V, three-state mode
IOH = -100MA
(continued)
525
(Table 2 continued)
SIGNAL
SYMBOL
DWS (DMA WRITE
VOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
Output Low Voltage
VSS
0.4
Volts
IOL
~
1.6 mA
1
VIN
~
6V
VIN
~
6V
VIN
~
6V
VIN
~
6V
SLOT), XFER, STROBE
MEM IDLE, XFER REO
IL
Leakage Current
VIH
Input High Voltage
3.5
VDD
/1 A
Volts
VIL
Input Low Voltage
VSS
0.8
Volts
1
IL
Leakage Current
LOAD REG, READ
VIH
Input High Voltage
3.5
VDD
/1 A
Volts
REG, Pl, P2
VIL
Input Low Voltage
VSS
0.8
Volts
IL
Leakage Current
VIH
Input High Voltage
VIL
Input Low Voltage
IL
Leakage Current
WRITE,
1
/1A
3.5
VDD
Volts
VSS
0.8
Volts
1
/1A
Table 2
NOTE: Positive current is defined.as conventional current flowing into the pin referenced.
AC CHARACTERISTICS
MAX
UNITS
NOTES
.5
10
/1s
Note 1
Pulse Width
180
P -180
ns
tr, tf
td1
to WRITE +Delay
0
250
ns
Note 1
td2
to WRITEtDelay
0
200
ns
Note 1
PW2
WRITE Pulse Width
t1
WRITEho CYCLE REO
t2
SYMBOL
PARAMETER
MIN
P
Clock Period
PWl
TYP
~
~
P <1>-100
P
ns
t r , tf
P +100-1d2
p +300-td2
ns
Note 4
WRITdto ENABLE & DIRECTI0Nt
450
ns
t3
MEMIDLEtWENABLE~
400
ns
14
XFER REO ho MEM IDLE+Set-up
+
200
50ns typical
50ns typical
ns
t5
MEM IDLE+to ADDR Valid
50
300
ns
CL
~
500 pF
t6
MEM IDLEtto ADDR Hi-Z
30
250
ns
CL
~
500 pF
t7
MEM IDLEt to XFER & DWSt
50
300
ns
CL
~
50 pF
t8
MEM IDLE to XFER & DWSt
50
300
ns
CL
~
50 pF
t9
MEM IDLEttoSTROBEt
600
3P + 100
ns
CL
~
50 pF
tlO
STROBE Pulse Width
200
P + 30
2
ns
CL
~
50 pF
tll
DB Input Set-up Time
300
t12
WRITEho READ/LOAD REGt
600
ns
t13
READ REG +to DB Valid
40
300
ns
CL
~
100 pF
t14
WRITElto MEM IDLq
2P