1979_NEC_Microcomputer_Catalog 1979 NEC Microcomputer Catalog

User Manual: 1979_NEC_Microcomputer_Catalog

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NEe
NEe Microcomputers, Inc.
CONTENTS
1. Numerical Index
2. Memories

II
I
II
II

Index
Selection Guide
Alternate Source Guide

3.

4.

5.
6.
7.

8.

Random Access Memories (RAMs)
Dynamic NMOS
Static NMOS
CMOS
Read Only Memories (ROMs)
Erasable/Reprogrammable
Mask Programmable
Microcomputers
Index
Selection Guide
Alternate Source Guide

II
II

pCOM~4

Microcomputers
pCOM-42
pCOM-43/44/45
pCOM-46

pCOM-8 Microcomputers
Processors
Single Chip Microcomputers
Peripherals
Microcomputer on a Board

II
II

Reference Section
Representatives and Distributors
ROM Ordering Procedure
Quality Assurance Chart

1

:~,

NEe

NEe Microcomputers, Inc.

NUMERICAL INDEX

II
PRODUCT

PAGE

pPD371 ....••..........•.. 247
pPD372 . . . . . . . . . . . . . . . . . .. 255
pPD379 • . . . . . . . . . . . . . . . . . . 263
pPD410 . . . . • . . . . . . . . . . . . ..
51
pPD411 ...•. . . . . . . . . . . . . . .
9
pPD411A . ... . . .. . . . . . ... ..
17
pPD416 . . . . . . . . . . . . . . . . . .. 25
pPD421 . . . . . . . . . • . . . . . . . . . 67
pPD443/6508 . . . . . . . . . . . . . .. 69
pPD444/6514 . . . . • . . . . . . . . .. 78
pPD445L . . . . • . . . . . • . . . . . .. 79
pPD454 .•.......•.....•.. , 85
pPD458 . . . . . . . . . . . . . . . . . .. 91
pPD546 . . . . . • . . . . . . . . . . . . . 139
pPD547 . . . . . . . . . . . . . . . . . . . 141
pPD547L . . . . . . . . . . . • . . . . .. 143
pPD548 . . . . . . . . . . . . . . . . . . . 127
pPD550 . • . . . . . . . . . . . . . . . . . 145
pPD551 .....•......•...... 163
pPD552 .....•.•........... 147
pPD553 .......•.•......... 149
pPD554 . . . . . . . . . . . . . . . . . . . 151
pPD555 .... ; ....•....•..... 129
pPD556 . . . . . . . . • . . . . . . . . . . 159
pPD650 ......•.••.•....... 153
pPD651 . . . . . . . . . • . . . . . . . . . 155
pPD652 ....•.•............ 157
pPD765 . . . . . . . . . . . • . . . . . . . 271
pPD780 . . . . . . . . . . . . . . • . . . . 167
;UPD2101AL .. . . . . . . . . . . . . .. 35
pPD2102AL ...•.......... .. 41
pPD2111AL ..•...•.•.•.. . .. 45
pPD2114L •....•........... 55
pPD2147 ..•.•............. 60
pPD2316E ......•......•... 103
pPD2332 . . . . . . . . . . . . . . . . . . 107

PRODUCT

PAGE

pPD2364 . . . . . . . . . . . . . . . • . . . . 111
pPD2716 .•................•. 99
pPD4104 . . . . . . . . . . . . . . . . . . . . 61
pPD5101 L • . . . . . . . . . . . . . . . . . .. 73
I.lPD8021 ....•....•.......... 211
I.lPD8035 . . . . . . . . . . . . . . . . . . . . 225
I.lPD8039 . . . . . • . . . . . . . . . . . . . . 237
I.lPD8041 . . . . . . . . . . . . . . . . . . . . 217
I.lPD8048 . . . . . . . . . . . . . . . . . . . . 225
pPD8049 . • . . . . . . . . . . . . . . . . . . 237
I.lPD8080AF . . . . . . . . . . . . . . . . . . 183
I.lPD8085A . . . . . . . . . . . . . . . . . . . 197
I.lPD8155 . • . . . . . . . . . . . . . . . . . . 289
pPD8156 . . . . . . . . . . . . . . . . . . . . 289
I.lPB8212 . . . . . . • . . . . . . . . . . . . . 297
I.lPB8214 . . . . . . . . . . . . . . • . . . . . 303
I.lPB8216 . . . . . . . . . . . . . . . . . . . . 309
pPB8224 . . . . . . . . . . . . . • . . . . . . 313
I.lPB8226 . . . . . . . . . . . . . . . . . . . . 309
I.lPB8228 . . . . . . . . . . . . . . . . . . . . 319
I.lPB8238 . • . . . . . . . . . . . . . . . . . . 319
I.lPD8243 . . . . . . . . . . . . . . . . . . . . 325
I.lPD8251 . . . . . . . . . . . . . . . . . . . . 331
I.lPD8251A . . . . . . . . . . . . . . . . . . . 331
I.lPD8253 ......•.... ·········349
I.lPD8255 . . . . . . . . . . . . . . . . . . . . 357
I.lPD8255A-5 . . . . . . . . . . . . . . . . . . 357
I.lPD8257 . . . . . . . . . . . . . . . . . . . . 365
I.lPD8259 . . . . . . . . . . . . . . . . . . . . 373
I.lPD8279-5 . . . . . . . . . . . . . . . . . . . 389
I.lPD8355 . . . . . . . . . . . . . . . . . . . . 399
I.lPD8741 . . . . . . . . . • . . . . . . . . . . 217
I.lPD8748 . . . . . . . . . . . . . . . . . . . . 225
I.lPD8755A . . . . . . • . . . . . . . . . . . . 399
TK-80A
. . . . . . . . . . . . · ......• 405

3

NEe

NEe Microcomputers, Inc.

MEMORY INDEX
RANDOM ACCESS MEMORIES
Dynamic NMOS RAMs
!1PD411 . • • • . • . • . . • . • . . . . . . . • . . . • • . . • . . . . • . . . .
!1P D4 11 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!1PD416. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .

PAGE

9
17
25

Static NMOS RAMs
!1PD21 01 AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!1PD2102AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!1PD2111AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!1PD410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!1PD2114L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
!1PD2147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
!1PD4104 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . .. .
)1PD421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

35
41
45
51
55
60
61
67

CMOS RAMs
!1PD443/6508 . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .
!1PD5101 L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.uPD444/6514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
!1PD445L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69
73
78
79

READ ONLY MEMORIES
Erasable/Reprogrammable ROMs
!1PD454 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!1PD458 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
!1PD2716 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

85
91
99

Mask Programmable ROMs
!1PD2316E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
!1PD2332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!1PD2364 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . .

103
107
111

5

'!\lEe Microcomputers, Inc.
MEMORY SELECTION GUIDE

DEVICE

SUPPLY
VOLTAGES

TECHNOLOGY

DYNAMIC RANDOM ACCESS MEMORIES
pPD411
pPD411-4
MPD411A
pPD416

4K x 1 TS
4K x 1 TS
4K x 1 TS

NMOS
NMOS
NMOS

150 ns
135 ns
200 ns

380 ns
320 ns
400 ns

+12,+5,-5
+15,+5,-5
+12, +5,-5

C

16K x 1 TS

NMOS

120 ns

375 ns

+12, +5, -5

C/D

22
22
16

200 ns
300 ns

200 ns
300 ns

C/D

16

450
450
80
85

450 ns
450 ns
220 ns
180 ns
300 ns

C
C
C

18
20
22
22
18

D
D

22

STATIC RANDOM ACCESS MEMORIES
MPD443/6508
pPD444/6514
pPD445L

1K x 1 TS
1Kx4TS

MPD2114L

1Kx4TS
256 x 4 TS
4K x 1 TS
4K x 1 TS
1Kx4TS

MPD2147
pPD421 (F)

4K x 1 TS
1Kx8TS

MPD5101L
MPD410
MPD4104

CMOS
CMOS
CMOS
CMOS
NMOS
NMOS
NMOS

ns
ns
ns
ns

NMOS

200 ns
55 ns

NMOS

85 ns

+5
+5
+5
+5
+12,+5,-5
+5

55 ns

+5
+5

85 ns

+5

450 ns
450 ns

+5

C/D
D
C
D
D

18
18
22

MASK PROGRAMMED READ ONL Y MEMORIES
MPD2316E
MPD2332

2K x 8 TS
4K x 8 TS

NMOS
NMOS

MPD2364

8K x 8 TS

NMOS

450 ns
450 ns
450 ns

450 ns

+5
+5

C/D
C/D
C/D

24
24

D
D
D

24
24

24

FIELD PROGRAMMABLE READ ONL Y MEMORIES
MPD2716 (F)
MPD454
pPD458

Notes: (F) C D -

6

2K x 8 TS
256 x B TS
1Kx8TS

Future Product
Read Mode
Plastic Package
Hermetic Package

NMOS

450 ns

450 ns

NMOS
NMOS

800 ns
450 ns

800 ns
450 ns

+1>
+12,+5*
+12, +5*

28

NEe

NEe Microcomputers, Inc.
MEMORY ALTERNATE SOURCE GUIDE

I

MANUFACTURER

PART NUMB'ER

DESCRIPTION

NEC REPLACEMENT

AMD

AM2101
AM2101
AM2111
AM9060
AM9101
AM9102
AM9107
AM9111
AM9216

256 x 4 SRAM
1024 xl SRAM
256 x4SRAM
4096 x 1 DRAM
256 x 4 SRAM
1024 xl SRAM
4096 x 1 DRAM
256x 4SRAM
2048 x 8 ROM

JIPD2101AL
JIPD2102AL
JIPD2111AL
JIPD411/JIPD411A
JIPD2101AL
JIPD2102AL
JIPD411/JIPD411A
JIPD2111AL .,
JIPD2316E

EM&MSEMI

4200
4300
4402
810B

4096 xl SRAM
4096 xl SRAM
4096 x lSRAM
1024 x 8S~AM

JIPD41 0
JIPD410
JIPD41 0
MPD421

FAIRCHILD

2101L
2102
3538
F16K

256 x 4 SRAM
1024 xl SRAM
256 x 4SRAM
16384 x 1 DRAM

JIPD2101AL
JIPD2102AL
JIPD2101AL
JIPD416

FUJITSU

MB2114
MB8101
MB8107
MBBlll
MB8116

1024
256
4096
256
16384

IlPD2114L
JIPD2101AL
JIPD411/IlPD411A
JIPD2111AL
JIPD416

7

HARRIS

INTERSIL

INTEL

-

x
x
x
x
x

4SRAM
4SRAM
1 DRAM
4 SRAM
1 DRAM

II

JIPD5101~

HM6501
HM6508
HM6514

256 x 4SRAM
1024 x 1 SRAM
1024 x4SRAM

2616
IM6508A
7101
7111
7114
7116
7280/A
IM7552

2048 x 8 ROM
1024 x lSRAM
256 x 4SRAM
256 x 4 SRAM
1024x 4SRAM
16384 x 1 DRAM
4096 x 1 DRAM
512 xl SRAM

JIPD2316E
JIPD443/6508
IlPD2101AL
JIPD2111AL
JIPD2114L
JIPD416
IlPD411/JIPD411A
JIPD2102AL

256 x 4SRAM
1024x lSRAM
4096 x 1.DRAM
256 x 4SRAM
1024 x 4 SRAM
16384 x 1 DRAM
4096 x 1 SRAM
2048 x 8 ROM
2048 x 8 EPROM
256 x 4SRAM
. 256 x 4 SRAM
1024 xl SRAM
256x 4 SRAM

JIPD2101AL
JIPD2102AL
JIPD411/IlPD411A
IlPD2111AL
IlPD2114L
JIPD416
JIPD2147
JIPD2316E
IlPD2716
JIPD5101L
JIPD2101AL
JIPD2102AL
IlPD2111AL

2101
2102
2107
2111
2114
2117
2147
, 2316E
2716
5101
8101A
8102A
8111A

1

IlPD443/6508
JIPD444/6514

7

NEe

NEe Microcomputers, Inc.
MEMORY ALTERNATE SOURCE GUIDE

I

MANUFACTURER

PART NUMBER

DESCRIPTION

NEC REPLACEMENT

MOSTEK

MK32000
MK34000
MK36000
MK4102
,MK4104
MK4116

4096
2048
8192
1024
4096
16384

x 8 ROM
x 8 ROM
x 8 ROM
x 1 SRAM
x 1 SRAM
x 1 DRAM

IlPD2332
J.lPD2316E
J.lPD2364
J.lPD2102AL
IlPD41 04
J.lPD416

MOTOROLA

MCM2102
MCM2111
MCM6616
MCM68111
MCM68317

1024 x 1 SRAM
256 x 4 SRAM
16384 x 1 DRAM
256 x 4 SRAM
2048 x 8 ROM

J.lPD2102AL
IlPD2111AL
J.lPD416
IlPD2111AL
J.lPD2316E

NATIONAL

MM2101
MM2102A
MM2111
MM5280A
MM5281
MM74C920

256
1024
256
4096
4096
256

x 4 SRAM
x 1 SRAM
x 4 SRAM
x 1 DRAM
x 1 DRAM
x 4 SRAM

J.lPD2101AL
J.lPD2102AL
J.lPD2111AL
J.lPD411/IlPD411 A
J.lPD411/J.lPD411A
IlPD5101 L

SIGNETICS

2101
2102
2111
2316
2601
2611
2680

256 x 4 SRAM
1024 x 1 SRAM
256 x 4 SRAM
2048 x 8 ROM
256 x 4 SRAM
256 x 4 SRAM
4096 x 1 DRAM

J.lPD2101AL
IlPD2102AL
IlPD2111AL
IlPD2316E
J.lPD2101AL
IlPD2111AL
J.lPD411/IlPD411A

T.!.

TMS2101
TMS2102
TMS4033
TMS4034
TMS4039
TMS4042
TMS4044
TMS4060
TMS4116
TMS4732

x 4 SRAM
x 1 SRAM
x 1 SRAM
x 1 SRAM
x 4 SRAM
x 4 SRAM
x 4 SRAM
x 1 DRAM
x 1 DRAM
x 8 ROM

J.lPD2101AL
J.lPD2102AL
J.lPD2102AL
IlPD2102AL
J.lPD2101AL
J.lPD2111AL
J.lPD2114L
J.lPD411/J.lPD411A
J.LPD416
J.lPD2332

8

256
1024
1024
1024
256
256
1024
4096
16384
4096

I

NEe

NEe Mi,crocomputers, Inc.

p.PD411·E
I" PD411
I" PD411·1
,...PD411·2
I"PD411·3
I" PD411·4

I

FULL~r DECODED RANDOM ACCESS MEMORY
DESCRI PTION

The flPD4!11 Family consists of six 4096 words by 1 bit dynamic N-channel MOS
RAMs. Th~,ey are designed for memory applications where very low cost and large bit
storage an~ important design objectives. The flPD411 Family is designed using dynamic
circuitry ~Vhi'ch reduces. the standby power dissipation.
Reading ir,formation from the memory isa non-destructive. Refreshing i§~asHY
accomplished by performing one read cycle on each of the 64 row addresses. Each
row addre"s must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic high ol'a logic low.

FEATUR ES

All of the'~;e products are guaranteed for operation over the 0 to 70°C temperature
range.
Important, features of the flPD411 family are:
• Low Standby Power
• 4096 words x 1 bit Organization
• A single low-capacitance high level clock input with solid±l volt margins.
• Inactive Power/0.3 mW (Typ.)
• Power Supply: +12, +5, -5V
• Easy Svstem Interface
• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple 'Memory Expansion by Chip Select
• Tflree ~~;tate Output and TTL Compatible
• 22 pin .Ceramic Dual-in-Line Package
• Replacement for INTEL'S 2107B, TI'S 4060 and Equivalent Devices.
• 4 Perfa'rmance Ranges:

r---,-

ACCESS TIME

RNV CYCLE

RMWCYCLE

,uPD411-E

350 ns

800 ns

960 ns

1 ms

,uPD411,

300 ns

470 ns

650 ns

2 ms

,uPD411-1

250 ns

470 ns

640'ns

2 ms

200 ns

400 ns

520 ns

2 ms

,uPD411-~,

150 ns

380 ns

470 ns

2 ms

,uPD411-~4

135 ns

320 ns

320 ns

2 ms

t--::::-:-:-:--

~,...

~2'
t--::::-:-:-:--

PIN CONFIGURATION

VBB

REFRESH TIME

PIN NAMES

Ag
AlO

All

AO A11
AO A5 '.

Adqress Inputs

CE

Chip'Enaole

Refresh Addresses

CS

Chip Select

PIN
POUT

Data Input

WE

Write Enable

DOUT

VD[)

Power (+12V)

AO

VCC

Power (+5V)

VSS

Ground

Cs
DIN

fl PD
411

Data Output

Al .

VBB

Power

A2Ql0

NC

No Connection

Vee q~_l_____...

I

).t PD411
FUNCTIONAL DESCRIPTION

CE Chip Enable
A single external clock input is required. All read, write, refresh and read-rTH?dify-write
operations take place when chip enable input is high. When the chip enable i's low, the
memory is in the low power standby mode. No read/write operations can ta:ke place
because the chip is automatically p r e c h a r g i n g . ;
CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. '!The data
input and data output terminals are enabled when chip select is low. The ch ;ip select
input must be low on or before the rising edge of the chip enable and can bei driven
from standard TTL circuits. A register for the chip select input is provided Ci'n the chip
to reduce overhead and simplify system design.
'
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The ',WE
terminal can be driven from standard TTL circuits. The data input is disable!d when the
read mode is selected.
'.
.
AO-A11 Addresses
All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers al'e provided on the chip to reduce overhead and simplify system design.
DIN Data Input
Data is written during a write or read-modify-write cycle while the chip enable is high.
The data in terminal can be driven from standard TiL circuits. There is no register on
the data in terminal.
DOUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high-impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from d,;lta in.
Refresh
Refresh must be performed every two milliseconds by cycling through the 6A addresses
of the lower-order-address inputs AO through A5 or by addressing every 10\1'.1 within any
2*-millisecond period. Addressing any row refreshes all 64 bits in that row.
The chip does not need to be selected during the refresh. If the chip is refre,;hed during
a write mode, the chip select must be high.
*!'PD411-E = 1 millisecond refresh period,

AO
A1
A2
A3

ROW
DECODE
A.ND

-oVDiD
- 0 VC'C

MEMORY
ARRAY
64 X 64

64

A4

-<>

A5

CE
DIN
WE
CS

b
DOUT

10

A6

AS
A7

VSS

-<> VBB

A10
Ag
A11

BLOCK DIAGRAM

JL PD411
ABSOLUTE MAXIMUM
RATINGS*

MPD411·4

MPD411 FAMILY
(EXCEPT 411·41

CD

Note:

. +1O oe to +55°e
. . . -55°C to +150oe
- 0.3 to +25 Volts CD
-0.3 to +25 Volts' CD
- 0.3 to +25 Volts CD
-0.3 to +25 Volts CD
. . . . . . . . . . 1.5W

. . . oOeto+70oe
-55°C to +150 oe
-0.3 to +20 Volts
-0.3 to +20 Volts
- 0.3 to +20 Volts
-0.3 to +20 Volts
. . . . . . . . 1.0W

Operating Temperature.
Storage Temperature
All Output Voltages ..
All Input Voltages . . .
Supply Voltage VDD ..
Supply Voltage Vee
Power Dissipation . . .
Relative to VBB

COMMENT: Stress above those listed ·under "Absolute Maximum Ratings" may cause per:manent
damage to the device. This is a str'ess rating only and functional operation of the device at these or
any other conditions'above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*ta

DC CHARACTERISTICS

Ta

=
=

25°C

oOe

to 70"C, VOD =

Except VOO

=

+15V

,5V

r12V '5°0, Vee
fOI

VBB

VSS~OV,

5V

411-4.

LIMITS
SYMBOL

PARAMETER

MIN

TYP

CD

TEST CONDITI.oNS

UNJT
MAX

Input Load Current

'll

001

10

gA

VIN

CE Input Load Current

'LC

0.Q1

10

gA

V,N

II

VIL MIN to VIH MAX
VILC MIN to VIHC MAX

f--- -

Output LeakcJge Current
lor High Impedance State

~

0.01

ILO

' 10

gA

CE

=

VILe orCS '- VIH

Vo

=

OV 10 5.25V

VOO Supply Current
rJurlng CE off

100 OFF

20

100 ON.

35'

VDO Supply Current
dUring CE on

gA

CE"

60'

mA

eE

200

Average VOO Current

VIHC. To

=

=

To

1,OV to 0.6V

~

25 'c

25'C

100 AV

29

60

mA

Cycle Time

=

800 ns

!-(P0411

100 AV

37

60

mA

Cycle Time

=

470 ns

!-(P0411-1

loOAV

37

60

mA

Cycle Time

=

470

n5

!--,P041 1-2

IOo'AV

37

60

mA

Cycle Time

~

400

n5

!-(PD411·3

100 AV

41

65

mA

Cycle Time

=

380 ns

100 AV

55

80

mA

Cycle Time

=

320 n,

100

gA

10

gA

CE

V

10L

=

IOH

=

!--,P0411-E

!--,PD411A
V9S Supply Current
VCC

Su~ply

Q)

'BB

Current

dUring CE ofl

0.01

ICCOFF

@

Input Low Voltage

VIL

Input High Voltage

V,H

1.0
2.4

VILC

1.0

CE Input High Voltage

VIHC

VOD 1

Output Low Voltage

VOL

Output High Voltage

VOH

Note,

CD

Typical values are lor T a

=

VIH

VCC+l
0.6
VDD

VOO+l
0.40

2.4

=

VILc orCS

0.6

@)

CE Input Low Voltage

=

Vee

3_2 mA
2.0 mA

25 'C and nominill power supply voltages.

Q)
@

The ISS current IS the sum of all leakage curreors.

@

3.5V lor I-IPD411·E

®

65mAfor1-lP0411-3

During CE on Vee ,upply current is dependent on 'output loading
Vce is connected to output buffer only

80 mA for /lP0411A

®

41 rnA for !-(PD411-3
55 rnA for /lPD411·4

CAPACITANCE

Ta=O° -70"C
LIMITS
PARAMETER

SYMBOL
MIN

TYP

MAX

UNIT

TEST
CONDITIONS

Address Capacitance, CS

CAD

4

6

pF

VIN = VSS

CE Capacitance

CCE

27

pF

VIN = VSS

Data Output Capacitance

COUT

VOUT = OV

CIN

7
10

pF

DIN and WE Capacitance

18
5
8

pF

VIN = VSS

11

}LPD411
AC CHARACTERISTICS

READ CYCLE
Ta =

aOc to

70°C, VOD '" 12V ± 5%, Vee" 5V

±

5%, VBS

=

-5V

±

5%, Vss

=

OV, unless otnervvise noted,

Except VOO '" +15V ± 5%10r411-4
LIMITS
SYMBOL

PARAMETER

/lPD411-E

~PD411

iJP.D411-'

j.LPD411·2

j.!PD41'-3

j.lPD411·4

MIN MAX

MIN MAX

MIN MAX

MIN MAX

MIN MAX

MIN MAX

Time Between Refresh

tREF

Address to CE Set Up Time

tAC

0

0

1

2

2

2

2

2

0

0

0

0
100

UNIT

m<

"'
"'
"'
"'

Address Hold Time

tAH

150

150

150

150

150

CE Off Time

tcc

380

130

170

130

130

CE Transition Time

tT

0

40

0

40

0

40

0

40

0

40

0

40

CE Off to Output High
Impedance State

tCF

0

130

0

130

0

130

0

130

0

130

0

130

Cycle Time

tCY

800

CE on Time

tCE

380

CE Output Delay

tco

330

280

230

180

130

115

Access Time

lACe

350

300

250

200

150

135

CE to WE

'WL

40

40'

40

40

40

40

n<

WEtoCEon

twc

0

0

0

0

0

0

n<

470

470
3000

300

3000

400

260

3000

230

80

380
3000

210

320
3000

200

3000

"'
"'
"'
"'
n<

WRITE CYCLE
Ta '"

aOc to

70"e, VOO

Except VOO - +15V

+

= 12V ± 5%,

Vee

=

5V ± 5%, VSS

=

-5V

±

5%, VSS"

av, unless otherwise noted,

5% for 411 4

".

LIMITS
PARAMETER

SYMBOL

iJPD41'-E

,uPD411

MIN MAX

MI~

800

470

MAX

iJPD41H

/-'PD41'-2

,uPD411-3

/-lPD411-4

MIN MAX

MIN MAX

MIN MAX

MIN MAX

470

400

380

320

UNIT

n<
m,

Cycle Time

tCY

Time Between Refresh

tREF

Address to CE Set Up Time

tAC

0

0

0

0

0

0

Address Hold Time

tAH

150

150

150

150

150

100

CE Off Time

tcc

380

130

170

130

130

80

CE Transition Time

tT

0

40

0

40

0

40

0

40

0

40

0

40

CE Off to Output High
Impedance State

tCF

0

130

0

130

0

130

0

130

0

130

0

130

n<

CE on Time

tCE

380

3000

300

3000

260

3000

230

3000

210

3000

200

3000

n<

WE to CE off

tw

200

180

180

15d

150

65

n<

CE to WE

tcw

380

300

260

230

210

200

n<

DIN to WE Set UpG)

tDW

0

0

0

0

0

0

n<

DIN Hold Time

tDH

40

40

40

40

40

40

n<

WE Pulse Width

twp

200

180

180

150

100

65

n<

Note:

CD

1

2

2

2

2

2

"'

n,

"'

n<

If WE is low before CE goes high then DIN must be valid when CE goes high.

READ-MODIFY-WRITE CYCLE
Ta = oOe to-70°C, VDO = 12V :!: 5%, Vee
Except VOO = +15V:!: 5% for 411·4

= 5V

f

5%, VBB

= -5V

:!: 5%, VSS

= OV,

unless otherwise noted,

LIMITS
PARAMETER

SYMBOL

/lPD411-E

-",PD411

-",PD411-1

-",PD411-2

-",PD411·3

j.tPD411-4

MIN MAX

MIN MAX

MIN MAX

MIN MAX

MIN MAX

MIN MAX

960

650

640

520

470

320

Read-ModifY-Write
(RMW) Cycle Time

tRWC

Time Between RefresJ:!

tREF

Address to CE Set Up Time

tAC

0

1

2

2

0

0

2

n<
2

2

0

0

0

UNIT

m,
m

Address Hold Time

tAH

150

150

150

150

150

100

n<

CE Off Time

tcc

380

130

170

130

130

80

CE Transition Time

tT

0

40

0

40

0

40

0

40

0

40

0

40

"'n<

CE Off to Output High
Impedance State

tCF

0

130

0

130

0

130

0

130

0

130

0

130

n<

CE Width DUring RMW

tCRW

540

3000

480

3000

430

3000

350

3000

300

3000

200

3000

n<

WE to CE on

twc

WE to CE off

0

0

0

0

0

0

n<

tw

200

180

180

150

150

65

n<

WE Pulse Width

twp

200

180

180

150

100

65

n<

DIN to WE Set Up

tDW

0

0

0

0

0

0

n<

DIN Hold Time

tDH

40

40

40

40

40

40

CE to Output Display

tco

330

280

230

180

130

115

Access Time

tACC

350

300

250

200

150

135

12

n<
n<
n,

JLPD411
READ CYCLE

TIMING WAVEFORMS

00

·10

~

V

30

~

_0

,,'1>

I
-

"
.s

V

~

~V

SPEC LIMIT: 3.2mA, DAV

1/-

r-

V OH (V)

VDO - Vas

14

~

l"
-~f
~~

...U

13

,':'

?:
g

~'"

12

>

1000

~~y

-

0

0 ,0
'

t-

GUARANTEED
OPERATING REGION

'= , /

i'-

i'- I"- J
',?",-p

100

~ .......

~

R

~

w

'"

1.

r-......

.......

10

11

.1"C"

,..,."" ~

10

·3

........

·4

·5

SPEC LIMIT: 2 ms

c:.
c:. -

·6

I

'i.

I

I
20

40

60

Ta ('Cl
·8

Vas (V)

Power consumption = V DD x IDDAV + VBB x IBB'

POWER CONSUMPTION

Typical power dissiption for each product is shown below,
mW (TYP.)

CONDITIONS

pPD411.E

350

pPD411

450

pPD411·1

450

pPD411-2

450

pPD411-3

550

= 25° C, tCY = 800ns, tCE = 380ns
Ta = 25° C, tcy = 470ns, tCE = 300ns
Ta = 25° C, \y = 470ns, tCE = 260ns
Ta = 25° C, tcy = 400ns, tCE = 230ns
Ta = 25° C, tcy = 380ns, tCE = 210ns

pPD411-4

660

Ta - 25° C, tCY - 320ns, tCE - 200ns

Ta

See above curves for power dissipation versus cycle time.

14

J'PD411
100

CURRENT WAVEFORMS

200

300

400

500

CEIV)

ICE ImA)

IOOlmA)

40 :

20 r---------~~------------------~~----------~--

IBB ImA)

......=~~.----"""----

0 ,t----...--t-+-f~_,---

t----+--i--"""'----------------+-+-

-20

-40 ' - - _ _ _:>.L._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _' - -__

~,

PACKAGE OUTLINE
IlPD411D

---.j

A

~'I
,i.·~rl~J

J ~_* ~,~~,U.,

T ·:

H

B

:
:•
,

I

:

•

G

M

'
I
!

ITEM

MILLIMETERS

INCHES

A
B

27.43 MAX
1.27 MAX
2.54 + 0.1
0.42 ± 0.1
25.4 ± 0.3
1.5 ± 0.2
3.5 ± 0.3
3.7 ± 0.3
4.2 MAX
5.08 MAX
10.16 ± 0.15
9.1 ± 0.2
0.25 ± 0.05

1.079 MAX
0.05 MAX
0.10
0.016
1.0
0.059
0.138
0.145
0.165 MAX
0.200 MAX
0.400
0.358
0.009

C

0
E
F
G
H

1
J
K
L
M

0

\J

SP411-8-77-GY-CAT ,)

15

II

.' '

NEe
NEe Microcomputers, Inc.

fLPD411A-E
fLPD411A
fLPD411A-1
fLPD411A-2

409681T DYNAMIC RAMS
DESCR IPTION

The J.(PD411A Family consists of four 4096 wordsbY 1 bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The J.(PD411A Family is designed ~sing
dynamic circuitry which 'reduc~s the standby power dissipation.
Reading in'formation from the memory is non-de.structive. Refreshing is easily
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic high or a logic low.
'

FEATURES

• Low Standby Power
• 4096 words x 1 bit Organization

II

• A single low-capacitance high level clock input with solid ±1 volt margins.
•

Inactive Power 0.7 mW (Typ.)

•

Power Supply +12, +5, -5V

•

Easy System Interface

• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple Memory Expansion by Chip Select
• Three State Output and TT L Compatible
•

22 pin Plastic or Cerdip o.ual-in-Line Package

•

Replacement for INTEL's21076, T!.',s 4060 and Equivalent Devices.

• 4 Performance Ranges:

PIN CONFIGURATION

REFRESH TIME

ACCESS TIME

RIWCYCLE

RMW CYCLE

pPD411AE

350 ns

800 ns

960 ns

1 ms

pPD411A

300 ns

470 ns

650 ns

2 ms

.u PD411A·l

250 ns

430 ns

600 os

2 ms

pPD411A2

200 ns

400 os

,520 ns

2ms

Vaa

Vss

Ag

AS

AlO
All

CS
DIN

PIN NAMES
AO' A11

Add ress I n puts

AO·A5

Refresh Addresses

A7

CE

Chip Enable

A6

CS

Chip Select

VDD
CE

DIN

Data Input

NC
As'

Al

A4

A2

.".3

Vce

WE

DOUT

Data Output

WE

Write Enable

VDD

Power (+12V)

Vce

Power (+5V)

VSS

Ground

VBB'

(Pow., -5V)

NC

No Connection

17

fLPD41tA
CE Chip Enable
A single extern'ai clock input is required. All read, write, refresh and read-modify-write
operations take place when chip enable input is high. When the chip enable is low, the
memory is in the low power standby mode. No read/write operations can take place
because the chip is automatically precharging.

FUNCTIONAL DESCRIPTION

CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when·chip select is low. The chip select
input must be low on or before the rising edge of the .chip enable and can be driven
from standarG TTL circuits. A register for the chip select input is provided on the chip
to reduce overhead and simplify system design:
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The' WE
terminal tan be driven from standard TTL circuits. The data input is disabled when the
read mode is selected.
'
AO-A"

Addresses

All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are provided on the chip to'reduce overhead and simplify system design.
DIN Data Input
Data is written during a write or read-modify-write cycle while the chip enable is high.
The data in terminal can be driven from standard TTL circuits. There is no register on
the data in terminal.
DOUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high-impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cycl-ing through the 64 addresses
of the lower-order-address inputs AO through AS or by' addressing every row within any
2* -m ill isecond period. Addressing any row refreshes all 64 bits in ,that row.
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the chip select must be high.
'"PD411A-E = 1 millisecond refresh period.

AO
A,
A2

a:
w

u.
u.
::J
ID

A3

BLOCK DIAGRAM
a:

w
0
0
w
0

u

s:

A4
A5

0

a:

- - - 0 VDD

- - - - . 0 VCC

CELL MATRIX
64 x 64

~Vss
~VBB

TIMING
CE

18

GENERATOR

1/0

p.PD411A
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to +70o e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150o e
Output Voltage CD ............... '.................. +20 to -0.3 Volts
Ali Input Voltages CD .........................•..... +20 to -0.3 Volts
Supply Voltage VDD CD ............................. +20 to -0.3 Volts
Supply Voltage Vee CD ...................... :' ...... +20 to -0.3 Volts
Supply Voltage VsS  (l)

lDW

DIN Hold Time

'OH

40

40

40

40

WE Pulse Width

'WP

200

'80

180

'50

tT" tr '" tf '" 20 ns

CL'" 50 pF

230

Note:(!) If WE is low before CE goes high then DIN must be valid when CE goes high.

READ·MODIFV·WRITE CYCLE
Ta= O°Cto 70o e, VDD '" 12V t 10%, Vec '" 5V ± 10%, Vaa

-;0

5V t 10%, VSS '" OV, unless otherWise noted.

LIMITS
,uPD411A-E
MAX

,uP0411A
. MIN

MAX

,uPD411A-l

',uPD411A-2

MIN

MIN

PARAMETER

SYMBOL

MIN

Read-Modify-Write (RMWI
Cycle Time

tRwe

960

Time Between Refresh

IREF

Address to CE Set Up Time

tAC

Address Hold Time

tAH

150 .

'50

'50

'50

CE Off Time

tec

380

130

130

130

650

MAX

MAX

UNIT

TEST CONDITIONS

520

600

"

T_+_+_40-+_-+_4_0+_+_40+_+_40+_--1 IT'" Ir ~ tf = 20 ns
i-C
",E=-T,-'=-'":::';",tio,-'...:T",;m-='_ _+_t:.:.
CE Off to Output High
Impedance State

130

ICF

130

130

130

CL = 50 pF

i-"'eE"'w="=..
=O="'=;""'-RM-w----1-'-e-Rw---1i--54-0+3-0-00-+-4-BO-+-3-00-0+4-3-0+-3-00-0+-35-0+-300=0j - - - j Load = 'TTL Gate

i-w.-=E::.'O:::e=E-="-='=="----1c--'W=e"-1I--"-1r'-'-=-+-=+-=+=+-=+=+=+---1
~ to CE off

tIN

200

180

180

150

~ Pulse Width

twP

200

180

180

150

DIN to ~ Set Up

tDW

CE to Output Delay

teo

330

280

230

180

Access Time

tACC

350

300

250

200

20

Vref -" 2.0

('If

O.s'Volts

p.PD411A
READ AND REFRESH CYCLE

TIMING WAVEFORMS

CD

r------------------'CV-------------------'CE

CE

ADDRESS CAN CHANGE

----rn
HIGH
IMPEDANCE

UNDEFINED

'Ace __-'--______.1

WRITE CYCLE

I

CE

.

--------+--------~ .k----l------------~--_L--:__=_+- V,H
D,N

--------+---------'1<=---------------+----'t '--"'==-+-- VIL
'C

DOUT'

_ HIGH

VALID OR

HIGH

_~~~~~~4_-U-N-D-EF-'N-E-D--~~--~--~M~OO~I~FI~ED~+-----'~~~~g

READ-MODIFY-WRITE CYCLE
I------------------'RWC:-----------------~__j
tCRW
CE

V,Le

V'H

AO- All

ANO~

__~,~~~+_----~~~--------------------~~--'

-----r---+t-------------,~~~----------~~~/------~-VIH
DIN

D,N CAN CHANGE

-----r---+t-------------~~--~--------~--~~~~~-VIL

1------- 'ACC ------Notes:



11 .. ! I

l -I -

SP~C+T

f-I- t--

'ODAV _. ICY

1.25

I I

NORMALIZED CYCLE TIME
IOL - VOL

50

50

AO

"I"
"-

40

'\.

f- ~ f'<;
20

~ f'\.

10

f-

V

<'

-"

SPEC LIMIT-

""

o~'/V
l~;'.%G V
VA"

30

_0

20

'..['\.

10

~

2ml',2AY

/'

171/

Ih

vv

I

SPEC LIMIT: 3.2mA. D.4V

17·

'"

/

/

I-

VDD - VSS

14

13

b2~Y

1000

I'"

,,~

~w

WQ-ojJ~
R

~

g

I-

!- ~~;R:AT~~~E~EG!ON

I"-

100

V

~~It--..
.......

]

I'--

~

12

/

>

10

~~;;.

V

SPE

.~g; ~ p....-Vj 0 ~ fo

10

1

l1!:tT:

20

.,

·3

f

m~

I
40
Ta (C)

60

POWER CONSUMPTION

Power consumption ~ VDD x IDDAV + VSS x ISS
Typical power dissipation for each product is shown below.

mW (TYP.)

CONDITIONS

/lPD411A-E

300mW

T a ~ 25°C, tcy = 800 ns, tCE = 380 ns

/lPD411A

460mW

T a = 25 e, tcy = 470 ns, lCE = 300 ns

/lPD411A-1

460mW

T a = 25 e, ley = 430 ns, tCE = 260 ns

/lPD411A-2

460mW

T a ~ 25°C, ley = 400 ns, leE = 230 ns

See curve above for power dissipation versus cycle time.

22

CUR RENT WAVEFORMS



5

a

50

100

150

200 .. 250

300

350

.400

450

500

TIME Ins)

100
80

;;C

60

i
0

}]

40
20

a

50

·100

250

.150· 200

,joo

350

4t'lO

450

500

I

TIME Ins)

30

<"
i

20

Ol·

E?

10
0
450

500

-10
-20

;;C

40

i

u

!:?

30
20
.'

10

a

50

. '100 .150

200

2S0

300

350

400

;;C

i

"'w

30

-

450

500

450'

500

TIME Ins)
'''.

20

!:?
10.
250 . .

o.
50

100

150 . 200':

I

350

400

•

TIME Ins)

-10
-20
-30

Note:

-...J

0.:
:;:

I;

//

CYCLE TIME tpc Insl

320
300 250
375

1000

500

400

300

250

200

160

50mA

II

~

..s

IlPD416- 5~

..s

40 rnA

w

w

a:
a:

::J

30 mA

::J 30 mA

>-

"",'

I

20 mA

M

0
0

X

«
:;:

"","

SPEC LIMIT

...J
0..
0..
If)

SPEC LIMIT

()

()

::J

40mA

~
a:
a:

fZ

'0,<,\ , ; /

1>(-. ,"
eQ";; ,\'0'<'\ "'"

"'"

,..

.,.o 20 mA

If)

'f,C

).

:...

o

-

~ 10mA

.' V"

1.---- -\'i~

o

X

" "'"

0

0..
0..

::J

",'1'«;:/ ",'1't/

10 mA

>...J

--- -

o
1.0

2:0

3.0

CYCLE RATE IMHzl ~ 10 3 /tRC Insl

4.0

o

1.0

2.0

3.0

4.0

FIGURE 4
Maxim~m

.

5.0

CYCLE RATE IMHzl ~ 10 3 /tRC Insl

FIGURE 3
Maximum 1003 versus cycle rate for device
operation at extended frequencies.

28

_

IDD4 versus cycle rate for device
operation in page mode.

6.0

JL PD416
AC

Ta '" O°C to +70°C. VDD

= +12V 1:

10%, VCC

= +5V

t 10% Vaa '" -5V:t 10% VSS '"

CHARACTERISTICS

ov

LIMITS
~PD416

SYMBOL

PARAMETER
Random read or write
cycle time

tAe

Read-write cycle time
Page mode cycle time

tpc

Access tione from

MIN

MIN

MAX

J.lPD416-5

MAX

MIN

375

375

320

375

375

320

330

275

225

170

160

tOFF

Transition time
(rise and fait)

o

200

150

120

@®

200

165

135

100

80

®®

80

60

50

40

35

50
150

10,000

250

50
120

10,000

200

32,000

35

35
100

100
150

32,000

120

10,000

RAS hold time

tASH

200

CAS pulse width

tCAS

200

10,000

165

10,000

135

10,000

100

10,000

80

10,000

40

100

35

85

25

65

20

50

15

40

RASto CAS deray
time
CAS to RA'S
precharge time

tCRP

CONDITIONS

250

200
300

TEST

UNIT

MAX

300

50

RAS pulse width

MIN

465

CAS

tAP

.uPD416-3

MAX

410

Output buffer

RAS precharge time

MIN

510

Access time from

turn-off delay

MAX

~PD416-2

575

tRAC

AAS

~PD416-1

165

-20

-20

80

100

135

®

-20

Row address
set-uptime
Row address
hold time
Column address
set-uptime
Column  twcs (mm),
is an early write cycle and the dle with IlPD411 and Other 4K Dynamic RAMs -'

Vss

Vss

As

Ag
A10

A7

An

A6

cs
DIN

VDD
CE

DOUT

(NC)

AO

AS

A1

A4

A2

A3

Vce

WE

Revl2

51

II

.; ~:

"~~OCK DIA~.~;AM
. " i;

MEMORY

ARRAY
64)( 64

CE

DOPT

AO A, A2 A3

A~

A,5

Op.rating Temperature . . . . . • . . . . . . . . . . . . . . . . • • . . . . . . . . 0°0 to +70°0
Storage Temperature· ..... : ...•.. ' ..
_65°C to"1500~
All Output Voltag.,s...•.. , ....•• ,.;, •.. :" ..........•••. '.' . '. -0.3 to :20 Volt 0
All Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . • • . • . . . .. -0.3 to 20 Volts
Supply Voltage VDD . . . . . . . . . . . . . . . . . . . . . • . . . . . . . " -0.3 to +20 Volts0
Supply Voltage VCC . . . . . . . . . . . . . . . • . . . . . . . . • . . • . .. -0.3 to +20 Volts0
Supply Voltage VSS .... ' •..... ', .:. . . . . . • . . . • .•.• . . • •. -0.3 to +20 Volts0
Power Dissipation. . . . . . . . . . . . . . . . . . . • . . . . . • . . . . . . . . . . . . . .. 1.0VI/

>:-.......... : .. '... :......

':~':

Note:

0

.:'

ABSOLUTE MAXIMUM
RATINGS*

.

R.lative to VBB

COMMENT: Stress above 1;hose,listed under "Absolute. Maximum A~ti-Qgs" may,cause perm~nent

damage:,to the device. This is a stress rating on1Y,and fU"!~tional operat.i~n_of. t~e ~evice at these or
any oth'e~ conditions above those ind'icated in 'the operational sections of tliis "Specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
*Ta=2SoC
Ta =

oDe to 70"C; VOO "" 12V ± 5%; Vee'" 5V ± 5%; Ves = -5V

± 5%;

Vss = OV

LIMITS

PARAMETER

SYMBOL

M'N

MAX

'LI

10

CE Input Leakage Current

'LC

10

"A

Output Leakage Current

'LO

10·

"A

VOO Supply Current

'OOaFF

Input Leakage Current

TEST
CONOITIONS

UN'T

"A

DC .CHARACTER ISTICS

VIN - VI'LMIN to
VIHMAX

.

VIN - VILCM1N to

VIHCMAX
CE '" VIL.,C or
'CScVIH

Vo = OV to 5.25V

200

"A

mA

CE '" ....:1.0V toO.6V

duringCE off
IDOON

20

,uPD410

tODAV

24

,uPD410·1

~~

,uPD410-2

IODAV
IODAV

,uP0410-3

tODAY

VOO Supply Current
duringCE on

Average VOO
Current

,uPD410-5

'BB

Vee Supply Current
during CE off

'CeOFF

Average

Vee Current

45
45
45

IODAV

Ves Supply Current

'CCAV

Input Lovv VOlt~ge

V'L

.

-1.0

Input High Voltage.

V'H

CE Input Low Voltage

VILe

-1.0

CE Input,High,Yoltage

VIHC

VOO-1

Output Low Volttlge

VOL

0

Output High Voltage

VOH

2.4

2.'

mA
mA
mA
mA
mA

100

"A

15

mA

21

mA

Minimum Cycle Time

CE

VILe or

Cs= ~IH

DOUT .. No load

0.6

V

VCC+ 1

V

0.6

V

VOO+1

V

0.4

V

IOL "~.2 rnA

V

IOH

VCC

2.0mA

T. = O°C to 70°C; VDD = 12V ± 5%; VCC = 5V ± 5%; VBB = -5V ± 5%; VSS = OV
LIMITS
PARAMETER
Address Capacitance
CS Capac,itance
·.D IN Capacitance
DOUT Capacitance
WE Capacitance
CE Capacitance

52

SYMBOL
CAD
Ccs
CIN
COUT
OwE
CCE

MIN

TYP

4
4
8
5
8
18

MAX
6
6
10
7
10
27

TEST
UNIT'
CONDITIONS
pF
pF'

VIN = VSS

pF,

VIN =VSS
VIN = VSS

pF
pf
pf

VOUT.-VSS
VIN = VSS
VIN = VSS

CAPACITANCE

fL PD410

Ac

CHARACTERISTICS

Ta

~

O"C to lQu e · VOD

~

12V • 5%- Vee = 5V • 5%-

Ves- 5V' 5%"VSS"OV
:L1MITS

SYMBOL

MIN

410-2

410-1

410
PARAMETER

MAX

MIN

MAX

MIN

410-6

410·3

MAX

MIN

MAX

MIN

MAX

TeST
CONDITIONS

UNIT

READ, WRITE AND READ-MODIFY·WRITE

' 0

Address 10 CE
Set'Up Time

'Ae

0

Address Hold

'AH

90

70

50

50

50

'ee

190

140

90

90

,90

Time
CE OU Time

CE Transition
Ttme

'T

40

40

40

CE off 10 Output

'eF

90

90

90

0,

40

0

40

90

0

90

High Impedance

State

READ

CycleT,me
CE on Time

CE Output

'eY
'e,
teo

440

330

230

2000

170

220
2000

110

2000

220

,,'

110

2000

220

190

140

90

80

200

150

100

90

110

'T - 10 ns

2000

50 pF + ITIL,
Ref = 2.0 or O.SV
Load

Delay

Access
Time

lACe

CE to WE

'WL

WE to CE on

'we

20

20

20

20

80
20

"'

lAce = lAC
+ tco + tr

"'

WRITE
CycleT,me

'eY

CE on T,me

,tCE

230

WE!oCEoff

IW

130

100

eE to WE

'ew
'OW

130

100

DIN to WE

330
2000

170,

220
2000

1>0

220
2000

110

70

IT

220
2060

110

70

70

70

70

20

20

70

70

~

10 ns

2000

I

Set Up
DIN Hold Time

'OH

60

WE Pulse
Width

'WP

130

100

70

READ·MODIFY-WRITE

280

280

tRwe

560

CE Width
DurmgAMW

tCRW

350

WE to CE on

'we
'w

130

100

70

70

70

twp

130

100

70

70

70

Read-Mod,fy·

420

280

'T

10 ns

Wnte (RMW}
Cycle Time

WE to CE off

WE Pulse
W,dth

2000

260

170

2000

2000

170

2000

PO

2000

DIN loWE
Set Up

'ow

DIN HOld
Time

'OH

CE to Output
Delav

'eo

190

140

90

80

70

Load - 50 pF + ITTL.
ReI = 2.0 Or a.BV

Al:l:ess Time

IACC

200

150

100

90

80

IACC - lAC
+ tco + IT

PACKAGE OUTLINE
J,lPD410D

20

20

60

20

A

-ilD

M

-I c lE
ITEM

MILLIMETERS

INCHES

A

27.43 Max.
1.27 Max,
2,54 + 0.1
0.42 ± 0.1
25.4 ± 0.3
1.5 + 0.2
3.5 ± 0.3
3.7 ± 0.3
4.2 Max.
5.08 Max.
10.16+0.15
9,1 + 0.2
0.25±0.05

1,079 Max.
0.05 Max,
0,10
0,016
1,0
0.059
0,138
0.145
0.165 Max.
0.200 Max.
0.400
0.358
0.009

B

C
0
E
F

G
H

I
J
K
L

M

53

fLPD410
TIMING WAVEFORMS

READ CYCLE
CE

ADDRESS
ANDCs

DOUT

WRITE CYCLE
VtHC
CE

ADDRESS

AND

CS

VIL

-----_+\~~~~---_+~~~~~-~~----- VIH

- - - - _ t ' ~------+_--,..

\----+--- V,L
VOH

l----VOL

READ·MODIFY·WRITE CYCLE

CE

ADDRESS
ANDCs

WE

DIN CAN CHANGE

IMPEDANCE

.....

---i:2=-t-AC--.....J~ ---+--+
Notes:
CD VOO - 2V is the reference level fOr measuring timing of CE,
(2)

VSS + 2V is the reference level for measuring timing of CEo

@

VfHM1N is the reference level for measuring timing of the addresses,

- - VOL

CS, WE and DIN.

®

VILMAX is the reference level for.measuring timing of the addresses,

C$, WE and DIN.
@

VSS + 2.0V is the reference level for measuring timing of DOUT.

@

V,SS + O.SV is the reference level for measuring timing of DOUT.

(j)

WE must be at VIH until eOnd of tcO.

SP41 O·g· 78·G Y·CA T

54

NEe
jLPD2114L
jLPD2114L·1
p.PD2114L·2
jLPD2114L·3
jLPD2114L·S

NEe Microcomputers, Inc.

4096 BIT (1024 x 4 BITS) STATIC RAM
DESCRIPTION

The NEC .uPD2114L is a 4096 bit static Random Access Memory organized as 1024
words by 4 bits using N-channel Silicon-gate MOS technology_ It uses fully DC stable
(static) circuitry throughout, in both the array and the decoding, and therefore requires
no clocks or refreshing to operate and simplify system design_ The data is read out
nondestructively and has the same polarity as the input data. Common input/output
pins are provided.
The .uPD2114L is designed for memory applications where high performance, low cost,
large bit storage, and simple interfacing are important design objectives. The .uPD2114L
is placed in an 18-pin package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
A separate Chip Select (CS) lead allows easy selection of an individual package whim
outputs are OR-Tied.

F EATU RES

• Access Time: Selection from 150-450 ns
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Single +5 Volt Supply
Directly TTL Compatible - All Inputs and Outputs
CompletelyStatic - No Clock or Timing Strobe Required
Low Operating Power - Typically 0.06 mW/Bit
Identical Cycle and Access Times
Common Data Input and Output using Three-State Output
High Density 18-pin Plastic and Ceramic Packages
Replacement for 2114L and Equivalent Devices

AS

PIN NAMES

Vee

A5

A7

AO·Ag

Address Inputs

A4

AS

WE

Write Enable

A3

Ag

Ao

1(0,

A,

1(02

A2

CS
GND

1(03

es

Ctiip Select

110,-1(04

'Data Input/Output

(+5Vi

Vee

Power

GND

Ground

.

1(04

iiVE

Rev/l
55

II

fLPP2114L

BLOCK DIAGRAM
_----<@vcc
_----<(VGNO

r

MEMORY ARRAY
64 ROWS
64 COLLi.r'.~NS

ROW
SELECTOR

A.

1

A7 17
AS 16

1'0, 14

SENSEswnCH

tl02 13
DATA
CONTROL

1103 12
1/04 11

. . -100 e to +80°C
. -65°eto+150oe
-0.5 to +7 Volts 70'C Vee' +5V' 10% ool',"olhocwi" oo"d
LIMITS

PARAMETER

SYI\180L

I

2114L

I

2114L·'

~MIN I MAX

MIN

,

I

2114L-3

I

2114L-5

'RC

Access Time

'A

450

300

'CO

120

10'0

450

300

Chip Selection

250

200

150

to Output Active

20

tc~

CONDIl:IQNS

200

150

",80

70

60

, ".ns

20

20

20

Ir

=

'T

250

,CL

=

,tf =

=

i(}

ns

10q pF

Load"=

Chip Selection

Output

-TEST

[UNIT

READ CYCLE

Read Cy~le, Time

to OutPlit Valid

2114L-2

MAxi MIN I MAX IMINIMAXIMINl MAXL

,:nLgate

Input Levels = 0.8·

20

and 2.0V

3~State

from Deselectlon
Output 'Hold'

100

tOTO

i;om

Address ChanRe

50

'aHA

80

70

50

50

60

50

50

50

"'

Vref " 1.5V

WRITE CYCLE
Write Cycle Time

'we

450

300

250

200

150

'T

Write Time

'w

200

150

120

120

80

eL

=
=

Ir

'1

10 ns

100 pF

Write Release

Load

'WR

Time

Output TState
100

'OTW

fromWr!te

80

70

60

50

=

1 TTL gate

Input" levels - 0.8
and 2.0V

Data to Write
200

'ow

Time Ovedap

150

....

120

120

80

Vref

l.5V

Data Hold from

a

'DH

Write Time

I
I

Address i6 Wr'ne
-tAW

Setup Time

:

TIMING WAVEFORMS

READ CYCLE

CD

tRC

WRITE CYCLE

1 - - - - - - - - - tWC:-----------i

-----+-d~"

~------tw(D-----~

Ir~~~---------

WE

DOUT

Notes:

GJ WE is high for Read Cycle
(?). tw

is measured from the latter of CS or WE going low to
the earlier of CS or WE going high.

57

II

,.,. PD2114l

TYPICAL OPERATING
CHARACTE RISTI.CS
NORMALIZED ACCESS TIMEVS.
AMBIENT TEMPERATURE

NORMALIZED ACCESS TIME VS.
.
SUPPLY VOLTAGE'

..,

"

1.2

r-'"

r-'"

1.1

-

0.9

0.8

4

V

N

:::;

II:

z

,_,I

w

~~

w

N

:::;
<{ 1.0
:;:
0

...

Cl .1.1

Cl

4.5

5

5.5

~ 1.0
II:

o
z

~
0.9

0.8

6

o

f-"""

/

20

V

60

80

Vet (V)

NORMALIZED POWER SUPPLY CURRENT VS.
SUPPLY VOLTAGE

NORMALIZED POWER SUPPLY CURRENT VS.
AMBIENT TEMPERATURE

1.2

1.2

u

u

!:?
Cl

1.1

w

N

:::;
<{

1.0

:;:

~

II:

0

z

0.9

0.8
4

~

~

~

,...

!:?

Cl 1.1
w
N

:::;
<{ 1.0
:;:
II:

o
Z

5

4.5

Vee

5.5'

a.9
0.8

6

~

............

............... ...
o

20

80

(V)

OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE

OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE

15

15

~ 10

~

E

10

E

..J

::r:

52

S?
5

5

0
·0

0.2

0.4
VOL (V)

58

~

0.6

0

4
VOH (V)

/LPD·2114L
. PACKAGE OUTLINES
ILPD2114LC/D

~----------A--------~~

IlPD2114LC (Plastic)
ITEM

. INCHES

MILLlME:TERS

23.2 MAX.

0.91 MAX.

B

1.44

C

2.54
0.45·
20.32
1.2
2.5 MIN.

0.055
0.1
0.02
0;8
0.06

"
D

E
F

G
~

0.1 MIN.
0.02 MIN.
,a.la, MAX.
0.2 MAX.

0.5 MIN.
4.6 MAX.

5.1 MAX;
7.62
6.7
0.25

K
l

M

II

0.3
0.26
0.01

I. ..
,1·· \=,~=I
.. .
LI
1 ~TT5IF"=i1
.
T"
A

.Op::c

H

I
I

T:

I
,

I

':

•

I
I

:

J

~

::

o.J
,

M

IlPD2114LD (Cerdip)
ITEM

Po

MiLLIMETERS

B
C
D

23.2 MAX.
1.44
2.54
0.45

E

20.32

F

1.2
2.5 MIN.
0.5 MIN.
4.6 MAX.
5.1 MAX.
7.62
6.7
0.25

G
H
[

J
K
l

M

INCI:IES

0.91 MAX.
0.055
0.1
0.02
0.8
0.06
0.1 MIN.
0.02 MIN.
0.18 MAX.
0:2 MAX.

0.3
0.26
0.01

SP2114L·ll·78·GY-CAT

59

NEe
NEe Microcomputers, Inc.

4096 X
DESCRI PTION

1 BIT STATIC

RAM

The MPD2l47 is a 4096-bit static Random Access Memory organized as 4096 words by
1 bit using a high,pe'rformance II/IOS techflology, It uses a uniquely innovative design
approach which provides th~ ease-of-use features associated with nonclocked static
memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipatign without the need for
clocks, address setup and hold times, nor reduced data rates due to cycle times that
are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes highdeselecting the MPD2147 - the part automatically reduces its power requirements and
remains i~ this low power standby mode as long as CS remains high. This device feature
results in system power savings as great as 85 percent in larger systems, w.here the
majority of devices are deselected.
The MPD2l47 is placed in an l8-pin package configured with the industry standard
pinout. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V
supply. The data is read out nondestructively and has the same polarity as the input
data. A data input and a separate three-state output are used.

FEATU RES

• Completely Static Memory - No Clock or Timing Strobe Required
•
•
•
•
•
•
•
•

Equal Access and Cycle Times
Single +5V Supply
Automatic Power-Down
Directly. TTL Compatible - All Inputs and Outputs,
Separate Data Input and Output
Three-State Output
Available in Standard l8-Pin Ceramic Package
Three Performance Ranges:
ACCESS TIME '

ACTIVE CURRENT

STANDBY CURRENT
20mA

IlPD2147

85 ns

1S0 mA

IlPD2147-2

70 ns

1S0 mA

20mA

IlPD2147-3

55 ns

180mA

30mA
PIN NAMES

PIN CONFIGURATION

AO

vee"

Al

AS

Arr A

. Address Inputs

1

WE

Write Enable

CS

Chip Select

Data Input

A2

'A7

DIN'

A3

AS

DO'lJT

Data Output

A4

Ag

VCr.

Power (+5vl

A5

A10

DOUT

All

CS

WE

MODE

WE

DIN

H

X

Not Selected

High Z

es

L

L

Write

High Z

Active

L

H

Read

DOUT

Active

Ground

GND

GND

60

TRUTH TABLE
OUTPUT

POWER
Standby

NEe

NEe Microcomputers, Inc.

4096
DESCR IPTION

F EATUR ES

,u.P041 04·30
,u. P 04104·32
,u. P 04104·33
J.L PD41 04·35
,u. P041 04·36

x 1 STATIC NMOS RAM

The ilPD4104 is a high performance 4K static RAM. Organized as 4096 x l,it uses a
combination of static stor CE by more than 1lv\IS then clata ou t may

® tc=tCE+tp+2fT·
® The true level of the outPut in the open Circuit c:ondition will
be determined totally bV OUtput load conditions. The output
is guaranteed to be open circuit within tOFF.

not remain open circuited.

®

Oeterm'ined bV user. Total cvcle time c'arinot exceed tCE

@

STANDBY
CHARACTERISTICS

tRMW" tAC + twpL + tp + 3 tT + tMOO·

LIMiTS

PARAMETER
VCC:l!i StandbY

SYMBOL

4104 30
MAX

IpD

TF

100

Power Supply Rise Time

TR

100

TCE

300

CE Width

,TpPD

"I" Leoral CE Min Level

V'H

Standby Aocwery Time

TRC

Note

0

MAX

2.2

4104-35
MIN MAX

4104-36

MIN

TEST
CONDITIONS

MAX

3.0

3.3

Standby Curren,t
Power Supply Fall'Time
Chip Enable Pulse

MIN

3.0

VPD

Chip .EnatHe Precharge To
Power Down Time

4104·33

MAX

3.3

mA

3.3

100

100

100

100

100'

100

100

>00

85

2.2

2'
500

500

500

MaXimum value for IpO is guaranteed at VPD mln.mum value (~3V)

POWER DOWN

TIMING WAVEFORMS

Vee

63

I

j.i·P'D4104
READ CYCLE

Tll\i1lNGW AVE FO R,I\i1S
(CONT.)

CE

tAS
VlH- rr"J.=-..u.----'":loL"...,,..,..,'77..,.,,~,..,..,...,..,..,.,,..,.,.rr,..,..,..,,,...,.,.rr,..,..,...,..,..,.,,'rrrrr
ADqRESSES '!4IL-

WE

VIH -

Vi~- :..u.J..J....L.LI.4-L.LI.J..J....L.LI.J..J....L.LI.J..J....:..u.J..J....I.4J.J..J....L.LI.J..J....L.LI.J..J....~~L.LI.~L.LI.J../..LU..

1----'----- tAC -.~---~-0>1
VDH~

DOUT

________________

~~

____

VOL -

WRITE CYCLE

W~

VIH VIL -

DIN

VIH VIL-

READ-MODIFY-WRITE CYCLE

________~~--------tRMW------------.1
CE

VIH -"
VIL 1--------tCE--------~

WE

VIH V1L -

V,H DIN

VIL-

tAC-:-t_tMOD_j_ _ _
VOH-

DOUT

64

VOL-

--------OPEN~

VALID

.~

tOFF

)--OPEN-

ILPD4104
OPERATIONAL
DESCRIPTION

READ CYCLE
The selection of one of the possible 4096 bits is made by virtue ofthe 12 address bits
presented at,the inputs. These are latched into the chip by the negative going edge of
chip enable (CE). If the write enable (VilE) input is held at a high level N IHI while the
CE input is clocked to a low level (V1L), a relld oPeration will'.beperformec;l. At the
access time (tAC), valid data will appear a~ the output ,Since th~ output is ~nlaiched
by a positive transition of CE, it will be' in the high impedance state from 'the previous
cycle until the access time. It will go to tl1e high impedance state a'gain at the end of the
current cycle when CE goes high.
The address lines may be set up for the next cycle any time after the address hold time
has been satisfied for t~e current cycle.
WRIT!: CYCLE
Data to be written into a selected cell is latched into the chip by the later negative
transition of CE or WE. If WE is brought low before CE, the cyclE! is an "Early Write"
cycle, and data will be latched byCE.I,f CE is brought low before WE, as in a ReadModify-Write cycle, then data will be hitched by WE.
.

II

If the cycle is an "Early Write" cycle, the output will remain in the high impedance
state. For a R'ead-Modify-Write cycle; the output will be active for the Modify and
Write portions of the memory cycle until CE goes high. If WE is brought low after CE
but before the access time, the state of the output will be undefined. The desired data
will be written into the cell if data-in is valid on the leading edge of WE, tOI H is satisfied
and WE occurs prior to CEgoing high byat least ttje minimum lead time (twpL!.

READ-MODlfY·WRITE
Read and Write cycles can be combined to allow reading of a selected location'and then
modifyIng that data within the same memorytycle. Data is read at th~ acce'~ time and
modified during a perilld defined by the user. New data is written oetween WE iow and
the posi;tive transition of CEo Data o~t will remain valid until the rising edge of CEo A
minimum R-M-W cycle time can be calculated by tRMW = tAC + tMOO + tWPL + tp +
3 tT; where tRMW is the cycle time, tAC is the access ti(Tle, tMOO is the user defined
modify time, twPL is the WE to CE lead time, tp i,s the CE high time, and tT is one
transition time.
POWER DoNN MODE
In power':down, datamay be retained indefinitely by maintaining VCC at+3V.
However, ,prior to Vee going below VCC minimum (":4.5V) CE must be taken high
(VIH = 2.2V) and held for a minimum 'time period tppo and maintained at VIH fot
the entire standby period: After power'is returned to VCC min or above, CE must be
held high. for ,a minimum of tRC in onder that the device may operate properly. See
power down waveforms herein,. Any active cycle in progress prior to power down must
be completed so that tCE min is not violated.

65

p,PD4104
PACKAGE'
/lPD4104C/gUTLINES

SP41 04-113-78-GY-CAT

66

NE'C

NEe Microcomputers, Inc.

ILPD421

~OOa[~~~~illOOW
8K BIT STATIC RAM
DESCR I PTI ON

FEATURES

PIN CONFIGURATION

The NEC JlPD421 is a very high speed 8192 bit static Random Access Memory
organized as 1024 words by 8 bits. Features include a power down mode controlled by
the chip select input for an 80 percent power saving.

• 1024 X 8·Bit Organization
•

Very Fast Access Time: 85/100/150/200 ns

•

Single +5V Power Supply

•

Low Power Standby Mode

•

N·Channel Silicon Gate Process

•

Fully TTL Compatible

•

Six-Device Static Cell

•

Three State Common I/O

•

Compatible with 8108 and Equivalent Devices

•

Available in a 22·Pin Dual·in·Line Package

AS

Vce

A5

A7

A4

AS

A3

Ag

A2

es

A,

WE

AO

I/OS

I/O,

1/07

1/02

I/OS

1/03

1/05

GND

1/04

67

'NEe

NEe Microcomputers, Inc.

JLP0443/6508
JL P 0443/6508· 1

,~rnff[~~~~illrnW

, -,

,I '

'

1024 BIT CMOS RANDOM ACCESSiVlEMQRY

OESCR IPTION

The j.lPD443/6508 is 'a high speed, low'p~w~r, siliconQllte CMOS 1024 bit static RAM
organized as ·1024 words by 1 bit. In all. stati<; state~ this R~~'exhibits the microwatt
'
power requiremetjts typical ,of CMOS.·,· :
:

:

Inputs and three state output are TTLcomi>~tibJe. The~~sic part operates at 4 to 7
volts with a +5V, 25°C access time of,200 ns and supply currept
/lA. Data
retention is.guaranteed to 3V.on all parts.
,.
1

onoo

FEATURES

•
•
•
'.
•

Low Po:wer Operation
Excellent Speed Operation
TTL Compatible on Inputs and Outputs
Static Operation
On·Chip Address Register
~. Replacement for 1M 6508 and Equivalent Devices' ,
• Available in Standard 16 Pin Ceramic Package

I
",'

,",'

0'

;;-.

PIN CONFIGURATION

PIN

Vee
01

WE
Ag
AS

AO·A~

A7'

DO

A6 .

GNb

Address Input

CS

Chip Select

WE

Wri to Enable'

VCC

Powerl+5V)"

01

Data' Input

,DO

,A4

NAMES

Data O"tput

','

~PD443/6508
BLOCK DIAGRAM
.~

CELL ARRAY
32 x 32

DATA
CONTROL
COLUMN DECODE
AND
BUFFER REGISTER

CS

Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to +70oe
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°eto+150oe
Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to Vee +0.5 Volts
Output Voltages ............................... -0.5 to Vee +0.5 Volts
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 Volts

ABSOLUTE MAXI MUM
RATINGS*

COMMI;NT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent,
damage to the device. This is a stress rating only and functional operation of the device at these ()r
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating ~onditions for extended periods may affect devi~e
reliability.

*Ta = 25°C
Ta

= oOe.o +700 e: Vee = +5V ± 5%

DC CHARACTERISTICS
~

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

1 UNIT
V

Logical "1" Input Voltage

VIH

Logical "0" Input Voltage

VIL

Input Leakage

IlL

Logical "1" Output Voltage

VOH2

Vee-O.01

V

lOUT

Logical "1" Output Voltage

VOHl

2.4

V

10H

Logical "0" Output Voltage

VOL2

Logical "0" Output Voltage

VOL1

Output ,Leakage

10

Supply Current

Ice

Vce- 2.0

-t.O

0.8

V

1.0

/lA

GND+O.Ol

-1.0
1.0

I nput

Cap~citance

Output Capacitence

SYMBOL

MIN

=0
= -0.2 mA

=0
= 2.0 mA

V

lOUT

V

IOL

1·0

/lA

OV <; Vo <; Vce

/lA

VIN - Vee

100

TYP

OV <; V'IN <; Vee

0.45

LIMITS
PARAMETER

70

TEST
CONDITIONS

MAX

UNIT

CIN

5.0

7.0

pF

COUT

6.0

10.0

pF

TEST
CONDITIONS

CAPACITANCE

fLP 0443/6508
AC CHARACTERISTICS

-

a

LIMITS
PARAMETER
Access Time From CS

Output Enable

~ime

Output Disable Time

es Pulse Width
es Pulse Width

SYMBOL

"P0443/6508-1
MAX
MIN

"P0443/6508
MIN
MAX

UNIT

'AC

250

300

ns

'EN

180

180

n,

180

n,

180

'DIS

tf = 20 ns

'CS

150

165

n,

(Negati~e)

'd

250

300

n,

V,ef = 50%

twp

165

165

n,

Load = 1 Tl L Ga'e

(~egative)

Up Time

'ADDS

7

7

ns

Address Hold Time

'A DOH

90

90

ns

Data Set Up Time

'OS

165

165

Data Hold time

'DH

0

0

TIMING WAVEFORMS

~r =

(Positive)

Write Pulse Width
Address Set

TEST
CONDITIONS

"

CL = 50 pF

ns
ns

READ CYCLE

I

cs
AO-Ag

DATA OUT

Note:

Vee IV)

IOH (mA)

tA - Vee (Ta)
700
LOAD~ 'Tll<'fOPF

600

-

;;

'"

\\

500

' \~

400

.80 C

..........

300

N '..........
~

200

VCC IVI

IOL (rnA)

ICCDR- Ta

700
T111
::
=tt
~ .....
I

r :

H,

TT

: :

,:'

::

:

'G

ITEM

A

D
F
G
H

K

M

M

INCHES

MILLIMETERS
28.0 Max.

1.4 Max.
2.54
0.50' 0:10
25.4

1.10 Max.
0.025 M;:lx.

0.10
O. 2 . 0.004

1.

1.40

0.055

2.54 Mm.

O.10Mm.

O.5Mm,

0.02 Mm.

4.7 Max.
5.2 Max.
10.16
8.5
+0.10

0.25 0.05

O.~Mi.I)(.

a.20Max.

0.40
0.33

O.Oll~:~

SP6.101 L-B-77-GY-CAT

n

NEC

NEe Microcomputers, Inc.

. lL PI;)444/6514

~rn~[~~~~illrnW
1K X 4 BIT STATIC CMOS RAM
OESCRI PTION

FEATURES

The NEC pPD444/6514 is a 4096 bit Random Access Memory fabricated using the
NEC CMOS process. This yields devices with low operating power and standby currents
of exceptionally low magnitude. These characteristics make the pPD444/6514 ideal for
applications requiring battery backup. In addition, the compatibility of the
pPD444/ 6514 with 2114-type devices affords the designer a higher degree of flexibility.

• LowPowerOperation
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Excellent Speed Operation (300 ns access time)
TTL Compatible on Inputs and Outputs
Completely Static Operation
Single +5V Supply
Common Data Input and Output Using Three-State Outputs
The Basic Part Operates at +4V to +7V
Data Retention is Guaranteed to +2V on All Parts
Replacement for 2114 and Equivalent Devices

A6

VCC

A5

A7

A4

AS

A3

Ag

AO

1/°1

A1

1/°2

A2

1/°3

CS

1/°4

GND

78

WE

··NEC
NEe Microcomputers, Inc.

p.PD445L
fLPD445L·1

FULLY DECODED 4096 STATIC CMOS RAM
DESC R I PTION

The IlPD445L is a very low power 4,096 bit (1024 words by 4 bits) static RAM fabricatec
with NEC's complementary.MOS (CMOS) process. It has-two chip enable inputs (CE1,
CE2). Minimum standby current is drawn when CEl is at a high level, while inhibiting
all address and control line tr,ansitions or, unconditionally When CE2 is at a low level.
This device ideally meets the· low power requirements of battery operated systems and
battery back-up systems for non-volatilitY of data.
The IlPD445L uses fully static circuitry requiring no Clock,ing. Output data is read out
non-destructively by placing a high on the R/W pirf.and has the sam.e polarity as input
data. All inputs and outputs are directly TTL compatible. The device has common
input/output data busses and an OD (Output Disabfe) pin for use i.n Common I/O bus
systems.
The JLPD445L is guaranteed to retain data with the power supply voltage as low as 2.0
volts.

FEATURES

• Single+5VPowerSupply
• Ideal for Battery Operation
• Low Standby Power for Data Retention
• Simple Memory Expansion - Chip Enable ,Inputs
• Access Time - 650 ns Max. (IlPD445L)
450,ns Max. (IlPD445L~1)
• Directly TTL Compatible - All Inputs and Outputs
• Common Data Input and Output
• Static CMOS - No Clocks Refreshing Required
• 20 Pin Dual-In-Line Plastic Package

PIN CONFIGURATION
A3

PIN .NAMES

vcc

A2

A4

·A,

RIW

AO

CE,

A5

OD

As

CE2

A7

AS

GND

Af!

I/O,

1/°4

1/°2

li03

- Address Input
Output' Disable·
Read/Write
Chip Enab)e ,

Ao-Ag
OD
R/W
CE,
CE2
1/0,-110 4
VCC
GND

Chip Enable 2
Data Input/Output
Power Supply
Gr"l'nd

OPERATION MODES
CE,
0
0

CE2

OD

,
, ,

Chip

Output Mode
Data Out

0

Selected
High Impedance

Others

Non-Selected

79

JLPD445L
BLOCK DIAGRAM

...... -1 oOe to +70o e
. ... -400 eto +125°e
-0.3 to Vee +0.3 Volts
-0.3 to Vee +0.3 Volts
-0.3 to +7 Volts

Operating Temperature .. .
Storage Temperature.. .
All Output Voltages ...... .
All Input Voltages ....... .
Supply Voltage Vee ..... .

ABSOLUTE MAXIMUM
RATINGS*

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliabil ity.

*Ta = 25°C
Ta = -10 to +70°C; +5V

±

10%
liMITS

PARAMETER

SYMBOL

I\!IIN

TYP

MAX

UNIT

TEST
CONDITIONS

V

Input High Voltage

VIH

+2.2

Vee

Input Low Voltage

Vil

-0.3

+ 0.65

Output High Voltage

VOH1
VOH2

+2.4

Output Low Voltage

VOL

+ 0.4

V

IUH

+ 1.0

"A

VI = Vee

ILil

- 1.0

"A

VI = OV

IlOH

+ 1.0

"A

Vo = Vee,
CE1 = 2,2V

1.0

"A

Vo = OV,
CE1 = 2.2V

Input.'Leakage
Current High

Input Leakage
Curren,t Low

Output Leakage
Current High

Output Leakage
Current Low

IlOl.

Supply Cu rrent

ICC1

V
V
V

+3.5

12

25

rnA

IOH =-1.0rnA
IOH - ·100"A

IOl

==

+2.0 mA

Outputs Open
VI = Vee except
eE1

<

O.65V

Outputs Open
Supply Current

ICC2

Standby Current

ICCl

80

16

30

rnA

40

"A

VI'= 2.2V except
CE1 '" 0.65V
VI = 0 to S.25V
Except CE2 .;;; O.2V

DC CHARACTERISTICS

fLPD445L
AC CHARACTERISTICS

READ CYCLE
Ta

= -10°C to +70o C;

VCC

= +5V

± 10%

LIMITS
445L-1

445L
.PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

TEST
CONDITIONS

UNIT

Read Cycle Time

tRC

Access Time

tA

650

450
450

ns

Chip Enable
(CE1) to Output

tCOl

600

400

ns

Chip Enable
(CE2) to Output

'tC02

700

500

ns

Input Rise Time
20 ns

OutpUt Enable.
to Output

tOD

350

250

ns

Iriput F all Time
20 ns

Output Disable
(OD) to Floating

tDF

130

ns

Data Output
Hold Time

tOHl

0

0

ns

Chip Disable
to Floating

tOH2

0

0

ns

Address Rise
and Fall Time

tr
tf

650

150

0

ns

0,

,

300

Input Voltage Levels
V

+0.65 to +2.2V

Timing Measurement

Reference Level
+1.5V

".

300

=

=

Output Load
1 TTL + 100 pF
For Address change
during Chip Enabled

ns

WRITE CYCLE

,.
;

LIMITS
445L

PARAMETER

SYMBOL

MIN

445L-1

MAX

MIN

MAX

TEST
CONDITIONS

UNIT

Write Cycle Time

twc

650

450

ns

Address Setup
Time

tAW

150

130

ns

Chip Enable
(CE1) to Write
End

tCW1·

550

.350

ns

;.Input Rise Time
20 ns

Chip Enable
(CE2) to Write
End'

tCW2

550

350

ns

Input Fall Time
20 ns

Data Setup Time

tDW

400

250

ns

Data Hold Time

tDH

100

50

ns

Timing Measurement

Write Pulse Width

twp

400

250

ns

Reference Level =
+L5V

tWR

50'

50

ns

Output Disable
Setup Time'

tDS

150

130

ns

Address Rise
and Fall Time

tr
tf

Input Voltage Levels
VI

.,

Ad,dress Hold.
Time

300

300

= +0.65 to +2.2V

For Address change
during Chip Enabled

ns

LOW Vec DATA RETENTION
a
PARAMETER

SYMBOL

V CC for Data Retention

VCCDR

Data Retention Current

ICCDR

Chip Deselect Setup Time

tCDR

Chip Deselect Hold Time

tFt

Note: CD tRC

LIMITS
TYP

MIN

MAX

V

+2.0.
'

..

UNIT

40

!-LA

0

ns

tRcCD

ns

TEST
CONDITIONS
CE2'; +0.2V
VCCDR - +2.0V
CE2'; +0.2V

= Read Cycle Time

8~

I

TIMING WAVEfORMS

READ CYCLE

ADDRESS·

tOH2

CE,

too
00
(COMMON 1/0)
toP~

1----,--tA - - - - - - 1
DATA OUT

-

..... - - HIGH IMPEDANCE STATE

WRITE CYCLE

1-----------tWC---------------;
ADDRESS

-------t---"' r--------- tcw , ----------i

CE,
1--t--------tCW2-------~~

00
(COMMON 110)

tOH
DATA
IN

L-._f------tow
------~~~--------twp--------~,-------~------R/W

-

-

-

-

HIGH IMPEDANCE: STATE

LOW VCC DATA RETENTIONG)
DATA RETENTION MODE

SUPPLY VOLTAGE (Vee)

VI~
CHIP ENABLE (CE21

O.2V

VCCDR

~

F

..
_ _ _ _ _ _ _ _ _ _ _,......______

.

V,H

·ti:,V

w----------------~-_--------~Note CD Apply Il!Ss than VCCDR to all Illputs for ~atillt'tel1tlon modt'.

82

ILPD445L
CAPACITANCE
PARAMETER

PACKAGE OUTLINE
IlPD445LC

SYMBOL

MIN

LIMITS
TYP MAX

UNIT

TEST
CONDITIONS

Input Capacitance

Cr

5

8

pF

VI = OV

Output Capacitance

Co

8

12

pF

VO=OV

i'

K--~---I

~----------------A-----------------4

IF- =1
L

i

o-w~
ITEM

MILLIMETERS

INCHES

A

27.00

1.07

a

2.07

0.08

C

2.54

0.10

D

0.50

0.02

E

22.86

0.90

F

1.20

0.05

G

2.54 MIN

0.10 MIN

H

0.50 MIN

0.02 MIN

1

4.58 MAX

0.18

J

5.08 MAX

0.20

K

10.16

0.40

L

8.60

0.39

M

0.25

~~.~~

I

+0.004
0.01 -0.002

SP44SL-8--78--GY·CAT

83

NEe

NEe Microcomputers, Inc.

JJ. PD454

FULLY DECODED 2048 BIT ELECTRICALLY
ERASABLE AND'PROGRAMMABLE
READ ONLy MEMORY .
DESCR IPTION

The J,lPD454 EEPROM, a 256 W\irds x 8 Bits Read Only Memory, is designed for rapid
development of microcomputer systems. The ability to electrically program, erase, and
reprogram the pPD454 provideSa· fasi: and convenient means of debugging both hardware and software designs.

Th~ J,lPD454

F EA TU R ES

PIN CONFIGURATION

is pin for pin compatibl·e with NEC's J,lPD464 mask programmed ROM.

,; Electrically Erasable ·and Programmable
• Fully Decoded, 256 Words x 8 Bits Organization
• Access Time. 800 ns Max
• Low Power: 245 mW (Typ.) in Read Operation
670 mW (Typ.).in Programming Operation
• Fast Programming and Erasure Speed
• Low Power for Programming and Erasure
• Static, No Clock Required
• .lnpu.tJOutput TTL Compatible for Read and Programming Operation
• ·Three-State Output, OR·Tie Capability
• N-Channel MOS Fabrication
~ Two Power Supplies, +12V and +5V for Read Operation
• 24 Pin Cerarnic DIP

cs

24

VCC

AO

23

DO

22

D1

A1

3

A2

4

A3

5

A4

6

A5

7

A6
A7
PG

I

D2

J,lPD
454

20

D3

19

D4

18

D5

8

17

D6

9

16

D7

10

15

VCG

VCl

11

14

VDD

VBB

12

13

Vss
t,"'.

Rev/1
85

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . -40°C to +125°C
.
CD
All Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +11 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3to+11 VOlts.®
Supply Voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to +15 VoltsI'D
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7 Volts (i)
.
@
Supply Voltage VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to -7 Volts
Supply Voltage PG . , . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 VoltsCD@
Supply Voltage VCl . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +43 Voll's(i)@·
Supply Voltage VCG . . . . . . . . . . . . . . . . . . . . . . . . . . .. -44 to +30 Volt~(i) @
Notes:
Relative to V BB .
.
® Data in the memory cell is not guaranteed to be preserved.
Specifies ratings which will not cause permanent damage to the device.

ABSOLUTE MAXIMUM
RATINGS*



MAX

UNIT

Address Setup
Time

tASW

10

fJs

Address Hold
Time

tAHW

10

fJS

tww

40

Write Data Width
V SS Setup Time

TSS

Vss Hold Time

TSH

PG, VCG Setup
Time

TpS

1.0
1.0
10

100

ms

TEST
CONDITIONS

per one word

fJs
JlS

fJS

TIMING WAVEFORMS

AO-Ag

~--------

"----r---""--- --- ---~

01 -

Os _ _ _ _-..::::.:....:.~

(INPUT)

- - - - "1"Write

\.'----95

,.,. PD458
, .

Ta

ERASURE OPERATION*

= 25°C ± 2°C, VOO = VCC = PG = OV, VSS = OV or Open

CS, AO -

A9 and 01 '- 08 = Either HIGH or lOW level;or non-connected

PARAMETER

SYMBOL

Supply Voltage

VBB

Supply Voltage

LIMITS
MIN

TYP

-4.75

-:5.0

UNI.T
MAX

TEST
CONDITIONS

-5.25 :V

VCl

+35

+36

+37

V

through RCl

Supply Voltage

VCG

-39

-40

-41

V

through RCG

Supply Current
(VBB)

IBB

-240

mA

Supply Current
(VCl)

ICl

+240

mA

Initial peak
cu rrent; See
tim ing chart.

Supply Current
(VCG)

ICG

-20

IlA

.,

Ta = 25°C ± 2°C, VOD = Vce = PG = OV, VSS = OV or Open
(;S, AO - A9 and.Ol - 08 = Either HIGH or lOW level, or non-connected
PARAMETER
Clear Time
V BB Setup Time

SYMBOL

LIMITS
MIN.

TYP

MAX

60

TCl

DC CHARACTERISTICS

UNIT

..

AC CHARACTERISTICS

TEST
CONDITIONS

sec

TBS

0

VBB Hold Time

TBH

0

Ils

VCG Setup Time

TCS

1.0

Ils

V CG Hold Time

TCH

1.0

j.ls

Ils

TIMING WAVEFORMS
-4.75V

TCS
35V
~-----TCL----~

ICL

IBB

---------I~ - -

Peak = +240 mA max.

V"- --.

Peak = ':':240 mA max.
Note: The supply currents'IBB and lel diminish to almost zero within Tel*Erasur.e operation clears all 8192 bits tei logic "0" simultaneously'.
98·

,.,. PD458
APPENDIX
PROM PROGRAMMER
DESIGN

To insure integrity and retention of data programmed in the J1PD458,
the following requirements are speCified for the IlPD458 supply
voltage and current levels. The PROM PROGRAMMER should be designed
such that voltages provided to the PROM socket be within the range
specified on any occasion including power on/off to the programmer,
power on/off to the IlPD458, and in READ, WRITE or ERASE operation.
Surge or noise voltages beyond the specified range are to be avoided.
Setting VDD =+12V ± 5%, VCC = +5V ± 5% and VCG = +3V ±0.1V after
erasure and comparing data read from the IlPD458 with zero effectively
tests for proper erasure.
.
Setting V DD= +12V ± 5%, V CC = +5V ± 5% and V CG = - 3V ± 0.1 V after
programming and comparing data read from the }1PD458 with the desired
data coupled with erase verification, provides a simple test of worst-case
temperature and long-term data retention.
Under normal Read Mode conditions, VCG should either be grounded
directly or held at OV ± 0.1 V through RCG' RCG is required when any
non-zero voltage is applied to VCG.
LlMITS@
PROGRAM

READ
SYMBOL
VOD

MIN

TYP

MAX

MIN

+11.4

+12

+12.6

-0.3
-0.3

VCC

+4.75

VCG

-0.1

0

+0.1

+5.25

+5

Vss

-0.1

0

+0.1

PG

-0.3

0

+0.3

VCl

-0.1

0

+0.1

+25
-1.9
+25

TYP

MIN

0

+0.3

-0.3

0

+0.3

0

+0.3

-0.3

0

+0.3

+26
-2
+26

-0.1

ERASE

MAX

0

+27
·-2.1
+27
+0.1

-39
-4.75
-0.3
+35

TYP

-40
-5
0
+36

MAX

-41

TEST
UNIT CONDITIONS
V

-5.25

V

+0.3

v

+37

II

V
V

V

+20

-20

ISS

-0.2

-8

-15

-240

mA

IpG

-0.2

+30

+50

-0.2

mA

0
0
0
0
0

ICL

-0.5

mA

(i)

mA

ICC

+20

+30

-0.2

-0.2

100

+55

+80

-0.2

-0.2 I rnA

+10

ICG

-10

+240

pA

CD At typical supply voltage

Notes:

(3)

All voltages relative to VSS '" OV.

PACKAGE OUTLINE
IlPD458D

~-------------E--------------~

1.5 MAX.

0.059 MAX

~C~--~2.54~~--~O.~'----~
----o-r-----;;-O.5c;;Oc-o"CC.,--l--;;oo.oC;C"-OC
OO::;004:---1
33.0

1,299

0.05
3.2MIN
1.0 MIN

0.126 MIN
0,04 MIN

3.3MAX

5.2 MAX.

0.20 MAX

0.60
13.9

0.55
0.012

~

0.004

97

JLPD458

CD@

+5V

AS

Ag

NC

VCC

AS

Ag

25
NC

h

A6
2

A5
3

A4
4

A6

A5

A4

+5V

AS

Ag

-5V

vcc

AS

Ag

VBB

A7

CS

+12V NC

OR

°7

23
VOO

05

19
06

°5

°2

03

NC

Os

AO
S

01

AO

°1

°2

03

Os

07

06

05

A3
5

A2
6

A1

A3

A2

A1

cs

Voo

06

07

OV
°4

~

17

04

16
15
VCl PG

Vss

VBB

!1PD458D (EEPROM)

9
~~

OV

2708 (PROM ERASABLE
WITH ULTRAVIOLET)

°4

PG

Os

°7

A1

AO

01

°2

03

Vss

A1

AO

°1

°2

03

OV

06

05

°4

04

CS/WE

A7

A6

A4

A7

A6

A5

A4

+5V

AS

Ag

-5V

CS1 +12V CS2

Os

°7

24
vcc

23
AS

22

21
VBB

19
20
CS1 Voo

17
08

16

Ag

A3

A2

lS

I

!1PD2308C/D - 2308
(MASK ROM)

°4

°7

CS2/CS2

A7

A6
2

A7

A6

A5

A4

A3

A2

VCC

AS

(NC)
Ag -5V

cs

VOD

2S

27

26

A4

A1

A1

°2

03 Vss

AO

°1

°2

03

ov

(NC)
OV Os

°7

06

°5

04

II VCl PROG

21

20

19

18

17

I 16

22

2308/
2708

A7

3

4

5

6

7

S

AS

A5

A4

A3

A2

A1

AO

0)

®

COMMON PIN
CONFIGURATION

458

2

Notes:

15

9

01

10
02

11
03

12

13

14
VBB

Names of signals.
Names of the terminal.

SP458-4-77-GY-CAT

98

NEe

NEe Microcomputers, Inc.

JLPD2716

~rn~[~WJ~~illrnW
16K ULTRAVIOLET ERASABLE PROM
I,

DESCR I PTION

"

The /.IP02716 is a 16,384-bit Ultraviolet Era!iable and Electrically Programmable Read
Only Memory. Orga~ized as 2048 words x 8 !bits, it opera,tes from a single +5 volt powe
supply, making it ideal for microprocessor a~!plications. It is pin·for·pin compatible
with the ilP02316E, allowing economical changeover to a masked ROM for production
quantities.
The /.IP02716 features fast, simple, one pulse, programming, controlled by TTL level
signals. Total prog~amming time for all 16,38:4 bits is only 100 seconds.

FEATURES

• Access Time - 450 ns Max
•
•
•
•
•
•

2048 Words x 8 Bits Organization
Single+5V Supply
Pin Compatible with /.IP02316E Masked R:OM
F--_~

BLOCK DIAGRAM

GNDO>---~

V~pO

_
OE
CE/PGM _

~

.

OUTPUT. ENABLE
CHIP ENABI.E AND
PROG LOGIC

Ao-A10 .
ADDRESS
INPUTS

OUTPUT BUFFERS

Y
DECODER

Y-GATING

X
DECODER

16,3B4 BIT .•.
CELL MATRIX

Operating Temperature- _. _ .. __ . ___ .. _ .. _. __ . _ ...... _. :-10°Cto+80°C
Storage Temperature... _ ........ _ . . . . . . . . . . . . . . . . . . . -65°.C to+125°C
All Input Voltages ................. _ .. ; ... _ ........ +6 to -Cl;3 Volts CD
All Output Voltages . . . . . . . . . . . . . . . . . . . . _ . _ .... _ . _ +6 to .... 0;3 VQlts CD
Supply Current Vpp . . . . . . . . . . . . _ . . . . . . . . . . . _ ... +26.5 to-O,3 Volts ®
Notes:

ABSOLUTE MAXIMUM
RATINGS·

CD With Respect to Ground.
(2)

With Respect to Ground During Program.

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause p~rmanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta = 2SoC

Ta = 25°C; f

= 1 MHz·

CAPACITANCE
LIMITS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

TEST
CONDITIONS

= OV
= OV

Input Capacitance

GIN

4

6

pF

VIN

Output Capacitance

GOUT

8

12

pF

VOUT

Note:

CD

This parameter is only samp,led and is not 100% tested.

The recommended erasure procedure iii to illuminate the window with a ultraviolet
lamp which lias a wavelength of 2537 ~ngstroms (A). The distance should ·be one inch
from the window to the lamp. Erasure time will be from 19 to 45 minutes depending
on the type of ultraviol.et lamP. The al:nouht of time required can be expressed as the
total amount of.ultraviolet energy inciident to the Window, expressed in watt-seconds
per square centimeter. The J.lPD2716 Irequires an integrated dosage (ultraviolet intensity
x exposure time) of ·15 watt-~econds/Gm2. This erase energy includes sufficient guardband to ensure complete erasure of alii bits.

100

; Vpp = VCC ± O.6V (i)
LIMITS

PARAMETER

AC CHARACTERISTICS

SYMBOL MIN

TYP(V

MAX

UNIT

TEST
CONDITIONS

Input Load Current

III

10

MA

VIN = 5.25V

Output Leakage Current

ILO

10

MA

VOUT = 5.25V

Vpp Current

IpP1 (2J

12

rnA

VPP = 5.85V

Vee Current (Standby)

ICC1

10

25

rnA

CE = VIH, OE - VIL

57

100

rnA

CE=CE=VIL

(2J

Vee Current'(Activel

ICC2 0

Input Low Voltage

VIL

-0.1

Inpu~

VIH

2.0

High Voltage

Output Low Voltage

VOL

Output High Voltage

VOH

Ta

Dot to + 70oe;

Vee='

5V,.

5%

0.8

V

VCC+ 1

V

0.45
2,2

CD C??: Vpp

v'ce

=

O.6V

+

V

IOL = 2.1 rnA

V

IOH = -400~A

@

®

LIMITS
PARAMETER
Address to Output Delay
CE to Output Delay
Output Enable to Output Delay
Ena~e

Output

High to OutPut Float

Address to Output Hold

CD

Notes:

Vee

SYMBOL

MIN

TVP@

MAX

TEST
CONDITIONS

UNIT

tAce

450

CE"'OE-VIL

teE

450

OE=VIL

tOE

140

CE

=

VIL

tOF

100

CE

=

V1L

eE" OE- V'L

tDH

must be applied simultaneously or b€fore Vpp and removed simultaneously or

after Vpp.

(2)

Vpp may be connected directly to VCC except during programming. The supply

of ICC and IpP1.
® The tolerance of 0.6V allows the use of a driver circuit for switching the Vpp

II

current would then be the sum

supply pin from VCC in read to 25V for programming.

TIMING WAVEFORMSG)

@
@

Typical values are for T a = 25°C and nominal supply voltages.

®

AC Test Conditions:

This parameter is only sampled and is not 100% tested.
Output Load: 1 TTL gate and CL "" 100 p"F
Input Ri~e and Fall Times: >:;;20 ns
Input Pulse Levels: O.SV to 2.2V
Timing Measurement Reference Level:
Inputs:
lV and 2V
Outputs: O.SV and 2V

CE

------t-""\
'-----

6l' ------r-----"\

-f+f+{

CD BE may be delayed up to tACC -

o

... ~

... i

OUTPUT _ _ _ _ _ _H"":,;:G;.;H,.;;Z'-_ _ _

Notes:

_~X'-__

ADDRESSES
VALID

ADDRESSES

l

V

tDF

VALID OUTPUT

tOE after the falling edge of

HIGH Z

ff without impact on tACC.

tOF is specified from BE or CE, whichever occurs first.

101

fLPD2716
Initially, and after each erasure, all bits of the pPD2716 are in the "1" state. Information is introduced by
selectively programmir9 "0" into the desired bit locations. A programmed "0" can only :i.' changed to a "1"
by UV erasure.
.

PROGRAMMING
OPERATION ..

The IlPD2716 is programmed by applying a 50 ms, TTL programming pulse to the CE/PGM pin with the CE
input high and the Vpp supply at 25V ± 1V. Any location may be programmed at any time - either
individually, sequentially, Of randomly. The programming time fbr a singl,e bit is only 50 ms and for all bits
is approximately 100 seconds for the ,uPD2716.

CAUTION: The Vee and Vpp supplied must be sequenced on and off such that Vee is applied simultaneously or before Vpp and removed simultaneously or after Vpp to prevent damage to the ,uPD2716. The.
maximum allowable voltage during programming wh ich may be applied to the Vpp with respect to ground is
+26V. Care must be taken when switching the Vpp supply to prevent overshoot exceeding the 26V ma'ximum
specification, For convenience in .programming, the JiPD27l6, may be verified with the Vpp supply at 25V ±
lV. During normal read operation, however, Vpp must be at Vee.

25"C'5C:VCC·5V'5":,W:Vpp~25Vl1VW @

T,

LIMITS
MAX

UNIT

Input Clinent (for Any Input)

III

10

Vpp Supply Current

IPPl

12

"A
mA

U/PGM - VIL
CE/PGM= VIH

PARAMETER

SYMBOL

MIN

TYP

Vpp SupplV Current During
Programming Pulse

IPP2

30

mA

Vce Supply CUI rent

ICC

100

mA

Input Low Level

VIL

0.1

0.8

V

Input High Level

VIH

2.0

Vec+ 1

V

,-

T -2S"C+ S"C'Vec-SV
-+SllIo(2)'Vpp=25V -+ lV

LIMITS

DC CHARACTERISTICS
TEST
CONDITIONS

VIL

C to +70°C;

vee:: +5 ± 5% unless otherwise noted.

DC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

MIN

MAX

UNIT

TEST CONDITIONS

"A
"A

VIN = OV

ILOH

+10

"A

Chip Deselected.

ILOL

-20

"A

Chip Deselected, Vo '" OV

120

mA

Output Leakage Current

Output Leakage Current
Power Supply Current

lee

Input "Low" Voltage

VIL

-0.5

Input "High" Voltage

VIH

+2.4

Output "Low" Voltage

VOL

Output "High" Voltage

VOH

104

 - - - - - - I

PACKAGE OUTLINE
J.!PD548C

A----------------~

:g~~J--gn~~
c-

i UUJ~LU I

-tl-O

~----~----------E--------------~

ITEM

MILLIMETERS

A

56,0 MAX

2.2 MAX

INCHES

B

2,6 MAX

0.1 MAX

C

2.54

0.1

0
E
F

0.5 ± 0.1

0.02 ± 0,004
2.0

50,B

G

1.5
'3.2 MIN

H

0.5 MIN

0.02 MIN

I

5.22 MAX

0.20 MAX

6.72 MAX

0.22 MAX

J

0.059
0.126 MIN

K

15.24

0.6

L
M

13.2

0.52
0.01 ± 0.004

0.3± 0.1

SP54&9-78-GN-CAT

128

ttlE'C

NEe Microcomputers, Inc.

JLP0555

EVACHIP·42

DESCR I PTION

The I-!PD555 is a system evaluation chip designeoto support both hardware and s.oftwan
debugging of the tJCOM-42 (tJPD548) one-chip microcomputer system.
.
The tJPD555 and thetJPD548 have the same functionality in all aspects except that the
does not contain a read only memory. but proviQes addressing C9pability to
external memory and HOLD function for step-by-step operation.

tJPD~55

FEATURES

•
•
•
•
•
•
•
..
•

•
•
•
•

PIN CONFIGURATION

4-Bit Parallel Processor
.
(
Powerful 72 Instruction Set Inctuding Decimal/Binary Arithmetic Operations
10J.ls Instruction Cycle Time
-'
Addressing Capability up to 1920 Words by 10-Bits of External Program Memory'
96 Words by 4-Bit Data Memory On Chip
4- Level Su broutines
Two Interrupt Input Lines (fA and IB)
HOLD Capability
A Variety of Input/Output Ports10 Discrete Output Ports (Fg-FO)
Two 8-Bit Output Ports (U7-UO. RrRo)
4-Bit I nput Port (K3-Kol
4-Bit Input/Output Port (S3-S0)
I/O Level Compatible with IlPD5101
l-Bit Test Input Line
p-Channel MOS
Open Drain Output
Single Power Supply: -10V
Available in a 64 Pin Ceramic Dual-in-Line.Package
,

GND ri~-",,-~-~;t-.,

II

up

P3
P?
P1
Po

U1
U2
U3
U4

A6

Us

AS
A4
A3

U6
U7
F9

A2

Fa

A1

F7

AO
Ip
11
12 "

F6
FS
F4
F3

13

F2

14

1=1

15

;-0

16
17
18

53
$2

PIN NAMES

Po - P3

Page Output

t\O-AS

Address Output

10- 19

Instruction Input

HOLD

HOLD Input

~O

R7

Output Port R
Clock Input

¢

. -RES

Reset Input

K4

K4 Test Input Line

ItO.- K3

K Input Port

TEST

Ie Test Input

rhterrupt Input

19

51
So

HOLD

fA

'I',,'B

RO

IB

So - S3

Input/Output Port S

Fa:-: Fg

Output Port F

Uo-

Output Port U

°R1

R2
R3
R4

R5

TEST

K3
K2
K1

U7

~o

R6

K4

R7

~ES

(--10VI VGG . . ._-----~r,J

129

JLPD555
u) 0

F-g

FO

HOLD

IA

18

K4

BLOCK Dl.AGRAM

R) 0

CG

RES

53·0

TEST

K3-0

OperatingTemperature . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage VGG ...... " . . . . . . . . . . . . . . . . . . . . . . .
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All Output Voltages ... : . . . . . . . . . . . . . . . . . . . : . . . . . . . .

-10°Cto+70°C
-40°C to +125°C
-15 to +0.3 Volts
-20 to +0.3 Volts
;"20 to +0.3 Volts

ABSOLUTE MAXIMUM
RATINGS*

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional o"eratit?n of the device at these or
any other conditions above those indicated in the operational sections of this specification. is not
implied. Exposure to absolute mc;lximum rating conditions' for extended periods may affect device
reliability.
*T a ='25°C

CAPACITANCE
LIMITS
PARAMETER

SYMBOL MIN

TYP

MAX

TEST
UNIT CONDITIONS

Input Capacitance

CI

15

pf

Output Capacitance

Co

15

pf

Input/Output Capacitance

CIO

15

pf

130

f

= 1 MHz

,.,.PD555
DC CHARACTERISTICS

Ta = _10°C to +70°C; VGG = -10V ± 10%, unless otherwise noted.
LIMITS
PARAMETER

AC CHARACTERISTICS

SYMBOL

MIN

MAX

TYP

a

~2.0

TEST
;CONDITIONS

UNIT

High Level Input
Voltage

VIH

V

Low Level Input
Voltage

VILl

-4.3

VIL2

-7.0

V

Except S, ¢, IB-O

High Level Input
Le*age Cl,Jrrent

I LlH

+10

IlA

VI =-lV

Low LQvel Input
Leakage Current

I LlL

-10

IlA

VI =-llV

High Level Output
Current

IOH

rnA

Vo = -lV, except
Sport

Low. Level Output
Leakage Current

I!-OL1

High Level Output
Voltage

VOH

Low Lellel Output
Leakage Current

ILOL2

Power Supply
,
Current

IGG

,),

V

-1.0
.-30

VO=-llV;
. ·except Sport

V

IOH = -100IlA,
Sport

-10

!1A

Vo = -5V,
Sport

-60

rnA

-1.75

-30

Il.A

S,¢,lg·O

Ta = _10°C to +70°C, VGG = -10V ± 10%, unless otherwise noted ..
LI!\I1 ITS
PARAMETER
Clock Frequency

SY!\I1BOL

MIN

TYP

MAX

UNIT

200

KHz

f¢

100

Clock Pulse Width

t¢w

2.25

Clock Rise and
Fall Times

tr, tf

0.5

J,lS

Input Setup Time
from Output

tiS

~.5

J,lS

TEST
CONDITIONS

II

CL = 100 pF,
RL = 5.1 KD

131

,uPD555
TIMING WAVEFORM

rp---

P3·0
AS.O

-

_ _ _ _ _ _ _ _ _ _ _ _ _ _ ..JI

19-0
-

-- -

-

_

-

_________________ __ J I

PACKAGE OUTLINE
J.lPD555D

ITEM
A
B

C
0
E
F

G
H
I

J
K
L
M

MI LLIMETERS

82.0 MAX
1.6
2.54
0.43 + 0.1
78.8
1.27

3.2 MIN
1.3MIN
3.9
5.2 MAX
22.96

20.3
0.3 ± 0.1

INCHES
3.23 MAX

0.063
0.1
0.017 + 0.004
3.1
0.05
0.13 MIN
0.05 MIN
0.154
0.205 MAX
0.904
0.8
0.012 + 0.004

SP555·9·78·GN·CAT
132

NEe Microcomputers, Inc.
fLCOM·43/44/454·BIT SINGLE CHIP
MICROCOMPUTERS
DESCRIPTION

The !1COM-43 Family consists of three device types' designed to offer a full range of
cost/performance tradeoffs, All three devices share compatible hardware and instruction set, The !1COM-43 Family is designed for general purpose controller applications
and offers ideal devices for industrial controls, appliance controls, games, etc.
All three devices contain the functional blocks'necessary to enable, their use for both
industrial and non-industrial controller applicatioris, These blocks include: a 4-bit
parallel ALU; &bit wide ROM for program storage; 4:bit wide RAM for data storage;
stack register for subroutines; extensive I/O; and an'()n-chip clock generator.
The instruction set of the !1COM-43 Family is designed to perform controller-oriented
functions and for efficient use of the fixed program memory space. The instruction
set includes a number of multifunction instructions, powerful I/O instructions
including single bit manipulation, and test-and-skip instructions for conditional
processi ng.
The three device types comprising the !1COMA3 Family are differentiated by ROM/
RAM size and I/O lines, The !1COM-43 has 2000 x 8 ROM, 96 x 4 RAM and 35 I/O
lines. The ,uCOMA4 has 1000 x 8 ROM, 64 x 4 RAM and 35 I/O lines. The !1COMA5
has 1000 x 8 or 640 x 8 ROM, 32 x 4 RAM and 21 I/O lines. In addition, the
!1COM-43 has real hardware interrupt, 3 level stack a'nd programmable timer, while
the !1COM-44/45 have pseudo-interrupt capability and a single level stack,

FEATURES

• Stand Alone 4·Bit Microcomputers for Control Applications
•

Powerful Instruction Set Capable of: Binary Addition; Decimal Addition and
Subtraction; Logical Operations

•

10!1s Instruction Cycle

•

Choice of ROM Size: 2000
1000
1000
640

•

Choice of RAM Size:

96 x 4 - !1COMA3
64 x 4 - pCOMA4
32 x 4 - !1COM-45

•

Choice of I/O Power:

35 lines - !1COM-43
35 lines- !1COM-44
21 lines - !1COMA5

•

All Capable of Single Bit Manipulation and 4-Bit Parallel Processing.

•

Interrupt Capability

•

On-Chip Clock Generator

•

Open Drain Outputs

x
x
x
x

8 - !1COM-43
8 - !1COM-44
8 -!1COMA5
8

•

Choice of PMOS or CMOS Technology, Both Requiring Single Supplies

•

Available in 42 Pin or 28 Pin Plastic Dual-in-line Packages

133

p.COM-43/44/45
Cl l

PCO
PCl
PC2
PC3
INT
RES
PDO
PDl
PD2
PD3
PEO
PEl
PE2
PE3
PFO
PFl
PF2
PF3
TEST
OV)GND

ell
PCo
PCl
PC2
PC3
PDO
PDl
PD2
PD3
PEO
PEl
PE2
PE3
VSS(OVI

IlCOM
43/
44

ClO
VGGHOV)
PB3
PB2
PBl
PBo
PA3
PA2
PAl
PAO
PI2
Pll
PIO
PH3
PH2
PHl
PHO
PG3
PG2
PGl
PGO

Clo
VGG(-10V)
RES
INT
PA3
PA2
PAl
PAO
PGo
PF3
PF2
PFl
PFo
TEST

PIN CONFI.GURATIONS
PIN NAMES
CL O-CL 1

External Clock Source

PC O PC3

Input/Olltput Port C

lin

Interrupt Input

RES

Reset

PDO-PD3

Input/Output Port D

PEa PE 3

Output Port E

PF O PF3

Output Port F

TEST

Input for Testing

PGO-PG3

Output Port G

(Normally GNOl
P~O-PH3

Output Port H

PIO-PI3

Output Port I

PAO-PA3

!nput Port A

PBO-PB3

Input Port B

PIN NAMES
CLO-CL1

External Clock Source

PCO-PC3

Input/Output Port C

POO-PD3

Input/Output Port D

PE O-PE 3

Output Port E

PF O- PF 3

Output Port F

PG O

Output Port G

PA O- PA 3

Input Port A

INT

Interrupt Input

RES

Reset

BLOCK DIAGRAM
/.lCOM-43

P10·2

PHO-3

CONTROL
&
DECODE

ROM
2000><8

PGO_3

PEO-3

PDO-J

134

fLeo M·43/44/45
BLOCK DIAGRAMS
~COM-44
PJO_2'

CONTROL
&
DECODE'

nOl\1
1000'<.8

PFO-3

PDO-3

lNT
PCO_3

PBO-3

RES

~AO-3

~COM-45

CONTROl
&
HOM

DECODE
PGo

PFO·3

PEO-3
)

PDO-3

INT

HES

PAO-3

FUNCTIONAL
DESCRIPTION

Program Counter
The 11-bit program count,er (1O-bit for pCOM-44i45) is organized as a 3-bit register
(2·bit for pCOM·44/45) and an 8-bit binary up-counter (lower eight bits). The contents
of the upper register specify one of the fields of the ROI\ll"The 8-bit binary counter is
divided so that the contents of the higher two bits specify one of four pages in a field
and the lower six bits specify one of 64 addresses in a page. The contents of the lower
eight bits of the program counter (8-bit binary up·counter) are simply incremented to
execute the instructi.ons sequentially. In a field, a page is automatically extended to the
next one and four'pages (256 bytes) are automatically executed.
Stack Register
The stack register is a last-in-first·out (LIFO) push down stack register organized as 3
words x 11 bits (1 word x1 0 bits for pCOM-44/45). This register is used to save the
contents of the program counter (rllturn address) when a subroutine is called or an
interrupt is acknowledged.
ROM (Read-Only Memory),
The user's application program is stored in the 8-bit wide mask programmable read-only
memory (ROM). The ROM is organized into fields and pages. The 2000 word ROM of
the pCOM-43 has eight fields, the 1000 word ROM of the pCOM-44/45 has four fields
and the 640 word ROM, of the low-end pCOM-45 ,has two fiel ds. Each fiel d is divided
into four pages of 64 words each,a'nd each word ~onsists of eight bits.

135

II

fLCOM.43144i45
RAM (Data Memory)
The RAM is organized in a multi-row by 16 column configuration. It is addressed by
data pointer of which tHe higher bits (DPH) address the row and the lower bits (DPL
address the column. The exact RAM size for each device is shown below.

IlCOM-43

RAM

ROW/COLUMN
ORGANIZATION

DPH

DPL

96 x 4

6 x 16

3

4

Il COM-44

64 x

4

4 x 16

2

4

IlCOM-45

32 x 4

2 x 16

1

4

Internal Registers
The ALU (Arithmetic Logic Unit) and the ACC (Accumulator) form the heart of the
IlCOM-43 Family microcomputer system. The ALU performs arithmetic and logical
operations and tests for operation results. The result of an operation by the ALU is
stored in the ACC and in the carry F IF. The ACC is a 4-bit register which stores ALU
results and other data to be processed. The carry F IF is a single bit flip-flop which
indicates when a carry bit is generated during addition.
Flag Register (IlCOM-43 Only)
A 4-bit word in the RAM can be specifically used as a software controlled general
purpose flag register. The individual flag bits can be set or reset and tested for either a
1 or a O. This can be done directly without modifying the RAM data pointer.
Working Registers (IlCOM-43 Only)
There are six words in RAM that can be used as 4-bit general purpose working registers.
These registers can be directly manipulated without modification of the.data pointer and
are used for data transfer and exchange between the data pointer and the working
register, and between the ACC ahd the working register.
Programmable Interval Timer (IlCOM-43 Only)
The IlCOM-43 contains a software programmable interval timer composed of a 6-bit
polynomial counter and a 6-bit programmable binary counter.
The initial setting of the timer is done using the timer set instruction STM, with the
timer starting to count at the end of the STM instruction execution. The STM
instructio.n contains six binary bits o.f immediate data which is loaded in the 6-bit
programmable binary counter upon STM instruction execution. By varying the 6-bit
immediate data,one of 64 time intervals can be programmed.
I/O P.orts
The IlCOM-43/44 have 35 input/output ports (IlCOM-45 has 21) for communication
with and control of the external world. These ports are organized into nine input/output
ports (A to I). Eight ports(A to H) are composed ot four bits each and the last port(l)
is composed of three bits.

CD

Input Ports

(4 bits each): A, B

Input/Output Ports

(4 bits each): C, D

Output Ports

(4 bits each): E, F, G ~, H

Output Ports

(3 bits): I

Notes:

CD

H

0.7VCC

VCC

V

CLO, Ext. Clk.

Clock Low
Voltage

VL

0

0.3VCC

V

CLO, Ext. Clk.

Clock Leakage

ILH

200

}J.A

Clock Leakage
Current Low

ILL

-200

}J.A

CLO, Ext. Clk.
(VOH = VCC)
CLb, Ext. Clk.
(Vl1l = OV)

Clock Frequency

I
tr, tl

440

0.8

Current High

Clock Rise and Fall
Times
Clock Pulse Width

tW

150
0

0.3

KHz
}J.s

Ext. Clk.

0.5

5.6

}J.s

Ext. Clk.
155

II

J.L PD651
Ta

= -30°C to +85°C, VCC =+5V ± 10%.

CAPACITANCE

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Input Capacitance

CI

15

pf

Output Capacitance

Co

15

pf

CIO

15

pf

I/O Capacitance

TEST CONDITIONS

f = 1 MHz

CLOCK WAVEFORM

1 If

------O.7VCC

ov-- ---

__ K_

I

~ L--·

I

A

PACKAGE OUTLINE
J.lPD651C

~J~Li
iUDUUUD1UJ~,} :~~.~
IB~JU UE~~-r
U

M

ITEM

MILLIMETERS

A

56.0 MAX

2.2 MAX

INCHES

B

2.6 MAX

0.1 MAX

C

2.54

0.1

D
E

0.5 ± 0.1
50.8

0.02 ± 0.004
2.0

F

1.5

0.059

G

3.2 MIN

0.126MIN

H

0.5 MIN

0.02 MIN

\

5.22 MAX

0.20 MAX

J

5.72 MAX

0.22 MAX

K

15.24

0.6

L

13.2

0.52

M

0.3 ± 0.1

0.01 + 0.004

SP651-9-7 B-G N-CAT
156

NEe

NEe Microcomputers, Inc.

fLPD652

,u.COM·45 SINGLE CHIP MICROCOMPUTER
D ESC R I PTI 0 N

The pPD652 is a CMOS version of the pCOM-45. It features a single +5 volt power
supply, a 2 mA (max), 800 pA (typ) current drain and extended temperature range. As
a f.lCOM-45, it includes 1000 x 8 ROM, 32 x 4 RAM, and 21 I/O lines in a 42 pin
plastic dual-i n-I ine package.

ABSOLUTE MAXIMUM
RATINGS*

_30° C to +85 0 C
Operating Temperature ....
_55°C
to +125°C
Storage Temperature.
-0.3 to +7.0 Volts
Supply Voltage . . . . . . . . . .
Input Voltages. . . . . . . . . .
. . . . . . . . . . . . . -0.3 to +7.0 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7.0 Volts
Output Current (Each Output Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specHication is not

implied, Exposure to absolute maximum rating conditions for extended periods may affect device
rei iabil ity.

*Ta = 25°C
DC/AC CHARACTERISTICS

Ta

= _30° C to

+85 0 C, VCC

= +5V ± 10%.
LIMITS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

TEST CONOITIONS

Input High Voltage

VIH

Input Low Voltage

VIL

I nput Lea kage
Current High

ILIH

+10

Input Leakage
Current Low

ILiL

-10

IJ.A

Ports A, C, D, INT, RES
(VI = OV)

I/O Leakage
Current High

IIOH

+10

IJ.A

Ports C and D (VI

I/O Leakage
Current Low

IIOL

-10

IJ.A

Ports C and D (VO = 0vl

Output High
Voltage 1

VOH1

VCC-O.5

V

VCC-0 .5

V

Ports
(IOH
Ports
(IOH

VCC-2.5

V

Ports C to G (IOH ~ -2 mAl

0.7VCC

VCC

0

0.3VCC

V

Ports A, C, D, I NT, RES

V

Ports A,C, D, INT, RES

IJ.A

Ports A, C, D, INT, RES
(VI = VcCI

C and D
= -1 mAl
Eta G
~-1 mAl

Output High
Voltage 2

VOH2

Output Low Voltage

VOLl

0.6

V

Ports E to G
1i0L = 2 mAl

VOL2

0.4

V

Ports E to G
1i0L = 1.2 mAl

2.0

mA

Supply Current

ICC

Clock High
Voltage

VWH

0.5

5.6

~s

Clock Pulse Width Low

t

RD

:r--c----MI

'------

-t--------r-----{INI\-------+--------r---------

Memory Read or Write Cycles
This diagram illustrates the timing of memory read or write cycles other than an op
code fetch (M1 cycle). The function of the MREO and "lD signals is exactly the same
as in the op code fetch cycle. When a memory write cycle is implemented, the MR EO
becomes active and is use~rectly as a chip enable for dynamic memories, when the
address bus is stable. The WR line is used directly a> a R W pulse to any type of semiconductor memory, and is active when data on th'. Jata JUS is stable.
\----Memory Read Cycle---I+__--Memory Write Cycle

'I>

RD
WR

-r-----r-----~IN}--+---<==t==:JD~A~T~A~O~UQT======~

WAIT

174

'-TL-----

fL PD780
TIMING WAVEFORMS
(CONT.)

Input or Output Cycles
This illustrates the timing for an I/O read or I/O write operation. A single wait. state
(TW) is automatically inserted in·J/O operations to allowsufficient time for an I/O
port to decode its address and activate the WAIT line, iJ necessary.

-~~r---L- ~
Tl

'I'
AO·A t .

1

PORT ADDRESS

}

'iN'

WAIT

Read
Cycle

- --- --- :rc- - ---, -----

- --- - ---

--

WR
OUT

00. 0 7

Interrupt Request/Acknowledge Cycle

}

W,oIe

Cycle

The processor samples the interrupt signal with the rising edge of the last clock at the
end of any instruction. A special M1 cycle is started when an interrupt is accepted.
During the M1 cycle, the 10RO (instead of MREO) signal becomes active, indicating
that the interrupting device can put an 8-bit vector on the data b.us. Two wait states
(TW) are automatically added to this cyCle. This makes it easy to implement a ripple
priority interrupt scheme.

.

INT

Last T State

Tl

T2

Tw

h

W

T3

-~~~~~
'---"~
---,
___ '--L,--___
_____
---.---'______________ _
I

REFRESH

PC

MI
MREO
IORO

~r-----~------_t------_r------~------t_--_1rm~---"-"-'
WAIT

--------- ==-= :::.-__ ____TL:: ===
~

-~

RO

INSTRUCTION SET

The following summary shows the assembly language mnemonic and the symbolic
operation performed by the instructions of the tLPD7BO and tLPD7BO-1 processors.
The instructions are divided into 16 categories:
Miscellaneous Group
Rotates and Shifts
Bit Set, Reset and Test
In put and Output
Jumps
Calls
Restarts
Returns

B-Bit Loads
16-Bit Loads
Exchanges
Memory Block Moves
MemoryBlock Searches
. 8-Bit Arithmetic and Logic
16-Bit Arithmetic
G.eneral Purpose Accumulator and Flag Operations

The addressing Modes include c'ornbinations of.the following:
Indexed
Register
Implied
Register Indirect
Bit

Immediate
Immediate Extended
Modified Page Zero
Relative
Extended
175

II

ILPD780
INSTRUCTION SET TABLE
SYMBOLIC
OPERATION

MNEMONIC

ADC HL, 55

HL-HL+ss+CY

ADCA.r
ADC A.n

A-A+r+CY
A-A+n +CY

ADC A.IHU
A +- A
ADC A.IIX + d) A+-A

+ (HLI + CY
+ (IX +d) + CY

A + (IV + d) + CY

ADC A.IIY+d)

A

ADD A, n

A-A+ n

ole-

NO,T
STATES

C

1

11

I

,

1

4
7

I
I

Add with carry loc. (H U to ACe
Add with carry loc. (IX + d) to ACe

7
19

+ d) to ACe

NO.
BYTES

DESCRIPTION
Add with carry reg. pair

to H L

55

Add with carry Aeg. r to ACe
. Add with carry value n to ACe

Add with carry loc. (IV

Add value n to ACe

2

Z

FLAGS
P/V S

OPCOOE
76 543 210

N

H

0

X

11
01

101
ssl

101®
010

10
11
nn
10
11
10
dd
11
10
dd

001
001
nnn
001
all
001
ddd
111
001
ddd

110
nnn
110
101
110
ddd
101
110
ddd

11
nn

000
nnn

110
nnn

V

I

I
I

V
V

I
I

0
0

I
I

I
I

I
I

V
V

I
I

a
a

I
I

19

I

I

V

I

a

I

7

I

I

V

I

a

,

rrr®

ADDA, r

A+-A+r

Add Reg. no ACe

1

4

I

I

V

I

0

I

10 000

rrr®

ADD A.IHL)

A+-A+{HU

Add location (H L) to ACe

1

7

I

I

V

I

I

10 000

110

+ d) to ACe

3

19

I

I

V

,

a
a

I

101
110
ddd

Add location (IV + dl to ACe

3

19

I

t

V

,

11 011
10 000
dd ddd

0

1

11 111 101
10 000 110
dd ddd ddd

0

X

00

ssl

001®

0

X

11
00

all
ppl

101©
001
101@
001

ADD A.IIX + d) A-A+(lX+d)

ADD A. IIY + d) A +- A

+ (lY + d)

Add location (IX

ADD HL, S5

HL~HL+ss

Add Reg. pair 5S to HL

1

11

,

ADD IX. pp

IX - IK+ pp

Add Reg. pair pp to I X

2

15

I

Add R~g. pair rr to IV

2

15

1

4
7

a
0

ADD tV, rr

IV

ANDr
AND n

A-AAr
A ...... AAn

Logical' AND' of Reg. r A ACe
Logical 'AND' of value n A ACC

AND IHLI
AND IIX +d)

A -AAIHLI
A-AAIIX +d)

Logical 'AND' of loc. (HLl A ACC
Logical 'AND' of loc. (IX + d) A ACC

7
19

AND IIY +d)

A+-AAOY

+ d) A ACe

19

BIT b. IHLI

Z- (HL) b

Test BIT bof location (HL)

BITb.IIX+d)

Z +- (iX"""+d1 b

Test BIT b at location (IX

BITb.IIY+d)

+- ~V''''!T

+ d)

Logical 'AND' of loc. (IV

2

12

+ d)

4

20

z-li"Y'+'d) b

Test BIT bat I'ocation (IY + d)

4

20

BITb, r

Z ...... rb

Test BIT of Reg. r

2

8

CALLcc, nn

If condition cc false continue,
else same as CALL nn

Call subroutine at location nn jf
condition cc is true

3

10

CALL nn

ISP-l) -PC H
ISP- 2) - PCl
PC +- nn

Unconditional call subroutine at
location nn

3

17

1

CCF

CY +- CY

Complement carry flag

cpr
CPn

A-r
A-n

Compare Reg. r with Ace
Compare value n with ACC

CP IHLI
CP IIX +d)

A - IHLI
A - IIX + d)

Compare lac., (HU with ACe
Compare lac. (IX: + d) with ACe

CPIIY+d)

Compare loc. (lY

4

X

11
00

111
rrl

I
I

I
I

tOO

rrr®

p
P

I
I

a
0

I
I

I

P

I

0

I

10
11
nn
10
11
10
dd
11
10
dd

100
nnn
100
011
100
ddd
111
100
ddd

110
nnn
110
101
110
ddd
101
110
ddd

I

X

X

0

1

11
01

001 011®
bbb 110

1

X

X

a

1

11
11
dd
01

011
001
ddd
bbb

I

X

X

a

1

11 111 101®
11 001 011
dd ddd ddd
01 bbb 110

I

X

X

a

1

11
01

I
I

0
0

I
I

0

·
·
·
·

·· · ..
·· ·· ..
,
· ··
0

101®
011
ddd
110

~~ ?~~®®

11 <-cc-+ 100®
nn nnn nnn
nn nnn nnn
11
nn
nn

001
nnn
nnn

101
nnn
nnn

111

111

a

X

00

I
I

V
V

I
I

1
1

I
I

19

I
I

I
I

V
V

I
I

1
1

I
I

19

I

I

V

10 111 rrr®
11 111 110
nn nnn nnn
10 111 110
11 011 101
10 111 110
dd ddd ddd
11 111 101
10 111 110
dd ddd ddd

7

CPO

A-IHL)
HL+-HL-1
BC ...... BC- 1

Compare location (HLl and ACC,
decrement HL and Be

2

16

CPDR

A - IHLI
HL - HL~ 1
BC-BC-l
until A "" (HL) or Be"" 0

Compare location (HLI and ACe,
decrement HL and BC, repeat until
BC" a

2

21 if BC '" 0
andA'i (HLI
16;t BC" 0
orA"IHl)

176

0
a
a

P
P

I
I

4
7

+ d) with ACC

·· ·· ··
· ··

·
·

I

1

I

I@ tCDt

1

I

11
10

101
101

101
001

j@ t CD ,

1

I

11
10

101
111

101
001

ILPD780
SVMBOLIC
OPERATION

MNEMONIC
CPI

A- (HLI
HL of- HL + 1

OESCRIPTION

NO.
BVTES

NO. T
STATES

Compare location IHLl and ACe,
incremeht HL and decrement Be

2

16

A- (HLI
HL-HL+l

Compare location (HL) and ACe.

2

BC-BC-l

Repeat un,til

21 if Be '= 0
and A -I (HLI
16 if'Be = 0
or A =-(HLl

BC~BC-l

CPIR

increment H L, decrement Be

until
A ~ (HLI or BC

CPL

~

Be'= c

0

A~A

DAA

Complement ACe (,'s comp.)

1

4

Decimal adjust ACe

1

4

DECr
DEC IHLI
DEC (IX +dl

r- r - 1
(HLI ~ IHLI- 1
(IX + dl ~ (IX + dl- 1

Decrement loc. (IX

+ d)

23

DEC (IV +dl

(IV + dl ~ (IV + dl - 1

Decrement Ia'c. (IV

+ d)

23

DEC IX

IX-IX-l

Decrement I X

2

10

DEelY

IY-IY-l

Decrement IV

2

10

DECss

ss-ss-l

Decrement Reg. pair ss

1

6

01

IFF

Disable interrupts

1

4

Decrement B and jump relative if
B=O

'2

8

Decrement Reg. r
Decrement loc. {HU

4
11

(.

DJNZ, e

~O

S" - B-1 if B = 0
continue jf 8

PC-PC+e
~

*0

EI

IFF

Enable interrupts

1

4

EX (Spi. HL

H - (SP +'11
L-ISPI

Exchange the location (SP) and HL

1

19

EX (SPI. IX

IX H -ISP + 11
IX L - (SPI

Exchange the location (SP) and IX

2

23

EX (SPI. IV

IV H - (SP + 11
IV L - (SPI

Exchange the location (SP) and IV

2

23

AF - AF'

Exchange the contents of AF, AF'

1

4

Exchange the contents of DE and HL

1

4

Exchange the contents of BC, DE, HL
with contents of BC', DE', HL',
respectively

1

4

EX AF, AF'
EX DE, HL

1

,DE - HL

EXX

QC- BC'
DE - DE'
HL- HL'

HALT

Processo( Halted

HAL T (wait for interrupt or reset)

1

4

IMO

Set Interrupt mode 0

?

8

IMI

Set I nte~r~pt mode 1

2

8

1M 2

Set Interrupt mode 2

2

8

Load ACC with input from device n

2

11

INA, (nl

A~lnl

IN r, ICI

r~(CI

INC IHLI

(HLI

INC IX
INC(lX+dl

Load
(CI

~eg.

r with input from device

2

12

Increment location (HL)

1

11

IX-IX+ 1

Increment IX

2

10

fiX + dl-flX +dl + 1

Increment location (IX + d)

3

23

INC IY

IY-IY+ 1

Increment IV

2

10

INC,flY+dl

(Iv + dl -(IV + dl + 1

Increment location (IV + d)

3

23

INC r

r-r+ 1

Increment Reg. r

1

4

INCss

ss-~s+

Increment Reg..pair ss

1

6

IND

(HLI-ICI
B~B'-1

Load location (HLl with input from
port IC). decrement HL and B

2

16

~

(HLI + 1

1

IiL~HL-l

C

Z

·

·

FLAGS
PN S

OPCOOE
N

H

76 543 210

I@ ICD I

1

I

11 101 101
10 100 001

I@ ICD 1

1

I

11 101 101
10 110 001

···· ·
···
1

I

I

p

I

I

I

I

V
V
V

I

V

I

·

I

1

00

I
I

00 100

111

00
00
11
00
dd
11
00
dd

101@
101
101
101
ddd
101
101
ddd

I

1
1
1

I

I

1

I

I

·· ·· ··
·· ·· ··
·· ·· ·· ·· · ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ·• ·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·
·· · · · · ·
~

~

101

rrr
110
011
110
ddd
111
110
ddd

111

11 011
00 101

101
011

11 111
00 101

101
011

00

ssl

011@

11

110 011

00 010 000
~-2----'"

11

111

11

100 011

11
11

011 101
100 011

11
11

111 101
100 011

00 001

011

000

11

101

011

11

011

001

01

110 110

11
01

101
000

101
110

11
01

101
010

101 .
110

11
01

101
011

101
110

11
nn

011 011
nnn nnn
101. 101
rr r 000

I

P

I

0

I

11
01

I

V

I

0

I

00 110 100

I

V

I

0

I

·· ·· ··

·
··· · · · · ·
I

V

I

V

I@ X

eD

11 011 101
00 100 011
11 011 101
00 110 100
dd ddd ddd
11
00

111 101
100 011

I

0

I

11 111 101
00 110 100
dd ddd ddd

I

0

I

00

rrr

00

ssO Oll@

X

1

X

11 101
10 101

loo®
101
010

177

I

INSTRUCTION SET TABLE
(CaNT.)

p.PD780
','

SYMBOLIC
OPERATION

MNEMONIC
INDR

INI

IHLI ~ ICI '
B ~B-l

port (e), decrement HL and deere-

HL

ment B, repeat until B "" 0

+-

+-

HL + 1

IHLI ~ ICI
B-B-l
HL

<-

HL

+ 1 until B :: 0

NO,
BYTES

NO, T
STATES

2

21

Load location (HU with input from
port (e); and increment HL and
decrement B

2

16

Load location (HU with input from
port (e), Increment H L and deerement B, repeat until B = 0

2

21

Load location (HL) with input from

H L - 1 until B '" 0

IHLI ~ ICI
B ~B-l
HL

INIR

DESCRIPTION

JP IHLI

PC~

HL

Unconditional jump to (HLI

1

4

JP OXI

PC

~

IX

Unconditional jump to (I Xl

2

8

JP IIVI

PC~

IV

Unconditional jump to (lY)

2

8

JP ce, nn

If cc true PC - nn else continue

Jump to location nn if condition cc

3

10

IS

JP nn

JR C, e

PC- nn

Unconditional jump to location nn

If C = 0 continue

If C = 1 PC
JR e
JR NC, e

true

<-

Jump relative to PC + e, If carry:: 1

3

2

PC + e

PC';""PC+e

-

Unconditional jump relative to PC + e

If C '" 1 continue
If C = 0 PC +- PC + e

Jump relative to PC + e If carry = 0

JR NZ, e

If Z '" 1 continue

Jump relative to PC + e If non·zero

JR Z, e

If Z '" 0 continue

Jump relative to PC + e If zero

2
2

10

7 if condition
met. 12, if
not

12

7

2

7

2

7

1

7

IZ 001
IZ = 11
LD A, fBCI

A~

IBCI

LD A, IDEI

A~

IDEI

Load ACC with location (DE)

1

7

LD A, I

A~I

Load ACC With I

2

9

LD A, (nn)

A+- (nn)

Load ACC with location nn

3

13

to A, R

A-R

Load ACC With location (BC)

Load ACC With Reg. R

2

9

LD IBCI, ~

IBCI- A

LD IDEI, A

·(OE1- A

LD iHLI, n

IHLI- n

Load location (HL) With value n

2

10

LD 55, nn

55 ...... nn

Load Reg. pair S5 with value nn

4

20

LD HL, (nn)

H ..... (nn + 1)
L .... (nn)

Load location (BCI With ACC

1

7

ACe

1

7

Load locatIOn (DE) with

Load HL with location (nn)

3

16

LDIHLI.'

IHLI· ,

Load location (HU With Reg. r

1

7

LD I, A

I·, A

Load I with ACC

2

9

LD IX, nn

IX ...... nn

Load IX With value nn

4

19

LD IX, (nn)

IX H ...... (nn+l)
IX L .... (nn)

Load IX with rocation (nn)

4

20

LD(IX+d),n

(IX +d) ...... n

Load location (IX + d) with value n

4

19

LD (IX +dl, r

178

(IX + d) ..... r

Load location (IX + d) with Reg. r

3

19

C

Z

FLAGS
PIV S,

OPCODE
N

H

76 543 ,210

·
·
·
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
· · · · · ·•
·· ·· ·
·· ·· ··
·· ·· ··
··· ·· ·· ·· ·· ··
·· ·· ··
·
··· ··· ··· ··· ··· ···
·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
1

X

X

1

X

11 101
10 111

IG) X

X

1

X

11 101 101
10 100 010

1

X

1

X

11 101 101
10 110 010

X.

:

I

I

IFF

IFF

I

I

0

0

0

0

101
010

11

101

11
11

011 ,10)
101 001

11
11

111
101

001

101
001

11 +-cc- 01O®
nn
nn

nnn
nnn

nnn
nnn

11

000 011

nn
nn

nnn
nnn

nnn
nnn

00 111

000

~e-2~

00 Oil

000

~-2~

00 110 000
...........e-2~

00 100 000
~e-2--...

00 101

000

~e-2~

00 001

010

00 Qll

010

11 ,101 101
01 010 111
00 111

010

nn
nn

nnn
nnn

nnn
nnn

11
01

101
011

101
111

00 000 010
00 010 010
00

110 110

nn

nnn

00

ssO

001@

nn
nn

nnn
nnn

nnn
nnn

nnn

00 101

010

nn
nn

nnn
nnn

nnn
nnn

01

110 ,,,@

11
01

101 101
000 111

11 011 101
00 100 001
nn
nn

nnn nnn
nnn nnn

11 all 101
00, 101 ,010
nn
nn

nnn
nnn

nnn
nnn

11 011 101
00 110 110
dd
~n

ddd ddd
nnn r,nn

11 011 101@
01 110
dd ddd ddd

'"

fLPD780
SYMBOLIC
OPERATION

MNEMONIC

OESCRIPTION

NO.
BYTES

NO. T
STATES

LD IV, nn

IV-nn

Load IY with value nn

4

14

LD IY, (nnl

1YH-(nn+1)
IY L -Innl

Load IV with location Inn)

4

20

LD

SSH +- (n~ +
sSL +- Inn)

Load Reg. pair dd with location (nn)

4

20

4

19

3

19

3

13

Load location (nn) with Reg. pair dd

4

20

(nn + 1)- H
(nn) +- L

Load location (nn) with HL

3

16

(nn + 1) -IX H

Load location (nn) with IX

4

20

(nn + 1) -IY H
(nn) +- IV L

Load location (nn) with IV

4

20

LOR,A

R-A

Load A with ACe

2

9

LOr,IHLI

r - (HU

Load Reg. r with location (HLl

1

7

LO r, IIX +dl

r+-(!X+d)

Load Reg. r with location OX + dl

3

19

LDr,(lY+d)

r - (lY+dl

Load Reg. r with location (lY + dl

3

19

LOr, n

r~n

Load Reg. r with value n

2

7

55,

(nn)

11

+ dl with

LD IIY + dl, n

(JY+d)-n

Load (ly

LDIIY+dl.r

(ly +d)-r

Load location (ly + dl with Reg. r

LO (nnl, A

(nn) -A

Load location (nn) with

LD Inn>.ss

Inn

+ 1) -+-:ssH

(nn)

LO (nn). HL

LO (nn), IX

+-

value n

Ace

sSL

(nn)""" IX L

LD (nn), IV

LD, r, r

r-r

Load Reg. r with Reg.

1

4

LD SP, HL

SP +- HL

Load SP with HL

1

6

LDSP, IX

SP-IX

Load SP with IX

2

10

LD SP, IV

SP-IV

Load SP with IY

2

10

LDO

IOEI- (HLI
DE-OE-l
HL+-HL·-l
BC ~ BC- 1

Load location (D E) wi th I ocat ion
(HL), decrement DE. HL and Be

2

16

LDDR

IOEI- (HLI
DE +- DE - 1
HL-HL-l
BC +- BC - 1 until BC = 0

Load location (DEI with location
IHLI

2

21

(DEI ~ (HLI
DE +- DE + 1
HL+-HL+ 1

Load location (DEI with location
(H Ll. increment DE, HL; decrement
BC

2

Load location (DEI with location
IHL), increment DE, HL: decrement
BC and repeat until BC = 0

2

Neg~te

2

LDI

16

BC~BC-l

LOIR

(OEI ~ (HLI
DE +- DE + 1
HL ~ HL + 1
BC +- BC - 1 until BC

NEG

A

~O-A

:=

21 if Be"40
16ifBC=Q

C

Z

FLAGS
P/V S

OPCOOE
N

H

·· ··
·· ··
·· ··
·· ··

··
··
··
··
·· ·· ··
· · ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
· · ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ··
·· ·
I

· · .. ·

· · dI) •
·· ·
0

76 543 210
11 111 101
00 100 001
nn nnn nnn
nn nnn nnn
11
00
nn
nn

111
101
nnn
nnn

101
010
nnn
nnn

11
01
nn
nn

101
ssl
nnn
nnn

101®
011
nnn
nnn

11 111 101
00 110 110
dd ddd ddd
nn nnn nnn
11
01
dd

111
110
ddd

101®
crr
ddd

00 110 010
nn nnn nnn
nn nnn nnn
11
01
nn
nn

101
ssO
nnn
nnn

101®
011
nnn
nnn

00 100 010
nn
nn

nnn
nnn

nnn
nnn

11
00
nn
nn

011 101
100 010
nnn nnn
nnn nnn

11 111 101
00 100 010
nn nnn nnn
nn nnn nnn
11
01

101
001

101
111

01

cr r

110®

11 011
01 rrr
dd ddd

101®
110
ddd

11 111 101®
01 " r 110
dd ddd ddd

,"

00
nn nnn

110®
nnn

01

,"

r'r'r'®

11

111

001

11
11

011
111

101
001

11
11

111
111

101
001

0

0

11
10

101
101

101
000

0

0

11

101
111

101
000

11
10

101

101
000

10

0

0

foo

0

0

11
10

101 101
110 000

1

!

11
01

101
000

0

ACe (2) complementl

8

!

I

V

I

101
100

179

II

INSTRUCTION SET TABLE
(CONT.)

ILPD780
SYMBOLIC
OPERATION

MNEMONIC

NOP
OR e
OR n
OR IHLI
OR IIX +dl

NO.
BYTES

DESCRIPTION
No operation

A· AVe
A· AV n

1

4
7

Logical 'OR' of lac. (HU and ACe
Logical 'OR' of lac. IIX +di A ACC

ORIIY+di

A·--AV(IY+d)

Logical 'OR' of lac. (IY + d) A ACe

OTDR

ICI~'

Load output port tel with contents

IHLI

B-1
1 until B 00

HL· Hl

7

21 If 8

of

16 If B

Load output port (el with location
{HLl, InCI"f!ment HL, decrement B,
I"cpeat until B -' 0

QUT(Cl.r

lei· e

L03d output port

2

(el With Reg. r

2

12

OUT {nl. A

(n) .

L08d output POrt (n) With ACC

2

11

ICi·- IHLI
B .- 8 -- 1
Hl· HL-l

Load output port (C) With location
(HL), Increment HL (O)

15<1>(0)

tdcl

Dala Siable from \IVA
--~

Anv !"lold Time for 'fietup Time

90

60

50

®
®

®
®

CL'" 200pF

~df
'H
IDl'I.(MR)

100

85

MAEO Delay from R,Sing Edge of Clock 10 MAEO High

'OH" MAl

100

85

MREO Delav from Failing Edge of Clock 10 MREO High

IOHli.(MR)

100

Pulse Width, ·MA EO low

IwtMAL)

®

Pulse Width, MREO High

IwtMRH)

®

lORa Delay from RISing Edge of Clock to IORO low

IDL'i,(JA)

90

lORa Delay from Falling Edge of Clock to IORO low

~D~I.(lR)

11Q

~5

IORq Delay from Rismg Edge of Clock to H)RQ High

IOH'HIRI

100

85

IOR9 Delay from Fallmg Edge of Clock to IORO High

IDHlli(IR)

1'10

85

AD Delav from RISing Edge of Clock to AD low

IDLI~tRO)

100

85

RO Delav from Fallmg:Edge of Clock to RD low

tDL'i'.(RO)

130

95

RO Delav from RISing Edge of Clock 10 RO High

'OHII'/RO)

100

85

85

@
@
75

RO Delay from Fallmg Edge of Clock to AO High

'OH'HRO)

110

85

WR Delay from Rlsmg Ed~ of Clock 10 WR low

'OL".{WR)

80

65

WR Oelav from Fallmg Edge of Clock to WR low

tOLII·/WR)

90

80

WR Delav from Failing Edge of Clock to WR High

tOHII'/WR)

100

Pulse Width to WR Low

IwtWRL)

MI Delav from RISing Edge of Clock to'MI low
RI~lOg

Edge of Clock to MI High

RFSH Delay from R"lsing Edge of Clock to AFSH Low

IDUM!)

~ 30

100

10H(MI)

130

100

'OLtAF)

180

130

'OH(AF)
IsIWT)

HALT Delay Time from Failing Edge of Clock

'O(HTI

INT Setup Time to RISing Edge of Clock

'sOT)

Pulse Width, NP4\1 Low
BUSRO Setup Time to R,slOg Edge of Clock

B"liSA"R Delay from

ICLlBA)

120

100

tDHtBA)

110

100

BUSAK Delay from Failing Edge of Clock to BUSAK High

150
300

300

'wINML)

80

80

's(90)

80

'sIRS}
IFtC)

FROM OUTPUT
UNDER TEST

= 50pF

Cl

= 50pF

60
100

' m,

Cl

50

90

@

= 30pF

120

80

Delay to Float /MREQ, lORa, RO and WR)

Cl

70

70

80

RESET Setup Time to Rlsmg Edge of Clock

= 50 pF

80

WAIT Setup Time to Failing Ed'ge of Clock

RISing Edge of Clock 10 BUSAK low

Cl

~

®I

RFSH Oelav from Rlsl'n'g Edge of Clock 10 RFSH High

MI Stable Prior to IORO {lnterrupi Ack.l

80

@

o----r---+----l4f---4

·These values apply to the .I.IP0780"

!-OAD CIRCUIT FOR OUTPUT
"

172

50pF

150

MREO DeiaV from Failing Edge of ~Iock to MAEQ low

MI DeiaV from

~

CL

35

50

,Idem

Data Siable Prior to WA "(I/O Cvcle)

90

(j)

Delay to Float DUring Write Cycle

CONDITIONS

2000

30

(j)

teaf

Data Stable Prior to WR, (Memorv Cycle)

110

145

Data D(Jfput Delay

Dala Setup Tune to Failing Edge of Clock Durmg M2 to M5 Cycles

TEST

,uPD780-1

SYMBOL

t\'EC
NEe Microcomputers, Inc.

fL PD8080AF
fL PD8080AF·2

fL PD8080AF·1
fLPD8080AF 8·BIT N·CHANNEL
MIROPROCESSOR FAMILY

DESCRIPTION

FEATURES

The .uPD8080AF is.a complete 8-bitparallel processor for use in general purpose
digital computer systems_ It is fabricated on a single LSI chip using N-channel silicon
gate MOS process, which offers much higher performance than conventional microprocessors (1-28 fJ.S minimum instruction cycle). A complete microcomputer system
is formed when the .uPD8080AF is interfaced with I/O ports (up to 256 input and 256
output ports) and any type or speed of semiconductor memory. It is available in a
40 pin ceramic or plastic package.
•

•

•
•
•
•
•
•
•
•

PIN CONFIGURATION

78 Powerful Instructions
Three Devices - Three Clock Frequencies
.uPD8080AF - 2.0 MHz
fJ.PD8080AF-2 - 2.5 MHz
.uPD8080AF-l - 3.0 MHz
Direct Access to 64K Bytes of Memory with 16-Bit Program Counter
256 8-Bit Input Ports and 256 8-Bit Output Ports
Double Length Operations Including Addition
Automatic Stack Memory Operation with 16-Bit Stack Pointer
TTL Compatible (Except Clocks)
Multi-byte Interrupt Capability
Fully Compatible with I ndustry Standard 8080A
Available in either Plastic or Ceramic Package

AlO
VSS
04
05
06
07
03
02
01
00
VBB
RESET
HOLO
INT
<1>2

INTE
OBIN
WR
SYNC
VCC

3
4
5
6
7
8
9
j.tPD
10
118080AF
12
13
14
15
16
17
18
19
20

25

All
A14
A13
A12
A15
A9
A8
A7
A6
A5
A4
A3
VOO
A2
Al
AO
WAIT
REAOY

I

<1>1

21

HLOA

Rev/1

183

fLPD8080AF
The IlPD8080AF contains six B-bit data registers, an 8-bit accumulator, four testable
flag bits, and an 8-bit parallel binary arithmetic unit. The IlPD8080AF also provides
decimal·arithmetic capability and it includes 16-bit arithmetic and immediate operators
which greatly simplify memory address calculations, and high speed arithmetic
operations.

FUNCTIONAL,
DESCRIPTION

The IlPD8080AF utilizes a 16-bit address bus to directly address 64K bytes of
memory, is fully TTL compatible (1.9 mAl, and utilizes the following addressing
modes: Direct; Register; Register Indirect; and Immediate.
The IlPD8080AF has a stack architecture wherein any portion of the external memory
can be used as a last in/first out (U Fa) stack to store/retrieve the contents of the
ac;cumulator, the flags, or any of the data registers.
The IlPD8080AF also contains a 16-bit stack pointer to control the addressing o.f this
external stack. One of the major advantages of the stack is that multiple level interrupts can easily be handled since complete system status can be saved when an interrupt occurs and then restored after the interrupt is complete. Another major advantage
is that almost unlimited subroutine nesting is possible.
This processor is designed to greatly simplify system design. Separate 16-line address
and a-line bidirectional data busses are employed to allow direct interface to memories
antll/O ports. Control signals, requiring no decoding, are provided directly by the
processor. All busses, including the control bus, are TTL compatible.
Communication on both the address lines and the data lines can be interlocked by
usjng the HOLD input. When the Hold Acknowledge (HLDA) signal is issued by the
J~ocessor, its operation is suspended and the address and data lines are forced to be in
the FLOATING state. This permits other devices, such as direct memory access channels (DMA), to be connected to the address and data busses.
The IlPD8080AF has the capability to accept a multiple byte instruction upon ~n interrupt. This means that a CALL instruction can be inserted so that any address in the
memory can be the starting location for an interrupt program. This allows the assignment of a separate location for each interrupt operation, and as a result no polling is
required to determine which operation is to be performed.
NEC offers three versions of the IlPD8080AF. These processors have all the features
of the IlPD8080AF except the clock frequency ranges from 2.0 MHz to 3.0 MHz.
These units meet the performance requirements of a variety of systems while maintaining software and hardware compatibility with other 8080A devices.
AS

a-I!s

(THREE STATE)

AB _

LATCH

·BUFFER

a IN/OECREMENTER
PC (161

SP (l6)
TIMING aCONTROl

lIB)-

STATE CNTR

LIS)

DECODER

FLAG REGISTER
BIT 1- S:SIGN
BIT 6 - Z:ZERO

81 T 5 - O.ALWAYS·O"
All 4 - ACY'AUXILIARY CARRY

BIT 3- 0" AlWAYS·O"
81T 2- P:PARITY
BIT I -1.ALWAYS "1"
BITO-CV'CARRY

184

-TEMPORARY REGISTER
080-1 \THREE STATE I

BLOCK DIAGRAM

ILPD8080AF
PIN IDENTIFICATION

I

PIN
NO,

SYMBOL

1,
25-27,
29-40

A15 - AO

NAME

FUNCTION

Address Bus
(outpu't threestate)

or specify the I/O device number (up to 256 input and 256 output
devices). AO is the least signifi_cant bit.

The address bus is used to address memory (up to 64K 8-bit words)

2

VSS

Ground (input)

Ground

3-10

D7 - DO

Data Bus (input/
output three-state)

The bidirectional data bus communicates between the processor,
memory, and I/O-devices for instructions and data transfers. During each sync time, the data bus contains a status word that
describ~s the current machine cycle. DO is the ,least significant bi~,.

11

VBB

VBB Supply Voltage
(input)

-5V ± 5%

12

RESET

Reset (input)

If the RESET signal is activated, the program counter is cleared.
After RESET, the program starts at location 0 in memory. The
INTE and HLDA flip-flops are also reset. The flags, accumulator,
stack pointer, and registers are not cleared. (Note: External synchronization is not required for the RESET input signal which
must be active for a mi'nimum of 3 clock periods.)

13

HOLD

Hold (input)

HOLD requests the processor to enter the i~OLD state. The,HOLD
state allows an external device to gain control of the ,uPD8080AF
add((,!ss and data buses as soon as the ,uPD8080AF has completed
its use of these'buses' fo-r the current machi ne cycte. It is recognized under the ,following conditions:
The processor is in the HA LT state.
The processor is in the T2 or TW stage and the READY signal
is active.
As a result of entering the HOLD state, the ADDRESS BUS
(A15 - AO) and DATA BUS (D7 - DO) are in their high imped·
ance state. The processor indicates its state on the HOLD

··

ACKNOWLEDGE IHLDA) pin,
14

INT

15

1>2

16

INTE

17

DBIN

CD

Interrupt Request
(input)

The }1PD8080AF recognizes an interrupt request on this line at
the end of the current instruction or while halted. If the
J1PD8080AF is in the HOLD state, or if the Interrupt Enable
flip-flop is reset, it will not honor the request.

Phase Two (input)

Phase two of processor clock.

Interrupt Enable
(output)

INTE indicates the content of the internal interrupt enable flip;flop. This flip-flop is set by the Enable (EI) or reset 'by the
Disable (01) interrupt instructions and inhibits interrupts from
being accepted by the processor when it is reset. INTE is automatically reset (disabling further interrupts) during T 1 of the
instruction fetch cycle (M 1) when an interrupt is accepted and
is also reset by the RESET signal.

Data Bus In
(output)

DBIN indicates that the data bus is in the input mode. This

sign~t'is used to enable the gating of data onto the J1PD8080AF
data bus from memQry or input ports.

18

WR

Write (output)

WR is used for memory WRITE or I/O output control. The data
on the data bus is valid while the iNA signal is active (WR "" 0).

19

SYNC

Synchronizing Signal
(output)

The SYNC s..ignal indicates,the beginning of each machine cycle.

20

VCC

VCC Supply

+5V ± 5%

Voltage (input)
21

HLDA

Hold Acknowledge
(output)

HLDA is in response to the HOLD signal and indicates that the
data and address bus will go to the high impedance state. The
HLDA signal begins at:
T3 for READ memory or iriput operations.
The dock period following T3 for WR ITE memory or
OUTPUT operations.
In either case, the HLDA appears after the rising edge of ¢1 and
high impedance occurs after the rising edge of 412.

··
22

1>1

Phase One (input)

Phase one of processor clock.

23

READY

Ready (inpu:t)

The READY signal indicates to the ,uPD8080AF that valid memo
ory or input d,ata is av:aila,ble on the ,Ll~D8080AF data bus.
READY is used to synchronize the processor with slower memory
or I/O devices. I(after sending an address out, the ,uPD8080AF
does not receive a high on the READY prn, the J1PD8080AF enters
a WAIT state for as long as the READY pin is low. (READY can
al,so be used to single step the processor.)

24

WAIT

Wait (output)

The-WAIT signal indicates that the processor i's in a'WAIT state.

28

VDD

VDD Supply Voltage
(input)

+12V ± 5%

Note:

-



u

>-

..J

it
:>

'"

0.5 .....- - - - - - L - - - - ' - - - - - '
+75
+50
o
+25
AMBIENT TEMPERATURE rei
Notes:

 VIH

internal active 'pull-up resistors will

be switched onto the data bus.

@ Minus (-I designates c'urrent flow out of the device.
@ .0.1 supply/aTa = -0.45%/"C.

.

CAPACITANCE

Ta = 25°C, Vee = VDD = VSS = OV, VBB = -5V.
LIMITs
PARAMETER

186

Clock Capacitance
Input Capacitance
['Output Capacitance

SYMBOL
C¢
CIN
GoUT

MIN

TYP MAx
17

6
10

25
10
20

UNIT TEST CONDITIONS
',pF
pF
pF

Ie = 1 MHz
Unmeasured Pins
Returned to Vss

PROCESSOR STATE
TRANSITION DIAGRAM

fLPD8080AF

RESET

I
I·

I
I

:0

I HOLD
I MO·DE

I
I
I
'-----U~--'......-- - - .J
RESET HLTA

II
Notes:



Q)

INTE F/F IS RESET IF INTERNAl, INT F/F IS SET.
INTERNAL INT F/F IS RESET IF.JNTE F/F IS RESET.'
IF REQUIRED. T4 AND T5 ARE·COMPLETEDStMULTANEOUSLY
WITH ENTERING ROlD STATE.

187

}LPD8080AF
T a'" O°C to +70°C, VOO '" +12V ± 5%, Vee = +5V ± 5%, VSB = -5V ± 5%, VSS '" av. unless otherwise
specified.
LIMITS
PARAMETER

SYMBOL

MIN

MAX

UNIT

0.48

2.0

,Msec

Clock Rise and Fall Time

'CY@
tr,tf

TYP

0

50

nsec

1>1 Pulse Width

'2· Leading Edge~
Del~y

nsec

'OA@

200

nsec

Data Output Delay From 1>2

'OO@

220

nsec

Signal Output Delay From 1>1,
or 2

OBIN Delay From 1>2

'OF @

"'

25

120

nsec

140

nsec

'OF

nsee

CL" 100 pF

CL" 50 pF

Delay for Input Bus to Enter

CD

Input Mode

'01

Data Setup Time During 1>1 and
OBIN

'OS1

30

osee

'DS2

150

nsee

Data Setup Time to <1>2 Dur.!ng
OBIN
Data Hold Time ·From 112 During
OBIN

'OH

INTE Output Delay From 1>2

'IE@

READY Setup Time During t/>,2

'RS

120'

nsec

CD

CD

nsec
200

nsec

HOLD Setup Time to 4>2

'HS

140

nsee

INT Setup Time During c/l2
(During ¢1 in Halt Mode)

'IS

120

nsee

Hold Time from led with DBIN status, No bus conflict can then occur and data hold time
is assured. tOH "" 50 ns or tOF, whichever is less.
+5V

@ Load Circuit.

2.1K

e-____e-__~(~__-+

~P08080AFo-__

OUTPUT

@ Ac'ual 'CY " '03 + 'r

'CY Min.

TYPICAL A OUTPUT DELAY VS.
A CAPACITANCE
+20

]
r

j

+10

w
0
~

0

~
~

:0

0

"

-10

/

20
-100

/
-50

~

/

'-SPEC

o

+50

.6. CAPACIT ANCE
(CACTUAL -

188

(pf)

CSPEC)

+100

AC CHARACTERISTICS

J.LPD8080AF

fLPD8080AF
AC CHARACTERISTICS
IlPD8080AF-2

Ta

= O°C to +70°C, Vbo = +12V

± 5%,

Vee = +SV

±

5%,

Vas = -5V ±

5%, VSS = OV. unless otherwise

specified.

-'
LIMITS
P)\RAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Clock Pertb_1 Pulse Width

t¢1

0
60

¢2 Pulse WJdth

t¢2

175

osec
nsec
nsec

Delay rj) 1 to 4>2

tOl
t02

0
70

nsec
nsec

Delay t/>l.to ¢2 Leading Edges

t03

70

Address Output Delay From rp2

tOA@
too@

Delay (/>2 to 411-

Data Output Delay From {/J2

TEST CONOI,TIONS

nsec

175

j1sec

200

nsec

120
140

"sec

tOF

osec

CL

= 100 pF

CL

= 50 pF

CL

= 50 pF

CL

= 100 pF': Address,

CL

~

Signal Oytput Delay From cbl,

or ¢2 (SYNC, WR, WAIT,
HLOA)
2
Delay for Input Bus to Enter
Input Mode

toc@
tOF@
tOI

25

CD

nsec

Data Setup Time During ¢1 and

OBIN

tOSl

io

osec

Data Setup Time to t/>2 During
OBIN

tOS2

130

nsec

Data Hold Time From ¢2 During

..-

CD

CD
90

osec
osec
osec

HOLD Setup Time to ¢2

'IE,@
'RS
tHS

120

nsec

tNT Setup Time During f/>2
(for all modes)

tiS

100

nsec

INT, HOLD)

tH

0

nsec

Delay to Float During Hold
(Address and Data Bus)

tFO

OBIN

tOH'

INTE Qutput Delay From ¢2

R EADY· S~tupTi~;D~ri~-g -~2" ..

200

Hold Time from c/J2 (READY,

120

nsec

'Output Da.ta Stable F~~m WA'

®
®

nsec

Output pata S.table Prio~ to WR

iAW@
tow@
two@

nsec

Addres$:Stable from.WR
H LD,A to Float Delay

tWA ®
tHF@

(J)
(J)

nsec

WR to Float Delay

tWF

®

®
®

Address Hold Time flfter DBIN
during HLDA

tAH

®

-20

Address Stable Prior to WR

Notes Continued:

@

nsec
Data

nsec

nsec

50 pF: WR,
HLOA,OBIN

nsec
.

The ,f.ollowing are releVant when interfacind

the ~PD8080AF to devices having VIH = 3.3V.

a. Maximum ~utPut rise time from 0.8" to 3.3\' = 100 ns at CL = SPEC.
b. Output delay when measured to 3.0V = SPEC +60 ns at CL = SPEC.

c. If CL '" SPEC, add 0.6 ns/pF if CL
CL < CSPEC.

> CSPEC, subtract 0.3 ns/pF

II

(from modified delav) if

189

f'PD8080AF
T a '" aOc to +70°C, VOO '" +12V ± 5%, Vee
specified.

=

+5V ± 5%, VSS = -5V ± 5%, VSS == OV, unless otherwise

LIMITS
PARAMETER

SYMBOL

MIN

MAX

UNIT

2.0

,usee

25

nsee

'CY@

0.32

Clock Rise and Fall Time

tr,tf

0

1>1 Pulse Width

'<1>1

(/)2 Pulse Width

'<1>2

Delay c,bl to rp2

Delay t:f;J2 to 1>1

Clock Period

Delay ¢1 to

cP2 Leading Edges

cp2

Address Output Delay From

TYP

50
" 145

nsee

'01

0

nsee

'02

60

nsee

'03

60

nsee

nsee

<%>
'00 <%>
'OA

Data Output Delay From cp2

TEST CONDITIONS

150

nsee

180

nsee

110

nsee

130

nsee

'OF

nsee

CL· 50 pF

Signal Output Delay From 1,

<1>2 (SYNC, WR, WAIT,
HLOA)

0'

'oc
'OF

<%>
<%>

Input Mode

'01

CD

Data Setup Time During 4>1 and
OBIN

'OSl

10 "

nsee

Data Setup Time to 1>2 During
OBIN

'OS2

120

nsee

DB I N Delay From 1J2

25

CL· 50 pF

Delay for I nput Bus to Enter

Data Hold Time From $2 During

'OH
'IE @

CD

INTE Output Delay From 2 (READY,
INT, HOLO)

r----r""

nsee

nsee

'FO

Address Stable Prior to WR

'AW@

®

nsec

Output Data Stable Prior to WR

'OW@

®

nsec

Output Data Stable From WR

'wo0

nsec

Address Stable from WR

'WA

0

Q)
(J)

0

120

nsec

nsec

HLOA to Float Delay

'HF

®

nsec

WR to Float Delay

'WF @

(~)

nsec

Address Hold Time after OBIN
during HLDA

'AH @

-20

nsec

®

~P08080AF-2
~P08080AF-l

CL· 50 pF: WR,
HLOA,OBIN

2'~ - '03 - 'r2 - 140
2 'CY - '03 - 'r¢2 - 130
110
2,CY '03 'r2
tow

Device
~P08080AF

MP08080AF-2
~P08080AF-l

CL=50pF: Address,
Data

tAW

Oevice
~P08080AF

®

CL - 50 pF

nsee

Delay to Float During Hold
(Address and Data Bus)

Notes Continued:

190

nsee
200

'CY - '03 - "<1>2 - 170
70
'CY '03 ',2 + 10 ns, If HLOA, 'wo • twA •

(j)

If no' HLOA,

®
®

'HF· '03 + 'r2 - 50 ns.
'WF· '03 + "<1>2 - 10 ns,

'WF·

AC CHARACTERISTICS
MPD8080AF-1

TIMING WAVEFORMS

0

(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = B.OV,
"0" = 1.0V; INPUTS "1" = 3.3V, "0" = O.BV; OUTPUTS "1" = 2.0V, ".0" = O.BV.)

- .... r

~~'eY-h

"

..

~

"t

1-'0,-1

'0'

-

A,.....

'I

D 7 .[)O

IT

SYNC

_

-----

-I to: 1_

' 01

I~

~

DU ~

t

.~

--I'wA

f-tow

I :----/...D

~

!

1
_tof--l

-----------

I

'I

i

I'
"t

------------

r::
tH-

_

I~e ~

!

'RS'

'oe-

toe

~I

!I

r
.
1..'.
'1.... :, . '
__ tH

,.

I-..

II:

Y0 T

HOLD

~r

-:-

"-'I'

-tAS~'
HLDA

-

'NT

I

... 'HF ....

. ,.

I .

- toe

.

l:01Y

.t';~T

l-t":L

._~?-~~-.----...,..----

1 • SYNC of each machine cycle, a status word that identifies the
type of machine cycle is available on the data bus.
Execution times and machine cycles used for each type of instruction are shown
below.
CLOCK TIMES
(MIN/MAX)

MACHINE CYCLES EXECUTED

INSTRUCTION
RST X and PUSH RP

PCR5

CD

SPW3

®

SPW3

®

All CALL Instructions

PCR5

CD

PCR3

PCR3

Conditional TURN

PCR5

G)

SPR3

@
@

@
@

A ET Instruction

PCR4
PCR4

CD
CD

SPR3

XTHL
DAD RP

PCR4

(j)

PCX3

INR R; INX RP, OCR R;
DCX RP; PCHL;
MOV R, R; SPHL

PCR5

CD

All JUMP Instructions

PCR4

CD

PCR3

(1) PCR3 (1)

POP RP

PCR4

@

SPR3

@

PCR4

PCR3

@

PCR3

@

PCR4

PCR3

PCR3

BBW3

@

LHLD

PCR4

@

BBR3

@

16

PCR4

@
@

BBR3

SHLO

BBW3

@

BBW3 (])

16

STAX B

PCR4

STAX 0

PCR4

LDAX 8

PCR4

G)

BCR3

LDAX 0

PCR4

(j)

DER3

@
@
@
@
@
@
@

@
@

BBR3

STA

CD
CD
CD
CD
CD
CD
CD

SPR3

LOA

MDV R, M; ADD M;
ADC M; SUB M; SB 8 M;
ANAM;XRAM;
ORAM;CMPM

PCR4

(J) H LR 3

C3>

SPR3

11
SPW3

(§) SPW3 (§)

11/17
5/11

Instructions

,nd LXI RP

SPR3

@
@

®

@)
@
PCX3 QS)

10

SPR3
SPR3

SPW3

®

SPW5

®

18
10

5

PCR3
PCR3
BCW3
DEW3

PCR3
PCR3

10
13
13

7
7
7
7
7

INR M and OCR M

PCR4

CD

HLR3@ HLW3

MVIM

PCR4

CD

PCR3

@

MVI R; ADI; ACI; SUI;
SBI;ANI; XRI;ORI; CPI

PCR4

(J) PCR3

C3>

MOV M, R

PCR4

CD

(;l)

EI; 01 ADD R;
ADC R; SU8 R;
S88 R; ANA R; XRA R;
ORA R; CM? R; RLC;
RRC; RAL; RAR;
DAA; CMA; STC;
CMC; NOP; XCHG

PCR4

(J)

OUT

PCR4

IN

PCR4

HLT

PCR4

(j)
(j)
(j)

H LW3

10

HLW3

@

10

(;l)

10
7
7

4

PCR3
PCR3
PCX3

@
@

ABW3

fJ)

10

ABR3

@

10

®

l

7

Machine Cycle Symbol Definition

Tp :1
XX Y Z

@ .. Statusword defining type of machine
0

XX

HL

... ,,",., W
...this
" .machine
,"
,
Number
of' clocks
for
cycle - " DE
R :. Read cycle - data into processor
Sp
W = Write cycle - data out of proces.,sor
B6

X

'" No data transfer

PC

=

AB

Registers Hand L used as address
Registers Band C used as address
Registers D and E used as address
Stack Pointer used as address
Byte 2 and 3 used as address
Byte 2 used as address

Program Counter used as address

Underlined (XXYZ@) indicates machine cycle is executed if condition is True.

194

INSTRUCTION CYCLE
TIMES

p.PD8080AF
STATUS INFORMATION
DEFINITION

INTA

DEFINITION

DATA BUS BIT

SYMBOLS

or ft,,·
G)

Input frequency must be twice t,he

,·6 MHz> 50% DC

II

int~rnal operating frequency.

The Status Outputs are valid during ALE time and have the following m~aning:

Halt
Write
Read
Fetch

S1

SO

0
0

0
1

0

These pins may be decoded to portray the processor's data bus status.

203

fLPD8086A

The MPDa085Ahas five interruptpins available.t9·~he user. INTR is operationally the
same as the 8080 interrupt request, three (3) internally maskable restart interrupts:
RESTART 5.5, 6.5 and 7.5, and TRAP, a nonmaskable restart.
RESTART
ADDRESS

INTERRUPT

PRIORITY
Highest

INTERRUPTS

TRAP

24 16

I

RST 5.5

2C16

I

RST 6.5

34 16

I

RST 7.5

3C16

INTR

Lowest

INTR, RST 5.5 and RST 6.5 are all level sensing inputs while RST 7.5 is set on a rising
edge. TRAP, the highest priority interrupt, is nonmaskable and is set on the rising edge
or positive level. It must make a low to high transition and remain high to be seen, but
it will not be generated again until it makes another low to high transition.
Serial input and output is accomplished with two new instructions not included in the
8080: RIM and SIM. These instructions serve severalpurlloses: serial I/O, and reading
or setting the interrupt mask.
The RIM (Read Interrupt Mask) inStruction is used for reading the interrupt mask and
for reading serial data. After execution of the RIM instruction the ACC content is as
follows:

I I /5 6~5 I 5~5 I
SID

SERIAL
DATA
IN

IE

I

I

PENDING
INTERRUPTS

INTERRUPT
. MASKS
INTERRUPT
ENABLE

Note: After the TRAP interrupt, the R 1M instruction must be executed to preserve the
status of IE.
The SIM (Set Interrupt Mask) instruction is used to program the interrupt mask and to
output serial data. Presetting the ACC for the SIM instruction has the following
meaning:

I

SERIAL
OUT
DATA
SERIAL
OUT
DATA
ENABLE
(1 = ENABLE)

204

M

M

6.5

5.5

I I
I

I

RESET
RST7.5
ENABLE

RST
MASKS
(1 = SET)

MASK
SET
ENABLE
(1 = ENABLE)

SE RIAL I/O

,",PD8085A

INSTRUCTION SET

The instruction set includes arithmetic. and logical operators with direct, register,
indirect, and immediate addressing modes.
Move, load, and store instruction groups provide the.ability -to move either 8 or 16 bits
of data b~tween memory, the six working registers and the accumulator using direct,
register,indirect, and immediate addressing modes.

con-

The ability to. branch to different portions of the program is provided with direct,
ditional, or computed jumps. Also, the ability to call and return from suhroutines is
provided both conditionally and unconditionally; The R.f:START(or single byte call
instruction) is usef!.!1 for interrupt vector oP!lration.

Conditional jumps, calls and returns execute based on the state of th.e four testable
flags (Sign! 'Zero, Parity and Carry). The state of each flag i$ determined by the result
of the lasfinstruction executed that affected flags. (Se~ Instruction Set Table.)
The Sign flag is set (High) if bit 7 of the re;ult is a "1"; otherwise it is reset (Low). The
Zero flag is set if the result 'is "0"; otherwise it isre~et; The Parity flag is set if the
modulo 2 sum of the bits of the result is "O"(Even Parity); otherwise (Odd Parity) it
is reset. The Carry flag is set if the last instruction resul'ted in a carry.or a borrow out
of the most significant bit (bit 7) of the result; otherwise it is reset.
In addition to the four testable flags, the tLPD8085A has.another flag.(ACY) that is.
not directly testable. It is used for multiple precision. a'rithmetic operations with the
DAA instruction. The Auxiliary Carry flag is set if the last instruction resulted in a
carry or a borrow from bit3 li1to bit'4;.otlierwise it is reset ..
Double precision operators such as stack manipul~tion arid double add instructions
extend both the arithmetic and interrupt handling capability of ~he tLPD8085A. The
ability to increment and decrement memory, the six general registers arid the accumulator are provided as well as extended increment and decrement instructions to
operate on the register pairs and stack pointer. Further capability is provided by the
ability to rotate the accumulator left or right through orar()und the carry ~it.
Input and output may be accomplished using memory addresses as I/O ports or the
directly addressed I/O provided for in the tLPD8085A instructi~n's~t.
Two instructions, RIM and SIM, are used for reading and setting the internal interrupt
mask as well as input and output to the serial I/O port.
.
The special instruction group completes thetLPD8085A instruction set: NOP, HALT
stop processor execution; DAA provid~s decimal arithmetic capability; STC sets the
carry flag; CMC complements it; CMA complements the contents of the accllmUlator;
and XCHG exchanges the contents of two 16-bit register pairs directly.

DATA AND INSTRUCTION
FORMATS

Data in the tLPD8085A is stored as 8-bit binary integers. All data/instruction transfers
to the system data bus are in the following forlTlat:

1071061051041031021011001
MSB

DATA WORD

LSB

Instructions are one, two, or three bytes long. Multiple byte instructions must be
stored in successive locations of programmem·ory. The address of the first byte is used
as the address of the ins~ruction.
One Byte Instructions

- TYPICAL INSTRUCTIONS·

Register to'register, memory
reference, arithmetic or logica,

Two By-te Instructions

1071 061 051 041 03 1021 011001OP COOE
107.1061051041031021011001 OPERANO

rotate, return, push, poP. enable,
or disable, inte~r'upt instructions
Immediate mode or I/O instruc-

tions

Three Byte Instructions'

I D71 061 051 04 103 102 I 01 I DO I QP CODE ~~o~~;~s~I:~~~.!~:ct load aAd

1071 06105104 103 102101 100 1LOW AOORESS OR OPERANO 1
1071 06 105104 103 102101 1001 HIGH AOORESS OR OPERANO 2
205

II

p.PD8085A
INSTRUCTION SET
TABLE

INSTRUCTION

Clock

MNEMONIC'

DESCRIPTION

0, 06 Os 04 03 02 0,

Do • Cyctts3

MNEMONIC1

DESCRIPTION

MOVE

d

MOVd,s

Mov8,egl$1erl0reQ,ner

0

I

Move reglstar to memorv.

0

I

MOV d,M

Move memorv 10 regIster

Old

d

1

1

0

MVI d,Da
MVI 1.1,08

Move ,mmed,ate to reglsler
Move ,mmedla's 10 mamo.y

0
0

d
0

1
1

1

0

d
1

d

d

1

0

d
1

LXIB,DIS

Inc.emenlregnt&r
Decrement regliter
Incrementmemorv

o

0

'd

0
0

0
a

d
1

1
d
1

d
0

lXI 0,016
10

0

LXI H.Dt6

LXI SP,016

0

1
1

APes

ORAs
CMPs

Addmemorv toA

Cvdes3

1

0

0

0

1

0

0

0

o

0

0
1

o

PUSH H
S

Load ,mmed,ate register
paIr DE
Load ,mmedrate regIster
palrHL
l08d Immed'BIe Slack
Poonter

o

0

0

0

0

0

0

I

10

o

0

0

1

0

0

a

1

10

o

0

1

0

0

a

0

I

1

0

0

0

I

PUSH

S

PUSH PSW

Push reglSterp,lIr BC
on slack
Push registe.p;l1f DE

12

I

0

0

0

I

0

I

I

0

I

0

I

0

I

1

0

0

I

0

1

o

1

12

10

PUSh register Pill' HL
on slack
Push Aandflagsonstack

"

POP

o

o

1

1

0

1

0

1

1
1

0
0

1
1

1

0

POPB
POP 0

PopreglSterP!ltr BCoff
(cluSlYa OR Immedlale

ORI08
CPI08

OR ,mmed,ate With A
Compare Immediate wuh A

•

1

1

ALU

0'0

0
1

1
0

1
0

1
,1

1
1

0
0

1

0
1

1
0

I

I
I

0
0

1

0

0
0
0

0
0
\

0
1
0

1
I
1
1

10
10
10
10

INCREMENT REGISTER PAIR

O~--------------------------------------------------~
INX B
INX D

r---------------~A~LU~-~,M~M~ED~,.~T7E~TO~A~C~CU~M~U~LA~T=OR~---------------; :~~~
1

0
0
0

Inc.ement BC
l"c.ememOE
Inc.eme"t HL
lnc.reme",StackPom'er

o
o
o
o

0

0

0

0

0

0
0

0
1

1
0

0
0

0
0

0

1

1

0

0

1

1

DECREMENT REGISTER PAIR

DCX
DCX
DCX
DCX

B

0
H

SP

Decremen' ~C
Decrement DE
Decreme,,' HL
Dec.ementS,ackPomler

o
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

1

0

I

I
1

REGISTER INDIRECT
•

0

STAX B
STAX 0
LDAX B

Siore A at
Sto,e A at
LOijd A a'
LOtpressu:!:n, or
constant. always 8382 of InstrucllO"
AOOR ~ 16-b.' Memorv address up'esslo"

2ddqorsss 0008 OOlC-OIOD-OlIE·
lOlL -110Memorv - III A
3Two pOlslble cvcle limes (1/101 tndlC
RST
LD.A
STA
LHLD
. SHLD
XTHL
CALL

4

1
.1

4
4

1
1

4

.1
1

\

1
1
1
1
1
1
1
1
1
1
1
1
1
1/3
1
2
2
2/3
2

.

2

..

2
2
.2
2/5
3
3
3
3
3
3
3
3
3
3
3
3

4
4
5
5
5
5

CLOCK. STATUS
MIN/MAX

\

.

4
4
4
4
4
4

4
4
4
4
4
5
6
6
6
6/12
6
7
7
7/10
7
7
7
7
7
9/18
10
10
10
10
10
10
10
10
10
10
12
12
13
13
16
16
16
18

II

207

JLPD8QI5A

IlPD8085AC~~TLI N E
PACKAGE

208

ILPD8085A
IlPD8085A FAMILY MINIMUM
SYSTEM CONFIGURATION

A minimum computer system consisting of a processor, ROM, RAM, and
I/O can be built with only 3-40 pin packs. This system is shown below with
its address, data, control busses and I/O ports.

Vcc
INTERRUPTS

I

I! i !

~I

RST 7.5 AST 6.5 RST 5.5 TRAP

5

~

rl

RESET IN

PORTe

~ t tt

SID

SOD

81 SO

11

PORTS

111 11111111 11
PcO

PAO - - - - -- PA7

-

ill1Wi
-

--PC 5 PBo

- PB7

TIMER

1--1 N

x,
I-

.uPDS085A PROCESSOR

,uPD8156 RAM-I/O (256 X 8)

:::J

0

I-

X2

0

w
roo >
 grou nd potential.

XTAL1

One side offrequency source,input using resistor,
inductor, crystal or external source. (non-TTL
compatible VIH).

1·2,
26-27

15

,

' Testable'input using transfer functions JT1 and JNT1.
T1 can be made the counter/timer input using the ..
STRT CNT instruction. T1 also provides zero-cross
sensing fori ow· frequency AC"input signals.

,

AC CHARACTERISTICS

"

16

XTAL2

The other side, of frequency source input.

17

RESET

RESET ,initializes the processor, setting program
counter to zero and clearing status flip·flops.

18-25

P10-P17
(Port 1)

Tbe sec;ond of.~o 8-bit quasi bi,directiQnal I/O ports. '

28

Vce

+5V power supply input.

.- T a = Cfc to +7Cfc; Vcc

= 5.5V

± 1 V; VSS

= OV
LIMITS

SYMBOL'

PARAMETER

Cycle Time

TCY

Oscillator Frequency Variation
(Resistor Mode)

"F

MIN.
10.0
-20

TYP

MAX
50.0
+20

UNIT

TEST CONDITIONS

MS"

3 MHzXTAL =

%

F = 25 MHz-----~DATA VALID

..."

WRITE OPERATION - DATA BUS BUFFER REGISTER
SYSTEM
ADDRESS BUS

WR

DATA.US
(lNPUTI

220

WRITE CONTROL

--=====-- r-""';;;=-=;;';;"--"'[ '--"':;;''';'''';''''''';''''''';';''-DATA CAN CHANGE

DATA VALID

DATA CAN CHANGE

p.PD8041/8741
PACKAGE OUTLINE
pPD8041C/D
pPD8741C/D

~~~~_A-==--==-==-=:-t-h--r-I ~K~

~G'~~-

+~J\-

(Plastic)
ITEM

MILLIMETERS

A

51.5 MAX

B

C
'0
E

F

INCHES
2.028 MAX

1.62

0.064

2.54 ± 0.1

0.10* 0.004

0.5 ± 0.1

0.019 ± 0.004

48.26

1.9
0.047 MIN

G

1.2MIN
2.54 MIN

0.10MIN

H

0.5MIN

0.019 MIN

I
J

5.22 MAX

0.206 MAX

5.72 MAX

0.225 MAX

K

15.24

L

13.2

M

'

0.600
0.520

0.25 +0.1
- 0.05

+ 0.004
0.010 _ 0.002

(Ceramic)
ITEM
A

MILLIMETeRS
51.5 MAX

INCHES
2.028 MAX

B
C
0

1.62

0.064

2.54 ± 0.1

0.100 ± 0.004

0.50±0.1

0.0197 ± 0.004

E

48.26 ± 0.2

F
G
H

1.900± 0.008

1.27

0.050

3.2MIN

0.126 MIN

1.0 MIN

0.04 MIN

I
J

4.2 MAX

0.17 MAX

5.2 MAX

0.205 MAX

K

15.24 ± 0.1

0.6 ± 0.004

L

+ 0.2
13.5 _ 0.25

0.531

M

0.30± 0.1

~ ~:~~~

0.012 ± 0.004

221

INSTRUCTION SET

JL PD8041 18741
INSTRUCTION CODE

MNEMONIC

ADO A,

~

d'lta

FUNCTION
(A)

+-

(A) + data

DESCRIPTION

07
De
AT R

Add Immediate the specif ied Data to the
Accumulator.

d7

ADO A, Rr

(A)-(A)+(Rr)
forr ~ 0- 7

Add contents 'of designated register to
the Accumulator.

ADDA,@Rr

(A)-(A)+({Rr)1
forr" 0-- 1

memory location to the Accumulator.

ADDC A, :; data

(A) -- (A)

+ Ie) + data

Add Immediate with carry the specified
data to the Accumulator.

ADOC A, Ar

(A)- (AI + leI + (Ar)
for r= 0- 7

Add with carry the contents of the
designated register to the Accumulator.

AOne A,@Rr

(A) -- (A) + fe)
for r = 0- 1

data memory location to the

+ ({Rd)

0
d6

Os
0
d,

0,
0
d.

FLAGS

0>

02

0,

DO

0
d>

0
d2

I
dl

dO

CYCLES

BYTES

C AC

0

Add Indirect the contents the data

d,

d6

0
d,

d.

0
d3

0
d2

1
dl

1
dO

1
d.

d,

1
d.

0
d3

0
d2

1
dl

1
dO

0

Add Indirect with carry the contents of
Accumulator.

ANL A,

= data

(AI

+--

(A) AND data

Logical and specified Immediate Data
with Accumulator.

0
d7

ANLA, Ar

(AI <-- (AI AND (RrI
for r '" 0- 7

Logical and contents of designated
register with Accumulator.

ANLA,@Rr

(A) <-- (A) AND ((Rr))
forr = 0··1

Logical and Indirect the contents of data
memory with Accumulator.

CPL A

(AI -NOT (A)

Complement the contents of the
AccumulatOI.

CLR A

(A) -0

CLEAR the contents of the Accumulator.

OAA

1

(A)-- (A)+1

INCA
ORLA,

!•

DECIMAL ADJUST the contents of the
Accumulator.
(AI-(A)

DEC A

=data

DECREMENT by 1 the accumulator's
Increment by 1 ,he accumulator's
contents.

(AI .... (A) OR data

Logical OR or specified Immediate data
With Accumulator

GRL A, Rr

(AI +- (A) OR (Rr)
for r = 0 ·7

Logical ORcontants of designated
register with Accumulator.

ORL A,@Rr

(A) - (A) OR ((Rr))
for r = 0 -1

LogICal OR Indlract the contents of data
memory location With Accumulator.

(AN + 1) .. (AN)
(AO) .... (A 71
for N '" 0- 6
{AN + 1 I - (AN); N = 0 ·6
(AO} .... IC)
(C) ... (A7)

Rotate Accumulator left by l·bl! Without
carry.

RL A

ALC A

d6

0
d,

0
d,

0
d3

0
d2

1
d,

1
dO

1
d6

0
d,

1
d.

0
d3

0
.2

dl

1
dO

'6

"

'.

'3

'2

'I

'0

'3
0
'3

'2

'1

'2
1
'2

'I
1

'0
0
'0

'2

'I
.0
'1

'0
0
'0
0
'0

",

'"

'1

'0
0
'0

1

Rotate Accumulator left by 1-bit throug,
carry.

RR A

(AN) - IAN + 1); N = 0 - 6
(A7)" (AO)

Rotate Accumulator right by 1·bit
without carry.

RRCA

(AN) .... (AN + 11; N"0-6
(A7J" ICI
ICI· (AD)

Rotate Accumulator fight by 1-bit
,through carry.

SWAP A

(A4-71;':

XAL A, =data

(AI .. (A) XOR data

Logical XOR speCified immediate data
with Accumulator.

XRL A, Rr

(AI <- (A) XOR (Ar)
for r =0- 7

Logical XOA contents of designated
register with Accumulator.

XALA,@Rr

(A) - (AI XOA ((Ar))
for r = 0
1

Logical XOA Indirect the contents of data
memory location with Accumulator.

(Ao- 31

0
d7

Swap the 24·bit nibbles in the
Accumulator.

1
d,

1

BAANCH
DJNZ Ar, addr

(ArI-IAr) 1;r - 0- 7
If (Rrl*O:
(PC 0 - 7) <-- addr

Oecrement the specified register and
testcontenH.

JBb addr

(PC 0- 7) .... addr If Bb = 1
(PC) .. (PC) + 2 if Bb = 0

Jump 10 speCified address if
Accumulator bit isset.

JCaddr

(PCO- 7) -addr if C-1
{PCI - (PC) + 2 If C '" 0

Jump to specified addrCfl if carry flag
is set.

JFOaddr

(PCO-7) .... addr if FO" 1
(PC) ......)(PCI + 2 if FO = 0

Jump to specified address if Flag FO is
set.

JF1 addr

(PCO-7) .... addrifF1 =1
(PC) .... (PC) + 2 if Fl = 0

Jump to specified address if Flag Fl IS

(PC8-10)--addr8-TO
(PC 0 - 7) ...... addr 0 - 7
(PC 1H -DBF

Direct Jump to specifIed address Within
the 2K address block.

JMPP@A

(PC 0- 7) .... ((An

Jump indirect to specified address With
With address page.

JNC addr

IPCO-7)<--addrifC=O
(PCI <-- (PC) + 2 ifC= 1

Jump to specified address jf

JNIBF addr

IPCO- n ...... addr if IBF =
(PC) ...... (PC) + 2 if IBF = 1

Jump to specified address if input buffer
fuli flag is low.

JMPaddr

JOBF

222

"
b2

",
"1
"
'7
'10

"

carrv flag is

low.

(PCO-n .... addr ifOBF= 1 Jump to specified address if output
(PC) .... (PC) + 2ifOBF = 0
buffer full flag is set.

''.. ''..
'. ''..
b,

bO

1

"1

0

1
'6

'9
'6

..
..

"1
"1
"'8
"

1

"1
"
"

1

'6

"
"
"

1

'3

1

'.

..
..'.
0

'3
0
'3

'3
0
'3
0
'3

"
'2
1
'2
1

..

'1
1

'1

FO

F'

IBF DBF

fL PD8041/8741

INSTRUCTION SET (CONT.)

-----~----

INSTRUCTION CODE
MNEMONIC

FUNCTION

06

Os

'7

'S

's

'7

'S
0
'S
0
'S
0
'S
1

's

BRAN
JNTO_addr

(PC 0- 7) .... addr itTO= 0

JNTl addr

(PC 0- 7) <--addr if Tl = 0
(PC) ~ (PC) + 2 if Tl '" 1

Jump to specified address if Test 1 is low.

(PC 0 - 7)

Jump to specified address jf accumulator

Jump to specified address if Test 0 is low.

(PC) +- (PC) + 2 jf TO '" 1

JNZ addr

(PC)

<-

addr jf A of 0

+-

(PC) + 2 if A = 0

Jump to specified address if Timer Flag

JTOaddr

(PC 0- 71 ..... addr if TO

1

Jump to specified address if Test 0 is a L

JTl addr

(Pf; 0 - 7) <- addr if Tl '" 1
(PC) +- (PCI + 2 If Tl '" 0

Jump to SpeCified address if Test 1 is a 1.

(PC 0- 7Y--addr if A

Jump to specified address if Accumulator
isQ

(PC)

JZ addr

<-

(PC)

+-

+ 2 if

(PC)

(PC)

+ 2 If

=

=

0

1

1

a7

's

0
d7

dS

1
dS

,

dS
0

d7

0
dS

0

is ret to 1.

87

TO = 0

A I 0

0
'S
0
'S
1
'S
0
'S
0
'S

87

is non-zero.

(PCO-7) <-addrifTF '" 1
(PC) <- (PC) + 2 if TF '" 0

JTF add,

0

'7
0
'7

's

CONTROL
EN I

Enable the External Interrupt mput.

DIS I

0,

'''...
'.
'.
''..
1

0

0,

FLAGS

03

0,

'3
0
'3

"1
"1
"1
"1

'1
1
'1
1
'1

'2
1

"

"t

'1
1

"

'1

'0
0
'0
0
'0
0
'0
0
'0

0

'3
0
'3
0
'3
0
'3
0
'3

'1

t

DO

CYCLES

BYTES

C

AC

FO

F1

IBF

OBF

'0
'0
,0

Disable the External.lnterrupt Input

SEL RBO

(BS) <- 0

Select Bank 0 (locations 0 - 7) of Data
Memory.

SEL RBl

(8S) +-1

Select Bank 1 (locations 24 - 31) of
Data Memory.

MOV A, # data

(A) <-data

Move Immediate the specified data into
the Accumulator.

MOVA, Rr

(AI-IRr);r"'0-7

Move the contents of the designated
registers mto the Accumulator.

MOVA,@Rr

(AI - (IRrn;

MOV A, PSW

(AI <-(PSW)

MOV Rr, # data

(Ar) <-data; r '" 0- 7

Move Immediate the specified data into
the designated register

MOV Rr, A

(Rr)-(A);r=0-7

Move Accumulator Contents Into the
desIgnated register.

MOV@Ar,A

((Ar)) <- (A); r '"' 0- 1

Move Indirect Accumulator Contents
Into data memory location

MOV @ Rr, # data

HRr)) .- data; r " 0 - 1

Move Immediate the specified data into
data memory.

MOV PSW, A

(PSW) <-(AI

Move contents of Accumulator into the
program status ward.

DATA MOVES

0- ,

f

d4

d3

d2

d,

1
dO

d5
1

d.

d3

d,

d,

dO

dS

d.

d3

d,

dl

dO

Move Indirect the contents of data
memory location Into the Accumulator
Move contents of the Program Status
Word into the Accumulator.

MOVP A,@A

(PC 0- 7) <- (A)
+-- ((PCll

Move data m the current page into the
Accumulator.

MOVP3 A,@A

(PC a - 7) -<- (A)
(PC8- 10)-011
(A) -((PCll

Move Program data in Page 3 Into the
Accumulator.

(A)

a-

XCH A, Rr

(A) ~ (Ar);r '"

XCHA,@Rr

(A):;:::((Ar)); r=O-l

XCHD A,@Rr

(A 0 - 3) :; BAril
r'" 0 1

7

a - 3));

d7

1

0

0

0

Exchange the Accumulator and
designated register's contents.
Exchange Indirect contents of Accumu·
lator and location in data memory.
Exchange Indirect 4·bit contents of
Accumulator and data memory.
FLAGS

CPL

e

(e)

+--

NOT (C)
NOT (FO)

CPL FO

(FOI

CPl Fl

(Fl)-NOT(Ft)

e

+-

Complement Content of carry bit.
Complement Content of Flag FO.
Complement Content of Flag F1

(el --0

Clear content of carry bit to

ClR Fa

(FQ}-O

Clear content of Flag 0 to O.

CLR Fl

(Fll ..... 0

Clear

ClA

con~ent

a.

of Flag 1 to O.

II

223

II- PD8041/8741

INSTRUCTION SET (CONT.)
INSTRUCTION CODE

07

DESCRIPTION

FUNCTION

MNEMONIC

06

05

04

ANlPp. _data

IPP) - IPpl AND data
P"' 1·- 2

Logical and Immedillt. specified data
with deSignated port (1 or 2J

ANLD Pp, A

Ippl .... (Ppl AND IA 0 - 31
p=4 7

Logical and contana of Accumulator

1
d7

INA,Pp

(AI -- (Ppl; p = , - 2

03

0
dS

0

, ,

d,

d,

0

0

INP T OUTPUT

d3

. FLAGS

02

01

0

p

d2

d,

d2

d,

DO

CYCLES

BYTES

C· AC

FO

F1

IBF

OBF

P
dO

with designated pert (4 - 71.
Input data from deSignated port (1 - 21
into Accumulator.

0

IN A, DBB

(A)"" (DBB)

Input strobed DBB data into
AcculTKoIlator 81!d cJeer IBF

MOVO A, Pp

(AO- 3) .... (PP);p· 4- 7
(A4· 7)-0

Move contents of deSignated port (4
into Accumulator.

Move pP. A

(PP) .... AQ-3;p=4

Move contents of Accumulator to
deslgna'ed port (4 71.

DAlO pP. A

(Pp) ... (Pp) OR (A 0 - 3)
p"4 7

Logical or contents of Accumulator with
deSignated port (4 - 7).

IPPI - IPp) OR data

Logical or Immediate specified data With
deSignated port t 1 . 2)

1
d7

tOBBltAI

Output conteno of Accumulator onto
DBB and set OBF.

0

CUTL Pp, A

IPp) - (A); p = 1

Output contents of Accumulator to
designated port 11 21.

OEC Rr

(Rr)- (Rr)

OAL pP. =datl

7

p = 1·2

OUT OBB,A

2

71
"

,

0
de

d,

d,

d3

p

P
dO

0

0

0

REGISTERS
(Rd

1; r = 0

7

Decrem'nt by 1 contents of designated
register.

INCRr

(RrI·- (Rr! +1;r = D·· 7

Increment by 1 contents of des,ignated
register.

INC@Rr

IIRdl .. (IRrJl + 1;
r· 0 .. 1

Increment Indirect by 1 the contents of
data memory location.

"

SUBROUTINE
liSP)) -- (PCI, IPSW 4·· 7)

CALL ac:Idr

Call deSignated Subroutine.

(SPI ... (SP) + 1
(PCB-1Q)-addr8·10
(PCO-1)-addrQ-7
IPClll-0BF
RET

(SP) .... (SP) - 1
(PCI .- liSP))

Return from Subroutine without
restoring Program Status Word.

RETR

(SP) .. (SP) 1
(PC) .... liSP))
(PSW 4 - 7) -- I(SP))

Return from Subroutine restoring
Program Status Word.

al0

a9

a8

a7

~

as

a4

~

a2

a1

ao

TIMER/COUNTER
EN TeNTI

Enable Internal interrupt Flag for
TimerfCounter output.

Q

0

DIS TeNTI

Disable Internal interrupt Flag for
Timer/Counter output.

o

.0

MOVA. T

(A)

MOVT, A

(T)- (A)

Move contents of Timer/Counter into
Accumulator.

~.(T)

Move contents of .Accumulator into
Timer/Counter.

STOP TeNT

Stop Count for Event Counter.

STRT :NT

Start Count for Event Counter.

STRTT

Start Count for Timer.

'0
MISCELLANEOUS

NOP
Notes

No Operation performed.

I

I

0

o

0

(j)
@
Q)

Instruction Code DeSignations rand I..l form the binary lepresentatlon of The Re~lstt!rs 31lt! POI'h IIwolVl'cl

@)

NumerlcaJ SUbSCllptS appearing in the FUNCTION column reference the specific bits affected.

I

' I

' I

The dot undel' the appropllate flag bit Indlcate~ that rts content IS subject to change by the Instluctlon ,t tlppear~ 'n
References to the address and data ale speclfred rn bytes 2 and or 1 of the Instruction

Symbol Definitions:
SYMBOL
A
AC
addr
Bb
BS
BUS
C
CLK
CNT
D
data
DBF
FO, Fl
I
P
IBF

DESCRIPTION
The Accumulator
The Auxiliary Carry Flag
Program Memory Address (12 bits)
Bit Designator b = 0 7)
The Bank Switch
The BUS Port
Carry Flaa
Clock Signal
Event Counter
Nibble Designator (4 bits)
Number ,or ExpresSion (8 bits)
Memory Bank Flip·Flop
Flags O. I,
Interrupt
''In·Page'· Operation Designator
Input Buffer Full Flag

SYMBOL
Pp
PSW
Rr
SP
T
TF
Tn. T1

X

#
@

$
(x)
((x))
<-

OBF
DBB

DESCRIPTION
Port Designator (p = 1, 2 or 4 - 7)
Program Status Word
Register Designator (r =0, 1 or 0 - 7)
Stack PointeT
Timer
Timer Flag
Testable Flags 0, 1
External RAM
Prefix for Immediate Data
Prefix for I ndirect Address
Program Counter's Current Value
Contents of External RAM Location
Contents of Memory Location Addressed
by the Contents of External RAM Location.
Replaced By
Output Buffer Full
Data Bus Buffer
SP8041/8741·9·78-GN·CAT

224

"NEe

NEe Microc~mputers, Inc.

JLPD8048
JLPD8748*
JLPD8035

JLPD8048 FAMILY OF SINGLE CHIP,
8·BIT MIC~OCOMPUTERS
DESCRIPTION

The pPDaO~8'famiIY of single c!1ip a:bitmicrocomputers is comprised of the pPD8048,

pPD87~8 a~d pPD8035. The processors in this family differ only in their internal pro·
gram memory optiQns: the pPD8048 with 1K x 8 bytes of mask ROM, the pPD8748
with 1 K x 8 bytes of UV erasable EPROM and the pPD8035 witnexternal memory.
"""

F EATU RES

• Fully Gompatible With Industry. ,Standard 8048/8748/8035 ,
• NMOS Silicon Gate Technology Requiring a Single +5V Supply
• 2.5 ps Cycle Time. All Instruction for 2 Bytes
• Inte~val Timer/Event Cour]ter
• 64 x 8 Byte RAM Data Me'mory
• Single Level Interrldo not require a mask ROM.
The J,lPDB035 is intended for applications using external program memory only. It
contains all the features of the J,lPD8048 except the 1024 x B-bit internal ROM. The
external program memory can be implemented using standard 8080A/8085A memory
products.

POWER(UPPLV

BLOCK DIAGRAM

IVAIHAOLE WORD LENQTHI

,.,. P080481874818035
PIN IDENTIFICATION

PIN
NO.

SYMBOL

1

TO

2

XTALI

FUNCTION

Testable input using conditional transfer funct!ons JTO and
JNTO. The internal State Clqck (elK) is available to TO
using the ENTO elK instruction. TO can alS9"be used
during programming as a testable flag.

One side of the crystal

inpl!~

for external oscillator or

frequency (non TIL compatibie V IH).
3

XTAl2

The other side of the crystal input.

4

RESET

Active low input for processor initialization. R"ESET is
also used for-PROM programming verificatiqn and powerdown (non TTL compatible: V ).

5

SS

Single Step input (active-low). SS together with ALE allolivs

the'processor to "single-step" through each instryction in
prQgram memory.

6

INT

Interrupt input {active-I owL tNT will start an interrupt if
an enable internJpt instruction has been executeq. A reset
wjll disable the interrupt. INT J;an be tested
conqitional jump'instruction.

by:iss~ing

a

7

EA

Ex~ernal Access input (active-~'1gh). A logic "1~' at this
inpu! commands the processor to perform all program
memory fe!ches from 'external m~morv.

8

RO

READ strobe output (active· low). RD will pulse low when
the processor performs a BUS READ. RD will also' enable
data onto the proc~ssor BUS from a peripheral device and
function as a READ STROBE for ~x!ernal DATA MEMORY.

9

I'SEN

10

WR

11

ALi:

,l\ddre~s b~tch En~ble output {active high}. Occurring once
each cycle,'the falling edge of ALE latches the address for
external memory or peripheraf~, ALE can also be used as
a clock output.,~
"

12-19

DO- D7 BUS

8-bit, bidirectional.port. ~ynchfonous reads a~ writes can
be performed on ttiis port ~sing R D and WR Slr'obes. The
contents of the DO - 07 BUS can:be latched in a s~atic
mode.

Program Store Enable output (active·low). PSEN becomes
activp- only during an external memory fetch..
WRITE strobe output (active·low). WR~II pulse low when
the prpcessor performs a BUS WR ITE. ~R can also function
as a WRITE STROBE for external DATA MEMORY.

During an external memory fetCh, the DO - D7 BUS holds
the least significant bits of the program, counter. PSEN
controls the ,incoming addressed instruction. Also~ for an
e~ternal RAM data store instruction the DO - D7 BUS,
co~trolled by ALE" AD and WR, contains addre'ss and data
information.
'

Pro~essor's GROUND potenti.1.

20

VSS

21 -'24,
3S - 38

P20 - P27:
PORT 2

Port 2 is the second of two 8-bit quasi-bidirectional ports.
For external data memory fetches, the four most significant
bi,ts of the program counter are contained in P20 - P23. Bits
P:!O - P23 are also used as a 4·bit I/O bus for the "PD8243,
INPUT/OUTPUT EXPANDER.

25

PROG

Program Pulse. A +25V pulse applied tq this input iS,used
tor programmin,g the ,uPD8748. P~OG is also used as an outpu.t strobe for the ilPD8243.

26

VDD

Prog~~mming Po~r Supply. VDO must be set to +25V, for
programming the "PD8748, and to +5V for the ROM and
PROM versions for normal operClti9n. VDO function~ as the.
low Power Standby input for the "PD8048.

27 - 34

PlQ.c PI j:
PORT 1

39

Tl

Testab!e input using conditional transfer functions JTl and
JNTl. Tl can be made the counter/timer input using the
STRT CNT instruction.

40

VCC

Primary Power Supply. VCC must be +5V for programming
and operation of the "PD8748, 'and for'operation of the
"PD8035 and "PD8048.

II

Port 1 is one of two 8-bit qu~si-bi~irectional ports.

227

f.L PD80481874818035
aOc to +7aoC

Operating Temperature . . . . . . . . . .
Storage Temperature (Ceramic Package) .
Storage Temperature (Plastic Package) .
Voltage on Any Pin
Power Dissipation . . . . . . . . .
Note:

- - - -<"-_-"A~,,,~:::X:;:::":""-_'J~ - '- -'

____~X

X~______~______
VERIFY MODE TIMING
(I'PD8048/8748. ON L Yl

Not..

CD

Cood,t,ons CS TTL logIc '.,.', Ao TTL Log'c "0" '"'''' b. met.
(use 10K res .. l0,to Vee lor CS, and 10K re"st<>r to Vss fo, "1.01
@ICY 5JO,canbe""hlevedu""983MH~I"quenCvsDUrce(LC.
XTALore.ternallat'ho XTAL 1 and XTAL2 tnp"IS.

,231

I

P. PD8048/8748/8035

INSTRUCTION SET

INSTRUCTION CODE

MNEMONIC

FUNCTION

ADD A, # data

(A) <--- (A) + data

AOD A, Ar

(A) <--- (A)

DESCRIPTION

Add Immediate the specified Data to the
Accumu'lator.

+ (Rr)

Add contents of designated register to
the Accu mu lator.

for r" 0- 7

ADD A,@Rr

(AI

ADD~

(A) <--- (A)

(A)

<---

a-

for r"

A, .:It data

+ ((Rd)

(A)

(A)

<---

03

02

0,

DO

d6

d5

0
d4

0
d3

d2

d,

dO

d6

0
d5

d4

d3

d2

d,

dO

d5
0

d4

d3

d2

d,

dO

d5

d4

d3

d2

dl

dO

0

0

d5

d4

d3

d2

dl

1
dO

'2

'1

'0

'0
0
'0
0
'0

CYCLES

Add Indirect the contents the data

1

memory location to the Accumulator.

+ (e) + data
+ (e) + (Rd

for r" 0 - 7

Add Immediate with carry the specified

,

1

(A) <- (A) + (e) + HRr))
for r = 0- 1

Add Indirectwith carry the contents of
data memory locat'ion to the
Accumulator.

ANL A, # data

(A) - (AI AND data

Logical and specified Immediate Data
with Accumulator.

ANL A, Rr

(A) -lA) AND {Ad
for r eo 0 ~ 7

Logical and contents of designated
register with Accumulator.

1

d7
0

ANLA,@Rr

{AI <- (AI AND ((Rd)
for r eo 0 - 1

Logical and Indirect the contents of data
memory with Accumulator.

CPL A

{A} -NOT (A)

Complement the contents pf the
Accumulator.

CLR A

(A) +-0

CLEAR the contents of the Accumulator.

DEC A

(A) -lA) --1

DECREMENT by 1 the accumulator's
contents.

INCA

(A) - (A) + 1

Increment by 1 the accumulator's
contents.

ORL A, = data

(AI - (A) OR data

Logical OR specified immediate data
with Accumulator

DAA

0
d7

Add with carry the contents of the
designated register to ~he Accumulator.

ADDC A,@Rr

d6

DECIMAL ADJUST the contents of the
Accumulator.

d7

ORL A, Rr

(A) <-- (A) OR (Rr)
forr=0-7

Logical ORcontents of deSignated
register with Accumulator.

0

ORLA,@Rr

{AI- (A) OR HRd}
for r '" 0 - 1

Logical OR Indirect the C{mtMts of data
memory location with Accumulator.

0

AL A

(AN + 1) +- (AN)
(A O) +- (A 7 )
for N = 0 - 6
(AN+ l)<--(AN);N =0-6

Rotate Accumulator left by l-bit wltholJt
carry.

ALC A

0,

0

data to the Accumulator.
AOOC A, Rr

d7

FLAGS

05

07
06
ACCUMULATOR,

IAOI~

lei

~

ICI
IA71

(AN) <-- (AN + 1); N = 0 - 6
(A71 <- (AO)

Rotate Accumulator right by l-bit
without carry.

AACA

(AN) - (AN + 1); N "0 - 6

Rotate Accumulator right by 1-blt
through carry.

SWAP A

(A4_7) -.;:. (AO - 3)

Swap the 2 4-blt nibbles in the
Accumulator.

XRL A, #data

(AI

Logical XOR specified immediate data
with Accumulator.

<--

(A) XOR data

,

Rotate Accumulator left by l-blt through
carry.

AAA

IA71-ICI
ICI-IAOI

1
d6

,
d7

.d6

XRL A, Ar

(AI <-- (A) XOA (Rr)
for r = 0 - 7

Logical XOR contents of designated
register with Accumulator.

XAL A,@Ar

(A) -<--- (AI XOR ((Arl)
for r = 0 - 1

Logical XOA Indirect the contents of data
memory location with Accumulator.

DJNZ Rr, addr

(Ad +- (Rr) 1;r
If (Rr) =1= 0;
.(PC 0 - 7) +- addr

Decrement the specified register and
test contents.

'7

'6

'5

'4

'3

JBb addr

(PC 0- 7) -addr if Bb "" 1
(PC) ..... (PC) + 2 if Bb = 0

Jump to specified address If
Accumulator bit is sel.

b2
'7

b,
'6

bO
'5

'4

'3

'2

'1

JC addr

(PC 0 - 7) ...... addr if C "" 1
(PC) .... (PC) + 2 if C. = 0

JUrTlP to speCified address 'd carry flag
is set.

'4

0
'3

'2

,

'1

Jump to specified address if Flag FO is

'6
0
'6

'5

(PC 0- 7) -addr if FO = 1
(PC) .... )(PC) + 2 if FO ~ 0

'7
1
'7

'5

'3

'2

'1

JFl addr

(PC 0- 7) -addr if Fl = 1
(PC)' ~ (PC) + 2 'if Fl '" 0

Jump to specified address if Flag Fl is

, ,

'4

'7

'6

'5

'4

(PC 8 - 10),'" addr 8- 10
(PCO- 7) -addr 0- 7
(pC 11) "-DBF

Direct Jump to speCified address within
the 2K address block.

"0
'7

'9
'6

'8
'5

'4

'3
0
'3

'2

JMP addr

0
1

BRANCH

JFO addr

0-7

JMPP@A

IP.C 0- 71-IIAII

Jump Indirect to specified address with
with address page.

JNC addr

(PC 0 - 7) .... addr if C -= 0
(PC) ... (PC) + 2 if C = 1

Jump to specified address if carry flag is
low.

JNI addr

(PC 0 - 7) ...... addr if I '" 0
(PC) <-- (PC) + 2 if I = 1

Jump to specified address if interrupt
is low.

232

,

,

1
'2

'1
0

'0
0

'1

'0
2"

'7

,

~6

'5

'4

'3

'2

,

'1

'7

0
'6

'5

'4

'3

'2

'1

'0
0
'0

SVTES

C AC

FO

F,

P. PD804818748/8035

INSTRUCTION SET (CONT.)

INSTRUCTION CODe

MNEMONIC

FUNCTION

."

DESCRIPTION

Os

DO'

03

'4

's

'5
0
'5
.0
'5
0
'5

,

'4

0
'S

'3
0
'3
0
'3
0
'3
0

'5

'4
'4

's

'5
0
'5

.0
dS

d5

06

FLAGS

1>2

0,

DO

'0

CV.CLES "BYTES

C AC

FO

F1

BRANCH (CONT.)
JNTO addr

(PCO- 7)-addr If TO(PCI- (PC) + 2 if TO= 1

0:

Jump to specified address if Test 0 is low.

0

JNn addr

(PC'O-7J --adclr ifn = 0
(PC) .~ (PC) + 2 If T1 = 1

Jump to specified address If Test 1 IS low.

'7
0
'7

(PC 0- 71..-.addr if A '" 0
(PC) .- (PC) + 2 If A = 0

Jump to specified address If accumulator
is non-zero.

JNZ addr
JTF addr

(PC 0- 7) -addr if TF '" 1
(PCI .- (PC) + 2 if TF = 0

Jump to specified address If Timer Flag

JTO addr

(PC 0- 7) -addr ilTO = 1
(PC) -- (PCI + 2 if TO = 0

Jump to specified address If Test 0 is a I

JTl addr

(PCO-71..-addr ifTl '" 1
(pc)·- (pel + 2 if T1 '" 0

Jump to specified address

(PC 0- 7) -addr if A '" 0
(PC) .- (PC) + 2 .f A I 0

Jump to specified address if Accumulator
is O.

JZaddr

is set to 1.

If

Test 1

15

a 1.

,

'7
0
'7
0
'7
0
B7

,

's
's
0
'6
0

,
, ,

'7

'S

'4
B4

,

'4

'2

"

B2

B,

B2

,
,

"

B2

B,

'3
0
'3
0
B3

'2

"

d3

B2

",

'2

"

di

d,

CO~TROL

EN I

Enable the External Interrupt input.

015 I

Oisable the External Interrupt IOput.

ENTO CLK

0
BO
0
BO
'0
BO
0
'0
0
BO

Enabl!l the Clock Output pin TO.

SELMBO

(nBF) - 0

SEL.: MBl

(OBF) •

Select Bank 0 (locations 0 - 2047) of
Program Memory.

,

Select Bank 1 (locations 2048 - 4095) of
Program.M.emory.
Select Bank 0 {locations
Memory.

IB81-0

SEL RBO

,

a-

Select Bank 1 (locations 24
Data Memory.

SEL RBl

(85) •

MOV A, - data

IAI· data

MOVA, Rr

(A)- (Rr);r= 0

MOVA,@Ar

(A) - ((Rd); r =

MOVA, PSW

(A) . (PSW)

7) of Data
31) of
DATA MOVES

MOV Ar,

= data

Move Immediate the speCified data lOt?
the Accumulator.

a

IArl - data; r =

a

MOV Rr, A

(Rr) - (A); r = 0
((Rrl)'-(A);r='O

=data

MOVPSW, A

1

, ,

Move Immediate the specified data IOta
the deSignated register.

7
7

((Rr))- data; r = 0

,

(PSW) • (AI

dO

"
"
d7

,
dS
0

Move Accumulator Contents IOta the
designated 'register.
1

d4

Move Indirect the contents of data
memory location Into the AccumulatOl.
Move contents of the Program Status
Word Into the Accumulator.

MOV@Rr,A
MOV@ Rr,

d7

Move the contents of the deSignated
registers IOta the Accumulator.

7

,

d5

d4

2'
d3

d2

d,

dO

0
d3

d2

d,

c
dO

. O·

. Move Indirect Accumulator Contents
into data memory location.
Move ImmedIate the specified data IOta
data memory.

d,

dS

d5

'd4

,

Move contents of Accumulator Into the
program status word.

a

MOVP A.@A

(PC
71·- (AI
(A) • (lPCII

Move dota 10 the current page IOta the
Accumulator.

MOVP3 A,@A

(PC 0 71·- (AI
(PCS ·10) (A) . "PCII

Move Program data
Accumulator.

all

10

Page 3 mto the

MOVX A,@R

IAi"'IIRr));r"-

a

1

Move Indirect the contents of external·
data memory into the Acc\lmulator.

MOVX@A,A

(fRd) - (A);r = 0

1

Move Indirect the con·tents of the
Accumulator IOta external data memory.

XCH A, Rr

(AI~(Rr);r=0-7

Exchange the Accumulator and
designated register's contents.

XCH A,@Rr

(A);:::((Rrl); r=0-1

Exchange Indirect contents of Accumu·
lator and locatIon m data memory.

XCHD A,@Ar

(AO-3).!;: ((Ar)) 0-3)i;

Exchange Indirect 4·blt contents of
Accumulator and data memory.

r '" 0-1

·0

II

.. ,

FLAGS
CPLC

(CI' NOTIC)

Complement Content of carry bIt.

CPL FO

(FOI - NOT (FO)

Complement Content of -Flag FO.

CPL F1

(F1I· NOT (Ft)

Complement Content of Flag F 1

C

(.cl- 0

Clear content of car~v bit to O.

CLR FO

(FO).- 0

Clear content of Flag 0 to O.

CLR F1

IF1) • 0

Clear content of Flag 1 to O.

CLR

.'

.

1

233

J.L PD8048/8748/8035

INSTRUCTION SET (CONT.)
FLAGS

INSTRUCTION CODE

MNEMONIC

" FUNCTION

DESCRIPTION

07

06

05

0"

03

02

01

DO

d5

d4

d3

d2

dl

dO

d2

p
dl

dO

dl

dO

CYCLES

INPUT/OUTPUT
ANL BUS,

data

(BUS)·

AN~

(BUS)

data

LO.~_lc_a~ and Immed'8te-spec,'fied data

contents of BUS.
ANL Pp,

.0:

data

(Pp) AND data

ANLDPp,A

(Pp) AND (A 0

3)

7

p

d7

Logical and contents of Accumulator with

1

designated POI"t {4

IN A, Pp

IA)·

(Pp); p . 1

INS A, BUS

(A)·

(BUS)

2

MOVD A, Pp

(AD ·3)' (Pp);p
(A 4
7)· 0
(Pp).
cIata

(SUS)·

3;p

4

7
7

ORLPp,

OR (A 0

3)

OR data

Move contents of designated port 14

DUTL Pp, A

(Ppl·

(AI;p

DEC Rr

(Rrl·

{Rrl

I

71

71

I

0

d5

d4

d3

d2

1

71
p

p

d3

02

'1
1

dO

'3

'2

'1

'0

With

d7

contents of Accumuiator onto

2

d6

logical 01 contents of Accumulator With

(A)

1

1
d7

Logical or Immediate
deSignated port {1

p -

(BUS),

p

1

Move contents of Accumulatol to

designated pon {4

data

d3

1

Logical or I mmedl8te specified data With

p - 4

DUTL BUS, A

d4

Into AccumulatQI

4

(BUS) OR data

(Pp) .

d5

21

contents of BUS
ORlO Pp, A

d6

71.

Input data from desIgl18ted port (1
Illto Accumulator

designated port (4
OR L BUS,

d6

Input strobed BUS data Into Accumulator.

MOVO Pp, A

AO

d7

and Immediate specified data
designated port (lor 2)

2

06

0

d5

d4

0

0

OutDut contents of Accumulatol to
21
deSignated port (1
REGISTERS

IRI)

1;

7

Decrement by 1 contents of deSignated
I ~lg 1st e I .

INC HI

(Rr)·

INC@RI

(tRr))'

IRrl +1: r

,-- 0

{(RI))

-+

<.

0

7

Increment by 1 contents of deSIgnated
leglster

1;

InClement indirect by 1 the contents of
data memory locatIon

1

SUBROUTINE
CALL acid I

IPCI, (PSW 4

((SP))·

7)

Call deSIgnated SubroutIne.

(SPI' (SPI i 1
(PC8
10)' addIS
10
{PC 0
71 - addr 0 7
(PC 111· OSF

RET

(SPI'
IPCI

(SPI
{ISPII

Retuln from SUb,outlne WIthout
lestorlny Program Status WOld

RETR

(SPI· (SPI
1
(PC)· (ISPI)
{PSW 4 71· (iSPII

Re'uln from Subrout'ne ,,,,<:10(1119
P.-ogram Status Word

'10

'9

'R

'7

'6

'5

'4

TIMER/COUNTER
EN TCNTI

Enable Internal Interrupt Flag for
TImer/Counter output.

DIS TCNTI

DIsable Internal Interrupt Flag tor
Timer/Counter output.

MOV A, T

(AI·

IT)

MDV T, A

IT)·

{AI

Move contents of T,mer/Counter Into
Accumulatol
Move contents of Accumulator Into
Timer/Counter.

STOP TCNT

Stop Count for Event Counter

STRT CNT

Start Count for Event Counter.

STRT T

Start Count for TImer

NOP

No OperatIon performed.

MISCELLANEOUS

Notes

CD
@
@

®

InstructIon Corle DeSignatIons rand p form the binary representation of the Registers and Ports Involved
The dot under the appropriate flag bit ,ndicates that Its contenl IS subJect to change by the InstructIon II appears In.
References to the address and data are specified In bytes 2 and/or 1 of the IIlstructlOn
Numerical Subscripts appearing in the FUNCTION column reference the specific bits affected

Symbol Definitions:
SYMBOL

A
AC
addr
Bb
BS
BUS

C
ClK

CNT
D
data
DBF
Fa, Fl
I
P

234

OESCRIPTION

The Accumulator
The Auxiliary Carry Flag
Program Memory Address {12 bits}
Bit Designator (b a 71
The Bank Switch
The BUS Port
Carry Flag
Clock Signal
Event Counter
Nibble Designator (4 bits)
Number or Expression {S bits}
Memory Bank Flip·Flop
Flags 0,1
Interrupt
''In·Page'' Operation Designator

SYMBOL
Pp
PSW
Rr'
SP

T
TF
TO, Tl
X

@

$
(xl
((xii

-

DESCRIPTION

Port Designator (p - 1, 2 or 4 - 7)
Program Status Word
Register Designator (r 0,1 or
71
Stack Pointer
Timer
Timer Flag
Testable Flags 0, 1
External RAM
Prefix for Immediate Data
Prefix for Indirect Address
Program Counter's Current Value
Contents of External RAM Location
Contents of Memory Location Addressed
I:lY the Contents of External RAM Location.
Replaced By

°

2

BYTES

C

AC

FO

F1

P. PD8048/87 48/8035

LOGIC SYMBOL
PORT =1
PORT =2
READ
WRITE

IlPD
8048

PROGRAM STORE
ENABLE

FAMILY

ADDRESS LATCH
ENABLE

PORT EXPANDER
STROBE

BUS

PACKAGE OUTLINES

------------------A----------------~

~PD8048C/D
~PD8748D
~PD8035C/D

-IC :-~

-E·---·_·--

D

Plastic
ITEM

MILLIMETERS

A

51.5 MAX

B

1.62

0.064

C

2.54 ± 0.1
0.5 ± 0.1

0.10 + 0.004

D
E

48.26

0.019 + 0.004

1.2 MIN

1.9
0.047 MIN

G

2.54 MIN

0.10MIN

H

0.5 MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

0.225 MAX

F

.

INCHES
2.028 MAX

K

15.24

l

13.2

M

0.600
0.520

0.25

+ 0.1
0.05

0.010 + 0.004
0.002

----K -

.---1

fMC .~
0" _ 15°·-1

1--

II

Ceramic
ITEM
A
B
C

D

E

MILLIMETERS
51.5 MAX
1.62

2.54 + 0.1
0.50+0.1
48.26 ± 0.2

INCHES
2.028 MAX
0.064

0.100 -t 0.004
0.0197 + 0.004
1.900 + 0.008

F

1.27

0.050

G

3.2MIN

0.126MIN

H

1.0 MIN

0.04 MIN

I
J

4.2 MAX

0.17 MAX

5.2 MAX

0.205 MAX

K

15.24 ± 0.1

l

13.5

M

+ 0.2

0.6 ± 0.004

- 0.25

0.531 + 0.008
- 0.010

0.30:t 0.1

0,012 + 0.004

SP8048-7-78-G N-CA T

235

NEe
NEe Microcomputers, Inc.

}LPD8049
}LPD8039

~m~[~~~~ffirnW
SINGLE CHIP

DESCRIPTION

FEATURES

PIN CONFIGURATION

8.~IT

MICROCOMPUTERS

The NECJ.lPDS049 andJ.lPDS039are single chip S-bit microcomputers. The. processors
differ only in their internal program memory options: the J.lPDS049 with 2K x S bytes
of mask ROM and the J.lPDS039 with external program memory.
. ..
,
• Fully Compatible with Industry Standard S049/S039
• Pin Compatible with the J.lPDS04S/S74S/S035
• NMOS Silicon Gate Technology Requiring a Single +5V Supply
• 2.5 J.ls Cycle Time. All Instructions 1 or 2 Bytes
• I nterval Timer/Event Counter
• 2K x S Bytes of ROM', 12S x S Bytes of RAM
• Single Level Interrupt
• 96 Instructions: 70 Percent Single Byte
• 27 I/O Lines
• Internal Clock Generator
• Compatible with SOSOA/SOS5A Peripherals
• Available in Both Ceramic and Plastic 40-Pin Packages

TO
XTAL 1
XTAL 2
RESET

SS
INT
EA
RD
PSEN

WR
ALE
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
VSS

J.lPD
8049/

S039

Vee
Tl
P27
P26
P25
P24
P17
P16
P15
P14
P13
P12
Pll
Pl0
VDD
PROG
P23
P22
P2l
P20

II

237

f'PD804918039
The NEe IlPD8049 and IlPD8039 are single component, 8-bit, parallel microprocessors
using N-channel silicon gate MOS technology. The IlPD8049 and IlPD8039 efficiently
function in control as well as arithmetic applications. The flexibility of the instruction
set allows for the direct set and reset of individual data bits within the accumulator and
the I/O port structure. Standard logic function implementation is facilitated by the
large variety of branch and table look-up instructions.

FUNCTIONAL
DESCRIPTION

The IlPD!!049 and IlPD8039 instruction set is comprised of 1 and 2 byte instructions
with over 70 percent single-byte and req~iring only 1 6r 2 cycles per instruction with
over 50 percent single-cycle.
The IlPD8049 and IlPD8039 microprocessors will function as stand-alone microcomputers. Their functions can easily be expanded using standard 8080A/8085A
peripherals and memories.
The IlPD8049 contains the following functions usually found in external peripheral
devices: 2048 x 8 bits of mask ROM program memory; 128 x 8 bits of RAM'data
memory; 27 I/O lines; an 8-bit interval timer/event counter; and oscillator and clock
circuitry.
The IlPD8039 is intended for applications using external program memory only. It
contains all.the features of the IlPD8049 except the 2048 x 8-bit internal ROM. The
external program memory can be implemented u,sing standard 8080A/8085A memory
products.

BLOCK DIAGRAM

...'1'""

,,,

"AM

REGisteR 7
LEVEL STACK
IVARIA8LfWORDLENGTHI

Acc~tTTeST

RESIOENTDATAMEMORV_RAM

U28x81

'STROBEl
CYCLE

238

fL P 08049/8039
PIN IDENTIFICATION

PIN
FUNCTION

NO.

SYMBOL

1

TO

2

XTAL 1

One side of the crystal input for external oscillator or
frequency (non TTL compatible V 1H ).

3

XTAL 2

The other side of the crystal input.

4

RESET

Testable input using conditional transfer functions JTO and
JNTO. The internal State Clock (elK) is available to TO
using the ENTO elK instruction. TO can also be used
during programming as a testable flag.

Active low input for processor initialization. RESET is
also used for PROM programming verification and powerdown (non TTL compatible V I.

5

SS

Single Step input {-active-Iowl. SS together with ALE allows
the processor to "single-step" through each instruction in
program memory.

6

INT

Interrupt input {active-I owL 'NT will start an interrupt if
an enable interrupt instruction has been executed. A reset
will disable the interrupt. j"f\j"T can be tested by issuing a
conditional jum'p instruction.

7

EA

External Access input (active-high). A logic "1" at this
input commands the processor to perform all program
memory fetches from external memory.

8

RD

READ strobe output (active-Iowl. RD will pulse low when
the proceSSor performs a BUS READ. RD will also enable
data onto the processor BUS from a peripheral device and
function as a READ STROBE for exter'nal DATA MEMORY.

9

PSEN

10

WR

WR ITE strobe output (active-Iowl. WR will pulse low when
the processor performs a BUS WR ITE. WR can also function
asa WRITE STROBE for external DATA MEMORY.

11

ALE

Address Latch Enable output (active-high). Occurring once
each cycle, the falling edge of ALE latches the address for
external memory or peripherals. ALE can also be used as
a clock output.

12 -19

DO - D7 BUS

a-bit, bidirectional port. Synchronous reads and writes can
be performed on this port using RD and WR strobes. The
contents of the DO - 07 BUS can be latched in a static
mode.

Program Store Enable output (active-Iowl. PSEN becomes
active only during an external memory fetch.

During an external memory fetch, the DO - 07 BUS holds
the least significant bits of the program counter. PSEN
controls the incoming addressed instruction. Also, for an
external RAM data s..!.Q!e instruction the DO.- 07 aus,
controlled by ALE, RO and WR, contains address and data
information.

20

VSS

21 - 24,
35 - 38

P20 - P27:
PORT2

Port 2 is the second of two a-bit quasi-bidirectional ports.
For external data memory fetches, the four most significant
bits of the program counter are contained in P20 - P23. Bits
P20 - P23 are also used as a'4-bit 1/0 bus for the I'PD8243,
INPUT/OUTPUT EXPANDER.

Processor's GROUND potential.

25

PROG

PROG is the output strobe for the I'PD8243 1/0 expander.

26

VDD

VOO is +5V for normal operation. It also functions as low
power standby pin.

27 - 34

PlO - P17:
PORT 1

39

T1

40

Vee

Port 1 is one of two 8-bit quasi-bidirectional ports.
Testable input using conditiona't transfer functions JT1 and
JNT1. T1 can be made the counter/timer input using the
STRT CNT instruction.
Primary Power supply.
operation.

Vee

is +5V during normal

239

II

J.L P08049/8039
OOC to +70°C
-65°C to +150°C
. -65°Ctot125°C
- 0.5 to +7 Volts  the specil ied Data to the
Accumulator.

0
d7

o

Add contents 01 designated register to

ADD A,@Rr

IAI·- (AI + (IArll
for r = 0 1

ADDC A, =- data

(A) • ciA) + (C) + data

Add Immediate With carry the speCified
data to the Accumulator.

ADDC A, Rr

(AI,

(AI + ICI + (Rrl
for r = 0
7

Add With carry the contents 01 the
designated register to the Accumulator

ADDC A.@Rr

(AI· (AI + lei + I{Rdl
for r = 0 1

0

Add Indirect the contents the data

ANl A, =- data

(AI· (AI AND data

ANl A, Rr

(AI - (AI AND (Rd
for r -"- 0 7

d7

d6

d5

0

d4

1

Add Indirect With carry the contents of
data memory location 10 the
Accumulator.

Immediate Data

d7

d6

o

Logical and contents of designated
register With Accumulator.

ANL A,@Rr

(AI ,- (AI AND (IRd)
tor r = 0 1

CPL A

{AI

+

NOT (AI

Complement the contents of the
Accumulator

ClR A

(AI

+

0

CLEAR the contents of the Accumulator

d5

0

Logical and Indirect the contents of data

memory

OAA

With

Accumulator

DECIMAL ADJUST the contents of the
Accumulator
(AI· (AI

INCA

(AI· (AI + 1

ORLA, = data

(Ai

+

DECREMENT by 1 the accumulator's

l'

DEC A

by 1 the accumulator's

(Ai OR data

Logical OR specified Immediate data
With Accumulator

d7

(AI· (AI OR (Rr)
for r =
7

Logical QRcontents of deSignated
register With Accumulator.

(AI, (A) OR ((Rr))
for r =
1

Logical OR Indirect the contents of data
memory location With A(;cumula.tor.

RL A

~AN +

11 - IAN)
lAO} +- (A71
for N = 0 -- 6

Rotate Accumulator left by '·bl! Without
carry.

Rle A

IAN + 1) +- (ANI; N =
(AOI +- ICI
IC)-- (A71

a

6

Rotate Accumulator left by 1-blt throuqh
carry.

RR A

(ANI +- (AN + 1 I; N = a
(A71 + lAO)

6

Rotate Accumulator right by l-blt
Without carry.

(AN) +- (AN + 1 I; N ;. 0 - 6
(A7)' (CI
lAO)

Rotate Accumulator right by l-bl!
through carry

SWAP A

(A4_7l .' (A O - 3)

Swap the 2 4-blt nibbles
Accumulator

XRL A, =-data

(AI' (AI XOR data

logical XOR speCified Immediate data
With Accumulator.

a

a

d6

d5

d4'

d6

d5

d4

d3

d2

a4

a3

a2

al

ao

o

ORl A. Rr
ORLA,@Rr

RRC A

a
d6

(C)'-

In

the
1

d7

o

XRL A, Rr

(A) -- IAl XOR IRrl
for r = 0 - 7

Logical XOR contents of deSignated
register With Accumulator.

XRLA,@Rr

(AI' (AI XOR ((Rrll
for r =
1

Logical XOR I ndlfect the contents of data
memory location With Accumulator

+- (Rr)
l;r
If (Rr) ~ 0
(PC 0 - 7) +- addr

Decrement the speCified register and

a-

1

1

BRANCH
0- 7

DJNZ Rr, addr

(Ar)

JBb addr

(PC
7) <-- addr If Bb = 1
(PC)' (PC) + 2 Ii Sb = 0

Jump to speCified address If
Accumulator bit IS set.

JC addr

{PC 0 - 7} +- addr If C = 1
(PC) - (PCl + 2 If C " a

Jump to specified address If carry flag

a-

b2
87

JFO addr

(PC 0 -- 7) +- addr Ii FO -" 1
(PCI . IIPCI + 2 If FO =

Jump to specified address

JFl addr

(PC 0 7) +-addr If Fl = 1
(PCI' (PCI + 2 If FlO

Jump to speci/,ed address If Flag Fl

JMP addr

(PCB 10)- addrB 10
(PC 0 - 7)·- addr 0 7
IPC 11) - DSF

Direct Jump to
the 2K address

JMPP@A

(PC 0

Jump Indirect to speCified address With
With address page

JNC addr

(PC a
71
addr If C = 0
(PC)' (PC) + 2 If C ~ 1

JNI addr

(PC 0
(PC)'

a

7)

+

+

(IAI)

If

bl
a6

bO

a5

II

0 .

Flag Fa IS

O·

IS

'0'

addles> Within

Jump to specified address If carry flag
low

71 - addr If I ~ 0
Jump:o speCified addres_s If. l(lterrupt
(PC) + 2 If I l l s low

'4

IS

CJ7

a6

a5

04

a3

d2

al

aO

a7

a6

a5

a4

.a
83

a2

al

aO

243

P. PD8049/80S9
INSTRUCTION SET" (CONT.j
MNEMONIC

.,.,

DESCRIPTION

FUNCTION

.. ,~LAGS

INSTRUCTION CODE

0&

D.

D.

'5
0
'5
0
8S
0
'S

8.
0

03

0,

DO

, ",

'0
0
'0
0
'0
0
80
0
'0
0
'0
0
80

02

CYCLES

BYTES

BRANCH (CONT.)
(peD 71 ...... add'"ifTO-O
(PC) +- (PC) + 2 if TO= 1

Jump to specified address if Test a is low.

JNT1 addr

(PCO-71-addr iln

Jump to specified address

JNZaddr

(PC 0 - 7) ...... addr if A" 0
(PC) - (PCI + 2 if A = 0

Jump to specified
is non-zero.

(PC 0- 7)-addr if TF = ,
(PC) +- (PC) + 2if TF '" 0

Jump to specified address If Timer Flag

JTOaddr

(PC 0 - 71- addr if TO = 1
(PCI- (pCI + 2 if TO'" 0

Jump to specified address if Test 0 is a I.

JT1 addr

(PCO-71-addr if T1 ;: 1
(PCI +- (PCI + 2 If T1 = 0

Jump to specified address if Test 1 is a 1.

(PCO-7) -addr if A = 0
(PCI - (PC) + 2 if A I

Jump to specified address if Accumulator
is 0.

JNTOaddr

(pel

JTF addr

JZaddr

<-

=

0

If

Test 1

IS

a.

a~dre5s

If accumulator

is set to 1.

EN I
DIS I

Disable the External Interrupt input.
Enable the Clock Output pin TO.

ENTO ClK

,

as

'7
0
'7
0
'7
0
'7

'6
0
'6
0
'6

,

,
, ,
'6

SEl MBl

(DBF)" 1

SElRBO

(BS)

SEl RS1

(BS)·- 1

Select Bank 1 (locations 24 - 311 of
Data Memory.

(A)· data

Move Immediate the speCified data Into
the Accumulator.

=data

(A) - (tRr)); r = 0 - 1

Move Indirect the contents of deta
memory location into the Accumulator.

MOVA.PSW

IAI-·IPSWI

Move contents of the Program Status
Word into the Accumulator.

MOV Ar, = data

(Ar) -data;r = 0- 7

Move Immediate the specified data into
the designated register.

.... tAr); r '"' 0- 7

tAr) - (A); r,- 0··7

=data

((Rdl- (AI; r·

a- 1

((RrI)'" data;r = 0- 1

0
d7

8_

,0

Move Indirect Accumulator
into dete memory location.

, ",
, ",
, ",

82

'2

, ",

82
82

8,

...

,
d7

d_

,

d3

0
d2

d6

, , ,

,

d_

d3

d2

0
d3

O·
d2

d5

IPSWI-IAI

Move contents of Accumulator into the
program status word.
Move data in the current page IOta the
Accumulator.

,
d7

MOVX A.@A
MOVXOR. A

IIRr)) .... (Al;r;; 0-1

Move Indirect the contents of the
Accumulator into external data memory.

XCH A.Rr

(A);! (Ar);r:ll 0-7

Exchange the Accumulator and
designated register's contents.

0
d6

, ,
dS
0

d,

Move Program data in Page 3 into the
Accumulator.
Move Indirect the contents of external
data memory. into the Accumulator.

XCHA.@Rr

IAI;:;IIR,II;

XCHD A.@lRr

IA 0- 31 :!;IIMI
r=0-1

Exchange Indirect 4-bit contents of
Accumulator and data memory.

CPLC

Complement ~ontent of carry bit.

CPLFO

ICI-NOTICI
IFOI- NOT IFOI

Complement Content of Flag FO.

CPl F1

IFII' NOT IFII

Complement Content of Flag F1

ClR C
CLR FO

ICI' 0
IFOI-O

Clear content of F le9 0 to 0.

CLR F1

IFII" 0

Clear content of Flag 1 to O.

Exchange Indirect contents of Accumulator and location in data memory.

FL Gs

Clear content of carry bit to O.

, ,
d,

dO

d,

,..

dO·

0

Conte~ts

IPCO-71-.IAI
IAI-IIPCII
IPCO- 71-IAI
tPC8- 10j .... 011
IAI' IIPCII
(A)-I(Rrll;r=O-l

,-0-'
0- 311;

,
dS

,.

Move Immediate the specified data into
data memory.

MOVPA.@A

244

"

'2 .

Move Accumulator Contents into the
designated register.

MOVPSW, A

MOVP3A.OA

0
d6

Move the contents of the designated
registers Into the Accumulator.

MOVA.@Rr

MOV@ Rr.

8.

'2

Select Bank 0 (locations 0 - 7) of Data
Memory.

t~)

MOV@Rr.A

0
8S
0
'5

2.
'2

Select Bank 1 lIocations 2048 - 4095) of
, Program Memory.

0

MOVA. Rr

MOV Rr.A

's

0

DATA MOVES
MOVA,

,

'',.,.
',,.

0
83
0
'3
0
'3
0
'3
0
'3
0
83
0
'3

Select Bank a (locations 0 - 20471 of
Program Memory.

(OBF) - 0

ot-

0
'6

'7
'6
CONTAOL

Enable the External Interrupt input.

SElMBO

low.

(PC) + 2 if T1 = 1

0
'7
0
'7

'0

0
d,

,
dO

C At

FO

F,

INSTRUCTION SET (CaNT.)

}L P 08049/8039
INSTRUCTION CODE

MNEMONIC

FUNCTION

07

DESCRIPTION

06

05

04

03

02

FLAGS
01

00

CYCLES

BYTES

C AC

FO

F1

INPUT/OUTPUT
ANL BUS, #: data

(BUS)

Logical and Immediate--specrtied data
With contents of BUS.

1
d7

ANL PP. # data

(Pp) +- (Pp) AND data
p = 1 . 2

Logical and Immediate specified data
With designated port (lor 21

d7

d2

ANLD Pp. A

(Pp)

Logical and contents of Accumulator with
deSignated port (4 .- 71.

1

1

IN A, Pp

(A)

+-,

(Pp); p = 1 -- 2

(A)

+-

(BUS)

(BUS) AND data

+-

<-

(Pp) AND (A 0 - 3)

p=4-7

INS A, BUS
MOVD A, Pp

(A 0- 3)

+-

(A 4·- 7)

+-

Input strobed BUS

data into Accumulator.

(Pp\; p = 4 - 7

Move contents of designated port 14

0

Into Accumulator.

(Pp) -A 0- 3;p=4 - 7

Move contents of Accumulator to
designated port (4 71.

(BUS)..- (BUS) OR data

Logical or Immediate speCified data with
contents of BUS

ORLO PP. A

(Pp)

Logical or contents of Accumulator With
designated port (4 - 7).

(Pp) OR (A 0 - 3)

p=4-7
OAL Pp.:t:: data

IPp) <- (Pp) OR data
p= 1- 2

Logical or Immediate specified data With
deSignated port (1 21

OUTL BUS, A

(BUS)

Output contents of Accumulator onto
BUS.

OUTL Pp, A

(Pp)

DEC Rr

(Ar} ..... (Arl" 1;r"'O-7

+-

(A)

(AI; p

=

dO

o

P.
dO

1 - 2

0

7J

MOVO pp. A

+-

d2

Input data from designated port;1 - 2)
mto Accumulator.

OR L BUS, .. data

+--

0
d6

d7

d7

d6

d6

d5

d4

0

0

d5

d4

d3

d2

d,

dO

d3

d2

p
d,

dO

0

P

0

Output contents of Accumulator to
deSignated port (1
21.
REGISTERS

(Rr)

INC Ar

(Rr)-(Arl+l;r=O

INC@Rr

(IAr)) <- ((Rd) + 1;
r = 0 - 1

CALL addr

((SP))

7

Decrement by 1 contents of deSignated
register.
Increment by 1 contents of deSignated
register.
Increment Indirect by 1 the contents of
data memory location.
SUBROUTINE

<-

(PC), (PSW 4

7)

Call deSignated Subroutine.

(SP) <- (SP) + 1
(PC8-10)"-addr8-10
(PC 0 - 7) ..... addr 0 - 7
(PC 11) <- DBF
RET

(SP) <- (SP) - 1
(pel .- {(SP))

Return from Subroutme without
restonng Program Status Word.

AETR

(SP) .... (SP) - 1
(PC) <- ((SP))
(PSW 4 - 7) ..... ((SP))

Return from Subroutine restoring
Program Status Word.

"0

'9

'R

'7

'6

'5

'4

'3

'2

"

'0

TIMER/COUNTER

0

EN TCNTI

Enable Internal Interrupt Flag for
Timer/Counter output.

DIS TCNTI

Disable Internal interrupt Flag for
Timer/Counter output.

MOVA, T

(A) -- (T)

MOV T, A

(T) <-(A)

Move contents of Timer/Counter
Accumulator.

InTO

Move contents of Accumulator into
Timer/Counter.

STOP TCNT

Stop Count for Event Counter

STRT CNT

Start Count lor Event Counter.

STRTT

Start Count for Timer

NOP

No OpE"ratlon performed

MISCELLANEOUS

Notes:

o

0

G)

Instruction Code DeSignations rand p form the bmary representatIOn of the RegIsters and Ports Involved

@
@
@)

The dot under the appropriaTe flag bit indicates that its content IS subject to change by the Irlstructlon It appears In

II

References to the address and data are specified in bytes 2 and/or 1 of the InstructIon
Numerical Subscripts appearing in the FUNCTION column reference the specific bits affected.

Symbol Definitions:

SYMBOL
A
AC
addr
8b
8S
8US
C
CLK
CNT
0
data
D8F
FO. Fl
I
P

DESCRIPTION
The Accumulator
The Auxiliary Carry Flag
Program Memory Address (12 bits)
Bit Designator (b - 0 ~ 7)
The Bank Switch
The BUS Port
Carry Flag
Clock Si nal
Event Counter
Nibble Designator (4 Qits)
Number or Expre$sion (8 bits)
Memory Bank Flip-Flop
Flags 0.1
Interru t
"In-Page" Operation Designator

SYMBOL
Pp
PSW
Rr
SP
T
Tf
TO. Tl

X

"

@

$

Ixl
Ilxll

-

DESCRIPTION
Port Designator (p - 1, 2 or 4 - 7)
Program Status Word
Register Designator (r - 0, 1 or 0 - 7)
Stack Pointer
Timer
Timer Flag
Testable Flags 0> 1
External RAM
Prefix for Immediate Data
Prefix for Indirect Address
Pr()gram Counter's Current Value
Contents of External RAM location
Contents of Memory location Addressed
by the Contents of External RAM location.
Replaced By

245

:". PD804918039
A

H=l-- K ...
,
JI

..

..

.'. ,.'

[I
u
"
, -B~ ___-1~~~

....

.

•.•.

. . ,.

I

--g--

':

':

~

1 1.
~

I ...... Ii .. ~
J

G

II.

~
- - - - - -- -

PACKAGE OUTLINES
.PD8049C1D
/lPD8039C/D

M

0° - 15°

I--

Plastic
ITEM

MILLIMETERS

A

51.5 MAX

INCHES
2.028 MAX

B

1.62

0.064

c

2.54 ± 0.1

0.10 ± 0.004

D

0.5 ± 0.1

0.019 + 0.004

E
F

48.26

1.9

1.2 MIN

0.047 MIN

G

2.54 MIN

0.10MIN

H

0.5 MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

0.225 MAX

K

5.72 MAX
15.24

L

13.2

0.520

M

0.25

+0.1
0.05

0.600

+ 0.004
0.010 _ 0,002

Ceramic
ITEM
A

B
C
D
E

MILLIMETERS
51.5 MAX
1.62

2.54+0.1
0.50 + 0.1
48.26 ± 0.2

INCHES
2.028 MAX
0.064
0.100 + 0.004
0.0197 + 0.004
1.900 + 0.008

F

1.27

0.050

G

3.2 MIN

0.126 MIN

H

1.0 MIN

0.04 MIN

I
J

4.2 MAX

0.17 MAX

5.2 MAX

0.205 MAX

K

15.24 ± 0.1

0.6 ± 0.004

L

13.5 _ 0.25

0.531~ ~:~:

M

0.30 ± 0.1

0.012 ± 0.004

+ 0.2

SP8049/8039-9-78-GN-CAT

246

'ttiEC

NEe Microcomputers, Inc.

JLPD371

MAGNETIC TAPE CASSETTE/CARTRIDGE'
CONTROLLER
DESCRIPTION

The NEC IlPD371 is a high performance N-Channel LSI tape cassette/cartridge
controller designed to interface between mo~t cassette or cartridge tape drives and
most microprocessors or minicomputers.
The IlPD371 converts 8-bit parallel data into serial phase encoded data til..be wrhten on
tape and converts phase encoded data read from tape into 8-bit parallel data, calculates
the CRC during write operations, verifies the CRC during read operations, informs the
processor program when to send data bytes during write operations and when to read' '
bytes during read operations, convertnape drive status signals into register ,bit levels
which may be read by the processor program and converts software commands into
signals which may be understood by the tape drivels).
The IlPD371 read and write data paths are completely separate to allow read-after-write
data verification.
The IlPD371 places no limitation on the selection of tape speed si(lce the IlPD371
maximum data transfer rate is considerably faster than that of the' fastest cassette or
, cartridge drive.

FEATURES

• Compatible with ANSI, ECMA and ISO standard
•
•
•
•
•
•
•

PIN CONFIGURATION

Also compatible with most other standards
Hardware CRC generatiCln and verification
Read-after-write capability
High speed file search
Multiple drive capability
May rea,j.or write on one drive while rewinding or file search.ingon',another
Maximuni Data Transfer rate of 375K bits/sec'eql,livalen,tto 468 'IPS at 800 BPI

MBH

AJVL

VDD
DB7

Vcc
RST

DBS
DB5
DB4

WCK
DO

DB3
DB2
DB1
DBO
W/R
OS

C1
WD
GAP
SG
RD(-I
RD(+I
MKI

RSo

MKO

RS1

S1

RS2'
DT

G3
'C2

UA

S2

RW1

S3

RWO
1
VBB

REO
2
VSS

247

/-L PD371
ABSOLUTE MAXIMUM
RATINGS*

O°c to +70°C
. -40°C to +125°C
. - 1 to +8 Volts G:;
-1 to +8 Volts CD
-1 to +16 Volts CD
-1 to +16 Volts CD
-1 to +8 Volts CD
.. -10toOVolts

Operating Temperature
Storage Temperature.
All Output Voltages
All Input Voltages ..
Clock Voltages . . . .
Supply Voltage VDD
Supply Voltage VCC .
Supply Voltage VBB .

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability,

*T a =25°C
Note:

Ta

CD

VBB = -5V ± 5%. All voltages measured with respect to GND.

a - 70°C VDD = +12V ± 5% VCC
PARAMETER

SYMBOL

+5V ± 5% VBB

-5V ± 5% VSS = OV

LIMITS
MIN

Input High Voltage

VIH

+3.0

Input Low Voltage

VIL

a
+3.5

Output High Voltage

VOH

Output Low Voltage

VOL

Clock Input High Voltage

VOH

+9

Clock Input Low Voltage

VOL

a

Input Leakage Current
Input
DBa - DB7
Leakage All Except DBO Current DB7 (-25K
Internal Pull-upsl

TYP

MAX
VCC
+0.8

UNIT

TEST CON DITIONS

V
V
V

IOH=-1 mA

+0.4

V

IOL -+1.7mA

VDD
+0.65

V

ILiH

+10

VI =+3.0V

III L 1

-10

Il A
Il A
mA

VI = +O.4V

-1.0

III L 2

DC CHARACTERISTICS

V
VI = +0.8V

Clock Input Leakage Current

ILOH

+20

IlA

VO=+9.0V

Clock Input Leakage Current

ILOL

-20

Il A

Vo - +0.65V

Output Leakage Current

ILOH

+10

IlA

Vo = +3.5V

Output Leakage Current

ILOL

-10

Vo = +O.4V

Power Supply Current (V DD )

100

+20

IlA
mA

Power Supply Current (V cci

ICC

+30

Power Supply Current (VSBI

ISB

-2

mA

mA

CAPACITANCE
PARAMETER

LIMITS

SYMBOL
MIN

248

TYP

MAX

UNIT

TEST CONDITIONS
fc = 1 MHz. All pins
except measuring pin
are grounded.

Clock Capacitance

Co

35

pF

Input Capacitance

CIN

10

pF

Output Capacitance

COUT

20

pF

I

pPD371
AC CHARACTERISTICS

Ta = 0 - 70°C, VDD = +12V ± 5%, VCC = +5V ± 5%, VBB = ,.5V.± 5%, VSS "CU

PARAMETER

LIMITS

SYMBOL
MIN

TYP

UNIT

Clock Period

tcy

Clock Rise and Fall Times

t r,

1 Pulse Width

tl

60

2 Pulse Width

t2

220

ns

1 to 2 Delay

-.to 1

0

ns

11'

'TEST CONDITIONS

MAX.

480

5000

ns

0

50

ns

.

'"

~

ns

..

2 to 1 Delay
Delay 1 to 2 Lead Edges

t02

' 70

tD3.

sO

Data Out Delay from 1

tOOl

480

ns

Data Out Delay from 1

tOD2

ns

lTTL & CL - 3GpF

RSO - RS2 to Output Delay

tACCl

260
. -300

ns

lTTL&CL=30pF

OS, W/R to Output Delay

tACC2

200

ns

lTTL & CL - 30 pF

DBO - DB7 to 2 Setup
Time

. ,tlSl

250

Time

tlS2

350

OS, W/R to2 Setup Time

1"163

150

Input Hold Time from 2

tlH

30

ns

ns
lTTL & CL = 30 pF

n,

RSO - RS2 to 2 Setup

..

ns
ns
~

ns

TIMING WAVEFORMS
1 and ¢2 are MOS level (12V) clock pulses. The timing of ¢1 and 4>2 is shown
in the Timing Diagram.

WRITE DATA

Phase encoded data to be written on tape leaves the IJ.PD371 at pin 36.

TAPE DRIVE COMMAND
AND STATUS
37

C1

27

C2

28

C3

29

S1

26

S2

25

S3

Cl, C2 and C3 are general purpose tape drive commands.
Cl, C2 and C3 are set and reset by the software manipulation of bits 5, 6 and 7,
respectively, in Write Register 3. Since el, C2 and C3 are defined by software,
they may be configured for any purpose. Typical uses for C1, C2 and C3 are
WRITE ENABLE, FORWARD and REVERSE.
S" S2 and S3 are general purpose tape drive status inputs. Their logic levels
are indicated by bits 3, 4 and 7 of Read Register 1, respectively. Typical tape
drive status signals are WRITE PERMIT, CASSETTE IN PLACE and SIDE.
The IJPD371 can adapt to any tape drive status signal set with ~ slight change
in software.

DUAL TAPE DRIVE SYSTEM
COMMAND AND STATUS
17

UA

Unit
Address

19

RWO

Rewind a

Rewind Command for Drive a.

18

RW1

Rewind 1

Rewind Command for Drive 1.

30

MKO

Marker a

EDT/BOT status from Drive a.

31

MK1

Marker 1

EOT /BOT status from Drive 1.

32

RD(+)

Read
Data ~+)

A positive pulse from the tape drive at each positive transition in the read data.

RDH

Read
Data (-I

A

Selects Drive a v$l(!n low and Drive 1 when high.

READ DATA

33

posi~ive

pulse from the tape drive at each negative transition in the read data.

MISCELLANEOUS
1
42

I
I

MBH
AWL

I

I

MBH must be tied to the Vr:r: (+5V) supp'ly.
AWL 'is a logic low output under all normal operating conditions of the IJPD371.

POWER SUPPLY VOLTAGES

+12V

2

VDD

41

VCC

+5V,

22

VSS

Ground

VBB

-5V

21

Note:

250

CD Refer to diagram on follOWing page.

PIN IDENTI FICATIONG)

).I. PD371
PIN IDENTIFICATION
(CaNT.)

PROCESSOR INTERFACE

TAPE DRIVE INTERFACE

Aeset

REGISTER

{

SELECT

40
Write 'Data

Register Write/Read Select, 11
.
' 12
RegIster Data Strobe

OS

Drive Command 1

ASO

Drive Command 2

Register Select 1 14

AS,

Driv"e Command 3

Register Select 2

RB2

Register Select 0

COMMANOS

,3

,S

}

~RIVl:

TO

TAPE

WIA

Drive Status, 1

Interrupt Request

AEO

TAPE DRIVE

Drive Status 2

CQMMAND

Diive Status 3

AND STATUS

DBa
DB,
DB2
OB3

I&PD371

UA

AW,

DB4
DBS

Drive Address (1/0)
Rewind Command Drive 0

Rewind Command Drive 1
Drive 0 EDT/BOT Sra"Tus

MK,

DBS

Drive 1 EDT/BOT Status

DB,

WeK

RD(+)
ROt)

Read Data
PosiTive Transitions
Read Data

}

FADM

TAPE DRIVE

Negative Transitions
GAP

TIMING

Data Transition

DO

!\!1BH

Must be High (+5V)

SG

AWL

Always Low

}

MiSe

DT

MOS

lEVEL
CLOCKS

Von Vee Vss Vas

+11V

PACKAGE OUTLINE
}lPD3710

l~

,A,

+sv ov -5V

krJF=1

H~iVVVVVVVVViiVVVVuWiuVi=tt
B I :=:-___ --11- -0
~ c t--"-jFI-"-- .1

ITEM

MILLIMETERS

A

53.5 MAX

C

2.54

0.10

D

50.80

F

1.27

0.05
0.10 MIN

G

2.54 MAX
1.0 MIN

0.04 MIN

I

4.2'MAX

0.17 MAX

5.2 MAX

0.21 MAX

15.24

L

13.50

M

0.3_,

~
,- .

II

2.0

H

J

150

INCHES

0.05

K

-

2.1 MAX

1.35

B

MOO

0.60
0.53
0.012

251

JL,PD371
From the point of view of'the processor program, the J.lPD371 makes the tape drive
(or multiple drive system) appear as ten addressable registers. The program controls
the drive(s) and transmits data to be written on tape by manipulating bits in the six
J.lPD37j Write Registers. The program senses the status of the drive(s) and reads data
stored on tape by reading bits from the four'J.lPD371 Read Registers.

REGISTER ADDRESS

~--r---~--'---~

REGISTER
NAME

BIT-NUMBERS

~-'----r---v---'----r---r---'---4

o

7

WRITE REGISTERS
o

o

o

o

o

o

WRo IRST I MBL I SRS I WME IWCR I

X

IWMD I GNT

WR, I WRRIRRRI x I RREIRRDIGREIGRDI
o

o

WR2 I WD71 WD61WD51 WD41 WD31WD21 WD,I WDO
WR3 I C31 C21 c, I RRI I RW I

WRs

0

I
0

X

X

I

X

Ix I RME IRMD I

X

I

X

I

WR6
I

X

X

I

X

I

X

X

I

I

X

I

X

I

X

X

I

X

X

I

I

I UA I

READ REGISTERS
0

0

0

0

0

0

0

RRO

I AWH IAWL I C21 C3 IRDFIGROIWROIRROI

RR,
I

0

0

0

0

0

S3 I MK IMKFI S2

I Rw'l c, I UA I

RR2
RR3

IDOE ICOR [NBR INAR I
I WD I GPF IREC I CRENOTUSED
X

252

S,
I

=

ADDRESSABLE INTERNAL
REGISTERS

p.PD371

ADDRESSABLE
INTERNAL REGISTER
BIT
!DENTI FICATION

BIT

SYMBOL

NAME

WRITE REGISTER
GNT

Gap Noi,se Tal erance

1

WMD

Write Mode Disable

2

-

3

WCR

4

WME

Write Mode Enable

5

SRS

Status Reset

6

MBL

Must Be Low

7

RST

Reset

WriteCRC

UA

-

Unit Address
Not used

READ REGISTER

a

a

,

RRO

Read Request,

WRO

Write Request
Gap Request

2

GRO

3

RDF

Read Flag

4

C3

Command'3
'Command 2

WRITE REGISTEF,j 1

5

C2

-

Not used

6

AWL

Always Low

7

AWH

Always High

GRD

Gap Request Disable

2

GRE

Gap Request Enable

3

RRD

Read Request Disable

4

RRE

Read Request Enable

5

-

6

RRR

Read Request Reset

7

WRR

Write Request Reset

Not used

WRITE REGISTER 2
WDOWD7

Write Buffer Register

READ REGISTER'

a

,

UA

Unit Address

C,

Command'

2

RW

Rewind

3

S,

Status'

4

S2'
MKF

Status :1

5
6

MK

Marker

7

S3

Status 3

WRITE REGISTER 3

a

-

Not used
Not used

2

-

,

NAME

WRITE REGISTER 6
0,
, -'7

Not used

,,

0-7

SYMBOL

a

a

a

BIT.

READ REGISTER 2
0-7

Not used

3

RW

Rewind

4

RRI

Rewind Reset Inhibit

5

Marker Flag

ROO R07

Read Buffer Register

READ REGISTER 3

0

NAR

1

NBR

Noise Before Record

2

COR

Comma'nd Overrun

Noise After Record

C,

Command One

6

C2

Command Two

7

C3

Command Three

WRITE REGISTER 4

5

REC

Record Detection

-

-

6

GPF

Gap Flag

7

WD

Write Data

Not used

WRITE REGISTER 5

a

,

-

-

Not used

2

-

Not used

3

DOE

Drop Out Error

4

CRE

CRG Error

II

Not used

3

RMD

Read Mode Disable

4

RME

Read Mode Enable

5

-

Not used

6

-

Not used

7

-

Not used

SP371-B-77-GN·CAT

253

I

NEe

NEe Microcomputers, Inc.

,uPD372

FLOPPY DISK CONTROLLER
OESCR IPTION

The I1PD372D is a single LSI floppy disk controller chip which contains the circuitry
to read, write, track seek, load and unload the head, generate and detect CRC
characters, and perform all other floppy disk operations. It is completely compatible
with the IBM, Minifloppy*TM, hard sector, and other formats and controls up to
4 floppy disk drives. The I1PD372D may be interfaced directly to a host processor;
or to a controller processor first,"which in turn is interfaced to the host. These
processors do not necessarily have to be of the 8080A type.
Data transfers to and from the I1PD372D are done through addressable internal
registers. These internal regsiters allow a large variety of system architectures to be
configured; they provide status information on the drive, as well as perform data
transfers between the drive and the processor.
The I1PD372D issues interrupts to the processor upo~ detection of an address mark
and then when each subsequent data byte is available during either reading or writing.
An 8·bit bi·directional data bus and 5 register select lines provide access to the 9
internal registers' contents. An internal interval timer is provided which facilitates
performing such drive timing functions as: stepping rate, head settling time, track
settling time, etc.
*TMShugart Associates.

FEATU R ES

• Compatible with IBM 3740 format
• Also compatible with other formats including Minifloppy and hard sector
• Controls up to four floppy disk drives
• Can perform overlap seeks
• Input and output TTL compatible (except for ¢1 and ¢2)
• Interfaces to most microprocessors including 8080A
• Standard power supplies (+12V,+5V and -5V)
• Controls most floppy disk drives including:
CALCOMP 140, 142
ORBIS 74,76/77
CDC BR803
PER SCI 70, 75
INNOVEX 210, 410
REMEX RFS 7400
PERTEC FD400
SHUGART SA400 (Minifloppy)
POTTER 004740
WANGCO 82 (Minifloppy)
GSI M0050 (Minifloppy)
SHUGART SA900,SA800
GSI110

PIN CONFIGURATION

RST-r-:----..

,,2
,,1

W/R

os

VDD

RS2
RS,

vcc
DB7

RSo

DBG

lOX

DBS

WFT

DB4

TOO

DB3

RCK

DB2

RD

DB,

RYA

DBa

WCK

UAo

RYS

UA,

CKS

USo

AWL

UB,

REO

SOS

WD

SID

HLD

WE

VSS
VBB

'--_ _ _ _ _ _.r

WFR
LCT

Rev/2
255

JLPD372
Temperature Under Bias
.... ... ... .
. ... o°c to +70°C ABSOLUTE MAXIMUM
Storage Temperature. . . . . .
-40°C to +125°C
RATI NGS*
All Output Voltages.
. . .. . . . .
. :-1.0to +8 VoltsQ)
. -1.0 to +8 VoltsQ)
All Input Voltages ..
Clock Voltage .....
-1.0to+16Volts(j)
Supply VOltaqe VDD
-1.0 to +16 Volts(j)
Supply Voltage Vcc . . . . . . . . . .
. -1.0 to +8 V~lts(j)
Supply Voltage VBB . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . .. 10 to +0 Volts
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of 'this specification is-not implied.
Exposure to absolute maximum rating conditions, for extended periods may affect device reliability.

"r a = 25°C
Note: (j) VBB = - 5V ± 5%
DC CHARACTERISTICS

Ta = -70°C, V DD = +12V ± 5%, VCC = +5V ± 5%, V BB = ~5V ± 5%, VSS = OV
LIMITS
PARAMETER

SYMBOL

MIN

High Level Input
Voltage

V IH

Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage

TYP

MAX

UNIT

+3.0

VCC

V

V IL

0

+{l.8

V

V OH

+3.5

TEST
CONDITIONS

V

IOH=-1.0rnA

VOL1 0

+0.5

V

10L = +1.7 rnA

VOL2G)

+0.5

V

10L -+3.3 rnA

High Level Clock
Voltage

V1>H

+9

V DD

V

Low Level Clock
Voltage

V1>L

0

+{l.8

V

High Level Input
Leakage Current

ILiH

+10

IJ.A

VI = +3.0V

Low Level Input
Leakage Current

ILiL

-10

IJ.A

VI

High Level Clock
Leakage Current

IL1>H

+10

IJ.A

V1>

Low Level Clock
Leakage Current

IL1>L

-10

IJ.A

V1> = +0.8V

High Level Output
Leakage Current

I LOH

+10

IJ.A

Vo

= +3.5V

Low Level Output
Leakage Current

I LOL

-10

IJ.A

Vo

= +0.5V

Power Supply
Current (V DDI

IDD

+20

rnA

Power Supply
Current (V CCI

ICC

+23

rnA

Power Supply
Current (V BBI

IBB

Notes:

CD

CKS, REO, UA O' UA 1, UB O' UB 1, DBO-DB7'

~ WD, HLD, LCT, WE, WFR, SOS, SID.

256

-2

.

rnA

= +0.8V
= +9.0V

AC CHARACTERISTICS

Ta

=0

= +12V

-70"C Voo

+5% Vee

= +5V

+5% VaB

=:

JI. PD372

-5V +5% Vss = OV

LIMITS
PARAMETER

SYMBOL

Clock Period

tcy

MAX

UNIT

480

7.000

ns

0

50

ns

TYP

MIN

Clock Rise and Fall Times

tr,tf

(,'), Pulse Width

t(:) 1

60

ns

(:)2 Pulse Width

t':)2

90

ns

r'"!1 to (;)2 Delay

'0

1.)2 to r;)1 Delay
Delay 01 to (12 Leading Edges

Data Out

Del~v

from. (;)1

@
~

Data Out Delay
from (:>2

WD Delay Time
Data Out Delay from

Rs 2

OS' W/R'

0

ns

'02

70

ns

'03

100

ns,

TOOl

90

ns '

1 TTL and Cj = 30 pF

'002

200

ns

1,TTL and Cj - 30 pF

200

ns

2 TTL and Cj - 50 pF

'003

no

ns

2 TTL and Cj

to0 4

200

ns

Data Setup Time to (;)1

1JSl

150

ns

Data Setup Time to r;')2

1JS2

120

ns

Data Hold Time from (),

1JHl

10

ns

Data Hold Time from (:)2

1JH2

10

WD pulse width

'wo

'03-40

@,

Input pulse width

No'es:

TEST CONDITIONS

tw

= 50 pF

ns
ns

'03

'Cy+150

AS

,

CD

CKS, AWL, REO, UA O' UA 1, UB O' UB 1,

@

HLb, LCT, WFR, WE, 50S, 510.

G)'

lOX, RYA, RYB, RST, WFT, TOO' WCK, RCK.

I------"v - - - - - I

TIMING WAVEFORMS
0'

0,2
'02

INPUT

1

OUTPUT

OUTPUT

WD

DBa
INPUT

II

7

RS 2

WIR

os
OUTPUT

INPUT

DS -

tOOl
OBO_7

RSQ,,0

WiR RS 2

--I'"!'---Jt'--

G)

Notes:'~ lOX, RYA,

RYB, RST, WFT, TOO, WCK:RCK.

.

2 CKS, WFR, SOS, SID', REO, HLD. UA o , 1, UB",l, WE, LCT.
~nput must not make lev,el transition within tlS1 and
tlH1 times, or register contents may be modified.

3 RSO' RS,

CD The logic condition which plac~s J..lPD372 i':lformation on·{)BO_7

IS DS· W/R· RS 2 - Care must be taken·to iri~ure'that this condition
IS not met inad~ertei1tIY If OS, W/R and.RS2 .are allowed tQ 'change
state asynchronously.
'

257

r·

J.I. PD372'
~200

ns---1

Raw Data

°1

from Floppy
Drive

-

'..

1 s

2 J.lS
Mi;sing

III

3

4

}is

I

Early

READ CLOCK (RCK) AND
READ DATA (RD) REQUIRED
BY J,lPD372

J.L5

I

- , , , . - - - - ' - - - - - .•....,..;.' - - - ' - - - ,
U
.....
LJ-4-i...:

(pin 101 RCK

(Pin11IRD

- i §I-- -'S :
---'CY -150 ns
x=J..

RD must be Stable

?2 'CY + 100 ns

Notes:

CD

tey = 4>1 Clock Period

@T1?ICy+160ns

@
PIN
ND.
1

SYMBDL
RST

NAME

T2?ICY + 160 ns

PIN IDENTIFICATION

INPUTI
OUTPUT CONNECTION

FUNCTION

Initializes internal register,s. counters

Reset

and F/F's

2

W/R

Register Write/
Read Select

3

DS

Data Strobe

4·6

RS"
RS1
RS2

Register Select

7

IDX

Index

W/R = 1 implies OBO_7 data written
into pP0372 registers
Processor

Internal Register Select
Pulse Signal that indicates start of
Input

8

WFT

Write Fault

9

TOO

Track 00

08 0 _7 Write and read strobe

Disk track
Write Fault Signal

FDD

Indicates that Head is positioned on

Track 00
10

RCK

Read Clock

11

RD

Read Data

12

RYA

Ready A

13

WCK

Write Clock

14

RYB

Ready B

15

CKS

Clock States

16

AWL

Always Low

Indicates that FDD A is Ready

Processor
FDD

Indicates that FOD B is Ready

Always a logic zero

17

REQ

Request

18

WD

Write Data

Serial Write Data (Clock & Data
Bits)

19

HLD

Head Load

Command which causes R/W head
to contact disk

22

LCT

Low Current

Processor

Interrupt Request

Command to lower write current
for inner tracks

Output

23

WFR

Write Fault Reset

24

WE

Write Enable

25

SID

Step In or Direction

R/W head step control

26

SOS

Step Out or Step

R/W head step control

27-30 UAO. UA1
UBO. UB1

FDD Select

31·38 DBO·7

Data Bus

258

FDD

Signal to reset write fault latch

FOO Unit Select
Input!
Output

Processor

Bi-directional diHa bus

II. PD372

PIN IDENTIFICATION
(CONT.)

PRDCESSOR INTERFACE

DISK DR1VE INTERFACE

'Reset

"

'
) TD
DISK DRIVE

He~d Load

Register Write/Read Select
REGISTER
{
SELECT
COMMANDS·

. Low Current

Register Data St~'rage
Register Select 2
Register Select 1

Write Fault Reset
Write -Current Enable

Register 5.elect 0

Step In Or Direction
Step Out Or Step,

Interrupt Request

Disk Drive 80 Select
ois'i( Drive A1' Sel~t

DISK DRIVE
COMMANDS

D,isk Drive B1 Select

,Pisk Drive AO Select

....D372

Data Bus 0
Data Bus 1
Data ,Bus 2

Read Clock
Read Data

}

FRDM
DISK DRIVE

Data Bus 3

DATA BUS

!;lata Bus 4
Da'ta Bus 5

Index

Data Bus 6
Data Bus 7

track Zero

Write Fault
Disk Drive A Ready

' } DISK, DRIVE
STATUS

Disk Drive BReady
Write Clock

TIMING {

¢1

. Clock Status
Always Low

GND-5V +5V +12V,.

PACKAGE OUTLINE
J,lPD372D

ITEM'
A

MILLIMETERS
53.5 MAX

INCHES
2.1 MAX

B

1.35

0.05

C

2.54

0.10

D

50.80

F

1.27

0.05
0.10 MIN

2.0

G

2.54 MAX

H

1.0MIN

0.04 MIN

I

4.2 MAX

0,17 MAX

J,

5.2 MAX

0.21 MAX

K

15.24

0.60

L

13.50

0.53

M

0.3

0.012

,

259

'fL PD372
BIT

INTERNAL REGISTER IDENTIFICATION
FUNCTION

NAME

SYMBOL

WRITE REGISTER

a
1
2
3
4
5
6

7

a
1
2
3
4
5
6

7

WFR
LCT
HLD

MBL
RST
UAo
UAI
UAS
CB3
CB4
CB5
CBS

Not Used
Write Fault Reset
Low Cutrent
Head Load
Not Used
Not Used
Must Be Low
Reset
Unit AO Select
Unit A 1 Select
Unit A Strobe
Clock Bit 3
Clock Bit 4
Clock Bit 5
Not Used
Clock Bit Strobe

a

Resets Pin 23 to Zero
Sets Pin 22, Should be Zero for TRKS
Sets Pin 19, Loading FDD Head

Software Reset, Same t:ffect as

~in

> 43

1

WRITE REGISTER 1
Device Select Pin 30
Device Select Pin 29
Strobe for Enabling UAO and OAI to be Loaded
Enables Clock Pulse fF,j to be Written
Enables Clock Pulse #4 to be Written
Enables Clock Pulse #5 to be Written
Enables Clock Bits to be Loaded
WRITE REGISTER 2

a
1
2
3
4
5
6

7

a
1
2
3
4
5
6
7

Data
Data
Data
Data
Data
Data
Data
Data

a

WDo
WDI
WD2
WD3
WD4
WD5
WD6
WD7

Write
Write
Write
Write
Write
Write
Write
Write

CCW
CCG
WER
IXS
WES
STT
WCS
RCS

WRITE REGISTER 3
Cyclic Check Words
One During R/W, Zero for CRC Reset
Starts CRC Generator in Write Mode
Cyclic Check Generator Start
Write Enable Reset
Resets Pin 24 to Zero
Enable Index Hole Detection
Index Start
Write Enable Set
Sets Pin 24 to One
Enables Read and Write Operations to Occur
Start
Write Clock Set
Write Clock Selected
Read Clock Set
Read Clock Selected

Bit
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

WRITE REGISTER 4

a
1
2
3
4
5
6
7

UBo
UBI
UBS

SOS
SID
STS

Device Select Pin 28
Device Select Pin 27
Strobe for Enabling UBO, UB 1 to be Loaded

Unit BO Select
Unit B 1 Select
Unit B Strobe
Not Used
Not Used
Step Out or Step
Step In or Direction
Step Strobe

Sets Pin 26 to One
Sets Pin 25 to Dne
Enables SOS and SID to be Loaded

WRITE REGISTER 5

I

0-7

a
1
2
3
4
5
6
7

260

This Register Not Used
WRITE REGISTER 6
DRR
IRR
TRR

Data Register Reset
Index Request Reset
Timer Request Reset
Not Used
Not Used
Not Used
Not Used
Not Used

Resets DRO (RRO Bit 0)
Resets IRO (RRO Bit 11
Resets TRO (RRO Bit 2)

,uPD372
INTERNAL REGISTER IDENTIFICATION (CO NT.)
BIT

SYMBOL

NAME

FUNCTION

READ REGISTER 0
0

ORO

Data Request

Read Data Byte from R Fl2 or Write Data Byte
into WR2

1
2
3
4
5
e
7

IRO
TRO
ERR

Index Request

Timer Request
Error

Set by Physical Index Pulse
Set by Every 512tl1 Write ClK Pulse
logical OR of WFT + RYA + COR

UBO
UB1
RYB
AlH

Drive BO Selected
Drive B1 Selected
Drive BReady
Always High

Always Contains a Logical One

0
1
2
3
4
5
e
7

UAO
UA1
WFT
RYA
COR
DER

Drive
Drive
Write
Drive

TOO
WRT

Track Zero

Write Mode

0
1
2
3
4
5
e
7

ROO
RD1
RD2
RD3
RD4
RD5
ROe
RD7

Read
Read
Read
Read
Read
Read
Read
Read

Ready Signal from Pin 14

READ REGISTER 1
AO Selected
A 1 Selected
Fault
A Ready

Indicates Status of Pin 8
Indicates Status of Pin 12
Processor Did Not Respond in Time to a DRO
CRC Error During Read
Indicates Status of Pin 9
Indicates which Clock WCK or RCK has been
Selected

Command Overrun

Data Error

READ REGISTER 2

ADDRESSABLE
INTERNAL REGISTERS

Data
Data
Data
Data
Data
Data
Data
Data

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

0
1
2
3
4
5
6
7

Data is transferred to the flPD372's internal addressable registers by signals W/R
(Write=1, Read=O), OS (Data Strobe) and RSO-RS2 (Register Select 0,1 and 2).
Timing constraints for these signals are shown in the Timing Diagram. Diagram below
shows register allocations and functional content.
REGISTER ADDRESS

I

I

BIT NUMBERS

REGISTER
NAME

I

W/R RS21 RS, RSO

7

I

6

I

I

5

,4

3

I

I

2

I

,

I

0

I

WRITE REGISTERS

0

0

0

WRO

RST

MBL

X

X

HLD

LCT

WFR

X

WRl

CBS

X

CB5

CB4

CB3

UAS

UA l

UAO

WD 7

WD6

WD5

WD4

WD3

WD2

WDl

WDO

WR3

RCS

WCS

STT

WES

TXS

WER

CCG

CCW

WR4

STS

SID

SOS

X

X

UBS

UBl

UBo

WR6

X

X

X

X

X

TRR

IRR

DRR

WR2

I

READ REGISTERS

0

RRl

0
0

RRO

0

RR2

I
I

ALH
WRT
RD7

i

RYB

UBl

UBo

ERR

TRO

IRO

DRO

TOO

DER

COR

RYA

WFT

UA l

UAO

RD6

RD5

RD4

RD3

RD2

RDl

RDO

X

~

NOT USED
SP372-8-77-GN-CAT

261

II

NEe

NEe Microcomputers, Inc.

JLPD379'

SYNCHRONOUS
RECEIVER/TRANSMITTER
DESCR IPTION

FEATURES

The /JPD379 Synchronous ReceiverfTransmitter is an MaS LSI monolithic circuit that
performs all the receiving and transmitting functions associated with Basic and High
Level Data Link Control Procedures. This circuit is fabricated using N-channel AL-Gate
MaS technology, all9win9 all inputs and outputs to be directly TTL compatible. The
operation mode, baud rate and synchronous character are changeabfe through the use
of external control. The /JPD379 is packa~ed in a 42 pin Dual-in-line ceramic package.

• Suitable for Synchronous Basic and High Level Data Link Control Procedures
(BiSync or SPLC)
•

Full or Half Duplex Operation

•

Fully Double Buffered Transmit and Receive

•

Directly TTL Compatible

• Three-State Data au tputs

PIN CONFIGURATION

•

Programmable Sync Word

•

Detection/Rejection of Flag, Abort and Idle Patterns

•

Zero Insertion and Rejection

•

Indication of Overrun and Underrun Errors

•

SOOK Bits/Sec Operating Speed

NC

NC

VDD

Vee

Cs

MRL

RR"

MS,
MS2
TC

I>Im
RC
RI

'ffiiI.

CFR
ABTR
SYNR/lDLR
RDS
RD7

SNTR/CFT

II

SYNC/ZiP

/JPD

379

TDS
TD7
TD6

RD6

TDS

RDS

TD4
TD3
TD2

RD4
RD3
RD2
RD,
DR

TO,
TO
SYNT/ABTT
TCBE

OE

GND
NC: NO CONNECTION

Rev/1

263

f'PD379
Basic Sync Mode Transmission
The Sync character may be 16 in hexadecimal or it may be set to any other pattern
in the Closed Mode. When the mode control register is loaded with MSl = high and
MS2 = low, the j.!P0379 enters the Basic Sync mode from th,e Closed Mode. The Sync
character is continuously transmitted until a transmission data character is loaded.
After a data character is loaded, it is serialized and trans'mitted out from the TO
(Transmitter Output) line. If an underrun occurs, Sync character(s) are again trans·
mitted automatically until the next data character is loaded. Transmission data is sent
out from LSB (TO 1) first,to MSB (TOa) last on the TO line.
Basic Sync Mode: Receive
The RI (Receiver input) line first searches for Sync characters. Once an a-bit Sync
character has been detected, the'following received bits are treated as data characters
and outputted on lines ROl - ROa in parallel.
When device operation is started, the receiver section should be first brought into
Closed mode or should be reset in orderto ensure synchronization.
SOLC Mode Transmission
Until a data character is loaded, the Flag pattern (7E in hexadecimal) is automatically
transmitted continuously. After a data character is loaded, it is serialized and transmitted out from LSB (T01) to MSB (TOa) on the TO line. In transmitting data
characters, a dummy bit 0 is automatically inserted immediately following five (5)
successive l's. This is called Zero-Insertion and is performed in order to maintain
synchronization with the receiver and to avoid duplication of Flag pattern in data
characters. (Zero-Insertion may be prohibited optionally with the ZiP command, if
necessary.) If an underrun occurs while data characters are being transmitted, an Abort
pattern (FF in hexadecimal) and then a Flag pattern are automatically transmitted.
After that, the Flag pattern is again automatically transmitted until the next data
character is loaded.
'
If a low level is placed on the CFT (Closing Flag Transmit) line while a data character
is being transmitted, a Closing Flag will be transmitted immediately following transmission of the current data character.
SOLC Mode Receive
First, the Flag pattern is searched for on the R I line. Once a Flag pattern is detected,
inserted zero's are rejected from all the following characters except Flag, Abort (7 to
14 successive l's) and Idle (15 successive l's) patterns, and then deserialized and output on the ROl - ROa lines in parallel.
If an overrun occurs, all the following data inputs are neglected and the j.!P0379 goes
back to the first stage to search for the next Flag pattern.
Closed Mode
When there is a change of mode, it must pass through the closed mode. In the closed
mode, the following input signals may be used:
CS, SYNC, TCB L, MS1, MS2, M R L, TO 1 - TOa
After leaving the closed mode, Sync characters are transmitted synchronously with the
rising edge of TC. The receiver operates synchronously with the falling edge of RC,
after RR = 1.
The following timing diagram shows how mode changes may be accomplished.

~ ~==='--:J=ml--:;:::::t'
=.~:---t,-;: ',- ,~: j: _=,

_=1='

264

CLOSED

BASIC

CLOSED

SOLe

MODE

SYNC

MODE

MODE

MODE

'

FUNCTIONAL
DESCRIPTION

fLPD379

BLOCK DIAGRAM

SYNC/&

SHll'/CJ'f

TCei.
SYNT/ABTT

leaE

TC

TO

o

INPUT
<> OUTPUT
• • CONTROLLEO BY
THE alNPUT
CFR

ABSOLUTE MAXIMUM
RATINGS*

ASTR SVNRJ DR OE
IOLR

DOC to +70"'C
-40°C to +125°C

Temperature Under Bias
Storage Temperature.
All Output Voltages
All Input Voltages
Supply Voltage Vee.
Supply Voltage VDD .
Supply Voltage VBB-'

. . . . . . . . . OV 10 +8.0V CD
. OV 10 +8.0V CD
...... OV 10 +8.0V CD
OV 10 +16.0V CD
-1O.0V 10 OV

COMMENT: Stress above those listed under" Absolute MaXimum Ratings" may cause permanent
damage to the device. This is a stress ratmg only and functional operation 01 the deVice at these or
any other conditions above those indicated In the operational sections 6f this specification IS not
implied. Exposure to absolute maximum rating condilions for extended periods may affect deVice
reliability.

"T a

=

25°C

Note:

AC CHARACTERISTICS

Ta

CD

VSS

= -

5 ± 5%

= O°C to +70°C, VDD = 12V ± 5%, VCC = 5V ± 5%, VSS = -5V ± 5%

PARAMETER
Clock Frequency

SYMBOL
fe

:

LIMITS
MIN

TYP

DC

MAX
800

UNIT

TEST CONDITIONS

KHz

TC,RC
TC,RC

Pulse Width

tpw

250

ns

MRL

250

ns

TCSl

250

ns

SNTR/CFT

250

ns

ZIP

400

ns

250

ns

RR
DRR·

Setup Time

tSET UP

250

ns

Hold Time

tHOLD

150

ns

Rise Time

tr

150

ns

Fall Time

1f

150

ns
ns

Pulse Interval

lee

Output Delay

tpdl

180

270

ns

Time

tpd2

410

600

ns

Fan Out

N

100

1

CL = 20 pf
1 TTL Load
Standard TTL Load

*50% Duty Cycle

265

fL PD379
PIN IDENTIFICATION

FUNCTION

PIN

NO.

SYMBOL

BASIC SYNC MODE

SOLe MODE

NC

No Connection

Voo

+12V Power Supply

CS

Chip Select When "1·~. the following inputs are disableq and the outputs are put into the high
impedance state: (Input Disabled) R"R, ORA, SYNC/ZiP, SNTA/CFT, TeBL, MAL; (Output-High
Impedance) CFR, ABTR, SYNR/IDLA, AD1 - RDS. DR, DE, TCBE, CYNT/ABTT

AR

Receiver Reset - Receiver portion is reset with a "0" and operation is stopped
RD,- RDa---"":"l"
CFR, ABTR, SYNR/lDLR, AR, DE - - - - "0"

ORR

Data Received Reset - Resets DR flag to "0"

RC

Receiver Clock - Receiver clock input. Trailing edge of clock is located in the center of receiver input
bits (AI).
.

AI

Receiver Input

CfR

(Normally "0")

Received data serial input
Closing Fla'g Received - Goes high whenever a Flag
has been received during data reception. Goes low
on the rising edge of DR or OE comman~s

ABTR

("0" Constant)

Abort Received - Becomes "1" when 7 - 14 con·
tinuous "1 "s are received, after receiving the flag.
Goes low on the rising edge of DR or OE commands.

10

SYNA
lOLA

Sync Character Received
Goes high when synchronization has occurred, or whenever the con·
tents of the Sync Character Buffer and the contents
of the Receiver Character Buffer coincide. Goes
low when DR goes high and the AD1 - ROS out·
PUts are different from the Sync Character.

Idle Pattern R~ceived Becomes "1" (Idle) when
it receives 15 consecutive "1 "5. Goes lowon the
rising edge of DR or OE outputs.

11 - lS

RDS - RD1

'9

DR

Receiver Data Outputs - Received character output terminal (AD1 :LSB RDg:MSB)
Data Received - Goes high when the received character has been transferred from the Receiver Shift
Register to the Receiver Buffer Register

-DRd~;; ~O~;hi~ fo-;:-thefir; S-;n;;-Cha;;t; -TDRd;S--;;O-;;-h~hfO-;:-Fla;'-Ab;;'~;:-ldiepa~---input. It is reset when ORR is driven low.

20

DE

terns_ It is reset lII,'hen (1) ORR'" "0", (2) On the
rising edge of OE, (3)Seven (7) successive "1"s
have been received.

Overrun Error - OE ~ "1" shows that DR was still high when the received character is moved from the
receiving shift register to the receiving buffer register

oETs -;:;;;-ifDR ;;i~-;h;nth;;~~ ~;;;;cte;Tltis7es;t ~ the risi~;-dg-;ofDR -- - ----is transferred from the Receiver Shift Reg'lster to
the Receiver Buffer Register
21

VBS

22

Vss

23

TCBE

5V Power Supply
Ground
Transmitter Character Buffer Register Empty

TCBE - "1" when the transmitter character buffer is

~~y:.------ - - - - - - - - - - -

Itis-;e;;~-;;(l ') TCBL~-;;cr':-(2i

TCBE is reset when TCBl is driven low

24

SYNT
ABTT

25
~

26

TO
33

TOt

TOg

wh"e;;

CFT-:"0" in the data transmission mode, (3) One·half
bit before ABTT goes high,

SYNC Character Transmit SYNT'" "1" when a
synchronous character is being transmitted. It is
reset when: (1) SNTR '" "0", (2) when transmission of data commences

Abort Pattern Transmit - ABTI '" "1" when an
Abort Pattern is being transmitted

Transmitter Output - Transmitter data OUtPUt. TO '" "1" in the closed mode.
Transmitter Data Inputs - Transmitter character input. (T01 '" lSB, TOS - MSB)

34

SYNC
ZIP

SYNC Character - In the Closed Mode, the SYNC I Zero Insertion Prohibit - When ZIP is driven
line is used to select a SYNC character to be loaded I low, zero-insertion will be prohibited for all subse·
into the syNC Character Buffer. The selected
I quent data characters until a Closing Flag or an
SYNC character is loaded into the buffer on the
I Abort Pattern is transmitted.
rising edge of TCBl and is selected as follows'
(1) When SYNC'" "0", the character placed on the
Tol - TOa inputs is loaded, (2) When SYNC '"
"1",16 Hexadecimal is loaded.

35

SNTR

SYNC Character Transmit Reset - When SNTR is
driven low, SYNT is reset to "0".

eFT

Closing Flag Transmit - DUring transmission, CFT
low causes the following operations to occur'
(1) TCBE Output is reset to "0", (2) The Closing
I Flag will be transmitted after the end of transmission
of the current data character.

~

I

i
36

TCBl

37

Te

Transmitter Character Buffer load - (1) In the closed Mode: the SYNC Character Buffer is loaded on the
rising edge of TCBl. If the SYNC input is low, the buffer is loaded wit~ the data on the TO, - TOa inputs;
if SYNC is high, the buffer is loaded with (16) Hex. (2) In the Basic SYNC or SDlC Modes: When TCBl
is driven low (a) TCBE is reset to "0" and (b) the data chara'ci:.er on the TOl - TOg inputs is loaded into
the Transmitter Character Buffer. The loaded character is latched on the rising edge of TCBL.
Transmitter Clock - Clock input for transmission.

38

Mode Select 2

39

Mode Select 1
Used to select one of three modes.
MSl

MS2

L

L

MODE
Closed Mode
Closed Mode
Basic Synchronous Mode
SOLC Synchronous Mode

In the closed mode TO and AD, - ROg are high, all other outputs are low.
40

MRL

41

Vee
Ne

42

266

Mode Control Register load - When MR l is low, the'operational mode is selected by the current status
of MS1 and MS2. When MAL goes high, the operational mode is latched based upon the status of MS,
and MS2.
+5V Power Supply
No Connection

JLPD379
TIMING WAVEFORMS

MODESELECT

MODE

Closed
Basic Sync
SOLC

MS1. MS2

MS1

MS2

MRL

0
1
1

·0 or 1
1
1

l...J"
LJ"

1....S

CH.IP SELECT

D,UT

IN

Should be stable.

Unit:nsec

TRAN~ITTER SECTION
TC

TO

SYNT

leBE

ABTT

SYNC

IHOLD

267

p.PD379

TIMING WAV.EFORMS

(CaNT.)'

RECEIVER SECTION
RC

.

DR

RD,---+~.r--------~~~------~r---­
I

RD. __-+~________~,~~______~~___
ABTR
IOLR

CFR

OE

SYNR

RD,
I

R"e~--+--..I!

ABT~~C~~ -----1--..... 1
SYNR/IDLR

DC CHARACTERISTICS
Parameter

Limits
Symbol Min Typ Max

Input High Voltage
Input Low Voltage
Output Leakage Current

VIH
VIL
IOL

3.0

Voo
0.11

-20

:zo

Output High Voltage
Output Low Voltage
Input Low Current
Voo Supply Current
V CC Supply Current
Vaa Supply Current

VOH
VOL
IlL

3.5

Fan-out

N

0.4
1.4
20
65
-2.0
1

15
40

100

ICC
laa

O.~

Unit
V
V
/-I A

Test Conditions
With Built·in
pull~up

resistors

-V 0 = 0.4 to 3.5V
(CS)= 3.5V
V
IOH - -10DI-IA
V
IOL = 1.6mA
mA
VIL = 0.4V
mA
mA
mA
StanC; Vee'" +5V ± 5% unless othetwise specified.

AC CHARACTERISTICS
LIMITS

PARAMETER

SYMBOL

Clock Period

"'CY

Clock Active (High)

"'0

Clock Rise Time

"'r

Clock Fall Time

"'f

AO. CS,~ Set Up Time toAD,J,

TAA

AO. CS, OACK Hold Time from RD

t

MIN

TAR

Data Access Time from RD .I.

TAD

t

9,0

8,0

1,0

UNIT
MH,

20

"'ns

20

ns

30

ns

5,0

ns

300
200

ns

100

ns

TOF

20

AO. CS, DACK Set Up Time to WR t

TAW

50

ns

AO. CS, OACK Hold Time to WR t

TWA

30

ns

WFiWidth

TWW

300

ns

Data Set Up Ti me to WR t

TOW

250

ns

Data Hold Time from WA t

TWO

30

INT Delay Time from AD t

TAl

DB to Float Delay Time from RD

tNT Delay Time from WR

t

n,

ORO Delay Time from ~ t

13
1,0

TAM

t

ns

500

TWI

WR or AD Response Time from ORO

n.

500

TMCY

ORO Cycle Time

1.0

TRWM

"s
... s

"'n,

300

TC Width

TTC

Rest Width

TRST

WeK Cycle Time

TCY

WCK Active Time (High)

TO

WCK Rise Time

Tr

30

ns

WCK Fall Time

Tf

30

ns
n,

3,0

"'

2or4@

Pre-Shift Delay Time from WCK t
WDA Delay Time from WCK

t

"'

1 or 2

150

250

350

TCp

20

150

TCO

20

150

R DO Active Time (High)

TROD

Window Cycle Time

TWCY

a

MFM'" 1

n,
os

100

MFM - 0

"'

1,0

TAOW

MFM'"

n,

2,0

100

n,

TUS

12

SEEKfRW Hold Time to LOW CURRENT/
DIRECTION t

"'

TSO

7

"'

l.OW CURRENT/DIRECTION Hold Time to
FAULT RESET/STEP t

TDST

1.0

"s

1,0

Window Hold Time to/from ROD

TEST
CONDITIONS

ns

35

TAA

J=rnWidth

MAX

TYP 1

MFM'" 1

TWAO
USO,1

Hold Time to RW/SEEK t

USO, 1 Hold Time from FAULT
AESET/STEP t

TSTU

STEP Active Time (High)

TSTP

LOW CURRENT/DIRECTION HoldTime from
FAUL T RESET/STEP ~

TSTD

STEP Cycle Time

TSC

FAULT RESET Active Time (High)

TFA

Notes:

8 MHz Clock
Period

"s
5,0

I

"'

5.0

"s

@

@

8,0

10

m,

"'

a

MHz Clock
Period

CD Typical values for T a'" 25° C and nominal supply voltage.
® The former value of 2 and 1 are applied to Standard Floppy, and the latter value of 4 and 2 are
applied to Mini-floppy.

@

Ta

Under Software Control, The range is from 1 ms to 16 ms at 8 MHz Clock Period, and 2'to 32 ms
at 4 MHz Clock Period.

= 25'C; f = 1 MHz
PARAMETER

CAPACITANCE
SYMBOL

LIMITS
MIN

TYP

MAX

UNIT

Clock I nput Capacitance

CIN('!»

35

pF

Input Capacitance

CIN

10

pF

Output Capacitance

COUT

20

pF

274

TEST
CONDITIONS

All Pins Except Pin Under
Test Tied to AC Ground

,",PD76S
TIMING WAVEFORMS

PROCESSQR READ OPERATION

AO.Cs.~ ~

______________

----x

TAR---;

AD

_______

I' __
TRA
______
__

I~

I .'

,---I

DATA

~~}(~

'I - - - T R R _ I

.

_ITDF'--

~ _ _ _ ~ ~R~{

.:

)

_ _ ,- __ _

,-.,T R.."'\
I - '1
INT --.________________
....:,._....:,

~

PROCESSOR WRITE OPERATION'

ClK

- - -__ I·~O

I

'--II
R~ 1--11
I

. I

---!

I--<1>F

DMA OPERATION

DRQ

J:1----\.
TAM-';

I

1<

.r-

II

~I.~--------JI
TMCY

..

(!
I.
r--TRWM

\i

~

WR OR

RD

FDD READ OPERATIQN

WRITE CLOCK

I

I

'"",-_J

1

II~

I-,-TF

TR-'-:r--WRITE ENABLE

I

II

I

I--- TCy--I
1

~

:

I

PRESHIFT 0 OR

.c:x:-----...;~'fl
.~
-:

T CP

X,--_X:='

~TCD

WRITE DATA

.PRESHIFT 0
NORMAL
lATE
EARLY
INVALID

0
0
1..
1

PRESHIFT l

0
1
Q

1

275

fLPD765
SEEK OPERATION
uSa, 1

-=x:--,.--..JX_----rX'-------)C
--:

-

RW/SE E 1<

I

:--TUS

-T-J~'
:

\

I

'_Iy

I

K"'___~~,

TOST __ :
STEP

:-~

/

1'---'
I

...- - ' - -....

~TSO~"._ _ _

DIRECTION

TIMING WAVEFORMS
(CaNT.)

x

:
I

I 1 _ TSTU

~~----------

~~TSTU~

---------':

X'----_

r-- TSTP

I
I

I

I

~I~.------TSC------~-~I

FLTRESET
I

FAULT RESET '"

_______

FILE UNSAFE RESET

I

-J~I
i '-------

_I

TFR:--

FDD READ OPERATlCN

READDATA

~_ _ _ _ _ _ _ _ _~~~I__________
-I
I

I __ TRDD

I-TwRD-J

I

I

READ OATAWINDOW _ _ _ _ _ _ _

I

I-TRDW~

I

U
II

1

I

-J~

~

1_-TWCy-----l--1

Note: Either polarity data window is valid.

RESET

TERMINAL COUNT

TC

-J1--i

RESET--ti___I

I---- T TC

I--TRST

The flPD765 contains two registers which may be accessed by the main system proces'
sor; a Status Register and a Data Register. The g·bit Main Status Register contains the
status information of the FDe, and may be accessed at any time. The g,bit Data
Register (actually consists of several registers in a stack with only one register pre,
sented to the data bus at a time), which stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command. The Status
Register may only be read and is used to facilitate the transfer of data between the
processor and flPD765.
The relationship between the Status/Data registers and the signals RD, WR, and AO
is shown below.

276'

AO

RD

WR

0

0

1

Read Status Register

0

1

0

Illegal

0

0

0

Illegal

FUNCTION

1

0

0

Illegal

1

0

1

Read from Data Register

1

1

0

Write into Data Register

INTERNAL REGISTERS

",PD765
INTERNAL REGISTERS
(CaNT.)

The bits in the Main Status Register are defined as follows:
NAME

BIT NUMBER

SYMBOL

FDD 0 Busy

DBa

DaB

DESCRIPTION

FDD number- 0 is-in the Seek mode.

OBI

FDO 1 Bus-y

DIB

FDO number 1 is in the Seek mode.

DB2

FDD 2 Busy

D2B

FDD number 2 is in the Seek mode.

DB3

FOO 3 Busy

D3B

FDD number 3-is-in the Seek mode.

DB4

Foe Busy

CB

A read or write com'mand is in

DB5

Non·DMA mode

NOM

The FOe is in the non-DMA mode.

DBB

Data Input/Output

010

Indicates direction of data transfer
between FOe and Data Register. If
DID == "1" then transfer is from
Data Register to the Processor. If
010 == "0", then transfer is from the
Processor to Data Register.

DB?

Request for Master

ROM

Indicates Data Aegister is ready to
send or receive data to or from the
Processor. Both bits 010 and ROM
should be used to perform the handshaking functions of, "ready" and
"direction" to the processor.

process.

The 010 and ROM bi'ts in the Status Register indicate when Data is ready and in which
direction data will be transferred on the Data Bus.
Out,FoC and Into Processor

Data In/Out
Out

(010)

pro~essor and Illto Foci
I

Ready

Request for Master

,4.,

(ROM)

I
1

~
I

I I

rI ; h
,~
~
~
~
:
1
11111
,'

r-1

~

Ready

rl--"

§

:

RD~:

I A I BI
Notes. ~ -

A

IBI A I C I D I C 10 IBI

A

I

Data n:glster ready to be wn~ten into by processor

[ill
[f] -

Daw register not ready t.o be written

[QJ -

Data register not reJdy for next data byleto be read by processor

InlO

by processor

Data reg~ster ready for next data byte to be read bV the processor

PACKAGE OUTLINE
JIPD765C

ITEM

INCHES
5t5MAX
2.54±O.1
0.5± 0.1

48.26

2.028 MAX

O.IO±O.OQ4
0.019 + 0.004

>.,

I.2MIN

0.047 MIN

2.54 MIN

0.10MIN

0.5 MIN

0.019 MIN

5.22 MAX

0.206 MAX
0.225 MAX

15.24

0.600
0.520

+0.1
0.25
• 0.05

COMMAND SEQUENCE

0,010

+ 0.004

- 0.002

The I'P0765 is capable of performing 15 different commands. Each command is initiated by a
multi-byte transfer from the processor, and the result after execution of the command may also
be a multi-byte transfer back to the processor. Because of this multi·byte interchange of information between the I'P0765 and thep'rocessor, it is convenient to consider each command .as
consisti ng of three phases:
Command Phase:

The FOC receives all information required to perform a particular
operatioQ from the processor.

Execution Phase:

The FOC performs the operation it was instructed to do.

Result Phase:

After completion of the operation, status and other housekeeping
information are made available to the.processor.

277

IL'PD765

INSTRUCTION SET(i)

I
PHASE

R/W

DATA BUS

D7

06

Os

D.

0> D.

01

DO

I
I

Ri:MAFtKS

L
PHASE

R/W

Command

W
W

MT

MF SK
X

X

D6

Os D

Command Codes

W
W
W
W
W
W
W

X

HO USl

C~mand

USO

H
R

'II

to Command execution

W
W
W
W
W
W

EDT
GPl
OTl

Execution

Data·transfer between the
F DO and main-system
STO
sf 1
ST'

W
W

Secto~ 10 information after
Command execution

N

X

X

X

0

1

X

X

W
W
W
W
W
W
W

0
HD US,

Command Codes

usa

e

Se<:t~r

H
R

to Command execution

10 information prior

MF SK
X

X

0

0

0

X

X

HO

Command Codes

US1

USO

e

Sector ID information prior

H
R

to Command execution

N

EDT
GPl
OTl
Oeta-transfer between t he
FOD and main-system. FDC
reads all of cvlinders contenu

R
R
R
R
R
R
R

STO
STl
ST2

OTl

Result

STO
ST'
ST.

Status information after
Command execution

e

Sector 10 information after
Command uecution

H
~

Commend execution

e

Sector 10 information after
Command execution

H
R
N

W
W

0

MF

0

0

X

X

X

X

Commands
X

HO US,

USO
The first correct 10 information
on the Cylinder is stored in
Data Regi'ter

Command

W

0

X

X

X

0
X

Command Codes
HD US,

USO

e

W
W
W
W
W
W
W

Sector Ie information prior
to Com~and execution

H
R
EDT
GPl
OTl

Execution

Status information after
Command execution
Sector ID information during
Execution Phase

N

W
W

0

MF

0

0

X

X

X

Command Codes

0
X

HO US,

usa
Bytes/Sector
Sec:torslTrack
Gap3
Filler Byte

N

se
GPl
0

Execution
Result

N

STO
STl
ST2
C
H
R

W
W
W
W

WRITE DATA

0

R
R
R
R
R
R
R

FORMAT A TRACK

N

MF

ear .

StatuI information after

GPl.;

MT

REMARKS

READ 10

Command

Data'~ran5fer belween lhe
.FOO and main-system

W

X

Execution

N

R
R
R
R
R
R
R

Command

0

EDT

Execution

Result

I.

from ii'K:Iex hal#to

Result

H
R

MT MF SK

DO

Execution

READ DELETED DATA

Command

I'

Status information after
,Command execution

e

R
R
R

W
W

Sector lD information prior

N

Result

D> D.

REACi A TRACK

0
X

J

DATA $US

D7

READ DATA

Data-transfar between the
,main-system and FOD

FOC formats an entire CYlinder

R
R
R
R
R
R
R

STO
ST'
ST2

Status information after
Command execution

e

In thi' cal., tha 10 Information
has no meaning

H
R
N

SCAN EQUAL

Result

R
R
R
R

STO

Status information after
Command execution

sT,

Command

ST.

e

Sector 10 infotmation after
Command uecution

H
R

W
W
W
W
W
W
W
W
W

MT

MF

0

0

X

X

X

X

HO US,

,

Not.:

II
R

278

Sector ID information prior
to Command execution

STO
ST'
ST 2

e
H-----

Status information after
Command execution
Sector 10 information after
Command execution

N

Symbols u~ in,this tabla are described at the end of this section.
AO should equal binary 1 for all,op,erations.,
X = Don't care, usually made to equal binary O.

X.

~

X

,

0

X

X

e
H
A

0

0

HD USl

Command Codes
USO
Sector 10 information prior
to Command execution

N

EDT
GPl
STP

Execution

Result

N

EDT
GPL
OTl
Oa-!;a-,transfer between the
FOD and main-System

R
R
R
R
R
R
R

CD
®
®

Command Codes

MT MF SK

USO

Execution

Result

W
W
W
W
W
W
W
W
W

N

WRITE DELETED DATA
Command

®

Data-compared between the
FOO and main-system

R
R
R
R
R
R
R

STO
ST'
ST'

e

H
R
N

Status information after
Command execution
Sector 10 information after
Command execution

INSTRUCTION SET
(CONT.)

I
R/W

PHASE

Commecd

I

JLPD765

06

05 DO

03

02

I

I

DATA BUS

0,

0,

REMARKS

DO

R/W

PHASE

06

05

DO

W

MT

MF

SK

1

X

X

Command

Command Codes
X

HD

US,

X

X

X

Command Codes

SPECIFY

Command

.. ..

W
SRT
Hl T

W
W

Command

Command Codes
X

X

X

W
W
W
W
W
W
W

,

X

X

HO

US,

US1

usa

1

,

Status information about FDD

seEK
Command Codes

X

HO

ST 3

Result
SCAN HIGH OR eQUAL

SK

HUT
NO

W

W

MF

Command Codes

...

SENSE DRIVE STATUS
Sector 10 information after
Command execution

MT

Status information al the end
of seek-operation about the FOC

STO
PCN

Status information after
Command execution

ST 0
ST 1
ST 2

Result

W

usa

W

Data-compared between the

W

US,

Head retracted to Track 0

Result

FDO and main-system

Command

USO

1

W
X

W

Sector 10 information prior
Command execution

X

X

HD US1

W

Head is positioned over
proper Cylinder on
Diskette

EOT
GPl
STP
Data·compared between the
F DO and main·system

ST 0

ST'
ST 2
C

COMMAND SYMBOL
DESCRIPTION

Status information after
Command execution

Command Codes

usa

NeN

Execution

Exocution

Result

C

Execution

Command
EOT
GPl
STP

Execution

I

REMARKS

SENSE INTERRUPT STATUS

W
W
W
W
W

Commecd

DO

Command Codes

W
Sector ID information prior
Command execution

W

0,

W

USO

w

03 02

RECALIBRATE

SCAN LOW OR eQUAL

W

I

DATA BUS

0,

INVALID
_ _ _ Invalid Codes _ _ _ _

W

Command

ST 0

Result

Invalid Command Codes
jNoOp - FDC goes into
Standby State)
STO=80
(16)

Sector 10 information after
Command execution

SYMBOL

DESCRIPTION

NAME
Address

AO

Lln~

0

!l

AO controls seiec{lon of Mal!l Status
(AO
(AD

Cylmdec Nembee

I

= 0)

or Data Reg!ster

1)

C stands for the current 'selected Cylinder
(track) number 0 til '·0 ugh 76 of the
medium

Data

o stands for

the data pattern which IS

gOing to be written Into a Sectol
S-blt Data BuS:-Cv~07 stands fOI a most

07- 0 0

Data Bus

DTL

Data Length

When N IS defmed as 00, OTL stand, tOI
the data length which users
qOln~ to
read out or write Into the Sector.

EOT

End of Track

EOT stands for the final Sectw number
on a Cylinder.

GPl

Gap Length

GPL stanns for the length of Gap 3
(spacing between Sectors excluding
Sync. Field).

Head Address

H stands for head !lumber 0 or 1, as
5pecifled In 10 field

Head

HD stands for a selected head number 0
or 1. (H = HD III all command words.1

Head Load Time

HL T stands tor the head load time in the
FOD (2 to 256 ms 111 2 inS Incremenh).

Head Unload Trme

HUT ~ta!lds tor the head unload t:me
after a read or write operation ha:.

Significant bit, and DO stands tal a least
Significant bit

HD
HlT

i

HUT

MF
MT

i
I
I

I

I

veo

occurred (0 to 240 ms III 16 ms
Illcrements)
FM or MFM Mode

If MF

I')

low, FM mode

I,

st!ected, and If

it is high, MFM mode IS selecteeJ
Multi-Track

If MT IS high, a

be performe,d.
cylinder under both
HOD and ·.HOl will be read or written.)

279

Jl. PD765
':':':

DESCRIPTION

NAME

SYMBOL
N
NCN

N"stands for the number of data bytes
written in a Sector.

New Cylinder Number

NCN stands for a new Cylinder number,
which is going to be reached as a result of the
Seek operation~ Desired position of Head:

,.
ND

Non-DMA Mode

NO stands for ope~ation in the Non-DMA Mode.

PCN

Present Cylinder

peN stands for the Cylinder number at the com·

COMMAND SYMBOL
DESeRI PTION· (CONT.)

pletion of SENSE INTERRUPT STATUS

Number

I
I

,

Number

Command. Position of Head at present time.

R

R stands for the Sector number, which will

Record

be

re;~d

or written,

R/W stands for either Read (R I or Write (WI

RNI

ReadNirite

SC

Sector

SC indicates the number of Sectors per

SK

Skip

SK stands for Skip Deleted Data Address Mark.

Step Rate Time

SRT stand, for the Stepping Rate for the FDD.

signal.

Cylinder.
SRT

ST a
ST 1
ST 2
ST:i

I
I

(1 to 16 ms in 1 ms increments.) Must be
defined for each of the four drives.

Status a
Status 1
Status 2
Status 3

5T D-3 stand for qne of four registers which

store the status information after a command
has been executed. This information is
available during the result phase after command
execution. These registers.should not be con'
fused with the main statlls'register (selected by

I

AO = 01. ST 0-3 may be read only after a com·
mand has been executed and contain informatior
relevant to that particular command.

STP

During a Scan operation, if STP = 1, the data in
sectors is compared byte by byte
witH data sent from the processor jor DMA);
and if STP = 2, then alternate sectors are read
and compared.
co~tiguous

i
usa, US1

Unit Select

US stands for a selected drive number 0 or 1.

SYSTEM CONFIGURATION

8000 SYSTEM BUS

080-7

AO

MeMR
iOR

080-7

M8\1IW

iNA

i15W

cs

AD

cs

INT

HRO

RESET

HLOA

#PD8267

TC
TERMINAL
COUNT

·280

RD DATA

ORO

CON~~;LLER DACK

READ
DATA
WINDOW

jlPD765
FPC

JLPD765
PROCESSOR INTERFACE

During Command or Result Phases the Main Status Register (described earlier) must be
read by the processor before each byte of information is written into or read from the
Data Register. Bits D6 and D7 in the Main Status Register must be in a 0 and 1 state,
respectively, before each byte of the command word may be written into the /-lPD765.
Many of the commands require multiple bytes, and as a result the Main Status Register
must be read prior to each byte transfer to the ,.d'D765. On the other hand, during,the
Result Phase, D6 and D7 in the Main Status Register must both be 1 's (D6 = 1 and
D7 = 1) before reading each byte from the Data Register. Note, this reading of the
Main Status Register before each byte transfer to the /-lPD765 is required in only the
Command and Result Phases, and NOT during the Execution Phase.
During the Execution Phase, the Main Status Register need'not be read. If the /-lPD765
is in the NON·DMA Mode, then the receipt of each data byte (if /-lPD765 is reading data
from FDD) is indicated by an Interrupt signal on pin 18 (lNT = 1). The generation of a
Read signal (RD = 0) will reset the Interrupt as vyell as output the D'ata onto the Data
Bus. If the processor cannot handle Interrupts fast enough,(every 13 /-lsI then it may
poll the Main Status Register and then bit D7 (ROM) functions just like the Interrupt
signal. If a Write Command is in process then the WR signal performs the reset to the
Interru pt signal.
" ,
If the /-lPD765 is in the DMA Mode, no Interrupts are,generated during the Execution
Phase. The /-lPD765 generates DRO's (DMA Requests) when each byte of data is avail·
able. The DMA Controller responds to this request with both a DACK = 0 (DMA
Acknowledge) and a RD = 0 (Read signall. When the DMA Acknowledge signal goes
low '(DACK = 0) then the DMA Request'is reset (DRO = 0). If a Write Command has
been programmed then a WR signal will appear instead of RD, After the Execution
Phase has been completed (Terminal Count has occurred) then an Interrupt will occur
(I NT = 1). This signifies the beginning of the Result Phase. When the first byte of data
is read during the Result Phase, the Interrupt is automatically reset (INT = 0).
It is important to note that during the Result Phase all bytes shown in the Command
Table must be read. The Read Data Command, for example has seven bytes of data in
the Result Phase. All seven bytes must be read in order to successfully complete the
Read Data Command. The /-lPD765 will not accept a neW command until all seven
bytes have been read, Other commands may require fewer bytes to be read during the
Result Phase.
The /-lPD765 contains five Status Registers. The Main Status Register mentioned above
may be read by the processor at any time. The other four Status Registers (STO, ST1,
ST2, and ST3) are only available during the Result Phase, and may be read only,after
successfully completing a command. The particular command which has been executed
determines how many of the Status Registers will be read.
The bytes of data.which are sent to the /-lPD765 to form the Command Phase, and are
read out of the /-lPD76'5 in the Result Phase; must occur in the order shown in the Command Table. That is, the Command Code must be sent first and the other bytes sent in
the prescribed seque'nce. No foreshortening of the CQmm,md or Result Phases are
allowed. After the last byte of data in the Command Phase is sent to the /-lPD765, the
Execution Phase autOmatically starts. In a similar .fashion, when the last byte of data is
read outin the Resuh Phase, the command is auto(Tlatically ended and the/-lPD765 is
ready for a new cOI"fji'nand. A command may be truncated (prematurely ended) by
simply sending a Terminal Count signal to pin 16 (TC = 1). This is a convenient means
of ensuring that the processor may always get the /-lPD765's attention even if the disk
system hangs up in an abnormal manner.

281

II

fLPD765
READ DATA
A set of nine (9) byte words are required to place the FDC into the Read Data Mode. After the Read Data
command has been issued the FDC loads the head (if it is in the unloaded state), waits the specified head
settling time (defined in the Specily Command), and qegins reading ID Address Marks and ID fields. Wh.en
the current sector number ("R") stored in the 10 Register (I DR) compares with the sector number read off
the diskette, then the FDC outputs data (from the data field) byte-ta-byte to the main system via the data

bus.
After completion of the read operation from the current sector, the Sector Number is incremented by one,
and the data from the next sector is read and output pn the data bus. This continuous read function is called
a "Multi-Sector Read Operation." The Read Data Command may be terminated by the receipt of a Terminal
Count signal. Upon receipt of this signal, th~ FOe stops outputting data to the processor, but will continue
to read data from the current sector, check CRC (Cyclic Redundancy Count) bytes, and then at the end of
the sector terminate the Read Data Command.
The amount of data which can be handled with a single command to the FDC depends upon MT (multi·
track), MF (MFM/FMl, and N (Number of Bytes/Sector). Table 1 below shows the Transfer Capacity.
Multi· Track
MT

MFM/FM
MF

a
a

a

1
1

a

a
a

a

1
1

a

a
a

a

1
1

a

1
1
1
1
1
1

Bytes/Sector
N

(Bytes/Sector) (Number of Sectors)

Final Sector Read
from Diskette

00
01

(128) (26) = 3,328
(256) (26) .- 6,656

26 at Side'O
or 26 at Side 1

00
01

(128) (52)
(256) (52)

01
02

(256) (15)
(512) (15)

01
02

(256) (30)
(512) (30)

Maximum Transfer Capacity

02
03

(512) (8)
(1024) (8)

02
03

(512) (16)
(1024) (16)

=
=
=
=
=
=

6,656
13,312

26 at Side 1

3,840
7,680

15 at Side a
or 15 at Side 1

7,680
15,360

15 at Side 1

-

4,096
8,192

8 at Side a
or 8 at Side 1

8,192
16,384

8atSide1

=
=
=

Table 1. Transfer Capacity
The "multi-track" function (MT} allows the FOe to read data from both sides of the diskette. For a
particuLu cylinder, data will be transferred starting at Sector 0, Side 0 and completing at Sector L, Side 1
(Sector L = last sector on the side), Note, this function pertains to only one cylinder (the same track) on
each side of the diskette.
When N = 0, then DTL defines the data length which the FDC must treat as a sector. If DTL is smaller than
the actual data length in a Sector, the data beyond DTL in the Sector, is not sent to the Data Bus. The FDC
reads (internally) the complete Sector performing the CRC check, and depending upon the manner of com·
mand termination, may perform a Multi-Sector Read Operation. When N is non-zero, then DTL has no
meaning and should be set to F F Hexidecimal.

At the completion of the Read Data Command, the head is not unloaded until after Head Unload Time
Interval (specified in the Specify Command) has elapsed. If the processor issues another command before
the head unloads then the head settling time may be saved between subsequent reads. This time out is
particularly valuable when a diskette is copied from one drive to another.
If the FDC detects the Index H~le twice without finding the right sector, (indicated in "R"), then the FDC
sets the ND (No Data) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
(Status Register 0 also has bits 7 and 6 set to 0 and 1 respectively.)
,After reading the 10 and Data Fields in ~ach secto!:', the FOe checks the eRe bytes, 'If a read error is
detected (illcorrect CRC in ID field), the FDC sets the DE (Data Error) flag in Status Register 1 to a 1 (high),
and if a CRC error occurs in the Data Field'the F DC also sets the 'DD (Data Error in Data Field) flag in
Status Register 2 to a 1 (high), and terminates the Read Data Command. (Status Register 0 also has bits 7
and 6 set to a and 1 respectively.)
Status Register 2 to a 1 (high), and terminates the Read Data Command.
If the FDG reads a Deleted Data Address Mark off the diskette, and the SK bit (bit D5 in the first' Command
Word) is not set (SK = 0), then the FDC sets the DM. (Control. Mark) flag in .statu~,Register 2 to a1' (high),
and terminates the Read Data Command, after reading all the data in the Sector. If SK = 1, the FDC skips
the sector with the Deleted Data Address Mark and reads th~ next sector.
During disk data transfers between the FOe and the processor, via the data bus, the FOe must be serviced
by the processor every 27 jJ.S in the FM Mode, and every 13jJ.s in the MFM Mode, orthe FDC sets the OR
(Over Run) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
If the processor terminates a read (or write) operation in the FOC, tllen the ID Information in the Result
Phase is dependent upon the state of the MT bit and EDT byte. Table 2 shows the values for C, H, R, and
N, when the processor terminates the Command.

282

FUNCTIONAL
DESCRIPTION OF
COMMANDS

JLPD765
FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

MT

EOT

10 Information at Result Pha••

Final Sector Transferred to Pr,?cessor

N

NC

R+ 1

NC

C+l

NC

R'~

NC

NC

NC

R+1

NC

Se.ctor 26 at Side 1
Seetor 15 at Side 1
Sector ,8 at Side 1

C+l

NC

R = 01

NC

Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0

NC

NC

R+ 1

NC

Sector 26 at Side 0
Sector 15 at Side a
Sector 8 at Side 0

NC

LSB

R

NC

Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1

NC

NC

R+ 1

'Ne

Sector 26 at Side 1
Sector 1,5 at Side 1
Sector 8 at Side 1

(;+1

LSB

R = 01

NC

lA
OF
08

Sector 1 to 25 at S id.e 0
Sector 1 to 14 afSide 0
Sector 1 to 7 at Side 0,

NC

l'A
08

Sector 26 at Side a
Sector 15 at Side a
Sector 8 at Side 0

,IA
OF
08

Sector 1 to 25 at Side 1
Sector 1 to 14,at Side 1
Sector 1 to 7 at Side 1

lA
OF
08
1A
OF

OF

'H

R

C

01

0

08
lA
OF
1

08
lA
OF

08
1A
OF

08
Notes:

=

01

NC (No Change): 'The same value as the one at the- beginning of command execution.
LSB (Least Significant Bit): The least

signific~nt bit of,H is complemented:

Table 2: 10 Information When Processor Terminates Command.'
WRITE DATA
A set of nine (9) bytes are required to set the FDe into the Write Data mode.-After' the Write Data comrpand
has been issued the FDe loads the head (if it is in the unfoaded state), waits the specified heat settling time
(defined in the Specify Command). and begins reading ID Fields. When the current sector number ("A").
stored in the ID Register (I'DR) ,compares with the sect~r number read off the di;kett.... then the FOC takes
data from the processor byte·by·byte via the data bus. and outputs it to the'FDD.
After writing data into the current sector, the Sector Number stored in "R" is incremented by one, and the
next data field is written into. The FDC continues this '''Mul,~i-Sector ~rite Operation" until the issuance of
~ T 'rminal Count signal. If a Terminal Count signal. rs sent to the F DC it continues writin~ into the current
'.' 1·,r to complete the data field. If the T~rmina"1 Count signal i~ re~eived while a d~t~ field is being written
to"n the remai,nder of the data field is filled with 00 (zeros). '
,
The FOe reads the 10 field of each sector and checks the eRe bytes. If the FOC detects a read error
(incorrect CRC) in one of the ID Fields. it sets,the DE (Data Erwr) fiag of Status Register 1 to a 1 (high).
and terminates the "Write Data Command. (Status Register a a~so has bits 7 ~md 6 set to 0 and 1 respectively.)
The Write Command operates in much the same manne"r as the Read Command. 'The following items are the
same, and one should refer to the Read Data Command for details:
•
•
•

Transfer Capacity
EN (End of Cylinder) Flag
ND (No Data) Flag

•
•
•

Head Unload Time Interval
10 Information when the "processor terminates command (see Table 2
Definition of DTL when N = 0 and when N -=1= a

In the Write Data mode, data transfers between the" processor and FOe, via the Data Bus, must occur every
31 J.Ls in the FM mode~ and every 15/.1s in the MFM mode."1f the time interval between data transfers is
longer than this then the FDC sets the OR (Over Run) flag in Status Register 1 to a 1 (high). and terminates
the Write Data Command, (Status Register 0 also has bit 7 and 6 set to a and ,- respectively,)
WRITE DELETED DATA
":"'~:s command is the same as the Write Data Command except a Deleted Data Address Mark is written at the
be!Jinning of the Data Field instead of the normal Data Address Mark.

READ DELETED DATA
This command is the same as the Read Data Command except that when the F DC det,ects a Data Address
Mark at the beginning of a Data Field (and SK = a (low), it will read all the data in the sector and set the
MD flag in Status Register 2 to a 1 (high). and then terminate the command. If SK = 1. then 'tn~ FDC skips
the sector with the Data Address Mark and reads the next sector.

283

READ A TRAG.K
This command is

s'imila~ to READ DATA Command except that this is a continuous READ operation

where the entire contents of the track are read. Imtnediately -after encountering the INDEX HOLE, the
FOe starts reading all data on 'the track, Gap bytes, Address Marks and Data are all read as a continuous
data stream. If the FDGfinds an error in the ID or DATA CRC check bytes, it continues to read data
from the track. The FOe compares the 10 information read,from each sector with the value stored in the
IDR, and sets the NDlflag of Status Register 1 to a 1 (high) if there is no comparison. Multi·track or skip
operations are no~ al}owed with this command.
This command terminates when EOT number of sectors have been read (EOT max = F Fhex = 255decl.
If the FDC does n"t-find an ID Address Mark on the diskette after it encounters the INDEX HOLE for the
second time, then it sets the MA (missing address mask) flag in Status Register 1 to a 1 (high), and termi·
nates the command. (Status Register 0 has bits 7 and 6 set to 0 and 1 respectively).
READID
The READ ID Command is used to give the present position of the recording head. The FDC stores the
values from the first ID Field it is able to read. If no proper ID Address Mark is found on the diskette,
before the INDEX HOLE is encountered for the second time then the MA (Missing Address Mark) flag in
Status Register 1 is set to a 1 (high), and if no data is found then the NO (No Data) flag is also set in Status
Register 1 to a 1 (high). The command is then terminated with Bits 7 and 6 in Status Register 0 set to 0
and 1 respectively.
FORMAT A TRACK
The Format Command allows an entire track to be formatted. After the INDEX HOLE is detected, Data is
";"itten on the Diskette; Gaps, Address Marks, ID Fields and Data Fields, all per the IBM System 34 (Double
Density) or System 3740 (Single Density) Format are recorded. The particular format which will be written
is controlled by the values programmed into N (number of bytes/sector), SC (sectors/cylinderl. GPL (Gap
Length), and D (Data Pattern) which are supplied by the processor during the Command Phase. The Data
Field is filled with the Byte of data stored in D. The ID Field for each sector is supplied by the processor;
that is, four data requests per sector are made by the FDC fo; C (Cylinder Number), H (Head Number),
R (Sector Number) and N (Number of Bytes/Sector). This allows the diskette to be formatted with nonsequential sector numbers, if desired.
After formatting each sector, the processor must send new values for C, H, R, and N to the ,",PD765 for
each sector on the track. The contents of the R register is incremented by one after each sector is
formatted, thUS, the R register contains a value of R + 1 when it is read during the Result Phase. This
incrementing and formatting continue, for the whole cylinder until the FDC encounters the INDEX HOLE

for the second time, whereupon it terminates the command.
If a F AUL T signal is received from the FDD at the end of a write operatioo, then the F DC sets the
EC flag of Status Register 0 to a 1 (high); and terminates the command after setting bits 7 and 6 of Status
Register 0 to 0 andl respectively. Also the loss of a READY signal at the beginning of a command
execution phase causes bits 7 and 6 of Status Register 0 to be set to 0 and 1 respecitvely.

Table 3 shows the relationship between N,

_FORMAT

FM Mode

FM Mode

MFM Mode

SECTOR SIZE

N-

se, and GPL for various sector sizes:

SC

GPL

CD

GPL

(VI

REMARKS

128 bytes/Sector

00

lA(16)

.07 (16)

lB(16)

I BM Diskette 1

256

01

OF(16)

OE(16)

2A(16)

IBM Diskette 2

512

02

08

lB(16)

3A(16)

-

1024 bytes/Sector

03

04

-

2048

04

02

-

4096

05

01

-

256

01

lA(16)

OE(16)

36(16)

512

02

OF(16)

lB(16)

54(16)

1024

03

08

35(16)

74(16)

2048

04

04

-

4096

05

02

-

-

8192

06

01

-

-

IBM Diskette 2D

IBM Diskette 2D

Table 3
Note:

284

 NCN: Direction signal to FDD·set to a 0 (Iowf, and Step. Pu.!;es ar.e issued. (Step Out.)
The rate at which Step Pulses are issued is controlled by SRT (Stepping Rate Time) in the SPECI FY Com·
mand. After each Step Pulse is issued NCN is compared against PCN, and when NCN = PCN, then
5E
(Seek End) flag is set in Status Register 0 to 11 1 (high). and the command is termin·ated.

the

DUrin'g the Command Phase of the Seek operation the FDC is in the FDC BUSY state, but during'the
Execution Phase it is irr

Inter.nal

SR flip-flop

@ Previous data remains

II

DC CHARACTERISTICS
PARAMETER

SYMBOL

LIMITS
MIN

UNIT -rEST CONDITIONS

T.YP

MAX

IF

-0.14

-'0.25

rnA

VF·0.45V

Input Load Current MD input

IF

-0.25

-0.75

mA

VF - 0.45V

Input Lo8d Cur~nt 'D'S1 Input

IF

-0.26

-1.d

mA

VF·0.4SV

Input Leakage Current ACK,

IR

10

JlA

VA= 5.2SV

Input Leakage Current MD
Input

'A

30

JlA

VA =.5.25V

Input Leakage
Input

'A

,40

p.A

VA = 6.25V

V

Ic·-5mA

Input-load Current ACK, 052.
CR, 011 - DIs Inputs

OS, CR, 011 - D1a1nputs

Cu~rent

OS1

Inp'ut Forward Voltage Clamp

Vc

Input "low" Voltage

V,L

Input "High" Voltage

V,H

Output " Low" Voltage

VOL

Output "High" Voltage
Short Circuit Output Current
Output Leakage Current' High
Impedance State
Power Supply Current

VOH
ISC

-0.85:·

0.85
2.0
3.65
-15

V
V

0.26
4.0·
-'38

10
ICC

-1.3

103

0.45

V

10L = 15mA .

V
-75

Il)A

"OH = -i mA
VO'c oli

20

"A

VO-,O.45V/~.25V

130

mA

299

P. PB8212
Ta

= O°Cto +70°C; VCC

=

AC CHARACTERISTICS

+5V ± 5%
LIMITS
SYMBOL
UNIT TEST CONDITIONS
MIN TYP MAX

PARAMETER
Pulse Width

tpw

Data To Output Delay

tpd

ns

30
20

30

ns

40

ns

Input Pulse
Amplitude = 2.5V
Input Rise and Fall
Times = 5 ns

Write Enable To Output Delay

twe

Data Setup Time

tset

15

Data Hold Time

th

20

Reset to Output Delay

tr

40

ns

Set To Output Delay

ts

.30

ns

Output Enable/Disable Time

teltd

45

ns

 --

30

-

20

-:;,.--

------

10

50 OC---cl.'::-O---C:''::-0---=3'''.0---=4.LO---c:"50

o

OUTPUT "HIGH' VOLTAGE NI

o

50

100

I-- ~

150

200

i--

250

II

300

LOAD CAPACITANCE (pFI
DATA TO OUTPUT DELAY

" r -_ _~V~S~T~'M~P~'~RA~T~U~R~'_r-_~
Vee

=

WRITE ENABLE TO OUTPUT DELAY

+5.0V

'0 t---- ---+----4---+---4

~40r-_ _~VS~T'~M~P~'R~A~T~UR~'~~_--,
_
Vee

+S.OV

j35~~.~---~-~--~--

16~--F~-~---~--~-~--~

~

30

12~--~--~-~--~-~

101-t::=~==h:=>'11

~

5TB-

D~

';
25

t--

t++--t----------

_---

'\

1_+

O'O~--\t~~~~--~-~~~---

~15It4==t~"~·~ 10 ~ ...jL~---+---

.....

D5 1

B

Ie
PRIORITY
COMPARATOR

D

-=Ie

INTERRUPT
FLIP-FLOP

01---....------------------'
INTERRUPT
DISABLE
FLIP-FLOP

INTE

7}----------------------------------J

ClK

6r-----------------------------------~

General
The MPB8214 is an LSI device designed to simplify the circuitry required to
implement an interrupt driven microcomputer system. Up to eight interrupting
devices can be connected to a MPB8214, which will assign priority to incoming
interrupt requests and accept the highest. It will also compare the priority of the
highest incoming request with the priority of the interrupt being serviced. If the
serviced interrupt has a higher priority, the incoming request will not be accepted.
A system with more than eight interrupting devices can be implemented by inter·
connecting additional MPB8214s. In order to facilitate this expansion, control
signals are provided for cascading the controllers so that there is a priority established among the controllers. In addition, the interrupt and vector information
outputs are open collector.
Priority Encoder and Request Latch
The priority encoder portion of the MPB8214 accepts up to eight active low
interrupt requests (RO-R7). The circuit assigns priority to the incoming requests,
with R7 having the highest priority and RO the lowest. If two or more requests
occur simultaneoLAsly, the MPBS214 accepts the one having the highest priority.
Once an incoming interrupt request is accepted, it is stored by the request latch and
a three·bit code is output. As shown in the following table, the outputs, (AO-A2)
are the complement of the request level (modulo 8) and directly correspond to the
bit pattern required to generate the one byte RESTART (RST) instructions
recognized by an 8080A. Simultaneously with the ,A;Q-A2 outputs, a system
interrupt request (INT) is output by the MPB8214. It should be noted that incoming
interrupt requests that are not accepted are not latched and must~remain as an
input to the MPB8214 in order to be serviced.

304

FUNCTIONAL
DESCRIPTION

fL PB8214

FUNCTIONAL
DESCRIPTION
(CONT.)

RESTART GENERATION TABLE

~~~UR~~;~--t-7i
I R- ~r*: ~~ r~ r~If~t~
I
~~_'
RST

LOWEST

0,0

R;Tn

1

1

_1

1

1

1

1

1

1

0

R2

5

1

1

1

0

1

R3

4

R6

1

:•r-~r-r
~-~:: : :
110

~- ~

1

1

l1-c---a-

HIGHEST~~d=~
'CAUTION

0

°

0

I

1

~

1
1

I

I

1

1
1

1
,

1

1

1

1

1

0

1

1

1

RST 0 will vector the program counter to iOCfltlQIl 0 (lero) and
Illvoke the same routine as the "RESET" Input to SOSOA.

Current Status Register
The current status register is designed to prevent an incoming interrupt request from
overriding the servicing of an interrupt with higher priority. Via software, the priority
level of the interrupt being serviced by the microprocessor is written into the current
status register on BO-B2' The bit pattern written should be the complement of the
interrupt level_
The interrupt level currently being serviced is written into the current status register
by driving ECS (Enable Current Status) low. The ,uPB8214 will only accept interrupts
with a higher priority than the value contained by the current status register. Note
that the programmer is free to use the current status register for other than as above.
Other levels may be written into it. The comparison may be completely disabled by
driving SGS (Status Group Select) low when ECS is driven low; This will cause the
,uPB8214 to accept incoming interrupts only on the basis of their priority to each
other.
Priority Comparator
The priority comparator circuitry compares the level of the interrupt accepted by the
priority encoder and request latch with the contents of the current status register.
If the incoming request has a priority level higher than that of the current status
register, the INT output is enabled. Note that this comparison can be disabled by
loading the current status register with SGS=O.
Expansion Control Signals
A microcomputer design may often require more than eight different interrupts. The
,uPB8214 is designed so that interrupt system expansion is easily performed via the
use of three signals: ETLG (Enable This Level Group); ENLG (Enable Next Level
Group); and ELR (Enable Level Read). A high input to ETLG indicates that the
,uPB8214 may accept an interrupt. In a typical system, the'ENLG output from one
,uPB8214 is connected to the ETLG input of another ,uPB8214, etc. The ETLG of
the ,uPB8214 with the highest priority is tied high. This configuration sets up
priority among the cascaded ,uPB8214's. The ENLG output will be high for any
device that does not have an interrupt pending, thereby allowing a device with lower
priority to accept interrupts. The ELR inPut is basically a chip enable and allows
hardware or software to selectively disable/enableindividual ,uPB&214's. A low on
the E CR input enables the device.

305

II

fLPB8214
Interrupt Control Circuitry
The ,uPB8214 contains two flip-flops and several gates which determine whether an
accepted interrupt request to the ,uPB8214 will generate a system interrupt to the
8080A. A condition gate drives the D input of the interrupt flip-flop whenever an
interrupt request has been completely accepted. This requires that: the ETlG
(Enable This level Gro\-lp) and INTE (Interrupt Enable) inputs to the ,uPB8214 are
high; the ElR input is low; the incoming request must be of a higher priority than
the contents of the current status register; and the ,uPB8214 must have been enabled
to accept interrupt requests by the clearing of the interrupt disable flip-flop.

FUNCTIONAL
DESCRIPTION
(CONT.)

Once the condition gate drives the D input of the interrupt flip-flop high, a system
interrupt (lNT) to the 8080A is generated on the next rising edge of the ClK input
to the ,uPB8214. This ClK input is typically connected to the 2 (TTL) output of an
8224 so that 8080A set-up time specifications are met. When INT is generated, it
sets the interrupt disable fli~-flop so that no additional system interrupts will be
generated until it is reset. It is reset by driving ECS (Enable Current Status) loW,
thereby writing into the current status register.
It should be noted that the open collector INT output from the ,uPB8214 is active
for only one clock period and thus must be externally latched for inputting to the
8080A. Also, because the INT output is open collector, when ,uPB8214's are
cascaded, an INT output from anyone will set all of the interrupt disable flipflops in the array. Each ,uPB8214's interrupt disable flip-flop must then be
cleared individually in order to generate subsequent system interrupts.

0,
OO=~~============8~O~8~OA~0~A~TA~B~U~S========~========OO
02
02

0,

.-.,-1-++-------- ------.

g~

-----. r-

--- .-g~

~

~

Os

Os

07

REQUESTS

~=

7

=

Fr.iRS1'176

lf7-

T

6
VCC
CLK.'K
~ 'K
),.;,. ltiTE
filINiTT'J>".+++l-4':H-!'l4l' STB
i!,.; Ro
5"'"
DO

'¢2nTLI
INIE R<)INTERRUPT

TYPICAL ILPB8214
CIRCUITRY

I~

ifo' ~

If,< ~
~~

f-t

AD :
~ '0

A2
IlPB
i-=< R7 8214
ETLG '3

c.;..BO

~Bi

4Bi
-----'-< SGS

t

07

'OK
INTJ>:23++t++t+t-l-INT

r

OOo~

~ g~ gg~~

TO 8080A

,S 04 IlPB 004~
'8 05 8212005~
~ 06
00sr;';'i-9----'
~~
0071-'2,-,'_ _--,
CLR_
OS2 MO OS,

--.1'3 GNO
.12

INTA

l'

ENABLE
CURRENT-3 ECS
STATUS
ELR
(FROM 1/0 PORT DECODER L..E.\r;9,",-......J
GNO

Operating Temperature .................................. O~C to +706 C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65¢C to +125°C
All Output and Supply Voltages . • . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +5.5 Volts
Output Currents . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • . ., .... 100 rnA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to 'absolute maximum rating conditions for extended periods may affect device
reliability,

306

ABSOLUTE MAXIMUM
RATINGS*

,",PB8214
DC CHARACTERISTICS

Ta" oOe to +7oo e, Vee = 5V ±5%
SYMBOL

PARAMETER

..

Input Clamp Voltage (all inputs),

Vc
IF

Input Forward Current: . ETLG input
all other inputs
Input Reverse Current: ETLG input
all other inputs
Input LOW Voltage~".all inputs
Input HIGH Voltage: all inputs
Power Supply Current
Output HIGH Voltage: ENLG QutP.ut

,Short Circuit OutpufCurrent: ENLG output

CAPACITANCE@

Current:

Jl.;Jf and

.15
-.08

AO 1\2

YIL'
VIH
ICC
. VOL
NOH
lOS:
ICEX

UNiT

MAX.
-1.0
·0.5
-0.25
80
40
0.8

90
.. 3
3.0
35

Ic~-5mA

V
mA
mA
JJA
JJA
V
V
mA

2.0

2.4
'20

TEST CONDITIONS

130
..45

VF~0.45V .

: VR-5.25V
VCC~5.0V

VCC-5.0V

®

IOL-l0rnA
10H--lmA
rnA· . VOS~OV. VCC 5.0V
JJA
VCEX=5.25V
V

V

-55
100

Ta=25°e
PARAMETER
Input Capacitance'
Output Capacitance

ACCHARACTERISTICS

.

LIMITS
TYP.(j)

IR

Output LOW Voltage: atl outputs

·Output Lea'kage

MIN .

SYMBOL

MIN.

CIN
,COUT

LIMn'S
TYP.(J)

MAX.

5.

10:

7

12.

MIN.

liMITS
TYP.(j)

TEST CONi?ITIONS

!,INIT
pF
pF

VBIAS=2.5V
YCC=5V
f=lmHz.

Ta = oOe to +700 e Vee = +5V -+ 5%
PARAMETER
elK Cycle Time

m. m. INT Pul... Width
INTE Setup Time to ClK
INTE Hqld Time after ClK
ETlG Setup Time to ClK
ETlG Hold Time After ClK
ECS Setup Time to ClK
ECS Hold Time After ClK
ECS Setup Time to ClK
ECS Hold Time After ClK
ECS Setup Time 10 ClK
ECS Hold Time Afler ClK

SYMBOL
tCY
tPW
tlSS
tlSH
tETCS®
tETCH®
tECCS®'

70

"0
70

50

IECSS~
IECSH®

IRCS@
IRCH@
IICS

IREN

E,NlG Propagation Delay

E~S

to ENLG Propagation Delay

Notes:

54
a.StO.1

o.02± 0.004

27.94
G
H

.

I

J

,

L
M

INCHES

2.53

33 MAX.

~t

t.t

t.'

0.059

3.2 MIN.
0.5 MIN.

5.22 MAX.

a.125 MIN.
0.02 MIN.
0.206 MAX.

5.72 MAX.

o.225MAK

ta2
""

o.25±o.l

PACKAGE OUTLINE
IlPB8214C

~6

~52

0.01 to.004

SP8214-2-77-GN-eAT

308

NEe
NEe Microcomputers, Inc.

,...PB8216
,...PB8226

4 BIT PARALLEL BIDIRECTIONAL
BUS DRIVER
DESCR IPTION

FEATURES

All inputs are low power TTL compatible. For driving MaS, the.'DO outputs 'provide
a high 3.6,sV (VOH), and for high capacitance terminated bus structures, the DB
outputs provide a high 55 mA (lOL) capability.

• Data Bus Buffer Driver for "COM·8 Microprocessor Family
•

Low Input Load Current - 0.25 mA Maximum

•

High Output Drive Capability for Driving System Data Bus

• 3.65\1 Output High Voltage for Direct Interface to "COM-8 Microprocessor
Family
• Three State Outputs
•

Reduces System Package Count

• Available in 16 pin packa!!es: Cerdip and Plastic

PIN CONFIGURATION

Vee
DIEN
D0 3
DB3

PIN NAMES

DI3
D02
DB2

000 - 003
OlEN
~

Data Output
Data In Enable Direction Control
.~C~h,p~S~"~~I________~

DI2

Rev/2

309

p.P 88216/8226
Microprocessors like the /JPD8080A are MOS devices and are generally capable of
driving a single TTL load. This also applies to MOS memory devices. This type of drive
is sufficient for small systems with a few components, but often it is necessary to
buffer the miCroprocessor and memories when adding components or expanding to a
multi-board system.

FUNCTIONAL.
DESCRIPTION

The /JPD8216/8226 is a four bit bi·directional bus driver specifically designed to buffer
microcomputer system components.
Bi-Directional Driver
Each buffered line of the four bit driver consists of two separate buffers. They are
three state in nature to achieve direct bus interface and bi-directional capability. On
one side of the driver the output of one buffer and the input of another are tied
together (DB), this is used to interface to the system side components such as memo
ories, I/O, etc. Its interface is directly TTL compatible and it has high drive (55 mAl.
For maximum flexibility on the other side of the driver the inputs and outputs are
separate. They can be tied together so that the driver can be used to buffer a true
bi-directional bus such as the BOBOA Data Bus. The DO outputs on this side of the
driver have a special high voltage output drive capability (3.65V) so that direct interface to the 8080A processor is achieved with an adequate amount of noise immunity
(650 mV worst case).
Control Gating CS,

i5iEN

The CS input is used for device selection. When CS is "high" the output drivers are
all forced tcitheir high·impedance state. When it is "low" the device is selected
(enabled) and the data flow direction is determined by the 01 EN input.
The 5iEiii input controls the data flow direction (see Block Diagrams for complete
truth table). This directional control is accomplished by forcing one of the pair of
buffers to its high impedance state. This allows the other to transmit its data. This is
accomplished by a simple two gate circuit.
The /JPB8216/B226 is a device that will reduce component count in microcomputer
systems and at the same time enhance noise immunity to assure reliable, high
performance operation.

BLOCK DIAGRAMS

8226.
DIOO----D--t---,

01 0
DBa
0°0

D I, <>---II--I:>--+--,

Ol~

DB,
DO,<>----i---<}--i--~

o

DB,
00,

12<>----+---I:::~-+--..,

DI2
OB 2

002o----;---<}--;--~

0°2

013<>----;---C~-;--,

01.3

310

L-----~~----_ocs

OlEN

RESULT

0

DI ... D8

1

0

r--;- -,-

D0 3

CS

CS

0

0

DB3

OlEN <>---...-------'

OlEN

DB" DO

1

) High Impedance

fLPB821618226
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature ... . . .
. . . . . . . . . . . . . . . . . . . O°C to 70°C
Storage Temperature (Cerdip) . .
. ........... -65°C to +150°C
(Plastic) ................ :., .......... -65°Cto+125°C
~II Outpu.t and Supply Voltages ............ ',; '.•..•. '.' '.' . -0.5 to +7 VoltS'
All Input Voltages .......... :
........,., ; ...... -1.3 to +5.5 Volts
. Output. Currents
........ "
...:" ....... 125 mA

COMMENT: Stress above those listed urder "Absolute ·Ma.ximum Ratings" llIay. cause pe:rmanent
damage to the device. This is a stress rating only and functional operation of the device'at these or
any. other conditions above those indicated in the' ope";tional sections. (if this specification is not
implied. ExpOsure to absolute maximum rating condition" for exte~ded 'periods may affect device
. . . .
"
reliabilitY.
'Ta

DC CHARACTERISTICS

= 2poC

T a --0"Cto+70"C VCC-+SV'S'Jf

SYMBOL

PARAMETER
Input Load Current

LIMITS
MIN

TYP(j)

IFl

MAX

UNIT

TEST CONDITIONS

-O.S

mA

VF - O.4S

liTtiii. CS
Input Load Current All
Other Inputs

.IF2

-0.2S"

mA

VF - 0.4S

Input Leakage"Current·

IRl

2U

/lA

VR - S.2SV

IR2

10

~A

VR = S.2SV

Vc

-1.0

V

IC= -S mA

BiEN. CS
Input Leakage

Curren~

01 Inputs

Input Forward Voltage
Clamp
. Input "Low" Voltage
In~ut

VIH

Output Leakage Current DO
(3·State) •
DB
Power Supply Current

8216
8226

2.0

V
V

10
10

2.0
100

~A

ICC
ICC

130
120

mA
mA

VOll

Output "Low" Voltage

Vo = a.4S/S.2SV

0.48

V

DO Outputs IOL lSmA
DB Outputs 10L = 2S mA

8216

VOL2

0.7

V

DB Outputs IOL - 55 rnA

8226

0.7

V

DB Outputs 10H = SamA

Output "High" Voltage

VOL2
VOHl

3.6:

V

DO Outputs 10H =

1 mA

Output "High" Voltage

VOH2

2.4

V

DB Outputs 10H

lamA

Output Short Circuit
Current

In~

Output "Low" Voltage

Note:

CAPACITANCE

0.9S

VIL

"High" Voltage

CD

lOS

lS
-30·

6S
-120

mA
mA

DO Outputs Vo OV
DB Outputs Vce 5.0V

Typical values are for Ta "" 25"e, Vee"" 5.0V:

2 (TTL)

1

STSTB

2

GND

Reset Input.

RESIN

REsiN

SYNC

PIN NAMES

Vee

VDD

RESET

Reset O"utput.

RDYIN

Ready Input

READY

Ready Output

SYNC

Sync Input

STSTii

Status ?,TB

,j;
¢2
XTAL1
XTAL2

Output'

}
}

Processpr
Clocks

Crystal

II

Connections
Used With

TANK

Overtone
Crystal
,OSCillator

OSC

Output
02 C,LK

¢2 (TTLI

Vce
VDD
GND

(TTL Level)

+5V
+12V

OV

313

·IJ.PB8224
FUNCTIONAL DESCR IPTION

Clock Generator
Irhe clock generator circuitry consists of a crystal controlled oscillator and a
divide-by-nine counter. The crystal frequency is a function of the 8080A
processor speed and is basically nine times the processor frequency, i.e.:
Crystal frequency = ~
tCY
where tCY is the 8080A processor clock period.
A series resonant fundamental mode crystal is normally used and is connected
across input pins XTAL 1 and XTAL2. If an overtone mode crystal is used, an
additional LC network, AC coupled to ground. must be connected to the
TANK input of the flPB8224 as shown. in the followi~g figure.

r------,
I

LC =(2;F)2

: FOR OVERTONE CRYSTALS ONLY

I
I

I

01-,

I

,._.±_,3-10 PF

lJ

I (ONLY NEEDED

I
l _

I

I

'- _ _ _ _ _ _ _ J

I

13

14

TANK

OSC

12

_

..I

ABOVE 10MHz~

15

XTALl

XTAL2

11

19 SYNC

The formula for the LC network is:

'--ST'STl3

LC =(_1_)2

21TF

where F is the desired frequency of oscillation.
The output of the oscillator is input to the divide-by-nine counter. It is also
buffered and brought out on the OSC pin, allowing this stable, crystal controlled
source to be used for derivation of other system timing signals. The divide-bynine counter generates the two non-overlapping processor clocks, 5%, VDD

PARAMETER

= t

12V '5%

SYMBOL

Input Current Loading

UNIT

LIMITS

TVP

MIN

0.25

'F

Input Leakage Current

'R

10

Input Forward Clamp Voltage

Ve

-1.0

Input "Low" Voltage

V,L

Input "High" Voltage

V,H

TEST CONDITIONS

MAX
mA

VF

MA

Vo- 525V
Ie

VCC~50V

0.8

Reset Input

2.6

All Other Inputs

2.0
RESIN Input Hysteresis

0.25

VIH-VIL

Output "Low" Voltage

0.45V

-5mA

V

Vee- 5OV

k'l. '-"2L Readv, Reset, STST8

0.45

VOL

2.5mA

10L

All Other Inputs

045

Output "High" Voltage

IOL

0

=

4>,,4>2

94

IOH

READY, RESET

36

'OH

All Other Outputs

2.4

'OH
-60

mA

Power Supply Current

ICC

115

mA

Power Supply Current

100

15

mA

OutPut Short Circuit Current

Ise ([)

·10

Va

(All Low Voltage Outputs Only)

G)

Note:

Ta

=::

Vee

=::

1 MHz; Vee

PARAMETER

=

5V; VOO

=::

12V; VBIAS

SYMBOL

Input Capacitance

CD

CIN

= 2.:_~V

LIMITS
Typi

MIN

Note:

-100p.A
-100;J.A

OV
50V

Cautlon,4>1 and $2 output dnvers do nOI have short CirCuit protection

25°C; f

CAPACITANCECD

15mA

VOH

I

I

I

UNIT

I

pF

I

TEST CONDITIONS

MAX

8

I

ThiS parame~er IS periodically sampled and not 100% tested.

315

JJ. P'B8224 ,
AC CHARACTERISTICS

T a:: Q"c to' +70"C; Vee;;: +5V ±5%; Voo;;: +'1'2V ±5%

'PARAMETER

(i

LIMITS

SYMBOL

TYP

MIN

tPl Pulse Width

tel

2tCY

1/>2 Pulse Width

t¢2

5tCY

4>1 to q,2 Delay

tOI

1>2 to ¢, Delay

t02

2tCY

1/>1 to <1>2 Delay

t03

2tCY

cJ>, and 1/>2 Rise Time

tR

tP1 and $2 Fall Time

tF

4>2 to $2 (TTLl Delay

t04l2

MAX

"

9 - 2On5
"'9

TEST IlpNOITIONS

UIliIT

-35n5
ns

0

""""9"

CL = 20 pF to 50 pF

-14n5

2tCY

9

9

+20n5
20
20

-5

+15

ns

(>2 TTL, CL - 30 pF

Rl =300H

,R2=600.u
(~2

t('1 ':;TST8

09~ay

6tCY

tDSS

STSTB Pulse Width

tpw

RDVIN Setup Time

tORS

6tCY

S

tCY

9

-30ns

RDVIN Hold Time

ns

-15n5

50n5-

toSTsTB

9

ST~:B, CL = 15 pF

4tCY

g-

ns

A,; ~K
A2 =4K

4tCY

After ""STSB

tORH

-9-

READY or RESET

'DR

4tCY

9

to q,2 Oelay

ns

-25n5

R?~P.Y

R,
A2
Crystal Frequency

= 2K
= 4K

MH,

...lL.

fCLK

and Reset

CL'';'10pF

tCY

Maximum Oscillating

27

fMAX

MH,

Frequency

CD

Note:

ICY represents the processor clock period
vcc,

rN~UT

~
J

CL
GND

"1

R2

~ GND

TEST CIRCUIT

TIMING WAVEFORMS

'R
';'1

- __-Nr---'D2

'·'2

--f'l

',.2 ITTLl _ _ _ _ _ _ _ _ _ _

SYNC
(FROM PROCESSOR)
1------IDSS+------11-

~---'O"H---_I
RDVIN OR

R'E'Si'N
'DR

READY -

- -

- -

- - - -

-

-

- -

- -

- -

-

-'\,.----+----------

---------"1"-------------- ------ ---- ---'DR

RESET

Voltage Measurement Points: <1>1, <1>2 Logic "0" = 1.0V, Logic "1"
All other signals measured at '1.5V.
316

= 8.0V,

p.PB8224
CRYSTAL REQUIREMENTS Tolerance . . . . .

0.005% at 0° C-700 C
Series (Fundamental) (j)
. 20·35 pF
75·20 ohms
... 4mW

Resonance
Load Capacitance
Equivalent Resistance ..
Power Dissipation (Min)

nsists of a status latch for
definition of processor machine cycles and a gating array to decode this information
for direct interface to system components. The controller can enable gating of a
multi·byte interrupt onto the data bus or can automatically insert a RESTART 7 onto
the data bus .without any additional components.
Two devices are provided. The JlPB8228 fo(small systems without tight write timing
constraints and the JlPB8238 for larger systems.

FEA TU RES

• System Controller for 8080A Systems
•

Bi·Directional Data Bus for Processor Isolation

•

3.60V Output High Voltage for Direct Interface to 8080A Processor

• • Three State Outputs on System Data Bus

PIN CONFIGURATION

•

Enables Use of Multi·Byte I nterrupt Instructions

•

Generates RST 7 Interrupt Instruction

•

JlPB8228 for Small Memory Systems

•

JlPB8238 for Large Memury Systems

•

Reduces System Package Count

•

Schottky Bipolar Technology

STffi

vcc

HLDA

I/OW

WR

PIN NAMES

MEMW

DBIN
DB4
D4

I/OR

07- Do
DB7 DB

Data Bus (Processor Side)

MEMR

IIOR

00 Read

INTA

ii1JSEi'ii

DB7
D7

DS

DB3

DBS

D3

D5

DB2

DBS

D2
DBO

Dl
DBI

GND

DO

Data Bus (System Side)

IIOW

I/O Write

MEMR

Memory Read

MEMW

Memory Write

DBIN

OBI N (From Processor)

INTA

I nterrupt Acknowledge

HLDA

HLDA (From Processor)

WR

WR (From Processor)

aUSEN

Bus Enable Input

STSTB

Status Strobe I From ",P88224)

VCC
GND

+5V

o Volts

NC: No Connection

Revll
319

fLP 88228/8238
Bi-Directional Bus Driver
The eight bit, bi-directional bus driver provides buffering between the processor data
bus and the system data bus. On the processor side, the IlPB8228/8238 exceeds the
minimum input voltage requirements (3.0V) of the IlPD8080A. On the system si,de,
the driver is capable of adequate drive current (10 mAl for connection of a'iarge
number of memory and 1/0 devices to the bus. Signal flow in the bus driver is controlled by the gating array and its outputs can be forced into a high impedance state
by use of the BUSEN input.

FUNCTIONAL DESCRIPTION

Status Latch
The Status Latch in the IlPB8228/8238 stores the status information placed on the
data bus by the 8080A at the beginning of each machine cycle. The information is
latched when STSTB goes low and is then decoded by the gating array for the
generation of control signals.
Gating Array
The Gating Array generates "active low" control signals for direct interfacing to system
components by gating the contents of the status latch with control signals from the
8080A.
MEM/R, liaR and INTA are generated by gating the O'BIN signal from the processor
with the contents of the status latch, 1/0 R is used to enable an 1/0 input onto the
system data bus. MEM/R is used to enable a memory input.
INTA is normally used to gate an interrupt instruction onto the system data bus, When
used with the IlP08080A processor, the IlPB8228/8238 will decode an interrupt
acknowledge status word during all three machine cycles for a mUlti-byte interrupt
instruction. For 8080A type processors that do not generate an interrupt acknowledge
status word during the second and third machine cycles of a multi-byte interrupt
instruction, the IlPB8228/8238 will internally generate an INTA pulse for those
machine cycles.
The IlPB8228/8238 also provides the designer the ability to place a single interrupt
instruction onto the bus without adding additional components. By connecting the
+12 volt supply to the INTA output (pin 23) of the IlPB8228/8238 through a 1 K
ohm series resistor, RESTART 7 will be gated onto the processor data bus when OBIN
is active during an interrupt acknowledge machine cycle.
MEM/W and IIOW are generated by gating the WR signal from the processor with the
contents of the status latch. IIOW indicates that an output port write is about to
occur. MEM/W indicates that a memory write will occur.
The data bus output buffers and control signal buffers can be asynchronously forced
into a high impedance state by placing a high on the BUSEN pin of the IlPB82281
8238. Normal operation is performed with BDSEN low.

BLOCK DIAGRAM

DBa
DB,

PROCESSOR

D3

DATA
BUS

vee®GNO@-

320

SYSTEM DATA BUS

p.PB'8228/8238
ABSOLUTE
MAXIMUM RATINGS*

Operating Temperature
Storage Temperature
All Output or Supply Voltages
All Input Voltag.es ..
Output Currents

••

.. O°C to +7Qo~
-65°C to +1509 (;
. -0.5 to +7 Volts
-1.5 to 5.5 Volts
. . . . . . . 100mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only -and functional 'operation of the device at these or
any other conditions above those indicated in the operational sections of,this specification i~ 'not
implied. Exposure to absolute maximum rating conditions for- extended per'iods may affect device
reliability.

DC CHARACTERISTICS
LIMITS

PARAMETER

SYMBOL

Input Clamp Voltage, All Inputs

Ve

Input Load Current. STSTB

'F

MIN

TVP

'R

All Other Inputs
Input Threshold Voltage, All Inputs

VTH

Power Supply Current

ICC

Output Low Voltage, DO through D7

VOL

"A

Vee: 5.25V

"A.

VF == OASV

250

"A

100

"A

20

"A

100

"A

2.0

Ctrc~it

V
rnA

190

Off State Output Current,
All Control Outputs

10 (oft)

INT A Current

liNT

VR·S.OV
Vee' SV
Vee· S.2SV

Vee,:: 4. 75V; tOl = 2 rnA

0.48

V

tOl'" 10mA

V

Vee = 4.75V; 10H = -lO"A

V

15

lOS

Vee' 5.2SV

V

2.4

Current, All Outputs

-5 rnA

0.45

3.6

All Other Outputs

==

"A

750

0.8

VOH

TEST CONDITIONS
Vee - 4.75V; ICC

250

All Other Outputs

Short

V

5PO

DBO through DB7

Output High Voltage, DO through D7

UNIT

-1.0

All Other Inputs
Input Leakage Current, STSTB

MAX

IOH =-1 rnA

90

rnA

100

"A

Vee == 5.25V: Vo == 5.0V

-100

"A

Vo '" OASV

rnA

Vee = 5V

(See Figure below)

Q2V

~''''

INTA 23

10%

II

I

liNT

INTA TEST CIRCUIT

CAPACITANCE
LIMITS
PARAMETER

Input Capacitance

SYMBOL

MIN

TYP

MAX

UNIT

TEST.
CONDITIONS

CIN

12

pF

VBIAS

Output Capacitance
Con'trol Signa'ls

COUT.

15

pF

VCC

I/O Capacitance
100r DB)

CI/O

15

pP

f

=

=

=

2.5V.

5.0V.

1 MHz

NOTE: This parameter ,is periodically sampled and not 100% tested.

321

fL PB822818238
Ta O"c to
=

e, vee =

700

5V

5%

:!-

AC CHARACTERISTICS
LIMITS

PARAMETER

SYMBOL

Width of Status Strobe

tpw

Setup Time, Status Inputs

TVP

UNIT

MAX

CONDITIONS

22

tss

DO"°7

Hoi"Time, Status InpuTS 00-07
Delay from STSTS to

MIN

TEST

tSH

dny

toe

Control SIgnal
Delay from DBIN to Control

20

60

CL -'" 100 pF

ns

CL" 100 p~,

tRR

30

tRE

45

CL = 2SpF

tRO

30

CL" 25pF

Outputs

tWR

45

CL=100pF

Delay to Enable System Bus
DBa-DB7 after STSTS

tWE

30

CL -' 100pF

two

40

CL = 10QpF

IE

30

CL=10QpF

Outputs
Delay from DBIN to·Enablel
Disable aOSOA Bus

Delay from System Bus to
SOaOA 8us during Read
Delay from WR to Control

Delay from SOSOA Bus DO-D7

to System Bus DBa-DB7 during
Write

Delay from System Bus Enable
to System Bus DBO-DB7

HLDA to Read Status Outputs

IHO

Setup Time, System Bus
Inputs to HLDA

tos

10

IOH

20

Hold Time. System Bus
Inputs to HLDA

25

For 00·07: Rl '" 4 Kn. R2 '" ""n,
Cl = ,25 pF. For all other outputs
Rl '" 500n, A2 '" 1 Kn, Cl

=

100 pF.
OUTPUT
PIN

CL=100pF

trl
' .

l :~ND

=

",

vcc

::D

TEST CIRCUIT

TIMING WAVEFORMS

"I

1'--+-+_..Jf'-__________________

PROCESSOR DATA BUS _ _ _ _ _

INTA.liDA, MEMR'------~

,+---+---j-I1

DURING HLDA

-t-w--'--7--.lv-- - - - - - - - - - - - - -4--'1'---+-'1'-- - - - - - - - - - - - -

SYSTEM BUS DURING READ _ _ _ _ _ _ _ _ _

PRoceSSOR BUS DURING READ -

jlPB8228 I/OWor MEMW

-- -

-

-

-

-

--

-------+-+--------'-'l----1
IDC

1-

"PB8238 IIOW or MEMW .

PROCESSOR BUS DURING WRITE
SYSTEM BUS DURING WRITE. _ _ _ _ _ _ _ _ _

j

BUsEN,

,
SYSTEMBUSOUTPUTS~--:....-· -

}
-'E~

-

-

---

--------- - - - - - -- - ---

VOLTAGE MEASUREMENT POINTS

322,

.°

0 0 7 [when output,1
dt 1.5V

Log.~

"0"

0 BV. Log" .""

3 OV

All 1 182511
420n 18251AI

>-

+10



to "turn the line around." The TxEn bit in the
co~mand ,instruction does not effect TxE.
In the Synchronous mode, a "one" on this output indicates that a Sync character or character~ are about to be automatically transmhted
as "fillers" because, the next data character, has
not been loaded,
The Transmitter Clock controls the. serial charllc
ter transmission rate. In "the Asynchronous
mode, file Tx-C frequency is a multiple of the
actual Baud Rate. Two bits of the Mode Instruction select the multiple·to be 1 x, 16x, or 64x
the BaudRate. In the Synchronous mode, the
TxC frequency is automatically selected to
equal the actual Ilaud Rate.
Note that for both Synchronous and Asynchronous modes, serial data is sh ifted out of the
USART by the falling edge of.TxC.
The Transmit CoritTol Logic outputs the
composite serial data stream
thi.s pin.

Clock

0"

\

ADDRESS BUS

II

AO

}

\

CONTROL BUS

I/O R

\

-IIOW

RESET

,,2
(TTL)

\

OATA Bl)S

~
·8

c/D

CS

V
D7 - DO

RD

WR.

RESEt

ClK

itPD8251/8251A

339

jLPD8251/8251 A
The Receive Buffer ilccepts serial data input at the RxD pin and converts the data
from serial to parallel format, Bits or characters required for the specific communication technique in use are checked and then an eight-bit "assembled" character is
readied for the processor_ For communication techniques which require less than
eight bits, the ILPD8251 and ILPD8251 A set the extra bits to "zero_"

PIN IDENTIFICATION

PIN
NO_

SYMBOL

RxRDY

FUNCTION

NAME

Receiver Control Logic
14

RECEIVE BUFFER

Reteiver ReadY

..

This block manages.all activities related to
incoming'data.

The Reseiver Ready output indicates that the
ReceiveLBuffer is ready with an "assembled"
character for input to the processor. f.or Polled
operation. the processor can check RxRDY
using a Status Read or RxRDY can be con-

nected to the processor interrupt structure.
Note that reading the character to the processor automatically resets RxR DY.

25

RxC

Receiver Clock

The Receiver Clock determines the rate at which
the incoming character is received. In the Asyn-

chronous mode, the RxC frequency may be 1.16
or 64 times the actual Baud Rate but in the Synchronous mode the i"fXC frequency must equal
the Baud Rate. Two bits in the mode instruction

select Asynchronous at lx, 16x or 64x or Synchronous operation at 1x the Baud Rate.

Unlike TxC, data is sampled by the I'PD8251 and
I'PD8251 A on the rising edge of'R'X'C.

LPD8251 and MPD8251A to define th'e
desired mode and communications format. The c.ontrol words will specify the BAUD
RATE FACTOR (lx, 16x, 64x), CHARACTER LENGTH (5 to 8), NUMBER OF
STOP BITS (1, 1·1/2,2) ASYNCHRONOUS or SYi\JCHRONOUS MODE, SYNDET
(IN or OUT), PARITY, etc.
After receiving the control words, the MPD8251 and MPD8251A are ready to communicate. TxRDY is raised to signal the processor that the USART is ready to receive a
character for transmission. When the processor writes a character to the USART,
TxRDY is automatically reset.
Concurrently, the >LPD8251 and >LPD8251A may receive serial data; ~nd after
receiving an entirecharacter, the RxRDY output is raised to indicate a completed
character is ready for the processor. The processor fetch will automatically reset
RxRDY.
Note:

The MPD8251 and .,uPD8251A may provide faulty RxRDY for the first.reqd
after power-on or for the fi,rst read after receive ,is re-enabled by a command
instruction{Rx~). A dummy read is recommended to clear faulty RxRDY.
But this is not 'the case for the first read after hardware or software reset
after the device operation has once been established.
The MPD8251 and MPD8251A cannot transmit until the TxEN (Transmitter
Enable) bit has been set by' a Command Irlstruction and until the CTS '(Clear
to Send) input is a "zero": TxD is held in the "marking" state after Reset
awaiting new control words.

USART PROG RAMM I NG

The USART must be loaded with a group of two to four control words provided by
the processor before data reception and transmission can begin: A Reset (internal or
external) must immediately proceep the control wordswhi~1i are used to program the
complete operational description of the communicationsinterfa'ce.lf,~n ext~rnal
RESET is not available, three successive 00 Hex or two successive 80 Hex command
inst~i.Jcti(>ns (Cio'= j) followed by a software reset co'mmand instruction (40 Hex)
can be used to initia:iize the MPD8251 and >LPD8251A.
There are two cOr]trol word formats:
1. Mode Instruction
2. Command Instruction

MODE INSTRUCTION

COMMAND I NSTRUCTION

cha,racteristi'~S~,

This control ord spec,ifi,es the general
,f the interf,ace regarding the
,
SYNCHRONOUS or ASYNCHRONOUS MODE, BAUD RATE FACTOR, CHARACTER
LENGTH, PARITY, arid NUMBER OF STOP BITS. Once the Mode Instruction
'
has been received, SYNC characters or Command Instructi()ns may be inserted dependingon the Mode Instruction content.
W,

This control word will be inte~preted as a SYNC ch~;act'er definition if immediateiy
preceded by a Mode Instruction which spe~ified '~' Synch;onous format. After the
SYNC character(s) are' specified or after an AsynchrOhous Mode I nstruction, all subsequent control wordswill be interpreted as an upd~te to the"Command Instruction.',
Command Instruction updates may occur a,t any timedur'i!J9 the data bi,oC;k. To
modify the,Mode Instruction: a bit may be ~et in theComrnand Instruction which
cause's an internal Reset which allows a new Mode Instruction to be acceptep,

-,

'

341

7

fL P08251:/8251 A
c/o = 1

MODE INSTRUCTION

C/D= 1

SYNC CHARACTER 1

C/O = 1

SYNC CHARACTER 2

C/O = 1

COMMAND INSTRUCTION

C/O

=

}

C/O = 0

SYNC MODE
ONLY

efore the STOP bitisl. as specified by the
Mode Instruction. Then, depending on CTS and TxEN, 'the character. may be trans·
mitted as a serial data stream at the TxD output. Data is shifted out by the falling
edge of TxC at TxC, TxC/16 or TxC/64, as defined by the Mode Instruction.

ASYNCHRONOUS
TRANSMISSION

If no data characters have been loaded into the /JPD8251 and /JPD8251A, or if all
available characters have been transmitted, the TxD output remains "high" (marking)
in preparation for sending the START bit of the next character provided by the
processor. TxD may be forced to send a BREAK (continuously low) by setting the cor·
rect bit in the Command Instruction.
The RxD input line is normally held "high" (marking) by the transmitting device.
A falling edge at RxD signals the possible 'beginning of a START bit and 'a new
character. The START bit is checked by testing for a "Jow" at its nominal', center
as specified by the BAUD RATE. If a "low" is detected again, it is considered valid,
and the bit assembling counter starts counting. The bit counter locates the approxi ..
mate center of the date, parity (if specified), and STOP bits. The parity error flag (PE)
is set, ,if a parity error occurs. I,nput bits are sampled at the RxD pin with the rising
edge of RxC. If a high is not detected for the srop bit, which normally signais the end
of an input character, a framing ~rror (FE) willl:>e set. After a valid STOP bit. the input
character is loaded into the parallel Oata Bus Buffer of the /JPD8251 and /JPD8251A
and the RxRDY signal is raised to ihdicate to the processor that a character is ready to
be fetched. 'If the processcirhas failed to fetch the p'revious character, the new character replaces the old and the overrun flag (OE) is set. All the error flags can be reset
by setting abit in the Command Instruction. Error flag conditions will not stop subsequent USART operation.
,,342

ASYNCHRONOUS
RECEIVE

p.PD8251/8251A
MODE INSTRUCTION
FORMAT

ASYNCHRONOUS MODE

1 s21

S1 1 EP 1 PEN 1 L21

L1 1 B21

B1

1

L

BAUD RATE FACTOR
1

0

1

0

0

0

1

1

SYNC
MODE

I1XI

116XI

164XI

CHARACTER LENGTH
0

1

0

1

8

1

0

0

1

5

6

BITS

BITS

7
BITS

BITS

PARITY ENABLE
1 = ENABLE
O=DISABLE
EVEN PARITY GENERATION/CHEC K
1 = EVEN
0= ODD
NUMBER OF STOP BITS

0

1

0

0

1

1

INVALID

1
BIT

W,

2
SITS

..
TRANSMIT/RECEIVE
FORMAT
ASYNCHRONOUS MODE

TxD

1

0

BITS

ST~

MARKING

BITS

L

TRANSMITTER OUTPUT
DO

01

02

i t

START
BIT

RxD

I

DA T

~ _IT_S-,~~,-\-B

STOn
BITS

L

_ _ _-,

RECEIVER INPUT
PROCESSOR BYTE (5-8 BITS/CHARI

DATA

C:~RACTER

ASSEMBLED SERIAL DATA OUTPUT ITxDI

,--S_T_BA_I~_T~

D_A_T_A,~HARACTER

STOn

___

BITW

TRANSMISSION FORMAT
SERIAL DATA INPUT IRxDI

r---,--------il f----.----.----i

ST:I~T

tJ

~~~;

DATA CHARACTER

'------'-----1
PROCESSOR BYTE 15-8 BITS/CHARI

G>

;l
DATA CHA;ACTER
RECEIVE FORMAT
Notes:

CD

Q)

G)

Generated by pPD8251/8251 A
Does not appear on the Data Bus.
If character length is defined as 5, 6, or 7 bits, the

unused bits are set to "zero."

343

IkP D82.51 /8251 A
SYNCHRONOUS
TRANSMISSION

As in Asynchronous transmission, the TxD putput remains "high" (marking)
until the pPD8251 and pPD8251 A receive the first character (usually a SYNC
character) from the processor. After a Command Instruction has set TxEN and
after Clear to Send (CTS) goes low, the first character is serially transmitted.
Data is shifted out on the falling edge of TxC and the same rate as TxC.
Once transmission has started, Synchronous Mode format requires that the serial data
stream at TxD conti.nue at the TxC rate or SYNC will be lost. If a data character is
not provided by the processor before the pPD8251 and pPD8251A Transmit
Buffer becomes empty, the SYNC character(s) loaded directly following the Mode
Instruction will be automatically inserted in the TxD data stream. The SYNC
character(sl are inserted to fill the line and maintain synchronization until new data
characters are available for transmission. If the pPD8251 and pPD8251A become
empty, and must send the SYNC character(sl. the TxEMPTY output is raised to signal
the processor that the Transmitter Buffer is empty and SYNC characters are being
transmitted. TxEMPTY is automatically reset by the next character from the processor.
In Synchronous Receive, character synchronization can be either external or internal.
If the internal SYNC mode has been selected, and the Enter HUNT (EH) bit
has been set by a Command Instruction, the receiver goes into the HUNT mode.

SYNCHRONOUS
RECEIVE

Incoming data on the RxD input is sampled on the rising edge of RxC, and the
Receive Buffer is compared with the first SYNC character after each bit has been
loaded until a match is found. If two SYNC characters have been programmed, the
next received character is also compared. When the SYNC character(s) programmed
have been detected, the pPD8251 and pPD8251A leave the HUNT mode and are in char·
acter synchronization. At this time, the SYNDET (output) i.s set high. SYNDET is
automatically reset by a STATUS READ.
If external SYNC has been specified in the Mode Instruction, a "one" applied
to the SYNDET (input) for at least one RxC cycle will synchronize the USART.
Parity and Overrun Errors are treated the same in the Synchronous as in the
Asynchronous Mode. If not in HUNT, parity will continue to be checked even
if the receiver is not enabled. Framing errors do not apply in the Synchronous
format.
The processor may command the receiver to enter the HUNT mode with a Command
Instruction which sets Enter HUNT (EH) if synchronization is lost.
07

D6

05

04

03

02

D1

DO

I I I I IL21 L, I I I
I
ses

ESD

EP

PEN

0

CHARACTER LENGTH

0

1

0

0

0

1

1

5

6

8

BITS

BITS

7
BITS

I

I

I

MODE INSTRUCTION
FORMAT
SYNCHRONOUS MODE

0

1

BITS

PARITY ENABLE
11 ENABLE)
10 DISABLE)

..

EVEN PARITY GENERATION/CHE eK
1 EVEN
ODD

0

EXTERNAL SYNC DETECT
1 SYNDEr IS AN INPUT
SYNDET IS AN OUTPUT

0

51 NG LE CHARACTER SYNC
1 SINGLE SYNC CHARACTER
DOUBLE SYNC CHARACTER

o

344

p,PD8251/8251A
TRANSMIT/RECEIVE
FORMAT
SYNCHRONOUS MODE

PROCESSOR BYTES 15-8 BITS/CHARI

DATA
ASSE~1BLED

C~A:RACTERS

"

SERIAL DATA OUTPUT ITxDI

DA T A, CH A RS-:_CT_E_R_S_ _ _.J

TRANSMIT FORMAT
SERIAL DATA INPUT IRxDI

DAT~CHAR;~_C_TE_R_S

____

PR'OCESSOR BYTES 15-8 BLTS'CHARI

I

~

CD

DATAC:~
RECEIVE FORMAT

Note:

CD

If character length

IS

defined as 5, 6

01"

7 bits, the unused

bits are set to "zero."

COMMAND INSTRUCTION
FORMAT

STATUS READ FORMAT

PARITY ERROR

OVERRUN ERROR

FRAMING ERROR

CD

After the fUflctional definition of the pPD8251 and pPD8251A has been specified by
the Mode Instruction and the SYNC character(s) have been entered (if in SYNC mode),
the USART is ready to receive Command Instructions and begin communication. A
Command Instruction is used to control the specific operation of the format selected
by the Mode Instruction. Enable Transmit, Enable Receive, Error Reset and Modem
Controls are controlled by the Command Instruction.
After the Mode Instruction and the SYNC character(s) (as needed) are loaded, all
subsequent "control writes" (C/O = 1) will load or overwrite the Command Instruction
register. A ReSet operation (internal via CMD IR or external via the RESET input)
will cause ;the pPD8251 and pPD8251A to interpret the next "control write", which
must immediately follow the reset, as a Mode Instruction.
It is frequently necessary for the processor to examine the status of an active
interface device to determine if errors have occurred or if there are other conditions
which require a response from the processor. The pPD8251 and pPD8251A have
features which allow the processor to read the device status at any time. A data fetch
is issued by the processor while holding the C/O input "high" to obtain device Status
Information. Many of the bits in the status register are copies of external pins. This
dual status arr ~ clock periods, where N is the decimal value of count
data), If the count register is reloaded with a new value during counting, the new value
will be reflected immediately after the output transition of the current count,
The OUTPUT will be held in the high state while GATE is asserted, Counting will start
from the full count data after the GATE has been removed,

0141

3

2

1

0[41

3

2

I

0141

3

2

I

0151

4

3

2

1

0151

4

3

2

1

0151

4

0141

OUTPUT n

OUTPUT"

3

.~

GATE
[RESET)

0141

4

3

2

1014).3

2

10[41

PUTPUT n

Mode 4: Software Triggered Strobe
The OUTPUT goes high when MODE 4 is set, and counting begins after the second
byte of data has been loaded, When the terminal count is reached, the OUTPUT will
pulse low for one clock period, Changes in count data are reflected in the OUTPUT as
soon as the new data has been loaded into the count registers. During the loading of
new data, the OUTPUT is held high and counting is inhibited,
The OUTPUT is held high for the duration of GATE, The counters are reset and
counting begins from the full data value after GATE is removed.

JlJLJlJU1JU1JU1J1JlJlJ1
led
OUTPUT"

u

GAT~",

UUTPur.)

Mode 5: Hardware Triggered Strobe
Loading MODE 5 sets OUTPUT high. Counting begins when count data is loaded and
GATE goes high, After terminal count is reached, the OUTPUT wi'l pulse low for one
clock period, Subsequent trigger pulses will restart the counting se';uence with the
OUTPUT pulsing Iowan terminal count following the last rising ecge of the trigger
input (Reference bottom half of timing diagram),

rT~~J(~Ef11
OUTPUT"

355

ILPD8253

I"

A-----

£3,
0-15°

PACKAGE
ILPD8253C OUTLINE
ILPD8253C-5

I--

SP8253-9·78•G N·CAT
356

NE'C

NEe Microcomputers, Inc.

fLPD8255.
fLPD8255A·5*

PROGRAMMABLE PERIPHERAL INTERFACES
DESCRIPTION

F EATU R ES

PIN CONFIGURATION

The pPD8255 and pPD8255A-5 are general purpose programmable INPUT/OUTPUT
devices designed for use with the 8080A/8085A microprocessors. Twe~ty-four (24)
I/O lines may be programmeq in two groups of twelve (group! and groupII)~nd used
in three modes of operation. In the Basic mode, (MODE 0), each group of twelve I/O
pins may be programmed ih sets of 4 to be input or output. In the Strobed mode,
(MODE 1), each group may be programmed to have 8 I ines of input or output, Three
of the remaining four pins in each group are used for handshaking 'strobes and interrupt
control signals. The Bidirectional Bus made, (MODE 2), uses the8 lines of Port A for
a bidirectional bus, and five lines from Port C for bus control signals': The pPD8255
and pPD8255A-5 are packaged in 40'pin plastic dual-in-I ine packages.

• Fully Compatible with the 8080A/8085 Microprocessor Families
•

All Inputs and Outputs TTL Compatible

•

24 Pn;>grammable I/O Pins

•

Direct Bit SET/RESET Eases Control Application Interfaces

•

8 - 2 mA Darlington Drive Outputs for Printers and Displays (}.lPD8255)

•

8 - 4 mA Darlington. Drive Outputs for Printers and Displays (pPD8255A-5)

•

LSI Drastically Reduces System Package Count

•

Standard40 Pin Dual-In-Line Plastic Package

PA3
PA2
PAl
PAa
RD

PA4
PA5
PA6
PA7
WR
RESET
DO
D1
D2
D3
D4
D5
D6

cs

GND
A1
Aa
PC7
PC6
PC5
PC4
PCa
PC,
PC2.
PC3
PCa
PC,
PC2

pPD
8255/
8255A-5

PIN NAMES'
07- 0 0
RESET

Data Bus (Bi-Dlrectional)
Reset Input

CS

ChiP Select
Read Input

RO
WR

Ab, Al
PA].-Mo

II

Write Input
Port Address
Port A (Bit)

PB1-PBo
PC7-PCO

Port 8 (Bit)

VCC

+5 Volts

GNO

o Volts

Port C (Bid

D7

vcc
PB7
PB6
PB5
P,B4
PB3

* All data pertaining to the pPD8255A-5 is preliminary.
Rev/2

357

J.L PQ8255/8255A·5
General
FUNCTIONAL DESCRIPTION
The /lPDS255 and/lPD8255A-5 Programmable Peripheral Interfaces (PPllare designed
for use in SOSOA/SOS5A microprocessor systems. Peripheral equipment can be effectively
and efficiently interfaced to the S080A/SOS5A data and control busses with the /lPDS255
and /lPD8255A:5. The /lPDS255 and /lPDS255A.5 are functionally configured to be
programmed by system software to avoid external logic for peripheral interfaces.
Data Bus Buffer
The 3-state, bidirectional, eight bit Data Bus Buffer (DO·D7) of the /lPDS255 and .
/lPDS255A-5 can be directly interfaced to the Pfoce'lor's system Data Bus (DO·D7).
The Data aus Buffer is controlled by execution of IN and OUT instructions by the
processor. Control Words and Status information are also transmitted via the Data Bus
Buffer.
Read/Write and Control Logic
This block manages all of the internal and external transfers of Data, Control and
Status. Through this block, the processor Address and Control busses can control the
peripheral.interfaces.
. .
Chip Select, CS,. pin 6
A Logic Low, VI L. on this input enables the /lPDS255 and /lPDS255A-5 for com·
munication with the SOSOA/SOS5A.
Read, RD, pin 5
A Logic Low, VIL, on this input enables the MPDS255 and /lPDS255A-5 to send Data
or Status to the processor via the Data Bus Buffer.
Write, WR, pin 36
A Logic Low, VIL, on this input enables the Data Bus Buffer to receive Data or Con·
trol Words from the processor.
Port Select 0, AO, pin 9
Port Select 1, A1, pin S
These two inputs are used in conjunction with CS, RD, and WR to control the selec·
tion of one of three ports on the Control Word Register. AO and A 1 are usually
connected to AO and Al of the processor Address Bus.
Reset, pin 35
A Logic High, VIH, on this input clears the Control Register and sets ports A, B, and
C to the input mode. The input latches in ports A, B, and C are not cleared."· .
Group I and Group II Controls
Through an OUT instruction in System S.oftware from the processor, a control wOrd
is transmitted to the pPDS255 and /lPDS255A-5. Information such as "MODE," .
"Bit SET," and "Bit RESET" is used to initialize the functional configuration of each
I/O port.
Each group (I and II) accepts "commands" from the Read/INrite Control Logic and
"control words" from the internal data bus and.in turn controls its associated I/O
ports.
Group I - Port A and upper Port C (PC7-PC4)
Group II - Port Band 10iNer Port C (PC3-PCO)
While the Control Word Register can be written into, the contents cannot be read back
to the processor.
,
Ports A, B, and C
The three S·bit I/O ports (A, B, and C) in the /lPDS255 and /lPDS255A-5 can aU be
configured to meet a wide variety of functional requirements through system software.
The effectiveness and flexibility of the /lPDS255 and 'J,lPDS255A-5 is further
enhanced by special features unique to each of the ports.
Port A = An S·bit data output latch/buffer and data input latch.
Port B = An S·bit data input/output latch/buffer and an S·bit data input buffer.
Port C = An S·bit output latch/buffer and a data input buffer (input not latched).
Port C may be divided into two independent 4-bit control and status ports for use with
Ports A and B.

358

fL PD8255/8255A·5
BLOCK DIAGRAM

,,----~

ABSOLUTE MAXIMUM
RATINGS'

o°C to +70°C
-65°C to +125°C
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts

Operating Temperature
Storage Temperature ..
All Output Voltages CD.
All Input Voltages CD
Supply Voltages G) ...
Note:

CD

With respect to VSS

COMMENT: Stress above those listed, under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS
LIMITS
,tIPD8255

j.jPD8255A-5

TVP MAX

MIN

TYP

MIN

~~t Low Voltage

V,L

vss-o.s

InfJut High Voltage

V,H

Output Low Voltage

VOL

Output High Voltage

VOH

Darlington Drive Current

10H('

-2

Power Supply Current

ICC

40

Input Leakage Current

ILiH

10

Input leakage Current

Ilil

-10

MA

VOUT - Vec, CS

MA

VOUT -- a 4V. CS

08 -0.5

Vce

2.4

2.4

v

40

120

II

V

-4

mA

VOH - 1.5V. REXT

120

mA

Vce -

10

MA

VII\)'o Vec

-10

MA

VIN

Output leakdge Current

IlOH

10

Output leakage Current

IlOl

-10

-10

CD

V

0.4

10

Notes.

UNIT

08

Vee

2

MAX

TEST
CONDITIONS

SYMBOL

PARAMETER

t

7bO~l

5V. Output Open

D.4V
~

20V
20V

Any set of eight 181 outputs from either POri A, 1:3, or C can ,(JUice 2 mA into 1 5V fa' j.lP08255. or 4 mA Into
1 SV for j.lP08255A·5

@

For ,"PD8255 10l.
1 7 mA
For )..IP08255A-5 10l - 2 5 mA for DB Po't. 17 mA tor PerlpFjernl Porto

@

-100
For

CAPACITANCE

Ta

0

25'C; VCC

IOH

0

for DB

J1S

-400

POll,

50).lS lor Perlphera: Ports

tor DB Port. -200)Js for Peripheral Ports

VSS ~ OV

PARAMETER

SYMBOL

LIMITS
MIN TYP MAX UNIT

TEST CONDITIONS

Input Capacitance

CIN

10

pF

Ic~lMH7

1/0 Capacitance

CI/O

20

pF

LJnnwasured pins
returned to VSS

359

fL PD8255/8255A~5
AC CHARACTERISTICS

TI - (fCtO+7O"c;VCC. +5V t. 9o;VSS· OV
LIMITS

SYMBOL

PARAMETER

08....
MIN MAX

....

MIN

MAX

UNIT

TIlT
CONDtTIONI

READ
Add.... hble B.fo... ~

'AR

Addrea Salbli :A.fUr JI!'Ali

'RA

READ PuIleWldth

'RR

011111 Velld From n1Ari

&0
0
-

Plastic
ITEM

MILLIMETERS

A

51.5 MAX

INCHES
2.028 MAX

B

1.62

0.064

C

2.54 ± 0.1

0.10. ± 0.004

0

0.5 ± 0.1

0.019 ± .0.004

E
F

48.26

1.9

1.2 MIN

0.047 MIN

G

2.54 MIN

0.10.MIN

H

0.5MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

0.225 MAX

K

15.24

L

13.2

M

0.25

0.600
0.520
+ 0.1
0.010

. 0.05

+ 0.004
0.002

r-- .
. ~IIJ f-K9j
~I··
G
"qHUVjvvunVVITvuvvvutl
-n= I
'--A

0

-lC~

.

-J~

~L-

-B00_lD

Ceramic
ITEM
A

MILLIMETERS
51.5 MAX

INCHES
2.028 MAX

B
C
0

2.54'+ 0.1

0.100 + 0.004

0.50+0.1

0.0197 + 0.004

E

48.26 ± 0.2

1.62

0.064

1.900+ 0.008

F

1.27

0.050

G

3.2MIN

0.128 MIN

H

1.0MIN

0.04 MIN

1
J

4.2 MAX

O.17.MAX

5.2 MAX

O.20SMAX

K

lS.24 ± 0.1

.0.6 ± 0.004

L

+ 0.2
13.5 _ 0.25

+'0.008
0.531 _ 0.010

M

0.30 ± 0.1

0.012 ± 0.004

SP8255/8255A-9-78-GN-CAT

363

NEe

NEe Microcomputers, Inc.

fLPD8257
fLPD8257·5

PROGRAMMABLE DMA CONTROLLER
DESCR IPTION

FEATURES

The IlPD8257 is a programmable four:channel Direct Memory Access (DMA) controller
It is designed to simplify high speed transfers between peripheral devices and memories.
Upon a peripheral request, the 8257 generates a sequential memory address, thus
allowing the peripheral to read or write data directly to or from memory. Peripheral
requests are prioritized within the 8257 so that the system bus may be acquired by the
generation of a single HOLD command to the 8080. DMA cycle counts are maintained
for each of the four channels, and a control signal notifies the peripheral when the
pre programmed member of DMA cycles has occurred. Output control signals are also
provided which allow simplified sectored data transfers and expansion to other 8257
devices for systems requiring more than fourDMA channels.

• Four Channel DMAControlier
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Priority DMA Request Logic
Channel Inhibit Logic
Terminal Count and Modulo 128 Outputs
Automatic Load Mode
Single TTL Clock
Single +5V Supply
Expandable
40 Pin Plastic Dual·ln·Line Package
IIOR
IIOW

MEMR
MEMW
MARK
READY
HlDA
ADDSTB
AEN
HRO

Cs

IlPD

8257/
8257·5

ClK
RESET
DACK2
DACK3
DR03
DR02
DRO,
DROO
GND

A7
A6
A5
A4
TC
A3
A2
A1
Ao

PIN NAMES
D7-DO
ArAo
IIOR
I/OW

Data Bus
Address Bus
1/0 Read
If0 Write

MEMR

Memory Read

MEMW

Memory Write

CLK

Clock Input

vcc

RESET

Reset tnput

Do
D1
D2
D3

READY

Ready

~

DACKO
DACK1
D5
D6
D7

HRQ

Hold Request (to BOSOA)

HLDA

Hold Acknowledge,(from 8000A)

AEN

Address Enable

ADSTB

Address Strobe

TC

Terminal Count

MARK

Modulo 128 Mark

DRQ3-DRClo

DMA Request Input

DACK 3 -DACK O

DMA Acknowledge Out

CS

Chip Select

vCC
GND

+5 Volts
Ground

Rev/1
365

fLPD8257
TheS257 is a programmable, Direct Memory Access (DMA) device and when used with an 8212
1/0 port device, it provides a complete four-channel DMA controller for use in 8080 based systems. Once initialized by an 8080 CPU, the 8257 will block transfer up to 16,364 bytes of data
between memory and a peripheral device without any attention from the CPU, and it will do
this on all 4-DMA channels. After receiving a DMA transfer request from a peripheral, the following sequence of events occur within the 8257.

FUNCTIONAL
DESCRIPTION

o It acquires control of the system bus (placing 8080 in hold mode).
o

Resolves priority conflicts if mUltiple DMA requests are made:

o

A 16 bit memory address word is generated with the aid of an 8212 in the following manner:
The 8257 outputs the least significant eight bits (AO-A7) which go directly onto the
add ress bus.
The 8257 outputs the most significant eight bits (A 8 -A 15 ) onto the data bus where they
are latched into an 8212 a.nd then sent to the high order bits on the address bus.

o

Theappropriate memory and 1/0 readlwrite control signals are generated allowing the
peripheral to receive or deposit a data byte directly from o~ tc the appropriate memory
location.

Block transfer of data (e.g., a sector of data on a floppy disk) either to or from a peripheral may
be accomplished as long as the peripheral maintains its DMA Request (DRO I. The 8257 retains
control of the system bus as .long as DRO n remains higher until the Termin~1 Count (TCI is
reached. When the Terminal Count occurs, TC goes high, informing the CPU that the operation is
complete.
There are three different modes of operation:
o

DMA read; which causes data to be transferred from memory to a peripheral;

•

DMA write; which causes data to be transferreq from a,peripheral to memory; and

o

DMA verify; which does not actually involve the transfer of data.

The DMA read and write modes are the normal operating conditions for the 8257. The DMA
verify mode responds in the same manner as read/write except no' memory or I/O read/write
control sionals are generated, thus preventing the transfer of data. The peripheral gains control
of the system bus and obtains DMA Acknowledgements for its requests, thus allowing it to
access each byte of a data block for check purposes or accumulation of a CRC (Cyclic Redundancy
Code) checkword. In some applications it is necessary for a block of DMA read or write cycles to
be followed by a block of DMA verify cycles to allow the peripheral to verify its newly acquired
data.

BLOCK DIAGRAM

I/OR
I/OW

ClK
RESET

AO
A,
A2
A3

cs
A4
A5
AS
A7
CONTROL
READY

HRO

HLDA
MEMR

MEMW
AEN
ADST8

TC
MARK

366

lOGIC.
AND
MODE
SET
REG

.fLPD8257
AC CHARACTERISTICS
PERIPHERAL (SLAVE) MODE

PARAMETERS
T,"O"Cto70"C;VCC"5V'5%;GNO"OV(j)
BUS

r-------------~--~~--~--Ll-MI-TS------r-~-----,
PARAMETER

SYMBOL

~PD8257

",PD8257-S

I MIN ITVP·I MAX TMINT TVP IMAX I

CO~~~~ONS

0

Adr or CSt Hold from Rdt

, '. Tan<

Data Access from Ad,
DB-Float Delav from

UNIT

300
t50

~di-.

250

Ad Width

200

CL = 100pF

150

Cl- '" 100 pF
CL'" 15pF

20

20

250
WAITE

CSt Setup to Wr l

Tew

300

300

CSt. Hold from Wrf

TW~

20

20

Adr Setup to Wr ~

TAW

20

20

Adr Hold from Wrf

T ••"

200

200

200

200

Data Setup to Wr l

Tnw

Data Hold from Wrt

TWO

WrWldth

TWWS

OTtriER TIMING

Reset Pulse Width

TRSTW

300

Power Supply tlVccl Setup to ReseH

TASTO

SOD

Signal Rise Time

T

300

Signal Fall Time

Reset to First

20

20

20

20

IOW.~,

tCy.

Note: CD-All timing measurements are made at the followmg reference voltages' unles:; speclfleg o~herWlse
at 2.0V, "0" at O.BV, Output "1" at 2.0V, "0" at a.BV.
_ ,~ ."

TIMING WAVEFORMS
PERIPHERAL (SLAVE) MODE

lnpu.t "1"

READ TIMING
CHIP SELECT

AOOAE$BUS~'

______-J~____________-+__~__~Jt'__________~__~

DATA BUS

WRITE TIMING
Tew

Twe

CHIP'SELECT

ADDRESS BUS

X
I---- TAW.-------

).

DATA BUS

I-

TOW--

II

/

-~TWA

K
~TWO-4

,...........

iTcIWR

RES ET TIMING

I' TASTW. f.---.

.1----'-

TRSTS

TWWS

I.------

I

RESE"!

!---TASTD-

Vee

--A

367

jL:P08257
Ta

<=

QOCto

ufe; vee =

AC CHARACTERISTICS
DMA (MASTER) MODE

+5V ± 5%; GNC = OV

"LIMITS
PARAMETER

SYMBOL

.POB257.6

""OB257
MIN
MAX

MIN

Cycle Time (Period)

TCY

0,320

4

0,320

Clock Active (High)

Te

120

,BTCY

BO

TOS

120

TOH

0

DAat Setup to

(J ~

(51, 54)

DRQ.j, Hold from HLDAt

UNIT

MAX

4'

TEST
CONDITIONS

.s

: ,BTCY

ns

120
4

0

TOO,

160

160

ns

CD

HRQt or.j. Delay from 8t (SI, 54)
(measured at 3.3V)

TOO1

250

250

ns

@

HRQt or J, Delay frQm

t' (51, 54)

(J

(measured at 2.DV)

100

100

HLOAt or J.$etup to 9.j. (51,54)

THS

AENt Delayfroml).j. (51)

TAEL

300

300

ns

ns

AENl Delay from 8t (SI)

TAET

200

200

ns

250

ns

CD
CD

ns

@
(?)
(?)
(?)
(?)
@
@
(?)
(?)
@
@

(51)

TSTL

200

200

ns

CD

Adr 5tb.j. Delay from 8 t (52)

TSTT

140

140

ns

CD

Adr 5tb Width (51·52)

TSW

TCy-l00

TCy-l00

ns

Rd.j. or Wr (Ext)J. Delay from Adr
Stb.j. (52)

TASC

70

70

ns

@
@

Rd.j. or Wr (Extl~ Delay from Adr (DB)
I Float) IS2)

'TO'BC

20

Adr (AB) (Active) Delay from AENt (SO
Adr (AB) (Active) Delay from

et (S1)

TAEA

20

20

ns

250

TFAAB

Adr (AB) (Floa.t) Delay from 9t (SO

TAFAB

150

150

ns

Adr (AB) (Stable) Delav from /H (51)

TASM

250

250

ns

Adr (AB) (Stable) Hold from 6t (51)

TAH

TASM-50

TASM-50

Adr fAB) (Valid)·Hold from Rdt (51,51)

TAHR

60

60

Adr (AB) (Valid) Hold from Wrt (51,51)

TAHW

300

300

Adr (Del (Active) Delay from ot (51)

TFAOB

Adr (DB) (Float) Delay from 9t (82)

TAFDB

Adr (DB) Setup to Adr Stb.!. (51·52)

TASS

100

100

Adr (OBI (Valid) Hold from Adr Stbh!{S2)

TAHS

50

50

Adr Stbt Delay from

et

DACKt or ~Oelay from 8l (52,51) and
TC/Mark t Delay from f (53) and
TC/Mark .j. Delay from 8 t (54)

e

Rd~ or Wr (Ext).j. Delay from 8f (52) and
Wr.j. Delav from t (53)

e
e
e

Rdf Delay from ~ (51, 51l and
Wrf Delay from t (54)
Rd or Wr (Active) from

et

(51)

ns
ns

300
TSTT+20

250

TSTT+20

300

ns

170

ns'
ns

ns

@

250

ns

CD@

20

..

TAK'

250

. To.CL

200

200

ns

@@

TOCT

200

200

ns

@(i)
~

"TFAC

300

300

ns

Rd or Wr (Floatl"irom'ef (511

T,.r

150

150

ns

(2)

Rd Width (52·51 or 511

TRWM

2TCY+
Te-5O

2TCY+
T.-50

ns

@
@
@

Wr Width (53·54)

TWWM

TCy-50

TCy-50

ns

Wr (Ext) Width (52·54)

TWWME

2TCy-50

2TCY-50

ns

READY Set Up Time to 8t (53, Swl

TAB

30

30

ns

READY Hold Time from 8t (53, Swl

TRH

20

20

ns

Notes:

CD
(?)
@
@

Load = 1 TTL
Load = 1 TTL + 50 pF
Load = 1 TTL+ IRL = 3,3K). VOH = 3,3V
Tracking Specification

@'''TAK<60n.

@
(i)

368

"TOGL < 50 ns,
"TOCT < 50 ns

TIMING WAVEFORMS
DMA (MASTER) MODE

~CONSECUTIVE CYCLES AND BURST MODE SEQUENCE
"

CLOCK

SI

I

SO

I

r

S1

I

S2

S3

I

S4

I

S1

I

S2

I

S3

f~CONTROL OVERRIDE S~nUENCE

'"

I

S4

SI~I

I

~~~TO~~~ '-'~~

I--

,r-

I--

TOS
DAOo_3

_
"Rn

j-Tonll

THS.:J

HLDA

TDn ....

It

TAEL_

.... i--

j4

-0

ASM

NOT READY SEQUENCE~

I

SO

S1

I

S2

I

S3

I

SIN

I

SW I

S4' I

SI

SI

I SI

\.J\JV\J ~~~

..::l

--I I+- T HS

4-T HS

TAEL--O

:~TAFAB7I

-"'"'-----

~

ADOSTa -----:-

-1--- :H:~~;:H~
. . . r--

~
~ fTSTT

I-

'. . r

TFAC-oj

____

...~~

j---")

TAK

I..

ADDO_7

.z

~

r. . .

T~CL"'"

.-~

• 'TRS-'i.
7(
T AK ",

TC!MARK __ _ _ ______

'" 1r+

T DCT

1+-111:

....

TOCL

_:~

Il..

TRH

~=:~~f~~.~~~T~A~K~
~

----,---<::::=>-- ----- ----------

.

.1
F:----II-...... ----

It--TDBC

~~---4)'-

r-'

--I

---------

TWWM

X,

I

---

J

I+--TAHW

'-~,

[.-TWWME

I

--I r-- TAHR
7

TAFC

DATAO_7
(UPPER ADR)

- - - - - - - - ADR STB

-----

I" '!-TDCT ~TRWM---l

MEMRD/I/O RD ___'---'

--------

,

I~...,I--TASC

HLDA

(LOWER ADA)

------1)-...-

TASS

fo-

.1EMWR!I!O WA __ ~--';

CLOCK

AEN
r-TAEA

-;"'-4)... t-TAFDB

TSTL_

READY _ _ _

SI

TAET

DATAO_7
TFADB ....
(UPPER ADA) ___

___

I

--------- DROo-3

- '---_.I
....

(LOWER ADR) ____

_ _ _~

SI

HRn

~

T FAAB ...

DACKO_3

I

TnH

AEN

ADDO_7

S4

I

~

TRd r--"l.

J J ; - T RS

DACKO-3

---- MEMRD/i70AD
---- MEMWR/iIO"WFi
--- READY

L:::~__________~~------------Lt::::\::::~------~----------------~/L:::::::::::::J\~--------TC/MARK
)~

______ t : : : : \

1:
""0

C

Q)

N

'"
'"

(II

Ol

.....

II

p.PD8257
Internally the 8257 contains six different states (SO, S1, S2, S3, S4 and SW). the
DMA OPERATION
duration of each state is determined by the input clock. In the idle state, (S1). no DMA
operation is being executed. A DMA cycle is started upon receipt of one or more DMA
Requests (DRO n ), then the 8257 enters the SO state. During state SO a Hold Request
(HRO) is sent to the 8080 and the 8257 waits in SO until the 8080 issues a Hold
Acknowledge (H LDA) back. During SO, DMA Requests are sampled and DMA priority
,is resolved (based upon either the fixed or priority scheme). After receipt of HLDA, the
DMA Acknowledge line (DACK n ) with the highest priority is driven low selecting that
particular peripheral for the DMA cycle. The DMA Request line (DRO n ) must remain
high until either a DMA Acknowledge (DACKh) or both DACK n and TC (Terminal
Count) occur, indicating the end of a block or sector transfer (burst model.
The DMA cycle consists of four internal states; SI, S2, S3 and S4. If the access time
of the memory or I/O device is not fast enough to return, a Ready command to the
8257 after it reaches state S3, then a Wait state is initiated (SWl. One or more than
one Wait state occurs until a Ready signal is received, and the 8257 is ililowed to go
into state S4. Either the extended write option or the DMA Verify mode may
eliminate any Wait state.
If the 8257 should lose control of the system bus (i.e., H LOA goes low) then the
current DMA cycle is completed, the device goes into the S1 state, and no more
DMA cycles occur until the bus is reacquired. Ready setup time (tRS). write setup
time (tDW). read data access time (tRD) and HLDA setup time (tOS) should all be
carefully observed during the handshaking mode between the 8257 and the 8080.
During DMA write cycles, the I/O Read (I/O R) output is generated at the beginning
of state S2 and the Memory Write (MEMW) output is generated at the beginning of
S3. During DMA read cycles, the Memory Read (MEMR) output is generated at the
beginning of state S2 and the I/O Write (I/O W) goes low at the beginning of state S3.
No Read or Write control signals are generated during DMA verify cycles.

RESET

HRQ+ HLDA
Notes:

CD
@

370

HRQ is set if ORO n is active.
HRQ is reset if DRQn is not active.

DMA OPERATION
STATE DIAGRAM

fL PD8257
TYPICAL 8257
SYSTEM INTERFACE SCHEMATIC

25
26
27
29
30
31
32
33
34
35
1 "

80BOA

INT~

HOLD

HLDA

r..D~ ''''~
14
OSC
ROVIN

DBIN
WR

5

~

II

19

I

I
I

A 5
'

13
21

"

17
18

1

4

2
13
16
11
9
5
18
20
7

8224
11

_19.
7

~
3
6

SYNC

.,

~

RESET

~
"2

~

8228

-~:~-j

MEMR

MEMW

DO

I
I DATA
IBUS
I

07

N~---<

IIOR
1I0W
tNTA

"
"

"

~-.~.

~~'--'

CONTROL

25
27
23

RUS

BiJSEN

7

o21TTLI
6

ADDRESS
BUS

I

40
37
38
39
36

~

23. READY

~..'2.

STsT'B

I

~
9
17

1'4

REsiN-2...:

I

I

3

~5

..--'-?-

AO

10

HUM HRQ

22

~

#-

~

~

¥.-

f4

~
26

~
37
38
39
40

23
22
21
3
4
1
2

13
12

11

CHIP SELECT

6

READY

19
25

82571
8257"5
RESET
ClK
CS

READY

DROo
OACKO

18
24

ORO,

17
14

DRQ2

DACKl

I

DACK2

16
15

DR03

36
5

TC

DACK3

MARK

EN ADSTB
8

9

Ii3
DS2
DISABhE I/O
ADDR,ESS BUS

11
STB
4

~

~

6
B
10
15

~

~

8212

18
20
22

VCC~
GND

17
19
21

ern
MD

DSI

2

l'
371"

fLPD8257
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. DoC to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts 

::.

Note. VOUT>GND+0.45V

Ta

= 2SoC' VCC =GND =OV
PARAMETER

I nput CapaCitance'
I/O Capacitance

SYMBOL

CAPACITANCE
LIMITS
MIN.

TYP.

MAX..

CIN
CliO

UNIT

TEST CONDITIONS

10

pF

Ic = 1 MHz

20

pF

Unmeasured pins
returned to GND

PACKAGE OUTLINE
ILPD8257C
ILPD8257C-5

ITEM

MILLIMETERS

INCHES

A

51.5 MAX
1.62
2.:;4 ± 0.1

2.02S MAX
0.064
O.10± 0.004

·0.5 ± 0.1
4S.26
1.2 MIN
2.54 MIN
0.5MIN
5.22 MAX
5.72 MAX
15.24
13.2
+0.1
0.25 _ 0.05

0.01 g ± 0.004

B

e
D
E

F

G
·H

.1
J
:K
L
M

I"

1.9
0.047 MIN
0.10MIN
0.019 MIN'
0.206 MAX
0.225 MAX
0.600
0.520
+ 0.004
0.010 _ 0.002

SP8257-1().78-GN-CAT

372

NEe

NEe Microcomputers, Inc.

J'PD8259

J' PD8259·5*
PROGRAMMABLE INTERRUPT CONTROLLER

DESCRIPTION

FEATURES

The NEC'~PD8259 is a programmable interrupt controller directly compatible with the
8080Al8085A/~PD780(Z80TM). 'It can service eight levels of interrupts and contains
on-chip logic to expand interrupt capabilities up to sixty-four levels with the addition
of other ~PD8259's. The user is offered a selection of priority algorithms to tailor the
priority processing to meet his systems requirements. These algorithms can be dynamically modified during operation, expanding the versatility of the microprocessor
system.

• Eight Level Priority Controller
• P~ogrammable Base Vector Address
•
•
•
•
•
•
•

PIN CONFIGURATION

Expandable to 64 Levels
Programmable Interrupt Modes (Algorithms)
Individual Request Mask Capability
Single +5V Supply (No Clocks)
Full Compatibility with 8080A/~PD780(ZBOTM)
~PD825g.5 Compatible with B085A Speeds
Available in 28 Pin Plastic and Ceramic Packages

cs

VCC

WR

AO

AD

iNi'A

01

IR7

Os

IRS

05

IR5

04

IR4

03.
02

IR2

01

IR1

DO

IRO

IR3

CASO

INT

CAS1

SP

GNO

CAS 2

PIN NAMES
07- 0 0
RD
WR

Data Bus (Bi-Directional)

IlilT
INTA
IRO-IR7

Read Input
Write In,put
Command Select Address
Cascade Lines
Slave Program Input
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs

CS

Chip Select

AO
CAS2-CASO
SP

*AII data pertaining t~ the ~PD825g.5 is preliminary.

TM: Z80 is a registened trademark of Zilog, Inc.

313

II

,.,. PD8259
INTERRUPT REQUEST REGISTER (lRR) AND IN-SERVICE REGISTER (lSR)
The interrupt request register and in-service register store the in-coming interrupt
request signals appearing on the I RO-7 lines (refer to functional block diagram). The
inputs requesting service are stored in the IRR while the interrupts actually being
serviced are stored in the ISR.
A positive transition on an IR input sets the corresponding bit in the Interrupt Request
Register, and at the same time the INT output of the J-LPD8259 is set hig,h. The IR input
line must remain high until the first INTA input has been received. Multiple, nonmasked interrupts occurring simultaneously can be stored in the IRR. The incoming
INTA sets the appropriate ISR bit (determined by the programmed interrupt algorithm)
and resets the corresponding IRR bit. The ISR bit stays high-active during the interrupt
service subroutine until it is reset by the programmed End-of-Interrupt (EOI) command.
PRIORITY RESOLVER
The priority resolver decides the priority of the interrupt levels in the IRR. When the
highest priority interrupt is determined it is loaded into the appropriate bit of the
In-Service register by the first INTA pulse.
DATA BUS BUFFER
The 3-state, 8-bit, bi-directional data bus buffer interfaces the J-LPD8259 to the
processor's system bus. It buffers the Control Word and Status Data transfers between
the J-LPD8259 and the processor bus.
READIWRITE LOGIC
The read/write logic accepts processor data and stores it in its Initialization Command
Word (lCW) and Operation Command Word (OCW) registers. It also controls the
transfer of the Status Data to the processor's data bus.
CHIP SELECT (CS)
The J-LPD8259 is enabled when an active-low signal is received at this input. Reading
or writing of the J-LPD8259 is inhibited when it is not selected.
WRITE (WR)
This active-low signal instructs the J-LPD8259 to receive Command Data from the
processor.
READ (RD)
When an active-low signal is received on the RD input, the status of the Interrupt
Request Register, In-Service Register, Interrupt Mask Register or binary code of the
Interrupt Level is placed on the data bus.
INTERRUPT (lNT)
The interrupt output from the J-LPD8259 is directly connected to the processor's INT
input. The voltage levels of this output are compatible with the 8080's input voltage
and timing requirements.
INTERRUPT MASK REGISTER IIMR)
The interrupt mask register stores the bits for the individual interrupt bits to be masked.
The IMR masks the data in the ISR. Lower priority lines are not affected by masking a
higher priority line.

374

BASIC FUNCTIONAL
DESCRIPTION

p.PD8259
FUNCTIONAL DESCRIPTION
(CONT.)

INTERRUPT ACKNOWLEDGE (lNTA)
The interrupt acknowledge signal is usually received from the 8228 (system controller
for the.8080A). The system controller generates three INTA pulses to signal the 8259
to issue a 3-byte CA LL instruction onto the data .bus.
AO
AO is usually connected to the processor's address bus. Together with WR and RD
signals it directs the loading of data into the command register or the reading of
status data. The following table illustrates the basic operations performed. Note that
it is divided into three functions: Input, Output and Bus Disable distinguished by the
RD, WR, and CS inputs.
.
~PD8259 BASIC OPERATION

AO

D4

D3

°
1

RD

WR

CS

PROCESSOR INPUT OPERATION (READ)

0
0

1
1

0
0

IRR, ISR Of IR -+ Data Bus (J)
.IMR -+ Data Bus

1
1
1
1

0
0
0
0

0
0
0
0

PROCESSOR OUTPUT OPERATION (WRITE)

°
0
0
1

0
0
1
X

0
1
X
X

Data
Data
Data
Data

Bus -+ OCW2
Bus -+ 6CW3'
Bus -+ ICW1
Bus -+ OCW1., ICW2, ICW3 (i)

DISAaLE FUNCTION
X
X

Notes:

X
X

X
X

1
X

1
X

0
1

Data Bus -+ 3-State
Data Bus -+ 3-State

CD

The contents of OCW2 written prior to the READ operation governs the
selection of the IRR, ISR or Interrupt Level.
(i) The sequencer logic on the ~PD8259 aligns these commands in the
proper order_

CASCADE BUFFER/COMPARATOR ..(For Use in Multiple ~PD8259 Array.)
The ID's of all ~PD8259's are buffered and compared in the cascade buffer/ comparator. The master ~PD8259 will send the ID of the interrupting slave device along
the CASO, 1,2lines to all slave devices. The casc.ade buffer/comparator compares its
preprogrammed ID to the CASO, 1, 2 lines. The next two iN'TA pulses strobe the preprogrammed, 2 byte CALL routine address onto the data bus from the slave whose ID
matches the code on the CASO, 1, 2 lines.

SLAVE PROGRAM (SP). (For Use in Multiple~PD8259 Array.)
The interrupt capability cim be expanded to 64 levels by cascading multiple ~PD8259's
in a master-plus-slaves array. The master controls the slav~s through the CASO, 1, 2
lines. The SP input to the. device selects the CASo-2 lines as either outputs (SP=l) for
the master or as inputs (SP=O) for the slaves. 'For one deviqe only the SP must be set
toa logic ''1'' since it is functioning as a master.

375

II

f"PD8259
BLOCK DIAGRAM

AO

PROCESSOR PROCESSOR PROCESSOR
ADDRESS
BUS
BUS
BUS

INTERNAL
BUS

SLAVE

PROGRAM

CASCADE
LINES

Operating Temperature .....
. . . . . . . . . . . . . . . . . . . . . . . .. OoC to +70°C
Storage Temperature ..
..... -65°Cto+125°C
Voltage on Any Pin ...... .
-0.5 to +7 Volts
Power Dissipation ....... . ••••...•••••••.••...•••••.•.••.••• 1W

 ± 0.1

0.02 ± 0,004

33.02

G

1.3

1.5

0.059

2.54 MIN.

O.10MIN.

O.SMIN.

0.02 MIN.

5.22 MAX.

0.205 MAX.

5.72 MAX.

0.225 MAX.

0.6

15.24

13.2
M

0.25

0.52

~ ~:~~

0.01 + 0.004
0.002

I'

A

1+-1 ~:~

=f~i.~nlt~n~Jlli~~ET~tif~" ~M II
(Ceramic)
ITEM

MilLIMETERS

0.059 MAX

f-----c'--- ~~::'O_l
D

33.0

e.

0.02 ' 0.004
1299
0.05

3.2MIN.
1.0 MIN

0.126 MIN
0.04 MIN
0.13 MAX

S.2MAX
0.60
13.9

0.30 ' 0.1

0.55
0.012 • 0.004

377

p.PD8259
Ta

= oOe to +70o e; vee = +5V +- 5%· GND = OV

AC CHARACTERISTICS
LIMITS

8259
PARAMETER

SYMBOL

MIN

J

8259·5

MAXi MIN

MAX

UNIT

TEST
CONDITIONS

READ
eS/AO Stable Before RD or INTA

tAR

50

50

ns

eS/AO Stable After RD or INTA

tRA

50

30

ns

R 0 Pulse Width

tRR

420

Data Valid From RDilNTA

tRD

Data Float After RDIINTA

tDF

AO Stable Before WR

tAW

50

50

oS

AO Stable After WR

tWA

20

30

ns

es Stable Before WR

tew

50

es Stable After WR

twe

20

WR Pulse Width

tww

400

300

ns

Data Valid to WR IT. E.I

tow
twe."

300

250

ns

40

30

ns

ns

300
300

20

200

20

ns
200

ns

100

ns

CD
CD

WRITE

Data Valid After WR

ns
ns

OTHER
Width of Interrupt Request Pulse

INT

t After IR

1

Cascade Line Stable After INTA t
Not.:

CD For "PD8259:

CL

= 100

tlW

100

100

liNT

400

350

ns

'Ie

400

400

ns

pi; lor "PD8259-5; C L

= 150

pi

READ
CHIP SELECT

-J,.________

ADDRESSBUS __

~--_+~,~-----

WRITE

CHIP SELECT

DATABUS,________~~~~--~--~---I/OWR

378

TIMING WAVEFORMS

jl.PD8259
TIMING WAVEFORMS
(CaNT.)

READ STATUS/POL.L MODE

. Cs~,-______/

\""'______1

WR---...

OATA':~ wml7lJ/(~JW2W
OTHER

IR

tl~
_ _t_IN_T_ _ _ _ _ _ _-'-I

I NT

,.\~=:::-_---:=

----.-lr-

'::\"'0" '."OAN~
~
~:=LJ;;
Note: IR must stay "high" at least until the leading edge of 1st

t\\\\g

iiiiTA.

INPUT WAVEFORMS FOR AC TESTS

"j(..

0.45

.

2.2

0.8

.JL

.2.2

>='O"T<
..

0.8

INITIALIZATION SEQUENCE
WR

STORE BYTE 1

STORE BYTE 2

STORE BYTE 3

379.

fLPD8259
The IlPD8259 derives iti'versatil ity from its programmable interrupt modes and its
ability to jump to aiw memory address through programmable CALL instructions. The
following sequence demonstrates how the IlPD8259 interacts with the processor.

DETAILED OPERATIONAL
DESCRIPTION

1. An interrupt or interrupts appearing on I R0-7 sets the corresponding I R bit(s)
high. This in turn sets the corresponding IR R bit(s) high.
2. Once the IRR bills) has been set~ the MPD8259 will resolve the priorities
according to the preprogrammed-interru'pt algorithm. It then issues an INT signal
to the processo~.
3. The processor group issues an INTA to the MPD8259 when it receives the INT.
4. The INTA input to the MPD8259 from the processor group sets the highest
priority ISR bit and resets the corresponding IRR bit. The INTA also signals the
MPD8259 to issue an 8-bit CALL instruction op-code (11001101) onto its Data
bus lines.
5. The CALL instruction code instructs the processor group'to issue two more
INTA pulses to the MPD8259.
6. The two INTA pulses signal.thellPD8259 to place its preprogrammed interrupt
vector address onto the Data bus. The first iNTA releases the low·order 8·bits
of the address and the second INTA re,leases the high-order 8-bits.
7. The MPD8259's CALL instruction sequence is complete. A preprogrammed EOI
(End-of-Interrupt) command is issued to the MPD8259 at the end of an interrupt
service routine to reset the ISR bit and allow the MPD8259 to service the next
interrupt.
Two types of command words are required from the processor to fully define the
operating modes of the MPD8259.
1. Initialization Command Words (lCWs)
Each MPD8259 in the interrupt array must be initialized prior to nor~operation.
The initialization is performed by a 2 or 3-byte sequence clocked by WR pulses.
Figure 1 shows this sequence. (Refer to Figure 2 for bit definitions.)

ICWl

ICW2

ICW3

READY TO ACCEPT REQUESTS
IN FULLY NESTED MODE
INITIALIZATION SEQUENCE - FIGURE 1.

380

PROGRAMMING THE
IlPD8259

p..PD8259
PROGRAMMING THE
IlPD8259 (CONT.)

2. Operation Command Words (OCWs)
The operation command words are used to program the various interrupt
algorithms listed below:
• Fully Nested Mode
• Rotating Priority Mode
• Special Mask Mode
• Polled Mode
Once the IlPD8259 has been initialized, OCWs can be written at any time.

INITIALIZATION
COMMAND WORDS
1 and 2 (lCW1 and ICW2)

When AO = 0 and D4 = 1 in a command to the ;UPD8259,together with CS = 0, it is
recognized as Initialization Command Word 1. This is the start of the initialization
sequence and causes the following to occur:
• The Interrupt Request edge-sense circuitry is reset so that an input must make a
low-to-high transition to generate its interrupt.
• The initialization sequence clears Interrupt Mask Register to all unmasked and
resets the Special Mask Mode and Status Read Flip-Flops.
•

I R7 input is set to priority 7.

There are eight equally-spaced base vector addresses in memory for the eight interrupt
inputs. The interval between the base vectoT addresses can be programmed to be either
four or eight requiring 32 or 64 bytes in memory, respectively. The following shows
how the address format is mapped onto the Data bus.
D7

D6

D5

D4

D3

D2

Dl

DO

I A71 A61 A51 A41 A31 A21 All AO]

~--------AUTOMATICALLY INSERTED

DEFINED BY

D5'7 OF ICWI

BY IlPDB25.~

DEF INED BY ICW2

The IlPD8259 automatically defines AO_4with a separate address for each interrupt
input. The base vector addresses A 15-6 are programmed by ICW1 and ICW2. A5 is
either defined by the IlPD8259 if the address interval is eight or must be user-defined if
the interval is 4. The 8-byte CALL interval is consistent with 8080A processor R ESTAR'
instruction software. The 4-byte CALL interval can be used for a compact jump table.
Refer to Figure 4 for a table of address formats.
The following is an example of an interrupt acknowledge sequence. The IlPD8259 has
been programmed for a CALL address (base vector address) interval of eight (F = 0) and
there is an interrupt appearing on IR4. The 3-bytesequence is strobed out to the Data
bus by three INTA pulses.

.CALL CODE

2NDINTA

3RDINTA

LI_A~7LI_A~6~1__L-~__L-~_0~__~

LOWER ROUT·INE
ADDRESS (FROM
FIGO~E 4)

HIGHER ROUTINE
ADDRESS

3.81

,.,. P08259
It is only necessary to program ICW3 when there afe multiple IlPD8259s in the", ,
interrupt array, i.e., S = O. There are two types of ICW3s. The first is for programming
the master IlPD8259. The second is for 'the slaves.

INITIALIZATION COMMAND

WORD 3 (iCW3) 6
DB7

BD
CS

VSS

AO

DBa
DB1
DB2

TM:

DBO_7

'---

Z80 is a registered trademark of Zilog.

389

fLPD8279·S
The,pPD8279-5 has two basic functions: 1) to control displays to output and 2) to
control a keyboard for input. Its specific purpose is to unburden the host processor
from monitoring keys and refreshing displays. The J.lPD8279-5 is designed to directly
interface the microprocessor bus. The microprocessor must program the operating
mode to the J.lPD8279-5,these modes are as fdllows:

FUNCTIONAL
DESCRIPTION

Output Modes
• . 8 or 16 Character Display
• Right or Left Entry
Input Modes
•

Scanned Keyboard with Encoded 8 x 8 x 4 Key Format or Decoded 4 x 8 x 8
Scan Lines.
• Scanned Sensor Matrix with' Encoded 8 x 8 or Decoded 4 x 8 Scan Lines.
• Strobed Input.

BLOCK DIAGRAM
elK RESET

OBO·7

IRQ

CNTLlSTB

. . . . 0° C to +70° C
. -65°C to +125°C
-0.5 to +7 VoltsCD
-0.5 to +7 VoltsCD
-0.5 to +7 VoltsCD
. . . . . . . . . . . . . 1W

Operating Temperature
Storage Temperature, .
All Output Voltages
All Input Voltages ..... .
Supply Voltages.
Power Dissipation ..... .
Note:

W

120

ns

Clock Period

tCY

320

ns

GENERAL TIMING
Keyboard Scan Time;
Keyboard Debounce Time;
Key Scan Time;
Display Scan Time;

392

5.1 ms
10.3 ms
80Ms
10.3 ms

CAPACITANCE

Digit-on Time;
Blanking Time;
Internal Clock Cycle;

480Ms
160Ms
10 MS

J-L PD8279·5
TIMING WAVEFORMS

INPUT

FOR AC TESTS

24

045

READ
- ......,r-------------"1l,,---------{SYSTEM'S
AO, CS

AOOR ES& BUS)

(READ CONTROL I

DATABUS---------+---------r----~------(OUTPUTI _ _ _ _ _ _ _ _ _~-~-----~--------------

WRITE
AO.

Cs

_..J'"..________________

~I\.-------_---

we

{SYSTeM'S
i\LJOHESS BUS)

(wr-1ITE CONTROL)

DATABus----------""\I~-------~~r---~-------------(INPUT)

UATA

MAYCII!\NGr-

CLOCK INPUT

393

p.PD8279·S
The following is a description of each section of the t/PD8279-5. See the block
)
diagram for functional reference.
I/O Control and Data Buffers
Communication to and from the t/PD8279-5 is performed by selecting CS, AO, Ri5 and
WR. The type of information written or read by the processor is selected by AO. A
logic 0 states that information is data while a 1 selects command or status. AD and WR
select the direction by which the transfer occurs through the Data Buffers. When the
chip is deselected (CS = 1) the bi-directional Data Buffers are in a high impedance state
thus enabling the t/PD8279-5 to be tied directly to the processor data bus.
Timing Registers and Timing Control
The Timing Registers store the display and keyboard modes and other conditions programmed by the processor. The timing control contains the timing counter chain. One
counter is a divide by N scaler which may be programmed to match the processor
cycle time. The scale; must take a value between 2 and 31 in binary. A value which
scales the internal frequency to 100 KHz gives a 5.1 ms scan time and 10.3 ms switch
debounce. The other counters divide down to make key, row matrix and display scans.
Scan Counter
The scan c_ounter can operate in either the encoded or decoded mode. In the encoded
mode, the counter provides a count which must be decoded to provide the scan Ii nes.
In the decoded mode, the counter provides a lout of 4 decoded scan. In the encoded
mode the scan lines are active high and in the decoded mode they are active low.
Return Buffers, Keyboard Debol!nce and Control
The eight return lines are buffered and latched by the return buffers. In the keyboard
mode these lines are scanned sampling for key closures in each row. If the debounce
circuit senses a closure, about 10 ms are timed out and a check is performed again. If
the switch is still pressed, the address of the switch matrix plus the status of shift and
control are written into the FIFO. In the scanned sensor mode, the contents of
return lines are sent directly to the sensor RAM (FIFO) each key scan. In the strobed
mode, the transfer takes place on the rising edge of CNTL/STB.
FIFO/Sensor RAM and Status
This section is a dual purpose 8 x 8 RAM. In strobe or keyboard mode it is a
FIFO. Each entry is pushed into the FIFO and read in order. Status keeps track of the
number of entries in the FIFO. Too many reads or writes to the F!FO will be treated
as an error condition. The status logic generates an IRO whenever the FIFO has an
entry. In the sensor mode the memory is a sensor RAM which detects changes in the
status of a sensor. If a change occurs, the IROis generated until the change is
acknowledged.
.
Display Address Registers and Display RAM
The Display Address Register contains the address of the word being read or written
by the processor, as well as the word being displayed. This address may be pro'
grammed to auto-increment after each read or write. The display RAM may pe read
by the processor any time after the mode and address is set. Data entry to the display
RAM may be set to either right or left entry.

394

OPERATIONAL
DESCRIPTION

/LPD8279·5
COMMAND OPE RATION

The commands programmable to the pPD8279-5 via the data bus with CS active (0)
and AO high are as follows:

Keyboard/Display Mode Set

[OJ 0101 DI D 1K 1K 1K 1
MSB

lSB

Display Mode:
DO

o
o

8-8-bit character display - left entry,

0" ,

1G)

16-8 bit character display - left entry

o

8-8 bit character display - Right entry
16-8 bit character display - Right entry

Note: G) Power on default condition
'Keyboard Mode:

KKK

0 0
0 0'
0

0 1
0

,Encoded Scan - 2 Key lockout

0

'Decoded Scan - 2 Key lockout

0

Encoded S~an - N Key Roi'lover'

ci

Encoded Scan-Sensor Matrix

0

Strobed Input, Encoded Display Scan

Decoded Scan - N Key Rollover

0

Decoded Scan-Sensor Matrix
Strobed Input, Deqld~d bisplay Scan

Program Clock
Where PPPPP is the presealer value between 2 and 31 this presealer divides the external
clock by PPPPP 10 develop its internal frequency, After reset, a default value of 31 is
.
."
('.
generated,

Read FIFO/Sensor RAM

101110lA11xlAlAIAI AO,=O
AI is the auto-increment flag, AAA is the row to'be read by the processor, The read
command is accomplished with (CS, RD ' NiJ by the proceSSOr, H, AI,is 1" thp row
select counter will be increi11ented after each read, Note that auto-i~crementi,ng has
no effect on the display, "
,
,':,',,""
,

, Read Di,splayBAM

II

Where AI is'the auto-incr'erTient fhig arid' AAAA is the character which the'processor
is about to read,

Write Display RAM

where AAAA is the character the process",r)s

a~~u.t, to, write,

Display Write Inhibit Blanking

[j~J'1

xl ~ltltltJ

Where IWA and IWB are Inhibit Writing nibble A andB respectively, a,nd S'lA, BlB
are blanking_ When using the display as a dual 4-bit, it is necessary to mask one of the
4·bit halves,to eliminate interaction betweert the'two,halves, Thi~'is,accornplished with
the IW flags, The Bl flags,~Uow the programmer to blank either'balf of the display
independently, To blank a display formatted as'a single 8-bit, it is necessary to set
both BlA and B'lB, Default after a reset is all zeros, All signals are active high (1),

395

p.PD8279·S
Cle~r

0 I CD I CD I CD I CF
CD

CD

CD

0

X
0

X

X

All zeros
AS.= 2016
All ones
Disabl~ clear display

1

0

COMMAND OPERATION
(CONT.)

CA

This command is used to clear the display RAM, the FIFO, or both. The CD options
allow the user the ability to clear the displ~y RAM to either all zeros or all ones.
CF clears the FI FO.
CA clears all.
Clearing t~e display takes one complete display scan. Durfng this time the professor
can't write to the display RAM.
CF will set the FIFO empty flag and reset I RO. The sensor matrix mode RAM pointer
will then be set to row O.
CA is equivalent to CF and CD. The display is cleared using the display clear code
specified and resets the internal timing logic to. synchronize it.

End Interrupt/Error MO~!I Set

[DJT1[E t x'[x I X I >U
In the sensor matrix mode, this instruction clears IRO and allows writing into RAM.
In N key rollover, setting the E bit to 1 allows for operating in the special Error mode.
See Description of FIFO status.

FIFO Status
1 DU 1 S/E
Where: DU
S/E

0 1 U 1 FIN I N I. N

Display Unavailable because a clear display
progress.

qr clear all comm~nd

is in

'

Sensor Error flag due to multiple closure of switch matrix.

o

FIFO Overrun since an attemptwas made to push too many
characters into the FIFO.

U

FIFO Underrun. An indication that the processor tried to read an
empty FIFO.

F
NNN

FIFO Full Flag.·
The Number of characters presently in the FIFO.

The FIFO Status is Read with AO high and CS, RD active low.
The Display not available is an indication that the CD or CA command has 'lot
completed its clearing. The S/E flags are used to show an error in multiple closures has
are
occurred. The 0 or U, overrun. or underrun, flags occur when too many characters
,
written into the FIFO or the processor tries to read an empty FIFO. F is an indication
that the FIFO is full and NNN is the number of characters in the FIFO. i!

Data Read
Data can be read during AO = 0 and when CS, RD are active low. The source of the
data is determined by the Read Display or Read FIFO commands.

Data Write
Data is written to the chip when AO, CS, and WR are active low. Data will be written
into the display RAM with its address selected by the latest Read or Write Display
command.

3~6

p.PD8279·S
Data Format

COMMAND OPERATION
(CONT.)

LIC_N_T_L~I~S_H~_____S_C_A_N____

- L_____
R_E_T___

~

In the Scanned Key mode, the characters in the F tFO correspond to the above format
where CNTL and SH are the most significant bits and the SCAN and return lines are
the scan and column counters.

I

RL7

I

RL6

I

I

RL5

RL4

I

RL3

I

RL2

I

RLl

I

RLa

I

In the Sensor Matrix mode, the data corresponds directly to the row of the sensor
RAM being scanned. Shift and control (SH, CNTL) are not used in this mode.

Control Address Summary
DATA
MSB
a
a
a

a
a

LSB

Ia
Ia

I0
P I P
Al I X
Al
IA
Al I A

K

K

K

Keyboard Display Mode Set

P

P

P

Load Program Clock

A

A

A

Read FIFO/Sensor RAM

A

A

A

Read Display RAM

A

A

A

Write Display RAM

IW
A

IW
B

B;

I

BL
B

Display Write Inhibit/Blanking

ICD I CD

CD

CF

I CA I

0

a

I

a

I
I Ia
a

I

I

a

Ix I

a
a

lou I

S/E

0

Clear

E

X

X

X

X

End Interrupt/Error Mode Set

U

F

N

N

N

FIFO Status

PACKAGE OUTLINE
J,LPD8279C-5

~~mlif' !~~~lJ

A

' I'

-j

c r-

.0'-

Q

- E-

: jet-

M

00

_

150

>-

I

-j

(Plastic)
ITEM

MILLIMETERS

A

51.5 MAX

INCHES
2.028 MAX

1.62

0.064

C

2.54±O.1

O.10±O.OO4

0

0.5 ± 0.1

0.019 ± 0.004

B

E
F

48.26

1.9

1.2MIN

0.047 MIN

G

2.54 MIN

O.10MIN

H

0.5MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

0.225 MAX

K

15.24

L

13.2

M

0.25

0.600
0.520

+ 0.1
0.05

0.010

+ 0.004
0.002

SP827g.g. 78-G N-C AT

397

NEe
NEe Microcomputers, Inc.

JLPD8355
p.PD8755A*

16,384 BIT ROM WITH ItO PORTS
16,384 BIT EPROM WITH 1/0 PORTS*

DESCR IPTION

F EA TU R ES

The /lPD8355 and the /lPD8755A are /lPD8085A Family components with the
/lPD8355 containing 2048 X 8 bits of mask ROM and the JlPD8755A containing
2048 X 8 bits of mask EPROM for program development. Both components also contain two general purpose 8-bit I/O ports. They are housed in 40 pin packages. are
designed to directly interface to the /lPD8085A and are pin for pin compatible to each
other.

• 2048 X 8 Bits Mask ROM (/lPD8355)
•
•
•
•
•
•
•
•

PIN CONFIGURATIONS

2048 X 8 Bits. Mask EPROM (/lPD8755A)
2 Programmable I/O Ports
Single Power Supplies: +5V
Directly Interfaces to the /lPD8085A
Pin for Pin Compatible
JlPD8755A: UV Eraseable and Electrically Programmable
JlPD8355 available in Plastic Package
JlPD8755A Available in Ceramic Package

CE
CE
ClK
RESET
NC
READY
IO/iiii
lOR
RD
lOW
ALE
ADO
AD,
AD2
AD3
AD4
AD5
AD6
AD7
VSS

IlPD
8355

VCC
PB7
PB6
PB5
PB4
PB3
PB2
PB,
PBo
PA7
PA6
PA5
PA4
PA3
PA2
PA,
PAO
A10
Ag
AS

CE
CE
ClK
RESET
VDD
READY
IOiM
lOR
RD
lOW
ALE
ADO
AD,
AD2
AD3
AD4
AD5
AD6
AD7
VSS

vcc

JlPD
8755A

PB7
PB6
PB5
PB4
PB3
PB2
PB,
PBo
PA7
PA6
PA5
PA4
PA3
PA2
PA,
PAO
A10
Ag
AS

NC: Not Connected

* All data pertaining to the JlPD8755A is preliminary.

399

I

f'PD8355/8755A

The pPD8355 and pPD8755A contain 16,384 bits of mask ROM and EPROM
respectively, organized as 2048 X 8. The 2048 word memory location may be
selected anywhere within the 64K memory space by using the upper 5-bits of
address from the pPD8085A as a chip select.

FUNCTIONAL DESCRIPTION

The two general purpose I/O ports may be programmed input or output at any
time. Upon power up, they will be reset to the input mode.
VDDG)

vcc (+5V)

BLOCK DIAGRAM

8

AD7-ADO

-+-

AlO - A8

D

READY
CE
CE
ALE
RD

[J

lOW
lOR
ClK

101M

PA7·PAO

8

8

RESET
VSS (OV)
Note: G) VDD applies to !,PD8755A only.

Operating Temperature (pPD8355) . . . . . . . . . . . . . . . . . . . . . . .. OOC to +70°C
(pPD8755A) . . . . . . . . . . . . . . . . . . . . -10° C to +70° C
Storage Temperature (Ceramic Package). . . . . . . . . . . . . . . . .. -65°C to +150°C
(Plastic Package). . . . . . . . . . . . . . . . . .. -40°C to +125°C
Voltage on Any Pin (pPD8355). . . . . . . . . . . . . . . . . . . . .. -0.3 to +7 Volts CD
(pPD8755A) . . . . . . . . . . . . . . . . . . .. -0.5 to +7 Volts Ao-PA7

Port A

General Purpose I/O Port

32-39

PBO-PB7

Port B

General Purpose I/O Port

VCC

5V Input

Power Supply

40 .
Notes:

CD MPD8355

~ MPD8755A

I/O PORTS

I/O Port activity is controlled by Performing I/O reads and writes to selected I/O port
mlnibers. Any activity to and from theMPD8355 requires the chip enables to be active.
This can be accomplished with no el(ternal decoding for multiple devices by utilizing
the upper address lines for chip selects. CD Port activity is controlled by the following
I/O addresses:
AD1

ADO

0

0

PQ~T SELECTED

A

FUNCTION
Read or Write PA

0

1

B

Read or Write PB

1

0

A

Write PA Data Direction

1

1

B

Write PB Data Direction

Since the data direction registers for PA and P~ are each 8-bits, any pin on PA or PB
may be programmed as input or output (0 = in, 1 =out).
Note:

cD During ALE time the data/address lines are duplicated on A15-A8.
401

I

JLP D8355/8755A
ACCHARACTER ISTICS

LIMITS
SYMBOL

PARAMeTER
Clock Cycle Time

tCYC

M'N

TVP

MAX

UNIT

320

80
T, "
I--'-'-'---+-=-+_-+-'-_+--'''--I

!-=C"'LK.:.:Pc::":::''':..:W.::;d:.:''''----'--_ _ _ _ _
eLK Pulse Width

T2

elK Aise and Fall Time

If,lr

'AL

50

'LA

80

Latch to READ/WA ITE Control
Valid Data Out Delav from READ Control

" C

CLOAD. ~ H~O pF

'20

Address to Latch Set Up Time
Address Hpld Time After latch

TEST
CONDITIONS

30

100

~

'RD

'AD
~:.:.::t::.,~::,::,.-":-:=:lbC-:':::;:':j:t.,.~',,":cO:..:".:.:'V:c'"lid'-_ _ j--='-+=-+_-+CC:':'-+-'----I
,150 pF Loa~ ..
400

'LL

100

Data Bus Float After AEAD

tRDF

READ/WR,ITE Control, to Latch Enable

'CL

20

'00

READ/WRITE Control Width

'CC

250

Data In to WRITE Set Up Time

'OW

'50

Data In Hold Time After WAITE

'WD

WRITE to Port Output

'WP

'0
400

POft Input Set Up Time'

'PR

50

Port Input Hold Time

'RP

50

READY HOlQ TIME

tRYH

ADDRESS (CEl to READY

tARY

Recovery Time Between Controls

'RV

DatB Out Delay from REAO Control

tRCE

Notes:

~
160
300
10

ill J,!PD8355
® /.4PD8755A

TIMING WAVEFORMS.

ROM READ, I/O REAPANDWRITE (j)

"-\\~_ _. . J / " " _ - - - ' r = T l = f T 2 L

elK \teY/"'_ _

A6.'O-""'-r------------------------""'\
IO/M __-'~::::::::~~::::::::~~--~-------------------..J

ADO-7

DATA

-,"]t--,..----~

tee
PROM READ, I/O READ AND WRITE

AS",O

ADDRESS

=:I::~~~~r~===:-r_-'1-__
>r ----<

ADO-7 ___-'l'-_ _----'l.

".,.D_A_T_A_ _ _

ALE

eE

Notes:

402

<2>

tee
CD fJ PD8355
@ fJ PD8755A
® CE must remain Ipw for the entire cycle

ADDRESS )-

JLPD8355/8755A
CLOCK

TIMING WAVEFo.RMS
(CONT.)

WAIT STATE TIMING (READY =0)

INPUT 1\40DE:

1/0 PORT

D~~A-------"V

_______ ..A_ _ _ _ _ __

OUTPUT MODE:

.

\ i
twp=.j

I~

1--/

PORT ------------~

I

GLITCH FREE
OUTPUT
,'

OUTPUT

------------

EPROM PROGRAMMING, Erasure of the IlPD8755A occurs when expos!ld to ultraviolet light sources of waveIlPD8755A lengths less than 4000 A. It is recommended, if the device is exposed to room
fluorescent lighting or direct sunlight, that opaque labels be placed over the window to
prevent exposure. To erase, expose the device to ultraviolet light at 2537 A at a
minimum of 15 W-sec/cm 2 (intensity X expose time). After erasure,. all bits are in the
logic 1 state. Logic O's must be selectively programmed into·the desired locations. It
is recommended that NEe's prom programmer be used for this application. '
4Q3

p;PD8355/8755A

. ;====---A

Jr_~I_ PPDB3~5~
Hi~l~~J
~IH-rHliml1-rl-i:t:-r~
:l-rlilili--lil---n-~---~'f~l
PACKAG OUTLINE
r--- _________
•

~

E-

'

~~

,- G

0° - 15°

D

E
F
G

\--

2.028 MAX
0.064
0.10± 0.004
0.019 ± 0.004
1.9
0.047 MIN
0.10MIN
0.019 MIN
0.206 MAX
0.225 MAX
0.600
0.520

8
C

pPDB756AD

M

_____ __----I
D
I

2.54.± 0.1
0.5 ± 0.1
48.26
1.2 MIN
2.54 MIN
0.5MIN
5.22 MAX
5.72 MAX
15.24
13.2
0.25 + 0.1
- 0.05

I

A

ceramic

-

Q TEM
L-A
_B

C
_D

~E

F

l

tL

MILLIMETERS

0.064

3.2MIN
~OMIN

I
J

4.2 MAX
5.2 MAX
15.24 ± 0.1

K

L

1-

13.5 + 0.2
- 0.25
0.30 + 0.1

--i

~
0.0197 + 0.004
1.900+ O.OOB
0.050
-

~.27

H

-,

2.028 MAX-

51.5 MAX
1.62
+==2.54 ± 0.1
0.50 + 0.1
48.26 + 0.2

G

M

INCHES

O~

0.04 MIN

-

O.~

0.205 MAX-

I
T

0.6±~

0.531 + o.ooa

~

0.012 ± 0.004

---'

SP8355/8755A-8-78-GN -CAT

404

NEe Microcomputers, Inc.

NEe

TK·80A

DESCRIPTION

The TK-80A is a single-board computer based on NEC Microcomputers' industry
standard )1PD8080AF. It facilitates understanding and developing 8080A systems and
assembly language programs,and consists of the following blocks:
•

)1PD8080A Microprocessor Chip Set

•

Monitor and User ROM

•

RAM

•

DMA Display

•

Programmable I/O

•

25 Key Keyboard

•

Tape Cassette Interface

405

TK·80A
The j.lPDBOBOAF Processor,j.lPBB224 Clock Generator and Driver and the j.lPBB22B
System Controller and Bus Driver comprise the BOBOA chip set. The BOBOA executes
programs stored in memory and supports a large instruction set detailed in the j.lCOM·8
Software Manual. The 8224, coupled with an lB.OOO MHz crystal, provides the 2.0
MHz, non-overlapping two-phase MOS clocks required by the 8080A. The 8224 also
provides latches for synchronizing the RESET IN and READY IN signals. The 8228
provides bi-directional data bus drivers which buffer the B080A data bus for on-board
and external use. The 822B also provides a Status Latch and gating array which provide
active low memory and I/O read/write strobes, an Interrupt Acknowledge Strobe, and a
data control bus enable input. The 8080A address bus is buffered by 3-state low power
Schottky drivers with their enable pins tied to the bus enable input of the 8228, thus
allowing the address, data and control busses to be asynchronously disabled by a single
control line for user DMA.
The TK-80A resident monitor is provided in NEC Microcomputers' 1 K x 8 electrically
erasable read-only memory, the j.lPD458. Since the 2708 and 458 are pin compatible
when installed, (pin 1 to pin 1 J. either 2708's or 458's may ue used to expand the
ROM/PROM space. Through proper manipulation of on-board jumpers, any of the
following devices may be used:
PIN

ORGANIZATION

TYPE

+12, +5

458

1K x 8

EEPROM

lK x 8

EPROM

+12, +5,-5

2308

lK x 8

Mask ROM

+12,+5,-5

2758

lK x 8

EPROM

+5

2716

2K x 8

EPROM

+5

231.6E

2K x 8

Mask ROM

+5

2732(6)

4K x 8

EPROM

+5

4K x 8

Mask ROM

+5

.,.

MONITOR AND USER
ROM/PROM

SUPPLI ES (j)

2708

2332 (6)

I-IPD8080A
MICROPROCESSOR
CHIP SET

Notes: (j) Read Mode.

(6) OOOOthrough OFFF only. (All addresses in hexadecimal notation.)
The standard configuration TK-80A haslK bytes of socketed RAM (2 pieces
RAM
"PD2114LC) located at 8000 through 83FF. Up to 3K additional RAM may be
instailed in the sockets dedicated to locations 8400 through 8FFF. All memory and
port address decoding is completely implemented to ensure that all possible expansion
options are available to the user. The Protect/Enable switch provides for the connection
of battery backup to all on-board RAM. If data must be retained for long periods of
time with power off, the use of the NEC's 2114-compatible "PD444 CMOS RAM is
recommended.
In order to improve throughput and demonstrate Direct Memory Access through
"Hidden Refresh", the TK"80A uses an 8-byte block of RAM to control the 8-digit
LED display directly. Data bytes, whose bits correspond one-for-one to display segments, are stored in display RAM, where they are directly accessed for display.

DMA DISPLAY

The "PD8255 Programmable Peripheral Interface provides the TK·80A with 24 I/O
lines. Because the 8255 is a very flexible I/O device, the TK-80A can support considerable user I/O in addition to the Keyboard, Cassette and Display. The B255 is located at
Port Addresses OF8 through OFB, thus leaving both conventional and bit select
decoding methods open for user expansion.

PROG RAMMABLE I/O

406

TK·80A
TAPE CASSETTE
INTERFACE

The on-board "Kansas City" compatible interface provides means forreliable,
inexpensive mass storage using an audio cassette tape recorder. The data transfer rate is
software selectable at 300 or 1200 baud. Jumpers in the interface circuitry allow the
user to modify record and play back signal polarities to accommodate most tape
recorders.

EXPANSION
CONNECTORS

A 50 pin header, J1, for use with flat cable, allows expansion of the TK-80A for use
with the EB-80A Expansion Board or other user circ(Jitry. Buffered Address, Data and
Control lines, as well as most commonly used interface signals, are available on J1_
J2, a 40 pin header, provides access to the on-board 8255. The 8255 input/output lines
can be buffered and/or terminated with optional circuitry installed in sockets provided.
Additional interface signals and a 2400 or 1200 Hz interrupt clock are also available
on J2_

BLOCK DIAGRAM

<

Oc::JO
'i5OciO'

USER I/O

<

~J

USERI/O

__

t

--

-I

80'G'T
DISPLAY

k-;tIi

L..-_ _-,,;--'

CASSETTE
INTERFACE

.------l
r-----l

I

,-l-- - - - , I I

r'---"---"--,

I I

j.lPD8255

I1PD8080AF
MICROPROCESSOR
CHIP SET

PER!PHERAL
INTERFACE

I

I I_J

IJ -

J

DISPLAY
OMA
LOGIC

,----J---U,,----,-,---,-,-----,,--J~D

I

ADDRESS BUS

I

DATA BUS

c---'-------'

I

i
'---_ _->UL....--_ _~ L-_ _ _-----'---'I '---_ _ _ _\.JL.~_____.,

CONTROL BUS

}

u

HARDWARE
SPECIFICATIONS

I

• Word Size
-

Instruction: 1,2, or 3 8-Bit Bytes
8 Bits

Data~

•

System Clock: 2 MHz± 0.1%

•

Cycle Time
-

•

Basic Instruction Cycle: 2.0/ls CD
Maximum Instruction Cycle: 9.01ls

Processor Ch ip Set
Processor: IlPD8080AF
Clock: /lPB8224
Bus Control: /lP B8228

Note:

CD

Basic Instruction Cycle is defined to be the shortest instruction, i.e., four
clock cycles.

407

JK·80A
MEMORY ADDRESSES
On-Board ROM/PROM
On-Board RAM

HARDWARE
SPECIFICATIONS (CONT_)

0000 - 03FF (Monitor)
8000 - 83FF

MEMORY CAPACITY
4k
8K
4K
Up

On-Board ROM/PROM:
On-Board RAM:
Off-Board Expansion:

Bytes using 1 K Memories
Bytes using 2K Memories
Bytes in 1 K Increments
to 64K Bytes Total

I/O ADDRESSES
On-Board Programmable I/O Controller: pPD8255

A

Port
Address

B
F9

C
FA

Control
FB

I/O CAPACITY
•

Parallel: 24 Lines
Expansion to a total of 48 I/O lines (34 uncommitted) is possible using the
optional EB-80A Expansion Board and to 256 Ports using customer supplied
circuitry_

•

Compatible with: 7400,7403,7408, 7409, 7426,7432, 7437 and 7438.

•

Cassette:
"Kansas City" Compatible
8-Bit Characters
One Start Bit and Two Stop Bits
300 or 1200 Baud (Software Select)
Sinusoidal FSK Recording
Logic "0" - 1200 Hz
Logic "1" - 2400 Hz
Output 30 mV or 3V Peak-to-Peak
Input - 0_3 - 10V Peak-to-Peak, 2V Peak-to-Peak Nominal

DISPLAY
•

Number:

8 Digits

•

Size:

0_5 in (1_27 em)

•

Type:

LED Seven Segment with Right-Hand Decimal

KEYBOARD
•

Keyswitches: Gold Contact Crossbar Type, 0_150 in travel

•

Key tops: Double-Shot Removable

INTERRUPTS
On-board logic may be used to auto-vector the processor to 0038 using RESTART 7_
External user logic may be used to supply 3-byte interrupts that vector to any memory
location_
INTERFACES
•

Fully TTL Compatible

•

Address and Data Bus

•

Control Bus

•

Parallel I/O

•

Interrupt Request

•

Interrupt Clock Available: 2400 Hz - TTL Compatible

408

TK·80A
HARDWARE
SPECIFICATIONS (CaNT.)

CONNECTORS
•

Power:

1 piece 4 conductor nylon crimp type, 0.156 centers Molex 09-50-7041 or
equivalent (supplied)
4 pieces terminals, crimp,loose Molex 08-50-0106 or equivalent (supplied)
50 conductor flat cable connector
3M 3425-0000 or equivalent

•

Bus:

•

Parallel I/O:

•

Cassette: In and Out:

40 conductor flat cable connector
3M 3417-0000 or equivalent
Standard 1/8" miniature phone plug
Switchcraft "Tini-Plug" 750 or equivalent

PHYSICAL CHARACTERISTICS
13.00 in (33.02 cm)

•

Width:

•

Depth:

1.40 in (3.56 cm)

•

Height:

7.50 in (19.05 cm)

•

Weight:

18 oz (510.3 gm)

ELECTRICAL CHARACTERISTICS
DC POWER

CD

VCC= +5V ± 5%
VDD = +12V ± 5%
VBB = -5V ± 5%
Notes:

~.ic Sales, Inc.
Raleigh NC 27619

Newfoundland
Nova Scotia

.Ontarip

..'

Prince EdWard Israrid
Quebec '.
Kay,t:.r0n,ics Limited

Ville St. Pierre Quebec H8R 1 A3

' 514/i11l7·'343<1

NEe

NEe Microcomputers, Inc.

U.S. DISTRIBUTORS
Arizona

G.S. Marshall
Tempe AZ 85282
602/968-61.81
Sterling Electronics
Phoeni x AZ 85036
. 602/258·4531
California
Diplomat/Westland, Inc.
Sunnyvale CA 94086
4081734·1900
IntermEirk Electronics

San Diego CA 921 21
714/279·5200
Intermark Electronics
Santa Ana CA 92705
714/540·1322
Intermark Electronics

Illinois
Diplomat/Lakeland, Inc.
Elk Grove Village I L 60007
312/595·1000
Semiconductor Specialists, Inc.
Ch icago I L 60666
312/279·1000

Missouri
Diplomat/St. Louis, Inc.
St. Louis MO 63144
314/645·8550

Pennsylvania

Semiconductor Specialists, Inc.

Semiconductor Specialists, Inc.

Hazelwood !IIIO 63042
314/731·2400

Pittsburgh PA 15238
412/781·81 20

Louisiana

New JerSey
Diplomat/I.P.C. Corporation
Mount Laurel NJ 08054
609/234·8080
Diplomat/I.P.C. Corporation
Totowa NJ 07512
201/785·1830'

Sterling Electronics

Baton Rouge LA 70806
504/926·9407
Maryland
Alma ~Iectronics Corpor.ation

Baltimore MD 21227
301/247·5955
Technico, Inc.
Columbia MD 21045
301/461·2200

Sunnyvale CA 94086
408/738·1111
G.S. Marshall
Canoga Park CA 91304
Massachusetts
213/999·5001
Diplomat/I.P.C. of Massachusetts
G .S. Marshall
Chicopee' Falls MA 01020
EI Monte CA 91731
413/592·9441
213/686·0141
Diplomat
G.S. Marshall
Holl iston MA 01746
Irvine CA 92707
6171429·4120
714/556·6400
~G.S. Marshall
Future: Electronics
San Diego CA 92111
Canada Corpora,ticn
714/278·6350
Natick MA 01760
61 7/879·0860
G.S. Marshall
Sunnyvale CA 94086
Semiconductor Specialists, Inc.
408/732·1100
Burlington MA 01803
. 617 /272~161 0
Sterling Electronics
North Hollywood CA 91605
,Sterling Electronics
Waltham MA 02154
213/7644111
617/894·6200
Sterling Electronics
San Diego CA 92111
714/565·2441
. Michigan
Western Microtechnology Sales
Diplon,at/Northland, Inc.
Sunnyvale CA 94086
Farmington MI 48024
408/737·1660
313/477·3200 '
Colorado
Century Electronics

Wheatridge CO 80033
303/424·1985

Connecticut·
Milgray Electronics, Inc.
Orange CT 06477
203/795-0711
Florida
Diplomat/Southland, Inc.
Clearwater FL 33515
813/443·4514

New Mexico
Century Electronics

Albuquerque NM 87123
505/292·2700
Sterling Electronics
Albuquerque NM 87107
505/345-6601
'New. York
Diplomat Electronics
Corporation

Woodbury NY 11797
516/921·9373
Milgray Electrohics, Inc.
Freeport NY 11 520
5'1 6/546·6000
Summit Distribut9rs, Inc.

Buffalo NY 14202

716/884·3450
Summit Elec. of Rochester, Inc.
Rochester NY 14623
716/442·3494

North Carolina
Resco/Raleigh
Raleigh NC 27612
919/781·5700

Reptron Electronics, Inc.

Livonia MI 48150
313/525·2700
Semiconductor Specialists, Inc..
Farmington MI 48024
313/478·2700

Minnesota
Diplomat/Electro-Com Corporation
Minneapolis MN 55421
6,1;2/788-8601'
SeiniconduClor'Speclalists, Inc"."
Minneapolis MN 55420
612/854-8841

Ohio
Hughes·Peters, Inc.
Cincinnati OH 45227
513/351·2000
Norman Davis Electronics

South Euclid OH 44121
216/381-0500
Reptron Electronics, Inc.

Alma Electronics Corporation

Philadelphia PA 19114
215/6984000

Texas
Kent Electronics

Houston TX 77036
713/780·7770
Semiconductor Specialists, Inc.

Dallas TX 75220
214/358·5211
Sterl ing,Electronics

Dallas TX 75229
214/357·9131
Sterling Electronics
Houston TX '17027
713/627·9800
Utah
Century. Electronrcs

Salt La keCity UT 84119
801/972·6969
Diplomat/Alta·Land, Inc.
'Salt Lake CityUT 84115

801/486·7227
~irginia

Techni,cQ, Inc.
Roanoke VA 24019
703/563·4975
Washington
Bell Industries
Believue'WA 98005
20&/747·1515
Sterling Electronics

Tukwila WA 98118
206/575·1910
Wisconsin
Semi.cQnductor Specialists, Inc.

Milwaukee WI 53226
414/257·1330

CANADIAN
DISTRIBUTORS
Ontario
,F.utur~ ~Electronics

Corporation

Ottawa Ontario K2C 3P2
613/820·9471
Future Electronics Corporation

Downsview Ontario M3H 5S9
416/663·5563

Columbus OH 43205
614/253·7433

Quebec

Hughes·Peters, Inc.
Columbus OH 43221
614/294·5351

Montreal Quebec H4P 2K5
514/735:5775

Future Electronics Corporation

415

11

!\fEe

NEe Quality Assurance
Procedures
One of the important factors
contributing to the final quality of
our memory and microcomputer
components is the attention
given to the parts during the
manufacturing process. All
Production Operations in NEC
follow the procedures of MIL
Standard 883A. Of particular
importance to the reliability
program are three areas that
demonstrate NEC's commitment
to the production of components
of the highest quality.

Visual
Inspection
Method
2010.2 Condo B

I. Burn-In - All memory and
microcomputer products are
dynamically burned in at an
ambient temperature sufficient to
bring the junction to a temperature
of 150 ·C. The duration of the
burn-in is periodically adjusted
to reflect Ihe production history
and experience of NEC with each
product. 100% of all NEC memory
and microcomputer products
receive an operational burn-in
stress.
II. Electrical Test- Memory and
microcomputer testing at NEC is
not considered a statistical game
where the device is subjected to a
series of pseudo random address
and data patterns. Not only is this
unnecessarily time consuming.
but it does not effectively
eliminate weak or defective parts.
NEC's test procedures are based
on the internal physical and
electrical organization of each
device and are designed to
provide the maximum electrical
margin for solid board operation.
For further information on
NEC's testing procedures see your
local NEC representative.
III. After completion of all
100% test operations. production
lois are held in storage
until completion of two groups
of extended sample testing: an
operating life test and a series
of environmental tests. Upon
successful completion of
these tests. the parts are released
from storage and sent to final
QA testing.

I

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I

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NEe Microcomputers, Inc.
416
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