1979_Philips_Semiconductors_and_Integrated_Circuits_Part_6b_ICs_for_Digital_Systems_in_Radio_and_TV 1979 Philips Semiconductors And Integrated Circuits Part 6b ICs For Digital Systems In Radio TV
User Manual: 1979_Philips_Semiconductors_and_Integrated_Circuits_Part_6b_ICs_for_Digital_Systems_in_Radio_and_TV
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Semiconductors and
integrated circuits
Part 6b
August 1979
ICs for digital systems in radio and
television receivers
SEMICONDUCTORS AND INTEGRATED CIRCUITS
PART 6b - AUGUST 1979
ICs FOR DIGITAL SYSTEMS IN RADIO AND
TELEVISION RECEIVERS
FUNCTIONAL AND NUMERICAL INDEX
--
GENERAL
PACKAGE OUTLINES
INTRODUCTION TO
DIGITAL SYSTEMS
DEVICE DATA
--
DA T A HANDBOOK SYSTEM
____JL__
DATA HANDBOOK SYSTEM
Our Data Handbook System is a comprehensive source of information on electronic components, sub·
assemblies and materials; it is made up of three series of handbooks each comprising several parts.
ELECTRON TUBES
BLUE
RED
SEMICONDUCTORS AND INTEGRATED CIRCUITS
COMPONENTS AND MATERIALS
GREEN
The severat parts contain all pertinent data available at the time of publication, and each is revised and
reissued periodically.
Where ratings or specifications differ from those published in the preceding edition they are pointed
out by arrows. Where application information is given it is advisory and does not form part of the
product specification.
If you need confirmation that the published data about any of our products are the latest available,
please contact our representative. He is at your service and will be glad to answer your inquiries.
This information is furnished for guidance, and with no guarantee as to its accuracy or completeness; its publication conveys no licence
under any patent or other right, nor does the publisher assume liability for any consequence of its use; specifications and availability of
goods mentioned in it are subject to change without notice; it is not to be reproduced in any way, in whole or in part without the
written consent of the publisher.
I(Octobe~1917
ELECTRON TUBES (BLUE SERIES)
Part 1a December 1975
ET1 a 12-75
Transmitting tubes for communication, tubes for r_ f. heating
Types PE05/25 to TBW15/25
Part 1b August1977
ET1b 08-77
Transmitting tubes for communication, tubes for r.f. heating,
amplifier circuit assemblies
Part 2a November 1977
ET2a ,11-77
Microwave tubes
Communication magnetrons, magnetrons for microwave
heating, klystrons, travelling-wave tubes, diodes, triodes
T-R switches
Part 2b May 1978
ET2b 05-78
Microwave semiconductors and componentsGunn, Impatt and noise diodes, mixer and detector diodes,
backward diodes, varactor diodes, Gunn oscillators, subassemplies, circulators and isolators
Part 3
January 1975
ET301-75
Special Quality tubes, miscellaneous devices
Part 4
March 1975
ET403-75
Receiving tubes
Part 5a March 1978
ET5a 03-78
Cathode"ray tubes
Instrument tubes, monitor and display tubes, C.R. tubes.
for special applications
Part 5b December 1978
ET5b 12-78
Camera tubes and accessories, image intensifiers
Part 6
ET601-77
Products for nuclear technology
Channel electron multipliers, neutron tubes, Geiger-MUlier
tubes
Part 7a March 1977
ET7a 03-77
Gas-filled tubes .
Thyratrons, industrial rectifying tubes, ignitrons,
high-voltage rectifying tubes
Part 7b May 1979
ET7b 05-79
Gas-filled tubes
Segment indicator tubes, indicator tubes, 'switching diodes,
dry reed contact units
Part 8
July 1979
ET807-79
Picture tubes and components
Colc;>ur TV picture tubes, black and white TV picture tubes,
monitor tubes, components for colour television, components for black and white television.
Part 9
March 1978
ET91;»3-78
Photomultiplier tubes; phototubes
January 1977
~.ril1979 ~
(
Jl
--------------------------------------------------------'
----------------------
SEMICONDUCTORS AND INTEGRATED CIRCUITS (RED SERIES)
~art 1a
August 1978
SC1a 08-78
Rectifier diodes, thyristors, triacs
Rectifier diodes, voltage regulator diodes (> 1,5 W),
transient suppressor diodes, rectifier stacks, thyristors, triacs
SC1b 05-77
Diodes
Small signal germanium diodes, small signal silicon diodes,
special diodes, voltage regulator diodes « 1,5 WI, voltage
reference diodes, tuner diodes
SC211-77
Low-frequency and dual transistors*
SC206-79
Low-frequency power transistors
SC301-78
High-frequency, switching and field-effect transistors
SC4a 12-78
Transmitting transistors and modules
SC4b 09-78
Devices for optoelectronics
Photosensitive diodes and transistors, light ·emitting diodes,
photocouplers, infrared sensitive devices,
photoconductive devices
SC4c 07-78
Discrete semiconductors for hybrid thick and thin-film circuits
SC5a 11-76
Professional analogue integrated circuits
March 1977
SC5b 03-77
Consumer integrated circuits
Radio-audio, television
October 1977
SC610-77
Digital integrated ~ircuits
LOCMOS HE4000B family
.SC6b 08-79
ICs for digital systems in radio and television receivers
~~~t 2/1. November 1977
0art 26 June 1979
th.··3
January 1978
da"rt 4a December 1978
~rt 4b
September 1978
L c July1978
0~. Novembe'.1978
~rt 5b
Part 6
/'Part 6b August 1979
Signetics integrated circuits 1978 .
Bipolar and MOS memories
Bipolar and MOS microprocessors
Analogue circuits
Logic - TTL
* Low-frequency general purpose transistors will be transferred to SC3 later·in 1979. The old book
SC2 11-77 should be kept until then.
'I (AU~~t979
COMPONENTS AND MATERIALS (GREEN SERIES)
Part 1
July 1979
CM107-79
Assemblies for industrial use
PLC modules, high noise immunity logic FZ/30-series,
NORbits 60-series, 61-series; 90-series, input devices,
hybrid integrated circuits, peripheral deviCes
Part 2a
October 1977
CM2a 10-77
Resistors
Fixed resistors, variable resistors, voltage dependent resistors
(VDR), light dependent resistors (LDR), negative temperature coefficient thermistors (NTC), positive temperature
coefficient thermistors (PTe), test switches
Part 2b
February 1978
CM2b
02~78
Capacitors
Electrolytic and solid capacitors, film capacitors, ceramic
capacitors, variable capacitors
Part 3a
September 1978 CM3a 09-78
FMtuners, television tuners, surface acoustic wave filters
Part 3b
October 1978
Loudspeakers
Part 4a
November 1978 CM4a 11-78
Part 4b
Febr!:,ary 1979
CM4b 02~79
Piezoelectric ceramics, permanent magnet materials
Part 6
April 1977
CM604-77
Electric motors and accessories
Small synchronous motors, stepper motors, miniature
direct current motors
Part 7
September 1971 CM709-71
Circuit blocks
Circuit blocks 100 kHz-series, circuit blocks 1-series, circuit
blocks' 1a-series, circuit blocks for ferrite core memory drive
Part 7a
January 1979
CM7a 01-79
Assemblies
Circuit blocks 40-series and CSA70 (L), counter modules
50-series, input/output devices
Part 8
June 1979
CM806-79
Variable mains transformers
Part 9
August 1979
CM908-79
Piezoelectric quartz devices
Quartz crystal units, temperature compensated crystal
oscillators
Part 10
April 1978
CM1004-78
Connectors
Augun
19791 (
CM3b 10-78
Soft ferrites
Ferrites for radio, audio and televiSion, beads and chokes,
Ferroxcube potcores and square cores, Ferroxcube transformer cores
FUNCTIONAL AND NUMERICAL INOEX
----
__________________Jl__
IN_DEX
________
SELECTION GUIDE BY FUNCTION
REMOTE CONTROL SYSTEMS
For general purpose application
SAF1032P
SAF1039P
receiver/decoder for infrared operation
remote transmitter for infrared operation
For simple and middle class TV receivers
SAA5000
SAA5010
SAA5012A
remote control transmitter encoder
remote control receiver decoder
remote control receiver decoder
For sophisticated radio and television systems
SAB3011
SAB3012
SAB3022
SAB3032
SAB3042
TDB1033
remote transmitter
receiver and analogue memory
receiver and analogue memory
receiver and analogue memory
infrared decoder; microcomputer compatible
preamplifier for ultrasonic/infrared remote control transmission
DIGITAL CHANNEL SELECT SYSTEM (DICS OR TRD)
Control systems
SAB2021
SAB3011
SAB3012
SAB3017
SAB3022
SAB3032
TDB1033
instruction encoder
remote transmitter
receiver and analogue memory
I BUS sub-system interface
receiver and analogue memory
receiver and analogue memory
preamplifier for ultrasonic/infrared remote control transmission
Tuning systems
SAB1009B
SAB1046
SAB2015
SAB2022
SAB2024
SAB2034
wide-band limiting amplifier
1 GHz divider-by-256
control and station memory circuit
fine detuning circuit
frequency control circuit
frequency control circuit for Italian TV channels
Display systems
SAB1016
control circuit for on-screen display of station and/or channel number
'I (
June 1979
-----.
VIDEO TUNING SYSTEMS (VTS)
Control systems
SAB3011
SAB3042
TDB1033
remote transmitter,
.'.
"
infrared deCoder;microcomputer~ompatlble ' .
preamplifier for ultrasonic/infrared remote control transmission
Tuning systems
SAB1009S
SAB1046
SAB3013
SAB3024
SAB3034
wide-band limiting amplifier
1 GHz divider·by·256
6·function analogue memory;micl'Qcomputer controlled
computer interface for tuning systems
analogue and tuning circuit
Display systems
SAA1060
LED display/interface circuit
TELETEXT AND VIEWDATA
Teletext decoder ICs
---=
-
SAA5020
SAA5030
SAA5040'
SAA5041
SAA5043
,SAA5050
SAA5051
SAA5052
Teletext timing chain circuit
Teletext video processor
Teletext acquisition and control cir<~!Jit
Teletext acquisition and control, circ,~it
Teletext acquisition and control circpit
Teletext character generator (English)
Teletext character generator (Germ~,,)
Teletext character generator (SwediSh)
RADIO TUNING SYSTEMS
SAA1056
SAA1058
SAA 1060
SAA1062
PLL frequency synthesizer
,c,
125 MHz amplifier and divider·by·32/33
LED display/interface circuit
'.
LCD display/interface circuit
FREQUENCY MEASUREMENT AND DISPLAY SYSTEM
SAA1058
SAA1070
2
125 MHz amplifier and divider·by·32/33
display interface and frequency counter
,
. '. ~
___- -___Jl__
IND,...--EX----.--
NUMERICAL INDEX
SAA1056
SAA1058
SAA1060
SAA1062
SAA1070
PLL frequency synthesizer
125 MHz amplifier and divider-by-32/33
LED display/interface circuit
LCD display/interface circuit
display interface and frequency counter
SAA50PO
SAA501 0
SAA5012A
SAA5020
SAA5030
remote control transmitter encoder
remote control receiver decoder
remote control receiver decoder
Teletext timing chain circuit
Teletext video processor
SAA5040
SAA5041
SAA5043
SAA5050
SAA5051
Teletext acquisition and control circuit
Teletext acquisition and control circuit
Teletext acquisition and control circuit
Teletext character generator (English)
Teletext character generator (German)
SAA5052
SAB1009B
SAB1016
SAB1046
SAB2015
Teletext character generator (Swedish)
wide-band limiting amplifier .
control circuit for on-screen display of station and/or channel number
1 G Hz divider-by-256
control and station memory circuit
SAB2021
SAB2022
SAB2024
SAB2034
SAB3011
instruction encoder
fine detuning circuit
frequency control circuit
frequency control circuit for Italian TV channels
remote transmitter
SAB30·1 ....
SAB3012A
SAB3013
SAB3017
$AB3017A
receiver and analogue memory (for TV)
receiver and analogue memory (for Radio); see SAB3012 data
6·function analogue memory; microcomputer controlled
I BUS sub-system interface
standard version; see SAB3017 data
SAB3022
SAB3022B
SAB3024
SAB3032
SAB3034
receiver and analogue memory
standard version; see SAB3022 data
computer interface for tuning systems
receiver and an~Jogue memory
analogue and tuning circuit
SAB3042
SAF1032P
SAF1039P
TDB1033
infrared decoder; microcomputer compatible
receiver/decoder for infrared operation'
remote transmitter for infrared operation
preamplifier for ultrasonic/infrared remote control transmission
---
3
GENERAL
Rating systems
Handling MOS devices
-
____Jl_____
RATING SYSTEMS
The rating systems described are those recommended by the International Electrotechnical Commission
(IEC) in its Publication 134.
DEFINITIONS OF TERMS USED
Electronic device. An electronic tube or valve, transistor or other semiconductor device.
Note
This definition excludes inductors, capacitors, resistors and similar components.
Characteristic. A characteristic is an inherent and measurable property of a device. Such a property
may be electrical, mechanical, thermal, hydraulic, electro-magnetic, or nuclear, and can be expressed
as a value for stated or recognized conditions. Acharacteristic may also be a set of related values,
usually shown in graphical form.
Bogey electronic device. An electronic device whose characteristics have the published nominal values
for the type. A bogey electronic device for any particular application can be obtained by considering
only thosecharacteristiclii which are directly related to the application.
Rating. A value which establishes either a limiting capability or a limiting condition for an electronic
device. It is determined for specified values of environment and operation, and may be stated in any
suitable terms.
Note
Limiting conditions may be either maxima or minima.
Rating system. The
se~
of principles upon which ratings are established and which determine their
interpretation.
Note
The rating system indipates the division of responsibility between the device manufacturer and the
circuit designer, with the object of ensuring that the working conditions do not exceed the ratings.
ABSOLUTE MAXIMUM RATING SYSTEM
Absolute maximum ratings are limiting values of operating and "environmental conditions applicable to
any electronic device of a specified type as defined by its published data, which should not be exceeded under the worst probable conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device,
taking no responsibility for equipment variations, environmental variations, and the effects of changes
in operating conditions due to variations in the characteristics of the device under consideration and
of all other electronic devices in the equipment.
The equipment manufacturer should design so that, initially and throughout life, no absolute maximum
value for the intended service is exceeded with any device under the worst probable operating conditi.ons with respect to supply voltage variation, equipment component variation, equipment control
adjustment, load variations, signal variation, environmental conditions, and variations in characteristics
of the device under consideration and of all other electronic devices in the equipment.
'I
October 1977
---
-=
___Jl_____
DESIGN MAXIMUM RATING SYSTEM
Design maximum ratings are limiting values of operating and environmental conditiops applicable to a
bogey electronic device of a specified type as defined by its published data, and should not be exceeded under the worst probable conditions.
T~ese
values are chosen by the device manufacturer to provide acceptable serviceability of the device,
taking responsibility for the effects of changes in operating conditions due to variations in the characteristics of the electronic device under consideration.
The equipment manufacturer should design so that, initially and throughout life, no design maximum
value for the intended service is exceeded with a bogey device under the worst probable operating
conditions with respect to supply voltage variation, equipment component variation, variation in
characteristics of all other devices in the equipment, equipment control adjustment, load variation,
signal variation and environmental conditions.
DESIGN CENTRE. RATING SYSTEM
Design centre ratings are limiting values of operating and environmental conditions applicable to a
bogey electronic device of a specified type as defined by its published data, and should not be exceeded under normal conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device
in average applications, taking responsibility for normal changes in operating conditions due to rated
supply voltage variation, equipment component variation, equipment control adjustment, load variation,
signal variation, environmental conditions, and variations in the characteristics of all electronic devices.
The equipment manufacturer should design so that, initially, no design centre value for the intended
service is exceeded with a bogey electronic device in equipment operating at the stated normal supply
voltage.
.
----
2
October 1977
(
_ _ _ _J
HANDLING
MOS DEVICES
HANDLING MOS DEVICES
Though all our MaS integrated circuits incorporate protection against electrostatic discharges, they
can nevertheless be damaged by accidental over-voltages. In storing and handling them, the following
precautions are recommended.
Caution
Testing or handling and mounting call for special attention to personal safety. Personnel handling MaS
devices should normally be connected to ground via a resistor.
Storage and transport
Store and transport the circuits in their original packing. Alternatively, use may be made of a conductive
material or special IC carrier that either short-circuits all leads or insulates them from external contact.
Testing or handling
Work on a conductive surface (e.g. metal table top) when testing the circuits or transferring them from
one carrier to another., Electrically connect the person doing the testing or hanpling to the conductive
surface, for example by a metal bracelet and a conductive cord or chain. Connect all testing and handling equipment to the same surface.
Signals should not be applied to the inputs while the device power supply is off. All unused input leads
should be connected to either the supply voltage or ground.
Mounting
Mount MaS integrated circuits on printed circuit boards after all other components have been mounted.
Take care that the circuits themselves, metal parts of the board, mounting tools, and the person doing
the mounting are kept at the same electric (ground) potential. If it is impossible to ground the printedcircuit board the person mounting the circuits should touch the board before bringing MaS circuits
into contact with it.
Soldering
Soldering iron tips, including those of low-voltage irons, or soldering baths should also be kept at the
same potential as the MaS circuits and the board.
Static charges
Dress personnel in clothing of non-electrostatic material (no wool, silk or synthetic fibres). After the
Mas circuits. have been mounted on the board proper handling precautions should still be observed.
Until the sub-assemblies are inserted into a complete system in which the proper voltages are supplied,
the board is no more than an extension of the leads of the devices mounted on the board. To prevent
static charges from being transmitted through the board wiring to the device it is recommended that
conductive clips or conductive tape be put on the circuit board terminals.
Transient voltages
To prevent permanent damage due to transient voltages, do not insert or remove MaS devices, or
printed-circuit boards with MaS devices, from test sockets or systems with power on.
Voltage surges
Beware of voltage surges due to switching electrical equipment on or off, relays and d.c. lines.
'I
October 1977
<.
PACKAGE OUTLINES
-~-j
PACKAGE
OUTLINES
14-LEAD DUAL IN-LINE; PLASTIC (SOT-27S, T, V)
1...- - - - - - - 1 9 , 5
II
max - - - - - - _
---~
I
I
+
~o
3,05
;j- 0,32
~3
12x
+
max
--
~
,
.
,~,
.
:
I
~(')
.
-- ~~xl-I-I--I_I_I-1
II
1,1
I
:1
1,1
max
.I-m-_/,
9.5_
7,6
7Z51136.\O
Positional accuracy.
@ Maximum Material Condition.
(3)
(1)
Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2)
Lead spacing tolerances apply
from seating plane to the line
indicated.
(3)
Index may be horizontal as shown,
or vertical.
top view
Dimensions in mm
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mm above it).
If its temperature is below 300 0C it must not be in contact for more than 10 seconds; if between
300 0C and 400 oC, for not more than 5 seconds.
2. By dip or wav~
The maximum permissible temperature of the solder is 260 oC; this temperature must not be in
contact with the joint for more than 5 seconds. The total contact time of successive solder waves
must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must
not exceed the specified storage maximum. Ifthe printed-circuit board has beEm pre-heated, forced
cooling may be necessary immediately after soldering to keep the temperature withinthe permissible limit.
3. Repairing soldered joints
The same precautions and limits apply as in (1) above.
')
June 1979
16-LEAD DUAL IN-LINE'; PLASTIC '(SOT-3St
...
41----------
lj
1
1:
51
--~
~
'
I
I
~
3,4
•
22 max - - - - - - - -
'1 x
~3
m~
~(11
~
lZSJ __1_1_1_1
___ 2,21_1---1_1
max,
il
ma:x
"
fI
,','
~-m-l'
'_9,5~
, ,
.$-
'7,6
7ZS5041,7
Positional accuracy.
I
@
Centre-lines of all leads are
within ±O,127 mm of the nominal
position shown;inthe worst case,
the spacing 'between any two leads
~ may deviate from nominal by
±O,254 mm.
(2)
Lead spacing tolerances apply
from seating plane to the line
indicated.
top view
Dimensions in mm
----
Maximum Material Condition.
(1)
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mmabove it).
'If i'tit'emperature 'is beloW 30(j 0Cit must not' be in contact for more than 10 seconds; if between
300 °C ,and 400 oC, for not more than 5 seconds.
2. By dip or wave
Themaximuiri permissiblefemperature tif the s61der is 260- o C; this te'J1i'perature must not beih
contaCt with the joint for more tHan '5 seconds. The totalc()ntact 'time of successiVe solder waves
must not exceed 5 seconds.
/'
The device 'may be mounted up to the ~eating plcme;but the temperatllre'of the plastic body must
, not exceedih~ speCified storage ma,ximum.lhhe printed-circuit board' has been pre~heated,forced
cool iri~ maybe' necessar{lmr'n-ediatehl aftersolderillg to, keep the t~mperatiife"withinthe pei'l"hissible limit.
'
~.
Repairing soldered joints
The same precautions and limits ,apply as in (1) abolie.
'2
_______J
PACKAGE
OUTLINES
16-LEAD DUAL IN-LINE; PLASTIC (SOT -382)
- - - - - - - - 19,5 max - - - - - - -
4,7
max
+o,sf ,I
~mln •
+
-.
3,43
3,OS
076
+'
--
,
'
~
,~,
I
I
I
-. II 0,32
'I
I
irmax
ii,
IIII
14x
+
121
,
,
,
"f_~_r,
'
I_I+--I~I_I_I_I_I
0,76
max
_9,S_1
7,6
$
-I@)
top view
Positional accuracy.
Maximum Material Condition.
(1 )
Centre-lines of all leads are
within ±O,127 mm of the n~minal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±O,254 mm,
(2)
Lead spacing tolerances apply
from seating plane to the line
indicated.
lead 1 indication (either index (')r sign)
Dimensions in mm
7273586.1
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mm above it').
If its temperature is below 300 0C it must not be in contact for more than 10 seconds; if between
300 0C and 400 oC, for not more than 5 seconds.
2. By dip or wave
The maximum permissible temperature of the solder is 260 °C; this temperature must not be in
contact with the joint for more than 5 seconds. The total contact time of successive solder waves
must not exceed 5 seconds. '
The device may be mounted up to the seating plane, but the temperature of the plastic body must
not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced
cooling may be necessary immediately after soldering to keep the temperature within the permis.
sible limit.
3. Repairing soldered joints
The same precautions and limits apply as in (1) above.
June 1979
3
l~.,~______~
PACKAGE
OUTLINES
18-LEAD DUAL IN:-LlNE; PLASTIC (SOT -102A)
23,5 max - - - - , - - - - - : - - - "~
4,7
max
t
~
+'
'~11
min
3,9
3,4
1Sx
,
.. '
,
,
I
'/2,541'
....j ... IO.254
,
,
,
12
11
10
•
07S 12 )
@I
(1)
... 1,75/~1_1.:.--1_1_1~1_1_1
ma~
14
-8,25maxside view
I
II
II
max'
@
Maximum Material Condition.
(1)
Centre-lines of all leads are
within ±O, 127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±O,254
mm.
II
1.1
~
.~
(2)
lead spacing tolerances apply
from seating plane tothe line
indicated.
(3)
Index may be horizontal as shown,
or vertical.
i-/7,S21_i
'_41--_ _
,9,5
'-·S7,S
7Z70173.2
Dimensions in mrn
SOLDERING
See page 1 of this chapter (SOT-27S, T, V)
4
Positional accuracy.
I
II
II
u
I
$-
I
I
__ ,L0,32
June 1979
(
top view
____------J
PACKAGE
OUTLINES
24-LEAD DUAL IN-LINE; PLASTIC (SOT-101A)
.
I-
c:
il
32 max
_ _ _ --1
-----'h
~+
+
,
3,9
3,4
2,2
max
i_
top view
(3)
----
\
----- - - - - - - - - - - - -
$
Positional accuracy.
@ Maximum Material Condition.
side view
(1 )
Centre-lines of all leads are
within ±O,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±O,254 mm.
(2)
Lead spacing tolerances apply
from seating plane to the line
indicated.
(3)
Index may be horizontal as shown,
or vertical.
max
-----~
~~:15
----------.'
Dimensions in mm
SOLDERING
See page 1 of this chapter (SOT-27S, T, V)
June 1979
5
.PACKAGE
l"'"-----:--_ __
OUTLINES
28-LEAD DUAL IN-LINE; PLASTIC (SOT-117)
, - - - - - - - - - - - - - 36max
.,
c
fj
+
,
3,9
3,4
i.....
1,7
max·
28
27
26
25
24
23
22
21
20
19
18
17
16
15
top view
13)
--=
-=
~
- - 15.B max - - -
_ _ ,".1
-~
-
-I
mo: -_I
side view
- - - - - M - - - -...
,. . -~---
SOLDERING
See pagel of this chapter (SOT-27S, T, V)
June
.-,.
~~:1~ ~-~~-
Dimensions in mm
6
•
1979rf
?l73669.1
$
Positional accuracy.
@
Maximum Material Condition.
(1)
Centre-I ines of all leads are
within ±O, 127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±O,254 mm.
(2)
Lead spacing tolerances apply
from seating 'plane to the line
indicated.
(3)
Index may be hori?ontal as shQI,IVn, '
or vertical.
INTRODUCTION TO
DIGITAL SYSTEMS
-
_ _ _ _J
INTRODUCTION TO
DIGITAL SYSTEMS
TUNING AND CONTROL SYSTEMS FOR RADIO AND
TV R!=CEIVERS, TEXT DECODERS AND TV GAMES
FOREWORD
TV and radio receivers have conventionally used analogue tuning and control systems. However, the
development of lSI technology has now progressed to the state where these functions can be economically performed by mass-produced digital lSI circuits. Bulky and unreliable mUlti-way switches and
potentiometers can be replaced by simple single-pole switches. Moreover, the digital circuitry allows the
use of remote control systems, again developed using lSI techniques.
New functions for the TV receiver, such as Teletext and video games, can easily be accommodated
using digital control techniques. This handbook describes a complete range of lSI circuits designed to
perform all tuning, control and remote control functions required for TV and radio receivers. The
processes used to fabricate these ICs vary according to the function, for example, ECl for high-frequency circuits, lOCMOS for low-power circuits, etc. However, all circuits are produced by basically
simple processes, providing good yield and reliability.
Available systems·
• Remote control systems: three different remote control systems are available which cope with
different.market or system requirements.
• DICS (Digital Channel Select) system (also referred to as the TRD system): the well-known system
in volume productiqn; closed loop digital tuning, based on the Fll (frequency locked loop) principle; including remote control and display features.
• VTS (Video Tuning System): the next generation system for microcomputer based closed loop
tuning systems (Fll principle); a full range of microcomputer peripherals.
• Teletext and Viewdata systems: the new digital text communication systems with on-screen text
display.
• RTS (Radio Tuning System): digital tuning, control and display system for radio receivers, with or
without remote control.
• Digital Frequency Counter system: frequency measurement and display system for radio receivers.
The systems are designed so that they can be operated independently or built into a single system.
Their compatible design philosophy means that basic systems can easily be expanded when design
requirements are changed. Moreover, the TV and radio systems can be operated independently via a
single remote control unit, while sub-systems such as TV games, slide and film projectors and recorders
can be operated via the TV or radio equipment. Figure 1 shows a typical system approach, controlling
TV, radio etc. from a Single transmitter unit.
I (June
1979
---
~Inml-
Oz
N
C5-t
;:j:~
»0
X-c
en =0
.~-t
4 MHz
PACKAGE OUTLINE
16-lead 01 L; plastic (SOT-38Z).
June 1979
SAA1056
GENERAL DESCRIPTION
The integrated circuit SAA 1056, together with a suitable prescaler (32/33) and 10oIY-filter; forms a
complete synthesizer functionfor,AI\,1/FM radio tuning systems.
The circuit comprises the fOIl~lIIiing blocks:
a. A dividing circuit formed by a 5-bitbinary Swallow counter with and a 1O-bit binary ptogrammable
divider .
. b. A frequency/phase detector which, via an external loop-filter; generates the control voitage for the
voltage-controlled oscillator (VCO). The detector also gives a lock indication.
c. A 13-bit binary reference frequency divider. This divider delivers the reference frequency to the
frequency Iphase detector.
d. The decoder delivers the dividing number for the reference divider. Depending on the logic states of
the 2 inputs (REF1 and REF2), four different dividing ratios (160,400,800 and 8000) for the,
reference 'frequencies can be fed to the frequency/phase detector~
e. A reference frequency oscillator. Together with a 4 MHz crystal a stable frequency is generated,
from which the reference frequencies are, derived. The 4 MHz signal is also available at a decoupled
output as a system clock for other ICs. ,
f. A 17-bit latch to store the data for the dividing number of the programmable divider (block a) and
2 bits for reference frequency choice.
g. A 17-bit shift register to receive the serial data for the latch.
h. A bus control to avoid improper data to be handled by the system.
i. Level shifters for the control inputs DATA, DLEN, ClB and REFE so no external interface is
necessary between the SAA 1056 on 9 V and the other ICs on 5 V.
OPERATION DESCRIPTION
Datainpl,Its (DlEN and DATA,)
The SAA 1056 accepts the serial 17-bit data word synchronized wit~ the clock burst (ClB), are offered
at the data input DATA. However, a command is accepted only when the data line enable input OLEN
is HIGH at the same time.
II
DlEN~ _ _~
-.-.-.
--"-
1/
OATA~ . . . .~~__~__~__~~~~__~__~~~~~~~
H
ClB l ----1-1
e---:-----
J....
Fig.
2,
January 1979
~
data word
-~---~..~I
Pulse diagram of the 17-bit data word.
7Z7-.911
P_L_L_f_re_q_u_e_n_c_y_s_y~n-th-e-s-iz-e-r- - - - - - - - - -
____
_ ___----______
~~
SAA1056
Each data word must start with a leading zero. The SAA1056 checks the data word for the correct
length (17 bits) including leading zero. The data word contains 15 bits as a binary coded ratio
for the programmable divider. The first 10 bits program the 1O-bit programmable divider and the
next 5 bits program the Swallow counter (see Fig. 3). The 16th bit (REF1) determines the ratio
of the reference divider in conjunction with the logic signal at input REFE.
5-bit data
Swallow counter
1O-bit data
programmable divider
£
I I
I
I // I
I
Isb
mSbl'Sb
mSblREFll
I~-·--.~t~·--~---L---L--~----~i ~·~--~--~~--L---~I-e-ad-i~n~g-Z-er-o~-1--~
7Z77994
Fig. 3 Organization of a data word.
Setting the reference divider (input REFE and control-bit REF1)
The reference divider can be set to four different ratios, using the two signals REF2 and REF1:
control bit
REF1
input
REFE
1
1
o
o
dividing ratio
Nref
1
160
400
800
8000
o
1
o
reference frequency
at fosc = 4 MHz; fref
25 kHz
10 kHz
5 kHz
0,5 kHz
Input frequency divider (FIN)
The input frequency is applied to input FIN for further processing in the circuit. It is divided in the
Swallow counter and the 10-bit programmable divider corresponding to the received data word. The
dividing numberof the dividing circuit is given by the following equation:
N = NS + P x Np
with:
Np ~ NS; 0";; NS ..;; 31
in which:
N
= dividing number of total divider
NS = value for the Swallow counter
= lowest dividing number of prescaler
p
Np = dividing number ohhe 1O-bit programmable divider.
January 1979
3
SAA/1056
OPERATION DESCRIPTION (continued)
In combination vvith the 32/33 divider (PRECO - 5AA 1058), the minimum and maximum dividing
number can be calculated:
Nmin = 0 + 32 x 31 = 992
Nmax =31 + 32 x 1023 = 32767
In combination with a standard 10/11 divider, the minimum and maximum dividing numbers are:
Nmin =0+ 9x 10=90
Nmax = 31 + 10 x 1023 = 10261
Count mode output for prescaler (CMOD)
Depending on the received data word, the 5~bit Swallow counter generates a signal for setting the
prescaler.
'.
0= divide by low dividing number
1 = divide by high dividing number.
The signal appears about 150 ns after the input pulse F'IN (see Fig. 4).
FIN
CMOD
H
L
~ ---t---~
-
~ ~150nsl-
~150nsL
;;;'250ns
-
7Z74912
Fig. 4 Timing of the CMOD signal.
Phase detector (frequency up/down) and lock detector outputs (FDN, FU, LOC)
-=-=
The frequency/phase detector outputsFDN and FU generate a contro(voltage via an external loop for
the voltage-controlled oscillator (VeO).
FDN: phase detector output, frequency down
0= active
1 =' inactive
FU:
phase detector output, frequency up
0= inactive
1 = active
Output LOC generates an extra signal if the loop is locked.
o = loop unlocked
1 = loop locked.
4
January 1979
(
P_L_L_f_re_q_ue_n_c_y_sy_n_~_e_si_ze_r ~
___
__
~ ~, ~_S_A__A_1_0_5_6~____
__________________________
V DDI
REFE
FU
CMOD
FIN
DLEN
LOC
DATA
GRZ
CLO
7
VSS'
8
FDN
9
OSC
Fig. 5 Pinning diagram.
PINNING
16
VDD
8 Vss
positive supply
negative supply (0 V)
Inputs
1
13
J
6
J
TEST
7Z77993
)
J
)
VDD
CLB
c
)
__
2
5
3
11
VDDI
FIN
DAT A
CLB
DLEN
REFE
QRZ
supply voltage for the level shifters
input frequency; maximum 4 MHz
data input for dividing numbers
clock burst for data transmission
data line enable for data transmission
reference frequency selection
quartz crystal input (4 MHz)
Outputs
4
12
10
14
7
9
CMOD
LOC
FDN
FU
CLO
OSC
count mode output for prescaler
lock detector output
phase detector output; frequency down
phase detector output; frequency up
system clock for other ICs (4 MHz)
quartz crystal oscillator output
January 1979
5
SAA1056
RATINGS
Limiting values in accordance with the
Ab~olute
Maximu';" System (IEC 134}
-0,3to+11 V
Supply volt,age range
VOO
Input voltage range
VI
-0,3 to +VOO V
Input current
±II
max.
1,0 mA
Output current
±IQ
max.
10 mA
I
max.
10 mA
Po
Ptot
max.
100 mW
max.
300 mW
Current from VOOI to VOO (VODI
< VOO)
-Power dissipation per output
Total power dissipation per package
Operating ambient temperature range
Tamb
T stg
Storage temperature range
-20 to +80 0C
-55 to +150 0C
CHARACTERISTICS
VSS;::: 0; T amb = -20 to +80 oC; unless otherwise specified'
Supply voltages
Quiescent current
Inputs lI\{ithout level
shifters; FIN, QRZ, TEST
input voltage LOW
input voltage HIGH
input current HIGH
input current LOW
VOO
V
symbol
min.
typo max ..
-
-
VOO
VOOI
8
4,5
9
5
10
5,5
V
V
10
100
-
-
100
p.A
8 to 10
8to 10
10
10
VIL
VIH
IIH
-IlL
0
0, 7V OO -
conditions
0, 3V OOV
VOO V
p.A
1
p.A
1
input frequency
8to 10
-
-
MHz
8 to 10
fl
0
4
duty factor
45
55
%
rise/fall time
8 to 10
tr,tf
-
-
50
ns
8 to 10
8to 10
VIL
VIH
(lo=O;VI =VOO
or VOOI or VSS
VI = 10 V
VI =0
Inputs with level shifters
OATA,CLB,OLEN,REFE
at VOOI = 4,5 to 5,5 V
input voltage LOW
input voltage HI G H
input current HIGH
input current LOW
8 to 10
rise/fall time
-
pulse width
.6
January 1979
10
10
(
IIH
-IlL
tr,tf
twH,twL
0
- 0,2VOO V
0, 8V OOIVOOI V
p.A
1
p.A
1
-
-
-
500
-
1
-
VI = 10 V
VI=O
p.s
ns
{at 0,8 xVOO resp.
0,2 x VOO levels
SAA1056
Pll frequency synthesizer
Voo
V
symbol
min.
typo max.
conditions
Outputs CMOO, CLO
open-drain, n-channel
output voltage LOW
CMOO
CLO
8 to 10
8 to 10
VOL
VOL
-
-
-
0,5
0,5
V
V
10
lOR
-
-
20
JJ.A
fall time; CMOO
8 to 10
tf
-
-
20
ns
fall time; CLO
8 to 10
tf
-
-
50
ns
-
output leakage current
IOL=5mA
10L = 6 mA
Va = 10 V
{CL = 25 pF
Rl = 1,2 k.Q ± 20?'6
{CL = 50pF
RL = 1 k.Q ± 10%
Outputs LOC, FU, FON
output voltage HIGH
output voltage LOW
rise/fall time
Output OSC
output voltage HI GH
output voltage LOW
8 to 10
·8 to 10
VOH
VOL
-
-
0.5
V
V
8 to 10
tr,tf
-
-
20
ns
8 to 10
8 to 10
VOH
VOL
VOO-1
-
-
V
V
VOO-0,5-
-
1
-10= 2,5 mA
10 = 5 mA
{Cl = 25 pF
RL=10k.Q±10%
-10= 1 mA
10:::: 1,8 mA
January 1979
7
-'
co
1111111
(J)
»
'»
APPLICATION INFORMATION
~
-0
(]I
.0)
c...
c:.
i
~
-.J
co
T
HI
22nF
. -=~~I!..
9Vo-fYVY'
1
27!l
~r-----~-
T I
II II
'\
n8008zl
Fig. 6 Typical application of the SAA1056 with the SAA1058 in a TV receiver.
tuning
voltage
.-.-"'a
I
CD
::::l
HI
22nF
~
T
[27fi
Rl
R2
~
Cl
::::l
:;t
i
(kll) (kill (JlF)
FM 15 4) 1
SW 10 47
1
MIWILW 68 47
~.
1
choke
9V
c....
c:
::::l
CIl
72600B3.1
<0
(J)
"-I
»
»
......
<0
Fig. 7 Typical application of the SAA 1056 with the SAA 1058 in a radio receiver.
o01
0)
<0
l___
DEVELOPMENt SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbaok system and
does not necessarily imply that the device will go into production
S_A_A_1_0_58_ _
125 MHz AMPLIFIER AND DIVIDER-BY -32/33
The silicon monolithic integrated circuit SAA 1058 i~ designed as a programmable-ratio divide-by-32/33
prescaler. It is intended for use in digital radio tuning systems and frequency counters in radio applications with an input frequency range from 0,5 to 125 M Hz. The high-frequency inputs are differential
inputs of a preamplifier for handling a.m. as well as f.m. oscillator signals. One output set provides
complementary ECl levels by emitter followers and a second output buffer set is intended to drive
MOS circuits by open collectors.
3
14
12
10
VCC 1 VCC2 VCC3
n.c.
REFIN
2 REFIN
5
0ECL 9
4
8
-732/33
REFIN
2
15
SET
VCC1
3
14
VCC2
IN
4
13
CM33
SAA 1058
IN
5
12
VCC3
VEE
6
11
°ECL
noc
7
1()
VCC4
°OC
8
9
°ECL
CM33
15
13
7Z79405
6
7Z79406
Fi.g. 1 Block diagram.
Fig. 2 Pin diagram.
VCC1 = VCC2 = VCC3 = VCC4 = 5 V
VEE = OV (ground)
Pin 16 preferably connected to VEE
QUICK REFERENCE DATA
Supply voltage
VCC
InplJt frequency range
fi
Input voltage range
f = 0,5 to 30 MHz
f = 30 to 125 MHz
Power consumption per package (no load)
5 ± 10% V
0,5 to 125 MHz
Vi(rms)
Vi(rms)
Pav
5 to 1.00 mV
10 to 100 mV
typo
550 mW
PACKAGE OUTLINE
16-lead 01 l; plastic (SOT-38).
I(
June 1979
--
SAA1058
E
~
Cl
:0
N
M
':;
f:
'"
M
~
""
co
M
....
c:5
en
iL:
M
2
June 1979
I(
l___
125 MHz amptifier and divider-by-32/33
S_A_A_10_5_8_ _
H n-1
IN L
SET
~
n
+1
+2
+3
...... +16
+17
-fJ
--
L
OECLorOOC
~
....... +31
i
H
eM33
+18
+32
+33
~---V'\.Y\/'---~
...
I
I
---+1--.. .
I
---~ __ ~
____ H
~---~
RECLQrOOC L
7Z80062.A
H n-1
IN.t.
SET :
CM33
n
.1
.2
+3
...... +16
+17
.18
....... +31
---0
,
~
I
-----"
H
ooe
H
~--
L
SP
+1'
+16
+18
+31
+33
+66 .81
.83 +96
~.49 ____ ~+65----I\(v,.___
+98
tQV
-----+----+
+
----t- --- + -----,n-I ---T---"
'11--· J=
'
~ --.J" ---.J" --il--~-l-H
---
L
H
CM33 L
OECLorQOC
+48' +50 +64
+n
, ___ ++17 ____ ++32 _____
---
---
I
OECLorOOC
L
7Z80063.A'
1-n
_,',N:
+33
'
OECLorOOC L
OECLor
+32
~ .. --~---~
---
I
I
I
I
I
I
L
__
~ ~ __ ~- - ~ __ -][--~__
L
tsu
-......==
--~
,l
~
tsu
~
7Z80064.1A
Fig. 4 Timing diagrams of programmable frequency dividing.
3
,l________---------.------
SAA1Q58
RATINGS
Limiting values ir;1 accordance wi:th the Absolute Maximum System (IEC 1,34)
7 V
Supply voltag.e(pins 3, 10,12 and 14) ,
VCC
max.
Output supply voltage (ptns 7 and 8, RL = 470S1)
Voo
max.
Input voltage
Total power dissipation up to T amb= 60 0C
VI
Ptot
max.
Storage temperature
T stg
-25 to
Operating ambient temperature
Tamb
14
V
Oto VCC
0,76 W
+ 125 °C
-20 to + 60 0C
CHARACTERiStiCS
VEE
= 0 V; V CC = 5 V
Supply current (13
(see Fig. 6); T amb
+ 110 + 112 + 114)*
Count input voltage (pins 4 and 5)
A.M. (0,5 MHz to 30 MHz)
F.M. (30 MHz to 125 MHz)
typo
<
110 mA
135 mA
Vi(rms)
5 to 100 mV
Vi(rrns)
10 to 100 mV
Ri
>
1 kU
Count mode input (pin 13)
input voltage for division-ratio 32
VCML
input voltage for division-ratio 33
VCMH
3V
-ICML
<
>
<
input current at V CM
=2 V
2 V
3,5 mA
tsu
typo
50 ns
I nput capacitance
CCM
typo
1 pF
Reset input voltage (pin ,15)
reset
VRL
3 V
-IRL
<
>
<
VOH
VOL
>
<
3,7 V
3,3 V
VOH
>
<
9V
no reset,
VRH
Input current at VR = 2 V
Emitter follower outputs (pins9 and 11)
output voltage; RL = 4,7 kU to ground
Open collector outputs (pins 7 and 8)
VDD= 11 V; RL = 470,S1
Output voltage HIGH
Output voltag~ LOW
* See Fig. 6.
4
ICC
A.C. input impedance
Set-up time changing the division-ratio
from 32 to 33 or vice versa
-===
--
= 25 oC, unless otherwise specified.
June
19791f
VOL
2 V
2 mA
2 V
125 MHz amplifier and divider-by-32/33
l_-.,.-_S_A....,...A_1_05--"B....,...-_
CHARACTER ISTICS (continued)
Open collector outputs (pins 7 and 8)
transition times, no capacitive load
100
Vi (rrT'ls)
(rnV)
typo
typo
15 ns
12 ns
7Z79407
/"
/
V/~ '// /: '/ /1/
/'///1 /'/. V/ /./1 / /
/ /1
/
/
/"
/
v/
/1/'
75
V'I/'
1/
VI/'
1/
VI/'
50
Vi-'
garanteed operating region
Vi-'
VI/'
1/
1//
//
25
1/
/
//
/
//
v/
/
///
////.: 7?; ~ /.jt
I'i
~ /V '///
/
'/"/v'/ ://1
10
Fig. 5 Triggering level requirements.
---=
=
'I (
June 1979
5
SAA105Sl
~~--------~~~--~~--~----~
Voo
Vcc
(!)V)
(9V)
I---_-I~
22nF
27n
RC7
RCS
470
470
n
14
12
n
10
50n
11
a.m. input
9
f.m: input
+32/33
8
'output
7
13
16
6
7Z79409
SET
CM33
Fig. 6 Test circuit..
......
----
6
June
19791 (
:....
N
APPLICATION INFORMATION
U1
:s:
:I:
HI
T
N
III
[27fl
Rl
22nF
3
'2..
R2 Cl
:::;;
(k0) (k0) (~F)
FM
SW
15 4,7
10 47
MlW/LW 68 47
il'
1
1
III
:::l
~
~
1
<'
a:
~
6W
<
N
t;)
W
AM
3k3
i
~
22nF
-,
.~
FM
82Q
B2Q
c....
c:
choke
:::l
CD
~
CO
9V
......
tuning
CO
7280083.1
voltage
~
-4
Fig, 7 Typical application of the SAA 1056 with the SAA 1058 in a radio receiver,
o01
(Xl
......
1111111
co
1II11U
en».
APPLICATION INFORMATION
»
....
o
/01
ex>
HI
T
~.---~--
22nF
CLB6p q6CLO
OLEN
DATA
Fig.8 Typical application of the SAA1056 with the SAA 105~ in a TV receiver.
tuning
voltage
L___
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
S_A_A_10_6_0_ _
LED DISPLAY/INTERFACE CIRCUIT,
6
Vec
15,19 v
DUP
LOEX
Features
DATA
OLEN
7Z78907.1
CLB
Fig. 1 Blqck diagram.
•
•
•
•
•
•
•
Driving 7, 14, 16-segment displays.
Driving linear displays, bar graph displays for analogue functions.
Serial to parallel decoder.
Bus control for the selection of 18-bit words.
2 x 16-bit latch.
Duplex operation for two modes of output: static (16 bit) or dynamic(2 x 16 bit).
Data transfer control.
• 2 outputs for higher output current (80 mAl.
---
QUICK REFERENCE DATA
Supply voltage range
Operating ambient temperature range
Maximum input frequency
Supply current
Output current
Output current (08 and 016 only)
VCC
4t06 V
Tamb
-20 to + 80 0C
fl
typo
typo
ICC
10
10
<
<
PACKAGE OUTLINE
24-lead OIL; plastic (SOT-101A).
EE
I (M~1979
50
60
40
80
kHz
mA
rnA
rnA
~
Jl________________________________
___S_A_A1_0_6_0___
GENERAL DESCRIPTION
The integrated circuit SAA 1060 is primarily designed to drive the display unit of a digital tuning
system. Itean also be used as a 16-bit serial to parallel decoder. Since the device has no decoder (this
is handled by a microcomputer), it has many applications:
• driving 7-segment displays
• driving 14-segmentdisplays
• driving linear displays, e.g. pointer, bar graph
• static output of switch-functions
• digital to analogue converter, with external R-2R network
• extension of the number of outputs for microprocessors or microcomputers.
Data transmission is initiated by means of a burst of clock pulses (ClB), a data line enable signal
(DlEN) and the data signal (DATA). The bus control circuit distinguishes between interference and
valid data by checking word length (17 bits) and the leading zero. This allows different bus information to be supplied on the same bus lines for other circuits (e.g. SAA 1056 with 16 bits).
The last bit (bit 17) of the data word contains the information which of the two internal latches will .
be loaded. The input lOEX determines if the latched data of selected latches presented directly to
the outputs, or synchronized. with the data select signal DUP.
is
The output stages are n-p-n transistors with open collectors. The current capability is designed for the
requirements of duplex operation. Two of the outputs (08 and 016) are arranged for doubl~ current,
so that 2 x 2 segments can be connected in parallel.
OPERATION DESCRIPTION
Data inputs (OLEN, DATA)
The SAA1060 processes serially the 18-bit data words synchronized with the clock burst (ClB) and
applied to the data input DATA~ A command will be accepted only ·when the data line. enable input
(DlEN) is HIGH (see Fig. 3).
16 th bit
1 5t bit
Fig. 2 Organization of a data word.
Condition for 17th bit:
= load data latch B
1 = load data latch A
o
--
The loading of the accepted information in one of the data latches is done by the 19th clock pulse,
when DlEN is lOW.
2
l___
LED display/interface circuit
S_A_A_10_6_0_ _
load pulse
:::N
~-i-t--t---:II
DATA~~start-bitl
--I
I~
bit'
I
+
d,"wo,d
uu]
C==]
bit'6
bit'?
test leading zero
~M
7Z78908
Fig. 3 Pulse diagram of the 16-bit data transmission.
Each data word must start with a leading zero. The SAA 1060 checks the data word for the correct
length (18 bits) and also for the leading zero.
The actual data is switched directly to the appropriate outputs. For switching on a segment, a 'a' (LOW)
is necessary at the appropriate data bit.
Data selection input (DUP)
The logic states at input DUP determine which of the two latch contents can be found on the output.
a = latch A contents
1 = latch B contents
Load control input (LOEX)
Input LOEX determines the operation mode in which the device is able to work.
a = duplex mode, i.e. output synchronized with the duplex signal
1 = d.c. mode, i.e. output direct from the by DUP selected data latch.
When operating in duplex mode at 50 Hz, the time between two data words to be transmitted must
be> 21 ms.
--
3
SAA1060l~
__________________
°16
°4
'° 11
~5
°15
°10
LOEX
°3
OLEN
°6
VCC
VEE
OUP
°9
DATA
°2
CLB
°7
°12
VEE
°14
°1
°13
Os
~
________
~
7Z78906
Fig. 4 Pinning diagram.
RATINGS (VEE = 0)
Limiting values in accordance with the Absolute Maximum System (J EC 134)
Supply voltage range
Vce
Total power dissipation
=
I
Operating ambient tempe~atu re range
Storage temperature range
F·
I
I
I
I
4
Mav19791 (
-0,3 to + 7 V
max.
Tamb
T stg
900 mW
-20 to + aO °C
-25 to + 125°C
__
l___
LED display/interface circuit
S_A_A_10_6_0_ _
CHARACTERISTICS
VEE = 0; T amb = 25 oC; unless otherwise specified
VCC
V
symbol
min. typo
max.
conditions
Supply voltage
-
Vec
4
Supply current
5
ICC
-
60
Inputs DATA, CLB,
OLEN, LOEX
input voltage HI GH
input voltage LOW -
5
5
VIH
VIL
2
input current LOW
5
-IlL
maximum input frequency
5
fl
Input DUP
input voltage HIGH
input voltage LOW
5
5
VIH
VIL
input current HIGH
5
IIH
maximum input frequency
5
fl
-
5
VOH
VOL
-
-
5
-
-
16,8
0,5
5
10L
-
-
60
mA
5
IQL
-
20
40
rnA
5
5
VOH
VOL
-
-
16,8
0,5
V
V
5
10L
-
-
120
mA
5
10L
-
40
80
rnA
Outputs 01 to 07,
09 to 015
output voltage.HIGH
output voltage LOW
output current LOW
duplex mode
d.c. mode
Outputs 08 and 016 output voltage HI GH
output voltage LOW
output current LOW
duplex mode
d.c. mode
-
5
6
V
-
rnA
-
5
1
V
V
-
20
J1.A
50
-
kHz
0,8
-
-6
-
12
0,4
-
12
rnA
50
-
kHz
0,01
VI =0
V
V
V-
10H =0
10L =40mA
V
(
peak value at
sinusoidal voltage
10H=0
10L =80mA
(
peak value at
sinusoidal voltage
---
'I (
May 1979
5
DEVELOPMENT SAMPLE DATA
SAA1062
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
LCD DISPLAY/INTERFACE CIRCUIT
Features
•
•
•
•
•
•
•
Driving 7 to 20-segment displays.
Driving linear displays.
Serial to parallel decoder of digital signals.
Bus control for the selection of 18/21-bit words.
17/20-bit latch.
A.C. segment drive.
On-chip oscillator.
QUICK REFERENCE DATA
Supply voltage range
Operating ambient temperature range
4,2 to 6 V
VCC
Tamb
-20 to + 70 0C
Maximum input frequency
typo
Supply current
typo
12 mA
Output current (01 to 020)
>
60 mA
50 kHz
GENERAL DESCRIPTION
The SAA 1062 is designed to drive a Liquid Crystal Display (LCD) of a digital tuning system. It contains
a shift register with programmable length (18 or 21 bits), latches, both synchronized or static, exclusiveOR segment drivers (17 or 20 bits), an I.f. oscillator and a backplane driver for the LCD. The circuit is
designed to be driven by a 3 bus structure from a microprocessor and can also be used as a programmable 17 or 20 bits serial-to-parallel decoder. It is also capable of storing 60 bits of information.
PACKAGE OUTLINE
. 28-lead OIL; plastic (SOT-117).
SAA1062
L
CLB
a 20
OLEN
a 19
DATA
a 18
VCC
a 17
VEE
a 16
Cext
a 15
BLS
a 14
AC/EL
a 13
a1
a 12
a2
0 11 '
a3
11
18 a10
a4
12
17
09
05
13
16
08
06
14
15 0 7
7Z78899
Fig. 1 Pinning diagram.
----
2
May
19791 (
0,
°17
°3
°2
°'8
r-
°'9
o
°20
c
c..
iii'
"C
-
~
:i"
S
4-
I»
2
~.
C')
c
;::i:
D
C
2'
Q
EXCLUSIVE
OR
INPUT
~
'<
BACK
PLANE
DRIVER
LF
TRIANGLE
GENERATOR
CURRENT/
VOLTAGE
STABILIZER
LEVEL
DETECTOR
co
8
.......
co
CLB
DLEN DATA
BLS
AC/EL
Fig. 2 Block diagram.
Co)
-7 4
6
C ext
(j)
7Z7890l
»
»
o
0')
I\)
SAA1062
OPERATION DESCRIPTION
The input information for this device consists of a data bus with 18 or 21 bits words, an external clock
synchronized with the data bus and an enable signal. The organization of these signals is given in Fig. 3.
These signals are handled by the BUS CONTROL circuit in which the decision is made whether these
signals are valid for the device. It contains a leading zero detector (start condition of reception) and a
data-length control. Leading zero is detected when the data signal is LOW and the OLEN signal is HIGH,
during the first HIGH period of the clock signal. During the HIGH period of OLEN, the length control
determines if the clock signal consists of the programmed number of pulses (18 or 21). This last function permits the user to supply other information on the same Signal lines.
Furthermore the bus control prevents the device from accepting inferferences on the signal lines. While
leading zero is detected, the shift register is set and for a proper leading zero the following data is
shifted into this register. The an position of the first bit of the register is shifted into the last bit, if the
length of the data and the clock input are correct. Incorrect length of the information is detected by
checking the value of the last bit of the programmed register. If the data transmission has been accepted
properly, the bus control stage generates a valid pulse (LOL). This pulse enables the load control circuit
to load the contents of the register into the latch. On the first edge of the backplane driver signal 'AC
out E L in' following on this 'LOL' pulse, the new information ofthis latch is transferred to the output
driver which also contains a latch. In the static mode this transfer is done immediately on the LOL
pulse. With this ability it is possible to load the device with 20 bits and to transfer this data to the
segment outputs; the SR and latches will be reloaded by a second complete load procedure without an
, AC out' edge, and then another reload without a load enable clock pulse which makes the SR contents
20 bits, the latches 20 bits and the output latches 20 bits of information.
The I.f. oscillator consists of a triangle generator of the 1-21 principle. It only needs an external capacitor to fix the frequency. As both amplitude and current are temperature compensated, this frequency
is more or less independent of pn temperature. An internal switching signal of this generator is divided
by 4 to attain a symmetrical output for the backplane driver (pin 8) of nominal 60 Hz for an external
capacitor of 22 nF.
The backplane driver is able to drive a 40 bits display. When Cext (pin 6) is connected to ground or
V CC, the device acts as a synchronized or static slave. I n this case the backplane driver is switched-off
and pin 8 only acts as the 'E L in' input.
The bit length of the shift register is programmed with BLS (Bit Length Selector) (pin 7). If BL.S is
kept LOW the DATA bit length is 20; for' BLS open or HIGH a DATA bit length of 17 is selected.
---
4
_Mav19791(
OLEN
DATA
~
.-n
~
c
c..
.g.
-
i
~d.r:d
f'---J\.
3."
significant data
!:e
load enable clock pulse.
at
~
CLB
bit number:
output:
CO)
:::;.
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
°3
°2
°20 °19 °18 °17 °16 °15 014 °13 °12 °11 °10
7
17
13
12
11
10
9
15
8
16
14
°9
6
°8
5
°7
4
°6
bit number:
3
°5
' 2
°4
1
output:
°17 °16 °15 °14 °13 °12 °11 °10 °9
°7
°6
°5
°4
°3
°2
01 -
°8
CO)
} 20 bits
01
c
;:;..
S.R.
} 17 bits
load bit
S.R.
7Z78900
Fig. 3 Organization of 18 and 21 bits words; DATA = LOW means segment 'on'.
s:
!II
-<
-'
co
co
"""'
(j)
»
»
.-\.
0
0">
I\)
en
SAA1062
RATINGS (VEE =0)
Limiting.values in accordance with the Absolute Maximum System (lEC 134)
Supply voltage
Total power dissipation at T amb = '100 °C
derate linearly with 0,02 W/oC
Operating ambient temperature range
Storage temperature range
6 V
VCC
max.
Ptot
max.
Tarnb
T stg
-55 to + 125 °C
500 mW
-25 to + 125 0C
CHARACTERISTICS
VEE =.0; VCC = 5 V; Tamb = 25 oC; unless otherwise specified
typo
max.
5
12
6
VCC
4,2
ICC
-
Inputs CLB, OLEN, DATA, BLS
input voltage HIGH
input voltage LOW
VIH
VIL
maximum input frequency
Input Cext
input voltage HI GH
input voltage LOW
input current HIGH
input current LOW
-
V
V
-
50
-
kHz
VIH
VIL
4,4
-
-
V
V
IIH
IlL
-
-
Output Cext (oscillator mode)
oscillator frequency
fosc
120
Output stage backplane (AC/E L)
output current sink/source
10
2,4
Output 01 to Q20
output curre,nt sink/source
10
(
-
fl
2,7
1979~
V
inA
-
VIH
V,L
May
condition
1,6
-1
\
Input AC/E L (in slave mode)
input voltage HI G H
inpu~ voltage LOW
d.c. rest voltage between
pin 8 (AC/EL) and one of
the segment drivers:
segment 'on' situation
segment' off' situation
6
min.
Supply current
Supply voltjige
---
symbol
-
-
+0,8
0,4
-
180
-40
JlA
JlA
-
-
-
2,3
V
V
360
Hz .
-
-
rnA
60
-
-
JlA
-
-
200
25
25
mV
mV
static mode
sync. slave mode
C = 22 nF
l_____
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
S_A_A_10___7_0_ _
DISPLAY INTERFACE AND FREQUENCY COUNTER
15
decoder
control
DISP
FIN
GATE _
QRZ
ose
19
12
13
17
18
SAA1070
stop
TIMING PULSE
GENERATOR
14
16
OUP
7Z79488
wavelength control
Features
Fig. 1 Block diagram.
• 18~bit frequency counter, 4%-digit LED driver and decoder.
• Internal timing unit with an external 4 MHz quartz crystal.
• 16-bit comparator eliminating the influence of interferences and display flicker.
• Display test and blanking facilities.
• A wide range of i.f. offset frequencies programmable by the user.
QUICK REFERENCE DATA
Supply voltage range
Operating ambient temperature range
Vee
4,5 to 5,5 V
o to + 70 0e
Tamb
<
<
I nput frequency
Output current at V Q = 0,5 V
Supply current
typo
3,75 MHz
60-mA
90 mA
PACKAGE OUTLINE
28-lead 01 L; plastic (SOT-117).
'I
May 1979
SAA1070
l'----______- -
GENERAL DESCRIPTION
A frequency indicator system can be made with the SAA i 070 and the frequency divider SAA 1058.
It has the following features:
'
• A 4%-digit LED display driver. Action starts in duplex mode: the indicators are driven by half sinewave pulses, the two character groups are switched during the zero crossing of the duplex phases.
This will obtain minimum interference at correct exploitation of the terminals.
• Ar18-bit frequency counter with display decoder and indicator memory. The counter can be
preset in a wide range of programmed offset frequencies, so it is possible to obtain, independent
of each other, 15/24 different Lf. signals in the FM, S'w, MW and LW ranges.
• A timing unit drive~ by a 4 MHz quartz crystal on t,he chip.
• A 16-bit comparator for loading the measured frequencies. The frequency value in the display latch
will only. be changed when three successive counter values are different to the latch values. This
eliminates display flicker for interferences and reduces the sensibility.
• Latch loading; in this case the frequency counter and the prescaler are stopped and the last measured
frequency is displayed continuously.
.
• In FM operation choice of displaying received frequency or channel number.
• Display test and blanking facilities.
OPERATION DESCRIPTION
The timing for a measurement cycle is started at a positive-to-negative transition of input DUP (pin 16).
The internal timing unit generates pulses of different length in which the programmed Lf. signals will
be determined (see Tables 1 and 2). ·During this time the driver outputs a1 to a9 are internally switched
as inputs; the. driver outputs are blocked. The programming of a '1' or '0' is achieved by using or
omitting 22 knresistors between the a,Ppropriate output and pin 15 (a, F), or between these outputs
and + 2,5 V (see Fig. 4).
The counter is preset (parallel i.f. presetting) depending on the i.f. chosen and the mode of operation
(FM, SW, MW and LW, see Table 3). This is followed by serial offset; the counter then has a pulse train
applied via a gating circuit, the number of pulses also depends on the programmfng of a1 to 09 and
the mode of operation. The gating circuit releases input FIN (pin 12) for a defined time, in which the
applied pulse to FIN switches the counter.
A HIGH level is obtained at output GATE (pin 13) during this specified measuring time; after that the
16 most significant bits of the counter will be compared with the contents of the latch. If an unequal
content is detected a 2-bit comparator counter is incremented: an equal state of the comparator resets
this counter. As soon as the comparator counter is in position 3, i.e. after three successive different
counter values, the new counter contents will be transferred to the latch at the following p~sitive-to
negative transition of signal DUP. The latch value will be decoded for a 7-segment display and transferred to the LED outputs 01 to 015 via a duplex circuit. The LED segments have to be connected to
the display outputs via current-limiting resistors (as explained above).'
,
2
Mav19791C
SAA1070
Display interface and frequency counter
Table 1. Setting of Lf. offset frequencies
for FM operation.
Wavelength control: WLC = F.C.
pin number
27
24
23
20
offset
frequency
MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10,7000
10,6000
10,6125
10,6250
10,6375
10,6500
10,6625
10,6750
10,6875
10,7000
10,7125
10,7250
10,7375
10,7500
10,7625
10,7750
Table 2. Setting of i.f. offset frequencies
for AM operation.
Wavelength control: WLC =S.M L.
pin number
28
26
25
22
21
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
offset frequency
kHz
S
ML
460,00
448,75
450,00
451,25
452,50
453,75
455,00
456,25
457,50
456,25
457,50
458,75
460,00
461,25
462,50
463,75
465,00
463,75
465,00
466,25
467,50
468,75
470,00
471,25
472,50
460
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
o = no resistor.
1 = 22 kn resistor to + 2,5 V (see Fig. 4).
May 1979
3
SAA1Q70
l________-..,.----
OPERATION DESCRIPTION (continued)
The operation mode of the circuit depends on the state of the wavelength control inputs (pins 8 to 11);
see Table 3;
Table 3. Truth table of the WLC inputs.
operation mode
v.h.f. frequency (FM)
v.h.f. channel (FM)
short wave
medium wave
long wa\(e
display test
display blan~ing
display blanking
display blanking
display blanking
wavelength control inputs
F I c I
I ML.:
pin number
11
10
9
8
s
0
1
X
0
1
1
1
0
0
X
X
X
X
X
0
1
1
1
1
1
0
1
0
0
0
1
1
1
0
0
,1
1
0
1
1
1
X
0
o=0V
0
l' = +'5 V
1
X = state is immaterial
(ground)
The display position and resolution of the frequency measurement is given in Table 4.
Table 4.
'
operation mode
v.h.f. frequency (FM)
v.h.f. channel (FM) .6
short wave
medium/long wave
.6
display range (number of indicators)
min.
max.
4
3
4
2
3
2
5
0
O.
0
0
0
0
0
0
0
0
0
0
0
9
+
1
1
9
9
resolution
5
9
9
9
9
5,*
**
MHz
0,05 MHz
9
9
9
9
5
kHz
kHz
0,1 MHz
5,0 kHz
1,0 kHz
Limited to 109,30 MHz for a maximum input frequency of 3,75 MHz.
Limited to -64 for a maximum input frequency of 3,75 MHz.
One channel = 300 kHz; e.g. channel 02 = 87,6 MHz
The display frequency corresponds to the frequency to be measured, at an. input frequency fin at pin 12:
--
fm + foffset
fin =--32-in which: fin = input frequency,
f m = frequency to be measu red,
foffset = i.f. offset frequency programmed as is Tables 1 and 2.
4
l
. Display interface and frequency counter
(
(
VEE
°9A
°10
°SF
°11
°7A
°12
°6A
°13
°5F
°14
, °4F
°15
°3A
ML
°2A
SAA1070
)
S
Q
F
DISP
:>
e
ase
~
FIN
ORZ
J
1F
J
~
(
J
13
16
DUP
Vee 14
15
O,F
GATE
~
)
J
J
>
7Z78898
J
Fig. 2 Pinning diagram.
)
PINNING
14
1
Vee
VEE
Inputs
ML
S
9
S
10
F
11
e
12
16
DUP
17
ORZ
FIN
positive supply
negative supply (0 V, ground)
medium and long wave
short wave
) wavelength control; when connected to ground
FM
channel control when connected to ground; other functions can be obtained by
connecting more wavelength control inputs to ground simultaneously (see Table 3).
input for frequency to be measured
synchronization of the internal timing unit and selection of the character groups
(duplex input)
input for the quartz-crystal oscillator
May 1979
5
l_____
• _ __
SAA1Q70
PINNING (continued)
19
DISP
control input for mode of operation
open: comparator operates
grounded: stop display is obtained; the timing unit is stopped in position 20 and
cannot be started again by the duplex input (DUP); the last displayed value
remains stored ~n the latches and is driven to the output; the comparator counter
is reset; output GATE (pin 13) is LOW
at V cc: the comparator function is switched-off; the contents of the counter are
loaded into the latches every period 18 of the timing unit; the timing unit will
also be stopped at the beginning of period 17 independent of the state of the
comparator output; in that case the display rate will be higher
Inputs/outputs
The following notation is used for the LED driver outputs:
o
(3 f)
I
rl------~'
duplex
phase
~'--------~I
charact~r
segment
position
e.g. 1 (4a) means: on duplex input = 1; the' a' segment of the fourth digit is driven.
20
21
22
23,
24
25
26
27
28
01F
Q2A
Q3A
Q4F
Q5F
Q6A
Q7A
Q8F
09A
LED output 0 (3f); 1 (2f)
LED output 0 (3g);1 (2g)
LED output o (3e); 1 (2e)
LED output 0 (3d); 1 (2d)
LED output o (3c); 1 (2c)
LED output 0 (3b); 1 (2b)
LED output 0 (3a); 1 (2a)
LED output 0 (5g); 1 (4b)
LED output 0 (1d); 1 (4f)
i.f.
Lf.
i.f.
i.f.
i.f.
i.f.
i.f.
i.f.
i.f.
offset
offset
offset
offset
offset
offset
offset
offset
offset
input 1 for
input 1 for
input 2 for
input 2 for
input 3 for
input 3 for
input 4 for
input 4 for
input 5 for
FM
AM
AM
FM
FM
AM
AM
FM
AM
Outputs
6
2
QlO
3
4
5
6
7
15
Q11
Q12
Q13
Q14
015
QIF
13
GATE
18
OSC
LED output 0 (5a', 5d); 1 (4a)'
LED output 0 (5b, 5e); 1 (4c)
LED output 0 (5c, 5f); 1 (4d)
LED output 0 (1c); 1 (4g)
LED output 0 (1a, 1b); 1 (4e)
LED output 0 (3h, MHz indicator); 1 (kHz indicator)
i.f. offset control output; this output is set to 2,5 V at the beginning of a
measuring period; when programming resistors are connected to this pin, it must
also be connected to both phases of the LED anode voltages via diodes; this
prevents a segment being switched off by the programming resistors.
open collector output; counter is active when this pin is HIGH; also used to drive
th~ reset input of the divide by 32 prescaler (SAA 1058)
output for the quartz-crystal oscillator
(
(
:l
LJ
.J
L.
~
:(
f)
~
U
~
L.
)
.J
LJ
>
U
:)
l
Display interface and frequency counter
SAA1070
---------------------
RATINGS
Limitingval.ues in accordance with the Absolute Maximum System (IEC 134)
+7 V
Supply voltage range
V CC
Total power dissipation
Operating ambient temperature range
Ptot
T amb
-20 to + 80 0C
Storage temperature range
T stg
-25 to
-0,5 to
max.
900 mW
+ 125 0C
CHARACTERISTICS
VEE = 0; V CC = 5 V; T amb = 25 oC; unless otherwise specified
symbol
min.
typo
max.
5
5,5
Supply voltage
VCC
4,5
Supply current
ICC
-
90
Inputs ML, S, F, C
open voltage
Via
2,5
4,5
-
V
VIH
VIL
2,0
0
-
5,0
1,0
V
V
-IlL
30
-
300
p.A
VIH
V,L
1,0
-6,0
-
-
12,0
0,4
V
V
RIH
0,6
-
1,5
VIH
VIL
2
0
-
5
1
input voltage HIGH
input voltage LOW
input current LOW; VI L
=1V
Input DUP
input voltage HIGH
input voltage LOW
input resistance HIGH
Input FIN
input voltage HIGH
input voltage LOW
-
V
mA
kS1
V
V
input current HIGH
IIH
20
p.A
CI
-
-
input capacitance
-
4
pF
input frequency
fl
-
-
3,75
Inputs 0lF, 02A, 03A, 04F, 05F, 06A, 07Ai
°8F,09A
input voltage HIGH
MHz
VIH
1,8
-
12
open voltage (logic LOW)
Via
0,2
1,4
1,5
V
input current HIGH
rlH
10
20
30
p.A
programming resistor between input
and pin 15 (at 2,5 V for HIGH)
RIF
15
22
33
kS1
-
-
-
-
I.F. offset
accuracy; WLC = F.C.
accuracy; WLC = S.M.L.
supply sensitivity; WLC = F.C.
supply sensitivity; WLC = S.M.L.
-
±8
± 0,6
10
0,8
May 1979
V
kHz
kHz
kHz/V
kHz/V
7
SAA1070
l
'---------------------------------------------------
CHARACTERISTICS (continued)
Input DISP
open voltage HIGH
open voltage lOW ) note 1
input voltage lOW
input voltage HI G H
Outputs 01A, 02A, 03A, 04F, 05F,·06A, 07A,
08F, 09A, 0 13
output voltage HIGH
output voltage lOW; 10l = 40 rnA
output current lOW; note 2
Outputs 0 10, 0 11, 0 12, 0 14,015
output voltage HIGH
output voltage lOW; 10l = 80 rnA
output current LOW; note 2
Oscillator connections OSC, ORZ
frequency
input voltage HIGH; ORZ
input voltage LOW; ORZ
input resistance ORZ
,
symbol
min.
VOH
Val
Vil
VIH
0,6
0
-0,4
2s O
max.
-
0,8
0,4
V
V
0
0,4
5,0.,
V
V
-
12
0,5
V
V
60
rnA
-
12
0,5
V
V
120
rnA
MHz
-
-
-
VOH
VOL
-
10L
-
VOH
VOL
-
10L
-
-
f
-
4,0
-
2,6
-2,0
-
-
5,0
2,0
V
V
50
-
-
kn
5,0
pF
-
V
V
1,0
12
V
, VIH
Vil
RI
input capacitance ORZ
CI
open voltage ORZ
open voltage OSC
Via
Via
Output GATE
output voltage lOW; ,10l = 20 rnA
output voltage HIGH; 10H = 0
VOL
VOH
Output OIF
output voltage; conductive
output voltage; non-conductive
Vo
Vo
output resistance; conductive
output resistance; non-conductive
typo
RO
An
-
.
2,25
1,5
-
-
-
-
2,2
2,5
-
-
2,8
12
V
V
350
50
500
650
n
kn
-
-
V
Notes
1. When this pinJs 'left open it acts as an output at which the number of serial offset pulses for the
i.f. offset can be obtained.
2. Peak current for sinusoidal voltage.
8
l___
Display interface and frequency counter
S_A_A_10_7_0_ _
APPLICATION INFORMATION
Vee
R7
=
5V d.c.
10
R29
Ison
from
SW/MW/LW
local osc. --6---It--4-.....,......-----i:-"-i
from VHF --r--it--t-----1---i
local osc.
1..
FIN to
SAAI070
7Z79489
J\..
DUP from - - - - - - - _ - - - - - - - - '
display circuit
Fig_ 3 Pre-scaler circuit for the frequency measurement system; to be used in combination with Fig. 4.
May 1979
9
~~_,
_____S_A_A_10_7_0___
_______________________________
APPLICATION INFORMATION (continued)
,"-----------
04
~--~~~~--------~-----------------_r----~--~~~-~®
8 V a.c.
®
:o~:l~
BY206
(4.)
, C13
I1 F
IO.l
lN414B
BY206
ferrite
B0135
bead
C16 +
t-4---------@
1 mF
(15V)
C5V6
I
'
~"-"-"-"-"-------"-"-"--~
~FI~N-fr-om------~r------------------------------------~------~
SAA 1058
-==
......
=
-S-·ET-t-o-------~---------------------------------------------Q)
SAA1058
1\... OUP
~--------------------------------------------®
7Z79490
Fig. 4 Display drive circuit for the frequency measurement system; continued on next page (see also
Fig. 3).
l___
Display interface and frequency counter
S_A_A_10_7_0_ _
Q0--~~--------------------------~--------------~----------------~
~--~----------------~~--~~~------~----~-+------~----~
L....T",,:;:,,-r-.:;....J L..T-T-;-M-ir+-J L..;-;:..;:...;:..;;..r.:;.:;,;.J L..T-T-;-M-ir+-J
L..;";;";:';"';""~
LED
6
LE 0
7
,40 lines
GROUP 1 _
GROUP 0 -
'2f 29 2e. 2d 2c 2b 2a 4b 4f 4a 08 4c 09 4d 010 49
3f 39 3e 3d 3c 3b 3a 59 ld 5a 5d 5b 5e 5c 5f lc
06 4e
la lb
7 0;
6 30p
;;;~~:~-o I 0LOP 0I 0~l 0~ [11~ I~
@-i-::~
-c:::J--O-+-+-4
- c:::J--o--f-
22k!1 0-R38toR40
for 452kHz
20 21 22 23 24 25 26 27 28
~
15
~
lC').=========:::;-'iI
II H CORRECTION rvI.F. OFFSET
.A
L
h
Ir--D...LECJ..O-D...LEJ..R-&....
decoder
I
control
LED DRIVE
L)
LOAD
CONTROL
- ] COMPARATOR
11
DISPLAY
REGISTER
1
I
l' i't ;LJ
@~
~
~_p_:_~_~_1._(_'-:-~2: i1-'-1 1- C.....J0~~~~j r======~~>L,F~~~~~~i~~~T~:~~YJ'~
I
®
counter
control
____
SAA 1070
13
17
IClO
18
ld'PF
1-1
1-1
. .__
'IC:=:::::::;-;:::===I'
1'1
TIMING PULSE
G_E_N_EtR,...A_T_O_R_.....J1 ~
II
CJ
, 47 ;; 47
pF
pF
C9,
C18
68: ~O
pF
nF
I
~
WAVELENGTH
CONTROL
?
~
TRIM·
~ER "Cl1
I
I~
.--_ _ _ _4 16
4MHz
i.f.
offset
select
II.F. OFFSET
ROM
CHANNEL
" VHF
III SW
IV MW/LW
11
10 9
8
14
IV
HH
C8
III
O.lIlF
Vee
1Z79491
,May 1979
11
__________________________
~-Jl---S-A-A-5-00-0---
REMOTE CONTROL TRANSMITTER ENCODER
The SAA5000 is aMOS N-channel integrated circuit which provides the encoding and modulation
functions for the remote control of television receivers, including those equipped with teletext
and viewdata facilities.
It is intended for use with the SAA5010 remote control receiver decoder device. 32 commands are
provided which can be activated by either touch or switch controls.
Modulation may be selected for either infra-red or ultrasonic transmission systems.
QUICK REFERENCE DATA
Supply voltage
VDD
nom.
<
Supply current (Inactive, IDD + 116)
(Active, IDD)
6
20
25
typo
Number of commands
V
I1A
mA
32
Power-up
Automatic
Operating temperature range
-20 to +70
Tamb
°C
PACKAGE OUTLINE
18-I~ad D I L; plastic (SOT-102A)
10
18
Viewed from top
9
PINNING
1.
2.
!:)
VSS
Oscillator (C and R common connection)
Oscillator (R connection)
8.
9.
10'1
Keyboard (Matrix outputs)
14.
5.
6.
7.
11.
12.
13.
Keyboard (Matrix inputs)
15.
16.
17.
18.
Data output (Modulator drive)
Ultrasonic/Infra-red select
VDO
'I
September 1978
----
jl_~
___._SA_A_OO_O_o___
_________________________
DESCRIPTION
The method of data encoding provides a 24-bit code whiCh incorporates protection against false
responses at the decoder under adverse transmission path conditions.
The device automatically "powers up" when the first command is selected and reverts to the standby
mode when the operation has been completed. No adj~stments or critical components are required in
the peripheral circuitry.
HANDLING
Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally
safe, it is desirable to take normal precautions appropriat~ to handling MOS devices. (See MOS Handling
Notes).
RATINGS Limiting values in accordance with the Absolute Maximum System.
Voltages
min.
max.
-0.3
7.5
V
Oata output (Modulator drive) (pin 16)
-0.3
11.0
V
Input voltage - all inputs (pins 2 to 9 and 17)
-0.3
7.5
V
Output voltage - all outputs except pin 16 (pins 10 to 15).
:-0.3
7.5
V
Supply voltage (pin 18)
Voo
Temperatures
Storage temperature
T stg
Operating ambient temperature
Tamb
-20 to +125
o.C
-20 to +70
°C
Data output
Safe duration for short circuit to VOO
CHARACTERISTICS
min.
Supply voltage (pin 18)
Voo
typo
max.
7.0
4.5
V
The following characteristics apply at T amb = 25 oC, VOO = 6 V unless otherwise stated.
Supply current
20
p,A
25
35
mA
8.2
10
ms
Inactive, IDD + 116
Active,lDD
Oscillator (pins 2 and 3)
Operating bit period
(VOD = 4.5 to 7 V, C = LO nF,' R = 220 kn)
6.5
Keyboard. Matrix inputs (pins 4 to 9)
1.45 .
Switching threshold voltage
V
Keyboard. Matrix outputs (pins 10 to 15)
Output voltage. HIGH state
Voo = 4.5 V
VDD = 4.5 V
2
lout = -10 p,A
lout = -125p,A
. September 1978
r
4.3
2.25
V
V
l
Remote control transmitter encoder circuit
min.
typo
SAA5000
max.
Output voltage. LOW state
'VOO = 7.5 V
Short circuit current
0.48
V
0.95
mA
Data output (Modulator drive) (pin 16)
Low-state voltage (116 = 15 mAl
0.5
V
2
ps
Pull-down transition time
Infra-red operation
Low-state duration
1 :24
(Expressed as a ratio of bit period)
Ultrasonic operation
'0' bit low .state duration
(E~pressed
as a ratio of bit period)
1 :6
'1' bit low state duration
4:6
(Expressed as a ratio of bit period)
APPLICATION DATA
Data bit period and response time
The data bit period is controlled by choice of the two oscillator timing components connected to pins
2 and 3. Table 1 shows oscillator timing component values against data bit period.
Ultrasonic operation (Fig.2)
The system response time is approximately 27 x bit period. The minimum bit period is limited by
ultrasonic echo decay time encountered under operational conditions and for reliable operation a
nominal bit period of 8.2 ms is recommended. Transmitter supply current for the recommended circuit
shown in Fig. 2 is approximately 3 mA r.m.s., and is independent of the data bit period.
--
Infra-red operation (Fig.3)
The system response time is approximately 51.5 x bit period. The transmitter stage (recommended
circuit shown in Fig. 3) supply current varies with the bit period as shown in Table 1.
Table 1
Oscillator resistor = 220, kQ
Oscillator capacitor (pF)
Bit period
Transmitter
stage average
current
100. 120 150 180 220 270 330 390 470 560 680 820 1000 1200
(ms)
0.82
1.0
1.2
1.5
1.8
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
10
Infra-red
(mA)
23
19
16
13
11
8.7
7.0
5.8
4.9
4.1
3.4
2.8
2.3
1.9
Ultrasonic
(mA)
3
3
3
3
3
3
3
3
3
3
3
3
3
3
September 1978
3
I--_SA_A--.5_00_0_-,
l""'-,'______________
APPLICATION DATA (continued)
The function is quoted against the corresponding pin number
Pin No.
1.
Vss Ground - 0 V
2; 3
Oscillato~
timing components
A resistor and capacitor are required totime the oscillator, the frequency of which
determines the output data bit rate. The capacitor is connected between pins 1 and 2
and the resistor betwee':l pins 2 and 3.
4,5,6,
7,8,9
Keyboard Inputs (From keyboard matrix)
10, 11, 12, Keyboard Outputs (To keyboard matrix)
13, 14, 15 In the 'powered down' state these outputs assume approximately the battery +ve
f
potential. The required data code sequence (see Table 2) is selected by connecting a
chosen input to one of the outputs via the keyboard matrix. The application of the high
level from the output to the input causes the circuit to 'power-up', the oscillator starts and
a sequence of pulses appear on the output pins. As a result of the connection between the
selected input and output the chosen message code appears at the data output (pin 16).
When the connection is removed the circuit returns to the 'powered-down' state at the end
of the message sequence.
Input sensitivity is controlled by the choice of the input pull-down resistors. For maximum
sensitivity (i.e. for touch sensitive keyboards) 6.8 Mil resistors are recommended. Lower
values can be used (18 kil minimum) with low impedance keyqoard switches.
16.
Data output (Modulator drive)
This is an open-drain output capable of sinking current to Vss.ln the 'powered down'
state the output ishigh impedance. When the circuit is active the 24 bit data sequence
appears at this output to control an ultrasonic or infra-red transmitter. (See Fig. 5 for
details of the data pulse train). When infra-red mode is selected the 24 bit sequence is
transmitted twice with an extra pulse at the end of each sequence. This is to ensure the
correct reception of the code by the receiver.
17.
----
UItrason icll nfra-red sel ect
By connecting this pin to VSS the data output pulses are suitable for ultrasonic
transmission .. By connecting this pin to VOO the output pulses are suitable for infra-red
transmission. (See Fig. 4 for details of data pulses).
-
18.
VDD Positive Supply"
A 6 V dry cell battery may be used for operation in a portable unit. Four HPJ cells, or
equ ivai ent,are recommended.
4
September 1978
i(
l__
Remote control transmitter encoder circuit
S_A_A_50_0_0_ _
Peripheral circuitry
Oscillator
components
10 11 12 13 14 15 16 ·17 1B
Ultrasonic /
L---~--t---1nlnfra - red
select
Tx
stage
T
6V
I
I
--L
(nom)
6 x 6.BMQ for touch controls
6 x 33kO for switches
Reversed
battery
protection
---
D793~a
Fig.1
1(
September 1978
5
__-S-A-A-.5-00-0---Jl-____________________
----~--
APPLICATION CIRCUITS
Ultrasonic Transmitter
Keypad
18
17
118 pins)
2
16
07928
Fig.2
Infra-red Transmitter
a.------~~----~~-----.----~--~--------~--------.-----n+6V
C2
Modulation -+-~_.I-~~
signal from
330)JF
lOV
I
SAASOOO
(pin161
--
D7929a
Fig.3
6
s=ber 19781 (
r
a=-
-lJ _____
.-J.ow
0%
16.6% Low state
j4-- duration
~
1=
-1
I
o=-n
bit period
-~_~ _~o~_state_
I
Low state
0%
duration---.t ~
Infrared
8.~
~.
2
;:;:
100%
I
1=
~
(l)
l[-
I
~
r+
0;
:::I
~
20.6%
r+
:::I
I
j 4 - - Operating
~
8:::I
3
100%
I
I
period
I
66.6%
: 4%
(l)
3
L_
I
0%
::D
Output (pin 16)
with pin 17
connected to Vss
I
I
I
1~
100%
voltage
I '
Ultrasonics
state_L_
.Next bit
voltage
I
U____lII
I
70.6%
output pin 16
with pin 17
connected to VOD
100%
0=
Last bit
of 24 bit
sequence
en
(l)
"0
at
3
C"
~
(0
.....
00
*
Extra pulse
for receiver
F/ F phase change
I
1
en
=
):>
Fig.4 Modulation output pulse
07936
""
187.471
1111111
.t
Next 24·bit
•
sequence
»
8
o
lfunf
co
CJ)
»
»
en
CD
'0
S
3
I Finish
,activation
~ Start
activation
~
r
co
'"
00
Transmisson
/
,
l
R~N
/
/
/
/
SEQ~ENCE
~I
time
1
079350
I
"-1
SEQUxE~CE
[W
SEQUJ
-==-- -- -- ---
--
~~~
/
START
CODE
MESSAGE
I
X'
Transmission
~~~~
time
SEQUyE NCE
~~~~
COMPLEMENTED
START
CODE
I
1-
SEQUI
-- --
COMPLEMENTED
MESSAGE
X
I
~-~
Operating bit period
Infra-red
I " III
,-nfur III 1linin 1III II I Ilf r III I IIII TT-TI1H I
Fig.5 Encoded data format (example: code 18)
See Fi'g. 4 for details of output pulses.
~
l__
Remote control transmitter encoder circuit
S_A_A_50_0_0_ _
Transmitter message code
Table 2
Binary code
Binary code
Key No.
Key No.
Bl
B2
B3
B4
B5
17
0
0
0
0
1
0
18
1
0
a
a
1
0
0
19
0
1
a
0
1
0
0
0
20
1
1
a
0
1
0
1
0
0
21
0
0
1
0
1
1
0
1
0
0
22
1
0
1
0
1
7
0
1
1
0
0
23
0
1
1
0
1
8
1
1
1
0
0
24
1
1
1
0
1
9
0
0
0
1
0
25
0
0
0
1
1
10
1
0
0
1
0
26
1
0
0
1
1
11
0
1
0
1
0
27
0
1
0
1
1
12
1
1
0
1
0
28
1
1
0
1
1
131
0
0
1
1
0
29
0
0
1
1
1
14
1
0
1
1
0
30
1
0
1
1
1
15
0
1
1
1
0
31
0
1
1
1
16
1
1
1
1
0
32
1
1
1
1
B3 B4
Bl
B2
B5
J
0
0
0
0
0
2
1
0
0
0
3
0
1
0
4
1
1
5
0
6
I
I
1
-
1
(september 1978
9
__________
~----------------jl---S-A-A-5-01-0----
REMOTE CONTROL'RECEIVER DECODER
The SAA5010 is aMOS N-channel integrated circuit which provides the receiver decoding function for
the' remote control of television receivers.
The SAA5010 is a 24-lead device for the control of television receivers incorporating stepable tuning
selector systems and including those equipped with teletext and viewdata facilities. It is suitable for use
either in ultrasonic or infra-red transmission systems and is intended for use with the SAA5000 transmitter encoder integrated circuit. The SAA5010 is also suitable for direct connectio'n to the SAA5040
and the SAA5050 teletext decoder circuits. Op~ration with the digital channel selection system (OICS)
is also possible.
QUICK REFERENCE OAT A
Supply voltage
Digital
Analogue
VD01
V002
nom.
nom.
5
12
V
V
1001
1002
typo
typo
20
10
mA
mA
Supply current
~igital
Analogue
Operating temperature range
-20 to +70
Tamb
°C
PACKAGE OUTLINE
24-lead 01 L; plastic (SOT-101 A)
Viewed from top
12
---
PINN!NG
1- VSS
2 - Local reset
3 - Step
4 - Clear
5 - Data out
6 - On/standby
7 - OLIM
8- OLEN
9 - Mute
10 - Analogue 1
11 - Analogue 2
12 - Analogue rate of change control
13 - V002
14 - Analogue 3
15 - Analogue 4
16 - Message received indicator
17 - Picture on sense
18 - 'Oscillator (R connection)
19 - Oscillator (C and R common connection)
20 - Teledata modes inhibit
21 - Clock out
22 - Data input
23 - Data input type selector
24 - VDD1
Ir
Augun 1978
__
~S_
»
~
o
l>
c:
(Q
li
....
co
"-J
00
ODD FIELD
DS06l.
(620)
(621)
(622)
307
308
309
Line sync pulses (4.66)J sec)
I
(623)
(524)
(625)
310
311
312
~2.5
lInes
~14
2
.14I
I.
IFive equalising pulses I
Occur at beginning of
I
2.33)Js long
I
each line
I
+ lOOns
-
I
2.5 lines
Five
+ lOOns
-
I ,
I
I
I
I
308
309
EVEN FIELD
I
L
310
311
312
8
-+I
equalising pulsesl
Line sync
pulses
4.55)Js long
2.33)Js long
I -+ lOOns
I
I
I
I
I~'---'~'---'~
307
7
5
I
2.5 lines
I Five
broad pulses
27.33)JS long
5
4
3
313
(314.)
Initiated at end of line 310 for
2
3
4
5
6
7
(315)
(316)
(317)
(31B)
(319)
(320)
even
field and at
Fig. 2 After hours sync waveforms (AHS)
end
of
line
309~ for
odd field
~
CD
(jj
~
ro+
ro+
3'
LINE RATE (ps)
60
0
I
Fl
5'
(C
I..
I
20
23
I
:
-
1
1
RACK
1
30
-- -
I
Display period
-f.continuous
I
CBB
45
I
I
Ii:
I
I
~
55 56.5
60
I
I
I
I
I -
I
50
I
I
I
I
1
1
40
1
- I - -1- -
--~----~--~--~
3~
I
I
- - - -l - ---J.
n
~
Q)
5'
~.
n
c
;:;:
I
I
LOSE
C:LR
PL
FIELD RATE (Line No,s)
595 600 605 610 615 620 625 5 10
282 287 292 297 302 307 312 1 I
DEW
I
l>
c
(C
c
1
RAM address
1-....t--+-+--+--+-.....J
I I
1
1
I
I
1r,- r
I
~
15 20 25 30 35 40 4S 50 55 60 65 70
I II
I
I
1-'_1 1 I
I I
I
I
I
\ I
1
1
co
High impedance (HIE connected to DEW)
-....J
CD
U)
. D80650
»
»
(j1
Fig.3 SAA5020 Output waveforms
co
1111111
§
_____________________________jl___
S_A_A_5_03_0___
TELETEXT VIDEO PROCESSOR
The SAA5030 is a monlithic bipolar integrated circuit used for teletext video processing. It is one of a
package of four circuits to be used in teletext TV data systems. The SAA5030 extracts data and data
clock information from the television composite video signal and feeds this to the Acquisition and
Control circuit SAA5040. A 6 MHz crystal controlled phase locked oscillator is incorporated which
drives the Timing Chain circuit SAA5020. An adaptive sync separator is also provided which derives
line and field sync pulses from the input video in order to synchronise the timing chain.
QUICK REFERENCE DATA
Supply voltage
Vsupply
nom
Supply current at Vsupply = 12 V
Isupply
typ
·110
Video input amplitude (sync-white)
V16video(p-p)
nom
2.4
V
V16teletext(p-p} nom
nom
V16sync(p-p}
1.1
V
Teletext data input amplitude
Sync ampl itude
Operating temperature range
12
0.7
-20 to +70
Tamb
V
mA
V
°C
PACKAGE OUTLINE
24-lead 01 L; plastic (SOT-101 with heat spreader)
24
Viewed from top
12
PINNING
1.
2.
3.
4.
5.
6.
7.
8.}
9.
10.
11.
12.
Signal presence time constant components.
Line reset time constant
Fast line reset output (FLR)
Ground (OV)
Sandcastle input (PL and CBB)
6 MHz output (F6)
Phase detector time constant components
6 MHz crystal
Picture on input (PO)
After hours sync input (AHS)
Sync output to TV
13.
14.
15.
16.
17.
18 ..
19.
20.
21.
22.
23. }
24.
'Field sync output (FS)
Field sync separator timing.
Sync separator capacitor
Composite video input
Supply voltage (+ve)
Clock output (F7)
Data output
Clock phase adjustment
Clock regenerator coi I
Clock pulse timing capacitor
Peak detector capacitors
~
August 1978
l____
SAA5030
RATINGS Limiting values in accordance with the Absolute Maximum System.
Voltages
Supply voltage
V 17-4
Vsupply
max.
13.2
V
Input voltages
V5-4
Yin
max.
9.0
V
Vl0-4
Vin
max.
Yin
max.
Vsupply
7.5
V
t.b.f.
W
-20 to +125
oC
-20 to +70
oC
V11-4
Dissipation
V
Temperatures
Storage temperature
T stg
Operating ambient temperature
Tamb
CHARACTERISTICS (At T amb = 25 oC, Vsupply = 12 V and with external componen,ts as shown in
Fig.l unless otherwise stated)
Supply voltage
V17~4
Vsupply
Supply current (Vsupply = 12.0 V)
min.
typo
max.
10.S
12.0
13.2
Isupply
110
V 16 video(p-p) 2.0
Zs
2.4
Source impedance, f = 100 kHz
Sync ampl itude
V16 sync{p-p) 0.07
V
mA
Video input and sync separator
Video input amplitude (sync to white) Fig.2
Delay through sync separator
0.7
3.0
V
250
n
1.0
0.5
Delay between field sync datum at pin 12
and the leading edge of separated field
sync at pin 13 (Note 1, Fig.3)
32
48
V
p.s
62
p.s
Field sync output
. V out (low) at 113 = +20 p.A
V out (high) at 113 =-100 p.A
----
2
August 1978
r
0.5
V13L
V13H
2.4
V
V
l__
Teletext video processor circuit
S_A_A_5_03_0_ _
Crystal controlled phase-locked oscillator
Measured using a crystal with the following specification e.g. catalogue no. 4322 14303241
C1 = 27.5 fF (typ)
Co = 6.8 pF
(typ)
CL = 20 pF
Trimability (CL increased to 30 pF)
> 750 Hz
Fundamental ESR
<50n
min.
F6
Frequency
typo
max.
6.0
MHz
Holding range
1.5
3.0
kHz
Catching range
1.5
3.0
kHz
0.3
mV/ns
Control sensitivity of phase
detector measured as voltage
at pin 7 with respect to phase
difference between separated
syncs and phase lock pulse Pi.
Control sensitivity of oscillator
measured as change in 6 MHz
phase shift from pin 8 to pin 9
with respect to voltage at pin 7
Gain of sustaining amplifier, V9-8
measured with input voltage of
100 mV(p-p) and phase detector
immobilised
2
deg/mV
2.5
Output voltage of 6 MHz signal at
pin 6, measured into 20 pF load
capacitance; peak-to-peak value
V/V
V
5.5
Output rise and fall times at pin 6
into 20 pF load
30
ns
Data slicer and clock regenerator
Teletext data input amplitude, pin 16
(Note 2, Fig. 2); peak-to-peak value
Data input amplitude at pin 16 required
to enable amplitude gate flip-flop (peak-to-peak value)
1.1
V
0.46
V
Attack rate, mec;lsured at pins 23 and 24
with a step to pin 16
Positive
Negative
Decay rate, measured at pins 23 and 24
with a step input to pin 16
Width of clock coil drive pulses from
pin 21 when clock amplitude is not being
controlled (Note 3)
V/p.s
V/p.s
15
9
48
100
40
I
144
---
mV/p.s
ns
March 1979
3
SAA5030
l
Data sli~r and clock rEigenerator (continued)
Clock hangover measured at pin 18
as the time .the .clock coil continues
ringing after the end of data (Note 4)
min.
typo
Clock
Periods
20
Data and clock output voltages at pins
18 and 19 measured with 20 pF load
capacitance; peak-to-peak value
5.5
Output rise and fall times at pins
18 and 19 into 20 pF loads
Input voltage for energising clock phase
setting circuit, pin 10
max.
V
30
10
ns
V
Sa,ndcastle input
Sandcastle detector thresholds, pin 5
Phase lock pulse (PL) on
2
V
3
Phase lock pulse off
Blanking pulse (CBB) on
4.5
V
V
5.5
Blanking pulse off
V
Dual polarity sync buffer
After hours sync (AHS) pulse input pin 11
Threshold for AHS active
1.0
V
Threshold for AHS off
2.0
V
2·9
V
Picture on (PO) input, pin 10
Threshold for PO active
1.0
Threshold for PO off
V
Sync output, pin 12
AHS output with pin 10< 1 V (Note 5); peak-to-peak value
0.7
Composite sync output with pin 10
> 2 V (Notes 5 and 6); peak-to-peak value
0.7
1.0
3
Output current
-~
V
V
mA
Line reset and signal presence detectors
~
Schmitt trigger threshold on pin 2 to inhibit
line reset output at pin 3 (syncs coincident)
6.T
Schmitt trigger threshold on pin 2 to permit·
line re,set output at pin 3 (syncs non-coincident)_
7.8
Line reset output V out (low) at 13 == +20 p.A
Line reset output V out (high) at 13 = -100 p.A
Signal presence Schmitt trigger threshold on
pin 2 below which the circuit accepts the
input signal
Signal presence Schmitt trigger threshold on pin 2
above which the input signal is rejected
4
August 1978
(
V
V
0.5
2.4
V
V
6.0
V
6.3
V
Teletext video processor circuit
l__
S_A_A_5_03_0_ _
Notes
1. This is measured with the dual polarity buffer external resistor connected to give negative going
syncs. The measurement is made after adjustment of the potential divider at pin 14 for optimum
delay.
2. The teletext data input contains binary elements as a two level NRZ signal shaped by a raised
cosine filter. The bit rate is 6.9375 M bit/s. The use of odd parity for the 8-bit bytes ensures that
there are neve~ more than 14 bit periods between each data transition.
3. This is measured by replacing the clock coil with a small value resistor.
4. This must be measured with the clock coil tuned and using a clock-cracker signal into pin 16. The
clock-cracker is a teletext waveform consisting of only one data transition in each byte.
5. With the external resistor connected to the ground rai I, syncs are positive going centred on +2.3 V.
With the resistor connected to the supply rail, syncs are negative going centred on +9.7 V.
6. When composite sync is being delivered, the level is substantially the same as that at the video
input.
APPLICATION DATA
The function is quoted against the corresponding pin number
Pin No.
1. Signal presence time constant
A capacitor and a resistor connected in parallel between this pin and supply determine the delay
in operation of the signal presence detector.
2.
Line reset time constant
A capacitor between this pin and supply integrates current pulses from the coincidence detector;
the resultant level is used to determine whether to allow F LR pulses (see pin 3).
3. Fast line reset output (FLR)
Positive-going sync pulses are produced at this output if the coincidence detector shows no
coincidence between the syncs separated from the incoming video and the CBB waveform from
the timing chain circuit SAA5020. These pulses are sent to the timing chain circuit and are used to
reset its counters, so as to effect rapid lock-up of the phase locked loop.
.
4. Ground OV
5. Sandcastle input (PL and CBB)
This input accepts a sandcastle waveform which is formed from PL and eBB from the timing
chain SAA5020. PL is obtained by slicing the waveform at 2.5 V, and this, together with separated
sync, are inputs to the phase detector which forms part of the phase locked loop. When the loop
has locked up, the edges of PL are nominally 2 p.s before and 2 p.s after the leading edge of
separated l.ine syncs.
eBB is obtained by slicing the waveform at 5 V, and is used to prevent the data slicer being offset
by the colour burst.
6. 6 MHz output (F6)
This is the output of the crystal oscillator (see pins 8 and 9), and is taken to the timing chain
Circuit SAA5020 via a series capacitor.
7. Phase detector time constant
The integrating components for the phase detector of the phase locked loop are connected
between this pin and supply.
August 1978
5
SAA5030
L____
~ _~_
APPLICATION DATA (continued)
8,9 6 MHz crystal
A 6 MHz crystal in series with a trimmer capacitor is connected between these pins. It forms part
of an oscillator whose frequency is controlled by the voltage on pin 7, which forms part of the
phase locked loop.
10. Picture on input (PO)
The PO signal from the acql,.lisition and control circuit SAA5040 is fed to this input and is used to
determine whether the input video (pin 16) or the AHS waveform (pin 11) appears at pin 12.
11. After hours sync (AHS)
A composite sync waveform AHS is generated in the timing chain circuit SAA5020 and is used to
synchronise the TV (see pin 10).
12. Sync outputto TV
Either the input video or AHS is available at this output dependent on whether the PO signal is
high or low. In addition either signal may be positive-going or negative-going, dependent on
whether the load resistor at this output is connected to ground or supply.
13. Field sync output (FS)
A pulse, derived 'from the input video by the field sync-separator, which is used to reset the line
counter in the timing chain circuit SAA5020.
14. Field sync separator timing
A capacitor and adjusting network is connected to this pin and forms the integrator of the field
sync separator.
15. Sync separator capacitor,
A capacitor connected to this pin forms part of the adaptive sync separator.
16. Composite video input
The composite video is fed to this input via a coupling capacitor.
17. Supply voltage + 12 V
18. Clock output
The regenerated clock, after extraction from the teletext data, is fed out to the acquisition and
. control circuit SAA5040 via a series capacitor.
19. Data output
The teletext data is sliced off the video waveform, squared up and latched within the SAA5030.
The latched output is fed to the acquisition and control circuit SAA5040 via a series capacitor.
- . 20~ Clock decoupling
A 1 nF capacitor between pin 20 and ground is required for clock decoupling.
21. Clock regenerator coil
A high-Q parallel tuned circuit is connected between this pin and an external potential divider.
The coil is part of the clock regeneration circuit (see pin 22).
6
March 1979
r
Teletext video processor circuit
l__
S_A_A_5_03_0_ _
22.
Clock pulse timing capacitor
Short pulses are derived from both edges of data with the aid of a capacitor connected to this
pin. The resulting pulses are fed, as a current, into the clock coil connected to pin 21.
Resulting oscillations are limited and taken to the acquisition and control circuit SAA5040 via
pin 18.
23,24 Peak detector capacitors
The teletext data is sliced with an automatic data slicer whose slicing level is the mid-point of
two peak detectors working on the video. Storage capacitors are connected to these pins for
the negative and positive peak detectors.
August 1978
7
JL. . . ______~'__________________
_ _S_'A_A_5_03_0_'__
To TAC
~
____
~A~--
Data
+12V
Field sync .toIIC.
_ __ _
Clock
~
1.5
kn
lkn.@1OJ.lHl0nF
----
Composite
sync to TV
J1flJL
68pF
r 1
10J.lF
Line
Reset
to TIC
D8109b
I ~ Ii
u
frQm
TIC
"---y---J
T
April1979~(
t
'"
lnF
6MHz
to TIC
Fig.1 Peripheral circuit.
s·
: : (1. 5kn, al.ternativ~
~ for negatIve sync
PO
from
TAC
AHS
from TIC
l__
Teletext video processor circuit
S_A_A_5_03_0_ _
-- -
-
--- -
----- -
-
-
-- -
-
Zero carrier 3V
- - - - Peak white 2.4V
r - - - - - - - Peak teletext 1.82V
r---*------Black
----------------------__ Sync
O.72V
OV
081100
Fig. 2 Part of teletext line, with burst, showing nominal levels.
--j
~
1
2.35)..1s.
equalising
pulse
32)Js
I
"'"--------'n---...n_rL
Field sync
datum
t
Broad pulse
separation 4.7)Js
t .
081110
r-
.
Leading edge of field
sync pulse
Fig. 3 Detail of idealised composite sync waveform.
August 1978
9
~___________________________jl___S~A_A_5_0_~___
TELETEXT ACQUISITION AND CONTROL CIRCUIT
The SAA5040 is an MOS N-channel integrated circuit which performs the control, data acquisition and
data routing functions of the teletext system.
The SAA5040 is a 28-lead device which receives serial teletext data from the SAA5030 video processor
and data from the remote control system e.g. SAA5010. The SAA5040 selects the required page
information and feeds it in parallel form to the teletext page memory.
The SAA5040 works in conjunction with the SAA5020 Timing Chain and the SAA5050 Character
Generator.
The circuit is designed in accordance with the September 1976 Broadcast Teletext specification
published by BBC/IBA/BREMA.
QUICK REFERENCE DATA
Voo
nom.
Supply current
IDD
typo
Operating ambient temperature
Tamb
Supply voltage
5
80
-20 to +70
V
mA
°C
PACKAGE OUTLINE
28-lead DI L; plastic (SOT-117)
15
28
Viewed from top
14
Pinning: see next page
I
August 1978
PINNING
1: VSS
2. F7 Data
3. F7 Clock
15. Write O.K. (WOK)
}
teletext from SAA5030
4. Not connected *
5. DUM
6. DATA
}
16. . Data out to memory (D 7)
17. Data out to memory (D6)
18. Data out to memory (D5)
Control from SAA5010
19. Data out to memory (D4)
20. Data out to memory (D3)
7. Data entry window (DEW)
-21. Data out to memory (D2)
8. Picture on output (PO)
22. Data out to memory (01)
9. Display enable output (DE)
10. 8ig character select (BCS)
23. Address out to memory (A4)
24. Address out to memory (A3)
11. Top/bottom (f/B)
25. Address out to memory (A2)
12. General line reset (GLR)
26. Address out to memory (A1)
13. 1 MHz Input (F1)
27. Address out to memory (AO)
14. VDD
28. Write address clock (WACK)
DESCRIPTION
The circuit consists of two main sections.
a)
Data Acquisition
The basic input to this section is the serial teletext data stream (F7 Data} from the Video
Processor Circuit SAA5030. This is clocked by a 6.9375 MHz clock also from the SAA5030.
The incoming data stream is processed and sorted so that the page of data selected by the u~er
is written as 7 bit parallel words into the system memory. Hamming and parity checks are
performed on the incoming data to reduce errors. Provision is also made to process the control
. bits in the page header.
b)
Contr:ol Section
The basic input to this section is the 7 bit serial data from the Remote Control Decoder SAA501.0.
This is clocked by the DUM signal.
The remote control commands are decoded and the control func.tions are stored.
See Table 1 for full details Of the remote control commands used in the SAA5040. The control
section can also write data into the page memory independently of the data acquisition section~
This gives an on screen display of certain user-selected functions, e.g. page number and programme
name.
The data and address outputs to the system memory are set to high impedance state if certain
remote control commands are received (e.g. viewdata mode). This is to allow another circuit to
access the memory using the same address and data lines. The address lines are also high impedance
while theSAA5040 is not writing into the memory.
---
* This pin must be connected to VSS for ceramic packages.
2
August 1978
(
l__
Teletext acquisition and control circuit
S_A_A_5_04_0_ _
HANDLING
Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally
safe, it is desirable to take normal precautions appropriate to handling MOS devices (see MOS Handling
Notes).
RATINGS Limiting values in accordance with the Absolute Maximum System.
Voltages (with respect to pin 1)
Supply voltage (pin 14)
VOO
Input voltage All inputs
Output voltage (pin 8)
All other outputs
min.
max.
-0.3
7.5
V
-0.3
-0.3
7.5
13.2
V
-0.3
7.5
V
V
Temperatures
Storage temperature
T stg
Operating ambient temperature
Tamb
-20 to +125
-20 to +70
oc
oC
CHARACTERISTICS
min.
typo
max.
Supply voltage
4.5
VOO (pin 14)
5.5
V
The following characteristics apply at T amb = 25 °C and VOO = 5 V unless otherwise stated.
Supply current
80
100
120
mA
5.5
V
Inputs
F7 Data (pin 2), F7 Clock (pin 3)
Input voltage; HIGH
VIH
Input voltage; LOW Note 1
VIL
0.5
V
Rise time
Fall time
tr
30
30
ns
ns
7
pF
}
Note 2
Input resistance
Input capacitance
3.5
tf
5
Mil
August 1978
3
Jl
SAA5040
CHARACTERISTICS (continued)
F1 (pin 13)
min.
typo
max.
Input voltage; HIGH
VIH
2.4
Input voltage; LOW
VIL
0
Rise time
tr
50
ns
tf
30
ns
Fall time
Input
}
Note3
capa~itance
Input leakage current (Vin = 0 to 5.5 V)
VDD
V
0~6
V
7
pF
10
IlA
VDD
0.8
V
7
pF
10
IlA
0.5
V
VDD
V
10
IlS
7
IlS
pF
-500
IlA
All other in~uts
DUM (pin 5), DATA (pin 6), DEW (pin 7), GLR (pin 12)
Input voltage; HIGH
VIH
2.0
Input voltage; LOW
VIL
0
Input capacitance
Input leakage current (Vin = 0 to 5.5 V)
V
Outputs
DE (pin 9), BCS (pin 10), TIB (pin 11) (With internal pull-up to VDD)
Output voltage; LOW (JOL = 200 IlA)
Output voltage; HIG H
Output voltage rise time
Output voltage fall time
VOL
0
IOH - -50.A for p;n ~ }
IOH == -30 IlA for pin 10 VOH
IOH == -20 IlA for pin 11
2.4
}
CL = 40 pF
tr
tf
Output capacitance
Output current with output in HIGH state
(V out = 0.5 V)
lout
-50
PO (pin 8) (With internal pull-up to VDol
0.5.
V
VDD
10
V
IlS
7
pF
..,..50
-500
Il A
0.5
V
VOO
100
ns
10
IlA
7
pF:
Output voltage; LOW (I0L = 140 IlAI
VOL
0
Output voltage; HIGH (lOH = -50 IlA)
VOH
2.4
Output rise and fall time (CL = 40 pF) (Note 3)
t r , tf
qutput capacitance
Output current with output in H IG H state
(V out == 0.5 VI
lout
01 to 07 (pins 16 to 22) (3-state)
Output voltage; LOW (lOL = 1001lA)
VOL
0
Output voltage; HIGH (JOH = -100 IlA)
VOH
2.4
Output rise and fall time (CL = 40 pF) (Note 3)
t r, tf
Leakage current in 'off' state (Vout = 0 to 5.5 V)
Output capacitance
4
August 1978
(
-10
V
l
Teletext acquisition and control circuit
WOK (pin 15) (3-state with internal pull-up to VDD)
= 400J.LA)
(lOH = -200 J.LA)
min.
Output voltage; LOW (JOL
VOL
0
Output voltage; HIGH
VOH
2.4
Output voltage rise time }
.
(C = 80 pF) (Note 3)
Output voltage fall tIme
L
typo
SAA5040
max.
0.5
V
VDD
V
tr
50
ns
tf
100
ns
Output current with 3-state 'off' (V out = 0.5 V)
-80
Output capacitance
-500
J.LA
7
pF
WACK (pin 28) (3':state)
Output voltage; LOW (lOL
= 1.6 mAl
= -100 J.LA)
Output voltage; HIGH (lOH
Output voltage rise time }
,.
(C = 40 pF) (Note 3)
Output voltage fall tIme
L
Leakage current in 'off' state (Vout
Output capacitance
Ao to A2
VOL
0
VOH
2.4
0.5
tr
tf
= 0 to 5.5 V)
-10
V
VDD
V
50
ns
300
ns
10
J.LA
7
pF
(pins 25 to 27 (3-state)
= 200 J.LA)
= -200 J.LA)
Output rise and fall time (CL = 90 pF) (Note 3)
Leakage current in 'off state (V out = 0 to 5.5 V)
Output ~oltage; LOW (JOL
VOL
0
Output voltage; HIG H (JOH
VOH
2.4
t r , tf
-10
Output capacitance
0.5
V
VDD
300
ns
10
J.LA
7
pF
V
A3 and A4 (pins 23 and 24) (3-statel
Output voltage; LOW (JOL = 1.6 mAl
= -200 J.LA)
Output rise and fall time (CL = 40 pF) (Note 3)
Leakage current in 'off' state (V out = 0 to 5.5 V)
Output voltage; HIGH (lOH
VOL
0
VOH
2.4
0.5
VDD
300
t r , tf
-10
Output capacitance
V
V
ns
10
J.LA
7
pF
TIMING CHARACTERISTICS
Teletext Data and Clock (F7 Data + F7 Clock)
(Note 2 and figure 1)
F7 Clock cycle time
TT tc
"F7 Clock duty cycle (HIGH to LOW)
144
ns
70
30
%
F7Clock to data set-up time"
TTtds
60
ns
F7 Clock to data hold time
TTtdh
40
ns
August 1978
5
_)l___~_~____________________
_""""--S_A_A50...........-.40........
·
TIMING· CHARACTERISTICS (continued)
min.
Control DATA and Clock (DATA
typo
max.
+ DUM)
(Note 3 and figure 2)
16
J.lS
DUM duty cycle
50 .
%
DUM to DATA set-up time
tds
14
J.lS
DUM to DATA hold time
tdh
14
J.lS
DUM cycle ,time
tc
Writing Teletext data into Memory during DEW
(Figure 3)
1150
WACK cycle time
WACK rising edge to WOK falling edge
e~ge
ns
tAWW
250
450
355
ns
ns
tWRW
220
WOK pulse width
tWFD
300
ns
Data output set-up time
tDW
330
ns
Data output hold time
tDH
0
ns
ns
ns
WACK rising edge to WOK rising
Row address set-up time before first WOK
tRAW
190
Row address valid time after last WdK
tRWR
0
Writing Header information into Memory during T,V line 40
(Figure 4)
This arrangement is a combined phasing of the
SAA5040 and the SAA5020 and is therefore
referred to F 1 input. The first WOK -is related
to F 1 No. 14% from the SAA5020.
ns
1000
F 1 Clock cycle time
Time from F1 to WOK falling edge
twf
Time from F 1 to WOK rising edge
tfw
Data output set-up time
tDW
Data output hold time
tDH
300
500
0
120
330
0
ns
ns
ns
-ns
. Notes
1. These inputs may be a.c. coupled. Minimum rating is -0.3 V but the input may be taken more
I
negative if a.c. coupled.
2. Transition times measured between 0.5 and 3.5 volt levels.
Delay times are measured from 1.5 V level.
3. Transition times measured between 0.8 and 2.0 volt levels.
Delay times are measured from 1.5 V level.
6
August 1978
(
l__
Teletext acquisition and control circuit
S_A_A_5_0_40_ _
APPLICATION DATA
The function is quoted against the corresponding pin number
Pin No.
1. VSS Ground - 0 V
2.
F7 Data
This input is a serial data stream of broadcast teletext data from the SAA5030 Video Processor,
the data being at a rate of 6.9375 MHz.
This input from the SAA5030 is a.c. coupled with internal d.c. restoration of the signal levels.
3.
F7 Clock
This input is a 6.9375 MHz clock from the SAA5030 Video Processor which is used to clock the
teletext data acquisition circuitry. The positive edge of this clock is nominally at the centre of
each teletext data bit.
This input from the SAA5030 is a.c. coupled with internal d.c. restoration of the signal levels.
5. D LI M Del imiter
This input from the SAA5010 Remote Control Receiver Decoder is used to clock remote control
data into the SAA5040. The positive going edge of every second clock pulse is nominally in the
centre of each remote control data bit.
6.
DATA Remote control data
This input is a 7 bit serial data stream from the SAA5010 Remote Control Receiver Decoder.
This data contains the teletext and viewdata remote control user functions. The nominal data
rate is 32Ils/bit. The remote control commands used in the SAA5040 are shown in Table 1.
7. DEW Data entry window
This input from the SAA5020 Timing Chain defines the period during which received teletext
data may be accepted by the SAA5040. This signal is also used to enable the 5 memory address
o~tputs (pins 23 to 27) and the 7 bit parallel data output (pins 16 to 22),
8.
PO Picture on
This output to the SAA5010, SAA5030 and SAA5050 circuits is a static level used for the
selection of TV picture video 'on' or 'off'. The output is HIG H for TV picture 'ON', LOW for TV
picture 'OFF'. The output has an internal pull-up to VDD'
9. DE Display enable
This output to the SAA5050 Teletext Character Generator is used °to enable the teletext display.
The output is high for display enabled, low for display disabled.
The output is also forced to the low state-during the DEW and TV line 40 periods and when a
teletext page is cleared.
The output has an internal pull-up to VDD'
--
10. BCS Big Character select
This output to the SAA5020 Timing Chain and SAA5050 Character Generator is used to select
double height character format under user control. The output is high for normal height characters,
low for double height characters. It is also forced to the high state on page clear.
The output has an internal pull-up to VDD'
11. T/BTop/bottom
This output to the SAA5020 Timing Chain is used to select whether top or bottom half page is
being viewed. The output is high for bottom half page and low for top half page. It is also forced
to the low state on page clear.
The output has an internal pull-up to VDD'
~
(August 1978
7
__
____________________________
~S_A_A_5_04_0 ~Jl
__
APPLICATION DATA (continued)
12.
GLR General line reset
This input from the SAA5020 Timing Chain is used as a reset signal for internal control and
display counter.
13.
F1
This input is a 1 MHz clock signal from the SAA5020 Timing Chain used to clock internal
remote control processing and encoding circuits.
14.
VOO +5 V Supply
This is the power supply input to the circuit.
15.
WOK Write O.K.
This 3-state output signal to the system memory is used to control the writing. of valid data
into the system memory. The signal is LOW to write, and is in the high impedance state
when v"iewdata is selected. The three state buffer is enabled at the same time as the data
outputs (see below). An internal pull-up device prevents the output from floating into the
LOW state when the 3-state buffer is off.
16. 17, 18; 07 to D1, Data outputs
19,20,21, These 3-state outputs are the seven bit parallel data outputs to the system memory. The
22
outputs are enabled at the following times:a)
During the data entry window (DEW) to write teletext data into the memory.
The data rate is 867 k bytes per second and is derived from the te.letext data clock.
b)
During TV line 40 for encoded status information about user commands (e.g.
programme number), to be written into the memory. This period is known as ED I L
(encoded data insertion line). The data rate is 1M byte per second and is derived
from the 1 MHz display clock F 1.
c)
When the page ·is being cleared. In this case the data output is forced to the space
code (0100000) during the display period for one field. This data is held at the space
code from either-TV line 40 (if page clear is caused by user command), or the
received teletext data line causing the clear function, until the start of the data entry
window (DEW) of the next field.
23,24,25, A4 to AO Memory addresses
26,27
These 3-state outputs are the 5bit row address to the page memory.
This address specifies in which of 24 rows the teletext data is to be written.
The outputs are enabled during the data entry period (DEW).
28.
WACK Write address clock
This 3-state output is used to clock the memory address counter during the data entry
period (DEW). The output is enabled only during this period. The positive-going edge of
WACK is used to clock the address counter.
8
August 1978
(
l__
Teletext acquisition and control circuit
S_A_A_5_04_0_ _
08060
F7 Clock
I
I
I
I
\4""" TTtds -+I- TTtdh--l
I
I
I
I
I
I
I
I
Fig. 1 Teletext data timing.
DLIM
080610
Fig. 2 Control clock and data timing.
Data
output
- : tRAWl--
MEMORY~
ROW
ADDRESS
CD
~
________________~__________
080620
Fig. 3 Writing teletext data into memory during DEW.
August 1978
9
t_ _ __
SAA5040
'I
Fl period No14
jr------"\\
~
Fl
..
I--- twf
'--;'""1- - - '
I
WOK~
--I
•
tfw
i:~\cv
1
I
output
~
!
CV
i
Q)
:
:
\
I
08066
\
I
I--tow~
Data
~r-------'
I
--l
/
10
August 1978
r
L5V
(1)
2.0V
t
I
I4OH
G)I . '-_ _ _ _ _ _ _ _ __
i:
C
Memory row address is valid from :::. Fl
period No 1 for complete line
Fig. 4 Writing data into memory during TV line 40.
--
CD
Q)' O.8V
IX
(D
T
\
l__
Teletext acquisition and control circuit
S_A_A_50_4_0_ _
TABLE 1
Remote control commands used in the SAA5040
CODE
TELEVISION MODE (b7
= b6 = 0)
TELE:rEXT MODE (b7
= 1,.b6 = 0)
bS b4 b3 b2 b1
RESET
(Note 1)
1
TV/ON
Gives programme display.
0
STATUS
Gives programme display.
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
TIME
Gives,time display.
STATUS
Gives programme and header display.
HOLD
Stops reception of teletext.
(Note 3)
DISPLA Y CANCEL
TAPE
Resets to small characters.
0
1
1
1
0
TIMED PAGE OFF
0
1
1
1
1
TIMED PAGE ON
1
0
0
0
0
BBC1
1
1
0
0
0
1
lTV
2
1
0
0
1
0
BBC2
3
1
0
0
1
1
BBC1
4
1
0
1
0
0
1
0
1
0
1
PROGRAMMES
1
0
1
1
0
(Note 2)
1
0
1
1
1
1
1
0
0
0
BBC2
9
1
1
0
0
1
BBC1
0
1
1
0
1
0
lTV
"
SMALL CHARACTERS
VCR
LARGE CHARACTERS TOP HALF PAGE
lTV
S
VCR
NUMBERS
BBC1
(Note 4)
~
6
~
lTV
7
8
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
SUPERIMPOSE
1
1
1
1
1
TE'LETEXT ION
--
LARGE CHARACTERS BOTTOM HALF PAGE
(Note 5)
Notes on Page 12
August 1978
11
~_S_A_A_5_0~_"___jl_______________________~____
Notes
12
1.
Reset clears the page memory, sets page number to 100 and time code to 00.00, and resets timed
page and display cancel modes.
2.
Programme names are displayed for 5 seconds in a box at the top left of the screen in large"
characters. Programme com'l11ands clear the page memory except in timed page mode.
3.
Display cancel removes the text and restores the television picture. The SAA5040 then reacts to
any update indicator on the selected page. An updated newsflash or subtitle is displayed
immediately. When an updated normal page arrives the page number only is displayed in a box
at the top left of the screen. The full page of text can then be displayed when required using the
teletext/on command.
4.
Three number commands in sequence request a new page, and four number comma"nds select a
new time code in timed page mode. When a new page has been requested the page header turns
green and the page numbers roll until the new page is captured.
5.
The teletext/on command resets display cancel, hold and superimpose modes.
6.
Status, timed page on, timed page off, numbers, superimpose and teletext/on commands all reset
to top half page and produce a box round the header for five seconds. This allows the header to
be seen even in the television picture is on (e.g. newsflash or display cancel modes).
7.
In viewdata mode (b7 = b6 = 1) the SAA5040 is disabled and teletext cannot be received. All
3-state outputs are high impedance.
8.
The table on Page 11 shows code required for functions specified. The SAA5010 transmits and the
SAA5040 requires the .!!'ve~e ~f t~se~o~s i.:!l' b7 to b1. The code is transmitted serially in
the following order: b7, b1, b2, b3, b4, b5, b6. For full details of remote control data coding
see SAA5010 data sheet;
August 1978
_____________________________jl___
S_A_A_5_04_1___
TELETEXT ACQUISITION AND CONTROL CIRCUIT
The SAA5041 is an MOS N-channel integrated circuit which performs the control, data acquisition and
data routing functions of the teletext system.
The SAA5041 is a 28-lead device which receives serial teletext data from the SAA5030 video processor
and data from the remote control system e.g. SAA5010. The SAA5041 selects the required page
information and feeds it in parallel form to the teletext page memory.
The SAA5041 works in conjunction with the SAA5020 Timing Chain and the SAA5050 or SAA5052
Character Generator. It is similar to the SAA5040 but provides German on-screen displays and has a
different set of remote control commands.
The circuit is designed in accordance with the September 1976 Broadcast Teletext specification
published by BBC/IBA/BREMA.
QUICK REFERENCE DATA
Supply voltage
VDD
nom.
Supply current
IDO
typo
Operating ambient temperature
Tamb
5
80
-20 to +70
V
mA
°C
PACKAGE OUTLINE
28-lead DIL; plastic (SOT-117)
28
15
Viewed from top
14
Pinning: see next page
~
(
Augurt 1978
l_____--------
SAA5041
PINNING
15. Write O.K. (WOK)
1. VSS
16. Data out tb memory (07)
2.
F7 Data
3.
F7 Clock
4.
Not connected *
18. Data out to memory (05)
5.
6.
DLiM
DATA
20.
Data oOt to memory (03)
7.
Data entrY,window (DEW)
21.
Data out to mer~'lOry (02)
8.
Picture on output (PO)
22.
Data out to memory (D 1)
9.
Display enable output (DE)
23. Address out to memory (A4)
} teletext from SAA5030
}
Control from remo,' te control system
17. Data out to memory (06)
19. Data out to memory (04)
10. Big character select (BCS)
24. Address out to memory (A3)
11. T op/bottom (T IB)
25. Address out to memory (A2)
12. General line reset (GLR)
26. Address out to memory (A1)
13.
1 MHz Input (F1l.
27. Address out to memory (AO)
28. Write address clock (WACK)
14. VDD
DESCRIPTION
The circuit consists of two main sections.
a)
Data Acquisition
The basic input to this section is the serial teletext data 'stream (F7 Data) from the Video
Processor Circuit SAA5030. This is clocked by a 6.9375 MHz clock also from the SAA5030.
The incoming data stream is processed and sorted So that the page of data selected by the user
is written as 7 bit parallel words into the system memory. Hamming and parity checks are
performed on the incoming data to reduce errors. Provision is also made to process the control
bits in the page header.
b)
Control Section
The basic input to this section is the 7 bit serial data from the Remote Control Decoder
(e.g. SAB3012 or SAA5010). This is clocked by the 0 LIM signal.
The remote control commands are decoded and the controlled functions· are stored.
See Table 1 for full details of the remote control commands used in the SAA5041. The control
section can also write data into the page memory independently of the data acquisition section.
This gives an on screen display of certain user-selected functions, e.g. page number and programme
name.
The data and address outputs to the system memory are set to high impedance state if certain
remote control commands are received (e.g. Viewdata mode). This is to allow another circuit to
access the memory using the same address and data lines. The address lines are also high impedance
while the SAI;\5041 Is not writing into the memory.
* This pin must be connected to VSS for ceramic packages.
2
August 1978
(
l
Teletext acquisition and control circuit
SAA5041
-----------------------
HANDLING
Inputs'and outputs are protected against electrostatic charge in normal handling. However, to be totally
safe, it is desirable to take normal precautions appropriate to handling MaS devices (see MaS Handling
Notes).
RATINGS Limiting values in accordance with the Absolute Maximum System.
Voltages (with respect to pin 1)
Supply voltage (pin 14)
Input voltage
Voo
All inputs
Output voltage (pin 8)
All other outputs
min.
max.
-0.3
-0.3
7.5
7.5
-0.3
13.2
V
-0.3
7.5
V
V
V
Temperatures
Storage temperature
T stg
Operating ambient temperature
Tamb
-20 to +125
°C
-20 to +70
°C
CHARACTERISTICS
min.
typo
max.
Supply voltage
VOO (pin 14)
4.5
The following characteristics apply at Tamb
= 25 °C and
VOO
5.5
V
= 5 V unless otherwise stated.
Supply current
100
.
80
120
mA
5.5
0.5
V
30
ns
Inputs
F7 Data (pin 2), F7 Clock (pin 3)
Input voltage; HIGH
Input voltage; LOW
Rise time
, Fall time
VIH
Note 1
}
3.5
VIL
tr
Note 2
30
tf
Inpl\t resistance
5
I nput capacitance
(
--
ns
Mfl
7
~
V
August 1978
pF
3
/
jl----.._ _ _ _ __
_SA_A5_041_
. CHARACTERISTICS (continued)
F1 (pin 13)
min.
Input voltage; HIGH
VIH
2.4
Input voltage; LOW
VIL
0
Rise time
Fall time
}
Note 3
typo
max.
VOD
V
0.6
V
tr
50
ns
tf
30
ns
7
pF
10
JJ.A
Input capacitance
.-
Input leakage current (Vin = 0 to 5.5 V)
All other inputs
OUM (pin 5), OATA (pin 6), OEW (pin 7), G LR (pin 12)
Input voltage; HIGH
VIH
2.0
VOD
V
0.8
7
pF
10
JJ.A
0.5
V
VOD
V
tr
10
JJ.s
tf
1
JJ.s
7
pF
-50
-500
JJ.A
0.5
V
VOO
10
V
JJ.s
7
pF
-500
JJ.A
o
Input voltage; LOW
Input capacitance
Input leakage current (Vin = 0 to 5.5 V)
V
Outputs
DE (pin 9). BCS (pin 10), T/B (pin 11) (With internal pull-up to VOO)
Output voltage; LOW (\0 L = 200 JJ.A)
Output voltqge; HIGH
VOL
0
IOH " -50 pA for pin 9. }
10H = -30 JJ.A for pin 10 VOH
10H = -20 JJ.A for pin 11
2.4
Output voltage rise time
Output voltage fall time
}
CL
= 40 pF
Output capacitance
Output current with output in !-JIG H state
(V out = 0.5 V)
lout
PO (pin 8) (With internal pull-up to VOO)
Output voltage; LOW (lOL
--
= 140 JJ.A)
VOL
0
Output voltage; HIGH (\OH = -50 JJ.A)
VOH
2.4
Output rise and fall time (CL = 40 pF) (Note 3)
t r , tf
Output capacitance
Output current with ?utput in HIG H state
(V out = 0.5 V)
lout
-50
01 to 07 (pins 16 to 22) (3-state)
Output voltage; LOW' (\0 L = 100 JJ.A)
YOL
0
Output voltage; HIGH (lOI--j = -100 JJ.A)
VOH
2.4
Output rise and fall time (CL = 40 pF) (Note 3)
t r , tf
Leakage current in 'off' state (V out
Output capacitance
4
August 1978
'I (
= a to 5.5 V)
-10
0.5
V
. VOO
V
100
ns
10
JJ.A
7
pF
l
Teletext acquisition and control circuit
min.
WOK (pin 15) (3-state with internal pull-Up to VDD)
Output voltage; lOW (lOl
= 400 JlA)
= -200 JlA)
Output voltage; HIG H (lOH
Output voltage rise time}
(Cl = 80 pF) (Note 3)
Output voltage fall time
VOL
0
VOH
2.4
typo
SAA5041
max.
0.5
V
VDD
V
tr
50
ns
tf
100
ns
Output current with 3-state 'off' (Vout = 0.5 V)
-80
Output capacitance
-500
JlA
7
pF
WACK (pin 28) (3-state)
Output voltage; LOW (lOL
= 1.6 mA)
VOL
0
Output voltage; HIGH (lOH = -100tlA)
VOH
2.4
Output voltage rise time }
tr
(Cl = 40 pF) (Note 1)
Output voltage fall time
0.5
V
VDD
50
ns
300
tf
Leakage current in 'off' state (V out = 0 to 5.5 V)
Output capacitance
--10
V
ns
10
JlA
7
pF
AO to A2 (pins 25 to 27) (3-state)
VOL
0
0.5
V
Output voltage; HIGH UOH
VOH
2.4
V
Output rise and fall time
t r,
VD6
300
-10
10
J.l-A
7
pF
Output voltage; lOW (lOl == 200 JlA)
= -200 JlA)
(CL = 90 pF) (Note 3)
1f
leakage current in 'off' state (V out = 0 to 5,5 VI
Output capacitance
ns
A3 and A4 (pins 23 and 24) (3-state)
Output voltage; lOW (lOl = 1.6 mAl
VOL
0
Output voltage; HIGH (lOH = -200 JlA)
VOH
2.4
Output rise and fall time (Cl
leakage current in 'off' state
= 40 pF) (Note 3)
(V out = 0 to 5.5 V)
0.5
VDD
300
t r , tf
-10
Output capacitance
V
V
ns
10
JiA
7
pF
TIMING CHARACTERISTICS
---
Teletext Data and Clock (F7 Data + F7 Clock)
(Note 2 and figure 1)
F7 Clock cycle time
TT tc
F7 Clock duty cycle (HIGH to LOW)
144
ns
30
70
%
F7 Clock to data set-up time
TTtds
60
ns
F7 Clock to data hold time
TTtdh
40
ns
'I
(August 1978
5
Jl____________________________
____S_A_A_5_M_'___
TIMING CHARACTERISTICS (continued)
min.
typo
max.
Control DATA and Clock (DATA + DLlM)
(Note 3 and figure 2)
DUM cycle time
16
JlS
DUM duty cycle
50
%
DUM to DATA set-up time
14
Jls
DUM to DATA hold time
14
JlS
Writing Teletext data into Memory during DEW
(Figure 3)
WACK cycle time
1150
WACK rising edge to WOK falling edge
tAWW'
WACK rising edge to WOK rising edge
ns
250
450
ns
355
ns
twRW
220
WOK pulse width
tWFD
300
ns
Data output set-up time
tow
330
ns
Data output hold time
tDH
0
ns
Row address set-up time before first WOK
tRAW
190
ns
Row address valid time after last WOK
tRWR
0
ns
Writing Header information into Memory during TV line 40
(Figure4)
This arrangement is a combined phasing of the
SAA5041 and the SAA5020 and is therefore
referred to F1 input. The first WOK is related
to F 1 No. 14% from the SAA5020
F 1 Clock cycle time
--
twf
Time from F 1 to WOK rising edge
tfw
Data output set-up time
tow
330
ns
Data output hold time
tDH
0
ns
300
500
ns
0
120
ns
Notes
1. These inputs may be a.c. coupled. Minimum rating is ~0.3 V but the input may be taken more
negative if a.c. coupled.
2. Transition times measured between 0.5 and 3.5 volt levels.
Delay times are measured from 1.5 V level.
3. Transition times measured between 0.8 and 2.0 volt levels.
Delay time,s are measured from 1.5 V level.
_ 6_
ns
1000
Time from F1 to WOK falling edge
August 1978
~
(
Teletext acquisition and control circuit
l__
S_A_A_5_04_1__
APPLICATION DATA
The function is quoted against the corresponding pin number
Pin No.
1. VSS Ground - 0 V
2.
F7 Data
This input is a serial data stream of broadcast teletext data from the SAA5030 Video Processor,
the data being at a rate of 6.9375 MHz.
This input from the SAA5030 is a.c. coupled with internal d.c. restoration of the signal levels.
3.
F7 Clock
This input is a 6.9375 MHz clock from the SAA5030 Video Processor which is used to clock the
teletext data acquisition circuitry. The positive edge of this clock is nominally at the centre of
each teletext data bit.
This input from the SAA5030 is a.c. coupled with internal d.c. restoration of the signal levels.
5. DLIM Delimiter
This input from the remote control system (e.Q. SAA5010) is used to clock remote control
data into the SAA5041. The positive going edge of every second clock pulse is nominally in the
centre of each remote control data bit.
6.
DATA Remote control data
This input is 7 bit serial data stream from the remote control system (e.g. SAA5010)
This data contains the teletext and v iewdata remote control user functions. The nominal data
rate is 32 J,ls/bit. The remote control commands used in the SAA5041 are shown in Table 1.
7.
DEW Data entry window
This input from the SAA5020 Timing Chain defines the period during which received teletext
data may be accepted by the SAA5041. This signal is also used to enable the 5 memory address
outputs (pins 23 to 27) and the 7 bit parallel data output (pins 16 to 22).
8.
PO Picture on
This output to the SAA5010, SAA503d and SAA5050 or SAA5052 circuits is a static level used
for theselection of TV picture video 'on' or 'off'. The output is HIG H for TV picture ON, LOW
for TV picture OFF. The output has internal pull-up to VDD'
9. DE Display enable
This output to the SAA5050 or SAA5052 Teletext Character Generators is used to enable the
teletext display. The output is high for display enabled, low for display disabled.
The output is also forced to the low state during the DEW and TV line 40 periods and when a
teletext page is cleared.
The output has an internal pull-up to VDD'
10. BCS Big Character select
This output to the SAA5020 Timing Chain and SAA5050 or SAA5052 Character Generators
is used to select double height character format under user control. The output is high for
normal height characters, low for double height characters. It is also forced to the high state on
page clear.
The output has an internal pull-Up to VDD'
11.
TIB T op/bottom
This output to the SAA5020 Timing Chain is used to select whether top or bottom half page is
being viewed. The output is high for bottom half page and low for top half page. It is also forced
to the low state on page clear. The output has an internal pull-up to VDD'
August 1978
7
__
~S_A_A_5_~_1___jl_____________________________
APPLICATION DATA (continued)
12.
GLR General nne reset
This input from the SAA5020 Timing Chain is used as a reset signal for internal control
and display counter.
13.
F1
This input is a 1 MHz clock signal from the SAA5020 Timing Chain used to clock internal
remote control processing and encoding circuits.
14.
VDD +5 V Supply ,
This is the power,supply input to the circuit.
15.
WOK Write O.K.
This 3-state output signal to the system memory is used to control the writing of valid
data into the system memory. The signal is LOW to write, and is in the high impedal1ce
state when v iewdata is selected. The three state buffer is enabled at the same time as the
data outputs (see below). An internal pull-up device prevents the output from floating into
the LOW state when the 3-state buffer is off.
16,17, 18, D7 to D1, Data outputs
19, 20, 21, These 3-state outputs are the seven bit parallel data outputs to the system memory. The
22.
outputs are enabled at the following times:a)
During the data e~try window (DEW) to write teletext data into the memory.
The data rate is 867 k bytes per second and is derived from the teletext data clock.
b)
During TV line 40 for encoded status information about user commands (e.g.
programme number), to be written into the memory. This period is known as EDI L
(encoded data insertion line). The data rate is 1M byte per second and is gerived
from the 1 MHz display clock F1.
c)
When the page is being cleared. In this case the data output is forced to the space
code (0100000) during the display period for one field. This data is held at the
space code from either TV line 40 Of page clear is caused by user command), or the
received teletext data line causing the clear function, until the start of the data entry
window (DEW) of "the next field.
23, 24, 25, A4 to AO Memory addresses
26,27.
.--.........
28.
:::
These 3-state outputs are the 5 bit row address to the page memory.
This address specifies in which of 24 rows the teletext data is to be written.
The outputs are enabled during the data entry period (DEW).
WACK Write address clock
This 3-state output is used to clock the memory address counter during the data entry
period (DEW). The output is enabled only during this period. The positive-going edge of
WACK is used to clock the address counter.
8
August
1978
1r
l__
Teletext acquisition and control circuit
S_A_A_504----.;..1_
08060
F7 Clock
I
I
I
I
14- TTtds ---+- TTtdh---l
I
I
I
I
I
I
I
I
Fig. 1 Teletext data timing.
DLIM
080610
Fig. 2 Control clock and data timing.
\'----
---
Data
output
-ltRAW~
MEMORY~
ROW
CD
ADDRESS
~
__________________________~
080620
Fig. 3 Writing teletext data into memory during DEW.
August 1978
9
~_S_A_A_5~~_1___Jl_________~__~____~~~____
Fl period No14
j
Fl
r - - -_____\
f--twf
I
WOK~
f - - - tow
I
Data
\1@
outputJ\CJJ
:
~ '---:-1_ _
--I tfw ~~_ _--,
!:A~
I
1
-----r-I
I
, ~
i
!
\
I
T
\
/
I@V
August 1978
r
1.SV
(]
G)
2.0V
O.8V
'C
61\'-__________
Memory row address is valid from
period No 1 for complete line
Fig. 4 Writing data into memory during TV line 40.
10
CD
t
f4-- OH
I::
08066
"j
..J
~ Fl
l__
Teletext acquisition and control circuit
S_A_A_5_04_1_ _
TABLE 1
Remote control command codes used in the SAA5041
CODE
TELEVISION MODE (b6 = b7
= 0)
TELETEXT MODE (b7
= 1.• b6 = 0)
b5 b4 b3 b2 b1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
TIME
Displays time.
STATUS
Gives header and time display.
TIMED PAGE
On/off toggle function.
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
1
0
0
1
0
2
1
0
0
1
1
3
1
0
1
0
0
4
TELETEXT RESET
(Note 1)
•
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
8
1
1
0
0
1
9
1
1
0
1
0
5
PROGRAMMES
Clear memory except
NUMBERS
6
in Timed Page mode
(Note 2)
7
::::
-
SMALL CHARACTERS
1
1
0
1
1
LARGE CHARACTERS Top/bottom toggle function
1
1
1
0
0
HO LD Stops reception of teletext (Note 3)
~I
1
1
1
0
1
1
1
1
1
1
1
1
DISPLAY CANCEL (Note 4)
SUPERIMPOSE
NORMAL DISPLAY (Note 5)
Notes on page 12
August 1978
11
~_S_A~A_5_M_'___jl_____~__~__________________
Notes
12
1.
The teletext res,et command. clears the page memory, selects page 100, goes to small characters
and resets hold, timed page and display caricel modes.
2.
Three number commands in sequence request a newpage, and four number commands select a
new time code in timed page mode. When a new page is requested the header turns green and the
page numbers roll until a new page is captured.
3.
When hold mode is selected HALT is displayed in green at the top right of the screen.
4.
Display cancel removes the text and restores the television picture; ThE! SAA5041 then reacts
to any update indicator on the selected page. An updated newsflash or subtitle is displayed
immediately. When an updated normal page arrives the page number only is displayed in a box at
the top left of the screen. The full page of text can then be displayed when required using the
normal display command.
5.
The normal display command resets hold, display cancel and superimpose modes.
6.
Status, timed page, numbers, hold, superimpose and normal display commands all,reset to top
half page and produce a box around the header for five seconds. This allows the header to be
seen even if the television picture is on (e.g. newsflash or display cancel modes).
7.
An 5 is displayed before the page number at the top left of the screen (e.g. 5123).
8.
In v iewdata mode (b7 = b6 = 1) the 5AA5041 is disabled and teletext cannot be received. All
3-state outputs are high impedance.
9.
The table on Page 11 shows code required for functions specified. The 5AA5041 requires the
~ve~e ~f tties~cook system and
does not necessarily imply that the device will go into production
S_A_B1_0_0_9_B_ _
SUPERSEDES DATA SHEET SAB1009A AUGUST 1978
WIDE-BAND LIMITING AMPLIFIER
The SAB1009B is a three-stage differential amplifier in the range 70 to 900 MHz with inherent limiting
action. The differential inputs are internally biased to permit capacitive coupling and asymmetrical
drive. For asymmetrical drive pin 3 should be used as an input and pin 4 should be grounded via a 56 n
resistor and a d.c. blocking capacitor. The outputs are complementary with non-standard levels.
The device is specified for a nominal supply voltage of 5 V; it may also be operated with a supply
voltage of 5,2 V ± 5%. The voltage dropping resistor Ree has then to be increased to 82 n.
9
Vee
3
I,
Q, 10
4
'2
Q
n.c.
n.c. VEE
Q
1 Vee
n.c.
SAB1009B
2 11
VEE
7Z74638.2
',7,12
7Z74639.2
Fig. 1 Block diagram.
Fig. 2 Pins marked n.c. should preferably
be grounded or connected to supply.
Vee via 75 n to 5 V.
VEE = 0 V (ground).
QUICK REFERENCE DATA
Supply voltage
5 ± 5% V
VCC
Supply voltage dropping resistor
RCC
Frequency range
fi
Differential clipped output voltage
R L = 50 n at each output
Vo(p-p)
typo
Pav
typo
Power consumption per package (no load)
Operating ambient temperature
75
Tamb
550 mV
75 mW
o to + 70
PACKAGE OUTLINE
14-lead 01 L; plastic (SOT-27S, T, V).
n
70 to 900 MHz
'I
June 1979
0C
l_ _ __
SA810098
r---.---------------------~~------~--~~------09
. - - + - - - - - 0 10
t----011
3 0-----+---+-------.......-1
40----+---+-------.......----+-------J
1....-.-----012
. . . .----------------------------07
~-~----------
~
Fig. 3 Circuit diagram.
RAT,INGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage (d.c.)
VCC
Input voltage
VI
Storage temperature
T stg
-55 to + 125 0C
Junction temperature
Tj
max.
____
2
_ _ June 1979
~
(
max.
7 V
a to + 5
V
125 °C
Wide-band limiting amplifier
L_.__SA_B_1_0_09_B_ _
D.C. CHARACTERISTICS
VCCvia75nt05V
The circuit has been designed to meet the d.c. specifications shown in the table below after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed-circuit board.
symbol
Supply
current
I . typo
CC max.
pin
under
test
9
Tamb (oC)
conditions
0
25
70
-
23
30
-
min.
typo
max.
70
-
900
MHz
-
-
-
-
dB
dB
dB
dB
dB
-
1,5
dB
mA
mA
l pins 3 and 4 open,
J no d.c. load.
A.C. CHARACTERISTICS
V CC via 75 n to 5 V ± 5%; T amb = 0 to + 70 °C
symbol
Frequency
range
pin
under
test
f·I
r 26
Gain *
Gain variation
versus
temperature
26
23
19
116
G
-
llG
-
I nput voltage
standingwave ratio
VSWR
3
-
-
5
I nput voltage
Vi(rms)
3
-
-
150
conditions
fi
fi
fi
fi
fi
70
100
= 200
= 500
= 900
=
=
MHz
MHz
MHz
MHz
MHz
I
Vj{rmsJ = 25 mV;
Zi nom = 75 n
Source connected
1 to pin 3; pin 4
grounded via 56 n
in series with 10 nF.
mV
* For gain
. d eflnltlon
. . . see Fig.
. 6 (G = 20 log -V2) .
V1
June 1979
3
1 - -_ _
-S-A-B-10-0-9-B--l-~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
A.C. CHARACTERISTICS (continued)
7Z746442
40
-""'"
G
(dB)
-~
t""-
~
.............
~
[""-...
~
30
~
~
.........
~
I"'"
~P
,
~
1\
I.........
.............
~
(-
.............
,
glJ
~iJriJfl
~ee(j
~11J1i)
20
'giJ'
N
'fl
~
I
1
10
20
50
70
100
200
f (MHz)
500
Fig. 4 Gain as a function of frequency. V CC = 5 V; T amb = 25 oC.
4
June
19791 (
f""'o.
i'o.
1000
l__
Wide·band limiting amplifier
S_A_B_1_00_9_B_ _
A.C. CHARACTERISTICS (continued)
Vi(rms) = 25 mV
Vee = + 5 V
Ree = 75.n
--
7Z78976
Fig. 5 Smith chart of typical input impedance at pin 3 with pin 4 terminated to ground.
'I (
June 1979
5
SA810098
Jl
Test circuit
Vee
=5 V
hybrid
junction
v.h.f./u.h.f.
sinewave
generator
(-3dB)
V1
~
4
11
(-3dB)
SAB
1009B
=
Fig. 6 Test circuits for defining gain.
V1 and V2 are minimum input lev~ls for correct operation.
..
0
V2
Gain defined as G == 2 log --'-.
V1
Capacitors must be leadlessceramic (value 10 nF).
Hybrid junctions are Anzac H-183-4 or similar.
Connections to the device must be kept short for proper tests.
Cables are 50 n coaxial cables.
6
June
19791 (
13
reference
SAB
1046
(12)
to
oscilloscope
:E
APPLICATION INFORMATION
c:
L5
+5V
C13~
Ol
3'
22J1FJ;
;::.:
5"
CQ
L4
R5
'P
c::l
C.
+9V
Ol
3
~
C11
C8
v.h.f.
L1
.1
~"
10nF~
L2
34nH
~
9
46nH'
4
C3 J;6,8 PF
C1
u.h.f.
~
C2
II
I
10pF
41
'/
R4Q
56,Q _
C5
10nF
SAB
1009B
110~
C7
1~
10nF
I
FDIV
SAB
1046
~
2
r,10
R9
II ~~n
OV
7Z78975
'l'
t...
C
::l
CD
....
(0
-...J
(0
Fig. 7 H.F. divider for DICS in television receivers (prescaler module). The pins not
mentioned are connected to ground except pin 5 of SAB 1046 which is connected to V CC .
Values of R8, R9 and L6 have to be chosen in accordance with the load capacitance.
en
»
OJ
o
o
<.0
OJ
-...J
1111111
jl_________----------------------
______
SA_B_1_00_9_B___
1....
·------------
ov
7278974
--
50mm ------------~
+5 V
+9 V
OV
Fig. 8 Component layout of circuit shown in Fig. 7.
8
. June 1!179
~
(
F DIV
I
________________________________jl____
S_A_B_1_01_6____
CONTROL CIRCUIT FOR ON-SCREEN DISPLAY OF STATION
ANDIOR CHANNEL NUMBER
STOP DICL
ADI
BDI
HPOS
VPOS
GDISP
PRON
RSET
-1§.
r-+
-1i r-+
.-3
r--+
1
~
~
DISPLAY POSITION
t-CONTROL
-2 ---+
.-J. --+
PCEN
PCDA
CLCK
h4
-9
10
19
18
V DD
t
6
8
7
CHARACTER
ROM
DISPLAY
---+
CONTROL
-+- ~
FRAM
-+- ~
CHAR
-+- ll...-
VOLN
i
STATION / CHANNEL NUMBER
REGISTER
STATION
NUMBER
MEMORY
'------+
1
[
112
VSS
21
20 22
PRGB
PRGA.
23
2
CPEN1
PRGC CPEN2
7Z74946
Fig. 1 Block diagram.
Features
•
•
•
•
•
•
•
Station and channel number display (4 digits).
Station number display is separate (2 digits; 1 to 16).
4-digit display (0000 to 9999).
Character rounding for improving the legibility of the numerals.
Internal digital display positioning and defining the length of display; no control knob.
Control signal for separate background.
Parallel outputs for station information.
QUICK REFERENCE DATA
Supply voltage range
VOO
Operating ambient temperature range
Tamb
8 to 10 V
o to + 70
0C
I nput frequency
fOICL
typo
Clock frequency
fCLCK
typo
62,5 kHz
100
typo
20 pA
Quiescent current; VOO
= 10 V;
IQ = 0; Tamb = 25 0C
2,5 MHz.
PACKAGE OUTLINE
24-lead OIL; plastic (SOT-101A).
l
February 1979
jl~________________________________
_____S_A_B1_0_16____
GENERAL DESCRIPTION
The SAB1016 integrated circuit controls the on-screen display of station and/or channel number. It
generates data for partially blanking the upper part of the scan of a TV receiver and thereby displaying
the number of the selected station and/or channel. The numerals are normally displayed for 2,5 seconds
after station/channel selection.
Modes of operation:
• flashing display facility during store
• background only if channel mode is set, or in search tuning mode
• persistent on-screen display
The 4 characters are presented on a background; station number left and channel number right,
separated by a blank position.
The characters are built up from a 5 x 7 dot matrix. The duration of one display data bit is ~ 400 ns
in the horizontal direction; vertically a display data bit corresponds to 3 lines per half picture. The
legibility of the display is improved by incorporation of the additional display rounding facility; i.e.
display dots which were touching diagonally are now connected by an extra display rounding dot,
which is displaced by half a dot horizontally and one line per half picture vertically.
2
1st field
line
nd
field
line
~~----~~~~~~~~~~I------I~r---- n + 1
m+l---7S'~_-.,..
m
+2 -
~<;4----tc---+--_~~~~~--f--__-~~~--- n + 2
~M----tr----+-----t'i~~~~M---~-__-~~;- ___ n + 3
m
+3-
*~~""":~-+--~""'""''f''''"'''":---I--~~~~r-
m+4-
~~~~'----+-----I.--+----L.--~--+'i~~~;---- n + 4
-0~~~~~a------I------~~~~~~~-- n + 5
m + 5 --'4%%%%%~----+_----~%%%%~
----'4<~~~~7f--------+_----~~~~7*''----- n
m + 6 - - --~~~~~,"","","",""~,",,~,",,,",,~ry9,ry9,~;,L--_ _-....:.~~~~~~~~~~~~~~~~~___ --- n
+6
+7
7Z74950.1
400ns
----
Fig. 2, Construction of a character from display dots with additional character rounding dots.
2
l___
Control circuit for on-screen display of station
S_A_B_10_1_6_ _
and/or channel number
OPERATION DESCRIPTION
Data input
The data input for generation of the characters is performed serially via the data input PCDA synchronized with the system clock (CLCK). The data are accepted if, during data transfer, the data
enable input PCEN is HIGH. The data are accepted into an input register, which also serves as a shift
register. In order to represent 4 characters, a group of 16 bits is necessary as the address for the internal
12 x 36-bit character ROM. The following characters are displayed on the screen according to the code
in Table 1.
.
Table 1
address code
D
C
B
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
on-screen selected
character
0
1
2
3
4
5
6
7
8
9
blank
blank
blank
blank
blank
The positioning of the on-screen display and the number of digits are controlled by the logic states at
the control inputs GDISP and PRON (see Table 2). They also define the display format of the commands accepted by the circuit (see Fig. 4).
Table 2. Display format
control inputs
PRON
GDISP
0
0
1
0
1
0
display
format
DBUS
format
display format
6 bits
16 bits
6 bits
IBUS
GBUS
IBUS
13 bits
DBUS
2 digit; station no. at left (1 to 16)
4 digit; e.g. clack (0000 to 9999)
2 digit; station no. at right (1 to 16)
4 digit; station and/or channel no. at
right (1 to 1699)
February 1979
3
jl_________________________________
_____
S_AB-1-0-16--__
GDISP = 0
PRON = 0
GDISP = 0
PRON = 1
GDISP = 1
PRON = 0
GDISP = 1
PRON = 1
7Z74947
Fig. 3 Presentation of the various display formats.
4
. February 1979
(
l
Control circuit for on-screen display of station
and/or channel number
SAB1016
'-----------------------
The various data words have different lengths and conform to the following formats:
6 th bit
1st bit
~BbYt~ I FIE
D
IC I B IA I
13 th bit
1st bit
l~BbYt; I D I C I B I A I D I C
I I I Ic I I I
B
A
D
B
A
DMS
~~"-----y---I~
units
2-digit
tens
l-digit
binary- coded
station number
display
mode bit
y
channel number
16 th bit
1st bit
~BbYt~ I D I ~ I B I A I D I c
I I I I c I I A I Ic I I I
B
A
D
B
D
B
A
~ "-----y---I "-----y---I "-----y---I
4-digit
3-digit
2-digit
l-digit
7Z74948
Fig.4 Available display formats. A start bit is sent before each data word in each case.
CLCK
~
PCEN H
L ------H
- - - - - - - - - - - - - - data word
PCDA
~ ~
start-bit
.L
I
--------------1
bit-l
leading zero
bit-n
W%
7Z74949
Fig.5 Display data timing diagram.
February 1979
5
Jl
SAB1016
Data word I BUS
The serial transfer of the 6·bit1BUS data word is accepted on input PCDA, when input PRON is LOW,
and the data contain the control and display instructions as given in Table 3.
Table 3. IBUS instructions
IBUS code
2
4
16
17 .
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
36
37
instruction
F
E
D
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1·
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
off (stand by)
display short (2,5 s)
station 16
1
2
3
4
5
,6
7
8
9
10
11
12
13
14
15
display on/off
step station up
step station down
Any possible input codes which are not in Table 3 will be received by the circuit, but not evaluated.
The station number, transmitted in binary form, will be transferred internally into a 2 x 4 bit code
(BCD).
The display mode control inputs ADI and BDI must be connected to LOW.
6
February 1979
(
Control circuit for" on-screen display of station
and/or channel number
l
SAB1016
'----------------------
Data word OBUS
The serial transfer of the 13-bit DBUS data word is arranged as a display mode bit (DMB) together
with 3 data blocks, and is accepted according to the conditions of Table 2. Bits 2 to 5 contain station
numbers 1 to 16, which are transferred into 2 x 4 bits internally; whilst bits 7 to 9 and 10 to 13 contain
the 1st and 2nd digit of the channel number respectively; they are binary coded as given in Table 4.
Table 4. Specification of the DBUS code
DBUS input code
D
C
B
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
channel
number
0
1
2
3
4
station
number
16
1
2
3
4
5
6
7
1
5
6
7
0
0
8
8
0
1
1
0
1
0
1
9
9
10
11
12
13
14
15
0
0
0
1
1
1
0
1
blank
blank
blank
blank
blank
The 1st bit of a DBUS instruction (DMB) is a display mode bit with the following code:
DMB
o
1
instruction
display of station and channel number
display of channel number only
The display mode control inputs ADI and BDI can be driven as required (see Table 5).
February 1979
7
SAB1016
l _ ._ - - - , - - - - _
Data word GBUS
Corresponding with the input conditions for the control inputs GDISP and PHON quoted in Table 2,
the SAB 1016 accepts a 17-bit serial data transfer which causes the display of a 4-digit character
combination. This is obtained with the GBUS data word. Each part of the four 4-bit data block (see
Fig. 4) corresponds with a character, which is binary coded as in Table 1.
Control of display mode
The type and manner of the display can be contr911ed at the inputs ADI and BDl. The following
display modes are provided:
Table 5.
ADI
BDI
1
0
0
0
1
0
display mode
ON for 2,5 s after selection
persistent
flashing (0,32 sON; 0,32 s OFF)
background only (2,5 s)
--.
Synchron ization
Display synchronization is achieved by means of the inputs VPOS for vertical and HPOS for the
horizontal sync. If the sync pulses of a TV correspond with the requirements in Fig. 6, they can be
applied directly to the inputs of the circuit.
HPOS~--~
-l 11!J.s < twHPOS <20 /lS
l-
vpos~-_J
--I
1-1}Js56/lS 7Z74952
tRVJlOS>5,6ms-7Z74953
Fig. 6 Sync pulse specifications.
--
As soon as there is a display command in the form of data received, an external oscillator is sta~ted by
signal STOP = LOW, which is caused by the first horizontal pulse (H paS) after a vertical pulse (VPOS).
The oscillator frequency is 2,5 MHz, i.e. a periodic time of T = 400 ns, which isthe smallest time unit
in the representation of a display data bit. The oscillator is stopped at the end of a line.
The instant of time of a display, i.e. the output of signals at FRAM for the background and CHAR for
characters is determined by:
1. The state of an internal vertical position counter, which releases the output in the 46th line of a
TV picture.
2. The state of the horizontal position counter, which determines the position of the start and finish
of display in a picture-line. The display depends on the logic states of the display format control
inputs GDISP and PRON (see Fig. 7).The height of the display field (33 lilies) and character height
(21 lines) are established by the vertical positiQn counter.
June
19791(
Q)
::::I
Co
Q
start of scan --------,-
n
45 lines of field
--+•
1
1"";00 00·1
33 lines of field
_t
':j'
Q)
::::I
::::I
~
::::I
c:
3
C"
~
0
0
~
~
(')
~.
c:
;:j:
....
Q
0
::::I
*ii
::::I
~
~
Q)
HPOS
36T
--I
0
....
en
at
~.
I.
15T
-<
FRAMl
0
::::I
1-
r-------------------~
L-____________~--~------_+----------~--+_------ FRAM2
33T - - - - - - FRAM3
102T
--------------------------~
15T
FRAM4
33T
I•
horizontal line period = 64 J1 s
T = duration of 1 display data bit
11
(I)
0-
= 400ns for f DICL = 2,5 MHz
.. I
F RAM 1
F RAM2
F RAM3
F RAM4
:
:
:
:
station no. only at left
4-digit display
station no. only at right
station & channel no. at right
2
Q)
7Z74945
-<
to
to
-.;J
to
Fig. 7 Relationship between the horizontal pulses from the receiver and the display width defining pulses (FRAM)
determined by the display mode inputs GDISP and PRON (see also Table 2).
en
»
OJ
o
....
m
1IllJJ1-
....
0
lines from top of
TV field raster
11
station number data
(II
0-
2
til
-<
CO
-...J
CHAR
channel number data
1-45
(J)
»
OJ
....
0....
0)
FRAM
{
1-6
CO
} '6-51
52-54
55-57
58-60
61-63
64-66
67-69
70-72
7-9
1-3
10-12
4-6
7-9 '13-15
10-12 16-18
13-15 19-21
16-18 22-24
19-21 25-27
.}731"
28-33 {
79-312,5
FRAMl-33
CHAR1-3
CHAR4-6
CHAR7-9
CHAR10-12
CHAR13-15
CHAR16-18
CHAR19-21
1 2T
1-
5T
~1'Tl-
5T
-1-
7T
-1-
5T
_I'TI _ _
Fig. 8 Display data from the SAB1016. The character rounding bits are omitted for clarity. T
5T
-I
2T
I
= 1 bit duration = 400 ns.
7Z71676
l__
Control circuit for on-screen display of station
S_A_B_1_01_6_ _
and/or channel number
Station memory
Serially transmitted station numbers (OBUS; IBUS) are loaded into the internal station number
memory. The output information is available at the station outputs according to Table 6. If an I BUS
instruction directs a step station up (+) or down (-l, then the setting of the station counter is increased
or decreased by 1. The output states at the station outputs also change accordingly.
Table 6.
station no.
on display
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
CPEN1
0
0
0
0
0
0
0
0
1
CPEN2
1
1
1
1
0
0
0
0
0
0
0
0
station outputs
PRGC
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
PRGB
PRGA
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
\\",j
After the end of station selection, a HI G H signal appears at output va LN for 160 ms. Th is signal can
be used for suppression of sound in the TV receiver (muting circuit).
February 1979
11
Jl________________________________
_____
S_AB_1_0_16_'___
PINNING
24
12
HSET
positive supply
negative supply (0 V)
1
RSET
4
5
6
7
8
9
14
15
18
19
GDISP
PRON
PCEN
CLCK
PCDA
DICL
VPOS
HPOS
SOl
ADI
reset signal, synchronized
internally with system clock
control of display data format/
position of display field
data enable (DBUS)
system clock; 62,5 kHz
data (DBUS)
display clock; 2,5 MHz
vertical sync pulse
horizontal sync pulse
3
11
TEST1
TEST2
Inputs
CPEN2
J
VDD
VSS
TEST1
PRGC
GDISP
PRGA
PRON
PRGB
PCEN
ADI
CLCK
BDI
PCDA
FRAM
DICL
CHAR
STOP
HPOS
TEST2 11
14 VPOS
VSS 12
13 VOLN
7Z74944
Fig. 9 Pinning diagram.
display mode control
test inputs
Outputs
10
STOP
13
16
17
2
20
21
22
23
VOLN
CHAR
FRAM
CPEN2
PRGB
PRGA
PRGC
CPEN1
control signal external 2,5 MHz
display oscillator
output signal for muting
character data output
display field output (background)
' station re,gister outputs
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
-
VDD
Input voltage range
VI
-0,3 to VDD + 0,3 V
Input current
± I,
± IQ
max.
max.
10 mA
PQ
Ptot
max.
50 mW
Output cu rrent
Power dissipation per output
Total power dissipation per package
Operating ambient temperature range
Storage temperature range
12
-0,3 to + 11 V
Supply voltage range
February 1979
(
Tamb
T stg
10 mA
500 mW
max.
o to
+ 70 0C .
-55 to + 150 °C
l
Control circuit for on-screen display of station
and/or channel number
SAB1016
----------------------
CHARACTERISTICS
VSS = 0; T amb = 0 to + 70 °C; unless otherwise specified
VDD
V
symbol
min.
typo max.
conditions
Supply voltage
-
VDD
8
9
10
Quiescent current
per package
10
IDD
-
-
100
Input leakage current
10
IIR
-
-
1
/lA
{ all inputs at 10 V;
Tamb = 25 °C
Input leakage current
10
-IIR
-
-
1
/lA
{ all inputs at VSS;
Tamb = 25 °C
I nput voltage LOW
8 to 10
VIL
0
-
1,5
V
Input voltage HIGH
8 to 10
VIH
VDD-1,5 -
VDD
V
8 to 10
8 to 10
VOH
VOL
VDD-1
-
-
-
8 to 10
8 to 10
VOH
VOL
VDD-1
-
-
-
V
/lA
I Q = 0; T amb = 25 °C
Outputs PRGA,PRGB,
PRGC,CPEN1,CPEN2,
VOLN
output voltage HIGH
output voltage LOW
1
V
V
-IOH = 1 mA
IOL = 1 mA
Outputs F RAM,CHAR,
STOP
output voltage HIGH
output voltage LOW
1
V
V
-IOH = 3 mA
IOL = 3 mA
Input DICL
input frequency
8 to 10
fDICL
duty factor
8 to 10
[)
rise/fall time
8 to 10
tr; tf
-
2,5
2,8
0,45
-
0,55
-
-
50
MHz
ns
Input CLCK
-
-
100
0,2
-
0,8
tr: tf
-
-
1
fHPOS
-
-
16
tr; tf
-
-
500
ns
8 to 10
fVPOS
-
-
100
Hz
8 to 10
tr: tf
-
-
500
ns
input frequency
8 to 10
fCLCK
duty factor
8 to 10
[)
rise/fall time
8 to 10
input frequency
8 to 10
rise/fall time
8 to 10
kHz
/lS
Input HPOS
kHz
Input VPOS
input frequency
rise/fall time
--
February 1979
13
jl~________________________________
_____S_A_B_10_16____
APPLICATION INFORMATION
2,5 MHz
OSCILLATOR
HEF4025B
6
10
kn
56pF
13 VOLN
14
to/from {
display
interface
TEST2
VPOS
STOP 10
15 HPOS
16
CHAR
DICL
17 FRAM
PCDA
<0
from
{
tuning part
18 BDI
19 ADI
20 PRGB
21
PRGA
22 PRGC
23
CPEN1
+9V
0
co
id~' input vol~age
I
Input, frequency
fi
Differential
input voltage
IV 2- V 31 pop
2 and3
Slew rate for operation:
down to 70 MHz
70
--
1000 MHz
-
-
1,4
V
80
-
-
V Ills
V!(p_p) - 600 mV,
tested frequency on pin
11 or 12 is fj/256
*
{ square-wa~e drive
Vi(p-p) min. 160 mV
Guaranteed operating region (see also Fig. 4)
---_ .._-input frequency
--
Minimum required
input level Vi(p-p)
*
MHz
70
200
500
900
1000
mV
dBm
355
-5
160
-12
140
-13
100
-16
200
-10
* For definition of input voltage see Fig. 5.
I(
June 1979
----
3
SAB1046
l " , - - - - - ,_
__
A.C. CHARACTERISTICS (continued)
7Z74877.1
1000
Vj(p_p)
(mV)
500
,
I\. ~ ~V::t//,
i\"
200
I'
100
guarant~ed
.
operating region
m~x
"Ii ~
~ r--
I
'l/.: ~~ ~
"'~
1"0...
~~
~
,
~
50
1\
Ij
20
10
10
20
50
100
Fig. 4 V CC
200
1000
500
2000
fi (MHz)
= 5 V; V D D = 5 to 9 V; T amb = 0 to 70 °C.
hybrid junction
VCC
(5V)
V DD
4
13
Vi
v.h.f./u.h.f.
sinewave
generator
~
(-3dB)
(-3dB)
~
H
2
11
(12)
to
oscilloscope
SAB1046
3
(-3dB)
50n
10
......--- VEE = OV
+-----~-------~-
7Z74878.1
Fig. 5 Test circuit.
4
Cable must be 50 n coaxial.
The capacitors are leadless ceramic (multilayer capacitors) of 10 nF.
All connections to the device must be kept short.
Hybrid junctions are ANZAC H-183-4 or similar.
June 1979
(
APPLICATION INFORMATION
C)
:::t
N
L5
+5V
a.
.r
is:
22JlF
~
c-<
J;
N
(J'I
0')
R5
L4
+9V
C8
v.h.f.
Ll
34nH
.1
Cll
10nFI
L2
9
46nH'
4
C3~6,8PF
u.h.f.
" r"\
J-Y•
Cl
C2
SAB
1009B
1
10pF
41
110~
C7
1~
10nF
R4Q
56[2
C5
10nF
I
FDIV
SAB
1046
~
2
r,10
R9
1/ ~~[2
OV
7Z78975
c....
c:
:::l
Fig.6 H.F. divider for DICS in television receivers (prescaler module).
lO
-..J
lO
Values of R8, R9 and L6 have to be chosen ill accordance with the load capacitance.
The pins not mentioned are connected to ground except pin 5 of SAB1046 which is
connected to V CC.
CD
en
»
OJ
o
.,J::io.
0')
(J'I
1111111
SAB1046
APPLICATION INFORMATION (continued)
OV
7Z78974
+5V
+9V
OV
Fig. 7 Component layout of circuit shown in Fig. 6.
6
June
19791 (
F DIV
________
----------~------------jl----S-A-B-20-1-5--CONTROL AND STATION MEMORY CIRCUIT
V DD
124
ONOF
...E
H
MEMORY
PROTECTION
~
STATION MEMORY
16 x 8 BIT
RAM
-------CHANNEL COUNTER
CLCK
DATA
OLEN
GAP
POFF
RSET
VSYNC
AGC
STCL
NXCH
AFCON
STATION
COUNTER
1!
1
2
~l
IBUS RECEIVER
8
15
21
23
,----
I
•.:
1! 1
CENTRAL CONTROL
I
.!L
DBUS OUTPUTS
I
DISPLAY MODE
CONTROL
~ lL
~
i
14
1
10
13
SEARCH TUNING!
9
CHANNEL CHECK
PCEN
~ ADI
1L
3
BDI
MIST
17
11
PCDA
SILT
7Z74955
112
Fig. 1 Block diagram.
QUICK REFERENCE OATA
Supply voltage range
8 to 10 V
VDD
oto + 70
Operating ambient temperature range
Tamb
Clock frequency
fCLCK
typo
Quiescent current; VDO = 10 V; IQ = 0; Tamb = 25 °C
I DO
typo
0
62,5 kHz
4 IlA
PACKAGE OUTLINE
24-lead OIL; plastic (SOT-101A).
"I (
C
February 1979
jl___________________-----------
____S_A_B_2_0_15___
GENERAL DESCRIPTION
The SAB2015 is the station memory and control circuit for the frequency control IC SAB2024. The
device is implemented in LOCMOS, which requires only a small back-up battery to retain the station
memory contents during power interruptions. The SAB2015 is driven and controlled'via the serial data
instruction bus (IBUS). The instructions applied via the I BUS control the following functions:
•
•
•
•
•
•
The storage of up to 16 stations of the viewer's choice.
Direct station selection.
The bidirectional step station function.
Direct channel number access.
The bidirectional channel number step function.
Bidirectional search tuning through all channels with automatic stop on location of a television
transm ission.
• The recall of last viewed station at POWE RON.
• Automatic muting in case of absence of transmission.
Information is transferred to the frequency control IC SAB2024 and the on-screen display IC SAB1016
via the DB US station and/or channel select and display.
OPERATION DESCRIPTION
Data input
The SAB2Q15 can perform the instructions as listed in Table 1. The instructions are received in I BUS
code; the instruction code, synchronized with-the system clock, must be applied to input DATA. It
will be accepted only if the data enable input DLEN is HIGH at the same time (for details see IBUS
description) .
Four modes of I BUS instructions are available:
• Station call instructions ca'ri'-!;'1)qdify only the station counter, the memory contents, and the channel
".,
counter.
• Channel mode instruction will only alter the contents of the channel counter.
• Recall instructions reproduce only the last DBUS output and can change the display mode control
signals.
• The 'standby' instruction resets the system, while an unfinished instruction sequence will be aborted.
=
=
=
2
February
19791 (
l___
Control and station memory circuit
S_A_B_2_0_15_ _
Table 1. IBUS instruction set
IBUS
code
no.
I BUS input code
instruction mode
F
E
D
C
B
A
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1
a
a
a
a
a
a
1
1
1
1
a
a
a
a
1
1
1
1
1
1
a
a
1
1
a
a
1
1
a
a
1
1
a
a
1
1
a
a
a
1
a
1
a
1
a
1
a
1
a
1
a
1
a
1
a
1
1
1
1
1
1
1
1
1
1
a
a
a
a
a
a
a
0
1
a
a
1
0
0
0
0
0
a
a
a
a
1
1
1
1
a
0
a
1
0
1
1
a
a
1
1
a
a
1
1
0
a
1
0
1
1
1
a
1
a
1
a
1
a
1
a
1
a
1
1
a
1
a
1
2
3
4
5
6
7
8
9
set channel entry mode/on
search tuning up/on
search tuning down/on
step channel up/on
step channel down/on
mute/on
display short; 2,5 seconds
display ON/OFF
store
station call instruction
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
36
37
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
1
16
17
18
19
20
21
22
23
24
25
34
5
35
38
39
a
a
a
a
a
a
a
a
a
a
1
a
1
1
1
1
4
32
33
a
a
1
1
a
a
a
a
0
0
0
0
0
1
0
0
a
a
a
a
1
0
0
1
2
a
a
0
0
1
a
b
16/0n
lion
2/0n
3/0n
4/0n
5/0n
6/0n
710n
8/0n
9/on
la/on
l1/on
12/0n
13/on
14/on
15/on
step station up
step station down
channel mode instruction; digit
a
a
0
1
recall instruction
standby instruction
OFF
'I (
February 1979
3
J
SAB2015
Data output
Each instruction running on the I BUS is checked for transmission errors by the on-chip I BUS receiver.
Faultless received instructions are processed and start the output sequence,to the DBUS, which contains
13 data bits in binary code and one leading zero bit (see Fig. 2 and Table 2).
leading zero bit
display mode bit
bits for station number
bits for channel number
1
1
4
8
13th bit
,st bit
I Ic I I I Ic I I I Ic I I I
B
D
A
D
B
A
D
B
A
DMB
I
I
'--y------I '--y------I '---y----I '--y-----l "---y--J
units
2-digit
tens
1-digit
binary-coded
station number
display
mode bit
leading
zero
Fig. 2 OBUS
instruction format.
y
channel number
7Z74956
The 1st bit of a DBUS instruction (DMB) is a display mode bit with the following code:
DMB
instruction
display of station and c.hannel number
display of channel number only
0
1
Table 2. Specification of the DBUS code
DBUS input code
D
0
0
0
0
0
0
0
0
1
1
1
1
--
station
number
C
B
A
channel
number
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
a
a
1
0
1
2
1
3
0
1
0
1
0
1
0
1
0
1
0
1
4
5
6
16 .
1
2
3
4
5
6
7
8
9
7
8
9
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
blank
blank
blank
blank
blank
*
*
*
*
*
10
11
12
13
14
15
* Not processed by the SAB2015.
DBUS transmission is synchronized with the system clock. A data enable signal is available at output
PCEN in parallel with a data word at output PCOA (see Fig. 3). A DBUS sequence which possibly will
be followed by a tuning operation is started after a delay of about 30 ms related to the end of a
received instruction. The state of output SI LT changes from LOW to HIGH directly after acceptance
of an instruction, so click-free muting is achieved, even before the last selected transmitter is left.
4
1(
Fehrua" 1979
l
Control and station memory circuit
l-i_
SAB2015
ClCK H
II
.
--
tCl
PCEN H
L
PCDA ~ ~ start - bit
L
-D-M-S--r---A--.----S----r
"'-1
C
D
7Z74961
leading zero
Fig. 3 Timing diagram for channel and station number information on OBUS.
PROCESSING OF INSTRUCTIONS
1.
Station/digit instructions
Each station/digit instruction sets the display mode bit (OMB) in the OBUS transmission LOW
(except in case 1.1.3c)
1.1.
Set station number (1 to 16)
The processing of these I BUS instructions depends on the preceding instructions.
1.1.1. The corresponding digit will be stored in the station counter, if the instructions 'set channel
entry mode' or 'store' were not previously received. The channel number stored under that
address is read from the memory.
OBUS transmission:
, OM B = LOW'
1.1.2.
+
'station number
+
'stored channel number
Instruction 'store' previously given; two kinds of operation are possible:
a. Last instruction before the 'store' instruction was a 'channel mode' instruction. The station
number is then taken from the station counter and the channel counter contents are stored
under the new address in the RAM.
OBUS transmission:
, OMB = LOW /
+
'station number'
+
'channel number from channel counter
b. Last instruction before the 'store' instruction was a 'station' instruction. The channel number
which was stored under the 'old' station number is then restored in the RAM under the new
address or new station number.
OBUS transmission:
10MB = LOW!
1.1.3.
+
Istation number!
+
I stored channel number!
Instruction 'set channel entry mode' previously given; three kinds of operation are possible:
a. The instruction contains a digit which is greater than 9; the instruction is then not processed,
nor will there by any OBUS transmission.
b. The I BUS station/digit instruction, which is transferred, contains the first digit (0 to 9) of a
channel number.
OBUS transmission:
/OMB=HIGH/
+
'blank!
+
/1stdi9it+blank/
I(
February 1979
5
~
j~___~____________________________
__S_A_B2_0_15____
c. One digit has already been entered. The channel selection sequence is completed after the
second 'station/digit instruction and is transferred to the channel counter. This results in the
output of the channel number at the OBUS.
OBUS transmission:
10MB = HIGH
1.2.
I
Istation number I
+
+
Ichannel number from channel counter I
Step station (up /down)
The conten.ts of the station counter are incremented or decremented by 1. The channel number
stored under the new address is read from the memory.
OBUS transmission:
10MB = LOW
I
I station number ± 1
+
2.
Channel mode instructions
2.1.
Set channel entry mode/on
+
I stored channel number
Each channel instruction sets the display mode bit of the OBUS transmission to f:lIGH.
This instruction prepares the system for a direct entry of two digits for a two-digit channel
number.
OBUS transmission:
10MB = HIGH
2.2.
I
+
13 blanks
Step channel (up/down)
The execution of these instructions depends on the kind of the last preceding instruction.
a. The step channel instruction follows a station instruction. The channel number stored under
the preceding station number is incremented or decremented by 1, as long as there is no
identifying signal for unallocated channel numbers at input GAP (see note 1). The new
channel number is stored in the channel counter.
OBUS transmission:
10MB = HIGH
I
+
I station number 1
+
I stored channel number ± 1
b. The step channel instruction follows a channel instruction. The contents of the channel
counter are incremented or decremented by 1, as long as there is no identifying signal for
unallocated channel numbers at input GAP (see note 1).
OBUS transmission:
-.......==...
-
10MB = HIGH 1- +. I station number I·
+
channel number from channel counter ± 1
Note 1. Identification of unallocated channel numbers
The numbers in the series 00 to 99 are not all allocated in the CCI R standard TV channels, so it is
meaningless to step through channels which have no TV channel allocated. The frequency control IC
SAB2024 therefore produces at its output GAPa HIGH signal for channel numbers 00, 01,13 to 20
and 70 to 99 for as long as the circuit is not driven by an enable signal for special and cable TV
channels. The HIGH signal isapplied to input GAP of SAB2015 and causes rapid increment or
decrement of the channel number, until GAP is set LOW:
6
Febiuary 1979
J(
l___
Control and station memory circuit
S_A_B_2_01_5_ _
2.3.
Search tuning (up/down)
These I BUS instructions initialize an automatic step channel operation starting at the last
selected chc;tnnel (up or down) with one step to start with. Further stepping will happen if the
NXCH input is drawn HIGH. This is the case if the frequency control IC SAB2024 has run
through a micro-step tuning range and with the HIGH signal at its NXCH output demands that
the next channel number is given to the DBUS.
Due to the identification of unallocated channels at a HIGH signal at input GAP, atuning
. process in these ranges is suppressed also in case of search tuning.
DBUS transmission at NXCH = HIGH:
10MB = HIGH
I
+
Istation number I
+
channel number from channel counter ± 1
Search tuning stops automatically if a received transmission is suitable for viewing. A running
search operation can be stopped by the instructions:
station call
set channel entry mode/on
step station (up/down)
step channel (up/down)
OFF
3.
Reca" instruction
All these instructions lead to the repetition of the last preceding station or channel DBUS
transm ission.
4.
Standby instruction
The 'OFF' instruction resets the followihg signal processing circuit parts to the standby state:
search tuning
store
display (2,5 s)
set channel entry mode
The 'OFF' instruction starts no DBUS transmission.
5.
Display mode control outputs (ADI and BDI)
The state of the mode control signals ADI and BDI is determined by the input conditions
shown in Table 3.
Table 3.
input
POFF
1
0
0
0
0
0
store
set
channel
X
X
X
on-screen
display
(2,5 s)
1
X
X
0
X
X
1
X
X
X
X
0
0
0
0
0
0
1
1
0
0
----=
outputs
received I BUS instructions
search
tuning
(running)
on-screen
display
ON/OFF
ADI
BDI
X
X
0
0
1
X
X
1
0
0
0
0
0
1
0
1
1
1
o = IBUS instruction should not be received previously.
1 = I BUS instruction received.
X = eventually previously received IBUS instruction will be reset.
I(
February 1979
7
Jl_______________--__-------------
_____
SA_B_2_0_15____
6.
Television transmission identification; muting signal
In order to determine if a received transmission is suitable for viewing, particular timing
requirements of the input signals AFCON, AGe and VSYNC must be fulfilledlsee Fig. 4). The
automatic channel-check will be started in 2 cases:
a. By an instruction which starts a new tuning procedure.
b. When the automatic frequency control is switched off (AFCON = LOW).
For as long as the channel-check circuit has not recognized'a suitable transmitter, the circuit
produces a muting signal (S I LT = HI GH). The channel-check is finished, i.e. a transmitter is
recognized as suitable, if the following criteria are fulfilled:
a. Digital tuning must be finished, i.e. automatic frequency control is on (AF=CON = HIGH).
b. The tuner control voltage is switched on (AGC = HIGH).
c. Correct video sync pulses are present (VSYNC = HIGH).
If one of these criteria fails, then output MIST generates a micro-step pulse for switching over to
the next micro-step range and channel-check starts the next cycle.
STCL
JLJUL_...f"L_IL _____________
_JL.Il..f1..Iln.Ll..flI: _1-I1I ~ ~.::...rl-
peEN
~
CLCK
~
:::::l.. _____ _r----
AFCON
< TC>
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_____ : JC: :m: ~=:::III: : -: __1;.::;.81L,;,;19~
30131
10
,.-,
I
MIST
::::: 12ms delay
wait until
AFCON= HIGH
then test
rcv = HIGH
::::: 61 ms delay
=:: 49ms
check VSYNC
,I
restart
or stop
sequence
7Z60093
tYPH
r
l
tYPL
J
CLCK
n'-f1-JL
LJl.._
av·
I
~
L
VSYNC---1
. I
JlSU==U-
STCL ---~'-'-'....
___..r
check
distance
32 l
to FDIV
SAB 2024
from
SAB2024
Vtuning
FUP
200
k>l
AFCON
t---------------- SAB2024
SAB2015
100k>l
VSYNC
1 k>l
10nF
I
10nF
to
SAB2015
AFC
TDA2541
Fig. 8 Tuning interface and band select; used in combination with Fig. 6.
Rmax = 470
kn
Cmax = 560 nF
tv max
L...L..--&..-.-r--1-..oo.TICo
= 130 ms
tv max is the maximum delay which can be obtained
under worst-case conditions.
Fig. 9 Tuning constants at input TICO (Fig. 6).
June 1979
13
l__
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
S_A_B_2_02_1_ _
INSTRUCTION ENCODER
V DD
118
DMA
DMB
DMC
DMD
RESET
PA
PB
PC
PO
LP
13
12
11
KEYBOARD
v
SERIAL
r----l\
---y
i
17
a
ENCODER
OLEN
5
POL
CONTROL
~
15
--
14
CONTROL
WITH
3
DATA
6
AND OUTPUT
1
1
4
PARALLEL TO
TRANSLATOR
ENCODER
10
2
....
MEMORY
16
--..
MC
ONOF
CLCK
1
7
9
7Z76915
1
VSS
Fig. 1 Block diagram.
Features
• Parallel to serial keyboard encoder; used in the DICS (Digital Channel Select) system with the
SAB2015 and SAB2024.
• Parallel/serial conversion of 4-bit parallel information for station/channel selection in the tuning
system.
• External time constant for generating a delay time for key bouncing.
• Serial instruction output; compatible with the OICS IBUS interface.
QUICK REFERENCE DATA
Supply voltage range
VDO
Operating ambient temperature range
Tamb
Clock frequency
fCLCK
typo
62,5 kHz
100
typo
20 IlA
Quiescent current; VDO = 10 V; IQ
= 0; Tamb = 25 °C
4,75 to 10 V
o to + 70
PACKAGE OUTLINE
1a-lead 01 L; plastic (SOT-102A).
1
May 1979
°C
____S_A_B_2_0-2-1---Jl---~~------------------~------GENERAL DESCRIPTION
The SAB2021 is intended as a control circuit with parallel input for the serial instruction bus (IBUS)
of the DICS system (as shown in Fig. 2). The circuit can be used for local control of the tuning system.
The possibilities of the parallel inputs allow connection of remote control systems with parall~1 output
of instructions.
The device is implemented in LOCMOS technology.
to DICS tuning
and display system
SAS2015
rsus
CONTROL
INPUT
MATRIX
.I
I
I
STATION
SELECTION
MATRIX
I
--------_ ..
15
7ZS006S.1A
Fig. 2 Circuit SAB2021 providing local control.
2
May·1979
(
~~
___In_s_tru_c_tio_n_e_nc_o_de_r_____________________________
_____
s_A_B_2_0_2_1_____
OPERATION DESCRIPTION
Station/channel select inputs (PA, PB, PC, PD and LP)
A parallel instruction at inputs PA to PD generates the serial output of an IBUS data word. A data
word contains a coded digit instruction for 1 to 16/0, and is used in the tuning system (SAB2015)
for station call or direct channel selection.
Truth table 1. Station call instruction
inputs
output
LP
PA
PB
PC
PD
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
O.
0
0
0
1
0
1
0
0
1
1
0
0
1
X
0
0
1
0
1
1
1
X
X
ONOF
IBUS
code
no.
F
IBUS
instruction code
E
D
B
C
18
19
20
21
22
23
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
no outp ut 0 p eration
16
17
1
0
24
25
26
27
28
29
30
31
X
X
-
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
1
0
1
0
1
0
1
1
instruction (SAB2015)
channel
station
number
number
0/16
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
9
An IBUS data output can be initialized in 2 ways:
a. An output is initialized by an H/L transition at input LP (Fig. 3). The data word contains the coded
instruction at the inputs PA to PD. Station selection and direct channel selection in the tuning
system are possible in this mode. The inputs DMA to DMD overrule the LP signal.
b. When LP = LOW: the data word output is initialized by new information at the inputs (Fig. 4). Only
station selection is possible in this mode of operatio'1.
Only one I BUS data word is generated in both cases.
May 1979
3
jL_·______________________~__--__-
____S_A_B_2_0_2_l___
Lp
JBUS (DLEN)
Fig. 3 Output operation initialized by LP (load station); ,fC LCK = 62,5 kHz.
PA .. PD~......._ _ _ _ _ _ _ _+--
LP
--+1-*-----
,.
H
L----r-----------------~
JEWS (OLEN) _ _-+-_______--'1
~'I fctp ~641.l5
--"""'---1----+--17Z80095
1_64 <: tdOLEN < 96 <..,5)
Fig. 4 Output operation initialized by new information at inputs PA to PO; fCLCK = 62,5 kHz.
Tuning control inputs (OMA, OMB, OMC, OMO)
A parallel instruction at the input DMA to OMO generates one of 15 IBUS instructions for controlling
the tuning system. the arrangement is shown in truth table 2.
An IBUS data word is initialized if one or more of these inputs are switched from the quiescent state
HIGH to LOW. An output is only possible out of the quiescent state HIGH. A key operation at the
inputs must last until the IBUS data transmission is finished. Ifthe key contact is opened before
an output operation was initialized no output appears (Fig. 5).
The instruction via OMA to DMO is ineffective if an output operation, inith:ll.ized via the inputs PA to
PO and LP is in progress. If the bus-line is occupied (DLEN = HIGH) the output is delayed witil the
bus is free, and then carried out for as long as initialization is still present (Fig. 6).
---
4
In_u_ru_~_io_n_en_co_de_r
___
~~
___________________________
--_S_A_B_2_0_2_1____
__
Truth table 2. Tuning control instructions
inputs
OMA
OMB
OMC
OMO
F
IBUS
instruction code
0
C
E
B
1
1
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
,0
0
0
1
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
1
1
1
0
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
0
1
1
1
1
a
1
1
1
1
no
a
a
0
1
1
0
0
1
0
1
output
A
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
1
1
output operation
1
1
0
1
0
a
a
a
a
a
a a
a
a
ONOF
0
IBUS
code
nr.
a
5
33
32
38
34
4
35
39
36
37
2
48
49
50
54
-
-
0
a
0
a
a
a
a
1
a
-
1
0
0
-
instruction for
SAB2015
search tuning up
store
display on/off
step channel up
channel mode
display mode (2,5 s)
search tuning down
step channel down
step station up
step station down
off
fine detuning up*
fine detuning down*
finedetuning basic*
decimal 1*
no key information
~
* Not applicable for the SAB2015, but for SAB2022.
DMAIBICID
l_tdOM~~
I
-+________---lr~--------}"'""--------
IBUS (DLEN) _ _ _
1_
64 0)
VILT
----
Voo
Fig. 2 Single step change of a stored analogue value;
3
Jl_ - :. _______________
___
SA_B_2_0_2_2_ _
Key control inputs (TCA, TCB)
The ' inputs are coded instruction keyboard inputs and the addressed information can be changed via
both inputs.The inputs are effective, if the device is in.the normal mode and input CHAN is LOW.
The inputs operate by the following codes:
inputs
TCA
TCB
1
1
1
0
1
0
0
0
function
start position
step function down; decrease of analogue output value
step function up; increase of analogue output value
basic value; 50% of analogue value
The instructions are accepted only after a delay time tRC, in order to avoid erroneous information
caused by key,boun~ing. The delay time is determined by an ext~rnal RC circuit at terminal RC.
Each instruction, which is applied during the time ts (see Fig. 2), leads to a change in the memory
contents and thus of the analogue value by 1 step. If the instruction is applied for a longer period
(continuous operation) then there will only be a further change in the analogue value after a time tA
(see Fig. 3); Le: after a period of about 4 x tRC' Thus in continuous operation,automatic stepwise
changes can be achieved.
Basic set input (CHAN)
A HIGH level applied to this input generates the 50% analogue level (basic set) independently of
addressing at output FINE. The key control inputs TCA and TCB are i,nhibited. The CHAN signal is
effective during normal operation (LCA = LCB = LOW).
Mode control inputs (LCA, LCB)
The mode of operation is determined by the signals at inputs LCA and LeB.
inputs
LCA
LCB
1
1
1
0
1
0
0
0
operation mode
test
reset all internal flip-flops
stand-by (all outputs LOW)
normal
Time constant input/output (RC)
This terminal is an input of an internal Schmitt-trigger as well as an output for an external RC time
constant (opendrain, p-channel). An external capacitor and resistor in parallel (see Fig. 1) determine
a delay time for key bouncing suppression.
If TCA and TCB are HIGH, then the RC circuit will be continuously charged (start position). The
charging will be interrupted by a key instruction and discharging starts. Discharging is detected by the
trip level 'LOW' of the internal Schmitt-trigger and defines the end of the delay time. If alltomatic
step function is applied, RC will be charged with a pulse corresponding to 128 system clock periods in
duration (see Fig. 3).
4
May
19791f
":i.
111
c..
~
s:::
-,
CLCK
ADDRESS
TCA,TCB
Re
FINE
= : : : :nn...:: :nn.:-: :nn.::.:...n..rL : :.rut:
~
-t
:i.
~ .:.rut: :
:.nn.: : ::
:::= loQRIss STA~~:= ::.:==:.- = :: :.L1____
:=::J : : :
~
::::s
rtCLCK
--1-------1_-, -
n
:::;.
(')
s:::
;:;:
______________ --1
-Itc-
- _
tSA
~ I..
tA
~
-r- --r- - - ' - - ' - -r::.:::
2048· fcLcK + 4t RC
.;
I.
tA
-J-
n· tA--..1
~E~L-f=':= :)(." =====:'T::I.'l:::C::::':
CADA,CADB _ _ _ _ _
LCA
Ie
=LCB =LOW
!X'ln.21
JL __ --1L __ JL __ ~ __ JL __ JL __ JL __
tSA
=384 • tCLCK
-+- tRC
tRC .. RC . In -.Yill
VDD
tc = charge time =128· tClCK
7ZBD1DD
Fig. 3 Automatic step function.
:s:
I»
...
<
co
co
(J)
"
»
OJ
I\)
o
I\)
I\.)
U1
1111111
jl,__________~___________________
____S_A_B_2_0_2_2___
Analogue output (FINE)
The 5-bit word stored in the read/write memory (RAM) is converted into a pUlse-width modulated
signal and is available at output FINE. The signal is a pulse train with a repetition rate of 32 x 4 = 128
clock periods. Variation of 32 steps are possible.
step 1 :
final value; smallest analogue setting; reached by step function down; output duty
factor = 1/32.
step 15:
basic value (50%); attained when TCA = TCB = LOW or CHAN = HIGH or by step function;
duty factor = Y:!.
step 32:
final value; largest analogue setting; reached by step function up; duty factor = 1 (HIGH
output signal).
The analogue voltage corresponding to the pulse code at the analogue output is obtained by using
simple integrating networks.
Control outputs (CADf., CADB)
The control signals CADA and CADB present additional information, e.g. control of display and/or for
remote drive of the SAB2022. When an instruction on TCA or TCB is applied the corresponding
output (CADA, CADB) generates a single pulse per step. The pulse will be repeated with a time interval
tRC of the external time constant, because automatic step function is used (see truth table below and
Fig. 4). If a final value is reached the corresponding output ger;Jerates an output signal of % x fCLCK
with a duty factor of 0,5.
As long as TCA = TCB = LOW and output FINE generates the basic value or if CHAN = HIGH, a
frequency of 1/128 x fCLCK appears at both outputs CADA and CADS.
Truth table
inputs
TCA
0
1.
0
X
X
1
outputs
TCS
CHAN
CADA
CADS
1
0
0
X
1
X
0
0
0
1
0
0
P1
0
P1
P2
P3
0
0
P1
P1
P2
0
P3
X = state is immaterial
P1, P2 and P3: see Fig. 4.
-
6
operation mode
Mav19791 (
decrease of analogue output value
increase of analogue output value
.basic value; 50% of analogue value
basic value; 50% of analogue value
final value; step 1
final value; step 32
-n
:r
CD
Co
_-----II
tPI =
TCA or TCB
(key pressed)
-ltPII--
L
_
~
C
::I
5'
(,Q
2,
n
c
1_
;::;.'
'·ICLCK
=RC·ln -V-»O
VILT
_ _ ~RC
_
PI
-tRC
'
.
-no tRe
P2
I
DO
~I
__IL __ ~
1
tp2
= 2'fcLCK
T2
= fCLCK
T3
= fCLCK
128
n, T2
P3 _ _.........~
4
7280102
Fig, 4 Waveforms showing interrelationship between inputs TCA, TCB and outputs P1, P2 and P3 at CADA or CADB; see also truth table.
s:
III
..
<
co
-..J
co
(J)
»
OJ
I\)
0
I\)
-..J
I
N
1111111
Jl_______________________________
____S_A_B_20_2_2___
CLCK·
VDD
PRGD
CHAN
PRGC
RC
PRGB
4,
LCA
SAB2022
PRGA
5
LCB
FINE
6
TCB
CADB
7
10
VSS
8
9
TCA
CADA
7Z78903
Fig. 5 Pinning diagram.
PINNING
Inputs
1
2
3
4
5
10
11
12
13
15
CLCK
PRGD
PRGC
. PRGB
PRGA
TCA
TCB
LCB
LCA
CHAN
system clock; 62,5 kHz
)
1
J
}
address inputs (station inputs)
key control inputs
mode control inputs
basic set input
Input/output
14
RC
time constant output; Schmitt-trigger input
Outputs
6
7
9
8
FINE
CADB
CADA
analogue output
control outputs
Mav19791 (
F_in_ed_~_U~ni_ng_C_irc_ui_t
___
~~
__________________________
____·_S_A_B_2_0_2_2____
RATINGS (VSS = 0)
Limiting values in accordance with the Absolute Maximum System (I EC 134)
+ 11 V
+ VOO V
Supply voltage range
VOO
Input voltage range
VI
-0,3 to
± II
± 10
max.
10 rnA
max.
100 mW
. Input current
Output current
-0,3 to
max.
10 rnA
Po
Po
max.
50 rnW
Total power dissipation per package
Ptot
max.
300 mW
Operating ambient temperature range
Tamb
T stg
Power dissipation for outputs FINE, RC
Power dissipation for outputs CAOA, CAOB
Storage temperature range
o to + 70
-55 to
0C
+ 150 0C
CHARACTERISTICS
VSS = 0; T amb
= 0 to + 70 oC; unless otherwise specified
VOO
V
symbol
min.
typo
max.
conditions
Supply voltage
-
VOO
8
9
10
V
Supply voltage for
retention data
at stand-by
-
VOOR
3,3
-
-
V
Supply current for
retention data
at stand-by
-
IOOR
-
-
20
IlA
Supply voltage
transition rate
-
dVoo/dt
-
-
0,1
V/lls
Input leakage current
10
IIR
-
-
1
IlA
-IIR
-
-
1
IlA
8 to 10 VISL
8 to 10 VISH
0
-
1,5
V
VOO-1,5
-
VOO V
5,6
7,0
-
-
-
V
V
2,4
3,0
V
V
I nput voltage LOW
I nput voltage HI G H
all inputs VSS or VOO;
Tamb = 25 oC;
10=0
Tamb = 25 oC;
inputs 10 V
Tamb = 25 oC;
inputs VSS
Schmitt-trigger
input RC
Trip level HIGH
8
10
VIHT
VIHT
Trip level LOW
8
10
VILT
VILT
-
-
--
I(
May 1979
9
Jl. _______________
_ _S_A_B_20_2_2_ _
CHARACTER ~STICS(continued)
VSS
= 0; T amb = 0 to + 70 oC; unless otherwise specified
VDD
V
symbol
min.
typo
max.
conditions
Outputs CADA;
CADB; FINE
Output voltage HIGH
a to 10
VOH
VDD-1
'-
-
V
-IOH
Output voltage LOW
a to 10
VOL
-
-
1
V
IOL
a to 10
VOH
VDD-1
-
-
V
p-channel on;
-IOH = 1 mA
p-channel off
= 1 mA
= 1 mA
Output RC
Output voltage HIGH
Output leakage current
10
lOR
-
Clock frequency
a to 10
fCLCK
0
Input rise/fall time
ato 10
tr: tf
-
---
~
10
Mayt979
~(
-
.62,5
-
10
p.A
100
kHz
1
p.s
BAW62 (2x)
"5'
CD
c..
.....
+9V
CD
u ....."
C
sl
VSS
PRGA - -
PRGA
PRGB - -
PRGB
PRGC - -
PRGC
CPEN1--
PRGD
16
5
4
lSknn
3
~
Ir:lft.ll::
2
n
t;;
~
~
CADA
12
9
•. LCAI
7
13
ITCA
BAW62 (2x)
.....
co
-
:,~' '~7
..... ..( a,f,c.
I
cc
n
:;'
n
c
::i:
MODULE EQUIPPED
WITH TDA2541
nco
CADB
n,C.
ITCB
10kn
+9V~
....co
270kn
1-------BB105
11
10
~
+33V
SAB2022
14
<
5'
6
CLCK
4,7kn
::I
+9V
I I I
FINE +
BASIC
(J)
7Z78904
FINE-
Fig, 6 Typical application diagram for fine tuning,
......
1111111
»
OJ
I\)
o
I\)
I\)
________________________________~l___
·_S_A_B_2_0_24_.__- -
FREQUENCY CONTROL CIRCUIT
CHAN
NXCH
STCL
MIST
V DD
17
24
13 18
PCEN
-=-t------------~
PCDA
~------------+I
14 CLCKO
SAB2024
QRZ1
RSET
OSC
FOR
SEARCH
TUNING
AND
MICROSTEP
TUNING
1
TICO
11
15
16
AFCON
FUP
FDN
CATV 2
FDIV~7~-+~--~+_--------------------~------+1
22 21
20 19
GAP
VHFA
VHFB UHF
Fig. 1 Block diagram.
Features
•
•
•
•
•
Automatic band switching, determined by the channel numbers.
Micro-step tuning for unallocated frequencies.
Control signal for AFC on/off.
CATV channels available.
Improved selection in respect of adjacent channels.
--
QUICK REFERENCE DATA
Supply voltage range
VOO
Operating ambient temperature range
T amb
0 to
Oscillator input frequency
fQRZ1
<
Frequency divider input frequency range
fFOIV
0,3 to3,5 MHz
Quiescent current; VOD= 10 V; IQ = 0; Tamb = 25 °C
100
typo
8 to 10 V
+ 70 °C
4,5 MHz
PACKAGE OUTLINE
24-lead 01 L; plastic (SOT-101 A).
r(
May 1979
40 p.A
Jl~
_____
8_AB_2_0_2_4___
________________________________
GENERAL DESCRIPTION
The frequency control circuit SAB2024 measures continuously the oscillator frequency of the TV
tuner. Together with the prescalerand the tuner it forms the frequency locked-loop in the DICS
system (Digital Char.nel Selection). When a tuning procedure is started, the oscillator frequency of the
TV tuner is measured and corrected until the deviation in frequency found is within the specified limit.
After that the automatic frequency control (AFC) part of the TV set is switched on to complete the
tuning.
Frequency measurement
The actual measurement is done within a fixed time of 2048 flS, which is derived from the 4 MHz
crystal oscillator. Before the measurement starts, the frequency counter is loaded 'with the addressed
contents from the frequency ROM. This content is the binary equivalent of the desired oscillator
frequency of the tuner in MHz. The frequency counter is now decremented with the incoming
frequency applied at input FDIV within the 2048 flS. Any remaining frequency in the frequency
counter at'the end of the measuring time generates a pulse to outputs FUP or FDN with a duration
proportional to the tuning error. This pulse is used to modify the tuning voltage. By means of this, the
oscillator returns to the desired frequency within the range -337,5 kHz to + 787,5 kHz. When the
digital tuning is complete, the offset inaccuracy is set to -1337,5 kHz to + 787,5 kHz. The AFC is
then switched on to 'complete the tuning operation.
ROM program
As 'already mentioned, the ROM is programmed with the binary coded local oscillator frequencies
(x + 39) MHz, calculated from
fosc
= fcarrier + Lt. = (x,25 + 38,9)
MHz,
associated with 100 (00 to 99) channels as shown in Tables 1 and 2.
Channels 77 to 99 are reserved for the S-band, used in CATV systems. The unused channels are automatically bypassed, indicated by signal GAP being HIGH. The ROM also generates the required band
switch information as given in Tables 1 and 3. An adaption to Italian channels is possible (with the
SAB2034).
Micro-step tuning
To enable the location of transmission of unallocated frequencies, the DICS system incorporates the
micro-step tuning facility. Whenever a channel is selected and the TV transmission is not present, the
micro-step tuning will automatically come into operation (see Fig. 3). The local oscillator frequency
is detuned in five discrete steps away from the centre frequency in such a way that a complete coverage of the entire band is obtained.
If a station is not detected, the micro-step will be automatically continued, except for search tuning.
In that case a channel step will be done.
Whenever a TV carrier drifts in frequency and comes outside the AFC control range (see Fig. 2), the
micro-step tun,ing is restarted, thus within the channel range, the system follows the TV carrier.
Band switching and band ends
During band switching or during micro-step tuning, the system can tune to frequency areas outside th~
specified band ends. This results in an out of order situation for the control loop. A time constant is
generated to avoid unwanted system blocks. Ifthe tuner does not deliver the desired frequency in a '
time td (see Fig. 7) the output AFCON pulse will be set HIGH am;! the normal transmitter identification
will be started. The delay time td is externally controlled by an RC network connected to input TICO.
This delay time must be long enough, for the system to tune properly and reliably under all conditions
(see Fig. 12).
2
Mav19791(
___F_re_q_u_e_nc_y__
co_n_t_ro_l_c_ir_cu_i_t________________________________
~,J~~_ _
-S--A_B--2-0__2-4--------
Data bus instruction format
The format and timing of the DBUS is shown in Figs 4 and 5. Only the channel number information
is relevant to the SAB2024, namely, the channel number addresses the frequency ROM.
video carrier
corresponding to CCI R
digital tuning range
(1)
125kHz
AFC control range
1
1--
•
• -787,5kHz--337,5kHz
e.g. A1
--I
1-- 125 kHz
...----1337,5kHz
J
--~---;..~1-787,5kHz
7Z84089
(1) Possible error in frequency measurement.
Fig. 2 Digital tuning and control range.
-
May 1979
3
1111111
~
channel A
I•
s:
OJ
-5
-4
-<
-3
-2
7 MHz
-1
+1
- I
f\)
-\
;l
;j
+2
----.--
~
en
»
OJ
channel B
-2
-1
+1
'-I
fil
!lI
fjB4
VHF
~A3
~
filA4
~
filB2
II
t1B6
fJ
channel A
channel B
\.
-3
-2
.---- ,------.-
-.--
.1
8MHz
-4
-4
-1
\,
~
fitA6
-ll 1,375MHz _
_ I 1,375MHz 1_
-5
fJ
I[B3
E1
-
~B5
FJ
f;jA5
(MHz)
m
FJB1
r;lA1
+3
-,-- I
cD·
co
+2
+1
+2
+3
-2
-3
+4
-1
+1
+2
(MHz)
I
r---~--
~"'"'B""'1-------"'~
~A1
=ra
1[84
UHF
fitA4
~
r;lA3
f;jB5
r:1
fitA5
-
ij
I1J
fjB3
-
~
tilB2
f:jA2~
~B61
~A6
~
~
--I'
1-.
~
375kHz
--I
1--
375kHz
Fig. 3 Micro-step tuning. The shaded 125 kHz areas are maximum tuning errors.
7Z71674
oI\)
~
Jl___
S_A_B_2_0_2_4___
_F_r_eq_U_en_c_y_co_n_tr_o_1c_ir_c_ui_t_ _......:._ _ _ _ _ _ _ _ _ _ _
Table 1. DICS channel numbers and allocated TV channels (VHF).
CATV = 0
channel designation
DICS
channel number
special
channels
European
channels
VHF A
VHF B
CATV
VHF A
=1
VHF B
frequency
range
47 MHz
2
3
4
77
78
79
68 MHz
[ij
l
S2
S3
89 MHz
104 MHz
80
Ml
81
M2
82
M3
83
M4
84
M5
85
M6
86
M7
87
88
M9
89
Ml0
M8
5
E5
6
E6
E7
7
8
9
E8
E9
10
El0
11
Ell
12
90
E12
L.-_.J--l- - - - - -
91
U2
U3
--
U4
94
U5
95
96
97
U6
99
230 MHz
Ul
92
93
98
174 MHz
U7
U8
U9
Ul0
300 MHz
'I
(May 1979
5
jl~____________~__________~___
_____
S_AB_2_0_2_4___
Table 2. DIGS channel number (ROM addresses) and the allbcated frequencies (VHF andUHF).
i
address
DIGS
channel
number
video
carrier
freq.
MHz
fosc
ROM
contents
MHz
address
DICS
channel
number
video
carrier
freq.
MHz
fosc
ROM
contents
MHz
address
DICS
channel
number
video
carrier
freq.
MHz
fosc
ROM
contents
MHz
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
44,25
44,25
48,25
55,25
62,25
175,25
182,25
189,25
196,25
203,25
210,25
217,25
224,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
471,25
479,25
487,25
495,25
503,25
511,25
519,25
527,25
535,25
543,25
551,25
559,25
567,25
83
83
87
94
101
214
221
228
235
242
249
256
263
83
83
83
83
83
83
83
83
510
518
526
534
542
550
558
566
574
582
590
598
606
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
575,25
583,25
591,25
599,25
607,25
615,25
623,25
631,25
639,25
647,25
655,25
663,25
671,25
679,25
687,25
695,25
703,25
711,25
719,25
727,25
735,25
743,25
751,25
759,25
767,25
775,25
783,25
791,25
799,25
807,25
815,25
823,25
831,25
614
622
630
638
646
654
662
670
678
686
694
702
710
718
726
734
742
750
758
766
774
782
790
798
806
814
822
830
838
846
854
862
870
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
839,25
847,25
855,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
69,25
76,25
83,25
105,25
112,25
119,25
126,25
133,25
140,25
147,25
154,25
161,25
168,25
231,25
238,25
245,25
252,25
259,25
266,25
273,25
280,25
287,25
294,25
878
886
894
83
83
83
83
83
83
83
108
115
122
144
151
·158
165
172
179
186
193
200
207
270
277
284
291
298
305
312
319
326
333
!
i
Note: ROM content is fosc = fcarrier + i.f. = x,25 + 38,9 = (x + 39) MHz.
6
May
~9791
(
l
Frequency control circuit
SAB2024
~--------------------
Table 3. Truth table of output signals for determining receptiQn range of TV tuner.
(Jutputs
channel number
CATV
VHF A
VHF 8
00,01; 13 to 20;
70 to 76
a
1
1
1
02 to 04
0
1
1
1
05 to 12
0
1
21 to 69
UHF
GAP
a
a
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
77 to 80
0
1
1
1
0
0
0
0
1
0
81 to 99
0
1
0
0
1
1
0
0
1
0
13 th bit
I
Die
I I I
8
A
Die
I I I
B
A
Die
I I I
B
A
DMS
I
I
' - - - y - - / ' - - - y - - / '----y----I '---y--J '---y--J
tens
1-digit
units
2-digit
binary-coded
station number
display
mode bit
leading
zero
y
channel number
7Z74956
Fig. 4 D-8US instruction format.
CLCK
PCDA
~
D
W@
7Z74961
Fig. 5 Timing diagram for channel and station number information on D-BUS.
May 1979
7
~ S_A_8_20~2_4 ~jl~_____________________________
___
__
r
.
measuring time
tuning time
2,04Sms -----..,...,....; - - - - 2,04Sms - - -...·~I
(jnt!~;a~~) ______,
~I-----------......I!I
STCL
-
321ls (VHF)
SIlS (UHF)
1-___ -
FUP/FDN
-------------------------------+--~
AFCON
7Z84090
Fig. 6 Timing diagram for signals STCl, FUP, FDN and AFCON.
threshold of input TICO
------
r-·----------------ILJ-LSl_JL
~121ls
AFCON
normal case
~
-.1
1_
204SJLs
(1) Minimum time for charging the external capacitor (C).
(2) Delay time for AFCON is HIGH.
Fig. 7 Charging time and delay time waveforms for terminal TICO.
See also Fig. 12.
8
Mav1979
~
(
7284091
l___
Frequency control circuit
S_A_B_20_2_4_ _
PINNING
RSET
V DD
CATV
CHAN
VDD
VSS
positive supply
negative supply (OV)
1
RSET
reset signal; a HIGH at the
input causes zero setting of
the whole .circuit
enable signal for cable TV
channels (see Table 3)
D-BUS data enable signal
D-BUS data input
input for the devided TV
tuner oscillator frequency
quartz crystal input
control signal for micro-step
tuning; ranges 1 to 6
24
12
Inputs
PCEN
VHFA
TEST1
VHFB
2
CATV
PCDA
UHF
3
GAP
7
PCEN
PCDA
FDIV
NXCH
9
17
QRZ1
MIST
4,6
TEST1, 1
TEST2
connect to VSS
5
TEST2
FDIV
TlCO
8
17 MIST
QRZ1
9
16 FDN
f
Input/output
OSC
15
AFCON
VSS
FUP
14 CLCKO
8
TICO
interrupts tuning process;
releases control signal (from
SAB2015) for micro-step
tuning
13 STCL
12
7Z84092
Fig. 8 Pinning diagram.
Outputs
10
11
13
14
15
16
18
19
OSC
AFCON
STCL
CLCKO
FUP
FDN
NXCH
GAP
20
21
22
23
UHF
VHFB'
VHFA
CHAN
quartz crystal output
automatic frequency signal; HIGH = AFC on
search tuning clock; repetition rate 2,048 ms
system clock; 62,5 kHz
tuning voltage control output for tuner oscillator frequency up
.tuning voltage control output for tuner oscillator frequency down
control signal for channel step during search tuning
identifying signal for unallocated channel numbers during channel search tuning
(GAP = HIGH; channel number to be bypassed)
band switch output for UHF band IV!V
band switch output for VHF. band III
band switch output for VHF band I
HIGH state indicates channel function: e.g. channel search tuning
May 1979
9
jl____________----________________
_____
S-AB_2_,O_2_4___
RATINGS (VSS = 0)
Limiting values in accordance with the Absolute Maximum System (IEC 134)
-0,3 to
+ 11 V
Supply voltage range
VOO
I nput voltage range
VI
-0,3 to VOO V
Input current
± II
max.
10 mA
Output current; all outputsexcept TICO
±IO
max.
10 mA
Output current; TICO
+10
-10
max.
max.
35 mA
10 mA
Power dissipation per output; except TICO
Po
max.
50 mW
Po
max.
200 mW
Ptot
Tamb,
T stg
max.
,Power dissipatiqnoutput TICO
Total power dissipation per package
Operating ambient temperature range
Storage temperature range
o to
300 mW
+ 70 0C
-55 to + 150 °C
CHARACTE R ISTICS
VSS = 0; Tamb = a to + 70 oC; unless otherwise specified
VDO
V
symbol
min.
typo max.
conditions
Supply voltage
-
VOO
8
9
10
V
Quiescent current
per package
10
100
-
-
100
/lA
I
\
Input leakage current
10
IIR
-
-
1
/lA
I
I
-IIR
-
-
1
/lA
I
0
-
0,3VOO V
I
I nput voltage LOW
8 to 10 VIL
8 to 10 VIH
Input voltage HIGH
IQ =0'
inputs to VOO orVss
Tarnb = 25 oC;
inputs 10 V
J Tarnb"" 25 oC;
inputs VSS
O,7Voo -
VOO
VOO-1
-+
-
V
-'-10 =0,6 mA
-
-
1
'V
.!ci = 1,9 mA
V 00""" 1 -
-
V
-IQ =2,4 rnA
-
-
1
V
IQ = 3,8 mA
-
-
50
/lA
VQ = 10V
1
V
IQ = 30 mA
V
Outputs; except
OSZ;CLCKO;TICO
--
Output voltage fi I GH
8 to 10 VQH
8 to 10 VQL
Output voltage LOW
Outputs OSZ;CLCKO
Output voltage HI G H
Output voltage LOW
I
8 to 10 VQH
8 to 10 VQL
Output TI CO
open drain n-charmel
Off-current
10
Output voltage LOW
May
19791 (
IQ
~_ to 10 VQL
-
~~
___F_re_q_u_e_nc_y_c_o_n_tr_o_l_ci_rc_u_it_________________________________
VDD
V
SymbOI~n.
-+
Clock frequency
8 to 10 fCLCKO
Input frequency
ORZ1; FDIV
8 to 10 fl
Duty factor
ORZ1; FDIV.
8 to 10 8
Input rise/fall time
typo
max.
conditions
kHz
62,5*
4,5
0,2
S_A
__B__2_0_2__4______
______
MHz
0,8
t6 tf
* Equals fORZ1/64.
I.
May 1979
11
SAB2024
L_'_ _
~~
to/from tuning interface (Fig. 11 )
~
if
VSYNCr
AFCON
FDN
FUP
~
.n
4MHz
~STCL
VSS
~ VSYNC
15 GAP
to
SAB2013
(1)
to
{
SAB1016
from {
power
on/off
control
(Fig. 10)
14
13 STCL
l.L-
---1?
L.TSTB ~
OLEN
18 PCOA
17 MIST
I
18 NXCH
19 BDI
TSTO
L-
19 GAP
TSTA
4
20 UHF
21 POFF
TSTC
22
MIST '3
L
21 VHFB
--.ll.
...n. CHAN
!--
23 RSET
DATA
24 VDD
CLCK 1
+9V.1.1
\.--y--I
IBUS
VHFA
VDO
'-y--'
ITO~
~
f11---
J:2PF 1150 PF
OSC 10
FUP
20 ADI
0NOF
AFCON
---1.§. FDN
NXCH 9
:----ll
. VSS
14 CLCKO
AGC ,lLVDD
L~ PCEN
SILT
-
AFCON
QRZl
.,.
'"
'"~
0
N
rL--
TlCO
r!L--
FDIV
rZ--+-- from pre - scaler
TEST2
PCDA
TESTl
PCEN
from timing control (Fig. 12)
H
rL~
fL-
CATV 2
RSET
H
VDD~
band switching
normal
"/
7Z74957.A
(1) Output SI LT can be used for muting during channel mode operations and/or dark tuning.
Fig.9 Interconnection diagram of the SAB2015 and SAB2024 used in a tuner circuit.
toSAB2015
~
RSET
voo
POFF'
VDD (+9V)
-;:
.
~
+
9V
1
SILT
(1) Operate button to clear station memory of SAB2015 after battery charge. System reset pu Ise
RSET will remain LOW if tuning operation is in progress.
r
1
Fig. 10 Power ON/OFF circuitry; used in combination with Fig. 9.
12
May 1979
___
Fr_e_q_ue_"_c_y_C_o_"t_ro_l_c_ir_c_ui_t______________________________
--'~ ~,
S__A_B__2_0_2__4_______
_____
+9V
UHF
VHFB
FREQUENCY
DIVIDER
SAA1009A
and SAB1046
VHFA
FDN
39 kn
to FDIV
SAB2024
- - . . - - - - . - - + 33 V
from
SAB2024
Vtuning
FUP
BAW62
200
kn
AFCON
~--------------------------~SAB2024
SAB2015
lOOkn
lkn
10nF
AFC
1--C::::J~Vc..:Sc..:..Y.:.:.N.::..C+ ~~B 2015
100kn
10nF
I
TDA2541
Fig. 11 Tuning interface and band select; used in combination with Fig. 9.
--
+9V
Rmax = 470
kn
Cmax = 560 nF
td max = 130 ms
non
J-t--4--C::::J- TICD
tdmax is the maximum delay which can be obtained under
worst-case conditions.
Fig. 12 Tuning constants at input TICD (Fig. 9).
June 1979
13
______________________________jl____
SA_B_2_0_34____
FREQUENCY CONTROL CIRCUIT
for Italian TV channels
/
/
The SAB2034 frequency control circuit is identical to the SAB2024 except for the ROM content
which is adapted to the Italian channel frequencies.
The proper frequencies for the channels A to L are programmed under the channel numbers 02 to 11
as shown in the ROM content below.
address
DICS
channel
number
video
carrier
freq.
MHz
fosc
ROM
contents
MHz
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
44,25
44,25
53,75
62,25
82,25
175,25
183,75
192,25
201,25
210,25
217,25
224,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
471,25
479,25
487,25
495,25
503,25
511,25
519,25
527,25
535,25
83
83
92
101
121
214
222
231
240
249
256
263
83
83
83
83
83
83
83
83
83
510
518
526
534
542
550
558
566
574
Italian
channel
A
B
C
D
E
F
G
H
L
E12
address
DICS
channel
number
video
carrier
freq.
MHz
fosc
ROM
contents
MHz
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
543,25
551,25
559,25
567,25
575,25
583,25
591,25
599,25
607,25
615,25
623,25
631,25
639,25
647,25
655,25
663,25
671,25
679,25
687,25
695,25
703,25
711,25
719,25
727,25
735,25
,743,25
751,25
759,25
767,25
775,25
582
590
598
606
614
622
630
638
646
654
662
670
678
686
694
702
710
718
726
734
742
750
758
766
774
782
790
798
806
814
,
I
I
Italian
channel
N.B. Table continued on next page.
"
May 1979
__
__ ____ ____ _____________
~_S_A_B_20~3_4 ~Jl~: ~ ~ ~
__
Table continued
address
DICS
channel
number
video
carrier
freq.
MHz
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
783,25
791,25
799,25
807,25
815,25
823,25
831,25
839,25
847,25
855,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44;25
44,25
fosc
ROM
contents,
MHz
I
Note: ROM content is fosc
822
830
838
846
854
862
870
878
886
894
83
83
83
83
83 :
83
83
83
83
83
May
address
DICS
channel
number
video
carrier
freq.
MHz
fosc
ROM
contents
MHz
80
81
82
83
84,
85
86
87
88
89
90'
91
92
93
94
95
96
97
98
99
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
44,25
83
83
83
83
83
83
83
83
83
83
83
83
83
83
83
83
83
83
83
83
= fcarrier. + i.f. = x,25 + 38,9 = (x + 39) MHz.
---- .
2
Italian
channel
19791(
Italian
channel
)l
------------------------------------------------------'
SAB3011
----------------~---
REMOTE TRANSMITTER
MOA MOB MOC
14
GCLS
GCL
15
Vss VOO
13
OSCILLATORI
DIVIDER
12
24
POLSE
CODE
MODULATOR -
KEYBOARD
SCANNER/COUNTER
MATRIX/SENSE
zzzzzzzz
zzzzzzzz
wwwwwwww
O~NM-..:rLf)tDr--
UlUlUlUlUlUlUlUl
MATRIX/DRIVE
zzzzzzzz
O~NM-.4'Lf)tDr--
»»»»
0::0::0::0::0::0::0::0::
a a a a a a a a
7Z80076
Fig. 1 Block diagram.
Features
•
•
•
•
•'
•
Transmitter for 2 x 64 commands.
One transmitter for two types of equipment, e.g. radio and television.
Very low current consumption.
Particularly suitable for infrared or ultrasonic transmission modes.
Transmission by means of a pulse code modulation.
Short interval between operation and re-operation of the same key, due to automatic double word
spacing.
QUICK REFERENCE DATA
Supply voltage range
VOO
7to
Operating ambient temperature range
Tamb
o to +70
10 V
Minimum oscillator input frequency
fOCLS
Quiescent current
VDO = 10 V; IQ = 0; Tamb =25 °C
100
0C
4 MHz
typo
1 p.A
PACKAGE OUTLINE
24-lead OIL; plastic (SOT-101A).
January 1979
Jl__________________
_ _-S-AB_3-0_,11______
GENERAL DESCRIPTION
When a key is depressed the oscillator starts running and the keyboard is scanned. The drivers are
a'ctivated one at a time and during each driver~on period, the sense lines are sequentially scanned.
This operation is controlled by the scanning counter such that the value in the counter represents the
code of the key being scanned. The counter is stopped when the activated key is located. This mode of
operation is particularly free from interference, so the SAB3011 can also be used for AM/FM radio
receivers. A serial pulse train is now produced at the signal output (REMO), and is suitable for infrared
or ultrasonic transmission. Each operation of a key produces transmis~ion ofa double 7-bit data word,
in which the binary code elements are represented by different periods between the pulses.
The data word is repeated continually for as Iiong as the key is depressed, at least one repetition. After
release of the key, or after the first repetition, the circuit automatically returns to the standby state.
The SAB3011 is specifically designed for battery powered operation~ It is fabricated using LOCMOS
techniques to provide a circuit that consumes very little power. At standby, with no key operated, the
oscillator is switched off, so only leakage currents determine the current consumption; minimum battery
load.
The serial pulse code-train used is specially developed for infrared or ultrasonic transmission. Due to
the particular requirements of both media on the one hand, and the transmitter elements on the other,
there are different pulse formats for the two modes of operation. Application in the local mode differs
only very slightly from the infrared operation mode. The principle is the same for all modes of
operation. The binary code elements are represented by pulse separations to, which follow one another
as a series in time. As well as the two pulse separations too and t01 used to represent '0' and '1', there
are also two further time separations tow and tos involved (see Figures 2 and 3). tow serves to
separate words transmitted directly after each other, whiisttOS separates double words when the same
key-command is given. Thefour tim~ s~parations too, tOl, tow andtOS are in the ratio 9: 11: 14: 19
for ultrasonic mode, and 5: 7: '14: 19 for infrared and local mode.
2
January 1979
(
____
~l
__R_e_mo_te_tr_an_sm_itt_er_______________________
REMO HL
~I------'I
--.JI
-I:pw 1_'0_.
S_A_8_3_0_11____
pulse width: tpw = 3tUD
unit delay: tUD = 1,024 ms
at fO = 4 MHz
1
7Z82013
tD = tDO = 9tuo
to=tD1 = 11tuo
tD = tDW= 14tUO
tD = tDS = 19tUD
represents logical '0'
represents logical '1'
word separation
double word separation
Fig. 2 Output signals of the SAB3011 for ultrasonic transmission.
REMO
:~ _____~lli
--11I
tM
I:-t
pw
-
•
tD
7Z79343
fO=4MHz
tM = 112tO
1
= 28 p.s
tpw = 5,5tM = 154 p.s
to = - = 250 ns
fO
fM = J....= 35,7 kHz
tM
fpW = 6,5 kHz
tD
tD
tD
tD
represents logical '0'
represents logical '1'
word separation
double word separation
unit delay: tu D = 4096to = 1,024 ms
at fO = 4 MHz.
= tDO = 5tUD
= tD1 = 7tUD
= tDW = 14tUD
= tDS = 19tUD
Fig. 3 Output signals of the SAB3011 for infrared transmission.
January 1979
3
SAB3011
L""----_ _ _ _---.---
OPERATION DESCRIPTION
Mode programming inputs (MOA, MOB, MOC)
test.
The SAB3011 has several modes of operation like a reset, ultrasonic, infrared, local,
The
operation mode is determined by the inputs MOA, MOB and MOC as shown in Table 1. Input MOC
also determines the polarity of the start bits of each command wo~d.
Table 1. Mode programming.
mode inputs
MOA MOB MOC
a
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
mode
a
0
a
a
reset
ultrasonic
infrared
local
test
ultrasonic
infrared
local
1
1
1
1
start bitS
(=MOC)
0
0
0
0
1
1
1
1
Sense inputs (SENON to SEN7N)
These terminals are the sense inputs of the 8 x 8 key-matrix. If no key is operated, all sense inputs
are HIGH due to internal pull-up elements.
Driver outputs (DRVaN to DRV7Nl
These outputs are drivers for the 8x 8 key-matrix, and are open-drain n-channel transistors. At standby, all drivers are active; i.e. conductive to VSS. During scanning only one driver at a time is conductive to VSS (low-ohmic), while all the other drivers are high-ohmic. Duringthe output process, a driver
remains conductive, if its line locates an operated key.
The arrangement of the IBUS code number for the keyboard is shown in Table 2.
Output (REMO)
--,--.
4
The signal output REMO.is LOW during standby. During signal transmission, 7 'bits are transmitted in
the sequence: S, A, B, C, D, E, F. Bit'S' is a start bit, and is determined by the logic level at MOC (see
Table 1). The code ofthe bits A to F is defined by the 64 key-matrix positions, which are obtained from
the crossing-over of the 8 sense inputs and the 8 drive outputs (see Table 2 and Fig. 6).
External circuitry and examples of circuits for infrared and ultrasonic transmission are shown in the
section APPLICATION INFORMATION.
January, 1979
(
R_em_o_~_tra_ns_m_it _er
___
jl____S~A_B_3_0_11
__
________________________
~
Table 2. Arrangement of IBUS code for the keyboard.
SAB3011 inputs
SEN. N
ORV. N
IBUS
code no.
F
SAB3012 IBUS code
E
0
C
B
A
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
oto 7
o to 7
oto 7
oto 7
o to 7
1
2
3
4
5
6
7
8 to 15
16 to 23
24 to 31
32 to 39
40 to 47
48 to 55
56 to 63
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
000
000
000
000
000
000
000
to
to
to
to
to
to
to
111
111
111
111
111
111
111
o to 7
o to 7
Oscillator input (OClS)/output (OCl)
Input aClS is the system clock input for local operation. Ouput aCl serves as driver for the oscillator
external circuitry (see Fig. 4).
alC
alCS
alC
QlCS
10Mn
(a)
(b)
----
7Z82012
Fig. 4 Typical external oscillator circuitry: (a) crystal oscillator; (b) LC oscillator.
Data for coil in Fig. 4(b):
Frame core: FXC grade 401 ;,catalogue no. 3122104 91480
Screw core: FXC grade 401; catalogue no. 3122 104 90590
Coil former: catalogue no. 4312 021 29670
Number of turns: 25 turns enamelled Cu wire (0,08 mm)
') (January
1979
5
Jl
SAB3011
key-matrix
sense inputs
SEN6N
VOO
SEN2N
ORV7N
SENON
ORV6N
SEN1N
4
21 ORV5N
SEN3N
5
20 ORV4N
SEN5N
6
positive supply
key-matrix
drive outputs
19 ORV3N
SAB3011
l
osc. input
SEN4N
7
18 ORviN
SEN7N
8
17 ORV1N
QClS
9
16 ORVON
osc. output
QCl 10
15 MOB
remote data
output
REMO 11
MOA
ground
VSS 12
13 MOC
}
mo~econtwl
mputs
7Z77997
Fig.5 Pinning diagram.
RATINGS (VSS = 0)
Limiting values in accordance with the Absolute Maximum System ( I EC 134)
--
--
~
VOD
-0,3 to
I nput voltage range
VI
"":'0,3 to + VDD V
Input current
II
max.
10 mA
Negative input current
-II
max.
10 mA
Output cu rrent
IQ
max.
10 mA
Negative output current
-IQ
max.
10 rnA
Power dissipation per output
PQ
Ptot
max.
50 mW
Total power dissipation per package
Operating ambient temperature range
Storage temperature range
6
+ 11 V
Supply voltage range
Janua~.1979 ~
(
Tamb
T stg
max.
o to
300 mW
+10 °C
-55 to' +150 0C
~l._.~__
S_AB_3_0_11_____
__R_em_o_te_tr_an_sm_it_te_t_________________________
CHARACTERISTICS
VSS = 0; T amb = 0 to + 70 oC; unless otherwise specified
VDD
V
symbol
min.
typo max.
Supply voltage
-
VDD
7
-
10
V
Supply current
10
IDD
-
-
10
J.l.A
{ 10 = 0 **
VSEN.N = VDD
10
10
II
-II
-
-
-
1
1
J.l.A
J.l.A
VI = 10 V **
VI =OV **
I nput voltage LOW
7 to 10
VIL
0
-
0,3VDD V
Input voltage HIGH
7 to 10
VIH
0,7VDD -
Input current
7 to 10
-II
20
Input voltage HIGH
7
VIH
0,7VDD -
Output vo'itage LOW
7 to 10
VOL
-
-
1
V
10 = 1,5 mA
Output voltage HIGH
7 to 10
VOH
VDD-1
-
-
V
-10 = 2,7 mA
Output voltage LOW
7 to 10
VOL
-
V
10 = 1,5 mA
7 to 10
VOH
VDD-1
-
1
Output voltage HIGH
-
V
-10 = 0,6 mA
7 to 10
VOL
-
-
1
V
10 = 1,5 mA
10
10
-
-
J.l.A
J.l.A
Va =
-
5
1
4
MHz
conditions
Inputs MOA; MOB;
MOC; OCLS
Input current
{
VDD
V
250
J.l.A
VI =OV
-
V
-II = 1 J.l.A **
Inputs SENON to
SEN7N *
-
Output REMO
Output OCL
Outputs DRVON to
DRV7N
open drain n-channel
Output voltage LOW
10
Output leakage current {
10
-----
10 V
Va = 10 V **
Input OCLS
Minimum input
frequency
7 to 10
fOCLS
-
-
Duty factor
7 to 10
0
0,45
0,5 0,55
Input rise/fall time
7 to 10
tr: tf
-
-
50
f = 4 MHz
ns
Sense inputs with p-channel pull-up transistor.
At Tamb = 25 °C.
January 1979
7
~~_SA_B_3_0_11__~jl~____________~____--___________
APPLICATION INFORMATION
5. 7
z z
0
z z
en en
en en en
w
0
8
16
16
17
18
19
20
21
22
56
mode programming
inputs
---.=-
-
{
23
13
15
14
11
~
w
w
8
6
z z
M
V
z z
w w
z
N
z
z z
z (0
It)
......
z z z
w
w
en en
w
en
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
SAB3011
DRV5N
'DRV6N
DRV7N
MOC
MOB
MOA
REMO
~
GClS
10
~
~r
OSCi~~TOR
~DI7Z79364
Fig. 6 Typical remote transmitter circuit using SAB3011.
8
January
19791 (
___
,J~
__R_e_m_ot_e_tr_an_sm
__
itt_er_____________________________
--S-A-B--3_0_11______
+9V
1.Jl...r
-
Fig. 7 Ultrasonic transmitter circuit.
Characteristics
f = 40,5 kHz
L34 = 10,4 niH
0=65
transmission distance: 11 to 14 m
4,7nF
drive signal
from REMO
(pin 11, SAB3011) '-----+---+--t
10nF
~--~----4-_I,--o+9V
7ZB0075
-----
Fig. 8 Ultrasonic transmitter circuit.
Characteristics
f= 40 kHz
L13 = 60 mH
0=65
p (1 m)
1000
330
mA
Pa
5
12
0,85
1,3
transmission
distance (m)
10
15
.1(
January 1979
9
_____S_AB~3_0_11~~jl-:~__~__________________________
APPLICATION INFORMATION (continued)
24
33fi
Voo u--+--__----1r--1
220jJF(16V)
1----+--11
H
~I
SAB3011
REM 0
BZX 75
C1V4
V
ss
12
Fig.9 Infrared transmitter circuit.
§;,',.',
F
10
January 1979
(
Jl
~-------------------------------------------------'
SAB3012
'---------------------
RECEIVER AND ANALOGUE MEMORY
MOSAI
MOSBI
24
12
ANDA
OUTPUT CONTROL
AND
STATION COUNTER
RSIGI
ANDB
DATA
DLEN
CLCK
RESTI
LOCA
LOCB
LOCC
~~~
LOCD
ANALOGUE MEMORY
LOCE
VOLU (Ana/I)
BRIG (Anal 2)
SATU(AnaI3)
CONT (Anal I.)
7ZS0DSD
RSVI
OFF RSV2
Fig. 1 Block diagram.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
. Receiver for 2 x 64 commands in two versions: SAB3012 for TV, SAB3012A for radio.
6 +1 bit code word and the command group (1 bit) are ~ask programmed.
Infrared operation: LC or crystal oscillator at the transmitter.
Ultrasonic operation: crystal oscillator at the transmitter.
Four 63-step analogue memories with 0/ A converter; basic setting 28/63.
Short response time (speed for altering the analogue memories):
infrared: 115 ms/step; 7,2 s/63 steps.
ultrasonic: 85 ms/step; 5,4 s/63 steps.
ON/OFF (standby) output.
Serial instruction output (I BUS),
High security against interferences.
Fast operation, even with the same key, due to double word separation test.
Inputs for local operation via encoded keys; up to 31 commands.
Coded outputs for display of analogue. signals.
Supply voltage: 5 V.
---
=
QUICK REFERENCE DATA
Supply voltage
Voo
Operating ambient temperature range
Tamb
Clock frequency
fCLCK
typo
62,5 kHz
IDO
typo
20 mA
Supply current at VOO
= 5 V; Tamb = 25 °C
typo
5 V
o to + 70
PACKAGE OUTLINE
24-lead 01 L; plastic (SOT-101A).
'(Januar.1979
0C
Jl
SAB3012
'---------------------------------------------------
~--------------~----
GENERAL DESCRIPTION
The circuit is implemented in N-channel MOS technology. Serial data is derived from the transmitter
SAB3011 in remote or extended local operation mode. This data is applied to the RSIGI input, where
it is checked and decoded and serially applied as commands to the IBUS. Some commands are also
used internally for control of 4 analogue functions and the station memory. Moreoveri the circuit has
available an input/output for the ON/OFF function, two auxiliary outputs for reserve commands, and
the choice of two outputs for control of the on-screen display of the analogue values, or for numeral
display control.
For normal local operation, five inputs are available, via which -31 different commands are parallel
addressable.
/
Special features:
• -Serial interface for 64 commands.
• Universal control functions for sub-systems: e.g. tuning systems, Teletext, Vieyvdata, video games,
clock with addressable memory etc.
• After operation of a sub-system, the analogue functions and the, ON/OF F function remain under
direct control.
• Capability for use inan operation mode with parallel station outputs.
O,PERATION DESCRIPTION
Remote control data input (RSIGI)
Serial data is derived from the transmitter in remote or local operation mode. This data is applied to
the RSIGI input (see Fig. 2), where it is checked and decoded. The instruction bus (IBUS) is then
enabled and an output operation takes place.
Response times:
infrared: ~ 110 ms.
ultrasonic: ~ 170 ms.
The following tests are carried out for each signal or signal group:
• Dead-time, time between two pulses.
• Word separation.
• Double word separation.
Signals which do not come within the zero or one 'window', restart the input detection procedure.
The commands are transmitted as 7-bit words (1 start bit, 6 data bits). The receiver circuit SAB3012
is mask-programmed for start bit S = 0; but a version is also available for radio use, the SAB3012A
for S = 1Table 1 shows the I BUS-codes.
zero time
(to)
one time
(to)
7,2 ms ± 1 ms
7,2 ms ± 0,13 ms
5,1 ms ± 1 rt;s
5,1 ms ± 0,13 ms
RSIGI
infrared
operation mode
I RA (wide window)
IRB (narrow window)
iJ- to-_.r:
Fig. 2 Specification of the timing of the input signal.
2
January 1979
~.
(
tp
= 1',1 ms
an~a_IO_g_U_e_m_e_m_o_r_Y
___R_e_ce_iv_e_r_a_nd__
________________
~~,-
____S_._A_B
__3_0_1_2________
local keyboard inputs (LOCA, LOCB, LOCC, LOCO and LaCE)
Up to 31 commands (see Table 1) for local control are possible by addressing these 5 inputs from a
binary encoded keyboard. A keyboard input (local control) overrides the remote control commands
at input RSIGI (from SAB3011). Current IBUS output data is completely isolated.
r
key up
r
key down
______________:1:11...1r""1'-'II"'"IIr--~IlllL..,....-r-~
LO-C-A-tO-LO-C-E---;II""'lI-'I-'I'1
~
r
key down
16 I.-bouncing time
ms
rSingle command
debounce ____ 16
time
ms
1..-
7ZB0077
Repetition rate: 2/second x TR = 510 ms
8/second x T R = 129 ms
Fig. 3 Relationship between key operation and command output.
Mode control inputs (MOSAI, MOSBI)
The SAB3012 can decode either infrared or ultrasonic transmission. Pulse code modulation, as used in
the SAB3011, offers good performance for a wide range of applications. In view of optimum performance, particularly in respect to the power requirements of the transmitter,pulse widths are matched
to the transmission path. This requires a matching of the time window at the receiver in order to
achieve the greatest possible freedom from interference.
mode
inputs
MOSAI
MOSBI
operation
output
oscillator freq.
transmitter
1
2
3
0
0
1
0
1
0
infrared
infrared
ultrasonic
IBUS
IBUS
IBUS
4 MHz ± 14%
4 MHz ± 0,8%
4 MHz ± 9°/
10
4
1
1
infrared
parallel
4 MHz ± 14%
wide window
small window
station number
register available
Test input (TEST)
Normally grounded.
~ (Janua~
1979
3
~~_S_A_B_30_1_2 jl~·_______________·_'_____________
___
Table 1. Specifications of the IBUS-code
RSIGI/
instruction code
inputs
IBUS
code
wC U aloe(
no.
UU U U()
00
00 F E o C B A *,.j
...1...1
...1...1
U
9
0 0 0 0 0
0 0 0 0 1
0 0 0 0 1
0 0 0 1 0
1 1 0 1 0 0 0 0 1 0
0 0 0 1 1
0 0 0 1 1
8
9
10
11
12
13
14
15
------
16
17
18
19
20
21
22
23
0
0
0
0
0
24
25
26
27
28
29
30
31
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0
0
0
0
0
0 0
o 0
1
1
1
1
0
0
0
o ~O 0
0 1
0 0
1 1
1 0
0 1
0 0
1 1
1 0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
0
0
0
0
0
0
0
0
1 0
t 0
1 0
1 0
1 0
1 0
1 0
1 0
0
0
0
0
1
1
1
1
1 S
0 S
1 S
0 R8
1 S
0 S
1 S
N
>
en
a:
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
S
S
S
S
S
S
S
S
0 1 1 0 0 0 S,
0 1 1 0 0 1 S
0 .1
0 1
0 1
0 1
0 1
0 1
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
0
1
0
1
0
1
S
S
S
S
S
S
R8 = repeat ~ 8/second
V : miJte control
January 1979
~(
;::)
~
«z
0
> «
...I
(I)
S
Ual «
C() ( ) ( ) ()
«Z «Z «cZ alc
Za: a: a: a:
« « « «0.. 0..0.. 0..
...I
29/ 29/ 29/ 29/
63 63 63 63
0
0
1
o
0
0/1
0
0
n
Jl
O. R8
1 R8
o R8
1 R8
o R8
1 R8
o R8
1 R8
* Instruction class (CL.): S = single
4
....
u. >
u. en
0 a:
0 0 0 0 0 0 S
0
1
2
3
4
5
6
7
outputs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
U
U
U
U
U
V
Lf
V
V
U
U
U
U
U
'U
1 1 1 1
0 0 0 0
0 0 0 1
·0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1
1
1
1
1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
l___
Receiver and analogue memory
S_A_B_30_12_ __
IBUS
code
no.
SAB3012
SAB2013
0
basic set analogue
basic set analogue
-
1
2
3
4
5
6
7
mute/on
off
reserve A
on
on
reserve B
reserve C
mute/on
off
display of mode (2,5 s)
mode reset
display of mode (2,5 s)
.search tuning up
...,..
on
on
-
SAB2015
8
9
10
11
12
13
14
15
-
-
volume up
volume down
brightness up
brightness down
saturation up
satu ration down
contrast up
contr~st down
16
17
18
19
20
22
23
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
station 16/0
1/1
2/2
3/3
4/4
5/5
6/6
7/7
24
25
26
27
28
29
30
31
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
station 8/8
9/9
10/11/12/13/14/15/-
i1'
-
-
-
-
-
-
-
~
-
~. (
January 1979
---
5
Table 1. Specification of the I BUS-code (continued)
RSIGI/
inputs
instruction code
IBUS,
code
w 0 ()CO <
no.
() () ( ) ( ) ()
0 0 00 0 F E D C B A
-J -J -J-J -J
32
33
34
35
36
37
38
39
1 1 1 0 1 1 0 0
1 1 1 0 0 1 0 0
1 1 1 1 0 1 0 0
1 0 0
1 1 0 0 1 1 0 0
1 1 0 0 0 1 0 0
1 1 0 1 1 1 0 0
1 0 0
40
41
42
43
44
45
46
47
1
1
1
1
1
1
1
1
0 1 0
0 1 0
0 1 1
0 1 1
0 0 0
0 0 0
0 0 1
0 0 1
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
outputs
*..J
()
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
0
0
1
0
1
R8
R8
R8 .-
48
49
50
51
52
53
54
55
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
S
S
56
57
58
59
60
61
62
63
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0 S
1 S
0 S
1 S
0 R2
1 R2
0 R2
1 R2
1
1
1
1
1
1
1
1
0
LL
LL
1 0 0 0
R8
0 1 0 0 1 R8
R8
1 R8
R8
6
: change of station counter
JanuOiy
19791 (
(J)
(J)
a:
>
a:
:::>
N
-J
('t)
.q-
-J
-J
<
z z<
0
> < <
-J
S
* Instruction class (CL): S = single
U : mute control
.-
..
0
0
1
1
0
0
l
1
l
Receiver and analogue memory
SAB3012
-----------------------
IBUS
SAB3012
code
no.
32
33
34
35
36
37
38
39
-
40
41
42
43
44
45
46
47
volume up
volume down
brightness up
brightness down
saturation up
saturation down
contrast up
contrast down
48
49
50
51
52
53
54
55
-
56
57
58
59
60
61
62
63
on
on
on
on
on
on
SAB2013
on
on
on
on
on
on
-
-
-
SAB2015
display on/off
store
channel mode
search tuning down
step station up
step station down
step channel up
step channel down
-
-
-
-
-
-
.-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I.
January 1979
7
l_________-
SAB3012
IBUS outputs
Outputs DATA and OLEN are inverted.
.
Proper commands are available for the duration of a key operation as a single command or repeated
commands, in accordance with the sub-system requirements (see Table 1). The following output modes
are provided:
• Single command; e.g. digits.
• Repetition rate: 2/second; e.g. step functions.
• Repetition rate: 8/second; e.g. analogue functions.
The IBUS command is available at output DATA synchronous with the system clock; the word length
is 7 bits, one start bit and 6 data bits.
CLCK
H
L
I
H
OLEN
~
.
I
I~I-----------------'i
F_~_~~'"
DATA L_lstart-bit 1
...__A_........_._B_........__
C_-'-__i5_-'-__E_........__
I.
command code bits
•
I
7Z79348
Fig. 4 Output waveforms of a command transmission.
Various word formats can be transmitted between the sub-systems, so it is necessary that each receiver
should carry out recognition of a word format. Word formats which do not correspond with the
requirements have no effect on the system. It is also necessary that all sub-systems which receive or
supply information to the BUS-line should check whether or not the BUS is occupied, if yes, the
output is delayed. Output OLEN acts as an input for this procedure. The output delay amounts to
7 x tCLK == 112 JlS.
--
~
8
January
19791 (
l___
Receiver and analogue memory
S_A_B3_0_12_ _
Analogue memories
The SAB3012 contains four 63-step memories for analogue functions. The speed of stepping depends
upon the transmission rate of the remote control; e.g.:
infrared transmission: 115 ms/step.
ultrasonic transmission: 85 ms/step.
Stepping through the full range takes:
infrared transmission: 7,2 seconds.
ultrasonic transmission: 5,4 seconds.
When operating inthe local mode, via inputs LOCA to LaCE, the stepping speed is 129 ms/step; 8,1
seconds for the full range.
The analogue values are represented by rectangular pulses of 1 kHz; the duty factor determines the
analogue values. The analogue voltage is available at the output of an externally connected low-pass
filter.
ihe command (0) 'basic. setting' presets the analogue memory to a mid-position (29/63).
After switChing-on the supply, the analogue memories are preset via input RESTI to position 29/63.
ihe volume control out~ut (VOLU) is set LOW, respectively enabled by the toggle command mute (1).
ihe volutne output Will tje set LOW for a short period TS (see Fig. 5) by the following commands:
step 16 to 31.
statioh 1 to 16/0 to 9.
step 36 to 39; station step up/down and channel step up/down.
Muting will be resetby the following commands:
mute command (1).
volume up command (40); the volume output increases starting from LOW.
. basic setting command (0).
OFF command (2).
In the standby mode, output OFF
= HIGH, the analogue memories cannot be changed.
January 1979
9
. ,. . ,. . ,. ., ., . ,~S. . ,A_B3Q~_.12~.~_)l_~
..
__- ,. __~---,..._~_---:----,..._~
key operation (local control)
30ms
debounce - time
VOLU
signal RSI G I: word comparison effective
(remote control)
m
E%?i1
I~--'-
OLEN
---.--1
U
TS
Fig. 5 Timing diagram for muting atstation and channel selection.
HSIGI mode
(from SAB3011)
TS
infrared transmission
ultrasonic transmission
local operation
230 ms
170 ms
260 ms
Input/output OFF
OFF is the output of a flip-flop (ON/OFF-flag). If this output is LOW, the system is in the ON-mode;
if HIGH, the system is standby (OFF). The sy'stem is set to the standby mode by a reset at input REST!.
Terminal OFF operates as an input in standby. Forcing to LOW (set time ~32 J,Ls) makes the chip
operational, e.g. switching on via a wiping contact on the mains switch.
Reserve outputs (RSV1 and RSV2)
RSV1 is the output of a flip-flop, which toggles after the proper received command reserve A (3). The
output is also set LOW by a reset at the input REST!.
RSV2 generates a single pulse by the command reserve B (6); duration of the pulse:
RSIGI mode
(from SAB3011)
110 ms
85 ms
. infrared transmission
ultrasonic transmission
Command reserve C (7) sets RSV2 HIGH with a duration of a key-down operation; error-free reception is assumed.
-
10
January 1979
(
l__. .
Receiver and analogue memory
S_A_B......
3_01......
2_ _
Display of analogue values outputs (ANDA and ANDB)
Both outputs carry information Goncerning the changes in an analogue function. This information can
be used to control the display of the analogue function.
Some examples of display:
•
•
•
•
Bar graphs with changing colour identification.
Multiple bar graphs.
Numerical display ofthe activated analogue function.
Multiple numerical display of the analogue values.
I.
CLCK
n
H
I
n
L--~~
~I
63 xtcLcK
n
11·
~,~
n
~-
-
-
-
-
-
-
-
r1
~
u
r1 r1
~
u
r1
u
I .
,..., ru w
r1
I
ANALOGUE
.
H
l
I
-----,_ _ _ _.-.Ir - - - - +--.I
I
ANDA
~ ~-------------I
I
H
ANDB
L
___ ~__
--+-IJ---:--""'L
address coding of
analogue function
Fig.
6
7Z80078
Output signals for display applications.
Analogue memory states:
analogue function
VOLUME
ANAL2
ANAL3
ANAL4
ANDA
ANDB
o
o
o
1
1
1
o
1
January 1979
11
SAB;3012
trigger
volume (anal 1)
trigger
brightness (anal 2)
trigger
contrast (anal 4)
trigger
saturation (anal 3)
ANDS----------------~~
7Z77996
Fig. 7 Example of a circuit showing the generation of the analogue signals.
Internal station counter outputs (PRCA, PRCS, PRCC, PRCD)
By applying a HIGH level to inputs·MOSAI and MaSSI, the outputs,ANDA, ANDS, DATA and
OLEN are switched-over internally to the station counter.
The following arrangement has been made:
terminal
ANOA
ANOS
DATA
OLEN
station counter
PRCA
PRCS
PRCC
PRCO
The station counter outputs are coded as shown in Table 1.
tfthe stationcounter contains a command, the volume output (VOLU) is set LOW for a short period
(mute). The change of the station counter is obtained during the mute period (see Fig. 5).
12
January 1979
(
l___
Receiver and analogue memory
S_A_B_30_1_2_ _
data in
RSIGI
VSS
clock
CLCK
LOCA
reset
RESTI
LOCB
TEST
LOCC
CONT
LOCO
SATU
LOCE
analogue
outputs
BRIG
local
keyboard
ANOB} analogue display
signals
ANOA
VOLU
OFF
DATA}
__
IBUS information
OLEN
T {RSVl
auxi lary .
outputs
RSV2
MOSSI}
mode control
MOSAI
VOO
1Z77999
Fig. 8 Pinning diagram.
RATINGS (VSS = 0)
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage
VOO
max.
7,5 V
I nput voltage
VI
max.
15 V
Input current
II
max.
10 mA
Negative input current
-If
max.
10 mA
Output current
10
max.
10 mA
Negative output current
-10
max.
10 mA
Power dissipation per output
Po
max.
50 mW
500 mW
Total power dissipation per package
Ptot
max.
Operating ambient temperature range
Tamb
T stg
-20 to + 70 0C
Storage temperature range
-55 to + 150 0c
January 1979
13
)l__-________"____-_--.....,,,
2
_ _S-.A_'8_30_'.1__ _
CHARACTERISTICS
VSS == 0; T amb = 25 oC; unless o~h,erw!se specified
,
,
VOD
V
.~ymbol
min.
typo
max.
conditions
V
Supply voltage
-
VOO
4,5
5,0
5,5
Supply current
5
100
mA
5
IIR
-
25
Input leakage current
-
1
IJ.A
I nput voltage lOW
5
Vil
-0,3
~
0,8
V
I nput voltage HI GH
5
Y.IH
3,5
-
10
V
Output voltage
open drain; lOW
5
-
1
-
-
15
V
V
lal
5
Val
VaH
-
Output voltage HI G H
-
-
1
V
lOt
-
..;:..
15
V
laH
-
-
rnA
Val -YaH
V I = -0,3 to + 10 V
Outputs DATA, OLEN, OFF,
RSV1 , RSV2,AN OA,AN DB
laH
= 2,5 mA
= 20IJ.A
Outputs VOlU, BRIG,
CONT, SATU
Output voltage
open drain; lOW
5
Output voltage HIGH
5·
Val
VaH
Input OFF current
set to standby mode
5
IOFf
15
Clock frequency
5
fClCK
56;25 62,5 68,75 kHz
Duty factor
5
0
0,4
0,5
0,6
-
I nput rise/fall time
5
t6 t f
-
-
1
IJ.S
:
--=--
. January 1.97.9
(
= 6 mA
= 20 IJ.A
-/ II I /
APPLICATION INFORMATION
:J:J
~
~.
+12V
Q)
~
c..
Vss VOO
INFRARED
AMPLIFIER
TD81033
I----------- 2 x T CLCK) externally arid it is continuQuslyin the enabled state when ENQ is connected to ground.
Terminal ENQ has art open drain output stage, so it needs an external pull-up resistor.
4
May
1979l (
IB_U_S_~_b._~_sm_m_i_nt_erl_a_~
__
,J~_____
S_A_8_3_0_1_7______
_________________________
f
LCK
iBUS
OLEN
DATA
PA,PB,PC
H
L
~----,
H~
L
startbit
~=x
old
value
PD,PE,PF
VP
ENO
LX
LX (pulse
operation)
I
~~@
A
B
C
is
acting as inputs
E
F
c::::J\
output
L
output
new value
old value
H
X
new value
old value
H
U-
L
x::=
H
L
H
L
x::=
On
On+1
H
U-
L
7279619
Fig. 4 Timing diagram for the output signals_
Outputs (LA, LB, Le, LD, LE)
The operation mode of these outputs is determined by an internal mask-programmable command
decoder (see Table 2).
Table 3 shows the mode of the mask-programmed output stages for the standard version SAB3017 A.
The signals LA to LE can only be changed when the circuit is in the enabled state (ENO = LOW)_ For
each single output, the commands x or x and y determine the addressed output_
A group of commands can be specified for x and y, which have a common bit pattern.
The outputs LA to LE are open drain outputs, so they need external pull-up resistors.
Terminals LA to LE also operate as inputs: for the functions m = 0, T or RS, they can be set LOW by
applying a LOW pulse (T> 2 x T CLCK) externally_
Reset
The SAB3017 automatically initiates a reset cycle after switching on the supply. ifhe outputs PA to
PF are then LOW; the outputs VP, LA to LE and ENO are then HIGH_
May 1979
5
~ ~~~~~ ~~~ ~~_
SAB3017
___
____
Table 2. Possible functions at 1he outputs
L~
____
to LE.
, ,
operation mode
m
circuit enabied(ENO = 0)
output is
ou~put is
set (LOW)'
reset (HIGH)
by
by
circuit is disabled
(ENO=l)
D
c,ommand x
HIGH
= latch
all other commands
except x
T
= toggle
command x
command x
latest state is maintained
RS
p
= ,set/reset
command x
command y
latest state is maintained
= pulse
LOW pulse, initiated by command x
HIGH, no pulse
Table 3. Decoded outputs for the standard version SAB3017 A.
IBUS~
code
no.
14
15
16
17
18
19
20
21
22
23
32
45
further
I
I
'
outputs PAto PF
LA
F
E
D
C
B
A
0
0
0
0
0
0
0
0
0
0
1
1
X
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
X
1
1
1
0
0
1
1
0
0
1
1
0
1
X
0
1
0
1
0
1
1
1
0
1
X
1
0
0
0
0
1
1
1
1
0
1
X
1
0
1
0
1
0
0
X
°n+1
On
On
On
On
On
On
On
On
On
On
On
On
On
LB
m
°n+1
1
1
1
1
1
1
1
LC
m
T
m
1
1
RS
RS
RS
RS
RS
RS
RS
RS
1
1
1
1
0
1
1
1
°n+l
On
On
1
1
1
D
1
an
0
On
LE
LD
RS
°n+1
0
1
1
1
1
1
1
1
1
1
1
1
1
m
P
°n+1
1
0
1
1
1
1
1
1
1
1
1
1
1
m
P
l___
I BUS sUb-system interface
S_A......
B __
30_1_7_ _
CLCK
Vss
PC
2
17
VP
PB
3
16
LA
PA
4
15
LB
OLEN
5
14
LC
DATA
6
13
LO
PF
7
12
LE
PE
8
11
PO
ENQ
9
10
VOO
SAB3017
7Z79615
Fig. 5 Pinning diagram.
PINNING
1
10
VSS
VOO
negative supply (0 V)
positive supply
5
6
18
OLEN
DATA
CLCK
data line enable input
data input
clock input
4
3
2
11
8
7
PA
PB
PC
PO
PE
PF
16
15
14
13
12
LA
LB
LC
LO
LE
1
address inputs
parallel data outputs
decode outputs/set inputs (LOW)
I
9
ENQ
enable input/output
17
VP
data valid - pulse output
'I (
May 1979
7
Jl___--__------------------------
_____
SA_B_3_0_17____
RATINGS (VSS = 0)
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage range
VOO
Input voltage range
VI
Output voltage range
Va
Input current
±II
±IO·
. Output current
Power dissipation per output
Po
Total power dissipation per package
Ptot
Operating ambient temperature range
Tamb
T stg
Storage temperature range
-0,3 to +7,5
-0,3 to +15
o to +15
max.
10
max.
10
max.
50
max.
300
o to +70
V
V
V
mA
mA /
mW
mW
°C
-55 to +150 °C
CHARACTERISTICS
V SS = 0; T amb = 0 to +70 oC; unless otherwise specified
Voo
V
-
VOO
4,5
Supply current
5
5
5
5
5
5
5
5
100
-
Input voltage HIGH
Input leakage current
Output voltage lOW
Output leakage current
Clock frequency
Input rise/fall times
8
min.
Supply voltage
Input voltage lOW
-=
symbol
VIH
-0,3
3,5
IIR
-
Val
-
lOR
-
Vil
10
fClCK
tr:tf
-
typo
5
14
62,5
-
conditions
max.
5,5
V
-
mA
1,2
15
1
1
20
70
1
V
V
= -0,3 to +15 V
IlA
VI
V
10 = 1 mA; open drain
IlA
Va
kHz
IlS
= 15 V
(HIGH)
l___
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply. that the device will go into production
S_A_B_3'O_2_2_ _
RECEIVER AND ANALOGUE MEMORY
V DD
Vss
12
AUTOMATIC RESET
4
DECODER
RSIGI
17
CLCK
LOCA
LOCB
LOCC
LOCD
LOCE
18
16
15
2
23
22
21
20
8
7
ANALOGUE MEMORY
6
5
19
MODEP
-
'PRGA
PRGB
PRGC
PRGD
VOLU
ANAL2
ANAL3
ANAL4
7Z74914.1
RSVA
OFF
RSVD
RSVB
Fig. 1 Block diagram; infrared receiver.
Features
• Receiver for 2 x 64 comm~nds. 6 + 1 bit code word (selectable).
• Four 63-step analogue memories with O/A converter; basic setting 50% (31/64); VOLU 30% (19/64)
or 50% (31/64).
• Short response time (speed for altering the analogue memories):
115 ms/step; 7,3 s/63 steps.
• ON/OFF (standby) output.
• Serial instruction output (IBUS).
• High security against interference.
• The output signals of the station memory and the IBUS commands are available simultaneously.
• Inputs for local operation via diode-encoded keys; up to 31 commands; mask-programmable.
• Various repetition rates at the IBUS for single commands, step commands (2/second) and analogue
commands (a/second).
• Outputs for sub-systems.
QUICK REFERENCE DATA
Supply voltage
VOO
typo
Operating ambient temperature range
Tamb
o to +70
Clock frequency
fCLCK
Supply current at VOO = 5 V; Tamb = 25 °C
5 V
62,5 kHz
typo
100
20 mA
PACKAGE OUTLINE
24-lead 01 L; plastic (SOT-101A).
0C
I(
June 1979
--
SAB3022
GENERAL DESCRIPTION,
The circuit is implemented in N-channel MaS technology, Serial data is derived from the transmitter
SAB3011 in remote or extended local operation mode. This data is applied to the RSIGI input, where it
is checked and decoded and serially applied as commands to the I BUS. Some commands are also used
internally for control of 4 analogue functions and the station memory. Moreover, the circuit has available an input/output for the ON/OF F function, three auxiliary outputs for reserve commands, each
containing the station-change signal and a sub-system identification signal. For local operation, five
inputs are available, via which 31 different commands a.re parallel addressable (can be chosen by maskprogramming).
Special features:
• Serial output for 64 commands.
• Universal control functions for sub-systems, e.g. tuning systems, Teletext, Viewdata, videogames,
clock with addressable memory, etc.
- . • After addressing a sub-system, the analogue functions and the reserve functions remain available.
• Parallel station outputs.
OPERATION DESCRIPTION
Remote control data input (RSIGI)
Serial data is derived from the transmitter in rem'ote or Icreal operation mode. This data is applied to
the RSIGI input (see Fig. 2), where it is checked and decoded. The instruction bus (IBUS) is then
enabled and an output operation takes place.
Response time for infrared operation: :::::: 110 ms.
The following tests are carried out for each signal or signal group:
•
•
•
•
Dead-time, (time between two pulses).
Word separation.
Bit counting .
Word comparison.
Signals which do not come within the zero or one 'window', restart the input detection procedure. The
commands are transmitted as7-bit words (1 start bit, 6 data bits). The system will accept leading '0'
command (start bit S = 0) for RSVO = HIGH and leading '1' commands (S = 1) for RSVO= LOW.
Table 1 shows the IBUS-codes.
lero time
one time
(to)
(to)
5,1 ms ± 1 ms
5,1 ms ± 0,13 ms
7,2 ins ± 1 ms
7,2 ms ± 0,13 ms
infrared
operation mode
I RA (wide window)
IRB (narrow window)
RSIGI
•
to - - - _..~I
7279347.1
tp=l,lms
Fig. 2 Specification of the timing of the input signal.
2
June 1979
(
l___
Receiver and analogue memory
SA_B_3_0_2_2_ _
Local keyboard inputs (LOCA, LOCB, LOCC, LOCD and LOCE)
Up to 31 commands (see Table 2) for local control are possible by addressing these 5 inputs from a
binary encoded keyboard. The inputs are drawn internally to VDD at standby. Out of the 64 commands 31 can be stored in the·mask-programmable ROM with the desired key addresses. This ROM
can be chosen by the user. The ROM of the standard version SAB3022B (see Table 2) is programmed
by the manufacturer. A keyboard input (local controll overrides the remote control commands at
input RSIG I (from SAB3011). Current I BUS output data is completely stopped.
r
LO-C-A-to-LO-C-E--''""'I,.....,I......I....'
--.
r
key down
key up
I
key down
_________~----;I::1~I""'"~1..,'---rWIL"I"'T""n
16 I.-bouncing time
ms
rSingle command
debounce
time
I
16
ms'--
~~32
7ZBOD??
ms
Repe~ition rate: 2/second x TR = 516 ms
8/second x T A = 129 ms
Fig. 3 Relationship between key operation and command output.
-
'I (
February 1979
3
ll1lffr
0l:Io
en
»
CO
Table 1. Specifications of the IBUS-code (continued on next page).
"T1
CD
C'"
2
Q)
-<
to
to
......
RSIGI/
IBUS
code
no.
0
1
2
3
4
5
6
7
F
E
D
C
B
A
0
0
0
a
a
a
a
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
8
9
10
11
12
13
14
15
O' 0
16
17
18
19
20
21
22
23
0
24
25
26
27
28
29
",...
0
1
a
a
a
a
1
1
1
1
1
0
a
0
1
a
1
0
1
0
1
0
1
0
1
0
1
0
a
a
0
0
1
1
1
1
0
a
a
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
a
a
0
4
a
4
c.u
function
instruction code
a
1
1
0
1
0
1
,...
*..,j
u
basic set analogue
mute/on
OFF
reserve A
on
on
reserve B/on
reserve C/on
S
S
S
S
R8
S
S
S
-
R8
R8
R8
R8
R8
R8
R8
R8
on/station ·16
1
on/
on/
2
on/
3
4
on/
on/
5
on/
6
on/
7
S
S
S
S
S
S
S
S
8
9
10
11
12
13
4A
reserve D'"
-
-
-
on/
on/
on/
on/
6n/
on/
..
,
u.
u.
0
«
>
en
a:
N
co
>
en
a:
:::J
....J
0
>
**
....J
«
z
«
('I)
....J
«
z
«
o::t
....J
«
z
«
c..
Cl
>
en
a:
w
Cl
0
~
«
U
U
c..
c..
a:
u
U
a:
1
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
1
1
1
1
1
,1
n
1
1
a:
co
c..
Cl
U
a:
c..
31/64 31/64 31/64
a
0
1
1
0/1
0
0
0
0
1
n
n
U
0
0
0
a
0
0
a
U
U
U
U
U
U
U
0
U
S
S
S
S
S
S
0
0
0
0
0
0
U
U
C"
n
U
U
U
U
U
U
u
U
U
U
U
U
U
U
U
U
U
U
, r
, r
1
0
1
0
1
0
0
0
0
0
0
0
oI\)
I\)
~
c:
:J
(l)
co
-....J
co
32
33
34
35
36
37
38
39
1
40
41
42
43
44
45
46
47
1
48
49
50
51
52
53
54
55
1
56
57
58
59
60
61
62
63
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
s
on
on
on/step station up
on/step station down
on
on
S
S
S
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
volume up
volume down
ANAL2 up
ANAL2 down
ANAL3 up
ANAL3 down
ANAL4 up
ANAL4 down
R8
R8
R8
R8
R8
R8
R8
R8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
-
S
S
S
S
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
* Instruction class
0
1
0
0
1
1
1
on
on
on
on
on
R8
R8
R8
R8
R8
station memory
disconnected
(eL.): S = single
R2 = repeat ~ 2/second
RS = repeat ~ 8/second
0
0
0
0
0
0
:lJ
~
:C!"
~
U
U
CIl
U
X
X
U
X
X
X
X
X
X
:J
Q.
CIl
~
CIl
0"
(CI
c:
(l)
-
on
on
on
on
on
on
on
on
R2
R2
R2
R2
-
R8
R8
R8
R8
R8
R8
R8
-+1
-+0
3(l)
3
o
-+1
-+0
-<
-+1
-+0
-+1
-+0
0
0
0
0
0
0
0
0
0
0
0
0
0
** Mask-programmed;
u: mute control
I
0
0
0
0
0
0
0
0
19/16, 31/64 or unchanged.
.4
MODEP = LOW.
X : change of station counter
(J)
»
OJ
w
o
I\)
I'\.)
U"I
1111111
l
SAB3022
Table 2. Allocation of local command codes for the standard version (SAB3022B).
6
IBUS
code
no.
LOCE
LOCO
LOCC
LOCB
LOCA
36
33
1
5
38
40
41
4
32
42
43
44
45
39
34
37
2
48
49
46
47
50
·56
0
6
7
57
58
17
35
59
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
·0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
local control inputs
February 1979
~(
command valid
for DICS system
1
0
0
1
1
1
0
0
0
1
0
no command
step station up
store
mute
search up/on
step channel up
volume up
volume down
display short
display on/off
ANAL 2 up
ANAL 2 down
ANAL3 up
ANAL 3 down
step channel down
channel mode
step station down
OFF
ANAL4 up
ANAL 4 down
reserved
basic set analogue
reserve B
reserve C
reserved
reserved
station 1
search down
reserved
l__
Receiver and analogue memory
S_A_83_0_2_2_ _
IBUS outputs
Outputs OATA and OLEN are inverted.
Correctly received commands are available for the duration of a key operation as a single command or
as repeated commands, in accordance with the sub-system requirements (see Table 1). The following
output modes are prov~ded:
• Single command; e.g. digits.
• Repetition rate: 2/second; e.g. step functions.
• Repetition rate: 8/second; e.g. analogue functions.
The IBUS command is available at output OAT A synchronous with the system clock; the word length
is 7 bits, one start bit and 6 data bits.
CLCK
H
L
H
DLEN~
I
I
I~I--------------------------~~
DATA L _ , start-bit
A_---I_ _B_....&..__C_---'_ _
5_....&..__E_---'_ _
F_-+'-'"'"""~
L.1_ _
I•
com'mand code bits
.. i1Z79348
Fig.4 Output waveforms of a command transmission.
Various word formats can be transmitted between the sub-systems, so it is necessary that each receiver
should carry out recognition of a word format. Word formats which do not correspond with the requirements have no effect on the system. It is also necessary that all sub-systems which receive or
supply information to the BUS-line should check whether or not the BUS is occupied, if yes, the output is delayed. Output OLEN acts as an input for this procedure. The output delay amounts to 32 x
tCLCK = 512 ps.
'I (
June 1979
7
~
·_jl___________________________~__
__S_A_B3_0_2_2__
Analogue memories
The SAB3022 contains four 64-step memories for analogue functions. The speed of stepping is
115 ms/step.
Stepping through the full range takes: 7,3 seconds.
When operating in the local mode, via inputs LOCA to LaCE, the stepping speed becomes 129 ms/step;
8,2 seconds for the full range.
The output waveform -of the analogue values is pulse-width modulated and has a repetition rate of
approximately 2 kHz; the duty factor determines the analogue values. The analogue voltage is available
at the output of an externally connected low-pass filter.
By the command (0) 'basic setting' and after switching-on the supply, the analogue memories (ANAL 2,
ANAL 3 and ANAL 4) are preset to a mid-position (31/64 in the standard version). Tre VOLU memory
is set to 30% in the standard version, after switching-on the supply (set to 50% and/orset.to normal by
command 0 can be obtained by mask-programming).
The volume control output (VOLU) is set LOW when, by a mute command (1), the flip-flop is set.
The volume output. will be set LOW for TS = 200 ms (see Fig. 5) when the station is changed by the
following commands (only if MODEP = HIGH):
16 to 31 (station 1 to 16).
36 and 37 (step station up/down).
The flip-flop will be reset by the following commands:
,
mute command (1).
volume up command (40); the volume output increases from LOW.
basic setting command (0); if chosen by mask-programming.
OFF command (2).
In the standby mode, output OFF = HIGH, the analogue memories cannot be changed. The output
VOLU = LOW, independent of memory values.
8
February 1979
(
l___
Receiver and analogue memory
SA_B_3_0_2_2_ _
I key operation; bouncing time finished (32 ms)
t
signal RSIGI valid
1 - - - - - - TS - - - T
-1-1
---"'!n
OPov (internal_'y_)_ _
n'""___---!
~
L...-_ _ _.....
I
VOLU
--1611S
OLEN
PRG
RSVO
7Z74963
Fig. 5 Timing diagram for muting at station and channel selection.
RSIGI mode
(from SAB3011)
TS
infrared transmission
local operation
200 ms
260 ms
Input/output OFF
OFF is the output of a flip-flop (ON/OFF-flag). If this output is LOW, the system is in the ON-mode,
if HIGH, the system is in the standby mode. The system is set to the standby mode by switching-on
the supply or using the command OF F. Terminal OF F operates as an input and allows setting of the
flip-flop to the on-state e.g. switching on via a wiping contact on the mains switch, while OFF 'is forced
to VSS for at least two clock cycles. The flip-flop can be set LOW = ON by a number of commands
(see Table 1).
Reserve outputs (RSVA, RSVB and RSVD)
RSVA is the output of a flip-flop which changes its state after each RESERVE A command (3).
RSVB provides a single positive pulse for 1 ms upon receipt of a RESERVE B command (6).
A RESERVE C command (7) generates a HIGH level on the RSVB outpur for as long as the command
is received, with a minimum of 100 ms (error-free reception assumed).
The function of the RSVD output depends upon the use of the MODEP output. If MODEP is LOW,
the RSVD output is LOW as long as the RESERVE D command (8) is received, with a minimum of
100 ms.
If MODEP = HIGH, a LOW pulse appears on the RSVD output during a change of the station
memory contents by the commands 16 to 31, 36 and 37 (see also Figs 5 and 6).
RSVD can also be used as an input: if it is connected to ground (VSS), the circuit will expect to receive
remote commands with a leading one in place of a leading zero.
.
I(
February 1979
9
S_A~B_30_2_2
____
jl______________________________
___
(1)
(2)
t
OPDV..Jl
(internally)
__ -
t
In'---------~-n1..----
_TS/2-
RSVA (3)
command 3
-
l-l,536ms
::x
MODEP, OFF
(H:~I
1 .......- - - - - - - - - - - - - - -
-~---!
(H--L)
RSVB
command 6
I-512J..LS
l-l,024ms
r---1
~
-I
RSVB (4)
command 7
I~----------------------------
l-l,024ms
L
I
--'I"
RSVD
--,
oommand8
>TSI2 .______________ 1_
only for -RSVB
LI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~~~.e,
change
I
7Z74962
(1) Key down; bouncing time finished; signal RSIGI: word comparison effective.
(2) Key up; bouncing time finished; signal RSIGI: word comparison uneffective, or. the time-window
has been exceeded.
(3) For SAB3032: RSVF, command 10.
--===
(4) For SAB3032: RSVE, command 9.
--
Fig. 6 Timing diagram for some outputs; fCLCK = 62,5 kHz.
10
. February 19791 (
r
~I
c
:>
~,
..I
:::
~
)
J
U
>
U
)
Receiver and analogue memory
l___
S_AB_3_0_2_2_ _
Station memory outputs (PRGA, PRGB, PRGC, PRGD and MODEP)
The station memory outputs are coded as shown in Table 1.
These are the outputs of a 4-bit station memory, the content of which is changed by commands
16 to 31 (station 1 to 16) or commands 36 and 37 (step station up/down). A step station command
(36 and 37) in the standby mode switches the system into the ON-mode without station alteration.
The MODEP terminal indicates whether a sub-system is selected (MODEP:::: LOW) or not (MODEP ::::
HIGH). A sub-system is selected by the commands 56 to 63. When a sub-system is selected, or when
MODEP is switched LOW externally, the commands 16 to 31,36 and 37 do not influence the station
memory contents. Output VO LU is not mute controlled and RSVD delivers no station change signal,
and can only be influenced by command 8 (reserve D).
At commands 2 (OFF), 4 (on) and after switching on the supply voltage, the.circuit is in the MODEp::::
HIGH state, meaning the station memory can be addressed.
When the SAB3022 is used in the DICS (Digital Channel Selection) system, MODEP should be switched
LOW externally, to avoid unwanted muting during input of digits.
The step station cycle is reduced from 16 to 12 stations, if PRGD is connected to ground (VSS)'
Standby state
The SAB3022 has a built-in reset circuit. After switching on the supply voltage, the next two clock
cycles will reset the circuit into the standby mode.
The circuit will be in the following operating states:
1.
2.
3.
4.
5.
6.
7.
VOLU:::: LOW.
Analogue memories are set to 50%; VOLU is set to 30% (for the standard version).
Station memory is at station 1.
OFF:::: HIGH.
Mute-flag is not set.
All reserve outputs (except RSVD) are LOW.
MODEp:::: HIGH.
Programming of modes using outputs as inputs
Several outputs can be used as inputs (MODEP, RSVD, PRGD), for programming other operating
modes. This can be obtained in 2 ways:
1. By means of a connection to ground (VSS). In this case the output signal is not available.
2. By means of a bipolar transistor in a common emitter circuit which clamps the output level at
VBE (see Fig. 6). The output signal is available with reversed polarity at the collector of the transistor.
June 1979
11
~__S_A_B_3_0_22____jl_________________________________
Q
Q
input
stage
output
stage - - - - - - '
7Z74913
Fig. 6 Clamping the output voltage to VBE.
/'
12
February 1979
(
L___
Receiver and analogue memory
S_A_B3_0_2_2_ _
data in
RSIGI
VSS
clock
CLCK
LOCA
reserve D
RSVD
LOCB
sub-system
display
MODEP
LOCC
ANAL4
LOCD
ANAL3
LOCE
ANAL2
PRGB
VOLU
PRGA
OFF
PRGC
reserve A
RVSA
PRGD
reserve BIC
RVSB
analogue
outputs
14
DATA
13
DLEN
local
keyboard
station
memory
outputs
}
VDD
12
I BUS information
7Z82021
Fig_ 7 Pinning diagram.
RATINGS (VSS = 0)
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage
VDD
max.
Input voltage
-VI
max.
15 V
Input current
II
max.
10 rnA
Negative input current
-II
max.
10 mA
Output current
IQ
max.
10 mA
Negative output current
-IQ
max.
10 mA
Power dissipation per output
PQ
max.
50 mW
Total power dissipation per package
Ptot
max.
500 mW
Operating ambient temperature range
Tamb
T stg
Storage temperature range
7,5 V
-20 to + 70 °C
-55 to + 150°C
February 1979
13
~__S_A_B_3_0_22____~~_~______________________________
CHARACTERISTICS
VSS = 0; T amb
= 25 oC; unless otherwise specified
VDD
V
symbol
min.
,typo
SlIPply voltage
-
VDD
4,5
5,0
Supply current
5
IDD
-
-
Input voltage
lO~
conditions
m~x.
5,5
25
V
rnA
5
Vil
-0,3
-
Input voltage HIGH
5
VIH
3,5
-
15
Input leakage current
RSIGI, ClCK
5
IIR
-
-
1
IlA
VI=-O,3to+10V
Input current lOW
lOCA to lOCE,
OFF, DlEN
5
-IlL
-
-
100
IlA
VI =0
Output voltage lOW
5
VOL
-
-
Output current HIGH
5
IOH
-
-
Output voltage lOW
5
Val
5
IQH
-
-
Output cu rrent HI GH '
Output voltage lOW
5
Val
-
-
1
V
IOl=4 mA
Output current HIGH
5
IOH
-
-
20
Il A
VOH = 15 V
Output voltage HIGH
5
VOH
3,5
-
15
V
10>0
Input OFF current
during standby setting
5
IOFF
15
-
-
rnA
Val ~VOH
Clock frequency
5
fClCK
56,25 62,5
Duty factor
5
8
0,4
0,5
0,6
Input rise/fall time
5
tr: tf
-
-
1
1,2
V
V
Outputs OF=F; RSVA, RSVB,
RSVD, MODEP, PRGA to
PRGD
0,8
20
V
IQl = 1 rnA
IlA
VOH = 1? V
OutP!Jts DATA, OLEN
-I
0,8
20
V
IOl =2 mA
IlA
VOH =15 V
Outputs VOlU, ANAl2
ANAl3, ANAl4
Outputs RSVA, RSVD,
MODEP, OFF, PRGD
--
==
-==
14
February 1-979
(
68,75 kHz
/lS
OV
APPLICATION INFORMATION
+5V
:xl
CD
n
Il-
fD
+12V
I
~c€
I
_--J._ _
1---.,..,~1RSIG I
TDB1033
J2
VDD
PRCA 17
PRCB 18
16
PRCC 15
PRCD
~
I
~
0"
c:
CD
3
CD
3
o
SAB2064
-<
[
SAB3022
CD
CLCK
I-BUS
~
~ILO.CA
~ LOCB
n..
LOCC
~, LOCD
')n.
"'v
~
},~~
MODEP
3 ~ RSVD
2
"Sf
~}
13
DATAI
DLEN 14
l I
reserve
ICLCK
c:
II>
cc
I
4
~
II>
DIGITAL
CHANNEL. DISPLAY
19.1 LOCE
-<
::::J
c..
I
In
BINARY
ENCODER
LOCAL KEYBOARD
~
II>
'---.---..J
r
24
VSS
AMPLIFIER
r---------..
CD
:C.
CLOCK
62,5 kHz
-....J
L-_ _ _ _ _ _>---.~
volume
l-----..--t--.~
brightness
II :
~ II
:~:~:"
IIll
U
)
June.1979
3
I'
l
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
SAB3032
.'-----
RECEIVER AND ANALOGUE MEMORY
The SAB3032 is identical to the SAB3022 except for extra output functions; ANDA, ANDB, RSVE,
RSVF.
Additional features
• Output of a binary-coded display command to realize on-screen bar display or digit display of the
stored analogue values.
• Output of a control command for the display of analogue values.
• Two extra reserve functions.
GENERAL DESCRIPTION
With the SAB3032 the following display possibilities can be obtained in addition to the SAB3022.
•
•
•
•
On-screen bar display with different colours for each analogue function.
Multiple on-screen bar display of all analogue functions.
Numerical display of the altered analogue functions.
Multiple numerical display of the analogue values.
QUICK REFERENCE DATA
VDD
typo
Operating ambient temperature range
Tamb
o to
Clock frequency
fCLCK
Supply voltage range
Supply current at VDD =
5 V; Tamb = 25 °C
'DD
5 V
+70 0C
62,5 kHz
typo
20 mA
PACKAGE OUTLINE
28-lead DIL; plastic (SOT-117l.
I
February 1979
Jl________________________________
_____
SA_B_3_0_3_2_,__
OPERATION DESCRIPTION
Reserve outputs (RSVE, RSVF)
A reserve E (9) command generates a HIGH level on the RSVE output for as long as the command is
received at the remote control or at the receiver;
RSVF is the output of a flip-flop which changes its state after each reserve F (10) command. After
switching on the supply voltage output RSVF = LOW.
Fig. 6 of .the SAB3022 shows the timing of these outputs (see data sheet SAB3022).
Display of analogue values outputs (ANDA, ANDB)
Output AN DA generates a clock and a gating signal synchronized with the I BUS output (see I=ig. 1).
The addressed analogue values (VOLU, ANAL2, ANAL3, ANAL4) are generated by the clock signal
together with the DATA signal, which are available at output ANDB in binary code ..
When the analogue value is changed by a command, the spedfic binary-coded analogue value will be
generated serially (simultaneously with the gating signal at ANDA). The signal of the addressed
- analogue value is generated at ANDB simultaneously. This output is obtained at every analogue value
change, thus also at the- commands basic set analogue mute/on and OFF, and after switching on the
supply voltage.
When no special analogue function is selected the output VOLU is switched to ANDB.
When ANDB is connected to VSS, analogue memory output VOLU will be affected by the command
basic set analogue (0).
----\
2
February 1979
f
Receiver and analogue memory
l",-__S_A_B_3_03_2_ _
CLCK
DLEN
~~______________________~
DATA
~
I
A"
EIF_
BCD
start- bit
ANDA
VOLU
ANAL2
ANAL3
ANAL4
--
nJ1...f1J
--
~
~
~
LSB
ANDB
MSB
_""'~
~
7Z74964
binary coded
analogue value
Fig. 1 Timing diagram for signals ANDA and ANDB; display of analogue value.
I
February 1979
3
SAB3032
)l
RSVE
VSS
RSIGI
RSVF
CLCK
LOCA
RSVD
LOCB
MODEP
LOCC
ANAL4
LOCO
ANAL3
LOCE
ANAL2
PRGB
VOLU
PRGA
OFF
PRGC
RSVA
11
PRGD
RSVB
12
DATA
VDD 13
DLEN
ANDB
15 ANDA
14
7Z82070
Fig. 2 Pinning diagram; based on development samples,
.may be changed in future designs.
RATI NGS see SAB3022
=
CHARACTERISTICS see SAB3022 except for:
:::::
VSS
=
0; T amb = 25 DC; unless otherwise' specified
VDD
V
symbol
min.
typo
-
-
conditions
max.
Outputs RSVE" RSVF,
ANDA, ANDB
4
Output voltage LOW
5
VOL
Output current HI G H
5
IOH
February 1979
(
0,8
V
IOL = 1 mA
20
IlA
VOH = 15 V
l___
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
S_A_B_30_3_4_ _
ANALOGUE AND TUNING CIRCUIT (A & T)
400kHz from
microcomputer
a.f.c.
r-=.C=.;Li-+--t-+-l
PRECOUNTER
c=J 4MHz
L
TUNING
CONTROL
ANO
CLO
(4MHz)
AN1
AN2
AN3
AN4
AN5
FIN
BUS RECEIVER
CBUS
DATA (13)
OCL(l1)
OLEN (12)
&
CONTROL
17 TEST
~--~. .--~
SAB3034
10
Fig. 1 Block diagram.
VOO
vSS
7Z79624
The SAB3034 analogue and tuning circuit (A & T) provides closed loop digital tuning and control
of up to six analogue functions. The Ie is used in combination with a microcomputer and comprises
the following:
•
•
•
•
•
Frequency measurement.
Digital to analogue conversion of 6 analogue functions.
Command data handling.
Tuning control.
Although an on-chip 4 MHz crystal oscillator is provided, the 400 kHz clock output of the microcomputer can directly be used (see Fig. 1 pins 2 and 3).
PACKAGE OUTLINE
18-lead OIL; plastic (SOT-102A).
June 1979
jl~____________________~------~
_____
S_AB_3_0_,3_4___
GENERAL DESCRIPTION
The SAB3034 performs frequency-locked loop digital tuning and also provides digital control of up
to six analogue functions. Control data is transmitted from a microcomputer, vi!,! the CBUS (inputs
DATA, DlEN and Del) as sixteen 12-bit words.
Serial 'data on input DATA is shifted into the data receiver with the data clock DCl, when the data line
enable signal DLEN is HIGH. Valid received data is loaded into the data buffer.
Six words define the tuning window, the holding range, the tuning speed and the clock oscillator
frequency.
The clock frequency of 400 kHz may be derived directly from a microcomputer or may be generated
with a 4 MHz crystal-contro.lled oscillator. Eight data words control the analogue part. Two data words
provide 12 bits of frequency data.
The 12-bit frequency counter has an accuracy of 1024 MHz/212 = 250 kHz which iswithin the catching
range of a.tc. circuits. With one frequency defining word, frequencies up to 2 10 MHz = 1024 MHz can
be specified in increments of 1 MHIl.
While with a second data word increments of 250 kHz in frequency can be specified.
Six data words set the required values (0 to 63) into the six 6-bit analogue registers. The contents of
the registers are converted into pUlse-width modulated outputs with a frequency of 6,25 kHz and a
duty factor proportional to the analogue value (see Fig. 2).
External BC filters smooth the analogue outputs to obtain d.c. control voltages for the ICs in the
television receiver. Two data words simultaneously enable or disable all of the analog~e outputs.
, - 64 clock periods
.. ,
-.f1
increment 0
fl
...,11-
1 clpck period
increment 31 .
r
J
,I
..
.. ..
32 c!ockperiods 1 32 clock periods .1
..
increment 63
7Z79623
Fig. 2 Pulse-width modulated analogue outputs from the SAB3034.
2
June 1979
1(
l._SAB3034
Analogue and tuning circuit (A & T)
VSS
FIN
ClO
TEST
CLI
FUP
ANO
FDN
AN1
SAB3034
14 AFC
AN2
13 DAT.A
AN3
12 Di-EN
AN4
11
DCl
10
VDD
AN5
9
7Z84094
Fig. 3 Pinning diagram.
June 1979
3
l___
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
S_A_B_30_4_2_ _
INFRARED DECODER; MICROCOMPUTER COMPATIBLE
RSIGI ~ 4-
INFRARED
DECODER
f-+-
OSC
ORZ
12
13
16
OSCI LLATOR/
DIVIDER
CLCK
( 62,5 kHz)
12
LOCA - ~
LOCB
LOCC
11 f+-
.!Q. 4-
LOCD ~ f-+LOCE
OUTPUT
CONTROLI
REGISTER
LOCAL
CONTROL
DECODER
5
DATA
6
.....
...!... f-+SAB3042
AUTOMATIC
RESET
19
r-+
13
11
15
LlNH DAV
14
7Z82235
SHCL
Fig. 1 Block diagram.
Features
• Remote control receiver for 128 commands to be used in combination with the remote transmitter
SAB3011 in microcomputer controlled tuning concepts.
• High security against interferences by word format checking and double word testing, also in case of
a simultaneous infrared sound transmission.
• Asynchronous serial command output to the microcomputer with processing of acknowledgement
signals produced by the microcomputer.
.
• Relieving the microcomputer of real time processing, e.g. incoming signals are permanently checked
with the command format validity and freedom from interferences.
• Separate inputs for local operation (up to 31 commands); mask-programmable.
• Only three terminals of the microcomputer are necessary for the control part ofthe television receiver.
• Internal clock oscillator.
QUICK REFERENCE DATA
Supply voltage
VDD
Operating ambient temperature range
Tamb
Oscillator frequency
Supply current; VDD = 5 V; Tamb = 25
5 V
typo
o to + 70
4 MHz
fORZ typo
°c
100
typo
20 mA
PACKAGE OUTLINE
16-lead 01 L; plastic (SOT-38ZI.
.
~
0C
June 1979
-
I
-_.~_A~B3--0-4-·~---Jl~-----------------------------
____
GENERAL DESCRIPTION
The SAB3042 decodes the pulse code modulated signals from the remote transmitter SAB3011.
Correct reception of two command words activates the IBUS outputs D LEN' and DATA, as well as the
CBUS signals DAV, LlNH and SHCL. The IBUS outputs can be used for driving systems which are
accessible via this type of interface, e.g. Teletext and Viewdata. The CBUS output data can be used for
control of a microcomputer. For local operation, 5 inputs are available (LOCA to LOCE), via which up
to 31 commands can be loaded into the command register.
OPERATION DESCRIPTION
Remote control signal input (RS I G I)
The signals from the remote control'transmitter are applied to the RSIGI input, where they are
checked and decoded. The instruction bus (JBUS) is then enabled and an output operation takes place.
The microcomputer is also warned via DAV, that a message is waiting. The response time is about 110 ms.
The following tests are carried out for each signal:
• Control of pulse distance for logic 0 or 1 'and word separation.
• Comparison of two successive transmitted words.
• Detection of noise between the signals.
Signals which do not come within the zero or one 'window', restart the timing procedure. The commands are transmitted as 7-bit words (1 start bit, 6 data bits).
Local keyboard inputs (LOCA, LOCB, LOCC, LOCD and LOCE)
The SAB3042 has 5 keyboard inputs for local control. The coding of the commands is initiated via an
external diode matrix; up to 31 commands (see Table 1) for local control are possible. The selection of
these commands (31 out of, 64 available) are stored in a mask-programmable ROM (according to the
wishes of the customer).
'
The inputs are drawn internally to VDD, if the keys are not used.
The response time is 32 ms for local commands.
A local ~ommand overrides a remote control command at input RSIGI. The current output data at the
I BUS or the CBUS will, however, be completed. For waveforms see Fig. 2.
IBUS outputs (DATA, DLEN)
Correctly received commands are available for the duration of a key operation as a single command or
as repeated commands, in accordance with the sub-system requirements (see Table 1). The following,
output modes are provided:
.
• Single command; e.g. digits; instruction class'S'.
• Repetition rate: 2/second; e.g. step function; instruction class 'R2'.
.• Repetition rate: 8/second; e.g. analogue functions; instruction class 'R8'.
I
~
The IBUS command is available at output DATA synchronous with the system clock; the word length
is 7 bits, one start bit and 6 data bits (see Fig. 3).
2
l___
Infrared decoder; microcomputer compatible
S_AB_3_0_4_2_ _
r---
LOCA to
LOCE
r
key down
11111
---
I
16 ms
key
up
__________--&..111.....1.. . ,11
down
11111
debounce
.
--- 16 1--time
ms
bouncing time
r
~ key
I.
single command
--+----..
- - >32ms 1-
, - - >32ms - repetitio~
rate' RB'
OLEN
u
OLEN
repetition rate 'R2'
u
CBUS
7Z82237
Fig. 2 Relationship between key operation and command output.
H
CLCK
L
H
OLEN:
DATA L
------------'r_I
I
I
li--
start-bit 1
...__A_---''--_B_---'''__
C_--'-__5__
I•
&....-_E_---''--_F_~-;..{..{."j~"'"''
command code bits'
•
I
1279348
---
Fig.3 Output waveforms of a command transmission.
"I (June
1979
3
S_A_B_30_4_~_-
____
Jl_________~~-----------------"1
__
Data output; e.g. request at the CBUS interface
Inputs/outputs (DAV, LlNH, SHCLl
The CBUS inputs/outputs are assigned for the asynchronous request of a command by external units.
The commands activate the CBUS with a repetition rate of a/second during a key operation. The
receiving of a command will be indicated by setting the DAV signal to LOW (see Fig. 5). The output
will be delayed in case of an occupied BUS (DAV = LOW or l.:TNH = LOW). Input DAV is an input for
this control. If the external unit recognizes DAV = LOW the request for information is started by setting
LlNH to LOW. TheSAB3042 indicates the reception LlNH = LOW by setting DAV to HIGH. The data
- word can be shifted out after a certain hold time by a series of clock pulses, the frequency of which
can be chosen in a wide range. The SAB3042 generates DAV = HIGH by applying further clock pulses,
after the data word is shifted out.
The request will be terminated by setting UNH = HIGH, also in case the data word is not completely
shifted out.
A new incoming command can overrule an enclosed command for as long as the request is not yet
started (LiNH = HIGH). A command, which is overruled, is lost. A stored command cannot be
overruled when LlNH is set LOW.
The following information is shifted out at the CBUS in addition to the 7-bit information of the
remote transmitter (start bit S and data bits A to F).
L-bit: this bit indicates, whether the command has been initiated by the local control inputs LOCA to
LOCE (L = HIGH), or by the remote control (L = LOW).
R-bit: this bit indicates, whether the previous command is still applied without interruption of the
key operation. R is LOW in case the command is on the CBUS output for the first time; R is
HIGH for all following commands. The R-bit enables the external system to execute commands
as single commands or repeated commands.
Oscillator inputs (OSC, ORZ)
SAB3042
OSC
2
ORZ
1 MU
3
The system clock frequency of 62,5 kHz is generated
internally from a 4 MHz quartz crystal oscillator. The
terminals ORZ and OSC are the input/output of the
4 MHz oscillator. An external oscillator signal of 4 MHz
can be applied to terminal ORZ.
22
J;PF
--
Fig. 4 Application advice for the oscillator.
Reset
The circuit generates a reset signal internally. A reset-cycle with a duration of two clock cycles is
automatically initiated after switching on the supply. The IBUS outputs DATA, DLEN and the CBUS
output DAV are then HIGH.
.
4
June
19791 (
LJL. V L . L . v r IVIL.r'l .---oI"'\IVIl
L.L-.
LJr\
I
r\
~
I»
(1)"
__
H
DAV
L
CiJ
(2h,
Q.
Q.
CD
F
8Q.
-_ H
LlNH L
____ I________
r-1
,~
3
c:;-
a
td2 I
SHCL H
L
JI
8
r-1
r-,
I
I
7Z82238
3
"t:I
C
~
n
o
3
(1) CBUS is occupied by previous transmission.
ac:
(jj'
(2) Start of a new CBUS transmission by a HIGH-to-LOW transition at output DAV.
Fig. 5 Waveforms showing CBUS output signals.
c...
C
:::J
CD
co
(J)
»
OJ
......
to
c.v
0
~
I\)
m
I
1111111
$_A_J3_39_~.~_2_.
___
_)
l. ._________-----------
Table 1. Specifications of the IBUS/CBUS-code (continued on next page)
RSIGI/
IBUS
code
no.
0
1
2
3
4
5
6
7
*
6
LaCE
LOCD
LOCC
LOCB
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
8
9
10
11
12
13
14
15
---
local control inputs *
1
1
1
DATA/DAV
output code
LOCA
S
F
E
D
C
B
·A
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O.
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
S
S
S
S
R8
S
S
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1. 1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
R8
R8
R8
R8
R8
R8
R8
R8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
S
S
S
S
S
S
S
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1.
1
1
1
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
S
S
S
S
S
S
S
S
0
0
1
0
0
0
1
0
0
0
16
17
18
19
20
21
22
23
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
0
24
25
26
27
28
.29
30
31
1
1
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
1
1
0
1
} See next page.
•
Jun~1979
It
0
1
IBUS
instr.
class
1
1
b
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
**
l___
Infrared decoder; microcomputer compatible
S_AB_3_0_4_2_ _
RSIGI/
IBUS
code
no.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64-127
*
local control inputs *
OATA/OAV
output code
LOCE
LOCO
LOCC
LbcB
0
1
0
0
1
0
1
1
1
1
1
1
0
0
1
1
0
1
1
0
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
0
1
0
0
LOCA
1
0
0
IBUS
instr.
class
S
F
E
0
IC
B
A
**
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
S
S
1
0
1
0
1
0
1
0
1
0
0
'0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
. 1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
0
1
0
1
0
1
1
1
0
0
1
0
O·
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
-
-
-
-
1
1
1
1
1
1
1
1
1
S
S
R2
R2
R2
R2
R8
R8
R8
R8
R8
R8
R8
R8
S
S
S
S
R8
R8
R8
R8
1
0
1
R8
R8
R8
R8
R8
R8
R8
R8
-
-
S
1
0
1
l'
0
0
1
0
1
--
The selection of local commands is mask-programmable. The table gives local commands for the
standard version SAB3042B.
Instruction class: S = single
R2 = repeat ~ 2/second
R8 = repeat ~ 8/second.
i(JUne1979
7
SAB3042
Jl
vss
CLCK
OSC
OAV
QRZ
SHCL
RSIGI
LlNH
DATA
LOCA
OLEN
LOCB
LOCE
LOCC
LOCO
VOO
7Z82233
Fig. 6 Pinning diagram.
PINNING
1
9
4
VSS
VOO
RSIGI
12
local keyboard inputs (5-bits)
7
LOCA
LOCB
LOCC
LOCO
LOCE
6
5
16
OLEN
DATA
CLCK
data line enable input/output
data output
clock output (62,5 kHz)
14
15
13
SHCL
OAV
LlNH
asynchronous clock-burst
data output
control signal
3
2
QRZ
OSC
oscillator input
oscillator output
11
10
8
--------
8
June
negative supply (0 V)
positive supply
data input; remote control
19791 (
}
IBUS
} CBUS
l___
Infrared decoder; microcomputer compatible
S_A_B3_0_4_2_ _
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage range
-0,3 to + 7,5 V
VOD
Input voltage range
-0,3 to
Input current
+ 15 V
max.
10 mA
Output current
± II
,± 10
max.
10 mA
Power dissipation per output
Po
max.
50 mW
Total power dissipation per package
Ptot
max.
800 mW
Operating ambient temperature range
Tamb
Storage temperature range
T stg
o to + 70
0C
-55 to + 150 °C
CHARACTERISTICS
VSS
= 0; Tamb = 0 to + 70 oC; unless otherwise specified
VDD
V
symbol
min.
typo
max.
conditions
Supply voltage
-
VDD
4,5
5,0
5,5
V
Supply current
5
IDD
-
-
25
mA
VIL
-0,3
-
1,2
V
-
15
V
Inputs RSIGI, LlNH,
ORZ, LOCA to LOCE
I nput voltage LOW
5
I"nput voltage HI GH
5
VIH
2,0
Input leakage current
5
IIR
-
-
1
IlA
VI
= -0,3 to + 15 V
Input current LOW
LOC~ to LOCE
5
-IlL
10
-
100
IlA
VI
=
Output leakage current
5
lOR
-
-
20
IlA
Va = 15 V
Output voltage LOW
DATA
OAV,OSC
5
5
VOL
VOL
-
-
1
0,4
V
V
-10 = 1 mA
-10 = 1,6 mA
0
Outputs DATA, DAV,
OSC (open drain)
---
! internal high-ohmic
l pu II-up transistor
Input/output OLEN
(open drain)
Input values
-
-
see RSIGI
Output values
Input current LOW
5
-IlL
10
Input values
-
-
see RSIGI
Input current LOW
5
-IlL
10
Output voltage LOW
5
VOL
-
Output leakage current
5
lOR
-
see DATA
-
100
IlA
100
IlA
VI =0
1
V
-10 = 5mA
20
IlA
Va
VI = 0
Input/output CLCK
-
= 15 V
I (June
1979
9
CHARACTERISTICS (continued)
\
VOO
V
symbol
min.
typo
max.
conditions
OsciUator frequency
ORZ,OSC
5
f
3
4
4,1
Duty factor
5
5
0,4
0,5
0,6
Switching times
see Fig. 5
5
tR
1
-
4
ms
fORZ = 4 MI-!z
5
td1; td2
-
-
20
JIS
fORZ = 4 MHz
5
td3
-
-
5
JIS
5
tA
0
-
-
JIS
5
tSL; tw;
tH; tL
5
-
-
JIS
I nput rise/fall times
I
I
MHz
Input ORZ
5
tr; tf
-
-
50
ns
All other inputs
5
t6 tf
-
-
1
JIS
OV
+12 V
+5V
........... . - - - - - -
..------
}
CBUS to
microcomputer
..........
'--......-.....-- VOO
22
J;PF
Fig. 7 Typical receiver circuit uSingSAB3042.
10
JU,ne1979
(
_ _ _J
SAF1032P
SAF1039P
REMOTE CONTROL SYSTEM FOR INFRARED OPERATION
The SAF1032P (receiver/decoder) and the SAF1039P (transmitter) form the basic parts of a sophisticated remote control system (pcm: pulse code modulation) for infrared operation. The ICs can be
used, for example, in TV, audio, industrial equipment, etc.
Features:
SAF1032P receiver/decoder:
• 16 programme selection codes
• automatic preset to stand-by at power 'ON', including automatic analogue base settings to 50% and
automatic preset of programme selection '1' code
• 3 analogue function controls, each with 63 steps
• single supply voltage
• protection against corrupt codes.
SAF1039P transmitter:
• 32 different control commands
• static keyboard matrix
• current drains from battery only during key closure time
,. two transm ission modes selectable.
The devices are implemented in LOCMOS (Local Oxidation Complementary MOS) technology to
achieve an extremely low power consumption.
Inputs and outputs are protected against electrostatic effects in a wide variety of device-handling
situations. However, to be totally safe, it is desirable to take handling precautions into account.
VDD
SElA
SElC
f/lSCI
SELB
SELD
I
TRY2
DATA
H¢LD
I
I
TRSL
I
TRf/l1
TRf/l2 I
14
SAF1032P
4
2
L30T
I
L2f1lT
L1f/lT
2
6
I SINC I
BIND
SINA
TRXO
I
TRX1
BINS
4
TRX2
I
TRX3
7Z74348
6
TRDT
I
TRf/lS
TINH
7Z74349.1
Fig. 1 Pin designations.
PACKAGE OUTLINES
SAF1032P: 18-lead DI L; plastic (SOT-102A).
SAF 1039P: 16-lead D I L; plastic {SOT-38Zl.
'I
January 1979
SAF1032P
SAF1039P
PINNING
To facilitate easy function recognition, each integrated circuit pin has been allocated a code as shown
below.
SAF1032P
1
2
3
4
5
6
7
8
9
L3cz)T
L2(l)T
L1(l)T
BIND
BINC
BINB
BINA
TV(l)T
VSS
linear output
linear output
linear output
binary 8 output
binary 4 output,
binary 2 output
binary 1 output
on/off input/output
10
11
12
13
14
15
16
17
18
H(l)LO
DATA
MAIN
(l)SCI
SELD
SELC
SELB
SELA
VOO
control input
data input
reset input
clock input
binary 8 output
binary 4 output
bjnary 2 output
binary 1 output
9
TR(l)1
TR(l)2
TRSL
TRY3
TRY2
TRY1
TRYO
VOO
oscillator control input
oscillator control input
keyboard select line
keybo~rd input
keyboard input
keyboard input
keyboard input
SAF1039P
1
2
3
4
5
6
7
8
TRXO
TRX1
TRX2
TRX3
TROT
TINH
TR(l)S
VSS
keyboard input
keyboard input
keyboard inp~t
keyboard input
data output
inhibit output/mode select input
oscillator output
-=......
=
~
2
January 1979
~(
10
11
12
13
14
15
16
SAF1032P
SAF1039P
Remote control system for infrared operation
BASIC OPERATING PRINCIPLES
The data to be transmitted are arranged as serial information with a fixed pattern (see Fig. 2), in
which the data bit-locations BO to B4 represent the generated key-command code. To cope with I R
(infrared) interferences of other sources a selective data transmission is present. Each transmitted bit
has a burst of 26 oscillator periods.
Before any operation will be executed in the receiver/decoder chip, the transmitted data must be
accepted twice in sequence. This means the start code must be recognized each time a data word is
applied and comparison must be true between the data bits of two successively received data words. If
both requirements are met, one group of binary output buffers will be loaded with a code defined by
the stored data bits, and an internal operation can also take place. See operati ng code table on page 7.
The contents of the 3 analogue function registers are available on the three outputs in a pulse code
versus time modulation format after D(digital) to A (analogue) conversion. The proper analogue levels
can be obtained by using simple integrated networks. For local control a second transmitter chip
(SAF1039P) is used (see Fig. 7).
DATA
MODE1
DATA
MODE2
~_~~L-
_ _ _ _~_~~_ _ _ _~~~~__j _ _ _ _~~~~_ _ _ _ _~_ _ _ _ _~
rkey down
TINH
...- - - - - - start code
-------I~~I......I _ _ - - - - -
I~..~---------------------
one data word
data bits
- - - - - - - - 1....1
--------------------~
7Z74351.2
32xTo =32x 27 ms(21
ft
(1) TO = 1 clock period
= 128 oscillator periods.
(2) f t in kHz.
Fig. 2 Pattern for data to be transmitted.
TIMING CONSIDERATIONS
The transmitter and receiver operate at different oscillator frequencies. Due to the design neither
frequency is very critical, but correlation between them must exist. Calculation of these timing
requirements shows the following.
With a tolerance of ±10% on the oscillator frequency (f t ) of the transmitter, the receiver oscillator
frequency (f r = 3 x f t ) must be kept constant with a tolerance of ±20%.
On the other hand, the data pulse generated by the pulse stretcher circuit (at the receiver side) may
vary ±25% in duration.
January 1979
3
l_ __
SAF1032P
SAF1039P
GENERAL DESCRIPTION OF THE SAF1039P TRANSMITTER
SAF1039P
ENCODING
OUTPUT
GATING
INPUT
CONTROL
SCALER
27
OSCILLATOR
vss
16
Fig. 3 Block diagram of SAF1039P transmitter.
Any keyboard activity on the inputs TRXO to TRX3, TRYO to TRY3 and TRSL will be detected. For
a legal key depression, one key down at a time (one TRX and TRY input activated), the osCillator
starts running and a data word, as shown on page 3, is genetated and supplied to the output TRDT. If
none, or more than 2 inputs are activated at the same time, the input detection logic of the chip will
generate an overall reset and the oscillator stopsrunning (no legal key operation).
-
This means that for each key-bounce the logic will be reset, and by releasing a key the transmitted data
are stopped at once.
.
The minimum key contact time required is the duration of two data words. The on-chip oscillator is
frequency controlled with the external components R1 and C1 (see circuit Fig. 6); the addition of
resistor R2 means that the oscillator frequency is practically independent of supply voltage variations.
A complete data word is arranged as shown in Fig. 2, and has a length of 32 x TO ms, where TO = 271ft .
Operation mode
--
4
DATA
FUNCTION OF TINH
1
unmodulated: LOCAL operation
output, external pull-up resistor to VDD
2
modulated: REMOTE control
input, connected to VSS
January
1979~
(
SAF1032P
SAF1039P
Remote control system for infrared operation
GENERAL DESCRIPTION OF THE SAF1032P RECEIVER/DECODER
7
«z
II
5
17
4
u
0
~
iii
iii
iii
Ul
z
iii
10 H!1lLD
6
m
z
Z
BINARY OUTPUT
FLAGS (BINF)
UJ
~
UJ
Ul
16
:l
UJ
Ul
15
14
0
....J
UJ
Ul
II
BINARY SELECT
FLAGS (SELF)
I
II
BUFFER
REGISTER
(BFR)
I
I
I
,
START CODE
DETECTION
(CST0)
Voo
LINEAR 2
REGISTER
(LlN2)
r+-
DIGITAL TO
ANALOGUE
CONVERSION
(D/A)
r+-
DIGITAL TO
ANALOGUE
CONVERSION
(D/A)
I
REGISTER
(LlN3)
1
~
{
COMPARATOR
(K!1lM)
"0 / '1' DETECTOR
j
I
DIGITAL TO
ANALOGUE
CONVERSION
(D/A)
LINEAR 3
ANALOGUE
DECODER
(ANDEC)
+
I
r+-
It
DATA SHIFT
REGISTER
(SRDT)
I
11 DATA
II
LINEAR 1
REGISTER
(LlN1)
1
I
J
I
I
COMPARATOR
COUNTER
(C(/}MP)
BIT COUNTER
(BITC)
TIMER COUNTER
(CTlM)
I'
J
I
TIL
SAF1032P
/18
L1!1lT 3
L20T 2
L3!1lT 1
ill
Ii
MAIN
FLAG
(MAINF)
MAIN 12
rV ON/OFF
FLAG
(TV0NF)
TV0T 8
I
t
PRESET
FLAG
(PREST)
~~
Vss
9
7Z743S2
1
Fig. 4 Block diagram of SAF 1032P receiver/decoder.
The logic circuitry of the receiver/decoder chip is divided into four main parts as shown in the block
diagram above.
Part I
This part decodes the applied DATA information into logic '1' and '0'.
It also recognizes the start code and compares the stored data-bits with the new data-bits accepted.
January 1979
5
L
SAF1032P
SAFi)39P
'---------------~--------------------------------------
Part
n
This part stores the programme selection code in the output group (BINF) and memorizes it for
condition H({)LD = LOW.
It puts the functional code to output gro\Jp (SE LF) during data accept time, and decodes the internally
used analogue commands (AN DEC).
.
.
Part.111
This part controls the analogue function registers (each 6-bits long), and connects the contents of the
three registers to the analogue outputs by means of D/A conversion. During sound mute, output L 10T
will be forced to HIGH level.
Part IV
This part keeps track for correct power 'ON' operation, and puts chip in 'stand-by' condition at supply
voltage interruptions.
The logic design is dynamic and synchronous with the clock frequency ({)SCI), while the required
control timing signals are derived from the bit counter (BITC).
Operation
Serial information applied to the DATA input will be translated into logic '1' and '0' by means of a
time ratio detector.
After recognizing the start code (CST({») of the data word, the data bits will be loaded into the data
shift register (SRDT). At the first trailing edge of the following data word a comparison (K0M) takes
place between the contents of SRDT and the buffer register (BFR). If SRDT equals BFR, the required
operation will be executed under control of the comparator counter (C({)MP).
As shown in the operating code table on page 7, the 4-bit wide binary output buffer (BINF) will be
loaded for BFRO = '0', while for BFRO = '1' the binary output buffer (SE LF), also 4-bitwide will be
activated during the data accept time.
At the same time operations involving the internal commands are executed. The contents of the
analogue function registers (each 6-bits long) are controlled over 63 steps, with minimum and maximum
detection, while the D/A conversion results in a pulsed output signal with a conversion period of
384 clock periods (see Fig. 5).
'
First power 'ON' will always put the chip in the 'stand-by' position. This results in an internal
clearing of all logic circuitry and a 50% presetting of the contents of the analogue registers (analogue
base value). The programme selection '1' code will also be prepared and all the outputs will be nonactive (see table on page 8).
From 'standcb/ the chip can be made operational via a programme selection command, generated
LOCAL or via REMOTE, or directly by forcing the TV ON/OFF output (TV({)T) to zero for at least
2 clock periods of the oscillator frequency.
For POWER ON RESET a negative-going pulse should be applied to input MAIN, when VDD is
st~bilized; pulse width LOW ~ 100 MS.
.
~I
ANALOGUE.
OUTPUT
(SO 0/0 contents)
1--6 clock periods
nnnnnnnn
.J U U U U U U U L
1-------..
384 clock periods
Fig. 5 Analogue output pulses.
6
I
January 1979
(
n-n n n
__ .J U U U L
.1
7Z76078
SAF1032P
SAF1039P
Remote control system for infrared operation
OPERATING CODE TABLE
key-matrix
position
TRX. TRY. TRSL 0
0
0
0
0
1
1
1
1
0
1
2
3
0
1
2
3
0 0
0 0
0 '0
0 q
0 1
0 1
0 1
0 1
2
2
3
3
3
3
2
3
1
2
3
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
2
1
1
1
2
2
2
2
3
3
3
3
0
1
0
2
3
B
C
0
1
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
. 1
1
0
1
1
0
0
0
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
0 0
0 0
1 0
1 0
0 0
.0-" 0
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
1
1
1
0
1
1
1
0
0
1
0
1
0
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
1
1
1
2
3
A
1
1
0
0
1
1
1
0
1
C
1
0
1
1
1
1
1
1
B
0
0
0
0
2
3
2
3
1
A
0
0
0
0
1
1
1
1
function
4
2
0
0
0
0
0
0
0
0
SELF
(SEL.)
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
BINF
(BIN.)
buffer
BFR
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
programme
select + ON
analogue base
reg. (LlN3) + 1
reg. (LlN2) + 1
reg. (LI N 1) + 1
OFF
reg. (LlN3) - 1
reg. (LlN2) - 1
reg. (LlN1) - 1
1
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0
programme
select + ON
1
0
1
1
1
0
0
0
0
0
0
0
0
mute (set/reset)
spare functions
Note
Reset mute also on programme select codes, (LI N 1), ± 1, and analogue base.
January 1979
7
l____
SAF1032P
SAF1039P
OPERATING OUTPUT CODE
(SEL.)
(BIN.)
"-
0
1
2
3
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
X
X
X
0
X
X
1
1
1
1
X
X
X
0
0
0,
1
1
X
X
'stand-by' OF F
via remote
0
ON - 'not hold' condition
non-operating
ON - 'hold' condition
non-operati ng
TV(l)T
A
C
C
B
(L.(l)T)
B
0
A
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
8
-0,5 to 11 V
Supply voltage
VOO-VSS
Input voltage
VI
max.
11 V
Current into any terminal
±II
max.
10 mA
Power dissipation (per output)
Po
max.
50 mW
Power dissipation (per package)
Ptot
max.
200 mW'
Operating ambient temperature
Tamb
Storage temperature
Tstg
January 1979
(
-40 to +85 °C
-65 to +150 0C
SAF1032p·
SAF1039P
Remote control system for infrared operation
CHARACTERISTICS
T amb = 0 to +85 °C (unless otherwise specified)
SAF1039P only
Recommended supply voltage
symbol
min.
VOO
7
VOO
V
Tamb
typo
max.
-
10
V
-
10
50
J.1.A
J.1.A
10
7
25
65
-
1,7
0,8
-
mA
mA.
10
10
all
25
7 to 10
7.to 10
10
all
all
25
7
all
7
all
°C
Supply current
quiescent
100
-
operating; TRQ)1 at VSS;
outputs unloaded;
one keyboard switch
closed
100
-
Inputs (note 1 )
TRQ)2; TINH (note 2)
input voltage HIGH
input voltage LOW
input current
VIH
VIL
II
0, 8V OO 0
10- 5
-
Outputs
TROT; TR0S; TRQ)1
output current HI G H
at VOH = VOO -0,5 V
1
V
VOO
0, 2V OO V
.1
J.1.A
-IOH
0,4
-
-
mA
output current LOW
at VOL = 0,4 V
IOL
0,4
-
-
mA
TROT output leakage
current.when disabled
Vo = VSS to VOO
IOL
-
--
1
p.A
10
25
IOL
0,4
--
-
mA
7
all
0,15f nom
mA
2,5
. rnA
-
7 to 10
10
10
all
all
TINH
output current LOW
VOL = 0,4 V
Oscillator
frequency variation with
supply voltage, temperature
and spread of I C properties
f nom = 36 kHz (note 3)
oscillator current drain
M
lose
-
-
-
-
-
1,3
I
For notes see page 11.
January 1979
25
SAF1032P
SAF1039P
L
'---------------------------------------------------
CHARACTERISTICS
T amb = 0 to +85 °C (unless otherwise specified)
SAF1032P only
Vob
V
Tamb
.oC
min.
typo
max.
VOO
8
-
10
V
quiescent
100
-
1
50
300
IlA
IlA
10
10
25
85
operating; 10 = 0; at
0SCI frequency of 100 kHz
100
-
-
1
rnA
10
all
VIH
VIL
0, 7V OO
0
-
V
VOO
0, 2V OD V
8 to 10
8 to 10
all
all
Vti
Vtd
O,4Voo
0, 1V OO
-
0, 9V OO V
0, 6V OO V
5 to 10
5 to 10
all
all
input current; all inputs
except TV0T
II
-
10-5
1
IlA
10
25
input signal rise and fall
times (10% and 90% VOO)
all inputs except MAIN
t r , tf
-
-
5
IlS
8 to 10
all
Outputs
programme selection:
BINA/B/C/O
auxiliary:
SELA/B/C/O
analogue:
L30T; L20T; L10T.
TV0T (note 4)
all open drain n-channel
output current LOW
at VOL = 0,4 V
IOL
1,6
-
-
rnA
8
all
output leakage current
at Va =VSS to VOO
IOL
-
-
10
IlA
10
all
symbol
Recommended supply voltage
Supply current
Inputs
DATA; 0SCI; H0LO;
TV0T (see note 4)
input voltage HIGH,
input voltage LOW
MAIN; tripping levels
input voltage increasing
input voltage decreasing
For note 4 see page 11.
10
January 1979
Remote control system for infrared operation
SAF1032P
SAF1039P
Notes (to pages 9 and 10)
1. The keyboard inputs (TRX.; TRY.; TRSL) are not voltage driven (see application information
diagram Fig. 6).
If one key is depressed, the circuit generates the corresponding code. The number of keys
depressed at a time, and this being recognized by the circuit as an illegal operation, depends on the
supply voltage (VOO) and the leakag~ current (between device and printed-circuit board) externally
applied to the keyboard inputs.
If no leakage is assumed, the circuit recognizes an operation as illegal for any number of keys> 1
depressed at the same time with VOO = 7 V. At a leakage due to a 1 Mn resistor connected to each
keyboard input and returned to either VDO or VSS, the circuit recognizes at least 2 keys depressed
at a time with VOO = 7V.
The highest permissible values of the contact series resistance of the keyboard switches is 500 n.
2. Inhibit output transistor disabled.,
3. Af is the width of the distribution curve at 20 points (0 = standard deviation).
4. Terminal TVQ)T is input for manual 'ON'. When applying a LOW level TVQ)T becomes an output
carrying a LOW level.
January 1979
11
l~_ _
SAF1032P
SAF1039P
APPLICATION INFORMATION
VDD----~
+
+
9V
C1
150pF
SAF1039P
·(2%)
'--y---J
I
~
R2100kU
~
I
s: saturation
B: brightness
V:volume
-J Z74 353.2
Fig. 6 Interconnection diagram of transmitter circuit SAF1039P in a remote
control system, for a television. receiver with 12 programmes.
12
January 1979
(
:JJ
1 nF
10kD.
+12V~1---,
CD
. - - - - - - - - . - - - - - VDD
(+9
V)
PULSE
STRETCHER
(2x 1/4HEF4011B)
3
o
S-
a
:::l
f'+
2~
BPW34
OSCillATOR
(2x 1/4HEF4011B)
j 1/4HEF4011B
I I I
VSS
+12V
S
3
Q
~
III
Cil
c..
o
i
POWER ON
RESET
ii1
f'+
c)'
:::l
BZX79
-C7V5
811
1
k
~gll
811
1
k
k~~
BAW62
100kn
~+12V
"""- Dl lO
VSS--~----~--+--~~~
9 VSS
8 TVQ)T
DATA 11
5J~~~
150 pF
(2%)
~~~~
[3J~6]~
c....
III
:::l
c::
III
~
co
CO
'"
n.c.
MAIN
12
Q)SCI
13
{ ::~:::
SE lB
16
BINA
!~I~~~~~amme
6 BINB
SAF
1032P
B"'~
-+_--+______ }
5 U'.!~_ _
l~~
.1
B"·- _ _~_ _ _ _ _ _ _ _ _ __
sWitch les
.
l1Q)T
SELA 17
L2Q)T
V DD 18
L3Q)T
E1G8
ITJITJITJ
for interface
see Fig. 8
(J)(J)
»»
~"'TI
-4 -4
Fig.7 Interconnection diagram showing the SAF1032P and SAF1039P used in a TV control system.
00
c.vc.v
<01\.)
\J\J
w
SAF1032P
SAF1039P
Voo
+12V
volume
(pin 5; TBA750)
Voo
+12V
brightness
(pin 11; TDA2560)
2
Voo
+12V
saturation
(pin 16; TDA2560)
3
Voo
33kn
..--__e-+
to pin ,9 of TDA2581
to pin 4 of TDA2581
7Z743S4.1
Fig. 8 I Additional circuits from outputs L1 Qn (1), L20T (2), L30T (3) and
TV0T (4) of the SAF1032P in circuit of Fig. 7.
:--1....4----J-an-u-a-rY-1-9-7-9-
(
l__
DEVELOPMENT SAMPLE DATA
This information is derived from development samples made available
for evaluation. It does not form part of our data handbook system and
does not necessarily imply that the device will go into production
T_D_B_10_3_3_ _
PREAMPLIFIER FOR ULTRASONIC/INFRARED
REMOTE CONTROL TRANSMISSION
\,4
115
12
t
113
AMPLIFIER
V>-V>-V""
1
inp ut
V
16
SYNCHRONOUS
DEMODU-
V
A.G.C.
AMPLIFIER
TDB1033
LATOR
l4-
OUTPUT
I---+-
STAGE
12
I-+- I -ou- tput
;-+-
COMPARATOR
LIMITER
f-+- ~
- 2-
I
6
ou tput
7Z82232
4
8
9
11
a.g.c. timing
5
comparator
~hreshold
Fig. 1 Block diagram.
Features
•
•
•
•
Three differential amplifier stages; two of which are gain controlled.
The a.g.c. time-constant can be determined externally.
Built-in synchronous demodulator with limiter and a.g.c. amplifier;
Comparator for improving the noise performance, with adjustable threshold.
QUICK REFERENCE DATA
Supply voltage
Vp
typ.
12 V
Voltage gain
Gv
typ.
97 dB
Input sensitivity (r.m.s. value)
Vj(rms)
typ.
110 p.V
Supply current
Ip
typ.
Operating ambient temperature range
Tamb
-20 to +60 °C
38 mA
PACKAGE OUTLINE
l6-lead 01 L; plastic (SOT-38).
'I
June 1979
~
jl________________
__
T_DB_1_0_33_ _
GENERAL DESCRIPTION
The TDB1033 comprises'3 differential amplifier stages, of which the first and second stages are gain
controlled. The output of the third stage is connected to asynchronoLls demodulator and limiter
(reference signal for switching the demodulator). The demodulator is followed by an output stage which
delivers a positive-going and a negative-going output signal. The negative"goingsignal is used to obtain
the a.g.c. signal.
The a.g.c. time-constant can be determined by an external RC circuit. The output stage signal is
externally connected to the input of the comparator, of which the threshold voltage can be adjusted
by choice of an external resistor.
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEC134)
Supply voltage
V p = V 13-3
max.
Input voltage
VI =V16-1
max.
15 V
Vp
Input current
II = 116/1
max.
2 mA
Total power dissipation
Ptot
max.
600 mW
Operating ambient temperature range
Tamb
T stg
Storage temperature range
-20 to +60 °C
-20, to +125 0C
CHARACTERISTICS
Vp
= V13 = +12 V; V3 = 0 (ground); Tamb = 25 0 C; unless otherwise specified
Quiescent current
I p = 113
typo
38 mA
I nput resistance
symmetrical
R16-1
typo
18 kU
typo
9 kU
non-symmetrical
Output resistance of output stage
negative-going output
positive-going output
typo
9 kU
typo
14 kU
Gain control
The control voltage depends on the amplitude, the repetition rate, and the duty factor of the input
signal. The control voltage range is 0 to 5.4 V (see Fig. 2)
Output voltages in the control range at VI = V16-3(rms) ='1 mV
LOW level; measured at pin 12
HIGH level; measured at pin 12
LOW level; measured at pin 11
HIGH level; measured at pin 11
2
Jun.
19791(
V12L
V12H
typo
typo
0,5 V,
typo
typo
l,2 V
5,9 V,
5,5 V'
l___
Preamplifier for ultrasonic/infrared remote control transmission
T_D_B_10_3_3_ _
V12 - 3
(V)
b
2,4
---
2,0
1,6
V
/
1,2
/
/'
/
,....-
I--'
Q
--
./
.-
0,8
0,4
"-
c
0,01
0,1
1
10
40
60
80
100
100
120
V16 - 1
1000 mV
140 dB
Fig. 2 Typical behaviour of the control voltage V 4-3 (curve a) and the demodulated output voltage
V12-3 (HIGH level is curve b; LOW level is curve c) as a function of the r.m.s. input voltageV1S_1
(measured within the pulse-burst, see Fig. 4).
Comparator
Output voltage without drive
VS-3
typo
0,7 V
Output voltage with drive
VS-3
typo
9,2 V
>
>
1,5 V/J.lS
Rate of rise of output voltage
AVS_3/ At
Rate of fall of output voltage
AVS_3/ At
Resistance for threshold adjustment (see Fig. 3)
R5-3
I nternal resistance
RS-3
1,0 V/J.lS
1 to 4,7 k,Q
typo
5 k,Q
VS-3
(V)
,/
/V
/
/
V
V
/
J
I
I
I
1
Fig. 3 Typical dependency of the threshold level of the
comparator on the resistor value between pins 5 and 3
(ground).
I
I
I
3
RS-3 (kill 5
June 1979
3
~l_.__________~___________________
_____
T_DB_1_0_33____
CHARACTERISTICS (continued)
Limiter
D.C. voltage at pins 8 and 9 with respect to ground
Signal at the LC resonant circuit (peak-to-peak value)
at V16-1(rms) = 1 mV; limiter is active
V8-9(p-p)
typo
7,3 V
typo
2,1 V
typo
110 IlV
400 IlV
The TOB1033 used as signal amplifier for infrared transmission (see Fig. 4),
Input voltage at R5-3 = 1 kn
V16-3
<
D.C. level at pins 12 and 11; V16-3 = 0
V12-3
V11-3
typo
typo
1 V
5,4 V
V o-3(p-p)
Gv = 20 log ---'-............""-V16-3(rms)
>
88 dB
97 dB
G = 20 log V 12-3(p-p)
v
V16-3(p-p)
>
Voltage gain with comparator and LC circuit
at R5-3 = 1 kn
typo
Voltage gain without comparator and with LC circuit
Control range at ~ V,12-3 = 2 dB
Noise voltage at pins 11 and 12 (r.m.s. value)
measured with a,large bandwidth; V 16-3 = 0
Vp
typo
78 dB
87 dB
~V16-3,
>
77 dB
V12-3(rms)
Vl1-3(rms)
typo
typo
= +12V
input
SOQ
fres= 3S,7 kHz
7zeOl0S
measuring
signal
Fig. 4 Measuring circuit for infrared transmission; for coil data see Fig. 6.
June
19791 (
100 mV
100 mV
Preamplifier for ultrasonic/infrared remote control transmission
The TDB1033 used as signal amplifier for ultrasonic transmission (see Fig. 5).
Input voltage ar R5-3 = 2,4 kn (r.m.s. value)
D.C. level at pins 12 and 11; V16-3
=0
V16-3(rms)
<
100 JlV
V12-3
typo
typo
1 V
5,4 V
>
100 dB
>
90 dB
AV16-3
>
65 dB
V12-3(rms)
V11-3(rms)
typo
typo
60 mV
60 mV
Vll-3
Voltage gain with comparator and LC circuit
at R5-3
= 2,4 kn
Gv = 20 log
l
TDB1033
V6-3(p-p)
--,-::.....::...!.!~~
V16-1 (rms)
Voltage gain without comparator and with LC circuit
G = 20 log V12-3(p-p)
v
V16-1(p-p)
Control range at A V 12-3 = 1 dB
Noise voltage at pins 11 and 12 (r.m.s. value)
measured with a large bandwidth; V16-1 = 0 V
measuring
signal
Fif. 5 Measuring circuit for ultrasonic transmission; for coil data see Fig. 9.
June 1979
5
}l_________________
___
TD_B_1_03_3_ _
APPLICATION INFORMATION
BPW34
t.70pF
90 PF
1
*)
*)t2%Tol.
Fig. 6 Preamplifier for infrared transmission with passive double-T suppression filter for 95 kHz and
with LC demodulator circuit. Co~1 data: 240 turns, 0,18 cf> enamelled copper wire; R = 3,5 n; L = 1 mHi
frame core and Ferroxcube grade 38 screw core with trimming stud at one end.
Fig. 7 Preamplifier for infrared transmission with a Chebyshev-filter having a resonance frequency of
35,7 kHz.
6
June 1979
(
Preamplifier for ultrasonic/infrared remote control transmission
l_·__T_D_B_10_3_3_ _
Vp = +10 to +15V
Fig. 8 Simplified preamplifier for infrared transmission with a Butterworth-low-pass filter; angular
frequency is 35,7 kHz.
+12V
10
J.lF
tantal
+
Fig. 9 Preamplifier with ultrasonic transmission with symmetrical PXE transducer. Coil data: 390
turns, 0,12 ,Calie 13, No. 51 + 39, BOGOTA D.E. 1., Tel. 600600.
Denmark: MINIWATT A ,
5A, DK-2400K0BENHAVN NV., Tel. (01) 691622.
,Kaivokatu8,SF-00100HELSINKll0, Tel. 17271.
France: R.T.C. LA
MPELEC, 130 Avenue Ledru Rollin, F-75540 PARIS 11, Tel. 355-44-99.
Germany: VALVO, UB BaueJ~:e~.d~~hilips G.m.b.H., Valvo Haus, Burchardstrasse 19, D-2 HAMBURG 1, Tel. (040) 3296-1.
Greece: PHILIPS
a Division, 52, Av. Syngrou, ATHENS, Tel. 915311.
Hong Kong: PHILIPS
I
Div., 15/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, Tel. NT 24 51 21.
India: PEICO ELECTRONICS & E
TD., Band Box House, 254-D, Dr. Annie Besant Rd., Prabhadevi, BOMBAY-25-DD, Tel. 457311-5.
ELEiC)IO~IC;S, Elcoma Division, 'Timah' Building, JI. Jen.. Ghtot Subroto, P.O. Box 220, JAKARTA, Tel. 44 163.
'''''ClinT'',.., . . "
~.,."'''''''''QU, Clonskeagh, DUBLIN 14, Tel. 693355.
Italy: PHILIPS S.p.A., SezioneElc,om;U'l'\lzz!lIV NovElmt)re3, 1-20124 MILANO, Tel. 2-6994.
Japan: NIHON PHI LIPS CORP
Bldg., 26-33 Takanawa 3-chome, Minato-ku, TOKYO (108), Tel. 448-5611.
(IC Products) SIGNE I
0, Tel. (03)230-1521.
Korea: PHILIPS ELECTRONICS
,Elcoma Div., Philips House, 260-199Itaewon-dong, Yongsan-ku, C.P.O. Box 3680, SEOUL, Tel. 794-420<
Malaysia: PHILIPS MALAYSIA SDN...·
Lot 2, Jalan 222, Section 14, Petaling Jaya, P.O.B. 2163, KUALA LUMPUR, Selangor, Tel. 77 4:4 11.
Mexico: ELECTRONICA S.A. de C.V., Varsovia No. 36, MEXICO 6, D.F., Tel. 533-11-80.
Netherlands: PHILIPS NEDERLAND B.V., Afd. Elonco, Boschdijk 525,5600 PD EINDHOVEN, Tel. (040) 79 33 33.
New Zealand: PHILIPS ELECTRICAL IND. LTD., Elcoma Division, 2Wagener Place, St. Lukes, AUCKLAND, Tel. 867119.
Norway: NORSK A/S PHILIPS, Electronica, S0rkedalsveien 6, OSLO 3, Tel. 463890.
Peru: CADESA, Rocca de Vergallo 247, LIMA 17, Tel. 628599.
Philippines: PHILIPS INDUSTRIAL DEV. INC., 2246 Pasong Tamo, P.O. Box 911, Makati Comm. Centre, MAKATI-RIZAL 3116, Tel. 86-89-51 to 59.
Portugal: PHILIPS PORTUGESA S.A.R.L., Av. Eng. Duharte Pacheco 6, LISBOA 1, Tel. 683121.
Singapore: PHILIPS PROJECT DEV. (Singapore) PTE LTD., Elcoma Div., P.O.B. 340, Toa Payoh CPO, Lorong 1, Toa Payoh, SINGAPORE 12, Tel. 538811
South Africa: EDAC (Pty.) Ltd., 3rd Floor Rainer House, Upper Railway Rd. & Ove St., New Doornfontein, JOHANNESBURG 2001, Tel. 614-2362/9.
Spain: COPRESA SA, Balmes 22, BARCELONA 7, Tel. 301 6312.
Sweden: A.B. ELCOMA, Lidingovagen 50, S-115 84 STOCKHOLM 27, Tel. 08/679780.
Switzerland: PHILIPS A.G., Elcoma Dept., Allmendstrasse 140-142, CH-8027 ZURICH, Tel. 01/432211.
Taiwan: PHILIPS TAIWAN LTD., 3rd FI., San Min Building, 57-1, Chung Shan N. Rd, Section 2, P.O. Box 22978, TAIPEI, Tel. 5513101-5.
Thailand: PHILIPS ELECTRICAL CO. OF THAILAND LTD., 283 Silom Road, P.O. Box 961, BANGKOK, Tel. 233-6330-9.
Turkey: TURK PHILIPS TICARET A.S., EMET Department, Inonu Cad. No. 78-80, ISTANBUL, Tel. 43 59 10.
United Kingdom: MULLARD LTD., Mullard'House, Torrington Place, LONDON WC1E 7HD, Tel. 01-5806633.
United States: (Active devices & Materials) AMPEREX SALES CORP., Providence Pike, SLATERSVILLE, R.1. 02876, Tel. (401) 762-9000.
(Passive devices) MEPCO/ELECTRA ING., Columbia Rd., MORRISTOWN, N.J. 07960, Tel. (201) 539-2000.
(IC Products) SIGNETICS CORPORATION, 811 East Arques Avenue, SUNNYVALE, California 94086, Tel. (408) 739-7700.
Uruguay: LUZILECTRON SA, Rondeau 1567, pi so 5, MONTEVIDEO, Tel. 94321.
Venezuela: IND. VENEZOLANAS PHILIPS S.A., Elcoma Dept., A. Ppal de los Ruices, Edif. Centro Colgate, CARACAS, Tel. 360511.
A13
, 1979 N.V. Philips' Gloeilampenfabrieken
This information is furnished for guidance, and with no guarantees as to its accuracy or completeness; its publication conveys no licence under any patent or other right, nor doe
the publisher assume liability for any consequence of its use; specifications and availability of goods mentioned in it are subject to change without notice; it is not to be reproduce
in anyway, in whole or in part. without the written consent of the publisher
Printed in The Netherlands
9398 105 40011
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